Repository: Ralim/IronOS Branch: dev Commit: a79791fb9a5c Files: 1038 Total size: 25.3 MB Directory structure: gitextract_r8x0x9vd/ ├── .flake8 ├── .gitattributes ├── .github/ │ ├── FUNDING.yml │ ├── ISSUE_TEMPLATE/ │ │ ├── bug_report.md │ │ ├── everything-else--questions--notes-etc-.md │ │ └── feature_request.md │ ├── dependabot.yml │ ├── pull_request_template.md │ ├── security.md │ └── workflows/ │ ├── docs.yml │ └── push.yml ├── .gitignore ├── .gitmodules ├── Development Resources/ │ ├── TS100/ │ │ ├── KiCad/ │ │ │ ├── MCU_SubBoard.sch │ │ │ ├── TS100.pro │ │ │ └── TS100.sch │ │ └── TS100.ioc │ └── TS80/ │ ├── TS80-Bootloader.hex │ └── TS80.ioc ├── Documentation/ │ ├── Bluetooth.md │ ├── DebugMenu.md │ ├── DebuggingPD.md │ ├── Development.md │ ├── Flashing/ │ │ ├── MHP30.md │ │ ├── Pinecil V1.md │ │ ├── Pinecil V2.md │ │ ├── TS100.md │ │ └── TS80(P).md │ ├── GettingStarted.md │ ├── HallSensor.md │ ├── Hardware.md │ ├── HardwareIssues.md │ ├── History.md │ ├── Logo.md │ ├── Menu.md │ ├── PortingToNewDevice.md │ ├── Power.md │ ├── PowerSources.md │ ├── README.md │ ├── Settings.md │ ├── Temperature.md │ ├── Translation.md │ ├── Troubleshooting.md │ ├── WS2812BModding.md │ └── index.md ├── Env.yml ├── LICENSE ├── Makefile ├── README.md ├── Translations/ │ ├── BitmapEditor.html │ ├── README.md │ ├── brieflz.py │ ├── brieflz_test.py │ ├── font_tables.py │ ├── gen_menu_docs.py │ ├── make_translation.py │ ├── make_translation_test.py │ ├── migrate.py │ ├── objcopy.py │ ├── translation_BE.json │ ├── translation_BG.json │ ├── translation_CS.json │ ├── translation_DA.json │ ├── translation_DE.json │ ├── translation_EL.json │ ├── translation_EN.json │ ├── translation_ES.json │ ├── translation_ET.json │ ├── translation_FI.json │ ├── translation_FR.json │ ├── translation_HR.json │ ├── translation_HU.json │ ├── translation_IT.json │ ├── translation_JA_JP.json │ ├── translation_LT.json │ ├── translation_NB.json │ ├── translation_NL.json │ ├── translation_NL_BE.json │ ├── translation_PL.json │ ├── translation_PT.json │ ├── translation_RO.json │ ├── translation_RU.json │ ├── translation_SK.json │ ├── translation_SL.json │ ├── translation_SR_CYRL.json │ ├── translation_SR_LATN.json │ ├── translation_SV.json │ ├── translation_TR.json │ ├── translation_UK.json │ ├── translation_UZ.json │ ├── translation_VI.json │ ├── translation_YUE_HK.json │ ├── translation_ZH_CN.json │ ├── translation_ZH_TW.json │ ├── translations_definitions.json │ └── wqy-bitmapsong/ │ ├── AUTHORS │ ├── COPYING │ ├── README.md │ ├── README_original │ └── wenquanyi_9pt.bdf ├── scripts/ │ ├── IronOS-mkdocs.yml │ ├── IronOS.Dockerfile │ ├── LICENSE_RELEASE.md │ ├── deploy.sh │ └── flash_ts10X_linux.sh └── source/ ├── .clang-format ├── Core/ │ ├── BSP/ │ │ ├── BSP.h │ │ ├── BSP_Common.c │ │ ├── BSP_Flash.h │ │ ├── BSP_PD.h │ │ ├── BSP_Power.h │ │ ├── BSP_QC.h │ │ ├── Defines.h │ │ ├── MHP30/ │ │ │ ├── BSP.cpp │ │ │ ├── FreeRTOSConfig.h │ │ │ ├── IRQ.cpp │ │ │ ├── IRQ.h │ │ │ ├── Pins.h │ │ │ ├── Power.cpp │ │ │ ├── QC_GPIO.cpp │ │ │ ├── README.md │ │ │ ├── Setup.c │ │ │ ├── Setup.h │ │ │ ├── Software_I2C.h │ │ │ ├── Startup/ │ │ │ │ └── startup_stm32f103t8ux.S │ │ │ ├── ThermoModel.cpp │ │ │ ├── Vendor/ │ │ │ │ ├── CMSIS/ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ └── STM32F1xx/ │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ ├── stm32f103xb.h │ │ │ │ │ │ ├── stm32f1xx.h │ │ │ │ │ │ └── system_stm32f1xx.h │ │ │ │ │ └── Include/ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ └── tz_context.h │ │ │ │ └── STM32F1xx_HAL_Driver/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ ├── stm32f1xx_hal.h │ │ │ │ │ ├── stm32f1xx_hal_adc.h │ │ │ │ │ ├── stm32f1xx_hal_adc_ex.h │ │ │ │ │ ├── stm32f1xx_hal_cortex.h │ │ │ │ │ ├── stm32f1xx_hal_def.h │ │ │ │ │ ├── stm32f1xx_hal_dma.h │ │ │ │ │ ├── stm32f1xx_hal_dma_ex.h │ │ │ │ │ ├── stm32f1xx_hal_exti.h │ │ │ │ │ ├── stm32f1xx_hal_flash.h │ │ │ │ │ ├── stm32f1xx_hal_flash_ex.h │ │ │ │ │ ├── stm32f1xx_hal_gpio.h │ │ │ │ │ ├── stm32f1xx_hal_gpio_ex.h │ │ │ │ │ ├── stm32f1xx_hal_iwdg.h │ │ │ │ │ ├── stm32f1xx_hal_pwr.h │ │ │ │ │ ├── stm32f1xx_hal_rcc.h │ │ │ │ │ ├── stm32f1xx_hal_rcc_ex.h │ │ │ │ │ ├── stm32f1xx_hal_tim.h │ │ │ │ │ └── stm32f1xx_hal_tim_ex.h │ │ │ │ └── Src/ │ │ │ │ ├── stm32f1xx_hal.c │ │ │ │ ├── stm32f1xx_hal_adc.c │ │ │ │ ├── stm32f1xx_hal_adc_ex.c │ │ │ │ ├── stm32f1xx_hal_cortex.c │ │ │ │ ├── stm32f1xx_hal_dma.c │ │ │ │ ├── stm32f1xx_hal_exti.c │ │ │ │ ├── stm32f1xx_hal_flash.c │ │ │ │ ├── stm32f1xx_hal_flash_ex.c │ │ │ │ ├── stm32f1xx_hal_gpio.c │ │ │ │ ├── stm32f1xx_hal_gpio_ex.c │ │ │ │ ├── stm32f1xx_hal_iwdg.c │ │ │ │ ├── stm32f1xx_hal_pwr.c │ │ │ │ ├── stm32f1xx_hal_rcc.c │ │ │ │ ├── stm32f1xx_hal_rcc_ex.c │ │ │ │ ├── stm32f1xx_hal_tim.c │ │ │ │ └── stm32f1xx_hal_tim_ex.c │ │ │ ├── configuration.h │ │ │ ├── flash.c │ │ │ ├── fusb_user.cpp │ │ │ ├── port.c │ │ │ ├── portmacro.h │ │ │ ├── postRTOS.cpp │ │ │ ├── preRTOS.cpp │ │ │ ├── stm32f103.ld │ │ │ ├── stm32f1xx_hal_msp.c │ │ │ ├── stm32f1xx_hal_timebase_TIM.c │ │ │ ├── stm32f1xx_it.c │ │ │ └── system_stm32f1xx.c │ │ ├── Miniware/ │ │ │ ├── BSP.cpp │ │ │ ├── FreeRTOSConfig.h │ │ │ ├── IRQ.cpp │ │ │ ├── IRQ.h │ │ │ ├── Pins.h │ │ │ ├── Power.cpp │ │ │ ├── QC_GPIO.cpp │ │ │ ├── README.md │ │ │ ├── Setup.cpp │ │ │ ├── Setup.h │ │ │ ├── Software_I2C.h │ │ │ ├── Startup/ │ │ │ │ └── startup_stm32f103t8ux.S │ │ │ ├── ThermoModel.cpp │ │ │ ├── Vendor/ │ │ │ │ ├── CMSIS/ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ └── STM32F1xx/ │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ ├── stm32f103xb.h │ │ │ │ │ │ ├── stm32f1xx.h │ │ │ │ │ │ └── system_stm32f1xx.h │ │ │ │ │ └── Include/ │ │ │ │ │ ├── arm_common_tables.h │ │ │ │ │ ├── arm_const_structs.h │ │ │ │ │ ├── arm_math.h │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ ├── cmsis_armcc_V6.h │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ ├── core_cmFunc.h │ │ │ │ │ ├── core_cmInstr.h │ │ │ │ │ ├── core_cmSimd.h │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ └── core_sc300.h │ │ │ │ └── STM32F1xx_HAL_Driver/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ ├── stm32f1xx_hal.h │ │ │ │ │ ├── stm32f1xx_hal_adc.h │ │ │ │ │ ├── stm32f1xx_hal_adc_ex.h │ │ │ │ │ ├── stm32f1xx_hal_cortex.h │ │ │ │ │ ├── stm32f1xx_hal_def.h │ │ │ │ │ ├── stm32f1xx_hal_dma.h │ │ │ │ │ ├── stm32f1xx_hal_dma_ex.h │ │ │ │ │ ├── stm32f1xx_hal_flash.h │ │ │ │ │ ├── stm32f1xx_hal_flash_ex.h │ │ │ │ │ ├── stm32f1xx_hal_gpio.h │ │ │ │ │ ├── stm32f1xx_hal_gpio_ex.h │ │ │ │ │ ├── stm32f1xx_hal_i2c.h │ │ │ │ │ ├── stm32f1xx_hal_iwdg.h │ │ │ │ │ ├── stm32f1xx_hal_pwr.h │ │ │ │ │ ├── stm32f1xx_hal_rcc.h │ │ │ │ │ ├── stm32f1xx_hal_rcc_ex.h │ │ │ │ │ ├── stm32f1xx_hal_tim.h │ │ │ │ │ └── stm32f1xx_hal_tim_ex.h │ │ │ │ └── Src/ │ │ │ │ ├── stm32f1xx_hal.c │ │ │ │ ├── stm32f1xx_hal_adc.c │ │ │ │ ├── stm32f1xx_hal_adc_ex.c │ │ │ │ ├── stm32f1xx_hal_cortex.c │ │ │ │ ├── stm32f1xx_hal_dma.c │ │ │ │ ├── stm32f1xx_hal_flash.c │ │ │ │ ├── stm32f1xx_hal_flash_ex.c │ │ │ │ ├── stm32f1xx_hal_gpio.c │ │ │ │ ├── stm32f1xx_hal_gpio_ex.c │ │ │ │ ├── stm32f1xx_hal_iwdg.c │ │ │ │ ├── stm32f1xx_hal_pwr.c │ │ │ │ ├── stm32f1xx_hal_rcc.c │ │ │ │ ├── stm32f1xx_hal_rcc_ex.c │ │ │ │ ├── stm32f1xx_hal_tim.c │ │ │ │ └── stm32f1xx_hal_tim_ex.c │ │ │ ├── configuration.h │ │ │ ├── flash.c │ │ │ ├── fusb_user.cpp │ │ │ ├── port.c │ │ │ ├── portmacro.h │ │ │ ├── postRTOS.cpp │ │ │ ├── preRTOS.cpp │ │ │ ├── stm32f103.ld │ │ │ ├── stm32f1xx_hal_msp.c │ │ │ ├── stm32f1xx_hal_timebase_TIM.c │ │ │ ├── stm32f1xx_it.c │ │ │ └── system_stm32f1xx.c │ │ ├── Pinecil/ │ │ │ ├── BSP.cpp │ │ │ ├── Debug.cpp │ │ │ ├── Debug.h │ │ │ ├── FreeRTOSConfig.h │ │ │ ├── I2C_Wrapper.cpp │ │ │ ├── IRQ.cpp │ │ │ ├── IRQ.h │ │ │ ├── NOTES.md │ │ │ ├── Pins.h │ │ │ ├── Power.cpp │ │ │ ├── QC_GPIO.cpp │ │ │ ├── README.md │ │ │ ├── Setup.cpp │ │ │ ├── Setup.h │ │ │ ├── ThermoModel.cpp │ │ │ ├── UnitSettings.h │ │ │ ├── Vendor/ │ │ │ │ ├── NMSIS/ │ │ │ │ │ └── Core/ │ │ │ │ │ └── Include/ │ │ │ │ │ ├── core_compatiable.h │ │ │ │ │ ├── core_feature_base.h │ │ │ │ │ ├── core_feature_cache.h │ │ │ │ │ ├── core_feature_dsp.h │ │ │ │ │ ├── core_feature_eclic.h │ │ │ │ │ ├── core_feature_fpu.h │ │ │ │ │ ├── core_feature_pmp.h │ │ │ │ │ ├── core_feature_timer.h │ │ │ │ │ ├── nmsis_compiler.h │ │ │ │ │ ├── nmsis_core.h │ │ │ │ │ ├── nmsis_gcc.h │ │ │ │ │ ├── nmsis_version.h │ │ │ │ │ ├── riscv_bits.h │ │ │ │ │ └── riscv_encoding.h │ │ │ │ ├── OS/ │ │ │ │ │ └── FreeRTOS/ │ │ │ │ │ └── Source/ │ │ │ │ │ └── portable/ │ │ │ │ │ └── GCC/ │ │ │ │ │ ├── port.c │ │ │ │ │ ├── portasm.S │ │ │ │ │ └── portmacro.h │ │ │ │ └── SoC/ │ │ │ │ └── gd32vf103/ │ │ │ │ ├── Board/ │ │ │ │ │ └── pinecil/ │ │ │ │ │ ├── Source/ │ │ │ │ │ │ └── GCC/ │ │ │ │ │ │ └── gcc_gd32vf103_flashxip.ld │ │ │ │ │ └── openocd_gd32vf103.cfg │ │ │ │ └── Common/ │ │ │ │ ├── Include/ │ │ │ │ │ ├── Usb/ │ │ │ │ │ │ ├── drv_usb_core.h │ │ │ │ │ │ ├── drv_usb_dev.h │ │ │ │ │ │ ├── drv_usb_host.h │ │ │ │ │ │ ├── drv_usb_hw.h │ │ │ │ │ │ ├── drv_usb_regs.h │ │ │ │ │ │ ├── drv_usbd_int.h │ │ │ │ │ │ ├── drv_usbh_int.h │ │ │ │ │ │ ├── usb_ch9_std.h │ │ │ │ │ │ ├── usb_conf.h │ │ │ │ │ │ ├── usbd_conf.h │ │ │ │ │ │ ├── usbd_core.h │ │ │ │ │ │ ├── usbd_enum.h │ │ │ │ │ │ ├── usbd_transc.h │ │ │ │ │ │ ├── usbh_conf.h │ │ │ │ │ │ ├── usbh_core.h │ │ │ │ │ │ ├── usbh_enum.h │ │ │ │ │ │ ├── usbh_pipe.h │ │ │ │ │ │ └── usbh_transc.h │ │ │ │ │ ├── gd32vf103.h │ │ │ │ │ ├── gd32vf103_adc.h │ │ │ │ │ ├── gd32vf103_bkp.h │ │ │ │ │ ├── gd32vf103_crc.h │ │ │ │ │ ├── gd32vf103_dac.h │ │ │ │ │ ├── gd32vf103_dbg.h │ │ │ │ │ ├── gd32vf103_dma.h │ │ │ │ │ ├── gd32vf103_eclic.h │ │ │ │ │ ├── gd32vf103_exmc.h │ │ │ │ │ ├── gd32vf103_exti.h │ │ │ │ │ ├── gd32vf103_fmc.h │ │ │ │ │ ├── gd32vf103_fwdgt.h │ │ │ │ │ ├── gd32vf103_gpio.h │ │ │ │ │ ├── gd32vf103_i2c.h │ │ │ │ │ ├── gd32vf103_libopt.h │ │ │ │ │ ├── gd32vf103_pmu.h │ │ │ │ │ ├── gd32vf103_rcu.h │ │ │ │ │ ├── gd32vf103_rtc.h │ │ │ │ │ ├── gd32vf103_spi.h │ │ │ │ │ ├── gd32vf103_timer.h │ │ │ │ │ ├── gd32vf103_usart.h │ │ │ │ │ ├── gd32vf103_wwdgt.h │ │ │ │ │ ├── n200_func.h │ │ │ │ │ ├── nuclei_sdk_soc.h │ │ │ │ │ └── system_gd32vf103.h │ │ │ │ └── Source/ │ │ │ │ ├── Drivers/ │ │ │ │ │ ├── Usb/ │ │ │ │ │ │ ├── drv_usb_core.c │ │ │ │ │ │ ├── drv_usb_dev.c │ │ │ │ │ │ ├── drv_usb_host.c │ │ │ │ │ │ ├── drv_usbd_int.c │ │ │ │ │ │ ├── drv_usbh_int.c │ │ │ │ │ │ ├── gd32vf103_usb_hw.c │ │ │ │ │ │ ├── usbd_core.c │ │ │ │ │ │ ├── usbd_enum.c │ │ │ │ │ │ ├── usbd_transc.c │ │ │ │ │ │ ├── usbh_core.c │ │ │ │ │ │ ├── usbh_enum.c │ │ │ │ │ │ ├── usbh_pipe.c │ │ │ │ │ │ └── usbh_transc.c │ │ │ │ │ ├── gd32vf103_adc.c │ │ │ │ │ ├── gd32vf103_bkp.c │ │ │ │ │ ├── gd32vf103_crc.c │ │ │ │ │ ├── gd32vf103_dac.c │ │ │ │ │ ├── gd32vf103_dbg.c │ │ │ │ │ ├── gd32vf103_dma.c │ │ │ │ │ ├── gd32vf103_eclic.c │ │ │ │ │ ├── gd32vf103_exmc.c │ │ │ │ │ ├── gd32vf103_exti.c │ │ │ │ │ ├── gd32vf103_fmc.c │ │ │ │ │ ├── gd32vf103_fwdgt.c │ │ │ │ │ ├── gd32vf103_gpio.c │ │ │ │ │ ├── gd32vf103_i2c.c │ │ │ │ │ ├── gd32vf103_pmu.c │ │ │ │ │ ├── gd32vf103_rcu.c │ │ │ │ │ ├── gd32vf103_rtc.c │ │ │ │ │ ├── gd32vf103_spi.c │ │ │ │ │ ├── gd32vf103_timer.c │ │ │ │ │ ├── gd32vf103_usart.c │ │ │ │ │ ├── gd32vf103_wwdgt.c │ │ │ │ │ └── n200_func.c │ │ │ │ ├── GCC/ │ │ │ │ │ ├── intexc_gd32vf103.S │ │ │ │ │ └── startup_gd32vf103.S │ │ │ │ ├── Stubs/ │ │ │ │ │ ├── close.c │ │ │ │ │ ├── fstat.c │ │ │ │ │ ├── gettimeofday.c │ │ │ │ │ ├── isatty.c │ │ │ │ │ ├── lseek.c │ │ │ │ │ ├── read.c │ │ │ │ │ ├── sbrk.c │ │ │ │ │ └── stub.h │ │ │ │ ├── gd32vf103_soc.c │ │ │ │ └── system_gd32vf103.c │ │ │ ├── configuration.h │ │ │ ├── flash.c │ │ │ ├── fusb_user.cpp │ │ │ ├── postRTOS.cpp │ │ │ └── preRTOS.cpp │ │ ├── Pinecilv2/ │ │ │ ├── BSP.cpp │ │ │ ├── Debug.cpp │ │ │ ├── Debug.h │ │ │ ├── FreeRTOSConfig.h │ │ │ ├── I2C_Wrapper.cpp │ │ │ ├── IRQ.cpp │ │ │ ├── IRQ.h │ │ │ ├── MemMang/ │ │ │ │ └── heap_5.c │ │ │ ├── NOTES.md │ │ │ ├── Pins.h │ │ │ ├── Power.cpp │ │ │ ├── QC_GPIO.cpp │ │ │ ├── README.md │ │ │ ├── Setup.cpp │ │ │ ├── Setup.h │ │ │ ├── ThermoModel.cpp │ │ │ ├── UnitSettings.h │ │ │ ├── bl702_config.h │ │ │ ├── bl_irq.c │ │ │ ├── bl_irq.h │ │ │ ├── bl_mcu_sdk/ │ │ │ │ ├── LICENSE │ │ │ │ ├── ReleaseNotes │ │ │ │ ├── bsp/ │ │ │ │ │ └── bsp_common/ │ │ │ │ │ └── platform/ │ │ │ │ │ ├── bflb_platform.c │ │ │ │ │ ├── bflb_platform.h │ │ │ │ │ ├── cpp_new.cpp │ │ │ │ │ └── syscalls.c │ │ │ │ ├── common/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── bl_math/ │ │ │ │ │ │ ├── arm_dsp_wrapper.c │ │ │ │ │ │ └── arm_dsp_wrapper.h │ │ │ │ │ ├── device/ │ │ │ │ │ │ ├── drv_device.c │ │ │ │ │ │ └── drv_device.h │ │ │ │ │ ├── list/ │ │ │ │ │ │ └── drv_list.h │ │ │ │ │ ├── misc/ │ │ │ │ │ │ ├── compiler/ │ │ │ │ │ │ │ ├── common.h │ │ │ │ │ │ │ └── gcc.h │ │ │ │ │ │ ├── misc.c │ │ │ │ │ │ └── misc.h │ │ │ │ │ ├── partition/ │ │ │ │ │ │ ├── partition.c │ │ │ │ │ │ └── partition.h │ │ │ │ │ ├── pid/ │ │ │ │ │ │ ├── pid.c │ │ │ │ │ │ └── pid.h │ │ │ │ │ ├── ring_buffer/ │ │ │ │ │ │ ├── ring_buffer.c │ │ │ │ │ │ └── ring_buffer.h │ │ │ │ │ ├── soft_crc/ │ │ │ │ │ │ ├── softcrc.c │ │ │ │ │ │ └── softcrc.h │ │ │ │ │ └── timestamp/ │ │ │ │ │ ├── timestamp.c │ │ │ │ │ └── timestamp.h │ │ │ │ ├── components/ │ │ │ │ │ ├── ble/ │ │ │ │ │ │ ├── ble_stack/ │ │ │ │ │ │ │ ├── bl_hci_wrapper/ │ │ │ │ │ │ │ │ ├── bl_hci_wrapper.c │ │ │ │ │ │ │ │ └── bl_hci_wrapper.h │ │ │ │ │ │ │ ├── common/ │ │ │ │ │ │ │ │ ├── atomic_c.c │ │ │ │ │ │ │ │ ├── buf.c │ │ │ │ │ │ │ │ ├── dec.c │ │ │ │ │ │ │ │ ├── dummy.c │ │ │ │ │ │ │ │ ├── hex.c │ │ │ │ │ │ │ │ ├── include/ │ │ │ │ │ │ │ │ │ ├── atomic.h │ │ │ │ │ │ │ │ │ ├── errno.h │ │ │ │ │ │ │ │ │ ├── misc/ │ │ │ │ │ │ │ │ │ │ ├── __assert.h │ │ │ │ │ │ │ │ │ │ ├── byteorder.h │ │ │ │ │ │ │ │ │ │ ├── dlist.h │ │ │ │ │ │ │ │ │ │ ├── printk.h │ │ │ │ │ │ │ │ │ │ ├── slist.h │ │ │ │ │ │ │ │ │ │ ├── stack.h │ │ │ │ │ │ │ │ │ │ ├── util.h │ │ │ │ │ │ │ │ │ │ └── utils_string.h │ │ │ │ │ │ │ │ │ ├── net/ │ │ │ │ │ │ │ │ │ │ └── buf.h │ │ │ │ │ │ │ │ │ ├── toolchain/ │ │ │ │ │ │ │ │ │ │ ├── common.h │ │ │ │ │ │ │ │ │ │ ├── gcc.h │ │ │ │ │ │ │ │ │ │ └── xcc.h │ │ │ │ │ │ │ │ │ ├── toolchain.h │ │ │ │ │ │ │ │ │ ├── work_q.h │ │ │ │ │ │ │ │ │ └── zephyr/ │ │ │ │ │ │ │ │ │ └── types.h │ │ │ │ │ │ │ │ ├── log.c │ │ │ │ │ │ │ │ ├── log.h │ │ │ │ │ │ │ │ ├── poll.c │ │ │ │ │ │ │ │ ├── rpa.c │ │ │ │ │ │ │ │ ├── rpa.h │ │ │ │ │ │ │ │ ├── tinycrypt/ │ │ │ │ │ │ │ │ │ ├── Kconfig │ │ │ │ │ │ │ │ │ ├── README │ │ │ │ │ │ │ │ │ ├── include/ │ │ │ │ │ │ │ │ │ │ └── tinycrypt/ │ │ │ │ │ │ │ │ │ │ ├── aes.h │ │ │ │ │ │ │ │ │ │ ├── cbc_mode.h │ │ │ │ │ │ │ │ │ │ ├── ccm_mode.h │ │ │ │ │ │ │ │ │ │ ├── cmac_mode.h │ │ │ │ │ │ │ │ │ │ ├── constants.h │ │ │ │ │ │ │ │ │ │ ├── ctr_mode.h │ │ │ │ │ │ │ │ │ │ ├── ctr_prng.h │ │ │ │ │ │ │ │ │ │ ├── ecc.h │ │ │ │ │ │ │ │ │ │ ├── ecc_dh.h │ │ │ │ │ │ │ │ │ │ ├── ecc_dsa.h │ │ │ │ │ │ │ │ │ │ ├── ecc_platform_specific.h │ │ │ │ │ │ │ │ │ │ ├── hmac.h │ │ │ │ │ │ │ │ │ │ ├── hmac_prng.h │ │ │ │ │ │ │ │ │ │ ├── sha256.h │ │ │ │ │ │ │ │ │ │ └── utils.h │ │ │ │ │ │ │ │ │ └── source/ │ │ │ │ │ │ │ │ │ ├── aes_decrypt.c │ │ │ │ │ │ │ │ │ ├── aes_encrypt.c │ │ │ │ │ │ │ │ │ ├── cbc_mode.c │ │ │ │ │ │ │ │ │ ├── ccm_mode.c │ │ │ │ │ │ │ │ │ ├── cmac_mode.c │ │ │ │ │ │ │ │ │ ├── ctr_mode.c │ │ │ │ │ │ │ │ │ ├── ctr_prng.c │ │ │ │ │ │ │ │ │ ├── ecc.c │ │ │ │ │ │ │ │ │ ├── ecc_dh.c │ │ │ │ │ │ │ │ │ ├── ecc_dsa.c │ │ │ │ │ │ │ │ │ ├── ecc_platform_specific.c │ │ │ │ │ │ │ │ │ ├── hmac.c │ │ │ │ │ │ │ │ │ ├── hmac_prng.c │ │ │ │ │ │ │ │ │ ├── sha256.c │ │ │ │ │ │ │ │ │ └── utils.c │ │ │ │ │ │ │ │ ├── utils.c │ │ │ │ │ │ │ │ └── work_q.c │ │ │ │ │ │ │ ├── hci_onchip/ │ │ │ │ │ │ │ │ ├── hci_driver.c │ │ │ │ │ │ │ │ └── hci_internal.h │ │ │ │ │ │ │ ├── host/ │ │ │ │ │ │ │ │ ├── at.c │ │ │ │ │ │ │ │ ├── at.h │ │ │ │ │ │ │ │ ├── att.c │ │ │ │ │ │ │ │ ├── att_internal.h │ │ │ │ │ │ │ │ ├── avdtp_internal.h │ │ │ │ │ │ │ │ ├── conn.c │ │ │ │ │ │ │ │ ├── conn_internal.h │ │ │ │ │ │ │ │ ├── crypto.c │ │ │ │ │ │ │ │ ├── crypto.h │ │ │ │ │ │ │ │ ├── ecc.h │ │ │ │ │ │ │ │ ├── gatt.c │ │ │ │ │ │ │ │ ├── gatt_internal.h │ │ │ │ │ │ │ │ ├── hci_core.c │ │ │ │ │ │ │ │ ├── hci_core.h │ │ │ │ │ │ │ │ ├── hci_ecc.c │ │ │ │ │ │ │ │ ├── hci_ecc.h │ │ │ │ │ │ │ │ ├── hfp_hf.c │ │ │ │ │ │ │ │ ├── hfp_internal.h │ │ │ │ │ │ │ │ ├── iso_internal.h │ │ │ │ │ │ │ │ ├── keys.c │ │ │ │ │ │ │ │ ├── keys.h │ │ │ │ │ │ │ │ ├── keys_br.c │ │ │ │ │ │ │ │ ├── l2cap.c │ │ │ │ │ │ │ │ ├── l2cap_internal.h │ │ │ │ │ │ │ │ ├── monitor.c │ │ │ │ │ │ │ │ ├── monitor.h │ │ │ │ │ │ │ │ ├── multi_adv.c │ │ │ │ │ │ │ │ ├── multi_adv.h │ │ │ │ │ │ │ │ ├── rfcomm_internal.h │ │ │ │ │ │ │ │ ├── sdp.c │ │ │ │ │ │ │ │ ├── sdp_internal.h │ │ │ │ │ │ │ │ ├── settings.c │ │ │ │ │ │ │ │ ├── settings.h │ │ │ │ │ │ │ │ ├── smp.h │ │ │ │ │ │ │ │ ├── smp_null.c │ │ │ │ │ │ │ │ └── uuid.c │ │ │ │ │ │ │ ├── include/ │ │ │ │ │ │ │ │ ├── bluetooth/ │ │ │ │ │ │ │ │ │ ├── a2dp-codec.h │ │ │ │ │ │ │ │ │ ├── a2dp.h │ │ │ │ │ │ │ │ │ ├── addr.h │ │ │ │ │ │ │ │ │ ├── att.h │ │ │ │ │ │ │ │ │ ├── avdtp.h │ │ │ │ │ │ │ │ │ ├── bluetooth.h │ │ │ │ │ │ │ │ │ ├── buf.h │ │ │ │ │ │ │ │ │ ├── conn.h │ │ │ │ │ │ │ │ │ ├── crypto.h │ │ │ │ │ │ │ │ │ ├── gap.h │ │ │ │ │ │ │ │ │ ├── gatt.h │ │ │ │ │ │ │ │ │ ├── hci_err.h │ │ │ │ │ │ │ │ │ ├── hci_host.h │ │ │ │ │ │ │ │ │ ├── hci_raw.h │ │ │ │ │ │ │ │ │ ├── hci_vs.h │ │ │ │ │ │ │ │ │ ├── hfp_hf.h │ │ │ │ │ │ │ │ │ ├── iso.h │ │ │ │ │ │ │ │ │ ├── l2cap.h │ │ │ │ │ │ │ │ │ ├── rfcomm.h │ │ │ │ │ │ │ │ │ ├── sdp.h │ │ │ │ │ │ │ │ │ └── uuid.h │ │ │ │ │ │ │ │ └── drivers/ │ │ │ │ │ │ │ │ └── bluetooth/ │ │ │ │ │ │ │ │ └── hci_driver.h │ │ │ │ │ │ │ ├── port/ │ │ │ │ │ │ │ │ ├── bl_port.c │ │ │ │ │ │ │ │ └── include/ │ │ │ │ │ │ │ │ ├── bl_port.h │ │ │ │ │ │ │ │ ├── ble_config.h │ │ │ │ │ │ │ │ └── zephyr.h │ │ │ │ │ │ │ └── services/ │ │ │ │ │ │ │ ├── bas.c │ │ │ │ │ │ │ ├── bas.h │ │ │ │ │ │ │ ├── dis.c │ │ │ │ │ │ │ ├── dis.h │ │ │ │ │ │ │ ├── hog.c │ │ │ │ │ │ │ ├── hog.h │ │ │ │ │ │ │ ├── oad/ │ │ │ │ │ │ │ │ ├── oad.h │ │ │ │ │ │ │ │ ├── oad_client.h │ │ │ │ │ │ │ │ ├── oad_main.h │ │ │ │ │ │ │ │ └── oad_service.h │ │ │ │ │ │ │ ├── scps.c │ │ │ │ │ │ │ └── scps.h │ │ │ │ │ │ └── blecontroller/ │ │ │ │ │ │ ├── ble_inc/ │ │ │ │ │ │ │ ├── ble_lib_api.h │ │ │ │ │ │ │ └── hci_onchip.h │ │ │ │ │ │ └── lib/ │ │ │ │ │ │ └── README.md │ │ │ │ │ ├── freertos/ │ │ │ │ │ │ └── portable/ │ │ │ │ │ │ ├── gcc/ │ │ │ │ │ │ │ └── risc-v/ │ │ │ │ │ │ │ └── bl702/ │ │ │ │ │ │ │ ├── freertos_risc_v_chip_specific_extensions.h │ │ │ │ │ │ │ ├── port.c │ │ │ │ │ │ │ ├── portASM.S │ │ │ │ │ │ │ └── portmacro.h │ │ │ │ │ │ └── readme.txt │ │ │ │ │ └── nmsis/ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── core/ │ │ │ │ │ └── inc/ │ │ │ │ │ ├── core_compatiable.h │ │ │ │ │ ├── core_feature_base.h │ │ │ │ │ ├── core_feature_cache.h │ │ │ │ │ ├── core_feature_dsp.h │ │ │ │ │ ├── core_feature_eclic.h │ │ │ │ │ ├── core_feature_fpu.h │ │ │ │ │ ├── core_feature_pmp.h │ │ │ │ │ ├── core_feature_timer.h │ │ │ │ │ ├── nmsis_compiler.h │ │ │ │ │ ├── nmsis_core.h │ │ │ │ │ ├── nmsis_gcc.h │ │ │ │ │ ├── nmsis_version.h │ │ │ │ │ ├── riscv_bits.h │ │ │ │ │ └── riscv_encoding.h │ │ │ │ └── drivers/ │ │ │ │ └── bl702_driver/ │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── bl702_flash.ld │ │ │ │ ├── cpu_flags.cmake │ │ │ │ ├── hal_drv/ │ │ │ │ │ ├── default_config/ │ │ │ │ │ │ ├── adc_config.h │ │ │ │ │ │ ├── dac_config.h │ │ │ │ │ │ ├── i2s_config.h │ │ │ │ │ │ └── uart_config.h │ │ │ │ │ ├── inc/ │ │ │ │ │ │ ├── hal_adc.h │ │ │ │ │ │ ├── hal_boot2.h │ │ │ │ │ │ ├── hal_clock.h │ │ │ │ │ │ ├── hal_common.h │ │ │ │ │ │ ├── hal_dma.h │ │ │ │ │ │ ├── hal_flash.h │ │ │ │ │ │ ├── hal_gpio.h │ │ │ │ │ │ ├── hal_i2c.h │ │ │ │ │ │ ├── hal_mtimer.h │ │ │ │ │ │ ├── hal_pm.h │ │ │ │ │ │ ├── hal_pm_util.h │ │ │ │ │ │ ├── hal_rtc.h │ │ │ │ │ │ ├── hal_sec_aes.h │ │ │ │ │ │ ├── hal_sec_dsa.h │ │ │ │ │ │ ├── hal_sec_ecdsa.h │ │ │ │ │ │ ├── hal_sec_hash.h │ │ │ │ │ │ ├── hal_uart.h │ │ │ │ │ │ ├── hal_usb.h │ │ │ │ │ │ └── hal_wdt.h │ │ │ │ │ └── src/ │ │ │ │ │ ├── hal_boot2.c │ │ │ │ │ ├── hal_clock.c │ │ │ │ │ ├── hal_common.c │ │ │ │ │ ├── hal_dma.c │ │ │ │ │ ├── hal_flash.c │ │ │ │ │ ├── hal_gpio.c │ │ │ │ │ ├── hal_i2c.c │ │ │ │ │ ├── hal_mtimer.c │ │ │ │ │ ├── hal_pm.c │ │ │ │ │ ├── hal_pm_util.c │ │ │ │ │ ├── hal_rtc.c │ │ │ │ │ ├── hal_sec_aes.c │ │ │ │ │ ├── hal_sec_dsa.c │ │ │ │ │ ├── hal_sec_ecdsa.c │ │ │ │ │ ├── hal_sec_hash.c │ │ │ │ │ ├── hal_uart.c │ │ │ │ │ ├── hal_usb.c │ │ │ │ │ └── hal_wdt.c │ │ │ │ ├── regs/ │ │ │ │ │ ├── aon_reg.h │ │ │ │ │ ├── bl702.h │ │ │ │ │ ├── bl70x_reg.svc │ │ │ │ │ ├── cam_reg.h │ │ │ │ │ ├── cci_reg.h │ │ │ │ │ ├── cks_reg.h │ │ │ │ │ ├── dma_reg.h │ │ │ │ │ ├── ef_ctrl_reg.h │ │ │ │ │ ├── ef_data_0_reg.h │ │ │ │ │ ├── emac_reg.h │ │ │ │ │ ├── glb_reg.h │ │ │ │ │ ├── gpip_reg.h │ │ │ │ │ ├── hbn_reg.h │ │ │ │ │ ├── i2c_reg.h │ │ │ │ │ ├── i2s_reg.h │ │ │ │ │ ├── ir_reg.h │ │ │ │ │ ├── kys_reg.h │ │ │ │ │ ├── l1c_reg.h │ │ │ │ │ ├── mjpeg_reg.h │ │ │ │ │ ├── pdm_reg.h │ │ │ │ │ ├── pds_reg.h │ │ │ │ │ ├── pwm_reg.h │ │ │ │ │ ├── qdec_reg.h │ │ │ │ │ ├── sec_dbg_reg.h │ │ │ │ │ ├── sec_eng_reg.h │ │ │ │ │ ├── sf_ctrl_reg.h │ │ │ │ │ ├── soc702_reg.svd │ │ │ │ │ ├── spi_reg.h │ │ │ │ │ ├── timer_reg.h │ │ │ │ │ ├── tzc_sec_reg.h │ │ │ │ │ ├── uart_reg.h │ │ │ │ │ └── usb_reg.h │ │ │ │ ├── risc-v/ │ │ │ │ │ └── Core/ │ │ │ │ │ └── Include/ │ │ │ │ │ ├── clic.h │ │ │ │ │ ├── riscv_bits.h │ │ │ │ │ ├── riscv_const.h │ │ │ │ │ └── riscv_encoding.h │ │ │ │ ├── startup/ │ │ │ │ │ ├── GCC/ │ │ │ │ │ │ ├── entry.S │ │ │ │ │ │ └── start_load.c │ │ │ │ │ ├── drv_mmheap.c │ │ │ │ │ ├── drv_mmheap.h │ │ │ │ │ ├── interrupt.c │ │ │ │ │ ├── system_bl702.c │ │ │ │ │ └── system_bl702.h │ │ │ │ └── std_drv/ │ │ │ │ ├── inc/ │ │ │ │ │ ├── bl702_acomp.h │ │ │ │ │ ├── bl702_adc.h │ │ │ │ │ ├── bl702_aon.h │ │ │ │ │ ├── bl702_cam.h │ │ │ │ │ ├── bl702_clock.h │ │ │ │ │ ├── bl702_common.h │ │ │ │ │ ├── bl702_dac.h │ │ │ │ │ ├── bl702_dma.h │ │ │ │ │ ├── bl702_ef_ctrl.h │ │ │ │ │ ├── bl702_emac.h │ │ │ │ │ ├── bl702_glb.h │ │ │ │ │ ├── bl702_gpio.h │ │ │ │ │ ├── bl702_hbn.h │ │ │ │ │ ├── bl702_i2c.h │ │ │ │ │ ├── bl702_i2c_gpio_sim.h │ │ │ │ │ ├── bl702_i2s.h │ │ │ │ │ ├── bl702_ir.h │ │ │ │ │ ├── bl702_kys.h │ │ │ │ │ ├── bl702_l1c.h │ │ │ │ │ ├── bl702_mjpeg.h │ │ │ │ │ ├── bl702_nf_cfg.h │ │ │ │ │ ├── bl702_nflash.h │ │ │ │ │ ├── bl702_pds.h │ │ │ │ │ ├── bl702_psram.h │ │ │ │ │ ├── bl702_pwm.h │ │ │ │ │ ├── bl702_qdec.h │ │ │ │ │ ├── bl702_romdriver.h │ │ │ │ │ ├── bl702_sec_dbg.h │ │ │ │ │ ├── bl702_sec_eng.h │ │ │ │ │ ├── bl702_sf_cfg.h │ │ │ │ │ ├── bl702_sf_cfg_ext.h │ │ │ │ │ ├── bl702_sf_ctrl.h │ │ │ │ │ ├── bl702_sflash.h │ │ │ │ │ ├── bl702_sflash_ext.h │ │ │ │ │ ├── bl702_spi.h │ │ │ │ │ ├── bl702_timer.h │ │ │ │ │ ├── bl702_uart.h │ │ │ │ │ ├── bl702_usb.h │ │ │ │ │ ├── bl702_xip_sflash.h │ │ │ │ │ └── bl702_xip_sflash_ext.h │ │ │ │ └── src/ │ │ │ │ ├── bl702_acomp.c │ │ │ │ ├── bl702_adc.c │ │ │ │ ├── bl702_aon.c │ │ │ │ ├── bl702_cam.c │ │ │ │ ├── bl702_clock.c │ │ │ │ ├── bl702_common.c │ │ │ │ ├── bl702_dac.c │ │ │ │ ├── bl702_dma.c │ │ │ │ ├── bl702_ef_ctrl.c │ │ │ │ ├── bl702_emac.c │ │ │ │ ├── bl702_glb.c │ │ │ │ ├── bl702_hbn.c │ │ │ │ ├── bl702_i2c.c │ │ │ │ ├── bl702_i2c_gpio_sim.c │ │ │ │ ├── bl702_i2s.c │ │ │ │ ├── bl702_ir.c │ │ │ │ ├── bl702_kys.c │ │ │ │ ├── bl702_l1c.c │ │ │ │ ├── bl702_mjpeg.c │ │ │ │ ├── bl702_pds.c │ │ │ │ ├── bl702_psram.c │ │ │ │ ├── bl702_pwm.c │ │ │ │ ├── bl702_qdec.c │ │ │ │ ├── bl702_romapi.c │ │ │ │ ├── bl702_romdriver.c │ │ │ │ ├── bl702_sec_dbg.c │ │ │ │ ├── bl702_sec_eng.c │ │ │ │ ├── bl702_sf_cfg.c │ │ │ │ ├── bl702_sf_cfg_ext.c │ │ │ │ ├── bl702_sf_ctrl.c │ │ │ │ ├── bl702_sflash.c │ │ │ │ ├── bl702_sflash_ext.c │ │ │ │ ├── bl702_spi.c │ │ │ │ ├── bl702_timer.c │ │ │ │ ├── bl702_uart.c │ │ │ │ ├── bl702_usb.c │ │ │ │ ├── bl702_xip_sflash.c │ │ │ │ └── bl702_xip_sflash_ext.c │ │ │ ├── ble.c │ │ │ ├── ble.h │ │ │ ├── ble_characteristics.h │ │ │ ├── ble_handlers.cpp │ │ │ ├── ble_handlers.h │ │ │ ├── ble_peripheral.c │ │ │ ├── ble_peripheral.h │ │ │ ├── board.c │ │ │ ├── clock_config.h │ │ │ ├── configuration.h │ │ │ ├── crc32.h │ │ │ ├── flash.c │ │ │ ├── fusb_user.cpp │ │ │ ├── peripheral_config.h │ │ │ ├── pinmux_config.h │ │ │ ├── postRTOS.cpp │ │ │ └── preRTOS.cpp │ │ └── Sequre/ │ │ ├── BSP.cpp │ │ ├── FreeRTOSConfig.h │ │ ├── IRQ.cpp │ │ ├── IRQ.h │ │ ├── Pins.h │ │ ├── Power.cpp │ │ ├── README.md │ │ ├── Setup.cpp │ │ ├── Setup.h │ │ ├── Software_I2C.h │ │ ├── Startup/ │ │ │ └── startup_stm32f103t8ux.S │ │ ├── ThermoModel.cpp │ │ ├── Vendor/ │ │ │ ├── CMSIS/ │ │ │ │ ├── Device/ │ │ │ │ │ └── ST/ │ │ │ │ │ └── STM32F1xx/ │ │ │ │ │ └── Include/ │ │ │ │ │ ├── stm32f103xb.h │ │ │ │ │ ├── stm32f1xx.h │ │ │ │ │ └── system_stm32f1xx.h │ │ │ │ └── Include/ │ │ │ │ ├── arm_common_tables.h │ │ │ │ ├── arm_const_structs.h │ │ │ │ ├── arm_math.h │ │ │ │ ├── cmsis_armcc.h │ │ │ │ ├── cmsis_armcc_V6.h │ │ │ │ ├── cmsis_gcc.h │ │ │ │ ├── core_cm0.h │ │ │ │ ├── core_cm0plus.h │ │ │ │ ├── core_cm3.h │ │ │ │ ├── core_cm4.h │ │ │ │ ├── core_cm7.h │ │ │ │ ├── core_cmFunc.h │ │ │ │ ├── core_cmInstr.h │ │ │ │ ├── core_cmSimd.h │ │ │ │ ├── core_sc000.h │ │ │ │ └── core_sc300.h │ │ │ └── STM32F1xx_HAL_Driver/ │ │ │ ├── Inc/ │ │ │ │ ├── Legacy/ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ ├── stm32f1xx_hal.h │ │ │ │ ├── stm32f1xx_hal_adc.h │ │ │ │ ├── stm32f1xx_hal_adc_ex.h │ │ │ │ ├── stm32f1xx_hal_cortex.h │ │ │ │ ├── stm32f1xx_hal_def.h │ │ │ │ ├── stm32f1xx_hal_dma.h │ │ │ │ ├── stm32f1xx_hal_dma_ex.h │ │ │ │ ├── stm32f1xx_hal_flash.h │ │ │ │ ├── stm32f1xx_hal_flash_ex.h │ │ │ │ ├── stm32f1xx_hal_gpio.h │ │ │ │ ├── stm32f1xx_hal_gpio_ex.h │ │ │ │ ├── stm32f1xx_hal_i2c.h │ │ │ │ ├── stm32f1xx_hal_iwdg.h │ │ │ │ ├── stm32f1xx_hal_pwr.h │ │ │ │ ├── stm32f1xx_hal_rcc.h │ │ │ │ ├── stm32f1xx_hal_rcc_ex.h │ │ │ │ ├── stm32f1xx_hal_tim.h │ │ │ │ └── stm32f1xx_hal_tim_ex.h │ │ │ └── Src/ │ │ │ ├── stm32f1xx_hal.c │ │ │ ├── stm32f1xx_hal_adc.c │ │ │ ├── stm32f1xx_hal_adc_ex.c │ │ │ ├── stm32f1xx_hal_cortex.c │ │ │ ├── stm32f1xx_hal_dma.c │ │ │ ├── stm32f1xx_hal_flash.c │ │ │ ├── stm32f1xx_hal_flash_ex.c │ │ │ ├── stm32f1xx_hal_gpio.c │ │ │ ├── stm32f1xx_hal_gpio_ex.c │ │ │ ├── stm32f1xx_hal_i2c.c │ │ │ ├── stm32f1xx_hal_iwdg.c │ │ │ ├── stm32f1xx_hal_pwr.c │ │ │ ├── stm32f1xx_hal_rcc.c │ │ │ ├── stm32f1xx_hal_rcc_ex.c │ │ │ ├── stm32f1xx_hal_tim.c │ │ │ └── stm32f1xx_hal_tim_ex.c │ │ ├── configuration.h │ │ ├── flash.c │ │ ├── port.c │ │ ├── portmacro.h │ │ ├── postRTOS.cpp │ │ ├── preRTOS.cpp │ │ ├── stm32f103.ld │ │ ├── stm32f1xx_hal_msp.c │ │ ├── stm32f1xx_hal_timebase_TIM.c │ │ ├── stm32f1xx_it.c │ │ └── system_stm32f1xx.c │ ├── Drivers/ │ │ ├── BMA223.cpp │ │ ├── BMA223.hpp │ │ ├── BMA223_defines.h │ │ ├── BootLogo.cpp │ │ ├── BootLogo.h │ │ ├── Buttons.cpp │ │ ├── Buttons.hpp │ │ ├── FS2711.cpp │ │ ├── FS2711.hpp │ │ ├── FS2711_defines.h │ │ ├── Font.h │ │ ├── HUB238.cpp │ │ ├── HUB238.hpp │ │ ├── I2CBB1.cpp │ │ ├── I2CBB1.hpp │ │ ├── I2CBB2.cpp │ │ ├── I2CBB2.hpp │ │ ├── I2C_Wrapper.hpp │ │ ├── LIS2DH12.cpp │ │ ├── LIS2DH12.hpp │ │ ├── LIS2DH12_defines.hpp │ │ ├── MMA8652FC.cpp │ │ ├── MMA8652FC.hpp │ │ ├── MMA8652FC_defines.h │ │ ├── MSA301.cpp │ │ ├── MSA301.h │ │ ├── MSA301_defines.h │ │ ├── OLED.cpp │ │ ├── OLED.hpp │ │ ├── README.md │ │ ├── SC7A20.cpp │ │ ├── SC7A20.hpp │ │ ├── SC7A20_defines.h │ │ ├── Si7210.cpp │ │ ├── Si7210.h │ │ ├── Si7210_defines.h │ │ ├── TipThermoModel.cpp │ │ ├── TipThermoModel.h │ │ ├── USBPD.cpp │ │ ├── USBPD.h │ │ ├── Utils.cpp │ │ ├── Utils.hpp │ │ ├── WS2812.h │ │ ├── WS2812B.h │ │ └── accelerometers_common.h │ ├── Inc/ │ │ ├── FreeRTOSHooks.h │ │ ├── QC3.h │ │ ├── ScrollMessage.hpp │ │ ├── Settings.h │ │ ├── Translation.h │ │ ├── Translation_multi.h │ │ ├── Types.h │ │ ├── expMovingAverage.h │ │ ├── history.hpp │ │ ├── main.hpp │ │ ├── power.hpp │ │ ├── settingsGUI.hpp │ │ ├── stm32f1xx_hal_conf.h │ │ └── stm32f1xx_it.h │ ├── LangSupport/ │ │ ├── lang_multi.cpp │ │ └── lang_single.cpp │ ├── Src/ │ │ ├── FreeRTOSHooks.c │ │ ├── QC3.cpp │ │ ├── ScrollMessage.cpp │ │ ├── Settings.cpp │ │ ├── Translation.cpp │ │ ├── freertos.c │ │ ├── main.cpp │ │ ├── power.cpp │ │ ├── settingsGUI.cpp │ │ └── syscalls.c │ ├── Threads/ │ │ ├── GUIRendering.md │ │ ├── GUIThread.cpp │ │ ├── MOVThread.cpp │ │ ├── PIDThread.cpp │ │ ├── POWThread.cpp │ │ └── UI/ │ │ ├── README.md │ │ ├── drawing/ │ │ │ ├── mono_128x32/ │ │ │ │ ├── draw_cjc_sampling.cpp │ │ │ │ ├── draw_debug_menu.cpp │ │ │ │ ├── draw_homescreen_detailed.cpp │ │ │ │ ├── draw_homescreen_simplified.cpp │ │ │ │ ├── draw_power_source_icon.cpp │ │ │ │ ├── draw_profile_advanced.cpp │ │ │ │ ├── draw_soldering_basic_status.cpp │ │ │ │ ├── draw_soldering_power_status.cpp │ │ │ │ ├── draw_soldering_sleep_mode.cpp │ │ │ │ ├── draw_temperature_change.cpp │ │ │ │ ├── draw_tip_temperature.cpp │ │ │ │ ├── draw_usb_pd_debug.cpp │ │ │ │ ├── draw_warning_undervoltage.cpp │ │ │ │ ├── pre_render_assets.cpp │ │ │ │ ├── printSleepCountdown.cpp │ │ │ │ ├── print_voltage.cpp │ │ │ │ └── show_warning.cpp │ │ │ ├── mono_96x16/ │ │ │ │ ├── draw_cjc_sampling.cpp │ │ │ │ ├── draw_debug_menu.cpp │ │ │ │ ├── draw_homescreen_detailed.cpp │ │ │ │ ├── draw_homescreen_simplified.cpp │ │ │ │ ├── draw_power_source_icon.cpp │ │ │ │ ├── draw_profile_advanced.cpp │ │ │ │ ├── draw_soldering_basic_status.cpp │ │ │ │ ├── draw_soldering_power_status.cpp │ │ │ │ ├── draw_soldering_sleep_mode.cpp │ │ │ │ ├── draw_temperature_change.cpp │ │ │ │ ├── draw_tip_temperature.cpp │ │ │ │ ├── draw_usb_pd_debug.cpp │ │ │ │ ├── draw_warning_undervoltage.cpp │ │ │ │ ├── pre_render_assets.cpp │ │ │ │ ├── printSleepCountdown.cpp │ │ │ │ ├── print_voltage.cpp │ │ │ │ └── show_warning.cpp │ │ │ └── ui_drawing.hpp │ │ └── logic/ │ │ ├── CJC.cpp │ │ ├── DebugMenu.cpp │ │ ├── HomeScreen.cpp │ │ ├── OperatingModes.cpp │ │ ├── OperatingModes.h │ │ ├── SettingsMenu.cpp │ │ ├── ShowStartupWarnings.cpp │ │ ├── Sleep.cpp │ │ ├── Soldering.cpp │ │ ├── SolderingProfile.cpp │ │ ├── TemperatureAdjust.cpp │ │ ├── USBPDDebug_FS2711.cpp │ │ ├── USBPDDebug_FUSB.cpp │ │ ├── USBPDDebug_HUSB238.cpp │ │ └── utils/ │ │ ├── GUIDelay.cpp │ │ ├── OperatingModeUtilities.h │ │ ├── SolderingCommon.cpp │ │ ├── SolderingCommon.h │ │ ├── checkUndervoltage.cpp │ │ ├── getHallEffectSleepTimeout.cpp │ │ ├── getSleepTimeout.cpp │ │ ├── min.cpp │ │ ├── shouldDeviceShutdown.cpp │ │ └── shouldDeviceSleep.cpp │ └── brieflz/ │ ├── README.md │ ├── brieflz.c │ ├── brieflz.h │ ├── brieflz_btparse.h │ ├── brieflz_hashbucket.h │ ├── brieflz_lazy.h │ ├── brieflz_leparse.h │ └── depack.c ├── Makefile ├── Middlewares/ │ └── Third_Party/ │ └── FreeRTOS/ │ └── Source/ │ ├── CMSIS_RTOS/ │ │ ├── cmsis_os.c │ │ └── cmsis_os.h │ ├── croutine.c │ ├── event_groups.c │ ├── include/ │ │ ├── FreeRTOS.h │ │ ├── StackMacros.h │ │ ├── atomic.h │ │ ├── croutine.h │ │ ├── event_groups.h │ │ ├── list.h │ │ ├── message_buffer.h │ │ ├── mpu_prototypes.h │ │ ├── mpu_syscall_numbers.h │ │ ├── mpu_wrappers.h │ │ ├── newlib-freertos.h │ │ ├── picolibc-freertos.h │ │ ├── portable.h │ │ ├── projdefs.h │ │ ├── queue.h │ │ ├── semphr.h │ │ ├── stack_macros.h │ │ ├── stream_buffer.h │ │ ├── task.h │ │ └── timers.h │ ├── list.c │ ├── queue.c │ ├── stream_buffer.c │ ├── tasks.c │ └── timers.c ├── build.sh ├── dfuse-pack.py ├── metadata.py └── version.h ================================================ FILE CONTENTS ================================================ ================================================ FILE: .flake8 ================================================ [flake8] ignore = E203, E266, E501, W503, F403, F401 max-line-length = 200 ================================================ FILE: .gitattributes ================================================ # Ignore all differences in line endings * -crlf ================================================ FILE: .github/FUNDING.yml ================================================ # These are supported funding model platforms ko_fi: ralim custom: https://paypal.me/RalimTek ================================================ FILE: .github/ISSUE_TEMPLATE/bug_report.md ================================================ --- name: Bug report about: Create a report to help us improve title: '' labels: '' assignees: Ralim --- **Describe the bug** **To Reproduce** **Expected behavior** **Details of your device:** - Device: [e.g. TS80/Pinecil etc] - Release: [eg 2.15.40087E6] - Power adapter being used: - If this is an accelerometer related issue, please include its model number here: **Additional context** ================================================ FILE: .github/ISSUE_TEMPLATE/everything-else--questions--notes-etc-.md ================================================ --- name: Everything else (Questions, notes etc) about: For remarking questions or notes title: '' labels: '' assignees: '' --- ================================================ FILE: .github/ISSUE_TEMPLATE/feature_request.md ================================================ --- name: Feature request about: Suggest an idea for this project title: '' labels: enhancement assignees: Ralim --- **Is your feature request related to a problem? Please describe.** **Describe the solution you'd like** **Describe alternatives you've considered** **Additional context** ================================================ FILE: .github/dependabot.yml ================================================ version: 2 updates: - package-ecosystem: "github-actions" directory: "/" schedule: # Check for updates to GitHub Actions every weekday interval: "weekly" open-pull-requests-limit: 10 commit-message: prefix: chore include: scope ================================================ FILE: .github/pull_request_template.md ================================================ * **Please check if the PR fulfills these requirements** - [] The changes have been tested locally - [] There are no breaking changes * **What kind of change does this PR introduce?** * **What is the current behavior?** * **What is the new behavior (if this is a feature change)?** * **Other information**: ================================================ FILE: .github/security.md ================================================ # Security Policy ## Supported Versions Use this section to tell people about which versions of your project are currently being supported with security updates. | Version | Supported | | ------- | ------------------ | | Latest Release | :white_check_mark: | | master | :white_check_mark: | ## Reporting a Vulnerability 1. Report in an issue please and tag @ralim 2. All issues are read within 1 working week in general; often within 24 hours 3. Issue shall recieve a comment within 14 days; but goal is < 2. 4. Issue will be open until the vulnerability is closed in all supported versions ================================================ FILE: .github/workflows/docs.yml ================================================ name: Docs # Controls when the workflow will run on: # Triggers the workflow on push or pull request push: branches: [dev, docs] # Allows you to run this workflow manually from the Actions tab workflow_dispatch: # Allow one concurrent deployment concurrency: group: "pages" cancel-in-progress: true jobs: deploy-docs: # The type of runner that the job will run on runs-on: ubuntu-latest steps: - uses: actions/checkout@v6 with: fetch-depth: 0 - uses: actions/setup-python@v6 with: python-version: '3.12.3' - run: | pip install --upgrade pip && pip install mkdocs mkdocs-gen-files pymdown-extensions \ mkdocs-git-revision-date-plugin mkdocs-autolinks-plugin \ mkdocs-awesome-pages-plugin - run: git config user.name 'github-actions[bot]' && git config user.email 'github-actions[bot]@users.noreply.github.com' - name: Publish docs run: mkdocs gh-deploy -f scripts/IronOS-mkdocs.yml -d ../site ================================================ FILE: .github/workflows/push.yml ================================================ name: CI on: push: pull_request: branches: - master - dev - main jobs: build: runs-on: ubuntu-24.04 container: image: alpine:3.21 strategy: matrix: model: [ "TS100", "TS80", "TS80P", "Pinecil", "MHP30", "Pinecilv2", "S60", "S60P", "T55", "TS101", ] fail-fast: true steps: - name: Install dependencies (apk) run: apk add --no-cache gcc-riscv-none-elf g++-riscv-none-elf gcc-arm-none-eabi g++-arm-none-eabi newlib-riscv-none-elf newlib-arm-none-eabi findutils python3 py3-pip make git bash - name: Install dependencies (python) run: python3 -m pip install --break-system-packages bdflib - uses: actions/checkout@v6 with: submodules: true - name: Git ownership exception run: git config --global --add safe.directory /__w/IronOS/IronOS && git config --global safe.directory "$GITHUB_WORKSPACE" - name: Git meta info run: echo "GITHUB_CI_PR_SHA=${{github.event.pull_request.head.sha}}" >> "${GITHUB_ENV}" - name: Build ${{ matrix.model }} run: cd source && ./build.sh -m ${{ matrix.model }} - name: Copy license files run: cp LICENSE scripts/LICENSE_RELEASE.md source/Hexfile/ - name: Generate json index file run: ./source/metadata.py ${{ matrix.model }}.json - name: Archive ${{ matrix.model }} artifacts uses: actions/upload-artifact@v5 with: name: ${{ matrix.model }} path: | source/Hexfile/${{ matrix.model }}_*.hex source/Hexfile/${{ matrix.model }}_*.dfu source/Hexfile/${{ matrix.model }}_*.bin source/Hexfile/${{ matrix.model }}.json source/Hexfile/LICENSE source/Hexfile/LICENSE_RELEASE.md if-no-files-found: error build_multi-lang: runs-on: ubuntu-24.04 container: image: alpine:3.21 strategy: matrix: model: ["Pinecil", "Pinecilv2"] fail-fast: true steps: - name: Install dependencies (apk) run: apk add --no-cache gcc-riscv-none-elf g++-riscv-none-elf gcc-arm-none-eabi g++-arm-none-eabi newlib-riscv-none-elf newlib-arm-none-eabi findutils python3 py3-pip make git bash musl-dev - name: Install dependencies (python) run: python3 -m pip install --break-system-packages bdflib - uses: actions/checkout@v6 with: submodules: true - name: Git ownership exception run: git config --global --add safe.directory /__w/IronOS/IronOS && git config --global safe.directory "$GITHUB_WORKSPACE" - name: Git meta info run: echo "GITHUB_CI_PR_SHA=${{github.event.pull_request.head.sha}}" >> "${GITHUB_ENV}" - name: Build ${{ matrix.model }} run: make -C source/ -j$(nproc) model="${{ matrix.model }}" firmware-multi_compressed_European firmware-multi_compressed_Belarusian+Bulgarian+Russian+Serbian+Ukrainian firmware-multi_Chinese+Japanese - name: Copy license files run: cp LICENSE scripts/LICENSE_RELEASE.md source/Hexfile/ - name: Generate json index file run: ./source/metadata.py ${{ matrix.model }}_multi-lang.json - name: Archive ${{ matrix.model }} artifacts uses: actions/upload-artifact@v5 with: name: ${{ matrix.model }}_multi-lang path: | source/Hexfile/${{ matrix.model }}_*.hex source/Hexfile/${{ matrix.model }}_*.dfu source/Hexfile/${{ matrix.model }}_*.bin source/Hexfile/${{ matrix.model }}_multi-lang.json source/Hexfile/LICENSE source/Hexfile/LICENSE_RELEASE.md if-no-files-found: error upload_metadata: needs: [build, build_multi-lang] runs-on: ubuntu-24.04 steps: - name: Download all prebuilts uses: actions/download-artifact@v6 with: path: source/Hexfile/ merge-multiple: true - run: ls -R source/Hexfile - name: Upload JSONs in bulk as metadata uses: actions/upload-artifact@v5 with: name: metadata path: source/Hexfile/*.json if-no-files-found: error tests: runs-on: ubuntu-24.04 container: image: alpine:3.21 steps: - name: Install dependencies (apk) run: apk add --no-cache python3 py3-pip make git bash findutils gcc musl-dev - uses: actions/checkout@v6 with: submodules: true - name: Install dependencies (python) run: python3 -m pip install --break-system-packages bdflib - name: Run python tests run: ./Translations/make_translation_test.py - name: Run BriefLZ tests run: make -C source/ Objects/host/brieflz/libbrieflz.so && ./Translations/brieflz_test.py check_c-cpp: runs-on: ubuntu-24.04 container: image: alpine:3.21 steps: - name: Install dependencies (apk) run: apk add --no-cache make git diffutils findutils clang-extra-tools bash - uses: actions/checkout@v6 with: submodules: true - name: Check format style with clang-format run: make clean check-style check-settings-docs: runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v6 - name: Run the menu docs generator run: python Translations/gen_menu_docs.py - name: Check that Documentation/Settings.md didn't change run: git diff --exit-code check_python: runs-on: ubuntu-24.04 container: image: alpine:3.21 steps: - name: Install dependencies (apk) run: apk add --no-cache python3 py3-pip make git black - uses: actions/checkout@v6 with: submodules: true - name: Install dependencies (python) run: python3 -m pip install --break-system-packages bdflib flake8 - name: Check python formatting with black run: black --diff --check Translations - name: Check python with flake8 run: flake8 Translations check_shell: name: check_shell runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v6 - name: shellcheck uses: reviewdog/action-shellcheck@v1 with: github_token: ${{ secrets.github_token }} reporter: github-pr-review # Change reporter. exclude: "./.git/*" # Optional. check_all_files_with_shebangs: "false" # Optional. check_docs: runs-on: ubuntu-24.04 container: image: alpine:3.21 steps: - name: Install dependencies (apk) run: apk add --no-cache git bash grep - uses: actions/checkout@v6 with: submodules: true fetch-tags: true fetch-depth: 0 - name: Git ownership exception run: git config --global --add safe.directory /__w/IronOS/IronOS && git config --global safe.directory "$GITHUB_WORKSPACE" - name: Check and verify documentation run: ./scripts/deploy.sh docs ================================================ FILE: .gitignore ================================================ #### Generic #### # Object files *.o *.ko *.obj *.elf *.d *.DS_Store # Precompiled Headers *.gch *.pch # Libraries *.lib *.a *.la *.lo # Shared objects (inc. Windows DLLs) *.dll *.so *.so.* *.dylib # Executables *.exe *.out *.app *.i*86 *.x86_64 # Debug files *.dSYM/ *.su # Custom scripts & misc. files *.pyc *.lst *.mk *.list # Auto generated files *.cache codeship.aes CoreCompileInputs.cache # IDE configs .vs/* .settings/* .cproject.swp # Visual Studios .vscode/* !.vscode/settings.json !.vscode/tasks.json !.vscode/launch.json !.vscode/extensions.json .vscode/settings.json # Eclipse .metadata bin/ tmp/ *.tmp *.bak *.swp *~.nib local.properties .settings/ .loadpath .recommenders # External tool builders .externalToolBuilders/ # Locally stored "Eclipse launch configurations" *.launch # PyDev specific (Python IDE for Eclipse) *.pydevproject # CDT- autotools .autotools # Java annotation processor (APT) .factorypath # PDT-specific (PHP Development Tools) .buildpath # sbteclipse plugin .target # Tern plugin .tern-project # TeXlipse plugin .texlipse # STS (Spring Tool Suite) .springBeans # Code Recommenders .recommenders/ # Annotation Processing .apt_generated/ # Scala IDE specific (Scala & Java development for Eclipse) .cache-main .scala_dependencies .worksheet # source code tagging systems (GNU Global, ctags, cscope) GPATH GRTAGS GTAGS *tags *tags/ .*tags .*tags/ cscope.* cscope/ .cscope/ #### Jetbrains: IntelliJ, RubyMine, PhpStorm, AppCode, PyCharm, CLion, Android Studio and WebStorm #### # Reference: https://intellij-support.jetbrains.com/hc/en-us/articles/206544839 # User-specific stuff .idea/ .idea/**/workspace.xml .idea/**/tasks.xml .idea/**/usage.statistics.xml .idea/**/dictionaries .idea/**/shelf # Sensitive or high-churn files .idea/**/dataSources/ .idea/**/dataSources.ids .idea/**/dataSources.local.xml .idea/**/sqlDataSources.xml .idea/**/dynamic.xml .idea/**/uiDesigner.xml .idea/**/dbnavigator.xml # Gradle .idea/**/gradle.xml .idea/**/libraries # CMake cmake-build-*/ # Mongo Explorer plugin .idea/**/mongoSettings.xml # File-based project format *.iws # IntelliJ out/ # mpeltonen/sbt-idea plugin .idea_modules/ # JIRA plugin atlassian-ide-plugin.xml # Cursive Clojure plugin .idea/replstate.xml # Crashlytics plugin (for Android Studio and IntelliJ) com_crashlytics_export_strings.xml crashlytics.properties crashlytics-build.properties fabric.properties # Editor-based Rest Client .idea/httpRequests #### IronOS project specific files #### # Binaries source/Hexfile/ source/Objects/ BUILDS/ # Autogenerated source/Core/Gen/ source/Core/Inc/unit.h # Deploy scripts/ci/artefacts/ scripts/ci/secrets/unencrypted/ # Generated static local docs site/ # Translations Translations/__pycache__/ Translation Editor/__pycache__/ Translation Editor/.vscode/ # misc. source/compile_commands.json source/.metadata/* # TS100 related TS100/KiCad/TS100.bak Logo GUI/TS100 Logo Editor/TS100 Logo Editor/obj/ Logo GUI/TS100 Logo Editor/TS100 Logo Editor/bin/ # Tests/linters/sanitizers source/check-style.log .ash_history ================================================ FILE: .gitmodules ================================================ [submodule "source/Core/Drivers/usb-pd"] path = source/Core/Drivers/usb-pd url = https://github.com/Ralim/usb-pd.git ================================================ FILE: Development Resources/TS100/KiCad/MCU_SubBoard.sch ================================================ EESchema Schematic File Version 2 LIBS:power LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:stm32 LIBS:mma8652fc LIBS:switches LIBS:TS100-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 2 2 Title "TS100 Soldering Iron Schematic" Date "" Rev "2.46" Comp "" Comment1 "" Comment2 "" Comment3 "Converted by Ben V. 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H 1975 4600 50 0000 L CNN F 2 "" H 1988 4550 50 0001 C CNN F 3 "" H 1950 4700 50 0001 C CNN 1 1950 4700 1 0 0 -1 $EndComp Wire Wire Line 1950 4550 1950 2750 Wire Wire Line 1950 2750 3100 2750 $Comp L VDD #PWR201 U 1 1 591D66BF P 1950 2450 F 0 "#PWR201" H 1950 2300 50 0001 C CNN F 1 "VDD" H 1950 2600 50 0000 C CNN F 2 "" H 1950 2450 50 0001 C CNN F 3 "" H 1950 2450 50 0001 C CNN 1 1950 2450 1 0 0 -1 $EndComp $Comp L MMA8652FC U3 U 1 1 591D6A94 P 3750 6350 F 0 "U3" H 3400 5950 60 0000 C CNN F 1 "MMA8652FC" H 3950 5950 60 0000 C CNN F 2 "" H 3550 6100 60 0001 C CNN F 3 "" H 3550 6100 60 0000 C CNN 1 3750 6350 1 0 0 -1 $EndComp $Comp L GND #PWR204 U 1 1 591D6B9E P 4650 6700 F 0 "#PWR204" H 4650 6450 50 0001 C CNN F 1 "GND" H 4650 6550 50 0000 C CNN F 2 "" H 4650 6700 50 0001 C CNN F 3 "" H 4650 6700 50 0001 C CNN 1 4650 6700 1 0 0 -1 $EndComp Wire Wire Line 4500 6600 4650 6600 Wire Wire Line 4650 6400 4650 6700 Wire Wire Line 4500 6400 4650 6400 Connection ~ 4650 6600 Wire Wire Line 4500 6500 4650 6500 Connection ~ 4650 6500 $Comp L VDD #PWR203 U 1 1 591D6DA1 P 4650 5900 F 0 "#PWR203" H 4650 5750 50 0001 C CNN F 1 "VDD" H 4650 6050 50 0000 C CNN F 2 "" H 4650 5900 50 0001 C CNN F 3 "" H 4650 5900 50 0001 C CNN 1 4650 5900 1 0 0 -1 $EndComp Wire Wire Line 4650 5900 4650 6200 Wire Wire Line 4650 6100 4500 6100 Wire Wire Line 4650 6200 4500 6200 Connection ~ 4650 6100 $Comp L C C22 U 1 1 591D70DB P 2250 6550 F 0 "C22" H 2275 6650 50 0000 L CNN F 1 "104" H 2275 6450 50 0000 L CNN F 2 "" H 2288 6400 50 0001 C CNN F 3 "" H 2250 6550 50 0001 C CNN 1 2250 6550 1 0 0 -1 $EndComp Text HLabel 3050 6350 0 60 Input ~ 0 SDA Text HLabel 3050 6250 0 60 Input ~ 0 SCL Wire Wire Line 2250 6400 2250 6100 Wire Wire Line 2250 6100 3050 6100 $Comp L GND #PWR202 U 1 1 591D735E P 2250 6700 F 0 "#PWR202" H 2250 6450 50 0001 C CNN F 1 "GND" H 2250 6550 50 0000 C CNN F 2 "" H 2250 6700 50 0001 C CNN F 3 "" H 2250 6700 50 0001 C CNN 1 2250 6700 1 0 0 -1 $EndComp $Comp L C C18 U 1 1 591D7528 P 8200 5800 F 0 "C18" H 8225 5900 50 0000 L CNN F 1 "105" H 8225 5700 50 0000 L CNN F 2 "" H 8238 5650 50 0001 C CNN F 3 "" H 8200 5800 50 0001 C CNN 1 8200 5800 1 0 0 -1 $EndComp $Comp L C C19 U 1 1 591D75B9 P 8500 5800 F 0 "C19" H 8525 5900 50 0000 L CNN F 1 "105" H 8525 5700 50 0000 L CNN F 2 "" H 8538 5650 50 0001 C CNN F 3 "" H 8500 5800 50 0001 C CNN 1 8500 5800 1 0 0 -1 $EndComp $Comp L C C20 U 1 1 591D75EF P 8800 5800 F 0 "C20" H 8825 5900 50 0000 L CNN F 1 "105" H 8825 5700 50 0000 L CNN F 2 "" H 8838 5650 50 0001 C CNN F 3 "" H 8800 5800 50 0001 C CNN 1 8800 5800 1 0 0 -1 $EndComp $Comp L C C25 U 1 1 591D7626 P 9100 5800 F 0 "C25" H 9125 5900 50 0000 L CNN F 1 "104" H 9125 5700 50 0000 L CNN F 2 "" H 9138 5650 50 0001 C CNN F 3 "" H 9100 5800 50 0001 C CNN 1 9100 5800 1 0 0 -1 $EndComp $Comp L C C21 U 1 1 591D7668 P 9400 5800 F 0 "C21" H 9425 5900 50 0000 L CNN F 1 "105" H 9425 5700 50 0000 L CNN F 2 "" H 9438 5650 50 0001 C CNN F 3 "" H 9400 5800 50 0001 C CNN 1 9400 5800 1 0 0 -1 $EndComp Wire Wire Line 8200 5950 9400 5950 Connection ~ 8500 5950 Connection ~ 8800 5950 Connection ~ 9100 5950 Wire Wire Line 8200 5650 9400 5650 Connection ~ 9100 5650 Connection ~ 8800 5650 Connection ~ 8500 5650 $Comp L GND #PWR208 U 1 1 591D78AD P 8800 5950 F 0 "#PWR208" H 8800 5700 50 0001 C CNN F 1 "GND" H 8800 5800 50 0000 C CNN F 2 "" H 8800 5950 50 0001 C CNN F 3 "" H 8800 5950 50 0001 C CNN 1 8800 5950 1 0 0 -1 $EndComp $Comp L VDD #PWR207 U 1 1 591D78DF P 8800 5650 F 0 "#PWR207" H 8800 5500 50 0001 C CNN F 1 "VDD" H 8800 5800 50 0000 C CNN F 2 "" H 8800 5650 50 0001 C CNN F 3 "" H 8800 5650 50 0001 C CNN 1 8800 5650 1 0 0 -1 $EndComp Text Label 3050 6600 2 60 ~ 0 ACC_INT2 Text Label 3050 6500 2 60 ~ 0 ACC_INT1 Text Label 3100 3850 2 60 ~ 0 ACC_INT2 Text Label 3100 4050 2 60 ~ 0 ACC_INT1 $EndSCHEMATC ================================================ FILE: Development Resources/TS100/KiCad/TS100.pro ================================================ update=18/05/2017 9:29:06 PM version=1 last_client=kicad [pcbnew] version=1 LastNetListRead= UseCmpFile=1 PadDrill=0.600000000000 PadDrillOvalY=0.600000000000 PadSizeH=1.500000000000 PadSizeV=1.500000000000 PcbTextSizeV=1.500000000000 PcbTextSizeH=1.500000000000 PcbTextThickness=0.300000000000 ModuleTextSizeV=1.000000000000 ModuleTextSizeH=1.000000000000 ModuleTextSizeThickness=0.150000000000 SolderMaskClearance=0.000000000000 SolderMaskMinWidth=0.000000000000 DrawSegmentWidth=0.200000000000 BoardOutlineThickness=0.100000000000 ModuleOutlineThickness=0.150000000000 [cvpcb] version=1 NetIExt=net [general] version=1 [eeschema] version=1 LibDir= [eeschema/libraries] LibName1=power LibName2=device LibName3=transistors LibName4=conn LibName5=linear LibName6=regul LibName7=74xx LibName8=cmos4000 LibName9=adc-dac LibName10=memory LibName11=xilinx LibName12=microcontrollers LibName13=dsp LibName14=microchip LibName15=analog_switches LibName16=motorola LibName17=texas LibName18=intel LibName19=audio LibName20=interface LibName21=digital-audio LibName22=philips LibName23=display LibName24=cypress LibName25=siliconi LibName26=opto LibName27=atmel LibName28=contrib LibName29=valves LibName30=stm32 LibName31=mma8652fc LibName32=switches ================================================ FILE: Development Resources/TS100/KiCad/TS100.sch ================================================ EESchema Schematic File Version 2 LIBS:power LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:stm32 LIBS:mma8652fc LIBS:switches LIBS:TS100-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 1 2 Title "TS100 Soldering Iron Schematic" Date "2017-05-18" Rev "2.46" Comp "" Comment1 "" Comment2 "" Comment3 "Converted by Ben V. Brown" Comment4 "KiCad port of published schematic" $EndDescr $Sheet S 1450 1000 1450 1850 U 591D5966 F0 "STM32 & Accel Sub Board" 60 F1 "MCU_SubBoard.sch" 60 F2 "SWDIO" I R 2900 1100 60 F3 "SWCLK" I R 2900 1200 60 F4 "USB_D-" I R 2900 1350 60 F5 "USB_D+" I R 2900 1450 60 F6 "K1" I R 2900 1650 60 F7 "nCR" I R 2900 2150 60 F8 "TMP36" I R 2900 2250 60 F9 "K2" I R 2900 1750 60 F10 "SCL" I R 2900 2550 60 F11 "SDA" I R 2900 2650 60 F12 "Po" I R 2900 2050 60 F13 "Vb" I R 2900 1950 60 $EndSheet $Comp L BARREL_JACK J101 U 1 1 591D8B75 P 1600 3600 F 0 "J101" H 1600 3795 50 0000 C CNN F 1 "BARREL_JACK" H 1600 3445 50 0000 C CNN F 2 "" H 1600 3600 50 0001 C CNN F 3 "" H 1600 3600 50 0001 C CNN 1 1600 3600 1 0 0 -1 $EndComp Text Label 1900 3500 0 60 ~ 0 VIN $Comp L GND #PWR103 U 1 1 591D8F24 P 2000 3800 F 0 "#PWR103" H 2000 3550 50 0001 C CNN F 1 "GND" H 2000 3650 50 0000 C CNN F 2 "" H 2000 3800 50 0001 C CNN F 3 "" H 2000 3800 50 0001 C CNN 1 2000 3800 1 0 0 -1 $EndComp Wire Wire Line 1900 3600 2000 3600 Wire Wire Line 2000 3600 2000 3800 Wire Wire Line 1900 3700 2000 3700 Connection ~ 2000 3700 $Comp L SW_Push SW1 U 1 1 591D9BC6 P 1400 4550 F 0 "SW1" H 1450 4650 50 0000 L CNN F 1 "SW_Push" H 1400 4490 50 0000 C CNN F 2 "" H 1400 4750 50 0001 C CNN F 3 "" H 1400 4750 50 0001 C CNN F 4 "-" H 1400 4550 60 0001 C CNN "bom_partno" 1 1400 4550 0 1 1 0 $EndComp $Comp L SW_Push SW101 U 1 1 591DA371 P 1700 4550 F 0 "SW101" H 1750 4650 50 0000 L CNN F 1 "SW_Push" H 1700 4490 50 0000 C CNN F 2 "" H 1700 4750 50 0001 C CNN F 3 "" H 1700 4750 50 0001 C CNN 1 1700 4550 0 1 1 0 $EndComp $Comp L GND #PWR102 U 1 1 591DA3DA P 1700 4750 F 0 "#PWR102" H 1700 4500 50 0001 C CNN F 1 "GND" H 1700 4600 50 0000 C CNN F 2 "" H 1700 4750 50 0001 C CNN F 3 "" H 1700 4750 50 0001 C CNN 1 1700 4750 1 0 0 -1 $EndComp $Comp L GND #PWR101 U 1 1 591DA436 P 1400 4750 F 0 "#PWR101" H 1400 4500 50 0001 C CNN F 1 "GND" H 1400 4600 50 0000 C CNN F 2 "" H 1400 4750 50 0001 C CNN F 3 "" H 1400 4750 50 0001 C CNN 1 1400 4750 1 0 0 -1 $EndComp Text Label 1400 4350 0 60 ~ 0 K1 Text Label 1700 4350 0 60 ~ 0 K2 Text Label 2900 1750 0 60 ~ 0 K2 Text Label 2900 1650 0 60 ~ 0 K1 $EndSCHEMATC ================================================ FILE: Development Resources/TS100/TS100.ioc ================================================ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_7 ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_9 ADC1.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC1.Channel-3\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC1.Channel-4\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC1.Channel-5\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC1.ContinuousConvMode=ENABLE ADC1.DataAlign=ADC_DATAALIGN_RIGHT ADC1.DiscontinuousConvMode=DISABLE ADC1.EnableAnalogWatchDog=false ADC1.EnableRegularConversion=ENABLE ADC1.ExternalTrigConv=ADC_SOFTWARE_START ADC1.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,EnableRegularConversion,NbrOfConversion,ExternalTrigConv,InjNumberOfConversion,EnableAnalogWatchDog,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,master,Rank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,Rank-3\#ChannelInjectedConversion,Channel-3\#ChannelInjectedConversion,SamplingTime-3\#ChannelInjectedConversion,InjectedOffset-3\#ChannelInjectedConversion,Rank-4\#ChannelInjectedConversion,Channel-4\#ChannelInjectedConversion,SamplingTime-4\#ChannelInjectedConversion,InjectedOffset-4\#ChannelInjectedConversion,Rank-5\#ChannelInjectedConversion,Channel-5\#ChannelInjectedConversion,SamplingTime-5\#ChannelInjectedConversion,InjectedOffset-5\#ChannelInjectedConversion,ExternalTrigInjecConv,InjectedConvMode,Mode ADC1.InjNumberOfConversion=4 ADC1.InjectedConvMode=None ADC1.InjectedOffset-2\#ChannelInjectedConversion=0 ADC1.InjectedOffset-3\#ChannelInjectedConversion=0 ADC1.InjectedOffset-4\#ChannelInjectedConversion=0 ADC1.InjectedOffset-5\#ChannelInjectedConversion=0 ADC1.Mode=ADC_DUALMODE_REGSIMULT_INJECSIMULT ADC1.NbrOfConversion=2 ADC1.NbrOfConversionFlag=1 ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.Rank-1\#ChannelRegularConversion=2 ADC1.Rank-2\#ChannelInjectedConversion=1 ADC1.Rank-3\#ChannelInjectedConversion=2 ADC1.Rank-4\#ChannelInjectedConversion=3 ADC1.Rank-5\#ChannelInjectedConversion=4 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5 ADC1.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_239CYCLES_5 ADC1.SamplingTime-3\#ChannelInjectedConversion=ADC_SAMPLETIME_71CYCLES_5 ADC1.SamplingTime-4\#ChannelInjectedConversion=ADC_SAMPLETIME_239CYCLES_5 ADC1.SamplingTime-5\#ChannelInjectedConversion=ADC_SAMPLETIME_71CYCLES_5 ADC1.ScanConvMode=ADC_SCAN_ENABLE ADC1.master=1 ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_8 ADC2.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC2.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC2.Channel-3\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC2.Channel-4\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC2.ContinuousConvMode=DISABLE ADC2.DataAlign=ADC_DATAALIGN_RIGHT ADC2.DiscontinuousConvMode=DISABLE ADC2.EnableAnalogWatchDog=false ADC2.EnableRegularConversion=ENABLE ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,Rank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,Rank-3\#ChannelInjectedConversion,Channel-3\#ChannelInjectedConversion,SamplingTime-3\#ChannelInjectedConversion,InjectedOffset-3\#ChannelInjectedConversion,Rank-4\#ChannelInjectedConversion,Channel-4\#ChannelInjectedConversion,SamplingTime-4\#ChannelInjectedConversion,InjectedOffset-4\#ChannelInjectedConversion,InjNumberOfConversion,Mode,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,EnableRegularConversion,NbrOfConversion,InjectedConvMode,EnableAnalogWatchDog ADC2.InjNumberOfConversion=4 ADC2.InjectedConvMode=None ADC2.InjectedOffset-1\#ChannelInjectedConversion=0 ADC2.InjectedOffset-2\#ChannelInjectedConversion=0 ADC2.InjectedOffset-3\#ChannelInjectedConversion=0 ADC2.InjectedOffset-4\#ChannelInjectedConversion=0 ADC2.Mode=ADC_DUALMODE_REGSIMULT_INJECSIMULT ADC2.NbrOfConversion=1 ADC2.NbrOfConversionFlag=1 ADC2.Rank-0\#ChannelRegularConversion=1 ADC2.Rank-1\#ChannelInjectedConversion=1 ADC2.Rank-2\#ChannelInjectedConversion=2 ADC2.Rank-3\#ChannelInjectedConversion=3 ADC2.Rank-4\#ChannelInjectedConversion=4 ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-3\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-4\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.ScanConvMode=ADC_SCAN_ENABLE Dma.ADC1.2.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC1.2.Instance=DMA1_Channel1 Dma.ADC1.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC1.2.MemInc=DMA_MINC_ENABLE Dma.ADC1.2.Mode=DMA_CIRCULAR Dma.ADC1.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC1.2.PeriphInc=DMA_PINC_DISABLE Dma.ADC1.2.Priority=DMA_PRIORITY_VERY_HIGH Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.I2C1_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.I2C1_RX.0.Instance=DMA1_Channel7 Dma.I2C1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE Dma.I2C1_RX.0.MemInc=DMA_MINC_ENABLE Dma.I2C1_RX.0.Mode=DMA_NORMAL Dma.I2C1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.I2C1_RX.0.PeriphInc=DMA_PINC_DISABLE Dma.I2C1_RX.0.Priority=DMA_PRIORITY_MEDIUM Dma.I2C1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.I2C1_TX.1.Direction=DMA_MEMORY_TO_PERIPH Dma.I2C1_TX.1.Instance=DMA1_Channel6 Dma.I2C1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE Dma.I2C1_TX.1.MemInc=DMA_MINC_ENABLE Dma.I2C1_TX.1.Mode=DMA_NORMAL Dma.I2C1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.I2C1_TX.1.PeriphInc=DMA_PINC_DISABLE Dma.I2C1_TX.1.Priority=DMA_PRIORITY_MEDIUM Dma.I2C1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.Request0=I2C1_RX Dma.Request1=I2C1_TX Dma.Request2=ADC1 Dma.RequestsNb=3 FREERTOS.FootprintOK=true FREERTOS.INCLUDE_vTaskDelete=0 FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configTOTAL_HEAP_SIZE,INCLUDE_vTaskDelete,FootprintOK FREERTOS.Tasks01=GUITask,0,512,StartGUITask,Default,NULL,Dynamic,NULL,NULL;PIDTask,0,256,StartPIDTask,Default,NULL,Dynamic,NULL,NULL;ROTTask,-2,256,StartRotationTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configMAX_PRIORITIES=4 FREERTOS.configMINIMAL_STACK_SIZE=256 FREERTOS.configTICK_RATE_HZ=100 FREERTOS.configTOTAL_HEAP_SIZE=10240 File.Version=6 I2C1.DutyCycle=I2C_DUTYCYCLE_2 I2C1.I2C_Mode=I2C_Fast I2C1.IPParameters=I2C_Mode,DutyCycle IWDG.IPParameters=Prescaler IWDG.Prescaler=IWDG_PRESCALER_256 KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=ADC1 Mcu.IP1=ADC2 Mcu.IP10=TIM3 Mcu.IP2=DMA Mcu.IP3=FREERTOS Mcu.IP4=I2C1 Mcu.IP5=IWDG Mcu.IP6=NVIC Mcu.IP7=RCC Mcu.IP8=SYS Mcu.IP9=TIM2 Mcu.IPNb=11 Mcu.Name=STM32F103T(8-B)Ux Mcu.Package=VFQFPN36 Mcu.Pin0=PA6 Mcu.Pin1=PA7 Mcu.Pin10=PB5 Mcu.Pin11=PB6 Mcu.Pin12=PB7 Mcu.Pin13=VP_FREERTOS_VS_ENABLE Mcu.Pin14=VP_IWDG_VS_IWDG Mcu.Pin15=VP_SYS_VS_tim1 Mcu.Pin16=VP_TIM2_VS_ClockSourceINT Mcu.Pin17=VP_TIM2_VS_no_output1 Mcu.Pin18=VP_TIM2_VS_no_output3 Mcu.Pin19=VP_TIM3_VS_ClockSourceINT Mcu.Pin2=PB0 Mcu.Pin20=VP_TIM3_VS_no_output4 Mcu.Pin3=PB1 Mcu.Pin4=PA8 Mcu.Pin5=PA9 Mcu.Pin6=PA13 Mcu.Pin7=PA14 Mcu.Pin8=PB3 Mcu.Pin9=PB4 Mcu.PinsNb=21 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103T8Ux MxCube.Version=4.26.0 MxDb.Version=DB.4.0.260 NVIC.ADC1_2_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DMA1_Channel6_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DMA1_Channel7_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.I2C1_ER_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.I2C1_EV_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:true NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.TimeBase=TIM1_UP_IRQn NVIC.TimeBaseIP=TIM1 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true PA13.Locked=true PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK PA6.GPIOParameters=GPIO_Label PA6.GPIO_Label=KEY_B PA6.Locked=true PA6.Signal=GPIO_Input PA7.GPIOParameters=GPIO_Label PA7.GPIO_Label=TMP36_INPUT PA7.Locked=true PA7.Signal=ADCx_IN7 PA8.GPIOParameters=GPIO_Label PA8.GPIO_Label=OLED_RESET PA8.Locked=true PA8.Signal=GPIO_Output PA9.GPIOParameters=GPIO_Label PA9.GPIO_Label=KEY_A PA9.Locked=true PA9.Signal=GPIO_Input PB0.GPIOParameters=GPIO_Label PB0.GPIO_Label=TIP_TEMP PB0.Locked=true PB0.Signal=ADCx_IN8 PB1.GPIOParameters=GPIO_Label PB1.GPIO_Label=VIN PB1.Locked=true PB1.Signal=ADCx_IN9 PB3.GPIOParameters=GPIO_Label PB3.GPIO_Label=INT_Orientation PB3.Locked=true PB3.Signal=GPXTI3 PB4.GPIOParameters=GPIO_Label PB4.GPIO_Label=PWM Out PB4.Locked=true PB4.Signal=S_TIM3_CH1 PB5.GPIOParameters=GPIO_Label PB5.GPIO_Label=INT_Movement PB5.Locked=true PB5.Signal=GPXTI5 PB6.GPIOParameters=GPIO_Label PB6.GPIO_Label=SCL PB6.Mode=I2C PB6.Signal=I2C1_SCL PB7.GPIOParameters=GPIO_Label PB7.GPIO_Label=SDA PB7.Mode=I2C PB7.Signal=I2C1_SDA PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103T(8-B)Ux PCC.PartNumber=STM32F103T8Ux PCC.Seq0=0 PCC.Series=STM32F1 PCC.Temperature=25 PCC.Vdd=3.3 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=3 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F103T8Ux ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.6.1 ProjectManager.FreePins=true ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Src ProjectManager.PreviousToolchain=TrueSTUDIO ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=TS100.ioc ProjectManager.ProjectName=TS100 ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=TrueSTUDIO ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-SystemClock_Config-RCC-false-HAL-true,6-MX_TIM3_Init-TIM3-false-HAL-true,7-MX_IWDG_Init-IWDG-false-HAL-true,8-MX_TIM2_Init-TIM2-false-HAL-true,9-MX_ADC2_Init-ADC2-false-HAL-true RCC.ADCFreqValue=8000000 RCC.ADCPresc=RCC_ADCPCLK2_DIV8 RCC.AHBFreq_Value=64000000 RCC.APB1CLKDivider=RCC_HCLK_DIV16 RCC.APB1Freq_Value=4000000 RCC.APB1TimFreq_Value=8000000 RCC.APB2Freq_Value=64000000 RCC.APB2TimFreq_Value=64000000 RCC.FCLKCortexFreq_Value=64000000 RCC.FamilyName=M RCC.HCLKFreq_Value=64000000 RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler RCC.MCOFreq_Value=64000000 RCC.PLLCLKFreq_Value=64000000 RCC.PLLMCOFreq_Value=32000000 RCC.PLLMUL=RCC_PLL_MUL16 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI_DIV2 RCC.SYSCLKFreq_VALUE=64000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=64000000 RCC.USBFreq_Value=42666666.666666664 RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5 SH.ADCx_IN7.0=ADC1_IN7,IN7 SH.ADCx_IN7.ConfNb=1 SH.ADCx_IN8.0=ADC1_IN8,IN8 SH.ADCx_IN8.1=ADC2_IN8,IN8 SH.ADCx_IN8.ConfNb=2 SH.ADCx_IN9.0=ADC2_IN9 SH.ADCx_IN9.1=ADC1_IN9,IN9 SH.ADCx_IN9.ConfNb=2 SH.GPXTI3.0=GPIO_EXTI3 SH.GPXTI3.ConfNb=1 SH.GPXTI5.0=GPIO_EXTI5 SH.GPXTI5.ConfNb=1 SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1 SH.S_TIM3_CH1.ConfNb=1 TIM2.Channel-PWM\ Generation1\ No\ Output=TIM_CHANNEL_1 TIM2.Channel-PWM\ Generation3\ No\ Output=TIM_CHANNEL_3 TIM2.IPParameters=Channel-PWM Generation1 No Output,Channel-PWM Generation3 No Output TIM3.Channel-Output\ Compare4\ No\ Output=TIM_CHANNEL_4 TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM3.ClockDivision=TIM_CLOCKDIVISION_DIV4 TIM3.IPParameters=Channel-PWM Generation1 CH1,OCFastMode_PWM-PWM Generation1 CH1,ClockDivision,Prescaler,Period,Channel-Output Compare4 No Output,OCMode_4,Pulse-Output Compare4 No Output TIM3.OCFastMode_PWM-PWM\ Generation1\ CH1=TIM_OCFAST_ENABLE TIM3.OCMode_4=TIM_OCMODE_ACTIVE TIM3.Period=65535 TIM3.Prescaler=2000 TIM3.Pulse-Output\ Compare4\ No\ Output=65000 VP_FREERTOS_VS_ENABLE.Mode=Enabled VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG VP_SYS_VS_tim1.Mode=TIM1 VP_SYS_VS_tim1.Signal=SYS_VS_tim1 VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM2_VS_no_output1.Mode=PWM Generation1 No Output VP_TIM2_VS_no_output1.Signal=TIM2_VS_no_output1 VP_TIM2_VS_no_output3.Mode=PWM Generation3 No Output VP_TIM2_VS_no_output3.Signal=TIM2_VS_no_output3 VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT VP_TIM3_VS_no_output4.Mode=Output Compare4 No Output VP_TIM3_VS_no_output4.Signal=TIM3_VS_no_output4 board=TS100 ================================================ FILE: Development Resources/TS80/TS80-Bootloader.hex ================================================ :020000040800F2 :2000000020310020E52E00088D2E00088F2E0008912E0008932E0008952E00080000000071 :20002000000000000000000000000000972E0008992E0008000000009B2E00089D2E000880 :20004000252F0008292F00082D2F0008312F0008352F0008392F00083D2F0008412F000850 :20006000452F0008492F00084D2F0008512F0008552F0008592F00085D2F0008612F000830 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:203FC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01 :203FE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1 :00000001FF ================================================ FILE: Development Resources/TS80/TS80.ioc ================================================ #MicroXplorer Configuration settings - do not modify ADC1.Channel-31\#ChannelRegularConversion=ADC_CHANNEL_4 ADC1.Channel-32\#ChannelInjectedConversion=ADC_CHANNEL_2 ADC1.Channel-33\#ChannelInjectedConversion=ADC_CHANNEL_2 ADC1.Channel-34\#ChannelInjectedConversion=ADC_CHANNEL_2 ADC1.Channel-35\#ChannelInjectedConversion=ADC_CHANNEL_2 ADC1.ContinuousConvMode=DISABLE ADC1.DataAlign=ADC_DATAALIGN_RIGHT ADC1.DiscontinuousConvMode=DISABLE ADC1.EnableAnalogWatchDog=false ADC1.EnableRegularConversion=ENABLE ADC1.ExternalTrigConv=ADC_SOFTWARE_START ADC1.ExternalTrigInjecConv=ADC_INJECTED_SOFTWARE_START ADC1.IPParameters=Rank-31\#ChannelRegularConversion,Channel-31\#ChannelRegularConversion,SamplingTime-31\#ChannelRegularConversion,NbrOfConversionFlag,master,Rank-32\#ChannelInjectedConversion,Channel-32\#ChannelInjectedConversion,SamplingTime-32\#ChannelInjectedConversion,InjectedOffset-32\#ChannelInjectedConversion,Rank-33\#ChannelInjectedConversion,Channel-33\#ChannelInjectedConversion,SamplingTime-33\#ChannelInjectedConversion,InjectedOffset-33\#ChannelInjectedConversion,Rank-34\#ChannelInjectedConversion,Channel-34\#ChannelInjectedConversion,SamplingTime-34\#ChannelInjectedConversion,InjectedOffset-34\#ChannelInjectedConversion,Rank-35\#ChannelInjectedConversion,Channel-35\#ChannelInjectedConversion,SamplingTime-35\#ChannelInjectedConversion,InjectedOffset-35\#ChannelInjectedConversion,InjNumberOfConversion,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,EnableRegularConversion,NbrOfConversion,ExternalTrigConv,ExternalTrigInjecConv,InjectedConvMode,EnableAnalogWatchDog ADC1.InjNumberOfConversion=4 ADC1.InjectedConvMode=None ADC1.InjectedOffset-32\#ChannelInjectedConversion=0 ADC1.InjectedOffset-33\#ChannelInjectedConversion=0 ADC1.InjectedOffset-34\#ChannelInjectedConversion=0 ADC1.InjectedOffset-35\#ChannelInjectedConversion=0 ADC1.NbrOfConversion=1 ADC1.NbrOfConversionFlag=1 ADC1.Rank-31\#ChannelRegularConversion=1 ADC1.Rank-32\#ChannelInjectedConversion=1 ADC1.Rank-33\#ChannelInjectedConversion=2 ADC1.Rank-34\#ChannelInjectedConversion=3 ADC1.Rank-35\#ChannelInjectedConversion=4 ADC1.SamplingTime-31\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.SamplingTime-32\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.SamplingTime-33\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.SamplingTime-34\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.SamplingTime-35\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC1.ScanConvMode=ADC_SCAN_ENABLE ADC1.master=1 ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 ADC2.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_3 ADC2.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_3 ADC2.Channel-3\#ChannelInjectedConversion=ADC_CHANNEL_3 ADC2.Channel-4\#ChannelInjectedConversion=ADC_CHANNEL_3 ADC2.ContinuousConvMode=DISABLE ADC2.DataAlign=ADC_DATAALIGN_RIGHT ADC2.DiscontinuousConvMode=DISABLE ADC2.EnableAnalogWatchDog=false ADC2.EnableRegularConversion=ENABLE ADC2.ExternalTrigConv=ADC_SOFTWARE_START ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,Rank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,Rank-3\#ChannelInjectedConversion,Channel-3\#ChannelInjectedConversion,SamplingTime-3\#ChannelInjectedConversion,InjectedOffset-3\#ChannelInjectedConversion,Rank-4\#ChannelInjectedConversion,Channel-4\#ChannelInjectedConversion,SamplingTime-4\#ChannelInjectedConversion,InjectedOffset-4\#ChannelInjectedConversion,InjNumberOfConversion,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,EnableRegularConversion,NbrOfConversion,ExternalTrigConv,EnableAnalogWatchDog ADC2.InjNumberOfConversion=0 ADC2.InjectedOffset-1\#ChannelInjectedConversion=0 ADC2.InjectedOffset-2\#ChannelInjectedConversion=0 ADC2.InjectedOffset-3\#ChannelInjectedConversion=0 ADC2.InjectedOffset-4\#ChannelInjectedConversion=0 ADC2.NbrOfConversion=1 ADC2.NbrOfConversionFlag=1 ADC2.Rank-0\#ChannelRegularConversion=1 ADC2.Rank-1\#ChannelInjectedConversion=1 ADC2.Rank-2\#ChannelInjectedConversion=2 ADC2.Rank-3\#ChannelInjectedConversion=3 ADC2.Rank-4\#ChannelInjectedConversion=4 ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-3\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.SamplingTime-4\#ChannelInjectedConversion=ADC_SAMPLETIME_1CYCLE_5 ADC2.ScanConvMode=ADC_SCAN_DISABLE Dma.I2C1_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.I2C1_RX.0.Instance=DMA1_Channel7 Dma.I2C1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE Dma.I2C1_RX.0.MemInc=DMA_MINC_ENABLE Dma.I2C1_RX.0.Mode=DMA_NORMAL Dma.I2C1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.I2C1_RX.0.PeriphInc=DMA_PINC_DISABLE Dma.I2C1_RX.0.Priority=DMA_PRIORITY_MEDIUM Dma.I2C1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.I2C1_TX.1.Direction=DMA_MEMORY_TO_PERIPH Dma.I2C1_TX.1.Instance=DMA1_Channel6 Dma.I2C1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE Dma.I2C1_TX.1.MemInc=DMA_MINC_ENABLE Dma.I2C1_TX.1.Mode=DMA_NORMAL Dma.I2C1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.I2C1_TX.1.PeriphInc=DMA_PINC_DISABLE Dma.I2C1_TX.1.Priority=DMA_PRIORITY_MEDIUM Dma.I2C1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.Request0=I2C1_RX Dma.Request1=I2C1_TX Dma.RequestsNb=2 FREERTOS.FootprintOK=true FREERTOS.INCLUDE_vTaskDelete=0 FREERTOS.IPParameters=Tasks01,configTICK_RATE_HZ,configMAX_PRIORITIES,configMINIMAL_STACK_SIZE,configTOTAL_HEAP_SIZE,INCLUDE_vTaskDelete,FootprintOK FREERTOS.Tasks01=GUITask,0,512,StartGUITask,Default,NULL,Dynamic,NULL,NULL;PIDTask,0,256,StartPIDTask,Default,NULL,Dynamic,NULL,NULL;ROTTask,-2,256,StartRotationTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configMAX_PRIORITIES=4 FREERTOS.configMINIMAL_STACK_SIZE=256 FREERTOS.configTICK_RATE_HZ=100 FREERTOS.configTOTAL_HEAP_SIZE=10240 File.Version=6 I2C1.DutyCycle=I2C_DUTYCYCLE_2 I2C1.I2C_Mode=I2C_Fast I2C1.IPParameters=I2C_Mode,DutyCycle IWDG.IPParameters=Prescaler IWDG.Prescaler=IWDG_PRESCALER_256 KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=ADC1 Mcu.IP1=ADC2 Mcu.IP10=TIM3 Mcu.IP2=DMA Mcu.IP3=FREERTOS Mcu.IP4=I2C1 Mcu.IP5=IWDG Mcu.IP6=NVIC Mcu.IP7=RCC Mcu.IP8=SYS Mcu.IP9=TIM2 Mcu.IPNb=11 Mcu.Name=STM32F103T(8-B)Ux Mcu.Package=VFQFPN36 Mcu.Pin0=PA0-WKUP Mcu.Pin1=PA2 Mcu.Pin10=PA11 Mcu.Pin11=PA12 Mcu.Pin12=PA13 Mcu.Pin13=PA14 Mcu.Pin14=PA15 Mcu.Pin15=PB3 Mcu.Pin16=PB4 Mcu.Pin17=PB5 Mcu.Pin18=PB6 Mcu.Pin19=PB7 Mcu.Pin2=PA3 Mcu.Pin20=VP_FREERTOS_VS_ENABLE Mcu.Pin21=VP_IWDG_VS_IWDG Mcu.Pin22=VP_SYS_VS_ND Mcu.Pin23=VP_SYS_VS_tim1 Mcu.Pin24=VP_TIM2_VS_ClockSourceINT Mcu.Pin25=VP_TIM2_VS_no_output1 Mcu.Pin26=VP_TIM2_VS_no_output3 Mcu.Pin27=VP_TIM3_VS_ClockSourceINT Mcu.Pin28=VP_TIM3_VS_no_output4 Mcu.Pin3=PA4 Mcu.Pin4=PA6 Mcu.Pin5=PB0 Mcu.Pin6=PB1 Mcu.Pin7=PA8 Mcu.Pin8=PA9 Mcu.Pin9=PA10 Mcu.PinsNb=29 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103T8Ux MxCube.Version=4.26.0 MxDb.Version=DB.4.0.260 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.DMA1_Channel6_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DMA1_Channel7_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.I2C1_ER_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.I2C1_EV_IRQn=true\:5\:0\:false\:false\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:true NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.TimeBase=TIM1_UP_IRQn NVIC.TimeBaseIP=TIM1 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true PA0-WKUP.GPIOParameters=GPIO_Label PA0-WKUP.GPIO_Label=RM PA0-WKUP.Locked=true PA0-WKUP.Signal=GPIO_Output PA10.GPIOParameters=GPIO_Label PA10.GPIO_Label=QC_DM_11K PA10.Locked=true PA10.Signal=GPIO_Output PA11.GPIOParameters=GPIO_Label PA11.GPIO_Label=USB_DM PA11.Locked=true PA11.Signal=GPIO_Analog PA12.GPIOParameters=GPIO_Label PA12.GPIO_Label=USB_DP PA12.Locked=true PA12.Signal=GPIO_Analog PA13.GPIOParameters=GPIO_Label PA13.GPIO_Label=QC_DP_SENSE PA13.Locked=true PA13.Signal=GPIO_Input PA14.GPIOParameters=GPIO_Label PA14.GPIO_Label=QC_DM_SENSE PA14.Locked=true PA14.Signal=GPIO_Input PA15.GPIOParameters=GPIO_Label PA15.GPIO_Label=OLED_RESET PA15.Locked=true PA15.Signal=GPIO_Output PA2.GPIOParameters=GPIO_Label PA2.GPIO_Label=ADC_VIN PA2.Locked=true PA2.Signal=ADCx_IN2 PA3.GPIOParameters=GPIO_Label PA3.GPIO_Label=ADC_TIP PA3.Locked=true PA3.Signal=ADCx_IN3 PA4.GPIOParameters=GPIO_Label PA4.GPIO_Label=ADC_TMP36 PA4.Locked=true PA4.Signal=ADCx_IN4 PA6.GPIOParameters=GPIO_Label PA6.GPIO_Label=PWM Out PA6.Locked=true PA6.Signal=S_TIM3_CH1 PA8.GPIOParameters=GPIO_Label PA8.GPIO_Label=QC_DM_3K PA8.Locked=true PA8.Signal=GPIO_Output PA9.GPIOParameters=GPIO_Label PA9.GPIO_Label=MODEL_SEL PA9.Locked=true PA9.Signal=GPIO_Input PB0.GPIOParameters=GPIO_Label PB0.GPIO_Label=KEY_A PB0.Locked=true PB0.Signal=GPIO_Input PB1.GPIOParameters=GPIO_Label PB1.GPIO_Label=KEY_B PB1.Locked=true PB1.Signal=GPIO_Input PB3.GPIOParameters=GPIO_Label PB3.GPIO_Label=QC_DP_3K PB3.Locked=true PB3.Signal=GPIO_Output PB4.GPIOParameters=GPIO_Label PB4.GPIO_Label=IMU_INT2 PB4.Locked=true PB4.Signal=GPXTI4 PB5.GPIOParameters=GPIO_Label PB5.GPIO_Label=IMU_INT1 PB5.Locked=true PB5.Signal=GPXTI5 PB6.GPIOParameters=GPIO_Label PB6.GPIO_Label=SCL PB6.Mode=I2C PB6.Signal=I2C1_SCL PB7.GPIOParameters=GPIO_Label PB7.GPIO_Label=SDA PB7.Mode=I2C PB7.Signal=I2C1_SDA PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103T(8-B)Ux PCC.PartNumber=STM32F103T8Ux PCC.Seq0=0 PCC.Series=STM32F1 PCC.Temperature=25 PCC.Vdd=3.3 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=3 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F103T8Ux ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.6.1 ProjectManager.FreePins=true ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Src ProjectManager.PreviousToolchain=SW4STM32 ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=TS80.ioc ProjectManager.ProjectName=TS80 ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=SW4STM32 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_I2C1_Init-I2C1-false-HAL-true,4-SystemClock_Config-RCC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_ADC2_Init-ADC2-false-HAL-true RCC.ADCFreqValue=8000000 RCC.ADCPresc=RCC_ADCPCLK2_DIV8 RCC.AHBFreq_Value=64000000 RCC.APB1CLKDivider=RCC_HCLK_DIV16 RCC.APB1Freq_Value=4000000 RCC.APB1TimFreq_Value=8000000 RCC.APB2Freq_Value=64000000 RCC.APB2TimFreq_Value=64000000 RCC.FCLKCortexFreq_Value=64000000 RCC.FamilyName=M RCC.HCLKFreq_Value=64000000 RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler RCC.MCOFreq_Value=64000000 RCC.PLLCLKFreq_Value=64000000 RCC.PLLMCOFreq_Value=32000000 RCC.PLLMUL=RCC_PLL_MUL16 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI_DIV2 RCC.SYSCLKFreq_VALUE=64000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=64000000 RCC.USBFreq_Value=42666666.666666664 RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5 SH.ADCx_IN2.0=ADC1_IN2,IN2 SH.ADCx_IN2.ConfNb=1 SH.ADCx_IN3.0=ADC1_IN3,IN3 SH.ADCx_IN3.1=ADC2_IN3,IN3 SH.ADCx_IN3.ConfNb=2 SH.ADCx_IN4.0=ADC1_IN4,IN4 SH.ADCx_IN4.ConfNb=1 SH.GPXTI4.0=GPIO_EXTI4 SH.GPXTI4.ConfNb=1 SH.GPXTI5.0=GPIO_EXTI5 SH.GPXTI5.ConfNb=1 SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1 SH.S_TIM3_CH1.ConfNb=1 TIM2.Channel-PWM\ Generation1\ No\ Output=TIM_CHANNEL_1 TIM2.Channel-PWM\ Generation3\ No\ Output=TIM_CHANNEL_3 TIM2.IPParameters=Channel-PWM Generation1 No Output,Channel-PWM Generation3 No Output TIM3.Channel-Output\ Compare4\ No\ Output=TIM_CHANNEL_4 TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM3.ClockDivision=TIM_CLOCKDIVISION_DIV4 TIM3.IPParameters=Channel-PWM Generation1 CH1,OCFastMode_PWM-PWM Generation1 CH1,ClockDivision,Prescaler,Period,Channel-Output Compare4 No Output,OCMode_4,Pulse-Output Compare4 No Output TIM3.OCFastMode_PWM-PWM\ Generation1\ CH1=TIM_OCFAST_ENABLE TIM3.OCMode_4=TIM_OCMODE_ACTIVE TIM3.Period=65535 TIM3.Prescaler=2000 TIM3.Pulse-Output\ Compare4\ No\ Output=65000 VP_FREERTOS_VS_ENABLE.Mode=Enabled VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG VP_SYS_VS_ND.Mode=No_Debug VP_SYS_VS_ND.Signal=SYS_VS_ND VP_SYS_VS_tim1.Mode=TIM1 VP_SYS_VS_tim1.Signal=SYS_VS_tim1 VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM2_VS_no_output1.Mode=PWM Generation1 No Output VP_TIM2_VS_no_output1.Signal=TIM2_VS_no_output1 VP_TIM2_VS_no_output3.Mode=PWM Generation3 No Output VP_TIM2_VS_no_output3.Signal=TIM2_VS_no_output3 VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT VP_TIM3_VS_no_output4.Mode=Output Compare4 No Output VP_TIM3_VS_no_output4.Signal=TIM3_VS_no_output4 board=TS100 ================================================ FILE: Documentation/Bluetooth.md ================================================ # Bluetooth Low Energy The Pinecilv2 has hardware support for Bluetooth Low Energy (BLE). This protocol allows reading and writing of parameters to the Pinecil during runtime. The BLE interface advertises three services, these provide access to live telemetry as well as the ability to read/write settings. These are outlined in more detail below. Pinecil devices advertise themselves on BLE as `Pinecil-XXXXXXX`. They also include the UUID `9eae1000-9d0d-48c5-AA55-33e27f9bc533` in the advertisement packet to allow for filtering. Unless otherwise noted, all data is sent and received as Little-Endian. As of the time of writing this, notifications are not fully implemented so data will need to be polled. Notification/Indication support will come when there is time to implement it. ## Using the BLE Interface It is advised to follow the below points when first implementing a BLE integration. Of course once the integration is working feel free to deviate from these. These are just _suggested_ ideas to help kickstart. 1. When filtering for devices, its preferable to filter by the UUID `9eae1000-9d0d-48c5-AA55-33e27f9bc533`, rather than by the device name if possible. 2. Upon first collection check if the three expected services exist; if they don't the user may have selected an incorrect device. 3. It's best to read the live bulk endpoint over the live service when its easy to do so (one read vs ~15). 1. However if you are just updating one or two line items it may be more efficient to just read these on the live service. 2. Feel free to test both and decide. 4. When reading settings from the device; the association of number <-> setting is fixed, but you may see settings you don't yet know about, make sure you can handle these. 5. You probably don't want to show unknown setting's to the user though. 6. Read the device firmware revision and ensure you can decode it. If BLE is revised it may be essential for handling versions cleanly. 7. It's advisable to keep an eye on the IronOS repository or at least setup the Github watch for release notifications. 1. Future releases may revise some BLE aspects or add new settings for example. ## Services Below is a description of each service. Note that the exact settings are not listed for brevity; it's best to refer to [the uuid lists](https://github.com/Ralim/IronOS/blob/dev/source/Core/BSP/Pinecilv2/ble_characteristics.h) and the [handlers](https://github.com/Ralim/IronOS/blob/dev/source/Core/BSP/Pinecilv2/ble_handlers.cpp) alongside this. ### Live `UUID: d85ef000-168e-4a71-AA55-33e27f9bc533` The live services has one characteristic per reading. The readings (in order) are: When implementing these; the ones that are not obvious are generally found in the debugging menu. Values are encoded as an unsigned 32 bit number for all results. 1. Live temperature (In C) 2. Live set point 3. DC input voltage 4. Handle temperature (In C) 5. Power level 6. Power source 7. Tip resistance 8. uptime 9. Time of last movement 10. Maximum temperature settable 11. Raw tip reading 12. Hall sensor 13. Operating mode 14. Estimated wattage ### Settings `UUID: f6d80000-5a10-4eba-AA55-33e27f9bc533` The settings service has two special entries; for saving and resetting settings. Otherwise all settings are enumerated using UUID's of the format : `f6d7ZZZZ-5a10-4eba-AA55-33e27f9bc533))` where `ZZZZ` is the setting number as matched from [Settings.h](https://github.com/Ralim/IronOS/blob/dev/source/Core/Inc/Settings.h#L16). All data is read and written in fixed unsigned 16 bit numbers. #### Settings save To save the settings write a `0x0001` to `f6d7FFFF-5a10-4eba-AA55-33e27f9bc533`. Its advised to not save settings on each change but instead to give the user a save button _or_ save after a timeout. This is just to reduce write cycles on the internal flash. #### Settings reset To reset all settings to defaults; write a `0x0001` to `f6d7FFFE-5a10-4eba-AA55-33e27f9bc533`. This will reset settings immediately. ### Bulk `UUID: 9eae1000-9d0d-48c5-AA55-33e27f9bc533` The bulk endpoint is where extra data is located with varying read sizes. #### Live data The bulk live data endpoint provides all of the data provided in the live endpoint, as one large single-read binary blob. This is designed for applications that are showing large amounts of data as this is more efficient for reading. #### Accelerometer Name _Not yet implemented_ #### Build ID This encodes the current build ID to allow viewing and handling when the BLE format changes. #### Device Serial Number This is generally the device CPU serial number. For most devices this can be used as an ID. On PinecilV2 its the MAC address. #### Device Unique ID This is only relevant on the PinecilV2. This is a random ID that is burned in at the factory. This is used by the online authenticity checker tool. ================================================ FILE: Documentation/DebugMenu.md ================================================ # Debugging Menu In this firmware there is extra debugging information in a hidden sub-menu. This menu is meant to be simple, so it has no fancy GUI animations. - Access it by pressing and holding the rear button (`-/B`) on the iron while it is on the home screen. - Use the front button (`+/A`) to scroll through the menu. - To exit, use the rear button (`-/B`) again. ## Menu items Items are shown in the menu on a single line, so they use short codes. ### Version There is a static line on top which is presented on every sub-screen and reflects exact version of firmware. Version line on top has the following format - `vX.YYN.[ZZZZZZZZ]`: - X: major version - Y: minor version - N: build type: - R - git-related **r**elease tag vXX.YY - T - git-related release **t**ag but version is not vXX.YY ! - D - git-related **d**ev branch - B - git-related custom **b**ranch - E - git-related from d**e**tached commit - G - neither above but **g**it-related - C - build from github **C**I during _pull request_ - H - build outside of a git tree (i.e. release tarball or **h**omebrew customization without git) - S - something **s**pecial[^ERR] - V - something **v**ery special[^ERR] [^ERR]: `S` and `V` are reserved letters for cases when source of firmware is having very unique origin & configuration - Z: short commit ID hash with 8 digits generated automatically from git (for git-related build types only) I.e.: - `v2.22H` means firmware built locally from tarball with release version of `2.22` - `v2.22D.1A2B3C4D` means firmware with development version of `2.22` from git `dev` branch & with commit ID `1A2B3C4D` (so it can be traced for debug purposes) - `v2.22R.5E6F7G8H` means firmware with official release version of `2.22` and it's properly tagged with `v2.22` git tag & with commit ID `5E6F7G8H`' --- **Additional scroll-able items appear in this order**: ### Timestamp - This is a timestamp of firmware compilation and it has the following format: `YYYYMMDD HHMMSS` (i.e., `20230701 213456` means it has been built in July, 1st, 2023 at 9:34:56 pm) ### ID - This is used by Irons that have an ID and serial number to help check if the iron is authentic. All Pinecil V1 show the same ID number as this is the number programmed into the MCU. - The new Pinecil V2 released Aug. 2, 2022 now uses MCU BL706, which enables generating a unique ID/Serial number to every iron. This can be used to verify your [Pinecil authenticity here](https://pinecil.pine64.org/). ### ACC This indicates the accelerometer that is fitted inside the unit. - MMA8652 - LIS2DH12 - BMA223 - MSA301 - SC7A20 - None -> running in fallback without movement detection - Scanning -> Still searching I2C for one ### PWR This indicates the current power source for the iron. This may change during power up as the sources are negotiated in turn. - **DC** input (dumb) - **QC** input (We used QC2/3 negotiation for current supply) - **PD W. VBus** input (PD subsystem is used to negotiate for current supply); and VBus is connected to your input power source - **PD No VBus** input (PD subsystem is used to negotiate for current supply); and VBus is **NOT** connected to your input power source. If it is Not required or possible to do a special mod of your PCB (i.e. late model V1, some early Green PCB models) then [PD No VBus] displays on-screen ([see details and PD Debug section below](https://ralim.github.io/IronOS/DebugMenu/#pd-debug-menu)). ### Vin The input voltage as read by the internal ADC. Can be used to sanity check it is being read correctly. ### Tip C This is the tip temperature in °C. This can be used with RTip for assessing temperature processing performance. ### Han C This is the handle temperature or more accurately the reading of the Cold Junction Compensation (CJC) temperature sensor. This is expressed in °C. Range of 20-40 °C is normal depending on how hot/cold the room is and how long power has been plugged in which warms the PCB further. This is used for CJC of the tip temperature. > If CHan is extremely high, this indicates the temperature sensor isn't reading correctly ([see Troubleshooting](https://ralim.github.io/IronOS/Troubleshooting/)) ### Max C This indicates the max temperature in °C that the system estimates it can measure the tip reliably to. This is dependent on a few factors including the handle temperature so it can move around during use. As you use the iron, the Max increases to a point. ### UpTime This shows how many deciseconds the unit has been powered for (600 ds = 1 minute). ### Move This is the last timestamp of movement. When the iron is moved, this should update to match the Time field (previous menu item). This can be used for checking performance of the movement detection code. ### Tip Res This indicates the tip resistance that the device is currently using. For devices with multiple possible values to choose from (Pinecil V2), the appropriate value is automatically detected at every boot-up. Tip should be installed before boot-up or reading can not be done. ### Tip R This is the raw tip reading in μV. Tip must be installed or reading will be high/inaccurate. At cool, the range of 700-1000 is normal for larger tips and ~1500 for smaller tips (TS80). This is used to evaluate the calibration routines. ### Tip O This is the offset resulting from the *'Cold Junction Compensation Calibration'*. ### HW G This indicates the high water mark for the stack for the GUI thread. The smaller this number is, the less headroom we have in the stack. As this is a high-water mater, you should only trust this once you have walked through all GUI options to "hit" the worst one. ### HW M This indicates the high-water mark for the stack for the movement detection thread. The smaller this number is, the less headroom we have in the stack. ### HW P This indicates the high-water mark for the stack for the PID thread. The smaller this number is, the less headroom we have in the stack. ### Hall This appears if your device is capable of having a hall effect sensor installed (Pinecil). This shows the current magnetic field strength reading from the sensor. It is used to check if the sensor is operational, and for diagnostics and optimal placement of magnets on a stand (higher number is better/stronger). [See Hall Sensor for details](https://ralim.github.io/IronOS/HallSensor/). # PD Debug menu On the Pinecil; if the iron is booted up while long holding the front button (`+`); it will show an extra hidden menu for inspecting USB-PD power adapters. We can also connect to any PD USB power to check Vbus status, even some cell phones with a USB-C port will work if it is PD. It will not show PD messages when Pinecil is powered by DC port, QC, or USB 5V (non-PD). For example, if you connect to a QC charger, you may simply see "PD State 6" which indicates "waiting for source" as no PD messages will be ever be sent and you will not be able to use (`+`) to scroll through PD negotiated messages. Pressing (`+`) cycles through elements, and (`-`) or unplugging will exit the menu. The first page shows the PD negotiation stage number; which can be used for diagnosing if PD is not working. Once negotiation is complete; use (`+`) button to advance to other screens which show the different proposals advertised for voltage and current (State 12 means all is good with the PD charger). #### Below is a method for user modification to convert some early models of Pinecil V1 to safely support 24V on the DC5525 barrel. ⚠️ Warning: do this at your own risk, read everything in this document, and go to the [Pine64 community chat](https://wiki.pine64.org/wiki/Pinecil#Community_links) if you desire advice. An incorrect cut of the trace could render the Pinecil non-working. Background: a simple user modification to the PCB on _some models_ of original V1 allows it to safely use DC barrel 24V by cutting a trace line to the Vbus which held it back to 21V. You can check whether your Pinecil V1 needs the update or can benefit from it by using a hidden trick in the PD debug menu. - Follow instructions above to enter the PD Debug menu. - After a few seconds or after PD negotiates (state above 5) it will show `[PD No VBus]` if it is not needed (i.e., late model V1). Alternately, if it shows `[VBus]`, then the mod has not been done and there is still a connection to the Vbus (the Vbus connection limits you to 21V until you do the mod). - If you need to do the mod, then follow the instructions/links below which have photos. Careful to only cut the trace and nothing else. - Then use the PD debug menu again to check for `[PD No Vbus]` before attaching any 24V PSU to the DC barrel. If you do not get the message, then try cutting the trace a little deeper or using alcohol to clear the gap of copper dust. Then check PD messages again. If you need advice/tips, join the Pine64 chat room. The mod method is shown in the [February 2022 PINE64 community updates](https://www.pine64.org/2022/02/15/february-update-chat-with-the-machine/). Early Pinecil V1 models required cutting a trace to achieve 24V safety with DC barrel PSU. Late model V1 made sometime in 2022 came with `[No Vbus]` already displayed, and no mod is required. | Pinecil V2 model released Aug. 2, 2022 is an overhaul of the PCB with all relevant components capable of 28V. V2 requires no mods to support the use of 24V DC Barrel jack charger. | :-------- ================================================ FILE: Documentation/DebuggingPD.md ================================================ # Debugging PD When using many of these soldering irons, the recommended power source is to use a USB-PD power supply. Occasionally, issues are run into where the iron reboots or appears to not boot when connected to this supply. There are generally a few different reasons for this to occur, the first is of course a bug or incompatibility in the IronOS PD-stack / firmware, but there are also power adapters that either have issues or try to be _smart_ to the detriment of compatibility. It also helps to remember that driving a soldering iron is not like a normal load that these power supplies are designed for. Normally a laptop or phone will gently ramp the power draw up and down. Where as the soldering iron will rapidly go from 0 to full power, and then back to 0 again. This can cause issues with some power supplies tripping out. In general, a normal, boring 60-100W PD supply is recommended. Watch out for adapters with multiple ports that are used by marketing to advertise a higher number. It's somewhat common to see 65W adapters being pushed that have two ports, one of which is 45W and one that is 20W. These cannot support 65W output on one typically. Smarter chargers that try to implement every known protocol can come with quirks. Often slight shortcuts are taken in the PD implementation that can cause hard to debug issues. ## If the unit doesn't power up at all This can be the most frustrating one to diagnose. First, test the device powers up when powered by a USB-A -> USB-C cable. Or a DC power supply. This can rule out other issues that cause the device to appear off (bad flashing). ### No power If your device won't power up on any other supply type, look into if you can boot into the bootloader. This is usually done by holding down a button while connecting it to a computer and then checking if it's detected. If the device shows up to a computer, but doesn't operate when powered up normally, the two most likely causes are a bad flash/firmware OR a non-functioning display. Testing alternative firmware builds or trying to heat the unit (pressing the front button) can be ways to test this. ### Powers up on other supplies If the device powers up on other supplies, but not on the USB-PD supply, it could be a problem with the USB-PD supply itself. Try using a different USB-PD supply to see if the issue persists. If the unit does not power on any PD supplies it could be damage to the PD PHY or the USB connector. USB-PD uses the CC pins on the connector, which are not used for normal data so a USB-A adapter for example doesn't use these at all. ## If the unit powers up but keeps rebooting There are two causes of this: 1. If the reboot occurs when the unit starts to heat up, then it is the power supply being unable to supply the power requested. 2. The unit reboots frequently even without any buttons being pressed. If this is the issue that you are seeing, then the problem is that something during the PD initialisation is failing. The _best_ way to resolve this is to be able to capture the USB PD traffic. This is the only way to know what is **really** going on and why the two devices can't negotiate. To capture PD traffic requires a device that can capture this data. A logic analyser can be used on the CC pins, though note that the signalling voltage is < 3.3V so it will require a logic analyser that can handle this or buffering. Alternatively, a lot of the higher-end USB power meter units can capture the packets. It doesn't matter if it only shows these on screen or if it can save these out to a file (ideally a file though). **Without a traffic capture, all debugging is guessing** On firmwares 2.23+ there is a toggle in advanced settings to change the PD mode. This will adjust how the firmware negotiates with the PD supply slightly. This can enable/disable the PPS and EPR modes (dynamic voltage negotiation). PPS is known to be incorrectly implemented on some supplies, so turning off these features can improve compatibility. If the device is _sometimes_ stable, you can on Pinecil devices boot while holding the front button to enter the PD debug menu. This will show what voltages & power levels are being advertised by the device. This can be used to cross-check with what is printed on the adapter. Take into consideration that non e-marked cables will be limited to 3A and that EPR requires specifically marked cables. If you take the tip out of the iron, it will result in most devices not negotiating a PD profile (the irons wait to know what kind of tip is installed). This can be used to stop the failing negotiations in some situations to allow viewing this menu. Before filing a support request, please try testing other power adapters & cables to try and narrow down the possibilities of the issue being a one-off. If you have the capability to capture the PD traffic, that makes the problem exponentially easier to rectify. ================================================ FILE: Documentation/Development.md ================================================ # Development Building this software can be performed two ways: using the STM32CubeIDE or using command line tools. ## STM32CubeIDE The easiest way to start working with the STM32CubeIDE is to create a new project for the STM32F103RCTx. Once this is created, remove the auto-generated source code. Next, drag the contents of the `source` folder into the project and choose to link to files. You will need to update the build settings for include paths and point to the new `.ld` linker file. ## Command line tools and building a release In the `source` folder there is a `Makefile` that can be used to build the repository using command line tools. When running the `make` command, specify which model of the device and the language(s) you would like to use. ### Windows (MSYS2 environment) 1. Download `msys2` install package from the [official website](https://msys2.org) and install it according to the instruction there; 2. Install requried packages (here and for the future commands use **`mingw64.exe`** terminal): ``` $ pacman -S mingw-w64-x86_64-arm-none-eabi-gcc mingw-w64-x86_64-libwinpthread-git python3 python3-pip make unzip git ``` 3. Download _3rd party RISC-V toolchain_ `xpack-riscv-none-elf-gcc-...-win32-x64.zip` from [this repository](https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases); 4. Move downloaded `xpack-riscv-none-elf-gcc-...-win32-x64.zip` to `msys64` _Windows_ directory (e.g., `C:\msys64\`); 5. Extract files from `xpack-riscv-none-elf-gcc-...-win32-x64.zip` and go back to _home_ directory: ``` $ cd / $ unzip xpack-riscv-none-elf-gcc-...-win32-x64.zip $ cd ~ ``` 6. Permanently set `PATH` environment variable, so all required toolchains could be available for `make` and for other build scripts: ``` $ echo 'export PATH=/xpack-riscv-none-elf-gcc-.../bin:${PATH}' >> ~/.bashrc $ source ~/.bashrc ``` 7. Additionally, `OpenOCD` and/or `ST-Link` can be installed as well to help with flashing: ``` $ pacman -S mingw-w64-x86_64-openocd $ pacman -S mingw-w64-x86_64-stlink ``` 8. Clone _IronOS_ repo: ``` $ git clone --recursive https://github.com/Ralim/IronOS.git $ cd IronOS ``` 9. Follow steps _4-8_ from [macOS section](#macos); 10. `pip` can be updated inside `venv` only: ``` $ python3 -m pip install --upgrade pip ``` ### macOS Use the following steps to set up a build environment for IronOS on the command line (in Terminal). 1. [Follow steps 1 – 3 here to install the toolchain](https://github.com/glegrain/STM32-with-macOS#0---installing-the-toolchain) needed to compile for STM32 microcontrollers. 2. Install `python`: ``` brew install python ``` 3. (Optional) Update `pip` so it doesn't warn you about being out-of-date: ``` python3 -m pip install --upgrade pip ``` 4. Change to the `source` directory: ``` cd source ``` 5. Create a Python virtual environment for IronOS named `ironos-venv` to keep your Python installation clean: ``` python3 -m venv ironos-venv ``` 6. Activate the Python virtual environment: ``` source ironos-venv/bin/activate ``` 7. Install the dependencies required to run `make-translation.py`: ``` pip install bdflib ``` 8. All done! See some examples below for how you can build your own IronOS. ### Examples To build a single language Simplified Chinese firmware for the TS80P with 8 simultaneous jobs: ``` make -j8 model=TS80P firmware-ZH_CN ``` To build a European multi-language firmware for the Pinecil with as many simultaneous jobs as there are logical processors on Linux: ``` make -j$(nproc) model=Pinecil firmware-multi_European ``` To build a Cyrillic compressed multi-language firmware for the Pinecil with as many simultaneous jobs as there are logical processors on macOS: ``` make -j$(sysctl -n hw.logicalcpu) model=Pinecil firmware-multi_compressed_Belarusian+Bulgarian+Russian+Serbian+Ukrainian ``` To build a custom multi-language firmware including English and Simplified Chinese for the TS80: ``` make -j8 model=TS80 custom_multi_langs="EN ZH_CN" firmware-multi_Custom ``` To build a custom compressed multi-language firmware including German, Spanish, and French for the TS100 (note if `model` is unspecified, it will default to `TS100`): ``` make -j8 custom_multi_langs="DE ES FR" firmware-multi_compressed_Custom ``` To build a release instead, run the `build.sh` script. This will update translations and also build every language for all device models. For macOS users, replace `make -j$(nproc)` in the script with `make -j$(sysctl -n hw.logicalcpu)` before running. ## Updating languages To update the language translation files and their associated font maps, execute the `make_translation.py` code from the `Translations` directory. If you edit the translation definitions or the English translation, please also run `gen_menu_docs.py` to update the settings menu documentation automatically. ## Building Pinecil V1 I highly recommend using the command line tools and using Docker to run the compiler. It's a bit fussier on setup than the STM tooling, and this is by far the easiest way. If you _need_ an IDE I have used [Nuclei's IDE](https://nucleisys.com/download.php). Follow the same idea as the STM Cube IDE notes above. ## Building Pinecil V2 To build the Pinecil V2 firmware, you can use a Docker container that provides a consistent development environment across different operating systems, including Windows with WSL2. Here's how to do it: ### Prerequisites Docker Desktop: Install the latest version of Docker Desktop for your operating system from the official website. On Windows follow the instructions on the official documentation to install 'Windows Subsystem for Linux' (WSL2). ### Building Steps 1. Clone the repository, initialize and update submodules: ```sh git clone --recurse-submodules https://github.com/Ralim/IronOS.git ``` 2. Start the Docker container with the development environment: ```sh cd IronOS ./scripts/deploy.sh ``` This script will build a Docker image and run a container with the necessary tools to build the firmware. 3. Build the firmware for Pinecil V2: ```sh cd source/ ./build.sh -l EN -m Pinecilv2 ``` This command will compile the firmware with English language support for Pinecil V2 board. 4. Find the firmware artifacts: After the build completes successfully, you can find the firmware artifacts in the `source/Hexfile` directory. ================================================ FILE: Documentation/Flashing/MHP30.md ================================================ # Flashing / Upgrading your iron ## Downloading source file In the development of this firmware, there are three _types_ of firmware released. These are the "Main" stable releases, which generally have high confidence in being bug free. Release candidates are released slightly more often, and these are generally perfectly fine for everyday use. These are released early to allow for translation checking and for wonderful people to help spot bugs and regressions. Finally, there are the "mainline" builds, which are built from the main git branch. These are built on every change and can be found on the Actions tab (see below). ### Main release Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases). Download the zip file that matches your model of soldering iron and extract it. Select the appropriate file type for your unit, in general Miniware devices need `.hex` and Pinecil needs `.dfu`. Flash according to details below ### Bleeding edge / latest For the _latest_ code, you will need to download the zip file from the artifacts page on the build for what you want. Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch you would like. In general you probably want `master`. Once you click on a run, scroll down to the "Artifacts" section and then click on your model to download a zip file. Then this works the same as a production release (use the correct file). # MHP30 This is completely safe, but if it goes wrong just put the corresponding `.hex` file from [the official website](https://e-design.com.cn/en/NewsDetail/4203645.html) ([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)) onto the unit and you're back to the old firmware. Downloads for the `.hex` files to flash are available on the [releases page.](https://github.com/Ralim/IronOS/releases) The file you want is called MHP30.zip. Inside the zip file (make sure to extract the file before flashing with it) will be a file called `MHP30_{Language-Code}.hex`. Officially the bootloader on the devices only works under Windows (use the built-in File Explorer, as alternative file managers or copy handlers like Teracopy will fail). However, users have reported that it does work under [Mac](#mac), and can be made to work under [Linux](#linux) _sometimes_ (look for details below). 1. Hold the button closest to the tip (MHP30 the left button on the back), and plug in the USB to the computer. 2. The unit will appear as a USB drive. (Screen will say `DFU` on it.) 3. Drag the `.hex` file onto the USB drive. 4. The unit will disconnect and reconnect. 5. The filename will have changed to end in _.RDY_ or _.ERR_ 6. If it ends with _.RDY_ you're done! Otherwise, something went wrong. 7. If it didn't work the first time, try copying the file again without disconnecting the device, often it will work on the second shot. 8. Disconnect the USB and power up the device. You're good to go. For the more adventurous out there, you can also load this firmware onto the device using an SWD programmer, for easier installation follow the guide at the end of this document. On the USB-C port, `USB_D+` is shorted to `SWDIO` and `USB_D-` is shorted to `SWCLK` so debugging works without disassembly (attach while staying in the bootloader). Installing [IronOS-dfu](https://github.com/Ralim/IronOS-dfu) is recommended as it allows reliable flashing of binary files with [dfu-util](http://dfu-util.sourceforge.net/). Noting that for the MHP30 the stock firmware checks a checksum at the end of the first 8k that has to be valid or else it goes into "demo mode". ## Mac sgr1ff1n (Shane) commented in [issue 11](https://github.com/Ralim/IronOS/issues/11) that upgrading worked on their Mac as per normal: > I just wanted to say that I was able to update the firmware on my ts100 from the stock version to 1.08 found in this repository using my Mac. I simply followed the same steps however through Finder. I have a MacBook Pro (13-inch, Mid 2012) running Sierra 10.12.4 (16E195). ## Linux While in the past there were reports of unreliable upgrades, the consensus in [issue 11](https://github.com/Ralim/IronOS/issues/11) is that things work mostly as expected in Linux. @awigen has contributed a script [flash_ts100_linux.sh](https://raw.githubusercontent.com/Ralim/IronOS/dev/scripts/flash_ts100_linux.sh) that works on Ubuntu 16.04 as well as other distros. If you want to do it manually (or if the script does not work for some reason) the general procedure is the same as for Windows, the differences are in the way to mount the unit and copy the firmware. Remember that after flashing, the firmware filename will have changed to end in `.RDY` or `.ERR` or `.NOT` and only `.RDY` means the flashing was successful! - The unit has to be mounted as `msdos` type (thanks @balrog-kun for having spotted it). You may disable automount, but unmounting the automounted drive and remounting as `msdos` works fine. You do not need to turn off automounting, but you do need to unmount the device with `umount`. - It is recommended to use an all-caps filename for the firmware, even if successful flashing were done with lower case names. - Avoid USB hubs, plug directly in your computer. - If it fails, try again several times without unplugging. Just let it remount. Example, to be run as root, once the unit has been plugged in DFU mode and auto-mounted: ```bash FW=ts100.hex unset NAME eval $(lsblk -P -p -d --output NAME,MODEL|grep "DFU[ _]Disk") [ -z ${NAME+x} ] && exit 1 # Could not find DFU device umount "$NAME" mkdir /tmp/mntdfu mount -t msdos "$NAME" /tmp/mntdfu cp "$FW" "/tmp/mntdfu/$(basename $FW|tr a-z A-Z)" sync umount /tmp/mntdfu rmdir /tmp/mntdfu ``` Device will reboot and automount will rerun if not disabled. Check the extension of your firmware, it should be `.RDY` now. ## FAQ #### The file is showing up with the extension `.ERR` This can occur during the programming process if any of the checks in the bootloader fail. This is often triggered by anti-virus software or using a non-Windows host OS. First, try just copying the file a second time. 1. Attach the iron in DFU mode. 2. Copy the `.hex` file to the device. 3. The device disconnects and connects with the `.ERR` file. 4. Copy the same `.hex` file again **⛔ DO NOT TRY AND DELETE THE OLD ONE ⛔**. 5. The device will disconnect and reconnect again. 6. The device _should_ now have the `.RDY` file. 7. You're done. If this fails and you are on Mac or Linux reading the wiki page about programming can help. There is also a very long issue thread going through all of the different attempts around this too. If you are on Windows, it's often best to try another computer (friends, work, partners etc.). #### Device randomly disconnects or does not show up in DFU mode 1. Check if the USB cable you are using has the data pins; test it on another device. There are a surprisingly large number of micro-USB cables that are power _only_. 2. Try other USB ports. Often different USB controllers will interact with the units differently due to design quirks in the Miniware design. ### Alternative bootloader If you are an advanced user, and you have used `usb-dfu` tools before, or you would like to learn; there is an alternative bootloader for these irons. This will **NOT** show up as a USB storage drive, but instead show up using a standard DFU protocol device. You can then use dfu tools or GUIs to upgrade the iron using the `.bin` files that are posted to the releases page. To install this alternative bootloader, follow the instructions [here](https://github.com/Ralim/IronOS-dfu/blob/mainline/docs/Bootloader.md). Note that this is only recommended for users who know what they are doing. If you don't understand how this works, please don't flash this. ================================================ FILE: Documentation/Flashing/Pinecil V1.md ================================================ # Flashing / Upgrading your iron ## Downloading source file In the development of this firmware, there are three _types_ of firmware released. These are the "Main" stable releases, which generally have high confidence in being bug free. Release candidates are released slightly more often, and these are generally perfectly fine for everyday use. These are released early to allow for translation checking and for wonderful people to help spot bugs and regressions. Finally, there are the "mainline" builds, which are built from the main git branch. These are built on every change and can be found on the Actions tab (see below). ### Main release Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases). Download the zip file that matches your model of soldering iron and extract it. Select the appropriate file type for your unit, in general Miniware devices need `.hex`, Pinecil V1 needs `.dfu`, and Pinecil V2 needs `.bin`. Flash according to details below. ### Bleeding edge / latest For the _latest_ code, you will need to download the zip file from the artifacts page on the build for what you want. Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch you would like. In general you probably want `master`. Once you click on a run, scroll down to the "Artifacts" section and then click on your model to download a zip file. Then this works the same as a production release (use the correct file). # Pinecil V1 - The MCU used in Pinecil supports usb-dfu. Reference [Pinecil Wiki](https://wiki.pine64.org/wiki/Pinecil) for hardware and firmware instructions. - Recommended Updater for Windows/MacOS: [Pine64 Updater](https://github.com/pine64/pine64_updater) is an easy-to-use GUI app. It is fast and automatically fetches the newest stable version of IronOS from GitHub. It can also be used to load custom boot logo art. - Recommended Updater for Linux/MacOS: [PineFlash](https://github.com/Spagett1/PineFlash) is an easy-to-use GUI app. It is fast and automatically fetches the newest stable version of IronOS from Github. It can also be used to load custom boot logo art. - Troubleshooting: if you have issues using the Pine64 Updater or your install fails, please go to troubleshooting tips below. - The [Pinecil Wiki](https://wiki.pine64.org/wiki/Pinecil) is a great resource for all things Pinecil. - Community chat: if troubleshooting doesn't work, then join the Pine64 > Pinecil channel [here](https://wiki.pine64.org/wiki/Pinecil#Live_Community_Chat). There are knowledgeable members in Discord/Telegram/Matrix. Discord has a bridge bot connection to Telegram and Matrix so that all pine64 volunteers/members can see advice for Pinecil and related items or just get tips on which power supply to purchase. - One advantage of Pinecil is that you cannot permanently damage it doing a firmware update (because DFU is in ROM); an update could render Pinecil temporarily inoperable if you flash an invalid firmware. But no worries, simply re-flashing with a working firmware copy will fix everything. - USB-C cable is required to do an update. Generally, all USB controllers work, but some hubs have issues, so it is preferred to avoid USB hubs for updates. - Alternate Update Methods: if your OS is not currently supported by the [Pine64 Updater](https://github.com/pine64/pine64_updater) or it does not meet your needs, i.e., you want to install a beta version, the below manual methods may be used. ## Linux and Mac ### Steps ⛔ Do not use the DC barrel jack while updating firmware or you may destroy your PC. ⛔ 1. Highly recommend updating `dfu-util` to the newest version before starting. 2. Download and extract the firmware package from GitHub [IronOS Releases](https://github.com/Ralim/IronOS/releases). 3. Enter DFU mode: press and hold (`-`) button at the back of the iron before you connect the USB-C cable. 4. Connect USB to PC, and USB-C to back of Pinecil, keep holding (`-`) button down. 5. Once the USB cable is connected at two ends, wait ~10 seconds more, then release the (`-`) button. 6. The screen will stay **black/off** to indicate the Pinecil is in DFU mode. This is normal. 7. Using `dfu-util` you can flash the firmware using a command line like this: ``` dfu-util -D Pinecil_EN.dfu ``` Choose the file name from the folder with the appropriate 2-letter country code for your chosen language (i.e., EN = English). ### Troubleshooting: - If you get a message stating that `More than one DFU capable USB device found!` when running the above command you probably have an old version of `dfu-util` installed. Might be worth updating. You can still install on the old version, but you will have to specify which DFU interface to flash to. Running the command `dfu-util -l` will show you if there are several DFU devices detected. Example: ``` Found DFU: [28e9:0189] ver=0100, devnum=48, cfg=1, intf=0, path="1-1", alt=1, name="@Option Bytes /0x1FFFF800/01*016Be", serial="??" Found DFU: [28e9:0189] ver=0100, devnum=48, cfg=1, intf=0, path="1-1", alt=0, name="@Internal Flash /0x08000000/128*001Kg", serial="??" ``` In this example we see that more than one part of the Pinecil is detected as a DFU interface and we need to specify which one we want to flash to. We want the `Internal Flash` so in this case we can use `alt=0` to identify which interface to target. The command would then look like this: ``` dfu-util -D Pinecil_EN.dfu -a 0 ``` - Note: if you use an older release of `dfu-util` and do not see `alt=0, name="@Internal Flash /0x08000000/128*001Kg"` when running `dfu-util -l` you likely will not be able to update without first updating 'dfu-util'. - If your update is crashing part-way into the update, there is sometimes an issue with older/fussy USB controllers (they can show up/disappear/then show up again) - Try a direct connection to the USB port, do not use a USB hub, and use shorter cable. If possible, pick a port connected to the main board. - Switch to a different PC/Laptop and use different ports. USB-C ports are recommended but some have also reported having a fussy C port. - Hold down the (-) button for the entire firmware update, do not release until near the end. - `DC Low` message: a pc/laptop cannot fully power Pinecil, it generally can only get 5 V (non-PD) to communicate for firmware updates and Pinecil will report 'DC Low'. This is normal. - If `dfu-util` aborts with an error like ``` dfu-util: Cannot open DFU device 28e9:0189 found on devnum 42 (LIBUSB_ERROR_IO) ``` and `dmesg` reports USB errors like these ``` kernel: usb 1-1: reset full-speed USB device number 42 using xhci_hcd kernel: usb 1-1: device descriptor read/64, error -71 kernel: usb 1-1: device descriptor read/64, error -71 kernel: usb 1-1: reset full-speed USB device number 42 using xhci_hcd kernel: usb 1-1: device descriptor read/64, error -71 kernel: usb 1-1: device descriptor read/64, error -71 kernel: usb 1-1: reset full-speed USB device number 42 using xhci_hcd kernel: usb 1-1: Device not responding to setup address. kernel: usb 1-1: Device not responding to setup address. kernel: usb 1-1: device not accepting address 42, error -71 ``` then try to disable USB autosuspend. This can be done with a set of udev rules specifically for the Pinecil: ```udev SUBSYSTEM=="usb", ATTR{idVendor}=="28e9", ATTR{idProduct}=="0189", MODE:="0660" SUBSYSTEM=="usb", ATTR{idVendor}=="28e9", ATTR{idProduct}=="0189", GROUP="plugdev" SUBSYSTEM=="usb", ATTR{idVendor}=="28e9", ATTR{idProduct}=="0189", TEST=="power/control", ATTR{power/control}="on" ``` ## Windows Two Options for Windows ### Option 1: use command line ### Steps ⛔ Do not use the DC barrel jack while updating firmware or you may destroy your PC. ⛔ 1. Using command line `dfu-util` is similar to above for Linux / Mac. 2. Highly recommend updating `dfu-util` to the newest version. 3. Download and extract the firmware package from GitHub [IronOS Releases](https://github.com/Ralim/IronOS/releases). 4. Enter DFU mode: press and hold (-) button at the back of the iron (do not release). 5. Connect USB to PC, and USB-C to the back of Pinecil, keep holding (-) button down. 6. Screen will stay **black/off** to indicate the Pinecil is in DFU mode. This is normal. 7. After the USB cable is connected at both ends, wait ~10 seconds more, then release the (-) button. 8. Open PowerShell or Command window. 9. Change to the directory of the unzipped firmware files 10. Using `dfu-util,` flash the firmware using a command like this: ``` dfu-util -D Pinecil_EN.dfu ``` - If you have errors, see Troubleshooting above. ### Option 2: use the GUI tool from chip vendor ### Steps ⛔ Do not use the DC barrel jack while updating firmware or you may destroy your PC. ⛔ 1. If you are uncomfortable with the command line, then this chip vendor supplied GUI tool/drivers is an option. 2. Download and extract the firmware package from GitHub [IronOS Releases](https://github.com/Ralim/IronOS/releases). 3. Download both the `GD32 MCU DFU TOOL` and the `GD32 Dfu Drivers`. - GD32 DFU Tool [here](http://www.gd32mcu.com/en/download?kw=GD32+MCU+Dfu+Tool&lan=en). If the link breaks, search for "GD32 MCU Dfu Tool" at this [link](http://www.gd32mcu.com/en/download/). - GD32 DFU Drivers [here](http://www.gd32mcu.com/en/download?kw=GD32+Dfu+Drivers&lan=en). If the link breaks, search for "GD32 Dfu Drivers" at this [link](http://www.gd32mcu.com/en/download/). - Check properties of both downloads, tick Unblock if needed, then Unzip 4. Install the drivers and the GD32 DFU tool (ignore prompts to update the tool). 5. Enter DFU mode: press and hold (`-`) button at the back of Pinecil (do not release). 6. Connect Pinecil to a PC via USB cable (do not release the (`-`) yet). 7. Screen will stay **black/off** to indicate the Pinecil is in DFU mode. This is normal. 8. You may hear a beep from Windows as it connects to Pinecil in DFU mode. 9. If you see windows notification that it `does not recognize USB device`, then you didn't connect, repeat step 3-8. 10. Open the GD32 DFU Tool (ignore prompts to update tool). 11. At the top of the DFU tool, you should see `GD DFU DEVICE 1` appear if you successfully connected Pinecil. 12. If DFU Device box at top is blank, then Pinecil is not connected in DFU mode, repeat steps 3-11. 13. If it has been more than 10 seconds since you connected the USB cable, Release the (`-`) button. (don't use Upload from Device section) 14. Select `Download to device` > Open > Browse to folder you unzipped in step 2. 15. Select the `hex` file for language. English is Pinecil_EN.hex , tick `Verify after download`. 16. Click `OK` at bottom. After a few minutes you will see 0-100%, Download successfully! Click `Leave DFU` at the top. 17. Disconnect Pinecil cable from PC, plug it into a power supply. 18. Do not need to press any buttons, a new screen should appear. 19. To confirm upgrade, hold the minus (`-`) button down for a few seconds, it then shows new firmware version v2.xx.x....date - If you have errors, see Troubleshooting above. ================================================ FILE: Documentation/Flashing/Pinecil V2.md ================================================ # Flashing / Upgrading your iron ## Downloading source file In the development of this firmware, there are three _types_ of firmware released. These are the "Main" stable releases, which generally have high confidence in being bug free. Release candidates are released slightly more often, and these are generally perfectly fine for everyday use. These are released early to allow for translation checking and for wonderful people to help spot bugs and regressions. Finally, there are the "mainline" builds, which are built from the main git branch. These are built on every change and can be found on the Actions tab (see below). ### Main release Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases). Download the zip file that matches your model of soldering iron and extract it. Select the appropriate file type for your unit, in general Miniware devices need `.hex`, Pinecil V1 needs `.dfu`, and Pinecil V2 needs `.bin`. Flash according to details below. ### Bleeding edge / latest For the _latest_ code, you need to download the zip file from the artifacts page for the build that you want. Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch and beta you would like. In general you probably want `master`. Once you click on a run, scroll down to the "Artifacts" section and then click on your device model name to download a zip file. Then this works the same as a production release (use the correct file). ## Pinecil V2 - The MCU in Pinecil V2 is Bouffalo BL706 and does _not_ use usb-dfu for flashing as the previous Pinecil V1 MCU did. - See the Pinecil Wiki page [here](https://wiki.pine64.org/wiki/Pinecil#Firmware_&_Updates) for instructions. - The V2 uses the [BLISP flasher](https://github.com/pine64/blisp) to upload the firmware to the MCU. - The [Pinecil Wiki](https://wiki.pine64.org/wiki/Pinecil) is a great resource for all things Pinecil. - Community chat: if there are issues updating, then join the Pine64 > Pinecil channel [here](https://wiki.pine64.org/wiki/Pinecil#Live_Community_Chat). There are knowledgeable members in Discord/Telegram/Matrix. Discord has a bridge bot connection to Telegram and Matrix so that all pine64 volunteers/members can see advice for Pinecil and related items or just get tips on which power supply to purchase. - One advantage of Pinecil is that you cannot permanently damage it doing a firmware update (because BIN is in ROM); an update could render Pinecil temporarily inoperable if you flash an invalid firmware. But no worries, simply re-flashing with a working firmware copy will fix everything. - USB-C cable is required to do an update. Generally, all USB controllers work, but some hubs have issues, so it is preferred to avoid USB hubs for updates. - Background on the [BL706 chipset](https://lupyuen.github.io/articles/bl706) ### Troubleshooting If you are running into issues such as timeouts during the programming or bootloader errors, the BL702 has a not-amazing USB PHY built in. This can cause problems on cheap cables (especially "thin" ones that tend not to have shielding). One of the authors (Ralim) has found this especially common on the cables supplied with Apple chargers when used with newer Ryzen processor ports. It is _strongly_ reccomended to use a good quality cable, ideally _short_. Also try other USB ports, as on some devices they can use different hub's or lengths of signalling, and this can fix the issue. By the PinecilV2's design, by default some of the internal buses are exposed on the USB3 pins, to enable hacking/debugging/mods. This is suspected it _may_ play poorly on some chipsets. Try using a USB2.0 cable. Others have had luck with chaining USB-C->USB-A->USB-C. This may be due to this, as a lot of these adaptors are USB2 or only USB3 5gbps (half USB3 pins). Another workaround is to put a USB hub somewhere in the chain, as these will re-form the signal and can work around the issue. _Finally_, some users have reported issues under Windows that were fixed by changing OS (Typically to a Linux live cd). ================================================ FILE: Documentation/Flashing/TS100.md ================================================ # Flashing / Upgrading your iron ## Downloading source file In the development of this firmware, there are three _types_ of firmware released. These are the "Main" stable releases, which generally have high confidence in being bug free. Release candidates are released slightly more often, and these are generally perfectly fine for everyday use. These are released early to allow for translation checking and for wonderful people to help spot bugs and regressions. Finally, there are the "mainline" builds, which are built from the main git branch. These are built on every change and can be found on the Actions tab (see below). ### Main release Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases). Download the zip file that matches your model of soldering iron and extract it. Select the appropriate file type for your unit, in general Miniware devices need `.hex` and Pinecil needs `.dfu`. Flash according to details below ### Bleeding edge / latest For the _latest_ code, you will need to download the zip file from the artifacts page on the build for what you want. Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch you would like. In general you probably want `master`. Once you click on a run, scroll down to the "Artifacts" section and then click on your model to download a zip file. Then this works the same as a production release (use the correct file). # TS100 This is completely safe, but if it goes wrong just put the corresponding `.hex` file from [the official website](https://e-design.com.cn/en/NewsDetail/4203645.html) ([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)) onto the unit and you're back to the old firmware. Downloads for the `.hex` files to flash are available on the [releases page.](https://github.com/Ralim/IronOS/releases) The file you want is called TS100.zip. Inside the zip file (make sure to extract the file before flashing with it) will be a file called `TS100_{Language-Code}.hex`. Officially the bootloader on the devices only works under Windows (use the built-in File Explorer, as alternative file managers or copy handlers like Teracopy will fail). However, users have reported that it does work under [Mac](#mac), and can be made to work under [Linux](#linux) _sometimes_ (look for details below). 1. Hold the button closest to the tip (MHP30 the left button on the back), and plug in the USB to the computer. 2. The unit will appear as a USB drive. (Screen will say `DFU` on it.) 3. Drag the `.hex` file onto the USB drive. 4. The unit will disconnect and reconnect. 5. The filename will have changed to end in _.RDY_ or _.ERR_ 6. If it ends with _.RDY_ you're done! Otherwise, something went wrong. 7. If it didn't work the first time, try copying the file again without disconnecting the device, often it will work on the second shot. 8. Disconnect the USB and power up the device. You're good to go. For the more adventurous out there, you can also load this firmware onto the device using an SWD programmer, for easier installation follow the guide at the end of this document. On the bottom of the MCU riser PCB, there are 4 pads for programming. On v2.51A PCB revision `USB_D+` is shorted to `SWDIO` and `USB_D-` is shorted to `SWCLK` so debugging works without disassembly (attach while staying in the bootloader). Installing [IronOS-dfu](https://github.com/Ralim/IronOS-dfu) is recommended as it allows reliable flashing of binary files with [dfu-util](http://dfu-util.sourceforge.net/). On some newer TS100 units, the SWD pins are wired up to the USB pins, on older ones they are not sadly. ## Mac sgr1ff1n (Shane) commented in [issue 11](https://github.com/Ralim/IronOS/issues/11) that upgrading worked on their Mac as per normal: > I just wanted to say that I was able to update the firmware on my ts100 from the stock version to 1.08 found in this repository using my Mac. I simply followed the same steps however through Finder. I have a MacBook Pro (13-inch, Mid 2012) running Sierra 10.12.4 (16E195). ## Linux While in the past there were reports of unreliable upgrades, the consensus in [issue 11](https://github.com/Ralim/IronOS/issues/11) is that things work mostly as expected in Linux. @awigen has contributed a script [flash_ts10X_linux.sh](https://raw.githubusercontent.com/Ralim/IronOS/dev/scripts/flash_ts10X_linux.sh) that works on Ubuntu 16.04 as well as other distros. If you want to do it manually (or if the script does not work for some reason) the general procedure is the same as for Windows, the differences are in the way to mount the unit and copy the firmware. Remember that after flashing, the firmware filename will have changed to end in `.RDY` or `.ERR` or `.NOT` and only `.RDY` means the flashing was successful! - The unit has to be mounted as `msdos` type (thanks @balrog-kun for having spotted it). You may disable automount, but unmounting the automounted drive and remounting as `msdos` works fine. You do not need to turn off automounting, but you do need to unmount the device with `umount`. - It is recommended to use an all-caps filename for the firmware, even if successful flashing were done with lower case names. - Avoid USB hubs, plug directly in your computer. - If it fails, try again several times without unplugging. Just let it remount. Example, to be run as root, once the unit has been plugged in DFU mode and auto-mounted: ```bash FW=ts100.hex unset NAME eval $(lsblk -P -p -d --output NAME,MODEL|grep "DFU[ _]Disk") [ -z ${NAME+x} ] && exit 1 # Could not find DFU device umount "$NAME" mkdir /tmp/mntdfu mount -t msdos "$NAME" /tmp/mntdfu cp "$FW" "/tmp/mntdfu/$(basename $FW|tr a-z A-Z)" sync umount /tmp/mntdfu rmdir /tmp/mntdfu ``` Device will reboot and automount will rerun if not disabled. Check the extension of your firmware, it should be `.RDY` now. ## FAQ #### The file is showing up with the extension `.ERR` This can occur during the programming process if any of the checks in the bootloader fail. This is often triggered by anti-virus software or using a non-Windows host OS. First, try just copying the file a second time. 1. Attach the iron in DFU mode. 2. Copy the `.hex` file to the device. 3. The device disconnects and connects with the `.ERR` file. 4. Copy the same `.hex` file again **⛔ DO NOT TRY AND DELETE THE OLD ONE ⛔**. 5. The device will disconnect and reconnect again. 6. The device _should_ now have the `.RDY` file. 7. You're done. If this fails and you are on Mac or Linux reading the wiki page about programming can help. There is also a very long issue thread going through all of the different attempts around this too. If you are on Windows, it's often best to try another computer (friends, work, partners etc.). #### Device randomly disconnects or does not show up in DFU mode 1. Check if the USB cable you are using has the data pins; test it on another device. There are a surprisingly large number of micro-USB cables that are power _only_. 2. Try other USB ports. Often different USB controllers will interact with the units differently due to design quirks in the Miniware design. ### Alternative bootloader If you are an advanced user, and you have used `usb-dfu` tools before, or you would like to learn; there is an alternative bootloader for these irons. This will **NOT** show up as a USB storage drive, but instead show up using a standard DFU protocol device. You can then use dfu tools or GUIs to upgrade the iron using the `.bin` files that are posted to the releases page. To install this alternative bootloader, follow the instructions [here](https://github.com/Ralim/IronOS-dfu/blob/mainline/docs/Bootloader.md). Note that this is only recommended for users who know what they are doing. If you don't understand how this works, please don't flash this. ================================================ FILE: Documentation/Flashing/TS80(P).md ================================================ # Flashing / Upgrading your iron ## Downloading source file In the development of this firmware, there are three _types_ of firmware released. These are the "Main" stable releases, which generally have high confidence in being bug free. Release candidates are released slightly more often, and these are generally perfectly fine for everyday use. These are released early to allow for translation checking and for wonderful people to help spot bugs and regressions. Finally, there are the "mainline" builds, which are built from the main git branch. These are built on every change and can be found on the Actions tab (see below). ### Main release Main releases are made to the [releases page](https://github.com/Ralim/IronOS/releases). Download the zip file that matches your model of soldering iron and extract it. Select the appropriate file type for your unit, in general Miniware devices need `.hex` and Pinecil needs `.dfu`. Flash according to details below ### Bleeding edge / latest For the _latest_ code, you will need to download the zip file from the artifacts page on the build for what you want. Head to the [Actions](https://github.com/Ralim/IronOS/actions) page and then select the run for the appropriate branch you would like. In general you probably want `master`. Once you click on a run, scroll down to the "Artifacts" section and then click on your model to download a zip file. Then this works the same as a production release (use the correct file). # TS80 / TS80P This is completely safe, but if it goes wrong just put the corresponding `.hex` file from [the official website](https://e-design.com.cn/en/NewsDetail/4203645.html) ([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)) onto the unit and you're back to the old firmware. Downloads for the `.hex` files to flash are available on the [releases page.](https://github.com/Ralim/IronOS/releases) The file you want is called TS80.zip or TS80P.zip. Inside the zip file (make sure to extract the file before flashing with it) will be a file called `TS80_{Language-Code}.hex`/`TS80P_{Language-Code}.hex`. Officially the bootloader on the devices only works under Windows (use the built-in File Explorer, as alternative file managers or copy handlers like Teracopy will fail). However, users have reported that it does work under [Mac](#mac), and can be made to work under [Linux](#linux) _sometimes_ (look for details below). 1. Hold the button closest to the tip (MHP30 the left button on the back), and plug in the USB to the computer. 2. The unit will appear as a USB drive. (Screen will say `DFU` on it.) 3. Drag the `.hex` file onto the USB drive. 4. The unit will disconnect and reconnect. 5. The filename will have changed to end in _.RDY_ or _.ERR_ 6. If it ends with _.RDY_ you're done! Otherwise, something went wrong. 7. If it didn't work the first time, try copying the file again without disconnecting the device, often it will work on the second shot. 8. Disconnect the USB and power up the device. You're good to go. If you get a message when copying: "Are you sure you want to move this file without its properties?" then this can cause an issue where the iron thinks that the file has finished copying before it actually has and can cause a .ERR file. Since this dialog prompt is caused by copying a file from NTFS to FAT (the iron's filesystem) in windows, you can fix this by formatting a thumbdrive as FAT32 and then storing the hex file on that before copying the file to the iron. As there will be no NTFS properties on the file when stored on a FAT32 filesystem, there will be no prompt, and the copy will then proceed normally. For the more adventurous out there, you can also load this firmware onto the device using an SWD programmer, for easier installation follow the guide at the end of this document. On the USB port, `USB_D+` is shorted to `SWDIO` and `USB_D-` is shorted to `SWCLK` so debugging works without disassembly (attach while staying in the bootloader). Installing [IronOS-dfu](https://github.com/Ralim/IronOS-dfu) is recommended as it allows reliable flashing of binary files with [dfu-util](http://dfu-util.sourceforge.net/). ## Mac sgr1ff1n (Shane) commented in [issue 11](https://github.com/Ralim/IronOS/issues/11) that upgrading worked on their Mac as per normal: > I just wanted to say that I was able to update the firmware on my TS100 from the stock version to 1.08 found in this repository using my Mac. I simply followed the same steps however through Finder. I have a MacBook Pro (13-inch, Mid 2012) running Sierra 10.12.4 (16E195). ## Linux While in the past there were reports of unreliable upgrades, the consensus in [issue 11](https://github.com/Ralim/IronOS/issues/11) is that things work mostly as expected in Linux. @awigen has contributed a script [flash_TS100_linux.sh](https://raw.githubusercontent.com/Ralim/IronOS/master/Flashing/flash_TS100_linux.sh) that works on Ubuntu 16.04 as well as other distros. If you want to do it manually (or if the script does not work for some reason) the general procedure is the same as for Windows, the differences are in the way to mount the unit and copy the firmware. Remember that after flashing, the firmware filename will have changed to end in `.RDY` or `.ERR` or `.NOT` and only `.RDY` means the flashing was successful! - The unit has to be mounted as `msdos` type (thanks @balrog-kun for having spotted it). You may disable automount, but unmounting the automounted drive and remounting as `msdos` works fine. You do not need to turn off automounting, but you do need to unmount the device with `umount`. - It is recommended to use an all-caps filename for the firmware, even if successful flashing were done with lower case names. - Avoid USB hubs, plug directly in your computer. - If it fails, try again several times without unplugging. Just let it remount. Example, to be run as root, once the unit has been plugged in DFU mode and auto-mounted: ```bash FW=TS80.hex unset NAME eval $(lsblk -P -p -d --output NAME,MODEL|grep "DFU[ _]Disk") [ -z ${NAME+x} ] && exit 1 # Could not find DFU device umount "$NAME" mkdir /tmp/mntdfu mount -t msdos "$NAME" /tmp/mntdfu cp "$FW" "/tmp/mntdfu/$(basename $FW|tr a-z A-Z)" sync umount /tmp/mntdfu rmdir /tmp/mntdfu ``` Device will reboot and automount will rerun if not disabled. Check the extension of your firmware, it should be `.RDY` now. ## FAQ #### The file is showing up with the extension `.ERR` This can occur during the programming process if any of the checks in the bootloader fail. This is often triggered by anti-virus software or using a non-Windows host OS. First, try just copying the file a second time. 1. Attach the iron in DFU mode. 2. Copy the `.hex` file to the device. 3. The device disconnects and connects with the `.ERR` file. 4. Copy the same `.hex` file again **⛔ DO NOT TRY AND DELETE THE OLD ONE ⛔**. 5. The device will disconnect and reconnect again. 6. The device _should_ now have the `.RDY` file. 7. You're done. If this fails and you are on Mac or Linux reading the wiki page about programming can help. There is also a very long issue thread going through all of the different attempts around this too. If you are on Windows, it's often best to try another computer (friends, work, partners etc.). #### Device randomly disconnects or does not show up in DFU mode 1. Check if the USB cable you are using has the data pins; test it on another device. There are a surprisingly large number of micro-USB cables that are power _only_. 2. Try other USB ports. Often different USB controllers will interact with the units differently due to design quirks in the Miniware design. ### Alternative bootloader If you are an advanced user, and you have used `usb-dfu` tools before, or you would like to learn; there is an alternative bootloader for these irons. This will **NOT** show up as a USB storage drive, but instead show up using a standard DFU protocol device. You can then use dfu tools or GUIs to upgrade the iron using the `.bin` files that are posted to the releases page. To install this alternative bootloader, follow the instructions [here](https://github.com/Ralim/IronOS-dfu/blob/mainline/docs/Bootloader.md). Note that this is only recommended for users who know what they are doing. If you don't understand how this works, please don't flash this. ================================================ FILE: Documentation/GettingStarted.md ================================================ # Getting Started Getting started with IronOS on your Pinecil/TS80/TS80P/TS100. If your device did not come with IronOS already installed, or if you need to update to the latest version; please see the flashing guide for your device: - [MHP30](https://ralim.github.io/IronOS/Flashing/MHP30) - [Pinecil V1](https://ralim.github.io/IronOS/Flashing/Pinecil%20V1/) - [Pinecil V2](https://ralim.github.io/IronOS/Flashing/Pinecil%20V2/) - [TS80 / TS80P](https://ralim.github.io/IronOS/Flashing/TS80%28P%29/) - [TS100](https://ralim.github.io/IronOS/Flashing/TS100) It is recommended to update to the newest stable release when you first receive your device to ensure you are up to date. Once your Iron has been flashed, on first power on it _may_ warn you about the system settings being reset. _Do not panic_; this is 100% completely normal. This is here to note to you that they have been reset to handle the internal structure changing. If you receive a warning about the accelerometer or USB-PD not being detected, please see [here](https://ralim.github.io/IronOS/HardwareIssues/). ## The Home screen (or idle screen) This is the landing page of the firmware, from here you can choose to either go into the [settings menu](#Settings-Menu) or go into [soldering mode](#Soldering-Mode). By default this will show a screen similar to the one below: ![Home Screen](https://raw.githubusercontent.com/Ralim/IronOS/dev/Documentation/images/HomeScreen.png) Note that this may be drawn mirrored depending on the orientation of your screen (detailed mode shows a different home screen). The soldering iron symbol on the screen will appear near the tip. This is here to indicate that pressing the button closest to the front of the iron will enter soldering mode. And naturally, the slider controls icon (or spanner icon in older versions) represents that pressing the button near the rear of the soldering iron will enter the settings menu. In the settings, you can turn on a detailed idle screen instead. The buttons still function the same, however, the image will be swapped for a text telling you the current status of the iron with extra details. Depending on how your device is being powered, at right side of the screen, the firmware will either show the voltage your unit is being provided with, a battery icon (if battery mode is enabled) or a power plug icon. If you see an (**X**) where the soldering iron should be, this indicates that the firmware can't see the tip connected. This could indicate a problem with the iron or tip. First, try removing the tip screw and tip and gently reinstalling both; ensure that the tip is seated all the way back. If the issue persists please see the [hardware issues section](https://ralim.github.io/IronOS/HardwareIssues/). This OLED screen features burn-in protection; if no buttons or movement have been detected for a while it will automatically blank the screen to reduce burn-in when the iron is left unattended. Any movement or button press will wake the screen. ### Hidden Extras Additionally to the two icons shown, there are two "hidden" actions that can be performed on this menu. On devices that do not support profile mode, if you press and hold the button near the tip (`+/A`), this enters the temperature adjustment screen. Normally this is not required; but if you would like to adjust the set temperature _before_ the tip starts to heat, this can be useful. If you press and hold the button near the rear of the iron (`-/B`), it will take you into the [debug menu](https://ralim.github.io/IronOS/DebugMenu/). ## Soldering Mode When you press the button to enter the soldering mode, the iron will instantly start to heat up the tip. The firmware defaults to 320 °C as the set point for the soldering mode, however on this screen you can enter into the adjustment screen by pressing either button. Pressing and holding the button near the tip will enter **Boost** mode. This allows a temporary override of the set temperature to a higher (or lower) value. This can be useful as a way to force the tip to a higher temperature to drive more wattage into a large joint when the thermal connection is not ideal. Pressing and holding the rear button will exit soldering mode and land you back at the home screen. You can also do this by pressing both buttons at once and this will also work, this is a bit harder to do but is kept for compatibility with the Miniware firmware. Pressing and holding **both** buttons at once will enter locked mode, which will prevent the buttons from doing anything. You can in the settings allow boost mode in locked mode optionally. This can be useful if you find yourself hitting the buttons and entering into the temperature adjustment screen by accident. ### Idle Sleep If the iron detects a period of time without any significant movement, it will enter sleep mode. This is indicated with a screen graphic similar to Zzzz (or text in detailed mode). In Sleep mode, the temperature of the iron automatically lowers to 150 °C (default), which is just below the melting point of the solder. This helps reduce rate of oxidation and damage to the iron tip. In general, when not using the iron, unplug it or let it sleep to increase the longevity of replaceable tips. The default sleep temperature can be customized. Simply picking up or moving the iron will wake it back up into soldering mode. You can also press any button and this will also wake the iron up. #### Optional Hall Effect Feature (Pinecil only): Pinecil has an unpopulated footprint (U14) for a hall effect sensor (Si7210-B-00-IV). Adding the sensor and placing a neodymium magnet on the holder stand will trigger Pinecil to sleep after it enters the stand, and Zzzz will appear on-screen. The magnet is positioned on the stand in proximity to the sensor/handle which then activates one of 10 user defined settings (0=off, 1=lowest sensitivity, 9=highest sensitivity). Read the Hall Sensor document for [details on installation](https://ralim.github.io/IronOS/HallSensor/). ### Idle Shutdown If, after entering sleep mode, the iron still does not see movement for a much longer time (default=10 minutes); it will shut down and return to the home screen. ## Profile Mode (MHP30 only) On devices that support it, a long press on `(+/A)` takes you into profile mode, which initiates the profile selected in the relevant settings. Profile mode plays out as follows: 1. Check if the temperature is below 55C. If not, you will get a warning and cannot enter profile mode. 2. Preheat by raising the target temperature to the configured preheat temperature with the configured preheat speed. 3. Wait for the device to reach the preheat temperature. 4. Gradually move the target temperature to the configured end temperature of the first phase over the configured duration. 5. Wait for the device to reach the end temperature. 6. Repeat steps 4 and 5 for the next phases until there are no more phases configured. 7. Cool down by lowering the target temperature to 0 with the configured cooldown speed. 8. Once the temperature is below 55C, sound the buzzer (if available) and exit profile mode. You can manually exit profile mode manually in the same way as the soldering mode, by pressing and holding the rear button or pressing both buttons at once. ## Settings Menu The settings menu is the most evolving aspect of the firmware, so each option is not documented here. However, do not panic, as every menu option has an on-screen description so you don't _need_ to come back here to figure them all out. To navigate the menu, the two buttons act separately. The rear button (`-/B`) is pressed to enter the menu and scrolls down the main options, and the other front button (`+/A`) will enter and change the current option. To see a description of an option, just wait, and after a few seconds, it will scroll across the screen. The menu is comprised of a 'main menu' of categories and then sub-items that allow you to adjust parameters. You can long hold buttons to change through options faster, and there is some acceleration when holding the buttons. There is a small scrollbar that appears along the right edge of the screen to indicate how far through the current list you are (looks like a dot). Additionally, this scrollbar will blink rapidly when you are on the last value in a range of a sub-menu. For example, if you are in Motion Sensitivity, which has a range of 0 - 9, it will blink when you are at 9. I highly recommend taking a few minutes to go through all of the options in the menu to get a feel for what you can change, almost every aspect of the internal system is adjustable to suit your needs. If you want to start over, simply go to Advanced settings > Restore default settings, confirm using the front (`+/A`) button. This sets all menu items to defaults, and keeps the same version firmware. ================================================ FILE: Documentation/HallSensor.md ================================================ # Hall Effect Sensor ## Sleep Mode Menu In sleep mode, the iron automatically lowers the temperature to 150°C (default). This default setting was chosen as it is just below the melting point of a wide range of solders. A lower standby temperature helps reduce the oxidation rate and prevent damage to the soldering tips. As a general rule, when not in use, unplug the unit or let it go into sleep mode to extend the life of the replaceable tips. The default sleep temperature can be adjusted to your preference. Simply moving the iron or pressing any button will wake it back up into soldering mode. The sensitivity is adjustable. It is recommended to adjust this to suit your environment so that it reliably stays in sleep mode when not in use, but does not go into sleep mode when in use. (This may vary depending on the amount of movement during soldering.) ### Optional Hall Effect Feature (Pinecil (v1/v2) only): Inside the [Sleep Menu](https://ralim.github.io/IronOS/Settings/#setting-sleep-temp) is an additional type of sleep setting. Pinecil has an unpopulated footprint (**U14**) for a hall effect sensor, Silicon Labs **Si7210-B-00-IV**. After installing the hall effect sensor (HES), it is possible to auto-trigger Pinecil to enter sleep mode when it enters the stand, and _Zzzz_ will appear (or text in detailed mode). This could be a fun enhancement for any Pinecil and adds a feature typically only found in more expensive high-end irons. The HES is available at many electronic stores for ~$2-$6. After installing the HES on the PCB, place a magnet on the stand close enough to the sensor to activate one of ten user selectable settings. - 0=off, 1=1000, 2=750, 3=500, 4=250, 5=150, 6=100, 7=75, 8=50, 9=25 (9 has the highest sensitivity to magnets) - Setting of 1 might be used if you solder on PCBs with magnets and do not wish Pinecil to auto-sleep constantly. A very strong/large magnet would be required on the stand to activate the sleep mode if you use setting 1. - Setting of 9 would be useful if you only had a small magnet and are not concerned about Pinecil falsely triggering sleep mode near magnetized items/tools. - Actively watch the _hall_ number change while you slowly move the magnet around to seek the best locations & whether you have too many or too few magnets. Position the magnet(s) where you have the highest hall number will ensure consistent sleep mode when you place the iron in the stand. This requires some experimenting. - [See debug menu for how to display the _Hall_ number](https://ralim.github.io/IronOS/DebugMenu/) - Note that the sensor is physically located near the copper contacts for the tip at the front of the handle. [Reference Schematics U14](https://files.pine64.org/doc/Pinecil/Pinecil_schematic_v1.0a_20201120.pdf). - Neodymium magnets are recommended. If using small magnets, 2-3 may be required, but too many could also be detrimental. - Positioning/type/quantity of magnets is important for best results. Sometimes too many magnets breaks the effect by distorting the magnetic field **[as seen in this demo video](https://www.youtube.com/shorts/afkqKwCX00I)**. The video shows magnets at the top of the stand, and the pinecil goes correctly into Zzzz with _only_ those magnets. When more magnets are added at the side, the Pinecil did not go to sleep, which is contrary to the goal. See the PDF below for details on magnetic fields with SI7210-B. - Orientation of North and South faces of magnets is important to increase reaction of the hall sensor [see data sheet SI7210-B-00-IV](https://www.silabs.com/documents/public/application-notes/an1018-si72xx-sensors.pdf). ================================================ FILE: Documentation/Hardware.md ================================================ ## Notes on the various supported hardware Below are short summaries / notes around the hardware. This is not an in-depth comparison of the features of the units. Please do your own research before purchasing. Due to descisions out of our control, Miniware no longer provides source-code/schematics/support for any open source firmware on their devices. This does mean that only (TS100/TS80/TS80P) are "open" to any extent. TS80P is pushing that as it was never open at all but just happens to be very close to the TS80. While this generally shouldn't affect the performance of the device, it does mean that their newer products can be slow to be supported or some issues are harder to resolve. Sequre has so far been supportive of the S60 by providing schematics. The Pine64 units (Pinecil) are schematics-available (i.e you can download them on the Pine64 Wiki). They are currently the only vendor that has provided financial support of the project. They are also the only vendor that allows contact directly to the engineering teams for hardware issues. This results in generally better support for these devices. It does **not** mean that this firmware is designed around them, but it does help however that they are designed with this firmware in mind as Ralim talks to them. Where possible features are designed to work across all devices but the time for support may vary depending on the hardware and its quirks. ## A quick note on power supplies For all devices listed **except** the MHP30: These soldering irons do *NOT* contain DC/DC converters. This means that your power at the tip is a function of the supplied voltage. Just because the iron "supports" running at a wide range of voltages, you should always use a voltage near the upper limit where possible. It is highly recommended to use a PD adapter where possible as this allows the iron to _know_ the limitations of your supply. The marked irons can only turn the tip on and off in software, this means that they can't control the maximum power drawn from the supply. This is why when using PD the iron may select a lower voltage than your power supplies maximum. This is to prevent your power supply failing from over current. For more information about power management underhood, please, [see the related documentation section](https://ralim.github.io/IronOS/Power/). For the MHP30, it contains a buck DC/DC, which means it can utilise most power supplies fairly well, but you should still aim for highest voltage that is reasonable to use. ### TS100 The TS100 was the first supported soldering iron, and is generally a very capable device. Its now generally not reccomended to buy new as other devices have all of its features and more, and can often be the same price or cheaper. It's still fully supported though, nothing will be taken away from it. - can run from 9-25V DC; - provides a power range that is determined by the input voltage; - voltages below 12V don't overly work well for any substantial mass; - the original firmware can be found [here](https://e-design.com.cn/en/NewsDetail/4203645.html)([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)). ![](https://brushlesswhoop.com/images/ts100-og.jpg) ### TS101 The TS101 is the direct replacement of the TS100 with the same tip compatibility. It adds a spring pressure tip holding mechanism instead of using a screw so tips are easier to swap on the fly (But are held less securely and can pull out depending on the use case). It adds USB-C PD support and the hardware is compatible with 28V EPR power supplies (under both IronOS and official firmware). It unfortunately uses an STM32 clone MCU with quirks, so performance of the screen isn't as good as it could be but its perfectly usable. The bootloader for programming is the biggest weakness of this device and programming can be a pain. Fortunately, IronOS is relatively stable feature wise, so you shouldn't need to update the device often. The Miniware bootup logo is burned into their bootloader, so IronOS cant remove this. IronOS can show your own logo when it starts however. There are quirks to loading a logo on this device, so be sure to read the documentation if you are coming from other devices. ### TS80 TS80 is a successor to TS100, it moves to custom smaller tips that perform better at lower wattages. It is optimised for a 9V/2A Quick Charge 3.0 power supply. This is commonly found on older power banks on the USB-A port. It does **not** support USB-PD and will not work when powered from a USB-C power supply in most cases. - uses _Quick Charge 3.0_ / _QC3_ capable charger only (18W max); - doesn't support PD as it is not designed on the hardware level; - the original firmware can be found [here](https://e-design.com.cn/en/NewsDetail/4203645.html)([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)). ![Image of TS80](https://core-electronics.com.au/media/catalog/product/4/2/4244-01.jpg) ### TS80P The TS80P is the direct successor to the TS80 and essentially what the TS80 should have been from its debut. It is nearly identical except it adds USB-PD support for far better compatibility with modern power banks as well as a faster tip removal method. - supports _Quick Charge 3.0_ (_QC3_: 9V/2A,12V/1.5A 18W max); - supports _Power Delivery_ (_PD_: 9V/3A & 12V/3A, 30W max)\*\*; - the original firmware can be found [here](https://e-design.com.cn/en/NewsDetail/4203645.html)([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)). \*\*: use valid PD device that supports 12V/3A as power source to get full 30W potential, otherwise the iron will fall back to 9V/18W power mode. ![](https://static.eleshop.nl/mage/media/catalog/product/cache/10/image/800x/040ec09b1e35df139433887a97daa66f/s/-/s-l1600_5.jpg) ### MHP30 MHP30 is a **M**ini **H**ot **P**late: - accelerometer is the MSA301, this is mounted roughly in the middle of the unit; - USB-PD is using the FUSB302; - the hardware I2C bus on PB6/7 is used for the MSA301 and FUSB302; - the OLED is the same SSD1306 as everything else, but it’s on a bit-banged bus; - the original firmware can be found [here](https://e-design.com.cn/en/NewsDetail/4203645.html)([mirror backup](https://github.com/Ralim/IronOS-Meta/tree/main/Firmware/Miniware)). ### Pinecil Pincecil: - first model of soldering iron from PINE64; - the default firmware can be found [here](https://files.pine64.org/os/Pinecil/Pinecil_firmware_20201115.zip). ![](https://pine64.com/wp-content/uploads/2020/11/pinecil-bb2-04.jpg?v=0446c16e2e66) ================================================ FILE: Documentation/HardwareIssues.md ================================================ # Hardware Issues While we would love everything to work perfectly, sometimes that just doesn't happen. Please do not email maintainers directly, these will generally be ignored. Keep issue discussions to GitHub issues or the discussions page so that the whole community can help and work together. ## No Accelerometer detected If your iron was previously working, this could be a bug (and we are very sorry). Please check the currently open and recently closed issues to check if anyone else has run into this. You can try going back to a release on the firmware to test if this is a new issue before opening an issue. If this is a new iron, also feel free to open an issue if you don't see any; a vendor _could_ have changed the model of the accelerometer on us without warning _again_. In which case, support should come shortly. If your iron is new, there is a slim chance your accelerometer may be DOA and need replacement. **Note this warning will only be shown the first few times until settings are reset** ## No USB-PD IC detected Generally, this means either something went very awry in the firmware, or the chip is not answering as would normally be expected. Try rolling back to an earlier release to confirm if the issue still persists then the device may need repair. If you have some form of seller protection/support, you most likely want to reach out to this to be safe. If you don't, you can always attempt to replace the IC yourself. As of writing both the TS80P and Pinecil use the FUSB302. **Note this warning will only be shown the first few times until settings are reset** ## No tip detected If your tip is not being detected, the most likely cause is that the heater element inside the tip has been damaged from over-temperature, being dropped or bad luck. As the heater coil is part of the temperature measurement circuit neither will work if it's damaged. The best way to see if this is the case is to measure the resistance across the contacts to the tip using a multimeter. you are expecting to see measurements in the range of 4-10 ohms. Anything higher than 10 ohms is _generally_ an issue. ## Iron will not heat up and displays a high temperature Check the Rtip and CHan numbers ([see debug menu](https://ralim.github.io/IronOS/DebugMenu/)). Extremly high CHan is suspect to a problem with the cold junction compensation temperature sensor. For Pinecil V1, inspect near U10 which is the TMP36 sensor ([see issue here](https://github.com/Ralim/IronOS/issues/1234)). You may be able to reflow/resolder the TMP36 chip at U10 to correct a weak solder joint. If it worked on older firmware, but not on 2.16+, weak solder joints are suspect. The newer firmware runs the ADC a bit faster to keep tighter control of the tip temperature. Normally this wont cause an issue as the output from the TMP36 is powerful enough to keep up without any issue. But if you have a weak or cold solder joint this could cause issues. If the CHan is extremely high, and reflowing the temperature sensor does not resolve the issue; inspect the pins in the main MCU, possibly try giving them a light squeeze to the board while watching CHan. If you have a different device, follow the same logic and locate the temperature sensor on your device. ================================================ FILE: Documentation/History.md ================================================ # Version Changes ## v2.23 ### High level changes - Miniware I2C changed to bit-bang for improved compatibility with newer devices with STM32 clone IC's - Looping Boot Logo option (loops until button press) - More fixes for GD32 clones with Miniware devices - Bluetooth BLE is off by default (security) - Large internal code refactoring to make the screen drawing more flexible for larger OLEDs - Further improvements to drawing on larger screen resolutions - 4 Ohm tip support on Pinecil 1/2 + TS10x (Note this is at your own risk, not all hardware is designed for this) - Fixes for PPS mode on some USB-PD supplies - Rework of thermal runaway detection - Fixes to the ID numbers used for operating modes over BLE - Rework of the I2C on PinecilV2 to remove issues with temperature regulation and screen glitching - Default for USB-PD negotiation changed to use "safe" profile, to be conservative in selecting voltages. - Fixes for USB-PD to implement device capabilites. This should fix unit reboot issues with some laptops - Looots of translation & documentation updates ❤️ - Fixes for RTOS issues / updated FreeRTOS version - Multiple fixes for _MHP30_ to help with clone STM32's - Share missing settings over _BLE_ for _Pinecil V2_ - Add code for `ws2812b` LED mod for _Pinecil V2_ (Must be hand compiled). - Add option to swap A/B buttons in Settings menu - Disable _"double slide"_ animation between home and soldering screens if detailed view is set for both modes. ## v2.22 ### New Hardware Support #### Sequre S60 The [Sequre S60](https://sequremall.com/products/sequre-s60-nano-electric-soldering-iron-support-pd-qc-power-supply-compatible-with-c210-soldering-iron-tips-precision-electronic-mobile-phone-repair-tool-anti-static-soldering-pen?variant=42361945096380) uses JBC tips, which makes it quite useful for the smaller tip types and extra options available. #### TS101 The TS101 is the evolution of the TS100, picking up USB-PD. It has otherwise similar tip support to the TS100/Pinecil/PinecilV2. Absolutely massive kudos goes to @VioletEternity for her work on the reverse engineering of this. If you at all are helped by IronOS running on this device more credit goes to her than to I. Also big thanks to @whitequark for organising + supporting + magic. ### Features & changes #### PinecilV2 notes 1. BLE is fixed on all devices. 2. Bootup Logo support is finalised and working. 3. Improved the tip control, improving accuracy and remove most oscillations. #### Profile heating mode for MHP30 This lets you define a heat profile and run this profile akin to a proper reflow device. This can be used on the MHP30 by long-holding the A button (aka start button). Profile can be edited in settings. #### Note on newer OLED's To prevent this release being held up forever, the TS101 and S60 are being released with a limitation on the OLED screen. The current code will only draw to the upper left corner of the screen. Assets have been made for rendering this at full size, but the code is not complete yet. #### Smaller updates - Filtering added to MHP tilt-exit to make it less sensitive - Warning if a tip is detected to be shorted (TS101 + PinecilV2) - Translation updates ❤️ - Documentation updates - Lots of tooling and code cleanups ## v2.21 ### Features & changes - Bluetooth Low Energy support for PinecilV2 - Large cleanup of translation files; and refactor of how we handle fonts for translations - Fixes for I2C corruption on PinecilV2 - Option for using adjustable profiles on USB-PD or not - Cleanups and improvements to the generated [documents website](https://ralim.github.io/IronOS) ### PinecilV2 notes For Pinecil V2 users blisp is currently my recommended CLI tool for updating the device. It is built for all main OS's automatically. This does not apply to V1 devices. If your iron came with a blue grip, its a V1 and update the same as always. If your device came with a green silicone grip its a V2 device. Alternatively you can use Spagett1's PineFlash tool that should provide a GUI interface for PinecilV1 & PinecilV2. For a small number of V2 Pinecil devices there appears to be an interference issue between the Bluetooth Low Energy and some devices; more information here. If this occurs to you, please let us know in the issue and rollback to 2.20 for now. ## v2.20 - First "full" release for PinecilV2 - Loots of documentation updates - Documentation is [now nicely readable as a site](https://ralim.github.io/IronOS/GettingStarted) - A fair collection of bugfixes for PinecilV2 - Cold Junction Calibration was reworked and now occurs _at next boot_ to make it easier to perform when the device is cold ## v2.19 - Bug-fix Infinite Boot Logo - Shutdown settings for MHP30 - Accelerometer sensitivity for MHP30 - Allow showing unique device ID - Bug-fix chance of a power pulse at device boot - Updated translations - Improved documents, added features table ## v2.18 - Support for animated bootup logo's - Bootup logo's moved to their own IronOS-Meta repo - New Vietnamese translation (limited due to screen size) - Fixes for SC7A20 in TS80(P) - Updated translations - Better Instructions/documents ## v2.17 ### Features & changes - Indicate status of VBus for modding Pinecil (debug menu) - Better hall effect sensor sensitivity adjustment (larger range with more steps) - Temperature increment will "round" to nearest multiple of increase amount - Build setup migrated to Alpine (You can now build in docker easily, and on PinePhone/PinePhonePro) - -> Removed proprietary compiler for Pinecil RISCV now all uses normal gcc - -> Removed using the arm specific build of gcc for the one that alpine ships (Miniware devices) - Logo generator python script creates `.dfu` files for ease of use with Pinecil - Upgrades to translations - Support for new GD32103 based TS100 units turning up on the market - Raw hall effect reading now shows in the Pinecil debug menu - Fixed automatic orientation for newer TS80P's with the SC7 accelerometer - User interface slight changes - New `metadata.zip` file to allow the Pine Updater to automatically fetch information on releases ### Notes - VBus mod detection may not play well with all PPS chargers. If your iron reboots when you view this in the debug menu its not a fault. ([#1226](https://github.com/Ralim/IronOS/issues/1226)) - `metadata.zip` is only designed for use by automatic software, ignore it for normal use - More details on Pinecil VBus mod coming via other channels. - Hall effect sensor is not fitted to Pinecil's by default, you have to fit this yourself if you want the feature - Tweaks to the Accelerometer code means the drivers are slightly more fussy. If you run into any issues let us know in the discussion or issues. - -> Release has been updated to build `e065be3` after one bug with the BMA223 was found. ## v2.16 - Overhaul of the Timer+ADC setup with help from @sandmanRO - Overhaul of the PID with help from @sandmanRO - Settings _should_ now upgrade in place to future versions, with resets only happening to new/changed settings - Shows error if tip runaway (failed temperature sensor) is detected - USB-PD now has a timeout, to allow forcing QC3 negotiation to start faster - QC3 Voltages are now adjustable to user desired setpoint - Added a small tolerance to allow "overvoltage" on QC3 above unit specifications. - Please note: Doing this is entirely at your own risk! - New Advanced view that is much nicer to use and a very good daily driver option from @Mel-kior - OLED brightness and contrast thanks to @alvinhochun - Scrollbar is fixed so it doesnt jump around when menus are shown/hidden - Moved to `.dfu` files from `.bin` to make flashing commands easier - Every language had translation updates I believe - Romanian language added ## v2.15 ### Features & changes - MHP30 support - Multi-lingual firmware combinations now exist for Pinecil - More fine grained voltage controlled options - USB-PD improvements (version one and two) - More configuration options for power pulse - All font / character encoding has been very reworked - More translation updates than one can count - More languages 😱 ### MHP30 support The MHP30 is a small reflow station from Miniware. Thanks to a massive amount of help from @g3gg0 this firmware brings the beginnings of support for this unit. Also kudo's to @Vinigas and @GoJian for helping with testing. This is not a _final_ version I'm sure, but this is a working, usable version of firmware support. Programs the same as any one Miniware unit using drag and drop. **Note: The boot logo scripts will need updates for this unit, so not supported yet.** The flood doors are now open for feature requests for this unit :) ## v2.14 - Fixing auto rotation bug in the LIS accelerometer in the TS80/TS80P - Adds support for two new accelerometers -- SC7A20 (Future Pinecil batch) #786 -- MSA301 (Newer TS80P) #761 - Add warnings if accelerometer or USB-PD IC's are not detected #752 -- Only shows for first few boots, to help catch unsupported models - Fixed cooling down blink to be sane speed #769 - Cleanup of threads and slightly faster power negotiation #790 - Updates to flashing scripts #775 - Documentation updates all over the place (and the wiki was given a cleanup)| - Updates to makefile #792 #787 - Cleanup the folder name of the source code #800 - clang-format spec setup #801 ## v2.13 - First _official_ Pinecil release - All of the wire for Pinecil releases added - Updated Translations - Delay accelerometer to help with entering sleep on startup - Dual speed PWM to help with power limit control - Improve heat up time - Adds locking mode - Improved docs all over the place - Repo rename occured TS100 -> IronOS - Hall effect sensor support added (not fitted in Pinecil but optional) - QC 20V support for Pinecil - CI upgrades for faster builds - Fixed bug with accelerometer model on Pinecil - Rework of all of the temperature curves for better accuracy ## v2.12 - Only released as pre-release - [TS80P] Improvements to the PD negotiation to handle a few more adapters cleanly - Pause on the last item in a list - Clean up the menu (removed both enables and settings, so that you can turn things off easier) - Removing the very old single line menu style. ## v2.11 - First TS80P support - Added in a USB-PD driver stack for the FUSB302 - Fixed some graphical glitches ## v2.10 - GUI polish (animations and scroll bars) - Power pulse to keep power supplies alive - Adjustable tip response gain ## v2.09 - Adjustable steps in temperature adjustment - Git hash now in build string - Adjustable language to set if US units are available or not - Some minor QC3 improvements ## v2.08 - Fixes auto start in sleep mode - Power limiters ## v2.07 - QC fixes - Cosmetic fixes for leading 0's ## v2.06 - Warning on settings reset - Temp temp re-write - Display calibration offset - Hide some leading 0's - Menu timeouts ## v2.05 - Language updates ## v2.04 - GUI updates ## v2.03 - Support for new accelerometers ## v2.02 - Adds small font ## v2.01 - Newer settings menu ## v2.00 - Complete re-write of the low layer system to use the STM32 HAL for easier development - This allowed easier setup for the new ADC auto measuring system - Better tip PWM control - Moved to FreeRTOS for scheduling - Complete re-write from blank - Added detailed screen views - Added smaller font for said screen views ## v1.17 - Added blinking cooldown display - Allowed smaller sleep timeout values - New font! - Automatic startup option ## v1.16 - Added automatic rotation support - Added power display graph ## v1.15 - Added support for a custom bootup logo to be programmed via the DFU bootloader ## v1.14 - Changed input voltage cutoff to be based on cell count rather than voltage ## v1.13 - Swapped buttons for menu to prevent accidentally changing first menu item - Added auto key repeat ## v1.12 - Increases sensitivity options to be 1\*9 with 0 off state - Fixes issue where going from COOL \*> soldering can leave screen off ## v1.11 - Boost mode - Change sensitivity options to be 1\*8 ## v1.10 - Adds help text to settings - Improves settings for the display update rate ## v1.09 - Adds display modes, for slowing down or simplifying the display ## v1.08 - Fix settings menu not showing flip display ## v1.07 - Adds shutdown time to automatically shutdown the iron after inactivity ## v1.06 - Changes H and C when the iron is heating to the minidso chevron like images ## v1.05 - Adds ability to calibrate the input voltage measurement ## v1.04 - Increased accuracy of the temperature control - Improved PID response slightly - Allows temperature offset calibration - Nicer idle screen ## v1.03 - Improved Button handling - Ability to set motion sensitivity - DC voltmeter page shows input voltage ## v1.02 - Adds hold both buttons on IDLE to access the therometer mode - Changes the exit soldering mode to be holding both buttons (Like original firmware) ================================================ FILE: Documentation/Logo.md ================================================ # Startup Logo / Animation When the device starts, you can have it optionally show either a static image or an animation. You can also set if these should stay on the screen or dismiss after some amount of time. These can be an elegant way to personalise your device or just mark it as your one at a meetup where there may be multiple. All devices supported by IronOS support this logo, and follow a similar process for setting one up. Please read the below general information as well as any model specific notes. Bootup logos are stored at the end of the flash storage in the Iron; next to the user settings. By locating them at the end of storage they are not erased during the normal firmware upgrade process. Once a logo is set it should stay (unless we need to change things in the main firmware); so to erase your logo you will also find that we generate an erase file. Alternatively your method of flashing _may_ support doing a full erase flash which will also work for this. ## Generating the Logo files Because logos are stored at a fixed location in the device's internal flash; we can use the same method to flash these as you would normal firmware. This does also mean that we need to convert the image/animation file into the format that IronOS understands. IronOS uses a pre-processed file format to dramatically reduce the amount of space required to store the image; allowing for animations and saving space. In the [IronOS-Meta](https://github.com/Ralim/IronOS-Meta) repository is a `python` script to convert images into this pre-processed file format. Additionally, memebers of the community have contributed back their logo images as well. We provide these pre-converted for all models and ready to use in [IronOS-Meta/releases](https://github.com/Ralim/IronOS-Meta/releases). Download the zip for Pinecil or Miniware and then install using the instructions in the Flashing section below. If you want to make custom art then it needs to be converted with the Python script. You can checkout the repository or use the download-as-zip button in the Github web interface to download the code. Inside the download code is a `Boot Logos` folder, inside here is the python script required for logo conversion. It is easiest if you copy your logo file to be converted into this folder too, in order to keep commands shorter. The image can be in color and any size, but it will be resized and converted to 1-bit color. However, it looks best if you create a 96x16 image (`png` or `bmp`) in any image editor and color the pixels black & white manually. The thresholding used for converting colour to B&W may not always work as well as one would hope. The converter requires at least Python3 and Pillow apps as well as the IntelHex library for Python. Follow online instructions for installing Python, Pillow, and IntelHex on your machine. Any reasonably recent version should work well. When running the script on the Windows operating system it is recommended to use `Powershell` rather than the old `Command Prompt`. For installing pillow, you can install it via your package manager (Debian and similar distros) or via pip. To install via pip the command should be `python -m pip install pillow`. For installing IntelHex you can use the same pip command as above but replace `pillow` with `intelhex` so that it becomes `python -m pip install intelhex`. In your shell you can now execute `python img2logo.py input.png out -m ${model}` to convert the file `input.png` and create output files in the folder `out`. The model should be replaced by one of the following options: - `miniware` for older Miniware Irons -> TS100, TS80, TS80P - `pinecilv1` for the Pinecil V1 - `pinecilv2` for the Pinecil V2 - `ts101` for the Miniware TS101 [^1] [^2] - `s60` for the Sequre S60 [^1] - `mhp30` for the Miniware MHP30 Different models are used for different flash locations for the image storage. This means that files are **not** interchangeable between devices. If you are flashing multiple devices you will need to create a different file for different models. After processing its expected to have a `.hex` and `.dfu` file created to be used. Which one to use will depend on your device. Note: make sure your image file is in the same folder as script files (img2logo.py, output_dfu.py, output_hex.py). [^1] Note that these devices have larger resolution screens that the logo system supports right now. Fixes are coming for this soon, roughly scheduled for 2.23. [^2] The TS101 requires extra steps, see below. ### TS101 Quirks When Miniware designed the TS101 they cut cost by using an STM32 clone with some odd quirks. They also re-wrote their USB bootloader, which has introduced new bugs for us to deal with. Their bootloader appears to have kept the existing limit of not being able to flash small hex files, but they no longer fall for the older "just repeat the content" trick and instead reject the file. Additionally, while the MCU in use has 128K of flash, their bootloader (at least for me) fails to write to anything above 99K. It _looks_ like a watchdog reset or hard crash. Unsure. This has flow on effects, where the settings can still be located in the upper ~28K of flash, but it cant be used for anything we flash over USB. Of that 100K we can use, they waste 32K of it for their bootloader (Old bootloaders were 16K). This means the main "app" of IronOS is limited to around 67K (100K-32K for bootloader, -1K for logo). For this device the Logo is not located at the end of flash but instead at the last writable page (99K). Additionally, as we need to do a large write, to avoid having to waste more flash space; the logo is merged with the normal firmware. This means that the firmware and logo are flashed together once. Future updates can be done without merging as it will leave the logo data there as normal firmware doesnt touch that area of flash. To do this, download the latest version of IronOS and merge it with the logo using the `--merge` command line argument. To create the logo file for a TS101 the full command looks like `python3 img2logo.py -m ts101 --merge `. For this reason, there are no TS101 logo's generated by the IronOS-Meta repo. ## Flashing the Logo ### Upload via virtual disk (TS100,TS101,TS80,TS80P,S60,MHP30) If you normally update your firmware by having your device show up as a flash drive this is the method for you. This applies to all Miniware + S60 devices running the stock DFU bootloader. Place your device into update mode (usually by holding the B button when connecting your device to your pc via USB). Upload the `.hex` file you created earlier as if it was a firmware update. Do any normal tricks required for firmware flashing if any are required. Afterwards the firmware should indicate that it has worked (often by creating a `.rdy` file). At this point unplug your iron and re-connect it to power to start normally and the logo should welcome you. ### Upload via GUI flash tool (PinecilV1/V2) If you normally upload your firmware using a helper application, they should accept the files from the bootlogo the same as the normal firmware. Try the `.dfu` file first and then the `.hex`. If neither work then the application may not be updated to be able to handle boot logos. And you may need to use a different/newer tool. ### Upload via dfu-util (PinecilV1/IronOS-DFU) For the PinecilV1 and for any devices that have been converted to use `IronOS-DFU` as the bootloader you can flash these via the `dfu-util` command line tool. For these flash as per usual using the `.dfu` file. Afterwards power cycle and the logo should show up. ### Upload via blisp (PinecilV2) For the PinecilV2 we suggest `blisp` as the command line tool to use if you are not using a GUI tool. `blisp` has been updated to accept `.dfu` files as well as the `.bin` files it historically used. As such you use the `.dfu` file for the logo and flash as per normal otherwise and it will work and reboot at the end. It should show you your new logo after flashing. ================================================ FILE: Documentation/Menu.md ================================================ # Menu System In this firmware for these soldering irons, all settings are adjustable on the device itself. This means a computer is **not** required to change any setting. ## Soldering mode In this mode the iron works as you would expect, pressing either button will take you to a temperature change screen. - Use each button to go up/down in temperature. Pressing both buttons exits the temperature menu (or wait 3 seconds and it will time out). - Pressing both buttons or holding the rear button (`-/B`) will exit Soldering Mode. - Holding the front button (`+/A`) will enter [Boost mode](https://ralim.github.io/IronOS/Menu/#boost-mode) (if enabled). ## Profile mode (MHP30 only) In this mode, accessible by long pressing `(+/A)`, the configured profile will be initiated. - You cannot adjust the temperature or enter boost mode. - Pressing both buttons or holding the rear button (`-/B`) will exit Profile Mode as well. ## Settings mode This mode allows you to cycle through all the options and set custom values. The menu is arranged so that the most often used settings are first. - The rear button (`-/B`) cycles through the main options. (declines i.e. Additional warning to proceed.) - The front button (`+/A`) either enters a submenu or changes the selected option. (accepts i.e. Additional warning to proceed.) - If the device is unplugged before exiting the main menu settings will not be saved. - To exit the menu, either continue to press (`-/B`) or hold it until the idle screen is reached. Alternatively, you could press (`-/A`) & (`-/B`) simultaneously to exit the submenu and once more to exit the main menu. - If you idle on a setting (i.e., don't press any buttons), after 3 seconds, the screen scrolls a brief description (mini help guide). - Enter submenus using the front button (`+/A`) if you are going to change it or wish to view it. - Scrolling through the all options of a submenu will return you back to its entry location. ### Calibrating input voltage Due to the tolerance on the resistors used for the input voltage divider, some irons can be up to 0.6 V out on the voltage measurement. Please calibrate your iron if you have any issues with the cutoff voltage. This calibration is not required if you have no issues. Note that cutoff messages can also be triggered by using a power supply that is too weak and fails under the load of the iron. To calibrate your iron: 1. Measure the input voltage with a multimeter and note it down. 2. Connect the input to your iron. 3. Enter the settings menu 4. Under the Advanced submenu 5. Select the calibrate voltage option 6. Use the front and back buttons to adjust the displayed voltage to minimize the error to your original measurement 7. Press both buttons at the same time to Save and Exit to the menu ### Calibrate Tip CJC This calibrates the [Cold Junction Compensation](https://ralim.github.io/IronOS/Temperature/) *(CJC)* for the tip. This is normally not needed unless you have an issue with tip temperature or your tips are wearing out prematurely. Changing tip lengths does not necessarily mean a calibration is needed. Check first that your tips are not defective and measured resistance is close to specifications *[Pinecil / TS100 short tips **6.2 Ω**, long tips **8 Ω**, TS80/P ~**4.5 Ω**]*. What this is for:
Some tips have an offset on their readings which causes issues, i.e. The actual temperature of the tip is much higher than displayed. Follow the steps below to calibrate this. Caution:
If the method below is not followed, the iron could be worse than before calibration. If you need to repeat the method, first unplug and let the handle/PCB cool down to room temperature. 1. Connect power to your device. 2. Go to **`Advanced Settings`** using (`-/B`) and press (`+/A`) to select it. Use (`-/B`) to scroll to **`Calibrate CJC at next boot`** and confirm with (`+/A`). 3. Accept the *'warning text'* with (`+/A`). 3. Exit the settings menu as usual by pressing and holding (`-/B`). 4. Unplug you device. 5. **Critical: Make sure a tip is attached & wait until the tip & handle are at room temperature.** (Wait a reasonable amount of time after having used the device.) 6. Power the device and ideally keep it out of your hands (You know it might get warm.). 7. The display shows **`calibrating ....`** for a short time while the device measures and compares the tip and handle voltages. 8. **`Calibration done!`** is displayed for 3 seconds. The new offset value can later be viewed in the **`Debug menu`**. 9. Calibration is done and the device proceeds booting. Note: offsets are dependant on your tip, temperature sensor, and the MCU. It's the culmination of tolerances at rest. Typical values are 700-1000 range. This is only designed to be used at boot while cold (ambient / room temperature), as temperatures drift apart as soon as power is connected. Doing this reading repeatedly could result in wide varience of the offset number and/or incorrect calibration. ### Boost mode This allows you to change the front button (`+/A`) to become a boost button when you hold it for > 2 seconds. A boost button changes the soldering temperature for short periods. For example, when soldering a big joint and you need a much higher temperature, hold the (`+/A`) button down and it will temporarily increase the temperature to your 'boost' setting. When you release the button, the temperature will gradually go back to the normal set temperature. The boost temperature is set in Soldering settings. ================================================ FILE: Documentation/PortingToNewDevice.md ================================================ # Requesting support for a new device IronOS is largely designed to run on devices that are using _fairly_ modern microcontrollers at their core. Generally this means an ARM Cortex or RISC-V processor. At this point in time it is not planned to support 8051 or similar cored devices. This is largely due to the reliance on FreeRTOS at the moment. When requesting a port for a new device, please try and find out if the hardware meets the below requirements. The feature list's below are organised into three categories; Hard requirements that as of current must be met, soft requirements that _should_ be met for full featured performance and the final category of planned _but not yet implemented_ features; which can be implemented but can result in delays as these are not yet implemented. Aside from the below, keep in mind IronOS is really designed for soldering irons. This has expanded out into hot-plates as they are exceptionally similar devices. ## Hard requirements 1. Supported processor (Arm Cortex or RISC-V). (Though generally anything that has an existing FreeRTOS port is possible). 2. 64K of flash or larger (See note A) 3. 16K of ram or larger 4. Device has one or more heating elements that can be controlled by a main temperature sensor 5. If the main temperature sensor is a thermocouple, a reference temperature sensor for cold junction compensation must exist and be close to the sensor contacts 6. Means of the user updating the device without opening 7. Known pinmap for the microcontroller. (see note B) ## Soft requirements 1. USB-PD is strongly preferred over Quick Charge; Quick Charge only devices are considered legacy and will likely not be prioritiesd. 2. Open source or at the least schematics available is **strongly** preferred and will prioritise the device. 3. Likewise friendly vendors will help dramatically with support, due to both questions and also appearances to help the community. 4. Hardware PWM wired up to the tip control is nice to have but not essential 5. Very strong preference against devices that use the endless sea of STM32 clones. ## Planned features These features are planned for eventual support, but will likely not be done until devices need them. - Colour screens - More than 2 buttons for input, or encoder inputs - WiFi/Zigbee/ any other networking ## Notes ### Note A - Flash storage space 64KB is generally the minimum recommended size for the hardware to have. Larger is _definitely_ preferred as it enables more features or the multi-pack language firmwares. Keep in mind that on some devices we loose space to a USB DFU bootloader (Older STM32F1's) so the firmware _can_ work with less. But it can come at the cost of features. 128KB or larger is **great**. For devices that have BLE or WiFi or other features, often code requirements are significantly larger. These are considered non essential features so will be ignored if we run into size issues. ### Note B - Pinmap for the microcontroller In order to be able to write the interfacing code to communicate with the hardware, we need to know what pins on the microcontroller go to what hardware. It is also loosely required to have an understanding of the rest of the device, we do not need details on a lot of the boring aspects,but if for example a USB-PD interface IC is used we would want to know which one. ## Example request for adding a new device Device Name: Device Type: Approximate Price: Example purchase locations: ### Hardware details Microcontroller version: `STM32F103C8Tx` Flash size (If external to the MCU):`N/A` Microcontroller Pinout: Device type: Device meets hard requirements list [] Device meets soft requirements list [] Device features USB-PD [] Device features USB-QC [] Device features DC Input [] Device features BLE [] ================================================ FILE: Documentation/Power.md ================================================ # Power & Performance All of the irons are [PWM controlled](https://www.digikey.com/en/blog/pulse-width-modulation#) resistive heating elements. This means that the electronics in the handle can only turn the heating element on and off. This *means* that the power provided in the tip is 100% controlled by the supply voltage used (higher voltage PSU = higher performance). Irons at their simplest are just a resistor (Ω) connected to your power source via a switch. - When the switch is on, the power in the resistor is: *`P(watts) = V(volts) \times\ I(current=amps)`* - Current through the resistor is: *`I(amps) = V(volts) ÷ Ω (resistance)`* - Combining these gives some common equations for Power *`P(watts) = V(volts) * I(amps)`* or *`P = V^2 ÷ Ω`* The resistance of the tip is a fixed constant in ohms (Ω): - 6.2 Ω Pine64 short tip - 8.0 Ω TS100/Pinecil long tip - 4.5 Ω TS80(P) This means the power delivered to the soldering tip is proportional to the voltage squared. Therefore the Pinecil and TS100 perform poorly when run off 12V power supplies and may issue a `Thermal Runaway` message (weak power supply). #### Use an [Ohm calculator](https://www.rapidtables.com/calc/electric/power-calculator.html#dc) to quickly derive watts. | Type | Volts| / | Tip Ω | = | Amps | * | Volts | = | Watts | | :--------: | :--: |:-:| :---: |:-:|:-----:|:-:| :---: |:-:|:-----:| | USB QC3.0 | 9V | / | 4.5 Ω | = | 2.0A | * | 9V | = | 18W | | USB-C PD | 12V | / | 4.5 Ω | = | 3.0A | * | 12V | = | 32W | | USB-C PD | 20V | / | 8.0 Ω | = | 2.5A | * | 20V | = | 50W | | USB-C PD | 20V | / | 6.2 Ω | = | 3.2A | * | 20V | = | 64W | | DC Barrel | 24V | / | 8.0 Ω | = | 3.0A | * | 24V | = | 72W | | DC Barrel | 24V | / | 6.2 Ω | = | 3.8A | * | 24V | = | 92W | | EPR PD3.1 | 28V | / | 8.0 Ω | = | 3.5A | * | 28V | = | 98W | | EPR PD3.1 | 28V | / | 6.2 Ω | = | 4.5A | * | 28V | = | 126W | ## Output Control & Regulation These soldering irons use a FET to switch the power to the soldering iron tip. This is a P-MOSFET and its controlled via a small transistor circuit, which in turn is controlled via the MCU (i.e., STM32). The MCU controls this PWM output proportional to the output from the PID control loop running in the software. To measure the tip temperature in the iron, the iron has a small op-amp connected across the terminals at the cold end of the tip. This is setup to measure the voltage across the same terminals that are used to power the tip. In order to read the very small voltage generated by the [thermocouple cold junction](https://ralim.github.io/IronOS/Temperature/), the iron's output must be turned off for a moment. Once the output is turned off (via the FET), the system has a recovery time as the tip capacitance discharges and the op-amp exits saturation. After this delay period, the MCU's ADC (analog-to-digital converter) samples the output of the op-amp 8 times quickly and then sets a flag to turn the PWM output back on. This enforces a small dead time in the output signal while this occurs, so there is a balance between sampling the temperature often to maintain a stable tip temperature control and sampling less often to increase the maximum power deliverable to the tip ([see Complexity of measurement](https://ralim.github.io/IronOS/Temperature/#complexity-of-measurement)). ## Power sources Supported by IronOS hardware may use different power sources (chargers/powerbanks/battery packs) with different standards & protocols (QC/PD/etc). For more information collected by the community on that, please, [see the related documentation section](https://ralim.github.io/IronOS/PowerSources/). ================================================ FILE: Documentation/PowerSources.md ================================================ # Power sources Supported by IronOS hardware may use different power sources (chargers/powerbanks/battery packs) with different standards & protocols (QC/PD/etc). This document contains information collected by the community with tested power sources. This is not ads but first hands-on experience results from real users since some chargers/powerbanks regardless labels on the box may not fully support what's declared! ## QC(3) ### Compatible Devices (QuickCharge for TS80/P) The following table is the list of compatible device and remarks when powering up the TS80 through it for both stock firmware from MiniDso and IronOS. The list of devices below are primarily taken from [#349](https://github.com/Ralim/ts100/issues/349#issuecomment-449559806) | Device Name | Stock FW | IronOS FW | |-------------|:--------:|:---------:| | Anker PowerCore II Slim 10000 Powerbank | Not Working | Good | | [Aukey 26.5/30 Ah Powerbank (PB-Y3)](https://www.aukey.com/products/30000mah-power-bank-with-quick-charge-3-0/) | OK\*\* (15sec t/o) | OK\*\* (15sec t/o) | | Aukey QC3 Charger | Good | Only 5V | | [Aukey QC3 Charging Station (PA-T11)](https://www.aukey.com/products/6-port-charging-station-with-quick-charge-3-0-pa-t11/) | Good | Good | | Besiter 20000mah QC3 | Not Working | Only 5V | | BlitzWolf BW-P5 | Not Working\* | Unknown | | BlitzWolf BW-PF2 | OK\*\* (10sec t/o) | OK\*\* (10sec t/o) | | BlitzWolf BW-PL3 | Low Voltage | OK | | BlitzWolf BW-PL4 | Unknown | Not Working | | BlitzWolf BW-S6 | Unknown | OK | | Charmast 20800 mAh QC 3.0 | Low Voltage\* | Good | | Clas Ohlson Powerbank USB-C 10050 mAh, Clas Ohlson | Unknown | OK\*\* | | [Cygnett 20,000mAh USB-C](https://www.cygnett.com/products/20-000mah-usb-c-power-bank-in-black)| Not Working | Good | | [HAME H13D](https://www.amazon.com/dp/B07GWMFW82) 10000mAh PD/QC3.0 Power Bank | OK\*\* (30sec t/o) | OK\*\* (30sec t/o?) | | HIPER 10000 mAh 18W PD+QC3.0 (MPX10000) | Low Voltage | OK\*\* (30sec t/o) | | [iMuto Portable Charger 30000mAh](https://www.amazon.com/gp/product/B01MXCMGB8/ref=ppx_yo_dt_b_asin_title_o05_s00) | Low Voltage | Good | | ISDT BG-8S | Good | Good | | [iVoler Quick Charge 3.0 USB C 30W 2-Port USB](https://www.amazon.de/dp/B077P8ZZB8/) | Good | Good | | [imuto X6L Pro 30000 mah](https://www.amazon.com/dp/B01MXCMGB8) | Not Working | Bad | | Interstep 10000 mAh 18W PD+QC3.0+FCP+AFC (MPX10000) | Good | OK\*\* (30sec t/o) | | Jackery Black 420 | Low Voltage | Good | | Kogan Premium 80W 5 Port USB Charger| Low Voltage | Good | | Nokia AD-18WE | Unknown | OK | | [Omars 2000mAh USB-C PD+QC3.0 (OMPB20KBUPLT / OMPB20KPLT)](https://www.amazon.com/dp/B07CMLVR6C) | OK\*\* (20sec t/o) | Unknown | | Polaroid PS100 Powerbank (https://polaroid.com/products/ps100) | Good | Good | | Xiaomi 10000mAh Mi Power Bank Pro (PLM03ZM) | Good | Unknown | | Xiaomi 10000mAh Mi Power Bank 2i (PLM09ZM) | Good | Good | | Xiaomi 20000mAh Mi Power Bank 3 (PLM07ZM) | Unknown | Good Type A, Bad Type C | | [ZeroLemon ToughJuice](https://www.amazon.com/dp/B01CZR3LT2/) 30000mAh PD/QC2.0 Power Bank | OK\*\* (20sec t/o) | OK\*\* (20sec t/o?) | | [URUAV XT-60 to USB module](https://www.banggood.com/URUAV-XT-60-to-USB-Charger-Converter-Support-3S-6S-LiPo-Battery-10_5V-32V-Input-3V-20V-Output-45W-Max-Fast-Charging-Adapter-For-RC-Racing-Drone-p-1475876.html) | Unknown | Good | \* Need further tests on newer firmware \*\* Most Power Banks shut down if current draw drops below 50mA, assuming that charging is complete and avoiding overcharging. Custom firmware is designed to avoid this until it enters Zzzz mode. ### DIY QC3.0 You may also build your own QC3.0 power source that requires this little [thing](https://www.tindie.com/products/soubitos/qualcomm-qc2-3-diy-8-32vin-36-12vout-3a-max/) and have at least 3S lithium packs or any input voltage from 8 to 32V. You can also go for an [alternate module](https://www.banggood.com/DC-Buck-Module-12V24V-to-QC3_0-Single-USB-Mobile-Charging-Board-p-1310585.html) which has at least one good review of it. **DISCLAIMER:** _**We do not hold any responsibility for accidents that happen when building your own QC3.0 power source!!!**_ ## PD The following additional table is the list of devices compatible with hardware which requires Power Delivery support (>= 30W). Devices from the list have been successfully tested & used with TS80P in PD mode. Please, keep in mind that: - PD can be provided only through usb-c <-> usb-c cable; - not only a charger but a cable itself should be capable to carry higher wattages. ### Compatible Devices (PowerDelivery for TS80P) | Device Name | IronOS FW | |-------------|:---------:| | Traver Charger QC09 (45W max)\* | OK | | Xiaomi AD65GEU Mi 65W Fast Charger with GaN Tech (AD65GEU, 65W max) | OK | \* Comes as an _option_ for extra price in the package with TS80P from [official store](https://aliexpress.com/item/4000764937427.html) or from [NovelLife store separately](https://aliexpress.com/item/4001316262433.html) on AliExpress. Please, DO NOT BUY cheap "fast chargers with QC/PD support" for a few dollars online (i.e., less than ~10$): if you check reviews, then you see that they are phonies - even if you get lucky, you probably get 5V/1A max from them. ================================================ FILE: Documentation/README.md ================================================ #### This is autogenerated README for brief navigation through github over official documentation for IronOS project #### This documentation is also available [here online](https://ralim.github.io/IronOS) - [Home](../Documentation/index.md) - [Getting Started](../Documentation/GettingStarted.md) - Flashing the firmware - [MHP30](../Documentation/Flashing/MHP30.md) - [Pinecil V1](../Documentation/Flashing/Pinecil%20V1.md) - [Pinecil V2](../Documentation/Flashing/Pinecil%20V2.md) - [TS80(P)](../Documentation/Flashing/TS80(P).md) - [TS100](../Documentation/Flashing/TS100.md) - Operation - [Main Menu](../Documentation/Menu.md) - [Settings](../Documentation/Settings.md) - [Debug Menu](../Documentation/DebugMenu.md) - [Power](../Documentation/Power.md) - [Temperature](../Documentation/Temperature.md) - [Startup Logo](../Documentation/Logo.md) - Hardware - [Bluetooth (Pinecil V2)](../Documentation/Bluetooth.md) - [Debugging USB-PD](../Documentation/DebuggingPD.md) - [Hall Sensor (Pinecil)](../Documentation/HallSensor.md) - [Hardware Notes](../Documentation/Hardware.md) - [Known Hardware Issues](../Documentation/HardwareIssues.md) - [New Hardware Requirements](../Documentation/PortingToNewDevice.md) - [Power sources](../Documentation/PowerSources.md) - [Troubleshooting](../Documentation/Troubleshooting.md) - [WS2812B RGB Modding (Pinecil V2)](../Documentation/WS2812BModding.md) - [Translations](../Documentation/Translation.md) - [Development](../Documentation/Development.md) - [Changelog](../Documentation/History.md) ================================================ FILE: Documentation/Settings.md ================================================ # IronOS Settings Menu The below breaks down the menu's and what each setting means. ## Menu Categories In the menu there are a few main categories that are used to keep the list manageable. ### Category: Power settings Menu for settings related to power. Main settings to do with the input voltage. ### Category: Soldering settings Settings for soldering mode, such as boost temps, the increment used when pressing buttons and if button locking is enabled. ### Category: Sleep mode Settings to do with power saving, such as sleep mode, sleep temps, and shutdown modes. ### Category: User interface User interface related settings, such as units. ### Category: Advanced settings Advanced settings. Misc catchall for settings that don't fit anywhere else or settings that require some thought before use. ## Settings These are all of the settings possible in the menu. **Not all settings are visible for all devices.** For example, the TS100 does not have USB-PD settings. When using the device, if unsure you can pause (press nothing) on a setting and after a short delay help text will scroll across the screen. This is the "on device help text". ### Setting: Power source When the device is powered by a battery, this adjusts the low voltage threshold for when the unit should turn off the heater to protect the battery. On device help text: Set cutoff voltage to prevent battery overdischarge (DC=10V) (S=3.3V per cell, disable PWR limit) ### Setting: Minimum voltage When powered by a battery, this adjusts the minimum voltage per cell before shutdown. (This is multiplied by the cell count.) On device help text: Minimum allowed voltage per battery cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V) ### Setting: QC voltage This adjusts the maximum voltage the QC negotiation will adjust to. Does NOT affect USB-PD. Should be set safely based on the current rating of your power supply. On device help text: Max QC voltage the iron should negotiate for ### Setting: PD timeout How long until firmware stops trying to negotiate for USB-PD and tries QC instead. Longer times may help dodgy / old PD adapters, faster times move onto PD quickly. Units of 100ms. Recommended to keep small values. On device help text: PD negotiation timeout in 100ms steps for compatibility with some QC chargers ### Setting: PD Mode Adjusts how the USB-PD Logic selects the voltage. No Dynamic disables EPR & PPS protocols, Safe mode does not use padding resistance (will select a slightly lower voltage). On device help text: No Dynamic disables EPR & PPS, Safe mode does not use padding resistance ### Setting: Boost temp When the unit is in soldering mode. You can hold down the button at the front of the device to temporarily override the soldering temperature to this value. This SETS the temperature, it does not ADD to it. On device help text: Tip temperature used in "boost mode" ### Setting: Start-up behavior When the device powers up, should it enter into a special mode. These settings set it to either start into soldering mode, sleeping mode or auto mode (Enters into soldering mode on the first movement). On device help text: S=heat to soldering temp | Z=standby at sleep temp until moved | R=standby without heating until moved ### Setting: Temp change short Factor by which the temperature is changed with a quick press of the buttons. On device help text: Temperature-change-increment on short button press ### Setting: Temp change long Factor by which the temperature is changed with a hold of the buttons. On device help text: Temperature-change-increment on long button press ### Setting: Allow locking buttons If locking the buttons against accidental presses is enabled. On device help text: While soldering, hold down both buttons to toggle locking them (B=boost mode only | F=full locking) ### Setting: Profile Phases set the number of phases for profile mode. On device help text: Number of phases in profile mode ### Setting: Preheat Temp Preheat to this temperature at the start of profile mode. On device help text: Preheat to this temperature at the start of profile mode ### Setting: Preheat Speed How fast the temperature is allowed to rise during the preheat phase at the start of profile mode. On device help text: Preheat at this rate (degrees per second) ### Setting: Phase 1 Temp Target temperature for the end of phase 1 of profile mode. On device help text: Target temperature for the end of this phase ### Setting: Phase 1 Duration Duration of phase 1 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature. On device help text: Target duration of this phase (seconds) ### Setting: Phase 2 Temp Target temperature for the end of phase 2 of profile mode. On device help text: ### Setting: Phase 2 Duration Duration of phase 2 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature. On device help text: ### Setting: Phase 3 Temp Target temperature for the end of phase 3 of profile mode. On device help text: ### Setting: Phase 3 Duration Duration of phase 3 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature. On device help text: ### Setting: Phase 4 Temp Target temperature for the end of phase 5 of profile mode. On device help text: ### Setting: Phase 4 Duration Duration of phase 5 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature. On device help text: ### Setting: Phase 5 Temp Target temperature for the end of phase 5 of profile mode. On device help text: ### Setting: Phase 5 Duration Duration of phase 5 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature. On device help text: ### Setting: Cooldown Speed How fast the temperature is allowed to drop during the cooldown phase at the end of profile mode. On device help text: Cooldown at this rate at the end of profile mode (degrees per second) ### Setting: Motion sensitivity Scale of how sensitive the device is to movement. Higher numbers == more sensitive. 0 == motion detection turned off. On device help text: 1=least sensitive | ... | 9=most sensitive ### Setting: Sleep temp Temperature the device will drop down to while asleep. Typically around halfway between off and soldering temperature. On device help text: Tip temperature while in "sleep mode" ### Setting: Sleep timeout How long of a period without movement / button-pressing is required before the device drops down to the sleep temperature. On device help text: Interval before "sleep mode" starts (s=seconds | m=minutes) ### Setting: Shutdown timeout How long of a period without movement / button-pressing is required before the device turns off the tip heater completely and returns to the main idle screen. On device help text: Interval before the iron shuts down (m=minutes) ### Setting: Hall sensor sensitivity If the unit has a hall effect sensor (Pinecil), this adjusts how sensitive it is at detecting a magnet to put the device into sleep mode. On device help text: Sensitivity to magnets (1=least sensitive | ... | 9=most sensitive) ### Setting: HallSensor SleepTime If the unit has a hall effect sensor (Pinecil), this adjusts how long the device takes before it drops down to the sleep temperature when hall sensor is over threshold. On device help text: Interval before "sleep mode" starts when hall effect is above threshold ### Setting: Temperature unit If the device shows temperatures in °C or °F. On device help text: C=°Celsius | F=°Fahrenheit ### Setting: Display orientation If the display should rotate automatically or if it should be fixed for left- or right-handed mode. On device help text: R=right-handed | L=left-handed | A=automatic ### Setting: Cooldown flashing If the idle screen should blink the tip temperature for attention while the tip is over 50°C. Intended as a 'tip is still hot' warning. On device help text: Flash temp reading at idle while tip is hot ### Setting: Scrolling speed How fast the description text scrolls when hovering on a menu. Faster speeds may induce tearing, but allow reading the whole description faster. On device help text: Scrolling speed of info text (S=slow | F=fast) ### Setting: Swap + - keys Swaps which button increments and decrements on temperature change screens. On device help text: Reverse assignment of buttons for temperature adjustment ### Setting: Swap A B keys Swaps which button is used as Enter/Change and as Scroll/Back in Settings menu. On device help text: Reverse assignment of buttons for Settings menu ### Setting: Anim. speed How fast should the menu animations loop, or if they should not loop at all. On device help text: Pace of icon animations in menu (S=slow | M=medium | F=fast) ### Setting: Anim. loop Should the menu animations loop. Only visible if the animation speed is not set to "Off" On device help text: Loop icon animations in main menu ### Setting: Screen brightness Display brightness. Higher values age the OLED faster due to burn-in. (However, it is notable that most of these screens die from other causes first.) On device help text: Adjust the OLED screen brightness ### Setting: Invert screen Inverts the entire OLED. On device help text: Invert the OLED screen colors ### Setting: Boot logo duration Sets the duration for the boot logo (s=seconds). On device help text: Set boot logo duration (s=seconds) ### Setting: Detailed idle screen Should the device show an 'advanced' view on the idle screen. The advanced view uses text to show more details than the typical icons. On device help text: Display detailed info in a smaller font on idle screen ### Setting: Detailed solder screen Should the device show an 'advanced' soldering view. This is a text-based view that shows more information at the cost of no nice graphics. On device help text: Display detailed info in a smaller font on soldering screen ### Setting: Bluetooth Should BLE be enabled at boot time. On device help text: Enables BLE ### Setting: Power limit Allows setting a custom wattage for the device to aim to keep the AVERAGE power below. The unit can't control its peak power no matter how you set this. (Except for MHP30 which will regulate nicely to this). If USB-PD is in use, the limit will be set to the lower of this and the supplies advertised wattage. On device help text: Average maximum power the iron can use (W=watt) ### Setting: Calibrate CJC at next boot Note: If the difference between the target temperature and the measured temperature is less than 5°C, **calibration is NOT required at all**. This is used to calibrate the offset between ADC and Op-amp of the tip **at next boot** (Ideally it has to be done at boot, before internal components get warm.). If the checkbox is set, the calibration will only be performed at the next boot. After a successful calibration the checkbox will be unchecked again! If you need to repeat the calibration however, you have to set the checkbox *again*, unplug your device and let it cool down to room/ambient temperature & power it up, ideally while it sits on the desk. Also, the calibration will only take place if both of the following conditions are met: - The tip must be installed. - The temperature difference between tip and handle must be less than 10°C. (~ ambient / room temperature) Otherwise, the calibration will be performed the next time the device is started and both conditions are met, unless the corresponding checkbox is unchecked. Hence, never repeat the calibration in quick succession! On device help text: Calibrate Cold Junction Compensation at next boot (not required if Delta T is < 5°C) ### Setting: Calibrate input voltage Enters an adjustment mode where you can gradually adjust the measured voltage to compensate for any unit-to-unit variance in the voltage sense resistors. On device help text: Start VIN calibration (long press to exit) ### Setting: Power pulse Enables and sets the wattage of the power pulse. Power pulse causes the device to briefly turn on the heater to draw power to avoid power banks going to sleep. On device help text: Intensity of power of keep-awake-pulse (W=watt) ### Setting: Power pulse delay Adjusts the time interval between power pulses. Longer gaps reduce undesired heating of the tip, but needs to be fast enough to keep your power bank awake. On device help text: Delay before keep-awake-pulse is triggered (x 2.5s) ### Setting: Power pulse duration How long should the power pulse go for. Some power banks require seeing the power draw be sustained for a certain duration to keep awake. Should be kept as short as possible to avoid wasting power / undesired heating of the tip. On device help text: Keep-awake-pulse duration (x 250ms) ### Setting: Restore default settings Resets all settings and calibrations to factory defaults. Does NOT erase custom user boot up logo's. On device help text: Reset all settings to default ### Setting: Language: EN English Changes the device language on multi-lingual builds. On device help text: ### Setting: Soldering Tip Type For manually selecting the type of tip fitted On device help text: Select the tip type fitted ================================================ FILE: Documentation/Temperature.md ================================================ # Tip temperature measurement The soldering irons use a modified N-type thermocouple in the tip to measure the tip temperature. This is constructed for free by using a different type of metal to join one of the rings to the heating coil. This effectively creates a free temperature sensor for very low cost and construction difficulty. The downsides of this are twofold; one, it is made using non-optimal metals and has a non-constant temperature response; and two, as this uses the same connections as the heating current, you can't measure the temperature while you are heating the tip. ## How a thermocouple works (brief) [Thermocouples use a junction of two dissimilar metals](https://www.youtube.com/watch?v=v7NUi88Lxi8) to create a very small amount of power (microvolts). This can then be measured and used with a known transfer function to derive the temperature of the junction. This has some fairly large limitations, but it also has the benefit of being extremely cheap. Conventionally a thermocouple is created using two dissimilar metals that join, and then the other ends of these metals are terminated to copper contacts. These copper contacts are also part of the construction of the thermocouple and are referred to as the cold junction. As there are these extra two joins between the thermocouple wires and the copper; these also have properties of their own in their reactions with temperature. If the cold junction is held at 0 degrees Celsius, then their effect is considered to be null, and so they can be ignored. However, in the real world the joins to copper are often at room temperature, and as such the measured voltage from the thermocouple must be compensated to remove the influence of these joints. This process is often called cold junction compensation. Every time in the circuit there is a join between two different metals, then a small thermocouple is created, this means that _every_ soldered connection is also one. ## How these irons implement the temperature reading If you analyse one of the open circuit schematics (Pinecil, TS100, TS80) they all use the same approximate formula. This consists of an op-amp that is connected directly across the heating connections to the tip, and a separate handle temperature sensor. When the iron is **not** heating the tip, the microcontroller uses the ADC to read the output from the op-amp. This produces a voltage that _should_ be linear to the temperature of (tip-handle). This value is then offset compensated (to remove ADC+op-amp offsets), and then converted into a temperature delta in °C/K. This temperature delta can then be added to the handle temperature to derive the tip temperature in degrees Celsius. Depending on the construction of the tip, the lookup values used for converting the tip reading in µV into °C/K varies. It is worth noting, however, that TS100 and Pinecil tips are approximately the same as the Hakko T12 tips. (In @Ralim's testing, to within measurement error). This makes sense as the T12 tips are an excellent and cheap design for Miniware to mimic in making the TS100 in the first place. ## Implications of this ### Reading accuracy vs Heating performance tradeoff Because the tip can only be measured when the unit is not heating, the more often the tip is measured (for finer temperature control) the less time the unit can spend heating up the tip. This means that for fast heat up and fine temperature control the firmware now implements two speeds to the controller loop. During heating up the system runs fewer temperature measurements and instead allows the tip to spend more time burning power. Once the unit is up to temperature, the rate of taking temperature readings is doubled to allow for faster reaction times. ### Tip heat up lag time As the temperature sensor is a part of the heater coil inside of the tip (or very close by, not entirely certain); the temperature reading is of the _inside_ of the tip, rather than the outside. The outside temperature is the most critical for the user as this is where the solder is actually melting and performing work. The PID controller in the firmware is tuned to be slightly underdamped and thus more "jumpy" than some people would expect. This is based on the theory that if the inside of the tip is seeing the temperature drop; the outside temperature has dropped more and so we should overcompensate until they equalise. This is why sometimes the temperature may flick around a little during use but the tip temperature itself is quite stable. The thermal mass of the tip smooths these small amounts out nicely for the user. Though seeing larger jumps on some tips than others _may_ indicate that the tip does not have optimal internal thermal bonding between the heater coil and the tip itself. The firmware uses the theory that these irons are aimed more to the power users territory than most, so it tries to _not_ hide the actual temperature. Some soldering iron controllers hide the actual measurement once you are within a certain tolerance of this. For example, on a digital Weller unit that Ralim has, if set to 350 °C, it will regulate to within around +/- 3°C but not indicate you are outside of the margin of error until you exceed +/- 5°C. This gives the illusion that it's holding the temperature perfectly when in actuality it's moving around as well. Given enough time (3-5 seconds) with no external cooling, the inside and outside temperatures of the tip will be equal. When testing the tip temperature accuracy try to allow time for the system to stabilise. ### Complexity of measurement The firmware in these irons does a *best-effort* of calculating an accurate temperature. As always there is a tradeoff between perfect accuracy and firmware complexity and setup. These irons are built down to a cost; expecting accuracy greater than 1% is not really an option as the voltage reference is only 1% accurate at best. So _all_ measurements are affected by its accuracy. The low-cost chips used in the irons do not come calibrated from the factory so we do not have an internal calibration we can use to try and measure this inaccuracy. The firmware only accounts for [cold junction compensation](https://www.tegam.com/what-exactly-is-cold-junction-compensation/) and then treats the remaining error as being a constant offset. While the error is small, it is actually composed of both a constant offset as well as an offset that is linear to the handle temperature. This offset that is linear to handle temperature is as of current not modelled into the firmware and is assumed to be constant. This is generally *close enough* as once the unit is in use, the handle temperature is usually within 10 °C as the components inside warm-up from use. This means that this error is "relatively" constant once the unit is being used. `However, this can cause odd behaviour when the tip temperature ~= room temperature. It can cause some jumping and movement in the readings when attempting to control the tip to sub 100 °C.` This is a known tradeoff that is made as the irons intended use case means that it will spend most of its time above 150 °C, at which point these errors are no longer the dominant error sources in the system. ================================================ FILE: Documentation/Translation.md ================================================ # Translation At the present time the main way of performing translations is to open a PR to this repository. All translations are stored as `json` files in the repository. Currently there is ongoing work to look into a more user friendly method of editing translations than these but for now these are reliable. You can create a pull request with the new / updated json configuration file, and this will include this language into the new builds for the firmware. For testing you can build locally and test of course; but if you dont want to figure out the build environment; you can just open a PR and github will build the firmware for you using the _actions_ feature. This means that once you have a github account you can perform all of your edits inside Github should this be desired. Translations are _NOT_ accepted via issues/discussions or email. ================================================ FILE: Documentation/Troubleshooting.md ================================================ # Troubleshooting If your device is not operating as expected; and you are within the manufacturer support window, please first contact your manufacturer and RMA / warranty your device. If your iron is not working as expected, [the Debug menu](https://ralim.github.io/IronOS/DebugMenu/) exposes internal measurements to help you narrow down the root cause of the issue. Alongside all of these, issues with the soldering of the main MCU could cause all of these as well; and should always be checked. The tip is important for the operation of your iron. T100 and Pinecil tips are around 8 ohms, and TS80(P) tips are around 4.5 ohms. You are welcome to open discussions about issues as well, or if you bought your Pinecil from an official store; use the [Pinecil community chat](https://wiki.pine64.org/wiki/Pinecil#Community_links) for support. But it is helpful to do some basic diagnostics first just in case the issue is easily fixed. The **VAST** majority of issues are poor soldering or cold solder joints. If you can open up your iron, give it a good look at all the connection points, and use another iron to reflow any suspicious ones, this can fix most issues. ## Tip Shorted warning If you are powering up a device that supports tip resistance detection (TS101 and Pinecilv2 as of present), the firmware checks the readings of the raw tip resistance and sorts these into three "bins". `8 ohm tips`, `6.2 ohm tips` and `tip-shorted`. The tip resistance is used when negotiating USB-PD and in thermal calculations. The `tip-shorted` option is selected if your tip is measured to be abnormally small. This could indicate a failed driver mosfet or a failed tip. When this warning is shown; heating will be disabled to protect from damage. As trying to heat a shorted tip can damage the iron itself. It is best to take out your tip and manually measure and verify the tip's resistance. It should be 6-8 ohms (depending on tip type). When measuring resistances this small some multimeters can struggle. If you have access to a current limited bench power supply, you can try doing a 4 wire measurement by measuring the voltage drop on the tip while applying a known current. `(R=V/I)`. If the tip measures correctly you may have a damaged driver mosfet; it would be ideal to open your iron and test the mosfet is operating correctly. If after both of these checks everything looks as expected, feel free to open a discussion on IronOS to talk about the issue (Or for Pinecil the community chat can be a much faster response). ## High tip temp reading when the tip is cool If you are finding the tip is reading high; the first fields to check in the Debug menu are `RTip` and `CHan`. - `RTip` is the raw tip reading in μV; at cool this should be around 700-1000 for larger tips and ~1500 for smaller tips (TS80's) - `CHan` is the temperature of the temperature sensor on the PCB in degrees Celsius \* 10. So 29 °C ambient should read as 290 ### RTip is out of spec `RTip` will over-read on bad contacts or no tip inserted. If `RTip` is overreading, you may have one of the following: - Partially stuck on main MOSFET - Slow reacting main MOSFET driver transistor - Damaged Op-Amp - Poor soldering on the Op-Amp circuitry - No tip inserted or tip that is not connecting correctly If `RTip` is under-reading you most likely have issues with the Op-Amp or the tip. The signal should be pulled high by hardware (reading hot), so this often means the MCU is not reading the signal correctly. Check MCU soldering. ### CHan is out of spec CHan reading comes directly from the cold junction compensation temperature sensor. This is usually a TMP36 (Pinecil V1), or an NTC thermistor (MHP30, TS80P, Pinecil V2). If `CHan` is reading low: - Check the connection from the MCU to the handle temperature sensor. - Check the power pin connection on the TMP36 - Check pullup resistor on the NTC thermistor - Check no bridged pins or weak shorts on the signal to nearby pins on MCU or temperature sensor - Reflow/resolder the aforementioned components If `CHan` is reading higher - Check ground connections on the sensors - Check no bridged pins or weak shorts on the signal to nearby pins on MCU or temperature sensor - Reflow/resolder the aforementioned components ## No display OR dots on the display If when you power up your iron you get no display, the first test is to (carefully) attempt to heat the tip. Press the front button (`+/A`) on your device and check if the tip heats up. If the tip does not heat up, it is worth trying to reflash the firmware first in case it is corrupted. The main failure mode of the OLED display module is usually poor soldering on the OLED display cable to the main PCB. As this is soldered by hand generally, it's the most prone to failures. If you have a poor connection or a floating pin, you can end up with a state where the screen works _sometimes_ and then freezes or only works on some power cycles. It might work on very old versions of IronOS but not the newest ones. You could try to reflow the pins for the OLED. On 96x16 screens, carefully peel it back from the adhesive and reflow the solder on the pins. As the OLED runs on an I2C bus, there are pull up resistors on the SDA and SCL pins. It is worth checking these as well, while they don't often fail, issues with these can cause _weird_ display issues. If after all of the checks OLED is still blank, or screen works but pixels are barely visible, although soldering iron itself is working (i.e., you can safely check that it's turning on, heating up & melting solder successfully), then it means that _most likely_ OLED is dead. But it can be relatively easily replaced. Models like `TS100`, `TS80`, and `TS80P` share the same OLED screen which can be bought online and used for replacement. To do so: - find & buy at electronics shop [of your choice] display with the following spec line: ```OLED 0.69 inch / 14 pins / 96 x 16 pixels / **9616TSWC** / I2C IIC``` - disassemble your soldering iron; - desolder old OLED and solder back new one; - assemble your soldering iron back. There are a few youtube videos how to do it like [this one for `TS100`](https://www.youtube.com/watch?v=HlWAY0oYPFI). Unfortunately, this is a well-known issue of screens with OLED technology: sooner or later the brightness is starting to _"fade out"_ until complete off. Usually common recommendations to prolong its lifetime are: reduce brightness & reduce too often updates (i.e., disable animations). But your results may vary since there were reports when users couldn't see anything after turning on soldering irons which were just laying in a box for a few months after buying. And there are users with first `TS100` models not having any issues with display at all. ## Tip heats when not in heating mode ⚠️ DISCONNECT YOUR TIP ⚠️ Most likely you have either a blown MOSFET or shorted pin. Check the MOSFET and also its driver transistor. The firmware will not enable the tip until you are in soldering mode. ## Accelerometer not detected Your Iron may have a new accelerometer that is not supported yet (happens every year or so) OR there is a soldering issue with the accelerometer (reflow/resolder). ================================================ FILE: Documentation/WS2812BModding.md ================================================ # WS2812B RGB Modding (Pinecil V2) ## What is it? The idea of this mod is to bring the RGB feature of the MHP30 to the Pinecil V2. Use a transparent shell for a better effect. Pinecil V2 has a free GPIO_12 accessible through TP10, which is along the screen, cf [Pinecil PCB placement v2.0](https://files.pine64.org/doc/Pinecil/Pinecil_PCB_placement_v2.0_20220608.pdf) page 3. (TP9 (GPIO_14) is also available but hidden below the screen. If you want to use it, change `WS2812B_Pin` in `source/Core/BSP/Pinecilv2/Pins.h`.) We'll using it to drive a WS2812B and let the color logic already present for the MHP30 do its magic: - green when temperature is safe (< 55°C) - pulsing red when heating - solid red when desired temperature is reached - orange when cooling down ## Electrical considerations WS2812B requires a Vdd between 3.5 and 5.3V and Vih (high level of input signal) must be at least 0.7*Vdd. Pinecil V2 GPIO levels are 3.3V and the 5V rail is actually max 4.6V. So we can directly power the WS2812B on the 5V rail and command it with the GPIO without need for a level shifter, or for a Zener diode to clamp Vdd. ## How to wire it? - WS2812B pin 1 (Vdd) is connected to the "5V" rail, e.g. on the C8 capacitor as illustrated [here](https://github.com/Ralim/IronOS/issues/1410#issuecomment-1296064392). - WS2812B pin 3 (Vss) is connected to the Pinecil GND, e.g. on the U10 pad at the back of the PCB, below R35, as illustrated [here](https://github.com/Ralim/IronOS/issues/1410#issuecomment-1296064392). - WS2812B pin 4 (Din) is connected to TP10. You can use e.g. 0.1-mm enameled wire and isolate connections with UV glue to avoid any shortcut. ## How to enable it in the code? `make firmware-EN model=Pinecilv2 ws2812b_enable=1` ================================================ FILE: Documentation/index.md ================================================ # IronOS - Flexible Soldering iron control Firmware The firmware implements all of the standard features of a 'smart' soldering iron, with lots of little extras and tweaks. I highly recommend reading the installation guide fully when installing on your iron. And after install just explore the settings menu. For soldering irons that are designed to be powered by 'smart' power sources (PD and QC), the firmware supports settings around the negotiated power and voltage. For soldering irons that are designed to be powered by batteries (TS100 & Pinecil), settings for a cutoff voltage for battery protection are supported. Currently **31** languages are supported. When downloading the firmware for your soldering iron, take note of the language code in the file name. This project is considered stable & feature complete for everyday use with a supported device, _so please suggest any feature improvements you would like!_ _This firmware does **NOT** support the USB port while running for changing settings. This is done through the onscreen menu only. Logos are edited on a computer and flashed like firmware._ | Device | DC | QC | PD | EPR | BLE | Battery | Recommended | | :--------: | :-: | :-: | :-: | :-: | :-: | :-----: | :---------: | | MHP30 | ❌ | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | | Pinecil V1 | ✔️ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ❌ | | Pinecil V2 | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | | TS80P | ❌ | ✔️ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | | TS100 | ✔️ | ❌ | ❌ | ❌ | ❌ | ✔️ | ❌ | | TS80 | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | ❌ | \*Please note that Miniware started shipping TS100's using cloned STM32 Chips. While these do work with IronOS, their DFU bootloader works terribly, and it is hard to get it to successfully flash larger firmware images like IronOS without timing out. This is the main reason why the TS100 is **_no longer recommended_**. ## Getting Started To get started with IronOS firmware, please jump to [Getting Started Guide](https://ralim.github.io/IronOS/GettingStarted/). But the [TL;DR](https://www.merriam-webster.com/dictionary/TL%3BDR) is to press the button near the front of the iron to heat up. Use the button near the back of the iron to enter the settings menu. Long hold the rear button in soldering mode to exit back to the start screen. ## Installation For notes on installation for your device, please refer to the flashing guide for your device: - [MHP30](https://ralim.github.io/IronOS/Flashing/MHP30) - [Pinecil V1](https://ralim.github.io/IronOS/Flashing/Pinecil%20V1/) - [Pinecil V2](https://ralim.github.io/IronOS/Flashing/Pinecil%20V2/) - [TS80 / TS80P](https://ralim.github.io/IronOS/Flashing/TS80%28P%29/) - [TS100](https://ralim.github.io/IronOS/Flashing/TS100) But the _generic_ [TL;DR](https://www.merriam-webster.com/dictionary/TL%3BDR) is to: - [download firmware from here](https://github.com/Ralim/IronOS/releases) for the correct model with suitable language support; - put a device into DFU/bootloader mode (usually by keep holding A/+/front button while connecting a device to power source to power device on); - flash the firmware by drag-n-drop the firmware file using a file manager of your OS **or** using a separate flashing tool. ## Key Features - PID style iron temperature control - Automatic sleep with selectable sensitivity - Motion wake support - All settings exposed in the intuitive menu - (TS100) Set a voltage lower limit for Lithium batteries so you don't kill your battery pack - (TS80) Set 18 W or 24 W settings for your power bank - (TS80P) Automatically negotiates appropriate PD and falls back to QC mode like TS80 - (Pinecil) Supports all 3 power modes (PD, QC, DC In). - (Pinecilv2) Supports USB-PD EPR for 28V operation. - Improved readability Fonts, supporting multiple languages - Use hardware features to improve reliability - Can disable movement detection if desired - Boost mode lets you temporarily change the temperature when soldering (i.e. raise the temperature for short periods) - (TS100/Pinecil) Battery charge level indicator if power source set to a lipo cell count - (TS80/TS80P/Pinecil) Power bank operating voltage is displayed - [Custom boot up logo support](https://ralim.github.io/IronOS/Logo/) - Automatic LCD rotation based on the orientation ## Menu System This new firmware uses a new menu system to allow access to the settings on the device. When on the main screen and having the tip plugged in, the unit shows a pair of prompts for the two most common operations. - Pressing the button near the tip enters the _soldering mode_ - Pressing the button near the USB end enters the _settings menu_ - When not in _soldering mode_, holding down the button near the tip will enter _soldering temperature adjust mode_ (This is the same as the one in the _soldering mode_, but allows to adjust the temperature before heating up), in _soldering mode_ however this will activate _boost mode_ as long as you hold down the button. - Holding down the button near the USB end will show the _[debug menu](https://ralim.github.io/IronOS/DebugMenu/)._ In _soldering mode_ this ends the heating. Operation details are over in the [Menu information.](https://ralim.github.io/IronOS/Menu/) ## Feedback If you would like to: - report any issue related to IronOS - request a feature - provide some suggestion then you can [fill this form](https://github.com/Ralim/IronOS/issues/new/choose) using github account\*. And if you would like to: - ask more generic question about IronOS/supported hardware/something you're curious about/etc. - reach out community to chat with - share your soldering & DIY skills - share some interesting finding - share useful related hardware/software with others or _anything_ like that, then you can use forum-like [Discussions here](https://github.com/Ralim/IronOS/discussions). \*: You may need to create it first if you don't have one - it's free of charge. ================================================ FILE: Env.yml ================================================ name: "ironos" services: builder: stdin_open: true tty: true build: context: . dockerfile: scripts/IronOS.Dockerfile command: /bin/sh volumes: - ./:/build/ironos:Z ================================================ FILE: LICENSE ================================================ GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc. Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The GNU General Public License is a free, copyleft license for software and other kinds of works. The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program--to make sure it remains free software for all its users. We, the Free Software Foundation, use the GNU General Public License for most of our software; it applies also to any other work released this way by its authors. You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. 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Developers that use the GNU GPL protect your rights with two steps: (1) assert copyright on the software, and (2) offer you this License giving you legal permission to copy, distribute and/or modify it. For the developers' and authors' protection, the GPL clearly explains that there is no warranty for this free software. For both users' and authors' sake, the GPL requires that modified versions be marked as changed, so that their problems will not be attributed erroneously to authors of previous versions. Some devices are designed to deny users access to install or run modified versions of the software inside them, although the manufacturer can do so. This is fundamentally incompatible with the aim of protecting users' freedom to change the software. The systematic pattern of such abuse occurs in the area of products for individuals to use, which is precisely where it is most unacceptable. Therefore, we have designed this version of the GPL to prohibit the practice for those products. If such problems arise substantially in other domains, we stand ready to extend this provision to those domains in future versions of the GPL, as needed to protect the freedom of users. Finally, every program is threatened constantly by software patents. States should not allow patents to restrict development and use of software on general-purpose computers, but in those that do, we wish to avoid the special danger that patents applied to a free program could make it effectively proprietary. To prevent this, the GPL assures that patents cannot be used to render the program non-free. The precise terms and conditions for copying, distribution and modification follow. TERMS AND CONDITIONS 0. Definitions. "This License" refers to version 3 of the GNU General Public License. "Copyright" also means copyright-like laws that apply to other kinds of works, such as semiconductor masks. "The Program" refers to any copyrightable work licensed under this License. Each licensee is addressed as "you". "Licensees" and "recipients" may be individuals or organizations. To "modify" a work means to copy from or adapt all or part of the work in a fashion requiring copyright permission, other than the making of an exact copy. The resulting work is called a "modified version" of the earlier work or a work "based on" the earlier work. A "covered work" means either the unmodified Program or a work based on the Program. To "propagate" a work means to do anything with it that, without permission, would make you directly or secondarily liable for infringement under applicable copyright law, except executing it on a computer or modifying a private copy. Propagation includes copying, distribution (with or without modification), making available to the public, and in some countries other activities as well. To "convey" a work means any kind of propagation that enables other parties to make or receive copies. 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The Corresponding Source for a work in source code form is that same work. 2. Basic Permissions. All rights granted under this License are granted for the term of copyright on the Program, and are irrevocable provided the stated conditions are met. This License explicitly affirms your unlimited permission to run the unmodified Program. The output from running a covered work is covered by this License only if the output, given its content, constitutes a covered work. This License acknowledges your rights of fair use or other equivalent, as provided by copyright law. You may make, run and propagate covered works that you do not convey, without conditions so long as your license otherwise remains in force. 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You may convey verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice; keep intact all notices stating that this License and any non-permissive terms added in accord with section 7 apply to the code; keep intact all notices of the absence of any warranty; and give all recipients a copy of this License along with the Program. You may charge any price or no price for each copy that you convey, and you may offer support or warranty protection for a fee. 5. Conveying Modified Source Versions. You may convey a work based on the Program, or the modifications to produce it from the Program, in the form of source code under the terms of section 4, provided that you also meet all of these conditions: a) The work must carry prominent notices stating that you modified it, and giving a relevant date. b) The work must carry prominent notices stating that it is released under this License and any conditions added under section 7. This requirement modifies the requirement in section 4 to "keep intact all notices". c) You must license the entire work, as a whole, under this License to anyone who comes into possession of a copy. This License will therefore apply, along with any applicable section 7 additional terms, to the whole of the work, and all its parts, regardless of how they are packaged. This License gives no permission to license the work in any other way, but it does not invalidate such permission if you have separately received it. d) If the work has interactive user interfaces, each must display Appropriate Legal Notices; however, if the Program has interactive interfaces that do not display Appropriate Legal Notices, your work need not make them do so. A compilation of a covered work with other separate and independent works, which are not by their nature extensions of the covered work, and which are not combined with it such as to form a larger program, in or on a volume of a storage or distribution medium, is called an "aggregate" if the compilation and its resulting copyright are not used to limit the access or legal rights of the compilation's users beyond what the individual works permit. Inclusion of a covered work in an aggregate does not cause this License to apply to the other parts of the aggregate. 6. Conveying Non-Source Forms. You may convey a covered work in object code form under the terms of sections 4 and 5, provided that you also convey the machine-readable Corresponding Source under the terms of this License, in one of these ways: a) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by the Corresponding Source fixed on a durable physical medium customarily used for software interchange. b) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by a written offer, valid for at least three years and valid for as long as you offer spare parts or customer support for that product model, to give anyone who possesses the object code either (1) a copy of the Corresponding Source for all the software in the product that is covered by this License, on a durable physical medium customarily used for software interchange, for a price no more than your reasonable cost of physically performing this conveying of source, or (2) access to copy the Corresponding Source from a network server at no charge. c) Convey individual copies of the object code with a copy of the written offer to provide the Corresponding Source. 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If you convey an object code work under this section in, or with, or specifically for use in, a User Product, and the conveying occurs as part of a transaction in which the right of possession and use of the User Product is transferred to the recipient in perpetuity or for a fixed term (regardless of how the transaction is characterized), the Corresponding Source conveyed under this section must be accompanied by the Installation Information. But this requirement does not apply if neither you nor any third party retains the ability to install modified object code on the User Product (for example, the work has been installed in ROM). The requirement to provide Installation Information does not include a requirement to continue to provide support service, warranty, or updates for a work that has been modified or installed by the recipient, or for the User Product in which it has been modified or installed. Access to a network may be denied when the modification itself materially and adversely affects the operation of the network or violates the rules and protocols for communication across the network. Corresponding Source conveyed, and Installation Information provided, in accord with this section must be in a format that is publicly documented (and with an implementation available to the public in source code form), and must require no special password or key for unpacking, reading or copying. 7. Additional Terms. "Additional permissions" are terms that supplement the terms of this License by making exceptions from one or more of its conditions. Additional permissions that are applicable to the entire Program shall be treated as though they were included in this License, to the extent that they are valid under applicable law. If additional permissions apply only to part of the Program, that part may be used separately under those permissions, but the entire Program remains governed by this License without regard to the additional permissions. When you convey a copy of a covered work, you may at your option remove any additional permissions from that copy, or from any part of it. (Additional permissions may be written to require their own removal in certain cases when you modify the work.) You may place additional permissions on material, added by you to a covered work, for which you have or can give appropriate copyright permission. Notwithstanding any other provision of this License, for material you add to a covered work, you may (if authorized by the copyright holders of that material) supplement the terms of this License with terms: a) Disclaiming warranty or limiting liability differently from the terms of sections 15 and 16 of this License; or b) Requiring preservation of specified reasonable legal notices or author attributions in that material or in the Appropriate Legal Notices displayed by works containing it; or c) Prohibiting misrepresentation of the origin of that material, or requiring that modified versions of such material be marked in reasonable ways as different from the original version; or d) Limiting the use for publicity purposes of names of licensors or authors of the material; or e) Declining to grant rights under trademark law for use of some trade names, trademarks, or service marks; or f) Requiring indemnification of licensors and authors of that material by anyone who conveys the material (or modified versions of it) with contractual assumptions of liability to the recipient, for any liability that these contractual assumptions directly impose on those licensors and authors. All other non-permissive additional terms are considered "further restrictions" within the meaning of section 10. If the Program as you received it, or any part of it, contains a notice stating that it is governed by this License along with a term that is a further restriction, you may remove that term. If a license document contains a further restriction but permits relicensing or conveying under this License, you may add to a covered work material governed by the terms of that license document, provided that the further restriction does not survive such relicensing or conveying. If you add terms to a covered work in accord with this section, you must place, in the relevant source files, a statement of the additional terms that apply to those files, or a notice indicating where to find the applicable terms. Additional terms, permissive or non-permissive, may be stated in the form of a separately written license, or stated as exceptions; the above requirements apply either way. 8. Termination. You may not propagate or modify a covered work except as expressly provided under this License. Any attempt otherwise to propagate or modify it is void, and will automatically terminate your rights under this License (including any patent licenses granted under the third paragraph of section 11). However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation. Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice. Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, you do not qualify to receive new licenses for the same material under section 10. 9. Acceptance Not Required for Having Copies. You are not required to accept this License in order to receive or run a copy of the Program. Ancillary propagation of a covered work occurring solely as a consequence of using peer-to-peer transmission to receive a copy likewise does not require acceptance. However, nothing other than this License grants you permission to propagate or modify any covered work. These actions infringe copyright if you do not accept this License. Therefore, by modifying or propagating a covered work, you indicate your acceptance of this License to do so. 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and propagate that work, subject to this License. You are not responsible for enforcing compliance by third parties with this License. An "entity transaction" is a transaction transferring control of an organization, or substantially all assets of one, or subdividing an organization, or merging organizations. If propagation of a covered work results from an entity transaction, each party to that transaction who receives a copy of the work also receives whatever licenses to the work the party's predecessor in interest had or could give under the previous paragraph, plus a right to possession of the Corresponding Source of the work from the predecessor in interest, if the predecessor has it or can get it with reasonable efforts. You may not impose any further restrictions on the exercise of the rights granted or affirmed under this License. For example, you may not impose a license fee, royalty, or other charge for exercise of rights granted under this License, and you may not initiate litigation (including a cross-claim or counterclaim in a lawsuit) alleging that any patent claim is infringed by making, using, selling, offering for sale, or importing the Program or any portion of it. 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. The work thus licensed is called the contributor's "contributor version". A contributor's "essential patent claims" are all patent claims owned or controlled by the contributor, whether already acquired or hereafter acquired, that would be infringed by some manner, permitted by this License, of making, using, or selling its contributor version, but do not include claims that would be infringed only as a consequence of further modification of the contributor version. For purposes of this definition, "control" includes the right to grant patent sublicenses in a manner consistent with the requirements of this License. Each contributor grants you a non-exclusive, worldwide, royalty-free patent license under the contributor's essential patent claims, to make, use, sell, offer for sale, import and otherwise run, modify and propagate the contents of its contributor version. In the following three paragraphs, a "patent license" is any express agreement or commitment, however denominated, not to enforce a patent (such as an express permission to practice a patent or covenant not to sue for patent infringement). To "grant" such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party. If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. "Knowingly relying" means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid. If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it. A patent license is "discriminatory" if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007. Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program. 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License "or any later version" applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . Also add information on how to contact you by electronic and paper mail. If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: Copyright (C) This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an "about box". You should also get your employer (if you work as a programmer) or school, if any, to sign a "copyright disclaimer" for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . ================================================ FILE: Makefile ================================================ #!/usr/bin/env make INFO:=top-level Makefile for IronOS - Soldering Iron Open Source Firmware Project. ### global adjustable variables # command for "docker compose" from DOCKER env. var. ifdef DOCKER DOCKER_BIN:=$(DOCKER) else DOCKER_BIN:= endif # detect availability of docker ifndef DOCKER_BIN DOCKER_COMPOSE:=$(shell command -v docker-compose 2>/dev/null) DOCKER_TOOL:=$(shell command -v docker 2>/dev/null) ifdef DOCKER_COMPOSE DOCKER_BIN:=$(DOCKER_COMPOSE) else ifdef DOCKER_TOOL DOCKER_BIN:=$(DOCKER_TOOL) compose endif # DOCKER_* checks endif # DOCKER_BIN # command for python-based mkdocs tool ifndef MKDOCS MKDOCS:=mkdocs endif # build output related directories ifdef OUT OUT_DIR=$(OUT) else OUT_DIR=$(CURDIR)/BUILDS endif OUT_HEX=$(CURDIR)/source/Hexfile ### global static variables # docker-related files DOCKER_YML=$(CURDIR)/Env.yml DOCKER_FILE=$(CURDIR)/scripts/IronOS.Dockerfile # docker dependencies DOCKER_DEPS=$(DOCKER_YML) $(DOCKER_FILE) # compose docker-compose command DOCKER_CMD=$(DOCKER_BIN) -f $(DOCKER_YML) run --rm builder # MkDocs config MKDOCS_YML=$(CURDIR)/scripts/IronOS-mkdocs.yml # supported models MODELS=TS100 TS80 TS80P Pinecil MHP30 Pinecilv2 S60 TS101 S60P T55 # target names & dir names MODELS_ML=Pinecil Pinecilv2 # target names MODELS_MULTILANG=Pinecil_multi-lang Pinecilv2_multi-lang # dir names # zip command (to pack artifacts) ZIP=zip -q -j -r ### targets # default target to show help help: @echo @echo "Welcome!" @echo "This is $(INFO)" @echo "To read more about supported commands (aka \"targets\"), type \"make list\"." @echo "But if you're impatient then just type \"make docker-build\" - it will:" @echo " * download, configure & start docker container" @echo " * compile builds of IronOS firmware for all supported models inside that container" @echo " * export generated binaries to \"scripts/ci/artefacts/\" local directory" @echo "Patches are welcome. Happy Hacking!" @echo # target to list supported targets with additional info list: @echo @echo "Supported top-level targets:" @echo " * help - shows short basic help" @echo " * list - this output" @echo " * docker-shell - start docker container with shell inside to work on IronOS with all tools needed" @echo " * docker-build - compile builds of IronOS for supported models inside docker container and place them to $(OUT_DIR) (set OUT env var to override: OUT=/path/to/dir make ...)" @echo " * docker-clean - delete created docker image for IronOS & its build cache objects (to free a lot of space)" @echo " * docker-clean-cache - delete build cache objects of IronOS docker image EXCEPT the image itself" @echo " * docker-clean-image - delete docker image for IronOS EXCEPT its build cache objects" @echo " * docs - generate \"site\"/ directory with documentation in a form of static html files using ReadTheDocs framework and $(MKDOCS_YML) local config file" @echo " * docs-deploy - generate & deploy docs online to gh-pages branch of current github repo" @echo " * tests - run set of checks, linters & tests (equivalent of github CI IronOS project settings for push trigger)" @echo " * clean-build - delete generated files & dirs produced during builds EXCEPT docker image & its build cache" @echo " * clean-full - delete generated files & dirs produced during builds INCLUDING docker image & its build cache" @echo "" @echo "NOTES on supported pass-trough targets:" @echo " * main Makefile is located in source/ directory and used to build the firmware itself;" @echo " * this top-level Makefile supports to call targets from source/Makefile;" @echo " * if you set up development environment right on your host, then to build firmware locally, you can just type right from here:" @echo @echo " $$ make firmware-LANG_ID model=MODEL_ID" @echo @echo "Full list of current supported IDs:" @echo " * LANG_ID: $(shell echo "`ls Translations/ | grep -e "^translation_.*.json$$" | sed -e 's,^translation_,,g; s,\.json$$,,g; ' | tr '\n' ' '`")" @echo " * MODEL_ID: $(MODELS)" @echo @echo "For example, to make a local build of IronOS firmware for TS100 with English language, just type:" @echo @echo " $$ make firmware-EN model=TS100" @echo # detect availability of docker docker-check: ifeq ($(DOCKER_BIN),) @echo "ERROR: Can't find docker-compose nor docker tool. Please, install docker and try again" @exit 1 else @true endif # former start_dev.sh docker-shell: docker-check $(DOCKER_DEPS) $(DOCKER_CMD) # former build.sh docker-build: docker-check $(DOCKER_DEPS) $(DOCKER_CMD) make build-all # delete docker image docker-clean-image: -docker rmi ironos-builder:latest # delete docker build cache objects docker-clean-cache: -docker system prune --filter label=ironos-builder:latest --force # delete docker image & cache related to IronOS container docker-clean: docker-clean-image docker-clean-cache # generate docs in site/ directory (DIR for -d is relative to mkdocs.yml file location, hence use default name/location site by setting up ../site) docs: $(MKDOCS_YML) Documentation/* Documentation/Flashing/* Documentation/images/* $(MKDOCS) build -f $(MKDOCS_YML) -d ../site # deploy docs to gh-pages branch of current repo automagically using ReadTheDocs framework docs-deploy: $(MKDOCS_YML) Documentation/* Documentation/Flashing/* Documentation/images/* $(MKDOCS) gh-deploy -f $(MKDOCS_YML) -d ../site # routine check to verify documentation test-md: @echo "" @echo "---- Checking documentation... ----" @echo "" @./scripts/deploy.sh docs # shell style & linter check (github CI version of shellcheck is more recent than alpine one so the latter may not catch some policies) test-sh: @echo "" @echo "---- Checking shell scripts... ----" @echo "" @for f in `find ./scripts -type f -iname "*.sh" ! -name "flash_ts100_linux.sh"` ; do shellcheck "$${f}"; done; # python-related tests & checks test-py: @echo "" @echo "---- Checking python code... ----" @echo "" flake8 Translations black --diff --check Translations @$(MAKE) -C source/ Objects/host/brieflz/libbrieflz.so ./Translations/brieflz_test.py ./Translations/make_translation_test.py # clang-format check for C/C++ code style test-ccpp: @echo "" @echo "---- Checking C/C++ code... ----" @echo "" $(MAKE) -C source/ clean check-style # meta target for tests & checks based on .github/workflows/push tests: test-md test-sh test-py test-ccpp @echo "" @echo "All tests & checks have been completed successfully." @echo "" # former scripts/ci/buildAll.sh - all in one to build all firmware & place the produced binaries into one output directory build-all: @mkdir -p $(OUT_DIR) @chmod 0777 $(OUT_DIR) cd source && bash ./build.sh @echo "All Firmware built" @for model in $(MODELS); do \ mkdir -p $(OUT_DIR)/$${model} ; \ cp -r $(OUT_HEX)/$${model}_*.bin $(OUT_DIR)/$${model}/ ; \ cp -r $(OUT_HEX)/$${model}_*.hex $(OUT_DIR)/$${model}/ ; \ cp -r $(OUT_HEX)/$${model}_*.dfu $(OUT_DIR)/$${model}/ ; \ done; @echo "Resulting output directory: $(OUT_DIR)" # target to build multilang supported builds for Pinecil & PinecilV2 build-multilang: @for modelml in $(MODELS_ML); do \ $(MAKE) -C source/ -j2 model=$${modelml} firmware-multi_compressed_European firmware-multi_compressed_Belarusian+Bulgarian+Russian+Serbian+Ukrainian firmware-multi_Chinese+Japanese ; \ mkdir -p $(OUT_DIR)/$${modelml}_multi-lang ; \ cp $(OUT_HEX)/$${modelml}_multi_*.bin $(OUT_DIR)/$${modelml}_multi-lang ; \ cp $(OUT_HEX)/$${modelml}_multi_*.hex $(OUT_DIR)/$${modelml}_multi-lang ; \ cp $(OUT_HEX)/$${modelml}_multi_*.dfu $(OUT_DIR)/$${modelml}_multi-lang ; \ done; @echo "Resulting output directory: $(OUT_DIR)" # target to reproduce zips according to github CI settings; artifacts will be in $(OUT_DIR)/CI/*.zip ci: tests build-all build-multilang @mkdir -p $(OUT_DIR)/metadata; @for m in $(MODELS) $(MODELS_MULTILANG); do \ cp LICENSE scripts/LICENSE_RELEASE.md $(OUT_DIR)/$${m}/ ; \ $(ZIP) $(OUT_DIR)/$${m}.zip $(OUT_DIR)/$${m} ; \ ./source/metadata.py $${m}.json $${m}; \ cp $(OUT_HEX)/$${m}.json $(OUT_DIR)/metadata; \ done; @$(ZIP) $(OUT_DIR)/metadata.zip $(OUT_DIR)/metadata @mkdir -p $(OUT_DIR)/CI @mv $(OUT_DIR)/*.zip $(OUT_DIR)/CI @chmod 0777 $(OUT_DIR)/CI @chmod 0666 $(OUT_DIR)/CI/*.zip @echo "Resulting artifacts directory: $(OUT_DIR)/CI" # pass-through target for Makefile inside source/ dir %: $(MAKE) -C source/ $@ # global clean-up target for produced/generated files inside tree clean-build: $(MAKE) -C source/ clean-all rm -Rf site rm -Rf $(OUT_DIR) # global clean-up target clean-full: clean-build docker-clean # phony targets .PHONY: help list .PHONY: docker-check docker-shell docker-build docker-clean-image docker-clean-cache docker-clean .PHONY: docs docs-deploy .PHONY: test-md test-sh test-py test-ccpp tests .PHONY: build-all build-multilang ci .PHONY: clean-build clean-full ================================================ FILE: README.md ================================================ [![CI Build](https://github.com/Ralim/IronOS/actions/workflows/push.yml/badge.svg)](https://github.com/Ralim/IronOS/actions/workflows/push.yml) [![Total Downloads](https://img.shields.io/github/downloads/ralim/IronOS/total)](https://github.com/Ralim/IronOS) [![Contributors](https://img.shields.io/github/contributors-anon/ralim/ironos?color=blue&style=flat)](https://github.com/Ralim/IronOS/graphs/contributors) [![Latest Release](https://img.shields.io/github/v/release/ralim/IronOS)](https://github.com/Ralim/IronOS/releases/latest) # IronOS - Open Source Flexible Firmware for Soldering Hardware _This repository was formerly known as TS100, it's the same great code. Just with more supported devices._ Originally conceived as an alternative firmware for the _TS100_, this firmware has evolved into a complex soldering hardware control firmware. The firmware implements all of the standard features of a _smart_ soldering hardware, with lots of little extras and tweaks. I highly recommend reading the installation guide fully when installing on your device. And after install just explore the settings menu. For soldering hardware that is designed to be powered by _smart_ power sources such as _PD_ or _QC_, the firmware supports settings around the negotiated power and voltage. For soldering hardware that is designed to be powered by batteries (_TS100_ & _Pinecil_), settings for a cutoff voltage for battery protection are supported. Currently **31** languages are supported. When downloading the firmware for your soldering hardware, take note of the _language code_ in the file name. This project is considered feature complete for use on a daily basis, _so please suggest any feature improvements you would like!_ _This firmware does **NOT** support the USB port while running for changing settings (this is done through the onscreen menu only). Custom logos are edited on a computer and flashed in the same manner as firmware._ ## Supported Hardware | Device | DC | QC | PD | EPR\*\*\*\* | BLE | Tip Sense | Recommended Purchase | Notes | | :------------: | :-: | :-: | :-: | :-: | :-: | :-------: | :------------------: | :-------------------------------------: | | Miniware MHP30 | ❌ | ❌ | ✔️ | ❌ | ❌ | ✔️ | ✔️ | | | Pinecil V1 | ✔️ | ✔️ | ✔️ | ❌ | ❌ | ❌ | ❌ \* | | | Pinecil V2 | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | | | Miniware TS101 | ✔️ | ❌ | ✔️ | ✔️ | ❌ | ✔️ | ✔️ \*\*\*\*\* | Full OLED resolution not yet supported. | | Sequre S60 | ❌ | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | Full OLED resolution not yet supported. | | Sequre S60P | ❌ | ❌ | ✔️ | ❌ | ❌ | ❌ | ✔️ | Full OLED resolution not yet supported. | | Sequre T55 | ❌ | ❌ | ✔️ | ❌ | ❌ | N/A | ✔️ | Full OLED resolution not yet supported. | | Miniware TS80P | ❌ | ✔️ | ✔️ | ❌ | ❌ | N/A | ✔️ | | | Miniware TS100 | ✔️ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌\*\* | | | Miniware TS80 | ❌ | ✔️ | ❌ | ❌ | ❌ | N/A | ❌\*\*\* | | _Tip Sense_ refers to the device being able to choose between the _"regular"_ _TS100_ or _Hakko T12 style_ tips and _Pine64_'s custom shorter tips which have lower resistance and allow for more power. This is N/A for _TS80(P)_ as there is only one model of tip for them. _Recommended Purchase_ is only referring to if you are buying a **new** device. Of course all the devices listed are supported and will work excellently for years to come. The _TS101_ & _S60(P)_ irons and _MHP30_ & _T55_ plates feature a higher resolution OLED than other devices. Work is ongoing to support this fully, for now a cropped view is usable. \* _PinecilV1_ stopped being manufactured a long time ago now, all models for sale online are generally clones (or old stock). Vendors are trying to sell these for more than _Pine64_ sells the _V2_ for now. Thus the _V1_ is **_no longer recommended_**. \*\* Please note that _Miniware_ started shipping _TS100_'s using **cloned STM32 chips**. While these do work with _IronOS_, their **DFU bootloader** works terribly, and it is hard to get it to successfully flash larger firmware images like _IronOS_ without timing out. This is the main reason why the _TS100_ is **_no longer recommended_**. \*\*\* _TS80_ is replaced by _TS80P_. Production ramped down a long time ago and it's just existing stock clearing the system. It's marked not recommended being optimistic that people might pause and buy the far superior _TS80P_ instead. This is the main reason why the _TS80_ is **_no longer recommended_**. \*\*\*\* **EPR/PPS with 28V support** is _**disabled by default**_ due to [safety concerns](https://github.com/Ralim/IronOS/pull/2073), but to turn it back on set _PD Mode_ option in _Power settings_ submenu to _Safe_ or _Default_. \*\*\*\*\* Some users confirm that there is a version of newer _TS101_ revision with another OLED screen model, which is not supported yet at all by _IronOS_ unfortunately. See [this bug report](https://github.com/Ralim/IronOS/issues/2063) for more information. ## Getting Started To get started with _IronOS firmware_, please jump to [Getting Started Guide](https://ralim.github.io/IronOS/GettingStarted/). ## Installation For notes on installation for your device, please refer to the flashing guide for your device: - [MHP30](https://ralim.github.io/IronOS/Flashing/MHP30) - [Pinecil V1](https://ralim.github.io/IronOS/Flashing/Pinecil%20V1/) - [Pinecil V2](https://ralim.github.io/IronOS/Flashing/Pinecil%20V2/) - [TS80 / TS80P](https://ralim.github.io/IronOS/Flashing/TS80%28P%29/) - [TS100](https://ralim.github.io/IronOS/Flashing/TS100) ## Builds The links in the table below allow to download available builds directly: - current _Stable Release_ is **`v2.22`**; - _Development Build_ **dynamically** provides _**the latest successful build**_ from **`dev`** branch. | Device | Stable Release | Development Build | |:---------------------:|:--------------:|:-----------------:| | Pinecil V1 | [Pinecil.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/Pinecil.zip) | [Pinecil.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/Pinecil.zip) | | Pinecil V1/multilang | [Pinecil_multi-lang.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/Pinecil_multi-lang.zip) | [Pinecil_multi-lang.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/Pinecil_multi-lang.zip) | | Pinecil V2 | [PinecilV2.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/PinecilV2.zip) | [PinecilV2.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/Pinecilv2.zip) | | Pinecil V2/multilang | [PinecilV2_multi-lang.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/PinecilV2_multi-lang.zip) | [PinecilV2_multi-lang.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/Pinecilv2_multi-lang.zip) | | Miniware TS100 | [TS100.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/TS100.zip) | [TS100.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/TS100.zip) | | Miniware TS101 | [TS101.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/TS101.zip) | [TS101.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/TS101.zip) | | Miniware TS80 | [TS80.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/TS80.zip) | [TS80.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/TS80.zip) | | Miniware TS80P | [TS80P.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/TS80P.zip) | [TS80P.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/TS80P.zip) | | Miniware MHP30 | [MHP30.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/MHP30.zip) | [MHP30.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/MHP30.zip) | | Sequre S60 | [S60.zip](https://github.com/Ralim/IronOS/releases/download/v2.23/S60.zip) | [S60.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/S60.zip) | | Sequre S60P | Not Released | [S60P.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/S60P.zip) | | Sequre T55 | Not Released | [T55.zip](https://nightly.link/Ralim/IronOS/workflows/push/dev/T55.zip) | ## Key Features - PID style iron temperature control; - automatic sleep with selectable sensitivity; - adjustable & tweakable motion wake support; - all settings exposed in the intuitive menu; - (_TS100_) set a voltage lower limit for Lithium batteries so you don't kill your battery pack; - (_TS80_) set 18W or 24W settings for your power bank; - (_TS80P_) automatically negotiates appropriate PD and falls back to QC mode like _TS80_; - (_Pinecil_) supports all 3 power modes (PD, QC, DC In); - (_Pinecilv2_) supports _USB-PD EPR_ for **28V** operation; - improved readability Fonts, supporting multiple languages; - use hardware features to improve reliability; - boost mode lets you temporarily change the temperature when soldering (i.e. raise the temperature for short periods); - (_TS100_/_Pinecil_) battery charge level indicator if power source set to a LiPo cell count; - (_TS80_/_TS80P_/_Pinecil_) power bank operating voltage is displayed; - [custom boot up logo support](https://ralim.github.io/IronOS/Logo/)[^bootlogo]; - automatic LCD rotation based on the orientation; - ... and many many other cool & hackable features![^changelog] [^bootlogo]: **BOOTUP LOGO NOTICE**: IronOS supports both a bootup logo _AND_ bootup animations. However, _**they are no longer included in this repo**_. **Please, [read the docs](https://ralim.github.io/IronOS/Logo/) for more information**. [^changelog]: [See the full changelog here](https://ralim.github.io/IronOS/History). ## Basic Control Supported device is controlled by two buttons which can be pressed in the following ways: - short: ~1 second or so; - long: more than 1 second; - both (press & hold both of them together). Available buttons are: - `+/A` button: near the front closer to the tip (for irons) or on the left side of the device (for plates); - `-/B` button: near the back far from the tip (for irons) or on the right side of the device (for plates). After powering on the device for the first time with _IronOS_ installed and having the tip/plate plugged in, on the main menu in _standby mode_ the unit shows a pair of prompts for the two most common operations: - pressing the `+/A` button enters the _soldering mode_; - pressing the `-/B` button enters the _settings menu_; - in _soldering mode_: - short press of `+/A` / `-/B` buttons changes the soldering temperature; - long press of the `+/A` button enables _boost mode_ (increasing soldering temperature to the adjustable setting as long as the button is pressed); - long press of the `-/B` button enters _standby mode_ and stops heating; - in _standby mode_: - long press of the `+/A` button enters _soldering temperature adjust mode_ (the same as the one in the _soldering mode_, but allows to adjust the temperature before heating up); - long hold of the `-/B` button enters the [_debug menu_](https://ralim.github.io/IronOS/DebugMenu/); - in _menu mode_ (to make it short here): - `-/B` scrolls & cycles through menus and submenus; - `+/A` enters to menu & submenu settings or changes their values if they are activated already. Additional details are described in the [menu information](https://ralim.github.io/IronOS/Menu/). ## Remote Control ### Pinecil V2 only Pinecil V2 has [_Bluetooth Low Energy_ module](https://ralim.github.io/IronOS/Bluetooth), which is supported by _IronOS_ since `2.21` release to control some of the settings using additional tools like [PineSAM](https://github.com/builder555/PineSAM) or [PineTool](https://github.com/lachlanbell/PineTool). In `2.21` and `2.22` releases the module was _on_ by default. However, **_Bluetooth_ is turned off in the settings by default in current `dev` builds and for 2.23+** [due to security concerns](#1856).[^ble] To enable _Bluetooth_ back: - go to _Settings_ menu; - press `-/B` button four times to scroll the menu for `Advanced settings`; - press `+/A` button to open submenu; - press `+/A` button to toggle/enable _Bluetooth_ feature; - press `-/B` **and hold it** for just more than five seconds to exit from the _Settings_ menu. [^ble]: This is related only to situations when a user restores default settings using menu, or when _IronOS_ update is taking place on a new device or on a device with a previous firmware version. ## Translations Is your preferred language missing localisation of some of the text? Translations are stored as `json` files in the `Translations` folder. _Pull requests_ are loved and accepted to enhance the firmware. ## Thanks If you love this firmware and want to continue my caffeine addiction, you can do so [here](https://paypal.me/RalimTek) (or email me for other options). I also want to give a shout out to all of the [Fantastic Contributors](https://github.com/Ralim/IronOS/graphs/contributors). Especially to the following users, who have helped in various ways that are massively appreciated: - [Dhiltonp](https://github.com/dhiltonp) - [Mrkvozrout](https://github.com/Mrkvozrout) - [JonnieZG](https://github.com/jonnieZG) - [Federck](https://github.com/federck) - [Jvitkauskas](https://github.com/jvitkauskas) - [Doegox](https://github.com/doegox) - [Perillamint](https://github.com/perillamint) - [GeminiServer](https://github.com/GeminiServer) - [Patrick Horlebein](https://github.com/PixelPirate) - [Firebie](https://github.com/Firebie) - [Agatti](https://github.com/agatti) - [Discip](https://github.com/discip) - [Paul Fertser](https://github.com/paulfertser) Plus the huge number of people who have contributed translations, your effort is massively appreciated. ## License The code created by the community is covered by the [GNU GPLv3](https://www.gnu.org/licenses/gpl-3.0.html#license-text) license **unless noted elsewhere**. Other components such as _FreeRTOS_ and _USB-PD_ have their own licenses. ## Commercial Use This software is provided _**"AS IS"**_, so I cannot provide any commercial support for the firmware. However, you are more than welcome to distribute links to the firmware or provide hardware with this firmware. **Please do not re-host the files, but rather link to this page, so that there are no old versions of the firmware scattered around**. ================================================ FILE: Translations/BitmapEditor.html ================================================ TS100 Bitmap Editor
1x 2x 4x 8x 10x 12x 16x 32x INVERT!
(Remember to set correct canvas size before importing)

================================================ FILE: Translations/README.md ================================================ ### CJK Notes Unlike Latin and Cyrillic scripts, CJK Unified Ideographs cannot be legibly displayed using the small font, which is only 6x8px in size. Therefore, Hanzi, Kanji and Hanja can only be displayed using the 12x16px large font. By default, menu items are shown using two lines of text with the small font. When translating such items for CJK, leave the first line empty and put the translated text on the second line. This way, the firmware will automatically know to display the text using the large font. This also applies to the `SettingsResetMessage` text -- just start the message with `\n`. ================================================ FILE: Translations/brieflz.py ================================================ import ctypes import functools import os from pathlib import Path HERE = Path(__file__).resolve().parent @functools.lru_cache(maxsize=None) def _libbrieflz(): so_path = os.path.join(HERE, "../source/Objects/host/brieflz/libbrieflz.so") libbrieflz = ctypes.cdll.LoadLibrary(so_path) return libbrieflz @functools.lru_cache(maxsize=None) def _fn_blz_max_packed_size(): """Returns the blz_max_packed_size C function. :: /** * Get bound on compressed data size. * * @see blz_pack * * @param src_size number of bytes to compress * @return maximum size of compressed data */ BLZ_API size_t blz_max_packed_size(size_t src_size); """ fn = _libbrieflz().blz_max_packed_size fn.argtype = [ ctypes.c_size_t, ] fn.restype = ctypes.c_size_t return fn def blz_max_packed_size(src_size: int) -> int: """Get bound on compressed data size.""" fn_blz_max_packed_size = _fn_blz_max_packed_size() return int(fn_blz_max_packed_size(src_size)) @functools.lru_cache(maxsize=None) def _fn_blz_workmem_size_level(): """Returns the blz_workmem_size_level C function. :: /** * Get required size of `workmem` buffer. * * @see blz_pack_level * * @param src_size number of bytes to compress * @param level compression level * @return required size in bytes of `workmem` buffer */ BLZ_API size_t blz_workmem_size_level(size_t src_size, int level); """ fn = _libbrieflz().blz_workmem_size_level fn.argtype = [ ctypes.c_size_t, ctypes.c_int, ] fn.restype = ctypes.c_size_t return fn def blz_workmem_size_level(src_size: int, level: int) -> int: """Get required size of `workmem` buffer.""" fn_blz_workmem_size_level = _fn_blz_workmem_size_level() return int(fn_blz_workmem_size_level(src_size, level)) @functools.lru_cache(maxsize=None) def _fn_blz_pack_level(): """Returns the blz_pack_level C function. :: /** * Compress `src_size` bytes of data from `src` to `dst`. * * Compression levels between 1 and 9 offer a trade-off between * time/space and ratio. Level 10 is optimal but very slow. * * @param src pointer to data * @param dst pointer to where to place compressed data * @param src_size number of bytes to compress * @param workmem pointer to memory for temporary use * @param level compression level * @return size of compressed data */ BLZ_API unsigned long blz_pack_level(const void *src, void *dst, unsigned long src_size, void *workmem, int level); """ fn = _libbrieflz().blz_pack_level fn.argtype = [ ctypes.c_char_p, ctypes.c_char_p, ctypes.c_ulong, ctypes.c_char_p, ctypes.c_int, ] fn.restype = ctypes.c_ulong return fn def compress(data: bytes) -> bytes: """Returns a bytes object of the brieflz-compressed data.""" fn_blz_pack_level = _fn_blz_pack_level() output_buffer_len = blz_max_packed_size(len(data)) src = data dst = ctypes.create_string_buffer(output_buffer_len) src_size = len(src) workmem = ctypes.create_string_buffer(blz_workmem_size_level(len(data), 10)) level = 10 res = fn_blz_pack_level(src, dst, src_size, workmem, level) if res == 0: raise BriefLZError() else: return bytes(dst[:res]) # type: ignore @functools.lru_cache(maxsize=None) def _fn_blz_depack_srcsize(): """Returns the blz_depack_srcsize C function. :: /** * Decompress `src_size` bytes of data from `src` to `dst`. * * This function is unsafe. If the provided data is malformed, it may * read more than `src_size` from the `src` buffer. * * @param src pointer to compressed data * @param dst pointer to where to place decompressed data * @param src_size size of the compressed data * @return size of decompressed data */ BLZ_API unsigned long blz_depack_srcsize(const void *src, void *dst, unsigned long src_size); """ fn = _libbrieflz().blz_depack_srcsize fn.argtype = [ ctypes.c_char_p, ctypes.c_char_p, ctypes.c_ulong, ] fn.restype = ctypes.c_ulong return fn def depack_srcsize(data: bytes, expected_depack_size: int) -> bytes: """Returns a bytes object of the uncompressed data.""" fn_blz_depack_srcsize = _fn_blz_depack_srcsize() output_buffer_len = expected_depack_size * 2 src = data dst = ctypes.create_string_buffer(output_buffer_len) src_size = len(src) res = fn_blz_depack_srcsize(src, dst, src_size) if res == 0: raise BriefLZError() else: return bytes(dst[:res]) # type: ignore class BriefLZError(Exception): """Exception raised for brieflz compression or decompression error.""" def __init__(self): pass ================================================ FILE: Translations/brieflz_test.py ================================================ #!/usr/bin/env python3 import brieflz import unittest TEST_DATA = ( b"Lorem ipsum dolor sit amet, consectetur adipiscing elit. " b"Ut consequat mattis orci ac laoreet. Duis ac turpis tempus, varius lacus non, dignissim lectus. " b"Curabitur quis metus luctus, sollicitudin ipsum at, dictum metus. " b"Cras sed est nec ex tempor tincidunt in at ante. Vivamus laoreet urna eget lectus euismod feugiat. " b"Duis a massa ac metus pellentesque interdum. Nunc congue, est faucibus convallis commodo, justo nibh sagittis augue, sed tristique urna neque vitae urna. " b"Donec quis orci et purus imperdiet sollicitudin." ) class TestBriefLZ(unittest.TestCase): def test_roundtrip(self): packed = brieflz.compress(TEST_DATA) depacked = brieflz.depack_srcsize(packed, len(TEST_DATA)) self.assertEqual(depacked, TEST_DATA) if __name__ == "__main__": unittest.main() ================================================ FILE: Translations/font_tables.py ================================================ from typing import Dict, Final, Tuple def get_font_map_ascii_basic() -> Dict[str, bytes]: font = { # U+0000..U+007F Basic Latin " ": b"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "!": b"\x00\x00\x00\x00\x7C\xFF\xFF\x7C\x00\x00\x00\x00\x00\x00\x00\x00\x00\x33\x33\x00\x00\x00\x00\x00", '"': b"\x00\x00\x00\x3C\x3C\x00\x00\x3C\x3C\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "#": b"\x00\x00\x10\x90\xF0\x7E\x1E\x90\xF0\x7E\x1E\x10\x00\x02\x1E\x1F\x03\x02\x1E\x1F\x03\x02\x00\x00", "$": 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b"\x00\xE0\xE0\x00\x00\x00\x00\x00\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "v": b"\x00\x60\xE0\x80\x00\x00\x00\x00\x80\xE0\x60\x00\x00\x00\x01\x07\x1E\x38\x38\x1E\x07\x01\x00\x00", "w": b"\x00\xE0\xE0\x00\x00\xE0\xE0\x00\x00\xE0\xE0\x00\x00\x07\x1F\x38\x1C\x0F\x0F\x1C\x38\x1F\x07\x00", "x": b"\x00\x60\xE0\xC0\x80\x00\x80\xC0\xE0\x60\x00\x00\x00\x30\x38\x1D\x0F\x07\x0F\x1D\x38\x30\x00\x00", "y": b"\x00\x00\x60\xE0\x80\x00\x00\x80\xE0\x60\x00\x00\x00\x00\x00\x81\xE7\x7E\x1E\x07\x01\x00\x00\x00", "z": b"\x00\x60\x60\x60\x60\x60\xE0\xE0\x60\x20\x00\x00\x00\x30\x38\x3C\x36\x33\x31\x30\x30\x30\x00\x00", "{": b"\x00\x00\x80\xC0\xFC\x7E\x07\x03\x03\x03\x00\x00\x00\x00\x00\x01\x1F\x3F\x70\x60\x60\x60\x00\x00", "|": b"\x00\x00\x00\x00\x00\xFF\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "}": b"\x00\x00\x03\x03\x03\x07\x7E\xFC\xC0\x80\x00\x00\x00\x00\x60\x60\x60\x70\x3F\x1F\x01\x00\x00\x00", "~": b"\x00\x10\x18\x0C\x04\x0C\x18\x10\x18\x0C\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", } return font def get_font_map_latin_extended() -> Dict[str, bytes]: font = { # U+0080..U+00FF Latin-1 Supplement "¡": b"\x00\x00\x00\x00\x80\xF3\xF3\x80\x00\x00\x00\x00\x00\x00\x00\x00\x0F\x3F\x3F\x0F\x00\x00\x00\x00", "¢": b"\x00\x00\xE0\xF0\x38\xFE\xFE\x18\x38\x30\x00\x00\x00\x00\x03\x07\x0E\x3F\x3F\x0C\x0E\x06\x00\x00", "£": b"\x00\x00\x00\x80\xF8\xFC\x8C\x8C\x1C\x18\x00\x00\x00\x00\x18\x1C\x1F\x0B\x18\x18\x18\x18\x08\x00", "¤": b"\x00\xF6\xFE\x18\x0C\x0C\x0C\x0C\x18\xFE\xF6\x00\x00\x1B\x1F\x06\x0C\x0C\x0C\x0C\x06\x1F\x1B\x00", "¥": b"\x00\x03\x0F\x3C\xF0\xC0\xC0\xF0\x3C\x0F\x03\x00\x00\x00\x0A\x0A\x0A\x3F\x3F\x0A\x0A\x0A\x00\x00", "¦": b"\x00\x00\x00\x00\x00\x1F\x1F\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "§": b"\x00\x00\xDC\xFE\x22\x22\x22\x22\xE6\xC4\x00\x00\x00\x00\x08\x19\x11\x11\x11\x11\x1F\x0E\x00\x00", "¨": b"\x00\x00\x00\x03\x03\x00\x00\x03\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "©": b"\x00\xF0\xF8\x1C\xCC\xEC\x2C\x6C\x4C\x1C\xF8\xF0\x00\x07\x0F\x1C\x19\x1B\x1A\x1B\x19\x1C\x0F\x07", "«": b"\x00\x80\xC0\x60\x20\x00\x80\xC0\x60\x20\x00\x00\x00\x00\x01\x03\x02\x00\x00\x01\x03\x02\x00\x00", "¬": b"\x18\x18\x18\x18\x18\x18\x18\x18\x18\xF8\xF8\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x03\x03\x00", "®": b"\x00\xF0\xF8\x1C\xEC\xEC\xAC\xEC\x4C\x1C\xF8\xF0\x00\x07\x0F\x1C\x1B\x1B\x18\x1B\x1B\x1C\x0F\x07", "¯": b"\x00\x00\x00\x00\x00\x0C\x0C\x0C\x0C\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "°": b"\x00\x00\x00\x1E\x3F\x33\x33\x3F\x1E\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "±": b"\x00\x00\x00\xC0\xC0\xF0\xF0\xC0\xC0\x00\x00\x00\x00\x00\x00\x18\x18\x1B\x1B\x18\x18\x00\x00\x00", "²": b"\x00\x00\x19\x1D\x15\x17\x12\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "³": b"\x00\x00\x11\x15\x15\x1F\x0A\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "´": b"\x00\x00\x00\x00\x04\x06\x03\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "µ": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x00\xFF\xFF\x0E\x0C\x0C\x0C\x06\x0F\x0F\x00\x00", "¶": b"\x00\x38\x7C\xC6\x82\xFE\xFE\x02\xFE\xFE\x02\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x3F\x3F\x00\x00", "¹": b"\x00\x00\x12\x1F\x1F\x10\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "»": b"\x00\x20\x60\xC0\x80\x00\x20\x60\xC0\x80\x00\x00\x00\x02\x03\x01\x00\x00\x02\x03\x01\x00\x00\x00", "¼": b"\x00\x48\x7C\x7C\x40\x80\xC0\x60\x30\x10\x00\x00\x00\x00\x04\x06\x03\x01\x06\x07\x04\x1F\x1F\x00", "½": b"\x00\x48\x7C\x7C\x40\x80\xC0\x60\x30\x10\x00\x00\x00\x00\x04\x06\x03\x01\x00\x19\x1D\x17\x12\x00", "¾": b"\x00\x44\x54\x7C\x28\x80\xC0\x60\x30\x10\x00\x00\x00\x00\x04\x06\x03\x01\x06\x07\x04\x1F\x1F\x00", "¿": b"\x00\x00\x00\x80\xC0\xFB\x7B\x00\x00\x00\x00\x00\x00\x0E\x1F\x3B\x31\x30\x30\x30\x38\x1E\x0E\x00", "À": b"\x00\x00\x00\x80\xE1\x7B\x7E\xE4\x80\x00\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Á": b"\x00\x00\x00\x80\xE4\x7E\x7B\xE1\x80\x00\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Â": b"\x00\x00\x00\x84\xE6\x7B\x7B\xE6\x84\x00\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Ã": b"\x00\x00\x00\x82\xE3\x79\x7B\xE2\x83\x01\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Ä": b"\x00\x00\x00\x83\xE3\x78\x78\xE3\x83\x00\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Å": b"\x00\x00\x00\x80\xE2\x75\x75\xE2\x80\x00\x00\x00\x00\x38\x3E\x0F\x0D\x0C\x0C\x0D\x0F\x3E\x38\x00", "Æ": b"\x00\x00\x80\xF0\x7C\x1F\xFF\xFF\xC3\xC3\x03\x00\x00\x3C\x3F\x07\x06\x06\x3F\x3F\x30\x30\x30\x00", "Ç": b"\x00\xF0\xFC\x0E\x07\x03\x03\x03\x07\x1E\x1C\x00\x00\x01\x07\xCE\xDC\xF8\xF8\x18\x1C\x0E\x06\x00", "È": b"\x00\xF8\xF8\x99\x9B\x9E\x9C\x98\x98\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "É": b"\x00\xF8\xF8\x98\x98\x9C\x9E\x9B\x99\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "Ê": b"\x00\xF8\xF8\x9C\x9E\x9B\x9B\x9E\x9C\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "Ë": b"\x00\xF8\xF8\x9B\x9B\x98\x98\x9B\x9B\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "Ì": b"\x00\x00\x00\x19\x1B\xFE\xFC\x18\x18\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Í": b"\x00\x00\x00\x18\x18\xFC\xFE\x1B\x19\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Î": b"\x00\x00\x00\x1C\x1E\xFB\xFB\x1E\x1C\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ï": b"\x00\x00\x00\x1B\x1B\xF8\xF8\x1B\x1B\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ð": b"\x00\xC0\xFF\xFF\xC3\x03\x03\x07\x0E\xFC\xF0\x00\x00\x00\x3F\x3F\x30\x30\x30\x38\x1C\x0F\x03\x00", "Ñ": b"\x00\xF8\xF8\x72\xE3\xC1\x83\x02\x03\xF9\xF8\x00\x00\x3F\x3F\x00\x00\x01\x03\x07\x0E\x3F\x3F\x00", "Ò": b"\x00\xE0\xF0\x39\x1B\x1E\x1C\x18\x38\xF0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Ó": b"\x00\xE0\xF0\x38\x18\x1C\x1E\x1B\x39\xF0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Ô": b"\x00\xE0\xF0\x3C\x1E\x1B\x1B\x1E\x3C\xF0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Õ": b"\x00\xE0\xF0\x3A\x1B\x19\x1B\x1A\x3B\xF1\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Ö": b"\x00\xE0\xF0\x3B\x1B\x18\x18\x1B\x3B\xF0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "×": b"\x00\xF0\xF8\x1C\x0C\x8C\xEC\x7C\x18\xFC\xF4\x00\x00\x2F\x3F\x18\x3E\x37\x31\x30\x38\x1F\x0F\x00", "Ù": b"\x00\xF8\xF8\x01\x03\x06\x04\x00\x00\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "Ú": b"\x00\xF8\xF8\x00\x00\x04\x06\x03\x01\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "Û": b"\x00\xF8\xF8\x04\x06\x03\x03\x06\x04\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "Ü": b"\x00\xF8\xF8\x03\x03\x00\x00\x03\x03\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "Ý": b"\x00\x08\x18\x30\x60\xC4\xC6\x63\x31\x18\x08\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "ß": b"\x00\x00\xC0\xE0\x30\x10\x10\x30\xE0\xC0\x00\x00\x00\x00\xFF\xFF\x21\x21\x21\x33\x3F\x1E\x00\x00", "à": b"\x00\x00\x40\x60\x62\x66\x6C\x68\x60\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "á": b"\x00\x00\x40\x60\x68\x6C\x66\x62\x60\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "â": b"\x00\x00\x40\x68\x6C\x66\x66\x6C\x68\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "ã": b"\x00\x00\x40\x68\x6C\x64\x6C\x68\x6C\xE4\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "ä": b"\x00\x00\x40\x6C\x6C\x60\x60\x6C\x6C\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "å": b"\x00\x00\x40\x60\x64\x6A\x6A\x64\x60\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "æ": b"\x00\x80\xC0\x40\x40\xC0\x80\x40\x40\xC0\x80\x00\x00\x1C\x3E\x22\x22\x1F\x3F\x22\x22\x33\x11\x00", "ç": b"\x00\x80\xC0\xE0\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\x0F\x1F\xB8\xB0\xF0\xF0\x30\x38\x18\x08\x00", "è": b"\x00\x80\xC0\xE0\x62\x66\x6C\x68\x60\xC0\x80\x00\x00\x0F\x1F\x33\x33\x33\x33\x33\x33\x13\x03\x00", "é": b"\x00\x80\xC0\xE0\x60\x68\x6C\x66\x62\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x33\x33\x33\x13\x03\x00", "ê": b"\x00\x80\xC0\xE8\x6C\x66\x66\x6C\x68\xC0\x80\x00\x00\x0F\x1F\x33\x33\x33\x33\x33\x33\x13\x03\x00", "ë": b"\x00\x80\xC0\xEC\x6C\x60\x60\x6C\x6C\xC0\x80\x00\x00\x0F\x1F\x33\x33\x33\x33\x33\x33\x13\x03\x00", "ì": b"\x00\x00\x00\x00\x62\xE6\xEC\x08\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "í": b"\x00\x00\x00\x00\x68\xEC\xE6\x02\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "î": b"\x00\x00\x00\x08\x6C\xE6\xE6\x0C\x08\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ï": b"\x00\x00\x00\x0C\x6C\xE0\xEC\x0C\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ñ": b"\x00\x00\xE0\xE8\x6C\x64\x6C\x68\xEC\xC4\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00", "ò": b"\x00\x80\xC0\xE0\x62\x66\x6C\x68\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "ó": b"\x00\x80\xC0\xE0\x68\x6C\x66\x62\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "ô": b"\x00\x80\xC0\xE8\x6C\x66\x66\x6C\xE8\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "õ": b"\x00\x80\xC8\xEC\x64\x6C\x68\x6C\xE4\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "ö": b"\x00\x80\xC0\xEC\x6C\x60\x60\x6C\xEC\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "÷": b"\x00\x00\x80\x80\x80\xB0\xB0\x80\x80\x80\x00\x00\x00\x00\x01\x01\x01\x0D\x0D\x01\x01\x01\x00\x00", "ø": b"\x00\x80\xC0\xE0\x60\x60\x60\xE0\xC0\xE0\xA0\x00\x00\x2F\x3F\x18\x3C\x36\x33\x31\x38\x1F\x0F\x00", "ù": b"\x00\xE0\xE0\x00\x02\x06\x0C\x08\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "ú": b"\x00\xE0\xE0\x00\x08\x0C\x06\x02\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "û": b"\x00\xE0\xE0\x08\x0C\x06\x06\x0C\x08\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "ü": b"\x00\xE0\xE0\x0C\x0C\x00\x00\x0C\x0C\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "ý": b"\x00\x00\x60\xE0\x80\x10\x18\x8C\xE4\x60\x00\x00\x00\x00\x00\x81\xE7\x7E\x1E\x07\x01\x00\x00\x00", "þ": b"\x00\x00\x03\xFF\xFF\x1B\x18\x18\xF8\xF0\x00\x00\x00\x00\x30\x3F\x3F\x36\x06\x06\x07\x03\x00\x00", "ÿ": b"\x00\x00\x60\xEC\x8C\x00\x00\x8C\xEC\x60\x00\x00\x00\x00\x00\x81\xE7\x7E\x1E\x07\x01\x00\x00\x00", # U+0100..U+017F Latin Extended A "Ā": b"\x00\x00\x00\xE0\xF9\x1D\x1D\xF9\xE0\x00\x00\x00\x00\x38\x3F\x07\x06\x06\x06\x06\x07\x3F\x38\x00", "ā": b"\x00\x00\x40\x60\x68\x68\x68\x68\x68\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "Ă": b"\x00\x00\x00\xE0\xF9\x1A\x1A\xF9\xE0\x00\x00\x00\x00\x38\x3F\x07\x06\x06\x06\x06\x07\x3F\x38\x00", "ă": b"\x00\x00\x40\x60\x64\x68\x68\x68\x64\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "Ą": b"\x00\x00\x00\xE0\xFC\x1F\x1F\xFC\xE0\x00\x00\x00\x00\x38\x3F\x07\x06\x06\x06\x06\x67\xBF\xB8\x00", "ą": b"\x00\x00\x40\x60\x60\x60\x60\x60\x60\xE0\xC0\x00\x00\x1C\x3E\x33\x33\x33\x33\x33\x73\xBF\xBF\x00", "Ć": b"\x00\x80\xE0\x70\x38\x18\x1A\x1B\x39\x70\x60\x00\x00\x03\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "ć": b"\x00\x80\xC0\xE0\x60\x60\x68\x6C\x64\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x30\x18\x08\x00", "Ĉ": b"\x00\x80\xE0\x70\x3A\x1B\x19\x1B\x3A\x70\x60\x00\x00\x03\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "ĉ": b"\x00\x80\xC0\xE0\x68\x6C\x64\x6C\x68\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x30\x18\x08\x00", "Ċ": b"\x00\x80\xE0\x70\x38\x18\x1A\x18\x38\x70\x60\x00\x00\x03\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "ċ": b"\x00\x80\xC0\xE0\x60\x60\x68\x60\x60\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x30\x18\x08\x00", "Č": b"\x00\x80\xE0\x70\x39\x1B\x1A\x1B\x39\x70\x60\x00\x00\x03\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "č": b"\x00\x80\xC0\xE0\x64\x6C\x68\x6C\x64\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x30\x18\x08\x00", "Ď": b"\x00\xF8\xF8\x19\x1B\x1A\x1B\x39\x70\xE0\x80\x00\x00\x3F\x3F\x30\x30\x30\x30\x38\x1C\x0F\x03\x00", "ď": b"\x00\x80\xC0\xE0\x60\x60\xE0\xFF\xFF\x00\x05\x03\x00\x0F\x1F\x38\x30\x30\x30\x3F\x3F\x00\x00\x00", "Đ": b"\xC0\xFF\xFF\xC3\xC3\x03\x03\x07\x0E\xFC\xF0\x00\x00\x3F\x3F\x30\x30\x30\x30\x38\x1C\x0F\x03\x00", "đ": b"\x00\x80\xC0\xE0\x60\x60\x60\xE4\xC4\xFF\xFF\x04\x00\x0F\x1F\x38\x30\x30\x30\x30\x30\x3F\x3F\x00", "Ē": b"\x00\xFC\xFC\x8C\x8D\x8D\x8D\x8D\x8C\x0C\x0C\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "ē": b"\x00\x80\xC0\xE0\x68\x68\x68\x68\x68\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x33\x33\x33\x13\x01\x00", "Ĕ": b"\x00\xF8\xF8\x98\x99\x9A\x9A\x99\x98\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "ĕ": b"\x00\x80\xC0\xE0\x64\x68\x68\x68\x64\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x33\x33\x33\x13\x01\x00", "Ė": b"\x00\xF8\xF8\x98\x98\x98\x9A\x98\x98\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "ė": b"\x00\x80\xC0\xE0\x60\x60\x68\x60\x60\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x33\x33\x33\x13\x01\x00", "Ę": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xC3\xC3\x03\x03\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x70\xB0\xB0\x00", "ę": b"\x00\x80\xC0\xE0\x60\x60\x60\x60\x60\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x73\xB3\xB3\x13\x01\x00", "Ě": b"\x00\xF8\xF8\x98\x99\x9B\x9A\x9B\x99\x18\x18\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "ě": b"\x00\x80\xC0\xE0\x64\x6C\x68\x6C\x64\xC0\x80\x00\x00\x0F\x1F\x3B\x33\x33\x33\x33\x33\x13\x01\x00", "Ĝ": b"\x00\x80\xE0\x70\x1A\x1B\x19\x1B\x1A\x38\x30\x00\x00\x03\x0F\x1C\x38\x30\x33\x33\x33\x3F\x3F\x00", "ĝ": b"\x00\x80\xC0\xE0\x68\x6C\x64\x6C\x68\xE0\xE0\x00\x00\x03\xC7\xCE\xCC\xCC\xCC\xCC\xE6\x7F\x3F\x00", "Ğ": b"\x00\x80\xE0\x70\x1A\x19\x19\x19\x1A\x38\x30\x00\x00\x03\x0F\x1C\x38\x30\x33\x33\x33\x3F\x3F\x00", "ğ": b"\x00\x80\xC0\xE0\x68\x64\x64\x64\x68\xE0\xE0\x00\x00\x03\xC7\xCE\xCC\xCC\xCC\xCC\xE6\x7F\x3F\x00", "Ġ": b"\x00\x80\xE0\x70\x18\x18\x1A\x18\x18\x38\x30\x00\x00\x03\x0F\x1C\x38\x30\x33\x33\x33\x3F\x3F\x00", "ġ": b"\x00\x80\xC0\xE0\x60\x60\x68\x60\x60\xE0\xE0\x00\x00\x03\xC7\xCE\xCC\xCC\xCC\xCC\xE6\x7F\x3F\x00", "Ģ": b"\x00\xF0\xFC\x0E\x07\x03\xC3\xC3\xC3\xC7\xC6\x00\x00\x03\x0F\x1C\x38\x30\xB0\x70\x30\x3F\x3F\x00", "ģ": b"\x00\x80\xC0\xE0\x60\x60\x6C\x6A\x60\xE0\xE0\x00\x00\x03\xC7\xCE\xCC\xCC\xCC\xCC\xE6\x7F\x3F\x00", "Ĥ": b"\x00\xFC\xFC\x80\x82\x81\x81\x82\x80\xFC\xFC\x00\x00\x3F\x3F\x01\x01\x01\x01\x01\x01\x3F\x3F\x00", "ĥ": b"\x00\xFE\xFE\xC0\x62\x63\x61\xE3\xC2\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00\x00", "Ħ": b"\x02\xFF\xFF\xC2\xC2\xC2\xC2\xC2\xC2\xFF\xFF\x02\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "ħ": b"\x04\xFF\xFF\xC4\x64\x60\x60\xE0\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00\x00", "Ĩ": b"\x00\x00\x00\x1A\x19\xFB\xFB\x1A\x19\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ĩ": b"\x00\x00\x00\x08\x64\xEC\xE8\x04\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ī": b"\x00\x00\x00\x0C\x0D\xFD\xFD\x0D\x0C\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ī": b"\x00\x00\x00\x08\x68\xE8\xE8\x00\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ĭ": b"\x00\x00\x00\x18\x19\xFA\xFA\x19\x18\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ĭ": b"\x00\x00\x00\x00\x64\xE8\xE8\x04\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Į": b"\x00\x00\x00\x03\x03\xFF\xFF\x03\x03\x00\x00\x00\x00\x00\x00\x30\x30\x7F\xBF\xB0\x30\x00\x00\x00", "į": b"\x00\x00\x00\x00\x60\xEC\xEC\x00\x00\x00\x00\x00\x00\x00\x00\x30\x30\x7F\xBF\xB0\x30\x00\x00\x00", "İ": b"\x00\x00\x00\x18\x18\xF8\xFA\x18\x18\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ı": b"\x00\x00\x00\x00\x60\xE0\xE0\x00\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "IJ": b"\x00\x03\xFF\xFF\x03\x00\x00\x00\x03\xFF\xFF\x00\x00\x30\x3F\x3F\x30\x0C\x1C\x30\x30\x3F\x1F\x00", "ij": b"\x00\x00\x20\xEC\xEC\x00\x00\x20\xEC\xEC\x00\x00\x00\x00\x30\x3F\x3F\x70\xC0\xC0\xFF\x7F\x00\x00", "Ĵ": b"\x00\x00\x00\x00\x02\x03\x01\x03\x02\xF8\xF8\x00\x00\x0E\x1E\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ĵ": b"\x00\x00\x00\x00\x00\x08\x6C\xE4\xEC\x08\x00\x00\x00\x00\x00\x60\xE0\xC0\xC0\xFF\x7F\x00\x00\x00", "Ķ": b"\x00\xFF\xFF\xC0\xE0\xF0\x38\x1C\x0E\x07\x03\x00\x00\x3F\x3F\x00\x01\xA3\x67\x0E\x1C\x38\x30\x00", "ķ": b"\x00\x00\xFF\xFF\x00\x80\xC0\xE0\x60\x00\x00\x00\x00\x00\x3F\x3F\x03\xA7\x6F\x1C\x38\x30\x00\x00", "ĸ": b"\x00\x00\xE0\xE0\x00\x80\xC0\xE0\x60\x20\x00\x00\x00\x00\x3F\x3F\x03\x07\x0F\x1C\x38\x30\x00\x00", "Ĺ": b"\x00\xF8\xFA\x03\x01\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "ĺ": b"\x00\x00\x00\x00\x18\xFA\xFB\x01\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ļ": b"\x00\xFF\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x30\x30\xB0\x70\x30\x30\x30\x30\x00", "ļ": b"\x00\x00\x00\x00\x03\xFF\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x30\x30\xBF\x7F\x30\x30\x00\x00\x00", "Ľ": b"\x00\xFF\xFF\x00\x00\x05\x03\x00\x00\x00\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "ľ": b"\x00\x00\x00\x00\x03\xFF\xFF\x00\x05\x03\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ŀ": b"\x00\xFF\xFF\x00\x00\x00\x20\x00\x00\x00\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "ŀ": b"\x00\x00\x00\x00\x03\xFF\xFF\x00\x40\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ł": b"\x80\xFF\xFF\x20\x10\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "ł": b"\x00\x00\x00\x00\x83\xFF\xFF\x20\x10\x00\x00\x00\x00\x00\x00\x31\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ń": b"\x00\xFF\xFF\x0E\x38\xF2\xC3\x01\x00\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x03\x07\x1C\x3F\x3F\x00", "ń": b"\x00\x00\xE0\xE0\x60\x68\x6C\x64\xE0\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00", "Ņ": b"\x00\xFF\xFF\x0E\x38\xF0\xC0\x00\x00\xFF\xFF\x00\x00\x3F\x3F\x00\x00\xA0\x63\x07\x1C\x3F\x3F\x00", "ņ": b"\x00\x00\xE0\xE0\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\xA0\x60\x00\x3F\x3F\x00", "Ň": b"\x00\xFF\xFF\x0E\x38\xF1\xC2\x01\x00\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x03\x07\x1C\x3F\x3F\x00", "ň": b"\x00\x00\xE0\xE0\x64\x6C\x68\x6C\xE4\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00", "ʼn": b"\x00\x0A\xE6\xE0\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x3F\x3F\x00", "Ŋ": b"\x00\x00\xFF\xFF\x06\x03\x03\x03\x07\xFE\xFC\x00\x00\x00\x3F\x3F\x00\x00\x20\x20\x30\x1F\x0F\x00", "ŋ": b"\x00\x00\xE0\xE0\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\x00\x3F\x3F\x00\x00\x00\xC0\xC0\xFF\x7F\x00", "Ō": b"\x00\xC0\xF0\x38\x1D\x0D\x0D\x1D\x38\xF0\xC0\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "ō": b"\x00\x80\xC0\xE0\x68\x68\x68\x68\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Ŏ": b"\x00\x80\xE0\x70\x39\x1A\x1A\x39\x70\xE0\x80\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "ŏ": b"\x00\x80\xC0\xE0\x64\x68\x68\x64\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Ő": b"\x00\x80\xE0\x70\x3A\x19\x1A\x39\x70\xE0\x80\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "ő": b"\x00\x80\xC0\xE0\x68\x64\x68\x64\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Œ": b"\xF0\xFC\x0E\x03\x03\x07\xFE\xFF\xC3\xC3\xC3\x00\x03\x0F\x1C\x30\x30\x38\x1F\x3F\x30\x30\x30\x00", "œ": b"\x80\xC0\xE0\x60\x60\xE0\xC0\x60\x60\x60\x40\x80\x0F\x1F\x38\x30\x30\x1F\x1F\x3B\x33\x33\x1B\x09", "Ŕ": b"\x00\xF8\xF8\x98\x98\x9A\x9B\x99\xF8\xF0\x60\x00\x00\x3F\x3F\x01\x01\x03\x07\x0F\x1D\x38\x30\x00", "ŕ": b"\x00\x00\xE0\xE0\xC0\x60\x68\x6C\x64\xE0\xC0\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00", "Ŗ": b"\x00\xFF\xFF\x83\x83\x83\x83\x83\xC7\xFE\x7C\x00\x00\x3F\x3F\x01\x01\xA3\x67\x0F\x1D\x38\x30\x00", "ŗ": b"\x00\x00\xE0\xE0\xC0\x60\x60\x60\x60\xE0\xC0\x00\x00\x00\x3F\x3F\x00\xA0\x60\x00\x00\x00\x00\x00", "Ř": b"\x00\xF8\xF8\x99\x9B\x9A\x9B\x99\xF8\xF0\x60\x00\x00\x3F\x3F\x01\x01\x03\x07\x0F\x1D\x38\x30\x00", "ř": b"\x00\x00\xE0\xE0\xC4\x6C\x68\x6C\x64\xE0\xC0\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00", "Ś": b"\x00\x60\xF0\xF8\x98\x9A\x9B\x99\x98\x30\x20\x00\x00\x0C\x1C\x39\x31\x31\x31\x31\x3B\x1F\x0E\x00", "ś": b"\x00\xC0\xE0\x60\x68\x6C\x64\x60\x40\x00\x00\x00\x00\x11\x33\x33\x33\x33\x33\x3F\x1E\x00\x00\x00", "Ŝ": b"\x00\x60\xF0\xF8\x9A\x9B\x99\x9B\x9A\x30\x20\x00\x00\x0C\x1C\x39\x31\x31\x31\x31\x3B\x1F\x0E\x00", "ŝ": b"\x00\xC0\xE0\x68\x6C\x64\x6C\x68\x40\x00\x00\x00\x00\x11\x33\x33\x33\x33\x33\x3F\x1E\x00\x00\x00", "Ş": b"\x00\x3C\x7E\xE7\xC3\xC3\xC3\xC3\xC7\x8E\x0C\x00\x00\x0C\x1C\x38\x30\xB0\xF0\x30\x39\x1F\x0F\x00", "ş": b"\x00\xC0\xE0\x60\x60\x60\x60\x60\x40\x00\x00\x00\x00\x11\x33\x33\xB3\xF3\x33\x3F\x1E\x00\x00\x00", "Š": b"\x00\x60\xF0\xF8\x99\x9B\x9A\x9B\x99\x30\x20\x00\x00\x0C\x1C\x39\x31\x31\x31\x31\x3B\x1F\x0E\x00", "š": b"\x00\xC0\xE0\x64\x6C\x68\x6C\x64\x40\x00\x00\x00\x00\x11\x33\x33\x33\x33\x33\x3F\x1E\x00\x00\x00", "Ţ": b"\x00\x00\x03\x03\x03\xFF\xFF\x03\x03\x03\x00\x00\x00\x00\x00\x00\x00\xBF\xBF\x60\x00\x00\x00\x00", "ţ": b"\x00\x60\x60\xFE\xFE\x60\x60\x60\x00\x00\x00\x00\x00\x00\x00\x1F\x3F\xB0\xB0\xF0\x30\x00\x00\x00", "Ť": b"\x00\x00\x18\x19\x1B\xFA\xFA\x1B\x19\x18\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "ť": b"\x00\x60\x60\xFE\xFE\x60\x65\x63\x00\x00\x00\x00\x00\x00\x00\x1F\x3F\x30\x30\x30\x30\x00\x00\x00", "Ŧ": b"\x00\x00\x03\xC3\xC3\xFF\xFF\xC3\xC3\x03\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "ŧ": b"\x00\x30\x30\xFE\xFE\x30\x30\x30\x00\x00\x00\x00\x00\x03\x03\x1F\x3F\x33\x33\x30\x30\x00\x00\x00", "Ũ": b"\x00\xF8\xF8\x02\x01\x03\x03\x02\x01\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ũ": b"\x00\xE0\xE0\x08\x04\x0C\x0C\x08\x04\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "Ū": b"\x00\xFC\xFC\x00\x01\x01\x01\x01\x00\xFC\xFC\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ū": b"\x00\xE0\xE0\x00\x08\x08\x08\x08\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "Ŭ": b"\x00\xFC\xFC\x00\x01\x02\x02\x01\x00\xFC\xFC\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ŭ": b"\x00\xE0\xE0\x00\x04\x08\x08\x04\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "Ů": b"\x00\xF8\xF8\x00\x06\x09\x09\x06\x00\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ů": b"\x00\xE0\xE0\x00\x0C\x12\x12\x0C\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "Ű": b"\x00\xF8\xF8\x00\x02\x01\x02\x01\x00\xF8\xF8\x00\x00\x07\x1F\x38\x30\x30\x30\x30\x38\x1F\x07\x00", "ű": b"\x00\xE0\xE0\x00\x08\x04\x08\x04\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x00", "Ų": b"\x00\xFF\xFF\x00\x00\x00\x00\x00\x00\xFF\xFF\x00\x00\x07\x1F\x38\x30\xF0\xB0\xB0\x38\x1F\x07\x00", "ų": b"\x00\xE0\xE0\x00\x00\x00\x00\x00\x00\xE0\xE0\x00\x00\x0F\x1F\x38\x30\xF0\xB0\xB0\x18\x3F\x3F\x00", "Ŵ": b"\x00\xFC\xFC\x00\x02\x81\x81\x02\x00\xFC\xFC\x00\x00\x3F\x3F\x1C\x06\x03\x03\x06\x1C\x3F\x3F\x00", "ŵ": b"\x00\xE0\xE0\x00\x04\xE8\xE8\x04\x00\xE0\xE0\x00\x00\x07\x1F\x38\x1C\x0F\x0F\x1C\x38\x1F\x07\x00", "Ŷ": b"\x00\x02\x0E\x3C\xF2\xC1\xC1\xF2\x3C\x0E\x02\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "ŷ": b"\x00\x00\x60\xE0\x88\x04\x04\x88\xE0\x60\x00\x00\x00\x00\x00\x81\xE7\x7E\x1E\x07\x01\x00\x00\x00", "Ÿ": b"\x00\x02\x0E\x3C\xF1\xC0\xC0\xF1\x3C\x0E\x02\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "Ź": b"\x00\x18\x18\x18\x18\x1A\x9B\xD9\xF8\x78\x38\x00\x00\x30\x38\x3C\x3E\x37\x33\x31\x30\x30\x30\x00", "ź": b"\x00\x60\x60\x60\x68\x6C\xE4\xE0\x60\x20\x00\x00\x00\x30\x38\x3C\x36\x33\x31\x30\x30\x30\x00\x00", "Ż": b"\x00\x18\x18\x18\x18\x18\x9A\xD8\xF8\x78\x38\x00\x00\x30\x38\x3C\x3E\x37\x33\x31\x30\x30\x30\x00", "ż": b"\x00\x60\x60\x60\x60\x68\xE0\xE0\x60\x20\x00\x00\x00\x30\x38\x3C\x36\x33\x31\x30\x30\x30\x00\x00", "Ž": b"\x00\x18\x18\x18\x19\x1B\x9A\xDB\xF9\x78\x38\x00\x00\x30\x38\x3C\x3E\x37\x33\x31\x30\x30\x30\x00", "ž": b"\x00\x60\x60\x64\x6C\x68\xEC\xE4\x60\x20\x00\x00\x00\x30\x38\x3C\x36\x33\x31\x30\x30\x30\x00\x00", "ſ": b"\x00\x00\x00\x00\xFC\xFE\x06\x06\x0E\x0C\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x00\x00\x00\x00\x00", } return font def get_font_map_greek() -> Dict[str, bytes]: font = { # U+0370..U+03FF Greek and Coptic "Έ": b"\x06\xFC\xFC\x8C\x8C\x8C\x8C\x8C\x8C\x0C\x0C\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "Α": b"\x00\x00\x00\xE0\xFC\x1F\x1F\xFC\xE0\x00\x00\x00\x00\x38\x3F\x07\x06\x06\x06\x06\x07\x3F\x38\x00", "Β": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xE7\xFE\xBC\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x39\x1F\x0F\x00", "Γ": b"\x00\xFF\xFF\x03\x03\x03\x03\x03\x03\x03\x03\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "Δ": b"\x00\x00\x00\xE0\xFC\x1F\x1F\xFC\xE0\x00\x00\x00\x00\x38\x3F\x37\x30\x30\x30\x30\x37\x3F\x38\x00", "Ε": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xC3\xC3\x03\x03\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "Ζ": b"\x00\x03\x03\x03\x03\xC3\xE3\x33\x1F\x0F\x03\x00\x00\x30\x3C\x3E\x33\x31\x30\x30\x30\x30\x30\x00", "Η": b"\x00\xFF\xFF\xC0\xC0\xC0\xC0\xC0\xC0\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "Θ": b"\x00\xF0\xFC\x0E\xC7\xC3\xC3\xC7\x0E\xFC\xF0\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "Ι": b"\x00\x00\x00\x03\x03\xFF\xFF\x03\x03\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Κ": b"\x00\xFF\xFF\xC0\xE0\xF0\x38\x1C\x0E\x07\x03\x00\x00\x3F\x3F\x00\x01\x03\x07\x0E\x1C\x38\x30\x00", "Λ": b"\x00\x00\x00\xE0\xFC\x1F\x1F\xFC\xE0\x00\x00\x00\x00\x38\x3F\x07\x00\x00\x00\x00\x07\x3F\x38\x00", "Μ": b"\x00\xFF\xFF\x1E\x78\xE0\xE0\x78\x1E\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x01\x01\x00\x00\x3F\x3F\x00", "Ν": b"\x00\xFF\xFF\x0E\x38\xF0\xC0\x00\x00\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x03\x07\x1C\x3F\x3F\x00", "Ξ": b"\x00\x03\x03\xC3\xC3\xC3\xC3\xC3\xC3\x03\x03\x00\x00\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x00", "Ο": b"\x00\xF0\xFC\x0E\x07\x03\x03\x07\x0E\xFC\xF0\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "Π": b"\x00\xFF\xFF\x03\x03\x03\x03\x03\x03\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "Ρ": b"\x00\xFF\xFF\x83\x83\x83\x83\x83\xC7\xFE\x7C\x00\x00\x3F\x3F\x01\x01\x01\x01\x01\x01\x00\x00\x00", "Σ": b"\x00\x03\x0F\x1F\x33\xE3\xE3\x03\x03\x03\x03\x00\x00\x30\x3C\x3E\x33\x31\x30\x30\x30\x30\x30\x00", "Τ": b"\x00\x03\x03\x03\x03\xFF\xFF\x03\x03\x03\x03\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "Υ": b"\x00\x03\x0F\x3C\xF0\xC0\xC0\xF0\x3C\x0F\x03\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "Φ": b"\x00\xF8\xFC\x0E\x06\xFF\xFF\x06\x0E\xFC\xF8\x00\x00\x03\x07\x0E\x0C\x3F\x3F\x0C\x0E\x07\x03\x00", "Χ": b"\x00\x03\x0F\x3C\xF0\xC0\xC0\xF0\x3C\x0F\x03\x00\x00\x30\x3C\x0F\x03\x00\x00\x03\x0F\x3C\x30\x00", "Ψ": b"\x00\x3F\x7F\xE0\xC0\xFF\xFF\xC0\xE0\x7F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "Ω": b"\x00\xF0\xFC\x0E\x07\x03\x03\x07\x0E\xFC\xF0\x00\x00\x63\x6F\x7C\x70\x00\x00\x70\x7C\x6F\x63\x00", "ά": b"\x00\x80\xC0\xE0\x60\x6C\x6E\x66\xC0\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x20", "έ": b"\x00\xE0\xF0\x30\x30\x36\x37\x33\x30\x70\x60\x00\x00\x1D\x3F\x33\x33\x33\x33\x33\x33\x38\x18\x00", "ή": b"\x00\xE0\xE0\xC0\x60\x6C\x6E\xE6\xE0\xC0\x00\x00\x00\x1F\x1F\x00\x00\x00\x00\x00\x7F\x7F\x00\x00", "ί": b"\x00\x00\x00\xEC\xEE\x06\x00\x00\x00\x00\x00\x00\x00\x00\x00\x1F\x3F\x30\x30\x30\x00\x00\x00\x00", "α": b"\x00\x80\xC0\xE0\x60\x60\x60\x60\xC0\xE0\xE0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x18\x3F\x3F\x20", "β": b"\x00\x00\xC0\xE0\x30\x10\x10\x30\xE0\xC0\x00\x00\x00\x00\xFF\xFF\x21\x21\x21\x33\x3F\x1E\x00\x00", "γ": b"\x00\x60\xE0\x80\x00\x00\x00\x00\x80\xE0\x60\x00\x00\x00\x01\x07\x1E\xF8\xF8\x1E\x07\x01\x00\x00", "δ": b"\x00\x83\xC7\xEF\x7F\x7B\x73\x63\xE3\xC3\x83\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "ε": b"\x00\xE0\xF0\x30\x30\x30\x30\x30\x30\x70\x60\x00\x00\x1D\x3F\x33\x33\x33\x33\x33\x33\x38\x18\x00", "ζ": b"\x00\x83\xC3\xE3\x63\x63\x63\x73\x3F\x1F\x00\x00\x00\x0F\x1F\x38\x30\x30\x30\xF0\xE0\x00\x00\x00", "η": b"\x00\xE0\xE0\xC0\x60\x60\x60\xE0\xE0\xC0\x00\x00\x00\x1F\x1F\x00\x00\x00\x00\x00\x7F\x7F\x00\x00", "θ": b"\x00\xF0\xF8\x1C\x8C\x8C\x8C\x8C\x1C\xF8\xF0\x00\x00\x0F\x1F\x38\x31\x31\x31\x31\x38\x1F\x0F\x00", "ι": b"\x00\x00\x00\xE0\xE0\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x1F\x3F\x30\x30\x30\x00\x00\x00\x00", "κ": b"\x00\x00\xC0\xC0\x00\x00\x80\xC0\xC0\x00\x00\x00\x00\x00\x3F\x3F\x06\x0F\x1F\x39\x30\x00\x00\x00", "λ": b"\x00\x00\x00\x00\xC0\xE0\xE0\xC0\x00\x00\x00\x00\x00\x30\x3C\x0F\x03\x00\x00\x03\x0F\x3C\x30\x00", "μ": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x00\xFF\xFF\x0E\x0C\x0C\x0C\x06\x0F\x0F\x00\x00", "ν": b"\x00\x60\xE0\x80\x00\x00\x00\x00\x80\xE0\x60\x00\x00\x00\x01\x07\x1E\x38\x38\x1E\x07\x01\x00\x00", "ξ": b"\x00\x3C\xFE\xE7\xC3\xC3\xC3\xC3\x00\x00\x00\x00\x00\x0F\x1F\x39\x30\x30\xF0\xE0\x00\x00\x00\x00", "ο": b"\x00\x80\xC0\xE0\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "π": b"\x00\x60\xE0\xE0\x60\x60\x60\xE0\xE0\x60\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x3F\x3F\x30\x00\x00", "ρ": b"\x00\xE0\xE0\x60\x60\x60\x60\x60\xE0\xC0\x80\x00\x00\xFF\xFF\x0C\x18\x18\x18\x18\x1C\x0F\x07\x00", "ς": b"\x00\x80\xC0\xE0\x60\x60\x60\xE0\xC0\x80\x00\x00\x00\x0F\x1F\x38\x30\x30\xF0\xE0\x03\x03\x00\x00", "σ": b"\x00\x80\xC0\xE0\x60\x60\x60\xE0\xE0\xE0\x60\x00\x00\x0F\x1F\x38\x30\x30\x30\x38\x1F\x0F\x00\x00", "τ": b"\x00\x60\x60\xE0\xE0\x60\x60\x60\x00\x00\x00\x00\x00\x00\x00\x1F\x3F\x30\x30\x30\x00\x00\x00\x00", "υ": b"\x00\xE0\xE0\x00\x00\x00\x00\x00\xE0\xE0\x00\x00\x00\x0F\x1F\x38\x30\x30\x30\x38\x1F\x0F\x00\x00", "φ": b"\x00\xC0\xE0\x70\x30\xF8\xF8\x30\x70\xE0\xC0\x00\x00\x07\x0F\x1C\x18\x7F\x7F\x18\x1C\x0F\x07\x00", "χ": b"\x00\x70\xF0\xC0\x80\x00\x80\xC0\xF0\x70\x00\x00\x00\x70\x78\x1D\x0F\x07\x0F\x1D\x78\x70\x00\x00", "ψ": b"\x00\xE0\xE0\x00\x00\xE0\xE0\x00\x00\xE0\xE0\x00\x00\x07\x0F\x1C\x18\x7F\x7F\x18\x1C\x0F\x07\x00", "ω": b"\x00\xC0\xE0\x00\x00\x00\x00\x00\x00\xE0\xC0\x00\x00\x0F\x1F\x38\x38\x1E\x1E\x38\x38\x1F\x0F\x00", "ό": b"\x00\x80\xC0\xE0\x60\x6C\x6E\x66\xE0\xC0\x80\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "ύ": b"\x00\xE0\xE0\x00\x00\x0C\x0E\x06\xE0\xE0\x00\x00\x00\x0F\x1F\x38\x30\x30\x30\x38\x1F\x0F\x00\x00", "ώ": b"\x00\xC0\xE0\x00\x00\x18\x1C\x0C\x00\xE0\xC0\x00\x00\x0F\x1F\x38\x38\x1E\x1E\x38\x38\x1F\x0F\x00", } return font def get_font_map_cyrillic() -> Dict[str, bytes]: font = { # U+0400..U+04FF Cyrillic "Ѐ": b"\x00\xFC\xFC\x8D\x8F\x8E\x8C\x8C\x8C\x0C\x0C\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x31\x30\x30\x00", "Ё": b"\x00\xFE\xFE\xC7\xC7\xC6\xC6\xC7\xC7\x06\x06\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "Ђ": b"\x00\x03\xFF\xFF\x83\xC3\xC3\xC3\xC0\x80\x00\x00\x00\x00\x3F\x3F\x01\x00\x30\x30\x39\x1F\x0F\x00", "Ѓ": b"\x00\xFC\xFC\x0C\x0C\x0C\x0E\x0F\x0D\x0C\x0C\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "Є": b"\x00\xF8\xFC\xCE\xC7\xC3\xC3\xC3\x07\x0E\x0C\x00\x00\x07\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "Ѕ": b"\x00\x3C\x7E\x67\xE3\xC3\xC3\xC3\x87\x8E\x0C\x00\x00\x0C\x1C\x38\x30\x30\x30\x31\x39\x1F\x0F\x00", "І": b"\x00\x00\x00\x03\x03\xFF\xFF\x03\x03\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ї": b"\x00\x00\x00\x0D\x0D\xFC\xFC\x0D\x0D\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "Ј": b"\x00\x00\x00\x00\x00\x00\x03\x03\x03\xFF\xFF\x00\x00\x0E\x1E\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "Љ": b"\x00\x00\xFE\xFF\x03\x03\xFF\xFF\xC0\xC0\x80\x00\x00\x30\x3F\x1F\x00\x00\x3F\x3F\x30\x39\x1F\x0F", "Њ": b"\x00\xFF\xFF\xC0\xC0\xC0\xFF\xFF\xC0\xC0\x80\x00\x00\x3F\x3F\x00\x00\x00\x3F\x3F\x30\x39\x1F\x0F", "Ћ": b"\x00\x03\xFF\xFF\xC3\xC3\xC3\xC3\xC0\x80\x00\x00\x00\x00\x3F\x3F\x01\x00\x00\x00\x01\x3F\x3F\x00", "Ќ": b"\x00\xFF\xFF\xC0\xE2\xF3\x39\x1C\x0E\x07\x03\x00\x00\x3F\x3F\x00\x01\x03\x07\x0E\x1C\x38\x30\x00", "Ѝ": b"\x00\xFF\xFF\x00\x01\xC3\xF2\x38\x0E\xFF\xFF\x00\x00\x3F\x3F\x1C\x07\x03\x00\x00\x00\x3F\x3F\x00", "Ў": b"\x00\x07\x1F\x7C\xF1\xC1\xC1\xF1\x7C\x1F\x07\x00\x00\x00\x30\x30\x3C\x0F\x07\x01\x00\x00\x00\x00", "Џ": b"\x00\xFF\xFF\x00\x00\x00\x00\x00\x00\xFF\xFF\x00\x00\x1F\x1F\x18\x18\x78\x78\x18\x18\x1F\x1F\x00", "А": b"\x00\x00\x00\xE0\xFC\x1F\x1F\xFC\xE0\x00\x00\x00\x00\x38\x3F\x07\x06\x06\x06\x06\x07\x3F\x38\x00", "Б": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xC3\xC3\x83\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x39\x1F\x0F\x00", "В": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xE7\xFE\xBC\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x39\x1F\x0F\x00", "Г": b"\x00\xFF\xFF\x03\x03\x03\x03\x03\x03\x03\x03\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "Ґ": b"\x00\xFC\xFC\x0C\x0C\x0C\x0C\x0C\x0C\x0F\x0F\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "Д": b"\x00\x00\xF8\xFE\x0F\x03\x03\x03\xFF\xFF\x00\x00\x00\x70\x7F\x1F\x18\x18\x18\x18\x1F\x7F\x70\x00", "Е": b"\x00\xFF\xFF\xC3\xC3\xC3\xC3\xC3\xC3\x03\x03\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x30\x30\x30\x00", "Ж": b"\x00\x03\x0F\xFC\xE0\xFF\xFF\xE0\xFC\x0F\x03\x00\x00\x38\x3F\x07\x00\x3F\x3F\x00\x07\x3F\x38\x00", "З": b"\x0C\x0E\x07\x03\xC3\xC3\xC3\xC3\xC3\xE7\x7E\x3C\x0C\x1C\x38\x30\x30\x30\x30\x30\x30\x39\x1F\x0E", "И": b"\x00\xFF\xFF\x00\x00\xC0\xF0\x38\x0E\xFF\xFF\x00\x00\x3F\x3F\x1C\x07\x03\x00\x00\x00\x3F\x3F\x00", "Й": b"\x00\xFF\xFF\x00\x02\xC3\xF1\x38\x0E\xFF\xFF\x00\x00\x3F\x3F\x1C\x07\x03\x00\x00\x00\x3F\x3F\x00", "К": b"\x00\xFF\xFF\xC0\xE0\xF0\x38\x1C\x0E\x07\x03\x00\x00\x3F\x3F\x00\x01\x03\x07\x0E\x1C\x38\x30\x00", "Л": b"\x00\x00\xF0\xFC\x1E\x07\x03\x03\x03\xFF\xFF\x00\x00\x30\x3F\x1F\x00\x00\x00\x00\x00\x3F\x3F\x00", "М": b"\x00\xFF\xFF\x1E\x78\xE0\xE0\x78\x1E\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x01\x01\x00\x00\x3F\x3F\x00", "Н": b"\x00\xFF\xFF\xC0\xC0\xC0\xC0\xC0\xC0\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "О": b"\x00\xF0\xFC\x0E\x07\x03\x03\x07\x0E\xFC\xF0\x00\x00\x03\x0F\x1C\x38\x30\x30\x38\x1C\x0F\x03\x00", "П": b"\x00\xFF\xFF\x03\x03\x03\x03\x03\x03\xFF\xFF\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "Р": b"\x00\xFF\xFF\x83\x83\x83\x83\x83\xC7\xFE\x7C\x00\x00\x3F\x3F\x01\x01\x01\x01\x01\x01\x00\x00\x00", "С": b"\x00\xF0\xFC\x0E\x07\x03\x03\x03\x07\x0E\x0C\x00\x00\x03\x0F\x1C\x38\x30\x30\x30\x38\x1C\x0C\x00", "Т": b"\x00\x03\x03\x03\x03\xFF\xFF\x03\x03\x03\x03\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "У": b"\x00\x07\x1F\x7C\xF0\xC0\xC0\xF0\x7C\x1F\x07\x00\x00\x00\x30\x30\x3C\x0F\x07\x01\x00\x00\x00\x00", "Ф": b"\x00\xF8\xFC\x0E\x06\xFF\xFF\x06\x0E\xFC\xF8\x00\x00\x03\x07\x0E\x0C\x3F\x3F\x0C\x0E\x07\x03\x00", "Х": b"\x00\x03\x0F\x3C\xF0\xC0\xC0\xF0\x3C\x0F\x03\x00\x00\x30\x3C\x0F\x03\x00\x00\x03\x0F\x3C\x30\x00", "Ц": b"\x00\xFF\xFF\x00\x00\x00\x00\x00\xFF\xFF\x00\x00\x00\x1F\x1F\x18\x18\x18\x18\x18\x1F\x7F\x78\x00", "Ч": b"\x00\x7F\xFF\xC0\xC0\xC0\xC0\xC0\xC0\xFF\xFF\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "Ш": b"\x00\xFF\xFF\x00\x00\xFF\xFF\x00\x00\xFF\xFF\x00\x00\x3F\x3F\x30\x30\x3F\x3F\x30\x30\x3F\x3F\x00", "Щ": b"\x00\xFF\xFF\x00\x00\xFF\xFF\x00\x00\xFF\xFF\x00\x00\x1F\x1F\x18\x18\x1F\x1F\x18\x18\x1F\x7F\x70", "Ъ": b"\x03\x03\xFF\xFF\xC0\xC0\xC0\xC0\xC0\x80\x00\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x39\x1F\x0F\x00", "Ы": b"\x00\xFF\xFF\xC0\xC0\xC0\xC0\x80\x00\x00\xFF\xFF\x00\x3F\x3F\x30\x30\x30\x39\x1F\x0F\x00\x3F\x3F", "Ь": b"\x00\xFF\xFF\xC0\xC0\xC0\xC0\xC0\xC0\x80\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x39\x1F\x0F\x00", "Э": b"\x00\x0C\x0E\x07\xC3\xC3\xC3\xC7\xCE\xFC\xF8\x00\x00\x0C\x1C\x38\x30\x30\x30\x38\x1C\x0F\x07\x00", "Ю": b"\x00\xFF\xFF\xC0\xFC\xFE\x07\x03\x07\xFE\xFC\x00\x00\x3F\x3F\x00\x0F\x1F\x38\x30\x38\x1F\x0F\x00", "Я": b"\x00\x7C\xFE\xC7\x83\x83\x83\x83\x83\xFF\xFF\x00\x00\x30\x38\x1D\x0F\x07\x03\x01\x01\x3F\x3F\x00", "а": b"\x00\x00\x30\x30\x30\x30\x30\x30\x30\xF0\xE0\x00\x00\x1E\x3F\x33\x33\x33\x33\x33\x33\x3F\x3F\x00", "б": b"\x00\xE0\xF0\x30\x30\x30\x30\x30\x30\x30\x00\x00\x00\x1F\x3F\x33\x33\x33\x33\x33\x33\x3F\x1E\x00", "в": b"\x00\xF0\xF0\x30\x30\x30\x30\x30\xF0\xE0\x00\x00\x00\x3F\x3F\x33\x33\x33\x33\x33\x33\x3F\x1E\x00", "г": b"\x00\xF0\xF0\x30\x30\x30\x30\x30\x30\x30\x30\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "ґ": b"\x00\xF0\xF0\x30\x30\x30\x30\x30\x30\x3C\x3C\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "д": b"\x00\x00\xC0\xE0\x70\x30\x30\x30\xF0\xF0\x00\x00\x00\x60\x7F\x3F\x30\x30\x30\x30\x3F\x7F\x60\x00", "е": b"\x00\xE0\xF0\x30\x30\x30\x30\x30\x30\xF0\xE0\x00\x00\x1F\x3F\x33\x33\x33\x33\x33\x33\x33\x33\x00", "ж": b"\x00\x30\xF0\xC0\x00\xF0\xF0\x00\xC0\xF0\x30\x00\x00\x30\x3C\x0F\x03\x3F\x3F\x03\x0F\x3C\x30\x00", "з": b"\x00\x60\x70\x30\x30\x30\x30\x30\x30\xF0\xE0\x00\x00\x18\x38\x30\x33\x33\x33\x33\x33\x3F\x1D\x00", "и": b"\x00\xF0\xF0\x00\x00\x00\x80\xC0\xE0\xF0\xF0\x00\x00\x3F\x3F\x1C\x0E\x07\x03\x01\x00\x3F\x3F\x00", "й": b"\x00\xF0\xF0\x00\x04\x08\x88\xC4\xE0\xF0\xF0\x00\x00\x3F\x3F\x1C\x0E\x07\x03\x01\x00\x3F\x3F\x00", "к": b"\x00\xF0\xF0\x80\x80\xC0\xE0\x70\x30\x10\x00\x00\x00\x3F\x3F\x03\x03\x07\x0E\x1C\x38\x30\x20\x00", "л": b"\x00\x00\xC0\xE0\x70\x30\x30\x30\x30\xF0\xF0\x00\x00\x30\x3F\x1F\x00\x00\x00\x00\x00\x3F\x3F\x00", "м": b"\x00\xF0\xF0\xE0\xC0\x80\x80\xC0\xE0\xF0\xF0\x00\x00\x3F\x3F\x00\x01\x03\x03\x01\x00\x3F\x3F\x00", "н": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x3F\x3F\x03\x03\x03\x03\x03\x03\x3F\x3F\x00", "о": b"\x00\xC0\xE0\x70\x30\x30\x30\x30\x70\xE0\xC0\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x1F\x0F\x00", "п": b"\x00\xF0\xF0\x30\x30\x30\x30\x30\x30\xF0\xF0\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x3F\x3F\x00", "р": b"\x00\xF0\xF0\x30\x30\x30\x30\x30\x70\xE0\xC0\x00\x00\xFF\xFF\x0C\x0C\x0C\x0C\x0C\x0E\x07\x03\x00", "с": b"\x00\xC0\xE0\x70\x30\x30\x30\x30\x70\x60\x40\x00\x00\x0F\x1F\x38\x30\x30\x30\x30\x38\x18\x08\x00", "т": b"\x00\x30\x30\x30\x30\xF0\xF0\x30\x30\x30\x30\x00\x00\x00\x00\x00\x00\x3F\x3F\x00\x00\x00\x00\x00", "у": b"\x00\x30\xF0\xC0\x00\x00\x00\x00\xC0\xF0\x30\x00\x00\x60\xE0\xC3\xE7\x7C\x3C\x0F\x03\x00\x00\x00", "ф": b"\x00\x80\xC0\x60\x60\xF0\xF0\x60\x60\xC0\x80\x00\x00\x0F\x1F\x30\x30\xFF\xFF\x30\x30\x1F\x0F\x00", "х": b"\x00\x30\x70\xC0\x80\x00\x00\x80\xC0\x70\x30\x00\x00\x30\x38\x0C\x07\x03\x03\x07\x0C\x38\x30\x00", "ц": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x00\x3F\x3F\x30\x30\x30\x30\x30\x3F\xFF\xF0\x00", "ч": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x01\x03\x03\x03\x03\x03\x03\x03\x3F\x3F\x00", "ш": b"\x00\xF0\xF0\x00\x00\xE0\xE0\x00\x00\xF0\xF0\x00\x00\x3F\x3F\x30\x30\x3F\x3F\x30\x30\x3F\x3F\x00", "щ": b"\x00\xF0\xF0\x00\x00\xF0\xF0\x00\x00\xF0\xF0\x00\x00\x3F\x3F\x30\x30\x3F\x3F\x30\x30\x3F\xFF\xE0", "ъ": b"\x30\x30\xF0\xF0\x80\x80\x80\x80\x80\x00\x00\x00\x00\x00\x3F\x3F\x31\x31\x31\x31\x3B\x1F\x0E\x00", "ы": b"\x00\xF0\xF0\x80\x80\x80\x00\x00\x00\xF0\xF0\x00\x00\x3F\x3F\x31\x31\x3B\x1F\x0E\x00\x3F\x3F\x00", "ь": b"\x00\xF0\xF0\x80\x80\x80\x80\x80\x80\x00\x00\x00\x00\x3F\x3F\x31\x31\x31\x31\x31\x3B\x1F\x0E\x00", "э": b"\x00\x40\x60\x70\x30\x30\x30\x30\x70\xE0\xC0\x00\x00\x08\x18\x38\x30\x33\x33\x33\x3B\x1F\x0F\x00", "ю": b"\x00\xF0\xF0\x00\xE0\xF0\x30\x30\x30\xF0\xE0\x00\x00\x3F\x3F\x03\x1F\x3F\x30\x30\x30\x3F\x1F\x00", "я": b"\x00\xC0\xE0\x70\x30\x30\x30\x30\x30\xF0\xF0\x00\x00\x21\x33\x3B\x1E\x0E\x06\x06\x06\x3F\x3F\x00", "ѐ": b"\x00\xE0\xF0\x32\x36\x36\x34\x30\x30\xF0\xE0\x00\x00\x1F\x3F\x33\x33\x33\x33\x33\x33\x33\x33\x00", "ё": b"\x00\xE0\xF0\x34\x34\x30\x30\x34\x34\xF0\xE0\x00\x00\x1F\x3F\x33\x33\x33\x33\x33\x33\x33\x33\x00", "ђ": b"\x00\x30\xFC\xFC\x30\xB0\xB0\xB0\x80\x80\x00\x00\x00\x00\x3F\x3F\x07\x03\x01\x01\xC1\xFF\x3F\x00", "ѓ": b"\x00\xF0\xF0\x30\x30\x34\x36\x32\x30\x30\x30\x00\x00\x3F\x3F\x00\x00\x00\x00\x00\x00\x00\x00\x00", "є": b"\x00\xC0\xE0\x70\x30\x30\x30\x30\x70\x60\x40\x00\x00\x0F\x1F\x3B\x33\x33\x33\x30\x38\x18\x08\x00", "ѕ": b"\x00\xE0\xF0\xB0\xB0\x30\x30\x30\x30\x70\x60\x00\x00\x18\x39\x31\x33\x33\x33\x37\x36\x3E\x1C\x00", "і": b"\x00\x00\x00\x00\x30\xF6\xF6\x00\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ї": b"\x00\x00\x00\x04\x34\xF0\xF4\x04\x00\x00\x00\x00\x00\x00\x00\x30\x30\x3F\x3F\x30\x30\x00\x00\x00", "ј": b"\x00\x00\x00\x00\x00\x30\x30\xF6\xF6\x00\x00\x00\x00\x00\x00\x60\xE0\xC0\xC0\xFF\x7F\x00\x00\x00", "љ": b"\x00\x00\xE0\xF0\x30\x30\xF0\xF0\x00\x00\x00\x00\x00\x30\x3F\x1F\x00\x00\x3F\x3F\x33\x33\x1E\x0C", "њ": b"\x00\xF0\xF0\x00\x00\x00\xF0\xF0\x00\x00\x00\x00\x00\x3F\x3F\x03\x03\x03\x3F\x3F\x33\x33\x1E\x0C", "ћ": b"\x00\x30\xFC\xFC\xB0\xB0\xB0\xB0\x80\x80\x00\x00\x00\x00\x3F\x3F\x01\x01\x01\x01\x01\x3F\x3F\x00", "ќ": b"\x00\xF0\xF0\x80\x88\xCC\xE4\x70\x30\x10\x00\x00\x00\x3F\x3F\x03\x03\x07\x0E\x1C\x38\x30\x20\x00", "ѝ": b"\x00\xF0\xF0\x00\x06\x0C\x88\xC0\xE0\xF0\xF0\x00\x00\x3F\x3F\x1C\x0E\x07\x03\x01\x00\x3F\x3F\x00", "ў": b"\x00\x30\xF0\xC0\x04\x08\x08\x04\xC0\xF0\x30\x00\x00\x60\xE0\xC3\xE7\x7C\x3C\x0F\x03\x00\x00\x00", "џ": b"\x00\xF0\xF0\x00\x00\x00\x00\x00\x00\xF0\xF0\x00\x00\x3F\x3F\x30\x30\xF0\xF0\x30\x30\x3F\x3F\x00", } return font def get_small_font_map_ascii_basic() -> Dict[str, bytes]: font = { # U+0000..U+007F Basic Latin " ": b"\x00\x00\x00\x00\x00\x00", "!": b"\x00\x00\x4f\x00\x00\x00", '"': b"\x00\x07\x00\x07\x00\x00", "#": b"\x14\x7f\x14\x7f\x14\x00", "$": b"\x24\x2a\x7f\x2a\x12\x00", "%": b"\x23\x13\x08\x64\x62\x00", "&": b"\x36\x49\x56\x20\x58\x00", "'": b"\x00\x05\x03\x00\x00\x00", "(": b"\x00\x1c\x22\x41\x00\x00", ")": b"\x00\x41\x22\x1c\x00\x00", "*": b"\x14\x08\x3e\x08\x14\x00", "+": b"\x08\x08\x3e\x08\x08\x00", ",": b"\x00\x50\x30\x00\x00\x00", "-": b"\x08\x08\x08\x08\x08\x00", ".": b"\x00\x60\x60\x00\x00\x00", "/": b"\x20\x10\x08\x04\x02\x00", "0": b"\x3e\x51\x49\x45\x3e\x00", "1": b"\x00\x42\x7f\x40\x00\x00", "2": b"\x42\x61\x51\x49\x46\x00", "3": b"\x21\x41\x45\x4b\x31\x00", "4": b"\x18\x14\x12\x7f\x10\x00", "5": b"\x27\x45\x45\x45\x39\x00", "6": b"\x3c\x4a\x49\x49\x30\x00", "7": b"\x01\x71\x09\x05\x03\x00", "8": b"\x36\x49\x49\x49\x36\x00", "9": b"\x06\x49\x49\x29\x1e\x00", ":": b"\x00\x36\x36\x00\x00\x00", ";": b"\x00\x56\x36\x00\x00\x00", "<": b"\x08\x14\x22\x41\x00\x00", "=": b"\x14\x14\x14\x14\x14\x00", ">": b"\x00\x41\x22\x14\x08\x00", "?": b"\x02\x01\x51\x09\x06\x00", "@": b"\x32\x49\x79\x41\x3e\x00", "A": b"\x7e\x09\x09\x09\x7e\x00", "B": b"\x7f\x49\x49\x49\x36\x00", "C": b"\x3e\x41\x41\x41\x22\x00", "D": b"\x7f\x41\x41\x22\x1c\x00", "E": b"\x7f\x49\x49\x49\x41\x00", "F": b"\x7f\x09\x09\x09\x01\x00", "G": b"\x3e\x41\x41\x49\x7a\x00", "H": b"\x7f\x08\x08\x08\x7f\x00", "I": b"\x00\x41\x7f\x41\x00\x00", "J": b"\x20\x40\x41\x3f\x01\x00", "K": b"\x7f\x08\x14\x22\x41\x00", "L": b"\x7f\x40\x40\x40\x40\x00", "M": b"\x7f\x02\x0c\x02\x7f\x00", "N": b"\x7f\x04\x08\x10\x7f\x00", "O": b"\x3e\x41\x41\x41\x3e\x00", "P": b"\x7f\x09\x09\x09\x06\x00", "Q": b"\x3e\x41\x51\x21\x5e\x00", "R": b"\x7f\x09\x19\x29\x46\x00", "S": b"\x26\x49\x49\x49\x32\x00", "T": b"\x01\x01\x7f\x01\x01\x00", "U": b"\x3f\x40\x40\x40\x3f\x00", "V": b"\x1f\x20\x40\x20\x1f\x00", "W": b"\x3f\x40\x38\x40\x3f\x00", "X": b"\x63\x14\x08\x14\x63\x00", "Y": b"\x07\x08\x70\x08\x07\x00", "Z": b"\x61\x51\x49\x45\x43\x00", "[": b"\x00\x7f\x41\x41\x00\x00", "\\": b"\x02\x04\x08\x10\x20\x00", "]": b"\x00\x41\x41\x7f\x00\x00", "^": b"\x04\x02\x01\x02\x04\x00", "_": b"\x40\x40\x40\x40\x40\x00", "`": b"\x00\x03\x05\x00\x00\x00", "a": b"\x20\x54\x54\x54\x78\x00", "b": b"\x7f\x48\x44\x44\x38\x00", "c": b"\x38\x44\x44\x44\x20\x00", "d": b"\x38\x44\x44\x48\x7f\x00", "e": b"\x38\x54\x54\x54\x18\x00", "f": b"\x00\x04\x7e\x05\x01\x00", "g": b"\x08\x54\x54\x54\x3c\x00", "h": b"\x7f\x08\x04\x04\x78\x00", "i": b"\x00\x44\x7d\x40\x00\x00", "j": b"\x20\x40\x44\x3d\x00\x00", "k": b"\x00\x7f\x10\x28\x44\x00", "l": b"\x00\x41\x7f\x40\x00\x00", "m": b"\x7c\x04\x78\x04\x78\x00", "n": b"\x7c\x08\x04\x04\x78\x00", "o": b"\x38\x44\x44\x44\x38\x00", "p": b"\x7c\x14\x14\x14\x08\x00", "q": b"\x08\x14\x14\x14\x7c\x00", "r": b"\x7c\x08\x04\x04\x08\x00", "s": b"\x48\x54\x54\x54\x24\x00", "t": b"\x04\x3e\x44\x40\x20\x00", "u": b"\x3c\x40\x40\x20\x7c\x00", "v": b"\x0c\x30\x40\x30\x0c\x00", "w": b"\x3c\x40\x30\x40\x3c\x00", "x": b"\x44\x24\x38\x48\x44\x00", "y": b"\x44\x48\x30\x10\x0c\x00", "z": b"\x44\x64\x54\x4c\x44\x00", "{": b"\x08\x36\x41\x00\x00\x00", "|": b"\x00\x00\x77\x00\x00\x00", "}": b"\x00\x00\x41\x36\x08\x00", "~": b"\x02\x01\x02\x04\x02\x00", } return font def get_small_font_map_latin_extended() -> Dict[str, bytes]: font = { # U+0080..U+00FF Latin-1 Supplement "¡": b"\x00\x00\x79\x00\x00\x00", "¢": b"\x1c\x22\x7f\x22\x10\x00", "£": b"\x50\x7e\x51\x41\x42\x00", "¤": b"\x22\x1c\x14\x1c\x22\x00", "¥": b"\x15\x16\x7c\x16\x15\x00", "¦": b"\x00\x00\x77\x00\x00\x00", "§": b"\x4a\x55\x55\x55\x29\x00", "¨": b"\x00\x01\x00\x01\x00\x00", "©": b"\x00\x18\x24\x24\x00\x00", "«": b"\x08\x14\x00\x08\x14\x00", "¬": b"\x08\x08\x08\x08\x38\x00", "­": b"\x08\x08\x08\x08\x08\x00", "¯": b"\x00\x01\x01\x01\x00\x00", "°": b"\x00\x00\x07\x05\x07\x00", "±": b"\x44\x44\x5f\x44\x44\x00", "²": b"\x1d\x15\x17\x00\x00\x00", "³": b"\x15\x15\x1f\x00\x00\x00", "´": b"\x00\x04\x02\x01\x00\x00", "µ": b"\x7c\x10\x10\x0c\x10\x00", "¶": b"\x02\x07\x7f\x01\x7f\x00", "·": b"\x00\x00\x08\x00\x00\x00", "¸": b"\x00\x40\x60\x00\x00\x00", "¹": b"\x12\x1f\x10\x00\x00\x00", "º": b"\x07\x05\x07\x00\x00\x00", "»": b"\x14\x08\x00\x14\x08\x00", "¼": b"\x21\x17\x38\x24\x72\x00", "½": b"\x21\x17\x78\x54\x5e\x00", "¿": b"\x30\x48\x45\x40\x20\x00", "À": b"\x78\x15\x16\x14\x78\x00", "Á": b"\x78\x14\x16\x15\x78\x00", "Â": b"\x78\x16\x15\x16\x78\x00", "Ã": b"\x7a\x29\x2a\x79\x00\x00", "Ä": b"\x78\x15\x14\x15\x78\x00", "Å": b"\x78\x14\x15\x14\x78\x00", "Æ": b"\x7e\x09\x7f\x49\x49\x00", "Ç": b"\x0e\x51\x71\x11\x08\x00", "È": b"\x7c\x55\x56\x44\x44\x00", "É": b"\x7c\x54\x56\x45\x44\x00", "Ê": b"\x7c\x56\x55\x46\x44\x00", "Ë": b"\x7c\x55\x54\x45\x44\x00", "Ì": b"\x00\x49\x7a\x48\x00\x00", "Í": b"\x00\x48\x7a\x49\x00\x00", "Î": b"\x00\x4a\x79\x4a\x00\x00", "Ï": b"\x44\x45\x7c\x45\x44\x00", "Ð": b"\x08\x7f\x49\x22\x1c\x00", "Ñ": b"\x7a\x11\x22\x79\x00\x00", "Ò": b"\x38\x45\x46\x44\x38\x00", "Ó": b"\x38\x44\x46\x45\x38\x00", "Ô": b"\x38\x46\x45\x46\x38\x00", "Õ": b"\x32\x49\x4a\x31\x00\x00", "Ö": b"\x38\x45\x44\x45\x38\x00", "×": b"\x22\x14\x08\x14\x22\x00", "Ø": b"\x58\x24\x54\x48\x34\x00", "Ù": b"\x38\x41\x42\x40\x38\x00", "Ú": b"\x38\x40\x42\x41\x38\x00", "Û": b"\x38\x42\x41\x42\x38\x00", "Ü": b"\x3c\x41\x40\x41\x3c\x00", "Ý": b"\x04\x08\x72\x09\x04\x00", "Þ": b"\x7f\x22\x22\x22\x1c\x00", "ß": b"\x7e\x11\x25\x25\x1a\x00", "à": b"\x20\x55\x56\x54\x78\x00", "á": b"\x20\x54\x56\x55\x78\x00", "â": b"\x20\x56\x55\x56\x78\x00", "ã": b"\x22\x55\x56\x55\x78\x00", "ä": b"\x20\x55\x54\x55\x78\x00", "å": b"\x20\x54\x55\x54\x78\x00", "æ": b"\x24\x54\x7c\x54\x48\x00", "ç": b"\x1c\x22\x62\x22\x10\x00", "è": b"\x38\x55\x56\x54\x08\x00", "é": b"\x38\x54\x56\x55\x08\x00", "ê": b"\x38\x56\x55\x56\x08\x00", "ë": b"\x38\x55\x54\x55\x08\x00", "ì": b"\x00\x45\x7e\x40\x00\x00", "í": b"\x00\x44\x7e\x41\x00\x00", "î": b"\x00\x46\x7d\x42\x00\x00", "ï": b"\x00\x45\x7c\x41\x00\x00", "ñ": b"\x78\x12\x09\x0a\x71\x00", "ò": b"\x38\x45\x46\x44\x38\x00", "ó": b"\x38\x44\x46\x45\x38\x00", "ô": b"\x38\x46\x45\x46\x38\x00", "õ": b"\x32\x49\x4a\x31\x00\x00", "ö": b"\x38\x45\x44\x45\x38\x00", "÷": b"\x08\x08\x2a\x08\x08\x00", "ø": b"\x58\x24\x54\x48\x34\x00", "ù": b"\x3c\x41\x42\x20\x7c\x00", "ú": b"\x3c\x40\x42\x21\x7c\x00", "û": b"\x3c\x42\x41\x22\x7c\x00", "ü": b"\x3c\x41\x40\x21\x5c\x00", "ű": b"\x3c\x41\x40\x21\x5c\x00", "ų": b"\x3C\x40\x40\x20\xDC\x80", "ý": b"\x44\x48\x32\x11\x0c\x00", "þ": b"\x7c\x28\x28\x10\x00\x00", "ÿ": b"\x44\x49\x30\x11\x0c\x00", # U+0100..U+017F Latin Extended A "Ā": b"\x78\x15\x15\x15\x78\x00", "ā": b"\x20\x55\x55\x55\x78\x00", "Ă": b"\x78\x15\x16\x15\x78\x00", "ă": b"\x20\x55\x56\x55\x78\x00", "Ą": b"\x7e\x09\x09\x49\xbe\x00", "ą": b"\x20\x54\x54\xd4\x78\x00", "Ć": b"\x38\x44\x46\x45\x28\x00", "ć": b"\x38\x44\x46\x45\x20\x00", "Ĉ": b"\x38\x46\x45\x46\x28\x00", "ĉ": b"\x38\x46\x45\x46\x20\x00", "Ċ": b"\x38\x44\x45\x44\x28\x00", "ċ": b"\x38\x44\x45\x44\x20\x00", "Č": b"\x38\x45\x46\x45\x28\x00", "č": b"\x38\x45\x46\x45\x20\x00", "Ď": b"\x7c\x45\x46\x29\x10\x00", "ď": b"\x38\x44\x44\x4A\x7F\x00", "Đ": b"\x08\x7f\x49\x22\x1c\x00", "đ": b"\x38\x44\x44\x4A\x7F\x00", "Ē": b"\x7c\x55\x55\x55\x44\x00", "ē": b"\x38\x55\x55\x55\x08\x00", "Ĕ": b"\x7c\x55\x56\x55\x44\x00", "ĕ": b"\x38\x55\x56\x55\x08\x00", "Ė": b"\x7c\x54\x55\x54\x44\x00", "ė": b"\x38\x54\x55\x54\x08\x00", "Ę": b"\x7f\x49\x49\xc9\x41\x00", "ę": b"\x38\x54\x54\xd4\x18\x00", "Ě": b"\x7c\x55\x56\x55\x44\x00", "ě": b"\x38\x55\x56\x55\x08\x00", "Ĝ": b"\x38\x46\x55\x56\x70\x00", "ĝ": b"\x08\x56\x55\x56\x3c\x00", "Ğ": b"\x38\x45\x56\x55\x30\x00", "ğ": b"\x08\x55\x56\x55\x3c\x00", "Ġ": b"\x38\x44\x55\x54\x30\x00", "ġ": b"\x08\x54\x55\x54\x3c\x00", "Ģ": b"\x0e\x51\x35\x15\x1c\x00", "Ĥ": b"\x7c\x12\x11\x12\x7c\x00", "ĥ": b"\x02\x79\x22\x10\x60\x00", "Ħ": b"\x02\x7f\x0a\x7f\x02\x00", "ħ": b"\x02\x7f\x12\x08\x70\x00", "Ĩ": b"\x4a\x49\x7a\x49\x48\x00", "ĩ": b"\x02\x49\x7a\x41\x00\x00", "Ī": b"\x44\x45\x7d\x45\x44\x00", "ī": b"\x00\x45\x7d\x41\x00\x00", "Ĭ": b"\x44\x45\x7e\x45\x44\x00", "ĭ": b"\x00\x45\x7e\x41\x00\x00", "Į": b"\x00\x41\x7f\xc1\x00\x00", "į": b"\x00\x44\x7d\xc0\x00\x00", "İ": b"\x44\x44\x7d\x44\x44\x00", "ı": b"\x00\x44\x7c\x40\x00\x00", "ij": b"\x44\x7d\x40\x44\x3d\x00", "Ĵ": b"\x20\x40\x46\x3d\x06\x00", "ĵ": b"\x00\x20\x46\x3d\x02\x00", "Ķ": b"\x1f\x44\x2a\x11\x00\x00", "ķ": b"\x1f\x44\x2a\x11\x00\x00", "ĸ": b"\x7c\x10\x28\x44\x00\x00", "Ĺ": b"\x7c\x40\x42\x41\x40\x00", "Ľ": b"\x7c\x40\x42\x41\x40\x00", "ĺ": b"\x00\x44\x7e\x41\x00\x00", "Ļ": b"\x1f\x50\x30\x10\x10\x00", "ļ": b"\x00\x51\x3f\x10\x00\x00", "ľ": b"\x00\x41\x7f\x40\x03\x00", "Ŀ": b"\x7f\x40\x40\x48\x40\x00", "ŀ": b"\x00\x41\x7f\x40\x08\x00", "Ł": b"\x10\x7F\x48\x44\x40\x00", "ł": b"\x00\x49\x7F\x44\x00\x00", "Ń": b"\x7c\x08\x12\x21\x7c\x00", "ń": b"\x7c\x08\x06\x05\x78\x00", "Ņ": b"\x1f\x42\x24\x08\x1f\x00", "ņ": b"\x1f\x42\x21\x01\x1e\x00", "Ň": b"\x7c\x09\x12\x21\x7c\x00", "ň": b"\x7c\x09\x06\x05\x78\x00", "Ō": b"\x38\x45\x45\x45\x38\x00", "ō": b"\x38\x45\x45\x45\x38\x00", "Ŏ": b"\x38\x45\x46\x45\x38\x00", "ŏ": b"\x38\x45\x46\x45\x38\x00", "ő": b"\x38\x45\x44\x45\x38\x00", "Œ": b"\x3e\x41\x7f\x49\x49\x00", "œ": b"\x38\x44\x7c\x54\x58\x00", "Ŕ": b"\x7c\x14\x16\x15\x68\x00", "ŕ": b"\x7c\x08\x06\x05\x08\x00", "Ŗ": b"\x1f\x45\x25\x05\x1a\x00", "ŗ": b"\x1f\x42\x21\x01\x02\x00", "Ř": b"\x7c\x15\x16\x15\x68\x00", "ř": b"\x7c\x09\x06\x05\x08\x00", "Ś": b"\x08\x54\x56\x55\x20\x00", "ś": b"\x48\x54\x56\x55\x24\x00", "Ŝ": b"\x08\x56\x55\x56\x20\x00", "ŝ": b"\x48\x56\x55\x56\x24\x00", "Ş": b"\x02\x55\x35\x15\x08\x00", "ş": b"\x12\x55\x35\x15\x09\x00", "Š": b"\x08\x55\x56\x55\x20\x00", "š": b"\x48\x55\x56\x55\x24\x00", "Ţ": b"\x01\x41\x3f\x01\x01\x00", "ţ": b"\x02\x4f\x32\x10\x08\x00", "Ť": b"\x04\x05\x7e\x05\x04\x00", "ť": b"\x04\x3e\x44\x40\x23\x00", "Ŧ": b"\x01\x09\x7f\x09\x01\x00", "ŧ": b"\x14\x3e\x54\x40\x20\x00", "Ū": b"\x3c\x41\x41\x41\x3c\x00", "ū": b"\x3c\x41\x41\x21\x7c\x00", "Ŭ": b"\x3c\x41\x42\x41\x3c\x00", "ŭ": b"\x3c\x41\x41\x21\x7c\x00", "Ů": b"\x3c\x40\x41\x40\x3c\x00", "ů": b"\x3c\x41\x41\x21\x7c\x00", "Ŵ": b"\x3c\x42\x39\x42\x3c\x00", "ŵ": b"\x3c\x42\x31\x42\x3c\x00", "Ŷ": b"\x04\x0a\x71\x0a\x04\x00", "ŷ": b"\x04\x4a\x31\x12\x0c\x00", "Ÿ": b"\x04\x09\x70\x09\x04\x00", "Ź": b"\x44\x64\x56\x4d\x44\x00", "ź": b"\x44\x64\x56\x4d\x44\x00", "Ż": b"\x44\x64\x55\x4c\x44\x00", "ż": b"\x44\x64\x55\x4c\x44\x00", "Ž": b"\x44\x65\x56\x4d\x44\x00", "ž": b"\x44\x65\x56\x4d\x44\x00", "ſ": b"\x00\x04\x7e\x01\x01\x00", } return font def get_small_font_map_greek() -> Dict[str, bytes]: font = { # U+0370..U+03FF Greek and Coptic "Έ": b"\x03\x7F\x49\x49\x49\x41", "Α": b"\x7e\x09\x09\x09\x7e\x00", "Β": b"\x7f\x49\x49\x49\x36\x00", "Γ": b"\x7f\x01\x01\x01\x01\x00", "Δ": b"\x70\x4C\x43\x4C\x70\x00", "Ε": b"\x7f\x49\x49\x49\x41\x00", "Ζ": b"\x61\x51\x49\x45\x43\x00", "Η": b"\x7f\x08\x08\x08\x7f\x00", "Θ": b"\x3E\x49\x49\x49\x3E\x00", "Ι": b"\x00\x41\x7f\x41\x00\x00", "Κ": b"\x7f\x08\x14\x22\x41\x00", "Λ": b"\x70\x0C\x03\x0C\x70\x00", "Μ": b"\x7f\x02\x0c\x02\x7f\x00", "Ν": b"\x7f\x04\x08\x10\x7f\x00", "Ξ": b"\x41\x49\x49\x49\x41\x00", "Ο": b"\x3e\x41\x41\x41\x3e\x00", "Π": b"\x7F\x01\x01\x01\x7F\x00", "Ρ": b"\x7f\x09\x09\x09\x06\x00", "Σ": b"\x63\x55\x49\x41\x41\x00", "Τ": b"\x01\x01\x7f\x01\x01\x00", "Υ": b"\x07\x08\x70\x08\x07\x00", "Φ": b"\x0c\x12\x7f\x12\x0c\x00", "Χ": b"\x63\x14\x08\x14\x63\x00", "Ψ": b"\x07\x08\x7F\x08\x07\x00", "Ω": b"\x5E\x61\x01\x61\x5E\x00", "ά": b"\x38\x45\x45\x38\x7C\x40", "έ": b"\x28\x55\x55\x44\x28\x00", "ή": b"\x04\x79\x05\x04\xF8\x00", "ί": b"\x04\x3D\x41\x40\x00\x00", "α": b"\x38\x44\x44\x38\x7C\x40", "β": b"\x7E\x21\x25\x25\x1A\x00", "γ": b"\x0C\x10\x60\x10\x0C\x00", "δ": b"\x30\x4B\x45\x49\x30\x00", "ε": b"\x28\x54\x54\x44\x28\x00", "ζ": b"\x00\x31\x49\x45\xC3\x00", "η": b"\x04\x78\x04\x04\xF8\x00", "θ": b"\x3E\x49\x49\x49\x3E\x00", "ι": b"\x04\x3C\x40\x40\x00\x00", "κ": b"\x00\x7C\x10\x28\x44\x00", "λ": b"\x70\x0A\x04\x08\x70\x00", "μ": b"\xFC\x10\x10\x3C\x20\x00", "ν": b"\x1C\x20\x40\x20\x1C\x00", "ξ": b"\x36\x49\x49\xC9\x00\x00", "ο": b"\x38\x44\x44\x44\x38\x00", "π": b"\x04\x7C\x04\x7C\x44\x00", "ρ": b"\xF8\x24\x24\x24\x18\x00", "ς": b"\x38\x44\x44\xC4\x04\x00", "σ": b"\x38\x44\x44\x44\x3C\x04", "τ": b"\x04\x3C\x44\x44\x00\x00", "υ": b"\x3C\x40\x40\x40\x3C\x00", "φ": b"\x18\x24\x7e\x24\x18\x00", "χ": b"\x44\x24\x38\x48\x44\x00", "ψ": b"\x1C\x20\x7C\x20\x1C\x00", "ω": b"\x38\x44\x30\x44\x38\x00", "ό": b"\x38\x45\x45\x44\x38\x00", "ύ": b"\x3C\x41\x41\x40\x3C\x00", "ώ": b"\x38\x45\x31\x44\x38\x00", } return font def get_small_font_map_cyrillic() -> Dict[str, bytes]: font = { # U+0400..U+04FF Cyrillic "Ѐ": b"\x7c\x55\x56\x44\x44\x00", "Ё": b"\x7c\x55\x54\x45\x44\x00", "Ђ": b"\x01\x7f\x09\x49\x31\x00", "Ѓ": b"\x7c\x04\x06\x05\x04\x00", "Є": b"\x3e\x49\x49\x41\x00\x00", "Ѕ": b"\x06\x49\x49\x49\x30\x00", "І": b"\x41\x41\x7f\x41\x41\x00", "Ї": b"\x44\x45\x7c\x45\x44\x00", "Ј": b"\x20\x40\x41\x3f\x01\x00", "Љ": b"\x7f\x01\x7f\x48\x30\x00", "Њ": b"\x7f\x08\x7f\x48\x30\x00", "Ћ": b"\x01\x01\x7f\x09\x71\x00", "Ќ": b"\x7c\x12\x29\x44\x00\x00", "Ѝ": b"\x7c\x21\x12\x08\x7c\x00", "Ў": b"\x44\x49\x32\x09\x04\x00", "Џ": b"\x3f\x20\x60\x20\x3f\x00", "А": b"\x7e\x09\x09\x09\x7e\x00", "Б": b"\x7f\x49\x49\x49\x31\x00", "В": b"\x7f\x49\x49\x49\x36\x00", "Г": b"\x7f\x01\x01\x01\x01\x00", "Ґ": b"\x7E\x02\x02\x02\x03\x00", "Д": b"\x60\x3f\x21\x3f\x60\x00", "Е": b"\x7f\x49\x49\x49\x41\x00", "Ж": b"\x77\x08\x7f\x08\x77\x00", "З": b"\x00\x41\x49\x49\x36\x00", "И": b"\x7f\x10\x08\x04\x7f\x00", "Й": b"\x7c\x21\x12\x09\x7c\x00", "К": b"\x7f\x08\x14\x22\x41\x00", "Л": b"\x40\x3f\x01\x01\x7f\x00", "М": b"\x7f\x02\x04\x02\x7f\x00", "Н": b"\x7f\x08\x08\x08\x7f\x00", "О": b"\x3e\x41\x41\x41\x3e\x00", "П": b"\x7f\x01\x01\x01\x7f\x00", "Р": b"\x7f\x09\x09\x09\x06\x00", "С": b"\x3e\x41\x41\x41\x22\x00", "Т": b"\x01\x01\x7f\x01\x01\x00", "У": b"\x47\x48\x30\x08\x07\x00", "Ф": b"\x0c\x12\x7f\x12\x0c\x00", "Х": b"\x63\x14\x08\x14\x63\x00", "Ц": b"\x3f\x20\x20\x3f\x60\x00", "Ч": b"\x07\x08\x08\x08\x7f\x00", "Ш": b"\x7F\x40\x7F\x40\x7F\x00", "Щ": b"\x7F\x40\x7F\x40\x7F\xC0", "Ъ": b"\x01\x7f\x48\x48\x30\x00", "Ы": b"\x7f\x48\x30\x00\x7f\x00", "Ь": b"\x00\x7f\x48\x48\x30\x00", "Э": b"\x22\x49\x49\x2a\x1c\x00", "Ю": b"\x7f\x08\x3e\x41\x3e\x00", "Я": b"\x46\x29\x19\x09\x7f\x00", "а": b"\x20\x54\x54\x54\x78\x00", "б": b"\x3c\x4a\x4a\x4a\x30\x00", "в": b"\x7c\x54\x54\x54\x28\x00", "г": b"\x7c\x04\x04\x04\x04\x00", "ґ": b"\x7C\x04\x04\x04\x06\x00", "д": b"\x40\x3c\x24\x3c\x60\x00", "е": b"\x38\x54\x54\x54\x18\x00", "ж": b"\x6c\x10\x7c\x10\x6c\x00", "з": b"\x28\x44\x54\x54\x28\x00", "и": b"\x7c\x20\x10\x08\x7c\x00", "й": b"\x7c\x21\x12\x09\x7c\x00", "к": b"\x7c\x10\x28\x44\x00\x00", "л": b"\x40\x3c\x04\x04\x7c\x00", "м": b"\x7c\x08\x10\x08\x7c\x00", "н": b"\x7c\x10\x10\x10\x7c\x00", "о": b"\x38\x44\x44\x44\x38\x00", "п": b"\x7c\x04\x04\x04\x7c\x00", "р": b"\x7c\x14\x14\x14\x08\x00", "с": b"\x38\x44\x44\x44\x20\x00", "т": b"\x04\x04\x7c\x04\x04\x00", "у": b"\x4c\x50\x20\x10\x0c\x00", "ф": b"\x18\x24\x7e\x24\x18\x00", "х": b"\x44\x28\x10\x28\x44\x00", "ц": b"\x3c\x20\x20\x3c\x60\x00", "ч": b"\x0c\x10\x10\x10\x7c\x00", "ш": b"\x7C\x40\x7C\x40\x7C\x00", "щ": b"\x7C\x40\x7C\x40\xFC\x00", "ъ": b"\x04\x7c\x50\x20\x00\x00", "ы": b"\x7c\x50\x20\x00\x7c\x00", "ь": b"\x00\x7c\x50\x20\x00\x00", "э": b"\x28\x44\x54\x54\x28\x00", "ю": b"\x7c\x10\x38\x44\x38\x00", "я": b"\x48\x34\x14\x14\x7c\x00", "ѐ": b"\x38\x55\x56\x54\x08\x00", "ё": b"\x38\x55\x54\x55\x08\x00", "ђ": b"\x02\x3f\x12\x48\x30\x00", "ѓ": b"\x7c\x04\x06\x05\x04\x00", "є": b"\x38\x54\x54\x44\x28\x00", "ѕ": b"\x08\x54\x54\x54\x20\x00", "і": b"\x00\x44\x7d\x40\x00\x00", "ї": b"\x00\x45\x7c\x41\x00\x00", "ј": b"\x20\x40\x44\x3d\x00\x00", "љ": b"\x7c\x04\x7c\x50\x20\x00", "њ": b"\x7c\x10\x7c\x50\x20\x00", "ћ": b"\x04\x7e\x14\x10\x60\x00", "ќ": b"\x7c\x12\x29\x44\x00\x00", "ѝ": b"\x7c\x21\x12\x08\x7c\x00", "ў": b"\x4c\x51\x22\x11\x0c\x00", "џ": b"\x3c\x20\x60\x20\x3c\x00", } return font NAME_ASCII_BASIC: Final = "ascii_basic" NAME_LATIN_EXTENDED: Final = "latin_extended" NAME_CYRILLIC: Final = "cyrillic" NAME_CJK: Final = "cjk" NAME_GREEK: Final = "greek" ALL_FONTS = [ NAME_ASCII_BASIC, NAME_LATIN_EXTENDED, NAME_CYRILLIC, NAME_GREEK, NAME_CJK, # CJK must come last ] ALL_PRE_RENDERED_FONTS = [ NAME_ASCII_BASIC, NAME_LATIN_EXTENDED, NAME_CYRILLIC, NAME_GREEK, ] def get_font_maps_for_name( font_name: str, ) -> Tuple[Dict[str, bytes], Dict[str, bytes]]: if font_name == NAME_ASCII_BASIC: return get_font_map_ascii_basic(), get_small_font_map_ascii_basic() elif font_name == NAME_LATIN_EXTENDED: return get_font_map_latin_extended(), get_small_font_map_latin_extended() elif font_name == NAME_CYRILLIC: return get_font_map_cyrillic(), get_small_font_map_cyrillic() elif font_name == NAME_GREEK: return get_font_map_greek(), get_small_font_map_greek() else: raise ValueError("Invalid font name") ================================================ FILE: Translations/gen_menu_docs.py ================================================ #!/usr/bin/env python3 import json import logging import os import sys from pathlib import Path logging.basicConfig(stream=sys.stdout, level=logging.DEBUG) HERE = Path(__file__).resolve().parent TRANSLATION_DEFS_PATH = os.path.join(HERE, "translations_definitions.json") ENGLISH_TRANSLATION_PATH = os.path.join(HERE, "translation_EN.json") MENU_DOCS_FILE_PATH = os.path.join(HERE.parent, "Documentation/Settings.md") # Loading a single JSON file def load_json(filename: str, skip_first_line: bool) -> dict: with open(filename) as f: if skip_first_line: f.readline() return json.loads(f.read()) def write_header(filep): """ Writes the markdown constant header area out """ constant_header = """ # IronOS Settings Menu The below breaks down the menu's and what each setting means. """ filep.write(constant_header) def write_menu_categories(filep, defs, translation_data): """ Writes the menu categories section out """ menu_cat_pretense = """ ## Menu Categories In the menu there are a few main categories that are used to keep the list manageable. """ filep.write(menu_cat_pretense) for menu in defs.get("menuGroups", {}): menu_id = menu.get("id", "") entry = translation_data.get("menuGroups", {}).get(menu_id, "") name = " ".join(entry.get("displayText").split("\n")) desc = menu.get("description", "") section = f""" ### Category: {name} {desc} """ filep.write(section) def write_menu_entries(filep, defs, translation_data): """ Writes the menu entries section out """ menu_entries_pretense = """ ## Settings These are all of the settings possible in the menu. **Not all settings are visible for all devices.** For example, the TS100 does not have USB-PD settings. When using the device, if unsure you can pause (press nothing) on a setting and after a short delay help text will scroll across the screen. This is the "on device help text". """ filep.write(menu_entries_pretense) for menu in defs.get("menuOptions", {}): menu_id = menu.get("id", "") entry = translation_data.get("menuOptions", {}).get(menu_id, "") name = " ".join(entry.get("displayText").split("\n")) desc = menu.get("description", "") on_device_desc = entry.get("description", "") section = f""" ### Setting: {name} {desc} On device help text: {on_device_desc} """ filep.write(section) def main() -> None: json_dir = HERE print(json_dir) logging.info("Loading translation definitions") defs = load_json(TRANSLATION_DEFS_PATH, False) eng_translation = load_json(ENGLISH_TRANSLATION_PATH, False) with open(MENU_DOCS_FILE_PATH, "w") as outputf: write_header(outputf) write_menu_categories(outputf, defs, eng_translation) write_menu_entries(outputf, defs, eng_translation) logging.info("Done") if __name__ == "__main__": main() ================================================ FILE: Translations/make_translation.py ================================================ #!/usr/bin/env python3 import argparse import functools import json import hashlib import logging import os import pickle import re import subprocess import sys import time from pathlib import Path from typing import Dict, List, Optional, TextIO, Tuple, Union from dataclasses import dataclass from bdflib import reader as bdfreader from bdflib.model import Font, Glyph import font_tables import brieflz import objcopy logging.basicConfig(stream=sys.stdout, level=logging.DEBUG) HERE = Path(__file__).resolve().parent @functools.lru_cache(maxsize=None) def cjk_font() -> Font: with open(os.path.join(HERE, "wqy-bitmapsong/wenquanyi_9pt.bdf"), "rb") as f: return bdfreader.read_bdf(f) # Loading a single JSON file def load_json(filename: str) -> dict: with open(filename) as f: return json.loads(f.read()) def get_language_unqiue_id(language_ascii_name: str): """ Given a language code, it will return a unique (enough) uint16_t id code When we have a collision here we can tweak this, but language list should be fairly stable from now on """ return ( int(hashlib.sha1(language_ascii_name.encode("utf-8")).hexdigest(), 16) % 0xFFFF ) def read_translation(json_root: Union[str, Path], lang_code: str) -> dict: filename = f"translation_{lang_code}.json" file_with_path = os.path.join(json_root, filename) try: lang = load_json(file_with_path) except json.decoder.JSONDecodeError as e: logging.error(f"Failed to decode {filename}") logging.exception(str(e)) sys.exit(2) validate_langcode_matches_content(filename, lang) return lang def filter_translation(lang: dict, defs: dict, macros: frozenset): def check_excluded(record): if "include" in record and not any(m in macros for m in record["include"]): return True if "exclude" in record and any(m in macros for m in record["exclude"]): return True return False for category in ("menuOptions", "menuGroups", "menuValues"): for _, record in enumerate(defs[category]): if check_excluded(record): lang[category][record["id"]]["displayText"] = "" lang[category][record["id"]]["description"] = "" for _, record in enumerate(defs["messagesWarn"]): if check_excluded(record): lang["messagesWarn"][record["id"]]["message"] = "" return lang def validate_langcode_matches_content(filename: str, content: dict) -> None: # Extract lang code from file name lang_code = filename[12:-5].upper() # ...and the one specified in the JSON file... try: lang_code_from_json = content["languageCode"] except KeyError: lang_code_from_json = "(missing)" # ...cause they should be the same! if lang_code != lang_code_from_json: raise ValueError( f"Invalid languageCode {lang_code_from_json} in file {filename}" ) def write_start(f: TextIO): f.write( "// WARNING: THIS FILE WAS AUTO GENERATED BY make_translation.py. PLEASE DO NOT EDIT.\n" ) f.write("\n") f.write('#include "Translation.h"\n') def get_constants() -> List[Tuple[str, str]]: # Extra constants that are used in the firmware that are shared across all languages return [ ("LargeSymbolPlus", "+"), ("SmallSymbolPlus", "+"), ("LargeSymbolMinus", "-"), ("SmallSymbolMinus", "-"), ("LargeSymbolSpace", " "), ("SmallSymbolSpace", " "), ("LargeSymbolDot", "."), ("SmallSymbolDot", "."), ("SmallSymbolSlash", "/"), ("SmallSymbolColon", ":"), ("LargeSymbolDegC", "C"), ("SmallSymbolDegC", "C"), ("LargeSymbolDegF", "F"), ("SmallSymbolDegF", "F"), ("LargeSymbolMinutes", "m"), ("SmallSymbolMinutes", "m"), ("LargeSymbolSeconds", "s"), ("SmallSymbolSeconds", "s"), ("LargeSymbolWatts", "W"), ("SmallSymbolWatts", "W"), ("LargeSymbolVolts", "V"), ("SmallSymbolVolts", "V"), ("SmallSymbolAmps", "A"), ("LargeSymbolDC", "DC"), ("LargeSymbolCellCount", "S"), ("SmallSymbolVersionNumber", read_version()), ("SmallSymbolPDDebug", "PD Debug"), ("SmallSymbolState", "State"), ("SmallSymbolNoVBus", "No VBus"), ("SmallSymbolVBus", "VBus"), ("LargeSymbolSleep", "Zzz "), ] def get_debug_menu() -> List[str]: return [ time.strftime( "%Y%m%d %H%M%S", time.gmtime(int(os.environ.get("SOURCE_DATE_EPOCH", time.time()))), ), "ID ", "ACC ", "PWR ", "Vin ", "Tip C ", "Han C ", "Max C ", "UpTime ", "Move ", "Tip Res", "Tip R ", "Tip O ", "HW G ", "HW M ", "HW P ", "Hall ", ] def get_accel_names_list() -> List[str]: return [ "Scanning", "None", "MMA8652FC", "LIS2DH12", "BMA223", "MSA301", "SC7A20", "GPIO", "LIS2 CLONE", ] def get_power_source_list() -> List[str]: return [ "DC", "QC", "PV:PDwVBus", "PD:No VBus", ] def test_is_small_font(msg: str) -> bool: return "\n" in msg and msg[0] != "\n" def get_letter_counts(defs: dict, lang: dict, build_version: str) -> Dict: """From the source definitions, language file and build version; calculates the ranked symbol list Args: defs (dict): Definitions lang (dict): Language lookup build_version (str): The build version id to ensure its letters are included Returns: Dict: _description_ """ big_font_messages = [] small_font_messages = [] # iterate over all strings obj = lang["messagesWarn"] for mod in defs["messagesWarn"]: eid = mod["id"] msg = obj[eid]["message"] if test_is_small_font(msg): small_font_messages.append(msg) else: big_font_messages.append(msg) obj = lang["characters"] for mod in defs["characters"]: eid = mod["id"] msg = obj[eid] if test_is_small_font(msg): small_font_messages.append(msg) else: big_font_messages.append(msg) obj = lang["menuOptions"] for mod in defs["menuOptions"]: eid = mod["id"] msg = obj[eid]["displayText"] if test_is_small_font(msg): small_font_messages.append(msg) else: big_font_messages.append(msg) obj = lang["menuOptions"] for mod in defs["menuOptions"]: eid = mod["id"] msg = obj[eid]["description"] big_font_messages.append(msg) obj = lang["menuValues"] for mod in defs["menuValues"]: eid = mod["id"] msg = obj[eid]["displayText"] if test_is_small_font(msg): small_font_messages.append(msg) else: big_font_messages.append(msg) obj = lang["menuGroups"] for mod in defs["menuGroups"]: eid = mod["id"] msg = obj[eid]["displayText"] if test_is_small_font(msg): small_font_messages.append(msg) else: big_font_messages.append(msg) obj = lang["menuGroups"] for mod in defs["menuGroups"]: eid = mod["id"] msg = obj[eid]["description"] big_font_messages.append(msg) constants = get_constants() for x in constants: if x[0].startswith("Small"): small_font_messages.append(x[1]) else: big_font_messages.append(x[1]) small_font_messages.extend(get_debug_menu()) small_font_messages.extend(get_accel_names_list()) small_font_messages.extend(get_power_source_list()) # collapse all strings down into the composite letters and store totals for these # Doing this seperately for small and big font def sort_and_count(list_in: List[str]): symbol_counts: dict[str, int] = {} for line in list_in: line = line.replace("\n", "").replace("\r", "") line = line.replace("\\n", "").replace("\\r", "") if line: for letter in line: symbol_counts[letter] = symbol_counts.get(letter, 0) + 1 # swap to Big -> little sort order return symbol_counts small_symbol_counts = sort_and_count(small_font_messages) big_symbol_counts = sort_and_count(big_font_messages) return { "smallFontCounts": small_symbol_counts, "bigFontCounts": big_symbol_counts, } def convert_letter_counts_to_ranked_symbols_with_forced( symbol_dict: Dict[str, int] ) -> List[str]: # Add in forced symbols first ranked_symbols = [] ranked_symbols.extend(get_forced_first_symbols()) # Now add in all the others based on letter count symbols_by_occurrence = [ x[0] for x in sorted( symbol_dict.items(), key=lambda kv: (kv[1], kv[0]), reverse=True ) ] ranked_symbols.extend([x for x in symbols_by_occurrence if x not in ranked_symbols]) return ranked_symbols def merge_letter_count_info(a: Dict, b: Dict) -> Dict: """Merge the results from get_letter_counts Combining the ranked symbols lists Args: a (Dict): get_letter_counts b (Dict): get_letter_counts Returns: Dict: get_letter_counts """ smallFontCounts = {} bigFontCounts = {} for x in a.get("smallFontCounts", []): old = smallFontCounts.get(x, 0) old += a["smallFontCounts"][x] smallFontCounts[x] = old for x in a.get("bigFontCounts", []): old = bigFontCounts.get(x, 0) old += a["bigFontCounts"][x] bigFontCounts[x] = old for x in b.get("smallFontCounts", []): old = smallFontCounts.get(x, 0) old += b["smallFontCounts"][x] smallFontCounts[x] = old for x in b.get("bigFontCounts", []): old = bigFontCounts.get(x, 0) old += b["bigFontCounts"][x] bigFontCounts[x] = old return { "smallFontCounts": smallFontCounts, "bigFontCounts": bigFontCounts, } def get_cjk_glyph(sym: str) -> Optional[bytes]: try: glyph: Glyph = cjk_font()[ord(sym)] except KeyError: return None data = glyph.data src_left, src_bottom, src_w, src_h = glyph.get_bounding_box() dst_w = 12 dst_h = 16 # The source data is a per-row list of ints. The first item is the bottom- # most row. For each row, the LSB is the right-most pixel. # Here, (x, y) is the coordinates with origin at the top-left. def get_cell(x: int, y: int) -> bool: # Adjust x coordinates by actual bounding box. adj_x = x - src_left if adj_x < 0 or adj_x >= src_w: return False # Adjust y coordinates by actual bounding box, then place the glyph # baseline 3px above the bottom edge to make it centre-ish. # This metric is optimized for WenQuanYi Bitmap Song 9pt and assumes # each glyph is to be placed in a 12x12px box. adj_y = y - (dst_h - src_h - src_bottom - 3) if adj_y < 0 or adj_y >= src_h: return False if data[src_h - adj_y - 1] & (1 << (src_w - adj_x - 1)): return True else: return False # A glyph in the font table is divided into upper and lower parts, each by # 8px high. Each byte represents half if a column, with the LSB being the # top-most pixel. The data goes from the left-most to the right-most column # of the top half, then from the left-most to the right-most column of the # bottom half. bs = bytearray() for block in range(2): for c in range(dst_w): b = 0 for r in range(8): if get_cell(c, r + 8 * block): b |= 0x01 << r bs.append(b) return bytes(bs) def get_bytes_from_font_index(index: int) -> bytes: """ Converts the font table index into its corresponding bytes """ # We want to be able to use more than 254 symbols (excluding \x00 null # terminator and \x01 new-line) in the font table but without making all # the chars take 2 bytes. To do this, we use \xF1 to \xFF as lead bytes # to designate double-byte chars, and leave the remaining as single-byte # chars. # # For the sake of sanity, \x00 always means the end of string, so we skip # \xF1\x00 and others in the mapping. # # Mapping example: # # 0x02 => 2 # 0x03 => 3 # ... # 0xEF => 239 # 0xF0 => 240 # 0xF1 0x01 => 1 * 0xFF - 15 + 1 = 241 # 0xF1 0x02 => 1 * 0xFF - 15 + 2 = 242 # ... # 0xF1 0xFF => 1 * 0xFF - 15 + 255 = 495 # 0xF2 0x01 => 2 * 0xFF - 15 + 1 = 496 # ... # 0xF2 0xFF => 2 * 0xFF - 15 + 255 = 750 # 0xF3 0x01 => 3 * 0xFF - 15 + 1 = 751 # ... # 0xFF 0xFF => 15 * 0xFF - 15 + 255 = 4065 if index < 0: raise ValueError("index must be positive") page = (index + 0x0E) // 0xFF if page > 0x0F: raise ValueError("page value out of range") if page == 0: return bytes([index]) else: # Into extended range # Leader is 0xFz where z is the page number # Following char is the remainder leader = page + 0xF0 value = ((index + 0x0E) % 0xFF) + 0x01 if leader > 0xFF or value > 0xFF: raise ValueError("value is out of range") return bytes([leader, value]) def bytes_to_escaped(b: bytes) -> str: return "".join((f"\\x{i:02X}" for i in b)) def bytes_to_c_hex(b: bytes) -> str: return ", ".join((f"0x{i:02X}" for i in b)) + "," @dataclass class FontMapsPerFont: font12_symbols_ordered: List[str] font12_maps: Dict[str, Dict[str, bytes]] font06_symbols_ordered: List[str] font06_maps: Dict[str, Dict[str, bytes]] def get_font_map_per_font( text_list_small_font: List[str], text_list_large_font: List[str] ) -> FontMapsPerFont: pending_small_symbols = set(text_list_small_font) pending_large_symbols = set(text_list_large_font) if len(pending_small_symbols) != len(text_list_small_font): raise ValueError("`text_list_small_font` contains duplicated symbols") if len(pending_large_symbols) != len(text_list_large_font): raise ValueError("`text_list_large_font` contains duplicated symbols") total_symbol_count_small = len(pending_small_symbols) # \x00 is for NULL termination and \x01 is for newline, so the maximum # number of symbols allowed is as follow (see also the comments in # `get_bytes_from_font_index`): if total_symbol_count_small > (0x10 * 0xFF - 15) - 2: # 4063 raise ValueError( f"Error, too many used symbols for this version (total {total_symbol_count_small})" ) logging.info(f"Generating fonts for {total_symbol_count_small} symbols") total_symbol_count_large = len(pending_large_symbols) # \x00 is for NULL termination and \x01 is for newline, so the maximum # number of symbols allowed is as follow (see also the comments in # `get_bytes_from_font_index`): if total_symbol_count_large > (0x10 * 0xFF - 15) - 2: # 4063 raise ValueError( f"Error, too many used symbols for this version (total {total_symbol_count_large})" ) logging.info(f"Generating fonts for {total_symbol_count_large} symbols") # Build the full font maps font12_map: Dict[str, bytes] = {} font06_map: Dict[str, bytes] = {} # First we go through and do all of the CJK characters that are in the large font to have them removed for sym in text_list_large_font: font12_line = get_cjk_glyph(sym) if font12_line is None: continue font12_map[sym] = font12_line pending_large_symbols.remove(sym) # Now that all CJK characters are done, we next have to fill out all of the small and large fonts from the remainders # This creates our superset of characters to reference off that are pre-rendered ones (non CJK) # Collect font bitmaps by the defined font order: for font in font_tables.ALL_PRE_RENDERED_FONTS: font12, font06 = font_tables.get_font_maps_for_name(font) font12_map.update(font12) font06_map.update(font06) # LARGE FONT for sym in text_list_large_font: if sym in pending_large_symbols: font_data = font12_map.get(sym, None) if font_data is None: raise KeyError(f"Symbol |{sym}| is missing in large font set") font12_map[sym] = font_data pending_large_symbols.remove(sym) if len(pending_large_symbols) > 0: raise KeyError( f"Missing large font symbols for {len(pending_large_symbols)} characters: {pending_large_symbols}" ) # SMALL FONT for sym in text_list_small_font: if sym in pending_small_symbols: font_data = font06_map.get(sym, None) if font_data is None: raise KeyError(f"Symbol |{sym}| is missing in small font set") font06_map[sym] = font_data pending_small_symbols.remove(sym) if len(pending_small_symbols) > 0: raise KeyError( f"Missing small font symbols for {len(pending_small_symbols)} characters: {pending_small_symbols}" ) return FontMapsPerFont( text_list_large_font, font12_map, text_list_small_font, font06_map ) def get_forced_first_symbols() -> List[str]: """Get the list of symbols that must always occur at start of small and large fonts Used by firmware for displaying numbers and hex strings Returns: List[str]: List of single character strings that must be the first N entries in a font table """ forced_first_symbols = [ "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "a", "b", "c", "d", "e", "f", " ", # We lock these to ease printing functions; and they are always included due to constants "-", "+", ] return forced_first_symbols def build_symbol_conversion_map(sym_list: List[str]) -> Dict[str, bytes]: forced_first_symbols = get_forced_first_symbols() if sym_list[: len(forced_first_symbols)] != forced_first_symbols: raise ValueError("Symbol list does not start with forced_first_symbols.") # the text list is sorted # allocate out these in their order as number codes symbol_map: Dict[str, bytes] = {"\n": bytes([1])} index = 2 # start at 2, as 0= null terminator,1 = new line # Assign symbol bytes by font index for index, sym in enumerate(sym_list, index): assert sym not in symbol_map symbol_map[sym] = get_bytes_from_font_index(index) return symbol_map def make_font_table_cpp( small_font_sym_list: List[str], large_font_sym_list: List[str], font_map: FontMapsPerFont, small_symbol_map: Dict[str, bytes], large_symbol_map: Dict[str, bytes], ) -> str: output_table = make_font_table_named_cpp( "USER_FONT_12", large_font_sym_list, font_map.font12_maps ) output_table += make_font_table_06_cpp(small_font_sym_list, font_map) return output_table def make_font_table_named_cpp( name: Optional[str], sym_list: List[str], font_map: Dict[str, bytes], ) -> str: output_table = "" if name: output_table = f"const uint8_t {name}[] = {{\n" for i, sym in enumerate(sym_list): output_table += f"{bytes_to_c_hex(font_map[sym])}//0x{i + 2:X} -> {sym}\n" if name: output_table += f"}}; // {name}\n" return output_table def make_font_table_06_cpp(sym_list: List[str], font_map: FontMapsPerFont) -> str: output_table = "const uint8_t USER_FONT_6x8[] = {\n" for i, sym in enumerate(sym_list): font_bytes = font_map.font06_maps[sym] if font_bytes: font_line = bytes_to_c_hex(font_bytes) else: font_line = "// " # placeholder output_table += f"{font_line}//0x{i + 2:X} -> {sym}\n" output_table += "};\n" return output_table def convert_string_bytes(symbol_conversion_table: Dict[str, bytes], text: str) -> bytes: # convert all of the symbols from the string into bytes for their content output_string = b"" for c in text.replace("\\r", "").replace("\\n", "\n"): if c not in symbol_conversion_table: print(symbol_conversion_table) logging.error(f"Missing font definition for {c}") raise KeyError(f"Missing font definition for {c}") else: output_string += symbol_conversion_table[c] return output_string def convert_string(symbol_conversion_table: Dict[str, bytes], text: str) -> str: # convert all of the symbols from the string into escapes for their content return bytes_to_escaped(convert_string_bytes(symbol_conversion_table, text)) def escape(string: str) -> str: return json.dumps(string, ensure_ascii=False) def write_bytes_as_c_array( f: TextIO, name: str, data: bytes, indent: int = 2, bytes_per_line: int = 16 ) -> None: f.write(f"const uint8_t {name}[] = {{\n") for i in range(0, len(data), bytes_per_line): f.write(" " * indent) f.write(", ".join((f"0x{b:02X}" for b in data[i : i + bytes_per_line]))) f.write(",\n") f.write(f"}}; // {name}\n\n") @dataclass class LanguageData: langs: List[dict] defs: dict build_version: str small_text_symbols: List[str] large_text_symbols: List[str] font_map: FontMapsPerFont def prepare_language(lang: dict, defs: dict, build_version: str) -> LanguageData: language_code: str = lang["languageCode"] logging.info(f"Preparing language data for {language_code}") # Iterate over all of the text to build up the symbols & counts letter_count_data = get_letter_counts(defs, lang, build_version) small_font_symbols = convert_letter_counts_to_ranked_symbols_with_forced( letter_count_data["smallFontCounts"] ) large_font_symbols = convert_letter_counts_to_ranked_symbols_with_forced( letter_count_data["bigFontCounts"] ) # From the letter counts, need to make a symbol index and matching font index font_data = get_font_map_per_font(small_font_symbols, large_font_symbols) return LanguageData( [lang], defs, build_version, small_font_symbols, large_font_symbols, font_data, ) def prepare_languages( langs: List[dict], defs: dict, build_version: str ) -> LanguageData: language_codes: List[str] = [lang["languageCode"] for lang in langs] logging.info(f"Preparing language data for {language_codes}") # Build the full font maps total_symbol_counts: Dict[str, Dict[str, int]] = {} for lang in langs: letter_count_data = get_letter_counts(defs, lang, build_version) total_symbol_counts = merge_letter_count_info( total_symbol_counts, letter_count_data ) small_font_symbols = convert_letter_counts_to_ranked_symbols_with_forced( total_symbol_counts["smallFontCounts"] ) large_font_symbols = convert_letter_counts_to_ranked_symbols_with_forced( total_symbol_counts["bigFontCounts"] ) font_data = get_font_map_per_font(small_font_symbols, large_font_symbols) return LanguageData( langs, defs, build_version, small_font_symbols, large_font_symbols, font_data, ) def render_font_block(data: LanguageData, f: TextIO, compress_font: bool = False): font_map = data.font_map small_font_symbol_conversion_table = build_symbol_conversion_map( data.small_text_symbols ) large_font_symbol_conversion_table = build_symbol_conversion_map( data.large_text_symbols ) if not compress_font: font_table_text = make_font_table_cpp( data.small_text_symbols, data.large_text_symbols, font_map, small_font_symbol_conversion_table, large_font_symbol_conversion_table, ) f.write(font_table_text) f.write( "const FontSection FontSectionInfo = {\n" " .font12_start_ptr = USER_FONT_12,\n" " .font06_start_ptr = USER_FONT_6x8,\n" " .font12_decompressed_size = 0,\n" " .font06_decompressed_size = 0,\n" " .font12_compressed_source = 0,\n" " .font06_compressed_source = 0,\n" "};\n" ) else: font12_uncompressed = bytearray() for sym in data.large_text_symbols: font12_uncompressed.extend(font_map.font12_maps[sym]) font12_compressed = brieflz.compress(bytes(font12_uncompressed)) logging.info( f"Font table 12x16 compressed from {len(font12_uncompressed)} to {len(font12_compressed)} bytes (ratio {len(font12_compressed) / len(font12_uncompressed):.3})" ) write_bytes_as_c_array(f, "font_12x16_brieflz", font12_compressed) font06_uncompressed = bytearray() for sym in data.small_text_symbols: font06_uncompressed.extend(font_map.font06_maps[sym]) font06_compressed = brieflz.compress(bytes(font06_uncompressed)) logging.info( f"Font table 06x08 compressed from {len(font06_uncompressed)} to {len(font06_compressed)} bytes (ratio {len(font06_compressed) / len(font06_uncompressed):.3})" ) write_bytes_as_c_array(f, "font_06x08_brieflz", font06_compressed) f.write( f"static uint8_t font12_out_buffer[{len(font12_uncompressed)}];\n" f"static uint8_t font06_out_buffer[{len(font06_uncompressed)}];\n" "const FontSection FontSectionInfo = {\n" " .font12_start_ptr = font12_out_buffer,\n" " .font06_start_ptr = font06_out_buffer,\n" f" .font12_decompressed_size = {len(font12_uncompressed)},\n" f" .font06_decompressed_size = {len(font06_uncompressed)},\n" " .font12_compressed_source = font_12x16_brieflz,\n" " .font06_compressed_source = font_06x08_brieflz,\n" "};\n" ) def write_language( data: LanguageData, f: TextIO, strings_bin: Optional[bytes] = None, compress_font: bool = False, ) -> None: if len(data.langs) > 1: raise ValueError("More than 1 languages are provided") lang = data.langs[0] defs = data.defs small_font_symbol_conversion_table = build_symbol_conversion_map( data.small_text_symbols ) large_font_symbol_conversion_table = build_symbol_conversion_map( data.large_text_symbols ) language_code: str = lang["languageCode"] logging.info(f"Generating block for {language_code}") try: lang_name = lang["languageLocalName"] except KeyError: lang_name = language_code if strings_bin or compress_font: f.write('#include "brieflz.h"\n') f.write(f"\n// ---- {lang_name} ----\n\n") render_font_block(data, f, compress_font) f.write(f"\n// ---- {lang_name} ----\n\n") translation_common_text = get_translation_common_text( small_font_symbol_conversion_table, large_font_symbol_conversion_table ) f.write(translation_common_text) f.write( f"const bool HasFahrenheit = {('true' if lang.get('tempUnitFahrenheit', True) else 'false')};\n\n" ) if not strings_bin: translation_strings_and_indices_text = get_translation_strings_and_indices_text( lang, defs, small_font_symbol_conversion_table, large_font_symbol_conversion_table, ) f.write(translation_strings_and_indices_text) f.write( "const TranslationIndexTable *Tr = &translation.indices;\n" "const char *TranslationStrings = translation.strings;\n\n" ) else: compressed = brieflz.compress(strings_bin) logging.info( f"Strings compressed from {len(strings_bin)} to {len(compressed)} bytes (ratio {len(compressed) / len(strings_bin):.3})" ) write_bytes_as_c_array(f, "translation_data_brieflz", compressed) f.write( f"static uint8_t translation_data_out_buffer[{len(strings_bin)}] __attribute__((__aligned__(2)));\n\n" "const TranslationIndexTable *Tr = reinterpret_cast(translation_data_out_buffer);\n" "const char *TranslationStrings = reinterpret_cast(translation_data_out_buffer) + sizeof(TranslationIndexTable);\n\n" ) if not strings_bin and not compress_font: f.write("void prepareTranslations() {}\n\n") else: f.write("void prepareTranslations() {\n") if compress_font: f.write( " blz_depack_srcsize(font_12x16_brieflz, font_out_buffer, sizeof(font_12x16_brieflz));\n" ) if strings_bin: f.write( " blz_depack_srcsize(translation_data_brieflz, translation_data_out_buffer, sizeof(translation_data_brieflz));\n" ) f.write("}\n\n") sanity_checks_text = get_translation_sanity_checks_text(defs) f.write(sanity_checks_text) def write_languages( data: LanguageData, f: TextIO, strings_obj_path: Optional[str] = None, compress_font: bool = False, ) -> None: defs = data.defs small_font_symbol_conversion_table = build_symbol_conversion_map( data.small_text_symbols ) large_font_symbol_conversion_table = build_symbol_conversion_map( data.large_text_symbols ) language_codes: List[str] = [lang["languageCode"] for lang in data.langs] logging.info(f"Generating block for {language_codes}") lang_names = [ lang.get("languageLocalName", lang["languageCode"]) for lang in data.langs ] f.write('#include "Translation_multi.h"') f.write(f"\n// ---- {lang_names} ----\n\n") render_font_block(data, f, compress_font) f.write(f"\n// ---- {lang_names} ----\n\n") translation_common_text = get_translation_common_text( small_font_symbol_conversion_table, large_font_symbol_conversion_table ) f.write(translation_common_text) f.write( f"const bool HasFahrenheit = {('true' if any([lang.get('tempUnitFahrenheit', True) for lang in data.langs]) else 'false')};\n\n" ) max_decompressed_translation_size = 0 if not strings_obj_path: for lang in data.langs: lang_code = lang["languageCode"] translation_strings_and_indices_text = ( get_translation_strings_and_indices_text( lang, defs, small_font_symbol_conversion_table, large_font_symbol_conversion_table, suffix=f"_{lang_code}", ) ) f.write(translation_strings_and_indices_text) f.write("const LanguageMeta LanguageMetas[] = {\n") for lang in data.langs: lang_code = lang["languageCode"] lang_id = get_language_unqiue_id(lang_code) f.write( " {\n" f" .uniqueID = {lang_id},\n" f" .translation_data = reinterpret_cast(&translation_{lang_code}),\n" f" .translation_size = sizeof(translation_{lang_code}),\n" f" .translation_is_compressed = false,\n" " },\n" ) f.write("};\n") else: for lang in data.langs: lang_code = lang["languageCode"] sym_name = objcopy.cpp_var_to_section_name(f"translation_{lang_code}") strings_bin = objcopy.get_binary_from_obj(strings_obj_path, sym_name) if len(strings_bin) == 0: raise ValueError(f"Output for {sym_name} is empty") max_decompressed_translation_size = max( max_decompressed_translation_size, len(strings_bin) ) compressed = brieflz.compress(strings_bin) logging.info( f"Strings for {lang_code} compressed from {len(strings_bin)} to {len(compressed)} bytes (ratio {len(compressed) / len(strings_bin):.3})" ) write_bytes_as_c_array( f, f"translation_data_brieflz_{lang_code}", compressed ) f.write("const LanguageMeta LanguageMetas[] = {\n") for lang in data.langs: lang_code = lang["languageCode"] lang_id = get_language_unqiue_id(lang_code) f.write( " {\n" f" .uniqueID = {lang_id},\n" f" .translation_data = translation_data_brieflz_{lang_code},\n" f" .translation_size = sizeof(translation_data_brieflz_{lang_code}),\n" f" .translation_is_compressed = true,\n" " },\n" ) f.write("};\n") f.write( "const uint8_t LanguageCount = sizeof(LanguageMetas) / sizeof(LanguageMetas[0]);\n\n" f"alignas(TranslationData) uint8_t translation_data_out_buffer[{max_decompressed_translation_size}];\n" "const uint16_t translation_data_out_buffer_size = sizeof(translation_data_out_buffer);\n\n" ) sanity_checks_text = get_translation_sanity_checks_text(defs) f.write(sanity_checks_text) def get_translation_common_text( small_symbol_conversion_table: Dict[str, bytes], large_symbol_conversion_table: Dict[str, bytes], ) -> str: translation_common_text = "" # Write out firmware constant options constants = get_constants() for x in constants: if x[0].startswith("Small"): translation_common_text += f'const char* {x[0]} = "{convert_string(small_symbol_conversion_table, x[1])}";//{x[1]} \n' elif x[0].startswith("Large"): str = x[1] translation_common_text += f'const char* {x[0]} = "{convert_string(large_symbol_conversion_table, str)}";//{x[1]} \n' else: raise ValueError(f"Constant {x} is not size encoded") translation_common_text += "\n" # Debug Menu translation_common_text += "const char* DebugMenu[] = {\n" for c in get_debug_menu(): translation_common_text += ( f'\t "{convert_string(small_symbol_conversion_table, c)}",//"{c}" \n' ) translation_common_text += "};\n\n" # accel names translation_common_text += "const char* AccelTypeNames[] = {\n" for c in get_accel_names_list(): translation_common_text += ( f'\t "{convert_string(small_symbol_conversion_table, c)}",//{c} \n' ) translation_common_text += "};\n\n" # power source types translation_common_text += "const char* PowerSourceNames[] = {\n" for c in get_power_source_list(): translation_common_text += ( f'\t "{convert_string(small_symbol_conversion_table, c)}",//{c} \n' ) translation_common_text += "};\n\n" return translation_common_text @dataclass class TranslationItem: info: str str_index: int def get_translation_strings_and_indices_text( lang: dict, defs: dict, small_font_symbol_conversion_table: Dict[str, bytes], large_font_symbol_conversion_table: Dict[str, bytes], suffix: str = "", ) -> str: # For all strings; we want to convert them to their byte encoded form (using font index lookups) # Then we want to sort by their reversed format to see if we can remove any duplicates by combining the tails (last n bytes;n>0) # Finally we look for any that are contained inside one another, and if they are we update them to point to this # _OR_ we can be lazy and abuse cpu power and just make python search for our substring each time we append byte_encoded_strings: List[bytes] = [] # List of byte arrays of encoded strings byte_encoded_strings_unencoded_reference: List[str] = [] @dataclass class TranslatedStringLocation: byte_encoded_translation_index: int = 0 str_start_offset: int = 0 translated_string_lookups: Dict[str, TranslatedStringLocation] = {} # We do the collapse on the encoded strings; since we are doing different fonts, this avoids needing to track fonts # Also means if things line up nicely for us; we can do it across fonts (rare) def add_encoded_string( unencoded_string: str, encoded_string: bytes, translation_id: str ): for i, byte_data in enumerate(byte_encoded_strings): if byte_data.endswith(encoded_string): logging.info(f"Collapsing {translation_id}") record = TranslatedStringLocation( i, len(byte_data) - len(encoded_string) ) translated_string_lookups[translation_id] = record return byte_encoded_strings.append(encoded_string) byte_encoded_strings_unencoded_reference.append(unencoded_string) record = TranslatedStringLocation(len(byte_encoded_strings) - 1, 0) translated_string_lookups[translation_id] = record def encode_string_and_add( message: str, translation_id: str, force_large_text: bool = False ): encoded_data: bytes if force_large_text is False and test_is_small_font(message): encoded_data = convert_string_bytes( small_font_symbol_conversion_table, message ) else: if force_large_text is False: message = "\n" + message encoded_data = convert_string_bytes( large_font_symbol_conversion_table, message ) add_encoded_string(message, encoded_data, translation_id) for index, record in enumerate(defs["menuOptions"]): lang_data = lang["menuOptions"][record["id"]] # Add to translations the menu text and the description encode_string_and_add( lang_data["description"], "menuOptions" + record["id"] + "description", True ) encode_string_and_add( lang_data["displayText"], "menuOptions" + record["id"] + "displayText" ) for index, record in enumerate(defs["menuValues"]): lang_data = lang["menuValues"][record["id"]] # Add to translations the menu text and the description encode_string_and_add( lang_data["displayText"], "menuValues" + record["id"] + "displayText" ) for index, record in enumerate(defs["menuGroups"]): lang_data = lang["menuGroups"][record["id"]] # Add to translations the menu text and the description encode_string_and_add( lang_data["description"], "menuGroups" + record["id"] + "description", True ) encode_string_and_add( lang_data["displayText"], "menuGroups" + record["id"] + "displayText" ) for index, record in enumerate(defs["messagesWarn"]): lang_data = lang["messagesWarn"][record["id"]] # Add to translations the menu text and the description encode_string_and_add( lang_data["message"], "messagesWarn" + record["id"] + "Message" ) for index, record in enumerate(defs["characters"]): lang_data = lang["characters"][record["id"]] # Add to translations the menu text and the description encode_string_and_add(lang_data, "characters" + record["id"] + "Message", True) # ----- Write the string table: offset = 0 # NOTE: Cannot specify C99 designator here due to GCC (g++) bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55227 translation_strings_text = " /* .strings = */ {\n" for i, encoded_bytes in enumerate(byte_encoded_strings): if i > 0: translation_strings_text += ' "\\0"\n' # Write a comment of what it is translation_strings_text += f" // {offset: >4}: {escape(byte_encoded_strings_unencoded_reference[i])}\n" # Write the actual data translation_strings_text += f' "{bytes_to_escaped(encoded_bytes)}"' offset += len(encoded_bytes) + 1 translation_strings_text += "\n }, // .strings\n\n" str_total_bytes = offset ################# Part 2: Emit all the string offsets string_index_commulative_lengths = [] position = 0 for string in byte_encoded_strings: string_index_commulative_lengths.append(position) position += len(string) + 1 translation_indices_text = " .indices = {\n" # Write out the constant strings (ones we reference directly) for _, record in enumerate(defs["messagesWarn"]): # Add to translations the menu text and the description lang_data = lang["messagesWarn"][record["id"]] key = "messagesWarn" + record["id"] + "Message" translated_index = translated_string_lookups[key] string_index = translated_index.byte_encoded_translation_index start_index = ( string_index_commulative_lengths[string_index] + translated_index.str_start_offset ) translation_indices_text += ( f" .{record['id']} = {start_index}, // {escape(lang_data['message'])}\n" ) translation_indices_text += "\n" # Constant short values we use in settings menu for _, record in enumerate(defs["characters"]): # Add to translations the menu text and the description lang_data = lang["characters"][record["id"]] key = "characters" + record["id"] + "Message" translated_index = translated_string_lookups[key] string_index = translated_index.byte_encoded_translation_index start_index = ( string_index_commulative_lengths[string_index] + translated_index.str_start_offset ) translation_indices_text += ( f" .{record['id']} = {start_index}, // {escape(lang_data)}\n" ) for _, record in enumerate(defs["menuValues"]): # Add to translations the menu text and the description lang_data = lang["menuValues"][record["id"]] key = "menuValues" + record["id"] + "displayText" translated_index = translated_string_lookups[key] string_index = translated_index.byte_encoded_translation_index start_index = ( string_index_commulative_lengths[string_index] + translated_index.str_start_offset ) translation_indices_text += ( f" .{record['id']} = {start_index}, // {escape(lang_data)}\n" ) translation_indices_text += "\n" # Now for the fun ones, where they are nested and ordered def write_grouped_indexes(output_text: str, name: str, mainKey: str, subKey: str): max_len = 30 output_text += f" .{name} = {{\n" for index, record in enumerate(defs[mainKey]): lang_data = lang[mainKey][record["id"]] key = mainKey + record["id"] + subKey raw_string = lang_data[subKey] translated_index = translated_string_lookups[key] string_index = translated_index.byte_encoded_translation_index start_index = ( string_index_commulative_lengths[string_index] + translated_index.str_start_offset ) output_text += f" /* {record['id'].ljust(max_len)[:max_len]} */ {start_index}, // {escape(raw_string)}\n" output_text += f" }}, // {name}\n\n" return output_text translation_indices_text = write_grouped_indexes( translation_indices_text, "SettingsDescriptions", "menuOptions", "description" ) translation_indices_text = write_grouped_indexes( translation_indices_text, "SettingsShortNames", "menuOptions", "displayText" ) translation_indices_text = write_grouped_indexes( translation_indices_text, "SettingsMenuEntriesDescriptions", "menuGroups", "description", ) translation_indices_text = write_grouped_indexes( translation_indices_text, "SettingsMenuEntries", "menuGroups", "displayText" ) translation_indices_text += " }, // .indices\n\n" return ( "struct {\n" " TranslationIndexTable indices;\n" f" char strings[{str_total_bytes}];\n" f"}} const translation{suffix} = {{\n" + translation_indices_text + translation_strings_text + f"}}; // translation{suffix}\n\n" ) def get_translation_sanity_checks_text(defs: dict) -> str: sanity_checks_text = "\n// Verify SettingsItemIndex values:\n" for i, mod in enumerate(defs["menuOptions"]): eid = mod["id"] sanity_checks_text += ( f"static_assert(static_cast(SettingsItemIndex::{eid}) == {i});\n" ) sanity_checks_text += f"static_assert(static_cast(SettingsItemIndex::NUM_ITEMS) == {len(defs['menuOptions'])});\n" return sanity_checks_text def get_version_suffix(ver) -> str: # Check env var from push.yml first: # - if it's pull request then use vX.YY + C.ID for version line as in *C*I with proper tag instead of merge tag for detached tree if os.environ.get("GITHUB_CI_PR_SHA", "") != "": return "C" + "." + os.environ["GITHUB_CI_PR_SHA"][:8].upper() # - no github PR SHA ID, hence keep checking suffix = str("") try: # Use commands _hoping_ they won't be too new for one environments nor deprecated for another ones: ## - get commit id; --short=8 - the shorted hash with 8 digits (increase/decrease if needed!) sha_id = f"{subprocess.check_output(['git', 'rev-parse', '--short=8', 'HEAD']).strip().decode('ascii').upper()}" ## - if the exact commit relates to tag, then this command should return one-line tag name: tag = f"{subprocess.check_output(['git', 'tag', '--points-at', '%s' % sha_id]).strip().decode('ascii')}" if ( f"{subprocess.check_output(['git', 'rev-parse', '--symbolic-full-name', '--short', 'HEAD']).strip().decode('ascii')}" == "HEAD" ): return "E" + "." + sha_id else: ## - get short "traditional" branch name (as in `git branch` for that one with asterisk): branch = f"{subprocess.check_output(['git', 'symbolic-ref', '--short', 'HEAD']).strip().decode('ascii')}" if tag and "" != tag: # _Speculate_ on tag that it's Release... if ver == tag: # ... but only if double-check for tag is matched suffix = "R" else: # ... otherwise it's tagged but not a release version! suffix = "T" elif branch and "" != branch: # _Hardcoded_ current main development branch... if "dev" == branch: suffix = "D" # ... or some other branch else: suffix = "B" else: # Something else but from Git suffix = "G" # Attach SHA commit to ID a build since it's from git anyway suffix += "." + sha_id except subprocess.CalledProcessError: # No git tree so _probably_ Homebrew build from source suffix = "H" except OSError: # Something _special_? suffix = "S" if "" == suffix: # Something _very_ special! suffix = "V" return suffix def read_version() -> str: with open(HERE.parent / "source" / "version.h") as version_file: for line in version_file: if re.findall(r"^.*(?<=(#define)).*(?<=(BUILD_VERSION))", line): matches = re.findall(r"\"(.+?)\"", line) if matches: version = matches[0] version += get_version_suffix(version) return version def parse_args() -> argparse.Namespace: parser = argparse.ArgumentParser() parser.add_argument( "--output-pickled", help="Write pickled language data for later reuse", type=argparse.FileType("wb"), required=False, dest="output_pickled", ) parser.add_argument( "--input-pickled", help="Use previously generated pickled language data", type=argparse.FileType("rb"), required=False, dest="input_pickled", ) parser.add_argument( "--strings-obj", help="Use generated TranslationData by extracting from object file", type=argparse.FileType("rb"), required=False, dest="strings_obj", ) parser.add_argument( "--compress-font", help="Compress the font table", action="store_true", required=False, dest="compress_font", ) parser.add_argument( "--macros", help="Extracted macros to filter translation strings by", type=argparse.FileType("r"), required=True, dest="macros", ) parser.add_argument( "--output", "-o", help="Target file", type=argparse.FileType("w"), required=True ) parser.add_argument( "languageCodes", metavar="languageCode", nargs="+", help="Language(s) to generate", ) return parser.parse_args() def main() -> None: json_dir = HERE args = parse_args() if args.input_pickled and args.output_pickled: logging.error("error: Both --output-pickled and --input-pickled are specified") sys.exit(1) macros = ( frozenset(re.findall(r"#define ([^ ]+)", args.macros.read())) if args.macros else frozenset() ) language_data: LanguageData if args.input_pickled: logging.info(f"Reading pickled language data from {args.input_pickled.name}...") language_data = pickle.load(args.input_pickled) language_codes = [lang["languageCode"] for lang in language_data.langs] if language_codes != args.languageCodes: logging.error( f"error: languageCode {args.languageCode} does not match language data {language_codes}" ) sys.exit(1) logging.info(f"Read language data for {language_codes}") logging.info(f"Build version: {language_data.build_version}") else: try: build_version = read_version() except FileNotFoundError: logging.error("error: Could not find version info ") sys.exit(1) logging.info(f"Build version: {build_version}") logging.info(f"Making {args.languageCodes} from {json_dir}") defs_ = load_json(os.path.join(json_dir, "translations_definitions.json")) if len(args.languageCodes) == 1: lang_ = filter_translation( read_translation(json_dir, args.languageCodes[0]), defs_, macros ) language_data = prepare_language(lang_, defs_, build_version) else: langs_ = [ filter_translation(read_translation(json_dir, lang_code), defs_, macros) for lang_code in args.languageCodes ] language_data = prepare_languages(langs_, defs_, build_version) out_ = args.output write_start(out_) if len(language_data.langs) == 1: if args.strings_obj: sym_name = objcopy.cpp_var_to_section_name("translation") strings_bin = objcopy.get_binary_from_obj(args.strings_obj.name, sym_name) if len(strings_bin) == 0: raise ValueError(f"Output for {sym_name} is empty") write_language( language_data, out_, strings_bin=strings_bin, compress_font=args.compress_font, ) else: write_language(language_data, out_, compress_font=args.compress_font) else: if args.strings_obj: write_languages( language_data, out_, strings_obj_path=args.strings_obj.name, compress_font=args.compress_font, ) else: write_languages(language_data, out_, compress_font=args.compress_font) if args.output_pickled: logging.info(f"Writing pickled data to {args.output_pickled.name}") pickle.dump(language_data, args.output_pickled) logging.info("Done") if __name__ == "__main__": main() ================================================ FILE: Translations/make_translation_test.py ================================================ #!/usr/bin/env python3 import json import os import unittest class TestMakeTranslation(unittest.TestCase): def test_get_bytes_from_font_index(self): from make_translation import get_bytes_from_font_index self.assertEqual(get_bytes_from_font_index(2), b"\x02") self.assertEqual(get_bytes_from_font_index(239), b"\xEF") self.assertEqual(get_bytes_from_font_index(240), b"\xF0") self.assertEqual(get_bytes_from_font_index(241), b"\xF1\x01") self.assertEqual(get_bytes_from_font_index(495), b"\xF1\xFF") self.assertEqual(get_bytes_from_font_index(496), b"\xF2\x01") self.assertEqual(get_bytes_from_font_index(750), b"\xF2\xFF") self.assertEqual(get_bytes_from_font_index(751), b"\xF3\x01") self.assertEqual(get_bytes_from_font_index(0x10 * 0xFF - 15), b"\xFF\xFF") with self.assertRaises(ValueError): get_bytes_from_font_index(0x10 * 0xFF - 14) def test_bytes_to_escaped(self): from make_translation import bytes_to_escaped self.assertEqual(bytes_to_escaped(b"\x00"), "\\x00") self.assertEqual(bytes_to_escaped(b"\xF1\xAB"), "\\xF1\\xAB") def test_bytes_to_c_hex(self): from make_translation import bytes_to_c_hex self.assertEqual(bytes_to_c_hex(b"\x00"), "0x00,") self.assertEqual(bytes_to_c_hex(b"\xF1\xAB"), "0xF1, 0xAB,") def test_no_language_id_collisions(self): """ Asserting that we have no language collisions and that the has works ok """ from make_translation import get_language_unqiue_id seen_ids = [] for filename in os.listdir("."): if filename.endswith(".json") and filename.startswith("translation_"): with open(filename) as f: data = json.loads(f.read()) lang_code = data.get("languageCode") self.assertNotEqual(lang_code, None) id = get_language_unqiue_id(lang_code) self.assertFalse(id in seen_ids) seen_ids.append(id) if __name__ == "__main__": unittest.main() ================================================ FILE: Translations/migrate.py ================================================ #!/usr/bin/env python3 import json import os import sys # Migrate json files to use "\n" encoding rather than [] def load_json(filename: str) -> dict: with open(filename, "r", encoding="utf8") as f: return json.loads(f.read()) def save_json(filename: str, data: dict): with open(filename, "w", encoding="utf8") as f: json.dump(data, f, indent=4, ensure_ascii=False) file_name = sys.argv[1] print(file_name) data = load_json(file_name) # Migrate messages to be delimited for key in data["messagesWarn"]: old_message = data["messagesWarn"][key] if isinstance(old_message, list): print(old_message) new_message = "\n".join(old_message) data["messagesWarn"][key] = {"message": new_message} else: data["messagesWarn"][key] = {"message": old_message} for key in data["messages"]: old_message = data["messages"][key] if isinstance(old_message, list): print(old_message) new_message = "\n".join(old_message) data["messagesWarn"][key] = {"message": new_message} else: data["messagesWarn"][key] = {"message": old_message} del data["messages"] print("Part 2") # for menu-groups break out the text2 field for key in data["menuGroups"]: old_data = data["menuGroups"][key] if isinstance(old_data.get("text2", ""), list): new_data = "\n".join(old_data["text2"]) data["menuGroups"][key]["displayText"] = new_data del data["menuGroups"][key]["text2"] else: data["menuGroups"][key]["displayText"] = old_data["text2"].replace("\n", "") del data["menuGroups"][key]["text2"] data["menuGroups"][key]["description"] = data["menuGroups"][key]["desc"] del data["menuGroups"][key]["desc"] print("Part 3") # for menu-groups break out the text2 field for key in data["menuOptions"]: old_data = data["menuOptions"][key] if isinstance(old_data.get("text2", ""), list): new_data = "\n".join(old_data["text2"]) data["menuOptions"][key]["displayText"] = new_data del data["menuOptions"][key]["text2"] else: data["menuOptions"][key]["displayText"] = old_data["text2"].replace("\n", "") del data["menuOptions"][key]["text2"] data["menuOptions"][key]["description"] = data["menuOptions"][key]["desc"] del data["menuOptions"][key]["desc"] save_json(file_name, data) ================================================ FILE: Translations/objcopy.py ================================================ import os import subprocess import tempfile if "OBJCOPY" in os.environ: OBJCOPY = os.environ["OBJCOPY"] else: OBJCOPY = "objcopy" def get_binary_from_obj(objfile_path: str, section_name: str) -> bytes: tmpfd, tmpfile = tempfile.mkstemp() result = subprocess.run( [OBJCOPY, "-O", "binary", "-j", section_name, objfile_path, tmpfile] ) result.check_returncode() with open(tmpfd, "rb") as f: bin: bytes = f.read() os.remove(tmpfile) return bin def cpp_var_to_section_name(var_name: str) -> str: return f".rodata._ZL{len(var_name)}{var_name}" ================================================ FILE: Translations/translation_BE.json ================================================ { "languageCode": "BE", "languageLocalName": "Беларуская", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Каліброўка\nзроблена!" }, "ResetOKMessage": { "message": "Скід OK" }, "SettingsResetMessage": { "message": "Налады\nскінуты!" }, "NoAccelerometerMessage": { "message": "Акселерометр\nне выяўлены!" }, "NoPowerDeliveryMessage": { "message": "USB-PD\nне выяўлены!" }, "LockingKeysString": { "message": "ЗАБЛАК." }, "UnlockingKeysString": { "message": "АДБЛАК." }, "WarningKeysLockedString": { "message": "!ЗАБЛАК.!" }, "WarningThermalRunaway": { "message": "Некантралюемае\nразаграванне" }, "WarningTipShorted": { "message": "!Кароткае замыканне на джале!" }, "SettingsCalibrationWarning": { "message": "Пераканайцеся, што пры наступнай загрузцы наканечнік і ручка маюць пакаёвую тэмпературу!" }, "CJCCalibrating": { "message": "каліброўка\n" }, "SettingsResetWarning": { "message": "Вы ўпэннены, што жадаеце скінуць налады да першапачатковых значэнняў?" }, "UVLOWarningString": { "message": "НІЗК. НАПР." }, "UndervoltageString": { "message": "Нізк. напр.\n" }, "InputVoltageString": { "message": "Увах. напр.: \n" }, "SleepingAdvancedString": { "message": "Чаканне...\n" }, "SleepingTipAdvancedString": { "message": "Джала: \n" }, "ProfilePreheatString": { "message": "Разагрэць\n" }, "ProfileCooldownString": { "message": "Астудзіць\n" }, "DeviceFailedValidationWarning": { "message": "Ваша прылада, хутчэй за ўсё, падробка!" }, "TooHotToStartProfileWarning": { "message": "Занадта горача,\nкаб запусціць профіль" } }, "characters": { "SettingRightChar": "П", "SettingLeftChar": "Л", "SettingAutoChar": "А", "SettingSlowChar": "М", "SettingMediumChar": "С", "SettingFastChar": "Х", "SettingStartSolderingChar": "П", "SettingStartSleepChar": "Ч", "SettingStartSleepOffChar": "Х", "SettingLockBoostChar": "Т", "SettingLockFullChar": "П" }, "menuGroups": { "PowerMenu": { "displayText": "Налады\nсілкавання", "description": "" }, "SolderingMenu": { "displayText": "Налады\nпайкі", "description": "" }, "PowerSavingMenu": { "displayText": "Рэжым\nчакання", "description": "" }, "UIMenu": { "displayText": "Налады\nінтэрфейсу", "description": "" }, "AdvancedMenu": { "displayText": "Дадатковыя\nналады", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Звыч.\nрэжым" }, "USBPDModeNoDynamic": { "displayText": "Без\nдынамікі" }, "USBPDModeSafe": { "displayText": "Бяспечны\nрэжым" }, "TipTypeAuto": { "displayText": "Аўта\n" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Крыніца\nсілкавання", "description": "Вызначыць напруджанне адсечкі для прадухілення глыбокай разрадкі (DC=10В) (S=3,3В на ячэйку, без абмежавання магутнасці)" }, "MinVolCell": { "displayText": "Мін.\nнапр.", "description": "Мінімальнае дазволеннае напруджанне на ячэйку (3S: 3 - 3,7В | 4S: 2,4 - 3,7В)" }, "QCMaxVoltage": { "displayText": "Напрудж.\nQC", "description": "Максімальнае напруджанне, узгадняемае па пратаколу QC" }, "PDNegTimeout": { "displayText": "Затрымка\nPD", "description": "Затрымка з крокам 100 мс перад ўзгадненем PD для сумяшчальнасці з некаторымі зараднымі прыладамі QC" }, "USBPDMode": { "displayText": "Рэжым\nPD", "description": "«Без дынамікі» адключае EPR і PPS, «Бяспечны рэжым» не выкарыстоўвае карэкціровачнае супраціўленне" }, "BoostTemperature": { "displayText": "T° турба\nрэжыму", "description": "Тэмпература джала ў турба-рэжыме" }, "AutoStart": { "displayText": "Стартавы\nрэжым", "description": "П=нагрэў да тэмп. пайкі | Ч=чаканне | Х=чаканне без нагрэву" }, "TempChangeShortStep": { "displayText": "Крок T°\nкароткі", "description": "Крок вымярэння тэмпературы пры кароткім націсканні кнопак" }, "TempChangeLongStep": { "displayText": "Крок T°\nдоўгі", "description": "Крок вымярэння тэмпературы пры доўгім націсканні кнопак" }, "LockingMode": { "displayText": "Дазволіць\nблок кнопак", "description": "Падчас пайкі падоўжаны націск дзьвюх кнопак блакуе іх (Т=Толькі турба | П=Поўная блакіроўка)" }, "ProfilePhases": { "displayText": "Фазы\nпрофілю", "description": "Колькасць фаз у профільным рэжыме" }, "ProfilePreheatTemp": { "displayText": "T°\nразагр.", "description": "Разаграваць да гэтай тэмпературы ў пачатку профільнага рэжыму" }, "ProfilePreheatSpeed": { "displayText": "Хуткасть\nразагр.", "description": "Разаграваць з гэтай хуткасцю (градусы на секунду)" }, "ProfilePhase1Temp": { "displayText": "Фаза 1\nтэмпература", "description": "Мэтавая тэмпература ў канцы гэтай фазы" }, "ProfilePhase1Duration": { "displayText": "Фаза 1\nпрацягласць", "description": "Мэтавая працягласць гэтай фазы (секунды)" }, "ProfilePhase2Temp": { "displayText": "Фаза 2\nтэмпература", "description": "Мэтавая тэмпература ў канцы гэтай фазы" }, "ProfilePhase2Duration": { "displayText": "Фаза 2\nпрацягласць", "description": "Мэтавая працягласць гэтай фазы (секунды)" }, "ProfilePhase3Temp": { "displayText": "Фаза 3\nтэмпература", "description": "Мэтавая тэмпература ў канцы гэтай фазы" }, "ProfilePhase3Duration": { "displayText": "Фаза 3\nпрацягласць", "description": "Мэтавая працягласць гэтай фазы (секунды)" }, "ProfilePhase4Temp": { "displayText": "Фаза 4\nтэмпература", "description": "Мэтавая тэмпература ў канцы гэтай фазы" }, "ProfilePhase4Duration": { "displayText": "Фаза 4\nпрацягласць", "description": "Мэтавая працягласць гэтай фазы (секунды)" }, "ProfilePhase5Temp": { "displayText": "Фаза 5\nтэмпература", "description": "Мэтавая тэмпература ў канцы гэтай фазы" }, "ProfilePhase5Duration": { "displayText": "Фаза 5\nпрацягласць", "description": "Мэтавая працягласць гэтай фазы (секунды)" }, "ProfileCooldownSpeed": { "displayText": "Хуткасць\nастывання", "description": "Астуджаць з гэтай хуткасцю ў канцы профільнага рэжыму (градусы на секунду)" }, "MotionSensitivity": { "displayText": "Адчувальн.\nакселерометра", "description": "Адчувальнасць акселерометра (1=Мін. | ... | 9=Макс.)" }, "SleepTemperature": { "displayText": "T°\nчакання", "description": "Тэмпература рэжыму чакання" }, "SleepTimeout": { "displayText": "Таймаўт\nчакання", "description": "Час да пераходу ў рэжым чакання (у секундах або хвілінах)" }, "ShutdownTimeout": { "displayText": "Таймаут\nадкл.", "description": "Час да адключэння паяльніка (у хвілінах)" }, "HallEffSensitivity": { "displayText": "Датчык Хола\nадчувальнасць", "description": "Адчувальнасць датчыка Хола да магнітаў (1=Мін. | ... | 9=Макс.)" }, "HallEffSleepTimeout": { "displayText": "Датчык Хола\nчас чакання", "description": "Час перад рэжымам чакання, калі эфект Хола перавышае парог" }, "TemperatureUnit": { "displayText": "Адзінкі\nтэмпературы", "description": "Адзінкі вымярэння тэмпературы" }, "DisplayRotation": { "displayText": "Арыентацыя\nэкрана", "description": "П=Правая рука | Л=Левая рука | А=Аўта" }, "CooldownBlink": { "displayText": "Мігценне T°\nпры астудж.", "description": "Мігцець паказаннямі тэмпературы, пакуль джала яшчэ гарачае" }, "ScrollingSpeed": { "displayText": "Хуткацсь\nтексту", "description": "Хуткасць гартання тэксту (М=марудна | Х=хутка)" }, "ReverseButtonTempChange": { "displayText": "Памяняць\n+ і -", "description": "Памяняць месцамі кнопкі вызначэння тэмпературы" }, "ReverseButtonSettings": { "displayText": "Памяняць\nA і B", "description": "Памяняць месцамі кнопкі навігацыі ў наладах" }, "AnimSpeed": { "displayText": "Хуткасць\nанімацыі", "description": "Хуткасць анімацыі значкоў у галоўным меню (Н=Нізкая | С=Сярэдняя | В=Высокая)" }, "AnimLoop": { "displayText": "Зацыкліць\nанімацыю", "description": "Зацыкліць анімацыю значкоў у галоўным меню" }, "Brightness": { "displayText": "Экран\nЯркасць", "description": "Рэгуляцыя яркасці OLED-экрана" }, "ColourInversion": { "displayText": "Экран\nІнверсія", "description": "Інверсія колераў OLED-экрана" }, "LOGOTime": { "displayText": "Працягл.\nлагатыпа", "description": "Усталяваць працягласць лагатыпа загрузкі (у секундах)" }, "AdvancedIdle": { "displayText": "Падрабязны\nрэжым чакання", "description": "Адлюстроўваць дэталёвую інфармацыю паменьшаным шрыфтом на экране чакання" }, "AdvancedSoldering": { "displayText": "Падрабязны\nэкран пайкі", "description": "Паказваць дэталёвую інформацыю паменьшаным шрыфтом на экране пайкі" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Уключыць BLE" }, "PowerLimit": { "displayText": "Межы\nмагутн.", "description": "Сярэдняя максімальная магутнасць, якую можа выкарыстоўваць паяльнік (у ватах)" }, "CalibrateCJC": { "displayText": "Калібр. CJC\nпры наст. укл.", "description": "Каліброўка тэмпературы (Cold Junction Compensation) пры наступным уключэнні (не патрабуецца, калі розніца тэмператур меньш за 5°C)" }, "VoltageCalibration": { "displayText": "Калібр. увах.\nнапруджання", "description": "Каліброўка ўваходнага напруджання (доўгае націсканне для выхаду)" }, "PowerPulsePower": { "displayText": "Імп. сілк.\nМоц", "description": "Моц імпульса, які ўтрымлівае ад сну крыніцу сілкавання (у ватах)" }, "PowerPulseWait": { "displayText": "Імп. сілк.\nЗатрымка", "description": "Затрымка перад падачай імпульсу, які ўтрымлівае крыніцу сілкавання ад сну (x 2.5с)" }, "PowerPulseDuration": { "displayText": "Імп. сілк.\nПрацягласць", "description": "Працягласць імпульсу, які ўтрымлівае крыніцу сілкавання ад сну (x 250мс)" }, "SettingsReset": { "displayText": "Скід\nналад", "description": "Скід налад да першапачатковых значэнняў" }, "LanguageSwitch": { "displayText": "Мова:\n BE Беларуская", "description": "" }, "SolderingTipType": { "displayText": "Тып\nджала", "description": "Абярыце тып усталяванага джала" } } } ================================================ FILE: Translations/translation_BG.json ================================================ { "languageCode": "BG", "languageLocalName": "Български", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Калибрирането\nе завършено!" }, "ResetOKMessage": { "message": "Нулиране" }, "SettingsResetMessage": { "message": "Настройките бяха\nнулирани!" }, "NoAccelerometerMessage": { "message": "Не е открит\nакселерометър!" }, "NoPowerDeliveryMessage": { "message": "Не е открито\nUSB-PD захранване!" }, "LockingKeysString": { "message": "ЗАКЛЮЧ" }, "UnlockingKeysString": { "message": "ОТКЛЮЧ" }, "WarningKeysLockedString": { "message": "!ЗАКЛЮЧ!" }, "WarningThermalRunaway": { "message": "Неконтролируемо\nпрегряване" }, "WarningTipShorted": { "message": "!КС на човка!" }, "SettingsCalibrationWarning": { "message": "Преди рестартиране се уверете, че човка и дръжката са на стайна температурата!" }, "CJCCalibrating": { "message": "калибриране\n" }, "SettingsResetWarning": { "message": "Сигурни ли сте, че искате да върнете фабричните настройки?" }, "UVLOWarningString": { "message": "НИС.НАПР." }, "UndervoltageString": { "message": "Ниско напрежение\n" }, "InputVoltageString": { "message": "Входно V: \n" }, "SleepingAdvancedString": { "message": "Сън...\n" }, "SleepingTipAdvancedString": { "message": "Човка:\n" }, "ProfilePreheatString": { "message": "Загряване\n" }, "ProfileCooldownString": { "message": "Охлаждане\n" }, "DeviceFailedValidationWarning": { "message": "Вероятно, устройство е фалшификат!" }, "TooHotToStartProfileWarning": { "message": "Твърде горещо за\nстартиране на профила" } }, "characters": { "SettingRightChar": "Д", "SettingLeftChar": "Л", "SettingAutoChar": "А", "SettingSlowChar": "Н", "SettingMediumChar": "С", "SettingFastChar": "В", "SettingStartSolderingChar": "З", "SettingStartSleepChar": "С", "SettingStartSleepOffChar": "П", "SettingLockBoostChar": "Т", "SettingLockFullChar": "П" }, "menuGroups": { "PowerMenu": { "displayText": "Настройки на\nзахранването", "description": "" }, "SolderingMenu": { "displayText": "Настройки на\nзапояване", "description": "" }, "PowerSavingMenu": { "displayText": "Авто\nизключване", "description": "" }, "UIMenu": { "displayText": "Интерфейс\n", "description": "" }, "AdvancedMenu": { "displayText": "Допълнителни\nнастройки", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Вкл.\nPPSиERP" }, "USBPDModeNoDynamic": { "displayText": "Изкл.\n" }, "USBPDModeSafe": { "displayText": "Вкл.без\nискане" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Гранично\nнапрежение", "description": "Минимално напрежение, за да не се изтощи батерията (DC 10V) (S 3,3V за клетка)" }, "MinVolCell": { "displayText": "Мин.\nнапрежение", "description": "Минимално допустимо напрежение на акумулаторна клетка (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "Напреж.\nна QC", "description": "Максимална напрежение с QC захранвания" }, "PDNegTimeout": { "displayText": "PD\nинтервал", "description": "PD интервал за договаряне на захранването на стъпки от 100 мс за съвместимост с някои QC захранвания (0=Изкл.)" }, "USBPDMode": { "displayText": "PD\nрежим", "description": "Вкл.без искане: включи PPS и EPR без да искате повече мощност" }, "BoostTemperature": { "displayText": "Турбо\nтемп.", "description": "Температурата за \"турбо\" режим" }, "AutoStart": { "displayText": "Автоматичен\nработен режим", "description": "Режим на поялника при включване на захранването (З=Запояване | С=Сън | П=Покой на стайна температурата)" }, "TempChangeShortStep": { "displayText": "Промяна T\nбързо", "description": "Промяна на температурата при бързо натискане на бутон" }, "TempChangeLongStep": { "displayText": "Промяна Т\nзадържане", "description": "Промяна на температурата при задържане на бутон" }, "LockingMode": { "displayText": "Бутони за\nзаключване", "description": "Докато запоявате, задръжте двата бутона, за да превключите заключването им (Т=Турбо режим | П=Пълно)" }, "ProfilePhases": { "displayText": "Брой\nетапи", "description": "Броят на етапите в режим на термичен профил" }, "ProfilePreheatTemp": { "displayText": "Температурата\nна загряване", "description": "Температурата на загряване в началото на режим на термичен профил" }, "ProfilePreheatSpeed": { "displayText": "Скорост на\nзагряване", "description": "Скорост на предварително загряване (градуси в секунда)" }, "ProfilePhase1Temp": { "displayText": "Етап 1\nТемпературата", "description": "Температурата в края на този етап" }, "ProfilePhase1Duration": { "displayText": "Етап 1\nПродължителност", "description": "Продължителност на този етап (в секунди)" }, "ProfilePhase2Temp": { "displayText": "Етап 2\nТемпературата", "description": "" }, "ProfilePhase2Duration": { "displayText": "Етап 2\nПродължителност", "description": "" }, "ProfilePhase3Temp": { "displayText": "Етап 3\nТемпературата", "description": "" }, "ProfilePhase3Duration": { "displayText": "Етап 3\nПродължителност", "description": "" }, "ProfilePhase4Temp": { "displayText": "Етап 4\nТемпературата", "description": "" }, "ProfilePhase4Duration": { "displayText": "Етап 4\nПродължителност", "description": "" }, "ProfilePhase5Temp": { "displayText": "Етап 5\nТемпературата", "description": "" }, "ProfilePhase5Duration": { "displayText": "Етап 5\nПродължителност", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Скорост на\nохлаждане", "description": "Скорост на охлаждане в края на режим на термичен профил (градуси в секунда)" }, "MotionSensitivity": { "displayText": "Чувствител.\nна движение", "description": "Чувствителност на движение на акселерометър (1=Слабо | ... | 9=Силно)" }, "SleepTemperature": { "displayText": "Темп.\nсън", "description": "Температурата при режим \"сън\"" }, "SleepTimeout": { "displayText": "Време\nсън", "description": "Включване в режим \"сън\" (секунди | минути)" }, "ShutdownTimeout": { "displayText": "Време\nизкл.", "description": "Изключване след (минути)" }, "HallEffSensitivity": { "displayText": "Датчик\nна Хол", "description": "Чувствителност на сензора към магнитно поле (1=Слабо | ... | 9=Силно)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Интервалът преди началото на \"режим на заспиване\", когато ефектът на Хол надвиши прага" }, "TemperatureUnit": { "displayText": "Единици за\nтемпературата", "description": "Единици за температурата (C=Целзии | F=Фаренхайт)" }, "DisplayRotation": { "displayText": "Ориентация\nна дисплея", "description": "Ориентация на дисплея (Д=Дясна ръка | Л=Лява ръка | А=Авто)" }, "CooldownBlink": { "displayText": "Мигай при\nтопъл поялник", "description": "След изключване от работен режим, индикатора за температурата да мига докато човката на поялника все още е топла" }, "ScrollingSpeed": { "displayText": "Скорост\nна текста", "description": "Скорост на движение на този текст (Н=Ниска | B=Висока)" }, "ReverseButtonTempChange": { "displayText": "Размяна\nбутони +/-", "description": "Обръщане на бутоните + и - за промяна на температурата на човка на поялника" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Скорост на\nанимацията", "description": "Скорост на анимация на иконата в главното меню (Н=Ниска | C=Средна | B=Висока)" }, "AnimLoop": { "displayText": "Анимац.\nцикъл", "description": "Зациклена анимация на иконите в главното меню" }, "Brightness": { "displayText": "Яркост\nна екрана", "description": "Регулирайте яркостта на екрана" }, "ColourInversion": { "displayText": "Инвертиране\nна екрана", "description": "Инверсия на пикселите на екрана" }, "LOGOTime": { "displayText": "Продължит.\nлогото", "description": "Продължителност на логото за стартиране (в секунди)" }, "AdvancedIdle": { "displayText": "Детайлен\nекран в покой", "description": "Покажи детайлна информация със ситен шрифт на екрана в режим на покой" }, "AdvancedSoldering": { "displayText": "Детайлен\nработен екран", "description": "Детайлна информация в работен режим при запояване" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Включи BLE" }, "PowerLimit": { "displayText": "Лимит на\nмощност", "description": "Максимална мощност на поялника (вати)" }, "CalibrateCJC": { "displayText": "Калибриране\nна темп.", "description": "Калибриране на температурата (CJC) при следващо включване (не се изисква, ако разликата е по-малка от 5 °С)" }, "VoltageCalibration": { "displayText": "Калибриране\nнапрежение", "description": "Калибриране на входното напрежение (задръжте бутонa за изход)" }, "PowerPulsePower": { "displayText": "Захранващ\nимпулс", "description": "Поддържане на интензивност на захранващия импулс (вати)" }, "PowerPulseWait": { "displayText": "Закъснение\nна импулса", "description": "Пауза между импулсите, които предпазват захранването от автоматично изключване (x 2,5 с)" }, "PowerPulseDuration": { "displayText": "Продължит.\nна импулса", "description": "Дължината на импулса, който предпазва захранването от автоматично изключване (x 250 мс)" }, "SettingsReset": { "displayText": "Фабрични\nнастройки", "description": "Връщане на фабрични настройки" }, "LanguageSwitch": { "displayText": "Език:\n BG Български", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_CS.json ================================================ { "languageCode": "CS", "languageLocalName": "Český", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrace\ndokončena!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Nějaká nastavení\nbyla změněna!" }, "NoAccelerometerMessage": { "message": "Akcelerometr\nnebyl detekován!" }, "NoPowerDeliveryMessage": { "message": "Žádný IO USB-PD\nnebyl detekován!" }, "LockingKeysString": { "message": "ZAMČENO" }, "UnlockingKeysString": { "message": "ODEMČENO" }, "WarningKeysLockedString": { "message": "ZAMČENO!" }, "WarningThermalRunaway": { "message": "Teplotní\nOchrana" }, "WarningTipShorted": { "message": "!Zkrat na hrotu!" }, "SettingsCalibrationWarning": { "message": "Před restartem se ujistěte, že hrot a držák mají pokojovou teplotu!" }, "CJCCalibrating": { "message": "kalibrování\n" }, "SettingsResetWarning": { "message": "Opravdu chcete resetovat zařízení do továrního nastavení?" }, "UVLOWarningString": { "message": "Nízké DC" }, "UndervoltageString": { "message": "Nízké napětí\n" }, "InputVoltageString": { "message": "Napětí: \n" }, "SleepingAdvancedString": { "message": "Režim spánku...\n" }, "SleepingTipAdvancedString": { "message": "Hrot: \n" }, "ProfilePreheatString": { "message": "Předehřívání\n" }, "ProfileCooldownString": { "message": "Zchlazování\n" }, "DeviceFailedValidationWarning": { "message": "Vaše zařízení je pravěpodobně padělek!" }, "TooHotToStartProfileWarning": { "message": "Teplota příliš vysoká pro start profilu" } }, "characters": { "SettingRightChar": "P", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "P", "SettingMediumChar": "S", "SettingFastChar": "R", "SettingStartSolderingChar": "P", "SettingStartSleepChar": "S", "SettingStartSleepOffChar": "M", "SettingLockBoostChar": "B", "SettingLockFullChar": "U" }, "menuGroups": { "PowerMenu": { "displayText": "Napájecí\nnastavení", "description": "" }, "SolderingMenu": { "displayText": "Pájecí\nnastavení", "description": "" }, "PowerSavingMenu": { "displayText": "Režim\nspánku", "description": "" }, "UIMenu": { "displayText": "Uživatelské\nrozhraní", "description": "" }, "AdvancedMenu": { "displayText": "Pokročilá\nnastavení", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Zdroj\nnapájení", "description": "Při nižším napětí ukončit pájení (DC 10V) (S 3,3V na článek, zakázat omezení napájení)." }, "MinVolCell": { "displayText": "Minimální\nnapětí", "description": "Minimální dovolené napětí po článku (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "Napětí\nQC", "description": "Maximální napětí QC pro jednání páječkou" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "Maximální prodleva při jednání PD ve 100ms krocích pro kompatibilitu s některými QC nabíječkami" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Povoluje režimy PPS & EPR" }, "BoostTemperature": { "displayText": "Teplota\nboostu", "description": "Teplota hrotu v \"režimu boost\"" }, "AutoStart": { "displayText": "Chování\npři startu", "description": "P=pájecí teplota | S=spánková teplota | M=zahřát hrot po pohybu" }, "TempChangeShortStep": { "displayText": "Krok teploty\nkrátký?", "description": "Velikost přídavku při změně teploty krátkým stiskem tlačítka" }, "TempChangeLongStep": { "displayText": "Krok teploty\ndlouhý?", "description": "Velikost přídavku při změně teploty dlouhým stiskem tlačítka" }, "LockingMode": { "displayText": "Povolit zamč.\ntlačítek", "description": "Při pájení podržte obě tlačítka pro jejich zamčení (B=pouze v režimu boost | U=úplné zamčení)" }, "ProfilePhases": { "displayText": "Profilové\nFáze", "description": "Počet fází v profilovém režimu" }, "ProfilePreheatTemp": { "displayText": "Teplota\nPředehřátí", "description": "Teplota na kterou předehřát na začátku profilového režimu" }, "ProfilePreheatSpeed": { "displayText": "Rychlost\nPředehřívání", "description": "Rychlost předehřívání (stupně za sekundu)" }, "ProfilePhase1Temp": { "displayText": "Teplota\nFáze 1", "description": "Cílová teplota na konci této fáze" }, "ProfilePhase1Duration": { "displayText": "Trvání\nFáze 1", "description": "Doba trvání této fáze (sekundy)" }, "ProfilePhase2Temp": { "displayText": "Teplota\nFáze 2", "description": "" }, "ProfilePhase2Duration": { "displayText": "Trvání\nFáze 2", "description": "" }, "ProfilePhase3Temp": { "displayText": "Teplota\nFáze 3", "description": "" }, "ProfilePhase3Duration": { "displayText": "Trvání\nFáze 3", "description": "" }, "ProfilePhase4Temp": { "displayText": "Teplota\nFáze 4", "description": "" }, "ProfilePhase4Duration": { "displayText": "Trvání\nFáze 4", "description": "" }, "ProfilePhase5Temp": { "displayText": "Teplota\nFáze 5", "description": "" }, "ProfilePhase5Duration": { "displayText": "Trvání\nFáze 5", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Rychlost\nochlazování", "description": "Rychlost ochlazování na konci profilového režimu (stupně za sekundu)" }, "MotionSensitivity": { "displayText": "Citlivost\nna pohyb", "description": "1=nejméně citlivé | ... | 9=nejvíce citlivé" }, "SleepTemperature": { "displayText": "Teplota\nve spánku", "description": "Teplota hrotu v režimu spánku." }, "SleepTimeout": { "displayText": "Čas\ndo spánku", "description": "\"Režim spánku\" naběhne v (s=sekundách | m=minutách)" }, "ShutdownTimeout": { "displayText": "Čas do\nvypnutí", "description": "Interval automatického vypnutí (m=minut)" }, "HallEffSensitivity": { "displayText": "Citlivost\nHall. čidla", "description": "Citlivost Hallova čidla pro detekci spánku (1=nejméně citlivé | ... | 9=nejvíce citlivé)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval před začátkem \"režimu spánku\", kdy Hallův efekt překročí práh" }, "TemperatureUnit": { "displayText": "Jednotka\nteploty", "description": "C=Celsius | F=Fahrenheit" }, "DisplayRotation": { "displayText": "Orientace\nobrazovky", "description": "P=pravák | L=levák | A=automaticky" }, "CooldownBlink": { "displayText": "Blikáni při\nchladnutí", "description": "Blikat teplotou při chladnutí dokud je hrot horký" }, "ScrollingSpeed": { "displayText": "Rychlost\nposouvání", "description": "Rychlost posouvání popisků podobných tomuto (P=pomalu | R=rychle)" }, "ReverseButtonTempChange": { "displayText": "Prohodit\ntl. +-?", "description": "Prohodit tlačítka pro změnu teploty" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nrychlost", "description": "Tempo animace ikon v menu (P=pomalu | S=středně | R=rychle)" }, "AnimLoop": { "displayText": "Anim.\nsmyčka", "description": "Animovat ikony hlavního menu ve smyčce" }, "Brightness": { "displayText": "Jas\nobrazovky", "description": "Upravit jas OLED" }, "ColourInversion": { "displayText": "Invertovat\nobrazovku", "description": "Invertovat barvy na OLED" }, "LOGOTime": { "displayText": "Trvání\nboot loga", "description": "Nastavení doby trvání boot loga (s=sekundy)" }, "AdvancedIdle": { "displayText": "Podrobná obr.\nnečinnosti", "description": "Zobrazit detailní informace malým fontem na obrazovce nečinnosti" }, "AdvancedSoldering": { "displayText": "Podrobná obr.\npájení", "description": "Zobrazit detailní informace malým fontem na obrazovce pájení" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Povoluje BLE" }, "PowerLimit": { "displayText": "Omezení\nVýkonu", "description": "Maximální příkon páječky (W=watt)" }, "CalibrateCJC": { "displayText": "Kalibrovat CJC\npři příštím startu", "description": "Při příštím startu bude kalibrována kompenzace studeného spoje (není třeba pokud Delta T je < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibrovat\nvstupní napětí?", "description": "Začít kalibraci vstupního napětí (dlouhý stisk pro ukončení)" }, "PowerPulsePower": { "displayText": "Napájecí\npulz", "description": "Intenzita výkonu pulzu pro udržení páječky vzhůru (watt)" }, "PowerPulseWait": { "displayText": "Prodleva\nnapáj. pulzu", "description": "Prodleva než je spuštěn pulz pro udržení páječky vzhůru pulzu pro udržení páječky vzhůru (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Délka\nnapáj. pulzu", "description": "Délka pulzu pro udržení páječky vzhůru (x 250ms)" }, "SettingsReset": { "displayText": "Obnovit tovární\nnastavení?", "description": "Obnovit všechna nastavení na výchozí" }, "LanguageSwitch": { "displayText": "Jazyk:\n CS Český", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_DA.json ================================================ { "languageCode": "DA", "languageLocalName": "Dansk", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrering\nFærdig!" }, "ResetOKMessage": { "message": "Nulstil OK" }, "SettingsResetMessage": { "message": "Visse indstillinger\nEr blevet ændret!" }, "NoAccelerometerMessage": { "message": "ingen accelerometer\nfundet!" }, "NoPowerDeliveryMessage": { "message": "ingen USB-PD IC\nFundet!" }, "LockingKeysString": { "message": "LÅST" }, "UnlockingKeysString": { "message": "ULÅST" }, "WarningKeysLockedString": { "message": "!LÅST!" }, "WarningThermalRunaway": { "message": "Termisk\nRunaway" }, "WarningTipShorted": { "message": "!Tip Kortsluttet!" }, "SettingsCalibrationWarning": { "message": "Før genstart, skal du sørge for, at tip & håndtag er ved stuetemperatur!" }, "CJCCalibrating": { "message": "kalibrering\n" }, "SettingsResetWarning": { "message": "Er du sikker du vil resette indstillingerne til standard?" }, "UVLOWarningString": { "message": "Lav Volt" }, "UndervoltageString": { "message": "Undervolt\n" }, "InputVoltageString": { "message": "Input V: \n" }, "SleepingAdvancedString": { "message": "Dvale...\n" }, "SleepingTipAdvancedString": { "message": "Tip: \n" }, "ProfilePreheatString": { "message": "Forvarmning\n" }, "ProfileCooldownString": { "message": "Nedkøling\n" }, "DeviceFailedValidationWarning": { "message": "Din enhed er højst sandsyneligt en Kopivare!" }, "TooHotToStartProfileWarning": { "message": "For varm til\nat starte profil" } }, "characters": { "SettingRightChar": "H", "SettingLeftChar": "V", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "F", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "D", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Strøm\nIndstillinger", "description": "" }, "SolderingMenu": { "displayText": "Lodde\nIndstillinger", "description": "" }, "PowerSavingMenu": { "displayText": "Dvale\nmode", "description": "" }, "UIMenu": { "displayText": "Bruger\nGrændseflade", "description": "" }, "AdvancedMenu": { "displayText": "Advancerede\nIndstillinger", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Standard\nMode" }, "USBPDModeNoDynamic": { "displayText": "Ingen\nDynamic" }, "USBPDModeSafe": { "displayText": "Sikker\nMode" }, "TipTypeAuto": { "displayText": "Auto\nOpdag" }, "TipTypeT12Long": { "displayText": "TS100\nLang" }, "TipTypeT12Short": { "displayText": "Pine\nKort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Strøm\nKilde", "description": "Strømforsyning. Indstil Cutoff Spændingen. (DC 10V) (S 3,3V per celle)" }, "MinVolCell": { "displayText": "Minimum\nSpænding", "description": "Minimum tilladt spænding pr. celle (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "QC\nSpænding", "description": "Max QC spænding Loddekolben skal forhandle sig til" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD-forhandlingstimeout i trin på 100 ms for kompatibilitet med nogle QC-opladere" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Ingen dynamisk deaktiverer EPR & PPS, sikker tilstand bruger ikke pad modstand" }, "BoostTemperature": { "displayText": "Boost\ntemp", "description": "Temperatur i \"boost mode\"" }, "AutoStart": { "displayText": "Start-up\nOpførsel", "description": "Start automatisk med lodning når strøm sættes til. (L=Lodning | D=Dvale tilstand | R=Dvale tilstand rumtemperatur)" }, "TempChangeShortStep": { "displayText": "Temp ændring\nkort", "description": "Temperatur-ændring-stigning ved kort tryk på knappen" }, "TempChangeLongStep": { "displayText": "Temp ændring\nlang", "description": "Temperatur-ændring-stigning ved lang tryk på knappen" }, "LockingMode": { "displayText": "Tillad låsning\naf knapperne", "description": "Hold begge knapper nede under lodning for at låse dem (B=kun boost-tilstand | F=fuld låsning)" }, "ProfilePhases": { "displayText": "Profil\nFaser", "description": "Antal faser i profiltilstand" }, "ProfilePreheatTemp": { "displayText": "Forvarmnings\nTemp", "description": "Forvarm til denne temperatur ved starten af profiltilstand" }, "ProfilePreheatSpeed": { "displayText": "Forvarmnings\nHastighed", "description": "Forvarm med denne hastighed (grader pr. sekund)" }, "ProfilePhase1Temp": { "displayText": "Fase 1\nTemp", "description": "Måltemperatur for slutningen af denne fase" }, "ProfilePhase1Duration": { "displayText": "Fase 1\nVarighed", "description": "Målvarigheden af denne fase (sekunder)" }, "ProfilePhase2Temp": { "displayText": "Fase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Fase 2\nVarighed", "description": "" }, "ProfilePhase3Temp": { "displayText": "Fase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Fase 3\nVarighed", "description": "" }, "ProfilePhase4Temp": { "displayText": "Fase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Fase 4\nVarighed", "description": "" }, "ProfilePhase5Temp": { "displayText": "Fase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Fase 5\nVarighed", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Nedkølings\nHastighed", "description": "Nedkøl med denne hastighed i slutningen af profiltilstand (grader pr. sekund)" }, "MotionSensitivity": { "displayText": "Bevægelses\nfølsomhed", "description": "Bevægelsesfølsomhed (1=Mindst følsom | ... | 9=Mest følsom)" }, "SleepTemperature": { "displayText": "Dvale\ntemp", "description": "Dvale Temperatur (C)" }, "SleepTimeout": { "displayText": "Dvale\ntimeout", "description": "Dvale Timeout (Minutter | Sekunder)" }, "ShutdownTimeout": { "displayText": "Sluknings\ntimeout", "description": "sluknings Timeout (Minutter)" }, "HallEffSensitivity": { "displayText": "Hall føler\nfølsomhed", "description": "følsomhed overfor magneten (1=Mindst følsom | ... | 9=Mest følsom)" }, "HallEffSleepTimeout": { "displayText": "Hall føler\nSovetid", "description": "Intervallet før starten af \"dvaletilstand\", når Hall føleren overskrider tærsklen" }, "TemperatureUnit": { "displayText": "Temperatur\nEnhed", "description": "Temperatur Enhed (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Skærm\nOrientering", "description": "Skærm Orientering (H=Højre Håndet | V=Venstre Håndet | A=Automatisk)" }, "CooldownBlink": { "displayText": "Køl ned\nBlinkning", "description": "Blink temperaturen på skærmen, mens spidsen stadig er varm." }, "ScrollingSpeed": { "displayText": "Scrolling\nHastighed", "description": "Hastigheden infotekst ruller forbi med (S=Langsom | F=Hurtigt)" }, "ReverseButtonTempChange": { "displayText": "Skift\n+ - tasterne", "description": "Skift tildeling af knapper til temperaturjustering" }, "ReverseButtonSettings": { "displayText": "Skift\nA B keys", "description": "Skift tildeling af knapper til indstillingsmenuen" }, "AnimSpeed": { "displayText": "Anim.\nHastighed", "description": "Hastigheden for ikonanimationer i menuen (S=langsomt | M=medium | F=hurtigt)" }, "AnimLoop": { "displayText": "Anim.\nsløfe", "description": "ikonanimation sløfe i hovedmenuen" }, "Brightness": { "displayText": "Skærm\nlysstyrke", "description": "Juster lysstyrken på OLED-skærmen" }, "ColourInversion": { "displayText": "spejlvende\nskærm", "description": "spejlvende farverne på OLED-skærmen" }, "LOGOTime": { "displayText": "opstartslogo\nvarighed", "description": "Indstiller varigheden for opstartslogoet (s=sekunder)" }, "AdvancedIdle": { "displayText": "Detaljeret\nStandby skærm", "description": "Vis detialieret information med en mindre skriftstørrelse på standby skærmen." }, "AdvancedSoldering": { "displayText": "Detaljeret\nloddeskærm", "description": "Vis detaljeret information mens der loddes" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Aktivere BLE" }, "PowerLimit": { "displayText": "Strøm\nbegrænsning", "description": "Maksimal effekt Loddekolben kan bruge (W=watt)" }, "CalibrateCJC": { "displayText": "kalibrere CJK\nunder næste opstart", "description": "Ved næste opstart vil tip Cold Junction Kompensation blive kalibreret (ikke påkrævet, hvis Delta T er < 5°C))" }, "VoltageCalibration": { "displayText": "Kalibrere\ninput spændingen?", "description": "VIN kalibrering. Knapperne justere, Lang tryk for at gå ud" }, "PowerPulsePower": { "displayText": "Strøm\npuls", "description": "Intensiteten af strøm for hold-vågen-puls (watt)" }, "PowerPulseWait": { "displayText": "Strøm puls\nForsinkelse", "description": "Forsinkelse før hold-vågen-puls udløses (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Strøm puls\nvarighed", "description": "Hold-vågen-pulsvarighed (x 250ms)" }, "SettingsReset": { "displayText": "Gendan fabriks\nIndstillinger", "description": "Gendan alle indstillinger" }, "LanguageSwitch": { "displayText": "Sprog:\n DA Dansk", "description": "" }, "SolderingTipType": { "displayText": "Lodde\nTip Typen", "description": "Vælg den type tip der er monteret" } } } ================================================ FILE: Translations/translation_DE.json ================================================ { "languageCode": "DE", "languageLocalName": "Deutsch", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Erfolgreich\nkalibriert!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Einstellungen\nzurückgesetzt!" }, "NoAccelerometerMessage": { "message": "Bewegungssensor\nnicht erkannt!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\nnicht erkannt!" }, "LockingKeysString": { "message": "GESPERRT" }, "UnlockingKeysString": { "message": "ENTSPERRT" }, "WarningKeysLockedString": { "message": "!GESPERRT!" }, "WarningThermalRunaway": { "message": "Thermal\nRunaway" }, "WarningTipShorted": { "message": "!Lötspitze\nkurzgeschlossen!" }, "SettingsCalibrationWarning": { "message": "Vor dem Neustart bitte sicherstellen, dass Lötspitze & Gerät Raumtemperatur haben!" }, "CJCCalibrating": { "message": "kalibriere\n" }, "SettingsResetWarning": { "message": "Sicher, dass alle Werte zurückgesetzt werden sollen?" }, "UVLOWarningString": { "message": "V niedr." }, "UndervoltageString": { "message": "Unterspannung\n" }, "InputVoltageString": { "message": "V Eingang: \n" }, "SleepingAdvancedString": { "message": "Ruhemodus...\n" }, "SleepingTipAdvancedString": { "message": "Temp: \n" }, "ProfilePreheatString": { "message": "Vorwärmen\n" }, "ProfileCooldownString": { "message": "Abkühlen\n" }, "DeviceFailedValidationWarning": { "message": "Höchstwahrscheinlich ist das Gerät eine Fälschung!" }, "TooHotToStartProfileWarning": { "message": "Zu heiß für\nProfilstart!" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "R", "SettingStartSleepOffChar": "K", "SettingLockBoostChar": "B", "SettingLockFullChar": "V" }, "menuGroups": { "PowerMenu": { "displayText": "Energie-\neinstellungen", "description": "" }, "SolderingMenu": { "displayText": "Löt-\neinstellungen", "description": "" }, "PowerSavingMenu": { "displayText": "Ruhe-\nmodus", "description": "" }, "UIMenu": { "displayText": "Anzeige-\neinstellungen", "description": "" }, "AdvancedMenu": { "displayText": "Erweiterte\nEinstellungen", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Spannungs-\nquelle", "description": "Spannungsquelle (Abschaltspannung) (DC=10V | nS=n*3.3V für n LiIon-Zellen)" }, "MinVolCell": { "displayText": "Minimale\nSpannung", "description": "Minimal zulässige Spannung pro Zelle (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "Spannungs-\nmaximum", "description": "Maximal zulässige Spannung der verwendeten Spannungsversorgung (V=Volt)" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD Abfragedauer in 100ms Schritten (Kompatibilität mit best. QC-Ladegeräten)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Aktiviert PPS & EPR" }, "BoostTemperature": { "displayText": "Boost-\ntemperatur", "description": "Temperatur der Lötspitze im Boostmodus" }, "AutoStart": { "displayText": "Start im\nLötmodus", "description": "Heizverhalten beim Einschalten der Spannungsversorgung (L=Lötmodus | R=Ruhemodus | K=Ruhemodus mit kalter Spitze)" }, "TempChangeShortStep": { "displayText": "Temp-Schritt\nDruck kurz", "description": "Schrittweite für Temperaturänderung bei kurzem Tastendruck" }, "TempChangeLongStep": { "displayText": "Temp-Schritt\nDruck lang", "description": "Schrittweite für Temperaturänderung bei langem Tastendruck" }, "LockingMode": { "displayText": "Tasten-\nsperre", "description": "Langes Drücken beider Tasten im Lötmodus sperrt diese (B=nur Boost | V=vollständig)" }, "ProfilePhases": { "displayText": "Profile\nPhasen", "description": "Anzahl an Phasen im Profilmodus" }, "ProfilePreheatTemp": { "displayText": "Vorheiz-\ntemperatur", "description": "Zu Beginn des Profilmodus auf diese Temperatur vorheizen" }, "ProfilePreheatSpeed": { "displayText": "Vorheiz-\nrate", "description": "Mit dieser Geschwindigkeit vorheizen (Grad pro Sekunde)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemperatur", "description": "Zieltemperatur zum Ende dieser Phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDauer", "description": "Dauer dieser Phase (Sekunden)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemperatur", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDauer", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemperatur", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDauer", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemperatur", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDauer", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemperatur", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDauer", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Abkühl-\nrate", "description": "Am Ende des Profilmodus mit dieser Geschwindigkeit abkühlen (Grad pro Sekunde)" }, "MotionSensitivity": { "displayText": "Bewegungs-\nempfindlichk.", "description": "1=minimal | ... | 9=maximal" }, "SleepTemperature": { "displayText": "Ruhe-\ntemperatur", "description": "Ruhetemperatur der Lötspitze" }, "SleepTimeout": { "displayText": "Ruhever-\nzögerung", "description": "Dauer vor Übergang in den Ruhemodus (s=Sekunden | m=Minuten)" }, "ShutdownTimeout": { "displayText": "Abschalt-\nverzög.", "description": "Dauer vor automatischer Abschaltung (m=Minuten)" }, "HallEffSensitivity": { "displayText": "Empfindlichkeit\nder Hall-Sonde", "description": "Empfindlichkeit der Hall-Sonde um den Ruhemodus auszulösen (1=minimal | ... | 9=maximal)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Dauer vor dem Wechsel in den \"Ruhemodus\", nachdem die Hall-Sonde auslöst" }, "TemperatureUnit": { "displayText": "Temperatur-\neinheit", "description": "C=°Celsius | F=°Fahrenheit" }, "DisplayRotation": { "displayText": "Anzeige-\nausrichtung", "description": "R=rechtshändig | L=linkshändig | A=automatisch" }, "CooldownBlink": { "displayText": "Abkühl-\nblinken", "description": "Temperaturanzeige blinkt beim Abkühlen, solange Spitze heiß ist" }, "ScrollingSpeed": { "displayText": "Scroll-\ngeschw.", "description": "Scrollgeschwindigkeit der Erläuterungen (L=langsam | S=schnell)" }, "ReverseButtonTempChange": { "displayText": "+- Tasten\numkehren", "description": "Tastenbelegung zur Temperaturänderung umkehren" }, "ReverseButtonSettings": { "displayText": "A B Tasten\nvertauschen", "description": "Umgekehrte Belegung der Tasten für das Einstellungsmenü" }, "AnimSpeed": { "displayText": "Anim.\nGeschw.", "description": "Geschwindigkeit der Icon-Animationen im Menü (L=langsam | M=mittel | S=schnell)" }, "AnimLoop": { "displayText": "Anim.\nSchleife", "description": "Icon-Animationen im Hauptmenü wiederholen" }, "Brightness": { "displayText": "Bildschirm-\nhelligkeit", "description": "Verändert die Helligkeit des OLED-Displays" }, "ColourInversion": { "displayText": "Farben\numkehren", "description": "Invertiert die Farben des OLED-Displays" }, "LOGOTime": { "displayText": "Startlogo-\ndauer", "description": "Legt die Dauer der Anzeige des Startlogos fest (s=Sekunden)" }, "AdvancedIdle": { "displayText": "Detaillierte\nRuheansicht", "description": "Detaillierte Anzeige im Ruhemodus" }, "AdvancedSoldering": { "displayText": "Detaillierte\nLötansicht", "description": "Detaillierte Anzeige im Lötmodus" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Aktiviert Bluetooth LE" }, "PowerLimit": { "displayText": "Leistungs-\nmaximum", "description": "Durchschnittliche maximal zulässige Leistungsaufnahme des Lötkolbens (W=Watt)" }, "CalibrateCJC": { "displayText": "Temperatur\nkalibrieren", "description": "Beim nächsten Start wird die Kaltstellenkompensation kalibriert (nicht nötig wenn Delta T < 5°C)" }, "VoltageCalibration": { "displayText": "Eingangsspannung\nkalibrieren", "description": "Kalibrierung der Eingangsspannung (Langer Tastendruck zum Verlassen)" }, "PowerPulsePower": { "displayText": "Leistungs-\nimpuls", "description": "Powerbank mit einem Impuls wach halten (Watt)" }, "PowerPulseWait": { "displayText": "Impuls-\nverzögerung", "description": "Dauer vor Abgabe von Wachhalteimpulsen (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Impuls-\ndauer", "description": "Dauer des Wachhalteimpulses (x 250ms)" }, "SettingsReset": { "displayText": "Einstellungen\nzurücksetzen", "description": "Werte auf Werkseinstellungen zurücksetzen" }, "LanguageSwitch": { "displayText": "Sprache:\n DE Deutsch", "description": "" }, "SolderingTipType": { "displayText": "Löt-\nspitzentyp", "description": "Wählen Sie den Typ der eingesetzten Spitze" } } } ================================================ FILE: Translations/translation_EL.json ================================================ { "languageCode": "EL", "languageLocalName": "Greek", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "Βαθμονόμηση\nολοκληρώθηκε!" }, "ResetOKMessage": { "message": "Επαν. OK" }, "SettingsResetMessage": { "message": "Κάποιες ρυθμ.\nάλλαξαν" }, "NoAccelerometerMessage": { "message": "Δεν εντοπίστηκε\nεπιταχυνσιόμετρο" }, "NoPowerDeliveryMessage": { "message": "Δεν εντοπίστηκε\nκύκλωμα USB-PD" }, "LockingKeysString": { "message": "ΚΛΕΙΔ." }, "UnlockingKeysString": { "message": "ΞΕΚΛΕΙΔ." }, "WarningKeysLockedString": { "message": "ΚΛΕΙΔΩΜΕΝΑ\nΠΛΗΚΤΡΑ!" }, "WarningThermalRunaway": { "message": "Θερμική\nΦυγή" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Πριν την επανεκκίνηση, βεβαιωθείτε ότι η μύτη και η συσκ. είναι σε θερμ. δωματίου!" }, "CJCCalibrating": { "message": "βαθμονόμηση\n" }, "SettingsResetWarning": { "message": "Σίγουρα θέλετε επαναφορά αρχικών ρυθμίσεων;" }, "UVLOWarningString": { "message": "Χαμηλ DC" }, "UndervoltageString": { "message": "Υπόταση\n" }, "InputVoltageString": { "message": "Είσοδος V: \n" }, "SleepingAdvancedString": { "message": "Υπνος...\n" }, "SleepingTipAdvancedString": { "message": "Μύτη: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Η συσκευή σας ίσως να μην είναι αυθεντική!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "Α", "SettingSlowChar": "Α", "SettingMediumChar": "Μ", "SettingFastChar": "Γ", "SettingStartSolderingChar": "Κ", "SettingStartSleepChar": "Ζ", "SettingStartSleepOffChar": "Υ", "SettingLockBoostChar": "B", "SettingLockFullChar": "Π" }, "menuGroups": { "PowerMenu": { "displayText": "Ρυθμίσεις\nενέργειας", "description": "" }, "SolderingMenu": { "displayText": "Ρυθμίσεις\nκόλλησης", "description": "" }, "PowerSavingMenu": { "displayText": "Λειτουργία\nύπνου", "description": "" }, "UIMenu": { "displayText": "Διεπαφή\nχρήστη", "description": "" }, "AdvancedMenu": { "displayText": "Προηγμένες\nρυθμίσεις", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Πηγή\nενέργειας", "description": "Πηγή ενέργειας. Oρισμός τάσης απενεργοποίησης. (DC 10V) (S 3.3V ανα μπαταρία, απενεργοποίηση ενεργειακού ορίου)" }, "MinVolCell": { "displayText": "Ελάχιστη\nτάση", "description": "Ελάχιστη επιτρεπτή τάση ανα μπαταρία (3 σε σειρά: 3 - 3.7V | 4-6 σε σειρά: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Τάση\nQC", "description": "Μέγιστη τάση QC που να ζητείται από το τροφοδοτικό" }, "PDNegTimeout": { "displayText": "χρονικό όριο\nPD", "description": "Χρονικό όριο διαπραγμάτευσης PD σε βήματα 100ms για συμβατότητα με κάποιους φορτιστές QC" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Ενεργοποιεί λειτουργίες PPS & EPR." }, "BoostTemperature": { "displayText": "Θερμοκ.\nboost", "description": "Θερμοκρασία στη \"λειτουργία boost\"" }, "AutoStart": { "displayText": "Ζέσταμα\nκατά την εν.", "description": "Κ=θερμ. κόλλησης | Z=αναμονή σε θερμοκρασία ύπνου μέχρι την κίνηση | Υ=αναμονή χωρίς ζέσταμα μέχρι την κίνηση" }, "TempChangeShortStep": { "displayText": "Αλλαγή θερμοκ.\nστιγμιαίο", "description": "Βήμα αλλαγής θερμοκρασίας σε στιγμιαίο πάτημα πλήκτρου" }, "TempChangeLongStep": { "displayText": "Αλλαγή θερμοκ.\nπαρατεταμένο", "description": "Βήμα αλλαγής θερμοκρασίας σε παρατεταμένο πάτημα πλήκτρου" }, "LockingMode": { "displayText": "Κλείδωμα\nπλήκτρων", "description": "Κατά την κόλληση, κρατήστε και τα δύο πλήκτρα για κλείδωμα (B=μόνο λειτ. boost | Π=πλήρες κλείδωμα)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Ευαισθησία\nκίνησης", "description": "1=λιγότερο ευαίσθητο | ... | 9=περισσότερο ευαίσθητο" }, "SleepTemperature": { "displayText": "Θερμοκρ.\nύπνου", "description": "Θερμοκρασία μύτης σε λειτ. ύπνου" }, "SleepTimeout": { "displayText": "Έναρξη\nύπνου", "description": "Χρονικό διάστημα πρίν την ενεργοποίηση λειτουργίας ύπνου (Δ=δευτ. | Λ=λεπτά)" }, "ShutdownTimeout": { "displayText": "Έναρξη\nαπενεργ.", "description": "Χρονικό διάστημα πρίν την απενεργοποίηση του κολλητηριού (Λ=λεπτά)" }, "HallEffSensitivity": { "displayText": "Ευαισθ. αισθ. \nφαιν. Hall", "description": "Ευαισθησία του αισθητήρα φαινομένου Hall για εντοπισμό αδράνειας (1=λιγότερο ευαίσθητο | ... | 9=περισσότερο ευαίσθητο)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Το διάστημα πριν από την \"λειτουργία ύπνου\" ξεκινά όταν το εφέ αίθουσας είναι πάνω από το όριο" }, "TemperatureUnit": { "displayText": "Μονάδες\nθερμοκρασίας", "description": "C=Κελσίου | F=Φαρενάιτ" }, "DisplayRotation": { "displayText": "Διάταξη\nοθόνης", "description": "R=δεξιόχειρες | L=αριστερόχειρες | Α=αυτόματο" }, "CooldownBlink": { "displayText": "Αναβοσβήσιμο\nψύξης", "description": "Αναβοσβήσιμο της ενδειξης θερμοκρασίας κατά την παύση θέρμανσης όταν η μύτη είναι ακόμα καυτή" }, "ScrollingSpeed": { "displayText": "Ταχύτητα\nκύλισης", "description": "Ταχύτητα κύλισης κειμένου (Α=αργά | Γ=γρήγορα)" }, "ReverseButtonTempChange": { "displayText": "Αντιστροφή\nπλήκτρων + -", "description": "Αντιστροφή διάταξης πλήκτρων στη ρύθμιση θερμοκρασίας" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Ταχύτητα\nκιν. εικονιδ.", "description": "Ρυθμός κίνησης εικονιδίων στο μενού (Α=αργός | Μ=μέτριος | Γ=γρήγορος)" }, "AnimLoop": { "displayText": "Επανάληψη\nκιν. εικονιδ.", "description": "Επανάληψη κίνησης εικονιδίων στο αρχικό μενού" }, "Brightness": { "displayText": "Αντίθεση\nοθόνης", "description": "Ρύθμιση φωτεινότητας οθόνης OLED" }, "ColourInversion": { "displayText": "Αντιστροφή\nχρωμάτων", "description": "Αντιστροφή χρωμάτων οθόνης OLED" }, "LOGOTime": { "displayText": "Διάρκεια\nlogo εκκίνησης", "description": "Διάρκεια εμφάνισης της εικόνας εκκίνησης (s=seconds)" }, "AdvancedIdle": { "displayText": "Λεπτομερής\nοθ. αδράνειας", "description": "Προβολή λεπτομερών πληροφοριών σε μικρότερη γραμματοσειρά στην οθόνη αδράνειας" }, "AdvancedSoldering": { "displayText": "Λεπτομερής\nοθ. κόλλησης", "description": "Προβολή λεπτομερών πληροφοριών σε μικρότερη γραμματοσειρά στην οθόνη κόλλησης" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Ενεργειακό\nόριο", "description": "Μέγιστη ενέργεια που μπορεί να χρησιμοποιεί το κολλητήρι (W=watt)" }, "CalibrateCJC": { "displayText": "Βαθμονόμηση CJC\nσε επόμενη έναρξη", "description": "Στην επόμενη εκκίνηση θα γίνει βαθμονόμηση θερμοκρασίας (δεν απαιτείται αν Δθερμ < 5 C)" }, "VoltageCalibration": { "displayText": "Βαθμονόμηση\nτάσης εισόδου;", "description": "Έναρξη βαθμονόμησης τάσης εισόδου (κράτημα για έξοδο)" }, "PowerPulsePower": { "displayText": "Παλμός\nενέργειας", "description": "Ένταση ενέργειας παλμού διατήρησης λειτουργίας (W=watt)" }, "PowerPulseWait": { "displayText": "Καθυστέρηση\nπαλμού ενέργ.", "description": "Καθυστέρηση πριν την ενεργοποίση παλμού διατήρησης λειτουργίας (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Διάρκεια\nπαλμού ενέργ.", "description": "Διάρκεια παλμού διατήρησης ενέργειας (x 250ms)" }, "SettingsReset": { "displayText": "Επαναφορά\nεργ. ρυθμίσεων;", "description": "Επαναφορά στις προεπιλεγμένες ρυθμίσεις" }, "LanguageSwitch": { "displayText": "Γλώσσα:\n EL Ελληνικά", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_EN.json ================================================ { "languageCode": "EN", "languageLocalName": "English", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Certain settings\nchanged!" }, "NoAccelerometerMessage": { "message": "No accelerometer\ndetected!" }, "NoPowerDeliveryMessage": { "message": "No USB-PD IC\ndetected!" }, "LockingKeysString": { "message": "LOCKED" }, "UnlockingKeysString": { "message": "UNLOCKED" }, "WarningKeysLockedString": { "message": "!LOCKED!" }, "WarningThermalRunaway": { "message": "Thermal\nRunaway" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Are you sure you want to restore default settings?" }, "UVLOWarningString": { "message": "DC LOW" }, "UndervoltageString": { "message": "Undervoltage\n" }, "InputVoltageString": { "message": "Input V: \n" }, "SleepingAdvancedString": { "message": "Sleeping...\n" }, "SleepingTipAdvancedString": { "message": "Tip: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "F", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Power\nsettings", "description": "" }, "SolderingMenu": { "displayText": "Soldering\nsettings", "description": "" }, "PowerSavingMenu": { "displayText": "Sleep\nmode", "description": "" }, "UIMenu": { "displayText": "User\ninterface", "description": "" }, "AdvancedMenu": { "displayText": "Advanced\nsettings", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Power\nsource", "description": "Set cutoff voltage to prevent battery overdischarge (DC=10V) (S=3.3V per cell, disable PWR limit)" }, "MinVolCell": { "displayText": "Minimum\nvoltage", "description": "Minimum allowed voltage per battery cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nvoltage", "description": "Max QC voltage the iron should negotiate for" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD negotiation timeout in 100ms steps for compatibility with some QC chargers" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Boost\ntemp", "description": "Tip temperature used in \"boost mode\"" }, "AutoStart": { "displayText": "Start-up\nbehavior", "description": "S=heat to soldering temp | Z=standby at sleep temp until moved | R=standby without heating until moved" }, "TempChangeShortStep": { "displayText": "Temp change\nshort", "description": "Temperature-change-increment on short button press" }, "TempChangeLongStep": { "displayText": "Temp change\nlong", "description": "Temperature-change-increment on long button press" }, "LockingMode": { "displayText": "Allow locking\nbuttons", "description": "While soldering, hold down both buttons to toggle locking them (B=boost mode only | F=full locking)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Motion\nsensitivity", "description": "1=least sensitive | ... | 9=most sensitive" }, "SleepTemperature": { "displayText": "Sleep\ntemp", "description": "Tip temperature while in \"sleep mode\"" }, "SleepTimeout": { "displayText": "Sleep\ntimeout", "description": "Interval before \"sleep mode\" starts (s=seconds | m=minutes)" }, "ShutdownTimeout": { "displayText": "Shutdown\ntimeout", "description": "Interval before the iron shuts down (m=minutes)" }, "HallEffSensitivity": { "displayText": "Hall sensor\nsensitivity", "description": "Sensitivity to magnets (1=least sensitive | ... | 9=most sensitive)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "Temperature\nunit", "description": "C=°Celsius | F=°Fahrenheit" }, "DisplayRotation": { "displayText": "Display\norientation", "description": "R=right-handed | L=left-handed | A=automatic" }, "CooldownBlink": { "displayText": "Cooldown\nflashing", "description": "Flash temp reading at idle while tip is hot" }, "ScrollingSpeed": { "displayText": "Scrolling\nspeed", "description": "Scrolling speed of info text (S=slow | F=fast)" }, "ReverseButtonTempChange": { "displayText": "Swap\n+ - keys", "description": "Reverse assignment of buttons for temperature adjustment" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nspeed", "description": "Pace of icon animations in menu (S=slow | M=medium | F=fast)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loop icon animations in main menu" }, "Brightness": { "displayText": "Screen\nbrightness", "description": "Adjust the OLED screen brightness" }, "ColourInversion": { "displayText": "Invert\nscreen", "description": "Invert the OLED screen colors" }, "LOGOTime": { "displayText": "Boot logo\nduration", "description": "Set boot logo duration (s=seconds)" }, "AdvancedIdle": { "displayText": "Detailed\nidle screen", "description": "Display detailed info in a smaller font on idle screen" }, "AdvancedSoldering": { "displayText": "Detailed\nsolder screen", "description": "Display detailed info in a smaller font on soldering screen" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Power\nlimit", "description": "Average maximum power the iron can use (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "Calibrate Cold Junction Compensation at next boot (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "Calibrate\ninput voltage", "description": "Start VIN calibration (long press to exit)" }, "PowerPulsePower": { "displayText": "Power\npulse", "description": "Intensity of power of keep-awake-pulse (W=watt)" }, "PowerPulseWait": { "displayText": "Power pulse\ndelay", "description": "Delay before keep-awake-pulse is triggered (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduration", "description": "Keep-awake-pulse duration (x 250ms)" }, "SettingsReset": { "displayText": "Restore default\nsettings", "description": "Reset all settings to default" }, "LanguageSwitch": { "displayText": "Language:\n EN English", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_ES.json ================================================ { "languageCode": "ES", "languageLocalName": "Castellano", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "¡Calibracion\nlista!" }, "ResetOKMessage": { "message": "Listo" }, "SettingsResetMessage": { "message": "¡Ajustes\nReiniciados!" }, "NoAccelerometerMessage": { "message": "¡Acelerómetro no \nDetectado!" }, "NoPowerDeliveryMessage": { "message": "¡USB-PD no \nDetectado!" }, "LockingKeysString": { "message": "BLOQUEADO" }, "UnlockingKeysString": { "message": "DESBLOQUEADO" }, "WarningKeysLockedString": { "message": "¡BLOQUEADO!" }, "WarningThermalRunaway": { "message": "Térmico\nFuera de control" }, "WarningTipShorted": { "message": "¡Punta en cortocircuito!" }, "SettingsCalibrationWarning": { "message": "¡Antes de reiniciar, asegúrese de que la punta y el mango estén a temperatura ambiente!" }, "CJCCalibrating": { "message": "Calibrando\n" }, "SettingsResetWarning": { "message": "¿Quieres restablecer los ajustes?" }, "UVLOWarningString": { "message": "CC BAJA" }, "UndervoltageString": { "message": "Voltaje bajo\n" }, "InputVoltageString": { "message": "Voltaje: \n" }, "SleepingAdvancedString": { "message": "En reposo...\n" }, "SleepingTipAdvancedString": { "message": "Punta: \n" }, "ProfilePreheatString": { "message": "Precalentado\n" }, "ProfileCooldownString": { "message": "Enfriado\n" }, "DeviceFailedValidationWarning": { "message": "¡Es probable que su dispositivo sea falso!" }, "TooHotToStartProfileWarning": { "message": "Muy caliente para \nempezar perfil" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "I", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "R", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "R", "SettingStartSleepOffChar": "F", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Potencia\najustes", "description": "" }, "SolderingMenu": { "displayText": "Soldadura\najustes", "description": "" }, "PowerSavingMenu": { "displayText": "Modos de\nreposo", "description": "" }, "UIMenu": { "displayText": "Interfaz\nde usuario", "description": "" }, "AdvancedMenu": { "displayText": "Ajustes\navanzados", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Modo por\nDefecto" }, "USBPDModeNoDynamic": { "displayText": "Dinámico\nNo" }, "USBPDModeSafe": { "displayText": "Modo\nSeguro" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Fuente\nde energía", "description": "Elige el tipo de fuente para limitar el voltaje (DC 10V) (S 3,3V por pila, ilimitado)" }, "MinVolCell": { "displayText": "Mínimo\nvoltaje", "description": "Voltaje mínimo permitido por célula (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "Potencia de\nentrada", "description": "Potencia en vatios del adaptador de corriente utilizado" }, "PDNegTimeout": { "displayText": "PD\ntiempo de espera", "description": "Tiempo de espera de negociación de PD en pasos de 100ms para compatibilidad con algunos cargadores QC (0: apagado)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Permite modos PPS & EPR" }, "BoostTemperature": { "displayText": "Ajustar la\ntemp. extra", "description": "Temperatura de la punta de \"modo boost\"" }, "AutoStart": { "displayText": "Calentar\nal enchufar", "description": "Calentado automático al iniciar (S=entrar en modo soldar | R=solo entrar en reposo | F=en reposo pero mantiene la punta fría)" }, "TempChangeShortStep": { "displayText": "Cambio temp.\npuls. cortas", "description": "Aumento de la temperatura al pulsar brevemente un botón" }, "TempChangeLongStep": { "displayText": "Cambio temp.\npuls. largas", "description": "Aumento de la temperatura al pulsar prolongadamente un botón" }, "LockingMode": { "displayText": "Permitir botones\nbloqueo", "description": "Mientras suelda, mantenga pulsados ambos botones para alternar su bloqueo (B=sólo modo boost | F=bloqueo total)" }, "ProfilePhases": { "displayText": "Fases de\nPerfil", "description": "Numero de fases en modo perfil" }, "ProfilePreheatTemp": { "displayText": "Temp de \n precalentado", "description": "Precalentar a esta temperatura al inicio del modo perfil" }, "ProfilePreheatSpeed": { "displayText": "Velocidad de \nPrecalentado", "description": "Precalentar a esta velocidad (grados por segundo)" }, "ProfilePhase1Temp": { "displayText": "Fase 1\nTemp", "description": "Temperatura objetivo al final de esta fase" }, "ProfilePhase1Duration": { "displayText": "Fase 1\nDuración", "description": "Duración objetivo de esta fase (segundos)" }, "ProfilePhase2Temp": { "displayText": "Fase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Fase 2\nDuración", "description": "" }, "ProfilePhase3Temp": { "displayText": "Fase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Fase 3\nDuración", "description": "" }, "ProfilePhase4Temp": { "displayText": "Fase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Fase 4\nDuración", "description": "" }, "ProfilePhase5Temp": { "displayText": "Fase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Fase 5\nDuración", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Velocidad de\nEnfriamineto", "description": "Enfriar a esta velocidad al final del modo perfil (grados por segundo)" }, "MotionSensitivity": { "displayText": "Detección de\nmovimiento", "description": "Tiempo de reacción al agarrar (1=menos sensible | ... | 9=más sensible)" }, "SleepTemperature": { "displayText": "Temperatura\nen reposo", "description": "Temperatura de la punta en \"reposo\"" }, "SleepTimeout": { "displayText": "Entrar\nen reposo", "description": "Tiempo de inactividad para entrar en reposo (min | seg)" }, "ShutdownTimeout": { "displayText": "Tiempo de\napagado", "description": "Tiempo de inactividad para apagarse (en minutos)" }, "HallEffSensitivity": { "displayText": "Hall Eff\nSensibilidad", "description": "Sensibilidad del sensor de efecto Hall en la detección de reposo (1=menos sensible | ... | 9=más sensible)" }, "HallEffSleepTimeout": { "displayText": "Tiempo reposo\nSensor Hall", "description": "Intervalo antes de que \"modo resposo\" empiece cuando sensorhall supera límite" }, "TemperatureUnit": { "displayText": "Unidad de\ntemperatura", "description": "Unidad de temperatura (C=Centígrados | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Orientación\nde pantalla", "description": "Orientación de la pantalla (D=diestro | I=zurdo | A=automático)" }, "CooldownBlink": { "displayText": "Parpadear\nal enfriar", "description": "Parpadear texto en inactivo cuando la punta este caliente" }, "ScrollingSpeed": { "displayText": "Velocidad\ndel texto", "description": "Velocidad de desplazamiento del texto (R=rápida | L=lenta)" }, "ReverseButtonTempChange": { "displayText": "Invertir\nbotones +/-", "description": "Invertir botones de ajuste de temperatura" }, "ReverseButtonSettings": { "displayText": "Cambiar\nteclas A B", "description": "Asignación inversa de botonos para el menú de configuración" }, "AnimSpeed": { "displayText": "Anim.\nvelocidad", "description": "Velocidad de animaciones de iconos en el menú (L=baja | M=media | R=alta)" }, "AnimLoop": { "displayText": "Anim.\nbucle", "description": "Bucle de animaciones del menú principal" }, "Brightness": { "displayText": "Pantalla\nbrillo", "description": "Ajusta el brillo de la pantalla OLED" }, "ColourInversion": { "displayText": "Invertir\npantalla", "description": "Invertir la pantalla OLED" }, "LOGOTime": { "displayText": "Logo inicial\nduración", "description": "Duración de la animación del logo inicial (s=segundos)" }, "AdvancedIdle": { "displayText": "Info extra en\nmodo reposo", "description": "Mostrar información detallada en tamaño pequeño en la pantalla de reposo" }, "AdvancedSoldering": { "displayText": "Info extra\nal soldar", "description": "Mostrar información detallada en tamaño pequeño en la pantalla de soldadura" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Habilitar BLE" }, "PowerLimit": { "displayText": "Potencia\nlímite", "description": "Elige el límite de potencia máxima del soldador (en vatios)" }, "CalibrateCJC": { "displayText": "Calibrar CJC\nen el próximo inicio", "description": "Al siguinte inicio la compensación de referencia será calibrada (no requerido si el Delta T es < 5°C)" }, "VoltageCalibration": { "displayText": "Calibrar voltaje\nde entrada", "description": "Iniciar calibración VIN (pulsación larga para salir)" }, "PowerPulsePower": { "displayText": "Pulsos bat.\nconstantes", "description": "Intensidad de la potencia del pulso para mantener encendido (W=Vatio)" }, "PowerPulseWait": { "displayText": "Tiempo entre\n pulso de energia", "description": "Tiempo de espera del pulso para mantener encendido (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Duración de\n pulso de energia", "description": "Duración del pulso para mantener encendido (x 250ms)" }, "SettingsReset": { "displayText": "Volver a ajustes\nde fábrica", "description": "Restablecer todos los ajustes por defecto" }, "LanguageSwitch": { "displayText": "Idioma:\n ES Castellano", "description": "" }, "SolderingTipType": { "displayText": "Tipo de\nTpunta", "description": "Selecciona la punta montada" } } } ================================================ FILE: Translations/translation_ET.json ================================================ { "languageCode": "ET", "languageLocalName": "Eesti", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibreerimine\ntehtud!" }, "ResetOKMessage": { "message": "Vaikesätted\ntaastatud" }, "SettingsResetMessage": { "message": "Osad seadistused\non muutunud!" }, "NoAccelerometerMessage": { "message": "Kiirendusandurit\nei tuvastatud!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\nei tuvastatud!" }, "LockingKeysString": { "message": "LUKUS" }, "UnlockingKeysString": { "message": "AVATUD" }, "WarningKeysLockedString": { "message": "!LUKUS!" }, "WarningThermalRunaway": { "message": "Termiline\närajooks" }, "WarningTipShorted": { "message": "!Otsik lühises!" }, "SettingsCalibrationWarning": { "message": "Enne taaskäivitamist veenduge, et otsik ja käepide on toatemperatuuril!" }, "CJCCalibrating": { "message": "kalibreerimine\n" }, "SettingsResetWarning": { "message": "Kas olete kindel, et soovite taastada vaikesätted?" }, "UVLOWarningString": { "message": "DC MADAL" }, "UndervoltageString": { "message": "Alapinge\n" }, "InputVoltageString": { "message": "Sisend V: \n" }, "SleepingAdvancedString": { "message": "Unerežiim...\n" }, "SleepingTipAdvancedString": { "message": "Otsik: \n" }, "ProfilePreheatString": { "message": "Eelkuumutus\n" }, "ProfileCooldownString": { "message": "Jahtumine\n" }, "DeviceFailedValidationWarning": { "message": "Teie seade on tõenäoliselt võltsing!" }, "TooHotToStartProfileWarning": { "message": "Liiga kuum,\net alustada profiili" } }, "characters": { "SettingRightChar": "P", "SettingLeftChar": "V", "SettingAutoChar": "A", "SettingSlowChar": "A", "SettingMediumChar": "K", "SettingFastChar": "T", "SettingStartSolderingChar": "J", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "P", "SettingLockBoostChar": "B", "SettingLockFullChar": "T" }, "menuGroups": { "PowerMenu": { "displayText": "Toiteseaded\n", "description": "" }, "SolderingMenu": { "displayText": "Jootmise\nseaded", "description": "" }, "PowerSavingMenu": { "displayText": "Unerežiimi\nseaded", "description": "" }, "UIMenu": { "displayText": "Kasutaja-\nliides", "description": "" }, "AdvancedMenu": { "displayText": "Täpsemad\nseaded", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Toiteallikas\nDC", "description": "Määrab katkestuspinge, et vältida aku liigset tühjenemist. (DC 10V) (S=3,3V elemendi kohta, eemaldab voolupiirangud)" }, "MinVolCell": { "displayText": "Minimaalne\npinge", "description": "Minimaalne lubatud pinge akuelemendi kohta (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\npinge", "description": "Maks. QC pinge, mida jootekolb läbirääkima peaks" }, "PDNegTimeout": { "displayText": "PD\naegumine", "description": "PD läbirääkimise aegumine 100ms sammudena, et tagada ühilduvus osade QC laadijatega" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Võimaldab PPS- ja EPR-režiimi" }, "BoostTemperature": { "displayText": "Boost\ntemp", "description": "Kolviotsiku temperatuur \"boost režiimis\"" }, "AutoStart": { "displayText": "Käitumine\nkäivitusel", "description": "J=kuumuta jootmistemperatuurini | Z=unerežiim, kuni seadet liigutatakse | P=unerežiim toatemperatuuril, kuni seadet liigutatakse" }, "TempChangeShortStep": { "displayText": "Temp. muut\nlühike", "description": "Temperatuuri muutmine lühikese vajutusega" }, "TempChangeLongStep": { "displayText": "Temp. muut\npikk", "description": "Temperatuuri muutmine pika vajutusega" }, "LockingMode": { "displayText": "Luba nuppude\nlukustamine", "description": "Hoidke jootmise ajal mõlemad nupud all, et lülitada nende lukustamist (B=ainult boostrežiimis | T=täielik lukustamine)." }, "ProfilePhases": { "displayText": "Profiil\nfaasid", "description": "Faaside arv profiilirežiimis" }, "ProfilePreheatTemp": { "displayText": "Eelkuumutus\ntemp.", "description": "Eelkuumuta sellele temperatuurile profiilirežiimi alguses" }, "ProfilePreheatSpeed": { "displayText": "Eelkuumutus\nkiirus", "description": "Eelkuumuta sellise kiirusega (kraadi sekundis)." }, "ProfilePhase1Temp": { "displayText": "Faas 1\ntemp.", "description": "Selle faasi lõpu sihttemperatuur" }, "ProfilePhase1Duration": { "displayText": "Faas 1\nkestus", "description": "Selle faasi sihtkestus (sekundites)" }, "ProfilePhase2Temp": { "displayText": "Faas 2\ntemp.", "description": "" }, "ProfilePhase2Duration": { "displayText": "Faas 2\nkestus", "description": "" }, "ProfilePhase3Temp": { "displayText": "Faas 3\ntemp.", "description": "" }, "ProfilePhase3Duration": { "displayText": "Faas 3\nkestus", "description": "" }, "ProfilePhase4Temp": { "displayText": "Faas 4\ntemp.", "description": "" }, "ProfilePhase4Duration": { "displayText": "Faas 4\nkestus", "description": "" }, "ProfilePhase5Temp": { "displayText": "Faas 5\ntemp.", "description": "" }, "ProfilePhase5Duration": { "displayText": "Faas 5\nkestus", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Jahtumise\nkiirus", "description": "Jahtumine selle kiirusega profiilirežiimi lõpus (kraadi sekundis)" }, "MotionSensitivity": { "displayText": "Liikumise\ntundlikkus", "description": "1=vähetundlikuim | ... | 9=kõige tundlikum" }, "SleepTemperature": { "displayText": "Unerežiimi\ntemp", "description": "Kolviotsiku temperatuur \"unerežiimis\"" }, "SleepTimeout": { "displayText": "Unerežiimi\nviide", "description": "Aeg enne \"unerežiimi\" algust (s=sekundid | m=minutid)" }, "ShutdownTimeout": { "displayText": "Seiskumise\nviide", "description": "Aeg enne jootekolvi välja lülitamist (m=minutid)" }, "HallEffSensitivity": { "displayText": "Halli anduri\ntundlikkus", "description": "Tundlikkus magnetite suhtes (1=vähetundlikum | ... | 9=kõige tundlikum)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Intervall enne \"unerežiimi\" käivitub, kui saaliefekt on üle läve" }, "TemperatureUnit": { "displayText": "Temperatuuri\nühik", "description": "C=°Celsius | F=°Fahrenheit" }, "DisplayRotation": { "displayText": "Ekraani\norienteeritus", "description": "P=paremakäeline | V=vasakukäeline | A=automaatne" }, "CooldownBlink": { "displayText": "Jahtumisel\nvilkumine", "description": "Vilguta otsiku temperatuuri, kui see jahtub ja on veel ohtlikult kuum" }, "ScrollingSpeed": { "displayText": "Kerimise\nkiirus", "description": "Infoteksti kerimise kiirus (A = aeglane | K = kiire)" }, "ReverseButtonTempChange": { "displayText": "Vaheta\n+ - nupud", "description": "Temperatuurinuppude asukohtade vahetus" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nkiirus", "description": "Menüüikoonide animatsiooni kiirus (A=aeglane | K=keskmine | T=tempokas)" }, "AnimLoop": { "displayText": "Pidevad\nanim.", "description": "Esitage menüüs pidevalt animatsioone" }, "Brightness": { "displayText": "Ekraani\nheledus", "description": "Seadista OLED ekraani heledust" }, "ColourInversion": { "displayText": "Ekraani\ninverteerimine", "description": "Inverteeri OLED ekraani värvid" }, "LOGOTime": { "displayText": "Alguslogo\nkestus", "description": "Aeg, mille jooksul näidatakse logo peale kolvi käivitamist (s=sekundites)" }, "AdvancedIdle": { "displayText": "Andmed\npuhkeolekus", "description": "Näita unerežiimis üksikasjalikumat teavet väiksemas kirjas" }, "AdvancedSoldering": { "displayText": "Andmed\njootmisel", "description": "Näita jootmisel üksikasjalikumat teavet väiksemas kirjas" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Luba BLE" }, "PowerLimit": { "displayText": "Võimsus-\npiirang", "description": "Suurim lubatud võimsus mida kolb võib kasutada (W=vatti)" }, "CalibrateCJC": { "displayText": "Kalibr. CJC\ntuleval käivit.", "description": "Kalibreeri külmaühenduse kompensatsioon (CJC) järgmisel käivitamisel (ei ole vajalik, kui Delta T on < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibreeri\nsisendpinge", "description": "Sisendpinge (VIN) kalibreerimine (väljumiseks vajutage pikalt)" }, "PowerPulsePower": { "displayText": "Impulsi\ntugevus", "description": "Ärkvelolekuimpulsi tugevus (vattides). Vajalik, vältimaks akupanga uinumist." }, "PowerPulseWait": { "displayText": "Impulsi\nviivitus", "description": "Viivitus enne ärkvelolekuimpulsi käivitumist (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Impulsi\nkestus", "description": "Ärkvelolekuimpulsi kestus (x 250ms)" }, "SettingsReset": { "displayText": "Taasta\nvaikesätted", "description": "Nulli kõik seadistused vaikesätetele" }, "LanguageSwitch": { "displayText": "Keel:\n ET Eesti", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_FI.json ================================================ { "languageCode": "FI", "languageLocalName": "Suomi", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrointi\nvalmis!" }, "ResetOKMessage": { "message": "Tehdasasetukset\npalautettu!" }, "SettingsResetMessage": { "message": "Tehdasasetukset\npalautettu!" }, "NoAccelerometerMessage": { "message": "Kiihtyvyysanturi\npuuttuu!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\npuuttuu!" }, "LockingKeysString": { "message": "Näppäinlukko\nkäytössä." }, "UnlockingKeysString": { "message": "Näppäimet\nkäytössä." }, "WarningKeysLockedString": { "message": "!Näppäimet\nlukittu!" }, "WarningThermalRunaway": { "message": "!Lämmönsäätelyn\nhäiriö!" }, "WarningTipShorted": { "message": "!Kärki\noikosulussa!" }, "SettingsCalibrationWarning": { "message": "Varmista laitteen ja kärjen huoneenlämpöisyys ennen uudelleenkäynnistystä!" }, "CJCCalibrating": { "message": "Kalibroidaan\n" }, "SettingsResetWarning": { "message": "Haluatko varmasti palauttaa oletusarvot?" }, "UVLOWarningString": { "message": "DC jännite alhainen." }, "UndervoltageString": { "message": "Alijännite.\n" }, "InputVoltageString": { "message": "Jännite: \n" }, "SleepingAdvancedString": { "message": "Lepotila...\n" }, "SleepingTipAdvancedString": { "message": "Kärki: \n" }, "ProfilePreheatString": { "message": "Esilämmitetään\n" }, "ProfileCooldownString": { "message": "Jäähtyy\n" }, "DeviceFailedValidationWarning": { "message": "Laite saattaa olla väärennös!" }, "TooHotToStartProfileWarning": { "message": "Lämpötila liian korkea\nprofiilin aloitukseen!" } }, "characters": { "SettingRightChar": "O", "SettingLeftChar": "V", "SettingAutoChar": "A", "SettingSlowChar": "A", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "J", "SettingStartSleepChar": "L", "SettingStartSleepOffChar": "H", "SettingLockBoostChar": "V", "SettingLockFullChar": "K" }, "menuGroups": { "PowerMenu": { "displayText": "Virta-\nasetukset", "description": "" }, "SolderingMenu": { "displayText": "Juotos-\nasetukset", "description": "" }, "PowerSavingMenu": { "displayText": "Lepotilan\nasetukset", "description": "" }, "UIMenu": { "displayText": "Käyttö-\nliittymä", "description": "" }, "AdvancedMenu": { "displayText": "Lisä-\nasetukset", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "USB-PD\noletus-t" }, "USBPDModeNoDynamic": { "displayText": "USB-PD\nvakaa-ti" }, "USBPDModeSafe": { "displayText": "USB-PD\nturva-ti" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Virtalähde\nDC", "description": "Virtalähde. Asettaa katkaisujännitteen. (DC 10V) (S 3.3V per kenno, poistaa virtarajoitukset)" }, "MinVolCell": { "displayText": "Pienin\njännite", "description": "Pienin sallittu jännite per kenno (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\njännite", "description": "Ensisijainen maksimi QC jännite." }, "PDNegTimeout": { "displayText": "PD\naikakatkais", "description": "PD neuvottelun aikakatkaisu 100ms askelin joitakin QC-latureita varten." }, "USBPDMode": { "displayText": "PD\ntila", "description": "Vakaa tila ei käytä EPR & PPS, turva-tila ei käytä vastuksen pehmustusta." }, "BoostTemperature": { "displayText": "Tehostus-\nlämpötila", "description": "Tehostustilan lämpötila." }, "AutoStart": { "displayText": "Autom.\nkäynnistys", "description": "Käynnistää virrat kytkettäessä juotostilan automaattisesti. (J=juotostila | L=Lepotila | H=Lepotila huoneenlämpö)" }, "TempChangeShortStep": { "displayText": "Lämmön muutos\nlyhyt painal.", "description": "Lämpötilan muutos lyhyellä painalluksella." }, "TempChangeLongStep": { "displayText": "Lämmön muutos\npitkä painal.", "description": "Lämpötilan muutos pitkällä painalluksella." }, "LockingMode": { "displayText": "Salli nappien\nlukitus", "description": "Kolvatessa paina molempia näppäimiä lukitaksesi ne (V=vain tehostus | K=kaikki)" }, "ProfilePhases": { "displayText": "Profiili\nvaiheet", "description": "Vaiheiden määrä profiilitilassa." }, "ProfilePreheatTemp": { "displayText": "Esilämmityksen\nlämpötila", "description": "Esilämmittää tähän lämpötilaan profiilitilan alussa." }, "ProfilePreheatSpeed": { "displayText": "Esilämmityksen\nnopeus", "description": "Esilämmityksen nopeus (asteita/sekunti)" }, "ProfilePhase1Temp": { "displayText": "Vaiheen 1\nTemp", "description": "Kohdelämpötila tämän vaiheen lopussa." }, "ProfilePhase1Duration": { "displayText": "Vaiheen 1\nkesto", "description": "Tämän vaiheen ajankäyttö (sekunteina) Saattaa kestää kauemmin jos lämmitys hitaampaa." }, "ProfilePhase2Temp": { "displayText": "Vaiheen 2\nlämpötila", "description": "Kohdelämpötila tämän vaiheen lopussa." }, "ProfilePhase2Duration": { "displayText": "Vaiheen 2\nkesto", "description": "Tämän vaiheen ajankäyttö (sekunteina) Saattaa kestää kauemmin jos lämmitys hitaampaa." }, "ProfilePhase3Temp": { "displayText": "Vaiheen 3\nlämpötila", "description": "Kohdelämpötila tämän vaiheen lopussa." }, "ProfilePhase3Duration": { "displayText": "Vaiheen 3\nkesto", "description": "Tämän vaiheen ajankäyttö (sekunteina) Saattaa kestää kauemmin jos lämmitys hitaampaa." }, "ProfilePhase4Temp": { "displayText": "Vaiheen 4\nlämpötila", "description": "Kohdelämpötila tämän vaiheen lopussa." }, "ProfilePhase4Duration": { "displayText": "Vaiheen 4\nkesto", "description": "Tämän vaiheen ajankäyttö (sekunteina) Saattaa kestää kauemmin jos lämmitys hitaampaa." }, "ProfilePhase5Temp": { "displayText": "Vaiheen 5\nlämpötila", "description": "Kohdelämpötila tämän vaiheen lopussa." }, "ProfilePhase5Duration": { "displayText": "Vaiheen 5\nkesto", "description": "Tämän vaiheen ajankäyttö (sekunteina) Saattaa kestää kauemmin jos lämmitys hitaampaa." }, "ProfileCooldownSpeed": { "displayText": "Jäähtymis\nnopeus", "description": "Jäähtymisnopeus profiilitilan lopussa (asteita sekunnissa)" }, "MotionSensitivity": { "displayText": "Liikkeen\nherkkyys", "description": "1=vähäinen herkkyys | ... | 9=suurin herkkyys" }, "SleepTemperature": { "displayText": "Lepotilan\nlämpötila", "description": "Kärjen lämpötila \"lepotilassa\"" }, "SleepTimeout": { "displayText": "Lepotilan\nviive", "description": "\"Lepotilan\" ajastus (s=sekuntia | m=minuuttia)" }, "ShutdownTimeout": { "displayText": "Sammutus\nviive", "description": "Automaattisen sammutuksen ajastus (m=minuuttia)" }, "HallEffSensitivity": { "displayText": "Hall-\nherk.", "description": "Hall-efektianturin herkkyys lepotilan tunnistuksessa (1=vähäinen herkkyys | ... | 9=suurin herkkyys)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Aikaväli ennen \"lepotilaa\" alkaa, kun hall-efekti ylittää kynnyksen" }, "TemperatureUnit": { "displayText": "Lämpötilan\nyksikkö", "description": "C=celsius, F=fahrenheit" }, "DisplayRotation": { "displayText": "Näytön\nkierto", "description": "O=oikeakätinen | V=vasenkätinen | A=automaattinen" }, "CooldownBlink": { "displayText": "Jäähdytyksen\nvilkutus", "description": "Vilkuttaa jäähtyessä juotoskärjen lämpötilaa sen ollessa vielä vaarallisen kuuma" }, "ScrollingSpeed": { "displayText": "Selityksien\nnopeus", "description": "Selityksien vieritysnopeus (H=hidas | N=nopea)" }, "ReverseButtonTempChange": { "displayText": "Suunnanvaihto\n+ - näppäimille", "description": "Lämpötilapainikkeiden suunnan vaihtaminen" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Animaation\nnopeus", "description": "Animaatioiden nopeus valikossa (A=alhainen | K=keskiverto | S=suuri)" }, "AnimLoop": { "displayText": "Animaation\ntoistaminen", "description": "Toista animaatiot valikossa." }, "Brightness": { "displayText": "Näytön\nkirkkaus", "description": "Säädä OLED-näytön kirkkautta." }, "ColourInversion": { "displayText": "Käänteiset\nvärit", "description": "Asettaa käänteiset värit OLED-näyttöön." }, "LOGOTime": { "displayText": "Käynnistysl\naika näytöllä", "description": "Aseta käynnistyslogon aika näytöllä (s=sekunteja)" }, "AdvancedIdle": { "displayText": "Tiedot\nlepotilassa", "description": "Näyttää yksityiskohtaisemmat tiedot pienellä fontilla lepotilassa." }, "AdvancedSoldering": { "displayText": "Tarkempi\njuotosnäyttö", "description": "Näyttää yksityiskohtaisemmat tiedot pienellä fontilla juotostilassa" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "BLE käyttöön." }, "PowerLimit": { "displayText": "Tehon-\nrajoitus", "description": "Suurin sallittu teho (Watti)" }, "CalibrateCJC": { "displayText": "Kalibroi CJC\nensi käynnist", "description": "Ensi käynnistyksessä kärjen Cold Junction Compensation kalibroidaan (ei tarpeellista jos Delta T on < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibroi\ntulojännite?", "description": "Tulojännitteen kalibrointi (VIN) (paina pitkään poistuaksesi)" }, "PowerPulsePower": { "displayText": "Herätyspulssin\nvoimakkuus", "description": "Herätyspulssin voimakkuus (Watteina)" }, "PowerPulseWait": { "displayText": "Pulssin\nodotusaika", "description": "Odotusaika herätyspulssin lähetykseen (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Pulssin\nkesto", "description": "Herätyspulssin kesto (x 250ms)" }, "SettingsReset": { "displayText": "Palauta\ntehdasasetukset?", "description": "Palauta kaikki asetukset oletusarvoihin" }, "LanguageSwitch": { "displayText": "Kieli:\n FI Suomi", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_FR.json ================================================ { "languageCode": "FR", "languageLocalName": "Français", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Étalonnage\nterminé !" }, "ResetOKMessage": { "message": "Réin. OK" }, "SettingsResetMessage": { "message": "Réglages\nréinitialisés !" }, "NoAccelerometerMessage": { "message": "Accéléromètre\nnon détecté !" }, "NoPowerDeliveryMessage": { "message": "USB-PD\nnon détecté !" }, "LockingKeysString": { "message": "Verr." }, "UnlockingKeysString": { "message": "Déverr." }, "WarningKeysLockedString": { "message": "! VERR. !" }, "WarningThermalRunaway": { "message": "Surchauffe\ncritique" }, "WarningTipShorted": { "message": "!Court-circuit Panne!" }, "SettingsCalibrationWarning": { "message": "Avant de redémarrer, assurez-vous que la panne et la poignée sont à température ambiante !" }, "CJCCalibrating": { "message": "Étalonnage\n" }, "SettingsResetWarning": { "message": "Voulez-vous vraiment réinitialiser les paramètres aux valeurs par défaut ?" }, "UVLOWarningString": { "message": "DC FAIBLE" }, "UndervoltageString": { "message": "Sous-tension\n" }, "InputVoltageString": { "message": "Tension:\n" }, "SleepingAdvancedString": { "message": "En veille...\n" }, "SleepingTipAdvancedString": { "message": "Panne:\n" }, "ProfilePreheatString": { "message": "Préchauffage\n" }, "ProfileCooldownString": { "message": "Refroidissement\n" }, "DeviceFailedValidationWarning": { "message": "Votre appareil semble être une contrefaçon !" }, "TooHotToStartProfileWarning": { "message": "Trop chaud pour\nactiver le profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "G", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "R", "SettingStartSolderingChar": "A", "SettingStartSleepChar": "V", "SettingStartSleepOffChar": "O", "SettingLockBoostChar": "B", "SettingLockFullChar": "V" }, "menuGroups": { "PowerMenu": { "displayText": "Paramètres\nd'alim.", "description": "" }, "SolderingMenu": { "displayText": "Paramètres\nde soudure", "description": "" }, "PowerSavingMenu": { "displayText": "Mode\nveille", "description": "" }, "UIMenu": { "displayText": "Interface\nutilisateur", "description": "" }, "AdvancedMenu": { "displayText": "Options\navancées", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Mode\npar Défaut" }, "USBPDModeNoDynamic": { "displayText": "Non\nDynamique" }, "USBPDModeSafe": { "displayText": "Mode\nSécurisé" }, "TipTypeAuto": { "displayText": "Détéction\nAuto." }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nCourt" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Source\nd'alim.", "description": "Source d'alimentation. Définit la tension de coupure (DC 10V) (S 3.3V par cellule, désactive la limite de puissance)" }, "MinVolCell": { "displayText": "Tension\nminimale", "description": "Tension minimale autorisée par cellule (3S : 3 - 3.7V | 4-6S : 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Tension\nQC", "description": "Tension maximale désirée avec une alimentation QC" }, "PDNegTimeout": { "displayText": "Délai\nexpir. PD", "description": "Délai de négociation PD par paliers de 100ms pour la compatibilité avec certains chargeurs QC" }, "USBPDMode": { "displayText": "Mode\nPD", "description": "Le mode Non Dynamique désactive EPR & PPS, le mode Sécurisé n'utilise pas de résistance à la protection" }, "BoostTemperature": { "displayText": "Temp.\nboost", "description": "Température utilisée en \"mode boost\"" }, "AutoStart": { "displayText": "Chauffer\nau démarrage", "description": "A=activé | V=mode veille | O=mode veille à température ambiante" }, "TempChangeShortStep": { "displayText": "Incrément\nappui court", "description": "Incrément de changement de température sur appui court" }, "TempChangeLongStep": { "displayText": "Incrément\nappui long", "description": "Incrément de changement de température sur appui long" }, "LockingMode": { "displayText": "Verrouiller\nles boutons", "description": "Pendant la soudure, appuyer sur les deux boutons pour les verrouiller (B=boost seulement | V=verr. total)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Nombre de phases dans le mode de profile" }, "ProfilePreheatTemp": { "displayText": "Temp.\nPréchauffage", "description": "Préchauffer à cette température au début du mode de profile" }, "ProfilePreheatSpeed": { "displayText": "Vitesse\nPréchauffage", "description": "Préchauffer à cette vitesse (degrés par seconde)" }, "ProfilePhase1Temp": { "displayText": "Temp.\nPhase 1", "description": "Température séléctionnée pour la fin de cette phase" }, "ProfilePhase1Duration": { "displayText": "Durée\nPhase 1", "description": "Durée séléctionnée pour cette phase (secondes)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Vitesse de\nRefroidissement", "description": "Refroidissement à ce rythme à la fin du mode profil (degrés par seconde)" }, "MotionSensitivity": { "displayText": "Sensibilité\nau mouvement", "description": "1=très peu sensible | ... | 9=extrêmement sensible" }, "SleepTemperature": { "displayText": "Temp.\nveille", "description": "Température de la panne en \"mode veille\"" }, "SleepTimeout": { "displayText": "Délai\nveille", "description": "Délai avant mise en veille (s=secondes | m=minutes)" }, "ShutdownTimeout": { "displayText": "Délai\narrêt", "description": "Délai avant l'arrêt du fer à souder (m=minutes)" }, "HallEffSensitivity": { "displayText": "Sensibilité capteur\neffet hall", "description": "Sensibilité du capteur à effet Hall pour la mise en veille (1=peu sensible | ... | 9=très sensible)" }, "HallEffSleepTimeout": { "displayText": "Temps de veille\ncapteur effet hall", "description": "Intervalle avant le démarrage du \"mode veille\" lorsque l'effet Hall est supérieur au seuil" }, "TemperatureUnit": { "displayText": "Unité de\ntempérature", "description": "C=Celsius | F=Fahrenheit" }, "DisplayRotation": { "displayText": "Orientation\nde l'écran", "description": "D=droitier | G=gaucher | A=automatique" }, "CooldownBlink": { "displayText": "Refroidir en\nclignotant", "description": "Faire clignoter la température lors du refroidissement tant que la panne est chaude" }, "ScrollingSpeed": { "displayText": "Vitesse\nde défilement", "description": "Vitesse de défilement du texte (R=rapide | L=lent)" }, "ReverseButtonTempChange": { "displayText": "Inverser les\ntouches + -", "description": "Inverser les boutons d'ajustement de température" }, "ReverseButtonSettings": { "displayText": "Inverser les\ntouches A B", "description": "Inverser les boutons pour le menu Paramètres" }, "AnimSpeed": { "displayText": "Vitesse\nanim. icônes", "description": "Vitesse des animations des icônes dans le menu (L=lente | M=moyenne | R=rapide)" }, "AnimLoop": { "displayText": "Rejouer\nanim. icônes", "description": "Rejouer en boucle les animations des icônes dans le menu principal" }, "Brightness": { "displayText": "Luminosité\nde l'écran", "description": "Ajuster la luminosité de l'écran OLED" }, "ColourInversion": { "displayText": "Inverser\nles couleurs", "description": "Inverser les couleurs de l'écran OLED" }, "LOGOTime": { "displayText": "Durée logo\ndémarrage", "description": "Définit la durée d'affichage du logo au démarrage (s=secondes)" }, "AdvancedIdle": { "displayText": "Écran veille\ndétaillé", "description": "Afficher les informations détaillées sur l'écran de veille" }, "AdvancedSoldering": { "displayText": "Écran soudure\ndétaillé", "description": "Afficher les informations détaillées sur l'écran de soudure" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Activer le bluetooth basse consommation" }, "PowerLimit": { "displayText": "Limite de\npuissance", "description": "Puissance maximale utilisable (W=watts)" }, "CalibrateCJC": { "displayText": "Étalonner CJC\nau reboot", "description": "Au prochain démarrage, la compensation de soudure froide (CJC) sera calibrée (non nécessaire si Delta T est < 5°C)." }, "VoltageCalibration": { "displayText": "Étalonner\ntension d'entrée", "description": "Étalonner tension d'entrée (appui long pour quitter)" }, "PowerPulsePower": { "displayText": "Puissance\nimpulsions", "description": "Puissance des impulsions pour éviter la mise en veille des batteries (watts)" }, "PowerPulseWait": { "displayText": "Délai entre\nles impulsions", "description": "Délai entre chaque impulsion pour empêcher la mise en veille (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Durée des\nimpulsions", "description": "Durée des impulsions pour empêcher la mise en veille (x 250ms)" }, "SettingsReset": { "displayText": "Réinitialisation\nd'usine", "description": "Réinitialiser tous les réglages" }, "LanguageSwitch": { "displayText": "Langue:\n FR Français", "description": "" }, "SolderingTipType": { "displayText": "Type\nde panne", "description": "Séléctionner le type de panne utilisé" } } } ================================================ FILE: Translations/translation_HR.json ================================================ { "languageCode": "HR", "languageLocalName": "Hrvatski", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibracija\ndovršena!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Neke postavke\nsu izmijenjene!" }, "NoAccelerometerMessage": { "message": "Akcelerometar\nnije pronađen!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\nnije pronađen!" }, "LockingKeysString": { "message": "ZAKLJUČ" }, "UnlockingKeysString": { "message": "OTKLJUČ" }, "WarningKeysLockedString": { "message": "ZAKLJUČ!" }, "WarningThermalRunaway": { "message": "Neispravan\ngrijač" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Prije restarta provjerite da su vrh i ručka na sobnoj temperaturi!" }, "CJCCalibrating": { "message": "kalibriram\n" }, "SettingsResetWarning": { "message": "Jeste li sigurni da želite sve postavke vratiti na tvorničke vrijednosti?" }, "UVLOWarningString": { "message": "BAT!!!" }, "UndervoltageString": { "message": "PRENIZAK NAPON\n" }, "InputVoltageString": { "message": "Napon V: \n" }, "SleepingAdvancedString": { "message": "SPAVAM...\n" }, "SleepingTipAdvancedString": { "message": "Vrh: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Vaš uređaj je najvjerojatnije krivotvoren!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "B", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "T", "SettingStartSleepOffChar": "H", "SettingLockBoostChar": "B", "SettingLockFullChar": "Z" }, "menuGroups": { "PowerMenu": { "displayText": "Postavke\nnapajanja", "description": "" }, "SolderingMenu": { "displayText": "Postavke\nlemljenja", "description": "" }, "PowerSavingMenu": { "displayText": "Ušteda\nenergije", "description": "" }, "UIMenu": { "displayText": "Korisničko\nsučelje", "description": "" }, "AdvancedMenu": { "displayText": "Napredne\nopcije", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Izvor\nnapajanja", "description": "Izvor napajanja. Postavlja napon isključivanja. (DC 10V) (S 3.3V po ćeliji)" }, "MinVolCell": { "displayText": "Najniži\nnapon", "description": "Najniži dozvoljeni napon po ćeliji baterije (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Snaga\nnapajanja", "description": "Snaga modula za napajanje" }, "PDNegTimeout": { "displayText": "USB-PD\ntimeout", "description": "Timeout za USB-Power Delivery u koracima od 100ms za kompatibilnost s nekim QC punjačima" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Boost\ntemp", "description": "Temperatura u pojačanom (Boost) načinu." }, "AutoStart": { "displayText": "Auto\nstart", "description": "Ako je aktivno, lemilica po uključivanju napajanja odmah počinje grijati. (L=lemljenje | T=spavanje toplo | H=spavanje hladno)" }, "TempChangeShortStep": { "displayText": "Korak temp\nkratki pritisak", "description": "Korak temperature pri kratkom pritisku tipke" }, "TempChangeLongStep": { "displayText": "Korak temp\ndugi pritisak", "description": "Korak temperature pri dugačkom pritisku tipke" }, "LockingMode": { "displayText": "Zaključavanje\ntipki", "description": "Tokom lemljenja, držite obje tipke kako biste ih zaključali ili otključali (B=zaključan boost | Z=zaključano sve)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Osjetljivost\npokreta", "description": "Osjetljivost prepoznavanja pokreta. (1=najmanje osjetljivo | ... | 9=najosjetljivije)" }, "SleepTemperature": { "displayText": "Temp\nspavanja", "description": "Temperatura na koju se spušta lemilica nakon određenog vremena mirovanja (C | F)" }, "SleepTimeout": { "displayText": "Vrijeme\nspavanja", "description": "Vrijeme mirovanja nakon kojega lemilica spušta temperaturu. (Minute | Sekunde)" }, "ShutdownTimeout": { "displayText": "Vrijeme\ngašenja", "description": "Vrijeme mirovanja nakon kojega će se lemilica ugasiti (Minute)" }, "HallEffSensitivity": { "displayText": "Osjetljivost\nHall senzora", "description": "Osjetljivost senzora magnetskog polja za detekciju spavanja (N=Najmanja | S=Srednja | V=Visoka)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval prije pokretanja \"načina mirovanja\" kada je Hall efekt iznad praga" }, "TemperatureUnit": { "displayText": "Jedinica\ntemperature", "description": "Jedinica temperature (C=Celzij | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Rotacija\nekrana", "description": "Orijentacija ekrana (D=desnoruki | L=ljevoruki | A=automatski)" }, "CooldownBlink": { "displayText": "Upozorenje\npri hlađenju", "description": "Bljeskanje temperature prilikom hlađenja, ako je lemilica vruća" }, "ScrollingSpeed": { "displayText": "Brzina\nporuka", "description": "Brzina kretanja dugačkih poruka (B=brzo | S=sporo)" }, "ReverseButtonTempChange": { "displayText": "Zamjena\n+ - tipki", "description": "Zamjenjuje funkciju gornje i donje tipke za podešavanje temperature" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Brzina\nanimacije", "description": "Brzina animacije ikona u menijima (S=sporo | M=srednje | B=brzo)" }, "AnimLoop": { "displayText": "Ponavljanje\nanimacije", "description": "Hoće li se animacije menija vrtiti u petlji - samo ako brzina animacije nije na \"Ugašeno\"" }, "Brightness": { "displayText": "Svjetlina\nekrana", "description": "Podešavanje svjetline OLED ekrana. Veća svjetlina može dugotrajno dovesti do pojave duhova na ekranu." }, "ColourInversion": { "displayText": "Inverzija\nekrana", "description": "Inverzan prikaz slike na ekranu" }, "LOGOTime": { "displayText": "Trajanje\nboot logotipa", "description": "Trajanje prikaza boot logotipa (s=seconds)" }, "AdvancedIdle": { "displayText": "Detalji\npri čekanju", "description": "Prikazivanje detaljnih informacija tijekom čekanja" }, "AdvancedSoldering": { "displayText": "Detalji\npri lemljenju", "description": "Prikazivanje detaljnih informacija tijekom lemljenja" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Ograničenje\nsnage", "description": "Najveća snaga koju lemilica smije vući iz napajanja (W=watt)" }, "CalibrateCJC": { "displayText": "Kalibracija kod\nsljed. starta", "description": "Kod sljedećeg starta izvršit će se kalibracija (nije potrebno ako je pogreška manja od 5°C)" }, "VoltageCalibration": { "displayText": "Kalibracija\nnapajanja", "description": "Kalibracija ulaznog napona napajanja (Podešavanje tipkama, dugački pritisak za kraj)" }, "PowerPulsePower": { "displayText": "Snaga period.\npulsa napajanja", "description": "Intenzitet periodičkog pulsa kojega lemilica povlači kako se USB napajanje ne bi ugasilo (W=watt)" }, "PowerPulseWait": { "displayText": "Interval per.\npulsa nap.", "description": "Razmak periodičkih pulseva koje lemilica povlači kako se USB napajanje ne bi ugasilo (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Trajanje per.\npulsa nap.", "description": "Trajanje periodičkog pulsa kojega lemilica povlači kako se USB napajanje ne bi ugasilo (x 250ms)" }, "SettingsReset": { "displayText": "Tvorničke\npostavke", "description": "Vraćanje svih postavki na tvorničke vrijednosti" }, "LanguageSwitch": { "displayText": "Jezik:\n HR Hrvatski", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_HU.json ================================================ { "languageCode": "HU", "languageLocalName": "Magyar", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibráció\nkész!" }, "ResetOKMessage": { "message": "Törlés OK" }, "SettingsResetMessage": { "message": "Beállítások\nvisszaállítva!" }, "NoAccelerometerMessage": { "message": "Nincs\ngyorsulásmérő!" }, "NoPowerDeliveryMessage": { "message": "Nincs\nUSB-PD IC!" }, "LockingKeysString": { "message": "LEZÁRVA" }, "UnlockingKeysString": { "message": "FELOLDVA" }, "WarningKeysLockedString": { "message": "!LEZÁRVA!" }, "WarningThermalRunaway": { "message": "Kontrollálatlan\nhőmérséklet!" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Újraindítás előtt a hegy és az eszköz legyen szobahőmérsékletű!" }, "CJCCalibrating": { "message": "Kalibrálás\n" }, "SettingsResetWarning": { "message": "Biztos visszaállítja a beállításokat alapértékekre?" }, "UVLOWarningString": { "message": "DC túl alacsony" }, "UndervoltageString": { "message": "Alulfeszültség\n" }, "InputVoltageString": { "message": "Bemenet V: \n" }, "SleepingAdvancedString": { "message": "Alvás...\n" }, "SleepingTipAdvancedString": { "message": "Hegy: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Az eszköz valószínűleg nem eredeti!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "J", "SettingLeftChar": "B", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "K", "SettingFastChar": "Gy", "SettingStartSolderingChar": "F", "SettingStartSleepChar": "A", "SettingStartSleepOffChar": "Sz", "SettingLockBoostChar": "B", "SettingLockFullChar": "T" }, "menuGroups": { "PowerMenu": { "displayText": "Táp\nbeállítások", "description": "" }, "SolderingMenu": { "displayText": "Forrasztási\nbeállítások", "description": "" }, "PowerSavingMenu": { "displayText": "Alvási\nmódok", "description": "" }, "UIMenu": { "displayText": "Felhasználói\nfelület", "description": "" }, "AdvancedMenu": { "displayText": "Haladó\nbeállítások", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Áram\nforrás", "description": "Kikapcsolási feszültség beállítása (DC:10V | S:3.3V/LiPo cella | ki)" }, "MinVolCell": { "displayText": "Minimum\nfeszültség", "description": "Minimális engedélyezett cellafeszültség (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Max. USB\nfeszültség", "description": "Maximális USB feszültség (QuickCharge)" }, "PDNegTimeout": { "displayText": "PD\nidőtúllépés", "description": "PD egyeztetés időkerete (kompatibilitás QC töltőkkel) (x 100ms)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Boost\nhőmérséklet", "description": "Hőmérséklet \"boost\" módban" }, "AutoStart": { "displayText": "Automatikus\nindítás", "description": "Bekapcsolás után automatikusan lépjen forrasztás módba (F=forrasztás | A=alvó mód | Sz=szobahőmérséklet)" }, "TempChangeShortStep": { "displayText": "Hőm. állítás\nrövid", "description": "Hőmérséklet állítás rövid gombnyomásra (C | F)" }, "TempChangeLongStep": { "displayText": "Hőm. állítás\nhosszú", "description": "Hőmérséklet állítás hosszú gombnyomásra (C | F)" }, "LockingMode": { "displayText": "Lezárás\nengedélyezés", "description": "Forrasztás közben mindkét gombot hosszan lenyomva lezárja a kezelést (B=csak \"boost\" módban | T=teljes lezárás)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Mozgás\nérzékenység", "description": "Mozgás érzékenység beállítása (1=legkevésbé érzékeny | ... | 9=legérzékenyebb)" }, "SleepTemperature": { "displayText": "Alvási\nhőmérséklet", "description": "Hőmérséklet alvó módban (C | F)" }, "SleepTimeout": { "displayText": "Alvás\nidőzítő", "description": "Alvási időzítő (perc | másodperc)" }, "ShutdownTimeout": { "displayText": "Kikapcsolás\nidőzítő", "description": "Kikapcsolási időzítő (perc)" }, "HallEffSensitivity": { "displayText": "Alvásérzékelő\nérzékenység", "description": "Alvásérzékelő gyorsulásmérő érzékenysége (1=legkevésbé érzékeny | ... | 9=legérzékenyebb)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Az \"alvó üzemmód\" előtti intervallum akkor kezdődik, amikor a hall-effektus meghaladja a küszöbértéket" }, "TemperatureUnit": { "displayText": "Hőmérséklet\nmértékegysége", "description": "Hőmérséklet mértékegysége (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Kijelző\ntájolása", "description": "Kijelző tájolása (J=jobbkezes | B=balkezes | A=automatikus)" }, "CooldownBlink": { "displayText": "Villogás\nhűléskor", "description": "Villogjon a hőmérséklet kijelzése hűlés közben, amíg a forrasztó hegy forró" }, "ScrollingSpeed": { "displayText": "Görgetés\nsebessége", "description": "Szöveggörgetés sebessége" }, "ReverseButtonTempChange": { "displayText": "+/- gomb\nmegfordítása", "description": "Forrasztó hegy hőmérsékletállító gombok felcserélése" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Animáció\nsebessége", "description": "Menüikonok animációjának sebessége (L=lassú | K=közepes | Gy=gyors)" }, "AnimLoop": { "displayText": "Folytonos\nanimáció", "description": "Főmenü ikonjainak folytonos animációja" }, "Brightness": { "displayText": "Képernyő\nkontraszt", "description": "Képernyő kontrasztjának állítása" }, "ColourInversion": { "displayText": "Képernyő\ninvertálás", "description": "Képernyő színeinek invertálása" }, "LOGOTime": { "displayText": "Boot logo\nmegjelenítés", "description": "Boot logo megjelenítési idejének beállítása (s=seconds)" }, "AdvancedIdle": { "displayText": "Részletes\nkészenlét", "description": "Részletes információk megjelenítése kisebb betűméretben a készenléti képernyőn" }, "AdvancedSoldering": { "displayText": "Részletes\nforrasztás infó", "description": "Részletes információk megjelenítése forrasztás közben" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Teljesítmény\nmaximum", "description": "Maximális felvett teljesitmény beállitása" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nköv. indításnál", "description": "Következő indításnál a hegy Cold Junction Compensation kalibrálása (nem szükséges ha Delta T kisebb mint 5°C)" }, "VoltageCalibration": { "displayText": "Bemeneti fesz.\nkalibrálása?", "description": "Bemeneti feszültség kalibrálása (hosszan nyomva kilép)" }, "PowerPulsePower": { "displayText": "Ébr. pulzus\nnagysága", "description": "Powerbankot ébrentartó áramfelvételi pulzusok nagysága (W)" }, "PowerPulseWait": { "displayText": "Ébr. pulzus\nidőköze", "description": "Powerbankot ébrentartó áramfelvételi pulzusok időköze (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Ébr. pulzus\nidőtartama", "description": "Powerbankot ébrentartó áramfelvételi pulzusok időtartama (x 250ms)" }, "SettingsReset": { "displayText": "Gyári\nbeállítások?", "description": "Beállítások alaphelyzetbe állítása" }, "LanguageSwitch": { "displayText": "Nyelv:\n HU Magyar", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_IT.json ================================================ { "languageCode": "IT", "languageLocalName": "Italiano", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibrazione\ncompletata!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Impostazioni\nripristinate" }, "NoAccelerometerMessage": { "message": "Accelerometro\nnon rilevato" }, "NoPowerDeliveryMessage": { "message": "USB PD\nnon rilevato" }, "LockingKeysString": { "message": "Blocc." }, "UnlockingKeysString": { "message": "Sblocc." }, "WarningKeysLockedString": { "message": "BLOCCATO" }, "WarningThermalRunaway": { "message": "Temperatura\nfuori controllo" }, "WarningTipShorted": { "message": "Punta in cortocircuito!" }, "SettingsCalibrationWarning": { "message": "Prima di riavviare assicurati che la punta e l'impugnatura siano a temperatura ambiente!" }, "CJCCalibrating": { "message": "Calibrazione in corso\n" }, "SettingsResetWarning": { "message": "Ripristinare le impostazioni predefinite?" }, "UVLOWarningString": { "message": "DC BASSA" }, "UndervoltageString": { "message": "DC INSUFFICIENTE\n" }, "InputVoltageString": { "message": "V in: \n" }, "SleepingAdvancedString": { "message": "Riposo\n" }, "SleepingTipAdvancedString": { "message": "Punta: \n" }, "ProfilePreheatString": { "message": "Preriscaldamento\n" }, "ProfileCooldownString": { "message": "Raffreddamento\n" }, "DeviceFailedValidationWarning": { "message": "È probabile che questo dispositivo sia contraffatto!" }, "TooHotToStartProfileWarning": { "message": "Troppo caldo\nper il profilo" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "S", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "V", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "R", "SettingStartSleepOffChar": "A", "SettingLockBoostChar": "T", "SettingLockFullChar": "C" }, "menuGroups": { "PowerMenu": { "displayText": "Opzioni\nalimentaz", "description": "" }, "SolderingMenu": { "displayText": "Opzioni\nsaldatura", "description": "" }, "PowerSavingMenu": { "displayText": "Risparmio\nenergetico", "description": "" }, "UIMenu": { "displayText": "Interfaccia\nutente", "description": "" }, "AdvancedMenu": { "displayText": "Opzioni\navanzate", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Modalità\npredefinita" }, "USBPDModeNoDynamic": { "displayText": "Modalità\nstatica" }, "USBPDModeSafe": { "displayText": "Modalità\nsicura" }, "TipTypeAuto": { "displayText": "Rilevaz.\nauto" }, "TipTypeT12Long": { "displayText": "TS100\nlunga" }, "TipTypeT12Short": { "displayText": "Pine\ncorta" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Sorgente\nalimentaz", "description": "Imposta una tensione minima di alimentazione attraverso la selezione di una sorgente [DC: 10 V; 3S/4S/5S/6S: 3,3 V per cella]" }, "MinVolCell": { "displayText": "Tensione\nmin celle", "description": "Modifica la tensione di minima carica delle celle di una batteria Li-Po [3S: 3,0-3,7 V; 4S/5S/6S: 2,4-3,7 V]" }, "QCMaxVoltage": { "displayText": "Tensione\nQC", "description": "Imposta la massima tensione negoziabile con un alimentatore Quick Charge [volt]" }, "PDNegTimeout": { "displayText": "Abilitazione\nUSB PD", "description": "Imposta il tempo di negoziazione del protocollo USB Power Delivery con alimentatori compatibili [0: disattiva; multipli di 100 ms]" }, "USBPDMode": { "displayText": "Modalità\nUSB PD", "description": "Abilita le modalità Power Delivery PPS ed EPR" }, "BoostTemperature": { "displayText": "Temp\nturbo", "description": "Imposta la temperatura della funzione turbo [°C/°F]" }, "AutoStart": { "displayText": "Avvio\nautomatico", "description": "Attiva automaticamente il saldatore quando viene alimentato [S: saldatura; R: riposo; A: temperatura ambiente]" }, "TempChangeShortStep": { "displayText": "Temp passo\nbreve", "description": "Imposta il passo dei valori di temperatura per una breve pressione dei tasti" }, "TempChangeLongStep": { "displayText": "Temp passo\nlungo", "description": "Imposta il passo dei valori di temperatura per una lunga pressione dei tasti" }, "LockingMode": { "displayText": "Blocco\ntasti", "description": "Blocca i tasti durante la modalità saldatura; tieni premuto entrambi per bloccare o sbloccare [T: consenti Turbo; C: blocco completo]" }, "ProfilePhases": { "displayText": "Fasi modalità\nprofilo", "description": "Imposta il numero di fasi da implementare per un profilo di riscaldamento personalizzato" }, "ProfilePreheatTemp": { "displayText": "Temperatura\npreriscaldamento", "description": "Imposta la temperatura di preriscaldamento da raggiungere all'inizio del profilo di riscaldamento" }, "ProfilePreheatSpeed": { "displayText": "Velocità\npreriscaldamento", "description": "Imposta la velocità di preriscaldamento [°C/s]" }, "ProfilePhase1Temp": { "displayText": "Temperatura\nfase 1", "description": "Imposta la temperatura da raggiungere alla fine di questa fase" }, "ProfilePhase1Duration": { "displayText": "Durata\nfase 1", "description": "Imposta la durata di questa fase [secondi]" }, "ProfilePhase2Temp": { "displayText": "Temperatura\nfase 2", "description": "" }, "ProfilePhase2Duration": { "displayText": "Durata\nfase 2", "description": "" }, "ProfilePhase3Temp": { "displayText": "Temperatura\nfase 3", "description": "" }, "ProfilePhase3Duration": { "displayText": "Durata\nfase 3", "description": "" }, "ProfilePhase4Temp": { "displayText": "Temperatura\nfase 4", "description": "" }, "ProfilePhase4Duration": { "displayText": "Durata\nfase 4", "description": "" }, "ProfilePhase5Temp": { "displayText": "Temperatura\nfase 5", "description": "" }, "ProfilePhase5Duration": { "displayText": "Durata\nfase 5", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Velocità\nraffreddamento", "description": "Imposta la velocità di raffreddamento al termine del profilo di riscaldamento [°C/s]" }, "MotionSensitivity": { "displayText": "Sensibilità\nal movimento", "description": "Imposta la sensibilità al movimento per uscire dalla modalità riposo [1: minima; 9: massima]" }, "SleepTemperature": { "displayText": "Temperatura\nriposo", "description": "Imposta la temperatura da mantenere in modalità riposo [°C/°F]" }, "SleepTimeout": { "displayText": "Timer\nriposo", "description": "Imposta un timer per entrare in modalità riposo [secondi/minuti]" }, "ShutdownTimeout": { "displayText": "Timer\nspegnimento", "description": "Imposta un timer per lo spegnimento [minuti]" }, "HallEffSensitivity": { "displayText": "Sensore\nHall", "description": "Regola la sensibilità del sensore ad effetto Hall per entrare in modalità riposo [1: minima; 9: massima]" }, "HallEffSleepTimeout": { "displayText": "Timer\nHall", "description": "Imposta un timer per entrare in modalità riposo quando il sensore ad effetto Hall è al di sopra della soglia di attivazione [secondi]" }, "TemperatureUnit": { "displayText": "Unità di\ntemperatura", "description": "Scegli l'unità di misura per la temperatura [C: grado Celsius; F: grado Farenheit]" }, "DisplayRotation": { "displayText": "Orientamento\nschermo", "description": "Imposta l'orientamento dello schermo [D: mano destra; S: mano sinistra; A: automatico]" }, "CooldownBlink": { "displayText": "Avviso\npunta calda", "description": "Evidenzia il valore di temperatura durante il raffreddamento se la punta è ancora calda" }, "ScrollingSpeed": { "displayText": "Velocità\ntesto", "description": "Imposta la velocità di scorrimento del testo [L: lenta; V: veloce]" }, "ReverseButtonTempChange": { "displayText": "Inversione\ntasti", "description": "Inverti i tasti per aumentare o diminuire la temperatura della punta" }, "ReverseButtonSettings": { "displayText": "Inversione\ntasti A/B", "description": "Inverti il funzionamento dei tasti del saldatore all'interno del menù principale" }, "AnimSpeed": { "displayText": "Velocità\nanimazioni", "description": "Imposta la velocità di riproduzione delle animazioni del menù principale [L: lenta; M: media; V: veloce]" }, "AnimLoop": { "displayText": "Ciclo\nanimazioni", "description": "Abilita la riproduzione ciclica delle animazioni del menù principale" }, "Brightness": { "displayText": "Luminosità\nschermo", "description": "Regola la luminosità dello schermo [1: minimo; 10: massimo]" }, "ColourInversion": { "displayText": "Inverti\ncolori", "description": "Inverti i colori dello schermo" }, "LOGOTime": { "displayText": "Durata\nlogo", "description": "Imposta la permanenza sullo schermo del logo iniziale [secondi]" }, "AdvancedIdle": { "displayText": "Interfaccia\ntestuale", "description": "Mostra informazioni dettagliate all'interno della schermata principale" }, "AdvancedSoldering": { "displayText": "Dettagli\nsaldatura", "description": "Mostra informazioni dettagliate durante la modalità saldatura" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Abilita BLE" }, "PowerLimit": { "displayText": "Limite\npotenza", "description": "Imposta il valore di potenza massima erogabile al saldatore [watt]" }, "CalibrateCJC": { "displayText": "Calibra T\nall'avvio", "description": "Calibra le rilevazioni di temperatura al prossimo riavvio (non necessario se lo scarto di temperatura è minore di 5 °C)" }, "VoltageCalibration": { "displayText": "Calibrazione\ntensione", "description": "Calibra la tensione in ingresso; regola con entrambi i tasti, tieni premuto il tasto superiore per uscire" }, "PowerPulsePower": { "displayText": "Potenza\nimpulso", "description": "Regola la potenza di un segnale di attività per prevenire lo standby eventuale dell'alimentatore [watt]" }, "PowerPulseWait": { "displayText": "Distanza\nimpulsi", "description": "Imposta il tempo che deve intercorrere tra un segnale di attività e il successivo [multipli di 2,5 s]" }, "PowerPulseDuration": { "displayText": "Durata\nimpulso", "description": "Regola la durata del segnale di attività [multipli di 250 ms]" }, "SettingsReset": { "displayText": "Ripristino\nimpostazioni", "description": "Ripristina le impostazioni predefinite" }, "LanguageSwitch": { "displayText": "Lingua:\n IT Italiano", "description": "" }, "SolderingTipType": { "displayText": "Tipo di\npunta", "description": "Seleziona il modello della punta in uso" } } } ================================================ FILE: Translations/translation_JA_JP.json ================================================ { "languageCode": "JA_JP", "languageLocalName": "日本語", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "Calibration done!" }, "ResetOKMessage": { "message": "リセットOK" }, "SettingsResetMessage": { "message": "初期化されました" }, "NoAccelerometerMessage": { "message": "加速度計未検出" }, "NoPowerDeliveryMessage": { "message": "PD IC未検出" }, "LockingKeysString": { "message": "ボタンロック" }, "UnlockingKeysString": { "message": "ロックを解除" }, "WarningKeysLockedString": { "message": "!入力ロック中!" }, "WarningThermalRunaway": { "message": "過熱" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating" }, "SettingsResetWarning": { "message": "設定をリセットしますか？" }, "UVLOWarningString": { "message": "電圧が低すぎます" }, "UndervoltageString": { "message": "Undervoltage" }, "InputVoltageString": { "message": "Input V: " }, "SleepingAdvancedString": { "message": "Sleeping..." }, "SleepingTipAdvancedString": { "message": "Tip: " }, "ProfilePreheatString": { "message": "Preheat" }, "ProfileCooldownString": { "message": "Cooldown" }, "DeviceFailedValidationWarning": { "message": "このデバイスはおそらく偽造品です" }, "TooHotToStartProfileWarning": { "message": "Too hot to start profile" } }, "characters": { "SettingRightChar": "右", "SettingLeftChar": "左", "SettingAutoChar": "自", "SettingSlowChar": "遅", "SettingMediumChar": "中", "SettingFastChar": "速", "SettingStartSolderingChar": "熱", "SettingStartSleepChar": "待", "SettingStartSleepOffChar": "室", "SettingLockBoostChar": "ブ", "SettingLockFullChar": "全" }, "menuGroups": { "PowerMenu": { "displayText": "電源設定", "description": "" }, "SolderingMenu": { "displayText": "半田付け設定", "description": "" }, "PowerSavingMenu": { "displayText": "待機設定", "description": "" }, "UIMenu": { "displayText": "UI設定", "description": "" }, "AdvancedMenu": { "displayText": "高度な設定", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "下限電圧", "description": "下限電圧を指定する " }, "MinVolCell": { "displayText": "最低電圧", "description": "セルあたりの最低電圧 <ボルト> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>" }, "QCMaxVoltage": { "displayText": "QC電圧", "description": "QC電源使用時に要求する目標電圧" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "一部のQC電源との互換性のため、PDネゴシエーションをタイムアウトする時間 " }, "USBPDMode": { "displayText": "PD VPDO", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "ブースト温度", "description": "ブーストモードで使用される温度" }, "AutoStart": { "displayText": "自動加熱", "description": "電源投入時に自動的に加熱する <熱=半田付けモード | 待=スタンバイモード | 室=室温スタンバイモード>" }, "TempChangeShortStep": { "displayText": "温度変化 短", "description": "ボタンを短く押した時の温度変化値" }, "TempChangeLongStep": { "displayText": "温度変化 長", "description": "ボタンを長押しした時の温度変化値" }, "LockingMode": { "displayText": "ボタンロック", "description": "半田付けモード時に両方のボタンを長押しし、ボタンロックする <ブ=ブーストのみ許可 | 全=すべてをロック>" }, "ProfilePhases": { "displayText": "Profile Phases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat Temp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat Speed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1 Temp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1 Duration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2 Temp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2 Duration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3 Temp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3 Duration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4 Temp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4 Duration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5 Temp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5 Duration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown Speed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "動きの感度", "description": "1=最低感度 | ... | 9=最高感度" }, "SleepTemperature": { "displayText": "待機温度", "description": "スタンバイ時のコテ先温度" }, "SleepTimeout": { "displayText": "待機遅延", "description": "スタンバイモードに入るまでの待機時間 " }, "ShutdownTimeout": { "displayText": "自動オフ", "description": "自動電源オフまでの待機時間 " }, "HallEffSensitivity": { "displayText": "磁界感度", "description": "スタンバイモードに入るのに使用される磁場センサーの感度 <1=最低感度 | ... | 9=最高感度>" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "ホール効果が閾値を超えたときに\"「スリープモード」\"が開始されるまでの間隔" }, "TemperatureUnit": { "displayText": "温度単位", "description": "C=摂氏 | F=華氏" }, "DisplayRotation": { "displayText": "画面の向き", "description": "右=右利き | 左=左利き | 自=自動" }, "CooldownBlink": { "displayText": "冷却中に点滅", "description": "加熱の停止後、コテ先が熱い間は温度表示を点滅する" }, "ScrollingSpeed": { "displayText": "スクロール速度", "description": "テキストをスクロールする速さ <遅=遅い | 速=速い>" }, "ReverseButtonTempChange": { "displayText": "キー入れ替え", "description": "温度設定時に+ボタンと-ボタンを入れ替える" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "動画の速度", "description": "メニューアイコンのアニメーションの速さ <遅=低速 | 中=中速 | 速=高速>" }, "AnimLoop": { "displayText": "動画をループ", "description": "メニューアイコンのアニメーションをループする" }, "Brightness": { "displayText": "画面輝度", "description": "画面の明るさ・コントラストを変更する" }, "ColourInversion": { "displayText": "色反転", "description": "画面の色を反転する" }, "LOGOTime": { "displayText": "起動画面", "description": "起動画面の表示時間を設定する" }, "AdvancedIdle": { "displayText": "詳細な待受画面", "description": "待ち受け画面に詳細情報を表示する" }, "AdvancedSoldering": { "displayText": "詳細な作業画面", "description": "半田付け画面に詳細情報を表示する" }, "BluetoothLE": { "displayText": "Bluetooth", "description": "Enables BLE" }, "PowerLimit": { "displayText": "電力制限", "description": "最大電力を制限する " }, "CalibrateCJC": { "displayText": "Calibrate CJC", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5 C)" }, "VoltageCalibration": { "displayText": "電圧校正", "description": "入力電圧(VIN)の校正を開始する <長押しで終了>" }, "PowerPulsePower": { "displayText": "電力パルス", "description": "電源をオンに保つための電力パルス <ワット>" }, "PowerPulseWait": { "displayText": "パルス間隔", "description": "電源をオンに保つための電力パルスの時間間隔 " }, "PowerPulseDuration": { "displayText": "パルス時間長", "description": "電源をオンに保つための電力パルスの時間長 " }, "SettingsReset": { "displayText": "設定をリセット", "description": "すべての設定を初期化する" }, "LanguageSwitch": { "displayText": "言語： 日本語", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_LT.json ================================================ { "languageCode": "LT", "languageLocalName": "Lietuvių", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibravimas\natliktas!" }, "ResetOKMessage": { "message": "Atstatyta" }, "SettingsResetMessage": { "message": "Nust. \natstatyti!" }, "NoAccelerometerMessage": { "message": "Nerastas\nakselerometras!" }, "NoPowerDeliveryMessage": { "message": "Nerastas\nUSB-PD IC!" }, "LockingKeysString": { "message": "UŽRAKIN" }, "UnlockingKeysString": { "message": "ATRAKIN" }, "WarningKeysLockedString": { "message": "!UŽRAK!" }, "WarningThermalRunaway": { "message": "Perkaitimo\npavojus" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "Kalibruojama\n" }, "SettingsResetWarning": { "message": "Ar norite atstatyti nustatymus į numatytas reikšmes?" }, "UVLOWarningString": { "message": "MAŽ VOLT" }, "UndervoltageString": { "message": "Žema įtampa\n" }, "InputVoltageString": { "message": "Įvestis V: \n" }, "SleepingAdvancedString": { "message": "Miegu...\n" }, "SleepingTipAdvancedString": { "message": "Antg: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "K", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "V", "SettingFastChar": "G", "SettingStartSolderingChar": "T", "SettingStartSleepChar": "M", "SettingStartSleepOffChar": "K", "SettingLockBoostChar": "T", "SettingLockFullChar": "V" }, "menuGroups": { "PowerMenu": { "displayText": "Maitinimo\nnustatymai", "description": "" }, "SolderingMenu": { "displayText": "Litavimo\nnustatymai", "description": "" }, "PowerSavingMenu": { "displayText": "Miego\nrežimai", "description": "" }, "UIMenu": { "displayText": "Naudotojo\nsąsaja", "description": "" }, "AdvancedMenu": { "displayText": "Išplėsti.\nnustatymai", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Maitinimo\nšaltinis", "description": "Išjungimo įtampa. (DC 10V) (arba celių [S] kiekis [3.3V per celę])" }, "MinVolCell": { "displayText": "Minimalus\nvoltažas", "description": "Minimalus voltažas, kuris yra leidžiamas kiekvienam baterijos elementui (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC mait.\nįtampa", "description": "Maksimali QC maitinimo bloko įtampa" }, "PDNegTimeout": { "displayText": "PD\nlaikas", "description": "PD suderinimo laikas žingsniais po 100ms suderinamumui su kai kuriais QC įkrovikliais" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Turbo\ntemperat.", "description": "Temperatūra turbo režimu" }, "AutoStart": { "displayText": "Automatinis\npaleidimas", "description": "Ar pradėti kaitininti iš karto įjungus lituoklį (T=Taip | M=Miegas | K=Miegoti kambario temperatūroje)" }, "TempChangeShortStep": { "displayText": "Temp.keitim.\ntrump.spust.", "description": "Temperatūros keitimo žingsnis trumpai spustėlėjus mygtuką" }, "TempChangeLongStep": { "displayText": "Temp.keitim.\nilgas pasp.", "description": "Temperatūros keitimo žingsnis ilgai paspaudus mygtuką" }, "LockingMode": { "displayText": "Mygtukų\nužraktas", "description": "Lituodami, ilgai paspauskite abu mygtukus, kad juos užrakintumėte (T=leidžiamas tik Turbo režimas | V=Visiškas užrakinimas)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Judesio\njautrumas", "description": "Judesio jautrumas (1=Mažiausias | ... | 9=Didžiausias)" }, "SleepTemperature": { "displayText": "Miego\ntemperat.", "description": "Antgalio temperatūra miego režimu" }, "SleepTimeout": { "displayText": "Miego\nlaikas", "description": "Užmigimo laikas (sekundės | minutės)" }, "ShutdownTimeout": { "displayText": "Išjungimo\nlaikas", "description": "Išjungimo laikas (minutės)" }, "HallEffSensitivity": { "displayText": "Holo\njutiklis", "description": "Holo jutiklio jautrumas nustatant miegą (1=Mažiausias | ... | 9=Didžiausias)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Intervalas prieš \"miego režimą\" prasideda, kai salės efektas viršija slenkstį" }, "TemperatureUnit": { "displayText": "Temperatūros\nvienetai", "description": "Temperatūros vienetai (C=Celsijus | F=Farenheitas)" }, "DisplayRotation": { "displayText": "Ekrano\norientacija", "description": "Ekrano orientacija (D=Dešiniarankiams | K=Kairiarankiams | A=Automatinė)" }, "CooldownBlink": { "displayText": "Atvėsimo\nmirksėjimas", "description": "Ar mirksėti temperatūrą ekrane kol vėstantis antgalis vis dar karštas?" }, "ScrollingSpeed": { "displayText": "Aprašymo\ngreitis", "description": "Greitis, kuriuo šis tekstas slenka" }, "ReverseButtonTempChange": { "displayText": "Sukeisti + -\nmygtukus?", "description": "Sukeisti + - temperatūros keitimo mygtukus vietomis" }, "ReverseButtonSettings": { "displayText": "Sukeisti A B\nmygtukus?", "description": "Sukeisti nustatymų meniu mygtukus vietomis" }, "AnimSpeed": { "displayText": "Animacijų\ngreitis", "description": "Paveiksliukų animacijų greitis meniu punktuose (L=Lėtas | V=Vidutinis | G=Greitas)" }, "AnimLoop": { "displayText": "Animacijų\npakartojimas", "description": "Leidžia kartoti animacijas be sustojimo pagrindiniame meniu" }, "Brightness": { "displayText": "Ekrano\nšviesumas", "description": "Nustato OLED ekrano kontrastą/šviesumą." }, "ColourInversion": { "displayText": "Ekrano\ninvertavimas", "description": "Invertuoja OLED ekrano spalvas" }, "LOGOTime": { "displayText": "Įkrovos logotipo\ntrukmė", "description": "Nustatykite įkrovos logotipo trukmę (s=sekundės)" }, "AdvancedIdle": { "displayText": "Detalus lau-\nkimo ekranas", "description": "Ar rodyti papildomą informaciją mažesniu šriftu laukimo ekrane" }, "AdvancedSoldering": { "displayText": "Detalus lita-\nvimo ekranas", "description": "Ar rodyti išsamią informaciją lituojant" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Galios\nriba", "description": "Didžiausia galia, kurią gali naudoti lituoklis (Vatai)" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibruoti\nįvesties įtampą?", "description": "Įvesties įtampos kalibravimas. Trumpai paspauskite, norėdami nustatyti, ilgai paspauskite, kad išeitumėte." }, "PowerPulsePower": { "displayText": "Galios\npulso W", "description": "Periodinis galios pulso intensyvumas maitinblokiui, neleidžiantis jam užmigti." }, "PowerPulseWait": { "displayText": "Galios pulso\ndažnumas", "description": "Pasikartojantis laiko intervalas (x 2.5s), ties kuriuo kartojamas galios pulsas maitinblokiui, neleidžiantis jam užmigti" }, "PowerPulseDuration": { "displayText": "Galios pulso\ntrukmė", "description": "Galios pulso aktyvioji trukmė (x 250ms)" }, "SettingsReset": { "displayText": "Atstatyti\nnustatymus?", "description": "Nustato nustatymus į numatytuosius" }, "LanguageSwitch": { "displayText": "Kalba:\n LT Lietuvių", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_NB.json ================================================ { "languageCode": "NB", "languageLocalName": "Norsk bokmål", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Tilbakestilling OK" }, "SettingsResetMessage": { "message": "Noen innstillinger\nble endret!" }, "NoAccelerometerMessage": { "message": "Ingen akselerometer\nfunnet!" }, "NoPowerDeliveryMessage": { "message": "Ingen USB-PD IC\nfunnet!" }, "LockingKeysString": { "message": "LÅST" }, "UnlockingKeysString": { "message": "ÅPNET" }, "WarningKeysLockedString": { "message": "!LÅST!" }, "WarningThermalRunaway": { "message": "Termisk\nrømling" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Er du sikker på at du vil tilbakestille til standardinnstillinger?" }, "UVLOWarningString": { "message": "Lavspenn" }, "UndervoltageString": { "message": "Underspenning\n" }, "InputVoltageString": { "message": "Innspenn.: \n" }, "SleepingAdvancedString": { "message": "Dvale...\n" }, "SleepingTipAdvancedString": { "message": "Spiss: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Enheten din er sannsynligvis en forfalskning!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "H", "SettingLeftChar": "V", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "F", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "D", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Effekt-\ninnst.", "description": "" }, "SolderingMenu": { "displayText": "Lodde-\ninnst.", "description": "" }, "PowerSavingMenu": { "displayText": "Dvale-\ninnst.", "description": "" }, "UIMenu": { "displayText": "Bruker-\ngrensesn.", "description": "" }, "AdvancedMenu": { "displayText": "Avanserte\nvalg", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Kilde\n", "description": "Strømforsyning. Sett nedre spenning for automatisk nedstenging. (DC 10V) (S 3.3V per celle)" }, "MinVolCell": { "displayText": "Minimum\nspenning", "description": "Minimum tillatt spenning per celle (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC-\nspenning", "description": "Maks QC-spenning bolten skal forhandle om" }, "PDNegTimeout": { "displayText": "PD-\ntidsavb.", "description": "PD-forhandlingstidsavbrudd i steg på 100 ms for kompatibilitet med noen QC-ladere" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "KTmp\n", "description": "Temperatur i \"kraft-modus\"" }, "AutoStart": { "displayText": "AStart\n", "description": "Start automatisk med lodding når strøm kobles til. (L=Lodding | D=Dvale | R=Dvale romtemperatur)" }, "TempChangeShortStep": { "displayText": "Temp-endring\nkort", "description": "Hvor mye temperaturen skal endres ved kort trykk på knapp" }, "TempChangeLongStep": { "displayText": "Temp-endring\nlang", "description": "Hvor mye temperaturen skal endres ved langt trykk på knapp" }, "LockingMode": { "displayText": "Tillat å låse\nknapper", "description": "Mens du lodder, hold nede begge knapper for å bytte mellom låsemodus (B=kun boost | F=full lås)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "BSensr\n", "description": "Bevegelsesfølsomhet (1=Minst følsom | ... | 9=Mest følsom)" }, "SleepTemperature": { "displayText": "DTmp\n", "description": "Dvaletemperatur (C)" }, "SleepTimeout": { "displayText": "DTid\n", "description": "Tid før dvale (Minutter | Sekunder)" }, "ShutdownTimeout": { "displayText": "AvTid\n", "description": "Tid før automatisk nedstenging (Minutter)" }, "HallEffSensitivity": { "displayText": "Hall-sensor\nfølsomhet", "description": "Sensitiviteten til Hall-effekt-sensoren for å detektere inaktivitet (1=Minst følsom | ... | 9=Mest følsom)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Intervall før \"dvalemodus\" starter når halleffekten er over terskelen" }, "TemperatureUnit": { "displayText": "TmpEnh\n", "description": "Temperaturskala (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "SkRetn\n", "description": "Skjermretning (H=Høyrehendt | V=Venstrehendt | A=Automatisk)" }, "CooldownBlink": { "displayText": "KjBlnk\n", "description": "Blink temperaturen på skjermen mens spissen fortsatt er varm." }, "ScrollingSpeed": { "displayText": "RullHa\n", "description": "Hastigheten på rulletekst" }, "ReverseButtonTempChange": { "displayText": "Bytt\n+ - kn.", "description": "Bytt om på knappene for å stille temperatur" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nhastighet", "description": "Hastigheten til animasjonene i menyen (S=slow | M=medium | F=fast)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loop ikon-animasjoner i hovedmenyen" }, "Brightness": { "displayText": "Skjerm-\nlysstyrke", "description": "Juster lysstyrken til OLED-skjermen" }, "ColourInversion": { "displayText": "Inverter\nskjerm", "description": "Inverter fargene på OLED-skjermen" }, "LOGOTime": { "displayText": "Oppstartlogo\nvarighet", "description": "Setter varigheten til oppstartlogoen (s=sekunder)" }, "AdvancedIdle": { "displayText": "AvDvSk\n", "description": "Vis detaljert informasjon med liten skrift på dvaleskjermen." }, "AdvancedSoldering": { "displayText": "AvLdSk\n", "description": "Vis detaljert informasjon ved lodding" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Effekt-\ngrense", "description": "Maks effekt jernet kan bruke (W=watt)" }, "CalibrateCJC": { "displayText": "TempKal?\n", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "KalSpIn?\n", "description": "Kalibrer spenning. Knappene justerer. Langt trykk for å gå ut" }, "PowerPulsePower": { "displayText": "Effekt-\npuls", "description": "Hvor høy effekt pulsen for å holde laderen våken skal ha (watt)" }, "PowerPulseWait": { "displayText": "Effektpuls\nforsink.", "description": "Forsinkelse før effektpulsen utløses (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Effektpuls\nvarighet", "description": "Hvor lenge holde-våken-pulsen varer (x 250ms)" }, "SettingsReset": { "displayText": "TilbStl?\n", "description": "Tilbakestill alle innstillinger" }, "LanguageSwitch": { "displayText": "Språk:\n NB Norsk bm", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_NL.json ================================================ { "languageCode": "NL", "languageLocalName": "Nederlands", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibratie\nklaar!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Sommige instellingen\nzijn veranderd!" }, "NoAccelerometerMessage": { "message": "Geen accelerometer\ngedetecteerd!" }, "NoPowerDeliveryMessage": { "message": "Geen USB-PD IC\ngedetecteerd!" }, "LockingKeysString": { "message": "GEBLOKKEERD" }, "UnlockingKeysString": { "message": "VRIJ" }, "WarningKeysLockedString": { "message": "!GEBLOKKEERD!" }, "WarningThermalRunaway": { "message": "Thermisch\nop hol geslagen" }, "WarningTipShorted": { "message": "!Kortgesloten Soldeerpunt!" }, "SettingsCalibrationWarning": { "message": "Voordat je opnieuw opstart: zorg dat de soldeerpunt op kamertemperatuur is!" }, "CJCCalibrating": { "message": "Kalibreren\n" }, "SettingsResetWarning": { "message": "Weet je zeker dat je de fabrieksinstellingen terug wilt zetten?" }, "UVLOWarningString": { "message": "DC Laag" }, "UndervoltageString": { "message": "Te lage spanning\n" }, "InputVoltageString": { "message": "Ingangs spanning: \n" }, "SleepingAdvancedString": { "message": "Slaapt...\n" }, "SleepingTipAdvancedString": { "message": "Punt: \n" }, "ProfilePreheatString": { "message": "Voorverwarmen\n" }, "ProfileCooldownString": { "message": "Afkoelen\n" }, "DeviceFailedValidationWarning": { "message": "Jou apparaat is waarschijnlijk een namaak!" }, "TooHotToStartProfileWarning": { "message": "Te warm om\nprofiel te starten" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "T", "SettingStartSleepChar": "S", "SettingStartSleepOffChar": "Z", "SettingLockBoostChar": "B", "SettingLockFullChar": "V" }, "menuGroups": { "PowerMenu": { "displayText": "Energie-\ninstellingen", "description": "" }, "SolderingMenu": { "displayText": "Soldeer\ninstellingen", "description": "" }, "PowerSavingMenu": { "displayText": "Slaap-\nstand", "description": "" }, "UIMenu": { "displayText": "Gebruiker-\nsomgeving", "description": "" }, "AdvancedMenu": { "displayText": "Geavanceerde\ninstellingen", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Vermogens\nbron", "description": "Minimale spanning om de batterij te beschermen tegen te ver ontladen (DC 10V) (S=3,3V per cell, zet PWR limiet uit)" }, "MinVolCell": { "displayText": "Minimum\nspanning", "description": "Minimale toegelaten voltage per cel (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "QC\nspanning", "description": "Maximale QC spanning de soldeerbout zou moeten aanvragen" }, "PDNegTimeout": { "displayText": "PD ver-\nloop tijd", "description": "PD onderhandelings verlooptijd, afstemmingsduur in stappen van 100 ms (voor compatibiliteit met sommige QC laders)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Zet PPS & EPR modes aan" }, "BoostTemperature": { "displayText": "Boost\ntemp", "description": "Tip temperatuur tijdens \"boost-modus\"" }, "AutoStart": { "displayText": "start-\ngedrag", "description": "T=verwarm naar soldeer temp | S=standby op slaap temp tot bewogen | Z=standby zonder verwarmen tot bewogen" }, "TempChangeShortStep": { "displayText": "temp veran-\ndering kort", "description": "Temperatuur veranderings stap bij korte druk op de knop" }, "TempChangeLongStep": { "displayText": "temp veran-\ndering lang", "description": "Temperatuur veranderings stap bij lange druk op de knop" }, "LockingMode": { "displayText": "Vergrendel-\nings knoppen", "description": "Houd tijdens het solderen beide knoppen ingedrukt om de vergrendeling in of uit te schakelen (B=alleen boost-modus | V=volledige vergrendeling)" }, "ProfilePhases": { "displayText": "Profiel\nfases", "description": "Nummer van fases in profiel modus" }, "ProfilePreheatTemp": { "displayText": "Voorverwarm\ntemperatuur", "description": "Voorverwarm naar deze temperatuur op de start van profiel modus" }, "ProfilePreheatSpeed": { "displayText": "Voorverwarm\nsnelheid", "description": "Voorverwarm op deze snelheid (graden per seconden)" }, "ProfilePhase1Temp": { "displayText": "Fase 1\ntemperatuur", "description": "Doel temperatuur op het einde van deze fase" }, "ProfilePhase1Duration": { "displayText": "Fase\nduur", "description": "Doel tijdsduur van deze fase (in seconden)" }, "ProfilePhase2Temp": { "displayText": "Fase 2\ntemperatuur", "description": "" }, "ProfilePhase2Duration": { "displayText": "Fase 2\nduur", "description": "" }, "ProfilePhase3Temp": { "displayText": "Fase 3\ntemperatuur", "description": "" }, "ProfilePhase3Duration": { "displayText": "Fase 3\nduur", "description": "" }, "ProfilePhase4Temp": { "displayText": "Fase 4\ntemperatuur", "description": "" }, "ProfilePhase4Duration": { "displayText": "Fase 4\nduur", "description": "" }, "ProfilePhase5Temp": { "displayText": "Fase 5\ntemperatuur", "description": "" }, "ProfilePhase5Duration": { "displayText": "Fase 5\nduur", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Afkoel\nsnelheid", "description": "De snelheid van afkoelen op het eind van profiel modus (graden per seconden)" }, "MotionSensitivity": { "displayText": "Bewegings-\ngevoeligheid", "description": "Bewegingsgevoeligheid (1=minst gevoelig | ... | 9=meest gevoelig)" }, "SleepTemperature": { "displayText": "Slaap\ntemp", "description": "Temperatuur in slaapstand (°C)" }, "SleepTimeout": { "displayText": "Slaap ver-\ntraging", "description": "Interval voor \"slaap stand\" start (Minuten | Seconden)" }, "ShutdownTimeout": { "displayText": "Uitschakel\nna", "description": "Automatisch afsluiten na (Minuten)" }, "HallEffSensitivity": { "displayText": "Hall sensor\ngevoeligheid", "description": "Gevoeligheid naar de magneten (1=minst gevoelig | ... | 9=meest gevoelig)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval voordat de \"slaapmodus\" start wanneer het Hall-effect boven de drempelwaarde komt" }, "TemperatureUnit": { "displayText": "Temperatuur\neenheid", "description": "C=°Celsius | F=°Fahrenheit" }, "DisplayRotation": { "displayText": "Scherm-\noriëntatie", "description": "R=Rechtshandig | L=Linkshandig | A=Automatisch" }, "CooldownBlink": { "displayText": "Afkoel\nknipper", "description": "Temperatuur knippert in hoofdmenu tijdens afkoeling" }, "ScrollingSpeed": { "displayText": "Scroll\nsnelheid", "description": "Scrollsnelheid van de tekst. (Langzaam | Snel)" }, "ReverseButtonTempChange": { "displayText": "Wissel\n+ - knoppen", "description": "Wissel de knoppen voor temperatuur controle om" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nsnelheid", "description": "Snelheid van de icoon animaties in het menu (Langzaam | Middel | Snel)" }, "AnimLoop": { "displayText": "Anim.\nherhaling", "description": "Herhaal icoon animaties in hoofdmenu" }, "Brightness": { "displayText": "Scherm\nhelderheid", "description": "Verander de helderheid van het OLED scherm" }, "ColourInversion": { "displayText": "Inverteer\nscherm", "description": "Keer de kleuren van het OLED scherm om" }, "LOGOTime": { "displayText": "Opstart\nlogo duur", "description": "Zet het duur van het opstart logo (s=seconden)" }, "AdvancedIdle": { "displayText": "Detail\nslaapscherm", "description": "Gedetailleerde informatie in een kleiner lettertype in het slaapscherm" }, "AdvancedSoldering": { "displayText": "Detail\nsoldeerscherm", "description": "Gedetailleerde informatie in kleiner lettertype in soldeerscherm" }, "BluetoothLE": { "displayText": "Blue-\ntooth", "description": "Zet Bluetooth aan" }, "PowerLimit": { "displayText": "P\nlimiet", "description": "Gemiddelde maximale vermogen dat de soldeerbout mag gebruiken (W=watt)" }, "CalibrateCJC": { "displayText": "Kalibreer CJC\nbij opstart", "description": "Bij de volgende opstart tip \"Cold Junction Compensation\" wordt gekalibreerd (niet nodig als Delta T < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibreer vo-\nedingsspanning", "description": "VIN Kalibreren (lang in te drukken om te annuleren)" }, "PowerPulsePower": { "displayText": "Power\npuls", "description": "Power van de aanhoud puls (W=watt)" }, "PowerPulseWait": { "displayText": "Energie pulse\nvertraging", "description": "Vertraging voordat de aanhoud puls wordt geactiveerd (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduur", "description": "Aanhoud pulse duur (x 250 ms)" }, "SettingsReset": { "displayText": "Instellingen\nresetten?", "description": "Alle instellingen terug zetten naar fabrieksinstellingen" }, "LanguageSwitch": { "displayText": "Taal:\n NL Nederlands", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_NL_BE.json ================================================ { "languageCode": "NL_BE", "languageLocalName": "Vlaams", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibratie\ngedaan!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Sommige settings\nzijn veranderd!" }, "NoAccelerometerMessage": { "message": "Geen accelerometer\ngedectecteerd!" }, "NoPowerDeliveryMessage": { "message": "Geen USB-PD IC\ngedetecteerd!" }, "LockingKeysString": { "message": "LOCKED" }, "UnlockingKeysString": { "message": "UNLOCKED" }, "WarningKeysLockedString": { "message": "!LOCKED!" }, "WarningThermalRunaway": { "message": "Thermisch\nop hol geslagen" }, "WarningTipShorted": { "message": "!Soldeerpunt kortgesloten!" }, "SettingsCalibrationWarning": { "message": "Voordat je opnieuw opstart: stel zeker dat de soldeerpunt op kamertemperatuur is!" }, "CJCCalibrating": { "message": "Calibreren\n" }, "SettingsResetWarning": { "message": "Weet je zeker dat je de fabrieksinstellingen terug wilt zetten?" }, "UVLOWarningString": { "message": "Onderspanning" }, "UndervoltageString": { "message": "Onderspanning\n" }, "InputVoltageString": { "message": "Voedingsspanning: \n" }, "SleepingAdvancedString": { "message": "Slaapstand...\n" }, "SleepingTipAdvancedString": { "message": "Punt: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Jou apparaat is waarschijnlijk namaak!" }, "TooHotToStartProfileWarning": { "message": "Te warm om\nprofiel te starten!" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "T", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "T", "SettingStartSleepChar": "S", "SettingStartSleepOffChar": "K", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Vermogens-\ninstellingen", "description": "" }, "SolderingMenu": { "displayText": "Soldeer\ninstellingen", "description": "" }, "PowerSavingMenu": { "displayText": "Slaap-\nstanden", "description": "" }, "UIMenu": { "displayText": "Gebruikers-\ninterface", "description": "" }, "AdvancedMenu": { "displayText": "Geavanceerde\ninstellingen", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Spannings-\nbron", "description": "Minimale toegelate voltage" }, "MinVolCell": { "displayText": "Minimum\nvoltage", "description": "Minimale toegelaten voltage per cel (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Vermogen\nwatt", "description": "Vermogen van de adapter" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD afstemmingsduur in stappen van 100ms (voor compatibiliteit met sommige QC laders)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Zet PPS & EPR modes aan" }, "BoostTemperature": { "displayText": "Verhog\nings temp", "description": "Verhogingstemperatuur" }, "AutoStart": { "displayText": "start-\ntemperatuur", "description": "Breng de soldeerbout op temperatuur bij het opstarten. (T=Soldeertemperatuur | S=Slaapstand-temperatuur | K=Slaapstand kamertemperatuur)" }, "TempChangeShortStep": { "displayText": "temp veran\ndering kort", "description": "Temperatuurveranderingsstap bij korte druk op de knop" }, "TempChangeLongStep": { "displayText": "temp veran\ndering lang", "description": "Temperatuurveranderingsstap bij lange druk op de knop" }, "LockingMode": { "displayText": "Vergrendel-\ning knoppen", "description": "Houd tijdens het solderen beide knoppen ingedrukt om de vergrendeling in of uit te schakelen (B=alleen boost-modus | F=volledige vergrendeling)" }, "ProfilePhases": { "displayText": "Profiel\nfases", "description": "Nummer van fases in profiel modus" }, "ProfilePreheatTemp": { "displayText": "Voorverwarm\ntemperatuur", "description": "Voorverwarm naar deze temperatuur op de start van profiel modus" }, "ProfilePreheatSpeed": { "displayText": "Voorverwarm\nsnelheid", "description": "Voorverwarm op deze snelheid (graden per seconden)" }, "ProfilePhase1Temp": { "displayText": "Fase 1\ntemperatuur", "description": "Doel temperatuur op het einde van deze fase" }, "ProfilePhase1Duration": { "displayText": "Fase\nduur", "description": "Doel tijdsduur van deze fase (in seconden)" }, "ProfilePhase2Temp": { "displayText": "Fase 2\ntemperatuur", "description": "" }, "ProfilePhase2Duration": { "displayText": "Fase 2\nduur", "description": "" }, "ProfilePhase3Temp": { "displayText": "Fase 3\ntemperatuur", "description": "" }, "ProfilePhase3Duration": { "displayText": "Fase 3\nduur", "description": "" }, "ProfilePhase4Temp": { "displayText": "Fase 4\ntemperatuur", "description": "" }, "ProfilePhase4Duration": { "displayText": "Fase 4\nduur", "description": "" }, "ProfilePhase5Temp": { "displayText": "Fase 5\ntemperatuur", "description": "" }, "ProfilePhase5Duration": { "displayText": "Fase 5\nduur", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Afkoel\nsnelheid", "description": "De snelheid van afkoelen op het eind van profiel modus (graden per seconden)" }, "MotionSensitivity": { "displayText": "Bewegings-\ngevoeligheid", "description": "Bewegingsgevoeligheid (1=minst gevoelig | ... | 9=meest gevoelig)" }, "SleepTemperature": { "displayText": "Slaap\ntemp", "description": "Temperatuur in slaapstand (°C)" }, "SleepTimeout": { "displayText": "Slaap\ntime-out", "description": "Slaapstand time-out (Minuten | Seconden)" }, "ShutdownTimeout": { "displayText": "Uitschakel\ntime-out", "description": "Automatisch afsluiten time-out (Minuten)" }, "HallEffSensitivity": { "displayText": "Hall sensor\ngevoeligheid", "description": "Gevoeligheid naar de magneten (1=minst gevoelig | ... | 9=meest gevoelig)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval voordat de \"slaapmodus\" start wanneer het Hall-effect boven de drempelwaarde komt" }, "TemperatureUnit": { "displayText": "Temperatuur\nschaal", "description": "Temperatuurschaal (°C=Celsius | °F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Scherm-\noriëntatie", "description": "Schermoriëntatie (R=Rechtshandig | L=Linkshandig | A=Automatisch)" }, "CooldownBlink": { "displayText": "Afkoel\nknipper", "description": "Temperatuur knippert in hoofdmenu tijdens afkoeling." }, "ScrollingSpeed": { "displayText": "Scroll\nsnelheid", "description": "Scrollsnelheid van de tekst." }, "ReverseButtonTempChange": { "displayText": "Wissel\n+ - knoppen", "description": "Wissel de knoppen voor temperatuur controle" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nsnelheid", "description": "Snelheid van de icoon animaties in het menu (T=sloom | M=middel | S=snel)" }, "AnimLoop": { "displayText": "Anim.\nherhaling", "description": "Herhaal icoon animaties in hoofdmenu" }, "Brightness": { "displayText": "Scherm\nhelderheid", "description": "Verander de helderheid van het OLED scherm" }, "ColourInversion": { "displayText": "Omkeer\nscherm", "description": "Omkeer de kleuren van het OLED scherm" }, "LOGOTime": { "displayText": "Opstart\nlogo lengte", "description": "Zet het lengte van het opstart logo (s=seconden)" }, "AdvancedIdle": { "displayText": "Gedetailleerd\nslaapscherm", "description": "Gedetailleerde informatie in een kleiner lettertype in het slaapscherm" }, "AdvancedSoldering": { "displayText": "Gedetailleerd\nsoldeerscherm", "description": "Gedetailleerde informatie in kleiner lettertype in soldeerscherm" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Zet Bluetooth aan" }, "PowerLimit": { "displayText": "Power\nlimit", "description": "Gemiddelde maximale power dat de soldeerbout mag gebruiken (W=watt)" }, "CalibrateCJC": { "displayText": "Calibreer CJC\nbij opstart", "description": "Bij de volgende opstart tip Cold Junction Compensation wordt gecalibreerd (niet nodig als Delta T < 5°C)" }, "VoltageCalibration": { "displayText": "Calibreervo-\nedingsspanning?", "description": "VIN Calibreren. Bevestigen door knoppen lang in te drukken." }, "PowerPulsePower": { "displayText": "Power\npuls", "description": "Power van de wakker-houd-puls (W=watt)" }, "PowerPulseWait": { "displayText": "Power pulse\nvertraging", "description": "Vertraging voordat de wakker-houd-puls wordt geactiveerd (x 2,5s)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduur", "description": "Keep-awake-pulse duration (x 250ms)" }, "SettingsReset": { "displayText": "Instellingen\nresetten?", "description": "Alle instellingen resetten" }, "LanguageSwitch": { "displayText": "Spraak:\n NL_BE Vlaams", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_PL.json ================================================ { "languageCode": "PL", "languageLocalName": "Polski", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Skalibrowano!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Ust. \nzresetowane" }, "NoAccelerometerMessage": { "message": "Nie rozpoznano\nakcelerometru!" }, "NoPowerDeliveryMessage": { "message": "Nie rozpoznano\nkont. USB-PD IC!" }, "LockingKeysString": { "message": "ZABLOK." }, "UnlockingKeysString": { "message": "ODBLOK." }, "WarningKeysLockedString": { "message": "!ZABLOK!" }, "WarningThermalRunaway": { "message": "Ucieczka\ntermiczna" }, "WarningTipShorted": { "message": "!Zwarty grot!" }, "SettingsCalibrationWarning": { "message": "Upewnij się, że końcówka i uchwyt mają temperaturę pokojową podczas następnego rozruchu!" }, "CJCCalibrating": { "message": "kalibracja\n" }, "SettingsResetWarning": { "message": "Czy na pewno chcesz przywrócić ustawienia fabryczne?" }, "UVLOWarningString": { "message": "NIS. NAP" }, "UndervoltageString": { "message": "Zbyt niskie nap.\n" }, "InputVoltageString": { "message": "Nap. wej.: \n" }, "SleepingAdvancedString": { "message": "Tr. uśpienia\n" }, "SleepingTipAdvancedString": { "message": "Grot: \n" }, "ProfilePreheatString": { "message": "Rozgrzewanie\n" }, "ProfileCooldownString": { "message": "Schładzanie\n" }, "DeviceFailedValidationWarning": { "message": "Twoje urządzenie jest najprawdopodobniej podróbką!" }, "TooHotToStartProfileWarning": { "message": "Zbyt gorące, aby\nuruchomić profil" } }, "characters": { "SettingRightChar": "P", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "W", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "T", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "O", "SettingLockBoostChar": "B", "SettingLockFullChar": "P" }, "menuGroups": { "PowerMenu": { "displayText": "Ustawienia\nzasilania", "description": "" }, "SolderingMenu": { "displayText": "Lutowanie\n", "description": "" }, "PowerSavingMenu": { "displayText": "Oszcz.\nenergii", "description": "" }, "UIMenu": { "displayText": "Interfejs\nużytkownika", "description": "" }, "AdvancedMenu": { "displayText": "Ustawienia\nzaawans.", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Tryb\ndomyślny" }, "USBPDModeNoDynamic": { "displayText": "Nie\ndynamiczny" }, "USBPDModeSafe": { "displayText": "Tryb\nbezpieczny" }, "TipTypeAuto": { "displayText": "Auto\nwykrycie" }, "TipTypeT12Long": { "displayText": "Długi\nTS100" }, "TipTypeT12Short": { "displayText": "Krótki\nPine" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Źródło\nzasilania", "description": "Źródło zasilania. Ustaw napięcie odcięcia. (DC 10V) (S=3.3V dla ogniw Li, wyłącz limit mocy)" }, "MinVolCell": { "displayText": "Minimalne\nnapięcie", "description": "Minimalne dozwolone napięcie na komórkę (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "Napięcie QC", "description": "Maksymalne napięcie, które lutownica będzie próbowała wynegocjować z ładowarką Quick Charge (V)" }, "PDNegTimeout": { "displayText": "Limit czasu\nPD", "description": "Limit czasu negocjacji PD w krokach co 100ms dla zgodności z niektórymi ładowarkami QC (0: wyłączone)" }, "USBPDMode": { "displayText": "Tryb PD", "description": "Włącza tryby PPS & EPR." }, "BoostTemperature": { "displayText": "Temp.\nboost", "description": "Temp. w trybie \"boost\" " }, "AutoStart": { "displayText": "Aut. uruch.\ntr. lutowania", "description": "Automatyczne uruchamianie trybu lutowania po włączeniu zasilania. (T: lutowanie | Z: uśpienie | O: uśpienie w temp. pokojowej)" }, "TempChangeShortStep": { "displayText": "Zm. temp.\nkr. przyc.", "description": "Wartość zmiany temperatury, po krótkim przyciśnięciu (°C)" }, "TempChangeLongStep": { "displayText": "Zm. temp.\ndł. przyc.", "description": "Wartość zmiany temperatury, po długim przyciśnięciu (°C)" }, "LockingMode": { "displayText": "Blokada\nprzycisków", "description": "W trybie lutowania, wciśnij oba przyciski aby je zablokować (B=tylko Boost | P=pełna blokada)" }, "ProfilePhases": { "displayText": "Fazy\nprofilu", "description": "Liczba faz w trybie profilu" }, "ProfilePreheatTemp": { "displayText": "Temp.\nrozgrzewania", "description": "Rozgrzanie do tej temp. na początku trybu profilu" }, "ProfilePreheatSpeed": { "displayText": "Prędk.\nrozgrzewania", "description": "Tempo rozgrzewania (stopnie na sekundę)" }, "ProfilePhase1Temp": { "displayText": "Temp.\nfazy 1", "description": "Docelowa temp. na koniec tej fazy" }, "ProfilePhase1Duration": { "displayText": "Dług.\nfazy 1", "description": "Docelowy czas trwania tej fazy (sekundy)" }, "ProfilePhase2Temp": { "displayText": "Temp.\nfazy 2", "description": "" }, "ProfilePhase2Duration": { "displayText": "Dług.\nfazy 2", "description": "" }, "ProfilePhase3Temp": { "displayText": "Temp.\nfazy 3", "description": "" }, "ProfilePhase3Duration": { "displayText": "Dług.\nfazy 3", "description": "" }, "ProfilePhase4Temp": { "displayText": "Temp.\nfazy 4", "description": "" }, "ProfilePhase4Duration": { "displayText": "Dług.\nfazy 4", "description": "" }, "ProfilePhase5Temp": { "displayText": "Temp.\nfazy 5", "description": "" }, "ProfilePhase5Duration": { "displayText": "Dług.\nfazy 5", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Prędk.\nschładzania", "description": "Tempo schładzania na koniec trybu profilu (stopnie na sekundę)" }, "MotionSensitivity": { "displayText": "Czułość\nwykr. ruchu", "description": "Czułość wykrywania ruchu (1: Minimalna | ... | 9: Maksymalna)" }, "SleepTemperature": { "displayText": "Temp.\nuśpienia", "description": "Temperatura w trybie uśpienia (°C)" }, "SleepTimeout": { "displayText": "Czas do\nuśpienia", "description": "Czas do przejścia w tryb uśpienia (minuty | sekundy)" }, "ShutdownTimeout": { "displayText": "Czas do\nwyłączenia", "description": "Czas do wyłączenia (minuty)" }, "HallEffSensitivity": { "displayText": "Czułość\ncz. Halla", "description": "Czułość czujnika Halla, używanego do przechodznia w tryb uśpienia (1: Minimalna | ... | 9: Maksymalna)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Odstęp przed rozpoczęciem \"trybu uśpienia\", gdy efekt Halla przekracza próg" }, "TemperatureUnit": { "displayText": "Jednostka\ntemperatury", "description": "Jednostka temperatury (C: Celciusz | F: Fahrenheit)" }, "DisplayRotation": { "displayText": "Obrót\nekranu", "description": "Obrót ekranu (P: dla praworęcznych | L: dla leworęcznych | A: automatycznie)" }, "CooldownBlink": { "displayText": "Mig. podczas\nschładzania", "description": "Temperatura miga podczas schładzania, gdy grot jest wciąż gorący" }, "ScrollingSpeed": { "displayText": "Sz. przew.\ntekstu", "description": "Szybkość przewijania tekstu" }, "ReverseButtonTempChange": { "displayText": "Zamień przyc.\n+ -", "description": "Zamienia działanie przycisków zmiany temperatury grotu" }, "ReverseButtonSettings": { "displayText": "Zamień\nklawisze A i B", "description": "Odwrotne przypisanie przycisków dla menu Ustawienia" }, "AnimSpeed": { "displayText": "Prędkosć\nanimacji", "description": "Prędkość animacji ikon w menu (W: mała | M: średnia | S: duża)" }, "AnimLoop": { "displayText": "Zapętlona\nanimacja", "description": "Zapętla animację ikon w menu głównym" }, "Brightness": { "displayText": "Jasność\nwyświetlacza", "description": "Regulacja kontrastu/jasności wyświetlacza OLED" }, "ColourInversion": { "displayText": "Odwrócenie\nkolorów", "description": "Odwrócenie kolorów wyświetlacza OLED" }, "LOGOTime": { "displayText": "Długość wyś.\nloga", "description": "Ustawia czas wyświetlania loga podczas uruchamiania (s=sekund)" }, "AdvancedIdle": { "displayText": "Szczegółowy\nekran bezczyn.", "description": "Wyświetla szczegółowe informacje za pomocą mniejszej czcionki na ekranie bezczynności" }, "AdvancedSoldering": { "displayText": "Sz. inf. w\ntr. lutowania", "description": "Wyświetl szczegółowe informacje w trybie lutowania" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Włącza Bluetooth Low Energy" }, "PowerLimit": { "displayText": "Ogr.\nmocy", "description": "Maksymalna moc (W), jakiej może użyć lutownica" }, "CalibrateCJC": { "displayText": "Kalibracja temperatury\nprzy następnym uruchomieniu", "description": "Kalibracja temperatury przy następnym włączeniu (nie jest wymagana, jeśli różnica temperatur jest mniejsza niż 5°C" }, "VoltageCalibration": { "displayText": "Kalibracja\nnapięcia", "description": "Kalibracja napięcia wejściowego. Krótkie naciśnięcie, aby ustawić, długie naciśnięcie, aby wyjść." }, "PowerPulsePower": { "displayText": "Moc\nimpulsu", "description": "W przypadku używania powerbanku, utrzymuj moc na poziomie (W) aby nie uśpić powerbanku" }, "PowerPulseWait": { "displayText": "Czas między\nimp. mocy", "description": "Czas między kolejnymi impulsami mocy zapobiegającymi usypianiu powerbanku (x2,5 s)" }, "PowerPulseDuration": { "displayText": "Długość\nimpulsu mocy", "description": "Długość impulsu mocy zapobiegającego usypianiu powerbanku (x250 ms)" }, "SettingsReset": { "displayText": "Ustawienia\nfabryczne", "description": "Resetuje wszystkie ustawienia" }, "LanguageSwitch": { "displayText": "Język:\n PL Polski", "description": "" }, "SolderingTipType": { "displayText": "Typ grotu", "description": "Wybierz typ zamontowanego grotu" } } } ================================================ FILE: Translations/translation_PT.json ================================================ { "languageCode": "PT", "languageLocalName": "Português", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibração\nfeita!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Algumas configurações\nforam alteradas!" }, "NoAccelerometerMessage": { "message": "Acelerómetro não\ndetetado!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC não\ndetetado!" }, "LockingKeysString": { "message": "Bloqueado" }, "UnlockingKeysString": { "message": "Desbloqueado" }, "WarningKeysLockedString": { "message": "!Bloqueado!" }, "WarningThermalRunaway": { "message": "Avalanche\nTérmica" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Antes de reiniciar certifique-se que o ferro está à temperatura ambiente!" }, "CJCCalibrating": { "message": "a calibrar\n" }, "SettingsResetWarning": { "message": "Definições de fábrica?" }, "UVLOWarningString": { "message": "DC BAIXO" }, "UndervoltageString": { "message": "Subtensão\n" }, "InputVoltageString": { "message": "Tensão: \n" }, "SleepingAdvancedString": { "message": "Repouso...\n" }, "SleepingTipAdvancedString": { "message": "Ponta: \n" }, "ProfilePreheatString": { "message": "Pré-Aquecer\n" }, "ProfileCooldownString": { "message": "Arrefecer\n" }, "DeviceFailedValidationWarning": { "message": "O seu dispositivo provavelmente é falsificado!" }, "TooHotToStartProfileWarning": { "message": "Demasiado quente para\niniciar perfil" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "C", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "F", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "H", "SettingStartSleepOffChar": "A", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Opções de\nEnergia", "description": "" }, "SolderingMenu": { "displayText": "Opções de\nSolda", "description": "" }, "PowerSavingMenu": { "displayText": "Modo de\nRepouso", "description": "" }, "UIMenu": { "displayText": "Interface\nUtilizador", "description": "" }, "AdvancedMenu": { "displayText": "Opções\nAvançadas", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Fonte\nalimentação", "description": "Fonte de alimentação. Define a tensão de corte. (DC=10V) (S=3.3V/célula)" }, "MinVolCell": { "displayText": "Tensão\nmínima", "description": "Tensão mínima permitida por célula de bateria (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Potência\nFonte", "description": "Potência da fonte usada (Watt)" }, "PDNegTimeout": { "displayText": "PD tempo\nlimite", "description": "Tempo limite de negoiciação de PD de 100ms para compatibilidade com alguns carregadores é (0: disabled)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Activa o modo PPS & EPR" }, "BoostTemperature": { "displayText": "Temp.\nModo Turbo", "description": "Ajuste de temperatura do \"modo turbo\"" }, "AutoStart": { "displayText": "Aquecimento\nautomático", "description": "Aquece a ponta automaticamente ao ligar (S=soldagem | H=hibernar | A=hibernar temp. ambiente)" }, "TempChangeShortStep": { "displayText": "Mudança temp.\ncurta", "description": "A temperatura será aumentada com um click curto" }, "TempChangeLongStep": { "displayText": "Mudança temp.\nlonga", "description": "A temperatura será aumentada com um click longo" }, "LockingMode": { "displayText": "Permitir bloq.\nbotões", "description": "Durante a solda premir os dois botões para alternar entre (B=modo turbo | F=bloqueio total)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Temperatura\nPré-aquecimento", "description": "Pré-aquecer a esta temperatura quando o perfil é selecionado" }, "ProfilePreheatSpeed": { "displayText": "Velocidade\nPré-aquecimento", "description": "Ritmo de pré-aquecimento (graus por segundo)" }, "ProfilePhase1Temp": { "displayText": "Temp.\nFase 1", "description": "Temperatura alvo no final desta fase" }, "ProfilePhase1Duration": { "displayText": "Duração\nFase 1", "description": "Duração alvo desta fase (segundos)" }, "ProfilePhase2Temp": { "displayText": "Temp.\nFase 2", "description": "" }, "ProfilePhase2Duration": { "displayText": "Duração\nFase 2", "description": "" }, "ProfilePhase3Temp": { "displayText": "Temp.\nFase 3", "description": "" }, "ProfilePhase3Duration": { "displayText": "Duração\nFase 3", "description": "" }, "ProfilePhase4Temp": { "displayText": "Temp.\nFase 4", "description": "" }, "ProfilePhase4Duration": { "displayText": "Duração\nFase 4", "description": "" }, "ProfilePhase5Temp": { "displayText": "Temp.\nFase 5", "description": "" }, "ProfilePhase5Duration": { "displayText": "Duração\nFase 5", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Velocidade\nArrefecimento", "description": "Arrefecer a este ritmo após sair do perfil selecionado (graus por segundo)" }, "MotionSensitivity": { "displayText": "Sensibilidade\nmovimento", "description": "Sensibilidade ao movimento (1=Menor | ... | 9=Maior)" }, "SleepTemperature": { "displayText": "Temperatura\nrepouso", "description": "Temperatura de repouso (C)" }, "SleepTimeout": { "displayText": "Tempo\nrepouso", "description": "Tempo para repouso (Minutos | Segundos)" }, "ShutdownTimeout": { "displayText": "Tempo\ndesligar", "description": "Tempo para desligar (Minutos)" }, "HallEffSensitivity": { "displayText": "Sensibilidade de\nmagnetismo", "description": "Sensibilidade de magnetismo (1=Menor | ... | 9=Maior)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Intervalo antes do início do \"modo de suspensão\" quando o efeito Hall está acima do limite" }, "TemperatureUnit": { "displayText": "Unidade\ntemperatura", "description": "Unidade de temperatura (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Orientação\necrã", "description": "Orientação do ecrã (D=estro | C=anhoto | A=utomática)" }, "CooldownBlink": { "displayText": "Piscar ao\narrefecer", "description": "Faz o valor da temperatura piscar durante o arrefecimento" }, "ScrollingSpeed": { "displayText": "Velocidade\ntexto ajuda", "description": "Velocidade a que o texto de ajuda é apresentado" }, "ReverseButtonTempChange": { "displayText": "Trocar\nbotões + -", "description": "Inverte o funcionamento dos botões de ajuste da temperatura" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Velocidade\nde animação", "description": "Velocidade das animações no menu (S=lenta | M=média | F=rápida)" }, "AnimLoop": { "displayText": "Repetir\nanimações", "description": "Repete animações de ícones no menu principal" }, "Brightness": { "displayText": "Brilho\ndo ecrã", "description": "Ajusta o brilho do ecrã OLED" }, "ColourInversion": { "displayText": "Inverter\necrã", "description": "Inverte as cores do ecrã OLED" }, "LOGOTime": { "displayText": "Tempo img.\nno arranque", "description": "Define a duração do logotipo no arranque em (s=segundos)" }, "AdvancedIdle": { "displayText": "Ecrã repouso\navançado", "description": "Mostra informações avançadas quando em repouso" }, "AdvancedSoldering": { "displayText": "Ecrã solda\navançado", "description": "Mostra informações avançadas durante a solda" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Ativa o Bluetooth Low Energy (BLE)" }, "PowerLimit": { "displayText": "Limite\npotência", "description": "Potência máxima a usar (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrar CJC\nno próximo arranque", "description": "No próximo arranque CJC será calibrada (não será necessário caso o Delta T seja < 5°C)" }, "VoltageCalibration": { "displayText": "Calibrar\ntensão", "description": "Calibra a tensão de alimentação. Use os botões para ajustar o valor. Mantenha pressionado para sair" }, "PowerPulsePower": { "displayText": "Potência\ndo pulso", "description": "Intensidade de potência de arranque (W=watt)" }, "PowerPulseWait": { "displayText": "Espera do\npulso", "description": "Espera entre o acordar e o envio da rectivação (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Duração\npulso", "description": "Manter os inplosus de rectivação em (x 250ms)" }, "SettingsReset": { "displayText": "Reset de\nfábrica?", "description": "Repôe todos os ajustes" }, "LanguageSwitch": { "displayText": "Idioma:\n PT Português", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_RO.json ================================================ { "languageCode": "RO", "languageLocalName": "Română", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Setările au fost\nresetate!" }, "NoAccelerometerMessage": { "message": "Fără accelerometru\ndetectat!" }, "NoPowerDeliveryMessage": { "message": "Fără USB-PD IC\ndetectat!" }, "LockingKeysString": { "message": "BLOCAT" }, "UnlockingKeysString": { "message": "DEBLOCAT" }, "WarningKeysLockedString": { "message": "!BLOCAT!" }, "WarningThermalRunaway": { "message": "Încălzire\nEşuată" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Înainte de repornire, asiguraţi-vă că vârful şi mânerul sunt la temperatura camerei!" }, "CJCCalibrating": { "message": "calibrare\n" }, "SettingsResetWarning": { "message": "Sigur doriţi să restauraţi la setările implicite?" }, "UVLOWarningString": { "message": "DC SCĂZUT" }, "UndervoltageString": { "message": "Voltaj scăzut\n" }, "InputVoltageString": { "message": "Intrare V: \n" }, "SleepingAdvancedString": { "message": "Adormit...\n" }, "SleepingTipAdvancedString": { "message": "Tip: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Dispozitivul dvs. este cel mai probabil un fals!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "S", "SettingAutoChar": "A", "SettingSlowChar": "Î", "SettingMediumChar": "M", "SettingFastChar": "R", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Setări de\nalimentare", "description": "" }, "SolderingMenu": { "displayText": "Setări de\nlipire", "description": "" }, "PowerSavingMenu": { "displayText": "Modul\nrepaus", "description": "" }, "UIMenu": { "displayText": "Interfaţă\nutilizator", "description": "" }, "AdvancedMenu": { "displayText": "Opţiuni\navansate", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Sursa de\nalimentare", "description": "Sursa de alimentare. Setează tensiunea de întrerupere. (DC 10V) (S 3.3V per celulă, dezactivaţi limita de alimentare)" }, "MinVolCell": { "displayText": "Voltaj\nminim", "description": "Tensiunea minimă admisă pe celulă (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nvoltaj", "description": "Tensiunea maximă QC dorită pentru care negociază letconul" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "Timp limită de negociere pentru tranzacţia PD, în paşi de 100ms, pentru compatibilitate cu alimentatoarele QC" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Modifică\ntemp. impuls", "description": "Temperatura utilizată în \"modul de impuls\"" }, "AutoStart": { "displayText": "Auto\nstart", "description": "Start letcon în modul de lipire la pornire (S=lipire | Z=repaus | R=repaus la temperatura camerei)" }, "TempChangeShortStep": { "displayText": "Schimbare temp.\napăsare scută", "description": "Schimbarea temperaturii la apăsarea scurtă a butonului" }, "TempChangeLongStep": { "displayText": "Schimbare temp.\napăsare lungă", "description": "Schimbarea temperaturii la apăsarea lungă a butonului" }, "LockingMode": { "displayText": "Blocare\nbutoane", "description": "Când lipiţi, apăsaţi lung ambele butoane, pentru a le bloca (B=numai \"modul boost\" | F=blocare completă)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Sensibilitate\nla miscare", "description": "Sensibilitate senzor miscare (1=puţin sensibil | ... | 9=cel mai sensibil)" }, "SleepTemperature": { "displayText": "Temp\nrepaus", "description": "Temperatura vârfului în \"modul repaus\"" }, "SleepTimeout": { "displayText": "Expirare\nrepaus", "description": "Interval înainte de lansarea \"modului de repaus\" în (s=secunde | m=minute)" }, "ShutdownTimeout": { "displayText": "Expirare\noprire", "description": "Interval înainte ca letconul să se oprească (m=minute)" }, "HallEffSensitivity": { "displayText": "Sensibilitate\nsenzor Hall", "description": "Sensibilitate senzor cu efect Hall pentru a detecta repausul (1=putin sensibil | ... | 9=cel mai sensibil)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Intervalul înainte de începerea \"modului de repaus\" când efectul de sală este peste prag" }, "TemperatureUnit": { "displayText": "Unitate de\ntemperatură", "description": "C=Celsius | F=Fahrenheit" }, "DisplayRotation": { "displayText": "Orientare\necran", "description": "R=dreptaci | L=stângaci | A=auto" }, "CooldownBlink": { "displayText": "Clipeşte\nla răcire", "description": "Clipeşte temperatura după oprirea încălzirii, în timp ce vârful este încă fierbinte" }, "ScrollingSpeed": { "displayText": "Viteză\nderulare", "description": "Viteză derulare text cu informatii la (S=lent | F=rapid)" }, "ReverseButtonTempChange": { "displayText": "Inversare\n+ - butoane", "description": "Inversarea butoanelor de reglare a temperaturii" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Animaţii\nviteză", "description": "Ritmul animaţiilor pictogramei din meniu (Î=încet | M=mediu | R=rapid)" }, "AnimLoop": { "displayText": "Animaţii\nbuclă", "description": "Animaţii de pictograme în meniul principal" }, "Brightness": { "displayText": "Ecranului\nluminozitatea", "description": "Ajusteaza luminozitatea ecranului" }, "ColourInversion": { "displayText": "Inversează\nculoarea", "description": "Inversează culoarea ecranului" }, "LOGOTime": { "displayText": "Durată\nlogo încărcare", "description": "Setaţi durată logo de pornire (s=secunde)" }, "AdvancedIdle": { "displayText": "Detalii,\necran inactiv", "description": "Afisaţi informaţii detaliate într-un font mai mic pe ecranul de repaus" }, "AdvancedSoldering": { "displayText": "Detalii\necran lipire", "description": "Afisaţi informaţii detaliate într-un font mai mic pe ecranul de lipire" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Activează BLE" }, "PowerLimit": { "displayText": "Putere\nlimită", "description": "Puterea maximă pe care letconul o poate folosi (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrare CJC\nla următoarea pornire", "description": "La următorul vârf de pornire, compensarea joncţiunii reci va fi calibrată (nu este necesară dacă Delta T este < 5°C)" }, "VoltageCalibration": { "displayText": "Calibrare tens.\nde intrare?", "description": "Porniţi calibrarea VIN (apăsaţi lung pentru a ieşi)" }, "PowerPulsePower": { "displayText": "Putere\npuls", "description": "Puterea pulsului de menţinere activă a blocului de alimentare (watt)" }, "PowerPulseWait": { "displayText": "Întârziere\npuls putere", "description": "Perioada pulsului de mentinere (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Durată\npuls putere", "description": "Durata pulsului de menţinere (x 250ms)" }, "SettingsReset": { "displayText": "Setări\ndin fabrică", "description": "Reveniţi la setările din fabrică" }, "LanguageSwitch": { "displayText": "Limbă:\n RO Română", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_RU.json ================================================ { "languageCode": "RU", "languageLocalName": "Русский", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Калибровка\nзавершена!" }, "ResetOKMessage": { "message": "Готово!" }, "SettingsResetMessage": { "message": "Настройки\nсброшены!" }, "NoAccelerometerMessage": { "message": "Акселерометр\nне обнаружен!" }, "NoPowerDeliveryMessage": { "message": "Питание по USB-PD\nне обнаружено" }, "LockingKeysString": { "message": "ЗАБЛОК" }, "UnlockingKeysString": { "message": "РАЗБЛОК" }, "WarningKeysLockedString": { "message": "!ЗАБЛОК!" }, "WarningThermalRunaway": { "message": "Неуправляемый\nразогрев" }, "WarningTipShorted": { "message": "!КЗ на жале!" }, "SettingsCalibrationWarning": { "message": "Пожалуйста, убедитесь, что жало и корпус имеют комнатную температуру при следующей загрузке!" }, "CJCCalibrating": { "message": "калибровка\n" }, "SettingsResetWarning": { "message": "Вы уверены, что хотите сбросить настройки к значениям по умолчанию?" }, "UVLOWarningString": { "message": "НИЗ.НАПР" }, "UndervoltageString": { "message": "Низ. напряжение\n" }, "InputVoltageString": { "message": "Питание(В):\n" }, "SleepingAdvancedString": { "message": "Сон...\n" }, "SleepingTipAdvancedString": { "message": "Жало: \n" }, "ProfilePreheatString": { "message": "Преднагрев\n" }, "ProfileCooldownString": { "message": "Остывание\n" }, "DeviceFailedValidationWarning": { "message": "Вероятно, это поддельное устройство!" }, "TooHotToStartProfileWarning": { "message": "Слишком горячо для\nстарта профиля" } }, "characters": { "SettingRightChar": "П", "SettingLeftChar": "Л", "SettingAutoChar": "А", "SettingSlowChar": "М", "SettingMediumChar": "С", "SettingFastChar": "Б", "SettingStartSolderingChar": "П", "SettingStartSleepChar": "С", "SettingStartSleepOffChar": "К", "SettingLockBoostChar": "Т", "SettingLockFullChar": "П" }, "menuGroups": { "PowerMenu": { "displayText": "Настройки\nпитания", "description": "" }, "SolderingMenu": { "displayText": "Настройки\nпайки", "description": "" }, "PowerSavingMenu": { "displayText": "Авто\nвыключение", "description": "" }, "UIMenu": { "displayText": "Интерфейс\n", "description": "" }, "AdvancedMenu": { "displayText": "Доп.\nнастройки", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Вкл.\nPPSиEPR" }, "USBPDModeNoDynamic": { "displayText": "Откл.\n" }, "USBPDModeSafe": { "displayText": "Вкл.без\nзапроса" }, "TipTypeAuto": { "displayText": "Авто\nопред-е" }, "TipTypeT12Long": { "displayText": "TS100\nстанд." }, "TipTypeT12Short": { "displayText": "Pine\nкоротк." }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80(P)\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Предельное\nнапряжение", "description": "Установка минимально предельного напряжения от аккумулятора для предотвращения глубокого разряда (DC 10В | S 3,3В на ячейку, без ограничения мощности)" }, "MinVolCell": { "displayText": "Мин.\nнапряжение", "description": "Минимально разрешённое напряжение на ячейку (3S: 3 - 3,7В | 4S-6S: 2,4 - 3,7В)" }, "QCMaxVoltage": { "displayText": "Напр-е\nдля QC", "description": "Максимальное напряжение для согласования с источником питания по QC" }, "PDNegTimeout": { "displayText": "Интервал\nPD", "description": "Интервал согласования питания по Power Delivery с шагом 100 мс для совместимости с некоторыми источниками питания по QC (0=Откл.)" }, "USBPDMode": { "displayText": "Режим\nPD", "description": "Вкл.без запроса: включить PPS и EPR без запроса большей мощности" }, "BoostTemperature": { "displayText": "t° турбо\nрежима", "description": "Температура жала в турбо-режиме" }, "AutoStart": { "displayText": "Режим при\nвключении", "description": "Режим, в котором включается паяльник (П=Пайка | С=Сон | К=Ожидание при комн. темп.)" }, "TempChangeShortStep": { "displayText": "Шаг t° при\nкор.наж-ии", "description": "Шаг изменения температуры при коротком нажатии кнопок" }, "TempChangeLongStep": { "displayText": "Шаг t° при\nдол.наж-ии", "description": "Шаг изменения температуры при долгом нажатии кнопок" }, "LockingMode": { "displayText": "Разрешить\nблок. кнопок", "description": "Блокировать кнопки при их долгом нажатии в режиме пайки (Т=Только турбо | П=Полная блокировка)" }, "ProfilePhases": { "displayText": "Этапы\nпрофиля", "description": "Количество этапов в режиме профиля" }, "ProfilePreheatTemp": { "displayText": "Температура\nпреднагрева", "description": "Температура предварительного нагрева в начале режима термопрофиля" }, "ProfilePreheatSpeed": { "displayText": "Скорость\nпреднагрева", "description": "Скорость предварительного нагрева в начале режима термопрофиля (в градусах в секунду)" }, "ProfilePhase1Temp": { "displayText": "Температура\n1-го этапа", "description": "Необходимая температура в конце 1-го этапа" }, "ProfilePhase1Duration": { "displayText": "Длительность\n1-го этапа", "description": "Необходимая длительность 1-го этапа (в секундах)" }, "ProfilePhase2Temp": { "displayText": "Температура\n2-го этапа", "description": "" }, "ProfilePhase2Duration": { "displayText": "Длительность\n2-го этапа", "description": "" }, "ProfilePhase3Temp": { "displayText": "Температура\n3-го этапа", "description": "" }, "ProfilePhase3Duration": { "displayText": "Длительность\n3-го этапа", "description": "" }, "ProfilePhase4Temp": { "displayText": "Температура\n4-го этапа", "description": "" }, "ProfilePhase4Duration": { "displayText": "Длительность\n4-го этапа", "description": "" }, "ProfilePhase5Temp": { "displayText": "Температура\n5-го этапа", "description": "" }, "ProfilePhase5Duration": { "displayText": "Длительность\n5-го этапа", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Скорость\nостывания", "description": "Скорость остывания в конце режима термопрофиля (в градусах в секунду)" }, "MotionSensitivity": { "displayText": "Чувствительн.\nакселерометра", "description": "Чувствительность акселерометра (1=мин. | ... | 9=макс.)" }, "SleepTemperature": { "displayText": "t° при\nсне", "description": "Температура жала в режиме сна" }, "SleepTimeout": { "displayText": "Интервал\nсна", "description": "Время до перехода в режим сна (секунды | минуты)" }, "ShutdownTimeout": { "displayText": "Интервал\nотключ-я", "description": "Время до выключения паяльника (в минутах)" }, "HallEffSensitivity": { "displayText": "Датчик\nХолла", "description": "Чувствительность датчика Холла к магнитному полю (1=мин. | ... | 9=макс.)" }, "HallEffSleepTimeout": { "displayText": "Интервал\nдатчика Холла", "description": "Время между превышением датчиком Холла порогового значения и режимом сна" }, "TemperatureUnit": { "displayText": "Единицы\nизмерения", "description": "Единицы измерения температуры (C=°Цельcия | F=°Фаренгейта)" }, "DisplayRotation": { "displayText": "Поворот\nэкрана", "description": "Поворот экрана (П=Правша | Л=Левша | А=Авто)" }, "CooldownBlink": { "displayText": "Мигание t°\nпри остывании", "description": "Мигать температурой на экране при остывании, пока жало ещё горячее" }, "ScrollingSpeed": { "displayText": "Скорость\nтекста", "description": "Скорость прокрутки текста (М=Медленная | Б=Быстрая)" }, "ReverseButtonTempChange": { "displayText": "Поменять\nкнопки +/-", "description": "Поменять кнопки изменения температуры" }, "ReverseButtonSettings": { "displayText": "Поменять\nкнопки A/B", "description": "Поменять назначение кнопок A/B в меню настроек" }, "AnimSpeed": { "displayText": "Скорость\nанимации", "description": "Скорость анимации иконок в главном меню (М=Медленная| С=Средняя | Б=Быстрая)" }, "AnimLoop": { "displayText": "Зацикленная\nанимация", "description": "Зацикленная анимация иконок в главном меню" }, "Brightness": { "displayText": "Яркость\nэкрана", "description": "Уровень яркости пикселей на экране" }, "ColourInversion": { "displayText": "Инверсия\nэкрана", "description": "Инвертировать пиксели на экране" }, "LOGOTime": { "displayText": "Длит-ть\nлоготипа", "description": "Длительность отображения логотипа (в секундах)" }, "AdvancedIdle": { "displayText": "Подробный\nэкран ожидания", "description": "Показывать дополнительную информацию на экране ожидания уменьшенным шрифтом" }, "AdvancedSoldering": { "displayText": "Подробный\nэкран пайки", "description": "Показывать дополнительную информацию на экране пайки уменьшенным шрифтом" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Включить BLE" }, "PowerLimit": { "displayText": "Предел\nмощ-ти", "description": "Максимальная мощность, которую может использовать паяльник (в ваттах)" }, "CalibrateCJC": { "displayText": "Калибровка\nтемпературы", "description": "Калибровка температуры (CJC) при следующем включении (не требуется при разнице менее 5°C)" }, "VoltageCalibration": { "displayText": "Калибровка\nнапряжения", "description": "Калибровка входного напряжения (долгое нажатие для выхода)" }, "PowerPulsePower": { "displayText": "Сила имп.\nпитания", "description": "Сила импульса, удерживающего от автовыключения источник питания (в ваттах)" }, "PowerPulseWait": { "displayText": "Пауза имп.\nпитания (К)", "description": "Коэффициент паузы между импульсами, удерживающими от автовыключения источник питания (К x 2,5 с)" }, "PowerPulseDuration": { "displayText": "Длина имп.\nпитания (К)", "description": "Коэффициент длины импульса, удерживающего от автовыключения источник питания (К x 250 мс)" }, "SettingsReset": { "displayText": "Сброс\nнастроек", "description": "Сброс настроек к значениям по умолчанию" }, "LanguageSwitch": { "displayText": "Язык:\n RU Русский", "description": "" }, "SolderingTipType": { "displayText": "Тип\nжала", "description": "Выбор типа установленного жала" } } } ================================================ FILE: Translations/translation_SK.json ================================================ { "languageCode": "SK", "languageLocalName": "Slovenčina", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrácia\ndokončená!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Nastavenia\nresetované" }, "NoAccelerometerMessage": { "message": "Bez pohybového\nsenzora!" }, "NoPowerDeliveryMessage": { "message": "Chýba čip\nUSB-PD!" }, "LockingKeysString": { "message": "ZABLOK." }, "UnlockingKeysString": { "message": "ODBLOK." }, "WarningKeysLockedString": { "message": "!ZABLOK!" }, "WarningThermalRunaway": { "message": "Únik\nTepla" }, "WarningTipShorted": { "message": "!Skrat hrotu!" }, "SettingsCalibrationWarning": { "message": "Pred reštartovaním sa uistite, že hrot a rúčka sú v izbovej teplote!" }, "CJCCalibrating": { "message": "kalibrovanie\n" }, "SettingsResetWarning": { "message": "Naozaj chcete obnoviť továrenské nastavenia?" }, "UVLOWarningString": { "message": "Nízke U!" }, "UndervoltageString": { "message": "Nízke napätie\n" }, "InputVoltageString": { "message": "Vstupné U: \n" }, "SleepingAdvancedString": { "message": "Pokojový režim.\n" }, "SleepingTipAdvancedString": { "message": "Hrot: \n" }, "ProfilePreheatString": { "message": "Predhrievanie\n" }, "ProfileCooldownString": { "message": "Schladzovanie\n" }, "DeviceFailedValidationWarning": { "message": "Vaše zariadenie je pravdepodobne falzifikát!" }, "TooHotToStartProfileWarning": { "message": "Teplota príliš vysoká pre štart profilu" } }, "characters": { "SettingRightChar": "P", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "P", "SettingMediumChar": "S", "SettingFastChar": "R", "SettingStartSolderingChar": "Z", "SettingStartSleepChar": "S", "SettingStartSleepOffChar": "I", "SettingLockBoostChar": "B", "SettingLockFullChar": "P" }, "menuGroups": { "PowerMenu": { "displayText": "Nastavenie\nvýkonu", "description": "" }, "SolderingMenu": { "displayText": "Nastavenie\nspájkovania", "description": "" }, "PowerSavingMenu": { "displayText": "Úsporný\nrežim", "description": "" }, "UIMenu": { "displayText": "Nastavenie\nzobrazenia", "description": "" }, "AdvancedMenu": { "displayText": "Pokročilé\nnastavenia", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Zdroj\nnapätia", "description": "Zdroj napätia. Nastavenie napätia pre vypnutie (cutoff) (DC=10V | nS=n*3.3V pre LiIon články)" }, "MinVolCell": { "displayText": "Minimálne\nnapätie", "description": "Minimálne napätie povolené na jeden článok (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Obmedzenie QC\nnapätia", "description": "Maximálne QC napätie ktoré si má systém vyžiadať" }, "PDNegTimeout": { "displayText": "Čas vypršania\nPower Delivery", "description": "Čas vyjednávania Power Delivery v 100ms krokoch pre kompatibilitu s niektorými QC nabíjačkami (0: vypnuté)" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Zapína PPS & EPR režimy" }, "BoostTemperature": { "displayText": "Boost\nteplota", "description": "Cieľová teplota pre prudký náhrev (v nastavených jednotkách)" }, "AutoStart": { "displayText": "Automatické\nspustenie", "description": "Pri štarte spustiť režim spájkovania (Z=Spájkovanie | S=Spanok | I=Spanok izbová teplota)" }, "TempChangeShortStep": { "displayText": "Malý krok\nteploty", "description": "Zmena teploty pri krátkom stlačení tlačidla" }, "TempChangeLongStep": { "displayText": "Veľký krok\nteploty", "description": "Zmena teploty pri držaní tlačidla" }, "LockingMode": { "displayText": "Povoliť zámok\ntlačidiel", "description": "Zamknutie tlačidiel - dlhé stlačenie oboch naraz počas spájkovania (B=Okrem boost | P=Plné zamknutie)" }, "ProfilePhases": { "displayText": "Profilové\nFázy", "description": "Počet fáz v profilovóm režime" }, "ProfilePreheatTemp": { "displayText": "Teplota\nPredhriatia", "description": "Teplota na ktorú sa má predohriať na začiatku profilového režimu" }, "ProfilePreheatSpeed": { "displayText": "Rýchlosť\nPredhriatia", "description": "Rýchlosť predhrievania (stupňe za sekundu)" }, "ProfilePhase1Temp": { "displayText": "Teplota\nFáza 1", "description": "Cieľová teplota na konci tejto fázy" }, "ProfilePhase1Duration": { "displayText": "Trvanie\nFáza 1", "description": "Doba trvania tejto fázy (sekundy)" }, "ProfilePhase2Temp": { "displayText": "Teplota\nFáza 2", "description": "" }, "ProfilePhase2Duration": { "displayText": "Trvanie\nFáza 2", "description": "" }, "ProfilePhase3Temp": { "displayText": "Teplota\nFáza 3", "description": "" }, "ProfilePhase3Duration": { "displayText": "Trvanie\nFáza 3", "description": "" }, "ProfilePhase4Temp": { "displayText": "Teplota\nFáza 4", "description": "" }, "ProfilePhase4Duration": { "displayText": "Trvanie\nFáza 4", "description": "" }, "ProfilePhase5Temp": { "displayText": "Teplota\nFáza 5", "description": "" }, "ProfilePhase5Duration": { "displayText": "Trvanie\nFáza 5", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Rýchlosť\nochladzovania", "description": "Rýchlosť ochladzovania na konci profilového režimu (stupne za sekundu)" }, "MotionSensitivity": { "displayText": "Citlivosť\npohybu", "description": "Citlivosť detekcie pohybu (1=Min | ... | 9=Max)" }, "SleepTemperature": { "displayText": "Pokojová\nteplota", "description": "Pokojová teplota (v nastavených jednotkách)" }, "SleepTimeout": { "displayText": "Pokojový\nrežim po", "description": "Pokojový režim po (s=sekundách | m=minútach)" }, "ShutdownTimeout": { "displayText": "Vypnutie\npo", "description": "Čas na vypnutie (minúty)" }, "HallEffSensitivity": { "displayText": "Citliv.\nHall", "description": "Citlivosť Hallovho senzora pre detekciu spánku (1=Min | ... | 9=Max)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval pred spustením \"režimu spánku\" keď je hall efekt nad prahovou hodnotou" }, "TemperatureUnit": { "displayText": "Jednotka\nteploty", "description": "Jednotky merania teploty (C=stupne Celzia | F=stupne Fahrenheita)" }, "DisplayRotation": { "displayText": "Orientácia\ndispleja", "description": "Orientácia displeja (P=Pravák | L=Ľavák | A=Auto)" }, "CooldownBlink": { "displayText": "Blikanie pri\nchladnutí", "description": "Blikanie ukazovateľa teploty počas chladnutia hrotu" }, "ScrollingSpeed": { "displayText": "Rýchlosť\nskrolovania", "description": "Rýchlosť pohybu tohto textu" }, "ReverseButtonTempChange": { "displayText": "Otočenie\ntlačidiel +/-", "description": "Prehodenie tlačidiel na nastavovanie teploty" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Rýchlosť\nanimácií", "description": "Rýchlosť animácií ikoniek v menu (P=pomaly | S=stredne | R=rýchlo)" }, "AnimLoop": { "displayText": "Opakovanie\nanimácií", "description": "Opakovanie animácií ikoniek v hlavnom menu" }, "Brightness": { "displayText": "Jas\nobrazovky", "description": "Mení jas/kontrast OLED displeja" }, "ColourInversion": { "displayText": "Invertovať\nobrazovku", "description": "Invertovať farby OLED displeja" }, "LOGOTime": { "displayText": "Trvanie\nboot loga", "description": "Doba trvania boot loga (s=sekundy)" }, "AdvancedIdle": { "displayText": "Detaily v\npokoj. režime", "description": "Zobraziť detailné informácie v pokojovom režime (T=Zap | F=Vyp)" }, "AdvancedSoldering": { "displayText": "Detaily počas\nspájkovania", "description": "Zobrazenie detailov počas spájkovania" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Zapne BLE" }, "PowerLimit": { "displayText": "Obmedzenie\nvýkonu", "description": "Obmedzenie výkonu podľa použitého zdroja (watt)" }, "CalibrateCJC": { "displayText": "Kalibrácia CJC\npri nasledujúcom štarte", "description": "Pri nasledujúcom štarte bude kalibrovaná kompenzácia studeného spoja (nie je potrebné ak Delta T je < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibrácia\nnap. napätia", "description": "Kalibrácia napájacieho napätia. Krátke stlačenie mení nastavenie, dlhé stlačenie pre návrat" }, "PowerPulsePower": { "displayText": "Intenzita\nimpulzu", "description": "Impulz udržujúci napájací zdroj zapnutý (power banky) (watt)" }, "PowerPulseWait": { "displayText": "Interval\nimpulzu", "description": "Interval medzi impulzami udržujúcimi napájací zdroj zapnutý (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Dĺžka\nimpulzu", "description": "Dĺžka impulzu udržujúci napájací zdroj zapnutý (x 250ms)" }, "SettingsReset": { "displayText": "Obnovenie\nnastavení", "description": "Obnovenie nastavení na pôvodné hodnoty" }, "LanguageSwitch": { "displayText": "Jazyk:\n SK Slovenčina", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_SL.json ================================================ { "languageCode": "SL", "languageLocalName": "Slovenščina", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Nastavitve \nOK!" }, "NoAccelerometerMessage": { "message": "Ni \npospeševalnik" }, "NoPowerDeliveryMessage": { "message": "Ni USB-PD \nčipa!" }, "LockingKeysString": { "message": "ZAKLENJ." }, "UnlockingKeysString": { "message": "ODKLENJ." }, "WarningKeysLockedString": { "message": "ZAKLENJ." }, "WarningThermalRunaway": { "message": "Thermal\nRunaway" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Res želite ponastaviti na privzete nastavitve?" }, "UVLOWarningString": { "message": "NIZKA U" }, "UndervoltageString": { "message": "Nizka napetost\n" }, "InputVoltageString": { "message": "Vhodna U: \n" }, "SleepingAdvancedString": { "message": "Spim...\n" }, "SleepingTipAdvancedString": { "message": "Konica \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "L", "SettingAutoChar": "S", "SettingSlowChar": "P", "SettingMediumChar": "M", "SettingFastChar": "H", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "V", "SettingLockBoostChar": "L", "SettingLockFullChar": "P" }, "menuGroups": { "PowerMenu": { "displayText": "Power\nsettings", "description": "" }, "SolderingMenu": { "displayText": "Nastavitve\nspajkanja", "description": "" }, "PowerSavingMenu": { "displayText": "Način\nspanja", "description": "" }, "UIMenu": { "displayText": "Uporabniški\nvmesnik", "description": "" }, "AdvancedMenu": { "displayText": "Napredne\nmožnosti", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Vir\nnapajanja", "description": "Vir napajanja. Nastavi napetost izklopa. (DC 10V) (S 3.3V na celico)" }, "MinVolCell": { "displayText": "Minimum\nvoltage", "description": "Minimum allowed voltage per battery cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nnapetost", "description": "Moč napajalnega vira v vatih [W]" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD negotiation timeout in 100ms steps for compatibility with some QC chargers" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Pospešena\ntemp.", "description": "Temperatura v pospešenem načinu" }, "AutoStart": { "displayText": "Samodejni\nzagon", "description": "Samodejno gretje konice ob vklopu (S=spajkanje | Z=spanje | V=spanje na sobni temperaturi)" }, "TempChangeShortStep": { "displayText": "Kratka sprememba\ntemperature?", "description": "Temperatura se spremeni ob kratkem pritisku na gumb." }, "TempChangeLongStep": { "displayText": "Dolga sprememba\ntemperature?", "description": "Temperatura se spremeni ob dolgem pritisku na gumb." }, "LockingMode": { "displayText": "Omogoči\nzaklep gumbov", "description": "Za zaklep med spajkanjem drži oba gumba (L=le pospešeno | P=polno)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Občutljivost\npremikanja", "description": "1=najmanjša | ... | 9=največja" }, "SleepTemperature": { "displayText": "Temp. med\nspanjem", "description": "Temperatura med spanjem" }, "SleepTimeout": { "displayText": "Čas do\nspanja", "description": "Čas pred spanjem (s=sekunde | m=minute)" }, "ShutdownTimeout": { "displayText": "Čas do\nizklopa", "description": "Čas do izklopa (m=minute)" }, "HallEffSensitivity": { "displayText": "Občut.\nHall son", "description": "Občutljivost Hallove sonde za zaznavanje spanja (1=najmanjša | ... | 9=največja)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval pred začetkom \"načina mirovanja\", ko je Hallov učinek nad pragom" }, "TemperatureUnit": { "displayText": "Enota za\ntemperaturo", "description": "Enota za temperaturo (C=celzij | F=fahrenheit)" }, "DisplayRotation": { "displayText": "Orientacija\nzaslona", "description": "D=desničar | L=levičar | S=samodejno" }, "CooldownBlink": { "displayText": "Utripanje med\nhlajenjem", "description": "Ko je konica še vroča, utripaj prikaz temperature med hlajenjem." }, "ScrollingSpeed": { "displayText": "Hitrost\nbesedila", "description": "Hitrost, s katero se prikazuje besedilo (P=počasi | H=hitro)" }, "ReverseButtonTempChange": { "displayText": "Obrni\ntipki + -?", "description": "Zamenjaj funkciji gumbov." }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nspeed", "description": "Pace of icon animations in menu (P=slow | M=medium | H=fast)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loop icon animations in main menu" }, "Brightness": { "displayText": "Screen\nbrightness", "description": "Adjust the OLED screen brightness" }, "ColourInversion": { "displayText": "Invert\nscreen", "description": "Invert the OLED screen colors" }, "LOGOTime": { "displayText": "Boot logo\nduration", "description": "Set boot logo duration (s=seconds)" }, "AdvancedIdle": { "displayText": "Več info. na\nmir. zaslonu", "description": "Prikaži več informacij z manjšo pisavo na mirovalnem zaslonu." }, "AdvancedSoldering": { "displayText": "Več info na\nzaslonu spaj.", "description": "Prikaže več informacij z manjšo pisavo na zaslonu med spajkanjem." }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Meja\nmoči", "description": "Največja dovoljena moč v vatih [W]" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibriram\nvhodno napetost?", "description": "Kalibracija VIN (nastavitve z gumbi, dolg pritisk za izhod)" }, "PowerPulsePower": { "displayText": "Pulz\nmoči", "description": "Velikost moči za vzdrževanje budnosti." }, "PowerPulseWait": { "displayText": "Power pulse\ndelay", "description": "Delay before keep-awake-pulse is triggered (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduration", "description": "Keep-awake-pulse duration (x 250ms)" }, "SettingsReset": { "displayText": "Tovarniške\nnastavitve?", "description": "Ponastavitev vseh nastavitev" }, "LanguageSwitch": { "displayText": "Jezik:\n SL Slovenščina", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_SR_CYRL.json ================================================ { "languageCode": "SR_CYRL", "languageLocalName": "Српски", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Certain settings\nwere changed!" }, "NoAccelerometerMessage": { "message": "No accelerometer\ndetected!" }, "NoPowerDeliveryMessage": { "message": "No USB-PD IC\ndetected!" }, "LockingKeysString": { "message": "LOCKED" }, "UnlockingKeysString": { "message": "UNLOCKED" }, "WarningKeysLockedString": { "message": "!LOCKED!" }, "WarningThermalRunaway": { "message": "Thermal\nRunaway" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Да ли заиста желите да вратите поставке на фабричке вредности?" }, "UVLOWarningString": { "message": "НИЗ.НАП." }, "UndervoltageString": { "message": "ПРЕНИЗАК НАПОН\n" }, "InputVoltageString": { "message": "Ул. напон: \n" }, "SleepingAdvancedString": { "message": "Спавање...\n" }, "SleepingTipAdvancedString": { "message": "Врх: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "Д", "SettingLeftChar": "Л", "SettingAutoChar": "А", "SettingSlowChar": "С", "SettingMediumChar": "M", "SettingFastChar": "Б", "SettingStartSolderingChar": "Л", "SettingStartSleepChar": "С", "SettingStartSleepOffChar": "X", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Power\nsettings", "description": "" }, "SolderingMenu": { "displayText": "Поставке\nлемљења", "description": "" }, "PowerSavingMenu": { "displayText": "Уштеда\nенергије", "description": "" }, "UIMenu": { "displayText": "Корисничко\nсучеље", "description": "" }, "AdvancedMenu": { "displayText": "Напредне\nпоставке", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Врста\nнапајања", "description": "Тип напајања; одређује најнижи радни напон. (DC=адаптер [10V] | S=батерија [3,3V по ћелији])" }, "MinVolCell": { "displayText": "Minimum\nvoltage", "description": "Minimum allowed voltage per battery cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Улазна\nснага", "description": "Снага напајања у ватима." }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD negotiation timeout in 100ms steps for compatibility with some QC chargers" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Темп.\nпојачања", "description": "Температура врха лемилице у току појачања." }, "AutoStart": { "displayText": "Врући\nстарт", "description": "Лемилица одмах по покретању прелази у режим лемљења и греје се. (Л=лемљење | С=спавати | X=спавати собна температура)" }, "TempChangeShortStep": { "displayText": "Temp change\nshort", "description": "Temperature-change-increment on short button press" }, "TempChangeLongStep": { "displayText": "Temp change\nlong", "description": "Temperature-change-increment on long button press" }, "LockingMode": { "displayText": "Allow locking\nbuttons", "description": "While soldering, hold down both buttons to toggle locking them (B=boost mode only | F=full locking)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Осетљивост\nна покрет", "description": "Осетљивост сензора покрета. (1=најмање осетљиво | ... | 9=најосетљивије)" }, "SleepTemperature": { "displayText": "Темп.\nспавања", "description": "Температура на коју се спушта лемилица након одређеног времена мировања. (C | F)" }, "SleepTimeout": { "displayText": "Време до\nспавања", "description": "Време мировања након кога лемилица спушта температуру. (m=минути | s=секунде)" }, "ShutdownTimeout": { "displayText": "Време до\nгашења", "description": "Време мировања након кога се лемилица гаси. (m=минути)" }, "HallEffSensitivity": { "displayText": "Hall sensor\nsensitivity", "description": "Sensitivity to magnets (1=најмање осетљиво | ... | 9=најосетљивије)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Интервал пре почетка \"режима спавања\" када је ефекат Хола изнад прага" }, "TemperatureUnit": { "displayText": "Јединица\nтемпературе", "description": "Јединице у којима се приказује температура. (C=целзијус | F=фаренхајт)" }, "DisplayRotation": { "displayText": "Оријентација\nекрана", "description": "Како је окренут екран. (Д=за десноруке | Л=за леворуке | А=аутоматски)" }, "CooldownBlink": { "displayText": "Упозорење\nпри хлађењу", "description": "Приказ температуре трепће приликом хлађења докле год је врх и даље врућ." }, "ScrollingSpeed": { "displayText": "Брзина\nпорука", "description": "Брзина кретања описних порука попут ове. (С=споро | Б=брзо)" }, "ReverseButtonTempChange": { "displayText": "Swap\n+ - keys", "description": "Reverse assignment of buttons for temperature adjustment" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nspeed", "description": "Pace of icon animations in menu (С=slow | M=medium | Б=fast)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loop icon animations in main menu" }, "Brightness": { "displayText": "Screen\nbrightness", "description": "Adjust the OLED screen brightness" }, "ColourInversion": { "displayText": "Invert\nscreen", "description": "Invert the OLED screen colors" }, "LOGOTime": { "displayText": "Boot logo\nduration", "description": "Set boot logo duration (s=seconds)" }, "AdvancedIdle": { "displayText": "Детаљи током\nмировања", "description": "Приказивање детаљних информација на екрану током мировања." }, "AdvancedSoldering": { "displayText": "Детаљи током\nлемљења", "description": "Приказивање детаљних информација на екрану током лемљења." }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Power\nlimit", "description": "Average maximum power the iron can use (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5 C)" }, "VoltageCalibration": { "displayText": "Калибрација\nулазног напона", "description": "Калибрисање улазног напона. Подешава се на тастере; дуги притисак за крај." }, "PowerPulsePower": { "displayText": "Power\npulse", "description": "Intensity of power of keep-awake-pulse (W=watt)" }, "PowerPulseWait": { "displayText": "Power pulse\ndelay", "description": "Delay before keep-awake-pulse is triggered (x 2.5с)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduration", "description": "Keep-awake-pulse duration (x 250мс)" }, "SettingsReset": { "displayText": "Фабричке\nпоставке", "description": "Враћање свих поставки на фабричке вредности." }, "LanguageSwitch": { "displayText": "Jезик:\n SR Српски", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_SR_LATN.json ================================================ { "languageCode": "SR_LATN", "languageLocalName": "Srpski", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Certain settings\nwere changed!" }, "NoAccelerometerMessage": { "message": "No accelerometer\ndetected!" }, "NoPowerDeliveryMessage": { "message": "No USB-PD IC\ndetected!" }, "LockingKeysString": { "message": "LOCKED" }, "UnlockingKeysString": { "message": "UNLOCKED" }, "WarningKeysLockedString": { "message": "!LOCKED!" }, "WarningThermalRunaway": { "message": "Thermal\nRunaway" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Da li zaista želite da vratite postavke na fabričke vrednosti?" }, "UVLOWarningString": { "message": "NIZ.NAP." }, "UndervoltageString": { "message": "PRENIZAK NAPON\n" }, "InputVoltageString": { "message": "Ul. napon: \n" }, "SleepingAdvancedString": { "message": "Spavanje...\n" }, "SleepingTipAdvancedString": { "message": "Vrh: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "D", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "B", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "S", "SettingStartSleepOffChar": "X", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Power\nsettings", "description": "" }, "SolderingMenu": { "displayText": "Postavke\nlemljenja", "description": "" }, "PowerSavingMenu": { "displayText": "Ušteda\nenergije", "description": "" }, "UIMenu": { "displayText": "Korisničko\nsučelje", "description": "" }, "AdvancedMenu": { "displayText": "Napredne\npostavke", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Vrsta\nnapajanja", "description": "Tip napajanja; određuje najniži radni napon. (DC=adapter [10V], S=baterija [3,3V po ćeliji])" }, "MinVolCell": { "displayText": "Minimum\nvoltage", "description": "Minimum allowed voltage per battery cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Ulazna\nsnaga", "description": "Snaga napajanja u vatima." }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD negotiation timeout in 100ms steps for compatibility with some QC chargers" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Temp.\npojačanja", "description": "Temperatura vrha lemilice u toku pojačanja." }, "AutoStart": { "displayText": "Vrući\nstart", "description": "Lemilica odmah po pokretanju prelazi u režim lemljenja i greje se. (L=lemljenje | S=spavati | X=spavati sobna temperatura)" }, "TempChangeShortStep": { "displayText": "Temp change\nshort", "description": "Temperature-change-increment on short button press" }, "TempChangeLongStep": { "displayText": "Temp change\nlong", "description": "Temperature-change-increment on long button press" }, "LockingMode": { "displayText": "Allow locking\nbuttons", "description": "While soldering, hold down both buttons to toggle locking them (B=boost mode only | F=full locking)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Osetljivost\nna pokret", "description": "Osetljivost senzora pokreta. (1=najmanje osetljivo | ... | 9=najosetljivije)" }, "SleepTemperature": { "displayText": "Temp.\nspavanja", "description": "Temperatura na koju se spušta lemilica nakon određenog vremena mirovanja. (C | F)" }, "SleepTimeout": { "displayText": "Vreme do\nspavanja", "description": "Vreme mirovanja nakon koga lemilica spušta temperaturu. (m=minuti | s=sekunde)" }, "ShutdownTimeout": { "displayText": "Vreme do\ngašenja", "description": "Vreme mirovanja nakon koga se lemilica gasi. (m=minuti)" }, "HallEffSensitivity": { "displayText": "Hall sensor\nsensitivity", "description": "Sensitivity to magnets (1=najmanje osetljivo | ... | 9=najosetljivije)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "Jedinica\ntemperature", "description": "Jedinice u kojima se prikazuje temperatura. (C=celzijus | F=farenhajt)" }, "DisplayRotation": { "displayText": "Orijentacija\nekrana", "description": "Kako je okrenut ekran. (D=za desnoruke | L=za levoruke | A=automatski)" }, "CooldownBlink": { "displayText": "Upozorenje\npri hlađenju", "description": "Prikaz temperature trepće prilikom hlađenja dokle god je vrh i dalje vruć." }, "ScrollingSpeed": { "displayText": "Brzina\nporuka", "description": "Brzina kretanja opisnih poruka poput ove. (S=sporo | B=brzo)" }, "ReverseButtonTempChange": { "displayText": "Swap\n+ - keys", "description": "Reverse assignment of buttons for temperature adjustment" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\nspeed", "description": "Pace of icon animations in menu (S=slow | M=medium | B=fast)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loop icon animations in main menu" }, "Brightness": { "displayText": "Screen\nbrightness", "description": "Adjust the OLED screen brightness" }, "ColourInversion": { "displayText": "Invert\nscreen", "description": "Invert the OLED screen colors" }, "LOGOTime": { "displayText": "Boot logo\nduration", "description": "Set boot logo duration (s=seconds)" }, "AdvancedIdle": { "displayText": "Detalji tokom\nmirovanja", "description": "Prikazivanje detaljnih informacija na ekranu tokom mirovanja." }, "AdvancedSoldering": { "displayText": "Detalji tokom\nlemljenja", "description": "Prikazivanje detaljnih informacija na ekranu tokom lemljenja." }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Power\nlimit", "description": "Average maximum power the iron can use (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibracija\nulaznog napona", "description": "Kalibrisanje ulaznog napona. Podešava se na tastere; dugi pritisak za kraj." }, "PowerPulsePower": { "displayText": "Power\npulse", "description": "Intensity of power of keep-awake-pulse (W=watt)" }, "PowerPulseWait": { "displayText": "Power pulse\ndelay", "description": "Delay before keep-awake-pulse is triggered (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Power pulse\nduration", "description": "Keep-awake-pulse duration (x 250ms)" }, "SettingsReset": { "displayText": "Fabričke\npostavke", "description": "Vraćanje svih postavki na fabričke vrednosti." }, "LanguageSwitch": { "displayText": "Jezik:\n SR Srpski", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_SV.json ================================================ { "languageCode": "SV", "languageLocalName": "Svenska", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrering\nfärdig!" }, "ResetOKMessage": { "message": "Återställning\nOK" }, "SettingsResetMessage": { "message": "Inställningar\nåterställda" }, "NoAccelerometerMessage": { "message": "Ingen\naccelerometer" }, "NoPowerDeliveryMessage": { "message": "Ingen USB-PD IC\nhittades!" }, "LockingKeysString": { "message": "LÅST" }, "UnlockingKeysString": { "message": "UPPLÅST" }, "WarningKeysLockedString": { "message": "!LÅST!" }, "WarningThermalRunaway": { "message": "Termisk\nFlykt" }, "WarningTipShorted": { "message": "!Spets Kortsluten!" }, "SettingsCalibrationWarning": { "message": "Före omstart, säkerställ att spetsen och handtaget är i rumstemperatur!" }, "CJCCalibrating": { "message": "kalibrerar\n" }, "SettingsResetWarning": { "message": "Är du säker på att du vill återställa inställningarna?" }, "UVLOWarningString": { "message": "DC LÅG" }, "UndervoltageString": { "message": "Underspänning\n" }, "InputVoltageString": { "message": "Inspän. V: \n" }, "SleepingAdvancedString": { "message": "Viloläge...\n" }, "SleepingTipAdvancedString": { "message": "Spets: \n" }, "ProfilePreheatString": { "message": "Förvärmning\n" }, "ProfileCooldownString": { "message": "Nedkyldning\n" }, "DeviceFailedValidationWarning": { "message": "Din enhet är sannerligen oäkta!" }, "TooHotToStartProfileWarning": { "message": "För varm för att\nstarta profilen!" } }, "characters": { "SettingRightChar": "H", "SettingLeftChar": "V", "SettingAutoChar": "A", "SettingSlowChar": "L", "SettingMediumChar": "M", "SettingFastChar": "S", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "V", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "T", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Effekt-\ninställning", "description": "" }, "SolderingMenu": { "displayText": "Lödnings-\ninställning", "description": "" }, "PowerSavingMenu": { "displayText": "Vilo-\nläge", "description": "" }, "UIMenu": { "displayText": "Användar-\ngränssnitt", "description": "" }, "AdvancedMenu": { "displayText": "Avancerade\nalternativ", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Ström-\nkälla", "description": "Strömkälla. Anger lägsta spänning. (DC 10V) (S 3.3V per cell)" }, "MinVolCell": { "displayText": "Minimim-\nspänning", "description": "Minimumspänning per cell (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nspänning", "description": "Maximal QC-spänning enheten skall efterfråga" }, "PDNegTimeout": { "displayText": "PD\npauser", "description": "PD förhandlings pauser i 100ms steg för kompatibilitet med vissa PD laddare" }, "USBPDMode": { "displayText": "PD\nMode", "description": "Slår på PPS & EPR lägen" }, "BoostTemperature": { "displayText": "Turbo-\ntemp", "description": "Temperatur i \"turbo-läge\"" }, "AutoStart": { "displayText": "Auto\nstart", "description": "Startar automatiskt lödpennan vid uppstart. (L=Lödning | V=Viloläge | R=Viloläge Rumstemperatur)" }, "TempChangeShortStep": { "displayText": "Temp.just\nkorttryck", "description": "Temperaturjustering vid kort knapptryckning" }, "TempChangeLongStep": { "displayText": "Temp.just\nlångtryck", "description": "Temperaturjustering vid lång knapptryckning" }, "LockingMode": { "displayText": "Tillåt lås\nvia knappar", "description": "Vid lödning, håll nere bägge knappar för att slå på lås (T=Bara turbo | F=Fullt lås)" }, "ProfilePhases": { "displayText": "Profil-\nfaser", "description": "Antal faser i profil läge" }, "ProfilePreheatTemp": { "displayText": "Förvärmnings-\ntemp", "description": "Förvärm till denna temperatur i början av provil läget" }, "ProfilePreheatSpeed": { "displayText": "Förvärmnings-\nhastighet", "description": "Förvärm enligt denna hastighet (grader per sekund)" }, "ProfilePhase1Temp": { "displayText": "Fas 1\nTemp", "description": "Måltemperatur i slutet av denna fas" }, "ProfilePhase1Duration": { "displayText": "Fas 1\nTidslängd", "description": "Mållängd av denna fasen (sekunder)" }, "ProfilePhase2Temp": { "displayText": "Fas 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Fas 2\nTidslängd", "description": "" }, "ProfilePhase3Temp": { "displayText": "Fas 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Fas 3\nTidslängd", "description": "" }, "ProfilePhase4Temp": { "displayText": "Fas 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Fas 4\nTidslängd", "description": "" }, "ProfilePhase5Temp": { "displayText": "Fas 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Fas 5\nTidslängd", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Nedkylnings-\nhastighet", "description": "Kyl ned i denna hastighet i slutet av profilen (grader per sekund)" }, "MotionSensitivity": { "displayText": "Rörelse-\nkänslighet", "description": "Rörelsekänslighet (1=minst känslig | ... | 9=mest känslig)" }, "SleepTemperature": { "displayText": "Vilo-\ntemp", "description": "Vilotemperatur (C)" }, "SleepTimeout": { "displayText": "Vilo-\ntimeout", "description": "Vilo-timeout (m=Minuter | s=Sekunder)" }, "ShutdownTimeout": { "displayText": "Avstängn.\ntimeout", "description": "Avstängnings-timeout (Minuter)" }, "HallEffSensitivity": { "displayText": "Sensor-\nkänslght", "description": "Känslighet för halleffekt-sensorn för viloläges-detektering (1=minst känslig | ... | 9=mest känslig)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "Temperatur-\nenheter", "description": "Temperaturenhet (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "Visnings\nläge", "description": "Visningsläge (H=Högerhänt | V=Vänsterhänt | A=Automatisk)" }, "CooldownBlink": { "displayText": "Nedkylnings-\nblink", "description": "Blinka temperaturen medan spetsen kyls av och fortfarande är varm." }, "ScrollingSpeed": { "displayText": "Beskrivning\nrullhast.", "description": "Hastighet som den här texten rullar i" }, "ReverseButtonTempChange": { "displayText": "Omvända\n+- knappar", "description": "Omvänd ordning för temperaturjustering via plus/minus knapparna" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.-\nhastighet", "description": "Animationshastighet för ikoner i menyer (L=långsam | M=medel | S=snabb)" }, "AnimLoop": { "displayText": "Anim.\nloop", "description": "Loopa animationer i huvudmeny" }, "Brightness": { "displayText": "Skärmens\nLjusstyrka", "description": "Justera OLED skärmens ljusstyrka" }, "ColourInversion": { "displayText": "Invertera\nskärm", "description": "Invertera OLED skärmens färger" }, "LOGOTime": { "displayText": "Start logo\nTidslängd", "description": "Sätt uppstartslogotypens tidslängd (s=sekunder)" }, "AdvancedIdle": { "displayText": "Detaljerad\nvid inaktiv", "description": "Visa detaljerad information i mindre typsnitt när inaktiv." }, "AdvancedSoldering": { "displayText": "Detaljerad\nlödng.skärm", "description": "Visa detaljerad information vid lödning" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Tillåter BLE" }, "PowerLimit": { "displayText": "Max-\neffekt", "description": "Maximal effekt som enheten kan använda (Watt)" }, "CalibrateCJC": { "displayText": "Kalibrera CJC\nnästa uppstart", "description": "Vid nästa uppstart kommer spets Cold Junction Compensation kalibreras (ej nödvändigt om Delta T är < 5°C)" }, "VoltageCalibration": { "displayText": "Kalibrera\ninspänning?", "description": "Inspänningskalibrering. Knapparna justerar, håll inne för avslut" }, "PowerPulsePower": { "displayText": "Effekt\npuls", "description": "Intensiteten av effekt för håll-vaken-puls (W=watt)" }, "PowerPulseWait": { "displayText": "Effekt puls\nfördröjning", "description": "Fördröjning innan håll-vaken-pulsen skickas (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Effekt puls\ntidsmängd", "description": "Håll-vaken-puls varaktighet (x 250ms)" }, "SettingsReset": { "displayText": "Fabriks-\ninställ?", "description": "Återställ alla inställningar" }, "LanguageSwitch": { "displayText": "Språk:\n SV Svenska", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_TR.json ================================================ { "languageCode": "TR", "languageLocalName": "Türkçe", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrasyon\ntamam!" }, "ResetOKMessage": { "message": "Sıfırlama Tamam" }, "SettingsResetMessage": { "message": "Ayarlar\nSıfırlandı" }, "NoAccelerometerMessage": { "message": "İvme sensörü\ntespit edilmedi!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\ntespit edilmedi!" }, "LockingKeysString": { "message": "KİLİTLİ" }, "UnlockingKeysString": { "message": "KİLİT AÇIK" }, "WarningKeysLockedString": { "message": "!KİLİTLİ!" }, "WarningThermalRunaway": { "message": "Termal\nKaçak" }, "WarningTipShorted": { "message": "!Uç Kısa Devre!" }, "SettingsCalibrationWarning": { "message": "Yeniden başlatmadan önce uç ve sapın oda sıcaklığında olduğundan emin olun!" }, "CJCCalibrating": { "message": "kalibre ediliyor\n" }, "SettingsResetWarning": { "message": "Ayarları varsayılan değerlere sıfırlamak istediğinizden emin misiniz?" }, "UVLOWarningString": { "message": "Güç Az" }, "UndervoltageString": { "message": "Düşük Voltaj\n" }, "InputVoltageString": { "message": "Giriş V: \n" }, "SleepingAdvancedString": { "message": "Bekleme Modu...\n" }, "SleepingTipAdvancedString": { "message": "Uç: \n" }, "ProfilePreheatString": { "message": "Ön Isıtma\n" }, "ProfileCooldownString": { "message": "Soğuma\n" }, "DeviceFailedValidationWarning": { "message": "Cihazınız büyük olasılıkla sahte!" }, "TooHotToStartProfileWarning": { "message": "Profil başlatmak için\nçok sıcak" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "O", "SettingSlowChar": "Y", "SettingMediumChar": "O", "SettingFastChar": "H", "SettingStartSolderingChar": "L", "SettingStartSleepChar": "U", "SettingStartSleepOffChar": "S", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Güç\nAyarları", "description": "" }, "SolderingMenu": { "displayText": "Lehimleme\nAyarları", "description": "" }, "PowerSavingMenu": { "displayText": "Uyku\nModları", "description": "" }, "UIMenu": { "displayText": "Kullanıcı\nArayüzü", "description": "" }, "AdvancedMenu": { "displayText": "Gelişmiş\nAyarlar", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "GÇKYN\n", "description": "\"Güç Kaynağı\". En düşük çalışma voltajını ayarlar. (DC 10V) (S 3.3V hücre başına)" }, "MinVolCell": { "displayText": "Minimum\nVoltaj", "description": "Pil hücresi başına izin verilen minimum voltaj (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nvoltajı", "description": "Max istenecek QC voltajı" }, "PDNegTimeout": { "displayText": "PD\nTimeout", "description": "Bazı QC şarj cihazlarıyla uyumluluk için 100ms adımlarında PD pazarlık zaman aşımı" }, "USBPDMode": { "displayText": "PD\nMode", "description": "PPS & EPR modlarını etkinleştirir" }, "BoostTemperature": { "displayText": "YKSC\n", "description": "Yüksek Performans Modu Sıcaklığı" }, "AutoStart": { "displayText": "OTOBAŞ\n", "description": "Güç verildiğinde otomatik olarak lehimleme modunda başlat. (L=Lehimleme Modu | U=Uyku Modu | S=Uyku Modu Oda Sıcaklığı)" }, "TempChangeShortStep": { "displayText": "Sıcaklık değişimi\nkısa", "description": "Kısa basışlardaki sıcaklık derecesi atlama oranı" }, "TempChangeLongStep": { "displayText": "Sıcaklık değişimi\nuzun", "description": "Uzun başışlardaki sıcaklık derecesi atlama oranı" }, "LockingMode": { "displayText": "Kilitleme\nİzni", "description": "Lehimleme sırasında, her iki düğmeye basılı tutarak kilitleme modunu değiştirin (B=Sadece performans modu | F=tam kilit)" }, "ProfilePhases": { "displayText": "Profil\nAşamaları", "description": "Profil modundaki aşamaların sayısı" }, "ProfilePreheatTemp": { "displayText": "Ön Isıtma\nSıcaklık", "description": "Profil modunun başlangıcında bu sıcaklığa kadar ön ısıtma yapar" }, "ProfilePreheatSpeed": { "displayText": "Ön Isıtma\nHızı", "description": "Bu hızda ön ısıtma yapın (saniye başına derece)" }, "ProfilePhase1Temp": { "displayText": "Aşama 1\nSıcaklık", "description": "Bu aşamanın sonunda hedeflenen sıcaklık" }, "ProfilePhase1Duration": { "displayText": "Aşama 1\nSüre", "description": "Bu aşamanın hedef süresi (saniye)" }, "ProfilePhase2Temp": { "displayText": "Aşama 2\nSıcaklık", "description": "" }, "ProfilePhase2Duration": { "displayText": "Aşama 2\nSüre", "description": "" }, "ProfilePhase3Temp": { "displayText": "Aşama 3\nSıcaklık", "description": "" }, "ProfilePhase3Duration": { "displayText": "Aşama 3\nSüre", "description": "" }, "ProfilePhase4Temp": { "displayText": "Aşama 4\nSıcaklık", "description": "" }, "ProfilePhase4Duration": { "displayText": "Aşama 4\nSüre", "description": "" }, "ProfilePhase5Temp": { "displayText": "Aşama 5\nSıcaklık", "description": "" }, "ProfilePhase5Duration": { "displayText": "Aşama 5\nSüre", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Soğuma\nHızı", "description": "Profil modunun sonunda bu hızda soğuma yapın (saniye başına derece)" }, "MotionSensitivity": { "displayText": "HARHAS\n", "description": "Hareket Hassasiyeti (1=En az duyarlı | ... | 9=En duyarlı)" }, "SleepTemperature": { "displayText": "BKSC\n", "description": "Bekleme Modu Sıcaklığı (C)" }, "SleepTimeout": { "displayText": "BMZA\n", "description": "Bekleme Modu Zaman Aşımı (Dakika | Saniye)" }, "ShutdownTimeout": { "displayText": "KPTZA\n", "description": "Kapatma Zaman Aşımı (Dakika)" }, "HallEffSensitivity": { "displayText": "Hall Sensör\nHassasiyeti", "description": "Mıknatıslara duyarlılık (1=En az duyarlı | ... | 9=En duyarlı)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Hall etkisi eşiğin üzerinde olduğunda \"uyku modu\" başlamadan önceki aralık" }, "TemperatureUnit": { "displayText": "SCKBRM\n", "description": "Sıcaklık Birimi (C=Celsius | F=Fahrenheit)" }, "DisplayRotation": { "displayText": "GRNYÖN\n", "description": "Görüntü Yönlendirme (R=Sağlak | L=Solak | O=Otomatik)" }, "CooldownBlink": { "displayText": "SĞGÖST\n", "description": "Soğutma ekranında uç hala sıcakken derece gösterilsin." }, "ScrollingSpeed": { "displayText": "YZKYHZ\n", "description": "Bu yazının kayma hızı (Y=Yavaş | H=Hızlı)" }, "ReverseButtonTempChange": { "displayText": "Düğme Yerleri\nRotasyonu", "description": "\"Düğme Yerleri Rotasyonu\" Sıcaklık ayar düğmelerinin yerini değiştirin" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Animasyon\nHızı", "description": "Menüdeki simge animasyonlarının hızı (Y=Yavaş | O=Orta | H=Hızlı)" }, "AnimLoop": { "displayText": "Animasyon\nDöngüsü", "description": "Ana menüde simge animasyonlarının döngüsü" }, "Brightness": { "displayText": "Ekran\nparlaklığı", "description": "OLED ekran parlaklığını ayarlar" }, "ColourInversion": { "displayText": "Ekran\nRenkleri", "description": "OLED ekran renklerini ters çevir" }, "LOGOTime": { "displayText": "Boot Logo\nSüresi", "description": "Boot logo süresi (s=saniye)" }, "AdvancedIdle": { "displayText": "AYRBİL\n", "description": "Boş ekranda ayrıntılı bilgileri daha küçük bir yazı tipi ile göster." }, "AdvancedSoldering": { "displayText": "GELLHM\n", "description": "\"Gelişmiş Lehimleme\" Lehimleme yaparken detaylı bilgi göster" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Bluetooth LE'yi etkinleştirir" }, "PowerLimit": { "displayText": "Güç\nlimiti", "description": "Havyanın kullanacağı en yüksek güç (W=Watts)" }, "CalibrateCJC": { "displayText": "CJC Kalibrasyonu\nSonraki Boot'ta", "description": "Sonraki boot'ta uç Soğuk Nokta Kompansasyonu kalibre edilecek (Delta T < 5°C ise gerekmez)" }, "VoltageCalibration": { "displayText": "VOL KAL?\n", "description": "Voltaj Girişi Kalibrasyonu. Düğmeler ayarlar, çıkmak için uzun bas." }, "PowerPulsePower": { "displayText": "Güç\nDarbeleri", "description": "Güç girişi voltajı ölçüm yoğunluğunu sık tut." }, "PowerPulseWait": { "displayText": "Güç Darbesi\nGecikmesi", "description": "Uyanık tutma darbesinin tetiklenmeden önceki gecikme süresi (x 2.5s)" }, "PowerPulseDuration": { "displayText": "Güç Darbesi\nSüresi", "description": "Uyanık tutma darbesi süresi (x 250ms)" }, "SettingsReset": { "displayText": "SIFIRLA?\n", "description": "Bütün ayarları sıfırlar" }, "LanguageSwitch": { "displayText": "Dil:\n TR Türkçe", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_UK.json ================================================ { "languageCode": "UK", "languageLocalName": "Українська", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "КХС\nвідкалібровано!" }, "ResetOKMessage": { "message": "Скид. OK" }, "SettingsResetMessage": { "message": "Налаштування\nскинуті!" }, "NoAccelerometerMessage": { "message": "Акселерометр\nне виявлено!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\nне виявлено!" }, "LockingKeysString": { "message": "ЗАБЛОК." }, "UnlockingKeysString": { "message": "РОЗБЛОК." }, "WarningKeysLockedString": { "message": "!ЗАБЛОК!" }, "WarningThermalRunaway": { "message": "Некерований\nрозігрів" }, "WarningTipShorted": { "message": "!Жало закорочено!" }, "SettingsCalibrationWarning": { "message": "Під час наступного завантаження переконайтеся, що жало і ручка мають кімнатну температуру!" }, "CJCCalibrating": { "message": "калібрування\n" }, "SettingsResetWarning": { "message": "Ви дійсно хочете скинути налаштування до значень за замовчуванням? (A=Так, В=Ні)" }, "UVLOWarningString": { "message": "АККУМ--" }, "UndervoltageString": { "message": "Низька напруга\n" }, "InputVoltageString": { "message": "Жив.(B): \n" }, "SleepingAdvancedString": { "message": "Сон...\n" }, "SleepingTipAdvancedString": { "message": "Жало: \n" }, "ProfilePreheatString": { "message": "Попередній\nрозігрів" }, "ProfileCooldownString": { "message": "Охолодження\n" }, "DeviceFailedValidationWarning": { "message": "Вірогідно ваш пристрій підробний!" }, "TooHotToStartProfileWarning": { "message": "Занадто гараче для\nзміни профілів" } }, "characters": { "SettingRightChar": "П", "SettingLeftChar": "Л", "SettingAutoChar": "A", "SettingSlowChar": "Н", "SettingMediumChar": "С", "SettingFastChar": "М", "SettingStartSolderingChar": "П", "SettingStartSleepChar": "С", "SettingStartSleepOffChar": "К", "SettingLockBoostChar": "Т", "SettingLockFullChar": "П" }, "menuGroups": { "PowerMenu": { "displayText": "Параметри\nживлення", "description": "" }, "SolderingMenu": { "displayText": "Параметри\nпайки", "description": "" }, "PowerSavingMenu": { "displayText": "Режим сну\n", "description": "" }, "UIMenu": { "displayText": "Параметри\nінтерфейсу", "description": "" }, "AdvancedMenu": { "displayText": "Додаткові\nпараметри", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Режим\nЗамовчуванню" }, "USBPDModeNoDynamic": { "displayText": "Без\nДинамічного" }, "USBPDModeSafe": { "displayText": "Безпечний\nРежим" }, "TipTypeAuto": { "displayText": "Авто\nВизначення" }, "TipTypeT12Long": { "displayText": "TS100\nДовге" }, "TipTypeT12Short": { "displayText": "Pine\nКоротке" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Джерело\nживлення", "description": "Встановлює напругу відсічки. (DC - 10V) (3S - 9.9V | 4S - 13.2V | 5S - 16.5V | 6S - 19.8V)" }, "MinVolCell": { "displayText": "Мін.\nнапруга", "description": "Мінімальна дозволена напруга на комірку (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "Потужність\nдж. живлення", "description": "Потужність ДЖ в Ватах" }, "PDNegTimeout": { "displayText": "PD\nЗатримка", "description": "Затримка у 100мс інкрементах для PD для сумісності з деякими версіями QC (0: вимкнена)" }, "USBPDMode": { "displayText": "PD\nРежим", "description": "Вмикає режими PPS & EPR." }, "BoostTemperature": { "displayText": "Темпер.\nТурбо", "description": "Температура \"Турбо\" режиму" }, "AutoStart": { "displayText": "Гарячий\nстарт", "description": "Режим запуску паяльника (П=Пайка | С=Сон | К=Сон при кімн. темп.)" }, "TempChangeShortStep": { "displayText": "Зміна темп.\nкоротким", "description": "Зміна температуру при короткому натисканні!" }, "TempChangeLongStep": { "displayText": "Зміна темп.\nдовгим", "description": "Зміна температуру при довгому натисканні!" }, "LockingMode": { "displayText": "Дозволити\nблок. кнопок", "description": "Під час пайки тривале натискання обох кнопок заблокує їх (Т=Тільки турбо | П=Повне)" }, "ProfilePhases": { "displayText": "Етапи\nпрофілів", "description": "Кількість етапів в режимі профілів" }, "ProfilePreheatTemp": { "displayText": "Температура\nПоп.Розігріву", "description": "Попередньо розігріти до цієї температури на початку режимку профілів" }, "ProfilePreheatSpeed": { "displayText": "Швидкість\nПоп.Розігріву", "description": "Розігрівати з швидкістю (t° у сек)" }, "ProfilePhase1Temp": { "displayText": "Етап 1\nТемпература", "description": "Температура на кінці цього етапу" }, "ProfilePhase1Duration": { "displayText": "Етап 1\nТривалість", "description": "Тривалість цього етапу (сек)" }, "ProfilePhase2Temp": { "displayText": "Етап 2\nТемпература", "description": "" }, "ProfilePhase2Duration": { "displayText": "Етап 2\nТривалість", "description": "" }, "ProfilePhase3Temp": { "displayText": "Етап 3\nТемпература", "description": "" }, "ProfilePhase3Duration": { "displayText": "Етап 3\nТривалість", "description": "" }, "ProfilePhase4Temp": { "displayText": "Етап 4\nТемпература", "description": "" }, "ProfilePhase4Duration": { "displayText": "Етап 4\nТривалість", "description": "" }, "ProfilePhase5Temp": { "displayText": "Етап 5\nТемпература", "description": "" }, "ProfilePhase5Duration": { "displayText": "Етап 5\nТривалість", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Швидкість\nОхолодження", "description": "Швидкість охолодження на кінці режиму профілів (t° у сек)" }, "MotionSensitivity": { "displayText": "Чутливість\nдатчику руху", "description": "Акселерометр (1=мін. чутливості | ... | 9=макс. чутливість)" }, "SleepTemperature": { "displayText": "Темпер.\nсну", "description": "Температура режиму сну (C° | F°)" }, "SleepTimeout": { "displayText": "Тайм-аут\nсну", "description": "Час до переходу до сну (Хв | Сек)" }, "ShutdownTimeout": { "displayText": "Часу до\nвимкнення", "description": "Час до вимкнення (Хв)" }, "HallEffSensitivity": { "displayText": "Чутливість\nДатчику Холла", "description": "Чутливість датчика Холла при виявленні сну (1=мін. чутливість | ... | 9=макс. чутливість)" }, "HallEffSleepTimeout": { "displayText": "Датчик Холла\nЧас сну", "description": "Проміжок часу до \"часу сну\" за умови спрацювання датчику Холла" }, "TemperatureUnit": { "displayText": "Формат темпе-\nратури(C°/F°)", "description": "Одиниця виміру температури (C=Цельсій | F=Фаренгейт)" }, "DisplayRotation": { "displayText": "Обертання\nекрану", "description": "Орієнтація екрану (П=Правша | Л=Лівша | A=Автооберт.)" }, "CooldownBlink": { "displayText": "Показ t° при\nохолодженні", "description": "Показувати температуру на екрані охолодження, поки жало залишається гарячим, при цьому екран мерехтить" }, "ScrollingSpeed": { "displayText": "Швидкість\nтексту", "description": "Швидкість прокрутки тексту (Н=Низькa | М=Максимальна)" }, "ReverseButtonTempChange": { "displayText": "Інвертувати\nкнопки +-?", "description": "Інвертувати кнопки зміни температури." }, "ReverseButtonSettings": { "displayText": "Поміняти\nклавіші A і B", "description": "Зворотне призначення кнопок для меню Налаштування" }, "AnimSpeed": { "displayText": "Швидкість\nанімації", "description": "Швидкість анімації іконок у меню (Н=Низькa | С=Середня | М=Максимальна)" }, "AnimLoop": { "displayText": "Циклічна\nанімація", "description": "Циклічна анімація іконок у меню" }, "Brightness": { "displayText": "Яскравість\nекрану", "description": "Налаштування контрасту/яскравості OLED екрану" }, "ColourInversion": { "displayText": "Інверт\nекрану", "description": "Інвертувати кольори на OLED екрані" }, "LOGOTime": { "displayText": "Тривалість\nлоготипу при запуску", "description": "Поточна тривалість показу лого при запуску (сек)" }, "AdvancedIdle": { "displayText": "Детальний ре-\nжим очікуван.", "description": "Показувати детальну інформацію маленьким шрифтом на домашньому екрані" }, "AdvancedSoldering": { "displayText": "Детальний\nрежим пайки", "description": "Показувати детальну інформацію при пайці." }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Увімкнути BLE" }, "PowerLimit": { "displayText": "Макс.\nпотуж.", "description": "Макс. потужність, яку може використовувати паяльник (Ватт)" }, "CalibrateCJC": { "displayText": "Калібрувати КХС\nпри наступному запуску", "description": "При наступному запуску буде відкалібровано Компенсацію Холодного Спаю жала (непотрібне при різниці температур < 5°C)" }, "VoltageCalibration": { "displayText": "Калібрування\nнапруги", "description": "Калібрування напруги входу. Налаштувати кнопками, натиснути і утримати щоб завершити." }, "PowerPulsePower": { "displayText": "Пульс.\nНавантаж.", "description": "Деякі PowerBank-и з часом вимк. живлення, якщо пристрій споживає дуже мало енергії)" }, "PowerPulseWait": { "displayText": "Час між імп.\nнапруги", "description": "Час між імпульсами напруги яка не дає PowerBank-у заснути (x 2.5с)" }, "PowerPulseDuration": { "displayText": "Тривалість\nімп. напруги", "description": "Тривалість імпульсу напруги яка не дає PowerBank-у заснути (x 250мс)" }, "SettingsReset": { "displayText": "Скинути всі\nналаштування?", "description": "Скидання всіх параметрів до стандартних значень." }, "LanguageSwitch": { "displayText": "Мова:\n UK Українська", "description": "" }, "SolderingTipType": { "displayText": "Тип Жала", "description": "Оберіть відповідний тип жала" } } } ================================================ FILE: Translations/translation_UZ.json ================================================ { "languageCode": "UZ", "languageLocalName": "O'zbek", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Kalibrovka\nyakunlandi!" }, "ResetOKMessage": { "message": "Sozlamalar\ntiklandi" }, "SettingsResetMessage": { "message": "Ayrim sozlamalar\no'zgartirildi" }, "NoAccelerometerMessage": { "message": "Akselerometr\ntopilmadi!" }, "NoPowerDeliveryMessage": { "message": "USB-PD IC\ntopilmadi!" }, "LockingKeysString": { "message": "QULFLANDI" }, "UnlockingKeysString": { "message": "QULF OCHILDI" }, "WarningKeysLockedString": { "message": "!QULFLANGAN!" }, "WarningThermalRunaway": { "message": "Issiqlik\nqochishi" }, "WarningTipShorted": { "message": "!Uchida qisqa tutashuv!" }, "SettingsCalibrationWarning": { "message": "Qayta yuklashdan oldin, uchi va tutqich xona haroratida ekanligiga ishonch hosil qiling!" }, "CJCCalibrating": { "message": "Kalibrovka\nqilinmoqda" }, "SettingsResetWarning": { "message": "Sozlamalarni standart holatga qaytarishni istaysizmi?" }, "UVLOWarningString": { "message": "DC PAST" }, "UndervoltageString": { "message": "Past kuchlanish\n" }, "InputVoltageString": { "message": "Kirish kuchlanishi: \n" }, "SleepingAdvancedString": { "message": "Uyqu holati...\n" }, "SleepingTipAdvancedString": { "message": "Uch: \n" }, "ProfilePreheatString": { "message": "Qizdirish\n" }, "ProfileCooldownString": { "message": "Sovutish\n" }, "DeviceFailedValidationWarning": { "message": "Qurilmangiz soxta bo'lishi mumkin!" }, "TooHotToStartProfileWarning": { "message": "Profilni boshlash uchun\njuda issiq" } }, "characters": { "SettingRightChar": "O", "SettingLeftChar": "C", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "O", "SettingFastChar": "T", "SettingStartSolderingChar": "P", "SettingStartSleepChar": "U", "SettingStartSleepOffChar": "X", "SettingLockBoostChar": "B", "SettingLockFullChar": "T" }, "menuGroups": { "PowerMenu": { "displayText": "Quvvat\nsozlamalari", "description": "" }, "SolderingMenu": { "displayText": "Paylash\nsozlamalari", "description": "" }, "PowerSavingMenu": { "displayText": "Uyqu\nrejimi", "description": "" }, "UIMenu": { "displayText": "Foydalanuvchi\ninterfeysi", "description": "" }, "AdvancedMenu": { "displayText": "Kengaytirilgan\nsozlamalar", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Quvvat\nmanbai", "description": "Batareya haddan tashqari zaryadsizlanishini oldini olish uchun kuchlanish chegarasini o'rnatish (DC 10V) (S=3.3V har bir yacheyka uchun, quvvat PWR chegarasini o'chirish)" }, "MinVolCell": { "displayText": "Minimal\nkuchlanish", "description": "Batareya yacheyka uchun minimal ruxsat etilgan kuchlanish (3S: 3 - 3.7V | 4-6S: 2.4 - 3.7V)" }, "QCMaxVoltage": { "displayText": "QC\nvoltage", "description": "Max QC voltage the iron should negotiate for" }, "PDNegTimeout": { "displayText": "PD\ntimeout", "description": "PD negotiation timeout in 100ms steps for compatibility with some QC chargers" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Kuchaytirish\nharorati", "description": "\"Boost mode\" rejimida uch harorati" }, "AutoStart": { "displayText": "Boshlash\nholati", "description": "P=paylash temperaturasigacha qizdirish | U=qo'zg'atilmagunicha uyqu rejimida ushlash | X=qo'zg'atilmagunicha qizdirilmagan holda ushlash" }, "TempChangeShortStep": { "displayText": "Tugmaning qisqa\nbosilishi", "description": "Qisqa bosilgandagi harorat o'zgarishi-oshirish" }, "TempChangeLongStep": { "displayText": "Tugmaning uzoqroq\nbosilishi", "description": "Uzoqroq bosilgandagi harorat o'zgarishi-oshirish" }, "LockingMode": { "displayText": "Tugmalarni qulflashni\nfaollashtirish", "description": "Qulflash uchun paylash davomida ikkala tugmani bosib turing (B=faqat boost mode uchun | T=to'liq qulflash)" }, "ProfilePhases": { "displayText": "Profil\nbosqichlari", "description": "Profil rejimlarida bosqichlar soni" }, "ProfilePreheatTemp": { "displayText": "Dastlabgi\nHarorat", "description": "Profil rejimida dastlab ushbu haroratga qizdirish" }, "ProfilePreheatSpeed": { "displayText": "Qizdirish\nTezligi", "description": "Ushbu tezlikda qizdirish (1 sekundda shuncha daraja)" }, "ProfilePhase1Temp": { "displayText": "1-faza\nHarorati", "description": "Bu fazaning oxirida mo'ljallangan harorat" }, "ProfilePhase1Duration": { "displayText": "1-faza\nDavomiyligi", "description": "Ushbu fazaning davomiyligi (sekund)" }, "ProfilePhase2Temp": { "displayText": "2-faza\nHarorati", "description": "" }, "ProfilePhase2Duration": { "displayText": "2-faza\nDavomiyligi", "description": "" }, "ProfilePhase3Temp": { "displayText": "3-faza\nHarorati", "description": "" }, "ProfilePhase3Duration": { "displayText": "3-faza\nDavomiyligi", "description": "" }, "ProfilePhase4Temp": { "displayText": "4-faza\nHarorati", "description": "" }, "ProfilePhase4Duration": { "displayText": "4-faza\nDavomiyligi", "description": "" }, "ProfilePhase5Temp": { "displayText": "5-faza\nHarorati", "description": "" }, "ProfilePhase5Duration": { "displayText": "5-faza\nDavomiyligi", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Sovutish\ntezligi", "description": "Profil rejimi oxirida bu tezlikda sovutish (1 sekundda shuncha daraja)" }, "MotionSensitivity": { "displayText": "Harakat\nsezgirligi", "description": "1=quyi sezgirlik | ... | 9=eng yuqori sezgirlik" }, "SleepTemperature": { "displayText": "Uyqu\nharorati", "description": "\"Uyqu holati\"dagi uch harorati" }, "SleepTimeout": { "displayText": "Uyquga ketish\nvaqti", "description": "\"Uyqu holati\" boshlanishidan oldingi interval sleep mode (s=sekund | m=minut)" }, "ShutdownTimeout": { "displayText": "O'chish\nvaqti", "description": "Temirni o'chirishdan oldingi interval (m=minut)" }, "HallEffSensitivity": { "displayText": "Hall sensori\nsezgirligi", "description": "Magnitlarga nisbatan sezgirlik darajasi (1=quyi sezgirlik | ... | 9=eng yuqori sezgirlik)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "Harorat o'lchov\nbirligi", "description": "C=°Selsiy | F=°Fahrenheit" }, "DisplayRotation": { "displayText": "Ekran\nyo'nalishi", "description": "O=o'ng qo'l | C=chap qo'l | A=avtomatik" }, "CooldownBlink": { "displayText": "Sovutish\nindikatori", "description": "Uchi qizigan bo'sh turgan holatida harorat o'lchovini yangilab turish" }, "ScrollingSpeed": { "displayText": "Matn aylanish\ntezligi", "description": "Matn aylanish tezligini sozlash (S=sekin | T=tez)" }, "ReverseButtonTempChange": { "displayText": "(+) va (-) tugmalarni\nalmashtirish", "description": "Harorat o'zgarishi uchun tugmachalarni vazifasini almashish" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Anim.\ntezligi", "description": "Menyudagi ikonka animatsiyalari tezligini sozlash (S=sekin | O=o'rtacha | T=tez)" }, "AnimLoop": { "displayText": "Anim.\nqaytarilishi", "description": "Bosh menyudagi ikonka anim. qaytarilishi" }, "Brightness": { "displayText": "Ekran\nyorqinligi", "description": "OLED ekran yorqinligini sozlash" }, "ColourInversion": { "displayText": "Ranglarni\ninvert qilish", "description": "OLED ekran ranglarini teskari qilish" }, "LOGOTime": { "displayText": "Yuklanish logosi\ndavomiyligi", "description": "Yuklanish logosi davomiyligini o'rnatish (s=sekund)" }, "AdvancedIdle": { "displayText": "Batafsil\nbo'sh turgandagi ekran", "description": "B'sh turgandagi ekranda kichik shriftda batafsil ma’lumotni ko'rsatish" }, "AdvancedSoldering": { "displayText": "Batafsil\npayvandlash ekrani", "description": "Payvandlash ekrani uchun kichik shrift bilan batafsil ma’lumotni ko'rsatish" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Faollashtirish BLE" }, "PowerLimit": { "displayText": "Quvvat\nchegarasi", "description": "Temir foydalanishi mumkin bo'lgan o'rtacha maksimal quvvat (W=watt)" }, "CalibrateCJC": { "displayText": "Keyingi yuklashda\nCJC kalibrovkasi", "description": "Keyingi yuklashda Sovuq Tugun Kompensatsiyasini (CJC) kalibrlash (Delta T < 5°C bo'lsa, talab qilinmaydi)" }, "VoltageCalibration": { "displayText": "Kirish kuchlanishini\nkalibrlash", "description": "VIN kalibrovkasini boshlash (chiqish uchun uzoq bosib turing)" }, "PowerPulsePower": { "displayText": "Quvvat\npulsi", "description": "Uxlashdan saqlash pulsining quvvat intensivligi (W=watt)" }, "PowerPulseWait": { "displayText": "Quvvat pulsi\nkechikishi", "description": "Uxlashdan saqlash pulsi boshlanishigacha bo'lgan kechikish (x 2.5 soniya)" }, "PowerPulseDuration": { "displayText": "Quvvat pulsi\ndavomiyligi", "description": "Uxlashdan saqlash pulsi davomiyligi (x 250ms)" }, "SettingsReset": { "displayText": "Sozlamalarni\nqayta tiklash", "description": "Barcha sozlamalarni odatiy holatga qaytarish" }, "LanguageSwitch": { "displayText": "Til:\n UZ O'zbek tili", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_VI.json ================================================ { "languageCode": "VI", "languageLocalName": "Tieng Viet", "tempUnitFahrenheit": false, "messagesWarn": { "CalibrationDone": { "message": "Calibration\ndone!" }, "ResetOKMessage": { "message": "Reset OK" }, "SettingsResetMessage": { "message": "Mot so cài đat\nđã thay đoi" }, "NoAccelerometerMessage": { "message": "Không phát hien\ngia toc ke!" }, "NoPowerDeliveryMessage": { "message": "Không phát hien\nUSB-PD IC!" }, "LockingKeysString": { "message": "Đã khóa" }, "UnlockingKeysString": { "message": "Mo khóa" }, "WarningKeysLockedString": { "message": "Đã khóa!" }, "WarningThermalRunaway": { "message": "Nhiet\nTat gia nhiet" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating\n" }, "SettingsResetWarning": { "message": "Ban chac chan muon khôi phuc tat ca cài đat ve mac đinh?" }, "UVLOWarningString": { "message": "DC thap" }, "UndervoltageString": { "message": "Đien áp thap\n" }, "InputVoltageString": { "message": "Đau vào V: \n" }, "SleepingAdvancedString": { "message": "Đang ngu...\n" }, "SleepingTipAdvancedString": { "message": "Meo: \n" }, "ProfilePreheatString": { "message": "Preheat\n" }, "ProfileCooldownString": { "message": "Cooldown\n" }, "DeviceFailedValidationWarning": { "message": "Your device is most likely a counterfeit!" }, "TooHotToStartProfileWarning": { "message": "Too hot to\nstart profile" } }, "characters": { "SettingRightChar": "R", "SettingLeftChar": "L", "SettingAutoChar": "A", "SettingSlowChar": "S", "SettingMediumChar": "M", "SettingFastChar": "F", "SettingStartSolderingChar": "S", "SettingStartSleepChar": "Z", "SettingStartSleepOffChar": "R", "SettingLockBoostChar": "B", "SettingLockFullChar": "F" }, "menuGroups": { "PowerMenu": { "displayText": "Cài đat\nnguon đien", "description": "" }, "SolderingMenu": { "displayText": "Cài đat\ntay hàn", "description": "" }, "PowerSavingMenu": { "displayText": "Che đo\nngu", "description": "" }, "UIMenu": { "displayText": "Giao dien\nnguoi dùng", "description": "" }, "AdvancedMenu": { "displayText": "Cài đat\nnâng cao", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "Nguon\nđien", "description": "Nguon đien, đat đien áp giam. (DC 10V) (S 3.3V moi cell, tat gioi han công suat)" }, "MinVolCell": { "displayText": "Voltage\ntoi thieu", "description": "Đien áp toi thieu cho phép trên moi cell (3S: 3 - 3,7V | 4-6S: 2,4 - 3,7V)" }, "QCMaxVoltage": { "displayText": "QC\nvoltage", "description": "Đien áp QC toi đa mà tay hàn yêu cau" }, "PDNegTimeout": { "displayText": "PD\nsau", "description": "Thoi gian cho đàm phán PD trong các buoc 100ms đe tuong thích voi mot so bo sac QC" }, "USBPDMode": { "displayText": "PD\nMode", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "Tăng\nnhiet đo", "description": "Nhiet đo dùng trong che đo \"tăng cuong\"" }, "AutoStart": { "displayText": "Nhiet đo\nđang tăng", "description": "S=nhiet đo hàn | Z=cho o nhiet đo ngu đen khi cu đong | R=cho mà không gia nhiet đen khi cu đong" }, "TempChangeShortStep": { "displayText": "Thay đoi n.đo\nan nút nhanh", "description": "Biên đo tăng/giam nhiet đo khi an nút nhanh" }, "TempChangeLongStep": { "displayText": "Thay đoi n.đo\nan nút lâu", "description": "Biên đo tăng/giam nhiet đo khi an nút lâu" }, "LockingMode": { "displayText": "Cho phép khóa\ncác nút", "description": "Trong khi hàn, giu ca 2 nút đe khóa (B=chi che đo tăng cuong | F=khóa hoàn toàn)" }, "ProfilePhases": { "displayText": "Profile\nPhases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat\nTemp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat\nSpeed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1\nTemp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1\nDuration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2\nTemp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2\nDuration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3\nTemp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3\nDuration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4\nTemp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4\nDuration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5\nTemp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5\nDuration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown\nSpeed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "Cam bien\ncu đong", "description": "1=đo nhay thap nhat| ... | 9=đo nhay cao nhat" }, "SleepTemperature": { "displayText": "Nhiet đo\nkhi ngu", "description": "Giam nhiet đo khi o \"Che đo ngu\"" }, "SleepTimeout": { "displayText": "Ngu\nsau", "description": "thoi gian truoc khi \"Che đo ngu\" bat đau (s=giây | m=phút)" }, "ShutdownTimeout": { "displayText": "Tat\nsau", "description": "khoang thoi gian truoc khi tay hàn tat (m=phút)" }, "HallEffSensitivity": { "displayText": "Hall\nđo nhay", "description": "Đo nhay cam bien Hall đe phát hien che đo ngu (1=ít nhay nhat |...| 9=nhay nhat)" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "Đon vi\nnhiet đo", "description": "C= Đo C | F= Đo F" }, "DisplayRotation": { "displayText": "Huong\nhien thi", "description": "R=huong tay phai | L=huong tay trái | A=tu đong" }, "CooldownBlink": { "displayText": "Nguoi đi\nchop mat", "description": "Nhap nháy nhiet đo sau khi viec gia nhiet tam dung trong khi mui hàn van nóng" }, "ScrollingSpeed": { "displayText": "Toc đo\ncuon", "description": "Toc đo cuon văn ban(S=cham | F=nhanh)" }, "ReverseButtonTempChange": { "displayText": "Đao nguoc\nnút + -", "description": "Đao nguoc chuc năng các nút đieu chinh nhiet đo" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "Toc đo\nhoat anh", "description": "Toc đo cua hoat anh menu (S=cham | M=trung bình | F=nhanh)" }, "AnimLoop": { "displayText": "Hoat anh\nlap lai", "description": "Lap lai các hoat anh trong màn hình chính" }, "Brightness": { "displayText": "Đo tuong phan\nmàn hình", "description": "Đieu chinh đo sáng màn hình OLED" }, "ColourInversion": { "displayText": "Đao nguoc màu\nmàn hình", "description": "Đao nguoc màu màn hình OLED" }, "LOGOTime": { "displayText": "Boot logo\nduration", "description": "Set boot logo duration (s=seconds)" }, "AdvancedIdle": { "displayText": "Chi tiet\nmàn hình cho", "description": "hien thi thông tin chi tiet bang phông chu nho hon trên màn hình cho" }, "AdvancedSoldering": { "displayText": "Chi tiet\nmàn hình hàn", "description": "Hien thi thông tin bang phông chu nho hon trên màn hình hàn" }, "BluetoothLE": { "displayText": "Bluetooth\n", "description": "Enables BLE" }, "PowerLimit": { "displayText": "Công suat\ngioi han", "description": "Công suat toi đa mà tay hàn có the su dung (W=watt)" }, "CalibrateCJC": { "displayText": "Calibrate CJC\nat next boot", "description": "Calbrate Cold Junction Compensation at next boot (not required if Delta T is < 5°C)" }, "VoltageCalibration": { "displayText": "Hieu chinh\nđien áp đau vào?", "description": "bat đau hieu chuan VIN (nhan và giu đe thoát)" }, "PowerPulsePower": { "displayText": "Công suat\nkích nguon", "description": "Cuong đo công suat kích nguon (watt)" }, "PowerPulseWait": { "displayText": "Trì hoãn\nđien áp kích", "description": "Trì hoãn truoc khi kích hoat kích nguon(x 2,5 giây)" }, "PowerPulseDuration": { "displayText": "Thoi luong\nkích nguon", "description": "thoi luong kích nguon (x 250ms)" }, "SettingsReset": { "displayText": "Khôi phuc\ncài đat goc?", "description": "đat lai tat ca cài đat ve mac đinh" }, "LanguageSwitch": { "displayText": "Ngôn ngu:\n VI Tieng Viet", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_YUE_HK.json ================================================ { "languageCode": "YUE_HK", "languageLocalName": "廣東話 (香港)", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "Calibration done!" }, "ResetOKMessage": { "message": "已重設！" }, "SettingsResetMessage": { "message": "設定已被重設！" }, "NoAccelerometerMessage": { "message": "未能偵測加速度計" }, "NoPowerDeliveryMessage": { "message": "未能偵測PD晶片" }, "LockingKeysString": { "message": "已鎖定" }, "UnlockingKeysString": { "message": "已解除鎖定" }, "WarningKeysLockedString": { "message": "!撳掣鎖定!" }, "WarningThermalRunaway": { "message": "加熱失控" }, "WarningTipShorted": { "message": "!Tip Shorted!" }, "SettingsCalibrationWarning": { "message": "Before rebooting, make sure tip & handle are at room temperature!" }, "CJCCalibrating": { "message": "calibrating" }, "SettingsResetWarning": { "message": "你係咪確定要將全部設定重設到預設值？" }, "UVLOWarningString": { "message": "電壓過低" }, "UndervoltageString": { "message": "Undervoltage" }, "InputVoltageString": { "message": "Input V: " }, "SleepingAdvancedString": { "message": "Sleeping..." }, "SleepingTipAdvancedString": { "message": "Tip: " }, "ProfilePreheatString": { "message": "Preheat" }, "ProfileCooldownString": { "message": "Cooldown" }, "DeviceFailedValidationWarning": { "message": "依支焫雞好有可能係冒牌貨！" }, "TooHotToStartProfileWarning": { "message": "Too hot to start profile" } }, "characters": { "SettingRightChar": "右", "SettingLeftChar": "左", "SettingAutoChar": "自", "SettingSlowChar": "慢", "SettingMediumChar": "中", "SettingFastChar": "快", "SettingStartSolderingChar": "焊", "SettingStartSleepChar": "待", "SettingStartSleepOffChar": "室", "SettingLockBoostChar": "增", "SettingLockFullChar": "全" }, "menuGroups": { "PowerMenu": { "displayText": "電源設定", "description": "" }, "SolderingMenu": { "displayText": "焊接設定", "description": "" }, "PowerSavingMenu": { "displayText": "待機設定", "description": "" }, "UIMenu": { "displayText": "使用者介面", "description": "" }, "AdvancedMenu": { "displayText": "進階設定", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "電源", "description": "輸入電源；設定自動停機電壓 " }, "MinVolCell": { "displayText": "最低電壓", "description": "每粒電池嘅最低可用電壓 <伏特> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>" }, "QCMaxVoltage": { "displayText": "QC電壓", "description": "使用QC電源時請求嘅最高目標電壓" }, "PDNegTimeout": { "displayText": "PD逾時", "description": "設定USB PD協定交涉嘅逾時時限；為兼容某啲QC電源而設 " }, "USBPDMode": { "displayText": "PD VPDO", "description": "No Dynamic disables EPR & PPS, Safe mode does not use padding resistance" }, "BoostTemperature": { "displayText": "增熱温度", "description": "喺增熱模式時使用嘅温度" }, "AutoStart": { "displayText": "自動啓用", "description": "開機時自動啓用 <焊=焊接模式 | 待=待機模式 | 室=室温待機>" }, "TempChangeShortStep": { "displayText": "温度調整 短", "description": "調校温度時短撳一下嘅温度變幅" }, "TempChangeLongStep": { "displayText": "温度調整 長", "description": "調校温度時長撳嘅温度變幅" }, "LockingMode": { "displayText": "撳掣鎖定", "description": "喺焊接模式時，同時長撳兩粒掣啓用撳掣鎖定 <增=淨係容許增熱模式 | 全=鎖定全部>" }, "ProfilePhases": { "displayText": "Profile Phases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat Temp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat Speed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1 Temp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1 Duration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2 Temp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2 Duration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3 Temp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3 Duration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4 Temp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4 Duration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5 Temp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5 Duration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown Speed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "動作敏感度", "description": "1=最低敏感度 | ... | 9=最高敏感度" }, "SleepTemperature": { "displayText": "待機温度", "description": "喺待機模式時嘅焫雞咀温度" }, "SleepTimeout": { "displayText": "待機延時", "description": "自動進入待機模式前嘅閒置等候時間 " }, "ShutdownTimeout": { "displayText": "自動熄機", "description": "自動熄機前嘅閒置等候時間 " }, "HallEffSensitivity": { "displayText": "磁場敏感度", "description": "磁場感應器用嚟啓動待機模式嘅敏感度 <1=最低敏感度 | ... | 9=最高敏感度>" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "温度單位", "description": "C=攝氏 | F=華氏" }, "DisplayRotation": { "displayText": "畫面方向", "description": "右=使用右手 | 左=使用左手 | 自=自動" }, "CooldownBlink": { "displayText": "降温時閃爍", "description": "停止加熱之後，當焫雞咀仲係熱嗰陣閃爍畫面" }, "ScrollingSpeed": { "displayText": "捲動速度", "description": "解說文字嘅捲動速度" }, "ReverseButtonTempChange": { "displayText": "反轉加減掣", "description": "反轉調校温度時加減掣嘅方向" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "動畫速度", "description": "功能表圖示動畫嘅速度 <慢=慢速 | 中=中速 | 快=快速>" }, "AnimLoop": { "displayText": "動畫循環", "description": "循環顯示功能表圖示動畫" }, "Brightness": { "displayText": "熒幕亮度", "description": "設定OLED熒幕嘅亮度" }, "ColourInversion": { "displayText": "熒幕反轉色", "description": "反轉OLED熒幕嘅黑白色" }, "LOGOTime": { "displayText": "開機畫面", "description": "設定開機畫面顯示時長 " }, "AdvancedIdle": { "displayText": "詳細閒置畫面", "description": "喺閒置畫面以英文細字顯示詳細嘅資料" }, "AdvancedSoldering": { "displayText": "詳細焊接畫面", "description": "喺焊接模式畫面以英文細字顯示詳細嘅資料" }, "BluetoothLE": { "displayText": "Bluetooth", "description": "Enables BLE" }, "PowerLimit": { "displayText": "功率限制", "description": "限制焫雞可用嘅最大功率 " }, "CalibrateCJC": { "displayText": "校正CJC", "description": "At next boot tip Cold Junction Compensation will be calibrated (not required if Delta T is < 5 C)" }, "VoltageCalibration": { "displayText": "輸入電壓校正？", "description": "開始校正VIN輸入電壓 <長撳以退出>" }, "PowerPulsePower": { "displayText": "電源脈衝", "description": "為保持電源喚醒而通電所用嘅功率 " }, "PowerPulseWait": { "displayText": "電源脈衝間隔", "description": "為保持電源喚醒，每次通電之間嘅間隔時間 " }, "PowerPulseDuration": { "displayText": "電源脈衝時長", "description": "為保持電源喚醒，每次通電脈衝嘅時間長度 " }, "SettingsReset": { "displayText": "全部重設？", "description": "將所有設定重設到預設值" }, "LanguageSwitch": { "displayText": "語言： 廣東話", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translation_ZH_CN.json ================================================ { "languageCode": "ZH_CN", "languageLocalName": "简体中文", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "校正完成！" }, "ResetOKMessage": { "message": "已重置！" }, "SettingsResetMessage": { "message": "设定已被重置！" }, "NoAccelerometerMessage": { "message": "未检测到加速度计" }, "NoPowerDeliveryMessage": { "message": "未检测到PD电路" }, "LockingKeysString": { "message": "已锁定" }, "UnlockingKeysString": { "message": "已解锁" }, "WarningKeysLockedString": { "message": "!按键锁定!" }, "WarningThermalRunaway": { "message": "加热失控" }, "WarningTipShorted": { "message": "!烙铁头短路!" }, "SettingsCalibrationWarning": { "message": "在重启前请确认烙铁头及本体已完全冷却！" }, "CJCCalibrating": { "message": "校正中" }, "SettingsResetWarning": { "message": "你是否确定要将全部设定重置为默认值？" }, "UVLOWarningString": { "message": "电压过低" }, "UndervoltageString": { "message": "欠压" }, "InputVoltageString": { "message": "VIN: \n" }, "SleepingAdvancedString": { "message": "Zzzz..." }, "SleepingTipAdvancedString": { "message": "<--- " }, "ProfilePreheatString": { "message": "预热中" }, "ProfileCooldownString": { "message": "冷却" }, "DeviceFailedValidationWarning": { "message": "这支电烙铁很有可能是冒牌货！" }, "TooHotToStartProfileWarning": { "message": "设备过热" } }, "characters": { "SettingRightChar": "右", "SettingLeftChar": "左", "SettingAutoChar": "自", "SettingSlowChar": "慢", "SettingMediumChar": "中", "SettingFastChar": "快", "SettingStartSolderingChar": "焊", "SettingStartSleepChar": "待", "SettingStartSleepOffChar": "室", "SettingLockBoostChar": "增", "SettingLockFullChar": "全" }, "menuGroups": { "PowerMenu": { "displayText": "电源设置", "description": "" }, "SolderingMenu": { "displayText": "焊接设置", "description": "" }, "PowerSavingMenu": { "displayText": "待机设置", "description": "" }, "UIMenu": { "displayText": "用户界面", "description": "" }, "AdvancedMenu": { "displayText": "高级设置", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "默认模式" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "安全模式" }, "TipTypeAuto": { "displayText": "自动检测" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "下限电压", "description": "设置自动停机电压 " }, "MinVolCell": { "displayText": "最低电压", "description": "每节电池的最低允许电压 <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>" }, "QCMaxVoltage": { "displayText": "QC电压", "description": "使用QC电源时请求的最高目标电压" }, "PDNegTimeout": { "displayText": "PD超时", "description": "设定USB-PD协议交涉的超时时限；为兼容某些QC电源而设 " }, "USBPDMode": { "displayText": "PD\nVPDO", "description": "启用PPS和EPR快充支持" }, "BoostTemperature": { "displayText": "增热温度", "description": "增热模式时使用的温度" }, "AutoStart": { "displayText": "自动启动", "description": "开机时自动启动 <焊=焊接模式 | 待=待机模式 | 室=室温待机>" }, "TempChangeShortStep": { "displayText": "短按温度调整", "description": "调校温度时短按按键的温度变幅" }, "TempChangeLongStep": { "displayText": "长按温度调整", "description": "调校温度时长按按键的温度变幅" }, "LockingMode": { "displayText": "按键锁定", "description": "焊接模式时，同时长按两个按键启用按键锁定 <增=只容许增热模式 | 全=完全锁定>" }, "ProfilePhases": { "displayText": "配置阶数", "description": "配置模式下的阶段数量" }, "ProfilePreheatTemp": { "displayText": "预热温度", "description": "配置开始时的目标温度" }, "ProfilePreheatSpeed": { "displayText": "预热速度", "description": "将以此速度进行预热 (度/秒)" }, "ProfilePhase1Temp": { "displayText": "阶段1温度", "description": "此阶段结束时的目标温度" }, "ProfilePhase1Duration": { "displayText": "阶段1时间", "description": "此阶段的目标持续时间（秒）" }, "ProfilePhase2Temp": { "displayText": "阶段2温度", "description": "此阶段结束时的目标温度" }, "ProfilePhase2Duration": { "displayText": "阶段2时间", "description": "此阶段的目标持续时间（秒）" }, "ProfilePhase3Temp": { "displayText": "阶段3温度", "description": "此阶段结束时的目标温度" }, "ProfilePhase3Duration": { "displayText": "阶段3时间", "description": "此阶段的目标持续时间（秒）" }, "ProfilePhase4Temp": { "displayText": "阶段4温度", "description": "此阶段结束时的目标温度" }, "ProfilePhase4Duration": { "displayText": "阶段4时间", "description": "此阶段的目标持续时间（秒）" }, "ProfilePhase5Temp": { "displayText": "阶段5温度", "description": "此阶段结束时的目标温度" }, "ProfilePhase5Duration": { "displayText": "阶段5时间", "description": "此阶段的目标持续时间（秒）" }, "ProfileCooldownSpeed": { "displayText": "冷却速度", "description": "在配置模式结束时以此速度进行冷却（度/秒）" }, "MotionSensitivity": { "displayText": "动作灵敏度", "description": "1=最低灵敏度 | ... | 9=最高灵敏度" }, "SleepTemperature": { "displayText": "待机温度", "description": "待机模式时的烙铁头温度" }, "SleepTimeout": { "displayText": "待机超时", "description": "自动进入待机模式前的等候时间 " }, "ShutdownTimeout": { "displayText": "自动关机", "description": "自动关机前的等候时间 " }, "HallEffSensitivity": { "displayText": "磁场灵敏度", "description": "霍尔效应传感器用作启动待机模式的灵敏度 <1=最低灵敏度 | ... | 9=最高灵敏度>" }, "HallEffSleepTimeout": { "displayText": "霍尔传感器休眠时间", "description": "当霍尔传感器检测值高于阈值时，进入“睡眠模式”前的间隔时间" }, "TemperatureUnit": { "displayText": "温度单位", "description": "C=摄氏 | F=华氏" }, "DisplayRotation": { "displayText": "显示方向", "description": "右=右手 | 左=左手 | 自=自动" }, "CooldownBlink": { "displayText": "降温时闪显", "description": "停止加热之后，闪动温度显示提醒烙铁头仍处于高温状态" }, "ScrollingSpeed": { "displayText": "滚动速度", "description": "解说文字的滚动速度" }, "ReverseButtonTempChange": { "displayText": "调换加减键", "description": "调校温度时更换加减键的方向" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "动画速度", "description": "主菜单中功能图标动画的播放速度 <慢=慢速 | 中=中速 | 快=快速>" }, "AnimLoop": { "displayText": "动画循环", "description": "主菜单中循环播放功能图标动画" }, "Brightness": { "displayText": "屏幕亮度", "description": "调整OLED屏幕的亮度" }, "ColourInversion": { "displayText": "反转屏幕颜色", "description": "反转OLED黑/白屏幕" }, "LOGOTime": { "displayText": "开机画面", "description": "设定开机画面显示时长 " }, "AdvancedIdle": { "displayText": "闲置画面详情", "description": "闲置画面以英语小字体显示详情" }, "AdvancedSoldering": { "displayText": "焊接画面详情", "description": "焊接模式画面以英语小字体显示详请" }, "BluetoothLE": { "displayText": "蓝牙", "description": "启用蓝牙支持" }, "PowerLimit": { "displayText": "功率限制", "description": "限制烙铁可用的最大功率 " }, "CalibrateCJC": { "displayText": "校正CJC", "description": "在下次重启时校正烙铁头热电偶冷接点补偿值（CJC）（温差小于5摄氏度时无需校正）" }, "VoltageCalibration": { "displayText": "输入电压校正", "description": "开始校正输入电压（VIN）<长按以退出>" }, "PowerPulsePower": { "displayText": "电源脉冲", "description": "为保持电源处于唤醒状态所用的功率 " }, "PowerPulseWait": { "displayText": "电源脉冲间隔", "description": "为保持电源处于唤醒状态，每次通电之间的间隔时间 " }, "PowerPulseDuration": { "displayText": "电源脉冲时长", "description": "为保持电源处于唤醒状态，每次通电脉冲的时间长度 " }, "SettingsReset": { "displayText": "全部重置", "description": "将所有设定重置为默认值" }, "LanguageSwitch": { "displayText": "语言：简体中文", "description": "" }, "SolderingTipType": { "displayText": "焊接头类型", "description": "选择安装合适的尖端类型" } } } ================================================ FILE: Translations/translation_ZH_TW.json ================================================ { "languageCode": "ZH_TW", "languageLocalName": "正體中文", "tempUnitFahrenheit": true, "messagesWarn": { "CalibrationDone": { "message": "校正完成！" }, "ResetOKMessage": { "message": "已重設！" }, "SettingsResetMessage": { "message": "設定已被重設！" }, "NoAccelerometerMessage": { "message": "未能偵測加速度計" }, "NoPowerDeliveryMessage": { "message": "未能偵測PD晶片" }, "LockingKeysString": { "message": "已鎖定" }, "UnlockingKeysString": { "message": "已解除鎖定" }, "WarningKeysLockedString": { "message": "!按鍵鎖定!" }, "WarningThermalRunaway": { "message": "加熱失控" }, "WarningTipShorted": { "message": "!烙鐵頭短路!" }, "SettingsCalibrationWarning": { "message": "在重啟前請確認烙鐵頭及本體已完全冷卻！" }, "CJCCalibrating": { "message": "校正中" }, "SettingsResetWarning": { "message": "你是否確定要將全部設定重設到預設值？" }, "UVLOWarningString": { "message": "電壓過低" }, "UndervoltageString": { "message": "Undervoltage" }, "InputVoltageString": { "message": "Input V: " }, "SleepingAdvancedString": { "message": "Sleeping..." }, "SleepingTipAdvancedString": { "message": "Tip: " }, "ProfilePreheatString": { "message": "Preheat" }, "ProfileCooldownString": { "message": "Cooldown" }, "DeviceFailedValidationWarning": { "message": "這支電烙鐵很有可能是冒牌貨！" }, "TooHotToStartProfileWarning": { "message": "Too hot to start profile" } }, "characters": { "SettingRightChar": "右", "SettingLeftChar": "左", "SettingAutoChar": "自", "SettingSlowChar": "慢", "SettingMediumChar": "中", "SettingFastChar": "快", "SettingStartSolderingChar": "焊", "SettingStartSleepChar": "待", "SettingStartSleepOffChar": "室", "SettingLockBoostChar": "增", "SettingLockFullChar": "全" }, "menuGroups": { "PowerMenu": { "displayText": "電源設定", "description": "" }, "SolderingMenu": { "displayText": "焊接設定", "description": "" }, "PowerSavingMenu": { "displayText": "待機設定", "description": "" }, "UIMenu": { "displayText": "使用者介面", "description": "" }, "AdvancedMenu": { "displayText": "進階設定", "description": "" } }, "menuValues": { "USBPDModeDefault": { "displayText": "Default\nMode" }, "USBPDModeNoDynamic": { "displayText": "No\nDynamic" }, "USBPDModeSafe": { "displayText": "Safe\nMode" }, "TipTypeAuto": { "displayText": "Auto\nSense" }, "TipTypeT12Long": { "displayText": "TS100\nLong" }, "TipTypeT12Short": { "displayText": "Pine\nShort" }, "TipTypeT12PTS": { "displayText": "PTS\n200" }, "TipTypeTS80": { "displayText": "TS80\n" }, "TipTypeJBCC210": { "displayText": "JBC\nC210" } }, "menuOptions": { "DCInCutoff": { "displayText": "電源", "description": "輸入電源；設定自動停機電壓 " }, "MinVolCell": { "displayText": "最低電壓", "description": "每顆電池的最低可用電壓 <伏特> <3S: 3.0V - 3.7V, 4/5/6S: 2.4V - 3.7V>" }, "QCMaxVoltage": { "displayText": "QC電壓", "description": "使用QC電源時請求的最高目標電壓" }, "PDNegTimeout": { "displayText": "PD逾時", "description": "設定USB PD協定交涉的逾時時限；為兼容某些QC電源而設 " }, "USBPDMode": { "displayText": "PD VPDO", "description": "開啟PPS及EPR支援" }, "BoostTemperature": { "displayText": "增熱溫度", "description": "於增熱模式時使用的溫度" }, "AutoStart": { "displayText": "自動啟用", "description": "開機時自動啟用 <焊=焊接模式 | 待=待機模式 | 室=室溫待機>" }, "TempChangeShortStep": { "displayText": "溫度調整 短", "description": "調校溫度時短按一下的溫度變幅" }, "TempChangeLongStep": { "displayText": "溫度調整 長", "description": "調校溫度時長按按鍵的溫度變幅" }, "LockingMode": { "displayText": "按鍵鎖定", "description": "於焊接模式時，同時長按兩個按鍵啟用按鍵鎖定 <增=只容許增熱模式 | 全=鎖定全部>" }, "ProfilePhases": { "displayText": "Profile Phases", "description": "Number of phases in profile mode" }, "ProfilePreheatTemp": { "displayText": "Preheat Temp", "description": "Preheat to this temperature at the start of profile mode" }, "ProfilePreheatSpeed": { "displayText": "Preheat Speed", "description": "Preheat at this rate (degrees per second)" }, "ProfilePhase1Temp": { "displayText": "Phase 1 Temp", "description": "Target temperature for the end of this phase" }, "ProfilePhase1Duration": { "displayText": "Phase 1 Duration", "description": "Target duration of this phase (seconds)" }, "ProfilePhase2Temp": { "displayText": "Phase 2 Temp", "description": "" }, "ProfilePhase2Duration": { "displayText": "Phase 2 Duration", "description": "" }, "ProfilePhase3Temp": { "displayText": "Phase 3 Temp", "description": "" }, "ProfilePhase3Duration": { "displayText": "Phase 3 Duration", "description": "" }, "ProfilePhase4Temp": { "displayText": "Phase 4 Temp", "description": "" }, "ProfilePhase4Duration": { "displayText": "Phase 4 Duration", "description": "" }, "ProfilePhase5Temp": { "displayText": "Phase 5 Temp", "description": "" }, "ProfilePhase5Duration": { "displayText": "Phase 5 Duration", "description": "" }, "ProfileCooldownSpeed": { "displayText": "Cooldown Speed", "description": "Cooldown at this rate at the end of profile mode (degrees per second)" }, "MotionSensitivity": { "displayText": "動作敏感度", "description": "1=最低敏感度 | ... | 9=最高敏感度" }, "SleepTemperature": { "displayText": "待機溫度", "description": "於待機模式時的烙鐵頭溫度" }, "SleepTimeout": { "displayText": "待機延時", "description": "自動進入待機模式前的閒置等候時間 " }, "ShutdownTimeout": { "displayText": "自動關機", "description": "自動關機前的閒置等候時間 " }, "HallEffSensitivity": { "displayText": "磁場敏感度", "description": "磁場感應器用作啟動待機模式的敏感度 <1=最低敏感度 | ... | 9=最高敏感度>" }, "HallEffSleepTimeout": { "displayText": "HallSensor\nSleepTime", "description": "Interval before \"sleep mode\" starts when hall effect is above threshold" }, "TemperatureUnit": { "displayText": "溫標", "description": "C=攝氏 | F=華氏" }, "DisplayRotation": { "displayText": "畫面方向", "description": "右=使用右手 | 左=使用左手 | 自=自動" }, "CooldownBlink": { "displayText": "降溫時閃爍", "description": "停止加熱之後，當烙鐵頭仍處於高溫時閃爍畫面" }, "ScrollingSpeed": { "displayText": "捲動速度", "description": "解說文字的捲動速度" }, "ReverseButtonTempChange": { "displayText": "調換加減鍵", "description": "調校溫度時調換加減鍵的方向" }, "ReverseButtonSettings": { "displayText": "Swap\nA B keys", "description": "Reverse assignment of buttons for Settings menu" }, "AnimSpeed": { "displayText": "動畫速度", "description": "功能表圖示動畫的速度 <慢=慢速 | 中=中速 | 快=快速>" }, "AnimLoop": { "displayText": "動畫循環", "description": "循環顯示功能表圖示動畫" }, "Brightness": { "displayText": "螢幕亮度", "description": "設定OLED螢幕的亮度" }, "ColourInversion": { "displayText": "螢幕反轉色", "description": "反轉OLED螢幕的黑白色彩" }, "LOGOTime": { "displayText": "開機畫面", "description": "設定開機畫面顯示時長 " }, "AdvancedIdle": { "displayText": "詳細閒置畫面", "description": "於閒置畫面以英文小字型顯示詳細資料" }, "AdvancedSoldering": { "displayText": "詳細焊接畫面", "description": "於焊接模式畫面以英文小字型顯示詳細資料" }, "BluetoothLE": { "displayText": "藍牙", "description": "開啟藍牙支援" }, "PowerLimit": { "displayText": "功率限制", "description": "限制烙鐵可用的最大功率 " }, "CalibrateCJC": { "displayText": "校正CJC", "description": "在下次重啟時校正烙鐵頭熱電偶冷接點補償值（CJC）（溫差小於5攝氏度時無需校正）" }, "VoltageCalibration": { "displayText": "輸入電壓校正？", "description": "開始校正VIN輸入電壓 <長按以退出>" }, "PowerPulsePower": { "displayText": "電源脈衝", "description": "為保持電源喚醒而通電所用的功率 " }, "PowerPulseWait": { "displayText": "電源脈衝間隔", "description": "為保持電源喚醒，每次通電之間的間隔時間 " }, "PowerPulseDuration": { "displayText": "電源脈衝時長", "description": "為保持電源喚醒，每次通電脈衝的時間長度 " }, "SettingsReset": { "displayText": "全部重設？", "description": "將所有設定重設到預設值" }, "LanguageSwitch": { "displayText": "語言：正體中文", "description": "" }, "SolderingTipType": { "displayText": "Soldering\nTip Type", "description": "Select the tip type fitted" } } } ================================================ FILE: Translations/translations_definitions.json ================================================ { "messagesWarn": [ { "id": "CalibrationDone", "description": "Confirmation message indicating calibration is complete." }, { "id": "ResetOKMessage", "description": "Shown when the settings are reset to factory defaults by the user." }, { "id": "SettingsResetMessage", "description": "Shown when certain settings are reset to factory defaults due to incompatible firmware changes." }, { "id": "NoAccelerometerMessage", "description": "No accelerometer could be communicated with. This means that either the device's accelerometer is broken or unknown to IronOS. All motion-based settings are disabled and motion-based features will not work." }, { "id": "NoPowerDeliveryMessage", "include": ["POW_PD"], "description": "The IC required for USB-PD could not be communicated with. This is an error warning that USB-PD WILL NOT FUNCTION. Generally indicative of either a hardware or software issues." }, { "id": "LockingKeysString", "description": "Shown when keys are locked" }, { "id": "UnlockingKeysString", "description": "Shown when keys are unlocked" }, { "id": "WarningKeysLockedString", "description": "Warning that is shown when input is ignored due to the key lock being on" }, { "id": "WarningThermalRunaway", "description": "Warning text shown when the software has disabled the heater as a safety precaution as the temperature reading didn't react as expected." }, { "id": "WarningTipShorted", "description": "Warning text shown when the software has detected that the users tip is likely shorted." }, { "id": "SettingsCalibrationWarning", "description": "Confirmation message shown before performing an offset calibration. Should warn the user to make sure tip and handle are at the same temperature." }, { "id": "CJCCalibrating", "description": "Message indicating CJC is being calibrated." }, { "id": "SettingsResetWarning", "description": "Confirmation message shown before confirming a settings reset." }, { "id": "UVLOWarningString", "maxLen": 8, "include": ["POW_DC"], "description": "Warning text shown when the unit turns off due to undervoltage in simple mode." }, { "id": "UndervoltageString", "maxLen": 15, "include": ["POW_DC"], "description": "Warning text shown when the unit turns off due to undervoltage in advanced mode." }, { "id": "InputVoltageString", "maxLen": 11, "note": "Preferably end with a space", "include": ["POW_DC"], "description": "Prefix text for 'Input Voltage' shown before showing the input voltage reading." }, { "id": "ProfilePreheatString", "maxLen": 9, "include": ["PROFILE_SUPPORT"], "description": "Shown in profile mode while preheating" }, { "id": "ProfileCooldownString", "maxLen": 9, "include": ["PROFILE_SUPPORT"], "description": "Shown in profile mode while cooling down" }, { "id": "SleepingAdvancedString", "maxLen": 15, "exclude": ["NO_SLEEP_MODE"], "description": "The text shown to indicate the unit is in sleep mode when the advanced view is turned on." }, { "id": "SleepingTipAdvancedString", "maxLen": 6, "exclude": ["NO_SLEEP_MODE"], "description": "The prefix text shown before tip temperature when the unit is sleeping with advanced view on." }, { "id": "DeviceFailedValidationWarning", "default": "Device may be\ncounterfeit", "description": "Warning shown if the device may be a clone or counterfeit unit." }, { "id": "TooHotToStartProfileWarning", "default": "Too hot to\nstart profile", "include": ["PROFILE_SUPPORT"], "description": "Shown when profile mode is started while the device is too hot." } ], "characters": [ { "id": "SettingRightChar", "len": 1, "description": "Shown for fixed Right-handed display rotation." }, { "id": "SettingLeftChar", "len": 1, "description": "Shown for fixed Left-handed display rotation." }, { "id": "SettingAutoChar", "len": 1, "description": "Shown for automatic display rotation." }, { "id": "SettingSlowChar", "len": 1, "description": "Shown when a setting is set to a slow value i.e. animation speed" }, { "id": "SettingMediumChar", "len": 1, "description": "Shown when a setting is set to a medium value i.e. animation speed" }, { "id": "SettingFastChar", "len": 1, "description": "Shown when a setting is set to a fast value i.e. animation speed" }, { "id": "SettingStartSolderingChar", "len": 1, "description": "Shown when the auto start mode is set to go straight to soldering." }, { "id": "SettingStartSleepChar", "len": 1, "description": "Shown when the auto start mode is set to start in sleep mode." }, { "id": "SettingStartSleepOffChar", "len": 1, "description": "Shown when the auto start state is set to go to an off state, but on movement wake into soldering mode." }, { "id": "SettingLockBoostChar", "len": 1, "default": "B", "description": "Shown when the locking mode is set to lock all buttons except for boost mode." }, { "id": "SettingLockFullChar", "len": 1, "default": "F", "description": "Shown when the locking mode is set to lock all buttons." } ], "menuGroups": [ { "id": "PowerMenu", "maxLen": 5, "maxLen2": 11, "include": ["POW_DC", "POW_PD", "POW_QC"], "description": "Menu for settings related to power. Main settings to do with the input voltage." }, { "id": "SolderingMenu", "maxLen": 5, "maxLen2": 11, "description": "Settings for soldering mode, such as boost temps, the increment used when pressing buttons and if button locking is enabled." }, { "id": "PowerSavingMenu", "maxLen": 5, "maxLen2": 11, "description": "Settings to do with power saving, such as sleep mode, sleep temps, and shutdown modes." }, { "id": "UIMenu", "maxLen": 5, "maxLen2": 11, "description": "User interface related settings, such as units." }, { "id": "AdvancedMenu", "maxLen": 5, "maxLen2": 11, "description": "Advanced settings. Misc catchall for settings that don't fit anywhere else or settings that require some thought before use." } ], "menuValues": [ { "id": "USBPDModeDefault", "description": "When in this mode we enable all PD features, and we pad resistance slightly to account for cable and PCB trace loss" }, { "id": "USBPDModeNoDynamic", "description": "When in this mode we only enable fixed voltage USB-PD options, and we pad resistance slightly to account for cable and PCB trace loss" }, { "id": "USBPDModeSafe", "description": "When in this mode we enable all PD features, but we don't pad resistance slightly to account for cable and PCB trace loss" }, { "id": "TipTypeAuto", "description": "This is for automatic best-effort tip selection based on resistance" }, { "id": "TipTypeT12Long", "description": "Hakko T12 or older (long) TS100 tips" }, { "id": "TipTypeT12Short", "description": "Pine 6.2 ohm short TS100 style tips" }, { "id": "TipTypeT12PTS", "description": "PTS200 4 ohm short TS100 style tips" }, { "id": "TipTypeTS80", "description": "Miniware TS80(P) tips" }, { "id": "TipTypeJBCC210", "description": "JBC (or clone) tips" } ], "menuOptions": [ { "id": "DCInCutoff", "maxLen": 5, "maxLen2": 11, "include": ["POW_DC"], "description": "When the device is powered by a battery, this adjusts the low voltage threshold for when the unit should turn off the heater to protect the battery." }, { "id": "MinVolCell", "maxLen": 4, "maxLen2": 9, "include": ["POW_DC"], "description": "When powered by a battery, this adjusts the minimum voltage per cell before shutdown. (This is multiplied by the cell count.)" }, { "id": "QCMaxVoltage", "maxLen": 8, "maxLen2": 15, "include": ["POW_QC"], "description": "This adjusts the maximum voltage the QC negotiation will adjust to. Does NOT affect USB-PD. Should be set safely based on the current rating of your power supply." }, { "id": "PDNegTimeout", "maxLen": 8, "maxLen2": 15, "include": ["POW_PD"], "description": "How long until firmware stops trying to negotiate for USB-PD and tries QC instead. Longer times may help dodgy / old PD adapters, faster times move onto PD quickly. Units of 100ms. Recommended to keep small values." }, { "id": "USBPDMode", "maxLen": 7, "maxLen2": 15, "include": ["POW_PD"], "description": "Adjusts how the USB-PD Logic selects the voltage. No Dynamic disables EPR & PPS protocols, Safe mode does not use padding resistance (will select a slightly lower voltage)." }, { "id": "BoostTemperature", "maxLen": 4, "maxLen2": 9, "description": "When the unit is in soldering mode. You can hold down the button at the front of the device to temporarily override the soldering temperature to this value. This SETS the temperature, it does not ADD to it." }, { "id": "AutoStart", "maxLen": 6, "maxLen2": 13, "description": "When the device powers up, should it enter into a special mode. These settings set it to either start into soldering mode, sleeping mode or auto mode (Enters into soldering mode on the first movement)." }, { "id": "TempChangeShortStep", "maxLen": 8, "maxLen2": 15, "description": "Factor by which the temperature is changed with a quick press of the buttons." }, { "id": "TempChangeLongStep", "maxLen": 6, "maxLen2": 15, "description": "Factor by which the temperature is changed with a hold of the buttons." }, { "id": "LockingMode", "maxLen": 6, "maxLen2": 13, "description": "If locking the buttons against accidental presses is enabled." }, { "id": "ProfilePhases", "maxLen": 6, "maxLen2": 13, "include": ["PROFILE_SUPPORT"], "description": "set the number of phases for profile mode." }, { "id": "ProfilePreheatTemp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Preheat to this temperature at the start of profile mode." }, { "id": "ProfilePreheatSpeed", "maxLen": 5, "maxLen2": 11, "include": ["PROFILE_SUPPORT"], "description": "How fast the temperature is allowed to rise during the preheat phase at the start of profile mode." }, { "id": "ProfilePhase1Temp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Target temperature for the end of phase 1 of profile mode." }, { "id": "ProfilePhase1Duration", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Duration of phase 1 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature." }, { "id": "ProfilePhase2Temp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Target temperature for the end of phase 2 of profile mode." }, { "id": "ProfilePhase2Duration", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Duration of phase 2 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature." }, { "id": "ProfilePhase3Temp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Target temperature for the end of phase 3 of profile mode." }, { "id": "ProfilePhase3Duration", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Duration of phase 3 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature." }, { "id": "ProfilePhase4Temp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Target temperature for the end of phase 5 of profile mode." }, { "id": "ProfilePhase4Duration", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Duration of phase 5 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature." }, { "id": "ProfilePhase5Temp", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Target temperature for the end of phase 5 of profile mode." }, { "id": "ProfilePhase5Duration", "maxLen": 4, "maxLen2": 9, "include": ["PROFILE_SUPPORT"], "description": "Duration of phase 5 of profile mode. The phase might actually take longer if it takes longer to reach the target temperature." }, { "id": "ProfileCooldownSpeed", "maxLen": 5, "maxLen2": 11, "include": ["PROFILE_SUPPORT"], "description": "How fast the temperature is allowed to drop during the cooldown phase at the end of profile mode." }, { "id": "MotionSensitivity", "maxLen": 6, "maxLen2": 13, "description": "Scale of how sensitive the device is to movement. Higher numbers == more sensitive. 0 == motion detection turned off." }, { "id": "SleepTemperature", "maxLen": 4, "maxLen2": 9, "exclude": ["NO_SLEEP_MODE"], "description": "Temperature the device will drop down to while asleep. Typically around halfway between off and soldering temperature." }, { "id": "SleepTimeout", "maxLen": 4, "maxLen2": 9, "exclude": ["NO_SLEEP_MODE"], "description": "How long of a period without movement / button-pressing is required before the device drops down to the sleep temperature." }, { "id": "ShutdownTimeout", "maxLen": 5, "maxLen2": 11, "description": "How long of a period without movement / button-pressing is required before the device turns off the tip heater completely and returns to the main idle screen." }, { "id": "HallEffSensitivity", "maxLen": 6, "maxLen2": 13, "include": ["HALL_SENSOR"], "description": "If the unit has a hall effect sensor (Pinecil), this adjusts how sensitive it is at detecting a magnet to put the device into sleep mode." }, { "id": "HallEffSleepTimeout", "maxLen": 10, "maxLen2": 10, "include": ["HALL_SENSOR"], "description": "If the unit has a hall effect sensor (Pinecil), this adjusts how long the device takes before it drops down to the sleep temperature when hall sensor is over threshold." }, { "id": "TemperatureUnit", "maxLen": 6, "maxLen2": 13, "description": "If the device shows temperatures in °C or °F." }, { "id": "DisplayRotation", "maxLen": 6, "maxLen2": 13, "exclude": ["NO_DISPLAY_ROTATE"], "description": "If the display should rotate automatically or if it should be fixed for left- or right-handed mode." }, { "id": "CooldownBlink", "maxLen": 6, "maxLen2": 13, "description": "If the idle screen should blink the tip temperature for attention while the tip is over 50°C. Intended as a 'tip is still hot' warning." }, { "id": "ScrollingSpeed", "maxLen": 6, "maxLen2": 11, "description": "How fast the description text scrolls when hovering on a menu. Faster speeds may induce tearing, but allow reading the whole description faster." }, { "id": "ReverseButtonTempChange", "maxLen": 6, "maxLen2": 15, "description": "Swaps which button increments and decrements on temperature change screens." }, { "id": "ReverseButtonSettings", "maxLen": 6, "maxLen2": 15, "description": "Swaps which button is used as Enter/Change and as Scroll/Back in Settings menu." }, { "id": "AnimSpeed", "maxLen": 6, "maxLen2": 13, "description": "How fast should the menu animations loop, or if they should not loop at all." }, { "id": "AnimLoop", "maxLen": 6, "maxLen2": 13, "description": "Should the menu animations loop. Only visible if the animation speed is not set to \"Off\"" }, { "id": "Brightness", "maxLen": 7, "maxLen2": 15, "description": "Display brightness. Higher values age the OLED faster due to burn-in. (However, it is notable that most of these screens die from other causes first.)" }, { "id": "ColourInversion", "maxLen": 7, "maxLen2": 15, "description": "Inverts the entire OLED." }, { "id": "LOGOTime", "maxLen": 7, "maxLen2": 15, "description": "Sets the duration for the boot logo (s=seconds)." }, { "id": "AdvancedIdle", "maxLen": 6, "maxLen2": 13, "description": "Should the device show an 'advanced' view on the idle screen. The advanced view uses text to show more details than the typical icons." }, { "id": "AdvancedSoldering", "maxLen": 6, "maxLen2": 13, "description": "Should the device show an 'advanced' soldering view. This is a text-based view that shows more information at the cost of no nice graphics." }, { "id": "BluetoothLE", "maxLen": 7, "maxLen2": 15, "include": ["BLE_ENABLED"], "description": "Should BLE be enabled at boot time." }, { "id": "PowerLimit", "maxLen": 5, "maxLen2": 11, "description": "Allows setting a custom wattage for the device to aim to keep the AVERAGE power below. The unit can't control its peak power no matter how you set this. (Except for MHP30 which will regulate nicely to this). If USB-PD is in use, the limit will be set to the lower of this and the supplies advertised wattage." }, { "id": "CalibrateCJC", "maxLen": 8, "maxLen2": 15, "description": "Note:\r\nIf the difference between the target temperature and the measured temperature is less than 5°C, **calibration is NOT required at all**.\r\n\r\nThis is used to calibrate the offset between ADC and Op-amp of the tip **at next boot** (Ideally it has to be done at boot, before internal components get warm.). If the checkbox is set, the calibration will only be performed at the next boot. After a successful calibration the checkbox will be unchecked again! If you need to repeat the calibration however, you have to set the checkbox *again*, unplug your device and let it cool down to room/ambient temperature & power it up, ideally while it sits on the desk.\r\n\r\n\r\nAlso, the calibration will only take place if both of the following conditions are met:\r\n- The tip must be installed.\r\n- The temperature difference between tip and handle must be less than 10°C. (~ ambient / room temperature)\r\n\r\nOtherwise, the calibration will be performed the next time the device is started and both conditions are met, unless the corresponding checkbox is unchecked.\r\nHence, never repeat the calibration in quick succession!" }, { "id": "VoltageCalibration", "maxLen": 8, "maxLen2": 15, "description": "Enters an adjustment mode where you can gradually adjust the measured voltage to compensate for any unit-to-unit variance in the voltage sense resistors." }, { "id": "PowerPulsePower", "maxLen": 6, "maxLen2": 15, "description": "Enables and sets the wattage of the power pulse. Power pulse causes the device to briefly turn on the heater to draw power to avoid power banks going to sleep." }, { "id": "PowerPulseWait", "maxLen": 6, "maxLen2": 13, "description": "Adjusts the time interval between power pulses. Longer gaps reduce undesired heating of the tip, but needs to be fast enough to keep your power bank awake." }, { "id": "PowerPulseDuration", "maxLen": 6, "maxLen2": 13, "description": "How long should the power pulse go for. Some power banks require seeing the power draw be sustained for a certain duration to keep awake. Should be kept as short as possible to avoid wasting power / undesired heating of the tip." }, { "id": "SettingsReset", "maxLen": 8, "maxLen2": 15, "description": "Resets all settings and calibrations to factory defaults. Does NOT erase custom user boot up logo's." }, { "id": "LanguageSwitch", "maxLen": 7, "maxLen2": 15, "description": "Changes the device language on multi-lingual builds." }, { "id": "SolderingTipType", "maxLen": 7, "maxLen2": 15, "description": "For manually selecting the type of tip fitted" } ] } ================================================ FILE: Translations/wqy-bitmapsong/AUTHORS ================================================ ========================================================== Wen Quan Yi Bitmap Song CJK Fonts Contributors and Credits ---------------------------------------------------------- Email confusers: replace " #" to "@" , replace " _" to "." ---------------------------------------------------------- Summary: This font package is copyrighted by the WenQuanYi Board of Trustees 2004-2010 http://wenq.org/index.cgi?WQYBOT ---------------------------------------------------------- Table of Content I. Pevious Work II. WenQuanYi Bitmap Font developers III.Authors for CJK Bitmap Glyphs (CJK Basic) IV. Authors for CJK Extension A Glyphs V. Authors for CJK Basic glyphs standard verfication VI. Other resources ---------------------------------------------------------- I. Previous Work: firefly firefly #firefly _idv _tw provided multi-size Big5/GB2312 glyphs http://www.study-area.org/apt/firefly-font/ Chinese National Standard GB19966-2005 provided all 12pt face CJK glyphs between U3400-U9FA5 http://www.standardcn.com/standard_plan/ list_standard_content.asp?stand_id=GB@19966-2005 ---------------------------------------------------------- II .WenQuanYi Bitmap Font developers 1. Core members Qianqian Fang[FangQ] (fangq #nmr _mgh _harvard _edu) project founder and maintainer, wiki developer, release manager, software programer, major font developer and reviewer http://nmr.mgh.harvard.edu/~fangq/ http://bbs.dartmouth.edu/~fangq/blog/ Hong Wang (hongclean #gmail _com) key contributor, major reviewer Kefu Chai[tchaikov] (tchaikov #sjtu _edu _cn) web development, major reviewer ailantian* (ailantian #email _jlu _edu _cn) key developer for vector Chinese project http://ailantian.blogchina.com Haitao Han[niqiu]* (chenniqiu #gmail _com) key developer for vector Chinese project http://www.livejournal.com/~niqiu/ Qian Cai[caiqian]* (caiqian #gmail _com) creator of WenQuanYi bitmap font standard Funda Wang[fundawang]*(fundawang #linux _net _cn) key developer, technical support http://my.opera.com/fundawang/ Qing Lei[fiag]* (fiag.hit #gmail _com) key developer for vector Chinese project Nicolas Wang[ZaiJianQingRen]* (abcxyz54321 #163 _com) key contributor, major reviewer * the status is inactive 2. Team B members activeion (jizh #cnst _pku _edu _cn) amadeoh (zh217 #cam _ac _uk) BabyPBC (babypbc #etang _com) [Baochuan Pang] BenBear (cxj26424 #163 _com) [Xiongjie Chen] brep (brep #163 _com) chaoslawful (wangxz00 #mails _tsinghua _edu _cn) [Xiaozhe Wang] DannyZeng eka (ekapie #googlemail _com) (key contributor for glyph fine-tunning) keykeen (kaleasy #21cn _com) liyi (liyi79 #gmail _com) [Yi Li] lucifer (xinjibo #163 _com) [Jibo Xin] nilarcs (nilarcs #163 _com) [Jun Zhang] pangwa (pangwa #gmail _com) [Guang Han] pathfinder (pathfinder_name #hotmail _com) [Wei Yao] pinker (pinker #pku _edu _cn) PONY (yangxcmail-linux #yahoo _com _cn) pupilzeng shhky stid xuxiaodong #tsinghua _org _cn http://stid.blogchina.com/ wuler.lv (wuler.lv #gmail _com) [Wuler Lv] xnuxmwx (xnuxmwx #gmail _com) [Man Xu] http://www.tanvy.com/ namespace #yeah _net leftstand #chinaacc _com The following contributors had contributed for the development of CJK Extension A bitmaps: MarkLam (mark.jlam#gmail_com) twang467 (twang467#21cn_com) [Qiang Wang] buick (weiyiwei#gmail_com) [Yiwei Wei] liqian qinling (qin_ling#sohu_com) http://qinling.bokee.com Seeker (seeker#yeah_net) xiaoma (mayueping#gmail_com) SiCengXiangShi (liyulongmen#yahoo_com_cn) the_owl (weitao1979#gmail_com ) whppc (lyons.chang#gmail_com) eka (ekapie#googlemail_com) failsafe (simon.youngest#gmail_com) MSN:failsafenow@hotmail.com musiccow (blkatbyhh#gmail_com) http://my.opera.com/musiccow Blueelf (yshen#fas_harvard_edu) http://bbs.dartmouth.edu/web/yinghua/ lenovox (lenovox#126_com) fourbrow (fourbrow#163_com) udi (udisaar#gmail_com) leal (linxiao.li#gmail_com) http://www.leal.cn soicer (soicer#gmail_com) http://www.qianxinlei.com xuande (liu.i3655#gmail_com) [liu bei] lrobinson (lrobinson#126_com) zhouyingxin (yingxinzhou#gmail_com) [Yingxin Zhou] chenzhipeter(chenzhipeter#126_com) havas (zhihua.tan#gmail_com) [Zhihua Tan] The following contributors helped in developing non-CJK characters hzhsun (zhuang1 #cs _uml _edu) [Zhonghong Huang] weitao (weitao1979 #gmail _com) [Wei Tao] If your name is missing, please send an email to fangqqnmr.mgh.harvard.edu, we will add you to the list for all subsequent releases. 3. Donation Providers We sincerely appreciate the generous donations from many friends. Their donations not only support the project to grow healthily, but also encourage all the developers. A list of supporters can be found at http://wenq.org/index.cgi?Donation ---------------------------------------------------------- III. Authors for CJK Bitmap Glyphs (CJK Basic) * Project proceeded between 10/2004-04/2005 * Original project record: http://wenq.org/?UNICODE_U19968-U40869 http://wenq.org/index.cgi?offline * Progress log: http://wenq.org/index.cgi?CJK_TeamB_Progress -------------------------------------------------- Group Author Level Reviewer -------------------------------------------------- U+4E00~U+4E64 :anonymous: L3 FangQ U+4E65~U+4EC9 :anonymous: L3 FangQ U+4ECA~U+4F2E niqiu L3 FangQ U+4F2F~U+4F93 FangQ L3 FangQ U+4F94~U+4FF8 pupilzeng L3 FangQ U+4FF9~U+505D niqiu L3 FangQ U+505E~U+50C2 nilarcs L3 FangQ U+50C3~U+5127 achaoge/FangQ L3 FangQ U+5128~U+518C anonyous L3 tchaikov U+518D~U+51F1 FangQ L3 tchaikov U+51F2~U+5256 fundawang L3 FangQ U+5257~U+52BB FangQ/shhky L3 Caiqian U+52BC~U+5320 :anonymous: L3 Caiqian U+5321~U+5385 FangQ L3 tchaikov U+5386~U+53EA FangQ L3 tchaikov U+53EB~U+544F amadeoh/FangQ L3 wanghong U+5450~U+54B4 :anonymous: L3 tchaikov U+54B5~U+5519 FangQ L3 tchaikov U+551A~U+557E :anonymous: L3 FangQ U+557F~U+55E3 FangQ L3 FangQ U+55E4~U+5648 :anonymous: L3 wanghong U+5649~U+56AD FangQ L3 wanghong U+56AE~U+5712 vertex/FangQ L3 FangQ U+5713~U+5777 xnuxmwx L3 FangQ U+5778~U+57DC wanghong L3 FangQ U+57DD~U+5841 FangQ L3 tchaikov U+5842~U+58A6 fundawang L3 tchaikov U+58A7~U+590B :anonymous: L1 FangQ U+590C~U+5970 FangQ L1 FangQ U+5971~U+59D5 wanghong L1 FangQ U+59D6~U+5A3A :anonymous: L1 FangQ U+5A3B~U+5A9F brep) L3 FangQ U+5AA0~U+5B04 :anonymous: L1 FangQ U+5B05~U+5B69 pinker) L1 FangQ U+5B6A~U+5BCE fundawang L1 FangQ U+5BCF~U+5C33 fundawang) L3 FangQ U+5C34~U+5C98 fundawang) L3 FangQ U+5C99~U+5CFD ailantian L3 FangQ U+5CFE~U+5D62 :anonymous: L1 FangQ U+5D63~U+5DC7 :anonymous: L1 FangQ U+5DC8~U+5E2C :anonymous: L1 FangQ U+5E2D~U+5E91 chaoslawful L3 FangQ U+5E92~U+5EF6 brep L3 FangQ U+5EF7~U+5F5B xnuxmwx L3 FangQ U+5F5C~U+5FC0 FangQ L3 wanghong U+5FC1~U+6025 keykeen L3 wanghong U+6026~U+608A pangwa L3 tchaikov U+608B~U+60EF :anonymous: L3 tchaikov U+60F0~U+6154 :anonymous: L3 wanghong U+6155~U+61B9 :anonymous: L3 wanghong U+61BA~U+621E wanghong L3 wanghong U+621F~U+6283 FangQ L3 wanghong U+6284~U+62E8 brep L3 tchaikov U+62E9~U+634D brep L3 FangQ U+634E~U+63B2 FangQ L3 tchaikov U+63B3~U+6417 :anonymous: L3 tchaikov U+6418~U+647C :anonymous: L1 FangQ U+647D~U+64E1 wanghong L1 FangQ U+64E2~U+6546 wanghong L1 FangQ U+6547~U+65AB :anonymous: L1 FangQ U+65AC~U+6610 keykeen L1 FangQ U+6611~U+6675 FangQ L1 FangQ U+6676~U+66DA FangQ L1 FangQ U+66DB~U+673F FangQ L1 FangQ U+6740~U+67A4 FangQ L1 FangQ U+67A5~U+6809 FangQ L1 FangQ U+680A~U+686E activeion L1 FangQ U+686F~U+68D3 FangQ L1 FangQ U+68D4~U+6938 wanghong L1 FangQ U+6939~U+699D wanghong L1 FangQ U+699E~U+6A02 wanghong L1 FangQ U+6A03~U+6A67 wanghong L1 FangQ U+6A68~U+6ACC pinker L1 FangQ U+6ACD~U+6B31 FangQ L1 FangQ U+6B32~U+6B96 wanghong L1 FangQ U+6B97~U+6BFB FangQ L1 FangQ U+6BFC~U+6C60 FangQ L1 FangQ U+6C61~U+6CC5 wuler.lv L3 wanghong U+6CC6~U+6D2A wuler.lv L3 wanghong U+6D2B~U+6D8F wanghong L1 FangQ U+6D90~U+6DF4 wanghong L1 FangQ U+6DF5~U+6E59 wanghong L1 FangQ U+6E5A~U+6EBE wanghong L1 FangQ U+6EBF~U+6F23 wanghong L1 FangQ U+6F24~U+6F88 wanghong L2 wanghong U+6F89~U+6FED wanghong L3 tchaikov U+6FEE~U+7052 wanghong L3 tchaikov U+7053~U+70B7 wanghong L3 tchaikov U+70B8~U+711C wanghong L3 wanghong U+711D~U+7181 wanghong L3 wanghong U+7182~U+71E6 wanghong L3 tchaikov U+71E7~U+724B wanghong L3 tchaikov U+724C~U+72B0 wanghong L3 tchaikov U+72B1~U+7315 wanghong L3 tchaikov U+7316~U+737A wanghong L3 tchaikov U+737B~U+73DF wanghong L3 tchaikov U+73E0~U+7444 wanghong L3 tchaikov U+7445~U+74A9 wanghong L3 tchaikov U+74AA~U+750E wanghong L3 tchaikov U+750F~U+7573 wanghong L3 tchaikov U+7574~U+75D8 wanghong L3 tchaikov U+75D9~U+763D wanghong L3 tchaikov U+763E~U+76A2 wanghong L3 tchaikov U+76A3~U+7707 wanghong L3 tchaikov U+7708~U+776C wanghong L3 tchaikov U+776D~U+77D1 wanghong L3 tchaikov U+77D2~U+7836 keykeen L3 tchaikov U+7837~U+789B keykeen L3 tchaikov U+789C~U+7900 keykeen L3 tchaikov U+7901~U+7965 keykeen ?? tchaikov U+7966~U+79CA keykeen ?? tchaikov U+79CB~U+7A2F pathfinder ?? tchaikov U+7A30~U+7A94 wanghong ?? tchaikov U+7A95~U+7AF9 wanghong (not done yet) U+7AFA~U+7B5E xnuxmwx (not done yet) U+7B5F~U+7BC3 keykeen (not done yet) U+7BC4~U+7C28 keykeen/FangQ (not done yet) U+7C29~U+7C8D FangQ (not done yet) U+7C8E~U+7CF2 FangQ/LiuQingyan (not done yet) U+7CF3~U+7D57 keykeen (not done yet) U+7D58~U+7DBC chaoslawful (not done yet) U+7DBD~U+7E21 tchaikov (not done yet) U+7E22~U+7E86 liyi (not done yet) U+7E87~U+7EEB brep (not done yet) U+7EEC~U+7F50 FangQ (not done yet) U+7F51~U+7FB5 FangQ (not done yet) U+7FB6~U+801A brep (not done yet) U+801B~U+807F liyi (not done yet) U+8080~U+80E4 tchaikov (not done yet) U+80E5~U+8149 ailantian (not done yet) U+814A~U+81AE lucifer (not done yet) U+81AF~U+8213 keykeen (not done yet) U+8214~U+8278 keykeen (not done yet) U+8279~U+82DD caiqian (not done yet) U+82DE~U+8342 wanghong (not done yet) U+8343~U+83A7 keykeen (not done yet) U+83A8~U+840C keykeen (not done yet) U+840D~U+8471 keykeen (not done yet) U+8472~U+84D6 wanghong (not done yet) U+84D7~U+853B BabyPBC (not done yet) U+853C~U+85A0 BabyPBC (not done yet) U+85A1~U+8605 FangQ (not done yet) U+8606~U+866A tchaikov (not done yet) U+866B~U+86CF keykeen (not done yet) U+86D0~U+8734 ailantian (not done yet) U+8735~U+8799 wanghong (not done yet) U+879A~U+87FE chaoslawful (not done yet) U+87FF~U+8863 wanghong (not done yet) U+8864~U+88C8 lucifer (not done yet) U+88C9~U+892D lucifer (not done yet) U+892E~U+8992 wanghong (not done yet) U+8993~U+89F7 wanghong (not done yet) U+89F8~U+8A5C ailantian (not done yet) U+8A5D~U+8AC1 ailantian (not done yet) U+8AC2~U+8B26 ailantian (not done yet) U+8B27~U+8B8B wanghong (not done yet) U+8B8C~U+8BF0 stid (not done yet) U+8BF1~U+8C55 wanghong (not done yet) U+8C56~U+8CBA wanghong (not done yet) U+8CBB~U+8D1F pinker (not done yet) U+8D20~U+8D84 brep (not done yet) U+8D85~U+8DE9 ailantian (not done yet) U+8DEA~U+8E4E ailantian (not done yet) U+8E4F~U+8EB3 tchaikov (not done yet) U+8EB4~U+8F18 wanghong (not done yet) U+8F19~U+8F7D wanghong L3 FangQ U+8F7E~U+8FE2 chaoslawful L3 FangQ U+8FE3~U+9047 keykeen L3 FangQ U+9048~U+90AC keykeen L3 FangQ U+90AD~U+9111 wanghong L3 FangQ U+9112~U+9176 nilarcs L3 wanghong U+9177~U+91DB wanghong L3 wanghong U+91DC~U+9240 wanghong L3 wanghong U+9241~U+92A5 lucifer ?? wanghong U+92A6~U+930A FangQ ?? wanghong U+930B~U+936F FangQ ?? wanghong U+9370~U+93D4 wanghong ?? wanghong U+93D5~U+9439 FangQ (not done yet) U+943A~U+949E chaoslawful (not done yet) U+949F~U+9503 wanghong (not done yet) U+9504~U+9568 wanghong (not done yet) U+9569~U+95CD Yei (not done yet) U+95CE~U+9632 FangQ (not done yet) U+9633~U+9697 wanghong (not done yet) U+9698~U+96FC wanghong (not done yet) U+96FD~U+9761 wanghong (not done yet) U+9762~U+97C6 wanghong (not done yet) U+97C7~U+982B wanghong (not done yet) U+982C~U+9890 wanghong (not done yet) U+9891~U+98F5 wanghong (not done yet) U+98F6~U+995A FangQ (not done yet) U+995B~U+99BF wanghong (not done yet) U+99C0~U+9A24 wanghong (not done yet) U+9A25~U+9A89 wanghong (not done yet) U+9A8A~U+9AEE wanghong (not done yet) U+9AEF~U+9B53 wanghong (not done yet) U+9B54~U+9BB8 FangQ L3 wanghong U+9BB9~U+9C1D FangQ L3 wanghong U+9C1E~U+9C82 FangQ ?? wanghong U+9C83~U+9CE7 wanghong L1 wanghong U+9CE8~U+9D4C wanghong L3 wanghong U+9D4D~U+9DB1 FangQ L2 wanghong U+9DB2~U+9E16 wanghong L3 wanghong U+9E17~U+9E7B wanghong L3 wanghong U+9E7C~U+9EE0 wanghong L1 wanghong U+9EE1~U+9F45 wanghong L3 wanghong U+9F46~U+9FAA albert liu/FangQ L3 wanghong ---------------------------------------------------------- IV. Authors for CJK Extension A Glyphs * Project proceeded between 04/2005 to 07/2006 * Original project record: http://wenq.org/?CJKExtA_Index http://wenq.org/index.cgi?offline_ExtA * Progress log: http://wenq.org/index.cgi?CJKExtA_TeamB_Progress ---------------------------------------------------------- Unicode Author ---------------------------------------------------------- U3400 BLOCK by FangQ U3410 BLOCK by fundawang U3420 BLOCK by fundawang U3430 BLOCK by fundawang U3440 BLOCK by fundawang U3450 BLOCK by fundawang U3460 BLOCK by fundawang U3470 BLOCK by fundawang U3480 BLOCK by fundawang U3490 BLOCK by fundawang U34A0 BLOCK by fiag U34B0 BLOCK by :anonymous: U34C0 BLOCK by fundawang U34D0 BLOCK by fundawang U34E0 BLOCK by :anonymous: U34F0 BLOCK by :anonymous: U3500 BLOCK by fundawang,buick U3510 BLOCK by :anonymous: U3520 BLOCK by fundawang U3530 BLOCK by :anonymous: U3540 BLOCK by :anonymous: U3550 BLOCK by :anonymous: U3560 BLOCK by :anonymous: U3570 BLOCK by :anonymous: U3580 BLOCK by fundawang U3590 BLOCK by :anonymous: U35A0 BLOCK by qinling U35B0 BLOCK by :anonymous: U35C0 BLOCK by :anonymous: U35D0 BLOCK by qinling U35E0 BLOCK by fundawang U35F0 BLOCK by :anonymous: U3600 BLOCK by :anonymous: U3610 BLOCK by :anonymous: U3620 BLOCK by :anonymous: U3630 BLOCK by fundawang U3640 BLOCK by :anonymous: U3650 BLOCK by :anonymous: U3660 BLOCK by ZJQR U3670 BLOCK by ZJQR U3680 BLOCK by ZJQR U3690 BLOCK by MarkLam U36A0 BLOCK by MarkLam U36B0 BLOCK by MarkLam U36C0 BLOCK by MarkLam U36D0 BLOCK by MarkLam U36E0 BLOCK by MarkLam U36F0 BLOCK by MarkLam U3700 BLOCK by ZJQR U3710 BLOCK by ZJQR U3720 BLOCK by ZJQR U3730 BLOCK by ZJQR U3740 BLOCK by ZJQR U3750 BLOCK by ailantian U3760 BLOCK by ZJQR,ailantian U3770 BLOCK by ZJQR U3780 BLOCK by ZJQR U3790 BLOCK by ZJQR U37A0 BLOCK by MarkLam U37B0 BLOCK by MarkLam U37C0 BLOCK by MarkLam U37D0 BLOCK by MarkLam U37E0 BLOCK by MarkLam U37F0 BLOCK by MarkLam U3800 BLOCK by MarkLam U3810 BLOCK by ZJQR U3820 BLOCK by ZJQR U3830 BLOCK by FangQ U3840 BLOCK by ZJQR U3850 BLOCK by ZJQR U3860 BLOCK by ZJQR U3870 BLOCK by ZJQR,fundawang U3880 BLOCK by musiccow U3890 BLOCK by ZJQR,FangQ U38A0 BLOCK by ZJQR U38B0 BLOCK by :anonymous: U38C0 BLOCK by :anonymous: U38D0 BLOCK by :anonymous: U38E0 BLOCK by whppc U38F0 BLOCK by whppc U3900 BLOCK by PONY U3910 BLOCK by PONY U3920 BLOCK by PONY U3930 BLOCK by PONY U3940 BLOCK by ZJQR U3950 BLOCK by ZJQR U3960 BLOCK by fiag U3970 BLOCK by ZJQR U3980 BLOCK by fiag U3990 BLOCK by ZJQR U39A0 BLOCK by LeeZJQR U39B0 BLOCK by :anonymous: U39C0 BLOCK by PONY U39D0 BLOCK by PONY U39E0 BLOCK by PONY U39F0 BLOCK by PONY U3A00 BLOCK by PONY U3A10 BLOCK by PONY U3A20 BLOCK by PONY U3A30 BLOCK by :anonymous: U3A40 BLOCK by zhouyingxin U3A50 BLOCK by ZJQR U3A60 BLOCK by chenzhipeter U3A70 BLOCK by :anonymous: U3A80 BLOCK by PONY U3A90 BLOCK by PONY U3AA0 BLOCK by PONY U3AB0 BLOCK by :anonymous: U3AC0 BLOCK by :anonymous: U3AD0 BLOCK by failsafe U3AE0 BLOCK by failsafe U3AF0 BLOCK by failsafe U3B00 BLOCK by :anonymous:,fourbrow U3B10 BLOCK by :anonymous: U3B20 BLOCK by ZJQR U3B30 BLOCK by lenovox U3B40 BLOCK by lenovox U3B50 BLOCK by udi U3B60 BLOCK by :anonymous: U3B70 BLOCK by :anonymous: U3B80 BLOCK by :anonymous: U3B90 BLOCK by lenovox U3BA0 BLOCK by :anonymous: U3BB0 BLOCK by lrobinson U3BC0 BLOCK by :anonymous: U3BD0 BLOCK by chenzhipeter,ZJQR U3BE0 BLOCK by :anonymous: U3BF0 BLOCK by :anonymous: U3C00 BLOCK by :anonymous: U3C10 BLOCK by gsyZJQR U3C20 BLOCK by ZJQR U3C30 BLOCK by ZJQR U3C40 BLOCK by ZJQR U3C50 BLOCK by ZJQR U3C60 BLOCK by ZJQR U3C70 BLOCK by ZJQR U3C80 BLOCK by ZJQR U3C90 BLOCK by ZJQR U3CA0 BLOCK by ZJQR U3CB0 BLOCK by ZJQR U3CC0 BLOCK by udi U3CD0 BLOCK by :anonymous: U3CE0 BLOCK by :anonymous: U3CF0 BLOCK by ZJQR U3D00 BLOCK by leal U3D10 BLOCK by :anonymous: U3D20 BLOCK by ZJQR U3D30 BLOCK by ZJQR U3D40 BLOCK by ZJQR U3D50 BLOCK by ZJQR U3D60 BLOCK by ZJQR U3D70 BLOCK by ZJQR U3D80 BLOCK by ZJQR U3D90 BLOCK by ZJQR U3DA0 BLOCK by ZJQR U3DB0 BLOCK by ZJQR U3DC0 BLOCK by ZJQR U3DD0 BLOCK by ZJQR U3DE0 BLOCK by ZJQR U3DF0 BLOCK by ZJQR U3E00 BLOCK by ZJQR U3E10 BLOCK by ZJQR U3E20 BLOCK by ZJQR U3E30 BLOCK by ZJQR U3E40 BLOCK by ZJQR U3E50 BLOCK by ZJQR U3E60 BLOCK by ZJQR U3E70 BLOCK by ZJQR U3E80 BLOCK by ZJQR U3E90 BLOCK by ZJQR U3EA0 BLOCK by ZJQR U3EB0 BLOCK by udi,ZJQR U3EC0 BLOCK by :anonymous: U3ED0 BLOCK by :anonymous: U3EE0 BLOCK by :anonymous: U3EF0 BLOCK by :anonymous: U3F00 BLOCK by ZJQR U3F10 BLOCK by ZJQR U3F20 BLOCK by ZJQR U3F30 BLOCK by ZJQR U3F40 BLOCK by ZJQR U3F50 BLOCK by soicer U3F60 BLOCK by ZJQR U3F70 BLOCK by PONY U3F80 BLOCK by PONY U3F90 BLOCK by PONY U3FA0 BLOCK by PONY U3FB0 BLOCK by ZJQR U3FC0 BLOCK by ZJQR U3FD0 BLOCK by ZJQR U3FE0 BLOCK by ZJQR U3FF0 BLOCK by niqiu U4000 BLOCK by FangQ U4010 BLOCK by FangQ U4020 BLOCK by FangQ U4030 BLOCK by niqiu U4040 BLOCK by niqiu U4050 BLOCK by niqiu U4060 BLOCK by niqiu U4070 BLOCK by niqiu U4080 BLOCK by niqiu,FangQ U4090 BLOCK by niqiu,FangQ U40A0 BLOCK by niqiu,FangQ U40B0 BLOCK by niqiu,FangQ U40C0 BLOCK by buick U40D0 BLOCK by niqiu,FangQ U40E0 BLOCK by ZJQR U40F0 BLOCK by ZJQR U4100 BLOCK by buick U4110 BLOCK by xiaoma U4120 BLOCK by ZJQR U4130 BLOCK by ailantian U4140 BLOCK by ZJQR U4150 BLOCK by ZJQR U4160 BLOCK by ZJQR U4170 BLOCK by ZJQR U4180 BLOCK by ZJQR U4190 BLOCK by ZJQR U41A0 BLOCK by ZJQR U41B0 BLOCK by ZJQR U41C0 BLOCK by ZJQR U41D0 BLOCK by ZJQR U41E0 BLOCK by ZJQR U41F0 BLOCK by ZJQR U4200 BLOCK by ZJQR U4210 BLOCK by ZJQR U4220 BLOCK by ZJQR U4230 BLOCK by FangQ U4240 BLOCK by FangQ U4250 BLOCK by ZJQR U4260 BLOCK by ZJQR U4270 BLOCK by ZJQR U4280 BLOCK by ZJQR U4290 BLOCK by ZJQR U42A0 BLOCK by ZJQR U42B0 BLOCK by ZJQR U42C0 BLOCK by ZJQR U42D0 BLOCK by Seeker U42E0 BLOCK by twang467 U42F0 BLOCK by twang467 U4300 BLOCK by twang467 U4310 BLOCK by twang467 U4320 BLOCK by twang467 U4330 BLOCK by twang467 U4340 BLOCK by twang467 U4350 BLOCK by twang467 U4360 BLOCK by twang467 U4370 BLOCK by twang467 U4380 BLOCK by Blueelf U4390 BLOCK by twang467 U43A0 BLOCK by twang467 U43B0 BLOCK by twang467 U43C0 BLOCK by twang467 U43D0 BLOCK by twang467 U43E0 BLOCK by ZJQR U43F0 BLOCK by ZJQR U4400 BLOCK by ZJQR U4410 BLOCK by ZJQR U4420 BLOCK by ZJQR U4430 BLOCK by ZJQR U4440 BLOCK by whppc U4450 BLOCK by ZJQR U4460 BLOCK by ZJQR U4470 BLOCK by ZJQR U4480 BLOCK by ZJQR U4490 BLOCK by ZJQR U44A0 BLOCK by ZJQR U44B0 BLOCK by ZJQR U44C0 BLOCK by ZJQR U44D0 BLOCK by ZJQR U44E0 BLOCK by ZJQR U44F0 BLOCK by ZJQR U4500 BLOCK by :anonymous: U4510 BLOCK by ZJQR U4520 BLOCK by ZJQR U4530 BLOCK by ZJQR U4540 BLOCK by ZJQR U4550 BLOCK by ZJQR U4560 BLOCK by ZJQR U4570 BLOCK by ZJQR U4580 BLOCK by ZJQR U4590 BLOCK by ZJQR U45A0 BLOCK by ZJQR U45B0 BLOCK by ZJQR U45C0 BLOCK by ZJQR U45D0 BLOCK by ZJQR U45E0 BLOCK by ZJQR U45F0 BLOCK by havas U4600 BLOCK by havas U4610 BLOCK by ZJQR U4620 BLOCK by ZJQR U4630 BLOCK by ZJQR U4640 BLOCK by ZJQR U4650 BLOCK by ZJQR U4660 BLOCK by tchaikov U4670 BLOCK by ZJQR U4680 BLOCK by eka U4690 BLOCK by eka U46A0 BLOCK by ZJQR U46B0 BLOCK by ZJQR U46C0 BLOCK by xuande U46D0 BLOCK by ZJQR U46E0 BLOCK by tchaikov U46F0 BLOCK by tchaikov U4700 BLOCK by tchaikov U4710 BLOCK by tchaikov U4720 BLOCK by tchaikov U4730 BLOCK by tchaikov U4740 BLOCK by ZJQR U4750 BLOCK by ZJQR U4760 BLOCK by ZJQR U4770 BLOCK by ZJQR U4780 BLOCK by ZJQR U4790 BLOCK by wanghong U47A0 BLOCK by wanghong U47B0 BLOCK by wanghong U47C0 BLOCK by wanghong U47D0 BLOCK by buick U47E0 BLOCK by buick U47F0 BLOCK by PONY U4800 BLOCK by :anonymous: U4810 BLOCK by SCXS U4820 BLOCK by SCXS U4830 BLOCK by :anonymous: U4840 BLOCK by SCXS U4850 BLOCK by SCXS U4860 BLOCK by fiag U4870 BLOCK by fiag U4880 BLOCK by ZJQR U4890 BLOCK by ZJQR U48A0 BLOCK by ZJQR U48B0 BLOCK by ZJQR U48C0 BLOCK by :anonymous: U48D0 BLOCK by ZJQR U48E0 BLOCK by :anonymous: U48F0 BLOCK by :anonymous: U4900 BLOCK by ZJQR U4910 BLOCK by ZJQR U4920 BLOCK by musiccow U4930 BLOCK by musiccow U4940 BLOCK by musiccow U4950 BLOCK by ZJQR U4960 BLOCK by ZJQR U4970 BLOCK by ZJQR U4980 BLOCK by ZJQR U4990 BLOCK by ZJQR U49A0 BLOCK by ZJQR U49B0 BLOCK by ZJQR U49C0 BLOCK by ZJQR U49D0 BLOCK by eka U49E0 BLOCK by eka U49F0 BLOCK by :anonymous: U4A00 BLOCK by :anonymous: U4A10 BLOCK by :anonymous: U4A20 BLOCK by :anonymous: U4A30 BLOCK by :anonymous: U4A40 BLOCK by :anonymous: U4A50 BLOCK by :anonymous: U4A60 BLOCK by :anonymous: U4A70 BLOCK by :anonymous: U4A80 BLOCK by :anonymous: U4A90 BLOCK by :anonymous: U4AA0 BLOCK by :anonymous: U4AB0 BLOCK by :anonymous: U4AC0 BLOCK by :anonymous: U4AD0 BLOCK by :anonymous: U4AE0 BLOCK by :anonymous: U4AF0 BLOCK by :anonymous: U4B00 BLOCK by :anonymous: U4B10 BLOCK by :anonymous: U4B20 BLOCK by :anonymous: U4B30 BLOCK by :anonymous: U4B40 BLOCK by :anonymous: U4B50 BLOCK by :anonymous: U4B60 BLOCK by :anonymous: U4B70 BLOCK by :anonymous: U4B80 BLOCK by :anonymous: U4B90 BLOCK by :anonymous: U4BA0 BLOCK by :anonymous: U4BB0 BLOCK by :anonymous: U4BC0 BLOCK by :anonymous: U4BD0 BLOCK by :anonymous: U4BE0 BLOCK by :anonymous: U4BF0 BLOCK by :anonymous: U4C00 BLOCK by FangQ U4C10 BLOCK by :anonymous: U4C20 BLOCK by :anonymous: U4C30 BLOCK by :anonymous: U4C40 BLOCK by :anonymous: U4C50 BLOCK by :anonymous: U4C60 BLOCK by :anonymous: U4C70 BLOCK by :anonymous: U4C80 BLOCK by :anonymous: U4C90 BLOCK by :anonymous: U4CA0 BLOCK by :anonymous: U4CB0 BLOCK by :anonymous: U4CC0 BLOCK by :anonymous: U4CD0 BLOCK by :anonymous: U4CE0 BLOCK by :anonymous: U4CF0 BLOCK by :anonymous: U4D00 BLOCK by :anonymous: U4D10 BLOCK by :anonymous: U4D20 BLOCK by :anonymous: U4D30 BLOCK by :anonymous: U4D40 BLOCK by :anonymous: U4D50 BLOCK by :anonymous: U4D60 BLOCK by :anonymous: U4D70 BLOCK by :anonymous: U4D80 BLOCK by :anonymous: U4D90 BLOCK by :anonymous: U4DA0 BLOCK by :anonymous: *note: ZJQR for ZaiJianQingRen, SCXS for ShiCengXiangShi ---------------------------------------------------------- V. Authors for CJK Basic glyphs standard verfication *original project record: http://wenq.org/index.cgi?ProjectTotem ---------------------------------------------------------- Unicode Reviewer ---------------------------------------------------------- U+4E00~U+4E64 by FangQ U+4E65~U+4EC9 by FangQ U+4ECA~U+4F2E by FangQ U+4F2F~U+4F93 by mumchristmas U+4F94~U+4FF8 by mumchristmas U+4FF9~U+505D by mumchristmas U+505E~U+50C2 by mumchristmas U+50C3~U+5127 by mumchristmas U+5128~U+518C by lsz U+518D~U+51F1 by lsz U+51F2~U+5256 by lsz U+5257~U+52BB by fundawang U+52BC~U+5320 by fundawang U+5321~U+5385 by :anonymous: U+5386~U+53EA by tchaikov U+53EB~U+544F by tchaikov U+5450~U+54B4 by tchaikov U+54B5~U+5519 by tchaikov U+551A~U+557E by tchaikov U+557F~U+55E3 by tchaikov U+55E4~U+5648 by tchaikov U+5649~U+56AD by nihui U+56AE~U+5712 by tchaikov U+5713~U+5777 by tchaikov U+5778~U+57DC by tchaikov U+57DD~U+5841 by pem U+5842~U+58A6 by nihui U+58A7~U+590B by dblobster U+590C~U+5970 by tchaikov U+5971~U+59D5 by tchaikov U+59D6~U+5A3A by tchaikov U+5A3B~U+5A9F by tchaikov U+5AA0~U+5B04 by tchaikov U+5B05~U+5B69 by tchaikov U+5B6A~U+5BCE by tchaikov U+5BCF~U+5C33 by tchaikov U+5C34~U+5C98 by tchaikov U+5C99~U+5CFD by tchaikov U+5CFE~U+5D62 by tchaikov U+5D63~U+5DC7 by tchaikov U+5DC8~U+5E2C by tchaikov U+5E2D~U+5E91 by tchaikov U+5E92~U+5EF6 by tchaikov U+5EF7~U+5F5B by tchaikov U+5F5C~U+5FC0 by tchaikov U+5FC1~U+6025 by tchaikov U+6026~U+608A by tchaikov U+608B~U+60EF by tchaikov U+60F0~U+6154 by tchaikov U+6155~U+61B9 by tchaikov U+61BA~U+621E by tchaikov U+621F~U+6283 by tchaikov U+6284~U+62E8 by tchaikov U+62E9~U+634D by tchaikov U+634E~U+63B2 by tchaikov U+63B3~U+6417 by tchaikov U+6418~U+647C by tchaikov U+647D~U+64E1 by tchaikov U+64E2~U+6546 by tchaikov U+6547~U+65AB by tchaikov U+65AC~U+6610 by tchaikov U+6611~U+6675 by tchaikov U+6676~U+66DA by tchaikov U+66DB~U+673F by tchaikov U+6740~U+67A4 by wanghong U+67A5~U+6809 by wanghong U+680A~U+686E by wanghong U+686F~U+68D3 by wanghong U+68D4~U+6938 by wanghong U+6939~U+699D by wanghong U+699E~U+6A02 by wanghong U+6A03~U+6A67 by wanghong U+6A68~U+6ACC by wanghong U+6ACD~U+6B31 by wanghong U+6B32~U+6B96 by wanghong U+6B97~U+6BFB by wanghong U+6BFC~U+6C60 by wanghong U+6C61~U+6CC5 by wanghong U+6CC6~U+6D2A by wanghong U+6D2B~U+6D8F by wanghong U+6D90~U+6DF4 by wanghong U+6DF5~U+6E59 by wanghong U+6E5A~U+6EBE by wanghong U+6EBF~U+6F23 by wanghong U+6F24~U+6F88 by wanghong U+6F89~U+6FED by wanghong U+6FEE~U+7052 by wanghong U+7053~U+70B7 by wanghong U+70B8~U+711C by wanghong U+711D~U+7181 by wanghong U+7182~U+71E6 by wanghong U+71E7~U+724B by wanghong U+724C~U+72B0 by wanghong U+72B1~U+7315 by wanghong U+7316~U+737A by wanghong U+737B~U+73DF by wanghong U+73E0~U+7444 by wanghong U+7445~U+74A9 by tchaikov U+74AA~U+750E by lsz U+750F~U+7573 by lsz U+7574~U+75D8 by lsz U+75D9~U+763D by lsz U+763E~U+76A2 by lsz U+76A3~U+7707 by lsz U+7708~U+776C by lsz U+776D~U+77D1 by lsz U+77D2~U+7836 by lsz U+7837~U+789B by lsz U+789C~U+7900 by lsz U+7901~U+7965 by tchaikov U+7966~U+79CA by tchaikov U+79CB~U+7A2F by tchaikov U+7A30~U+7A94 by tchaikov U+7A95~U+7AF9 by tchaikov U+7AFA~U+7B5E by tchaikov U+7B5F~U+7BC3 by tchaikov U+7BC4~U+7C28 by tchaikov U+7C29~U+7C8D by tchaikov U+7C8E~U+7CF2 by tchaikov U+7CF3~U+7D57 by the_owl U+7D58~U+7DBC by the_owl U+7DBD~U+7E21 by wanghong U+7E22~U+7E86 by wanghong U+7E87~U+7EEB by wanghong U+7EEC~U+7F50 by wanghong U+7F51~U+7FB5 by wanghong U+7FB6~U+801A by wanghong U+801B~U+807F by wanghong U+8080~U+80E4 by wanghong U+80E5~U+8149 by wanghong U+814A~U+81AE by wanghong U+81AF~U+8213 by wanghong U+8214~U+8278 by wanghong U+8279~U+82DD by wanghong U+82DE~U+8342 by wanghong U+8343~U+83A7 by wanghong U+83A8~U+840C by wanghong U+840D~U+8471 by tchaikov U+8472~U+84D6 by tchaikov U+84D7~U+853B by FangQ U+853C~U+85A0 by FangQ U+85A1~U+8605 by FangQ U+8606~U+866A by FangQ U+866B~U+86CF by FangQ U+86D0~U+8734 by FangQ U+8735~U+8799 by FangQ U+879A~U+87FE by wanghong U+87FF~U+8863 by wanghong U+8864~U+88C8 by wanghong U+88C9~U+892D by wanghong U+892E~U+8992 by wanghong U+8993~U+89F7 by wanghong U+89F8~U+8A5C by wanghong U+8A5D~U+8AC1 by wanghong U+8AC2~U+8B26 by wanghong U+8B27~U+8B8B by wanghong U+8B8C~U+8BF0 by wanghong U+8BF1~U+8C55 by wanghong U+8C56~U+8CBA by wanghong U+8CBB~U+8D1F by FangQ U+8D20~U+8D84 by FangQ U+8D85~U+8DE9 by wanghong U+8DEA~U+8E4E by wanghong U+8E4F~U+8EB3 by wanghong U+8EB4~U+8F18 by wanghong U+8F19~U+8F7D by wanghong U+8F7E~U+8FE2 by wanghong U+8FE3~U+9047 by wanghong U+9048~U+90AC by wanghong U+90AD~U+9111 by wanghong U+9112~U+9176 by wanghong U+9177~U+91DB by FangQ U+91DC~U+9240 by FangQ U+9241~U+92A5 by FangQ U+92A6~U+930A by FangQ U+930B~U+936F by FangQ U+9370~U+93D4 by FangQ U+93D5~U+9439 by FangQ U+943A~U+949E by FangQ U+949F~U+9503 by FangQ U+9504~U+9568 by FangQ U+9569~U+95CD by FangQ U+95CE~U+9632 by FangQ U+9633~U+9697 by FangQ U+9698~U+96FC by FangQ U+96FD~U+9761 by FangQ U+9762~U+97C6 by FangQ U+97C7~U+982B by FangQ U+982C~U+9890 by FangQ U+9891~U+98F5 by FangQ U+98F6~U+995A by FangQ U+995B~U+99BF by FangQ U+99C0~U+9A24 by FangQ U+9A25~U+9A89 by FangQ U+9A8A~U+9AEE by FangQ U+9AEF~U+9B53 by FangQ U+9B54~U+9BB8 by FangQ U+9BB9~U+9C1D by FangQ U+9C1E~U+9C82 by wanghong U+9C83~U+9CE7 by wanghong U+9CE8~U+9D4C by wanghong U+9D4D~U+9DB1 by wanghong U+9DB2~U+9E16 by wanghong U+9E17~U+9E7B by wanghong U+9E7C~U+9EE0 by FangQ U+9EE1~U+9F45 by wanghong U+9F46~U+9FAA by FangQ ---------------------------------------------------------- VI. Other resources Webspace provider: Sourceforge provided free webspace and great tools to help the development: http://sf.net/ Wiki development: Qianqian Fang developed the WenQuanYi wiki software (Habitat wiki: http://wenq.org/habitat/) based on UseModWiki written by Clifford Adams. The Javascript font editor (Pixel: http://wenq.org/index.cgi?Pixel) was writen by Qianqian Fang. The font editor previewer was written by Chai Kov (tchaikov #sjtu _edu _cn) ========================================================== ================================================ FILE: Translations/wqy-bitmapsong/COPYING ================================================ GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. 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If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. 2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, c) Accompany it with the information you received as to the offer to distribute corresponding source code. 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If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Library General Public License instead of this License. ================================================ FILE: Translations/wqy-bitmapsong/README.md ================================================ This directory contains files included from the WenQuanYi Bitmap Song font release, obtainable on the project's [SourceForge download page][wqy-sf]. The project author, Fang QianQian, kindly agreed to provide the font using the "GPLv2 or later" license in order to be compatible with IronOS, which is licensed under GPLv3. The release package with the changed license was made available via the project's SourceForge page on 2021-02-03 with the file name [`wqy-bitmapsong-bdf-1.0.0-RC1_GPLv2+.tar.gz`][wqy-sf-dl]. [wqy-sf]: https://sourceforge.net/projects/wqy/files/wqy-bitmapfont/1.0.0-RC1/ [wqy-sf-dl]: https://sourceforge.net/projects/wqy/files/wqy-bitmapfont/1.0.0-RC1/wqy-bitmapsong-bdf-1.0.0-RC1_GPLv2%2B.tar.gz/download. ================================================ FILE: Translations/wqy-bitmapsong/README_original ================================================ ========================================================== Wen Quan Yi Bitmap Song CJK Fonts Release Notes ---------------------------------------------------------- Dedication: ---------------------------------------------------------- Summary: Authors : WenQuanYi Contributors Webpage : http://wenq.org/en/ Font Name: WenQuanYi Bitmap Song Version : 1.0 (Hero) RC1 (0.9.9.8) Release : 8 Copyright: 2004-2010, The WenQuanYi Project Board of Trustees and Qianqian Fang License : GPL v2 or later version (with font embedding exception **) ---------------------------------------------------------- May the Font be with you, forever! ---------------------------------------------------------- Legal Disclaimer: Copyright (c) 2004-2010, The WenQuanYi Project Board of Trustees and Qianqian Fang This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ---------------------------------------------------------- Table of Content I. Introduction II. Installation III. About "The WenQuanYi Project" IV. Links to Open-source CJK font resources ---------------------------------------------------------- I. Introduction WenQuanYi bitmap fonts include all 20,932 Unicode 5.2 CJK Unified Ideographs (U4E00 - U9FA5) and 6,582 CJK Extension A characters (U3400 - U4DB5) at 5 different pixel sizes (9pt-12X12, 10pt-13X13, 10.5pt-14x14, 11pt-15X15 and 12pt-16x16 pixel). Use of this bitmap font for on-screen display of Chinese (traditional and simplified) in web pages and elsewhere eliminates the annoying "blurring" problems caused by insufficient "hinting" of anti-aliased vector CJK fonts. In addition, Latin characters, Japanese Kanas and Korean Hangul glyphs (U+AC00~U+D7A3) are also included. This font was built upon the previous works by firefly (firefly[at]firefly(dot)idv(dot)tw)[2]. The 12pt bitmap glyphs between U3400-U9FA5 were derived from Chinese national standard GB19966-2005 [3]. We release this font to the public as an open-source software in terms of GNU General Public License version 2. You are free to copy, distribute, and/or modify this font as long as you pass the freedoms to the users of the derived work. We hope you find this font useful. Please direct your feedback and bug-reports to our forum at http://wenq.org/forum/ In addition to bitmap font development, we also develop vector fonts and other CJK-related resources at WenQuanYi. Please join us by visiting our website at http://wenq.org/en/ We also welcome donations if you found this font to be useful to you. ---------------------------------------------------------- II. Installation Guide Please refer to INSTALL for details. ---------------------------------------------------------- III. About The WenQuanYi Project The Wen Quan Yi Project was founded by Qianqian Fang[5] in Oct. 2004. The goal of this project is to develop CJK related open-source software and resources. The initial effots of the project focused on creating high quality bitmap character glyphs and outline fonts for all 70,000+ CJK characters currently encoded by the Unicode Consortium [4]. The contributors of the Wen Quan Yi Project use wiki[1] as the primary development tool for glyph creation, documentation and coordinations. The Wen Quan Yi wiki (Habitat wiki: http://wenq.org/habitat/ ) was developed by Qianqian Fang based on UseModWiki v1.0. For commercial use, please contact the project maintainer (Qianqian Fang) or consult copyright law firms to make sure your plan is compliant with the font licenses. Commercial licenses are also available upon request. ---------------------------------------------------------- IV. Links to Open-source CJK font resources [1] The WenQuanYi Project Homepage http://wenq.org/ (Chinese version) http://wenq.org/en/ (English version) http://wenq.org/forum/ (User forum) [2] Firefly bitmap font http://www.study-area.org/apt/firefly-font/ [3] Chinese National Standard GB19966-2005 (mandatory) http://www.standardcn.com/standard_plan/list_standard_content.asp? stand_id=GB@19966-2005 [4] The Unicode Consortium http://www.unicode.org/ [5] Qianqian Fang homepage http://nmr.mgh.harvard.edu/~fangq/ ** GPL v2.0 license with font embedding exception: As a special exception, if you create a document which uses this font, and embed this font or unaltered portions of this font into the document, this font does not by itself cause the resulting document to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the document might be covered by the GNU General Public License. If you modify this font, you may extend this exception to your version of the font, but you are not obligated to do so. If you do not wish to do so, delete this exception statement from your version. ========================================================== ================================================ FILE: Translations/wqy-bitmapsong/wenquanyi_9pt.bdf ================================================ STARTFONT 2.1 FONT -wenquanyi-wenquanyi bitmap song-medium-r-normal--12-120-75-75-P-119-ISO10646-1 COMMENT ========================================================== COMMENT Wen Quan Yi Bitmap Song COMMENT ---------------------------------------------------------- COMMENT Summary: COMMENT COMMENT Authors : WenQuanYi Contributors COMMENT Webpage : http://wenq.org/en/ COMMENT Font Name: WenQuanYi Bitmap Song COMMENT Version : 0.9.9.8 COMMENT Release : 8 COMMENT Copyright: (C)2004-2010, WenQuanYi Project COMMENT Board of Trustees and Qianqian Fang COMMENT License : GPL v2 or later versions (with font embedding exception) COMMENT COMMENT May the Font be with you, forever! COMMENT ---------------------------------------------------------- COMMENT WenQuanYi bitmap fonts include all 20,932 Unicode 5.2 COMMENT CJK Unified Ideographs (U4E00 - U9FA5) and 6,582 COMMENT CJK Extension A characters (U3400 - U4DB5) at COMMENT 5 different pixel sizes (9pt-12X12, 10pt-13X13, COMMENT 10.5pt-14x14, 11pt-15X15 and 12pt-16x16 pixel). COMMENT Use of this bitmap font for on-screen display of Chinese COMMENT (traditional and simplified) in web pages and elsewhere COMMENT eliminates the annoying "blurring" problems caused by COMMENT insufficient "hinting" of anti-aliased vector CJK fonts. COMMENT In addition, Latin characters, Japanese Kanas and COMMENT Korean Hangul glyphs (U+AC00~U+D7A3) are also included. COMMENT ---------------------------------------------------------- COMMENT WenQuanYi Contributors: COMMENT COMMENT Project Maintainer: Qianqian Fang(fangqnmr.mgh.harvard.edu) COMMENT COMMENT Major contributors: wanghong, tchaikov,ailantian,niqiu,fiag COMMENT caiqian,fundawang COMMENT Other contributors: activeion,amadeoh,BabyPBC,BenBear, COMMENT brep,chaoslawful,DannyZeng,farm,fiag,keykeen, COMMENT liyi,lucifer,nilarcs,niqiu,pangwa,pathfinder, COMMENT pinker,PONY,pupilzeng,shhky,stid,wuler.lv, COMMENT xnuxmwx,namespace,leftstand,MarkLam,buick, COMMENT liqian,qinling,Seeker,xiaoma,ZaiJianQingRen, COMMENT SiCengXiangShi,the_owl,whppc,eka,failsafe, COMMENT musiccow,Blueelf,lenovox,udi,leal COMMENT ---------------------------------------------------------- COMMENT This file: WenQuanYi Bitmap Song 9pt medium COMMENT Created by Qianqian Fang (fangqnmr.mgh.harvard.edu) COMMENT ---------------------------------------------------------- SIZE 12 75 75 FONTBOUNDINGBOX 12 14 0 -3 STARTPROPERTIES 27 FONT_NAME "WenQuanYi Bitmap Song" FONT_ASCENT 12 FONT_DESCENT 3 UNDERLINE_POSITION -3 UNDERLINE_THICKNESS 1 QUAD_WIDTH 12 X_HEIGHT 5 CAP_HEIGHT 7 FONTNAME_REGISTRY "" FAMILY_NAME "WenQuanYi Bitmap Song" FOUNDRY "WenQuanYi" WEIGHT_NAME "Medium" SETWIDTH_NAME "Normal" SLANT "R" ADD_STYLE_NAME "" FONT_VERSION "000.998" PIXEL_SIZE 12 POINT_SIZE 120 DEFAULT_CHAR 0 RESOLUTION_X 75 RESOLUTION_Y 75 RESOLUTION 75 SPACING "P" AVERAGE_WIDTH 119 CHARSET_REGISTRY "ISO10646" CHARSET_ENCODING "1" CHARSET_COLLECTIONS "ASCII ISO8859-5 GB2312.1980 BIG5-0 KSC5601.1989-0 JISX0208.1997 ISO10646-1" ENDPROPERTIES CHARS 30503 STARTCHAR nounicode-3-1-c ENCODING 12 SWIDTH 333 0 DWIDTH 6 0 BBX 1 1 0 0 BITMAP 00 ENDCHAR STARTCHAR nounicode-3-1-d ENCODING 13 SWIDTH 333 0 DWIDTH 4 0 BBX 1 1 3 -1 BITMAP 00 ENDCHAR STARTCHAR U_0020 ENCODING 32 SWIDTH 500 0 DWIDTH 6 0 BBX 1 1 0 0 BITMAP 00 ENDCHAR STARTCHAR exclam ENCODING 33 SWIDTH 500 0 DWIDTH 6 0 BBX 1 9 2 0 BITMAP 80 80 80 80 80 80 00 00 80 ENDCHAR STARTCHAR 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BBX 11 11 0 -1 BITMAP 0000 0000 0000 F000 3000 5200 9100 8100 8100 4200 3C00 ENDCHAR STARTCHAR U_21BC ENCODING 8636 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1000 2000 4000 FFE0 0000 0000 0000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_21BD ENCODING 8637 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 4000 2000 1000 0000 0000 0000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_21BE ENCODING 8638 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 8000 C000 A000 9000 8000 8000 8000 8000 8000 8000 8000 ENDCHAR STARTCHAR U_21BF ENCODING 8639 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1000 3000 5000 9000 1000 1000 1000 1000 1000 1000 1000 ENDCHAR STARTCHAR U_21C0 ENCODING 8640 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0080 0040 FFE0 0000 0000 0000 0000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_21C1 ENCODING 8641 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 0000 0000 0000 0000 FFE0 0040 0080 ENDCHAR STARTCHAR U_21C2 ENCODING 8642 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 8000 8000 8000 8000 8000 8000 8000 8000 A000 C000 8000 ENDCHAR STARTCHAR U_21C3 ENCODING 8643 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 2000 2000 2000 2000 2000 2000 2000 A000 6000 2000 ENDCHAR STARTCHAR U_21C4 ENCODING 8644 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0080 0040 FFE0 0040 2080 4000 FFE0 4000 2000 0000 0000 ENDCHAR STARTCHAR U_21C5 ENCODING 8645 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 7200 AA00 2200 2200 2200 2200 2200 2A80 2700 2200 ENDCHAR STARTCHAR U_21C6 ENCODING 8646 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 2000 4000 FFE0 4000 2080 0040 FFE0 0040 0080 ENDCHAR STARTCHAR U_21C7 ENCODING 8647 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 4000 FFE0 4000 2000 2000 4000 FFE0 4000 2000 0000 ENDCHAR STARTCHAR U_21C8 ENCODING 8648 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 7380 AD40 2100 2100 2100 2100 2100 2100 2100 2100 ENDCHAR STARTCHAR U_21C9 ENCODING 8649 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 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BITMAP 0000 1000 2000 7FE0 8000 8000 7FE0 2000 1000 0000 0000 ENDCHAR STARTCHAR U_21D1 ENCODING 8657 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1800 2400 6600 A500 2400 2400 2400 2400 2400 2400 2400 ENDCHAR STARTCHAR U_21D2 ENCODING 8658 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0100 0080 FFC0 0020 FFC0 0080 0100 0000 0000 0000 ENDCHAR STARTCHAR U_21D3 ENCODING 8659 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2800 2800 2800 2800 2800 2800 2800 AA00 6C00 2800 1000 ENDCHAR STARTCHAR U_21D4 ENCODING 8660 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 2080 7FC0 8020 7FC0 2080 0000 0000 0000 ENDCHAR STARTCHAR U_21D5 ENCODING 8661 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 3000 4800 CC00 4800 4800 4800 4800 4800 CC00 4800 3000 ENDCHAR STARTCHAR U_21D6 ENCODING 8662 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP F800 9000 8800 C400 A200 1100 0880 0440 0220 0100 0080 ENDCHAR STARTCHAR U_21D7 ENCODING 8663 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 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8000 8000 8000 8000 8000 9000 9000 6000 ENDCHAR STARTCHAR U_2202 ENCODING 8706 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 3800 4400 0400 0400 3C00 4400 8800 9000 6000 ENDCHAR STARTCHAR U_2203 ENCODING 8707 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FC00 0400 0400 0400 0400 7C00 0400 0400 0400 0400 FC00 ENDCHAR STARTCHAR U_2204 ENCODING 8708 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0800 FC00 1400 1400 1400 7C00 2400 2400 2400 FC00 4000 ENDCHAR STARTCHAR U_2205 ENCODING 8709 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 1E40 2180 4180 8240 8440 8840 9040 6080 6100 9E00 ENDCHAR STARTCHAR U_2206 ENCODING 8710 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 1000 1000 2800 2800 4400 4400 8200 8200 FE00 ENDCHAR STARTCHAR U_2207 ENCODING 8711 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 FE00 8200 8200 4400 4400 2800 2800 1000 1000 ENDCHAR STARTCHAR U_2208 ENCODING 8712 SWIDTH 1000 0 DWIDTH 12 0 BBX 6 10 3 0 BITMAP 1C 20 40 80 FC 80 80 40 20 1C ENDCHAR STARTCHAR U_2209 ENCODING 8713 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0400 3E00 4800 8800 FC00 9000 5000 3E00 2000 0000 ENDCHAR STARTCHAR U_220A ENCODING 8714 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 7000 8000 F000 8000 7000 0000 0000 ENDCHAR STARTCHAR U_220B ENCODING 8715 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 F800 0400 0200 FE00 0200 0400 F800 0000 0000 ENDCHAR STARTCHAR U_220C ENCODING 8716 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0400 FF00 08C0 0840 0820 FFE0 1020 1040 10C0 FF00 2000 ENDCHAR STARTCHAR U_220D ENCODING 8717 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 7800 0400 0200 0200 7E00 0200 0400 0800 F000 ENDCHAR STARTCHAR U_220E ENCODING 8718 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 FF80 FF80 FF80 FF80 FF80 FF80 FF80 FF80 FF80 0000 ENDCHAR STARTCHAR U_220F ENCODING 8719 SWIDTH 1000 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP FF80 4100 4100 4100 4100 4100 4100 4100 4100 E380 ENDCHAR STARTCHAR U_2210 ENCODING 8720 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 8200 8200 8200 8200 8200 8200 8200 8200 8200 8200 FE00 ENDCHAR STARTCHAR U_2211 ENCODING 8721 SWIDTH 1000 0 DWIDTH 12 0 BBX 8 10 2 0 BITMAP FF 41 20 10 08 08 10 20 41 FF ENDCHAR STARTCHAR U_2212 ENCODING 8722 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 0000 FE00 0000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_2213 ENCODING 8723 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 F800 0000 2000 2000 F800 2000 2000 0000 0000 ENDCHAR STARTCHAR U_2214 ENCODING 8724 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 1000 0000 1000 1000 1000 FE00 1000 1000 1000 0000 ENDCHAR STARTCHAR U_2215 ENCODING 8725 SWIDTH 1000 0 DWIDTH 12 0 BBX 6 11 3 -1 BITMAP 04 08 08 10 10 20 20 40 40 80 80 ENDCHAR STARTCHAR U_2216 ENCODING 8726 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 8000 8000 4000 4000 2000 2000 1000 1000 0800 0800 ENDCHAR STARTCHAR U_2217 ENCODING 8727 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 2000 A800 7000 7000 A800 2000 0000 0000 ENDCHAR STARTCHAR U_2218 ENCODING 8728 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 6000 9000 9000 6000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_2219 ENCODING 8729 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 C000 C000 0000 0000 0000 0000 0000 ENDCHAR STARTCHAR U_221A ENCODING 8730 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 03E0 0200 0400 0400 0800 0800 4800 D000 5000 2000 2000 ENDCHAR STARTCHAR U_221B ENCODING 8731 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP CF00 2800 4800 3000 D000 1000 2000 A000 A000 4000 4000 ENDCHAR STARTCHAR U_221C ENCODING 8732 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP A400 A400 F400 2800 0800 0800 D000 5000 5000 2000 2000 ENDCHAR STARTCHAR U_221D ENCODING 8733 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 6 0 2 BITMAP 3870 4480 8300 8300 4480 3870 ENDCHAR STARTCHAR U_221E ENCODING 8734 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 6 0 2 BITMAP 38E0 4510 8208 8208 4510 38E0 ENDCHAR STARTCHAR U_221F ENCODING 8735 SWIDTH 1000 0 DWIDTH 12 0 BBX 9 9 2 1 BITMAP 0000 8000 8000 8000 8000 8000 8000 8000 FFE0 ENDCHAR STARTCHAR U_2220 ENCODING 8736 SWIDTH 1000 0 DWIDTH 12 0 BBX 10 9 1 1 BITMAP 0080 0100 0200 0400 0800 1000 2000 4000 FF80 ENDCHAR STARTCHAR U_2221 ENCODING 8737 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0040 0080 0100 0200 1C00 0A00 1100 2080 4080 FFE0 0080 ENDCHAR STARTCHAR U_2222 ENCODING 8738 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0020 02C0 0300 0D00 3080 C080 3080 0D00 0300 02C0 0020 ENDCHAR STARTCHAR U_2223 ENCODING 8739 SWIDTH 1000 0 DWIDTH 6 0 BBX 1 12 0 -1 BITMAP 80 80 80 80 80 80 80 80 80 80 80 80 ENDCHAR STARTCHAR U_2224 ENCODING 8740 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 2000 2000 2800 3000 6000 A000 2000 2000 2000 2000 ENDCHAR STARTCHAR U_2225 ENCODING 8741 SWIDTH 1000 0 DWIDTH 12 0 BBX 3 11 4 -1 BITMAP A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 ENDCHAR STARTCHAR U_2226 ENCODING 8742 SWIDTH 1000 0 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0 BBX 11 6 0 2 BITMAP 20C0 4120 8220 8420 4840 3080 ENDCHAR STARTCHAR U_223E ENCODING 8766 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 3080 4840 8420 4240 2180 0000 0000 0000 ENDCHAR STARTCHAR U_223F ENCODING 8767 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 5000 8800 8800 0400 0400 0400 0220 0220 0140 0080 ENDCHAR STARTCHAR U_2240 ENCODING 8768 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 8000 4000 2000 2000 2000 4000 8000 8000 8000 4000 2000 ENDCHAR STARTCHAR U_2241 ENCODING 8769 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 0100 7220 8CC0 0B00 1000 2000 0000 ENDCHAR STARTCHAR U_2242 ENCODING 8770 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 FFE0 0000 6020 98C0 0700 0000 0000 ENDCHAR STARTCHAR U_2243 ENCODING 8771 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 0000 0000 7020 8C40 0380 0000 FFE0 0000 0000 ENDCHAR STARTCHAR U_2244 ENCODING 8772 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 0000 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ENDCHAR STARTCHAR U_35CA ENCODING 13770 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0000 7BC0 4A40 4A40 7BC0 0000 7BC0 4A40 4A40 7BC0 4A40 ENDCHAR STARTCHAR U_35CB ENCODING 13771 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0380 E480 AFE0 AA00 ABE0 AA80 AC80 EBE0 0880 1140 2620 ENDCHAR STARTCHAR U_35CC ENCODING 13772 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A820 A7C0 A280 A440 A7E0 A100 E7C0 0100 0FE0 ENDCHAR STARTCHAR U_35CD ENCODING 13773 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 00C0 EF00 A100 AFE0 A380 A540 BFE0 A440 E7C0 0440 07C0 ENDCHAR STARTCHAR U_35CE ENCODING 13774 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0800 1EE0 EAA0 AAA0 B6E0 A100 BFE0 A380 E540 1920 0100 ENDCHAR STARTCHAR U_35CF ENCODING 13775 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 E100 A300 A540 A920 A100 AFE0 A100 E5C0 0500 1FE0 ENDCHAR STARTCHAR U_35D0 ENCODING 13776 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 E200 AFE0 A480 AA40 B120 E000 AFC0 0A40 0940 1FE0 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ENDCHAR STARTCHAR U_55A2 ENCODING 21922 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 00C0 E700 A100 AFE0 A100 ADE0 A920 ED60 0920 0FE0 0820 ENDCHAR STARTCHAR U_55A3 ENCODING 21923 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 F3E0 9420 9BA0 92A0 93A0 F020 00C0 5240 4920 8920 ENDCHAR STARTCHAR U_55A4 ENCODING 21924 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 F7C0 9440 97C0 9440 9FE0 F100 97C0 0100 0100 0FE0 ENDCHAR STARTCHAR U_55A5 ENCODING 21925 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 AA40 AFE0 AA40 ABC0 E800 AFE0 0A40 1180 2660 ENDCHAR STARTCHAR U_55A6 ENCODING 21926 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1F80 1080 1F80 0000 F1E0 9520 F5E0 0400 4440 4440 7FC0 ENDCHAR STARTCHAR U_55A7 ENCODING 21927 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A820 AFE0 A000 A7C0 A440 E7C0 A440 0440 0FE0 ENDCHAR STARTCHAR U_55A8 ENCODING 21928 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 FFE0 9440 97C0 9000 9FE0 F820 9380 02A0 04A0 0860 ENDCHAR STARTCHAR U_55A9 ENCODING 21929 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 E500 A880 B760 A000 BD40 F540 9E80 1680 1D40 1540 ENDCHAR STARTCHAR U_55AA ENCODING 21930 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0400 FFE0 0400 75C0 5540 75C0 0400 FFE0 2140 2880 3060 ENDCHAR STARTCHAR U_55AB ENCODING 21931 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 05E0 FEA0 A4A0 BEA0 A520 BEC0 E200 BFE0 0200 0D80 3060 ENDCHAR STARTCHAR U_55AC ENCODING 21932 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 7F80 0800 FFE0 2080 DF60 1100 7FC0 4040 4F40 4940 4FC0 ENDCHAR STARTCHAR U_55AD ENCODING 21933 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A280 AFE0 A880 A900 EE40 A980 0E60 1080 2F00 ENDCHAR STARTCHAR U_55AE ENCODING 21934 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 79E0 4920 4920 7FE0 2240 3FC0 2240 3FC0 0200 7FE0 0200 ENDCHAR STARTCHAR U_55AF ENCODING 21935 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 1FC0 E480 BA60 AFC0 A200 EA80 BFE0 0880 0880 3080 ENDCHAR STARTCHAR U_55B0 ENCODING 21936 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 0280 F540 9FE0 9440 97C0 F440 87C0 0560 0480 0660 ENDCHAR STARTCHAR U_55B1 ENCODING 21937 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 E800 ABE0 AAA0 ABE0 AAA0 EBE0 A880 0BE0 1080 27E0 ENDCHAR STARTCHAR U_55B2 ENCODING 21938 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0480 E480 A8E0 BB20 A420 AB20 BEA0 E0A0 0A20 1520 15C0 ENDCHAR STARTCHAR U_55B3 ENCODING 21939 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 FFE0 9540 9920 97C0 9440 F7C0 9440 07C0 0000 1FE0 ENDCHAR STARTCHAR U_55B4 ENCODING 21940 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 02A0 EAC0 AB80 AAA0 BFE0 A100 E100 AFE0 0580 0940 1120 ENDCHAR STARTCHAR U_55B5 ENCODING 21941 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0280 F280 9FE0 9280 97E0 9520 F520 97E0 0520 07E0 0420 ENDCHAR STARTCHAR U_55B6 ENCODING 21942 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 4880 2500 FFC0 8040 BF40 2100 3F00 0000 7F80 4080 7F80 ENDCHAR STARTCHAR U_55B7 ENCODING 21943 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A540 AFE0 A440 AFE0 E820 A920 0920 0280 0C60 ENDCHAR STARTCHAR U_55B8 ENCODING 21944 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0480 FFE0 4440 7FC0 4440 7FC0 4440 0280 7B00 4A40 79C0 ENDCHAR STARTCHAR U_55B9 ENCODING 21945 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 FFE0 9280 9540 9FE0 9100 FFE0 9100 07C0 0100 1FE0 ENDCHAR STARTCHAR U_55BA ENCODING 21946 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 04C0 E700 A900 AA40 BBC0 A920 EBC0 A880 0AC0 0CA0 0920 ENDCHAR STARTCHAR U_55BB ENCODING 21947 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0300 E480 BB60 A000 AE20 AAA0 EEA0 AAA0 0EA0 0A20 0AE0 ENDCHAR STARTCHAR U_55BC ENCODING 21948 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0780 0900 F7C0 9040 97C0 9040 F7C0 8200 0D40 1460 03C0 ENDCHAR STARTCHAR U_55BD ENCODING 21949 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0920 F540 9FE0 9380 9540 9920 FFE0 9240 0680 0140 0E20 ENDCHAR STARTCHAR U_55BE ENCODING 21950 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 1280 7FE0 5220 1F80 2200 7FE0 0000 1F80 1080 1F80 ENDCHAR STARTCHAR U_55BF ENCODING 21951 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 3F80 2080 2080 FFE0 8A20 FBE0 0400 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_55C0 ENCODING 21952 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 11C0 7D40 1140 FE60 8400 7BC0 0140 7940 4880 7940 4A20 ENDCHAR STARTCHAR U_55C1 ENCODING 21953 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FC0 E900 A9C0 A900 ABE0 AAA0 EBC0 AA80 15C0 1540 2A60 ENDCHAR STARTCHAR U_55C2 ENCODING 21954 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 03E0 0C40 EA40 A580 A200 A7C0 A900 EFE0 A100 0920 0FE0 ENDCHAR STARTCHAR U_55C3 ENCODING 21955 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A440 A7C0 A000 AFE0 E820 ABA0 0AA0 0BA0 0860 ENDCHAR STARTCHAR U_55C4 ENCODING 21956 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1FE0 E200 A7C0 A440 A740 A5C0 E440 AFE0 1480 0300 1CE0 ENDCHAR STARTCHAR U_55C5 ENCODING 21957 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 07C0 F440 9740 95C0 9440 97C0 F140 9FE0 0280 0C60 ENDCHAR STARTCHAR U_55C6 ENCODING 21958 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0300 E680 A940 BFA0 A880 AF80 E880 AFC0 0C40 17C0 2440 ENDCHAR STARTCHAR U_55C7 ENCODING 21959 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0400 FFE0 2480 5540 FFE0 0000 3FC0 2940 2F40 2040 3FC0 ENDCHAR STARTCHAR U_55C8 ENCODING 21960 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0540 FA80 9540 97C0 9440 9FC0 FA40 9A40 0FC0 0820 07E0 ENDCHAR STARTCHAR U_55C9 ENCODING 21961 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 F100 97C0 9100 9FE0 9240 FF80 9440 0FA0 0540 1B20 ENDCHAR STARTCHAR U_55CA ENCODING 21962 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 07C0 F100 9FE0 9440 97C0 9440 F7C0 9440 07C0 0280 0C60 ENDCHAR STARTCHAR U_55CB ENCODING 21963 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 FFC0 A440 BFE0 AAA0 BFC0 E840 AFC0 0840 0FC0 0840 ENDCHAR STARTCHAR U_55CC ENCODING 21964 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0840 E480 BFE0 A280 A440 A820 BFE0 EAA0 AAA0 0AA0 1FE0 ENDCHAR STARTCHAR U_55CD ENCODING 21965 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0BE0 E520 BF20 A520 B5E0 B520 FF20 A5E0 0520 0A20 14E0 ENDCHAR STARTCHAR U_55CE ENCODING 21966 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 E900 AFC0 A900 AFC0 A900 EFE0 A020 0D20 0AA0 12C0 ENDCHAR STARTCHAR U_55CF ENCODING 21967 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0480 FFE0 9480 9300 9480 9960 F100 9FE0 0580 0940 1320 ENDCHAR STARTCHAR U_55D0 ENCODING 21968 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 EFE0 A920 A7C0 A100 A7C0 E100 1FE0 0440 07C0 0440 ENDCHAR STARTCHAR U_55D1 ENCODING 21969 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 E7C0 A100 AFE0 A440 AFA0 A000 EFE0 AAA0 0AA0 1FE0 ENDCHAR STARTCHAR U_55D2 ENCODING 21970 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0480 FFE0 9480 9380 9440 9BA0 F000 97C0 0440 07C0 0440 ENDCHAR STARTCHAR U_55D3 ENCODING 21971 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FC0 E480 A300 BFE0 AAA0 A440 EBA0 0100 1FE0 0540 0920 ENDCHAR STARTCHAR U_55D4 ENCODING 21972 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 FFE0 9440 97C0 9440 9740 F5C0 9440 0FE0 0280 0C60 ENDCHAR STARTCHAR U_55D5 ENCODING 21973 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 E800 ABC0 A800 AFE0 AAA0 EB40 AA60 0FE0 1440 22C0 ENDCHAR STARTCHAR U_55D6 ENCODING 21974 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0300 ED60 A920 AF60 A920 AFE0 E100 AFE0 0440 0380 1C60 ENDCHAR STARTCHAR U_55D7 ENCODING 21975 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 07C0 E440 A740 A540 AFE0 F460 87C0 0440 07C0 0440 04C0 ENDCHAR STARTCHAR U_55D8 ENCODING 21976 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 00E0 0F00 F520 92C0 97C0 9280 F7C0 9100 8FE0 0280 1C60 ENDCHAR STARTCHAR U_55D9 ENCODING 21977 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 FFE0 9440 9280 9FE0 9920 FFE0 9200 03C0 0440 1980 ENDCHAR STARTCHAR U_55DA ENCODING 21978 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0200 EFC0 A840 AFC0 A800 AFE0 E800 AFE0 0020 0AA0 1540 ENDCHAR STARTCHAR U_55DB ENCODING 21979 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0880 FFE0 A500 AFC0 A540 BFE0 E540 AFC0 0500 0D40 1520 ENDCHAR STARTCHAR U_55DC ENCODING 21980 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0100 F7E0 9140 9FE0 9380 9D20 F7E0 9440 07C0 0440 07C0 ENDCHAR STARTCHAR U_55DD ENCODING 21981 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0FE0 E440 A7C0 A000 AFE0 AAA0 E920 AFE0 0920 0920 0860 ENDCHAR STARTCHAR U_55DE ENCODING 21982 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0440 0280 EFE0 A240 A440 A480 A9A0 E640 A240 05A0 0EE0 ENDCHAR STARTCHAR U_55DF ENCODING 21983 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0440 F280 9FE0 9100 97C0 9100 FFE0 9400 0FC0 1100 2FE0 ENDCHAR STARTCHAR U_55E0 ENCODING 21984 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1A00 E7C0 AA40 5440 7A80 0900 1280 FFE0 1440 5440 27C0 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ENDCHAR STARTCHAR U_7C76 ENCODING 31862 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 A780 7480 2480 FC80 2480 7480 6C80 A4A0 24A0 2860 ENDCHAR STARTCHAR U_7C77 ENCODING 31863 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 A8C0 7700 2100 F900 27E0 7100 6900 A120 2120 20E0 ENDCHAR STARTCHAR U_7C78 ENCODING 31864 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 AFC0 7240 2240 FA40 27C0 7240 AA40 AA40 2260 2220 ENDCHAR STARTCHAR U_7C79 ENCODING 31865 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 7100 27E0 FA40 2280 7480 AB00 A980 2240 2C20 ENDCHAR STARTCHAR U_7C7A ENCODING 31866 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 AA00 73E0 2400 FBC0 2040 7080 A900 AA20 2220 21E0 ENDCHAR STARTCHAR U_7C7B ENCODING 31867 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 1500 FFE0 1500 2480 4040 0400 FFE0 0A00 1100 E0E0 ENDCHAR STARTCHAR U_7C7C ENCODING 31868 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2080 A880 7080 22A0 FAA0 22A0 72A0 AAA0 AAA0 23E0 2220 ENDCHAR STARTCHAR U_7C7D ENCODING 31869 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 23E0 A840 7080 2080 F880 27E0 7080 A880 AC80 2280 2100 ENDCHAR STARTCHAR U_7C7E ENCODING 31870 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 ABE0 7120 2520 F520 2520 7120 6A20 A220 24A0 2440 ENDCHAR STARTCHAR U_7C7F ENCODING 31871 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2040 A840 7040 27E0 F840 2240 7140 A940 AA40 2140 2080 ENDCHAR STARTCHAR U_7C80 ENCODING 31872 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2080 A880 77E0 2080 FA80 2280 7280 AA80 A900 2280 2C60 ENDCHAR STARTCHAR U_7C81 ENCODING 31873 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2040 AB80 7080 2080 FFE0 2080 7080 A880 A880 2080 2080 ENDCHAR STARTCHAR U_7C82 ENCODING 31874 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0800 1F00 2200 0400 1B00 E4E0 1500 FFE0 1500 E4E0 0400 ENDCHAR STARTCHAR U_7C83 ENCODING 31875 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 AC80 74A0 27C0 FC80 2480 7480 6C80 A5A0 26A0 2460 ENDCHAR STARTCHAR U_7C84 ENCODING 31876 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 20C0 AF00 7400 2400 FFC0 2540 7540 AD40 A480 2940 3620 ENDCHAR STARTCHAR U_7C85 ENCODING 31877 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 AA00 73E0 26A0 FAA0 22A0 72A0 ACA0 A920 2220 20C0 ENDCHAR STARTCHAR U_7C86 ENCODING 31878 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 7180 2540 FD20 2520 7140 6880 A100 2200 2C00 ENDCHAR STARTCHAR U_7C87 ENCODING 31879 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 A900 77E0 2000 FB80 2280 7280 6A80 A2A0 24A0 2860 ENDCHAR STARTCHAR U_7C88 ENCODING 31880 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 AFC0 7240 2240 FA40 27C0 7240 AA40 AA40 2240 2FE0 ENDCHAR STARTCHAR U_7C89 ENCODING 31881 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2280 AA80 7240 2420 F800 27C0 7240 6A40 A240 2440 2980 ENDCHAR STARTCHAR U_7C8A ENCODING 31882 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 4240 7A80 4320 7A20 C1E0 2480 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_7C8B ENCODING 31883 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 AA00 7780 FA80 22A0 74A0 6960 A100 2FE0 2100 2100 ENDCHAR STARTCHAR U_7C8C ENCODING 31884 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27A0 A8A0 70A0 23A0 FC20 27A0 70A0 A8A0 A8A0 24A0 2320 ENDCHAR STARTCHAR U_7C8D ENCODING 31885 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 21C0 AF00 7100 21C0 FF00 2100 71E0 AF00 A920 2120 20E0 ENDCHAR STARTCHAR U_7C8E ENCODING 31886 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 ABC0 7240 FA40 63C0 7280 AA80 2280 2440 2440 2820 ENDCHAR STARTCHAR U_7C8F ENCODING 31887 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 7100 27E0 F900 3280 6A80 6440 A640 2920 3120 ENDCHAR STARTCHAR U_7C90 ENCODING 31888 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A880 73E0 2220 FA20 23E0 7200 6A00 A200 2400 2400 ENDCHAR STARTCHAR U_7C91 ENCODING 31889 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 ABE0 72A0 22A0 FAA0 23E0 7200 AA00 A220 2220 21E0 ENDCHAR STARTCHAR U_7C92 ENCODING 31890 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A880 77E0 2000 FA40 2240 7140 A980 A880 2080 2FE0 ENDCHAR STARTCHAR U_7C93 ENCODING 31891 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2240 AA40 7240 27E0 FA40 2240 73C0 6A40 A240 A240 23C0 ENDCHAR STARTCHAR U_7C94 ENCODING 31892 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 23E0 AA00 7200 23E0 FA20 2220 73E0 AA00 AA00 2200 23E0 ENDCHAR STARTCHAR U_7C95 ENCODING 31893 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2080 A900 73E0 2220 FA20 23E0 7220 6A20 A220 23E0 2220 ENDCHAR STARTCHAR U_7C96 ENCODING 31894 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 77E0 2100 F900 27C0 7100 AB80 A540 2920 2100 ENDCHAR STARTCHAR U_7C97 ENCODING 31895 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 23C0 AA40 7240 23C0 FA40 2240 73C0 6A40 A240 2240 2FE0 ENDCHAR STARTCHAR U_7C98 ENCODING 31896 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 71E0 2100 F900 27E0 7420 AC20 A420 27E0 2420 ENDCHAR STARTCHAR U_7C99 ENCODING 31897 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2080 2080 A880 73E0 22A0 FAA0 23E0 72A0 6AA0 A2A0 23E0 ENDCHAR STARTCHAR U_7C9A ENCODING 31898 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 ABE0 7400 2900 F5E0 2720 6D20 7560 AD00 2420 27E0 ENDCHAR STARTCHAR U_7C9B ENCODING 31899 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0400 7FC0 0440 FFE0 0440 7FC0 1500 4E40 7FC0 4E40 9540 ENDCHAR STARTCHAR U_7C9C ENCODING 31900 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 2480 3F80 4440 4440 7FC0 2480 1500 FFE0 1500 E4E0 ENDCHAR STARTCHAR U_7C9D ENCODING 31901 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 AC00 7400 27E0 FD00 25E0 7520 AD20 A520 2AA0 3440 ENDCHAR STARTCHAR U_7C9E ENCODING 31902 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 AA80 7280 2FE0 FAA0 2AA0 7AE0 AC20 A820 2FE0 2820 ENDCHAR STARTCHAR U_7C9F ENCODING 31903 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 0A00 7FC0 4A40 7FC0 2480 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_7CA0 ENCODING 31904 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2000 AA40 7240 27E0 FA40 2240 7240 77E0 A000 2240 2420 ENDCHAR STARTCHAR U_7CA1 ENCODING 31905 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 A820 7BA0 2820 FBA0 2AA0 3AA0 6BA0 AAA0 2820 28E0 ENDCHAR STARTCHAR U_7CA2 ENCODING 31906 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 8400 57E0 6A20 C500 58E0 2480 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_7CA3 ENCODING 31907 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2EE0 AAA0 7AA0 2AA0 FFE0 2AA0 3AA0 6AA0 AAA0 2AA0 3560 ENDCHAR STARTCHAR U_7CA4 ENCODING 31908 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0800 7FC0 5540 7FC0 4E40 5540 FFE0 0800 3FC0 0040 0380 ENDCHAR STARTCHAR U_7CA5 ENCODING 31909 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP E4E0 2420 3520 EEE0 8580 9F80 E4E0 2E20 3520 2520 C4C0 ENDCHAR STARTCHAR U_7CA6 ENCODING 31910 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 1500 FFE0 1500 E4E0 1080 3BE0 4A80 ABE0 1080 E080 ENDCHAR STARTCHAR U_7CA7 ENCODING 31911 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A880 77E0 2400 FC80 2480 77E0 AC80 A480 2880 2BE0 ENDCHAR STARTCHAR U_7CA8 ENCODING 31912 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 A880 7100 23E0 FA20 2220 73E0 AA20 AA20 23E0 2220 ENDCHAR STARTCHAR U_7CA9 ENCODING 31913 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 77A0 F940 27E0 7080 6B00 A6C0 2B00 2220 21E0 ENDCHAR STARTCHAR U_7CAA ENCODING 31914 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 1500 FFE0 1500 2480 D160 7FC0 1100 FFE0 1100 E0E0 ENDCHAR STARTCHAR U_7CAB ENCODING 31915 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 A900 7200 2FE0 FAA0 2AA0 7AA0 6AA0 AAA0 2AA0 2860 ENDCHAR STARTCHAR U_7CAC ENCODING 31916 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2280 AA80 7280 FFE0 2AA0 3AA0 6FE0 AAA0 2AA0 2FE0 2820 ENDCHAR STARTCHAR U_7CAD ENCODING 31917 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 A900 7280 2440 FBA0 2000 77C0 6C40 A440 2440 27C0 ENDCHAR STARTCHAR U_7CAE ENCODING 31918 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 A900 77C0 2440 FFC0 2440 77E0 AD40 A480 2540 2620 ENDCHAR STARTCHAR U_7CAF ENCODING 31919 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 AC40 77C0 2440 FC40 27C0 7440 AFC0 A2A0 24A0 2860 ENDCHAR STARTCHAR U_7CB0 ENCODING 31920 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2060 AB80 72A0 2120 FBC0 2040 3080 6BE0 A080 2080 2180 ENDCHAR STARTCHAR U_7CB1 ENCODING 31921 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 4F80 A280 6AC0 D4A0 4B80 6480 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_7CB2 ENCODING 31922 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 3C00 23E0 7A40 C980 3260 C480 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_7CB3 ENCODING 31923 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 A900 77E0 2520 FFE0 2520 77E0 AD00 A500 2300 2CE0 ENDCHAR STARTCHAR U_7CB4 ENCODING 31924 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 ACA0 74A0 27E0 FCA0 27E0 7080 A880 ABE0 2080 2FE0 ENDCHAR STARTCHAR U_7CB5 ENCODING 31925 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0800 7FC0 5540 7FC0 5540 64C0 FFE0 1000 3F80 0080 0700 ENDCHAR STARTCHAR U_7CB6 ENCODING 31926 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 A840 77C0 F840 2FE0 7120 6D40 A380 2540 2920 2200 ENDCHAR STARTCHAR U_7CB7 ENCODING 31927 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 ABE0 7420 FD60 23A0 77E0 6D20 A3A0 2360 2520 20C0 ENDCHAR STARTCHAR U_7CB8 ENCODING 31928 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2240 AFE0 7240 23C0 FA40 23C0 7240 6A40 AFE0 2240 2420 ENDCHAR STARTCHAR U_7CB9 ENCODING 31929 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7240 2240 FDA0 2520 7100 6FE0 A100 2100 2100 ENDCHAR STARTCHAR U_7CBA ENCODING 31930 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7520 27E0 FD20 27E0 75A0 AA80 AFE0 2080 2080 ENDCHAR STARTCHAR U_7CBB ENCODING 31931 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 23E0 AA00 73C0 2200 FBC0 2200 77E0 AAA0 AAC0 2340 2620 ENDCHAR STARTCHAR U_7CBC ENCODING 31932 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 92A0 54A0 FEA0 5540 9340 2540 7D40 94A0 7EA0 24A0 C4A0 ENDCHAR STARTCHAR U_7CBD ENCODING 31933 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7420 23C0 F800 27E0 7100 AD40 A520 2920 2300 ENDCHAR STARTCHAR U_7CBE ENCODING 31934 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7100 27C0 F100 2FE0 7440 6FC0 A440 27C0 2440 ENDCHAR STARTCHAR U_7CBF ENCODING 31935 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 AD40 77C0 2540 FFC0 2100 77E0 A900 AB80 2540 2920 ENDCHAR STARTCHAR U_7CC0 ENCODING 31936 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 AFE0 7480 2280 FAA0 24C0 7480 6D80 A6A0 24A0 2460 ENDCHAR STARTCHAR U_7CC1 ENCODING 31937 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2240 AFE0 7100 27E0 FA80 2540 72A0 AD00 AA40 2180 2600 ENDCHAR STARTCHAR U_7CC2 ENCODING 31938 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 AFE0 7440 27C0 FC40 27C0 7440 6FE0 A680 2440 27E0 ENDCHAR STARTCHAR U_7CC3 ENCODING 31939 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 23C0 AA40 73C0 2240 FFE0 2200 77E0 6AA0 A520 22A0 2440 ENDCHAR STARTCHAR U_7CC4 ENCODING 31940 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7820 2FE0 F800 2FE0 7AA0 6FE0 AAA0 3AA0 2860 ENDCHAR STARTCHAR U_7CC5 ENCODING 31941 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 A940 7080 27E0 FAA0 2580 7100 AFE0 AB80 2540 2920 ENDCHAR STARTCHAR U_7CC6 ENCODING 31942 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 A900 7200 2FE0 FAA0 2BA0 7AA0 6BA0 AAA0 2FE0 2820 ENDCHAR STARTCHAR U_7CC7 ENCODING 31943 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 AC40 77E0 2500 FDE0 2680 77E0 AC80 A480 2540 2620 ENDCHAR STARTCHAR U_7CC8 ENCODING 31944 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 A920 75C0 2700 F9E0 2220 73E0 AA20 ABE0 2220 2260 ENDCHAR STARTCHAR U_7CC9 ENCODING 31945 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2280 AD20 76A0 27E0 F280 2D60 73C0 6A40 A580 2240 2420 ENDCHAR STARTCHAR U_7CCA ENCODING 31946 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 24E0 A4A0 7EA0 24E0 FEA0 2AA0 3AE0 6AA0 AEA0 2120 2260 ENDCHAR STARTCHAR U_7CCB ENCODING 31947 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 A280 7FE0 2000 FE20 2AA0 3EA0 6AA0 AEA0 2A20 2A60 ENDCHAR STARTCHAR U_7CCC ENCODING 31948 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 AF40 7560 2240 FD00 24E0 73C0 AA40 ABC0 2240 23C0 ENDCHAR STARTCHAR U_7CCD ENCODING 31949 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 AA80 77E0 2240 FA40 25A0 77E0 AA40 A240 25A0 2FE0 ENDCHAR STARTCHAR U_7CCE ENCODING 31950 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 AC00 77E0 26A0 FFE0 26A0 77E0 AC80 A7E0 2880 37E0 ENDCHAR STARTCHAR U_7CCF ENCODING 31951 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 A820 7FE0 2AA0 F9C0 2BE0 6A20 7BE0 AA20 2BE0 3220 ENDCHAR STARTCHAR U_7CD0 ENCODING 31952 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2140 AFE0 7520 27E0 FD20 27E0 7520 A840 AFE0 2240 21C0 ENDCHAR STARTCHAR U_7CD1 ENCODING 31953 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 A920 7760 2880 FFE0 2120 75A0 AB60 ADA0 2120 26C0 ENDCHAR STARTCHAR U_7CD2 ENCODING 31954 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2280 AFE0 7280 27E0 FA00 23E0 72A0 ABE0 AAA0 27E0 2AA0 ENDCHAR STARTCHAR U_7CD3 ENCODING 31955 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1380 7A80 1280 FCE0 8400 7DC0 5540 FD40 3880 5540 9220 ENDCHAR STARTCHAR U_7CD4 ENCODING 31956 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27E0 AD40 7280 2360 FD00 27E0 7520 AFE0 A900 2140 27A0 ENDCHAR STARTCHAR U_7CD5 ENCODING 31957 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2440 AA80 77E0 2100 F900 27C0 7100 AFE0 A540 2AA0 2AA0 ENDCHAR STARTCHAR U_7CD6 ENCODING 31958 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7940 2FE0 F940 2FC0 7900 ABC0 AA40 2A40 33C0 ENDCHAR STARTCHAR U_7CD7 ENCODING 31959 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFC0 7440 2740 FDC0 2440 77C0 A140 AFE0 2280 2C60 ENDCHAR STARTCHAR U_7CD8 ENCODING 31960 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2200 AFE0 7820 27C0 F920 2340 7580 6AC0 A5A0 22A0 2500 ENDCHAR STARTCHAR U_7CD9 ENCODING 31961 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2880 AE80 73E0 2480 FFE0 2400 75E0 AD20 A5E0 2A00 33E0 ENDCHAR STARTCHAR U_7CDA ENCODING 31962 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 AFE0 7480 2240 FA40 2EE0 7240 6E40 AA40 33E0 2200 ENDCHAR STARTCHAR U_7CDB ENCODING 31963 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2520 AB40 77E0 2420 FBC0 2240 73C0 6900 A3C0 2100 27E0 ENDCHAR STARTCHAR U_7CDC ENCODING 31964 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0400 FFE0 9100 FFE0 BB40 D560 A480 9500 FFE0 9500 E4E0 ENDCHAR STARTCHAR U_7CDD ENCODING 31965 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2140 ABA0 74A0 27E0 F880 2760 7280 AD20 A240 2080 2700 ENDCHAR STARTCHAR U_7CDE ENCODING 31966 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2480 FFE0 1500 7FC0 A4A0 3F80 7FC0 1100 FFE0 1100 E0E0 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ENDCHAR STARTCHAR U_7CE6 ENCODING 31974 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AFE0 7100 27C0 FC40 27C0 7280 6FE0 A440 27C0 2440 ENDCHAR STARTCHAR U_7CE7 ENCODING 31975 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 27C0 AC40 77C0 2440 FFE0 2540 37C0 6D40 AFE0 2100 2FE0 ENDCHAR STARTCHAR U_7CE8 ENCODING 31976 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 AA20 73E0 2C80 FBE0 2EA0 77E0 AEA0 A480 34A0 2BE0 ENDCHAR STARTCHAR U_7CE9 ENCODING 31977 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 AA80 7440 2FE0 FD60 2BA0 6FE0 7440 A7C0 2440 27C0 ENDCHAR STARTCHAR U_7CEA ENCODING 31978 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 7C80 47E0 7D40 43E0 7C80 A5E0 BE80 0A80 7FE0 1280 E260 ENDCHAR STARTCHAR U_7CEB ENCODING 31979 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 AAA0 7FE0 2000 FFE0 2440 77C0 6220 A540 2C80 2660 ENDCHAR STARTCHAR U_7CEC ENCODING 31980 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2FE0 AAA0 7FE0 2100 FFA0 2140 77E0 AA20 A7E0 2A20 23E0 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ENDCHAR STARTCHAR U_82EA ENCODING 33514 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 0400 7FC0 4640 4940 50C0 6040 41C0 ENDCHAR STARTCHAR U_82EB ENCODING 33515 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1500 07C0 0400 3FC0 2040 2040 3FC0 2040 ENDCHAR STARTCHAR U_82EC ENCODING 33516 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 4440 4440 4640 4940 50C0 4040 7FC0 ENDCHAR STARTCHAR U_82ED ENCODING 33517 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2100 47E0 F120 2120 4920 F620 44A0 0840 ENDCHAR STARTCHAR U_82EE ENCODING 33518 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1100 2200 6A40 AA40 2A40 2A40 2FC0 2000 ENDCHAR STARTCHAR U_82EF ENCODING 33519 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 0400 FFE0 0400 1500 2480 5F40 8420 0400 ENDCHAR STARTCHAR U_82F0 ENCODING 33520 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7880 0880 7900 4100 7A00 0A40 4FA0 3220 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ENDCHAR STARTCHAR U_82F8 ENCODING 33528 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 2480 1500 FFE0 0400 0400 1400 0800 ENDCHAR STARTCHAR U_82F9 ENCODING 33529 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 2480 1480 1500 FFE0 0400 0400 0400 ENDCHAR STARTCHAR U_82FA ENCODING 33530 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3F80 2880 2480 FFE0 4480 7FE0 0080 0300 ENDCHAR STARTCHAR U_82FB ENCODING 33531 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2080 2FE0 6080 A880 2480 2480 2080 2180 ENDCHAR STARTCHAR U_82FC ENCODING 33532 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 7FE0 1100 2400 2400 3FC0 4400 9F80 0400 0400 7FE0 ENDCHAR STARTCHAR U_82FD ENCODING 33533 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 03C0 3D00 2500 2480 2480 2540 46A0 8480 ENDCHAR STARTCHAR U_82FE ENCODING 33534 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 0480 1280 5100 5240 5420 98A0 1080 6F80 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ENDCHAR STARTCHAR U_83D8 ENCODING 33752 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 7FE0 0900 1080 7E80 1280 1D40 3520 5200 1440 17A0 ENDCHAR STARTCHAR U_83D9 ENCODING 33753 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1F00 FFE0 2480 FFE0 2480 FFE0 0400 7FC0 ENDCHAR STARTCHAR U_83DA ENCODING 33754 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 7FE0 0900 0600 1940 7FC0 0900 0640 79C0 ENDCHAR STARTCHAR U_83DB ENCODING 33755 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 4A40 7BC0 4A40 7BC0 4040 4140 4080 ENDCHAR STARTCHAR U_83DC ENCODING 33756 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 01C0 7E80 2880 1500 FFE0 1500 2480 C460 ENDCHAR STARTCHAR U_83DD ENCODING 33757 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 2240 FFE0 2200 3BC0 E340 2480 2940 D620 ENDCHAR STARTCHAR U_83DE ENCODING 33758 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 7900 11E0 FEA0 10A0 3920 5520 92A0 1440 ENDCHAR STARTCHAR U_83DF ENCODING 33759 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1F00 2200 FFC0 2240 3FC0 0A20 32A0 C1E0 ENDCHAR STARTCHAR U_83E0 ENCODING 33760 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4100 27E0 9520 57C0 2540 E480 2940 3620 ENDCHAR STARTCHAR U_83E1 ENCODING 33761 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 3F80 0200 55A0 4E20 5520 6CE0 4020 7FE0 ENDCHAR STARTCHAR U_83E2 ENCODING 33762 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 2400 F7C0 2840 3740 E540 27A0 2420 63E0 ENDCHAR STARTCHAR U_83E3 ENCODING 33763 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 7FE0 5220 7E20 4540 4540 7C80 5140 7E20 ENDCHAR STARTCHAR U_83E4 ENCODING 33764 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 0800 FFE0 2080 DF60 1100 1240 0FC0 ENDCHAR STARTCHAR U_83E5 ENCODING 33765 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 23C0 FA00 23E0 3240 6A40 A240 2440 2840 ENDCHAR STARTCHAR U_83E6 ENCODING 33766 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 4040 2780 6400 27E0 2900 2900 5100 8FE0 ENDCHAR STARTCHAR U_83E7 ENCODING 33767 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FE0 4080 5F00 5100 5FE0 5100 54A0 9A60 ENDCHAR STARTCHAR U_83E8 ENCODING 33768 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 1100 7FC0 0800 FFE0 1100 0E00 F1E0 ENDCHAR STARTCHAR U_83E9 ENCODING 33769 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 1100 FFE0 0000 3F80 2080 2080 3F80 ENDCHAR STARTCHAR U_83EA ENCODING 33770 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 8020 FFE0 0800 1FC0 3040 DFC0 1040 ENDCHAR STARTCHAR U_83EB ENCODING 33771 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 2480 2480 7FC0 0400 3F80 0400 FFE0 ENDCHAR STARTCHAR U_83EC ENCODING 33772 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 4FE0 2220 9540 5880 27E0 C420 47E0 4420 ENDCHAR STARTCHAR U_83ED ENCODING 33773 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 4200 2440 8FE0 6020 2FC0 C840 4FC0 4840 ENDCHAR STARTCHAR U_83EE ENCODING 33774 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FE0 4440 7FC0 4460 5FC0 4600 4900 B0E0 ENDCHAR STARTCHAR U_83EF ENCODING 33775 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 2480 FFE0 2480 7FC0 0400 FFE0 0400 ENDCHAR STARTCHAR U_83F0 ENCODING 33776 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 F860 17C0 2540 3D40 E540 2520 25A0 E9A0 ENDCHAR STARTCHAR U_83F1 ENCODING 33777 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 0400 FFE0 2880 DF60 2900 0600 F9E0 ENDCHAR STARTCHAR U_83F2 ENCODING 33778 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 0A00 7BC0 0A00 7BC0 0A00 FBE0 0A00 0A00 ENDCHAR STARTCHAR U_83F3 ENCODING 33779 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 0E00 3180 DF60 0400 7FC0 2480 1500 FFE0 ENDCHAR STARTCHAR U_83F4 ENCODING 33780 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 1500 3F80 E4E0 3F80 24A0 3FA0 03E0 ENDCHAR STARTCHAR U_83F5 ENCODING 33781 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 4A40 7FC0 4440 7FC0 5040 5F40 40C0 ENDCHAR STARTCHAR U_83F6 ENCODING 33782 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 0800 7FC0 2480 DF60 0400 7FC0 0400 ENDCHAR STARTCHAR U_83F7 ENCODING 33783 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 3F80 0080 FFE0 8420 BF80 2480 2580 0400 ENDCHAR STARTCHAR U_83F8 ENCODING 33784 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1100 FA80 2440 3920 28C0 4A00 4900 B0C0 ENDCHAR STARTCHAR U_83F9 ENCODING 33785 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 27C0 9440 57C0 2440 27C0 C440 4440 5FE0 ENDCHAR STARTCHAR U_83FA ENCODING 33786 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 3FC0 2040 3FC0 2840 2FC0 2840 4FC0 88C0 ENDCHAR STARTCHAR U_83FB ENCODING 33787 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 1080 FFE0 1080 3980 56C0 94A0 18A0 1080 ENDCHAR STARTCHAR U_83FC ENCODING 33788 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 2440 4A80 1180 6440 14A0 6B00 1100 E0E0 ENDCHAR STARTCHAR U_83FD ENCODING 33789 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 13E0 1D40 1140 FF40 5540 5280 9140 3620 ENDCHAR STARTCHAR U_83FE ENCODING 33790 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 0800 FFE0 2440 C6A0 1540 64A0 0C00 ENDCHAR STARTCHAR U_83FF ENCODING 33791 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 FE20 24A0 7AA0 10A0 7CA0 10A0 1E20 F0E0 ENDCHAR STARTCHAR U_8400 ENCODING 33792 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 4840 7F00 4880 4F80 4900 8920 B0E0 ENDCHAR STARTCHAR U_8401 ENCODING 33793 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 1100 1D00 1700 1100 FFE0 1100 E0E0 ENDCHAR STARTCHAR U_8402 ENCODING 33794 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 7C00 13C0 7E40 1240 3A40 57C0 9240 1000 ENDCHAR STARTCHAR U_8403 ENCODING 33795 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 2100 5280 8C40 0400 FFE0 0400 0400 ENDCHAR STARTCHAR U_8404 ENCODING 33796 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3FE0 5020 BF20 0820 FFA0 4920 7F20 00C0 ENDCHAR STARTCHAR U_8405 ENCODING 33797 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFC0 4480 7F80 0420 03E0 3FC0 2440 3FC0 ENDCHAR STARTCHAR U_8406 ENCODING 33798 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 7FE0 1500 3FC0 2440 3FC0 2440 3FC0 1200 7FE0 0200 ENDCHAR STARTCHAR U_8407 ENCODING 33799 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 1FC0 1000 1F80 1000 FFE0 1280 1500 18E0 ENDCHAR STARTCHAR U_8408 ENCODING 33800 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 3F80 2080 3F80 2080 3F80 0A80 1220 61E0 ENDCHAR STARTCHAR U_8409 ENCODING 33801 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 77C0 5540 7540 5540 77C0 5420 5420 B3E0 ENDCHAR STARTCHAR U_840A ENCODING 33802 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 2480 5540 8E20 1500 2480 4440 8420 ENDCHAR STARTCHAR U_840B ENCODING 33803 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FE0 0480 FFE0 0480 7FE0 1100 0E00 F1E0 ENDCHAR STARTCHAR U_840C ENCODING 33804 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 4A40 7BC0 4A40 7BC0 4A40 0440 08C0 ENDCHAR STARTCHAR U_840D ENCODING 33805 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 5100 2FE0 9920 5540 2540 2FE0 C100 4100 4100 ENDCHAR STARTCHAR U_840E ENCODING 33806 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 3F80 0400 FFE0 2480 FFE0 1100 0E00 F9E0 ENDCHAR STARTCHAR U_840F ENCODING 33807 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 7FE0 0900 0F00 1200 2BC0 6040 3BC0 2040 3FC0 2040 ENDCHAR STARTCHAR U_8410 ENCODING 33808 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 0480 7FE0 0480 3F80 27E0 5400 8FE0 ENDCHAR STARTCHAR U_8411 ENCODING 33809 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2200 3FE0 6200 BFC0 2200 3FC0 2200 3FE0 ENDCHAR STARTCHAR U_8412 ENCODING 33810 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 2100 4880 9240 3F00 1220 2220 C1E0 ENDCHAR STARTCHAR U_8413 ENCODING 33811 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 7FE0 1500 7FE0 4020 5FA0 1080 1E80 1780 1080 7FE0 ENDCHAR STARTCHAR U_8414 ENCODING 33812 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 2000 F7C0 2240 3240 E480 27C0 2440 67C0 ENDCHAR STARTCHAR U_8415 ENCODING 33813 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FE0 1100 0E00 3180 DFE0 1080 1F80 2080 ENDCHAR STARTCHAR U_8416 ENCODING 33814 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3780 2080 3B80 2080 3F80 1200 2220 C1E0 ENDCHAR STARTCHAR U_8417 ENCODING 33815 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 8020 3F80 0000 FFE0 2480 4440 8C20 ENDCHAR STARTCHAR U_8418 ENCODING 33816 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 1100 2E80 C060 7FC0 1500 2480 CC60 ENDCHAR STARTCHAR U_8419 ENCODING 33817 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2100 27E0 FD20 2100 7180 AAA0 22A0 24E0 ENDCHAR STARTCHAR U_841A ENCODING 33818 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 27C0 F440 2380 3D60 E7C0 2100 2FE0 6100 ENDCHAR STARTCHAR U_841B ENCODING 33819 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3F80 3280 2980 3F80 1100 FFE0 1100 2100 ENDCHAR STARTCHAR U_841C ENCODING 33820 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2080 F8E0 A880 ABE0 AA20 B220 23E0 2220 ENDCHAR STARTCHAR U_841D ENCODING 33821 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 4A40 7FC0 1000 3F80 5100 0E00 F800 ENDCHAR STARTCHAR U_841E ENCODING 33822 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 7FC0 4440 4A40 0000 4AC0 7320 4220 71E0 ENDCHAR STARTCHAR U_841F ENCODING 33823 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7A00 2780 FA80 2680 73A0 A2A0 24A0 2860 ENDCHAR STARTCHAR U_8420 ENCODING 33824 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 7BC0 4A40 7BC0 4A40 7BC0 4A40 4A40 9480 ENDCHAR STARTCHAR U_8421 ENCODING 33825 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 4200 27C0 8440 57C0 2440 C440 47C0 4440 ENDCHAR STARTCHAR U_8422 ENCODING 33826 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4400 27C0 0840 6740 1540 6740 24A0 23E0 ENDCHAR STARTCHAR U_8423 ENCODING 33827 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 0200 FFE0 8020 3F80 1200 13C0 2A00 C7E0 ENDCHAR STARTCHAR U_8424 ENCODING 33828 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 8420 7FC0 4440 7FC0 0480 0440 FFE0 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ENDCHAR STARTCHAR U_842C ENCODING 33836 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3F80 2480 3F80 2480 FFC0 8540 9F40 80C0 ENDCHAR STARTCHAR U_842D ENCODING 33837 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1140 7F80 0400 3F80 2480 7FC0 4540 5F40 40C0 ENDCHAR STARTCHAR U_842E ENCODING 33838 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 1A00 2D80 C060 7D40 4540 7D40 4440 4C80 ENDCHAR STARTCHAR U_842F ENCODING 33839 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 1F00 2200 7F80 A080 3F80 2080 3F80 60C0 ENDCHAR STARTCHAR U_8430 ENCODING 33840 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 0400 7FC0 5540 7FC0 1500 2480 C460 ENDCHAR STARTCHAR U_8431 ENCODING 33841 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 8020 7FC0 2080 3F80 2080 3F80 FFE0 ENDCHAR STARTCHAR U_8432 ENCODING 33842 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 7FC0 2480 7FE0 0800 FFE0 2900 4600 B9E0 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ENDCHAR STARTCHAR U_843A ENCODING 33850 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 5F40 4040 7FC0 2080 3F80 2080 3F80 ENDCHAR STARTCHAR U_843B ENCODING 33851 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 1100 FFE0 2080 3F80 2080 3F80 2080 ENDCHAR STARTCHAR U_843C ENCODING 33852 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 4A40 4A40 FFE0 1000 3F80 0080 0700 ENDCHAR STARTCHAR U_843D ENCODING 33853 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4780 2C80 8300 5480 2860 C780 4480 4780 ENDCHAR STARTCHAR U_843E ENCODING 33854 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 0A00 7F80 1AC0 2440 CAC0 0000 7FC0 4A40 FFE0 ENDCHAR STARTCHAR U_843F ENCODING 33855 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 27C0 9100 5FE0 2100 E7C0 4440 47C0 4440 ENDCHAR STARTCHAR U_8440 ENCODING 33856 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 20C0 FF00 2100 37E0 E100 27C0 2440 67C0 ENDCHAR STARTCHAR U_8441 ENCODING 33857 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 0A00 FFE0 0400 7FC0 0400 FFE0 1100 0E00 71C0 ENDCHAR STARTCHAR U_8442 ENCODING 33858 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 7880 53E0 FCA0 54A0 7D20 2AC0 4820 87E0 ENDCHAR STARTCHAR U_8443 ENCODING 33859 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7A00 4BE0 4D00 79E0 4900 49E0 7900 0100 ENDCHAR STARTCHAR U_8444 ENCODING 33860 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7A00 4BE0 7D00 49C0 7900 49E0 4900 9900 ENDCHAR STARTCHAR U_8445 ENCODING 33861 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 27C0 2440 57C0 A440 27C0 5440 8440 0FE0 ENDCHAR STARTCHAR U_8446 ENCODING 33862 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 17C0 2440 27C0 6100 BFE0 2540 2940 3120 ENDCHAR STARTCHAR U_8447 ENCODING 33863 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7F80 0A00 FFE0 1440 2400 FFE0 1500 E4E0 ENDCHAR STARTCHAR U_8448 ENCODING 33864 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2080 7FC0 2080 3F80 0400 FFE0 2480 C460 ENDCHAR STARTCHAR U_8449 ENCODING 33865 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 2900 FFE0 2900 2F00 3FC0 0400 FFE0 1500 E4E0 ENDCHAR STARTCHAR U_844A ENCODING 33866 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 0A00 3F80 D160 1F00 1100 FFE0 1100 2100 ENDCHAR STARTCHAR U_844B ENCODING 33867 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7A00 4BE0 7C20 4BA0 7AA0 4BA0 4820 98C0 ENDCHAR STARTCHAR U_844C ENCODING 33868 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 1500 FFE0 1080 0F00 78C0 2100 FFE0 4A40 3180 CE60 ENDCHAR STARTCHAR U_844D ENCODING 33869 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 3F80 2080 7FC0 4440 7FC0 4440 7FC0 ENDCHAR STARTCHAR U_844E ENCODING 33870 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2FC0 4140 8FE0 2140 6FE0 A100 3FE0 2100 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ENDCHAR STARTCHAR U_8456 ENCODING 33878 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 9120 64C0 0500 FFE0 0A00 3180 C060 ENDCHAR STARTCHAR U_8457 ENCODING 33879 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1540 7F80 0500 FFE0 1F80 3080 DF80 1080 1F80 ENDCHAR STARTCHAR U_8458 ENCODING 33880 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1240 2480 FFE0 1240 7FC0 4440 7FC0 4440 7FC0 ENDCHAR STARTCHAR U_8459 ENCODING 33881 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 13E0 FE20 13E0 3220 5BE0 9620 13E0 1220 ENDCHAR STARTCHAR U_845A ENCODING 33882 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFC0 1100 1F00 1100 FFE0 2900 3080 3FC0 ENDCHAR STARTCHAR U_845B ENCODING 33883 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3F80 2080 3F80 2080 3FE0 6420 AA20 3F60 ENDCHAR STARTCHAR U_845C ENCODING 33884 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 23C0 F940 2140 FA40 2480 FFE0 0A00 F1E0 ENDCHAR STARTCHAR U_845D ENCODING 33885 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FD00 57E0 A920 5520 FD20 2120 3A20 C4C0 ENDCHAR STARTCHAR U_845E ENCODING 33886 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 F7E0 1240 73C0 8240 F3C0 1240 17E0 6040 ENDCHAR STARTCHAR U_845F ENCODING 33887 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 1500 3F80 2080 3F80 2080 7FC0 0400 7FC0 0400 FFE0 ENDCHAR STARTCHAR U_8460 ENCODING 33888 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2FC0 4040 4FC0 C040 5FE0 54A0 4300 5CE0 ENDCHAR STARTCHAR U_8461 ENCODING 33889 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3FE0 4A20 BFA0 2920 3F20 2920 3F20 2940 ENDCHAR STARTCHAR U_8462 ENCODING 33890 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 0A00 3580 C260 3F80 2A80 2A80 FFE0 ENDCHAR STARTCHAR U_8463 ENCODING 33891 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 1100 3F80 0400 FFE0 2480 3F80 2480 7FC0 0400 FFE0 ENDCHAR STARTCHAR U_8464 ENCODING 33892 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 2940 4040 F7E0 2840 FA40 0140 A840 A940 8080 ENDCHAR STARTCHAR U_8465 ENCODING 33893 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 4440 7D40 4540 7D40 4540 5440 49C0 ENDCHAR STARTCHAR U_8466 ENCODING 33894 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 3F80 0880 FFE0 1080 3FC0 2200 7FE0 0200 ENDCHAR STARTCHAR U_8467 ENCODING 33895 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7D00 13E0 FD20 8D20 1120 FD20 12A0 7440 ENDCHAR STARTCHAR U_8468 ENCODING 33896 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3F80 2480 3F80 2480 FFE0 2280 2900 70E0 ENDCHAR STARTCHAR U_8469 ENCODING 33897 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 4000 F7C0 9540 9540 F7C0 9420 F420 03E0 ENDCHAR STARTCHAR U_846A ENCODING 33898 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0A00 FFE0 2A00 3C40 4940 FD40 5540 7D40 5540 7C40 94C0 ENDCHAR STARTCHAR U_846B ENCODING 33899 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 23C0 FA40 23C0 7A40 4BC0 7A40 0440 08C0 ENDCHAR STARTCHAR U_846C ENCODING 33900 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 2A80 D320 21E0 5100 FFE0 1100 E100 ENDCHAR STARTCHAR U_846D ENCODING 33901 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 4840 7BC0 4000 7BC0 4240 7980 4660 ENDCHAR STARTCHAR U_846E ENCODING 33902 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7B80 4280 74E0 4000 7FC0 4280 F900 4EE0 ENDCHAR STARTCHAR U_846F ENCODING 33903 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4200 93E0 E420 4920 F4A0 5020 A920 A8C0 ENDCHAR STARTCHAR U_8470 ENCODING 33904 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 2840 3FA0 6480 AA40 37A0 2C80 2300 3CE0 ENDCHAR STARTCHAR U_8471 ENCODING 33905 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 5100 7FC0 9240 1C40 6640 1B80 4A40 48A0 87A0 ENDCHAR STARTCHAR U_8472 ENCODING 33906 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 0800 3F80 2480 3F80 0440 7580 2480 CC60 ENDCHAR STARTCHAR U_8473 ENCODING 33907 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1140 7FE0 4100 7F20 4940 7F40 5580 4CA0 B360 ENDCHAR STARTCHAR U_8474 ENCODING 33908 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1140 7FE0 4100 5D20 4140 5D80 5520 5EA0 8460 ENDCHAR STARTCHAR U_8475 ENCODING 33909 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FE80 5340 2180 5E80 8460 7F80 0A00 F1E0 ENDCHAR STARTCHAR U_8476 ENCODING 33910 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 FFE0 2080 FFE0 8020 3F80 0400 1400 0800 ENDCHAR STARTCHAR U_8477 ENCODING 33911 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 8420 FFE0 2480 3F80 2480 FFE0 0400 ENDCHAR STARTCHAR U_8478 ENCODING 33912 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 4440 7FC0 4440 7FC0 1440 52A0 8FA0 ENDCHAR STARTCHAR U_8479 ENCODING 33913 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 2900 7BE0 2480 3AE0 2BA0 2EE0 2A80 4A20 B1E0 ENDCHAR STARTCHAR U_847A ENCODING 33914 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 7FE0 0900 1F80 1080 7FE0 1080 1F80 1080 7FC0 0080 ENDCHAR STARTCHAR U_847B ENCODING 33915 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FC0 4440 5F40 5540 5F40 4540 5FA0 80A0 ENDCHAR STARTCHAR U_847C ENCODING 33916 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4E40 5140 7FC0 2880 DF60 2900 4600 39C0 ENDCHAR STARTCHAR U_847D ENCODING 33917 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 4A40 7FC0 0800 FFE0 1100 0E00 F1E0 ENDCHAR STARTCHAR U_847E ENCODING 33918 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 3BC0 4A40 AAC0 1220 E1E0 5440 52A0 8FA0 ENDCHAR STARTCHAR U_847F ENCODING 33919 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 7FE0 0900 3FC0 2240 3FC0 2940 2A40 2CC0 4940 8FC0 ENDCHAR STARTCHAR U_8480 ENCODING 33920 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 1F80 1080 1F80 1080 3FC0 2940 2940 FFE0 ENDCHAR STARTCHAR U_8481 ENCODING 33921 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4240 3FE0 E700 2A80 3240 2220 5200 8FE0 ENDCHAR STARTCHAR U_8482 ENCODING 33922 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 7FC0 1100 FFE0 8420 3F80 2480 2580 0400 ENDCHAR STARTCHAR U_8483 ENCODING 33923 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 0F80 1100 FFE0 1480 6B00 1680 0A60 3600 ENDCHAR STARTCHAR U_8484 ENCODING 33924 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 80A0 7BC0 0480 FA80 2A80 4920 87E0 ENDCHAR STARTCHAR U_8485 ENCODING 33925 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 2900 4200 1780 62A0 2460 7FC0 0E00 3580 C460 ENDCHAR STARTCHAR U_8486 ENCODING 33926 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0900 77C0 2540 F860 0400 FFE0 0900 0600 F9E0 ENDCHAR STARTCHAR U_8487 ENCODING 33927 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 0940 7FE0 4100 5F20 5120 5540 54A0 4B60 B220 ENDCHAR STARTCHAR U_8488 ENCODING 33928 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 5240 7B80 4220 71E0 3F80 2080 3F80 2080 3F80 ENDCHAR STARTCHAR U_8489 ENCODING 33929 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 3F80 2480 FFE0 2080 2480 2480 0A00 F1E0 ENDCHAR STARTCHAR U_848A ENCODING 33930 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1200 FFC0 1200 32C0 6700 BA20 21E0 0200 7B80 4A20 79E0 ENDCHAR STARTCHAR U_848B ENCODING 33931 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 27C0 AC80 6300 2480 7FE0 A480 2280 2180 ENDCHAR STARTCHAR U_848C ENCODING 33932 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 5140 2480 FFE0 2480 4C40 FFE0 1100 0E00 F1E0 ENDCHAR STARTCHAR U_848D ENCODING 33933 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 5500 2800 FF80 0900 0FC0 1080 7FE0 9520 2AE0 ENDCHAR STARTCHAR U_848E ENCODING 33934 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 0900 FFE0 4900 2FC0 8840 4B80 2AA0 2AC0 CA80 4B40 5620 ENDCHAR STARTCHAR U_848F ENCODING 33935 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 FFE0 8A20 7FC0 4A40 5340 7FC0 4040 7FC0 ENDCHAR STARTCHAR U_8490 ENCODING 33936 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 3FC0 2440 3FC0 2440 3FC0 0B60 12A0 E1E0 ENDCHAR STARTCHAR U_8491 ENCODING 33937 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 4A40 7C20 4BC0 7D40 4540 4480 9B60 ENDCHAR STARTCHAR U_8492 ENCODING 33938 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 2100 77E0 5100 77C0 4540 7540 5540 7540 0100 ENDCHAR STARTCHAR U_8493 ENCODING 33939 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1200 FFE0 1200 2100 57C0 7100 2D40 7FC0 0100 A920 A8E0 ENDCHAR STARTCHAR U_8494 ENCODING 33940 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 F7C0 9100 9FE0 F080 9FE0 9480 F280 0100 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ENDCHAR STARTCHAR U_849C ENCODING 33948 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7BC0 0000 FBE0 2080 72C0 AAA0 24A0 6180 ENDCHAR STARTCHAR U_849D ENCODING 33949 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 7FE0 5040 5FC0 5040 5FC0 4A80 9240 A620 ENDCHAR STARTCHAR U_849E ENCODING 33950 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 4480 2FE0 A800 7A40 2940 C940 4880 4FE0 ENDCHAR STARTCHAR U_849F ENCODING 33951 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 2200 FBE0 0420 53A0 52A0 2BA0 F020 00C0 ENDCHAR STARTCHAR U_84A0 ENCODING 33952 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1500 3F80 2080 3F80 2080 3F80 5440 52A0 8FA0 ENDCHAR STARTCHAR U_84A1 ENCODING 33953 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 1500 7FE0 0900 FFE0 8420 FFE0 0800 1FC0 2040 C380 ENDCHAR STARTCHAR U_84A2 ENCODING 33954 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1100 FFE0 1100 F100 9280 AFE0 9100 DFE0 A540 8920 9320 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ENDCHAR STARTCHAR U_96D9 ENCODING 38617 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2A80 3FE0 6A80 BFC0 2A80 3FE0 0000 3FC0 0880 0700 78E0 ENDCHAR STARTCHAR U_96DA ENCODING 38618 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP FFE0 0900 7BC0 4A40 7BC0 2200 3FE0 6200 BFC0 2200 3FE0 ENDCHAR STARTCHAR U_96DB ENCODING 38619 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 4100 FA80 ABE0 FE80 2A80 CBE0 7A80 ABE0 FA80 2BE0 D200 ENDCHAR STARTCHAR U_96DC ENCODING 38620 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 2100 FE80 4BE0 4A80 B7E0 1280 FE80 13E0 3A80 5680 93E0 ENDCHAR STARTCHAR U_96DD ENCODING 38621 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 5580 AA80 57E0 FE80 8BE0 FA80 AA80 ABE0 FA80 87E0 7E00 ENDCHAR STARTCHAR U_96DE ENCODING 38622 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 1980 EA80 A7E0 5280 23E0 CA80 7280 23E0 FA80 5280 8BE0 ENDCHAR STARTCHAR U_96DF ENCODING 38623 SWIDTH 1000 0 DWIDTH 12 0 BBX 11 11 0 -1 BITMAP 4220 7FE0 1200 3FC0 6200 BFC0 2200 7FE0 59A0 6F60 4060 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BITMAP 2080 1140 1080 1800 EF80 4200 4000 4000 9000 8F00 ENDCHAR STARTCHAR U_F717 ENCODING 63255 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 20 2C 38 C0 4C 72 C2 02 04 18 ENDCHAR STARTCHAR U_F718 ENCODING 63256 SWIDTH 0 0 DWIDTH 12 0 BBX 9 12 2 -1 BITMAP 0100 0080 1000 1400 E800 2000 2E00 7100 0100 0100 0600 3800 ENDCHAR STARTCHAR U_F719 ENCODING 63257 SWIDTH 0 0 DWIDTH 12 0 BBX 8 6 2 2 BITMAP 0E 71 81 01 02 0C ENDCHAR STARTCHAR U_F71A ENCODING 63258 SWIDTH 0 0 DWIDTH 12 0 BBX 10 7 1 1 BITMAP 0F80 B040 4040 0040 0040 0080 0700 ENDCHAR STARTCHAR U_F71B ENCODING 63259 SWIDTH 0 0 DWIDTH 12 0 BBX 11 10 1 0 BITMAP 0020 0040 0720 1880 E040 0040 0040 0080 0300 0400 ENDCHAR STARTCHAR U_F71C ENCODING 63260 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 1F80 E400 0800 1000 1000 1000 1800 0E00 ENDCHAR STARTCHAR U_F71D ENCODING 63261 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 1F80 E480 0900 1080 1000 1000 1800 0E00 ENDCHAR STARTCHAR U_F71E ENCODING 63262 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 40 20 20 20 2E 30 C0 80 80 7E ENDCHAR STARTCHAR U_F71F ENCODING 63263 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0100 2280 2100 2000 2600 3800 4000 8000 8000 7E00 ENDCHAR STARTCHAR U_F720 ENCODING 63264 SWIDTH 0 0 DWIDTH 12 0 BBX 8 10 2 0 BITMAP 10 10 78 21 26 44 44 9C 27 1C ENDCHAR STARTCHAR U_F721 ENCODING 63265 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 4000 4E00 8000 8000 8000 C000 9000 8F80 ENDCHAR STARTCHAR U_F722 ENCODING 63266 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 8800 4E00 7900 5080 5080 A080 B780 C780 ENDCHAR STARTCHAR U_F723 ENCODING 63267 SWIDTH 0 0 DWIDTH 12 0 BBX 10 10 2 0 BITMAP 2000 2000 3300 FC80 3080 2080 6080 AF80 A980 2640 ENDCHAR STARTCHAR U_F724 ENCODING 63268 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 3F00 4880 9080 9080 9080 A080 4100 0600 ENDCHAR STARTCHAR U_F725 ENCODING 63269 SWIDTH 0 0 DWIDTH 12 0 BBX 9 9 2 0 BITMAP 4200 4280 4F00 8200 8200 C200 8F00 9280 8C00 ENDCHAR STARTCHAR U_F726 ENCODING 63270 SWIDTH 0 0 DWIDTH 12 0 BBX 10 11 1 0 BITMAP 0080 0040 4200 4200 4380 8E00 8200 8200 CE00 9380 0E00 ENDCHAR STARTCHAR U_F727 ENCODING 63271 SWIDTH 0 0 DWIDTH 12 0 BBX 11 11 1 0 BITMAP 0040 00A0 42C0 4200 4380 8E00 8200 8200 CE00 9380 8E00 ENDCHAR STARTCHAR U_F728 ENCODING 63272 SWIDTH 0 0 DWIDTH 12 0 BBX 10 9 2 1 BITMAP 1300 F100 2100 4180 4140 4100 4200 6200 3C00 ENDCHAR STARTCHAR U_F729 ENCODING 63273 SWIDTH 0 0 DWIDTH 12 0 BBX 11 11 1 0 BITMAP 0040 00A0 3240 D100 2100 4180 4140 4100 4200 6200 3C00 ENDCHAR STARTCHAR U_F72A ENCODING 63274 SWIDTH 0 0 DWIDTH 12 0 BBX 11 10 1 0 BITMAP 00C0 10A0 F340 2100 4180 4140 4100 4200 6200 3C00 ENDCHAR STARTCHAR U_F72B ENCODING 63275 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 0800 0400 1800 1000 0F00 3480 C480 BC00 ENDCHAR STARTCHAR U_F72C ENCODING 63276 SWIDTH 0 0 DWIDTH 12 0 BBX 11 10 1 0 BITMAP 0080 0960 0CA0 1000 1000 0E00 3980 C480 C580 3C00 ENDCHAR STARTCHAR U_F72D ENCODING 63277 SWIDTH 0 0 DWIDTH 12 0 BBX 10 9 1 0 BITMAP 0880 0D40 10C0 1000 0F00 3880 C480 C500 3C00 ENDCHAR STARTCHAR U_F72E ENCODING 63278 SWIDTH 0 0 DWIDTH 12 0 BBX 10 6 1 2 BITMAP 1800 2400 4200 C100 0080 0040 ENDCHAR STARTCHAR U_F72F ENCODING 63279 SWIDTH 0 0 DWIDTH 12 0 BBX 10 8 1 2 BITMAP 0180 0140 1880 2400 4200 C100 0080 0040 ENDCHAR STARTCHAR U_F730 ENCODING 63280 SWIDTH 0 0 DWIDTH 12 0 BBX 10 8 2 1 BITMAP 0180 0280 1100 6800 4400 8200 0180 00C0 ENDCHAR STARTCHAR U_F731 ENCODING 63281 SWIDTH 0 0 DWIDTH 12 0 BBX 9 8 2 1 BITMAP 4F00 4200 8F80 8200 8200 CE00 9380 9E00 ENDCHAR STARTCHAR U_F732 ENCODING 63282 SWIDTH 0 0 DWIDTH 12 0 BBX 11 8 1 1 BITMAP 4FE0 4240 8F80 8200 8200 CE00 9380 9E40 ENDCHAR STARTCHAR U_F733 ENCODING 63283 SWIDTH 0 0 DWIDTH 12 0 BBX 11 10 1 1 BITMAP 0020 0040 4F60 4200 9F80 8200 8200 CE00 9380 8C00 ENDCHAR STARTCHAR U_F734 ENCODING 63284 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 10 10 16 F8 14 78 10 78 96 60 ENDCHAR STARTCHAR U_F735 ENCODING 63285 SWIDTH 0 0 DWIDTH 12 0 BBX 10 10 2 0 BITMAP 0400 3C00 0800 0900 1100 7D00 A300 C2C0 8400 1800 ENDCHAR STARTCHAR U_F736 ENCODING 63286 SWIDTH 0 0 DWIDTH 12 0 BBX 10 10 1 0 BITMAP 2000 1000 9880 6140 31C0 E100 6100 6100 4100 3E00 ENDCHAR STARTCHAR U_F737 ENCODING 63287 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0400 4400 4E00 7900 4880 B080 B080 B080 C100 0E00 ENDCHAR STARTCHAR U_F738 ENCODING 63288 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 10 10 20 78 A0 C0 78 42 42 3C ENDCHAR STARTCHAR U_F739 ENCODING 63289 SWIDTH 0 0 DWIDTH 12 0 BBX 8 6 3 2 BITMAP 7E 21 EE 10 10 10 ENDCHAR STARTCHAR U_F73A ENCODING 63290 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0800 6B00 5C80 3080 E880 1700 1000 0800 0800 0800 ENDCHAR STARTCHAR U_F73B ENCODING 63291 SWIDTH 0 0 DWIDTH 12 0 BBX 8 8 2 1 BITMAP 18 5E 96 B5 D5 56 0C 10 ENDCHAR STARTCHAR U_F73C ENCODING 63292 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0C00 5200 5F00 B280 D280 D280 D280 4F00 0800 1000 ENDCHAR STARTCHAR U_F73D ENCODING 63293 SWIDTH 0 0 DWIDTH 12 0 BBX 6 8 3 1 BITMAP 20 10 1C 10 10 78 94 60 ENDCHAR STARTCHAR U_F73E ENCODING 63294 SWIDTH 0 0 DWIDTH 12 0 BBX 8 10 2 0 BITMAP 08 08 08 0E 08 08 08 7E 8B 78 ENDCHAR STARTCHAR U_F73F ENCODING 63295 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 38 38 40 40 9C A2 C2 02 04 78 ENDCHAR STARTCHAR U_F740 ENCODING 63296 SWIDTH 0 0 DWIDTH 12 0 BBX 6 10 3 0 BITMAP 40 58 64 C4 C4 C4 C4 44 08 10 ENDCHAR STARTCHAR U_F741 ENCODING 63297 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 08 78 10 20 5C E2 82 32 4C 38 ENDCHAR STARTCHAR U_F742 ENCODING 63298 SWIDTH 0 0 DWIDTH 12 0 BBX 10 10 2 0 BITMAP 2000 4000 5000 7600 FA00 4200 4200 C240 4380 4000 ENDCHAR STARTCHAR U_F743 ENCODING 63299 SWIDTH 0 0 DWIDTH 12 0 BBX 8 10 2 0 BITMAP 04 3C 08 10 2E 71 C1 81 02 0C ENDCHAR STARTCHAR U_F744 ENCODING 63300 SWIDTH 0 0 DWIDTH 12 0 BBX 7 7 3 1 BITMAP 20 20 FC 22 62 E2 2C ENDCHAR STARTCHAR U_F745 ENCODING 63301 SWIDTH 0 0 DWIDTH 12 0 BBX 9 11 2 -1 BITMAP 2000 2000 2000 3600 F980 2080 6080 A080 A100 6300 2C00 ENDCHAR STARTCHAR U_F746 ENCODING 63302 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0C00 3800 0800 1600 1980 6080 A080 A480 CB00 4600 ENDCHAR STARTCHAR U_F747 ENCODING 63303 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0400 3C00 1E00 3100 5900 2A00 1C00 3700 C880 8980 ENDCHAR STARTCHAR U_F748 ENCODING 63304 SWIDTH 0 0 DWIDTH 12 0 BBX 8 10 3 0 BITMAP 10 2C F0 40 79 8E 98 68 40 3E ENDCHAR STARTCHAR U_F749 ENCODING 63305 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 1000 0800 1000 1000 2000 5C00 6400 4480 8480 8700 ENDCHAR STARTCHAR U_F74A ENCODING 63306 SWIDTH 0 0 DWIDTH 12 0 BBX 5 5 4 3 BITMAP F8 30 20 40 40 ENDCHAR STARTCHAR U_F74B ENCODING 63307 SWIDTH 0 0 DWIDTH 12 0 BBX 8 9 2 0 BITMAP 9F 61 0E 08 08 10 10 20 40 ENDCHAR STARTCHAR U_F74C ENCODING 63308 SWIDTH 0 0 DWIDTH 12 0 BBX 4 6 4 2 BITMAP 10 20 60 A0 20 20 ENDCHAR STARTCHAR U_F74D ENCODING 63309 SWIDTH 0 0 DWIDTH 12 0 BBX 5 10 3 0 BITMAP 08 08 10 30 30 D0 10 10 10 10 ENDCHAR STARTCHAR U_F74E ENCODING 63310 SWIDTH 0 0 DWIDTH 12 0 BBX 5 7 4 1 BITMAP 20 F8 88 90 10 20 40 ENDCHAR STARTCHAR U_F74F ENCODING 63311 SWIDTH 0 0 DWIDTH 12 0 BBX 7 10 3 0 BITMAP 10 10 1E E2 82 84 04 08 10 20 ENDCHAR STARTCHAR U_F750 ENCODING 63312 SWIDTH 0 0 DWIDTH 12 0 BBX 7 5 3 3 BITMAP 0C 30 10 10 FE ENDCHAR STARTCHAR U_F751 ENCODING 63313 SWIDTH 0 0 DWIDTH 12 0 BBX 9 6 2 2 BITMAP 7F00 0800 0800 0800 0800 FF80 ENDCHAR STARTCHAR U_F752 ENCODING 63314 SWIDTH 0 0 DWIDTH 12 0 BBX 7 6 2 2 BITMAP 08 7E 08 18 28 D8 ENDCHAR STARTCHAR U_F753 ENCODING 63315 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0800 0400 0400 7F80 0C00 1400 2400 4400 8C00 0400 ENDCHAR STARTCHAR U_F754 ENCODING 63316 SWIDTH 0 0 DWIDTH 12 0 BBX 6 8 4 1 BITMAP 10 20 FC 24 24 44 48 88 ENDCHAR STARTCHAR U_F755 ENCODING 63317 SWIDTH 0 0 DWIDTH 12 0 BBX 8 9 3 1 BITMAP 03 12 20 FC 24 24 44 48 88 ENDCHAR STARTCHAR U_F756 ENCODING 63318 SWIDTH 0 0 DWIDTH 12 0 BBX 9 9 2 1 BITMAP 1000 0800 0F00 7800 0F80 F800 0800 0400 0400 ENDCHAR STARTCHAR U_F757 ENCODING 63319 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 2380 1000 1600 F800 1000 1F00 E800 0800 0800 0800 ENDCHAR STARTCHAR U_F758 ENCODING 63320 SWIDTH 0 0 DWIDTH 12 0 BBX 7 9 3 0 BITMAP 10 12 3E 44 04 08 10 20 C0 ENDCHAR STARTCHAR U_F759 ENCODING 63321 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 0080 0180 1200 3E00 4400 0400 0800 1800 2000 C000 ENDCHAR STARTCHAR U_F75A ENCODING 63322 SWIDTH 0 0 DWIDTH 12 0 BBX 8 8 3 1 BITMAP 20 7F 88 88 10 10 20 40 ENDCHAR STARTCHAR U_F75B ENCODING 63323 SWIDTH 0 0 DWIDTH 12 0 BBX 8 11 3 0 BITMAP 02 05 22 20 7F 88 88 10 10 20 40 ENDCHAR STARTCHAR U_F75C ENCODING 63324 SWIDTH 0 0 DWIDTH 12 0 BBX 7 6 3 2 BITMAP FE 02 02 04 04 FE ENDCHAR STARTCHAR U_F75D ENCODING 63325 SWIDTH 0 0 DWIDTH 12 0 BBX 9 9 2 2 BITMAP 0080 0100 0080 FF00 0200 0200 0200 0200 FE00 ENDCHAR STARTCHAR U_F75E ENCODING 63326 SWIDTH 0 0 DWIDTH 12 0 BBX 9 9 2 1 BITMAP 0400 2400 2400 FF80 2400 2400 0400 0800 1000 ENDCHAR STARTCHAR U_F75F ENCODING 63327 SWIDTH 0 0 DWIDTH 12 0 BBX 9 11 2 0 BITMAP 0100 0A80 2500 2400 3F00 E400 2400 2400 0800 0800 1000 ENDCHAR STARTCHAR U_F760 ENCODING 63328 SWIDTH 0 0 DWIDTH 12 0 BBX 8 8 2 1 BITMAP 20 00 C1 01 02 04 18 60 ENDCHAR STARTCHAR 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STARTCHAR U_F772 ENCODING 63346 SWIDTH 0 0 DWIDTH 12 0 BBX 5 10 4 0 BITMAP 08 90 88 80 E0 90 80 80 80 80 ENDCHAR STARTCHAR U_F773 ENCODING 63347 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 2 0 BITMAP 1000 0800 0800 FF80 0800 0800 1000 1000 2000 4000 ENDCHAR STARTCHAR U_F774 ENCODING 63348 SWIDTH 0 0 DWIDTH 12 0 BBX 9 6 2 2 BITMAP 4E00 3000 0000 0000 0000 FF80 ENDCHAR STARTCHAR U_F775 ENCODING 63349 SWIDTH 0 0 DWIDTH 12 0 BBX 6 8 4 1 BITMAP 0C 7C 08 48 30 28 44 80 ENDCHAR STARTCHAR U_F776 ENCODING 63350 SWIDTH 0 0 DWIDTH 12 0 BBX 8 10 2 0 BITMAP 18 00 5E 24 08 1A 29 C9 08 08 ENDCHAR STARTCHAR U_F777 ENCODING 63351 SWIDTH 0 0 DWIDTH 12 0 BBX 6 8 4 1 BITMAP 08 04 08 08 10 30 60 80 ENDCHAR STARTCHAR U_F778 ENCODING 63352 SWIDTH 0 0 DWIDTH 12 0 BBX 10 6 2 2 BITMAP 1200 1100 2080 2040 4040 8000 ENDCHAR STARTCHAR U_F779 ENCODING 63353 SWIDTH 0 0 DWIDTH 12 0 BBX 10 8 1 2 BITMAP 00C0 0080 1200 1100 2080 2040 4040 8000 ENDCHAR STARTCHAR U_F77A ENCODING 63354 SWIDTH 0 0 DWIDTH 12 0 BBX 10 8 2 2 BITMAP 0080 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80 80 ENDCHAR STARTCHAR U_FF5D ENCODING 65373 SWIDTH 0 0 DWIDTH 12 0 BBX 3 12 2 -1 BITMAP 80 40 40 40 40 20 40 40 40 40 40 80 ENDCHAR STARTCHAR U_FF5E ENCODING 65374 SWIDTH 0 0 DWIDTH 12 0 BBX 12 3 0 3 BITMAP 1C00 6310 80E0 ENDCHAR STARTCHAR U_FFE0 ENCODING 65504 SWIDTH 0 0 DWIDTH 12 0 BBX 7 9 2 0 BITMAP 04 3C 4A 88 90 90 A2 64 58 ENDCHAR STARTCHAR U_FFE1 ENCODING 65505 SWIDTH 0 0 DWIDTH 12 0 BBX 10 10 1 0 BITMAP 0600 0900 0800 0800 0800 FE00 0800 7040 9C80 6300 ENDCHAR STARTCHAR U_FFE3 ENCODING 65507 SWIDTH 0 0 DWIDTH 12 0 BBX 12 1 0 10 BITMAP FFF0 ENDCHAR STARTCHAR U_FFE5 ENCODING 65509 SWIDTH 0 0 DWIDTH 12 0 BBX 9 10 1 0 BITMAP E380 4100 2200 7F00 1400 7F00 0800 0800 0800 1C00 ENDCHAR ENDFONT ================================================ FILE: scripts/IronOS-mkdocs.yml ================================================ # Project info site_name: IronOS site_url: https://ralim.github.io/IronOS/ site_description: "IronOS Open Source Soldering Iron firmware for Miniware and Pinecil" # Repo config repo_url: https://github.com/ralim/IronOS/ # Dir & location config docs_dir: ../Documentation edit_uri: edit/dev/Documentation/ # Theme and config theme: name: readthedocs highlightsjs: true hljs_languages: - yaml # Navigation structure nav: - Home: index.md - Getting Started: GettingStarted.md - Flashing the firmware: - MHP30: Flashing/MHP30.md - Pinecil V1: Flashing/Pinecil V1.md - Pinecil V2: Flashing/Pinecil V2.md - TS80(P): Flashing/TS80(P).md - TS100: Flashing/TS100.md - Operation: - Main Menu: Menu.md - Settings: Settings.md - Debug Menu: DebugMenu.md - Power: Power.md - Temperature: Temperature.md - Startup Logo: Logo.md - Hardware: - Bluetooth (Pinecil V2): Bluetooth.md - Debugging USB-PD: DebuggingPD.md - Hall Sensor (Pinecil): HallSensor.md - Hardware Notes: Hardware.md - Known Hardware Issues: HardwareIssues.md - New Hardware Requirements: PortingToNewDevice.md - Power sources: PowerSources.md - Troubleshooting: Troubleshooting.md - WS2812B RGB Modding (Pinecil V2): WS2812BModding.md - Translations: Translation.md - Development: Development.md - Changelog: History.md # Plugins plugins: - search - autolinks - awesome-pages - git-revision-date # Markdown Extensions markdown_extensions: - attr_list - pymdownx.emoji: emoji_index: !!python/name:pymdownx.emoji.twemoji emoji_generator: !!python/name:pymdownx.emoji.to_svg ================================================ FILE: scripts/IronOS.Dockerfile ================================================ # Default Reference Distro for development env & deploy: # * Alpine Linux, version 3.21 * FROM alpine:3.22 LABEL maintainer="Ben V. Brown " # Default current dir when container starts WORKDIR /build/ironos # Installing the two compilers (ARM & RISCV), python3 & pip, clang tools, etc.: ## - compilers: gcc-*, newlib-* ## - python3: py*, black (required to check Python code formatting) ## - misc: findutils, make, git, diffutils, zip ## - musl-dev (required for the multi lang firmwares) ## - clang (required for clang-format to check C++ code formatting) ## - shellcheck (to check sh scripts) ARG APK_COMPS="gcc-riscv-none-elf g++-riscv-none-elf gcc-arm-none-eabi g++-arm-none-eabi newlib-riscv-none-elf newlib-arm-none-eabi" ARG APK_PYTHON="python3 py3-pip black" ARG APK_MISC="findutils make git diffutils zip" ARG APK_DEV="musl-dev clang bash clang-extra-tools shellcheck" # PIP packages to check & test Python code, and generate docs ARG PIP_PKGS='bdflib flake8 pymdown-extensions mkdocs mkdocs-autolinks-plugin mkdocs-awesome-pages-plugin mkdocs-git-revision-date-plugin' # Install system packages using alpine package manager RUN apk add --no-cache ${APK_COMPS} ${APK_PYTHON} ${APK_MISC} ${APK_DEV} # Install Python3 packages as modules using pip, yes we dont care if packages break RUN python3 -m pip install --break-system-packages ${PIP_PKGS} # Git trust to avoid related warning RUN git config --global --add safe.directory /build/ironos # Copy the whole source tree working dir into container COPY . /build/ironos ================================================ FILE: scripts/LICENSE_RELEASE.md ================================================ This document outlines the license of IronOS and its dependencies. - IronOS: GPL-3.0-only - FreeRTOS Kernel: MIT - FUSB302 driver: Apache-2.0 - CMSIS + STM32F1xx HAL driver: BSD-3-Clause - NMSIS: Apache-2.0 - GD32VF103 board files: BSD-3-Clause - WenQuanYi Bitmap Song font: GPL-2.0-or-later - BriefLZ compression library: Zlib The source code of IronOS can be obtained on the [IronOS GitHub repo][gh]. [gh]: https://github.com/Ralim/IronOS IronOS --- Copyright (c) 2016-2020 Ben V. Brown and contributors For the license text, see `LICENSE` file. FreeRTOS Kernel --- ``` Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in al copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITN FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS O COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHE IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ``` FUSB302 driver --- ``` PD Buddy Firmware Library - USB Power Delivery for everyone Copyright 2017-2018 Clayton G. Hobbs Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. ``` CMSIS + STM32F1xx HAL driver --- * Only applies to TS100, TS80 and TS80P releases. ``` COPYRIGHT(c) 2017 STMicroelectronics Redistribution and use in source and binary forms, with or without dification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ``` NMSIS --- * Only applies to Pinecil releases. ``` Copyright (c) 2019 Nuclei Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 Licensed under the Apache License, Version 2.0 (the License); you may not use this file except in compliance with the License. You may obtain a copy of the License at www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an AS IS BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. ``` GD32VF103 board files --- * Only applies to Pinecil releases. ``` Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ``` WenQuanYi Bitmap Song font --- * Only applies to CJK (Chinese, Japanese and Korean) language releases. ``` Copyright (c) 2004-2010, The WenQuanYi Project Board of Trustees and Qianqian Fang This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ``` BriefLZ compression library --- * Only applies to multi-language builds. ``` The zlib License (Zlib) Copyright (c) 2002-2020 Joergen Ibsen This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: 1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. 2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. 3. This notice may not be removed or altered from any source distribution. ``` ================================================ FILE: scripts/deploy.sh ================================================ #!/usr/bin/env bash # little helper for docker deployment to: # - start development environment for IronOS ("shell" sub-command) # - generate full set of builds ("build" sub-command) # - probably doing some other routines (check source briefly before running undocumented commands!) #set -x #set -e ### helper functions # brief help (some supported commands may be missing!) usage() { echo -e "\nUsage: ${0} [CMD]\n" echo "CMD (docker related):" echo -e "\tshell - start docker container with shell inside to work on IronOS with all tools needed" echo -e "\tbuild - compile builds of IronOS inside docker container for supported hardware" echo -e "\tclean - delete created docker image for IronOS & its build cache objects\n" echo "CMD (helper routines):" echo -e "\tdocs - high level target to run docs_readme and docs_history (see below)\n" echo -e "\tdocs_readme - generate & OVERWRITE(!) README.md inside Documentation/ based on nav section from mkdocs.yml if it changed\n" echo -e "\tdocs_history - check if History.md has the changelog for the latest stable release\n" echo -e "\tcheck_style_file SRC - run code style checks based on clang-format & custom parsers for source code file SRC\n" echo -e "\tcheck_style_log - run clang-format using source/Makefile and generate gcc-compatible error log in source/check-style.log\n" echo -e "STORAGE NOTICE: for \"shell\" and \"build\" commands extra files will be downloaded so make sure that you have ~5GB of free space.\n" } # Documentation/README.md automagical generation routine docs_readme() { # WARNING: ON RUN Documentaion/README.md MAY BE OVERWRITTEN WITHOUT ANY WARNINGS / CONFIRMATIONS !!! # Returns: ## 0 to the environment & silence - if there are no any changes in README.md nor updates in mkdocs.yml ## 1 to the environment (as error) & note message - if the update of README.md in repo is required yml="scripts/IronOS-mkdocs.yml" md_old="Documentation/README.md" md_new="Documentation/README" # ^^^^ hardcoded paths relative to IronOS/ to make this func very trivial # file overwritten section looks out of style but hoping to make shellcheck happy cat << EOF > "${md_new}" #### This is autogenerated README for brief navigation through github over official documentation for IronOS project #### This documentation is also available [here online](https://ralim.github.io/IronOS) EOF # it probably will become unexplainable in a few months but so far it works: sed '1,/^nav/d; /^ *$/,$d; s,- ,- [,; s,: ,](../Documentation/,; s,.md,.md),; s,:$,],; s,/Pinecil ,/Pinecil%20,; /^ - \[.*\]$/ s,\[,,; s,]$,,' "${yml}" >> "${md_new}" ret=0 if [ -z "$(diff -q "${md_old}" "${md_new}")" ]; then rm "${md_new}" ret=0 else mv "${md_new}" "${md_old}" echo "" echo "${yml} seems to be updated..." echo "... while ${md_old} is out-of-date!" echo "" echo "Please, update ${md_old} in your local working copy by command:" echo "" echo " $ ./scripts/deploy.sh docs_readme" echo "" echo "And then commit & push changes to update ${md_old} in the repo:" echo "" echo " $ git commit ${md_old} -m \"${md_old}: update autogenerated file\" && git push" echo "" ret=1 fi; return "${ret}" } # Documentation/History.md automagical changelog routine docs_history() { md="Documentation/History.md" ver_md="$(sed -ne 's/^## //1p' "${md}" | head -1)" echo "Latest changelog: ${ver_md}" ver_git="$(git tag -l | sort | grep -e "^v" | grep -v "rc" | tail -1)" echo "Latest release tag: ${ver_git}" ret=0 if [ "${ver_md}" != "${ver_git}" ]; then ret=1 echo "It seems there is no changelog information for ${ver_git} in ${md} yet." echo "Please, update changelog information in ${md}." fi; return "${ret}" } # Check for links to release builds in README.md docs_links() { ver_git="$(git tag -l | sort | grep -e "^v" | grep -v "rc" | tail -1)" md="README.md" test -f "${md}" || (echo "deploy.sh: docs_links: ERROR with the project directory structure!" && exit 1) ver_md="$(grep -c "${ver_git}" "${md}")" ret=0 if [ "${ver_md}" -eq 0 ]; then ret=1 echo "Please, update mention & links in ${md} inside Builds section for release builds with version ${ver_git}." fi; return "${ret}" } # source/Makefile:ALL_LANGUAGES & Translations/*.json automagical routine build_langs() { mk="../source/Makefile" cd Translations/ || (echo "deploy.sh: build_langs: ERROR with the project directory structure!" && exit 1) langs="$(echo "$(find ./*.json | sed -ne 's,^\./translation_,,; s,\.json$,,; /[A-Z]/p' ; sed -ne 's/^ALL_LANGUAGES=//p;' "${mk}")" | sed 's, ,\n,g; s,\r,,g' | sort | uniq -u)" if [ -n "${langs}" ]; then echo "It seems there is mismatch between supported languages and enabled builds." echo "Please, check files in Translations/ and ALL_LANGUAGES variable in source/Makefile for:" echo "${langs}" return 1 fi; cd .. echo -ne "\n" grep -nH $'\11' Translations/translation*.json ret="${?}" if [ "${ret}" -eq 0 ]; then echo -ne "\t^^^^\t^^^^\n" echo "Please, remove any tabs as indention from json file(s) in Translations/ directory (see the exact files & lines in the list above)." echo "Use spaces only to indent in the future, please." echo -ne "\n" return 1 fi; grep -nEH -e "^( {1}| {3}| {5}| {7}| {9}| {11})[^ ]" Translations/translation*.json ret="${?}" if [ "${ret}" -eq 0 ]; then echo -ne "\t^^^^\t^^^^\n" echo "Please, remove any odd amount of extra spaces as indention from json file(s) in Translations/ directory (see the exact files & lines in the list above)." echo "Use even amount of spaces to indent in the future, please (two actual spaces per one indent, not tab)." echo -ne "\n" return 1 fi; return 0 } # Helper function to check code style using clang-format & grep/sed custom parsers: # - basic logic moved from source/Makefile : `check-style` target for better maintainance since a lot of sh script involved; # - output goes in gcc-like error compatible format for IDEs/editors. check_style_file() { ret=0 src="${1}" test ! -f "${src}" && echo "ERROR!!! Provided file ${src} is not available to check/read!!!" && exit 1 # count lines using diff between beauty-fied file & original file to detect format issue var="$(clang-format "$src" | diff "$src" - | wc -l)" if [ "${var}" -ne 0 ]; then # show full log error or, if LIST=anything provided, then show only filename of interest (implemented for debug purposes mainly) if [ -z "${LIST}" ]; then # sed is here only for pretty logging clang-format "${src}" | diff "${src}" - | sed 's/^---/-------------------------------------------------------------------------------/; s/^< /--- /; s/^> /+++ /; /^[0-9].*/ s/[acd,].*$/ERROR1/; /^[0-9].*/ s,^,\n\n\n\n'"${src}"':,; /ERROR1$/ s,ERROR1$,:1: error: clang-format code style mismatch:,; ' else echo "${src}" fi; ret=1 fi; return "${ret}" } # check_style routine for those who too lazy to do it everytime manually check_style_log() { log="source/check-style.log" make -C source check-style 2>&1 | tee "${log}" chmod 0666 "${log}" sed -i -e 's,\r,,g' "${log}" return 0 } ### main docker_conf="Env.yml" # get absolute location of project root dir to make docker happy with config(s) # (successfully tested on relatively POSIX-compliant Dash shell) # this script script_file="/deploy.sh" # IronOS/scripts/deploy.sh script_path="${PWD}"/"${0}" # IronOS/scripts/ script_dir=${script_path%"${script_file}"} # IronOS/ root_dir="${script_dir}/.." # IronOS/Env.yml docker_file="-f ${root_dir}/${docker_conf}" # allow providing custom path to docker tool using DOCKER_BIN external env. var. # (compose sub-command must be included, i.e. DOCKER_BIN="/usr/local/bin/docker compose" ./deploy.sh) if [ -z "${DOCKER_BIN}" ]; then docker_app="" else docker_app="${DOCKER_BIN}" fi; # detect availability of docker docker_compose="$(command -v docker-compose)" if [ -n "${docker_compose}" ] && [ -z "${docker_app}" ]; then docker_app="${docker_compose}" fi; docker_tool="$(command -v docker)" if [ -n "${docker_tool}" ] && [ -z "${docker_app}" ]; then docker_app="${docker_tool} compose" fi; # give function argument a name cmd="${1}" # meta target to verify markdown documents if [ "docs" = "${cmd}" ]; then docs_readme readme="${?}" docs_history hist="${?}" build_langs langs="${?}" docs_links links="${?}" if [ "${readme}" -eq 0 ] && [ "${hist}" -eq 0 ] && [ "${langs}" -eq 0 ] && [ "${links}" -eq 0 ]; then ret=0 else ret=1 fi; exit ${ret} fi; # if only README.md for Documentation update is required then run it & exit if [ "docs_readme" = "${cmd}" ]; then docs_readme exit "${?}" fi; # if only History.md for Documentation update is required then run it & exit if [ "docs_history" = "${cmd}" ]; then docs_history exit "${?}" fi; if [ "build_langs" = "${cmd}" ]; then build_langs exit "${?}" fi; if [ "docs_links" = "${cmd}" ]; then docs_links exit "${?}" fi; if [ "check_style_file" = "${cmd}" ]; then check_style_file "${2}" exit "${?}" fi; if [ "check_style_log" = "${cmd}" ]; then check_style_log exit "${?}" fi; # if docker is not presented in any way show warning & exit if [ -z "${docker_app}" ]; then echo "ERROR: Can't find docker-compose nor docker tool. Please, install docker and try again." exit 1 fi; # construct command to run if [ -z "${cmd}" ] || [ "${cmd}" = "shell" ]; then docker_cmd="run --rm builder" elif [ "${cmd}" = "build" ]; then docker_cmd="run --rm builder make build-all OUT=${OUT}" elif [ "${cmd}" = "clean" ]; then docker rmi ironos-builder:latest docker system prune --filter label=ironos-builder:latest --force exit "${?}" else usage exit 1 fi; # change dir to project root dir & run constructed command cd "${root_dir}" || exit 1 echo -e "\n====>>>> Firing up & starting container..." if [ "${cmd}" = "shell" ]; then echo -e "\t* type \"exit\" to end the session when done;" fi; echo -e "\t* type \"${0} clean\" to delete created container (but not cached data)" echo -e "\n====>>>> ${docker_app} ${docker_file} ${docker_cmd}\n" eval "${docker_app} ${docker_file} ${docker_cmd}" exit "${?}" ================================================ FILE: scripts/flash_ts10X_linux.sh ================================================ #!/bin/bash # TS100 Flasher for Linux by Alex Wigen (https://github.com/awigen) # Jan 2021 - Update by Ysard (https://github.com/ysard) # Jul 2025 - Update by Karakurt DIR_TMP="/tmp/ironos" HEX_FIRMWARE="$DIR_TMP/ts100.hex" MAX_TRIES=5 usage() { echo echo "#######################" echo "# TS100/TS101 Flasher #" echo "#######################" echo echo " Usage: $0 " echo echo "This script has been tested to work on Fedora and Arch Linux." echo "If you experience any issues please open a ticket at:" echo "https://github.com/Ralim/IronOS/issues/new" echo } GAUTOMOUNT=0 disable_gautomount() { if ! GSETTINGS=$(which gsettings); then return 1 fi if ! gsettings get org.gnome.desktop.media-handling automount | grep true > /dev/null; then GAUTOMOUNT=1 gsettings set org.gnome.desktop.media-handling automount false fi } enable_gautomount() { if [ "$GAUTOMOUNT" -ne 0 ]; then gsettings set org.gnome.desktop.media-handling automount true fi } is_attached() { if ! output=$(lsblk -b --raw --output NAME,MODEL | grep 'DFU.*Disk'); then return 1 fi DEVICE=$(echo "$output" | awk '{print "/dev/"$1}') } instructions="not printed" wait_for_iron() { while ! is_attached; do if [ "$instructions" = "not printed" ]; then echo echo "#####################################################" echo "# Waiting for config disk device to appear #" echo "# #" echo "# Connect the soldering iron with a USB cable while #" echo "# holding the button closest to the tip pressed #" echo "#####################################################" echo instructions="printed" fi sleep 0.1 done } mount_iron() { mkdir -p "$DIR_TMP" user="${UID:-$(id -u)}" if ! sudo mount -t msdos -o uid="$user" "$DEVICE" "$DIR_TMP"; then echo "Failed to mount $DEVICE on $DIR_TMP" exit 1 fi } umount_iron() { if ! (mountpoint "$DIR_TMP" > /dev/null && sudo umount "$DIR_TMP"); then echo "Failed to unmount $DIR_TMP" exit 1 fi sleep 1 sudo rmdir "$DIR_TMP" } check_flash() { RDY_FIRMWARE="${HEX_FIRMWARE%.*}.rdy" ERR_FIRMWARE="${HEX_FIRMWARE%.*}.err" if [ -f "$RDY_FIRMWARE" ]; then echo -e "\e[92mFlash is done\e[0m" echo "Disconnect the USB and power up the iron. You're good to go." return 0 elif [ -f "$ERR_FIRMWARE" ]; then echo -e "\e[91mFlash error; Please retry!\e[0m" return 1 else echo -e "\e[91mUNKNOWN error\e[0m" echo "Flash result: " ls "$DIR_TMP"/ts100* return 1 fi } cleanup() { enable_gautomount if [ -d "$DIR_TMP" ]; then umount_iron fi } trap cleanup EXIT if [ "$#" -ne 1 ]; then echo "Please provide a HEX file to flash" usage exit 1 fi if [ ! -f "$1" ]; then echo "'$1' is not a regular file, please provide a HEX file to flash" usage exit 1 fi if [ "$(head -c1 "$1")" != ":" ] || [ "$(tail -n1 "$1" | head -c1)" != ":" ]; then echo "'$1' doesn't look like a valid HEX file. Please provide a HEX file to flash" usage exit 1 fi disable_gautomount TRIES=0 while [ $TRIES -lt $MAX_TRIES ]; do wait_for_iron NAME=$(sudo fatlabel "$DEVICE" 2>/dev/null) echo "Found $NAME config disk device on $DEVICE" mount_iron echo "Mounted config disk drive, flashing..." dd if="$1" of="$HEX_FIRMWARE" oflag=direct umount_iron echo "Waiting for $NAME to flash" sleep 5 echo "Remounting config disk drive" wait_for_iron mount_iron check_flash && exit 0 echo "Retrying automatically..." TRIES=$((TRIES + 1)) done echo -e "\e[91mMax retries reached.\e[0m" exit 1 ================================================ FILE: source/.clang-format ================================================ --- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -2 AlignAfterOpenBracket: Align AlignArrayOfStructures: Right AlignConsecutiveAssignments: Enabled: true AcrossEmptyLines: false AcrossComments: false AlignCompound: false PadOperators: true AlignConsecutiveBitFields: Enabled: true AcrossEmptyLines: false AcrossComments: false AlignCompound: false PadOperators: false AlignConsecutiveDeclarations: Enabled: true AcrossEmptyLines: false AcrossComments: false AlignCompound: false PadOperators: false AlignConsecutiveMacros: Enabled: true AcrossEmptyLines: false AcrossComments: false AlignCompound: false PadOperators: false AlignConsecutiveShortCaseStatements: Enabled: true AcrossEmptyLines: false AcrossComments: false AlignCaseColons: false AlignEscapedNewlines: Right AlignOperands: Align AlignTrailingComments: Kind: Always OverEmptyLines: 0 AllowAllArgumentsOnNextLine: true AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: Never AllowShortCaseLabelsOnASingleLine: false AllowShortEnumsOnASingleLine: true AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: Never AllowShortLambdasOnASingleLine: All AllowShortLoopsOnASingleLine: false AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: MultiLine AttributeMacros: - __capability BinPackArguments: true BinPackParameters: true BitFieldColonSpacing: Both BraceWrapping: AfterCaseLabel: false AfterClass: false AfterControlStatement: Never AfterEnum: false AfterExternBlock: false AfterFunction: false AfterNamespace: false AfterObjCDeclaration: false AfterStruct: false AfterUnion: false BeforeCatch: false BeforeElse: false BeforeLambdaBody: false BeforeWhile: false IndentBraces: false SplitEmptyFunction: true SplitEmptyRecord: true SplitEmptyNamespace: true BreakAfterAttributes: Never BreakAfterJavaFieldAnnotations: false BreakArrays: true BreakBeforeBinaryOperators: None BreakBeforeConceptDeclarations: Always BreakBeforeBraces: Attach BreakBeforeInlineASMColon: OnlyMultiline BreakBeforeTernaryOperators: true BreakConstructorInitializers: BeforeColon BreakInheritanceList: BeforeColon BreakStringLiterals: true ColumnLimit: 200 CommentPragmas: "^ IWYU pragma:" CompactNamespaces: false ConstructorInitializerIndentWidth: 4 ContinuationIndentWidth: 4 Cpp11BracedListStyle: true DerivePointerAlignment: false DisableFormat: false EmptyLineAfterAccessModifier: Never EmptyLineBeforeAccessModifier: LogicalBlock ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true ForEachMacros: - foreach - Q_FOREACH - BOOST_FOREACH IfMacros: - KJ_IF_MAYBE IncludeBlocks: Preserve IncludeCategories: - Regex: '^"(llvm|llvm-c|clang|clang-c)/' Priority: 2 SortPriority: 0 CaseSensitive: false - Regex: '^(<|"(gtest|gmock|isl|json)/)' Priority: 3 SortPriority: 0 CaseSensitive: false - Regex: ".*" Priority: 1 SortPriority: 0 CaseSensitive: false IncludeIsMainRegex: "(Test)?$" IncludeIsMainSourceRegex: "" IndentAccessModifiers: false IndentCaseBlocks: false IndentCaseLabels: false IndentExternBlock: AfterExternBlock IndentGotoLabels: true IndentPPDirectives: None IndentRequiresClause: true IndentWidth: 2 IndentWrappedFunctionNames: false InsertBraces: false InsertNewlineAtEOF: false InsertTrailingCommas: None IntegerLiteralSeparator: Binary: 0 BinaryMinDigits: 0 Decimal: 0 DecimalMinDigits: 0 Hex: 0 HexMinDigits: 0 JavaScriptQuotes: Leave JavaScriptWrapImports: true KeepEmptyLinesAtTheStartOfBlocks: true KeepEmptyLinesAtEOF: false LambdaBodyIndentation: Signature LineEnding: DeriveLF MacroBlockBegin: "" MacroBlockEnd: "" MaxEmptyLinesToKeep: 1 NamespaceIndentation: None ObjCBinPackProtocolList: Auto ObjCBlockIndentWidth: 2 ObjCBreakBeforeNestedBlockParam: true ObjCSpaceAfterProperty: false ObjCSpaceBeforeProtocolList: true PackConstructorInitializers: BinPack PenaltyBreakAssignment: 2 PenaltyBreakBeforeFirstCallParameter: 19 PenaltyBreakComment: 300 PenaltyBreakFirstLessLess: 120 PenaltyBreakOpenParenthesis: 0 PenaltyBreakString: 1000 PenaltyBreakTemplateDeclaration: 10 PenaltyExcessCharacter: 1000000 PenaltyIndentedWhitespace: 0 PenaltyReturnTypeOnItsOwnLine: 60 PointerAlignment: Right PPIndentWidth: -1 QualifierAlignment: Leave ReferenceAlignment: Pointer ReflowComments: true RemoveBracesLLVM: false RemoveParentheses: Leave RemoveSemicolon: false RequiresClausePosition: OwnLine RequiresExpressionIndentation: OuterScope SeparateDefinitionBlocks: Leave ShortNamespaceLines: 1 SortIncludes: CaseSensitive SortJavaStaticImport: Before SortUsingDeclarations: LexicographicNumeric SpaceAfterCStyleCast: false SpaceAfterLogicalNot: false SpaceAfterTemplateKeyword: true SpaceAroundPointerQualifiers: Default SpaceBeforeAssignmentOperators: true SpaceBeforeCaseColon: false SpaceBeforeCpp11BracedList: false SpaceBeforeCtorInitializerColon: true SpaceBeforeInheritanceColon: true SpaceBeforeJsonColon: false SpaceBeforeParens: ControlStatements SpaceBeforeParensOptions: AfterControlStatements: true AfterForeachMacros: true AfterFunctionDefinitionName: false AfterFunctionDeclarationName: false AfterIfMacros: true AfterOverloadedOperator: false AfterRequiresInClause: false AfterRequiresInExpression: false BeforeNonEmptyParentheses: false SpaceBeforeRangeBasedForLoopColon: true SpaceBeforeSquareBrackets: false SpaceInEmptyBlock: false SpacesBeforeTrailingComments: 1 SpacesInAngles: Never SpacesInContainerLiterals: true SpacesInLineCommentPrefix: Minimum: 1 Maximum: -1 SpacesInParens: Never SpacesInParensOptions: InCStyleCasts: false InConditionalStatements: false InEmptyParentheses: false Other: false SpacesInSquareBrackets: false Standard: Latest StatementAttributeLikeMacros: - Q_EMIT StatementMacros: - Q_UNUSED - QT_REQUIRE_VERSION TabWidth: 8 UseTab: Never VerilogBreakBetweenInstancePorts: true WhitespaceSensitiveMacros: - BOOST_PP_STRINGIZE - CF_SWIFT_NAME - NS_SWIFT_NAME - PP_STRINGIZE - STRINGIZE --- ================================================ FILE: source/Core/BSP/BSP.h ================================================ #include "BSP_Flash.h" #include "BSP_PD.h" #include "BSP_Power.h" #include "BSP_QC.h" #include "Defines.h" #include "Types.h" #include "configuration.h" #include #include /* * BSP.h -- Board Support * * This exposes functions that are expected to be implemented to add support for different hardware */ #ifndef BSP_BSP_H_ #define BSP_BSP_H_ #ifdef __cplusplus extern "C" { #endif // maximum htim2 PWM value extern const uint16_t powerPWM; // htim2.Init.Period, the full PWM cycle extern uint16_t totalPWM; // Called first thing in main() to init the hardware void preRToSInit(); // Called once the RToS has started for any extra work void postRToSInit(); // Called once from preRToSInit() void BSPInit(void); // Called to reset the hardware watchdog unit void resetWatchdog(); // Accepts a output level of 0.. to use to control the tip output PWM void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM); // Returns the Handle temp in C, X10 uint16_t getHandleTemperature(uint8_t sample); // Returns the Tip temperature ADC reading in raw units uint16_t getTipRawTemp(uint8_t refresh); // Returns the main DC input voltage, using the adjustable divisor + sample flag uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample); // Readers for the two buttons // !! Returns 1 if held down, 0 if released uint8_t getButtonA(); uint8_t getButtonB(); // This is a work around that will be called if I2C starts to bug out // This should toggle the SCL line until SDA goes high to end the current transaction void unstick_I2C(); // Reboot the IC when things go seriously wrong void reboot(); // If the user has programmed in a bootup logo, draw it to the screen from flash // Returns 1 if the logo was printed so that the unit waits for the timeout or button void showBootLogoIfavailable(); // delay wrapper for delay using the hardware timer (used before RTOS) void delay_ms(uint16_t count); // Probe if the Hall sensor is fitted to the unit bool getHallSensorFitted(); // If the iron has a hall effect sensor in the handle, return an signed count of the reading // If the sensor is single polarity (or polarity insensitive) just return 0..32768 int16_t getRawHallEffect(); // Returns true if power is from dumb "DC" input rather than "smart" QC or PD bool getIsPoweredByDCIN(); // Logs the system state to a debug interface if supported void log_system_state(int32_t PWMWattsx10); // Returns true if the tip is disconnected bool isTipDisconnected(); // Return hardware unique ID if possible uint64_t getDeviceID(); // If device has burned in validation code's, return the code uint32_t getDeviceValidation(); // If device validation passes returns 0 uint8_t getDeviceValidationStatus(); // Status LED controls enum StatusLED { LED_OFF = 0, // Turn off status led LED_STANDBY, // unit is in sleep /standby LED_HEATING, // The unit is heating up to temperature LED_HOT, // The unit is at operating temperature LED_COOLING_STILL_HOT, // The unit is off and cooling but still hot LED_UNKNOWN, // }; void setStatusLED(const enum StatusLED state); void setBuzzer(bool on); // preStartChecks are run until they return 0 // By the PID, after each ADC sample comes in // For example, on the MHP30 this is used to figure out the resistance of the hotplate uint8_t preStartChecks(); uint8_t preStartChecksDone(); // Check if the tip or output mosfet is shorted (if possible) bool isTipShorted(); // Show the boot logo void showBootLogo(void); #ifdef __cplusplus } #endif #endif /* BSP_BSP_H_ */ ================================================ FILE: source/Core/BSP/BSP_Common.c ================================================ #include "BSP.h" ================================================ FILE: source/Core/BSP/BSP_Flash.h ================================================ /* * BSP_Flash.h * * Created on: 29 May 2020 * Author: Ralim */ #include "stdint.h" #ifndef BSP_BSP_FLASH_H_ #define BSP_BSP_FLASH_H_ #ifdef __cplusplus extern "C" { #endif /* * Wrappers to allow read/writing to a sector of flash that we use to store all of the user settings * * Should allow reading and writing to the flash */ // Erase the flash, then save the buffer. Returns 1 if worked void flash_save_buffer(const uint8_t *buffer, const uint16_t length); void flash_read_buffer(uint8_t *buffer, const uint16_t length); #ifdef __cplusplus } #endif #endif /* BSP_BSP_FLASH_H_ */ ================================================ FILE: source/Core/BSP/BSP_PD.h ================================================ /* * BSP_PD.h * * Created on: 21 Jul 2020 * Author: Ralim */ #ifndef USER_BSP_PD_H_ #define USER_BSP_PD_H_ #include "BSP.h" bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf); bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf); void setupFUSBIRQ(); bool getFUS302IRQLow(); #endif /* USER_BSP_PD_H_ */ ================================================ FILE: source/Core/BSP/BSP_Power.h ================================================ #include "stdint.h" /* * BSP_Power.h -- Board Support for Power control * * These functions are hooks used to allow for power control * */ #ifndef BSP_POWER_H_ #define BSP_POWER_H_ #include "Types.h" #ifdef __cplusplus extern "C" { #endif // Called periodically in the movement handling thread // Can be used to check any details for the power system void power_check(); // Returns the tip resistance in x10 ohms, so 7.5 = 75; 14=140 etc uint8_t getTipResistanceX10(); uint16_t getTipThermalMass(); uint16_t getTipInertia(); TemperatureType_t getCustomTipMaxInC(); #ifdef __cplusplus } #endif #endif ================================================ FILE: source/Core/BSP/BSP_QC.h ================================================ /* * BSP_QC.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_BSP_QC_H_ #define BSP_BSP_QC_H_ #include "stdint.h" #ifdef __cplusplus extern "C" { #endif // Init GPIO for QC neg void QC_Init_GPIO(); // Set the DP pin to 0.6V void QC_DPlusZero_Six(); // Set the DM pin to 0.6V void QC_DNegZero_Six(); // Set the DP pin to 3.3V void QC_DPlusThree_Three(); // Set the DM pin to 3.3V void QC_DNegThree_Three(); // Turn on weak pulldown on the DM pin // This is used as a helper for some power banks void QC_DM_PullDown(); // Turn off the pulldown void QC_DM_No_PullDown(); // Turn on output drivers that were initally disabled to prevent spike through QC disable mode void QC_Post_Probe_En(); // Check if DM was pulled down // 1=Pulled down, 0 == pulled high uint8_t QC_DM_PulledDown(); // Re-sync if required void QC_resync(); #ifdef __cplusplus } #endif #endif /* BSP_BSP_QC_H_ */ ================================================ FILE: source/Core/BSP/Defines.h ================================================ /* * Defines.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_DEFINES_H_ #define BSP_DEFINES_H_ #include "FreeRTOSConfig.h" enum Orientation { ORIENTATION_LEFT_HAND = 0, ORIENTATION_RIGHT_HAND = 1, ORIENTATION_FLAT = 3 }; #define TICKS_SECOND configTICK_RATE_HZ #define TICKS_MIN (60 * TICKS_SECOND) #define TICKS_100MS (TICKS_SECOND / 10) #define TICKS_10MS (TICKS_100MS / 10) #endif /* BSP_DEFINES_H_ */ ================================================ FILE: source/Core/BSP/MHP30/BSP.cpp ================================================ // BSP mapping functions #include "BSP.h" #include "BootLogo.h" #include "I2C_Wrapper.hpp" #include "Pins.h" #include "Setup.h" #include "TipThermoModel.h" #include "Utils.hpp" #include "WS2812.h" #include "configuration.h" #include "history.hpp" #include "main.hpp" #include WS2812 ws2812; volatile uint16_t PWMSafetyTimer = 0; volatile uint8_t pendingPWM = 0; uint16_t totalPWM = 255; const uint16_t powerPWM = 255; uint16_t tipSenseResistancex10Ohms = 0; volatile bool tipMeasurementOccuring = false; history rawTempFilter = {{0}, 0, 0}; void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); } #ifdef TEMP_NTC // Lookup table for the NTC // Stored as ADCReading,Temp in degC static const int32_t NTCHandleLookup[] = { // ADC Reading , Temp in Cx10 808, 1600, // 832, 1590, // 848, 1580, // 872, 1570, // 888, 1560, // 912, 1550, // 936, 1540, // 960, 1530, // 984, 1520, // 1008, 1510, // 1032, 1500, // 1056, 1490, // 1080, 1480, // 1112, 1470, // 1136, 1460, // 1168, 1450, // 1200, 1440, // 1224, 1430, // 1256, 1420, // 1288, 1410, // 1328, 1400, // 1360, 1390, // 1392, 1380, // 1432, 1370, // 1464, 1360, // 1504, 1350, // 1544, 1340, // 1584, 1330, // 1632, 1320, // 1672, 1310, // 1720, 1300, // 1760, 1290, // 1808, 1280, // 1856, 1270, // 1912, 1260, // 1960, 1250, // 2016, 1240, // 2072, 1230, // 2128, 1220, // 2184, 1210, // 2248, 1200, // 2304, 1190, // 2368, 1180, // 2440, 1170, // 2504, 1160, // 2576, 1150, // 2648, 1140, // 2720, 1130, // 2792, 1120, // 2872, 1110, // 2952, 1100, // 3040, 1090, // 3128, 1080, // 3216, 1070, // 3304, 1060, // 3400, 1050, // 3496, 1040, // 3592, 1030, // 3696, 1020, // 3800, 1010, // 3912, 1000, // 4024, 990, // 4136, 980, // 4256, 970, // 4376, 960, // 4504, 950, // 4632, 940, // 4768, 930, // 4904, 920, // 5048, 910, // 5192, 900, // 5336, 890, // 5488, 880, // 5648, 870, // 5808, 860, // 5976, 850, // 6144, 840, // 6320, 830, // 6504, 820, // 6688, 810, // 6872, 800, // 7072, 790, // 7264, 780, // 7472, 770, // 7680, 760, // 7896, 750, // 8112, 740, // 8336, 730, // 8568, 720, // 8800, 710, // 9040, 700, // 9288, 690, // 9536, 680, // 9792, 670, // 10056, 660, // 10320, 650, // 10592, 640, // 10872, 630, // 11152, 620, // 11440, 610, // 11728, 600, // 12024, 590, // 12320, 580, // 12632, 570, // 12936, 560, // 13248, 550, // 13568, 540, // 13888, 530, // 14216, 520, // 14544, 510, // 14880, 500, // 15216, 490, // 15552, 480, // 15888, 470, // 16232, 460, // 16576, 450, // 16920, 440, // 17272, 430, // 17616, 420, // 17968, 410, // 18320, 400, // 18664, 390, // 19016, 380, // 19368, 370, // 19712, 360, // 20064, 350, // 20408, 340, // 20752, 330, // 21088, 320, // 21432, 310, // 21768, 300, // 22096, 290, // 22424, 280, // 22752, 270, // 23072, 260, // 23392, 250, // 23704, 240, // 24008, 230, // 24312, 220, // 24608, 210, // 24904, 200, // 25192, 190, // 25472, 180, // 25744, 170, // 26016, 160, // 26280, 150, // 26536, 140, // 26784, 130, // 27024, 120, // 27264, 110, // 27496, 100, // 27720, 90, // 27936, 80, // 28144, 70, // 28352, 60, // 28544, 50, // 28736, 40, // 28920, 30, // 29104, 20, // 29272, 10, // }; const int NTCHandleLookupItems = sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t)); #endif // These are called by the HAL after the corresponding events from the system // timers. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { // Period has elapsed if (htim->Instance == TIM4) { // STM uses this for internal functions as a counter for timeouts HAL_IncTick(); } } uint16_t getHandleTemperature(uint8_t sample) { int32_t result = getADC(0); return Utils::InterpolateLookupTable(NTCHandleLookup, NTCHandleLookupItems, result); } uint16_t getTipInstantTemperature() { return getADC(2); } uint16_t getTipRawTemp(uint8_t refresh) { if (refresh && (tipMeasurementOccuring == false)) { uint16_t lastSample = getTipInstantTemperature(); rawTempFilter.update(lastSample); return lastSample; } else { return rawTempFilter.average(); } } uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { // ADC maximum is 32767 == 3.3V at input == 28.05V at VIN // Therefore we can divide down from there // Multiplying ADC max by 4 for additional calibration options, // ideal term is 467 static uint8_t preFillneeded = 10; static uint32_t samples[BATTFILTERDEPTH]; static uint8_t index = 0; if (preFillneeded) { for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) { samples[i] = getADC(1); } preFillneeded--; } if (sample) { samples[index] = getADC(1); index = (index + 1) % BATTFILTERDEPTH; } uint32_t sum = 0; for (uint8_t i = 0; i < BATTFILTERDEPTH; i++) { sum += samples[i]; } sum /= BATTFILTERDEPTH; if (divisor == 0) { divisor = 1; } return sum * 4 / divisor; } void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) { // We can just set the timer directly if (htim3.Instance->PSC > 20) { htim3.Instance->CCR1 = 0; } else { htim3.Instance->CCR1 = pulse; } } void unstick_I2C() { GPIO_InitTypeDef GPIO_InitStruct; int timeout = 100; int timeout_cnt = 0; while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) { // Move clock to release I2C HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET); asm("nop"); asm("nop"); asm("nop"); asm("nop"); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); timeout_cnt++; if (timeout_cnt > timeout) { return; } } } uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; } uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; } void BSPInit(void) { ws2812.init(); } void reboot() { NVIC_SystemReset(); } void delay_ms(uint16_t count) { HAL_Delay(count); } void setPlatePullup(bool pullingUp) { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Pin = PLATE_SENSOR_PULLUP_Pin; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = pullingUp ? GPIO_MODE_OUTPUT_PP : GPIO_MODE_INPUT; HAL_GPIO_Init(PLATE_SENSOR_PULLUP_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(PLATE_SENSOR_PULLUP_GPIO_Port, PLATE_SENSOR_PULLUP_Pin, pullingUp ? GPIO_PIN_SET : GPIO_PIN_RESET); } void performTipMeasurementStep(bool start) { static uint16_t adcReadingPD1Set = 0; static TickType_t lastMeas = 0; // Inter state that performs the steps to measure the resistor on the tip // Return 1 if a measurement is ongoing // We want to perform our startup measurements of the tip resistance until we detect one fitted // Step 1; if not setup, we turn on pullup and then wait if (tipMeasurementOccuring == false && (start || tipSenseResistancex10Ohms == 0 || lastMeas == 0)) { tipMeasurementOccuring = true; tipSenseResistancex10Ohms = 0; lastMeas = xTaskGetTickCount(); adcReadingPD1Set = 0; setPlatePullup(true); return; } // Wait 100ms for settle time if ((xTaskGetTickCount() - lastMeas) < (TICKS_100MS)) { return; } lastMeas = xTaskGetTickCount(); // We are sensing the resistance if (adcReadingPD1Set == 0) { // We will record the reading for PD1 being set adcReadingPD1Set = getADC(3); setPlatePullup(false); return; } // Taking reading two uint16_t adcReadingPD1Cleared = getADC(3); uint32_t a = ((int)adcReadingPD1Set - (int)adcReadingPD1Cleared); a *= 10000; uint32_t b = ((int)adcReadingPD1Cleared + (32768 - (int)adcReadingPD1Set)); if (b) { tipSenseResistancex10Ohms = a / b; } else { tipSenseResistancex10Ohms = adcReadingPD1Set = lastMeas = 0; } if (tipSenseResistancex10Ohms > 1100 || tipSenseResistancex10Ohms < 900) { tipSenseResistancex10Ohms = 0; // out of range adcReadingPD1Set = 0; lastMeas = 0; return; } tipMeasurementOccuring = false; } bool isTipDisconnected() { static bool lastDisconnectedState = false; // For the MHP30 we want to include a little extra logic in here // As when the tip is first connected we want to measure the ~100 ohm resistor on the base of the tip // And likewise if its removed we want to clear that measurement /* * plate_sensor_res = ((adc5_value_PD1_set - adc5_value_PD1_cleared) / (adc5_value_PD1_cleared + 4096 - adc5_value_PD1_set)) * 1000.0; * */ if (tipMeasurementOccuring) { performTipMeasurementStep(false); return true; // We fake no tip disconnection during the measurement cycle to mask it } // If we are too close to the top, most likely disconnected tip bool tipDisconnected = getTipInstantTemperature() > (4090 * 8); if (tipDisconnected == false && lastDisconnectedState == true) { // Tip is now disconnected performTipMeasurementStep(true); } lastDisconnectedState = tipDisconnected; return tipDisconnected; } uint8_t preStartChecks() { performTipMeasurementStep(false); return tipMeasurementOccuring ? 0 : 1; } void setBuzzer(bool on) { if (on) { htim3.Instance->CCR2 = 128; htim3.Instance->PSC = 100; // drop down into audible range } else { htim3.Instance->CCR2 = 0; htim3.Instance->PSC = 1; // revert back out of hearing range } } void setStatusLED(const enum StatusLED state) { static enum StatusLED lastState = LED_UNKNOWN; static TickType_t buzzerEnd = 0; if (lastState != state || state == LED_HEATING) { switch (state) { default: case LED_UNKNOWN: case LED_OFF: ws2812.led_set_color(0, 0, 0, 0); break; case LED_STANDBY: ws2812.led_set_color(0, 0, 0xFF, 0); // green break; case LED_HEATING: { ws2812.led_set_color(0, ((HAL_GetTick() / 10) % 192) + 64, 0, 0); // Red fade } break; case LED_HOT: ws2812.led_set_color(0, 0xFF, 0, 0); // red break; case LED_COOLING_STILL_HOT: ws2812.led_set_color(0, 0xFF, 0x8C, 0x00); // Orange break; } ws2812.led_update(); lastState = state; } } uint64_t getDeviceID() { // return HAL_GetUIDw0() | ((uint64_t)HAL_GetUIDw1() << 32); } uint8_t preStartChecksDone() { return 1; } uint16_t getTipThermalMass() { return TIP_THERMAL_MASS; } uint16_t getTipInertia() { return TIP_THERMAL_MASS; } void showBootLogo(void) { BootLogo::handleShowingLogo((uint8_t *)FLASH_LOGOADDR); } ================================================ FILE: source/Core/BSP/MHP30/FreeRTOSConfig.h ================================================ /* FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. All rights reserved VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. *************************************************************************** >>! NOTE: The modification to the GPL is included to allow you to !<< >>! distribute a combined work that includes FreeRTOS without being !<< >>! obliged to provide the source code for proprietary components !<< >>! outside of the FreeRTOS kernel. !<< *************************************************************************** FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Full license text is available on the following link: http://www.freertos.org/a00114.html *************************************************************************** * * * FreeRTOS provides completely free yet professionally developed, * * robust, strictly quality controlled, supported, and cross * * platform software that is more than just the market leader, it * * is the industry's de facto standard. * * * * Help yourself get started quickly while simultaneously helping * * to support the FreeRTOS project by purchasing a FreeRTOS * * tutorial book, reference manual, or both: * * http://www.FreeRTOS.org/Documentation * * * *************************************************************************** http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading the FAQ page "My application does not run, what could be wrong?". Have you defined configASSERT()? http://www.FreeRTOS.org/support - In return for receiving this top quality embedded software for free we request you assist our global community by participating in the support forum. http://www.FreeRTOS.org/training - Investing in training allows your team to be as productive as possible as early as possible. Now you can receive FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers Ltd, and the world's leading authority on the world's leading RTOS. http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, including FreeRTOS+Trace - an indispensable productivity tool, a DOS compatible FAT file system, and our tiny thread aware UDP/IP stack. http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS licenses offer ticketed support, indemnification and commercial middleware. http://www.SafeRTOS.com - High Integrity Systems also provide a safety engineered and independently SIL3 certified version for use in safety and mission critical applications that require provable dependability. 1 tab == 4 spaces! */ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H /*----------------------------------------------------------- * Application specific definitions. * * These definitions should be adjusted for your particular hardware and * application requirements. * * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #ifdef __cplusplus extern "C" { #endif /* USER CODE END Includes */ /* Ensure stdint is only used by the compiler, and not the assembler. */ #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) #include extern uint32_t SystemCoreClock; #endif #define configUSE_PREEMPTION 1 #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ (SystemCoreClock) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((uint16_t)256) #define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/ #define configMAX_TASK_NAME_LEN (32) #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 #define configUSE_TIMERS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configCHECK_FOR_STACK_OVERFLOW 2 /*Bump this to 2 during development and bug hunting*/ #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 #define configMAX_CO_ROUTINE_PRIORITIES (2) /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ #define INCLUDE_vTaskPrioritySet 1 #define INCLUDE_uxTaskPriorityGet 0 #define INCLUDE_vTaskDelete 0 #define INCLUDE_vTaskCleanUpResources 0 #define INCLUDE_vTaskSuspend 0 #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1 /* Cortex-M specific definitions. */ #ifdef __NVIC_PRIO_BITS /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ #define configPRIO_BITS __NVIC_PRIO_BITS #else #define configPRIO_BITS 4 #endif /* The lowest interrupt priority that can be used in a call to a "set priority" function. */ #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 /* The highest interrupt priority that can be used by any interrupt service routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values. */ #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 /* Interrupt priorities used by the kernel port layer itself. These are generic to all Cortex-M ports, and do not rely on any particular library functions. */ #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) /* Normal assert() semantics without relying on the provision of an assert.h header file. */ /* USER CODE BEGIN 1 */ #define configASSERT(x) \ if ((x) == 0) { \ taskDISABLE_INTERRUPTS(); \ for (;;) \ ; \ } /* USER CODE END 1 */ /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ #define vPortSVCHandler SVC_Handler #define xPortPendSVHandler PendSV_Handler #if configUSE_TIMERS #define configTIMER_TASK_PRIORITY 2 #define configTIMER_QUEUE_LENGTH 8 #define configTIMER_TASK_STACK_DEPTH (512 / 4) #endif #ifdef __cplusplus } #endif #endif /* FREERTOS_CONFIG_H */ ================================================ FILE: source/Core/BSP/MHP30/IRQ.cpp ================================================ /* * IRQ.c * * Created on: 30 May 2020 * Author: Ralim */ #include "IRQ.h" #include "Pins.h" #include "configuration.h" /* * Catch the IRQ that says that the conversion is done on the temperature * readings coming in Once these have come in we can unblock the PID so that it * runs again */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { static uint8_t counter = 0; BaseType_t xHigherPriorityTaskWoken = pdFALSE; if (hadc == &hadc1) { counter++; if (counter % 32 == 0) { // 64 = 128ms, 32 = 64ms if (pidTaskNotification) { vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } } } extern osThreadId POWTaskHandle; void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { (void)GPIO_Pin; // Notify POW thread that an irq occured if (POWTaskHandle != nullptr) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken); /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE. The macro used to do this is dependent on the port and may be called portEND_SWITCHING_ISR. */ portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } bool getFUS302IRQLow() { #ifdef POW_PD // Return true if the IRQ line is still held low return HAL_GPIO_ReadPin(INT_PD_GPIO_Port, INT_PD_Pin) == GPIO_PIN_RESET; #else return false; #endif } ================================================ FILE: source/Core/BSP/MHP30/IRQ.h ================================================ /* * Irqs.h * * Created on: 30 May 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_IRQ_H_ #define BSP_MINIWARE_IRQ_H_ #include "BSP.h" #include "I2C_Wrapper.hpp" #include "Setup.h" #include "main.hpp" #include "stm32f1xx_hal.h" #ifdef __cplusplus extern "C" { #endif void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_GPIO_EXTI_Callback(uint16_t); #ifdef __cplusplus } #endif #endif /* BSP_MINIWARE_IRQ_H_ */ ================================================ FILE: source/Core/BSP/MHP30/Pins.h ================================================ /* * Pins.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_PINS_H_ #define BSP_MINIWARE_PINS_H_ #include "configuration.h" // MHP30 pin map #define KEY_B_Pin GPIO_PIN_0 #define KEY_B_GPIO_Port GPIOB #define TMP36_INPUT_Pin GPIO_PIN_1 #define TMP36_INPUT_GPIO_Port GPIOB #define TMP36_ADC1_CHANNEL ADC_CHANNEL_9 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_9 #define TIP_TEMP_Pin GPIO_PIN_2 #define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_2 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_2 #define VIN_Pin GPIO_PIN_1 #define VIN_GPIO_Port GPIOA #define VIN_ADC1_CHANNEL ADC_CHANNEL_1 #define VIN_ADC2_CHANNEL ADC_CHANNEL_1 #define OLED_RESET_Pin GPIO_PIN_4 #define OLED_RESET_GPIO_Port GPIOB #define KEY_A_Pin GPIO_PIN_10 #define KEY_A_GPIO_Port GPIOA #define PWM_Out_Pin GPIO_PIN_6 #define PWM_Out_GPIO_Port GPIOA #define PWM_Out_CHANNEL TIM_CHANNEL_1 #define BUZZER_Pin GPIO_PIN_7 #define BUZZER_GPIO_Port GPIOA #define BUZZER_CHANNEL TIM_CHANNEL_2 #define SCL_Pin GPIO_PIN_6 #define SCL_GPIO_Port GPIOB #define SDA_Pin GPIO_PIN_7 #define SDA_GPIO_Port GPIOB #define SCL2_Pin GPIO_PIN_3 #define SCL2_GPIO_Port GPIOB #define SDA2_Pin GPIO_PIN_15 #define SDA2_GPIO_Port GPIOA #define INT_PD_Pin GPIO_PIN_5 #define INT_PD_GPIO_Port GPIOB #define HEAT_EN_Pin GPIO_PIN_3 #define HEAT_EN_GPIO_Port GPIOA #define PLATE_SENSOR_PULLUP_Pin GPIO_PIN_1 #define PLATE_SENSOR_PULLUP_GPIO_Port GPIOD #define PLATE_SENSOR_Pin GPIO_PIN_5 #define PLATE_SENSOR_GPIO_Port GPIOA #define PLATE_SENSOR_ADC1_CHANNEL ADC_CHANNEL_5 #define PLATE_SENSOR_ADC2_CHANNEL ADC_CHANNEL_5 #define WS2812_Pin GPIO_PIN_8 #define WS2812_GPIO_Port GPIOA #endif /* BSP_MINIWARE_PINS_H_ */ ================================================ FILE: source/Core/BSP/MHP30/Power.cpp ================================================ #include "BSP.h" #include "BSP_Power.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "USBPD.h" #include "configuration.h" void power_check() { #ifdef POW_PD // Cant start QC until either PD works or fails if (USBPowerDelivery::negotiationComplete()) { return; } #endif } bool getIsPoweredByDCIN() { return false; } uint8_t getTipResistanceX10() { return TIP_RESISTANCE; } bool isTipShorted() { return false; } ================================================ FILE: source/Core/BSP/MHP30/QC_GPIO.cpp ================================================ /* * QC.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "configuration.h" #include "stm32f1xx_hal.h" #ifdef POW_QC void QC_DPlusZero_Six() { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+ } void QC_DNegZero_Six() { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); } void QC_DPlusThree_Three() { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+ } void QC_DNegThree_Three() { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); } void QC_DM_PullDown() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Pin = GPIO_PIN_11; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_DM_No_PullDown() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_11; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_Init_GPIO() { // Setup any GPIO into the right states for QC GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); // Turn off output mode on pins that we can GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_Post_Probe_En() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; } #endif void QC_resync() { #ifdef POW_QC seekQC(systemSettings.QCIdealVoltage, systemSettings.voltageDiv); // Run the QC seek again if we have drifted too much #endif } ================================================ FILE: source/Core/BSP/MHP30/README.md ================================================ # BSP section for STM32F103 based Miniware products This folder contains the hardware abstractions required for the TS100, TS80 and probably TS80P soldering irons. ## Main abstractions * Hardware Init * -> Should contain all bootstrap to bring the hardware up to an operating point * -> Two functions are required, a pre and post FreeRToS call * I2C read/write * Set PWM for the tip * Links between IRQ's on the system and the calls in the rest of the firmware ================================================ FILE: source/Core/BSP/MHP30/Setup.c ================================================ /* * Setup.c * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #include "Setup.h" #include "Pins.h" #include ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; DMA_HandleTypeDef hdma_adc1; IWDG_HandleTypeDef hiwdg; TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; #define ADC_CHANNELS 4 #define ADC_SAMPLES 16 uint32_t ADCReadings[ADC_SAMPLES * ADC_CHANNELS]; // room for 32 lots of the pair of readings // Functions static void SystemClock_Config(void); static void MX_ADC1_Init(void); static void MX_IWDG_Init(void); static void MX_TIM3_Init(void); static void MX_TIM2_Init(void); static void MX_DMA_Init(void); static void MX_GPIO_Init(void); static void MX_ADC2_Init(void); void Setup_HAL() { SystemClock_Config(); __HAL_AFIO_REMAP_SWJ_NOJTAG(); MX_GPIO_Init(); MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_TIM3_Init(); MX_TIM2_Init(); MX_IWDG_Init(); HAL_ADC_Start(&hadc2); HAL_ADCEx_MultiModeStart_DMA(&hadc1, ADCReadings, (ADC_SAMPLES * ADC_CHANNELS)); // start DMA of normal readings // HAL_ADCEx_InjectedStart(&hadc1); // enable injected readings // HAL_ADCEx_InjectedStart(&hadc2); // enable injected readings } // channel 0 -> temperature sensor, 1-> VIN, 2-> tip uint16_t getADC(uint8_t channel) { uint32_t sum = 0; for (uint8_t i = 0; i < ADC_SAMPLES; i++) { uint16_t adc1Sample = ADCReadings[channel + (i * ADC_CHANNELS)]; uint16_t adc2Sample = ADCReadings[channel + (i * ADC_CHANNELS)] >> 16; sum += (adc1Sample + adc2Sample); } return sum >> 2; } /** System Clock Configuration */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64MHz HAL_RCC_OscConfig(&RCC_OscInitStruct); /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // TIM // 2,3,4,5,6,7,12,13,14 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 mhz to some peripherals and adc HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_CFGR_ADCPRE_DIV8; // 6 or 8 are the only non overclocked options HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); } /* ADC1 init function */ static void MX_ADC1_Init(void) { ADC_MultiModeTypeDef multimode; ADC_ChannelConfTypeDef sConfig; /**Common config */ hadc1.Instance = ADC1; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.NbrOfConversion = ADC_CHANNELS; HAL_ADC_Init(&hadc1); /**Configure the ADC multi-mode */ multimode.Mode = ADC_DUALMODE_REGSIMULT_INJECSIMULT; HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode); /**Configure Regular Channel */ sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; sConfig.Channel = TMP36_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_1; HAL_ADC_ConfigChannel(&hadc1, &sConfig); /**Configure Regular Channel */ sConfig.Channel = VIN_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_2; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = TIP_TEMP_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_3; HAL_ADC_ConfigChannel(&hadc1, &sConfig); sConfig.Channel = PLATE_SENSOR_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_4; HAL_ADC_ConfigChannel(&hadc1, &sConfig); SET_BIT(hadc1.Instance->CR1, (ADC_CR1_EOSIE)); // Enable end of Normal // Run ADC internal calibration while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) { ; } } /* ADC2 init function */ static void MX_ADC2_Init(void) { ADC_ChannelConfTypeDef sConfig; /**Common config */ hadc2.Instance = ADC2; hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc2.Init.ContinuousConvMode = ENABLE; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.NbrOfConversion = ADC_CHANNELS; HAL_ADC_Init(&hadc2); sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; /**Configure Regular Channel */ sConfig.Channel = TMP36_ADC2_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_1; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = VIN_ADC2_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_2; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = TIP_TEMP_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_3; HAL_ADC_ConfigChannel(&hadc2, &sConfig); sConfig.Channel = PLATE_SENSOR_ADC2_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_4; HAL_ADC_ConfigChannel(&hadc2, &sConfig); // Run ADC internal calibration while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK) { ; } } /* IWDG init function */ static void MX_IWDG_Init(void) { hiwdg.Instance = IWDG; hiwdg.Init.Prescaler = IWDG_PRESCALER_256; hiwdg.Init.Reload = 100; #ifndef SWD_ENABLE HAL_IWDG_Init(&hiwdg); #endif } /* TIM3 init function */ static void MX_TIM3_Init(void) { TIM_ClockConfigTypeDef sClockSourceConfig; TIM_MasterConfigTypeDef sMasterConfig; TIM_OC_InitTypeDef sConfigOC; memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig)); memset(&sMasterConfig, 0, sizeof(sMasterConfig)); memset(&sConfigOC, 0, sizeof(sConfigOC)); htim3.Instance = TIM3; htim3.Init.Prescaler = 1; htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.Period = 255; // htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; // 4mhz before div htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; // Preload the ARR register (though we dont use this) HAL_TIM_Base_Init(&htim3); sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig); HAL_TIM_PWM_Init(&htim3); HAL_TIM_OC_Init(&htim3); sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig); sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.Pulse = 0; // Output control sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, PWM_Out_CHANNEL); HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, BUZZER_CHANNEL); GPIO_InitTypeDef GPIO_InitStruct; /**TIM3 GPIO Configuration PWM_Out_Pin ------> TIM3_CH1 */ GPIO_InitStruct.Pin = PWM_Out_Pin | BUZZER_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct); HAL_TIM_PWM_Start(&htim3, PWM_Out_CHANNEL); HAL_TIM_PWM_Start(&htim3, BUZZER_CHANNEL); } /* TIM3 init function */ static void MX_TIM2_Init(void) { TIM_ClockConfigTypeDef sClockSourceConfig; TIM_MasterConfigTypeDef sMasterConfig; TIM_OC_InitTypeDef sConfigOC; htim2.Instance = TIM2; htim2.Init.Prescaler = 200; // 2 MHz timer clock/2000 = 1 kHz tick rate // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow" htim2.Init.CounterMode = TIM_COUNTERMODE_UP; // dummy value, will be reconfigured by BSPInit() htim2.Init.Period = 10; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; // 8 MHz (x2 APB1) before divide htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; htim2.Init.RepetitionCounter = 0; HAL_TIM_Base_Init(&htim2); sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig); HAL_TIM_PWM_Init(&htim2); sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig); sConfigOC.OCMode = TIM_OCMODE_PWM1; // dummy value, will be reconfigured by BSPInit() in the BSP.cpp sConfigOC.Pulse = 5; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4); GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = HEAT_EN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges HAL_GPIO_Init(HEAT_EN_GPIO_Port, &GPIO_InitStruct); HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4); } /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 10, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); } static void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct; memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; /*Configure GPIO pins : PD0 PD1 */ GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_PD01_ENABLE(); //^ remap XTAL so that pins used /* * Configure All pins as analog by default */ GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */ GPIO_InitStruct.Pin = KEY_B_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = KEY_A_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(KEY_A_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pin : OLED_RESET_Pin */ GPIO_InitStruct.Pin = OLED_RESET_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = WS2812_Pin; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(WS2812_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(WS2812_GPIO_Port, WS2812_Pin, GPIO_PIN_RESET); // Pull down LCD reset HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); HAL_Delay(30); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET); } #ifdef USE_FULL_ASSERT void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); } #endif ================================================ FILE: source/Core/BSP/MHP30/Setup.h ================================================ /* * Setup.h * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #ifndef SETUP_H_ #define SETUP_H_ #ifdef __cplusplus extern "C" { #endif #include "stm32f1xx_hal.h" extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; extern DMA_HandleTypeDef hdma_adc1; extern DMA_HandleTypeDef hdma_i2c1_rx; extern DMA_HandleTypeDef hdma_i2c1_tx; extern IWDG_HandleTypeDef hiwdg; extern TIM_HandleTypeDef htim1; extern DMA_HandleTypeDef hdma_tim1_ch1; extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim3; void Setup_HAL(); uint16_t getADC(uint8_t channel); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one #ifdef __cplusplus } #endif #endif /* SETUP_H_ */ ================================================ FILE: source/Core/BSP/MHP30/Software_I2C.h ================================================ /* * Software_I2C.h * * Created on: 25 Jul 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_ #define BSP_MINIWARE_SOFTWARE_I2C_H_ #include "BSP.h" #include "configuration.h" #include "stm32f1xx_hal.h" #ifdef I2C_SOFT_BUS_2 #define SOFT_SCL2_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET) #define SOFT_SCL2_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET) #define SOFT_SDA2_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET) #define SOFT_SDA2_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET) #define SOFT_SDA2_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SCL2_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0) #endif #ifdef I2C_SOFT_BUS_1 #define SOFT_SCL1_HIGH() HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET) #define SOFT_SCL1_LOW() HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET) #define SOFT_SDA1_HIGH() HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET) #define SOFT_SDA1_LOW() HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_RESET) #define SOFT_SDA1_READ() (HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SCL1_READ() (HAL_GPIO_ReadPin(SCL_GPIO_Port, SCL_Pin) == GPIO_PIN_SET ? 1 : 0) #endif #define SOFT_I2C_DELAY() \ { \ for (int xx = 0; xx < 15; xx++) { \ asm("nop"); \ } \ } // 40 ~= 100kHz; 15 gives around 250kHz or so which is fast _and_ stable #endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */ ================================================ FILE: source/Core/BSP/MHP30/Startup/startup_stm32f103t8ux.S ================================================ /** ****************************************************************************** * @file startup_stm32.s * @author Ac6 * @version V1.0.0 * @date 12-June-2014 ****************************************************************************** */ .syntax unified .cpu cortex-m3 .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2] adds r2, r2, #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex-M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler .word PVD_IRQHandler .word TAMPER_IRQHandler .word RTC_IRQHandler .word FLASH_IRQHandler .word RCC_IRQHandler .word EXTI0_IRQHandler .word EXTI1_IRQHandler .word EXTI2_IRQHandler .word EXTI3_IRQHandler .word EXTI4_IRQHandler .word DMA1_Channel1_IRQHandler .word DMA1_Channel2_IRQHandler .word DMA1_Channel3_IRQHandler .word DMA1_Channel4_IRQHandler .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler .word ADC1_2_IRQHandler .word USB_HP_CAN1_TX_IRQHandler .word USB_LP_CAN1_RX0_IRQHandler .word CAN1_RX1_IRQHandler .word CAN1_SCE_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_IRQHandler .word TIM1_UP_IRQHandler .word TIM1_TRG_COM_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler .word TIM4_IRQHandler .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler .word I2C2_EV_IRQHandler .word I2C2_ER_IRQHandler .word SPI1_IRQHandler .word SPI2_IRQHandler .word USART1_IRQHandler .word USART2_IRQHandler .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTC_Alarm_IRQHandler .word USBWakeUp_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word BootRAM /* @0x108. This is for boot in RAM mode for STM32F10x Medium Density devices. */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMPER_IRQHandler .thumb_set TAMPER_IRQHandler,Default_Handler .weak RTC_IRQHandler .thumb_set RTC_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak USB_HP_CAN1_TX_IRQHandler .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler .weak USB_LP_CAN1_RX0_IRQHandler .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_IRQHandler .thumb_set TIM1_BRK_IRQHandler,Default_Handler .weak TIM1_UP_IRQHandler .thumb_set TIM1_UP_IRQHandler,Default_Handler .weak TIM1_TRG_COM_IRQHandler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler /************************ (C) COPYRIGHT Ac6 *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/ThermoModel.cpp ================================================ /* * ThermoModel.cpp * * Created on: 1 May 2021 * Author: Ralim */ #include "Setup.h" #include "TipThermoModel.h" #include "Types.h" #include "Utils.hpp" #include "configuration.h" extern uint16_t tipSenseResistancex10Ohms; TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { // For the MHP30, we are mimicing the original code and using the resistor fitted to the base of the heater head, // this is measured at boot in pid task and in the disconnected tip check if tip is removed if (tipSenseResistancex10Ohms > 900 && tipSenseResistancex10Ohms <= 1100) { int32_t a = ((tipSenseResistancex10Ohms / 10) + 300) * (3300000 - tipuVDelta); int32_t b = a / 1000000; int32_t c = tipuVDelta - b; int32_t d = c * 243 / 1000; return d / 10; } return 0xFFFF; } ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h ================================================ /** ****************************************************************************** * @file stm32f103xb.h * @author MCD Application Team * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f103xb * @{ */ #ifndef __STM32F103xB_H #define __STM32F103xB_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F10x Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers *********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMPER_IRQn = 2, /*!< Tamper Interrupt */ RTC_IRQn = 3, /*!< RTC global Interrupt */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm3.h" #include "system_stm32f1xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SMPR1; __IO uint32_t SMPR2; __IO uint32_t JOFR1; __IO uint32_t JOFR2; __IO uint32_t JOFR3; __IO uint32_t JOFR4; __IO uint32_t HTR; __IO uint32_t LTR; __IO uint32_t SQR1; __IO uint32_t SQR2; __IO uint32_t SQR3; __IO uint32_t JSQR; __IO uint32_t JDR1; __IO uint32_t JDR2; __IO uint32_t JDR3; __IO uint32_t JDR4; __IO uint32_t DR; } ADC_TypeDef; typedef struct { __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ uint32_t RESERVED[16]; __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ } ADC_Common_TypeDef; /** * @brief Backup Registers */ typedef struct { uint32_t RESERVED0; __IO uint32_t DR1; __IO uint32_t DR2; __IO uint32_t DR3; __IO uint32_t DR4; __IO uint32_t DR5; __IO uint32_t DR6; __IO uint32_t DR7; __IO uint32_t DR8; __IO uint32_t DR9; __IO uint32_t DR10; __IO uint32_t RTCCR; __IO uint32_t CR; __IO uint32_t CSR; } BKP_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; __IO uint32_t TDTR; __IO uint32_t TDLR; __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; __IO uint32_t RDTR; __IO uint32_t RDLR; __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; __IO uint32_t MSR; __IO uint32_t TSR; __IO uint32_t RF0R; __IO uint32_t RF1R; __IO uint32_t IER; __IO uint32_t ESR; __IO uint32_t BTR; uint32_t RESERVED0[88]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FMR; __IO uint32_t FM1R; uint32_t RESERVED2; __IO uint32_t FS1R; uint32_t RESERVED3; __IO uint32_t FFA1R; uint32_t RESERVED4; __IO uint32_t FA1R; uint32_t RESERVED5[8]; CAN_FilterRegister_TypeDef sFilterRegister[14]; } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; __IO uint32_t CPAR; __IO uint32_t CMAR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; __IO uint32_t IFCR; } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; __IO uint32_t EMR; __IO uint32_t RTSR; __IO uint32_t FTSR; __IO uint32_t SWIER; __IO uint32_t PR; } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; __IO uint32_t KEYR; __IO uint32_t OPTKEYR; __IO uint32_t SR; __IO uint32_t CR; __IO uint32_t AR; __IO uint32_t RESERVED; __IO uint32_t OBR; __IO uint32_t WRPR; } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint16_t RDP; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRP0; __IO uint16_t WRP1; __IO uint16_t WRP2; __IO uint16_t WRP3; } OB_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t CRL; __IO uint32_t CRH; __IO uint32_t IDR; __IO uint32_t ODR; __IO uint32_t BSRR; __IO uint32_t BRR; __IO uint32_t LCKR; } GPIO_TypeDef; /** * @brief Alternate Function I/O */ typedef struct { __IO uint32_t EVCR; __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; __IO uint32_t MAPR2; } AFIO_TypeDef; /** * @brief Inter Integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t OAR1; __IO uint32_t OAR2; __IO uint32_t DR; __IO uint32_t SR1; __IO uint32_t SR2; __IO uint32_t CCR; __IO uint32_t TRISE; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CSR; } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CFGR; __IO uint32_t CIR; __IO uint32_t APB2RSTR; __IO uint32_t APB1RSTR; __IO uint32_t AHBENR; __IO uint32_t APB2ENR; __IO uint32_t APB1ENR; __IO uint32_t BDCR; __IO uint32_t CSR; } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t CRH; __IO uint32_t CRL; __IO uint32_t PRLH; __IO uint32_t PRLL; __IO uint32_t DIVH; __IO uint32_t DIVL; __IO uint32_t CNTH; __IO uint32_t CNTL; __IO uint32_t ALRH; __IO uint32_t ALRL; } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SR; __IO uint32_t DR; __IO uint32_t CRCPR; __IO uint32_t RXCRCR; __IO uint32_t TXCRCR; __IO uint32_t I2SCFGR; } SPI_TypeDef; /** * @brief TIM Timers */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ typedef struct { __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ __IO uint16_t RESERVED2; /*!< Reserved */ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ #define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */ #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ /* USB device FS */ #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *)TIM2_BASE) #define TIM3 ((TIM_TypeDef *)TIM3_BASE) #define TIM4 ((TIM_TypeDef *)TIM4_BASE) #define RTC ((RTC_TypeDef *)RTC_BASE) #define WWDG ((WWDG_TypeDef *)WWDG_BASE) #define IWDG ((IWDG_TypeDef *)IWDG_BASE) #define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define USART2 ((USART_TypeDef *)USART2_BASE) #define USART3 ((USART_TypeDef *)USART3_BASE) #define I2C1 ((I2C_TypeDef *)I2C1_BASE) #define I2C2 ((I2C_TypeDef *)I2C2_BASE) #define USB ((USB_TypeDef *)USB_BASE) #define CAN1 ((CAN_TypeDef *)CAN1_BASE) #define BKP ((BKP_TypeDef *)BKP_BASE) #define PWR ((PWR_TypeDef *)PWR_BASE) #define AFIO ((AFIO_TypeDef *)AFIO_BASE) #define EXTI ((EXTI_TypeDef *)EXTI_BASE) #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) #define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ADC2 ((ADC_TypeDef *)ADC2_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) #define TIM1 ((TIM_TypeDef *)TIM1_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE) #define USART1 ((USART_TypeDef *)USART1_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) #define RCC ((RCC_TypeDef *)RCC_BASE) #define CRC ((CRC_TypeDef *)CRC_BASE) #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) #define OB ((OB_TypeDef *)OB_BASE) #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ #define PWR_CR_LPDS_Pos (0U) #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ #define PWR_CR_PDDS_Pos (1U) #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ #define PWR_CR_CWUF_Pos (2U) #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ #define PWR_CR_CSBF_Pos (3U) #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ #define PWR_CR_PVDE_Pos (4U) #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ #define PWR_CR_PLS_Pos (5U) #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ /* Legacy defines */ #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register ********************/ #define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ #define PWR_CSR_SBF_Pos (1U) #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ #define PWR_CSR_PVDO_Pos (2U) #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ #define PWR_CSR_EWUP_Pos (8U) #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ /******************************************************************************/ /* */ /* Backup registers */ /* */ /******************************************************************************/ /******************* Bit definition for BKP_DR1 register ********************/ #define BKP_DR1_D_Pos (0U) #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR2 register ********************/ #define BKP_DR2_D_Pos (0U) #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR3 register ********************/ #define BKP_DR3_D_Pos (0U) #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR4 register ********************/ #define BKP_DR4_D_Pos (0U) #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR5 register ********************/ #define BKP_DR5_D_Pos (0U) #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR6 register ********************/ #define BKP_DR6_D_Pos (0U) #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR7 register ********************/ #define BKP_DR7_D_Pos (0U) #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR8 register ********************/ #define BKP_DR8_D_Pos (0U) #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR9 register ********************/ #define BKP_DR9_D_Pos (0U) #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR10 register *******************/ #define BKP_DR10_D_Pos (0U) #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ #define RTC_BKP_NUMBER 10 /****************** Bit definition for BKP_RTCCR register *******************/ #define BKP_RTCCR_CAL_Pos (0U) #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ #define BKP_RTCCR_CCO_Pos (7U) #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ #define BKP_RTCCR_ASOE_Pos (8U) #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ #define BKP_RTCCR_ASOS_Pos (9U) #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ /******************** Bit definition for BKP_CR register ********************/ #define BKP_CR_TPE_Pos (0U) #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ #define BKP_CR_TPAL_Pos (1U) #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ /******************* Bit definition for BKP_CSR register ********************/ #define BKP_CSR_CTE_Pos (0U) #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ #define BKP_CSR_CTI_Pos (1U) #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ #define BKP_CSR_TPIE_Pos (2U) #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ #define BKP_CSR_TEF_Pos (8U) #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ #define BKP_CSR_TIF_Pos (9U) #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_HSION_Pos (0U) #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ #define RCC_CR_HSIRDY_Pos (1U) #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ #define RCC_CR_HSITRIM_Pos (3U) #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ #define RCC_CR_HSICAL_Pos (8U) #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ #define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ #define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ #define RCC_CR_HSEBYP_Pos (18U) #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ #define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ #define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ #define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ #define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCC_CFGR_ADCPRE_Pos (14U) #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ #define RCC_CFGR_PLLXTPRE_Pos (17U) #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ /*!< PLLMUL configuration */ #define RCC_CFGR_PLLMULL_Pos (18U) #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ #define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ #define RCC_CFGR_PLLMULL4_Pos (19U) #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ #define RCC_CFGR_PLLMULL5_Pos (18U) #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ #define RCC_CFGR_PLLMULL6_Pos (20U) #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ #define RCC_CFGR_PLLMULL7_Pos (18U) #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ #define RCC_CFGR_PLLMULL8_Pos (19U) #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ #define RCC_CFGR_PLLMULL9_Pos (18U) #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ #define RCC_CFGR_PLLMULL10_Pos (21U) #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ #define RCC_CFGR_PLLMULL11_Pos (18U) #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ #define RCC_CFGR_PLLMULL12_Pos (19U) #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ #define RCC_CFGR_PLLMULL13_Pos (18U) #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ #define RCC_CFGR_PLLMULL14_Pos (20U) #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ #define RCC_CFGR_PLLMULL15_Pos (18U) #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ #define RCC_CFGR_PLLMULL16_Pos (19U) #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ #define RCC_CFGR_USBPRE_Pos (22U) #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ /*!< MCO configuration */ #define RCC_CFGR_MCO_Pos (24U) #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ /* Reference defines */ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!<****************** Bit definition for RCC_CIR register ********************/ #define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ #define RCC_CIR_LSERDYF_Pos (1U) #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ #define RCC_CIR_HSIRDYF_Pos (2U) #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ #define RCC_CIR_HSERDYF_Pos (3U) #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ #define RCC_CIR_PLLRDYF_Pos (4U) #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ #define RCC_CIR_CSSF_Pos (7U) #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ #define RCC_CIR_LSIRDYIE_Pos (8U) #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ #define RCC_CIR_LSERDYIE_Pos (9U) #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ #define RCC_CIR_HSIRDYIE_Pos (10U) #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ #define RCC_CIR_HSERDYIE_Pos (11U) #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ #define RCC_CIR_PLLRDYIE_Pos (12U) #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ #define RCC_CIR_LSIRDYC_Pos (16U) #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ #define RCC_CIR_LSERDYC_Pos (17U) #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ #define RCC_CIR_HSIRDYC_Pos (18U) #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ #define RCC_CIR_HSERDYC_Pos (19U) #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ #define RCC_CIR_PLLRDYC_Pos (20U) #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ #define RCC_CIR_CSSC_Pos (23U) #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2RSTR register *****************/ #define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ #define RCC_APB2RSTR_IOPARST_Pos (2U) #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ #define RCC_APB2RSTR_IOPBRST_Pos (3U) #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ #define RCC_APB2RSTR_IOPCRST_Pos (4U) #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ #define RCC_APB2RSTR_IOPDRST_Pos (5U) #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ #define RCC_APB2RSTR_ADC1RST_Pos (9U) #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ #define RCC_APB2RSTR_ADC2RST_Pos (10U) #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ #define RCC_APB1RSTR_BKPRST_Pos (27U) #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ #define RCC_APB1RSTR_TIM4RST_Pos (2U) #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ /****************** Bit definition for RCC_AHBENR register ******************/ #define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ #define RCC_AHBENR_SRAMEN_Pos (2U) #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ #define RCC_AHBENR_FLITFEN_Pos (4U) #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ #define RCC_AHBENR_CRCEN_Pos (6U) #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ /****************** Bit definition for RCC_APB2ENR register *****************/ #define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ #define RCC_APB2ENR_IOPAEN_Pos (2U) #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ #define RCC_APB2ENR_IOPBEN_Pos (3U) #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ #define RCC_APB2ENR_IOPCEN_Pos (4U) #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ #define RCC_APB2ENR_IOPDEN_Pos (5U) #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ #define RCC_APB2ENR_ADC1EN_Pos (9U) #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ #define RCC_APB2ENR_ADC2EN_Pos (10U) #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ #define RCC_APB2ENR_TIM1EN_Pos (11U) #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ #define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ #define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ #define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ #define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ #define RCC_APB1ENR_TIM3EN_Pos (1U) #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ #define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ #define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ #define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ #define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ #define RCC_APB1ENR_BKPEN_Pos (27U) #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ #define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ #define RCC_APB1ENR_TIM4EN_Pos (2U) #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ #define RCC_APB1ENR_SPI2EN_Pos (14U) #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ #define RCC_APB1ENR_USART3EN_Pos (18U) #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ #define RCC_APB1ENR_I2C2EN_Pos (22U) #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ #define RCC_APB1ENR_USBEN_Pos (23U) #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ /******************* Bit definition for RCC_BDCR register *******************/ #define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ #define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ #define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ #define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ #define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ /******************* Bit definition for RCC_CSR register ********************/ #define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ #define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ #define RCC_CSR_RMVF_Pos (24U) #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ #define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ #define RCC_CSR_PORRSTF_Pos (27U) #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ #define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ #define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ #define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ /* */ /******************************************************************************/ /******************* Bit definition for GPIO_CRL register *******************/ #define GPIO_CRL_MODE_Pos (0U) #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ #define GPIO_CRL_MODE0_Pos (0U) #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ #define GPIO_CRL_MODE1_Pos (4U) #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ #define GPIO_CRL_MODE2_Pos (8U) #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ #define GPIO_CRL_MODE3_Pos (12U) #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ #define GPIO_CRL_MODE4_Pos (16U) #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ #define GPIO_CRL_MODE5_Pos (20U) #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ #define GPIO_CRL_MODE6_Pos (24U) #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ #define GPIO_CRL_MODE7_Pos (28U) #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ #define GPIO_CRL_CNF_Pos (2U) #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ #define GPIO_CRL_CNF0_Pos (2U) #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ #define GPIO_CRL_CNF1_Pos (6U) #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ #define GPIO_CRL_CNF2_Pos (10U) #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ #define GPIO_CRL_CNF3_Pos (14U) #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ #define GPIO_CRL_CNF4_Pos (18U) #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ #define GPIO_CRL_CNF5_Pos (22U) #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ #define GPIO_CRL_CNF6_Pos (26U) #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ #define GPIO_CRL_CNF7_Pos (30U) #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_CRH register *******************/ #define GPIO_CRH_MODE_Pos (0U) #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ #define GPIO_CRH_MODE8_Pos (0U) #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ #define GPIO_CRH_MODE9_Pos (4U) #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ #define GPIO_CRH_MODE10_Pos (8U) #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ #define GPIO_CRH_MODE11_Pos (12U) #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ #define GPIO_CRH_MODE12_Pos (16U) #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ #define GPIO_CRH_MODE13_Pos (20U) #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ #define GPIO_CRH_MODE14_Pos (24U) #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ #define GPIO_CRH_MODE15_Pos (28U) #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ #define GPIO_CRH_CNF_Pos (2U) #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ #define GPIO_CRH_CNF8_Pos (2U) #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ #define GPIO_CRH_CNF9_Pos (6U) #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ #define GPIO_CRH_CNF10_Pos (10U) #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ #define GPIO_CRH_CNF11_Pos (14U) #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ #define GPIO_CRH_CNF12_Pos (18U) #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ #define GPIO_CRH_CNF13_Pos (22U) #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ #define GPIO_CRH_CNF14_Pos (26U) #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ #define GPIO_CRH_CNF15_Pos (30U) #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ /*!<****************** Bit definition for GPIO_IDR register *******************/ #define GPIO_IDR_IDR0_Pos (0U) #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ #define GPIO_IDR_IDR1_Pos (1U) #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ #define GPIO_IDR_IDR2_Pos (2U) #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ #define GPIO_IDR_IDR3_Pos (3U) #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ #define GPIO_IDR_IDR4_Pos (4U) #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ #define GPIO_IDR_IDR5_Pos (5U) #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ #define GPIO_IDR_IDR6_Pos (6U) #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ #define GPIO_IDR_IDR7_Pos (7U) #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ #define GPIO_IDR_IDR8_Pos (8U) #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ #define GPIO_IDR_IDR9_Pos (9U) #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ #define GPIO_IDR_IDR10_Pos (10U) #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ #define GPIO_IDR_IDR11_Pos (11U) #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ #define GPIO_IDR_IDR12_Pos (12U) #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ #define GPIO_IDR_IDR13_Pos (13U) #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ #define GPIO_IDR_IDR14_Pos (14U) #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ #define GPIO_IDR_IDR15_Pos (15U) #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_ODR register *******************/ #define GPIO_ODR_ODR0_Pos (0U) #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ #define GPIO_ODR_ODR1_Pos (1U) #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ #define GPIO_ODR_ODR2_Pos (2U) #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ #define GPIO_ODR_ODR3_Pos (3U) #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ #define GPIO_ODR_ODR4_Pos (4U) #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ #define GPIO_ODR_ODR5_Pos (5U) #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ #define GPIO_ODR_ODR6_Pos (6U) #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ #define GPIO_ODR_ODR7_Pos (7U) #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ #define GPIO_ODR_ODR8_Pos (8U) #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ #define GPIO_ODR_ODR9_Pos (9U) #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ #define GPIO_ODR_ODR10_Pos (10U) #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ #define GPIO_ODR_ODR11_Pos (11U) #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ #define GPIO_ODR_ODR12_Pos (12U) #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ #define GPIO_ODR_ODR13_Pos (13U) #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ #define GPIO_ODR_ODR14_Pos (14U) #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ #define GPIO_ODR_ODR15_Pos (15U) #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_BSRR register *******************/ #define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ #define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ #define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ #define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ #define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ #define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ #define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ #define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ #define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ #define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ #define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ #define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ #define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ #define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ #define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ #define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ #define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_BRR register *******************/ #define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_LCKR register *******************/ #define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ #define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ #define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ #define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ #define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ #define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ #define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ #define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ #define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ #define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ #define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ #define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ #define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ #define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ #define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ #define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ #define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_EVCR register *******************/ #define AFIO_EVCR_PIN_Pos (0U) #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ #define AFIO_EVCR_PIN_PX2_Pos (1U) #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ #define AFIO_EVCR_PIN_PX3_Pos (0U) #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ #define AFIO_EVCR_PIN_PX4_Pos (2U) #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ #define AFIO_EVCR_PIN_PX5_Pos (0U) #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ #define AFIO_EVCR_PIN_PX6_Pos (1U) #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ #define AFIO_EVCR_PIN_PX7_Pos (0U) #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ #define AFIO_EVCR_PIN_PX8_Pos (3U) #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ #define AFIO_EVCR_PIN_PX9_Pos (0U) #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ #define AFIO_EVCR_PIN_PX10_Pos (1U) #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ #define AFIO_EVCR_PIN_PX11_Pos (0U) #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ #define AFIO_EVCR_PIN_PX12_Pos (2U) #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ #define AFIO_EVCR_PIN_PX13_Pos (0U) #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ #define AFIO_EVCR_PIN_PX14_Pos (1U) #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ #define AFIO_EVCR_PIN_PX15_Pos (0U) #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ #define AFIO_EVCR_PORT_Pos (4U) #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ #define AFIO_EVCR_PORT_PC_Pos (5U) #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ #define AFIO_EVCR_PORT_PD_Pos (4U) #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ #define AFIO_EVCR_PORT_PE_Pos (6U) #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ #define AFIO_EVCR_EVOE_Pos (7U) #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ /****************** Bit definition for AFIO_MAPR register *******************/ #define AFIO_MAPR_SPI1_REMAP_Pos (0U) #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ #define AFIO_MAPR_I2C1_REMAP_Pos (1U) #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ #define AFIO_MAPR_USART1_REMAP_Pos (2U) #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ #define AFIO_MAPR_USART2_REMAP_Pos (3U) #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ #define AFIO_MAPR_USART3_REMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ #define AFIO_MAPR_TIM1_REMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ #define AFIO_MAPR_TIM2_REMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ #define AFIO_MAPR_TIM3_REMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ #define AFIO_MAPR_TIM4_REMAP_Pos (12U) #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ #define AFIO_MAPR_CAN_REMAP_Pos (13U) #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ /*!< CAN_REMAP configuration */ #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ #define AFIO_MAPR_PD01_REMAP_Pos (15U) #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ /*!< SWJ_CFG configuration */ #define AFIO_MAPR_SWJ_CFG_Pos (24U) #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTICR1 register *****************/ #define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ #define AFIO_EXTICR1_EXTI1_Pos (4U) #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ #define AFIO_EXTICR1_EXTI2_Pos (8U) #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ #define AFIO_EXTICR1_EXTI3_Pos (12U) #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTICR2 register *****************/ #define AFIO_EXTICR2_EXTI4_Pos (0U) #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ #define AFIO_EXTICR2_EXTI5_Pos (4U) #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ #define AFIO_EXTICR2_EXTI6_Pos (8U) #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ #define AFIO_EXTICR2_EXTI7_Pos (12U) #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTICR3 register *****************/ #define AFIO_EXTICR3_EXTI8_Pos (0U) #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ #define AFIO_EXTICR3_EXTI9_Pos (4U) #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ #define AFIO_EXTICR3_EXTI10_Pos (8U) #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ #define AFIO_EXTICR3_EXTI11_Pos (12U) #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTICR4 register *****************/ #define AFIO_EXTICR4_EXTI12_Pos (0U) #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ #define AFIO_EXTICR4_EXTI13_Pos (4U) #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ #define AFIO_EXTICR4_EXTI14_Pos (8U) #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ #define AFIO_EXTICR4_EXTI15_Pos (12U) #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ /****************** Bit definition for AFIO_MAPR2 register ******************/ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ #define EXTI_IMR_MR0_Pos (0U) #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ #define EXTI_IMR_MR1_Pos (1U) #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ #define EXTI_IMR_MR2_Pos (2U) #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ #define EXTI_IMR_MR3_Pos (3U) #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ #define EXTI_IMR_MR4_Pos (4U) #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ #define EXTI_IMR_MR5_Pos (5U) #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ #define EXTI_IMR_MR6_Pos (6U) #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ #define EXTI_IMR_MR7_Pos (7U) #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ #define EXTI_IMR_MR8_Pos (8U) #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ #define EXTI_IMR_MR9_Pos (9U) #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ #define EXTI_IMR_MR10_Pos (10U) #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ #define EXTI_IMR_MR11_Pos (11U) #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ #define EXTI_IMR_MR12_Pos (12U) #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ #define EXTI_IMR_MR13_Pos (13U) #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ #define EXTI_IMR_MR14_Pos (14U) #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ #define EXTI_IMR_MR15_Pos (15U) #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ #define EXTI_IMR_MR16_Pos (16U) #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ #define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 #define EXTI_IMR_IM1 EXTI_IMR_MR1 #define EXTI_IMR_IM2 EXTI_IMR_MR2 #define EXTI_IMR_IM3 EXTI_IMR_MR3 #define EXTI_IMR_IM4 EXTI_IMR_MR4 #define EXTI_IMR_IM5 EXTI_IMR_MR5 #define EXTI_IMR_IM6 EXTI_IMR_MR6 #define EXTI_IMR_IM7 EXTI_IMR_MR7 #define EXTI_IMR_IM8 EXTI_IMR_MR8 #define EXTI_IMR_IM9 EXTI_IMR_MR9 #define EXTI_IMR_IM10 EXTI_IMR_MR10 #define EXTI_IMR_IM11 EXTI_IMR_MR11 #define EXTI_IMR_IM12 EXTI_IMR_MR12 #define EXTI_IMR_IM13 EXTI_IMR_MR13 #define EXTI_IMR_IM14 EXTI_IMR_MR14 #define EXTI_IMR_IM15 EXTI_IMR_MR15 #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ #define EXTI_EMR_MR1_Pos (1U) #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ #define EXTI_EMR_MR2_Pos (2U) #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ #define EXTI_EMR_MR3_Pos (3U) #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ #define EXTI_EMR_MR4_Pos (4U) #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ #define EXTI_EMR_MR5_Pos (5U) #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ #define EXTI_EMR_MR6_Pos (6U) #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ #define EXTI_EMR_MR7_Pos (7U) #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ #define EXTI_EMR_MR8_Pos (8U) #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ #define EXTI_EMR_MR9_Pos (9U) #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ #define EXTI_EMR_MR10_Pos (10U) #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ #define EXTI_EMR_MR11_Pos (11U) #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ #define EXTI_EMR_MR12_Pos (12U) #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ #define EXTI_EMR_MR13_Pos (13U) #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ #define EXTI_EMR_MR14_Pos (14U) #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ #define EXTI_EMR_MR15_Pos (15U) #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ #define EXTI_EMR_MR16_Pos (16U) #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ #define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ #define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 #define EXTI_EMR_EM1 EXTI_EMR_MR1 #define EXTI_EMR_EM2 EXTI_EMR_MR2 #define EXTI_EMR_EM3 EXTI_EMR_MR3 #define EXTI_EMR_EM4 EXTI_EMR_MR4 #define EXTI_EMR_EM5 EXTI_EMR_MR5 #define EXTI_EMR_EM6 EXTI_EMR_MR6 #define EXTI_EMR_EM7 EXTI_EMR_MR7 #define EXTI_EMR_EM8 EXTI_EMR_MR8 #define EXTI_EMR_EM9 EXTI_EMR_MR9 #define EXTI_EMR_EM10 EXTI_EMR_MR10 #define EXTI_EMR_EM11 EXTI_EMR_MR11 #define EXTI_EMR_EM12 EXTI_EMR_MR12 #define EXTI_EMR_EM13 EXTI_EMR_MR13 #define EXTI_EMR_EM14 EXTI_EMR_MR14 #define EXTI_EMR_EM15 EXTI_EMR_MR15 #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR1_Pos (1U) #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ #define EXTI_RTSR_TR2_Pos (2U) #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ #define EXTI_RTSR_TR3_Pos (3U) #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ #define EXTI_RTSR_TR4_Pos (4U) #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ #define EXTI_RTSR_TR5_Pos (5U) #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ #define EXTI_RTSR_TR6_Pos (6U) #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ #define EXTI_RTSR_TR7_Pos (7U) #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ #define EXTI_RTSR_TR8_Pos (8U) #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ #define EXTI_RTSR_TR9_Pos (9U) #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ #define EXTI_RTSR_TR10_Pos (10U) #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ #define EXTI_RTSR_TR11_Pos (11U) #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ #define EXTI_RTSR_TR12_Pos (12U) #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ #define EXTI_RTSR_TR13_Pos (13U) #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ #define EXTI_RTSR_TR14_Pos (14U) #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ #define EXTI_RTSR_TR15_Pos (15U) #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16_Pos (16U) #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR1_Pos (1U) #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ #define EXTI_FTSR_TR2_Pos (2U) #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ #define EXTI_FTSR_TR3_Pos (3U) #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ #define EXTI_FTSR_TR4_Pos (4U) #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ #define EXTI_FTSR_TR5_Pos (5U) #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ #define EXTI_FTSR_TR6_Pos (6U) #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ #define EXTI_FTSR_TR7_Pos (7U) #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ #define EXTI_FTSR_TR8_Pos (8U) #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ #define EXTI_FTSR_TR9_Pos (9U) #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ #define EXTI_FTSR_TR10_Pos (10U) #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ #define EXTI_FTSR_TR11_Pos (11U) #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ #define EXTI_FTSR_TR12_Pos (12U) #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ #define EXTI_FTSR_TR13_Pos (13U) #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ #define EXTI_FTSR_TR14_Pos (14U) #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ #define EXTI_FTSR_TR15_Pos (15U) #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16_Pos (16U) #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER1_Pos (1U) #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ #define EXTI_SWIER_SWIER2_Pos (2U) #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ #define EXTI_SWIER_SWIER3_Pos (3U) #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ #define EXTI_SWIER_SWIER4_Pos (4U) #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ #define EXTI_SWIER_SWIER5_Pos (5U) #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ #define EXTI_SWIER_SWIER6_Pos (6U) #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ #define EXTI_SWIER_SWIER7_Pos (7U) #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ #define EXTI_SWIER_SWIER8_Pos (8U) #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ #define EXTI_SWIER_SWIER9_Pos (9U) #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ #define EXTI_SWIER_SWIER10_Pos (10U) #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ #define EXTI_SWIER_SWIER11_Pos (11U) #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ #define EXTI_SWIER_SWIER12_Pos (12U) #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ #define EXTI_SWIER_SWIER13_Pos (13U) #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ #define EXTI_SWIER_SWIER14_Pos (14U) #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ #define EXTI_SWIER_SWIER15_Pos (15U) #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16_Pos (16U) #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ #define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ #define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ #define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ #define EXTI_PR_PR4_Pos (4U) #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ #define EXTI_PR_PR5_Pos (5U) #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ #define EXTI_PR_PR6_Pos (6U) #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ #define EXTI_PR_PR7_Pos (7U) #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ #define EXTI_PR_PR8_Pos (8U) #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ #define EXTI_PR_PR9_Pos (9U) #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ #define EXTI_PR_PR10_Pos (10U) #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ #define EXTI_PR_PR11_Pos (11U) #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ #define EXTI_PR_PR12_Pos (12U) #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ #define EXTI_PR_PR13_Pos (13U) #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ #define EXTI_PR_PR14_Pos (14U) #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ #define EXTI_PR_PR15_Pos (15U) #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ #define EXTI_PR_PR16_Pos (16U) #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ #define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ #define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 #define EXTI_PR_PIF1 EXTI_PR_PR1 #define EXTI_PR_PIF2 EXTI_PR_PR2 #define EXTI_PR_PIF3 EXTI_PR_PR3 #define EXTI_PR_PIF4 EXTI_PR_PR4 #define EXTI_PR_PIF5 EXTI_PR_PR5 #define EXTI_PR_PIF6 EXTI_PR_PR6 #define EXTI_PR_PIF7 EXTI_PR_PR7 #define EXTI_PR_PIF8 EXTI_PR_PR8 #define EXTI_PR_PIF9 EXTI_PR_PR9 #define EXTI_PR_PIF10 EXTI_PR_PR10 #define EXTI_PR_PIF11 EXTI_PR_PR11 #define EXTI_PR_PIF12 EXTI_PR_PR12 #define EXTI_PR_PIF13 EXTI_PR_PR13 #define EXTI_PR_PIF14 EXTI_PR_PR14 #define EXTI_PR_PIF15 EXTI_PR_PR15 #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 #define EXTI_PR_PIF18 EXTI_PR_PR18 /******************************************************************************/ /* */ /* DMA Controller */ /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ #define DMA_ISR_GIF1_Pos (0U) #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ #define DMA_ISR_TCIF1_Pos (1U) #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ #define DMA_ISR_HTIF1_Pos (2U) #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ #define DMA_ISR_TEIF1_Pos (3U) #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ #define DMA_ISR_GIF2_Pos (4U) #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ #define DMA_ISR_TCIF2_Pos (5U) #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ #define DMA_ISR_HTIF2_Pos (6U) #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ #define DMA_ISR_TEIF2_Pos (7U) #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ #define DMA_ISR_GIF3_Pos (8U) #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ #define DMA_ISR_TCIF3_Pos (9U) #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ #define DMA_ISR_HTIF3_Pos (10U) #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ #define DMA_ISR_TEIF3_Pos (11U) #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ #define DMA_ISR_GIF4_Pos (12U) #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ #define DMA_ISR_TCIF4_Pos (13U) #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ #define DMA_ISR_HTIF4_Pos (14U) #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ #define DMA_ISR_TEIF4_Pos (15U) #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ #define DMA_ISR_GIF5_Pos (16U) #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ #define DMA_ISR_TCIF5_Pos (17U) #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ #define DMA_ISR_HTIF5_Pos (18U) #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ #define DMA_ISR_TEIF5_Pos (19U) #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ #define DMA_ISR_GIF6_Pos (20U) #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ #define DMA_ISR_TCIF6_Pos (21U) #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ #define DMA_ISR_HTIF6_Pos (22U) #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ #define DMA_ISR_TEIF6_Pos (23U) #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ #define DMA_ISR_GIF7_Pos (24U) #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ #define DMA_ISR_TCIF7_Pos (25U) #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ #define DMA_ISR_HTIF7_Pos (26U) #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ #define DMA_ISR_TEIF7_Pos (27U) #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ #define DMA_IFCR_CGIF1_Pos (0U) #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ #define DMA_IFCR_CTCIF1_Pos (1U) #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ #define DMA_IFCR_CHTIF1_Pos (2U) #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ #define DMA_IFCR_CTEIF1_Pos (3U) #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ #define DMA_IFCR_CGIF2_Pos (4U) #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ #define DMA_IFCR_CTCIF2_Pos (5U) #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ #define DMA_IFCR_CHTIF2_Pos (6U) #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ #define DMA_IFCR_CTEIF2_Pos (7U) #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ #define DMA_IFCR_CGIF3_Pos (8U) #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ #define DMA_IFCR_CTCIF3_Pos (9U) #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ #define DMA_IFCR_CHTIF3_Pos (10U) #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ #define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ #define DMA_IFCR_CGIF4_Pos (12U) #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ #define DMA_IFCR_CTCIF4_Pos (13U) #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ #define DMA_IFCR_CHTIF4_Pos (14U) #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ #define DMA_IFCR_CTEIF4_Pos (15U) #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ #define DMA_IFCR_CGIF5_Pos (16U) #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ #define DMA_IFCR_CTCIF5_Pos (17U) #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ #define DMA_IFCR_CHTIF5_Pos (18U) #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ #define DMA_IFCR_CTEIF5_Pos (19U) #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ #define DMA_IFCR_CGIF6_Pos (20U) #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ #define DMA_IFCR_CTCIF6_Pos (21U) #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ #define DMA_IFCR_CHTIF6_Pos (22U) #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ #define DMA_IFCR_CTEIF6_Pos (23U) #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ #define DMA_IFCR_CGIF7_Pos (24U) #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ #define DMA_IFCR_CTCIF7_Pos (25U) #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ #define DMA_IFCR_CHTIF7_Pos (26U) #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ #define DMA_IFCR_CTEIF7_Pos (27U) #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register *******************/ #define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ #define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ #define DMA_CCR_HTIE_Pos (2U) #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ #define DMA_CCR_TEIE_Pos (3U) #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ #define DMA_CCR_DIR_Pos (4U) #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ #define DMA_CCR_CIRC_Pos (5U) #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ #define DMA_CCR_PINC_Pos (6U) #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ #define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ #define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ #define DMA_CCR_MSIZE_Pos (10U) #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ #define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ #define DMA_CCR_MEM2MEM_Pos (14U) #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register ******************/ #define DMA_CNDTR_NDT_Pos (0U) #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register *******************/ #define DMA_CPAR_PA_Pos (0U) #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register *******************/ #define DMA_CMAR_MA_Pos (0U) #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_SR_EOS_Pos (1U) #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_SR_JEOS_Pos (2U) #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ #define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ /* Legacy defines */ #define ADC_SR_EOC (ADC_SR_EOS) #define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ #define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ #define ADC_CR1_EOSIE_Pos (5U) #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_CR1_JEOSIE_Pos (7U) #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ #define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ #define ADC_CR1_DUALMOD_Pos (16U) #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ #define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ /* Legacy defines */ #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) /******************* Bit definition for ADC_CR2 register ********************/ #define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ #define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CR2_CAL_Pos (2U) #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ #define ADC_CR2_RSTCAL_Pos (3U) #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ #define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ #define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CR2_JEXTSEL_Pos (12U) #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ #define ADC_CR2_JEXTTRIG_Pos (15U) #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ #define ADC_CR2_EXTSEL_Pos (17U) #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ #define ADC_CR2_EXTTRIG_Pos (20U) #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ #define ADC_CR2_JSWSTART_Pos (21U) #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR2_SWSTART_Pos (22U) #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR2_TSVREFE_Pos (23U) #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /****************** Bit definition for ADC_SMPR1 register *******************/ #define ADC_SMPR1_SMP10_Pos (0U) #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP11_Pos (3U) #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP12_Pos (6U) #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP13_Pos (9U) #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP14_Pos (12U) #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP15_Pos (15U) #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP16_Pos (18U) #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP17_Pos (21U) #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ #define ADC_SMPR2_SMP0_Pos (0U) #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP1_Pos (3U) #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP2_Pos (6U) #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP3_Pos (9U) #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP4_Pos (12U) #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP5_Pos (15U) #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP6_Pos (18U) #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP7_Pos (21U) #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP8_Pos (24U) #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP9_Pos (27U) #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ #define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ #define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ #define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ #define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ #define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ13_Pos (0U) #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ #define ADC_SQR1_SQ14_Pos (5U) #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ15_Pos (10U) #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ16_Pos (15U) #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ #define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ #define ADC_SQR2_SQ7_Pos (0U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ8_Pos (5U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ9_Pos (10U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ10_Pos (15U) #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ11_Pos (20U) #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ12_Pos (25U) #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ #define ADC_SQR3_SQ1_Pos (0U) #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ2_Pos (5U) #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ3_Pos (10U) #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ4_Pos (15U) #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ5_Pos (20U) #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ6_Pos (25U) #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ #define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_ADC2DATA_Pos (16U) #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ /*****************************************************************************/ /* */ /* Timers (TIM) */ /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ #define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2017 STMicroelectronics. * All rights reserved.
* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f1xx * @{ */ #ifndef __STM32F1XX_H #define __STM32F1XX_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /** * @brief STM32 Family */ #if !defined(STM32F1) #define STM32F1 #endif /* STM32F1 */ /* Uncomment the line below according to the target STM32L device used in your application */ #if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \ && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC) /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined(USE_HAL_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ /** * @brief CMSIS Device version number V4.3.2 */ #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC)) /** * @} */ /** @addtogroup Device_Included * @{ */ #if defined(STM32F100xB) #include "stm32f100xb.h" #elif defined(STM32F100xE) #include "stm32f100xe.h" #elif defined(STM32F101x6) #include "stm32f101x6.h" #elif defined(STM32F101xB) #include "stm32f101xb.h" #elif defined(STM32F101xE) #include "stm32f101xe.h" #elif defined(STM32F101xG) #include "stm32f101xg.h" #elif defined(STM32F102x6) #include "stm32f102x6.h" #elif defined(STM32F102xB) #include "stm32f102xb.h" #elif defined(STM32F103x6) #include "stm32f103x6.h" #elif defined(STM32F103xB) #include "stm32f103xb.h" #elif defined(STM32F103xE) #include "stm32f103xe.h" #elif defined(STM32F103xG) #include "stm32f103xg.h" #elif defined(STM32F105xC) #include "stm32f105xc.h" #elif defined(STM32F107xC) #include "stm32f107xc.h" #else #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" #endif /** * @} */ /** @addtogroup Exported_types * @{ */ typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum { SUCCESS = 0U, ERROR = !SUCCESS } ErrorStatus; /** * @} */ /** @addtogroup Exported_macros * @{ */ #define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT)) #define CLEAR_REG(REG) ((REG) = (0x0)) #define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define READ_REG(REG) ((REG)) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) /** * @} */ #if defined(USE_HAL_DRIVER) #include "stm32f1xx_hal.h" #endif /* USE_HAL_DRIVER */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32F1xx_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h ================================================ /** ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F10x_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F10X_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_armcc.h ================================================ /**************************************************************************/ /** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined(__TARGET_ARCH_6_M) && (__TARGET_ARCH_6_M == 1)) || (defined(__TARGET_ARCH_6S_M) && (__TARGET_ARCH_6S_M == 1))) #define __ARM_ARCH_6M__ 1 #endif #if (defined(__TARGET_ARCH_7_M) && (__TARGET_ARCH_7_M == 1)) #define __ARM_ARCH_7M__ 1 #endif #if (defined(__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) #define __ARM_ARCH_7EM__ 1 #endif /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return (__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return (__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return (__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return (__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return (__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return (__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return (__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return (__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return (__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) register uint32_t __regfpscr __ASM("fpscr"); return (__regfpscr); #else return (0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() \ do { \ __schedule_barrier(); \ __isb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() \ do { \ __schedule_barrier(); \ __dsb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() \ do { \ __schedule_barrier(); \ __dmb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t)__ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t)__ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t)__ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t)__ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) #define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_armclang.h ================================================ /**************************************************************************/ /** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile("MRS %0, control" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile("MRS %0, control_ns" : "=r"(result)); return (result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile("MRS %0, ipsr" : "=r"(result)); return (result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile("MRS %0, apsr" : "=r"(result)); return (result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile("MRS %0, xpsr" : "=r"(result)); return (result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile("MRS %0, psp" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile("MRS %0, psp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile("MRS %0, msp" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile("MRS %0, msp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :); } #endif #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile("MRS %0, sp_ns" : "=r"(result)); return (result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile("MRS %0, primask" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, primask_ns" : "=r"(result)); return (result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); } #endif #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile("MRS %0, basepri" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); return (result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile("MRS %0, faultmask" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); return (result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, psplim" : "=r"(result)); return result; #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, msplim" : "=r"(result)); return result; #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) #define __get_FPSCR (uint32_t) __builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined(__thumb__) && !defined(__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l"(r) #define __CMSIS_GCC_USE_REG(r) "l"(r) #else #define __CMSIS_GCC_OUT_REG(r) "=r"(r) #define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF); /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF); /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t) __builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile("bkpt " #value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t) __builtin_clz #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) \ || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t) __builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t) __builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t) __builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t) __builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t) __builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t) __builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t) __builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t) __builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t) __builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t) __builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t) __builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t) __builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #define __SSAT16(ARG1, ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) #define __USAT16(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } #if 0 #define __PKHBT(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #define __PKHTB(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2)); \ else \ __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #endif #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) __STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_compiler.h ================================================ /**************************************************************************/ /** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined(__CC_ARM) #include "cmsis_armcc.h" /* * Arm Compiler 6 (armclang) */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined(__GNUC__) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined(__ICCARM__) #include /* * TI Arm Compiler */ #elif defined(__TI_ARM__) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * TASKING Compiler */ #elif defined(__TASKING__) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * COSMIC Compiler */ #elif defined(__CSMC__) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_gcc.h ================================================ /**************************************************************************/ /** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.0.4 * @date 09. April 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile("MRS %0, control" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile("MRS %0, control_ns" : "=r"(result)); return (result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile("MRS %0, ipsr" : "=r"(result)); return (result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile("MRS %0, apsr" : "=r"(result)); return (result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile("MRS %0, xpsr" : "=r"(result)); return (result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile("MRS %0, psp" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile("MRS %0, psp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile("MRS %0, msp" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile("MRS %0, msp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :); } #endif #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile("MRS %0, sp_ns" : "=r"(result)); return (result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile("MRS %0, primask" : "=r"(result)::"memory"); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, primask_ns" : "=r"(result)::"memory"); return (result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); } #endif #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile("MRS %0, basepri" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); return (result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile("MRS %0, faultmask" : "=r"(result)); return (result); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); return (result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, psplim" : "=r"(result)); return result; #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, msplim" : "=r"(result)); return result; #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); #endif } #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile("VMRS %0, fpscr" : "=r"(result)); return (result); #endif #else return (0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined(__thumb__) && !defined(__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l"(r) #define __CMSIS_GCC_RW_REG(r) "+l"(r) #define __CMSIS_GCC_USE_REG(r) "l"(r) #else #define __CMSIS_GCC_OUT_REG(r) "=r"(r) #define __CMSIS_GCC_RW_REG(r) "+r"(r) #define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile("wfi") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile("isb 0xF" ::: "memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile("dsb 0xF" ::: "memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile("dmb 0xF" ::: "memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile("bkpt " #value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t) __builtin_clz #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) \ || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr)); return (result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); return (result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); return (result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); return (result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1, ARG2) \ __extension__({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1, ARG2) \ __extension__({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(ptr) : "memory"); #endif return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(ptr) : "memory"); #endif return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldaexb %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldaexh %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("ldaex %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile("stlexb %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); return (result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile("stlexh %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); return (result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile("stlex %0, %2, %1" : "=&r"(result), "=Q"(*ptr) : "r"((uint32_t)value)); return (result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #define __SSAT16(ARG1, ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) #define __USAT16(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } #if 0 #define __PKHBT(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #define __PKHTB(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2)); \ else \ __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #endif #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) __STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_iccarm.h ================================================ /**************************************************************************/ /** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.0.7 * @date 19. June 2018 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__ == 1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__ == 1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language = save #pragma language = extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t *)(ptr); } #pragma language = restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language = save #pragma language = extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t *)(ptr) = val; ; } #pragma language = restore #define __UNALIGNED_UINT16_WRITE(PTR, VAL) __iar_uint16_write(PTR, VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language = save #pragma language = extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t *)(ptr); } #pragma language = restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language = save #pragma language = extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t *)(ptr) = val; ; } #pragma language = restore #define __UNALIGNED_UINT32_WRITE(PTR, VAL) __iar_uint32_write(PTR, VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language = save #pragma language = extended __packed struct __iar_u32 { uint32_t v; }; #pragma language = restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U))) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE) (__arm_wsr("FAULTMASK_NS", (VALUE))) #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __TZ_get_PSPLIM_NS() (0U) #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) #else #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #endif #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t)__iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r"(res)); return res; } #endif #if (!((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined(__FPU_USED) && (__FPU_USED == 1U)))) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress = Pe940 #pragma diag_suppress = Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__ == 0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r"(value) : "cc"); return (result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0" ::"r"(value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2)); } #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r"(res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" ::"r"(value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r"(res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" ::"r"(value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" ::"r"(value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM_NS" : "=r"(res)); #endif return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { #if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM_NS,%0" ::"r"(value)); #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r"(res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" ::"r"(value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("STLB %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("STLH %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("STL %1, [%0]" ::"r"(ptr), "r"(value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default = Pe940 #pragma diag_default = Pe177 #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/cmsis_version.h ================================================ /**************************************************************************/ /** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.2 * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN (5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB (1U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB) /*!< CMSIS Core(M) version number */ #endif ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************/ /** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TI_ARM__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1 : 6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1 : 8; /*!< bit: 16..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2 : 2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined(__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined(__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************/ /** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TI_ARM__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************/ /** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TI_ARM__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1 : 6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1 : 8; /*!< bit: 16..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2 : 2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1U]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return (0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/MHP30/Vendor/CMSIS/Include/tz_context.h ================================================ /****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S(void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S(TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S(TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h ================================================ /** ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32_HAL_LEGACY #define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose * @{ */ #define AES_FLAG_RDERR CRYP_FLAG_RDERR #define AES_FLAG_WRERR CRYP_FLAG_WRERR #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR /** * @} */ /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ #define ADC_RESOLUTION12b ADC_RESOLUTION_12B #define ADC_RESOLUTION10b ADC_RESOLUTION_10B #define ADC_RESOLUTION8b ADC_RESOLUTION_8B #define ADC_RESOLUTION6b ADC_RESOLUTION_6B #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV #define REGULAR_GROUP ADC_REGULAR_GROUP #define INJECTED_GROUP ADC_INJECTED_GROUP #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP #define AWD_EVENT ADC_AWD_EVENT #define AWD1_EVENT ADC_AWD1_EVENT #define AWD2_EVENT ADC_AWD2_EVENT #define AWD3_EVENT ADC_AWD3_EVENT #define OVR_EVENT ADC_OVR_EVENT #define JQOVF_EVENT ADC_JQOVF_EVENT #define ALL_CHANNELS ADC_ALL_CHANNELS #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} */ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32L0) || defined(STM32L4) #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ /* to the second dedicated IO (only for COMP2). */ #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ #if defined(COMP_CSR_LOCK) #define COMP_FLAG_LOCK COMP_CSR_LOCK #elif defined(COMP_CSR_COMP1LOCK) #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK #elif defined(COMP_CSR_COMPxLOCK) #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK #endif #if defined(STM32L4) #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #endif #if defined(STM32L0) #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #else #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #endif #endif /** * @} */ /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig /** * @} */ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE /** * @} */ /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose * @{ */ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE 0x00000000U #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #if defined(STM32G4) || defined(STM32H7) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 #define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #if defined(STM32L4) #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif #endif /* STM32L4 */ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE #define OBEX_PCROP OPTIONBYTE_PCROP #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define PAGESIZE FLASH_PAGE_SIZE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #if defined(STM32G0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #if defined(STM32G4) #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ /** * @} */ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 #endif /** * @} */ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** * @} */ /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose * @{ */ #define GET_GPIO_SOURCE GPIO_GET_INDEX #define GET_GPIO_INDEX GPIO_GET_INDEX #if defined(STM32F4) #define GPIO_AF12_SDMMC GPIO_AF12_SDIO #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #endif #if defined(STM32F7) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32L4) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32H7) #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #if defined(STM32H743xx) || defined(STM32H753xx) || defined(STM32H750xx) || defined(STM32H742xx) || defined(STM32H745xx) || defined(STM32H755xx) || defined(STM32H747xx) || defined(STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ #if defined(STM32F3) /** @brief Constants defining available sources associated to external events. */ #define HRTIM_EVENTSRC_1 (0x00000000U) #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /** @brief Constants defining the events that can be selected to configure the * set/reset crossbar of a timer output */ #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /** @brief Constants defining the event filtering applied to external events * by a timer */ #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) #endif /* STM32F3 */ /** * @} */ /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose * @{ */ #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose * @{ */ #define KR_KEY_RELOAD IWDG_KEY_RELOAD #define KR_KEY_ENABLE IWDG_KEY_ENABLE #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS /** * @} */ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE /** * @} */ /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ #define NOR_StatusTypedef HAL_NOR_StatusTypeDef #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS #define NOR_ONGOING HAL_NOR_STATUS_ONGOING #define NOR_ERROR HAL_NOR_STATUS_ERROR #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT #define __NOR_WRITE NOR_WRITE #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose * @{ */ #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) #define I2S_IT_TXE I2S_IT_TXP #define I2S_IT_RXNE I2S_IT_RXP #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} */ /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose * @{ */ /* Compact Flash-ATA registers description */ #define CF_DATA ATA_DATA #define CF_SECTOR_COUNT ATA_SECTOR_COUNT #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER #define CF_CYLINDER_LOW ATA_CYLINDER_LOW #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH #define CF_CARD_HEAD ATA_CARD_HEAD #define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT /** * @} */ /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN /** * @} */ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE #if defined(STM32H7) #define SPI_FLAG_TXE SPI_FLAG_TXP #define SPI_FLAG_RXNE SPI_FLAG_RXP #define SPI_IT_TXE SPI_IT_TXP #define SPI_IT_RXNE SPI_IT_RXP #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR #define TIM_DMABase_DIER TIM_DMABASE_DIER #define TIM_DMABase_SR TIM_DMABASE_SR #define TIM_DMABase_EGR TIM_DMABASE_EGR #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 #define TIM_DMABase_CCER TIM_DMABASE_CCER #define TIM_DMABase_CNT TIM_DMABASE_CNT #define TIM_DMABase_PSC TIM_DMABASE_PSC #define TIM_DMABase_ARR TIM_DMABASE_ARR #define TIM_DMABase_RCR TIM_DMABASE_RCR #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR #define TIM_DMABase_DCR TIM_DMABASE_DCR #define TIM_DMABase_DMAR TIM_DMABASE_DMAR #define TIM_DMABase_OR1 TIM_DMABASE_OR1 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 #define TIM_DMABase_OR TIM_DMABASE_OR #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS #if defined(STM32L0) #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO #endif #if defined(STM32F3) #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif #if defined(STM32H7) #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif /** * @} */ /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose * @{ */ #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING /** * @} */ /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose * @{ */ #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 #define __DIV_LPUART UART_DIV_LPUART #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK /** * @} */ /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE #define USARTNACK_ENABLED USART_NACK_ENABLE #define USARTNACK_DISABLED USART_NACK_DISABLE /** * @} */ /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose * @{ */ #define CFR_BASE WWDG_CFR_BASE /** * @} */ /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose * @{ */ #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) #define CAN_TXSTATUS_OK ((uint8_t)0x01U) #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} */ /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ #define VLAN_TAG ETH_VLAN_TAG #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK #define ETH_MMCCR 0x00000100U #define ETH_MMCRIR 0x00000104U #define ETH_MMCTIR 0x00000108U #define ETH_MMCRIMR 0x0000010CU #define ETH_MMCTIMR 0x00000110U #define ETH_MMCTGFSCCR 0x0000014CU #define ETH_MMCTGFMSCCR 0x00000150U #define ETH_MMCTGFCR 0x00000168U #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} */ /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR #define DCMI_IT_OVF DCMI_IT_OVR #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop /** * @} */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ || defined(STM32H7) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 #define CM_RGB888 DMA2D_INPUT_RGB888 #define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 #define CM_L8 DMA2D_INPUT_L8 #define CM_AL44 DMA2D_INPUT_AL44 #define CM_AL88 DMA2D_INPUT_AL88 #define CM_L4 DMA2D_INPUT_L4 #define CM_A8 DMA2D_INPUT_A8 #define CM_A4 DMA2D_INPUT_A4 /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish /*HASH Algorithm Selection*/ #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) #else #define HAL_VREFINT_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose * @{ */ #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program /** * @} */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) \ || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #if defined(STM32G0) #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB #define PMODE_BIT_NUMBER VOS_BIT_NUMBER #define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER #define PMODE_BitNumber PMODE_BIT_NUMBER #define EWUP_BitNumber EWUP_BIT_NUMBER #define FPDS_BitNumber FPDS_BIT_NUMBER #define ODEN_BitNumber ODEN_BIT_NUMBER #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ */ #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /* Exported macros ------------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose * @{ */ #define AES_IT_CC CRYP_IT_CC #define AES_IT_ERR CRYP_IT_ERR #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} */ /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER /** * @} */ /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ #define __ADC_ENABLE __HAL_ADC_ENABLE #define __ADC_DISABLE __HAL_ADC_DISABLE #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE #define __ADC_IS_ENABLED ADC_IS_ENABLE #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR_RK ADC_JSQR_RK #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER #define __HAL_ADC_SQR1 ADC_SQR1 #define __HAL_ADC_SMPR1 ADC_SMPR1 #define __HAL_ADC_SMPR2 ADC_SMPR2 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK #define __HAL_ADC_SQR2_RK ADC_SQR2_RK #define __HAL_ADC_SQR1_RK ADC_SQR1_RK #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ /** * @} */ /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE /** * @} */ /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 /** * @} */ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32F3) #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \ : __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \ : __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \ : __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \ : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \ : __HAL_COMP_COMP7_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \ : __HAL_COMP_COMP7_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \ : __HAL_COMP_COMP7_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \ : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #if defined(STM32L0) || defined(STM32L4) /* Note: On these STM32 families, the only argument of this macro */ /* is COMP_FLAG_LOCK. */ /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ /* argument. */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) #endif /** * @} */ #if defined(STM32L0) || defined(STM32L4) /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} */ #endif /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose * @{ */ #define IS_WRPAREA IS_OB_WRPAREA #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM #define IS_TYPEERASE IS_FLASH_TYPEERASE #define IS_NBSECTORS IS_FLASH_NBSECTORS #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE /** * @} */ /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE #else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE #endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST #define __HAL_I2C_SPEED I2C_SPEED #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB #define __HAL_I2C_FREQRANGE I2C_FREQRANGE /** * @} */ /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET /** * @} */ /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \ do { \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while (0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVM_DISABLE() \ do { \ HAL_PWREx_DisablePVM1(); \ HAL_PWREx_DisablePVM2(); \ HAL_PWREx_DisablePVM3(); \ HAL_PWREx_DisablePVM4(); \ } while (0) #define __HAL_PWR_PVM_ENABLE() \ do { \ HAL_PWREx_EnablePVM1(); \ HAL_PWREx_EnablePVM2(); \ HAL_PWREx_EnablePVM3(); \ HAL_PWREx_EnablePVM4(); \ } while (0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #if defined(STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #if defined(STM32WB) #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED #define QSPI_IRQHandler QUADSPI_IRQHandler #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #if defined(STM32H7) #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #if defined(STM32L1) #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #endif /* STM32L1 */ #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #endif #if defined(STM32F7) || defined(STM32L4) #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #if defined(STM32H7) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK #define IS_RCC_HCLK_DIV IS_RCC_PCLK #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK #define RCC_IT_HSI14 RCC_IT_HSI14RDY #define RCC_IT_CSSLSE RCC_IT_LSECSS #define RCC_IT_CSSHSE RCC_IT_CSS #define RCC_PLLMUL_3 RCC_PLL_MUL3 #define RCC_PLLMUL_4 RCC_PLL_MUL4 #define RCC_PLLMUL_6 RCC_PLL_MUL6 #define RCC_PLLMUL_8 RCC_PLL_MUL8 #define RCC_PLLMUL_12 RCC_PLL_MUL12 #define RCC_PLLMUL_16 RCC_PLL_MUL16 #define RCC_PLLMUL_24 RCC_PLL_MUL24 #define RCC_PLLMUL_32 RCC_PLL_MUL32 #define RCC_PLLMUL_48 RCC_PLL_MUL48 #define RCC_PLLDIV_2 RCC_PLL_DIV2 #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 #define RCC_MCO_DIV4 RCC_MCODIV_4 #define RCC_MCO_DIV8 RCC_MCODIV_8 #define RCC_MCO_DIV16 RCC_MCODIV_16 #define RCC_MCO_DIV32 RCC_MCODIV_32 #define RCC_MCO_DIV64 RCC_MCODIV_64 #define RCC_MCO_DIV128 RCC_MCODIV_128 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE #define CR_HSION_BB RCC_CR_HSION_BB #define CR_CSSON_BB RCC_CR_CSSON_BB #define CR_PLLON_BB RCC_CR_PLLON_BB #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB #define CR_MSION_BB RCC_CR_MSION_BB #define CSR_LSION_BB RCC_CSR_LSION_BB #define CSR_LSEON_BB RCC_CSR_LSEON_BB #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB #define CR_HSEON_BB RCC_CR_HSEON_BB #define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 /** * @} */ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32G0) || defined(STM32L5) || defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #if defined(STM32F1) #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \ ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE /** * @} */ /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn #define SDMMC1_IRQHandler SDIO_IRQHandler #endif #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif #if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose * @{ */ #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED /** * @} */ /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SPI_1LINE_TX SPI_1LINE_TX #define __HAL_SPI_1LINE_RX SPI_1LINE_RX #define __HAL_SPI_RESET_CRC SPI_RESET_CRC /** * @} */ /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose * @{ */ #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT #define __USART_ENABLE __HAL_USART_ENABLE #define __USART_DISABLE __HAL_USART_DISABLE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE /** * @} */ /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose * @{ */ #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo /** * @} */ /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** * @} */ /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose * @{ */ #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA #endif /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ #if defined(STM32H7) || defined(STM32G4) || defined(STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} */ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal.h * @author MCD Application Team * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_H #define __STM32F1xx_HAL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_conf.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup HAL * @{ */ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef; /** * @} */ /* Exported types ------------------------------------------------------------*/ extern volatile uint32_t uwTick; extern uint32_t uwTickPrio; extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ */ /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode * @brief Freeze/Unfreeze Peripherals in Debug mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @{ */ /* Peripherals on APB1 */ /** * @brief TIM2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) /** * @brief TIM3 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #if defined(DBGMCU_CR_DBG_TIM4_STOP) /** * @brief TIM4 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM5_STOP) /** * @brief TIM5 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM6_STOP) /** * @brief TIM6 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM7_STOP) /** * @brief TIM7 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM12_STOP) /** * @brief TIM12 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM13_STOP) /** * @brief TIM13 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM14_STOP) /** * @brief TIM14 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #endif /** * @brief WWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) /** * @brief IWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) /** * @brief I2C1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) /** * @brief I2C2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #endif #if defined(DBGMCU_CR_DBG_CAN1_STOP) /** * @brief CAN1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #endif #if defined(DBGMCU_CR_DBG_CAN2_STOP) /** * @brief CAN2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #endif /* Peripherals on APB2 */ #if defined(DBGMCU_CR_DBG_TIM1_STOP) /** * @brief TIM1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM8_STOP) /** * @brief TIM8 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM9_STOP) /** * @brief TIM9 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM10_STOP) /** * @brief TIM10 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM11_STOP) /** * @brief TIM11 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM15_STOP) /** * @brief TIM15 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM16_STOP) /** * @brief TIM16 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM17_STOP) /** * @brief TIM17 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #endif /** * @} */ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ */ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ */ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw2(void); void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc.h * @author MCD Application Team * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_H #define __STM32F1xx_HAL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief Structure definition of ADC and regular group initialization * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of @ref ADC_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADC_Scan_mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADC_External_trigger_source_Regular */ } ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer This parameter can be a value of @ref ADC_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ } ADC_ChannelConfTypeDef; /** * @brief ADC Configuration analog watchdog definition * @note The setting of these parameters with function is conditioned to ADC state. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of @ref ADC_channels. */ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ } ADC_AnalogWDGConfTypeDef; /** * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY \ 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \ external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY \ 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \ external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** * @brief ADC handle Structure definition */ typedef struct __ADC_HandleTypeDef { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC required parameters */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (*ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (*ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ void (*MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (*MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief HAL ADC Callback ID enumeration definition */ typedef enum { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** * @brief HAL ADC Callback pointer definition */ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_Error_Code ADC Error Code * @{ */ #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ #define HAL_ADC_ERROR_INTERNAL \ 0x01U /*!< ADC IP internal error: if problem of clocking, \ enable/disable, erroneous state */ #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Data_align ADC data alignment * @{ */ #define ADC_DATAALIGN_RIGHT 0x00000000U #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} */ /** @defgroup ADC_Scan_mode ADC scan mode * @{ */ /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ /* compatibility with other STM32 devices having a sequencer with */ /* additional options. */ #define ADC_SCAN_DISABLE 0x00000000U #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} */ /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} */ /** @defgroup ADC_channels ADC channels * @{ */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ #define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3)) #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4)) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ /** * @} */ /** @defgroup ADC_sampling_times ADC sampling times * @{ */ #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1)) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2)) /*!< Sampling time 41.5 ADC clock cycles */ #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ /** * @} */ /** @defgroup ADC_regular_rank ADC rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 0x00000001U #define ADC_REGULAR_RANK_2 0x00000002U #define ADC_REGULAR_RANK_3 0x00000003U #define ADC_REGULAR_RANK_4 0x00000004U #define ADC_REGULAR_RANK_5 0x00000005U #define ADC_REGULAR_RANK_6 0x00000006U #define ADC_REGULAR_RANK_7 0x00000007U #define ADC_REGULAR_RANK_8 0x00000008U #define ADC_REGULAR_RANK_9 0x00000009U #define ADC_REGULAR_RANK_10 0x0000000AU #define ADC_REGULAR_RANK_11 0x0000000BU #define ADC_REGULAR_RANK_12 0x0000000CU #define ADC_REGULAR_RANK_13 0x0000000DU #define ADC_REGULAR_RANK_14 0x0000000EU #define ADC_REGULAR_RANK_15 0x0000000FU #define ADC_REGULAR_RANK_16 0x00000010U /** * @} */ /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE 0x00000000U #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) /** * @} */ /** @defgroup ADC_conversion_group ADC conversion group * @{ */ #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) /** * @} */ /** @defgroup ADC_Event_type ADC Event type * @{ */ #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ /** * @} */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ /** * @} */ /** @defgroup ADC_flags_definition ADC flags definition * @{ */ #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADC_Private_Constants ADC Private Constants * @{ */ /** @defgroup ADC_conversion_cycles ADC conversion cycles * @{ */ /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U /** * @} */ /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels * @{ */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0) #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) /** * @} */ /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ /** * @brief Enable the ADC peripheral * @note ADC enable requires a delay for ADC stabilization time * (refer to device datasheet, parameter tSTAB) * @note On STM32F1, if ADC is already enabled this macro trigs a conversion * SW start on regular group. * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** * @brief Disable the ADC peripheral * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected ADC's flag status. * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the ADC's pending flags * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) /** @brief Reset ADC handle state * @param __HANDLE__: ADC handle * @retval None */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do { \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while (0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) #endif /** * @} */ /* Private macro ------------------------------------------------------------*/ /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Verification of ADC state: enabled or disabled * @param __HANDLE__: ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) /** * @brief Simultaneously clears and sets specific bits of the handle State * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__: ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Set ADC number of conversions into regular channel sequence length. * @param _NbrOfConversion_: Regular channel sequence length * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13))) /** * @brief Set the injected sequence length. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos) /** * @brief Set the selected injected channel rank * Note: on STM32F1 devices, channel rank position in JSQR register * is depending on total number of ranks selected into * injected sequencer (ranks sequence starting from 4-JL) * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) /** * @brief Configures the number of discontinuous conversions for the regular group channels. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @param _SCAN_MODE_: Scan conversion mode. * @retval None */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* is equivalent to ADC_SCAN_ENABLE. */ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)) /** * @brief Get the maximum ADC conversion cycles on all channels. * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) * Approximation of sampling time within 4 ranges, returns the highest value: * below 7.5 cycles {1.5 cycle; 7.5 cycles}, * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} * equal to 239.5 cycles * Unit: ADC clock cycles * @param __HANDLE__: ADC handle * @retval ADC conversion cycles on all channels */ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)) \ ? \ \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \ || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5)) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT)) #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE)) #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)) #define IS_ADC_CHANNEL(CHANNEL) \ (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) \ || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \ || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16) \ || ((CHANNEL) == ADC_CHANNEL_17)) #define IS_ADC_SAMPLE_TIME(TIME) \ (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \ || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5)) #define IS_ADC_REGULAR_RANK(CHANNEL) \ (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5) \ || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10) \ || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \ || ((CHANNEL) == ADC_REGULAR_RANK_16)) #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) \ (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \ || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)) #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) /** @defgroup ADC_range_verification ADC range verification * For a unique ADC resolution: 12 bits * @{ */ #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) /** * @} */ /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification * @{ */ #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification * @{ */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) /** * @} */ /** * @} */ /* Include ADC HAL Extension module */ #include "stm32f1xx_hal_adc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* IO operation functions *****************************************************/ /** @addtogroup ADC_Exported_Functions_Group2 * @{ */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADC_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ /* Peripheral State functions *************************************************/ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /* Internal HAL driver functions **********************************************/ /** @addtogroup ADC_Private_Functions * @{ */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc); void ADC_StabilizationTime(uint32_t DelayUs); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_EX_H #define __STM32F1xx_HAL_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADCEx Exported Types * @{ */ /** * @brief ADC Configuration injected Channel structure definition * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. */ typedef struct { uint32_t InjectedChannel; /*!< Selection of ADC channel to configure This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t InjectedRank; /*!< Rank in the injected group sequencer This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADCEx_External_trigger_source_Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ } ADC_InjectionConfTypeDef; #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * State of ADCs of the common group must be: disabled. */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADCEx_Common_mode Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). The equivalences are: - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ } ADC_MultiModeTypeDef; #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants * @{ */ /** @defgroup ADCEx_injected_rank ADCEx rank into injected group * @{ */ #define ADC_INJECTED_RANK_1 0x00000001U #define ADC_INJECTED_RANK_2 0x00000002U #define ADC_INJECTED_RANK_3 0x00000003U #define ADC_INJECTED_RANK_4 0x00000004U /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} */ /** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #if defined(STM32F103xE) || defined(STM32F103xG) /*!< External triggers of regular group for ADC3 only */ #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of regular group for all ADC instances */ #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_TRGO with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ /* Note for internal constant value management: If TIM8_TRGO is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_SOFTWARE_START ADC1_2_3_SWSTART /** * @} */ /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of injected group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #if defined(STM32F103xE) || defined(STM32F103xG) /*!< External triggers of injected group for ADC3 only */ #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of injected group for all ADC instances */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC1 or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_CC4 with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ /* Note for internal constant value management: If TIM8_CC4 is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART /** * @} */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST \ ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \ phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW \ ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \ cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ #define ADC_DUALMODE_INTERLFAST \ ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \ (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INTERLSLOW \ ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \ "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ /** * @} */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group * @{ */ /* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)(ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2)) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 #endif #if defined(STM32F103xE) || defined(STM32F103xG) /* External triggers of regular group for ADC3 */ #define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 #endif /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1)) #define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) /** * @} */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group * @{ */ /* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif #if defined(STM32F103xE) || defined(STM32F103xG) /* External triggers of injected group for ADC3 */ #define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif /* STM32F103xE || defined STM32F103xG */ /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro ADCEx Private Macro * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for regular group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC EXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_CONV__: External trigger selected for regular group. * @retval External trigger to be programmed into EXTSEL bits of CR2 register */ #if defined(STM32F103xE) || defined(STM32F103xG) #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__)) #else #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for injected group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC JEXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. * @retval External trigger to be programmed into JEXTSEL bits of CR2 register */ #if defined(STM32F103xE) || defined(STM32F103xG) #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__)) #else #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET)) #else #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET)) #else #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET)) #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Set handle of the other ADC sharing the common multimode settings * @param __HANDLE__: ADC handle * @param __HANDLE_OTHER_ADC__: other ADC handle * @retval None */ #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2) /** * @brief Set handle of the ADC slave associated to the ADC master * On STM32F1 devices, ADC slave is always ADC2 (this can be different * on other STM32 devices) * @param __HANDLE_MASTER__: ADC master handle * @param __HANDLE_SLAVE__: ADC slave handle * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4)) #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification * @{ */ #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) /** * @} */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \ || defined(STM32F105xC) || defined(STM32F107xC) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F101xE) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F101xG) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \ || defined(STM32F105xC) || defined(STM32F107xC) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F101xE) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F101xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_MODE(MODE) \ (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \ || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST) \ || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG)) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ */ /* IO operation functions *****************************************************/ /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ */ /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_cortex.h * @author MCD Application Team * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_CORTEX_H #define __STM32F1xx_HAL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup CORTEX * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types Cortex Exported Types * @{ */ #if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ */ typedef struct { uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ } MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 \ 0x00000007U /*!< 0 bits for pre-emption priority \ 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 \ 0x00000006U /*!< 1 bits for pre-emption priority \ 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 \ 0x00000005U /*!< 2 bits for pre-emption priority \ 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 \ 0x00000004U /*!< 3 bits for pre-emption priority \ 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 \ 0x00000003U /*!< 4 bits for pre-emption priority \ 0 bits for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /** * @} */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_DISABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported Macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) \ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) #if (__MPU_PRESENT == 1U) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \ || ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) \ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \ || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) \ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) \ || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) \ || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \ || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) \ || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \ || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_CORTEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_def.h * @author MCD Application Team * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DEF #define __STM32F1xx_HAL_DEF #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "Legacy/stm32_hal_legacy.h" #include "stm32f1xx.h" #include /* Exported types ------------------------------------------------------------*/ #ifndef USE_HAL_TIM_REGISTER_CALLBACKS #define USE_HAL_TIM_REGISTER_CALLBACKS 0 #endif #ifndef USE_HAL_I2C_REGISTER_CALLBACKS #define USE_HAL_I2C_REGISTER_CALLBACKS 0 #endif #ifndef USE_HAL_ADC_REGISTER_CALLBACKS #define USE_HAL_ADC_REGISTER_CALLBACKS 0 #endif /** * @brief HAL Status structures definition */ typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** * @brief HAL Lock structures definition */ typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do { \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while (0U) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * In this later function, when the Handle's "State" field is set to 0, it will execute the function * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1U) /* Reserved for future use */ #error "USE_RTOS should be 0 in the current HAL release" #else #define __HAL_LOCK(__HANDLE__) \ do { \ if ((__HANDLE__)->Lock == HAL_LOCKED) { \ return HAL_BUSY; \ } else { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ } while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do { \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ } while (0U) #endif /* USE_RTOS */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __weak #define __weak __attribute__((weak)) #endif #ifndef __packed #define __packed __attribute__((packed)) #endif #elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif #ifndef __ALIGN_END #define __ALIGN_END __attribute__((aligned(4))) #endif #elif defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__((aligned(4))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined(__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4) #elif defined(__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** * @brief __RAM_FUNC definition */ #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler V4/V5 and V6 -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ #define __RAM_FUNC #elif defined(__ICCARM__) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc #elif defined(__GNUC__) /* GNU Compiler ------------ RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif /** * @brief __NOINLINE definition */ #if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined(__GNUC__) /* ARM V4/V5 and V6 & GNU Compiler ------------------------------- */ #define __NOINLINE __attribute__((noinline)) #elif defined(__ICCARM__) /* ICCARM Compiler --------------- */ #define __NOINLINE _Pragma("optimize = no_inline") #endif #ifdef __cplusplus } #endif #endif /* ___STM32F1xx_HAL_DEF */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma.h * @author MCD Application Team * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_H #define __STM32F1xx_HAL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ /** * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** * @brief HAL DMA State structures definition */ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ } HAL_DMA_StateTypeDef; /** * @brief HAL DMA Error Code structure definition */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ } HAL_DMA_LevelCompleteTypeDef; /** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ } HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ HAL_LockTypeDef Lock; /*!< DMA locking object */ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ uint32_t ChannelIndex; /*!< DMA Channel Index */ } DMA_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code * @{ */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} */ /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** * @} */ /** @defgroup DMA_Priority_level DMA Priority level * @{ */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) /** * @} */ /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ #define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_TE6 0x00800000U #define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_TE7 0x08000000U /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ /** @brief Reset DMA handle state. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /* Interrupt & Flag management */ /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) /** * @brief Disable the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) /** * @brief Check whether the specified DMA Channel interrupt is enabled or not. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__: DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) /** * @} */ /* Include DMA HAL Extension module */ #include "stm32f1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ */ /** @addtogroup DMA_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @{ */ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE)) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE)) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD)) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD)) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma_ex.h * @author MCD Application Team * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_EX_H #define __STM32F1xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup DMAEx DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros * @{ */ /* Interrupt & Flag management */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices * @{ */ /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TC7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 \ : DMA_FLAG_TC5) /** * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_HT7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 \ : DMA_FLAG_HT5) /** * @brief Returns the current DMA Channel transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TE7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 \ : DMA_FLAG_TE5) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_GL7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 \ : DMA_FLAG_GL5) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) /** * @brief Clears the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) /** * @} */ #else /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices * @{ */ /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \ : DMA_FLAG_TC7) /** * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \ : DMA_FLAG_HT7) /** * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \ : DMA_FLAG_TE7) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \ : DMA_FLAG_GL7) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) /** * @brief Clear the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) /** * @} */ #endif /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ /* STM32F103xG || STM32F105xC || STM32F107xC */ #endif /* __STM32F1xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_exti.h * @author MCD Application Team * @brief Header file of EXTI HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_EXTI_H #define STM32F1xx_HAL_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup EXTI EXTI * @brief EXTI HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Types EXTI Exported Types * @{ */ /** * @brief HAL EXTI common Callback ID enumeration definition */ typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00U } EXTI_CallbackIDTypeDef; /** * @brief EXTI Handle structure definition */ typedef struct { uint32_t Line; /*!< Exti line number */ void (*PendingCallback)(void); /*!< Exti pending callback */ } EXTI_HandleTypeDef; /** * @brief EXTI Configuration structure definition */ typedef struct { uint32_t Line; /*!< The Exti line to be configured. This parameter can be a value of @ref EXTI_Line */ uint32_t Mode; /*!< The Exit Mode to be configured for a core. This parameter can be a combination of @ref EXTI_Mode */ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter can be a value of @ref EXTI_Trigger */ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of @ref EXTI_GPIOSel */ } EXTI_ConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants EXTI Exported Constants * @{ */ /** @defgroup EXTI_Line EXTI Line * @{ */ #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #if defined(EXTI_IMR_IM18) #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ #endif /* EXTI_IMR_IM18 */ #if defined(EXTI_IMR_IM19) #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #endif /* EXTI_IMR_IM19 */ /** * @} */ /** @defgroup EXTI_Mode EXTI Mode * @{ */ #define EXTI_MODE_NONE 0x00000000u #define EXTI_MODE_INTERRUPT 0x00000001u #define EXTI_MODE_EVENT 0x00000002u /** * @} */ /** @defgroup EXTI_Trigger EXTI Trigger * @{ */ #define EXTI_TRIGGER_NONE 0x00000000u #define EXTI_TRIGGER_RISING 0x00000001u #define EXTI_TRIGGER_FALLING 0x00000002u #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @} */ /** @defgroup EXTI_GPIOSel EXTI GPIOSel * @brief * @{ */ #define EXTI_GPIOA 0x00000000u #define EXTI_GPIOB 0x00000001u #define EXTI_GPIOC 0x00000002u #define EXTI_GPIOD 0x00000003u #if defined(GPIOE) #define EXTI_GPIOE 0x00000004u #endif /* GPIOE */ #if defined(GPIOF) #define EXTI_GPIOF 0x00000005u #endif /* GPIOF */ #if defined(GPIOG) #define EXTI_GPIOG 0x00000006u #endif /* GPIOG */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Macros EXTI Exported Macros * @{ */ /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ /** * @brief EXTI Line property definition */ #define EXTI_PROPERTY_SHIFT 24u #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI bit usage */ #define EXTI_PIN_MASK 0x0000001Fu /** * @brief EXTI Mask for interrupt & event mode */ #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) /** * @brief EXTI Mask for trigger possibilities */ #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @brief EXTI Line number */ #if defined(EXTI_IMR_IM19) #define EXTI_LINE_NB 20UL #elif defined(EXTI_IMR_IM18) #define EXTI_LINE_NB 19UL #else /* EXTI_IMR_IM17 */ #define EXTI_LINE_NB 18UL #endif /* EXTI_IMR_IM19 */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ #define IS_EXTI_LINE(__LINE__) \ ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && ((((__LINE__)&EXTI_PROPERTY_MASK) == EXTI_CONFIG) || (((__LINE__)&EXTI_PROPERTY_MASK) == EXTI_GPIO)) \ && (((__LINE__)&EXTI_PIN_MASK) < EXTI_LINE_NB)) #define IS_EXTI_MODE(__LINE__) ((((__LINE__)&EXTI_MODE_MASK) != 0x00u) && (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) #define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__)&EXTI_CONFIG) != 0x00u) #if defined(GPIOG) #define IS_EXTI_GPIO_PORT(__PORT__) \ (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF) \ || ((__PORT__) == EXTI_GPIOG)) #elif defined(GPIOF) #define IS_EXTI_GPIO_PORT(__PORT__) \ (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE) || ((__PORT__) == EXTI_GPIOF)) #elif defined(GPIOE) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD) || ((__PORT__) == EXTI_GPIOE)) #else #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || ((__PORT__) == EXTI_GPIOB) || ((__PORT__) == EXTI_GPIOC) || ((__PORT__) == EXTI_GPIOD)) #endif /* GPIOG */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Functions EXTI Exported Functions * @brief EXTI Exported Functions * @{ */ /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions * @brief Configuration functions * @{ */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** * @} */ /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_EXTI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash.h * @author MCD Application Team * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_FLASH_H #define __STM32F1xx_HAL_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Constants * @{ */ #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ /** * @} */ /** @addtogroup FLASH_Private_Macros * @{ */ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) #if defined(FLASH_ACR_LATENCY) #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2)) #else #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #endif /* FLASH_ACR_LATENCY */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ /** * @brief FLASH Procedure structure definition */ typedef enum { FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U, FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U } FLASH_ProcedureTypeDef; /** * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ HAL_LockTypeDef Lock; /*!< FLASH locking object */ __IO uint32_t ErrorCode; /*!< FLASH error code This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ /** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ */ #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ /** * @} */ /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) /** * @brief Disable the FLASH half cycle access. * @note half cycle access can only be used with a low-frequency clock of less than 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. * @retval None */ #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) /** * @} */ #if defined(FLASH_ACR_LATENCY) /** @defgroup FLASH_EM_Latency FLASH Latency * @brief macros to handle FLASH Latency * @{ */ /** * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__)) /** * @brief Get the FLASH Latency. * @retval FLASH Latency * The value of this parameter depend on device used within the same series */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** * @} */ #endif /* FLASH_ACR_LATENCY */ /** @defgroup FLASH_Prefetch FLASH Prefetch * @brief macros to handle FLASH Prefetch buffer * @{ */ /** * @brief Enable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) /** * @brief Disable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) /** * @} */ /** * @} */ /* Include FLASH HAL Extended module */ #include "stm32f1xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler function */ void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); void HAL_FLASH_OB_Launch(void); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_FLASH_GetError(void); /** * @} */ /** * @} */ /* Private function -------------------------------------------------*/ /** @addtogroup FLASH_Private_Functions * @{ */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined(FLASH_BANK2_END) HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); #endif /* FLASH_BANK2_END */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_FLASH_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_FLASH_EX_H #define __STM32F1xx_HAL_FLASH_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup FLASHEx * @{ */ /** @addtogroup FLASHEx_Private_Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U #define OBR_REG_INDEX 1U #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) /** * @} */ /** @addtogroup FLASHEx_Private_Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) #if defined(FLASH_BANK2_END) #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) #endif /* FLASH_BANK2_END */ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU)) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU)))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU)) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU))) #endif /* STM32F105xC || STM32F107xC */ #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #if defined(FLASH_BANK2_END) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH)) #else #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) #endif /* FLASH_BANK2_END */ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \ ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types * @{ */ /** * @brief FLASH Erase structure definition */ typedef struct { uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. This parameter must be a value of @ref FLASHEx_Banks */ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END (x = 1 or 2 depending on devices)*/ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ } FLASH_EraseInitTypeDef; /** * @brief FLASH Options bytes program structure definition */ typedef struct { uint32_t OptionType; /*!< OptionType: Option byte to be configured. This parameter can be a value of @ref FLASHEx_OB_Type */ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_OB_WRP_State */ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ #if defined(FLASH_BANK2_END) uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ #else uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY */ #endif /* FLASH_BANK2_END */ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of @ref FLASHEx_OB_Data_Address */ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ } FLASH_OBProgramInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ */ /** @defgroup FLASHEx_Constants FLASH Constants * @{ */ /** @defgroup FLASHEx_Page_Size Page Size * @{ */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define FLASH_PAGE_SIZE 0x400U #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) #define FLASH_PAGE_SIZE 0x800U #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup FLASHEx_Type_Erase Type Erase * @{ */ #define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__)&0x0000FFFFU)); \ /* Enable Bank2 IT */ \ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ } while (0U) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \ do { \ /* Disable Bank1 IT */ \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \ /* Disable Bank2 IT */ \ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ } while (0U) /** * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) \ (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U)))) /** * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \ do { \ /* Clear FLASH_FLAG_OPTVERR flag */ \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ } else { \ /* Clear Flag in Bank1 */ \ if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \ FLASH->SR = ((__FLAG__)&SR_FLAG_MASK); \ } \ /* Clear Flag in Bank2 */ \ if (((__FLAG__) >> 16U) != RESET) { \ FLASH->SR2 = ((__FLAG__) >> 16U); \ } \ } \ } while (0U) #else /** * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) /** * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_BSY FLASH Busy flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__))) /** * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \ do { \ /* Clear FLASH_FLAG_OPTVERR flag */ \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ } else { \ /* Clear Flag in Bank1 */ \ FLASH->SR = (__FLAG__); \ } \ } while (0U) #endif /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); /** * @} */ /** @addtogroup FLASHEx_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_FLASH_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio.h * @author MCD Application Team * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_GPIO_H #define STM32F1xx_HAL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull_define */ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ } GPIO_InitTypeDef; /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { GPIO_PIN_RESET = 0u, GPIO_PIN_SET } GPIO_PinState; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_pins_define GPIO pins define * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ /** * @} */ /** @defgroup GPIO_mode_define GPIO mode define * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode * - y : External IT or Event trigger detection * - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ /** * @} */ /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Checks whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Generates a Software interrupt on selected EXTI line. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /** * @} */ /* Include GPIO HAL Extension module */ #include "stm32f1xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions * @{ */ /** @addtogroup GPIO_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ /** @addtogroup GPIO_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) #define IS_GPIO_MODE(MODE) \ (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \ || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \ || ((MODE) == GPIO_MODE_ANALOG)) #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Functions GPIO Private Functions * @{ */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.h * @author MCD Application Team * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_GPIO_EX_H #define STM32F1xx_HAL_GPIO_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration * @brief This section propose definition to use the Cortex EVENTOUT signal. * @{ */ /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin * @{ */ #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ #define IS_AFIO_EVENTOUT_PIN(__PIN__) \ (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_15)) /** * @} */ /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port * @{ */ #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ #define IS_AFIO_EVENTOUT_PORT(__PORT__) \ (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E)) /** * @} */ /** * @} */ /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping * @brief This section propose definition to remap the alternate function to some other port/pins. * @{ */ /** * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) * @retval None */ #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) /** * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) * @retval None */ #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) /** * @brief Enable the remapping of I2C1 alternate function SCL and SDA. * @note ENABLE: Remap (SCL/PB8, SDA/PB9) * @retval None */ #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) /** * @brief Disable the remapping of I2C1 alternate function SCL and SDA. * @note DISABLE: No remap (SCL/PB6, SDA/PB7) * @retval None */ #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) /** * @brief Enable the remapping of USART1 alternate function TX and RX. * @note ENABLE: Remap (TX/PB6, RX/PB7) * @retval None */ #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) /** * @brief Disable the remapping of USART1 alternate function TX and RX. * @note DISABLE: No remap (TX/PA9, RX/PA10) * @retval None */ #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) /** * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) * @retval None */ #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) /** * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) * @retval None */ #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) * @retval None */ #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) * @retval None */ #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) * @retval None */ #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) /** * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 * @retval None */ #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) * @retval None */ #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 * @retval None */ #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) #endif /** * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. * @retval None */ #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) /** * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note DISABLE: No remapping of PD0 and PD1 * @retval None */ #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) #if defined(AFIO_MAPR_TIM5CH4_IREMAP) /** * @brief Enable the remapping of TIM5CH4. * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. * @note This function is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) /** * @brief Disable the remapping of TIM5CH4. * @note DISABLE: TIM5_CH4 is connected to PA3 * @note This function is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) #endif #if defined(AFIO_MAPR_ETH_REMAP) /** * @brief Enable the remapping of Ethernet MAC connections with the PHY. * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) /** * @brief Disable the remapping of Ethernet MAC connections with the PHY. * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) #endif #if defined(AFIO_MAPR_CAN2_REMAP) /** * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) /** * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) #endif #if defined(AFIO_MAPR_MII_RMII_SEL) /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) #endif /** * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) /** * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) /** * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) #endif #if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) #endif /** * @brief Enable the Serial wire JTAG configuration * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State * @retval None */ #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) /** * @brief Enable the Serial wire JTAG configuration * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST * @retval None */ #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) /** * @brief Enable the Serial wire JTAG configuration * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled * @retval None */ #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) /** * @brief Disable the Serial wire JTAG configuration * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled * @retval None */ #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) #if defined(AFIO_MAPR_SPI3_REMAP) /** * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) /** * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) #endif #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) /** * @brief Control of TIM2_ITR1 internal mapping. * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) /** * @brief Control of TIM2_ITR1 internal mapping. * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) #endif #if defined(AFIO_MAPR_PTP_PPS_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note ENABLE: PTP_PPS is output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note DISABLE: PTP_PPS not output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) #endif #if defined(AFIO_MAPR2_TIM9_REMAP) /** * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). * @retval None */ #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) /** * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). * @retval None */ #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) #endif #if defined(AFIO_MAPR2_TIM10_REMAP) /** * @brief Enable the remapping of TIM10_CH1. * @note ENABLE: Remap (TIM10_CH1 on PF6). * @retval None */ #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) /** * @brief Disable the remapping of TIM10_CH1. * @note DISABLE: No remap (TIM10_CH1 on PB8). * @retval None */ #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) #endif #if defined(AFIO_MAPR2_TIM11_REMAP) /** * @brief Enable the remapping of TIM11_CH1. * @note ENABLE: Remap (TIM11_CH1 on PF7). * @retval None */ #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) /** * @brief Disable the remapping of TIM11_CH1. * @note DISABLE: No remap (TIM11_CH1 on PB9). * @retval None */ #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) #endif #if defined(AFIO_MAPR2_TIM13_REMAP) /** * @brief Enable the remapping of TIM13_CH1. * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). * @retval None */ #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) /** * @brief Disable the remapping of TIM13_CH1. * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). * @retval None */ #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) #endif #if defined(AFIO_MAPR2_TIM14_REMAP) /** * @brief Enable the remapping of TIM14_CH1. * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). * @retval None */ #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) /** * @brief Disable the remapping of TIM14_CH1. * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). * @retval None */ #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) #endif #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) /** * @brief Controls the use of the optional FSMC_NADV signal. * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. * @retval None */ #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) /** * @brief Controls the use of the optional FSMC_NADV signal. * @note CONNECTED: The NADV signal is connected to the output (default). * @retval None */ #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) #endif #if defined(AFIO_MAPR2_TIM15_REMAP) /** * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). * @retval None */ #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) /** * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). * @retval None */ #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) #endif #if defined(AFIO_MAPR2_TIM16_REMAP) /** * @brief Enable the remapping of TIM16_CH1. * @note ENABLE: Remap (TIM16_CH1 on PA6). * @retval None */ #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) /** * @brief Disable the remapping of TIM16_CH1. * @note DISABLE: No remap (TIM16_CH1 on PB8). * @retval None */ #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) #endif #if defined(AFIO_MAPR2_TIM17_REMAP) /** * @brief Enable the remapping of TIM17_CH1. * @note ENABLE: Remap (TIM17_CH1 on PA7). * @retval None */ #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) /** * @brief Disable the remapping of TIM17_CH1. * @note DISABLE: No remap (TIM17_CH1 on PB9). * @retval None */ #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) #endif #if defined(AFIO_MAPR2_CEC_REMAP) /** * @brief Enable the remapping of CEC. * @note ENABLE: Remap (CEC on PB10). * @retval None */ #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) /** * @brief Disable the remapping of CEC. * @note DISABLE: No remap (CEC on PB8). * @retval None */ #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) #endif #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) * @retval None */ #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). * @retval None */ #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) #endif #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) * @retval None */ #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) * @retval None */ #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) #endif #if defined(AFIO_MAPR2_TIM12_REMAP) /** * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) /** * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) #endif #if defined(AFIO_MAPR2_MISC_REMAP) /** * @brief Miscellaneous features remapping. * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is * selected as DAC Trigger 3, TIM15 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) /** * @brief Miscellaneous features remapping. * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) #endif /** * @} */ /** * @} */ /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros * @{ */ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0uL : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : 3uL) #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0uL : ((__GPIOx__) == (GPIOB)) ? 1uL : ((__GPIOx__) == (GPIOC)) ? 2uL : ((__GPIOx__) == (GPIOD)) ? 3uL : 4uL) #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #define GPIO_GET_INDEX(__GPIOx__) \ (((__GPIOx__) == (GPIOA)) ? 0uL \ : ((__GPIOx__) == (GPIOB)) ? 1uL \ : ((__GPIOx__) == (GPIOC)) ? 2uL \ : ((__GPIOx__) == (GPIOD)) ? 3uL \ : ((__GPIOx__) == (GPIOE)) ? 4uL \ : ((__GPIOx__) == (GPIOF)) ? 5uL \ : 6uL) #endif #define AFIO_REMAP_ENABLE(REMAP_PIN) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0u) #define AFIO_REMAP_DISABLE(REMAP_PIN) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg &= ~REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0u) #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg &= ~REMAP_PIN_MASK; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0u) #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ tmpreg |= DBGAFR_SWJCFG; \ AFIO->MAPR = tmpreg; \ } while (0u) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIOEx_Exported_Functions * @{ */ /** @addtogroup GPIOEx_Exported_Functions_Group1 * @{ */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); void HAL_GPIOEx_EnableEventout(void); void HAL_GPIOEx_DisableEventout(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_GPIO_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_iwdg.h * @author MCD Application Team * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_IWDG_H #define STM32F1xx_HAL_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup IWDG IWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup IWDG_Exported_Types IWDG Exported Types * @{ */ /** * @brief IWDG Init structure definition */ typedef struct { uint32_t Prescaler; /*!< Select the prescaler of the IWDG. This parameter can be a value of @ref IWDG_Prescaler */ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ } IWDG_InitTypeDef; /** * @brief IWDG Handle Structure definition */ typedef struct { IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */ } IWDG_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Constants IWDG Exported Constants * @{ */ /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ #define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ #define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IWDG_Exported_Macros IWDG Exported Macros * @{ */ /** * @brief Enable the IWDG peripheral. * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** * @brief Reload IWDG counter with value defined in the reload register * (write access to IWDG_PR and IWDG_RLR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions * @{ */ /* Initialization/Start functions ********************************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions * @{ */ /* I/O operation functions ****************************************************/ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup IWDG_Private_Constants IWDG Private Constants * @{ */ /** * @brief IWDG Key Register BitMask */ #define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ #define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ #define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ #define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Macros IWDG Private Macros * @{ */ /** * @brief Enable write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** * @brief Disable write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Check IWDG prescaler value. * @param __PRESCALER__ IWDG prescaler value * @retval None */ #define IS_IWDG_PRESCALER(__PRESCALER__) \ (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \ || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256)) /** * @brief Check IWDG reload value. * @param __RELOAD__ IWDG reload value * @retval None */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_pwr.h * @author MCD Application Team * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PWR_H #define __STM32F1xx_HAL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ */ /** * @brief PWR PVD configuration structure definition */ typedef struct { uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode */ } PWR_PVDTypeDef; /** * @} */ /* Internal constants --------------------------------------------------------*/ /** @addtogroup PWR_Private_Constants * @{ */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ */ #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 /** * @} */ /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins * @{ */ #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP /** * @} */ /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ #define PWR_MAINREGULATOR_ON 0x00000000U #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /** * @} */ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /** * @} */ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /** * @} */ /** @defgroup PWR_Flag PWR Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Macros PWR Exported Macros * @{ */ /** @brief Check PWR flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm * An additional wakeup event is detected if the WKUP pin is enabled * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) /** * @brief Enable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Enable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) /** * @brief Disable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Rising Trigger. * This parameter can be: * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising & falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); /** * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * This parameter can be: * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /** * @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI PVD Line Status. */ #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) /** * @brief Clear the PVD EXTI flag. * @retval None. */ #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None. */ #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup PWR_Private_Macros PWR Private Macros * @{ */ #define IS_PWR_PVD_LEVEL(LEVEL) \ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \ || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) #define IS_PWR_PVD_MODE(MODE) \ (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \ || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); /** * @} */ /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); /* #define HAL_PWR_ConfigPVD 12*/ void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); /* Low Power modes configuration functions ************************************/ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVDCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_PWR_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc.h * @author MCD Application Team * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_H #define __STM32F1xx_HAL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ /** * @brief RCC PLL configuration structure definition */ typedef struct { uint32_t PLLState; /*!< PLLState: The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ } RCC_PLLInitTypeDef; /** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ } RCC_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ /** * @} */ /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE 0x00000000U #define RCC_OSCILLATORTYPE_HSE 0x00000001U #define RCC_OSCILLATORTYPE_HSI 0x00000002U #define RCC_OSCILLATORTYPE_LSE 0x00000004U #define RCC_OSCILLATORTYPE_LSI 0x00000008U /** * @} */ /** @defgroup RCC_HSE_Config HSE Config * @{ */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** * @} */ /** @defgroup RCC_LSE_Config LSE Config * @{ */ #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ /** * @} */ /** @defgroup RCC_HSI_Config HSI Config * @{ */ #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ /** * @} */ /** @defgroup RCC_LSI_Config LSI Config * @{ */ #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ /** @defgroup RCC_PLL_Config PLL Config * @{ */ #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ /** @defgroup RCC_System_Clock_Source System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ /** * @} */ /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ /** * @} */ /** @defgroup RCC_MCO_Index MCO Index * @{ */ #define RCC_MCO1 0x00000000U #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler * @{ */ #define RCC_MCODIV_1 0x00000000U /** * @} */ /** @defgroup RCC_Interrupt Interrupts * @{ */ #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register * - XXX : Register index * - 001: CR register * - 010: BDCR register * - 011: CSR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SRAM_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_FLITF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CRC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) /** * @} */ /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_WWDG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_I2C1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_BKP_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_PWR_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} */ /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_AFIO_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOA_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) /** * @} */ /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) /** * @} */ /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** * @} */ /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) /** * @} */ /** @defgroup RCC_HSI_Configuration HSI Configuration * @{ */ /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = DISABLE) /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) /** * @} */ /** @defgroup RCC_LSI_Configuration LSI Configuration * @{ */ /** @brief Macro to enable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = ENABLE) /** @brief Macro to disable the Internal Low Speed oscillator (LSI). * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. */ #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = DISABLE) /** * @} */ /** @defgroup RCC_HSE_Configuration HSE Configuration * @{ */ /** * @brief Macro to configure the External High Speed oscillator (HSE). * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON turn ON the HSE oscillator * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do { \ if ((__STATE__) == RCC_HSE_ON) { \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } else if ((__STATE__) == RCC_HSE_OFF) { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } else if ((__STATE__) == RCC_HSE_BYPASS) { \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } else { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ } while (0U) /** * @} */ /** @defgroup RCC_LSE_Configuration LSE Configuration * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ if ((__STATE__) == RCC_LSE_ON) { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } else if ((__STATE__) == RCC_LSE_OFF) { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } else if ((__STATE__) == RCC_LSE_BYPASS) { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } else { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while (0U) /** * @} */ /** @defgroup RCC_PLL_Configuration PLL Configuration * @{ */ /** @brief Macro to enable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = ENABLE) /** @brief Macro to disable the main PLL. * @note The main PLL can not be disabled if it is used as system clock source */ #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = DISABLE) /** @brief Macro to configure the main PLL clock source and multiplication factors. * @note This function must be used only when the main PLL is disabled. * * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 @if STM32F105xC * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 @elseif STM32F107xC * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 @else * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 @endif * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__))) /** @brief Get oscillator clock selected as PLL input clock * @retval The clock source used for PLL entry. The returned value can be one * of the following: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock */ #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) /** * @} */ /** @defgroup RCC_Get_Clock_source Get Clock source * @{ */ /** * @brief Macro to configure the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one * of the following: * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock */ #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) /** * @} */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config * @{ */ #if defined(RCC_CFGR_MCO_3) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source */ #else /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source */ #endif #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) /** * @} */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macro to enable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = ENABLE) /** @brief Macro to disable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = DISABLE) /** @brief Macro to force the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_BDCR register. */ #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = ENABLE) /** @brief Macros to release the Backup domain reset. */ #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = DISABLE) /** * @} */ /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** @brief Enable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) /** @brief Disable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) /** @brief Clear the RCC's interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif * @arg @ref RCC_IT_CSS Clock Security System interrupt */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif * @arg @ref RCC_IT_CSS Clock Security System interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) /** @brief Check RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. @if STM32F105xx * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. @elsif STM32F107xx * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. @endif * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. * @arg @ref RCC_FLAG_PINRST Pin reset. * @arg @ref RCC_FLAG_PORRST POR/PDR reset. * @arg @ref RCC_FLAG_SFTRST Software reset. * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. * @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK))) /** * @} */ /** * @} */ /* Include RCC HAL Extension module */ #include "stm32f1xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions * @{ */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} */ /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); void HAL_RCC_DisableCSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** * @} */ /** * @} */ /** @addtogroup RCC_Private_Constants * @{ */ /** @defgroup RCC_Timeout RCC Timeout * @{ */ /* Disable Backup domain write protection state change timeout */ #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ /* LSE state change timeout */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ /** * @} */ /** @defgroup RCC_Register_Offset Register offsets * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) #define RCC_CR_OFFSET 0x00U #define RCC_CFGR_OFFSET 0x04U #define RCC_CIR_OFFSET 0x08U #define RCC_BDCR_OFFSET 0x20U #define RCC_CSR_OFFSET 0x24U /** * @} */ /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion * @brief RCC registers bit address in the alias region * @{ */ #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) /* Alias word address of HSEON bit */ #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) /* Alias word address of CSSON bit */ #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) /* Alias word address of PLLON bit */ #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) /* Alias word address of RMVF bit */ #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) /* --- BDCR Registers ---*/ /* Alias word address of LSEON bit */ #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) /* Alias word address of LSEON bit */ #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) /* Alias word address of RTCEN bit */ #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) /* Alias word address of BDRST bit */ #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) /** * @} */ /* CR register byte 2 (Bits[23:16]) base address */ #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) /* CIR register byte 1 (Bits[15:8]) base address */ #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) /* CIR register byte 2 (Bits[23:16]) base address */ #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) /* Defines used for Flags */ #define CR_REG_INDEX ((uint8_t)1) #define BDCR_REG_INDEX ((uint8_t)2) #define CSR_REG_INDEX ((uint8_t)3) #define RCC_FLAG_MASK ((uint8_t)0x1F) /** * @} */ /** @addtogroup RCC_Private_Macros * @{ */ /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy * @{ */ #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET /** * @} */ #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \ || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON)) #define IS_RCC_CLOCKTYPE(CLK) \ ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \ || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) \ (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \ || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.h * @author MCD Application Team * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_EX_H #define __STM32F1xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup RCCEx * @{ */ /** @addtogroup RCCEx_Private_Constants * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) /* Alias word address of PLLI2SON bit */ #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) /* Alias word address of PLL2ON bit */ #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ #endif /* STM32F105xC || STM32F107xC */ #define CR_REG_INDEX ((uint8_t)1) /** * @} */ /** @addtogroup RCCEx_Private_Macros * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) #define IS_RCC_HSE_PREDIV(__DIV__) \ (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || ((__DIV__) == RCC_HSE_PREDIV_DIV5) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || ((__DIV__) == RCC_HSE_PREDIV_DIV15) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) #else #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_PLL_MUL(__MUL__) \ (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) \ || ((__MUL__) == RCC_PLL_MUL6_5)) #define IS_RCC_MCO1SOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) #else #define IS_RCC_PLL_MUL(__MUL__) \ (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) \ || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) \ || ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || ((__MUL__) == RCC_PLL_MUL16)) #define IS_RCC_MCO1SOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) #endif /* STM32F105xC || STM32F107xC*/ #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) #define IS_RCC_PLLI2S_MUL(__MUL__) \ (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || ((__MUL__) == RCC_PLLI2S_MUL12) \ || ((__MUL__) == RCC_PLLI2S_MUL13) || ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || ((__MUL__) == RCC_PLLI2S_MUL20)) #define IS_RCC_HSE_PREDIV2(__DIV__) \ (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || ((__DIV__) == RCC_HSE_PREDIV2_DIV5) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || ((__PLL__) == RCC_PLL2_ON)) #define IS_RCC_PLL2_MUL(__MUL__) \ (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) \ || ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || ((__MUL__) == RCC_PLL2_MUL20)) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \ || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #elif defined(STM32F103xE) || defined(STM32F103xG) #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \ || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) /** * @brief RCC PLL2 configuration structure definition */ typedef struct { uint32_t PLL2State; /*!< The new state of the PLL2. This parameter can be a value of @ref RCCEx_PLL2_Config */ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. This parameter can be a value of @ref RCCEx_Prediv2_Factor */ #endif /* STM32F105xC || STM32F107xC */ } RCC_PLL2InitTypeDef; #endif /* STM32F105xC || STM32F107xC */ /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t Prediv1Source; /*!< The Prediv1 source value. This parameter can be a value of @ref RCCEx_Prediv1_Source */ #endif /* STM32F105xC || STM32F107xC */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) This parameter can be a value of @ref RCCEx_Prediv1_Factor */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ #if defined(STM32F105xC) || defined(STM32F107xC) RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ #endif /* STM32F105xC || STM32F107xC */ } RCC_OscInitTypeDef; #if defined(STM32F105xC) || defined(STM32F107xC) /** * @brief RCC PLLI2S configuration structure definition */ typedef struct { uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. This parameter can be a value of @ref RCCEx_Prediv2_Factor */ #endif /* STM32F105xC || STM32F107xC */ } RCC_PLLI2SInitTypeDef; #endif /* STM32F105xC || STM32F107xC */ /** * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< specifies the RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t AdcClockSelection; /*!< ADC clock source This parameter can be a value of @ref RCCEx_ADC_Prescaler */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) uint32_t I2s2ClockSelection; /*!< I2S2 clock source This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ uint32_t I2s3ClockSelection; /*!< I2S3 clock source This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ #if defined(STM32F105xC) || defined(STM32F107xC) RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ #endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) uint32_t UsbClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Prescaler */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ } RCC_PeriphCLKInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants * @{ */ /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ #define RCC_PERIPHCLK_RTC 0x00000001U #define RCC_PERIPHCLK_ADC 0x00000002U #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PERIPHCLK_I2S2 0x00000004U #define RCC_PERIPHCLK_I2S3 0x00000008U #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PERIPHCLK_USB 0x00000010U #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler * @{ */ #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 /** * @} */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source * @{ */ #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source * @{ */ #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC #endif /* STM32F105xC || STM32F107xC */ /** * @} */ #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) /** @defgroup RCCEx_USB_Prescaler USB Prescaler * @{ */ #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U /** * @} */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_USB_Prescaler USB Prescaler * @{ */ #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U /** * @} */ /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor * @{ */ #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Prediv1_Source Prediv1 Source * @{ */ #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor * @{ */ #define RCC_HSE_PREDIV_DIV1 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 #else #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor * @{ */ #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ /** * @} */ /** @defgroup RCCEx_PLL2_Config PLL Config * @{ */ #define RCC_PLL2_NONE 0x00000000U #define RCC_PLL2_OFF 0x00000001U #define RCC_PLL2_ON 0x00000002U /** * @} */ /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor * @{ */ #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) #else #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 #endif /* STM32F105xC || STM32F107xC */ #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 #else #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) #endif /* STM32F105xC || STM32F107xC*/ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Interrupt RCCEx Interrupt * @{ */ #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) /** * @} */ /** @defgroup RCCEx_Flag RCCEx Flag * Elements values convention: 0XXYYYYYb * - YYYYY : Flag position in the register * - XX : Register index * - 01: CR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /** * @} */ #endif /* STM32F105xC || STM32F107xC*/ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ */ /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE) #define __HAL_RCC_DMA2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) #define __HAL_RCC_FSMC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_SDIO_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) #endif /* STM32F105xC || STM32F107xC*/ #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMACTX_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMACRX_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) /** * @brief Enable ETHERNET clock. */ #define __HAL_RCC_ETH_CLK_ENABLE() \ do { \ __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ } while (0U) /** * @brief Disable ETHERNET clock. */ #define __HAL_RCC_ETH_CLK_DISABLE() \ do { \ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while (0U) #endif /* STM32F107xC*/ /** * @} */ /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) #endif /* STM32F105xC || STM32F107xC*/ #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) #endif /* STM32F107xC*/ /** * @} */ /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_I2C2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM6_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM7_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM7_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CEC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #endif /* STM32F100xB || STM32F100xE */ #ifdef STM32F100xE #define __HAL_RCC_TIM5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM12_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM13_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM14_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM12_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM13_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM14_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #endif /* STM32F100xB || STM32F100xE */ #ifdef STM32F100xE #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM16_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM17_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM10_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM11_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release * @brief Force or release AHB peripheral reset. * @{ */ #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) #endif /* STM32F107xC */ #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) #endif /* STM32F107xC */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_HSE_Configuration HSE Configuration * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. */ #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) #else /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. */ #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) /** * @brief Macro to get prediv1 factor for PLL. */ #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) #else /** * @brief Macro to get prediv1 factor for PLL. */ #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration * @{ */ /** @brief Macros to enable the main PLLI2S. * @note After enabling the main PLLI2S, the application software should wait on * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can * be used as system clock source. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = ENABLE) /** @brief Macros to disable the main PLLI2S. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = DISABLE) /** @brief macros to configure the main PLLI2S multiplication factor. * @note This function must be used only when the main PLLI2S is disabled. * * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL, (__PLLI2SMUL__)) /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration * @brief Macros to configure clock source of different peripherals. * @{ */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) /** @brief Macro to configure the USB clock. * @param __USBCLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) /** @brief Macro to get the USB clock (USBCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @brief Macro to configure the USB OTSclock. * @param __USBCLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) /** @brief Macro to get the USB clock (USBCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) #endif /* STM32F105xC || STM32F107xC */ /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). * @param __ADCCLKSOURCE__ specifies the ADC clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock */ #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). * @retval The clock source can be one of the following values: * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock */ #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_HSE_Configuration * @{ */ /** * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and * then change the PREDIV2 factor. * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. */ #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) /** * @brief Macro to get prediv2 factor for PLL2 & PLL3. */ #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) /** * @} */ /** @addtogroup RCCEx_PLLI2S_Configuration * @{ */ /** @brief Macros to enable the main PLL2. * @note After enabling the main PLL2, the application software should wait on * PLL2RDY flag to be set indicating that PLL2 clock is stable and can * be used as system clock source. * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = ENABLE) /** @brief Macros to disable the main PLL2. * @note The main PLL2 can not be disabled if it is used indirectly as system clock source * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = DISABLE) /** @brief macros to configure the main PLL2 multiplication factor. * @note This function must be used only when the main PLL2 is disabled. * * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 * */ #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL, (__PLL2MUL__)) /** * @} */ /** @defgroup RCCEx_I2S_Configuration I2S Configuration * @brief Macros to configure clock source of I2S peripherals. * @{ */ /** @brief Macro to configure the I2S2 clock. * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) /** @brief Macro to get the I2S2 clock (I2S2CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) /** @brief Macro to configure the I2S3 clock. * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) /** @brief Macro to get the I2S3 clock (I2S3CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_RCC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim.h * @author MCD Application Team * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_TIM_H #define STM32F1xx_HAL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ /** * @brief TIM Time base Configuration Structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** * @brief TIM Output Compare Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; /** * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** * @brief Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode. */ } TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable * filter and polarity. */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; /** * @brief TIM Channel States definition */ typedef enum { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ } HAL_TIM_ChannelStateTypeDef; /** * @brief DMA Burst States definition */ typedef enum { HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ } HAL_TIM_DMABurstStateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) typedef struct __TIM_HandleTypeDef #else typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { TIM_TypeDef * Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef * hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (*Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (*Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ void (*IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ void (*IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ void (*OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ void (*OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ void (*PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ void (*PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ void (*OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ void (*OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ void (*Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ void (*Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ void (*HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ void (*HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ void (*PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (*PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ void (*TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (*TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ void (*IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (*IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ void (*OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ void (*PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (*PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ void (*ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ void (*CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (*CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (*BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief HAL TIM Callback ID enumeration definition */ typedef enum { HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ /** * @} */ /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ #define TIM_DMABASE_CR1 0x00000000U #define TIM_DMABASE_CR2 0x00000001U #define TIM_DMABASE_SMCR 0x00000002U #define TIM_DMABASE_DIER 0x00000003U #define TIM_DMABASE_SR 0x00000004U #define TIM_DMABASE_EGR 0x00000005U #define TIM_DMABASE_CCMR1 0x00000006U #define TIM_DMABASE_CCMR2 0x00000007U #define TIM_DMABASE_CCER 0x00000008U #define TIM_DMABASE_CNT 0x00000009U #define TIM_DMABASE_PSC 0x0000000AU #define TIM_DMABASE_ARR 0x0000000BU #define TIM_DMABASE_RCR 0x0000000CU #define TIM_DMABASE_CCR1 0x0000000DU #define TIM_DMABASE_CCR2 0x0000000EU #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U #define TIM_DMABASE_DCR 0x00000012U #define TIM_DMABASE_DMAR 0x00000013U /** * @} */ /** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ /** * @} */ /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} */ /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ /** * @} */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity * @{ */ #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ /** * @} */ /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI \ TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be \ connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI \ TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be \ connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ /** * @} */ /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ /** * @} */ /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ /** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_ENABLE \ TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event \ (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ /** * @} */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ /** * @} */ /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ /** * @} */ /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */ #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ */ /** @brief Reset TIM handle state. * @param __HANDLE__ TIM handle. * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \ do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ (__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while (0) #else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \ do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while (0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while (0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while (0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** * @brief Check whether the specified TIM interrupt source is enabled or not. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do { \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while (0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do { \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while (0) /** * @brief Get the TIM Clock Division value on runtime. * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do { \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while (0) /** * @brief Get the TIM Input Capture prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval The input capture prescaler can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \ : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \ : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \ : ((__HANDLE__)->Instance->CCR4)) /** * @brief Set the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \ : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) /** * @brief Reset the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) /** * @brief Enable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \ : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) /** * @brief Disable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ do { \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ } while (0) /** * @} */ /* End of exported macros ----------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) #define IS_TIM_DMA_BASE(__BASE__) \ (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) \ || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) \ || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) \ || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) \ (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \ || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE)) #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW)) #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || ((__STATE__) == TIM_OCIDLESTATE_RESET)) #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || ((__STATE__) == TIM_OCNIDLESTATE_RESET)) #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC)) #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8)) #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE)) #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12)) #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_ALL)) #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \ || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \ || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) \ (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \ || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \ || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE)) #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE)) #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3)) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE)) #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) \ (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) \ || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF)) #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) #define IS_TIM_SLAVE_MODE(__MODE__) \ (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) \ || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2)) #define IS_TIM_OC_MODE(__MODE__) \ (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \ || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) \ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) \ || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE)) #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) \ (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING) \ || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE)) #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) #define IS_TIM_DMA_LENGTH(__LENGTH__) \ (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \ : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \ : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) \ : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \ : (__HANDLE__)->ChannelState[3]) #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \ : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ do { \ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ } while (0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \ : (__HANDLE__)->ChannelNState[3]) #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \ : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ do { \ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ } while (0) /** * @} */ /* End of private macros -----------------------------------------------------*/ /* Include TIM HAL Extended module */ #include "stm32f1xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @{ */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @{ */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @{ */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @{ */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @{ */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @{ */ /* Timer Encoder functions ****************************************************/ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief Peripheral State functions * @{ */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim_ex.h * @author MCD Application Team * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_TIM_EX_H #define STM32F1xx_HAL_TIM_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup TIMEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ /** * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ */ /** * @} */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ /** * @} */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @{ */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @{ */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @{ */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Extended Control functions ************************************************/ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal.c * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup HAL HAL * @brief HAL module driver. * @{ */ #ifdef HAL_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ /** * @brief STM32F1xx HAL Driver version number V1.1.7 */ #define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32F1xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ #define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC)) #define IDCODE_DEVID_MASK 0x00000FFFU /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface, the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL. (+) Configure The time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. (++) Time base configuration function (HAL_InitTick ()) is called automatically at the beginning of the program after reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). (++) Source of time base is configured to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** * @brief This function is used to initialize the HAL Library; it must be the first * instruction to be executed in the main program (before to call any other * HAL function), it performs the following: * Configure the Flash prefetch. * Configures the SysTick to generate an interrupt each 1 millisecond, * which is clocked by the HSI (at this stage, the clock is not yet * configured and thus the system is running from the internal HSI at 16 MHz). * Set NVIC Group Priority to 4. * Calls the HAL_MspInit() callback function defined in user file * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization * * @note SysTick is used as time base for the HAL_Delay() function, the application * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \ defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); /* Init the low level hardware */ HAL_MspInit(); /* Return function status */ return HAL_OK; } /** * @brief This function de-Initializes common part of the HAL and stops the systick. * of time base. * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ __HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB2_FORCE_RESET(); __HAL_RCC_APB2_RELEASE_RESET(); #if defined(STM32F105xC) || defined(STM32F107xC) __HAL_RCC_AHB_FORCE_RESET(); __HAL_RCC_AHB_RELEASE_RESET(); #endif /* De-Init the low level hardware */ HAL_MspDeInit(); /* Return function status */ return HAL_OK; } /** * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** * @brief DeInitializes the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** * @brief This function configures the source of the time base. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else { return HAL_ERROR; } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Provide a tick value in millisecond (+) Provide a blocking delay in millisecond (+) Suspend the time base source interrupt (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ */ /** * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; } /** * @brief Provides a tick value in millisecond. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; } /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { return uwTickPrio; } /** * @brief Set new tick Freq. * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; HAL_TickFreqTypeDef prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { /* Back up uwTickFreq frequency */ prevTickFreq = uwTickFreq; /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) { /* Restore previous tick frequency */ uwTickFreq = prevTickFreq; } } return status; } /** * @brief Return tick frequency. * @retval tick period in Hz */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { wait += (uint32_t)(uwTickFreq); } while ((HAL_GetTick() - tickstart) < wait) { } } /** * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { /* Enable SysTick Interrupt */ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Returns the HAL revision * @retval version 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; } /** * @brief Returns the device revision identifier. * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); } /** * @brief Returns the device identifier. * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** * @brief Returns first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); } /** * @brief Returns second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** * @brief Returns third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** * @brief Enable the Debug Module during SLEEP mode * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @} */ /** * @} */ #endif /* HAL_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC * + Operation functions * ++ Start, stop, get result of conversions of regular * group, using 3 possible modes: polling, interruption or DMA. * + Control functions * ++ Channels configuration on regular group * ++ Channels configuration on injected group * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management * Other functions (extended functions) are available in file * "stm32f1xx_hal_adc_ex.c". * @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit resolution (+) Interrupt generation at the end of regular conversion, end of injected conversion, and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) ADC conversion of regular group and injected group. (+) External trigger (timer or EXTI) for both regular and injected groups. (+) DMA request generation for transfer of conversions data of regular group. (+) Multimode Dual mode (available on devices with 2 ADCs or more). (+) Configurable DMA data storage in Multimode Dual mode (available on devices with 2 DCs or more). (+) Configurable delay between conversions in Dual interleaved mode (available on devices with 2 DCs or more). (+) ADC calibration (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. Caution: On STM32F1, ADC clock frequency max is 14MHz (refer to device datasheet). Therefore, ADC clock prescaler must be configured in function of ADC clock source frequency to remain below this maximum frequency. (++) One clock setting is mandatory: ADC clock (core clock, also possibly conversion clock). (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; (+++) __ADC1_CLK_ENABLE(); (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, groups regular/injected, channels parameters *** ========================================================================== [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the injected group parameters (conversion trigger, sequencer, ..., of injected group) and the channels for injected group parameters (channel number, channel rank into sequencer, ..., into injected group) using function HAL_ADCEx_InjectedConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). (#) Optionally, for devices with several ADC instances: configure the multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() (++) For devices with several ADCs: ADC multimode conversion with transfer by DMA: (+++) Activate the ADC peripheral (slave) and start conversions using function HAL_ADC_Start() (+++) Activate the ADC peripheral (master) and start conversions using function HAL_ADCEx_MultiModeStart_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral (master) using function HAL_ADCEx_MultiModeStop_DMA() (+++) Stop conversion and disable the ADC peripheral (slave) using function HAL_ADC_Stop_IT() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback (+@) HAL_ADCEx_InjectedConvCpltCallback() *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_Init(). (++) Disable the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_ADC_RegisterCallback() to register an interrupt callback. [..] Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback [..] By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() or @ref HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ /* Timeout values for ADC enable and disable settling time. */ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_ENABLE_TIMEOUT 2U #define ADC_DISABLE_TIMEOUT 2U /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ #define ADC_STAB_DELAY_US 1U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (clock source APB2). * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cr1 = 0U; uint32_t tmp_cr2 = 0U; uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ /* at RCC top level. */ /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set ADC parameters */ /* Configuration of ADC: */ /* - data alignment */ /* - external trigger to start conversion */ /* - external trigger polarity (always set to 1, because needed for all */ /* triggers: external trigger of SW start) */ /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)); /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) { if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)); } else { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_SCAN | ADC_CR1_DISCEN | ADC_CR1_DISCNUM, tmp_cr1); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, ADC_CR2_ALIGN | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG | ADC_CR2_CONT, tmp_cr2); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); } MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, tmp_sqr1); /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE)) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * If needed, the example code can be copied and uncommented into * function HAL_ADC_MspDeInit(). * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); /* Reset register CR1 */ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH)); /* Reset register CR2 */ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | ADC_CR2_ADON)); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)); /* Reset register JOFR1 */ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); /* Reset register JOFR2 */ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); /* Reset register JOFR3 */ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); /* Reset register JOFR4 */ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); /* Reset register HTR */ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); /* Reset register LTR */ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ /* __HAL_RCC_ADC1_FORCE_RESET() */ /* __HAL_RCC_ADC1_RELEASE_RESET() */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Initializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief Register a User ADC Callback * To be used instead of the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID: hadc->ConvCpltCallback = pCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID: hadc->ConvHalfCpltCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID: hadc->LevelOutOfWindowCallback = pCallback; break; case HAL_ADC_ERROR_CB_ID: hadc->ErrorCallback = pCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID: hadc->InjectedConvCpltCallback = pCallback; break; case HAL_ADC_MSPINIT_CB_ID: hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID: hadc->MspDeInitCallback = pCallback; break; default: /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID: hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID: hadc->MspDeInitCallback = pCallback; break; default: /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a ADC Callback * ADC callback is redirected to the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID: hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID: hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID: hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; case HAL_ADC_ERROR_CB_ID: hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID: hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; case HAL_ADC_MSPINIT_CB_ID: hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID: hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default: /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID: hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID: hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default: /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 IO operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. * @note This function cannot be used in a particular setup: ADC configured * in DMA mode. * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. * @note On STM32F1 devices, limitation in case of sequencer enabled * (several ranks selected): polling cannot be done on each * conversion inside the sequence. In this case, polling is replaced by * wait for maximum conversion time. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* - If single conversion for regular group (Scan mode disabled or enabled */ /* with NbrOfConversion =1), flag EOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for regular group (scan mode enabled and */ /* NbrOfConversion >=2), flag EOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)) { /* Wait until End of Conversion flag is raised */ while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc)); while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles++; } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Poll for conversion event. * @param hadc: ADC handle * @param EventType: the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event. * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while (__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } /* Analog watchdog (level out of window) event */ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStart function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * ADC2 converted data can be transferred in dual ADC mode using DMA * of ADC1 (ADC master in multimode). * In case of using ADC1 with DMA on a device featuring 2 ADC * instances: ADC1 conversion register DR contains ADC1 conversion * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last * conversion result (ADC1 register DR bits 16 to 27). Therefore, to * have DMA transferring the conversion results of ADC1 only, DMA must * be configured to transfer size: half word. * @param hadc: ADC handle * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if (ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStop function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) { if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } } /* ========== Check End of Conversion flag for injected group ========== */ if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) { if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Determine whether any further conversion upcoming on group injected */ /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } } /* ========== Check Analog watchdog flags ========== */ if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) { if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } } } /** * @brief Conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } /** * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } /** * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } /** * @brief ADC error callback in non blocking mode * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3, ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank), ADC_SQR3_RK(sConfig->Channel, sConfig->Rank)); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2, ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank), ADC_SQR2_RK(sConfig->Channel, sConfig->Rank)); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank), ADC_SQR1_RK(sConfig->Channel, sConfig->Rank)); } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel), ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel)); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel), ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel)); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)) { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while (wait_loop_index != 0U) { wait_loop_index--; } } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Configures the analog watchdog. * @note Analog watchdog thresholds can be modified while ADC conversion * is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc: ADC handle * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Analog watchdog configuration */ /* Configure ADC Analog watchdog interrupt */ if (AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); } else { /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); } /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: regular and/or injected groups, */ /* one or all channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDCH, AnalogWDGConfig->WatchdogMode | AnalogWDGConfig->Channel); /* Set the high threshold */ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); /* Set the low threshold */ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief return the ADC state * @param hadc: ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Return ADC state */ return hadc->State; } /** * @brief Return the ADC error code * @param hadc: ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { return hadc->ErrorCode; } /** * @} */ /** * @} */ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart = 0U; __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while (wait_loop_index != 0U) { wait_loop_index--; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ while (ADC_IS_ENABLE(hadc) == RESET) { if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief Stop ADC conversion and disable the selected ADC * @note Prerequisite condition to use this function: ADC conversions must be * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart = 0U; /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively disabled */ while (ADC_IS_ENABLE(hadc) != RESET) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } /** * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of injected * group, using 2 possible modes: polling, interruption. * ++ Multimode feature (available on devices with 2 ADCs or more) * ++ Calibration (ADC automatic self-calibration) * + Control functions * ++ Channels configuration on injected group * Other functions (generic functions) are available in file * "stm32f1xx_hal_adc.c". * @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32f1xx_hal_adc.c". [..] @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extension HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /* Delay for ADC calibration: */ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_CALIBRATION_TIMEOUT 10U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions * @brief Extended Extended Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of injected group. (+) Stop conversion of injected group. (+) Poll for conversion complete on injected group. (+) Get result of injected channel conversion. (+) Start conversion of injected group and enable interruptions. (+) Stop conversion of injected group and disable interruptions. (+) Start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @endverbatim * @{ */ /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * During calibration process, ADC is enabled. ADC is let enabled at * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES); while (wait_loop_index != 0U) { wait_loop_index--; } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); tickstart = HAL_GetTick(); /* Wait for calibration reset completion */ while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); tickstart = HAL_GetTick(); /* Wait for calibration completion */ while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of injected group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable conversion of injected group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ /* Case of multimode enabled (for devices with several ADCs): if ADC is */ /* slave, ADC is enabled only (conversion is not started). If ADC is */ /* master, ADC is enabled and conversion is started. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for injected group conversion to be completed. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get timeout */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag JEOC is not set after each conversion, no timeout status can */ /* be set. */ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) { /* Wait until End of Conversion flag is raised */ while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc)); while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles++; } } /* Clear injected group conversion flag */ /* Note: On STM32F1 ADC, clear regular conversion flag raised */ /* simultaneously. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of injected group with interruption. * - JEOC (end of conversion of injected group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); /* Start conversion of injected group if software start has been selected */ /* and if automatic injected conversion is disabled. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note: On STM32F1 devices, ADC slave regular group must be configured * with conversion trigger ADC_SOFTWARE_START. * @note: ADC slave can be enabled preliminarily using single-mode * HAL_ADC_Start() function. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* On STM32F1 devices, ADC slave regular group must be configured with */ /* conversion trigger ADC_SOFTWARE_START. */ /* Note: External trigger of ADC slave must be enabled, it is already done */ /* into function "HAL_ADC_Init()". */ if (!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start conversion if all ADCs of multimode are effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state (ADC master) */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode of ADC master */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Start conversion of regular group if software start has been selected. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note Multimode is kept enabled after this function. To disable multimode * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC master peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Disable ADC slave peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); /* Check if ADC is effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Reset configuration of ADC DMA continuous request for dual mode */ CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Change ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc: ADC handle * @param InjectedRank: the converted ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch (InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Returns the last ADC Master&Slave regular conversions results data * in the selected multi mode. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval The converted data value. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { uint32_t tmpDR = 0U; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ /* only if ADC1 DMA mode is enabled. */ tmpDR = hadc->Instance->DR; if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) { tmpDR |= (ADC2->DR << 16U); } /* Return ADC converted value */ return tmpDR; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on injected group (+) Configure multimode @endverbatim * @{ */ /** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @param hadc: ADC handle * @param sConfigInjected: Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter "InjectedNbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) { if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1, ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, 0x01U)); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion), ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion)); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion), 0x00000000U); } } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - external trigger to start conversion */ /* Parameters update not conditioned to ADC state: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Note: In case of ADC already enabled, caution to not launch an unwanted */ /* conversion while modifying register CR2 by writing 1 to bit ADON. */ if (ADC_IS_ENABLE(hadc) == RESET) { MODIFY_REG(hadc->Instance->CR2, ADC_CR2_JEXTSEL | ADC_CR2_ADON, ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv)); } /* Configuration of injected group */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* InjectedChannel sampling time configuration */ /* For channels 10 to 17 */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel)); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel)); } /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch (sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)) { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while (wait_loop_index != 0U) { wait_loop_index--; } } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without reseting * the ADCs (both ADCs of the common group). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To change back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc: ADC handle * @param multimode: Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MODE(multimode->Mode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - ADC master and ADC slave DMA configuration */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* To optimize code, all multimode settings can be set when both ADCs of */ /* the common group are in state: disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))) { MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DUALMOD, multimode->Mode); } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M3 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). (#) please refer to programming manual for details in how to configure priority. -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest preemption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value 0x0F. (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32f1xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup CORTEX CORTEX * @brief CORTEX HAL module driver * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts Systick functionalities @endverbatim * @{ */ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } /** * @brief Sets the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) * @param PreemptPriority: The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup = 0x00U; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } /** * @brief Initiates a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { /* System Reset */ NVIC_SystemReset(); } /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** * @} */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ #if (__MPU_PRESENT == 1U) /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable the MPU and clear the control register*/ MPU->CTRL = 0U; } /** * @brief Enable the MPU. * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Ensure MPU setting take effects */ __DSB(); __ISB(); } /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; if ((MPU_Init->Enable) != RESET) { /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } else { MPU->RBAR = 0x00U; MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) */ uint32_t HAL_NVIC_GetPriorityGrouping(void) { /* Get the PRIGROUP[10:8] field value */ return NVIC_GetPriorityGrouping(); } /** * @brief Gets the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Get priority for Cortex-M system or device specific interrupts */ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); } /** * @brief Sets Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clears the pending bit of an external interrupt. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } /** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } /** * @brief Configures the SysTick clock source. * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; } } /** * @brief This function handles SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); } /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e. a member of DMA handle structure). *** DMA HAL driver macros list *** ============================================= [..] Below the list of most used macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in reference manual. @endverbatim * @{ */ /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined(DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0U; #if defined(DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* DMA2 */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); /* Clean all callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete (+) Handle DMA interrupt request @endverbatim * @{ */ /** * @brief Start the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_BUSY; } return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Abort the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if (hdma->State != HAL_DMA_STATE_BUSY) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return status; } /** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; } /** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0U; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if (CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); } else { /* Half Transfer Complete flag */ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } /* Get tick */ tickstart = HAL_GetTick(); while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } if (CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Handles DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } /* Transfer Error Interrupt management **************************************/ else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } return; } /** * @brief Register callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback: pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @brief UnRegister callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; break; case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state (+) Get error code @endverbatim * @{ */ /** * @brief Return the DMA hande state. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { /* Return DMA handle state */ return hdma->State; } /** * @brief Return the DMA error code. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_exti.c * @author MCD Application Team * @brief EXTI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @verbatim ============================================================================== ##### EXTI Peripheral features ##### ============================================================================== [..] (+) Each Exti line can be configured within this driver. (+) Exti line can be configured in 3 different modes (++) Interrupt (++) Event (++) Both of them (+) Configurable Exti lines can be configured with 3 different triggers (++) Rising (++) Falling (++) Both of them (+) When set in interrupt mode, configurable Exti lines have two different interrupts pending registers which allow to distinguish which transition occurs: (++) Rising edge pending interrupt (++) Falling (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can be selected through multiplexer. ##### How to use this driver ##### ============================================================================== [..] (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). (++) Choose the interrupt line number by setting "Line" member from EXTI_ConfigTypeDef structure. (++) Configure the interrupt and/or event mode using "Mode" member from EXTI_ConfigTypeDef structure. (++) For configurable lines, configure rising and/or falling trigger "Trigger" member from EXTI_ConfigTypeDef structure. (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" member from GPIO_InitTypeDef structure. (#) Get current Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). (++) Provide exiting handle as first parameter. (++) Provide which callback will be registered using one value from EXTI_CallbackIDTypeDef. (++) Provide callback function pointer. (#) Get interrupt pending bit using HAL_EXTI_GetPending(). (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** MISRA C:2012 deviation rule has been granted for following rule: * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out * of bounds [0,3] in following API : * HAL_EXTI_SetConfigLine * HAL_EXTI_GetConfigLine * HAL_EXTI_ClearConfigLine */ #ifdef HAL_EXTI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup EXTI_Exported_Functions * @{ */ /** @addtogroup EXTI_Exported_Functions_Group1 * @brief Configuration functions * @verbatim =============================================================================== ##### Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Set configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { uint32_t regval; uint32_t linepos; uint32_t maskline; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); /* Assign line number to handle */ hexti->Line = pExtiConfig->Line; /* Compute line mask */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* Configure triggers for configurable lines */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); /* Configure rising trigger */ /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) { EXTI->RTSR |= maskline; } else { EXTI->RTSR &= ~maskline; } /* Configure falling trigger */ /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) { EXTI->FTSR |= maskline; } else { EXTI->FTSR &= ~maskline; } /* Configure gpio port selection in case of gpio exti line */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = AFIO->EXTICR[linepos >> 2u]; regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); AFIO->EXTICR[linepos >> 2u] = regval; } } /* Configure interrupt mode : read current mode */ /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) { EXTI->IMR |= maskline; } else { EXTI->IMR &= ~maskline; } /* Configure event mode : read current mode */ /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) { EXTI->EMR |= maskline; } else { EXTI->EMR &= ~maskline; } return HAL_OK; } /** * @brief Get configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { uint32_t regval; uint32_t linepos; uint32_t maskline; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; /* Compute line mask */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* 1] Get core mode : interrupt */ /* Check if selected line is enable */ if ((EXTI->IMR & maskline) != 0x00u) { pExtiConfig->Mode = EXTI_MODE_INTERRUPT; } else { pExtiConfig->Mode = EXTI_MODE_NONE; } /* Get event mode */ /* Check if selected line is enable */ if ((EXTI->EMR & maskline) != 0x00u) { pExtiConfig->Mode |= EXTI_MODE_EVENT; } /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { /* Check if configuration of selected line is enable */ if ((EXTI->RTSR & maskline) != 0x00u) { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } else { pExtiConfig->Trigger = EXTI_TRIGGER_NONE; } /* Get falling configuration */ /* Check if configuration of selected line is enable */ if ((EXTI->FTSR & maskline) != 0x00u) { pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; } /* Get Gpio port selection for gpio lines */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = AFIO->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } else { pExtiConfig->GPIOSel = 0x00u; } } else { /* No Trigger selected */ pExtiConfig->Trigger = EXTI_TRIGGER_NONE; pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; } /** * @brief Clear whole configuration of a dedicated Exti line. * @param hexti Exti handle. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) { uint32_t regval; uint32_t linepos; uint32_t maskline; /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* compute line mask */ linepos = (hexti->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* 1] Clear interrupt mode */ EXTI->IMR = (EXTI->IMR & ~maskline); /* 2] Clear event mode */ EXTI->EMR = (EXTI->EMR & ~maskline); /* 3] Clear triggers in case of configurable lines */ if ((hexti->Line & EXTI_CONFIG) != 0x00u) { EXTI->RTSR = (EXTI->RTSR & ~maskline); EXTI->FTSR = (EXTI->FTSR & ~maskline); /* Get Gpio port selection for gpio lines */ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = AFIO->EXTICR[linepos >> 2u]; regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); AFIO->EXTICR[linepos >> 2u] = regval; } } return HAL_OK; } /** * @brief Register callback for a dedicated Exti line. * @param hexti Exti handle. * @param CallbackID User callback identifier. * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. * @param pPendingCbfn function pointer to be stored as callback. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) { HAL_StatusTypeDef status = HAL_OK; switch (CallbackID) { case HAL_EXTI_COMMON_CB_ID: hexti->PendingCallback = pPendingCbfn; break; default: status = HAL_ERROR; break; } return status; } /** * @brief Store line number as handle private field. * @param hexti Exti handle. * @param ExtiLine Exti line number. * This parameter can be from 0 to @ref EXTI_LINE_NB. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) { /* Check the parameters */ assert_param(IS_EXTI_LINE(ExtiLine)); /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } else { /* Store line number as handle private field */ hexti->Line = ExtiLine; return HAL_OK; } } /** * @} */ /** @addtogroup EXTI_Exported_Functions_Group2 * @brief EXTI IO functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Handle EXTI interrupt request. * @param hexti Exti handle. * @retval none. */ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) { uint32_t regval; uint32_t maskline; /* Compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending bit */ regval = (EXTI->PR & maskline); if (regval != 0x00u) { /* Clear pending bit */ EXTI->PR = maskline; /* Call callback */ if (hexti->PendingCallback != NULL) { hexti->PendingCallback(); } } } /** * @brief Get interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge Specify which pending edge as to be checked. * This parameter can be one of the following values: * @arg @ref EXTI_TRIGGER_RISING_FALLING * This parameter is kept for compatibility with other series. * @retval 1 if interrupt is pending else 0. */ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { uint32_t regval; uint32_t maskline; uint32_t linepos; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); /* Compute line mask */ linepos = (hexti->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* return 1 if bit is set else 0 */ regval = ((EXTI->PR & maskline) >> linepos); return regval; } /** * @brief Clear interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge Specify which pending edge as to be clear. * This parameter can be one of the following values: * @arg @ref EXTI_TRIGGER_RISING_FALLING * This parameter is kept for compatibility with other series. * @retval None. */ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { uint32_t maskline; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); /* Compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Clear Pending bit */ EXTI->PR = maskline; } /** * @brief Generate a software interrupt for a dedicated line. * @param hexti Exti handle. * @retval None. */ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) { uint32_t maskline; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); /* Compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Generate Software interrupt */ EXTI->SWIER = maskline; } /** * @} */ /** * @} */ #endif /* HAL_EXTI_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions * + Memory Control functions * + Peripheral State functions * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections (+) Prefetch on I-Code (+) Option Bytes programming ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH memory of all STM32F1xx devices. (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes (++) Set/Reset the write protection (++) Set the Read protection Level (++) Program the user Option Bytes (++) Launch the Option Bytes loader (++) Erase Option Bytes (++) Program the data Option Bytes (++) Get the Write protection. (++) Get the user option bytes. (#) Interrupts and flags management functions : this group includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the half cycle access (+) Enable/Disable the FLASH interrupts (+) Monitor the FLASH flags status @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ /** * @} */ /* Private macro ---------------------------- ---------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ */ /* Variables used for Erase pages under interruption*/ FLASH_ProcessTypeDef pFlash; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_SetErrorCode(void); extern void FLASH_PageErase(uint32_t PageAddress); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions * @brief Programming operation functions * @verbatim @endverbatim * @{ */ /** * @brief Program halfword, word or double word at a specified address * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_ERROR; uint8_t index = 0; uint8_t nbiterations = 0; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #if defined(FLASH_BANK2_END) } else { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if (status == HAL_OK) { if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; } for (index = 0U; index < nbiterations; index++) { FLASH_Program_HalfWord((Address + (2U * index)), (uint16_t)(Data >> (16U * index))); #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) } else { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) { break; } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Program halfword, word or double word at a specified address with interrupt enabled. * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); #if defined(FLASH_BANK2_END) /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { return HAL_ERROR; } if (Address <= FLASH_BANK1_END) { /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); } else { /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); } #else /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ pFlash.Address = Address; pFlash.Data = Data; if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; /* Program halfword (16-bit) at a specified address. */ pFlash.DataRemaining = 1U; } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; /* Program word (32-bit : 2*16-bit) at a specified address. */ pFlash.DataRemaining = 2U; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; /* Program double word (64-bit : 4*16-bit) at a specified address. */ pFlash.DataRemaining = 4U; } /* Program halfword (16-bit) at a specified address. */ FLASH_Program_HalfWord(Address, (uint16_t)Data); return status; } /** * @brief This function handles FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0U; /* Check FLASH operation error flags */ #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { /* Return the faulty address */ addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFFU; /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); /* Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); #endif /* FLASH_BANK2_END */ /* Process can continue only if no error detected */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; /* Check if there are still pages to erase */ if (pFlash.DataRemaining != 0U) { addresstmp = pFlash.Address; /*Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(addresstmp); /*Increment sector number*/ addresstmp = pFlash.Address + FLASH_PAGE_SIZE; pFlash.Address = addresstmp; /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); FLASH_PageErase(addresstmp); } else { /* No more pages to Erase, user callback can be called. */ /* Reset Sector and stop Erase pages procedure */ pFlash.Address = addresstmp = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(addresstmp); } } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); #if defined(FLASH_BANK2_END) /* Stop Mass Erase procedure if no pending mass erase on other bank */ if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) { #endif /* FLASH_BANK2_END */ /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0U); /* Stop Mass Erase procedure*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ else { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ if (pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } else { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure */ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } } } #if defined(FLASH_BANK2_END) /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); /* Process can continue only if no error detected */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; /* Check if there are still pages to erase*/ if (pFlash.DataRemaining != 0U) { /* Indicate user which page address has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Address); /* Increment page address to next page */ pFlash.Address += FLASH_PAGE_SIZE; addresstmp = pFlash.Address; /* Operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); FLASH_PageErase(addresstmp); } else { /*No more pages to Erase*/ /*Reset Address and stop Erase pages procedure*/ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) { /* MassErase ended. Return the selected bank*/ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0U); pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } else { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ if (pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } else { /*Program ended. Return the selected address*/ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } } } #endif if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { #if defined(FLASH_BANK2_END) /* Operation is completed, disable the PG, PER and MER Bits for both bank */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); /* Disable End of FLASH Operation and Error source interrupts for both banks */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #else /* Operation is completed, disable the PG, PER and MER Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); /* Disable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ } /** * @brief FLASH operation error interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief management functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim * @{ */ /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* Verify Flash is unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { status = HAL_ERROR; } } #if defined(FLASH_BANK2_END) if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) { /* Authorize the FLASH BANK2 Registers access */ WRITE_REG(FLASH->KEYR2, FLASH_KEY1); WRITE_REG(FLASH->KEYR2, FLASH_KEY2); /* Verify Flash BANK2 is unlocked */ if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) { status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; } /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; } /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); } else { return HAL_ERROR; } return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); return HAL_OK; } /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. * @retval None */ void HAL_FLASH_OB_Launch(void) { /* Initiates a system reset request to launch the option byte loading */ HAL_NVIC_SystemReset(); } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions * @brief Peripheral errors functions * @verbatim =============================================================================== ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permit to get in run-time errors of the FLASH peripheral. @endverbatim * @{ */ /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode The returned value can be: * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Program a half-word (16-bit) at a specified address. * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) } else { /* Proceed to program the new data */ SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t *)Address = Data; } /** * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } /* There is no error flag set */ return HAL_OK; } #if defined(FLASH_BANK2_END) /** * @brief Wait for a FLASH BANK2 operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) { /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) { if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } /* If there is an error flag set */ return HAL_OK; } #endif /* FLASH_BANK2_END */ /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { uint32_t flags = 0U; #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; #endif /* FLASH_BANK2_END */ } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions * + Extended Peripheral Control functions * @verbatim ============================================================================== ##### Flash peripheral extended features ##### ============================================================================== ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32F1xxx devices. It includes (++) Set/Reset the write protection (++) Program the user Option Bytes (++) Get the Read protection Level @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Variables * @{ */ /* Variables used for Erase pages under interruption*/ extern FLASH_ProcessTypeDef pFlash; /** * @} */ /** * @} */ /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants * @{ */ #define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos #define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos #define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ /* Erase operations */ static void FLASH_MassErase(uint32_t Banks); void FLASH_PageErase(uint32_t PageAddress); /* Option bytes control */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); static uint32_t FLASH_OB_GetWRP(void); static uint32_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetUser(void); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * @verbatim ============================================================================== ##### FLASH Erasing Programming functions ##### ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: (+) @ref HAL_FLASHEx_Erase: return only when erase has been done (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ /** * @brief Perform a mass erase or erase the specified FLASH memory pages * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @param[out] PageError pointer to variable that * contains the configuration information on faulty page in case of error * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; uint32_t address = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { #if defined(FLASH_BANK2_END) if (pEraseInit->Banks == FLASH_BANK_BOTH) { /* Mass Erase requested for Bank1 and Bank2 */ /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_BOTH); /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { status = HAL_OK; } /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } else if (pEraseInit->Banks == FLASH_BANK_2) { /* Mass Erase requested for Bank2 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_2); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); } } } else { /* Page Erase is requested */ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); #if defined(FLASH_BANK2_END) /* Page Erase requested on address located on bank2 */ if (pEraseInit->PageAddress > FLASH_BANK1_END) { /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; /* Erase by page by page to be done*/ for (address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages) * FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; break; } } } } else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; /* Erase page by page to be done*/ for (address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; break; } } } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #if defined(FLASH_BANK2_END) /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #endif if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; FLASH_MassErase(pEraseInit->Banks); } else { /* Erase by page to be done*/ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; pFlash.DataRemaining = pEraseInit->NbPages; pFlash.Address = pEraseInit->PageAddress; /*Erase 1st page and wait for IT*/ FLASH_PageErase(pEraseInit->PageAddress); } return status; } /** * @} */ /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim ============================================================================== ##### Option Bytes Programming functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH option bytes operations. @endverbatim * @{ */ /** * @brief Erases the FLASH option bytes. * @note This functions erases all option bytes except the Read protection (RDP). * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * @retval HAL status */ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) { uint8_t rdptmp = OB_RDP_LEVEL_0; HAL_StatusTypeDef status = HAL_ERROR; /* Get the actual read protection Option Byte value */ rdptmp = FLASH_OB_GetRDP(); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if (status == HAL_OK) { /* Restore the last read protection Option Byte value */ status = FLASH_OB_RDP_LevelConfig(rdptmp); } } /* Return the erase status */ return status; } /** * @brief Program option bytes * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Write protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /* Enable of Write protection on the selected page */ status = FLASH_OB_EnableWRP(pOBInit->WRPPage); } else { /* Disable of Write protection on the selected page */ status = FLASH_OB_DisableWRP(pOBInit->WRPPage); } if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Read protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) { status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* USER configuration */ if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { status = FLASH_OB_UserConfig(pOBInit->USERConfig); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* DATA configuration*/ if ((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) { status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option byte configuration * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; /*Get WRP*/ pOBInit->WRPPage = FLASH_OB_GetWRP(); /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /*Get USER*/ pOBInit->USERConfig = FLASH_OB_GetUser(); } /** * @brief Get the Option byte user data * @param DATAAdress Address of the option byte DATA * This parameter can be one of the following values: * @arg @ref OB_DATA_ADDRESS_DATA0 * @arg @ref OB_DATA_ADDRESS_DATA1 * @retval Value programmed in USER data */ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { uint32_t value = 0; if (DATAAdress == OB_DATA_ADDRESS_DATA0) { /* Get value programmed in OB USER Data0 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; } else { /* Get value programmed in OB USER Data1 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; } return value; } /** * @} */ /** * @} */ /** @addtogroup FLASHEx_Private_Functions * @{ */ /** * @brief Full erase of FLASH memory Bank * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg @ref FLASH_BANK_1 Bank1 to be erased @if STM32F101xG * @arg @ref FLASH_BANK_2 Bank2 to be erased * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased @endif @if STM32F103xG * @arg @ref FLASH_BANK_2 Bank2 to be erased * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (Banks == FLASH_BANK_BOTH) { /* bank1 & bank2 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR2, FLASH_CR2_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else if (Banks == FLASH_BANK_2) { /*Only bank2 will be erased*/ SET_BIT(FLASH->CR2, FLASH_CR2_MER); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else { #endif /* FLASH_BANK2_END */ #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } /** * @brief Enable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write protected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFF; #if defined(FLASH_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFF; #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be protected ******/ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { /* Enable write protection */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) if (WRP0_Data != 0xFFU) { OB->WRP0 &= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 &= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 &= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 &= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Disable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write unprotected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFF; #if defined(FLASH_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFF; #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be unprotected ******/ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) if (WRP0_Data != 0xFFU) { OB->WRP0 |= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 |= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 |= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 |= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Set the read protection level. * @param ReadProtectLevel specifies the read protection level. * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if (status == HAL_OK) { /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); WRITE_REG(OB->RDP, ReadProtectLevel); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE((UserConfig & OB_IWDG_SW))); assert_param(IS_OB_STOP_SOURCE((UserConfig & OB_STOP_NO_RST))); assert_param(IS_OB_STDBY_SOURCE((UserConfig & OB_STDBY_NO_RST))); #if defined(FLASH_BANK2_END) assert_param(IS_OB_BOOT1((UserConfig & OB_BOOT1_SET))); #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_BANK2_END) OB->USER = (UserConfig | 0xF0U); #else OB->USER = (UserConfig | 0x88U); #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } return status; } /** * @brief Programs a half word at a specified Option Byte Data address. * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param Address specifies the address to be programmed. * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data specifies the data to be programmed. * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } /* Return the Option Byte Data Program Status */ return status; } /** * @brief Return the FLASH Write Protection Option Bytes value. * @retval The FLASH Write Protection Option Bytes value */ static uint32_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(READ_REG(FLASH->WRPR)); } /** * @brief Returns the FLASH Read Protection level. * @retval FLASH RDP level * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory */ static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; uint32_t tmp_reg = 0U; /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); if (tmp_reg == FLASH_OBR_RDPRT) { readstatus = OB_RDP_LEVEL_1; } else { readstatus = OB_RDP_LEVEL_0; } return readstatus; } /** * @brief Return the FLASH User Option Byte value. * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . */ static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); } /** * @} */ /** * @} */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Erase the specified FLASH memory page * @param PageAddress FLASH page to erase * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (PageAddress > FLASH_BANK1_END) { /* Proceed to erase the page */ SET_BIT(FLASH->CR2, FLASH_CR2_PER); WRITE_REG(FLASH->AR2, PageAddress); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); WRITE_REG(FLASH->AR, PageAddress); SET_BIT(FLASH->CR, FLASH_CR_STRT); #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @verbatim ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: (+) Input mode (+) Analog mode (+) Output mode (+) Alternate function mode (+) External interrupt/event lines [..] During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. [..] All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. [..] In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. [..] All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. [..] The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests ##### How to use this driver ##### ============================================================================== [..] (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_MODE 0x00000003u #define EXTI_MODE 0x10000000u #define GPIO_MODE_IT 0x00010000u #define GPIO_MODE_EVT 0x00020000u #define RISING_EDGE 0x00100000u #define FALLING_EDGE 0x00200000u #define GPIO_OUTPUT_TYPE 0x00000010u #define GPIO_NUMBER 16u /* Definitions for bit manipulation of CRL and CRH register */ #define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */ #define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */ #define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */ #define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */ #define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */ #define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */ #define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */ #define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs to be ready for use. @endverbatim * @{ */ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00u; uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) { /* Get the IO position */ ioposition = (0x01uL << position); /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; if (iocurrent == ioposition) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) { /* If we are configuring the pin in OUTPUT push-pull mode */ case GPIO_MODE_OUTPUT_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; break; /* If we are configuring the pin in OUTPUT open-drain mode */ case GPIO_MODE_OUTPUT_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; break; /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ case GPIO_MODE_AF_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; break; /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ case GPIO_MODE_AF_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; break; /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ case GPIO_MODE_INPUT: case GPIO_MODE_IT_RISING: case GPIO_MODE_IT_FALLING: case GPIO_MODE_IT_RISING_FALLING: case GPIO_MODE_EVT_RISING: case GPIO_MODE_EVT_FALLING: case GPIO_MODE_EVT_RISING_FALLING: /* Check the GPIO pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); if (GPIO_Init->Pull == GPIO_NOPULL) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; } else if (GPIO_Init->Pull == GPIO_PULLUP) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; /* Set the corresponding ODR bit */ GPIOx->BSRR = ioposition; } else /* GPIO_PULLDOWN */ { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; /* Reset the corresponding ODR bit */ GPIOx->BRR = ioposition; } break; /* If we are configuring the pin in INPUT analog mode */ case GPIO_MODE_ANALOG: config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); temp = AFIO->EXTICR[position >> 2u]; CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); AFIO->EXTICR[position >> 2u] = temp; /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { SET_BIT(EXTI->IMR, iocurrent); } else { CLEAR_BIT(EXTI->IMR, iocurrent); } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { SET_BIT(EXTI->EMR, iocurrent); } else { CLEAR_BIT(EXTI->EMR, iocurrent); } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { SET_BIT(EXTI->RTSR, iocurrent); } else { CLEAR_BIT(EXTI->RTSR, iocurrent); } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { SET_BIT(EXTI->FTSR, iocurrent); } else { CLEAR_BIT(EXTI->FTSR, iocurrent); } } } position++; } } /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { uint32_t position = 0x00u; uint32_t iocurrent; uint32_t tmp; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0u) { /* Get current io position */ iocurrent = (GPIO_Pin) & (1uL << position); if (iocurrent) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = AFIO->EXTICR[position >> 2u]; tmp &= 0x0FuL << (4u * (position & 0x03u)); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { tmp = 0x0FuL << (4u * (position & 0x03u)); CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); } /*------------------------- GPIO Mode Configuration --------------------*/ /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); } position++; } } /** * @} */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read and Write * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the GPIOs. @endverbatim * @{ */ /** * @brief Reads the specified input port pin. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) { bitstatus = GPIO_PIN_SET; } else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } /** * @brief Sets or clears the selected data port bit. * * @note This function uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState: specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) { GPIOx->BSRR = GPIO_Pin; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } /** * @brief Toggles the specified GPIO pin * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { uint32_t odr; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Ouput Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** * @brief Locks GPIO Pins configuration registers. * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence * has been applied on a port bit, it is no longer possible to modify the value of the port bit until * the next reset. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ SET_BIT(tmp, GPIO_Pin); /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) { return HAL_OK; } else { return HAL_ERROR; } } /** * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** * @brief EXTI line detection callbacks. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); /* NOTE: This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.c * @author MCD Application Team * @brief GPIO Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * + Extended features functions * @verbatim ============================================================================== ##### GPIO Peripheral extension features ##### ============================================================================== [..] GPIO module on STM32F1 family, manage also the AFIO register: (+) Possibility to use the EVENTOUT Cortex feature ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to use EVENTOUT Cortex feature (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @brief GPIO HAL module driver * @{ */ #ifdef HAL_GPIO_MODULE_ENABLED /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions * @{ */ /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions * @verbatim ============================================================================== ##### Extended features functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() @endverbatim * @{ */ /** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * @retval None */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) { /* Verify the parameters */ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); /* Apply the new configuration */ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); } /** * @brief Enables the Event Output. * @retval None */ void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } /** * @brief Disables the Event Output. * @retval None */ void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_iwdg.c * @author MCD Application Team * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: * + Initialization and Start functions * + IO operation functions * @verbatim ============================================================================== ##### IWDG Generic features ##### ============================================================================== [..] (+) The IWDG can be started by either software or hardware (configurable through option byte). (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays active even if the main clock fails. (+) Once the IWDG is started, the LSI is forced ON and both cannot be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded into the counter and the watchdog reset is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. (+) Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI clock frequency dispersion. STM32F1xx devices provide the capability to measure the LSI clock frequency (LSI clock is internally connected to TIM5 CH4 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. [..] Default timeout value (necessary for IWDG_SR status register update): Constant LSI_VALUE is defined based on the nominal LSI clock frequency. This frequency being subject to variations as mentioned above, the default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT below) may become too short or too long. In such cases, this default timeout value can be tuned by redefining the constant LSI_VALUE at user-application level (based, for instance, on the measured LSI clock frequency as explained above). ##### How to use this driver ##### ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts counting down. (++) Enable write access to configuration registers: IWDG_PR and IWDG_RLR. (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_IWDG_Refresh() function. *** IWDG HAL driver macros list *** ==================================== [..] Below the list of most used macros in IWDG HAL driver: (+) __HAL_IWDG_START: Enable the IWDG peripheral (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_IWDG_MODULE_ENABLED /** @addtogroup IWDG * @brief IWDG HAL module driver. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. The timeout value is also calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. The timeout value is multiplied by 1000 to be converted in milliseconds. */ #define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup IWDG_Exported_Functions * @{ */ /** @addtogroup IWDG_Exported_Functions_Group1 * @brief Initialization and Start functions. * @verbatim =============================================================================== ##### Initialization and Start functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef of associated handle. (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog is reloaded in order to exit function with correct time base. @endverbatim * @{ */ /** * @brief Initialize the IWDG according to the specified parameters in the * IWDG_InitTypeDef and start watchdog. Before exiting function, * watchdog is refreshed in order to have correct time base. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; hiwdg->Instance->RLR = hiwdg->Init.Reload; /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); /* Wait for register to be updated */ while (hiwdg->Instance->SR != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { return HAL_TIMEOUT; } } /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); /* Return function status */ return HAL_OK; } /** * @} */ /** @addtogroup IWDG_Exported_Functions_Group2 * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Refresh the IWDG. @endverbatim * @{ */ /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); /* Return function status */ return HAL_OK; } /** * @} */ /** * @} */ #endif /* HAL_IWDG_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions * + Peripheral Control functions * ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Constants PWR Private Constants * @{ */ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ #define PVD_MODE_IT 0x00010000U #define PVD_MODE_EVT 0x00020000U #define PVD_RISING_EDGE 0x00000001U #define PVD_FALLING_EDGE 0x00000002U /** * @} */ /** @defgroup PWR_register_alias_address PWR Register alias address * @{ */ /* ------------- PWR registers bit address in the alias region ---------------*/ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) #define PWR_CR_OFFSET 0x00U #define PWR_CSR_OFFSET 0x04U #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) /** * @} */ /** @defgroup PWR_CR_register_alias PWR CR Register alias address * @{ */ /* --- CR Register ---*/ /* Alias word address of LPSDSR bit */ #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) /* Alias word address of DBP bit */ #define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) /* Alias word address of PVDE bit */ #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) /** * @} */ /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address * @{ */ /* --- CSR Register ---*/ /* Alias word address of EWUP1 bit */ #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) /** * @} */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup PWR_Private_Functions PWR Private Functions * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) * @{ */ static void PWR_OverloadWfe(void); /* Private functions ---------------------------------------------------------*/ __NOINLINE static void PWR_OverloadWfe(void) { __asm volatile("wfe"); __asm volatile("nop"); } /** * @} */ /** @defgroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] After reset, the backup domain (RTC registers, RTC backup data registers) is protected against possible unwanted write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim * @{ */ /** * @brief Deinitializes the PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) { __HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enables access to the backup domain (RTC registers, RTC * backup data registers ). * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { /* Enable access to RTC and backup registers */ *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE; } /** * @brief Disables access to the backup domain (RTC registers, RTC * backup data registers). * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { /* Disable access to RTC and backup registers */ *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE; } /** * @} */ /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== *** PVD configuration *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** ================================ [..] (+) WakeUp pin is used to wake up the system from Standby mode. This pin is forced in input pull-down configuration and is active on rising edges. (+) There is one WakeUp pin: WakeUp Pin 1 on PA.00. [..] *** Low Power modes configuration *** ===================================== [..] The device features 3 low-power modes: (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running (+) Stop mode: All clocks are stopped (+) Standby mode: 1.8V domain powered off *** Sleep mode *** ================== [..] (+) Entry: The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (+) Exit: (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) (+++) Any EXTI Line (Internal or External) configured in Event mode *** Stop mode *** ================= [..] The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In Stop mode, all I/O pins keep the same state as in Run mode. (+) Entry: The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) function with: (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction (+) Exit: (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. *** Standby mode *** ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (+) Entry: (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (+) Exit: (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in NRSTpin, IWDG Reset *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] (+) The MCU can be woken up from low-power mode by an RTC Alarm event, without depending on an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop and Standby modes (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. *** PWR Workarounds linked to Silicon Limitation *** ==================================================== [..] Below the list of all silicon limitations known on STM32F1xx prouct. (#)Workarounds Implemented inside PWR HAL Driver (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function @endverbatim * @{ */ /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } /** * @brief Enables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_EnablePVD(void) { /* Enable the power voltage detector */ *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE; } /** * @brief Disables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_DisablePVD(void) { /* Disable the power voltage detector */ *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE; } /** * @brief Enables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Enable the EWUPx pin */ *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; } /** * @brief Disables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Disable the EWUPx pin */ *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; } /** * @brief Enters Sleep mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ /* No check on Regulator because parameter not used in SLEEP mode */ /* Prevent unused argument(s) compilation warning */ UNUSED(Regulator); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ if (SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } } /** * @brief Enters Stop mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by using an interrupt or a wakeup event, * HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ CLEAR_BIT(PWR->CR, PWR_CR_PDDS); /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); PWR_OverloadWfe(); /* WFE redefine locally */ PWR_OverloadWfe(); /* WFE redefine locally */ } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enters Standby mode. * @note In Standby mode, all I/O pins are high impedance except for: * - Reset pad (still available) * - TAMPER pin if configured for tamper or calibration out. * - WKUP pin (PA0) if enabled. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Select Standby mode */ SET_BIT(PWR->CR, PWR_CR_PDDS); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined(__CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enables CORTEX M3 SEVONPEND bit. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_EnableSEVOnPend(void) { /* Set SEVONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Disables CORTEX M3 SEVONPEND bit. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) { /* Clear SEVONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief This function handles the PWR PVD interrupt request. * @note This API should be called under the PVD_IRQHandler(). * @retval None */ void HAL_PWR_PVD_IRQHandler(void) { /* Check PWR exti flag */ if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PWR Exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } } /** * @brief PWR PVD interrupt callback * @retval None */ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc.c * @author MCD Application Team * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from Internal High Speed oscillator (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS) ##### RCC Limitations ##### ============================================================================== [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup RCC RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA #define MCO1_PIN GPIO_PIN_8 /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ static void RCC_Delay(uint32_t mdelay); /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through the PLL as System clock source. (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC clock source. (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x [..] System, AHB and APB buses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock divided by 128. (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly. This clock is derived of the main PLL through PLL Multiplier. (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK (+@) IWDG clock which is always the LSI clock. (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. @endverbatim * @{ */ /* Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ | Latency | SYSCLK clock frequency (MHz) | |---------------|-------------------------------| |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | |---------------|-------------------------------| |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | |---------------|-------------------------------| |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | +-----------------------------------------------+ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL, PLL2 and PLL3 are OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled * - All flags are cleared * @note This function does not modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } /* Get Start Tick */ tickstart = HAL_GetTick(); /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); return HAL_OK; } /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) { /* Check the parameters */ assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) { /* Check the parameter */ assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) { return HAL_ERROR; } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) { return HAL_ERROR; } } } } return HAL_OK; } /** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. * @param FLatency FLASH Latency * The value of this parameter depend on device used within the same series * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick */ tickstart = HAL_GetTick(); while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); return HAL_OK; } /** * @} */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @endverbatim * @{ */ /** * @brief Selects the clock source to output on MCO pin. * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock @if STM32F105xC * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source @endif @if STM32F107xC * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source @endif * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio = {0U}; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* Prevent unused argument(s) compilation warning */ UNUSED(RCC_MCOx); UNUSED(RCC_MCODiv); /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; gpio.Pull = GPIO_NOPULL; gpio.Pin = MCO1_PIN; /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } /** * @brief Enables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)ENABLE; } /** * @brief Disables the Clock Security System. * @retval None */ void HAL_RCC_DisableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)DISABLE; } /** * @brief Returns the SYSCLK frequency * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; uint32_t sysclockfreq = 0U; #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; break; } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); } sysclockfreq = pllclk; break; } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; break; } } return sysclockfreq; } /** * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; } /** * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; #if defined(RCC_CFGR2_PREDIV1SRC) /* Get the Prediv1 source --------------------------------------------------*/ RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Get the HSE configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } else { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); /* Get the HSI configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } else { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); /* Get the LSE configuration -----------------------------------------------*/ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } else { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } /* Get the LSI configuration -----------------------------------------------*/ if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } else { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } /* Get the PLL configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } else { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); #if defined(RCC_CR_PLL2ON) /* Get the PLL2 configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) { RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; } else { RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; } RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); #endif /* RCC_CR_PLL2ON */ } /** * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; #endif } /** * @brief This function handles the RCC CSS interrupt request. * @note This API should be called under the NMI_Handler(). * @retval None */ void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } } /** * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); do { __NOP(); } while (Delay--); } /** * @brief RCC Clock Security System interrupt callback * @retval none */ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions * ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /** @defgroup RCCEx RCCEx * @brief RCC Extension HAL module driver. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Macros RCCEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. @endverbatim * @{ */ /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(RTC clock). * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U, temp_reg = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; #endif /* STM32F105xC || STM32F107xC */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) { /* Check the parameters */ assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) { return HAL_ERROR; } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) { return HAL_ERROR; } } } #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; } /** * @brief Get the PeriphClkInit according to the internal * RCC configuration registers. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t srcclk = 0U; /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; /* Get the RTC configuration -----------------------------------------------*/ srcclk = __HAL_RCC_GET_RTC_SOURCE(); /* Source clock is LSE or LSI*/ PeriphClkInit->RTCClockSelection = srcclk; /* Get the ADC clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); #if defined(STM32F105xC) || defined(STM32F107xC) /* Get the I2S2 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); /* Get the I2S3 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) /* Get the I2S2 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; /* Get the I2S3 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /* Get the USB clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ } /** * @brief Returns the peripheral clock frequency * @note Returns 0 if peripheral clock is unknown * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock @if STM32F103xE * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock @endif @if STM32F103xG * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock @endif @if STM32F105xC * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F107xC * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F102xx * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F103xx * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { #if defined(STM32F105xC) || defined(STM32F107xC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) { #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } #else if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) { /* Prescaler of 2 selected for USB */ frequency = pllclk; } else { /* Prescaler of 3 selected for USB */ frequency = (2 * pllclk) / 3; } #else /* USBCLK = PLLCLK / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) { /* No prescaler selected for USB */ frequency = pllclk; } else { /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_I2S2: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); } else { /* Check if PLLI2S is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; } case RCC_PERIPHCLK_I2S3: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); } else { /* Check if PLLI2S is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) { frequency = LSI_VALUE; } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { frequency = HSE_VALUE / 128U; } /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0U */ } break; } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; } } return (frequency); } /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function * @brief PLLI2S Management functions * @verbatim =============================================================================== ##### Extended PLLI2S Management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the PLLI2S activation or deactivation @endverbatim * @{ */ /** * @brief Enable PLLI2S * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that * contains the configuration information for the PLLI2S * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) { uint32_t tickstart = 0U; /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Check the parameters */ assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLLI2S. */ __HAL_RCC_PLLI2S_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ return HAL_ERROR; } return HAL_OK; } /** * @brief Disable PLLI2S * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) { uint32_t tickstart = 0U; /* Disable PLL I2S as not requested by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Disable the main PLLI2S. */ __HAL_RCC_PLLI2S_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ return HAL_ERROR; } return HAL_OK; } /** * @} */ /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function * @brief PLL2 Management functions * @verbatim =============================================================================== ##### Extended PLL2 Management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the PLL2 activation or deactivation @endverbatim * @{ */ /** * @brief Enable PLL2 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that * contains the configuration information for the PLL2 * @note The PLL2 configuration not modified if used indirectly as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { /* Check the parameters */ assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } return HAL_OK; } /** * @brief Disable PLL2 * @note PLL2 is not disabled if used indirectly as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) { uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } return HAL_OK; } /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + TIM Time Base Initialization * + TIM Time Base Start * + TIM Time Base Start Interruption * + TIM Time Base Start DMA * + TIM Output Compare/PWM Initialization * + TIM Output Compare/PWM Channel Configuration * + TIM Output Compare/PWM Start * + TIM Output Compare/PWM Start Interruption * + TIM Output Compare/PWM Start DMA * + TIM Input Capture Initialization * + TIM Input Capture Channel Configuration * + TIM Input Capture Start * + TIM Input Capture Start Interruption * + TIM Input Capture Start DMA * + TIM One Pulse Initialization * + TIM One Pulse Channel Configuration * + TIM One Pulse Start * + TIM Encoder Interface Initialization * + TIM Encoder Interface Start * + TIM Encoder Interface Start Interruption * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration @verbatim ============================================================================== ##### TIMER Generic features ##### ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an Output Compare signal. (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] Use Function @ref HAL_TIM_RegisterCallback() to register a callback. @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) IC_MspInitCallback : TIM IC Msp Init Callback. (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. (+) OC_MspInitCallback : TIM OC Msp Init Callback. (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. (+) ErrorCallback : TIM Error Callback. (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions * @{ */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. (+) Start the Time Base and enable interrupt. (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Base_MspDeInitCallback == NULL) { htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; } /* DeInit the low level hardware */ htim->Base_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in DMA mode. * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in DMA mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @verbatim ============================================================================== ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the TIM Output Compare. (+) Stop the TIM Output Compare. (+) Start the TIM Output Compare and enable interrupt. (+) Stop the TIM Output Compare and disable interrupt. (+) Start the TIM Output Compare and enable DMA transfer. (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } /* DeInit the low level hardware */ htim->OC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @verbatim ============================================================================== ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the TIM PWM. (+) Stop the TIM PWM. (+) Start the TIM PWM and enable interrupt. (+) Stop the TIM PWM and disable interrupt. (+) Start the TIM PWM and enable DMA transfer. (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } /* DeInit the low level hardware */ htim->PWM_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ } /** * @brief Starts the PWM signal generation. * @param htim TIM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @verbatim ============================================================================== ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the TIM Input Capture. (+) Stop the TIM Input Capture. (+) Start the TIM Input Capture and enable interrupt. (+) Stop the TIM Input Capture and disable interrupt. (+) Start the TIM Input Capture and enable DMA transfer. (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } /* DeInit the low level hardware */ htim->IC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @verbatim ============================================================================== ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the TIM One Pulse. (+) Stop the TIM One Pulse. (+) Start the TIM One Pulse and enable interrupt. (+) Stop the TIM One Pulse and disable interrupt. (+) Start the TIM One Pulse and enable DMA transfer. (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @note When the timer instance is initialized in One Pulse mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } /* DeInit the low level hardware */ htim->OnePulse_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @verbatim ============================================================================== ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the TIM Encoder. (+) Stop the TIM Encoder. (+) Start the TIM Encoder and enable interrupt. (+) Stop the TIM Encoder and disable interrupt. (+) Start the TIM Encoder and enable DMA transfer. (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @note When the timer instance is initialized in Encoder mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Encoder interface * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } /* DeInit the low level hardware */ htim->Encoder_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 The destination Buffer address for IC1. * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_ALL: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } default: break; } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief TIM IRQ handler management * @verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== [..] This section provides Timer IRQ handler function. @endverbatim * @{ */ /** * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief TIM Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM Output Compare handle * @param sConfig TIM Output Compare configuration structure * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); break; } default: break; } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_2) { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } else { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM PWM handle * @param sConfig TIM PWM configuration structure * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; break; } default: break; } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @note To output a waveform with a minimum delay user can enable the fast * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx * output is forced in response to the edge detection on TIx input, * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); break; } default: break; } switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM DMA Burst mode * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); /* Return function status */ return HAL_OK; } /** * @brief Stop the DMA burst reading * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Generate a software event * @param htim TIM handle * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances * supporting a break input. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); /* Process Locked */ __HAL_LOCK(htim); /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); /* Return function status */ return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim TIM handle * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); break; } case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); break; } default: break; } switch (Channel) { case TIM_CHANNEL_1: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } else { /* Disable the OCREF clear feature for Channel 1 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; } case TIM_CHANNEL_2: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } else { /* Disable the OCREF clear feature for Channel 2 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } break; } case TIM_CHANNEL_3: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } else { /* Disable the OCREF clear feature for Channel 3 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } break; } case TIM_CHANNEL_4: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } else { /* Disable the OCREF clear feature for Channel 4 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the clock source to be used * @param htim TIM handle * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); break; } case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; break; } case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; break; } case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); break; } case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); break; } case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); break; } case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input * @param htim TIM handle. * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 * pins are connected to the TI1 input (XOR combination) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Reset the TI1 selection */ tmpcr2 &= ~TIM_CR2_TI1S; /* Set the TI1 selection */ tmpcr2 |= TI1_Selection; /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; return HAL_OK; } /** * @brief Configures the TIM in Slave mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit * @param htim TIM handle. * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; break; } default: break; } return tmpreg; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: (+) TIM Period elapsed callback (+) TIM Output Compare callback (+) TIM Input capture callback (+) TIM Trigger callback (+) TIM Error callback @endverbatim * @{ */ /** * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } /** * @brief Period elapsed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file */ } /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } /** * @brief Input Capture half complete callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file */ } /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User TIM callback to be used instead of the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @param pCallback pointer to the callback function * @retval status */ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID: htim->PeriodElapsedCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID: htim->PeriodElapsedHalfCpltCallback = pCallback; break; case HAL_TIM_TRIGGER_CB_ID: htim->TriggerCallback = pCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID: htim->TriggerHalfCpltCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID: htim->IC_CaptureCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID: htim->IC_CaptureHalfCpltCallback = pCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID: htim->OC_DelayElapsedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID: htim->PWM_PulseFinishedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID: htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; case HAL_TIM_ERROR_CB_ID: htim->ErrorCallback = pCallback; break; case HAL_TIM_COMMUTATION_CB_ID: htim->CommutationCallback = pCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID: htim->CommutationHalfCpltCallback = pCallback; break; case HAL_TIM_BREAK_CB_ID: htim->BreakCallback = pCallback; break; default: /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = pCallback; break; default: /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } /** * @brief Unregister a TIM callback * TIM callback is redirected to the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; case HAL_TIM_PERIOD_ELAPSED_CB_ID: htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID: htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ break; case HAL_TIM_TRIGGER_CB_ID: htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ break; case HAL_TIM_TRIGGER_HALF_CB_ID: htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ break; case HAL_TIM_IC_CAPTURE_CB_ID: htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID: htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID: htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID: htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID: htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ break; case HAL_TIM_ERROR_CB_ID: htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ break; case HAL_TIM_COMMUTATION_CB_ID: htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ break; case HAL_TIM_COMMUTATION_HALF_CB_ID: htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ break; case HAL_TIM_BREAK_CB_ID: htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ break; default: /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; default: /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief TIM Peripheral State functions * @verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Base handle state. * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM OC handle state. * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM PWM handle state. * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Input Capture handle state. * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM One Pulse Mode handle state. * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM handle * @retval Active channel */ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) { return htim->Channel; } /** * @brief Return actual state of the TIM channel. * @param htim TIM handle * @param Channel TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); return channel_state; } /** * @brief Return actual state of a DMA burst operation. * @param htim TIM handle * @retval DMA burst state */ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); return htim->DMABurstState; } /** * @} */ /** * @} */ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } else { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureHalfCpltCallback(htim); #else HAL_TIM_IC_CaptureHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Period Elapse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else HAL_TIM_PeriodElapsedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else HAL_TIM_TriggerHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Slave Timer configuration function * @param htim TIM handle * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = htim->Instance->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; break; } case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); break; } default: break; } return HAL_OK; } /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 |= TIM_ICSelection; /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P); tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P); tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Reset interrupt callbacks to the legacy weak callbacks. * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim_ex.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Timer remapping capabilities configuration @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== [..] The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the Timer Hall Sensor Interface and the commutation event with the corresponding Interrupt and DMA request if needed (Note that One Timer is used to interface with the Hall sensor Interface and another Timer should be used to use the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. (+) Start the Hall Sensor Interface and enable interrupts. (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. @endverbatim * @{ */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. * @note When the timer instance is initialized in Hall Sensor Interface mode, * timer channels 1 and channel 2 are reserved and cannot be used for * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->HallSensor_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; OC_Config.OCMode = TIM_OCMODE_PWM2; OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; OC_Config.Pulse = sConfig->Commutation_Delay; TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Hall Sensor interface * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } /* DeInit the low level hardware */ htim->HallSensor_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Hall Sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. (+) Start the Complementary Output Compare/PWM and enable interrupts. (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM OC handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @verbatim ============================================================================== ##### Timer Complementary PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. (+) Start the Complementary PWM and enable interrupts. (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. (+) Start the Complementary Input Capture measurement. (+) Stop the Complementary Input Capture. (+) Start the Complementary Input Capture and enable interrupts. (+) Stop the Complementary Input Capture and disable interrupts. (+) Start the Complementary Input Capture and enable DMA transfers. (+) Stop the Complementary Input Capture and disable DMA transfers. (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. @endverbatim * @{ */ /** * @brief Configure the TIM commutation event sequence. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with interrupt. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with DMA. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in master mode. * @param htim TIM handle. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @note Interrupts can be generated when an active level is detected on the * break input, the break 2 input or the system break input. Break * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); UNUSED(Remap); return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @verbatim ============================================================================== ##### Extended Callbacks functions ##### ============================================================================== [..] This section provides Extended TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @endverbatim * @{ */ /** * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } /** * @brief Hall commutation changed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @verbatim ============================================================================== ##### Extended Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Hall Sensor interface handle state. * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return actual state of the TIM complementary channel. * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); return channel_state; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Commutation half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationHalfCpltCallback(htim); #else HAL_TIMEx_CommutHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback (complementary channel). * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA error callback (complementary channel) * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/configuration.h ================================================ #ifndef CONFIGURATION_H_ #define CONFIGURATION_H_ #include /** * Configuration.h * Define here your default pre settings for MHP30 * */ //=========================================================================== //============================= Default Settings ============================ //=========================================================================== /** * Default soldering temp is 320.0 C * Temperature the iron sleeps at - default 150.0 C */ #define SLEEP_TEMP 150 // Default sleep temperature #define BOOST_TEMP 420 // Default boost temp. #define BOOST_MODE_ENABLED 1 // 0: Disable 1: Enable /** * Blink the temperature on the cooling screen when its > 50C */ #define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable /** * How many seconds/minutes we wait until going to sleep/shutdown. * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds! */ #define SLEEP_TIME 5 // x10 Seconds #define SHUTDOWN_TIME 0 // Minutes -- Default shutdown to being off /** * Auto start off for safety. * Pissible values are: * 0 - none * 1 - Soldering Temperature * 2 - Sleep Temperature * 3 - Sleep Off Temperature */ #define AUTO_START_MODE 0 // Default to none /** * Locking Mode * When in soldering mode a long press on both keys toggle the lock of the buttons * Possible values are: * 0 - Desactivated * 1 - Lock except boost * 2 - Full lock */ #define LOCKING_MODE 0 // Default to desactivated for safety /** * OLED Orientation * */ #define ORIENTATION_MODE 0 // 0: Right 1:Left 2:Automatic - Default right #define MAX_ORIENTATION_MODE 1 // Unlikely to ever change #define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change /** * OLED Brightness * */ #define MIN_BRIGHTNESS 0 // Min OLED brightness selectable #define MAX_BRIGHTNESS 100 // Max OLED brightness selectable #define BRIGHTNESS_STEP 25 // OLED brightness increment #define DEFAULT_BRIGHTNESS 25 // default OLED brightness /** * Temp change settings */ #define TEMP_CHANGE_SHORT_STEP 1 // Default temp change short step +1 #define TEMP_CHANGE_LONG_STEP 10 // Default temp change long step +10 #define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value #define TEMP_CHANGE_LONG_STEP_MAX 90 // Temp change long step MAX value /* Power pulse for keeping power banks awake*/ #define POWER_PULSE_INCREMENT 1 #define POWER_PULSE_MAX 100 // x10 max watts #define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds #define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds #define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc #define ADC_VDD_MV 3300 // ADC max reading millivolts #define POWER_PULSE_WAIT_DEFAULT 4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s #define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms #define POWER_PULSE_DEFAULT 5 /** * OLED Orientation Sensitivity on Automatic mode! * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive> */ #define SENSITIVITY 7 // Default 7 /** * Detailed soldering screen * Detailed idle screen (off for first time users) */ #define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0 #define DETAILED_IDLE 0 // 0: Disable 1: Enable - Default 0 // Due to large thermal mass of the PCB being heated we need to pull this back a bit #define THERMAL_RUNAWAY_TIME_SEC 20 #define THERMAL_RUNAWAY_TEMP_C 2 #define CUT_OUT_SETTING 0 // default to no cut-off voltage #define RECOM_VOL_CELL 33 // Minimum voltage per cell (Recommended 3.3V (33)) #define TEMPERATURE_INF 0 // default to 0 #define DESCRIPTION_SCROLL_SPEED 0 // 0: Slow 1: Fast - default to slow #define ANIMATION_LOOP 1 // 0: off 1: on #define ANIMATION_SPEED settingOffSpeed_t::MEDIUM #define OP_AMP_Rf_MHP30 268500 // 268.5 Kilo-ohms -> Measured #define OP_AMP_Rin_MHP30 1600 // 1.6 Kilo-ohms -> Measured #define OP_AMP_GAIN_STAGE_MHP30 (1 + (OP_AMP_Rf_MHP30 / OP_AMP_Rin_MHP30)) // Deriving the Voltage div: // Vin_max = (3.3*(r1+r2))/(r2) // vdiv = (32768*4)/(vin_max*10) #ifndef MODEL_MHP30 #error "No model defined!" #endif #ifdef MODEL_MHP30 #define SOLDERING_TEMP 200 // Default soldering temp is 200.0 °C #define VOLTAGE_DIV 360 // Default for MHP30 #define PID_POWER_LIMIT 65 // Sets the max pwm power limit #define CALIBRATION_OFFSET 0 // the adc offset in uV - MHP compensates automagically #define MIN_CALIBRATION_OFFSET 0 // Min value for calibration #define POWER_LIMIT 65 // 65 watts default power limit #define MAX_POWER_LIMIT 65 // #define POWER_LIMIT_STEPS 1 // #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_MHP30 // #define USB_PD_VMAX 20 // Maximum voltage for PD to negotiate #define MODEL_HAS_DCDC // Has inductor to current filter #define PID_TIM_HZ (16) // #define MAX_TEMP_C 350 // Max soldering temp selectable °C #define MAX_TEMP_F 660 // Max soldering temp selectable °F #define MIN_TEMP_C 10 // Min soldering temp selectable °C #define MIN_TEMP_F 50 // Min soldering temp selectable °F #define MIN_BOOST_TEMP_C 150 // The min settable temp for boost mode °C #define MIN_BOOST_TEMP_F 300 // The min settable temp for boost mode °F #define NO_DISPLAY_ROTATE // Disable OLED rotation by accel #define SLEW_LIMIT 50 // Limit to 3.0 Watts per 64ms pid loop update rate slew rate #define TIPTYPE_MHP30 1 // It's own special tip #define ACCEL_SC7 #define ACCEL_MSA #define PROFILE_SUPPORT #define OLED_96x16 1 #define POW_PD 1 #define POW_PD_EXT 0 #define USB_PD_EPR_WATTAGE 0 /*No EPR*/ #define TEMP_NTC #define I2C_SOFT_BUS_2 1 #define I2C_SOFT_BUS_1 1 #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define BATTFILTERDEPTH 8 #define OLED_I2CBB2 #define ACCEL_EXITS_ON_MOVEMENT #define NEEDS_VBUS_PROBE 0 #define HARDWARE_MAX_WATTAGE_X10 650 #define TIP_THERMAL_MASS 65 // TODO, needs refinement #define TIP_RESISTANCE 60 // x10 ohms, ~6 typical #endif /* MHP30 */ #ifdef ACCEL_EXITS_ON_MOVEMENT #define NO_SLEEP_MODE #endif #define FLASH_LOGOADDR (0x08000000 + (126 * 1024)) #define SETTINGS_START_PAGE (0x08000000 + (127 * 1024)) #endif /* CONFIGURATION_H_ */ ================================================ FILE: source/Core/BSP/MHP30/flash.c ================================================ /* * flash.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "BSP_Flash.h" #include "stm32f1xx_hal.h" #include "string.h" void flash_save_buffer(const uint8_t *buffer, const uint16_t length) { FLASH_EraseInitTypeDef pEraseInit; pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES; pEraseInit.Banks = FLASH_BANK_1; pEraseInit.NbPages = 1; pEraseInit.PageAddress = (uint32_t)SETTINGS_START_PAGE; uint32_t failingAddress = 0; resetWatchdog(); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY); HAL_FLASH_Unlock(); HAL_Delay(1); resetWatchdog(); HAL_FLASHEx_Erase(&pEraseInit, &failingAddress); //^ Erase the page of flash (1024 bytes on this stm32) // erased the chunk // now we program it uint16_t *data = (uint16_t *)buffer; HAL_FLASH_Unlock(); for (uint16_t i = 0; i < (length / 2); i++) { resetWatchdog(); HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, SETTINGS_START_PAGE + (i * sizeof(uint16_t)), data[i]); } HAL_FLASH_Lock(); } void flash_read_buffer(uint8_t *buffer, const uint16_t length) { memcpy(buffer, (uint8_t *)SETTINGS_START_PAGE, length); } ================================================ FILE: source/Core/BSP/MHP30/fusb_user.cpp ================================================ #include "configuration.h" #ifdef POW_PD #include "BSP.h" #include "I2CBB1.hpp" #include "Pins.h" #include "Setup.h" #include "USBPD.h" bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return I2CBB1::Mem_Read(deviceAddr, registerAdd, buf, size); } bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return I2CBB1::Mem_Write(deviceAddr, registerAdd, (uint8_t *)buf, size); } void setupFUSBIRQ() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pin = INT_PD_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(INT_PD_GPIO_Port, &GPIO_InitStruct); HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0); HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); } #endif ================================================ FILE: source/Core/BSP/MHP30/port.c ================================================ /* * FreeRTOS Kernel V10.3.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ /*----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM CM3 port. *----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is defined. The value should also ensure backward compatibility. FreeRTOS.org versions prior to V4.4.0 did not include this definition. */ #ifndef configKERNEL_INTERRUPT_PRIORITY #define configKERNEL_INTERRUPT_PRIORITY 255 #endif #ifndef configSYSTICK_CLOCK_HZ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ /* Ensure the SysTick is clocked at the same frequency as the core. */ #define portNVIC_SYSTICK_CLK_BIT (1UL << 2UL) #else /* The way the SysTick is clocked is not modified in case it is not the same as the core. */ #define portNVIC_SYSTICK_CLK_BIT (0) #endif /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) #define portNVIC_SYSTICK_LOAD_REG (*((volatile uint32_t *)0xe000e014)) #define portNVIC_SYSTICK_CURRENT_VALUE_REG (*((volatile uint32_t *)0xe000e018)) #define portNVIC_SYSPRI2_REG (*((volatile uint32_t *)0xe000ed20)) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_INT_BIT (1UL << 1UL) #define portNVIC_SYSTICK_ENABLE_BIT (1UL << 0UL) #define portNVIC_SYSTICK_COUNT_FLAG_BIT (1UL << 16UL) #define portNVIC_PENDSVCLEAR_BIT (1UL << 27UL) #define portNVIC_PEND_SYSTICK_CLEAR_BIT (1UL << 25UL) #define portNVIC_PENDSV_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 16UL) #define portNVIC_SYSTICK_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 24UL) /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER (16) #define portNVIC_IP_REGISTERS_OFFSET_16 (0xE000E3F0) #define portAIRCR_REG (*((volatile uint32_t *)0xE000ED0C)) #define portMAX_8_BIT_VALUE ((uint8_t)0xff) #define portTOP_BIT_OF_BYTE ((uint8_t)0x80) #define portMAX_PRIGROUP_BITS ((uint8_t)7) #define portPRIORITY_GROUP_MASK (0x07UL << 8UL) #define portPRIGROUP_SHIFT (8UL) /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ #define portVECTACTIVE_MASK (0xFFUL) /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR (0x01000000UL) /* The systick is a 24-bit counter. */ #define portMAX_24_BIT_NUMBER (0xffffffUL) /* A fiddle factor to estimate the number of SysTick counts that would have occurred while the SysTick counter is stopped during tickless idle calculations. */ #define portMISSED_COUNTS_FACTOR (45UL) /* For strict compliance with the Cortex-M spec the task start address should have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ #define portSTART_ADDRESS_MASK ((StackType_t)0xfffffffeUL) /* Let the user override the pre-loading of the initial LR with the address of prvTaskExitError() in case it messes up unwinding of the stack in the debugger. */ #ifdef configTASK_RETURN_ADDRESS #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /* * Setup the timer to generate the tick interrupts. The implementation in this * file is weak to allow application writers to change the timer used to * generate the tick interrupt. */ void vPortSetupTimerInterrupt(void); /* * Exception handlers. */ void xPortPendSVHandler(void) __attribute__((naked)); void xPortSysTickHandler(void); void vPortSVCHandler(void) __attribute__((naked)); /* * Start first task is a separate function so it can be tested in isolation. */ static void prvPortStartFirstTask(void) __attribute__((naked)); /* * Used to catch tasks that attempt to return from their implementing function. */ static void prvTaskExitError(void); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting variable. */ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; /* * The number of SysTick increments that make up one tick period. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t ulTimerCountsForOneTick = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * The maximum number of tick periods that can be suppressed is limited by the * 24 bit resolution of the SysTick timer. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t xMaximumPossibleSuppressedTicks = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Compensate for the CPU cycles that pass while the SysTick is stopped (low * power functionality only. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t ulStoppedTimerCompensation = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ #if (configASSERT_DEFINED == 1) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const)portNVIC_IP_REGISTERS_OFFSET_16; #endif /* configASSERT_DEFINED */ /*-----------------------------------------------------------*/ /* * See header file for description. */ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) { /* Simulate the stack frame as it would be created by a context switch interrupt. */ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ pxTopOfStack--; *pxTopOfStack = ((StackType_t)pxCode) & portSTART_ADDRESS_MASK; /* PC */ pxTopOfStack--; *pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* LR */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ *pxTopOfStack = (StackType_t)pvParameters; /* R0 */ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ static void prvTaskExitError(void) { volatile uint32_t ulDummy = 0UL; /* A function that implements a task must not exit or attempt to return to its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT(uxCriticalNesting == ~0UL); portDISABLE_INTERRUPTS(); while (ulDummy == 0) { /* This file calls prvTaskExitError() after the scheduler has been started to remove a compiler warning about the function being defined but never called. ulDummy is used purely to quieten other warnings about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } /*-----------------------------------------------------------*/ void vPortSVCHandler(void) { __asm volatile(" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " msr psp, r0 \n" /* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" " orr r14, #0xd \n" " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n"); } /*-----------------------------------------------------------*/ static void prvPortStartFirstTask(void) { __asm volatile(" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " cpsie i \n" /* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n"); } /*-----------------------------------------------------------*/ /* * See header file for description. */ BaseType_t xPortStartScheduler(void) { /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY); #if (configASSERT_DEFINED == 1) { volatile uint32_t ulOriginalPriority; volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER); volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) { ulMaxPRIGROUPValue--; ucMaxPriorityValue <<= (uint8_t)0x01; } #ifdef __NVIC_PRIO_BITS { /* Check the CMSIS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS); } #endif #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS); } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; /* Start the first task. */ prvPortStartFirstTask(); /* Should never get here as the tasks will now be executing! Call the task exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); prvTaskExitError(); /* Should not get here! */ return 0; } /*-----------------------------------------------------------*/ void vPortEndScheduler(void) { /* Not implemented in ports where there is nothing to return to. Artificially force an assert. */ configASSERT(uxCriticalNesting == 1000UL); } /*-----------------------------------------------------------*/ void vPortEnterCritical(void) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if (uxCriticalNesting == 1) { configASSERT((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0); } } /*-----------------------------------------------------------*/ void vPortExitCritical(void) { configASSERT(uxCriticalNesting); uxCriticalNesting--; if (uxCriticalNesting == 0) { portENABLE_INTERRUPTS(); } } /*-----------------------------------------------------------*/ void xPortPendSVHandler(void) { /* This is a naked function. */ __asm volatile(" mrs r0, psp \n" " isb \n" " \n" " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ " ldr r2, [r3] \n" " \n" " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ " \n" " stmdb sp!, {r3, r14} \n" " mov r0, %0 \n" " msr basepri, r0 \n" " bl vTaskSwitchContext \n" " mov r0, #0 \n" " msr basepri, r0 \n" " ldmia sp!, {r3, r14} \n" " \n" /* Restore the context, including the critical nesting count. */ " ldr r1, [r3] \n" " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ " msr psp, r0 \n" " isb \n" " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)); } /*-----------------------------------------------------------*/ void xPortSysTickHandler(void) { /* The SysTick runs at the lowest interrupt priority, so when this interrupt executes all interrupts must be unmasked. There is therefore no need to save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if (xTaskIncrementTick() != pdFALSE) { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } } portENABLE_INTERRUPTS(); } /*-----------------------------------------------------------*/ #if (configUSE_TICKLESS_IDLE == 1) __attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; TickType_t xModifiableIdleTime; /* Make sure the SysTick reload value does not overflow the counter. */ if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) { xExpectedIdleTime = xMaximumPossibleSuppressedTicks; } /* Stop the SysTick momentarily. The time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time. */ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; /* Calculate the reload value required to wait xExpectedIdleTime tick periods. -1 is used because this code will execute part way through one of the tick periods. */ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL)); if (ulReloadValue > ulStoppedTimerCompensation) { ulReloadValue -= ulStoppedTimerCompensation; } /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ __asm volatile("cpsid i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* If a context switch is pending or a task is waiting for the scheduler to be unsuspended then abandon the low power entry. */ if (eTaskConfirmSleepModeStatus() == eAbortSleep) { /* Restart from whatever is left in the count register to complete this tick period. */ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; /* Restart SysTick. */ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; /* Reset the reload register to the value required for normal tick periods. */ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; /* Re-enable interrupts - see comments above the cpsid instruction() above. */ __asm volatile("cpsie i" ::: "memory"); } else { /* Set the new reload value. */ portNVIC_SYSTICK_LOAD_REG = ulReloadValue; /* Clear the SysTick count flag and set the count value back to zero. */ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Restart SysTick. */ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can set its parameter to 0 to indicate that its implementation contains its own wait for interrupt or wait for event instruction, and so wfi should not be executed again. However, the original expected idle time variable must remain unmodified, so a copy is taken. */ xModifiableIdleTime = xExpectedIdleTime; configPRE_SLEEP_PROCESSING(xModifiableIdleTime); if (xModifiableIdleTime > 0) { __asm volatile("dsb" ::: "memory"); __asm volatile("wfi"); __asm volatile("isb"); } configPOST_SLEEP_PROCESSING(xExpectedIdleTime); /* Re-enable interrupts to allow the interrupt that brought the MCU out of sleep mode to execute immediately. see comments above __disable_interrupt() call above. */ __asm volatile("cpsie i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* Disable interrupts again because the clock is about to be stopped and interrupts that execute while the clock is stopped will increase any slippage between the time maintained by the RTOS and calendar time. */ __asm volatile("cpsid i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* Disable the SysTick clock without reading the portNVIC_SYSTICK_CTRL_REG register to ensure the portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, the time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time*/ portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT); /* Determine if the SysTick clock has already counted to zero and been set back to the current reload value (the reload back being correct for the entire expected idle time) or if the SysTick is yet to count to zero (in which case an interrupt other than the SysTick must have brought the system out of sleep mode). */ if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) { uint32_t ulCalculatedLoadValue; /* The tick interrupt is already pending, and the SysTick count reloaded with ulReloadValue. Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick period. */ ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL) - (ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG); /* Don't allow a tiny value, or values that have somehow underflowed because the post sleep hook did something that took too long. */ if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) { ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL); } portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; /* As the pending tick will be processed as soon as this function exits, the tick value maintained by the tick is stepped forward by one less than the time spent waiting. */ ulCompleteTickPeriods = xExpectedIdleTime - 1UL; } else { /* Something other than the tick interrupt ended the sleep. Work out how long the sleep lasted rounded to complete tick periods (not the ulReload value which accounted for part ticks). */ ulCompletedSysTickDecrements = (xExpectedIdleTime * ulTimerCountsForOneTick) - portNVIC_SYSTICK_CURRENT_VALUE_REG; /* How many complete tick periods passed while the processor was waiting? */ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; /* The reload value is set to whatever fraction of a single tick period remains. */ portNVIC_SYSTICK_LOAD_REG = ((ulCompleteTickPeriods + 1UL) * ulTimerCountsForOneTick) - ulCompletedSysTickDecrements; } /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, then set portNVIC_SYSTICK_LOAD_REG back to its standard value. */ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; vTaskStepTick(ulCompleteTickPeriods); portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; /* Exit with interrupts enabled. */ __asm volatile("cpsie i" ::: "memory"); } } #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__((weak)) void vPortSetupTimerInterrupt(void) { /* Calculate the constants required to configure the tick interrupt. */ #if (configUSE_TICKLESS_IDLE == 1) { ulTimerCountsForOneTick = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ); xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL; portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT); } /*-----------------------------------------------------------*/ #if (configASSERT_DEFINED == 1) void vPortValidateInterruptPriority(void) { uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); /* Is the interrupt number a user defined interrupt? */ if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ulCurrentInterrupt]; /* The following assertion will fail if a service routine (ISR) for an interrupt that has been assigned a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API function. ISR safe FreeRTOS API functions must *only* be called from interrupts that have been assigned a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY. Numerically low interrupt priority numbers represent logically high interrupt priorities, therefore the priority of the interrupt must be set to a value equal to or numerically *higher* than configMAX_SYSCALL_INTERRUPT_PRIORITY. Interrupts that use the FreeRTOS API must not be left at their default priority of zero as that is the highest possible priority, which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, and therefore also guaranteed to be invalid. FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT(ucCurrentPriority >= ucMaxSysCallPriority); } /* Priority grouping: The interrupt controller (NVIC) allows the bits that define each interrupt's priority to be split between bits that define the interrupt's pre-emption priority bits and bits that define the interrupt's sub-priority. For simplicity all bits must be defined to be pre-emption priority bits. The following assertion will fail if this is not the case (if some bits represent a sub-priority). If the application only uses CMSIS libraries for interrupt configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue); } #endif /* configASSERT_DEFINED */ ================================================ FILE: source/Core/BSP/MHP30/portmacro.h ================================================ /* * FreeRTOS Kernel V10.3.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ #ifndef PORTMACRO_H #define PORTMACRO_H #include "FreeRTOSConfig.h" #include "projdefs.h" #ifdef __cplusplus extern "C" { #endif /*----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. *----------------------------------------------------------- */ /* Type definitions. */ #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE uint32_t #define portBASE_TYPE long typedef portSTACK_TYPE StackType_t; typedef long BaseType_t; typedef unsigned long UBaseType_t; #if (configUSE_16_BIT_TICKS == 1) typedef uint16_t TickType_t; #define portMAX_DELAY (TickType_t)0xffff #else typedef uint32_t TickType_t; #define portMAX_DELAY (TickType_t)0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ #define portSTACK_GROWTH (-1) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) #define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Scheduler utilities. */ #define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ __asm volatile("dsb" ::: "memory"); \ __asm volatile("isb"); \ } #define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04)) #define portNVIC_PENDSVSET_BIT (1UL << 28UL) #define portEND_SWITCHING_ISR(xSwitchRequired) \ if (xSwitchRequired != pdFALSE) \ portYIELD() #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) /*-----------------------------------------------------------*/ /* Critical section management. */ extern void vPortEnterCritical(void); extern void vPortExitCritical(void); #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() #define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are not necessary for to use this port. They are defined so the common demo files (which build with all the ports) will build. */ #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime) #endif /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) { uint8_t ucReturn; __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory"); return ucReturn; } /* Check the configuration. */ #if (configMAX_PRIORITIES > 32) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif /* Store/clear the ready priorities in a bit map. */ #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority)) #define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) &= ~(1UL << (uxPriority)) /*-----------------------------------------------------------*/ #define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities))) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ #ifdef configASSERT void vPortValidateInterruptPriority(void); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* portNOP() is not required by this port. */ #define portNOP() #define portINLINE __inline #ifndef portFORCE_INLINE #define portFORCE_INLINE inline __attribute__((always_inline)) #endif /*-----------------------------------------------------------*/ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) { uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); if (ulCurrentInterrupt == 0) { xReturn = pdFALSE; } else { xReturn = pdTRUE; } return xReturn; } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortRaiseBASEPRI(void) { uint32_t ulNewBASEPRI; __asm volatile(" mov %0, %1 \n" " msr basepri, %0 \n" " isb \n" " dsb \n" : "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory"); } /*-----------------------------------------------------------*/ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile(" mrs %0, basepri \n" " mov %1, %2 \n" " msr basepri, %1 \n" " isb \n" " dsb \n" : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory"); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile(" msr basepri, %0 " ::"r"(ulNewMaskValue) : "memory"); } /*-----------------------------------------------------------*/ #define portMEMORY_BARRIER() __asm volatile("" ::: "memory") #ifdef __cplusplus } #endif #endif /* PORTMACRO_H */ ================================================ FILE: source/Core/BSP/MHP30/postRTOS.cpp ================================================ #include "BSP.h" #include "FreeRTOS.h" #include "I2C_Wrapper.hpp" #include "QC3.h" #include "Settings.h" #include "cmsis_os.h" #include "main.hpp" #include "power.hpp" #include "stdlib.h" #include "task.h" // Initialisation to be performed with scheduler active void postRToSInit() {} ================================================ FILE: source/Core/BSP/MHP30/preRTOS.cpp ================================================ /* * preRTOS.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "I2CBB1.hpp" #include "I2CBB2.hpp" #include "Pins.h" #include "Setup.h" #include void preRToSInit() { /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); Setup_HAL(); // Setup all the HAL objects BSPInit(); I2CBB2::init(); I2CBB1::init(); } ================================================ FILE: source/Core/BSP/MHP30/stm32f103.ld ================================================ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20005000; /* end of RAM */ _Min_Heap_Size = 0x300; /* required amount of heap */ _Min_Stack_Size = 1024; /* required amount of stack */ __APP_BASE_ADDRESS__ = 0x08000000 + __BOOTLDR_SIZE__; __ROM_REGION_LENGTH__ = __FLASH_SIZE__ - __BOOTLDR_SIZE__; __FLASH_END_ADDR__ = __APP_BASE_ADDRESS__ + __ROM_REGION_LENGTH__; /* Memories definition */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K ROM (rx) : ORIGIN = __APP_BASE_ADDRESS__, LENGTH = __ROM_REGION_LENGTH__ } /* ROM is normally 48K after the bootloader, however we allocate the last page for settings, and the second last one for display boot logo*/ /* Sections */ SECTIONS { /* The startup code into ROM memory */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >ROM /* The program code and other data into ROM memory */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >ROM /* Constant data into ROM memory*/ .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >ROM .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >ROM .ARM : { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); } >ROM .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >ROM .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >ROM .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); } >ROM /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into RAM memory */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> ROM .bss : { /* Uninitialized data section into RAM memory */ . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM /* Remove information from the compiler libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: source/Core/BSP/MHP30/stm32f1xx_hal_msp.c ================================================ #include "Pins.h" #include "Setup.h" #include "stm32f1xx_hal.h" #include "string.h" /** * Initializes the Global MSP. */ void HAL_MspInit(void) { __HAL_RCC_AFIO_CLK_ENABLE(); HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* System interrupt init*/ /* MemoryManagement_IRQn interrupt configuration */ HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); /* BusFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); /* UsageFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); /* SVCall_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); /* DebugMonitor_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); } void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { GPIO_InitTypeDef GPIO_InitStruct; memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); if (hadc->Instance == ADC1) { __HAL_RCC_ADC1_CLK_ENABLE(); /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; HAL_DMA_Init(&hdma_adc1); __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1); /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0); HAL_NVIC_EnableIRQ(ADC1_2_IRQn); } else { __HAL_RCC_ADC2_CLK_ENABLE(); GPIO_InitStruct.Pull = GPIO_NOPULL; /**ADC2 GPIO Configuration PB0 ------> ADC2_IN8 PB1 ------> ADC2_IN9 */ GPIO_InitStruct.Pin = TIP_TEMP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = TMP36_INPUT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = VIN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = PLATE_SENSOR_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(PLATE_SENSOR_GPIO_Port, &GPIO_InitStruct); /* ADC2 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0); HAL_NVIC_EnableIRQ(ADC1_2_IRQn); } } void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) { if (htim_base->Instance == TIM3) { __HAL_RCC_TIM3_CLK_ENABLE(); } else if (htim_base->Instance == TIM2) { __HAL_RCC_TIM2_CLK_ENABLE(); } } ================================================ FILE: source/Core/BSP/MHP30/stm32f1xx_hal_timebase_TIM.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32f1xx_hal_timebase_TIM.c * @brief HAL time base based on the hardware TIM. ****************************************************************************** * @attention * *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" #include "stm32f1xx_hal_tim.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ TIM_HandleTypeDef htim4; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** * @brief This function configures the TIM4 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; uint32_t uwPrescalerValue = 0; uint32_t pFLatency; /*Configure the TIM4 IRQ priority */ HAL_NVIC_SetPriority(TIM4_IRQn, TickPriority, 0); /* Enable the TIM4 global Interrupt */ HAL_NVIC_EnableIRQ(TIM4_IRQn); /* Enable TIM4 clock */ __HAL_RCC_TIM4_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); /* Compute TIM4 clock */ uwTimclock = 2 * HAL_RCC_GetPCLK1Freq(); /* Compute the prescaler value to have TIM4 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U); /* Initialize TIM4 */ htim4.Instance = TIM4; /* Initialize TIMx peripheral as follow: + Period = [(TIM4CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim4.Init.Period = (1000000U / 1000U) - 1U; htim4.Init.Prescaler = uwPrescalerValue; htim4.Init.ClockDivision = 0; htim4.Init.CounterMode = TIM_COUNTERMODE_UP; if (HAL_TIM_Base_Init(&htim4) == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim4); } /* Return function status */ return HAL_ERROR; } /** * @brief Suspend Tick increment. * @note Disable the tick increment by disabling TIM4 update interrupt. * @param None * @retval None */ void HAL_SuspendTick(void) { /* Disable TIM4 update Interrupt */ __HAL_TIM_DISABLE_IT(&htim4, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. * @note Enable the tick increment by Enabling TIM4 update interrupt. * @param None * @retval None */ void HAL_ResumeTick(void) { /* Enable TIM4 Update interrupt */ __HAL_TIM_ENABLE_IT(&htim4, TIM_IT_UPDATE); } /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/MHP30/stm32f1xx_it.c ================================================ // This is the stock standard STM interrupt file full of handlers #include "stm32f1xx_it.h" #include "Pins.h" #include "Setup.h" #include "cmsis_os.h" #include "stm32f1xx.h" #include "stm32f1xx_hal.h" extern TIM_HandleTypeDef htim4; // used for the systick /******************************************************************************/ /* Cortex-M3 Processor Interruption and Exception Handlers */ /******************************************************************************/ void NMI_Handler(void) {} // We have the assembly for a breakpoint trigger here to halt the system when a debugger is connected // Hardfault handler, often a screwup in the code void HardFault_Handler(void) {} // Memory management unit had an error void MemManage_Handler(void) {} // Prefetcher or busfault occured void BusFault_Handler(void) {} void UsageFault_Handler(void) {} void DebugMon_Handler(void) {} // Systick is used by FreeRTOS tick void SysTick_Handler(void) { osSystickHandler(); } /******************************************************************************/ /* STM32F1xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ /* For the available peripheral interrupt handler names, */ /* please refer to the startup file. */ /******************************************************************************/ // DMA used to move the ADC readings into system ram void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); } // ADC interrupt used for DMA void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); } // used for hal ticks void TIM4_IRQHandler(void) { HAL_TIM_IRQHandler(&htim4); } void EXTI9_5_IRQHandler(void) { HAL_GPIO_EXTI_IRQHandler(INT_PD_Pin); } ================================================ FILE: source/Core/BSP/MHP30/system_stm32f1xx.c ================================================ // This file was automatically generated by the STM Cube software // And as such, is BSD licneced from STM #include "stm32f1xx.h" #if !defined(HSI_VALUE) #define HSI_VALUE \ 8000000U /*!< Default value of the Internal oscillator in Hz. \ This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ /*!< Uncomment the following line if you need to use external SRAM */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ /******************************************************************************* * Clock Definitions *******************************************************************************/ #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */ #endif const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit(void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; #if defined(STM32F105xC) || defined(STM32F107xC) /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= 0xEBFFFFFFU; /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000U; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | 0x8000; /* Vector Table Relocation in Internal FLASH. */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz or 25 MHz, depending on the product used), user has to ensure * that HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; #endif /* STM32F105xC */ #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if !defined(STM32F105xC) && !defined(STM32F107xC) pllmull = (pllmull >> 18U) + 2U; if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { #if defined(STM32F100xB) || defined(STM32F100xE) prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; } #endif } #else pllmull = pllmull >> 18U; if (pllmull != 0x0DU) { pllmull += 2U; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ pllmull = 13U / 2U; } if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { /* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; if (prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; } else { /* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F105xC */ break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Setup the external memory controller. Called in startup_stm32f1xx.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f1xx_xx.s/.c before jump to main. * This function configures the external SRAM mounted on STM3210E-EVAL * board (STM32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { __IO uint32_t tmpreg; /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ /* Enable FSMC clock */ RCC->AHBENR = 0x00000114U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); (void)(tmpreg); /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ GPIOD->CRL = 0x44BB44BBU; GPIOD->CRH = 0xBBBBBBBBU; GPIOE->CRL = 0xB44444BBU; GPIOE->CRH = 0xBBBBBBBBU; GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRH = 0xBBBB4444U; GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRH = 0x444B4B44U; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[5U] = 0x00110212U; } #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/BSP.cpp ================================================ // BSP mapping functions #include "BSP.h" #include "BootLogo.h" #include "I2C_Wrapper.hpp" #include "Pins.h" #include "Settings.h" #include "Setup.h" #include "TipThermoModel.h" #include "USBPD.h" #include "configuration.h" #include "history.hpp" #include "main.hpp" #include volatile uint16_t PWMSafetyTimer = 0; volatile uint8_t pendingPWM = 0; const uint16_t powerPWM = 255; static const uint8_t holdoffTicks = 14; // delay of 8 ms static const uint8_t tempMeasureTicks = 14; uint16_t totalPWM; // htimADC.Init.Period, the full PWM cycle static bool fastPWM; static bool infastPWM; void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); } #ifdef TEMP_NTC // Lookup table for the NTC // Stored as ADCReading,Temp in degC static const uint16_t NTCHandleLookup[] = { // ADC Reading , Temp in C 29189, 0, // 28832, 2, // 28450, 4, // 28042, 6, // 27607, 8, // 27146, 10, // 26660, 12, // 26147, 14, // 25610, 16, // 25049, 18, // 24465, 20, // 23859, 22, // 23234, 24, // 22591, 26, // 21933, 28, // 21261, 30, // 20579, 32, // 19888, 34, // 19192, 36, // 18493, 38, // 17793, 40, // 17096, 42, // 16404, 44, // 16061, 45, // }; #endif uint16_t getHandleTemperature(uint8_t sample) { int32_t result = getADCHandleTemp(sample); #ifdef TEMP_NTC // TS80P uses 100k NTC resistors instead // NTCG104EF104FT1X from TDK // For now not doing interpolation for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t))); i++) { if (result > NTCHandleLookup[(i * 2) + 0]) { return NTCHandleLookup[(i * 2) + 1] * 10; } } return 45 * 10; #endif #ifdef TEMP_TMP36 // We return the current handle temperature in X10 C // TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for // example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) = // 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125 // mV per count So we need to subtract an offset of 0.5V to center on 0C // (4964.8 counts) // result -= 4965; // remove 0.5V offset // 10mV per C // 99.29 counts per Deg C above 0C. Tends to read a tad over across all of my sample units result *= 100; result /= 994; return result; #endif return 0; } uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { // ADC maximum is 32767 == 3.3V at input == 28.05V at VIN // Therefore we can divide down from there // Multiplying ADC max by 4 for additional calibration options, // ideal term is 467 uint32_t res = getADCVin(sample); res *= 4; res /= divisor; return res; } static void switchToFastPWM(void) { // 10Hz infastPWM = true; totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; htimADC.Instance->ARR = totalPWM; htimADC.Instance->CCR1 = powerPWM + holdoffTicks; htimADC.Instance->PSC = 2690; } static void switchToSlowPWM(void) { // 5Hz infastPWM = false; totalPWM = powerPWM + tempMeasureTicks / 2 + holdoffTicks / 2; htimADC.Instance->ARR = totalPWM; htimADC.Instance->CCR1 = powerPWM + holdoffTicks / 2; htimADC.Instance->PSC = 2690 * 2; } void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) { PWMSafetyTimer = 20; // This is decremented in the handler for PWM so that the tip pwm is // disabled if the PID task is not scheduled often enough. fastPWM = shouldUseFastModePWM; pendingPWM = pulse; } // These are called by the HAL after the corresponding events from the system // timers. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { // Period has elapsed if (htim->Instance == ADC_CONTROL_TIMER) { // we want to turn on the output again PWMSafetyTimer--; // We decrement this safety value so that lockups in the // scheduler will not cause the PWM to become locked in an // active driving state. // While we could assume this could never happen, its a small price for // increased safety #ifdef TIP_HAS_DIRECT_PWM htimADC.Instance->CCR4 = powerPWM; if (pendingPWM && PWMSafetyTimer) { htimTip.Instance->CCR1 = pendingPWM; HAL_TIM_PWM_Start(&htimTip, PWM_Out_CHANNEL); } else { HAL_TIM_PWM_Stop(&htimTip, PWM_Out_CHANNEL); } #else htimADC.Instance->CCR4 = pendingPWM; if (htimADC.Instance->CCR4 && PWMSafetyTimer) { HAL_TIM_PWM_Start(&htimTip, PWM_Out_CHANNEL); } else { HAL_TIM_PWM_Stop(&htimTip, PWM_Out_CHANNEL); } #endif if (fastPWM != infastPWM) { if (fastPWM) { switchToFastPWM(); } else { switchToSlowPWM(); } } } else if (htim->Instance == TIM1) { // STM uses this for internal functions as a counter for timeouts HAL_IncTick(); } } void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { // This was a when the PWM for the output has timed out if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) { HAL_TIM_PWM_Stop(&htimTip, PWM_Out_CHANNEL); } } void unstick_I2C() { #ifndef I2C_SOFT_BUS_1 GPIO_InitTypeDef GPIO_InitStruct; int timeout = 100; int timeout_cnt = 0; // 1. Clear PE bit. hi2c1.Instance->CR1 &= ~(0x0001); /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ // 2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR). GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Pin = SCL_Pin; HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); GPIO_InitStruct.Pin = SDA_Pin; HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET); while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) { // Move clock to release I2C HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET); asm("nop"); asm("nop"); asm("nop"); asm("nop"); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); timeout_cnt++; if (timeout_cnt > timeout) { return; } } // 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain. GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Pin = SCL_Pin; HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = SDA_Pin; HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET); // 13. Set SWRST bit in I2Cx_CR1 register. hi2c1.Instance->CR1 |= 0x8000; asm("nop"); // 14. Clear SWRST bit in I2Cx_CR1 register. hi2c1.Instance->CR1 &= ~0x8000; asm("nop"); // 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register hi2c1.Instance->CR1 |= 0x0001; // Call initialization function. HAL_I2C_Init(&hi2c1); #endif } uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; } uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; } void BSPInit(void) { switchToFastPWM(); } void reboot() { NVIC_SystemReset(); } void delay_ms(uint16_t count) { HAL_Delay(count); } uint8_t lastTipResistance = 0; // default to unknown const uint8_t numTipResistanceReadings = 3; uint32_t tipResistanceReadings[3] = {0, 0, 0}; uint8_t tipResistanceReadingSlot = 0; bool isTipDisconnected() { uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5; uint32_t tipTemp = TipThermoModel::getTipInC(); return tipTemp > tipDisconnectedThres; } void setStatusLED(const enum StatusLED state) {} void setBuzzer(bool on) {} #ifdef TIP_RESISTANCE_SENSE_Pin // We want to calculate lastTipResistance // If tip is connected, and the tip is cold and the tip is not being heated // We can use the GPIO to inject a small current into the tip and measure this // The gpio is 100k -> diode -> tip -> gnd // Source is 3.3V-0.5V // Which is around 0.028mA this will induce: // 6 ohm tip -> 3.24mV (Real world ~= 3320) // 8 ohm tip -> 4.32mV (Real world ~= 4500) // Which is definitely measureable // Taking shortcuts here as we know we only really have to pick apart 6 and 8 ohm tips // These are reported as 60 and 75 respectively void performTipResistanceSampleReading() { // 0 = read then turn on pullup, 1 = read then turn off pullup, 2 = read again tipResistanceReadings[tipResistanceReadingSlot] = TipThermoModel::convertTipRawADCTouV(getTipRawTemp(1)); HAL_GPIO_WritePin(TIP_RESISTANCE_SENSE_GPIO_Port, TIP_RESISTANCE_SENSE_Pin, (tipResistanceReadingSlot == 0) ? GPIO_PIN_SET : GPIO_PIN_RESET); tipResistanceReadingSlot++; } bool tipShorted = false; void FinishMeasureTipResistance() { // Otherwise we now have the 4 samples; // _^_ order, 2 delta's, combine these int32_t calculatedSkew = tipResistanceReadings[0] - tipResistanceReadings[2]; // If positive tip is cooling calculatedSkew /= 2; // divide by two to get offset per time constant int32_t reading = (((tipResistanceReadings[1] - tipResistanceReadings[0]) + calculatedSkew) // jump 1 - skew + // + ((tipResistanceReadings[1] - tipResistanceReadings[2]) + calculatedSkew) // jump 2 - skew ) // / 2; // Take average // // As we are only detecting two resistances; we can split the difference for now uint8_t newRes = 0; if (reading > 1200) { // return; // Change nothing as probably disconnected tip tipResistanceReadingSlot = lastTipResistance = 0; return; } else if (reading < 200) { tipShorted = true; } else if (reading < 520) { newRes = 40; } else if (reading < 800) { newRes = 62; } else { newRes = 80; } lastTipResistance = newRes; } volatile bool tipMeasurementOccuring = true; volatile TickType_t nextTipMeasurement = 100; void performTipMeasurementStep() { // Wait 200ms for settle time if (xTaskGetTickCount() < (nextTipMeasurement)) { return; } nextTipMeasurement = xTaskGetTickCount() + (TICKS_100MS * 5); if (tipResistanceReadingSlot < numTipResistanceReadings) { performTipResistanceSampleReading(); return; } // We are sensing the resistance FinishMeasureTipResistance(); tipMeasurementOccuring = false; } #endif uint8_t preStartChecks() { #ifdef TIP_RESISTANCE_SENSE_Pin performTipMeasurementStep(); if (preStartChecksDone() != 1) { return 0; } #endif #ifdef HAS_SPLIT_POWER_PATH // We want to enable the power path that has the highest voltage // Nominally one will be ~=0 and one will be high. Unless you jamb both in, then both _may_ be high, or device may be dead { uint16_t dc = getRawDCVin(); uint16_t pd = getRawPDVin(); if (dc > pd) { HAL_GPIO_WritePin(DC_SELECT_GPIO_Port, DC_SELECT_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(PD_SELECT_GPIO_Port, PD_SELECT_Pin, GPIO_PIN_RESET); } else { HAL_GPIO_WritePin(PD_SELECT_GPIO_Port, PD_SELECT_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(DC_SELECT_GPIO_Port, DC_SELECT_Pin, GPIO_PIN_RESET); } } #endif return 1; } uint64_t getDeviceID() { // return HAL_GetUIDw0() | ((uint64_t)HAL_GetUIDw1() << 32); } uint8_t preStartChecksDone() { #ifdef TIP_RESISTANCE_SENSE_Pin return (lastTipResistance == 0 || tipResistanceReadingSlot < numTipResistanceReadings || tipMeasurementOccuring || tipShorted) ? 0 : 1; #else return 1; #endif } uint8_t getTipResistanceX10() { #ifdef TIP_RESISTANCE_SENSE_Pin // Return tip resistance in x10 ohms // We can measure this using the op-amp uint8_t user_selected_tip = getUserSelectedTipResistance(); if (user_selected_tip == 0) { return lastTipResistance; // Auto mode } return user_selected_tip; #else uint8_t user_selected_tip = getUserSelectedTipResistance(); if (user_selected_tip == 0) { return TIP_RESISTANCE; // Auto mode } return user_selected_tip; #endif } #ifdef TIP_RESISTANCE_SENSE_Pin bool isTipShorted() { return tipShorted; } #else bool isTipShorted() { return false; } #endif uint16_t getTipThermalMass() { #ifdef TIP_RESISTANCE_SENSE_Pin if (lastTipResistance >= 80) { return TIP_THERMAL_MASS; } return 45; #else return TIP_THERMAL_MASS; #endif } uint16_t getTipInertia() { #ifdef TIP_RESISTANCE_SENSE_Pin if (lastTipResistance >= 80) { return TIP_THERMAL_MASS; } return 10; #else return TIP_THERMAL_MASS; #endif } void showBootLogo(void) { BootLogo::handleShowingLogo((uint8_t *)FLASH_LOGOADDR); } ================================================ FILE: source/Core/BSP/Miniware/FreeRTOSConfig.h ================================================ /* FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. All rights reserved VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. This file is part of the FreeRTOS distribution. FreeRTOS is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License (version 2) as published by the Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. *************************************************************************** >>! NOTE: The modification to the GPL is included to allow you to !<< >>! distribute a combined work that includes FreeRTOS without being !<< >>! obliged to provide the source code for proprietary components !<< >>! outside of the FreeRTOS kernel. !<< *************************************************************************** FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Full license text is available on the following link: http://www.freertos.org/a00114.html *************************************************************************** * * * FreeRTOS provides completely free yet professionally developed, * * robust, strictly quality controlled, supported, and cross * * platform software that is more than just the market leader, it * * is the industry's de facto standard. * * * * Help yourself get started quickly while simultaneously helping * * to support the FreeRTOS project by purchasing a FreeRTOS * * tutorial book, reference manual, or both: * * http://www.FreeRTOS.org/Documentation * * * *************************************************************************** http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading the FAQ page "My application does not run, what could be wrong?". Have you defined configASSERT()? http://www.FreeRTOS.org/support - In return for receiving this top quality embedded software for free we request you assist our global community by participating in the support forum. http://www.FreeRTOS.org/training - Investing in training allows your team to be as productive as possible as early as possible. Now you can receive FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers Ltd, and the world's leading authority on the world's leading RTOS. http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, including FreeRTOS+Trace - an indispensable productivity tool, a DOS compatible FAT file system, and our tiny thread aware UDP/IP stack. http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS licenses offer ticketed support, indemnification and commercial middleware. http://www.SafeRTOS.com - High Integrity Systems also provide a safety engineered and independently SIL3 certified version for use in safety and mission critical applications that require provable dependability. 1 tab == 4 spaces! */ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H /*----------------------------------------------------------- * Application specific definitions. * * These definitions should be adjusted for your particular hardware and * application requirements. * * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #ifdef __cplusplus extern "C" { #endif /* USER CODE END Includes */ /* Ensure stdint is only used by the compiler, and not the assembler. */ #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) #include extern uint32_t SystemCoreClock; #endif #define configUSE_PREEMPTION 1 #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ (SystemCoreClock) #define configTICK_RATE_HZ (1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((uint16_t)256) #define configTOTAL_HEAP_SIZE ((size_t)1024 * 14) /*Currently use about 9000*/ #define configMAX_TASK_NAME_LEN (32) #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 #define configUSE_TIMERS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configCHECK_FOR_STACK_OVERFLOW 2 /*Bump this to 2 during development and bug hunting*/ #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 #define configMAX_CO_ROUTINE_PRIORITIES (2) /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ #define INCLUDE_vTaskPrioritySet 1 #define INCLUDE_uxTaskPriorityGet 0 #define INCLUDE_vTaskDelete 0 #define INCLUDE_vTaskCleanUpResources 0 #define INCLUDE_vTaskSuspend 0 #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1 /* Cortex-M specific definitions. */ #ifdef __NVIC_PRIO_BITS /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ #define configPRIO_BITS __NVIC_PRIO_BITS #else #define configPRIO_BITS 4 #endif /* The lowest interrupt priority that can be used in a call to a "set priority" function. */ #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 /* The highest interrupt priority that can be used by any interrupt service routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values. */ #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 /* Interrupt priorities used by the kernel port layer itself. These are generic to all Cortex-M ports, and do not rely on any particular library functions. */ #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) /* Normal assert() semantics without relying on the provision of an assert.h header file. */ /* USER CODE BEGIN 1 */ #define configASSERT(x) \ if ((x) == 0) { \ taskDISABLE_INTERRUPTS(); \ for (;;) \ ; \ } /* USER CODE END 1 */ /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ #define vPortSVCHandler SVC_Handler #define xPortPendSVHandler PendSV_Handler #if configUSE_TIMERS #define configTIMER_TASK_PRIORITY 2 #define configTIMER_QUEUE_LENGTH 8 #define configTIMER_TASK_STACK_DEPTH (512 / 4) #endif #ifdef __cplusplus } #endif #endif /* FREERTOS_CONFIG_H */ ================================================ FILE: source/Core/BSP/Miniware/IRQ.cpp ================================================ /* * IRQ.c * * Created on: 30 May 2020 * Author: Ralim */ #include "IRQ.h" #include "Pins.h" #include "configuration.h" /* * Catch the IRQ that says that the conversion is done on the temperature * readings coming in Once these have come in we can unblock the PID so that it * runs again */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; if (hadc == &hadc1) { if (pidTaskNotification) { vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } } extern osThreadId POWTaskHandle; void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { (void)GPIO_Pin; // Notify POW thread that an irq occured if (POWTaskHandle != nullptr) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken); /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE. The macro used to do this is dependent on the port and may be called portEND_SWITCHING_ISR. */ portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } bool getFUS302IRQLow() { #ifdef POW_PD // Return true if the IRQ line is still held low return HAL_GPIO_ReadPin(INT_PD_GPIO_Port, INT_PD_Pin) == GPIO_PIN_RESET; #else return false; #endif } ================================================ FILE: source/Core/BSP/Miniware/IRQ.h ================================================ /* * Irqs.h * * Created on: 30 May 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_IRQ_H_ #define BSP_MINIWARE_IRQ_H_ #include "BSP.h" #include "I2C_Wrapper.hpp" #include "Setup.h" #include "main.hpp" #include "stm32f1xx_hal.h" #ifdef __cplusplus extern "C" { #endif void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_GPIO_EXTI_Callback(uint16_t); #ifdef __cplusplus } #endif #endif /* BSP_MINIWARE_IRQ_H_ */ ================================================ FILE: source/Core/BSP/Miniware/Pins.h ================================================ /* * Pins.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_PINS_H_ #define BSP_MINIWARE_PINS_H_ #include "configuration.h" #ifdef MODEL_TS100 #define KEY_B_Pin GPIO_PIN_6 #define KEY_B_GPIO_Port GPIOA #define TMP36_INPUT_Pin GPIO_PIN_7 #define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_ADC1_CHANNEL ADC_CHANNEL_7 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_7 #define TIP_TEMP_Pin GPIO_PIN_0 #define TIP_TEMP_GPIO_Port GPIOB #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_8 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_8 #define VIN_Pin GPIO_PIN_1 #define VIN_GPIO_Port GPIOB #define VIN_ADC1_CHANNEL ADC_CHANNEL_9 #define VIN_ADC2_CHANNEL ADC_CHANNEL_9 #define OLED_RESET_Pin GPIO_PIN_8 #define OLED_RESET_GPIO_Port GPIOA #define KEY_A_Pin GPIO_PIN_9 #define KEY_A_GPIO_Port GPIOA #define INT_Orientation_Pin GPIO_PIN_3 #define INT_Orientation_GPIO_Port GPIOB #define PWM_Out_Pin GPIO_PIN_4 #define PWM_Out_GPIO_Port GPIOB #define PWM_Out_CHANNEL TIM_CHANNEL_1 #define TIP_CONTROL_TIMER TIM3 #define ADC_CONTROL_TIMER TIM2 #define ADC_CONTROL_TIMER_IRQ TIM2_IRQn #define ADC_TRIGGER ADC_EXTERNALTRIGINJECCONV_T2_TRGO #define INT_Movement_Pin GPIO_PIN_5 #define INT_Movement_GPIO_Port GPIOB #define SCL_Pin GPIO_PIN_6 #define SCL_GPIO_Port GPIOB #define SDA_Pin GPIO_PIN_7 #define SDA_GPIO_Port GPIOB #endif #ifdef MODEL_TS101 #define KEY_B_Pin GPIO_PIN_10 #define KEY_B_GPIO_Port GPIOA #define TMP36_INPUT_Pin GPIO_PIN_4 #define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_4 #define TIP_TEMP_Pin GPIO_PIN_3 #define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3 #define VIN_Pin GPIO_PIN_2 #define VIN_GPIO_Port GPIOA #define VIN_ADC1_CHANNEL ADC_CHANNEL_2 #define VIN_ADC2_CHANNEL ADC_CHANNEL_2 #define PD_VIN_Pin GPIO_PIN_6 #define PD_VIN_GPIO_Port GPIOA #define PD_VIN_ADC1_CHANNEL ADC_CHANNEL_6 #define PD_VIN_ADC2_CHANNEL ADC_CHANNEL_6 #define OLED_RESET_Pin GPIO_PIN_7 #define OLED_RESET_GPIO_Port GPIOA #define KEY_A_Pin GPIO_PIN_8 #define KEY_A_GPIO_Port GPIOA #define PWM_Out_Pin GPIO_PIN_0 #define PWM_Out_GPIO_Port GPIOA #define PWM_Out_CHANNEL TIM_CHANNEL_1 #define TIP_CONTROL_TIMER TIM2 #define ADC_CONTROL_TIMER TIM4 #define ADC_CONTROL_TIMER_IRQ TIM4_IRQn #define ADC_TRIGGER ADC_EXTERNALTRIGINJECCONV_T4_TRGO #define SCL_Pin GPIO_PIN_0 #define SCL_GPIO_Port GPIOB #define SDA_Pin GPIO_PIN_1 #define SDA_GPIO_Port GPIOB // PD controller #define SCL2_Pin GPIO_PIN_6 #define SCL2_GPIO_Port GPIOB #define SDA2_Pin GPIO_PIN_5 #define SDA2_GPIO_Port GPIOB #define INT_PD_Pin GPIO_PIN_7 #define INT_PD_GPIO_Port GPIOB // Selecting the DC source to route to theg #define DC_SELECT_Pin GPIO_PIN_4 #define DC_SELECT_GPIO_Port GPIOB #define PD_SELECT_Pin GPIO_PIN_15 #define PD_SELECT_GPIO_Port GPIOA #define TIP_RESISTANCE_SENSE_Pin GPIO_PIN_1 #define TIP_RESISTANCE_SENSE_GPIO_Port GPIOA #endif #if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0 // TS80 & TS80P pin map #define KEY_B_Pin GPIO_PIN_0 #define KEY_B_GPIO_Port GPIOB #define TMP36_INPUT_Pin GPIO_PIN_4 #define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC2_CHANNEL ADC_CHANNEL_4 #define TIP_TEMP_Pin GPIO_PIN_3 #define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_3 #define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_3 #define VIN_Pin GPIO_PIN_2 #define VIN_GPIO_Port GPIOA #define VIN_ADC1_CHANNEL ADC_CHANNEL_2 #define VIN_ADC2_CHANNEL ADC_CHANNEL_2 #define OLED_RESET_Pin GPIO_PIN_15 #define OLED_RESET_GPIO_Port GPIOA #define KEY_A_Pin GPIO_PIN_1 #define KEY_A_GPIO_Port GPIOB #define INT_Orientation_Pin GPIO_PIN_4 #define INT_Orientation_GPIO_Port GPIOB #define PWM_Out_Pin GPIO_PIN_6 #define PWM_Out_GPIO_Port GPIOA #define PWM_Out_CHANNEL TIM_CHANNEL_1 #define TIP_CONTROL_TIMER TIM3 #define ADC_CONTROL_TIMER TIM2 #define ADC_CONTROL_TIMER_IRQ TIM2_IRQn #define ADC_TRIGGER ADC_EXTERNALTRIGINJECCONV_T2_TRGO #define INT_Movement_Pin GPIO_PIN_5 #define INT_Movement_GPIO_Port GPIOB #define SCL_Pin GPIO_PIN_6 #define SCL_GPIO_Port GPIOB #define SDA_Pin GPIO_PIN_7 #define SDA_GPIO_Port GPIOB #define SCL2_Pin GPIO_PIN_5 #define SCL2_GPIO_Port GPIOA #define SDA2_Pin GPIO_PIN_1 #define SDA2_GPIO_Port GPIOA #endif #ifdef MODEL_TS80P // TS80P pin map #define INT_PD_Pin GPIO_PIN_9 #define INT_PD_GPIO_Port GPIOA #endif #endif /* BSP_MINIWARE_PINS_H_ */ ================================================ FILE: source/Core/BSP/Miniware/Power.cpp ================================================ #include "BSP.h" #include "BSP_Power.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "USBPD.h" #include "configuration.h" #include "stm32f1xx_hal.h" void power_check() { #ifdef POW_PD // Cant start QC until either PD works or fails if (!USBPowerDelivery::negotiationComplete()) { return; } if (USBPowerDelivery::negotiationHasWorked()) { return; // We are using PD } #endif #ifdef POW_QC QC_resync(); #endif } bool getIsPoweredByDCIN() { #if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0 return false; #endif #ifdef MODEL_TS101 // TODO have to check what we are using return HAL_GPIO_ReadPin(DC_SELECT_GPIO_Port, DC_SELECT_Pin) == GPIO_PIN_SET; #endif #ifdef MODEL_TS100 return true; #endif } ================================================ FILE: source/Core/BSP/Miniware/QC_GPIO.cpp ================================================ /* * QC.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "configuration.h" #include "stm32f1xx_hal.h" #ifdef POW_QC void QC_DPlusZero_Six() { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); // pull down D+ } void QC_DNegZero_Six() { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_RESET); } void QC_DPlusThree_Three() { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_SET); // pull up D+ } void QC_DNegThree_Three() { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, GPIO_PIN_SET); } void QC_DM_PullDown() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLDOWN; GPIO_InitStruct.Pin = GPIO_PIN_11; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_DM_No_PullDown() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_11; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_Init_GPIO() { // Setup any GPIO into the right states for QC GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); // Turn off output mode on pins that we can GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } void QC_Post_Probe_En() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); } uint8_t QC_DM_PulledDown() { return HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11) == GPIO_PIN_RESET ? 1 : 0; } #endif void QC_resync() { #ifdef POW_QC seekQC(getSettingValue(SettingsOptions::QCIdealVoltage), getSettingValue(SettingsOptions::VoltageDiv)); // Run the QC seek again if we have drifted too much #endif } ================================================ FILE: source/Core/BSP/Miniware/README.md ================================================ # BSP section for STM32F103 based Miniware products This folder contains the hardware abstractions required for the TS100, TS80 and probably TS80P soldering irons. ## Main abstractions * Hardware Init * -> Should contain all bootstrap to bring the hardware up to an operating point * -> Two functions are required, a pre and post FreeRToS call * I2C read/write * Set PWM for the tip * Links between IRQ's on the system and the calls in the rest of the firmware ================================================ FILE: source/Core/BSP/Miniware/Setup.cpp ================================================ /* * Setup.c * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #include "Setup.h" #include "BSP.h" #include "Pins.h" #include "configuration.h" #include "history.hpp" #include ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; DMA_HandleTypeDef hdma_adc1; IWDG_HandleTypeDef hiwdg; TIM_HandleTypeDef htimADC; TIM_HandleTypeDef htimTip; #define ADC_FILTER_LEN 4 #define ADC_SAMPLES 16 uint16_t ADCReadings[ADC_SAMPLES]; // Used to store the adc readings for the handle cold junction temp // Functions static void SystemClock_Config(void); static void MX_ADC1_Init(void); static void MX_IWDG_Init(void); static void MX_TIP_CONTROL_TIMER_Init(void); static void MX_ADC_CONTROL_TIMER_Init(void); static void MX_DMA_Init(void); static void MX_GPIO_Init(void); static void MX_ADC2_Init(void); void Setup_HAL() { SystemClock_Config(); #ifndef SWD_ENABLE __HAL_AFIO_REMAP_SWJ_DISABLE(); #else __HAL_AFIO_REMAP_SWJ_NOJTAG(); #endif MX_GPIO_Init(); MX_DMA_Init(); #ifndef I2C_SOFT_BUS_1 #error "Only Bit-Bang now" #endif MX_ADC1_Init(); MX_ADC2_Init(); MX_TIP_CONTROL_TIMER_Init(); MX_ADC_CONTROL_TIMER_Init(); MX_IWDG_Init(); HAL_ADC_Start_DMA(&hadc1, (uint32_t *)ADCReadings, (ADC_SAMPLES)); // start DMA of normal readings HAL_ADCEx_InjectedStart(&hadc1); // enable injected readings HAL_ADCEx_InjectedStart(&hadc2); // enable injected readings } uint16_t getADCHandleTemp(uint8_t sample) { static history filter = {{0}, 0, 0}; if (sample) { uint32_t sum = 0; for (uint8_t i = 0; i < ADC_SAMPLES; i++) { sum += ADCReadings[i]; } filter.update(sum); } return filter.average() >> 1; } #ifdef HAS_SPLIT_POWER_PATH static history filteredDC = {{0}, 0, 0}; static history filteredPD = {{0}, 0, 0}; uint16_t getRawDCVin() { return filteredDC.average(); } uint16_t getRawPDVin() { return filteredPD.average(); } #endif uint16_t getADCVin(uint8_t sample) { #ifdef HAS_SPLIT_POWER_PATH // In split power path operation, we need to read both inputs, and return the larger if (sample) { { uint16_t latestADC = 0; latestADC += hadc2.Instance->JDR1; latestADC += hadc2.Instance->JDR2; latestADC <<= 3; filteredDC.update(latestADC); } { uint16_t latestADC = 0; latestADC += hadc2.Instance->JDR3; latestADC += hadc2.Instance->JDR4; latestADC <<= 3; filteredPD.update(latestADC); } } uint16_t dc = filteredDC.average(); uint16_t pd = filteredPD.average(); if (dc > pd) { return dc; } return pd; #else static history filter = {{0}, 0, 0}; if (sample) { uint16_t latestADC = 0; latestADC += hadc2.Instance->JDR1; latestADC += hadc2.Instance->JDR2; latestADC += hadc2.Instance->JDR3; latestADC += hadc2.Instance->JDR4; latestADC <<= 1; filter.update(latestADC); } return filter.average(); #endif } // Returns either average or instant value. When sample is set the samples from the injected ADC are copied to the filter and then the raw reading is returned uint16_t getTipRawTemp(uint8_t sample) { static history filter = {{0}, 0, 0}; if (sample) { uint16_t latestADC = 0; latestADC += hadc1.Instance->JDR1; latestADC += hadc1.Instance->JDR2; latestADC += hadc1.Instance->JDR3; latestADC += hadc1.Instance->JDR4; latestADC <<= 1; filter.update(latestADC); return latestADC; } return filter.average(); } /** System Clock Configuration */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64MHz HAL_RCC_OscConfig(&RCC_OscInitStruct); /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM // 2,3,4,5,6,7,12,13,14 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 mhz to some peripherals and adc HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000); /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); } /* ADC1 init function */ static void MX_ADC1_Init(void) { ADC_ChannelConfTypeDef sConfig; ADC_InjectionConfTypeDef sConfigInjected; /**Common config */ hadc1.Instance = ADC1; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.NbrOfConversion = 1; HAL_ADC_Init(&hadc1); /**Configure Regular Channel */ sConfig.Channel = TMP36_ADC1_CHANNEL; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5; HAL_ADC_ConfigChannel(&hadc1, &sConfig); /**Configure Injected Channel */ // F in = 10.66 MHz /* * Injected time is 1 delay clock + (12 adc cycles*4)+4*sampletime =~217 * clocks = 0.2ms Charge time is 0.016 uS ideally So Sampling time must be >= * 0.016uS 1/10.66MHz is 0.09uS, so 1 CLK is *should* be enough * */ sConfigInjected.InjectedChannel = TIP_TEMP_ADC1_CHANNEL; sConfigInjected.InjectedRank = 1; sConfigInjected.InjectedNbrOfConversion = 4; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES_5; sConfigInjected.ExternalTrigInjecConv = ADC_TRIGGER; sConfigInjected.AutoInjectedConv = DISABLE; sConfigInjected.InjectedDiscontinuousConvMode = DISABLE; sConfigInjected.InjectedOffset = 0; HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); sConfigInjected.InjectedRank = 2; HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); sConfigInjected.InjectedRank = 3; HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); sConfigInjected.InjectedRank = 4; HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected); SET_BIT(hadc1.Instance->CR1, (ADC_CR1_JEOCIE)); // Enable end of injected conv irq // Run ADC internal calibration while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) { ; } } /* ADC2 init function */ static void MX_ADC2_Init(void) { ADC_InjectionConfTypeDef sConfigInjected; /**Common config */ hadc2.Instance = ADC2; hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc2.Init.ContinuousConvMode = ENABLE; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.NbrOfConversion = 0; HAL_ADC_Init(&hadc2); /**Configure Injected Channel */ sConfigInjected.InjectedChannel = VIN_ADC2_CHANNEL; sConfigInjected.InjectedRank = ADC_INJECTED_RANK_1; sConfigInjected.InjectedNbrOfConversion = 4; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES_5; sConfigInjected.ExternalTrigInjecConv = ADC_TRIGGER; sConfigInjected.AutoInjectedConv = DISABLE; sConfigInjected.InjectedDiscontinuousConvMode = DISABLE; sConfigInjected.InjectedOffset = 0; HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2; HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); #ifdef HAS_SPLIT_POWER_PATH sConfigInjected.InjectedChannel = PD_VIN_ADC2_CHANNEL; #endif sConfigInjected.InjectedRank = ADC_INJECTED_RANK_3; HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); sConfigInjected.InjectedRank = ADC_INJECTED_RANK_4; HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected); // Run ADC internal calibration while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK) { ; } } /* IWDG init function */ static void MX_IWDG_Init(void) { hiwdg.Instance = IWDG; hiwdg.Init.Prescaler = IWDG_PRESCALER_256; hiwdg.Init.Reload = 100; #ifndef SWD_ENABLE HAL_IWDG_Init(&hiwdg); #endif } /* TIM3 init function */ static void MX_TIP_CONTROL_TIMER_Init(void) { TIM_ClockConfigTypeDef sClockSourceConfig; TIM_MasterConfigTypeDef sMasterConfig; TIM_OC_InitTypeDef sConfigOC; htimTip.Instance = TIP_CONTROL_TIMER; #ifdef TIP_HAS_DIRECT_PWM htimTip.Init.Prescaler = 100; #else htimTip.Init.Prescaler = 3; #endif htimTip.Init.CounterMode = TIM_COUNTERMODE_UP; htimTip.Init.Period = 255; // 5 Khz PWM freq htimTip.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 4mhz before div htimTip.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; // Preload the ARR register (though we dont use this) HAL_TIM_Base_Init(&htimTip); sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; HAL_TIM_ConfigClockSource(&htimTip, &sClockSourceConfig); HAL_TIM_PWM_Init(&htimTip); HAL_TIM_OC_Init(&htimTip); sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; HAL_TIMEx_MasterConfigSynchronization(&htimTip, &sMasterConfig); sConfigOC.OCMode = TIM_OCMODE_PWM1; #ifdef TIP_HAS_DIRECT_PWM sConfigOC.Pulse = 0; // PWM is direct to tip #else sConfigOC.Pulse = 127; // 50% duty cycle, that is AC coupled through the cap to provide an on signal (This does not do tip at 50% duty cycle) #endif sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; HAL_TIM_PWM_ConfigChannel(&htimTip, &sConfigOC, PWM_Out_CHANNEL); GPIO_InitTypeDef GPIO_InitStruct; /**TIM3 GPIO Configuration PWM_Out_Pin ------> TIM3_CH1 */ GPIO_InitStruct.Pin = PWM_Out_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct); #ifdef MODEL_TS100 // Remap TIM3_CH1 to be on PB4 __HAL_AFIO_REMAP_TIM3_PARTIAL(); #else // No re-map required #endif HAL_TIM_PWM_Start(&htimTip, PWM_Out_CHANNEL); } /* TIM3 init function */ static void MX_ADC_CONTROL_TIMER_Init(void) { /* * We use the channel 1 to trigger the ADC at end of PWM period * And we use the channel 4 as the PWM modulation source using Interrupts * */ TIM_ClockConfigTypeDef sClockSourceConfig; TIM_MasterConfigTypeDef sMasterConfig; TIM_OC_InitTypeDef sConfigOC; // Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC // in the PWM off time. htimADC.Instance = ADC_CONTROL_TIMER; // dummy value, will be reconfigured by BSPInit() htimADC.Init.Prescaler = 2000; // 2 MHz timer clock/2000 = 1 kHz tick rate // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow" htimADC.Init.CounterMode = TIM_COUNTERMODE_UP; // dummy value, will be reconfigured by BSPInit() htimADC.Init.Period = powerPWM + 14 * 2; htimADC.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4; // 8 MHz (x2 APB1) before divide htimADC.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; htimADC.Init.RepetitionCounter = 0; HAL_TIM_Base_Init(&htimADC); sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; HAL_TIM_ConfigClockSource(&htimADC, &sClockSourceConfig); HAL_TIM_PWM_Init(&htimADC); HAL_TIM_OC_Init(&htimADC); sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; HAL_TIMEx_MasterConfigSynchronization(&htimADC, &sMasterConfig); sConfigOC.OCMode = TIM_OCMODE_PWM1; // dummy value, will be reconfigured by BSPInit() in the BSP.cpp sConfigOC.Pulse = powerPWM + 14; // 13 -> Delay of 7 ms // 255 is the largest time period of the drive signal, and then offset ADC sample to be a bit delayed after this /* * It takes 4 milliseconds for output to be stable after PWM turns off. * Assume ADC samples in 0.5ms * We need to set this to 100% + 4.5ms * */ sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; HAL_TIM_PWM_ConfigChannel(&htimADC, &sConfigOC, TIM_CHANNEL_1); sConfigOC.Pulse = 0; // default to entirely off HAL_TIM_OC_ConfigChannel(&htimADC, &sConfigOC, TIM_CHANNEL_4); HAL_TIM_Base_Start_IT(&htimADC); HAL_TIM_PWM_Start(&htimADC, TIM_CHANNEL_1); HAL_TIM_PWM_Start_IT(&htimADC, TIM_CHANNEL_4); HAL_NVIC_SetPriority(ADC_CONTROL_TIMER_IRQ, 15, 0); HAL_NVIC_EnableIRQ(ADC_CONTROL_TIMER_IRQ); } /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); /* DMA1_Channel7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); } /** Configure pins as * Analog * Input * Output * EVENT_OUT * EXTI * Free pins are configured automatically as Analog PB0 ------> ADCx_IN8 PB1 ------> ADCx_IN9 */ static void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; /*Configure GPIO pins : PD0 PD1 */ GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); /*Configure peripheral I/O remapping */ __HAL_AFIO_REMAP_PD01_ENABLE(); //^ remap XTAL so that pins can be analog (all input buffers off). // reduces power consumption /* * Configure All pins as analog by default */ GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | #ifdef MODEL_TS100 GPIO_PIN_3 | #endif GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); #ifdef MODEL_TS100 #ifndef SWD_ENABLE /* Pull USB and SWD lines low to prevent enumeration attempts and EMI affecting * the debug core */ GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_13, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_14, GPIO_PIN_RESET); #else /* Make all lines affecting SWD floating to allow debugging */ GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_14 | GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); #endif #else /* TS80 */ /* Leave USB lines open circuit*/ #endif /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */ GPIO_InitStruct.Pin = KEY_B_Pin | KEY_A_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pin : OLED_RESET_Pin */ GPIO_InitStruct.Pin = OLED_RESET_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(OLED_RESET_GPIO_Port, &GPIO_InitStruct); // Pull down LCD reset HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_RESET); HAL_Delay(30); HAL_GPIO_WritePin(OLED_RESET_GPIO_Port, OLED_RESET_Pin, GPIO_PIN_SET); #ifdef DC_SELECT_Pin GPIO_InitStruct.Pin = DC_SELECT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(DC_SELECT_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(DC_SELECT_GPIO_Port, DC_SELECT_Pin, GPIO_PIN_RESET); #endif #ifdef PD_SELECT_Pin GPIO_InitStruct.Pin = PD_SELECT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(PD_SELECT_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(PD_SELECT_GPIO_Port, PD_SELECT_Pin, GPIO_PIN_RESET); #endif #ifdef TIP_RESISTANCE_SENSE_Pin GPIO_InitStruct.Pin = TIP_RESISTANCE_SENSE_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(TIP_RESISTANCE_SENSE_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_WritePin(TIP_RESISTANCE_SENSE_GPIO_Port, TIP_RESISTANCE_SENSE_Pin, GPIO_PIN_RESET); #endif #ifdef INT_PD_Pin GPIO_InitStruct.Pin = INT_PD_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(INT_PD_GPIO_Port, &GPIO_InitStruct); #endif } #ifdef USE_FULL_ASSERT void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); } #endif ================================================ FILE: source/Core/BSP/Miniware/Setup.h ================================================ /* * Setup.h * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #ifndef SETUP_H_ #define SETUP_H_ #include "configuration.h" #ifdef __cplusplus extern "C" { #endif #include "stm32f1xx_hal.h" extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; extern DMA_HandleTypeDef hdma_adc1; extern IWDG_HandleTypeDef hiwdg; extern TIM_HandleTypeDef htimADC; extern TIM_HandleTypeDef htimTip; void Setup_HAL(); uint16_t getADCHandleTemp(uint8_t sample); uint16_t getADCVin(uint8_t sample); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one #ifdef HAS_SPLIT_POWER_PATH uint16_t getRawDCVin(); uint16_t getRawPDVin(); #endif #ifdef __cplusplus } #endif #endif /* SETUP_H_ */ ================================================ FILE: source/Core/BSP/Miniware/Software_I2C.h ================================================ /* * Software_I2C.h * * Created on: 25 Jul 2020 * Author: Ralim */ #ifndef BSP_MINIWARE_SOFTWARE_I2C_H_ #define BSP_MINIWARE_SOFTWARE_I2C_H_ #include "BSP.h" #include "configuration.h" #include "stm32f1xx_hal.h" #ifdef I2C_SOFT_BUS_2 #define SOFT_SCL2_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET) #define SOFT_SCL2_LOW() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET) #define SOFT_SDA2_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET) #define SOFT_SDA2_LOW() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET) #define SOFT_SDA2_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SCL2_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0) #endif #ifdef I2C_SOFT_BUS_1 #define SOFT_SCL1_HIGH() HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET) #define SOFT_SCL1_LOW() HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET) #define SOFT_SDA1_HIGH() HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET) #define SOFT_SDA1_LOW() HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_RESET) #define SOFT_SDA1_READ() (HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin) == GPIO_PIN_SET ? 1 : 0) #define SOFT_SCL1_READ() (HAL_GPIO_ReadPin(SCL_GPIO_Port, SCL_Pin) == GPIO_PIN_SET ? 1 : 0) #endif #define SOFT_I2C_DELAY() \ { \ for (int xx = 0; xx < 15; xx++) { \ asm("nop"); \ } \ } // 40 ~= 100kHz; 15 gives around 250kHz or so which is fast _and_ stable #endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */ ================================================ FILE: source/Core/BSP/Miniware/Startup/startup_stm32f103t8ux.S ================================================ /** ****************************************************************************** * @file startup_stm32.s * @author Ac6 * @version V1.0.0 * @date 12-June-2014 ****************************************************************************** */ .syntax unified .cpu cortex-m3 .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2] adds r2, r2, #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex-M. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler .word PVD_IRQHandler .word TAMPER_IRQHandler .word RTC_IRQHandler .word FLASH_IRQHandler .word RCC_IRQHandler .word EXTI0_IRQHandler .word EXTI1_IRQHandler .word EXTI2_IRQHandler .word EXTI3_IRQHandler .word EXTI4_IRQHandler .word DMA1_Channel1_IRQHandler .word DMA1_Channel2_IRQHandler .word DMA1_Channel3_IRQHandler .word DMA1_Channel4_IRQHandler .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler .word ADC1_2_IRQHandler .word USB_HP_CAN1_TX_IRQHandler .word USB_LP_CAN1_RX0_IRQHandler .word CAN1_RX1_IRQHandler .word CAN1_SCE_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_IRQHandler .word TIM1_UP_IRQHandler .word TIM1_TRG_COM_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler .word TIM4_IRQHandler .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler .word I2C2_EV_IRQHandler .word I2C2_ER_IRQHandler .word SPI1_IRQHandler .word SPI2_IRQHandler .word USART1_IRQHandler .word USART2_IRQHandler .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTC_Alarm_IRQHandler .word USBWakeUp_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word BootRAM /* @0x108. This is for boot in RAM mode for STM32F10x Medium Density devices. */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMPER_IRQHandler .thumb_set TAMPER_IRQHandler,Default_Handler .weak RTC_IRQHandler .thumb_set RTC_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak USB_HP_CAN1_TX_IRQHandler .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler .weak USB_LP_CAN1_RX0_IRQHandler .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_IRQHandler .thumb_set TIM1_BRK_IRQHandler,Default_Handler .weak TIM1_UP_IRQHandler .thumb_set TIM1_UP_IRQHandler,Default_Handler .weak TIM1_TRG_COM_IRQHandler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler /************************ (C) COPYRIGHT Ac6 *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/ThermoModel.cpp ================================================ /* * ThermoModel.cpp * * Created on: 1 May 2021 * Author: Ralim */ #include "TipThermoModel.h" #include "Utils.hpp" #include "configuration.h" #ifdef TEMP_uV_LOOKUP_HAKKO const int32_t uVtoDegC[] = { // // 0, 0, // 266, 10, // 522, 20, // 770, 30, // 1010, 40, // 1244, 50, // 1473, 60, // 1697, 70, // 1917, 80, // 2135, 90, // 2351, 100, // 2566, 110, // 2780, 120, // 2994, 130, // 3209, 140, // 3426, 150, // 3644, 160, // 3865, 170, // 4088, 180, // 4314, 190, // 4544, 200, // 4777, 210, // 5014, 220, // 5255, 230, // 5500, 240, // 5750, 250, // 6003, 260, // 6261, 270, // 6523, 280, // 6789, 290, // 7059, 300, // 7332, 310, // 7609, 320, // 7889, 330, // 8171, 340, // 8456, 350, // 8742, 360, // 9030, 370, // 9319, 380, // 9607, 390, // 9896, 400, // 10183, 410, // 10468, 420, // 10750, 430, // 11029, 440, // 11304, 450, // 11573, 460, // 11835, 470, // 12091, 480, // 12337, 490, // 12575, 500, // }; #endif #ifdef TEMP_uV_LOOKUP_TS80 const int32_t uVtoDegC[] = { // // 530, 0, // 1282, 10, // 2034, 20, // 2786, 30, // 3538, 40, // 4290, 50, // 5043, 60, // 5795, 70, // 6547, 80, // 7299, 90, // 8051, 100, // 8803, 110, // 9555, 120, // 10308, 130, // 11060, 140, // 11812, 150, // 12564, 160, // 13316, 170, // 14068, 180, // 14820, 190, // 15573, 200, // 16325, 210, // 17077, 220, // 17829, 230, // 18581, 240, // 19333, 250, // 20085, 260, // 20838, 270, // 21590, 280, // 22342, 290, // 23094, 300, // 23846, 310, // 24598, 320, // 25350, 330, // 26103, 340, // 26855, 350, // 27607, 360, // 28359, 370, // 29111, 380, // 29863, 390, // 30615, 400, // 31368, 410, // 32120, 420, // 32872, 430, // 33624, 440, // 34376, 450, // 35128, 460, // 35880, 470, // 36632, 480, // 37385, 490, // 38137, 500, // }; #endif const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(uVtoDegC[0])); TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); } ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h ================================================ /** ****************************************************************************** * @file stm32f103xb.h * @author MCD Application Team * @version V4.2.0 * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f103xb * @{ */ #ifndef __STM32F103xB_H #define __STM32F103xB_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F10x Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers *********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMPER_IRQn = 2, /*!< Tamper Interrupt */ RTC_IRQn = 3, /*!< RTC global Interrupt */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm3.h" #include "system_stm32f1xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SMPR1; __IO uint32_t SMPR2; __IO uint32_t JOFR1; __IO uint32_t JOFR2; __IO uint32_t JOFR3; __IO uint32_t JOFR4; __IO uint32_t HTR; __IO uint32_t LTR; __IO uint32_t SQR1; __IO uint32_t SQR2; __IO uint32_t SQR3; __IO uint32_t JSQR; __IO uint32_t JDR1; __IO uint32_t JDR2; __IO uint32_t JDR3; __IO uint32_t JDR4; __IO uint32_t DR; } ADC_TypeDef; typedef struct { __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ uint32_t RESERVED[16]; __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ } ADC_Common_TypeDef; /** * @brief Backup Registers */ typedef struct { uint32_t RESERVED0; __IO uint32_t DR1; __IO uint32_t DR2; __IO uint32_t DR3; __IO uint32_t DR4; __IO uint32_t DR5; __IO uint32_t DR6; __IO uint32_t DR7; __IO uint32_t DR8; __IO uint32_t DR9; __IO uint32_t DR10; __IO uint32_t RTCCR; __IO uint32_t CR; __IO uint32_t CSR; } BKP_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; __IO uint32_t TDTR; __IO uint32_t TDLR; __IO uint32_t TDHR; } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; __IO uint32_t RDTR; __IO uint32_t RDLR; __IO uint32_t RDHR; } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; __IO uint32_t FR2; } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; __IO uint32_t MSR; __IO uint32_t TSR; __IO uint32_t RF0R; __IO uint32_t RF1R; __IO uint32_t IER; __IO uint32_t ESR; __IO uint32_t BTR; uint32_t RESERVED0[88]; CAN_TxMailBox_TypeDef sTxMailBox[3]; CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; uint32_t RESERVED1[12]; __IO uint32_t FMR; __IO uint32_t FM1R; uint32_t RESERVED2; __IO uint32_t FS1R; uint32_t RESERVED3; __IO uint32_t FFA1R; uint32_t RESERVED4; __IO uint32_t FA1R; uint32_t RESERVED5[8]; CAN_FilterRegister_TypeDef sFilterRegister[14]; } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; __IO uint32_t CPAR; __IO uint32_t CMAR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; __IO uint32_t IFCR; } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; __IO uint32_t EMR; __IO uint32_t RTSR; __IO uint32_t FTSR; __IO uint32_t SWIER; __IO uint32_t PR; } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; __IO uint32_t KEYR; __IO uint32_t OPTKEYR; __IO uint32_t SR; __IO uint32_t CR; __IO uint32_t AR; __IO uint32_t RESERVED; __IO uint32_t OBR; __IO uint32_t WRPR; } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint16_t RDP; __IO uint16_t USER; __IO uint16_t Data0; __IO uint16_t Data1; __IO uint16_t WRP0; __IO uint16_t WRP1; __IO uint16_t WRP2; __IO uint16_t WRP3; } OB_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t CRL; __IO uint32_t CRH; __IO uint32_t IDR; __IO uint32_t ODR; __IO uint32_t BSRR; __IO uint32_t BRR; __IO uint32_t LCKR; } GPIO_TypeDef; /** * @brief Alternate Function I/O */ typedef struct { __IO uint32_t EVCR; __IO uint32_t MAPR; __IO uint32_t EXTICR[4]; uint32_t RESERVED0; __IO uint32_t MAPR2; } AFIO_TypeDef; /** * @brief Inter Integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t OAR1; __IO uint32_t OAR2; __IO uint32_t DR; __IO uint32_t SR1; __IO uint32_t SR2; __IO uint32_t CCR; __IO uint32_t TRISE; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CSR; } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CFGR; __IO uint32_t CIR; __IO uint32_t APB2RSTR; __IO uint32_t APB1RSTR; __IO uint32_t AHBENR; __IO uint32_t APB2ENR; __IO uint32_t APB1ENR; __IO uint32_t BDCR; __IO uint32_t CSR; } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t CRH; __IO uint32_t CRL; __IO uint32_t PRLH; __IO uint32_t PRLL; __IO uint32_t DIVH; __IO uint32_t DIVL; __IO uint32_t CNTH; __IO uint32_t CNTL; __IO uint32_t ALRH; __IO uint32_t ALRL; } RTC_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; __IO uint32_t CLKCR; __IO uint32_t ARG; __IO uint32_t CMD; __I uint32_t RESPCMD; __I uint32_t RESP1; __I uint32_t RESP2; __I uint32_t RESP3; __I uint32_t RESP4; __IO uint32_t DTIMER; __IO uint32_t DLEN; __IO uint32_t DCTRL; __I uint32_t DCOUNT; __I uint32_t STA; __IO uint32_t ICR; __IO uint32_t MASK; uint32_t RESERVED0[2]; __I uint32_t FIFOCNT; uint32_t RESERVED1[13]; __IO uint32_t FIFO; } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SR; __IO uint32_t DR; __IO uint32_t CRCPR; __IO uint32_t RXCRCR; __IO uint32_t TXCRCR; __IO uint32_t I2SCFGR; } SPI_TypeDef; /** * @brief TIM Timers */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ typedef struct { __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ __IO uint16_t RESERVED2; /*!< Reserved */ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) #define SDIO_BASE (PERIPH_BASE + 0x00018000U) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ /* USB device FS */ #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *)TIM2_BASE) #define TIM3 ((TIM_TypeDef *)TIM3_BASE) #define TIM4 ((TIM_TypeDef *)TIM4_BASE) #define RTC ((RTC_TypeDef *)RTC_BASE) #define WWDG ((WWDG_TypeDef *)WWDG_BASE) #define IWDG ((IWDG_TypeDef *)IWDG_BASE) #define SPI2 ((SPI_TypeDef *)SPI2_BASE) #define USART2 ((USART_TypeDef *)USART2_BASE) #define USART3 ((USART_TypeDef *)USART3_BASE) #define I2C1 ((I2C_TypeDef *)I2C1_BASE) #define I2C2 ((I2C_TypeDef *)I2C2_BASE) #define USB ((USB_TypeDef *)USB_BASE) #define CAN1 ((CAN_TypeDef *)CAN1_BASE) #define BKP ((BKP_TypeDef *)BKP_BASE) #define PWR ((PWR_TypeDef *)PWR_BASE) #define AFIO ((AFIO_TypeDef *)AFIO_BASE) #define EXTI ((EXTI_TypeDef *)EXTI_BASE) #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) #define ADC1 ((ADC_TypeDef *)ADC1_BASE) #define ADC2 ((ADC_TypeDef *)ADC2_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) #define TIM1 ((TIM_TypeDef *)TIM1_BASE) #define SPI1 ((SPI_TypeDef *)SPI1_BASE) #define USART1 ((USART_TypeDef *)USART1_BASE) #define SDIO ((SDIO_TypeDef *)SDIO_BASE) #define DMA1 ((DMA_TypeDef *)DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) #define RCC ((RCC_TypeDef *)RCC_BASE) #define CRC ((CRC_TypeDef *)CRC_BASE) #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) #define OB ((OB_TypeDef *)OB_BASE) #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ #define PWR_CR_LPDS_Pos (0U) #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ #define PWR_CR_PDDS_Pos (1U) #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ #define PWR_CR_CWUF_Pos (2U) #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ #define PWR_CR_CSBF_Pos (3U) #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ #define PWR_CR_PVDE_Pos (4U) #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ #define PWR_CR_PLS_Pos (5U) #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ /* Legacy defines */ #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register ********************/ #define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ #define PWR_CSR_SBF_Pos (1U) #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ #define PWR_CSR_PVDO_Pos (2U) #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ #define PWR_CSR_EWUP_Pos (8U) #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ /******************************************************************************/ /* */ /* Backup registers */ /* */ /******************************************************************************/ /******************* Bit definition for BKP_DR1 register ********************/ #define BKP_DR1_D_Pos (0U) #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR2 register ********************/ #define BKP_DR2_D_Pos (0U) #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR3 register ********************/ #define BKP_DR3_D_Pos (0U) #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR4 register ********************/ #define BKP_DR4_D_Pos (0U) #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR5 register ********************/ #define BKP_DR5_D_Pos (0U) #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR6 register ********************/ #define BKP_DR6_D_Pos (0U) #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR7 register ********************/ #define BKP_DR7_D_Pos (0U) #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR8 register ********************/ #define BKP_DR8_D_Pos (0U) #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR9 register ********************/ #define BKP_DR9_D_Pos (0U) #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ /******************* Bit definition for BKP_DR10 register *******************/ #define BKP_DR10_D_Pos (0U) #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ #define RTC_BKP_NUMBER 10 /****************** Bit definition for BKP_RTCCR register *******************/ #define BKP_RTCCR_CAL_Pos (0U) #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ #define BKP_RTCCR_CCO_Pos (7U) #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ #define BKP_RTCCR_ASOE_Pos (8U) #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ #define BKP_RTCCR_ASOS_Pos (9U) #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ /******************** Bit definition for BKP_CR register ********************/ #define BKP_CR_TPE_Pos (0U) #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ #define BKP_CR_TPAL_Pos (1U) #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ /******************* Bit definition for BKP_CSR register ********************/ #define BKP_CSR_CTE_Pos (0U) #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ #define BKP_CSR_CTI_Pos (1U) #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ #define BKP_CSR_TPIE_Pos (2U) #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ #define BKP_CSR_TEF_Pos (8U) #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ #define BKP_CSR_TIF_Pos (9U) #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_HSION_Pos (0U) #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ #define RCC_CR_HSIRDY_Pos (1U) #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ #define RCC_CR_HSITRIM_Pos (3U) #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ #define RCC_CR_HSICAL_Pos (8U) #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ #define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ #define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ #define RCC_CR_HSEBYP_Pos (18U) #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ #define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ #define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ #define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ /******************* Bit definition for RCC_CFGR register *******************/ /*!< SW configuration */ #define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCC_CFGR_ADCPRE_Pos (14U) #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ #define RCC_CFGR_PLLXTPRE_Pos (17U) #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ /*!< PLLMUL configuration */ #define RCC_CFGR_PLLMULL_Pos (18U) #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ #define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ #define RCC_CFGR_PLLMULL4_Pos (19U) #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ #define RCC_CFGR_PLLMULL5_Pos (18U) #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ #define RCC_CFGR_PLLMULL6_Pos (20U) #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ #define RCC_CFGR_PLLMULL7_Pos (18U) #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ #define RCC_CFGR_PLLMULL8_Pos (19U) #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ #define RCC_CFGR_PLLMULL9_Pos (18U) #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ #define RCC_CFGR_PLLMULL10_Pos (21U) #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ #define RCC_CFGR_PLLMULL11_Pos (18U) #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ #define RCC_CFGR_PLLMULL12_Pos (19U) #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ #define RCC_CFGR_PLLMULL13_Pos (18U) #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ #define RCC_CFGR_PLLMULL14_Pos (20U) #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ #define RCC_CFGR_PLLMULL15_Pos (18U) #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ #define RCC_CFGR_PLLMULL16_Pos (19U) #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ #define RCC_CFGR_USBPRE_Pos (22U) #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ /*!< MCO configuration */ #define RCC_CFGR_MCO_Pos (24U) #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ /* Reference defines */ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!<****************** Bit definition for RCC_CIR register ********************/ #define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ #define RCC_CIR_LSERDYF_Pos (1U) #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ #define RCC_CIR_HSIRDYF_Pos (2U) #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ #define RCC_CIR_HSERDYF_Pos (3U) #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ #define RCC_CIR_PLLRDYF_Pos (4U) #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ #define RCC_CIR_CSSF_Pos (7U) #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ #define RCC_CIR_LSIRDYIE_Pos (8U) #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ #define RCC_CIR_LSERDYIE_Pos (9U) #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ #define RCC_CIR_HSIRDYIE_Pos (10U) #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ #define RCC_CIR_HSERDYIE_Pos (11U) #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ #define RCC_CIR_PLLRDYIE_Pos (12U) #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ #define RCC_CIR_LSIRDYC_Pos (16U) #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ #define RCC_CIR_LSERDYC_Pos (17U) #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ #define RCC_CIR_HSIRDYC_Pos (18U) #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ #define RCC_CIR_HSERDYC_Pos (19U) #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ #define RCC_CIR_PLLRDYC_Pos (20U) #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ #define RCC_CIR_CSSC_Pos (23U) #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ /***************** Bit definition for RCC_APB2RSTR register *****************/ #define RCC_APB2RSTR_AFIORST_Pos (0U) #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ #define RCC_APB2RSTR_IOPARST_Pos (2U) #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ #define RCC_APB2RSTR_IOPBRST_Pos (3U) #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ #define RCC_APB2RSTR_IOPCRST_Pos (4U) #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ #define RCC_APB2RSTR_IOPDRST_Pos (5U) #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ #define RCC_APB2RSTR_ADC1RST_Pos (9U) #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ #define RCC_APB2RSTR_ADC2RST_Pos (10U) #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ #define RCC_APB2RSTR_TIM1RST_Pos (11U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ #define RCC_APB2RSTR_USART1RST_Pos (14U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ #define RCC_APB2RSTR_IOPERST_Pos (6U) #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ /***************** Bit definition for RCC_APB1RSTR register *****************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ #define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ #define RCC_APB1RSTR_BKPRST_Pos (27U) #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ #define RCC_APB1RSTR_TIM4RST_Pos (2U) #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ #define RCC_APB1RSTR_USBRST_Pos (23U) #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ /****************** Bit definition for RCC_AHBENR register ******************/ #define RCC_AHBENR_DMA1EN_Pos (0U) #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ #define RCC_AHBENR_SRAMEN_Pos (2U) #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ #define RCC_AHBENR_FLITFEN_Pos (4U) #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ #define RCC_AHBENR_CRCEN_Pos (6U) #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ /****************** Bit definition for RCC_APB2ENR register *****************/ #define RCC_APB2ENR_AFIOEN_Pos (0U) #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ #define RCC_APB2ENR_IOPAEN_Pos (2U) #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ #define RCC_APB2ENR_IOPBEN_Pos (3U) #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ #define RCC_APB2ENR_IOPCEN_Pos (4U) #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ #define RCC_APB2ENR_IOPDEN_Pos (5U) #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ #define RCC_APB2ENR_ADC1EN_Pos (9U) #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ #define RCC_APB2ENR_ADC2EN_Pos (10U) #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ #define RCC_APB2ENR_TIM1EN_Pos (11U) #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ #define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ #define RCC_APB2ENR_USART1EN_Pos (14U) #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ #define RCC_APB2ENR_IOPEEN_Pos (6U) #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ /***************** Bit definition for RCC_APB1ENR register ******************/ #define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ #define RCC_APB1ENR_TIM3EN_Pos (1U) #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ #define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ #define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ #define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ #define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ #define RCC_APB1ENR_BKPEN_Pos (27U) #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ #define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ #define RCC_APB1ENR_TIM4EN_Pos (2U) #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ #define RCC_APB1ENR_SPI2EN_Pos (14U) #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ #define RCC_APB1ENR_USART3EN_Pos (18U) #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ #define RCC_APB1ENR_I2C2EN_Pos (22U) #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ #define RCC_APB1ENR_USBEN_Pos (23U) #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ /******************* Bit definition for RCC_BDCR register *******************/ #define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ #define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ #define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ #define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ #define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ /******************* Bit definition for RCC_CSR register ********************/ #define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ #define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ #define RCC_CSR_RMVF_Pos (24U) #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ #define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ #define RCC_CSR_PORRSTF_Pos (27U) #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ #define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ #define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ #define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ /******************************************************************************/ /* */ /* General Purpose and Alternate Function I/O */ /* */ /******************************************************************************/ /******************* Bit definition for GPIO_CRL register *******************/ #define GPIO_CRL_MODE_Pos (0U) #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ #define GPIO_CRL_MODE0_Pos (0U) #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ #define GPIO_CRL_MODE1_Pos (4U) #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ #define GPIO_CRL_MODE2_Pos (8U) #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ #define GPIO_CRL_MODE3_Pos (12U) #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ #define GPIO_CRL_MODE4_Pos (16U) #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ #define GPIO_CRL_MODE5_Pos (20U) #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ #define GPIO_CRL_MODE6_Pos (24U) #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ #define GPIO_CRL_MODE7_Pos (28U) #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ #define GPIO_CRL_CNF_Pos (2U) #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ #define GPIO_CRL_CNF0_Pos (2U) #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ #define GPIO_CRL_CNF1_Pos (6U) #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ #define GPIO_CRL_CNF2_Pos (10U) #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ #define GPIO_CRL_CNF3_Pos (14U) #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ #define GPIO_CRL_CNF4_Pos (18U) #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ #define GPIO_CRL_CNF5_Pos (22U) #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ #define GPIO_CRL_CNF6_Pos (26U) #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ #define GPIO_CRL_CNF7_Pos (30U) #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ /******************* Bit definition for GPIO_CRH register *******************/ #define GPIO_CRH_MODE_Pos (0U) #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ #define GPIO_CRH_MODE8_Pos (0U) #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ #define GPIO_CRH_MODE9_Pos (4U) #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ #define GPIO_CRH_MODE10_Pos (8U) #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ #define GPIO_CRH_MODE11_Pos (12U) #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ #define GPIO_CRH_MODE12_Pos (16U) #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ #define GPIO_CRH_MODE13_Pos (20U) #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ #define GPIO_CRH_MODE14_Pos (24U) #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ #define GPIO_CRH_MODE15_Pos (28U) #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ #define GPIO_CRH_CNF_Pos (2U) #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ #define GPIO_CRH_CNF8_Pos (2U) #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ #define GPIO_CRH_CNF9_Pos (6U) #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ #define GPIO_CRH_CNF10_Pos (10U) #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ #define GPIO_CRH_CNF11_Pos (14U) #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ #define GPIO_CRH_CNF12_Pos (18U) #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ #define GPIO_CRH_CNF13_Pos (22U) #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ #define GPIO_CRH_CNF14_Pos (26U) #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ #define GPIO_CRH_CNF15_Pos (30U) #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ /*!<****************** Bit definition for GPIO_IDR register *******************/ #define GPIO_IDR_IDR0_Pos (0U) #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ #define GPIO_IDR_IDR1_Pos (1U) #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ #define GPIO_IDR_IDR2_Pos (2U) #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ #define GPIO_IDR_IDR3_Pos (3U) #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ #define GPIO_IDR_IDR4_Pos (4U) #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ #define GPIO_IDR_IDR5_Pos (5U) #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ #define GPIO_IDR_IDR6_Pos (6U) #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ #define GPIO_IDR_IDR7_Pos (7U) #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ #define GPIO_IDR_IDR8_Pos (8U) #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ #define GPIO_IDR_IDR9_Pos (9U) #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ #define GPIO_IDR_IDR10_Pos (10U) #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ #define GPIO_IDR_IDR11_Pos (11U) #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ #define GPIO_IDR_IDR12_Pos (12U) #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ #define GPIO_IDR_IDR13_Pos (13U) #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ #define GPIO_IDR_IDR14_Pos (14U) #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ #define GPIO_IDR_IDR15_Pos (15U) #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ /******************* Bit definition for GPIO_ODR register *******************/ #define GPIO_ODR_ODR0_Pos (0U) #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ #define GPIO_ODR_ODR1_Pos (1U) #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ #define GPIO_ODR_ODR2_Pos (2U) #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ #define GPIO_ODR_ODR3_Pos (3U) #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ #define GPIO_ODR_ODR4_Pos (4U) #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ #define GPIO_ODR_ODR5_Pos (5U) #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ #define GPIO_ODR_ODR6_Pos (6U) #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ #define GPIO_ODR_ODR7_Pos (7U) #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ #define GPIO_ODR_ODR8_Pos (8U) #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ #define GPIO_ODR_ODR9_Pos (9U) #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ #define GPIO_ODR_ODR10_Pos (10U) #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ #define GPIO_ODR_ODR11_Pos (11U) #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ #define GPIO_ODR_ODR12_Pos (12U) #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ #define GPIO_ODR_ODR13_Pos (13U) #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ #define GPIO_ODR_ODR14_Pos (14U) #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ #define GPIO_ODR_ODR15_Pos (15U) #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ /****************** Bit definition for GPIO_BSRR register *******************/ #define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ #define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ #define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ #define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ #define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ #define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ #define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ #define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ #define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ #define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ #define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ #define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ #define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ #define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ #define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ #define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ #define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ /******************* Bit definition for GPIO_BRR register *******************/ #define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ #define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ #define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ #define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ #define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ #define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ #define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ #define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ #define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ #define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ #define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ #define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ #define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ #define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ #define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ #define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ /****************** Bit definition for GPIO_LCKR register *******************/ #define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ #define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ #define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ #define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ #define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ #define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ #define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ #define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ #define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ #define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ #define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ #define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ #define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ #define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ #define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ #define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ #define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for AFIO_EVCR register *******************/ #define AFIO_EVCR_PIN_Pos (0U) #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ #define AFIO_EVCR_PIN_PX2_Pos (1U) #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ #define AFIO_EVCR_PIN_PX3_Pos (0U) #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ #define AFIO_EVCR_PIN_PX4_Pos (2U) #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ #define AFIO_EVCR_PIN_PX5_Pos (0U) #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ #define AFIO_EVCR_PIN_PX6_Pos (1U) #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ #define AFIO_EVCR_PIN_PX7_Pos (0U) #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ #define AFIO_EVCR_PIN_PX8_Pos (3U) #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ #define AFIO_EVCR_PIN_PX9_Pos (0U) #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ #define AFIO_EVCR_PIN_PX10_Pos (1U) #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ #define AFIO_EVCR_PIN_PX11_Pos (0U) #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ #define AFIO_EVCR_PIN_PX12_Pos (2U) #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ #define AFIO_EVCR_PIN_PX13_Pos (0U) #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ #define AFIO_EVCR_PIN_PX14_Pos (1U) #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ #define AFIO_EVCR_PIN_PX15_Pos (0U) #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ #define AFIO_EVCR_PORT_Pos (4U) #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ #define AFIO_EVCR_PORT_PC_Pos (5U) #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ #define AFIO_EVCR_PORT_PD_Pos (4U) #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ #define AFIO_EVCR_PORT_PE_Pos (6U) #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ #define AFIO_EVCR_EVOE_Pos (7U) #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ /****************** Bit definition for AFIO_MAPR register *******************/ #define AFIO_MAPR_SPI1_REMAP_Pos (0U) #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ #define AFIO_MAPR_I2C1_REMAP_Pos (1U) #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ #define AFIO_MAPR_USART1_REMAP_Pos (2U) #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ #define AFIO_MAPR_USART2_REMAP_Pos (3U) #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ #define AFIO_MAPR_USART3_REMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ #define AFIO_MAPR_TIM1_REMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ #define AFIO_MAPR_TIM2_REMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ #define AFIO_MAPR_TIM3_REMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ #define AFIO_MAPR_TIM4_REMAP_Pos (12U) #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ #define AFIO_MAPR_CAN_REMAP_Pos (13U) #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ /*!< CAN_REMAP configuration */ #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ #define AFIO_MAPR_PD01_REMAP_Pos (15U) #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ /*!< SWJ_CFG configuration */ #define AFIO_MAPR_SWJ_CFG_Pos (24U) #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ /***************** Bit definition for AFIO_EXTICR1 register *****************/ #define AFIO_EXTICR1_EXTI0_Pos (0U) #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ #define AFIO_EXTICR1_EXTI1_Pos (4U) #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ #define AFIO_EXTICR1_EXTI2_Pos (8U) #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ #define AFIO_EXTICR1_EXTI3_Pos (12U) #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ /***************** Bit definition for AFIO_EXTICR2 register *****************/ #define AFIO_EXTICR2_EXTI4_Pos (0U) #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ #define AFIO_EXTICR2_EXTI5_Pos (4U) #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ #define AFIO_EXTICR2_EXTI6_Pos (8U) #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ #define AFIO_EXTICR2_EXTI7_Pos (12U) #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ /***************** Bit definition for AFIO_EXTICR3 register *****************/ #define AFIO_EXTICR3_EXTI8_Pos (0U) #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ #define AFIO_EXTICR3_EXTI9_Pos (4U) #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ #define AFIO_EXTICR3_EXTI10_Pos (8U) #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ #define AFIO_EXTICR3_EXTI11_Pos (12U) #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ /***************** Bit definition for AFIO_EXTICR4 register *****************/ #define AFIO_EXTICR4_EXTI12_Pos (0U) #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ #define AFIO_EXTICR4_EXTI13_Pos (4U) #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ #define AFIO_EXTICR4_EXTI14_Pos (8U) #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ #define AFIO_EXTICR4_EXTI15_Pos (12U) #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ /****************** Bit definition for AFIO_MAPR2 register ******************/ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ #define EXTI_IMR_MR0_Pos (0U) #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ #define EXTI_IMR_MR1_Pos (1U) #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ #define EXTI_IMR_MR2_Pos (2U) #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ #define EXTI_IMR_MR3_Pos (3U) #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ #define EXTI_IMR_MR4_Pos (4U) #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ #define EXTI_IMR_MR5_Pos (5U) #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ #define EXTI_IMR_MR6_Pos (6U) #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ #define EXTI_IMR_MR7_Pos (7U) #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ #define EXTI_IMR_MR8_Pos (8U) #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ #define EXTI_IMR_MR9_Pos (9U) #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ #define EXTI_IMR_MR10_Pos (10U) #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ #define EXTI_IMR_MR11_Pos (11U) #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ #define EXTI_IMR_MR12_Pos (12U) #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ #define EXTI_IMR_MR13_Pos (13U) #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ #define EXTI_IMR_MR14_Pos (14U) #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ #define EXTI_IMR_MR15_Pos (15U) #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ #define EXTI_IMR_MR16_Pos (16U) #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ #define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 #define EXTI_IMR_IM1 EXTI_IMR_MR1 #define EXTI_IMR_IM2 EXTI_IMR_MR2 #define EXTI_IMR_IM3 EXTI_IMR_MR3 #define EXTI_IMR_IM4 EXTI_IMR_MR4 #define EXTI_IMR_IM5 EXTI_IMR_MR5 #define EXTI_IMR_IM6 EXTI_IMR_MR6 #define EXTI_IMR_IM7 EXTI_IMR_MR7 #define EXTI_IMR_IM8 EXTI_IMR_MR8 #define EXTI_IMR_IM9 EXTI_IMR_MR9 #define EXTI_IMR_IM10 EXTI_IMR_MR10 #define EXTI_IMR_IM11 EXTI_IMR_MR11 #define EXTI_IMR_IM12 EXTI_IMR_MR12 #define EXTI_IMR_IM13 EXTI_IMR_MR13 #define EXTI_IMR_IM14 EXTI_IMR_MR14 #define EXTI_IMR_IM15 EXTI_IMR_MR15 #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ #define EXTI_EMR_MR1_Pos (1U) #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ #define EXTI_EMR_MR2_Pos (2U) #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ #define EXTI_EMR_MR3_Pos (3U) #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ #define EXTI_EMR_MR4_Pos (4U) #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ #define EXTI_EMR_MR5_Pos (5U) #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ #define EXTI_EMR_MR6_Pos (6U) #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ #define EXTI_EMR_MR7_Pos (7U) #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ #define EXTI_EMR_MR8_Pos (8U) #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ #define EXTI_EMR_MR9_Pos (9U) #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ #define EXTI_EMR_MR10_Pos (10U) #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ #define EXTI_EMR_MR11_Pos (11U) #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ #define EXTI_EMR_MR12_Pos (12U) #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ #define EXTI_EMR_MR13_Pos (13U) #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ #define EXTI_EMR_MR14_Pos (14U) #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ #define EXTI_EMR_MR15_Pos (15U) #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ #define EXTI_EMR_MR16_Pos (16U) #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ #define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ #define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 #define EXTI_EMR_EM1 EXTI_EMR_MR1 #define EXTI_EMR_EM2 EXTI_EMR_MR2 #define EXTI_EMR_EM3 EXTI_EMR_MR3 #define EXTI_EMR_EM4 EXTI_EMR_MR4 #define EXTI_EMR_EM5 EXTI_EMR_MR5 #define EXTI_EMR_EM6 EXTI_EMR_MR6 #define EXTI_EMR_EM7 EXTI_EMR_MR7 #define EXTI_EMR_EM8 EXTI_EMR_MR8 #define EXTI_EMR_EM9 EXTI_EMR_MR9 #define EXTI_EMR_EM10 EXTI_EMR_MR10 #define EXTI_EMR_EM11 EXTI_EMR_MR11 #define EXTI_EMR_EM12 EXTI_EMR_MR12 #define EXTI_EMR_EM13 EXTI_EMR_MR13 #define EXTI_EMR_EM14 EXTI_EMR_MR14 #define EXTI_EMR_EM15 EXTI_EMR_MR15 #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR1_Pos (1U) #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ #define EXTI_RTSR_TR2_Pos (2U) #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ #define EXTI_RTSR_TR3_Pos (3U) #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ #define EXTI_RTSR_TR4_Pos (4U) #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ #define EXTI_RTSR_TR5_Pos (5U) #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ #define EXTI_RTSR_TR6_Pos (6U) #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ #define EXTI_RTSR_TR7_Pos (7U) #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ #define EXTI_RTSR_TR8_Pos (8U) #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ #define EXTI_RTSR_TR9_Pos (9U) #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ #define EXTI_RTSR_TR10_Pos (10U) #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ #define EXTI_RTSR_TR11_Pos (11U) #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ #define EXTI_RTSR_TR12_Pos (12U) #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ #define EXTI_RTSR_TR13_Pos (13U) #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ #define EXTI_RTSR_TR14_Pos (14U) #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ #define EXTI_RTSR_TR15_Pos (15U) #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16_Pos (16U) #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR1_Pos (1U) #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ #define EXTI_FTSR_TR2_Pos (2U) #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ #define EXTI_FTSR_TR3_Pos (3U) #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ #define EXTI_FTSR_TR4_Pos (4U) #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ #define EXTI_FTSR_TR5_Pos (5U) #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ #define EXTI_FTSR_TR6_Pos (6U) #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ #define EXTI_FTSR_TR7_Pos (7U) #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ #define EXTI_FTSR_TR8_Pos (8U) #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ #define EXTI_FTSR_TR9_Pos (9U) #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ #define EXTI_FTSR_TR10_Pos (10U) #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ #define EXTI_FTSR_TR11_Pos (11U) #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ #define EXTI_FTSR_TR12_Pos (12U) #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ #define EXTI_FTSR_TR13_Pos (13U) #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ #define EXTI_FTSR_TR14_Pos (14U) #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ #define EXTI_FTSR_TR15_Pos (15U) #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16_Pos (16U) #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER1_Pos (1U) #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ #define EXTI_SWIER_SWIER2_Pos (2U) #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ #define EXTI_SWIER_SWIER3_Pos (3U) #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ #define EXTI_SWIER_SWIER4_Pos (4U) #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ #define EXTI_SWIER_SWIER5_Pos (5U) #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ #define EXTI_SWIER_SWIER6_Pos (6U) #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ #define EXTI_SWIER_SWIER7_Pos (7U) #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ #define EXTI_SWIER_SWIER8_Pos (8U) #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ #define EXTI_SWIER_SWIER9_Pos (9U) #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ #define EXTI_SWIER_SWIER10_Pos (10U) #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ #define EXTI_SWIER_SWIER11_Pos (11U) #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ #define EXTI_SWIER_SWIER12_Pos (12U) #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ #define EXTI_SWIER_SWIER13_Pos (13U) #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ #define EXTI_SWIER_SWIER14_Pos (14U) #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ #define EXTI_SWIER_SWIER15_Pos (15U) #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16_Pos (16U) #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ #define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ #define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ #define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ #define EXTI_PR_PR4_Pos (4U) #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ #define EXTI_PR_PR5_Pos (5U) #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ #define EXTI_PR_PR6_Pos (6U) #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ #define EXTI_PR_PR7_Pos (7U) #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ #define EXTI_PR_PR8_Pos (8U) #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ #define EXTI_PR_PR9_Pos (9U) #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ #define EXTI_PR_PR10_Pos (10U) #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ #define EXTI_PR_PR11_Pos (11U) #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ #define EXTI_PR_PR12_Pos (12U) #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ #define EXTI_PR_PR13_Pos (13U) #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ #define EXTI_PR_PR14_Pos (14U) #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ #define EXTI_PR_PR15_Pos (15U) #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ #define EXTI_PR_PR16_Pos (16U) #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ #define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ #define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 #define EXTI_PR_PIF1 EXTI_PR_PR1 #define EXTI_PR_PIF2 EXTI_PR_PR2 #define EXTI_PR_PIF3 EXTI_PR_PR3 #define EXTI_PR_PIF4 EXTI_PR_PR4 #define EXTI_PR_PIF5 EXTI_PR_PR5 #define EXTI_PR_PIF6 EXTI_PR_PR6 #define EXTI_PR_PIF7 EXTI_PR_PR7 #define EXTI_PR_PIF8 EXTI_PR_PR8 #define EXTI_PR_PIF9 EXTI_PR_PR9 #define EXTI_PR_PIF10 EXTI_PR_PR10 #define EXTI_PR_PIF11 EXTI_PR_PR11 #define EXTI_PR_PIF12 EXTI_PR_PR12 #define EXTI_PR_PIF13 EXTI_PR_PR13 #define EXTI_PR_PIF14 EXTI_PR_PR14 #define EXTI_PR_PIF15 EXTI_PR_PR15 #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 #define EXTI_PR_PIF18 EXTI_PR_PR18 /******************************************************************************/ /* */ /* DMA Controller */ /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ #define DMA_ISR_GIF1_Pos (0U) #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ #define DMA_ISR_TCIF1_Pos (1U) #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ #define DMA_ISR_HTIF1_Pos (2U) #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ #define DMA_ISR_TEIF1_Pos (3U) #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ #define DMA_ISR_GIF2_Pos (4U) #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ #define DMA_ISR_TCIF2_Pos (5U) #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ #define DMA_ISR_HTIF2_Pos (6U) #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ #define DMA_ISR_TEIF2_Pos (7U) #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ #define DMA_ISR_GIF3_Pos (8U) #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ #define DMA_ISR_TCIF3_Pos (9U) #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ #define DMA_ISR_HTIF3_Pos (10U) #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ #define DMA_ISR_TEIF3_Pos (11U) #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ #define DMA_ISR_GIF4_Pos (12U) #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ #define DMA_ISR_TCIF4_Pos (13U) #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ #define DMA_ISR_HTIF4_Pos (14U) #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ #define DMA_ISR_TEIF4_Pos (15U) #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ #define DMA_ISR_GIF5_Pos (16U) #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ #define DMA_ISR_TCIF5_Pos (17U) #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ #define DMA_ISR_HTIF5_Pos (18U) #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ #define DMA_ISR_TEIF5_Pos (19U) #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ #define DMA_ISR_GIF6_Pos (20U) #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ #define DMA_ISR_TCIF6_Pos (21U) #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ #define DMA_ISR_HTIF6_Pos (22U) #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ #define DMA_ISR_TEIF6_Pos (23U) #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ #define DMA_ISR_GIF7_Pos (24U) #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ #define DMA_ISR_TCIF7_Pos (25U) #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ #define DMA_ISR_HTIF7_Pos (26U) #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ #define DMA_ISR_TEIF7_Pos (27U) #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ #define DMA_IFCR_CGIF1_Pos (0U) #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ #define DMA_IFCR_CTCIF1_Pos (1U) #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ #define DMA_IFCR_CHTIF1_Pos (2U) #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ #define DMA_IFCR_CTEIF1_Pos (3U) #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ #define DMA_IFCR_CGIF2_Pos (4U) #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ #define DMA_IFCR_CTCIF2_Pos (5U) #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ #define DMA_IFCR_CHTIF2_Pos (6U) #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ #define DMA_IFCR_CTEIF2_Pos (7U) #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ #define DMA_IFCR_CGIF3_Pos (8U) #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ #define DMA_IFCR_CTCIF3_Pos (9U) #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ #define DMA_IFCR_CHTIF3_Pos (10U) #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ #define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ #define DMA_IFCR_CGIF4_Pos (12U) #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ #define DMA_IFCR_CTCIF4_Pos (13U) #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ #define DMA_IFCR_CHTIF4_Pos (14U) #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ #define DMA_IFCR_CTEIF4_Pos (15U) #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ #define DMA_IFCR_CGIF5_Pos (16U) #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ #define DMA_IFCR_CTCIF5_Pos (17U) #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ #define DMA_IFCR_CHTIF5_Pos (18U) #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ #define DMA_IFCR_CTEIF5_Pos (19U) #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ #define DMA_IFCR_CGIF6_Pos (20U) #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ #define DMA_IFCR_CTCIF6_Pos (21U) #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ #define DMA_IFCR_CHTIF6_Pos (22U) #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ #define DMA_IFCR_CTEIF6_Pos (23U) #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ #define DMA_IFCR_CGIF7_Pos (24U) #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ #define DMA_IFCR_CTCIF7_Pos (25U) #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ #define DMA_IFCR_CHTIF7_Pos (26U) #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ #define DMA_IFCR_CTEIF7_Pos (27U) #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register *******************/ #define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ #define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ #define DMA_CCR_HTIE_Pos (2U) #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ #define DMA_CCR_TEIE_Pos (3U) #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ #define DMA_CCR_DIR_Pos (4U) #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ #define DMA_CCR_CIRC_Pos (5U) #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ #define DMA_CCR_PINC_Pos (6U) #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ #define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ #define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ #define DMA_CCR_MSIZE_Pos (10U) #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ #define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ #define DMA_CCR_MEM2MEM_Pos (14U) #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register ******************/ #define DMA_CNDTR_NDT_Pos (0U) #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register *******************/ #define DMA_CPAR_PA_Pos (0U) #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register *******************/ #define DMA_CMAR_MA_Pos (0U) #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_SR_EOS_Pos (1U) #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_SR_JEOS_Pos (2U) #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ #define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ /* Legacy defines */ #define ADC_SR_EOC (ADC_SR_EOS) #define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ #define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ #define ADC_CR1_EOSIE_Pos (5U) #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_CR1_JEOSIE_Pos (7U) #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ #define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ #define ADC_CR1_DUALMOD_Pos (16U) #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ #define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ #define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ /* Legacy defines */ #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) /******************* Bit definition for ADC_CR2 register ********************/ #define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ #define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CR2_CAL_Pos (2U) #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ #define ADC_CR2_RSTCAL_Pos (3U) #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ #define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ #define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CR2_JEXTSEL_Pos (12U) #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ #define ADC_CR2_JEXTTRIG_Pos (15U) #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ #define ADC_CR2_EXTSEL_Pos (17U) #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ #define ADC_CR2_EXTTRIG_Pos (20U) #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ #define ADC_CR2_JSWSTART_Pos (21U) #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR2_SWSTART_Pos (22U) #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR2_TSVREFE_Pos (23U) #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /****************** Bit definition for ADC_SMPR1 register *******************/ #define ADC_SMPR1_SMP10_Pos (0U) #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP11_Pos (3U) #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP12_Pos (6U) #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP13_Pos (9U) #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP14_Pos (12U) #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP15_Pos (15U) #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP16_Pos (18U) #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP17_Pos (21U) #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ #define ADC_SMPR2_SMP0_Pos (0U) #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP1_Pos (3U) #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP2_Pos (6U) #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP3_Pos (9U) #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP4_Pos (12U) #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP5_Pos (15U) #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP6_Pos (18U) #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP7_Pos (21U) #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP8_Pos (24U) #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP9_Pos (27U) #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ #define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ #define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ #define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ #define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ #define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ13_Pos (0U) #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ #define ADC_SQR1_SQ14_Pos (5U) #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ15_Pos (10U) #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ16_Pos (15U) #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ #define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ #define ADC_SQR2_SQ7_Pos (0U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ8_Pos (5U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ9_Pos (10U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ10_Pos (15U) #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ11_Pos (20U) #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ12_Pos (25U) #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ #define ADC_SQR3_SQ1_Pos (0U) #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ2_Pos (5U) #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ3_Pos (10U) #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ4_Pos (15U) #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ5_Pos (20U) #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ6_Pos (25U) #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ #define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_ADC2DATA_Pos (16U) #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ /*****************************************************************************/ /* */ /* Timers (TIM) */ /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ #define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f1xx * @{ */ #ifndef __STM32F1XX_H #define __STM32F1XX_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /** * @brief STM32 Family */ #if !defined(STM32F1) #define STM32F1 #endif /* STM32F1 */ /* Uncomment the line below according to the target STM32L device used in your application */ #if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \ && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC) /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined(USE_HAL_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ /** * @brief CMSIS Device version number V4.2.0 */ #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC)) /** * @} */ /** @addtogroup Device_Included * @{ */ #if defined(STM32F100xB) #include "stm32f100xb.h" #elif defined(STM32F100xE) #include "stm32f100xe.h" #elif defined(STM32F101x6) #include "stm32f101x6.h" #elif defined(STM32F101xB) #include "stm32f101xb.h" #elif defined(STM32F101xE) #include "stm32f101xe.h" #elif defined(STM32F101xG) #include "stm32f101xg.h" #elif defined(STM32F102x6) #include "stm32f102x6.h" #elif defined(STM32F102xB) #include "stm32f102xb.h" #elif defined(STM32F103x6) #include "stm32f103x6.h" #elif defined(STM32F103xB) #include "stm32f103xb.h" #elif defined(STM32F103xE) #include "stm32f103xe.h" #elif defined(STM32F103xG) #include "stm32f103xg.h" #elif defined(STM32F105xC) #include "stm32f105xc.h" #elif defined(STM32F107xC) #include "stm32f107xc.h" #else #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" #endif /** * @} */ /** @addtogroup Exported_types * @{ */ typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus; /** * @} */ /** @addtogroup Exported_macros * @{ */ #define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT)) #define CLEAR_REG(REG) ((REG) = (0x0)) #define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define READ_REG(REG) ((REG)) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) /** * @} */ #if defined(USE_HAL_DRIVER) #include "stm32f1xx_hal.h" #endif /* USE_HAL_DRIVER */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32F1xx_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h ================================================ /** ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team * @version V4.2.0 * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f10x_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F10x_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F10x_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F10X_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_common_tables.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 19. October 2015 * $Revision: V.1.4.5 a * * Project: CMSIS DSP Library * Title: arm_common_tables.h * * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * * Target Processor: Cortex-M4/Cortex-M3 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ #ifndef _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H #include "arm_math.h" extern const uint16_t armBitRevTable[1024]; extern const q15_t armRecipTableQ15[64]; extern const q31_t armRecipTableQ31[64]; /* extern const q31_t realCoefAQ31[1024]; */ /* extern const q31_t realCoefBQ31[1024]; */ extern const float32_t twiddleCoef_16[32]; extern const float32_t twiddleCoef_32[64]; extern const float32_t twiddleCoef_64[128]; extern const float32_t twiddleCoef_128[256]; extern const float32_t twiddleCoef_256[512]; extern const float32_t twiddleCoef_512[1024]; extern const float32_t twiddleCoef_1024[2048]; extern const float32_t twiddleCoef_2048[4096]; extern const float32_t twiddleCoef_4096[8192]; #define twiddleCoef twiddleCoef_4096 extern const q31_t twiddleCoef_16_q31[24]; extern const q31_t twiddleCoef_32_q31[48]; extern const q31_t twiddleCoef_64_q31[96]; extern const q31_t twiddleCoef_128_q31[192]; extern const q31_t twiddleCoef_256_q31[384]; extern const q31_t twiddleCoef_512_q31[768]; extern const q31_t twiddleCoef_1024_q31[1536]; extern const q31_t twiddleCoef_2048_q31[3072]; extern const q31_t twiddleCoef_4096_q31[6144]; extern const q15_t twiddleCoef_16_q15[24]; extern const q15_t twiddleCoef_32_q15[48]; extern const q15_t twiddleCoef_64_q15[96]; extern const q15_t twiddleCoef_128_q15[192]; extern const q15_t twiddleCoef_256_q15[384]; extern const q15_t twiddleCoef_512_q15[768]; extern const q15_t twiddleCoef_1024_q15[1536]; extern const q15_t twiddleCoef_2048_q15[3072]; extern const q15_t twiddleCoef_4096_q15[6144]; extern const float32_t twiddleCoef_rfft_32[32]; extern const float32_t twiddleCoef_rfft_64[64]; extern const float32_t twiddleCoef_rfft_128[128]; extern const float32_t twiddleCoef_rfft_256[256]; extern const float32_t twiddleCoef_rfft_512[512]; extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; /* floating-point bit reversal tables */ #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20) #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48) #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; /* fixed-point bit reversal tables */ #define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12) #define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24) #define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56) #define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112) #define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240) #define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480) #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; /* Tables for Fast Math Sine and Cosine */ extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; #endif /* ARM_COMMON_TABLES_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_const_structs.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 19. March 2015 * $Revision: V.1.4.5 * * Project: CMSIS DSP Library * Title: arm_const_structs.h * * Description: This file has constant structs that are initialized for * user convenience. For example, some can be given as * arguments to the arm_cfft_f32() function. * * Target Processor: Cortex-M4/Cortex-M3 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ #ifndef _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H #include "arm_common_tables.h" #include "arm_math.h" extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; #endif ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/arm_math.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2015 ARM Limited. All rights reserved. * * $Date: 20. October 2015 * $Revision: V1.4.5 b * * Project: CMSIS DSP Library * Title: arm_math.h * * Description: Public header file for CMSIS DSP Library * * Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ /** \mainpage CMSIS DSP Software Library * * Introduction * ------------ * * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * * The library is divided into a number of functions each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions * - Filters * - Matrix functions * - Transforms * - Motor control functions * - Statistical functions * - Support functions * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, * 32-bit integer and 32-bit floating-point values. * * Using the Library * ------------ * * The library installer contains prebuilt versions of the libraries in the Lib folder. * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) * * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * * Examples * -------- * * The library ships with a number of examples which demonstrate how to use the library functions. * * Toolchain Support * ------------ * * The library has been developed and tested with MDK-ARM version 5.14.0.0 * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Building the Library * ------------ * * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. * - arm_cortexM_math.uvprojx * * * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. * * Pre-processor Macros * ------------ * * Each library project have differant pre-processor macros. * * - UNALIGNED_SUPPORT_DISABLE: * * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access * * - ARM_MATH_BIG_ENDIAN: * * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. * * - ARM_MATH_MATRIX_CHECK: * * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices * * - ARM_MATH_ROUNDING: * * Define macro ARM_MATH_ROUNDING for rounding on support functions * * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and * ARM_MATH_CM7 for building the library on cortex-M7. * * - __FPU_PRESENT: * * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries * *
* CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- * * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: * |File/Folder |Content | * |------------------------------|------------------------------------------------------------------------| * |\b CMSIS\\Documentation\\DSP | This documentation | * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | * *
* Revision History of CMSIS-DSP * ------------ * Please refer to \ref ChangeLog_pg. * * Copyright Notice * ------------ * * Copyright (C) 2010-2015 ARM Limited. All rights reserved. */ /** * @defgroup groupMath Basic Math Functions */ /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. * As compared to most of the other functions in the CMSIS math library, the fast math functions * operate on individual values and not arrays. * There are separate functions for Q15, Q31, and floating-point data. * */ /** * @defgroup groupCmplxMath Complex Math Functions * This set of functions operates on complex data vectors. * The data in the complex arrays is stored in an interleaved fashion * (real, imag, real, imag, ...). * In the API functions, the number of samples in a complex array refers * to the number of complex values; the array contains twice this number of * real values. */ /** * @defgroup groupFilters Filtering Functions */ /** * @defgroup groupMatrix Matrix Functions * * This set of functions provides basic matrix math operations. * The functions operate on matrix data structures. For example, * the type * definition for the floating-point matrix structure is shown * below: * 
 *     typedef struct
 *     {
 *       uint16_t numRows;     // number of rows of the matrix.
 *       uint16_t numCols;     // number of columns of the matrix.
 *       float32_t *pData;     // points to the data of the matrix.
 *     } arm_matrix_instance_f32;
 *
* There are similar definitions for Q15 and Q31 data types. * * The structure specifies the size of the matrix and then points to * an array of data. The array is of size numRows X numCols * and the values are arranged in row order. That is, the * matrix element (i, j) is stored at: * 
 *     pData[i*numCols + j]
 *
* * \par Init Functions * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used * then the instance structure cannot be placed into a const data section. * To place the instance structure in a const data * section, manually initialize the data structure. For example: * 
 * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
 *
* where nRows specifies the number of rows, nColumns * specifies the number of columns, and pData points to the * data array. * * \par Size Checking * By default all of the matrix functions perform size checking on the input and * output matrices. For example, the matrix addition function verifies that the * two input matrices and the output matrix all have the same number of rows and * columns. If the size check fails the functions return: * 
 *     ARM_MATH_SIZE_MISMATCH
 *
* Otherwise the functions return * 
 *     ARM_MATH_SUCCESS
 *
* There is some overhead associated with this matrix size checking. * The matrix size checking is enabled via the \#define * 
 *     ARM_MATH_MATRIX_CHECK
 *
* within the library project settings. By default this macro is defined * and size checking is enabled. By changing the project settings and * undefining this macro size checking is eliminated and the functions * run a bit faster. With size checking disabled the functions always * return ARM_MATH_SUCCESS. */ /** * @defgroup groupTransforms Transform Functions */ /** * @defgroup groupController Controller Functions */ /** * @defgroup groupStats Statistics Functions */ /** * @defgroup groupSupport Support Functions */ /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. * Linear interpolation is used for 1-dimensional data and * bilinear interpolation is used for 2-dimensional data. */ /** * @defgroup groupExamples Examples */ #ifndef _ARM_MATH_H #define _ARM_MATH_H /* ignore some GCC warnings */ #if defined(__GNUC__) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" #endif #define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined(ARM_MATH_CM7) #include "core_cm7.h" #elif defined(ARM_MATH_CM4) #include "core_cm4.h" #elif defined(ARM_MATH_CM3) #include "core_cm3.h" #elif defined(ARM_MATH_CM0) #include "core_cm0.h" #define ARM_MATH_CM0_FAMILY #elif defined(ARM_MATH_CM0PLUS) #include "core_cm0plus.h" #define ARM_MATH_CM0_FAMILY #else #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "math.h" #include "string.h" #ifdef __cplusplus extern "C" { #endif /** * @brief Macros required for reciprocal calculation in Normalized LMS */ #define DELTA_Q31 (0x100) #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #ifndef PI #define PI 3.14159265358979f #endif /** * @brief Macros required for SINE and COSINE Fast math approximations */ #define FAST_MATH_TABLE_SIZE 512 #define FAST_MATH_Q31_SHIFT (32 - 10) #define FAST_MATH_Q15_SHIFT (16 - 10) #define CONTROLLER_Q31_SHIFT (32 - 9) #define TABLE_SIZE 256 #define TABLE_SPACING_Q31 0x400000 #define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE #define ALIGN4 #else #if defined(__GNUC__) #define ALIGN4 __attribute__((aligned(4))) #else #define ALIGN4 __align(4) #endif #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. */ typedef enum { ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** * @brief 8-bit fractional data type in 1.7 format. */ typedef int8_t q7_t; /** * @brief 16-bit fractional data type in 1.15 format. */ typedef int16_t q15_t; /** * @brief 32-bit fractional data type in 1.31 format. */ typedef int32_t q31_t; /** * @brief 64-bit fractional data type in 1.63 format. */ typedef int64_t q63_t; /** * @brief 32-bit floating-point type definition. */ typedef float float32_t; /** * @brief 64-bit floating-point type definition. */ typedef double float64_t; /** * @brief definition to read/write two 16 bit values. */ #if defined __CC_ARM #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED __attribute__((unused)) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #elif defined __GNUC__ #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #elif defined __ICCARM__ #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED #elif defined __CSMC__ #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED #elif defined __TASKING__ #define __SIMD32_TYPE __unaligned int32_t #define CMSIS_UNUSED #else #error Unknown compiler #endif #define __SIMD32(addr) (*(__SIMD32_TYPE **)&(addr)) #define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr)) #define __SIMD64(addr) (*(int64_t **)&(addr)) #if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) /** * @brief definition to pack two 16 bit values. */ #define __PKHBT(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)) #define __PKHTB(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)) #endif /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN #define __PACKq7(v0, v1, v2, v3) \ ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) #else #define __PACKq7(v0, v1, v2, v3) \ ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v0) << 24) & (int32_t)0xFF000000)) #endif /** * @brief Clips Q63 to Q31 values. */ static __INLINE q31_t clip_q63_to_q31(q63_t x) { return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; } /** * @brief Clips Q63 to Q15 values. */ static __INLINE q15_t clip_q63_to_q15(q63_t x) { return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : (q15_t)(x >> 15); } /** * @brief Clips Q31 to Q7 values. */ static __INLINE q7_t clip_q31_to_q7(q31_t x) { return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; } /** * @brief Clips Q31 to Q15 values. */ static __INLINE q15_t clip_q31_to_q15(q31_t x) { return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; } /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ static __INLINE q63_t mult32x64(q63_t x, q31_t y) { return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t)(x >> 32) * y))); } /* #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) #define __CLZ __clz #endif */ /* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ #if defined(ARM_MATH_CM0_FAMILY) && ((defined(__ICCARM__))) static __INLINE uint32_t __CLZ(q31_t data); static __INLINE uint32_t __CLZ(q31_t data) { uint32_t count = 0; uint32_t mask = 0x80000000; while ((data & mask) == 0) { count += 1u; mask = mask >> 1u; } return (count); } #endif /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ static __INLINE uint32_t arm_recip_q31(q31_t in, q31_t *dst, q31_t *pRecipTable) { q31_t out; uint32_t tempVal; uint32_t index, i; uint32_t signBits; if (in > 0) { signBits = ((uint32_t)(__CLZ(in) - 1)); } else { signBits = ((uint32_t)(__CLZ(-in) - 1)); } /* Convert input sample to 1.31 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 24); index = (index & INDEX_MASK); /* 1.31 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (uint32_t)(((q63_t)in * out) >> 31); tempVal = 0x7FFFFFFFu - tempVal; /* 1.31 with exp 1 */ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ out = clip_q63_to_q31(((q63_t)out * tempVal) >> 30); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1u); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ static __INLINE uint32_t arm_recip_q15(q15_t in, q15_t *dst, q15_t *pRecipTable) { q15_t out = 0; uint32_t tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; if (in > 0) { signBits = ((uint32_t)(__CLZ(in) - 17)); } else { signBits = ((uint32_t)(__CLZ(-in) - 17)); } /* Convert input sample to 1.15 format */ in = (in << signBits); /* calculation of index for initial approximated Val */ index = (uint32_t)(in >> 8); index = (index & INDEX_MASK); /* 1.15 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (uint32_t)(((q31_t)in * out) >> 15); tempVal = 0x7FFFu - tempVal; /* 1.15 with exp 1 */ out = (q15_t)(((q31_t)out * tempVal) >> 14); /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1); } /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0_FAMILY) static __INLINE q31_t __SSAT(q31_t x, uint32_t y) { int32_t posMax, negMin; uint32_t i; posMax = 1; for (i = 0; i < (y - 1); i++) { posMax = posMax * 2; } if (x > 0) { posMax = (posMax - 1); if (x > posMax) { x = posMax; } } else { negMin = -posMax; if (x < negMin) { x = negMin; } } return (x); } #endif /* end of ARM_MATH_CM0_FAMILY */ /* * @brief C custom defined intrinsic function for M3 and M0 processors */ #if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) /* * @brief C custom defined QADD8 for M3 and M0 processors */ static __INLINE uint32_t __QADD8(uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x) >> 24) + (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); } /* * @brief C custom defined QSUB8 for M3 and M0 processors */ static __INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) { q31_t r, s, t, u; r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; u = __SSAT(((((q31_t)x) >> 24) - (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); } /* * @brief C custom defined QADD16 for M3 and M0 processors */ static __INLINE uint32_t __QADD16(uint32_t x, uint32_t y) { /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ q31_t r = 0, s = 0; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined SHADD16 for M3 and M0 processors */ static __INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined QSUB16 for M3 and M0 processors */ static __INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ static __INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined QASX for M3 and M0 processors */ static __INLINE uint32_t __QASX(uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined SHASX for M3 and M0 processors */ static __INLINE uint32_t __SHASX(uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined QSAX for M3 and M0 processors */ static __INLINE uint32_t __QSAX(uint32_t x, uint32_t y) { q31_t r, s; r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined SHSAX for M3 and M0 processors */ static __INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) { q31_t r, s; r = (((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; s = (((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; return ((uint32_t)((s << 16) | (r))); } /* * @brief C custom defined SMUSDX for M3 and M0 processors */ static __INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); } /* * @brief C custom defined SMUADX for M3 and M0 processors */ static __INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); } /* * @brief C custom defined QADD for M3 and M0 processors */ static __INLINE int32_t __QADD(int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); } /* * @brief C custom defined QSUB for M3 and M0 processors */ static __INLINE int32_t __QSUB(int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); } /* * @brief C custom defined SMLAD for M3 and M0 processors */ static __INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q31_t)sum)))); } /* * @brief C custom defined SMLADX for M3 and M0 processors */ static __INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum)))); } /* * @brief C custom defined SMLSDX for M3 and M0 processors */ static __INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum)))); } /* * @brief C custom defined SMLALD for M3 and M0 processors */ static __INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q63_t)sum)))); } /* * @brief C custom defined SMLALDX for M3 and M0 processors */ static __INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) { /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q63_t)sum)))); } /* * @brief C custom defined SMUAD for M3 and M0 processors */ static __INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); } /* * @brief C custom defined SMUSD for M3 and M0 processors */ static __INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); } /* * @brief C custom defined SXTB16 for M3 and M0 processors */ static __INLINE uint32_t __SXTB16(uint32_t x) { return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000))); } #endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ /** * @brief Instance structure for the Q7 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q7_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q7_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** * @brief Instance structure for the Q15 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q15_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** * @brief Instance structure for the Q31 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q31_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** * @brief Instance structure for the floating-point FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; /** * @brief Processing function for the Q7 FIR filter. * @param[in] S points to an instance of the Q7 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q7(const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed. */ void arm_fir_init_q7(arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. * @param[in] S points to an instance of the Q15 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if * numTaps is not a supported value. */ arm_status arm_fir_init_q15(arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. * @param[in] S points to an instance of the floating-point FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_f32(const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_f32(arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** * @brief Instance structure for the Q31 Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q31_t * pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q31_t * pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** * @brief Instance structure for the floating-point Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q15(arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_fast_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q31(arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] S points to an instance of the floating-point Biquad cascade structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df1_f32(const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df1_init_f32(arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState); /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float32_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f32; /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float64_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f64; /** * @brief Instance structure for the Q15 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q15_t * pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q15; /** * @brief Instance structure for the Q31 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q31_t * pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; /** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); /** * @brief Q15 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); /** * @brief Q31 matrix addition. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); /** * @brief Floating-point, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); /** * @brief Q15, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pScratch); /** * @brief Q31, complex, matrix multiplication. * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_cmplx_mult_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); /** * @brief Floating-point matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst); /** * @brief Q15 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst); /** * @brief Q31 matrix transpose. * @param[in] pSrc points to the input matrix * @param[out] pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst); /** * @brief Floating-point matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); /** * @brief Q15 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @param[in] pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState); /** * @brief Q31 matrix multiplication * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); /** * @brief Floating-point matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); /** * @brief Q15 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); /** * @brief Q31 matrix subtraction * @param[in] pSrcA points to the first input matrix structure * @param[in] pSrcB points to the second input matrix structure * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); /** * @brief Floating-point matrix scaling. * @param[in] pSrc points to the input matrix * @param[in] scale scale factor * @param[out] pDst points to the output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst); /** * @brief Q15 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst); /** * @brief Q31 matrix scaling. * @param[in] pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst); /** * @brief Q31 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData); /** * @brief Q15 matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData); /** * @brief Floating-point matrix initialization. * @param[in,out] S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData); /** * @brief Instance structure for the Q15 PID Control. */ typedef struct { q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #ifdef ARM_MATH_CM0_FAMILY q15_t A1; q15_t A2; #else q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif q15_t state[3]; /**< The state array of length 3. */ q15_t Kp; /**< The proportional gain. */ q15_t Ki; /**< The integral gain. */ q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** * @brief Instance structure for the Q31 PID Control. */ typedef struct { q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ q31_t A2; /**< The derived gain, A2 = Kd . */ q31_t state[3]; /**< The state array of length 3. */ q31_t Kp; /**< The proportional gain. */ q31_t Ki; /**< The integral gain. */ q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** * @brief Instance structure for the floating-point PID Control. */ typedef struct { float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ float32_t A2; /**< The derived gain, A2 = Kd . */ float32_t state[3]; /**< The state array of length 3. */ float32_t Kp; /**< The proportional gain. */ float32_t Ki; /**< The integral gain. */ float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_f32(arm_pid_instance_f32 *S, int32_t resetStateFlag); /** * @brief Reset function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure */ void arm_pid_reset_f32(arm_pid_instance_f32 *S); /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q31(arm_pid_instance_q31 *S, int32_t resetStateFlag); /** * @brief Reset function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure */ void arm_pid_reset_q31(arm_pid_instance_q31 *S); /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q15(arm_pid_instance_q15 *S, int32_t resetStateFlag); /** * @brief Reset function for the Q15 PID Control. * @param[in,out] S points to an instance of the q15 PID Control structure */ void arm_pid_reset_q15(arm_pid_instance_q15 *S); /** * @brief Instance structure for the floating-point Linear Interpolate function. */ typedef struct { uint32_t nValues; /**< nValues */ float32_t x1; /**< x1 */ float32_t xSpacing; /**< xSpacing */ float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** * @brief Instance structure for the Q31 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q31_t * pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q15_t * pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q7_t * pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; /** * @brief Q7 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); /** * @brief Q15 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); /** * @brief Q31 vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); /** * @brief Floating-point vector multiplication. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_mult_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t * pTwiddle; /**< points to the Sin twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q15; /* Deprecated */ arm_status arm_cfft_radix2_init_q15(arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q15(const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t * pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; /* Deprecated */ arm_status arm_cfft_radix4_init_q15(arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_q15(const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc); /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t * pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q31; /* Deprecated */ arm_status arm_cfft_radix2_init_q31(arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q31(const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc); /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t * pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; /* Deprecated */ void arm_cfft_radix4_q31(const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc); /* Deprecated */ arm_status arm_cfft_radix4_init_q31(arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t * pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix2_instance_f32; /* Deprecated */ arm_status arm_cfft_radix2_init_f32(arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_f32(const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t * pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /* Deprecated */ arm_status arm_cfft_radix4_init_f32(arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_f32(const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q15_t * pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q15; void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const q31_t * pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q31; void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t * pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_f32; void arm_cfft_f32(const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q15_t * pTwiddleAReal; /**< points to the real twiddle factor table. */ q15_t * pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst); /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q31_t * pTwiddleAReal; /**< points to the real twiddle factor table. */ q31_t * pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint16_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ float32_t * pTwiddleAReal; /**< points to the real twiddle factor table. */ float32_t * pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; arm_status arm_rfft_init_f32(arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_f32(const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ uint16_t fftLenRFFT; /**< length of the real sequence */ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ } arm_rfft_fast_instance_f32; arm_status arm_rfft_fast_init_f32(arm_rfft_fast_instance_f32 *S, uint16_t fftLen); void arm_rfft_fast_f32(arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, uint8_t ifftFlag); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ float32_t normalize; /**< normalizing factor. */ float32_t * pTwiddle; /**< points to the twiddle factor table. */ float32_t * pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_f32 * pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ arm_status arm_dct4_init_f32(arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize); /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_f32(const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer); /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q31_t normalize; /**< normalizing factor. */ q31_t * pTwiddle; /**< points to the twiddle factor table. */ q31_t * pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q31 * pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize); /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] S points to an instance of the Q31 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer); /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q15_t normalize; /**< normalizing factor. */ q15_t * pTwiddle; /**< points to the twiddle factor table. */ q15_t * pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q15 * pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize); /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] S points to an instance of the Q15 DCT4 structure. * @param[in] pState points to state buffer. * @param[in,out] pInlineBuffer points to the in-place input and output buffer. */ void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer); /** * @brief Floating-point vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); /** * @brief Q7 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); /** * @brief Q15 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); /** * @brief Q31 vector addition. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_add_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); /** * @brief Floating-point vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); /** * @brief Q7 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); /** * @brief Q15 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); /** * @brief Q31 vector subtraction. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in each vector */ void arm_sub_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_f32(float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize); /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q7(q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize); /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q15(q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize); /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_scale_q31(q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize); /** * @brief Q7 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Q15 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Q31 vector absolute value. * @param[in] pSrc points to the input buffer * @param[out] pDst points to the output buffer * @param[in] blockSize number of samples in each vector */ void arm_abs_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Dot product of floating-point vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result); /** * @brief Dot product of Q7 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q7(q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result); /** * @brief Dot product of Q15 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result); /** * @brief Dot product of Q31 vectors. * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] result output result returned here */ void arm_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result); /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q7(q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q15(q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_shift_q31(q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_f32(float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q7 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q7(q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q15 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q15(q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q31 vector. * @param[in] pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_offset_q31(q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q7 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q15 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q31 vector. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] blockSize number of samples in the vector */ void arm_negate_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Copies the elements of a floating-point vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q7 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_copy_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize); /** * @brief Convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_conv_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst); /** * @brief Partial convolution of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Partial convolution of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Partial convolution of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q7 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Partial convolution of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Instance structure for the Q15 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q15_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** * @brief Instance structure for the Q31 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q31_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; /** * @brief Instance structure for the floating-point FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; /** * @brief Processing function for the floating-point FIR decimator. * @param[in] S points to an instance of the floating-point FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_f32(const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_f32(arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q15 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] S points to an instance of the Q31 FIR decimator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q31(arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q15_t * pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** * @brief Instance structure for the Q31 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q31_t * pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** * @brief Instance structure for the floating-point FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q15(const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q15(arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] S points to an instance of the Q15 FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_q31(const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q31(arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] S points to an instance of the floating-point FIR interpolator structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_interpolate_f32(const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] pCoeffs points to the filter coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_f32(arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize); /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q63_t * pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ q31_t * pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; /** * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cas_df1_32x64_q31(const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cas_df1_32x64_init_q31(arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift); /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_stereo_df2T_instance_f32; /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f64; /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f32(const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_stereo_df2T_f32(const arm_biquad_cascade_stereo_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] S points to an instance of the filter data structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_biquad_cascade_df2T_f64(const arm_biquad_cascade_df2T_instance_f64 *S, float64_t *pSrc, float64_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f32(arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_stereo_df2T_init_f32(arm_biquad_cascade_stereo_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f64(arm_biquad_cascade_df2T_instance_f64 *S, uint8_t numStages, float64_t *pCoeffs, float64_t *pState); /** * @brief Instance structure for the Q15 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q15_t * pState; /**< points to the state variable array. The array is of length numStages. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** * @brief Instance structure for the Q31 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q31_t * pState; /**< points to the state variable array. The array is of length numStages. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** * @brief Instance structure for the floating-point FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q15(arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState); /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] S points to an instance of the Q15 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q15(const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q31(arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState); /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] S points to an instance of the Q31 FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_q31(const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_f32(arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState); /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] S points to an instance of the floating-point FIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] blockSize number of samples to process. */ void arm_fir_lattice_f32(const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q15_t * pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q15_t * pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q15_t * pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** * @brief Instance structure for the Q31 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q31_t * pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q31_t * pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q31_t * pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** * @brief Instance structure for the floating-point IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_f32(const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_f32(arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q31(const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_q31(arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize); /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the Q15 IIR lattice structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_q15(const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. * @param[in] pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. */ void arm_iir_lattice_init_q15(arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize); /** * @brief Instance structure for the floating-point LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; /** * @brief Processing function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_f32(const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_init_f32(arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q15 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; /** * @brief Initialization function for the Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to the coefficient buffer. * @param[in] pState points to the state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q15(arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Processing function for Q15 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q15(const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize); /** * @brief Instance structure for the Q31 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; /** * @brief Processing function for Q31 LMS filter. * @param[in] S points to an instance of the Q15 LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_q31(const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 LMS filter. * @param[in] S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q31(arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Instance structure for the floating-point normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_f32(arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_init_f32(arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q31 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q31_t * recipTable; /**< points to the reciprocal initial value table. */ q31_t energy; /**< saves previous frame energy. */ q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q31(arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q31(arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Instance structure for the Q15 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ q15_t * pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q15_t * recipTable; /**< Points to the reciprocal initial value table. */ q15_t energy; /**< saves previous frame energy. */ q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] pSrc points to the block of input data. * @param[in] pRef points to the block of reference data. * @param[out] pOut points to the block of output data. * @param[out] pErr points to the block of error data. * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q15(arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize); /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] pCoeffs points to coefficient buffer. * @param[in] pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q15(arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Correlation of floating-point sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst); /** * @brief Correlation of Q15 sequences * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch); /** * @brief Correlation of Q15 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. */ void arm_correlate_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch); /** * @brief Correlation of Q31 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_correlate_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2); /** * @brief Correlation of Q7 sequences. * @param[in] pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst); /** * @brief Instance structure for the floating-point sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t * pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** * @brief Instance structure for the Q31 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q31_t * pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q31_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** * @brief Instance structure for the Q15 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q15_t * pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q15_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** * @brief Instance structure for the Q7 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q7_t * pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q7_t * pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] S points to an instance of the floating-point sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_f32(arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_f32(arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] S points to an instance of the Q31 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q31(arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q31(arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] S points to an instance of the Q15 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q15(arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q15(arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] S points to an instance of the Q7 sparse FIR structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data * @param[in] pScratchIn points to a temporary buffer of size blockSize. * @param[in] pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q7(arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] pCoeffs points to the array of filter coefficients. * @param[in] pState points to the state buffer. * @param[in] pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q7(arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cos output. */ void arm_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCosVal); /** * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] pSinVal points to the processed sine output. * @param[out] pCosVal points to the processed cosine output. */ void arm_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal); /** * @brief Floating-point complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); /** * @brief Q31 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); /** * @brief Q15 complex conjugate. * @param[in] pSrc points to the input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude squared * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); /** * @ingroup groupController */ /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * * This set of functions implements (PID) controllers * for Q15, Q31, and floating-point data types. The functions operate on a single sample * of data and each call to the function returns a single processed value. * S points to an instance of the PID control data structure. in * is the input sample value. The functions return the output value. * * \par Algorithm: * 
 *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
 *    A0 = Kp + Ki + Kd
 *    A1 = (-Kp ) - (2 * Kd )
 *    A2 = Kd
* * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant * * \par * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. * The controller attempts to minimize the error by adjusting the process control inputs. * The proportional value determines the reaction to the current error, * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * * \par Instance Structure * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. * A separate instance structure must be defined for each PID Controller. * There are separate instance structure declarations for each of the 3 supported data types. * * \par Reset Functions * There is also an associated reset function for each data type which clears the state array. * * \par Initialization Functions * There is also an associated initialization function for each data type. * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. * - Zeros out the values in the state buffer. * * \par * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * * \par Fixed-Point Behavior * Care must be taken when using the fixed-point versions of the PID Controller functions. * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup PID * @{ */ /** * @brief Process function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ static __INLINE float32_t arm_pid_f32(arm_pid_instance_f32 *S, float32_t in) { float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q31 PID Control. * @param[in,out] S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 64-bit accumulator. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * Thus, if the accumulator result overflows it wraps around rather than clip. * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ static __INLINE q31_t arm_pid_q31(arm_pid_instance_q31 *S, q31_t in) { q63_t acc; q31_t out; /* acc = A0 * x[n] */ acc = (q63_t)S->A0 * in; /* acc += A1 * x[n-1] */ acc += (q63_t)S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ acc += (q63_t)S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ out = (q31_t)(acc >> 31u); /* out += y[n-1] */ out += S->state[2]; /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q15 PID Control. * @param[in,out] S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using a 64-bit internal accumulator. * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ static __INLINE q15_t arm_pid_q15(arm_pid_instance_q15 *S, q15_t in) { q63_t acc; q15_t out; #ifndef ARM_MATH_CM0_FAMILY __SIMD32_TYPE *vstate; /* Implementation of PID controller */ /* acc = A0 * x[n] */ acc = (q31_t)__SMUAD((uint32_t)S->A0, (uint32_t)in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ vstate = __SIMD32_CONST(S->state); acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); #else /* acc = A0 * x[n] */ acc = ((q31_t)S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc += (q31_t)S->A1 * S->state[0]; acc += (q31_t)S->A2 * S->state[1]; #endif /* acc += y[n-1] */ acc += (q31_t)S->state[2] << 15; /* saturate the output */ out = (q15_t)(__SSAT((acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @} end of PID group */ /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst); /** * @brief Floating-point matrix inverse. * @param[in] src points to the instance of the input floating-point matrix structure. * @param[out] dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f64(const arm_matrix_instance_f64 *src, arm_matrix_instance_f64 *dst); /** * @ingroup groupController */ /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents * in the two-phase orthogonal stator axis Ialpha and Ibeta. * When Ialpha is superposed with Ia as shown in the figure below * \image html clarke.gif Stator current space vector and its components in (a,b). * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta * can be calculated using only Ia and Ib. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif * where Ia and Ib are the instantaneous stator phases and * pIalpha and pIbeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup clarke * @{ */ /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta */ static __INLINE void arm_clarke_f32(float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta) { /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = ((float32_t)0.57735026919 * Ia + (float32_t)1.15470053838 * Ib); } /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_clarke_q31(q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); } /** * @} end of clarke group */ /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q31(q7_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif * where pIa and pIb are the instantaneous stator phases and * Ialpha and Ibeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_clarke * @{ */ /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b */ static __INLINE void arm_inv_clarke_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb) { /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; } /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the subtraction, hence there is no risk of overflow. */ static __INLINE void arm_inv_clarke_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); } /** * @} end of inv_clarke group */ /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] pSrc input pointer * @param[out] pDst output pointer * @param[in] blockSize number of samples to process */ void arm_q7_to_q15(q7_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif * where Ialpha and Ibeta are the stator vector components, * pId and pIq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup park * @{ */ /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * The function implements the forward Park transform. * */ static __INLINE void arm_park_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal) { /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; } /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] pId points to output rotor reference frame d * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ static __INLINE void arm_park_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); } /** * @} end of park group */ /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q7_to_float(q7_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif * where pIalpha and pIbeta are the stator vector components, * Id and Iq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_park * @{ */ /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta */ static __INLINE void arm_inv_park_f32(float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal) { /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; } /** * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_inv_park_q31(q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); } /** * @} end of Inverse park group */ /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_float(q31_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * * \par * \image html LinearInterp.gif "Linear interpolation" * * \par * A Linear Interpolate function calculates an output value(y), for the input(x) * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) * * \par Algorithm: * 
 *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
 *       where x0, x1 are nearest values of input x
 *             y0, y1 are nearest values to output y
 *
* * \par * This set of functions implements Linear interpolation process * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single * sample of data and each call to the function returns a single processed value. * S points to an instance of the Linear Interpolate function data structure. * x is the input sample value. The functions returns the output value. * * \par * if x is outside of the table boundary, Linear interpolation returns first value of the table * if x is below input range and returns last value of table if x is above range. */ /** * @addtogroup LinearInterpolate * @{ */ /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ static __INLINE float32_t arm_linear_interp_f32(arm_linear_interp_instance_f32 *S, float32_t x) { float32_t y; float32_t x0, x1; /* Nearest input values */ float32_t y0, y1; /* Nearest output values */ float32_t xSpacing = S->xSpacing; /* spacing between input values */ int32_t i; /* Index variable */ float32_t *pYData = S->pYData; /* pointer to output table */ /* Calculation of index */ i = (int32_t)((x - S->x1) / xSpacing); if (i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } else if ((uint32_t)i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues - 1]; } else { /* Calculation of nearest input values */ x0 = S->x1 + i * xSpacing; x1 = S->x1 + (i + 1) * xSpacing; /* Read of nearest output values */ y0 = pYData[i]; y1 = pYData[i + 1]; /* Calculation of output */ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); } /* returns output value */ return (y); } /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] pYData pointer to Q31 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q31_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (q31_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* shift left by 11 to keep fract in 1.31 format */ fract = (x & 0x000FFFFF) << 11; /* Read two nearest output values from the index in 1.31(q31) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 2.30 format */ y = ((q31_t)((q63_t)y0 * (0x7FFFFFFF - fract) >> 32)); /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ y += ((q31_t)(((q63_t)y1 * fract) >> 32)); /* Convert y to 1.31 format */ return (y << 1u); } } /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] pYData pointer to Q15 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) { q63_t y; /* output */ q15_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & (int32_t)0xFFF00000) >> 20); if (index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if (index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract) and y is in 13.35 format */ y = ((q63_t)y0 * (0xFFFFF - fract)); /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ y += ((q63_t)y1 * (fract)); /* convert y to 1.15 format */ return (q15_t)(y >> 20); } } /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] pYData pointer to Q7 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q7_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ uint32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ if (x < 0) { return (pYData[0]); } index = (x >> 20) & 0xfff; if (index >= (nValues - 1)) { return (pYData[nValues - 1]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index and are in 1.7(q7) format */ y0 = pYData[index]; y1 = pYData[index + 1]; /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ y = ((y0 * (0xFFFFF - fract))); /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ y += (y1 * fract); /* convert y to 1.7(q7) format */ return (q7_t)(y >> 20); } } /** * @} end of LinearInterpolate group */ /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ float32_t arm_sin_f32(float32_t x); /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q31_t arm_sin_q31(q31_t x); /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q15_t arm_sin_q15(q15_t x); /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ float32_t arm_cos_f32(float32_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q31_t arm_cos_q31(q31_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q15_t arm_cos_q15(q15_t x); /** * @ingroup groupFastMath */ /** * @defgroup SQRT Square Root * * Computes the square root of a number. * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * 
 *      x1 = x0 - f(x0)/f'(x0)
 *
* where x1 is the current estimate, * x0 is the previous estimate, and * f'(x0) is the derivative of f() evaluated at x0. * For the square root function, the algorithm reduces to: * 
 *     x0 = in/2                         [initial guess]
 *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
 *
*/ /** * @addtogroup SQRT * @{ */ /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ static __INLINE arm_status arm_sqrt_f32(float32_t in, float32_t *pOut) { if (in >= 0.0f) { #if (__FPU_USED == 1) && defined(__CC_ARM) *pOut = __sqrtf(in); #elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined(__GNUC__) *pOut = __builtin_sqrtf(in); #elif (__FPU_USED == 1) && defined(__ICCARM__) && (__VER__ >= 6040000) __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); #else *pOut = sqrtf(in); #endif return (ARM_MATH_SUCCESS); } else { *pOut = 0.0f; return (ARM_MATH_ARGUMENT_ERROR); } } /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q31(q31_t in, q31_t *pOut); /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q15(q15_t in, q15_t *pOut); /** * @} end of SQRT group */ /** * @brief floating-point Circular write function. */ static __INLINE void arm_circularWrite_f32(int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief floating-point Circular Read function. */ static __INLINE void arm_circularRead_f32(int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0u; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t)(dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (int32_t *)dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q15 Circular write function. */ static __INLINE void arm_circularWrite_q15(q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q15 Circular Read function. */ static __INLINE void arm_circularRead_q15(q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t)(dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q15_t *)dst_end) { dst = dst_base; } /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q7 Circular write function. */ static __INLINE void arm_circularWrite_q7(q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if (wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = (uint16_t)wOffset; } /** * @brief Q7 Circular Read function. */ static __INLINE void arm_circularRead_q7(q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t)(dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while (i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if (dst == (q7_t *)dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if (rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult); /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q15(q15_t *pSrc, uint32_t blockSize, q63_t *pResult); /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_power_q7(q7_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Mean value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult); /** * @brief Mean value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); /** * @brief Mean value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Mean value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_mean_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Variance of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Variance of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Variance of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_var_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_rms_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output value. */ void arm_std_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); /** * @brief Floating-point complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude * @param[in] pSrc points to the complex input vector * @param[out] pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); /** * @brief Q15 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult); /** * @brief Q31 complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult); /** * @brief Floating-point complex dot product * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] realResult real part of the result returned here * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult); /** * @brief Q15 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q15(q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples); /** * @brief Q31 complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q31(q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples); /** * @brief Floating-point complex-by-real multiplication * @param[in] pSrcCmplx points to the complex input vector * @param[in] pSrcReal points to the real input vector * @param[out] pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_f32(float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples); /** * @brief Minimum value of a Q7 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] result is output pointer * @param[in] index is the array index of the minimum value in the input buffer. */ void arm_min_q7(q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index); /** * @brief Minimum value of a Q15 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[in] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); /** * @brief Minimum value of a Q31 vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); /** * @brief Minimum value of a floating-point vector. * @param[in] pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] pResult is output pointer * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of a Q7 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of a Q15 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of a Q31 vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); /** * @brief Maximum value of a floating-point vector. * @param[in] pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] pResult maximum value returned here * @param[out] pIndex index of maximum value returned here */ void arm_max_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); /** * @brief Q15 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples); /** * @brief Q31 complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication * @param[in] pSrcA points to the first input vector * @param[in] pSrcB points to the second input vector * @param[out] pDst points to the output vector * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples); /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q31 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q31(float32_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q15 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q15(float32_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] pSrc points to the floating-point input vector * @param[out] pDst points to the Q7 output vector * @param[in] blockSize length of the input vector */ void arm_float_to_q7(float32_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q15(q31_t *pSrc, q15_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q7(q31_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_float(q15_t *pSrc, float32_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q31(q15_t *pSrc, q31_t *pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] pSrc is input pointer * @param[out] pDst is output pointer * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q7(q15_t *pSrc, q7_t *pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. * The underlying function f(x, y) is sampled on a regular grid and the interpolation process * determines values between the grid points. * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. * Bilinear interpolation is often used in image processing to rescale images. * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. * * Algorithm * \par * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. * For floating-point, the instance structure is defined as: * 
 *   typedef struct
 *   {
 *     uint16_t numRows;
 *     uint16_t numCols;
 *     float32_t *pData;
 * } arm_bilinear_interp_instance_f32;
 *
* * \par * where numRows specifies the number of rows in the table; * numCols specifies the number of columns in the table; * and pData points to an array of size numRows*numCols values. * The data table pTable is organized in row order and the supplied data values fall on integer indexes. * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. * * \par * Let (x, y) specify the desired interpolation point. Then define: * 
 *     XF = floor(x)
 *     YF = floor(y)
 *
* \par * The interpolated output point is computed as: * 
 *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
 *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
 *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
 *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
 *
* Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** * @addtogroup BilinearInterpolate * @{ */ /** * * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ static __INLINE float32_t arm_bilinear_interp_f32(const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y) { float32_t out; float32_t f00, f01, f10, f11; float32_t *pData = S->pData; int32_t xIndex, yIndex, index; float32_t xdiff, ydiff; float32_t b1, b2, b3, b4; xIndex = (int32_t)X; yIndex = (int32_t)Y; /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { return (0); } /* Calculation of index for two nearest points in X-direction */ index = (xIndex - 1) + (yIndex - 1) * S->numCols; /* Read two nearest points in X-direction */ f00 = pData[index]; f01 = pData[index + 1]; /* Calculation of index for two nearest points in Y-direction */ index = (xIndex - 1) + (yIndex)*S->numCols; /* Read two nearest points in Y-direction */ f10 = pData[index]; f11 = pData[index + 1]; /* Calculation of intermediate values */ b1 = f00; b2 = f01 - f00; b3 = f10 - f00; b4 = f00 - f01 - f10 + f11; /* Calculation of fractional part in X */ xdiff = X - xIndex; /* Calculation of fractional part in Y */ ydiff = Y - yIndex; /* Calculation of bi-linear interpolated output */ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; /* return to application */ return (out); } /** * * @brief Q31 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q31_t arm_bilinear_interp_q31(arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y) { q31_t out; /* Temporary output */ q31_t acc = 0; /* output */ q31_t xfract, yfract; /* X, Y fractional parts */ q31_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q31_t * pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* shift left xfract by 11 to keep 1.31 format */ xfract = (X & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ x1 = pYData[(rI) + (int32_t)nCols * (cI)]; x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; /* 20 bits for the fractional part */ /* shift left yfract by 11 to keep 1.31 format */ yfract = (Y & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)]; y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ out = ((q31_t)(((q63_t)x1 * (0x7FFFFFFF - xfract)) >> 32)); acc = ((q31_t)(((q63_t)out * (0x7FFFFFFF - yfract)) >> 32)); /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ out = ((q31_t)((q63_t)x2 * (0x7FFFFFFF - yfract) >> 32)); acc += ((q31_t)((q63_t)out * (xfract) >> 32)); /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t)((q63_t)y1 * (0x7FFFFFFF - xfract) >> 32)); acc += ((q31_t)((q63_t)out * (yfract) >> 32)); /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t)((q63_t)y2 * (xfract) >> 32)); acc += ((q31_t)((q63_t)out * (yfract) >> 32)); /* Convert acc to 1.31(q31) format */ return ((q31_t)(acc << 2)); } /** * @brief Q15 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q15_t arm_bilinear_interp_q15(arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q15_t x1, x2, y1, y2; /* Nearest output values */ q31_t xfract, yfract; /* X, Y fractional parts */ int32_t rI, cI; /* Row and column indices */ q15_t * pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ out = (q31_t)(((q63_t)x1 * (0xFFFFF - xfract)) >> 4u); acc = ((q63_t)out * (0xFFFFF - yfract)); /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ out = (q31_t)(((q63_t)x2 * (0xFFFFF - yfract)) >> 4u); acc += ((q63_t)out * (xfract)); /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t)(((q63_t)y1 * (0xFFFFF - xfract)) >> 4u); acc += ((q63_t)out * (yfract)); /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t)(((q63_t)y2 * (xfract)) >> 4u); acc += ((q63_t)out * (yfract)); /* acc is in 13.51 format and down shift acc by 36 times */ /* Convert out to 1.15 format */ return ((q15_t)(acc >> 36)); } /** * @brief Q7 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q7_t arm_bilinear_interp_q7(arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q31_t xfract, yfract; /* X, Y fractional parts */ q7_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q7_t * pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & (q31_t)0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & (q31_t)0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)]; x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & (q31_t)0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)]; y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ out = ((x1 * (0xFFFFF - xfract))); acc = (((q63_t)out * (0xFFFFF - yfract))); /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ out = ((x2 * (0xFFFFF - yfract))); acc += (((q63_t)out * (xfract))); /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ out = ((y1 * (0xFFFFF - xfract))); acc += (((q63_t)out * (yfract))); /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ out = ((y2 * (yfract))); acc += (((q63_t)out * (xfract))); /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ return ((q7_t)(acc >> 40)); } /** * @} end of BilinearInterpolate group */ /* SMMLAR */ #define multAcc_32x32_keep32_R(a, x, y) a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32) /* SMMLSR */ #define multSub_32x32_keep32_R(a, x, y) a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32) /* SMMULR */ #define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32) /* SMMLA */ #define multAcc_32x32_keep32(a, x, y) a += (q31_t)(((q63_t)x * y) >> 32) /* SMMLS */ #define multSub_32x32_keep32(a, x, y) a -= (q31_t)(((q63_t)x * y) >> 32) /* SMMUL */ #define mult_32x32_keep32(a, x, y) a = (q31_t)(((q63_t)x * y) >> 32) #if defined(__CC_ARM) /* Enter low optimization region - place directly above function definition */ #if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7) #define LOW_OPTIMIZATION_ENTER _Pragma("push") _Pragma("O1") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7) #define LOW_OPTIMIZATION_EXIT _Pragma("pop") #else #define LOW_OPTIMIZATION_EXIT #endif /* Enter low optimization region - place directly above function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__GNUC__) #define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1"))) #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__ICCARM__) /* Enter low optimization region - place directly above function definition */ #if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7) #define LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") #else #define LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define LOW_OPTIMIZATION_EXIT /* Enter low optimization region - place directly above function definition */ #if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7) #define IAR_ONLY_LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") #else #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #endif /* Exit low optimization region - place directly after end of function definition */ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__CSMC__) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__TASKING__) #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #endif #ifdef __cplusplus } #endif #if defined(__GNUC__) #pragma GCC diagnostic pop #endif #endif /* _ARM_MATH_H */ /** * * End of file. */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc.h ================================================ /**************************************************************************/ /** * @file cmsis_armcc.h * @brief CMSIS Cortex-M Core Function/Instruction Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return (__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return (__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return (__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return (__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return (__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return (__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return (__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return (__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return (__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1); } #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) register uint32_t __regfpscr __ASM("fpscr"); return (__regfpscr); #else return (0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #endif } #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() \ do { \ __schedule_barrier(); \ __isb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() \ do { \ __schedule_barrier(); \ __dsb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() \ do { \ __schedule_barrier(); \ __dmb(0xF); \ __schedule_barrier(); \ } while (0U) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return (result); } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t)__ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t)__ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t)__ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t)__ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) #define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U)) #endif /* (__CORTEX_M >= 0x04) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_armcc_V6.h ================================================ /**************************************************************************/ /** * @file cmsis_armcc_V6.h * @brief CMSIS Cortex-M Core Function/Instruction Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CMSIS_ARMCC_V6_H #define __CMSIS_ARMCC_V6_H /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { __ASM volatile("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { __ASM volatile("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile("MRS %0, control" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile("MRS %0, control_ns" : "=r"(result)); return (result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile("MRS %0, ipsr" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get IPSR Register (non-secure) \details Returns the content of the non-secure IPSR Register when in secure state. \return IPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) { uint32_t result; __ASM volatile("MRS %0, ipsr_ns" : "=r"(result)); return (result); } #endif /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile("MRS %0, apsr" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get APSR Register (non-secure) \details Returns the content of the non-secure APSR Register when in secure state. \return APSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) { uint32_t result; __ASM volatile("MRS %0, apsr_ns" : "=r"(result)); return (result); } #endif /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile("MRS %0, xpsr" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get xPSR Register (non-secure) \details Returns the content of the non-secure xPSR Register when in secure state. \return xPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) { uint32_t result; __ASM volatile("MRS %0, xpsr_ns" : "=r"(result)); return (result); } #endif /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile("MRS %0, psp" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) { register uint32_t result; __ASM volatile("MRS %0, psp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) : "sp"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) : "sp"); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile("MRS %0, msp" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) { register uint32_t result; __ASM volatile("MRS %0, msp_ns" : "=r"(result)); return (result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) : "sp"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) : "sp"); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile("MRS %0, primask" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, primask_ns" : "=r"(result)); return (result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); } #endif #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile("MRS %0, basepri" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); return (result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) { __ASM volatile("MSR basepri_ns, %0" : : "r"(value) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) { __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Base Priority with condition (non_secure) \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) { __ASM volatile("MSR basepri_max_ns, %0" : : "r"(value) : "memory"); } #endif /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile("MRS %0, faultmask" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); return (result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); } #endif #endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ #if (__ARM_ARCH_8M__ == 1U) /** \brief Get Process Stack Pointer Limit \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) { register uint32_t result; __ASM volatile("MRS %0, psplim" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ /** \brief Get Process Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) { register uint32_t result; __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); return (result); } #endif /** \brief Set Process Stack Pointer Limit \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); } #if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); } #endif /** \brief Get Main Stack Pointer Limit \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) { register uint32_t result; __ASM volatile("MRS %0, msplim" : "=r"(result)); return (result); } #if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ /** \brief Get Main Stack Pointer Limit (non-secure) \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) { register uint32_t result; __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); return (result); } #endif /** \brief Set Main Stack Pointer Limit \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); } #if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ /** \brief Set Main Stack Pointer Limit (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); } #endif #endif /* (__ARM_ARCH_8M__ == 1U) */ #if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ /** \brief Get FPSCR \details eturns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #define __get_FPSCR __builtin_arm_get_fpscr #if 0 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) uint32_t result; __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); __ASM volatile (""); return(result); #else return(0); #endif } #endif #if (__ARM_FEATURE_CMSE == 3U) /** \brief Get FPSCR (non-secure) \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. \return Floating Point Status/Control register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) uint32_t result; __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ __ASM volatile("VMRS %0, fpscr_ns" : "=r"(result)); __ASM volatile(""); return (result); #else return (0); #endif } #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #define __set_FPSCR __builtin_arm_set_fpscr #if 0 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); __ASM volatile (""); #endif } #endif #if (__ARM_FEATURE_CMSE == 3U) /** \brief Set FPSCR (non-secure) \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. \param [in] fpscr Floating Point Status/Control value to set */ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ __ASM volatile("VMSR fpscr_ns, %0" : : "r"(fpscr) : "vfpcc"); __ASM volatile(""); #endif } #endif #endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined(__thumb__) && !defined(__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l"(r) #define __CMSIS_GCC_USE_REG(r) "l"(r) #else #define __CMSIS_GCC_OUT_REG(r) "=r"(r) #define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF); /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF); /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __builtin_bswap32 /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ #if 0 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } #endif /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { int32_t result; __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile("bkpt " #value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); #else int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return (result); } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __builtin_clz #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t) __builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t) __builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t) __builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t) __builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t) __builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t) __builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ /*#define __SSAT __builtin_arm_ssat*/ #define __SSAT(ARG1, ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat #if 0 #define __USAT(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) #endif /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); } #endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ #if (__ARM_ARCH_8M__ == 1U) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint8_t)result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); return ((uint16_t)result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); return (result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t) __builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t) __builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t) __builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t) __builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t) __builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t) __builtin_arm_stlex #endif /* (__ARM_ARCH_8M__ == 1U) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #define __SSAT16(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) #define __USAT16(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } #define __PKHBT(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #define __PKHTB(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2)); \ else \ __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #endif /* (__ARM_FEATURE_DSP == 1U) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_V6_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/cmsis_gcc.h ================================================ /**************************************************************************/ /** * @file cmsis_gcc.h * @brief CMSIS Cortex-M Core Function/Instruction Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #if defined(__GNUC__) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { __ASM volatile("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { __ASM volatile("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile("MRS %0, control" : "=r"(result)); return (result); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile("MRS %0, ipsr" : "=r"(result)); return (result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile("MRS %0, apsr" : "=r"(result)); return (result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile("MRS %0, xpsr" : "=r"(result)); return (result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile("MRS %0, psp\n" : "=r"(result)); return (result); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack) : "sp"); } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile("MRS %0, msp\n" : "=r"(result)); return (result); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack) : "sp"); } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile("MRS %0, primask" : "=r"(result)); return (result); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); } #if (__CORTEX_M >= 0x03U) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile("MRS %0, basepri" : "=r"(result)); return (result); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) { __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile("MRS %0, faultmask" : "=r"(result)); return (result); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); } #endif /* (__CORTEX_M >= 0x03U) */ #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) uint32_t result; /* Empty asm statement works as a scheduling barrier */ __ASM volatile(""); __ASM volatile("VMRS %0, fpscr" : "=r"(result)); __ASM volatile(""); return (result); #else return (0); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) /* Empty asm statement works as a scheduling barrier */ __ASM volatile(""); __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc"); __ASM volatile(""); #endif } #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined(__thumb__) && !defined(__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l"(r) #define __CMSIS_GCC_USE_REG(r) "l"(r) #else #define __CMSIS_GCC_OUT_REG(r) "=r"(r) #define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile("nop"); } /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ __attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { __ASM volatile("wfi"); } /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ __attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { __ASM volatile("wfe"); } /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ __attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { __ASM volatile("sev"); } /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { __ASM volatile("isb 0xF" ::: "memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { __ASM volatile("dsb 0xF" ::: "memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { __ASM volatile("dmb 0xF" ::: "memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief Reverse byte order in signed short value \details Reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); #else int32_t result; __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile("bkpt " #value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); #else int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return (result); } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __builtin_clz #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr)); return (result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); return (result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); return (result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); return (result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile("clrex" ::: "memory"); } /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); return (result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint8_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); #endif return ((uint16_t)result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) { uint32_t result; __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*addr)); return (result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM volatile("strbt %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM volatile("strht %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM volatile("strt %1, %0" : "=Q"(*addr) : "r"(value)); } #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #define __SSAT16(ARG1, ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) #define __USAT16(ARG1, ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u { uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); #else /* Big endian */ __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif return (llr.w64); } __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) { int32_t result; __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); return (result); } #define __PKHBT(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) #define __PKHTB(ARG1, ARG2, ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2)); \ else \ __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ __RES; \ }) __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); return (result); } #endif /* (__CORTEX_M >= 0x04) */ /*@} end of group CMSIS_SIMD_intrinsics */ #if defined(__GNUC__) #pragma GCC diagnostic pop #endif #endif /* __CMSIS_GCC_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0.h ================================================ /**************************************************************************/ /** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M0 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm0plus.h ================================================ /**************************************************************************/ /** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M0+ Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************/ /** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x03U) /*!< Cortex-M Core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Active Interrupt \details Reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************/ /** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x04U) /*!< Cortex-M Core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if (__FPU_PRESENT == 1) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif #if (__FPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M4 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1U) #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Active Interrupt \details Reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cm7.h ================================================ /**************************************************************************/ /** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x07U) /*!< Cortex-M Core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if (__FPU_PRESENT == 1) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #if (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif #if (__FPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ /*@} end of group CMSIS_FPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M4 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1U) #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Active Interrupt \details Reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { return 2UL; /* Double + Single precision FPU */ } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { return 1UL; /* Single precision FPU */ } else { return 0UL; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_INLINE void SCB_EnableICache(void) { #if (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_INLINE void SCB_DisableICache(void) { #if (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_INLINE void SCB_InvalidateICache(void) { #if (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_INLINE void SCB_EnableDCache(void) { #if (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); #if defined(__CC_ARM) __schedule_barrier(); #endif } while (ways--); } while (sets--); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_INLINE void SCB_DisableDCache(void) { #if (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); #if defined(__CC_ARM) __schedule_barrier(); #endif } while (ways--); } while (sets--); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_INLINE void SCB_InvalidateDCache(void) { #if (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); #if defined(__CC_ARM) __schedule_barrier(); #endif } while (ways--); } while (sets--); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_INLINE void SCB_CleanDCache(void) { #if (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)); #if defined(__CC_ARM) __schedule_barrier(); #endif } while (ways--); } while (sets--); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) { #if (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); #if defined(__CC_ARM) __schedule_barrier(); #endif } while (ways--); } while (sets--); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) { #if (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCIMVAC = op_addr; op_addr += linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) { #if (__DCACHE_PRESENT == 1) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCMVAC = op_addr; op_addr += linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) { #if (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCIMVAC = op_addr; op_addr += linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmFunc.h ================================================ /**************************************************************************/ /** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /*------------------ RealView Compiler -----------------*/ #if defined(__CC_ARM) #include "cmsis_armcc.h" /*------------------ ARM Compiler V6 -------------------*/ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armcc_V6.h" /*------------------ GNU Compiler ----------------------*/ #elif defined(__GNUC__) #include "cmsis_gcc.h" /*------------------ ICC Compiler ----------------------*/ #elif defined(__ICCARM__) #include /*------------------ TI CCS Compiler -------------------*/ #elif defined(__TMS470__) #include /*------------------ TASKING Compiler ------------------*/ #elif defined(__TASKING__) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ /*------------------ COSMIC Compiler -------------------*/ #elif defined(__CSMC__) #include #endif /*@} end of CMSIS_Core_RegAccFunctions */ #endif /* __CORE_CMFUNC_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmInstr.h ================================================ /**************************************************************************/ /** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /*------------------ RealView Compiler -----------------*/ #if defined(__CC_ARM) #include "cmsis_armcc.h" /*------------------ ARM Compiler V6 -------------------*/ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armcc_V6.h" /*------------------ GNU Compiler ----------------------*/ #elif defined(__GNUC__) #include "cmsis_gcc.h" /*------------------ ICC Compiler ----------------------*/ #elif defined(__ICCARM__) #include /*------------------ TI CCS Compiler -------------------*/ #elif defined(__TMS470__) #include /*------------------ TASKING Compiler ------------------*/ #elif defined(__TASKING__) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ /*------------------ COSMIC Compiler -------------------*/ #elif defined(__CSMC__) #include #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ #endif /* __CORE_CMINSTR_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_cmSimd.h ================================================ /**************************************************************************/ /** * @file core_cmSimd.h * @brief CMSIS Cortex-M SIMD Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CMSIMD_H #define __CORE_CMSIMD_H #ifdef __cplusplus extern "C" { #endif /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ /*------------------ RealView Compiler -----------------*/ #if defined(__CC_ARM) #include "cmsis_armcc.h" /*------------------ ARM Compiler V6 -------------------*/ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armcc_V6.h" /*------------------ GNU Compiler ----------------------*/ #elif defined(__GNUC__) #include "cmsis_gcc.h" /*------------------ ICC Compiler ----------------------*/ #elif defined(__ICCARM__) #include /*------------------ TI CCS Compiler -------------------*/ #elif defined(__TMS470__) #include /*------------------ TASKING Compiler ------------------*/ #elif defined(__TASKING__) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ /*------------------ COSMIC Compiler -------------------*/ #elif defined(__CSMC__) #include #endif /*@} end of group CMSIS_SIMD_intrinsics */ #ifdef __cplusplus } #endif #endif /* __CORE_CMSIMD_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************/ /** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0 : 1; /*!< bit: 0 Reserved */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of SC000 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) #define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************/ /** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V4.30 * @date 20. October 2015 ******************************************************************************/ /* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined(__ICCARM__) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ #if defined(__CC_ARM) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined(__GNUC__) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined(__ICCARM__) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined(__TMS470__) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined(__TASKING__) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #elif defined(__CSMC__) #define __packed #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ #define __STATIC_INLINE static inline #else #error Unknown compiler #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined(__CC_ARM) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__GNUC__) #if defined(__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__ICCARM__) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TMS470__) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__TASKING__) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined(__CSMC__) #if (__CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "core_cmFunc.h" /* Core Function Access */ #include "core_cmInstr.h" /* Core Instruction Access */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1U]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. \return Masked and shifted value. */ #define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ #define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ #define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Disable External Interrupt \details Disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Pending Interrupt \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Pending Interrupt \details Sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Clear Pending Interrupt \details Clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } /** \brief Get Active Interrupt \details Reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } /** \brief Set Interrupt Priority \details Sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) < 0) { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) < 0) { return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); } else { return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL)))); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for (;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar(void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar(void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h ================================================ /** ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team * @version V1.1.1 * @date 12-May-2017 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_HAL_LEGACY #define __STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose * @{ */ #define AES_FLAG_RDERR CRYP_FLAG_RDERR #define AES_FLAG_WRERR CRYP_FLAG_WRERR #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR /** * @} */ /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ #define ADC_RESOLUTION12b ADC_RESOLUTION_12B #define ADC_RESOLUTION10b ADC_RESOLUTION_10B #define ADC_RESOLUTION8b ADC_RESOLUTION_8B #define ADC_RESOLUTION6b ADC_RESOLUTION_6B #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV #define REGULAR_GROUP ADC_REGULAR_GROUP #define INJECTED_GROUP ADC_INJECTED_GROUP #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP #define AWD_EVENT ADC_AWD_EVENT #define AWD1_EVENT ADC_AWD1_EVENT #define AWD2_EVENT ADC_AWD2_EVENT #define AWD3_EVENT ADC_AWD3_EVENT #define OVR_EVENT ADC_OVR_EVENT #define JQOVF_EVENT ADC_JQOVF_EVENT #define ALL_CHANNELS ADC_ALL_CHANNELS #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} */ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32L0) || defined(STM32L4) #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ /* to the second dedicated IO (only for COMP2). */ #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ #if defined(COMP_CSR_LOCK) #define COMP_FLAG_LOCK COMP_CSR_LOCK #elif defined(COMP_CSR_COMP1LOCK) #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK #elif defined(COMP_CSR_COMPxLOCK) #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK #endif #if defined(STM32L4) #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #endif #if defined(STM32L0) #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #else #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #endif #endif /** * @} */ /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig /** * @} */ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE /** * @} */ /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose * @{ */ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE 0x00000000U #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE /** * @} */ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 #define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE /** * @} */ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE #define OBEX_PCROP OPTIONBYTE_PCROP #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define PAGESIZE FLASH_PAGE_SIZE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 /** * @} */ /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 /** * @} */ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #else #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 #endif /** * @} */ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** * @} */ /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose * @{ */ #define GET_GPIO_SOURCE GPIO_GET_INDEX #define GET_GPIO_INDEX GPIO_GET_INDEX #if defined(STM32F4) #define GPIO_AF12_SDMMC GPIO_AF12_SDIO #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #endif #if defined(STM32F7) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32L4) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE /** * @} */ /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose * @{ */ #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose * @{ */ #define KR_KEY_RELOAD IWDG_KEY_RELOAD #define KR_KEY_ENABLE IWDG_KEY_ENABLE #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS /** * @} */ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE /** * @} */ /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ #define NOR_StatusTypedef HAL_NOR_StatusTypeDef #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS #define NOR_ONGOING HAL_NOR_STATUS_ONGOING #define NOR_ERROR HAL_NOR_STATUS_ERROR #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT #define __NOR_WRITE NOR_WRITE #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose * @{ */ #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 /** * @} */ /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} */ /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose * @{ */ /* Compact Flash-ATA registers description */ #define CF_DATA ATA_DATA #define CF_SECTOR_COUNT ATA_SECTOR_COUNT #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER #define CF_CYLINDER_LOW ATA_CYLINDER_LOW #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH #define CF_CARD_HEAD ATA_CARD_HEAD #define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT /** * @} */ /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN /** * @} */ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE /** * @} */ /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR #define TIM_DMABase_DIER TIM_DMABASE_DIER #define TIM_DMABase_SR TIM_DMABASE_SR #define TIM_DMABase_EGR TIM_DMABASE_EGR #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 #define TIM_DMABase_CCER TIM_DMABASE_CCER #define TIM_DMABase_CNT TIM_DMABASE_CNT #define TIM_DMABase_PSC TIM_DMABASE_PSC #define TIM_DMABase_ARR TIM_DMABASE_ARR #define TIM_DMABase_RCR TIM_DMABASE_RCR #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR #define TIM_DMABase_DCR TIM_DMABASE_DCR #define TIM_DMABase_DMAR TIM_DMABASE_DMAR #define TIM_DMABase_OR1 TIM_DMABASE_OR1 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 #define TIM_DMABase_OR TIM_DMABASE_OR #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS /** * @} */ /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose * @{ */ #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING /** * @} */ /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose * @{ */ #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 #define __DIV_LPUART UART_DIV_LPUART #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK /** * @} */ /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE #define USARTNACK_ENABLED USART_NACK_ENABLE #define USARTNACK_DISABLED USART_NACK_DISABLE /** * @} */ /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose * @{ */ #define CFR_BASE WWDG_CFR_BASE /** * @} */ /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose * @{ */ #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE #define CAN_TXSTATUS_FAILED ((uint8_t)0x00) #define CAN_TXSTATUS_OK ((uint8_t)0x01) #define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /** * @} */ /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ #define VLAN_TAG ETH_VLAN_TAG #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK #define ETH_MMCCR 0x00000100U #define ETH_MMCRIR 0x00000104U #define ETH_MMCTIR 0x00000108U #define ETH_MMCRIMR 0x0000010CU #define ETH_MMCTIMR 0x00000110U #define ETH_MMCTGFSCCR 0x0000014CU #define ETH_MMCTGFMSCCR 0x00000150U #define ETH_MMCTGFCR 0x00000168U #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} */ /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR #define DCMI_IT_OVF DCMI_IT_OVR #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop /** * @} */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 #define CM_RGB888 DMA2D_INPUT_RGB888 #define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 #define CM_L8 DMA2D_INPUT_L8 #define CM_AL44 DMA2D_INPUT_AL44 #define CM_AL88 DMA2D_INPUT_AL88 #define CM_L4 DMA2D_INPUT_L4 #define CM_A8 DMA2D_INPUT_A8 #define CM_A4 DMA2D_INPUT_A4 /** * @} */ #endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish /*HASH Algorithm Selection*/ #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY /** * @} */ /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) #else #define HAL_VREFINT_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose * @{ */ #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program /** * @} */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) /** * @} */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER #define PMODE_BitNumber PMODE_BIT_NUMBER #define EWUP_BitNumber EWUP_BIT_NUMBER #define FPDS_BitNumber FPDS_BIT_NUMBER #define ODEN_BitNumber ODEN_BIT_NUMBER #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ */ #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt /** * @} */ /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /* Exported macros ------------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose * @{ */ #define AES_IT_CC CRYP_IT_CC #define AES_IT_ERR CRYP_IT_ERR #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} */ /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER /** * @} */ /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ #define __ADC_ENABLE __HAL_ADC_ENABLE #define __ADC_DISABLE __HAL_ADC_DISABLE #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE #define __ADC_IS_ENABLED ADC_IS_ENABLE #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR_RK ADC_JSQR_RK #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER #define __HAL_ADC_SQR1 ADC_SQR1 #define __HAL_ADC_SMPR1 ADC_SMPR1 #define __HAL_ADC_SMPR2 ADC_SMPR2 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK #define __HAL_ADC_SQR2_RK ADC_SQR2_RK #define __HAL_ADC_SQR1_RK ADC_SQR1_RK #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ /** * @} */ /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE /** * @} */ /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 /** * @} */ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32F3) #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \ : __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \ : __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \ : __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \ : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \ : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \ : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \ : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \ : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \ : __HAL_COMP_COMP7_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \ (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \ : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \ : __HAL_COMP_COMP7_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \ : __HAL_COMP_COMP7_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \ (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \ : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \ : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) #endif #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #if defined(STM32L0) || defined(STM32L4) /* Note: On these STM32 families, the only argument of this macro */ /* is COMP_FLAG_LOCK. */ /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ /* argument. */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) #endif /** * @} */ #if defined(STM32L0) || defined(STM32L4) /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} */ #endif /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose * @{ */ #define IS_WRPAREA IS_OB_WRPAREA #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM #define IS_TYPEERASE IS_FLASH_TYPEERASE #define IS_NBSECTORS IS_FLASH_NBSECTORS #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE /** * @} */ /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE #else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE #endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST #define __HAL_I2C_SPEED I2C_SPEED #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB #define __HAL_I2C_FREQRANGE I2C_FREQRANGE /** * @} */ /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT /** * @} */ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET /** * @} */ /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \ do { \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while (0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVM_DISABLE() \ do { \ HAL_PWREx_DisablePVM1(); \ HAL_PWREx_DisablePVM2(); \ HAL_PWREx_DisablePVM3(); \ HAL_PWREx_DisablePVM4(); \ } while (0) #define __HAL_PWR_PVM_ENABLE() \ do { \ HAL_PWREx_EnablePVM1(); \ HAL_PWREx_EnablePVM2(); \ HAL_PWREx_EnablePVM3(); \ HAL_PWREx_EnablePVM4(); \ } while (0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #if defined(STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #endif #if defined(STM32F7) || defined(STM32L4) #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32H7) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() #endif #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK #define IS_RCC_HCLK_DIV IS_RCC_PCLK #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK #define RCC_IT_HSI14 RCC_IT_HSI14RDY #define RCC_IT_CSSLSE RCC_IT_LSECSS #define RCC_IT_CSSHSE RCC_IT_CSS #define RCC_PLLMUL_3 RCC_PLL_MUL3 #define RCC_PLLMUL_4 RCC_PLL_MUL4 #define RCC_PLLMUL_6 RCC_PLL_MUL6 #define RCC_PLLMUL_8 RCC_PLL_MUL8 #define RCC_PLLMUL_12 RCC_PLL_MUL12 #define RCC_PLLMUL_16 RCC_PLL_MUL16 #define RCC_PLLMUL_24 RCC_PLL_MUL24 #define RCC_PLLMUL_32 RCC_PLL_MUL32 #define RCC_PLLMUL_48 RCC_PLL_MUL48 #define RCC_PLLDIV_2 RCC_PLL_DIV2 #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 #define RCC_MCO_DIV4 RCC_MCODIV_4 #define RCC_MCO_DIV8 RCC_MCODIV_8 #define RCC_MCO_DIV16 RCC_MCODIV_16 #define RCC_MCO_DIV32 RCC_MCODIV_32 #define RCC_MCO_DIV64 RCC_MCODIV_64 #define RCC_MCO_DIV128 RCC_MCODIV_128 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE #define CR_HSION_BB RCC_CR_HSION_BB #define CR_CSSON_BB RCC_CR_CSSON_BB #define CR_PLLON_BB RCC_CR_PLLON_BB #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB #define CR_MSION_BB RCC_CR_MSION_BB #define CSR_LSION_BB RCC_CSR_LSION_BB #define CSR_LSEON_BB RCC_CSR_LSEON_BB #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB #define CR_HSEON_BB RCC_CR_HSEON_BB #define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 /** * @} */ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #if defined(STM32F1) #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \ (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) \ ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() \ : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE /** * @} */ /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn #define SDMMC1_IRQHandler SDIO_IRQHandler #endif #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose * @{ */ #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED /** * @} */ /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SPI_1LINE_TX SPI_1LINE_TX #define __HAL_SPI_1LINE_RX SPI_1LINE_RX #define __HAL_SPI_RESET_CRC SPI_RESET_CRC /** * @} */ /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose * @{ */ #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT #define __USART_ENABLE __HAL_USART_ENABLE #define __USART_DISABLE __HAL_USART_DISABLE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE /** * @} */ /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose * @{ */ #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo /** * @} */ /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** * @} */ /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose * @{ */ #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ /** * @} */ #ifdef __cplusplus } #endif #endif /* ___STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal.h * @author MCD Application Team * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_H #define __STM32F1xx_HAL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_conf.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup HAL * @{ */ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef; /** * @} */ /* Exported types ------------------------------------------------------------*/ extern uint32_t uwTickPrio; extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ */ /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode * @brief Freeze/Unfreeze Peripherals in Debug mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @{ */ /* Peripherals on APB1 */ /** * @brief TIM2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) /** * @brief TIM3 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #if defined(DBGMCU_CR_DBG_TIM4_STOP) /** * @brief TIM4 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM5_STOP) /** * @brief TIM5 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM6_STOP) /** * @brief TIM6 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM7_STOP) /** * @brief TIM7 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM12_STOP) /** * @brief TIM12 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM13_STOP) /** * @brief TIM13 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM14_STOP) /** * @brief TIM14 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #endif /** * @brief WWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) /** * @brief IWDG Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) /** * @brief I2C1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) /** * @brief I2C2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #endif #if defined(DBGMCU_CR_DBG_CAN1_STOP) /** * @brief CAN1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #endif #if defined(DBGMCU_CR_DBG_CAN2_STOP) /** * @brief CAN2 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #endif /* Peripherals on APB2 */ #if defined(DBGMCU_CR_DBG_TIM1_STOP) /** * @brief TIM1 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM8_STOP) /** * @brief TIM8 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM9_STOP) /** * @brief TIM9 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM10_STOP) /** * @brief TIM10 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM11_STOP) /** * @brief TIM11 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM15_STOP) /** * @brief TIM15 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM16_STOP) /** * @brief TIM16 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #endif #if defined(DBGMCU_CR_DBG_TIM17_STOP) /** * @brief TIM17 Peripherals Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #endif /** * @} */ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ */ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ */ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw2(void); void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); void HAL_GetUID(uint32_t *UID); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc.h * @author MCD Application Team * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_H #define __STM32F1xx_HAL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief Structure definition of ADC and regular group initialization * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of @ref ADC_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADC_Scan_mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADC_External_trigger_source_Regular */ } ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer This parameter can be a value of @ref ADC_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ } ADC_ChannelConfTypeDef; /** * @brief ADC Configuration analog watchdog definition * @note The setting of these parameters with function is conditioned to ADC state. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of @ref ADC_channels. */ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ } ADC_AnalogWDGConfTypeDef; /** * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY \ 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \ external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY \ 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \ external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** * @brief ADC handle Structure definition */ typedef struct { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC required parameters */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ } ADC_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_Error_Code ADC Error Code * @{ */ #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ #define HAL_ADC_ERROR_INTERNAL \ 0x01U /*!< ADC IP internal error: if problem of clocking, \ enable/disable, erroneous state */ #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ /** * @} */ /** @defgroup ADC_Data_align ADC data alignment * @{ */ #define ADC_DATAALIGN_RIGHT 0x00000000U #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} */ /** @defgroup ADC_Scan_mode ADC scan mode * @{ */ /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ /* compatibility with other STM32 devices having a sequencer with */ /* additional options. */ #define ADC_SCAN_DISABLE 0x00000000U #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} */ /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} */ /** @defgroup ADC_channels ADC channels * @{ */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ #define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3)) #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4)) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) // #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */ // #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */ /** * @} */ /** @defgroup ADC_sampling_times ADC sampling times * @{ */ #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1)) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2)) /*!< Sampling time 41.5 ADC clock cycles */ #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */ /** * @} */ /** @defgroup ADC_regular_rank ADC rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 0x00000001U #define ADC_REGULAR_RANK_2 0x00000002U #define ADC_REGULAR_RANK_3 0x00000003U #define ADC_REGULAR_RANK_4 0x00000004U #define ADC_REGULAR_RANK_5 0x00000005U #define ADC_REGULAR_RANK_6 0x00000006U #define ADC_REGULAR_RANK_7 0x00000007U #define ADC_REGULAR_RANK_8 0x00000008U #define ADC_REGULAR_RANK_9 0x00000009U #define ADC_REGULAR_RANK_10 0x0000000AU #define ADC_REGULAR_RANK_11 0x0000000BU #define ADC_REGULAR_RANK_12 0x0000000CU #define ADC_REGULAR_RANK_13 0x0000000DU #define ADC_REGULAR_RANK_14 0x0000000EU #define ADC_REGULAR_RANK_15 0x0000000FU #define ADC_REGULAR_RANK_16 0x00000010U /** * @} */ /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE 0x00000000U #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) /** * @} */ /** @defgroup ADC_conversion_group ADC conversion group * @{ */ #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) /** * @} */ /** @defgroup ADC_Event_type ADC Event type * @{ */ #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */ /** * @} */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ /** * @} */ /** @defgroup ADC_flags_definition ADC flags definition * @{ */ #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADC_Private_Constants ADC Private Constants * @{ */ /** @defgroup ADC_conversion_cycles ADC conversion cycles * @{ */ /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U /** * @} */ /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels * @{ */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0) #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) /** * @} */ /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ /** * @brief Enable the ADC peripheral * @note ADC enable requires a delay for ADC stabilization time * (refer to device datasheet, parameter tSTAB) * @note On STM32F1, if ADC is already enabled this macro trigs a conversion * SW start on regular group. * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** * @brief Disable the ADC peripheral * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__: ADC handle * @param __INTERRUPT__: ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected ADC's flag status. * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the ADC's pending flags * @param __HANDLE__: ADC handle * @param __FLAG__: ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) /** @brief Reset ADC handle state * @param __HANDLE__: ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) /** * @} */ /* Private macro ------------------------------------------------------------*/ /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Verification of ADC state: enabled or disabled * @param __HANDLE__: ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) /** * @brief Simultaneously clears and sets specific bits of the handle State * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__: ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Set ADC number of conversions into regular channel sequence length. * @param _NbrOfConversion_: Regular channel sequence length * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. * @param _SAMPLETIME_: Sample time parameter. * @param _CHANNELNB_: Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13))) /** * @brief Set the injected sequence length. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos) /** * @brief Set the selected injected channel rank * Note: on STM32F1 devices, channel rank position in JSQR register * is depending on total number of ranks selected into * injected sequencer (ranks sequence starting from 4-JL) * @param _CHANNELNB_: Channel number. * @param _RANKNB_: Rank number. * @param _JSQR_JL_: Sequence length. * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) /** * @brief Configures the number of discontinuous conversions for the regular group channels. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @param _SCAN_MODE_: Scan conversion mode. * @retval None */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* is equivalent to ADC_SCAN_ENABLE. */ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)) /** * @brief Get the maximum ADC conversion cycles on all channels. * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) * Approximation of sampling time within 4 ranges, returns the highest value: * below 7.5 cycles {1.5 cycle; 7.5 cycles}, * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} * equal to 239.5 cycles * Unit: ADC clock cycles * @param __HANDLE__: ADC handle * @retval ADC conversion cycles on all channels */ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)) \ ? \ \ (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \ || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \ ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 \ : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5)) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT)) #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE)) #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)) #define IS_ADC_CHANNEL(CHANNEL) \ (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5) \ || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \ || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16) \ || ((CHANNEL) == ADC_CHANNEL_17)) #define IS_ADC_SAMPLE_TIME(TIME) \ (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \ || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5)) #define IS_ADC_REGULAR_RANK(CHANNEL) \ (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5) \ || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10) \ || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \ || ((CHANNEL) == ADC_REGULAR_RANK_16)) #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) \ (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \ || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)) #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) /** @defgroup ADC_range_verification ADC range verification * For a unique ADC resolution: 12 bits * @{ */ #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) /** * @} */ /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification * @{ */ #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification * @{ */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) /** * @} */ /** * @} */ /* Include ADC HAL Extension module */ #include "stm32f1xx_hal_adc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); /** * @} */ /* IO operation functions *****************************************************/ /** @addtogroup ADC_Exported_Functions_Group2 * @{ */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADC_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ /* Peripheral State functions *************************************************/ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /* Internal HAL driver functions **********************************************/ /** @addtogroup ADC_Private_Functions * @{ */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc); void ADC_StabilizationTime(uint32_t DelayUs); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_ADC_EX_H #define __STM32F1xx_HAL_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADCEx Exported Types * @{ */ /** * @brief ADC Configuration injected Channel structure definition * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. */ typedef struct { uint32_t InjectedChannel; /*!< Selection of ADC channel to configure This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details. */ uint32_t InjectedRank; /*!< Rank in the injected group sequencer This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADC_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADCEx_External_trigger_source_Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ } ADC_InjectionConfTypeDef; #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * State of ADCs of the common group must be: disabled. */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADCEx_Common_mode Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). The equivalences are: - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ } ADC_MultiModeTypeDef; #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants * @{ */ /** @defgroup ADCEx_injected_rank ADCEx rank into injected group * @{ */ #define ADC_INJECTED_RANK_1 0x00000001U #define ADC_INJECTED_RANK_2 0x00000002U #define ADC_INJECTED_RANK_3 0x00000003U #define ADC_INJECTED_RANK_4 0x00000004U /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} */ /** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #if defined(STM32F103xE) || defined(STM32F103xG) /*!< External triggers of regular group for ADC3 only */ #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 #define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of regular group for all ADC instances */ #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_TRGO with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ /* Note for internal constant value management: If TIM8_TRGO is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_SOFTWARE_START ADC1_2_3_SWSTART /** * @} */ /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group * @{ */ /*!< List of external triggers with generic trigger name, independently of */ /* ADC target, sorted by trigger name: */ /*!< External triggers of injected group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #if defined(STM32F103xE) || defined(STM32F103xG) /*!< External triggers of injected group for ADC3 only */ #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 #endif /* STM32F103xE || defined STM32F103xG */ /*!< External triggers of injected group for all ADC instances */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC1 or ADC2, a remap of trigger must be done from */ /* EXTI line 11 to TIM8_CC4 with macro: */ /* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ /* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ /* Note for internal constant value management: If TIM8_CC4 is available, */ /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART /** * @} */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ #define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST \ ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \ phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW \ ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \ cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ #define ADC_DUALMODE_INTERLFAST \ ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \ (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_INTERLSLOW \ ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \ "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ /** * @} */ #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group * @{ */ /* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)(ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2)) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 #endif #if defined(STM32F103xE) || defined(STM32F103xG) /* External triggers of regular group for ADC3 */ #define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 #endif /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1)) #define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) /** * @} */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group * @{ */ /* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ /* instance is available on the selected device). */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif #if defined(STM32F103xE) || defined(STM32F103xG) /* External triggers of injected group for ADC3 */ #define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #endif /* STM32F103xE || defined STM32F103xG */ /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro ADCEx Private Macro * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for regular group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC EXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_CONV__: External trigger selected for regular group. * @retval External trigger to be programmed into EXTSEL bits of CR2 register */ #if defined(STM32F103xE) || defined(STM32F103xG) #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__)) #else #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief For devices with 3 ADCs: Defines the external trigger source * for injected group according to ADC into common group ADC1&ADC2 or * ADC3 (some triggers with same source have different value to * be programmed into ADC JEXTSEL bits of CR2 register). * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__: ADC handle * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. * @retval External trigger to be programmed into JEXTSEL bits of CR2 register */ #if defined(STM32F103xE) || defined(STM32F103xG) #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__)) #else #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__) #endif /* STM32F103xE || STM32F103xG */ /** * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET)) #else #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET)) #else #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET)) #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Set handle of the other ADC sharing the common multimode settings * @param __HANDLE__: ADC handle * @param __HANDLE_OTHER_ADC__: other ADC handle * @retval None */ #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2) /** * @brief Set handle of the ADC slave associated to the ADC master * On STM32F1 devices, ADC slave is always ADC2 (this can be different * on other STM32 devices) * @param __HANDLE_MASTER__: ADC master handle * @param __HANDLE_SLAVE__: ADC slave handle * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4)) #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification * @{ */ #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) /** * @} */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \ || defined(STM32F105xC) || defined(STM32F107xC) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F101xE) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F101xG) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_EXTTRIG(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \ || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \ || defined(STM32F105xC) || defined(STM32F107xC) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F101xE) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F101xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) \ (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \ || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define IS_ADC_MODE(MODE) \ (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \ || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST) \ || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG)) #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ */ /* IO operation functions *****************************************************/ /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ */ /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); /** * @} */ /* Peripheral Control functions ***********************************************/ /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_ADC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_cortex.h * @author MCD Application Team * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_CORTEX_H #define __STM32F1xx_HAL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup CORTEX * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types Cortex Exported Types * @{ */ #if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ */ typedef struct { uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ } MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 \ 0x00000007U /*!< 0 bits for pre-emption priority \ 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 \ 0x00000006U /*!< 1 bits for pre-emption priority \ 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 \ 0x00000005U /*!< 2 bits for pre-emption priority \ 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 \ 0x00000004U /*!< 3 bits for pre-emption priority \ 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 \ 0x00000003U /*!< 4 bits for pre-emption priority \ 0 bits for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /** * @} */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_DISABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported Macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) \ (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) #if (__MPU_PRESENT == 1U) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) \ (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \ || ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) \ (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \ || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) \ (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B) \ || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB) \ || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \ || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB) \ || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \ || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_CORTEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_def.h * @author MCD Application Team * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DEF #define __STM32F1xx_HAL_DEF #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx.h" #if defined(USE_HAL_LEGACY) #include "Legacy/stm32_hal_legacy.h" #endif #include /* Exported types ------------------------------------------------------------*/ /** * @brief HAL Status structures definition */ typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** * @brief HAL Lock structures definition */ typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do { \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while (0U) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * In this later function, when the Handle's "State" field is set to 0, it will execute the function * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1U) /* Reserved for future use */ #error "USE_RTOS should be 0 in the current HAL release" #else #define __HAL_LOCK(__HANDLE__) \ do { \ if ((__HANDLE__)->Lock == HAL_LOCKED) { \ return HAL_BUSY; \ } else { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ } while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do { \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ } while (0U) #endif /* USE_RTOS */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__((aligned(4))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined(__CC_ARM) /* ARM Compiler */ #define __ALIGN_BEGIN __align(4) #elif defined(__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** * @brief __RAM_FUNC definition */ #if defined(__CC_ARM) /* ARM Compiler ------------ RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ #define __RAM_FUNC #elif defined(__ICCARM__) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc #elif defined(__GNUC__) /* GNU Compiler ------------ RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif /** * @brief __NOINLINE definition */ #if defined(__CC_ARM) || defined(__GNUC__) /* ARM & GNUCompiler ---------------- */ #define __NOINLINE __attribute__((noinline)) #elif defined(__ICCARM__) /* ICCARM Compiler --------------- */ #define __NOINLINE _Pragma("optimize = no_inline") #endif #ifdef __cplusplus } #endif #endif /* ___STM32F1xx_HAL_DEF */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma.h * @author MCD Application Team * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_H #define __STM32F1xx_HAL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ /** * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** * @brief HAL DMA State structures definition */ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ } HAL_DMA_StateTypeDef; /** * @brief HAL DMA Error Code structure definition */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ } HAL_DMA_LevelCompleteTypeDef; /** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ } HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ HAL_LockTypeDef Lock; /*!< DMA locking object */ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ uint32_t ChannelIndex; /*!< DMA Channel Index */ } DMA_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code * @{ */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} */ /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** * @} */ /** @defgroup DMA_Priority_level DMA Priority level * @{ */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) /** * @} */ /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ #define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_TE6 0x00800000U #define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_TE7 0x08000000U /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ /** @brief Reset DMA handle state. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /* Interrupt & Flag management */ /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) /** * @brief Disable the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) /** * @brief Check whether the specified DMA Channel interrupt is enabled or not. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__: DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) /** * @} */ /* Include DMA HAL Extension module */ #include "stm32f1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ */ /** @addtogroup DMA_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @{ */ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE)) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE)) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD)) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD)) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma_ex.h * @author MCD Application Team * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_EX_H #define __STM32F1xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup DMAEx DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros * @{ */ /* Interrupt & Flag management */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices * @{ */ /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TC7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 \ : DMA_FLAG_TC5) /** * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_HT7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 \ : DMA_FLAG_HT5) /** * @brief Returns the current DMA Channel transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TE7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 \ : DMA_FLAG_TE5) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_GL7 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 \ : DMA_FLAG_GL5) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) /** * @brief Clears the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) /** * @} */ #else /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices * @{ */ /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TC1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \ : DMA_FLAG_TC7) /** * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_HT1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \ : DMA_FLAG_HT7) /** * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_TE1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \ : DMA_FLAG_TE7) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1)) ? DMA_FLAG_GL1 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \ : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \ : DMA_FLAG_GL7) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) /** * @brief Clear the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) /** * @} */ #endif /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ /* STM32F103xG || STM32F105xC || STM32F107xC */ #endif /* __STM32F1xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash.h * @author MCD Application Team * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_FLASH_H #define __STM32F1xx_HAL_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Constants * @{ */ #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ /** * @} */ /** @addtogroup FLASH_Private_Macros * @{ */ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) #if defined(FLASH_ACR_LATENCY) #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2)) #else #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #endif /* FLASH_ACR_LATENCY */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ /** * @brief FLASH Procedure structure definition */ typedef enum { FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U, FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U } FLASH_ProcedureTypeDef; /** * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ HAL_LockTypeDef Lock; /*!< FLASH locking object */ __IO uint32_t ErrorCode; /*!< FLASH error code This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ /** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ */ #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ /** * @} */ /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) /** * @brief Disable the FLASH half cycle access. * @note half cycle access can only be used with a low-frequency clock of less than 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. * @retval None */ #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) /** * @} */ #if defined(FLASH_ACR_LATENCY) /** @defgroup FLASH_EM_Latency FLASH Latency * @brief macros to handle FLASH Latency * @{ */ /** * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__)) /** * @brief Get the FLASH Latency. * @retval FLASH Latency * The value of this parameter depend on device used within the same series */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** * @} */ #endif /* FLASH_ACR_LATENCY */ /** @defgroup FLASH_Prefetch FLASH Prefetch * @brief macros to handle FLASH Prefetch buffer * @{ */ /** * @brief Enable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) /** * @brief Disable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) /** * @} */ /** * @} */ /* Include FLASH HAL Extended module */ #include "stm32f1xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler function */ void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); void HAL_FLASH_OB_Launch(void); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_FLASH_GetError(void); /** * @} */ /** * @} */ /* Private function -------------------------------------------------*/ /** @addtogroup FLASH_Private_Functions * @{ */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined(FLASH_BANK2_END) HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); #endif /* FLASH_BANK2_END */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_FLASH_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_FLASH_EX_H #define __STM32F1xx_HAL_FLASH_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup FLASHEx * @{ */ /** @addtogroup FLASHEx_Private_Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U #define OBR_REG_INDEX 1U #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) /** * @} */ /** @addtogroup FLASHEx_Private_Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) #if defined(FLASH_BANK2_END) #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) #endif /* FLASH_BANK2_END */ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU)) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU)))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU)) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) #define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) \ ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU))) #endif /* STM32F105xC || STM32F107xC */ #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #if defined(FLASH_BANK2_END) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH)) #else #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) #endif /* FLASH_BANK2_END */ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) \ ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) \ (((ADDRESS) >= FLASH_BASE) \ && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \ : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types * @{ */ /** * @brief FLASH Erase structure definition */ typedef struct { uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. This parameter must be a value of @ref FLASHEx_Banks */ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END (x = 1 or 2 depending on devices)*/ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ } FLASH_EraseInitTypeDef; /** * @brief FLASH Options bytes program structure definition */ typedef struct { uint32_t OptionType; /*!< OptionType: Option byte to be configured. This parameter can be a value of @ref FLASHEx_OB_Type */ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_OB_WRP_State */ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ #if defined(FLASH_BANK2_END) uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ #else uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY */ #endif /* FLASH_BANK2_END */ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of @ref FLASHEx_OB_Data_Address */ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ } FLASH_OBProgramInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ */ /** @defgroup FLASHEx_Constants FLASH Constants * @{ */ /** @defgroup FLASHEx_Page_Size Page Size * @{ */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) #define FLASH_PAGE_SIZE 0x400U #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) #define FLASH_PAGE_SIZE 0x800U #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup FLASHEx_Type_Erase Type Erase * @{ */ #define FLASH_TYPEERASE_PAGES 0x00U /*!CR, ((__INTERRUPT__)&0x0000FFFFU)); \ /* Enable Bank2 IT */ \ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ } while (0U) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) \ do { \ /* Disable Bank1 IT */ \ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \ /* Disable Bank2 IT */ \ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ } while (0U) /** * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) \ (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U)))) /** * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \ do { \ /* Clear FLASH_FLAG_OPTVERR flag */ \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ } else { \ /* Clear Flag in Bank1 */ \ if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \ FLASH->SR = ((__FLAG__)&SR_FLAG_MASK); \ } \ /* Clear Flag in Bank2 */ \ if (((__FLAG__) >> 16U) != RESET) { \ FLASH->SR2 = ((__FLAG__) >> 16U); \ } \ } \ } while (0U) #else /** * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) /** * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_BSY FLASH Busy flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__))) /** * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) \ do { \ /* Clear FLASH_FLAG_OPTVERR flag */ \ if ((__FLAG__) == FLASH_FLAG_OPTVERR) { \ CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \ } else { \ /* Clear Flag in Bank1 */ \ FLASH->SR = (__FLAG__); \ } \ } while (0U) #endif /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); /** * @} */ /** @addtogroup FLASHEx_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_FLASH_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio.h * @author MCD Application Team * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_H #define __STM32F1xx_HAL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull_define */ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ } GPIO_InitTypeDef; /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_pins_define GPIO pins define * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ /** * @} */ /** @defgroup GPIO_mode_define GPIO mode define * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode * - y : External IT or Event trigger detection * - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ #define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ #define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ /** * @} */ /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Checks whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Generates a Software interrupt on selected EXTI line. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /** * @} */ /* Include GPIO HAL Extension module */ #include "stm32f1xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions * @{ */ /** @addtogroup GPIO_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ /** @addtogroup GPIO_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN(PIN) ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(MODE) \ (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING) \ || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \ || ((MODE) == GPIO_MODE_ANALOG)) #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Functions GPIO Private Functions * @{ */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.h * @author MCD Application Team * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_GPIO_EX_H #define __STM32F1xx_HAL_GPIO_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration * @brief This section propose definition to use the Cortex EVENTOUT signal. * @{ */ /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin * @{ */ #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ #define IS_AFIO_EVENTOUT_PIN(__PIN__) \ (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \ || ((__PIN__) == AFIO_EVENTOUT_PIN_15)) /** * @} */ /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port * @{ */ #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ #define IS_AFIO_EVENTOUT_PORT(__PORT__) \ (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E)) /** * @} */ /** * @} */ /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping * @brief This section propose definition to remap the alternate function to some other port/pins. * @{ */ /** * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) * @retval None */ #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) /** * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) * @retval None */ #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) /** * @brief Enable the remapping of I2C1 alternate function SCL and SDA. * @note ENABLE: Remap (SCL/PB8, SDA/PB9) * @retval None */ #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) /** * @brief Disable the remapping of I2C1 alternate function SCL and SDA. * @note DISABLE: No remap (SCL/PB6, SDA/PB7) * @retval None */ #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) /** * @brief Enable the remapping of USART1 alternate function TX and RX. * @note ENABLE: Remap (TX/PB6, RX/PB7) * @retval None */ #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) /** * @brief Disable the remapping of USART1 alternate function TX and RX. * @note DISABLE: No remap (TX/PA9, RX/PA10) * @retval None */ #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) /** * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) * @retval None */ #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) /** * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) * @retval None */ #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) * @retval None */ #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) * @retval None */ #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) * @retval None */ #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) * @retval None */ #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) * @retval None */ #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) /** * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) /** * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 * @retval None */ #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) * @retval None */ #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 * @retval None */ #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) #endif /** * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. * @retval None */ #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) /** * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). * @note DISABLE: No remapping of PD0 and PD1 * @retval None */ #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) #if defined(AFIO_MAPR_TIM5CH4_IREMAP) /** * @brief Enable the remapping of TIM5CH4. * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. * @note This function is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) /** * @brief Disable the remapping of TIM5CH4. * @note DISABLE: TIM5_CH4 is connected to PA3 * @note This function is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) #endif #if defined(AFIO_MAPR_ETH_REMAP) /** * @brief Enable the remapping of Ethernet MAC connections with the PHY. * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) /** * @brief Disable the remapping of Ethernet MAC connections with the PHY. * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) #endif #if defined(AFIO_MAPR_CAN2_REMAP) /** * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) /** * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) #endif #if defined(AFIO_MAPR_MII_RMII_SEL) /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) #endif /** * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) /** * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) /** * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 * @retval None */ #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) #endif #if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 * @retval None */ #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) #endif /** * @brief Enable the Serial wire JTAG configuration * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State * @retval None */ #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) /** * @brief Enable the Serial wire JTAG configuration * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST * @retval None */ #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) /** * @brief Enable the Serial wire JTAG configuration * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled * @retval None */ #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) /** * @brief Disable the Serial wire JTAG configuration * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled * @retval None */ #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) #if defined(AFIO_MAPR_SPI3_REMAP) /** * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) /** * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) #endif #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) /** * @brief Control of TIM2_ITR1 internal mapping. * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) /** * @brief Control of TIM2_ITR1 internal mapping. * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) #endif #if defined(AFIO_MAPR_PTP_PPS_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note ENABLE: PTP_PPS is output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). * @note DISABLE: PTP_PPS not output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) #endif #if defined(AFIO_MAPR2_TIM9_REMAP) /** * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). * @retval None */ #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) /** * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). * @retval None */ #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) #endif #if defined(AFIO_MAPR2_TIM10_REMAP) /** * @brief Enable the remapping of TIM10_CH1. * @note ENABLE: Remap (TIM10_CH1 on PF6). * @retval None */ #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) /** * @brief Disable the remapping of TIM10_CH1. * @note DISABLE: No remap (TIM10_CH1 on PB8). * @retval None */ #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) #endif #if defined(AFIO_MAPR2_TIM11_REMAP) /** * @brief Enable the remapping of TIM11_CH1. * @note ENABLE: Remap (TIM11_CH1 on PF7). * @retval None */ #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) /** * @brief Disable the remapping of TIM11_CH1. * @note DISABLE: No remap (TIM11_CH1 on PB9). * @retval None */ #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) #endif #if defined(AFIO_MAPR2_TIM13_REMAP) /** * @brief Enable the remapping of TIM13_CH1. * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). * @retval None */ #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) /** * @brief Disable the remapping of TIM13_CH1. * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). * @retval None */ #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) #endif #if defined(AFIO_MAPR2_TIM14_REMAP) /** * @brief Enable the remapping of TIM14_CH1. * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). * @retval None */ #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) /** * @brief Disable the remapping of TIM14_CH1. * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). * @retval None */ #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) #endif #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) /** * @brief Controls the use of the optional FSMC_NADV signal. * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. * @retval None */ #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) /** * @brief Controls the use of the optional FSMC_NADV signal. * @note CONNECTED: The NADV signal is connected to the output (default). * @retval None */ #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) #endif #if defined(AFIO_MAPR2_TIM15_REMAP) /** * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). * @retval None */ #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) /** * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). * @retval None */ #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) #endif #if defined(AFIO_MAPR2_TIM16_REMAP) /** * @brief Enable the remapping of TIM16_CH1. * @note ENABLE: Remap (TIM16_CH1 on PA6). * @retval None */ #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) /** * @brief Disable the remapping of TIM16_CH1. * @note DISABLE: No remap (TIM16_CH1 on PB8). * @retval None */ #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) #endif #if defined(AFIO_MAPR2_TIM17_REMAP) /** * @brief Enable the remapping of TIM17_CH1. * @note ENABLE: Remap (TIM17_CH1 on PA7). * @retval None */ #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) /** * @brief Disable the remapping of TIM17_CH1. * @note DISABLE: No remap (TIM17_CH1 on PB9). * @retval None */ #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) #endif #if defined(AFIO_MAPR2_CEC_REMAP) /** * @brief Enable the remapping of CEC. * @note ENABLE: Remap (CEC on PB10). * @retval None */ #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) /** * @brief Disable the remapping of CEC. * @note DISABLE: No remap (CEC on PB8). * @retval None */ #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) #endif #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) * @retval None */ #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). * @retval None */ #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) #endif #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) * @retval None */ #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) * @retval None */ #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) #endif #if defined(AFIO_MAPR2_TIM12_REMAP) /** * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) /** * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) #endif #if defined(AFIO_MAPR2_MISC_REMAP) /** * @brief Miscellaneous features remapping. * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is * selected as DAC Trigger 3, TIM15 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) /** * @brief Miscellaneous features remapping. * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) #endif /** * @} */ /** * @} */ /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros * @{ */ #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U) #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U) #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #define GPIO_GET_INDEX(__GPIOx__) \ (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U) #endif #define AFIO_REMAP_ENABLE(REMAP_PIN) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0U) #define AFIO_REMAP_DISABLE(REMAP_PIN) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg &= ~REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0U) #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg &= ~REMAP_PIN_MASK; \ tmpreg |= AFIO_MAPR_SWJ_CFG; \ tmpreg |= REMAP_PIN; \ AFIO->MAPR = tmpreg; \ } while (0U) #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \ do { \ uint32_t tmpreg = AFIO->MAPR; \ tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ tmpreg |= DBGAFR_SWJCFG; \ AFIO->MAPR = tmpreg; \ } while (0U) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIOEx_Exported_Functions * @{ */ /** @addtogroup GPIOEx_Exported_Functions_Group1 * @{ */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); void HAL_GPIOEx_EnableEventout(void); void HAL_GPIOEx_DisableEventout(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_GPIO_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h ================================================ #ifndef __STM32F1xx_HAL_I2C_H #define __STM32F1xx_HAL_I2C_H #endif /* __STM32F1xx_HAL_I2C_H */ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_iwdg.h * @author MCD Application Team * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_IWDG_H #define __STM32F1xx_HAL_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup IWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup IWDG_Exported_Types IWDG Exported Types * @{ */ /** * @brief IWDG Init structure definition */ typedef struct { uint32_t Prescaler; /*!< Select the prescaler of the IWDG. This parameter can be a value of @ref IWDG_Prescaler */ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ } IWDG_InitTypeDef; /** * @brief IWDG Handle Structure definition */ typedef struct { IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */ } IWDG_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Constants IWDG Exported Constants * @{ */ /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ #define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ #define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IWDG_Exported_Macros IWDG Exported Macros * @{ */ /** * @brief Enable the IWDG peripheral. * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** * @brief Reload IWDG counter with value defined in the reload register * (write access to IWDG_PR & IWDG_RLR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions * @{ */ /* Initialization/Start functions ********************************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions * @{ */ /* I/O operation functions ****************************************************/ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup IWDG_Private_Constants IWDG Private Constants * @{ */ /** * @brief IWDG Key Register BitMask */ #define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ #define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ #define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ #define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Macros IWDG Private Macros * @{ */ /** * @brief Enable write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** * @brief Disable write access to IWDG_PR and IWDG_RLR registers. * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Check IWDG prescaler value. * @param __PRESCALER__ IWDG prescaler value * @retval None */ #define IS_IWDG_PRESCALER(__PRESCALER__) \ (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \ || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256)) /** * @brief Check IWDG reload value. * @param __RELOAD__ IWDG reload value * @retval None */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_pwr.h * @author MCD Application Team * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_PWR_H #define __STM32F1xx_HAL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ */ /** * @brief PWR PVD configuration structure definition */ typedef struct { uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode */ } PWR_PVDTypeDef; /** * @} */ /* Internal constants --------------------------------------------------------*/ /** @addtogroup PWR_Private_Constants * @{ */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ */ #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 /** * @} */ /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins * @{ */ #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP /** * @} */ /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ #define PWR_MAINREGULATOR_ON 0x00000000U #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /** * @} */ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /** * @} */ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /** * @} */ /** @defgroup PWR_Flag PWR Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Macros PWR Exported Macros * @{ */ /** @brief Check PWR flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm * An additional wakeup event is detected if the WKUP pin is enabled * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) /** * @brief Enable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** * @brief Enable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) /** * @brief Disable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Rising Trigger. * This parameter can be: * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising & falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); /** * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * This parameter can be: * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /** * @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI PVD Line Status. */ #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) /** * @brief Clear the PVD EXTI flag. * @retval None. */ #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None. */ #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup PWR_Private_Macros PWR Private Macros * @{ */ #define IS_PWR_PVD_LEVEL(LEVEL) \ (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \ || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) #define IS_PWR_PVD_MODE(MODE) \ (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \ || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); /** * @} */ /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); /* #define HAL_PWR_ConfigPVD 12*/ void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); /* Low Power modes configuration functions ************************************/ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVDCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_PWR_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc.h * @author MCD Application Team * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_H #define __STM32F1xx_HAL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ /** * @brief RCC PLL configuration structure definition */ typedef struct { uint32_t PLLState; /*!< PLLState: The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ } RCC_PLLInitTypeDef; /** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ } RCC_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ /** * @} */ /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE 0x00000000U #define RCC_OSCILLATORTYPE_HSE 0x00000001U #define RCC_OSCILLATORTYPE_HSI 0x00000002U #define RCC_OSCILLATORTYPE_LSE 0x00000004U #define RCC_OSCILLATORTYPE_LSI 0x00000008U /** * @} */ /** @defgroup RCC_HSE_Config HSE Config * @{ */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** * @} */ /** @defgroup RCC_LSE_Config LSE Config * @{ */ #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ /** * @} */ /** @defgroup RCC_HSI_Config HSI Config * @{ */ #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ /** * @} */ /** @defgroup RCC_LSI_Config LSI Config * @{ */ #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ /** @defgroup RCC_PLL_Config PLL Config * @{ */ #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ /** @defgroup RCC_System_Clock_Source System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ /** * @} */ /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ /** * @} */ /** @defgroup RCC_MCO_Index MCO Index * @{ */ #define RCC_MCO1 0x00000000U #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler * @{ */ #define RCC_MCODIV_1 0x00000000U /** * @} */ /** @defgroup RCC_Interrupt Interrupts * @{ */ #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register * - X XX : Register index * - 001: CR register * - 010: BDCR register * - 011: CSR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SRAM_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_FLITF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CRC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) /** * @} */ /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_WWDG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_I2C1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_BKP_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_PWR_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} */ /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_AFIO_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOA_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) /** * @} */ /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) /** * @} */ /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** * @} */ /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) /** * @} */ /** @defgroup RCC_HSI_Configuration HSI Configuration * @{ */ /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = DISABLE) /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) /** * @} */ /** @defgroup RCC_LSI_Configuration LSI Configuration * @{ */ /** @brief Macro to enable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = ENABLE) /** @brief Macro to disable the Internal Low Speed oscillator (LSI). * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. */ #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = DISABLE) /** * @} */ /** @defgroup RCC_HSE_Configuration HSE Configuration * @{ */ /** * @brief Macro to configure the External High Speed oscillator (HSE). * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON turn ON the HSE oscillator * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do { \ if ((__STATE__) == RCC_HSE_ON) { \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } else if ((__STATE__) == RCC_HSE_OFF) { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } else if ((__STATE__) == RCC_HSE_BYPASS) { \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } else { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ } while (0U) /** * @} */ /** @defgroup RCC_LSE_Configuration LSE Configuration * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ if ((__STATE__) == RCC_LSE_ON) { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } else if ((__STATE__) == RCC_LSE_OFF) { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } else if ((__STATE__) == RCC_LSE_BYPASS) { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } else { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while (0U) /** * @} */ /** @defgroup RCC_PLL_Configuration PLL Configuration * @{ */ /** @brief Macro to enable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = ENABLE) /** @brief Macro to disable the main PLL. * @note The main PLL can not be disabled if it is used as system clock source */ #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = DISABLE) /** @brief Macro to configure the main PLL clock source and multiplication factors. * @note This function must be used only when the main PLL is disabled. * * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 @if STM32F105xC * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 @elseif STM32F107xC * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 @else * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 @endif * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__))) /** @brief Get oscillator clock selected as PLL input clock * @retval The clock source used for PLL entry. The returned value can be one * of the following: * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock */ #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) /** * @} */ /** @defgroup RCC_Get_Clock_source Get Clock source * @{ */ /** * @brief Macro to configure the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one * of the following: * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock */ #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) /** * @} */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config * @{ */ #if defined(RCC_CFGR_MCO_3) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source */ #else /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source */ #endif #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) /** * @} */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macro to enable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = ENABLE) /** @brief Macro to disable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = DISABLE) /** @brief Macro to force the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_BDCR register. */ #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = ENABLE) /** @brief Macros to release the Backup domain reset. */ #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = DISABLE) /** * @} */ /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** @brief Enable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) /** @brief Disable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) /** @brief Clear the RCC's interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif * @arg @ref RCC_IT_CSS Clock Security System interrupt */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. @if STM32F105xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @elsif STM32F107xx * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. @endif * @arg @ref RCC_IT_CSS Clock Security System interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) /** @brief Check RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. @if STM32F105xx * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. @elsif STM32F107xx * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. @endif * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. * @arg @ref RCC_FLAG_PINRST Pin reset. * @arg @ref RCC_FLAG_PORRST POR/PDR reset. * @arg @ref RCC_FLAG_SFTRST Software reset. * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. * @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK))) /** * @} */ /** * @} */ /* Include RCC HAL Extension module */ #include "stm32f1xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions * @{ */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} */ /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); void HAL_RCC_DisableCSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** * @} */ /** * @} */ /** @addtogroup RCC_Private_Constants * @{ */ /** @defgroup RCC_Timeout RCC Timeout * @{ */ /* Disable Backup domain write protection state change timeout */ #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ /* LSE state change timeout */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ /** * @} */ /** @defgroup RCC_Register_Offset Register offsets * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) #define RCC_CR_OFFSET 0x00U #define RCC_CFGR_OFFSET 0x04U #define RCC_CIR_OFFSET 0x08U #define RCC_BDCR_OFFSET 0x20U #define RCC_CSR_OFFSET 0x24U /** * @} */ /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion * @brief RCC registers bit address in the alias region * @{ */ #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) /* Alias word address of HSEON bit */ #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) /* Alias word address of CSSON bit */ #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) /* Alias word address of PLLON bit */ #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) /* Alias word address of RMVF bit */ #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) /* --- BDCR Registers ---*/ /* Alias word address of LSEON bit */ #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) /* Alias word address of LSEON bit */ #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) /* Alias word address of RTCEN bit */ #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) /* Alias word address of BDRST bit */ #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) /** * @} */ /* CR register byte 2 (Bits[23:16]) base address */ #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) /* CIR register byte 1 (Bits[15:8]) base address */ #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) /* CIR register byte 2 (Bits[23:16]) base address */ #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) /* Defines used for Flags */ #define CR_REG_INDEX ((uint8_t)1) #define BDCR_REG_INDEX ((uint8_t)2) #define CSR_REG_INDEX ((uint8_t)3) #define RCC_FLAG_MASK ((uint8_t)0x1F) /** * @} */ /** @addtogroup RCC_Private_Macros * @{ */ /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy * @{ */ #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET /** * @} */ #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \ || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON)) #define IS_RCC_CLOCKTYPE(CLK) \ ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \ || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) \ (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \ || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.h * @author MCD Application Team * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_RCC_EX_H #define __STM32F1xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup RCCEx * @{ */ /** @addtogroup RCCEx_Private_Constants * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) /* Alias word address of PLLI2SON bit */ #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) /* Alias word address of PLL2ON bit */ #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ #endif /* STM32F105xC || STM32F107xC */ #define CR_REG_INDEX ((uint8_t)1) /** * @} */ /** @addtogroup RCCEx_Private_Macros * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) #define IS_RCC_HSE_PREDIV(__DIV__) \ (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || ((__DIV__) == RCC_HSE_PREDIV_DIV5) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || ((__DIV__) == RCC_HSE_PREDIV_DIV15) \ || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) #else #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_PLL_MUL(__MUL__) \ (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) \ || ((__MUL__) == RCC_PLL_MUL6_5)) #define IS_RCC_MCO1SOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) #else #define IS_RCC_PLL_MUL(__MUL__) \ (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) \ || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) \ || ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || ((__MUL__) == RCC_PLL_MUL16)) #define IS_RCC_MCO1SOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) #endif /* STM32F105xC || STM32F107xC*/ #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) #if defined(STM32F105xC) || defined(STM32F107xC) #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) #define IS_RCC_PLLI2S_MUL(__MUL__) \ (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || ((__MUL__) == RCC_PLLI2S_MUL12) \ || ((__MUL__) == RCC_PLLI2S_MUL13) || ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || ((__MUL__) == RCC_PLLI2S_MUL20)) #define IS_RCC_HSE_PREDIV2(__DIV__) \ (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || ((__DIV__) == RCC_HSE_PREDIV2_DIV5) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) \ || ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || ((__PLL__) == RCC_PLL2_ON)) #define IS_RCC_PLL2_MUL(__MUL__) \ (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) \ || ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || ((__MUL__) == RCC_PLL2_MUL20)) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \ || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #elif defined(STM32F103xE) || defined(STM32F103xG) #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \ || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #else #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) /** * @brief RCC PLL2 configuration structure definition */ typedef struct { uint32_t PLL2State; /*!< The new state of the PLL2. This parameter can be a value of @ref RCCEx_PLL2_Config */ uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. This parameter can be a value of @ref RCCEx_Prediv2_Factor */ #endif /* STM32F105xC || STM32F107xC */ } RCC_PLL2InitTypeDef; #endif /* STM32F105xC || STM32F107xC */ /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t Prediv1Source; /*!< The Prediv1 source value. This parameter can be a value of @ref RCCEx_Prediv1_Source */ #endif /* STM32F105xC || STM32F107xC */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) This parameter can be a value of @ref RCCEx_Prediv1_Factor */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ #if defined(STM32F105xC) || defined(STM32F107xC) RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ #endif /* STM32F105xC || STM32F107xC */ } RCC_OscInitTypeDef; #if defined(STM32F105xC) || defined(STM32F107xC) /** * @brief RCC PLLI2S configuration structure definition */ typedef struct { uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. This parameter can be a value of @ref RCCEx_Prediv2_Factor */ #endif /* STM32F105xC || STM32F107xC */ } RCC_PLLI2SInitTypeDef; #endif /* STM32F105xC || STM32F107xC */ /** * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< specifies the RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t AdcClockSelection; /*!< ADC clock source This parameter can be a value of @ref RCCEx_ADC_Prescaler */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) uint32_t I2s2ClockSelection; /*!< I2S2 clock source This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ uint32_t I2s3ClockSelection; /*!< I2S3 clock source This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ #if defined(STM32F105xC) || defined(STM32F107xC) RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ #endif /* STM32F105xC || STM32F107xC */ #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) uint32_t UsbClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Prescaler */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ } RCC_PeriphCLKInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants * @{ */ /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ #define RCC_PERIPHCLK_RTC 0x00000001U #define RCC_PERIPHCLK_ADC 0x00000002U #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PERIPHCLK_I2S2 0x00000004U #define RCC_PERIPHCLK_I2S3 0x00000008U #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PERIPHCLK_USB 0x00000010U #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler * @{ */ #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 /** * @} */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source * @{ */ #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source * @{ */ #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC #endif /* STM32F105xC || STM32F107xC */ /** * @} */ #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) /** @defgroup RCCEx_USB_Prescaler USB Prescaler * @{ */ #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U /** * @} */ #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_USB_Prescaler USB Prescaler * @{ */ #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U /** * @} */ /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor * @{ */ #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Prediv1_Source Prediv1 Source * @{ */ #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor * @{ */ #define RCC_HSE_PREDIV_DIV1 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 #else #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor * @{ */ #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ /** * @} */ /** @defgroup RCCEx_PLL2_Config PLL Config * @{ */ #define RCC_PLL2_NONE 0x00000000U #define RCC_PLL2_OFF 0x00000001U #define RCC_PLL2_ON 0x00000002U /** * @} */ /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor * @{ */ #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) #else #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 #endif /* STM32F105xC || STM32F107xC */ #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 #else #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) #if defined(STM32F105xC) || defined(STM32F107xC) #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) #endif /* STM32F105xC || STM32F107xC*/ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Interrupt RCCEx Interrupt * @{ */ #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) /** * @} */ /** @defgroup RCCEx_Flag RCCEx Flag * Elements values convention: 0XXYYYYYb * - YYYYY : Flag position in the register * - XX : Register index * - 01: CR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /** * @} */ #endif /* STM32F105xC || STM32F107xC*/ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ */ /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE) #define __HAL_RCC_DMA2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) #define __HAL_RCC_FSMC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_SDIO_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) #endif /* STM32F105xC || STM32F107xC*/ #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMACTX_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMACRX_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) /** * @brief Enable ETHERNET clock. */ #define __HAL_RCC_ETH_CLK_ENABLE() \ do { \ __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ } while (0U) /** * @brief Disable ETHERNET clock. */ #define __HAL_RCC_ETH_CLK_DISABLE() \ do { \ __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while (0U) #endif /* STM32F107xC*/ /** * @} */ /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) #endif /* STM32F105xC || STM32F107xC*/ #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) #endif /* STM32F107xC*/ /** * @} */ /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USART3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_I2C2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM6_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM7_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM7_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_DAC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CEC_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #endif /* STM32F100xB || STM32F100xE */ #ifdef STM32F100xE #define __HAL_RCC_TIM5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM12_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM13_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM14_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_SPI3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART4_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_UART5_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM12_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM13_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM14_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #endif /* STM32F100xB || STM32F100xE */ #ifdef STM32F100xE #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM16_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM17_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_ADC3_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM10_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM11_CLK_ENABLE() \ do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); \ UNUSED(tmpreg); \ } while (0U) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release * @brief Force or release AHB peripheral reset. * @{ */ #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) #endif /* STM32F107xC */ #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) #if defined(STM32F107xC) #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) #endif /* STM32F107xC */ /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \ || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #endif /* STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #endif /* STM32F101xG || STM32F103xG */ /** * @} */ /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ #if defined(STM32F100xB) || defined(STM32F100xE) #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) #endif /* STM32F100xB || STM32F100xE */ #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \ || defined(STM32F105xC) || defined(STM32F107xC) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ #if defined(STM32F103xE) || defined(STM32F103xG) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F100xE) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) #endif /* STM32F100xE */ #if defined(STM32F101xG) || defined(STM32F103xG) #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) #endif /* STM32F101xG || STM32F103xG*/ /** * @} */ /** @defgroup RCCEx_HSE_Configuration HSE Configuration * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. */ #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) #else /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. */ #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) /** * @brief Macro to get prediv1 factor for PLL. */ #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) #else /** * @brief Macro to get prediv1 factor for PLL. */ #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration * @{ */ /** @brief Macros to enable the main PLLI2S. * @note After enabling the main PLLI2S, the application software should wait on * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can * be used as system clock source. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = ENABLE) /** @brief Macros to disable the main PLLI2S. * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = DISABLE) /** @brief macros to configure the main PLLI2S multiplication factor. * @note This function must be used only when the main PLLI2S is disabled. * * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL, (__PLLI2SMUL__)) /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration * @brief Macros to configure clock source of different peripherals. * @{ */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) /** @brief Macro to configure the USB clock. * @param __USBCLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) /** @brief Macro to get the USB clock (USBCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @brief Macro to configure the USB OTSclock. * @param __USBCLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) /** @brief Macro to get the USB clock (USBCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) #endif /* STM32F105xC || STM32F107xC */ /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). * @param __ADCCLKSOURCE__ specifies the ADC clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock */ #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). * @retval The clock source can be one of the following values: * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock */ #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_HSE_Configuration * @{ */ /** * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and * then change the PREDIV2 factor. * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. */ #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) /** * @brief Macro to get prediv2 factor for PLL2 & PLL3. */ #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) /** * @} */ /** @addtogroup RCCEx_PLLI2S_Configuration * @{ */ /** @brief Macros to enable the main PLL2. * @note After enabling the main PLL2, the application software should wait on * PLL2RDY flag to be set indicating that PLL2 clock is stable and can * be used as system clock source. * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = ENABLE) /** @brief Macros to disable the main PLL2. * @note The main PLL2 can not be disabled if it is used indirectly as system clock source * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = DISABLE) /** @brief macros to configure the main PLL2 multiplication factor. * @note This function must be used only when the main PLL2 is disabled. * * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock * This parameter can be one of the following values: * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 * */ #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL, (__PLL2MUL__)) /** * @} */ /** @defgroup RCCEx_I2S_Configuration I2S Configuration * @brief Macros to configure clock source of I2S peripherals. * @{ */ /** @brief Macro to configure the I2S2 clock. * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) /** @brief Macro to get the I2S2 clock (I2S2CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) /** @brief Macro to configure the I2S3 clock. * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) /** @brief Macro to get the I2S3 clock (I2S3CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry */ #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F1xx_HAL_RCC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim.h * @author MCD Application Team * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_TIM_H #define STM32F1xx_HAL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" #ifndef USE_HAL_TIM_REGISTER_CALLBACKS #define USE_HAL_TIM_REGISTER_CALLBACKS 0 #endif /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ /** * @brief TIM Time base Configuration Structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** * @brief TIM Output Compare Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; /** * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** * @brief Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode. */ } TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable * filter and polarity. */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; /** * @brief TIM Channel States definition */ typedef enum { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ } HAL_TIM_ChannelStateTypeDef; /** * @brief DMA Burst States definition */ typedef enum { HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ } HAL_TIM_DMABurstStateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) typedef struct __TIM_HandleTypeDef #else typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { TIM_TypeDef * Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef * hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (*Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (*Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ void (*IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ void (*IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ void (*OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ void (*OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ void (*PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ void (*PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ void (*OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ void (*OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ void (*Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ void (*Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ void (*HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ void (*HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ void (*PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (*PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ void (*TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (*TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ void (*IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (*IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ void (*OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ void (*PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (*PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ void (*ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ void (*CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (*CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (*BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief HAL TIM Callback ID enumeration definition */ typedef enum { HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ /** * @} */ /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ #define TIM_DMABASE_CR1 0x00000000U #define TIM_DMABASE_CR2 0x00000001U #define TIM_DMABASE_SMCR 0x00000002U #define TIM_DMABASE_DIER 0x00000003U #define TIM_DMABASE_SR 0x00000004U #define TIM_DMABASE_EGR 0x00000005U #define TIM_DMABASE_CCMR1 0x00000006U #define TIM_DMABASE_CCMR2 0x00000007U #define TIM_DMABASE_CCER 0x00000008U #define TIM_DMABASE_CNT 0x00000009U #define TIM_DMABASE_PSC 0x0000000AU #define TIM_DMABASE_ARR 0x0000000BU #define TIM_DMABASE_RCR 0x0000000CU #define TIM_DMABASE_CCR1 0x0000000DU #define TIM_DMABASE_CCR2 0x0000000EU #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U #define TIM_DMABASE_DCR 0x00000012U #define TIM_DMABASE_DMAR 0x00000013U /** * @} */ /** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ /** * @} */ /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} */ /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ /** * @} */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity * @{ */ #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ /** * @} */ /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI \ TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be \ connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI \ TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be \ connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ /** * @} */ /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ /** * @} */ /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ /** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_ENABLE \ TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event \ (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ /** * @} */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ /** * @} */ /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ /** * @} */ /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */ #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ */ /** @brief Reset TIM handle state. * @param __HANDLE__ TIM handle. * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \ do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ (__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while (0) #else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) \ do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while (0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while (0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while (0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** * @brief Check whether the specified TIM interrupt source is enabled or not. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do { \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while (0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do { \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while (0) /** * @brief Get the TIM Clock Division value on runtime. * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do { \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while (0) /** * @brief Get the TIM Input Capture prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval The input capture prescaler can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) \ : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \ : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \ : ((__HANDLE__)->Instance->CCR4)) /** * @brief Set the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \ : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) /** * @brief Reset the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) /** * @brief Enable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \ : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) /** * @brief Disable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ do { \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ } while (0) /** * @} */ /* End of exported macros ----------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) #define IS_TIM_DMA_BASE(__BASE__) \ (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR) \ || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) \ || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2) \ || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) \ (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \ || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE)) #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW)) #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || ((__STATE__) == TIM_OCIDLESTATE_RESET)) #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || ((__STATE__) == TIM_OCNIDLESTATE_RESET)) #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC)) #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8)) #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE)) #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12)) #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_ALL)) #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \ || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \ || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) \ (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \ || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \ || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE)) #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE)) #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3)) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE)) #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) \ (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) \ || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF)) #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) #define IS_TIM_SLAVE_MODE(__MODE__) \ (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) \ || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2)) #define IS_TIM_OC_MODE(__MODE__) \ (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \ || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) \ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) \ || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \ (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE)) #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) \ (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING) \ || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE)) #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) \ (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) #define IS_TIM_DMA_LENGTH(__LENGTH__) \ (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \ || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) \ : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \ : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \ : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) \ : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \ : (__HANDLE__)->ChannelState[3]) #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \ : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ do { \ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ } while (0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \ : (__HANDLE__)->ChannelNState[3]) #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \ : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \ : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ do { \ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ } while (0) /** * @} */ /* End of private macros -----------------------------------------------------*/ /* Include TIM HAL Extended module */ #include "stm32f1xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @{ */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @{ */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @{ */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @{ */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @{ */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @{ */ /* Timer Encoder functions ****************************************************/ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief Peripheral State functions * @{ */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim_ex.h * @author MCD Application Team * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F1xx_HAL_TIM_EX_H #define STM32F1xx_HAL_TIM_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal_def.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @addtogroup TIMEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ /** * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ */ /** * @} */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ /** * @} */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @{ */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @{ */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @{ */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Extended Control functions ************************************************/ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F1xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal.c * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup HAL HAL * @brief HAL module driver. * @{ */ #ifdef HAL_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ /** * @brief STM32F1xx HAL Driver version number V1.1.3 */ #define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC)) #define IDCODE_DEVID_MASK 0x00000FFFU /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface, the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL. (+) Configure The time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. (++) Time base configuration function (HAL_InitTick ()) is called automatically at the beginning of the program after reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). (++) Source of time base is configured to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** * @brief This function is used to initialize the HAL Library; it must be the first * instruction to be executed in the main program (before to call any other * HAL function), it performs the following: * Configure the Flash prefetch. * Configures the SysTick to generate an interrupt each 1 millisecond, * which is clocked by the HSI (at this stage, the clock is not yet * configured and thus the system is running from the internal HSI at 16 MHz). * Set NVIC Group Priority to 4. * Calls the HAL_MspInit() callback function defined in user file * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization * * @note SysTick is used as time base for the HAL_Delay() function, the application * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0) #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \ defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); /* Init the low level hardware */ HAL_MspInit(); /* Return function status */ return HAL_OK; } /** * @brief This function de-Initializes common part of the HAL and stops the systick. * of time base. * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ __HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB2_FORCE_RESET(); __HAL_RCC_APB2_RELEASE_RESET(); #if defined(STM32F105xC) || defined(STM32F107xC) __HAL_RCC_AHB_FORCE_RESET(); __HAL_RCC_AHB_RELEASE_RESET(); #endif /* De-Init the low level hardware */ HAL_MspDeInit(); /* Return function status */ return HAL_OK; } /** * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** * @brief DeInitializes the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** * @brief This function configures the source of the time base. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else { return HAL_ERROR; } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Provide a tick value in millisecond (+) Provide a blocking delay in millisecond (+) Suspend the time base source interrupt (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ */ /** * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; } /** * @brief Provides a tick value in millisecond. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; } /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { return uwTickPrio; } /** * @brief Set new tick Freq. * @retval Status */ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); } return status; } /** * @brief Return tick frequency. * @retval tick period in Hz */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { wait += (uint32_t)(uwTickFreq); } while ((HAL_GetTick() - tickstart) < wait) { } } /** * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { /* Enable SysTick Interrupt */ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Returns the HAL revision * @retval version 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; } /** * @brief Returns the device revision identifier. * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); } /** * @brief Returns the device identifier. * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** * @brief Enable the Debug Module during SLEEP mode * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * Note: On all STM32F1 devices: * If the system tick timer interrupt is enabled during the Stop mode * debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup * the system from Stop mode. * Workaround: To debug the Stop mode, disable the system tick timer * interrupt. * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode * Note: On devices STM32F10xx8 and STM32F10xxB, * STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xF/G and STM32F103xF/G * STM32F10xx4 and STM32F10xx6 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * debug mode (not accessible by the user software in normal mode). * Refer to errata sheet of these devices for more details. * @retval None */ void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Return the unique device identifier (UID based on 96 bits) * @param UID pointer to 3 words array. * @retval Device identifier */ void HAL_GetUID(uint32_t *UID) { UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE))); UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** * @brief Returns first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); } /** * @brief Returns second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** * @brief Returns third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** * @} */ /** * @} */ #endif /* HAL_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC * + Operation functions * ++ Start, stop, get result of conversions of regular * group, using 3 possible modes: polling, interruption or DMA. * + Control functions * ++ Channels configuration on regular group * ++ Channels configuration on injected group * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management * Other functions (extended functions) are available in file * "stm32f1xx_hal_adc_ex.c". * @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit resolution (+) Interrupt generation at the end of regular conversion, end of injected conversion, and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) ADC conversion of regular group and injected group. (+) External trigger (timer or EXTI) for both regular and injected groups. (+) DMA request generation for transfer of conversions data of regular group. (+) Multimode Dual mode (available on devices with 2 ADCs or more). (+) Configurable DMA data storage in Multimode Dual mode (available on devices with 2 DCs or more). (+) Configurable delay between conversions in Dual interleaved mode (available on devices with 2 DCs or more). (+) ADC calibration (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. Caution: On STM32F1, ADC clock frequency max is 14MHz (refer to device datasheet). Therefore, ADC clock prescaler must be configured in function of ADC clock source frequency to remain below this maximum frequency. (++) One clock setting is mandatory: ADC clock (core clock, also possibly conversion clock). (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; (+++) __ADC1_CLK_ENABLE(); (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, groups regular/injected, channels parameters *** ========================================================================== [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the injected group parameters (conversion trigger, sequencer, ..., of injected group) and the channels for injected group parameters (channel number, channel rank into sequencer, ..., into injected group) using function HAL_ADCEx_InjectedConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). (#) Optionally, for devices with several ADC instances: configure the multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() (++) For devices with several ADCs: ADC multimode conversion with transfer by DMA: (+++) Activate the ADC peripheral (slave) and start conversions using function HAL_ADC_Start() (+++) Activate the ADC peripheral (master) and start conversions using function HAL_ADCEx_MultiModeStart_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral (master) using function HAL_ADCEx_MultiModeStop_DMA() (+++) Stop conversion and disable the ADC peripheral (slave) using function HAL_ADC_Stop_IT() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback (+@) HAL_ADCEx_InjectedConvCpltCallback() *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_Init(). (++) Disable the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ /* Timeout values for ADC enable and disable settling time. */ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_ENABLE_TIMEOUT 2U #define ADC_DISABLE_TIMEOUT 2U /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ #define ADC_STAB_DELAY_US 1U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (clock source APB2). * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cr1 = 0U; uint32_t tmp_cr2 = 0U; uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ /* at RCC top level. */ /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_ADC_MspInit(hadc); } /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set ADC parameters */ /* Configuration of ADC: */ /* - data alignment */ /* - external trigger to start conversion */ /* - external trigger polarity (always set to 1, because needed for all */ /* triggers: external trigger of SW start) */ /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)); /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) { if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)); } else { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_SCAN | ADC_CR1_DISCEN | ADC_CR1_DISCNUM, tmp_cr1); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, ADC_CR2_ALIGN | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG | ADC_CR2_CONT, tmp_cr2); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); } MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, tmp_sqr1); /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE)) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * If needed, the example code can be copied and uncommented into * function HAL_ADC_MspDeInit(). * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); /* Reset register CR1 */ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH)); /* Reset register CR2 */ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | ADC_CR2_ADON)); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)); /* Reset register JOFR1 */ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); /* Reset register JOFR2 */ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); /* Reset register JOFR3 */ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); /* Reset register JOFR4 */ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); /* Reset register HTR */ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); /* Reset register LTR */ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ /* __HAL_RCC_ADC1_FORCE_RESET() */ /* __HAL_RCC_ADC1_RELEASE_RESET() */ /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Initializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitializes the ADC MSP. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 IO operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. * @note This function cannot be used in a particular setup: ADC configured * in DMA mode. * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. * @note On STM32F1 devices, limitation in case of sequencer enabled * (several ranks selected): polling cannot be done on each * conversion inside the sequence. In this case, polling is replaced by * wait for maximum conversion time. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* - If single conversion for regular group (Scan mode disabled or enabled */ /* with NbrOfConversion =1), flag EOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for regular group (scan mode enabled and */ /* NbrOfConversion >=2), flag EOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)) { /* Wait until End of Conversion flag is raised */ while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc)); while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles++; } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Poll for conversion event. * @param hadc: ADC handle * @param EventType: the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event. * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while (__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } /* Analog watchdog (level out of window) event */ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled: */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStart function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * ADC2 converted data can be transferred in dual ADC mode using DMA * of ADC1 (ADC master in multimode). * In case of using ADC1 with DMA on a device featuring 2 ADC * instances: ADC1 conversion register DR contains ADC1 conversion * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last * conversion result (ADC1 register DR bits 16 to 27). Therefore, to * have DMA transferring the conversion results of ADC1 only, DMA must * be configured to transfer size: half word. * @param hadc: ADC handle * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if (ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStop function. * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending * on devices) have DMA capability. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) { if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } } /* ========== Check End of Conversion flag for injected group ========== */ if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) { if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Determine whether any further conversion upcoming on group injected */ /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ HAL_ADCEx_InjectedConvCpltCallback(hadc); /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } } } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3, ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank), ADC_SQR3_RK(sConfig->Channel, sConfig->Rank)); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2, ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank), ADC_SQR2_RK(sConfig->Channel, sConfig->Rank)); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank), ADC_SQR1_RK(sConfig->Channel, sConfig->Rank)); } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel), ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel)); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel), ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel)); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Configures the analog watchdog. * @note Analog watchdog thresholds can be modified while ADC conversion * is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc: ADC handle * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Analog watchdog configuration */ /* Configure ADC Analog watchdog interrupt */ if (AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); } else { /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); } /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: regular and/or injected groups, */ /* one or all channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDCH, AnalogWDGConfig->WatchdogMode | AnalogWDGConfig->Channel); /* Set the high threshold */ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); /* Set the low threshold */ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief Peripheral State functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief return the ADC state * @param hadc: ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Return ADC state */ return hadc->State; } /** * @brief Return the ADC error code * @param hadc: ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { return hadc->ErrorCode; } /** * @} */ /** * @} */ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart = 0U; __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while (wait_loop_index != 0U) { wait_loop_index--; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ while (ADC_IS_ENABLE(hadc) == RESET) { if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief Stop ADC conversion and disable the selected ADC * @note Prerequisite condition to use this function: ADC conversions must be * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart = 0U; /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively disabled */ while (ADC_IS_ENABLE(hadc) != RESET) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of injected * group, using 2 possible modes: polling, interruption. * ++ Multimode feature (available on devices with 2 ADCs or more) * ++ Calibration (ADC automatic self-calibration) * + Control functions * ++ Channels configuration on injected group * Other functions (generic functions) are available in file * "stm32f1xx_hal_adc.c". * @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32f1xx_hal_adc.c". [..] @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extension HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ /* Delay for ADC calibration: */ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_CALIBRATION_TIMEOUT 10U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions * @brief Extended Extended Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of injected group. (+) Stop conversion of injected group. (+) Poll for conversion complete on injected group. (+) Get result of injected channel conversion. (+) Start conversion of injected group and enable interruptions. (+) Stop conversion of injected group and disable interruptions. (+) Start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @endverbatim * @{ */ /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * During calibration process, ADC is enabled. ADC is let enabled at * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES); while (wait_loop_index != 0U) { wait_loop_index--; } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); tickstart = HAL_GetTick(); /* Wait for calibration reset completion */ while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); tickstart = HAL_GetTick(); /* Wait for calibration completion */ while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enables ADC, starts conversion of injected group. * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable conversion of injected group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ /* Case of multimode enabled (for devices with several ADCs): if ADC is */ /* slave, ADC is enabled only (conversion is not started). If ADC is */ /* master, ADC is enabled and conversion is started. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for injected group conversion to be completed. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get timeout */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag JEOC is not set after each conversion, no timeout status can */ /* be set. */ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) { /* Wait until End of Conversion flag is raised */ while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc)); while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles++; } } /* Clear injected group conversion flag */ /* Note: On STM32F1 ADC, clear regular conversion flag raised */ /* simultaneously. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } /** * @brief Enables ADC, starts conversion of injected group with interruption. * - JEOC (end of conversion of injected group) * Each of these interruptions has its dedicated callback function. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode (for devices with several ADCs): */ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); /* Start conversion of injected group if software start has been selected */ /* and if automatic injected conversion is disabled. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @param hadc: ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note: On STM32F1 devices, ADC slave regular group must be configured * with conversion trigger ADC_SOFTWARE_START. * @note: ADC slave can be enabled preliminarily using single-mode * HAL_ADC_Start() function. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* On STM32F1 devices, ADC slave regular group must be configured with */ /* conversion trigger ADC_SOFTWARE_START. */ /* Note: External trigger of ADC slave must be enabled, it is already done */ /* into function "HAL_ADC_Init()". */ if (!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start conversion if all ADCs of multimode are effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state (ADC master) */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode of ADC master */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Start conversion of regular group if software start has been selected. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note Multimode is kept enabled after this function. To disable multimode * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC master peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Disable ADC slave peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); /* Check if ADC is effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Reset configuration of ADC DMA continuous request for dual mode */ CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Change ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc: ADC handle * @param InjectedRank: the converted ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch (InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Returns the last ADC Master&Slave regular conversions results data * in the selected multi mode. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @retval The converted data value. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { uint32_t tmpDR = 0U; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ /* only if ADC1 DMA mode is enabled. */ tmpDR = hadc->Instance->DR; if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) { tmpDR |= (ADC2->DR << 16U); } /* Return ADC converted value */ return tmpDR; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on injected group (+) Configure multimode @endverbatim * @{ */ /** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @param hadc: ADC handle * @param sConfigInjected: Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter "InjectedNbrOfConversion". */ // if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) // { // if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) // { // /* Clear the old SQx bits for all injected ranks */ // MODIFY_REG(hadc->Instance->JSQR , // ADC_JSQR_JL | // ADC_JSQR_JSQ4 | // ADC_JSQR_JSQ3 | // ADC_JSQR_JSQ2 | // ADC_JSQR_JSQ1 , // ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, // ADC_INJECTED_RANK_1, // 0x01U)); // } // /* If another injected rank than rank1 was intended to be set, and could */ // /* not due to ScanConvMode disabled, error is reported. */ // else // { // /* Update ADC state machine to error */ // SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); // // tmp_hal_status = HAL_ERROR; // } // } // else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion), ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion)); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion), 0x00000000U); } } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - external trigger to start conversion */ /* Parameters update not conditioned to ADC state: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Note: In case of ADC already enabled, caution to not launch an unwanted */ /* conversion while modifying register CR2 by writing 1 to bit ADON. */ if (ADC_IS_ENABLE(hadc) == RESET) { MODIFY_REG(hadc->Instance->CR2, ADC_CR2_JEXTSEL | ADC_CR2_ADON, ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv)); } /* Configuration of injected group */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* InjectedChannel sampling time configuration */ /* For channels 10 to 17 */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel)); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel)); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch (sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without reseting * the ADCs (both ADCs of the common group). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To change back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc: ADC handle * @param multimode: Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MODE(multimode->Mode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - ADC master and ADC slave DMA configuration */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* To optimize code, all multimode settings can be set when both ADCs of */ /* the common group are in state: disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))) { MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DUALMOD, multimode->Mode); } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M3 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). (#) please refer to programming manual for details in how to configure priority. -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest preemption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value 0x0F. (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32f1xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup CORTEX CORTEX * @brief CORTEX HAL module driver * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts Systick functionalities @endverbatim * @{ */ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } /** * @brief Sets the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) * @param PreemptPriority: The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup = 0x00U; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } /** * @brief Initiates a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { /* System Reset */ NVIC_SystemReset(); } /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** * @} */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ #if (__MPU_PRESENT == 1U) /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable the MPU and clear the control register*/ MPU->CTRL = 0U; } /** * @brief Enable the MPU. * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Ensure MPU setting take effects */ __DSB(); __ISB(); } /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; if ((MPU_Init->Enable) != RESET) { /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } else { MPU->RBAR = 0x00U; MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) */ uint32_t HAL_NVIC_GetPriorityGrouping(void) { /* Get the PRIGROUP[10:8] field value */ return NVIC_GetPriorityGrouping(); } /** * @brief Gets the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Get priority for Cortex-M system or device specific interrupts */ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); } /** * @brief Sets Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clears the pending bit of an external interrupt. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } /** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } /** * @brief Configures the SysTick clock source. * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; } } /** * @brief This function handles SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); } /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e. a member of DMA handle structure). *** DMA HAL driver macros list *** ============================================= [..] Below the list of most used macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in reference manual. @endverbatim * @{ */ /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0U; #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); /* Clean all callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete (+) Handle DMA interrupt request @endverbatim * @{ */ /** * @brief Start the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_BUSY; } return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Abort the DMA Transfer. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return status; } /** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; } /** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0U; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if (CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); } else { /* Half Transfer Complete flag */ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } /* Get tick */ tickstart = HAL_GetTick(); while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } if (CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Handles DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } /* Transfer Error Interrupt management **************************************/ else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } return; } /** * @brief Register callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback: pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @brief UnRegister callbacks * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID: User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; break; case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state (+) Get error code @endverbatim * @{ */ /** * @brief Return the DMA hande state. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { /* Return DMA handle state */ return hdma->State; } /** * @brief Return the DMA error code. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions * + Memory Control functions * + Peripheral State functions * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections (+) Prefetch on I-Code (+) Option Bytes programming ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH memory of all STM32F1xx devices. (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes (++) Set/Reset the write protection (++) Set the Read protection Level (++) Program the user Option Bytes (++) Launch the Option Bytes loader (++) Erase Option Bytes (++) Program the data Option Bytes (++) Get the Write protection. (++) Get the user option bytes. (#) Interrupts and flags management functions : this group includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the half cycle access (+) Enable/Disable the FLASH interrupts (+) Monitor the FLASH flags status @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ /** * @} */ /* Private macro ---------------------------- ---------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ */ /* Variables used for Erase pages under interruption*/ FLASH_ProcessTypeDef pFlash; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_SetErrorCode(void); extern void FLASH_PageErase(uint32_t PageAddress); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions * @brief Programming operation functions * @verbatim @endverbatim * @{ */ /** * @brief Program halfword, word or double word at a specified address * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_ERROR; uint8_t index = 0; uint8_t nbiterations = 0; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #if defined(FLASH_BANK2_END) } else { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if (status == HAL_OK) { if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; } for (index = 0U; index < nbiterations; index++) { FLASH_Program_HalfWord((Address + (2U * index)), (uint16_t)(Data >> (16U * index))); #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) } else { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) { break; } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Program halfword, word or double word at a specified address with interrupt enabled. * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: Specifies the address to be programmed. * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); #if defined(FLASH_BANK2_END) /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { return HAL_ERROR; } if (Address <= FLASH_BANK1_END) { /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); } else { /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); } #else /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ pFlash.Address = Address; pFlash.Data = Data; if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; /* Program halfword (16-bit) at a specified address. */ pFlash.DataRemaining = 1U; } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; /* Program word (32-bit : 2*16-bit) at a specified address. */ pFlash.DataRemaining = 2U; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; /* Program double word (64-bit : 4*16-bit) at a specified address. */ pFlash.DataRemaining = 4U; } /* Program halfword (16-bit) at a specified address. */ FLASH_Program_HalfWord(Address, (uint16_t)Data); return status; } /** * @brief This function handles FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0U; /* Check FLASH operation error flags */ #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { /* Return the faulty address */ addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFFU; /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); /* Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); #endif /* FLASH_BANK2_END */ /* Process can continue only if no error detected */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; /* Check if there are still pages to erase */ if (pFlash.DataRemaining != 0U) { addresstmp = pFlash.Address; /*Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(addresstmp); /*Increment sector number*/ addresstmp = pFlash.Address + FLASH_PAGE_SIZE; pFlash.Address = addresstmp; /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); FLASH_PageErase(addresstmp); } else { /* No more pages to Erase, user callback can be called. */ /* Reset Sector and stop Erase pages procedure */ pFlash.Address = addresstmp = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(addresstmp); } } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); #if defined(FLASH_BANK2_END) /* Stop Mass Erase procedure if no pending mass erase on other bank */ if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) { #endif /* FLASH_BANK2_END */ /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0U); /* Stop Mass Erase procedure*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ else { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ if (pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } else { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure */ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } } } #if defined(FLASH_BANK2_END) /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); /* Process can continue only if no error detected */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; /* Check if there are still pages to erase*/ if (pFlash.DataRemaining != 0U) { /* Indicate user which page address has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Address); /* Increment page address to next page */ pFlash.Address += FLASH_PAGE_SIZE; addresstmp = pFlash.Address; /* Operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); FLASH_PageErase(addresstmp); } else { /*No more pages to Erase*/ /*Reset Address and stop Erase pages procedure*/ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) { /* MassErase ended. Return the selected bank*/ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0U); pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } else { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ if (pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } else { /*Program ended. Return the selected address*/ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure*/ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } } } #endif if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { #if defined(FLASH_BANK2_END) /* Operation is completed, disable the PG, PER and MER Bits for both bank */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER)); /* Disable End of FLASH Operation and Error source interrupts for both banks */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #else /* Operation is completed, disable the PG, PER and MER Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); /* Disable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #endif /* FLASH_BANK2_END */ /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ } /** * @brief FLASH operation error interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief management functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim * @{ */ /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* Verify Flash is unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { status = HAL_ERROR; } } #if defined(FLASH_BANK2_END) if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) { /* Authorize the FLASH BANK2 Registers access */ WRITE_REG(FLASH->KEYR2, FLASH_KEY1); WRITE_REG(FLASH->KEYR2, FLASH_KEY2); /* Verify Flash BANK2 is unlocked */ if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) { status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; } /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; } /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); } else { return HAL_ERROR; } return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); return HAL_OK; } /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. * @retval None */ void HAL_FLASH_OB_Launch(void) { /* Initiates a system reset request to launch the option byte loading */ HAL_NVIC_SystemReset(); } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions * @brief Peripheral errors functions * @verbatim =============================================================================== ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permit to get in run-time errors of the FLASH peripheral. @endverbatim * @{ */ /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode The returned value can be: * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Program a half-word (16-bit) at a specified address. * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); #if defined(FLASH_BANK2_END) } else { /* Proceed to program the new data */ SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t *)Address = Data; } /** * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } /* There is no error flag set */ return HAL_OK; } #if defined(FLASH_BANK2_END) /** * @brief Wait for a FLASH BANK2 operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) { /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset. Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) { if (Timeout != HAL_MAX_DELAY) { if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } /* If there is an error flag set */ return HAL_OK; } #endif /* FLASH_BANK2_END */ /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { uint32_t flags = 0U; #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; #endif /* FLASH_BANK2_END */ } if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions * + Extended Peripheral Control functions * @verbatim ============================================================================== ##### Flash peripheral extended features ##### ============================================================================== ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32F1xxx devices. It includes (++) Set/Reset the write protection (++) Program the user Option Bytes (++) Get the Read protection Level @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Variables * @{ */ /* Variables used for Erase pages under interruption*/ extern FLASH_ProcessTypeDef pFlash; /** * @} */ /** * @} */ /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants * @{ */ #define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos #define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos #define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ /* Erase operations */ static void FLASH_MassErase(uint32_t Banks); void FLASH_PageErase(uint32_t PageAddress); /* Option bytes control */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); static uint32_t FLASH_OB_GetWRP(void); static uint32_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetUser(void); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * @verbatim ============================================================================== ##### FLASH Erasing Programming functions ##### ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: (+) @ref HAL_FLASHEx_Erase: return only when erase has been done (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ /** * @brief Perform a mass erase or erase the specified FLASH memory pages * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @param[out] PageError pointer to variable that * contains the configuration information on faulty page in case of error * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; uint32_t address = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { #if defined(FLASH_BANK2_END) if (pEraseInit->Banks == FLASH_BANK_BOTH) { /* Mass Erase requested for Bank1 and Bank2 */ /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_BOTH); /* Wait for last operation to be completed */ if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) { status = HAL_OK; } /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } else if (pEraseInit->Banks == FLASH_BANK_2) { /* Mass Erase requested for Bank2 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_2); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); } } else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); } } } else { /* Page Erase is requested */ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); #if defined(FLASH_BANK2_END) /* Page Erase requested on address located on bank2 */ if (pEraseInit->PageAddress > FLASH_BANK1_END) { /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; /* Erase by page by page to be done*/ for (address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages) * FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; break; } } } } else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; /* Erase page by page to be done*/ for (address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; break; } } } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); #if defined(FLASH_BANK2_END) /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); #endif if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; FLASH_MassErase(pEraseInit->Banks); } else { /* Erase by page to be done*/ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; pFlash.DataRemaining = pEraseInit->NbPages; pFlash.Address = pEraseInit->PageAddress; /*Erase 1st page and wait for IT*/ FLASH_PageErase(pEraseInit->PageAddress); } return status; } /** * @} */ /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim ============================================================================== ##### Option Bytes Programming functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH option bytes operations. @endverbatim * @{ */ /** * @brief Erases the FLASH option bytes. * @note This functions erases all option bytes except the Read protection (RDP). * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * @retval HAL status */ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) { uint8_t rdptmp = OB_RDP_LEVEL_0; HAL_StatusTypeDef status = HAL_ERROR; /* Get the actual read protection Option Byte value */ rdptmp = FLASH_OB_GetRDP(); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if (status == HAL_OK) { /* Restore the last read protection Option Byte value */ status = FLASH_OB_RDP_LevelConfig(rdptmp); } } /* Return the erase status */ return status; } /** * @brief Program option bytes * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Write protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /* Enable of Write protection on the selected page */ status = FLASH_OB_EnableWRP(pOBInit->WRPPage); } else { /* Disable of Write protection on the selected page */ status = FLASH_OB_DisableWRP(pOBInit->WRPPage); } if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Read protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) { status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* USER configuration */ if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { status = FLASH_OB_UserConfig(pOBInit->USERConfig); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* DATA configuration*/ if ((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) { status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option byte configuration * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; /*Get WRP*/ pOBInit->WRPPage = FLASH_OB_GetWRP(); /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /*Get USER*/ pOBInit->USERConfig = FLASH_OB_GetUser(); } /** * @brief Get the Option byte user data * @param DATAAdress Address of the option byte DATA * This parameter can be one of the following values: * @arg @ref OB_DATA_ADDRESS_DATA0 * @arg @ref OB_DATA_ADDRESS_DATA1 * @retval Value programmed in USER data */ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { uint32_t value = 0; if (DATAAdress == OB_DATA_ADDRESS_DATA0) { /* Get value programmed in OB USER Data0 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; } else { /* Get value programmed in OB USER Data1 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; } return value; } /** * @} */ /** * @} */ /** @addtogroup FLASHEx_Private_Functions * @{ */ /** * @brief Full erase of FLASH memory Bank * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg @ref FLASH_BANK_1 Bank1 to be erased @if STM32F101xG * @arg @ref FLASH_BANK_2 Bank2 to be erased * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased @endif @if STM32F103xG * @arg @ref FLASH_BANK_2 Bank2 to be erased * @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (Banks == FLASH_BANK_BOTH) { /* bank1 & bank2 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR2, FLASH_CR2_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else if (Banks == FLASH_BANK_2) { /*Only bank2 will be erased*/ SET_BIT(FLASH->CR2, FLASH_CR2_MER); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else { #endif /* FLASH_BANK2_END */ #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } /** * @brief Enable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write protected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFF; #if defined(FLASH_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFF; #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be protected ******/ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { /* Enable write protection */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) if (WRP0_Data != 0xFFU) { OB->WRP0 &= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 &= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 &= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 &= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Disable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write unprotected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFF; #if defined(FLASH_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFF; #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFF; #endif /* FLASH_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be unprotected ******/ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #elif defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) if (WRP0_Data != 0xFFU) { OB->WRP0 |= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 |= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 |= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 |= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* FLASH_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Set the read protection level. * @param ReadProtectLevel specifies the read protection level. * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if (status == HAL_OK) { /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); WRITE_REG(OB->RDP, ReadProtectLevel); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). * And BFBF2(Bit5) for STM32F101xG and STM32F103xG . * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE((UserConfig & OB_IWDG_SW))); assert_param(IS_OB_STOP_SOURCE((UserConfig & OB_STOP_NO_RST))); assert_param(IS_OB_STDBY_SOURCE((UserConfig & OB_STDBY_NO_RST))); #if defined(FLASH_BANK2_END) assert_param(IS_OB_BOOT1((UserConfig & OB_BOOT1_SET))); #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_BANK2_END) OB->USER = (UserConfig | 0xF0U); #else OB->USER = (UserConfig | 0x88U); #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } return status; } /** * @brief Programs a half word at a specified Option Byte Data address. * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param Address specifies the address to be programmed. * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data specifies the data to be programmed. * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t *)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } /* Return the Option Byte Data Program Status */ return status; } /** * @brief Return the FLASH Write Protection Option Bytes value. * @retval The FLASH Write Protection Option Bytes value */ static uint32_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(READ_REG(FLASH->WRPR)); } /** * @brief Returns the FLASH Read Protection level. * @retval FLASH RDP level * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory */ static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; uint32_t tmp_reg = 0U; /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); if (tmp_reg == FLASH_OBR_RDPRT) { readstatus = OB_RDP_LEVEL_1; } else { readstatus = OB_RDP_LEVEL_0; } return readstatus; } /** * @brief Return the FLASH User Option Byte value. * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), * FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). * And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG . */ static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); } /** * @} */ /** * @} */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Erase the specified FLASH memory page * @param PageAddress FLASH page to erase * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; #if defined(FLASH_BANK2_END) if (PageAddress > FLASH_BANK1_END) { /* Proceed to erase the page */ SET_BIT(FLASH->CR2, FLASH_CR2_PER); WRITE_REG(FLASH->AR2, PageAddress); SET_BIT(FLASH->CR2, FLASH_CR2_STRT); } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); WRITE_REG(FLASH->AR, PageAddress); SET_BIT(FLASH->CR, FLASH_CR_STRT); #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @verbatim ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: (+) Input mode (+) Analog mode (+) Output mode (+) Alternate function mode (+) External interrupt/event lines [..] During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. [..] All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. [..] In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. [..] All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. [..] The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests ##### How to use this driver ##### ============================================================================== [..] (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_MODE 0x00000003U #define EXTI_MODE 0x10000000U #define GPIO_MODE_IT 0x00010000U #define GPIO_MODE_EVT 0x00020000U #define RISING_EDGE 0x00100000U #define FALLING_EDGE 0x00200000U #define GPIO_OUTPUT_TYPE 0x00000010U #define GPIO_NUMBER 16U /* Definitions for bit manipulation of CRL and CRH register */ #define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */ #define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */ #define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */ #define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */ #define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */ #define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */ #define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */ #define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs to be ready for use. @endverbatim * @{ */ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position; uint32_t ioposition = 0x00U; uint32_t iocurrent = 0x00U; uint32_t temp = 0x00U; uint32_t config = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for (position = 0U; position < GPIO_NUMBER; position++) { /* Get the IO position */ ioposition = (0x01U << position); /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; if (iocurrent == ioposition) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) { /* If we are configuring the pin in OUTPUT push-pull mode */ case GPIO_MODE_OUTPUT_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; break; /* If we are configuring the pin in OUTPUT open-drain mode */ case GPIO_MODE_OUTPUT_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; break; /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ case GPIO_MODE_AF_PP: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; break; /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ case GPIO_MODE_AF_OD: /* Check the GPIO speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; break; /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ case GPIO_MODE_INPUT: case GPIO_MODE_IT_RISING: case GPIO_MODE_IT_FALLING: case GPIO_MODE_IT_RISING_FALLING: case GPIO_MODE_EVT_RISING: case GPIO_MODE_EVT_FALLING: case GPIO_MODE_EVT_RISING_FALLING: /* Check the GPIO pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); if (GPIO_Init->Pull == GPIO_NOPULL) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; } else if (GPIO_Init->Pull == GPIO_PULLUP) { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; /* Set the corresponding ODR bit */ GPIOx->BSRR = ioposition; } else /* GPIO_PULLDOWN */ { config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; /* Reset the corresponding ODR bit */ GPIOx->BRR = ioposition; } break; /* If we are configuring the pin in INPUT analog mode */ case GPIO_MODE_ANALOG: config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); temp = AFIO->EXTICR[position >> 2U]; CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); AFIO->EXTICR[position >> 2U] = temp; /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { SET_BIT(EXTI->IMR, iocurrent); } else { CLEAR_BIT(EXTI->IMR, iocurrent); } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { SET_BIT(EXTI->EMR, iocurrent); } else { CLEAR_BIT(EXTI->EMR, iocurrent); } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { SET_BIT(EXTI->RTSR, iocurrent); } else { CLEAR_BIT(EXTI->RTSR, iocurrent); } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { SET_BIT(EXTI->FTSR, iocurrent); } else { CLEAR_BIT(EXTI->FTSR, iocurrent); } } } } } /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { uint32_t position = 0x00U; uint32_t iocurrent = 0x00U; uint32_t tmp = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ uint32_t registeroffset = 0U; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0U) { /* Get current io position */ iocurrent = (GPIO_Pin) & (1U << position); if (iocurrent) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); /* ODR default value is 0 */ CLEAR_BIT(GPIOx->ODR, iocurrent); /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = AFIO->EXTICR[position >> 2U]; tmp &= 0x0FU << (4U * (position & 0x03U)); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { tmp = 0x0FU << (4U * (position & 0x03U)); CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp); /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); } } position++; } } /** * @} */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read and Write * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the GPIOs. @endverbatim * @{ */ /** * @brief Reads the specified input port pin. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) { bitstatus = GPIO_PIN_SET; } else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } /** * @brief Sets or clears the selected data port bit. * * @note This function uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState: specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) { GPIOx->BSRR = GPIO_Pin; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } /** * @brief Toggles the specified GPIO pin * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->ODR ^= GPIO_Pin; } /** * @brief Locks GPIO Pins configuration registers. * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence * has been applied on a port bit, it is no longer possible to modify the value of the port bit until * the next reset. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ SET_BIT(tmp, GPIO_Pin); /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Read LCKK bit*/ tmp = GPIOx->LCKR; if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) { return HAL_OK; } else { return HAL_ERROR; } } /** * @brief This function handles EXTI interrupt request. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** * @brief EXTI line detection callbacks. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); /* NOTE: This function Should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.c * @author MCD Application Team * @brief GPIO Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * + Extended features functions * @verbatim ============================================================================== ##### GPIO Peripheral extension features ##### ============================================================================== [..] GPIO module on STM32F1 family, manage also the AFIO register: (+) Possibility to use the EVENTOUT Cortex feature ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to use EVENTOUT Cortex feature (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @brief GPIO HAL module driver * @{ */ #ifdef HAL_GPIO_MODULE_ENABLED /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions * @{ */ /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions * @verbatim ============================================================================== ##### Extended features functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() @endverbatim * @{ */ /** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * @retval None */ void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) { /* Verify the parameters */ assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); /* Apply the new configuration */ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); } /** * @brief Enables the Event Output. * @retval None */ void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } /** * @brief Disables the Event Output. * @retval None */ void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_iwdg.c * @author MCD Application Team * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: * + Initialization and Start functions * + IO operation functions * @verbatim ============================================================================== ##### IWDG Generic features ##### ============================================================================== [..] (+) The IWDG can be started by either software or hardware (configurable through option byte). (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even if the main clock fails. (+) Once the IWDG is started, the LSI is forced ON and both can not be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. (+) Debug mode : When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx devices provide the capability to measure the LSI frequency (LSI clock connected internally to TIM5 CH4 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. ##### How to use this driver ##### ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts downcounting. (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR. (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. (++) wait for status flags to be reset" (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_IWDG_Refresh() function. *** IWDG HAL driver macros list *** ==================================== [..] Below the list of most used macros in IWDG HAL driver: (+) __HAL_IWDG_START: Enable the IWDG peripheral (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_IWDG_MODULE_ENABLED /** @defgroup IWDG IWDG * @brief IWDG HAL module driver. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ /* Status register need 5 RC LSI divided by prescaler clock to be updated. With higher prescaler (256), and according to HSI variation, we need to wait at least 6 cycles so 48 ms. */ #define HAL_IWDG_DEFAULT_TIMEOUT 48U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup IWDG_Exported_Functions * @{ */ /** @addtogroup IWDG_Exported_Functions_Group1 * @brief Initialization and Start functions. * @verbatim =============================================================================== ##### Initialization and Start functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef of associated handle. (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog is reloaded in order to exit function with correct time base. @endverbatim * @{ */ /** * @brief Initialize the IWDG according to the specified parameters in the * IWDG_InitTypeDef and start watchdog. Before exiting function, * watchdog is refreshed in order to have correct time base. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); /* Enable IWDG. LSI is turned on automaticaly */ __HAL_IWDG_START(hiwdg); /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; hiwdg->Instance->RLR = hiwdg->Init.Reload; /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); /* Wait for register to be updated */ while (hiwdg->Instance->SR != RESET) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { return HAL_TIMEOUT; } } /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); /* Return function status */ return HAL_OK; } /** * @} */ /** @addtogroup IWDG_Exported_Functions_Group2 * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Refresh the IWDG. @endverbatim * @{ */ /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); /* Return function status */ return HAL_OK; } /** * @} */ /** * @} */ #endif /* HAL_IWDG_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions * + Peripheral Control functions * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Constants PWR Private Constants * @{ */ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ #define PVD_MODE_IT 0x00010000U #define PVD_MODE_EVT 0x00020000U #define PVD_RISING_EDGE 0x00000001U #define PVD_FALLING_EDGE 0x00000002U /** * @} */ /** @defgroup PWR_register_alias_address PWR Register alias address * @{ */ /* ------------- PWR registers bit address in the alias region ---------------*/ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) #define PWR_CR_OFFSET 0x00U #define PWR_CSR_OFFSET 0x04U #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) /** * @} */ /** @defgroup PWR_CR_register_alias PWR CR Register alias address * @{ */ /* --- CR Register ---*/ /* Alias word address of LPSDSR bit */ #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) /* Alias word address of DBP bit */ #define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) /* Alias word address of PVDE bit */ #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) /** * @} */ /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address * @{ */ /* --- CSR Register ---*/ /* Alias word address of EWUP1 bit */ #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) /** * @} */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup PWR_Private_Functions PWR Private Functions * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) * @{ */ static void PWR_OverloadWfe(void); /* Private functions ---------------------------------------------------------*/ __NOINLINE static void PWR_OverloadWfe(void) { __asm volatile("wfe"); __asm volatile("nop"); } /** * @} */ /** @defgroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] After reset, the backup domain (RTC registers, RTC backup data registers) is protected against possible unwanted write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim * @{ */ /** * @brief Deinitializes the PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) { __HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enables access to the backup domain (RTC registers, RTC * backup data registers ). * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { /* Enable access to RTC and backup registers */ *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE; } /** * @brief Disables access to the backup domain (RTC registers, RTC * backup data registers). * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { /* Disable access to RTC and backup registers */ *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE; } /** * @} */ /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== *** PVD configuration *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** ================================ [..] (+) WakeUp pin is used to wake up the system from Standby mode. This pin is forced in input pull-down configuration and is active on rising edges. (+) There is one WakeUp pin: WakeUp Pin 1 on PA.00. [..] *** Low Power modes configuration *** ===================================== [..] The device features 3 low-power modes: (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like NVIC, SysTick, etc. are kept running (+) Stop mode: All clocks are stopped (+) Standby mode: 1.8V domain powered off *** Sleep mode *** ================== [..] (+) Entry: The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (+) Exit: (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) (+++) Any EXTI Line (Internal or External) configured in Event mode *** Stop mode *** ================= [..] The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In Stop mode, all I/O pins keep the same state as in Run mode. (+) Entry: The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) function with: (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction (+) Exit: (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. *** Standby mode *** ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (+) Entry: (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (+) Exit: (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in NRSTpin, IWDG Reset *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] (+) The MCU can be woken up from low-power mode by an RTC Alarm event, without depending on an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop and Standby modes (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. *** PWR Workarounds linked to Silicon Limitation *** ==================================================== [..] Below the list of all silicon limitations known on STM32F1xx prouct. (#)Workarounds Implemented inside PWR HAL Driver (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function @endverbatim * @{ */ /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } /** * @brief Enables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_EnablePVD(void) { /* Enable the power voltage detector */ *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE; } /** * @brief Disables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_DisablePVD(void) { /* Disable the power voltage detector */ *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE; } /** * @brief Enables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Enable the EWUPx pin */ *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; } /** * @brief Disables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Disable the EWUPx pin */ *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; } /** * @brief Enters Sleep mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ /* No check on Regulator because parameter not used in SLEEP mode */ /* Prevent unused argument(s) compilation warning */ UNUSED(Regulator); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ if (SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } } /** * @brief Enters Stop mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by using an interrupt or a wakeup event, * HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ CLEAR_BIT(PWR->CR, PWR_CR_PDDS); /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); PWR_OverloadWfe(); /* WFE redefine locally */ PWR_OverloadWfe(); /* WFE redefine locally */ } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enters Standby mode. * @note In Standby mode, all I/O pins are high impedance except for: * - Reset pad (still available) * - TAMPER pin if configured for tamper or calibration out. * - WKUP pin (PA0) if enabled. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Select Standby mode */ SET_BIT(PWR->CR, PWR_CR_PDDS); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined(__CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enables CORTEX M3 SEVONPEND bit. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_EnableSEVOnPend(void) { /* Set SEVONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Disables CORTEX M3 SEVONPEND bit. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) { /* Clear SEVONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief This function handles the PWR PVD interrupt request. * @note This API should be called under the PVD_IRQHandler(). * @retval None */ void HAL_PWR_PVD_IRQHandler(void) { /* Check PWR exti flag */ if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PWR Exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } } /** * @brief PWR PVD interrupt callback * @retval None */ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc.c * @author MCD Application Team * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from Internal High Speed oscillator (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS) ##### RCC Limitations ##### ============================================================================== [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup RCC RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA #define MCO1_PIN GPIO_PIN_8 /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through the PLL as System clock source. (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC clock source. (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x [..] System, AHB and APB buses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock divided by 128. (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly. This clock is derived of the main PLL through PLL Multiplier. (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK (+@) IWDG clock which is always the LSI clock. (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. @endverbatim * @{ */ /* Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ | Latency | SYSCLK clock frequency (MHz) | |---------------|-------------------------------| |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | |---------------|-------------------------------| |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | |---------------|-------------------------------| |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | +-----------------------------------------------+ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL, PLL2 and PLL3 are OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled * - All flags are cleared * @note This function does not modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL_StatusTypeDef */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; /* Get Start Tick */ tickstart = HAL_GetTick(); /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Set HSITRIM bits to the reset value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { return HAL_ERROR; } /* Get Start Tick */ tickstart = HAL_GetTick(); /* Second step is to clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON); /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Ensure to reset PLLSRC and PLLMUL bits */ CLEAR_REG(RCC->CFGR); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Reset HSEON & CSSON bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); #if defined(RCC_PLL2_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); /* Clear PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } #endif /* RCC_PLL2_SUPPORT */ #if defined(RCC_PLLI2S_SUPPORT) /* Get Start Tick */ tickstart = HAL_GetTick(); /* Clear PLL3ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); #endif /* RCC_CFGR2_PREDIV1 */ /* Reset all CSR flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); return HAL_OK; } /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS) * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*------------------------------ LSI Configuration -------------------------*/ /*------------------------------ LSE Configuration -------------------------*/ #if defined(RCC_CR_PLL2ON) /*-------------------------------- PLL2 Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) { /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) { /* Check the parameters */ assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Set PREDIV1 source to HSE */ CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) { /* Check the parameter */ assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); #if defined(RCC_CFGR2_PREDIV1SRC) assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } else { return HAL_ERROR; } } return HAL_OK; } /** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. * @param FLatency FLASH Latency * The value of this parameter depend on device used within the same series * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick */ tickstart = HAL_GetTick(); if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(TICK_INT_PRIORITY); return HAL_OK; } /** * @} */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @endverbatim * @{ */ /** * @brief Selects the clock source to output on MCO pin. * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock @if STM32F105xC * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source @endif @if STM32F107xC * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source @endif * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio = {0U}; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* Prevent unused argument(s) compilation warning */ UNUSED(RCC_MCOx); UNUSED(RCC_MCODiv); /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; gpio.Pull = GPIO_NOPULL; gpio.Pin = MCO1_PIN; /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } /** * @brief Enables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)ENABLE; } /** * @brief Disables the Clock Security System. * @retval None */ void HAL_RCC_DisableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)DISABLE; } /** * @brief Returns the SYSCLK frequency * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; uint32_t sysclockfreq = 0U; #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; break; } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv)); } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); } sysclockfreq = pllclk; break; } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; break; } } return sysclockfreq; } /** * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; } /** * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; #if defined(RCC_CFGR2_PREDIV1SRC) /* Get the Prediv1 source --------------------------------------------------*/ RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Get the HSE configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } else { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); /* Get the HSI configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } else { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); /* Get the LSE configuration -----------------------------------------------*/ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } else { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } /* Get the LSI configuration -----------------------------------------------*/ if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } else { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } /* Get the PLL configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } else { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); #if defined(RCC_CR_PLL2ON) /* Get the PLL2 configuration -----------------------------------------------*/ if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) { RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON; } else { RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF; } RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2(); RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL); #endif /* RCC_CR_PLL2ON */ } /** * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; #endif } /** * @brief This function handles the RCC CSS interrupt request. * @note This API should be called under the NMI_Handler(). * @retval None */ void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } } /** * @brief RCC Clock Security System interrupt callback * @retval none */ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /** @defgroup RCCEx RCCEx * @brief RCC Extension HAL module driver. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Macros RCCEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. @endverbatim * @{ */ /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(RTC clock). * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U, temp_reg = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t pllactive = 0U; #endif /* STM32F105xC || STM32F107xC */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); } #if defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ I2S2 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); } /*------------------------------ I2S3 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) { /* Check the parameters */ assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); /* Configure the I2S3 clock source */ __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); } /*------------------------------ PLL I2S Configuration ----------------------*/ /* Check that PLLI2S need to be enabled */ if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Update flag to indicate that PLL I2S should be active */ pllactive = 1; } /* Check if PLL I2S need to be enabled */ if (pllactive == 1) { /* Enable PLL I2S only if not active */ if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) { /* Check the parameters */ assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) { return HAL_ERROR; } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) { return HAL_ERROR; } } } #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; } /** * @brief Get the PeriphClkInit according to the internal * RCC configuration registers. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t srcclk = 0U; /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; /* Get the RTC configuration -----------------------------------------------*/ srcclk = __HAL_RCC_GET_RTC_SOURCE(); /* Source clock is LSE or LSI*/ PeriphClkInit->RTCClockSelection = srcclk; /* Get the ADC clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); #if defined(STM32F105xC) || defined(STM32F107xC) /* Get the I2S2 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); /* Get the I2S3 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) /* Get the I2S2 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; /* Get the I2S3 clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; #endif /* STM32F103xE || STM32F103xG */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) /* Get the USB clock configuration -----------------------------------------*/ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ } /** * @brief Returns the peripheral clock frequency * @note Returns 0 if peripheral clock is unknown * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock @if STM32F103xE * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock @endif @if STM32F103xG * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock @endif @if STM32F105xC * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F107xC * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F102xx * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif @if STM32F103xx * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { #if defined(STM32F105xC) || defined(STM32F107xC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; #endif /* STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) { #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_USB: { /* Get RCC configuration ------------------------------------------------------*/ temp_reg = RCC->CFGR; /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) { pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE) prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); } else { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } #else if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); } #endif /* STM32F105xC || STM32F107xC */ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); } /* Calcul of the USB frequency*/ #if defined(STM32F105xC) || defined(STM32F107xC) /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) { /* Prescaler of 2 selected for USB */ frequency = pllclk; } else { /* Prescaler of 3 selected for USB */ frequency = (2 * pllclk) / 3; } #else /* USBCLK = PLLCLK / USB prescaler */ if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) { /* No prescaler selected for USB */ frequency = pllclk; } else { /* Prescaler of 1.5 selected for USB */ frequency = (pllclk * 2) / 3; } #endif } break; } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_I2S2: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) { /* SYSCLK used as source clock for I2S2 */ frequency = HAL_RCC_GetSysClockFreq(); } else { /* Check if PLLI2S is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; } case RCC_PERIPHCLK_I2S3: { #if defined(STM32F103xE) || defined(STM32F103xG) /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); #else if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) { /* SYSCLK used as source clock for I2S3 */ frequency = HAL_RCC_GetSysClockFreq(); } else { /* Check if PLLI2S is enabled */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } #endif /* STM32F103xE || STM32F103xG */ break; } #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ case RCC_PERIPHCLK_RTC: { /* Get RCC BDCR configuration ------------------------------------------------------*/ temp_reg = RCC->BDCR; /* Check if LSE is ready if RTC clock selection is LSE */ if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } /* Check if LSI is ready if RTC clock selection is LSI */ else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) { frequency = LSI_VALUE; } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { frequency = HSE_VALUE / 128U; } /* Clock not enabled for RTC*/ else { frequency = 0U; } break; } case RCC_PERIPHCLK_ADC: { frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; } } return (frequency); } /** * @} */ #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function * @brief PLLI2S Management functions * @verbatim =============================================================================== ##### Extended PLLI2S Management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the PLLI2S activation or deactivation @endverbatim * @{ */ /** * @brief Enable PLLI2S * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that * contains the configuration information for the PLLI2S * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) { uint32_t tickstart = 0U; /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Check the parameters */ assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); /* Prediv2 can be written only when the PLL2 is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLLI2S. */ __HAL_RCC_PLLI2S_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); /* Configure the main PLLI2S multiplication factors. */ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); /* Enable the main PLLI2S. */ __HAL_RCC_PLLI2S_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ return HAL_ERROR; } return HAL_OK; } /** * @brief Disable PLLI2S * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) { uint32_t tickstart = 0U; /* Disable PLL I2S as not requested by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) { /* Disable the main PLLI2S. */ __HAL_RCC_PLLI2S_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ return HAL_ERROR; } return HAL_OK; } /** * @} */ /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function * @brief PLL2 Management functions * @verbatim =============================================================================== ##### Extended PLL2 Management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the PLL2 activation or deactivation @endverbatim * @{ */ /** * @brief Enable PLL2 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that * contains the configuration information for the PLL2 * @note The PLL2 configuration not modified if used indirectly as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) { uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { /* Check the parameters */ assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); /* Prediv2 can be written only when the PLLI2S is disabled. */ /* Return an error only if new value is different from the programmed value */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) { return HAL_ERROR; } /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the HSE prediv2 factor --------------------------------*/ __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); /* Configure the main PLL2 multiplication factors. */ __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); /* Enable the main PLL2. */ __HAL_RCC_PLL2_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } return HAL_OK; } /** * @brief Disable PLL2 * @note PLL2 is not disabled if used indirectly as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) { uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) { return HAL_ERROR; } else { /* Disable the main PLL2. */ __HAL_RCC_PLL2_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL2 is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } return HAL_OK; } /** * @} */ #endif /* STM32F105xC || STM32F107xC */ /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + TIM Time Base Initialization * + TIM Time Base Start * + TIM Time Base Start Interruption * + TIM Time Base Start DMA * + TIM Output Compare/PWM Initialization * + TIM Output Compare/PWM Channel Configuration * + TIM Output Compare/PWM Start * + TIM Output Compare/PWM Start Interruption * + TIM Output Compare/PWM Start DMA * + TIM Input Capture Initialization * + TIM Input Capture Channel Configuration * + TIM Input Capture Start * + TIM Input Capture Start Interruption * + TIM Input Capture Start DMA * + TIM One Pulse Initialization * + TIM One Pulse Channel Configuration * + TIM One Pulse Start * + TIM Encoder Interface Initialization * + TIM Encoder Interface Start * + TIM Encoder Interface Start Interruption * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration @verbatim ============================================================================== ##### TIMER Generic features ##### ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an Output Compare signal. (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] Use Function @ref HAL_TIM_RegisterCallback() to register a callback. @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) IC_MspInitCallback : TIM IC Msp Init Callback. (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. (+) OC_MspInitCallback : TIM OC Msp Init Callback. (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. (+) ErrorCallback : TIM Error Callback. (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions * @{ */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. (+) Start the Time Base and enable interrupt. (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Base_MspDeInitCallback == NULL) { htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; } /* DeInit the low level hardware */ htim->Base_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in DMA mode. * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in DMA mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @verbatim ============================================================================== ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the TIM Output Compare. (+) Stop the TIM Output Compare. (+) Start the TIM Output Compare and enable interrupt. (+) Stop the TIM Output Compare and disable interrupt. (+) Start the TIM Output Compare and enable DMA transfer. (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } /* DeInit the low level hardware */ htim->OC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @verbatim ============================================================================== ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the TIM PWM. (+) Stop the TIM PWM. (+) Start the TIM PWM and enable interrupt. (+) Stop the TIM PWM and disable interrupt. (+) Start the TIM PWM and enable DMA transfer. (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } /* DeInit the low level hardware */ htim->PWM_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ } /** * @brief Starts the PWM signal generation. * @param htim TIM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); // if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { // /* Enable the main output */ // __HAL_TIM_MOE_ENABLE(htim); // } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @verbatim ============================================================================== ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the TIM Input Capture. (+) Stop the TIM Input Capture. (+) Start the TIM Input Capture and enable interrupt. (+) Stop the TIM Input Capture and disable interrupt. (+) Start the TIM Input Capture and enable DMA transfer. (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } /* DeInit the low level hardware */ htim->IC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @verbatim ============================================================================== ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the TIM One Pulse. (+) Stop the TIM One Pulse. (+) Start the TIM One Pulse and enable interrupt. (+) Stop the TIM One Pulse and disable interrupt. (+) Start the TIM One Pulse and enable DMA transfer. (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @note When the timer instance is initialized in One Pulse mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } /* DeInit the low level hardware */ htim->OnePulse_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @verbatim ============================================================================== ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the TIM Encoder. (+) Stop the TIM Encoder. (+) Start the TIM Encoder and enable interrupt. (+) Stop the TIM Encoder and disable interrupt. (+) Start the TIM Encoder and enable DMA transfer. (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @note When the timer instance is initialized in Encoder mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Encoder interface * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } /* DeInit the low level hardware */ htim->Encoder_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } default: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 The destination Buffer address for IC1. * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_ALL: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } default: break; } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief TIM IRQ handler management * @verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== [..] This section provides Timer IRQ handler function. @endverbatim * @{ */ /** * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief TIM Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM Output Compare handle * @param sConfig TIM Output Compare configuration structure * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); break; } default: break; } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_2) { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } else { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM PWM handle * @param sConfig TIM PWM configuration structure * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; break; } default: break; } __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @note To output a waveform with a minimum delay user can enable the fast * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx * output is forced in response to the edge detection on TIx input, * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); break; } default: break; } switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM DMA Burst mode * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); /* Return function status */ return HAL_OK; } /** * @brief Stop the DMA burst reading * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Generate a software event * @param htim TIM handle * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances * supporting a break input. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); /* Process Locked */ __HAL_LOCK(htim); /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); /* Return function status */ return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim TIM handle * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); break; } case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); break; } default: break; } switch (Channel) { case TIM_CHANNEL_1: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } else { /* Disable the OCREF clear feature for Channel 1 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; } case TIM_CHANNEL_2: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } else { /* Disable the OCREF clear feature for Channel 2 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } break; } case TIM_CHANNEL_3: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } else { /* Disable the OCREF clear feature for Channel 3 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } break; } case TIM_CHANNEL_4: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } else { /* Disable the OCREF clear feature for Channel 4 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the clock source to be used * @param htim TIM handle * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); break; } case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; break; } case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; break; } case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); break; } case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); break; } case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); break; } case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input * @param htim TIM handle. * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 * pins are connected to the TI1 input (XOR combination) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Reset the TI1 selection */ tmpcr2 &= ~TIM_CR2_TI1S; /* Set the TI1 selection */ tmpcr2 |= TI1_Selection; /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; return HAL_OK; } /** * @brief Configures the TIM in Slave mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit * @param htim TIM handle. * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; break; } default: break; } return tmpreg; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: (+) TIM Period elapsed callback (+) TIM Output Compare callback (+) TIM Input capture callback (+) TIM Trigger callback (+) TIM Error callback @endverbatim * @{ */ /** * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } /** * @brief Period elapsed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file */ } /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } /** * @brief Input Capture half complete callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file */ } /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User TIM callback to be used instead of the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @param pCallback pointer to the callback function * @retval status */ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID: htim->PeriodElapsedCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID: htim->PeriodElapsedHalfCpltCallback = pCallback; break; case HAL_TIM_TRIGGER_CB_ID: htim->TriggerCallback = pCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID: htim->TriggerHalfCpltCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID: htim->IC_CaptureCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID: htim->IC_CaptureHalfCpltCallback = pCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID: htim->OC_DelayElapsedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID: htim->PWM_PulseFinishedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID: htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; case HAL_TIM_ERROR_CB_ID: htim->ErrorCallback = pCallback; break; case HAL_TIM_COMMUTATION_CB_ID: htim->CommutationCallback = pCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID: htim->CommutationHalfCpltCallback = pCallback; break; case HAL_TIM_BREAK_CB_ID: htim->BreakCallback = pCallback; break; default: /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = pCallback; break; default: /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } /** * @brief Unregister a TIM callback * TIM callback is redirected to the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; case HAL_TIM_PERIOD_ELAPSED_CB_ID: htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID: htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ break; case HAL_TIM_TRIGGER_CB_ID: htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ break; case HAL_TIM_TRIGGER_HALF_CB_ID: htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ break; case HAL_TIM_IC_CAPTURE_CB_ID: htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID: htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID: htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID: htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID: htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ break; case HAL_TIM_ERROR_CB_ID: htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ break; case HAL_TIM_COMMUTATION_CB_ID: htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ break; case HAL_TIM_COMMUTATION_HALF_CB_ID: htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ break; case HAL_TIM_BREAK_CB_ID: htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ break; default: /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID: htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID: htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID: htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID: htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID: htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID: htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID: htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID: htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID: htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID: htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID: htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID: htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID: htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID: htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; default: /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief TIM Peripheral State functions * @verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Base handle state. * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM OC handle state. * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM PWM handle state. * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Input Capture handle state. * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM One Pulse Mode handle state. * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM handle * @retval Active channel */ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) { return htim->Channel; } /** * @brief Return actual state of the TIM channel. * @param htim TIM handle * @param Channel TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); return channel_state; } /** * @brief Return actual state of a DMA burst operation. * @param htim TIM handle * @retval DMA burst state */ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); return htim->DMABurstState; } /** * @} */ /** * @} */ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } else { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureHalfCpltCallback(htim); #else HAL_TIM_IC_CaptureHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Period Elapse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else HAL_TIM_PeriodElapsedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else HAL_TIM_TriggerHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Slave Timer configuration function * @param htim TIM handle * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = htim->Instance->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; break; } case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); break; } default: break; } return HAL_OK; } /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 |= TIM_ICSelection; /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P); tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P); tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Reset interrupt callbacks to the legacy weak callbacks. * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_tim_ex.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Timer remapping capabilities configuration @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== [..] The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the Timer Hall Sensor Interface and the commutation event with the corresponding Interrupt and DMA request if needed (Note that One Timer is used to interface with the Hall sensor Interface and another Timer should be used to use the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" /** @addtogroup STM32F1xx_HAL_Driver * @{ */ /** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. (+) Start the Hall Sensor Interface and enable interrupts. (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. @endverbatim * @{ */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. * @note When the timer instance is initialized in Hall Sensor Interface mode, * timer channels 1 and channel 2 are reserved and cannot be used for * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->HallSensor_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; OC_Config.OCMode = TIM_OCMODE_PWM2; OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; OC_Config.Pulse = sConfig->Commutation_Delay; TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Hall Sensor interface * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } /* DeInit the low level hardware */ htim->HallSensor_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Hall Sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. (+) Start the Complementary Output Compare/PWM and enable interrupts. (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM OC handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @verbatim ============================================================================== ##### Timer Complementary PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. (+) Start the Complementary PWM and enable interrupts. (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. (+) Start the Complementary Input Capture measurement. (+) Stop the Complementary Input Capture. (+) Start the Complementary Input Capture and enable interrupts. (+) Stop the Complementary Input Capture and disable interrupts. (+) Start the Complementary Input Capture and enable DMA transfers. (+) Stop the Complementary Input Capture and disable DMA transfers. (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. @endverbatim * @{ */ /** * @brief Configure the TIM commutation event sequence. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with interrupt. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with DMA. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in master mode. * @param htim TIM handle. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @note Interrupts can be generated when an active level is detected on the * break input, the break 2 input or the system break input. Break * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); UNUSED(Remap); return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @verbatim ============================================================================== ##### Extended Callbacks functions ##### ============================================================================== [..] This section provides Extended TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @endverbatim * @{ */ /** * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } /** * @brief Hall commutation changed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @verbatim ============================================================================== ##### Extended Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Hall Sensor interface handle state. * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return actual state of the TIM complementary channel. * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); return channel_state; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Commutation half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationHalfCpltCallback(htim); #else HAL_TIMEx_CommutHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback (complementary channel). * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA error callback (complementary channel) * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/configuration.h ================================================ #ifndef CONFIGURATION_H_ #define CONFIGURATION_H_ #include /** * Configuration.h * Define here your default pre settings for TS80(P) or TS10(0/1) * */ //=========================================================================== //============================= Default Settings ============================ //=========================================================================== /** * Default soldering temp is 320.0 C * Temperature the iron sleeps at - default 150.0 C */ #define SLEEP_TEMP 150 // Default sleep temperature #define BOOST_TEMP 420 // Default boost temp. #define BOOST_MODE_ENABLED 1 // 0: Disable 1: Enable /** * Blink the temperature on the cooling screen when its > 50C */ #define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable /** * How many seconds/minutes we wait until going to sleep/shutdown. * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds! */ #define SLEEP_TIME 5 // x10 Seconds #define SHUTDOWN_TIME 10 // Minutes /** * Auto start off for safety. * Pissible values are: * 0 - none * 1 - Soldering Temperature * 2 - Sleep Temperature * 3 - Sleep Off Temperature */ #define AUTO_START_MODE 0 // Default to none /** * Locking Mode * When in soldering mode a long press on both keys toggle the lock of the buttons * Possible values are: * 0 - Desactivated * 1 - Lock except boost * 2 - Full lock */ #define LOCKING_MODE 0 // Default to desactivated for safety /** * OLED Orientation * */ #define ORIENTATION_MODE 2 // 0: Right 1:Left 2:Automatic - Default Automatic #define MAX_ORIENTATION_MODE 2 // Up to auto #define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change /** * OLED Brightness * */ #if defined(MODEL_TS101) #define MIN_BRIGHTNESS 1 // Min OLED brightness selectable #define MAX_BRIGHTNESS 101 // Max OLED brightness selectable #else #define MIN_BRIGHTNESS 0 // Min OLED brightness selectable #define MAX_BRIGHTNESS 100 // Max OLED brightness selectable #endif #define BRIGHTNESS_STEP 25 // OLED brightness increment #define DEFAULT_BRIGHTNESS 25 // default OLED brightness /** * Temp change settings */ #define TEMP_CHANGE_SHORT_STEP 1 // Default temp change short step +1 #define TEMP_CHANGE_LONG_STEP 10 // Default temp change long step +10 #define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value #define TEMP_CHANGE_LONG_STEP_MAX 90 // Temp change long step MAX value /* Power pulse for keeping power banks awake*/ #define POWER_PULSE_INCREMENT 1 #define POWER_PULSE_MAX 100 // x10 max watts #define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds #define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds #ifdef MODEL_TS100 #define POWER_PULSE_DEFAULT 0 #else #define POWER_PULSE_DEFAULT 5 #endif /* TS100 */ #define POWER_PULSE_WAIT_DEFAULT 4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s #define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms /** * OLED Orientation Sensitivity on Automatic mode! * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive> */ #define SENSITIVITY 7 // Default 7 /** * Detailed soldering screen * Detailed idle screen (off for first time users) */ #define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0 #define DETAILED_IDLE 0 // 0: Disable 1: Enable - Default 0 #define THERMAL_RUNAWAY_TIME_SEC 20 #define THERMAL_RUNAWAY_TEMP_C 3 #define CUT_OUT_SETTING 0 // default to no cut-off voltage #define RECOM_VOL_CELL 33 // Minimum voltage per cell (Recommended 3.3V (33)) #define TEMPERATURE_INF 0 // default to 0 #define DESCRIPTION_SCROLL_SPEED 0 // 0: Slow 1: Fast - default to slow #define ANIMATION_LOOP 1 // 0: off 1: on #define ANIMATION_SPEED settingOffSpeed_t::MEDIUM #define OP_AMP_Rf_TS100 750 * 1000 // 750 Kilo-ohms -> From schematic, R1 #define OP_AMP_Rin_TS100 2370 // 2.37 Kilo-ohms -> From schematic, R2 #define OP_AMP_GAIN_STAGE_TS100 (1 + (OP_AMP_Rf_TS100 / OP_AMP_Rin_TS100)) #define OP_AMP_Rf_TS80 180 * 1000 // 180 Kilo-ohms -> From schematic, R6 #define OP_AMP_Rin_TS80 2000 // 2.0 Kilo-ohms -> From schematic, R3 #define OP_AMP_GAIN_STAGE_TS80 (1 + (OP_AMP_Rf_TS80 / OP_AMP_Rin_TS80)) #define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc #define ADC_VDD_MV 3300 // ADC max reading millivolts #define POW_PD_EXT 0 // Deriving the Voltage div: // Vin_max = (3.3*(r1+r2))/(r2) // vdiv = (32768*4)/(vin_max*10) #if defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) + defined(MODEL_TS101) > 1 #error "Multiple models defined!" #elif defined(MODEL_TS100) + defined(MODEL_TS80) + defined(MODEL_TS80P) + defined(MODEL_TS101) == 0 #error "No model defined!" #endif #define NEEDS_VBUS_PROBE 0 // Miniware is swapping IMU's around a bit now, so we turn them all on #define ACCEL_MMA #define ACCEL_LIS #define ACCEL_SC7 #define ACCEL_MSA #define ACCEL_BMA #define MIN_CALIBRATION_OFFSET 100 // Min value for calibration #define SOLDERING_TEMP 320 // Default soldering temp is 320.0 °C #define PID_TIM_HZ (8) // Tick rate of the PID loop #define MAX_TEMP_C 450 // Max soldering temp selectable °C #define MAX_TEMP_F 850 // Max soldering temp selectable °F #define MIN_TEMP_C 10 // Min soldering temp selectable °C #define MIN_TEMP_F 50 // Min soldering temp selectable °F #define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C #define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F // Miniware cant be trusted, and keep using the GD32 randomly now, so assume they will clones in the future #define I2C_SOFT_BUS_1 1 #ifdef MODEL_TS100 #define VOLTAGE_DIV 467 // 467 - Default divider from schematic #define CALIBRATION_OFFSET 900 // 900 - Default adc offset in uV #define PID_POWER_LIMIT 70 // Sets the max pwm power limit #define POWER_LIMIT 0 // 0 watts default limit #define MAX_POWER_LIMIT 70 #define POWER_LIMIT_STEPS 5 #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS100 #define TEMP_uV_LOOKUP_HAKKO #define USB_PD_VMAX 20 // Maximum voltage for PD to negotiate #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define HARDWARE_MAX_WATTAGE_X10 750 #define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second #define TIP_RESISTANCE 75 // x10 ohms, 7.5 typical for ts100 tips #define POW_DC #define I2C_SOFT_BUS_1 1 #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define TIPTYPE_T12 1 // Can manually pick a T12 tip #define TEMP_TMP36 #endif /* TS100 */ #ifdef MODEL_TS101 #define VOLTAGE_DIV 700 // 700 - Default divider from schematic #define CALIBRATION_OFFSET 900 // 900 - Default adc offset in uV #define PID_POWER_LIMIT 100 // Sets the max pwm power limit #define POWER_LIMIT 0 // 0 watts default limit #define MAX_POWER_LIMIT 100 #define POWER_LIMIT_STEPS 5 #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS100 #define TEMP_uV_LOOKUP_HAKKO #define ACCEL_LIS_CLONE 1 #define HARDWARE_MAX_WATTAGE_X10 1000 #define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second #define TIP_RESISTANCE 75 // x10 ohms, 7.5 typical for ts100 tips #define TIP_HAS_DIRECT_PWM 1 #define POW_DC 1 #define POW_PD 1 #define USB_PD_EPR_WATTAGE 140 /* EPR Supported */ #define I2C_SOFT_BUS_2 1 #define OLED_I2CBB1 1 #define USB_PD_I2CBB2 1 #define USB_PD_VMAX 28 // Device supposedly can do 28V; looks like vmax is 33 ish #define OLED_128x32 1 #define OLED_FLIP 1 #define HAS_SPLIT_POWER_PATH 1 #define TEMP_NTC 1 #define ACCEL_I2CBB1 1 #define POW_EPR 1 #define TIP_TYPE_SUPPORT 1 // Support for tips of different types, i.e. resistance #define AUTO_TIP_SELECTION 1 // Can auto-select the tip #define TIPTYPE_T12 1 // Can manually pick a T12 tip #define HAS_POWER_DEBUG_MENU #define DEBUG_POWER_MENU_BUTTON_B #endif /* TS101 */ #if defined(MODEL_TS80) + defined(MODEL_TS80P) > 0 #define MAX_POWER_LIMIT 40 #define POWER_LIMIT_STEPS 2 #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_TS80 #define TEMP_uV_LOOKUP_TS80 #define USB_PD_VMAX 12 // Maximum voltage for PD to negotiate #define TIP_THERMAL_MASS 40 #define TIP_RESISTANCE 45 // x10 ohms, 4.5 typical for ts80 tips #define I2C_SOFT_BUS_2 1 #define LIS_ORI_FLIP #define OLED_FLIP #define TIPTYPE_TS80 1 // Only one tip type so far #endif /* TS80(P) */ #ifdef MODEL_TS80 #define VOLTAGE_DIV 780 // Default divider from schematic #define CALIBRATION_OFFSET 900 // the adc offset in uV #define PID_POWER_LIMIT 35 // Sets the max pwm power limit #define POWER_LIMIT 32 // 24 watts default power limit #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define HARDWARE_MAX_WATTAGE_X10 320 #define POW_QC #define TEMP_TMP36 #define I2C_SOFT_BUS_1 1 #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #endif /* TS80 */ #ifdef MODEL_TS80P #define VOLTAGE_DIV 650 // Default for TS80P with slightly different resistors #define CALIBRATION_OFFSET 1500 // the adc offset in uV #define PID_POWER_LIMIT 35 // Sets the max pwm power limit #define POWER_LIMIT 32 // 30 watts default power limit #define I2C_SOFT_BUS_2 1 #define HARDWARE_MAX_WATTAGE_X10 320 #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define POW_PD 1 #define USB_PD_EPR_WATTAGE 0 /*No EPR*/ #define POW_QC 1 #define TEMP_NTC #define I2C_SOFT_BUS_2 1 #define I2C_SOFT_BUS_1 1 #define OLED_I2CBB1 1 #define ACCEL_I2CBB1 1 #define SC7_ORI_FLIP #endif /* TS80P */ #ifdef MODEL_TS101 // For whatever reason, Miniware decided to not build a reliable DFU bootloader // It can't appear to flash to some of the upper pages of flash, // I'm slightly suspect a watchdog or something runs out // as device resets before file finishes copying // So logo has to be located on page 99 or else it cant be flashed on stock bootloader #define FLASH_LOGOADDR (0x08000000 + (99 * 1024)) #define SETTINGS_START_PAGE (0x08000000 + (127 * 1024)) #else #define FLASH_LOGOADDR (0x08000000 + (62 * 1024)) #define SETTINGS_START_PAGE (0x08000000 + (63 * 1024)) #define OLED_96x16 1 #endif /* TS101 */ #endif /* CONFIGURATION_H_ */ ================================================ FILE: source/Core/BSP/Miniware/flash.c ================================================ /* * flash.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "BSP_Flash.h" #include "stm32f1xx_hal.h" #include "string.h" void flash_save_buffer(const uint8_t *buffer, const uint16_t length) { FLASH_EraseInitTypeDef pEraseInit; pEraseInit.TypeErase = FLASH_TYPEERASE_PAGES; pEraseInit.Banks = FLASH_BANK_1; pEraseInit.NbPages = 1; pEraseInit.PageAddress = (uint32_t)SETTINGS_START_PAGE; uint32_t failingAddress = 0; resetWatchdog(); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY); HAL_FLASH_Unlock(); HAL_Delay(1); resetWatchdog(); HAL_FLASHEx_Erase(&pEraseInit, &failingAddress); //^ Erase the page of flash (1024 bytes on this stm32) // erased the chunk // now we program it uint16_t *data = (uint16_t *)buffer; HAL_FLASH_Unlock(); for (uint16_t i = 0; i < (length / 2); i++) { resetWatchdog(); HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, SETTINGS_START_PAGE + (i * sizeof(uint16_t)), data[i]); } HAL_FLASH_Lock(); } void flash_read_buffer(uint8_t *buffer, const uint16_t length) { memcpy(buffer, (uint8_t *)SETTINGS_START_PAGE, length); } ================================================ FILE: source/Core/BSP/Miniware/fusb_user.cpp ================================================ #include "configuration.h" #ifdef POW_PD #include "BSP.h" #include "I2CBB2.hpp" #include "Setup.h" bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return I2CBB2::Mem_Read(deviceAddr, registerAdd, buf, size); } bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return I2CBB2::Mem_Write(deviceAddr, registerAdd, buf, size); } void setupFUSBIRQ() { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pin = INT_PD_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(INT_PD_GPIO_Port, &GPIO_InitStruct); HAL_NVIC_SetPriority(EXTI9_5_IRQn, 10, 0); HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); } #endif ================================================ FILE: source/Core/BSP/Miniware/port.c ================================================ /* * FreeRTOS Kernel V10.3.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ /*----------------------------------------------------------- * Implementation of functions defined in portable.h for the ARM CM3 port. *----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is defined. The value should also ensure backward compatibility. FreeRTOS.org versions prior to V4.4.0 did not include this definition. */ #ifndef configKERNEL_INTERRUPT_PRIORITY #define configKERNEL_INTERRUPT_PRIORITY 255 #endif #ifndef configSYSTICK_CLOCK_HZ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ /* Ensure the SysTick is clocked at the same frequency as the core. */ #define portNVIC_SYSTICK_CLK_BIT (1UL << 2UL) #else /* The way the SysTick is clocked is not modified in case it is not the same as the core. */ #define portNVIC_SYSTICK_CLK_BIT (0) #endif /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) #define portNVIC_SYSTICK_LOAD_REG (*((volatile uint32_t *)0xe000e014)) #define portNVIC_SYSTICK_CURRENT_VALUE_REG (*((volatile uint32_t *)0xe000e018)) #define portNVIC_SYSPRI2_REG (*((volatile uint32_t *)0xe000ed20)) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_INT_BIT (1UL << 1UL) #define portNVIC_SYSTICK_ENABLE_BIT (1UL << 0UL) #define portNVIC_SYSTICK_COUNT_FLAG_BIT (1UL << 16UL) #define portNVIC_PENDSVCLEAR_BIT (1UL << 27UL) #define portNVIC_PEND_SYSTICK_CLEAR_BIT (1UL << 25UL) #define portNVIC_PENDSV_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 16UL) #define portNVIC_SYSTICK_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 24UL) /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER (16) #define portNVIC_IP_REGISTERS_OFFSET_16 (0xE000E3F0) #define portAIRCR_REG (*((volatile uint32_t *)0xE000ED0C)) #define portMAX_8_BIT_VALUE ((uint8_t)0xff) #define portTOP_BIT_OF_BYTE ((uint8_t)0x80) #define portMAX_PRIGROUP_BITS ((uint8_t)7) #define portPRIORITY_GROUP_MASK (0x07UL << 8UL) #define portPRIGROUP_SHIFT (8UL) /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ #define portVECTACTIVE_MASK (0xFFUL) /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR (0x01000000UL) /* The systick is a 24-bit counter. */ #define portMAX_24_BIT_NUMBER (0xffffffUL) /* A fiddle factor to estimate the number of SysTick counts that would have occurred while the SysTick counter is stopped during tickless idle calculations. */ #define portMISSED_COUNTS_FACTOR (45UL) /* For strict compliance with the Cortex-M spec the task start address should have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ #define portSTART_ADDRESS_MASK ((StackType_t)0xfffffffeUL) /* Let the user override the pre-loading of the initial LR with the address of prvTaskExitError() in case it messes up unwinding of the stack in the debugger. */ #ifdef configTASK_RETURN_ADDRESS #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /* * Setup the timer to generate the tick interrupts. The implementation in this * file is weak to allow application writers to change the timer used to * generate the tick interrupt. */ void vPortSetupTimerInterrupt(void); /* * Exception handlers. */ void xPortPendSVHandler(void) __attribute__((naked)); void xPortSysTickHandler(void); void vPortSVCHandler(void) __attribute__((naked)); /* * Start first task is a separate function so it can be tested in isolation. */ static void prvPortStartFirstTask(void) __attribute__((naked)); /* * Used to catch tasks that attempt to return from their implementing function. */ static void prvTaskExitError(void); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting variable. */ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; /* * The number of SysTick increments that make up one tick period. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t ulTimerCountsForOneTick = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * The maximum number of tick periods that can be suppressed is limited by the * 24 bit resolution of the SysTick timer. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t xMaximumPossibleSuppressedTicks = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Compensate for the CPU cycles that pass while the SysTick is stopped (low * power functionality only. */ #if (configUSE_TICKLESS_IDLE == 1) static uint32_t ulStoppedTimerCompensation = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ #if (configASSERT_DEFINED == 1) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const)portNVIC_IP_REGISTERS_OFFSET_16; #endif /* configASSERT_DEFINED */ /*-----------------------------------------------------------*/ /* * See header file for description. */ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) { /* Simulate the stack frame as it would be created by a context switch interrupt. */ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ pxTopOfStack--; *pxTopOfStack = ((StackType_t)pxCode) & portSTART_ADDRESS_MASK; /* PC */ pxTopOfStack--; *pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* LR */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ *pxTopOfStack = (StackType_t)pvParameters; /* R0 */ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ return pxTopOfStack; } /*-----------------------------------------------------------*/ static void prvTaskExitError(void) { // volatile uint32_t ulDummy = 0UL; // /* A function that implements a task must not exit or attempt to return to // its caller as there is nothing to return to. If a task wants to exit it // should instead call vTaskDelete( NULL ). // Artificially force an assert() to be triggered if configASSERT() is // defined, then stop here so application writers can catch the error. */ // configASSERT(uxCriticalNesting == ~0UL); // portDISABLE_INTERRUPTS(); // while (ulDummy == 0) { // /* This file calls prvTaskExitError() after the scheduler has been // started to remove a compiler warning about the function being defined // but never called. ulDummy is used purely to quieten other warnings // about code appearing after this function is called - making ulDummy // volatile makes the compiler think the function could return and // therefore not output an 'unreachable code' warning for code that appears // after it. */ // } for (;;) { } } /*-----------------------------------------------------------*/ void vPortSVCHandler(void) { __asm volatile(" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ " msr psp, r0 \n" /* Restore the task stack pointer. */ " isb \n" " mov r0, #0 \n" " msr basepri, r0 \n" " orr r14, #0xd \n" " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n"); } /*-----------------------------------------------------------*/ static void prvPortStartFirstTask(void) { __asm volatile(" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ " ldr r0, [r0] \n" " ldr r0, [r0] \n" " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " cpsie i \n" /* Globally enable interrupts. */ " cpsie f \n" " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n"); } /*-----------------------------------------------------------*/ /* * See header file for description. */ BaseType_t xPortStartScheduler(void) { /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY); #if (configASSERT_DEFINED == 1) { volatile uint32_t ulOriginalPriority; volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER); volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) { ulMaxPRIGROUPValue--; ucMaxPriorityValue <<= (uint8_t)0x01; } #ifdef __NVIC_PRIO_BITS { /* Check the CMSIS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS); } #endif #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS); } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; /* Start the first task. */ prvPortStartFirstTask(); /* Should never get here as the tasks will now be executing! Call the task exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); prvTaskExitError(); /* Should not get here! */ return 0; } /*-----------------------------------------------------------*/ void vPortEndScheduler(void) { /* Not implemented in ports where there is nothing to return to. Artificially force an assert. */ configASSERT(uxCriticalNesting == 1000UL); } /*-----------------------------------------------------------*/ void vPortEnterCritical(void) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if (uxCriticalNesting == 1) { configASSERT((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0); } } /*-----------------------------------------------------------*/ void vPortExitCritical(void) { configASSERT(uxCriticalNesting); uxCriticalNesting--; if (uxCriticalNesting == 0) { portENABLE_INTERRUPTS(); } } /*-----------------------------------------------------------*/ void xPortPendSVHandler(void) { /* This is a naked function. */ __asm volatile(" mrs r0, psp \n" " isb \n" " \n" " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ " ldr r2, [r3] \n" " \n" " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ " \n" " stmdb sp!, {r3, r14} \n" " mov r0, %0 \n" " msr basepri, r0 \n" " bl vTaskSwitchContext \n" " mov r0, #0 \n" " msr basepri, r0 \n" " ldmia sp!, {r3, r14} \n" " \n" /* Restore the context, including the critical nesting count. */ " ldr r1, [r3] \n" " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ " msr psp, r0 \n" " isb \n" " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)); } /*-----------------------------------------------------------*/ void xPortSysTickHandler(void) { /* The SysTick runs at the lowest interrupt priority, so when this interrupt executes all interrupts must be unmasked. There is therefore no need to save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if (xTaskIncrementTick() != pdFALSE) { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } } portENABLE_INTERRUPTS(); } /*-----------------------------------------------------------*/ #if (configUSE_TICKLESS_IDLE == 1) __attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; TickType_t xModifiableIdleTime; /* Make sure the SysTick reload value does not overflow the counter. */ if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) { xExpectedIdleTime = xMaximumPossibleSuppressedTicks; } /* Stop the SysTick momentarily. The time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time. */ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; /* Calculate the reload value required to wait xExpectedIdleTime tick periods. -1 is used because this code will execute part way through one of the tick periods. */ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL)); if (ulReloadValue > ulStoppedTimerCompensation) { ulReloadValue -= ulStoppedTimerCompensation; } /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ __asm volatile("cpsid i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* If a context switch is pending or a task is waiting for the scheduler to be unsuspended then abandon the low power entry. */ if (eTaskConfirmSleepModeStatus() == eAbortSleep) { /* Restart from whatever is left in the count register to complete this tick period. */ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; /* Restart SysTick. */ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; /* Reset the reload register to the value required for normal tick periods. */ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; /* Re-enable interrupts - see comments above the cpsid instruction() above. */ __asm volatile("cpsie i" ::: "memory"); } else { /* Set the new reload value. */ portNVIC_SYSTICK_LOAD_REG = ulReloadValue; /* Clear the SysTick count flag and set the count value back to zero. */ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Restart SysTick. */ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can set its parameter to 0 to indicate that its implementation contains its own wait for interrupt or wait for event instruction, and so wfi should not be executed again. However, the original expected idle time variable must remain unmodified, so a copy is taken. */ xModifiableIdleTime = xExpectedIdleTime; configPRE_SLEEP_PROCESSING(xModifiableIdleTime); if (xModifiableIdleTime > 0) { __asm volatile("dsb" ::: "memory"); __asm volatile("wfi"); __asm volatile("isb"); } configPOST_SLEEP_PROCESSING(xExpectedIdleTime); /* Re-enable interrupts to allow the interrupt that brought the MCU out of sleep mode to execute immediately. see comments above __disable_interrupt() call above. */ __asm volatile("cpsie i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* Disable interrupts again because the clock is about to be stopped and interrupts that execute while the clock is stopped will increase any slippage between the time maintained by the RTOS and calendar time. */ __asm volatile("cpsid i" ::: "memory"); __asm volatile("dsb"); __asm volatile("isb"); /* Disable the SysTick clock without reading the portNVIC_SYSTICK_CTRL_REG register to ensure the portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, the time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time*/ portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT); /* Determine if the SysTick clock has already counted to zero and been set back to the current reload value (the reload back being correct for the entire expected idle time) or if the SysTick is yet to count to zero (in which case an interrupt other than the SysTick must have brought the system out of sleep mode). */ if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) { uint32_t ulCalculatedLoadValue; /* The tick interrupt is already pending, and the SysTick count reloaded with ulReloadValue. Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick period. */ ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL) - (ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG); /* Don't allow a tiny value, or values that have somehow underflowed because the post sleep hook did something that took too long. */ if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) { ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL); } portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; /* As the pending tick will be processed as soon as this function exits, the tick value maintained by the tick is stepped forward by one less than the time spent waiting. */ ulCompleteTickPeriods = xExpectedIdleTime - 1UL; } else { /* Something other than the tick interrupt ended the sleep. Work out how long the sleep lasted rounded to complete tick periods (not the ulReload value which accounted for part ticks). */ ulCompletedSysTickDecrements = (xExpectedIdleTime * ulTimerCountsForOneTick) - portNVIC_SYSTICK_CURRENT_VALUE_REG; /* How many complete tick periods passed while the processor was waiting? */ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; /* The reload value is set to whatever fraction of a single tick period remains. */ portNVIC_SYSTICK_LOAD_REG = ((ulCompleteTickPeriods + 1UL) * ulTimerCountsForOneTick) - ulCompletedSysTickDecrements; } /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, then set portNVIC_SYSTICK_LOAD_REG back to its standard value. */ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; vTaskStepTick(ulCompleteTickPeriods); portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; /* Exit with interrupts enabled. */ __asm volatile("cpsie i" ::: "memory"); } } #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__((weak)) void vPortSetupTimerInterrupt(void) { /* Calculate the constants required to configure the tick interrupt. */ #if (configUSE_TICKLESS_IDLE == 1) { ulTimerCountsForOneTick = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ); xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL; portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT); } /*-----------------------------------------------------------*/ #if (configASSERT_DEFINED == 1) void vPortValidateInterruptPriority(void) { uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); /* Is the interrupt number a user defined interrupt? */ if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ulCurrentInterrupt]; /* The following assertion will fail if a service routine (ISR) for an interrupt that has been assigned a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API function. ISR safe FreeRTOS API functions must *only* be called from interrupts that have been assigned a priority at or below configMAX_SYSCALL_INTERRUPT_PRIORITY. Numerically low interrupt priority numbers represent logically high interrupt priorities, therefore the priority of the interrupt must be set to a value equal to or numerically *higher* than configMAX_SYSCALL_INTERRUPT_PRIORITY. Interrupts that use the FreeRTOS API must not be left at their default priority of zero as that is the highest possible priority, which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, and therefore also guaranteed to be invalid. FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT(ucCurrentPriority >= ucMaxSysCallPriority); } /* Priority grouping: The interrupt controller (NVIC) allows the bits that define each interrupt's priority to be split between bits that define the interrupt's pre-emption priority bits and bits that define the interrupt's sub-priority. For simplicity all bits must be defined to be pre-emption priority bits. The following assertion will fail if this is not the case (if some bits represent a sub-priority). If the application only uses CMSIS libraries for interrupt configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue); } #endif /* configASSERT_DEFINED */ ================================================ FILE: source/Core/BSP/Miniware/portmacro.h ================================================ /* * FreeRTOS Kernel V10.3.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ #ifndef PORTMACRO_H #define PORTMACRO_H #include "FreeRTOSConfig.h" #include "projdefs.h" #ifdef __cplusplus extern "C" { #endif /*----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. *----------------------------------------------------------- */ /* Type definitions. */ #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE uint32_t #define portBASE_TYPE long typedef portSTACK_TYPE StackType_t; typedef long BaseType_t; typedef unsigned long UBaseType_t; #if (configUSE_16_BIT_TICKS == 1) typedef uint16_t TickType_t; #define portMAX_DELAY (TickType_t)0xffff #else typedef uint32_t TickType_t; #define portMAX_DELAY (TickType_t)0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ #define portSTACK_GROWTH (-1) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) #define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Scheduler utilities. */ #define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ __asm volatile("dsb" ::: "memory"); \ __asm volatile("isb"); \ } #define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04)) #define portNVIC_PENDSVSET_BIT (1UL << 28UL) #define portEND_SWITCHING_ISR(xSwitchRequired) \ if (xSwitchRequired != pdFALSE) \ portYIELD() #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) /*-----------------------------------------------------------*/ /* Critical section management. */ extern void vPortEnterCritical(void); extern void vPortExitCritical(void); #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() #define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are not necessary for to use this port. They are defined so the common demo files (which build with all the ports) will build. */ #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime) #endif /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Generic helper function. */ __attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) { uint8_t ucReturn; __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory"); return ucReturn; } /* Check the configuration. */ #if (configMAX_PRIORITIES > 32) #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. #endif /* Store/clear the ready priorities in a bit map. */ #define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority)) #define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) &= ~(1UL << (uxPriority)) /*-----------------------------------------------------------*/ #define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities))) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ #ifdef configASSERT void vPortValidateInterruptPriority(void); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* portNOP() is not required by this port. */ #define portNOP() #define portINLINE __inline #ifndef portFORCE_INLINE #define portFORCE_INLINE inline __attribute__((always_inline)) #endif /*-----------------------------------------------------------*/ portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) { uint32_t ulCurrentInterrupt; BaseType_t xReturn; /* Obtain the number of the currently executing interrupt. */ __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); if (ulCurrentInterrupt == 0) { xReturn = pdFALSE; } else { xReturn = pdTRUE; } return xReturn; } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortRaiseBASEPRI(void) { uint32_t ulNewBASEPRI; __asm volatile(" mov %0, %1 \n" " msr basepri, %0 \n" " isb \n" " dsb \n" : "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory"); } /*-----------------------------------------------------------*/ portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile(" mrs %0, basepri \n" " mov %1, %2 \n" " msr basepri, %1 \n" " isb \n" " dsb \n" : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory"); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile(" msr basepri, %0 " ::"r"(ulNewMaskValue) : "memory"); } /*-----------------------------------------------------------*/ #define portMEMORY_BARRIER() __asm volatile("" ::: "memory") #ifdef __cplusplus } #endif #endif /* PORTMACRO_H */ ================================================ FILE: source/Core/BSP/Miniware/postRTOS.cpp ================================================ #include "BSP.h" // Initialisation to be performed with scheduler active void postRToSInit() {} ================================================ FILE: source/Core/BSP/Miniware/preRTOS.cpp ================================================ /* * preRTOS.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "I2CBB1.hpp" #include "I2CBB2.hpp" #include "Pins.h" #include "Setup.h" #include "configuration.h" #include void preRToSInit() { /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); Setup_HAL(); // Setup all the HAL objects BSPInit(); #ifdef I2C_SOFT_BUS_2 I2CBB2::init(); #endif #ifdef I2C_SOFT_BUS_1 I2CBB1::init(); #endif } ================================================ FILE: source/Core/BSP/Miniware/stm32f103.ld ================================================ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20005000; /* end of RAM */ _Min_Heap_Size = 0x300; /* required amount of heap */ _Min_Stack_Size = 1024; /* required amount of stack */ __APP_BASE_ADDRESS__ = 0x08000000 + __BOOTLDR_SIZE__; __ROM_REGION_LENGTH__ = __FLASH_SIZE__ - __BOOTLDR_SIZE__; __FLASH_END_ADDR__ = __APP_BASE_ADDRESS__ + __ROM_REGION_LENGTH__; /* Memories definition */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K ROM (rx) : ORIGIN = __APP_BASE_ADDRESS__, LENGTH = __ROM_REGION_LENGTH__ } /* ROM is normally 48K after the bootloader, however we allocate the last page for settings, and the second last one for display boot logo*/ /* Sections */ SECTIONS { /* The startup code into ROM memory */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >ROM /* The program code and other data into ROM memory */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >ROM /* Constant data into ROM memory*/ .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >ROM .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >ROM .ARM : { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); } >ROM .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >ROM .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >ROM .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); } >ROM /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into RAM memory */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> ROM .bss : { /* Uninitialized data section into RAM memory */ . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM /* Remove information from the compiler libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: source/Core/BSP/Miniware/stm32f1xx_hal_msp.c ================================================ #include "Pins.h" #include "Setup.h" #include "stm32f1xx_hal.h" /** * Initializes the Global MSP. */ void HAL_MspInit(void) { __HAL_RCC_AFIO_CLK_ENABLE(); // HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* System interrupt init*/ /* MemoryManagement_IRQn interrupt configuration */ HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); /* BusFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); /* UsageFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); /* SVCall_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); /* DebugMonitor_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); } void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { GPIO_InitTypeDef GPIO_InitStruct; if (hadc->Instance == ADC1) { __HAL_RCC_ADC1_CLK_ENABLE(); /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; HAL_DMA_Init(&hdma_adc1); __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1); /* ADC1 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0); HAL_NVIC_EnableIRQ(ADC1_2_IRQn); } else { __HAL_RCC_ADC2_CLK_ENABLE(); /**ADC2 GPIO Configuration PB0 ------> ADC2_IN8 PB1 ------> ADC2_IN9 */ GPIO_InitStruct.Pin = TIP_TEMP_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = TMP36_INPUT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct); GPIO_InitStruct.Pin = VIN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct); #ifdef PD_VIN_Pin GPIO_InitStruct.Pin = PD_VIN_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(PD_VIN_GPIO_Port, &GPIO_InitStruct); #endif /* ADC2 interrupt Init */ HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0); HAL_NVIC_EnableIRQ(ADC1_2_IRQn); } } void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) { if (htim_base->Instance == TIM3) { /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); } else if (htim_base->Instance == TIM2) { /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); } else if (htim_base->Instance == TIM4) { /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); } } ================================================ FILE: source/Core/BSP/Miniware/stm32f1xx_hal_timebase_TIM.c ================================================ /** ****************************************************************************** * @file stm32f1xx_hal_timebase_TIM.c * @brief HAL time base based on the hardware TIM. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and * USER CODE END. Other portions of this file, whether * inserted by the user or by software development tools * are owned by their respective copyright owners. * * Copyright (c) 2017 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted, provided that the following conditions are met: * * 1. Redistribution of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of other * contributors to this software may be used to endorse or promote products * derived from this software without specific written permission. * 4. This software, including modifications and/or derivative works of this * software, must execute solely and exclusively on microcontroller or * microprocessor devices manufactured by or for STMicroelectronics. * 5. Redistribution and use of this software other than as permitted under * this license is void and will automatically terminate your rights under * this license. * * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" #include "stm32f1xx_hal_tim.h" /** @addtogroup STM32F7xx_HAL_Examples * @{ */ /** @addtogroup HAL_TimeBase * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ TIM_HandleTypeDef htim1; uint32_t uwIncrementState = 0; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** * @brief This function configures the TIM1 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priorty. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; uint32_t uwPrescalerValue = 0; uint32_t pFLatency; /*Configure the TIM1 IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority, 0); /* Enable the TIM1 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); /* Enable TIM1 clock */ __HAL_RCC_TIM1_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); /* Compute TIM1 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000) - 1); /* Initialize TIM1 */ htim1.Instance = TIM1; /* Initialize TIMx peripheral as follow: + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim1.Init.Period = (1000000 / 1000) - 1; htim1.Init.Prescaler = uwPrescalerValue; htim1.Init.ClockDivision = 0; htim1.Init.CounterMode = TIM_COUNTERMODE_UP; if (HAL_TIM_Base_Init(&htim1) == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim1); } /* Return function status */ return HAL_ERROR; } /** * @brief Suspend Tick increment. * @note Disable the tick increment by disabling TIM1 update interrupt. * @param None * @retval None */ void HAL_SuspendTick(void) { /* Disable TIM1 update Interrupt */ __HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. * @note Enable the tick increment by Enabling TIM1 update interrupt. * @param None * @retval None */ void HAL_ResumeTick(void) { /* Enable TIM1 Update interrupt */ __HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE); } /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Miniware/stm32f1xx_it.c ================================================ // This is the stock standard STM interrupt file full of handlers #include "stm32f1xx_it.h" #include "Pins.h" #include "Setup.h" #include "cmsis_os.h" #include "stm32f1xx.h" #include "stm32f1xx_hal.h" extern TIM_HandleTypeDef htim1; // used for the systick /******************************************************************************/ /* Cortex-M3 Processor Interruption and Exception Handlers */ /******************************************************************************/ // Systick is used by FreeRTOS tick void SysTick_Handler(void) { osSystickHandler(); } /******************************************************************************/ /* STM32F1xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ /* For the available peripheral interrupt handler names, */ /* please refer to the startup file. */ /******************************************************************************/ // DMA used to move the ADC readings into system ram void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); } // ADC interrupt used for DMA void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); } // Timer 1 has overflowed, used for HAL ticks void TIM1_UP_IRQHandler(void) { HAL_TIM_IRQHandler(&htim1); } // Timer 3 is used for the PWM output to the tip void TIM3_IRQHandler(void) { TIM_HandleTypeDef *handle = &htimADC; if (htimTip.Instance == TIM3) { handle = &htimTip; } HAL_TIM_IRQHandler(handle); } // Timer 2 is used for co-ordination of PWM & ADC void TIM2_IRQHandler(void) { TIM_HandleTypeDef *handle = &htimADC; if (htimTip.Instance == TIM2) { handle = &htimTip; } HAL_TIM_IRQHandler(handle); } // Timer 2 is used for co-ordination of PWM & ADC void TIM4_IRQHandler(void) { TIM_HandleTypeDef *handle = &htimADC; if (htimTip.Instance == TIM4) { handle = &htimTip; } HAL_TIM_IRQHandler(handle); } void EXTI9_5_IRQHandler(void) { #ifdef INT_PD_Pin HAL_GPIO_EXTI_IRQHandler(INT_PD_Pin); #endif } ================================================ FILE: source/Core/BSP/Miniware/system_stm32f1xx.c ================================================ // This file was automatically generated by the STM Cube software // And as such, is BSD licneced from STM #include "stm32f1xx.h" #if !defined(HSI_VALUE) #define HSI_VALUE \ 8000000U /*!< Default value of the Internal oscillator in Hz. \ This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ /*!< Uncomment the following line if you need to use external SRAM */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #ifndef VECT_TAB_OFFSET #error VECT_TAB_OFFSET #endif /******************************************************************************* * Clock Definitions *******************************************************************************/ #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */ #endif const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit(void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; #if defined(STM32F105xC) || defined(STM32F107xC) /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= 0xEBFFFFFFU; /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x00FF0000U; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * 8 MHz or 25 MHz, depending on the product used), user has to ensure * that HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; #endif /* STM32F105xC */ #if defined(STM32F100xB) || defined(STM32F100xE) uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if !defined(STM32F105xC) && !defined(STM32F107xC) pllmull = (pllmull >> 18U) + 2U; if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { #if defined(STM32F100xB) || defined(STM32F100xE) prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */ SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; } else { SystemCoreClock = HSE_VALUE * pllmull; } #endif } #else pllmull = pllmull >> 18U; if (pllmull != 0x0DU) { pllmull += 2U; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ pllmull = 13U / 2U; } if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { /* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; if (prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; } else { /* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F105xC */ break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) /** * @brief Setup the external memory controller. Called in startup_stm32f1xx.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f1xx_xx.s/.c before jump to main. * This function configures the external SRAM mounted on STM3210E-EVAL * board (STM32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { __IO uint32_t tmpreg; /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is required, then adjust the Register Addresses */ /* Enable FSMC clock */ RCC->AHBENR = 0x00000114U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ RCC->APB2ENR = 0x000001E0U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); (void)(tmpreg); /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ GPIOD->CRL = 0x44BB44BBU; GPIOD->CRH = 0xBBBBBBBBU; GPIOE->CRL = 0xB44444BBU; GPIOE->CRH = 0xBBBBBBBBU; GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRH = 0xBBBB4444U; GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRH = 0x444B4B44U; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[5U] = 0x00110212U; } #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: source/Core/BSP/Pinecil/BSP.cpp ================================================ // BSP mapping functions #include "BSP.h" #include "BootLogo.h" #include "I2C_Wrapper.hpp" #include "IRQ.h" #include "Pins.h" #include "Settings.h" #include "Setup.h" #include "TipThermoModel.h" #include "configuration.h" #include "gd32vf103_timer.h" #include "history.hpp" #include "main.hpp" const uint16_t powerPWM = 255; const uint8_t holdoffTicks = 10; const uint8_t tempMeasureTicks = 14; uint16_t totalPWM; // Total length of the cycle's ticks void resetWatchdog() { fwdgt_counter_reload(); } uint16_t getHandleTemperature(uint8_t sample) { #ifdef TEMP_TMP36 // We return the current handle temperature in X10 C // TMP36 in handle, 0.5V offset and then 10mV per deg C (0.75V @ 25C for // example) STM32 = 4096 count @ 3.3V input -> But We oversample by 32/(2^2) = // 8 times oversampling Therefore 32768 is the 3.3V input, so 0.1007080078125 // mV per count So we need to subtract an offset of 0.5V to center on 0C // (4964.8 counts) // int32_t result = getADCHandleTemp(sample); result -= 4965; // remove 0.5V offset // 10mV per C // 99.29 counts per Deg C above 0C result *= 100; result /= 993; return result; #else #error Pinecil only uses TMP36 #endif } uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { uint32_t res = getADCVin(sample); res *= 4; res /= divisor; return res; } void unstick_I2C() { /* configure SDA/SCL for GPIO */ GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin; gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); for (int i = 0; i < 8; i++) { asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); GPIO_BOP(GPIOB) |= SCL_Pin; asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); GPIO_BOP(GPIOB) &= SCL_Pin; } /* connect PB6 to I2C0_SCL */ /* connect PB7 to I2C0_SDA */ gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); } uint8_t getButtonA() { return (gpio_input_bit_get(KEY_A_GPIO_Port, KEY_A_Pin) == SET) ? 1 : 0; } uint8_t getButtonB() { return (gpio_input_bit_get(KEY_B_GPIO_Port, KEY_B_Pin) == SET) ? 1 : 0; } void reboot() { eclic_system_reset(); } void delay_ms(uint16_t count) { delay_1ms(count); } uint32_t __get_IPSR(void) { return 0; // To shut-up CMSIS } bool isTipDisconnected() { uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5; uint32_t tipTemp = TipThermoModel::getTipInC(); return tipTemp > tipDisconnectedThres; } void setStatusLED(const enum StatusLED state) {} void setBuzzer(bool on) {} uint8_t preStartChecks() { return 1; } uint64_t getDeviceID() { return dbg_id_get(); } uint8_t getTipResistanceX10() { uint8_t user_selected_tip = getUserSelectedTipResistance(); if (user_selected_tip == 0) { return TIP_RESISTANCE; // Auto mode } return user_selected_tip; } bool isTipShorted() { return false; } uint8_t preStartChecksDone() { return 1; } uint16_t getTipThermalMass() { return TIP_THERMAL_MASS; } uint16_t getTipInertia() { return TIP_THERMAL_MASS; } void showBootLogo(void) { BootLogo::handleShowingLogo((uint8_t *)FLASH_LOGOADDR); } ================================================ FILE: source/Core/BSP/Pinecil/Debug.cpp ================================================ /* * Debug.cpp * * Created on: 26 Jan. 2021 * Author: Ralim */ #include "Debug.h" #include "FreeRTOS.h" #include "Pins.h" extern "C" { #include "gd32vf103_usart.h" } char uartOutputBuffer[uartOutputBufferLength]; volatile uint32_t currentOutputPos = 0xFF; volatile uint32_t outputLength = 0; extern volatile uint8_t pendingPWM; void log_system_state(int32_t PWMWattsx10) { if (currentOutputPos == 0xFF) { // Want to print a CSV log out the uart // Tip_Temp_C,Handle_Temp_C,Output_Power_Wattx10,PWM,Tip_Raw\r\n // 3+1+3+1+3+1+3+1+5+2 = 23, so sizing at 32 for now outputLength = snprintf(uartOutputBuffer, uartOutputBufferLength, "%lu,%u,%li,%u,%lu\r\n", TipThermoModel::getTipInC(false), // Tip temp in C getHandleTemperature(0), // Handle temp in C X10 PWMWattsx10, // Output Wattage pendingPWM, // PWM TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true) // Tip temp in uV ); // Now print this out the uart via IRQ (DMA cant be used as oled has it) currentOutputPos = 0; /* enable USART1 Transmit Buffer Empty interrupt */ usart_interrupt_enable(UART_PERIF, USART_INT_TBE); } } ssize_t _write(int fd, const void *ptr, size_t len) { if (len > uartOutputBufferLength) { len = uartOutputBufferLength; } outputLength = len; currentOutputPos = 0; memcpy(uartOutputBuffer, ptr, len); /* enable USART1 Transmit Buffer Empty interrupt */ usart_interrupt_enable(UART_PERIF, USART_INT_TBE); delay_ms(1); return len; } void USART1_IRQHandler(void) { if (RESET != usart_interrupt_flag_get(UART_PERIF, USART_INT_FLAG_TBE)) { /* write one byte to the transmit data register */ usart_data_transmit(UART_PERIF, uartOutputBuffer[currentOutputPos++]); if (currentOutputPos >= outputLength) { currentOutputPos = 0xFF; // Mark done usart_interrupt_disable(UART_PERIF, USART_INT_TBE); } } } ================================================ FILE: source/Core/BSP/Pinecil/Debug.h ================================================ /* * Debug.h * * Created on: 26 Jan. 2021 * Author: Ralim */ #ifndef CORE_BSP_PINE64_DEBUG_H_ #define CORE_BSP_PINE64_DEBUG_H_ #include "BSP.h" #include "TipThermoModel.h" #include #include const unsigned int uartOutputBufferLength = 32; extern char uartOutputBuffer[uartOutputBufferLength]; extern "C" { ssize_t _write(int fd, const void *ptr, size_t len); void USART1_IRQHandler(void); } #endif /* CORE_BSP_PINE64_DEBUG_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/FreeRTOSConfig.h ================================================ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H #include "nuclei_sdk_soc.h" #include #define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 #define configUSE_TICKLESS_IDLE 0 #define configCPU_CLOCK_HZ ((uint32_t)SystemCoreClock) #define configRTC_CLOCK_HZ ((uint32_t)32768) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) #define configMAX_TASK_NAME_LEN 24 #define configIDLE_SHOULD_YIELD 0 #define configUSE_TASK_NOTIFICATIONS 1 #define configUSE_MUTEXES 1 #define configUSE_RECURSIVE_MUTEXES 0 #define configUSE_COUNTING_SEMAPHORES 0 #define configQUEUE_REGISTRY_SIZE 10 #define configUSE_QUEUE_SETS 0 #define configUSE_TIME_SLICING 1 #define configUSE_NEWLIB_REENTRANT 0 #define configENABLE_BACKWARD_COMPATIBILITY 0 #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS #define INCLUDE_uxTaskGetStackHighWaterMark 1 #define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_vTaskDelay 1 /* Memory allocation related definitions. */ #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 0 #define configTOTAL_HEAP_SIZE 1024 #define configAPPLICATION_ALLOCATED_HEAP 0 /* Hook function related definitions. */ #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 0 #define configCHECK_FOR_STACK_OVERFLOW 1 #define configUSE_MALLOC_FAILED_HOOK 0 #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 /* Run time and task stats gathering related definitions. */ #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_TRACE_FACILITY 0 #define configUSE_STATS_FORMATTING_FUNCTIONS 0 /* Co-routine related definitions. */ #define configUSE_CO_ROUTINES 0 #define configMAX_CO_ROUTINE_PRIORITIES 1 /* Software timer related definitions. */ #define configUSE_TIMERS 0 #define configTIMER_TASK_PRIORITY 3 #define configTIMER_QUEUE_LENGTH 5 #define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE /* Interrupt nesting behaviour configuration. */ #define configPRIO_BITS (4UL) #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x1 #define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0xe #define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) #define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) /* Define to trap errors during development. */ #define configASSERT(x) \ if ((x) == 0) { \ taskDISABLE_INTERRUPTS(); \ for (;;) \ ; \ } #define INCLUDE_vTaskPrioritySet 1 #define INCLUDE_uxTaskPriorityGet 1 #define INCLUDE_vTaskDelete 1 #define INCLUDE_vTaskSuspend 1 #define INCLUDE_xResumeFromISR 1 #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1 #define INCLUDE_xTaskGetIdleTaskHandle 1 #define INCLUDE_eTaskGetState 0 #define INCLUDE_xEventGroupSetBitFromISR 1 #define INCLUDE_xTimerPendFunctionCall 0 #define INCLUDE_xTaskAbortDelay 0 #define INCLUDE_xTaskGetHandle 1 #define INCLUDE_xTaskResumeFromISR 1 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #endif /* FREERTOS_CONFIG_H */ ================================================ FILE: source/Core/BSP/Pinecil/I2C_Wrapper.cpp ================================================ /* * FRToSI2C.cpp * * Created on: 14Apr.,2018 * Author: Ralim */ #include "BSP.h" #include "IRQ.h" #include "Setup.h" #include SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr; StaticSemaphore_t FRToSI2C::xSemaphoreBuffer; #define I2C_TIME_OUT (uint16_t)(12000) void FRToSI2C::CpltCallback() { // TODO } bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); } uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) { uint8_t temp = 0; Mem_Read(add, reg, &temp, 1); return temp; } enum class i2c_step { // Write+read steps Write_start, // Sending start on bus Write_device_address, // start sent, send device address Write_device_memory_address, // device address sent, write the memory location Write_device_data_start, // Write all of the remaining data using DMA Write_device_data_finish, // Write all of the remaining data using DMA Read_start, // second read Read_device_address, // Send device address again for the read Read_device_data_start, // read device data via DMA Read_device_data_finish, // read device data via DMA Send_stop, // send the stop at the end of the transaction Wait_stop, // Wait for stop to send and we are done Done, // Finished Error_occured, // Error occured on the bus }; struct i2c_state { i2c_step currentStep; bool isMemoryWrite; bool wakePart; uint8_t deviceAddress; uint8_t memoryAddress; uint8_t *buffer; uint16_t numberOfBytes; dma_parameter_struct dma_init_struct; }; i2c_state currentState; void perform_i2c_step() { // Performs next step of the i2c state machine if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { i2c_flag_clear(I2C0, I2C_FLAG_AERR); // Arb error - we lost the bus / nacked currentState.currentStep = i2c_step::Error_occured; } switch (currentState.currentStep) { case i2c_step::Error_occured: i2c_stop_on_bus(I2C0); break; case i2c_step::Write_start: /* enable acknowledge */ i2c_ack_config(I2C0, I2C_ACK_ENABLE); /* i2c master sends start signal only when the bus is idle */ if (!i2c_flag_get(I2C0, I2C_FLAG_I2CBSY)) { /* send the start signal */ i2c_start_on_bus(I2C0); currentState.currentStep = i2c_step::Write_device_address; } break; case i2c_step::Write_device_address: /* i2c master sends START signal successfully */ if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) { i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); // Clear sbsend by reading ctrl banks i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_TRANSMITTER); currentState.currentStep = i2c_step::Write_device_memory_address; } break; case i2c_step::Write_device_memory_address: // Send the device memory location if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { // addr sent i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); if (currentState.wakePart) { // We are stopping here currentState.currentStep = i2c_step::Send_stop; return; } i2c_flag_clear(I2C0, I2C_FLAG_BTC); // Write out the 8 byte address i2c_data_transmit(I2C0, currentState.memoryAddress); if (currentState.isMemoryWrite) { currentState.currentStep = i2c_step::Write_device_data_start; } else { currentState.currentStep = i2c_step::Read_start; } } break; case i2c_step::Write_device_data_start: /* wait until the transmission data register is empty */ if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) { dma_deinit(DMA0, DMA_CH5); dma_init(DMA0, DMA_CH5, ¤tState.dma_init_struct); i2c_dma_last_transfer_config(I2C0, I2C_DMALST_ON); dma_circulation_disable(DMA0, DMA_CH5); /* enable I2C0 DMA */ i2c_dma_enable(I2C0, I2C_DMA_ON); /* enable DMA0 channel5 */ dma_channel_enable(DMA0, DMA_CH5); currentState.currentStep = i2c_step::Write_device_data_finish; } break; case i2c_step::Write_device_data_finish: // Wait for complete then goto stop /* wait until BTC bit is set */ if (dma_flag_get(DMA0, DMA_CH5, DMA_FLAG_FTF)) { /* wait until BTC bit is set */ if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) { currentState.currentStep = i2c_step::Send_stop; } } break; case i2c_step::Read_start: if (i2c_flag_get(I2C0, I2C_FLAG_BTC)) { /* wait until BTC bit is set */ i2c_start_on_bus(I2C0); currentState.currentStep = i2c_step::Read_device_address; } break; case i2c_step::Read_device_address: if (i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) { i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); if (currentState.numberOfBytes == 1) { /* disable acknowledge */ i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_RECEIVER); while (!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { } i2c_ack_config(I2C0, I2C_ACK_DISABLE); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); /* wait for the byte to be received */ while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { } /* read the byte received from the EEPROM */ *currentState.buffer = i2c_data_receive(I2C0); while (i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { i2c_data_receive(I2C0); } i2c_stop_on_bus(I2C0); while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP)) { asm("nop"); } currentState.currentStep = i2c_step::Done; } else if (currentState.numberOfBytes == 2) { /* disable acknowledge */ i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_RECEIVER); while (!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { } i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); /* wait for the byte to be received */ while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { } i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); i2c_ack_config(I2C0, I2C_ACK_DISABLE); /* read the byte received from the EEPROM */ *currentState.buffer = i2c_data_receive(I2C0); currentState.buffer++; /* wait for the byte to be received */ while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { } /* read the byte received from the EEPROM */ *currentState.buffer = i2c_data_receive(I2C0); while (i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { i2c_data_receive(I2C0); } i2c_stop_on_bus(I2C0); while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP)) { asm("nop"); } currentState.currentStep = i2c_step::Done; } else { i2c_master_addressing(I2C0, currentState.deviceAddress, I2C_RECEIVER); currentState.currentStep = i2c_step::Read_device_data_start; } } break; case i2c_step::Read_device_data_start: if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { // addr sent i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); /* one byte master reception procedure (polling) */ if (currentState.numberOfBytes == 0) { currentState.currentStep = i2c_step::Send_stop; } else { /* more than one byte master reception procedure (DMA) */ while (currentState.numberOfBytes) { if (3 == currentState.numberOfBytes) { /* wait until BTC bit is set */ while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) { } i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); /* disable acknowledge */ i2c_ack_config(I2C0, I2C_ACK_DISABLE); } else if (2 == currentState.numberOfBytes) { /* wait until BTC bit is set */ while (!i2c_flag_get(I2C0, I2C_FLAG_BTC)) { } /* disable acknowledge */ i2c_ack_config(I2C0, I2C_ACK_DISABLE); /* send a stop condition to I2C bus */ i2c_stop_on_bus(I2C0); } /* wait until RBNE bit is set */ while (!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) { } /* read a byte from the EEPROM */ *currentState.buffer = i2c_data_receive(I2C0); /* point to the next location where the byte read will be saved */ currentState.buffer++; /* decrement the read bytes counter */ currentState.numberOfBytes--; } currentState.currentStep = i2c_step::Wait_stop; // currentState.currentStep = i2c_step::Read_device_data_finish; } } break; case i2c_step::Read_device_data_finish: // Wait for complete then goto stop /* wait until BTC bit is set */ break; case i2c_step::Send_stop: /* send a stop condition to I2C bus*/ i2c_stop_on_bus(I2C0); currentState.currentStep = i2c_step::Wait_stop; break; case i2c_step::Wait_stop: /* i2c master sends STOP signal successfully */ if ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) != I2C_CTL0_STOP) { currentState.currentStep = i2c_step::Done; } break; default: // If we get here something is amiss return; } } bool perform_i2c_transaction(uint16_t DevAddress, uint16_t memory_address, uint8_t *p_buffer, uint16_t number_of_byte, bool isWrite, bool isWakeOnly) { currentState.isMemoryWrite = isWrite; currentState.wakePart = isWakeOnly; currentState.deviceAddress = DevAddress; currentState.memoryAddress = memory_address; currentState.numberOfBytes = number_of_byte; currentState.buffer = p_buffer; // Setup DMA currentState.dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; currentState.dma_init_struct.memory_addr = (uint32_t)p_buffer; currentState.dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; currentState.dma_init_struct.number = number_of_byte; currentState.dma_init_struct.periph_addr = (uint32_t)&I2C_DATA(I2C0); currentState.dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; currentState.dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; currentState.dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; if (currentState.isMemoryWrite) { currentState.dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; } else { currentState.dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; } // Clear flags I2C_STAT0(I2C0) = 0; I2C_STAT1(I2C0) = 0; i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); i2c_data_receive(I2C0); i2c_data_receive(I2C0); currentState.currentStep = i2c_step::Write_start; // Always start in write mode TickType_t timeout = xTaskGetTickCount() + TICKS_100MS; while ((currentState.currentStep != i2c_step::Done) && (currentState.currentStep != i2c_step::Error_occured)) { if (xTaskGetTickCount() > timeout) { i2c_stop_on_bus(I2C0); return false; } perform_i2c_step(); } return currentState.currentStep == i2c_step::Done; } bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) { if (!lock()) { return false; } bool res = perform_i2c_transaction(DevAddress, read_address, p_buffer, number_of_byte, false, false); if (!res) { I2C_Unstick(); } unlock(); return res; } bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) { if (!lock()) { return false; } bool res = perform_i2c_transaction(DevAddress, MemAddress, p_buffer, number_of_byte, true, false); if (!res) { I2C_Unstick(); } unlock(); return res; } bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); } bool FRToSI2C::probe(uint16_t DevAddress) { uint8_t temp[1]; return Mem_Read(DevAddress, 0x00, temp, sizeof(temp)); } void FRToSI2C::I2C_Unstick() { unstick_I2C(); } bool FRToSI2C::lock() { if (I2CSemaphore == nullptr) { return false; } return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE; } void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); } bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) { for (int index = 0; index < registersLength; index++) { if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) { return false; } if (registers[index].pause_ms) { delay_ms(registers[index].pause_ms); } } return true; } bool FRToSI2C::wakePart(uint16_t DevAddress) { // wakepart is a special case where only the device address is sent if (!lock()) { return false; } bool res = perform_i2c_transaction(DevAddress, 0, NULL, 0, false, true); if (!res) { I2C_Unstick(); } unlock(); return res; } void I2C_EV_IRQ() {} void I2C_ER_IRQ() { // Error callbacks } ================================================ FILE: source/Core/BSP/Pinecil/IRQ.cpp ================================================ /* * IRQ.c * * Created on: 30 May 2020 * Author: Ralim */ #include "IRQ.h" #include "Pins.h" #include "configuration.h" volatile uint8_t i2c_read_process = 0; volatile uint8_t i2c_write_process = 0; volatile uint8_t i2c_slave_address = 0; volatile uint8_t i2c_error_code = 0; volatile uint8_t *i2c_write; volatile uint8_t *i2c_read; volatile uint16_t i2c_nbytes; volatile uint16_t i2c_write_dress; volatile uint16_t i2c_read_dress; volatile uint8_t i2c_process_flag = 0; static bool fastPWM; static void switchToSlowPWM(void); static void switchToFastPWM(void); void ADC0_1_IRQHandler(void) { adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); // unblock the PID controller thread if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; if (pidTaskNotification) { vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } } volatile uint16_t PWMSafetyTimer = 0; volatile uint8_t pendingPWM = 0; void TIMER1_IRQHandler(void) { static bool lastPeriodWasFast = false; if (timer_interrupt_flag_get(TIMER1, TIMER_INT_UP) == SET) { timer_interrupt_flag_clear(TIMER1, TIMER_INT_UP); // rollover turn on output if required if (PWMSafetyTimer) { PWMSafetyTimer--; if (lastPeriodWasFast != fastPWM) { if (fastPWM) { switchToFastPWM(); } else { switchToSlowPWM(); } } if (pendingPWM) { timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, pendingPWM); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 50); } else { timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0); } } } if (timer_interrupt_flag_get(TIMER1, TIMER_INT_CH1) == SET) { timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH1); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0); } } void switchToFastPWM(void) { fastPWM = true; totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; TIMER_CAR(TIMER1) = (uint32_t)totalPWM; // ~10Hz TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks; // 1 kHz tick rate TIMER_PSC(TIMER1) = 18000; } void switchToSlowPWM(void) { // 5Hz fastPWM = false; totalPWM = powerPWM + tempMeasureTicks / 2 + holdoffTicks / 2; TIMER_CAR(TIMER1) = (uint32_t)totalPWM; TIMER_CH0CV(TIMER1) = powerPWM + holdoffTicks / 2; TIMER_PSC(TIMER1) = 36000; } void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) { PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is // disabled if the PID task is not scheduled often enough. pendingPWM = pulse; fastPWM = shouldUseFastModePWM; } extern osThreadId POWTaskHandle; void EXTI5_9_IRQHandler(void) { #ifdef POW_PD if (RESET != exti_interrupt_flag_get(EXTI_5)) { exti_interrupt_flag_clear(EXTI_5); if (POWTaskHandle != nullptr) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken); /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE. The macro used to do this is dependent on the port and may be called portEND_SWITCHING_ISR. */ portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } #endif } bool getFUS302IRQLow() { // Return true if the IRQ line is still held low return (RESET == gpio_input_bit_get(FUSB302_IRQ_GPIO_Port, FUSB302_IRQ_Pin)); } // These are unused for now void I2C0_EV_IRQHandler(void) {} void I2C0_ER_IRQHandler(void) {} ================================================ FILE: source/Core/BSP/Pinecil/IRQ.h ================================================ /* * Irqs.h * * Created on: 30 May 2020 * Author: Ralim */ #ifndef BSP_PINE64_IRQ_H_ #define BSP_PINE64_IRQ_H_ #include "BSP.h" #include "I2C_Wrapper.hpp" #include "Setup.h" #include "gd32vf103.h" #include "main.hpp" #ifdef __cplusplus extern "C" { #endif void ADC0_1_IRQHandler(void); void TIMER1_IRQHandler(void); void EXTI5_9_IRQHandler(void); /* handle I2C0 event interrupt request */ void I2C0_EV_IRQHandler(void); /* handle I2C0 error interrupt request */ void I2C0_ER_IRQHandler(void); typedef enum { I2C_SEND_ADDRESS_FIRST = 0, // Sending slave address I2C_CLEAR_ADDRESS_FLAG_FIRST, // Clear address send I2C_TRANSMIT_WRITE_READ_ADD, // Transmit the memory address to read/write from I2C_SEND_ADDRESS_SECOND, // Send address again for read I2C_CLEAR_ADDRESS_FLAG_SECOND, // Clear address again I2C_TRANSMIT_DATA, // Transmit recieve data I2C_STOP, // Send stop I2C_ABORTED, // I2C_DONE, // I2C transfer is complete I2C_START, I2C_END, I2C_OK, I2C_SEND_ADDRESS, I2C_CLEAR_ADDRESS_FLAG, } i2c_process_enum; extern volatile uint8_t i2c_slave_address; extern volatile uint8_t i2c_read_process; extern volatile uint8_t i2c_write_process; extern volatile uint8_t i2c_error_code; extern volatile uint8_t *i2c_write; extern volatile uint8_t *i2c_read; extern volatile uint16_t i2c_nbytes; extern volatile uint16_t i2c_write_dress; extern volatile uint16_t i2c_read_dress; extern volatile uint8_t i2c_process_flag; #ifdef __cplusplus } #endif #endif /* BSP_PINE64_IRQ_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/NOTES.md ================================================ # Notes on RISC-V ## Pinmap | Pin Number | Name | Function | Notes | | ---------- | ---- | ---------------- | ----------- | | 17 | PB2 | BOOT2 | Pulldown | | 32 | | IMU INT 1 | N/A | | 30 | | IMU INT 2 | N/A | | | PA4 | Handle Temp | ADC Input ? | | | PA1 | Tip Temp | ADC Input ? | | | PB1 | B Button | Active High | | | PB0 | A Button | Active High | | | PA11 | USB D- | - | | | PA12 | USB D+ | - | | | PA6 | Tip PWM Out | - | | | PA0 | Input DC V Sense | ADC Input ? | | | PA9 | OLED Reset | | | | PB7 | SDA | I2C0_SDA | | | PB6 | SCL | I2C0_SCL | ## ADC Configuration For now running in matching mode for TS100 - X channels DMA in background - Sample tip using "Intereted" channels using TIMER 0,1,3 TRGO or timer0,1,2 channels - Using just 12 bit mode for now and move to hardware oversampling later - use DMA for normal samples and 4x16 bit regs for tip temp - It has dual ADC's so run them in pair mode ## Timers ### Timer 2 Timer 2 CH0 is tip drive PWM out. This is fixed at 50% duty cycle and used via the cap to turn on the heater tip. This should toggle relatively quickly. ================================================ FILE: source/Core/BSP/Pinecil/Pins.h ================================================ /* * Pins.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_PINE64_PINS_H_ #define BSP_PINE64_PINS_H_ #include "gd32vf103_gpio.h" #define KEY_B_Pin BIT(1) #define KEY_B_GPIO_Port GPIOB #define TMP36_INPUT_Pin BIT(4) #define TMP36_INPUT_GPIO_Port GPIOA #define TMP36_ADC0_CHANNEL ADC_CHANNEL_4 #define TMP36_ADC1_CHANNEL ADC_CHANNEL_4 #define TIP_TEMP_Pin BIT(1) #define TIP_TEMP_GPIO_Port GPIOA #define TIP_TEMP_ADC0_CHANNEL ADC_CHANNEL_1 #define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_1 #define VIN_Pin BIT(0) #define VIN_GPIO_Port GPIOA #define VIN_ADC0_CHANNEL ADC_CHANNEL_0 #define VIN_ADC1_CHANNEL ADC_CHANNEL_0 #define OLED_RESET_Pin BIT(9) #define OLED_RESET_GPIO_Port GPIOA #define KEY_A_Pin BIT(0) #define KEY_A_GPIO_Port GPIOB #define PWM_Out_Pin BIT(6) #define PWM_Out_GPIO_Port GPIOA #define SCL_Pin BIT(6) #define SCL_GPIO_Port GPIOB #define SDA_Pin BIT(7) #define SDA_GPIO_Port GPIOB #define USB_DM_Pin BIT(11) #define USB_DM_LOW_GPIO_Port GPIOA #define QC_DP_LOW_Pin BIT(7) #define QC_DP_LOW_GPIO_Port GPIOA // LOW = low resistance, HIGH = high resistance #define QC_DM_LOW_Pin BIT(8) #define QC_DM_LOW_GPIO_Port GPIOA #define QC_DM_HIGH_Pin BIT(10) #define QC_DM_HIGH_GPIO_Port GPIOA #define FUSB302_IRQ_Pin BIT(5) #define FUSB302_IRQ_GPIO_Port GPIOB // uart #define UART_TX_Pin BIT(2) #define UART_TX_GPIO_Port GPIOA #define UART_RX_Pin BIT(3) #define UART_RX_GPIO_Port GPIOA #define UART_PERIF USART1 #endif /* BSP_PINE64_PINS_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/Power.cpp ================================================ #include "BSP.h" #include "BSP_Power.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "USBPD.h" #include "configuration.h" void power_check() { #ifdef POW_PD // Cant start QC until either PD works or fails if (!USBPowerDelivery::negotiationComplete()) { return; } if (USBPowerDelivery::negotiationHasWorked()) { return; // We are using PD } #endif #ifdef POW_QC QC_resync(); #endif } bool getIsPoweredByDCIN() { #ifdef POW_PD if (!USBPowerDelivery::negotiationComplete()) { return false; // We are assuming not dc while negotiating } if (USBPowerDelivery::negotiationHasWorked()) { return false; // We are using PD } #endif #ifdef POW_QC if (hasQCNegotiated()) { return false; // We are using QC } #endif return true; } ================================================ FILE: source/Core/BSP/Pinecil/QC_GPIO.cpp ================================================ /* * QC.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "gd32vf103_libopt.h" #ifdef POW_QC void QC_DPlusZero_Six() { // pull down D+ gpio_bit_reset(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin); } void QC_DNegZero_Six() { gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin); gpio_bit_reset(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin); } void QC_DPlusThree_Three() { // pull up D+ gpio_bit_set(QC_DP_LOW_GPIO_Port, QC_DP_LOW_Pin); } void QC_DNegThree_Three() { gpio_bit_set(QC_DM_LOW_GPIO_Port, QC_DM_LOW_Pin); gpio_bit_set(QC_DM_HIGH_GPIO_Port, QC_DM_HIGH_Pin); } void QC_DM_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, USB_DM_Pin); } void QC_DM_No_PullDown() { gpio_init(USB_DM_LOW_GPIO_Port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_2MHZ, USB_DM_Pin); } void QC_Init_GPIO() { // Setup any GPIO into the right states for QC // D+ pulldown as output gpio_init(QC_DP_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DP_LOW_Pin); // Make two D- pins floating QC_DM_PullDown(); } void QC_Post_Probe_En() { // Make two D- pins outputs gpio_init(QC_DM_LOW_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_LOW_Pin); gpio_init(QC_DM_HIGH_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, QC_DM_HIGH_Pin); } uint8_t QC_DM_PulledDown() { return gpio_input_bit_get(USB_DM_LOW_GPIO_Port, USB_DM_Pin) == RESET ? 1 : 0; } #endif void QC_resync() { #ifdef POW_QC seekQC(getSettingValue(SettingsOptions::QCIdealVoltage), getSettingValue(SettingsOptions::VoltageDiv)); // Run the QC seek again if we have drifted too much #endif } ================================================ FILE: source/Core/BSP/Pinecil/README.md ================================================ # BSP section for Pinecil This folder contains the hardware abstractions required for the Pinecil. A RISC-V based soldering iron. ================================================ FILE: source/Core/BSP/Pinecil/Setup.cpp ================================================ /* * Setup.c * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #include "Setup.h" #include "BSP.h" #include "Debug.h" #include "Pins.h" #include "gd32vf103.h" #include "history.hpp" #include #define ADC_NORM_SAMPLES 16 #define ADC_FILTER_LEN 4 uint16_t ADCReadings[ADC_NORM_SAMPLES]; // room for 32 lots of the pair of readings // Functions void setup_gpio(); void setup_dma(); void setup_i2c(); void setup_adc(); void setup_timers(); void setup_iwdg(); void setup_uart(); void hardware_init() { // I2C setup_i2c(); // GPIO setup_gpio(); // DMA setup_dma(); // ADC's setup_adc(); // Timers setup_timers(); // Watchdog setup_iwdg(); // ELIC eclic_priority_group_set(ECLIC_PRIGROUP_LEVEL0_PRIO4); // uart for debugging setup_uart(); /* enable TIMER1 - PWM control timing*/ timer_enable(TIMER1); timer_enable(TIMER2); } uint16_t getADCHandleTemp(uint8_t sample) { static history filter = {{0}, 0, 0}; if (sample) { uint32_t sum = 0; for (uint8_t i = 0; i < ADC_NORM_SAMPLES; i++) { sum += ADCReadings[i]; } filter.update(sum); } return filter.average() >> 1; } uint16_t getADCVin(uint8_t sample) { static history filter = {{0}, 0, 0}; if (sample) { uint16_t latestADC = 0; latestADC += adc_inserted_data_read(ADC1, 0); latestADC += adc_inserted_data_read(ADC1, 1); latestADC += adc_inserted_data_read(ADC1, 2); latestADC += adc_inserted_data_read(ADC1, 3); latestADC <<= 1; filter.update(latestADC); } return filter.average(); } // Returns either average or instant value. When sample is set the samples from the injected ADC are copied to the filter and then the raw reading is returned uint16_t getTipRawTemp(uint8_t sample) { static history filter = {{0}, 0, 0}; if (sample) { uint16_t latestADC = 0; latestADC += adc_inserted_data_read(ADC0, 0); latestADC += adc_inserted_data_read(ADC0, 1); latestADC += adc_inserted_data_read(ADC0, 2); latestADC += adc_inserted_data_read(ADC0, 3); latestADC <<= 1; filter.update(latestADC); return latestADC; } return filter.average(); } void setup_uart() { // Setup the uart pins as a uart with dma /* enable USART clock */ rcu_periph_clock_enable(RCU_USART1); /* connect port to USARTx_Tx */ gpio_init(UART_TX_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_10MHZ, UART_TX_Pin); /* connect port to USARTx_Rx */ gpio_init(UART_RX_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_10MHZ, UART_RX_Pin); /* USART configure */ usart_deinit(UART_PERIF); usart_baudrate_set(UART_PERIF, 1000000); usart_word_length_set(UART_PERIF, USART_WL_8BIT); usart_stop_bit_set(UART_PERIF, USART_STB_1BIT); usart_parity_config(UART_PERIF, USART_PM_NONE); usart_hardware_flow_rts_config(UART_PERIF, USART_RTS_DISABLE); usart_hardware_flow_cts_config(UART_PERIF, USART_CTS_DISABLE); usart_receive_config(UART_PERIF, USART_RECEIVE_DISABLE); // Dont use rx for now usart_transmit_config(UART_PERIF, USART_TRANSMIT_ENABLE); eclic_irq_enable(USART1_IRQn, 15, 15); usart_enable(UART_PERIF); } void setup_gpio() { /* enable GPIOB clock */ rcu_periph_clock_enable(RCU_GPIOA); /* enable GPIOB clock */ rcu_periph_clock_enable(RCU_GPIOB); // Alternate function clock enable rcu_periph_clock_enable(RCU_AF); // Buttons as input gpio_init(KEY_A_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_A_Pin); gpio_init(KEY_B_GPIO_Port, GPIO_MODE_IPD, GPIO_OSPEED_2MHZ, KEY_B_Pin); // OLED reset as output gpio_init(OLED_RESET_GPIO_Port, GPIO_MODE_OUT_PP, GPIO_OSPEED_2MHZ, OLED_RESET_Pin); // I2C as AF Open Drain gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin); gpio_init(SCL_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SCL_Pin); // PWM output as AF Push Pull gpio_init(PWM_Out_GPIO_Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_Out_Pin); // Analog Inputs ... as analog inputs gpio_init(TMP36_INPUT_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TMP36_INPUT_Pin); gpio_init(TIP_TEMP_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, TIP_TEMP_Pin); gpio_init(VIN_GPIO_Port, GPIO_MODE_AIN, GPIO_OSPEED_2MHZ, VIN_Pin); // Remap PB4 away from JTAG NJRST gpio_pin_remap_config(GPIO_SWJ_NONJTRST_REMAP, ENABLE); // FUSB interrupt gpio_init(FUSB302_IRQ_GPIO_Port, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, FUSB302_IRQ_Pin); } void setup_dma() { // Setup DMA for ADC0 { /* enable DMA0 clock */ rcu_periph_clock_enable(RCU_DMA0); // rcu_periph_clock_enable(RCU_DMA1); /* ADC_DMA_channel configuration */ dma_parameter_struct dma_data_parameter; /* ADC DMA_channel configuration */ dma_deinit(DMA0, DMA_CH0); /* initialize DMA data mode */ dma_data_parameter.periph_addr = (uint32_t)(&ADC_RDATA(ADC0)); dma_data_parameter.periph_inc = DMA_PERIPH_INCREASE_DISABLE; dma_data_parameter.memory_addr = (uint32_t)(ADCReadings); dma_data_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; dma_data_parameter.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; dma_data_parameter.memory_width = DMA_MEMORY_WIDTH_16BIT; dma_data_parameter.direction = DMA_PERIPHERAL_TO_MEMORY; dma_data_parameter.number = ADC_NORM_SAMPLES; dma_data_parameter.priority = DMA_PRIORITY_HIGH; dma_init(DMA0, DMA_CH0, &dma_data_parameter); dma_circulation_enable(DMA0, DMA_CH0); /* enable DMA channel */ dma_channel_enable(DMA0, DMA_CH0); } } void setup_i2c() { /* enable I2C0 clock */ rcu_periph_clock_enable(RCU_I2C0); /* enable DMA0 clock */ rcu_periph_clock_enable(RCU_DMA0); // Setup I20 at 400kHz i2c_clock_config(I2C0, 400 * 1000, I2C_DTCY_2); i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0x7F); i2c_enable(I2C0); /* enable acknowledge */ i2c_ack_config(I2C0, I2C_ACK_ENABLE); } void setup_adc() { // Setup ADC in normal + injected mode // Want it to sample handle temp and input voltage normally via dma // Then injected trigger to sample tip temp memset(ADCReadings, 0, sizeof(ADCReadings)); rcu_periph_clock_enable(RCU_ADC0); rcu_periph_clock_enable(RCU_ADC1); adc_deinit(ADC0); adc_deinit(ADC1); /* config ADC clock */ rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV16); // Run in normal parallel + inserted parallel adc_mode_config(ADC_DAUL_INSERTED_PARALLEL); adc_special_function_config(ADC0, ADC_CONTINUOUS_MODE, ENABLE); adc_special_function_config(ADC0, ADC_SCAN_MODE, ENABLE); adc_special_function_config(ADC1, ADC_CONTINUOUS_MODE, ENABLE); adc_special_function_config(ADC1, ADC_SCAN_MODE, ENABLE); // Align right adc_data_alignment_config(ADC0, ADC_DATAALIGN_RIGHT); adc_data_alignment_config(ADC1, ADC_DATAALIGN_RIGHT); // Setup reading the handle temp adc_channel_length_config(ADC0, ADC_REGULAR_CHANNEL, 1); adc_channel_length_config(ADC1, ADC_REGULAR_CHANNEL, 0); // Setup the two channels adc_regular_channel_config(ADC0, 0, TMP36_ADC0_CHANNEL, ADC_SAMPLETIME_71POINT5); // temp sensor // Setup that we want all 4 inserted readings to be the tip temp adc_channel_length_config(ADC0, ADC_INSERTED_CHANNEL, 4); adc_channel_length_config(ADC1, ADC_INSERTED_CHANNEL, 4); for (int rank = 0; rank < 4; rank++) { adc_inserted_channel_config(ADC0, rank, TIP_TEMP_ADC0_CHANNEL, ADC_SAMPLETIME_28POINT5); adc_inserted_channel_config(ADC1, rank, VIN_ADC1_CHANNEL, ADC_SAMPLETIME_28POINT5); } // Setup timer 1 channel 0 to trigger injected measurements adc_external_trigger_source_config(ADC0, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_TRGO); adc_external_trigger_source_config(ADC1, ADC_INSERTED_CHANNEL, ADC0_1_EXTTRIG_INSERTED_T1_TRGO); adc_external_trigger_source_config(ADC0, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); adc_external_trigger_source_config(ADC1, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE); // Enable triggers for the ADC adc_external_trigger_config(ADC0, ADC_INSERTED_CHANNEL, ENABLE); adc_external_trigger_config(ADC1, ADC_INSERTED_CHANNEL, ENABLE); adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE); adc_external_trigger_config(ADC1, ADC_REGULAR_CHANNEL, ENABLE); adc_watchdog_disable(ADC0); adc_watchdog_disable(ADC1); adc_resolution_config(ADC0, ADC_RESOLUTION_12B); adc_resolution_config(ADC1, ADC_RESOLUTION_12B); /* clear the ADC flag */ adc_oversample_mode_disable(ADC0); adc_oversample_mode_disable(ADC1); adc_enable(ADC0); adc_calibration_enable(ADC0); adc_enable(ADC1); adc_calibration_enable(ADC1); adc_dma_mode_enable(ADC0); // Enable interrupt on end of injected readings adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOC); adc_interrupt_flag_clear(ADC0, ADC_INT_FLAG_EOIC); adc_interrupt_enable(ADC0, ADC_INT_EOIC); eclic_irq_enable(ADC0_1_IRQn, 2, 0); adc_software_trigger_enable(ADC0, ADC_REGULAR_CHANNEL); adc_software_trigger_enable(ADC1, ADC_REGULAR_CHANNEL); adc_tempsensor_vrefint_disable(); } void setup_timers() { // Setup timer 1 to run the actual PWM level /* enable timer1 clock */ rcu_periph_clock_enable(RCU_TIMER1); rcu_periph_clock_enable(RCU_TIMER2); timer_oc_parameter_struct timer_ocintpara; timer_parameter_struct timer_initpara; { // deinit to reset the timer timer_deinit(TIMER1); /* initialize TIMER init parameter struct */ timer_struct_para_init(&timer_initpara); /* TIMER1 configuration */ timer_initpara.prescaler = 30000; timer_initpara.alignedmode = TIMER_COUNTER_EDGE; timer_initpara.counterdirection = TIMER_COUNTER_UP; timer_initpara.period = powerPWM + tempMeasureTicks + holdoffTicks; timer_initpara.clockdivision = TIMER_CKDIV_DIV4; timer_initpara.repetitioncounter = 0; timer_init(TIMER1, &timer_initpara); /* CH0 configured to implement the PWM irq's for the output control*/ timer_channel_output_struct_para_init(&timer_ocintpara); timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_LOW; timer_ocintpara.outputstate = TIMER_CCX_ENABLE; timer_channel_output_config(TIMER1, TIMER_CH_0, &timer_ocintpara); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, powerPWM + holdoffTicks); timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_PWM1); timer_channel_output_shadow_config(TIMER1, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); /* CH1 used for irq */ timer_channel_output_struct_para_init(&timer_ocintpara); timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; timer_ocintpara.outputstate = TIMER_CCX_ENABLE; timer_channel_output_config(TIMER1, TIMER_CH_1, &timer_ocintpara); timer_master_output_trigger_source_select(TIMER1, TIMER_TRI_OUT_SRC_CH0); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, 0); timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM0); timer_channel_output_shadow_config(TIMER1, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); // IRQ timer_interrupt_enable(TIMER1, TIMER_INT_UP); timer_interrupt_enable(TIMER1, TIMER_INT_CH1); } eclic_irq_enable(TIMER1_IRQn, 2, 5); // Setup timer 2 to control the output signal { timer_deinit(TIMER2); /* initialize TIMER init parameter struct */ timer_struct_para_init(&timer_initpara); /* TIMER1 configuration */ timer_initpara.prescaler = 200; timer_initpara.alignedmode = TIMER_COUNTER_EDGE; timer_initpara.counterdirection = TIMER_COUNTER_UP; timer_initpara.period = 100; timer_initpara.clockdivision = TIMER_CKDIV_DIV4; timer_initpara.repetitioncounter = 0; timer_init(TIMER2, &timer_initpara); /* CH0 configuration in PWM mode0 */ timer_channel_output_struct_para_init(&timer_ocintpara); timer_ocintpara.outputstate = TIMER_CCX_ENABLE; timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE; timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; timer_channel_output_config(TIMER2, TIMER_CH_0, &timer_ocintpara); timer_channel_output_pulse_value_config(TIMER2, TIMER_CH_0, 0); timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_PWM0); timer_channel_output_shadow_config(TIMER2, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); timer_auto_reload_shadow_enable(TIMER2); timer_enable(TIMER2); } } void setup_iwdg() { fwdgt_config(0x0FFF, FWDGT_PSC_DIV256); fwdgt_enable(); } void setupFUSBIRQ() { eclic_global_interrupt_enable(); eclic_irq_enable(EXTI5_9_IRQn, 15, 0); gpio_exti_source_select(GPIO_PORT_SOURCE_GPIOB, GPIO_PIN_SOURCE_5); /* configure key EXTI line */ exti_init(EXTI_5, EXTI_INTERRUPT, EXTI_TRIG_FALLING); } ================================================ FILE: source/Core/BSP/Pinecil/Setup.h ================================================ /* * Setup.h * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #ifndef PINE_SETUP_H_ #define PINE_SETUP_H_ #include "gd32vf103_libopt.h" #include #ifdef __cplusplus extern "C" { #endif uint16_t getADC(uint8_t channel); void hardware_init(); uint16_t getADCHandleTemp(uint8_t sample); uint16_t getADCVin(uint8_t sample); #ifdef __cplusplus } #endif void setupFUSBIRQ(); extern const uint8_t holdoffTicks; extern const uint8_t tempMeasureTicks; #endif /* PINE_SETUP_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/ThermoModel.cpp ================================================ /* * ThermoModel.cpp * * Created on: 1 May 2021 * Author: Ralim */ #include "TipThermoModel.h" #include "Utils.hpp" #include "configuration.h" #ifdef TEMP_uV_LOOKUP_HAKKO const int32_t uVtoDegC[] = { // // uv -> temp in C 0, 0, // 266, 10, // 522, 20, // 770, 30, // 1010, 40, // 1244, 50, // 1473, 60, // 1697, 70, // 1917, 80, // 2135, 90, // 2351, 100, // 2566, 110, // 2780, 120, // 2994, 130, // 3209, 140, // 3426, 150, // 3644, 160, // 3865, 170, // 4088, 180, // 4314, 190, // 4544, 200, // 4777, 210, // 5014, 220, // 5255, 230, // 5500, 240, // 5750, 250, // 6003, 260, // 6261, 270, // 6523, 280, // 6789, 290, // 7059, 300, // 7332, 310, // 7609, 320, // 7889, 330, // 8171, 340, // 8456, 350, // 8742, 360, // 9030, 370, // 9319, 380, // 9607, 390, // 9896, 400, // 10183, 410, // 10468, 420, // 10750, 430, // 11029, 440, // 11304, 450, // 11573, 460, // 11835, 470, // 12091, 480, // 12337, 490, // 12575, 500, // }; #endif const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(uVtoDegC[0])); TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); } ================================================ FILE: source/Core/BSP/Pinecil/UnitSettings.h ================================================ /* * UnitSettings.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_PINE64_UNITSETTINGS_H_ #define BSP_PINE64_UNITSETTINGS_H_ #endif /* BSP_PINE64_UNITSETTINGS_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_compatiable.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_COMPATIABLE_H__ #define __CORE_COMPATIABLE_H__ /*! * @file core_compatiable.h * @brief ARM compatiable function definitions header file */ #ifdef __cplusplus extern "C" { #endif /* ===== ARM Compatiable Functions ===== */ /** * \defgroup NMSIS_Core_ARMCompatiable_Functions ARM Compatiable Functions * \ingroup NMSIS_Core * \brief A few functions that compatiable with ARM CMSIS-Core. * \details * * Here we provided a few functions that compatiable with ARM CMSIS-Core, * mostly used in the DSP and NN library. * @{ */ /** \brief Instruction Synchronization Barrier, compatiable with ARM */ #define __ISB() __RWMB() /** \brief Data Synchronization Barrier, compatiable with ARM */ #define __DSB() __RWMB() /** \brief Data Memory Barrier, compatiable with ARM */ #define __DMB() __RWMB() /** \brief LDRT Unprivileged (8 bit), ARM Compatiable */ #define __LDRBT(ptr) __LB((ptr)) /** \brief LDRT Unprivileged (16 bit), ARM Compatiable */ #define __LDRHT(ptr) __LH((ptr)) /** \brief LDRT Unprivileged (32 bit), ARM Compatiable */ #define __LDRT(ptr) __LW((ptr)) /** \brief STRT Unprivileged (8 bit), ARM Compatiable */ #define __STRBT(ptr) __SB((ptr)) /** \brief STRT Unprivileged (16 bit), ARM Compatiable */ #define __STRHT(ptr) __SH((ptr)) /** \brief STRT Unprivileged (32 bit), ARM Compatiable */ #define __STRT(ptr) __SW((ptr)) /* ===== Saturation Operations ===== */ /** * \brief Signed Saturate * \details Saturates a signed value. * \param [in] value Value to be saturated * \param [in] sat Bit position to saturate to (1..32) * \return Saturated value */ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1)) #else __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max; if (val > max) { return max; } else if (val < min) { return min; } } return val; } #endif /** * \brief Unsigned Saturate * \details Saturates an unsigned value. * \param [in] value Value to be saturated * \param [in] sat Bit position to saturate to (0..31) * \return Saturated value */ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #define __USAT(val, sat) __RV_UCLIP32((val), (sat - 1)) #else __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ===== Data Processing Operations ===== */ /** * \brief Reverse byte order (32 bit) * \details Reverses the byte order in unsigned integer value. * For example, 0x12345678 becomes 0x78563412. * \param [in] value Value to reverse * \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { uint32_t result; result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24); return result; } /** * \brief Reverse byte order (16 bit) * \details Reverses the byte order within each halfword of a word. * For example, 0x12345678 becomes 0x34127856. * \param [in] value Value to reverse * \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8); return result; } /** * \brief Reverse byte order (16 bit) * \details Reverses the byte order in a 16-bit value * and returns the signed 16-bit result. * For example, 0x0080 becomes 0x8000. * \param [in] value Value to reverse * \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { int16_t result; result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8); return result; } /** * \brief Rotate Right in unsigned value (32 bit) * \details Rotate Right (immediate) provides the value of * the contents of a register rotated by a variable number of bits. * \param [in] op1 Value to rotate * \param [in] op2 Number of Bits to rotate(0-31) * \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 = op2 & 0x1F; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** * \brief Reverse bit order of value * \details Reverses the bit order of the given value. * \param [in] value Value to reverse * \return Reversed value */ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #define __RBIT(value) __RV_BITREVI((value), 31) #else __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ /** * \brief Count leading zeros * \details Counts the number of leading zeros of a data value. * \param [in] data Value to count the leading zeros * \return number of leading zeros in value */ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) #define __CLZ(data) __RV_CLZ32(data) #else __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) { uint8_t ret = 0; uint32_t temp = ~data; while (temp & 0x80000000) { temp <<= 1; ret++; } return ret; } #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ /** @} */ /* End of Doxygen Group NMSIS_Core_ARMCompatiable_Functions */ #ifdef __cplusplus } #endif #endif /* __CORE_COMPATIABLE_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_base.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_BASE__ #define __CORE_FEATURE_BASE__ /*! * @file core_feature_base.h * @brief Base core feature API for Nuclei N/NX Core */ #include "riscv_encoding.h" #include #ifdef __cplusplus extern "C" { #endif /** * \defgroup NMSIS_Core_Registers Register Define and Type Definitions * \brief Type definitions and defines for core registers. * * @{ */ #ifndef __RISCV_XLEN /** \brief Refer to the width of an integer register in bits(either 32 or 64) */ #ifndef __riscv_xlen #define __RISCV_XLEN 32 #else #define __RISCV_XLEN __riscv_xlen #endif #endif /* __RISCV_XLEN */ /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */ #if __RISCV_XLEN == 32 typedef uint32_t rv_csr_t; #elif __RISCV_XLEN == 64 typedef uint64_t rv_csr_t; #else typedef uint32_t rv_csr_t; #endif /** @} */ /* End of Doxygen Group NMSIS_Core_Registers */ /** * \defgroup NMSIS_Core_Base_Registers Base Register Define and Type Definitions * \ingroup NMSIS_Core_Registers * \brief Type definitions and defines for base core registers. * * @{ */ /** * \brief Union type to access MISA register. */ typedef union { struct { rv_csr_t a : 1; /*!< bit: 0 Atomic extension */ rv_csr_t b : 1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation extension */ rv_csr_t c : 1; /*!< bit: 2 Compressed extension */ rv_csr_t d : 1; /*!< bit: 3 Double-precision floating-point extension */ rv_csr_t e : 1; /*!< bit: 4 RV32E base ISA */ rv_csr_t f : 1; /*!< bit: 5 Single-precision floating-point extension */ rv_csr_t g : 1; /*!< bit: 6 Additional standard extensions present */ rv_csr_t h : 1; /*!< bit: 7 Hypervisor extension */ rv_csr_t i : 1; /*!< bit: 8 RV32I/64I/128I base ISA */ rv_csr_t j : 1; /*!< bit: 9 Tentatively reserved for Dynamically Translated Languages extension */ rv_csr_t _reserved1 : 1; /*!< bit: 10 Reserved */ rv_csr_t l : 1; /*!< bit: 11 Tentatively reserved for Decimal Floating-Point extension */ rv_csr_t m : 1; /*!< bit: 12 Integer Multiply/Divide extension */ rv_csr_t n : 1; /*!< bit: 13 User-level interrupts supported */ rv_csr_t _reserved2 : 1; /*!< bit: 14 Reserved */ rv_csr_t p : 1; /*!< bit: 15 Tentatively reserved for Packed-SIMD extension */ rv_csr_t q : 1; /*!< bit: 16 Quad-precision floating-point extension */ rv_csr_t _resreved3 : 1; /*!< bit: 17 Reserved */ rv_csr_t s : 1; /*!< bit: 18 Supervisor mode implemented */ rv_csr_t t : 1; /*!< bit: 19 Tentatively reserved for Transactional Memory extension */ rv_csr_t u : 1; /*!< bit: 20 User mode implemented */ rv_csr_t v : 1; /*!< bit: 21 Tentatively reserved for Vector extension */ rv_csr_t _reserved4 : 1; /*!< bit: 22 Reserved */ rv_csr_t x : 1; /*!< bit: 23 Non-standard extensions present */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved5 : 38; /*!< bit: 24..61 Reserved */ rv_csr_t mxl : 2; /*!< bit: 62..63 Machine XLEN */ #else rv_csr_t _reserved5 : 6; /*!< bit: 24..29 Reserved */ rv_csr_t mxl : 2; /*!< bit: 30..31 Machine XLEN */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MISA_Type; /** * \brief Union type to access MSTATUS configure register. */ typedef union { struct { #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved0 : 3; /*!< bit: 0..2 Reserved */ rv_csr_t mie : 1; /*!< bit: 3 Machine mode interrupt enable flag */ rv_csr_t _reserved1 : 3; /*!< bit: 4..6 Reserved */ rv_csr_t mpie : 1; /*!< bit: 7 mirror of MIE flag */ rv_csr_t _reserved2 : 3; /*!< bit: 8..10 Reserved */ rv_csr_t mpp : 2; /*!< bit: 11..12 mirror of Privilege Mode */ rv_csr_t fs : 2; /*!< bit: 13..14 FS status flag */ rv_csr_t xs : 2; /*!< bit: 15..16 XS status flag */ rv_csr_t mprv : 1; /*!< bit: Machine mode PMP */ rv_csr_t _reserved3 : 14; /*!< bit: 18..31 Reserved */ rv_csr_t uxl : 2; /*!< bit: 32..33 user mode xlen */ rv_csr_t _reserved6 : 29; /*!< bit: 34..62 Reserved */ rv_csr_t sd : 1; /*!< bit: Dirty status for XS or FS */ #else rv_csr_t _reserved0 : 1; /*!< bit: 0 Reserved */ rv_csr_t sie : 1; /*!< bit: 1 supervisor interrupt enable flag */ rv_csr_t _reserved1 : 1; /*!< bit: 2 Reserved */ rv_csr_t mie : 1; /*!< bit: 3 Machine mode interrupt enable flag */ rv_csr_t _reserved2 : 1; /*!< bit: 4 Reserved */ rv_csr_t spie : 1; /*!< bit: 3 Supervisor Privilede mode interrupt enable flag */ rv_csr_t _reserved3 : 1; /*!< bit: Reserved */ rv_csr_t mpie : 1; /*!< bit: mirror of MIE flag */ rv_csr_t _reserved4 : 3; /*!< bit: Reserved */ rv_csr_t mpp : 2; /*!< bit: mirror of Privilege Mode */ rv_csr_t fs : 2; /*!< bit: FS status flag */ rv_csr_t xs : 2; /*!< bit: XS status flag */ rv_csr_t mprv : 1; /*!< bit: Machine mode PMP */ rv_csr_t sum : 1; /*!< bit: Supervisor Mode load and store protection */ rv_csr_t _reserved6 : 12; /*!< bit: 19..30 Reserved */ rv_csr_t sd : 1; /*!< bit: Dirty status for XS or FS */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MSTATUS_Type; /** * \brief Union type to access MTVEC configure register. */ typedef union { struct { rv_csr_t mode : 6; /*!< bit: 0..5 interrupt mode control */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t addr : 58; /*!< bit: 6..63 mtvec address */ #else rv_csr_t addr : 26; /*!< bit: 6..31 mtvec address */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MTVEC_Type; /** * \brief Union type to access MCAUSE configure register. */ typedef union { struct { rv_csr_t exccode : 12; /*!< bit: 11..0 exception or interrupt code */ rv_csr_t _reserved0 : 4; /*!< bit: 15..12 Reserved */ rv_csr_t mpil : 8; /*!< bit: 23..16 Previous interrupt level */ rv_csr_t _reserved1 : 3; /*!< bit: 26..24 Reserved */ rv_csr_t mpie : 1; /*!< bit: 27 Interrupt enable flag before enter interrupt */ rv_csr_t mpp : 2; /*!< bit: 29..28 Privilede mode flag before enter interrupt */ rv_csr_t minhv : 1; /*!< bit: 30 Machine interrupt vector table */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved2 : 32; /*!< bit: 31..62 Reserved */ rv_csr_t interrupt : 1; /*!< bit: 63 trap type. 0 means exception and 1 means interrupt */ #else rv_csr_t interrupt : 1; /*!< bit: 31 trap type. 0 means exception and 1 means interrupt */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MCAUSE_Type; /** * \brief Union type to access MCOUNTINHIBIT configure register. */ typedef union { struct { rv_csr_t cy : 1; /*!< bit: 0 1 means disable mcycle counter */ rv_csr_t _reserved0 : 1; /*!< bit: 1 Reserved */ rv_csr_t ir : 1; /*!< bit: 2 1 means disable minstret counter */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved1 : 61; /*!< bit: 3..63 Reserved */ #else rv_csr_t _reserved1 : 29; /*!< bit: 3..31 Reserved */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MCOUNTINHIBIT_Type; /** * \brief Union type to access msubm configure register. */ typedef union { struct { rv_csr_t _reserved0 : 6; /*!< bit: 0..5 Reserved */ rv_csr_t typ : 2; /*!< bit: 6..7 current trap type */ rv_csr_t ptyp : 2; /*!< bit: 8..9 previous trap type */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved1 : 54; /*!< bit: 10..63 Reserved */ #else rv_csr_t _reserved1 : 22; /*!< bit: 10..31 Reserved */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MSUBM_Type; /** * \brief Union type to access MMISC_CTRL configure register. */ typedef union { struct { rv_csr_t _reserved0 : 3; /*!< bit: 0..2 Reserved */ rv_csr_t bpu : 1; /*!< bit: 3 dynamic prediction enable flag */ rv_csr_t _reserved1 : 2; /*!< bit: 4..5 Reserved */ rv_csr_t misalign : 1; /*!< bit: 6 misaligned access support flag */ rv_csr_t _reserved2 : 2; /*!< bit: 7..8 Reserved */ rv_csr_t nmi_cause : 1; /*!< bit: 9 mnvec control and nmi mcase exccode */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved3 : 54; /*!< bit: 10..63 Reserved */ #else rv_csr_t _reserved3 : 22; /*!< bit: 10..31 Reserved */ #endif } b; /*!< Structure used for bit access */ rv_csr_t d; /*!< Type used for csr data access */ } CSR_MMISCCTRL_Type; /** * \brief Union type to access MSAVESTATUS configure register. */ typedef union { struct { rv_csr_t mpie1 : 1; /*!< bit: 0 interrupt enable flag of fisrt level NMI/exception nestting */ rv_csr_t mpp1 : 2; /*!< bit: 1..2 privilede mode of fisrt level NMI/exception nestting */ rv_csr_t _reserved0 : 3; /*!< bit: 3..5 Reserved */ rv_csr_t ptyp1 : 2; /*!< bit: 6..7 NMI/exception type of before first nestting */ rv_csr_t mpie2 : 1; /*!< bit: 8 interrupt enable flag of second level NMI/exception nestting */ rv_csr_t mpp2 : 2; /*!< bit: 9..10 privilede mode of second level NMI/exception nestting */ rv_csr_t _reserved1 : 3; /*!< bit: 11..13 Reserved */ rv_csr_t ptyp2 : 2; /*!< bit: 14..15 NMI/exception type of before second nestting */ #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64 rv_csr_t _reserved2 : 48; /*!< bit: 16..63 Reserved*/ #else rv_csr_t _reserved2 : 16; /*!< bit: 16..31 Reserved*/ #endif } b; /*!< Structure used for bit access */ rv_csr_t w; /*!< Type used for csr data access */ } CSR_MSAVESTATUS_Type; /** @} */ /* End of Doxygen Group NMSIS_Core_Base_Registers */ /* ########################### Core Function Access ########################### */ /** * \defgroup NMSIS_Core_CSR_Register_Access Core CSR Register Access * \ingroup NMSIS_Core * \brief Functions to access the Core CSR Registers * \details * * The following functions or macros provide access to Core CSR registers. * - \ref NMSIS_Core_CSR_Encoding * - \ref NMSIS_Core_CSR_Registers * @{ */ #ifndef __ASSEMBLY__ /** * \brief CSR operation Macro for csrrw instruction. * \details * Read the content of csr register to __v, * then write content of val into csr register, then return __v * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val value to store into the CSR register * \return the CSR register value before written */ #define __RV_CSR_SWAP(csr, val) \ ({ \ volatile rv_csr_t __v = (unsigned long)(val); \ __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \ __v; \ }) /** * \brief CSR operation Macro for csrr instruction. * \details * Read the content of csr register to __v and return it * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \return the CSR register value */ #define __RV_CSR_READ(csr) \ ({ \ volatile rv_csr_t __v; \ __ASM volatile("csrr %0, " STRINGIFY(csr) : "=r"(__v) : : "memory"); \ __v; \ }) /** * \brief CSR operation Macro for csrw instruction. * \details * Write the content of val to csr register * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val value to store into the CSR register */ #define __RV_CSR_WRITE(csr, val) \ ({ \ volatile rv_csr_t __v = (rv_csr_t)(val); \ __ASM volatile("csrw " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \ }) /** * \brief CSR operation Macro for csrrs instruction. * \details * Read the content of csr register to __v, * then set csr register to be __v | val, then return __v * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val Mask value to be used wih csrrs instruction * \return the CSR register value before written */ #define __RV_CSR_READ_SET(csr, val) \ ({ \ volatile rv_csr_t __v = (rv_csr_t)(val); \ __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \ __v; \ }) /** * \brief CSR operation Macro for csrs instruction. * \details * Set csr register to be csr_content | val * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val Mask value to be used wih csrs instruction */ #define __RV_CSR_SET(csr, val) \ ({ \ volatile rv_csr_t __v = (rv_csr_t)(val); \ __ASM volatile("csrs " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \ }) /** * \brief CSR operation Macro for csrrc instruction. * \details * Read the content of csr register to __v, * then set csr register to be __v & ~val, then return __v * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val Mask value to be used wih csrrc instruction * \return the CSR register value before written */ #define __RV_CSR_READ_CLEAR(csr, val) \ ({ \ volatile rv_csr_t __v = (rv_csr_t)(val); \ __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" : "=r"(__v) : "rK"(__v) : "memory"); \ __v; \ }) /** * \brief CSR operation Macro for csrc instruction. * \details * Set csr register to be csr_content & ~val * \param csr CSR macro definition defined in * \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS * \param val Mask value to be used wih csrc instruction */ #define __RV_CSR_CLEAR(csr, val) \ ({ \ volatile rv_csr_t __v = (rv_csr_t)(val); \ __ASM volatile("csrc " STRINGIFY(csr) ", %0" : : "rK"(__v) : "memory"); \ }) #endif /* __ASSEMBLY__ */ /** * \brief Enable IRQ Interrupts * \details Enables IRQ interrupts by setting the MIE-bit in the MSTATUS Register. * \remarks * Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE); } /** * \brief Disable IRQ Interrupts * \details Disables IRQ interrupts by clearing the MIE-bit in the MSTATUS Register. * \remarks * Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE); } /** * \brief Read whole 64 bits value of mcycle counter * \details This function will read the whole 64 bits of MCYCLE register * \return The whole 64 bits value of MCYCLE * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE */ __STATIC_FORCEINLINE uint64_t __get_rv_cycle(void) { #if __RISCV_XLEN == 32 volatile uint32_t high0, low, high; uint64_t full; high0 = __RV_CSR_READ(CSR_MCYCLEH); low = __RV_CSR_READ(CSR_MCYCLE); high = __RV_CSR_READ(CSR_MCYCLEH); if (high0 != high) { low = __RV_CSR_READ(CSR_MCYCLE); } full = (((uint64_t)high) << 32) | low; return full; #elif __RISCV_XLEN == 64 return (uint64_t)__RV_CSR_READ(CSR_MCYCLE); #else // TODO Need cover for XLEN=128 case in future return (uint64_t)__RV_CSR_READ(CSR_MCYCLE); #endif } /** * \brief Read whole 64 bits value of machine instruction-retired counter * \details This function will read the whole 64 bits of MINSTRET register * \return The whole 64 bits value of MINSTRET * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET */ __STATIC_FORCEINLINE uint64_t __get_rv_instret(void) { #if __RISCV_XLEN == 32 volatile uint32_t high0, low, high; uint64_t full; high0 = __RV_CSR_READ(CSR_MINSTRETH); low = __RV_CSR_READ(CSR_MINSTRET); high = __RV_CSR_READ(CSR_MINSTRETH); if (high0 != high) { low = __RV_CSR_READ(CSR_MINSTRET); } full = (((uint64_t)high) << 32) | low; return full; #elif __RISCV_XLEN == 64 return (uint64_t)__RV_CSR_READ(CSR_MINSTRET); #else // TODO Need cover for XLEN=128 case in future return (uint64_t)__RV_CSR_READ(CSR_MINSTRET); #endif } /** * \brief Read whole 64 bits value of real-time clock * \details This function will read the whole 64 bits of TIME register * \return The whole 64 bits value of TIME CSR * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME * \attention only available when user mode available */ __STATIC_FORCEINLINE uint64_t __get_rv_time(void) { #if __RISCV_XLEN == 32 volatile uint32_t high0, low, high; uint64_t full; high0 = __RV_CSR_READ(CSR_TIMEH); low = __RV_CSR_READ(CSR_TIME); high = __RV_CSR_READ(CSR_TIMEH); if (high0 != high) { low = __RV_CSR_READ(CSR_TIME); } full = (((uint64_t)high) << 32) | low; return full; #elif __RISCV_XLEN == 64 return (uint64_t)__RV_CSR_READ(CSR_TIME); #else // TODO Need cover for XLEN=128 case in future return (uint64_t)__RV_CSR_READ(CSR_TIME); #endif } /** @} */ /* End of Doxygen Group NMSIS_Core_CSR_Register_Access */ /* ########################### CPU Intrinsic Functions ########################### */ /** * \defgroup NMSIS_Core_CPU_Intrinsic Intrinsic Functions for CPU Intructions * \ingroup NMSIS_Core * \brief Functions that generate RISC-V CPU instructions. * \details * * The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler. * @{ */ /** * \brief NOP Instruction * \details * No Operation does nothing. * This instruction can be used for code alignment purposes. */ __STATIC_FORCEINLINE void __NOP(void) { __ASM volatile("nop"); } /** * \brief Wait For Interrupt * \details * Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction. * It will suspends execution until interrupt, NMI or Debug happened. * When Core is waked up by interrupt, if * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution */ __STATIC_FORCEINLINE void __WFI(void) { __RV_CSR_CLEAR(CSR_WFE, WFE_WFE); __ASM volatile("wfi"); } /** * \brief Wait For Event * \details * Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction. * It will suspends execution until event, NMI or Debug happened. * When Core is waked up, Core will resume previous execution */ __STATIC_FORCEINLINE void __WFE(void) { __RV_CSR_SET(CSR_WFE, WFE_WFE); __ASM volatile("wfi"); __RV_CSR_CLEAR(CSR_WFE, WFE_WFE); } /** * \brief Breakpoint Instruction * \details * Causes the processor to enter Debug state. * Debug tools can use this to investigate system state * when the instruction at a particular address is reached. */ __STATIC_FORCEINLINE void __EBREAK(void) { __ASM volatile("ebreak"); } /** * \brief Environment Call Instruction * \details * The ECALL instruction is used to make a service request to * the execution environment. */ __STATIC_FORCEINLINE void __ECALL(void) { __ASM volatile("ecall"); } /** * \brief WFI Sleep Mode enumeration */ typedef enum WFI_SleepMode { WFI_SHALLOW_SLEEP = 0, /*!< Shallow sleep mode, the core_clk will poweroff */ WFI_DEEP_SLEEP = 1 /*!< Deep sleep mode, the core_clk and core_ano_clk will poweroff */ } WFI_SleepMode_Type; /** * \brief Set Sleep mode of WFI * \details * Set the SLEEPVALUE CSR register to control the * WFI Sleep mode. * \param[in] mode The sleep mode to be set */ __STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode) { __RV_CSR_WRITE(CSR_SLEEPVALUE, mode); } /** * \brief Send TX Event * \details * Set the CSR TXEVT to control send a TX Event. * The Core will output signal tx_evt as output event signal. */ __STATIC_FORCEINLINE void __TXEVT(void) { __RV_CSR_SET(CSR_TXEVT, 0x1); } /** * \brief Enable MCYCLE counter * \details * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter */ __STATIC_FORCEINLINE void __enable_mcycle_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); } /** * \brief Disable MCYCLE counter * \details * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter */ __STATIC_FORCEINLINE void __disable_mcycle_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY); } /** * \brief Enable MINSTRET counter * \details * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter */ __STATIC_FORCEINLINE void __enable_minstret_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); } /** * \brief Disable MINSTRET counter * \details * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter */ __STATIC_FORCEINLINE void __disable_minstret_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR); } /** * \brief Enable MCYCLE & MINSTRET counter * \details * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter */ __STATIC_FORCEINLINE void __enable_all_counter(void) { __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); } /** * \brief Disable MCYCLE & MINSTRET counter * \details * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter */ __STATIC_FORCEINLINE void __disable_all_counter(void) { __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY); } /** * \brief Execute fence instruction, p -> pred, s -> succ * \details * the FENCE instruction ensures that all memory accesses from instructions preceding * the fence in program order (the `predecessor set`) appear earlier in the global memory order than * memory accesses from instructions appearing after the fence in program order (the `successor set`). * For details, please refer to The RISC-V Instruction Set Manual * \param p predecessor set, such as iorw, rw, r, w * \param s successor set, such as iorw, rw, r, w **/ #define __FENCE(p, s) __ASM volatile("fence " #p "," #s : : : "memory") /** * \brief Fence.i Instruction * \details * The FENCE.I instruction is used to synchronize the instruction * and data streams. */ __STATIC_FORCEINLINE void __FENCE_I(void) { __ASM volatile("fence.i"); } /** \brief Read & Write Memory barrier */ #define __RWMB() __FENCE(iorw, iorw) /** \brief Read Memory barrier */ #define __RMB() __FENCE(ir, ir) /** \brief Write Memory barrier */ #define __WMB() __FENCE(ow, ow) /** \brief SMP Read & Write Memory barrier */ #define __SMP_RWMB() __FENCE(rw, rw) /** \brief SMP Read Memory barrier */ #define __SMP_RMB() __FENCE(r, r) /** \brief SMP Write Memory barrier */ #define __SMP_WMB() __FENCE(w, w) /** \brief CPU relax for busy loop */ #define __CPU_RELAX() __ASM volatile("" : : : "memory") /* ===== Load/Store Operations ===== */ /** * \brief Load 8bit value from address (8 bit) * \details Load 8 bit value. * \param [in] addr Address pointer to data * \return value of type uint8_t at (*addr) */ __STATIC_FORCEINLINE uint8_t __LB(volatile void *addr) { uint8_t result; __ASM volatile("lb %0, 0(%1)" : "=r"(result) : "r"(addr)); return result; } /** * \brief Load 16bit value from address (16 bit) * \details Load 16 bit value. * \param [in] addr Address pointer to data * \return value of type uint16_t at (*addr) */ __STATIC_FORCEINLINE uint16_t __LH(volatile void *addr) { uint16_t result; __ASM volatile("lh %0, 0(%1)" : "=r"(result) : "r"(addr)); return result; } /** * \brief Load 32bit value from address (32 bit) * \details Load 32 bit value. * \param [in] addr Address pointer to data * \return value of type uint32_t at (*addr) */ __STATIC_FORCEINLINE uint32_t __LW(volatile void *addr) { uint32_t result; __ASM volatile("lw %0, 0(%1)" : "=r"(result) : "r"(addr)); return result; } #if __RISCV_XLEN != 32 /** * \brief Load 64bit value from address (64 bit) * \details Load 64 bit value. * \param [in] addr Address pointer to data * \return value of type uint64_t at (*addr) * \remarks RV64 only macro */ __STATIC_FORCEINLINE uint64_t __LD(volatile void *addr) { uint64_t result; __ASM volatile("ld %0, 0(%1)" : "=r"(result) : "r"(addr)); return result; } #endif /** * \brief Write 8bit value to address (8 bit) * \details Write 8 bit value. * \param [in] addr Address pointer to data * \param [in] val Value to set */ __STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val) { __ASM volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); } /** * \brief Write 16bit value to address (16 bit) * \details Write 16 bit value. * \param [in] addr Address pointer to data * \param [in] val Value to set */ __STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val) { __ASM volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); } /** * \brief Write 32bit value to address (32 bit) * \details Write 32 bit value. * \param [in] addr Address pointer to data * \param [in] val Value to set */ __STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val) { __ASM volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); } #if __RISCV_XLEN != 32 /** * \brief Write 64bit value to address (64 bit) * \details Write 64 bit value. * \param [in] addr Address pointer to data * \param [in] val Value to set */ __STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val) { __ASM volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); } #endif /** * \brief Compare and Swap 32bit value using LR and SC * \details Compare old value with memory, if identical, * store new value in memory. Return the initial value in memory. * Success is indicated by comparing return value with OLD. * memory address, return 0 if successful, otherwise return !0 * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] oldval Old value of the data in address * \param [in] newval New value to be stored into the address * \return return the initial value in memory */ __STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval) { uint32_t result; uint32_t rc; __ASM volatile("0: lr.w %0, %2 \n" " bne %0, %z3, 1f \n" " sc.w %1, %z4, %2 \n" " bnez %1, 0b \n" "1:\n" : "=&r"(result), "=&r"(rc), "+A"(*addr) : "r"(oldval), "r"(newval) : "memory"); return result; } /** * \brief Atomic Swap 32bit value into memory * \details Atomically swap new 32bit value into memory using amoswap.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] newval New value to be stored into the address * \return return the original value in memory */ __STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) { uint32_t result; __ASM volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); return result; } /** * \brief Atomic Add with 32bit value * \details Atomically ADD 32bit value with value in memory using amoadd.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be ADDed * \return return memory value + add value */ __STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic And with 32bit value * \details Atomically AND 32bit value with value in memory using amoand.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be ANDed * \return return memory value & and value */ __STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic OR with 32bit value * \details Atomically OR 32bit value with value in memory using amoor.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be ORed * \return return memory value | and value */ __STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic XOR with 32bit value * \details Atomically XOR 32bit value with value in memory using amoxor.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be XORed * \return return memory value ^ and value */ __STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic unsigned MAX with 32bit value * \details Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be compared * \return return the bigger value */ __STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) { uint32_t result; __ASM volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic signed MAX with 32bit value * \details Atomically signed max compare 32bit value with value in memory using amomax.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be compared * \return the bigger value */ __STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic unsigned MIN with 32bit value * \details Atomically unsigned min compare 32bit value with value in memory using amominu.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be compared * \return the smaller value */ __STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) { uint32_t result; __ASM volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic signed MIN with 32bit value * \details Atomically signed min compare 32bit value with value in memory using amomin.d. * \param [in] addr Address pointer to data, address need to be 4byte aligned * \param [in] value value to be compared * \return the smaller value */ __STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) { int32_t result; __ASM volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } #if __RISCV_XLEN == 64 /** * \brief Compare and Swap 64bit value using LR and SC * \details Compare old value with memory, if identical, * store new value in memory. Return the initial value in memory. * Success is indicated by comparing return value with OLD. * memory address, return 0 if successful, otherwise return !0 * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] oldval Old value of the data in address * \param [in] newval New value to be stored into the address * \return return the initial value in memory */ __STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval) { register uint64_t result; register uint64_t rc; __ASM volatile("0: lr.d %0, %2 \n" " bne %0, %z3, 1f \n" " sc.d %1, %z4, %2 \n" " bnez %1, 0b \n" "1:\n" : "=&r"(result), "=&r"(rc), "+A"(*addr) : "r"(oldval), "r"(newval) : "memory"); return result; } /** * \brief Atomic Swap 64bit value into memory * \details Atomically swap new 64bit value into memory using amoswap.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] newval New value to be stored into the address * \return return the original value in memory */ __STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval) { register uint64_t result; __ASM volatile("amoswap.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); return result; } /** * \brief Atomic Add with 64bit value * \details Atomically ADD 64bit value with value in memory using amoadd.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be ADDed * \return return memory value + add value */ __STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amoadd.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic And with 64bit value * \details Atomically AND 64bit value with value in memory using amoand.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be ANDed * \return return memory value & and value */ __STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amoand.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic OR with 64bit value * \details Atomically OR 64bit value with value in memory using amoor.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be ORed * \return return memory value | and value */ __STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amoor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic XOR with 64bit value * \details Atomically XOR 64bit value with value in memory using amoxor.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be XORed * \return return memory value ^ and value */ __STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amoxor.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic unsigned MAX with 64bit value * \details Atomically unsigned max compare 64bit value with value in memory using amomaxu.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be compared * \return return the bigger value */ __STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value) { register uint64_t result; __ASM volatile("amomaxu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic signed MAX with 64bit value * \details Atomically signed max compare 64bit value with value in memory using amomax.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be compared * \return the bigger value */ __STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amomax.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic unsigned MIN with 64bit value * \details Atomically unsigned min compare 64bit value with value in memory using amominu.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be compared * \return the smaller value */ __STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value) { register uint64_t result; __ASM volatile("amominu.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } /** * \brief Atomic signed MIN with 64bit value * \details Atomically signed min compare 64bit value with value in memory using amomin.d. * \param [in] addr Address pointer to data, address need to be 8byte aligned * \param [in] value value to be compared * \return the smaller value */ __STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value) { register int64_t result; __ASM volatile("amomin.d %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); return *addr; } #endif /* __RISCV_XLEN == 64 */ /** @} */ /* End of Doxygen Group NMSIS_Core_CPU_Intrinsic */ #ifdef __cplusplus } #endif #endif /* __CORE_FEATURE_BASE__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_cache.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_CACHE_H__ #define __CORE_FEATURE_CACHE_H__ /*! * @file core_feature_cache.h * @brief Cache feature API header file for Nuclei N/NX Core */ /* * Cache Feature Configuration Macro: * 1. __ICACHE_PRESENT: Define whether I-Cache Unit is present or not. * * 0: Not present * * 1: Present * 1. __DCACHE_PRESENT: Define whether D-Cache Unit is present or not. * * 0: Not present * * 1: Present */ #ifdef __cplusplus extern "C" { #endif #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) /* ########################## Cache functions #################################### */ /** * \defgroup NMSIS_Core_Cache Cache Functions * \brief Functions that configure Instruction and Data Cache. * @{ */ /** @} */ /* End of Doxygen Group NMSIS_Core_Cache */ /** * \defgroup NMSIS_Core_ICache I-Cache Functions * \ingroup NMSIS_Core_Cache * \brief Functions that configure Instruction Cache. * @{ */ /** * \brief Enable ICache * \details * This function enable I-Cache * \remarks * - This \ref CSR_MCACHE_CTL register control I Cache enable. * \sa * - \ref DisableICache */ __STATIC_FORCEINLINE void EnableICache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); } /** * \brief Disable ICache * \details * This function Disable I-Cache * \remarks * - This \ref CSR_MCACHE_CTL register control I Cache enable. * \sa * - \ref EnableICache */ __STATIC_FORCEINLINE void DisableICache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE); } /** @} */ /* End of Doxygen Group NMSIS_Core_ICache */ #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */ #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) /** * \defgroup NMSIS_Core_DCache D-Cache Functions * \ingroup NMSIS_Core_Cache * \brief Functions that configure Data Cache. * @{ */ /** * \brief Enable DCache * \details * This function enable D-Cache * \remarks * - This \ref CSR_MCACHE_CTL register control D Cache enable. * \sa * - \ref DisableDCache */ __STATIC_FORCEINLINE void EnableDCache(void) { __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); } /** * \brief Disable DCache * \details * This function Disable D-Cache * \remarks * - This \ref CSR_MCACHE_CTL register control D Cache enable. * \sa * - \ref EnableDCache */ __STATIC_FORCEINLINE void DisableDCache(void) { __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE); } /** @} */ /* End of Doxygen Group NMSIS_Core_DCache */ #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */ #ifdef __cplusplus } #endif #endif /** __CORE_FEATURE_CACHE_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_dsp.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_DSP__ #define __CORE_FEATURE_DSP__ /*! * @file core_feature_dsp.h * @brief DSP feature API header file for Nuclei N/NX Core */ /* * DSP Feature Configuration Macro: * 1. __DSP_PRESENT: Define whether Digital Signal Processing Unit(DSP) is present or not * * 0: Not present * * 1: Present */ #ifdef __cplusplus extern "C" { #endif #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) /* ########################### CPU SIMD DSP Intrinsic Functions ########################### */ /** * \defgroup NMSIS_Core_DSP_Intrinsic Intrinsic Functions for SIMD Instructions * \ingroup NMSIS_Core * \brief Functions that generate RISC-V DSP SIMD instructions. * \details * * The following functions generate specified RISC-V SIMD instructions that cannot be directly accessed by compiler. * * **DSP ISA Extension Instruction Summary** * + **Shorthand Definitions** * - r.H == rH1: r[31:16], r.L == r.H0: r[15:0] * - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0] * - r.B[x]: r[(x*8+7):(x*8+0)] * - r.H[x]: r[(x*16+7):(x*16+0)] * - r.W[x]: r[(x*32+31):(x*32+0)] * - r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains this upper part 32-bit value. * - r[xL]: the lower 32-bit of a 64-bit number; xL represents the GPR number that contains this lower part 32-bit value. * - r[xU].r[xL]: a 64-bit number that is formed from a pair of GPRs. * - s>>: signed arithmetic right shift: * - u>>: unsigned logical right shift * - SAT.Qn(): Saturate to the range of [-2^n, 2^n-1], if saturation happens, set PSW.OV. * - SAT.Um(): Saturate to the range of [0, 2^m-1], if saturation happens, set PSW.OV. * - RUND(): Indicate `rounding`, i.e., add 1 to the most significant discarded bit for right shift or MSW-type multiplication instructions. * - Sign or Zero Extending functions: * - SEm(data): Sign-Extend data to m-bit.: * - ZEm(data): Zero-Extend data to m-bit. * - ABS(x): Calculate the absolute value of `x`. * - CONCAT(x,y): Concatinate `x` and `y` to form a value. * - u<: Unsinged less than comparison. * - u<=: Unsinged less than & equal comparison. * - u>: Unsinged greater than comparison. * - s*: Signed multiplication. * - u*: Unsigned multiplication. * * @{ */ /** @} */ /* End of Doxygen Group NMSIS_Core_DSP_Intrinsic */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS SIMD Data Processing Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief SIMD Data Processing Instructions * \details */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB SIMD 16-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 16-bit Add/Subtract Instructions * \details * Based on the combination of the types of the two 16-bit arithmetic operations, the SIMD 16-bit * add/subtract instructions can be classified into 6 main categories: Addition (two 16-bit addition), * Subtraction (two 16-bit subtraction), Crossed Add & Sub (one addition and one subtraction), and * Crossed Sub & Add (one subtraction and one addition), Straight Add & Sub (one addition and one * subtraction), and Straight Sub & Add (one subtraction and one addition). * Based on the way of how an overflow condition is handled, the SIMD 16-bit add/subtract * instructions can be classified into 5 groups: Wrap-around (dropping overflow), Signed Halving * (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed Saturation (clipping overflow), * and Unsigned Saturation. * Together, there are 30 SIMD 16-bit add/subtract instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB SIMD 8-bit Addition & Subtraction Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Addition & Subtraction Instructions * \details * Based on the types of the four 8-bit arithmetic operations, the SIMD 8-bit add/subtract instructions * can be classified into 2 main categories: Addition (four 8-bit addition), and Subtraction (four 8-bit * subtraction). * Based on the way of how an overflow condition is handled for singed or unsigned operation, the * SIMD 8-bit add/subtract instructions can be classified into 5 groups: Wrap-around (dropping * overflow), Signed Halving (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed * Saturation (clipping overflow), and Unsigned Saturation. * Together, there are 10 SIMD 8-bit add/subtract instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT SIMD 16-bit Shift Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 16-bit Shift Instructions * \details * there are 14 SIMD 16-bit shift instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT SIMD 8-bit Shift Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Shift Instructions * \details * there are 14 SIMD 8-bit shift instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP SIMD 16-bit Compare Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 16-bit Compare Instructions * \details * there are 5 SIMD 16-bit Compare instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP SIMD 8-bit Compare Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Compare Instructions * \details * there are 5 SIMD 8-bit Compare instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY SIMD 16-bit Multiply Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 16-bit Multiply Instructions * \details * there are 6 SIMD 16-bit Multiply instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY SIMD 8-bit Multiply Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Multiply Instructions * \details * there are 6 SIMD 8-bit Multiply instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC SIMD 16-bit Miscellaneous Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 16-bit Miscellaneous Instructions * \details * there are 10 SIMD 16-bit Misc instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC SIMD 8-bit Miscellaneous Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Miscellaneous Instructions * \details * there are 10 SIMD 8-bit Miscellaneous instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK SIMD 8-bit Unpacking Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS * \brief SIMD 8-bit Unpacking Instructions * \details * there are 8 SIMD 8-bit Unpacking instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD Non-SIMD Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief Non-SIMD Instructions * \details */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU Non-SIMD Q15 saturation ALU Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD * \brief Non-SIMD Q15 saturation ALU Instructions * \details * there are 7 Non-SIMD Q15 saturation ALU Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU Non-SIMD Q31 saturation ALU Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD * \brief Non-SIMD Q31 saturation ALU Instructions * \details * there are Non-SIMD Q31 saturation ALU Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION 32-bit Computation Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD * \brief 32-bit Computation Instructions * \details * there are 8 32-bit Computation Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC OV (Overflow) flag Set/Clear Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD * \brief OV (Overflow) flag Set/Clear Instructions * \details * The following table lists the user instructions related to Overflow (OV) flag manipulation. there are 2 OV (Overflow) flag Set/Clear Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC Non-SIMD Miscellaneous Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD * \brief Non-SIMD Miscellaneous Instructions * \details * There are 13 Miscellaneous Instructions here. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS Partial-SIMD Data Processing Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief Partial-SIMD Data Processing Instructions * \details */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK SIMD 16-bit Packing Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief SIMD 16-bit Packing Instructions * \details * there are 4 SIMD16-bit Packing Instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC Signed MSW 32x32 Multiply and Add Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief Signed MSW 32x32 Multiply and Add Instructions * \details * there are 8 Signed MSW 32x32 Multiply and Add Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC Signed MSW 32x16 Multiply and Add Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief Signed MSW 32x16 Multiply and Add Instructions * \details * there are 15 Signed MSW 32x16 Multiply and Add Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB Signed 16-bit Multiply 32-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief Signed 16-bit Multiply 32-bit Add/Subtract Instructions * \details * there are 18 Signed 16-bit Multiply 32-bit Add/Subtract Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB Signed 16-bit Multiply 64-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief Signed 16-bit Multiply 64-bit Add/Subtract Instructions * \details * there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC Partial-SIMD Miscellaneous Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief Partial-SIMD Miscellaneous Instructions * \details * there are 7 Partial-SIMD Miscellaneous Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD 8-bit Multiply with 32-bit Add Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS * \brief 8-bit Multiply with 32-bit Add Instructions * \details * there are 3 8-bit Multiply with 32-bit Add Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE 64-bit Profile Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief 64-bit Profile Instructions * \details */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB 64-bit Addition & Subtraction Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE * \brief 64-bit Addition & Subtraction Instructions * \details * there are 10 64-bit Addition & Subtraction Instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB 32-bit Multiply with 64-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE * \brief 32-bit Multiply with 64-bit Add/Subtract Instructions * \details * there are 32-bit Multiply 64-bit Add/Subtract Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB Signed 16-bit Multiply with 64-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE * \brief Signed 16-bit Multiply with 64-bit Add/Subtract Instructions * \details * there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY RV64 Only Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief RV64 Only Instructions * \details */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB (RV64 Only) SIMD 32-bit Add/Subtract Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) SIMD 32-bit Add/Subtract Instructions * \details * The following tables list instructions that are only present in RV64. * There are 30 SIMD 32-bit addition or subtraction instructions.there are 4 SIMD16-bit Packing Instructions. */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT (RV64 Only) SIMD 32-bit Shift Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) SIMD 32-bit Shift Instructions * \details * there are 14 (RV64 Only) SIMD 32-bit Shift Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC (RV64 Only) SIMD 32-bit Miscellaneous Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) SIMD 32-bit Miscellaneous Instructions * \details * there are 5 (RV64 Only) SIMD 32-bit Miscellaneous Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT (RV64 Only) SIMD Q15 Saturating Multiply Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) SIMD Q15 Saturating Multiply Instructions * \details * there are 9 (RV64 Only) SIMD Q15 saturating Multiply Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT (RV64 Only) 32-bit Multiply Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) 32-bit Multiply Instructions * \details * there is 3 RV64 Only) 32-bit Multiply Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD (RV64 Only) 32-bit Multiply & Add Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) 32-bit Multiply & Add Instructions * \details * there are 3 (RV64 Only) 32-bit Multiply & Add Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC (RV64 Only) 32-bit Parallel Multiply & Add Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) 32-bit Parallel Multiply & Add Instructions * \details * there are 12 (RV64 Only) 32-bit Parallel Multiply & Add Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT (RV64 Only) Non-SIMD 32-bit Shift Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief (RV64 Only) Non-SIMD 32-bit Shift Instructions * \details * there are 1 (RV64 Only) Non-SIMD 32-bit Shift Instructions */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK 32-bit Packing Instructions * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY * \brief 32-bit Packing Instructions * \details * There are four 32-bit packing instructions here */ /* ===== Inline Function Start for 3.1. ADD8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief ADD8 (SIMD 8-bit Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * ADD8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit integer element additions simultaneously. * * **Description**:\n * This instruction adds the 8-bit integer elements in Rs1 with the 8-bit integer elements * in Rs2, and then writes the 8-bit element results to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned addition. * * **Operations**:\n * ~~~ * Rd.B[x] = Rs1.B[x] + Rs2.B[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ADD8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("add8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.1. ADD8 ===== */ /* ===== Inline Function Start for 3.2. ADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief ADD16 (SIMD 16-bit Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * ADD16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element additions simultaneously. * * **Description**:\n * This instruction adds the 16-bit integer elements in Rs1 with the 16-bit integer * elements in Rs2, and then writes the 16-bit element results to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned addition. * * **Operations**:\n * ~~~ * Rd.H[x] = Rs1.H[x] + Rs2.H[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ADD16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("add16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.2. ADD16 ===== */ /* ===== Inline Function Start for 3.3. ADD64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief ADD64 (64-bit Addition) * \details * **Type**: 64-bit Profile * * **Syntax**:\n * ~~~ * ADD64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add two 64-bit signed or unsigned integers. * * **RV32 Description**:\n * This instruction adds the 64-bit integer of an even/odd pair of registers specified * by Rs1(4,1) with the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1), and then * writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction has the same behavior as the ADD instruction in RV64I. * * **Note**:\n * This instruction can be used for either signed or unsigned addition. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * R[t_H].R[t_L] = R[a_H].R[a_L] + R[b_H].R[b_L]; * RV64: * Rd = Rs1 + Rs2; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_ADD64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("add64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.3. ADD64 ===== */ /* ===== Inline Function Start for 3.4. AVE ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief AVE (Average with Rounding) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * AVE Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Calculate the average of the contents of two general registers. * * **Description**:\n * This instruction calculates the average value of two signed integers stored in Rs1 and * Rs2, rounds up a half-integer result to the nearest integer, and writes the result to Rd. * * **Operations**:\n * ~~~ * Sum = CONCAT(Rs1[MSB],Rs1[MSB:0]) + CONCAT(Rs2[MSB],Rs2[MSB:0]) + 1; * Rd = Sum[(MSB+1):1]; * for RV32: MSB=31, * for RV64: MSB=63 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_AVE(long a, long b) { register long result; __ASM volatile("ave %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.4. AVE ===== */ /* ===== Inline Function Start for 3.5. BITREV ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief BITREV (Bit Reverse) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * BITREV Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Reverse the bit positions of the source operand within a specified width starting from bit * 0. The reversed width is a variable from a GPR. * * **Description**:\n * This instruction reverses the bit positions of the content of Rs1. The reversed bit width * is calculated as Rs2[4:0]+1 (RV32) or Rs2[5:0]+1 (RV64). The upper bits beyond the reversed width * are filled with zeros. After the bit reverse operation, the result is written to Rd. * * **Operations**:\n * ~~~ * msb = Rs2[4:0]; (for RV32) * msb = Rs2[5:0]; (for RV64) * rev[0:msb] = Rs1[msb:0]; * Rd = ZE(rev[msb:0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_BITREV(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("bitrev %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.5. BITREV ===== */ /* ===== Inline Function Start for 3.6. BITREVI ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief BITREVI (Bit Reverse Immediate) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * (RV32) BITREVI Rd, Rs1, imm[4:0] * (RV64) BITREVI Rd, Rs1, imm[5:0] * ~~~ * * **Purpose**:\n * Reverse the bit positions of the source operand within a specified width starting from bit * 0. The reversed width is an immediate value. * * **Description**:\n * This instruction reverses the bit positions of the content of Rs1. The reversed bit width * is calculated as imm[4:0]+1 (RV32) or imm[5:0]+1 (RV64). The upper bits beyond the reversed width * are filled with zeros. After the bit reverse operation, the result is written to Rd. * * **Operations**:\n * ~~~ * msb = imm[4:0]; (RV32) * msb = imm[5:0]; (RV64) * rev[0:msb] = Rs1[msb:0]; * Rd = ZE(rev[msb:0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ #define __RV_BITREVI(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("bitrevi %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.6. BITREVI ===== */ /* ===== Inline Function Start for 3.7. BPICK ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief BPICK (Bit-wise Pick) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * BPICK Rd, Rs1, Rs2, Rc * ~~~ * * **Purpose**:\n * Select from two source operands based on a bit mask in the third operand. * * **Description**:\n * This instruction selects individual bits from Rs1 or Rs2, based on the bit mask value in * Rc. If a bit in Rc is 1, the corresponding bit is from Rs1; otherwise, the corresponding bit is from Rs2. * The selection results are written to Rd. * * **Operations**:\n * ~~~ * Rd[x] = Rc[x]? Rs1[x] : Rs2[x]; * for RV32, x=31...0 * for RV64, x=63...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \param [in] c unsigned long type of value stored in c * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_BPICK(unsigned long a, unsigned long b, unsigned long c) { register unsigned long result; __ASM volatile("bpick %0, %1, %2, %3" : "=r"(result) : "r"(a), "r"(b), "r"(c)); return result; } /* ===== Inline Function End for 3.7. BPICK ===== */ /* ===== Inline Function Start for 3.8. CLROV ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC * \brief CLROV (Clear OV flag) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * CLROV # pseudo mnemonic * ~~~ * * **Purpose**:\n * This pseudo instruction is an alias to `CSRRCI x0, ucode, 1` instruction. * * */ __STATIC_FORCEINLINE void __RV_CLROV(void) { __ASM volatile("clrov "); } /* ===== Inline Function End for 3.8. CLROV ===== */ /* ===== Inline Function Start for 3.9. CLRS8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief CLRS8 (SIMD 8-bit Count Leading Redundant Sign) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLRS8 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of redundant sign bits of the 8-bit elements of a general register. * * **Description**:\n * Starting from the bits next to the sign bits of the 8-bit elements of Rs1, this instruction * counts the number of redundant sign bits and writes the result to the corresponding 8-bit elements * of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.B[x]; * cnt[x] = 0; * for (i = 6 to 0) { * if (snum[x](i) == snum[x](7)) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.B[x] = cnt[x]; * for RV32: x=3...0 * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLRS8(unsigned long a) { register unsigned long result; __ASM volatile("clrs8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.9. CLRS8 ===== */ /* ===== Inline Function Start for 3.10. CLRS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief CLRS16 (SIMD 16-bit Count Leading Redundant Sign) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLRS16 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of redundant sign bits of the 16-bit elements of a general register. * * **Description**:\n * Starting from the bits next to the sign bits of the 16-bit elements of Rs1, this * instruction counts the number of redundant sign bits and writes the result to the corresponding 16- * bit elements of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.H[x]; * cnt[x] = 0; * for (i = 14 to 0) { * if (snum[x](i) == snum[x](15)) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.H[x] = cnt[x]; * for RV32: x=1...0 * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLRS16(unsigned long a) { register unsigned long result; __ASM volatile("clrs16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.10. CLRS16 ===== */ /* ===== Inline Function Start for 3.11. CLRS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief CLRS32 (SIMD 32-bit Count Leading Redundant Sign) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLRS32 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of redundant sign bits of the 32-bit elements of a general register. * * **Description**:\n * Starting from the bits next to the sign bits of the 32-bit elements of Rs1, this * instruction counts the number of redundant sign bits and writes the result to the corresponding 32- * bit elements of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.W[x]; * cnt[x] = 0; * for (i = 30 to 0) { * if (snum[x](i) == snum[x](31)) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.W[x] = cnt[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLRS32(unsigned long a) { register unsigned long result; __ASM volatile("clrs32 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.11. CLRS32 ===== */ /* ===== Inline Function Start for 3.12. CLO8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief CLO8 (SIMD 8-bit Count Leading One) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLO8 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading one bits of the 8-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction * counts the number of leading one bits and writes the results to the corresponding 8-bit elements of * Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.B[x]; * cnt[x] = 0; * for (i = 7 to 0) { * if (snum[x](i) == 1) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.B[x] = cnt[x]; * for RV32: x=3...0 * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLO8(unsigned long a) { register unsigned long result; __ASM volatile("clo8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.12. CLO8 ===== */ /* ===== Inline Function Start for 3.13. CLO16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief CLO16 (SIMD 16-bit Count Leading One) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLO16 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading one bits of the 16-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction * counts the number of leading one bits and writes the results to the corresponding 16-bit elements * of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.H[x]; * cnt[x] = 0; * for (i = 15 to 0) { * if (snum[x](i) == 1) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.H[x] = cnt[x]; * for RV32: x=1...0 * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLO16(unsigned long a) { register unsigned long result; __ASM volatile("clo16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.13. CLO16 ===== */ /* ===== Inline Function Start for 3.14. CLO32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief CLO32 (SIMD 32-bit Count Leading One) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLO32 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading one bits of the 32-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction * counts the number of leading one bits and writes the results to the corresponding 32-bit elements * of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.W[x]; * cnt[x] = 0; * for (i = 31 to 0) { * if (snum[x](i) == 1) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.W[x] = cnt[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLO32(unsigned long a) { register unsigned long result; __ASM volatile("clo32 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.14. CLO32 ===== */ /* ===== Inline Function Start for 3.15. CLZ8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief CLZ8 (SIMD 8-bit Count Leading Zero) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLZ8 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading zero bits of the 8-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction * counts the number of leading zero bits and writes the results to the corresponding 8-bit elements of * Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.B[x]; * cnt[x] = 0; * for (i = 7 to 0) { * if (snum[x](i) == 0) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.B[x] = cnt[x]; * for RV32: x=3...0 * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLZ8(unsigned long a) { register unsigned long result; __ASM volatile("clz8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.15. CLZ8 ===== */ /* ===== Inline Function Start for 3.16. CLZ16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief CLZ16 (SIMD 16-bit Count Leading Zero) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLZ16 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading zero bits of the 16-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction * counts the number of leading zero bits and writes the results to the corresponding 16-bit elements * of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.H[x]; * cnt[x] = 0; * for (i = 15 to 0) { * if (snum[x](i) == 0) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.H[x] = cnt[x]; * for RV32: x=1...0 * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLZ16(unsigned long a) { register unsigned long result; __ASM volatile("clz16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.16. CLZ16 ===== */ /* ===== Inline Function Start for 3.17. CLZ32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief CLZ32 (SIMD 32-bit Count Leading Zero) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CLZ32 Rd, Rs1 * ~~~ * * **Purpose**:\n * Count the number of leading zero bits of the 32-bit elements of a general register. * * **Description**:\n * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction * counts the number of leading zero bits and writes the results to the corresponding 32-bit elements * of Rd. * * **Operations**:\n * ~~~ * snum[x] = Rs1.W[x]; * cnt[x] = 0; * for (i = 31 to 0) { * if (snum[x](i) == 0) { * cnt[x] = cnt[x] + 1; * } else { * break; * } * } * Rd.W[x] = cnt[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CLZ32(unsigned long a) { register unsigned long result; __ASM volatile("clz32 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.17. CLZ32 ===== */ /* ===== Inline Function Start for 3.18. CMPEQ8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP * \brief CMPEQ8 (SIMD 8-bit Integer Compare Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CMPEQ8 Rs, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit integer elements equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 8-bit integer elements in Rs1 with the 8-bit integer * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFF; otherwise, the result is * 0x0. The 8-bit element comparison results are written to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned numbers. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] == Rs2.B[x])? 0xff : 0x0; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CMPEQ8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("cmpeq8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.18. CMPEQ8 ===== */ /* ===== Inline Function Start for 3.19. CMPEQ16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP * \brief CMPEQ16 (SIMD 16-bit Integer Compare Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CMPEQ16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer elements equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 16-bit integer elements in Rs1 with the 16-bit integer * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFFFF; otherwise, the result * is 0x0. The 16-bit element comparison results are written to Rt. * * **Note**:\n * This instruction can be used for either signed or unsigned numbers. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] == Rs2.H[x])? 0xffff : 0x0; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CMPEQ16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("cmpeq16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.19. CMPEQ16 ===== */ /* ===== Inline Function Start for 3.20. CRAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief CRAS16 (SIMD 16-bit Cross Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CRAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit * chunk simultaneously. Operands are from crossed positions in 32-bit chunks. * * **Description**:\n * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with * the 16-bit integer element in [15:0] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [31:16] of 32-bit chunks in * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32- * bit chunks in Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][15:0]; * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][31:16]; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CRAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("cras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.20. CRAS16 ===== */ /* ===== Inline Function Start for 3.21. CRSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief CRSA16 (SIMD 16-bit Cross Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * CRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit * chunk simultaneously. Operands are from crossed positions in 32-bit chunks. * * **Description**:\n * This instruction subtracts the 16-bit integer element in [15:0] of 32-bit chunks in Rs2 * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [31:16] of 32-bit chunks * in Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to * [15:0] of 32-bit chunks in Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][15:0]; * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][31:16]; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CRSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("crsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.21. CRSA16 ===== */ /* ===== Inline Function Start for 3.22. INSB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief INSB (Insert Byte) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * (RV32) INSB Rd, Rs1, imm[1:0] * (RV64) INSB Rd, Rs1, imm[2:0] * ~~~ * * **Purpose**:\n * Insert byte 0 of a 32-bit or 64-bit register into one of the byte elements of another register. * * **Description**:\n * This instruction inserts byte 0 of Rs1 into byte `imm[1:0]` (RV32) or `imm[2:0]` (RV64) * of Rd. * * **Operations**:\n * ~~~ * bpos = imm[1:0]; (RV32) * bpos = imm[2:0]; (RV64) * Rd.B[bpos] = Rs1.B[0] * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ #define __RV_INSB(t, a, b) \ ({ \ register unsigned long __t = (unsigned long)(t); \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("insb %0, %1, %2" : "+r"(__t) : "r"(__a), "K"(b)); \ __t; \ }) /* ===== Inline Function End for 3.22. INSB ===== */ /* ===== Inline Function Start for 3.23. KABS8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief KABS8 (SIMD 8-bit Saturating Absolute) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KABS8 Rd, Rs1 * ~~~ * * **Purpose**:\n * Get the absolute value of 8-bit signed integer elements simultaneously. * * **Description**:\n * This instruction calculates the absolute value of 8-bit signed integer elements stored * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates * 0x7f as the output and sets the OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.B[x]; * if (src == 0x80) { * src = 0x7f; * OV = 1; * } else if (src[7] == 1) * src = -src; * } * Rd.B[x] = src; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KABS8(unsigned long a) { register unsigned long result; __ASM volatile("kabs8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.23. KABS8 ===== */ /* ===== Inline Function Start for 3.24. KABS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief KABS16 (SIMD 16-bit Saturating Absolute) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KABS16 Rd, Rs1 * ~~~ * * **Purpose**:\n * Get the absolute value of 16-bit signed integer elements simultaneously. * * **Description**:\n * This instruction calculates the absolute value of 16-bit signed integer elements stored * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction * generates 0x7fff as the output and sets the OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.H[x]; * if (src == 0x8000) { * src = 0x7fff; * OV = 1; * } else if (src[15] == 1) * src = -src; * } * Rd.H[x] = src; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KABS16(unsigned long a) { register unsigned long result; __ASM volatile("kabs16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.24. KABS16 ===== */ /* ===== Inline Function Start for 3.25. KABSW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KABSW (Scalar 32-bit Absolute Value with Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KABSW Rd, Rs1 * ~~~ * * **Purpose**:\n * Get the absolute value of a signed 32-bit integer in a general register. * * **Description**:\n * This instruction calculates the absolute value of a signed 32-bit integer stored in Rs1. * The result is sign-extended (for RV64) and written to Rd. This instruction with the minimum * negative integer input of 0x80000000 will produce a saturated output of maximum positive integer * of 0x7fffffff and the OV flag will be set to 1. * * **Operations**:\n * ~~~ * if (Rs1.W[0] >= 0) { * res = Rs1.W[0]; * } else { * If (Rs1.W[0] == 0x80000000) { * res = 0x7fffffff; * OV = 1; * } else { * res = -Rs1.W[0]; * } * } * Rd = SE32(res); * ~~~ * * \param [in] a signed long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KABSW(signed long a) { register unsigned long result; __ASM volatile("kabsw %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.25. KABSW ===== */ /* ===== Inline Function Start for 3.26. KADD8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief KADD8 (SIMD 8-bit Signed Saturating Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KADD8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.B[x] + Rs2.B[x]; * if (res[x] > 127) { * res[x] = 127; * OV = 1; * } else if (res[x] < -128) { * res[x] = -128; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KADD8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.26. KADD8 ===== */ /* ===== Inline Function Start for 3.27. KADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KADD16 (SIMD 16-bit Signed Saturating Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KADD16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1), * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] + Rs2.H[x]; * if (res[x] > 32767) { * res[x] = 32767; * OV = 1; * } else if (res[x] < -32768) { * res[x] = -32768; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KADD16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.27. KADD16 ===== */ /* ===== Inline Function Start for 3.28. KADD64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief KADD64 (64-bit Signed Saturating Addition) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * KADD64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add two 64-bit signed integers. The result is saturated to the Q63 range. * * **RV32 Description**:\n * This instruction adds the 64-bit signed integer of an even/odd pair of registers * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by * Rs2(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers * specified by Rd(4,1). * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed * integer in Rs2. If the result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the * range and the OV bit is set to 1. The saturated result is written to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * result = R[a_H].R[a_L] + R[b_H].R[b_L]; * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * R[t_H].R[t_L] = result; * RV64: * result = Rs1 + Rs2; * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * Rd = result; * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b long long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_KADD64(long long a, long long b) { register long long result; __ASM volatile("kadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.28. KADD64 ===== */ /* ===== Inline Function Start for 3.29. KADDH ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief KADDH (Signed Addition with Q15 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KADDH Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add the signed lower 32-bit content of two registers with Q15 saturation. * * **Description**:\n * The signed lower 32-bit content of Rs1 is added with the signed lower 32-bit content of * Rs2. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then sign- * extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] + Rs2.W[0]; * if (tmp > 32767) { * res = 32767; * OV = 1; * } else if (tmp < -32768) { * res = -32768; * OV = 1 * } else { * res = tmp; * } * Rd = SE(tmp[15:0]); * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KADDH(int a, int b) { register long result; __ASM volatile("kaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.29. KADDH ===== */ /* ===== Inline Function Start for 3.30. KADDW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KADDW (Signed Addition with Q31 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KADDW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add the lower 32-bit signed content of two registers with Q31 saturation. * * **Description**:\n * The lower 32-bit signed content of Rs1 is added with the lower 32-bit signed content of * Rs2. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then sign- * extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] + Rs2.W[0]; * if (tmp > (2^31)-1) { * res = (2^31)-1; * OV = 1; * } else if (tmp < -2^31) { * res = -2^31; * OV = 1 * } else { * res = tmp; * } * Rd = res[31:0]; // RV32 * Rd = SE(res[31:0]) // RV64 * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KADDW(int a, int b) { register long result; __ASM volatile("kaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.30. KADDW ===== */ /* ===== Inline Function Start for 3.31. KCRAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KCRAS16 (SIMD 16-bit Signed Saturating Cross Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KCRAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating addition and 16-bit signed integer element * saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32- * bit chunks. * * **Description**:\n * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it * subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for * subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0]; * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16]; * for (res in [res1, res2]) { * if (res > (2^15)-1) { * res = (2^15)-1; * OV = 1; * } else if (res < -2^15) { * res = -2^15; * OV = 1; * } * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KCRAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.31. KCRAS16 ===== */ /* ===== Inline Function Start for 3.32. KCRSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KCRSA16 (SIMD 16-bit Signed Saturating Cross Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KCRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element * saturating addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit * chunks. * * **Description**:\n * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it * adds the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 with the 16-bit signed * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd * for addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0]; * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16]; * for (res in [res1, res2]) { * if (res > (2^15)-1) { * res = (2^15)-1; * OV = 1; * } else if (res < -2^15) { * res = -2^15; * OV = 1; * } * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KCRSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.32. KCRSA16 ===== */ /* ===== Inline Function Start for 3.33.1. KDMBB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMBB (Signed Saturating Double Multiply B16 x B16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is * written into the destination register for RV32 or sign-extended to 64-bits and written into the * destination register for RV64. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be * saturated to 0x7FFFFFFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * } else { * resQ31 = 0x7FFFFFFF; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * OV = 1; * } * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMBB(unsigned int a, unsigned int b) { register long result; __ASM volatile("kdmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.33.1. KDMBB ===== */ /* ===== Inline Function Start for 3.33.2. KDMBT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMBT (Signed Saturating Double Multiply B16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is * written into the destination register for RV32 or sign-extended to 64-bits and written into the * destination register for RV64. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be * saturated to 0x7FFFFFFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * } else { * resQ31 = 0x7FFFFFFF; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * OV = 1; * } * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMBT(unsigned int a, unsigned int b) { register long result; __ASM volatile("kdmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.33.2. KDMBT ===== */ /* ===== Inline Function Start for 3.33.3. KDMTT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMTT (Signed Saturating Double Multiply T16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is * written into the destination register for RV32 or sign-extended to 64-bits and written into the * destination register for RV64. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be * saturated to 0x7FFFFFFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * } else { * resQ31 = 0x7FFFFFFF; * Rd = resQ31; // RV32 * Rd = SE(resQ31); // RV64 * OV = 1; * } * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMTT(unsigned int a, unsigned int b) { register long result; __ASM volatile("kdmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.33.3. KDMTT ===== */ /* ===== Inline Function Start for 3.34.1. KDMABB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMABB (Signed Saturating Double Multiply Addition B16 x B16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result * with the sign-extended lower 32-bit chunk destination register and write the saturated addition * result into the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV flag is set to 1. The result after saturation is written to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * } else { * resQ31 = 0x7FFFFFFF; * OV = 1; * } * resadd = Rd + resQ31; // RV32 * resadd = Rd.W[0] + resQ31; // RV64 * if (resadd > (2^31)-1) { * resadd = (2^31)-1; * OV = 1; * } else if (resadd < -2^31) { * resadd = -2^31; * OV = 1; * } * Rd = resadd; // RV32 * Rd = SE(resadd); // RV64 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMABB(long t, unsigned int a, unsigned int b) { __ASM volatile("kdmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.34.1. KDMABB ===== */ /* ===== Inline Function Start for 3.34.2. KDMABT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMABT (Signed Saturating Double Multiply Addition B16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result * with the sign-extended lower 32-bit chunk destination register and write the saturated addition * result into the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV flag is set to 1. The result after saturation is written to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * } else { * resQ31 = 0x7FFFFFFF; * OV = 1; * } * resadd = Rd + resQ31; // RV32 * resadd = Rd.W[0] + resQ31; // RV64 * if (resadd > (2^31)-1) { * resadd = (2^31)-1; * OV = 1; * } else if (resadd < -2^31) { * resadd = -2^31; * OV = 1; * } * Rd = resadd; // RV32 * Rd = SE(resadd); // RV64 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMABT(long t, unsigned int a, unsigned int b) { __ASM volatile("kdmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.34.2. KDMABT ===== */ /* ===== Inline Function Start for 3.34.3. KDMATT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KDMATT (Signed Saturating Double Multiply Addition T16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result * with the sign-extended lower 32-bit chunk destination register and write the saturated addition * result into the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV flag is set to 1. The result after saturation is written to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT * If (0x8000 != aop | 0x8000 != bop) { * Mresult = aop * bop; * resQ31 = Mresult << 1; * } else { * resQ31 = 0x7FFFFFFF; * OV = 1; * } * resadd = Rd + resQ31; // RV32 * resadd = Rd.W[0] + resQ31; // RV64 * if (resadd > (2^31)-1) { * resadd = (2^31)-1; * OV = 1; * } else if (resadd < -2^31) { * resadd = -2^31; * OV = 1; * } * Rd = resadd; // RV32 * Rd = SE(resadd); // RV64 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KDMATT(long t, unsigned int a, unsigned int b) { __ASM volatile("kdmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.34.3. KDMATT ===== */ /* ===== Inline Function Start for 3.35.1. KHM8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY * \brief KHM8 (SIMD Signed Saturating Q7 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KHM8 Rd, Rs1, Rs2 * KHMX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 * numbers again. * * **Description**:\n * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2. * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. * The result will be saturated to 0x7F and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * if (is `KHM8`) { * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom * } else if (is `KHMX8`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x80 != aop | 0x80 != bop) { * res = (aop s* bop) >> 7; * } else { * res= 0x7F; * OV = 1; * } * } * Rd.H[x/2] = concat(rest, resb); * for RV32, x=0,2 * for RV64, x=0,2,4,6 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHM8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.35.1. KHM8 ===== */ /* ===== Inline Function Start for 3.35.2. KHMX8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY * \brief KHMX8 (SIMD Signed Saturating Crossed Q7 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KHM8 Rd, Rs1, Rs2 * KHMX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 * numbers again. * * **Description**:\n * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2. * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. * The result will be saturated to 0x7F and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * if (is `KHM8`) { * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom * } else if (is `KHMX8`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x80 != aop | 0x80 != bop) { * res = (aop s* bop) >> 7; * } else { * res= 0x7F; * OV = 1; * } * } * Rd.H[x/2] = concat(rest, resb); * for RV32, x=0,2 * for RV64, x=0,2,4,6 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHMX8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khmx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.35.2. KHMX8 ===== */ /* ===== Inline Function Start for 3.36.1. KHM16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY * \brief KHM16 (SIMD Signed Saturating Q15 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KHM16 Rd, Rs1, Rs2 * KHMX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to * Q15 numbers again. * * **Description**:\n * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in * Rs2. * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15 * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * if (is `KHM16`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom * } else if (is `KHMX16`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x8000 != aop | 0x8000 != bop) { * res = (aop s* bop) >> 15; * } else { * res= 0x7FFF; * OV = 1; * } * } * Rd.W[x/2] = concat(rest, resb); * for RV32: x=0 * for RV64: x=0,2 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHM16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.36.1. KHM16 ===== */ /* ===== Inline Function Start for 3.36.2. KHMX16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY * \brief KHMX16 (SIMD Signed Saturating Crossed Q15 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KHM16 Rd, Rs1, Rs2 * KHMX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to * Q15 numbers again. * * **Description**:\n * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in * Rs2. * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15 * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * if (is `KHM16`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom * } else if (is `KHMX16`) { * op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top * op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x8000 != aop | 0x8000 != bop) { * res = (aop s* bop) >> 15; * } else { * res= 0x7FFF; * OV = 1; * } * } * Rd.W[x/2] = concat(rest, resb); * for RV32: x=0 * for RV64: x=0,2 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHMX16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khmx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.36.2. KHMX16 ===== */ /* ===== Inline Function Start for 3.37.1. KHMBB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief KHMBB (Signed Saturating Half Multiply B16 x B16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 * number again and saturate the Q15 result into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd = SE32(res[15:0]); // Rv32 * Rd = SE64(res[15:0]); // RV64 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KHMBB(unsigned int a, unsigned int b) { register long result; __ASM volatile("khmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.37.1. KHMBB ===== */ /* ===== Inline Function Start for 3.37.2. KHMBT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief KHMBT (Signed Saturating Half Multiply B16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 * number again and saturate the Q15 result into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd = SE32(res[15:0]); // Rv32 * Rd = SE64(res[15:0]); // RV64 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KHMBT(unsigned int a, unsigned int b) { register long result; __ASM volatile("khmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.37.2. KHMBT ===== */ /* ===== Inline Function Start for 3.37.3. KHMTT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief KHMTT (Signed Saturating Half Multiply T16 x T16) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15 * number again and saturate the Q15 result into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right- * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd = SE32(res[15:0]); // Rv32 * Rd = SE64(res[15:0]); // RV64 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KHMTT(unsigned int a, unsigned int b) { register long result; __ASM volatile("khmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.37.3. KHMTT ===== */ /* ===== Inline Function Start for 3.38.1. KMABB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMABB (SIMD Saturating Signed Multiply Bottom Halfs & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMABB Rd, Rs1, Rs2 * KMABT Rd, Rs1, Rs2 * KMATT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content * of 32-bit elements in another register and add the result to the content of 32-bit elements in the * third register. The addition result may be saturated and is written to the third register. * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) * * KMABT rd.W[x] + bottom*top (per 32-bit element) * * KMATT rd.W[x] + top*top (per 32-bit element) * * **Description**:\n * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2. * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2. * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2. * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMABB(long t, unsigned long a, unsigned long b) { __ASM volatile("kmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.38.1. KMABB ===== */ /* ===== Inline Function Start for 3.38.2. KMABT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMABT (SIMD Saturating Signed Multiply Bottom & Top Halfs & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMABB Rd, Rs1, Rs2 * KMABT Rd, Rs1, Rs2 * KMATT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content * of 32-bit elements in another register and add the result to the content of 32-bit elements in the * third register. The addition result may be saturated and is written to the third register. * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) * * KMABT rd.W[x] + bottom*top (per 32-bit element) * * KMATT rd.W[x] + top*top (per 32-bit element) * * **Description**:\n * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2. * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2. * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2. * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMABT(long t, unsigned long a, unsigned long b) { __ASM volatile("kmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.38.2. KMABT ===== */ /* ===== Inline Function Start for 3.38.3. KMATT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMATT (SIMD Saturating Signed Multiply Top Halfs & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMABB Rd, Rs1, Rs2 * KMABT Rd, Rs1, Rs2 * KMATT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content * of 32-bit elements in another register and add the result to the content of 32-bit elements in the * third register. The addition result may be saturated and is written to the third register. * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element) * * KMABT rd.W[x] + bottom*top (per 32-bit element) * * KMATT rd.W[x] + top*top (per 32-bit element) * * **Description**:\n * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2. * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2. * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2. * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMATT(long t, unsigned long a, unsigned long b) { __ASM volatile("kmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.38.3. KMATT ===== */ /* ===== Inline Function Start for 3.39.1. KMADA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMADA (SIMD Saturating Signed Multiply Two Halfs and Two Adds) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMADA Rd, Rs1, Rs2 * KMAXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds * the two 32-bit results and 32-bit elements in a third register together. The addition result may be * saturated. * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element) * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element) * * **Description**:\n * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit * elements in Rs2. * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in * Rs2. * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * // KMADA * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMAXDA * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADA(long t, unsigned long a, unsigned long b) { __ASM volatile("kmada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.39.1. KMADA ===== */ /* ===== Inline Function Start for 3.39.2. KMAXDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMAXDA (SIMD Saturating Signed Crossed Multiply Two Halfs and Two Adds) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMADA Rd, Rs1, Rs2 * KMAXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds * the two 32-bit results and 32-bit elements in a third register together. The addition result may be * saturated. * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element) * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element) * * **Description**:\n * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit * elements in Rs2. * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in * Rs2. * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * // KMADA * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMAXDA * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMAXDA(long t, unsigned long a, unsigned long b) { __ASM volatile("kmaxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.39.2. KMAXDA ===== */ /* ===== Inline Function Start for 3.40.1. KMADS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMADS (SIMD Saturating Signed Multiply Two Halfs & Subtract & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMADS Rd, Rs1, Rs2 * KMADRS Rd, Rs1, Rs2 * KMAXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the corresponding 32-bit elements in a third register. The addition result may be saturated. * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) * * **Description**:\n * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit * elements in Rs2. * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- * bit elements in Rs2. * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit * elements in Rs2. * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 * and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * // KMADS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMADRS * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * // KMAXDS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADS(long t, unsigned long a, unsigned long b) { __ASM volatile("kmads %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.40.1. KMADS ===== */ /* ===== Inline Function Start for 3.40.2. KMADRS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMADRS (SIMD Saturating Signed Multiply Two Halfs & Reverse Subtract & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMADS Rd, Rs1, Rs2 * KMADRS Rd, Rs1, Rs2 * KMAXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the corresponding 32-bit elements in a third register. The addition result may be saturated. * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) * * **Description**:\n * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit * elements in Rs2. * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- * bit elements in Rs2. * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit * elements in Rs2. * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 * and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * // KMADS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMADRS * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * // KMAXDS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADRS(long t, unsigned long a, unsigned long b) { __ASM volatile("kmadrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.40.2. KMADRS ===== */ /* ===== Inline Function Start for 3.40.3. KMAXDS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMAXDS (SIMD Saturating Signed Crossed Multiply Two Halfs & Subtract & Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMADS Rd, Rs1, Rs2 * KMADRS Rd, Rs1, Rs2 * KMAXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the corresponding 32-bit elements in a third register. The addition result may be saturated. * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element) * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element) * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element) * * **Description**:\n * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit * elements in Rs2. * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32- * bit elements in Rs2. * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit * elements in Rs2. * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1 * and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * // KMADS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMADRS * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * // KMAXDS * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMAXDS(long t, unsigned long a, unsigned long b) { __ASM volatile("kmaxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.40.3. KMAXDS ===== */ /* ===== Inline Function Start for 3.41. KMAR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief KMAR64 (Signed Multiply and Saturating Add to 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * KMAR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication * results to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by * Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the Q63 number range (-2^63 <= * Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written back * to the even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It * adds the 64-bit multiplication results to the 64-bit signed data of Rd with unlimited precision. If the * 64-bit addition result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range * and the OV bit is set to 1. The saturated result is written back to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * result = R[t_H].R[t_L] + (Rs1 * Rs2); * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * R[t_H].R[t_L] = result; * RV64: * // `result` has unlimited precision * result = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]); * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * Rd = result; * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_KMAR64(long long t, long a, long b) { __ASM volatile("kmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.41. KMAR64 ===== */ /* ===== Inline Function Start for 3.42.1. KMDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMDA (SIMD Signed Multiply Two Halfs and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMDA Rd, Rs1, Rs2 * KMXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * adds the two 32-bit results together. The addition result may be saturated. * * KMDA: top*top + bottom*bottom (per 32-bit element) * * KMXDA: top*bottom + bottom*top (per 32-bit element) * * **Description**:\n * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- * bit elements of Rs2. * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the * 32-bit elements of Rs2. * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1. * The final results are written to Rd. The 16-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * if Rs1.W[x] != 0x80008000) or (Rs2.W[x] != 0x80008000 { // KMDA Rd.W[x] = Rs1.W[x].H[1] * * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0]) * + (Rs1.W[x].H[0] * Rs2.W[x].H[1]; } else { Rd.W[x] = 0x7fffffff; OV = 1; } for RV32: x=0 for RV64: * x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMDA(unsigned long a, unsigned long b) { register long result; __ASM volatile("kmda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.42.1. KMDA ===== */ /* ===== Inline Function Start for 3.42.2. KMXDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMXDA (SIMD Signed Crossed Multiply Two Halfs and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMDA Rd, Rs1, Rs2 * KMXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * adds the two 32-bit results together. The addition result may be saturated. * * KMDA: top*top + bottom*bottom (per 32-bit element) * * KMXDA: top*bottom + bottom*top (per 32-bit element) * * **Description**:\n * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- * bit elements of Rs2. * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the * 32-bit elements of Rs2. * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1. * The final results are written to Rd. The 16-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * if Rs1.W[x] != 0x80008000) or (Rs2.W[x] != 0x80008000 { // KMDA Rd.W[x] = Rs1.W[x].H[1] * * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0]) * + (Rs1.W[x].H[0] * Rs2.W[x].H[1]; } else { Rd.W[x] = 0x7fffffff; OV = 1; } for RV32: x=0 for RV64: * x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMXDA(unsigned long a, unsigned long b) { register long result; __ASM volatile("kmxda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.42.2. KMXDA ===== */ /* ===== Inline Function Start for 3.43.1. KMMAC ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KMMAC (SIMD Saturating MSW Signed Multiply Word and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAC Rd, Rs1, Rs2 * KMMAC.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers and add the most significant * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are * saturated first and then written back to the third register. The `.u` form performs an additional * rounding up operation on the multiplication results before adding the most significant 32-bit part * of the results. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by * adding a 1 to bit 31 of the results. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][63:32]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAC(long t, long a, long b) { __ASM volatile("kmmac %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.43.1. KMMAC ===== */ /* ===== Inline Function Start for 3.43.2. KMMAC.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAC Rd, Rs1, Rs2 * KMMAC.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers and add the most significant * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are * saturated first and then written back to the third register. The `.u` form performs an additional * rounding up operation on the multiplication results before adding the most significant 32-bit part * of the results. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by * adding a 1 to bit 31 of the results. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][63:32]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAC_U(long t, long a, long b) { __ASM volatile("kmmac.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.43.2. KMMAC.u ===== */ /* ===== Inline Function Start for 3.44.1. KMMAWB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWB (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWB Rd, Rs1, Rs2 * KMMAWB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register and add the most significant 32-bit results with * the corresponding signed 32-bit elements of a third register. The addition result is written to the * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication * results from the most significant discarded bit before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to * bit 15 of the result before the addition operations. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][47:16]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWB(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.44.1. KMMAWB ===== */ /* ===== Inline Function Start for 3.44.2. KMMAWB.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWB.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWB Rd, Rs1, Rs2 * KMMAWB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register and add the most significant 32-bit results with * the corresponding signed 32-bit elements of a third register. The addition result is written to the * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication * results from the most significant discarded bit before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to * bit 15 of the result before the addition operations. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][47:16]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWB_U(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.44.2. KMMAWB.u ===== */ /* ===== Inline Function Start for 3.45.1. KMMAWB2 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWB2 Rd, Rs1, Rs2 * KMMAWB2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and add the * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third * register. The saturated addition result is written to the corresponding 32-bit elements of the third * register. The `.u` form rounds up the multiplication results from the most significant discarded bit * before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to the * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of * the result before the addition operations. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { * addop.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; * if (`.u` form) { * Mres[x][47:14] = Mres[x][47:14] + 1; * } * addop.W[x] = Mres[x][46:15]; // doubling * } * res[x] = Rd.W[x] + addop.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWB2(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawb2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.45.1. KMMAWB2 ===== */ /* ===== Inline Function Start for 3.45.2. KMMAWB2.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWB2 Rd, Rs1, Rs2 * KMMAWB2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and add the * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third * register. The saturated addition result is written to the corresponding 32-bit elements of the third * register. The `.u` form rounds up the multiplication results from the most significant discarded bit * before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to the * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of * the result before the addition operations. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { * addop.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; * if (`.u` form) { * Mres[x][47:14] = Mres[x][47:14] + 1; * } * addop.W[x] = Mres[x][46:15]; // doubling * } * res[x] = Rd.W[x] + addop.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWB2_U(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawb2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.45.2. KMMAWB2.u ===== */ /* ===== Inline Function Start for 3.46.1. KMMAWT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWT (SIMD Saturating MSW Signed Multiply Word and Top Half and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWT Rd, Rs1, Rs2 * KMMAWT.u Rd Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the * corresponding 32-bit elements of another register and add the most significant 32-bit results with * the corresponding signed 32-bit elements of a third register. The addition results are written to the * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication * results from the most significant discarded bit before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to * bit 15 of the result before the addition operations. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][47:16]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWT(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.46.1. KMMAWT ===== */ /* ===== Inline Function Start for 3.46.2. KMMAWT.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWT.u (SIMD Saturating MSW Signed Multiply Word and Top Half and Add with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWT Rd, Rs1, Rs2 * KMMAWT.u Rd Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the * corresponding 32-bit elements of another register and add the most significant 32-bit results with * the corresponding signed 32-bit elements of a third register. The addition results are written to the * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication * results from the most significant discarded bit before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to * bit 15 of the result before the addition operations. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * res[x] = Rd.W[x] + Round[x][32:1]; * } else { * res[x] = Rd.W[x] + Mres[x][47:16]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWT_U(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawt.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.46.2. KMMAWT.u ===== */ /* ===== Inline Function Start for 3.47.1. KMMAWT2 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWT2 Rd, Rs1, Rs2 * KMMAWT2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and add the * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third * register. The saturated addition result is written to the corresponding 32-bit elements of the third * register. The `.u` form rounds up the multiplication results from the most significant discarded bit * before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to the * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of * the result before the addition operations. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { * addop.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; * if (`.u` form) { * Mres[x][47:14] = Mres[x][47:14] + 1; * } * addop.W[x] = Mres[x][46:15]; // doubling * } * res[x] = Rd.W[x] + addop.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWT2(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawt2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.47.1. KMMAWT2 ===== */ /* ===== Inline Function Start for 3.47.2. KMMAWT2.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMAWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMAWT2 Rd, Rs1, Rs2 * KMMAWT2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and add the * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third * register. The saturated addition result is written to the corresponding 32-bit elements of the third * register. The `.u` form rounds up the multiplication results from the most significant discarded bit * before the addition operations. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to the * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of * the result before the addition operations. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { * addop.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; * if (`.u` form) { * Mres[x][47:14] = Mres[x][47:14] + 1; * } * addop.W[x] = Mres[x][46:15]; // doubling * } * res[x] = Rd.W[x] + addop.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMAWT2_U(long t, unsigned long a, unsigned long b) { __ASM volatile("kmmawt2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.47.2. KMMAWT2.u ===== */ /* ===== Inline Function Start for 3.48.1. KMMSB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMSB Rd, Rs1, Rs2 * KMMSB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers and subtract the most * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results * are written to the third register. The `.u` form performs an additional rounding up operation on * the multiplication results before subtracting the most significant 32-bit part of the results. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by * adding a 1 to bit 31 of the results. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * res[x] = Rd.W[x] - Round[x][32:1]; * } else { * res[x] = Rd.W[x] - Mres[x][63:32]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMSB(long t, long a, long b) { __ASM volatile("kmmsb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.48.1. KMMSB ===== */ /* ===== Inline Function Start for 3.48.2. KMMSB.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMSB Rd, Rs1, Rs2 * KMMSB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers and subtract the most * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results * are written to the third register. The `.u` form performs an additional rounding up operation on * the multiplication results before subtracting the most significant 32-bit part of the results. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by * adding a 1 to bit 31 of the results. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * res[x] = Rd.W[x] - Round[x][32:1]; * } else { * res[x] = Rd.W[x] - Mres[x][63:32]; * } * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMSB_U(long t, long a, long b) { __ASM volatile("kmmsb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.48.2. KMMSB.u ===== */ /* ===== Inline Function Start for 3.49.1. KMMWB2 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMWB2 Rd, Rs1, Rs2 * KMMWB2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and write the * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` * form rounds up the results from the most significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { * Rd.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][46:14] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][46:15]; * } * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMWB2(long a, unsigned long b) { register long result; __ASM volatile("kmmwb2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.49.1. KMMWB2 ===== */ /* ===== Inline Function Start for 3.49.2. KMMWB2.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMWB2 Rd, Rs1, Rs2 * KMMWB2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and write the * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` * form rounds up the results from the most significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) { * Rd.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][46:14] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][46:15]; * } * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMWB2_U(long a, unsigned long b) { register long result; __ASM volatile("kmmwb2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.49.2. KMMWB2.u ===== */ /* ===== Inline Function Start for 3.50.1. KMMWT2 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMWT2 Rd, Rs1, Rs2 * KMMWT2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and write the * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` * form rounds up the results from the most significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { * Rd.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][46:14] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][46:15]; * } * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMWT2(long a, unsigned long b) { register long result; __ASM volatile("kmmwt2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.50.1. KMMWT2 ===== */ /* ===== Inline Function Start for 3.50.2. KMMWT2.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief KMMWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMMWT2 Rd, Rs1, Rs2 * KMMWT2.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, double the multiplication results and write the * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u` * form rounds up the results from the most significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results. * * **Operations**:\n * ~~~ * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) { * Rd.W[x] = 0x7fffffff; * OV = 1; * } else { * Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][46:14] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][46:15]; * } * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMMWT2_U(long a, unsigned long b) { register long result; __ASM volatile("kmmwt2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.50.2. KMMWT2.u ===== */ /* ===== Inline Function Start for 3.51.1. KMSDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMSDA (SIMD Saturating Signed Multiply Two Halfs & Add & Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMSDA Rd, Rs1, Rs2 * KMSXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The * subtraction result may be saturated. * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element) * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element) * * **Description**:\n * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32- * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The * 16-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * // KMSDA * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMSXDA * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMSDA(long t, unsigned long a, unsigned long b) { __ASM volatile("kmsda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.51.1. KMSDA ===== */ /* ===== Inline Function Start for 3.51.2. KMSXDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief KMSXDA (SIMD Saturating Signed Crossed Multiply Two Halfs & Add & Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KMSDA Rd, Rs1, Rs2 * KMSXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The * subtraction result may be saturated. * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element) * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element) * * **Description**:\n * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32- * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The * 16-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * // KMSDA * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * // KMSXDA * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMSXDA(long t, unsigned long a, unsigned long b) { __ASM volatile("kmsxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.51.2. KMSXDA ===== */ /* ===== Inline Function Start for 3.52. KMSR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief KMSR64 (Signed Multiply and Saturating Subtract from 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * KMSR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers * specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the Q63 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated * result is written back to the even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It * subtracts the 64-bit multiplication results from the 64-bit signed data in Rd with unlimited * precision. If the 64-bit subtraction result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * result = R[t_H].R[t_L] - (Rs1 * Rs2); * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * R[t_H].R[t_L] = result; * RV64: * // `result` has unlimited precision * result = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * Rd = result; * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_KMSR64(long long t, long a, long b) { __ASM volatile("kmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.52. KMSR64 ===== */ /* ===== Inline Function Start for 3.53. KSLLW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KSLLW (Saturating Shift Left Logical for Word) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSLLW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do logical left shift operation with saturation on a 32-bit word. The shift amount is a * variable from a GPR. * * **Description**:\n * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with * zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. Any * shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated * to -2^31. And the saturated result is sign-extended and written to Rd. If any saturation is performed, * set OV bit to 1. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * res[(31+sa):0] = Rs1.W[0] << sa; * if (res > (2^31)-1) { * res = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res = 0x80000000; OV = 1; * } * Rd[31:0] = res[31:0]; // RV32 * Rd[63:0] = SE(res[31:0]); // RV64 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KSLLW(long a, unsigned int b) { register long result; __ASM volatile("ksllw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.53. KSLLW ===== */ /* ===== Inline Function Start for 3.54. KSLLIW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KSLLIW (Saturating Shift Left Logical Immediate for Word) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSLLIW Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do logical left shift operation with saturation on a 32-bit word. The shift amount is an * immediate value. * * **Description**:\n * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with * zero and the shift amount is specified by the imm5u constant. Any shifted value greater than 2^31-1 is * saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated result is * sign-extended and written to Rd. If any saturation is performed, set OV bit to 1. * * **Operations**:\n * ~~~ * sa = imm5u; * res[(31+sa):0] = Rs1.W[0] << sa; * if (res > (2^31)-1) { * res = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res = 0x80000000; OV = 1; * } * Rd[31:0] = res[31:0]; // RV32 * Rd[63:0] = SE(res[31:0]); // RV64 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ #define __RV_KSLLIW(a, b) \ ({ \ register long result; \ register long __a = (long)(a); \ __ASM volatile("kslliw %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.54. KSLLIW ===== */ /* ===== Inline Function Start for 3.55. KSLL8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief KSLL8 (SIMD 8-bit Saturating Shift Left Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLL8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift * amount is a variable from a GPR. * * **Description**:\n * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the low-order 3-bits of the value in the Rs2 register. * Any shifted value greater than 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is * saturated to -2^7. And the saturated results are written to Rd. If any saturation is performed, set OV * bit to 1. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * if (sa != 0) { * res[(7+sa):0] = Rs1.B[x] << sa; * if (res > (2^7)-1) { * res = 0x7f; OV = 1; * } else if (res < -2^7) { * res = 0x80; OV = 1; * } * Rd.B[x] = res[7:0]; * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLL8(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("ksll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.55. KSLL8 ===== */ /* ===== Inline Function Start for 3.56. KSLLI8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief KSLLI8 (SIMD 8-bit Saturating Shift Left Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLLI8 Rd, Rs1, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift * amount is an immediate value. * * **Description**:\n * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the imm3u constant. Any shifted value greater than * 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is saturated to -2^7. And the saturated * results are written to Rd. If any saturation is performed, set OV bit to 1. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * if (sa != 0) { * res[(7+sa):0] = Rs1.B[x] << sa; * if (res > (2^7)-1) { * res = 0x7f; OV = 1; * } else if (res < -2^7) { * res = 0x80; OV = 1; * } * Rd.B[x] = res[7:0]; * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_KSLLI8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("kslli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.56. KSLLI8 ===== */ /* ===== Inline Function Start for 3.57. KSLL16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief KSLL16 (SIMD 16-bit Saturating Shift Left Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLL16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift * amount is a variable from a GPR. * * **Description**:\n * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the low-order 4-bits of the value in the Rs2 register. * Any shifted value greater than 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is * saturated to -2^15. And the saturated results are written to Rd. If any saturation is performed, set OV * bit to 1. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * if (sa != 0) { * res[(15+sa):0] = Rs1.H[x] << sa; * if (res > (2^15)-1) { * res = 0x7fff; OV = 1; * } else if (res < -2^15) { * res = 0x8000; OV = 1; * } * Rd.H[x] = res[15:0]; * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("ksll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.57. KSLL16 ===== */ /* ===== Inline Function Start for 3.58. KSLLI16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief KSLLI16 (SIMD 16-bit Saturating Shift Left Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLLI16 Rd, Rs1, imm4u * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift * amount is an immediate value. * * **Description**:\n * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the imm4u constant. Any shifted value greater than * 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is saturated to -2^15. And the saturated * results are written to Rd. If any saturation is performed, set OV bit to 1. * * **Operations**:\n * ~~~ * sa = imm4u[3:0]; * if (sa != 0) { * res[(15+sa):0] = Rs1.H[x] << sa; * if (res > (2^15)-1) { * res = 0x7fff; OV = 1; * } else if (res < -2^15) { * res = 0x8000; OV = 1; * } * Rd.H[x] = res[15:0]; * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_KSLLI16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("kslli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.58. KSLLI16 ===== */ /* ===== Inline Function Start for 3.59.1. KSLRA8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief KSLRA8 (SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLRA8 Rd, Rs1, Rs2 * KSLRA8.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[3:0] < 0) { * sa = -Rs2[3:0]; * sa = (sa == 8)? 7 : sa; * if (`.u` form) { * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { * Rd.B[x] = SE8(Rs1.B[x][7:sa]); * } * } else { * sa = Rs2[2:0]; * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; * if (res > (2^7)-1) { * res[7:0] = 0x7f; OV = 1; * } else if (res < -2^7) { * res[7:0] = 0x80; OV = 1; * } * Rd.B[x] = res[7:0]; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA8(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.59.1. KSLRA8 ===== */ /* ===== Inline Function Start for 3.59.2. KSLRA8.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief KSLRA8.u (SIMD 8-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLRA8 Rd, Rs1, Rs2 * KSLRA8.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[3:0] < 0) { * sa = -Rs2[3:0]; * sa = (sa == 8)? 7 : sa; * if (`.u` form) { * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { * Rd.B[x] = SE8(Rs1.B[x][7:sa]); * } * } else { * sa = Rs2[2:0]; * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; * if (res > (2^7)-1) { * res[7:0] = 0x7f; OV = 1; * } else if (res < -2^7) { * res[7:0] = 0x80; OV = 1; * } * Rd.B[x] = res[7:0]; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.59.2. KSLRA8.u ===== */ /* ===== Inline Function Start for 3.60.1. KSLRA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief KSLRA16 (SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLRA16 Rd, Rs1, Rs2 * KSLRA16.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u` * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[4:0] < 0) { * sa = -Rs2[4:0]; * sa = (sa == 16)? 15 : sa; * if (`.u` form) { * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { * Rd.H[x] = SE16(Rs1.H[x][15:sa]); * } * } else { * sa = Rs2[3:0]; * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; * if (res > (2^15)-1) { * res[15:0] = 0x7fff; OV = 1; * } else if (res < -2^15) { * res[15:0] = 0x8000; OV = 1; * } * d.H[x] = res[15:0]; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.60.1. KSLRA16 ===== */ /* ===== Inline Function Start for 3.60.2. KSLRA16.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief KSLRA16.u (SIMD 16-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSLRA16 Rd, Rs1, Rs2 * KSLRA16.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u` * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[4:0] < 0) { * sa = -Rs2[4:0]; * sa = (sa == 16)? 15 : sa; * if (`.u` form) { * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { * Rd.H[x] = SE16(Rs1.H[x][15:sa]); * } * } else { * sa = Rs2[3:0]; * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; * if (res > (2^15)-1) { * res[15:0] = 0x7fff; OV = 1; * } else if (res < -2^15) { * res[15:0] = 0x8000; OV = 1; * } * d.H[x] = res[15:0]; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.60.2. KSLRA16.u ===== */ /* ===== Inline Function Start for 3.61. KSLRAW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KSLRAW (Shift Left Logical with Q31 Saturation or Shift Right Arithmetic) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSLRAW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31 * saturation for the left shift on a 32-bit data. * * **Description**:\n * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31]. * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. After the shift * operation, the final result is bit-31 sign-extended and written to Rd. If any saturation happens, this * instruction sets the OV flag. The value of Rs2[31:6] will not affected the operation of this instruction. * * **Operations**:\n * ~~~ * if (Rs2[5:0] < 0) { * sa = -Rs2[5:0]; * sa = (sa == 32)? 31 : sa; * res[31:0] = Rs1.W[0] >>(arith) sa; * } else { * sa = Rs2[5:0]; * tmp = Rs1.W[0] <<(logic) sa; * if (tmp > (2^31)-1) { * res[31:0] = (2^31)-1; * OV = 1; * } else if (tmp < -2^31) { * res[31:0] = -2^31; * OV = 1 * } else { * res[31:0] = tmp[31:0]; * } * } * Rd = res[31:0]; // RV32 * Rd = SE64(res[31:0]); // RV64 * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KSLRAW(int a, int b) { register long result; __ASM volatile("kslraw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.61. KSLRAW ===== */ /* ===== Inline Function Start for 3.62. KSLRAW.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KSLRAW.u (Shift Left Logical with Q31 Saturation or Rounding Shift Right Arithmetic) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSLRAW.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31 * saturation for the left shift and a rounding up operation for the right shift on a 32-bit data. * * **Description**:\n * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31]. * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. The right-shifted * result is added a 1 to the most significant discarded bit position for rounding effect. After the shift, * saturation, or rounding, the final result is bit-31 sign-extended and written to Rd. If any saturation * happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect the operation of this * instruction. * * **Operations**:\n * ~~~ * if (Rs2[5:0] < 0) { * sa = -Rs2[5:0]; * sa = (sa == 32)? 31 : sa; * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; * rst[31:0] = res[31:0]; * } else { * sa = Rs2[5:0]; * tmp = Rs1.W[0] <<(logic) sa; * if (tmp > (2^31)-1) { * rst[31:0] = (2^31)-1; * OV = 1; * } else if (tmp < -2^31) { * rst[31:0] = -2^31; * OV = 1 * } else { * rst[31:0] = tmp[31:0]; * } * } * Rd = rst[31:0]; // RV32 * Rd = SE64(rst[31:0]); // RV64 * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KSLRAW_U(int a, int b) { register long result; __ASM volatile("kslraw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.62. KSLRAW.u ===== */ /* ===== Inline Function Start for 3.63. KSTAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KSTAS16 (SIMD 16-bit Signed Saturating Straight Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSTAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating addition and 16-bit signed integer element * saturating subtraction in a 32-bit chunk simultaneously. Operands are from corresponding * positions in 32-bit chunks. * * **Description**:\n * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it * subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for * subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16]; * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0]; * for (res in [res1, res2]) { * if (res > (2^15)-1) { * res = (2^15)-1; * OV = 1; * } else if (res < -2^15) { * res = -2^15; * OV = 1; * } * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSTAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.63. KSTAS16 ===== */ /* ===== Inline Function Start for 3.64. KSTSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KSTSA16 (SIMD 16-bit Signed Saturating Straight Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSTSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element * saturating addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in * 32-bit chunks. * * **Description**:\n * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it * adds the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 with the 16-bit signed integer * element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number range (-2^15 * <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are * written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd for * addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16]; * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0]; * for (res in [res1, res2]) { * if (res > (2^15)-1) { * res = (2^15)-1; * OV = 1; * } else if (res < -2^15) { * res = -2^15; * OV = 1; * } * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSTSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.64. KSTSA16 ===== */ /* ===== Inline Function Start for 3.65. KSUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief KSUB8 (SIMD 8-bit Signed Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSUB8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 27 * -1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.B[x] - Rs2.B[x]; * if (res[x] > (2^7)-1) { * res[x] = (2^7)-1; * OV = 1; * } else if (res[x] < -2^7) { * res[x] = -2^7; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSUB8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.65. KSUB8 ===== */ /* ===== Inline Function Start for 3.66. KSUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief KSUB16 (SIMD 16-bit Signed Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KSUB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to * Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] - Rs2.H[x]; * if (res[x] > (2^15)-1) { * res[x] = (2^15)-1; * OV = 1; * } else if (res[x] < -2^15) { * res[x] = -2^15; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSUB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.66. KSUB16 ===== */ /* ===== Inline Function Start for 3.67. KSUB64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief KSUB64 (64-bit Signed Saturating Subtraction) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * KSUB64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a 64-bit signed integer subtraction. The result is saturated to the Q63 range. * * **RV32 Description**:\n * This instruction subtracts the 64-bit signed integer of an even/odd pair of * registers specified by Rs2(4,1) from the 64-bit signed integer of an even/odd pair of registers * specified by Rs1(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd * pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * This instruction subtracts the 64-bit signed integer of Rs2 from the 64-bit signed * integer of Rs1. If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated * to the range and the OV bit is set to 1. The saturated result is then written to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * result = R[a_H].R[a_L] - R[b_H].R[b_L]; * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * R[t_H].R[t_L] = result; * RV64: * result = Rs1 - Rs2; * if (result > (2^63)-1) { * result = (2^63)-1; OV = 1; * } else if (result < -2^63) { * result = -2^63; OV = 1; * } * Rd = result; * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b long long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_KSUB64(long long a, long long b) { register long long result; __ASM volatile("ksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.67. KSUB64 ===== */ /* ===== Inline Function Start for 3.68. KSUBH ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief KSUBH (Signed Subtraction with Q15 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSUBH Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract the signed lower 32-bit content of two registers with Q15 saturation. * * **Description**:\n * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit * content of Rs1. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] - Rs2.W[0]; * if (tmp > (2^15)-1) { * res = (2^15)-1; * OV = 1; * } else if (tmp < -2^15) { * res = -2^15; * OV = 1 * } else { * res = tmp; * } * Rd = SE(res[15:0]); * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KSUBH(int a, int b) { register long result; __ASM volatile("ksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.68. KSUBH ===== */ /* ===== Inline Function Start for 3.69. KSUBW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief KSUBW (Signed Subtraction with Q31 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * KSUBW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract the signed lower 32-bit content of two registers with Q31 saturation. * * **Description**:\n * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit * content of Rs1. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then * sign-extened and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] - Rs2.W[0]; * if (tmp > (2^31)-1) { * res = (2^31)-1; * OV = 1; * } else if (tmp < -2^31) { * res = -2^31; * OV = 1 * } else { * res = tmp; * } * Rd = res[31:0]; // RV32 * Rd = SE(res[31:0]); // RV64 * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KSUBW(int a, int b) { register long result; __ASM volatile("ksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.69. KSUBW ===== */ /* ===== Inline Function Start for 3.70.1. KWMMUL ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KWMMUL Rd, Rs1, Rs2 * KWMMUL.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally * rounds up the multiplication results from the most signification discarded bit. * * **Description**:\n * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts * the multiplication results one bit to the left and takes the most significant 32-bit results. If the * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u` * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit * 30 before the shift and saturation operations. * * **Operations**:\n * ~~~ * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) { * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][33:0] = Mres[x][63:30] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][62:31]; * } * } else { * Rd.W[x] = 0x7fffffff; * OV = 1; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KWMMUL(long a, long b) { register long result; __ASM volatile("kwmmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.70.1. KWMMUL ===== */ /* ===== Inline Function Start for 3.70.2. KWMMUL.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * KWMMUL Rd, Rs1, Rs2 * KWMMUL.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally * rounds up the multiplication results from the most signification discarded bit. * * **Description**:\n * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts * the multiplication results one bit to the left and takes the most significant 32-bit results. If the * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u` * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit * 30 before the shift and saturation operations. * * **Operations**:\n * ~~~ * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) { * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][33:0] = Mres[x][63:30] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][62:31]; * } * } else { * Rd.W[x] = 0x7fffffff; * OV = 1; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KWMMUL_U(long a, long b) { register long result; __ASM volatile("kwmmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.70.2. KWMMUL.u ===== */ /* ===== Inline Function Start for 3.71. MADDR32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief MADDR32 (Multiply and Add to 32-Bit Word) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MADDR32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit contents of two registers and add the lower 32-bit multiplication result * to the 32-bit content of a destination register. Write the final result back to the destination register. * * **Description**:\n * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2. It adds the * lower 32-bit multiplication result to the lower 32-bit content of Rd and writes the final result (RV32) * or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either signed or * unsigned integers. * * **Operations**:\n * ~~~ * RV32: * Mresult = Rs1 * Rs2; * Rd = Rd + Mresult.W[0]; * RV64: * Mresult = Rs1.W[0] * Rs2.W[0]; * tres[31:0] = Rd.W[0] + Mresult.W[0]; * Rd = SE64(tres[31:0]); * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_MADDR32(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("maddr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.71. MADDR32 ===== */ /* ===== Inline Function Start for 3.72. MAXW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief MAXW (32-bit Signed Word Maximum) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MAXW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Get the larger value from the 32-bit contents of two general registers. * * **Description**:\n * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the * larger value as the result, and writes the result to Rd. * * **Operations**:\n * ~~~ * if (Rs1.W[0] >= Rs2.W[0]) { * Rd = SE(Rs1.W[0]); * } else { * Rd = SE(Rs2.W[0]); * } * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_MAXW(int a, int b) { register long result; __ASM volatile("maxw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.72. MAXW ===== */ /* ===== Inline Function Start for 3.73. MINW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief MINW (32-bit Signed Word Minimum) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MINW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Get the smaller value from the 32-bit contents of two general registers. * * **Description**:\n * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the * smaller value as the result, and writes the result to Rd. * * **Operations**:\n * ~~~ * if (Rs1.W[0] >= Rs2.W[0]) { Rd = SE(Rs2.W[0]); } else { Rd = SE(Rs1.W[0]); } * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_MINW(int a, int b) { register long result; __ASM volatile("minw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.73. MINW ===== */ /* ===== Inline Function Start for 3.74. MSUBR32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief MSUBR32 (Multiply and Subtract from 32-Bit Word) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MSUBR32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit contents of two registers and subtract the lower 32-bit multiplication * result from the 32-bit content of a destination register. Write the final result back to the destination * register. * * **Description**:\n * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2, subtracts * the lower 32-bit multiplication result from the lower 32-bit content of Rd, then writes the final * result (RV32) or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either * signed or unsigned integers. * * **Operations**:\n * ~~~ * RV32: * Mresult = Rs1 * Rs2; * Rd = Rd - Mresult.W[0]; * RV64: * Mresult = Rs1.W[0] * Rs2.W[0]; * tres[31:0] = Rd.W[0] - Mresult.W[0]; * Rd = SE64(tres[31:0]); * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_MSUBR32(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("msubr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.74. MSUBR32 ===== */ /* ===== Inline Function Start for 3.75. MULR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief MULR64 (Multiply Word Unsigned to 64-bit Data) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MULR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit unsigned integer contents of two registers and write the 64-bit result. * * **RV32 Description**:\n * This instruction multiplies the 32-bit content of Rs1 with that of Rs2 and writes the 64-bit * multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d determines the * even/odd pair group of the two registers. Specifically, the register pair includes register 2d and * 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers. * * **RV64 Description**:\n * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2 and writes the 64-bit * multiplication result to Rd. * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers. * * **Operations**:\n * ~~~ * RV32: * Mresult = CONCAT(1`b0,Rs1) u* CONCAT(1`b0,Rs2); * R[Rd(4,1).1(0)][31:0] = Mresult[63:32]; * R[Rd(4,1).0(0)][31:0] = Mresult[31:0]; * RV64: * Rd = Mresult[63:0]; * Mresult = CONCAT(1`b0,Rs1.W[0]) u* CONCAT(1`b0,Rs2.W[0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_MULR64(unsigned long a, unsigned long b) { register unsigned long long result; __ASM volatile("mulr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.75. MULR64 ===== */ /* ===== Inline Function Start for 3.76. MULSR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief MULSR64 (Multiply Word Signed to 64-bit Data) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * MULSR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed integer contents of two registers and write the 64-bit result. * * **RV32 Description**:\n * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and * writes the 64-bit multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d * determines the even/odd pair group of the two registers. Specifically, the register pair includes * register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers. * * **RV64 Description**:\n * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and * writes the 64-bit multiplication result to Rd. * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * RV32: * Mresult = Ra s* Rb; * R[Rd(4,1).1(0)][31:0] = Mresult[63:32]; * R[Rd(4,1).0(0)][31:0] = Mresult[31:0]; * RV64: * Mresult = Ra.W[0] s* Rb.W[0]; * Rd = Mresult[63:0]; * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_MULSR64(long a, long b) { register long long result; __ASM volatile("mulsr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.76. MULSR64 ===== */ /* ===== Inline Function Start for 3.77. PBSAD ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief PBSAD (Parallel Byte Sum of Absolute Difference) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PBSAD Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Calculate the sum of absolute difference of unsigned 8-bit data elements. * * **Description**:\n * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. Then * it adds the absolute value of each difference together and writes the result to Rd. * * **Operations**:\n * ~~~ * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]); * Rd = SUM(absdiff[x]); * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PBSAD(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pbsad %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.77. PBSAD ===== */ /* ===== Inline Function Start for 3.78. PBSADA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief PBSADA (Parallel Byte Sum of Absolute Difference Accum) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PBSADA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Calculate the sum of absolute difference of four unsigned 8-bit data elements and * accumulate it into a register. * * **Description**:\n * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. It * then adds the absolute value of each difference together along with the content of Rd and writes the * accumulated result back to Rd. * * **Operations**:\n * ~~~ * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]); * Rd = Rd + SUM(absdiff[x]); * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PBSADA(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("pbsada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.78. PBSADA ===== */ /* ===== Inline Function Start for 3.79.1. PKBB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK * \brief PKBB16 (Pack Two 16-bit Data from Both Bottom Half) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PKBB16 Rd, Rs1, Rs2 * PKBT16 Rd, Rs1, Rs2 * PKTT16 Rd, Rs1, Rs2 * PKTB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 16-bit data from 32-bit chunks in two registers. * * PKBB16: bottom.bottom * * PKBT16 bottom.top * * PKTT16 top.top * * PKTB16 top.bottom * * **Description**:\n * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to * Rd.W[x] [15:0]. * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKBB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pkbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.79.1. PKBB16 ===== */ /* ===== Inline Function Start for 3.79.2. PKBT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK * \brief PKBT16 (Pack Two 16-bit Data from Bottom and Top Half) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PKBB16 Rd, Rs1, Rs2 * PKBT16 Rd, Rs1, Rs2 * PKTT16 Rd, Rs1, Rs2 * PKTB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 16-bit data from 32-bit chunks in two registers. * * PKBB16: bottom.bottom * * PKBT16 bottom.top * * PKTT16 top.top * * PKTB16 top.bottom * * **Description**:\n * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to * Rd.W[x] [15:0]. * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKBT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pkbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.79.2. PKBT16 ===== */ /* ===== Inline Function Start for 3.79.3. PKTT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK * \brief PKTT16 (Pack Two 16-bit Data from Both Top Half) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PKBB16 Rd, Rs1, Rs2 * PKBT16 Rd, Rs1, Rs2 * PKTT16 Rd, Rs1, Rs2 * PKTB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 16-bit data from 32-bit chunks in two registers. * * PKBB16: bottom.bottom * * PKBT16 bottom.top * * PKTT16 top.top * * PKTB16 top.bottom * * **Description**:\n * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to * Rd.W[x] [15:0]. * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKTT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pktt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.79.3. PKTT16 ===== */ /* ===== Inline Function Start for 3.79.4. PKTB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK * \brief PKTB16 (Pack Two 16-bit Data from Top and Bottom Half) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * PKBB16 Rd, Rs1, Rs2 * PKBT16 Rd, Rs1, Rs2 * PKTT16 Rd, Rs1, Rs2 * PKTB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 16-bit data from 32-bit chunks in two registers. * * PKBB16: bottom.bottom * * PKBT16 bottom.top * * PKTT16 top.top * * PKTB16 top.bottom * * **Description**:\n * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to * Rd.W[x] [15:0]. * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0]. * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0]. * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKTB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pktb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.79.4. PKTB16 ===== */ /* ===== Inline Function Start for 3.80. RADD8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief RADD8 (SIMD 8-bit Signed Halving Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RADD8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer element additions simultaneously. The element results are halved * to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to * Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7F, Rs2 = 0x7F, Rd = 0x7F * * Rs1 = 0x80, Rs2 = 0x80, Rd = 0x80 * * Rs1 = 0x40, Rs2 = 0x80, Rd = 0xE0 * ~~~ * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] + Rs2.B[x]) s>> 1; for RV32: x=3...0, for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RADD8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("radd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.80. RADD8 ===== */ /* ===== Inline Function Start for 3.81. RADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RADD16 (SIMD 16-bit Signed Halving Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RADD16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element additions simultaneously. The results are halved to avoid * overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to * Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7FFF, Rs2 = 0x7FFF, Rd = 0x7FFF * * Rs1 = 0x8000, Rs2 = 0x8000, Rd = 0x8000 * * Rs1 = 0x4000, Rs2 = 0x8000, Rd = 0xE000 * ~~~ * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) s>> 1; for RV32: x=1...0, for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RADD16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("radd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.81. RADD16 ===== */ /* ===== Inline Function Start for 3.82. RADD64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief RADD64 (64-bit Signed Halving Addition) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * RADD64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add two 64-bit signed integers. The result is halved to avoid overflow or saturation. * * **RV32 Description**:\n * This instruction adds the 64-bit signed integer of an even/odd pair of registers * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by * Rs2(4,1). The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to an * even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed * integer in Rs2. The 64-bit addition result is first arithmetically right-shifted by 1 bit and then * written to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) s>> 1; * RV64: * Rd = (Rs1 + Rs2) s>> 1; * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b long long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_RADD64(long long a, long long b) { register long long result; __ASM volatile("radd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.82. RADD64 ===== */ /* ===== Inline Function Start for 3.83. RADDW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief RADDW (32-bit Signed Halving Addition) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * RADDW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add 32-bit signed integers and the results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the first 32-bit signed integer in Rs1 with the first 32-bit signed * integer in Rs2. The result is first arithmetically right-shifted by 1 bit and then sign-extended and * written to Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF, Rd = 0x7FFFFFFF * * Rs1 = 0x80000000, Rs2 = 0x80000000, Rd = 0x80000000 * * Rs1 = 0x40000000, Rs2 = 0x80000000, Rd = 0xE0000000 * ~~~ * * **Operations**:\n * ~~~ * RV32: * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1; * RV64: * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1; * Rd[63:0] = SE(resw[31:0]); * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_RADDW(int a, int b) { register long result; __ASM volatile("raddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.83. RADDW ===== */ /* ===== Inline Function Start for 3.84. RCRAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RCRAS16 (SIMD 16-bit Signed Halving Cross Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RCRAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results * are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit * signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed integer element in * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `RADD16` and `RSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) s>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) s>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RCRAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.84. RCRAS16 ===== */ /* ===== Inline Function Start for 3.85. RCRSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RCRSA16 (SIMD 16-bit Signed Halving Cross Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RCRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results * are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in * [31:16] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `RADD16` and `RSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) s>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) s>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RCRSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.85. RCRSA16 ===== */ /* ===== Inline Function Start for 3.86. RDOV ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC * \brief RDOV (Read OV flag) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * RDOV Rd # pseudo mnemonic * ~~~ * * **Purpose**:\n * This pseudo instruction is an alias to `CSRR Rd, ucode` instruction which maps to the real * instruction of `CSRRS Rd, ucode, x0`. * * * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RDOV(void) { register unsigned long result; __ASM volatile("rdov %0" : "=r"(result)); return result; } /* ===== Inline Function End for 3.86. RDOV ===== */ /* ===== Inline Function Start for 3.87. RSTAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RSTAS16 (SIMD 16-bit Signed Halving Straight Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RSTAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The * results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit * signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed integer element in * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `RADD16` and `RSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) s>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) s>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSTAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.87. RSTAS16 ===== */ /* ===== Inline Function Start for 3.88. RSTSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RSTSA16 (SIMD 16-bit Signed Halving Straight Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RSTSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The * results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in * [15:0] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and then * written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `RADD16` and `RSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) s>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) s>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSTSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.88. RSTSA16 ===== */ /* ===== Inline Function Start for 3.89. RSUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief RSUB8 (SIMD 8-bit Signed Halving Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RSUB8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7F, Rs2 = 0x80, Rd = 0x7F * * Rs1 = 0x80, Rs2 = 0x7F, Rd = 0x80 * * Rs1= 0x80, Rs2 = 0x40, Rd = 0xA0 * ~~~ * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) s>> 1; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSUB8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rsub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.89. RSUB8 ===== */ /* ===== Inline Function Start for 3.90. RSUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief RSUB16 (SIMD 16-bit Signed Halving Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * RSUB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFF, Rb = 0x8000, Rt = 0x7FFF * * Ra = 0x8000, Rb = 0x7FFF, Rt = 0x8000 * * Ra = 0x8000, Rb = 0x4000, Rt = 0xA000 * ~~~ * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) s>> 1; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSUB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rsub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.90. RSUB16 ===== */ /* ===== Inline Function Start for 3.91. RSUB64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief RSUB64 (64-bit Signed Halving Subtraction) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * RSUB64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a 64-bit signed integer subtraction. The result is halved to avoid overflow or * saturation. * * **RV32 Description**:\n * This instruction subtracts the 64-bit signed integer of an even/odd pair of * registers specified by Rb(4,1) from the 64-bit signed integer of an even/odd pair of registers * specified by Ra(4,1). The subtraction result is first arithmetically right-shifted by 1 bit and then * written to an even/odd pair of registers specified by Rt(4,1). * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction subtracts the 64-bit signed integer in Rs2 from the 64-bit signed * integer in Rs1. The 64-bit subtraction result is first arithmetically right-shifted by 1 bit and then * written to Rd. * * **Operations**:\n * ~~~ * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) s>> 1; * RV64: * Rd = (Rs1 - Rs2) s>> 1; * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b long long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_RSUB64(long long a, long long b) { register long long result; __ASM volatile("rsub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.91. RSUB64 ===== */ /* ===== Inline Function Start for 3.92. RSUBW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief RSUBW (32-bit Signed Halving Subtraction) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * RSUBW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract 32-bit signed integers and the result is halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit * signed integer in Rs1. The result is first arithmetically right-shifted by 1 bit and then sign-extended * and written to Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x80000000, Rd = 0x7FFFFFFF * * Rs1 = 0x80000000, Rs2 = 0x7FFFFFFF, Rd = 0x80000000 * * Rs1 = 0x80000000, Rs2 = 0x40000000, Rd = 0xA0000000 * ~~~ * * **Operations**:\n * ~~~ * RV32: * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1; * RV64: * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1; * Rd[63:0] = SE(resw[31:0]); * ~~~ * * \param [in] a int type of value stored in a * \param [in] b int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_RSUBW(int a, int b) { register long result; __ASM volatile("rsubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.92. RSUBW ===== */ /* ===== Inline Function Start for 3.93. SCLIP8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief SCLIP8 (SIMD 8-bit Signed Clip Value) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCLIP8 Rd, Rs1, imm3u[2:0] * ~~~ * * **Purpose**:\n * Limit the 8-bit signed integer elements of a register into a signed range simultaneously. * * **Description**:\n * This instruction limits the 8-bit signed integer elements stored in Rs1 into a signed * integer range between 2^imm3u-1 and -2^imm3u, and writes the limited results to Rd. For example, if * imm3u is 3, the 8-bit input values should be saturated between 7 and -8. If saturation is performed, * set OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.B[x]; * if (src > (2^imm3u)-1) { * src = (2^imm3u)-1; * OV = 1; * } else if (src < -2^imm3u) { * src = -2^imm3u; * OV = 1; * } * Rd.B[x] = src * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SCLIP8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("sclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.93. SCLIP8 ===== */ /* ===== Inline Function Start for 3.94. SCLIP16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief SCLIP16 (SIMD 16-bit Signed Clip Value) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCLIP16 Rd, Rs1, imm4u[3:0] * ~~~ * * **Purpose**:\n * Limit the 16-bit signed integer elements of a register into a signed range simultaneously. * * **Description**:\n * This instruction limits the 16-bit signed integer elements stored in Rs1 into a signed * integer range between 2imm4u-1 and -2imm4u, and writes the limited results to Rd. For example, if * imm4u is 3, the 16-bit input values should be saturated between 7 and -8. If saturation is performed, * set OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.H[x]; * if (src > (2^imm4u)-1) { * src = (2^imm4u)-1; * OV = 1; * } else if (src < -2^imm4u) { * src = -2^imm4u; * OV = 1; * } * Rd.H[x] = src * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SCLIP16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("sclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.94. SCLIP16 ===== */ /* ===== Inline Function Start for 3.95. SCLIP32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief SCLIP32 (SIMD 32-bit Signed Clip Value) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SCLIP32 Rd, Rs1, imm5u[4:0] * ~~~ * * **Purpose**:\n * Limit the 32-bit signed integer elements of a register into a signed range simultaneously. * * **Description**:\n * This instruction limits the 32-bit signed integer elements stored in Rs1 into a signed * integer range between 2imm5u-1 and -2imm5u, and writes the limited results to Rd. For example, if * imm5u is 3, the 32-bit input values should be saturated between 7 and -8. If saturation is performed, * set OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.W[x]; * if (src > (2^imm5u)-1) { * src = (2^imm5u)-1; * OV = 1; * } else if (src < -2^imm5u) { * src = -2^imm5u; * OV = 1; * } * Rd.W[x] = src * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ #define __RV_SCLIP32(a, b) \ ({ \ register long result; \ register long __a = (long)(a); \ __ASM volatile("sclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.95. SCLIP32 ===== */ /* ===== Inline Function Start for 3.96. SCMPLE8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP * \brief SCMPLE8 (SIMD 8-bit Signed Compare Less Than & Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCMPLE8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer elements less than & equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is * true, the result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to * Rd * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] {le} Rs2.B[x])? 0xff : 0x0; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SCMPLE8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("scmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.96. SCMPLE8 ===== */ /* ===== Inline Function Start for 3.97. SCMPLE16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP * \brief SCMPLE16 (SIMD 16-bit Signed Compare Less Than & Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCMPLE16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements less than & equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is * true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written * to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] {le} Rs2.H[x])? 0xffff : 0x0; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SCMPLE16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("scmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.97. SCMPLE16 ===== */ /* ===== Inline Function Start for 3.98. SCMPLT8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP * \brief SCMPLT8 (SIMD 8-bit Signed Compare Less Than) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCMPLT8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer elements less than comparisons simultaneously. * * **Description**:\n * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit * signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? 0xff : 0x0; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SCMPLT8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("scmplt8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.98. SCMPLT8 ===== */ /* ===== Inline Function Start for 3.99. SCMPLT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP * \brief SCMPLT16 (SIMD 16-bit Signed Compare Less Than) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SCMPLT16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements less than comparisons simultaneously. * * **Description**:\n * This instruction compares the 16-bit signed integer elements in Rs1 with the two 16- * bit signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the * result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? 0xffff : 0x0; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SCMPLT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("scmplt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.99. SCMPLT16 ===== */ /* ===== Inline Function Start for 3.100. SLL8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SLL8 (SIMD 8-bit Shift Left Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SLL8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left shift operations simultaneously. The shift amount is a * variable from a GPR. * * **Description**:\n * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. * The shifted out bits are filled with zero and the shift amount is specified by the low-order 3-bits of * the value in the Rs2 register. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * Rd.B[x] = Rs1.B[x] << sa; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SLL8(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.100. SLL8 ===== */ /* ===== Inline Function Start for 3.101. SLLI8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SLLI8 (SIMD 8-bit Shift Left Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SLLI8 Rd, Rs1, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left shift operations simultaneously. The shift amount is an * immediate value. * * **Description**:\n * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. * The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * Rd.B[x] = Rs1.B[x] << sa; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SLLI8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("slli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.101. SLLI8 ===== */ /* ===== Inline Function Start for 3.102. SLL16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SLL16 (SIMD 16-bit Shift Left Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SLL16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left shift operations simultaneously. The shift amount is a * variable from a GPR. * * **Description**:\n * The 16-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. * The shifted out bits are filled with zero and the shift amount is specified by the low-order 4-bits of * the value in the Rs2 register. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * Rd.H[x] = Rs1.H[x] << sa; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.102. SLL16 ===== */ /* ===== Inline Function Start for 3.103. SLLI16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SLLI16 (SIMD 16-bit Shift Left Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SLLI16 Rd, Rs1, imm4[3:0] * ~~~ * * **Purpose**:\n * Do 16-bit element logical left shift operations simultaneously. The shift amount is an * immediate value. * * **Description**:\n * The 16-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with * zero and the shift amount is specified by the imm4[3:0] constant. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm4[3:0]; * Rd.H[x] = Rs1.H[x] << sa; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SLLI16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("slli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.103. SLLI16 ===== */ /* ===== Inline Function Start for 3.104. SMAL ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMAL (Signed Multiply Halfs & Add 64-bit) * \details * **Type**: Partial-SIMD * * **Syntax**:\n * ~~~ * SMAL Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top * 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back * to another even/odd pair of registers (RV32) or a register (RV64). * * **RV32 Description**:\n * This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit * content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of * registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of * registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register- * pair are treated as signed integers. * Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit * content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64- * bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are * treated as signed integers. * * **Operations**:\n * ~~~ * RV32: * Mres[31:0] = Rs2.H[1] * Rs2.H[0]; * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); + * Idx2 = CONCAT(Rd(4,1),1'b0); Idx3 = CONCAT(Rd(4,1),1'b1); * R[Idx3].R[Idx2] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: * Mres[0][31:0] = Rs2.W[0].H[1] * Rs2.W[0].H[0]; * Mres[1][31:0] = Rs2.W[1].H[1] * Rs2.W[1].H[0]; * Rd = Rs1 + SE64(Mres[1][31:0]) + SE64(Mres[0][31:0]); * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMAL(long long a, unsigned long b) { register long long result; __ASM volatile("smal %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.104. SMAL ===== */ /* ===== Inline Function Start for 3.105.1. SMALBB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALBB (Signed Multiply Bottom Halfs & Add 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALBB Rd, Rs1, Rs2 * SMALBT Rd, Rs1, Rs2 * SMALTT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit * content of the corresponding 32-bit elements of another register and add the results with a 64-bit * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back * to the register-pair (RV32) or the register (RV64). * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) * * SMALBT rt pair + bottom*top (all 32-bit elements) * * SMALTT rt pair + top*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2. * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * RV32: * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: * // SMALBB * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; * // SMALBT * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; * // SMALTT * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALBB(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalbb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.105.1. SMALBB ===== */ /* ===== Inline Function Start for 3.105.2. SMALBT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALBB Rd, Rs1, Rs2 * SMALBT Rd, Rs1, Rs2 * SMALTT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit * content of the corresponding 32-bit elements of another register and add the results with a 64-bit * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back * to the register-pair (RV32) or the register (RV64). * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) * * SMALBT rt pair + bottom*top (all 32-bit elements) * * SMALTT rt pair + top*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2. * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * RV32: * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: * // SMALBB * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; * // SMALBT * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; * // SMALTT * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALBT(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalbt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.105.2. SMALBT ===== */ /* ===== Inline Function Start for 3.105.3. SMALTT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALTT (Signed Multiply Top Halfs & Add 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALBB Rd, Rs1, Rs2 * SMALBT Rd, Rs1, Rs2 * SMALTT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit * content of the corresponding 32-bit elements of another register and add the results with a 64-bit * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back * to the register-pair (RV32) or the register (RV64). * * SMALBB: rt pair + bottom*bottom (all 32-bit elements) * * SMALBT rt pair + bottom*top (all 32-bit elements) * * SMALTT rt pair + top*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2. * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * RV32: * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: * // SMALBB * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; * // SMALBT * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; * // SMALTT * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALTT(long long t, unsigned long a, unsigned long b) { __ASM volatile("smaltt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.105.3. SMALTT ===== */ /* ===== Inline Function Start for 3.106.1. SMALDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALDA Rd, Rs1, Rs2 * SMALXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together. * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements) * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with * the top 16-bit content of Rs2 with unlimited precision. * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 * with the top 16-bit content of Rs2 with unlimited precision. * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- * bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- * bit elements of Rs2 with unlimited precision. * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the * 32-bit elements of Rs2 with unlimited precision. * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers. * * **Operations**:\n * ~~~ * RV32: * // SMALDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); * // SMALXDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); * RV64: * // SMALDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMALXDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + * SE64(Mres1[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALDA(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.106.1. SMALDA ===== */ /* ===== Inline Function Start for 3.106.2. SMALXDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALDA Rd, Rs1, Rs2 * SMALXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together. * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements) * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with * the top 16-bit content of Rs2 with unlimited precision. * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 * with the top 16-bit content of Rs2 with unlimited precision. * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- * bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- * bit elements of Rs2 with unlimited precision. * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the * 32-bit elements of Rs2 with unlimited precision. * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers. * * **Operations**:\n * ~~~ * RV32: * // SMALDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); * // SMALXDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); * RV64: * // SMALDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMALXDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + * SE64(Mres1[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALXDA(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.106.2. SMALXDA ===== */ /* ===== Inline Function Start for 3.107.1. SMALDS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALDS Rd, Rs1, Rs2 * SMALDRS Rd, Rs1, Rs2 * SMALXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is * written back to the register-pair. * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the top 16-bit content of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 * with the bottom 16-bit content of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the bottom 16-bit content of Rs2. * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content * of the 32-bit elements of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * * RV32: * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * * RV64: * // SMALDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * // SMALDRS * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMALXDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALDS(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.107.1. SMALDS ===== */ /* ===== Inline Function Start for 3.107.2. SMALDRS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALDS Rd, Rs1, Rs2 * SMALDRS Rd, Rs1, Rs2 * SMALXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is * written back to the register-pair. * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the top 16-bit content of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 * with the bottom 16-bit content of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the bottom 16-bit content of Rs2. * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content * of the 32-bit elements of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * * RV32: * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * * RV64: * // SMALDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * // SMALDRS * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMALXDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALDRS(long long t, unsigned long a, unsigned long b) { __ASM volatile("smaldrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.107.2. SMALDRS ===== */ /* ===== Inline Function Start for 3.107.3. SMALXDS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMALDS Rd, Rs1, Rs2 * SMALDRS Rd, Rs1, Rs2 * SMALXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is * written back to the register-pair. * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements) * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements) * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements) * * **RV32 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the top 16-bit content of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 * with the bottom 16-bit content of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of * Rs1 with the bottom 16-bit content of Rs2. * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and * Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content * of the 32-bit elements of Rs2. * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed * integers. * * **Operations**:\n * ~~~ * * RV32: * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * * RV64: * // SMALDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * // SMALDRS * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMALXDS * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMALXDS(long long t, unsigned long a, unsigned long b) { __ASM volatile("smalxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.107.3. SMALXDS ===== */ /* ===== Inline Function Start for 3.108. SMAR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief SMAR64 (Signed Multiply and Add to 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMAR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication * result to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is written * back to the pair of registers (RV32) or a register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by * Rd(4,1). The addition result is written back to the even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It * adds the 64-bit multiplication results to the 64-bit signed data of Rd. The addition result is written * back to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2); * * RV64: * Rd = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMAR64(long long t, long a, long b) { __ASM volatile("smar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.108. SMAR64 ===== */ /* ===== Inline Function Start for 3.109. SMAQA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD * \brief SMAQA (Signed Multiply Four Bytes with 32-bit Adds) * \details * **Type**: Partial-SIMD (Reduction) * * **Syntax**:\n * ~~~ * SMAQA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do four signed 8-bit multiplications from 32-bit chunks of two registers; and then adds * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together. * * **Description**:\n * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four * signed 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the signed * content of the corresponding 32-bit chunks of Rd. The final results are written back to the * corresponding 32-bit chunks in Rd. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + * (Rs1.W[x].B[3] s* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] s* Rs2.W[x].B[2]) + * (Rs1.W[x].B[1] s* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] s* Rs2.W[x].B[0]); * Rd.W[x] = res[x]; * for RV32: x=0, * for RV64: x=1,0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMAQA(long t, unsigned long a, unsigned long b) { __ASM volatile("smaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.109. SMAQA ===== */ /* ===== Inline Function Start for 3.110. SMAQA.SU ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD * \brief SMAQA.SU (Signed and Unsigned Multiply Four Bytes with 32-bit Adds) * \details * **Type**: Partial-SIMD (Reduction) * * **Syntax**:\n * ~~~ * SMAQA.SU Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do four `signed x unsigned` 8-bit multiplications from 32-bit chunks of two registers; and * then adds the four 16-bit results and the content of corresponding 32-bit chunks of a third register * together. * * **Description**:\n * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the * signed content of the corresponding 32-bit chunks of Rd. The final results are written back to the * corresponding 32-bit chunks in Rd. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + * (Rs1.W[x].B[3] su* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] su* Rs2.W[x].B[2]) + * (Rs1.W[x].B[1] su* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] su* Rs2.W[x].B[0]); * Rd.W[x] = res[x]; * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMAQA_SU(long t, unsigned long a, unsigned long b) { __ASM volatile("smaqa.su %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.110. SMAQA.SU ===== */ /* ===== Inline Function Start for 3.111. SMAX8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief SMAX8 (SIMD 8-bit Signed Maximum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMAX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] > Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMAX8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.111. SMAX8 ===== */ /* ===== Inline Function Start for 3.112. SMAX16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief SMAX16 (SIMD 16-bit Signed Maximum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMAX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] > Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMAX16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.112. SMAX16 ===== */ /* ===== Inline Function Start for 3.113.1. SMBB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMBB16 (SIMD Signed Multiply Bottom Half & Bottom Half) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMBB16 Rd, Rs1, Rs2 * SMBT16 Rd, Rs1, Rs2 * SMTT16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- * bit content of the 32-bit elements of another register and write the result to a third register. * * SMBB16: W[x].bottom*W[x].bottom * * SMBT16: W[x].bottom *W[x].top * * SMTT16: W[x].top * W[x].top * * **Description**:\n * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMBB16(unsigned long a, unsigned long b) { register long result; __ASM volatile("smbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.113.1. SMBB16 ===== */ /* ===== Inline Function Start for 3.113.2. SMBT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMBT16 (SIMD Signed Multiply Bottom Half & Top Half) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMBB16 Rd, Rs1, Rs2 * SMBT16 Rd, Rs1, Rs2 * SMTT16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- * bit content of the 32-bit elements of another register and write the result to a third register. * * SMBB16: W[x].bottom*W[x].bottom * * SMBT16: W[x].bottom *W[x].top * * SMTT16: W[x].top * W[x].top * * **Description**:\n * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMBT16(unsigned long a, unsigned long b) { register long result; __ASM volatile("smbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.113.2. SMBT16 ===== */ /* ===== Inline Function Start for 3.113.3. SMTT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMTT16 (SIMD Signed Multiply Top Half & Top Half) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMBB16 Rd, Rs1, Rs2 * SMBT16 Rd, Rs1, Rs2 * SMTT16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16- * bit content of the 32-bit elements of another register and write the result to a third register. * * SMBB16: W[x].bottom*W[x].bottom * * SMBT16: W[x].bottom *W[x].top * * SMTT16: W[x].top * W[x].top * * **Description**:\n * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2. * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2. * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16 * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMTT16(unsigned long a, unsigned long b) { register long result; __ASM volatile("smtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.113.3. SMTT16 ===== */ /* ===== Inline Function Start for 3.114.1. SMDS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMDS (SIMD Signed Multiply Two Halfs and Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMDS Rd, Rs1, Rs2 * SMDRS Rd, Rs1, Rs2 * SMXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. * * SMDS: top*top - bottom*bottom (per 32-bit element) * * SMDRS: bottom*bottom - top*top (per 32-bit element) * * SMXDS: top*bottom - bottom*top (per 32-bit element) * * **Description**:\n * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the * 32-bit elements of Rs2. * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of * multiplication are treated as signed integers. * * **Operations**:\n * ~~~ * * SMDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * * SMDRS: * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * * SMXDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMDS(unsigned long a, unsigned long b) { register long result; __ASM volatile("smds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.114.1. SMDS ===== */ /* ===== Inline Function Start for 3.114.2. SMDRS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMDRS (SIMD Signed Multiply Two Halfs and Reverse Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMDS Rd, Rs1, Rs2 * SMDRS Rd, Rs1, Rs2 * SMXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. * * SMDS: top*top - bottom*bottom (per 32-bit element) * * SMDRS: bottom*bottom - top*top (per 32-bit element) * * SMXDS: top*bottom - bottom*top (per 32-bit element) * * **Description**:\n * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the * 32-bit elements of Rs2. * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of * multiplication are treated as signed integers. * * **Operations**:\n * ~~~ * * SMDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * * SMDRS: * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * * SMXDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMDRS(unsigned long a, unsigned long b) { register long result; __ASM volatile("smdrs %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.114.2. SMDRS ===== */ /* ===== Inline Function Start for 3.114.3. SMXDS ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB * \brief SMXDS (SIMD Signed Crossed Multiply Two Halfs and Subtract) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMDS Rd, Rs1, Rs2 * SMDRS Rd, Rs1, Rs2 * SMXDS Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * perform a subtraction operation between the two 32-bit results. * * SMDS: top*top - bottom*bottom (per 32-bit element) * * SMDRS: bottom*bottom - top*top (per 32-bit element) * * SMXDS: top*bottom - bottom*top (per 32-bit element) * * **Description**:\n * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the * 32-bit elements of Rs2. * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of * the 32-bit elements of Rs2. * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit * content of the 32-bit elements of Rs2. * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of * multiplication are treated as signed integers. * * **Operations**:\n * ~~~ * * SMDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]); * * SMDRS: * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]); * * SMXDS: * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMXDS(unsigned long a, unsigned long b) { register long result; __ASM volatile("smxds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.114.3. SMXDS ===== */ /* ===== Inline Function Start for 3.115. SMIN8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief SMIN8 (SIMD 8-bit Signed Minimum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMIN8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit signed integer elements finding minimum operations simultaneously. * * **Description**:\n * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected * results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMIN8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smin8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.115. SMIN8 ===== */ /* ===== Inline Function Start for 3.116. SMIN16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief SMIN16 (SIMD 16-bit Signed Minimum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMIN16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements finding minimum operations simultaneously. * * **Description**:\n * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected * results are written to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMIN16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smin16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.116. SMIN16 ===== */ /* ===== Inline Function Start for 3.117.1. SMMUL ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief SMMUL (SIMD MSW Signed Multiply Word) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMUL Rd, Rs1, Rs2 * SMMUL.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed integer elements of two registers and write the most significant * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an * additional rounding up operation on the multiplication results before taking the most significant * 32-bit part of the results. * * **Description**:\n * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results. * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][63:32]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMUL(long a, long b) { register long result; __ASM volatile("smmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.117.1. SMMUL ===== */ /* ===== Inline Function Start for 3.117.2. SMMUL.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC * \brief SMMUL.u (SIMD MSW Signed Multiply Word with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMUL Rd, Rs1, Rs2 * SMMUL.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed integer elements of two registers and write the most significant * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an * additional rounding up operation on the multiplication results before taking the most significant * 32-bit part of the results. * * **Description**:\n * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results. * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction. * * **Operations**:\n * ~~~ * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x]; * if (`.u` form) { * Round[x][32:0] = Mres[x][63:31] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][63:32]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMUL_U(long a, long b) { register long result; __ASM volatile("smmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.117.2. SMMUL.u ===== */ /* ===== Inline Function Start for 3.118.1. SMMWB ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief SMMWB (SIMD MSW Signed Multiply Word and Bottom Half) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMWB Rd, Rs1, Rs2 * SMMWB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, and write the most significant 32-bit results to * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most * significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][47:16]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMWB(long a, unsigned long b) { register long result; __ASM volatile("smmwb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.118.1. SMMWB ===== */ /* ===== Inline Function Start for 3.118.2. SMMWB.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief SMMWB.u (SIMD MSW Signed Multiply Word and Bottom Half with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMWB Rd, Rs1, Rs2 * SMMWB.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the * corresponding 32-bit elements of another register, and write the most significant 32-bit results to * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most * significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][47:16]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMWB_U(long a, unsigned long b) { register long result; __ASM volatile("smmwb.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.118.2. SMMWB.u ===== */ /* ===== Inline Function Start for 3.119.1. SMMWT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief SMMWT (SIMD MSW Signed Multiply Word and Top Half) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMWT Rd, Rs1, Rs2 * SMMWT.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, and write the most significant 32-bit results to * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most * significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][47:16]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMWT(long a, unsigned long b) { register long result; __ASM volatile("smmwt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.119.1. SMMWT ===== */ /* ===== Inline Function Start for 3.119.2. SMMWT.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC * \brief SMMWT.u (SIMD MSW Signed Multiply Word and Top Half with Rounding) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMMWT Rd, Rs1, Rs2 * SMMWT.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the * corresponding 32-bit elements of another register, and write the most significant 32-bit results to * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most * significant discarded bit. * * **Description**:\n * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results. * * **Operations**:\n * ~~~ * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1]; * if (`.u` form) { * Round[x][32:0] = Mres[x][47:15] + 1; * Rd.W[x] = Round[x][32:1]; * } else { * Rd.W[x] = Mres[x][47:16]; * } * for RV32: x=0 * for RV64: x=1...0 * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMMWT_U(long a, unsigned long b) { register long result; __ASM volatile("smmwt.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.119.2. SMMWT.u ===== */ /* ===== Inline Function Start for 3.120.1. SMSLDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMSLDA Rd, Rs1, Rs2 * SMSLXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a * register (RV64). The subtraction result is written back to the register-pair. * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements) * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated * as signed integers. * * **Operations**:\n * ~~~ * * RV32: * // SMSLDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); * // SMSLXDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); * * RV64: * // SMSLDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMSLXDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - * SE64(Mres1[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMSLDA(long long t, unsigned long a, unsigned long b) { __ASM volatile("smslda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.120.1. SMSLDA ===== */ /* ===== Inline Function Start for 3.120.2. SMSLXDA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB * \brief SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMSLDA Rd, Rs1, Rs2 * SMSLXDA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a * register (RV64). The subtraction result is written back to the register-pair. * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements) * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements) * * **RV32 Description**:\n * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated * as signed integers. * * **Operations**:\n * ~~~ * * RV32: * // SMSLDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); * // SMSLXDA * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); * * RV64: * // SMSLDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); * // SMSLXDA * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - * SE64(Mres1[1][31:0]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMSLXDA(long long t, unsigned long a, unsigned long b) { __ASM volatile("smslxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.120.2. SMSLXDA ===== */ /* ===== Inline Function Start for 3.121. SMSR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief SMSR64 (Signed Multiply and Subtract from 64- Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SMSR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is * written back to the pair of registers (RV32) or a register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers * specified by Rd(4,1). The subtraction result is written back to the even/odd pair of registers * specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It * subtracts the 64-bit multiplication results from the 64-bit signed data of Rd. The subtraction result is * written back to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H].R[t_L] = R[t_H].R[t_L] - (Rs1 * Rs2); * * RV64: * Rd = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); * ~~~ * * \param [in] t long long type of value stored in t * \param [in] a long type of value stored in a * \param [in] b long type of value stored in b * \return value stored in long long type */ __STATIC_FORCEINLINE long long __RV_SMSR64(long long t, long a, long b) { __ASM volatile("smsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.121. SMSR64 ===== */ /* ===== Inline Function Start for 3.122.1. SMUL8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY * \brief SMUL8 (SIMD Signed 8-bit Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMUL8 Rd, Rs1, Rs2 * SMULX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do signed 8-bit multiplications and generate four 16-bit results simultaneously. * * **RV32 Description**:\n * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the * corresponding 8-bit data elements of Rs2. * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1). * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom * part of Rs1. * * **RV64 Description**:\n * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the * corresponding 8-bit data elements of Rs2. * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from * the bottom part of Rs1. * * **Operations**:\n * ~~~ * * RV32: * if (is `SMUL8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom * } else if (is `SMULX8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom * } * rest[x/2] = op1t[x/2] s* op2t[x/2]; * resb[x/2] = op1b[x/2] s* op2b[x/2]; * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1]; * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0]; * x = 0 and 2 * * RV64: * if (is `SMUL8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom * } else if (is `SMULX8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom * } * rest[x/2] = op1t[x/2] s* op2t[x/2]; * resb[x/2] = op1b[x/2] s* op2b[x/2]; * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1]; * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0]; * x = 0 and 2 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_SMUL8(unsigned int a, unsigned int b) { register unsigned long long result; __ASM volatile("smul8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.122.1. SMUL8 ===== */ /* ===== Inline Function Start for 3.122.2. SMULX8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY * \brief SMULX8 (SIMD Signed Crossed 8-bit Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMUL8 Rd, Rs1, Rs2 * SMULX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do signed 8-bit multiplications and generate four 16-bit results simultaneously. * * **RV32 Description**:\n * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the * corresponding 8-bit data elements of Rs2. * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1). * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom * part of Rs1. * * **RV64 Description**:\n * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the * corresponding 8-bit data elements of Rs2. * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data * elements of Rs1 with the fourth and third 8-bit data elements of Rs2. * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from * the bottom part of Rs1. * * **Operations**:\n * ~~~ * * RV32: * if (is `SMUL8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom * } else if (is `SMULX8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom * } * rest[x/2] = op1t[x/2] s* op2t[x/2]; * resb[x/2] = op1b[x/2] s* op2b[x/2]; * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1]; * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0]; * x = 0 and 2 * * RV64: * if (is `SMUL8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom * } else if (is `SMULX8`) { * op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top * op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom * } * rest[x/2] = op1t[x/2] s* op2t[x/2]; * resb[x/2] = op1b[x/2] s* op2b[x/2]; * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1]; * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0]; * x = 0 and 2 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_SMULX8(unsigned int a, unsigned int b) { register unsigned long long result; __ASM volatile("smulx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.122.2. SMULX8 ===== */ /* ===== Inline Function Start for 3.123.1. SMUL16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY * \brief SMUL16 (SIMD Signed 16-bit Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMUL16 Rd, Rs1, Rs2 * SMULX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do signed 16-bit multiplications and generate two 32-bit results simultaneously. * * **RV32 Description**:\n * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 * with the bottom 16-bit Q15 content of Rs2. * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16- * bit Q15 content of Rs2. * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1), * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes * register 2d and 2d+1. * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1. * * **RV64 Description**:\n * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15 * content of the lower 32-bit word in Rs2. * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1 * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the * lower 32-bit word in Rs2. * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of * the lower 32-bit word in Rs1 is written to Rd.W[0] * * **Operations**:\n * ~~~ * * RV32: * if (is `SMUL16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom * } else if (is `SMULX16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * res = aop s* bop; * } * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H] = rest; * R[t_L] = resb; * * RV64: * if (is `SMUL16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom * } else if (is `SMULX16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * res = aop s* bop; * } * Rd.W[1] = rest; * Rd.W[0] = resb; * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_SMUL16(unsigned int a, unsigned int b) { register unsigned long long result; __ASM volatile("smul16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.123.1. SMUL16 ===== */ /* ===== Inline Function Start for 3.123.2. SMULX16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY * \brief SMULX16 (SIMD Signed Crossed 16-bit Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SMUL16 Rd, Rs1, Rs2 * SMULX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do signed 16-bit multiplications and generate two 32-bit results simultaneously. * * **RV32 Description**:\n * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 * with the bottom 16-bit Q15 content of Rs2. * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16- * bit Q15 content of Rs2. * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1), * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes * register 2d and 2d+1. * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1. * * **RV64 Description**:\n * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15 * content of the lower 32-bit word in Rs2. * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1 * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the * lower 32-bit word in Rs2. * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of * the lower 32-bit word in Rs1 is written to Rd.W[0] * * **Operations**:\n * ~~~ * * RV32: * if (is `SMUL16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom * } else if (is `SMULX16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * res = aop s* bop; * } * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H] = rest; * R[t_L] = resb; * * RV64: * if (is `SMUL16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top * op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom * } else if (is `SMULX16`) { * op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top * op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom * } * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * res = aop s* bop; * } * Rd.W[1] = rest; * Rd.W[0] = resb; * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_SMULX16(unsigned int a, unsigned int b) { register unsigned long long result; __ASM volatile("smulx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.123.2. SMULX16 ===== */ /* ===== Inline Function Start for 3.124. SRA.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief SRA.u (Rounding Shift Right Arithmetic) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SRA.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform an arithmetic right shift operation with rounding. The shift amount is a variable * from a GPR. * * **Description**:\n * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are * filled with the sign-bit and the shift amount is specified by the low-order 5-bits (RV32) or 6-bits * (RV64) of the Rs2 register. For the rounding operation, a value of 1 is added to the most significant * discarded bit of the data to calculate the final result. And the result is written to Rd. * * **Operations**:\n * ~~~ * * RV32: * sa = Rs2[4:0]; * if (sa > 0) { * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; * Rd = res[31:0]; * } else { * Rd = Rs1; * } * * RV64: * sa = Rs2[5:0]; * if (sa > 0) { * res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1; * Rd = res[63:0]; * } else { * Rd = Rs1; * } * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SRA_U(long a, unsigned int b) { register long result; __ASM volatile("sra.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.124. SRA.u ===== */ /* ===== Inline Function Start for 3.125. SRAI.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief SRAI.u (Rounding Shift Right Arithmetic Immediate) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SRAI.u Rd, Rs1, imm6u[4:0] (RV32) * SRAI.u Rd, Rs1, imm6u[5:0] (RV64) * ~~~ * * **Purpose**:\n * Perform an arithmetic right shift operation with rounding. The shift amount is an * immediate value. * * **Description**:\n * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are * filled with the sign-bit and the shift amount is specified by the imm6u[4:0] (RV32) or imm6u[5:0] * (RV64) constant . For the rounding operation, a value of 1 is added to the most significant discarded * bit of the data to calculate the final result. And the result is written to Rd. * * **Operations**:\n * ~~~ * * RV32: * sa = imm6u[4:0]; * if (sa > 0) { * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; * Rd = res[31:0]; * } else { * Rd = Rs1; * } * * RV64: * sa = imm6u[5:0]; * if (sa > 0) { * res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1; * Rd = res[63:0]; * } else { * Rd = Rs1; * } * ~~~ * * \param [in] a long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ #define __RV_SRAI_U(a, b) \ ({ \ register long result; \ register long __a = (long)(a); \ __ASM volatile("srai.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.125. SRAI.u ===== */ /* ===== Inline Function Start for 3.126.1. SRA8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRA8 (SIMD 8-bit Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRA8 Rd, Rs1, Rs2 * SRA8.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 8-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * if (sa > 0) { * if (`.u` form) { // SRA8.u * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { // SRA8 * Rd.B[x] = SE8(Rd.B[x][7:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA8(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.126.1. SRA8 ===== */ /* ===== Inline Function Start for 3.126.2. SRA8.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRA8.u (SIMD 8-bit Rounding Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRA8 Rd, Rs1, Rs2 * SRA8.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 8-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * if (sa > 0) { * if (`.u` form) { // SRA8.u * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { // SRA8 * Rd.B[x] = SE8(Rd.B[x][7:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA8_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.126.2. SRA8.u ===== */ /* ===== Inline Function Start for 3.127.1. SRAI8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRAI8 (SIMD 8-bit Shift Right Arithmetic Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRAI8 Rd, Rs1, imm3u * SRAI8.u Rd, Rs1, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 8-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * if (sa > 0) { * if (`.u` form) { // SRA8.u * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { // SRA8 * Rd.B[x] = SE8(Rd.B[x][7:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRAI8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srai8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.127.1. SRAI8 ===== */ /* ===== Inline Function Start for 3.127.2. SRAI8.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRAI8.u (SIMD 8-bit Rounding Shift Right Arithmetic Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRAI8 Rd, Rs1, imm3u * SRAI8.u Rd, Rs1, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 8-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * if (sa > 0) { * if (`.u` form) { // SRA8.u * res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[7:0]; * } else { // SRA8 * Rd.B[x] = SE8(Rd.B[x][7:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRAI8_U(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srai8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.127.2. SRAI8.u ===== */ /* ===== Inline Function Start for 3.128.1. SRA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRA16 (SIMD 16-bit Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRA16 Rd, Rs1, Rs2 * SRA16.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 16-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * if (sa != 0) { * if (`.u` form) { // SRA16.u * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { // SRA16 * Rd.H[x] = SE16(Rs1.H[x][15:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("sra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.128.1. SRA16 ===== */ /* ===== Inline Function Start for 3.128.2. SRA16.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRA16.u (SIMD 16-bit Rounding Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRA16 Rd, Rs1, Rs2 * SRA16.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 16-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * if (sa != 0) { * if (`.u` form) { // SRA16.u * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { // SRA16 * Rd.H[x] = SE16(Rs1.H[x][15:sa]) * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("sra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.128.2. SRA16.u ===== */ /* ===== Inline Function Start for 3.129.1. SRAI16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRAI16 (SIMD 16-bit Shift Right Arithmetic Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRAI16 Rd, Rs1, imm4u * SRAI16.u Rd, Rs1, imm4u * ~~~ * * **Purpose**:\n * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is * an immediate value. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most * significant discarded bit of each 16-bit data to calculate the final results. And the results are written * to Rd. * * **Operations**:\n * ~~~ * sa = imm4u[3:0]; * if (sa > 0) { * if (`.u` form) { // SRAI16.u * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { // SRAI16 * Rd.H[x] = SE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRAI16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srai16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.129.1. SRAI16 ===== */ /* ===== Inline Function Start for 3.129.2. SRAI16.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRAI16.u (SIMD 16-bit Rounding Shift Right Arithmetic Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRAI16 Rd, Rs1, imm4u * SRAI16.u Rd, Rs1, imm4u * ~~~ * * **Purpose**:\n * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is * an immediate value. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most * significant discarded bit of each 16-bit data to calculate the final results. And the results are written * to Rd. * * **Operations**:\n * ~~~ * sa = imm4u[3:0]; * if (sa > 0) { * if (`.u` form) { // SRAI16.u * res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[15:0]; * } else { // SRAI16 * Rd.H[x] = SE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRAI16_U(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srai16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.129.2. SRAI16.u ===== */ /* ===== Inline Function Start for 3.130.1. SRL8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRL8 (SIMD 8-bit Shift Right Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRL8 Rt, Ra, Rb * SRL8.u Rt, Ra, Rb * ~~~ * * **Purpose**:\n * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register. * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded * bit of each 8-bit data element to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * if (sa > 0) { * if (`.u` form) { // SRL8.u * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[8:1]; * } else { // SRL8 * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL8(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.130.1. SRL8 ===== */ /* ===== Inline Function Start for 3.130.2. SRL8.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRL8.u (SIMD 8-bit Rounding Shift Right Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRL8 Rt, Ra, Rb * SRL8.u Rt, Ra, Rb * ~~~ * * **Purpose**:\n * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register. * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded * bit of each 8-bit data element to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[2:0]; * if (sa > 0) { * if (`.u` form) { // SRL8.u * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[8:1]; * } else { // SRL8 * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL8_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.130.2. SRL8.u ===== */ /* ===== Inline Function Start for 3.131.1. SRLI8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRLI8 (SIMD 8-bit Shift Right Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRLI8 Rt, Ra, imm3u * SRLI8.u Rt, Ra, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to * calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * if (sa > 0) { * if (`.u` form) { // SRLI8.u * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[8:1]; * } else { // SRLI8 * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRLI8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.131.1. SRLI8 ===== */ /* ===== Inline Function Start for 3.131.2. SRLI8.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT * \brief SRLI8.u (SIMD 8-bit Rounding Shift Right Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRLI8 Rt, Ra, imm3u * SRLI8.u Rt, Ra, imm3u * ~~~ * * **Purpose**:\n * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to * calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm3u[2:0]; * if (sa > 0) { * if (`.u` form) { // SRLI8.u * res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1; * Rd.B[x] = res[8:1]; * } else { // SRLI8 * Rd.B[x] = ZE8(Rs1.B[x][7:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRLI8_U(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srli8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.131.2. SRLI8.u ===== */ /* ===== Inline Function Start for 3.132.1. SRL16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRL16 (SIMD 16-bit Shift Right Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRL16 Rt, Ra, Rb * SRL16.u Rt, Ra, Rb * ~~~ * * **Purpose**:\n * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 16-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * if (sa > 0) { * if (`.u` form) { // SRL16.u * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[16:1]; * } else { // SRL16 * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.132.1. SRL16 ===== */ /* ===== Inline Function Start for 3.132.2. SRL16.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRL16.u (SIMD 16-bit Rounding Shift Right Logical) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRL16 Rt, Ra, Rb * SRL16.u Rt, Ra, Rb * ~~~ * * **Purpose**:\n * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 16-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = Rs2[3:0]; * if (sa > 0) { * if (`.u` form) { // SRL16.u * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[16:1]; * } else { // SRL16 * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.132.2. SRL16.u ===== */ /* ===== Inline Function Start for 3.133.1. SRLI16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRLI16 (SIMD 16-bit Shift Right Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRLI16 Rt, Ra, imm4u * SRLI16.u Rt, Ra, imm4u * ~~~ * * **Purpose**:\n * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit * data element to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm4u; * if (sa > 0) { * if (`.u` form) { // SRLI16.u * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[16:1]; * } else { // SRLI16 * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRLI16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.133.1. SRLI16 ===== */ /* ===== Inline Function Start for 3.133.2. SRLI16.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT * \brief SRLI16.u (SIMD 16-bit Rounding Shift Right Logical Immediate) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SRLI16 Rt, Ra, imm4u * SRLI16.u Rt, Ra, imm4u * ~~~ * * **Purpose**:\n * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit * data element to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm4u; * if (sa > 0) { * if (`.u` form) { // SRLI16.u * res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1; * Rd.H[x] = res[16:1]; * } else { // SRLI16 * Rd.H[x] = ZE16(Rs1.H[x][15:sa]); * } * } else { * Rd = Rs1; * } * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_SRLI16_U(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("srli16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.133.2. SRLI16.u ===== */ /* ===== Inline Function Start for 3.134. STAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief STAS16 (SIMD 16-bit Straight Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * STAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. * * **Description**:\n * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with * the 16-bit integer element in [31:16] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [15:0] of 32-bit chunks in * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32- * bit chunks in Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][31:16]; * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][15:0]; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_STAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("stas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.134. STAS16 ===== */ /* ===== Inline Function Start for 3.135. STSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief STSA16 (SIMD 16-bit Straight Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * STSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. * * **Description**:\n * This instruction subtracts the 16-bit integer element in [31:16] of 32-bit chunks in Rs2 * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [15:0] of 32-bit chunks in * Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to [15:0] of * 32-bit chunks in Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][31:16]; * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][15:0]; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_STSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("stsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.135. STSA16 ===== */ /* ===== Inline Function Start for 3.136. SUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief SUB8 (SIMD 8-bit Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SUB8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit integer element subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 8-bit integer elements in Rs2 from the 8-bit integer * elements in Rs1, and then writes the result to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned subtraction. * * **Operations**:\n * ~~~ * Rd.B[x] = Rs1.B[x] - Rs2.B[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUB8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("sub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.136. SUB8 ===== */ /* ===== Inline Function Start for 3.137. SUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief SUB16 (SIMD 16-bit Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * SUB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit integer element subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 16-bit integer elements in Rs2 from the 16-bit integer * elements in Rs1, and then writes the result to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned subtraction. * * **Operations**:\n * ~~~ * Rd.H[x] = Rs1.H[x] - Rs2.H[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("sub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.137. SUB16 ===== */ /* ===== Inline Function Start for 3.138. SUB64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief SUB64 (64-bit Subtraction) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * SUB64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a 64-bit signed or unsigned integer subtraction. * * **RV32 Description**:\n * This instruction subtracts the 64-bit integer of an even/odd pair of registers * specified by Rs2(4,1) from the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1), * and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * This instruction subtracts the 64-bit integer of Rs2 from the 64-bit integer of Rs1, * and then writes the 64-bit result to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned subtraction. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * R[t_H].R[t_L] = R[a_H].R[a_L] - R[b_H].R[b_L]; * * RV64: * Rd = Rs1 - Rs2; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_SUB64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("sub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.138. SUB64 ===== */ /* ===== Inline Function Start for 3.139.1. SUNPKD810 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief SUNPKD810 (Signed Unpacking Bytes 1 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords * of 32-bit chunks in a register. * * **Description**:\n * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) * // SUNPKD810, x=1,y=0 * // SUNPKD820, x=2,y=0 * // SUNPKD830, x=3,y=0 * // SUNPKD831, x=3,y=1 * // SUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUNPKD810(unsigned long a) { register unsigned long result; __ASM volatile("sunpkd810 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.139.1. SUNPKD810 ===== */ /* ===== Inline Function Start for 3.139.2. SUNPKD820 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief SUNPKD820 (Signed Unpacking Bytes 2 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords * of 32-bit chunks in a register. * * **Description**:\n * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) * // SUNPKD810, x=1,y=0 * // SUNPKD820, x=2,y=0 * // SUNPKD830, x=3,y=0 * // SUNPKD831, x=3,y=1 * // SUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUNPKD820(unsigned long a) { register unsigned long result; __ASM volatile("sunpkd820 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.139.2. SUNPKD820 ===== */ /* ===== Inline Function Start for 3.139.3. SUNPKD830 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief SUNPKD830 (Signed Unpacking Bytes 3 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords * of 32-bit chunks in a register. * * **Description**:\n * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) * // SUNPKD810, x=1,y=0 * // SUNPKD820, x=2,y=0 * // SUNPKD830, x=3,y=0 * // SUNPKD831, x=3,y=1 * // SUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUNPKD830(unsigned long a) { register unsigned long result; __ASM volatile("sunpkd830 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.139.3. SUNPKD830 ===== */ /* ===== Inline Function Start for 3.139.4. SUNPKD831 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief SUNPKD831 (Signed Unpacking Bytes 3 & 1) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords * of 32-bit chunks in a register. * * **Description**:\n * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) * // SUNPKD810, x=1,y=0 * // SUNPKD820, x=2,y=0 * // SUNPKD830, x=3,y=0 * // SUNPKD831, x=3,y=1 * // SUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUNPKD831(unsigned long a) { register unsigned long result; __ASM volatile("sunpkd831 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.139.4. SUNPKD831 ===== */ /* ===== Inline Function Start for 3.139.5. SUNPKD832 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief SUNPKD832 (Signed Unpacking Bytes 3 & 2) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords * of 32-bit chunks in a register. * * **Description**:\n * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y]) * // SUNPKD810, x=1,y=0 * // SUNPKD820, x=2,y=0 * // SUNPKD830, x=3,y=0 * // SUNPKD831, x=3,y=1 * // SUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUNPKD832(unsigned long a) { register unsigned long result; __ASM volatile("sunpkd832 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.139.5. SUNPKD832 ===== */ /* ===== Inline Function Start for 3.140. SWAP8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief SWAP8 (Swap Byte within Halfword) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SWAP8 Rd, Rs1 * ~~~ * * **Purpose**:\n * Swap the bytes within each halfword of a register. * * **Description**:\n * This instruction swaps the bytes within each halfword of Rs1 and writes the result to * Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = CONCAT(Rs1.H[x][7:0],Rs1.H[x][15:8]); * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SWAP8(unsigned long a) { register unsigned long result; __ASM volatile("swap8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.140. SWAP8 ===== */ /* ===== Inline Function Start for 3.141. SWAP16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief SWAP16 (Swap Halfword within Word) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * SWAP16 Rd, Rs1 * ~~~ * * **Purpose**:\n * Swap the 16-bit halfwords within each word of a register. * * **Description**:\n * This instruction swaps the 16-bit halfwords within each word of Rs1 and writes the * result to Rd. * * **Operations**:\n * ~~~ * Rd.W[x] = CONCAT(Rs1.W[x][15:0],Rs1.H[x][31:16]); * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SWAP16(unsigned long a) { register unsigned long result; __ASM volatile("swap16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.141. SWAP16 ===== */ /* ===== Inline Function Start for 3.142. UCLIP8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief UCLIP8 (SIMD 8-bit Unsigned Clip Value) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCLIP8 Rt, Ra, imm3u * ~~~ * * **Purpose**:\n * Limit the 8-bit signed elements of a register into an unsigned range simultaneously. * * **Description**:\n * This instruction limits the 8-bit signed elements stored in Rs1 into an unsigned integer * range between 2^imm3u-1 and 0, and writes the limited results to Rd. For example, if imm3u is 3, the 8- * bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.H[x]; * if (src > (2^imm3u)-1) { * src = (2^imm3u)-1; * OV = 1; * } else if (src < 0) { * src = 0; * OV = 1; * } * Rd.H[x] = src; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_UCLIP8(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("uclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.142. UCLIP8 ===== */ /* ===== Inline Function Start for 3.143. UCLIP16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief UCLIP16 (SIMD 16-bit Unsigned Clip Value) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCLIP16 Rt, Ra, imm4u * ~~~ * * **Purpose**:\n * Limit the 16-bit signed elements of a register into an unsigned range simultaneously. * * **Description**:\n * This instruction limits the 16-bit signed elements stored in Rs1 into an unsigned * integer range between 2imm4u-1 and 0, and writes the limited results to Rd. For example, if imm4u is * 3, the 16-bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit * to 1. * * **Operations**:\n * ~~~ * src = Rs1.H[x]; * if (src > (2^imm4u)-1) { * src = (2^imm4u)-1; * OV = 1; * } else if (src < 0) { * src = 0; * OV = 1; * } * Rd.H[x] = src; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_UCLIP16(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("uclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.143. UCLIP16 ===== */ /* ===== Inline Function Start for 3.144. UCLIP32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC * \brief UCLIP32 (SIMD 32-bit Unsigned Clip Value) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCLIP32 Rd, Rs1, imm5u[4:0] * ~~~ * * **Purpose**:\n * Limit the 32-bit signed integer elements of a register into an unsigned range * simultaneously. * * **Description**:\n * This instruction limits the 32-bit signed integer elements stored in Rs1 into an * unsigned integer range between 2imm5u-1 and 0, and writes the limited results to Rd. For example, if * imm5u is 3, the 32-bit input values should be saturated between 7 and 0. If saturation is performed, * set OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.W[x]; * if (src > (2^imm5u)-1) { * src = (2^imm5u)-1; * OV = 1; * } else if (src < 0) { * src = 0; * OV = 1; * } * Rd.W[x] = src * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_UCLIP32(a, b) \ ({ \ register unsigned long result; \ register unsigned long __a = (unsigned long)(a); \ __ASM volatile("uclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.144. UCLIP32 ===== */ /* ===== Inline Function Start for 3.145. UCMPLE8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP * \brief UCMPLE8 (SIMD 8-bit Unsigned Compare Less Than & Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCMPLE8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer elements less than & equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it * is true, the result is 0xFF; otherwise, the result is 0x0. The four comparison results are written to * Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] <=u Rs2.B[x])? 0xff : 0x0; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UCMPLE8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ucmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.145. UCMPLE8 ===== */ /* ===== Inline Function Start for 3.146. UCMPLE16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP * \brief UCMPLE16 (SIMD 16-bit Unsigned Compare Less Than & Equal) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCMPLE16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer elements less than & equal comparisons simultaneously. * * **Description**:\n * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it * is true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are * written to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] <=u Rs2.H[x])? 0xffff : 0x0; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UCMPLE16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ucmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.146. UCMPLE16 ===== */ /* ===== Inline Function Start for 3.147. UCMPLT8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP * \brief UCMPLT8 (SIMD 8-bit Unsigned Compare Less Than) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UCMPLT8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer elements less than comparisons simultaneously. * * **Description**:\n * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit * unsigned integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] (2^8)-1) { * res[x] = (2^8)-1; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKADD8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.149. UKADD8 ===== */ /* ===== Inline Function Start for 3.150. UKADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKADD16 (SIMD 16-bit Unsigned Saturating Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKADD16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit * unsigned integer elements in Rs2. If any of the results are beyond the 16-bit unsigned number * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] + Rs2.H[x]; * if (res[x] > (2^16)-1) { * res[x] = (2^16)-1; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKADD16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.150. UKADD16 ===== */ /* ===== Inline Function Start for 3.151. UKADD64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief UKADD64 (64-bit Unsigned Saturating Addition) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * UKADD64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add two 64-bit unsigned integers. The result is saturated to the U64 range. * * **RV32 Description**:\n * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by * Rs2(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers * specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned * integer in Rs2. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to * the range and the OV bit is set to 1. The saturated result is written to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); * result = R[a_H].R[a_L] + R[b_H].R[b_L]; * if (result > (2^64)-1) { * result = (2^64)-1; OV = 1; * } * R[t_H].R[t_L] = result; * * RV64: * result = Rs1 + Rs2; * if (result > (2^64)-1) { * result = (2^64)-1; OV = 1; * } * Rd = result; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_UKADD64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("ukadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.151. UKADD64 ===== */ /* ===== Inline Function Start for 3.152. UKADDH ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief UKADDH (Unsigned Addition with U16 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * UKADDH Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add the unsigned lower 32-bit content of two registers with U16 saturation. * * **Description**:\n * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit * content of Rs2. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] + Rs2.W[0]; * if (tmp > (2^16)-1) { * tmp = (2^16)-1; * OV = 1; * } * Rd = SE(tmp[15:0]); * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKADDH(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("ukaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.152. UKADDH ===== */ /* ===== Inline Function Start for 3.153. UKADDW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief UKADDW (Unsigned Addition with U32 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * UKADDW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add the unsigned lower 32-bit content of two registers with U32 saturation. * * **Description**:\n * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit * content of Rs2. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] + Rs2.W[0]; * if (tmp > (2^32)-1) { * tmp[31:0] = (2^32)-1; * OV = 1; * } * Rd = tmp[31:0]; // RV32 * Rd = SE(tmp[31:0]); // RV64 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKADDW(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("ukaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.153. UKADDW ===== */ /* ===== Inline Function Start for 3.154. UKCRAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKCRAS16 (SIMD 16-bit Unsigned Saturating Cross Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKCRAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed * positions in 32-bit chunks. * * **Description**:\n * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it * subtracts the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit * chunks in Rd for subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0]; * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16]; * if (res1 > (2^16)-1) { * res1 = (2^16)-1; * OV = 1; * } * if (res2 < 0) { * res2 = 0; * OV = 1; * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKCRAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.154. UKCRAS16 ===== */ /* ===== Inline Function Start for 3.155. UKCRSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKCRSA16 (SIMD 16-bit Unsigned Saturating Cross Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKCRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from crossed * positions in 32-bit chunks. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer element in [15:0] of 32-bit * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the * same time, it adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 with the 16- * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of * 32-bit chunks in Rd for addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0]; * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16]; * if (res1 < 0) { * res1 = 0; * OV = 1; * } else if (res2 > (2^16)-1) { * res2 = (2^16)-1; * OV = 1; * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKCRSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.155. UKCRSA16 ===== */ /* ===== Inline Function Start for 3.156. UKMAR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief UKMAR64 (Unsigned Multiply and Saturating Add to 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * UKMAR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is * saturated to the U64 range and written back to the pair of registers (RV32) or the register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers * specified by Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the U64 number * range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is * written back to the even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. * It adds the 64-bit multiplication results to the 64-bit unsigned data in Rd with unlimited precision. If * the 64-bit addition result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the * range and the OV bit is set to 1. The saturated result is written back to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * result = R[t_H].R[t_L] + (Rs1 * Rs2); * if (result > (2^64)-1) { * result = (2^64)-1; OV = 1; * } * R[t_H].R[t_L] = result; * * RV64: * // `result` has unlimited precision * result = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]); * if (result > (2^64)-1) { * result = (2^64)-1; OV = 1; * } * Rd = result; * ~~~ * * \param [in] t unsigned long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_UKMAR64(unsigned long long t, unsigned long a, unsigned long b) { __ASM volatile("ukmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.156. UKMAR64 ===== */ /* ===== Inline Function Start for 3.157. UKMSR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief UKMSR64 (Unsigned Multiply and Saturating Subtract from 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * UKMSR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit unsigned elements in two registers and subtract the 64-bit * multiplication results from the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). * The result is saturated to the U64 range and written back to the pair of registers (RV32) or a register * (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It * subtracts the 64-bit multiplication result from the 64-bit unsigned data of an even/odd pair of * registers specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the * U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The * saturated result is written back to the even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. * It subtracts the 64-bit multiplication results from the 64-bit unsigned data of Rd with unlimited * precision. If the 64-bit subtraction result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * result = R[t_H].R[t_L] - (Rs1 u* Rs2); * if (result < 0) { * result = 0; OV = 1; * } * R[t_H].R[t_L] = result; * * RV64: * // `result` has unlimited precision * result = Rd - (Rs1.W[0] u* Rs2.W[0]) - (Rs1.W[1] u* Rs2.W[1]); * if (result < 0) { * result = 0; OV = 1; * } * Rd = result; * ~~~ * * \param [in] t unsigned long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_UKMSR64(unsigned long long t, unsigned long a, unsigned long b) { __ASM volatile("ukmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.157. UKMSR64 ===== */ /* ===== Inline Function Start for 3.158. UKSTAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKSTAS16 (SIMD 16-bit Unsigned Saturating Straight Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKSTAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from * corresponding positions in 32-bit chunks. * * **Description**:\n * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in * Rs1 with the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it * subtracts the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit * chunks in Rd for subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16]; * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0]; * if (res1 > (2^16)-1) { * res1 = (2^16)-1; * OV = 1; * } * if (res2 < 0) { * res2 = 0; * OV = 1; * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSTAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.158. UKSTAS16 ===== */ /* ===== Inline Function Start for 3.159. UKSTSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKSTSA16 (SIMD 16-bit Unsigned Saturating Straight Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKSTSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from * corresponding positions in 32-bit chunks. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer element in [31:16] of 32-bit * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the * same time, it adds the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 with the 16- * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of * 32-bit chunks in Rd for addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16]; * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0]; * if (res1 < 0) { * res1 = 0; * OV = 1; * } else if (res2 > (2^16)-1) { * res2 = (2^16)-1; * OV = 1; * } * Rd.W[x][31:16] = res1; * Rd.W[x][15:0] = res2; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSTSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.159. UKSTSA16 ===== */ /* ===== Inline Function Start for 3.160. UKSUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief UKSUB8 (SIMD 8-bit Unsigned Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKSUB8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit * unsigned integer elements in Rs1. If any of the results are beyond the 8-bit unsigned number range * (0 <= RES <= 28-1), they are saturated to the range and the OV bit is set to 1. The saturated results are * written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.B[x] - Rs2.B[x]; * if (res[x] < 0) { * res[x] = 0; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSUB8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.160. UKSUB8 ===== */ /* ===== Inline Function Start for 3.161. UKSUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief UKSUB16 (SIMD 16-bit Unsigned Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UKSUB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit * unsigned integer elements in Rs1. If any of the results are beyond the 16-bit unsigned number * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] - Rs2.H[x]; * if (res[x] < 0) { * res[x] = 0; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSUB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.161. UKSUB16 ===== */ /* ===== Inline Function Start for 3.162. UKSUB64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief UKSUB64 (64-bit Unsigned Saturating Subtraction) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * UKSUB64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a 64-bit signed integer subtraction. The result is saturated to the U64 range. * * **RV32 Description**:\n * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers * specified by Rs1(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd * pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d` * register of the pair contains the low 32-bit of the operand. * * **RV64 Description**:\n * This instruction subtracts the 64-bit unsigned integer of Rs2 from the 64-bit * unsigned integer of an even/odd pair of Rs1. If the 64-bit result is beyond the U64 number range (0 <= * U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written * to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1); * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1); * result = R[a_H].R[a_L] - R[b_H].R[b_L]; * if (result < 0) { * result = 0; OV = 1; * } * R[t_H].R[t_L] = result; * * RV64 * result = Rs1 - Rs2; * if (result < 0) { * result = 0; OV = 1; * } * Rd = result; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_UKSUB64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("uksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.162. UKSUB64 ===== */ /* ===== Inline Function Start for 3.163. UKSUBH ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU * \brief UKSUBH (Unsigned Subtraction with U16 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * UKSUBH Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract the unsigned lower 32-bit content of two registers with U16 saturation. * * **Description**:\n * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit * content of Rs1. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] - Rs2.W[0]; * if (tmp > (2^16)-1) { * tmp = (2^16)-1; * OV = 1; * } * else if (tmp < 0) { * tmp = 0; * OV = 1; * } * Rd = SE(tmp[15:0]); * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSUBH(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("uksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.163. UKSUBH ===== */ /* ===== Inline Function Start for 3.164. UKSUBW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU * \brief UKSUBW (Unsigned Subtraction with U32 Saturation) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * UKSUBW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract the unsigned lower 32-bit content of two registers with unsigned 32-bit * saturation. * * **Description**:\n * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit * content of Rs1. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag. * * **Operations**:\n * ~~~ * tmp = Rs1.W[0] - Rs2.W[0]; * if (tmp < 0) { * tmp[31:0] = 0; * OV = 1; * } * Rd = tmp[31:0]; // RV32 * Rd = SE(tmp[31:0]); // RV64 * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSUBW(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("uksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.164. UKSUBW ===== */ /* ===== Inline Function Start for 3.165. UMAR64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB * \brief UMAR64 (Unsigned Multiply and Add to 64-Bit Data) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * UMAR64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is * written back to the pair of registers (RV32) or a register (RV64). * * **RV32 Description**:\n * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers * specified by Rd(4,1). The addition result is written back to the even/odd pair of registers specified by * Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2. * It adds the 64-bit multiplication results to the 64-bit unsigned data of Rd. The addition result is * written back to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1); * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2); * * RV64: * Rd = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]); * ~~~ * * \param [in] t unsigned long long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_UMAR64(unsigned long long t, unsigned long a, unsigned long b) { __ASM volatile("umar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.165. UMAR64 ===== */ /* ===== Inline Function Start for 3.166. UMAQA ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD * \brief UMAQA (Unsigned Multiply Four Bytes with 32- bit Adds) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * UMAQA Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do four unsigned 8-bit multiplications from 32-bit chunks of two registers; and then adds * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together. * * **Description**:\n * This instruction multiplies the four unsigned 8-bit elements of 32-bit chunks of Rs1 with the four * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the * unsigned content of the corresponding 32-bit chunks of Rd. The final results are written back to the * corresponding 32-bit chunks in Rd. * * **Operations**:\n * ~~~ * res[x] = Rd.W[x] + (Rs1.W[x].B[3] u* Rs2.W[x].B[3]) + * (Rs1.W[x].B[2] u* Rs2.W[x].B[2]) + (Rs1.W[x].B[1] u* Rs2.W[x].B[1]) + * (Rs1.W[x].B[0] u* Rs2.W[x].B[0]); * Rd.W[x] = res[x]; * for RV32: x=0, * for RV64: x=1...0 * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UMAQA(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("umaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 3.166. UMAQA ===== */ /* ===== Inline Function Start for 3.167. UMAX8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief UMAX8 (SIMD 8-bit Unsigned Maximum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UMAX8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 8-bit unsigned integer elements in Rs1 with the four 8- * bit unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The * two selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] >u Rs2.B[x])? Rs1.B[x] : Rs2.B[x]; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UMAX8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("umax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.167. UMAX8 ===== */ /* ===== Inline Function Start for 3.168. UMAX16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC * \brief UMAX16 (SIMD 16-bit Unsigned Maximum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UMAX16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] >u Rs2.H[x])? Rs1.H[x] : Rs2.H[x]; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UMAX16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("umax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.168. UMAX16 ===== */ /* ===== Inline Function Start for 3.169. UMIN8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC * \brief UMIN8 (SIMD 8-bit Unsigned Minimum) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * UMIN8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer elements finding minimum operations simultaneously. * * **Description**:\n * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] > 1; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URADD8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uradd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.174. URADD8 ===== */ /* ===== Inline Function Start for 3.175. URADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URADD16 (SIMD 16-bit Unsigned Halving Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URADD16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element additions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit * unsigned integer elements in Rs2. The results are first logically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFF, Rb = 0x7FFF Rt = 0x7FFF * * Ra = 0x8000, Rb = 0x8000 Rt = 0x8000 * * Ra = 0x4000, Rb = 0x8000 Rt = 0x6000 * ~~~ * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) u>> 1; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URADD16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uradd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.175. URADD16 ===== */ /* ===== Inline Function Start for 3.176. URADD64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief URADD64 (64-bit Unsigned Halving Addition) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * URADD64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add two 64-bit unsigned integers. The result is halved to avoid overflow or saturation. * * **RV32 Description**:\n * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by * Rs2(4,1). The 64-bit addition result is first logically right-shifted by 1 bit and then written to an * even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned * integer Rs2. The 64-bit addition result is first logically right-shifted by 1 bit and then written to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) u>> 1; * * RV64: * Rd = (Rs1 + Rs2) u>> 1; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_URADD64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("uradd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.176. URADD64 ===== */ /* ===== Inline Function Start for 3.177. URADDW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief URADDW (32-bit Unsigned Halving Addition) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * URADDW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Add 32-bit unsigned integers and the results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the first 32-bit unsigned integer in Rs1 with the first 32-bit * unsigned integer in Rs2. The result is first logically right-shifted by 1 bit and then sign-extended and * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFFFFFF, Rb = 0x7FFFFFFF Rt = 0x7FFFFFFF * * Ra = 0x80000000, Rb = 0x80000000 Rt = 0x80000000 * * Ra = 0x40000000, Rb = 0x80000000 Rt = 0x60000000 * ~~~ * * **Operations**:\n * ~~~ * * RV32: * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1; * * RV64: * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1; * Rd[63:0] = SE(resw[31:0]); * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URADDW(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("uraddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.177. URADDW ===== */ /* ===== Inline Function Start for 3.178. URCRAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URCRAS16 (SIMD 16-bit Unsigned Halving Cross Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URCRAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element * subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. * The results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1 * with the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned * integer in [31:16] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32- * bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `URADD16` and `URSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) u>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) u>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URCRAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.178. URCRAS16 ===== */ /* ===== Inline Function Start for 3.179. URCRSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URCRSA16 (SIMD 16-bit Unsigned Halving Cross Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URCRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element * addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. * The results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2 * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [31:16] of 32-bit chunks * in Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit * chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `URADD16` and `URSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) u>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) u>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URCRSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.179. URCRSA16 ===== */ /* ===== Inline Function Start for 3.180. URSTAS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URSTAS16 (SIMD 16-bit Unsigned Halving Straight Addition & Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URSTAS16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element * subtraction in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit * chunks. The results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1 * with the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned * integer in [15:0] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32- * bit chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `URADD16` and `URSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) u>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) u>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSTAS16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.180. URSTAS16 ===== */ /* ===== Inline Function Start for 3.181. URSTSA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URSTSA16 (SIMD 16-bit Unsigned Halving Straight Subtraction & Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URCRSA16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element * addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit * chunks. The results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2 * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [15:0] of 32-bit chunks in * Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit * chunks in Rd and [15:0] of 32-bit chunks in Rd. * * **Examples**:\n * ~~~ * Please see `URADD16` and `URSUB16` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) u>> 1; * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) u>> 1; * for RV32, x=0 * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSTSA16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.181. URSTSA16 ===== */ /* ===== Inline Function Start for 3.182. URSUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB * \brief URSUB8 (SIMD 8-bit Unsigned Halving Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URSUB8 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 8-bit unsigned integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7F, Rb = 0x80 Rt = 0xFF * * Ra = 0x80, Rb = 0x7F Rt = 0x00 * * Ra = 0x80, Rb = 0x40 Rt = 0x20 * ~~~ * * **Operations**:\n * ~~~ * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) u>> 1; * for RV32: x=3...0, * for RV64: x=7...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSUB8(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ursub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.182. URSUB8 ===== */ /* ===== Inline Function Start for 3.183. URSUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB * \brief URSUB16 (SIMD 16-bit Unsigned Halving Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * URSUB16 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 16-bit unsigned integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFF, Rb = 0x8000 Rt = 0xFFFF * * Ra = 0x8000, Rb = 0x7FFF Rt = 0x0000 * * Ra = 0x8000, Rb = 0x4000 Rt = 0x2000 * ~~~ * * **Operations**:\n * ~~~ * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) u>> 1; * for RV32: x=1...0, * for RV64: x=3...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSUB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ursub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.183. URSUB16 ===== */ /* ===== Inline Function Start for 3.184. URSUB64 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB * \brief URSUB64 (64-bit Unsigned Halving Subtraction) * \details * **Type**: DSP (64-bit Profile) * * **Syntax**:\n * ~~~ * URSUB64 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Perform a 64-bit unsigned integer subtraction. The result is halved to avoid overflow or * saturation. * * **RV32 Description**:\n * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers * specified by Rs1(4,1). The subtraction result is first logically right-shifted by 1 bit and then written * to an even/odd pair of registers specified by Rd(4,1). * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair * includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register * of the pair contains the low 32-bit of the result. * * **RV64 Description**:\n * This instruction subtracts the 64-bit unsigned integer in Rs2 from the 64-bit * unsigned integer in Rs1. The subtraction result is first logically right-shifted by 1 bit and then * written to Rd. * * **Operations**:\n * ~~~ * * RV32: * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1); * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1); * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1); * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) u>> 1; * * RV64: * Rd = (Rs1 - Rs2) u>> 1; * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_URSUB64(unsigned long long a, unsigned long long b) { register unsigned long long result; __ASM volatile("ursub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.184. URSUB64 ===== */ /* ===== Inline Function Start for 3.185. URSUBW ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION * \brief URSUBW (32-bit Unsigned Halving Subtraction) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * URSUBW Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Subtract 32-bit unsigned integers and the result is halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit * signed integer in Rs1. The result is first logically right-shifted by 1 bit and then sign-extended and * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0xFFFFFFFF * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x00000000 * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0x20000000 * ~~~ * * **Operations**:\n * ~~~ * * RV32: * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1; * * RV64: * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1; * Rd[63:0] = SE(resw[31:0]); * ~~~ * * \param [in] a unsigned int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSUBW(unsigned int a, unsigned int b) { register unsigned long result; __ASM volatile("ursubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.185. URSUBW ===== */ /* ===== Inline Function Start for 3.186. WEXTI ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief WEXTI (Extract Word from 64-bit Immediate) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * WEXTI Rd, Rs1, #LSBloc * ~~~ * * **Purpose**:\n * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or * a register (RV64) starting from a specified immediate LSB bit position. * * **RV32 Description**:\n * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified * by Rs1(4,1) starting from a specified immediate LSB bit position, #LSBloc. The extracted word is * written to Rd. * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d` * register of the pair contains the low 32-bit of the 64-bit value. * * **RV64 Description**:\n * This instruction extracts a 32-bit word from a 64-bit value in Rs1 starting from a specified * immediate LSB bit position, #LSBloc. The extracted word is sign-extended and written to lower 32- * bit of Rd. * * **Operations**:\n * ~~~ * * RV32: * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs2(4,1),1'b1); * src[63:0] = Concat(R[Idx1], R[Idx0]); * Rd = src[31+LSBloc:LSBloc]; * * RV64: * ExtractW = Rs1[31+LSBloc:LSBloc]; * Rd = SE(ExtractW) * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ #define __RV_WEXTI(a, b) \ ({ \ register unsigned long result; \ register long long __a = (long long)(a); \ __ASM volatile("wexti %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b)); \ result; \ }) /* ===== Inline Function End for 3.186. WEXTI ===== */ /* ===== Inline Function Start for 3.187. WEXT ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC * \brief WEXT (Extract Word from 64-bit) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * WEXT Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or * a register (RV64) starting from a specified LSB bit position in a register. * * **RV32 Description**:\n * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified * by Rs1(4,1) starting from a specified LSB bit position, specified in Rs2[4:0]. The extracted word is * written to Rd. * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register * pair includes register 2d and 2d+1. * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d` * register of the pair contains the low 32-bit of the 64-bit value. * * **Operations**:\n * ~~~ * * RV32: * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); * src[63:0] = Concat(R[Idx1], R[Idx0]); * LSBloc = Rs2[4:0]; * Rd = src[31+LSBloc:LSBloc]; * * RV64: * LSBloc = Rs2[4:0]; * ExtractW = Rs1[31+LSBloc:LSBloc]; * Rd = SE(ExtractW) * ~~~ * * \param [in] a long long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_WEXT(long long a, unsigned int b) { register unsigned long result; __ASM volatile("wext %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 3.187. WEXT ===== */ /* ===== Inline Function Start for 3.188.1. ZUNPKD810 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief ZUNPKD810 (Unsigned Unpacking Bytes 1 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * ZUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned * halfwords of 32-bit chunks in a register. * * **Description**:\n * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) * // ZUNPKD810, x=1,y=0 * // ZUNPKD820, x=2,y=0 * // ZUNPKD830, x=3,y=0 * // ZUNPKD831, x=3,y=1 * // ZUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ZUNPKD810(unsigned long a) { register unsigned long result; __ASM volatile("zunpkd810 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.188.1. ZUNPKD810 ===== */ /* ===== Inline Function Start for 3.188.2. ZUNPKD820 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief ZUNPKD820 (Unsigned Unpacking Bytes 2 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * ZUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned * halfwords of 32-bit chunks in a register. * * **Description**:\n * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) * // ZUNPKD810, x=1,y=0 * // ZUNPKD820, x=2,y=0 * // ZUNPKD830, x=3,y=0 * // ZUNPKD831, x=3,y=1 * // ZUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ZUNPKD820(unsigned long a) { register unsigned long result; __ASM volatile("zunpkd820 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.188.2. ZUNPKD820 ===== */ /* ===== Inline Function Start for 3.188.3. ZUNPKD830 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief ZUNPKD830 (Unsigned Unpacking Bytes 3 & 0) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * ZUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned * halfwords of 32-bit chunks in a register. * * **Description**:\n * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) * // ZUNPKD810, x=1,y=0 * // ZUNPKD820, x=2,y=0 * // ZUNPKD830, x=3,y=0 * // ZUNPKD831, x=3,y=1 * // ZUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ZUNPKD830(unsigned long a) { register unsigned long result; __ASM volatile("zunpkd830 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.188.3. ZUNPKD830 ===== */ /* ===== Inline Function Start for 3.188.4. ZUNPKD831 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief ZUNPKD831 (Unsigned Unpacking Bytes 3 & 1) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * ZUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned * halfwords of 32-bit chunks in a register. * * **Description**:\n * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) * // ZUNPKD810, x=1,y=0 * // ZUNPKD820, x=2,y=0 * // ZUNPKD830, x=3,y=0 * // ZUNPKD831, x=3,y=1 * // ZUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ZUNPKD831(unsigned long a) { register unsigned long result; __ASM volatile("zunpkd831 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.188.4. ZUNPKD831 ===== */ /* ===== Inline Function Start for 3.188.5. ZUNPKD832 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK * \brief ZUNPKD832 (Unsigned Unpacking Bytes 3 & 2) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * ZUNPKD8xy Rd, Rs1 * xy = {10, 20, 30, 31, 32} * ~~~ * * **Purpose**:\n * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned * halfwords of 32-bit chunks in a register. * * **Description**:\n * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit * chunks in Rd. * * **Operations**:\n * ~~~ * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x]) * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y]) * // ZUNPKD810, x=1,y=0 * // ZUNPKD820, x=2,y=0 * // ZUNPKD830, x=3,y=0 * // ZUNPKD831, x=3,y=1 * // ZUNPKD832, x=3,y=2 * for RV32: m=0, * for RV64: m=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ZUNPKD832(unsigned long a) { register unsigned long result; __ASM volatile("zunpkd832 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 3.188.5. ZUNPKD832 ===== */ #if (__RISCV_XLEN == 64) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) /* ===== Inline Function Start for 4.1. ADD32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief ADD32 (SIMD 32-bit Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * ADD32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element additions simultaneously. * * **Description**:\n * This instruction adds the 32-bit integer elements in Rs1 with the 32-bit integer * elements in Rs2, and then writes the 32-bit element results to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned addition. * * **Operations**:\n * ~~~ * Rd.W[x] = Rs1.W[x] + Rs2.W[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_ADD32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("add32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.1. ADD32 ===== */ /* ===== Inline Function Start for 4.2. CRAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief CRAS32 (SIMD 32-bit Cross Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * CRAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit * chunk simultaneously. Operands are from crossed 32-bit elements. * * **Description**:\n * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit * integer element in [31:0] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts * the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and * writes the result to [31:0] of Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[1] = Rs1.W[1] + Rs2.W[0]; * Rd.W[0] = Rs1.W[0] - Rs2.W[1]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CRAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("cras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.2. CRAS32 ===== */ /* ===== Inline Function Start for 4.3. CRSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief CRSA32 (SIMD 32-bit Cross Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * CRSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit * chunk simultaneously. Operands are from crossed 32-bit elements. * *Description: * * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element * in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit integer * element in [31:0] of Rs1 with the 32-bit integer element in [63:32] of Rs2, and writes the result to * [31:0] of Rd * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[1] = Rs1.W[1] - Rs2.W[0]; * Rd.W[0] = Rs1.W[0] + Rs2.W[1]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_CRSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("crsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.3. CRSA32 ===== */ /* ===== Inline Function Start for 4.4. KABS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC * \brief KABS32 (Scalar 32-bit Absolute Value with Saturation) * \details * **Type**: DSP (RV64 Only) 24 20 19 15 14 12 11 7 KABS32 10010 Rs1 000 Rd 6 0 GE80B 1111111 * * **Syntax**:\n * ~~~ * KABS32 Rd, Rs1 * ~~~ * * **Purpose**:\n * Get the absolute value of signed 32-bit integer elements in a general register. * * **Description**:\n * This instruction calculates the absolute value of signed 32-bit integer elements stored * in Rs1. The results are written to Rd. This instruction with the minimum negative integer input of * 0x80000000 will produce a saturated output of maximum positive integer of 0x7fffffff and the OV * flag will be set to 1. * * **Operations**:\n * ~~~ * if (Rs1.W[x] >= 0) { * res[x] = Rs1.W[x]; * } else { * If (Rs1.W[x] == 0x80000000) { * res[x] = 0x7fffffff; * OV = 1; * } else { * res[x] = -Rs1.W[x]; * } * } * Rd.W[x] = res[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KABS32(unsigned long a) { register unsigned long result; __ASM volatile("kabs32 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for 4.4. KABS32 ===== */ /* ===== Inline Function Start for 4.5. KADD32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KADD32 (SIMD 32-bit Signed Saturating Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KADD32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed * integer elements in Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.W[x] + Rs2.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KADD32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.5. KADD32 ===== */ /* ===== Inline Function Start for 4.6. KCRAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KCRAS32 (SIMD 32-bit Signed Saturating Cross Addition & Subtraction) * \details * **Type**: SIM (RV64 Only) * * **Syntax**:\n * ~~~ * KCRAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element saturating addition and 32-bit signed integer element * saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. * * **Description**:\n * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit * integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit integer element in [63:32] of * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction. * * **Operations**:\n * ~~~ * res[1] = Rs1.W[1] + Rs2.W[0]; * res[0] = Rs1.W[0] - Rs2.W[1]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[1] = res[1]; * Rd.W[0] = res[0]; * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KCRAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.6. KCRAS32 ===== */ /* ===== Inline Function Start for 4.7. KCRSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KCRSA32 (SIMD 32-bit Signed Saturating Cross Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KCRSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element * saturating addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. * *Description: * * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element * in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with the 32-bit * integer element in [63:32] of Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 * <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to * [63:32] of Rd for subtraction and [31:0] of Rd for addition. * * **Operations**:\n * ~~~ * res[1] = Rs1.W[1] - Rs2.W[0]; * res[0] = Rs1.W[0] + Rs2.W[1]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[1] = res[1]; * Rd.W[0] = res[0]; * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KCRSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.7. KCRSA32 ===== */ /* ===== Inline Function Start for 4.8.1. KDMBB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMBB16 (SIMD Signed Saturating Double Multiply B16 x B16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks * in the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF * and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * Rd.W[z] = resQ31[z]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMBB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kdmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.8.1. KDMBB16 ===== */ /* ===== Inline Function Start for 4.8.2. KDMBT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMBT16 (SIMD Signed Saturating Double Multiply B16 x T16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks * in the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF * and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * Rd.W[z] = resQ31[z]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMBT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kdmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.8.2. KDMBT16 ===== */ /* ===== Inline Function Start for 4.8.3. KDMTT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMTT16 (SIMD Signed Saturating Double Multiply T16 x T16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks * in the destination register. If saturation happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF * and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * Rd.W[z] = resQ31[z]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMTT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kdmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.8.3. KDMTT16 ===== */ /* ===== Inline Function Start for 4.9.1. KDMABB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMABB16 (SIMD Signed Saturating Double Multiply Addition B16 x B16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with * the values of the corresponding 32-bit chunks from the destination register and write the saturated * addition results back into the corresponding 32-bit chunks of the destination register. If saturation * happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then * doubled and saturated into Q31 values. The Q31 values are then added with the content of the * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation * are written back to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * resadd[z] = Rd.W[z] + resQ31[z]; * if (resadd[z] > (2^31)-1) { * resadd[z] = (2^31)-1; * OV = 1; * } else if (resadd[z] < -2^31) { * resadd[z] = -2^31; * OV = 1; * } * Rd.W[z] = resadd[z]; * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMABB16(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("kdmabb16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.9.1. KDMABB16 ===== */ /* ===== Inline Function Start for 4.9.2. KDMABT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMABT16 (SIMD Signed Saturating Double Multiply Addition B16 x T16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with * the values of the corresponding 32-bit chunks from the destination register and write the saturated * addition results back into the corresponding 32-bit chunks of the destination register. If saturation * happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then * doubled and saturated into Q31 values. The Q31 values are then added with the content of the * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation * are written back to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * resadd[z] = Rd.W[z] + resQ31[z]; * if (resadd[z] > (2^31)-1) { * resadd[z] = (2^31)-1; * OV = 1; * } else if (resadd[z] < -2^31) { * resadd[z] = -2^31; * OV = 1; * } * Rd.W[z] = resadd[z]; * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMABT16(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("kdmabt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.9.2. KDMABT16 ===== */ /* ===== Inline Function Start for 4.9.3. KDMATT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KDMATT16 (SIMD Signed Saturating Double Multiply Addition T16 x T16) * \details * **Type**: SIMD (RV64 only) * * **Syntax**:\n * ~~~ * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with * the values of the corresponding 32-bit chunks from the destination register and write the saturated * addition results back into the corresponding 32-bit chunks of the destination register. If saturation * happens, an overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then * doubled and saturated into Q31 values. The Q31 values are then added with the content of the * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <= * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation * are written back to Rd. * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be * set. * * **Operations**:\n * ~~~ * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1) * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1) * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1) * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y]; * If (0x8000 != aop[z] | 0x8000 != bop[z]) { * Mresult[z] = aop[z] * bop[z]; * resQ31[z] = Mresult[z] << 1; * } else { * resQ31[z] = 0x7FFFFFFF; * OV = 1; * } * resadd[z] = Rd.W[z] + resQ31[z]; * if (resadd[z] > (2^31)-1) { * resadd[z] = (2^31)-1; * OV = 1; * } else if (resadd[z] < -2^31) { * resadd[z] = -2^31; * OV = 1; * } * Rd.W[z] = resadd[z]; * ~~~ * * \param [in] t unsigned long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KDMATT16(unsigned long t, unsigned long a, unsigned long b) { __ASM volatile("kdmatt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.9.3. KDMATT16 ===== */ /* ===== Inline Function Start for 4.10.1. KHMBB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KHMBB16 (SIMD Signed Saturating Half Multiply B16 x B16) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop = Rs1.H[x]; bop = Rs2.H[y]; * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd.W[z] = SE32(res[15:0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHMBB16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.10.1. KHMBB16 ===== */ /* ===== Inline Function Start for 4.10.2. KHMBT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KHMBT16 (SIMD Signed Saturating Half Multiply B16 x T16) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop = Rs1.H[x]; bop = Rs2.H[y]; * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd.W[z] = SE32(res[15:0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHMBT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.10.2. KHMBT16 ===== */ /* ===== Inline Function Start for 4.10.3. KHMTT16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT * \brief KHMTT16 (SIMD Signed Saturating Half Multiply T16 x T16) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT) * ~~~ * * **Purpose**:\n * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an * overflow flag OV will be set. * * **Description**:\n * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15- * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated * to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1) * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1) * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1) * aop = Rs1.H[x]; bop = Rs2.H[y]; * If (0x8000 != aop | 0x8000 != bop) { * Mresult[31:0] = aop * bop; * res[15:0] = Mresult[30:15]; * } else { * res[15:0] = 0x7FFF; * OV = 1; * } * Rd.W[z] = SE32(res[15:0]); * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KHMTT16(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("khmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.10.3. KHMTT16 ===== */ /* ===== Inline Function Start for 4.11.1. KMABB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD * \brief KMABB32 (Saturating Signed Multiply Bottom Words & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMABB32 Rd, Rs1, Rs2 * KMABT32 Rd, Rs1, Rs2 * KMATT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element in a register with the 32-bit element in another register * and add the result to the content of 64-bit data in the third register. The addition result may be * saturated and is written to the third register. * * KMABB32: rd + bottom*bottom * * KMABT32: rd + bottom*top * * KMATT32: rd + top*top * * **Description**:\n * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2. * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2. * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2. * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * *Exceptions:* None * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMABB32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmabb32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.11.1. KMABB32 ===== */ /* ===== Inline Function Start for 4.11.2. KMABT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD * \brief KMABT32 (Saturating Signed Multiply Bottom & Top Words & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMABB32 Rd, Rs1, Rs2 * KMABT32 Rd, Rs1, Rs2 * KMATT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element in a register with the 32-bit element in another register * and add the result to the content of 64-bit data in the third register. The addition result may be * saturated and is written to the third register. * * KMABB32: rd + bottom*bottom * * KMABT32: rd + bottom*top * * KMATT32: rd + top*top * * **Description**:\n * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2. * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2. * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2. * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * *Exceptions:* None * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMABT32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmabt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.11.2. KMABT32 ===== */ /* ===== Inline Function Start for 4.11.3. KMATT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD * \brief KMATT32 (Saturating Signed Multiply Top Words & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMABB32 Rd, Rs1, Rs2 * KMABT32 Rd, Rs1, Rs2 * KMATT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element in a register with the 32-bit element in another register * and add the result to the content of 64-bit data in the third register. The addition result may be * saturated and is written to the third register. * * KMABB32: rd + bottom*bottom * * KMABT32: rd + bottom*top * * KMATT32: rd + top*top * * **Description**:\n * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2. * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2. * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2. * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32 * res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32 * res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * *Exceptions:* None * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMATT32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmatt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.11.3. KMATT32 ===== */ /* ===== Inline Function Start for 4.12.1. KMADA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMADA32 (Saturating Signed Multiply Two Words and Two Adds) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMADA32 Rd, Rs1, Rs2 * KMAXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated. * * KMADA32: rd + top*top + bottom*bottom * * KMAXDA32: rd + top*bottom + bottom*top * * **Description**:\n * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32- * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1 * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction. * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1 * with the top 32-bit element in Rs2. * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32 * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADA32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmada32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.12.1. KMADA32 ===== */ /* ===== Inline Function Start for 4.12.2. KMAXDA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMAXDA32 (Saturating Signed Crossed Multiply Two Words and Two Adds) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMADA32 Rd, Rs1, Rs2 * KMAXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated. * * KMADA32: rd + top*top + bottom*bottom * * KMAXDA32: rd + top*bottom + bottom*top * * **Description**:\n * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32- * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1 * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction. * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1 * with the top 32-bit element in Rs2. * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32 * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMAXDA32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmaxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.12.2. KMAXDA32 ===== */ /* ===== Inline Function Start for 4.13.1. KMDA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMDA32 (Signed Multiply Two Words and Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMDA32 Rd, Rs1, Rs2 * KMXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then * adds the two 64-bit results together. The addition result may be saturated. * * KMDA32: top*top + bottom*bottom * * KMXDA32: top*bottom + bottom*top * * **Description**:\n * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 * with the top 32-bit element of Rs2. * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 * with the bottom 32-bit element of Rs2. * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1. * The final result is written to Rd. The 32-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) { * Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32 * Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32 * } else { * Rd = 0x7fffffffffffffff; * OV = 1; * } * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMDA32(unsigned long a, unsigned long b) { register long result; __ASM volatile("kmda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.13.1. KMDA32 ===== */ /* ===== Inline Function Start for 4.13.2. KMXDA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMXDA32 (Signed Crossed Multiply Two Words and Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMDA32 Rd, Rs1, Rs2 * KMXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then * adds the two 64-bit results together. The addition result may be saturated. * * KMDA32: top*top + bottom*bottom * * KMXDA32: top*bottom + bottom*top * * **Description**:\n * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 * with the top 32-bit element of Rs2. * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1 * with the bottom 32-bit element of Rs2. * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1. * The final result is written to Rd. The 32-bit contents are treated as signed integers. * * **Operations**:\n * ~~~ * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) { * Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32 * Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32 * } else { * Rd = 0x7fffffffffffffff; * OV = 1; * } * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMXDA32(unsigned long a, unsigned long b) { register long result; __ASM volatile("kmxda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.13.2. KMXDA32 ===== */ /* ===== Inline Function Start for 4.14.1. KMADS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMADS32 (Saturating Signed Multiply Two Words & Subtract & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMADS32 Rd, Rs1, Rs2 * KMADRS32 Rd, Rs1, Rs2 * KMAXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to * 64-bit data in a third register. The addition result may be saturated. * * KMADS32: rd + (top*top - bottom*bottom) * * KMADRS32: rd + (bottom*bottom - top*top) * * KMAXDS32: rd + (top*bottom - bottom*top) * * **Description**:\n * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the top 32-bit element in Rs2. * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element in Rs1 with the bottom 32-bit element in Rs2. * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the bottom 32-bit element in Rs2. * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated * as signed integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADS32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmads32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.14.1. KMADS32 ===== */ /* ===== Inline Function Start for 4.14.2. KMADRS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMADRS32 (Saturating Signed Multiply Two Words & Reverse Subtract & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMADS32 Rd, Rs1, Rs2 * KMADRS32 Rd, Rs1, Rs2 * KMAXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to * 64-bit data in a third register. The addition result may be saturated. * * KMADS32: rd + (top*top - bottom*bottom) * * KMADRS32: rd + (bottom*bottom - top*top) * * KMAXDS32: rd + (top*bottom - bottom*top) * * **Description**:\n * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the top 32-bit element in Rs2. * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element in Rs1 with the bottom 32-bit element in Rs2. * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the bottom 32-bit element in Rs2. * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated * as signed integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMADRS32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmadrs32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.14.2. KMADRS32 ===== */ /* ===== Inline Function Start for 4.14.3. KMAXDS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMAXDS32 (Saturating Signed Crossed Multiply Two Words & Subtract & Add) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMADS32 Rd, Rs1, Rs2 * KMADRS32 Rd, Rs1, Rs2 * KMAXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to * 64-bit data in a third register. The addition result may be saturated. * * KMADS32: rd + (top*top - bottom*bottom) * * KMADRS32: rd + (bottom*bottom - top*top) * * KMAXDS32: rd + (top*bottom - bottom*top) * * **Description**:\n * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the top 32-bit element in Rs2. * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element in Rs1 with the bottom 32-bit element in Rs2. * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in * Rs1 with the bottom 32-bit element in Rs2. * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated * as signed integers. * * **Operations**:\n * ~~~ * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMAXDS32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmaxds32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.14.3. KMAXDS32 ===== */ /* ===== Inline Function Start for 4.15.1. KMSDA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMSDA32 (Saturating Signed Multiply Two Words & Add & Subtract) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMSDA32 Rd, Rs1, Rs2 * KMSXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then * subtracts the two 64-bit results from a third register. The subtraction result may be saturated. * * KMSDA: rd - top*top - bottom*bottom * * KMSXDA: rd - top*bottom - bottom*top * * **Description**:\n * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2. * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2. * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed * integers. * * **Operations**:\n * ~~~ * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32 * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMSDA32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmsda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.15.1. KMSDA32 ===== */ /* ===== Inline Function Start for 4.15.2. KMSXDA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief KMSXDA32 (Saturating Signed Crossed Multiply Two Words & Add & Subtract) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * KMSDA32 Rd, Rs1, Rs2 * KMSXDA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then * subtracts the two 64-bit results from a third register. The subtraction result may be saturated. * * KMSDA: rd - top*top - bottom*bottom * * KMSXDA: rd - top*bottom - bottom*top * * **Description**:\n * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2. * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2. * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed * integers. * * **Operations**:\n * ~~~ * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32 * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32 * if (res > (2^63)-1) { * res = (2^63)-1; * OV = 1; * } else if (res < -2^63) { * res = -2^63; * OV = 1; * } * Rd = res; * ~~~ * * \param [in] t long type of value stored in t * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_KMSXDA32(long t, unsigned long a, unsigned long b) { __ASM volatile("kmsxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b)); return t; } /* ===== Inline Function End for 4.15.2. KMSXDA32 ===== */ /* ===== Inline Function Start for 4.16. KSLL32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief KSLL32 (SIMD 32-bit Saturating Shift Left Logical) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSLL32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift * amount is a variable from a GPR. * * **Description**:\n * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. * Any shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is * saturated to -2^31. And the saturated results are written to Rd. If any saturation is performed, set OV * bit to 1. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * if (sa != 0) { * res[(31+sa):0] = Rs1.W[x] << sa; * if (res > (2^31)-1) { * res = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res = 0x80000000; OV = 1; * } * Rd.W[x] = res[31:0]; * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLL32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("ksll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.16. KSLL32 ===== */ /* ===== Inline Function Start for 4.17. KSLLI32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief KSLLI32 (SIMD 32-bit Saturating Shift Left Logical Immediate) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSLLI32 Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift * amount is an immediate value. * * **Description**:\n * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled * with zero and the shift amount is specified by the imm5u constant. Any shifted value greater than * 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated * results are written to Rd. If any saturation is performed, set OV bit to 1. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * if (sa != 0) { * res[(31+sa):0] = Rs1.W[x] << sa; * if (res > (2^31)-1) { * res = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res = 0x80000000; OV = 1; * } * Rd.W[x] = res[31:0]; * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLLI32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("kslli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.17. KSLLI32 ===== */ /* ===== Inline Function Start for 4.18.1. KSLRA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief KSLRA32 (SIMD 32-bit Shift Left Logical with Saturation or Shift Right Arithmetic) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSLRA32 Rd, Rs1, Rs2 * KSLRA32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`. * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u` * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[5:0] < 0) { * sa = -Rs2[5:0]; * sa = (sa == 32)? 31 : sa; * if (`.u` form) { * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * } else { * Rd.W[x] = SE32(Rs1.W[x][31:sa]); * } * } else { * sa = Rs2[4:0]; * res[(31+sa):0] = Rs1.W[x] <<(logic) sa; * if (res > (2^31)-1) { * res[31:0] = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res[31:0] = 0x80000000; OV = 1; * } * Rd.W[x] = res[31:0]; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA32(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.18.1. KSLRA32 ===== */ /* ===== Inline Function Start for 4.18.2. KSLRA32.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief KSLRA32.u (SIMD 32-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSLRA32 Rd, Rs1, Rs2 * KSLRA32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the * right shift. * * **Description**:\n * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`. * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u` * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit * position for rounding effect. After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[5:0] < 0) { * sa = -Rs2[5:0]; * sa = (sa == 32)? 31 : sa; * if (`.u` form) { * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * } else { * Rd.W[x] = SE32(Rs1.W[x][31:sa]); * } * } else { * sa = Rs2[4:0]; * res[(31+sa):0] = Rs1.W[x] <<(logic) sa; * if (res > (2^31)-1) { * res[31:0] = 0x7fffffff; OV = 1; * } else if (res < -2^31) { * res[31:0] = 0x80000000; OV = 1; * } * Rd.W[x] = res[31:0]; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U(unsigned long a, int b) { register unsigned long result; __ASM volatile("kslra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.18.2. KSLRA32.u ===== */ /* ===== Inline Function Start for 4.19. KSTAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KSTAS32 (SIMD 32-bit Signed Saturating Straight Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSTAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element saturating addition and 32-bit signed integer element * saturating subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit * elements. * * **Description**:\n * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit * integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit integer element in [31:0] of * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction. * * **Operations**:\n * ~~~ * res[1] = Rs1.W[1] + Rs2.W[1]; * res[0] = Rs1.W[0] - Rs2.W[0]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[1] = res[1]; * Rd.W[0] = res[0]; * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSTAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.19. KSTAS32 ===== */ /* ===== Inline Function Start for 4.20. KSTSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KSTSA32 (SIMD 32-bit Signed Saturating Straight Subtraction & Addition) * \details * **Type**: SIM (RV64 Only) * * **Syntax**:\n * ~~~ * KSTSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element * saturating addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit * elements. * *Description: * * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer * element in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with * the 32-bit integer element in [31:0] of Rs2. If any of the results are beyond the Q31 number range (- * 231 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are * written to [63:32] of Rd for subtraction and [31:0] of Rd for addition. * * **Operations**:\n * ~~~ * res[1] = Rs1.W[1] - Rs2.W[1]; * res[0] = Rs1.W[0] + Rs2.W[0]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[1] = res[1]; * Rd.W[0] = res[0]; * for RV64, x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSTSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("kstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.20. KSTSA32 ===== */ /* ===== Inline Function Start for 4.21. KSUB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief KSUB32 (SIMD 32-bit Signed Saturating Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * KSUB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit * signed integer elements in Rs1. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= * 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to * Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.W[x] - Rs2.W[x]; * if (res[x] > (2^31)-1) { * res[x] = (2^31)-1; * OV = 1; * } else if (res[x] < -2^31) { * res[x] = -2^31; * OV = 1; * } * Rd.W[x] = res[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_KSUB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.21. KSUB32 ===== */ /* ===== Inline Function Start for 4.22.1. PKBB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK * \brief PKBB32 (Pack Two 32-bit Data from Both Bottom Half) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * PKBB32 Rd, Rs1, Rs2 * PKBT32 Rd, Rs1, Rs2 * PKTT32 Rd, Rs1, Rs2 * PKTB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 32-bit data from 64-bit chunks in two registers. * * PKBB32: bottom.bottom * * PKBT32: bottom.top * * PKTT32: top.top * * PKTB32: top.bottom * * **Description**:\n * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * * **Operations**:\n * ~~~ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKBB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pkbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.22.1. PKBB32 ===== */ /* ===== Inline Function Start for 4.22.2. PKBT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK * \brief PKBT32 (Pack Two 32-bit Data from Bottom and Top Half) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * PKBB32 Rd, Rs1, Rs2 * PKBT32 Rd, Rs1, Rs2 * PKTT32 Rd, Rs1, Rs2 * PKTB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 32-bit data from 64-bit chunks in two registers. * * PKBB32: bottom.bottom * * PKBT32: bottom.top * * PKTT32: top.top * * PKTB32: top.bottom * * **Description**:\n * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * * **Operations**:\n * ~~~ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKBT32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pkbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.22.2. PKBT32 ===== */ /* ===== Inline Function Start for 4.22.3. PKTT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK * \brief PKTT32 (Pack Two 32-bit Data from Both Top Half) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * PKBB32 Rd, Rs1, Rs2 * PKBT32 Rd, Rs1, Rs2 * PKTT32 Rd, Rs1, Rs2 * PKTB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 32-bit data from 64-bit chunks in two registers. * * PKBB32: bottom.bottom * * PKBT32: bottom.top * * PKTT32: top.top * * PKTB32: top.bottom * * **Description**:\n * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * * **Operations**:\n * ~~~ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKTT32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pktt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.22.3. PKTT32 ===== */ /* ===== Inline Function Start for 4.22.4. PKTB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK * \brief PKTB32 (Pack Two 32-bit Data from Top and Bottom Half) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * PKBB32 Rd, Rs1, Rs2 * PKBT32 Rd, Rs1, Rs2 * PKTT32 Rd, Rs1, Rs2 * PKTB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Pack 32-bit data from 64-bit chunks in two registers. * * PKBB32: bottom.bottom * * PKBT32: bottom.top * * PKTT32: top.top * * PKTB32: top.bottom * * **Description**:\n * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0]. * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0]. * * **Operations**:\n * ~~~ * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_PKTB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("pktb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.22.4. PKTB32 ===== */ /* ===== Inline Function Start for 4.23. RADD32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RADD32 (SIMD 32-bit Signed Halving Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RADD32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element additions simultaneously. The results are halved to avoid * overflow or saturation. * * **Description**:\n * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to * Rd. * * **Examples**:\n * ~~~ * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF Rd = 0x7FFFFFFF * * Rs1 = 0x80000000, Rs2 = 0x80000000 Rd = 0x80000000 * * Rs1 = 0x40000000, Rs2 = 0x80000000 Rd = 0xE0000000 * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] + Rs2.W[x]) s>> 1; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RADD32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("radd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.23. RADD32 ===== */ /* ===== Inline Function Start for 4.24. RCRAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RCRAS32 (SIMD 32-bit Signed Halving Cross Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RCRAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit * signed integer element in [31:0] of Rs2, and subtracts the 32-bit signed integer element in [63:32] of * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd * for subtraction. * * **Examples**:\n * ~~~ * Please see `RADD32` and `RSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) s>> 1; * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) s>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RCRAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.24. RCRAS32 ===== */ /* ===== Inline Function Start for 4.25. RCRSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RCRSA32 (SIMD 32-bit Signed Halving Cross Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RCRSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit signed integer element in [31:0] of Rs2 from the * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0] * of Rs1 with the 32-bit signed integer element in [63:32] of Rs2. The two results are first * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of * Rd for addition. * * **Examples**:\n * ~~~ * Please see `RADD32` and `RSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) s>> 1; * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) s>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RCRSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.25. RCRSA32 ===== */ /* ===== Inline Function Start for 4.26. RSTAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RSTAS32 (SIMD 32-bit Signed Halving Straight Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RSTAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are * halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit * signed integer element in [63:32] of Rs2, and subtracts the 32-bit signed integer element in [31:0] of * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd * for subtraction. * * **Examples**:\n * ~~~ * Please see `RADD32` and `RSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) s>> 1; * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) s>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSTAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.26. RSTAS32 ===== */ /* ===== Inline Function Start for 4.27. RSTSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RSTSA32 (SIMD 32-bit Signed Halving Straight Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RSTSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are * halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit signed integer element in [63:32] of Rs2 from the * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0] * of Rs1 with the 32-bit signed integer element in [31:0] of Rs2. The two results are first arithmetically * right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for addition. * * **Examples**:\n * ~~~ * Please see `RADD32` and `RSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) s>> 1; * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) s>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSTSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.27. RSTSA32 ===== */ /* ===== Inline Function Start for 4.28. RSUB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief RSUB32 (SIMD 32-bit Signed Halving Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * RSUB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0x7FFFFFFF * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x80000000 * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0xA0000000 * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) s>> 1; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_RSUB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("rsub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.28. RSUB32 ===== */ /* ===== Inline Function Start for 4.29. SLL32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SLL32 (SIMD 32-bit Shift Left Logical) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SLL32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit elements logical left shift operations simultaneously. The shift amount is a * variable from a GPR. * * **Description**:\n * The 32-bit elements in Rs1 are left-shifted logically. And the results are written to Rd. * The shifted out bits are filled with zero and the shift amount is specified by the low-order 5-bits of * the value in the Rs2 register. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * Rd.W[x] = Rs1.W[x] << sa; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SLL32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.29. SLL32 ===== */ /* ===== Inline Function Start for 4.30. SLLI32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SLLI32 (SIMD 32-bit Shift Left Logical Immediate) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SLLI32 Rd, Rs1, imm5u[4:0] * ~~~ * * **Purpose**:\n * Do 32-bit element logical left shift operations simultaneously. The shift amount is an * immediate value. * * **Description**:\n * The 32-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with * zero and the shift amount is specified by the imm5u[4:0] constant. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * Rd.W[x] = Rs1.W[x] << sa; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SLLI32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("slli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.30. SLLI32 ===== */ /* ===== Inline Function Start for 4.31. SMAX32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC * \brief SMAX32 (SIMD 32-bit Signed Maximum) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SMAX32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] > Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMAX32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.31. SMAX32 ===== */ /* ===== Inline Function Start for 4.32.1. SMBB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT * \brief SMBB32 (Signed Multiply Bottom Word & Bottom Word) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMBB32 Rd, Rs1, Rs2 * SMBT32 Rd, Rs1, Rs2 * SMTT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element of a register with the signed 32-bit element of another * register and write the 64-bit result to a third register. * * SMBB32: bottom*bottom * * SMBT32: bottom*top * * SMTT32: top*top * * **Description**:\n * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2. It is actually an alias of `MULSR64` instruction. * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2. * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element * of Rs2. * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; * // SMTT32 Rd = res; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMBB32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.32.1. SMBB32 ===== */ /* ===== Inline Function Start for 4.32.2. SMBT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT * \brief SMBT32 (Signed Multiply Bottom Word & Top Word) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMBB32 Rd, Rs1, Rs2 * SMBT32 Rd, Rs1, Rs2 * SMTT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element of a register with the signed 32-bit element of another * register and write the 64-bit result to a third register. * * SMBB32: bottom*bottom * * SMBT32: bottom*top * * SMTT32: top*top * * **Description**:\n * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2. It is actually an alias of `MULSR64` instruction. * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2. * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element * of Rs2. * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; * // SMTT32 Rd = res; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMBT32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.32.2. SMBT32 ===== */ /* ===== Inline Function Start for 4.32.3. SMTT32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT * \brief SMTT32 (Signed Multiply Top Word & Top Word) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMBB32 Rd, Rs1, Rs2 * SMBT32 Rd, Rs1, Rs2 * SMTT32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Multiply the signed 32-bit element of a register with the signed 32-bit element of another * register and write the 64-bit result to a third register. * * SMBB32: bottom*bottom * * SMBT32: bottom*top * * SMTT32: top*top * * **Description**:\n * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2. It is actually an alias of `MULSR64` instruction. * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2. * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element * of Rs2. * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as * signed integers. * * **Operations**:\n * ~~~ * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1]; * // SMTT32 Rd = res; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMTT32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smtt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.32.3. SMTT32 ===== */ /* ===== Inline Function Start for 4.33.1. SMDS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief SMDS32 (Signed Multiply Two Words and Subtract) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMDS32 Rd, Rs1, Rs2 * SMDRS32 Rd, Rs1, Rs2 * SMXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then * perform a subtraction operation between the two 64-bit results. * * SMDS32: top*top - bottom*bottom * * SMDRS32: bottom*bottom - top*top * * SMXDS32: top*bottom - bottom*top * * **Description**:\n * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the top 32-bit element of Rs2. * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element of Rs1 with the bottom 32-bit element of Rs2. * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the bottom 32-bit element of Rs2. * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMDS32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.33.1. SMDS32 ===== */ /* ===== Inline Function Start for 4.33.2. SMDRS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief SMDRS32 (Signed Multiply Two Words and Reverse Subtract) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMDS32 Rd, Rs1, Rs2 * SMDRS32 Rd, Rs1, Rs2 * SMXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then * perform a subtraction operation between the two 64-bit results. * * SMDS32: top*top - bottom*bottom * * SMDRS32: bottom*bottom - top*top * * SMXDS32: top*bottom - bottom*top * * **Description**:\n * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the top 32-bit element of Rs2. * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element of Rs1 with the bottom 32-bit element of Rs2. * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the bottom 32-bit element of Rs2. * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMDRS32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smdrs32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.33.2. SMDRS32 ===== */ /* ===== Inline Function Start for 4.33.3. SMXDS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC * \brief SMXDS32 (Signed Crossed Multiply Two Words and Subtract) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SMDS32 Rd, Rs1, Rs2 * SMDRS32 Rd, Rs1, Rs2 * SMXDS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then * perform a subtraction operation between the two 64-bit results. * * SMDS32: top*top - bottom*bottom * * SMDRS32: bottom*bottom - top*top * * SMXDS32: top*bottom - bottom*top * * **Description**:\n * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the top 32-bit element of Rs2. * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit * element of Rs1 with the bottom 32-bit element of Rs2. * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of * Rs1 with the bottom 32-bit element of Rs2. * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed * integers. * * **Operations**:\n * ~~~ * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SMXDS32(unsigned long a, unsigned long b) { register long result; __ASM volatile("smxds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.33.3. SMXDS32 ===== */ /* ===== Inline Function Start for 4.34. SMIN32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC * \brief SMIN32 (SIMD 32-bit Signed Minimum) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SMIN32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit signed integer elements finding minimum operations simultaneously. * * **Description**:\n * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected * results are written to Rd. * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] < Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SMIN32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("smin32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.34. SMIN32 ===== */ /* ===== Inline Function Start for 4.35.1. SRA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRA32 (SIMD 32-bit Shift Right Arithmetic) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRA32 Rd, Rs1, Rs2 * SRA32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 32-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * if (sa > 0) { * if (`.u` form) { // SRA32.u * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRA32 * Rd.W[x] = SE32(Rs1.W[x][31:sa]) * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.35.1. SRA32 ===== */ /* ===== Inline Function Start for 4.35.2. SRA32.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRA32.u (SIMD 32-bit Rounding Shift Right Arithmetic) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRA32 Rd, Rs1, Rs2 * SRA32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is * added to the most significant discarded bit of each 32-bit data element to calculate the final results. * And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * if (sa > 0) { * if (`.u` form) { // SRA32.u * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRA32 * Rd.W[x] = SE32(Rs1.W[x][31:sa]) * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRA32_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("sra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.35.2. SRA32.u ===== */ /* ===== Inline Function Start for 4.36.1. SRAI32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRAI32 (SIMD 32-bit Shift Right Arithmetic Immediate) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SRAI32 Rd, Rs1, imm5u * SRAI32.u Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is * an immediate value. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most * significant discarded bit of each 32-bit data to calculate the final results. And the results are written * to Rd. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * if (sa > 0) { * if (`.u` form) { // SRAI32.u * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRAI32 * Rd.W[x] = SE32(Rs1.W[x][31:sa]); * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRAI32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srai32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.36.1. SRAI32 ===== */ /* ===== Inline Function Start for 4.36.2. SRAI32.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRAI32.u (SIMD 32-bit Rounding Shift Right Arithmetic Immediate) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SRAI32 Rd, Rs1, imm5u * SRAI32.u Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is * an immediate value. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most * significant discarded bit of each 32-bit data to calculate the final results. And the results are written * to Rd. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * if (sa > 0) { * if (`.u` form) { // SRAI32.u * res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRAI32 * Rd.W[x] = SE32(Rs1.W[x][31:sa]); * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRAI32_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srai32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.36.2. SRAI32.u ===== */ /* ===== Inline Function Start for 4.37. SRAIW.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT * \brief SRAIW.u (Rounding Shift Right Arithmetic Immediate Word) * \details * **Type**: DSP (RV64 only) * * **Syntax**:\n * ~~~ * SRAIW.u Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Perform a 32-bit arithmetic right shift operation with rounding. The shift amount is an * immediate value. * * **Description**:\n * This instruction right-shifts the lower 32-bit content of Rs1 arithmetically. The shifted * out bits are filled with the sign-bit Rs1(31) and the shift amount is specified by the imm5u constant. * For the rounding operation, a value of 1 is added to the most significant discarded bit of the data to * calculate the final result. And the result is sign-extended and written to Rd. * * **Operations**:\n * ~~~ * sa = imm5u; * if (sa != 0) { * res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1; * Rd = SE32(res[31:0]); * } else { * Rd = SE32(Rs1.W[0]); * } * ~~~ * * \param [in] a int type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in long type */ __STATIC_FORCEINLINE long __RV_SRAIW_U(int a, unsigned int b) { register long result; __ASM volatile("sraiw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.37. SRAIW.u ===== */ /* ===== Inline Function Start for 4.38.1. SRL32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRL32 (SIMD 32-bit Shift Right Logical) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRL32 Rd, Rs1, Rs2 * SRL32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit element logical right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 32-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * if (sa > 0) { * if (`.u` form) { // SRA32.u * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRA32 * Rd.W[x] = ZE32(Rs1.W[x][31:sa]) * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.38.1. SRL32 ===== */ /* ===== Inline Function Start for 4.38.2. SRL32.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRL32.u (SIMD 32-bit Rounding Shift Right Logical) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRL32 Rd, Rs1, Rs2 * SRL32.u Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit element logical right shift operations simultaneously. The shift amount is a * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted * results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant * discarded bit of each 32-bit data element to calculate the final results. And the results are written to * Rd. * * **Operations**:\n * ~~~ * sa = Rs2[4:0]; * if (sa > 0) { * if (`.u` form) { // SRA32.u * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRA32 * Rd.W[x] = ZE32(Rs1.W[x][31:sa]) * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRL32_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srl32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.38.2. SRL32.u ===== */ /* ===== Inline Function Start for 4.39.1. SRLI32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRLI32 (SIMD 32-bit Shift Right Logical Immediate) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRLI32 Rd, Rs1, imm5u * SRLI32.u Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit * data to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * if (sa > 0) { * if (`.u` form) { // SRLI32.u * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRLI32 * Rd.W[x] = ZE32(Rs1.W[x][31:sa]); * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRLI32(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.39.1. SRLI32 ===== */ /* ===== Inline Function Start for 4.39.2. SRLI32.u ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT * \brief SRLI32.u (SIMD 32-bit Rounding Shift Right Logical Immediate) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * SRLI32 Rd, Rs1, imm5u * SRLI32.u Rd, Rs1, imm5u * ~~~ * * **Purpose**:\n * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an * immediate value. The `.u` form performs additional rounding up operations on the shifted results. * * **Description**:\n * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit * data to calculate the final results. And the results are written to Rd. * * **Operations**:\n * ~~~ * sa = imm5u[4:0]; * if (sa > 0) { * if (`.u` form) { // SRLI32.u * res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1; * Rd.W[x] = res[31:0]; * else { // SRLI32 * Rd.W[x] = ZE32(Rs1.W[x][31:sa]); * } * } else { * Rd = Rs1; * } * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned int type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SRLI32_U(unsigned long a, unsigned int b) { register unsigned long result; __ASM volatile("srli32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.39.2. SRLI32.u ===== */ /* ===== Inline Function Start for 4.40. STAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief STAS32 (SIMD 32-bit Straight Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * STAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit * chunk simultaneously. Operands are from corresponding 32-bit elements. * * **Description**:\n * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit * integer element in [63:32] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts * the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and * writes the result to [31:0] of Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[1] = Rs1.W[1] + Rs2.W[1]; * Rd.W[0] = Rs1.W[0] - Rs2.W[0]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_STAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("stas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.40. STAS32 ===== */ /* ===== Inline Function Start for 4.41. STSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief STSA32 (SIMD 32-bit Straight Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * STSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit * chunk simultaneously. Operands are from corresponding 32-bit elements. * *Description: * * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer * element in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit * integer element in [31:0] of Rs1 with the 32-bit integer element in [31:0] of Rs2, and writes the result * to [31:0] of Rd * * **Note**:\n * This instruction can be used for either signed or unsigned operations. * * **Operations**:\n * ~~~ * Rd.W[1] = Rs1.W[1] - Rs2.W[1]; * Rd.W[0] = Rs1.W[0] + Rs2.W[0]; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_STSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("stsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.41. STSA32 ===== */ /* ===== Inline Function Start for 4.42. SUB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief SUB32 (SIMD 32-bit Subtraction) * \details * **Type**: DSP (RV64 Only) * * **Syntax**:\n * ~~~ * SUB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit integer element subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 32-bit integer elements in Rs2 from the 32-bit integer * elements in Rs1, and then writes the results to Rd. * * **Note**:\n * This instruction can be used for either signed or unsigned subtraction. * * **Operations**:\n * ~~~ * Rd.W[x] = Rs1.W[x] - Rs2.W[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_SUB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("sub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.42. SUB32 ===== */ /* ===== Inline Function Start for 4.43. UKADD32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKADD32 (SIMD 32-bit Unsigned Saturating Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKADD32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 32-bit unsigned integer elements in Rs1 with the 32-bit * unsigned integer elements in Rs2. If any of the results are beyond the 32-bit unsigned number * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.W[x] + Rs2.W[x]; * if (res[x] > (2^32)-1) { * res[x] = (2^32)-1; * OV = 1; * } * Rd.W[x] = res[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKADD32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.43. UKADD32 ===== */ /* ===== Inline Function Start for 4.44. UKCRAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKCRAS32 (SIMD 32-bit Unsigned Saturating Cross Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKCRAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed * 32-bit elements. * * **Description**:\n * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- * bit unsigned integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit unsigned * integer element in [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and * [31:0] of Rd for subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[1] + Rs2.W[0]; * res2 = Rs1.W[0] - Rs2.W[1]; * if (res1 > (2^32)-1) { * res1 = (2^32)-1; * OV = 1; * } * if (res2 < 0) { * res2 = 0; * OV = 1; * } * Rd.W[1] = res1; * Rd.W[0] = res2; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKCRAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.44. UKCRAS32 ===== */ /* ===== Inline Function Start for 4.45. UKCRSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKCRSA32 (SIMD 32-bit Unsigned Saturating Cross Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKCRSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from crossed * 32-bit elements. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the * 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned * integer element in [63:32] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and * [31:0] of Rd for addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[1] - Rs2.W[0]; * res2 = Rs1.W[0] + Rs2.W[1]; * if (res1 < 0) { * res1 = 0; * OV = 1; * } else if (res2 > (2^32)-1) { * res2 = (2^32)-1; * OV = 1; * } * Rd.W[1] = res1; * Rd.W[0] = res2; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKCRSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.45. UKCRSA32 ===== */ /* ===== Inline Function Start for 4.46. UKSTAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKSTAS32 (SIMD 32-bit Unsigned Saturating Straight Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKSTAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from * corresponding 32-bit elements. * * **Description**:\n * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- * bit unsigned integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit unsigned * integer element in [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and * [31:0] of Rd for subtraction. * * **Operations**:\n * ~~~ * res1 = Rs1.W[1] + Rs2.W[1]; * res2 = Rs1.W[0] - Rs2.W[0]; * if (res1 > (2^32)-1) { * res1 = (2^32)-1; * OV = 1; * } * if (res2 < 0) { * res2 = 0; * OV = 1; * } * Rd.W[1] = res1; * Rd.W[0] = res2; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSTAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.46. UKSTAS32 ===== */ /* ===== Inline Function Start for 4.47. UKSTSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKSTSA32 (SIMD 32-bit Unsigned Saturating Straight Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKSTSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from * corresponding 32-bit elements. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from * the 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned * integer element in [31:0] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and * [31:0] of Rd for addition. * * **Operations**:\n * ~~~ * res1 = Rs1.W[1] - Rs2.W[1]; * res2 = Rs1.W[0] + Rs2.W[0]; * if (res1 < 0) { * res1 = 0; * OV = 1; * } else if (res2 > (2^32)-1) { * res2 = (2^32)-1; * OV = 1; * } * Rd.W[1] = res1; * Rd.W[0] = res2; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSTSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ukstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.47. UKSTSA32 ===== */ /* ===== Inline Function Start for 4.48. UKSUB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief UKSUB32 (SIMD 32-bit Unsigned Saturating Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UKSUB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit * unsigned integer elements in Rs1. If any of the results are beyond the 32-bit unsigned number * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated * results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.W[x] - Rs2.W[x]; * if (res[x] < 0) { * res[x] = 0; * OV = 1; * } * Rd.W[x] = res[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UKSUB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.48. UKSUB32 ===== */ /* ===== Inline Function Start for 4.49. UMAX32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC * \brief UMAX32 (SIMD 32-bit Unsigned Maximum) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UMAX32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer elements finding maximum operations simultaneously. * * **Description**:\n * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] u> Rs2.W[x])? Rs1.W[x] : Rs2.W[x]; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_UMAX32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("umax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.49. UMAX32 ===== */ /* ===== Inline Function Start for 4.50. UMIN32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC * \brief UMIN32 (SIMD 32-bit Unsigned Minimum) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * UMIN32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer elements finding minimum operations simultaneously. * * **Description**:\n * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The * selected results are written to Rd. * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] > 1; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URADD32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("uradd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.51. URADD32 ===== */ /* ===== Inline Function Start for 4.52. URCRAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief URCRAS32 (SIMD 32-bit Unsigned Halving Cross Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * URCRAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element * subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The * results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- * bit unsigned integer element in [31:0] of Rs2, and subtracts the 32-bit unsigned integer element in * [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for * subtraction. * * **Examples**:\n * ~~~ * Please see `URADD32` and `URSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) u>> 1; * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) u>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URCRAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.52. URCRAS32 ===== */ /* ===== Inline Function Start for 4.53. URCRSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief URCRSA32 (SIMD 32-bit Unsigned Halving Cross Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * URCRSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element * addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results * are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the * 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer in * [31:0] of Rs1 with the 32-bit unsigned integer element in [63:32] of Rs2. The two results are first * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for * addition. * * **Examples**:\n * ~~~ * Please see `URADD32` and `URSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) u>> 1; * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) u>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URCRSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.53. URCRSA32 ===== */ /* ===== Inline Function Start for 4.54. URSTAS32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief URSTAS32 (SIMD 32-bit Unsigned Halving Straight Addition & Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * URSTAS32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element * subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. * The results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32- * bit unsigned integer element in [63:32] of Rs2, and subtracts the 32-bit unsigned integer element in * [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for * subtraction. * * **Examples**:\n * ~~~ * Please see `URADD32` and `URSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) u>> 1; * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) u>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSTAS32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.54. URSTAS32 ===== */ /* ===== Inline Function Start for 4.55. URSTSA32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief URSTSA32 (SIMD 32-bit Unsigned Halving Straight Subtraction & Addition) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * URSTSA32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element * addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The * results are halved to avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from * the 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer * in [31:0] of Rs1 with the 32-bit unsigned integer element in [31:0] of Rs2. The two results are first * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for * addition. * * **Examples**:\n * ~~~ * Please see `URADD32` and `URSUB32` instructions. * ~~~ * * **Operations**:\n * ~~~ * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) u>> 1; * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) u>> 1; * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSTSA32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("urstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.55. URSTSA32 ===== */ /* ===== Inline Function Start for 4.56. URSUB32 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB * \brief URSUB32 (SIMD 32-bit Unsigned Halving Subtraction) * \details * **Type**: SIMD (RV64 Only) * * **Syntax**:\n * ~~~ * URSUB32 Rd, Rs1, Rs2 * ~~~ * * **Purpose**:\n * Do 32-bit unsigned integer element subtractions simultaneously. The results are halved to * avoid overflow or saturation. * * **Description**:\n * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then * written to Rd. * * **Examples**:\n * ~~~ * * Ra = 0x7FFFFFFF, Rb = 0x80000000, Rt = 0xFFFFFFFF * * Ra = 0x80000000, Rb = 0x7FFFFFFF, Rt = 0x00000000 * * Ra = 0x80000000, Rb = 0x40000000, Rt = 0x20000000 * ~~~ * * **Operations**:\n * ~~~ * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) u>> 1; * for RV64: x=1...0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \param [in] b unsigned long type of value stored in b * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_URSUB32(unsigned long a, unsigned long b) { register unsigned long result; __ASM volatile("ursub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for 4.56. URSUB32 ===== */ #endif /* __RISCV_XLEN == 64 */ #if (__RISCV_XLEN == 32) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) /* XXXXX Nuclei Extended DSP Instructions for RV32 XXXXX */ /** * \defgroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM Nuclei Customized DSP Instructions * \ingroup NMSIS_Core_DSP_Intrinsic * \brief (RV32 only)Nuclei Customized DSP Instructions * \details This is Nuclei customized DSP instructions only for RV32 */ /* ===== Inline Function Start for A.1. DKHM8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKHM8 (64-bit SIMD Signed Saturating Q7 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKHM8 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7 * numbers again. * * **Description**:\n * For the `DKHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2. * * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen. * The result will be saturated to 0x7F and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x80 != aop | 0x80 != bop) { * res = (aop s* bop) >> 7; * } else { * res= 0x7F; * OV = 1; * } * } * Rd.H[x/2] = concat(rest, resb); * for RV32, x=0,2,4,6 * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKHM8(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dkhm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.1. DKHM8 ===== */ /* ===== Inline Function Start for A.2. DKHM16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKHM16 (64-bit SIMD Signed Saturating Q15 Multiply) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKHM16 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to * Q15 numbers again. * * **Description**:\n * For the `DKHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in * Rs2. * * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set. * * **Operations**:\n * ~~~ * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) { * if (0x8000 != aop | 0x8000 != bop) { * res = (aop s* bop) >> 15; * } else { * res= 0x7FFF; * OV = 1; * } * } * Rd.W[x/2] = concat(rest, resb); * for RV32: x=0, 2 * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKHM16(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dkhm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.2. DKHM16 ===== */ /* ===== Inline Function Start for A.3. DKABS8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKABS8 (64-bit SIMD 8-bit Saturating Absolute) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKABS8 Rd, Rs1 * # Rd, Rs1 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Get the absolute value of 8-bit signed integer elements simultaneously. * * **Description**:\n * This instruction calculates the absolute value of 8-bit signed integer elements stored * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates * 0x7f as the output and sets the OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.B[x]; * if (src == 0x80) { * src = 0x7f; * OV = 1; * } else if (src[7] == 1) * src = -src; * } * Rd.B[x] = src; * for RV32: x=7...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKABS8(unsigned long long a) { unsigned long long result; __ASM volatile("dkabs8 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A.3. DKABS8 ===== */ /* ===== Inline Function Start for A.4. DKABS16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKABS16 (64-bit SIMD 16-bit Saturating Absolute) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKABS16 Rd, Rs1 * # Rd, Rs1 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Get the absolute value of 16-bit signed integer elements simultaneously. * * **Description**:\n * This instruction calculates the absolute value of 16-bit signed integer elements stored * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction * generates 0x7fff as the output and sets the OV bit to 1. * * **Operations**:\n * ~~~ * src = Rs1.H[x]; * if (src == 0x8000) { * src = 0x7fff; * OV = 1; * } else if (src[15] == 1) * src = -src; * } * Rd.H[x] = src; * for RV32: x=3...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKABS16(unsigned long long a) { unsigned long long result; __ASM volatile("dkabs16 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A.4. DKABS16 ===== */ /* ===== Inline Function Start for A.5. DKSLRA8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKSLRA8 (64-bit SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKSLRA8 Rd, Rs1, Rs2 * # Rd, Rs1 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q7 saturation for the left shift. * * **Description**:\n * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`. * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. * If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[3:0] < 0) { * sa = -Rs2[3:0]; * sa = (sa == 8)? 7 : sa; * Rd.B[x] = SE8(Rs1.B[x][7:sa]); * } else { * sa = Rs2[2:0]; * res[(7+sa):0] = Rs1.B[x] <<(logic) sa; * if (res > (2^7)-1) { * res[7:0] = 0x7f; OV = 1; * } else if (res < -2^7) { * res[7:0] = 0x80; OV = 1; * } * Rd.B[x] = res[7:0]; * } * for RV32: x=7...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKSLRA8(unsigned long long a, int b) { unsigned long long result; __ASM volatile("dkslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.5. DKSLRA8 ===== */ /* ===== Inline Function Start for A.6. DKSLRA16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKSLRA16 (64-bit SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKSLRA16 Rd, Rs1, Rs2 * # Rd, Rs1 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with * Q15 saturation for the left shift. * * **Description**:\n * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`. * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. * After the shift, saturation, or rounding, the final results are written to * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect * this instruction. * * **Operations**:\n * ~~~ * if (Rs2[4:0] < 0) { * sa = -Rs2[4:0]; * sa = (sa == 16)? 15 : sa; * Rd.H[x] = SE16(Rs1.H[x][15:sa]); * } else { * sa = Rs2[3:0]; * res[(15+sa):0] = Rs1.H[x] <<(logic) sa; * if (res > (2^15)-1) { * res[15:0] = 0x7fff; OV = 1; * } else if (res < -2^15) { * res[15:0] = 0x8000; OV = 1; * } * d.H[x] = res[15:0]; * } * for RV32: x=3...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b int type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKSLRA16(unsigned long long a, int b) { unsigned long long result; __ASM volatile("dkslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.6. DKSLRA16 ===== */ /* ===== Inline Function Start for A.7. DKADD8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKADD8 (64-bit SIMD 8-bit Signed Saturating Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKADD8 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 8-bit signed integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.B[x] + Rs2.B[x]; * if (res[x] > 127) { * res[x] = 127; * OV = 1; * } else if (res[x] < -128) { * res[x] = -128; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=7...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKADD8(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dkadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.7. DKADD8 ===== */ /* ===== Inline Function Start for A.8. DKADD16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKADD16 (64-bit SIMD 16-bit Signed Saturating Addition) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKADD16 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 16-bit signed integer element saturating additions simultaneously. * * **Description**:\n * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1), * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] + Rs2.H[x]; * if (res[x] > 32767) { * res[x] = 32767; * OV = 1; * } else if (res[x] < -32768) { * res[x] = -32768; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=3...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKADD16(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dkadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.8. DKADD16 ===== */ /* ===== Inline Function Start for A.10. DKSUB8 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKSUB8 (64-bit SIMD 8-bit Signed Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKSUB8 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 8-bit signed elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.B[x] - Rs2.B[x]; * if (res[x] > (2^7)-1) { * res[x] = (2^7)-1; * OV = 1; * } else if (res[x] < -2^7) { * res[x] = -2^7; * OV = 1; * } * Rd.B[x] = res[x]; * for RV32: x=7...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKSUB8(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.9. DKSUB8 ===== */ /* ===== Inline Function Start for A.10. DKSUB16 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief DKSUB16 (64-bit SIMD 16-bit Signed Saturating Subtraction) * \details * **Type**: SIMD * * **Syntax**:\n * ~~~ * DKSUB16 Rd, Rs1, Rs2 * # Rd, Rs1, Rs2 are all even/odd pair of registers * ~~~ * * **Purpose**:\n * Do 16-bit signed integer elements saturating subtractions simultaneously. * * **Description**:\n * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to * Rd. * * **Operations**:\n * ~~~ * res[x] = Rs1.H[x] - Rs2.H[x]; * if (res[x] > (2^15)-1) { * res[x] = (2^15)-1; * OV = 1; * } else if (res[x] < -2^15) { * res[x] = -2^15; * OV = 1; * } * Rd.H[x] = res[x]; * for RV32: x=3...0, * ~~~ * * \param [in] a unsigned long long type of value stored in a * \param [in] b unsigned long long type of value stored in b * \return value stored in unsigned long long type */ __STATIC_FORCEINLINE unsigned long long __RV_DKSUB16(unsigned long long a, unsigned long long b) { unsigned long long result; __ASM volatile("dksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b)); return result; } /* ===== Inline Function End for A.10. DKSUB16 ===== */ /* ===== Inline Function Start for A.11.1. EXPD80 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief EXPD80 (Expand and Copy Byte 0 to 32bit) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * EXPD80 Rd, Rs1 * ~~~ * * **Purpose**:\n * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. * * **Description**:\n * Moves Rs1.B[0][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0]); * for RV32: x=0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_EXPD80(unsigned long a) { unsigned long result; __ASM volatile("expd80 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A11.1. EXPD80 ===== */ /* ===== Inline Function Start for A.11.2. EXPD81 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief EXPD81 (Expand and Copy Byte 1 to 32bit) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * EXPD81 Rd, Rs1 * ~~~ * * **Purpose**:\n * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. * * **Description**:\n * Moves Rs1.B[1][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0]); * for RV32: x=0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_EXPD81(unsigned long a) { unsigned long result; __ASM volatile("expd81 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A11.2. EXPD81 ===== */ /* ===== Inline Function Start for A.11.3. EXPD82 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief EXPD82 (Expand and Copy Byte 2 to 32bit) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * EXPD82 Rd, Rs1 * ~~~ * * **Purpose**:\n * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. * * **Description**:\n * Moves Rs1.B[2][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0]); * for RV32: x=0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_EXPD82(unsigned long a) { unsigned long result; __ASM volatile("expd82 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A11.3. EXPD82 ===== */ /* ===== Inline Function Start for A.11.4. EXPD83 ===== */ /** * \ingroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM * \brief EXPD83 (Expand and Copy Byte 3 to 32bit) * \details * **Type**: DSP * * **Syntax**:\n * ~~~ * EXPD83 Rd, Rs1 * ~~~ * * **Purpose**:\n * Copy 8-bit data from 32-bit chunks into 4 bytes in a register. * * **Description**:\n * Moves Rs1.B[3][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0] * * **Operations**:\n * ~~~ * Rd.W[x][31:0] = CONCAT(Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0]); * for RV32: x=0 * ~~~ * * \param [in] a unsigned long type of value stored in a * \return value stored in unsigned long type */ __STATIC_FORCEINLINE unsigned long __RV_EXPD83(unsigned long a) { unsigned long result; __ASM volatile("expd83 %0, %1" : "=r"(result) : "r"(a)); return result; } /* ===== Inline Function End for A11.4. EXPD83 ===== */ #endif /* __RISCV_XLEN == 32 */ #if defined(__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1) /* XXXXX ARM Compatiable SIMD API XXXXX */ /** \brief Q setting quad 8-bit saturating addition. */ #define __QADD8(x, y) __RV_KADD8(x, y) /** \brief Q setting quad 8-bit saturating subtract. */ #define __QSUB8(x, y) __RV_KSUB8((x), (y)) /** \brief Q setting dual 16-bit saturating addition. */ #define __QADD16(x, y) __RV_KADD16((x), (y)) /** \brief Dual 16-bit signed addition with halved results. */ #define __SHADD16(x, y) __RV_RADD16((x), (y)) /** \brief Q setting dual 16-bit saturating subtract. */ #define __QSUB16(x, y) __RV_KSUB16((x), (y)) /** \brief Dual 16-bit signed subtraction with halved results. */ #define __SHSUB16(x, y) __RV_RSUB16((x), (y)) /** \brief Q setting dual 16-bit add and subtract with exchange. */ #define __QASX(x, y) __RV_KCRAS16((x), (y)) /** \brief Dual 16-bit signed addition and subtraction with halved results.*/ #define __SHASX(x, y) __RV_RCRAS16((x), (y)) /** \brief Q setting dual 16-bit subtract and add with exchange. */ #define __QSAX(x, y) __RV_KCRSA16((x), (y)) /** \brief Dual 16-bit signed subtraction and addition with halved results.*/ #define __SHSAX(x, y) __RV_RCRSA16((x), (y)) /** \brief Dual 16-bit signed multiply with exchange returning difference. */ #define __SMUSDX(x, y) __RV_SMXDS((y), (x)) /** \brief Q setting sum of dual 16-bit signed multiply with exchange. */ __STATIC_FORCEINLINE int32_t __SMUADX(int32_t op1, int32_t op2) { return (int32_t)__RV_KMXDA(op1, op2); } /** \brief Q setting saturating add. */ #define __QADD(x, y) __RV_KADDW((x), (y)) /** \brief Q setting saturating subtract. */ #define __QSUB(x, y) __RV_KSUBW((x), (y)) /** \brief Q setting dual 16-bit signed multiply with single 32-bit accumulator. */ __STATIC_FORCEINLINE int32_t __SMLAD(int32_t op1, int32_t op2, int32_t op3) { return (int32_t)__RV_KMADA(op3, op1, op2); } /** \brief Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. */ __STATIC_FORCEINLINE int32_t __SMLADX(int32_t op1, int32_t op2, int32_t op3) { return (int32_t)__RV_KMAXDA(op3, op1, op2); } /** \brief Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. */ __STATIC_FORCEINLINE int32_t __SMLSDX(int32_t op1, int32_t op2, int32_t op3) { return (op3 - (int32_t)__RV_SMXDS(op1, op2)); } /** \brief Dual 16-bit signed multiply with single 64-bit accumulator. */ __STATIC_FORCEINLINE int64_t __SMLALD(int32_t op1, int32_t op2, int64_t acc) { return (int64_t)__RV_SMALDA(acc, op1, op2); } /** \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator. */ __STATIC_FORCEINLINE int64_t __SMLALDX(int32_t op1, int32_t op2, int64_t acc) { return (int64_t)__RV_SMALXDA(acc, op1, op2); } /** \brief Q setting sum of dual 16-bit signed multiply. */ __STATIC_FORCEINLINE int32_t __SMUAD(int32_t op1, int32_t op2) { return (int32_t)__RV_KMDA(op1, op2); } /** \brief Dual 16-bit signed multiply returning difference. */ __STATIC_FORCEINLINE int32_t __SMUSD(int32_t op1, int32_t op2) { return (int32_t)__RV_SMDRS(op1, op2); } /** \brief Dual extract 8-bits and sign extend each to 16-bits. */ #define __SXTB16(x) __RV_SUNPKD820(x) /** \brief Dual extracted 8-bit to 16-bit signed addition. TODO Need test */ __STATIC_FORCEINLINE int32_t __SXTAB16(uint32_t op1, uint32_t op2) { return __RV_ADD16(op1, __RV_SUNPKD830(op2)); } /** \brief 32-bit signed multiply with 32-bit truncated accumulator. */ __STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { int32_t mul; mul = (int32_t)__RV_SMMUL(op1, op2); return (op3 + mul); } #define __DKHM8 __RV_DKHM8 #define __DKHM16 __RV_DKHM16 #define __DKSUB16 __RV_DKSUB16 #define __SMAQA __RV_SMAQA #define __MULSR64 __RV_MULSR64 #define __DQADD8 __RV_DKADD8 #define __DQSUB8 __RV_DKSUB8 #define __DKADD16 __RV_DKADD16 #define __PKBB16 __RV_PKBB16 #define __DKSLRA16 __RV_DKSLRA16 #define __DKSLRA8 __RV_DKSLRA8 #define __KABSW __RV_KABSW #define __DKABS8 __RV_DKABS8 #define __DKABS16 __RV_DKABS16 #define __SMALDA __RV_SMALDA #define __SMSLDA __RV_SMSLDA #define __SMALBB __RV_SMALBB #define __SUB64 __RV_SUB64 #define __ADD64 __RV_ADD64 #define __SMBB16 __RV_SMBB16 #define __SMBT16 __RV_SMBT16 #define __SMTT16 __RV_SMTT16 #define __EXPD80 __RV_EXPD80 #define __SMAX8 __RV_SMAX8 #define __SMAX16 __RV_SMAX16 #define __PKTT16 __RV_PKTT16 #define __KADD16 __RV_KADD16 #define __SADD16 __RV_ADD16 #endif /* (__RISCV_FEATURE_DSP == 1) */ #endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */ /** \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. */ #define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) /** \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. */ #define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) #ifdef __cplusplus } #endif #endif /* __CORE_FEATURE_DSP__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_eclic.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_ECLIC__ #define __CORE_FEATURE_ECLIC__ /*! * @file core_feature_eclic.h * @brief ECLIC feature API header file for Nuclei N/NX Core */ /* * ECLIC Feature Configuration Macro: * 1. __ECLIC_PRESENT: Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not * * 0: Not present * * 1: Present * 2. __ECLIC_BASEADDR: Base address of the ECLIC unit. * 3. ECLIC_GetInfoCtlbits(): Define the number of hardware bits are actually implemented in the clicintctl registers. * Valid number is 1 - 8. * 4. __ECLIC_INTNUM : Define the external interrupt number of ECLIC Unit * */ #ifdef __cplusplus extern "C" { #endif #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) /** * \defgroup NMSIS_Core_ECLIC_Registers Register Define and Type Definitions Of ECLIC * \ingroup NMSIS_Core_Registers * \brief Type definitions and defines for eclic registers. * * @{ */ /** * \brief Union type to access CLICFG configure register. */ typedef union { struct { uint8_t _reserved0 : 1; /*!< bit: 0 Overflow condition code flag */ uint8_t nlbits : 4; /*!< bit: 29 Carry condition code flag */ uint8_t _reserved1 : 2; /*!< bit: 30 Zero condition code flag */ uint8_t _reserved2 : 1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint8_t w; /*!< Type used for byte access */ } CLICCFG_Type; /** * \brief Union type to access CLICINFO information register. */ typedef union { struct { uint32_t numint : 13; /*!< bit: 0..12 number of maximum interrupt inputs supported */ uint32_t version : 8; /*!< bit: 13..20 20:17 for architecture version,16:13 for implementation version */ uint32_t intctlbits : 4; /*!< bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers */ uint32_t _reserved0 : 8; /*!< bit: 25..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CLICINFO_Type; /** * \brief Access to the structure of a vector interrupt controller. */ typedef struct { __IOM uint8_t INTIP; /*!< Offset: 0x000 (R/W) Interrupt set pending register */ __IOM uint8_t INTIE; /*!< Offset: 0x001 (R/W) Interrupt set enable register */ __IOM uint8_t INTATTR; /*!< Offset: 0x002 (R/W) Interrupt set attributes register */ __IOM uint8_t INTCTRL; /*!< Offset: 0x003 (R/W) Interrupt configure register */ } CLIC_CTRL_Type; typedef struct { __IOM uint8_t CFG; /*!< Offset: 0x000 (R/W) CLIC configuration register */ uint8_t RESERVED0[3]; __IM uint32_t INFO; /*!< Offset: 0x004 (R/ ) CLIC information register */ uint8_t RESERVED1[3]; __IOM uint8_t MTH; /*!< Offset: 0x00B (R/W) CLIC machine mode threshold register */ uint32_t RESERVED2[0x3FD]; CLIC_CTRL_Type CTRL[4096]; /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */ } CLIC_Type; #define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */ #define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */ #define CLIC_CLICINFO_CTLBIT_Pos 21U /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */ #define CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos) /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */ #define CLIC_CLICINFO_VER_Pos 13U /*!< CLIC CLICINFO: VERSION Position */ #define CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICINFO: VERSION Mask */ #define CLIC_CLICINFO_NUM_Pos 0U /*!< CLIC CLICINFO: NUM Position */ #define CLIC_CLICINFO_NUM_Msk (0xFFFUL << CLIC_CLICINFO_NUM_Pos) /*!< CLIC CLICINFO: NUM Mask */ #define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */ #define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */ #define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */ #define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */ #define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */ #define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */ #define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */ #define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */ #define ECLIC_MAX_NLBITS 8U /*!< Max nlbit of the CLICINTCTLBITS */ #define ECLIC_MODE_MTVEC_Msk 3U /*!< ECLIC Mode mask for MTVT CSR Register */ #define ECLIC_NON_VECTOR_INTERRUPT 0x0 /*!< Non-Vector Interrupt Mode of ECLIC */ #define ECLIC_VECTOR_INTERRUPT 0x1 /*!< Vector Interrupt Mode of ECLIC */ /**\brief ECLIC Trigger Enum for different Trigger Type */ typedef enum ECLIC_TRIGGER { ECLIC_LEVEL_TRIGGER = 0x0, /*!< Level Triggerred, trig[0] = 0 */ ECLIC_POSTIVE_EDGE_TRIGGER = 0x1, /*!< Postive/Rising Edge Triggered, trig[1] = 1, trig[0] = 0 */ ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3, /*!< Negtive/Falling Edge Triggered, trig[1] = 1, trig[0] = 0 */ ECLIC_MAX_TRIGGER = 0x3 /*!< MAX Supported Trigger Mode */ } ECLIC_TRIGGER_Type; #ifndef __ECLIC_BASEADDR /* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in */ #error "__ECLIC_BASEADDR is not defined, please check!" #endif #ifndef __ECLIC_INTCTLBITS /* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */ #define __ECLIC_INTCTLBITS (__ECLIC_GetInfoCtlbits()) #endif /* ECLIC Memory mapping of Device */ #define ECLIC_BASE __ECLIC_BASEADDR /*!< ECLIC Base Address */ #define ECLIC ((CLIC_Type *)ECLIC_BASE) /*!< CLIC configuration struct */ /** @} */ /* end of group NMSIS_Core_ECLIC_Registers */ /* ########################## ECLIC functions #################################### */ /** * \defgroup NMSIS_Core_IntExc Interrupts and Exceptions * \brief Functions that manage interrupts and exceptions via the ECLIC. * * @{ */ /** * \brief Definition of IRQn numbers * \details * The core interrupt enumeration names for IRQn values are defined in the file .h. * - Interrupt ID(IRQn) from 0 to 18 are reserved for core internal interrupts. * - Interrupt ID(IRQn) start from 19 represent device-specific external interrupts. * - The first device-specific interrupt has the IRQn value 19. * * The table below describes the core interrupt names and their availability in various Nuclei Cores. */ /* The following enum IRQn definition in this file * is only used for doxygen documentation generation, * The .h is the real file to define it by vendor */ #if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) typedef enum IRQn { /* ========= Nuclei N/NX Core Specific Interrupt Numbers =========== */ /* Core Internal Interrupt IRQn definitions */ Reserved0_IRQn = 0, /*!< Internal reserved */ Reserved1_IRQn = 1, /*!< Internal reserved */ Reserved2_IRQn = 2, /*!< Internal reserved */ SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ Reserved3_IRQn = 4, /*!< Internal reserved */ Reserved4_IRQn = 5, /*!< Internal reserved */ Reserved5_IRQn = 6, /*!< Internal reserved */ SysTimer_IRQn = 7, /*!< System Timer Interrupt */ Reserved6_IRQn = 8, /*!< Internal reserved */ Reserved7_IRQn = 9, /*!< Internal reserved */ Reserved8_IRQn = 10, /*!< Internal reserved */ Reserved9_IRQn = 11, /*!< Internal reserved */ Reserved10_IRQn = 12, /*!< Internal reserved */ Reserved11_IRQn = 13, /*!< Internal reserved */ Reserved12_IRQn = 14, /*!< Internal reserved */ Reserved13_IRQn = 15, /*!< Internal reserved */ Reserved14_IRQn = 16, /*!< Internal reserved */ Reserved15_IRQn = 17, /*!< Internal reserved */ Reserved16_IRQn = 18, /*!< Internal reserved */ /* ========= Device Specific Interrupt Numbers =================== */ /* ToDo: add here your device specific external interrupt numbers. * 19~max(NUM_INTERRUPT, 1023) is reserved number for user. * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT. * According the interrupt handlers defined in startup_Device.S * eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */ FirstDeviceSpecificInterrupt_IRQn = 19, /*!< First Device Specific Interrupt */ SOC_INT_MAX, /*!< Number of total interrupts */ } IRQn_Type; #endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ #ifdef NMSIS_ECLIC_VIRTUAL #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h" #endif #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE #else #define ECLIC_SetCfgNlbits __ECLIC_SetCfgNlbits #define ECLIC_GetCfgNlbits __ECLIC_GetCfgNlbits #define ECLIC_GetInfoVer __ECLIC_GetInfoVer #define ECLIC_GetInfoCtlbits __ECLIC_GetInfoCtlbits #define ECLIC_GetInfoNum __ECLIC_GetInfoNum #define ECLIC_SetMth __ECLIC_SetMth #define ECLIC_GetMth __ECLIC_GetMth #define ECLIC_EnableIRQ __ECLIC_EnableIRQ #define ECLIC_GetEnableIRQ __ECLIC_GetEnableIRQ #define ECLIC_DisableIRQ __ECLIC_DisableIRQ #define ECLIC_SetPendingIRQ __ECLIC_SetPendingIRQ #define ECLIC_GetPendingIRQ __ECLIC_GetPendingIRQ #define ECLIC_ClearPendingIRQ __ECLIC_ClearPendingIRQ #define ECLIC_SetTrigIRQ __ECLIC_SetTrigIRQ #define ECLIC_GetTrigIRQ __ECLIC_GetTrigIRQ #define ECLIC_SetShvIRQ __ECLIC_SetShvIRQ #define ECLIC_GetShvIRQ __ECLIC_GetShvIRQ #define ECLIC_SetCtrlIRQ __ECLIC_SetCtrlIRQ #define ECLIC_GetCtrlIRQ __ECLIC_GetCtrlIRQ #define ECLIC_SetLevelIRQ __ECLIC_SetLevelIRQ #define ECLIC_GetLevelIRQ __ECLIC_GetLevelIRQ #define ECLIC_SetPriorityIRQ __ECLIC_SetPriorityIRQ #define ECLIC_GetPriorityIRQ __ECLIC_GetPriorityIRQ #endif /* NMSIS_ECLIC_VIRTUAL */ #ifdef NMSIS_VECTAB_VIRTUAL #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h" #endif #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define ECLIC_SetVector __ECLIC_SetVector #define ECLIC_GetVector __ECLIC_GetVector #endif /* (NMSIS_VECTAB_VIRTUAL) */ /** * \brief Set nlbits value * \details * This function set the nlbits value of CLICCFG register. * \param [in] nlbits nlbits value * \remarks * - nlbits is used to set the width of level in the CLICINTCTL[i]. * \sa * - \ref ECLIC_GetCfgNlbits */ __STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits) { ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk; ECLIC->CFG |= (uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk); } /** * \brief Get nlbits value * \details * This function get the nlbits value of CLICCFG register. * \return nlbits value of CLICCFG register * \remarks * - nlbits is used to set the width of level in the CLICINTCTL[i]. * \sa * - \ref ECLIC_SetCfgNlbits */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void) { return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos)); } /** * \brief Get the ECLIC version number * \details * This function gets the hardware version information from CLICINFO register. * \return hardware version number in CLICINFO register. * \remarks * - This function gets harware version information from CLICINFO register. * - Bit 20:17 for architecture version, bit 16:13 for implementation version. * \sa * - \ref ECLIC_GetInfoNum */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos)); } /** * \brief Get CLICINTCTLBITS * \details * This function gets CLICINTCTLBITS from CLICINFO register. * \return CLICINTCTLBITS from CLICINFO register. * \remarks * - In the CLICINTCTL[i] registers, with 2 <= CLICINTCTLBITS <= 8. * - The implemented bits are kept left-justified in the most-significant bits of each 8-bit * CLICINTCTL[I] register, with the lower unimplemented bits treated as hardwired to 1. * \sa * - \ref ECLIC_GetInfoNum */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos)); } /** * \brief Get number of maximum interrupt inputs supported * \details * This function gets number of maximum interrupt inputs supported from CLICINFO register. * \return number of maximum interrupt inputs supported from CLICINFO register. * \remarks * - This function gets number of maximum interrupt inputs supported from CLICINFO register. * - The num_interrupt field specifies the actual number of maximum interrupt inputs supported in this implementation. * \sa * - \ref ECLIC_GetInfoCtlbits */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void) { return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos)); } /** * \brief Set Machine Mode Interrupt Level Threshold * \details * This function sets machine mode interrupt level threshold. * \param [in] mth Interrupt Level Threshold. * \sa * - \ref ECLIC_GetMth */ __STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth) { ECLIC->MTH = mth; } /** * \brief Get Machine Mode Interrupt Level Threshold * \details * This function gets machine mode interrupt level threshold. * \return Interrupt Level Threshold. * \sa * - \ref ECLIC_SetMth */ __STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void) { return (ECLIC->MTH); } /** * \brief Enable a specific interrupt * \details * This function enables the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_DisableIRQ */ __STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk; } /** * \brief Get a specific interrupt enable status * \details * This function returns the interrupt enable status for the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \returns * - 0 Interrupt is not enabled * - 1 Interrupt is pending * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_EnableIRQ * - \ref ECLIC_DisableIRQ */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk); } /** * \brief Disable a specific interrupt * \details * This function disables the specific interrupt \em IRQn. * \param [in] IRQn Number of the external interrupt to disable * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_EnableIRQ */ __STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk; } /** * \brief Get the pending specific interrupt * \details * This function returns the pending status of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \returns * - 0 Interrupt is not pending * - 1 Interrupt is pending * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_ClearPendingIRQ */ __STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk); } /** * \brief Set a specific interrupt to pending * \details * This function sets the pending bit for the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_GetPendingIRQ * - \ref ECLIC_ClearPendingIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk; } /** * \brief Clear a specific interrupt from pending * \details * This function removes the pending state of the specific interrupt \em IRQn. * \em IRQn cannot be a negative number. * \param [in] IRQn Interrupt number * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetPendingIRQ * - \ref ECLIC_GetPendingIRQ */ __STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn) { ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk; } /** * \brief Set trigger mode and polarity for a specific interrupt * \details * This function set trigger mode and polarity of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] trig * - 00 level trigger, \ref ECLIC_LEVEL_TRIGGER * - 01 positive edge trigger, \ref ECLIC_POSTIVE_EDGE_TRIGGER * - 02 level trigger, \ref ECLIC_LEVEL_TRIGGER * - 03 negative edge trigger, \ref ECLIC_NEGTIVE_EDGE_TRIGGER * \remarks * - IRQn must not be negative. * * \sa * - \ref ECLIC_GetTrigIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig) { ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk; ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig << CLIC_INTATTR_TRIG_Pos); } /** * \brief Get trigger mode and polarity for a specific interrupt * \details * This function get trigger mode and polarity of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return * - 00 level trigger, \ref ECLIC_LEVEL_TRIGGER * - 01 positive edge trigger, \ref ECLIC_POSTIVE_EDGE_TRIGGER * - 02 level trigger, \ref ECLIC_LEVEL_TRIGGER * - 03 negative edge trigger, \ref ECLIC_NEGTIVE_EDGE_TRIGGER * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetTrigIRQ */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos)); } /** * \brief Set interrupt working mode for a specific interrupt * \details * This function set selective hardware vector or non-vector working mode of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] shv * - 0 non-vector mode, \ref ECLIC_NON_VECTOR_INTERRUPT * - 1 vector mode, \ref ECLIC_VECTOR_INTERRUPT * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_GetShvIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv) { ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk; ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv << CLIC_INTATTR_SHV_Pos); } /** * \brief Get interrupt working mode for a specific interrupt * \details * This function get selective hardware vector or non-vector working mode of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return shv * - 0 non-vector mode, \ref ECLIC_NON_VECTOR_INTERRUPT * - 1 vector mode, \ref ECLIC_VECTOR_INTERRUPT * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetShvIRQ */ __STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn) { return ((int32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos)); } /** * \brief Modify ECLIC Interrupt Input Control Register for a specific interrupt * \details * This function modify ECLIC Interrupt Input Control(CLICINTCTL[i]) register of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] intctrl Set value for CLICINTCTL[i] register * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_GetCtrlIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl) { ECLIC->CTRL[IRQn].INTCTRL = intctrl; } /** * \brief Get ECLIC Interrupt Input Control Register value for a specific interrupt * \details * This function modify ECLIC Interrupt Input Control register of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return value of ECLIC Interrupt Input Control register * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetCtrlIRQ */ __STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn) { return (ECLIC->CTRL[IRQn].INTCTRL); } /** * \brief Set ECLIC Interrupt level of a specific interrupt * \details * This function set interrupt level of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] lvl_abs Interrupt level * \remarks * - IRQn must not be negative. * - If lvl_abs to be set is larger than the max level allowed, it will be force to be max level. * - When you set level value you need use clciinfo.nlbits to get the width of level. * Then we could know the maximum of level. CLICINTCTLBITS is how many total bits are * present in the CLICINTCTL register. * \sa * - \ref ECLIC_GetLevelIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits == 0) { return; } if (nlbits > intctlbits) { nlbits = intctlbits; } uint8_t maxlvl = ((1 << nlbits) - 1); if (lvl_abs > maxlvl) { lvl_abs = maxlvl; } uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits); uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); cur_ctrl = cur_ctrl << nlbits; cur_ctrl = cur_ctrl >> nlbits; __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl)); } /** * \brief Get ECLIC Interrupt level of a specific interrupt * \details * This function get interrupt level of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return Interrupt level * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetLevelIRQ */ __STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits == 0) { return 0; } if (nlbits > intctlbits) { nlbits = intctlbits; } uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn); uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits); return lvl_abs; } /** * \brief Get ECLIC Interrupt priority of a specific interrupt * \details * This function get interrupt priority of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] pri Interrupt priority * \remarks * - IRQn must not be negative. * - If pri to be set is larger than the max priority allowed, it will be force to be max priority. * - Priority width is CLICINTCTLBITS minus clciinfo.nlbits if clciinfo.nlbits * is less than CLICINTCTLBITS. Otherwise priority width is 0. * \sa * - \ref ECLIC_GetPriorityIRQ */ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits < intctlbits) { uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1); if (pri > maxpri) { pri = maxpri; } pri = pri << (ECLIC_MAX_NLBITS - intctlbits); uint8_t mask = ((uint8_t)(-1)) >> intctlbits; pri = pri | mask; uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits); cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits); __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri)); } } /** * \brief Get ECLIC Interrupt priority of a specific interrupt * \details * This function get interrupt priority of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return Interrupt priority * \remarks * - IRQn must not be negative. * \sa * - \ref ECLIC_SetPriorityIRQ */ __STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS; if (nlbits < intctlbits) { uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn); uint8_t pri = cur_ctrl << nlbits; pri = pri >> nlbits; pri = pri >> (ECLIC_MAX_NLBITS - intctlbits); return pri; } else { return 0; } } /** * \brief Set Interrupt Vector of a specific interrupt * \details * This function set interrupt handler address of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \param [in] vector Interrupt handler address * \remarks * - IRQn must not be negative. * - You can set the \ref CSR_CSR_MTVT to set interrupt vector table entry address. * - If your vector table is placed in readonly section, the vector for IRQn will not be modified. * For this case, you need to use the correct irq handler name defined in your vector table as * your irq handler function name. * - This function will only work correctly when the vector table is placed in an read-write enabled section. * \sa * - \ref ECLIC_GetVector */ __STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector) { #if __RISCV_XLEN == 32 volatile uint32_t vec_base; vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT)); (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 4)) = vector; #elif __RISCV_XLEN == 64 volatile uint64_t vec_base; vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector; #else // TODO Need cover for XLEN=128 case in future volatile uint64_t vec_base; vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT)); (*(unsigned long *)(vec_base + ((int32_t)IRQn) * 8)) = vector; #endif } /** * \brief Get Interrupt Vector of a specific interrupt * \details * This function get interrupt handler address of the specific interrupt \em IRQn. * \param [in] IRQn Interrupt number * \return Interrupt handler address * \remarks * - IRQn must not be negative. * - You can read \ref CSR_CSR_MTVT to get interrupt vector table entry address. * \sa * - \ref ECLIC_SetVector */ __STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn) { #if __RISCV_XLEN == 32 return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4)); #elif __RISCV_XLEN == 64 return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8)); #else // TODO Need cover for XLEN=128 case in future return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8)); #endif } /** * \brief Set Exception entry address * \details * This function set exception handler address to 'CSR_MTVEC'. * \param [in] addr Exception handler address * \remarks * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align. * \sa * - \ref __get_exc_entry */ __STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr) { addr &= (rv_csr_t)(~0x3F); addr |= ECLIC_MODE_MTVEC_Msk; __RV_CSR_WRITE(CSR_MTVEC, addr); } /** * \brief Get Exception entry address * \details * This function get exception handler address from 'CSR_MTVEC'. * \return Exception handler address * \remarks * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align * \sa * - \ref __set_exc_entry */ __STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void) { unsigned long addr = __RV_CSR_READ(CSR_MTVEC); return (addr & ~ECLIC_MODE_MTVEC_Msk); } /** * \brief Set Non-vector interrupt entry address * \details * This function set Non-vector interrupt address. * \param [in] addr Non-vector interrupt entry address * \remarks * - This function use to set non-vector interrupt entry address to 'CSR_MTVT2' if * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then set address to 'CSR_MTVEC' * \sa * - \ref __get_nonvec_entry */ __STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr) { if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01); } else { addr &= (rv_csr_t)(~0x3F); addr |= ECLIC_MODE_MTVEC_Msk; __RV_CSR_WRITE(CSR_MTVEC, addr); } } /** * \brief Get Non-vector interrupt entry address * \details * This function get Non-vector interrupt address. * \return Non-vector interrupt handler address * \remarks * - This function use to get non-vector interrupt entry address from 'CSR_MTVT2' if * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then get address from 'CSR_MTVEC'. * \sa * - \ref __set_nonvec_entry */ __STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void) { if (__RV_CSR_READ(CSR_MTVT2) & 0x1) { return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1)); } else { rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC); return (addr & ~ECLIC_MODE_MTVEC_Msk); } } /** * \brief Get NMI interrupt entry from 'CSR_MNVEC' * \details * This function get NMI interrupt address from 'CSR_MNVEC'. * \return NMI interrupt handler address * \remarks * - This function use to get NMI interrupt handler address from 'CSR_MNVEC'. If CSR_MMISC_CTL[9] = 1 'CSR_MNVEC' * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector. * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored. */ __STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void) { return __RV_CSR_READ(CSR_MNVEC); } /** * \brief Save necessary CSRs into variables for vector interrupt nesting * \details * This macro is used to declare variables which are used for saving * CSRs(MCAUSE, MEPC, MSUB), and it will read these CSR content into * these variables, it need to be used in a vector-interrupt if nesting * is required. * \remarks * - Interrupt will be enabled after this macro is called * - It need to be used together with \ref RESTORE_IRQ_CSR_CONTEXT * - Don't use variable names __mcause, __mpec, __msubm in your ISR code * - If you want to enable interrupt nesting feature for vector interrupt, * you can do it like this: * \code * // __INTERRUPT attribute will generates function entry and exit sequences suitable * // for use in an interrupt handler when this attribute is present * __INTERRUPT void eclic_mtip_handler(void) * { * // Must call this to save CSRs * SAVE_IRQ_CSR_CONTEXT(); * // !!!Interrupt is enabled here!!! * // !!!Higher priority interrupt could nest it!!! * * // put you own interrupt handling code here * * // Must call this to restore CSRs * RESTORE_IRQ_CSR_CONTEXT(); * } * \endcode */ #define SAVE_IRQ_CSR_CONTEXT() \ rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE); \ rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC); \ rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM); \ __enable_irq(); /** * \brief Restore necessary CSRs from variables for vector interrupt nesting * \details * This macro is used restore CSRs(MCAUSE, MEPC, MSUB) from pre-defined variables * in \ref SAVE_IRQ_CSR_CONTEXT macro. * \remarks * - Interrupt will be disabled after this macro is called * - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT */ #define RESTORE_IRQ_CSR_CONTEXT() \ __disable_irq(); \ __RV_CSR_WRITE(CSR_MSUBM, __msubm); \ __RV_CSR_WRITE(CSR_MEPC, __mepc); \ __RV_CSR_WRITE(CSR_MCAUSE, __mcause); /** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */ #endif /* defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) */ #ifdef __cplusplus } #endif #endif /** __CORE_FEATURE_ECLIC__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_fpu.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_FPU_H__ #define __CORE_FEATURE_FPU_H__ /*! * @file core_feature_fpu.h * @brief FPU feature API header file for Nuclei N/NX Core */ /* * FPU Feature Configuration Macro: * 1. __FPU_PRESENT: Define whether Floating Point Unit(FPU) is present or not * * 0: Not present * * 1: Single precision FPU present, __RISCV_FLEN == 32 * * 2: Double precision FPU present, __RISCV_FLEN == 64 */ #ifdef __cplusplus extern "C" { #endif /* ===== FPU Operations ===== */ /** * \defgroup NMSIS_Core_FPU_Functions FPU Functions * \ingroup NMSIS_Core * \brief Functions that related to the RISC-V FPU (F and D extension). * \details * * Nuclei provided floating point unit by RISC-V F and D extension. * * `F extension` adds single-precision floating-point computational * instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32. * The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide, * and a floating-point control and status register fcsr, which contains the * operating mode and exception status of the floating-point unit. * * `D extension` adds double-precision floating-point computational instructions * compliant with the IEEE 754-2008 arithmetic standard. * The D extension widens the 32 floating-point registers, f0-f31, to 64 bits, __RISCV_FLEN = 64 * @{ */ #if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0) #if __FPU_PRESENT == 1 /** \brief Refer to the width of the floating point register in bits(either 32 or 64) */ #define __RISCV_FLEN 32 #elif __FPU_PRESENT == 2 #define __RISCV_FLEN 64 #else #define __RISCV_FLEN __riscv_flen #endif /* __FPU_PRESENT == 1 */ /** \brief Get FCSR CSR Register */ #define __get_FCSR() __RV_CSR_READ(CSR_FCSR) /** \brief Set FCSR CSR Register with val */ #define __set_FCSR(val) __RV_CSR_WRITE(CSR_FCSR, (val)) /** \brief Get FRM CSR Register */ #define __get_FRM() __RV_CSR_READ(CSR_FRM) /** \brief Set FRM CSR Register with val */ #define __set_FRM(val) __RV_CSR_WRITE(CSR_FRM, (val)) /** \brief Get FFLAGS CSR Register */ #define __get_FFLAGS() __RV_CSR_READ(CSR_FFLAGS) /** \brief Set FFLAGS CSR Register with val */ #define __set_FFLAGS(val) __RV_CSR_WRITE(CSR_FFLAGS, (val)) /** \brief Enable FPU Unit */ #define __enable_FPU() __RV_CSR_SET(CSR_MSTATUS, MSTATUS_FS) /** * \brief Disable FPU Unit * \details * * We can save power by disable FPU Unit. * * When FPU Unit is disabled, any access to FPU related CSR registers * and FPU instructions will cause illegal Instuction Exception. * */ #define __disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS) /** * \brief Load a single-precision value from memory into float point register freg using flw instruction * \details The FLW instruction loads a single-precision floating point value from memory * address (addr + ofs) into floating point register freg(f0-f31) * \param [in] freg The floating point register, eg. FREG(0), f0 * \param [in] addr The memory base address, 4 byte aligned required * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value * \remarks * * FLW and FSW operations need to make sure the address is 4 bytes aligned, * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical * NaNs are preserved * */ #define __RV_FLW(freg, addr, ofs) \ ({ \ register rv_csr_t __addr = (rv_csr_t)(addr); \ __ASM volatile("flw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \ }) /** * \brief Store a single-precision value from float point freg into memory using fsw instruction * \details The FSW instruction stores a single-precision value from floating point register to memory * \param [in] freg The floating point register(f0-f31), eg. FREG(0), f0 * \param [in] addr The memory base address, 4 byte aligned required * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value * \remarks * * FLW and FSW operations need to make sure the address is 4 bytes aligned, * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical * NaNs are preserved * */ #define __RV_FSW(freg, addr, ofs) \ ({ \ register rv_csr_t __addr = (rv_csr_t)(addr); \ __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \ }) /** * \brief Load a double-precision value from memory into float point register freg using fld instruction * \details The FLD instruction loads a double-precision floating point value from memory * address (addr + ofs) into floating point register freg(f0-f31) * \param [in] freg The floating point register, eg. FREG(0), f0 * \param [in] addr The memory base address, 8 byte aligned required * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value * \attention * * Function only available for double precision floating point unit, FLEN = 64 * \remarks * * FLD and FSD operations need to make sure the address is 8 bytes aligned, * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical * NaNs are preserved. */ #define __RV_FLD(freg, addr, ofs) \ ({ \ register rv_csr_t __addr = (rv_csr_t)(addr); \ __ASM volatile("fld " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \ }) /** * \brief Store a double-precision value from float point freg into memory using fsd instruction * \details The FSD instruction stores double-precision value from floating point register to memory * \param [in] freg The floating point register(f0-f31), eg. FREG(0), f0 * \param [in] addr The memory base address, 8 byte aligned required * \param [in] ofs a 12-bit immediate signed byte offset value, should be an const value * \attention * * Function only available for double precision floating point unit, FLEN = 64 * \remarks * * FLD and FSD operations need to make sure the address is 8 bytes aligned, * otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned) * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical * NaNs are preserved. * */ #define __RV_FSD(freg, addr, ofs) \ ({ \ register rv_csr_t __addr = (rv_csr_t)(addr); \ __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1) " : : "I"(ofs), "r"(__addr) : "memory"); \ }) /** * \def __RV_FLOAD * \brief Load a float point value from memory into float point register freg using flw/fld instruction * \details * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): * It will call \ref __RV_FLW to load a single-precision floating point value from memory to floating point register * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): * It will call \ref __RV_FLD to load a double-precision floating point value from memory to floating point register * * \attention * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent */ /** * \def __RV_FSTORE * \brief Store a float value from float point freg into memory using fsw/fsd instruction * \details * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): * It will call \ref __RV_FSW to store floating point register into memory * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): * It will call \ref __RV_FSD to store floating point register into memory * * \attention * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent */ #if __FPU_PRESENT == 1 #define __RV_FLOAD __RV_FLW #define __RV_FSTORE __RV_FSW /** \brief Type of FPU register, depends on the FLEN defined in RISC-V */ typedef uint32_t rv_fpu_t; #elif __FPU_PRESENT == 2 #define __RV_FLOAD __RV_FLD #define __RV_FSTORE __RV_FSD /** \brief Type of FPU register, depends on the FLEN defined in RISC-V */ typedef uint64_t rv_fpu_t; #endif /* __FPU_PRESENT == 2 */ /** * \brief Save FPU context into variables for interrupt nesting * \details * This macro is used to declare variables which are used for saving * FPU context, and it will store the nessary fpu registers into * these variables, it need to be used in a interrupt when in this * interrupt fpu registers are used. * \remarks * - It need to be used together with \ref RESTORE_FPU_CONTEXT * - Don't use variable names __fpu_context in your ISR code * - If you isr code will use fpu registers, and this interrupt is nested. * Then you can do it like this: * \code * void eclic_mtip_handler(void) * { * // !!!Interrupt is enabled here!!! * // !!!Higher priority interrupt could nest it!!! * * // Necessary only when you need to use fpu registers * // in this isr handler functions * SAVE_FPU_CONTEXT(); * * // put you own interrupt handling code here * * // pair of SAVE_FPU_CONTEXT() * RESTORE_FPU_CONTEXT(); * } * \endcode */ #define SAVE_FPU_CONTEXT() \ rv_fpu_t __fpu_context[20]; \ __RV_FSTORE(FREG(0), __fpu_context, 0 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(1), __fpu_context, 1 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(2), __fpu_context, 2 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(3), __fpu_context, 3 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(4), __fpu_context, 4 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(5), __fpu_context, 5 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(6), __fpu_context, 6 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(7), __fpu_context, 7 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(10), __fpu_context, 8 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(11), __fpu_context, 9 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES); \ __RV_FSTORE(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES); /** * \brief Restore necessary fpu registers from variables for interrupt nesting * \details * This macro is used restore necessary fpu registers from pre-defined variables * in \ref SAVE_FPU_CONTEXT macro. * \remarks * - It need to be used together with \ref SAVE_FPU_CONTEXT */ #define RESTORE_FPU_CONTEXT() \ __RV_FLOAD(FREG(0), __fpu_context, 0 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(1), __fpu_context, 1 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(2), __fpu_context, 2 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(3), __fpu_context, 3 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(4), __fpu_context, 4 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(5), __fpu_context, 5 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(6), __fpu_context, 6 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(7), __fpu_context, 7 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(10), __fpu_context, 8 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(11), __fpu_context, 9 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES); \ __RV_FLOAD(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES); #else #define SAVE_FPU_CONTEXT() #define RESTORE_FPU_CONTEXT() #endif /* __FPU_PRESENT > 0 */ /** @} */ /* End of Doxygen Group NMSIS_Core_FPU_Functions */ #ifdef __cplusplus } #endif #endif /** __RISCV_EXT_FPU_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_pmp.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_PMP_H__ #define __CORE_FEATURE_PMP_H__ /*! * @file core_feature_pmp.h * @brief PMP feature API header file for Nuclei N/NX Core */ /* * PMP Feature Configuration Macro: * 1. __PMP_PRESENT: Define whether Physical Memory Protection(PMP) is present or not * * 0: Not present * * 1: Present * 2. __PMP_ENTRY_NUM: Define the number of PMP entries, only 8 or 16 is configurable. */ #ifdef __cplusplus extern "C" { #endif #if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) /* ===== PMP Operations ===== */ /** * \defgroup NMSIS_Core_PMP_Functions PMP Functions * \ingroup NMSIS_Core * \brief Functions that related to the RISCV Phyiscal Memory Protection. * \details * Optional physical memory protection (PMP) unit provides per-hart machine-mode * control registers to allow physical memory access privileges (read, write, execute) * to be specified for each physical memory region. * * The PMP can supports region access control settings as small as four bytes. * * @{ */ #ifndef __PMP_ENTRY_NUM /* numbers of PMP entries(__PMP_ENTRY_NUM) should be defined in */ #error "__PMP_ENTRY_NUM is not defined, please check!" #endif /** * \brief Get 8bit PMPxCFG Register by PMP entry index * \details Return the content of the PMPxCFG Register. * \param [in] idx PMP region index(0-15) * \return PMPxCFG Register value */ __STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx) { rv_csr_t pmpcfg = 0; if (idx >= __PMP_ENTRY_NUM) return 0; #if __RISCV_XLEN == 32 if (idx < 4) { pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); } else if ((idx >= 4) && (idx < 8)) { idx -= 4; pmpcfg = __RV_CSR_READ(CSR_PMPCFG1); } else if ((idx >= 8) && (idx < 12)) { idx -= 8; pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); } else { idx -= 12; pmpcfg = __RV_CSR_READ(CSR_PMPCFG3); } idx = idx << 3; return (uint8_t)((pmpcfg >> idx) & 0xFF); #elif __RISCV_XLEN == 64 if (idx < 8) { pmpcfg = __RV_CSR_READ(CSR_PMPCFG0); } else { idx -= 8; pmpcfg = __RV_CSR_READ(CSR_PMPCFG2); } idx = idx << 3; return (uint8_t)((pmpcfg >> idx) & 0xFF); #else // TODO Add RV128 Handling return 0; #endif } /** * \brief Set 8bit PMPxCFG by pmp entry index * \details Set the given pmpxcfg value to the PMPxCFG Register. * \param [in] idx PMPx region index(0-15) * \param [in] pmpxcfg PMPxCFG register value to set */ __STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg) { rv_csr_t pmpcfgx = 0; if (idx >= __PMP_ENTRY_NUM) return; #if __RISCV_XLEN == 32 if (idx < 4) { pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx); } else if ((idx >= 4) && (idx < 8)) { idx -= 4; pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx); } else if ((idx >= 8) && (idx < 12)) { idx -= 8; pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx); } else { idx -= 12; pmpcfgx = __RV_CSR_READ(CSR_PMPCFG3); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfgx); } #elif __RISCV_XLEN == 64 if (idx < 8) { pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx); } else { idx -= 8; pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2); idx = idx << 3; pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx); __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx); } #else // TODO Add RV128 Handling #endif } /** * \brief Get PMPCFGx Register by index * \details Return the content of the PMPCFGx Register. * \param [in] idx PMPCFG CSR index(0-3) * \return PMPCFGx Register value * \remark * - For RV64, only idx = 0 and idx = 2 is allowed. * pmpcfg0 and pmpcfg2 hold the configurations * for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal * - For RV32, pmpcfg0–pmpcfg3, hold the configurations * pmp0cfg–pmp15cfg for the 16 PMP entries */ __STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx) { switch (idx) { case 0: return __RV_CSR_READ(CSR_PMPCFG0); case 1: return __RV_CSR_READ(CSR_PMPCFG1); case 2: return __RV_CSR_READ(CSR_PMPCFG2); case 3: return __RV_CSR_READ(CSR_PMPCFG3); default: return 0; } } /** * \brief Set PMPCFGx by index * \details Write the given value to the PMPCFGx Register. * \param [in] idx PMPCFG CSR index(0-3) * \param [in] pmpcfg PMPCFGx Register value to set * \remark * - For RV64, only idx = 0 and idx = 2 is allowed. * pmpcfg0 and pmpcfg2 hold the configurations * for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal * - For RV32, pmpcfg0–pmpcfg3, hold the configurations * pmp0cfg–pmp15cfg for the 16 PMP entries */ __STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg) { switch (idx) { case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break; case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break; case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break; case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break; default: return; } } /** * \brief Get PMPADDRx Register by index * \details Return the content of the PMPADDRx Register. * \param [in] idx PMP region index(0-15) * \return PMPADDRx Register value */ __STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx) { switch (idx) { case 0: return __RV_CSR_READ(CSR_PMPADDR0); case 1: return __RV_CSR_READ(CSR_PMPADDR1); case 2: return __RV_CSR_READ(CSR_PMPADDR2); case 3: return __RV_CSR_READ(CSR_PMPADDR3); case 4: return __RV_CSR_READ(CSR_PMPADDR4); case 5: return __RV_CSR_READ(CSR_PMPADDR5); case 6: return __RV_CSR_READ(CSR_PMPADDR6); case 7: return __RV_CSR_READ(CSR_PMPADDR7); case 8: return __RV_CSR_READ(CSR_PMPADDR8); case 9: return __RV_CSR_READ(CSR_PMPADDR9); case 10: return __RV_CSR_READ(CSR_PMPADDR10); case 11: return __RV_CSR_READ(CSR_PMPADDR11); case 12: return __RV_CSR_READ(CSR_PMPADDR12); case 13: return __RV_CSR_READ(CSR_PMPADDR13); case 14: return __RV_CSR_READ(CSR_PMPADDR14); case 15: return __RV_CSR_READ(CSR_PMPADDR15); default: return 0; } } /** * \brief Set PMPADDRx by index * \details Write the given value to the PMPADDRx Register. * \param [in] idx PMP region index(0-15) * \param [in] pmpaddr PMPADDRx Register value to set */ __STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr) { switch (idx) { case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break; case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break; case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break; case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break; case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break; case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break; case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break; case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break; case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break; case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break; case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break; case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break; case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break; case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break; case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break; case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break; default: return; } } /** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */ #endif /* defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) */ #ifdef __cplusplus } #endif #endif /** __CORE_FEATURE_PMP_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/core_feature_timer.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CORE_FEATURE_TIMER_H__ #define __CORE_FEATURE_TIMER_H__ /*! * @file core_feature_timer.h * @brief System Timer feature API header file for Nuclei N/NX Core */ /* * System Timer Feature Configuration Macro: * 1. __SYSTIMER_PRESENT: Define whether Private System Timer is present or not. * * 0: Not present * * 1: Present * 2. __SYSTIMER_BASEADDR: Define the base address of the System Timer. */ #ifdef __cplusplus extern "C" { #endif #if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) /** * \defgroup NMSIS_Core_SysTimer_Registers Register Define and Type Definitions Of System Timer * \ingroup NMSIS_Core_Registers * \brief Type definitions and defines for system timer registers. * * @{ */ /** * \brief Structure type to access the System Timer (SysTimer). * \details * Structure definition to access the system timer(SysTimer). * \remarks * - MSFTRST register is introduced in Nuclei N Core version 1.3(\ref __NUCLEI_N_REV >= 0x0103) * - MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104) * - CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104) */ typedef struct { __IOM uint64_t MTIMER; /*!< Offset: 0x000 (R/W) System Timer current value 64bits Register */ __IOM uint64_t MTIMERCMP; /*!< Offset: 0x008 (R/W) System Timer compare Value 64bits Register */ __IOM uint32_t RESERVED0[0x3F8]; /*!< Offset: 0x010 - 0xFEC Reserved */ __IOM uint32_t MSFTRST; /*!< Offset: 0xFF0 (R/W) System Timer Software Core Reset Register */ __IOM uint32_t RESERVED1; /*!< Offset: 0xFF4 Reserved */ __IOM uint32_t MTIMECTL; /*!< Offset: 0xFF8 (R/W) System Timer Control Register, previously MSTOP register */ __IOM uint32_t MSIP; /*!< Offset: 0xFFC (R/W) System Timer SW interrupt Register */ } SysTimer_Type; /* Timer Control / Status Register Definitions */ #define SysTimer_MTIMECTL_TIMESTOP_Pos 0U /*!< SysTick Timer MTIMECTL: TIMESTOP bit Position */ #define SysTimer_MTIMECTL_TIMESTOP_Msk (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos) /*!< SysTick Timer MTIMECTL: TIMESTOP Mask */ #define SysTimer_MTIMECTL_CMPCLREN_Pos 1U /*!< SysTick Timer MTIMECTL: CMPCLREN bit Position */ #define SysTimer_MTIMECTL_CMPCLREN_Msk (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos) /*!< SysTick Timer MTIMECTL: CMPCLREN Mask */ #define SysTimer_MTIMECTL_CLKSRC_Pos 2U /*!< SysTick Timer MTIMECTL: CLKSRC bit Position */ #define SysTimer_MTIMECTL_CLKSRC_Msk (1UL << SysTimer_MTIMECTL_CLKSRC_Pos) /*!< SysTick Timer MTIMECTL: CLKSRC Mask */ #define SysTimer_MSIP_MSIP_Pos 0U /*!< SysTick Timer MSIP: MSIP bit Position */ #define SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos) /*!< SysTick Timer MSIP: MSIP Mask */ #define SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMER value Mask */ #define SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL) /*!< SysTick Timer MTIMERCMP value Mask */ #define SysTimer_MTIMECTL_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MTIMECTL/MSTOP value Mask */ #define SysTimer_MSIP_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MSIP value Mask */ #define SysTimer_MSFTRST_Msk (0xFFFFFFFFUL) /*!< SysTick Timer MSFTRST value Mask */ #define SysTimer_MSFRST_KEY (0x80000A5FUL) /*!< SysTick Timer Software Reset Request Key */ #ifndef __SYSTIMER_BASEADDR /* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in */ #error "__SYSTIMER_BASEADDR is not defined, please check!" #endif /* System Timer Memory mapping of Device */ #define SysTimer_BASE __SYSTIMER_BASEADDR /*!< SysTick Base Address */ #define SysTimer ((SysTimer_Type *)SysTimer_BASE) /*!< SysTick configuration struct */ /** @} */ /* end of group NMSIS_Core_SysTimer_Registers */ /* ################################## SysTimer function ############################################ */ /** * \defgroup NMSIS_Core_SysTimer SysTimer Functions * \brief Functions that configure the Core System Timer. * @{ */ /** * \brief Set system timer load value * \details * This function set the system timer load value in MTIMER register. * \param [in] value value to set system timer MTIMER register. * \remarks * - Load value is 64bits wide. * - \ref SysTimer_GetLoadValue */ __STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value) { SysTimer->MTIMER = value; } /** * \brief Get system timer load value * \details * This function get the system timer current value in MTIMER register. * \return current value(64bit) of system timer MTIMER register. * \remarks * - Load value is 64bits wide. * - \ref SysTimer_SetLoadValue */ __STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void) { return SysTimer->MTIMER; } /** * \brief Set system timer compare value * \details * This function set the system Timer compare value in MTIMERCMP register. * \param [in] value compare value to set system timer MTIMERCMP register. * \remarks * - Compare value is 64bits wide. * - If compare value is larger than current value timer interrupt generate. * - Modify the load value or compare value less to clear the interrupt. * - \ref SysTimer_GetCompareValue */ __STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value) { SysTimer->MTIMERCMP = value; } /** * \brief Get system timer compare value * \details * This function get the system timer compare value in MTIMERCMP register. * \return compare value of system timer MTIMERCMP register. * \remarks * - Compare value is 64bits wide. * - \ref SysTimer_SetCompareValue */ __STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void) { return SysTimer->MTIMERCMP; } /** * \brief Enable system timer counter running * \details * Enable system timer counter running by clear * TIMESTOP bit in MTIMECTL register. */ __STATIC_FORCEINLINE void SysTimer_Start(void) { SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk); } /** * \brief Stop system timer counter running * \details * Stop system timer counter running by set * TIMESTOP bit in MTIMECTL register. */ __STATIC_FORCEINLINE void SysTimer_Stop(void) { SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk; } /** * \brief Set system timer control value * \details * This function set the system timer MTIMECTL register value. * \param [in] mctl value to set MTIMECTL register * \remarks * - Bit TIMESTOP is used to start and stop timer. * Clear TIMESTOP bit to 0 to start timer, otherwise to stop timer. * - Bit CMPCLREN is used to enable auto MTIMER clear to zero when MTIMER >= MTIMERCMP. * Clear CMPCLREN bit to 0 to stop auto clear MTIMER feature, otherwise to enable it. * - Bit CLKSRC is used to select timer clock source. * Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon* * - \ref SysTimer_GetControlValue */ __STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl) { SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk); } /** * \brief Get system timer control value * \details * This function get the system timer MTIMECTL register value. * \return MTIMECTL register value * \remarks * - \ref SysTimer_SetControlValue */ __STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void) { return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk); } /** * \brief Trigger or set software interrupt via system timer * \details * This function set the system timer MSIP bit in MSIP register. * \remarks * - Set system timer MSIP bit and generate a SW interrupt. * - \ref SysTimer_ClearSWIRQ * - \ref SysTimer_GetMsipValue */ __STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void) { SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk; } /** * \brief Clear system timer software interrupt pending request * \details * This function clear the system timer MSIP bit in MSIP register. * \remarks * - Clear system timer MSIP bit in MSIP register to clear the software interrupt pending. * - \ref SysTimer_SetSWIRQ * - \ref SysTimer_GetMsipValue */ __STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void) { SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk; } /** * \brief Get system timer MSIP register value * \details * This function get the system timer MSIP register value. * \return Value of Timer MSIP register. * \remarks * - Bit0 is SW interrupt flag. * Bit0 is 1 then SW interrupt set. Bit0 is 0 then SW interrupt clear. * - \ref SysTimer_SetSWIRQ * - \ref SysTimer_ClearSWIRQ */ __STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void) { return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk); } /** * \brief Set system timer MSIP register value * \details * This function set the system timer MSIP register value. * \param [in] msip value to set MSIP register */ __STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip) { SysTimer->MSIP = (msip & SysTimer_MSIP_Msk); } /** * \brief Do software reset request * \details * This function will do software reset request through MTIMER * - Software need to write \ref SysTimer_MSFRST_KEY to generate software reset request * - The software request flag can be cleared by reset operation to clear * \remarks * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core * - This function will not return, it will do while(1) to wait the Core reset happened */ __STATIC_FORCEINLINE void SysTimer_SoftwareReset(void) { SysTimer->MSFTRST = SysTimer_MSFRST_KEY; while (1) ; } #if defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) /** * \brief System Tick Configuration * \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer. * * In our default implementation, the timer counter will be set to zero, and it will start a timer compare non-vector interrupt * when it matchs the ticks user set, during the timer interrupt user should reload the system tick using \ref SysTick_Reload function * or similar function written by user, so it can produce period timer interrupt. * \param [in] ticks Number of ticks between two interrupts. * \return 0 Function succeeded. * \return 1 Function failed. * \remarks * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced, * but we assume that the CMPCLREN bit is set to 0, so MTIMER register will not be * auto cleared to 0 when MTIMER >= MTIMERCMP. * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the * function \ref SysTick_Config is not included. * - In this case, the file .h must contain a vendor-specific implementation * of this function. * - If user need this function to start a period timer interrupt, then in timer interrupt handler * routine code, user should call \ref SysTick_Reload with ticks to reload the timer. * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0 * \sa * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue */ __STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks) { SysTimer_SetLoadValue(0); SysTimer_SetCompareValue(ticks); ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); ECLIC_SetLevelIRQ(SysTimer_IRQn, 0); ECLIC_EnableIRQ(SysTimer_IRQn); return (0UL); } /** * \brief System Tick Reload * \details Reload the System Timer Tick when the MTIMECMP reached TIME value * * \param [in] ticks Number of ticks between two interrupts. * \return 0 Function succeeded. * \return 1 Function failed. * \remarks * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced, * but for this \ref SysTick_Config function, we assume this CMPCLREN bit is set to 0, * so in interrupt handler function, user still need to set the MTIMERCMP or MTIMER to reload * the system tick, if vendor want to use this timer's auto clear feature, they can define * \ref __Vendor_SysTickConfig to 1, and implement \ref SysTick_Config and \ref SysTick_Reload functions. * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the * function \ref SysTick_Reload is not included. * - In this case, the file .h must contain a vendor-specific implementation * of this function. * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0 * - Since the MTIMERCMP value might overflow, if overflowed, MTIMER will be set to 0, and MTIMERCMP set to ticks * \sa * - \ref SysTimer_SetCompareValue * - \ref SysTimer_SetLoadValue */ __STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks) { uint64_t cur_ticks = SysTimer->MTIMER; uint64_t reload_ticks = ticks + cur_ticks; if (__USUALLY(reload_ticks > cur_ticks)) { SysTimer->MTIMERCMP = reload_ticks; } else { /* When added the ticks value, then the MTIMERCMP < TIMER, * which means the MTIMERCMP is overflowed, * so we need to reset the counter to zero */ SysTimer->MTIMER = 0; SysTimer->MTIMERCMP = ticks; } return (0UL); } #endif /* defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) */ /** @} */ /* End of Doxygen Group NMSIS_Core_SysTimer */ #endif /* defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) */ #ifdef __cplusplus } #endif #endif /** __CORE_FEATURE_TIMER_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_compiler.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __NMSIS_COMPILER_H #define __NMSIS_COMPILER_H #include /*! * @file nmsis_compiler.h * @brief NMSIS compiler generic header file */ #if defined(__GNUC__) /** GNU GCC Compiler */ #include "nmsis_gcc.h" #else #error Unknown compiler. #endif #endif /* __NMSIS_COMPILER_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_core.h ================================================ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * -- Adaptable modifications made for Nuclei Processors. -- * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __NMSIS_CORE_H__ #define __NMSIS_CORE_H__ #include #ifdef __cplusplus extern "C" { #endif #include "nmsis_version.h" /** * \ingroup NMSIS_Core_VersionControl * @{ */ /* The following enum __NUCLEI_N_REV/__NUCLEI_NX_REV definition in this file * is only used for doxygen documentation generation, * The .h is the real file to define it by vendor */ #if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__) /** * \brief Nuclei N class core revision number * \details * Reversion number format: [15:8] revision number, [7:0] patch number * \attention * This define is exclusive with \ref __NUCLEI_NX_REV */ #define __NUCLEI_N_REV (0x0104) /** * \brief Nuclei NX class core revision number * \details * Reversion number format: [15:8] revision number, [7:0] patch number * \attention * This define is exclusive with \ref __NUCLEI_N_REV */ #define __NUCLEI_NX_REV (0x0100) #endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */ /** @} */ /* End of Group NMSIS_Core_VersionControl */ #include "nmsis_compiler.h" /* NMSIS compiler specific defines */ /* === Include Nuclei Core Related Headers === */ /* Include core base feature header file */ #include "core_feature_base.h" #ifndef __NMSIS_GENERIC /* Include core eclic feature header file */ #include "core_feature_eclic.h" /* Include core systimer feature header file */ #include "core_feature_timer.h" #endif /* Include core fpu feature header file */ #include "core_feature_fpu.h" /* Include core dsp feature header file */ #include "core_feature_dsp.h" /* Include core pmp feature header file */ #include "core_feature_pmp.h" /* Include core cache feature header file */ #include "core_feature_cache.h" /* Include compatiable functions header file */ #include "core_compatiable.h" #ifdef __cplusplus } #endif #endif /* __NMSIS_CORE_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_gcc.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __NMSIS_GCC_H__ #define __NMSIS_GCC_H__ /*! * @file nmsis_gcc.h * @brief NMSIS compiler GCC header file */ #include "riscv_encoding.h" #include #ifdef __cplusplus extern "C" { #endif /* ######################### Startup and Lowlevel Init ######################## */ /** * \defgroup NMSIS_Core_CompilerControl Compiler Control * \ingroup NMSIS_Core * \brief Compiler agnostic \#define symbols for generic c/c++ source code * \details * * The NMSIS-Core provides the header file nmsis_compiler.h with consistent \#define symbols for generate C or C++ source files that should be compiler agnostic. * Each NMSIS compliant compiler should support the functionality described in this section. * * The header file nmsis_compiler.h is also included by each Device Header File so that these definitions are available. * @{ */ /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* NMSIS compiler specific defines */ /** \brief Pass information from the compiler to the assembler. */ #ifndef __ASM #define __ASM __asm #endif /** \brief Recommend that function should be inlined by the compiler. */ #ifndef __INLINE #define __INLINE inline #endif /** \brief Define a static function that may be inlined by the compiler. */ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif /** \brief Define a static function that should be always inlined by the compiler. */ #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif /** \brief Inform the compiler that a function does not return. */ #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif /** \brief Inform that a variable shall be retained in executable image. */ #ifndef __USED #define __USED __attribute__((used)) #endif /** \brief restrict pointer qualifier to enable additional optimizations. */ #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif /** \brief specified the vector size of the variable, measured in bytes */ #ifndef __VECTOR_SIZE #define __VECTOR_SIZE(x) __attribute__((vector_size(x))) #endif /** \brief Request smallest possible alignment. */ #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif /** \brief Request smallest possible alignment for a structure. */ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif /** \brief Request smallest possible alignment for a union. */ #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" /** \brief Packed struct for unaligned uint16_t write access */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop /** \brief Pointer for unaligned write of a uint16_t variable. */ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" /** \brief Packed struct for unaligned uint16_t read access */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop /** \brief Pointer for unaligned read of a uint16_t variable. */ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" /** \brief Packed struct for unaligned uint32_t write access */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop /** \brief Pointer for unaligned write of a uint32_t variable. */ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" /** \brief Packed struct for unaligned uint32_t read access */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop /** \brief Pointer for unaligned read of a uint32_t variable. */ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif /** \brief Minimum `x` bytes alignment for a variable. */ #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif /** \brief restrict pointer qualifier to enable additional optimizations. */ #ifndef __RESTRICT #define __RESTRICT __restrict #endif /** \brief Barrier to prevent compiler from reordering instructions. */ #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("" ::: "memory") #endif /** \brief provide the compiler with branch prediction information, the branch is usually true */ #ifndef __USUALLY #define __USUALLY(exp) __builtin_expect((exp), 1) #endif /** \brief provide the compiler with branch prediction information, the branch is rarely true */ #ifndef __RARELY #define __RARELY(exp) __builtin_expect((exp), 0) #endif /** \brief Use this attribute to indicate that the specified function is an interrupt handler. */ #ifndef __INTERRUPT #define __INTERRUPT __attribute__((interrupt)) #endif /** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */ /* IO definitions (access restrictions to peripheral registers) */ /** * \defgroup NMSIS_Core_PeriphAccess Peripheral Access * \brief Naming conventions and optional features for accessing peripherals. * * The section below describes the naming conventions, requirements, and optional features * for accessing device specific peripherals. * Most of the rules also apply to the core peripherals. * * The **Device Header File ** contains typically these definition * and also includes the core specific header files. * * @{ */ /** \brief Defines 'read only' permissions */ #ifdef __cplusplus #define __I volatile #else #define __I volatile const #endif /** \brief Defines 'write only' permissions */ #define __O volatile /** \brief Defines 'read / write' permissions */ #define __IO volatile /* following defines should be used for structure members */ /** \brief Defines 'read only' structure member permissions */ #define __IM volatile const /** \brief Defines 'write only' structure member permissions */ #define __OM volatile /** \brief Defines 'read/write' structure member permissions */ #define __IOM volatile /** * \brief Mask and shift a bit field value for use in a register bit range. * \details The macro \ref _VAL2FLD uses the #define's _Pos and _Msk of the related bit * field to shift bit-field values for assigning to a register. * * **Example**: * \code * ECLIC->CFG = _VAL2FLD(CLIC_CLICCFG_NLBIT, 3); * \endcode * \param[in] field Name of the register bit field. * \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. * \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk) /** * \brief Mask and shift a register value to extract a bit filed value. * \details The macro \ref _FLD2VAL uses the #define's _Pos and _Msk of the related bit * field to extract the value of a bit field from a register. * * **Example**: * \code * nlbits = _FLD2VAL(CLIC_CLICCFG_NLBIT, ECLIC->CFG); * \endcode * \param[in] field Name of the register bit field. * \param[in] value Value of register. This parameter is interpreted as an uint32_t type. * \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos) /** @} */ /* end of group NMSIS_Core_PeriphAccess */ #ifdef __cplusplus } #endif #endif /* __NMSIS_GCC_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/nmsis_version.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __NMSIS_VERSION_H #define __NMSIS_VERSION_H /** * \defgroup NMSIS_Core_VersionControl Version Control * \ingroup NMSIS_Core * \brief Version \#define symbols for NMSIS release specific C/C++ source code * \details * * We followed the [semantic versioning 2.0.0](https://semver.org/) to control NMSIS version. * The version format is **MAJOR.MINOR.PATCH**, increment the: * 1. MAJOR version when you make incompatible API changes, * 2. MINOR version when you add functionality in a backwards compatible manner, and * 3. PATCH version when you make backwards compatible bug fixes. * * The header file `nmsis_version.h` is included by each core header so that these definitions are available. * * **Example Usage for NMSIS Version Check**: * \code * #if defined(__NMSIS_VERSION) && (__NMSIS_VERSION >= 0x00010105) * #warning "Yes, we have NMSIS 1.1.5 or later" * #else * #error "We need NMSIS 1.1.5 or later!" * #endif * \endcode * * @{ */ /*! * \file nmsis_version.h * \brief NMSIS Version definitions **/ /** * \brief Represent the NMSIS major version * \details * The NMSIS major version can be used to * differentiate between NMSIS major releases. * */ #define __NMSIS_VERSION_MAJOR (1U) /** * \brief Represent the NMSIS minor version * \details * The NMSIS minor version can be used to * query a NMSIS release update including new features. * **/ #define __NMSIS_VERSION_MINOR (0U) /** * \brief Represent the NMSIS patch version * \details * The NMSIS patch version can be used to * show bug fixes in this package. **/ #define __NMSIS_VERSION_PATCH (0U) /** * \brief Represent the NMSIS Version * \details * NMSIS Version format: **MAJOR.MINOR.PATCH** * * MAJOR: \ref __NMSIS_VERSION_MAJOR, stored in `bits [31:16]` of \ref __NMSIS_VERSION * * MINOR: \ref __NMSIS_VERSION_MINOR, stored in `bits [15:8]` of \ref __NMSIS_VERSION * * PATCH: \ref __NMSIS_VERSION_PATCH, stored in `bits [7:0]` of \ref __NMSIS_VERSION **/ #define __NMSIS_VERSION ((__NMSIS_VERSION_MAJOR << 16U) | (__NMSIS_VERSION_MINOR << 8) | __NMSIS_VERSION_PATCH) /** @} */ /* End of Doxygen Group NMSIS_Core_VersionControl */ #endif ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_bits.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __RISCV_BITS_H__ #define __RISCV_BITS_H__ #ifdef __cplusplus extern "C" { #endif #if __riscv_xlen == 64 #define SLL32 sllw #define STORE sd #define LOAD ld #define LWU lwu #define LOG_REGBYTES 3 #else #define SLL32 sll #define STORE sw #define LOAD lw #define LWU lw #define LOG_REGBYTES 2 #endif /* __riscv_xlen */ #define REGBYTES (1 << LOG_REGBYTES) #ifdef __riscv_flen #if __riscv_flen == 64 #define FPSTORE fsd #define FPLOAD fld #define LOG_FPREGBYTES 3 #else #define FPSTORE fsw #define FPLOAD flw #define LOG_FPREGBYTES 2 #endif /* __riscv_flen */ #endif #define FPREGBYTES (1 << LOG_FPREGBYTES) #define __rv_likely(x) __builtin_expect((x), 1) #define __rv_unlikely(x) __builtin_expect((x), 0) #define __RV_ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) #define __RV_ROUNDDOWN(a, b) ((a) / (b) * (b)) #define __RV_MAX(a, b) ((a) > (b) ? (a) : (b)) #define __RV_MIN(a, b) ((a) < (b) ? (a) : (b)) #define __RV_CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) #define __RV_EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define __RV_INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) #ifdef __ASSEMBLY__ #define _AC(X, Y) X #define _AT(T, X) X #else #define __AC(X, Y) (X##Y) #define _AC(X, Y) __AC(X, Y) #define _AT(T, X) ((T)(X)) #endif /* __ASSEMBLY__ */ #define _UL(x) (_AC(x, UL)) #define _ULL(x) (_AC(x, ULL)) #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) #define UL(x) (_UL(x)) #define ULL(x) (_ULL(x)) #define STR(x) XSTR(x) #define XSTR(x) #x #define __STR(s) #s #define STRINGIFY(s) __STR(s) #ifdef __cplusplus } #endif #endif /** __RISCV_BITS_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/NMSIS/Core/Include/riscv_encoding.h ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __RISCV_ENCODING_H__ #define __RISCV_ENCODING_H__ #include "riscv_bits.h" #ifdef __cplusplus extern "C" { #endif /** * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings * \ingroup NMSIS_Core * \brief NMSIS Core CSR Encodings * \details * * The following macros are used for CSR encodings * @{ */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 #define MSTATUS_MIE 0x00000008 #define MSTATUS_UPIE 0x00000010 #define MSTATUS_SPIE 0x00000020 #define MSTATUS_HPIE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 #define MSTATUS_MPRV 0x00020000 #define MSTATUS_PUM 0x00040000 #define MSTATUS_MXR 0x00080000 #define MSTATUS_VM 0x1F000000 #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000 #define MSTATUS_FS_INITIAL 0x00002000 #define MSTATUS_FS_CLEAN 0x00004000 #define MSTATUS_FS_DIRTY 0x00006000 #define SSTATUS_UIE 0x00000001 #define SSTATUS_SIE 0x00000002 #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_PUM 0x00040000 #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 #define CSR_MCACHE_CTL_IE 0x00000001 #define CSR_MCACHE_CTL_DE 0x00010000 #define DCSR_XDEBUGVER (3U << 30) #define DCSR_NDRESET (1 << 29) #define DCSR_FULLRESET (1 << 28) #define DCSR_EBREAKM (1 << 15) #define DCSR_EBREAKH (1 << 14) #define DCSR_EBREAKS (1 << 13) #define DCSR_EBREAKU (1 << 12) #define DCSR_STOPCYCLE (1 << 10) #define DCSR_STOPTIME (1 << 9) #define DCSR_CAUSE (7 << 6) #define DCSR_DEBUGINT (1 << 5) #define DCSR_HALT (1 << 3) #define DCSR_STEP (1 << 2) #define DCSR_PRV (3 << 0) #define DCSR_CAUSE_NONE 0 #define DCSR_CAUSE_SWBP 1 #define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 #define DCSR_CAUSE_STEP 4 #define DCSR_CAUSE_HALT 5 #define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) #define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) #define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) #define MCONTROL_SELECT (1 << 19) #define MCONTROL_TIMING (1 << 18) #define MCONTROL_ACTION (0x3f << 12) #define MCONTROL_CHAIN (1 << 11) #define MCONTROL_MATCH (0xf << 7) #define MCONTROL_M (1 << 6) #define MCONTROL_H (1 << 5) #define MCONTROL_S (1 << 4) #define MCONTROL_U (1 << 3) #define MCONTROL_EXECUTE (1 << 2) #define MCONTROL_STORE (1 << 1) #define MCONTROL_LOAD (1 << 0) #define MCONTROL_TYPE_NONE 0 #define MCONTROL_TYPE_MATCH 2 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 #define MCONTROL_ACTION_DEBUG_MODE 1 #define MCONTROL_ACTION_TRACE_START 2 #define MCONTROL_ACTION_TRACE_STOP 3 #define MCONTROL_ACTION_TRACE_EMIT 4 #define MCONTROL_MATCH_EQUAL 0 #define MCONTROL_MATCH_NAPOT 1 #define MCONTROL_MATCH_GE 2 #define MCONTROL_MATCH_LT 3 #define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) #define MIP_STIP (1 << IRQ_S_TIMER) #define MIP_HTIP (1 << IRQ_H_TIMER) #define MIP_MTIP (1 << IRQ_M_TIMER) #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_HEIP (1 << IRQ_H_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) #define MIE_SSIE MIP_SSIP #define MIE_HSIE MIP_HSIP #define MIE_MSIE MIP_MSIP #define MIE_STIE MIP_STIP #define MIE_HTIE MIP_HTIP #define MIE_MTIE MIP_MTIP #define MIE_SEIE MIP_SEIP #define MIE_HEIE MIP_HEIP #define MIE_MEIE MIP_MEIP /* === Nuclei custom CSR bit mask === */ #define WFE_WFE (0x1) #define TXEVT_TXEVT (0x1) #define SLEEPVALUE_SLEEPVALUE (0x1) #define MCOUNTINHIBIT_IR (1 << 2) #define MCOUNTINHIBIT_CY (1 << 0) #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10) #define MILM_CTL_ILM_EN (1 << 0) #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10) #define MDLM_CTL_DLM_EN (1 << 0) #define MSUBM_PTYP (0x3 << 8) #define MSUBM_TYP (0x3 << 6) #define MDCAUSE_MDCAUSE (0x3) #define MMISC_CTL_NMI_CAUSE_FFF (1 << 9) #define MMISC_CTL_MISALIGN (1 << 6) #define MMISC_CTL_BPU (1 << 3) #define MCACHE_CTL_IC_EN (1 << 0) #define MCACHE_CTL_IC_SCPD_MOD (1 << 1) #define MCACHE_CTL_DC_EN (1 << 16) #define MTVT2_MTVT2EN (1 << 0) #define MTVT2_COMMON_CODE_ENTRY (((1ULL << ((__riscv_xlen)-2)) - 1) << 2) #define MCFG_INFO_TEE (1 << 0) #define MCFG_INFO_ECC (1 << 1) #define MCFG_INFO_CLIC (1 << 2) #define MCFG_INFO_PLIC (1 << 3) #define MCFG_INFO_FIO (1 << 4) #define MCFG_INFO_PPI (1 << 5) #define MCFG_INFO_NICE (1 << 6) #define MCFG_INFO_ILM (1 << 7) #define MCFG_INFO_DLM (1 << 8) #define MCFG_INFO_ICACHE (1 << 9) #define MCFG_INFO_DCACHE (1 << 10) #define MICFG_IC_SET (0xF << 0) #define MICFG_IC_WAY (0x7 << 4) #define MICFG_IC_LSIZE (0x7 << 7) #define MICFG_ILM_SIZE (0x1F << 16) #define MICFG_ILM_XONLY (1 << 21) #define MDCFG_DC_SET (0xF << 0) #define MDCFG_DC_WAY (0x7 << 4) #define MDCFG_DC_LSIZE (0x7 << 7) #define MDCFG_DLM_SIZE (0x1F << 16) #define MPPICFG_INFO_PPI_SIZE (0x1F << 1) #define MPPICFG_INFO_PPI_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10) #define MFIOCFG_INFO_FIO_SIZE (0x1F << 1) #define MFIOCFG_INFO_FIO_BPA (((1ULL << ((__riscv_xlen)-10)) - 1) << 10) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 #define PRV_M 3 #define VM_MBARE 0 #define VM_MBB 1 #define VM_MBBID 2 #define VM_SV32 8 #define VM_SV39 9 #define VM_SV48 10 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 #define IRQ_S_TIMER 5 #define IRQ_H_TIMER 6 #define IRQ_M_TIMER 7 #define IRQ_S_EXT 9 #define IRQ_H_EXT 10 #define IRQ_M_EXT 11 #define IRQ_COP 12 #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 #define DEFAULT_NMIVEC 0x00001004 #define DEFAULT_MTVEC 0x00001010 #define CONFIG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 /* === FPU FRM Rounding Mode === */ /** FPU Round to Nearest, ties to Even*/ #define FRM_RNDMODE_RNE 0x0 /** FPU Round Towards Zero */ #define FRM_RNDMODE_RTZ 0x1 /** FPU Round Down (towards -inf) */ #define FRM_RNDMODE_RDN 0x2 /** FPU Round Up (towards +inf) */ #define FRM_RNDMODE_RUP 0x3 /** FPU Round to nearest, ties to Max Magnitude */ #define FRM_RNDMODE_RMM 0x4 /** * In instruction's rm, selects dynamic rounding mode. * In Rounding Mode register, Invalid */ #define FRM_RNDMODE_DYN 0x7 /* === FPU FFLAGS Accrued Exceptions === */ /** FPU Inexact */ #define FFLAGS_AE_NX (1 << 0) /** FPU Underflow */ #define FFLAGS_AE_UF (1 << 1) /** FPU Overflow */ #define FFLAGS_AE_OF (1 << 2) /** FPU Divide by Zero */ #define FFLAGS_AE_DZ (1 << 3) /** FPU Invalid Operation */ #define FFLAGS_AE_NV (1 << 4) /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ #define FREG(idx) f##idx /* === PMP CFG Bits === */ #define PMP_R 0x01 #define PMP_W 0x02 #define PMP_X 0x04 #define PMP_A 0x18 #define PMP_A_TOR 0x08 #define PMP_A_NA4 0x10 #define PMP_A_NAPOT 0x18 #define PMP_L 0x80 #define PMP_SHIFT 2 #define PMP_COUNT 16 // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_R 0x002 // Read #define PTE_W 0x004 // Write #define PTE_X 0x008 // Execute #define PTE_U 0x010 // User #define PTE_G 0x020 // Global #define PTE_A 0x040 // Accessed #define PTE_D 0x080 // Dirty #define PTE_SOFT 0x300 // Reserved for Software #define PTE_PPN_SHIFT 10 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) #ifdef __riscv #ifdef __riscv64 #define MSTATUS_SD MSTATUS64_SD #define SSTATUS_SD SSTATUS64_SD #define RISCV_PGLEVEL_BITS 9 #else #define MSTATUS_SD MSTATUS32_SD #define SSTATUS_SD SSTATUS32_SD #define RISCV_PGLEVEL_BITS 10 #endif /* __riscv64 */ #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) #endif /* __riscv */ #define DOWNLOAD_MODE_FLASHXIP 0 #define DOWNLOAD_MODE_FLASH 1 #define DOWNLOAD_MODE_ILM 2 #define DOWNLOAD_MODE_DDR 3 /** * \defgroup NMSIS_Core_CSR_Registers Core CSR Registers * \ingroup NMSIS_Core * \brief NMSIS Core CSR Register Definitions * \details * * The following macros are used for CSR Register Defintions. * @{ */ /* === Standard RISC-V CSR Registers === */ #define CSR_USTATUS 0x0 #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 #define CSR_INSTRET 0xc02 #define CSR_HPMCOUNTER3 0xc03 #define CSR_HPMCOUNTER4 0xc04 #define CSR_HPMCOUNTER5 0xc05 #define CSR_HPMCOUNTER6 0xc06 #define CSR_HPMCOUNTER7 0xc07 #define CSR_HPMCOUNTER8 0xc08 #define CSR_HPMCOUNTER9 0xc09 #define CSR_HPMCOUNTER10 0xc0a #define CSR_HPMCOUNTER11 0xc0b #define CSR_HPMCOUNTER12 0xc0c #define CSR_HPMCOUNTER13 0xc0d #define CSR_HPMCOUNTER14 0xc0e #define CSR_HPMCOUNTER15 0xc0f #define CSR_HPMCOUNTER16 0xc10 #define CSR_HPMCOUNTER17 0xc11 #define CSR_HPMCOUNTER18 0xc12 #define CSR_HPMCOUNTER19 0xc13 #define CSR_HPMCOUNTER20 0xc14 #define CSR_HPMCOUNTER21 0xc15 #define CSR_HPMCOUNTER22 0xc16 #define CSR_HPMCOUNTER23 0xc17 #define CSR_HPMCOUNTER24 0xc18 #define CSR_HPMCOUNTER25 0xc19 #define CSR_HPMCOUNTER26 0xc1a #define CSR_HPMCOUNTER27 0xc1b #define CSR_HPMCOUNTER28 0xc1c #define CSR_HPMCOUNTER29 0xc1d #define CSR_HPMCOUNTER30 0xc1e #define CSR_HPMCOUNTER31 0xc1f #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 #define CSR_SBADADDR 0x143 #define CSR_SIP 0x144 #define CSR_SPTBR 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 #define CSR_MBADADDR 0x343 #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 #define CSR_PMPCFG3 0x3a3 #define CSR_PMPADDR0 0x3b0 #define CSR_PMPADDR1 0x3b1 #define CSR_PMPADDR2 0x3b2 #define CSR_PMPADDR3 0x3b3 #define CSR_PMPADDR4 0x3b4 #define CSR_PMPADDR5 0x3b5 #define CSR_PMPADDR6 0x3b6 #define CSR_PMPADDR7 0x3b7 #define CSR_PMPADDR8 0x3b8 #define CSR_PMPADDR9 0x3b9 #define CSR_PMPADDR10 0x3ba #define CSR_PMPADDR11 0x3bb #define CSR_PMPADDR12 0x3bc #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 #define CSR_MCYCLE 0xb00 #define CSR_MINSTRET 0xb02 #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 #define CSR_MHPMCOUNTER5 0xb05 #define CSR_MHPMCOUNTER6 0xb06 #define CSR_MHPMCOUNTER7 0xb07 #define CSR_MHPMCOUNTER8 0xb08 #define CSR_MHPMCOUNTER9 0xb09 #define CSR_MHPMCOUNTER10 0xb0a #define CSR_MHPMCOUNTER11 0xb0b #define CSR_MHPMCOUNTER12 0xb0c #define CSR_MHPMCOUNTER13 0xb0d #define CSR_MHPMCOUNTER14 0xb0e #define CSR_MHPMCOUNTER15 0xb0f #define CSR_MHPMCOUNTER16 0xb10 #define CSR_MHPMCOUNTER17 0xb11 #define CSR_MHPMCOUNTER18 0xb12 #define CSR_MHPMCOUNTER19 0xb13 #define CSR_MHPMCOUNTER20 0xb14 #define CSR_MHPMCOUNTER21 0xb15 #define CSR_MHPMCOUNTER22 0xb16 #define CSR_MHPMCOUNTER23 0xb17 #define CSR_MHPMCOUNTER24 0xb18 #define CSR_MHPMCOUNTER25 0xb19 #define CSR_MHPMCOUNTER26 0xb1a #define CSR_MHPMCOUNTER27 0xb1b #define CSR_MHPMCOUNTER28 0xb1c #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f #define CSR_MUCOUNTEREN 0x320 #define CSR_MSCOUNTEREN 0x321 #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 #define CSR_MHPMEVENT6 0x326 #define CSR_MHPMEVENT7 0x327 #define CSR_MHPMEVENT8 0x328 #define CSR_MHPMEVENT9 0x329 #define CSR_MHPMEVENT10 0x32a #define CSR_MHPMEVENT11 0x32b #define CSR_MHPMEVENT12 0x32c #define CSR_MHPMEVENT13 0x32d #define CSR_MHPMEVENT14 0x32e #define CSR_MHPMEVENT15 0x32f #define CSR_MHPMEVENT16 0x330 #define CSR_MHPMEVENT17 0x331 #define CSR_MHPMEVENT18 0x332 #define CSR_MHPMEVENT19 0x333 #define CSR_MHPMEVENT20 0x334 #define CSR_MHPMEVENT21 0x335 #define CSR_MHPMEVENT22 0x336 #define CSR_MHPMEVENT23 0x337 #define CSR_MHPMEVENT24 0x338 #define CSR_MHPMEVENT25 0x339 #define CSR_MHPMEVENT26 0x33a #define CSR_MHPMEVENT27 0x33b #define CSR_MHPMEVENT28 0x33c #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 #define CSR_HPMCOUNTER3H 0xc83 #define CSR_HPMCOUNTER4H 0xc84 #define CSR_HPMCOUNTER5H 0xc85 #define CSR_HPMCOUNTER6H 0xc86 #define CSR_HPMCOUNTER7H 0xc87 #define CSR_HPMCOUNTER8H 0xc88 #define CSR_HPMCOUNTER9H 0xc89 #define CSR_HPMCOUNTER10H 0xc8a #define CSR_HPMCOUNTER11H 0xc8b #define CSR_HPMCOUNTER12H 0xc8c #define CSR_HPMCOUNTER13H 0xc8d #define CSR_HPMCOUNTER14H 0xc8e #define CSR_HPMCOUNTER15H 0xc8f #define CSR_HPMCOUNTER16H 0xc90 #define CSR_HPMCOUNTER17H 0xc91 #define CSR_HPMCOUNTER18H 0xc92 #define CSR_HPMCOUNTER19H 0xc93 #define CSR_HPMCOUNTER20H 0xc94 #define CSR_HPMCOUNTER21H 0xc95 #define CSR_HPMCOUNTER22H 0xc96 #define CSR_HPMCOUNTER23H 0xc97 #define CSR_HPMCOUNTER24H 0xc98 #define CSR_HPMCOUNTER25H 0xc99 #define CSR_HPMCOUNTER26H 0xc9a #define CSR_HPMCOUNTER27H 0xc9b #define CSR_HPMCOUNTER28H 0xc9c #define CSR_HPMCOUNTER29H 0xc9d #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f #define CSR_MCYCLEH 0xb80 #define CSR_MINSTRETH 0xb82 #define CSR_MHPMCOUNTER3H 0xb83 #define CSR_MHPMCOUNTER4H 0xb84 #define CSR_MHPMCOUNTER5H 0xb85 #define CSR_MHPMCOUNTER6H 0xb86 #define CSR_MHPMCOUNTER7H 0xb87 #define CSR_MHPMCOUNTER8H 0xb88 #define CSR_MHPMCOUNTER9H 0xb89 #define CSR_MHPMCOUNTER10H 0xb8a #define CSR_MHPMCOUNTER11H 0xb8b #define CSR_MHPMCOUNTER12H 0xb8c #define CSR_MHPMCOUNTER13H 0xb8d #define CSR_MHPMCOUNTER14H 0xb8e #define CSR_MHPMCOUNTER15H 0xb8f #define CSR_MHPMCOUNTER16H 0xb90 #define CSR_MHPMCOUNTER17H 0xb91 #define CSR_MHPMCOUNTER18H 0xb92 #define CSR_MHPMCOUNTER19H 0xb93 #define CSR_MHPMCOUNTER20H 0xb94 #define CSR_MHPMCOUNTER21H 0xb95 #define CSR_MHPMCOUNTER22H 0xb96 #define CSR_MHPMCOUNTER23H 0xb97 #define CSR_MHPMCOUNTER24H 0xb98 #define CSR_MHPMCOUNTER25H 0xb99 #define CSR_MHPMCOUNTER26H 0xb9a #define CSR_MHPMCOUNTER27H 0xb9b #define CSR_MHPMCOUNTER28H 0xb9c #define CSR_MHPMCOUNTER29H 0xb9d #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f /* === CLIC CSR Registers === */ #define CSR_MTVT 0x307 #define CSR_MNXTI 0x345 #define CSR_MINTSTATUS 0x346 #define CSR_MSCRATCHCSW 0x348 #define CSR_MSCRATCHCSWL 0x349 #define CSR_MCLICBASE 0x350 /* === Nuclei custom CSR Registers === */ #define CSR_MCOUNTINHIBIT 0x320 #define CSR_MILM_CTL 0x7C0 #define CSR_MDLM_CTL 0x7C1 #define CSR_MNVEC 0x7C3 #define CSR_MSUBM 0x7C4 #define CSR_MDCAUSE 0x7C9 #define CSR_MCACHE_CTL 0x7CA #define CSR_MMISC_CTL 0x7D0 #define CSR_MSAVESTATUS 0x7D6 #define CSR_MSAVEEPC1 0x7D7 #define CSR_MSAVECAUSE1 0x7D8 #define CSR_MSAVEEPC2 0x7D9 #define CSR_MSAVECAUSE2 0x7DA #define CSR_MSAVEDCAUSE1 0x7DB #define CSR_MSAVEDCAUSE2 0x7DC #define CSR_PUSHMSUBM 0x7EB #define CSR_MTVT2 0x7EC #define CSR_JALMNXTI 0x7ED #define CSR_PUSHMCAUSE 0x7EE #define CSR_PUSHMEPC 0x7EF #define CSR_MPPICFG_INFO 0x7F0 #define CSR_MFIOCFG_INFO 0x7F1 #define CSR_SLEEPVALUE 0x811 #define CSR_TXEVT 0x812 #define CSR_WFE 0x810 #define CSR_MICFG_INFO 0xFC0 #define CSR_MDCFG_INFO 0xFC1 #define CSR_MCFG_INFO 0xFC2 /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/ /* Exception Code in MCAUSE CSR */ #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_FAULT_LOAD 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_FAULT_STORE 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb /* Exception Subcode in MDCAUSE CSR */ #define DCAUSE_FAULT_FETCH_PMP 0x1 #define DCAUSE_FAULT_FETCH_INST 0x2 #define DCAUSE_FAULT_LOAD_PMP 0x1 #define DCAUSE_FAULT_LOAD_INST 0x2 #define DCAUSE_FAULT_LOAD_NICE 0x3 #define DCAUSE_FAULT_STORE_PMP 0x1 #define DCAUSE_FAULT_STORE_INST 0x2 #define read_fpu(reg) \ ({ \ unsigned long __tmp; \ asm volatile("fmv.x.w %0, " #reg : "=r"(__tmp)); \ __tmp; \ }) #define write_fpu(reg, val) \ ({ \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile("fmv.w.x " #reg ", %0" ::"i"(val)); \ else \ asm volatile("fmv.w.x " #reg ", %0" ::"r"(val)); \ }) #define read_csr(reg) \ ({ \ unsigned long __tmp; \ asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; \ }) #define write_csr(reg, val) \ ({ \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile("csrw " #reg ", %0" ::"i"(val)); \ else \ asm volatile("csrw " #reg ", %0" ::"r"(val)); \ }) #define swap_csr(reg, val) \ ({ \ unsigned long __tmp; \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ else \ asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ __tmp; \ }) #define set_csr(reg, bit) \ ({ \ unsigned long __tmp; \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; \ }) #define clear_csr(reg, bit) \ ({ \ unsigned long __tmp; \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; \ }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) #define rdinstret() read_csr(instret) #define ECLICINTCTLBITS 4 /*ECLIC memory map */ /* Offset */ /* 0x0000 1B RW ecliccfg */ #define ECLIC_CFG_OFFSET 0x0 /* 0x0004 4B R eclicinfo */ #define ECLIC_INFO_OFFSET 0x4 /* 0x000B 1B RW mintthresh */ #define ECLIC_MTH_OFFSET 0xB /* 0x1000+4*i 1B/input RW eclicintip[i] */ #define ECLIC_INT_IP_OFFSET _AC(0x1000, UL) /* 0x1001+4*i 1B/input RW eclicintie[i] */ #define ECLIC_INT_IE_OFFSET _AC(0x1001, UL) /* 0x1002+4*i 1B/input RW eclicintattr[i]*/ #define ECLIC_INT_ATTR_OFFSET _AC(0x1002, UL) #define ECLIC_INT_ATTR_SHV 0x01 #define ECLIC_INT_ATTR_TRIG_LEVEL 0x00 #define ECLIC_INT_ATTR_TRIG_EDGE 0x02 #define ECLIC_INT_ATTR_TRIG_POS 0x00 #define ECLIC_INT_ATTR_TRIG_NEG 0x04 /* 0x1003+4*i 1B/input RW eclicintctl[i] */ #define ECLIC_INT_CTRL_OFFSET _AC(0x1003, UL) #define ECLIC_ADDR_BASE 0xd2000000 #define ECLIC_CFG_NLBITS_MASK _AC(0x1E, UL) #define ECLIC_CFG_NLBITS_LSB (1u) #define MSIP_HANDLER eclic_msip_handler #define MTIME_HANDLER eclic_mtip_handler #define BWEI_HANDLER eclic_bwei_handler #define PMOVI_HANDLER eclic_pmovi_handler #define TIMER_MSIP 0xFFC #define TIMER_MSIP_size 0x4 #define TIMER_MTIMECMP 0x8 #define TIMER_MTIMECMP_size 0x8 #define TIMER_MTIME 0x0 #define TIMER_MTIME_size 0x8 #define TIMER_CTRL_ADDR 0xd1000000 #define TIMER_REG(offset) _REG32(TIMER_CTRL_ADDR, offset) #define TIMER_FREQ ((uint32_t)SystemCoreClock / 4) /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/ #ifdef __cplusplus } #endif #endif /* __RISCV_ENCODING_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/port.c ================================================ /* * FreeRTOS Kernel V10.2.1 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ /*----------------------------------------------------------- * Implementation of functions defined in portable.h for the Nuclei N/NX Processor port. *----------------------------------------------------------*/ /* Scheduler includes. */ #include "FreeRTOS.h" #include "task.h" #include // #define ENABLE_KERNEL_DEBUG #ifdef ENABLE_KERNEL_DEBUG #define FREERTOS_PORT_DEBUG(...) printf(__VA_ARGS__) #else #define FREERTOS_PORT_DEBUG(...) #endif #ifndef configSYSTICK_CLOCK_HZ #define configSYSTICK_CLOCK_HZ SOC_TIMER_FREQ #endif #ifndef configKERNEL_INTERRUPT_PRIORITY #define configKERNEL_INTERRUPT_PRIORITY 0 #endif #ifndef configMAX_SYSCALL_INTERRUPT_PRIORITY // See function prvCheckMaxSysCallPrio and prvCalcMaxSysCallMTH #define configMAX_SYSCALL_INTERRUPT_PRIORITY 255 #endif /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER (18) #define SYSTICK_TICK_CONST (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) /* Masks off all bits but the ECLIC MTH bits in the MTH register. */ #define portMTH_MASK (0xFFUL) /* Constants required to set up the initial stack. */ #define portINITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL) #define portINITIAL_EXC_RETURN (0xfffffffd) /* The systick is a 64-bit counter. */ #define portMAX_BIT_NUMBER (SysTimer_MTIMER_Msk) /* A fiddle factor to estimate the number of SysTick counts that would have occurred while the SysTick counter is stopped during tickless idle calculations. */ #define portMISSED_COUNTS_FACTOR (45UL) /* Let the user override the pre-loading of the initial LR with the address of prvTaskExitError() in case it messes up unwinding of the stack in the debugger. */ #ifdef configTASK_RETURN_ADDRESS #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS #else #define portTASK_RETURN_ADDRESS prvTaskExitError #endif /* * Setup the timer to generate the tick interrupts. The implementation in this * file is weak to allow application writers to change the timer used to * generate the tick interrupt. */ void vPortSetupTimerInterrupt(void); /* * Exception handlers. */ void xPortSysTickHandler(void); /* * Start first task is a separate function so it can be tested in isolation. */ extern void prvPortStartFirstTask(void) __attribute__((naked)); /* * Used to catch tasks that attempt to return from their implementing function. */ static void prvTaskExitError(void); #define xPortSysTickHandler eclic_mtip_handler /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting variable. */ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; /* * Record the real MTH calculated by the configMAX_SYSCALL_INTERRUPT_PRIORITY * The configMAX_SYSCALL_INTERRUPT_PRIORITY is not the left-aligned level value, * See equations below: * Level Bits number: lvlbits = min(nlbits, CLICINTCTLBITS) * Left align Bits number: lfabits = 8-lvlbits * 0 < configMAX_SYSCALL_INTERRUPT_PRIORITY <= (2^lvlbits-1) * uxMaxSysCallMTH = (configMAX_SYSCALL_INTERRUPT_PRIORITY << lfabits) | ((2^lfabits)-1) * If nlbits = 3, CLICINTCTLBITS=3, then lvlbits = 3, lfabits = 5 * Set configMAX_SYSCALL_INTERRUPT_PRIORITY to 6 * Then uxMaxSysCallMTH = (6<<5) | (2^5 - 1) = 223 * * See function prvCheckMaxSysCallPrio and prvCalcMaxSysCallMTH */ uint8_t uxMaxSysCallMTH = 255; /* * The number of SysTick increments that make up one tick period. */ #if (configUSE_TICKLESS_IDLE == 1) static TickType_t ulTimerCountsForOneTick = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * The maximum number of tick periods that can be suppressed is limited by the * 24 bit resolution of the SysTick timer. */ #if (configUSE_TICKLESS_IDLE == 1) static TickType_t xMaximumPossibleSuppressedTicks = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Compensate for the CPU cycles that pass while the SysTick is stopped (low * power functionality only. */ #if (configUSE_TICKLESS_IDLE == 1) static TickType_t ulStoppedTimerCompensation = 0; #endif /* configUSE_TICKLESS_IDLE */ /* * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ #if (configASSERT_DEFINED == 1) static uint8_t ucMaxSysCallPriority = 0; #endif /* configASSERT_DEFINED */ /*-----------------------------------------------------------*/ /* * See header file for description. * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in * a1, and pvParameters in a2. The new top of stack is passed out in a0. * * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). * * Register ABI Name Description Saver * x0 zero Hard-wired zero - * x1 ra Return address Caller * x2 sp Stack pointer Callee * x3 gp Global pointer - * x4 tp Thread pointer - * x5-7 t0-2 Temporaries Caller * x8 s0/fp Saved register/Frame pointer Callee * x9 s1 Saved register Callee * x10-11 a0-1 Function Arguments/return values Caller * x12-17 a2-7 Function arguments Caller * x18-27 s2-11 Saved registers Callee * x28-31 t3-6 Temporaries Caller * * The RISC-V context is saved RTOS tasks in the following stack frame, * where the global and thread pointers are currently assumed to be constant so * are not saved: * * mstatus * #ifndef __riscv_32e * x31 * x30 * x29 * x28 * x27 * x26 * x25 * x24 * x23 * x22 * x21 * x20 * x19 * x18 * x17 * x16 * #endif * x15 * x14 * x13 * x12 * x11 * pvParameters * x9 * x8 * x7 * x6 * x5 * portTASK_RETURN_ADDRESS * pxCode */ StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) { /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; *pxTopOfStack = portINITIAL_MSTATUS; /* MSTATUS */ /* Save code space by skipping register initialisation. */ #ifndef __riscv_32e pxTopOfStack -= 22; /* X11 - X31. */ #else pxTopOfStack -= 6; /* X11 - X15. */ #endif *pxTopOfStack = (StackType_t)pvParameters; /* X10/A0 */ pxTopOfStack -= 6; /* X5 - X9 */ *pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* RA, X1 */ pxTopOfStack--; *pxTopOfStack = ((StackType_t)pxCode); /* PC */ return pxTopOfStack; } /*-----------------------------------------------------------*/ static void prvTaskExitError(void) { volatile uint32_t ulDummy = 0; /* A function that implements a task must not exit or attempt to return to its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT(uxCriticalNesting == ~0UL); portDISABLE_INTERRUPTS(); while (ulDummy == 0) { /* This file calls prvTaskExitError() after the scheduler has been started to remove a compiler warning about the function being defined but never called. ulDummy is used purely to quieten other warnings about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ /* Sleep and wait for interrupt */ __WFI(); } } /*-----------------------------------------------------------*/ static uint8_t prvCheckMaxSysCallPrio(uint8_t max_syscall_prio) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = __ECLIC_INTCTLBITS; uint8_t lvlbits, temp; if (nlbits <= intctlbits) { lvlbits = nlbits; } else { lvlbits = intctlbits; } temp = ((1 << lvlbits) - 1); if (max_syscall_prio > temp) { max_syscall_prio = temp; } return max_syscall_prio; } static uint8_t prvCalcMaxSysCallMTH(uint8_t max_syscall_prio) { uint8_t nlbits = __ECLIC_GetCfgNlbits(); uint8_t intctlbits = __ECLIC_INTCTLBITS; uint8_t lvlbits, lfabits; uint8_t maxsyscallmth = 0; uint8_t temp; if (nlbits <= intctlbits) { lvlbits = nlbits; } else { lvlbits = intctlbits; } lfabits = 8 - lvlbits; temp = ((1 << lvlbits) - 1); if (max_syscall_prio > temp) { max_syscall_prio = temp; } maxsyscallmth = (max_syscall_prio << lfabits) | ((1 << lfabits) - 1); return maxsyscallmth; } /* * See header file for description. */ BaseType_t xPortStartScheduler(void) { /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. */ configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY); /* Get the real MTH should be set to ECLIC MTH register */ uxMaxSysCallMTH = prvCalcMaxSysCallMTH(configMAX_SYSCALL_INTERRUPT_PRIORITY); FREERTOS_PORT_DEBUG("Max SysCall MTH is set to 0x%x\n", uxMaxSysCallMTH); #if (configASSERT_DEFINED == 1) { /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = prvCheckMaxSysCallPrio(configMAX_SYSCALL_INTERRUPT_PRIORITY); FREERTOS_PORT_DEBUG("Max SysCall Priority is set to %d\n", ucMaxSysCallPriority); } #endif /* conifgASSERT_DEFINED */ __disable_irq(); /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; /* Start the first task. */ prvPortStartFirstTask(); /* Should never get here as the tasks will now be executing! Call the task exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); prvTaskExitError(); /* Should not get here! */ return 0; } /*-----------------------------------------------------------*/ void vPortEndScheduler(void) { /* Not implemented in ports where there is nothing to return to. Artificially force an assert. */ configASSERT(uxCriticalNesting == 1000UL); } /*-----------------------------------------------------------*/ void vPortEnterCritical(void) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if (uxCriticalNesting == 1) { configASSERT((__ECLIC_GetMth() & portMTH_MASK) == uxMaxSysCallMTH); } } /*-----------------------------------------------------------*/ void vPortExitCritical(void) { configASSERT(uxCriticalNesting); uxCriticalNesting--; if (uxCriticalNesting == 0) { portENABLE_INTERRUPTS(); } } /*-----------------------------------------------------------*/ void vPortAssert(int32_t x) { TaskHandle_t th; if ((x) == 0) { taskDISABLE_INTERRUPTS(); #if (INCLUDE_xTaskGetCurrentTaskHandle == 1) th = xTaskGetCurrentTaskHandle(); if (th) { printf("Assert in task %s\n", pcTaskGetName(th)); } #endif while (1) { /* Sleep and wait for interrupt */ __WFI(); }; } } /*-----------------------------------------------------------*/ void xPortTaskSwitch(void) { portDISABLE_INTERRUPTS(); /* Clear Software IRQ, A MUST */ SysTimer_ClearSWIRQ(); vTaskSwitchContext(); portENABLE_INTERRUPTS(); } /*-----------------------------------------------------------*/ void xPortSysTickHandler(void) { /* The SysTick runs at the lowest interrupt priority, so when this interrupt executes all interrupts must be unmasked. There is therefore no need to save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { SysTick_Reload(SYSTICK_TICK_CONST); /* Increment the RTOS tick. */ if (xTaskIncrementTick() != pdFALSE) { /* A context switch is required. Context switching is performed in the SWI interrupt. Pend the SWI interrupt. */ portYIELD(); } } portENABLE_INTERRUPTS(); } /*-----------------------------------------------------------*/ #if (configUSE_TICKLESS_IDLE == 1) __attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; volatile TickType_t xModifiableIdleTime, xTickCountBeforeSleep, XLastLoadValue; FREERTOS_PORT_DEBUG("Enter TickLess %d\n", (uint32_t)xExpectedIdleTime); /* Make sure the SysTick reload value does not overflow the counter. */ if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) { xExpectedIdleTime = xMaximumPossibleSuppressedTicks; } /* Stop the SysTick momentarily. The time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time. */ SysTimer_Stop(); /* Calculate the reload value required to wait xExpectedIdleTime tick periods. -1 is used because this code will execute part way through one of the tick periods. */ ulReloadValue = (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL)); if (ulReloadValue > ulStoppedTimerCompensation) { ulReloadValue -= ulStoppedTimerCompensation; } /* Enter a critical section but don't use the taskENTER_CRITICAL() method as that will mask interrupts that should exit sleep mode. */ __disable_irq(); /* If a context switch is pending or a task is waiting for the scheduler to be unsuspended then abandon the low power entry. */ if (eTaskConfirmSleepModeStatus() == eAbortSleep) { /* Restart from whatever is left in the count register to complete this tick period. */ /* Restart SysTick. */ SysTimer_Start(); /* Reset the reload register to the value required for normal tick periods. */ SysTick_Reload(ulTimerCountsForOneTick); /* Re-enable interrupts - see comments above the cpsid instruction() above. */ __enable_irq(); } else { xTickCountBeforeSleep = xTaskGetTickCount(); /* Set the new reload value. */ SysTick_Reload(ulReloadValue); /* Get System timer load value before sleep */ XLastLoadValue = SysTimer_GetLoadValue(); /* Restart SysTick. */ SysTimer_Start(); ECLIC_EnableIRQ(SysTimer_IRQn); __RWMB(); /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can set its parameter to 0 to indicate that its implementation contains its own wait for interrupt or wait for event instruction, and so wfi should not be executed again. However, the original expected idle time variable must remain unmodified, so a copy is taken. */ xModifiableIdleTime = xExpectedIdleTime; configPRE_SLEEP_PROCESSING(xModifiableIdleTime); if (xModifiableIdleTime > 0) { __WFI(); } configPOST_SLEEP_PROCESSING(xExpectedIdleTime); /* Re-enable interrupts to allow the interrupt that brought the MCU out of sleep mode to execute immediately. */ __enable_irq(); /* Make sure interrupt enable is executed */ __RWMB(); __FENCE_I(); __NOP(); /* Disable interrupts again because the clock is about to be stopped and interrupts that execute while the clock is stopped will increase any slippage between the time maintained by the RTOS and calendar time. */ __disable_irq(); /* Disable the SysTick clock. Again, the time the SysTick is stopped for is accounted for as best it can be, but using the tickless mode will inevitably result in some tiny drift of the time maintained by the kernel with respect to calendar time*/ ECLIC_DisableIRQ(SysTimer_IRQn); /* Determine if SysTimer Interrupt is not yet happened, (in which case an interrupt other than the SysTick must have brought the system out of sleep mode). */ if (SysTimer_GetLoadValue() >= (XLastLoadValue + ulReloadValue)) { /* As the pending tick will be processed as soon as this function exits, the tick value maintained by the tick is stepped forward by one less than the time spent waiting. */ ulCompleteTickPeriods = xExpectedIdleTime - 1UL; FREERTOS_PORT_DEBUG("TickLess - SysTimer Interrupt Entered!\n"); } else { /* Something other than the tick interrupt ended the sleep. Work out how long the sleep lasted rounded to complete tick periods (not the ulReload value which accounted for part ticks). */ xModifiableIdleTime = SysTimer_GetLoadValue(); if (xModifiableIdleTime > XLastLoadValue) { ulCompletedSysTickDecrements = (xModifiableIdleTime - XLastLoadValue); } else { ulCompletedSysTickDecrements = (xModifiableIdleTime + portMAX_BIT_NUMBER - XLastLoadValue); } /* How many complete tick periods passed while the processor was waiting? */ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; /* The reload value is set to whatever fraction of a single tick period remains. */ SysTick_Reload(ulTimerCountsForOneTick); FREERTOS_PORT_DEBUG("TickLess - External Interrupt Happened!\n"); } FREERTOS_PORT_DEBUG("End TickLess %d\n", (uint32_t)ulCompleteTickPeriods); /* Restart SysTick */ vTaskStepTick(ulCompleteTickPeriods); /* Exit with interrupts enabled. */ ECLIC_EnableIRQ(SysTimer_IRQn); __enable_irq(); } } #endif /* #if configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__((weak)) void vPortSetupTimerInterrupt(void) { /* Calculate the constants required to configure the tick interrupt. */ #if (configUSE_TICKLESS_IDLE == 1) { ulTimerCountsForOneTick = (SYSTICK_TICK_CONST); xMaximumPossibleSuppressedTicks = portMAX_BIT_NUMBER / ulTimerCountsForOneTick; ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ); FREERTOS_PORT_DEBUG("CountsForOneTick, SuppressedTicks and TimerCompensation: %u, %u, %u\n", (uint32_t)ulTimerCountsForOneTick, (uint32_t)xMaximumPossibleSuppressedTicks, (uint32_t)ulStoppedTimerCompensation); } #endif /* configUSE_TICKLESS_IDLE */ TickType_t ticks = SYSTICK_TICK_CONST; /* Make SWI and SysTick the lowest priority interrupts. */ /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */ SysTick_Config(ticks); ECLIC_DisableIRQ(SysTimer_IRQn); ECLIC_SetLevelIRQ(SysTimer_IRQn, configKERNEL_INTERRUPT_PRIORITY); ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); ECLIC_EnableIRQ(SysTimer_IRQn); /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */ ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT); ECLIC_SetLevelIRQ(SysTimerSW_IRQn, configKERNEL_INTERRUPT_PRIORITY); ECLIC_EnableIRQ(SysTimerSW_IRQn); } /*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/ #if (configASSERT_DEFINED == 1) void vPortValidateInterruptPriority(void) { uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ CSR_MCAUSE_Type mcause = (CSR_MCAUSE_Type)__RV_CSR_READ(CSR_MCAUSE); /* Make sure current trap type is interrupt */ configASSERT(mcause.b.interrupt == 1); if (mcause.b.interrupt) { ulCurrentInterrupt = mcause.b.exccode; /* Is the interrupt number a user defined interrupt? */ if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) { /* Look up the interrupt's priority. */ ucCurrentPriority = __ECLIC_GetLevelIRQ(ulCurrentInterrupt); /* The following assertion will fail if a service routine (ISR) for an interrupt that has been assigned a priority above ucMaxSysCallPriority calls an ISR safe FreeRTOS API function. ISR safe FreeRTOS API functions must *only* be called from interrupts that have been assigned a priority at or below ucMaxSysCallPriority. Numerically low interrupt priority numbers represent logically high interrupt priorities, therefore the priority of the interrupt must be set to a value equal to or numerically *higher* than ucMaxSysCallPriority. Interrupts that use the FreeRTOS API must not be left at their default priority of zero as that is the highest possible priority, which is guaranteed to be above ucMaxSysCallPriority, and therefore also guaranteed to be invalid. FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/FAQHelp.html */ configASSERT(ucCurrentPriority <= ucMaxSysCallPriority); } } } #endif /* configASSERT_DEFINED */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portasm.S ================================================ /* * FreeRTOS Kernel V10.2.1 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ #include "riscv_encoding.h" #ifndef __riscv_32e #define portRegNum 30 #else #define portRegNum 14 #endif #define portCONTEXT_SIZE ( portRegNum * REGBYTES ) .section .text.entry .align 8 .extern xPortTaskSwitch .extern pxCurrentTCB .global prvPortStartFirstTask /** * \brief Global interrupt disabled * \details * This function disable global interrupt. * \remarks * - All the interrupt requests will be ignored by CPU. */ .macro DISABLE_MIE csrc CSR_MSTATUS, MSTATUS_MIE .endm /** * \brief Macro for context save * \details * This macro save ABI defined caller saved registers in the stack. * \remarks * - This Macro could use to save context when you enter to interrupt * or exception */ /* Save caller registers */ .macro SAVE_CONTEXT csrrw sp, CSR_MSCRATCHCSWL, sp /* Allocate stack space for context saving */ #ifndef __riscv_32e addi sp, sp, -20*REGBYTES #else addi sp, sp, -14*REGBYTES #endif /* __riscv_32e */ STORE x1, 0*REGBYTES(sp) STORE x4, 1*REGBYTES(sp) STORE x5, 2*REGBYTES(sp) STORE x6, 3*REGBYTES(sp) STORE x7, 4*REGBYTES(sp) STORE x10, 5*REGBYTES(sp) STORE x11, 6*REGBYTES(sp) STORE x12, 7*REGBYTES(sp) STORE x13, 8*REGBYTES(sp) STORE x14, 9*REGBYTES(sp) STORE x15, 10*REGBYTES(sp) #ifndef __riscv_32e STORE x16, 14*REGBYTES(sp) STORE x17, 15*REGBYTES(sp) STORE x28, 16*REGBYTES(sp) STORE x29, 17*REGBYTES(sp) STORE x30, 18*REGBYTES(sp) STORE x31, 19*REGBYTES(sp) #endif /* __riscv_32e */ .endm /** * \brief Macro for restore caller registers * \details * This macro restore ABI defined caller saved registers from stack. * \remarks * - You could use this macro to restore context before you want return * from interrupt or exeception */ /* Restore caller registers */ .macro RESTORE_CONTEXT LOAD x1, 0*REGBYTES(sp) LOAD x4, 1*REGBYTES(sp) LOAD x5, 2*REGBYTES(sp) LOAD x6, 3*REGBYTES(sp) LOAD x7, 4*REGBYTES(sp) LOAD x10, 5*REGBYTES(sp) LOAD x11, 6*REGBYTES(sp) LOAD x12, 7*REGBYTES(sp) LOAD x13, 8*REGBYTES(sp) LOAD x14, 9*REGBYTES(sp) LOAD x15, 10*REGBYTES(sp) #ifndef __riscv_32e LOAD x16, 14*REGBYTES(sp) LOAD x17, 15*REGBYTES(sp) LOAD x28, 16*REGBYTES(sp) LOAD x29, 17*REGBYTES(sp) LOAD x30, 18*REGBYTES(sp) LOAD x31, 19*REGBYTES(sp) /* De-allocate the stack space */ addi sp, sp, 20*REGBYTES #else /* De-allocate the stack space */ addi sp, sp, 14*REGBYTES #endif /* __riscv_32e */ csrrw sp, CSR_MSCRATCHCSWL, sp .endm /** * \brief Macro for save necessary CSRs to stack * \details * This macro store MCAUSE, MEPC, MSUBM to stack. */ .macro SAVE_CSR_CONTEXT /* Store CSR mcause to stack using pushmcause */ csrrwi x0, CSR_PUSHMCAUSE, 11 /* Store CSR mepc to stack using pushmepc */ csrrwi x0, CSR_PUSHMEPC, 12 /* Store CSR msub to stack using pushmsub */ csrrwi x0, CSR_PUSHMSUBM, 13 .endm /** * \brief Macro for restore necessary CSRs from stack * \details * This macro restore MSUBM, MEPC, MCAUSE from stack. */ .macro RESTORE_CSR_CONTEXT LOAD x5, 13*REGBYTES(sp) csrw CSR_MSUBM, x5 LOAD x5, 12*REGBYTES(sp) csrw CSR_MEPC, x5 LOAD x5, 11*REGBYTES(sp) csrw CSR_MCAUSE, x5 .endm /** * \brief Exception/NMI Entry * \details * This function provide common entry functions for exception/nmi. * \remarks * This function provide a default exception/nmi entry. * ABI defined caller save register and some CSR registers * to be saved before enter interrupt handler and be restored before return. */ .section .text.trap /* In CLIC mode, the exeception entry must be 64bytes aligned */ .align 6 .global exc_entry exc_entry: /* Save the caller saving registers (context) */ SAVE_CONTEXT /* Save the necessary CSR registers */ SAVE_CSR_CONTEXT /* * Set the exception handler function arguments * argument 1: mcause value * argument 2: current stack point(SP) value */ csrr a0, mcause mv a1, sp /* * TODO: Call the exception handler function * By default, the function template is provided in * system_Device.c, you can adjust it as you want */ call core_exception_handler /* Restore the necessary CSR registers */ RESTORE_CSR_CONTEXT /* Restore the caller saving registers (context) */ RESTORE_CONTEXT /* Return to regular code */ mret /** * \brief Non-Vector Interrupt Entry * \details * This function provide common entry functions for handling * non-vector interrupts * \remarks * This function provide a default non-vector interrupt entry. * ABI defined caller save register and some CSR registers need * to be saved before enter interrupt handler and be restored before return. */ .section .text.irq /* In CLIC mode, the interrupt entry must be 4bytes aligned */ .align 2 .global irq_entry /* This label will be set to MTVT2 register */ irq_entry: /* Save the caller saving registers (context) */ SAVE_CONTEXT /* Save the necessary CSR registers */ SAVE_CSR_CONTEXT /* This special CSR read/write operation, which is actually * claim the CLIC to find its pending highest ID, if the ID * is not 0, then automatically enable the mstatus.MIE, and * jump to its vector-entry-label, and update the link register */ csrrw ra, CSR_JALMNXTI, ra /* Critical section with interrupts disabled */ DISABLE_MIE /* Restore the necessary CSR registers */ RESTORE_CSR_CONTEXT /* Restore the caller saving registers (context) */ RESTORE_CONTEXT /* Return to regular code */ mret /* Default Handler for Exceptions / Interrupts */ .global default_intexc_handler Undef_Handler: default_intexc_handler: 1: j 1b /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the stack for lazy saving of FPU registers. */ .align 3 prvPortStartFirstTask: /* Setup Interrupt Stack using The stack that was used by main() before the scheduler is started is no longer required after the scheduler is started. Interrupt stack pointer is stored in CSR_MSCRATCH */ la t0, _sp csrw CSR_MSCRATCH, t0 LOAD sp, pxCurrentTCB /* Load pxCurrentTCB. */ LOAD sp, 0x0(sp) /* Read sp from first TCB member */ /* Pop PC from stack and set MEPC */ LOAD t0, 0 * REGBYTES(sp) csrw CSR_MEPC, t0 /* Pop mstatus from stack and set it */ LOAD t0, (portRegNum - 1) * REGBYTES(sp) csrw CSR_MSTATUS, t0 /* Interrupt still disable here */ /* Restore Registers from Stack */ LOAD x1, 1 * REGBYTES(sp) /* RA */ LOAD x5, 2 * REGBYTES(sp) LOAD x6, 3 * REGBYTES(sp) LOAD x7, 4 * REGBYTES(sp) LOAD x8, 5 * REGBYTES(sp) LOAD x9, 6 * REGBYTES(sp) LOAD x10, 7 * REGBYTES(sp) LOAD x11, 8 * REGBYTES(sp) LOAD x12, 9 * REGBYTES(sp) LOAD x13, 10 * REGBYTES(sp) LOAD x14, 11 * REGBYTES(sp) LOAD x15, 12 * REGBYTES(sp) #ifndef __riscv_32e LOAD x16, 13 * REGBYTES(sp) LOAD x17, 14 * REGBYTES(sp) LOAD x18, 15 * REGBYTES(sp) LOAD x19, 16 * REGBYTES(sp) LOAD x20, 17 * REGBYTES(sp) LOAD x21, 18 * REGBYTES(sp) LOAD x22, 19 * REGBYTES(sp) LOAD x23, 20 * REGBYTES(sp) LOAD x24, 21 * REGBYTES(sp) LOAD x25, 22 * REGBYTES(sp) LOAD x26, 23 * REGBYTES(sp) LOAD x27, 24 * REGBYTES(sp) LOAD x28, 25 * REGBYTES(sp) LOAD x29, 26 * REGBYTES(sp) LOAD x30, 27 * REGBYTES(sp) LOAD x31, 28 * REGBYTES(sp) #endif addi sp, sp, portCONTEXT_SIZE mret .align 2 .global eclic_msip_handler eclic_msip_handler: addi sp, sp, -portCONTEXT_SIZE STORE x1, 1 * REGBYTES(sp) /* RA */ STORE x5, 2 * REGBYTES(sp) STORE x6, 3 * REGBYTES(sp) STORE x7, 4 * REGBYTES(sp) STORE x8, 5 * REGBYTES(sp) STORE x9, 6 * REGBYTES(sp) STORE x10, 7 * REGBYTES(sp) STORE x11, 8 * REGBYTES(sp) STORE x12, 9 * REGBYTES(sp) STORE x13, 10 * REGBYTES(sp) STORE x14, 11 * REGBYTES(sp) STORE x15, 12 * REGBYTES(sp) #ifndef __riscv_32e STORE x16, 13 * REGBYTES(sp) STORE x17, 14 * REGBYTES(sp) STORE x18, 15 * REGBYTES(sp) STORE x19, 16 * REGBYTES(sp) STORE x20, 17 * REGBYTES(sp) STORE x21, 18 * REGBYTES(sp) STORE x22, 19 * REGBYTES(sp) STORE x23, 20 * REGBYTES(sp) STORE x24, 21 * REGBYTES(sp) STORE x25, 22 * REGBYTES(sp) STORE x26, 23 * REGBYTES(sp) STORE x27, 24 * REGBYTES(sp) STORE x28, 25 * REGBYTES(sp) STORE x29, 26 * REGBYTES(sp) STORE x30, 27 * REGBYTES(sp) STORE x31, 28 * REGBYTES(sp) #endif /* Push mstatus to stack */ csrr t0, CSR_MSTATUS STORE t0, (portRegNum - 1) * REGBYTES(sp) /* Push additional registers */ /* Store sp to task stack */ LOAD t0, pxCurrentTCB STORE sp, 0(t0) csrr t0, CSR_MEPC STORE t0, 0(sp) jal xPortTaskSwitch /* Switch task context */ LOAD t0, pxCurrentTCB /* Load pxCurrentTCB. */ LOAD sp, 0x0(t0) /* Read sp from first TCB member */ /* Pop PC from stack and set MEPC */ LOAD t0, 0 * REGBYTES(sp) csrw CSR_MEPC, t0 /* Pop additional registers */ /* Pop mstatus from stack and set it */ LOAD t0, (portRegNum - 1) * REGBYTES(sp) csrw CSR_MSTATUS, t0 /* Interrupt still disable here */ /* Restore Registers from Stack */ LOAD x1, 1 * REGBYTES(sp) /* RA */ LOAD x5, 2 * REGBYTES(sp) LOAD x6, 3 * REGBYTES(sp) LOAD x7, 4 * REGBYTES(sp) LOAD x8, 5 * REGBYTES(sp) LOAD x9, 6 * REGBYTES(sp) LOAD x10, 7 * REGBYTES(sp) LOAD x11, 8 * REGBYTES(sp) LOAD x12, 9 * REGBYTES(sp) LOAD x13, 10 * REGBYTES(sp) LOAD x14, 11 * REGBYTES(sp) LOAD x15, 12 * REGBYTES(sp) #ifndef __riscv_32e LOAD x16, 13 * REGBYTES(sp) LOAD x17, 14 * REGBYTES(sp) LOAD x18, 15 * REGBYTES(sp) LOAD x19, 16 * REGBYTES(sp) LOAD x20, 17 * REGBYTES(sp) LOAD x21, 18 * REGBYTES(sp) LOAD x22, 19 * REGBYTES(sp) LOAD x23, 20 * REGBYTES(sp) LOAD x24, 21 * REGBYTES(sp) LOAD x25, 22 * REGBYTES(sp) LOAD x26, 23 * REGBYTES(sp) LOAD x27, 24 * REGBYTES(sp) LOAD x28, 25 * REGBYTES(sp) LOAD x29, 26 * REGBYTES(sp) LOAD x30, 27 * REGBYTES(sp) LOAD x31, 28 * REGBYTES(sp) #endif addi sp, sp, portCONTEXT_SIZE mret ================================================ FILE: source/Core/BSP/Pinecil/Vendor/OS/FreeRTOS/Source/portable/GCC/portmacro.h ================================================ /* * FreeRTOS Kernel V10.2.1 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * http://www.FreeRTOS.org * http://aws.amazon.com/freertos * * 1 tab == 4 spaces! */ #ifndef PORTMACRO_H #define PORTMACRO_H #ifdef __cplusplus extern "C" { #endif #include "nuclei_sdk_soc.h" /*----------------------------------------------------------- * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. * * These settings should not be altered. *----------------------------------------------------------- */ /* Type definitions. */ #define portCHAR char #define portFLOAT float #define portDOUBLE double #define portLONG long #define portSHORT short #define portSTACK_TYPE unsigned long #define portBASE_TYPE long #define portPOINTER_SIZE_TYPE unsigned long typedef portSTACK_TYPE StackType_t; typedef long BaseType_t; typedef unsigned long UBaseType_t; /* RISC-V TIMER is 64-bit long */ typedef uint64_t TickType_t; #define portMAX_DELAY (TickType_t)0xFFFFFFFFFFFFFFFFULL /*-----------------------------------------------------------*/ /* Architecture specifics. */ #define portSTACK_GROWTH (-1) #define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ) #define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Scheduler utilities. */ #define portYIELD() \ { \ /* Set a software interrupt(SWI) request to request a context switch. */ \ SysTimer_SetSWIRQ(); \ /* Barriers are normally not required but do ensure the code is completely \ within the specified behaviour for the architecture. */ \ __RWMB(); \ } #define portEND_SWITCHING_ISR(xSwitchRequired) \ if (xSwitchRequired != pdFALSE) \ portYIELD() #define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x) /*-----------------------------------------------------------*/ /* Critical section management. */ extern void vPortEnterCritical(void); extern void vPortExitCritical(void); #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() #define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are not necessary for to use this port. They are defined so the common demo files (which build with all the ports) will build. */ #define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) #define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ #ifndef portSUPPRESS_TICKS_AND_SLEEP extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime) #endif /*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/ #ifdef configASSERT extern void vPortValidateInterruptPriority(void); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* portNOP() is not required by this port. */ #define portNOP() __NOP() #define portINLINE __inline #ifndef portFORCE_INLINE #define portFORCE_INLINE inline __attribute__((always_inline)) #endif /* This variable should not be set in any of the FreeRTOS application only used internal of FreeRTOS Port code */ extern uint8_t uxMaxSysCallMTH; /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortRaiseBASEPRI(void) { ECLIC_SetMth(uxMaxSysCallMTH); __RWMB(); } /*-----------------------------------------------------------*/ portFORCE_INLINE static uint8_t ulPortRaiseBASEPRI(void) { uint8_t ulOriginalBASEPRI; ulOriginalBASEPRI = ECLIC_GetMth(); ECLIC_SetMth(uxMaxSysCallMTH); __RWMB(); /* This return might not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI(uint8_t ulNewMaskValue) { ECLIC_SetMth(ulNewMaskValue); __RWMB(); } /*-----------------------------------------------------------*/ #define portMEMORY_BARRIER() __asm volatile("" ::: "memory") #ifdef __cplusplus } #endif #endif /* PORTMACRO_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /****************************************************************************** * @file gcc_Device.ld * @brief GNU Linker Script for gd32vf103 based device * @version V1.0.0 * @date 17. Dec 2019 ******************************************************************************/ /*********** Use Configuration Wizard in Context Menu *************************/ OUTPUT_ARCH( "riscv" ) /********************* Flash Configuration ************************************ * Flash Configuration * Flash Base Address <0x0-0xFFFFFFFF:8> * Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> * */ __ROM_BASE = 0x08000000; __ROM_SIZE = 0x0001F400; /*--------------------- ILM RAM Configuration --------------------------- * ILM RAM Configuration * ILM RAM Base Address <0x0-0xFFFFFFFF:8> * ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> * */ __ILM_RAM_BASE = 0x80000000; __ILM_RAM_SIZE = 0x00010000; /*--------------------- Embedded RAM Configuration --------------------------- * RAM Configuration * RAM Base Address <0x0-0xFFFFFFFF:8> * RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> * */ __RAM_BASE = 0x20000000; __RAM_SIZE = 0x00006800; /********************* Stack / Heap Configuration **************************** * Stack / Heap Configuration * Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> * Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> * */ __STACK_SIZE = 0x00000800; __HEAP_SIZE = 0x00000800; /**************************** end of configuration section ********************/ /* Define base address and length of flash and ram */ MEMORY { flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH,ILM and RAM. * It references following symbols, which must be defined in code: * _Start : Entry of reset handler * * It defines following symbols, which code can use without definition: * _ilm_lma * _ilm * __etext * _etext * etext * _eilm * __preinit_array_start * __preinit_array_end * __init_array_start * __init_array_end * __fini_array_start * __fini_array_end * _data_lma * _edata * edata * __data_end__ * __bss_start * __fbss * _end * end * __heap_end * __StackLimit * __StackTop * __STACK_SIZE */ /* Define entry label of program */ ENTRY(_start) SECTIONS { __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K; .init : { /* vector table locate at flash */ *(.vtable) KEEP (*(SORT_NONE(.init))) } >flash AT>flash .ilalign : { . = ALIGN(4); /* Create a section label as _ilm_lma which located at flash */ PROVIDE( _ilm_lma = . ); } >flash AT>flash .ialign : { /* Create a section label as _ilm which located at flash */ PROVIDE( _ilm = . ); } >flash AT>flash /* Code section located at flash */ .text : { *(.text.unlikely .text.unlikely.*) *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) } >flash AT>flash .rodata : ALIGN(4) { . = ALIGN(4); *(.rdata) *(.rodata .rodata.*) /* section information for initial. */ . = ALIGN(4); __rt_init_start = .; KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; . = ALIGN(4); __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; *(.gnu.linkonce.r.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) } >flash AT>flash .fini : { KEEP (*(SORT_NONE(.fini))) } >flash AT>flash . = ALIGN(4); PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); PROVIDE( _eilm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >flash AT>flash .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >flash AT>flash .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >flash AT>flash .ctors : { /* gcc uses crtbegin.o to find the start of * the constructors, so we make sure it is * first. Because this is a wildcard, it * doesn't matter if the user does not * actually link against crtbegin.o; the * linker won't look for a file to match a * wildcard. The wildcard also means that it * doesn't matter which directory crtbegin.o * is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from * the crtend.o file until after the sorted ctors. * The .ctor section from the crtend file contains the * end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >flash AT>flash .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >flash AT>flash .lalign : { . = ALIGN(4); PROVIDE( _data_lma = . ); } >flash AT>flash .dalign : { . = ALIGN(4); PROVIDE( _data = . ); } >ram AT>flash /* Define data section virtual address is ram and physical address is flash */ .data : { *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.* .sdata*) *(.gnu.linkonce.s.*) } >ram AT>flash . = ALIGN(4); PROVIDE( _edata = . ); PROVIDE( edata = . ); PROVIDE( _fbss = . ); PROVIDE( __bss_start = . ); .bss : { *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); } >ram AT>ram . = ALIGN(8); PROVIDE( _end = . ); PROVIDE( end = . ); /* Define stack and head location at ram */ .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE : { PROVIDE( _heap_end = . ); . = __STACK_SIZE; PROVIDE( _sp = . ); } >ram AT>ram } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/openocd_gd32vf103.cfg ================================================ adapter_khz 100 reset_config srst_only adapter_nsrst_assert_width 100 interface cmsis-dap transport select jtag adapter_khz 100 autoexit true set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6d set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 20480 -work-area-backup 0 # Work-area is a space in RAM used for flash programming if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { set _WORKAREASIZE 0x5000 } # Allow overriding the Flash bank size if { [info exists FLASH_SIZE] } { set _FLASH_SIZE $FLASH_SIZE } else { # autodetect size set _FLASH_SIZE 0 } # flash size will be probed set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME # Expose Nuclei self-defined CSRS range 770-800,835-850,1984-2032,2064-2070 # See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306 # Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307) riscv expose_csrs 770-800,835-850,1984-2032,2064-2070 riscv set_reset_timeout_sec 1 init halt ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_core.h ================================================ /*! \file drv_usb_core.h \brief USB core low level driver header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USB_CORE_H #define __DRV_USB_CORE_H #include "drv_usb_regs.h" #include "usb_ch9_std.h" #define USB_FS_EP0_MAX_LEN 64U /* maximum packet size of EndPoint0 */ #define HC_MAX_PACKET_COUNT 140U /* maximum packet count */ #define EP_ID(x) ((uint8_t)((x)&0x7FU)) /* endpoint number */ #define EP_DIR(x) ((uint8_t)((x) >> 7)) /* endpoint direction */ enum _usb_eptype { USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ USB_EPTYPE_MASK = 3U, /*!< endpoint type mask */ }; typedef enum { USB_OTG_OK = 0, /*!< USB OTG status OK*/ USB_OTG_FAIL /*!< USB OTG status fail*/ } usb_otg_status; typedef enum { USB_OK = 0, /*!< USB status OK*/ USB_FAIL /*!< USB status fail*/ } usb_status; typedef enum { USB_USE_FIFO, /*!< USB use FIFO transfer mode */ USB_USE_DMA /*!< USB use DMA transfer mode */ } usb_transfer_mode; typedef struct { uint8_t core_enum; /*!< USB core type */ uint8_t core_speed; /*!< USB core speed */ uint8_t num_pipe; /*!< USB host channel numbers */ uint8_t num_ep; /*!< USB device endpoint numbers */ uint8_t transfer_mode; /*!< USB transfer mode */ uint8_t phy_itf; /*!< USB core PHY interface */ uint8_t sof_enable; /*!< USB SOF output */ uint8_t low_power; /*!< USB low power */ } usb_core_basic; /* function declarations */ /* config core capabilities */ usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); /*initializes the USB controller registers and prepares the core device mode or host mode operation*/ usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs); /* read a packet from the Rx FIFO associated with the endpoint */ void *usb_rxfifo_read(usb_core_regs *core_regs, uint8_t *dest_buf, uint16_t byte_count); /* write a packet into the Tx FIFO associated with the endpoint */ usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); /* flush a Tx FIFO or all Tx FIFOs */ usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num); /* flush the entire Rx FIFO */ usb_status usb_rxfifo_flush(usb_core_regs *usb_regs); /* get the global interrupts */ static inline uint32_t usb_coreintr_get(usb_core_regs *usb_regs) { return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; } #endif /* __DRV_USB_CORE_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_dev.h ================================================ /*! \file drv_usb_dev.h \brief USB device low level driver header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USB_DEV_H #define __DRV_USB_DEV_H #include "drv_usb_core.h" enum usb_ctl_status { USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ USB_CTL_DATA_IN, /*!< USB control transfer data in state */ USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ }; #define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ #define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ /* USB descriptor */ typedef struct _usb_desc { uint8_t *dev_desc; /*!< device descriptor */ uint8_t *config_desc; /*!< config descriptor */ uint8_t *bos_desc; /*!< BOS descriptor */ void *const *strings; /*!< string descriptor */ } usb_desc; /* USB power management */ typedef struct _usb_pm { uint8_t power_mode; /*!< power mode */ uint8_t power_low; /*!< power low */ uint8_t dev_remote_wakeup; /*!< remote wakeup */ uint8_t remote_wakeup_on; /*!< remote wakeup on */ } usb_pm; /* USB control information */ typedef struct _usb_control { usb_req req; /*!< USB standard device request */ uint8_t ctl_state; /*!< USB control transfer state */ uint8_t ctl_zlp; /*!< zero lenth package */ } usb_control; typedef struct { struct { uint8_t num : 4; /*!< the endpoint number.it can be from 0 to 6 */ uint8_t pad : 3; /*!< padding between number and direction */ uint8_t dir : 1; /*!< the endpoint direction */ } ep_addr; uint8_t ep_type; /*!< USB endpoint type */ uint8_t ep_stall; /*!< USB endpoint stall status */ uint8_t frame_num; /*!< number of frame */ uint16_t max_len; /*!< Maximum packet lenth */ /* transaction level variables */ uint8_t *xfer_buf; /*!< transmit buffer */ uint32_t xfer_len; /*!< transmit buffer length */ uint32_t xfer_count; /*!< transmit buffer count */ uint32_t remain_len; /*!< remain packet lenth */ uint32_t dma_addr; /*!< DMA address */ } usb_transc; typedef struct _usb_core_driver usb_dev; typedef struct _usb_class_core { uint8_t command; /*!< device class request command */ uint8_t alter_set; /*!< alternative set */ uint8_t (*init)(usb_dev *udev, uint8_t config_index); /*!< initialize handler */ uint8_t (*deinit)(usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ uint8_t (*req_proc)(usb_dev *udev, usb_req *req); /*!< device request handler */ uint8_t (*data_in)(usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ uint8_t (*data_out)(usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ uint8_t (*SOF)(usb_dev *udev); /*!< Start of frame handler */ uint8_t (*incomplete_isoc_in)(usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ } usb_class_core; typedef struct _usb_perp_dev { uint8_t config; /*!< configuration */ uint8_t dev_addr; /*!< device address */ __IO uint8_t cur_status; /*!< current status */ __IO uint8_t backup_status; /*!< backup status */ usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ usb_pm pm; /*!< power management */ usb_desc desc; /*!< USB descriptors */ usb_control control; /*!< USB control information */ usb_class_core *class_core; /*!< class driver */ } usb_perp_dev; typedef struct _usb_core_driver { usb_core_basic bp; /*!< USB basic parameters */ usb_core_regs regs; /*!< USB registers */ usb_perp_dev dev; /*!< USB peripheral device */ } usb_core_driver; /* function declarations */ /* initialize USB core registers for device mode */ usb_status usb_devcore_init(usb_core_driver *udev); /* enable the USB device mode interrupts */ usb_status usb_devint_enable(usb_core_driver *udev); /* active the usb transaction */ usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc); /* deactive the usb transaction */ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc); /* configure usb transaction to start IN transfer */ usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc); /* configure usb transaction to start OUT transfer */ usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc); /* set the usb transaction STALL status */ usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc); /* clear the usb transaction STALL status */ usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc); /* read device all OUT endpoint interrupt register */ uint32_t usb_oepintnum_read(usb_core_driver *udev); /* read device OUT endpoint interrupt flag register */ uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num); /* read device all IN endpoint interrupt register */ uint32_t usb_iepintnum_read(usb_core_driver *udev); /* read device IN endpoint interrupt flag register */ uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num); /* config the USB device to be disconnected */ void usb_dev_disconnect(usb_core_driver *udev); /* config the USB device to be connected */ void usb_dev_connect(usb_core_driver *udev); /* set the USB device address */ void usb_devaddr_set(usb_core_driver *pudev, uint8_t dev_addr); /* configures OUT endpoint 0 to receive SETUP packets */ void usb_ctlep_startout(usb_core_driver *udev); /* active remote wakeup signalling */ void usb_rwkup_active(usb_core_driver *udev); /* reset remote wakeup signalling */ void usb_rwkup_reset(usb_core_driver *udev); /* set remote wakeup signalling */ void usb_rwkup_set(usb_core_driver *udev); /* active USB core clock */ void usb_clock_active(usb_core_driver *udev); /* usb device suspend */ void usb_dev_suspend(usb_core_driver *udev); /* stop the device and clean up fifos */ void usb_dev_stop(usb_core_driver *udev); #endif /* __DRV_USB_DEV_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_host.h ================================================ /*! \file drv_usb_host.h \brief USB host mode low level driver header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USB_HOST_H #define __DRV_USB_HOST_H #include "drv_usb_core.h" #include "drv_usb_regs.h" #include "usb_ch9_std.h" typedef enum _usb_pipe_status { PIPE_IDLE = 0U, PIPE_XF, PIPE_HALTED, PIPE_NAK, PIPE_NYET, PIPE_STALL, PIPE_TRACERR, PIPE_BBERR, PIPE_REQOVR, PIPE_DTGERR, } usb_pipe_staus; typedef enum _usb_pipe_mode { PIPE_PERIOD = 0U, PIPE_NON_PERIOD = 1U } usb_pipe_mode; typedef enum _usb_urb_state { URB_IDLE = 0U, URB_DONE, URB_NOTREADY, URB_ERROR, URB_STALL } usb_urb_state; typedef struct _usb_pipe { uint8_t in_used; uint8_t dev_addr; uint32_t dev_speed; struct { uint8_t num; uint8_t dir; uint8_t type; uint16_t mps; } ep; uint8_t ping; uint32_t DPID; uint8_t *xfer_buf; uint32_t xfer_len; uint32_t xfer_count; uint8_t data_toggle_in; uint8_t data_toggle_out; __IO uint32_t err_count; __IO usb_pipe_staus pp_status; __IO usb_urb_state urb_state; } usb_pipe; typedef struct _usb_host_drv { uint8_t rx_buf[512U]; __IO uint32_t connect_status; __IO uint32_t port_enabled; __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; usb_pipe pipe[USBFS_MAX_TX_FIFOS]; } usb_host_drv; typedef struct _usb_core_driver { usb_core_basic bp; usb_core_regs regs; usb_host_drv host; } usb_core_driver; /* initializes USB core for host mode */ usb_status usb_host_init(usb_core_driver *pudev); /* initialize host pipe */ usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num); /* prepare host pipe for transferring packets */ usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num); /* halt host pipe */ usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num); /* configure host pipe to do ping operation */ usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num); /* reset host port */ uint32_t usb_port_reset(usb_core_driver *pudev); /* control the VBUS to power */ void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state); /* stop the USB host and clean up FIFO */ void usb_host_stop(usb_core_driver *pudev); //__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev) uint32_t usb_frame_even(usb_core_driver *pudev); //{ // return !(pudev->regs.hr->HFINFR & 0x01U); //} //__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) void usb_phyclock_config(usb_core_driver *pudev, uint8_t clock); //{ // pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; // pudev->regs.hr->HCTL |= clock; //} uint32_t usb_port_read(usb_core_driver *pudev); // inline uint32_t usb_port_read (usb_core_driver *pudev) //{ // return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); //} uint32_t usb_curspeed_get(usb_core_driver *pudev); // inline uint32_t usb_curspeed_get (usb_core_driver *pudev) //{ // return *pudev->regs.HPCS & HPCS_PS; //} //__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *pudev) uint32_t usb_curframe_get(usb_core_driver *pudev); //{ // return (pudev->regs.hr->HFINFR & 0xFFFFU); //} #endif /* __DRV_USB_HOST_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_hw.h ================================================ /*! \file drv_usb_hw.h \brief usb hardware configuration header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USB_HW_H #define __DRV_USB_HW_H #include "usb_conf.h" /* configure USB clock */ void usb_rcu_config(void); /* configure USB interrupt */ void usb_intr_config(void); /* initializes delay unit using Timer2 */ void usb_timer_init(void); /* delay in micro seconds */ void usb_udelay(const uint32_t usec); /* delay in milli seconds */ void usb_mdelay(const uint32_t msec); // Functions for USE_HOST_MODE /* configure USB VBus */ void usb_vbus_config(void); /* drive usb VBus */ void usb_vbus_drive(uint8_t State); #endif /* __DRV_USB_HW_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usb_regs.h ================================================ /*! \file drv_usb_regs.h \brief USB cell registers definition and handle macros \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USB_REGS_H #define __DRV_USB_REGS_H #include "usb_conf.h" #define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ #define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ #define USBFS_MAX_TX_FIFOS 15 /*!< FIFO number */ #define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ #define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ #define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ #define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ #define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ #define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ #define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ #define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ #define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ #define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ typedef enum { USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ } usb_core_enum; enum usb_reg_offset { USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ USB_REG_OFFSET_EP = 0x0020U, USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ USB_REG_OFFSET_CH = 0x0020U, USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ }; typedef struct { __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ uint32_t Reserved30[2]; /*!< Reserved 030h */ __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ __IO uint32_t CID; /*!< USB core ID register 03Ch */ uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ } usb_gr; typedef struct { __IO uint32_t HCTL; /*!< USB host control register 400h */ __IO uint32_t HFT; /*!< USB host frame interval register 404h */ __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ uint32_t Reserved40C; /*!< Reserved 40Ch */ __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ } usb_hr; typedef struct { __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ uint32_t Reserved[2]; } usb_pr; typedef struct { __IO uint32_t DCFG; /*!< USB device configuration register 800h */ __IO uint32_t DCTL; /*!< USB device control register 804h */ __IO uint32_t DSTAT; /*!< USB device status register 808h */ uint32_t Reserved0C; /*!< Reserved 80Ch */ __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ uint32_t Reserved20; /*!< Reserved 820h */ uint32_t Reserved24; /*!< Reserved 824h */ __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ __IO uint32_t DTHRCTL; /*!< dev thr 830h */ __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ uint32_t Reserved40; /*!< Reserved 840h */ __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ uint32_t Reserved48[15]; /*!< Reserved 848-880h */ __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ } usb_dr; typedef struct { __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ } usb_erin; typedef struct { __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ } usb_erout; typedef struct _usb_regs { usb_gr * gr; /*!< USBFS global registers */ usb_dr * dr; /*!< Device control and status registers */ usb_hr * hr; /*!< Host control and status registers */ usb_erin * er_in[6]; /*!< USB device IN endpoint register */ usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ usb_pr * pr[15]; /*!< USB Host channel-x control register */ __IO uint32_t *HPCS; /*!< USB host port control and status register */ __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ } usb_core_regs; /* global OTG control and status register bits definitions */ #define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ #define GOTGCS_ASV BIT(18) /*!< A-session valid */ #define GOTGCS_DI BIT(17) /*!< debounce interval */ #define GOTGCS_CIDPS BIT(16) /*!< id pin status */ #define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ #define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ #define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ #define GOTGCS_HNPS BIT(8) /*!< HNP successes */ #define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ #define GOTGCS_SRPS BIT(0) /*!< SRP successes */ /* global OTG interrupt flag register bits definitions */ #define GOTGINTF_DF BIT(19) /*!< debounce finish */ #define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ #define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ #define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ #define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ #define GOTGINTF_SESEND BIT(2) /*!< session end */ /* global AHB control and status register bits definitions */ #define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ #define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ #define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ #define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ #define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ /* global USB control and status register bits definitions */ #define GUSBCS_FDM BIT(30) /*!< force device mode */ #define GUSBCS_FHM BIT(29) /*!< force host mode */ #define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ #define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ #define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ #define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ #define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ #define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ #define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ /* global reset control register bits definitions */ #define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ #define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ #define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ #define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ #define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ #define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ #define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ #define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ /* global interrupt flag register bits definitions */ #define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ #define GINTF_SESIF BIT(30) /*!< session interrupt flag */ #define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ #define GINTF_IDPSC BIT(28) /*!< id pin status change */ #define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ #define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ #define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ #define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ #define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ #define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ #define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ #define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ #define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ #define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ #define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ #define GINTF_RST BIT(12) /*!< USB reset */ #define GINTF_SP BIT(11) /*!< USB suspend */ #define GINTF_ESP BIT(10) /*!< early suspend */ #define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ #define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ #define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ #define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ #define GINTF_SOF BIT(3) /*!< start of frame */ #define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ #define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ #define GINTF_COPM BIT(0) /*!< current operation mode */ /* global interrupt enable register bits definitions */ #define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ #define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ #define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ #define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ #define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ #define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ #define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ #define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ #define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ #define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ #define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ #define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ #define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ #define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ #define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ #define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ #define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ #define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ #define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ #define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ #define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ #define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ #define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ #define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ #define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ /* global receive status read and pop register bits definitions */ #define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ #define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ #define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ #define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ #define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ /* global receive FIFO length register bits definitions */ #define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ /* host non-periodic transmit FIFO length register bits definitions */ #define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ #define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ /** * @brief USB IN endpoint 0 transmit FIFO length register bits definitions */ #define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ #define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ /* host non-periodic transmit FIFO/queue status register bits definitions */ #define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ #define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ #define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ #define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ #define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ #define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ /* global core configuration register bits definitions */ #define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ #define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ #define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ #define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ #define GCCFG_PWRON BIT(16) /*!< power on */ /* core ID register bits definitions */ #define CID_CID BITS(0, 31) /*!< core ID */ /* host periodic transmit FIFO length register bits definitions */ #define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ #define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ /* device IN endpoint transmit FIFO length register bits definitions */ #define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ #define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ /* host control register bits definitions */ #define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ #define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ /* host frame interval register bits definitions */ #define HFT_FRI BITS(0, 15) /*!< frame interval */ /* host frame information remaining register bits definitions */ #define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ #define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ /* host periodic transmit FIFO/queue status register bits definitions */ #define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ #define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ #define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ #define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ #define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ #define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ #define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ #define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ #define TFQSTAT_TXFS BITS(0, 15) #define TFQSTAT_CNUM BITS(27, 30) /* host all channels interrupt register bits definitions */ #define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ /* host all channels interrupt enable register bits definitions */ #define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ /* host port control and status register bits definitions */ #define HPCS_PS BITS(17, 18) /*!< port speed */ #define HPCS_PP BIT(12) /*!< port power */ #define HPCS_PLST BITS(10, 11) /*!< port line status */ #define HPCS_PRST BIT(8) /*!< port reset */ #define HPCS_PSP BIT(7) /*!< port suspend */ #define HPCS_PREM BIT(6) /*!< port resume */ #define HPCS_PEDC BIT(3) /*!< port enable/disable change */ #define HPCS_PE BIT(2) /*!< port enable */ #define HPCS_PCD BIT(1) /*!< port connect detected */ #define HPCS_PCST BIT(0) /*!< port connect status */ /* host channel-x control register bits definitions */ #define HCHCTL_CEN BIT(31) /*!< channel enable */ #define HCHCTL_CDIS BIT(30) /*!< channel disable */ #define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ #define HCHCTL_DAR BITS(22, 28) /*!< device address */ #define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ #define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ #define HCHCTL_LSD BIT(17) /*!< low-speed device */ #define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ #define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ #define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ /* host channel-x split transaction register bits definitions */ #define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ #define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ #define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ #define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ #define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ /* host channel-x interrupt flag register bits definitions */ #define HCHINTF_DTER BIT(10) /*!< data toggle error */ #define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ #define HCHINTF_BBER BIT(8) /*!< babble error */ #define HCHINTF_USBER BIT(7) /*!< USB bus Error */ #define HCHINTF_NYET BIT(6) /*!< NYET */ #define HCHINTF_ACK BIT(5) /*!< ACK */ #define HCHINTF_NAK BIT(4) /*!< NAK */ #define HCHINTF_STALL BIT(3) /*!< STALL */ #define HCHINTF_DMAER BIT(2) /*!< DMA error */ #define HCHINTF_CH BIT(1) /*!< channel halted */ #define HCHINTF_TF BIT(0) /*!< transfer finished */ /* host channel-x interrupt enable register bits definitions */ #define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ #define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ #define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ #define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ #define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ #define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ #define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ #define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ #define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ #define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ #define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ /* host channel-x transfer length register bits definitions */ #define HCHLEN_PING BIT(31) /*!< PING token request */ #define HCHLEN_DPID BITS(29, 30) /*!< data PID */ #define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ #define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ /* host channel-x DMA address register bits definitions */ #define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ #define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ #define PORT_SPEED_HIGH PORT_SPEED(0) /*!< high speed */ #define PORT_SPEED_FULL PORT_SPEED(1) /*!< full speed */ #define PORT_SPEED_LOW PORT_SPEED(2) /*!< low speed */ #define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ #define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ #define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ #define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ #define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ #define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ #define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ #define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ #define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ #define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ #define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ #define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ extern const uint32_t PIPE_DPID[]; /* device configuration registers bits definitions */ #define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ #define DCFG_DAR BITS(4, 10) /*!< device address */ #define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ #define DCFG_DS BITS(0, 1) /*!< device speed */ /* device control registers bits definitions */ #define DCTL_POIF BIT(11) /*!< power-on initialization finished */ #define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ #define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ #define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ #define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ #define DCTL_GONS BIT(3) /*!< global OUT NAK status */ #define DCTL_GINS BIT(2) /*!< global IN NAK status */ #define DCTL_SD BIT(1) /*!< soft disconnect */ #define DCTL_RWKUP BIT(0) /*!< remote wakeup */ /* device status registers bits definitions */ #define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ #define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ #define DSTAT_SPST BIT(0) /*!< suspend status */ /* device IN endpoint common interrupt enable registers bits definitions */ #define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ #define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ #define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ #define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ #define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ #define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ #define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ /* device OUT endpoint common interrupt enable registers bits definitions */ #define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ #define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ #define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ #define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ #define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ #define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ /* device all endpoints interrupt registers bits definitions */ #define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ #define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ /* device all endpoints interrupt enable registers bits definitions */ #define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ #define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ /* device Vbus discharge time registers bits definitions */ #define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ /* device Vbus pulsing time registers bits definitions */ #define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ /* device IN endpoint FIFO empty interrupt enable register bits definitions */ #define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ /* device endpoint 0 control register bits definitions */ #define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ #define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ #define DEP0CTL_SNAK BIT(27) /*!< set NAK */ #define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ #define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ #define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ #define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ #define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ #define DEP0CTL_NAKS BIT(17) /*!< NAK status */ #define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ #define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ /* device endpoint x control register bits definitions */ #define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ #define DEPCTL_EPD BIT(30) /*!< endpoint disable */ #define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ #define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ #define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ #define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ #define DEPCTL_SNAK BIT(27) /*!< set NAK */ #define DEPCTL_CNAK BIT(26) /*!< clear NAK */ #define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ #define DEPCTL_STALL BIT(21) /*!< STALL handshake */ #define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ #define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ #define DEPCTL_NAKS BIT(17) /*!< NAK status */ #define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ #define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ #define DEPCTL_EPACT BIT(15) /*!< endpoint active */ #define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ /* device IN endpoint-x interrupt flag register bits definitions */ #define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ #define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ #define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ #define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ #define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ #define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ #define DIEPINTF_TF BIT(0) /*!< transfer finished */ /* device OUT endpoint-x interrupt flag register bits definitions */ #define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ #define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ #define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ #define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ #define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ #define DOEPINTF_TF BIT(0) /*!< transfer finished */ /* device IN endpoint 0 transfer length register bits definitions */ #define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ #define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ /* device OUT endpoint 0 transfer length register bits definitions */ #define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ #define DOEP0LEN_PCNT BIT(19) /*!< packet count */ #define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ /* device OUT endpoint-x transfer length register bits definitions */ #define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ #define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ #define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ #define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ #define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ /* device IN endpoint-x DMA address register bits definitions */ #define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ /* device OUT endpoint-x DMA address register bits definitions */ #define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ /* device IN endpoint-x transmit FIFO status register bits definitions */ #define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ /* USB power and clock registers bits definition */ #define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ #define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ #define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ #define RSTAT_DATA_UPDT 2U /* OUT data packet received */ #define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ #define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ #define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ #define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ #define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ #define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ #define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ #define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ #define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ #define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ #define DPID_MDATA 3U /* device endpoint data PID is MDATA */ #define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ #define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ #define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ #define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ #define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ #define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ #define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ #define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ #define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ #define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ #define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ #define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ #define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ #define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ #define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ #define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ #define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ #define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ #define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ #define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ #define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< Transfer length */ #define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< Packet count */ #define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ #define USB_ULPI_PHY 1 /*!< ULPI interface external PHY */ #define USB_EMBEDDED_PHY 2 /*!< Embedded PHY */ #define GRXSTS_PKTSTS_IN 2 #define GRXSTS_PKTSTS_IN_XFER_COMP 3 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 #define GRXSTS_PKTSTS_CH_HALTED 7 #define DEVICE_MODE 0 /*!< device mode */ #define HOST_MODE 1 /*!< host mode */ #define OTG_MODE 2 /*!< OTG mode */ #define HCTL_30_60MHZ 0 /*!< USB clock 30-60MHZ */ #define HCTL_48MHZ 1 /*!< USB clock 48MHZ */ #define HCTL_6MHZ 2 /*!< USB clock 6MHZ */ enum USB_SPEED { USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ USB_SPEED_LOW, /*!< USB speed low */ USB_SPEED_FULL, /*!< USB speed full */ USB_SPEED_HIGH /*!< USB speed high */ }; #define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ #define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ #define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ #define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ #define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ #define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ #define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ #define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ #endif /* __DRV_USB_REGS_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbd_int.h ================================================ /*! \file drv_usbd_int.h \brief USB device mode interrupt header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USBD_INT_H #define __DRV_USBD_INT_H #include "drv_usb_core.h" #include "drv_usb_dev.h" /* USB device-mode interrupts global service routine handler */ void usbd_isr(usb_core_driver *udev); #ifdef USB_HS_DEDICATED_EP1_ENABLED uint32_t USBD_OTG_EP1IN_ISR_Handler(usb_core_driver *udev); uint32_t USBD_OTG_EP1OUT_ISR_Handler(usb_core_driver *udev); #endif #endif /* __DRV_USBD_INT_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/drv_usbh_int.h ================================================ /*! \file drv_usbh_int.h.h \brief USB host mode interrupt management header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DRV_USBH_INT_H #define __DRV_USBH_INT_H #include "drv_usb_host.h" typedef struct _usbh_int_cb { uint8_t (*SOF)(usb_core_driver *pudev); } usbh_int_cb; extern usbh_int_cb *usbh_int_fop; uint32_t usbh_isr(usb_core_driver *pudev); #endif /* __DRV_USBH_INT_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_ch9_std.h ================================================ /*! \file usb_ch9_std.h \brief USB 2.0 standard defines \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USB_CH9_STD_H #define __USB_CH9_STD_H #include "usb_conf.h" #define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ #define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ #define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ #define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ #define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ #define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ #define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ /* bit 7 of bmRequestType: data phase transfer direction */ #define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ #define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ #define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ /* bit 6..5 of bmRequestType: request type */ #define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ #define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ #define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ #define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ #define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ #define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ #define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ #define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ /* bit 4..0 of bmRequestType: recipient type */ enum _usb_recp_type { USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ }; /* bRequest value */ enum _usb_request { USB_GET_STATUS = 0x0U, /*!< USB get status request */ USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ USB_RESERVED2 = 0x2U, USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ USB_RESERVED4 = 0x4U, USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ }; /* descriptor types of USB specifications */ enum _usb_desctype { USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualtfier descriptor type */ USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ }; /* USB Endpoint Descriptor bmAttributes bit definitions */ /* bits 1..0 : transfer type */ enum _usbx_type { USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ }; /* bits 3..2 : Sync type (only if ISOCHRONOUS) */ #define USB_EP_ATTR_NOSYNC 0x00 /* No Synchronization */ #define USB_EP_ATTR_ASYNC 0x04 /* Asynchronous */ #define USB_EP_ATTR_ADAPTIVE 0x08 /* Adaptive */ #define USB_EP_ATTR_SYNC 0x0C /* Synchronous */ #define USB_EP_ATTR_SYNCTYPE 0x0C /* Synchronous type */ /* bits 5..4 : usage type (only if ISOCHRONOUS) */ #define USB_EP_ATTR_DATA 0x00 /* Data endpoint */ #define USB_EP_ATTR_FEEDBACK 0x10 /* Feedback endpoint */ #define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 /* Implicit feedback Data endpoint */ #define USB_EP_ATTR_USAGETYPE 0x30 /* Usage type */ #define FEATURE_SELECTOR_EP 0x00 /* USB endpoint feature selector */ #define FEATURE_SELECTOR_DEV 0x01 /* USB device feature selector */ #define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) #define BYTE_LOW(x) ((uint8_t)((x)&0x00FFU)) #define BYTE_HIGH(x) ((uint8_t)(((x)&0xFF00U) >> 8U)) #define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) #define USB_DEFAULT_CONFIG 0U /* USB classes */ #define USB_CLASS_HID 0x03U /*!< USB HID class */ #define USB_CLASS_MSC 0x08U /*!< USB MSC class */ /* use the following values when USB host need to get descriptor */ #define USBH_DESC(x) (((x) << 8U) & 0xFF00U) /* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec standard request with no data stage timeout : 50ms */ #define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ #define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ #pragma pack(1) /* USB standard device request structure */ typedef struct _usb_req { uint8_t bmRequestType; /*!< type of request */ uint8_t bRequest; /*!< request of setup packet */ uint16_t wValue; /*!< value of setup packet */ uint16_t wIndex; /*!< index of setup packet */ uint16_t wLength; /*!< length of setup packet */ } usb_req; /* USB setup packet define */ typedef union _usb_setup { uint8_t data[8]; usb_req req; } usb_setup; /* USB descriptor defines */ typedef struct _usb_desc_header { uint8_t bLength; /*!< size of the descriptor */ uint8_t bDescriptorType; /*!< type of the descriptor */ } usb_desc_header; typedef struct _usb_desc_dev { usb_desc_header header; /*!< descriptor header, including type and size */ uint16_t bcdUSB; /*!< BCD of the supported USB specification */ uint8_t bDeviceClass; /*!< USB device class */ uint8_t bDeviceSubClass; /*!< USB device subclass */ uint8_t bDeviceProtocol; /*!< USB device protocol */ uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ uint16_t idVendor; /*!< vendor ID for the USB product */ uint16_t idProduct; /*!< unique product ID for the USB product */ uint16_t bcdDevice; /*!< product release (version) number */ uint8_t iManufacturer; /*!< string index for the manufacturer's name */ uint8_t iProduct; /*!< string index for the product name/details */ uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ } usb_desc_dev; typedef struct _usb_desc_config { usb_desc_header header; /*!< descriptor header, including type and size */ uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ uint8_t bmAttributes; /*!< configuration attributes */ uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ } usb_desc_config; typedef struct _usb_desc_itf { usb_desc_header header; /*!< descriptor header, including type and size */ uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ uint8_t bInterfaceClass; /*!< interface class ID */ uint8_t bInterfaceSubClass; /*!< interface subclass ID */ uint8_t bInterfaceProtocol; /*!< interface protocol ID */ uint8_t iInterface; /*!< index of the string descriptor describing the interface */ } usb_desc_itf; typedef struct _usb_desc_ep { usb_desc_header header; /*!< descriptor header, including type and size. */ uint8_t bEndpointAddress; /*!< logical address of the endpoint */ uint8_t bmAttributes; /*!< endpoint attributes */ uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ #ifdef AUDIO_ENDPOINT uint8_t bRefresh; /*!< reset to 0 */ uint8_t bSynchAddress; /*!< reset to 0 */ #endif } usb_desc_ep; typedef struct _usb_desc_LANGID { usb_desc_header header; /*!< descriptor header, including type and size. */ uint16_t wLANGID; /*!< LANGID code */ } usb_desc_LANGID; #pragma pack() #endif /* __USB_CH9_STD_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usb_conf.h ================================================ #ifndef __USB_CONF_H #define __USB_CONF_H #include "gd32vf103.h" #include //#ifndef USE_USB_FS //#define USE_USB_HS //#endif #define USE_USB_FS #ifdef USE_USB_FS #define USB_FS_CORE #endif #ifdef USE_USB_HS #define USB_HS_CORE #endif #ifdef USB_FS_CORE #define RX_FIFO_FS_SIZE 128 #define TX0_FIFO_FS_SIZE 64 #define TX1_FIFO_FS_SIZE 128 #define TX2_FIFO_FS_SIZE 0 #define TX3_FIFO_FS_SIZE 0 #define USB_RX_FIFO_FS_SIZE 128 #define USB_HTX_NPFIFO_FS_SIZE 96 #define USB_HTX_PFIFO_FS_SIZE 96 #endif /* USB_FS_CORE */ #ifdef USB_HS_CORE #define RX_FIFO_HS_SIZE 512 #define TX0_FIFO_HS_SIZE 128 #define TX1_FIFO_HS_SIZE 372 #define TX2_FIFO_HS_SIZE 0 #define TX3_FIFO_HS_SIZE 0 #define TX4_FIFO_HS_SIZE 0 #define TX5_FIFO_HS_SIZE 0 #ifdef USE_ULPI_PHY #define USB_OTG_ULPI_PHY_ENABLED #endif #ifdef USE_EMBEDDED_PHY #define USB_OTG_EMBEDDED_PHY_ENABLED #endif #define USB_OTG_HS_INTERNAL_DMA_ENABLED #define USB_OTG_HS_DEDICATED_EP1_ENABLED #endif /* USB_HS_CORE */ #ifndef USB_SOF_OUTPUT #define USB_SOF_OUTPUT 0 #endif #ifndef USB_LOW_POWER #define USB_LOW_POWER 0 #endif //#define USE_HOST_MODE //#define USE_DEVICE_MODE //#define USE_OTG_MODE #ifndef USE_HOST_MODE #define USE_DEVICE_MODE #endif #ifndef USB_FS_CORE #ifndef USB_HS_CORE #error "USB_HS_CORE or USB_FS_CORE should be defined" #endif #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #ifndef USE_USB_HS #ifndef USE_USB_FS #error "USE_USB_HS or USE_USB_FS should be defined" #endif #endif /****************** C Compilers dependant keywords ****************************/ /* In HS mode and when the DMA is used, all variables and data structures dealing with the DMA during the transaction process should be 4-bytes aligned */ #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED #if defined(__GNUC__) /* GNU Compiler */ #define __ALIGN_END __attribute__((aligned(4))) #define __ALIGN_BEGIN #endif /* __GNUC__ */ #else #define __ALIGN_BEGIN #define __ALIGN_END #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ #endif /* __USB_CONF_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_conf.h ================================================ #ifndef __USBD_CONF_H #define __USBD_CONF_H #include "usb_conf.h" #define USBD_CFG_MAX_NUM 1 #define USBD_ITF_MAX_NUM 1 #endif /* __USBD_CONF_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_core.h ================================================ /*! \file usbd_core.h \brief USB device mode core functions protype \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBD_CORE_H #define __USBD_CORE_H #include "drv_usb_core.h" #include "drv_usb_dev.h" typedef enum { USBD_OK = 0, /*!< status OK */ USBD_BUSY, /*!< status busy */ USBD_FAIL, /*!< status fail */ } usbd_status; enum _usbd_status { USBD_DEFAULT = 1, /*!< default status */ USBD_ADDRESSED = 2, /*!< address send status */ USBD_CONFIGURED = 3, /*!< configured status */ USBD_SUSPENDED = 4 /*!< suspended status */ }; /* function declarations */ /* device connect */ void usbd_connect(usb_core_driver *udev); /* device disconnect */ void usbd_disconnect(usb_core_driver *udev); /* set USB device address */ void usbd_addr_set(usb_core_driver *udev, uint8_t addr); /* initailizes the USB device-mode stack and load the class driver */ void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core); /* endpoint initialization */ uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc); /* configure the endpoint when it is disabled */ uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr); /* endpoint prepare to receive data */ uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); /* endpoint prepare to transmit data */ uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len); /* set an endpoint to STALL status */ uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr); /* clear endpoint STALLed status */ uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr); /* flush the endpoint FIFOs */ uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr); /* get the received data length */ uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num); #endif /* __USBD_CORE_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_enum.h ================================================ /*! \file usbd_enum.h \brief USB enumeration definitions \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBD_ENUM_H #define __USBD_ENUM_H #include "usbd_conf.h" #include "usbd_core.h" #include #ifndef NULL #define NULL 0U #endif typedef enum _usb_reqsta { REQ_SUPP = 0x0U, /* request support */ REQ_NOTSUPP = 0x1U /* request not support */ } usb_reqsta; /* string descriptor index */ enum _str_index { STR_IDX_LANGID = 0x0U, /* language ID string index */ STR_IDX_MFC = 0x1U, /* manufacturer string index */ STR_IDX_PRODUCT = 0x2U, /* product string index */ STR_IDX_SERIAL = 0x3U, /* serial string index */ STR_IDX_CONFIG = 0x4U, /* configuration string index */ STR_IDX_ITF = 0x5U, /* interface string index */ STR_IDX_MAX = 0x6U /* string maximum index */ }; typedef enum _usb_pwrsta { USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ } usb_pwrsta; typedef enum _usb_feature { USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ USB_FEATURE_TEST_MODE = 0x2U /* USB has endpoint test mode feature */ } usb_feature; #define ENG_LANGID 0x0409U /* english language ID */ #define CHN_LANGID 0x0804U /* chinese language ID */ /* USB device exported macros */ #define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) #define WIDE_STRING(string) _WIDE_STRING(string) #define _WIDE_STRING(string) L##string #define USBD_STRING_DESC(string) \ (void *)&(const struct { \ uint8_t _len; \ uint8_t _type; \ wchar_t _data[sizeof(string)]; \ }) { \ sizeof(WIDE_STRING(string)) + 2U - 2U, USB_DESCTYPE_STR, WIDE_STRING(string) \ } /* function declarations */ /* handle USB standard device request */ usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req); /* handle USB device class request */ usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req); /* handle USB vendor request */ usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req); /* handle USB enumeration error */ void usbd_enum_error(usb_core_driver *udev, usb_req *req); /* convert hex 32bits value into unicode char */ void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len); #endif /* __USBD_ENUM_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbd_transc.h ================================================ /*! \file usbd_transc.h \brief USB transaction core functions prototype \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBD_TRANSC_H #define __USBD_TRANSC_H #include "usbd_core.h" /* function declarations */ /* USB send data in the control transaction */ usbd_status usbd_ctl_send(usb_core_driver *udev); /* USB receive data in control transaction */ usbd_status usbd_ctl_recev(usb_core_driver *udev); /* USB send control transaction status */ usbd_status usbd_ctl_status_send(usb_core_driver *udev); /* USB control receive status */ usbd_status usbd_ctl_status_recev(usb_core_driver *udev); /* USB setup stage processing */ uint8_t usbd_setup_transc(usb_core_driver *udev); /* data out stage processing */ uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0"))); /* data in stage processing */ uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) __attribute__((optimize("O0"))); #endif /* __USBD_TRANSC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_conf.h ================================================ #ifndef __USBH_CONF_H #define __USBH_CONF_H #define USBH_MAX_EP_NUM 2 #define USBH_MAX_INTERFACES_NUM 2 #define USBH_MSC_MPS_SIZE 0x200 #endif /* __USBH_CONF_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_core.h ================================================ /*! \file usbh_core.h \brief USB host core state machine header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_CORE_H #define __USBH_CORE_H #include "drv_usb_host.h" #include "usbh_conf.h" #define MSC_CLASS 0x08U #define HID_CLASS 0x03U #define MSC_PROTOCOL 0x50U #define CBI_PROTOCOL 0x01U #define USBH_MAX_ERROR_COUNT 3U #define USBH_DEV_ADDR_DEFAULT 0U #define USBH_DEV_ADDR 1U typedef enum { USBH_OK = 0U, USBH_BUSY, USBH_FAIL, USBH_NOT_SUPPORTED, USBH_UNRECOVERED_ERROR, USBH_SPEED_UNKNOWN_ERROR, USBH_APPLY_DEINIT } usbh_status; /* USB host global operation state */ typedef enum { HOST_DEFAULT = 0U, HOST_DETECT_DEV_SPEED, HOST_DEV_ATTACHED, HOST_DEV_DETACHED, HOST_ENUM, HOST_CLASS_ENUM, HOST_CLASS_HANDLER, HOST_USER_INPUT, HOST_SUSPENDED, HOST_ERROR } usb_host_state; /* USB host enumeration state */ typedef enum { ENUM_DEFAULT = 0U, ENUM_GET_DEV_DESC, ENUM_SET_ADDR, ENUM_GET_CFG_DESC, ENUM_GET_CFG_DESC_SET, ENUM_GET_STR_DESC, ENUM_SET_CONFIGURATION, ENUM_DEV_CONFIGURED } usbh_enum_state; /* USB host control transfer state */ typedef enum { CTL_IDLE = 0U, CTL_SETUP, CTL_DATA_IN, CTL_DATA_OUT, CTL_STATUS_IN, CTL_STATUS_OUT, CTL_ERROR, CTL_FINISH } usbh_ctl_state; /* user action state */ typedef enum { USBH_USER_NO_RESP = 0U, USBH_USER_RESP_OK = 1U, } usbh_user_status; /* control transfer information */ typedef struct _usbh_control { uint8_t pipe_in_num; uint8_t pipe_out_num; uint8_t max_len; uint8_t error_count; uint8_t *buf; uint16_t ctl_len; uint16_t timer; usb_setup setup; usbh_ctl_state ctl_state; } usbh_control; /* USB device property */ typedef struct { uint8_t addr; uint32_t speed; usb_desc_dev dev_desc; usb_desc_config cfg_desc; usb_desc_itf itf_desc[USBH_MAX_INTERFACES_NUM]; usb_desc_ep ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; } usb_dev_prop; /** * @brief Device class callbacks */ typedef struct { usbh_status (*class_init)(usb_core_driver *pudev, void *phost); void (*class_deinit)(usb_core_driver *pudev, void *phost); usbh_status (*class_requests)(usb_core_driver *pudev, void *phost); usbh_status (*class_machine)(usb_core_driver *pudev, void *phost); } usbh_class_cb; /** * @brief User callbacks */ typedef struct { void (*dev_init)(void); void (*dev_deinit)(void); void (*dev_attach)(void); void (*dev_reset)(void); void (*dev_detach)(void); void (*dev_over_currented)(void); void (*dev_speed_detected)(uint32_t dev_speed); void (*dev_devdesc_assigned)(void *dev_desc); void (*dev_address_set)(void); void (*dev_cfgdesc_assigned)(usb_desc_config *cfg_desc, usb_desc_itf *itf_desc, usb_desc_ep *ep_desc); void (*dev_mfc_str)(void *mfc_str); void (*dev_prod_str)(void *prod_str); void (*dev_seral_str)(void *serial_str); void (*dev_enumerated)(void); usbh_user_status (*dev_user_input)(void); int (*dev_user_app)(void); void (*dev_not_supported)(void); void (*dev_error)(void); } usbh_user_cb; /** * @brief Host information */ typedef struct { usb_host_state cur_state; /*!< host state machine value */ usb_host_state backup_state; /*!< backup of previous state machine value */ usbh_enum_state enum_state; /*!< enumeration state machine */ usbh_control control; /*!< USB host control state machine */ usb_dev_prop dev_prop; /*!< USB device properity */ usbh_class_cb *class_cb; /*!< USB class callback */ usbh_user_cb * usr_cb; /*!< USB user callback */ } usbh_host; /* USB host stack initializations */ void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost); /* de-initialize USB host */ usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost); /* USB host core main state machine process */ void usbh_core_task(usb_core_driver *pudev, usbh_host *puhost); /* handle the error on USB host side */ void usbh_error_handler(usbh_host *puhost, usbh_status ErrType); /* get USB URB state */ static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.pipe[pp_num].urb_state; } /* get USB transfer data count */ static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num) { return pudev->host.backup_xfercount[pp_num]; } #endif /* __USBH_CORE_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_enum.h ================================================ /*! \file usbh_enum.h \brief USB host mode USB enumeration header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_ENUM_H #define __USBH_ENUM_H #include "usb_conf.h" #include "usbh_core.h" /* get the next descriptor header */ usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr); /* configure USB control status parameters */ void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len); /* get device descriptor from the USB device */ usbh_status usbh_devdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t len); /* get configuration descriptor from the USB device */ usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len); /* get string descriptor from the USB device */ usbh_status usbh_strdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len); /* set the configuration value to the connected device */ usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config); /* set the address to the connected device */ usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr); /* clear or disable a specific feature */ usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t pp_num); /* set the interface value to the connected device */ usbh_status usbh_setinterface(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t alter_setting); #endif /* __USBH_ENUM_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_pipe.h ================================================ /*! \file usbh_pipe.h \brief USB host mode pipe header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_PIPE_H #define __USBH_PIPE_H #include "usbh_core.h" #define HC_MAX 8U #define HC_OK 0x0000U #define HC_USED 0x8000U #define HC_ERROR 0xFFFFU #define HC_USED_MASK 0x7FFFU /* allocate a new pipe */ uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr); /* delete all USB host pipe */ uint8_t usbh_pipe_delete(usb_core_driver *pudev); /* free a pipe */ uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num); /* create a pipe */ uint8_t usbh_pipe_create(usb_core_driver *pudev, usb_dev_prop *udev, uint8_t pp_num, uint8_t ep_type, uint16_t ep_mpl); /* modify a pipe */ uint8_t usbh_pipe_update(usb_core_driver *pudev, uint8_t pp_num, uint8_t dev_addr, uint32_t dev_speed, uint16_t ep_mpl); #endif /* __USBH_PIPE_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/Usb/usbh_transc.h ================================================ /*! \file usbh_transc.h \brief USB host mode transactions header file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __USBH_TRANSC_H #define __USBH_TRANSC_H #include "usb_conf.h" #include "usbh_core.h" /* send the setup packet to the USB device */ usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num); /* send a data packet to the USB device */ usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); /* receive a data packet from the USB device */ usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); /* USB control transfer handler */ usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost); #endif /* __USBH_TRANSC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103.h ================================================ /****************************************************************************** * @file gd32vf103.h * @brief NMSIS Core Peripheral Access Layer Header File for GD32VF103 series * * @version V1.00 * @date 4. Jan 2020 ******************************************************************************/ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __GD32VF103_H__ #define __GD32VF103_H__ #include #ifdef __cplusplus extern "C" { #endif /** @addtogroup gd32 * @{ */ /** @addtogroup gd32vf103 * @{ */ /** @addtogroup Configuration_of_NMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum IRQn { /* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */ Reserved0_IRQn = 0, /*!< Internal reserved */ Reserved1_IRQn = 1, /*!< Internal reserved */ Reserved2_IRQn = 2, /*!< Internal reserved */ SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ Reserved3_IRQn = 4, /*!< Internal reserved */ Reserved4_IRQn = 5, /*!< Internal reserved */ Reserved5_IRQn = 6, /*!< Internal reserved */ SysTimer_IRQn = 7, /*!< System Timer Interrupt */ Reserved6_IRQn = 8, /*!< Internal reserved */ Reserved7_IRQn = 9, /*!< Internal reserved */ Reserved8_IRQn = 10, /*!< Internal reserved */ Reserved9_IRQn = 11, /*!< Internal reserved */ Reserved10_IRQn = 12, /*!< Internal reserved */ Reserved11_IRQn = 13, /*!< Internal reserved */ Reserved12_IRQn = 14, /*!< Internal reserved */ Reserved13_IRQn = 15, /*!< Internal reserved */ Reserved14_IRQn = 16, /*!< Internal reserved */ BusError_IRQn = 17, /*!< Bus Error interrupt */ PerfMon_IRQn = 18, /*!< Performance Monitor */ /* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */ /* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ /* interruput numbers */ WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ RTC_IRQn = 22, /*!< RTC alarm interrupt */ FMC_IRQn = 23, /*!< FMC interrupt */ RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ SPI0_IRQn = 54, /*!< SPI0 interrupt */ SPI1_IRQn = 55, /*!< SPI1 interrupt */ USART0_IRQn = 56, /*!< USART0 interrupt */ USART1_IRQn = 57, /*!< USART1 interrupt */ USART2_IRQn = 58, /*!< USART2 interrupt */ EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ EXMC_IRQn = 67, /*!< EXMC global interrupt */ TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ SPI2_IRQn = 70, /*!< SPI2 global interrupt */ UART3_IRQn = 71, /*!< UART3 global interrupt */ UART4_IRQn = 72, /*!< UART4 global interrupt */ TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ USBFS_IRQn = 86, /*!< USBFS global interrupt */ SOC_INT_MAX, } IRQn_Type; /* =========================================================================================================================== */ /* ================ Exception Code Definition ================ */ /* =========================================================================================================================== */ typedef enum EXCn { /* ======================================= Nuclei N/NX Specific Exception Code ======================================== */ InsUnalign_EXCn = 0, /*!< Instruction address misaligned */ InsAccFault_EXCn = 1, /*!< Instruction access fault */ IlleIns_EXCn = 2, /*!< Illegal instruction */ Break_EXCn = 3, /*!< Beakpoint */ LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */ LdFault_EXCn = 5, /*!< Load access fault */ StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */ StAccessFault_EXCn = 7, /*!< Store or AMO access fault */ UmodeEcall_EXCn = 8, /*!< Environment call from User mode */ MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */ NMI_EXCn = 0xfff, /*!< NMI interrupt*/ } EXCn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* ToDo: set the defines according your Device */ /* ToDo: define the correct core revision */ #define __NUCLEI_N_REV 0x0100 /*!< Core Revision r1p0 */ /* ToDo: define the correct core features for the nuclei_soc */ #define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */ #define __ECLIC_BASEADDR 0xD2000000UL /*!< Set to ECLIC baseaddr of your device */ #define __ECLIC_INTCTLBITS 4 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */ #define __ECLIC_INTNUM 86 /*!< Set to 1 - 1005, the external interrupt number of ECLIC Unit */ #define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */ #define __SYSTIMER_BASEADDR 0xD1000000UL /*!< Set to SysTimer baseaddr of your device */ /*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */ #define __FPU_PRESENT 0 #define __DSP_PRESENT 0 /*!< Set to 1 if DSP is present */ #define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */ #define __PMP_ENTRY_NUM 8 /*!< Set to 8 or 16, the number of PMP entries */ #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */ /** @} */ /* End of group Configuration_of_CMSIS */ #include /*!< Nuclei N/NX class processor and core peripherals */ /* ToDo: include your system_nuclei_soc.h file replace 'Device' with your device name */ #include "system_gd32vf103.h" /*!< gd32vf103 System */ /* ======================================== Start of section using anonymous unions ======================================== */ #if defined(__GNUC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* system frequency define */ #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ #define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ #define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) #define RTC_FREQ LXTAL_VALUE // The TIMER frequency is just the RTC frequency #define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock / 4) // LXTAL_VALUE units HZ /* enum definitions */ typedef enum { DISABLE = 0, ENABLE = !DISABLE } EventStatus, ControlStatus; typedef enum { FALSE = 0, TRUE = !FALSE } BOOL; typedef enum { RESET = 0, SET = 1, MAX = 0X7FFFFFFF } FlagStatus; typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrStatus; /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_peripherals * @{ */ /**************************************************************************** * Platform definitions *****************************************************************************/ /* ToDo: add here your device specific peripheral access structure typedefs following is an example for Systick Timer*/ /* =========================================================================================================================== */ /* ================ SysTick Timer ================ */ /* =========================================================================================================================== */ /*@}*/ /* end of group nuclei_soc_Peripherals */ /* ========================================= End of section using anonymous unions ========================================= */ #if defined(__GNUC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /* ToDo: add here your device peripherals base addresses following is an example for timer */ /** @addtogroup Device_Peripheral_peripheralAddr * @{ */ /* main flash and SRAM memory map */ #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ #define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ #define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ /* peripheral memory map */ #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ #define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ /* advanced peripheral bus 1 memory map */ #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ /* advanced peripheral bus 2 memory map */ #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ /* advanced high performance bus 1 memory map */ #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ /** @} */ /* End of group Device_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /* ToDo: add here your device peripherals pointer definitions following is an example for timer */ /** @addtogroup Device_Peripheral_declaration * @{ */ /* bit operations */ #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) #define BIT(x) ((uint32_t)((uint32_t)0x01U << (x))) #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval)&BITS((start), (end))) >> (start)) // Interrupt Numbers #define SOC_ECLIC_NUM_INTERRUPTS 86 #define SOC_ECLIC_INT_GPIO_BASE 19 // Interrupt Handler Definitions #define SOC_MTIMER_HANDLER eclic_mtip_handler #define SOC_SOFTINT_HANDLER eclic_msip_handler #define NUM_GPIO 32 extern uint32_t get_cpu_freq(void); /** * \brief delay a time in milliseconds * \param[in] count: count in milliseconds * \param[out] none * \retval none */ extern void delay_1ms(uint32_t count); /** @} */ /* End of group gd32vf103_soc */ /** @} */ /* End of group gd32vf103 */ /* define startup timeout value of high speed crystal oscillator (HXTAL) */ #if !defined(HXTAL_STARTUP_TIMEOUT) #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) #endif /* high speed crystal oscillator startup timeout */ /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ #if !defined(IRC8M_VALUE) #define IRC8M_VALUE ((uint32_t)8000000) #endif /* internal 8MHz RC oscillator value */ /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ #if !defined(IRC8M_STARTUP_TIMEOUT) #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) #endif /* internal 8MHz RC oscillator startup timeout */ /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ #if !defined(IRC40K_VALUE) #define IRC40K_VALUE ((uint32_t)40000) #endif /* internal 40KHz RC oscillator value */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ #if !defined(LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ #if !defined(HXTAL_VALUE) #define HXTAL_VALUE ((uint32_t)8000000) #endif /* high speed crystal oscillator value */ #ifdef __cplusplus } #endif #endif /* __GD32VF103_SOC_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_adc.h ================================================ /*! \file gd32vf103_adc.h \brief definitions for the ADC \version 2020-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_ADC_H #define GD32VF103_ADC_H #include "gd32vf103.h" /* ADC definitions */ #define ADC0 ADC_BASE #define ADC1 (ADC_BASE + 0x400U) /* registers definitions */ #define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ #define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ #define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ #define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ #define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ #define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ #define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ #define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ #define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ #define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ #define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ #define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ #define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ #define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ #define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ #define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ #define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ #define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ #define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ #define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */ /* bits definitions */ /* ADC_STAT */ #define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ #define ADC_STAT_EOC BIT(1) /*!< end of conversion */ #define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ #define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ /* ADC_CTL0 */ #define ADC_CTL0_WDCHSEL BITS(0, 4) /*!< analog watchdog channel select bits */ #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ #define ADC_CTL0_SM BIT(8) /*!< scan mode */ #define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ #define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */ #define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */ #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ /* ADC_CTL1 */ #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ #define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ #define ADC_CTL1_ETSIC BITS(12, 14) /*!< external trigger select for inserted channel */ #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ #define ADC_CTL1_ETSRC BITS(17, 19) /*!< external trigger select for regular channel */ #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ /* ADC_SAMPTx x=0..1 */ #define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n sample time selection */ /* ADC_IOFFx x=0..3 */ #define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */ /* ADC_WDHT */ #define ADC_WDHT_WDHT BITS(0, 11) /*!< analog watchdog high threshold */ /* ADC_WDLT */ #define ADC_WDLT_WDLT BITS(0, 11) /*!< analog watchdog low threshold */ /* ADC_RSQx x=0..2 */ #define ADC_RSQX_RSQN BITS(0, 4) /*!< nth conversion in regular sequence */ #define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */ /* ADC_ISQ */ #define ADC_ISQ_ISQN BITS(0, 4) /*!< nth conversion in inserted sequence */ #define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */ /* ADC_IDATAx x=0..3*/ #define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted data n */ /* ADC_RDATA */ #define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */ #define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */ /* ADC_OVSCR */ #define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ #define ADC_OVSCR_OVSR BITS(2, 4) /*!< oversampling ratio */ #define ADC_OVSCR_OVSS BITS(5, 8) /*!< oversampling shift */ #define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ #define ADC_OVSCR_DRES BITS(12, 13) /*!< ADC data resolution */ /* constants definitions */ /* adc_stat register value */ #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ #define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ /* scan mode */ #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ /* inserted channel group convert automatically */ #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ /* ADC sync mode */ #define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ #define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ #define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ #define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ #define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ #define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ /* adc_ctl1 register value */ #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ /* continuous mode */ #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ /* external trigger select for regular channel */ #define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ /* for ADC0 and ADC1 regular channel */ #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ #define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ #define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ #define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ #define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ #define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ /* external trigger mode for inserted channel */ #define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ /* for ADC0 and ADC1 inserted channel */ #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ #define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ #define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ #define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ #define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ #define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ /* adc_samptx register value */ #define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ /* adc_ioffx register value */ #define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ /* adc_wdht register value */ #define WDHT_WDHT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ /* adc_wdlt register value */ #define WDLT_WDLT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ /* adc_rsqx register value */ #define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ /* adc_isq register value */ #define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ /* ADC channel group definitions */ #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ /* ADC inserted channel definitions */ #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ /* ADC channel definitions */ #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ /* ADC interrupt */ #define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ /* ADC interrupt flag */ #define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ #define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ /* ADC resolution definitions */ #define OVSCR_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) #define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ #define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ #define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ #define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */ /* ADC oversampling mode */ #define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */ #define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ /* ADC oversampling shift */ #define OVSCR_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) #define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ /* ADC oversampling ratio */ #define OVSCR_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) #define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ #define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ #define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ #define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */ #define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */ #define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */ #define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */ #define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */ /* function declarations */ /* initialization config */ /* reset ADC */ void adc_deinit(uint32_t adc_periph); /* configure the ADC sync mode */ void adc_mode_config(uint32_t mode); /* enable or disable ADC special function */ void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); /* configure ADC data alignment */ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); /* enable ADC interface */ void adc_enable(uint32_t adc_periph); /* disable ADC interface */ void adc_disable(uint32_t adc_periph); /* ADC calibration and reset calibration */ void adc_calibration_enable(uint32_t adc_periph); /* enable the temperature sensor and Vrefint channel */ void adc_tempsensor_vrefint_enable(void); /* disable the temperature sensor and Vrefint channel */ void adc_tempsensor_vrefint_disable(void); /* DMA config */ /* enable DMA request */ void adc_dma_mode_enable(uint32_t adc_periph); /* disable DMA request */ void adc_dma_mode_disable(uint32_t adc_periph); /* regular group and inserted group config */ /* configure ADC discontinuous mode */ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); /* configure the length of regular channel group or inserted channel group */ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); /* configure ADC regular channel */ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); /* configure ADC inserted channel */ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); /* configure ADC inserted channel offset */ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); /* configure ADC external trigger source */ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); /* configure ADC external trigger */ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); /* enable ADC software trigger */ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); /* get channel data */ /* read ADC regular group data register */ uint16_t adc_regular_data_read(uint32_t adc_periph); /* read ADC inserted group data register */ uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); /* read the last ADC0 and ADC1 conversion result data in sync mode */ uint32_t adc_sync_mode_convert_value_read(void); /* watchdog config */ /* configure ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); /* configure ADC analog watchdog group channel */ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); /* disable ADC analog watchdog */ void adc_watchdog_disable(uint32_t adc_periph); /* configure ADC analog watchdog threshold */ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); /* interrupt & flag functions */ /* get the ADC flag bits */ FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); /* clear the ADC flag bits */ void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); /* get the bit state of ADCx software start conversion */ FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); /* get the bit state of ADCx software inserted channel start conversion */ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); /* get the ADC interrupt bits */ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); /* clear the ADC flag */ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); /* enable ADC interrupt */ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); /* disable ADC interrupt */ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); /* ADC resolution & oversample */ /* ADC resolution config */ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); /* ADC oversample mode config */ void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); /* enable ADC oversample mode */ void adc_oversample_mode_enable(uint32_t adc_periph); /* disable ADC oversample mode */ void adc_oversample_mode_disable(uint32_t adc_periph); #endif /* GD32VF103_ADC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_bkp.h ================================================ /*! \file gd32vf103_bkp.h \brief definitions for the BKP \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_BKP_H #define GD32VF103_BKP_H #include "gd32vf103.h" /* BKP definitions */ #define BKP BKP_BASE /*!< BKP base address */ /* registers definitions */ #define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ #define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ #define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ #define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ #define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ #define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ #define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ #define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ #define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ #define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ #define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ #define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ #define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ #define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ #define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ #define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ #define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ #define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ #define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ #define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ #define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ #define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ #define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ #define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ #define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ #define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ #define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ #define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ #define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ #define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ #define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ #define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ #define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ #define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ #define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ #define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ #define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ #define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ #define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ #define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ #define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ #define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ #define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ #define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ #define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ /* bits definitions */ /* BKP_DATA */ #define BKP_DATA BITS(0, 15) /*!< backup data */ /* BKP_OCTL */ #define BKP_OCTL_RCCV BITS(0, 6) /*!< RTC clock calibration value */ #define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ #define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ #define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ /* BKP_TPCTL */ #define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ #define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ /* BKP_TPCS */ #define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ #define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ #define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ #define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ #define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ /* constants definitions */ /* BKP data register number */ typedef enum { BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_1, /*!< BKP data register 1 */ BKP_DATA_2, /*!< BKP data register 2 */ BKP_DATA_3, /*!< BKP data register 3 */ BKP_DATA_4, /*!< BKP data register 4 */ BKP_DATA_5, /*!< BKP data register 5 */ BKP_DATA_6, /*!< BKP data register 6 */ BKP_DATA_7, /*!< BKP data register 7 */ BKP_DATA_8, /*!< BKP data register 8 */ BKP_DATA_9, /*!< BKP data register 9 */ BKP_DATA_10, /*!< BKP data register 10 */ BKP_DATA_11, /*!< BKP data register 11 */ BKP_DATA_12, /*!< BKP data register 12 */ BKP_DATA_13, /*!< BKP data register 13 */ BKP_DATA_14, /*!< BKP data register 14 */ BKP_DATA_15, /*!< BKP data register 15 */ BKP_DATA_16, /*!< BKP data register 16 */ BKP_DATA_17, /*!< BKP data register 17 */ BKP_DATA_18, /*!< BKP data register 18 */ BKP_DATA_19, /*!< BKP data register 19 */ BKP_DATA_20, /*!< BKP data register 20 */ BKP_DATA_21, /*!< BKP data register 21 */ BKP_DATA_22, /*!< BKP data register 22 */ BKP_DATA_23, /*!< BKP data register 23 */ BKP_DATA_24, /*!< BKP data register 24 */ BKP_DATA_25, /*!< BKP data register 25 */ BKP_DATA_26, /*!< BKP data register 26 */ BKP_DATA_27, /*!< BKP data register 27 */ BKP_DATA_28, /*!< BKP data register 28 */ BKP_DATA_29, /*!< BKP data register 29 */ BKP_DATA_30, /*!< BKP data register 30 */ BKP_DATA_31, /*!< BKP data register 31 */ BKP_DATA_32, /*!< BKP data register 32 */ BKP_DATA_33, /*!< BKP data register 33 */ BKP_DATA_34, /*!< BKP data register 34 */ BKP_DATA_35, /*!< BKP data register 35 */ BKP_DATA_36, /*!< BKP data register 36 */ BKP_DATA_37, /*!< BKP data register 37 */ BKP_DATA_38, /*!< BKP data register 38 */ BKP_DATA_39, /*!< BKP data register 39 */ BKP_DATA_40, /*!< BKP data register 40 */ BKP_DATA_41, /*!< BKP data register 41 */ } bkp_data_register_enum; /* BKP register */ #define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number)*0x04U) #define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) /* get data of BKP data register */ #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) /* RTC clock calibration value */ #define OCTL_RCCV(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0)) /* RTC output selection */ #define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ #define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ /* tamper pin active level */ #define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ #define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ /* tamper flag */ #define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ /* tamper interrupt flag */ #define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ /* function declarations */ /* reset BKP registers */ void bkp_deinit(void); /* write BKP data register */ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); /* read BKP data register */ uint16_t bkp_data_read(bkp_data_register_enum register_number); /* RTC related functions */ /* enable RTC clock calibration output */ void bkp_rtc_calibration_output_enable(void); /* disable RTC clock calibration output */ void bkp_rtc_calibration_output_disable(void); /* enable RTC alarm or second signal output */ void bkp_rtc_signal_output_enable(void); /* disable RTC alarm or second signal output */ void bkp_rtc_signal_output_disable(void); /* select RTC output */ void bkp_rtc_output_select(uint16_t outputsel); /* set RTC clock calibration value */ void bkp_rtc_calibration_value_set(uint8_t value); /* tamper pin related functions */ /* enable tamper pin detection */ void bkp_tamper_detection_enable(void); /* disable tamper pin detection */ void bkp_tamper_detection_disable(void); /* set tamper pin active level */ void bkp_tamper_active_level_set(uint16_t level); /* interrupt & flag functions */ /* enable tamper interrupt */ void bkp_interrupt_enable(void); /* disable tamper interrupt */ void bkp_interrupt_disable(void); /* get tamper flag state */ FlagStatus bkp_flag_get(void); /* clear tamper flag state */ void bkp_flag_clear(void); /* get tamper interrupt flag state */ FlagStatus bkp_interrupt_flag_get(void); /* clear tamper interrupt flag state */ void bkp_interrupt_flag_clear(void); #endif /* GD32VF103_BKP_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_crc.h ================================================ /*! \file gd32vf103_crc.h \brief definitions for the CRC \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_CRC_H #define GD32VF103_CRC_H #include "gd32vf103.h" /* CRC definitions */ #define CRC CRC_BASE /* registers definitions */ #define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ #define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ #define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ /* bits definitions */ /* CRC_DATA */ #define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ /* CRC_FDATA */ #define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ /* CRC_CTL */ #define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ /* function declarations */ /* deinit CRC calculation unit */ void crc_deinit(void); /* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ void crc_data_register_reset(void); /* read the value of the data register */ uint32_t crc_data_register_read(void); /* read the value of the free data register */ uint8_t crc_free_data_register_read(void); /* write data to the free data register */ void crc_free_data_register_write(uint8_t free_data); /* calculate the CRC value of a 32-bit data */ uint32_t crc_single_data_calculate(uint32_t sdata); /* calculate the CRC value of an array of 32-bit values */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); #endif /* GD32VF103_CRC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dac.h ================================================ /*! \file gd32vf103_dac.h \brief definitions for the DAC \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_DAC_H #define GD32VF103_DAC_H #include "gd32vf103.h" /* DACx(x=0,1) definitions */ #define DAC DAC_BASE #define DAC0 (0U) #define DAC1 (1U) /* registers definitions */ #define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ #define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ #define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ #define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ #define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ #define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ #define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ #define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ #define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ #define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ #define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ #define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ #define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ /* bits definitions */ /* DAC_CTL */ #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ #define DAC_CTL_DTSEL0 BITS(3, 5) /*!< DAC0 trigger source selection enable/disable bits */ #define DAC_CTL_DWM0 BITS(6, 7) /*!< DAC0 noise wave mode */ #define DAC_CTL_DWBW0 BITS(8, 11) /*!< DAC0 noise wave bit width */ #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ #define DAC_CTL_DTSEL1 BITS(19, 21) /*!< DAC1 trigger source selection enable/disable bits */ #define DAC_CTL_DWM1 BITS(22, 23) /*!< DAC1 noise wave mode */ #define DAC_CTL_DWBW1 BITS(24, 27) /*!< DAC1 noise wave bit width */ #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ /* DAC_SWT */ #define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ /* DAC0_R12DH */ #define DAC0_R12DH_DAC0_DH BITS(0, 11) /*!< DAC0 12-bit right-aligned data bits */ /* DAC0_L12DH */ #define DAC0_L12DH_DAC0_DH BITS(4, 15) /*!< DAC0 12-bit left-aligned data bits */ /* DAC0_R8DH */ #define DAC0_R8DH_DAC0_DH BITS(0, 7) /*!< DAC0 8-bit right-aligned data bits */ /* DAC1_R12DH */ #define DAC1_R12DH_DAC1_DH BITS(0, 11) /*!< DAC1 12-bit right-aligned data bits */ /* DAC1_L12DH */ #define DAC1_L12DH_DAC1_DH BITS(4, 15) /*!< DAC1 12-bit left-aligned data bits */ /* DAC1_R8DH */ #define DAC1_R8DH_DAC1_DH BITS(0, 7) /*!< DAC1 8-bit right-aligned data bits */ /* DACC_R12DH */ #define DACC_R12DH_DAC0_DH BITS(0, 11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ #define DACC_R12DH_DAC1_DH BITS(16, 27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ /* DACC_L12DH */ #define DACC_L12DH_DAC0_DH BITS(4, 15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ #define DACC_L12DH_DAC1_DH BITS(20, 31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ /* DACC_R8DH */ #define DACC_R8DH_DAC0_DH BITS(0, 7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ #define DACC_R8DH_DAC1_DH BITS(8, 15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ /* DAC0_DO */ #define DAC0_DO_DAC0_DO BITS(0, 11) /*!< DAC0 12-bit output data bits */ /* DAC1_DO */ #define DAC1_DO_DAC1_DO BITS(0, 11) /*!< DAC1 12-bit output data bits */ /* constants definitions */ /* DAC trigger source */ #define CTL_DTSEL(regval) (BITS(3, 5) & ((uint32_t)(regval) << 3)) #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ #define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ #define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ #define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ #define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ /* DAC noise wave mode */ #define CTL_DWM(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6)) #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ /* DAC noise wave bit width */ #define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8)) #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ #define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ #define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ #define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ #define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ #define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ #define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ #define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ #define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ #define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ /* unmask LFSR bits in DAC LFSR noise mode */ #define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ #define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ #define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ #define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ #define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ #define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ #define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ #define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ #define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ #define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ #define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ /* DAC data alignment */ #define DATA_ALIGN(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ /* triangle amplitude in DAC triangle noise mode */ #define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ #define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ #define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ #define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ #define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ #define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ #define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ #define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ #define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ /* function declarations */ /* initialization functions */ /* deinitialize DAC */ void dac_deinit(void); /* enable DAC */ void dac_enable(uint32_t dac_periph); /* disable DAC */ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ void dac_dma_disable(uint32_t dac_periph); /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ void dac_output_buffer_disable(uint32_t dac_periph); /* get the last data output value */ uint16_t dac_output_value_get(uint32_t dac_periph); /* set DAC data holding register value */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); /* DAC trigger configuration */ /* enable DAC trigger */ void dac_trigger_enable(uint32_t dac_periph); /* disable DAC trigger */ void dac_trigger_disable(uint32_t dac_periph); /* configure DAC trigger source */ void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); /* enable DAC software trigger */ void dac_software_trigger_enable(uint32_t dac_periph); /* disable DAC software trigger */ void dac_software_trigger_disable(uint32_t dac_periph); /* DAC wave mode configuration */ /* configure DAC wave mode */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); /* configure DAC wave bit width */ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); /* configure DAC LFSR noise mode */ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); /* configure DAC triangle noise mode */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); /* DAC concurrent mode configuration */ /* enable DAC concurrent mode */ void dac_concurrent_enable(void); /* disable DAC concurrent mode */ void dac_concurrent_disable(void); /* enable DAC concurrent software trigger */ void dac_concurrent_software_trigger_enable(void); /* disable DAC concurrent software trigger */ void dac_concurrent_software_trigger_disable(void); /* enable DAC concurrent buffer function */ void dac_concurrent_output_buffer_enable(void); /* disable DAC concurrent buffer function */ void dac_concurrent_output_buffer_disable(void); /* set DAC concurrent mode data holding register value */ void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); #endif /* GD32VF103_DAC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dbg.h ================================================ /*! \file gd32vf103_dbg.h \brief definitions for the DBG \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_DBG_H #define GD32VF103_DBG_H #include "gd32vf103.h" /* DBG definitions */ #define DBG DBG_BASE /* registers definitions */ #define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ #define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ /* bits definitions */ /* DBG_ID */ #define DBG_ID_ID_CODE BITS(0, 31) /*!< DBG ID code values */ /* DBG_CTL */ #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ #define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ #define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ #define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ #define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ #define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ #define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ #define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */ #define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ #define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ #define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ /* constants definitions */ /* debug hold when core is halted */ typedef enum { DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ } dbg_periph_enum; /* DBG low power mode configurations */ #define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ #define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ /* function declarations */ /* read DBG_ID code register */ uint32_t dbg_id_get(void); /* low power behavior configuration */ /* enable low power behavior when the MCU is in debug mode */ void dbg_low_power_enable(uint32_t dbg_low_power); /* disable low power behavior when the MCU is in debug mode */ void dbg_low_power_disable(uint32_t dbg_low_power); /* peripheral behavior configuration */ /* enable peripheral behavior when the MCU is in debug mode */ void dbg_periph_enable(dbg_periph_enum dbg_periph); /* disable peripheral behavior when the MCU is in debug mode */ void dbg_periph_disable(dbg_periph_enum dbg_periph); #endif /* GD32VF103_DBG_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_dma.h ================================================ /*! \file gd32vf103_dma.h \brief definitions for the DMA \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-10-30, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_DMA_H #define GD32VF103_DMA_H #include "gd32vf103.h" /* DMA definitions */ #define DMA0 (DMA_BASE) /*!< DMA0 base address */ #define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ /* registers definitions */ #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ #define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ #define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ #define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ #define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ #define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ #define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ #define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ #define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ #define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ #define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ #define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ #define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ #define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ #define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ #define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ /* bits definitions */ /* DMA_INTF */ #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ /* DMA_INTC */ #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ #define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ #define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ /* DMA_CHxCTL, x=0..6 */ #define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ #define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ #define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ #define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ #define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ #define DMA_CHXCTL_PWIDTH BITS(8, 9) /*!< transfer data width of peripheral */ #define DMA_CHXCTL_MWIDTH BITS(10, 11) /*!< transfer data width of memory */ #define DMA_CHXCTL_PRIO BITS(12, 13) /*!< priority level */ #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ /* DMA_CHxCNT, x=0..6 */ #define DMA_CHXCNT_CNT BITS(0, 15) /*!< transfer counter */ /* DMA_CHxPADDR, x=0..6 */ #define DMA_CHXPADDR_PADDR BITS(0, 31) /*!< peripheral base address */ /* DMA_CHxMADDR, x=0..6 */ #define DMA_CHXMADDR_MADDR BITS(0, 31) /*!< memory base address */ /* constants definitions */ /* DMA channel select */ typedef enum { DMA_CH0 = 0, /*!< DMA Channel0 */ DMA_CH1, /*!< DMA Channel1 */ DMA_CH2, /*!< DMA Channel2 */ DMA_CH3, /*!< DMA Channel3 */ DMA_CH4, /*!< DMA Channel4 */ DMA_CH5, /*!< DMA Channel5 */ DMA_CH6 /*!< DMA Channel6 */ } dma_channel_enum; /* DMA initialize struct */ typedef struct { uint32_t periph_addr; /*!< peripheral base address */ uint32_t periph_width; /*!< transfer data size of peripheral */ uint32_t memory_addr; /*!< memory base address */ uint32_t memory_width; /*!< transfer data size of memory */ uint32_t number; /*!< channel transfer number */ uint32_t priority; /*!< channel priority level */ uint8_t periph_inc; /*!< peripheral increasing mode */ uint8_t memory_inc; /*!< memory increasing mode */ uint8_t direction; /*!< channel data transfer direction */ } dma_parameter_struct; #define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift)*4U)) /*!< DMA channel flag shift */ /* DMA_register address */ #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ #define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ #define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ /* DMA reset value */ #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ /* DMA_INTF register */ /* interrupt flag bits */ #define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ /* flag bits */ #define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ #define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ /* DMA_CHxCTL register */ /* interrupt enable bits */ #define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ #define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ #define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ /* transfer direction */ #define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ #define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ /* peripheral increasing mode */ #define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */ #define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */ /* memory increasing mode */ #define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */ #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ /* transfer data size of peripheral */ #define CHCTL_PWIDTH(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ /* transfer data size of memory */ #define CHCTL_MWIDTH(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ /* channel priority level */ #define CHCTL_PRIO(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ /* memory to memory mode */ #define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ #define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ /* DMA_CHxCNT register */ /* transfer counter */ #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ /* function declarations */ /* DMA deinitialization and initialization functions */ /* deinitialize DMA a channel registers */ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); /* initialize the parameters of DMA struct with the default values */ void dma_struct_para_init(dma_parameter_struct *init_struct); /* initialize DMA channel */ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); /* enable DMA circulation mode */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA circulation mode */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); /* enable memory to memory mode */ void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable memory to memory mode */ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); /* enable DMA channel */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable DMA channel */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); /* DMA configuration functions */ /* set DMA peripheral base address */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); /* set DMA memory base address */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); /* set the number of remaining data to be transferred by the DMA */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); /* get the number of remaining data to be transferred by the DMA */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); /* configure priority level of DMA channel */ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); /* configure transfer data size of memory */ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); /* configure transfer data size of peripheral */ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); /* enable next address increasement algorithm of memory */ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable next address increasement algorithm of memory */ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); /* enable next address increasement algorithm of peripheral */ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); /* disable next address increasement algorithm of peripheral */ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); /* configure the direction of data transfer on the channel */ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); /* flag and interrupt functions */ /* check DMA flag is set or not */ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear the flag of a DMA channel */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* check DMA flag and interrupt enable bit is set or not */ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear the interrupt flag of a DMA channel */ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* enable DMA interrupt */ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); #endif /* GD32VF103_DMA_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_eclic.h ================================================ /*! \file gd32vf103_eclic.h \brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller) \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_ECLIC_H #define GD32VF103_ECLIC_H #include "gd32vf103.h" /* constants definitions */ #define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */ #define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */ #define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */ #define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */ #define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */ #define __SEV eclic_send_event /* function declarations */ /* enable the global interrupt */ void eclic_global_interrupt_enable(void); /* disable the global interrupt */ void eclic_global_interrupt_disable(void); /* set the priority group */ void eclic_priority_group_set(uint8_t prigroup); /* enable the interrupt request */ void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority); /* disable the interrupt request */ void eclic_irq_disable(uint32_t source); /* reset system */ void eclic_system_reset(void); /* send event(SEV) */ void eclic_send_event(void); #endif /* GD32VF103_ECLIC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exmc.h ================================================ /*! \file gd32vf103_exmc.h \brief definitions for the EXMC \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_EXMC_H #define GD32VF103_EXMC_H #include "gd32vf103.h" /* EXMC definitions */ #define EXMC (EXMC_BASE) /*!< EXMC register base address */ /* registers definitions */ /* NOR/PSRAM */ #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ /* bits definitions */ /* NOR/PSRAM */ /* EXMC_SNCTLx, x=0 */ #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ #define EXMC_SNCTL_NRTP BITS(2, 3) /*!< NOR bank memory type */ #define EXMC_SNCTL_NRW BITS(4, 5) /*!< NOR bank memory data bus width */ #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ /* EXMC_SNTCFGx, x=0 */ #define EXMC_SNTCFG_ASET BITS(0, 3) /*!< address setup time */ #define EXMC_SNTCFG_AHLD BITS(4, 7) /*!< address hold time */ #define EXMC_SNTCFG_DSET BITS(8, 15) /*!< data setup time */ #define EXMC_SNTCFG_BUSLAT BITS(16, 19) /*!< bus latency */ /* constants definitions */ /* EXMC NOR/SRAM timing initialize struct */ typedef struct { uint32_t bus_latency; /*!< configure the bus latency */ uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ } exmc_norsram_timing_parameter_struct; /* EXMC NOR/SRAM initialize struct */ typedef struct { uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ ControlStatus asyn_wait; /*!< enable or disable the asynchronous wait function */ ControlStatus nwait_signal; /*!< enable or disable the NWAIT signal */ ControlStatus memory_write; /*!< enable or disable the write operation */ uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ uint32_t databus_width; /*!< specifies the databus width of external memory */ uint32_t memory_type; /*!< specifies the type of external memory */ ControlStatus address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ exmc_norsram_timing_parameter_struct *read_write_timing; /*!< timing parameters for read and write */ } exmc_norsram_parameter_struct; /* EXMC register address */ #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ /* NOR bank memory data bus width */ #define SNCTL_NRW(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ /* NOR bank memory type */ #define SNCTL_NRTP(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ /* EXMC NOR/SRAM bank region definition */ #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ /* EXMC NWAIT signal polarity configuration */ #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ #define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ /* function declarations */ /* deinitialize EXMC NOR/SRAM region */ void exmc_norsram_deinit(uint32_t norsram_region); /* exmc_norsram_parameter_struct parameter initialize */ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); /* initialize EXMC NOR/SRAM region */ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); /* EXMC NOR/SRAM bank enable */ void exmc_norsram_enable(uint32_t norsram_region); /* EXMC NOR/SRAM bank disable */ void exmc_norsram_disable(uint32_t norsram_region); #endif /* GD32VF103_EXMC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_exti.h ================================================ /*! \file gd32vf103_exti.h \brief definitions for the EXTI \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_EXTI_H #define GD32VF103_EXTI_H #include "gd32vf103.h" /* EXTI definitions */ #define EXTI EXTI_BASE /* registers definitions */ #define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ #define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ #define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ #define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ #define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ #define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ /* bits definitions */ /* EXTI_INTEN */ #define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ #define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ #define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ #define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ #define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ #define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ #define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ #define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ #define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ #define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ #define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ #define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ #define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ #define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ #define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ #define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ #define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ #define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ #define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ /* EXTI_EVEN */ #define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ #define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ #define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ #define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ #define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ #define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ #define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ #define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ #define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ #define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ #define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ #define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ #define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ #define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ #define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ #define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ #define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ #define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ #define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ /* EXTI_RTEN */ #define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ #define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ #define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ #define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ #define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ #define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ #define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ #define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ #define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ #define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ #define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ #define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ #define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ #define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ #define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ #define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ #define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ #define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ #define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ /* EXTI_FTEN */ #define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ #define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ #define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ #define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ #define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ #define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ #define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ #define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ #define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ #define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ #define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ #define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ #define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ #define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ #define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ #define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ #define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ #define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ #define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ /* EXTI_SWIEV */ #define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ #define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ #define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ #define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ #define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ #define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ #define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ #define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ #define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ #define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ #define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ #define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ #define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ #define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ #define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ #define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ #define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ #define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ #define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ /* EXTI_PD */ #define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ #define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ #define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ #define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ #define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ #define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ #define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ #define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ #define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ #define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ #define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ #define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ #define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ #define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ #define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ #define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ #define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ #define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ #define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ /* constants definitions */ /* EXTI line number */ typedef enum { EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ EXTI_3 = BIT(3), /*!< EXTI line 3 */ EXTI_4 = BIT(4), /*!< EXTI line 4 */ EXTI_5 = BIT(5), /*!< EXTI line 5 */ EXTI_6 = BIT(6), /*!< EXTI line 6 */ EXTI_7 = BIT(7), /*!< EXTI line 7 */ EXTI_8 = BIT(8), /*!< EXTI line 8 */ EXTI_9 = BIT(9), /*!< EXTI line 9 */ EXTI_10 = BIT(10), /*!< EXTI line 10 */ EXTI_11 = BIT(11), /*!< EXTI line 11 */ EXTI_12 = BIT(12), /*!< EXTI line 12 */ EXTI_13 = BIT(13), /*!< EXTI line 13 */ EXTI_14 = BIT(14), /*!< EXTI line 14 */ EXTI_15 = BIT(15), /*!< EXTI line 15 */ EXTI_16 = BIT(16), /*!< EXTI line 16 */ EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */ } exti_line_enum; /* external interrupt and event */ typedef enum { EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_EVENT /*!< EXTI event mode */ } exti_mode_enum; /* interrupt trigger mode */ typedef enum { EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ EXTI_TRIG_BOTH, /*!< EXTI rising edge and falling edge trigger */ EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ } exti_trig_type_enum; /* function declarations */ /* initialization, EXTI lines configuration functions */ /* deinitialize the EXTI */ void exti_deinit(void); /* enable the configuration of EXTI initialize */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); /* enable the events from EXTI line x */ void exti_event_enable(exti_line_enum linex); /* disable the interrupts from EXTI line x */ void exti_interrupt_disable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); /* interrupt & flag functions */ /* get EXTI lines pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ void exti_flag_clear(exti_line_enum linex); /* get EXTI lines flag when the interrupt flag is set */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex); /* clear EXTI lines pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); /* enable the EXTI software interrupt event */ void exti_software_interrupt_enable(exti_line_enum linex); /* disable the EXTI software interrupt event */ void exti_software_interrupt_disable(exti_line_enum linex); #endif /* GD32VF103_EXTI_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fmc.h ================================================ /*! \file gd32vf103_fmc.h \brief definitions for the FMC \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-09-18, V1.0.1, firmware for GD32VF103 \version 2020-02-20, V1.0.2, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_FMC_H #define GD32VF103_FMC_H #include "gd32vf103.h" /* FMC and option byte definition */ #define FMC FMC_BASE /*!< FMC register base address */ #define OB OB_BASE /*!< option bytes base address */ /* registers definitions */ #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ #define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ #define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ #define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ #define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ #define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ #define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ #define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ #define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ #define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ #define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ #define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ /* bits definitions */ /* FMC_WS */ #define FMC_WS_WSCNT BITS(0, 2) /*!< wait state counter */ /* FMC_KEY */ #define FMC_KEY_KEY BITS(0, 31) /*!< FMC_CTL unlock key bits */ /* FMC_OBKEY */ #define FMC_OBKEY_OBKEY BITS(0, 31) /*!< option bytes unlock key bits */ /* FMC_STAT */ #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ #define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ #define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */ #define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ /* FMC_CTL */ #define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ #define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */ #define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */ #define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ #define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ #define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ #define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */ #define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ #define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ /* FMC_ADDR */ #define FMC_ADDR0_ADDR BITS(0, 31) /*!< Flash erase/program command address bits */ /* FMC_OBSTAT */ #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ #define FMC_OBSTAT_USER BITS(2, 9) /*!< store USER of option bytes block after system reset */ #define FMC_OBSTAT_DATA BITS(10, 25) /*!< store DATA of option bytes block after system reset. */ /* FMC_WP */ #define FMC_WP_WP BITS(0, 31) /*!< store WP of option bytes block after system reset */ /* FMC_WSEN */ #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ /* FMC_PID */ #define FMC_PID_PID BITS(0, 31) /*!< product ID bits */ /* constants definitions */ /* define the FMC bit position and its register index offset */ #define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) #define FMC_BIT_POS(val) ((uint32_t)(val)&0x1FU) #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) #define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) #define FMC_BIT_POS1(val) ((uint32_t)(val)&0x1FU) #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) /* configuration register */ #define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */ #define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */ #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ /* fmc state */ typedef enum { FMC_READY, /*!< the operation has been completed */ FMC_BUSY, /*!< the operation is in progress */ FMC_PGERR, /*!< program error */ FMC_WPERR, /*!< erase/program protection error */ FMC_TOERR, /*!< timeout error */ } fmc_state_enum; /* FMC interrupt enable */ typedef enum { FMC_INT_END = FMC_CTL_ENDIE, /*!< enable FMC end of program interrupt */ FMC_INT_ERR = FMC_CTL_ERRIE, /*!< enable FMC error interrupt */ } fmc_int_enum; /* FMC flags */ typedef enum { FMC_FLAG_BUSY = FMC_STAT_BUSY, /*!< FMC busy flag */ FMC_FLAG_PGERR = FMC_STAT_PGERR, /*!< FMC operation error flag */ FMC_FLAG_WPERR = FMC_STAT_WPERR, /*!< FMC erase/program protection error flag */ FMC_FLAG_END = FMC_STAT_ENDF, /*!< FMC end of operation flag */ } fmc_flag_enum; /* FMC interrupt flags */ typedef enum { FMC_INT_FLAG_PGERR = FMC_STAT_PGERR, /*!< FMC operation error interrupt flag */ FMC_INT_FLAG_WPERR = FMC_STAT_WPERR, /*!< FMC erase/program protection error interrupt flag */ FMC_INT_FLAG_END = FMC_STAT_ENDF, /*!< FMC end of operation interrupt flag */ } fmc_interrupt_flag_enum; /* unlock key */ #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ /* FMC wait state counter */ #define WS_WSCNT(regval) (BITS(0, 2) & ((uint32_t)(regval))) #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ /* option bytes software/hardware free watch dog timer */ #define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ #define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ /* option bytes reset or not entering deep sleep mode */ #define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ #define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ /* option bytes reset or not entering standby mode */ #define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ #define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ /* option bytes boot bank value */ #define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ #define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ /* read protect configure */ #define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ #define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ /* OB_SPC */ #define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ #define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ /* OB_USER */ #define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ #define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ /* OB_WP0 */ #define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ /* OB_WP1 */ #define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ /* OB_WP2 */ #define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ /* OB_WP3 */ #define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ /* option bytes write protection */ #define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ #define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ #define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ #define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ #define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ #define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ #define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ #define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ #define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ #define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ #define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ #define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ #define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ #define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ #define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ #define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ #define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ #define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ #define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ #define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ #define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ #define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ #define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ #define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ #define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ #define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ #define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ #define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ #define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ #define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ /* FMC timeout */ #define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ /* FMC BANK address */ #define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ #define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/ /* function declarations */ /* FMC main memory programming functions */ /* set the FMC wait state counter */ void fmc_wscnt_set(uint32_t wscnt); /* unlock the main FMC operation */ void fmc_unlock(void); /* lock the main FMC operation */ void fmc_lock(void); /* FMC erase page */ fmc_state_enum fmc_page_erase(uint32_t page_address); /* FMC erase whole chip */ fmc_state_enum fmc_mass_erase(void); /* FMC program a word at the corresponding address */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); /* FMC program a half word at the corresponding address */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); /* FMC option bytes programming functions */ /* unlock the option byte operation */ void ob_unlock(void); /* lock the option byte operation */ void ob_lock(void); /* erase the FMC option byte */ fmc_state_enum ob_erase(void); /* enable write protection */ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); /* configure security protection */ fmc_state_enum ob_security_protection_config(uint8_t ob_spc); /* program the FMC user option byte */ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); /* program the FMC data option byte */ fmc_state_enum ob_data_program(uint32_t address, uint8_t data); /* get OB_USER in register FMC_OBSTAT */ uint8_t ob_user_get(void); /* get OB_DATA in register FMC_OBSTAT */ uint16_t ob_data_get(void); /* get the FMC option byte write protection */ uint32_t ob_write_protection_get(void); /* get FMC option byte security protection state */ FlagStatus ob_spc_get(void); /* FMC interrupts and flags management functions */ /* enable FMC interrupt */ void fmc_interrupt_enable(fmc_int_enum interrupt); /* disable FMC interrupt */ void fmc_interrupt_disable(fmc_int_enum interrupt); /* check flag is set or not */ FlagStatus fmc_flag_get(fmc_flag_enum flag); /* clear the FMC flag */ void fmc_flag_clear(fmc_flag_enum flag); /* get FMC interrupt flag state */ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); /* clear FMC interrupt flag state */ void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); /* return the FMC state */ fmc_state_enum fmc_state_get(void); /* check FMC ready or not */ fmc_state_enum fmc_ready_wait(uint32_t timeout); #endif /* GD32VF103_FMC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_fwdgt.h ================================================ /*! \file gd32vf103_fwdgt.h \brief definitions for the FWDGT \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_FWDGT_H #define GD32VF103_FWDGT_H #include "gd32vf103.h" /* FWDGT definitions */ #define FWDGT FWDGT_BASE /*!< FWDGT base address */ /* registers definitions */ #define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ #define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ #define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ #define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ /* bits definitions */ /* FWDGT_CTL */ #define FWDGT_CTL_CMD BITS(0, 15) /*!< FWDGT command value */ /* FWDGT_PSC */ #define FWDGT_PSC_PSC BITS(0, 2) /*!< FWDGT prescaler divider value */ /* FWDGT_RLD */ #define FWDGT_RLD_RLD BITS(0, 11) /*!< FWDGT counter reload value */ /* FWDGT_STAT */ #define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ #define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ /* constants definitions */ /* psc register value */ #define PSC_PSC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) #define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ #define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ #define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ #define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ #define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ #define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ #define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ /* control value */ #define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ #define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ #define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ #define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ /* FWDGT timeout value */ #define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ #define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ /* FWDGT flag definitions */ #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ /* function declarations */ /* enable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_enable(void); /* disable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ void fwdgt_enable(void); /* reload the counter of FWDGT */ void fwdgt_counter_reload(void); /* configure counter reload value, and prescaler divider value */ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); /* get flag state of FWDGT */ FlagStatus fwdgt_flag_get(uint16_t flag); #endif /* GD32VF103_FWDGT_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_gpio.h ================================================ /*! \file gd32vf103_gpio.h \brief definitions for the GPIO \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_GPIO_H #define GD32VF103_GPIO_H #include "gd32vf103.h" /* GPIOx(x=A,B,C,D,E) definitions */ #define GPIOA (GPIO_BASE + 0x00000000U) #define GPIOB (GPIO_BASE + 0x00000400U) #define GPIOC (GPIO_BASE + 0x00000800U) #define GPIOD (GPIO_BASE + 0x00000C00U) #define GPIOE (GPIO_BASE + 0x00001000U) /* AFIO definitions */ #define AFIO AFIO_BASE /* registers definitions */ /* GPIO registers definitions */ #define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ #define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ /* AFIO registers definitions */ #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ #define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ #define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ #define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ #define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ /* bits definitions */ /* GPIO_CTL0 */ #define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ #define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ #define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ #define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ #define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ #define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ #define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ #define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ #define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ #define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ #define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ #define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ #define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ #define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ #define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ #define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ /* GPIO_CTL1 */ #define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ #define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ #define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ #define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ #define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ #define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ #define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ #define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ #define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ #define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ #define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ #define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ #define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ #define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ #define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ #define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ /* GPIO_ISTAT */ #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ #define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ #define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ #define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ #define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ #define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ #define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ #define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ #define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ #define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ #define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ #define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ #define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ #define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ #define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ #define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ /* GPIO_OCTL */ #define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ #define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ #define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ #define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ #define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ #define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ #define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ #define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ #define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ #define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ #define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ #define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ #define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ #define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ #define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ #define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ /* GPIO_BOP */ #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ #define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ #define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ #define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ #define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ #define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ #define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ #define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ #define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ #define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ #define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ #define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ #define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ #define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ #define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ #define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ #define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ #define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ #define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ #define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ #define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ #define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ #define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ #define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ #define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ #define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ #define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ #define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ #define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ #define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ #define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ #define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ /* GPIO_BC */ #define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ #define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ #define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ #define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ #define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ #define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ #define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ #define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ #define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ #define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ #define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ #define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ #define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ #define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ #define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ #define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ /* GPIO_LOCK */ #define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ #define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ #define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ #define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ #define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ #define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ #define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ #define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ #define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ #define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ #define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ #define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ #define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ #define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ #define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ #define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ #define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ /* AFIO_EC */ #define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ #define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ #define AFIO_EC_EOE BIT(7) /*!< event output enable */ /* AFIO_PCF0 */ #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ #define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ #define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ #define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ #define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ #define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ #define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ #define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ /* AFIO_EXTISS0 */ #define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ #define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ #define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ #define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ /* AFIO_EXTISS1 */ #define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ #define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ #define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ #define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ /* AFIO_EXTISS2 */ #define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ #define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ #define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ #define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ /* AFIO_EXTISS3 */ #define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ #define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ #define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ #define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ /* AFIO_PCF1 */ #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ /* constants definitions */ typedef FlagStatus bit_status; /* GPIO mode values set */ #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) #define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) /* GPIO mode definitions */ #define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ #define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ #define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ #define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ #define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ #define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ #define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ #define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ /* GPIO output max speed value */ #define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ #define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ #define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ /* GPIO event output port definitions */ #define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ #define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ #define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ #define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ #define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ /* GPIO output port source definitions */ #define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ #define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ #define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ #define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ #define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ /* GPIO event output pin definitions */ #define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ #define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ #define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ #define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ #define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ #define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ #define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ #define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ #define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ #define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ #define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ #define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ #define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ #define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ #define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ #define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ /* GPIO output pin source definitions */ #define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ #define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ #define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ #define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ #define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ #define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ #define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ #define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ #define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ #define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ #define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ #define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ #define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ #define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ #define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ #define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ /* GPIO pin definitions */ #define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ #define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ #define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ #define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ #define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ #define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ #define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ #define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ #define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ #define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ #define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ #define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ #define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ #define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ /* GPIO remap definitions */ #define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ #define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ #define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ #define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ #define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ #define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ #define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ #define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ #define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ #define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ #define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ #define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ #define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ #define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ #define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */ #define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */ #define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ #define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */ #define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */ #define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< JTAG-DP,but without NJTRST */ #define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */ #define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */ #define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */ #define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ /* function declarations */ /* reset GPIO port */ void gpio_deinit(uint32_t gpio_periph); /* reset alternate function I/O(AFIO) */ void gpio_afio_deinit(void); /* GPIO parameter initialization */ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); /* set GPIO pin bit */ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); /* reset GPIO pin bit */ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); /* write data to the specified GPIO pin */ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); /* write data to the specified GPIO port */ void gpio_port_write(uint32_t gpio_periph, uint16_t data); /* get GPIO pin input status */ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); /* get GPIO port input status */ uint16_t gpio_input_port_get(uint32_t gpio_periph); /* get GPIO pin output status */ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); /* get GPIO port output status */ uint16_t gpio_output_port_get(uint32_t gpio_periph); /* configure GPIO pin remap */ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); /* select GPIO pin exti sources */ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); /* configure GPIO pin event output */ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); /* enable GPIO pin event output */ void gpio_event_output_enable(void); /* disable GPIO pin event output */ void gpio_event_output_disable(void); /* lock GPIO pin bit */ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); #endif /* GD32VF103_GPIO_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_i2c.h ================================================ /*! \file gd32vf103_i2c.h \brief definitions for the I2C \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_I2C_H #define GD32VF103_I2C_H #include "gd32vf103.h" /* I2Cx(x=0,1) definitions */ #define I2C0 I2C_BASE /*!< I2C0 base address */ #define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ /* registers definitions */ #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ #define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ /* bits definitions */ /* I2Cx_CTL0 */ #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ #define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ #define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ #define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ #define I2C_CTL0_START BIT(8) /*!< start generation */ #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ #define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ #define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ #define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ /* I2Cx_CTL1 */ #define I2C_CTL1_I2CCLK BITS(0, 5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ #define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ /* I2Cx_SADDR0 */ #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ #define I2C_SADDR0_ADDRESS BITS(1, 7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ #define I2C_SADDR0_ADDRESS_H BITS(8, 9) /*!< highest two bits of a 10-bit address */ #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ /* I2Cx_SADDR1 */ #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ #define I2C_SADDR1_ADDRESS2 BITS(1, 7) /*!< second I2C address for the slave in dual-address mode */ /* I2Cx_DATA */ #define I2C_DATA_TRB BITS(0, 7) /*!< 8-bit data register */ /* I2Cx_STAT0 */ #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ #define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ #define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ #define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ #define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ #define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ #define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ #define I2C_STAT0_BERR BIT(8) /*!< bus error */ #define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ #define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ #define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ #define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ #define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ #define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ /* I2Cx_STAT1 */ #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ #define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ #define I2C_STAT1_PECV BITS(8, 15) /*!< packet error checking value */ /* I2Cx_CKCFG */ #define I2C_CKCFG_CLKC BITS(0, 11) /*!< clock control register in fast/standard mode (master mode) */ #define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ /* I2Cx_RT */ #define I2C_RT_RISETIME BITS(0, 5) /*!< maximum rise time in fast/standard mode (Master mode) */ /* I2Cx_FMPCFG */ #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ /* constants definitions */ /* define the I2C bit position and its register index offset */ #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset)&0xFFFFU) >> 6))) #define I2C_BIT_POS(val) ((uint32_t)(val)&0x1FU) #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) #define I2C_BIT_POS2(val) (((uint32_t)(val)&0x1F0000U) >> 16) /* register offset */ #define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ #define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ #define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ /* I2C flags */ typedef enum { /* flags in STAT0 register */ I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ /* flags in STAT1 register */ I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ } i2c_flag_enum; /* I2C interrupt flags */ typedef enum { /* interrupt flags in CTL1 register */ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ } i2c_interrupt_flag_enum; /* I2C interrupt enable or disable */ typedef enum { /* interrupt in CTL1 register */ I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ } i2c_interrupt_enum; /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ /* SMBus/I2C mode switch and SMBus type selection */ #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ /* I2C transfer direction */ #define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ #define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ #define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ /* I2C POAP position*/ #define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ /* I2C dual-address mode switch */ #define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ #define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ /* whether or not to stretch SCL low */ #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ #define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ /* whether or not to response to a general call */ #define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ /* software reset I2C */ #define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ #define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ /* I2C DMA mode configure */ /* DMA mode switch */ #define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ /* flag indicating DMA last transfer */ #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ /* I2C PEC configure */ /* PEC enable */ #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ #define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ /* PEC transfer */ #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ /* I2C SMBus configure */ /* issue or not alert through SMBA pin */ #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ /* ARP protocol in SMBus switch */ #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ /* transmit I2C data */ #define DATA_TRANS(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0)) /* receive I2C data */ #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ #define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ #define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ /* address mode for the I2C slave */ #define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ #define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ /* function declarations */ /* reset I2C */ void i2c_deinit(uint32_t i2c_periph); /* configure I2C clock */ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); /* configure I2C address */ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); /* SMBus type selection */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); /* configure I2C POAP position */ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); /* master sends slave address */ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); /* enable dual-address mode */ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); /* disable dual-address mode */ void i2c_dualaddr_disable(uint32_t i2c_periph); /* enable I2C */ void i2c_enable(uint32_t i2c_periph); /* disable I2C */ void i2c_disable(uint32_t i2c_periph); /* generate a START condition on I2C bus */ void i2c_start_on_bus(uint32_t i2c_periph); /* generate a STOP condition on I2C bus */ void i2c_stop_on_bus(uint32_t i2c_periph); /* I2C transmit data function */ void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); /* I2C receive data function */ uint8_t i2c_data_receive(uint32_t i2c_periph); /* enable I2C DMA mode */ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); /* configure whether next DMA EOT is DMA last transfer or not */ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); /* whether to stretch SCL low when data is not ready in slave mode */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); /* whether or not to response to a general call */ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); /* software reset I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); /* I2C PEC calculation on or off */ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); /* I2C whether to transfer PEC value */ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); /* packet error checking value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph); /* I2C issue alert through SMBA pin */ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); /* I2C ARP protocol in SMBus switch */ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); /* check I2C flag is set or not */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); /* clear I2C flag */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); /* enable I2C interrupt */ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); /* disable I2C interrupt */ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); /* check I2C interrupt flag */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); /* clear I2C interrupt flag */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32VF103_I2C_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_libopt.h ================================================ /*! \file gd32vf103_libopt.h \brief library optional for gd32vf103 \version 2019-6-5, V1.0.0, demo for GD32VF103 */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_LIBOPT_H #define GD32VF103_LIBOPT_H #ifdef __cplusplus extern "C" { #endif #include "gd32vf103.h" #include "gd32vf103_adc.h" #include "gd32vf103_bkp.h" #include "gd32vf103_crc.h" #include "gd32vf103_dac.h" #include "gd32vf103_dbg.h" #include "gd32vf103_dma.h" #include "gd32vf103_eclic.h" #include "gd32vf103_exmc.h" #include "gd32vf103_exti.h" #include "gd32vf103_fmc.h" #include "gd32vf103_fwdgt.h" #include "gd32vf103_gpio.h" #include "gd32vf103_i2c.h" #include "gd32vf103_pmu.h" #include "gd32vf103_rcu.h" #include "gd32vf103_rtc.h" #include "gd32vf103_spi.h" #include "gd32vf103_timer.h" #include "gd32vf103_usart.h" #include "gd32vf103_wwdgt.h" #ifdef __cplusplus } #endif #endif /* GD32VF103_LIBOPT_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_pmu.h ================================================ /*! \file gd32vf103_pmu.h \brief definitions for the PMU \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_PMU_H #define GD32VF103_PMU_H #include "gd32vf103.h" /* PMU definitions */ #define PMU PMU_BASE /*!< PMU base address */ /* registers definitions */ #define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ /* bits definitions */ /* PMU_CTL */ #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ #define PMU_CTL_LVDT BITS(5, 7) /*!< low voltage detector threshold */ #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ /* PMU_CS */ #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ #define PMU_CS_STBF BIT(1) /*!< standby flag */ #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ /* constants definitions */ /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5, 7) & ((uint32_t)(regval) << 5)) #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ /* PMU flag definitions */ #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ /* PMU ldo definitions */ #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ /* PMU flag reset definitions */ #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ /* PMU command constants definitions */ #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ /* function declarations */ /* reset PMU registers */ void pmu_deinit(void); /* select low voltage detector threshold */ void pmu_lvd_select(uint32_t lvdt_n); /* disable PMU lvd */ void pmu_lvd_disable(void); /* set PMU mode */ /* PMU work at sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); /* PMU work at deepsleep mode */ void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); /* PMU work at standby mode */ void pmu_to_standbymode(uint8_t standbymodecmd); /* enable PMU wakeup pin */ void pmu_wakeup_pin_enable(void); /* disable PMU wakeup pin */ void pmu_wakeup_pin_disable(void); /* backup related functions */ /* enable write access to the registers in backup domain */ void pmu_backup_write_enable(void); /* disable write access to the registers in backup domain */ void pmu_backup_write_disable(void); /* flag functions */ /* get flag state */ FlagStatus pmu_flag_get(uint32_t flag); /* clear flag bit */ void pmu_flag_clear(uint32_t flag_reset); #endif /* GD32VF103_PMU_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rcu.h ================================================ /*! \file gd32vf103_rcu.h \brief definitions for the RCU \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_RCU_H #define GD32VF103_RCU_H #include "gd32vf103.h" /* define clock source */ #define SEL_IRC8M ((uint16_t)0U) #define SEL_HXTAL ((uint16_t)1U) #define SEL_PLL ((uint16_t)2U) /* RCU definitions */ #define RCU RCU_BASE /* registers definitions */ #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ /* bits definitions */ /* RCU_CTL */ #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ #define RCU_CTL_IRC8MADJ BITS(3, 7) /*!< high speed internal oscillator clock trim adjust value */ #define RCU_CTL_IRC8MCALIB BITS(8, 15) /*!< high speed internal oscillator calibration value register */ #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ #define RCU_CFG0_SCS BITS(0, 1) /*!< system clock switch */ #define RCU_CFG0_SCSS BITS(2, 3) /*!< system clock switch status */ #define RCU_CFG0_AHBPSC BITS(4, 7) /*!< AHB prescaler selection */ #define RCU_CFG0_APB1PSC BITS(8, 10) /*!< APB1 prescaler selection */ #define RCU_CFG0_APB2PSC BITS(11, 13) /*!< APB2 prescaler selection */ #define RCU_CFG0_ADCPSC BITS(14, 15) /*!< ADC prescaler selection */ #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ #define RCU_CFG0_PLLMF BITS(18, 21) /*!< PLL clock multiplication factor */ #define RCU_CFG0_USBFSPSC BITS(22, 23) /*!< USBFS clock prescaler selection */ #define RCU_CFG0_CKOUT0SEL BITS(24, 27) /*!< CKOUT0 clock source selection */ #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ /* RCU_INT */ #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ /* RCU_APB2RST */ #define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ #define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ #define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ #define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ #define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ #define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ /* RCU_APB1RST */ #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ #define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ #define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ #define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ #define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ /* RCU_AHBEN */ #define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ #define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ #define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ #define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ /* RCU_APB2EN */ #define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ #define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ #define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ #define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ #define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ #define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ #define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ #define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ /* RCU_APB1EN */ #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ #define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ #define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ #define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ #define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ #define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ /* RCU_BDCTL */ #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ #define RCU_BDCTL_RTCSRC BITS(8, 9) /*!< RTC clock entry selection */ #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ /* RCU_RSTSCK */ #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ /* RCU_AHBRST */ #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ /* RCU_CFG1 */ #define RCU_CFG1_PREDV0 BITS(0, 3) /*!< PREDV0 division factor */ #define RCU_CFG1_PREDV1 BITS(4, 7) /*!< PREDV1 division factor */ #define RCU_CFG1_PLL1MF BITS(8, 11) /*!< PLL1 clock multiplication factor */ #define RCU_CFG1_PLL2MF BITS(12, 15) /*!< PLL2 clock multiplication factor */ #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ /* RCU_DSV */ #define RCU_DSV_DSLPVS BITS(0, 1) /*!< deep-sleep mode voltage select */ /* constants definitions */ /* define the peripheral clock enable bit position and its register index offset */ #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) #define RCU_BIT_POS(val) ((uint32_t)(val)&0x1FU) /* register offset */ /* peripherals enable */ #define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ #define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ #define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ /* peripherals reset */ #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ #define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ #define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ #define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ /* clock control */ #define CTL_REG_OFFSET 0x00U /*!< control register offset */ #define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ /* clock stabilization and stuck interrupt */ #define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ /* configuration register */ #define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ /* peripheral clock enable */ typedef enum { /* AHB peripherals */ RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ /* APB1 peripherals */ RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ /* APB2 peripherals */ RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ } rcu_periph_enum; /* peripheral clock enable when sleep mode*/ typedef enum { /* AHB peripherals */ RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ } rcu_periph_sleep_enum; /* peripherals reset */ typedef enum { /* AHB peripherals */ RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ /* APB1 peripherals */ RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ /* APB2 peripherals */ RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ } rcu_periph_reset_enum; /* clock stabilization and peripheral reset flags */ typedef enum { /* clock stabilization flags */ RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ /* reset source flags */ RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ } rcu_flag_enum; /* clock stabilization and ckm interrupt flags */ typedef enum { RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ } rcu_int_flag_enum; /* clock stabilization and stuck interrupt flags clear */ typedef enum { RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ } rcu_int_flag_clear_enum; /* clock stabilization interrupt enable or disable */ typedef enum { RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ } rcu_int_enum; /* oscillator types */ typedef enum { RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ } rcu_osci_type_enum; /* rcu clock frequency */ typedef enum { CK_SYS = 0, /*!< system clock */ CK_AHB, /*!< AHB clock */ CK_APB1, /*!< APB1 clock */ CK_APB2, /*!< APB2 clock */ } rcu_clock_freq_enum; /* RCU_CFG0 register bit define */ /* system clock source select */ #define CFG0_SCS(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ /* system clock source select status */ #define CFG0_SCSS(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ /* AHB prescaler selection */ #define CFG0_AHBPSC(regval) (BITS(4, 7) & ((uint32_t)(regval) << 4)) #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ /* APB1 prescaler selection */ #define CFG0_APB1PSC(regval) (BITS(8, 10) & ((uint32_t)(regval) << 8)) #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ /* APB2 prescaler selection */ #define CFG0_APB2PSC(regval) (BITS(11, 13) & ((uint32_t)(regval) << 11)) #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ /* ADC prescaler select */ #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ /* PLL clock source selection */ #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ #define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ /* PLL clock multiplication factor */ #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ #define CFG0_PLLMF(regval) (BITS(18, 21) & ((uint32_t)(regval) << 18)) #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ /* USBFS prescaler select */ #define CFG0_USBPSC(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ /* CKOUT0 clock source selection */ #define CFG0_CKOUT0SEL(regval) (BITS(24, 27) & ((uint32_t)(regval) << 24)) #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected */ #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ /* RTC clock entry selection */ #define BDCTL_RTCSRC(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ /* PREDV0 division factor */ #define CFG1_PREDV0(regval) (BITS(0, 3) & ((uint32_t)(regval) << 0)) #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ #define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ #define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ #define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ #define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ #define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ #define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ #define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ #define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ #define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ #define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ #define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ #define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ /* PREDV1 division factor */ #define CFG1_PREDV1(regval) (BITS(4, 7) & ((uint32_t)(regval) << 4)) #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ #define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ #define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ #define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ #define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ #define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ #define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ /* PLL1 clock multiplication factor */ #define CFG1_PLL1MF(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8)) #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ #define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ #define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ #define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ #define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ #define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ #define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ /* PLL2 clock multiplication factor */ #define CFG1_PLL2MF(regval) (BITS(12, 15) & ((uint32_t)(regval) << 12)) #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ #define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ /* PREDV0 input clock source selection */ #define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ /* I2S1 clock source selection */ #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ /* I2S2 clock source selection */ #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ /* deep-sleep mode voltage */ #define DSV_DSLPVS(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0)) #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ /* function declarations */ /* initialization, peripheral clock enable/disable functions */ /* deinitialize the RCU */ void rcu_deinit(void); /* enable the peripherals clock */ void rcu_periph_clock_enable(rcu_periph_enum periph); /* disable the peripherals clock */ void rcu_periph_clock_disable(rcu_periph_enum periph); /* enable the peripherals clock when sleep mode */ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); /* disable the peripherals clock when sleep mode */ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); /* reset the peripherals */ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); /* disable reset the peripheral */ void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); /* reset the BKP domain */ void rcu_bkp_reset_enable(void); /* disable the BKP domain reset */ void rcu_bkp_reset_disable(void); /* clock configuration functions */ /* configure the system clock source */ void rcu_system_clock_source_config(uint32_t ck_sys); /* get the system clock source */ uint32_t rcu_system_clock_source_get(void); /* configure the AHB prescaler selection */ void rcu_ahb_clock_config(uint32_t ck_ahb); /* configure the APB1 prescaler selection */ void rcu_apb1_clock_config(uint32_t ck_apb1); /* configure the APB2 prescaler selection */ void rcu_apb2_clock_config(uint32_t ck_apb2); /* configure the CK_OUT0 clock source and divider */ void rcu_ckout0_config(uint32_t ckout0_src); /* configure the PLL clock source selection and PLL multiply factor */ void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); /* configure the PREDV0 division factor and clock source */ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); /* configure the PREDV1 division factor */ void rcu_predv1_config(uint32_t predv1_div); /* configure the PLL1 clock */ void rcu_pll1_config(uint32_t pll_mul); /* configure the PLL2 clock */ void rcu_pll2_config(uint32_t pll_mul); /* peripheral clock configuration functions */ /* configure the ADC division factor */ void rcu_adc_clock_config(uint32_t adc_psc); /* configure the USBD/USBFS prescaler factor */ void rcu_usb_clock_config(uint32_t usb_psc); /* configure the RTC clock source selection */ void rcu_rtc_clock_config(uint32_t rtc_clock_source); /* configure the I2S1 clock source selection */ void rcu_i2s1_clock_config(uint32_t i2s_clock_source); /* configure the I2S2 clock source selection */ void rcu_i2s2_clock_config(uint32_t i2s_clock_source); /* interrupt & flag functions */ /* get the clock stabilization and periphral reset flags */ FlagStatus rcu_flag_get(rcu_flag_enum flag); /* clear the reset flag */ void rcu_all_reset_flag_clear(void); /* get the clock stabilization interrupt and ckm flags */ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); /* clear the interrupt flags */ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); /* enable the stabilization interrupt */ void rcu_interrupt_enable(rcu_int_enum stab_int); /* disable the stabilization interrupt */ void rcu_interrupt_disable(rcu_int_enum stab_int); /* oscillator configuration functions */ /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); /* turn on the oscillator */ void rcu_osci_on(rcu_osci_type_enum osci); /* turn off the oscillator */ void rcu_osci_off(rcu_osci_type_enum osci); /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); /* enable the HXTAL clock monitor */ void rcu_hxtal_clock_monitor_enable(void); /* disable the HXTAL clock monitor */ void rcu_hxtal_clock_monitor_disable(void); /* set the IRC8M adjust value */ void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); /* set the deep sleep mode voltage */ void rcu_deepsleep_voltage_set(uint32_t dsvol); /* get the system clock, bus and peripheral clock frequency */ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); #endif /* GD32VF103_RCU_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_rtc.h ================================================ /*! \file gd32vf103_rtc.h \brief definitions for the RTC \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_RTC_H #define GD32VF103_RTC_H #include "gd32vf103.h" /* RTC definitions */ #define RTC RTC_BASE /* registers definitions */ #define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ #define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ #define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ #define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ #define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ #define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ #define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ #define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ #define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ #define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ /* bits definitions */ /* RTC_INTEN */ #define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ #define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ #define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ /* RTC_CTL */ #define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ #define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ #define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ #define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ #define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ /* RTC_PSCH */ #define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ /* RTC_PSCL */ #define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ /* RTC_DIVH */ #define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ /* RTC_DIVL */ #define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ /* RTC_CNTH */ #define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ /* RTC_CNTL */ #define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ /* RTC_ALRMH */ #define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ /* RTC_ALRML */ #define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ /* constants definitions */ /* RTC interrupt enable or disable definitions */ #define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ #define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ #define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ /* RTC interrupt flag definitions */ #define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ #define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ #define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ /* RTC flag definitions */ #define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ #define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ #define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ #define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ #define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ /* function declarations */ /* initialization functions */ /* enter RTC configuration mode */ void rtc_configuration_mode_enter(void); /* exit RTC configuration mode */ void rtc_configuration_mode_exit(void); /* set RTC counter value */ void rtc_counter_set(uint32_t cnt); /* set RTC prescaler value */ void rtc_prescaler_set(uint32_t psc); /* operation functions */ /* wait RTC last write operation finished flag set */ void rtc_lwoff_wait(void); /* wait RTC registers synchronized flag set */ void rtc_register_sync_wait(void); /* set RTC alarm value */ void rtc_alarm_config(uint32_t alarm); /* get RTC counter value */ uint32_t rtc_counter_get(void); /* get RTC divider value */ uint32_t rtc_divider_get(void); /* flag & interrupt functions */ /* get RTC flag status */ FlagStatus rtc_flag_get(uint32_t flag); /* clear RTC flag status */ void rtc_flag_clear(uint32_t flag); /* get RTC interrupt flag status */ FlagStatus rtc_interrupt_flag_get(uint32_t flag); /* clear RTC interrupt flag status */ void rtc_interrupt_flag_clear(uint32_t flag); /* enable RTC interrupt */ void rtc_interrupt_enable(uint32_t interrupt); /* disable RTC interrupt */ void rtc_interrupt_disable(uint32_t interrupt); #endif /* GD32VF103_RTC_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_spi.h ================================================ /*! \file gd32vf103_spi.h \brief definitions for the SPI \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_SPI_H #define GD32VF103_SPI_H #include "gd32vf103.h" /* SPIx(x=0,1,2) definitions */ #define SPI0 (SPI_BASE + 0x0000F800U) #define SPI1 SPI_BASE #define SPI2 (SPI_BASE + 0x00000400U) /* SPI registers definitions */ #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ #define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ #define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ #define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ #define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ #define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ #define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ #define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ /* bits definitions */ /* SPI_CTL0 */ #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ #define SPI_CTL0_PSC BITS(3, 5) /*!< master clock prescaler selection */ #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ #define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ #define SPI_CTL0_RO BIT(10) /*!< receive only */ #define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ #define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ #define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ #define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ #define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ /* SPI_CTL1 */ #define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ #define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ #define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ #define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ #define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ #define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ #define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ /* SPI_STAT */ #define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ #define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ #define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ #define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ #define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ #define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ #define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ #define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ #define SPI_STAT_FERR BIT(8) /*!< format error bit */ /* SPI_DATA */ #define SPI_DATA_DATA BITS(0, 15) /*!< data transfer register */ /* SPI_CRCPOLY */ #define SPI_CRCPOLY_CRCPOLY BITS(0, 15) /*!< CRC polynomial value */ /* SPI_RCRC */ #define SPI_RCRC_RCRC BITS(0, 15) /*!< RX CRC value */ /* SPI_TCRC */ #define SPI_TCRC_TCRC BITS(0, 15) /*!< TX CRC value */ /* SPI_I2SCTL */ #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ #define SPI_I2SCTL_DTLEN BITS(1, 2) /*!< data length */ #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ #define SPI_I2SCTL_I2SSTD BITS(4, 5) /*!< I2S standard selection */ #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ #define SPI_I2SCTL_I2SOPMOD BITS(8, 9) /*!< I2S operation mode */ #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ /* SPI_I2SPSC */ #define SPI_I2SPSC_DIV BITS(0, 7) /*!< dividing factor for the prescaler */ #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ /* constants definitions */ /* SPI and I2S parameter struct definitions */ typedef struct { uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transtype */ uint32_t frame_size; /*!< SPI frame size */ uint32_t nss; /*!< SPI NSS control by handware or software */ uint32_t endian; /*!< SPI big endian or little endian */ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ uint32_t prescale; /*!< SPI prescale factor */ } spi_parameter_struct; /* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ #define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ /* SPI bidirectional transfer direction */ #define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ #define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ /* SPI transmit type */ #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ /* SPI frame size */ #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ /* SPI NSS control mode */ #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ #define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ /* SPI transmit way */ #define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ #define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ /* SPI clock phase and polarity */ #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ /* SPI clock prescale factor */ #define CTL0_PSC(regval) (BITS(3, 5) & ((uint32_t)(regval) << 3)) #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ #define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ #define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ #define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ #define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ #define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ /* I2S audio sample rate */ #define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ #define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ #define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ #define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ #define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ #define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ #define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ #define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ /* I2S frame format */ #define I2SCTL_DTLEN(regval) (BITS(1, 2) & ((uint32_t)(regval) << 1)) #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ /* I2S master clock output */ #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ /* I2S operation mode */ #define I2SCTL_I2SOPMOD(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ /* I2S standard */ #define I2SCTL_I2SSTD(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ #define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ /* I2S clock polarity */ #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ /* SPI DMA constants definitions */ #define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ #define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ /* SPI CRC constants definitions */ #define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ #define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ /* SPI/I2S interrupt enable/disable constants definitions */ #define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ #define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ #define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ /* SPI/I2S interrupt flag constants definitions */ #define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ #define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ #define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ #define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ #define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ #define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ /* SPI/I2S flag definitions */ #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ #define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ #define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ #define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ #define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ #define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ #define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ #define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ #define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ #define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ /* function declarations */ /* SPI/I2S deinitialization and initialization functions */ /* reset SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); /* initialize the parameters of SPI struct with the default values */ void spi_struct_para_init(spi_parameter_struct *spi_struct); /* initialize SPI parameter */ void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); /* enable SPI */ void spi_enable(uint32_t spi_periph); /* disable SPI */ void spi_disable(uint32_t spi_periph); /* initialize I2S parameter */ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); /* configure I2S prescaler */ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); /* enable I2S */ void i2s_enable(uint32_t spi_periph); /* disable I2S */ void i2s_disable(uint32_t spi_periph); /* NSS functions */ /* enable SPI NSS output */ void spi_nss_output_enable(uint32_t spi_periph); /* disable SPI NSS output */ void spi_nss_output_disable(uint32_t spi_periph); /* SPI NSS pin high level in software mode */ void spi_nss_internal_high(uint32_t spi_periph); /* SPI NSS pin low level in software mode */ void spi_nss_internal_low(uint32_t spi_periph); /* DMA communication */ /* enable SPI DMA */ void spi_dma_enable(uint32_t spi_periph, uint8_t dma); /* disable SPI DMA */ void spi_dma_disable(uint32_t spi_periph, uint8_t dma); /* normal mode communication */ /* configure SPI/I2S data frame format */ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); /* SPI transmit data */ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); /* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); /* configure SPI bidirectional transfer direction */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); /* SPI CRC functions */ /* set SPI CRC polynomial */ void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); /* get SPI CRC polynomial */ uint16_t spi_crc_polynomial_get(uint32_t spi_periph); /* turn on SPI CRC function */ void spi_crc_on(uint32_t spi_periph); /* turn off SPI CRC function */ void spi_crc_off(uint32_t spi_periph); /* SPI next data is CRC value */ void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); /* SPI TI mode functions */ /* enable SPI TI mode */ void spi_ti_mode_enable(uint32_t spi_periph); /* disable SPI TI mode */ void spi_ti_mode_disable(uint32_t spi_periph); /* SPI NSS pulse mode functions */ /* enable SPI NSS pulse mode */ void spi_nssp_mode_enable(uint32_t spi_periph); /* disable SPI NSS pulse mode */ void spi_nssp_mode_disable(uint32_t spi_periph); /* flag and interrupt functions */ /* enable SPI and I2S interrupt */ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); /* disable SPI and I2S interrupt */ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); /* get SPI and I2S interrupt status */ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); /* get SPI and I2S flag status */ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); /* clear SPI CRC error flag status */ void spi_crc_error_clear(uint32_t spi_periph); #endif /* GD32VF103_SPI_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_timer.h ================================================ /*! \file gd32vf103_timer.h \brief definitions for the TIMER \version 2019-06-05, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_TIMER_H #define GD32VF103_TIMER_H #include "gd32vf103.h" /* TIMERx(x=0..13) definitions */ #define TIMER0 (TIMER_BASE + 0x00012C00U) #define TIMER1 (TIMER_BASE + 0x00000000U) #define TIMER2 (TIMER_BASE + 0x00000400U) #define TIMER3 (TIMER_BASE + 0x00000800U) #define TIMER4 (TIMER_BASE + 0x00000C00U) #define TIMER5 (TIMER_BASE + 0x00001000U) #define TIMER6 (TIMER_BASE + 0x00001400U) /* registers definitions */ #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ #define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ #define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ #define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ #define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ #define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ /* bits definitions */ /* TIMER_CTL0 */ #define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ #define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ #define TIMER_CTL0_UPS BIT(2) /*!< update source */ #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ #define TIMER_CTL0_CAM BITS(5, 6) /*!< center-aligned mode selection */ #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ #define TIMER_CTL0_CKDIV BITS(8, 9) /*!< clock division */ /* TIMER_CTL1 */ #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ #define TIMER_CTL1_MMC BITS(4, 6) /*!< master mode control */ #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ #define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ #define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ #define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ #define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ /* TIMER_SMCFG */ #define TIMER_SMCFG_SMC BITS(0, 2) /*!< slave mode control */ #define TIMER_SMCFG_TRGS BITS(4, 6) /*!< trigger selection */ #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ #define TIMER_SMCFG_ETFC BITS(8, 11) /*!< external trigger filter control */ #define TIMER_SMCFG_ETPSC BITS(12, 13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ #define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ #define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ #define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ #define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ #define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ #define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ /* TIMER_INTF */ #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ #define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ #define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ #define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ #define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ #define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ #define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ #define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ #define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ #define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ #define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ /* TIMER_SWEVG */ #define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ #define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ #define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ #define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ #define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ #define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ #define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ #define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ /* TIMER_CHCTL0 */ /* output compare mode */ #define TIMER_CHCTL0_CH0MS BITS(0, 1) /*!< channel 0 mode selection */ #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ #define TIMER_CHCTL0_CH0COMCTL BITS(4, 6) /*!< channel 0 output compare control */ #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ #define TIMER_CHCTL0_CH1MS BITS(8, 9) /*!< channel 1 mode selection */ #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ #define TIMER_CHCTL0_CH1COMCTL BITS(12, 14) /*!< channel 1 output compare control */ #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ /* input capture mode */ #define TIMER_CHCTL0_CH0CAPPSC BITS(2, 3) /*!< channel 0 input capture prescaler */ #define TIMER_CHCTL0_CH0CAPFLT BITS(4, 7) /*!< channel 0 input capture filter control */ #define TIMER_CHCTL0_CH1CAPPSC BITS(10, 11) /*!< channel 1 input capture prescaler */ #define TIMER_CHCTL0_CH1CAPFLT BITS(12, 15) /*!< channel 1 input capture filter control */ /* TIMER_CHCTL1 */ /* output compare mode */ #define TIMER_CHCTL1_CH2MS BITS(0, 1) /*!< channel 2 mode selection */ #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ #define TIMER_CHCTL1_CH2COMCTL BITS(4, 6) /*!< channel 2 output compare control */ #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ #define TIMER_CHCTL1_CH3MS BITS(8, 9) /*!< channel 3 mode selection */ #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ #define TIMER_CHCTL1_CH3COMCTL BITS(12, 14) /*!< channel 3 output compare control */ #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ /* input capture mode */ #define TIMER_CHCTL1_CH2CAPPSC BITS(2, 3) /*!< channel 2 input capture prescaler */ #define TIMER_CHCTL1_CH2CAPFLT BITS(4, 7) /*!< channel 2 input capture filter control */ #define TIMER_CHCTL1_CH3CAPPSC BITS(10, 11) /*!< channel 3 input capture prescaler */ #define TIMER_CHCTL1_CH3CAPFLT BITS(12, 15) /*!< channel 3 input capture filter control */ /* TIMER_CHCTL2 */ #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ #define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ #define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ #define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ #define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ #define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ #define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ #define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ #define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ #define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ /* TIMER_CNT */ #define TIMER_CNT_CNT BITS(0, 15) /*!< 16 bit timer counter */ /* TIMER_PSC */ #define TIMER_PSC_PSC BITS(0, 15) /*!< prescaler value of the counter clock */ /* TIMER_CAR */ #define TIMER_CAR_CARL BITS(0, 15) /*!< 16 bit counter auto reload value */ /* TIMER_CREP */ #define TIMER_CREP_CREP BITS(0, 7) /*!< counter repetition value */ /* TIMER_CH0CV */ #define TIMER_CH0CV_CH0VAL BITS(0, 15) /*!< 16 bit capture/compare value of channel 0 */ /* TIMER_CH1CV */ #define TIMER_CH1CV_CH1VAL BITS(0, 15) /*!< 16 bit capture/compare value of channel 1 */ /* TIMER_CH2CV */ #define TIMER_CH2CV_CH2VAL BITS(0, 15) /*!< 16 bit capture/compare value of channel 2 */ /* TIMER_CH3CV */ #define TIMER_CH3CV_CH3VAL BITS(0, 15) /*!< 16 bit capture/compare value of channel 3 */ /* TIMER_CCHP */ #define TIMER_CCHP_DTCFG BITS(0, 7) /*!< dead time configure */ #define TIMER_CCHP_PROT BITS(8, 9) /*!< complementary register protect control */ #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ #define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ #define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ /* TIMER_DMACFG */ #define TIMER_DMACFG_DMATA BITS(0, 4) /*!< DMA transfer access start address */ #define TIMER_DMACFG_DMATC BITS(8, 12) /*!< DMA transfer count */ /* TIMER_DMATB */ #define TIMER_DMATB_DMATB BITS(0, 15) /*!< DMA transfer buffer address */ /* constants definitions */ /* TIMER init parameter struct definitions */ typedef struct { uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ uint32_t period; /*!< period value */ uint16_t clockdivision; /*!< clock division value */ uint8_t repetitioncounter; /*!< the counter repetition value */ } timer_parameter_struct; /* break parameter struct definitions */ typedef struct { uint16_t runoffstate; /*!< run mode off-state */ uint16_t ideloffstate; /*!< idle mode off-state */ uint16_t deadtime; /*!< dead time */ uint16_t breakpolarity; /*!< break polarity */ uint16_t outputautostate; /*!< output automatic enable */ uint16_t protectmode; /*!< complementary register protect control */ uint16_t breakstate; /*!< break enable */ } timer_break_parameter_struct; /* channel output parameter struct definitions */ typedef struct { uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocnpolarity; /*!< channel complementary output polarity */ uint16_t ocidlestate; /*!< idle state of channel output */ uint16_t ocnidlestate; /*!< idle state of channel complementary output */ } timer_oc_parameter_struct; /* channel input parameter struct definitions */ typedef struct { uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icfilter; /*!< channel input capture filter control */ } timer_ic_parameter_struct; /* TIMER interrupt enable or disable */ #define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ #define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ /* TIMER interrupt flag */ #define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ #define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ #define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ #define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ #define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ #define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ #define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ #define TIMER_INT_FLAG_BRK TIMER_INT_BRK /* TIMER flag */ #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ #define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ #define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ #define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ /* TIMER DMA source enable */ #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ #define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ #define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ #define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ #define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ /* channel DMA request source selection */ #define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ /* DMA access base address */ #define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ #define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ #define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ /* DMA access burst length */ #define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ #define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ /* TIMER software event generation source */ #define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ #define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ #define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ #define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ #define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ #define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ #define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ /* center-aligned mode selection */ #define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ #define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ #define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ /* specify division ratio between TIMER clock and dead-time and sampling clock */ #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ #define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ #define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ /* update source */ #define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ #define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ /* idle mode off-state configure */ #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ /* break input polarity */ #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ #define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ /* output automatic enable */ #define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ /* complementary register protect control */ #define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ #define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ /* break input enable */ #define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ /* TIMER channel n(n=0,1,2,3) */ #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4)) */ #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4)) */ #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4)) */ #define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4)) */ /* channel enable state */ #define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ #define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ /* channel complementary output enable state */ #define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ #define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ /* channel output polarity */ #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ /* channel complementary output polarity */ #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ /* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ /* idle state of channel complementary output */ #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ /* channel output compare mode */ #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ /* channel output compare shadow enable */ #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ /* channel output compare fast enable */ #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ /* channel output compare clear enable */ #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ /* channel control shadow register update control */ #define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ #define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ /* channel input capture polarity */ #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ /* TIMER input capture selection */ #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ /* channel input capture prescaler */ #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ /* trigger selection */ #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ #define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ /* master mode control */ #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ #define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ #define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ /* master slave mode selection */ #define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ /* external trigger prescaler */ #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ /* external trigger polarity */ #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ /* channel 0 trigger input selection */ #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ #define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ /* TIMERx(x=0..4) write CHxVAL register selection */ #define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ #define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ /* function declarations */ /* TIMER timebase */ /* deinit a timer */ void timer_deinit(uint32_t timer_periph); /* initialize TIMER init parameter struct */ void timer_struct_para_init(timer_parameter_struct *initpara); /* initialize TIMER counter */ void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); /* enable a timer */ void timer_enable(uint32_t timer_periph); /* disable a timer */ void timer_disable(uint32_t timer_periph); /* enable the auto reload shadow function */ void timer_auto_reload_shadow_enable(uint32_t timer_periph); /* disable the auto reload shadow function */ void timer_auto_reload_shadow_disable(uint32_t timer_periph); /* enable the update event */ void timer_update_event_enable(uint32_t timer_periph); /* disable the update event */ void timer_update_event_disable(uint32_t timer_periph); /* set TIMER counter alignment mode */ void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); /* set TIMER counter up direction */ void timer_counter_up_direction(uint32_t timer_periph); /* set TIMER counter down direction */ void timer_counter_down_direction(uint32_t timer_periph); /* configure TIMER prescaler */ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); /* configure TIMER repetition register value */ void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); /* configure TIMER autoreload register value */ void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); /* configure TIMER counter register value */ void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); /* read TIMER counter value */ uint32_t timer_counter_read(uint32_t timer_periph); /* read TIMER prescaler value */ uint16_t timer_prescaler_read(uint32_t timer_periph); /* configure TIMER single pulse mode */ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ void timer_update_source_config(uint32_t timer_periph, uint32_t update); /* TIMER DMA and event */ /* enable the TIMER DMA */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma); /* disable the TIMER DMA */ void timer_dma_disable(uint32_t timer_periph, uint16_t dma); /* channel DMA request source selection */ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); /* configure the TIMER DMA transfer */ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); /* software generate events */ void timer_event_software_generate(uint32_t timer_periph, uint16_t event); /* TIMER channel complementary protection */ /* initialize TIMER break parameter struct */ void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); /* configure TIMER break function */ void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); /* enable TIMER break function */ void timer_break_enable(uint32_t timer_periph); /* disable TIMER break function */ void timer_break_disable(uint32_t timer_periph); /* enable TIMER output automatic function */ void timer_automatic_output_enable(uint32_t timer_periph); /* disable TIMER output automatic function */ void timer_automatic_output_disable(uint32_t timer_periph); /* enable or disable TIMER primary output function */ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); /* enable or disable channel capture/compare control shadow register */ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); /* configure TIMER channel control shadow register update control */ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); /* TIMER channel output */ /* initialize TIMER channel output parameter struct */ void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); /* configure TIMER channel output function */ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); /* configure TIMER channel output compare mode */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); /* configure TIMER channel output pulse value */ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); /* configure TIMER channel output shadow function */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); /* configure TIMER channel output fast function */ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); /* configure TIMER channel output clear function */ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); /* configure TIMER channel output polarity */ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); /* configure TIMER channel complementary output polarity */ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); /* configure TIMER channel enable state */ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); /* configure TIMER channel complementary output enable state */ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); /* TIMER channel input */ /* initialize TIMER channel input parameter struct */ void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); /* configure TIMER input capture parameter */ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); /* configure TIMER channel input capture prescaler value */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); /* read TIMER channel capture compare register value */ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); /* configure TIMER input pwm capture function */ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); /* configure TIMER hall sensor mode */ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); /* TIMER master and slave mode */ /* select TIMER input trigger source */ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); /* select TIMER master mode output trigger source */ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); /* select TIMER slave mode */ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); /* configure TIMER master slave mode */ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); /* configure TIMER external trigger input */ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER quadrature decoder mode */ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); /* configure TIMER internal clock mode */ void timer_internal_clock_config(uint32_t timer_periph); /* configure TIMER the internal trigger as external clock input */ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); /* configure TIMER the external trigger as external clock input */ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 0 */ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 1 */ void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* disable TIMER the external clock mode 1 */ void timer_external_clock_mode1_disable(uint32_t timer_periph); /* TIMER interrupt and flag */ /* enable the TIMER interrupt */ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); /* disable the TIMER interrupt */ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); /* get TIMER interrupt flag */ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); /* clear TIMER interrupt flag */ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); /* get TIMER flag */ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); /* clear TIMER flag */ void timer_flag_clear(uint32_t timer_periph, uint32_t flag); #endif /* GD32VF103_TIMER_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_usart.h ================================================ /*! \file gd32vf103_usart.h \brief definitions for the USART \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-09-18, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_USART_H #define GD32VF103_USART_H #include "gd32vf103.h" /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ #define USART1 USART_BASE /*!< USART1 base address */ #define USART2 (USART_BASE + (0x00000400U)) /*!< USART2 base address */ #define UART3 (USART_BASE + (0x00000800U)) /*!< UART3 base address */ #define UART4 (USART_BASE + (0x00000C00U)) /*!< UART4 base address */ #define USART0 (USART_BASE + (0x0000F400U)) /*!< USART0 base address */ /* registers definitions */ #define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ #define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ #define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ #define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ #define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ #define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ #define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ /* bits definitions */ /* USARTx_STAT */ #define USART_STAT_PERR BIT(0) /*!< parity error flag */ #define USART_STAT_FERR BIT(1) /*!< frame error flag */ #define USART_STAT_NERR BIT(2) /*!< noise error flag */ #define USART_STAT_ORERR BIT(3) /*!< overrun error */ #define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ #define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ #define USART_STAT_TC BIT(6) /*!< transmission complete */ #define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ #define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ /* USARTx_DATA */ #define USART_DATA_DATA BITS(0, 8) /*!< transmit or read data value */ /* USARTx_BAUD */ #define USART_BAUD_FRADIV BITS(0, 3) /*!< fraction part of baud-rate divider */ #define USART_BAUD_INTDIV BITS(4, 15) /*!< integer part of baud-rate divider */ /* USARTx_CTL0 */ #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ #define USART_CTL0_REN BIT(2) /*!< receiver enable */ #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ #define USART_CTL0_PM BIT(9) /*!< parity mode */ #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ #define USART_CTL0_WL BIT(12) /*!< word length */ #define USART_CTL0_UEN BIT(13) /*!< USART enable */ /* USARTx_CTL1 */ #define USART_CTL1_ADDR BITS(0, 3) /*!< address of USART */ #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ #define USART_CTL1_CLEN BIT(8) /*!< CK length */ #define USART_CTL1_CPH BIT(9) /*!< CK phase */ #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ #define USART_CTL1_STB BITS(12, 13) /*!< STOP bits length */ #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ /* USARTx_CTL2 */ #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ /* USARTx_GP */ #define USART_GP_PSC BITS(0, 7) /*!< prescaler value for dividing the system clock */ #define USART_GP_GUAT BITS(8, 15) /*!< guard time value in smartcard mode */ /* constants definitions */ /* define the USART bit position and its register index offset */ #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) #define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) #define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) /* register offset */ #define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ #define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ #define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ #define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ /* USART flags */ typedef enum { /* flags in STAT register */ USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ } usart_flag_enum; /* USART interrupt flags */ typedef enum { /* interrupt flags in CTL0 register */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ /* interrupt flags in CTL1 register */ USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ /* interrupt flags in CTL2 register */ USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ } usart_interrupt_flag_enum; /* USART interrupt enable or disable */ typedef enum { /* interrupt in CTL0 register */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ /* interrupt in CTL1 register */ USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ /* interrupt in CTL2 register */ USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ } usart_interrupt_enum; /* USART receiver configure */ #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ /* USART transmitter configure */ #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ /* USART parity bits definitions */ #define CTL0_PM(regval) (BITS(9, 10) & ((uint32_t)(regval) << 9)) #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ /* USART wakeup method in mute mode */ #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) #define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ #define USART_WM_ADDR CTL0_WM(1) /*!< address match */ /* USART word length definitions */ #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ /* USART stop bits definitions */ #define CTL1_STB(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ /* USART LIN break frame length */ #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ /* USART CK length */ #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ /* USART clock phase */ #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ /* USART clock polarity */ #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ /* USART DMA request for receive configure */ #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ /* USART DMA request for transmission configure */ #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ /* USART RTS configure */ #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ /* USART CTS configure */ #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ /* USART IrDA low-power enable */ #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ /* function declarations */ /* initialization functions */ /* reset USART */ void usart_deinit(uint32_t usart_periph); /* configure USART baud rate value */ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); /* configure USART parity function */ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); /* configure USART word length */ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); /* configure USART stop bit length */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); /* USART normal mode communication */ /* enable USART */ void usart_enable(uint32_t usart_periph); /* disable USART */ void usart_disable(uint32_t usart_periph); /* configure USART transmitter */ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); /* configure USART receiver */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); /* USART transmit data function */ void usart_data_transmit(uint32_t usart_periph, uint32_t data); /* USART receive data function */ uint16_t usart_data_receive(uint32_t usart_periph); /* multi-processor communication */ /* configure address of the USART */ void usart_address_config(uint32_t usart_periph, uint8_t addr); /* enable mute mode */ void usart_mute_mode_enable(uint32_t usart_periph); /* disable mute mode */ void usart_mute_mode_disable(uint32_t usart_periph); /* configure wakeup method in mute mode */ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); /* LIN mode communication */ /* LIN mode enable */ void usart_lin_mode_enable(uint32_t usart_periph); /* LIN mode disable */ void usart_lin_mode_disable(uint32_t usart_periph); /* LIN break detection length */ void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); /* send break frame */ void usart_send_break(uint32_t usart_periph); /* half-duplex communication */ /* half-duplex enable */ void usart_halfduplex_enable(uint32_t usart_periph); /* half-duplex disable */ void usart_halfduplex_disable(uint32_t usart_periph); /* synchronous communication */ /* clock enable */ void usart_synchronous_clock_enable(uint32_t usart_periph); /* clock disable */ void usart_synchronous_clock_disable(uint32_t usart_periph); /* configure usart synchronous mode parameters */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); /* smartcard communication */ /* guard time value configure in smartcard mode */ void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut); /* smartcard mode enable */ void usart_smartcard_mode_enable(uint32_t usart_periph); /* smartcard mode disable */ void usart_smartcard_mode_disable(uint32_t usart_periph); /* NACK enable in smartcard mode */ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); /* NACK disable in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); /* IrDA communication */ /* enable IrDA mode */ void usart_irda_mode_enable(uint32_t usart_periph); /* disable IrDA mode */ void usart_irda_mode_disable(uint32_t usart_periph); /* configure the peripheral clock prescaler */ void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); /* configure IrDA low-power */ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); /* hardware flow communication */ /* configure hardware flow control RTS */ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); /* configure hardware flow control CTS */ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); /* configure USART DMA for reception */ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); /* configure USART DMA for transmission */ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); /* flag functions */ /* get flag in STAT register */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); /* clear flag in STAT register */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); /* interrupt functions */ /* enable USART interrupt */ void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt); /* disable USART interrupt */ void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt); /* get USART interrupt and flag status */ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); /* clear interrupt flag in STAT register */ void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag); #endif /* GD32VF103_USART_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/gd32vf103_wwdgt.h ================================================ /*! \file gd32vf103_wwdgt.h \brief definitions for the WWDGT \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef GD32VF103_WWDGT_H #define GD32VF103_WWDGT_H #include "gd32vf103.h" /* WWDGT definitions */ #define WWDGT WWDGT_BASE /*!< WWDGT base address */ /* registers definitions */ #define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ #define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ #define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ /* bits definitions */ /* WWDGT_CTL */ #define WWDGT_CTL_CNT BITS(0, 6) /*!< WWDGT counter value */ #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ /* WWDGT_CFG */ #define WWDGT_CFG_WIN BITS(0, 6) /*!< WWDGT counter window value */ #define WWDGT_CFG_PSC BITS(7, 8) /*!< WWDGT prescaler divider value */ #define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ /* WWDGT_STAT */ #define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ /* constants definitions */ #define CFG_PSC(regval) (BITS(7, 8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ #define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ #define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ /* function declarations */ /* reset the window watchdog timer configuration */ void wwdgt_deinit(void); /* start the window watchdog timer counter */ void wwdgt_enable(void); /* configure the window watchdog timer counter value */ void wwdgt_counter_update(uint16_t counter_value); /* configure counter value, window value, and prescaler divider value */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); /* enable early wakeup interrupt of WWDGT */ void wwdgt_interrupt_enable(void); /* check early wakeup interrupt state of WWDGT */ FlagStatus wwdgt_flag_get(void); /* clear early wakeup interrupt state of WWDGT */ void wwdgt_flag_clear(void); #endif /* GD32VF103_WWDGT_H */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/n200_func.h ================================================ /* See LICENSE file for licence details */ #ifndef N200_FUNC_H #define N200_FUNC_H #include #define ECLIC_GROUP_LEVEL0_PRIO4 0 #define ECLIC_GROUP_LEVEL1_PRIO3 1 #define ECLIC_GROUP_LEVEL2_PRIO2 2 #define ECLIC_GROUP_LEVEL3_PRIO1 3 #define ECLIC_GROUP_LEVEL4_PRIO0 4 void pmp_open_all_space(void); void switch_m2u_mode(void); uint32_t get_mtime_freq(void); uint32_t mtime_lo(void); uint32_t mtime_hi(void); uint64_t get_mtime_value(void); uint64_t get_instret_value(void); uint64_t get_cycle_value(void); uint32_t __attribute__((noinline)) measure_cpu_freq(size_t n); /* ECLIC relevant functions */ void eclic_init(uint32_t num_irq); uint64_t get_timer_value(void); void eclic_enable_interrupt(uint32_t source); void eclic_disable_interrupt(uint32_t source); void eclic_set_pending(uint32_t source); void eclic_clear_pending(uint32_t source); void eclic_set_intctrl(uint32_t source, uint8_t intctrl); uint8_t eclic_get_intctrl(uint32_t source); void eclic_set_intattr(uint32_t source, uint8_t intattr); uint8_t eclic_get_intattr(uint32_t source); void eclic_set_cliccfg(uint8_t cliccfg); uint8_t eclic_get_cliccfg(void); void eclic_set_mth(uint8_t mth); uint8_t eclic_get_mth(void); /* sets nlbits */ void eclic_set_nlbits(uint8_t nlbits); /* get nlbits */ uint8_t eclic_get_nlbits(void); void eclic_set_irq_lvl(uint32_t source, uint8_t lvl); uint8_t eclic_get_irq_lvl(uint32_t source); void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs); uint8_t eclic_get_irq_lvl_abs(uint32_t source); uint8_t eclic_set_irq_priority(uint32_t source, uint8_t priority); uint8_t eclic_get_irq_priority(uint32_t source); void eclic_mode_enable(void); void eclic_set_vmode(uint32_t source); void eclic_set_nonvmode(uint32_t source); void eclic_set_level_trig(uint32_t source); void eclic_set_posedge_trig(uint32_t source); void eclic_set_negedge_trig(uint32_t source); #endif ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/nuclei_sdk_soc.h ================================================ // See LICENSE for license details. #ifndef _NUCLEI_SDK_SOC_H #define _NUCLEI_SDK_SOC_H #ifdef __cplusplus extern "C" { #endif #include "gd32vf103.h" #include "gd32vf103_libopt.h" #ifdef __cplusplus } #endif #endif ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Include/system_gd32vf103.h ================================================ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /******************************************************************************* * @file system_gd32vf103.h * @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for * Device gd32vf103 * @version V1.00 * @date 7. Jan 2020 ******************************************************************************/ #ifndef __SYSTEM_GD32VF103_H__ #define __SYSTEM_GD32VF103_H__ #ifdef __cplusplus extern "C" { #endif #include extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** \brief Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit(void); /** \brief Update SystemCoreClock variable. Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ extern void SystemCoreClockUpdate(void); /** * \brief Register an exception handler for exception code EXCn */ extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler); /** * \brief Get current exception handler for exception code EXCn */ extern unsigned long Exception_Get_EXC(uint32_t EXCn); /** * \brief Initialize eclic config */ extern void ECLIC_Init(void); /** * \brief Initialize a specific IRQ and register the handler * \details * This function set vector mode, trigger mode and polarity, interrupt level and priority, * assign handler for specific IRQn. */ extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler); #ifdef __cplusplus } #endif #endif /* __SYSTEM_GD32VF103_H__ */ ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_core.c ================================================ /*! \file drv_usb_core.c \brief USB core driver which can operate in host and device mode \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "drv_usb_core.h" #include "drv_usb_hw.h" /*! \brief config USB core to soft reset \param[in] usb_regs: USB core registers \param[out] none \retval none */ static void usb_core_reset(usb_core_regs *usb_regs) { /* enable core soft reset */ usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; /* wait for the core to be soft reset */ while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) ; /* wait for addtional 3 PHY clocks */ usb_udelay(3); } /*! \brief config USB core basic \param[in] usb_basic: pointer to usb capabilities \param[in] usb_regs: USB core registers \param[in] usb_core: USB core \param[out] none \retval operation status */ usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core) { uint32_t i = 0, reg_base = 0; /* config USB default transfer mode as FIFO mode */ usb_basic->transfer_mode = USB_USE_FIFO; /* USB default speed is full-speed */ usb_basic->core_speed = USB_SPEED_FULL; usb_basic->core_enum = usb_core; switch (usb_core) { case USB_CORE_ENUM_HS: reg_base = USBHS_REG_BASE; /* set the host channel numbers */ usb_basic->num_pipe = USBHS_MAX_CHANNEL_COUNT; /* set the device endpoint numbers */ usb_basic->num_ep = USBHS_MAX_EP_COUNT; #ifdef USB_ULPI_PHY_ENABLED usb_basic->phy_itf = USB_ULPI_PHY; #else usb_basic->phy_itf = USB_EMBEDDED_PHY; #endif /* USB_ULPI_PHY_ENABLED */ #ifdef USB_HS_INTERNAL_DMA_ENABLED bp->transfer_mode = USB_USE_DMA; #endif /* USB_HS_INTERNAL_DMA_ENABLED */ break; case USB_CORE_ENUM_FS: reg_base = USBFS_REG_BASE; /* set the host channel numbers */ usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; /* set the device endpoint numbers */ usb_basic->num_ep = USBFS_MAX_EP_COUNT; /* USBFS core use embedded physical layer */ usb_basic->phy_itf = USB_EMBEDDED_PHY; break; default: return USB_FAIL; } usb_basic->sof_enable = USB_SOF_OUTPUT; usb_basic->low_power = USB_LOW_POWER; /* assign main registers address */ *usb_regs = (usb_core_regs){.gr = (usb_gr *)(reg_base + USB_REG_OFFSET_CORE), .hr = (usb_hr *)(reg_base + USB_REG_OFFSET_HOST), .dr = (usb_dr *)(reg_base + USB_REG_OFFSET_DEV), .HPCS = (uint32_t *)(reg_base + USB_REG_OFFSET_PORT), .PWRCLKCTL = (uint32_t *)(reg_base + USB_REG_OFFSET_PWRCLKCTL)}; /* assign device endpoint registers address */ for (i = 0; i < usb_basic->num_ep; i++) { usb_regs->er_in[i] = (usb_erin *)(reg_base + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); usb_regs->er_out[i] = (usb_erout *)(reg_base + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); } /* assign host pipe registers address */ for (i = 0; i < usb_basic->num_pipe; i++) { usb_regs->pr[i] = (usb_pr *)(reg_base + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); usb_regs->DFIFO[i] = (uint32_t *)(reg_base + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); } return USB_OK; } /*! \brief initializes the USB controller registers and prepares the core device mode or host mode operation \param[in] bp: usb capabilities \param[in] core_regs: usb core registers \param[out] none \retval operation status */ usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs) { uint32_t reg_value = usb_regs->gr->GCCFG; /* disable USB global interrupt */ usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; if (USB_ULPI_PHY == usb_basic.phy_itf) { reg_value &= ~GCCFG_PWRON; if (usb_basic.sof_enable) { reg_value |= GCCFG_SOFOEN; } usb_regs->gr->GCCFG = GCCFG_SOFOEN; /* init the ULPI interface */ usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); #ifdef USBHS_EXTERNAL_VBUS_ENABLED /* use external VBUS driver */ usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; #else /* use internal VBUS driver */ usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; #endif /* soft reset the core */ usb_core_reset(usb_regs); } else { usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; /* soft reset the core */ usb_core_reset(usb_regs); /* active the transceiver and enable vbus sensing */ reg_value = GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; #ifndef VBUS_SENSING_ENABLED reg_value |= GCCFG_VBUSIG; #endif /* VBUS_SENSING_ENABLED */ /* enable SOF output */ if (usb_basic.sof_enable) { reg_value |= GCCFG_SOFOEN; } usb_regs->gr->GCCFG = reg_value; usb_mdelay(20); } if (USB_USE_DMA == usb_basic.transfer_mode) { usb_regs->gr->GAHBCS |= GAHBCS_DMAEN; usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; usb_regs->gr->GAHBCS |= DMA_INCR8; } #ifdef USE_OTG_MODE /* enable USB OTG features */ usb_regs->gr->GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; /* enable the USB wakeup and suspend interrupts */ usb_regs->gr->GINTF = 0xBFFFFFFFU; usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; #endif /* USE_OTG_MODE */ return USB_OK; } /*! \brief write a packet into the Tx FIFO associated with the endpoint \param[in] core_regs: usb core registers \param[in] src_buf: pointer to source buffer \param[in] fifo_num: FIFO number which is in (0..3) \param[in] byte_count: packet byte count \param[out] none \retval operation status */ usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count) { uint32_t word_count = (byte_count + 3U) / 4U; __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; while (word_count-- > 0) { *fifo = *((uint32_t *)src_buf); src_buf += 4U; } return USB_OK; } /*! \brief read a packet from the Rx FIFO associated with the endpoint \param[in] core_regs: usb core registers \param[in] dest_buf: pointer to destination buffer \param[in] byte_count: packet byte count \param[out] none \retval void type pointer */ void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) { uint32_t word_count = (byte_count + 3U) / 4U; __IO uint32_t *fifo = usb_regs->DFIFO[0]; while (word_count-- > 0) { *(uint32_t *)dest_buf = *fifo; dest_buf += 4U; } return ((void *)dest_buf); } /*! \brief flush a Tx FIFO or all Tx FIFOs \param[in] core_regs: pointer to usb core registers \param[in] fifo_num: FIFO number which is in (0..3) \param[out] none \retval operation status */ usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num) { usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; /* wait for Tx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) ; /* wait for 3 PHY clocks*/ usb_udelay(3); return USB_OK; } /*! \brief flush the entire Rx FIFO \param[in] core_regs: pointer to usb core registers \param[out] none \retval operation status */ usb_status usb_rxfifo_flush(usb_core_regs *usb_regs) { usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; /* wait for Rx FIFO flush bit is set */ while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) ; /* wait for 3 PHY clocks */ usb_udelay(3); return USB_OK; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_dev.c ================================================ /*! \file drv_usb_dev.c \brief USB device mode low level driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "drv_usb_dev.h" #include "drv_usb_core.h" #include "drv_usb_hw.h" #include "gd32vf103_libopt.h" /* endpoint 0 max packet length */ static const uint8_t EP0_MAXLEN[4] = {[DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8}; #ifdef USB_FS_CORE /* USB endpoint Tx FIFO size */ static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = {(uint16_t)TX0_FIFO_FS_SIZE, (uint16_t)TX1_FIFO_FS_SIZE, (uint16_t)TX2_FIFO_FS_SIZE, (uint16_t)TX3_FIFO_FS_SIZE}; #elif defined(USB_HS_CORE) uint16_t USBHS_TX_FIFO_SIZE[USBHS_MAX_EP_COUNT] = {(uint16_t)TX0_FIFO_HS_SIZE, (uint16_t)TX1_FIFO_HS_SIZE, (uint16_t)TX2_FIFO_HS_SIZE, (uint16_t)TX3_FIFO_HS_SIZE, (uint16_t)TX4_FIFO_HS_SIZE, (uint16_t)TX5_FIFO_HS_SIZE}; #endif /* USBFS_CORE */ /*! \brief initialize USB core registers for device mode \param[in] udev: pointer to usb device \param[out] none \retval operation status */ usb_status usb_devcore_init(usb_core_driver *udev) { uint32_t i, ram_addr = 0; /* force to peripheral mode */ udev->regs.gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); udev->regs.gr->GUSBCS |= GUSBCS_FDM; // udev->regs.gr->GUSBCS &= ~(GUSBCS_FHM); /* restart the Phy Clock (maybe don't need to...) */ *udev->regs.PWRCLKCTL = 0U; /* config periodic frame interval to default value */ udev->regs.dr->DCFG &= ~DCFG_EOPFT; udev->regs.dr->DCFG |= FRAME_INTERVAL_80; udev->regs.dr->DCFG &= ~DCFG_DS; #ifdef USB_FS_CORE if (udev->bp.core_enum == USB_CORE_ENUM_FS) { /* set full-speed PHY */ udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; /* set Rx FIFO size */ udev->regs.gr->GRFLEN = RX_FIFO_FS_SIZE; /* set endpoint 0 Tx FIFO length and RAM address */ udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_FS_SIZE << 16) | ((uint32_t)RX_FIFO_FS_SIZE); ram_addr = RX_FIFO_FS_SIZE; /* set endpoint 1 to 3's Tx FIFO length and RAM address */ for (i = 1; i < USBFS_MAX_EP_COUNT; i++) { ram_addr += USBFS_TX_FIFO_SIZE[i - 1]; udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U) | ram_addr; } } #endif #ifdef USB_HS_CORE if (udev->bp.core == USB_CORE_HS) { if (udev->bp.core_phy == USB_ULPI_PHY) { udev->regs.dr->DCFG |= USB_SPEED_EXP_HIGH; } else { /* set High speed phy in Full speed mode */ udev->regs.dr->DCFG |= USB_SPEED_EXP_FULL; } /* Set Rx FIFO size */ udev->regs.gr->GRFLEN &= ~GRFLEN_RXFD; udev->regs.gr->GRFLEN |= RX_FIFO_HS_SIZE; /* Set endpoint 0 Tx FIFO length and RAM address */ udev->regs.gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)TX0_FIFO_HS_SIZE << 16) | RX_FIFO_HS_SIZE; ram_addr = RX_FIFO_HS_SIZE; /* Set endpoint 1 to 3's Tx FIFO length and RAM address */ for (i = 1; i < USBHS_MAX_EP_COUNT; i++) { ram_addr += USBHS_TX_FIFO_SIZE[i - 1]; udev->regs.gr->DIEPTFLEN[i - 1] = ((uint32_t)USBHS_TX_FIFO_SIZE[i] << 16) | ram_addr; } } #endif /* make sure all FIFOs are flushed */ /* flush all Tx FIFOs */ usb_txfifo_flush(&udev->regs, 0x10); /* flush entire Rx FIFO */ usb_rxfifo_flush(&udev->regs); /* clear all pending device interrupts */ udev->regs.dr->DIEPINTEN = 0U; udev->regs.dr->DOEPINTEN = 0U; udev->regs.dr->DAEPINT = 0xFFFFFFFFU; udev->regs.dr->DAEPINTEN = 0U; /* configure all IN/OUT endpoints */ for (i = 0; i < udev->bp.num_ep; i++) { if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; } else { udev->regs.er_in[i]->DIEPCTL = 0U; } /* set IN endpoint transfer length to 0 */ udev->regs.er_in[i]->DIEPLEN = 0U; /* clear all pending IN endpoint interrupts */ udev->regs.er_in[i]->DIEPINTF = 0xFFU; if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; } else { udev->regs.er_out[i]->DOEPCTL = 0U; } /* set OUT endpoint transfer length to 0 */ udev->regs.er_out[i]->DOEPLEN = 0U; /* clear all pending OUT endpoint interrupts */ udev->regs.er_out[i]->DOEPINTF = 0xFFU; } usb_devint_enable(udev); return USB_OK; } /*! \brief enable the USB device mode interrupts \param[in] udev: pointer to usb device \param[out] none \retval operation status */ usb_status usb_devint_enable(usb_core_driver *udev) { /* clear any pending USB OTG interrupts */ udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; /* clear any pending interrupts */ udev->regs.gr->GINTF = 0xBFFFFFFFU; /* enable the USB wakeup and suspend interrupts */ udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; /* enable device_mode-related interrupts */ if (USB_USE_FIFO == udev->bp.transfer_mode) { udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; } udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_MFIE; #ifdef VBUS_SENSING_ENABLED udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; #endif /* VBUS_SENSING_ENABLED */ /* enable USB global interrupt */ udev->regs.gr->GAHBCS |= GAHBCS_GINTEN; return USB_OK; } /*! \brief config the USB device to be disconnected \param[in] udev: pointer to usb device \param[out] none \retval operation status */ void usb_dev_disconnect(usb_core_driver *udev) { udev->regs.dr->DCTL |= DCTL_SD; } /*! \brief config the USB device to be connected \param[in] udev: pointer to usb device \param[out] none \retval operation status */ void usb_dev_connect(usb_core_driver *udev) { udev->regs.dr->DCTL &= ~DCTL_SD; } /*! \brief set the USB device address \param[in] udev: pointer to usb device \param[in] dev_addr: device address for setting \param[out] none \retval operation status */ void usb_devaddr_set(usb_core_driver *udev, uint8_t dev_addr) { udev->regs.dr->DCFG &= ~DCFG_DAR; udev->regs.dr->DCFG |= dev_addr << 4; } /*! \brief active the usb transaction \param[in] udev: pointer to usb device \param[in] transc: the usb transaction \param[out] none \retval status */ usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; __IO uint32_t epinten = 0U; /* get the endpoint number */ uint8_t ep_num = transc->ep_addr.num; /* enable endpoint interrupt number */ if (transc->ep_addr.dir) { reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; epinten = 1 << ep_num; } else { reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; epinten = 1 << (16 + ep_num); } /* if the endpoint is not active, need change the endpoint control register */ if (!(*reg_addr & DEPCTL_EPACT)) { *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); /* set endpoint maximum packet length */ if (0U == ep_num) { *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; } else { *reg_addr |= transc->max_len; } /* activate endpoint */ *reg_addr |= (transc->ep_type << 18) | (ep_num << 22) | DEPCTL_SD0PID | DEPCTL_EPACT; } #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED if ((ep_num == 1) && (udev->bp.core == USB_HS_CORE_ID)) { udev->regs.dr->DEP1INTEN |= epinten; } else #endif { /* enable the interrupts for this endpoint */ udev->regs.dr->DAEPINTEN |= epinten; } return USB_OK; } /*! \brief deactive the usb transaction \param[in] udev: pointer to usb device \param[in] transc: the usb transaction \param[out] none \retval status */ usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) { uint32_t epinten = 0U; uint8_t ep_num = transc->ep_addr.num; /* disable endpoint interrupt number */ if (transc->ep_addr.dir) { epinten = 1 << ep_num; udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; } else { epinten = 1 << (ep_num + 16); udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; } #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED if ((ep_num == 1) && (udev->bp.core == USB_CORE_HS)) { udev->regs.dr->DEP1INTEN &= ~epinten; } else #endif { /* disable the interrupts for this endpoint */ udev->regs.dr->DAEPINTEN &= ~epinten; } return USB_OK; } /*! \brief configure usb transaction to start IN transfer \param[in] udev: pointer to usb device \param[in] transc: the usb IN transaction \param[out] none \retval status */ usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc) { usb_status status = USB_OK; uint8_t ep_num = transc->ep_addr.num; __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); /* zero length packet or endpoint 0 */ if (0U == transc->xfer_len) { /* set transfer packet count to 1 */ eplen |= 1 << 19; } else { /* set transfer packet count */ if (0U == ep_num) { transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); eplen |= 1 << 19; } else { eplen |= ((transc->xfer_len - 1 + transc->max_len) / transc->max_len) << 19; } /* set endpoint transfer length */ eplen |= transc->xfer_len; if (transc->ep_type == USB_EPTYPE_ISOC) { eplen |= DIEPLEN_MCNT; } } udev->regs.er_in[ep_num]->DIEPLEN = eplen; if (USB_USE_DMA == udev->bp.transfer_mode) { udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; } if (transc->ep_type == USB_EPTYPE_ISOC) { if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8) & 0x1) { epctl |= DEPCTL_SD1PID; } else { epctl |= DEPCTL_SD0PID; } } /* enable the endpoint and clear the NAK */ epctl |= DEPCTL_CNAK | DEPCTL_EPEN; udev->regs.er_in[ep_num]->DIEPCTL = epctl; if (transc->ep_type != USB_EPTYPE_ISOC) { /* enable the Tx FIFO empty interrupt for this endpoint */ if (transc->xfer_len > 0) { udev->regs.dr->DIEPFEINTEN |= 1 << ep_num; } } else { usb_txfifo_write(&udev->regs, transc->xfer_buf, ep_num, transc->xfer_len); } return status; } /*! \brief configure usb transaction to start OUT transfer \param[in] udev: pointer to usb device \param[in] transc: the usb OUT transaction \param[out] none \retval status */ usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc) { usb_status status = USB_OK; uint8_t ep_num = transc->ep_addr.num; uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); /* zero length packet or endpoint 0 */ if ((0U == transc->xfer_len) || (0U == ep_num)) { /* set the transfer length to max packet size */ eplen |= transc->max_len; /* set the transfer packet count to 1 */ eplen |= 1U << 19; } else { /* configure the transfer size and packet count as follows: * pktcnt = N * xfersize = N * maxpacket */ uint32_t packet_count = (transc->xfer_len + transc->max_len - 1) / transc->max_len; eplen |= packet_count << 19; eplen |= packet_count * transc->max_len; } udev->regs.er_out[ep_num]->DOEPLEN = eplen; if (USB_USE_DMA == udev->bp.transfer_mode) { udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; } if (transc->ep_type == USB_EPTYPE_ISOC) { if (transc->frame_num) { epctl |= DEPCTL_SD1PID; } else { epctl |= DEPCTL_SD0PID; } } /* enable the endpoint and clear the NAK */ epctl |= DEPCTL_EPEN | DEPCTL_CNAK; udev->regs.er_out[ep_num]->DOEPCTL = epctl; return status; } /*! \brief set the usb transaction STALL status \param[in] udev: pointer to usb device \param[in] transc: the usb transaction \param[out] none \retval status */ usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; uint8_t ep_num = transc->ep_addr.num; if (transc->ep_addr.dir) { reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); /* set the endpoint disable bit */ if (*reg_addr & DEPCTL_EPEN) { *reg_addr |= DEPCTL_EPD; } } else { /* set the endpoint stall bit */ reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); } /* set the endpoint stall bit */ *reg_addr |= DEPCTL_STALL; return USB_OK; } /*! \brief clear the usb transaction STALL status \param[in] udev: pointer to usb device \param[in] transc: the usb transaction \param[out] none \retval status */ usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) { __IO uint32_t *reg_addr = NULL; uint8_t ep_num = transc->ep_addr.num; if (transc->ep_addr.dir) { reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); } else { reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); } /* clear the endpoint stall bits */ *reg_addr &= ~DEPCTL_STALL; /* reset data PID of the periodic endpoints */ if ((transc->ep_type == USB_EPTYPE_INTR) || (transc->ep_type == USB_EPTYPE_BULK)) { *reg_addr |= DEPCTL_SD0PID; } return USB_OK; } /*! \brief read device all OUT endpoint interrupt register \param[in] udev: pointer to usb device \param[out] none \retval none */ uint32_t usb_oepintnum_read(usb_core_driver *udev) { uint32_t value = udev->regs.dr->DAEPINT; value &= udev->regs.dr->DAEPINTEN; return (value & DAEPINT_OEPITB) >> 16; } /*! \brief read device OUT endpoint interrupt flag register \param[in] udev: pointer to usb device \param[in] ep_num: endpoint number \param[out] none \retval none */ uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num) { uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; value &= udev->regs.dr->DOEPINTEN; return value; } /*! \brief read device all IN endpoint interrupt register \param[in] udev: pointer to usb device \param[out] none \retval none */ uint32_t usb_iepintnum_read(usb_core_driver *udev) { uint32_t value = udev->regs.dr->DAEPINT; value &= udev->regs.dr->DAEPINTEN; return value & DAEPINT_IEPITB; } /*! \brief read device IN endpoint interrupt flag register \param[in] udev: pointer to usb device \param[in] ep_num: endpoint number \param[out] none \retval none */ uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num) { uint32_t value = 0U, fifoemptymask = 0U, commonintmask = 0U; commonintmask = udev->regs.dr->DIEPINTEN; fifoemptymask = udev->regs.dr->DIEPFEINTEN; /* check FIFO empty interrupt enable bit */ commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; return value; } /*! \brief configures OUT endpoint 0 to receive SETUP packets \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_ctlep_startout(usb_core_driver *udev) { /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); if (USB_USE_DMA == udev->bp.transfer_mode) { udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; /* endpoint enable */ udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; } } /*! \brief set remote wakeup signalling \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_rwkup_set(usb_core_driver *udev) { if (udev->dev.pm.dev_remote_wakeup) { /* enable remote wakeup signaling */ udev->regs.dr->DCTL |= DCTL_RWKUP; } } /*! \brief reset remote wakeup signalling \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_rwkup_reset(usb_core_driver *udev) { if (udev->dev.pm.dev_remote_wakeup) { /* disable remote wakeup signaling */ udev->regs.dr->DCTL &= ~DCTL_RWKUP; } } /*! \brief active remote wakeup signalling \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_rwkup_active(usb_core_driver *udev) { if (udev->dev.pm.dev_remote_wakeup) { if (udev->regs.dr->DSTAT & DSTAT_SPST) { if (udev->bp.low_power) { /* ungate USB core clock */ *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); } /* active remote wakeup signaling */ udev->regs.dr->DCTL |= DCTL_RWKUP; usb_mdelay(5); udev->regs.dr->DCTL &= ~DCTL_RWKUP; } } } /*! \brief active USB core clock \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_clock_active(usb_core_driver *udev) { if (udev->bp.low_power) { if (udev->regs.dr->DSTAT & DSTAT_SPST) { /* un-gate USB Core clock */ *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); } } } /*! \brief usb device suspend \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_dev_suspend(usb_core_driver *udev) { __IO uint32_t devstat = udev->regs.dr->DSTAT; if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { /* switch-off the USB clocks */ *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); } } /*! \brief stop the device and clean up fifos \param[in] udev: pointer to usb device \param[out] none \retval none */ void usb_dev_stop(usb_core_driver *udev) { uint32_t i; udev->dev.cur_status = 1; /* clear all interrupt flag and enable bits */ for (i = 0; i < udev->bp.num_ep; i++) { udev->regs.er_in[i]->DIEPINTF = 0xFFU; udev->regs.er_out[i]->DOEPINTF = 0xFFU; } udev->regs.dr->DIEPINTEN = 0U; udev->regs.dr->DOEPINTEN = 0U; udev->regs.dr->DAEPINTEN = 0U; udev->regs.dr->DAEPINT = 0xFFFFFFFFU; /* flush the FIFO */ usb_rxfifo_flush(&udev->regs); usb_txfifo_flush(&udev->regs, 0x10); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usb_host.c ================================================ /*! \file drv_usb_host.c \brief USB host mode low level driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "drv_usb_host.h" #include "drv_usb_core.h" #include "drv_usb_hw.h" const uint32_t PIPE_DPID[] = {PIPE_DPID_DATA0, PIPE_DPID_DATA1}; //__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *pudev) uint32_t usb_frame_even(usb_core_driver *pudev) { return !(pudev->regs.hr->HFINFR & 0x01U); } //__STATIC_INLINE void usb_phyclock_config (usb_core_driver *pudev, uint8_t clock) void usb_phyclock_config(usb_core_driver *pudev, uint8_t clock) { pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; pudev->regs.hr->HCTL |= clock; } //__STATIC_INLINE uint32_t usb_port_read (usb_core_driver *pudev) uint32_t usb_port_read(usb_core_driver *pudev) { return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); } //__STATIC_INLINE uint32_t usb_curspeed_get (usb_core_driver *pudev) uint32_t usb_curspeed_get(usb_core_driver *pudev) { return *pudev->regs.HPCS & HPCS_PS; } uint32_t usb_curframe_get(usb_core_driver *pudev) { return (pudev->regs.hr->HFINFR & 0xFFFFU); } /*! \brief initializes USB core for host mode \param[in] pudev: pointer to selected usb host \param[out] none \retval operation status */ usb_status usb_host_init(usb_core_driver *pudev) { uint32_t i = 0, inten = 0U; uint32_t nptxfifolen = 0U; uint32_t ptxfifolen = 0U; pudev->regs.gr->GUSBCS &= ~GUSBCS_FDM; pudev->regs.gr->GUSBCS |= GUSBCS_FHM; /* restart the PHY Clock */ *pudev->regs.PWRCLKCTL = 0U; /* initialize host configuration register */ if (USB_ULPI_PHY == pudev->bp.phy_itf) { usb_phyclock_config(pudev, HCTL_30_60MHZ); } else { usb_phyclock_config(pudev, HCTL_48MHZ); } usb_port_reset(pudev); /* support FS/LS only */ pudev->regs.hr->HCTL &= ~HCTL_SPDFSLS; /* configure data FIFOs size */ #ifdef USB_FS_CORE if (USB_CORE_ENUM_FS == pudev->bp.core_enum) { /* set Rx FIFO size */ pudev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; /* set non-periodic Tx FIFO size and address */ nptxfifolen |= USB_RX_FIFO_FS_SIZE; nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; /* set periodic Tx FIFO size and address */ ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_PFIFO_FS_SIZE; ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; pudev->regs.gr->HPTFLEN = ptxfifolen; } #endif /* USB_FS_CORE */ #ifdef USB_HS_CORE if (USB_CORE_HS == pudev->cfg.core) { /* set Rx FIFO size */ pudev->regs.gr->GRFLEN = USBHS_RX_FIFO_SIZE; /* set non-periodic Tx FIFO size and address */ nptxfifolen |= USBHS_RX_FIFO_SIZE; nptxfifolen |= USBHS_HTX_NPFIFO_SIZE; pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; /* set periodic Tx FIFO size and address */ ptxfifolen |= USBHS_RX_FIFO_SIZE + USBHS_HTX_PFIFO_SIZE; ptxfifolen |= USBHS_HTX_PFIFO_SIZE; pudev->regs.gr->HPTFLEN = ptxfifolen; } #endif #ifdef USE_OTG_MODE /* clear host set hnp enable in the usb_otg control register */ pudev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN; #endif /* disable all interrupts */ pudev->regs.gr->GINTEN = 0U; /* clear any pending USB OTG interrupts */ pudev->regs.gr->GOTGINTF = 0xFFFFFFFFU; /* enable the USB wakeup and suspend interrupts */ pudev->regs.gr->GINTF = 0xBFFFFFFFU; /* make sure the FIFOs are flushed */ /* flush all Tx FIFOs in device or host mode */ usb_txfifo_flush(&pudev->regs, 0x10U); /* flush the entire Rx FIFO */ usb_rxfifo_flush(&pudev->regs); /* clear all pending host channel interrupts */ for (i = 0U; i < pudev->bp.num_pipe; i++) { pudev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU; pudev->regs.pr[i]->HCHINTEN = 0U; } #ifndef USE_OTG_MODE usb_portvbus_switch(pudev, 1U); #endif /* USE_OTG_MODE */ pudev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; /* enable host_mode-related interrupts */ if (USB_USE_FIFO == pudev->bp.transfer_mode) { inten = GINTEN_RXFNEIE; } inten |= GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE; pudev->regs.gr->GINTEN |= inten; inten = GINTEN_DISCIE | GINTEN_SOFIE; pudev->regs.gr->GINTEN &= ~inten; pudev->regs.gr->GAHBCS |= GAHBCS_GINTEN; return USB_OK; } /*! \brief control the VBUS to power \param[in] pudev: pointer to selected usb host \param[in] state: VBUS state \param[out] none \retval none */ void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state) { uint32_t port = 0U; /* enable or disable the external charge pump */ usb_vbus_drive(state); /* turn on the host port power. */ port = usb_port_read(pudev); if (!(port & HPCS_PP) && (1U == state)) { port |= HPCS_PP; } if ((port & HPCS_PP) && (0U == state)) { port &= ~HPCS_PP; } *pudev->regs.HPCS = port; usb_mdelay(200U); } /*! \brief reset host port \param[in] pudev: pointer to usb device \param[out] none \retval operation status */ uint32_t usb_port_reset(usb_core_driver *pudev) { __IO uint32_t port = usb_port_read(pudev); *pudev->regs.HPCS = port | HPCS_PRST; usb_mdelay(100U); /* see note */ *pudev->regs.HPCS = port & ~HPCS_PRST; usb_mdelay(20U); return 1; } /*! \brief initialize host pipe \param[in] pudev: pointer to usb device \param[in] pipe_num: host pipe number which is in (0..7) \param[out] none \retval operation status */ usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num) { usb_status status = USB_OK; __IO uint32_t pp_ctl = 0U; __IO uint32_t pp_inten = HCHINTEN_TFIE; usb_pipe *pp = &pudev->host.pipe[pipe_num]; /* clear old interrupt conditions for this host channel */ pudev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU; if (USB_USE_DMA == pudev->bp.transfer_mode) { pp_inten |= HCHINTEN_DMAERIE; } if (pp->ep.dir) { pp_inten |= HCHINTEN_BBERIE; } /* enable channel interrupts required for this transfer */ switch (pp->ep.type) { case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE | HCHINTEN_NAKIE; if (!pp->ep.dir) { pp_inten |= HCHINTEN_NYETIE; if (pp->ping) { pp_inten |= HCHINTEN_ACKIE; } } break; case USB_EPTYPE_INTR: pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; break; case USB_EPTYPE_ISOC: pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; if (pp->ep.dir) { pp_inten |= HCHINTEN_USBERIE; } break; default: break; } pudev->regs.pr[pipe_num]->HCHINTEN = pp_inten; /* enable the top level host channel interrupt */ pudev->regs.hr->HACHINTEN |= 1U << pipe_num; /* make sure host channel interrupts are enabled */ pudev->regs.gr->GINTEN |= GINTEN_HCIE; /* program the host channel control register */ pp_ctl |= PIPE_CTL_DAR(pp->dev_addr); pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num); pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir); pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type); pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW); pp_ctl |= pp->ep.mps; pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM; pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; return status; } /*! \brief prepare host channel for transferring packets \param[in] pudev: pointer to usb device \param[in] pipe_num: host pipe number which is in (0..7) \param[out] none \retval operation status */ usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num) { usb_status status = USB_OK; uint16_t dword_len = 0U; uint16_t packet_count = 0U; __IO uint32_t pp_ctl = 0U; usb_pipe *pp = &pudev->host.pipe[pipe_num]; uint16_t max_packet_len = pp->ep.mps; /* compute the expected number of packets associated to the transfer */ if (pp->xfer_len > 0U) { packet_count = (pp->xfer_len + max_packet_len - 1U) / max_packet_len; if (packet_count > HC_MAX_PACKET_COUNT) { packet_count = HC_MAX_PACKET_COUNT; pp->xfer_len = packet_count * max_packet_len; } } else { packet_count = 1U; } if (pp->ep.dir) { pp->xfer_len = packet_count * max_packet_len; } /* initialize the host channel transfer information */ pudev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count); if (USB_USE_DMA == pudev->bp.transfer_mode) { pudev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf; } pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; if (usb_frame_even(pudev)) { pp_ctl |= HCHCTL_ODDFRM; } else { pp_ctl &= ~HCHCTL_ODDFRM; } /* set host channel enabled */ pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; if (USB_USE_FIFO == pudev->bp.transfer_mode) { if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) { switch (pp->ep.type) { /* non-periodic transfer */ case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: dword_len = (pp->xfer_len + 3U) / 4U; /* check if there is enough space in fifo space */ if (dword_len > (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { /* need to process data in nptxfempty interrupt */ pudev->regs.gr->GINTEN |= GINTEN_NPTXFEIE; } break; /* periodic transfer */ case USB_EPTYPE_INTR: case USB_EPTYPE_ISOC: dword_len = (pp->xfer_len + 3U) / 4U; /* check if there is enough space in fifo space */ if (dword_len > (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { /* need to process data in ptxfempty interrupt */ pudev->regs.gr->GINTEN |= GINTEN_PTXFEIE; } break; default: break; } /* write packet into the tx fifo. */ usb_txfifo_write(&pudev->regs, pp->xfer_buf, pipe_num, pp->xfer_len); } } return status; } /*! \brief halt pipe \param[in] pudev: pointer to usb device \param[in] pipe_num: host pipe number which is in (0..7) \param[out] none \retval operation status */ usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num) { __IO uint32_t pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; uint8_t ep_type = (pp_ctl & HCHCTL_EPTYPE) >> 18U; pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS; switch (ep_type) { case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: if (0U == (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { pp_ctl &= ~HCHCTL_CEN; } break; case USB_EPTYPE_INTR: case USB_EPTYPE_ISOC: if (0U == (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { pp_ctl &= ~HCHCTL_CEN; } break; default: break; } pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; return USB_OK; } /*! \brief configure host pipe to do ping operation \param[in] pudev: pointer to usb device \param[in] pipe_num: host pipe number which is in (0..7) \param[out] none \retval operation status */ usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num) { uint32_t pp_ctl = 0U; pudev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; return USB_OK; } /*! \brief stop the USB host and clean up FIFO \param[in] none \param[out] none \retval none */ void usb_host_stop(usb_core_driver *pudev) { uint32_t i; __IO uint32_t pp_ctl = 0U; pudev->regs.hr->HACHINTEN = 0x0U; pudev->regs.hr->HACHINT = 0xFFFFFFFFU; /* flush out any leftover queued requests. */ for (i = 0U; i < pudev->bp.num_pipe; i++) { pp_ctl = pudev->regs.pr[i]->HCHCTL; pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR); pp_ctl |= HCHCTL_CDIS; pudev->regs.pr[i]->HCHCTL = pp_ctl; } /* flush the FIFO */ usb_rxfifo_flush(&pudev->regs); usb_txfifo_flush(&pudev->regs, 0x10U); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbd_int.c ================================================ /*! \file drv_usbd_int.c \brief USB device mode interrupt routines \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_libopt.h" // #include "usbd_conf.h" #include "drv_usbd_int.h" #include "usbd_transc.h" static uint32_t usbd_int_epout(usb_core_driver *udev); static uint32_t usbd_int_epin(usb_core_driver *udev); static uint32_t usbd_int_rxfifo(usb_core_driver *udev); static uint32_t usbd_int_reset(usb_core_driver *udev); static uint32_t usbd_int_enumfinish(usb_core_driver *udev); static uint32_t usbd_int_suspend(usb_core_driver *udev); static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num); static const uint8_t USB_SPEED[4] = { [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = USB_SPEED_HIGH, [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = USB_SPEED_FULL, [DSTAT_EM_FS_PHY_48MHZ] = USB_SPEED_FULL, [DSTAT_EM_LS_PHY_6MHZ] = USB_SPEED_LOW}; __IO uint8_t setupc_flag = 0U; #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED /*! \brief USB dedicated OUT endpoint 1 interrupt service routine handler \param[in] udev: pointer to usb device instance \param[out] none \retval operation status */ uint32_t USBD_OTG_EP1OUT_ISR_Handler(usb_core_driver *udev) { uint32_t oepintr = 0U; uint32_t oeplen = 0U; oepintr = udev->regs.er_out[1]->DOEPINTF; oepintr &= udev->regs.dr->DOEP1INTEN; /* Transfer complete */ if (oepintr & DOEPINTF_TF) { /* Clear the bit in DOEPINTn for this interrupt */ udev->regs.er_out[1]->DOEPINTF = DOEPINTF_TF; if (USB_USE_DMA == udev->bp.transfer_mode) { oeplen = udev->regs.er_out[1]->DOEPLEN; /* ToDo : handle more than one single MPS size packet */ udev->dev.transc_out[1].xfer_count = udev->dev.transc_out[1].usb_transc - oeplen & DEPLEN_TLEN; } /* RX COMPLETE */ USBD_DCD_INT_fops->DataOutStage(udev, 1); } return 1; } /*! \brief USB dedicated IN endpoint 1 interrupt service routine handler \param[in] udev: pointer to usb device instance \param[out] none \retval operation status */ uint32_t USBD_OTG_EP1IN_ISR_Handler(usb_core_driver *udev) { uint32_t inten, intr, emptyen; inten = udev->regs.dr->DIEP1INTEN; emptyen = udev->regs.dr->DIEPFEINTEN; inten |= ((emptyen >> 1) & 0x1) << 7; intr = udev->regs.er_in[1]->DIEPINTF & inten; if (intr & DIEPINTF_TF) { udev->regs.dr->DIEPFEINTEN &= ~(0x1 << 1); udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TF; /* TX COMPLETE */ USBD_DCD_INT_fops->DataInStage(udev, 1); } if (intr & DIEPINTF_TXFE) { DCD_WriteEmptyTxFifo(udev, 1); udev->regs.er_in[1]->DIEPINTF = DIEPINTF_TXFE; } return 1; } #endif /*! \brief USB device-mode interrupts global service routine handler \param[in] udev: pointer to usb device instance \param[out] none \retval none */ void usbd_isr(usb_core_driver *udev) { if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN; /* there are no interrupts, avoid spurious interrupt */ if (!intr) { return; } /* OUT endpoints interrupts */ if (intr & GINTF_OEPIF) { usbd_int_epout(udev); } /* IN endpoints interrupts */ if (intr & GINTF_IEPIF) { usbd_int_epin(udev); } /* suspend interrupt */ if (intr & GINTF_SP) { usbd_int_suspend(udev); } /* wakeup interrupt */ if (intr & GINTF_WKUPIF) { /* inform upper layer by the resume event */ udev->dev.cur_status = udev->dev.backup_status; /* clear interrupt */ udev->regs.gr->GINTF = GINTF_WKUPIF; } /* wakeup interrupt */ if (intr & GINTF_MFIF) { /* clear interrupt */ udev->regs.gr->GINTF = GINTF_MFIF; } /* start of frame interrupt */ if (intr & GINTF_SOF) { if (udev->dev.class_core->SOF) { udev->dev.class_core->SOF(udev); } if (0U != setupc_flag) { setupc_flag++; if (setupc_flag >= 3U) { usbd_setup_transc(udev); setupc_flag = 0U; } } /* clear interrupt */ udev->regs.gr->GINTF = GINTF_SOF; } /* receive FIFO not empty interrupt */ if (intr & GINTF_RXFNEIF) { usbd_int_rxfifo(udev); } /* USB reset interrupt */ if (intr & GINTF_RST) { usbd_int_reset(udev); } /* enumeration has been done interrupt */ if (intr & GINTF_ENUMFIF) { usbd_int_enumfinish(udev); } /* incomplete synchronization IN transfer interrupt*/ if (intr & GINTF_ISOINCIF) { if (NULL != udev->dev.class_core->incomplete_isoc_in) { udev->dev.class_core->incomplete_isoc_in(udev); } /* Clear interrupt */ udev->regs.gr->GINTF = GINTF_ISOINCIF; } /* incomplete synchronization OUT transfer interrupt*/ if (intr & GINTF_ISOONCIF) { if (NULL != udev->dev.class_core->incomplete_isoc_out) { udev->dev.class_core->incomplete_isoc_out(udev); } /* clear interrupt */ udev->regs.gr->GINTF = GINTF_ISOONCIF; } #ifdef VBUS_SENSING_ENABLED /* Session request interrupt */ if (intr & GINTF_SESIF) { udev->regs.gr->GINTF = GINTF_SESIF; } /* OTG mode interrupt */ if (intr & GINTF_OTGIF) { if (udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { } /* Clear OTG interrupt */ udev->regs.gr->GINTF = GINTF_OTGIF; } #endif } } /*! \brief indicates that an OUT endpoint has a pending interrupt \param[in] udev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbd_int_epout(usb_core_driver *udev) { uint32_t epintnum = 0U; uint32_t ep_num = 0U; for (epintnum = usb_oepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) { if (epintnum & 0x1) { __IO uint32_t oepintr = usb_oepintr_read(udev, ep_num); /* transfer complete interrupt */ if (oepintr & DOEPINTF_TF) { /* clear the bit in DOEPINTF for this interrupt */ udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; if (USB_USE_DMA == udev->bp.transfer_mode) { __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - (eplen & DEPLEN_TLEN); } /* inform upper layer: data ready */ usbd_out_transc(udev, ep_num); if (USB_USE_DMA == udev->bp.transfer_mode) { if ((0U == ep_num) && (USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { usb_ctlep_startout(udev); } } } /* setup phase finished interrupt (control endpoints) */ if (oepintr & DOEPINTF_STPF) { /* inform the upper layer that a setup packet is available */ if ((0U == ep_num) && (0U != setupc_flag)) { usbd_setup_transc(udev); setupc_flag = 0U; udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; } } } } return 1; } /*! \brief indicates that an IN endpoint has a pending interrupt \param[in] udev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbd_int_epin(usb_core_driver *udev) { uint32_t epintnum = 0U; uint32_t ep_num = 0U; for (epintnum = usb_iepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) { if (epintnum & 0x1U) { __IO uint32_t iepintr = usb_iepintr_read(udev, ep_num); if (iepintr & DIEPINTF_TF) { udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; /* data transmittion is completed */ usbd_in_transc(udev, ep_num); if (USB_USE_DMA == udev->bp.transfer_mode) { if ((0U == ep_num) && (USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { usb_ctlep_startout(udev); } } } if (iepintr & DIEPINTF_TXFE) { usbd_emptytxfifo_write(udev, ep_num); udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; } } } return 1; } /*! \brief handle the RX status queue level interrupt \param[in] udev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbd_int_rxfifo(usb_core_driver *udev) { usb_transc *transc = NULL; uint8_t data_PID = 0; uint32_t bcount = 0; __IO uint32_t devrxstat = 0; /* disable the Rx status queue non-empty interrupt */ udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; /* get the status from the top of the FIFO */ devrxstat = udev->regs.gr->GRSTATP; transc = &udev->dev.transc_out[devrxstat & GRSTATRP_EPNUM]; bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4; data_PID = (devrxstat & GRSTATRP_DPID) >> 15; switch ((devrxstat & GRSTATRP_RPCKST) >> 17) { case RSTAT_GOUT_NAK: break; case RSTAT_DATA_UPDT: if (bcount > 0) { usb_rxfifo_read(&udev->regs, transc->xfer_buf, bcount); transc->xfer_buf += bcount; transc->xfer_count += bcount; } break; case RSTAT_XFER_COMP: /* trigger the OUT enpoint interrupt */ break; case RSTAT_SETUP_COMP: /* trigger the OUT enpoint interrupt */ break; case RSTAT_SETUP_UPDT: if ((transc->ep_addr.num == 0) && (bcount == 8) && (data_PID == DPID_DATA0)) { /* copy the setup packet received in FIFO into the setup buffer in RAM */ usb_rxfifo_read(&udev->regs, (uint8_t *)&udev->dev.control.req, bcount); transc->xfer_count += bcount; setupc_flag = 1; } break; default: break; } /* enable the Rx status queue level interrupt */ udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; return 1; } /*! \brief handle USB reset interrupt \param[in] udev: pointer to usb device instance \param[out] none \retval status */ static uint32_t usbd_int_reset(usb_core_driver *udev) { uint32_t i; /* clear the remote wakeup signaling */ udev->regs.dr->DCTL &= ~DCTL_RWKUP; /* flush the Tx FIFO */ usb_txfifo_flush(&udev->regs, 0); for (i = 0; i < udev->bp.num_ep; i++) { udev->regs.er_in[i]->DIEPINTF = 0xFFU; udev->regs.er_out[i]->DOEPINTF = 0xFFU; } /* clear all pending device endpoint interrupts */ udev->regs.dr->DAEPINT = 0xFFFFFFFFU; /* enable endpoint 0 interrupts */ udev->regs.dr->DAEPINTEN = 1U | (1U << 16); /* enable OUT endpoint interrupts */ udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; /* enable IN endpoint interrupts */ udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; /* reset device address */ udev->regs.dr->DCFG &= ~DCFG_DAR; udev->dev.dev_addr = 0U; /* configure endpoint 0 to receive SETUP packets */ usb_ctlep_startout(udev); /* clear USB reset interrupt */ udev->regs.gr->GINTF = GINTF_RST; udev->dev.transc_out[0] = (usb_transc){.ep_type = USB_EPTYPE_CTRL, .max_len = USB_FS_EP0_MAX_LEN}; usb_transc_active(udev, &udev->dev.transc_out[0]); udev->dev.transc_in[0] = (usb_transc){.ep_addr = {.dir = 1}, .ep_type = USB_EPTYPE_CTRL, .max_len = USB_FS_EP0_MAX_LEN}; usb_transc_active(udev, &udev->dev.transc_in[0]); /* upon reset call usr call back */ udev->dev.cur_status = USBD_DEFAULT; return 1; } /*! \brief handle USB speed enumeration finish interrupt \param[in] udev: pointer to usb device instance \param[out] none \retval status */ static uint32_t usbd_int_enumfinish(usb_core_driver *udev) { uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); udev->regs.dr->DCTL &= ~DCTL_CGINAK; udev->regs.dr->DCTL |= DCTL_CGINAK; udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; /* set USB turn-around time based on device speed and PHY interface */ if (USB_SPEED[enum_speed] == USB_SPEED_HIGH) { udev->bp.core_speed = USB_SPEED_HIGH; udev->regs.gr->GUSBCS |= 0x09 << 10; } else { udev->bp.core_speed = USB_SPEED_FULL; udev->regs.gr->GUSBCS |= 0x05 << 10; } /* clear interrupt */ udev->regs.gr->GINTF = GINTF_ENUMFIF; return 1; } /*! \brief USB suspend interrupt handler \param[in] udev: pointer to USB device instance \param[out] none \retval operation status */ static uint32_t usbd_int_suspend(usb_core_driver *udev) { __IO uint8_t low_power = udev->bp.low_power; __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); __IO uint8_t is_configured = (udev->dev.cur_status == USBD_CONFIGURED) ? 1U : 0U; udev->dev.backup_status = udev->dev.cur_status; udev->dev.cur_status = USBD_SUSPENDED; if (low_power && suspend && is_configured) { /* switch-off the otg clocks */ *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; /* enter DEEP_SLEEP mode with LDO in low power mode */ pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); } /* clear interrupt */ udev->regs.gr->GINTF = GINTF_SP; return 1U; } /*! \brief check FIFO for the next packet to be loaded \param[in] udev: pointer to usb device instance \param[in] ep_num: endpoint identifier which is in (0..3) \param[out] none \retval status */ static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num) { usb_transc *transc = NULL; uint32_t len = 0; uint32_t word_count = 0; transc = &udev->dev.transc_in[ep_num]; len = transc->xfer_len - transc->xfer_count; /* get the data length to write */ if (len > transc->max_len) { len = transc->max_len; } word_count = (len + 3) / 4; while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) > word_count) && (transc->xfer_count < transc->xfer_len)) { len = transc->xfer_len - transc->xfer_count; if (len > transc->max_len) { len = transc->max_len; } /* write FIFO in word(4bytes) */ word_count = (len + 3) / 4; /* write the FIFO */ usb_txfifo_write(&udev->regs, transc->xfer_buf, ep_num, len); transc->xfer_buf += len; transc->xfer_count += len; if (transc->xfer_count == transc->xfer_len) { /* disable the device endpoint FIFO empty interrupt */ udev->regs.dr->DIEPFEINTEN &= ~(0x01 << ep_num); } } return 1; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/drv_usbh_int.c ================================================ /*! \file drv_usbh_int.c \brief USB host mode interrupt handler file \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "drv_usbh_int.h" #include "drv_usb_core.h" #include "drv_usb_host.h" #if defined(__GNUC__) /*!< GNU compiler */ #pragma GCC optimize("O0") #endif /* __GNUC__ */ static uint32_t usbh_int_port(usb_core_driver *pudev); static uint32_t usbh_int_pipe(usb_core_driver *pudev); static uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num); static uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num); static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev); static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode); static inline void usb_pp_halt(usb_core_driver *pudev, uint8_t pp_num, uint32_t pp_int, usb_pipe_staus pp_status) { pudev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE; usb_pipe_halt(pudev, pp_num); pudev->regs.pr[pp_num]->HCHINTF = pp_int; pudev->host.pipe[pp_num].pp_status = pp_status; } /*! \brief handle global host interrupt \param[in] pudev: pointer to usb core instance \param[out] none \retval operation status */ uint32_t usbh_isr(usb_core_driver *pudev) { uint32_t Retval = 0U; __IO uint32_t intr = 0U; /* check if host mode */ if (HOST_MODE == (pudev->regs.gr->GINTF & GINTF_COPM)) { intr = usb_coreintr_get(&pudev->regs); if (!intr) { return 0; } if (intr & GINTF_SOF) { usbh_int_fop->SOF(pudev); /* clear interrupt */ pudev->regs.gr->GINTF = GINTF_SOF; } if (intr & GINTF_RXFNEIF) { Retval |= usbh_int_rxfifonoempty(pudev); } if (intr & GINTF_NPTXFEIF) { Retval |= usbh_int_txfifoempty(pudev, PIPE_NON_PERIOD); } if (intr & GINTF_PTXFEIF) { Retval |= usbh_int_txfifoempty(pudev, PIPE_PERIOD); } if (intr & GINTF_HCIF) { Retval |= usbh_int_pipe(pudev); } if (intr & GINTF_HPIF) { Retval |= usbh_int_port(pudev); } if (intr & GINTF_DISCIF) { pudev->host.connect_status = 0U; /* clear interrupt */ pudev->regs.gr->GINTF = GINTF_DISCIF; } if (intr & GINTF_ISOONCIF) { pudev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS; /* clear interrupt */ pudev->regs.gr->GINTF = GINTF_ISOONCIF; } } return Retval; } /*! \brief handle all host channels interrupt \param[in] pudev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbh_int_pipe(usb_core_driver *pudev) { uint32_t pp_num = 0U; uint32_t retval = 0U; for (pp_num = 0U; pp_num < pudev->bp.num_pipe; pp_num++) { if ((pudev->regs.hr->HACHINT & HACHINT_HACHINT) & (1U << pp_num)) { if (pudev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) { retval |= usbh_int_pipe_in(pudev, pp_num); } else { retval |= usbh_int_pipe_out(pudev, pp_num); } } } return retval; } /*! \brief handle the TX FIFO empty interrupt \param[in] pudev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode) { uint8_t pp_num = 0U; uint16_t word_count = 0U, len = 0U; __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; if (PIPE_NON_PERIOD == pp_mode) { txfiforeg = &pudev->regs.gr->HNPTFQSTAT; } else if (PIPE_PERIOD == pp_mode) { txfiforeg = &pudev->regs.hr->HPTFQSTAT; } else { return 0U; } txfifostate = *txfiforeg; pp_num = (txfifostate & TFQSTAT_CNUM) >> 27U; word_count = (pudev->host.pipe[pp_num].xfer_len + 3U) / 4U; while (((txfifostate & TFQSTAT_TXFS) > word_count) && (0U != pudev->host.pipe[pp_num].xfer_len)) { len = (txfifostate & TFQSTAT_TXFS) * 4U; if (len > pudev->host.pipe[pp_num].xfer_len) { /* last packet */ len = pudev->host.pipe[pp_num].xfer_len; if (PIPE_NON_PERIOD == pp_mode) { pudev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE; } else { pudev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE; } } word_count = (pudev->host.pipe[pp_num].xfer_len + 3U) / 4U; usb_txfifo_write(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, pp_num, len); pudev->host.pipe[pp_num].xfer_buf += len; pudev->host.pipe[pp_num].xfer_len -= len; pudev->host.pipe[pp_num].xfer_count += len; txfifostate = *txfiforeg; } return 1; } /*! \brief handle the host port interrupt \param[in] pudev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbh_int_port(usb_core_driver *pudev) { uint32_t retval = 0U; __IO uint32_t port_state = *pudev->regs.HPCS; /* clear the interrupt bits in GINTSTS */ port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); /* port connect detected */ if (*pudev->regs.HPCS & HPCS_PCD) { port_state |= HPCS_PCD; pudev->host.connect_status = 1U; retval |= 1U; } /* port enable changed */ if (*pudev->regs.HPCS & HPCS_PEDC) { port_state |= HPCS_PEDC; if (*pudev->regs.HPCS & HPCS_PE) { uint32_t port_speed = usb_curspeed_get(pudev); uint32_t clock_type = pudev->regs.hr->HCTL & HCTL_CLKSEL; pudev->host.connect_status = 1U; if (PORT_SPEED_LOW == port_speed) { pudev->regs.hr->HFT = 6000U; if (HCTL_6MHZ != clock_type) { if (USB_EMBEDDED_PHY == pudev->bp.phy_itf) { usb_phyclock_config(pudev, HCTL_6MHZ); } } } else if (PORT_SPEED_FULL == port_speed) { pudev->regs.hr->HFT = 48000U; if (HCTL_48MHZ != clock_type) { usb_phyclock_config(pudev, HCTL_48MHZ); } } else { /* for high speed device and others */ } pudev->host.port_enabled = 1U; pudev->regs.gr->GINTEN |= GINTEN_DISCIE; } else { pudev->host.port_enabled = 0U; } } /* clear port interrupts */ *pudev->regs.HPCS = port_state; return retval; } /*! \brief handle the OUT channel interrupt \param[in] pudev: pointer to usb device instance \param[in] pp_num: host channel number which is in (0..7) \param[out] none \retval operation status */ uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num) { usb_pr *pp_reg = pudev->regs.pr[pp_num]; usb_pipe *pp = &pudev->host.pipe[pp_num]; uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; if (intr_pp & HCHINTF_ACK) { pp_reg->HCHINTF = HCHINTF_ACK; } else if (intr_pp & HCHINTF_STALL) { usb_pp_halt(pudev, pp_num, HCHINTF_STALL, PIPE_STALL); } else if (intr_pp & HCHINTF_DTER) { usb_pp_halt(pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR); pp_reg->HCHINTF = HCHINTF_NAK; } else if (intr_pp & HCHINTF_REQOVR) { usb_pp_halt(pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR); } else if (intr_pp & HCHINTF_TF) { pp->err_count = 0U; usb_pp_halt(pudev, pp_num, HCHINTF_TF, PIPE_XF); } else if (intr_pp & HCHINTF_NAK) { pp->err_count = 0U; usb_pp_halt(pudev, pp_num, HCHINTF_NAK, PIPE_NAK); } else if (intr_pp & HCHINTF_USBER) { pp->err_count++; usb_pp_halt(pudev, pp_num, HCHINTF_USBER, PIPE_TRACERR); } else if (intr_pp & HCHINTF_NYET) { pp->err_count = 0U; usb_pp_halt(pudev, pp_num, HCHINTF_NYET, PIPE_NYET); } else if (intr_pp & HCHINTF_CH) { pudev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; switch (pp->pp_status) { case PIPE_XF: pp->urb_state = URB_DONE; if (USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { pp->data_toggle_out ^= 1U; } break; case PIPE_NAK: pp->urb_state = URB_NOTREADY; break; case PIPE_NYET: if (1U == pudev->host.pipe[pp_num].ping) { usb_pipe_ping(pudev, pp_num); } pp->urb_state = URB_NOTREADY; break; case PIPE_STALL: pp->urb_state = URB_STALL; break; case PIPE_TRACERR: if (3U == pp->err_count) { pp->urb_state = URB_ERROR; pp->err_count = 0U; } break; default: break; } pp_reg->HCHINTF = HCHINTF_CH; } return 1; } /*! \brief handle the IN channel interrupt \param[in] pudev: pointer to usb device instance \param[in] pp_num: host channel number which is in (0..7) \param[out] none \retval operation status */ uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num) { usb_pr *pp_reg = pudev->regs.pr[pp_num]; usb_pipe *pp = &pudev->host.pipe[pp_num]; __IO uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; uint8_t ep_type = (pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U; if (intr_pp & HCHINTF_ACK) { pp_reg->HCHINTF = HCHINTF_ACK; } else if (intr_pp & HCHINTF_STALL) { usb_pp_halt(pudev, pp_num, HCHINTF_STALL, PIPE_STALL); pp_reg->HCHINTF = HCHINTF_NAK; /* note: When there is a 'STALL', reset also nak, else, the pudev->host.pp_status = HC_STALL will be overwritten by 'NAK' in code below */ intr_pp &= ~HCHINTF_NAK; } else if (intr_pp & HCHINTF_DTER) { usb_pp_halt(pudev, pp_num, HCHINTF_DTER, PIPE_DTGERR); pp_reg->HCHINTF = HCHINTF_NAK; } if (intr_pp & HCHINTF_REQOVR) { usb_pp_halt(pudev, pp_num, HCHINTF_REQOVR, PIPE_REQOVR); } else if (intr_pp & HCHINTF_TF) { if (USB_USE_DMA == pudev->bp.transfer_mode) { pudev->host.backup_xfercount[pp_num] = pp->xfer_len - (pp_reg->HCHLEN & HCHLEN_TLEN); } pp->pp_status = PIPE_XF; pp->err_count = 0U; pp_reg->HCHINTF = HCHINTF_TF; switch (ep_type) { case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: usb_pp_halt(pudev, pp_num, HCHINTF_NAK, PIPE_XF); pp->data_toggle_in ^= 1U; break; case USB_EPTYPE_INTR: pp_reg->HCHCTL |= HCHCTL_ODDFRM; pp->urb_state = URB_DONE; break; default: break; } } else if (intr_pp & HCHINTF_CH) { pp_reg->HCHINTEN &= ~HCHINTEN_CHIE; switch (pp->pp_status) { case PIPE_XF: pp->urb_state = URB_DONE; break; case PIPE_STALL: pp->urb_state = URB_STALL; break; case PIPE_TRACERR: case PIPE_DTGERR: pp->err_count = 0U; pp->urb_state = URB_ERROR; break; default: if (USB_EPTYPE_INTR == ep_type) { pp->data_toggle_in ^= 1U; } break; } pp_reg->HCHINTF = HCHINTF_CH; } else if (intr_pp & HCHINTF_BBER) { pp->err_count++; usb_pp_halt(pudev, pp_num, HCHINTF_BBER, PIPE_TRACERR); } else if (intr_pp & HCHINTF_NAK) { switch (ep_type) { case USB_EPTYPE_CTRL: case USB_EPTYPE_BULK: /* re-activate the channel */ pp_reg->HCHCTL = (pp_reg->HCHCTL | HCHCTL_CEN) & ~HCHCTL_CDIS; break; case USB_EPTYPE_INTR: pp_reg->HCHINTEN |= HCHINTEN_CHIE; usb_pipe_halt(pudev, pp_num); break; default: break; } pp->pp_status = PIPE_NAK; pp_reg->HCHINTF = HCHINTF_NAK; } return 1; } /*! \brief handle the rx fifo non-empty interrupt \param[in] pudev: pointer to usb device instance \param[out] none \retval operation status */ static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev) { uint32_t count = 0U; __IO uint8_t pp_num = 0U; __IO uint32_t rx_stat = 0U; /* disable the rx status queue level interrupt */ pudev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; rx_stat = pudev->regs.gr->GRSTATP; pp_num = rx_stat & GRSTATRP_CNUM; switch ((rx_stat & GRSTATRP_RPCKST) >> 17U) { case GRXSTS_PKTSTS_IN: count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; /* read the data into the host buffer. */ if ((count > 0U) && (NULL != pudev->host.pipe[pp_num].xfer_buf)) { usb_rxfifo_read(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, count); /* manage multiple transfer packet */ pudev->host.pipe[pp_num].xfer_buf += count; pudev->host.pipe[pp_num].xfer_count += count; pudev->host.backup_xfercount[pp_num] = pudev->host.pipe[pp_num].xfer_count; if (pudev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { /* re-activate the channel when more packets are expected */ __IO uint32_t pp_ctl = pudev->regs.pr[pp_num]->HCHCTL; pp_ctl |= HCHCTL_CEN; pp_ctl &= ~HCHCTL_CDIS; pudev->regs.pr[pp_num]->HCHCTL = pp_ctl; } } break; case GRXSTS_PKTSTS_IN_XFER_COMP: break; case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; while (count > 0U) { rx_stat = pudev->regs.gr->GRSTATP; count--; } break; case GRXSTS_PKTSTS_CH_HALTED: break; default: break; } /* enable the rx status queue level interrupt */ pudev->regs.gr->GINTEN |= GINTEN_RXFNEIE; return 1; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/gd32vf103_usb_hw.c ================================================ /*! \file gd32vf103_usb_hw.c \brief this file implements the board support package for the USB host library \version 2019-6-5, V1.0.0, firmware for GD32VF103 */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "drv_usb_hw.h" #include "gd32vf103_libopt.h" #include #include #include #define TIM_MSEC_DELAY 0x01 #define TIM_USEC_DELAY 0x02 #define HOST_POWERSW_PORT_RCC RCU_GPIOD #define HOST_POWERSW_PORT GPIOD #define HOST_POWERSW_VBUS GPIO_PIN_13 __IO uint32_t delay_time = 0; __IO uint32_t usbfs_prescaler = 0; __IO uint32_t timer_prescaler = 5; static void hwp_time_set(uint8_t unit); static void hwp_delay(uint32_t ntime, uint8_t unit); /*! \brief configure USB clock \param[in] none \param[out] none \retval none */ void usb_rcu_config(void) { uint32_t system_clock = rcu_clock_freq_get(CK_SYS); if (system_clock == 48000000) { usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1; timer_prescaler = 3; } else if (system_clock == 72000000) { usbfs_prescaler = RCU_CKUSB_CKPLL_DIV1_5; timer_prescaler = 5; } else if (system_clock == 96000000) { usbfs_prescaler = RCU_CKUSB_CKPLL_DIV2; timer_prescaler = 7; } else { /* reserved */ } rcu_usb_clock_config(usbfs_prescaler); rcu_periph_clock_enable(RCU_USBFS); } /*! \brief configure USB global interrupt \param[in] none \param[out] none \retval none */ void usb_intr_config(void) { ECLIC_SetLevelIRQ(USBFS_IRQn, 1); ECLIC_SetPriorityIRQ(USBFS_IRQn, 0); ECLIC_EnableIRQ(USBFS_IRQn); #ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT /* enable the power module clock */ rcu_periph_clock_enable(RCU_PMU); /* USB wakeup EXTI line configuration */ exti_interrupt_flag_clear(EXTI_18); exti_init(EXTI_18, EXTI_INTERRUPT, EXTI_TRIG_RISING); exti_interrupt_enable(EXTI_18); ECLIC_SetLevelIRQ(USBFS_WKUP_IRQn, 3); ECLIC_SetPriorityIRQ(USBFS_WKUP_IRQn, 0); ECLIC_EnableIRQ(USBFS_WKUP_IRQn); #endif /* USBHS_LOW_PWR_MGMT_SUPPORT */ } /*! \brief drives the VBUS signal through gpio \param[in] state: VBUS states \param[out] none \retval none */ void usb_vbus_drive(uint8_t state) { if (0 == state) { /* DISABLE is needed on output of the Power Switch */ gpio_bit_reset(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); } else { /*ENABLE the Power Switch by driving the Enable LOW */ gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); } } /*! \brief configures the GPIO for the VBUS \param[in] none \param[out] none \retval none */ void usb_vbus_config(void) { rcu_periph_clock_enable(HOST_POWERSW_PORT_RCC); gpio_init(HOST_POWERSW_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, HOST_POWERSW_VBUS); /* by default, disable is needed on output of the power switch */ gpio_bit_set(HOST_POWERSW_PORT, HOST_POWERSW_VBUS); /* Delay is need for stabilising the Vbus Low in Reset Condition, * when Vbus=1 and Reset-button is pressed by user */ // usb_mdelay (1); usb_mdelay(2); } /*! \brief initializes delay unit using Timer2 \param[in] none \param[out] none \retval none */ void usb_timer_init(void) { rcu_periph_clock_enable(RCU_TIMER2); // eclic_irq_enable(TIMER2_IRQn, 2, 0); /*ECLIC_Register_IRQn(TIMER2_IRQn, ECLIC_VECTOR_INTERRUPT, ECLIC_LEVEL_TRIGGER, 2, 0, TIMER2_IRQHandler);*/ } /*! \brief delay in micro seconds \param[in] usec: value of delay required in micro seconds \param[out] none \retval none */ void usb_udelay(const uint32_t usec) { hwp_delay(usec, TIM_USEC_DELAY); } /*! \brief delay in milli seconds \param[in] msec: value of delay required in milli seconds \param[out] none \retval none */ void usb_mdelay(const uint32_t msec) { hwp_delay(msec, TIM_MSEC_DELAY); } /*! \brief timer base IRQ \param[in] none \param[out] none \retval none */ void usb_timer_irq(void) { if (timer_interrupt_flag_get(TIMER2, TIMER_INT_UP) != RESET) { timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); if (delay_time > 0x00U) { delay_time--; } else { timer_disable(TIMER2); } } } /*! \brief delay routine based on TIM2 \param[in] ntime: delay Time \param[in] unit: delay Time unit = mili sec / micro sec \param[out] none \retval none */ static void hwp_delay(uint32_t ntime, uint8_t unit) { delay_time = ntime; hwp_time_set(unit); while (delay_time != 0) ; timer_disable(TIMER2); } /*! \brief configures TIM2 for delay routine based on TIM2 \param[in] unit: msec /usec \param[out] none \retval none */ static void hwp_time_set(uint8_t unit) { timer_parameter_struct timer_basestructure; timer_disable(TIMER2); timer_interrupt_disable(TIMER2, TIMER_INT_UP); if (unit == TIM_USEC_DELAY) { timer_basestructure.period = 11; } else if (unit == TIM_MSEC_DELAY) { timer_basestructure.period = 11999; } else { /* no operation */ } timer_basestructure.prescaler = timer_prescaler; timer_basestructure.alignedmode = TIMER_COUNTER_EDGE; timer_basestructure.counterdirection = TIMER_COUNTER_UP; timer_basestructure.clockdivision = TIMER_CKDIV_DIV1; timer_basestructure.repetitioncounter = 0; timer_init(TIMER2, &timer_basestructure); timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); timer_auto_reload_shadow_enable(TIMER2); /* timer2 interrupt enable */ timer_interrupt_enable(TIMER2, TIMER_INT_UP); /* timer2 enable counter */ timer_enable(TIMER2); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_core.c ================================================ /*! \file usbd_core.c \brief USB device mode core functions \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbd_core.h" #include "drv_usb_hw.h" /* endpoint type */ const uint32_t ep_type[] = {[USB_EP_ATTR_CTL] = USB_EPTYPE_CTRL, [USB_EP_ATTR_BULK] = USB_EPTYPE_BULK, [USB_EP_ATTR_INT] = USB_EPTYPE_INTR, [USB_EP_ATTR_ISO] = USB_EPTYPE_ISOC}; /*! \brief initailizes the USB device-mode stack and load the class driver \param[in] udev: pointer to USB core instance \param[in] core: usb core type \param[in] class_core: class driver \param[out] none \retval none */ void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_class_core *class_core) { /* device descriptor, class and user callbacks */ udev->dev.class_core = class_core; /* configure USB capabilites */ usb_basic_init(&udev->bp, &udev->regs, core); /* initailizes the USB core*/ usb_core_init(udev->bp, &udev->regs); /* set device disconnect */ usbd_disconnect(udev); /* initailizes device mode */ usb_devcore_init(udev); /* set device connect */ usbd_connect(udev); udev->dev.cur_status = USBD_DEFAULT; } /*! \brief endpoint initialization \param[in] udev: pointer to USB core instance \param[in] ep_desc: pointer to endpoint descriptor \param[out] none \retval none */ uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc) { usb_transc *transc; uint8_t ep_addr = ep_desc->bEndpointAddress; uint8_t max_len = ep_desc->wMaxPacketSize; /* set endpoint direction */ if (EP_DIR(ep_addr)) { transc = &udev->dev.transc_in[EP_ID(ep_addr)]; transc->ep_addr.dir = 1U; } else { transc = &udev->dev.transc_out[ep_addr]; transc->ep_addr.dir = 0U; } transc->ep_addr.num = EP_ID(ep_addr); transc->max_len = max_len; transc->ep_type = ep_type[ep_desc->bmAttributes & USB_EPTYPE_MASK]; /* active USB endpoint function */ usb_transc_active(udev, transc); return 0; } /*! \brief configure the endpoint when it is disabled \param[in] udev: pointer to USB core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[out] none \retval none */ uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr) { usb_transc *transc; if (EP_DIR(ep_addr)) { transc = &udev->dev.transc_in[EP_ID(ep_addr)]; } else { transc = &udev->dev.transc_out[ep_addr]; } /* deactive USB endpoint function */ usb_transc_deactivate(udev, transc); return 0; } /*! \brief endpoint prepare to receive data \param[in] udev: pointer to usb core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[in] pbuf: user buffer address pointer \param[in] len: buffer length \param[out] none \retval none */ uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) { usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; /* setup the transfer */ transc->xfer_buf = pbuf; transc->xfer_len = len; transc->xfer_count = 0; if (USB_USE_DMA == udev->bp.transfer_mode) { transc->dma_addr = (uint32_t)pbuf; } /* start the transfer */ usb_transc_outxfer(udev, transc); return 0; } /*! \brief endpoint prepare to transmit data \param[in] udev: pointer to USB core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[in] pbuf: transmit buffer address pointer \param[in] len: buffer length \param[out] none \retval none */ uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint16_t len) { usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; /* setup the transfer */ transc->xfer_buf = pbuf; transc->xfer_len = len; transc->xfer_count = 0; if (USB_USE_DMA == udev->bp.transfer_mode) { transc->dma_addr = (uint32_t)pbuf; } /* start the transfer */ usb_transc_inxfer(udev, transc); return 0; } /*! \brief set an endpoint to STALL status \param[in] udev: pointer to USB core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[out] none \retval none */ uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr) { usb_transc *transc = NULL; if (EP_DIR(ep_addr)) { transc = &udev->dev.transc_in[EP_ID(ep_addr)]; } else { transc = &udev->dev.transc_out[ep_addr]; } transc->ep_stall = 1; usb_transc_stall(udev, transc); return (0); } /*! \brief clear endpoint STALLed status \param[in] udev: pointer to usb core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[out] none \retval none */ uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr) { usb_transc *transc = NULL; if (EP_DIR(ep_addr)) { transc = &udev->dev.transc_in[EP_ID(ep_addr)]; } else { transc = &udev->dev.transc_out[ep_addr]; } transc->ep_stall = 0; usb_transc_clrstall(udev, transc); return (0); } /*! \brief flush the endpoint FIFOs \param[in] udev: pointer to usb core instance \param[in] ep_addr: endpoint address in this parameter: bit0..bit6: endpoint number (0..7) bit7: endpoint direction which can be IN(1) or OUT(0) \param[out] none \retval none */ uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr) { if (EP_DIR(ep_addr)) { usb_txfifo_flush(&udev->regs, EP_ID(ep_addr)); } else { usb_rxfifo_flush(&udev->regs); } return (0); } /*! \brief set USB device address \param[in] udev: pointer to USB core instance \param[in] addr: device address to set \param[out] none \retval none */ void usbd_addr_set(usb_core_driver *udev, uint8_t addr) { usb_devaddr_set(udev, addr); } /*! \brief get the received data length \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint number \param[out] none \retval USB device operation cur_status */ uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num) { return udev->dev.transc_out[ep_num].xfer_count; } /*! \brief device connect \param[in] udev: pointer to USB device instance \param[out] none \retval none */ void usbd_connect(usb_core_driver *udev) { #ifndef USE_OTG_MODE /* connect device */ usb_dev_connect(udev); usb_mdelay(3); #endif /* USE_OTG_MODE */ } /*! \brief device disconnect \param[in] udev: pointer to USB device instance \param[out] none \retval none */ void usbd_disconnect(usb_core_driver *udev) { #ifndef USE_OTG_MODE /* disconnect device for 3ms */ usb_dev_disconnect(udev); usb_mdelay(3); #endif /* USE_OTG_MODE */ } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_enum.c ================================================ /*! \file usbd_enum.c \brief USB enumeration function \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbd_enum.h" #include "usb_ch9_std.h" static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req); static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req); static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = { [USB_GET_STATUS] = _usb_std_getstatus, [USB_CLEAR_FEATURE] = _usb_std_clearfeature, [USB_RESERVED2] = _usb_std_reserved, [USB_SET_FEATURE] = _usb_std_setfeature, [USB_RESERVED4] = _usb_std_reserved, [USB_SET_ADDRESS] = _usb_std_setaddress, [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, [USB_GET_INTERFACE] = _usb_std_getinterface, [USB_SET_INTERFACE] = _usb_std_setinterface, [USB_SYNCH_FRAME] = _usb_std_synchframe, }; /* get standard descriptor handler */ static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = {[USB_DESCTYPE_DEV - 1] = _usb_dev_desc_get, [USB_DESCTYPE_CONFIG - 1] = _usb_config_desc_get, [USB_DESCTYPE_STR - 1] = _usb_str_desc_get}; /*! \brief handle USB standard device request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req) { return (*_std_dev_req[req->bRequest])(udev, req); } /*! \brief handle USB device class request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device class request \param[out] none \retval USB device request status */ usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req) { if (USBD_CONFIGURED == udev->dev.cur_status) { if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { /* call device class handle function */ uint8_t res = udev->dev.class_core->req_proc(udev, req); return (usb_reqsta)res; } } return REQ_NOTSUPP; } /*! \brief handle USB vendor request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB vendor request \param[out] none \retval USB device request status */ usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req) { /* added by user... */ return REQ_SUPP; } /*! \brief no operation, just for reserved \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB vendor request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req) { /* no operation... */ return REQ_NOTSUPP; } /*! \brief get the device descriptor \param[in] udev: pointer to USB device instance \param[in] index: no use \param[out] len: data length pointer \retval descriptor buffer pointer */ static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) { *len = udev->dev.desc.dev_desc[0]; return udev->dev.desc.dev_desc; } /*! \brief get the configuration descriptor \brief[in] udev: pointer to USB device instance \brief[in] index: no use \param[out] len: data length pointer \retval descriptor buffer pointer */ static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) { *len = udev->dev.desc.config_desc[2]; return udev->dev.desc.config_desc; } /*! \brief get the BOS descriptor \brief[in] udev: pointer to USB device instance \brief[in] index: no use \param[out] len: data length pointer \retval descriptor buffer pointer */ static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) { *len = udev->dev.desc.bos_desc[2]; return udev->dev.desc.bos_desc; } /*! \brief get string descriptor \param[in] udev: pointer to USB device instance \param[in] index: string descriptor index \param[out] len: pointer to string length \retval descriptor buffer pointer */ static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) { uint8_t *desc = udev->dev.desc.strings[index]; *len = desc[0]; return desc; } /*! \brief handle Get_Status request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req) { uint8_t recp = BYTE_LOW(req->wIndex); usb_transc *transc = &udev->dev.transc_in[0]; static uint8_t status[2] = {0}; switch (req->bmRequestType & USB_RECPTYPE_MASK) { case USB_RECPTYPE_DEV: if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) { if (udev->dev.pm.power_mode) { status[0] = USB_STATUS_SELF_POWERED; } else { status[0] = 0U; } if (udev->dev.pm.dev_remote_wakeup) { status[0] |= USB_STATUS_REMOTE_WAKEUP; } else { status[0] = 0U; } transc->xfer_buf = status; transc->remain_len = 2U; return REQ_SUPP; } break; case USB_RECPTYPE_ITF: if ((USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { transc->xfer_buf = status; transc->remain_len = 2U; return REQ_SUPP; } break; case USB_RECPTYPE_EP: if (USBD_CONFIGURED == udev->dev.cur_status) { if (0x80U == (recp & 0x80U)) { status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; } else { status[0] = udev->dev.transc_out[recp].ep_stall; } transc->xfer_buf = status; transc->remain_len = 2U; return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB Clear_Feature request \param[in] udev: pointer to USB device instance \param[in] req: USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req) { uint8_t ep = 0; switch (req->bmRequestType & USB_RECPTYPE_MASK) { case USB_RECPTYPE_DEV: if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) { /* clear device remote wakeup feature */ if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { udev->dev.pm.dev_remote_wakeup = 0U; return REQ_SUPP; } } break; case USB_RECPTYPE_ITF: break; case USB_RECPTYPE_EP: /* get endpoint address */ ep = BYTE_LOW(req->wIndex); if (USBD_CONFIGURED == udev->dev.cur_status) { /* clear endpoint halt feature */ if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { usbd_ep_stall_clear(udev, ep); udev->dev.class_core->req_proc(udev, req); } return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB Set_Feature request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req) { uint8_t ep = 0; switch (req->bmRequestType & USB_RECPTYPE_MASK) { case USB_RECPTYPE_DEV: if ((USBD_ADDRESSED == udev->dev.cur_status) || (USBD_CONFIGURED == udev->dev.cur_status)) { /* set device remote wakeup feature */ if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { udev->dev.pm.dev_remote_wakeup = 1U; } return REQ_SUPP; } break; case USB_RECPTYPE_ITF: break; case USB_RECPTYPE_EP: /* get endpoint address */ ep = BYTE_LOW(req->wIndex); if (USBD_CONFIGURED == udev->dev.cur_status) { /* set endpoint halt feature */ if ((USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { usbd_ep_stall(udev, ep); } return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB Set_Address request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req) { if ((0U == req->wIndex) && (0U == req->wLength)) { udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; if (udev->dev.cur_status != USBD_CONFIGURED) { usbd_addr_set(udev, udev->dev.dev_addr); if (udev->dev.dev_addr) { udev->dev.cur_status = USBD_ADDRESSED; } else { udev->dev.cur_status = USBD_DEFAULT; } return REQ_SUPP; } } return REQ_NOTSUPP; } /*! \brief handle USB Get_Descriptor request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req) { uint8_t desc_type = 0; uint8_t desc_index = 0; usb_transc *transc = &udev->dev.transc_in[0]; /* get device standard descriptor */ switch (req->bmRequestType & USB_RECPTYPE_MASK) { case USB_RECPTYPE_DEV: desc_type = BYTE_HIGH(req->wValue); desc_index = BYTE_LOW(req->wValue); switch (desc_type) { case USB_DESCTYPE_DEV: transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); if (64U == req->wLength) { transc->remain_len = 8U; } break; case USB_DESCTYPE_CONFIG: transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); break; case USB_DESCTYPE_STR: if (desc_index < STR_IDX_MAX) { transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); } break; case USB_DESCTYPE_ITF: case USB_DESCTYPE_EP: case USB_DESCTYPE_DEV_QUALIFIER: case USB_DESCTYPE_OTHER_SPD_CONFIG: case USB_DESCTYPE_ITF_POWER: break; case USB_DESCTYPE_BOS: transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *)&(transc->remain_len)); break; default: break; } break; case USB_RECPTYPE_ITF: /* get device class special descriptor */ { uint8_t res = udev->dev.class_core->req_proc(udev, req); return (usb_reqsta)res; } case USB_RECPTYPE_EP: break; default: break; } if ((0U != transc->remain_len) && (0U != req->wLength)) { if (transc->remain_len < req->wLength) { if ((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { udev->dev.control.ctl_zlp = 1; } } else { transc->remain_len = req->wLength; } return REQ_SUPP; } return REQ_NOTSUPP; } /*! \brief handle USB Set_Descriptor request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req) { /* no handle... */ return REQ_SUPP; } /*! \brief handle USB Get_Configuration request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req) { usb_transc *transc = &udev->dev.transc_in[0]; switch (udev->dev.cur_status) { case USBD_ADDRESSED: if (USB_DEFAULT_CONFIG == udev->dev.config) { transc->xfer_buf = &(udev->dev.config); transc->remain_len = 1U; return REQ_SUPP; } break; case USBD_CONFIGURED: if (udev->dev.config != USB_DEFAULT_CONFIG) { transc->xfer_buf = &(udev->dev.config); transc->remain_len = 1U; return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB Set_Configuration request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req) { static uint8_t config; config = (uint8_t)(req->wValue); if (config <= USBD_CFG_MAX_NUM) { switch (udev->dev.cur_status) { case USBD_ADDRESSED: if (config) { udev->dev.class_core->init(udev, config); udev->dev.config = config; udev->dev.cur_status = USBD_CONFIGURED; } return REQ_SUPP; case USBD_CONFIGURED: if (USB_DEFAULT_CONFIG == config) { udev->dev.class_core->deinit(udev, config); udev->dev.config = config; udev->dev.cur_status = USBD_ADDRESSED; } else if (config != udev->dev.config) { /* clear old configuration */ udev->dev.class_core->deinit(udev, config); /* set new configuration */ udev->dev.config = config; udev->dev.class_core->init(udev, config); } return REQ_SUPP; case USBD_DEFAULT: break; default: break; } } return REQ_NOTSUPP; } /*! \brief handle USB Get_Interface request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req) { switch (udev->dev.cur_status) { case USBD_DEFAULT: break; case USBD_ADDRESSED: break; case USBD_CONFIGURED: if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { usb_transc *transc = &udev->dev.transc_in[0]; transc->xfer_buf = &(udev->dev.class_core->alter_set); transc->remain_len = 1U; return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB Set_Interface request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req) { switch (udev->dev.cur_status) { case USBD_DEFAULT: break; case USBD_ADDRESSED: break; case USBD_CONFIGURED: if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { udev->dev.class_core->alter_set = req->wValue; return REQ_SUPP; } break; default: break; } return REQ_NOTSUPP; } /*! \brief handle USB SynchFrame request \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval USB device request status */ static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req) { /* no handle... */ return REQ_SUPP; } /*! \brief handle USB enumeration error \param[in] udev: pointer to USB device instance \param[in] req: pointer to USB device request \param[out] none \retval none */ void usbd_enum_error(usb_core_driver *udev, usb_req *req) { usbd_ep_stall(udev, 0x80); usbd_ep_stall(udev, 0x00); usb_ctlep_startout(udev); } /*! \brief convert hex 32bits value into unicode char \param[in] value: hex 32bits value \param[in] pbuf: buffer pointer to store unicode char \param[in] len: value length \param[out] none \retval none */ void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len) { uint8_t index = 0; for (index = 0; index < len; index++) { if ((value >> 28) < 0x0A) { pbuf[2 * index] = (value >> 28) + '0'; } else { pbuf[2 * index] = (value >> 28) + 'A' - 10; } value = value << 4; pbuf[2 * index + 1] = 0; } } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbd_transc.c ================================================ /*! \file usbd_transc.c \brief USB transaction core functions \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbd_transc.h" #include "usbd_enum.h" /*! \brief USB send data in the control transaction \param[in] udev: pointer to USB device instance \param[out] none \retval USB device operation cur_status */ usbd_status usbd_ctl_send(usb_core_driver *udev) { usb_transc *transc = &udev->dev.transc_in[0]; usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); if (transc->remain_len > transc->max_len) { udev->dev.control.ctl_state = USB_CTL_DATA_IN; } else { udev->dev.control.ctl_state = USB_CTL_LAST_DATA_IN; } return USBD_OK; } /*! \brief USB receive data in control transaction \param[in] udev: pointer to USB device instance \param[out] none \retval USB device operation cur_status */ usbd_status usbd_ctl_recev(usb_core_driver *udev) { usb_transc *transc = &udev->dev.transc_out[0]; usbd_ep_recev(udev, 0U, transc->xfer_buf, transc->remain_len); if (transc->remain_len > transc->max_len) { udev->dev.control.ctl_state = USB_CTL_DATA_OUT; } else { udev->dev.control.ctl_state = USB_CTL_LAST_DATA_OUT; } return USBD_OK; } /*! \brief USB send control transaction status \param[in] udev: pointer to USB device instance \param[out] none \retval USB device operation cur_status */ usbd_status usbd_ctl_status_send(usb_core_driver *udev) { udev->dev.control.ctl_state = USB_CTL_STATUS_IN; usbd_ep_send(udev, 0U, NULL, 0U); usb_ctlep_startout(udev); return USBD_OK; } /*! \brief USB control receive status \param[in] udev: pointer to USB device instance \param[out] none \retval USB device operation cur_status */ usbd_status usbd_ctl_status_recev(usb_core_driver *udev) { udev->dev.control.ctl_state = USB_CTL_STATUS_OUT; usbd_ep_recev(udev, 0, NULL, 0); usb_ctlep_startout(udev); return USBD_OK; } /*! \brief USB setup stage processing \param[in] udev: pointer to USB device instance \param[out] none \retval USB device operation cur_status */ uint8_t usbd_setup_transc(usb_core_driver *udev) { usb_reqsta reqstat = REQ_NOTSUPP; usb_req req = udev->dev.control.req; switch (req.bmRequestType & USB_REQTYPE_MASK) { /* standard device request */ case USB_REQTYPE_STRD: reqstat = usbd_standard_request(udev, &req); break; /* device class request */ case USB_REQTYPE_CLASS: reqstat = usbd_class_request(udev, &req); break; /* vendor defined request */ case USB_REQTYPE_VENDOR: reqstat = usbd_vendor_request(udev, &req); break; default: break; } if (REQ_SUPP == reqstat) { if (req.wLength == 0) { usbd_ctl_status_send(udev); } else { if (req.bmRequestType & 0x80) { usbd_ctl_send(udev); } else { usbd_ctl_recev(udev); } } } else { usbd_enum_error(udev, &req); } return USBD_OK; } /*! \brief data out stage processing \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier(0..7) \param[out] none \retval USB device operation cur_status */ uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num) { if (ep_num == 0) { usb_transc *transc = &udev->dev.transc_out[0]; switch (udev->dev.control.ctl_state) { case USB_CTL_DATA_OUT: /* update transfer length */ transc->remain_len -= transc->max_len; usbd_ctl_recev(udev); break; case USB_CTL_LAST_DATA_OUT: if (udev->dev.cur_status == USBD_CONFIGURED) { if (udev->dev.class_core->data_out != NULL) { udev->dev.class_core->data_out(udev, 0U); } } transc->remain_len = 0U; usbd_ctl_status_send(udev); break; default: break; } } else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == USBD_CONFIGURED)) { udev->dev.class_core->data_out(udev, ep_num); } return USBD_OK; } /*! \brief data in stage processing \param[in] udev: pointer to USB device instance \param[in] ep_num: endpoint identifier(0..7) \param[out] none \retval USB device operation cur_status */ uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) { if (0U == ep_num) { usb_transc *transc = &udev->dev.transc_in[0]; switch (udev->dev.control.ctl_state) { case USB_CTL_DATA_IN: /* update transfer length */ transc->remain_len -= transc->max_len; usbd_ctl_send(udev); break; case USB_CTL_LAST_DATA_IN: /* last packet is MPS multiple, so send ZLP packet */ if (udev->dev.control.ctl_zlp) { usbd_ep_send(udev, 0U, NULL, 0U); udev->dev.control.ctl_zlp = 0U; } else { if (udev->dev.cur_status == USBD_CONFIGURED) { if (udev->dev.class_core->data_in != NULL) { udev->dev.class_core->data_in(udev, 0U); } } transc->remain_len = 0U; usbd_ctl_status_recev(udev); } break; default: break; } } else { if ((udev->dev.cur_status == USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { udev->dev.class_core->data_in(udev, ep_num); } } return USBD_OK; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_core.c ================================================ /*! \file usbh_core.c \brief USB host core state machine driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbh_core.h" #include "drv_usb_hw.h" #include "drv_usbh_int.h" #include "usbh_enum.h" #include "usbh_pipe.h" uint8_t usbh_sof(usb_core_driver *pudev); usbh_int_cb usbh_int_op = {usbh_sof}; usbh_int_cb *usbh_int_fop = &usbh_int_op; static usbh_status usbh_enum_task(usb_core_driver *pudev, usbh_host *puhost); /*! \brief USB SOF callback function from the interrupt \param[in] pudev: pointer to usb core instance \param[out] none \retval operation status */ uint8_t usbh_sof(usb_core_driver *pudev) { /* this callback could be used to implement a scheduler process */ return 0U; } /*! \brief USB host stack initializations \param[in] pudev: pointer to usb core instance \param[in] core: USBFS core or USBHS core \param[in] puhost: pointer to USB host \param[out] none \retval operation status */ void usbh_init(usb_core_driver *pudev, usb_core_enum core, usbh_host *puhost) { uint8_t i = 0U; /* host de-initializations */ usbh_deinit(pudev, puhost); pudev->host.connect_status = 0U; for (i = 0U; i < USBFS_MAX_TX_FIFOS; i++) { pudev->host.pipe[i].err_count = 0U; pudev->host.pipe[i].pp_status = PIPE_IDLE; pudev->host.backup_xfercount[i] = 0U; } pudev->host.pipe[0].ep.mps = 8U; usb_basic_init(&pudev->bp, &pudev->regs, core); #ifndef DUAL_ROLE_MODE_ENABLED usb_core_init(pudev->bp, &pudev->regs); usb_host_init(pudev); #endif /* DUAL_ROLE_MODE_ENABLED */ /* upon init call usr call back */ puhost->usr_cb->dev_init(); } /*! \brief de-initialize USB host \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to USB host \param[out] none \retval operation status */ usbh_status usbh_deinit(usb_core_driver *pudev, usbh_host *puhost) { /* software init */ puhost->cur_state = HOST_DEFAULT; puhost->backup_state = HOST_DEFAULT; puhost->enum_state = ENUM_DEFAULT; puhost->control.ctl_state = CTL_IDLE; puhost->control.max_len = USB_FS_EP0_MAX_LEN; puhost->dev_prop.addr = USBH_DEV_ADDR_DEFAULT; puhost->dev_prop.speed = PORT_SPEED_FULL; usbh_pipe_free(pudev, puhost->control.pipe_in_num); usbh_pipe_free(pudev, puhost->control.pipe_out_num); return USBH_OK; } /*! \brief USB host core main state machine process \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ void usbh_core_task(usb_core_driver *pudev, usbh_host *puhost) { volatile usbh_status status = USBH_FAIL; /* check for host port events */ if (((0U == pudev->host.connect_status) || (0U == pudev->host.port_enabled)) && (HOST_DEFAULT != puhost->cur_state)) { if (puhost->cur_state != HOST_DEV_DETACHED) { puhost->cur_state = HOST_DEV_DETACHED; } } switch (puhost->cur_state) { case HOST_DEFAULT: if (pudev->host.connect_status) { puhost->cur_state = HOST_DETECT_DEV_SPEED; usb_mdelay(100U); // usb_mdelay (2U); usb_port_reset(pudev); puhost->usr_cb->dev_reset(); } break; case HOST_DETECT_DEV_SPEED: if (pudev->host.port_enabled) { puhost->cur_state = HOST_DEV_ATTACHED; puhost->dev_prop.speed = usb_curspeed_get(pudev); puhost->usr_cb->dev_speed_detected(puhost->dev_prop.speed); usb_mdelay(50U); } break; case HOST_DEV_ATTACHED: puhost->usr_cb->dev_attach(); puhost->control.pipe_out_num = usbh_pipe_allocate(pudev, 0x00U); puhost->control.pipe_in_num = usbh_pipe_allocate(pudev, 0x80U); /* reset USB device */ usb_port_reset(pudev); /* open IN control pipe */ usbh_pipe_create(pudev, &puhost->dev_prop, puhost->control.pipe_in_num, USB_EPTYPE_CTRL, puhost->control.max_len); /* open OUT control pipe */ usbh_pipe_create(pudev, &puhost->dev_prop, puhost->control.pipe_out_num, USB_EPTYPE_CTRL, puhost->control.max_len); puhost->cur_state = HOST_ENUM; break; case HOST_ENUM: /* check for enumeration status */ if (USBH_OK == usbh_enum_task(pudev, puhost)) { /* the function shall return USBH_OK when full enumeration is complete */ /* user callback for end of device basic enumeration */ puhost->usr_cb->dev_enumerated(); puhost->cur_state = HOST_USER_INPUT; } break; case HOST_USER_INPUT: /* the function should return user response true to move to class state */ if (USBH_USER_RESP_OK == puhost->usr_cb->dev_user_input()) { if ((USBH_OK == puhost->class_cb->class_init(pudev, puhost))) { puhost->cur_state = HOST_CLASS_ENUM; } } break; case HOST_CLASS_ENUM: /* process class standard contol requests state machine */ status = puhost->class_cb->class_requests(pudev, puhost); if (USBH_OK == status) { puhost->cur_state = HOST_CLASS_HANDLER; } else { usbh_error_handler(puhost, status); } break; case HOST_CLASS_HANDLER: /* process class state machine */ status = puhost->class_cb->class_machine(pudev, puhost); usbh_error_handler(puhost, status); break; case HOST_SUSPENDED: break; case HOST_ERROR: /* re-initilaize host for new enumeration */ usbh_deinit(pudev, puhost); puhost->usr_cb->dev_deinit(); puhost->class_cb->class_deinit(pudev, puhost); break; case HOST_DEV_DETACHED: /* manage user disconnect operations*/ puhost->usr_cb->dev_detach(); /* re-initilaize host for new enumeration */ usbh_deinit(pudev, puhost); puhost->usr_cb->dev_deinit(); puhost->class_cb->class_deinit(pudev, puhost); usbh_pipe_delete(pudev); puhost->cur_state = HOST_DEFAULT; break; default: break; } } /*! \brief handle the error on USB host side \param[in] puhost: pointer to USB host \param[in] err_type: type of error or busy/OK state \param[out] none \retval none */ void usbh_error_handler(usbh_host *puhost, usbh_status err_type) { /* error unrecovered or not supported device speed */ if ((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) { puhost->usr_cb->dev_error(); puhost->cur_state = HOST_ERROR; } else if (USBH_APPLY_DEINIT == err_type) { puhost->cur_state = HOST_ERROR; /* user callback for initalization */ puhost->usr_cb->dev_init(); } } /*! \brief handle the USB enumeration task \param[in] pudev: pointer to selected USB device \param[in] puhost: pointer to host \param[out] none \retval none */ static usbh_status usbh_enum_task(usb_core_driver *pudev, usbh_host *puhost) { uint8_t str_buf[64]; usbh_status status = USBH_BUSY; static uint8_t index_mfc_str = 0U, index_prod_str = 0U, index_serial_str = 0U; switch (puhost->enum_state) { case ENUM_DEFAULT: /* get device descriptor for only 1st 8 bytes : to get ep0 maxpacketsize */ if (USBH_OK == usbh_devdesc_get(pudev, puhost, 8U)) { puhost->control.max_len = puhost->dev_prop.dev_desc.bMaxPacketSize0; /* issue reset */ usb_port_reset(pudev); /* modify control channels configuration for maximum packet size */ usbh_pipe_update(pudev, puhost->control.pipe_out_num, 0U, 0U, puhost->control.max_len); usbh_pipe_update(pudev, puhost->control.pipe_in_num, 0U, 0U, puhost->control.max_len); puhost->enum_state = ENUM_GET_DEV_DESC; } break; case ENUM_GET_DEV_DESC: /* get full device descriptor */ if (USBH_OK == usbh_devdesc_get(pudev, puhost, USB_DEV_DESC_LEN)) { puhost->usr_cb->dev_devdesc_assigned(&puhost->dev_prop.dev_desc); index_mfc_str = puhost->dev_prop.dev_desc.iManufacturer; index_prod_str = puhost->dev_prop.dev_desc.iProduct; index_serial_str = puhost->dev_prop.dev_desc.iSerialNumber; puhost->enum_state = ENUM_SET_ADDR; } break; case ENUM_SET_ADDR: /* set address */ if (USBH_OK == usbh_setaddress(pudev, puhost, USBH_DEV_ADDR)) { usb_mdelay(2); puhost->dev_prop.addr = USBH_DEV_ADDR; /* user callback for device address assigned */ puhost->usr_cb->dev_address_set(); /* modify control channels to update device address */ usbh_pipe_update(pudev, puhost->control.pipe_in_num, puhost->dev_prop.addr, 0U, 0U); usbh_pipe_update(pudev, puhost->control.pipe_out_num, puhost->dev_prop.addr, 0U, 0U); puhost->enum_state = ENUM_GET_CFG_DESC; } break; case ENUM_GET_CFG_DESC: /* get standard configuration descriptor */ if (USBH_OK == usbh_cfgdesc_get(pudev, puhost, USB_CFG_DESC_LEN)) { puhost->enum_state = ENUM_GET_CFG_DESC_SET; } break; case ENUM_GET_CFG_DESC_SET: /* get full config descriptor (config, interface, endpoints) */ if (USBH_OK == usbh_cfgdesc_get(pudev, puhost, puhost->dev_prop.cfg_desc.wTotalLength)) { /* user callback for configuration descriptors available */ puhost->usr_cb->dev_cfgdesc_assigned(&puhost->dev_prop.cfg_desc, puhost->dev_prop.itf_desc, puhost->dev_prop.ep_desc[0]); puhost->enum_state = ENUM_GET_STR_DESC; } break; case ENUM_GET_STR_DESC: if (index_mfc_str) { if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iManufacturer, str_buf, 0xFFU)) { /* user callback for manufacturing string */ puhost->usr_cb->dev_mfc_str(str_buf); index_mfc_str = 0U; } } else { if (index_prod_str) { /* check that product string is available */ if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iProduct, str_buf, 0xFFU)) { puhost->usr_cb->dev_prod_str(str_buf); index_prod_str = 0U; } } else { if (index_serial_str) { if (USBH_OK == usbh_strdesc_get(pudev, puhost, puhost->dev_prop.dev_desc.iSerialNumber, str_buf, 0xFFU)) { puhost->usr_cb->dev_seral_str(str_buf); puhost->enum_state = ENUM_SET_CONFIGURATION; index_serial_str = 0U; } } else { puhost->enum_state = ENUM_SET_CONFIGURATION; } } } break; case ENUM_SET_CONFIGURATION: if (USBH_OK == usbh_setcfg(pudev, puhost, puhost->dev_prop.cfg_desc.bConfigurationValue)) { puhost->enum_state = ENUM_DEV_CONFIGURED; } break; case ENUM_DEV_CONFIGURED: status = USBH_OK; break; default: break; } return status; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_enum.c ================================================ /*! \file usbh_enum.c \brief USB host mode enumberation driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbh_enum.h" #include "usbh_transc.h" static void usbh_devdesc_parse(usb_desc_dev *cfg_desc, uint8_t *buf, uint16_t len); static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf); static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf); static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf); static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf); static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len); /*! \brief configure USB control status parameters \param[in] puhost: pointer to usb host \param[in] buf: control transfer data buffer pointer \param[in] len: length of the data buffer \param[out] none \retval none */ void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len) { /* prepare the transactions */ puhost->control.buf = buf; puhost->control.ctl_len = len; puhost->control.ctl_state = CTL_SETUP; } /*! \brief get device descriptor from the USB device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] len: length of the descriptor \param[out] none \retval operation status */ usbh_status usbh_devdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t len) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_DEV), .wIndex = 0U, .wLength = len}; usbh_ctlstate_config(puhost, pudev->host.rx_buf, len); } status = usbh_ctl_handler(pudev, puhost); if (USBH_OK == status) { /* commands successfully sent and response received */ usbh_devdesc_parse(&puhost->dev_prop.dev_desc, pudev->host.rx_buf, len); } return status; } /*! \brief get configuration descriptor from the USB device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] len: length of the descriptor \param[out] none \retval operation status */ usbh_status usbh_cfgdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint16_t len) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), .wIndex = 0U, .wLength = len}; usbh_ctlstate_config(puhost, pudev->host.rx_buf, len); } status = usbh_ctl_handler(pudev, puhost); if (USBH_OK == status) { if (len <= USB_CFG_DESC_LEN) { usbh_cfgdesc_parse(&puhost->dev_prop.cfg_desc, pudev->host.rx_buf); } else { usbh_cfgset_parse(&puhost->dev_prop, pudev->host.rx_buf); } } return status; } /*! \brief get string descriptor from the USB device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] str_index: index for the string descriptor \param[in] buf: buffer pointer to the string descriptor \param[in] len: length of the descriptor \param[out] none \retval operation status */ usbh_status usbh_strdesc_get(usb_core_driver *pudev, usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){ .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_GET_DESCRIPTOR, .wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index, .wIndex = 0x0409U, .wLength = len}; usbh_ctlstate_config(puhost, pudev->host.rx_buf, len); } status = usbh_ctl_handler(pudev, puhost); if (USBH_OK == status) { /* commands successfully sent and response received */ usbh_strdesc_parse(pudev->host.rx_buf, buf, len); } return status; } /*! \brief set the address to the connected device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] dev_addr: device address to assign \param[out] none \retval operation status */ usbh_status usbh_setaddress(usb_core_driver *pudev, usbh_host *puhost, uint8_t dev_addr) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_SET_ADDRESS, .wValue = (uint16_t)dev_addr, .wIndex = 0U, .wLength = 0U}; usbh_ctlstate_config(puhost, NULL, 0U); } status = usbh_ctl_handler(pudev, puhost); return status; } /*! \brief set the configuration value to the connected device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] config_index: configuration value \param[out] none \retval operation status */ usbh_status usbh_setcfg(usb_core_driver *pudev, usbh_host *puhost, uint16_t config_index) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, .bRequest = USB_SET_CONFIGURATION, .wValue = config_index, .wIndex = 0U, .wLength = 0U}; usbh_ctlstate_config(puhost, NULL, 0U); } status = usbh_ctl_handler(pudev, puhost); return status; } /*! \brief set the interface value to the connected device \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] ep_num: endpoint number \param[in] alter_setting: altnated setting value \param[out] none \retval operation status */ usbh_status usbh_setinterface(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_num, uint8_t set) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, .bRequest = USB_SET_INTERFACE, .wValue = set, .wIndex = ep_num, .wLength = 0U}; usbh_ctlstate_config(puhost, NULL, 0U); } status = usbh_ctl_handler(pudev, puhost); return status; } /*! \brief clear or disable a specific feature \param[in] pudev: pointer to usb core instance \param[in] puhost: pointer to usb host \param[in] ep_addr: endpoint address \param[in] pp_num: pipe number \param[out] none \retval operation status */ usbh_status usbh_clrfeature(usb_core_driver *pudev, usbh_host *puhost, uint8_t ep_addr, uint8_t pp_num) { usbh_status status = USBH_BUSY; usbh_control *usb_ctl = &puhost->control; if (CTL_IDLE == usb_ctl->ctl_state) { usb_ctl->setup.req = (usb_req){.bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD, .bRequest = USB_CLEAR_FEATURE, .wValue = FEATURE_SELECTOR_EP, .wIndex = ep_addr, .wLength = 0}; if (EP_DIR(ep_addr)) { pudev->host.pipe[pp_num].data_toggle_in = 0U; } else { pudev->host.pipe[pp_num].data_toggle_out = 0U; } usbh_ctlstate_config(puhost, NULL, 0U); } status = usbh_ctl_handler(pudev, puhost); return status; } /*! \brief parse the device descriptor \param[in] dev_desc: pointer to usb device descriptor buffer \param[in] buf: pointer to the source descriptor buffer \param[in] len: length of the descriptor \param[out] none \retval operation status */ static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) { *dev_desc = (usb_desc_dev){ .header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)}, .bcdUSB = BYTE_SWAP(buf + 2U), .bDeviceClass = *(uint8_t *)(buf + 4U), .bDeviceSubClass = *(uint8_t *)(buf + 5U), .bDeviceProtocol = *(uint8_t *)(buf + 6U), .bMaxPacketSize0 = *(uint8_t *)(buf + 7U) }; if (len > 8U) { /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ dev_desc->idVendor = BYTE_SWAP(buf + 8U); dev_desc->idProduct = BYTE_SWAP(buf + 10U); dev_desc->bcdDevice = BYTE_SWAP(buf + 12U); dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); dev_desc->iProduct = *(uint8_t *)(buf + 15U); dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); } } /*! \brief parse the configuration descriptor \param[in] cfg_desc: pointer to usb configuration descriptor buffer \param[in] buf: pointer to the source descriptor buffer \param[out] none \retval operation status */ static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf) { /* parse configuration descriptor */ *cfg_desc = (usb_desc_config){ .header = { .bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U), }, .wTotalLength = BYTE_SWAP(buf + 2U), .bNumInterfaces = *(uint8_t *)(buf + 4U), .bConfigurationValue = *(uint8_t *)(buf + 5U), .iConfiguration = *(uint8_t *)(buf + 6U), .bmAttributes = *(uint8_t *)(buf + 7U), .bMaxPower = *(uint8_t *)(buf + 8U) }; } /*! \brief parse the configuration descriptor set \param[in] udev: pointer to USB core instance \param[in] buf: pointer to the source descriptor buffer \param[out] none \retval operation status */ static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf) { usb_desc_ep *ep = NULL; usb_desc_itf *itf = NULL, itf_value; usb_desc_header *pdesc = (usb_desc_header *)buf; int8_t itf_index = 0U, ep_index = 0U; uint16_t ptr; uint8_t prev_itf = 0U; uint16_t prev_ep_len = 0U; /* parse configuration descriptor */ usbh_cfgdesc_parse(&udev->cfg_desc, buf); ptr = USB_CFG_DESC_LEN; if (udev->cfg_desc.bNumInterfaces > USBH_MAX_INTERFACES_NUM) { return; } while (ptr < udev->cfg_desc.wTotalLength) { pdesc = usbh_nextdesc_get((uint8_t *)pdesc, &ptr); if (pdesc->bDescriptorType == USB_DESCTYPE_ITF) { itf_index = *(((uint8_t *)pdesc) + 2U); itf = &udev->itf_desc[itf_index]; if ((*((uint8_t *)pdesc + 3U)) < 3U) { usbh_itfdesc_parse(&itf_value, (uint8_t *)pdesc); /* parse endpoint descriptors relative to the current interface */ if (itf_value.bNumEndpoints > USBH_MAX_EP_NUM) { return; } for (ep_index = 0; ep_index < itf_value.bNumEndpoints;) { pdesc = usbh_nextdesc_get((void *)pdesc, &ptr); if (pdesc->bDescriptorType == USB_DESCTYPE_EP) { ep = &udev->ep_desc[itf_index][ep_index]; if (prev_itf != itf_index) { prev_itf = itf_index; usbh_itfdesc_parse(itf, (uint8_t *)&itf_value); } else { if (prev_ep_len > BYTE_SWAP((uint8_t *)pdesc + 4U)) { break; } else { usbh_itfdesc_parse(itf, (uint8_t *)&itf_value); } } usbh_epdesc_parse(ep, (uint8_t *)pdesc); prev_ep_len = BYTE_SWAP((uint8_t *)pdesc + 4U); ep_index++; } } } } } } /*! \brief parse the interface descriptor \param[in] itf_desc: pointer to usb interface descriptor buffer \param[in] buf: pointer to the source descriptor buffer \param[out] none \retval operation status */ static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf) { *itf_desc = (usb_desc_itf){ .header = { .bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U), }, .bInterfaceNumber = *(uint8_t *)(buf + 2U), .bAlternateSetting = *(uint8_t *)(buf + 3U), .bNumEndpoints = *(uint8_t *)(buf + 4U), .bInterfaceClass = *(uint8_t *)(buf + 5U), .bInterfaceSubClass = *(uint8_t *)(buf + 6U), .bInterfaceProtocol = *(uint8_t *)(buf + 7U), .iInterface = *(uint8_t *)(buf + 8U) }; } /*! \brief parse the endpoint descriptor \param[in] ep_desc: pointer to usb endpoint descriptor buffer \param[in] buf: pointer to the source descriptor buffer \param[out] none \retval operation status */ static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf) { *ep_desc = (usb_desc_ep){ .header = {.bLength = *(uint8_t *)(buf + 0U), .bDescriptorType = *(uint8_t *)(buf + 1U)}, .bEndpointAddress = *(uint8_t *)(buf + 2U), .bmAttributes = *(uint8_t *)(buf + 3U), .wMaxPacketSize = BYTE_SWAP(buf + 4U), .bInterval = *(uint8_t *)(buf + 6U) }; } /*! \brief parse the string descriptor \param[in] psrc: source pointer containing the descriptor data \param[in] pdest: destination address pointer \param[in] len: length of the descriptor \param[out] none \retval operation status */ static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len) { uint16_t str_len = 0U, index = 0U; /* the unicode string descriptor is not NULL-terminated. The string length is * computed by substracting two from the value of the first byte of the descriptor. */ /* check which is lower size, the size of string or the length of bytes read from the device */ if (USB_DESCTYPE_STR == psrc[1]) { /* make sure the descriptor is string type */ /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ str_len = USB_MIN(psrc[0] - 2U, len); psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */ for (index = 0U; index < str_len; index += 2U) { /* copy only the string and ignore the unicode id, hence add the src */ *pdest = psrc[index]; pdest++; } *pdest = 0U; /* mark end of string */ } } /*! \brief get the next descriptor header \param[in] pbuf: pointer to buffer where the configuration descriptor set is available \param[in] ptr: data popinter inside the configuration descriptor set \param[out] none \retval operation status */ usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr) { usb_desc_header *pnext; *ptr += ((usb_desc_header *)pbuf)->bLength; pnext = (usb_desc_header *)((uint8_t *)pbuf + ((usb_desc_header *)pbuf)->bLength); return (pnext); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_pipe.c ================================================ /*! \file usbh_pipe.c \brief USB host mode pipe operation driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbh_pipe.h" static uint16_t usbh_freepipe_get(usb_core_driver *pudev); /*! \brief create a pipe \param[in] pudev: pointer to usb core instance \param[in] pp_num: pipe number \param[in] udev: USB device \param[in] ep_type: endpoint type \param[in] ep_mpl: endpoint max packet length \param[out] none \retval operation status */ uint8_t usbh_pipe_create(usb_core_driver *pudev, usb_dev_prop *udev, uint8_t pp_num, uint8_t ep_type, uint16_t ep_mpl) { usb_pipe *pp = &pudev->host.pipe[pp_num]; pp->dev_addr = udev->addr; pp->dev_speed = udev->speed; pp->ep.type = ep_type; pp->ep.mps = ep_mpl; pp->ping = udev->speed == PORT_SPEED_HIGH; usb_pipe_init(pudev, pp_num); return HC_OK; } /*! \brief modify a pipe \param[in] pudev: pointer to usb core instance \param[in] pp_num: pipe number \param[in] dev_addr: device address \param[in] dev_speed: device speed \param[in] ep_type: endpoint type \param[in] ep_mpl: endpoint max packet length \param[out] none \retval operation status */ uint8_t usbh_pipe_update(usb_core_driver *pudev, uint8_t pp_num, uint8_t dev_addr, uint32_t dev_speed, uint16_t ep_mpl) { usb_pipe *pp = &pudev->host.pipe[pp_num]; if ((pp->dev_addr != dev_addr) && (dev_addr)) { pp->dev_addr = dev_addr; } if ((pp->dev_speed != dev_speed) && (dev_speed)) { pp->dev_speed = dev_speed; } if ((pp->ep.mps != ep_mpl) && (ep_mpl)) { pp->ep.mps = ep_mpl; } usb_pipe_init(pudev, pp_num); return HC_OK; } /*! \brief allocate a new pipe \param[in] pudev: pointer to usb core instance \param[in] ep_addr: endpoint address \param[out] none \retval operation status */ uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr) { uint16_t pp_num = usbh_freepipe_get(pudev); if (HC_ERROR != pp_num) { pudev->host.pipe[pp_num].in_used = 1U; pudev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr); pudev->host.pipe[pp_num].ep.num = EP_ID(ep_addr); } return pp_num; } /*! \brief free a pipe \param[in] pudev: pointer to usb core instance \param[in] pp_num: pipe number \param[out] none \retval operation status */ uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num) { if (pp_num < HC_MAX) { pudev->host.pipe[pp_num].in_used = 0U; } return USBH_OK; } /*! \brief delete all USB host pipe \param[in] pudev: pointer to usb core instance \param[out] none \retval operation status */ uint8_t usbh_pipe_delete(usb_core_driver *pudev) { uint8_t pp_num = 0U; for (pp_num = 2U; pp_num < HC_MAX; pp_num++) { pudev->host.pipe[pp_num] = (usb_pipe){0}; } return USBH_OK; } /*! \brief get a free pipe number for allocation \param[in] pudev: pointer to usb core instance \param[out] none \retval operation status */ static uint16_t usbh_freepipe_get(usb_core_driver *pudev) { uint8_t pp_num = 0U; for (pp_num = 0U; pp_num < HC_MAX; pp_num++) { if (pudev->host.pipe[pp_num].in_used == 0U) { return pp_num; } } return HC_ERROR; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/Usb/usbh_transc.c ================================================ /*! \file usbh_transc.c \brief USB host mode transactions driver \version 2019-6-5, V1.0.0, firmware for GD32 USBFS&USBHS */ /* Copyright (c) 2019, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "usbh_transc.h" #include "drv_usb_hw.h" /*! \brief prepare a pipe and start a transfer \param[in] pudev: pointer to usb core instance \param[in] pp_num: pipe number \param[out] none \retval operation status */ static uint32_t usbh_request_submit(usb_core_driver *pudev, uint8_t pp_num) { pudev->host.pipe[pp_num].urb_state = URB_IDLE; pudev->host.pipe[pp_num].xfer_count = 0U; return usb_pipe_xfer(pudev, pp_num); } /*! \brief send the setup packet to the USB device \param[in] pudev: pointer to usb core instance \param[in] buf: data buffer which will be sent to USB device \param[in] pp_num: pipe number \param[out] none \retval operation status */ usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num) { usb_pipe *pp = &pudev->host.pipe[pp_num]; pp->DPID = PIPE_DPID_SETUP; pp->xfer_buf = buf; pp->xfer_len = USB_SETUP_PACKET_LEN; uint32_t res = usbh_request_submit(pudev, pp_num); return (usbh_status)res; } /*! \brief send a data packet to the USB device \param[in] pudev: pointer to usb core instance \param[in] buf: data buffer which will be sent to USB device \param[in] pp_num: pipe number \param[in] len: length of the data to be sent \param[out] none \retval operation status */ usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) { usb_pipe *pp = &pudev->host.pipe[pp_num]; pp->xfer_buf = buf; pp->xfer_len = len; switch (pp->ep.type) { case USB_EPTYPE_CTRL: if (0U == len) { pp->data_toggle_out = 1U; } pp->DPID = PIPE_DPID[pp->data_toggle_out]; break; case USB_EPTYPE_INTR: pp->DPID = PIPE_DPID[pp->data_toggle_out]; pp->data_toggle_out ^= 1U; break; case USB_EPTYPE_BULK: pp->DPID = PIPE_DPID[pp->data_toggle_out]; break; case USB_EPTYPE_ISOC: pp->DPID = PIPE_DPID[0]; break; default: break; } usbh_request_submit(pudev, pp_num); return USBH_OK; } /*! \brief receive a data packet from the USB device \param[in] pudev: pointer to usb core instance \param[in] buf: data buffer which will be received from USB device \param[in] pp_num: pipe number \param[in] len: length of the data to be received \param[out] none \retval operation status */ usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) { usb_pipe *pp = &pudev->host.pipe[pp_num]; pp->xfer_buf = buf; pp->xfer_len = len; switch (pp->ep.type) { case USB_EPTYPE_CTRL: pp->DPID = PIPE_DPID[1]; break; case USB_EPTYPE_INTR: pp->DPID = PIPE_DPID[pp->data_toggle_in]; /* Toggle DATA PID */ pp->data_toggle_in ^= 1U; break; case USB_EPTYPE_BULK: pp->DPID = PIPE_DPID[pp->data_toggle_in]; break; case USB_EPTYPE_ISOC: pp->DPID = PIPE_DPID[0]; break; default: break; } usbh_request_submit(pudev, pp_num); return USBH_OK; } /*! \brief wait for USB URB(USB request block) state \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[in] pp_num: pipe number \param[in] wait_time: wait time \param[out] none \retval USB URB state */ static usb_urb_state usbh_urb_wait(usb_core_driver *pudev, usbh_host *puhost, uint8_t pp_num, uint32_t wait_time) { usb_urb_state urb_status = URB_IDLE; while (URB_DONE != (urb_status = usbh_urbstate_get(pudev, pp_num))) { if (URB_NOTREADY == urb_status) { break; } else if (URB_STALL == urb_status) { puhost->control.ctl_state = CTL_SETUP; break; } else if (URB_ERROR == urb_status) { puhost->control.ctl_state = CTL_ERROR; break; } else if ((wait_time > 0U) && ((usb_curframe_get(pudev) - puhost->control.timer) > wait_time)) { /* timeout for in transfer */ puhost->control.ctl_state = CTL_ERROR; break; } else { /* no operation, just wait */ } } return urb_status; } /*! \brief USB setup transaction \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ static void usbh_setup_transc(usb_core_driver *pudev, usbh_host *puhost) { usb_urb_state urb_status = URB_IDLE; /* send a SETUP packet */ usbh_ctlsetup_send(pudev, puhost->control.setup.data, puhost->control.pipe_out_num); urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_out_num, 0U); if (URB_DONE == urb_status) { uint8_t dir = (puhost->control.setup.req.bmRequestType & USB_TRX_MASK); if (puhost->control.setup.req.wLength) { if (USB_TRX_IN == dir) { puhost->control.ctl_state = CTL_DATA_IN; } else { puhost->control.ctl_state = CTL_DATA_OUT; } } else { if (USB_TRX_IN == dir) { puhost->control.ctl_state = CTL_STATUS_OUT; } else { puhost->control.ctl_state = CTL_STATUS_IN; } } /* set the delay timer to enable timeout for data stage completion */ puhost->control.timer = usb_curframe_get(pudev); } } /*! \brief USB data IN transaction \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ static void usbh_data_in_transc(usb_core_driver *pudev, usbh_host *puhost) { usb_urb_state urb_status = URB_IDLE; usbh_data_recev(pudev, puhost->control.buf, puhost->control.pipe_in_num, puhost->control.ctl_len); urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_in_num, DATA_STAGE_TIMEOUT); if (URB_DONE == urb_status) { puhost->control.ctl_state = CTL_STATUS_OUT; puhost->control.timer = usb_curframe_get(pudev); } } /*! \brief USB data OUT transaction \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ static void usbh_data_out_transc(usb_core_driver *pudev, usbh_host *puhost) { usb_urb_state urb_status = URB_IDLE; pudev->host.pipe[puhost->control.pipe_out_num].data_toggle_out = 1U; usbh_data_send(pudev, puhost->control.buf, puhost->control.pipe_out_num, puhost->control.ctl_len); urb_status = usbh_urb_wait(pudev, puhost, puhost->control.pipe_out_num, DATA_STAGE_TIMEOUT); if (URB_DONE == urb_status) { puhost->control.ctl_state = CTL_STATUS_IN; puhost->control.timer = usb_curframe_get(pudev); } } /*! \brief USB status IN transaction \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ static void usbh_status_in_transc(usb_core_driver *pudev, usbh_host *puhost) { uint8_t pp_num = puhost->control.pipe_in_num; usb_urb_state urb_status = URB_IDLE; usbh_data_recev(pudev, NULL, pp_num, 0U); urb_status = usbh_urb_wait(pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT); if (URB_DONE == urb_status) { puhost->control.ctl_state = CTL_FINISH; } } /*! \brief USB status OUT transaction \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval none */ static void usbh_status_out_transc(usb_core_driver *pudev, usbh_host *puhost) { uint8_t pp_num = puhost->control.pipe_out_num; usb_urb_state urb_status = URB_IDLE; pudev->host.pipe[pp_num].data_toggle_out ^= 1U; usbh_data_send(pudev, NULL, pp_num, 0U); urb_status = usbh_urb_wait(pudev, puhost, pp_num, NODATA_STAGE_TIMEOUT); if (URB_DONE == urb_status) { puhost->control.ctl_state = CTL_FINISH; } } /*! \brief USB control transfer handler \param[in] pudev: pointer to USB core instance \param[in] puhost: pointer to USB host \param[out] none \retval operation status */ usbh_status usbh_ctl_handler(usb_core_driver *pudev, usbh_host *puhost) { usbh_status status = USBH_BUSY; switch (puhost->control.ctl_state) { case CTL_SETUP: usbh_setup_transc(pudev, puhost); break; case CTL_DATA_IN: usbh_data_in_transc(pudev, puhost); break; case CTL_DATA_OUT: usbh_data_out_transc(pudev, puhost); break; case CTL_STATUS_IN: usbh_status_in_transc(pudev, puhost); break; case CTL_STATUS_OUT: usbh_status_out_transc(pudev, puhost); break; case CTL_FINISH: puhost->control.ctl_state = CTL_IDLE; status = USBH_OK; break; case CTL_ERROR: if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { /* do the transmission again, starting from SETUP packet */ puhost->control.ctl_state = CTL_SETUP; } else { status = USBH_FAIL; } break; default: break; } return status; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_adc.c ================================================ /*! \file gd32vf103_adc.c \brief ADC driver \version 2020-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_adc.h" #include "gd32vf103_rcu.h" /* discontinuous mode macro*/ #define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) /* ADC regular channel macro */ #define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) #define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) #define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) #define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) /* ADC sampling time macro */ #define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) #define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) #define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) /* ADC inserted channel macro */ #define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) #define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) /* ADC inserted channel offset macro */ #define ADC_OFFSET_LENGTH ((uint8_t)3U) #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! \brief reset ADC \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_deinit(uint32_t adc_periph) { switch (adc_periph) { case ADC0: /* reset ADC0 */ rcu_periph_reset_enable(RCU_ADC0RST); rcu_periph_reset_disable(RCU_ADC0RST); break; case ADC1: /* reset ADC1 */ rcu_periph_reset_enable(RCU_ADC1RST); rcu_periph_reset_disable(RCU_ADC1RST); break; default: break; } } /*! \brief configure the ADC sync mode \param[in] mode: ADC mode only one parameter can be selected which is shown as below: \arg ADC_MODE_FREE: all the ADCs work independently \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only \param[out] none \retval none */ void adc_mode_config(uint32_t mode) { ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); ADC_CTL0(ADC0) |= mode; } /*! \brief enable or disable ADC special function \param[in] adc_periph: ADCx, x=0,1 \param[in] function: the function to config only one parameter can be selected which is shown as below: \arg ADC_SCAN_MODE: scan mode select \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically \arg ADC_CONTINUOUS_MODE: continuous mode select \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) { if (newvalue) { if (0U != (function & ADC_SCAN_MODE)) { /* enable scan mode */ ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; } if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { /* enable inserted channel group convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; } if (0U != (function & ADC_CONTINUOUS_MODE)) { /* enable continuous mode */ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; } } else { if (0U != (function & ADC_SCAN_MODE)) { /* disable scan mode */ ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; } if (0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { /* disable inserted channel group convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; } if (0U != (function & ADC_CONTINUOUS_MODE)) { /* disable continuous mode */ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; } } } /*! \brief configure ADC data alignment \param[in] adc_periph: ADCx, x=0,1 \param[in] data_alignment: data alignment select only one parameter can be selected which is shown as below: \arg ADC_DATAALIGN_RIGHT: LSB alignment \arg ADC_DATAALIGN_LEFT: MSB alignment \param[out] none \retval none */ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) { if (ADC_DATAALIGN_RIGHT != data_alignment) { /* MSB alignment */ ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; } else { /* LSB alignment */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); } } /*! \brief enable ADC interface \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_enable(uint32_t adc_periph) { if ((uint32_t)RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { /* enable ADC */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; } } /*! \brief disable ADC interface \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_disable(uint32_t adc_periph) { /* disable ADC */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); } /*! \brief ADC calibration and reset calibration \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_calibration_enable(uint32_t adc_periph) { /* reset the selected ADC1 calibration registers */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB; /* check the RSTCLB bit state */ while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { } /* enable ADC calibration process */ ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; /* check the CLB bit state */ while ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { } } /*! \brief enable the temperature sensor and Vrefint channel \param[in] none \param[out] none \retval none */ void adc_tempsensor_vrefint_enable(void) { /* enable the temperature sensor and Vrefint channel */ ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; } /*! \brief disable the temperature sensor and Vrefint channel \param[in] none \param[out] none \retval none */ void adc_tempsensor_vrefint_disable(void) { /* disable the temperature sensor and Vrefint channel */ ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; } /*! \brief enable DMA request \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_dma_mode_enable(uint32_t adc_periph) { /* enable DMA request */ ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); } /*! \brief disable DMA request \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_dma_mode_disable(uint32_t adc_periph) { /* disable DMA request */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); } /*! \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 for regular channel, the number has no effect for inserted channel \param[out] none \retval none */ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) { /* disable discontinuous mode of regular & inserted channel */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); switch (adc_channel_group) { case ADC_REGULAR_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); /* enable regular channel group discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; break; case ADC_INSERTED_CHANNEL: /* enable inserted channel group discontinuous mode */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; case ADC_CHANNEL_DISCON_DISABLE: /* disable discontinuous mode of regular & inserted channel */ default: break; } } /*! \brief configure the length of regular channel group or inserted channel group \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] length: the length of the channel regular channel 1-16 inserted channel 1-4 \param[out] none \retval none */ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) { switch (adc_channel_group) { case ADC_REGULAR_CHANNEL: /* configure the length of regular channel group */ ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); break; case ADC_INSERTED_CHANNEL: /* configure the length of inserted channel group */ ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); break; default: break; } } /*! \brief configure ADC regular channel \param[in] adc_periph: ADCx, x=0,1 \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx \param[in] sample_time: the sample time value only one parameter can be selected which is shown as below: \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles \param[out] none \retval none */ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint32_t rsq, sampt; /* ADC regular sequence config */ if (rank < ADC_REGULAR_CHANNEL_RANK_SIX) { /* the regular group sequence rank is smaller than six */ rsq = ADC_RSQ2(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)); ADC_RSQ2(adc_periph) = rsq; } else if (rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) { /* the regular group sequence rank is smaller than twelve */ rsq = ADC_RSQ1(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))); ADC_RSQ1(adc_periph) = rsq; } else if (rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) { /* the regular group sequence rank is smaller than sixteen */ rsq = ADC_RSQ0(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))); ADC_RSQ0(adc_periph) = rsq; } else { } /* ADC sampling time config */ if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) { /* the regular group sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); ADC_SAMPT1(adc_periph) = sampt; } else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { /* the regular group sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; } else { } } /*! \brief configure ADC inserted channel \param[in] adc_periph: ADCx, x=0,1 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx \param[in] sample_time: The sample time value only one parameter can be selected which is shown as below: \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles \param[out] none \retval none */ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint8_t inserted_length; uint32_t isq, sampt; /* get inserted channel group length */ inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ isq = ADC_ISQ(adc_periph); isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH))); isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); ADC_ISQ(adc_periph) = isq; /* ADC sampling time config */ if (adc_channel < ADC_CHANNEL_SAMPLE_TEN) { /* the inserted group sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); ADC_SAMPT1(adc_periph) = sampt; } else if (adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { /* the inserted group sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; } else { } } /*! \brief configure ADC inserted channel offset \param[in] adc_periph: ADCx, x=0,1 \param[in] inserted_channel: insert channel select only one parameter can be selected \arg ADC_INSERTED_CHANNEL_0: inserted channel0 \arg ADC_INSERTED_CHANNEL_1: inserted channel1 \arg ADC_INSERTED_CHANNEL_2: inserted channel2 \arg ADC_INSERTED_CHANNEL_3: inserted channel3 \param[in] offset: the offset data \param[out] none \retval none */ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) { uint8_t inserted_length; uint32_t num = 0U; inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); if (num <= ADC_OFFSET_LENGTH) { /* calculate the offset of the register */ num = num * ADC_OFFSET_SHIFT_LENGTH; /* config the offset of the selected channels */ REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); } } /*! \brief configure ADC external trigger source \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] external_trigger_source: regular or inserted group trigger source only one parameter can be selected for regular channel: \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger for inserted channel: \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger \param[out] none \retval none */ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) { switch (adc_channel_group) { case ADC_REGULAR_CHANNEL: /* configure ADC regular group external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; case ADC_INSERTED_CHANNEL: /* configure ADC inserted group external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; default: break; } } /*! \brief configure ADC external trigger \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: select the channel group one or more parameters can be selected which are shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) { if (newvalue) { if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* enable ADC regular channel group external trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; } if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* enable ADC inserted channel group external trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; } } else { if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* disable ADC regular channel group external trigger */ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; } if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* disable ADC regular channel group external trigger */ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; } } } /*! \brief enable ADC software trigger \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: select the channel group one or more parameters can be selected which are shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \param[out] none \retval none */ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) { if (0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* enable ADC regular channel group software trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; } if (0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* enable ADC inserted channel group software trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; } } /*! \brief read ADC regular group data register \param[in] adc_periph: ADCx, x=0,1 \param[in] none \param[out] none \retval the conversion value */ uint16_t adc_regular_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); } /*! \brief read ADC inserted group data register \param[in] adc_periph: ADCx, x=0,1 \param[in] inserted_channel: insert channel select only one parameter can be selected \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 \arg ADC_INSERTED_CHANNEL_1: inserted channel1 \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 \param[out] none \retval the conversion value */ uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) { uint32_t idata; /* read the data of the selected channel */ switch (inserted_channel) { case ADC_INSERTED_CHANNEL_0: /* read the data of channel 0 */ idata = ADC_IDATA0(adc_periph); break; case ADC_INSERTED_CHANNEL_1: /* read the data of channel 1 */ idata = ADC_IDATA1(adc_periph); break; case ADC_INSERTED_CHANNEL_2: /* read the data of channel 2 */ idata = ADC_IDATA2(adc_periph); break; case ADC_INSERTED_CHANNEL_3: /* read the data of channel 3 */ idata = ADC_IDATA3(adc_periph); break; default: idata = 0U; break; } return (uint16_t)idata; } /*! \brief read the last ADC0 and ADC1 conversion result data in sync mode \param[in] none \param[out] none \retval the conversion value */ uint32_t adc_sync_mode_convert_value_read(void) { /* return conversion value */ return ADC_RDATA(ADC0); } /*! \brief configure ADC analog watchdog single channel \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) \param[out] none \retval none */ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); /* analog watchdog channel select */ ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); } /*! \brief configure ADC analog watchdog group channel \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_channel_group: the channel group use analog watchdog only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group \param[out] none \retval none */ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); /* select the group */ switch (adc_channel_group) { case ADC_REGULAR_CHANNEL: /* regular channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: /* inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_IWDEN; break; case ADC_REGULAR_INSERTED_CHANNEL: /* regular and inserted channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: break; } } /*! \brief disable ADC analog watchdog \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_watchdog_disable(uint32_t adc_periph) { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); } /*! \brief configure ADC analog watchdog threshold \param[in] adc_periph: ADCx, x=0,1 \param[in] low_threshold: analog watchdog low threshold, 0..4095 \param[in] high_threshold: analog watchdog high threshold, 0..4095 \param[out] none \retval none */ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) { ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); } /*! \brief get the ADC flag bits \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_flag: the adc flag bits only one parameter can be selected which is shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag \arg ADC_FLAG_EOC: end of group conversion flag \arg ADC_FLAG_EOIC: end of inserted group conversion flag \arg ADC_FLAG_STIC: start flag of inserted channel group \arg ADC_FLAG_STRC: start flag of regular channel group \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) { FlagStatus reval = RESET; if (ADC_STAT(adc_periph) & adc_flag) { reval = SET; } return reval; } /*! \brief clear the ADC flag bits \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_flag: the adc flag bits one or more parameters can be selected which are shown as below: \arg ADC_FLAG_WDE: analog watchdog event flag \arg ADC_FLAG_EOC: end of group conversion flag \arg ADC_FLAG_EOIC: end of inserted group conversion flag \arg ADC_FLAG_STIC: start flag of inserted channel group \arg ADC_FLAG_STRC: start flag of regular channel group \param[out] none \retval none */ void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); } /*! \brief get the bit state of ADCx software start conversion \param[in] adc_periph: ADCx, x=0,1 \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; if ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)) { reval = SET; } return reval; } /*! \brief get the bit state of ADCx software inserted channel start conversion \param[in] adc_periph: ADCx, x=0,1 \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) { FlagStatus reval = RESET; if ((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)) { reval = SET; } return reval; } /*! \brief get the ADC interrupt bits \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_interrupt: the adc interrupt bits only one parameter can be selected which is shown as below: \arg ADC_INT_FLAG_WDE: analog watchdog interrupt \arg ADC_INT_FLAG_EOC: end of group conversion interrupt \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) { FlagStatus interrupt_flag = RESET; uint32_t state; /* check the interrupt bits */ switch (adc_interrupt) { case ADC_INT_FLAG_WDE: /* get the ADC analog watchdog interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_WDE; if ((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_EOC: /* get the ADC end of group conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOC; if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { interrupt_flag = SET; } break; case ADC_INT_FLAG_EOIC: /* get the ADC end of inserted group conversion interrupt bits */ state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; if ((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { interrupt_flag = SET; } break; default: break; } return interrupt_flag; } /*! \brief clear the ADC flag \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_interrupt: the adc status flag one or more parameters can be selected which are shown as below: \arg ADC_INT_FLAG_WDE: analog watchdog interrupt \arg ADC_INT_FLAG_EOC: end of group conversion interrupt \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt \param[out] none \retval none */ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) { ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); } /*! \brief enable ADC interrupt \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_interrupt: the adc interrupt one or more parameters can be selected which are shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag \arg ADC_INT_EOC: end of group conversion interrupt flag \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag \param[out] none \retval none */ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) { /* enable ADC analog watchdog interrupt */ if (0U != (adc_interrupt & ADC_INT_WDE)) { ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_WDEIE; } /* enable ADC end of group conversion interrupt */ if (0U != (adc_interrupt & ADC_INT_EOC)) { ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOCIE; } /* enable ADC end of inserted group conversion interrupt */ if (0U != (adc_interrupt & ADC_INT_EOIC)) { ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_EOICIE; } } /*! \brief disable ADC interrupt \param[in] adc_periph: ADCx, x=0,1 \param[in] adc_interrupt: the adc interrupt flag one or more parameters can be selected which are shown as below: \arg ADC_INT_WDE: analog watchdog interrupt flag \arg ADC_INT_EOC: end of group conversion interrupt flag \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag \param[out] none \retval none */ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) { /* disable ADC analog watchdog interrupt */ if (0U != (adc_interrupt & ADC_INT_WDE)) { ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_WDEIE; } /* disable ADC end of group conversion interrupt */ if (0U != (adc_interrupt & ADC_INT_EOC)) { ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOCIE; } /* disable ADC end of inserted group conversion interrupt */ if (0U != (adc_interrupt & ADC_INT_EOIC)) { ADC_CTL0(adc_periph) &= ~(uint32_t)ADC_CTL0_EOICIE; } } /*! \brief adc resolution config \param[in] adc_periph: ADCx, x=0,1 \param[in] resolution: ADC resolution only one parameter can be selected which is shown as below: \arg ADC_RESOLUTION_12B: 12-bit ADC resolution \arg ADC_RESOLUTION_10B: 10-bit ADC resolution \arg ADC_RESOLUTION_8B: 8-bit ADC resolution \arg ADC_RESOLUTION_6B: 6-bit ADC resolution \param[out] none \retval none */ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) { ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES); ADC_OVSCR(adc_periph) |= (uint32_t)resolution; } /*! \brief adc oversample mode config \param[in] adc_periph: ADCx, x=0,1 \param[in] mode: ADC oversampling mode only one parameter can be selected which is shown as below: \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger \param[in] shift: ADC oversampling shift only one parameter can be selected which is shown as below: \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift \param[in] ratio: ADC oversampling ratio only one parameter can be selected which is shown as below: \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2 \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4 \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8 \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16 \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32 \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64 \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128 \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256 \param[out] none \retval none */ void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) { if (mode) { ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS; } else { ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS); } /* config the shift and ratio */ ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS)); ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); } /*! \brief enable ADC oversample mode \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_oversample_mode_enable(uint32_t adc_periph) { ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN; } /*! \brief disable ADC oversample mode \param[in] adc_periph: ADCx, x=0,1 \param[out] none \retval none */ void adc_oversample_mode_disable(uint32_t adc_periph) { ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_bkp.c ================================================ /*! \file gd32vf103_bkp.c \brief BKP driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_bkp.h" #include "gd32vf103_rcu.h" /* BKP register bits offset */ #define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) /*! \brief reset BKP registers \param[in] none \param[out] none \retval none */ void bkp_deinit(void) { /* reset BKP domain register*/ } /*! \brief write BKP data register \param[in] register_number: refer to bkp_data_register_enum only one parameter can be selected which is shown as below: \arg BKP_DATA_x(x = 0..41): bkp data register number x \param[in] data: the data to be write in BKP data register \param[out] none \retval none */ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) { if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { BKP_DATA10_41((uint32_t)register_number - 1U) = data; } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { BKP_DATA0_9((uint32_t)register_number - 1U) = data; } else { /* illegal parameters */ } } /*! \brief read BKP data register \param[in] register_number: refer to bkp_data_register_enum only one parameter can be selected which is shown as below: \arg BKP_DATA_x(x = 0..41): bkp data register number x \param[out] none \retval data of BKP data register */ uint16_t bkp_data_read(bkp_data_register_enum register_number) { uint16_t data = 0U; /* get the data from the BKP data register */ if ((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { data = BKP_DATA10_41((uint32_t)register_number - 1U); } else if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { data = BKP_DATA0_9((uint32_t)register_number - 1U); } else { /* illegal parameters */ } return data; } /*! \brief enable RTC clock calibration output \param[in] none \param[out] none \retval none */ void bkp_rtc_calibration_output_enable(void) { BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; } /*! \brief disable RTC clock calibration output \param[in] none \param[out] none \retval none */ void bkp_rtc_calibration_output_disable(void) { BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; } /*! \brief enable RTC alarm or second signal output \param[in] none \param[out] none \retval none */ void bkp_rtc_signal_output_enable(void) { BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; } /*! \brief disable RTC alarm or second signal output \param[in] none \param[out] none \retval none */ void bkp_rtc_signal_output_disable(void) { BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; } /*! \brief select RTC output \param[in] outputsel: RTC output selection only one parameter can be selected which is shown as below: \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output \param[out] none \retval none */ void bkp_rtc_output_select(uint16_t outputsel) { uint16_t ctl = 0U; /* configure BKP_OCTL_ROSEL with outputsel */ ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_ROSEL; ctl |= outputsel; BKP_OCTL = ctl; } /*! \brief set RTC clock calibration value \param[in] value: RTC clock calibration value \arg 0x00 - 0x7F \param[out] none \retval none */ void bkp_rtc_calibration_value_set(uint8_t value) { uint16_t ctl; /* configure BKP_OCTL_RCCV with value */ ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_RCCV; ctl |= (uint16_t)OCTL_RCCV(value); BKP_OCTL = ctl; } /*! \brief enable tamper detection \param[in] none \param[out] none \retval none */ void bkp_tamper_detection_enable(void) { BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; } /*! \brief disable tamper detection \param[in] none \param[out] none \retval none */ void bkp_tamper_detection_disable(void) { BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; } /*! \brief set tamper pin active level \param[in] level: tamper active level only one parameter can be selected which is shown as below: \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low \param[out] none \retval none */ void bkp_tamper_active_level_set(uint16_t level) { uint16_t ctl = 0U; /* configure BKP_TPCTL_TPAL with level */ ctl = BKP_TPCTL; ctl &= (uint16_t)~BKP_TPCTL_TPAL; ctl |= level; BKP_TPCTL = ctl; } /*! \brief enable tamper interrupt \param[in] none \param[out] none \retval none */ void bkp_interrupt_enable(void) { BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; } /*! \brief disable tamper interrupt \param[in] none \param[out] none \retval none */ void bkp_interrupt_disable(void) { BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; } /*! \brief get tamper flag state \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus bkp_flag_get(void) { if (BKP_TPCS & BKP_FLAG_TAMPER) { return SET; } else { return RESET; } } /*! \brief clear tamper flag state \param[in] none \param[out] none \retval none */ void bkp_flag_clear(void) { BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); } /*! \brief get tamper interrupt flag state \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus bkp_interrupt_flag_get(void) { if (BKP_TPCS & BKP_INT_FLAG_TAMPER) { return SET; } else { return RESET; } } /*! \brief clear tamper interrupt flag state \param[in] none \param[out] none \retval none */ void bkp_interrupt_flag_clear(void) { BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_crc.c ================================================ /*! \file gd32vf103_crc.c \brief CRC driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_crc.h" #include "gd32vf103_rcu.h" #define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) #define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) /*! \brief deinit CRC calculation unit \param[in] none \param[out] none \retval none */ void crc_deinit(void) { CRC_DATA = CRC_DATA_RESET_VALUE; CRC_FDATA = CRC_FDATA_RESET_VALUE; CRC_CTL = (uint32_t)CRC_CTL_RST; } /*! \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF \param[in] none \param[out] none \retval none */ void crc_data_register_reset(void) { CRC_CTL |= (uint32_t)CRC_CTL_RST; } /*! \brief read the value of the data register \param[in] none \param[out] none \retval 32-bit value of the data register */ uint32_t crc_data_register_read(void) { uint32_t data; data = CRC_DATA; return (data); } /*! \brief read the value of the free data register \param[in] none \param[out] none \retval 8-bit value of the free data register */ uint8_t crc_free_data_register_read(void) { uint8_t fdata; fdata = (uint8_t)CRC_FDATA; return (fdata); } /*! \brief write data to the free data register \param[in] free_data: specified 8-bit data \param[out] none \retval none */ void crc_free_data_register_write(uint8_t free_data) { CRC_FDATA = (uint32_t)free_data; } /*! \brief calculate the CRC value of a 32-bit data \param[in] sdata: specified 32-bit data \param[out] none \retval 32-bit value calculated by CRC */ uint32_t crc_single_data_calculate(uint32_t sdata) { CRC_DATA = sdata; return (CRC_DATA); } /*! \brief calculate the CRC value of an array of 32-bit values \param[in] array: pointer to an array of 32-bit values \param[in] size: size of the array \param[out] none \retval 32-bit value calculated by CRC */ uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { uint32_t index; for (index = 0U; index < size; index++) { CRC_DATA = array[index]; } return (CRC_DATA); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dac.c ================================================ /*! \file gd32vf103_dac.c \brief DAC driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_dac.h" #include "gd32vf103_rcu.h" /* DAC register bit offset */ #define DAC1_REG_OFFSET ((uint32_t)16U) #define DH_12BIT_OFFSET ((uint32_t)16U) #define DH_8BIT_OFFSET ((uint32_t)8U) /*! \brief deinitialize DAC \param[in] none \param[out] none \retval none */ void dac_deinit(void) { rcu_periph_reset_enable(RCU_DACRST); rcu_periph_reset_disable(RCU_DACRST); } /*! \brief enable DAC \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_enable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DEN0; } else { DAC_CTL |= DAC_CTL_DEN1; } } /*! \brief disable DAC \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_disable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DEN0; } else { DAC_CTL &= ~DAC_CTL_DEN1; } } /*! \brief enable DAC DMA function \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_dma_enable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DDMAEN0; } else { DAC_CTL |= DAC_CTL_DDMAEN1; } } /*! \brief disable DAC DMA function \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_dma_disable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DDMAEN0; } else { DAC_CTL &= ~DAC_CTL_DDMAEN1; } } /*! \brief enable DAC output buffer \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_output_buffer_enable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DBOFF0; } else { DAC_CTL &= ~DAC_CTL_DBOFF1; } } /*! \brief disable DAC output buffer \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_output_buffer_disable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DBOFF0; } else { DAC_CTL |= DAC_CTL_DBOFF1; } } /*! \brief get DAC output value \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval DAC output data */ uint16_t dac_output_value_get(uint32_t dac_periph) { uint16_t data = 0U; if (DAC0 == dac_periph) { /* store the DAC0 output value */ data = (uint16_t)DAC0_DO; } else { /* store the DAC1 output value */ data = (uint16_t)DAC1_DO; } return data; } /*! \brief set the DAC specified data holding register value \param[in] dac_periph: DACx(x = 0,1) \param[in] dac_align: data alignment only one parameter can be selected which is shown as below: \arg DAC_ALIGN_8B_R: data right 8 bit alignment \arg DAC_ALIGN_12B_R: data right 12 bit alignment \arg DAC_ALIGN_12B_L: data left 12 bit alignment \param[in] data: data to be loaded \param[out] none \retval none */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) { if (DAC0 == dac_periph) { switch (dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC0_R12DH = data; break; /* data left 12 bit alignment */ case DAC_ALIGN_12B_L: DAC0_L12DH = data; break; /* data right 8 bit alignment */ case DAC_ALIGN_8B_R: DAC0_R8DH = data; break; default: break; } } else { switch (dac_align) { /* data right 12 bit alignment */ case DAC_ALIGN_12B_R: DAC1_R12DH = data; break; /* data left 12 bit alignment */ case DAC_ALIGN_12B_L: DAC1_L12DH = data; break; /* data right 8 bit alignment */ case DAC_ALIGN_8B_R: DAC1_R8DH = data; break; default: break; } } } /*! \brief enable DAC trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_trigger_enable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DTEN0; } else { DAC_CTL |= DAC_CTL_DTEN1; } } /*! \brief disable DAC trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_trigger_disable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DTEN0; } else { DAC_CTL &= ~DAC_CTL_DTEN1; } } /*! \brief set DAC trigger source \param[in] dac_periph: DACx(x = 0,1) \param[in] triggersource: external triggers of DAC only one parameter can be selected which is shown as below: \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event \arg DAC_TRIGGER_SOFTWARE: software trigger \param[out] none \retval none */ void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) { if (DAC0 == dac_periph) { /* configure DAC0 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL |= triggersource; } else { /* configure DAC1 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL1; DAC_CTL |= (triggersource << DAC1_REG_OFFSET); } } /*! \brief enable DAC software trigger \param[in] dac_periph: DACx(x = 0,1) \retval none */ void dac_software_trigger_enable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_SWT |= DAC_SWT_SWTR0; } else { DAC_SWT |= DAC_SWT_SWTR1; } } /*! \brief disable DAC software trigger \param[in] dac_periph: DACx(x = 0,1) \param[out] none \retval none */ void dac_software_trigger_disable(uint32_t dac_periph) { if (DAC0 == dac_periph) { DAC_SWT &= ~DAC_SWT_SWTR0; } else { DAC_SWT &= ~DAC_SWT_SWTR1; } } /*! \brief configure DAC wave mode \param[in] dac_periph: DACx(x = 0,1) \param[in] wave_mode: noise wave mode only one parameter can be selected which is shown as below: \arg DAC_WAVE_DISABLE: wave disable \arg DAC_WAVE_MODE_LFSR: LFSR noise mode \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode \param[out] none \retval none */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { if (DAC0 == dac_periph) { /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; } else { /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); } } /*! \brief configure DAC wave bit width \param[in] dac_periph: DACx(x = 0,1) \param[in] bit_width: noise wave bit width only one parameter can be selected which is shown as below: \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 \param[out] none \retval none */ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { if (DAC0 == dac_periph) { /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; } else { /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (bit_width << DAC1_REG_OFFSET); } } /*! \brief configure DAC LFSR noise mode \param[in] dac_periph: DACx(x = 0,1) \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode only one parameter can be selected which is shown as below: \arg DAC_LFSR_BIT0: unmask the LFSR bit0 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] \param[out] none \retval none */ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { if (DAC0 == dac_periph) { /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; } else { /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); } } /*! \brief configure DAC triangle noise mode \param[in] dac_periph: DACx(x = 0,1) \param[in] amplitude: triangle amplitude in DAC triangle noise mode only one parameter can be selected which is shown as below: \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 \param[out] none \retval none */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { if (DAC0 == dac_periph) { /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; } else { /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (amplitude << DAC1_REG_OFFSET); } } /*! \brief enable DAC concurrent mode \param[in] none \param[out] none \retval none */ void dac_concurrent_enable(void) { uint32_t ctl = 0U; ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; DAC_CTL |= (ctl); } /*! \brief disable DAC concurrent mode \param[in] none \param[out] none \retval none */ void dac_concurrent_disable(void) { uint32_t ctl = 0U; ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; DAC_CTL &= (~ctl); } /*! \brief enable DAC concurrent software trigger function \param[in] none \param[out] none \retval none */ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; DAC_SWT |= (swt); } /*! \brief disable DAC concurrent software trigger function \param[in] none \param[out] none \retval none */ void dac_concurrent_software_trigger_disable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; DAC_SWT &= (~swt); } /*! \brief enable DAC concurrent buffer function \param[in] none \param[out] none \retval none */ void dac_concurrent_output_buffer_enable(void) { uint32_t ctl = 0U; ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; DAC_CTL &= (~ctl); } /*! \brief disable DAC concurrent buffer function \param[in] none \param[out] none \retval none */ void dac_concurrent_output_buffer_disable(void) { uint32_t ctl = 0U; ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; DAC_CTL |= (ctl); } /*! \brief set DAC concurrent mode data holding register value \param[in] dac_align: data alignment only one parameter can be selected which is shown as below: \arg DAC_ALIGN_8B_R: data right 8b alignment \arg DAC_ALIGN_12B_R: data right 12b alignment \arg DAC_ALIGN_12B_L: data left 12b alignment \param[in] data0: data to be loaded \param[in] data1: data to be loaded \param[out] none \retval none */ void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) { uint32_t data = 0U; switch (dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; DACC_R12DH = data; break; /* data left 12b alignment */ case DAC_ALIGN_12B_L: data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; DACC_L12DH = data; break; /* data right 8b alignment */ case DAC_ALIGN_8B_R: data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; DACC_R8DH = data; break; default: break; } } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dbg.c ================================================ /*! \file gd32vf103_dbg.c \brief DBG driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_dbg.h" #include "gd32vf103_rcu.h" /*! \brief read DBG_ID code register \param[in] none \param[out] none \retval DBG_ID code */ uint32_t dbg_id_get(void) { return DBG_ID; } /*! \brief enable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: one or more parameters can be selected which are shown as below: \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode \param[out] none \retval none */ void dbg_low_power_enable(uint32_t dbg_low_power) { DBG_CTL |= dbg_low_power; } /*! \brief disable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: one or more parameters can be selected which are shown as below: \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode \param[out] none \retval none */ void dbg_low_power_disable(uint32_t dbg_low_power) { DBG_CTL &= ~dbg_low_power; } /*! \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: refer to dbg_periph_enum one or more parameters can be selected which are shown as below: \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted \param[out] none \retval none */ void dbg_periph_enable(dbg_periph_enum dbg_periph) { DBG_CTL |= (uint32_t)dbg_periph; } /*! \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: refer to dbg_periph_enum one or more parameters can be selected which are shown as below: \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted \arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted \param[out] none \retval none */ void dbg_periph_disable(dbg_periph_enum dbg_periph) { DBG_CTL &= ~(uint32_t)dbg_periph; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_dma.c ================================================ /*! \file gd32vf103_dma.c \brief DMA driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-10-30, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_dma.h" #include "gd32vf103_rcu.h" #define DMA_WRONG_HANDLE \ while (1) { \ } /* check whether peripheral matches channels or not */ static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); /*! \brief deinitialize DMA a channel registers \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is deinitialized only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } /* disable DMA a channel */ DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; /* reset DMA channel registers */ DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, (uint32_t)channelx); } /*! \brief initialize the parameters of DMA struct with the default values \param[in] init_struct: the initialization data needed to initialize DMA channel \param[out] none \retval none */ void dma_struct_para_init(dma_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; init_struct->periph_width = 0U; init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; init_struct->memory_addr = 0U; init_struct->memory_width = 0U; init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; init_struct->number = 0U; init_struct->direction = DMA_PERIPHERAL_TO_MEMORY; init_struct->priority = DMA_PRIORITY_LOW; } /*! \brief initialize DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is initialized only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] init_struct: the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL number: the number of remaining data to be transferred by the DMA priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none */ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) { uint32_t ctl; if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } /* configure peripheral base address */ DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; /* configure memory base address */ DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; /* configure the number of remaining data to be transferred */ DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); /* configure peripheral transfer width,memory transfer width and priority */ ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ if (DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; } else { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; } /* configure memory increasing mode */ if (DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; } else { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /* configure the direction of data transfer */ if (DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; } else { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; } } /*! \brief enable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; } /*! \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; } /*! \brief enable memory to memory mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; } /*! \brief disable memory to memory mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; } /*! \brief enable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; } /*! \brief disable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; } /*! \brief set DMA peripheral base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set peripheral base address only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] address: peripheral base address \param[out] none \retval none */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHPADDR(dma_periph, channelx) = address; } /*! \brief set DMA memory base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set memory base address only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] address: memory base address \param[out] none \retval none */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHMADDR(dma_periph, channelx) = address; } /*! \brief set the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set number only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] number: the number of remaining data to be transferred by the DMA \param[out] none \retval none */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); } /*! \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to set number only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval uint32_t: the number of remaining data to be transferred by the DMA */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } return (uint32_t)DMA_CHCNT(dma_periph, channelx); } /*! \brief configure priority level of DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] priority: priority Level of this channel only one parameter can be selected which is shown as below: \arg DMA_PRIORITY_LOW: low priority \arg DMA_PRIORITY_MEDIUM: medium priority \arg DMA_PRIORITY_HIGH: high priority \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority \param[out] none \retval none */ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) { uint32_t ctl; if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PRIO; ctl |= priority; DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief configure transfer data size of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] mwidth: transfer data width of memory only one parameter can be selected which is shown as below: \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit \param[out] none \retval none */ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) { uint32_t ctl; if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_MWIDTH; ctl |= mwidth; DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief configure transfer data size of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] pwidth: transfer data width of peripheral only one parameter can be selected which is shown as below: \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit \param[out] none \retval none */ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) { uint32_t ctl; if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); /* assign regiser */ ctl &= ~DMA_CHXCTL_PWIDTH; ctl |= pwidth; DMA_CHCTL(dma_periph, channelx) = ctl; } /*! \brief enable next address increasement algorithm of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; } /*! \brief disable next address increasement algorithm of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } /*! \brief enable next address increasement algorithm of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; } /*! \brief disable next address increasement algorithm of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[out] none \retval none */ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; } /*! \brief configure the direction of data transfer on the channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] direction: specify the direction of data transfer only one parameter can be selected which is shown as below: \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral \param[out] none \retval none */ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } if (DMA_PERIPHERAL_TO_MEMORY == direction) { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; } else { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; } } /*! \brief check DMA flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] flag: specify get which flag only one parameter can be selected which is shown as below: \arg DMA_FLAG_G: global interrupt flag of channel \arg DMA_FLAG_FTF: full transfer finish flag of channel \arg DMA_FLAG_HTF: half transfer finish flag of channel \arg DMA_FLAG_ERR: error flag of channel \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { FlagStatus reval; if (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, (uint32_t)channelx)) { reval = SET; } else { reval = RESET; } return reval; } /*! \brief clear DMA a channel flag \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to clear flag only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] flag: specify get which flag only one parameter can be selected which is shown as below: \arg DMA_FLAG_G: global interrupt flag of channel \arg DMA_FLAG_FTF: full transfer finish flag of channel \arg DMA_FLAG_HTF: half transfer finish flag of channel \arg DMA_FLAG_ERR: error flag of channel \param[out] none \retval none */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, (uint32_t)channelx); } /*! \brief check DMA flag and interrupt enable bit is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] flag: specify get which flag only one parameter can be selected which is shown as below: \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel \arg DMA_INT_FLAG_ERR: error interrupt flag of channel \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { uint32_t interrupt_enable = 0U, interrupt_flag = 0U; switch (flag) { case DMA_INT_FLAG_FTF: /* check whether the full transfer finish interrupt flag is set and enabled */ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, (uint32_t)channelx); interrupt_enable = DMA_CHCTL(dma_periph, (uint32_t)channelx) & DMA_CHXCTL_FTFIE; break; case DMA_INT_FLAG_HTF: /* check whether the half transfer finish interrupt flag is set and enabled */ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, (uint32_t)channelx); interrupt_enable = DMA_CHCTL(dma_periph, (uint32_t)channelx) & DMA_CHXCTL_HTFIE; break; case DMA_INT_FLAG_ERR: /* check whether the error interrupt flag is set and enabled */ interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, (uint32_t)channelx); interrupt_enable = DMA_CHCTL(dma_periph, (uint32_t)channelx) & DMA_CHXCTL_ERRIE; break; default: DMA_WRONG_HANDLE } /* when the interrupt flag is set and enabled, return SET */ if (interrupt_flag && interrupt_enable) { return SET; } else { return RESET; } } /*! \brief clear DMA a channel flag \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to clear flag only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] flag: specify get which flag only one parameter can be selected which is shown as below: \arg DMA_INT_FLAG_G: global interrupt flag of channel \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel \arg DMA_INT_FLAG_ERR: error interrupt flag of channel \param[out] none \retval none */ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, (uint32_t)channelx); } /*! \brief enable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] source: specify which interrupt to enbale one or more parameters can be selected which are shown as below \arg DMA_INT_FTF: channel full transfer finish interrupt \arg DMA_INT_HTF: channel half transfer finish interrupt \arg DMA_INT_ERR: channel error interrupt \param[out] none \retval none */ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) |= source; } /*! \brief disable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) \param[in] source: specify which interrupt to disbale one or more parameters can be selected which are shown as below \arg DMA_INT_FTF: channel full transfer finish interrupt \arg DMA_INT_HTF: channel half transfer finish interrupt \arg DMA_INT_ERR: channel error interrupt \param[out] none \retval none */ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) { if (ERROR == dma_periph_and_channel_check(dma_periph, channelx)) { DMA_WRONG_HANDLE } DMA_CHCTL(dma_periph, channelx) &= ~source; } /*! \brief check whether peripheral and channels match \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA_CHx(x=0..6) \param[out] none \retval none */ static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) { ErrStatus val = SUCCESS; if (DMA1 == dma_periph) { /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ if (channelx > DMA_CH4) { val = ERROR; } } return val; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_eclic.c ================================================ /*! \file gd32vf103_eclic.c \brief ECLIC(Enhancement Core-Local Interrupt Controller) driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_eclic.h" #include "gd32vf103_rcu.h" #include "n200_func.h" #include "riscv_encoding.h" #define REG_DBGMCU2 ((uint32_t)0xE0042008U) #define REG_DBGMCU2EN ((uint32_t)0xE004200CU) /*! \brief enable the global interrupt \param[in] none \param[out] none \retval none */ void eclic_global_interrupt_enable(void) { /* set machine interrupt enable bit */ set_csr(mstatus, MSTATUS_MIE); } /*! \brief disable the global interrupt \param[in] none \param[out] none \retval none */ void eclic_global_interrupt_disable(void) { /* clear machine interrupt enable bit */ clear_csr(mstatus, MSTATUS_MIE); } /*! \brief set the priority group \param[in] prigroup: specify the priority group \arg ECLIC_PRIGROUP_LEVEL0_PRIO4 \arg ECLIC_PRIGROUP_LEVEL1_PRIO3 \arg ECLIC_PRIGROUP_LEVEL2_PRIO2 \arg ECLIC_PRIGROUP_LEVEL3_PRIO1 \arg ECLIC_PRIGROUP_LEVEL4_PRIO0 \param[out] none \retval none */ void eclic_priority_group_set(uint8_t prigroup) { eclic_set_nlbits(prigroup); } /*! \brief enable the interrupt request \param[in] source: interrupt request, detailed in IRQn_Type \param[in] level: the level needed to set (maximum is 15, refer to the priority group) \param[in] priority: the priority needed to set (maximum is 15, refer to the priority group) \param[out] none \retval none */ void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) { eclic_enable_interrupt(source); eclic_set_irq_lvl_abs(source, level); eclic_set_irq_priority(source, priority); } /*! \brief disable the interrupt request \param[in] source: interrupt request, detailed in IRQn_Type \param[out] none \retval none */ void eclic_irq_disable(uint32_t source) { eclic_disable_interrupt(source); } /*! \brief reset system \param[in] none \param[out] none \retval none */ void eclic_system_reset(void) { REG32(REG_DBGMCU2EN) = (uint32_t)0x4b5a6978U; REG32(REG_DBGMCU2) = (uint32_t)0x1U; } /*! \brief send event(SEV) \param[in] none \param[out] none \retval none */ void eclic_send_event(void) { set_csr(0x812U, 0x1U); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exmc.c ================================================ /*! \file gd32vf103_exmc.c \brief EXMC driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_exmc.h" #include "gd32vf103_rcu.h" /* EXMC bank0 register reset value */ #define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU) #define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) /* EXMC register bit offset */ #define SNCTL_NRMUX_OFFSET ((uint32_t)1U) #define SNCTL_WREN_OFFSET ((uint32_t)12U) #define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) #define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) #define SNTCFG_AHLD_OFFSET ((uint32_t)4U) #define SNTCFG_DSET_OFFSET ((uint32_t)8U) #define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) /*! \brief deinitialize EXMC NOR/SRAM region \param[in] norsram_region: select the region of bank0 \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) \param[out] none \retval none */ void exmc_norsram_deinit(uint32_t norsram_region) { /* reset the registers */ if (EXMC_BANK0_NORSRAM_REGION0 == norsram_region) { EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; } EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; } /*! \brief initialize the structure exmc_norsram_parameter_struct \param[in] none \param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer \retval none */ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { /* configure the structure with default value */ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; exmc_norsram_init_struct->address_data_mux = ENABLE; exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B; exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; exmc_norsram_init_struct->memory_write = ENABLE; exmc_norsram_init_struct->nwait_signal = ENABLE; exmc_norsram_init_struct->asyn_wait = DISABLE; /* read/write timing configure */ exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; } /*! \brief initialize EXMC NOR/SRAM region \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0 asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR address_data_mux: ENABLE read_write_timing: structure exmc_norsram_timing_parameter_struct set the time \param[out] none \retval none */ void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U; /* get the register value */ snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX)); snctl |= (uint32_t)((uint32_t)exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | exmc_norsram_init_struct->memory_type | exmc_norsram_init_struct->databus_width | exmc_norsram_init_struct->nwait_polarity | ((uint32_t)exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | ((uint32_t)exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | ((uint32_t)exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET); sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) | (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) | (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) | (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT); /* nor flash access enable */ if (EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { snctl |= (uint32_t)EXMC_SNCTL_NREN; } /* configure the registers */ EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; } /*! \brief enable EXMC NOR/PSRAM bank region \param[in] norsram_region: specify the region of NOR/PSRAM bank \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) \param[out] none \retval none */ void exmc_norsram_enable(uint32_t norsram_region) { EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; } /*! \brief disable EXMC NOR/PSRAM bank region \param[in] norsram_region: specify the region of NOR/PSRAM bank \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) \param[out] none \retval none */ void exmc_norsram_disable(uint32_t norsram_region) { EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_exti.c ================================================ /*! \file gd32vf103_exti.c \brief EXTI driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_exti.h" #include "gd32vf103_rcu.h" #define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) /*! \brief deinitialize the EXTI \param[in] none \param[out] none \retval none */ void exti_deinit(void) { /* reset the value of all the EXTI registers */ EXTI_INTEN = EXTI_REG_RESET_VALUE; EXTI_EVEN = EXTI_REG_RESET_VALUE; EXTI_RTEN = EXTI_REG_RESET_VALUE; EXTI_FTEN = EXTI_REG_RESET_VALUE; EXTI_SWIEV = EXTI_REG_RESET_VALUE; } /*! \brief initialize the EXTI \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[in] mode: interrupt or event mode, refer to exti_mode_enum only one parameter can be selected which is shown as below: \arg EXTI_INTERRUPT: interrupt mode \arg EXTI_EVENT: event mode \param[in] trig_type: trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below: \arg EXTI_TRIG_RISING: rising edge trigger \arg EXTI_TRIG_FALLING: falling edge trigger \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger \param[out] none \retval none */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) { /* reset the EXTI line x */ EXTI_INTEN &= ~(uint32_t)linex; EXTI_EVEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; /* set the EXTI mode and enable the interrupts or events from EXTI line x */ switch (mode) { case EXTI_INTERRUPT: EXTI_INTEN |= (uint32_t)linex; break; case EXTI_EVENT: EXTI_EVEN |= (uint32_t)linex; break; default: break; } /* set the EXTI trigger type */ switch (trig_type) { case EXTI_TRIG_RISING: EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; break; case EXTI_TRIG_FALLING: EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN |= (uint32_t)linex; break; case EXTI_TRIG_BOTH: EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex; break; case EXTI_TRIG_NONE: default: break; } } /*! \brief enable the interrupts from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_interrupt_enable(exti_line_enum linex) { EXTI_INTEN |= (uint32_t)linex; } /*! \brief enable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_event_enable(exti_line_enum linex) { EXTI_EVEN |= (uint32_t)linex; } /*! \brief disable the interrupt from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_interrupt_disable(exti_line_enum linex) { EXTI_INTEN &= ~(uint32_t)linex; } /*! \brief disable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_event_disable(exti_line_enum linex) { EXTI_EVEN &= ~(uint32_t)linex; } /*! \brief get EXTI lines flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval FlagStatus: status of flag (RESET or SET) */ FlagStatus exti_flag_get(exti_line_enum linex) { if (RESET != (EXTI_PD & (uint32_t)linex)) { return SET; } else { return RESET; } } /*! \brief clear EXTI lines pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } /*! \brief get EXTI lines flag when the interrupt flag is set \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval FlagStatus: status of flag (RESET or SET) */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { uint32_t flag_left, flag_right; flag_left = EXTI_PD & (uint32_t)linex; flag_right = EXTI_INTEN & (uint32_t)linex; if ((RESET != flag_left) && (RESET != flag_right)) { return SET; } else { return RESET; } } /*! \brief clear EXTI lines pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_interrupt_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } /*! \brief enable EXTI software interrupt event \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_software_interrupt_enable(exti_line_enum linex) { EXTI_SWIEV |= (uint32_t)linex; } /*! \brief disable EXTI software interrupt event \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..18): EXTI line x \param[out] none \retval none */ void exti_software_interrupt_disable(exti_line_enum linex) { EXTI_SWIEV &= ~(uint32_t)linex; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fmc.c ================================================ /*! \file gd32vf103_fmc.c \brief FMC driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-09-18, V1.0.1, firmware for GD32VF103 \version 2020-02-20, V1.0.2, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_fmc.h" #include "gd32vf103_rcu.h" /*! \brief set the FMC wait state counter \param[in] wscnt��wait state counter value \arg WS_WSCNT_0: FMC 0 wait state \arg WS_WSCNT_1: FMC 1 wait state \arg WS_WSCNT_2: FMC 2 wait state \param[out] none \retval none */ void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WS_WSCNT; FMC_WS = (reg | wscnt); } /*! \brief unlock the main FMC operation \param[in] none \param[out] none \retval none */ void fmc_unlock(void) { if ((RESET != (FMC_CTL & FMC_CTL_LK))) { /* write the FMC unlock key */ FMC_KEY = UNLOCK_KEY0; FMC_KEY = UNLOCK_KEY1; } } /*! \brief lock the main FMC operation \param[in] none \param[out] none \retval none */ void fmc_lock(void) { /* set the LK bit */ FMC_CTL |= FMC_CTL_LK; } /*! \brief FMC erase page \param[in] page_address: the page address to be erased. \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_page_erase(uint32_t page_address) { fmc_state_enum fmc_state; fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* if the last operation is completed, start page erase */ if (FMC_READY == fmc_state) { FMC_CTL |= FMC_CTL_PER; FMC_ADDR = page_address; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PER bit */ FMC_CTL &= ~FMC_CTL_PER; } /* return the FMC state */ return fmc_state; } /*! \brief FMC erase whole chip \param[in] none \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state; fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL |= FMC_CTL_MER; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER bit */ FMC_CTL &= ~FMC_CTL_MER; } /* return the FMC state */ return fmc_state; } /*! \brief FMC program a word at the corresponding address \param[in] address: address to program \param[in] data: word to program \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) { fmc_state_enum fmc_state = FMC_READY; fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL |= FMC_CTL_PG; REG32(address) = data; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL &= ~FMC_CTL_PG; } /* return the FMC state */ return fmc_state; } /* \brief FMC program a half word at the corresponding address \param[in] address: address to program \param[in] data: halfword to program \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) { fmc_state_enum fmc_state = FMC_READY; fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL |= FMC_CTL_PG; REG16(address) = data; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL &= ~FMC_CTL_PG; } /* return the FMC state */ return fmc_state; } /*! \brief unlock the option byte operation \param[in] none \param[out] none \retval none */ void ob_unlock(void) { if (RESET == (FMC_CTL & FMC_CTL_OBWEN)) { /* write the FMC key */ FMC_OBKEY = UNLOCK_KEY0; FMC_OBKEY = UNLOCK_KEY1; } /* wait until OBWEN bit is set by hardware */ while (RESET == (FMC_CTL & FMC_CTL_OBWEN)) { } } /*! \brief lock the option byte operation \param[in] none \param[out] none \retval none */ void ob_lock(void) { /* reset the OBWEN bit */ FMC_CTL &= ~FMC_CTL_OBWEN; } /*! \brief erase the FMC option byte unlock the FMC_CTL and option byte before calling this function \param[in] none \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum ob_erase(void) { uint16_t temp_spc = FMC_NSPC; fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); /* check the option byte security protection value */ if (RESET != ob_spc_get()) { temp_spc = FMC_USPC; } if (FMC_READY == fmc_state) { /* start erase the option byte */ FMC_CTL |= FMC_CTL_OBER; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* reset the OBER bit */ FMC_CTL &= ~FMC_CTL_OBER; /* set the OBPG bit */ FMC_CTL |= FMC_CTL_OBPG; /* no security protection */ OB_SPC = (uint16_t)temp_spc; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } else { if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } } /* return the FMC state */ return fmc_state; } /*! \brief enable write protection \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if you want to protect the corresponding pages. meanwhile, sector macro could used to set specific sector write protected. one or more parameters can be selected which are shown as below: \arg OB_WP_x(x = 0..31): write protect specify sector \arg OB_WP_ALL: write protect all sector \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) { uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); ob_wp = (uint32_t)(~ob_wp); temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); if (FMC_READY == fmc_state) { /* set the OBPG bit*/ FMC_CTL |= FMC_CTL_OBPG; if (0xFFU != temp_wp0) { OB_WP0 = temp_wp0; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); } if ((FMC_READY == fmc_state) && (0xFFU != temp_wp1)) { OB_WP1 = temp_wp1; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); } if ((FMC_READY == fmc_state) && (0xFFU != temp_wp2)) { OB_WP2 = temp_wp2; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); } if ((FMC_READY == fmc_state) && (0xFFU != temp_wp3)) { OB_WP3 = temp_wp3; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); } if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } /* return the FMC state */ return fmc_state; } /*! \brief configure security protection \param[in] ob_spc: specify security protection only one parameter can be selected which is shown as below: \arg FMC_NSPC: no security protection \arg FMC_USPC: under security protection \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) { fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { FMC_CTL |= FMC_CTL_OBER; FMC_CTL |= FMC_CTL_START; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* reset the OBER bit */ FMC_CTL &= ~FMC_CTL_OBER; /* start the option byte program */ FMC_CTL |= FMC_CTL_OBPG; OB_SPC = (uint16_t)ob_spc; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } else { if (FMC_TOERR != fmc_state) { /* reset the OBER bit */ FMC_CTL &= ~FMC_CTL_OBER; } } } /* return the FMC state */ return fmc_state; } /*! \brief program the FMC user option byte \param[in] ob_fwdgt: option byte watchdog value \arg OB_FWDGT_SW: software free watchdog \arg OB_FWDGT_HW: hardware free watchdog \param[in] ob_deepsleep: option byte deepsleep reset value \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode \param[in] ob_stdby:option byte standby reset value \arg OB_STDBY_NRST: no reset when entering standby mode \arg OB_STDBY_RST: generate a reset instead of entering standby mode \param[in] ob_boot: specifies the option byte boot bank value \arg OB_BOOT_B0: boot from bank0 \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) { fmc_state_enum fmc_state = FMC_READY; uint8_t temp; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* set the OBPG bit*/ FMC_CTL |= FMC_CTL_OBPG; temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); OB_USER = (uint16_t)temp; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } /* return the FMC state */ return fmc_state; } /*! \brief program the FMC data option byte \param[in] address: the option bytes address to be programmed \param[in] data: the byte to be programmed \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) { fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_READY == fmc_state) { /* set the OBPG bit */ FMC_CTL |= FMC_CTL_OBPG; REG16(address) = data; /* wait for the FMC ready */ fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); if (FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL &= ~FMC_CTL_OBPG; } } /* return the FMC state */ return fmc_state; } /*! \brief get OB_USER in register FMC_OBSTAT \param[in] none \param[out] none \retval the FMC user option byte values */ uint8_t ob_user_get(void) { /* return the FMC user option byte value */ return (uint8_t)(FMC_OBSTAT >> 2U); } /*! \brief get OB_DATA in register FMC_OBSTAT \param[in] none \param[out] none \retval ob_data */ uint16_t ob_data_get(void) { return (uint16_t)(FMC_OBSTAT >> 10U); } /*! \brief get the FMC option byte write protection \param[in] none \param[out] none \retval the FMC write protection option byte value */ uint32_t ob_write_protection_get(void) { /* return the FMC write protection option byte value */ return FMC_WP; } /*! \brief get FMC option byte security protection state \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; if (RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) { spc_state = SET; } else { spc_state = RESET; } return spc_state; } /*! \brief enable FMC interrupt \param[in] interrupt: the FMC interrupt source only one parameter can be selected which is shown as below: \arg FMC_INT_END: enable FMC end of program interrupt \arg FMC_INT_ERR: enable FMC error interrupt \param[out] none \retval none */ void fmc_interrupt_enable(fmc_int_enum interrupt) { FMC_CTL |= (uint32_t)interrupt; } /*! \brief disable FMC interrupt \param[in] interrupt: the FMC interrupt source only one parameter can be selected which is shown as below: \arg FMC_INT_END: enable FMC end of program interrupt \arg FMC_INT_ERR: enable FMC error interrupt \param[out] none \retval none */ void fmc_interrupt_disable(fmc_int_enum interrupt) { FMC_CTL &= ~(uint32_t)interrupt; } /*! \brief check flag is set or not \param[in] flag: check FMC flag only one parameter can be selected which is shown as below: \arg FMC_FLAG_BUSY: FMC busy flag \arg FMC_FLAG_PGERR: FMC operation error flag \arg FMC_FLAG_WPERR: FMC erase/program protection error flag \arg FMC_FLAG_END: FMC end of operation flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus fmc_flag_get(fmc_flag_enum flag) { FlagStatus status = RESET; if (FMC_STAT & flag) { status = SET; } /* return the state of corresponding FMC flag */ return status; } /*! \brief clear the FMC flag \param[in] flag: clear FMC flag only one parameter can be selected which is shown as below: \arg FMC_FLAG_PGERR: FMC operation error flag \arg FMC_FLAG_WPERR: FMC erase/program protection error flag \arg FMC_FLAG_END: FMC end of operation flag \param[out] none \retval none */ void fmc_flag_clear(fmc_flag_enum flag) { /* clear the flags */ FMC_STAT = flag; } /*! \brief get FMC interrupt flag state \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) { FlagStatus status = RESET; if (FMC_STAT & flag) { status = SET; } /* return the state of corresponding FMC flag */ return status; } /*! \brief clear FMC interrupt flag state \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag \param[out] none \retval none */ void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) { /* clear the flags */ FMC_STAT = flag; } /*! \brief get the FMC state \param[in] none \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_state_get(void) { fmc_state_enum fmc_state = FMC_READY; if ((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { fmc_state = FMC_BUSY; } else { if ((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { fmc_state = FMC_WPERR; } else { if ((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGERR))) { fmc_state = FMC_PGERR; } } } /* return the FMC state */ return fmc_state; } /*! \brief check whether FMC is ready or not \param[in] timeout: count of loop \param[out] none \retval state of FMC, refer to fmc_state_enum */ fmc_state_enum fmc_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; /* wait for FMC ready */ do { /* get FMC state */ fmc_state = fmc_state_get(); timeout--; } while ((FMC_BUSY == fmc_state) && (0x00U != timeout)); if (FMC_BUSY == fmc_state) { fmc_state = FMC_TOERR; } /* return the FMC state */ return fmc_state; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_fwdgt.c ================================================ /*! \file gd32vf103_fwdgt.c \brief FWDGT driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_fwdgt.h" #include "gd32vf103_rcu.h" /* write value to FWDGT_CTL_CMD bit field */ #define CTL_CMD(regval) (BITS(0, 15) & ((uint32_t)(regval) << 0)) /* write value to FWDGT_RLD_RLD bit field */ #define RLD_RLD(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*! \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none */ void fwdgt_write_enable(void) { FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; } /*! \brief disable write access to FWDGT_PSC and FWDGT_RLD \param[in] none \param[out] none \retval none */ void fwdgt_write_disable(void) { FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; } /*! \brief start the free watchdog timer counter \param[in] none \param[out] none \retval none */ void fwdgt_enable(void) { FWDGT_CTL = FWDGT_KEY_ENABLE; } /*! \brief reload the counter of FWDGT \param[in] none \param[out] none \retval none */ void fwdgt_counter_reload(void) { FWDGT_CTL = FWDGT_KEY_RELOAD; } /*! \brief configure counter reload value, and prescaler divider value \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) \param[in] prescaler_div: FWDGT prescaler value only one parameter can be selected which is shown as below: \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 \param[out] none \retval ErrStatus: ERROR or SUCCESS */ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; /* wait until the PUD flag to be reset */ do { flag_status = FWDGT_STAT & FWDGT_STAT_PUD; } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); if ((uint32_t)RESET != flag_status) { return ERROR; } /* configure FWDGT */ FWDGT_PSC = (uint32_t)prescaler_div; timeout = FWDGT_RLD_TIMEOUT; /* wait until the RUD flag to be reset */ do { flag_status = FWDGT_STAT & FWDGT_STAT_RUD; } while ((--timeout > 0U) && ((uint32_t)RESET != flag_status)); if ((uint32_t)RESET != flag_status) { return ERROR; } FWDGT_RLD = RLD_RLD(reload_value); /* reload the counter */ FWDGT_CTL = FWDGT_KEY_RELOAD; return SUCCESS; } /*! \brief get flag state of FWDGT \param[in] flag: flag to get only one parameter can be selected which is shown as below: \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus fwdgt_flag_get(uint16_t flag) { if (FWDGT_STAT & flag) { return SET; } return RESET; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_gpio.c ================================================ /*! \file gd32vf103_gpio.c \brief GPIO driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_gpio.h" #include "gd32vf103_rcu.h" #define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ #define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ #define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ #define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ #define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ #define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ #define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ #define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ #define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ /*! \brief reset GPIO port \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[out] none \retval none */ void gpio_deinit(uint32_t gpio_periph) { switch (gpio_periph) { case GPIOA: /* reset GPIOA */ rcu_periph_reset_enable(RCU_GPIOARST); rcu_periph_reset_disable(RCU_GPIOARST); break; case GPIOB: /* reset GPIOB */ rcu_periph_reset_enable(RCU_GPIOBRST); rcu_periph_reset_disable(RCU_GPIOBRST); break; case GPIOC: /* reset GPIOC */ rcu_periph_reset_enable(RCU_GPIOCRST); rcu_periph_reset_disable(RCU_GPIOCRST); break; case GPIOD: /* reset GPIOD */ rcu_periph_reset_enable(RCU_GPIODRST); rcu_periph_reset_disable(RCU_GPIODRST); break; case GPIOE: /* reset GPIOE */ rcu_periph_reset_enable(RCU_GPIOERST); rcu_periph_reset_disable(RCU_GPIOERST); break; default: break; } } /*! \brief reset alternate function I/O(AFIO) \param[in] none \param[out] none \retval none */ void gpio_afio_deinit(void) { rcu_periph_reset_enable(RCU_AFRST); rcu_periph_reset_disable(RCU_AFRST); } /*! \brief GPIO parameter initialization \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] mode: gpio pin mode only one parameter can be selected which is shown as below: \arg GPIO_MODE_AIN: analog input mode \arg GPIO_MODE_IN_FLOATING: floating input mode \arg GPIO_MODE_IPD: pull-down input mode \arg GPIO_MODE_IPU: pull-up input mode \arg GPIO_MODE_OUT_OD: GPIO output with open-drain \arg GPIO_MODE_OUT_PP: GPIO output with push-pull \arg GPIO_MODE_AF_OD: AFIO output with open-drain \arg GPIO_MODE_AF_PP: AFIO output with push-pull \param[in] speed: gpio output max speed value only one parameter can be selected which is shown as below: \arg GPIO_OSPEED_10MHZ: output max speed 10MHz \arg GPIO_OSPEED_2MHZ: output max speed 2MHz \arg GPIO_OSPEED_50MHZ: output max speed 50MHz \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) { uint16_t i; uint32_t temp_mode = 0U; uint32_t reg = 0U; /* GPIO mode configuration */ temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); /* GPIO speed configuration */ if (((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) { /* output mode max speed:10MHz,2MHz,50MHz */ temp_mode |= (uint32_t)speed; } /* configure the eight low port pins with GPIO_CTL0 */ for (i = 0U; i < 8U; i++) { if ((1U << i) & pin) { reg = GPIO_CTL0(gpio_periph); /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i, temp_mode); /* set IPD or IPU */ if (GPIO_MODE_IPD == mode) { /* reset the corresponding OCTL bit */ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); } else { /* set the corresponding OCTL bit */ if (GPIO_MODE_IPU == mode) { GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); } } /* set GPIO_CTL0 register */ GPIO_CTL0(gpio_periph) = reg; } } /* configure the eight high port pins with GPIO_CTL1 */ for (i = 8U; i < 16U; i++) { if ((1U << i) & pin) { reg = GPIO_CTL1(gpio_periph); /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i - 8U); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i - 8U, temp_mode); /* set IPD or IPU */ if (GPIO_MODE_IPD == mode) { /* reset the corresponding OCTL bit */ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); } else { /* set the corresponding OCTL bit */ if (GPIO_MODE_IPU == mode) { GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); } } /* set GPIO_CTL1 register */ GPIO_CTL1(gpio_periph) = reg; } } } /*! \brief set GPIO pin \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) { GPIO_BOP(gpio_periph) = (uint32_t)pin; } /*! \brief reset GPIO pin \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) { GPIO_BC(gpio_periph) = (uint32_t)pin; } /*! \brief write data to the specified GPIO pin \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[in] bit_value: SET or RESET only one parameter can be selected which is shown as below: \arg RESET: clear the port pin \arg SET: set the port pin \param[out] none \retval none */ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { if (RESET != bit_value) { GPIO_BOP(gpio_periph) = (uint32_t)pin; } else { GPIO_BC(gpio_periph) = (uint32_t)pin; } } /*! \brief write data to the specified GPIO port \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] data: specify the value to be written to the port output data register \param[out] none \retval none */ void gpio_port_write(uint32_t gpio_periph, uint16_t data) { GPIO_OCTL(gpio_periph) = (uint32_t)data; } /*! \brief get GPIO pin input status \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin only one parameter can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval input status of gpio pin: SET or RESET */ FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { if ((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { return SET; } else { return RESET; } } /*! \brief get GPIO port input status \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[out] none \retval input status of gpio all pins */ uint16_t gpio_input_port_get(uint32_t gpio_periph) { return (uint16_t)(GPIO_ISTAT(gpio_periph)); } /*! \brief get GPIO pin output status \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin only one parameter can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval output status of gpio pin: SET or RESET */ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { if ((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { return SET; } else { return RESET; } } /*! \brief get GPIO port output status \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[out] none \retval output status of gpio all pins */ uint16_t gpio_output_port_get(uint32_t gpio_periph) { return ((uint16_t)GPIO_OCTL(gpio_periph)); } /*! \brief configure GPIO pin remap \param[in] gpio_remap: select the pin to remap only one parameter can be selected which are shown as below: \arg GPIO_SPI0_REMAP: SPI0 remapping \arg GPIO_I2C0_REMAP: I2C0 remapping \arg GPIO_USART0_REMAP: USART0 remapping \arg GPIO_USART1_REMAP: USART1 remapping \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping \arg GPIO_USART2_FULL_REMAP: USART2 full remapping \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping \arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping \arg GPIO_TIMER3_REMAP: TIMER3 remapping \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping \arg GPIO_PD01_REMAP: PD01 remapping \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping \arg GPIO_CAN1_REMAP: CAN1 remapping \arg GPIO_SWJ_NONJTRST_REMAP: JTAG-DP,but without NJTRST \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled \arg GPIO_SPI2_REMAP: SPI2 remapping \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) { uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { /* get AFIO_PCF1 regiter value */ temp_reg = AFIO_PCF1; } else { /* get AFIO_PCF0 regiter value */ temp_reg = AFIO_PCF0; } temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; remap1 = remap & LSB_16BIT_MASK; /* judge pin remap type */ if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { temp_reg &= PCF_SWJCFG_MASK; AFIO_PCF0 &= PCF_SWJCFG_MASK; } else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) { remap2 = ((uint32_t)0x03U) << temp_mask; temp_reg &= ~remap2; temp_reg |= ~PCF_SWJCFG_MASK; } else { temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U)); temp_reg |= ~PCF_SWJCFG_MASK; } /* set pin remap value */ if (DISABLE != newvalue) { temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U)); } if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { /* set AFIO_PCF1 regiter value */ AFIO_PCF1 = temp_reg; } else { /* set AFIO_PCF0 regiter value */ AFIO_PCF0 = temp_reg; } } /*! \brief select GPIO pin exti sources \param[in] gpio_outputport: gpio event output port only one parameter can be selected which are shown as below: \arg GPIO_PORT_SOURCE_GPIOA: output port source A \arg GPIO_PORT_SOURCE_GPIOB: output port source B \arg GPIO_PORT_SOURCE_GPIOC: output port source C \arg GPIO_PORT_SOURCE_GPIOD: output port source D \arg GPIO_PORT_SOURCE_GPIOE: output port source E \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) \param[out] none \retval none */ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) { uint32_t source = 0U; source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); /* select EXTI sources */ if (GPIO_PIN_SOURCE_4 > output_pin) { /* select EXTI0/EXTI1/EXTI2/EXTI3 */ AFIO_EXTISS0 &= ~source; AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); } else if (GPIO_PIN_SOURCE_8 > output_pin) { /* select EXTI4/EXTI5/EXTI6/EXTI7 */ AFIO_EXTISS1 &= ~source; AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); } else if (GPIO_PIN_SOURCE_12 > output_pin) { /* select EXTI8/EXTI9/EXTI10/EXTI11 */ AFIO_EXTISS2 &= ~source; AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); } else { /* select EXTI12/EXTI13/EXTI14/EXTI15 */ AFIO_EXTISS3 &= ~source; AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); } } /*! \brief configure GPIO pin event output \param[in] output_port: gpio event output port only one parameter can be selected which are shown as below: \arg GPIO_EVENT_PORT_GPIOA: event output port A \arg GPIO_EVENT_PORT_GPIOB: event output port B \arg GPIO_EVENT_PORT_GPIOC: event output port C \arg GPIO_EVENT_PORT_GPIOD: event output port D \arg GPIO_EVENT_PORT_GPIOE: event output port E \param[in] output_pin: only one parameter can be selected which are shown as below: \arg GPIO_EVENT_PIN_x(x=0..15) \param[out] none \retval none */ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) { uint32_t reg = 0U; reg = AFIO_EC; /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN)); reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); reg |= (uint32_t)output_pin; AFIO_EC = reg; } /*! \brief enable GPIO pin event output \param[in] none \param[out] none \retval none */ void gpio_event_output_enable(void) { AFIO_EC |= AFIO_EC_EOE; } /*! \brief disable GPIO pin event output \param[in] none \param[out] none \retval none */ void gpio_event_output_disable(void) { AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); } /*! \brief lock GPIO pin \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) { uint32_t lock = 0x00010000U; lock |= pin; /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ GPIO_LOCK(gpio_periph) = (uint32_t)lock; GPIO_LOCK(gpio_periph) = (uint32_t)pin; GPIO_LOCK(gpio_periph) = (uint32_t)lock; lock = GPIO_LOCK(gpio_periph); lock = GPIO_LOCK(gpio_periph); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_i2c.c ================================================ /*! \file gd32vf103_i2c.c \brief I2C driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_i2c.h" #include "gd32vf103_rcu.h" /* I2C register bit mask */ #define I2CCLK_MAX ((uint32_t)0x00000036U) /*!< i2cclk maximum value */ #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ #define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ #define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ /* I2C register bit offset */ #define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ /*! \brief reset I2C \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_deinit(uint32_t i2c_periph) { switch (i2c_periph) { case I2C0: /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); rcu_periph_reset_disable(RCU_I2C0RST); break; case I2C1: /* reset I2C1 */ rcu_periph_reset_enable(RCU_I2C1RST); rcu_periph_reset_disable(RCU_I2C1RST); break; default: break; } } /*! \brief configure I2C clock \param[in] i2c_periph: I2Cx(x=0,1) \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) and fast mode plus (up to 1MHz) \param[in] dutycyc: duty cycle in fast mode or fast mode plus only one parameter can be selected which is shown as below: \arg I2C_DTCY_2: T_low/T_high=2 \arg I2C_DTCY_16_9: T_low/T_high=16/9 \param[out] none \retval none */ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { uint32_t pclk1, clkc, freq, risetime; uint32_t temp; pclk1 = rcu_clock_freq_get(CK_APB1); /* I2C peripheral clock frequency */ freq = (uint32_t)(pclk1 / 1000000U); if (freq >= I2CCLK_MAX) { freq = I2CCLK_MAX; } temp = I2C_CTL1(i2c_periph); temp &= ~I2C_CTL1_I2CCLK; temp |= freq; I2C_CTL1(i2c_periph) = temp; if (100000U >= clkspeed) { /* the maximum SCL rise time is 1000ns in standard mode */ risetime = (uint32_t)((pclk1 / 1000000U) + 1U); if (risetime >= I2CCLK_MAX) { I2C_RT(i2c_periph) = I2CCLK_MAX; } else if (risetime <= I2CCLK_MIN) { I2C_RT(i2c_periph) = I2CCLK_MIN; } else { I2C_RT(i2c_periph) = risetime; } clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); if (clkc < 0x04U) { /* the CLKC in standard mode minmum value is 4 */ clkc = 0x04U; } I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); } else if (400000U >= clkspeed) { /* the maximum SCL rise time is 300ns in fast mode */ I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); if (I2C_DTCY_2 == dutycyc) { /* I2C duty cycle is 2 */ clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; } else { /* I2C duty cycle is 16/9 */ clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } if (0U == (clkc & I2C_CKCFG_CLKC)) { /* the CLKC in fast mode minmum value is 1 */ clkc |= 0x0001U; } I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; } else { /* fast mode plus, the maximum SCL rise time is 120ns */ I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); if (I2C_DTCY_2 == dutycyc) { /* I2C duty cycle is 2 */ clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; } else { /* I2C duty cycle is 16/9 */ clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } /* enable fast mode */ I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; /* enable I2C fast mode plus */ I2C_FMPCFG(i2c_periph) |= I2C_FMPCFG_FMPEN; } } /*! \brief configure I2C address \param[in] i2c_periph: I2Cx(x=0,1) \param[in] mode: only one parameter can be selected which is shown as below: \arg I2C_I2CMODE_ENABLE: I2C mode \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits only one parameter can be selected which is shown as below: \arg I2C_ADDFORMAT_7BITS: 7bits \arg I2C_ADDFORMAT_10BITS: 10bits \param[in] addr: I2C address \param[out] none \retval none */ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SMBEN); ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ addr = addr & I2C_ADDRESS_MASK; I2C_SADDR0(i2c_periph) = (addformat | addr); } /*! \brief SMBus type selection \param[in] i2c_periph: I2Cx(x=0,1) \param[in] type: only one parameter can be selected which is shown as below: \arg I2C_SMBUS_DEVICE: device \arg I2C_SMBUS_HOST: host \param[out] none \retval none */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { if (I2C_SMBUS_HOST == type) { I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); } } /*! \brief whether or not to send an ACK \param[in] i2c_periph: I2Cx(x=0,1) \param[in] ack: only one parameter can be selected which is shown as below: \arg I2C_ACK_ENABLE: ACK will be sent \arg I2C_ACK_DISABLE: ACK will not be sent \param[out] none \retval none */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { if (I2C_ACK_ENABLE == ack) { I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); } } /*! \brief configure I2C POAP position \param[in] i2c_periph: I2Cx(x=0,1) \param[in] pos: only one parameter can be selected which is shown as below: \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte \param[out] none \retval none */ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { /* configure I2C POAP position */ if (I2C_ACKPOS_NEXT == pos) { I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); } } /*! \brief master sends slave address \param[in] i2c_periph: I2Cx(x=0,1) \param[in] addr: slave address \param[in] trandirection: transmitter or receiver only one parameter can be selected which is shown as below: \arg I2C_TRANSMITTER: transmitter \arg I2C_RECEIVER: receiver \param[out] none \retval none */ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) { /* master is a transmitter or a receiver */ if (I2C_TRANSMITTER == trandirection) { addr = addr & I2C_TRANSMITTER; } else { addr = addr | I2C_RECEIVER; } /* send slave address */ I2C_DATA(i2c_periph) = addr; } /*! \brief enable dual-address mode \param[in] i2c_periph: I2Cx(x=0,1) \param[in] dualaddr: the second address in dual-address mode \param[out] none \retval none */ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) { /* configure address */ dualaddr = dualaddr & I2C_ADDRESS2_MASK; I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | dualaddr); } /*! \brief disable dual-address mode \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_dualaddr_disable(uint32_t i2c_periph) { I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); } /*! \brief enable I2C \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_enable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; } /*! \brief disable I2C \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_disable(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); } /*! \brief generate a START condition on I2C bus \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_start_on_bus(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_START; } /*! \brief generate a STOP condition on I2C bus \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval none */ void i2c_stop_on_bus(uint32_t i2c_periph) { I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; } /*! \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1) \param[in] data: data of transmission \param[out] none \retval none */ void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) { I2C_DATA(i2c_periph) = DATA_TRANS(data); } /*! \brief I2C receive data function \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval data of received */ uint8_t i2c_data_receive(uint32_t i2c_periph) { return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); } /*! \brief enable I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1) \param[in] dmastate: only one parameter can be selected which is shown as below: \arg I2C_DMA_ON: DMA mode enable \arg I2C_DMA_OFF: DMA mode disable \param[out] none \retval none */ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) { /* configure I2C DMA function */ uint32_t ctl = 0U; ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMAON); ctl |= dmastate; I2C_CTL1(i2c_periph) = ctl; } /*! \brief configure whether next DMA EOT is DMA last transfer or not \param[in] i2c_periph: I2Cx(x=0,1) \param[in] dmalast: only one parameter can be selected which is shown as below: \arg I2C_DMALST_ON: next DMA EOT is the last transfer \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer \param[out] none \retval none */ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMALST); ctl |= dmalast; I2C_CTL1(i2c_periph) = ctl; } /*! \brief whether to stretch SCL low when data is not ready in slave mode \param[in] i2c_periph: I2Cx(x=0,1) \param[in] stretchpara: only one parameter can be selected which is shown as below: \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled \param[out] none \retval none */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { /* configure I2C SCL strerching enable or disable */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SS); ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } /*! \brief whether or not to response to a general call \param[in] i2c_periph: I2Cx(x=0,1) \param[in] gcallpara: only one parameter can be selected which is shown as below: \arg I2C_GCEN_ENABLE: slave will response to a general call \arg I2C_GCEN_DISABLE: slave will not response to a general call \param[out] none \retval none */ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_GCEN); ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } /*! \brief software reset I2C \param[in] i2c_periph: I2Cx(x=0,1) \param[in] sreset: only one parameter can be selected which is shown as below: \arg I2C_SRESET_SET: I2C is under reset \arg I2C_SRESET_RESET: I2C is not under reset \param[out] none \retval none */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) { /* modify CTL0 and configure software reset I2C state */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SRESET); ctl |= sreset; I2C_CTL0(i2c_periph) = ctl; } /*! \brief I2C PEC calculation on or off \param[in] i2c_periph: I2Cx(x=0,1) \param[in] pecpara: only one parameter can be selected which is shown as below: \arg I2C_PEC_ENABLE: PEC calculation on \arg I2C_PEC_DISABLE: PEC calculation off \param[out] none \retval none */ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECEN); ctl |= pecstate; I2C_CTL0(i2c_periph) = ctl; } /*! \brief I2C whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1) \param[in] pecpara: only one parameter can be selected which is shown as below: \arg I2C_PECTRANS_ENABLE: transfer PEC \arg I2C_PECTRANS_DISABLE: not transfer PEC \param[out] none \retval none */ void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; I2C_CTL0(i2c_periph) = ctl; } /*! \brief get packet error checking value \param[in] i2c_periph: I2Cx(x=0,1) \param[out] none \retval PEC value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph) { return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); } /*! \brief I2C issue alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1) \param[in] smbuspara: only one parameter can be selected which is shown as below: \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin \param[out] none \retval none */ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) { /* issue alert through SMBA pin configure*/ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; I2C_CTL0(i2c_periph) = ctl; } /*! \brief enable or disable I2C ARP protocol in SMBus switch \param[in] i2c_periph: I2Cx(x=0,1) \param[in] arpstate: only one parameter can be selected which is shown as below: \arg I2C_ARP_ENABLE: enable ARP \arg I2C_ARP_DISABLE: disable ARP \param[out] none \retval none */ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; I2C_CTL0(i2c_periph) = ctl; } /*! \brief check I2C flag is set or not \param[in] i2c_periph: I2Cx(x=0,1) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: \arg I2C_FLAG_SBSEND: start condition send out \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_BTC: byte transmission finishes \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode \arg I2C_FLAG_STPDET: stop condition detected in slave mode \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus \arg I2C_FLAG_LOSTARB: arbitration lost in master mode \arg I2C_FLAG_AERR: acknowledge error \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode \arg I2C_FLAG_I2CBSY: busy flag \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver \arg I2C_FLAG_RXGC: general call address (00h) received \arg I2C_FLAG_DEFSMB: default address of SMBus device \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode \arg I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { return SET; } else { return RESET; } } /*! \brief clear I2C flag \param[in] i2c_periph: I2Cx(x=0,1) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: \arg I2C_FLAG_SMBALT: SMBus Alert status \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_AERR: acknowledge error \arg I2C_FLAG_LOSTARB: arbitration lost in master mode \arg I2C_FLAG_BERR: a bus error \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 \param[out] none \retval none */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) { if (I2C_FLAG_ADDSEND == flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); } else { I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); } } /*! \brief enable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1) \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: \arg I2C_INT_ERR: error interrupt enable \arg I2C_INT_EV: event interrupt enable \arg I2C_INT_BUF: buffer interrupt enable \param[out] none \retval none */ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); } /*! \brief disable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1) \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_ERR: error interrupt enable \arg I2C_INT_EV: event interrupt enable \arg I2C_INT_BUF: buffer interrupt enable \param[out] none \retval none */ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) { I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); } /*! \brief check I2C interrupt flag \param[in] i2c_periph: I2Cx(x=0,1) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag \arg I2C_INT_FLAG_BTC: byte transmission finishes \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U, bufie; /* check BUFIE */ bufie = I2C_CTL1(i2c_periph) & I2C_CTL1_BUFIE; /* get the interrupt enable bit status */ intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); /* get the corresponding flag bit status */ flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { if (intenable && bufie) { intenable = 1U; } else { intenable = 0U; } } if ((0U != flagstatus) && (0U != intenable)) { return SET; } else { return RESET; } } /*! \brief clear I2C interrupt flag \param[in] i2c_periph: I2Cx(x=0,1) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag \param[out] none \retval none */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { if (I2C_INT_FLAG_ADDSEND == int_flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); } else { I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); } } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_pmu.c ================================================ /*! \file gd32vf103_pmu.c \brief PMU driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_pmu.h" #include "gd32vf103_rcu.h" #include "riscv_encoding.h" /*! \brief reset PMU register \param[in] none \param[out] none \retval none */ void pmu_deinit(void) { /* reset PMU */ rcu_periph_reset_enable(RCU_PMURST); rcu_periph_reset_disable(RCU_PMURST); } /*! \brief select low voltage detector threshold \param[in] lvdt_n: only one parameter can be selected which is shown as below: \arg PMU_LVDT_0: voltage threshold is 2.2V \arg PMU_LVDT_1: voltage threshold is 2.3V \arg PMU_LVDT_2: voltage threshold is 2.4V \arg PMU_LVDT_3: voltage threshold is 2.5V \arg PMU_LVDT_4: voltage threshold is 2.6V \arg PMU_LVDT_5: voltage threshold is 2.7V \arg PMU_LVDT_6: voltage threshold is 2.8V \arg PMU_LVDT_7: voltage threshold is 2.9V \param[out] none \retval none */ void pmu_lvd_select(uint32_t lvdt_n) { /* disable LVD */ PMU_CTL &= ~PMU_CTL_LVDEN; /* clear LVDT bits */ PMU_CTL &= ~PMU_CTL_LVDT; /* set LVDT bits according to lvdt_n */ PMU_CTL |= lvdt_n; /* enable LVD */ PMU_CTL |= PMU_CTL_LVDEN; } /*! \brief disable PMU lvd \param[in] none \param[out] none \retval none */ void pmu_lvd_disable(void) { /* disable LVD */ PMU_CTL &= ~PMU_CTL_LVDEN; } /*! \brief PMU work at sleep mode \param[in] sleepmodecmd: only one parameter can be selected which is shown as below: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of RISC-V system control register */ clear_csr(0x811U, 0x1U); /* select WFI or WFE command to enter sleep mode */ if (WFI_CMD == sleepmodecmd) { __WFI(); } else { clear_csr(mstatus, MSTATUS_MIE); set_csr(0x810U, 0x1U); __WFI(); clear_csr(0x810U, 0x1U); set_csr(mstatus, MSTATUS_MIE); } } /*! \brief PMU work at deepsleep mode \param[in] ldo: only one parameter can be selected which is shown as below: \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode \param[in] deepsleepmodecmd: only one parameter can be selected which is shown as below: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) { /* clear stbmod and ldolp bits */ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); /* set ldolp bit according to pmu_ldo */ PMU_CTL |= ldo; /* set CSR_SLEEPVALUE bit of RISC-V system control register */ set_csr(0x811U, 0x1U); /* select WFI or WFE command to enter deepsleep mode */ if (WFI_CMD == deepsleepmodecmd) { __WFI(); } else { clear_csr(mstatus, MSTATUS_MIE); set_csr(0x810U, 0x1U); __WFI(); clear_csr(0x810U, 0x1U); set_csr(mstatus, MSTATUS_MIE); } /* reset sleepdeep bit of RISC-V system control register */ clear_csr(0x811U, 0x1U); } /*! \brief pmu work at standby mode \param[in] standbymodecmd: only one parameter can be selected which is shown as below: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ void pmu_to_standbymode(uint8_t standbymodecmd) { /* set CSR_SLEEPVALUE bit of RISC-V system control register */ set_csr(0x811U, 0x1U); /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; /* select WFI or WFE command to enter standby mode */ if (WFI_CMD == standbymodecmd) { __WFI(); } else { clear_csr(mstatus, MSTATUS_MIE); set_csr(0x810U, 0x1U); __WFI(); clear_csr(0x810U, 0x1U); set_csr(mstatus, MSTATUS_MIE); } clear_csr(0x811U, 0x1U); } /*! \brief enable wakeup pin \param[in] none \param[out] none \retval none */ void pmu_wakeup_pin_enable(void) { PMU_CS |= PMU_CS_WUPEN; } /*! \brief disable wakeup pin \param[in] none \param[out] none \retval none */ void pmu_wakeup_pin_disable(void) { PMU_CS &= ~PMU_CS_WUPEN; } /*! \brief enable write access to the registers in backup domain \param[in] none \param[out] none \retval none */ void pmu_backup_write_enable(void) { PMU_CTL |= PMU_CTL_BKPWEN; } /*! \brief disable write access to the registers in backup domain \param[in] none \param[out] none \retval none */ void pmu_backup_write_disable(void) { PMU_CTL &= ~PMU_CTL_BKPWEN; } /*! \brief get flag state \param[in] flag: only one parameter can be selected which is shown as below: \arg PMU_FLAG_WAKEUP: wakeup flag \arg PMU_FLAG_STANDBY: standby flag \arg PMU_FLAG_LVD: lvd flag \param[out] none \retval FlagStatus SET or RESET */ FlagStatus pmu_flag_get(uint32_t flag) { if (PMU_CS & flag) { return SET; } else { return RESET; } } /*! \brief clear flag bit \param[in] flag_reset: only one parameter can be selected which is shown as below: \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag \arg PMU_FLAG_RESET_STANDBY: reset standby flag \param[out] none \retval none */ void pmu_flag_clear(uint32_t flag_reset) { switch (flag_reset) { case PMU_FLAG_RESET_WAKEUP: /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; break; case PMU_FLAG_RESET_STANDBY: /* reset standby flag */ PMU_CTL |= PMU_CTL_STBRST; break; default: break; } } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rcu.c ================================================ /*! \file gd32vf103_rcu.c \brief RCU driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_rcu.h" /* define startup timeout count */ #define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) #define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) /*! \brief deinitialize the RCU \param[in] none \param[out] none \retval none */ void rcu_deinit(void) { /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; rcu_osci_stab_wait(RCU_IRC8M); /* reset CTL register */ RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); RCU_CTL &= ~RCU_CTL_HXTALBPS; RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); /* reset CFG0 register */ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); /* reset INT and CFG1 register */ RCU_INT = 0x00ff0000U; RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); } /*! \brief enable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock \arg RCU_AF : alternate function clock \arg RCU_CRC: CRC clock \arg RCU_DMAx (x=0,1): DMA clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock \arg RCU_WWDGT: WWDGT clock \arg RCU_SPIx (x=0,1,2): SPI clock \arg RCU_USARTx (x=0,1,2): USART clock \arg RCU_UARTx (x=3,4): UART clock \arg RCU_I2Cx (x=0,1): I2C clock \arg RCU_CANx (x=0,1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock \arg RCU_ADCx (x=0,1): ADC clock \arg RCU_BKPI: BKP interface clock \param[out] none \retval none */ void rcu_periph_clock_enable(rcu_periph_enum periph) { RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); } /*! \brief disable the peripherals clock \param[in] periph: RCU peripherals, refer to rcu_periph_enum only one parameter can be selected which is shown as below: \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock \arg RCU_AF: alternate function clock \arg RCU_CRC: CRC clock \arg RCU_DMAx (x=0,1): DMA clock \arg RCU_USBFS: USBFS clock \arg RCU_EXMC: EXMC clock \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock \arg RCU_WWDGT: WWDGT clock \arg RCU_SPIx (x=0,1,2): SPI clock \arg RCU_USARTx (x=0,1,2): USART clock \arg RCU_UARTx (x=3,4): UART clock \arg RCU_I2Cx (x=0,1): I2C clock \arg RCU_CANx (x=0,1): CAN clock \arg RCU_PMU: PMU clock \arg RCU_DAC: DAC clock \arg RCU_RTC: RTC clock \arg RCU_ADCx (x=0,1): ADC clock \arg RCU_BKPI: BKP interface clock \param[out] none \retval none */ void rcu_periph_clock_disable(rcu_periph_enum periph) { RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); } /*! \brief enable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM_SLP: SRAM clock \param[out] none \retval none */ void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) { RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); } /*! \brief disable the peripherals clock when sleep mode \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum only one parameter can be selected which is shown as below: \arg RCU_FMC_SLP: FMC clock \arg RCU_SRAM_SLP: SRAM clock \param[out] none \retval none */ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) { RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); } /*! \brief reset the peripherals \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports \arg RCU_AFRST : reset alternate function clock \arg RCU_USBFSRST: reset USBFS \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER \arg RCU_WWDGTRST: reset WWDGT \arg RCU_SPIxRST (x=0,1,2): reset SPI \arg RCU_USARTxRST (x=0,1,2): reset USART \arg RCU_UARTxRST (x=3,4): reset UART \arg RCU_I2CxRST (x=0,1): reset I2C \arg RCU_CANxRST (x=0,1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC \arg RCU_ADCxRST (x=0,1): reset ADC \arg RCU_BKPIRST: reset BKPI \param[out] none \retval none */ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) { RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); } /*! \brief disable reset the peripheral \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum only one parameter can be selected which is shown as below: \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports \arg RCU_AFRST : reset alternate function clock \arg RCU_USBFSRST: reset USBFS \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER \arg RCU_WWDGTRST: reset WWDGT \arg RCU_SPIxRST (x=0,1,2): reset SPI \arg RCU_USARTxRST (x=0,1,2): reset USART \arg RCU_UARTxRST (x=3,4): reset UART \arg RCU_I2CxRST (x=0,1): reset I2C \arg RCU_CANxRST (x=0,1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC \arg RCU_ADCxRST (x=0,1): reset ADC \arg RCU_BKPIRST: reset BKPI \param[out] none \retval none */ void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) { RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); } /*! \brief reset the BKP domain \param[in] none \param[out] none \retval none */ void rcu_bkp_reset_enable(void) { RCU_BDCTL |= RCU_BDCTL_BKPRST; } /*! \brief disable the BKP domain reset \param[in] none \param[out] none \retval none */ void rcu_bkp_reset_disable(void) { RCU_BDCTL &= ~RCU_BDCTL_BKPRST; } /*! \brief configure the system clock source \param[in] ck_sys: system clock source select only one parameter can be selected which is shown as below: \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source \param[out] none \retval none */ void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; RCU_CFG0 = (reg | ck_sys); } /*! \brief get the system clock source \param[in] none \param[out] none \retval which clock is selected as CK_SYS source \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source */ uint32_t rcu_system_clock_source_get(void) { return (RCU_CFG0 & RCU_CFG0_SCSS); } /*! \brief configure the AHB clock prescaler selection \param[in] ck_ahb: AHB clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 \param[out] none \retval none */ void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; reg = RCU_CFG0; /* reset the AHBPSC bits and set according to ck_ahb */ reg &= ~RCU_CFG0_AHBPSC; RCU_CFG0 = (reg | ck_ahb); } /*! \brief configure the APB1 clock prescaler selection \param[in] ck_apb1: APB1 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 \param[out] none \retval none */ void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; reg = RCU_CFG0; /* reset the APB1PSC and set according to ck_apb1 */ reg &= ~RCU_CFG0_APB1PSC; RCU_CFG0 = (reg | ck_apb1); } /*! \brief configure the APB2 clock prescaler selection \param[in] ck_apb2: APB2 clock prescaler selection only one parameter can be selected which is shown as below: \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 \param[out] none \retval none */ void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; reg = RCU_CFG0; /* reset the APB2PSC and set according to ck_apb2 */ reg &= ~RCU_CFG0_APB2PSC; RCU_CFG0 = (reg | ck_apb2); } /*! \brief configure the CK_OUT0 clock source \param[in] ckout0_src: CK_OUT0 clock source selection only one parameter can be selected which is shown as below: \arg RCU_CKOUT0SRC_NONE: no clock selected \arg RCU_CKOUT0SRC_CKSYS: system clock selected \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected \arg RCU_CKOUT0SRC_EXT1: EXT1 selected \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected \param[out] none \retval none */ void rcu_ckout0_config(uint32_t ckout0_src) { uint32_t reg; reg = RCU_CFG0; /* reset the CKOUT0SRC, set according to ckout0_src */ reg &= ~RCU_CFG0_CKOUT0SEL; RCU_CFG0 = (reg | ckout0_src); } /*! \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection only one parameter can be selected which is shown as below: \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: \arg RCU_PLL_MULx (x = 2..14, 6.5, 16..32) \param[out] none \retval none */ void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) { uint32_t reg = 0U; reg = RCU_CFG0; /* PLL clock source and multiplication factor configuration */ reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); reg |= (pll_src | pll_mul); RCU_CFG0 = reg; } /*! \brief configure the PREDV0 division factor and clock source \param[in] predv0_source: PREDV0 input clock source selection only one parameter can be selected which is shown as below: \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock \param[in] predv0_div: PREDV0 division factor only one parameter can be selected which is shown as below: \arg RCU_PREDV0_DIVx, x = 1..16 \param[out] none \retval none */ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) { uint32_t reg = 0U; reg = RCU_CFG1; /* reset PREDV0SEL and PREDV0 bits */ reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); /* set the PREDV0SEL and PREDV0 division factor */ reg |= (predv0_source | predv0_div); RCU_CFG1 = reg; } /*! \brief configure the PREDV1 division factor \param[in] predv1_div: PREDV1 division factor only one parameter can be selected which is shown as below: \arg RCU_PREDV1_DIVx, x = 1..16 \param[out] none \retval none */ void rcu_predv1_config(uint32_t predv1_div) { uint32_t reg = 0U; reg = RCU_CFG1; /* reset the PREDV1 bits */ reg &= ~RCU_CFG1_PREDV1; /* set the PREDV1 division factor */ reg |= predv1_div; RCU_CFG1 = reg; } /*! \brief configure the PLL1 clock \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: \arg RCU_PLL1_MULx (x = 8..16, 20) \param[out] none \retval none */ void rcu_pll1_config(uint32_t pll_mul) { RCU_CFG1 &= ~RCU_CFG1_PLL1MF; RCU_CFG1 |= pll_mul; } /*! \brief configure the PLL2 clock \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: \arg RCU_PLL2_MULx (x = 8..16, 20) \param[out] none \retval none */ void rcu_pll2_config(uint32_t pll_mul) { RCU_CFG1 &= ~RCU_CFG1_PLL2MF; RCU_CFG1 |= pll_mul; } /*! \brief configure the ADC prescaler factor \param[in] adc_psc: ADC prescaler factor only one parameter can be selected which is shown as below: \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 \param[out] none \retval none */ void rcu_adc_clock_config(uint32_t adc_psc) { uint32_t reg0; /* reset the ADCPSC bits */ reg0 = RCU_CFG0; reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); /* set the ADC prescaler factor */ switch (adc_psc) { case RCU_CKADC_CKAPB2_DIV2: case RCU_CKADC_CKAPB2_DIV4: case RCU_CKADC_CKAPB2_DIV6: case RCU_CKADC_CKAPB2_DIV8: reg0 |= (adc_psc << 14); break; case RCU_CKADC_CKAPB2_DIV12: case RCU_CKADC_CKAPB2_DIV16: adc_psc &= ~BIT(2); reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); break; default: break; } /* set the register */ RCU_CFG0 = reg0; } /*! \brief configure the USBFS prescaler factor \param[in] usb_psc: USB prescaler factor only one parameter can be selected which is shown as below: \arg RCU_CKUSB_CKPLL_DIV1_5: USBFS prescaler select CK_PLL/1.5 \arg RCU_CKUSB_CKPLL_DIV1: USBFS prescaler select CK_PLL/1 \arg RCU_CKUSB_CKPLL_DIV2_5: USBFS prescaler select CK_PLL/2.5 \arg RCU_CKUSB_CKPLL_DIV2: USBFS prescaler select CK_PLL/2 \param[out] none \retval none */ void rcu_usb_clock_config(uint32_t usb_psc) { uint32_t reg; reg = RCU_CFG0; /* configure the USBFS prescaler factor */ reg &= ~RCU_CFG0_USBFSPSC; RCU_CFG0 = (reg | usb_psc); } /*! \brief configure the RTC clock source selection \param[in] rtc_clock_source: RTC clock source selection only one parameter can be selected which is shown as below: \arg RCU_RTCSRC_NONE: no clock selected \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock \param[out] none \retval none */ void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; reg = RCU_BDCTL; /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); } /*! \brief configure the I2S1 clock source selection \param[in] i2s_clock_source: I2S1 clock source selection only one parameter can be selected which is shown as below: \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock \param[out] none \retval none */ void rcu_i2s1_clock_config(uint32_t i2s_clock_source) { uint32_t reg; reg = RCU_CFG1; /* reset the I2S1SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S1SEL; RCU_CFG1 = (reg | i2s_clock_source); } /*! \brief configure the I2S2 clock source selection \param[in] i2s_clock_source: I2S2 clock source selection only one parameter can be selected which is shown as below: \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock \param[out] none \retval none */ void rcu_i2s2_clock_config(uint32_t i2s_clock_source) { uint32_t reg; reg = RCU_CFG1; /* reset the I2S2SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S2SEL; RCU_CFG1 = (reg | i2s_clock_source); } /*! \brief get the clock stabilization and periphral reset flags \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum only one parameter can be selected which is shown as below: \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag \arg RCU_FLAG_PLLSTB: PLL stabilization flag \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag \arg RCU_FLAG_EPRST: external PIN reset flag \arg RCU_FLAG_PORRST: power reset flag \arg RCU_FLAG_SWRST: software reset flag \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag \arg RCU_FLAG_LPRST: low-power reset flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus rcu_flag_get(rcu_flag_enum flag) { /* get the rcu flag */ if (RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { return SET; } else { return RESET; } } /*! \brief clear all the reset flag \param[in] none \param[out] none \retval none */ void rcu_all_reset_flag_clear(void) { RCU_RSTSCK |= RCU_RSTSCK_RSTFC; } /*! \brief get the clock stabilization interrupt and ckm flags \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum only one parameter can be selected which is shown as below: \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) { /* get the rcu interrupt flag */ if (RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { return SET; } else { return RESET; } } /*! \brief clear the interrupt flags \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below: \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear \param[out] none \retval none */ void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) { RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); } /*! \brief enable the stabilization interrupt \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum Only one parameter can be selected which is shown as below: \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable \param[out] none \retval none */ void rcu_interrupt_enable(rcu_int_enum stab_int) { RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); } /*! \brief disable the stabilization interrupt \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum only one parameter can be selected which is shown as below: \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable \param[out] none \retval none */ void rcu_interrupt_disable(rcu_int_enum stab_int) { RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); } /*! \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) \arg RCU_PLL_CK: phase locked loop(PLL) \arg RCU_PLL1_CK: phase locked loop 1 \arg RCU_PLL2_CK: phase locked loop 2 \param[out] none \retval ErrStatus: SUCCESS or ERROR */ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) { uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; switch (osci) { /* wait HXTAL stable */ case RCU_HXTAL: while ((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { reval = SUCCESS; } break; /* wait LXTAL stable */ case RCU_LXTAL: while ((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { reval = SUCCESS; } break; /* wait IRC8M stable */ case RCU_IRC8M: while ((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { reval = SUCCESS; } break; /* wait IRC40K stable */ case RCU_IRC40K: while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { reval = SUCCESS; } break; /* wait PLL stable */ case RCU_PLL_CK: while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { reval = SUCCESS; } break; /* wait PLL1 stable */ case RCU_PLL1_CK: while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { reval = SUCCESS; } break; /* wait PLL2 stable */ case RCU_PLL2_CK: while ((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); stb_cnt++; } /* check whether flag is set or not */ if (RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { reval = SUCCESS; } break; default: break; } /* return value */ return reval; } /*! \brief turn on the oscillator \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) \arg RCU_PLL_CK: phase locked loop(PLL) \arg RCU_PLL1_CK: phase locked loop 1 \arg RCU_PLL2_CK: phase locked loop 2 \param[out] none \retval none */ void rcu_osci_on(rcu_osci_type_enum osci) { RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); } /*! \brief turn off the oscillator \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) \arg RCU_PLL_CK: phase locked loop(PLL) \arg RCU_PLL1_CK: phase locked loop 1 \arg RCU_PLL2_CK: phase locked loop 2 \param[out] none \retval none */ void rcu_osci_off(rcu_osci_type_enum osci) { RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); } /*! \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) { uint32_t reg; switch (osci) { /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; RCU_CTL = (reg | RCU_CTL_HXTALBPS); break; /* enable LXTAL to bypass mode */ case RCU_LXTAL: reg = RCU_BDCTL; RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); break; case RCU_IRC8M: case RCU_IRC40K: case RCU_PLL_CK: case RCU_PLL1_CK: case RCU_PLL2_CK: break; default: break; } } /*! \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it \param[in] osci: oscillator types, refer to rcu_osci_type_enum only one parameter can be selected which is shown as below: \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) \param[out] none \retval none */ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; switch (osci) { /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; RCU_CTL &= ~RCU_CTL_HXTALEN; RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); break; /* disable LXTAL to bypass mode */ case RCU_LXTAL: reg = RCU_BDCTL; RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); break; case RCU_IRC8M: case RCU_IRC40K: case RCU_PLL_CK: case RCU_PLL1_CK: case RCU_PLL2_CK: break; default: break; } } /*! \brief enable the HXTAL clock monitor \param[in] none \param[out] none \retval none */ void rcu_hxtal_clock_monitor_enable(void) { RCU_CTL |= RCU_CTL_CKMEN; } /*! \brief disable the HXTAL clock monitor \param[in] none \param[out] none \retval none */ void rcu_hxtal_clock_monitor_disable(void) { RCU_CTL &= ~RCU_CTL_CKMEN; } /*! \brief set the IRC8M adjust value \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F \param[out] none \retval none */ void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) { uint32_t reg; reg = RCU_CTL; /* reset the IRC8MADJ bits and set according to irc8m_adjval */ reg &= ~RCU_CTL_IRC8MADJ; RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); } /*! \brief deep-sleep mode voltage select \param[in] dsvol: deep sleep mode voltage only one parameter can be selected which is shown as below: \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V \param[out] none \retval none */ void rcu_deepsleep_voltage_set(uint32_t dsvol) { dsvol &= RCU_DSV_DSLPVS; RCU_DSV = dsvol; } /*! \brief get the system clock, bus and peripheral clock frequency \param[in] clock: the clock frequency which to get only one parameter can be selected which is shown as below: \arg CK_SYS: system clock frequency \arg CK_AHB: AHB clock frequency \arg CK_APB1: APB1 clock frequency \arg CK_APB2: APB2 clock frequency \param[out] none \retval clock frequency of system, AHB, APB1, APB2 */ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) { uint32_t sws, ck_freq = 0U; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; uint32_t pllsel, predv0sel, pllmf, ck_src, idx, clk_exp; uint32_t predv0, predv1, pll1mf; /* exponent of AHB, APB1 and APB2 clock divider */ uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; sws = GET_BITS(RCU_CFG0, 2, 3); switch (sws) { /* IRC8M is selected as CK_SYS */ case SEL_IRC8M: cksys_freq = IRC8M_VALUE; break; /* HXTAL is selected as CK_SYS */ case SEL_HXTAL: cksys_freq = HXTAL_VALUE; break; /* PLL is selected as CK_SYS */ case SEL_PLL: /* PLL clock source selection, HXTAL or IRC8M/2 */ pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); if (RCU_PLLSRC_HXTAL == pllsel) { /* PLL clock source is HXTAL */ ck_src = HXTAL_VALUE; predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); /* source clock use PLL1 */ if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; if (17U == pll1mf) { pll1mf = 20U; } ck_src = (ck_src / predv1) * pll1mf; } predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; ck_src /= predv0; } else { /* PLL clock source is IRC8M/2 */ ck_src = IRC8M_VALUE / 2U; } /* PLL multiplication factor */ pllmf = GET_BITS(RCU_CFG0, 18, 21); if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { pllmf |= 0x10U; } if (pllmf < 15U) { pllmf += 2U; } else { pllmf += 1U; } cksys_freq = ck_src * pllmf; if (15U == pllmf) { /* PLL source clock multiply by 6.5 */ cksys_freq = ck_src * 6U + ck_src / 2U; } break; /* IRC8M is selected as CK_SYS */ default: cksys_freq = IRC8M_VALUE; break; } /* calculate AHB clock frequency */ idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 8, 10); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 11, 13); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; /* return the clocks frequency */ switch (clock) { case CK_SYS: ck_freq = cksys_freq; break; case CK_AHB: ck_freq = ahb_freq; break; case CK_APB1: ck_freq = apb1_freq; break; case CK_APB2: ck_freq = apb2_freq; break; default: break; } return ck_freq; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_rtc.c ================================================ /*! \file gd32vf103_rtc.c \brief RTC driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_rtc.h" #include "gd32vf103_rcu.h" /* RTC register high / low bits mask */ #define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ #define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ /* RTC register high bits offset */ #define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) /*! \brief enter RTC configuration mode \param[in] none \param[out] none \retval none */ void rtc_configuration_mode_enter(void) { RTC_CTL |= RTC_CTL_CMF; } /*! \brief exit RTC configuration mode \param[in] none \param[out] none \retval none */ void rtc_configuration_mode_exit(void) { RTC_CTL &= ~RTC_CTL_CMF; } /*! \brief set RTC counter value \param[in] cnt: RTC counter value \param[out] none \retval none */ void rtc_counter_set(uint32_t cnt) { rtc_configuration_mode_enter(); /* set the RTC counter high bits */ RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); /* set the RTC counter low bits */ RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); rtc_configuration_mode_exit(); } /*! \brief set RTC prescaler value \param[in] psc: RTC prescaler value \param[out] none \retval none */ void rtc_prescaler_set(uint32_t psc) { rtc_configuration_mode_enter(); /* set the RTC prescaler high bits */ RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); /* set the RTC prescaler low bits */ RTC_PSCL = (psc & RTC_LOW_BITS_MASK); rtc_configuration_mode_exit(); } /*! \brief wait RTC last write operation finished flag set \param[in] none \param[out] none \retval none */ void rtc_lwoff_wait(void) { /* loop until LWOFF flag is set */ while (RESET == (RTC_CTL & RTC_CTL_LWOFF)) { } } /*! \brief wait RTC registers synchronized flag set \param[in] none \param[out] none \retval none */ void rtc_register_sync_wait(void) { /* clear RSYNF flag */ RTC_CTL &= ~RTC_CTL_RSYNF; /* loop until RSYNF flag is set */ while (RESET == (RTC_CTL & RTC_CTL_RSYNF)) { } } /*! \brief set RTC alarm value \param[in] alarm: RTC alarm value \param[out] none \retval none */ void rtc_alarm_config(uint32_t alarm) { rtc_configuration_mode_enter(); /* set the alarm high bits */ RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); /* set the alarm low bits */ RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); rtc_configuration_mode_exit(); } /*! \brief get RTC counter value \param[in] none \param[out] none \retval RTC counter value */ uint32_t rtc_counter_get(void) { uint32_t temp = 0x0U; temp = RTC_CNTL; temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); return temp; } /*! \brief get RTC divider value \param[in] none \param[out] none \retval RTC divider value */ uint32_t rtc_divider_get(void) { uint32_t temp = 0x00U; temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); temp |= RTC_DIVL; return temp; } /*! \brief get RTC flag status \param[in] flag: specify which flag status to get only one parameter can be selected which is shown as below: \arg RTC_FLAG_SECOND: second interrupt flag \arg RTC_FLAG_ALARM: alarm interrupt flag \arg RTC_FLAG_OVERFLOW: overflow interrupt flag \arg RTC_FLAG_RSYN: registers synchronized flag \arg RTC_FLAG_LWOF: last write operation finished flag \param[out] none \retval SET or RESET */ FlagStatus rtc_flag_get(uint32_t flag) { if (RESET != (RTC_CTL & flag)) { return SET; } else { return RESET; } } /*! \brief clear RTC flag status \param[in] flag: specify which flag status to clear one or more parameters can be selected which are shown as below: \arg RTC_FLAG_SECOND: second interrupt flag \arg RTC_FLAG_ALARM: alarm interrupt flag \arg RTC_FLAG_OVERFLOW: overflow interrupt flag \arg RTC_FLAG_RSYN: registers synchronized flag \param[out] none \retval none */ void rtc_flag_clear(uint32_t flag) { /* clear RTC flag */ RTC_CTL &= ~flag; } /*! \brief get RTC interrupt flag status \param[in] flag: specify which flag status to get only one parameter can be selected which is shown as below: \arg RTC_INT_FLAG_SECOND: second interrupt flag \arg RTC_INT_FLAG_ALARM: alarm interrupt flag \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag \param[out] none \retval SET or RESET */ FlagStatus rtc_interrupt_flag_get(uint32_t flag) { if (RESET != (RTC_CTL & flag)) { return SET; } else { return RESET; } } /*! \brief clear RTC interrupt flag status \param[in] flag: specify which flag status to clear one or more parameters can be selected which are shown as below: \arg RTC_INT_FLAG_SECOND: second interrupt flag \arg RTC_INT_FLAG_ALARM: alarm interrupt flag \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag \param[out] none \retval none */ void rtc_interrupt_flag_clear(uint32_t flag) { /* clear RTC interrupt flag */ RTC_CTL &= ~flag; } /*! \brief enable RTC interrupt \param[in] interrupt: specify which interrupt to enbale one or more parameters can be selected which are shown as below: \arg RTC_INT_SECOND: second interrupt \arg RTC_INT_ALARM: alarm interrupt \arg RTC_INT_OVERFLOW: overflow interrupt \param[out] none \retval none */ void rtc_interrupt_enable(uint32_t interrupt) { RTC_INTEN |= interrupt; } /*! \brief disable RTC interrupt \param[in] interrupt: specify which interrupt to disbale one or more parameters can be selected which are shown as below: \arg RTC_INT_SECOND: second interrupt \arg RTC_INT_ALARM: alarm interrupt \arg RTC_INT_OVERFLOW: overflow interrupt \param[out] none \retval none */ void rtc_interrupt_disable(uint32_t interrupt) { RTC_INTEN &= ~interrupt; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_spi.c ================================================ /*! \file gd32vf103_spi.c \brief SPI driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_spi.h" #include "gd32vf103_rcu.h" /* SPI/I2S parameter initialization mask */ #define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ #define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ /* I2S clock source selection, multiplication and division mask */ #define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ #define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ #define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ #define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ /* default value and offset */ #define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ #define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ #define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ /*! \brief reset SPI and I2S \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_i2s_deinit(uint32_t spi_periph) { switch (spi_periph) { case SPI0: /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); rcu_periph_reset_disable(RCU_SPI0RST); break; case SPI1: /* reset SPI1 and I2S1 */ rcu_periph_reset_enable(RCU_SPI1RST); rcu_periph_reset_disable(RCU_SPI1RST); break; case SPI2: /* reset SPI2 and I2S2 */ rcu_periph_reset_enable(RCU_SPI2RST); rcu_periph_reset_disable(RCU_SPI2RST); break; default: break; } } /*! \brief initialize the parameters of SPI struct with the default values \param[in] spi_struct: SPI parameter stuct \param[out] none \retval none */ void spi_struct_para_init(spi_parameter_struct *spi_struct) { /* set the SPI struct with the default values */ spi_struct->device_mode = SPI_SLAVE; spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; spi_struct->frame_size = SPI_FRAMESIZE_8BIT; spi_struct->nss = SPI_NSS_HARD; spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; spi_struct->prescale = SPI_PSC_2; } /*! \brief initialize SPI parameter \param[in] spi_periph: SPIx(x=0,1,2) \param[in] spi_struct: SPI parameter initialization stuct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT nss: SPI_NSS_SOFT, SPI_NSS_HARD endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) \param[out] none \retval none */ void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) { uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); reg &= SPI_INIT_MASK; /* select SPI as master or slave */ reg |= spi_struct->device_mode; /* select SPI transfer mode */ reg |= spi_struct->trans_mode; /* select SPI frame size */ reg |= spi_struct->frame_size; /* select SPI NSS use hardware or software */ reg |= spi_struct->nss; /* select SPI LSB or MSB */ reg |= spi_struct->endian; /* select SPI polarity and phase */ reg |= spi_struct->clock_polarity_phase; /* select SPI prescale to adjust transmit speed */ reg |= spi_struct->prescale; /* write to SPI_CTL0 register */ SPI_CTL0(spi_periph) = (uint32_t)reg; SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); } /*! \brief enable SPI \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_enable(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; } /*! \brief disable SPI \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_disable(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); } /*! \brief initialize I2S parameter \param[in] spi_periph: SPIx(x=1,2) \param[in] mode: I2S operation mode only one parameter can be selected which is shown as below: \arg I2S_MODE_SLAVETX: I2S slave transmit mode \arg I2S_MODE_SLAVERX: I2S slave receive mode \arg I2S_MODE_MASTERTX: I2S master transmit mode \arg I2S_MODE_MASTERRX: I2S master receive mode \param[in] standard: I2S standard only one parameter can be selected which is shown as below: \arg I2S_STD_PHILLIPS: I2S phillips standard \arg I2S_STD_MSB: I2S MSB standard \arg I2S_STD_LSB: I2S LSB standard \arg I2S_STD_PCMSHORT: I2S PCM short standard \arg I2S_STD_PCMLONG: I2S PCM long standard \param[in] ckpl: I2S idle state clock polarity only one parameter can be selected which is shown as below: \arg I2S_CKPL_LOW: I2S clock polarity low level \arg I2S_CKPL_HIGH: I2S clock polarity high level \param[out] none \retval none */ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) { uint32_t reg = 0U; reg = SPI_I2SCTL(spi_periph); reg &= I2S_INIT_MASK; /* enable I2S mode */ reg |= (uint32_t)SPI_I2SCTL_I2SSEL; /* select I2S mode */ reg |= (uint32_t)mode; /* select I2S standard */ reg |= (uint32_t)standard; /* select I2S polarity */ reg |= (uint32_t)ckpl; /* write to SPI_I2SCTL register */ SPI_I2SCTL(spi_periph) = (uint32_t)reg; } /*! \brief configure I2S prescaler \param[in] spi_periph: SPIx(x=1,2) \param[in] audiosample: I2S audio sample rate only one parameter can be selected which is shown as below: \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz \param[in] frameformat: I2S data length and channel length only one parameter can be selected which is shown as below: \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit \param[in] mckout: I2S master clock output only one parameter can be selected which is shown as below: \arg I2S_MCKOUT_ENABLE: I2S master clock output enable \arg I2S_MCKOUT_DISABLE: I2S master clock output disable \param[out] none \retval none */ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) { uint32_t i2sdiv = 2U, i2sof = 0U; uint32_t clks = 0U; uint32_t i2sclock = 0U; /* deinit SPI_I2SPSC register */ SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; /* get the I2S clock source */ if (SPI1 == ((uint32_t)spi_periph)) { /* I2S1 clock source selection */ clks = I2S1_CLOCK_SEL; } else { /* I2S2 clock source selection */ clks = I2S2_CLOCK_SEL; } if (0U != (RCU_CFG1 & clks)) { /* get RCU PLL2 clock multiplication factor */ clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); if ((clks > 5U) && (clks < 15U)) { /* multiplier is between 8 and 16 */ clks += 2U; } else { if (15U == clks) { /* multiplier is 20 */ clks = 20U; } } /* get the PREDV1 value */ i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); /* calculate I2S clock based on PLL2 and PREDV1 */ i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); } else { /* get system clock */ i2sclock = rcu_clock_freq_get(CK_SYS); } /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ if (I2S_MCKOUT_ENABLE == mckout) { clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); } else { if (I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); } else { clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); } } /* remove the floating point */ clks = (clks + 5U) / 10U; i2sof = (clks & 0x00000001U); i2sdiv = ((clks - i2sof) / 2U); i2sof = (i2sof << 8U); /* set the default values */ if ((i2sdiv < 2U) || (i2sdiv > 255U)) { i2sdiv = 2U; i2sof = 0U; } /* configure SPI_I2SPSC */ SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); /* configure data frame format */ SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; } /*! \brief enable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ void i2s_enable(uint32_t spi_periph) { SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; } /*! \brief disable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none */ void i2s_disable(uint32_t spi_periph) { SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); } /*! \brief enable SPI NSS output \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nss_output_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; } /*! \brief disable SPI NSS output \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nss_output_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); } /*! \brief SPI NSS pin high level in software mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nss_internal_high(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; } /*! \brief SPI NSS pin low level in software mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nss_internal_low(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); } /*! \brief enable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2) \param[in] dma: SPI DMA mode only one parameter can be selected which is shown as below: \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA \arg SPI_DMA_RECEIVE: SPI receive data using DMA \param[out] none \retval none */ void spi_dma_enable(uint32_t spi_periph, uint8_t dma) { if (SPI_DMA_TRANSMIT == dma) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; } else { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; } } /*! \brief disable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2) \param[in] dma: SPI DMA mode only one parameter can be selected which is shown as below: \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA \arg SPI_DMA_RECEIVE: SPI receive data using DMA \param[out] none \retval none */ void spi_dma_disable(uint32_t spi_periph, uint8_t dma) { if (SPI_DMA_TRANSMIT == dma) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); } else { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); } } /*! \brief configure SPI/I2S data frame format \param[in] spi_periph: SPIx(x=0,1,2) \param[in] frame_format: SPI frame size only one parameter can be selected which is shown as below: \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits \param[out] none \retval none */ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) { /* clear SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); /* configure SPI_CTL0_FF16 bit */ SPI_CTL0(spi_periph) |= (uint32_t)frame_format; } /*! \brief SPI transmit data \param[in] spi_periph: SPIx(x=0,1,2) \param[in] data: 16-bit data \param[out] none \retval none */ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) { SPI_DATA(spi_periph) = (uint32_t)data; } /*! \brief SPI receive data \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval 16-bit data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph) { return ((uint16_t)SPI_DATA(spi_periph)); } /*! \brief configure SPI bidirectional transfer direction \param[in] spi_periph: SPIx(x=0,1,2) \param[in] transfer_direction: SPI transfer direction only one parameter can be selected which is shown as below: \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode \param[out] none \retval none */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) { if (SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { /* set the transmit-only mode */ SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; } else { /* set the receive-only mode */ SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; } } /*! \brief set SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2) \param[in] crc_poly: CRC polynomial value \param[out] none \retval none */ void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) { /* enable SPI CRC */ SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; /* set SPI CRC polynomial */ SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; } /*! \brief get SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval 16-bit CRC polynomial */ uint16_t spi_crc_polynomial_get(uint32_t spi_periph) { return ((uint16_t)SPI_CRCPOLY(spi_periph)); } /*! \brief turn on CRC function \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_crc_on(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; } /*! \brief turn off CRC function \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_crc_off(uint32_t spi_periph) { SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); } /*! \brief SPI next data is CRC value \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_crc_next(uint32_t spi_periph) { SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; } /*! \brief get SPI CRC send value or receive value \param[in] spi_periph: SPIx(x=0,1,2) \param[in] crc: SPI crc value only one parameter can be selected which is shown as below: \arg SPI_CRC_TX: get transmit crc value \arg SPI_CRC_RX: get receive crc value \param[out] none \retval 16-bit CRC value */ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) { if (SPI_CRC_TX == crc) { return ((uint16_t)(SPI_TCRC(spi_periph))); } else { return ((uint16_t)(SPI_RCRC(spi_periph))); } } /*! \brief enable SPI TI mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_ti_mode_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; } /*! \brief disable SPI TI mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_ti_mode_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); } /*! \brief enable SPI NSS pulse mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nssp_mode_enable(uint32_t spi_periph) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; } /*! \brief disable SPI NSS pulse mode \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_nssp_mode_disable(uint32_t spi_periph) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); } /*! \brief enable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2) \param[in] interrupt: SPI/I2S interrupt only one parameter can be selected which is shown as below: \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt \param[out] none \retval none */ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) { switch (interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; break; /* SPI/I2S receive buffer not empty interrupt */ case SPI_I2S_INT_RBNE: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; break; /* SPI/I2S error */ case SPI_I2S_INT_ERR: SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; break; default: break; } } /*! \brief disable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2) \param[in] interrupt: SPI/I2S interrupt only one parameter can be selected which is shown as below: \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, transmission underrun error and format error interrupt \param[out] none \retval none */ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) { switch (interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_TBE: SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); break; /* SPI/I2S receive buffer not empty interrupt */ case SPI_I2S_INT_RBNE: SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); break; /* SPI/I2S error */ case SPI_I2S_INT_ERR: SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); break; default: break; } } /*! \brief get SPI and I2S interrupt flag status \param[in] spi_periph: SPIx(x=0,1,2) \param[in] interrupt: SPI/I2S interrupt flag status only one parameter can be selected which is shown as below: \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag \arg SPI_INT_FLAG_CONFERR: config error interrupt flag \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) { uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); switch (interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_FLAG_TBE: reg1 = reg1 & SPI_STAT_TBE; reg2 = reg2 & SPI_CTL1_TBEIE; break; /* SPI/I2S receive buffer not empty interrupt */ case SPI_I2S_INT_FLAG_RBNE: reg1 = reg1 & SPI_STAT_RBNE; reg2 = reg2 & SPI_CTL1_RBNEIE; break; /* SPI/I2S overrun interrupt */ case SPI_I2S_INT_FLAG_RXORERR: reg1 = reg1 & SPI_STAT_RXORERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; /* SPI config error interrupt */ case SPI_INT_FLAG_CONFERR: reg1 = reg1 & SPI_STAT_CONFERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; /* SPI CRC error interrupt */ case SPI_INT_FLAG_CRCERR: reg1 = reg1 & SPI_STAT_CRCERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; /* I2S underrun error interrupt */ case I2S_INT_FLAG_TXURERR: reg1 = reg1 & SPI_STAT_TXURERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; /* SPI/I2S format error interrupt */ case SPI_I2S_INT_FLAG_FERR: reg1 = reg1 & SPI_STAT_FERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; default: break; } /* get SPI/I2S interrupt flag status */ if ((0U != reg1) && (0U != reg2)) { return SET; } else { return RESET; } } /*! \brief get SPI and I2S flag status \param[in] spi_periph: SPIx(x=0,1,2) \param[in] flag: SPI/I2S flag status one or more parameters can be selected which are shown as below: \arg SPI_FLAG_TBE: transmit buffer empty flag \arg SPI_FLAG_RBNE: receive buffer not empty flag \arg SPI_FLAG_TRANS: transmit on-going flag \arg SPI_FLAG_RXORERR: receive overrun error flag \arg SPI_FLAG_CONFERR: mode config error flag \arg SPI_FLAG_CRCERR: CRC error flag \arg SPI_FLAG_FERR: format error interrupt flag \arg I2S_FLAG_TBE: transmit buffer empty flag \arg I2S_FLAG_RBNE: receive buffer not empty flag \arg I2S_FLAG_TRANS: transmit on-going flag \arg I2S_FLAG_RXORERR: overrun error flag \arg I2S_FLAG_TXURERR: underrun error flag \arg I2S_FLAG_CH: channel side flag \arg I2S_FLAG_FERR: format error interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) { if (RESET != (SPI_STAT(spi_periph) & flag)) { return SET; } else { return RESET; } } /*! \brief clear SPI CRC error flag status \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_crc_error_clear(uint32_t spi_periph) { SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_timer.c ================================================ /*! \file gd32vf103_timer.c \brief TIMER driver \version 2019-06-05, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_timer.h" #include "gd32vf103_rcu.h" /* TIMER init parameter mask */ #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ #define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ /*! \brief deinit a timer \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_deinit(uint32_t timer_periph) { switch (timer_periph) { case TIMER0: /* reset TIMER0 */ rcu_periph_reset_enable(RCU_TIMER0RST); rcu_periph_reset_disable(RCU_TIMER0RST); break; case TIMER1: /* reset TIMER1 */ rcu_periph_reset_enable(RCU_TIMER1RST); rcu_periph_reset_disable(RCU_TIMER1RST); break; case TIMER2: /* reset TIMER2 */ rcu_periph_reset_enable(RCU_TIMER2RST); rcu_periph_reset_disable(RCU_TIMER2RST); break; case TIMER3: /* reset TIMER3 */ rcu_periph_reset_enable(RCU_TIMER3RST); rcu_periph_reset_disable(RCU_TIMER3RST); break; case TIMER4: /* reset TIMER4 */ rcu_periph_reset_enable(RCU_TIMER4RST); rcu_periph_reset_disable(RCU_TIMER4RST); break; case TIMER5: /* reset TIMER5 */ rcu_periph_reset_enable(RCU_TIMER5RST); rcu_periph_reset_disable(RCU_TIMER5RST); break; case TIMER6: /* reset TIMER6 */ rcu_periph_reset_enable(RCU_TIMER6RST); rcu_periph_reset_disable(RCU_TIMER6RST); break; default: break; } } /*! \brief initialize TIMER init parameter struct with a default value \param[in] initpara: init parameter struct \param[out] none \retval none */ void timer_struct_para_init(timer_parameter_struct *initpara) { /* initialize the init parameter struct member with the default value */ initpara->prescaler = 0U; initpara->alignedmode = TIMER_COUNTER_EDGE; initpara->counterdirection = TIMER_COUNTER_UP; initpara->period = 65535U; initpara->clockdivision = TIMER_CKDIV_DIV1; initpara->repetitioncounter = 0U; } /*! \brief initialize TIMER counter \param[in] timer_periph: TIMERx(x=0..6) \param[in] initpara: init parameter struct prescaler: prescaler value of the counter clock, 0~65535 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN period: counter auto reload value, 0~65535 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 repetitioncounter: counter repetition value, 0~255 \param[out] none \retval none */ void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) { /* configure the counter prescaler value */ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if ((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || (TIMER4 == timer_periph)) { TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); } else { TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_DIR); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); } /* configure the autoreload value */ TIMER_CAR(timer_periph) = (uint32_t)initpara->period; if ((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); } if (TIMER0 == timer_periph) { /* configure the repetition counter value */ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } /* generate an update event */ TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } /*! \brief enable a timer \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; } /*! \brief disable a timer \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; } /*! \brief enable the auto reload shadow function \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_auto_reload_shadow_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; } /*! \brief disable the auto reload shadow function \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_auto_reload_shadow_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; } /*! \brief enable the update event \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_update_event_enable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; } /*! \brief disable the update event \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval none */ void timer_update_event_disable(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPDIS; } /*! \brief set TIMER counter alignment mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] aligned: only one parameter can be selected which is shown as below: \arg TIMER_COUNTER_EDGE: edge-aligned mode \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode \param[out] none \retval none */ void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) { TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); TIMER_CTL0(timer_periph) |= (uint32_t)aligned; } /*! \brief set TIMER counter up direction \param[in] timer_periph: TIMERx(x=0..4) \param[out] none \retval none */ void timer_counter_up_direction(uint32_t timer_periph) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; } /*! \brief set TIMER counter down direction \param[in] timer_periph: TIMERx(x=0..4) \param[out] none \retval none */ void timer_counter_down_direction(uint32_t timer_periph) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; } /*! \brief configure TIMER prescaler \param[in] timer_periph: TIMERx(x=0..6) \param[in] prescaler: prescaler value \param[in] pscreload: prescaler reload mode only one parameter can be selected which is shown as below: \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event \param[out] none \retval none */ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) { TIMER_PSC(timer_periph) = (uint32_t)prescaler; if (TIMER_PSC_RELOAD_NOW == pscreload) { TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } /*! \brief configure TIMER repetition register value \param[in] timer_periph: TIMERx(x=0) \param[in] repetition: the counter repetition value, 0~255 \param[out] none \retval none */ void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { TIMER_CREP(timer_periph) = (uint32_t)repetition; } /*! \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..6) \param[in] autoreload: the counter auto-reload value \param[out] none \retval none */ void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; } /*! \brief configure TIMER counter register value \param[in] timer_periph: TIMERx(x=0..6) \param[in] counter: the counter value \param[out] none \retval none */ void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; } /*! \brief read TIMER counter value \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval counter value */ uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; count_value = TIMER_CNT(timer_periph); return (count_value); } /*! \brief read TIMER prescaler value \param[in] timer_periph: TIMERx(x=0..6) \param[out] none \retval prescaler register value */ uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); return (prescaler_value); } /*! \brief configure TIMER single pulse mode \param[in] timer_periph: TIMERx(x=0..6) \param[in] spmode: only one parameter can be selected which is shown as below: \arg TIMER_SP_MODE_SINGLE: single pulse mode \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode \param[out] none \retval none */ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { if (TIMER_SP_MODE_SINGLE == spmode) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; } else if (TIMER_SP_MODE_REPETITIVE == spmode) { TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); } else { /* illegal parameters */ } } /*! \brief configure TIMER update source \param[in] timer_periph: TIMERx(x=0..6) \param[in] update: only one parameter can be selected which is shown as below: \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, or the slave mode controller trigger \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow \param[out] none \retval none */ void timer_update_source_config(uint32_t timer_periph, uint32_t update) { if (TIMER_UPDATE_SRC_REGULAR == update) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; } else if (TIMER_UPDATE_SRC_GLOBAL == update) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; } else { /* illegal parameters */ } } /*! \brief enable the TIMER DMA \param[in] timer_periph: TIMERx(x=0..6) \param[in] dma: specify which DMA to enable one or more parameters can be selected which are shown as below: \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4) \param[out] none \retval none */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { TIMER_DMAINTEN(timer_periph) |= (uint32_t)dma; } /*! \brief disable the TIMER DMA \param[in] timer_periph: TIMERxTIMERx(x=0..6) \param[in] dma: specify which DMA to disbale one or more parameters can be selected which are shown as below: \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7) \param[out] none \retval none */ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); } /*! \brief channel DMA request source selection \param[in] timer_periph: TIMERx(x=0..4) \param[in] dma_request: channel DMA request source selection only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs \param[out] none \retval none */ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) { if (TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; } else if (TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; } else { /* illegal parameters */ } } /*! \brief configure the TIMER DMA transfer \param[in] timer_periph: TIMERx(x=0..4) \param[in] dma_baseaddr: only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0) \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4) \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0) \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4) \param[in] dma_lenth: only one parameter can be selected which is shown as below: \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time \param[out] none \retval none */ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) { TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); } /*! \brief software generate events \param[in] timer_periph: TIMERx(x=0..4) \param[in] event: the timer software event generation sources one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6) \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4) \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4) \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4) \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0) \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4) \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0) \param[out] none \retval none */ void timer_event_software_generate(uint32_t timer_periph, uint16_t event) { TIMER_SWEVG(timer_periph) |= (uint32_t)event; } /*! \brief initialize TIMER break parameter struct with a default value \param[in] breakpara: TIMER break parameter struct \param[out] none \retval none */ void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) { /* initialize the break parameter struct member with the default value */ breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; breakpara->deadtime = 0U; breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; breakpara->protectmode = TIMER_CCHP_PROT_OFF; breakpara->breakstate = TIMER_BREAK_DISABLE; } /*! \brief configure TIMER break function \param[in] timer_periph: TIMERx(x=0) \param[in] breakpara: TIMER break parameter struct runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE deadtime: 0~255 breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE \param[out] none \retval none */ void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) { TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | ((uint32_t)(breakpara->ideloffstate)) | ((uint32_t)(breakpara->deadtime)) | ((uint32_t)(breakpara->breakpolarity)) | ((uint32_t)(breakpara->outputautostate)) | ((uint32_t)(breakpara->protectmode)) | ((uint32_t)(breakpara->breakstate))); } /*! \brief enable TIMER break function \param[in] timer_periph: TIMERx(x=0) \param[out] none \retval none */ void timer_break_enable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; } /*! \brief disable TIMER break function \param[in] timer_periph: TIMERx(x=0) \param[out] none \retval none */ void timer_break_disable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; } /*! \brief enable TIMER output automatic function \param[in] timer_periph: TIMERx(x=0) \param[out] none \retval none */ void timer_automatic_output_enable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; } /*! \brief disable TIMER output automatic function \param[in] timer_periph: TIMERx(x=0) \param[out] none \retval none */ void timer_automatic_output_disable(uint32_t timer_periph) { TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; } /*! \brief enable or disable TIMER primary output function \param[in] timer_periph: TIMERx(x=0) \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { if (ENABLE == newvalue) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; } else { TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); } } /*! \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0) \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { if (ENABLE == newvalue) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; } else { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); } } /*! \brief configure TIMER channel control shadow register update control \param[in] timer_periph: TIMERx(x=0) \param[in] ccuctl: channel control shadow register update control only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none */ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) { if (TIMER_UPDATECTL_CCU == ccuctl) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); } else if (TIMER_UPDATECTL_CCUTRI == ccuctl) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; } else { /* illegal parameters */ } } /*! \brief initialize TIMER channel output parameter struct with a default value \param[in] ocpara: TIMER channel n output parameter struct \param[out] none \retval none */ void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) { /* initialize the channel output parameter struct member with the default value */ ocpara->outputstate = TIMER_CCX_DISABLE; ocpara->outputnstate = TIMER_CCXN_DISABLE; ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; } /*! \brief configure TIMER channel output function \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] ocpara: TIMER channeln output parameter struct outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH \param[out] none \retval none */ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; /* reset the CH0P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); /* set the CH0P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; if (TIMER0 == timer_periph) { /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; /* reset the CH0NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); /* set the CH0NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; /* reset the ISO0 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); /* set the ISO0 bit */ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; /* reset the ISO0N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); /* set the ISO0N bit */ TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; } TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); /* reset the CH1P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); /* set the CH1P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); if (TIMER0 == timer_periph) { /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); /* set the CH1NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); /* reset the ISO1 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); /* set the ISO1 bit */ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); /* reset the ISO1N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); /* set the ISO1N bit */ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); } TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; break; /* configure TIMER_CH_2 */ case TIMER_CH_2: /* reset the CH2EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); /* set the CH2EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); /* reset the CH2P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); /* set the CH2P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); if (TIMER0 == timer_periph) { /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); /* reset the CH2NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); /* set the CH2NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); /* reset the ISO2 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); /* set the ISO2 bit */ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); /* reset the ISO2N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); /* set the ISO2N bit */ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); } TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); /* reset the CH3P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); /* set the CH3P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); if (TIMER0 == timer_periph) { /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); } TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; break; default: break; } } /*! \brief configure TIMER channel output compare mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] ocmode: channel output compare mode only one parameter can be selected which is shown as below: \arg TIMER_OC_MODE_TIMING: timing mode \arg TIMER_OC_MODE_ACTIVE: active mode \arg TIMER_OC_MODE_INACTIVE: inactive mode \arg TIMER_OC_MODE_TOGGLE: toggle mode \arg TIMER_OC_MODE_LOW: force low mode \arg TIMER_OC_MODE_HIGH: force high mode \arg TIMER_OC_MODE_PWM0: PWM mode 0 \arg TIMER_OC_MODE_PWM1: PWM mode 1 \param[out] none \retval none */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; default: break; } } /*! \brief configure TIMER channel output pulse value \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] pulse: channel output pulse value \param[out] none \retval none */ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CH0CV(timer_periph) = (uint32_t)pulse; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CH1CV(timer_periph) = (uint32_t)pulse; break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CH2CV(timer_periph) = (uint32_t)pulse; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; } } /*! \brief configure TIMER channel output shadow function \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] ocshadow: channel output shadow state only one parameter can be selected which is shown as below: \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable \param[out] none \retval none */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); break; default: break; } } /*! \brief configure TIMER channel output fast function \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] ocfast: channel output fast function only one parameter can be selected which is shown as below: \arg TIMER_OC_FAST_ENABLE: channel output fast function enable \arg TIMER_OC_FAST_DISABLE: channel output fast function disable \param[out] none \retval none */ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); break; default: break; } } /*! \brief configure TIMER channel output clear function \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] occlear: channel output clear function only one parameter can be selected which is shown as below: \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable \param[out] none \retval none */ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); break; default: break; } } /*! \brief configure TIMER channel output polarity \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] ocpolarity: channel output polarity only one parameter can be selected which is shown as below: \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high \arg TIMER_OC_POLARITY_LOW: channel output polarity is low \param[out] none \retval none */ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); break; default: break; } } /*! \brief configure TIMER channel complementary output polarity \param[in] timer_periph: TIMERx(x=0) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0)) \param[in] ocnpolarity: channel complementary output polarity only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low \param[out] none \retval none */ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); break; default: break; } } /*! \brief configure TIMER channel enable state \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] state: TIMER channel enable state only one parameter can be selected which is shown as below: \arg TIMER_CCX_ENABLE: channel enable \arg TIMER_CCX_DISABLE: channel disable \param[out] none \retval none */ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); TIMER_CHCTL2(timer_periph) |= (uint32_t)state; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); break; default: break; } } /*! \brief configure TIMER channel complementary output enable state \param[in] timer_periph: TIMERx(x=0) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0 \arg TIMER_CH_1: TIMER channel 1 \arg TIMER_CH_2: TIMER channel 2 \param[in] ocnstate: TIMER channel complementary output enable state only one parameter can be selected which is shown as below: \arg TIMER_CCXN_ENABLE: channel complementary enable \arg TIMER_CCXN_DISABLE: channel complementary disable \param[out] none \retval none */ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); break; default: break; } } /*! \brief initialize TIMER channel input parameter struct with a default value \param[in] icpara: TIMER channel intput parameter struct \param[out] none \retval none */ void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) { /* initialize the channel input parameter struct member with the default value */ icpara->icpolarity = TIMER_IC_POLARITY_RISING; icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; icpara->icprescaler = TIMER_IC_PSC_DIV1; icpara->icfilter = 0U; } /*! \brief configure TIMER input capture parameter \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] icpara: TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8 icfilter: 0~15 \param[out] none \retval none */ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; break; /* configure TIMER_CH_2 */ case TIMER_CH_2: /* reset the CH2EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); /* reset the CH2P and CH2NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); /* reset the CH2MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); /* reset the CH2CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); /* set the CH2EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); /* reset the CH3P bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); /* reset the CH3MS bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); /* reset the CH3CAPFLT bit */ TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; break; default: break; } /* configure TIMER channel input capture prescaler value */ timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); } /*! \brief configure TIMER channel input capture prescaler value \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[in] prescaler: channel input capture prescaler value only one parameter can be selected which is shown as below: \arg TIMER_IC_PSC_DIV1: no prescaler \arg TIMER_IC_PSC_DIV2: divided by 2 \arg TIMER_IC_PSC_DIV4: divided by 4 \arg TIMER_IC_PSC_DIV8: divided by 8 \param[out] none \retval none */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { switch (channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; break; /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); break; default: break; } } /*! \brief read TIMER channel capture compare register value \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) \param[out] none \retval channel capture compare register value */ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) { uint32_t count_value = 0U; switch (channel) { case TIMER_CH_0: /* read TIMER channel 0 capture compare register value */ count_value = TIMER_CH0CV(timer_periph); break; case TIMER_CH_1: /* read TIMER channel 1 capture compare register value */ count_value = TIMER_CH1CV(timer_periph); break; case TIMER_CH_2: /* read TIMER channel 2 capture compare register value */ count_value = TIMER_CH2CV(timer_periph); break; case TIMER_CH_3: /* read TIMER channel 3 capture compare register value */ count_value = TIMER_CH3CV(timer_periph); break; default: break; } return (count_value); } /*! \brief configure TIMER input pwm capture function \param[in] timer_periph: TIMERx(x=0..4) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0 \arg TIMER_CH_1: TIMER channel 1 \param[in] icpwm: TIMER channel intput pwm parameter struct icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8 icfilter: 0~15 \param[out] none \retval none */ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; /* Set channel input polarity */ if (TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { icpolarity = TIMER_IC_POLARITY_FALLING; } else { icpolarity = TIMER_IC_POLARITY_RISING; } /* Set channel input mode selection */ if (TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { icselection = TIMER_IC_SELECTION_INDIRECTTI; } else { icselection = TIMER_IC_SELECTION_DIRECTTI; } if (TIMER_CH_0 == channel) { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); } else { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* set the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); } } /*! \brief configure TIMER hall sensor mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] hallmode: only one parameter can be selected which is shown as below: \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable \param[out] none \retval none */ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { if (TIMER_HALLINTERFACE_ENABLE == hallmode) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; } else if (TIMER_HALLINTERFACE_DISABLE == hallmode) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; } else { /* illegal parameters */ } } /*! \brief select TIMER input trigger source \param[in] timer_periph: TIMERx(x=0..4) \param[in] intrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4)) \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4)) \param[out] none \retval none */ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; } /*! \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..6) \param[in] outrigger: only one parameter can be selected which is shown as below: \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6)) \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6)) \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6)) \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4)) \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4)) \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4)) \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4)) \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4)) \param[out] none \retval none */ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; } /*! \brief select TIMER slave mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] slavemode: only one parameter can be selected which is shown as below: \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable \arg TIMER_ENCODER_MODE0: encoder mode 0 \arg TIMER_ENCODER_MODE1: encoder mode 1 \arg TIMER_ENCODER_MODE2: encoder mode 2 \arg TIMER_SLAVE_MODE_RESTART: restart mode \arg TIMER_SLAVE_MODE_PAUSE: pause mode \arg TIMER_SLAVE_MODE_EVENT: event mode \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0 \param[out] none \retval none */ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; } /*! \brief configure TIMER master slave mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] masterslave: only one parameter can be selected which is shown as below: \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none */ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { if (TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; } else if (TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; } else { /* illegal parameters */ } } /*! \brief configure TIMER external trigger input \param[in] timer_periph: TIMERx(x=0..4) \param[in] extprescaler: only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); } /*! \brief configure TIMER quadrature decoder mode \param[in] timer_periph: TIMERx(x=0..4) \param[in] decomode: only one parameter can be selected which is shown as below: \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input \param[in] ic0polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge \param[in] ic1polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge \arg TIMER_IC_POLARITY_FALLING: capture falling edge \param[out] none \retval none */ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) { /* configure the quadrature decoder mode */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; /* configure input capture selection */ TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); /* configure channel input capture polarity */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); } /*! \brief configure TIMER internal clock mode \param[in] timer_periph: TIMERx(x=0..4) \param[out] none \retval none */ void timer_internal_clock_config(uint32_t timer_periph) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; } /*! \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4) \param[in] intrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 \param[out] none \retval none */ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) { timer_input_trigger_source_select(timer_periph, intrigger); TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; } /*! \brief configure TIMER the external trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4) \param[in] extrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: active low or falling edge active \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) { if (TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; } else { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); /* set the CH0MS bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); /* reset the CH0CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; } /* select TIMER input trigger source */ timer_input_trigger_source_select(timer_periph, extrigger); /* reset the SMC bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); /* set the SMC bit */ TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; } /*! \brief configure TIMER the external clock mode0 \param[in] timer_periph: TIMERx(x=0..4) \param[in] extprescaler: only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); /* reset the SMC bit,TRGS bit */ TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); /* set the SMC bit,TRGS bit */ TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); } /*! \brief configure TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4) \param[in] extprescaler: only one parameter can be selected which is shown as below: \arg TIMER_EXT_TRI_PSC_OFF: no divided \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; } /*! \brief disable TIMER the external clock mode1 \param[in] timer_periph: TIMERx(x=0..4) \param[out] none \retval none */ void timer_external_clock_mode1_disable(uint32_t timer_periph) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; } /*! \brief enable the TIMER interrupt \param[in] timer_periph: please refer to the following parameters \param[in] interrupt: specify which interrupt to enable one or more parameters can be selected which are shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) \param[out] none \retval none */ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { TIMER_DMAINTEN(timer_periph) |= (uint32_t)interrupt; } /*! \brief disable the TIMER interrupt \param[in] timer_periph: TIMERx(x=0..6) \param[in] interrupt: specify which interrupt to disbale one or more parameters can be selected which are shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4) \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) \param[out] none \retval none */ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); } /*! \brief get timer interrupt flag \param[in] timer_periph: TIMERx(x=0..6) \param[in] interrupt: the timer interrupt bits only one parameter can be selected which is shown as below: \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0) \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) { uint32_t val; val = (TIMER_DMAINTEN(timer_periph) & interrupt); if ((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { return SET; } else { return RESET; } } /*! \brief clear TIMER interrupt flag \param[in] timer_periph: TIMERx(x=0..6) \param[in] interrupt: the timer interrupt bits one or more parameters can be selected which are shown as below: \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..4) \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) \param[out] none \retval none */ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) { TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); } /*! \brief get TIMER flags \param[in] timer_periph: TIMERx(x=0..6) \param[in] flag: the timer interrupt flags only one parameter can be selected which is shown as below: \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4) \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) { if (RESET != (TIMER_INTF(timer_periph) & flag)) { return SET; } else { return RESET; } } /*! \brief clear TIMER flags \param[in] timer_periph: TIMERx(x=0..6) \param[in] flag: the timer interrupt flags one or more parameters can be selected which are shown as below: \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4) \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) \param[out] none \retval none */ void timer_flag_clear(uint32_t timer_periph, uint32_t flag) { TIMER_INTF(timer_periph) = (~(uint32_t)flag); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_usart.c ================================================ /*! \file gd32vf103_usart.c \brief USART driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2019-09-18, V1.0.1, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_usart.h" #include "gd32vf103_rcu.h" /*! \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_deinit(uint32_t usart_periph) { switch (usart_periph) { case USART0: /* reset USART0 */ rcu_periph_reset_enable(RCU_USART0RST); rcu_periph_reset_disable(RCU_USART0RST); break; case USART1: /* reset USART1 */ rcu_periph_reset_enable(RCU_USART1RST); rcu_periph_reset_disable(RCU_USART1RST); break; case USART2: /* reset USART2 */ rcu_periph_reset_enable(RCU_USART2RST); rcu_periph_reset_disable(RCU_USART2RST); break; case UART3: /* reset UART3 */ rcu_periph_reset_enable(RCU_UART3RST); rcu_periph_reset_disable(RCU_UART3RST); break; case UART4: /* reset UART4 */ rcu_periph_reset_enable(RCU_UART4RST); rcu_periph_reset_disable(RCU_UART4RST); break; default: break; } } /*! \brief configure USART baud rate value \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] baudval: baud rate value \param[out] none \retval none */ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; switch (usart_periph) { /* get clock frequency */ case USART0: /* get USART0 clock */ uclk = rcu_clock_freq_get(CK_APB2); break; case USART1: /* get USART1 clock */ uclk = rcu_clock_freq_get(CK_APB1); break; case USART2: /* get USART2 clock */ uclk = rcu_clock_freq_get(CK_APB1); break; case UART3: /* get UART3 clock */ uclk = rcu_clock_freq_get(CK_APB1); break; case UART4: /* get UART4 clock */ uclk = rcu_clock_freq_get(CK_APB1); break; default: break; } /* oversampling by 16, configure the value of USART_BAUD */ udiv = (uclk + baudval / 2U) / baudval; intdiv = udiv & (0x0000fff0U); fradiv = udiv & (0x0000000fU); USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); } /*! \brief configure USART parity \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] paritycfg: configure USART parity only one parameter can be selected which is shown as below: \arg USART_PM_NONE: no parity \arg USART_PM_ODD: odd parity \arg USART_PM_EVEN: even parity \param[out] none \retval none */ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) { /* clear USART_CTL0 PM,PCEN bits */ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); /* configure USART parity mode */ USART_CTL0(usart_periph) |= paritycfg; } /*! \brief configure USART word length \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] wlen: USART word length configure only one parameter can be selected which is shown as below: \arg USART_WL_8BIT: 8 bits \arg USART_WL_9BIT: 9 bits \param[out] none \retval none */ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) { /* clear USART_CTL0 WL bit */ USART_CTL0(usart_periph) &= ~USART_CTL0_WL; /* configure USART word length */ USART_CTL0(usart_periph) |= wlen; } /*! \brief configure USART stop bit length \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] stblen: USART stop bit configure only one parameter can be selected which is shown as below: \arg USART_STB_1BIT: 1 bit \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) \arg USART_STB_2BIT: 2 bits \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) \param[out] none \retval none */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ USART_CTL1(usart_periph) &= ~USART_CTL1_STB; /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } /*! \brief enable USART \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_enable(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_UEN; } /*! \brief disable USART \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_disable(uint32_t usart_periph) { USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); } /*! \brief configure USART transmitter \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] txconfig: enable or disable USART transmitter only one parameter can be selected which is shown as below: \arg USART_TRANSMIT_ENABLE: enable USART transmission \arg USART_TRANSMIT_DISABLE: disable USART transmission \param[out] none \retval none */ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { uint32_t ctl = 0U; ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_TEN; ctl |= txconfig; /* configure transfer mode */ USART_CTL0(usart_periph) = ctl; } /*! \brief configure USART receiver \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] rxconfig: enable or disable USART receiver only one parameter can be selected which is shown as below: \arg USART_RECEIVE_ENABLE: enable USART reception \arg USART_RECEIVE_DISABLE: disable USART reception \param[out] none \retval none */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { uint32_t ctl = 0U; ctl = USART_CTL0(usart_periph); ctl &= ~USART_CTL0_REN; ctl |= rxconfig; /* configure receiver mode */ USART_CTL0(usart_periph) = ctl; } /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] data: data of transmission \param[out] none \retval none */ void usart_data_transmit(uint32_t usart_periph, uint32_t data) { USART_DATA(usart_periph) = USART_DATA_DATA & data; } /*! \brief USART receive data function \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval data of received */ uint16_t usart_data_receive(uint32_t usart_periph) { return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); } /*! \brief configure the address of the USART in wake up by address match mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] addr: address of USART/UART \param[out] none \retval none */ void usart_address_config(uint32_t usart_periph, uint8_t addr) { USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); } /*! \brief receiver in mute mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_mute_mode_enable(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_RWU; } /*! \brief receiver in active mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_mute_mode_disable(uint32_t usart_periph) { USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); } /*! \brief configure wakeup method in mute mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] wmethod: two methods be used to enter or exit the mute mode only one parameter can be selected which is shown as below: \arg USART_WM_IDLE: idle line \arg USART_WM_ADDR: address mask \param[out] none \retval none */ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) { USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); USART_CTL0(usart_periph) |= wmethod; } /*! \brief enable LIN mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) { USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } /*! \brief disable LIN mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) { USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } /*! \brief configure lin break frame length \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] lblen: lin break frame length only one parameter can be selected which is shown as below: \arg USART_LBLEN_10B: 10 bits \arg USART_LBLEN_11B: 11 bits \param[out] none \retval none */ void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) { USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); } /*! \brief send break frame \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_send_break(uint32_t usart_periph) { USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; } /*! \brief enable half duplex mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } /*! \brief disable half duplex mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); } /*! \brief enable CK pin in synchronous mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_synchronous_clock_enable(uint32_t usart_periph) { USART_CTL1(usart_periph) |= USART_CTL1_CKEN; } /*! \brief disable CK pin in synchronous mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_synchronous_clock_disable(uint32_t usart_periph) { USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); } /*! \brief configure USART synchronous mode parameters \param[in] usart_periph: USARTx(x=0,1,2) \param[in] clen: CK length only one parameter can be selected which is shown as below: \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase only one parameter can be selected which is shown as below: \arg USART_CPH_1CK: first clock transition is the first data capture edge \arg USART_CPH_2CK: second clock transition is the first data capture edge \param[in] cpl: clock polarity only one parameter can be selected which is shown as below: \arg USART_CPL_LOW: steady low value on CK pin \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { uint32_t ctl = 0U; /* read USART_CTL1 register */ ctl = USART_CTL1(usart_periph); ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); /* set CK length, CK phase, CK polarity */ ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); USART_CTL1(usart_periph) = ctl; } /*! \brief configure guard time value in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2) \param[in] gaut: guard time value \param[out] none \retval none */ void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut) << 8)); } /*! \brief enable smartcard mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_smartcard_mode_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_SCEN; } /*! \brief disable smartcard mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_smartcard_mode_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); } /*! \brief enable NACK in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_smartcard_mode_nack_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_NKEN; } /*! \brief disable NACK in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2) \param[out] none \retval none */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); } /*! \brief enable IrDA mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_irda_mode_enable(uint32_t usart_periph) { USART_CTL2(usart_periph) |= USART_CTL2_IREN; } /*! \brief disable IrDA mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[out] none \retval none */ void usart_irda_mode_disable(uint32_t usart_periph) { USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); } /*! \brief configure the peripheral clock prescaler in USART IrDA low-power mode \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] psc: 0x00-0xFF \param[out] none \retval none */ void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) { USART_GP(usart_periph) &= ~(USART_GP_PSC); USART_GP(usart_periph) |= psc; } /*! \brief configure IrDA low-power \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] irlp: IrDA low-power or normal only one parameter can be selected which is shown as below: \arg USART_IRLP_LOW: low-power \arg USART_IRLP_NORMAL: normal \param[out] none \retval none */ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) { USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); } /*! \brief configure hardware flow control RTS \param[in] usart_periph: USARTx(x=0,1,2) \param[in] rtsconfig: enable or disable RTS only one parameter can be selected which is shown as below: \arg USART_RTS_ENABLE: enable RTS \arg USART_RTS_DISABLE: disable RTS \param[out] none \retval none */ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) { uint32_t ctl = 0U; ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_RTSEN; ctl |= rtsconfig; /* configure RTS */ USART_CTL2(usart_periph) = ctl; } /*! \brief configure hardware flow control CTS \param[in] usart_periph: USARTx(x=0,1,2) \param[in] ctsconfig: enable or disable CTS only one parameter can be selected which is shown as below: \arg USART_CTS_ENABLE: enable CTS \arg USART_CTS_DISABLE: disable CTS \param[out] none \retval none */ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) { uint32_t ctl = 0U; ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_CTSEN; ctl |= ctsconfig; /* configure CTS */ USART_CTL2(usart_periph) = ctl; } /*! \brief configure USART DMA reception \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) \param[in] dmacmd: enable or disable DMA for reception only one parameter can be selected which is shown as below: \arg USART_DENR_ENABLE: DMA enable for reception \arg USART_DENR_DISABLE: DMA disable for reception \param[out] none \retval none */ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) { uint32_t ctl = 0U; ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_DENR; ctl |= dmacmd; /* configure DMA reception */ USART_CTL2(usart_periph) = ctl; } /*! \brief configure USART DMA transmission \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) \param[in] dmacmd: enable or disable DMA for transmission only one parameter can be selected which is shown as below: \arg USART_DENT_ENABLE: DMA enable for transmission \arg USART_DENT_DISABLE: DMA disable for transmission \param[out] none \retval none */ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) { uint32_t ctl = 0U; ctl = USART_CTL2(usart_periph); ctl &= ~USART_CTL2_DENT; ctl |= dmacmd; /* configure DMA transmission */ USART_CTL2(usart_periph) = ctl; } /*! \brief get flag in STAT register \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] flag: USART flags, refer to usart_flag_enum only one parameter can be selected which is shown as below: \arg USART_FLAG_CTS: CTS change flag \arg USART_FLAG_LBD: LIN break detected flag \arg USART_FLAG_TBE: transmit data buffer empty \arg USART_FLAG_TC: transmission complete \arg USART_FLAG_RBNE: read data buffer not empty \arg USART_FLAG_IDLE: IDLE frame detected flag \arg USART_FLAG_ORERR: overrun error \arg USART_FLAG_NERR: noise error flag \arg USART_FLAG_FERR: frame error flag \arg USART_FLAG_PERR: parity error flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) { if (RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { return SET; } else { return RESET; } } /*! \brief clear flag in STAT register \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] flag: USART flags, refer to usart_flag_enum only one parameter can be selected which is shown as below: \arg USART_FLAG_CTS: CTS change flag \arg USART_FLAG_LBD: LIN break detected flag \arg USART_FLAG_TC: transmission complete \arg USART_FLAG_RBNE: read data buffer not empty \param[out] none \retval none */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) { USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); } /*! \brief enable USART interrupt \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] interrupt only one parameter can be selected which is shown as below: \arg USART_INT_PERR: parity error interrupt \arg USART_INT_TBE: transmitter buffer empty interrupt \arg USART_INT_TC: transmission complete interrupt \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt \arg USART_INT_IDLE: IDLE line detected interrupt \arg USART_INT_LBD: LIN break detected interrupt \arg USART_INT_ERR: error interrupt \arg USART_INT_CTS: CTS interrupt \param[out] none \retval none */ void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt) { USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); } /*! \brief disable USART interrupt \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] interrupt only one parameter can be selected which is shown as below: \arg USART_INT_PERR: parity error interrupt \arg USART_INT_TBE: transmitter buffer empty interrupt \arg USART_INT_TC: transmission complete interrupt \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt \arg USART_INT_IDLE: IDLE line detected interrupt \arg USART_INT_LBD: LIN break detected interrupt \arg USART_INT_ERR: error interrupt \arg USART_INT_CTS: CTS interrupt \param[out] none \retval none */ void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt) { USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); } /*! \brief get USART interrupt and flag status \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] int_flag only one parameter can be selected which is shown as below: \arg USART_INT_FLAG_PERR: parity error interrupt and flag \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag \arg USART_INT_FLAG_TC: transmission complete interrupt and flag \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag \arg USART_INT_FLAG_CTS: CTS interrupt and flag \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) { uint32_t intenable = 0U, flagstatus = 0U; /* get the interrupt enable bit status */ intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); /* get the corresponding flag bit status */ flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); if (flagstatus && intenable) { return SET; } else { return RESET; } } /*! \brief clear USART interrupt flag in STAT register \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) \param[in] int_flag: USART interrupt flag only one parameter can be selected which is shown as below: \arg USART_INT_FLAG_CTS: CTS change flag \arg USART_INT_FLAG_LBD: LIN break detected flag \arg USART_INT_FLAG_TC: transmission complete \arg USART_INT_FLAG_RBNE: read data buffer not empty \param[out] none \retval none */ void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag) { USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag)); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/gd32vf103_wwdgt.c ================================================ /*! \file gd32vf103_wwdgt.c \brief WWDGT driver \version 2019-06-05, V1.0.0, firmware for GD32VF103 \version 2020-08-04, V1.1.0, firmware for GD32VF103 */ /* Copyright (c) 2020, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32vf103_wwdgt.h" #include "gd32vf103_rcu.h" /* write value to WWDGT_CTL_CNT bit field */ #define CTL_CNT(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0)) /* write value to WWDGT_CFG_WIN bit field */ #define CFG_WIN(regval) (BITS(0, 6) & ((uint32_t)(regval) << 0)) /*! \brief reset the window watchdog timer configuration \param[in] none \param[out] none \retval none */ void wwdgt_deinit(void) { rcu_periph_reset_enable(RCU_WWDGTRST); rcu_periph_reset_disable(RCU_WWDGTRST); } /*! \brief start the window watchdog timer counter \param[in] none \param[out] none \retval none */ void wwdgt_enable(void) { WWDGT_CTL |= WWDGT_CTL_WDGTEN; } /*! \brief configure the window watchdog timer counter value \param[in] counter_value: 0x00 - 0x7F \param[out] none \retval none */ void wwdgt_counter_update(uint16_t counter_value) { uint32_t reg = 0U; reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); reg |= CTL_CNT(counter_value); WWDGT_CTL = reg; } /*! \brief configure counter value, window value, and prescaler divider value \param[in] counter: 0x00 - 0x7F \param[in] window: 0x00 - 0x7F \param[in] prescaler: wwdgt prescaler value only one parameter can be selected which is shown as below: \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 \param[out] none \retval none */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) { uint32_t reg_cfg = 0U, reg_ctl = 0U; /* clear WIN and PSC bits, clear CNT bit */ reg_cfg = (WWDGT_CFG & (~(WWDGT_CFG_WIN | WWDGT_CFG_PSC))); reg_ctl = (WWDGT_CTL & (~WWDGT_CTL_CNT)); /* configure WIN and PSC bits, configure CNT bit */ reg_cfg |= CFG_WIN(window); reg_cfg |= prescaler; reg_ctl |= CTL_CNT(counter); WWDGT_CTL = reg_ctl; WWDGT_CFG = reg_cfg; } /*! \brief enable early wakeup interrupt of WWDGT \param[in] none \param[out] none \retval none */ void wwdgt_interrupt_enable(void) { WWDGT_CFG |= WWDGT_CFG_EWIE; } /*! \brief check early wakeup interrupt state of WWDGT \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus wwdgt_flag_get(void) { if (WWDGT_STAT & WWDGT_STAT_EWIF) { return SET; } return RESET; } /*! \brief clear early wakeup interrupt state of WWDGT \param[in] none \param[out] none \retval none */ void wwdgt_flag_clear(void) { WWDGT_STAT &= (~WWDGT_STAT_EWIF); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Drivers/n200_func.c ================================================ /* See LICENSE for license details. */ #include #include #include #include #if defined(__ICCRISCV__) #include "compiler.h" #elif defined(__GNUC__) #include #endif #include "gd32vf103_rcu.h" #include "n200_func.h" #include "riscv_encoding.h" /* Configure PMP to make all the address space accesable and executable */ void pmp_open_all_space(void) { /* Config entry0 addr to all 1s to make the range cover all space */ asm volatile("li x6, 0xffffffff" ::: "x6"); asm volatile("csrw pmpaddr0, x6" :::); /* Config entry0 cfg to make it NAPOT address mode, and R/W/X okay */ asm volatile("li x6, 0x7f" ::: "x6"); asm volatile("csrw pmpcfg0, x6" :::); } void switch_m2u_mode(void) { clear_csr(mstatus, MSTATUS_MPP); /* printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus)); */ /* printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc)); */ #if defined(__GNUC__) asm volatile("la x6, 1f " ::: "x6"); #endif asm volatile("csrw mepc, x6" :::); asm volatile("mret" :::); asm volatile("1:" :::); } uint32_t mtime_lo(void) { return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME); } uint32_t mtime_hi(void) { return *(volatile uint32_t *)(TIMER_CTRL_ADDR + TIMER_MTIME + 4); } uint64_t get_timer_value(void) { while (1) { uint32_t hi = mtime_hi(); uint32_t lo = mtime_lo(); if (hi == mtime_hi()) { return ((uint64_t)hi << 32) | lo; } } } uint32_t get_timer_freq(void) { return TIMER_FREQ; } uint64_t get_instret_value(void) { while (1) { #if defined(__ICCRISCV__) uint32_t hi = read_csr(CSR_MINSTRETH); uint32_t lo = read_csr(CSR_MINSTRETH); if (hi == read_csr(CSR_MINSTRETH)) #elif defined(__GNUC__) uint32_t hi = read_csr(minstreth); uint32_t lo = read_csr(minstret); if (hi == read_csr(minstreth)) #endif return ((uint64_t)hi << 32) | lo; } } uint64_t get_cycle_value(void) { while (1) { #if defined(__ICCRISCV__) uint32_t hi = read_csr(CSR_MCYCLEH); uint32_t lo = read_csr(CSR_MCYCLE); if (hi == read_csr(CSR_MCYCLEH)) #elif defined(__GNUC__) uint32_t hi = read_csr(mcycleh); uint32_t lo = read_csr(mcycle); if (hi == read_csr(mcycleh)) #endif return ((uint64_t)hi << 32) | lo; } } /* Note that there are no assertions or bounds checking on these */ /* parameter values. */ void eclic_init(uint32_t num_irq) { typedef volatile uint32_t vuint32_t; /* clear cfg register */ *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = 0; /* clear minthresh register */ *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = 0; /* clear all IP/IE/ATTR/CTRL bits for all interrupt sources */ vuint32_t *ptr; vuint32_t *base = (vuint32_t *)(ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET); vuint32_t *upper = (vuint32_t *)(base + num_irq * 4); for (ptr = base; ptr < upper; ptr = ptr + 4) { *ptr = 0; } } void eclic_enable_interrupt(uint32_t source) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) = 1; } void eclic_disable_interrupt(uint32_t source) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) = 0; } void eclic_set_pending(uint32_t source) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) = 1; } void eclic_clear_pending(uint32_t source) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) = 0; } void eclic_set_intctrl(uint32_t source, uint8_t intctrl) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET + source * 4) = intctrl; } uint8_t eclic_get_intctrl(uint32_t source) { return *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET + source * 4); } void eclic_set_intattr(uint32_t source, uint8_t intattr) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET + source * 4) = intattr; } uint8_t eclic_get_intattr(uint32_t source) { return *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET + source * 4); } void eclic_set_cliccfg(uint8_t cliccfg) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = cliccfg; } uint8_t eclic_get_cliccfg(void) { return *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET); } void eclic_set_mth(uint8_t mth) { *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = mth; } uint8_t eclic_get_mth(void) { return *(volatile uint8_t *)(ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET); } /* sets nlbits */ void eclic_set_nlbits(uint8_t nlbits) { /* shift nlbits to correct position */ uint8_t nlbits_shifted = nlbits << ECLIC_CFG_NLBITS_LSB; /* read the current cliccfg */ uint8_t old_cliccfg = eclic_get_cliccfg(); uint8_t new_cliccfg = (old_cliccfg & (~ECLIC_CFG_NLBITS_MASK)) | (ECLIC_CFG_NLBITS_MASK & nlbits_shifted); eclic_set_cliccfg(new_cliccfg); } /* get nlbits */ uint8_t eclic_get_nlbits(void) { /* extract nlbits */ uint8_t nlbits = eclic_get_cliccfg(); nlbits = (nlbits & ECLIC_CFG_NLBITS_MASK) >> ECLIC_CFG_NLBITS_LSB; return nlbits; } /* sets an interrupt level based encoding of nlbits and ECLICINTCTLBITS */ void eclic_set_irq_lvl(uint32_t source, uint8_t lvl) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits > ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; } /* shift lvl right to mask off unused bits */ lvl = lvl >> (8 - nlbits); /* shift lvl into correct bit position */ lvl = lvl << (8 - nlbits); /* write to clicintctrl */ uint8_t current_intctrl = eclic_get_intctrl(source); /* shift intctrl left to mask off unused bits */ current_intctrl = current_intctrl << nlbits; /* shift intctrl into correct bit position */ current_intctrl = current_intctrl >> nlbits; eclic_set_intctrl(source, (current_intctrl | lvl)); } /* gets an interrupt level based encoding of nlbits */ uint8_t eclic_get_irq_lvl(uint32_t source) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits > ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; } uint8_t intctrl = eclic_get_intctrl(source); /* shift intctrl */ intctrl = intctrl >> (8 - nlbits); /* shift intctrl */ uint8_t lvl = intctrl << (8 - nlbits); return lvl; } void eclic_set_irq_lvl_abs(uint32_t source, uint8_t lvl_abs) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits > ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; } /* shift lvl_abs into correct bit position */ uint8_t lvl = lvl_abs << (8 - nlbits); /* write to clicintctrl */ uint8_t current_intctrl = eclic_get_intctrl(source); /* shift intctrl left to mask off unused bits */ current_intctrl = current_intctrl << nlbits; /* shift intctrl into correct bit position */ current_intctrl = current_intctrl >> nlbits; eclic_set_intctrl(source, (current_intctrl | lvl)); } uint8_t eclic_get_irq_lvl_abs(uint32_t source) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits > ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; } uint8_t intctrl = eclic_get_intctrl(source); /* shift intctrl */ intctrl = intctrl >> (8 - nlbits); /* shift intctrl */ uint8_t lvl_abs = intctrl; return lvl_abs; } /* sets an interrupt priority based encoding of nlbits and ECLICINTCTLBITS */ uint8_t eclic_set_irq_priority(uint32_t source, uint8_t priority) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits >= ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; return 0; } /* shift priority into correct bit position */ priority = priority << (8 - ECLICINTCTLBITS); /* write to eclicintctrl */ uint8_t current_intctrl = eclic_get_intctrl(source); /* shift intctrl right to mask off unused bits */ current_intctrl = current_intctrl >> (8 - nlbits); /* shift intctrl into correct bit position */ current_intctrl = current_intctrl << (8 - nlbits); eclic_set_intctrl(source, (current_intctrl | priority)); return priority; } /* gets an interrupt priority based encoding of nlbits */ uint8_t eclic_get_irq_priority(uint32_t source) { /* extract nlbits */ uint8_t nlbits = eclic_get_nlbits(); if (nlbits > ECLICINTCTLBITS) { nlbits = ECLICINTCTLBITS; } uint8_t intctrl = eclic_get_intctrl(source); /* shift intctrl */ intctrl = intctrl << nlbits; /* shift intctrl */ uint8_t priority = intctrl >> (nlbits + (8 - ECLICINTCTLBITS)); return priority; } void eclic_mode_enable() { #if defined(__ICCRISCV__) uint32_t mtvec_value = read_csr(CSR_MTVEC); mtvec_value = mtvec_value & 0xFFFFFFC0; mtvec_value = mtvec_value | 0x00000003; write_csr(CSR_MTVEC, mtvec_value); #elif defined(__GNUC__) uint32_t mtvec_value = read_csr(mtvec); mtvec_value = mtvec_value & 0xFFFFFFC0; mtvec_value = mtvec_value | 0x00000003; write_csr(mtvec, mtvec_value); #endif } /* sets vector-mode or non-vector mode */ void eclic_set_vmode(uint32_t source) { /* read the current attr */ uint8_t old_intattr = eclic_get_intattr(source); /* Keep other bits unchanged and only set the LSB bit */ uint8_t new_intattr = (old_intattr | 0x1); eclic_set_intattr(source, new_intattr); } void eclic_set_nonvmode(uint32_t source) { /* read the current attr */ uint8_t old_intattr = eclic_get_intattr(source); /* Keep other bits unchanged and only clear the LSB bit*/ uint8_t new_intattr = (old_intattr & (~0x1)); eclic_set_intattr(source, new_intattr); } /* sets interrupt as level sensitive Bit 1, trig[0], is defined as "edge-triggered" (0: level-triggered, 1: edge-triggered); Bit 2, trig[1], is defined as "negative-edge" (0: positive-edge, 1: negative-edge).*/ void eclic_set_level_trig(uint32_t source) { /* read the current attr */ uint8_t old_intattr = eclic_get_intattr(source); /* Keep other bits unchanged and only clear the bit 1 */ uint8_t new_intattr = (old_intattr & (~0x2)); eclic_set_intattr(source, new_intattr); } void eclic_set_posedge_trig(uint32_t source) { /* read the current attr */ uint8_t old_intattr = eclic_get_intattr(source); /* Keep other bits unchanged and only set the bit 1 */ uint8_t new_intattr = (old_intattr | 0x2); /* Keep other bits unchanged and only clear the bit 2 */ new_intattr = (old_intattr & (~0x4)); eclic_set_intattr(source, new_intattr); } void eclic_set_negedge_trig(uint32_t source) { /*read the current attr */ uint8_t old_intattr = eclic_get_intattr(source); /* Keep other bits unchanged and only set the bit 1*/ uint8_t new_intattr = (old_intattr | 0x2); /* Keep other bits unchanged and only set the bit 2*/ new_intattr = (old_intattr | 0x4); eclic_set_intattr(source, new_intattr); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/intexc_gd32vf103.S ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /****************************************************************************** * \file intexc_gd32vf103.S * \brief NMSIS Interrupt and Exception Handling Template File * for Device gd32vf103 * \version V1.00 * \date 7 Jan 2020 * ******************************************************************************/ #include "riscv_encoding.h" /** * \brief Global interrupt disabled * \details * This function disable global interrupt. * \remarks * - All the interrupt requests will be ignored by CPU. */ .macro DISABLE_MIE csrc CSR_MSTATUS, MSTATUS_MIE .endm /** * \brief Macro for context save * \details * This macro save ABI defined caller saved registers in the stack. * \remarks * - This Macro could use to save context when you enter to interrupt * or exception */ /* Save caller registers */ .macro SAVE_CONTEXT /* Allocate stack space for context saving */ #ifndef __riscv_32e addi sp, sp, -20*REGBYTES #else addi sp, sp, -14*REGBYTES #endif /* __riscv_32e */ STORE x1, 0*REGBYTES(sp) STORE x4, 1*REGBYTES(sp) STORE x5, 2*REGBYTES(sp) STORE x6, 3*REGBYTES(sp) STORE x7, 4*REGBYTES(sp) STORE x10, 5*REGBYTES(sp) STORE x11, 6*REGBYTES(sp) STORE x12, 7*REGBYTES(sp) STORE x13, 8*REGBYTES(sp) STORE x14, 9*REGBYTES(sp) STORE x15, 10*REGBYTES(sp) #ifndef __riscv_32e STORE x16, 14*REGBYTES(sp) STORE x17, 15*REGBYTES(sp) STORE x28, 16*REGBYTES(sp) STORE x29, 17*REGBYTES(sp) STORE x30, 18*REGBYTES(sp) STORE x31, 19*REGBYTES(sp) #endif /* __riscv_32e */ .endm /** * \brief Macro for restore caller registers * \details * This macro restore ABI defined caller saved registers from stack. * \remarks * - You could use this macro to restore context before you want return * from interrupt or exeception */ /* Restore caller registers */ .macro RESTORE_CONTEXT LOAD x1, 0*REGBYTES(sp) LOAD x4, 1*REGBYTES(sp) LOAD x5, 2*REGBYTES(sp) LOAD x6, 3*REGBYTES(sp) LOAD x7, 4*REGBYTES(sp) LOAD x10, 5*REGBYTES(sp) LOAD x11, 6*REGBYTES(sp) LOAD x12, 7*REGBYTES(sp) LOAD x13, 8*REGBYTES(sp) LOAD x14, 9*REGBYTES(sp) LOAD x15, 10*REGBYTES(sp) #ifndef __riscv_32e LOAD x16, 14*REGBYTES(sp) LOAD x17, 15*REGBYTES(sp) LOAD x28, 16*REGBYTES(sp) LOAD x29, 17*REGBYTES(sp) LOAD x30, 18*REGBYTES(sp) LOAD x31, 19*REGBYTES(sp) /* De-allocate the stack space */ addi sp, sp, 20*REGBYTES #else /* De-allocate the stack space */ addi sp, sp, 14*REGBYTES #endif /* __riscv_32e */ .endm /** * \brief Macro for save necessary CSRs to stack * \details * This macro store MCAUSE, MEPC, MSUBM to stack. */ .macro SAVE_CSR_CONTEXT /* Store CSR mcause to stack using pushmcause */ csrrwi x0, CSR_PUSHMCAUSE, 11 /* Store CSR mepc to stack using pushmepc */ csrrwi x0, CSR_PUSHMEPC, 12 /* Store CSR msub to stack using pushmsub */ csrrwi x0, CSR_PUSHMSUBM, 13 .endm /** * \brief Macro for restore necessary CSRs from stack * \details * This macro restore MSUBM, MEPC, MCAUSE from stack. */ .macro RESTORE_CSR_CONTEXT LOAD x5, 13*REGBYTES(sp) csrw CSR_MSUBM, x5 LOAD x5, 12*REGBYTES(sp) csrw CSR_MEPC, x5 LOAD x5, 11*REGBYTES(sp) csrw CSR_MCAUSE, x5 .endm /** * \brief Exception/NMI Entry * \details * This function provide common entry functions for exception/nmi. * \remarks * This function provide a default exception/nmi entry. * ABI defined caller save register and some CSR registers * to be saved before enter interrupt handler and be restored before return. */ .section .text.trap /* In CLIC mode, the exeception entry must be 64bytes aligned */ .align 6 .global exc_entry .weak exc_entry exc_entry: /* Save the caller saving registers (context) */ SAVE_CONTEXT /* Save the necessary CSR registers */ SAVE_CSR_CONTEXT /* * Set the exception handler function arguments * argument 1: mcause value * argument 2: current stack point(SP) value */ csrr a0, mcause mv a1, sp /* * TODO: Call the exception handler function * By default, the function template is provided in * system_Device.c, you can adjust it as you want */ call core_exception_handler /* Restore the necessary CSR registers */ RESTORE_CSR_CONTEXT /* Restore the caller saving registers (context) */ RESTORE_CONTEXT /* Return to regular code */ mret /** * \brief Non-Vector Interrupt Entry * \details * This function provide common entry functions for handling * non-vector interrupts * \remarks * This function provide a default non-vector interrupt entry. * ABI defined caller save register and some CSR registers need * to be saved before enter interrupt handler and be restored before return. */ .section .text.irq /* In CLIC mode, the interrupt entry must be 4bytes aligned */ .align 2 .global irq_entry .weak irq_entry /* This label will be set to MTVT2 register */ irq_entry: /* Save the caller saving registers (context) */ SAVE_CONTEXT /* Save the necessary CSR registers */ SAVE_CSR_CONTEXT /* This special CSR read/write operation, which is actually * claim the CLIC to find its pending highest ID, if the ID * is not 0, then automatically enable the mstatus.MIE, and * jump to its vector-entry-label, and update the link register */ csrrw ra, CSR_JALMNXTI, ra /* Critical section with interrupts disabled */ DISABLE_MIE /* Restore the necessary CSR registers */ RESTORE_CSR_CONTEXT /* Restore the caller saving registers (context) */ RESTORE_CONTEXT /* Return to regular code */ mret /* Default Handler for Exceptions / Interrupts */ .global default_intexc_handler .weak default_intexc_handler Undef_Handler: default_intexc_handler: 1: j 1b ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/GCC/startup_gd32vf103.S ================================================ /* * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /****************************************************************************** * \file startup_gd32vf103.S * \brief NMSIS Nuclei N/NX Class Core based Core Device Startup File for * Device gd32vf103 * \version V1.00 * \date 21 Nov 2019 * * ******************************************************************************/ #include "riscv_encoding.h" .macro DECLARE_INT_HANDLER INT_HDL_NAME #if defined(__riscv_xlen) && (__riscv_xlen == 32) .word \INT_HDL_NAME #else .dword \INT_HDL_NAME #endif .endm /* * Put the interrupt vectors in this section according to the run mode: * FlashXIP: .vtable * ILM: .vtable * Flash: .vtable_ilm */ #if defined(DOWNLOAD_MODE) && (DOWNLOAD_MODE == DOWNLOAD_MODE_FLASH) .section .vtable_ilm #else .section .vtable #endif .weak eclic_msip_handler .weak eclic_mtip_handler .weak eclic_bwei_handler .weak eclic_pmovi_handler .weak WWDGT_IRQHandler .weak LVD_IRQHandler .weak TAMPER_IRQHandler .weak RTC_IRQHandler .weak FMC_IRQHandler .weak RCU_IRQHandler .weak EXTI0_IRQHandler .weak EXTI1_IRQHandler .weak EXTI2_IRQHandler .weak EXTI3_IRQHandler .weak EXTI4_IRQHandler .weak DMA0_Channel0_IRQHandler .weak DMA0_Channel1_IRQHandler .weak DMA0_Channel2_IRQHandler .weak DMA0_Channel3_IRQHandler .weak DMA0_Channel4_IRQHandler .weak DMA0_Channel5_IRQHandler .weak DMA0_Channel6_IRQHandler .weak ADC0_1_IRQHandler .weak CAN0_TX_IRQHandler .weak CAN0_RX0_IRQHandler .weak CAN0_RX1_IRQHandler .weak CAN0_EWMC_IRQHandler .weak EXTI5_9_IRQHandler .weak TIMER0_BRK_IRQHandler .weak TIMER0_UP_IRQHandler .weak TIMER0_TRG_CMT_IRQHandler .weak TIMER0_Channel_IRQHandler .weak TIMER1_IRQHandler .weak TIMER2_IRQHandler .weak TIMER3_IRQHandler .weak I2C0_EV_IRQHandler .weak I2C0_ER_IRQHandler .weak I2C1_EV_IRQHandler .weak I2C1_ER_IRQHandler .weak SPI0_IRQHandler .weak SPI1_IRQHandler .weak USART0_IRQHandler .weak USART1_IRQHandler .weak USART2_IRQHandler .weak EXTI10_15_IRQHandler .weak RTC_Alarm_IRQHandler .weak USBFS_WKUP_IRQHandler .weak EXMC_IRQHandler .weak TIMER4_IRQHandler .weak SPI2_IRQHandler .weak UART3_IRQHandler .weak UART4_IRQHandler .weak TIMER5_IRQHandler .weak TIMER6_IRQHandler .weak DMA1_Channel0_IRQHandler .weak DMA1_Channel1_IRQHandler .weak DMA1_Channel2_IRQHandler .weak DMA1_Channel3_IRQHandler .weak DMA1_Channel4_IRQHandler .weak CAN1_TX_IRQHandler .weak CAN1_RX0_IRQHandler .weak CAN1_RX1_IRQHandler .weak CAN1_EWMC_IRQHandler .weak USBFS_IRQHandler .globl vector_base vector_base: #if defined(DOWNLOAD_MODE) && (DOWNLOAD_MODE != DOWNLOAD_MODE_FLASH) j _start /* 0: Reserved, Jump to _start when reset for ILM/FlashXIP mode.*/ .align LOG_REGBYTES /* Need to align 4 byte for RV32, 8 Byte for RV64 */ #else DECLARE_INT_HANDLER default_intexc_handler /* 0: Reserved, default handler for Flash download mode */ #endif DECLARE_INT_HANDLER default_intexc_handler /* 1: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 2: Reserved */ DECLARE_INT_HANDLER eclic_msip_handler /* 3: Machine software interrupt */ DECLARE_INT_HANDLER default_intexc_handler /* 4: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 5: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 6: Reserved */ DECLARE_INT_HANDLER eclic_mtip_handler /* 7: Machine timer interrupt */ DECLARE_INT_HANDLER default_intexc_handler /* 8: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 9: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 10: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 11: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 12: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 13: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 14: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 15: Reserved */ DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */ DECLARE_INT_HANDLER eclic_bwei_handler /* 17: Bus Error interrupt */ DECLARE_INT_HANDLER eclic_pmovi_handler /* 18: Performance Monitor */ DECLARE_INT_HANDLER WWDGT_IRQHandler DECLARE_INT_HANDLER LVD_IRQHandler DECLARE_INT_HANDLER TAMPER_IRQHandler DECLARE_INT_HANDLER RTC_IRQHandler DECLARE_INT_HANDLER FMC_IRQHandler DECLARE_INT_HANDLER RCU_IRQHandler DECLARE_INT_HANDLER EXTI0_IRQHandler DECLARE_INT_HANDLER EXTI1_IRQHandler DECLARE_INT_HANDLER EXTI2_IRQHandler DECLARE_INT_HANDLER EXTI3_IRQHandler DECLARE_INT_HANDLER EXTI4_IRQHandler DECLARE_INT_HANDLER DMA0_Channel0_IRQHandler DECLARE_INT_HANDLER DMA0_Channel1_IRQHandler DECLARE_INT_HANDLER DMA0_Channel2_IRQHandler DECLARE_INT_HANDLER DMA0_Channel3_IRQHandler DECLARE_INT_HANDLER DMA0_Channel4_IRQHandler DECLARE_INT_HANDLER DMA0_Channel5_IRQHandler DECLARE_INT_HANDLER DMA0_Channel6_IRQHandler DECLARE_INT_HANDLER ADC0_1_IRQHandler DECLARE_INT_HANDLER CAN0_TX_IRQHandler DECLARE_INT_HANDLER CAN0_RX0_IRQHandler DECLARE_INT_HANDLER CAN0_RX1_IRQHandler DECLARE_INT_HANDLER CAN0_EWMC_IRQHandler DECLARE_INT_HANDLER EXTI5_9_IRQHandler DECLARE_INT_HANDLER TIMER0_BRK_IRQHandler DECLARE_INT_HANDLER TIMER0_UP_IRQHandler DECLARE_INT_HANDLER TIMER0_TRG_CMT_IRQHandler DECLARE_INT_HANDLER TIMER0_Channel_IRQHandler DECLARE_INT_HANDLER TIMER1_IRQHandler DECLARE_INT_HANDLER TIMER2_IRQHandler DECLARE_INT_HANDLER TIMER3_IRQHandler DECLARE_INT_HANDLER I2C0_EV_IRQHandler DECLARE_INT_HANDLER I2C0_ER_IRQHandler DECLARE_INT_HANDLER I2C1_EV_IRQHandler DECLARE_INT_HANDLER I2C1_ER_IRQHandler DECLARE_INT_HANDLER SPI0_IRQHandler DECLARE_INT_HANDLER SPI1_IRQHandler DECLARE_INT_HANDLER USART0_IRQHandler DECLARE_INT_HANDLER USART1_IRQHandler DECLARE_INT_HANDLER USART2_IRQHandler DECLARE_INT_HANDLER EXTI10_15_IRQHandler DECLARE_INT_HANDLER RTC_Alarm_IRQHandler DECLARE_INT_HANDLER USBFS_WKUP_IRQHandler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER EXMC_IRQHandler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER TIMER4_IRQHandler DECLARE_INT_HANDLER SPI2_IRQHandler DECLARE_INT_HANDLER UART3_IRQHandler DECLARE_INT_HANDLER UART4_IRQHandler DECLARE_INT_HANDLER TIMER5_IRQHandler DECLARE_INT_HANDLER TIMER6_IRQHandler DECLARE_INT_HANDLER DMA1_Channel0_IRQHandler DECLARE_INT_HANDLER DMA1_Channel1_IRQHandler DECLARE_INT_HANDLER DMA1_Channel2_IRQHandler DECLARE_INT_HANDLER DMA1_Channel3_IRQHandler DECLARE_INT_HANDLER DMA1_Channel4_IRQHandler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER default_intexc_handler DECLARE_INT_HANDLER CAN1_TX_IRQHandler DECLARE_INT_HANDLER CAN1_RX0_IRQHandler DECLARE_INT_HANDLER CAN1_RX1_IRQHandler DECLARE_INT_HANDLER CAN1_EWMC_IRQHandler DECLARE_INT_HANDLER USBFS_IRQHandler .section .init .globl _start .type _start,@function /** * Reset Handler called on controller reset */ _start: /* ===== Startup Stage 1 ===== */ /* Disable Global Interrupt */ csrc CSR_MSTATUS, MSTATUS_MIE /* Jump to logical address first to ensure correct operation of RAM region */ la a0, _start li a1, 1 slli a1, a1, 29 bleu a1, a0, _start0800 srli a1, a1, 2 bleu a1, a0, _start0800 la a0, _start0800 add a0, a0, a1 jr a0 _start0800: /* Initialize GP and Stack Pointer SP */ .option push .option norelax la gp, __global_pointer$ .option pop la sp, _sp /* * Set the the NMI base mnvec to share * with mtvec by setting CSR_MMISC_CTL * bit 9 NMI_CAUSE_FFF to 1 */ li t0, MMISC_CTL_NMI_CAUSE_FFF csrs CSR_MMISC_CTL, t0 /* * Intialize ECLIC vector interrupt * base address mtvt to vector_base */ la t0, vector_base csrw CSR_MTVT, t0 /* * Set ECLIC non-vector entry to be controlled * by mtvt2 CSR register. * Intialize ECLIC non-vector interrupt * base address mtvt2 to irq_entry. */ la t0, irq_entry csrw CSR_MTVT2, t0 csrs CSR_MTVT2, 0x1 /* * Set Exception Entry MTVEC to exc_entry * Due to settings above, Exception and NMI * will share common entry. */ la t0, exc_entry csrw CSR_MTVEC, t0 /* Set the interrupt processing mode to ECLIC mode */ li t0, 0x3f csrc CSR_MTVEC, t0 csrs CSR_MTVEC, 0x3 /* ===== Startup Stage 2 ===== */ /* Enable mcycle and minstret counter */ csrci CSR_MCOUNTINHIBIT, 0x5 /* ===== Startup Stage 3 ===== */ /* * Load code section from FLASH to ILM * when code LMA is different with VMA */ la a0, _ilm_lma la a1, _ilm /* If the ILM phy-address same as the logic-address, then quit */ beq a0, a1, 2f la a2, _eilm bgeu a1, a2, 2f 1: /* Load code section if necessary */ lw t0, (a0) sw t0, (a1) addi a0, a0, 4 addi a1, a1, 4 bltu a1, a2, 1b 2: /* Load data section */ la a0, _data_lma la a1, _data la a2, _edata bgeu a1, a2, 2f 1: lw t0, (a0) sw t0, (a1) addi a0, a0, 4 addi a1, a1, 4 bltu a1, a2, 1b 2: /* Clear bss section */ la a0, __bss_start la a1, _end bgeu a0, a1, 2f 1: sw zero, (a0) addi a0, a0, 4 bltu a0, a1, 1b 2: /* * Call vendor defined SystemInit to * initialize the micro-controller system */ call SystemInit /* Call global constructors */ la a0, __libc_fini_array call atexit /* Call C/C++ constructor start up code */ call __libc_init_array /* do pre-init steps before main */ call _premain_init /* ===== Call Main Function ===== */ /* argc = argv = 0 */ li a0, 0 li a1, 0 call main /* do post-main steps after main */ call _postmain_fini 1: j 1b ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/close.c ================================================ #include "stub.h" #include int _close(int fd) { return _stub(EBADF); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/fstat.c ================================================ #include "stub.h" #include #include #include int _fstat(int fd, struct stat *st) { return _stub(EBADF); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/gettimeofday.c ================================================ #include "nuclei_sdk_soc.h" #include #include int _gettimeofday(struct timeval *tp, void *tzp) { uint64_t cycles; cycles = __get_rv_cycle(); tp->tv_sec = cycles / SystemCoreClock; tp->tv_usec = (cycles % SystemCoreClock) * 1000000 / SystemCoreClock; return 0; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/isatty.c ================================================ /* See LICENSE of license details. */ #include int _isatty(int fd) { if (fd == STDOUT_FILENO || fd == STDERR_FILENO) { return 1; } return 0; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/lseek.c ================================================ #include "stub.h" #include #include #include off_t _lseek(int fd, off_t ptr, int dir) { return _stub(EBADF); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/read.c ================================================ #include "gd32vf103_usart.h" #include #include #include #include // #define UART_AUTO_ECHO ssize_t _read(int fd, void *ptr, size_t len) { return -1; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/sbrk.c ================================================ /* See LICENSE of license details. */ #include #include #include void *_sbrk(ptrdiff_t incr) { extern char _end[]; extern char _heap_end[]; static char *curbrk = _end; if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) { return NULL - 1; } curbrk += incr; return curbrk - incr; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/Stubs/stub.h ================================================ static inline int _stub(int err) { return -1; } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/gd32vf103_soc.c ================================================ #include "nuclei_sdk_soc.h" static uint32_t get_timer_freq() { return SOC_TIMER_FREQ; } uint32_t measure_cpu_freq(uint32_t n) { uint32_t start_mcycle, delta_mcycle; uint32_t start_mtime, delta_mtime; uint32_t mtime_freq = get_timer_freq(); // Don't start measuruing until we see an mtime tick uint32_t tmp = (uint32_t)SysTimer_GetLoadValue(); do { start_mtime = (uint32_t)SysTimer_GetLoadValue(); start_mcycle = __RV_CSR_READ(CSR_MCYCLE); } while (start_mtime == tmp); do { delta_mtime = (uint32_t)SysTimer_GetLoadValue() - start_mtime; delta_mcycle = __RV_CSR_READ(CSR_MCYCLE) - start_mcycle; } while (delta_mtime < n); return (delta_mcycle / delta_mtime) * mtime_freq + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; } uint32_t get_cpu_freq() { uint32_t cpu_freq; // warm up measure_cpu_freq(1); // measure for real cpu_freq = measure_cpu_freq(100); return cpu_freq; } /** * \brief delay a time in milliseconds * \details * provide API for delay * \param[in] count: count in milliseconds * \remarks */ void delay_1ms(uint32_t count) { uint64_t end_mtime; uint64_t delay_ticks = ((SOC_TIMER_FREQ / 4) * (uint64_t)count) / 1000; end_mtime = SysTimer_GetLoadValue() + delay_ticks; do { asm("nop"); } while (SysTimer_GetLoadValue() < end_mtime); } ================================================ FILE: source/Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Common/Source/system_gd32vf103.c ================================================ /****************************************************************************** * @file system_gd32vf103.c * @brief NMSIS Nuclei Core Device Peripheral Access Layer Source File for * Device gd32vf103 * @version V1.00 * @date 22. Nov 2019 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2019 Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "gd32vf103.h" #include "gd32vf103_rcu.h" #include #include /*---------------------------------------------------------------------------- Define clocks *----------------------------------------------------------------------------*/ /* ToDo: add here your necessary defines for device initialization following is an example for different system frequencies */ #ifndef SYSTEM_CLOCK #define SYSTEM_CLOCK __SYSTEM_CLOCK_108M_PLL_HXTAL #endif /** * \defgroup NMSIS_Core_SystemAndClock System and Clock Configuration * \brief Functions for system and clock setup available in system_.c. * \details * Nuclei provides a template file **system_Device.c** that must be adapted by * the silicon vendor to match their actual device. As a minimum requirement, * this file must provide: * - A device-specific system configuration function, \ref SystemInit(). * - A global variable that contains the system frequency, \ref SystemCoreClock. * * The file configures the device and, typically, initializes the oscillator (PLL) that is part * of the microcontroller device. This file might export other functions or variables that provide * a more flexible configuration of the microcontroller system. * * \note Please pay special attention to the static variable \c SystemCoreClock. This variable might be * used throughout the whole system initialization and runtime to calculate frequency/time related values. * Thus one must assure that the variable always reflects the actual system clock speed. * * \attention * Be aware that a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get * overwritten by C libray startup code and/or .bss section initialization. * Thus its highly recommended to call \ref SystemCoreClockUpdate at the beginning of the user \c main() routine. * * @{ */ /*---------------------------------------------------------------------------- System Core Clock Variable *----------------------------------------------------------------------------*/ /* ToDo: initialize SystemCoreClock with the system core clock frequency value achieved after system intitialization. This means system core clock frequency after call to SystemInit() */ /** * \brief Variable to hold the system core clock value * \details * Holds the system core clock, which is the system clock frequency supplied to the SysTick * timer and the processor core clock. This variable can be used by debuggers to query the * frequency of the debug timer or to configure the trace clock speed. * * \attention * Compilers must be configured to avoid removing this variable in case the application * program is not using it. Debugging systems require the variable to be physically * present in memory so that it can be examined to configure the debugger. */ uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; /* System Clock Frequency (Core Clock) */ /*---------------------------------------------------------------------------- Clock functions *----------------------------------------------------------------------------*/ /*! \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source \param[in] none \param[out] none \retval none */ static void system_clock_108m_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than * HXTAL_STARTUP_TIMEOUT */ do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { while (1) { } } /* HXTAL is stable */ /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB/1 */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); if (HXTAL_VALUE == 25000000) { /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10); /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) { } /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL2EN; /* wait till PLL1 is ready */ while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) { } } else if (HXTAL_VALUE == 8000000) { RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) { } /* enable PLL2 */ RCU_CTL |= RCU_CTL_PLL2EN; /* wait till PLL1 is ready */ while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) { } } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { } } /*! \brief configure the system clock \param[in] none \param[out] none \retval none */ static void system_clock_config(void) { system_clock_108m_hxtal(); } /** * \brief Function to update the variable \ref SystemCoreClock * \details * Updates the variable \ref SystemCoreClock and must be called whenever the core clock is changed * during program execution. The function evaluates the clock register settings and calculates * the current core clock. */ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ { /* ToDo: add code to calculate the system frequency based upon the current * register settings. * Note: This function can be used to retrieve the system core clock * frequeny after user changed register settings. */ uint32_t scss; uint32_t pllsel, predv0sel, pllmf, ck_src; uint32_t predv0, predv1, pll1mf; scss = GET_BITS(RCU_CFG0, 2, 3); switch (scss) { /* IRC8M is selected as CK_SYS */ case SEL_IRC8M: SystemCoreClock = IRC8M_VALUE; break; /* HXTAL is selected as CK_SYS */ case SEL_HXTAL: SystemCoreClock = HXTAL_VALUE; break; /* PLL is selected as CK_SYS */ case SEL_PLL: /* PLL clock source selection, HXTAL or IRC8M/2 */ pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); if (RCU_PLLSRC_IRC8M_DIV2 == pllsel) { /* PLL clock source is IRC8M/2 */ ck_src = IRC8M_VALUE / 2U; } else { /* PLL clock source is HXTAL */ ck_src = HXTAL_VALUE; predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); /* source clock use PLL1 */ if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; if (17U == pll1mf) { pll1mf = 20U; } ck_src = (ck_src / predv1) * pll1mf; } predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; ck_src /= predv0; } /* PLL multiplication factor */ pllmf = GET_BITS(RCU_CFG0, 18, 21); if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { pllmf |= 0x10U; } if (pllmf >= 15U) { pllmf += 1U; } else { pllmf += 2U; } SystemCoreClock = ck_src * pllmf; if (15U == pllmf) { /* PLL source clock multiply by 6.5 */ SystemCoreClock = ck_src * 6U + ck_src / 2U; } break; /* IRC8M is selected as CK_SYS */ default: SystemCoreClock = IRC8M_VALUE; break; } } /** * \brief Function to Initialize the system. * \details * Initializes the microcontroller system. Typically, this function configures the * oscillator (PLL) that is part of the microcontroller device. For systems * with a variable clock speed, it updates the variable \ref SystemCoreClock. * SystemInit is called from the file startup_device. */ void SystemInit(void) { /* ToDo: add code to initialize the system * Warn: do not use global variables because this function is called before * reaching pre-main. RW section maybe overwritten afterwards. */ /* reset the RCC clock configuration to the default reset state */ /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); /* reset HXTALEN, CKMEN, PLLEN bits */ RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); /* Reset HXTALBPS bit */ RCU_CTL &= ~(RCU_CTL_HXTALBPS); /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); RCU_CFG1 = 0x00000000U; /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); /* disable all interrupts */ RCU_INT = 0x00FF0000U; /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ system_clock_config(); } /** * \defgroup NMSIS_Core_IntExcNMI_Handling Interrupt and Exception and NMI Handling * \brief Functions for interrupt, exception and nmi handle available in system_.c. * \details * Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according * to their requirement. Silicon vendor could implement interface for different exception code and * replace current implementation. * * @{ */ /** \brief Max exception handler number, don't include the NMI(0xFFF) one */ #define MAX_SYSTEM_EXCEPTION_NUM 12 /** * \brief Store the exception handlers for each exception ID * \note * - This SystemExceptionHandlers are used to store all the handlers for all * the exception codes Nuclei N/NX core provided. * - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11] * - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] */ static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1]; /** * \brief Exception Handler Function Typedef * \note * This typedef is only used internal in this system_gd32vf103.c file. * It is used to do type conversion for registered exception handler before calling it. */ typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp); /** * \brief System Default Exception Handler * \details * This function provided a default exception and NMI handling code for all exception ids. * By default, It will just print some information for debug, Vendor can customize it according to its requirements. */ static void system_default_exception_handler(unsigned long mcause, unsigned long sp) { /* TODO: Uncomment this if you have implement printf function */ printf("MCAUSE: 0x%lx\r\n", mcause); printf("MEPC : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC)); printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR)); while (1) { } } /** * \brief Initialize all the default core exception handlers * \details * The core exception handler for each exception id will be initialized to \ref system_default_exception_handler. * \note * Called in \ref _init function, used to initialize default exception handlers for all exception IDs */ static void Exception_Init(void) { for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) { SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler; } } /** * \brief Register an exception handler for exception code EXCn * \details * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1]. * * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]. * \param EXCn See \ref EXCn_Type * \param exc_handler The exception handler for this exception code EXCn */ void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler) { if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM)) { SystemExceptionHandlers[EXCn] = exc_handler; } else if (EXCn == NMI_EXCn) { SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler; } } /** * \brief Get current exception handler for exception code EXCn * \details * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1]. * * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]. * \param EXCn See \ref EXCn_Type * \return Current exception handler for exception code EXCn, if not found, return 0. */ unsigned long Exception_Get_EXC(uint32_t EXCn) { if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM)) { return SystemExceptionHandlers[EXCn]; } else if (EXCn == NMI_EXCn) { return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]; } else { return 0; } } /** * \brief Common NMI and Exception handler entry * \details * This function provided a command entry for NMI and exception. Silicon Vendor could modify * this template implementation according to requirement. * \remarks * - RISCV provided common entry for all types of exception. This is proposed code template * for exception entry function, Silicon Vendor could modify the implementation. * - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC * which can help developer to register your exception handler for specific exception number. */ uint32_t core_exception_handler(unsigned long mcause, unsigned long sp) { uint32_t EXCn = (uint32_t)(mcause & 0X00000fff); EXC_HANDLER exc_handler; if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM)) { exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn]; } else if (EXCn == NMI_EXCn) { exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]; } else { exc_handler = (EXC_HANDLER)system_default_exception_handler; } if (exc_handler != NULL) { exc_handler(mcause, sp); } return 0; } /** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */ void SystemBannerPrint(void) { #if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1) #ifndef DOWNLOAD_MODE #error DOWNLOAD_MODE is not defined via build system, please check! #endif const char *download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"}; printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__); printf("Download Mode: %s\r\n", download_modes[DOWNLOAD_MODE]); printf("CPU Frequency %d Hz\r\n", SystemCoreClock); #endif } /** * \brief initialize eclic config * \details * Eclic need initialize after boot up, Vendor could also change the initialization * configuration. */ void ECLIC_Init(void) { /* TODO: Add your own initialization code here. This function will be called by main */ ECLIC_SetMth(0); ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS); } /** * \brief Initialize a specific IRQ and register the handler * \details * This function set vector mode, trigger mode and polarity, interrupt level and priority, * assign handler for specific IRQn. * \param [in] IRQn NMI interrupt handler address * \param [in] shv \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode * \param [in] trig_mode see \ref ECLIC_TRIGGER_Type * \param [in] lvl interupt level * \param [in] priority interrupt priority * \param [in] handler interrupt handler, if NULL, handler will not be installed * \return -1 means invalid input parameter. 0 means successful. * \remarks * - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt. * - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed */ int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler) { if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) { return -1; } /* set interrupt vector mode */ ECLIC_SetShvIRQ(IRQn, shv); /* set interrupt trigger mode and polarity */ ECLIC_SetTrigIRQ(IRQn, trig_mode); /* set interrupt level */ ECLIC_SetLevelIRQ(IRQn, lvl); /* set interrupt priority */ ECLIC_SetPriorityIRQ(IRQn, priority); if (handler != NULL) { /* set interrupt handler entry to vector table */ ECLIC_SetVector(IRQn, (rv_csr_t)handler); } /* enable interrupt */ ECLIC_EnableIRQ(IRQn); return 0; } /** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */ /** * \brief early init function before main * \details * This function is executed right before main function. * For RISC-V gnu toolchain, _init function might not be called * by __libc_init_array function, so we defined a new function * to do initialization */ void _premain_init(void) { /* TODO: Add your own initialization code here, called before main */ SystemCoreClock = get_cpu_freq(); /* Initialize exception default handlers */ Exception_Init(); /* ECLIC initialization, mainly MTH and NLBIT */ ECLIC_Init(); } /** * \brief finish function after main * \param [in] status status code return from main * \details * This function is executed right after main function. * For RISC-V gnu toolchain, _fini function might not be called * by __libc_fini_array function, so we defined a new function * to do initialization */ void _postmain_fini(int status) { /* TODO: Add your own finishing code here, called after main */ } /** * \brief _init function called in __libc_init_array() * \details * This `__libc_init_array()` function is called during startup code, * user need to implement this function, otherwise when link it will * error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init' * \note * Please use \ref _premain_init function now */ void _init(void) { /* Don't put any code here, please use _premain_init now */ } /** * \brief _fini function called in __libc_fini_array() * \details * This `__libc_fini_array()` function is called when exit main. * user need to implement this function, otherwise when link it will * error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini' * \note * Please use \ref _postmain_fini function now */ void _fini(void) { /* Don't put any code here, please use _postmain_fini now */ } /** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */ ================================================ FILE: source/Core/BSP/Pinecil/configuration.h ================================================ #ifndef CONFIGURATION_H_ #define CONFIGURATION_H_ #include /** * Configuration.h * Define here your default pre settings for Pinecil * */ //=========================================================================== //============================= Default Settings ============================ //=========================================================================== /** * Default soldering temp is 320.0 C * Temperature the iron sleeps at - default 150.0 C */ #define SLEEP_TEMP 150 // Default sleep temperature #define BOOST_TEMP 420 // Default boost temp. #define BOOST_MODE_ENABLED 1 // 0: Disable 1: Enable /** * Blink the temperature on the cooling screen when its > 50C */ #define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable /** * How many seconds/minutes we wait until going to sleep/shutdown. * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds! */ #define SLEEP_TIME 5 // x10 Seconds #define SHUTDOWN_TIME 10 // Minutes /** * Auto start off for safety. * Pissible values are: * 0 - none * 1 - Soldering Temperature * 2 - Sleep Temperature * 3 - Sleep Off Temperature */ #define AUTO_START_MODE 0 // Default to none /** * Locking Mode * When in soldering mode a long press on both keys toggle the lock of the buttons * Possible values are: * 0 - Desactivated * 1 - Lock except boost * 2 - Full lock */ #define LOCKING_MODE 0 // Default to desactivated for safety /** * OLED Orientation * */ #define ORIENTATION_MODE 2 // 0: Right 1:Left 2:Automatic - Default Automatic #define MAX_ORIENTATION_MODE 2 // Up to auto #define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change /** * OLED Brightness * */ #define MIN_BRIGHTNESS 0 // Min OLED brightness selectable #define MAX_BRIGHTNESS 100 // Max OLED brightness selectable #define BRIGHTNESS_STEP 25 // OLED brightness increment #define DEFAULT_BRIGHTNESS 25 // default OLED brightness /** * Temp change settings */ #define TEMP_CHANGE_SHORT_STEP 1 // Default temp change short step +1 #define TEMP_CHANGE_LONG_STEP 10 // Default temp change long step +10 #define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value #define TEMP_CHANGE_LONG_STEP_MAX 90 // Temp change long step MAX value /* Power pulse for keeping power banks awake*/ #define POWER_PULSE_INCREMENT 1 #define POWER_PULSE_MAX 100 // x10 max watts #define POWER_PULSE_WAIT_MAX 9 // 9*2.5s = 22.5 seconds #define POWER_PULSE_DURATION_MAX 9 // 9*250ms = 2.25 seconds #ifdef MODEL_Pinecil #define POWER_PULSE_DEFAULT 0 #else #define POWER_PULSE_DEFAULT 5 #endif /* Pinecil */ #define POWER_PULSE_WAIT_DEFAULT 4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s #define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms /** * OLED Orientation Sensitivity on Automatic mode! * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive> */ #define SENSITIVITY 7 // Default 7 /** * Detailed soldering screen * Detailed idle screen (off for first time users) */ #define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0 #define DETAILED_IDLE 0 // 0: Disable 1: Enable - Default 0 #define THERMAL_RUNAWAY_TIME_SEC 20 #define THERMAL_RUNAWAY_TEMP_C 3 #define CUT_OUT_SETTING 0 // default to no cut-off voltage #define RECOM_VOL_CELL 33 // Minimum voltage per cell (Recommended 3.3V (33)) #define TEMPERATURE_INF 0 // default to 0 #define DESCRIPTION_SCROLL_SPEED 0 // 0: Slow 1: Fast - default to slow #define ANIMATION_LOOP 1 // 0: off 1: on #define ANIMATION_SPEED settingOffSpeed_t::MEDIUM #define OP_AMP_Rf_Pinecil 750 * 1000 // 750 Kilo-ohms -> From schematic, R1 #define OP_AMP_Rin_Pinecil 2370 // 2.37 Kilo-ohms -> From schematic, R2 #define OP_AMP_GAIN_STAGE_PINECIL (1 + (OP_AMP_Rf_Pinecil / OP_AMP_Rin_Pinecil)) #define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc #define ADC_VDD_MV 3300 // ADC max reading millivolts #if defined(MODEL_Pinecil) == 0 #error "No model defined!" #endif #ifdef MODEL_Pinecil #define SOLDERING_TEMP 320 // Default soldering temp is 320.0 °C #define VOLTAGE_DIV 467 // 467 - Default divider from schematic #define CALIBRATION_OFFSET 900 // 900 - Default adc offset in uV #define MIN_CALIBRATION_OFFSET 100 // Min value for calibration #define PID_POWER_LIMIT 70 // Sets the max pwm power limit #define POWER_LIMIT 0 // 0 watts default limit #define MAX_POWER_LIMIT 70 // #define POWER_LIMIT_STEPS 5 // #define OP_AMP_GAIN_STAGE OP_AMP_GAIN_STAGE_PINECIL // Uses TS100 resistors #define TEMP_uV_LOOKUP_HAKKO // Use Hakko lookup table #define USB_PD_VMAX 20 // Maximum voltage for PD to negotiate #define PID_TIM_HZ (8) // Tick rate of the PID loop #define MAX_TEMP_C 450 // Max soldering temp selectable °C #define MAX_TEMP_F 850 // Max soldering temp selectable °F #define MIN_TEMP_C 10 // Min soldering temp selectable °C #define MIN_TEMP_F 50 // Min soldering temp selectable °F #define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C #define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F #define OLED_96x16 1 #define POW_PD 1 #define USB_PD_EPR_WATTAGE 0 /*No EPR (Yet?) */ #define POW_PD_EXT 0 #define POW_QC 1 #define POW_DC 1 #define POW_QC_20V 1 #define ENABLE_QC2 1 #define MAG_SLEEP_SUPPORT 1 #define TIP_TYPE_SUPPORT 1 // Support for tips of different types, i.e. resistance #define TIPTYPE_T12 1 // Can manually pick a T12 tip #define TEMP_TMP36 #define ACCEL_BMA #define ACCEL_SC7 #define HALL_SENSOR #define VBUS_MOD_TEST #define HALL_SI7210 #define DEBUG_UART_OUTPUT #define NEEDS_VBUS_PROBE 1 #define HARDWARE_MAX_WATTAGE_X10 750 #define TIP_THERMAL_MASS 65 // X10 watts to raise 1 deg C in 1 second #define TIP_RESISTANCE 75 // x10 ohms, 7.5 typical for Pinecil tips #define CANT_DIRECT_READ_SETTINGS #endif /* Pinecil */ #define FLASH_LOGOADDR (0x08000000 + (126 * 1024)) #define SETTINGS_START_PAGE (0x08000000 + (127 * 1024)) #define HAS_POWER_DEBUG_MENU #endif /* CONFIGURATION_H_ */ ================================================ FILE: source/Core/BSP/Pinecil/flash.c ================================================ /* * flash.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "BSP_Flash.h" #include "gd32vf103_libopt.h" #include "string.h" #define FMC_PAGE_SIZE ((uint16_t)0x400U) void flash_save_buffer(const uint8_t *buffer, const uint16_t length) { /* unlock the flash program/erase controller */ fmc_unlock(); /* clear all pending flags */ fmc_flag_clear(FMC_FLAG_END); fmc_flag_clear(FMC_FLAG_WPERR); fmc_flag_clear(FMC_FLAG_PGERR); resetWatchdog(); fmc_page_erase((uint32_t)SETTINGS_START_PAGE); resetWatchdog(); uint16_t *data = (uint16_t *)buffer; for (uint16_t i = 0; i < (length / 2); i++) { fmc_halfword_program((uint32_t)SETTINGS_START_PAGE + (i * 2), data[i]); fmc_flag_clear(FMC_FLAG_END); fmc_flag_clear(FMC_FLAG_WPERR); fmc_flag_clear(FMC_FLAG_PGERR); resetWatchdog(); } fmc_lock(); } void flash_read_buffer(uint8_t *buffer, const uint16_t length) { uint32_t *b = (uint32_t *)buffer; uint32_t *b2 = (uint32_t *)SETTINGS_START_PAGE; for (int i = 0; i < length / 4; i++) { b[i] = b2[i]; } } ================================================ FILE: source/Core/BSP/Pinecil/fusb_user.cpp ================================================ #include "configuration.h" #ifdef POW_PD #include "BSP.h" #include "I2C_Wrapper.hpp" #include "Setup.h" /* * Read multiple bytes from the FUSB302B * * cfg: The FUSB302B to communicate with * addr: The memory address from which to read * size: The number of bytes to read * buf: The buffer into which data will be read */ bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(deviceAddr, registerAdd, buf, size); } /* * Write multiple bytes to the FUSB302B * * cfg: The FUSB302B to communicate with * addr: The memory address to which we will write * size: The number of bytes to write * buf: The buffer to write */ bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Write(deviceAddr, registerAdd, (uint8_t *)buf, size); } #endif ================================================ FILE: source/Core/BSP/Pinecil/postRTOS.cpp ================================================ #include "BSP.h" #include "FreeRTOS.h" #include "I2C_Wrapper.hpp" #include "QC3.h" #include "Settings.h" #include "Si7210.h" #include "cmsis_os.h" #include "main.hpp" #include "power.hpp" #include "stdlib.h" #include "task.h" bool hall_effect_present = false; void postRToSInit() { // Any after RTos setup #ifdef HALL_SI7210 if (Si7210::detect()) { hall_effect_present = Si7210::init(); } #endif } int16_t getRawHallEffect() { if (hall_effect_present) { return Si7210::read(); } return 0; } bool getHallSensorFitted() { return hall_effect_present; } ================================================ FILE: source/Core/BSP/Pinecil/preRTOS.cpp ================================================ /* * preRTOS.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "Pins.h" #include "Setup.h" #include "gd32vf103_libopt.h" #include void preRToSInit() { // Normal system bringup -- GPIO etc hardware_init(); gpio_bit_reset(OLED_RESET_GPIO_Port, OLED_RESET_Pin); delay_ms(5); gpio_bit_set(OLED_RESET_GPIO_Port, OLED_RESET_Pin); FRToSI2C::FRToSInit(); } ================================================ FILE: source/Core/BSP/Pinecilv2/BSP.cpp ================================================ // BSP mapping functions #include "BSP.h" #include "BootLogo.h" #include "I2C_Wrapper.hpp" #include "IRQ.h" #include "Pins.h" #include "Settings.h" #include "Setup.h" #if defined(WS2812B_ENABLE) #include "WS2812B.h" #endif #include "TipThermoModel.h" #include "USBPD.h" #include "Utils.hpp" #include "bflb_platform.h" #include "bl702_adc.h" #include "configuration.h" #include "crc32.h" #include "hal_flash.h" #include "history.hpp" #include "main.hpp" extern ADC_Gain_Coeff_Type adcGainCoeffCal; // These control the period's of time used for the PWM const uint16_t powerPWM = 255; uint8_t holdoffTicks = 25; // This is the tick delay before temp measure starts (i.e. time for op-amp recovery) uint8_t tempMeasureTicks = 25; uint16_t totalPWM = 255; // Total length of the cycle's ticks #if defined(WS2812B_ENABLE) WS2812B ws2812b; #endif void resetWatchdog() { // #TODO } #ifdef TEMP_NTC // Lookup table for the NTC // Stored as ADCReading,Temp in degC static const int32_t NTCHandleLookup[] = { // ADC Reading , Temp in C x10 // Based on NTCG163JF103FTDS thermocouple datasheet values, // arranged in a voltage divider configuration, with the NTC // pulling up towards 3.3V, and with a 10k 1% pull-down resistor. // ADC Reading = 3.3V * 10 / (10 + TypkOhm) / 3.2V * (2 ^ 16) 3405, -400, // 4380, -350, // 5572, -300, // 6999, -250, // 8688, -200, // 10650, -150, // 12885, -100, // 15384, -50, // 18129, 0, // 21074, 50, // 24172, 100, // 27362, 150, // 30595, 200, // 33792, 250, // 36907, 300, // 39891, 350, // 42704, 400, // 45325, 450, // 47736, 500, // 49929, 550, // 51912, 600, // 53689, 650, // 55274, 700, // 56679, 750, // 57923, 800, // 59020, 850, // 59984, 900, // 60832, 950, // 61580, 1000, // 62232, 1050, // 62810, 1100, // 63316, 1150, // 63765, 1200, // 64158, 1250, // }; #endif uint16_t getHandleTemperature(uint8_t sample) { int32_t result = getADCHandleTemp(sample); // Tip is wired up with an NTC thermistor // 10K NTC balanced with a 10K pulldown // NTCG163JF103FTDS return Utils::InterpolateLookupTable(NTCHandleLookup, sizeof(NTCHandleLookup) / (2 * sizeof(int32_t)), result); } uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) { uint32_t res = getADCVin(sample); res *= 4; res /= divisor; return res; } void unstick_I2C() { /* configure SDA/SCL for GPIO */ // GPIO_BC(GPIOB) |= SDA_Pin | SCL_Pin; // gpio_init(SDA_GPIO_Port, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); // for (int i = 0; i < 8; i++) { // asm("nop"); // asm("nop"); // asm("nop"); // asm("nop"); // asm("nop"); // GPIO_BOP(GPIOB) |= SCL_Pin; // asm("nop"); // asm("nop"); // asm("nop"); // asm("nop"); // asm("nop"); // GPIO_BOP(GPIOB) &= SCL_Pin; // } // /* connect PB6 to I2C0_SCL */ // /* connect PB7 to I2C0_SDA */ // gpio_init(SDA_GPIO_Port, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, SDA_Pin | SCL_Pin); } uint8_t getButtonA() { uint8_t val = gpio_read(KEY_A_Pin); return val; } uint8_t getButtonB() { uint8_t val = gpio_read(KEY_B_Pin); return val; } void BSPInit(void) { #if defined(WS2812B_ENABLE) ws2812b.init(); #endif } void reboot() { hal_system_reset(); } void delay_ms(uint16_t count) { // delay_1ms(count); BL702_Delay_MS(count); } uint32_t __get_IPSR(void) { return 0; // To shut-up CMSIS } bool isTipDisconnected() { uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5; uint32_t tipTemp = TipThermoModel::getTipInC(); return tipTemp > tipDisconnectedThres; } void setStatusLED(const enum StatusLED state) { #if defined(WS2812B_ENABLE) static enum StatusLED lastState = LED_UNKNOWN; if (lastState != state || state == LED_HEATING) { switch (state) { default: case LED_UNKNOWN: case LED_OFF: ws2812b.led_set_color(0, 0, 0, 0); break; case LED_STANDBY: ws2812b.led_set_color(0, 0, 0xFF, 0); // green break; case LED_HEATING: { ws2812b.led_set_color(0, ((xTaskGetTickCount() / 4) % 192) + 64, 0, 0); // Red fade } break; case LED_HOT: ws2812b.led_set_color(0, 0xFF, 0, 0); // red break; case LED_COOLING_STILL_HOT: ws2812b.led_set_color(0, 0xFF, 0x20, 0x00); // Orange break; } ws2812b.led_update(); lastState = state; } #endif } void setBuzzer(bool on) {} uint8_t lastTipResistance = 0; // default to unknown const uint8_t numTipResistanceReadings = 3; uint32_t tipResistanceReadings[3] = {0, 0, 0}; uint8_t tipResistanceReadingSlot = 0; uint8_t getTipResistanceX10() { // Return tip resistance in x10 ohms // We can measure this using the op-amp uint8_t user_selected_tip = getUserSelectedTipResistance(); if (user_selected_tip == 0) { return lastTipResistance; // Auto mode } return user_selected_tip; } uint16_t getTipThermalMass() { return 120; } uint16_t getTipInertia() { return 750; } // We want to calculate lastTipResistance // If tip is connected, and the tip is cold and the tip is not being heated // We can use the GPIO to inject a small current into the tip and measure this // The gpio is 5.1k -> diode -> tip -> gnd // Source is 3.3V-0.5V // Which is around 0.54mA this will induce: // 6 ohm tip -> 3.24mV (Real world ~= 3320) // 8 ohm tip -> 4.32mV (Real world ~= 4500) // Which is definitely measurable // Taking shortcuts here as we know we only really have to pick apart 6 and 8 ohm tips // These are reported as 60 and 75 respectively void performTipResistanceSampleReading() { // 0 = read then turn on pullup, 1 = read then turn off pullup, 2 = read then turn on pullup, 3 = final read + turn off pullup tipResistanceReadings[tipResistanceReadingSlot] = TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0)); gpio_write(TIP_RESISTANCE_SENSE, tipResistanceReadingSlot == 0); tipResistanceReadingSlot++; } bool tipShorted = false; void FinishMeasureTipResistance() { // Otherwise we now have the 4 samples; // _^_ order, 2 delta's, combine these int32_t calculatedSkew = tipResistanceReadings[0] - tipResistanceReadings[2]; // If positive tip is cooling calculatedSkew /= 2; // divide by two to get offset per time constant int32_t reading = (((tipResistanceReadings[1] - tipResistanceReadings[0]) + calculatedSkew) // jump 1 - skew + // + ((tipResistanceReadings[1] - tipResistanceReadings[2]) + calculatedSkew) // jump 2 - skew ) // / 2; // Take average // As we are only detecting three resistances; we just bin to nearest uint8_t newRes = 0; if (reading > 8000) { // Let resistance be cleared to 0 } else if (reading < 500) { tipShorted = true; } else if (reading < 2600) { newRes = 40; } else if (reading < 4000) { newRes = 62; } else { newRes = 80; } lastTipResistance = newRes; } volatile bool tipMeasurementOccuring = true; volatile TickType_t nextTipMeasurement = 100; bool isTipShorted() { return tipShorted; } void performTipMeasurementStep() { // Wait 100ms for settle time if (xTaskGetTickCount() < (nextTipMeasurement)) { return; } nextTipMeasurement = xTaskGetTickCount() + TICKS_100MS; if (tipResistanceReadingSlot < numTipResistanceReadings) { performTipResistanceSampleReading(); return; } // We are sensing the resistance FinishMeasureTipResistance(); tipMeasurementOccuring = false; } uint8_t preStartChecks() { performTipMeasurementStep(); return preStartChecksDone(); } // If we are still measuring the tip; or tip is shorted; prevent heating uint8_t preStartChecksDone() { return (lastTipResistance == 0 || tipResistanceReadingSlot < numTipResistanceReadings || tipMeasurementOccuring || tipShorted) ? 0 : 1; } // Return hardware unique ID if possible uint64_t getDeviceID() { // uint32_t tmp = 0; // uint32_t tmp2 = 0; // EF_Ctrl_Read_Sw_Usage(0, &tmp); // EF_Ctrl_Read_Sw_Usage(1, &tmp2); // return tmp | (((uint64_t)tmp2) << 32); uint64_t tmp = 0; EF_Ctrl_Read_Chip_ID((uint8_t *)&tmp); return __builtin_bswap64(tmp); } auto crc32Table = CRC32Table<>(); uint32_t gethash() { static uint32_t computedHash = 0; if (computedHash != 0) { return computedHash; } uint32_t deviceKey = EF_Ctrl_Get_Key_Slot_w0(); const uint32_t crcInitialVector = 0xCAFEF00D; uint8_t crcPayload[] = {(uint8_t)(deviceKey), (uint8_t)(deviceKey >> 8), (uint8_t)(deviceKey >> 16), (uint8_t)(deviceKey >> 24), 0, 0, 0, 0, 0, 0, 0, 0}; EF_Ctrl_Read_Chip_ID(crcPayload + sizeof(deviceKey)); // Load device key into second half computedHash = crc32Table.computeCRC32(crcInitialVector, crcPayload, sizeof(crcPayload)); return computedHash; } uint32_t getDeviceValidation() { // 4 byte user data burned in at factory return EF_Ctrl_Get_Key_Slot_w1(); } uint8_t getDeviceValidationStatus() { uint32_t programmedHash = EF_Ctrl_Get_Key_Slot_w1(); uint32_t computedHash = gethash(); return programmedHash == computedHash ? 0 : 1; } void showBootLogo(void) { alignas(uint32_t) uint8_t scratch[1024]; flash_read(FLASH_LOGOADDR - 0x23000000, scratch, 1024); BootLogo::handleShowingLogo(scratch); } ================================================ FILE: source/Core/BSP/Pinecilv2/Debug.cpp ================================================ /* * Debug.cpp * * Created on: 26 Jan. 2021 * Author: Ralim */ #include "Debug.h" #include "FreeRTOS.h" #include "Pins.h" char uartOutputBuffer[uartOutputBufferLength]; volatile uint32_t currentOutputPos = 0xFF; volatile uint32_t outputLength = 0; extern volatile uint8_t pendingPWM; void log_system_state(int32_t PWMWattsx10) { if (currentOutputPos == 0xFF) { // Want to print a CSV log out the uart // Tip_Temp_C,Handle_Temp_C,Output_Power_Wattx10,PWM,Tip_Raw\r\n // 3+1+3+1+3+1+3+1+5+2 = 23, so sizing at 32 for now outputLength = snprintf(uartOutputBuffer, uartOutputBufferLength, "%lu,%u,%li,%u,%lu\r\n", // TipThermoModel::getTipInC(false), // Tip temp in C getHandleTemperature(0), // Handle temp in C X10 PWMWattsx10, // Output Wattage pendingPWM, // PWM TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true) // Tip temp in uV ); // Now print this out the uart via IRQ (DMA cant be used as oled has it) currentOutputPos = 0; /* enable USART1 Transmit Buffer Empty interrupt */ // usart_interrupt_enable(UART_PERIF, USART_INT_TBE); } } ================================================ FILE: source/Core/BSP/Pinecilv2/Debug.h ================================================ /* * Debug.h * * Created on: 26 Jan. 2021 * Author: Ralim */ #ifndef CORE_BSP_PINE64_DEBUG_H_ #define CORE_BSP_PINE64_DEBUG_H_ #include "BSP.h" #include "TipThermoModel.h" #include #include const unsigned int uartOutputBufferLength = 32; extern char uartOutputBuffer[uartOutputBufferLength]; extern "C" { ssize_t _write(int fd, const void *ptr, size_t len); void USART1_IRQHandler(void); } #endif /* CORE_BSP_PINE64_DEBUG_H_ */ ================================================ FILE: source/Core/BSP/Pinecilv2/FreeRTOSConfig.h ================================================ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H #include #define portCHAR char #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 #define CLINT_CTRL_ADDR (0x02000000UL) #define configCLINT_BASE_ADDRESS CLINT_CTRL_ADDR #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ (1000000UL) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)160) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ #define configTOTAL_HEAP_SIZE ((size_t)1024 * 8) #define configMAX_TASK_NAME_LEN (24) #define configUSE_TRACE_FACILITY 0 #define configIDLE_SHOULD_YIELD 0 #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 #define configUSE_APPLICATION_TASK_TAG 0 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 0 #define configUSE_TICKLESS_IDLE 0 #define configTASK_NOTIFICATION_ARRAY_ENTRIES 2 #define configUSE_TASK_NOTIFICATIONS 1 #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 /* Software timer definitions. */ #define configUSE_TIMERS 1 #define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) #define configTIMER_QUEUE_LENGTH 8 #define configTIMER_TASK_STACK_DEPTH (160) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY #define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) #endif #ifdef __cplusplus extern "C" { #endif /* Normal assert() semantics without relying on the provision of an assert.h header file. */ void vAssertCalled(void); #define configASSERT(x) \ if ((x) == 0) \ vAssertCalled() #ifdef __cplusplus } #endif #if (configUSE_TICKLESS_IDLE != 0) void vApplicationSleep(uint32_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) #endif #define INCLUDE_vTaskPrioritySet 0 #define INCLUDE_uxTaskPriorityGet 0 #define INCLUDE_vTaskDelete 1 #define INCLUDE_vTaskSuspend 1 #define INCLUDE_xResumeFromISR 1 #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 1 #define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1 #define INCLUDE_xTaskGetIdleTaskHandle 1 #define INCLUDE_eTaskGetState 1 #define INCLUDE_xEventGroupSetBitFromISR 1 #define INCLUDE_xTimerPendFunctionCall 0 #define INCLUDE_xTaskAbortDelay 0 #define INCLUDE_xTaskGetHandle 1 #define INCLUDE_xTaskResumeFromISR 1 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// #endif /* FREERTOS_CONFIG_H */ ================================================ FILE: source/Core/BSP/Pinecilv2/I2C_Wrapper.cpp ================================================ /* * FRToSI2C.cpp * * Created on: 14Apr.,2018 * Author: Ralim */ #include "BSP.h" #include "IRQ.h" #include "Setup.h" #include "bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h" extern "C" { #include "bflb_platform.h" #include "bl702_dma.h" #include "bl702_glb.h" #include "bl702_i2c.h" } #include // Semaphore for locking users of I2C SemaphoreHandle_t FRToSI2C::I2CSemaphore = nullptr; StaticSemaphore_t FRToSI2C::xSemaphoreBuffer; #define I2C_TIME_OUT (uint16_t)(12000) #define I2C_NOTIFY_INDEX 1 #define I2C_TX_FIFO_ADDR (0x4000A300 + 0x88) #define I2C_RX_FIFO_ADDR (0x4000A300 + 0x8C) // Used by the irq handler volatile uint8_t *IRQDataPointer; volatile uint8_t IRQDataSizeLeft; volatile bool IRQFailureMarker; volatile TaskHandle_t IRQTaskWaitingHandle = NULL; /****** IRQ Handlers ******/ void i2c_irq_tx_fifo_low() { // Filling tx fifo // Fifo is 32 bit, LSB sent first // FiFo can store up to 2, 32-bit words // So we fill it until it has no free room (or we run out of data) while (IRQDataSizeLeft > 0 && I2C_GetTXFIFOAvailable() > 0) { // Can put in at least 1 byte // Build a 32-bit word from bytes uint32_t value = 0; int packing = IRQDataSizeLeft >= 4 ? 0 : 4 - IRQDataSizeLeft; for (int i = 0; i < 4 && IRQDataSizeLeft > 0; i++) { value >>= 8; value |= (*IRQDataPointer) << 24; // Shift to the left, adding new data to the higher byte IRQDataPointer++; // Shift to next byte IRQDataSizeLeft--; } // Handle shunting remaining bytes if not a full 4 to send for (int i = 0; i < packing; i++) { value >>= 8; } // Push the new value to the fifo *((volatile uint32_t *)I2C_TX_FIFO_ADDR) = value; } if (IRQDataSizeLeft == 0) { // Disable IRQ, were done I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, MASK); } } void i2c_rx_pop_fifo() { // Pop one word from the fifo and store it uint32_t value = *((uint32_t *)I2C_RX_FIFO_ADDR); for (int i = 0; i < 4 && IRQDataSizeLeft > 0; i++) { *IRQDataPointer = value & 0xFF; IRQDataPointer++; IRQDataSizeLeft--; value >>= 8; } } void i2c_irq_rx_fifo_ready() { // Draining the Rx FiFo while (I2C_GetRXFIFOAvailable() > 0) { i2c_rx_pop_fifo(); } if (IRQDataSizeLeft == 0) { // Disable IRQ, were done I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, MASK); } } void i2c_irq_done_read() { IRQFailureMarker = false; // If there was a non multiple of 4 bytes to be read, they are pushed to the fifo now (end of transfer interrupt) // So we catch them here while (I2C_GetRXFIFOAvailable() > 0) { i2c_rx_pop_fifo(); } // Mask IRQ's back off FRToSI2C::CpltCallback(); // Causes the lock to be released } void i2c_irq_done() { IRQFailureMarker = false; // Mask IRQ's back off FRToSI2C::CpltCallback(); // Causes the lock to be released } void i2c_irq_nack() { IRQFailureMarker = true; // Mask IRQ's back off FRToSI2C::CpltCallback(); // Causes the lock to be released } /****** END IRQ Handlers ******/ void FRToSI2C::CpltCallback() { // This is only triggered from IRQ context I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, MASK); I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, MASK); I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, MASK); I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, MASK); CPU_Interrupt_Disable(I2C_IRQn); // Disable IRQ's I2C_Disable(I2C0_ID); // Disable I2C to tidy up // Unlock the semaphore && allow task switch if desired by RTOS BaseType_t xHigherPriorityTaskWoken = pdFALSE; xSemaphoreGiveFromISR(I2CSemaphore, &xHigherPriorityTaskWoken); xTaskNotifyIndexedFromISR(IRQTaskWaitingHandle, I2C_NOTIFY_INDEX, IRQFailureMarker ? 2 : 1, eSetValueWithOverwrite, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } bool FRToSI2C::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); } uint8_t FRToSI2C::I2C_RegisterRead(uint8_t add, uint8_t reg) { uint8_t temp = 0; Mem_Read(add, reg, &temp, 1); return temp; } bool FRToSI2C::Mem_Read(uint16_t DevAddress, uint16_t read_address, uint8_t *p_buffer, uint16_t number_of_byte) { if (!lock()) { return false; } I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; BL_Err_Type err = ERROR; i2cCfg.slaveAddr = DevAddress >> 1; i2cCfg.stopEveryByte = DISABLE; i2cCfg.subAddr = read_address; i2cCfg.dataSize = number_of_byte; i2cCfg.data = p_buffer; i2cCfg.subAddrSize = 1; // one byte address // Store handles for IRQ IRQDataPointer = p_buffer; IRQDataSizeLeft = number_of_byte; IRQTaskWaitingHandle = xTaskGetCurrentTaskHandle(); IRQFailureMarker = false; I2C_Disable(I2C0_ID); // Setup and run I2C_Init(I2C0_ID, I2C_READ, &i2cCfg); // Setup hardware for the I2C init header with the device address I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK); I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK); I2C_IntMask(I2C0_ID, I2C_RX_FIFO_READY_INT, UNMASK); I2C_Int_Callback_Install(I2C0_ID, I2C_TRANS_END_INT, i2c_irq_done_read); I2C_Int_Callback_Install(I2C0_ID, I2C_NACK_RECV_INT, i2c_irq_nack); I2C_Int_Callback_Install(I2C0_ID, I2C_RX_FIFO_READY_INT, i2c_irq_rx_fifo_ready); CPU_Interrupt_Enable(I2C_IRQn); CPU_Interrupt_Disable(BLE_IRQn); // Start I2C_Enable(I2C0_ID); // Wait for transfer in background uint32_t result = 0; xTaskNotifyWaitIndexed(I2C_NOTIFY_INDEX, 0xFFFFFFFF, 0xFFFFFFFF, &result, 0xFFFFFFFF); CPU_Interrupt_Enable(BLE_IRQn); return result == 1; } bool FRToSI2C::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *p_buffer, uint16_t number_of_byte) { if (!lock()) { return false; } I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; BL_Err_Type err = ERROR; i2cCfg.slaveAddr = DevAddress >> 1; i2cCfg.stopEveryByte = DISABLE; i2cCfg.subAddr = MemAddress; i2cCfg.dataSize = number_of_byte; i2cCfg.data = p_buffer; i2cCfg.subAddrSize = 1; // one byte address // Store handles for IRQ IRQDataPointer = p_buffer; IRQDataSizeLeft = number_of_byte; IRQTaskWaitingHandle = xTaskGetCurrentTaskHandle(); IRQFailureMarker = false; // Setup and run I2C_Init(I2C0_ID, I2C_WRITE, &i2cCfg); // Setup hardware for the I2C init header with the device address I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK); I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK); I2C_IntMask(I2C0_ID, I2C_TX_FIFO_READY_INT, UNMASK); I2C_Int_Callback_Install(I2C0_ID, I2C_TRANS_END_INT, i2c_irq_done); I2C_Int_Callback_Install(I2C0_ID, I2C_NACK_RECV_INT, i2c_irq_nack); I2C_Int_Callback_Install(I2C0_ID, I2C_TX_FIFO_READY_INT, i2c_irq_tx_fifo_low); CPU_Interrupt_Enable(I2C_IRQn); i2c_irq_tx_fifo_low(); CPU_Interrupt_Disable(BLE_IRQn); // Shut up BLE while we do the transfer // Start I2C_Enable(I2C0_ID); // Wait for transfer in background uint32_t result = 0; xTaskNotifyWaitIndexed(I2C_NOTIFY_INDEX, 0xFFFFFFFF, 0xFFFFFFFF, &result, 0xFFFFFFFF); CPU_Interrupt_Enable(BLE_IRQn); // Now BLE can run return result == 1; } bool FRToSI2C::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) { return Mem_Write(DevAddress, pData[0], pData + 1, Size - 1); } bool FRToSI2C::probe(uint16_t DevAddress) { uint8_t temp[1]; return Mem_Read(DevAddress, 0x00, temp, sizeof(temp)); } void FRToSI2C::I2C_Unstick() { unstick_I2C(); } bool FRToSI2C::lock() { if (I2CSemaphore == nullptr) { return false; } return xSemaphoreTake(I2CSemaphore, TICKS_SECOND) == pdTRUE; } void FRToSI2C::unlock() { xSemaphoreGive(I2CSemaphore); } bool FRToSI2C::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) { for (int index = 0; index < registersLength; index++) { if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) { return false; } if (registers[index].pause_ms) { delay_ms(registers[index].pause_ms); } } return true; } bool FRToSI2C::wakePart(uint16_t DevAddress) { // wakepart is a special case where only the device address is sent if (!lock()) { return false; } uint8_t temp[1] = {0}; I2C_Transfer_Cfg i2cCfg = {0, DISABLE, 0, 0, 0, 0}; BL_Err_Type err = ERROR; i2cCfg.slaveAddr = DevAddress >> 1; i2cCfg.stopEveryByte = DISABLE; i2cCfg.subAddr = 0; i2cCfg.dataSize = 1; i2cCfg.data = temp; i2cCfg.subAddrSize = 0; err = I2C_MasterReceiveBlocking(I2C0_ID, &i2cCfg); bool res = err == SUCCESS; if (!res) { I2C_Unstick(); } unlock(); return res; } ================================================ FILE: source/Core/BSP/Pinecilv2/IRQ.cpp ================================================ /* * IRQ.c * * Created on: 30 May 2020 * Author: Ralim */ #include "IRQ.h" #include "Pins.h" #include "configuration.h" #include "history.hpp" extern "C" { #include "bflb_platform.h" #include "bl702_adc.h" #include "bl702_glb.h" #include "bl702_pwm.h" #include "bl702_timer.h" } void start_PWM_output(void); #define ADC_Filter_Smooth 4 /* This basically smooths over one PWM cycle / set of readings */ history ADC_Vin; history ADC_Temp; history ADC_Tip; void read_adc_fifo(void) { // Read out all entries in the fifo uint8_t pending_readings = ADC_Get_FIFO_Count(); // There _should_ always be 8 readings here. If there are not, it means that the adc didnt start when we wanted and timing slipped // So if there isn't 8 readings, we throw them out if (pending_readings != 8) { MSG((char *)"Discarding out of sync adc %d\r\n", pending_readings); } else { while (pending_readings) { pending_readings--; uint32_t raw_reading = ADC_Read_FIFO(); ADC_Result_Type parsed = {0, 0, 0}; ADC_Parse_Result(&raw_reading, 1, &parsed); // Rollover prevention if (parsed.value > ((1 << 14) - 1)) { parsed.value = ((1 << 14) - 1); } switch (parsed.posChan) { case TMP36_ADC_CHANNEL: ADC_Temp.update(parsed.value << 2); break; case TIP_TEMP_ADC_CHANNEL: { ADC_Tip.update(parsed.value << 2); } break; case VIN_ADC_CHANNEL: ADC_Vin.update(parsed.value << 2); break; default: break; } } } // unblock the PID controller thread if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; if (pidTaskNotification) { vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } } } volatile bool inFastPWMMode = false; static void switchToFastPWM(void); static void switchToSlowPWM(void); volatile uint16_t PWMSafetyTimer = 0; volatile uint8_t pendingPWM = 0; volatile bool pendingNextPeriodIsFast = false; void timer0_comp0_callback(void) { // Trigged at end of output cycle; turn off the tip PWM PWM_Channel_Disable(PWM_Channel); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_0); } // Timer 0 is used to co-ordinate the ADC and the output PWM void timer0_comp1_callback(void) { ADC_FIFO_Clear(); ADC_Start(); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_1); } void timer0_comp2_callback(void) { // Triggered at end of timer cycle; re-start the tip driver ADC_Stop(); TIMER_Disable(TIMER_CH0); // Read the ADC data _now_. So that if things have gone out of sync, we know about it read_adc_fifo(); if (PWMSafetyTimer) { PWMSafetyTimer--; if (pendingNextPeriodIsFast != inFastPWMMode) { if (pendingNextPeriodIsFast) { switchToFastPWM(); } else { switchToSlowPWM(); } } // Update trigger for the end point of the PWM cycle if (pendingPWM > 0) { TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_0, pendingPWM - 1); // Turn on output PWM_Channel_Enable(PWM_Channel); } else { PWM_Channel_Disable(PWM_Channel); } } else { PWM_Channel_Disable(PWM_Channel); } TIMER_Enable(TIMER_CH0); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_2); } void switchToFastPWM(void) { inFastPWMMode = true; holdoffTicks = 20; tempMeasureTicks = 10; totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_1, powerPWM + holdoffTicks); TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_2, totalPWM); // Set divider to 10 ~= 10.5Hz uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 10); BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); } void switchToSlowPWM(void) { // 5Hz inFastPWMMode = false; holdoffTicks = 10; tempMeasureTicks = 5; totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; // Adjust ADC TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_1, powerPWM + holdoffTicks); TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_2, totalPWM); // Set divider for ~ 5Hz uint32_t tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, 20); BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal); } void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) { PWMSafetyTimer = 10; // This is decremented in the handler for PWM so that the tip pwm is // disabled if the PID task is not scheduled often enough. pendingPWM = pulse; pendingNextPeriodIsFast = shouldUseFastModePWM; } extern osThreadId POWTaskHandle; void GPIO_IRQHandler(void) { if (SET == GLB_Get_GPIO_IntStatus(FUSB302_IRQ_GLB_Pin)) { GLB_GPIO_IntClear(FUSB302_IRQ_GLB_Pin, SET); #ifdef POW_PD if (POWTaskHandle != nullptr) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken); /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE. The macro used to do this is dependent on the port and may be called portEND_SWITCHING_ISR. */ portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } #endif /* timeout check */ uint32_t timeOut = 32; do { timeOut--; } while ((SET == GLB_Get_GPIO_IntStatus(FUSB302_IRQ_GLB_Pin)) && timeOut); if (!timeOut) { // MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); } GLB_GPIO_IntClear(FUSB302_IRQ_GLB_Pin, RESET); } } bool getFUS302IRQLow() { // Return true if the IRQ line is still held low return !gpio_read(FUSB302_IRQ_Pin); } uint16_t getADCHandleTemp(uint8_t sample) { return ADC_Temp.average(); } uint16_t getADCVin(uint8_t sample) { return ADC_Vin.average(); } // Returns the current raw tip reading after any cleanup filtering // For Pinecil V2 we dont do any rolling filtering other than just averaging all 4 readings in the adc snapshot uint16_t getTipRawTemp(uint8_t sample) { return ADC_Tip.average() >> 1; } ================================================ FILE: source/Core/BSP/Pinecilv2/IRQ.h ================================================ /* * Irqs.h * * Created on: 30 May 2020 * Author: Ralim */ #ifndef BSP_PINE64_IRQ_H_ #define BSP_PINE64_IRQ_H_ #include "BSP.h" #include "I2C_Wrapper.hpp" #include "Setup.h" #include "main.hpp" #ifdef __cplusplus extern "C" { #endif void timer0_comp0_callback(void); void timer0_comp1_callback(void); void timer0_comp2_callback(void); void GPIO_IRQHandler(void); #ifdef __cplusplus } #endif #endif /* BSP_PINE64_IRQ_H_ */ ================================================ FILE: source/Core/BSP/Pinecilv2/MemMang/heap_5.c ================================================ /* * FreeRTOS Kernel V10.4.1 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in * the Software without restriction, including without limitation the rights to * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of * the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * https://www.FreeRTOS.org * https://github.com/FreeRTOS * * 1 tab == 4 spaces! */ /* * A sample implementation of pvPortMalloc() that allows the heap to be defined * across multiple non-contigous blocks and combines (coalescences) adjacent * memory blocks as they are freed. * * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative * implementations, and the memory management pages of https://www.FreeRTOS.org * for more information. * * Usage notes: * * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc(). * pvPortMalloc() will be called if any task objects (tasks, queues, event * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be * called before any other objects are defined. * * vPortDefineHeapRegions() takes a single parameter. The parameter is an array * of HeapRegion_t structures. HeapRegion_t is defined in portable.h as * * typedef struct HeapRegion * { * uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap. * size_t xSizeInBytes; << Size of the block of memory. * } HeapRegion_t; * * The array is terminated using a NULL zero sized region definition, and the * memory regions defined in the array ***must*** appear in address order from * low address to high address. So the following is a valid example of how * to use the function. * * HeapRegion_t xHeapRegions[] = * { * { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000 * { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000 * { NULL, 0 } << Terminates the array. * }; * * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions(). * * Note 0x80000000 is the lower address so appears in the array first. * */ #include /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining * all the API functions to use the MPU wrappers. That should only be done when * task.h is included from an application file. */ #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE #include "FreeRTOS.h" #include "task.h" #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE #if (configSUPPORT_DYNAMIC_ALLOCATION == 0) #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 #endif /* Block sizes must not get too small. */ #define heapMINIMUM_BLOCK_SIZE ((size_t)(xHeapStructSize << 1)) /* Assumes 8bit bytes! */ #define heapBITS_PER_BYTE ((size_t)8) /* Define the linked list structure. This is used to link free blocks in order * of their memory address. */ typedef struct A_BLOCK_LINK { struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ size_t xBlockSize; /*<< The size of the free block. */ } BlockLink_t; /*-----------------------------------------------------------*/ /* * Inserts a block of memory that is being freed into the correct position in * the list of free memory blocks. The block being freed will be merged with * the block in front it and/or the block behind it if the memory blocks are * adjacent to each other. */ static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert); /*-----------------------------------------------------------*/ /* The size of the structure placed at the beginning of each allocated memory * block must by correctly byte aligned. */ static const size_t xHeapStructSize = (sizeof(BlockLink_t) + ((size_t)(portBYTE_ALIGNMENT - 1))) & ~((size_t)portBYTE_ALIGNMENT_MASK); /* Create a couple of list links to mark the start and end of the list. */ static BlockLink_t xStart, *pxEnd = NULL; /* Keeps track of the number of calls to allocate and free memory as well as the * number of free bytes remaining, but says nothing about fragmentation. */ static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; static size_t xNumberOfSuccessfulAllocations = 0; static size_t xNumberOfSuccessfulFrees = 0; /* Gets set to the top bit of an size_t type. When this bit in the xBlockSize * member of an BlockLink_t structure is set then the block belongs to the * application. When the bit is free the block is still part of the free heap * space. */ static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc(size_t xWantedSize) { BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; /* The heap must be initialised before the first call to * prvPortMalloc(). */ configASSERT(pxEnd); vTaskSuspendAll(); { /* Check the requested block size is not so large that the top bit is * set. The top bit of the block size member of the BlockLink_t structure * is used to determine who owns the block - the application or the * kernel, so it must be free. */ if ((xWantedSize & xBlockAllocatedBit) == 0) { /* The wanted size is increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ if (xWantedSize > 0) { xWantedSize += xHeapStructSize; /* Ensure that blocks are always aligned to the required number * of bytes. */ if ((xWantedSize & portBYTE_ALIGNMENT_MASK) != 0x00) { /* Byte alignment required. */ xWantedSize += (portBYTE_ALIGNMENT - (xWantedSize & portBYTE_ALIGNMENT_MASK)); } else { mtCOVERAGE_TEST_MARKER(); } } else { mtCOVERAGE_TEST_MARKER(); } if ((xWantedSize > 0) && (xWantedSize <= xFreeBytesRemaining)) { /* Traverse the list from the start (lowest address) block until * one of adequate size is found. */ pxPreviousBlock = &xStart; pxBlock = xStart.pxNextFreeBlock; while ((pxBlock->xBlockSize < xWantedSize) && (pxBlock->pxNextFreeBlock != NULL)) { pxPreviousBlock = pxBlock; pxBlock = pxBlock->pxNextFreeBlock; } /* If the end marker was reached then a block of adequate size * was not found. */ if (pxBlock != pxEnd) { /* Return the memory space pointed to - jumping over the * BlockLink_t structure at its start. */ pvReturn = (void *)(((uint8_t *)pxPreviousBlock->pxNextFreeBlock) + xHeapStructSize); /* This block is being returned for use so must be taken out * of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; /* If the block is larger than required it can be split into * two. */ if ((pxBlock->xBlockSize - xWantedSize) > heapMINIMUM_BLOCK_SIZE) { /* This block is to be split into two. Create a new * block following the number of bytes requested. The void * cast is used to prevent byte alignment warnings from the * compiler. */ pxNewBlockLink = (void *)(((uint8_t *)pxBlock) + xWantedSize); /* Calculate the sizes of two blocks split from the * single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList((pxNewBlockLink)); } else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; if (xFreeBytesRemaining < xMinimumEverFreeBytesRemaining) { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; } else { mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned * by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; pxBlock->pxNextFreeBlock = NULL; xNumberOfSuccessfulAllocations++; } else { mtCOVERAGE_TEST_MARKER(); } } else { mtCOVERAGE_TEST_MARKER(); } } else { mtCOVERAGE_TEST_MARKER(); } traceMALLOC(pvReturn, xWantedSize); } (void)xTaskResumeAll(); #if (configUSE_MALLOC_FAILED_HOOK == 1) { if (pvReturn == NULL) { extern void vApplicationMallocFailedHook(void); vApplicationMallocFailedHook(); } else { mtCOVERAGE_TEST_MARKER(); } } #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ return pvReturn; } /*-----------------------------------------------------------*/ void vPortFree(void *pv) { uint8_t *puc = (uint8_t *)pv; BlockLink_t *pxLink; if (pv != NULL) { /* The memory being freed will have an BlockLink_t structure immediately * before it. */ puc -= xHeapStructSize; /* This casting is to keep the compiler from issuing warnings. */ pxLink = (void *)puc; /* Check the block is actually allocated. */ configASSERT((pxLink->xBlockSize & xBlockAllocatedBit) != 0); configASSERT(pxLink->pxNextFreeBlock == NULL); if ((pxLink->xBlockSize & xBlockAllocatedBit) != 0) { if (pxLink->pxNextFreeBlock == NULL) { /* The block is being returned to the heap - it is no longer * allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; vTaskSuspendAll(); { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; traceFREE(pv, pxLink->xBlockSize); prvInsertBlockIntoFreeList(((BlockLink_t *)pxLink)); xNumberOfSuccessfulFrees++; } (void)xTaskResumeAll(); } else { mtCOVERAGE_TEST_MARKER(); } } else { mtCOVERAGE_TEST_MARKER(); } } } /*-----------------------------------------------------------*/ size_t xPortGetFreeHeapSize(void) { return xFreeBytesRemaining; } /*-----------------------------------------------------------*/ size_t xPortGetMinimumEverFreeHeapSize(void) { return xMinimumEverFreeBytesRemaining; } /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert) { BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address * than the block being inserted. */ for (pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock) { /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after * make a contiguous block of memory? */ puc = (uint8_t *)pxIterator; if ((puc + pxIterator->xBlockSize) == (uint8_t *)pxBlockToInsert) { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; pxBlockToInsert = pxIterator; } else { mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before * make a contiguous block of memory? */ puc = (uint8_t *)pxBlockToInsert; if ((puc + pxBlockToInsert->xBlockSize) == (uint8_t *)pxIterator->pxNextFreeBlock) { if (pxIterator->pxNextFreeBlock != pxEnd) { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } /* If the block being inserted plugged a gab, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ if (pxIterator != pxBlockToInsert) { pxIterator->pxNextFreeBlock = pxBlockToInsert; } else { mtCOVERAGE_TEST_MARKER(); } } /*-----------------------------------------------------------*/ void vPortDefineHeapRegions(const HeapRegion_t *const pxHeapRegions) { BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock; size_t xAlignedHeap; size_t xTotalRegionSize, xTotalHeapSize = 0; BaseType_t xDefinedRegions = 0; size_t xAddress; const HeapRegion_t *pxHeapRegion; /* Can only call once! */ configASSERT(pxEnd == NULL); pxHeapRegion = &(pxHeapRegions[xDefinedRegions]); while (pxHeapRegion->xSizeInBytes > 0) { xTotalRegionSize = pxHeapRegion->xSizeInBytes; /* Ensure the heap region starts on a correctly aligned boundary. */ xAddress = (size_t)pxHeapRegion->pucStartAddress; if ((xAddress & portBYTE_ALIGNMENT_MASK) != 0) { xAddress += (portBYTE_ALIGNMENT - 1); xAddress &= ~portBYTE_ALIGNMENT_MASK; /* Adjust the size for the bytes lost to alignment. */ xTotalRegionSize -= xAddress - (size_t)pxHeapRegion->pucStartAddress; } xAlignedHeap = xAddress; /* Set xStart if it has not already been set. */ if (xDefinedRegions == 0) { /* xStart is used to hold a pointer to the first item in the list of * free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = (BlockLink_t *)xAlignedHeap; xStart.xBlockSize = (size_t)0; } else { /* Should only get here if one region has already been added to the * heap. */ configASSERT(pxEnd != NULL); /* Check blocks are passed in with increasing start addresses. */ configASSERT(xAddress > (size_t)pxEnd); } /* Remember the location of the end marker in the previous region, if * any. */ pxPreviousFreeBlock = pxEnd; /* pxEnd is used to mark the end of the list of free blocks and is * inserted at the end of the region space. */ xAddress = xAlignedHeap + xTotalRegionSize; xAddress -= xHeapStructSize; xAddress &= ~portBYTE_ALIGNMENT_MASK; pxEnd = (BlockLink_t *)xAddress; pxEnd->xBlockSize = 0; pxEnd->pxNextFreeBlock = NULL; /* To start with there is a single free block in this region that is * sized to take up the entire heap region minus the space taken by the * free block structure. */ pxFirstFreeBlockInRegion = (BlockLink_t *)xAlignedHeap; pxFirstFreeBlockInRegion->xBlockSize = xAddress - (size_t)pxFirstFreeBlockInRegion; pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd; /* If this is not the first region that makes up the entire heap space * then link the previous region to this region. */ if (pxPreviousFreeBlock != NULL) { pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion; } xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize; /* Move onto the next HeapRegion_t structure. */ xDefinedRegions++; pxHeapRegion = &(pxHeapRegions[xDefinedRegions]); } xMinimumEverFreeBytesRemaining = xTotalHeapSize; xFreeBytesRemaining = xTotalHeapSize; /* Check something was actually defined before it is accessed. */ configASSERT(xTotalHeapSize); /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ((size_t)1) << ((sizeof(size_t) * heapBITS_PER_BYTE) - 1); } /*-----------------------------------------------------------*/ void vPortGetHeapStats(HeapStats_t *pxHeapStats) { BlockLink_t *pxBlock; size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ vTaskSuspendAll(); { pxBlock = xStart.pxNextFreeBlock; /* pxBlock will be NULL if the heap has not been initialised. The heap * is initialised automatically when the first allocation is made. */ if (pxBlock != NULL) { do { /* Increment the number of blocks and record the largest block seen * so far. */ xBlocks++; if (pxBlock->xBlockSize > xMaxSize) { xMaxSize = pxBlock->xBlockSize; } /* Heap five will have a zero sized block at the end of each * each region - the block is only used to link to the next * heap region so it not a real block. */ if (pxBlock->xBlockSize != 0) { if (pxBlock->xBlockSize < xMinSize) { xMinSize = pxBlock->xBlockSize; } } /* Move to the next block in the chain until the last block is * reached. */ pxBlock = pxBlock->pxNextFreeBlock; } while (pxBlock != pxEnd); } } (void)xTaskResumeAll(); pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; pxHeapStats->xNumberOfFreeBlocks = xBlocks; taskENTER_CRITICAL(); { pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; } taskEXIT_CRITICAL(); } ================================================ FILE: source/Core/BSP/Pinecilv2/NOTES.md ================================================ # Notes on RISC-V ## Pinmap | Pin Number | Name | Function | Notes | | ---------- | ---- | ---------------- | ----------- | | 17 | PB2 | BOOT2 | Pulldown | | 32 | | IMU INT 1 | N/A | | 30 | | IMU INT 2 | N/A | | | PA4 | Handle Temp | ADC Input ? | | | PA1 | Tip Temp | ADC Input ? | | | PB1 | B Button | Active High | | | PB0 | A Button | Active High | | | PA11 | USB D- | - | | | PA12 | USB D+ | - | | | PA6 | Tip PWM Out | - | | | PA0 | Input DC V Sense | ADC Input ? | | | PA9 | OLED Reset | | | | PB7 | SDA | I2C0_SDA | | | PB6 | SCL | I2C0_SCL | ## ADC Configuration For now running in matching mode for TS100 - X channels DMA in background - Sample tip using "Intereted" channels using TIMER 0,1,3 TRGO or timer0,1,2 channels - Using just 12 bit mode for now and move to hardware oversampling later - use DMA for normal samples and 4x16 bit regs for tip temp - It has dual ADC's so run them in pair mode ## Timers ### Timer 2 Timer 2 CH0 is tip drive PWM out. This is fixed at 50% duty cycle and used via the cap to turn on the heater tip. This should toggle relatively quickly. ================================================ FILE: source/Core/BSP/Pinecilv2/Pins.h ================================================ /* * Pins.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_PINE64_PINS_H_ #define BSP_PINE64_PINS_H_ #include "bl702_adc.h" #include "bl702_pwm.h" #include "hal_gpio.h" #define KEY_B_Pin GPIO_PIN_28 #define TMP36_INPUT_Pin GPIO_PIN_20 #define TMP36_ADC_CHANNEL ADC_CHAN10 #define TIP_TEMP_Pin GPIO_PIN_19 #define TIP_TEMP_ADC_CHANNEL ADC_CHAN9 #define TIP_RESISTANCE_SENSE GPIO_PIN_24 #define VIN_Pin GPIO_PIN_18 #define VIN_ADC_CHANNEL ADC_CHAN8 #define OLED_RESET_Pin GPIO_PIN_3 #define KEY_A_Pin GPIO_PIN_25 #define PWM_Out_Pin GPIO_PIN_21 #define PWM_Channel PWM_CH1 #define SCL_Pin GPIO_PIN_11 #define SDA_Pin GPIO_PIN_10 #define USB_DM_Pin GPIO_PIN_8 #define QC_DP_LOW_Pin GPIO_PIN_5 // LOW = low resistance, HIGH = high resistance #define QC_DM_LOW_Pin GPIO_PIN_4 #define QC_DM_HIGH_Pin GPIO_PIN_6 #define FUSB302_IRQ_Pin GPIO_PIN_16 #define FUSB302_IRQ_GLB_Pin GLB_GPIO_PIN_16 // uart #define UART_TX_Pin GPIO_PIN_22 #define UART_RX_Pin GPIO_PIN_23 #if defined(WS2812B_ENABLE) // WS2812B mod using TP10 #define WS2812B_Pin GPIO_PIN_12 // WS2812B mod using TP9 is doable too, but harder to reach. Thanks @t3chguy //#define WS2812B_Pin GPIO_PIN_14 #endif #endif /* BSP_PINE64_PINS_H_ */ ================================================ FILE: source/Core/BSP/Pinecilv2/Power.cpp ================================================ #include "BSP.h" #include "BSP_Power.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #include "USBPD.h" #include "configuration.h" void power_check() { #ifdef POW_PD // Cant start QC until either PD works or fails if (!USBPowerDelivery::negotiationComplete()) { return; } if (USBPowerDelivery::negotiationHasWorked()) { return; // We are using PD } #endif #ifdef POW_QC QC_resync(); #endif } bool getIsPoweredByDCIN() { #ifdef POW_PD if (!USBPowerDelivery::negotiationComplete()) { return false; // We are assuming not dc while negotiating } if (USBPowerDelivery::negotiationHasWorked()) { return false; // We are using PD } #endif #ifdef POW_QC if (hasQCNegotiated()) { return false; // We are using QC } #endif return true; } ================================================ FILE: source/Core/BSP/Pinecilv2/QC_GPIO.cpp ================================================ /* * QC.c * * Created on: 29 May 2020 * Author: Ralim */ #include "BSP.h" #include "Pins.h" #include "QC3.h" #include "Settings.h" #ifdef POW_QC void QC_DPlusZero_Six() { // pull down D+ gpio_write(QC_DP_LOW_Pin, 0); } void QC_DNegZero_Six() { gpio_write(QC_DM_HIGH_Pin, 0); gpio_write(QC_DM_LOW_Pin, 1); } void QC_DPlusThree_Three() { // pull up D+ gpio_write(QC_DP_LOW_Pin, 1); } void QC_DNegThree_Three() { gpio_write(QC_DM_LOW_Pin, 1); gpio_write(QC_DM_HIGH_Pin, 1); } void QC_DM_PullDown() { // Turn on pulldown on D- gpio_set_mode(USB_DM_Pin, GPIO_INPUT_PD_MODE); gpio_set_mode(QC_DM_LOW_Pin, GPIO_INPUT_PD_MODE); gpio_set_mode(QC_DM_HIGH_Pin, GPIO_INPUT_PD_MODE); } void QC_DM_No_PullDown() { // Turn off pulldown on d- gpio_set_mode(USB_DM_Pin, GPIO_INPUT_MODE); } void QC_Init_GPIO() { // Setup any GPIO into the right states for QC // D+ pulldown as output gpio_set_mode(QC_DP_LOW_Pin, GPIO_OUTPUT_MODE); gpio_write(QC_DP_LOW_Pin, 0); // Make two D- pins floating gpio_set_mode(USB_DM_Pin, GPIO_INPUT_MODE); gpio_set_mode(QC_DM_LOW_Pin, GPIO_INPUT_MODE); gpio_set_mode(QC_DM_HIGH_Pin, GPIO_INPUT_MODE); } void QC_Post_Probe_En() { // Make two D- pins outputs gpio_set_mode(QC_DM_LOW_Pin, GPIO_OUTPUT_MODE); gpio_set_mode(QC_DM_HIGH_Pin, GPIO_OUTPUT_MODE); } uint8_t QC_DM_PulledDown() { return gpio_read(USB_DM_Pin) == 0; } #endif void QC_resync() { #ifdef POW_QC seekQC(getSettingValue(SettingsOptions::QCIdealVoltage), getSettingValue(SettingsOptions::VoltageDiv)); // Run the QC seek again if we have drifted too much #endif } ================================================ FILE: source/Core/BSP/Pinecilv2/README.md ================================================ # BSP section for Pinecil v2 This folder contains the hardware abstractions required for the Pinecil V2. A RISC-V based soldering iron. ================================================ FILE: source/Core/BSP/Pinecilv2/Setup.cpp ================================================ /* * Setup.c * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #include "Setup.h" #include "BSP.h" #include "Debug.h" #include "FreeRTOSConfig.h" #include "IRQ.h" #include "Pins.h" #include "bl702_dma.h" #include "bl702_sec_eng.h" #include "history.hpp" #include #define ADC_NORM_SAMPLES 16 #define ADC_FILTER_LEN 4 uint16_t ADCReadings[ADC_NORM_SAMPLES]; // room for 32 lots of the pair of readings // Heap extern uint8_t _heap_start; extern uint8_t _heap_size; // @suppress("Type cannot be resolved") static HeapRegion_t xHeapRegions[] = { {&_heap_start, (unsigned int)&_heap_size}, { NULL, 0}, /* Terminates the array. */ { NULL, 0} /* Terminates the array. */ }; // Functions void setup_timer_scheduler(void); void setup_pwm(void); void setup_adc(void); void hardware_init() { vPortDefineHeapRegions(xHeapRegions); HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL); // Set capcode { uint32_t tmpVal = 0; tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 33); tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 33); BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal); } Sec_Eng_Trng_Enable(); gpio_set_mode(OLED_RESET_Pin, GPIO_OUTPUT_MODE); gpio_set_mode(KEY_A_Pin, GPIO_INPUT_PD_MODE); gpio_set_mode(KEY_B_Pin, GPIO_INPUT_PD_MODE); gpio_set_mode(TMP36_INPUT_Pin, GPIO_HZ_MODE); gpio_set_mode(TIP_TEMP_Pin, GPIO_HZ_MODE); gpio_set_mode(VIN_Pin, GPIO_HZ_MODE); gpio_set_mode(TIP_RESISTANCE_SENSE, GPIO_OUTPUT_MODE); gpio_write(TIP_RESISTANCE_SENSE, 0); MSG((char *)"Pine64 Pinecilv2 Starting\r\n"); setup_timer_scheduler(); setup_adc(); setup_pwm(); I2C_SetSclSync(I2C0_ID, 1); I2C_SetDeglitchCount(I2C0_ID, 1); // Turn on de-glitch // Note on I2C clock rate @ 100Khz the screen update == 20ms which is too long for USB-PD to work // 200kHz and above works I2C_ClockSet(I2C0_ID, 300000); // Sets clock to around 25 kHz less than set here TIMER_SetCompValue(TIMER_CH0, TIMER_COMP_ID_0, 0); } void setup_pwm(void) { // Setup PWM we use for driving the tip PWM_CH_CFG_Type cfg = { PWM_Channel, // channel PWM_CLK_XCLK, // Clock PWM_STOP_ABRUPT, // Stop mode PWM_POL_NORMAL, // Normal Polarity 60, // Clock Div 100, // Period 0, // Thres 1 - start at beginning 50, // Thres 2 - turn off at 50% 0, // Interrupt pulse count }; PWM_Channel_Init(&cfg); PWM_Channel_Disable(PWM_Channel); } const ADC_Chan_Type adc_tip_pos_chans[] = {TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, TMP36_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL, VIN_ADC_CHANNEL, TIP_TEMP_ADC_CHANNEL}; const ADC_Chan_Type adc_tip_neg_chans[] = {ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND, ADC_CHAN_GND}; static_assert(sizeof(adc_tip_pos_chans) == sizeof(adc_tip_neg_chans)); void setup_adc(void) { // ADC_CFG_Type adc_cfg = {}; ADC_FIFO_Cfg_Type adc_fifo_cfg = {}; // Please also see PR #1529 for even more context /* A note on ADC settings The bl70x ADC seems to be very sensitive to various analog settings. It has been a challenge to determine what is the most correct way to configure it in order to get accurate readings that can be transformed into millivolts, for accurate measurements. This latest set of ADC parameters, matches the latest configuration from the upstream bl_mcu_sdk repository from commit hash: 9e189b69cbc0a75ffa170f600a28820848d56432 except for one difference. (Note: bl_mcu_sdk has been heavily refactored since it has been imported into IronOS.) You can make it match exactly by defining ENABLE_MIC2_DIFF, see the code #ifdef ENABLE_MIC2_DIFF below. I have decided to not apply this change because it appeared to make the lower end of the input less precise. Note that this configuration uses an ADC trimming value that is stored in the Efuse of the bl70x chip. The actual reading is divided by this "coe" value. We have found the following coe values on 3 different chips: 0.9629, 0.9438, 0.9876 Additional note for posterity: PGA = programmable gain amplifier. We would have expected to achieve the highest accuracy by disabling this amplifier, however we found that not to be the case, and in almost all cases we have found that there is a scaling error compared to the ideal Vref. The only other configuration we have found to be accurate was if we had: PGA disabled + Vref=2V + biasSel=AON + without trimming from the efuse. But we can't use it because a Vref=2V limits the higher end of temperature and voltage readings. Also we don't know if this other configuration is really accurate on all chips, or only happened to be accurate on the one chip on which it has been found. */ adc_cfg.clkDiv = ADC_CLK_DIV_4; adc_cfg.vref = ADC_VREF_3P2V; adc_cfg.resWidth = ADC_DATA_WIDTH_14_WITH_16_AVERAGE; adc_cfg.inputMode = ADC_INPUT_SINGLE_END; adc_cfg.v18Sel = ADC_V18_SEL_1P82V; adc_cfg.v11Sel = ADC_V11_SEL_1P1V; adc_cfg.gain1 = ADC_PGA_GAIN_1; adc_cfg.gain2 = ADC_PGA_GAIN_1; adc_cfg.chopMode = ADC_CHOP_MOD_AZ_PGA_ON; adc_cfg.biasSel = ADC_BIAS_SEL_MAIN_BANDGAP; adc_cfg.vcm = ADC_PGA_VCM_1P2V; adc_cfg.offsetCalibEn = DISABLE; adc_cfg.offsetCalibVal = 0; ADC_Disable(); ADC_Enable(); ADC_Reset(); ADC_Init(&adc_cfg); #ifdef ENABLE_MIC2_DIFF // This is the change that enables MIC2_DIFF, for now deciding not to enable it, since it seems to make results slightly worse { uint32_t tmpVal; tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); } #endif #if 1 // this sets the CVSP field (ADC conversion speed) { uint32_t regCfg2; regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); } #endif adc_fifo_cfg.dmaEn = DISABLE; adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_1; ADC_FIFO_Cfg(&adc_fifo_cfg); ADC_MIC_Bias_Disable(); ADC_Tsen_Disable(); ADC_Gain_Trim(); ADC_Stop(); ADC_FIFO_Clear(); ADC_Scan_Channel_Config(adc_tip_pos_chans, adc_tip_neg_chans, sizeof(adc_tip_pos_chans) / sizeof(ADC_Chan_Type), DISABLE); } void setup_timer_scheduler() { TIMER_Disable(TIMER_CH0); TIMER_CFG_Type cfg = { TIMER_CH0, // Channel TIMER_CLKSRC_32K, // Clock source TIMER_PRELOAD_TRIG_COMP2, // Trigger; reset after trigger 0 TIMER_COUNT_PRELOAD, // Counter mode 22, // Clock div (uint16_t)(powerPWM), // CH0 compare (pwm out) (uint16_t)(powerPWM + holdoffTicks), // CH1 compare (adc) (uint16_t)(powerPWM + holdoffTicks + tempMeasureTicks), // CH2 compare end of cycle 0, // Preload, copied to counter on trigger of comp2 }; TIMER_Init(&cfg); Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_0, timer0_comp0_callback); Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_1, timer0_comp1_callback); Timer_Int_Callback_Install(TIMER_CH0, TIMER_INT_COMP_2, timer0_comp2_callback); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_0); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_1); TIMER_ClearIntStatus(TIMER_CH0, TIMER_COMP_ID_2); TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_0, UNMASK); TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_1, UNMASK); TIMER_IntMask(TIMER_CH0, TIMER_INT_COMP_2, UNMASK); CPU_Interrupt_Enable(TIMER_CH0_IRQn); TIMER_Enable(TIMER_CH0); } void setupFUSBIRQ() { gpio_set_mode(FUSB302_IRQ_Pin, GPIO_SYNC_FALLING_TRIGER_INT_MODE); CPU_Interrupt_Disable(GPIO_INT0_IRQn); Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQHandler); CPU_Interrupt_Enable(GPIO_INT0_IRQn); gpio_irq_enable(FUSB302_IRQ_Pin, ENABLE); } ================================================ FILE: source/Core/BSP/Pinecilv2/Setup.h ================================================ /* * Setup.h * * Created on: 29Aug.,2017 * Author: Ben V. Brown */ #ifndef PINE_SETUP_H_ #define PINE_SETUP_H_ #include extern "C" { #include "bflb_platform.h" #include "bl702_adc.h" #include "bl702_common.h" #include "bl702_glb.h" #include "bl702_i2c.h" #include "bl702_pwm.h" #include "bl702_timer.h" #include "hal_adc.h" } #ifdef __cplusplus extern "C" { #endif uint16_t getADC(uint8_t channel); void hardware_init(); uint16_t getADCHandleTemp(uint8_t sample); uint16_t getADCVin(uint8_t sample); #ifdef __cplusplus } #endif void setupFUSBIRQ(); extern uint8_t holdoffTicks; extern uint8_t tempMeasureTicks; #endif /* PINE_SETUP_H_ */ ================================================ FILE: source/Core/BSP/Pinecilv2/ThermoModel.cpp ================================================ /* * ThermoModel.cpp * * Created on: 1 May 2021 * Author: Ralim */ #include "TipThermoModel.h" #include "Utils.hpp" #include "configuration.h" #ifdef TEMP_uV_LOOKUP_HAKKO const int32_t uVtoDegC[] = { // // uv -> temp in C 0, 0, // 266, 10, // 522, 20, // 770, 30, // 1010, 40, // 1244, 50, // 1473, 60, // 1697, 70, // 1917, 80, // 2135, 90, // 2351, 100, // 2566, 110, // 2780, 120, // 2994, 130, // 3209, 140, // 3426, 150, // 3644, 160, // 3865, 170, // 4088, 180, // 4314, 190, // 4544, 200, // 4777, 210, // 5014, 220, // 5255, 230, // 5500, 240, // 5750, 250, // 6003, 260, // 6261, 270, // 6523, 280, // 6789, 290, // 7059, 300, // 7332, 310, // 7609, 320, // 7889, 330, // 8171, 340, // 8456, 350, // 8742, 360, // 9030, 370, // 9319, 380, // 9607, 390, // 9896, 400, // 10183, 410, // 10468, 420, // 10750, 430, // 11029, 440, // 11304, 450, // 11573, 460, // 11835, 470, // 12091, 480, // 12337, 490, // 12575, 500, // }; #endif const int uVtoDegCItems = sizeof(uVtoDegC) / (2 * sizeof(int32_t)); TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return Utils::InterpolateLookupTable(uVtoDegC, uVtoDegCItems, tipuVDelta); } ================================================ FILE: source/Core/BSP/Pinecilv2/UnitSettings.h ================================================ /* * UnitSettings.h * * Created on: 29 May 2020 * Author: Ralim */ #ifndef BSP_MAGIC_UNITSETTINGS_H_ #define BSP_MAGIC_UNITSETTINGS_H_ #endif /* BSP_MAGIC_UNITSETTINGS_H_ */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl702_config.h ================================================ /** * @file bl602_config.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __BL702_CONFIG_H__ #define __BL702_CONFIG_H__ #include "clock_config.h" #include "peripheral_config.h" #include "pinmux_config.h" #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_irq.c ================================================ #include "bl_irq.h" extern pFunc __Interrupt_Handlers[IRQn_LAST]; void bl_irq_enable(unsigned int source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; } void bl_irq_disable(unsigned int source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; } void bl_irq_pending_set(unsigned int source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; } void bl_irq_pending_clear(unsigned int source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; } void bl_irq_register(int irqnum, void *handler) { if (irqnum < IRQn_LAST) { __Interrupt_Handlers[irqnum] = handler; } } void bl_irq_unregister(int irqnum, void *handler) { if (irqnum < IRQn_LAST) { __Interrupt_Handlers[irqnum] = NULL; } } void bl_irq_handler_get(int irqnum, void **handler) { if (irqnum < IRQn_LAST) { *handler = __Interrupt_Handlers[irqnum]; } } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_irq.h ================================================ #ifndef __BL_IRQ_H__ #define __BL_IRQ_H__ #include "bl702_glb.h" #include "risc-v/Core/Include/clic.h" #include "risc-v/Core/Include/riscv_encoding.h" void bl_irq_enable(unsigned int source); void bl_irq_disable(unsigned int source); void bl_irq_pending_set(unsigned int source); void bl_irq_pending_clear(unsigned int source); void bl_irq_register(int irqnum, void *handler); void bl_irq_unregister(int irqnum, void *handler); void bl_irq_handler_get(int irqnum, void **handler); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/LICENSE ================================================ Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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We also recommend that a file or class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. Copyright [2020] [BOUFFALO LAB (NANJING) CO., LTD.] Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/ReleaseNotes ================================================ bl mcu sdk Release Notes ---------------------------- 此文件包含 bl mcu sdk 软件开发包的发行说明。 每个版本的文字说明与发布时的说明保持一致（可能会有错别字的勘误）。 bl mcu sdk Release V1.4.4 ---------------------------- 新增功能说明： 1. 增加 adc dma, uart dma p2p, at client, tensorflow vww demo 2. boot2 更新 3. 删除 timer basic 和 dac_from_flash demo 4. 更新 bflb flash tool 到 1.7.1 5. ble lib 更新，使用 t-head 10.2 工具链构建（小于此工具链版本编译将报错） 修复问题说明： 1. 修正 dma 相关命令宏，重命名 DMA_BURST_xBYTE 防止误导 2. 修正 readme 中相关编译命令 bl mcu sdk Release V1.4.3 ---------------------------- 新增功能说明： 1. 增加 pikascript 和 mac154 组件 2. 增加 ble pds 的 demo 3. doc 缓存文件移出 4. 增加 cklink 和 jlink 在 eclipse 中的调试 修复问题说明： 1. driver 更新 2. Os to O2 3. uart sig 选定功能后，对与其他 sig 使用相同功能进行调整 bl mcu sdk Release V1.4.2 ---------------------------- 新增功能说明： 1. 重构 dac、dma 驱动，更新 dac、dma doc 2. 新增 arch_ffsll、arch_ctzll、arch_clzll 等函数 3. 优化 usb 协议栈 log 信息，msc 新增 sense code for requestSense command 修复问题说明： 1. 补充完整 xxx_close 函数，复位相关寄存器 2. 删除 drivers 下头文件部分依赖 3. 优化 usb 驱动中 端点0 设置 ack 的位置（放置中断中），防止重复设置。 bl mcu sdk Release V1.4.1 ---------------------------- 新增功能说明： 1. 新增 aes、ble pds31、freertos tickless、audio cube demo 2. 新增 usb 同步传输中断方式 3. 新增 lwip 组件以及对应 emac demo 4. 新增 pds31 快速唤醒功能 5. 文档更新，包含：flash、usb、fatfs、pm、emac、ble 修复问题说明： 1. pwm demo 文档中分频值修正 2. 修正 mtimer 获取 div 函数 3. 修正 dma 链表配置，当传输长度为 4095 时会配置错误，优化 if 判断 4. switch 禁用跳表选项 ，C flag 中添加 -fno-jump-tables 5. 部分 cdk 工程增加 syscall.c，对系统函数重定向，否则会进 M mode 异常 6. 修正 gpio func macro value，该值对配置 gpio 为 uart 时会有问题，出现覆盖问题 7. 补全 calloc 函数，浮点打印会使用 8. 从驱动库文件移除 bflb_platform.h 文件，减少只使用 std drv 时的依赖项 bl mcu sdk Release V1.4.0 ---------------------------- 新增功能说明： 1. 新增 mbedtls、rt-thread、nmsis 组件,新增 rt-thread msh、mfcc、nn、dsp demo 2. 新增 flash 模拟u盘升级、 c++、adc 中断读取、boot2 usb iap、prng demo 3. 修改 makefile 调用 cmake 执行命令 4. usb 协议栈新增 usb hs 功能 5. freertos 新增 tickless 功能 6. 重构芯片驱动的公用头文件包含、删除 flash 的相关 api 7. cdk 工程源文件更新 8. fatfs port接口新增 flash 读写（usb msc中可以使用） 9. 使能所有外设的 BSP_USING_XXX 宏 10. ble 新增 oad 功能，带加密功能 11. mmheap 组件更新，链表式的内存管理减少了 ram 的使用，但是会增加 malloc 和 free 时间 修复问题说明： 1. 修复 ble 在 pc上连接失败的问题，修改 capcode 可以解决 2. fatfs 中 FS_MAX_SS 参数需要适配其他种类的扇区，修复多个驱动注册到 fatfs 时，参数覆盖的 bug 3. bl706_avb 文件删除其他 demo 的 pinmux，只留 camera + lcd 的配置，同理 bl706_iot 文件只留 i2s + usb + adc + pwm 配置 4. 修正 adc_read 函数，只读取了一个 fifo 数值，影响 adc 采样效率 5. 修正 usb_dc_ep_set_stall 在 端点 stall 时没有开启下一次的端点接收的问题 bl mcu sdk Release V1.3.0 ---------------------------- 新增功能说明： 1. 新增 acomp、rtc、boot2、wdt、pm hal driver 和 demo 2. 新增 romfs demo、usb 麦克风和扬声器双声道 demo、带 tinyjpeg 组件的 spi lcd 显示 demo 3. 重构 boot2_iap demo，统一接口 4. 使能 romapi，减少 codesize 5. 新增 flash 自动识别和配置功能，适配不同的 flash 芯片 6. 重构 mcu lcd 驱动层，适配多种 mcu lcd 驱动 7. 新增 ssd1306 spi 和 i2c 驱动，新增 ws2812 、wm8978 驱动 8. shell 新增颜色显示和自定义打印接口（使用各种终端工具可以查看） 9. bl602 和 bl702 驱动库相关更新 10. 新增外部 cmake 工程编译方式，从而让 sdk 作为 submodule 使用 11. ld 文件的更新 12. ble lib 文件更新（需要使用最新的 toolchain（sifive）才能编译 ble demo） 修复问题说明： 1. 修复 eclipse openocd 调试时，openocd 版本太低导致无法调试 2. case 运行异常时，需要添加死循环 3. 驱动库的一些 bug fix 4. 开关外设中断的重名名 5. fix 重复定义的宏带来的 warning bl mcu sdk Release V1.2.6 ---------------------------- 新增功能说明： 1. 重构 board 系统目录结构 2. 删除 SUPPORT_XXX 功能，改成 cmake 自动识别组件库并参与编译，识别参数为 TARGET_REQUIRED_LIBS 3. 删除 device_register 中 flag 选项 4. 重构 timer hal 层, clock tree 和 demo 5. 添加 自动识别内外部 flash 并切换引脚功能 6. 添加 2线 flash 下载支持 7. 默认使能 cpu 浮点支持（非打印浮点支持） 8. 添加 bl702 qfn32 的 board 文件 9. 添加 boot2 hal 封装层 10. 添加 pid 算法 11. 添加 qdec hal 和 demo 修复问题说明： 1. 修复 开关全局中断嵌套带来的问题 2. 修复 使用 shell 功能时编译报错 3. memcpy 改用 romapi 4. 修复 cdk 中编译 ble demo 编译报错，未添加 board 支持 5. 修复 pwm demo 相关宏书写错误 6. 修复 std 和 hal 中 switch case 返回的一些 bug 7. cdk 相关 demo 改用 bl706_iot board 8. 修改 keyscan 默认时钟和分频 bl mcu sdk Release V1.2.5 ---------------------------- 新增功能说明： 1. 添加 tensorflow lite 支持 2. gpio_set_mode 添加高阻模式 3. 添加 keyscan hal 驱动 4. 新增 shell 文件系统 5. 更新 clock tree 宏定义、更新 board.c 中 pinmux 初始化配置 6. es8388 驱动增加双通道支持 7. il9341 增加字库，支持大字号显示 修复问题说明： 1. 修复 usb msc 中 interface num 为 0 2. 修复 uart 和 spi 开关 dma 时未设置 oflag 状态 3. 修改 CPU_ID 默认值，当不使用多核时默认为 none 4. 修复 adc 浮点输出问题 5. 修复 hal pwm 相关宏书写错误 bl mcu sdk Release V1.2.4 ---------------------------- 新增功能说明： 1. 增加部分 math 库函数对 arm dsp api 的兼容，以及优化 math 库效率 2. 增加 bl702 adc、camera 中断，重定义 clock tree 的相关宏， 3. 删除 GPIO32-GPIO37，更新 GPIO 初始化和读写函数，更新 sf flash 引脚初始化 4. 增加 i2s 双通道支持 5. 增加 adc、pwm、camera 相关 api 6. 增加 camera pingpong buffer case 7. cdk 工程更新 8. 更新 openocd cfg 文件，适配 openocd 0.11 版本 修复问题说明： 1. 对 pwm readme 说明修改 2. 修复 hal_usb 中对端点 0 状态的判断逻辑 3. 修复 flash 擦除扇区时多擦除扇区的问题 4. ble、lvgl、usb、boot2iap、adc 相关 demo 的修改 bl mcu sdk Release V1.2.3 ---------------------------- 新增功能说明： 1. 增加 case 输出成功和失败的 log 提示 2. 更新 cdk 工程，使用 minilibc 替代本地 libc 3. 更新 usb api 及其他文档说明 修复问题说明： 1. 修改 bl702_flash.ld 文件中 ram 的实际大小 2. 修复 main 函数返回时一直重入的问题 3. 删除 hal driver 中不需要的内容 4. 修复 cdk 工程中编译 camera case 存在的问题 bl mcu sdk Release V1.2.2 ---------------------------- 新增功能说明： 1. 新增 pwm 驱动 dc motor 和 step motor、dht11、custom hid 、shell demo 2. 为所有的 examples 添加 cdk 工程 3. 为 cdk 工程添加 openocd 支持 4. 更新文档 5. 使用 clang-format 格式化代码 修复问题说明： 1. 修复 __riscv_float_abi_single 未定义带来的 warning 2. 修改 bl702_flash.ld 中 heap 的 分配方式 3. 更新 shell 组件，添加使用时删除中间字符的功能 bl mcu sdk Release V1.2.1 ---------------------------- 新增功能说明： 1. 新增 readme for demo command line build 2. 更新 cmake 运行顺序 3. 更新 cdk flashloader 和 openocd cfg 4. 更新文档 修复问题说明： 1. 修复 board.c 中 ADC 的引脚初始化 2. 修复 ble 静态库依赖问题 bl mcu sdk Release V1.2.0 ---------------------------- 新增功能说明： 1. 新增 xz、ble 组件 2. usb_stack 中新增 usb video、hid、audio 驱动 3. 新增 bl602 driver 和 bl602_iot board 4. 为 examples 补全 cdk 工程 5. 新增 ble、psram、camera、boot2_iap、emac、usb_video、usb_audio、usb_hid、gpio_int、pwm_it、flash读写、lowpower、pka、systick、timer demo 6. 更新 flash Tools 7. 更新 cmake 文件 8. 更新 mtimer 时钟频率为1M，便于计算 9. 文档更新 修复问题说明： 1. 修复若干已知问题 bl mcu sdk Release V1.1.0 ---------------------------- 新增功能说明： 1. 新增 lvgl 组件以及基本 demo； 2. 新增 freertos 702 port 以及基本 demo； 3. 新增 usb 转串口标准驱动 demo，支持博流自定义 DTR、RTS 流控协议； 4. 文件系统添加命令行功能； 5. hal 层添加强转宏，从而用户可以在程序内修改； 修复问题说明： 1. 修正 usb 设备描述符初始化宏，添加协议类代码初始化； 2. 修复 hal 层驱动。 bl mcu sdk Release V1.0.0 ---------------------------- 初始化项目。该项目基于 cmake 构建，包含 bl702/bl704/bl706 系列 mcu 底层驱动、基本外设例程、common 驱动以及第三方组件。 支持 bl706_avb、bl706_iot 开发板的开发工作； 该项目也支持使用 CDK、eclipse 编译、烧写、调试代码； 该项目中还包含烧录工具、调试脚本、flash 算法文件以及构建 cmake 需要的一些工具。 ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.c ================================================ /** * @file bflb_platform.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "bflb_platform.h" #include "drv_mmheap.h" #include "hal_common.h" #include "hal_flash.h" #include "hal_mtimer.h" #include "hal_uart.h" #include "ring_buffer.h" extern uint32_t __HeapBase; extern uint32_t __HeapLimit; static uint8_t uart_dbg_disable = 0; struct heap_info mmheap_root; static struct heap_region system_mmheap[] = { {NULL, 0}, {NULL, 0}, /* Terminates the array. */ }; __WEAK__ void board_init(void) {} __WEAK__ enum uart_index_type board_get_debug_uart_index(void) { return 0; } void bl_show_flashinfo(void) { SPI_Flash_Cfg_Type flashCfg; uint8_t *pFlashCfg = NULL; uint32_t flashCfgLen = 0; uint32_t flashJedecId = 0; flashJedecId = flash_get_jedecid(); flash_get_cfg(&pFlashCfg, &flashCfgLen); arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen); MSG("show flash cfg:\r\n"); MSG("jedec id 0x%06X\r\n", flashJedecId); MSG("mid 0x%02X\r\n", flashCfg.mid); MSG("iomode 0x%02X\r\n", flashCfg.ioMode); MSG("clk delay 0x%02X\r\n", flashCfg.clkDelay); MSG("clk invert 0x%02X\r\n", flashCfg.clkInvert); MSG("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); MSG("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); MSG("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); MSG("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); MSG("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); MSG("cread support 0x%02X\r\n", flashCfg.cReadSupport); MSG("cread code 0x%02X\r\n", flashCfg.cReadMode); MSG("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); MSG("-------------------\r\n"); } void bflb_platform_init(uint32_t baudrate) { // static uint8_t initialized = 0; BL_Err_Type ret = ERROR; cpu_global_irq_disable(); ret = flash_init(); if (ret != SUCCESS) { MSG("flash init fail!!!\r\n"); } board_init(); if (!uart_dbg_disable) { uart_register(board_get_debug_uart_index(), "debug_log"); struct device *uart = device_find("debug_log"); if (uart) { device_open(uart, DEVICE_OFLAG_STREAM_TX | DEVICE_OFLAG_INT_RX); device_set_callback(uart, NULL); device_control(uart, DEVICE_CTRL_CLR_INT, (void *)(UART_RX_FIFO_IT)); } } static bool initialized = false; if (!initialized) { system_mmheap[0].addr = (uint8_t *)&__HeapBase; system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); if (system_mmheap[0].mem_size > 0) { mmheap_init(&mmheap_root, system_mmheap); } MSG("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024); initialized = 1; if (ret != SUCCESS) { MSG("flash init fail!!!\r\n"); } bl_show_flashinfo(); } MSG("Enable IRQ's\r\n"); cpu_global_irq_enable(); } #if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) static uint8_t eflash_loader_logbuf[1024] __attribute__((section(".system_ram_noinit"))); static uint32_t log_len = 0; uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen) { uint32_t len = log_len; if (len > maxlen) { len = maxlen; } memcpy(data, eflash_loader_logbuf, len); return len; } #endif void bflb_platform_printf(char *fmt, ...) { struct device *uart; char print_buf[128]; va_list ap; if (!uart_dbg_disable) { va_start(ap, fmt); vsnprintf(print_buf, sizeof(print_buf) - 1, fmt, ap); va_end(ap); #if ((defined BOOTROM) || (defined BFLB_EFLASH_LOADER)) uint32_t len = strlen(print_buf); if (log_len + len < sizeof(eflash_loader_logbuf)) { memcpy(eflash_loader_logbuf + log_len, print_buf, len); log_len += len; } #endif uart = device_find("debug_log"); device_write(uart, 0, (uint8_t *)print_buf, strlen(print_buf)); } } void bflb_platform_print_set(uint8_t disable) { uart_dbg_disable = disable; } uint8_t bflb_platform_print_get(void) { return uart_dbg_disable; } void bflb_platform_deinit(void) { if (!uart_dbg_disable) { struct device *uart = device_find("debug_log"); if (uart) { device_close(uart); device_unregister("debug_log"); } } } void bflb_platform_dump(uint8_t *data, uint32_t len) { uint32_t i = 0; if (!uart_dbg_disable) { for (i = 0; i < len; i++) { if (i % 16 == 0) { bflb_platform_printf("\r\n"); } bflb_platform_printf("%02x ", data[i]); } bflb_platform_printf("\r\n"); } } void bflb_platform_reg_dump(uint32_t addr) { bflb_platform_printf("%08x[31:0]=%08x\r\n", addr, *(volatile uint32_t *)(addr)); } void bflb_platform_init_time() {} void bflb_platform_deinit_time() {} void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)) { mtimer_set_alarm_time(time, interruptFun); } void bflb_platform_clear_time() {} void bflb_platform_start_time() {} void bflb_platform_stop_time() {} uint64_t bflb_platform_get_time_ms() { return mtimer_get_time_ms(); } uint64_t bflb_platform_get_time_us() { return mtimer_get_time_us(); } void bflb_platform_delay_ms(uint32_t ms) { mtimer_delay_ms(ms); } void bflb_platform_delay_us(uint32_t us) { mtimer_delay_us(us); } void bflb_print_device_list(void) { struct device *dev; dlist_t *node; uint8_t device_index = 0; MSG("Device List Print\r\n"); dlist_for_each(node, device_get_list_header()) { dev = dlist_entry(node, struct device, list); MSG("Index %d\r\nDevice Name = %s \r\n", device_index, dev->name); switch (dev->type) { case DEVICE_CLASS_GPIO: MSG("Device Type = %s \r\n", "GPIO"); break; case DEVICE_CLASS_UART: MSG("Device Type = %s \r\n", "UART"); break; case DEVICE_CLASS_SPI: MSG("Device Type = %s \r\n", "SPI"); break; case DEVICE_CLASS_I2C: MSG("Device Type = %s \r\n", "I2C"); break; case DEVICE_CLASS_ADC: MSG("Device Type = %s \r\n", "ADC"); break; case DEVICE_CLASS_DMA: MSG("Device Type = %s \r\n", "DMA"); break; case DEVICE_CLASS_TIMER: MSG("Device Type = %s \r\n", "TIMER"); break; case DEVICE_CLASS_PWM: MSG("Device Type = %s \r\n", "PWM"); break; case DEVICE_CLASS_SDIO: MSG("Device Type = %s \r\n", "SDIO"); break; case DEVICE_CLASS_USB: MSG("Device Type = %s \r\n", "USB"); break; case DEVICE_CLASS_I2S: MSG("Device Type = %s \r\n", "I2S"); break; case DEVICE_CLASS_CAMERA: MSG("Device Type = %s \r\n", "CAMERA"); break; case DEVICE_CLASS_NONE: break; default: break; } MSG("Device Handle = 0x%x \r\n", dev); MSG("---------------------\r\n", dev); device_index++; } } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/bflb_platform.h ================================================ /** * @file bflb_platform.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef _BFLB_PLATFORM_H #define _BFLB_PLATFORM_H #ifdef __cplusplus extern "C" { #endif #include #include #include #include #include #include #define MSG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) #define MSG_DBG(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) #define MSG_ERR(a, ...) bflb_platform_printf(a, ##__VA_ARGS__) #define BL_CASE_FAIL \ { \ MSG("case fail\r\n"); \ } #define BL_CASE_SUCCESS \ { \ MSG("case success\r\n"); \ } /* compatible with old version */ #ifndef DBG_TAG #define DBG_TAG "DEBUG" #endif /* * The color for terminal (foreground) * BLACK 30 * RED 31 * GREEN 32 * YELLOW 33 * BLUE 34 * PURPLE 35 * CYAN 36 * WHITE 37 */ #define _DBG_COLOR(n) bflb_platform_printf("\033[" #n "m") #define _DBG_LOG_HDR(lvl_name, color_n) \ bflb_platform_printf("\033[" #color_n "m[" lvl_name "/" DBG_TAG "] ") #define _DBG_LOG_X_END \ bflb_platform_printf("\033[0m\n") #define dbg_log_line(lvl, color_n, fmt, ...) \ do { \ _DBG_LOG_HDR(lvl, color_n); \ bflb_platform_printf(fmt, ##__VA_ARGS__); \ _DBG_LOG_X_END; \ } while (0) #define LOG_D(fmt, ...) dbg_log_line("D", 0, fmt, ##__VA_ARGS__) #define LOG_I(fmt, ...) dbg_log_line("I", 35, fmt, ##__VA_ARGS__) #define LOG_W(fmt, ...) dbg_log_line("W", 33, fmt, ##__VA_ARGS__) #define LOG_E(fmt, ...) dbg_log_line("E", 31, fmt, ##__VA_ARGS__) #define LOG_RAW(...) bflb_platform_printf(__VA_ARGS__) void bflb_platform_init(uint32_t baudrate); void bflb_platform_printf(char *fmt, ...); void bflb_platform_print_set(uint8_t disable); uint8_t bflb_platform_print_get(void); void bflb_platform_dump(uint8_t *data, uint32_t len); void bflb_platform_reg_dump(uint32_t addr); uint32_t bflb_platform_get_log(uint8_t *data, uint32_t maxlen); void bflb_platform_deinit(void); void bflb_platform_init_time(void); void bflb_platform_clear_time(void); uint64_t bflb_platform_get_time_ms(void); uint64_t bflb_platform_get_time_us(void); void bflb_platform_start_time(void); void bflb_platform_stop_time(void); void bflb_platform_set_alarm_time(uint64_t time, void (*interruptFun)(void)); void bflb_platform_deinit_time(void); void bflb_platform_delay_ms(uint32_t ms); void bflb_platform_delay_us(uint32_t us); void bflb_print_device_list(void); #ifdef __cplusplus } #endif #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/cpp_new.cpp ================================================ #include #include void *operator new(size_t size) { return malloc(size); } void *operator new[](size_t size) { return malloc(size); } void operator delete(void *ptr) { free(ptr); } void operator delete[](void *ptr) { free(ptr); } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/bsp/bsp_common/platform/syscalls.c ================================================ #include #include #include // #include "drv_mmheap.h" #include "drv_device.h" extern struct heap_info mmheap_root; #ifdef CONF_VFS_ENABLE #include #endif /* Reentrant versions of system calls. */ /* global errno in RT-Thread */ static volatile int _sys_errno = 0; #ifndef _REENT_ONLY int *__errno() { // #if (configUSE_POSIX_ERRNO == 1) // { // extern int FreeRTOS_errno; // return &FreeRTOS_errno; // } // #endif return (int *)&_sys_errno; } #endif int _getpid_r(struct _reent *ptr) { return 0; } int _execve_r(struct _reent *ptr, const char *name, char *const *argv, char *const *env) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _fcntl_r(struct _reent *ptr, int fd, int cmd, int arg) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _fork_r(struct _reent *ptr) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _fstat_r(struct _reent *ptr, int fd, struct stat *pstat) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _isatty_r(struct _reent *ptr, int fd) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _kill_r(struct _reent *ptr, int pid, int sig) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } int _link_r(struct _reent *ptr, const char *old, const char *new) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } _off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else _off_t rc; rc = aos_lseek(fd, pos, whence); return rc; #endif } int _mkdir_r(struct _reent *ptr, const char *name, int mode) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else int rc; rc = aos_mkdir(name); return rc; #endif } int _open_r(struct _reent *ptr, const char *file, int flags, int mode) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else int rc; rc = aos_open(file, flags); return rc; #endif } int _close_r(struct _reent *ptr, int fd) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else return aos_close(fd); #endif } _ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else _ssize_t rc; rc = aos_read(fd, buf, nbytes); return rc; #endif } int _rename_r(struct _reent *ptr, const char *old, const char *new) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else int rc; rc = aos_rename(old, new); return rc; #endif } int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else int rc; rc = aos_stat(file, pstat); return rc; #endif } int _unlink_r(struct _reent *ptr, const char *file) { #ifndef CONF_VFS_ENABLE /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; #else return aos_unlink(file); #endif } int _wait_r(struct _reent *ptr, int *status) { /* return "not supported" */ ptr->_errno = -ENOSYS; return -1; } _ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) { #ifndef CONF_VFS_ENABLE struct device *uart = device_find("debug_log"); if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd)) { device_write(uart, 0, (uint8_t *)buf, nbytes); } return 0; #else _ssize_t rc; rc = aos_write(fd, buf, nbytes); return rc; #endif } // void *_malloc_r(struct _reent *ptr, size_t size) { return NULL; } // void *_realloc_r(struct _reent *ptr, void *old, size_t newlen) { return NULL; } // void *_calloc_r(struct _reent *ptr, size_t size, size_t len) { return NULL; } // void _free_r(struct _reent *ptr, void *addr) {} void *_sbrk_r(struct _reent *ptr, ptrdiff_t incr) { return NULL; } /* for exit() and abort() */ void __attribute__((noreturn)) _exit(int status) { while (1) { } } void _system(const char *s) {} mode_t umask(mode_t mask) { return 022; } int flock(int fd, int operation) { return 0; } /* These functions are implemented and replaced by the 'common/time.c' file int _gettimeofday_r(struct _reent *ptr, struct timeval *__tp, void *__tzp); _CLOCK_T_ _times_r(struct _reent *ptr, struct tms *ptms); */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/CMakeLists.txt ================================================ ################# Add global include ################# list(APPEND ADD_INCLUDE "${CMAKE_CURRENT_SOURCE_DIR}/ring_buffer" "${CMAKE_CURRENT_SOURCE_DIR}/soft_crc" "${CMAKE_CURRENT_SOURCE_DIR}/memheap" "${CMAKE_CURRENT_SOURCE_DIR}/misc" "${CMAKE_CURRENT_SOURCE_DIR}/list" "${CMAKE_CURRENT_SOURCE_DIR}/device" "${CMAKE_CURRENT_SOURCE_DIR}/partition" "${CMAKE_CURRENT_SOURCE_DIR}/bl_math" "${CMAKE_CURRENT_SOURCE_DIR}/pid" "${CMAKE_CURRENT_SOURCE_DIR}/timestamp" ) ####################################################### ################# Add private include ################# # list(APPEND ADD_PRIVATE_INCLUDE # ) ####################################################### ############## Add current dir source files ########### file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/ring_buffer/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/soft_crc/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/memheap/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/misc/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/device/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/partition/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/bl_math/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/pid/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/timestamp/*.c" ) #aux_source_directory(. sources) list(APPEND ADD_SRCS ${sources}) ####################################################### ########### Add required/dependent components ######### #list(APPEND ADD_REQUIREMENTS xxx) ####################################################### ############ Add static libs ########################## #list(APPEND ADD_STATIC_LIB "libxxx.a") ####################################################### ############ Add dynamic libs ######################### # list(APPEND ADD_DYNAMIC_LIB "libxxx.so" # ) ####################################################### ############ Add global compile option ################ #add components denpend on this component string(TOUPPER ${CHIP} CHIPNAME) list(APPEND ADD_DEFINITIONS -D${CHIPNAME}) ####################################################### ############ Add private compile option ################ #add compile option for this component that won't affect other modules # list(APPEND ADD_PRIVATE_DEFINITIONS -Dxxx) ####################################################### generate_library() ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.c ================================================ /** * @file arm_dsp_wrapper.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "arm_dsp_wrapper.h" void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) { uint32_t blkCnt = blockSize >> 2u; float32_t in1 = value; float32_t in2 = value; float32_t in3 = value; float32_t in4 = value; while (blkCnt > 0u) { *pDst++ = in1; *pDst++ = in2; *pDst++ = in3; *pDst++ = in4; blkCnt--; } blkCnt = blockSize % 0x4u; while (blkCnt > 0u) { *pDst++ = value; blkCnt--; } } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/bl_math/arm_dsp_wrapper.h ================================================ /** * @file arm_dsp_wrapper.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __MY_MATH_F_H__ #define __MY_MATH_F_H__ #include "misc.h" #include "math.h" typedef float float32_t; __INLINE__ float32_t arm_sqrt_f32(float32_t x) { return sqrtf(x); } __INLINE__ float32_t arm_cos_f32(float32_t x) { return cosf(x); } void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.c ================================================ /** * @file drv_device.c * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "drv_device.h" #define DEVICE_CHECK_PARAM #define dev_open (dev->open) #define dev_close (dev->close) #define dev_read (dev->read) #define dev_write (dev->write) #define dev_control (dev->control) dlist_t device_head = DLIST_OBJECT_INIT(device_head); /** * This function get device list header * * @param None * * @return device header */ dlist_t *device_get_list_header(void) { return &device_head; } /** * This function registers a device driver with specified name. * * @param dev the pointer of device driver structure * @param name the device driver's name * @param flags the capabilities flag of device * * @return the error code, DEVICE_EOK on initialization successfully. */ int device_register(struct device *dev, const char *name) { dlist_t *node; dlist_for_each(node, &device_head) { struct device *dev_obj; dev_obj = dlist_entry(node, struct device, list); if (dev_obj == dev) { return -DEVICE_EEXIST; } } strcpy(dev->name, name); dlist_insert_after(&device_head, &(dev->list)); dev->status = DEVICE_REGISTERED; return DEVICE_EOK; } /** * This function unregisters a device driver with specified name. * * @param dev the pointer of device driver structure * @param name the device driver's name * @param flags the capabilities flag of device * * @return the error code, DEVICE_EOK on initialization successfully. */ int device_unregister(const char *name) { struct device *dev = device_find(name); if (!dev) { return -DEVICE_ENODEV; } dev->status = DEVICE_UNREGISTER; /* remove from old list */ dlist_remove(&(dev->list)); return DEVICE_EOK; } /** * This function finds a device driver by specified name. * * @param name the device driver's name * * @return the registered device driver on successful, or NULL on failure. */ struct device *device_find(const char *name) { struct device *dev; dlist_t *node; dlist_for_each(node, &device_head) { dev = dlist_entry(node, struct device, list); if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) { return dev; } } return NULL; } /** * This function will open a device * * @param dev the pointer of device driver structure * @param oflag the flags for device open * * @return the result */ int device_open(struct device *dev, uint16_t oflag) { #ifdef DEVICE_CHECK_PARAM int retval = DEVICE_EOK; if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) { if (dev_open != NULL) { retval = dev_open(dev, oflag); dev->status = DEVICE_OPENED; dev->oflag |= oflag; } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; #else return dev_open(dev, oflag); #endif } /** * This function will close a device * * @param dev the pointer of device driver structure * * @return the result */ int device_close(struct device *dev) { #ifdef DEVICE_CHECK_PARAM int retval = DEVICE_EOK; if (dev->status == DEVICE_OPENED) { if (dev_close != NULL) { retval = dev_close(dev); dev->status = DEVICE_CLOSED; dev->oflag = 0; } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; #else return dev_close(dev); #endif } /** * This function will perform a variety of control functions on devices. * * @param dev the pointer of device driver structure * @param cmd the command sent to device * @param arg the argument of command * * @return the result */ int device_control(struct device *dev, int cmd, void *args) { #ifdef DEVICE_CHECK_PARAM int retval = DEVICE_EOK; if (dev->status > DEVICE_UNREGISTER) { if (dev_control != NULL) { retval = dev_control(dev, cmd, args); } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; #else return dev_control(dev, cmd, args); #endif } /** * This function will write some data to a device. * * @param dev the pointer of device driver structure * @param pos the position of written * @param buffer the data buffer to be written to device * @param size the size of buffer * * @return the actually written size on successful, otherwise negative returned. */ int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) { #ifdef DEVICE_CHECK_PARAM int retval = DEVICE_EOK; if (dev->status == DEVICE_OPENED) { if (dev_write != NULL) { retval = dev_write(dev, pos, buffer, size); } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; #else return dev_write(dev, pos, buffer, size); #endif } /** * This function will read some data from a device. * * @param dev the pointer of device driver structure * @param pos the position of reading * @param buffer the data buffer to save read data * @param size the size of buffer * * @return the actually read size on successful, otherwise negative returned. */ int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) { #ifdef DEVICE_CHECK_PARAM int retval = DEVICE_EOK; if (dev->status == DEVICE_OPENED) { if (dev_read != NULL) { retval = dev_read(dev, pos, buffer, size); } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; #else return dev_read(dev, pos, buffer, size); #endif } /** * This function will read some data from a device. * * @param dev the pointer of device driver structure * @param pos the position of reading * @param buffer the data buffer to save read data * @param size the size of buffer * * @return the actually read size on successful, otherwise negative returned. */ int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)) { int retval = DEVICE_EOK; if (dev->status > DEVICE_UNREGISTER) { if (callback != NULL) { dev->callback = callback; } else { retval = -DEVICE_EFAULT; } } else { retval = -DEVICE_EINVAL; } return retval; } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/device/drv_device.h ================================================ /** * @file drv_device.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __DRV_DEVICE_H__ #define __DRV_DEVICE_H__ #include "drv_list.h" #include "stdio.h" #define DEVICE_NAME_MAX 20 /* max device name*/ #define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */ #define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */ #define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */ #define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */ #define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */ #define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */ #define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */ #define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */ #define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */ #define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/ #define DEVICE_CTRL_RESUME 0x04 /* resume device */ #define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */ #define DEVICE_CTRL_CONFIG 0x06 /* config device */ #define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */ #define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */ #define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */ #define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */ #define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */ #define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */ #define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */ #define DEVICE_CTRL_RESVD1 0x0E #define DEVICE_CTRL_RESVD2 0x0F /* * POSIX Error codes */ #define DEVICE_EOK 0 #define DEVICE_EFAULT 14 /* Bad address */ #define DEVICE_EEXIST 17 /* device exists */ #define DEVICE_ENODEV 19 /* No such device */ #define DEVICE_EINVAL 22 /* Invalid argument */ #define DEVICE_ENOSPACE 23 /* No more Device for Allocate */ #define __ASSERT_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__) #define __ASSERT_LOC(test) \ __ASSERT_PRINT("ASSERTION FAIL [%s] @ %s:%d\n", \ #test, \ __FILE__, __LINE__) #define DEVICE_ASSERT(test, fmt, ...) \ do { \ if (!(test)) { \ __ASSERT_LOC(test); \ __ASSERT_PRINT(fmt, ##__VA_ARGS__); \ } \ } while (0) enum device_class_type { DEVICE_CLASS_NONE = 0, DEVICE_CLASS_GPIO, DEVICE_CLASS_UART, DEVICE_CLASS_SPI, DEVICE_CLASS_I2C, DEVICE_CLASS_ADC, DEVICE_CLASS_DAC, DEVICE_CLASS_DMA, DEVICE_CLASS_TIMER, DEVICE_CLASS_PWM, DEVICE_CLASS_QDEC, DEVICE_CLASS_SDIO, DEVICE_CLASS_USB, DEVICE_CLASS_RMII, DEVICE_CLASS_I2S, DEVICE_CLASS_CAMERA, DEVICE_CLASS_SEC_HASH, DEVICE_CLASS_KEYSCAN, }; enum device_status_type { DEVICE_UNREGISTER = 0, DEVICE_REGISTERED, DEVICE_OPENED, DEVICE_CLOSED }; struct device { char name[DEVICE_NAME_MAX]; /*name of device */ dlist_t list; /*list node of device */ enum device_status_type status; /*status of device */ enum device_class_type type; /*type of device */ uint16_t oflag; /*oflag of device */ int (*open)(struct device *dev, uint16_t oflag); int (*close)(struct device *dev); int (*control)(struct device *dev, int cmd, void *args); int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size); void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event); void *handle; }; int device_register(struct device *dev, const char *name); int device_unregister(const char *name); struct device *device_find(const char *name); int device_open(struct device *dev, uint16_t oflag); int device_close(struct device *dev); int device_control(struct device *dev, int cmd, void *args); int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)); dlist_t *device_get_list_header(void); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/list/drv_list.h ================================================ /** * @file drv_list.h * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __DRV_LIST_H__ #define __DRV_LIST_H__ #include "string.h" #include "stdint.h" #ifdef __cplusplus extern "C" { #endif /** * container_of - return the member address of ptr, if the type of ptr is the * struct type. */ #define container_of(ptr, type, member) \ ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) /** * Double List structure */ struct dlist_node { struct dlist_node *next; /**< point to next node. */ struct dlist_node *prev; /**< point to prev node. */ }; typedef struct dlist_node dlist_t; /**< Type for lists. */ /** * @brief initialize a list * * @param l list to be initialized */ static inline void dlist_init(dlist_t *l) { l->next = l->prev = l; } /** * @brief insert a node after a list * * @param l list to insert it * @param n new node to be inserted */ static inline void dlist_insert_after(dlist_t *l, dlist_t *n) { l->next->prev = n; n->next = l->next; l->next = n; n->prev = l; } /** * @brief insert a node before a list * * @param n new node to be inserted * @param l list to insert it */ static inline void dlist_insert_before(dlist_t *l, dlist_t *n) { l->prev->next = n; n->prev = l->prev; l->prev = n; n->next = l; } /** * @brief remove node from list. * @param n the node to remove from the list. */ static inline void dlist_remove(dlist_t *n) { n->next->prev = n->prev; n->prev->next = n->next; n->next = n->prev = n; } /** * @brief move node from list. * @param n the node to remove from the list. */ static inline void dlist_move_head(dlist_t *l, dlist_t *n) { dlist_remove(n); dlist_insert_after(l, n); } /** * @brief move node from list. * @param n the node to remove from the list. */ static inline void dlist_move_tail(dlist_t *l, dlist_t *n) { dlist_remove(n); dlist_insert_before(l, n); } /** * @brief tests whether a list is empty * @param l the list to test. */ static inline int dlist_isempty(const dlist_t *l) { return l->next == l; } /** * @brief get the list length * @param l the list to get. */ static inline unsigned int dlist_len(const dlist_t *l) { unsigned int len = 0; const dlist_t *p = l; while (p->next != l) { p = p->next; len++; } return len; } /** * @brief initialize a dlist object */ #define DLIST_OBJECT_INIT(object) \ { \ &(object), &(object) \ } /** * @brief initialize a dlist object */ #define DLIST_DEFINE(list) \ dlist_t list = { &(list), &(list) } /** * @brief get the struct for this entry * @param node the entry point * @param type the type of structure * @param member the name of list in structure */ #define dlist_entry(node, type, member) \ container_of(node, type, member) /** * dlist_first_entry - get the first element from a list * @ptr: the list head to take the element from. * @type: the type of the struct this is embedded in. * @member: the name of the list_struct within the struct. * * Note, that list is expected to be not empty. */ #define dlist_first_entry(ptr, type, member) \ dlist_entry((ptr)->next, type, member) /** * dlist_first_entry_or_null - get the first element from a list * @ptr: the list head to take the element from. * @type: the type of the struct this is embedded in. * @member: the name of the list_struct within the struct. * * Note, that list is expected to be not empty. */ #define dlist_first_entry_or_null(ptr, type, member) \ (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member)) /** * dlist_for_each - iterate over a list * @pos: the dlist_t * to use as a loop cursor. * @head: the head for your list. */ #define dlist_for_each(pos, head) \ for (pos = (head)->next; pos != (head); pos = pos->next) /** * dlist_for_each_prev - iterate over a list * @pos: the dlist_t * to use as a loop cursor. * @head: the head for your list. */ #define dlist_for_each_prev(pos, head) \ for (pos = (head)->prev; pos != (head); pos = pos->prev) /** * dlist_for_each_safe - iterate over a list safe against removal of list entry * @pos: the dlist_t * to use as a loop cursor. * @n: another dlist_t * to use as temporary storage * @head: the head for your list. */ #define dlist_for_each_safe(pos, n, head) \ for (pos = (head)->next, n = pos->next; pos != (head); \ pos = n, n = pos->next) #define dlist_for_each_prev_safe(pos, n, head) \ for (pos = (head)->prev, n = pos->prev; pos != (head); \ pos = n, n = pos->prev) /** * dlist_for_each_entry - iterate over list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your list. * @member: the name of the list_struct within the struct. */ #define dlist_for_each_entry(pos, head, member) \ for (pos = dlist_entry((head)->next, typeof(*pos), member); \ &pos->member != (head); \ pos = dlist_entry(pos->member.next, typeof(*pos), member)) /** * dlist_for_each_entry_reverse - iterate over list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your list. * @member: the name of the list_struct within the struct. */ #define dlist_for_each_entry_reverse(pos, head, member) \ for (pos = dlist_entry((head)->prev, typeof(*pos), member); \ &pos->member != (head); \ pos = dlist_entry(pos->member.prev, typeof(*pos), member)) /** * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry * @pos: the type * to use as a loop cursor. * @n: another type * to use as temporary storage * @head: the head for your list. * @member: the name of the list_struct within the struct. */ #define dlist_for_each_entry_safe(pos, n, head, member) \ for (pos = dlist_entry((head)->next, typeof(*pos), member), \ n = dlist_entry(pos->member.next, typeof(*pos), member); \ &pos->member != (head); \ pos = n, n = dlist_entry(n->member.next, typeof(*n), member)) /** * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry * @pos: the type * to use as a loop cursor. * @n: another type * to use as temporary storage * @head: the head for your list. * @member: the name of the list_struct within the struct. */ #define dlist_for_each_entry_safe_reverse(pos, n, head, member) \ for (pos = dlist_entry((head)->prev, typeof(*pos), field), \ n = dlist_entry(pos->member.prev, typeof(*pos), member); \ &pos->member != (head); \ pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member)) /** * Single List structure */ struct slist_node { struct slist_node *next; /**< point to next node. */ }; typedef struct slist_node slist_t; /**< Type for single list. */ /** * @brief initialize a single list * * @param l the single list to be initialized */ static inline void slist_init(slist_t *l) { l->next = NULL; } static inline void slist_add_head(slist_t *l, slist_t *n) { n->next = l->next; l->next = n; } static inline void slist_add_tail(slist_t *l, slist_t *n) { while (l->next) { l = l->next; } /* append the node to the tail */ l->next = n; n->next = NULL; } static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n) { if (!next) { slist_add_tail(next, l); return; } while (l->next) { if (l->next == next) { l->next = n; n->next = next; } l = l->next; } } static inline slist_t *slist_remove(slist_t *l, slist_t *n) { /* remove slist head */ while (l->next && l->next != n) { l = l->next; } /* remove node */ if (l->next != (slist_t *)0) { l->next = l->next->next; } return l; } static inline unsigned int slist_len(const slist_t *l) { unsigned int len = 0; const slist_t *list = l->next; while (list != NULL) { list = list->next; len++; } return len; } static inline unsigned int slist_contains(slist_t *l, slist_t *n) { while (l->next) { if (l->next == n) { return 0; } l = l->next; } return 1; } static inline slist_t *slist_head(slist_t *l) { return l->next; } static inline slist_t *slist_tail(slist_t *l) { while (l->next) { l = l->next; } return l; } static inline slist_t *slist_next(slist_t *n) { return n->next; } static inline int slist_isempty(slist_t *l) { return l->next == NULL; } /** * @brief initialize a slist object */ #define SLIST_OBJECT_INIT(object) \ { \ NULL \ } /** * @brief initialize a slist object */ #define SLIST_DEFINE(slist) \ slist_t slist = { NULL } /** * @brief get the struct for this single list node * @param node the entry point * @param type the type of structure * @param member the name of list in structure */ #define slist_entry(node, type, member) \ container_of(node, type, member) /** * slist_first_entry - get the first element from a slist * @ptr: the slist head to take the element from. * @type: the type of the struct this is embedded in. * @member: the name of the slist_struct within the struct. * * Note, that slist is expected to be not empty. */ #define slist_first_entry(ptr, type, member) \ slist_entry((ptr)->next, type, member) /** * slist_tail_entry - get the tail element from a slist * @ptr: the slist head to take the element from. * @type: the type of the struct this is embedded in. * @member: the name of the slist_struct within the struct. * * Note, that slist is expected to be not empty. */ #define slist_tail_entry(ptr, type, member) \ slist_entry(slist_tail(ptr), type, member) /** * slist_first_entry_or_null - get the first element from a slist * @ptr: the slist head to take the element from. * @type: the type of the struct this is embedded in. * @member: the name of the slist_struct within the struct. * * Note, that slist is expected to be not empty. */ #define slist_first_entry_or_null(ptr, type, member) \ (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member)) /** * slist_for_each - iterate over a single list * @pos: the slist_t * to use as a loop cursor. * @head: the head for your single list. */ #define slist_for_each(pos, head) \ for (pos = (head)->next; pos != NULL; pos = pos->next) #define slist_for_each_safe(pos, next, head) \ for (pos = (head)->next, next = pos->next; pos; \ pos = next, next = pos->next) /** * slist_for_each_entry - iterate over single list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your single list. * @member: the name of the list_struct within the struct. */ #define slist_for_each_entry(pos, head, member) \ for (pos = slist_entry((head)->next, typeof(*pos), member); \ &pos->member != (NULL); \ pos = slist_entry(pos->member.next, typeof(*pos), member)) #define slist_for_each_entry_safe(pos, n, head, member) \ for (pos = slist_entry((head)->next, typeof(*pos), member), \ n = slist_entry(pos->member.next, typeof(*pos), member); \ &pos->member != (NULL); \ pos = n, n = slist_entry(pos->member.next, typeof(*pos), member)) #ifdef __cplusplus } #endif #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/common.h ================================================ #ifndef __COMMON_H #define __COMMON_H /** * @brief Memory access macro */ #define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) #define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) #define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) #define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) #define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) #define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) #define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) #define BL_WRWD_TO_BYTEP(p, val) \ { \ p[0] = val & 0xff; \ p[1] = (val >> 8) & 0xff; \ p[2] = (val >> 16) & 0xff; \ p[3] = (val >> 24) & 0xff; \ } /** * @brief Register access macro */ #define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) #define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) #define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) #define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) #define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) #define BL_CLR_REG_BIT(val, bitname) ((val) & bitname##_UMSK) #define BL_GET_REG_BITS_VAL(val, bitname) (((val) & bitname##_MSK) >> bitname##_POS) #define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val) & bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) #define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) #define BL_DRV_DUMMY \ { \ __ASM volatile("nop"); \ __ASM volatile("nop"); \ __ASM volatile("nop"); \ __ASM volatile("nop"); \ } /* Std driver attribute macro*/ #ifndef BFLB_USE_CUSTOM_LD_SECTIONS // #define ATTR_UNI_SYMBOL #define ATTR_STRINGIFY(x) #x #define ATTR_TOSTRING(x) ATTR_STRINGIFY(x) #define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__) #define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL))) #define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL))) #define ATTR_TCM_SECTION __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL))) #define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL))) #define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) #define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) #define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) #define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) #define ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((section(".nocache_noinit_ram"))) #define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) #define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) #define ATTR_EALIGN(x) __attribute__((aligned(x))) #define ATTR_FALLTHROUGH() __attribute__((fallthrough)) #define ATTR_USED __attribute__((__used__)) #else #include "bl_ld_sections.h" #endif /* BFLB_USE_CUSTOM_LD_SECTIONS */ #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/compiler/gcc.h ================================================ #ifndef __GCC_H #define __GCC_H #ifndef __ORDER_BIG_ENDIAN__ #define __ORDER_BIG_ENDIAN__ (1) #endif #ifndef __ORDER_LITTLE_ENDIAN__ #define __ORDER_LITTLE_ENDIAN__ (2) #endif #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ /* CPP header guards */ #ifdef __cplusplus #define EXTERN_C_BEGIN extern "C" { #define EXTERN_C_END } #else #define EXTERN_C_BEGIN #define EXTERN_C_END #endif #define __MACRO_BEGIN do { #define __MACRO_END \ } \ while (0) #if defined(__GNUC__) #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __INLINE__ #define __INLINE__ inline #endif #ifndef __ALWAYS_INLINE #define __ALWAYS_INLINE inline __attribute__((always_inline)) #endif #ifndef __ALWAYS_STATIC_INLINE #define __ALWAYS_STATIC_INLINE __attribute__((always_inline)) static inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __UNUSED__ #define __UNUSED__ __attribute__((__unused__)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __WEAK__ #define __WEAK__ __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED__ #define __PACKED__ __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __IRQ #define __IRQ __attribute__((interrupt)) #endif #ifndef __IRQ_ALIGN64 #define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64))) #endif #ifndef ALIGN4 #define ALIGN4 __attribute((aligned(4))) #endif #ifndef PACK_START #define PACK_START #endif #ifndef PACK_END #define PACK_END __attribute__((packed)) #endif #ifndef likely #define likely(x) __builtin_expect(!!(x), 1) #endif #ifndef unlikely #define unlikely(x) __builtin_expect(!!(x), 0) #endif #ifndef __ALIGNED__ #define __ALIGNED__(x) __attribute__((aligned(x))) #endif #ifndef SECTION #define SECTION(x) __attribute__((section(x))) #endif #ifndef __CONST__ #define __CONST__ __attribute__((__const__)) #endif #ifndef __NAKED__ #define __NAKED__ __attribute__((naked)) #endif #ifndef __deprecated #define __deprecated __attribute__((deprecated)) #endif #endif #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.c ================================================ /** * @file misc.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "misc.h" #ifndef BFLB_USE_ROM_DRIVER /****************************************************************************/ /** * @brief Char memcpy * * @param dst: Destination * @param src: Source * @param n: Count of char * * @return Destination pointer * *******************************************************************************/ __WEAK__ void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) { const uint8_t *p = src; uint8_t *q = dst; while (n--) { *q++ = *p++; } return dst; } /****************************************************************************/ /** * @brief Word memcpy * * @param dst: Destination * @param src: Source * @param n: Count of words * * @return Destination pointer * *******************************************************************************/ __WEAK__ uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n) { const uint32_t *p = src; uint32_t *q = dst; while (n--) { *q++ = *p++; } return dst; } /****************************************************************************/ /** * @brief Fast memcpy * * @param dst: Destination * @param src: Source * @param n: Count of bytes * * @return Destination pointer * *******************************************************************************/ __WEAK__ void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n) { uint32_t left, done, i = 0; uint8_t *dst = (uint8_t *)pdst; uint8_t *src = (uint8_t *)psrc; if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) { arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2); left = n % 4; done = n - left; while (i < left) { dst[done + i] = src[done + i]; i++; } } else { arch_memcpy(dst, src, n); } return dst; } /****************************************************************************/ /** * @brief char memset * * @param dst: Destination * @param val: Value to set * @param n: Count of char * * @return Destination pointer * *******************************************************************************/ __WEAK__ void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n) { uint8_t *p = (uint8_t *)s; while (n > 0) { *p++ = (uint8_t)c; --n; } return s; } /****************************************************************************/ /** * @brief Word memset * * @param dst: Destination * @param val: Value to set * @param n: Count of words * * @return Destination pointer * *******************************************************************************/ __WEAK__ uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n) { uint32_t *q = dst; while (n--) { *q++ = val; } return dst; } /****************************************************************************/ /** * @brief string compare * * @param s1: string 1 * @param s2: string 2 * @param n: Count of chars * * @return compare result * *******************************************************************************/ __WEAK__ int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n) { const unsigned char *c1 = s1, *c2 = s2; int d = 0; while (n--) { d = (int)*c1++ - (int)*c2++; if (d) { break; } } return d; } #endif void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length) { uint8_t *p = (uint8_t *)fifo_addr; uint8_t *q = data; while (length--) { *p = *q++; } } void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length) { uint8_t *p = (uint8_t *)fifo_addr; uint8_t *q = data; while (length--) { *q++ = *p; } } /****************************************************************************/ /** * @brief get u64 first number 1 from right to left * * @param val: target value * @param bit: first 1 in bit * * @return SUCCESS or ERROR * *******************************************************************************/ int arch_ffsll(uint64_t *val, uint32_t *bit) { if (!*val) { return ERROR; } *bit = __builtin_ffsll(*val) - 1; *val &= ~((1ULL) << (*bit)); return 0; } int arch_ctzll(uint64_t *val, uint32_t *bit) { if (!*val) { return -1; } *bit = __builtin_ctzll(*val); *val &= ~((1ULL) << (*bit)); return 0; } int arch_clzll(uint64_t *val, uint32_t *bit) { if (!*val) { return -1; } *bit = __builtin_clzll(*val); *val &= ~((1ULL) << (*bit)); return 0; } #ifdef DEBUG /******************************************************************************* * @brief Reports the name of the source file and the source line number * where the CHECK_PARAM error has occurred. * @param file: Pointer to the source file name * @param line: assert_param error line source number * @return None *******************************************************************************/ void check_failed(uint8_t *file, uint32_t line) { /* Infinite loop */ while (1) { } } #endif /* DEBUG */ /*@} end of group DRIVER_Public_Functions */ /*@} end of group DRIVER_COMMON */ /*@} end of group BL602_Periph_Driver */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/misc/misc.h ================================================ /** * @file misc.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef _MISC_H #define _MISC_H #include #include #include #include #include #include #include "compiler/gcc.h" #include "compiler/common.h" #ifdef BIT #undef BIT #define BIT(n) (1UL << (n)) #else #define BIT(n) (1UL << (n)) #endif /** * @brief Null Type definition */ #ifndef NULL #define NULL 0 #endif /** * @brief Error type definition */ typedef enum { SUCCESS = 0, ERROR = 1, TIMEOUT = 2, INVALID = 3, /* invalid arguments */ NORESC = 4 /* no resource or resource temperary unavailable */ } BL_Err_Type; /** * @brief Functional type definition */ typedef enum { DISABLE = 0, ENABLE = 1, } BL_Fun_Type; /** * @brief Status type definition */ typedef enum { RESET = 0, SET = 1, } BL_Sts_Type; /** * @brief Mask type definition */ typedef enum { UNMASK = 0, MASK = 1 } BL_Mask_Type; /** * @brief Logical status Type definition */ typedef enum { LOGIC_LO = 0, LOGIC_HI = !LOGIC_LO } LogicalStatus; /** * @brief Active status Type definition */ typedef enum { DEACTIVE = 0, ACTIVE = !DEACTIVE } ActiveStatus; /** * @brief Interrupt callback function type */ typedef void(intCallback_Type)(void); typedef void (*pFunc)(void); #define ARCH_MemCpy arch_memcpy #define ARCH_MemSet arch_memset #define ARCH_MemCmp arch_memcmp #define ARCH_MemCpy4 arch_memcpy4 #define ARCH_MemCpy_Fast arch_memcpy_fast #define ARCH_MemSet4 arch_memset4 #ifdef DEBUG void check_failed(uint8_t *file, uint32_t line); #define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) #else #define CHECK_PARAM(expr) ((void)0) #endif /* DEBUG */ void *arch_memcpy(void *dst, const void *src, uint32_t n); void *arch_memset(void *s, uint8_t c, uint32_t n); int arch_memcmp(const void *s1, const void *s2, uint32_t n); uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n); void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n); uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n); void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length); void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length); int arch_ctzll(uint64_t *val, uint32_t *bit); int arch_clzll(uint64_t *val, uint32_t *bit); int arch_ffsll(uint64_t *val, uint32_t *bit); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.c ================================================ /** ****************************************************************************** * @file partition.c * @version V1.0 * @date * @brief This file is the standard driver c file ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2019 Bouffalo Lab

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of Bouffalo Lab nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ #include "partition.h" #include "bflb_platform.h" #include "softcrc.h" /** @addtogroup BFLB_Common_Driver * @{ */ /** @addtogroup PARTITION * @{ */ /** @defgroup PARTITION_Private_Macros * @{ */ /*@} end of group PARTITION_Private_Macros */ /** @defgroup PARTITION_Private_Types * @{ */ /*@} end of group PARTITION_Private_Types */ /** @defgroup PARTITION_Private_Variables * @{ */ p_pt_table_flash_erase gp_pt_table_flash_erase = NULL; p_pt_table_flash_write gp_pt_table_flash_write = NULL; p_pt_table_flash_read gp_pt_table_flash_read = NULL; pt_table_iap_param_type p_iap_param; /*@} end of group PARTITION_Private_Variables */ /** @defgroup PARTITION_Global_Variables * @{ */ extern int main(void); /*@} end of group PARTITION_Global_Variables */ /** @defgroup PARTITION_Private_Fun_Declaration * @{ */ /*@} end of group PARTITION_Private_Fun_Declaration */ /** @defgroup PARTITION_Private_Functions * @{ */ /****************************************************************************/ /** * @brief Judge partition table valid * * @param ptStuff: Partition table stuff pointer * * @return 0 for invalid and 1 for valid * *******************************************************************************/ static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff) { pt_table_config *pt_table = &pt_stuff->pt_table; pt_table_entry_config *pt_entries = pt_stuff->pt_entries; uint32_t *p_crc32; uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt; if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) { if (pt_table->entryCnt > PT_ENTRY_MAX) { MSG("PT Entry Count Error\r\n"); return 0; } if (pt_table->crc32 != BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) { MSG("PT CRC Error\r\n"); return 0; } /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */ p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen); if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) { MSG("PT Entry CRC Error\r\n"); return 0; } return 1; } return 0; } /*@} end of group PARTITION_Private_Functions */ /** @defgroup PARTITION_Public_Functions * @{ */ /****************************************************************************/ /** * @brief Register partition flash read write erase fucntion * * @param erase: Flash erase function * @param write: Flash write function * @param read: Flash read function * * @return None * *******************************************************************************/ void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read) { gp_pt_table_flash_erase = erase; gp_pt_table_flash_write = write; gp_pt_table_flash_read = read; } /****************************************************************************/ /** * @brief Get active partition table whole stuff * * @param ptStuff[2]: Partition table stuff pointer * * @return Active partition table ID * *******************************************************************************/ pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]) { uint32_t pt_valid[2] = {0, 0}; pt_table_id_type activePtID; if (ptStuff == NULL) { return PT_TABLE_ID_INVALID; } activePtID = PT_TABLE_ID_INVALID; gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config)); pt_valid[0] = pt_table_valid(&ptStuff[0]); gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config)); pt_valid[1] = pt_table_valid(&ptStuff[1]); if (pt_valid[0] == 1 && pt_valid[1] == 1) { if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) { activePtID = PT_TABLE_ID_0; } else { activePtID = PT_TABLE_ID_1; } } else if (pt_valid[0] == 1) { activePtID = PT_TABLE_ID_0; } else if (pt_valid[1] == 1) { activePtID = PT_TABLE_ID_1; } return activePtID; } /****************************************************************************/ /** * @brief Get partition entry according to entry ID * * @param ptStuff: Partition table stuff pointer * @param type: Type of partition entry * @param ptEntry: Partition entry pointer to store read data * * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER * *******************************************************************************/ pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, pt_table_entry_type type, pt_table_entry_config *pt_entry) { uint32_t i = 0; if (pt_stuff == NULL || pt_entry == NULL) { return PT_ERROR_PARAMETER; } for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { if (pt_stuff->pt_entries[i].type == type) { ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); return PT_ERROR_SUCCESS; } } return PT_ERROR_ENTRY_NOT_FOUND; } /****************************************************************************/ /** * @brief Get partition entry according to entry name * * @param ptStuff: Partition table stuff pointer * @param name: Name of partition entry * @param ptEntry: Partition entry pointer to store read data * * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER * *******************************************************************************/ pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, uint8_t *name, pt_table_entry_config *pt_entry) { uint32_t i = 0; uint32_t len = strlen((char *)name); if (pt_stuff == NULL || pt_entry == NULL) { return PT_ERROR_PARAMETER; } for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { if (strlen((char *)pt_stuff->pt_entries[i].name) == len && memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); return PT_ERROR_SUCCESS; } } return PT_ERROR_ENTRY_NOT_FOUND; } /****************************************************************************/ /** * @brief Update partition entry * * @param targetTableID: Target partition table to update * @param ptStuff: Partition table stuff pointer * @param ptEntry: Partition entry pointer to update * * @return Partition update result * *******************************************************************************/ pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, pt_table_stuff_config *pt_stuff, pt_table_entry_config *pt_entry) { uint32_t i = 0; BL_Err_Type ret; uint32_t write_addr; uint32_t entries_len; pt_table_config *pt_table; pt_table_entry_config *pt_entries; uint32_t *crc32; if (pt_entry == NULL || pt_stuff == NULL) { return PT_ERROR_PARAMETER; } pt_table = &pt_stuff->pt_table; pt_entries = pt_stuff->pt_entries; if (target_table_id == PT_TABLE_ID_INVALID) { return PT_ERROR_TABLE_NOT_VALID; } if (target_table_id == PT_TABLE_ID_0) { write_addr = BFLB_PT_TABLE0_ADDRESS; } else { write_addr = BFLB_PT_TABLE1_ADDRESS; } for (i = 0; i < pt_table->entryCnt; i++) { if (pt_entries[i].type == pt_entry->type) { ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); break; } } if (i == pt_table->entryCnt) { /* Not found this entry ,add new one */ if (pt_table->entryCnt < PT_ENTRY_MAX) { ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); pt_table->entryCnt++; } else { return PT_ERROR_ENTRY_UPDATE_FAIL; } } /* Prepare write back to flash */ /* Update age */ pt_table->age++; pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4); /* Update entries CRC */ entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config); crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len); *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len); /* Write back to flash */ /* Erase flash first */ // ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1); ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4); if (ret != SUCCESS) { MSG_ERR("Flash Erase error\r\n"); return PT_ERROR_FALSH_WRITE; } /* Write flash */ ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config)); if (ret != SUCCESS) { MSG_ERR("Flash Write error\r\n"); return PT_ERROR_FALSH_WRITE; } return PT_ERROR_SUCCESS; } /****************************************************************************/ /** * @brief Create partition entry * * @param ptID: Partition table ID * * @return Partition create result * *******************************************************************************/ pt_table_error_type pt_table_create(pt_table_id_type pt_id) { uint32_t write_addr; BL_Err_Type ret; pt_table_config pt_table; if (pt_id == PT_TABLE_ID_INVALID) { return PT_ERROR_TABLE_NOT_VALID; } if (pt_id == PT_TABLE_ID_0) { write_addr = BFLB_PT_TABLE0_ADDRESS; } else { write_addr = BFLB_PT_TABLE1_ADDRESS; } /* Prepare write back to flash */ pt_table.magicCode = BFLB_PT_MAGIC_CODE; pt_table.version = 0; pt_table.entryCnt = 0; pt_table.age = 0; pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4); /* Write back to flash */ // ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1); ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config)); if (ret != SUCCESS) { MSG_ERR("Flash Erase error\r\n"); return PT_ERROR_FALSH_ERASE; } ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config)); if (ret != SUCCESS) { MSG_ERR("Flash Write error\r\n"); return PT_ERROR_FALSH_WRITE; } return PT_ERROR_SUCCESS; } pt_table_error_type pt_table_dump(void) { uint32_t pt_valid[2] = {0, 0}; pt_table_stuff_config pt_stuff[2]; gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); pt_valid[0] = pt_table_valid(&pt_stuff[0]); gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); pt_valid[1] = pt_table_valid(&pt_stuff[1]); if (pt_valid[0]) { MSG("PT TABLE0 valid\r\n"); } else { MSG("PT TABLE0 invalid\r\n"); } if (pt_valid[1]) { MSG("PT TABLE1 valid\r\n"); } else { MSG("PT TABLE1 invalid\r\n"); } for (int i = 0; i < 2; i++) { if (pt_valid[i] == 1) { MSG("ptStuff[%d].pt_table.magicCode 0x%08x\r\n", i, pt_stuff[i].pt_table.magicCode); MSG("ptStuff[%d].pt_table.version 0x%08x\r\n", i, pt_stuff[i].pt_table.version); MSG("ptStuff[%d].pt_table.entryCnt 0x%08x\r\n", i, pt_stuff[i].pt_table.entryCnt); MSG("ptStuff[%d].pt_table.age 0x%08x\r\n", i, pt_stuff[i].pt_table.age); MSG("ptStuff[%d].pt_table.crc32 0x%08x\r\n", i, pt_stuff[i].pt_table.crc32); for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) { MSG("ptStuff[%d].pt_entries[%d].type 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].type); MSG("ptStuff[%d].pt_entries[%d].device 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].device); MSG("ptStuff[%d].pt_entries[%d].active_index 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].active_index); MSG("ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[0]); MSG("ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[1]); MSG("ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[0]); MSG("ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[1]); MSG("ptStuff[%d].pt_entries[%d].len 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].len); MSG("ptStuff[%d].pt_entries[%d].age 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].age); } } } return PT_ERROR_SUCCESS; } pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para) { uint32_t pt_valid[2] = {0, 0}; pt_table_stuff_config pt_stuff[2]; uint8_t active_index; gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); pt_valid[0] = pt_table_valid(&pt_stuff[0]); gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); pt_valid[1] = pt_table_valid(&pt_stuff[1]); if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) { if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) { active_index = pt_stuff[0].pt_entries[0].active_index; para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; para->inactive_index = !(active_index & 0x01); para->inactive_table_index = 1; } else { active_index = pt_stuff[1].pt_entries[0].active_index; para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; para->inactive_index = !(active_index & 0x01); para->inactive_table_index = 0; } } else if (pt_valid[1] == 1) { active_index = pt_stuff[1].pt_entries[0].active_index; para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; para->inactive_index = !(active_index & 0x01); para->inactive_table_index = 0; } else if (pt_valid[0] == 1) { active_index = pt_stuff[0].pt_entries[0].active_index; para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; para->inactive_index = !(active_index & 0x01); para->inactive_table_index = 1; } else { return PT_ERROR_TABLE_NOT_VALID; } MSG("inactive_table_index %d, inactive index %d , IAP start addr %08x \r\n", para->inactive_table_index, para->inactive_index, para->iap_start_addr); return PT_ERROR_SUCCESS; } pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) { pt_table_stuff_config pt_stuff, pt_stuff_write; int32_t ret; uint32_t *p_crc32; uint32_t entries_len; if (para->inactive_table_index == 1) { gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); } else if (para->inactive_table_index == 0) { gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); } ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); pt_stuff_write.pt_table.age += 1; pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt; // pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len); p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len); *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len); if (para->inactive_table_index == 1) { // ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1); ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config)); if (ret != SUCCESS) { MSG_ERR("Flash Erase error\r\n"); return PT_ERROR_FALSH_ERASE; } ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); if (ret != SUCCESS) { MSG_ERR("Flash Write error\r\n"); return PT_ERROR_FALSH_WRITE; } } else if (para->inactive_table_index == 0) { // ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1); ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config)); if (ret != SUCCESS) { MSG_ERR("Flash Erase error\r\n"); return PT_ERROR_FALSH_ERASE; } ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); if (ret != SUCCESS) { MSG_ERR("Flash Write error\r\n"); return PT_ERROR_FALSH_WRITE; } } MSG("Update pt_table suss\r\n"); return PT_ERROR_SUCCESS; } /*@} end of group PARTITION_Public_Functions */ /*@} end of group PARTITION */ /*@} end of group BFLB_Common_Driver */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/partition/partition.h ================================================ /** ****************************************************************************** * @file partition.h * @version V1.0 * @date * @brief This file is the standard driver header file ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2020 Bouffalo Lab

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of Bouffalo Lab nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ #ifndef __PARTITION_H__ #define __PARTITION_H__ #include "misc.h" /** @addtogroup BFLB_Common_Driver * @{ */ /** @addtogroup PARTITION * @{ */ /** @defgroup PARTITION_Public_Types * @{ */ /** * @brief Partition table error type definition */ typedef enum { PT_ERROR_SUCCESS, /*!< Partition table error type:success */ PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */ PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ } pt_table_error_type; /** * @brief Partition id type definition */ typedef enum { PT_TABLE_ID_0, /*!< Partition table ID 0 */ PT_TABLE_ID_1, /*!< Partition table ID 1 */ PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ } pt_table_id_type; /** * @brief Partition id type definition */ typedef enum { PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */ } pt_table_entry_type; /** * @brief Partition table config definition */ typedef struct { uint32_t magicCode; /*!< Partition table magic code */ uint16_t version; /*!< Partition table verdion */ uint16_t entryCnt; /*!< Partition table entry count */ uint32_t age; /*!< Partition table age */ uint32_t crc32; /*!< Partition table CRC32 value */ } pt_table_config; /** * @brief Partition table entry config definition */ typedef struct { uint8_t type; /*!< Partition entry type */ uint8_t device; /*!< Partition entry device */ uint8_t active_index; /*!< Partition entry active index */ uint8_t name[9]; /*!< Partition entry name */ uint32_t start_address[2]; /*!< Partition entry start address */ uint32_t max_len[2]; /*!< Partition entry max length */ uint32_t len; /*!< Partition entry length */ uint32_t age; /*!< Partition entry age */ } pt_table_entry_config; /** * @brief Partition table stuff config definition */ typedef struct { pt_table_config pt_table; /*!< Partition table */ pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */ uint32_t crc32; /*!< Partition entries crc32 */ } pt_table_stuff_config; /** * @brief Partition table iap param definition */ typedef struct { uint32_t iap_start_addr; uint32_t iap_write_addr; uint32_t iap_img_len; uint8_t inactive_index; uint8_t inactive_table_index; } pt_table_iap_param_type; /*@} end of group PARTITION_Public_Types */ /** @defgroup PARTITION_Public_Constants * @{ */ /** @defgroup pt_table_error_type * @{ */ #define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ ((type) == PT_ERROR_TABLE_NOT_VALID) || \ ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ ((type) == PT_ERROR_CRC32) || \ ((type) == PT_ERROR_PARAMETER) || \ ((type) == PT_ERROR_FALSH_READ) || \ ((type) == PT_ERROR_FALSH_WRITE) || \ ((type) == PT_ERROR_FALSH_ERASE)) /** @defgroup pt_table_id_type * @{ */ #define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ ((type) == PT_TABLE_ID_1) || \ ((type) == PT_TABLE_ID_INVALID)) /** @defgroup pt_table_entry_type * @{ */ #define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ ((type) == PT_ENTRY_FW_CPU1) || \ ((type) == PT_ENTRY_MAX)) /*@} end of group PARTITION_Public_Constants */ /** @defgroup PARTITION_Public_Macros * @{ */ #define BFLB_PT_TABLE0_ADDRESS 0xE000 #define BFLB_PT_TABLE1_ADDRESS 0xF000 #define BFLB_PT_MAGIC_CODE 0x54504642 typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr); typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len); typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len); /*@} end of group PARTITION_Public_Macros */ /** @defgroup PARTITION_Public_Functions * @{ */ void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read); pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]); pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, pt_table_entry_type type, pt_table_entry_config *pt_entry); pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, uint8_t *name, pt_table_entry_config *pt_entry); pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, pt_table_stuff_config *pt_stuff, pt_table_entry_config *pt_entry); pt_table_error_type pt_table_create(pt_table_id_type pt_id); pt_table_error_type pt_table_dump(void); pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para); pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para); /*@} end of group PARTITION_Public_Functions */ /*@} end of group PARTITION */ /*@} end of group BFLB_Common_Driver */ extern pt_table_iap_param_type p_iap_param; #endif /* __PARTITION_H__ */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.c ================================================ /** * @file pid.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "pid.h" void pid_init(pid_alg_t *pid) { pid->set_val = 0.0f; pid->out_val = 0.0f; pid->last_error = 0.0f; pid->prev_error = 0.0f; pid->kp = 3.0f; pid->ki = 0.0f; pid->kd = 0.0f; pid->i_error = 0.0f; pid->sum_error = 0.0f; pid->max_val = 32; pid->min_val = -32; } // standard pid float standard_pid_cal(pid_alg_t *pid, float next_val) { pid->set_val = next_val; pid->i_error = pid->set_val - pid->out_val; pid->sum_error += pid->i_error; pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error); pid->last_error = pid->i_error; return pid->out_val; } // increment pid float increment_pid_cal(pid_alg_t *pid, float next_val) { pid->set_val = next_val; pid->i_error = pid->set_val - pid->out_val; float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error); pid->out_val += increment; pid->last_error = pid->prev_error; pid->prev_error = pid->i_error; return pid->out_val; } ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/pid/pid.h ================================================ /** * @file pid.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __PID_H__ #define __PID_H__ #include "stdint.h" typedef struct pid_alg { float set_val; float out_val; float kp; float ki; float kd; float i_error; float last_error; float prev_error; float sum_error; int max_val; int min_val; } pid_alg_t; void pid_init(pid_alg_t *pid); float standard_pid_cal(pid_alg_t *pid, float next_val); float increment_pid_cal(pid_alg_t *pid, float next_val); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.c ================================================ /** * @file ring_buffer.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "ring_buffer.h" /** @addtogroup BL_Common_Component * @{ */ /** @addtogroup RING_BUFFER * @{ */ /** @defgroup RING_BUFFER_Private_Macros * @{ */ /*@} end of group RING_BUFFER_Private_Macros */ /** @defgroup RING_BUFFER_Private_Types * @{ */ /*@} end of group RING_BUFFER_Private_Types */ /** @defgroup RING_BUFFER_Private_Fun_Declaration * @{ */ /*@} end of group RING_BUFFER_Private_Fun_Declaration */ /** @defgroup RING_BUFFER_Private_Variables * @{ */ /*@} end of group RING_BUFFER_Private_Variables */ /** @defgroup RING_BUFFER_Global_Variables * @{ */ /*@} end of group RING_BUFFER_Global_Variables */ /** @defgroup RING_BUFFER_Private_Functions * @{ */ /*@} end of group RING_BUFFER_Private_Functions */ /** @defgroup RING_BUFFER_Public_Functions * @{ */ /****************************************************************************/ /** * @brief Ring buffer init function * * @param rbType: Ring buffer type structure pointer * @param buffer: Pointer of ring buffer * @param size: Size of ring buffer * @param lockCb: Ring buffer lock callback function pointer * @param unlockCb: Ring buffer unlock callback function pointer * * @return SUCCESS * *******************************************************************************/ BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb) { /* Init ring buffer pointer */ rbType->pointer = buffer; /* Init read/write mirror and index */ rbType->readMirror = 0; rbType->readIndex = 0; rbType->writeMirror = 0; rbType->writeIndex = 0; /* Set ring buffer size */ rbType->size = size; /* Set lock and unlock callback function */ rbType->lock = lockCb; rbType->unlock = unlockCb; return SUCCESS; } /****************************************************************************/ /** * @brief Ring buffer reset function * * @param rbType: Ring buffer type structure pointer * * @return SUCCESS * *******************************************************************************/ BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType) { if (rbType->lock != NULL) { rbType->lock(); } /* Clear read/write mirror and index */ rbType->readMirror = 0; rbType->readIndex = 0; rbType->writeMirror = 0; rbType->writeIndex = 0; if (rbType->unlock != NULL) { rbType->unlock(); } return SUCCESS; } /****************************************************************************/ /** * @brief Use callback function to write ring buffer function * * @param rbType: Ring buffer type structure pointer * @param length: Length of data want to write * @param writeCb: Callback function pointer * @param parameter: Parameter that callback function may use * * @return Length of data actually write * *******************************************************************************/ uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter) { uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); if (writeCb == NULL) { return 0; } if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no space for new data */ if (sizeRemained == 0) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } /* Drop part of data when length out of space remained */ if (length > sizeRemained) { length = sizeRemained; } /* Get size of space remained in current mirror */ sizeRemained = rbType->size - rbType->writeIndex; if (sizeRemained > length) { /* Space remained is enough for data in current mirror */ writeCb(parameter, &rbType->pointer[rbType->writeIndex], length); rbType->writeIndex += length; } else { /* Data is divided to two parts with different mirror */ writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained); writeCb(parameter, &rbType->pointer[0], length - sizeRemained); rbType->writeIndex = length - sizeRemained; rbType->writeMirror = ~rbType->writeMirror; } if (rbType->unlock != NULL) { rbType->unlock(); } return length; } /****************************************************************************/ /** * @brief Copy data from data buffer to ring buffer function * * @param parameter: Pointer to source pointer * @param dest: Ring buffer to write * @param length: Length of data to write * * @return None * *******************************************************************************/ static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length) { uint8_t **src = (uint8_t **)parameter; ARCH_MemCpy_Fast(dest, *src, length); *src += length; } /****************************************************************************/ /** * @brief Write ring buffer function * * @param rbType: Ring buffer type structure pointer * @param data: Data to write * @param length: Length of data * * @return Length of data writted actually * *******************************************************************************/ uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) { return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data); } /****************************************************************************/ /** * @brief Write 1 byte to ring buffer function * * @param rbType: Ring buffer type structure pointer * @param data: Data to write * * @return Length of data writted actually * *******************************************************************************/ uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data) { if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no space for new data */ if (!Ring_Buffer_Get_Empty_Length(rbType)) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } rbType->pointer[rbType->writeIndex] = data; /* Judge to change index and mirror */ if (rbType->writeIndex != (rbType->size - 1)) { rbType->writeIndex++; } else { rbType->writeIndex = 0; rbType->writeMirror = ~rbType->writeMirror; } if (rbType->unlock != NULL) { rbType->unlock(); } return 1; } /****************************************************************************/ /** * @brief Write ring buffer function, old data will be covered by new data when ring buffer is * full * * @param rbType: Ring buffer type structure pointer * @param data: Data to write * @param length: Length of data * * @return Length of data writted actually * *******************************************************************************/ uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) { uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); uint32_t indexRemained = rbType->size - rbType->writeIndex; if (rbType->lock != NULL) { rbType->lock(); } /* Drop extra data when data length is large than size of ring buffer */ if (length > rbType->size) { data = &data[length - rbType->size]; length = rbType->size; } if (indexRemained > length) { /* Space remained is enough for data in current mirror */ ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length); rbType->writeIndex += length; /* Update read index */ if (length > sizeRemained) { rbType->readIndex = rbType->writeIndex; } } else { /* Data is divided to two parts with different mirror */ ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained); ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained); rbType->writeIndex = length - indexRemained; rbType->writeMirror = ~rbType->writeMirror; /* Update read index and mirror */ if (length > sizeRemained) { rbType->readIndex = rbType->writeIndex; rbType->readMirror = ~rbType->readMirror; } } if (rbType->unlock != NULL) { rbType->unlock(); } return length; } /****************************************************************************/ /** * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring * buffer is full * * @param rbType: Ring buffer type structure pointer * @param data: Data to write * * @return Length of data writted actually * *******************************************************************************/ uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data) { Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType); if (rbType->lock != NULL) { rbType->lock(); } rbType->pointer[rbType->writeIndex] = data; /* Judge to change index and mirror */ if (rbType->writeIndex == rbType->size - 1) { rbType->writeIndex = 0; rbType->writeMirror = ~rbType->writeMirror; /* Update read index and mirror */ if (status == RING_BUFFER_FULL) { rbType->readIndex = rbType->writeIndex; rbType->readMirror = ~rbType->readMirror; } } else { rbType->writeIndex++; /* Update read index */ if (status == RING_BUFFER_FULL) { rbType->readIndex = rbType->writeIndex; } } if (rbType->unlock != NULL) { rbType->unlock(); } return 1; } /****************************************************************************/ /** * @brief Use callback function to read ring buffer function * * @param rbType: Ring buffer type structure pointer * @param length: Length of data want to read * @param readCb: Callback function pointer * @param parameter: Parameter that callback function may use * * @return Length of data actually read * *******************************************************************************/ uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter) { uint32_t size = Ring_Buffer_Get_Length(rbType); if (readCb == NULL) { return 0; } if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no data */ if (!size) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } /* Ring buffer do not have enough data */ if (size < length) { length = size; } /* Get size of space remained in current mirror */ size = rbType->size - rbType->readIndex; if (size > length) { /* Read all data needed */ readCb(parameter, &rbType->pointer[rbType->readIndex], length); rbType->readIndex += length; } else { /* Read two part of data in different mirror */ readCb(parameter, &rbType->pointer[rbType->readIndex], size); readCb(parameter, &rbType->pointer[0], length - size); rbType->readIndex = length - size; rbType->readMirror = ~rbType->readMirror; } if (rbType->unlock != NULL) { rbType->unlock(); } return length; } /****************************************************************************/ /** * @brief Copy data from ring buffer to data buffer function * * @param parameter: Pointer to destination pointer * @param data: Data buffer to copy * @param length: Length of data to copy * * @return None * *******************************************************************************/ static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length) { uint8_t **dest = (uint8_t **)parameter; ARCH_MemCpy_Fast(*dest, data, length); *dest += length; } /****************************************************************************/ /** * @brief Read ring buffer function * * @param rbType: Ring buffer type structure pointer * @param data: Buffer for data read * @param length: Length of data to read * * @return Length of data read actually * *******************************************************************************/ uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) { return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data); } /****************************************************************************/ /** * @brief Read 1 byte from ring buffer function * * @param rbType: Ring buffer type structure pointer * @param data: Data read * * @return Length of data actually read * *******************************************************************************/ uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data) { if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no data */ if (!Ring_Buffer_Get_Length(rbType)) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } /* Read data */ *data = rbType->pointer[rbType->readIndex]; /* Update read index and mirror */ if (rbType->readIndex == rbType->size - 1) { rbType->readIndex = 0; rbType->readMirror = ~rbType->readMirror; } else { rbType->readIndex++; } if (rbType->unlock != NULL) { rbType->unlock(); } return 1; } /****************************************************************************/ /** * @brief Read ring buffer function, do not remove from buffer actually * * @param rbType: Ring buffer type structure pointer * @param data: Buffer for data read * @param length: Length of data to read * * @return Length of data read actually * *******************************************************************************/ uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) { uint32_t size = Ring_Buffer_Get_Length(rbType); if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no data */ if (!size) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } /* Ring buffer do not have enough data */ if (size < length) { length = size; } /* Get size of space remained in current mirror */ size = rbType->size - rbType->readIndex; if (size > length) { /* Read all data needed */ ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length); } else { /* Read two part of data in different mirror */ ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size); ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size); } if (rbType->unlock != NULL) { rbType->unlock(); } return length; } /****************************************************************************/ /** * @brief Read 1 byte from ring buffer function, do not remove from buffer actually * * @param rbType: Ring buffer type structure pointer * @param data: Data read * * @return Length of data actually read * *******************************************************************************/ uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data) { if (rbType->lock != NULL) { rbType->lock(); } /* Ring buffer has no data */ if (!Ring_Buffer_Get_Length(rbType)) { if (rbType->unlock != NULL) { rbType->unlock(); } return 0; } /* Read data */ *data = rbType->pointer[rbType->readIndex]; if (rbType->unlock != NULL) { rbType->unlock(); } return 1; } /****************************************************************************/ /** * @brief Get length of data in ring buffer function * * @param rbType: Ring buffer type structure pointer * * @return Length of data * *******************************************************************************/ uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType) { uint32_t readMirror = 0; uint32_t writeMirror = 0; uint32_t readIndex = 0; uint32_t writeIndex = 0; uint32_t size = 0; if (rbType->lock != NULL) { rbType->lock(); } readMirror = rbType->readMirror; writeMirror = rbType->writeMirror; readIndex = rbType->readIndex; writeIndex = rbType->writeIndex; size = rbType->size; if (rbType->unlock != NULL) { rbType->unlock(); } if (readMirror == writeMirror) { return writeIndex - readIndex; } else { return size - (readIndex - writeIndex); } } /****************************************************************************/ /** * @brief Get space remained in ring buffer function * * @param rbType: Ring buffer type structure pointer * * @return Length of space remained * *******************************************************************************/ uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType) { return (rbType->size - Ring_Buffer_Get_Length(rbType)); } /****************************************************************************/ /** * @brief Get ring buffer status function * * @param rbType: Ring buffer type structure pointer * * @return Status of ring buffer * *******************************************************************************/ Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType) { if (rbType->lock != NULL) { rbType->lock(); } /* Judge empty or full */ if (rbType->readIndex == rbType->writeIndex) { if (rbType->readMirror == rbType->writeMirror) { if (rbType->unlock != NULL) { rbType->unlock(); } return RING_BUFFER_EMPTY; } else { if (rbType->unlock != NULL) { rbType->unlock(); } return RING_BUFFER_FULL; } } if (rbType->unlock != NULL) { rbType->unlock(); } return RING_BUFFER_PARTIAL; } /*@} end of group RING_BUFFER_Public_Functions */ /*@} end of group RING_BUFFER */ /*@} end of group BL_Common_Component */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/ring_buffer/ring_buffer.h ================================================ /** * @file ring_buffer.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __RING_BUFFER_H__ #define __RING_BUFFER_H__ #include "misc.h" /** @addtogroup BL_Common_Component * @{ */ /** @addtogroup RING_BUFFER * @{ */ /** @defgroup RING_BUFFER_Public_Types * @{ */ /** * @brief Ring buffer status type definition */ typedef enum { RING_BUFFER_EMPTY, /*!< Ring buffer is empty */ RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */ RING_BUFFER_FULL, /*!< Ring buffer is full */ } Ring_Buffer_Status_Type; /** * @brief Ring buffer structure definition */ typedef struct { uint8_t *pointer; /*!< Pointer of ring buffer */ uint8_t readMirror; /*!< Read mirror,used to judge empty or full */ uint32_t readIndex; /*!< Index of read address */ uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */ uint32_t writeIndex; /*!< Index of write address */ uint32_t size; /*!< Size of ring buffer */ void (*lock)(void); /*!< Lock ring buffer */ void (*unlock)(void); /*!< Unlock ring buffer */ } Ring_Buffer_Type; /*@} end of group RING_BUFFER_Public_Types */ /** @defgroup RING_BUFFER_Public_Constants * @{ */ /** @defgroup RING_BUFFER_STATUS_TYPE * @{ */ #define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \ ((type) == RING_BUFFER_PARTIAL) || \ ((type) == RING_BUFFER_FULL)) /*@} end of group RING_BUFFER_Public_Constants */ /** @defgroup RING_BUFFER_Public_Macros * @{ */ typedef void(ringBuffer_Lock_Callback)(void); typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t); typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t); /*@} end of group RING_BUFFER_Public_Macros */ /** @defgroup RING_BUFFER_Public_Functions * @{ */ BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb); BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType); uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter); uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data); uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data); uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter); uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data); uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data); uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType); uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType); Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType); /*@} end of group RING_BUFFER_Public_Functions */ /*@} end of group RING_BUFFER */ /*@} end of group BL_Common_Component */ #endif /* __RING_BUFFER_H__ */ ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.c ================================================ /** * @file softcrc.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "softcrc.h" #include "misc.h" // ---------------- POPULAR POLYNOMIALS ---------------- // CCITT: x^16 + x^12 + x^5 + x^0 (0x1021,init 0x0000) // CRC-16: x^16 + x^15 + x^2 + x^0 (0x8005,init 0xFFFF) // we use 0x8005 here and const uint8_t chCRCHTalbe[] = { 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40}; const uint8_t chCRCLTalbe[] = { 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40}; uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len) { uint8_t chCRCHi = 0xFF; uint8_t chCRCLo = 0xFF; uint16_t wIndex; uint8_t *data = (uint8_t *)dataIn; while (len--) { wIndex = chCRCLo ^ *data++; chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex]; chCRCHi = chCRCLTalbe[wIndex]; } return ((chCRCHi << 8) | chCRCLo); } /* x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ const uint32_t crc32Tab[256] = { 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d}; uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len) { uint32_t crc = 0; uint8_t *data = (uint8_t *)dataIn; crc = crc ^ 0xffffffff; while (len--) { crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8); } return crc ^ 0xffffffff; } /****************************************************************************** * Name: CRC-32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 * Poly: 0x4C11DB7 * Init: 0xFFFFFFF * Refin: True * Refout: True * Xorout: 0xFFFFFFF * Alias: CRC_32/ADCCP * Use: WinRAR,ect. *****************************************************************************/ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len) { uint8_t i; uint32_t crc = ~initial; // Initial value uint8_t *data = (uint8_t *)dataIn; while (len--) { crc ^= *data++; // crc ^= *data; data++; for (i = 0; i < 8; ++i) { if (crc & 1) { crc = (crc >> 1) ^ 0xEDB88320; // 0xEDB88320= reverse 0x04C11DB7 } else { crc = (crc >> 1); } } } return ~crc; } #ifndef BFLB_USE_ROM_DRIVER __WEAK__ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) { return BFLB_Soft_CRC32_Ex(0, dataIn, len); } #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/soft_crc/softcrc.h ================================================ /** * @file softcrc.h * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #ifndef __SOFTCRC_H__ #define __SOFTCRC_H__ #include "stdint.h" uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len); uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len); uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); #endif ================================================ FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.c ================================================ /** * @file timestamp.c * @brief * * Copyright (c) 2021 Bouffalolab team * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * */ #include "timestamp.h" #define FOUR_YEAR_DAY ((365 << 2) + 1) // The total number of days in a 4-year cycle #define TIMEZONE (8) // Beijing time Zone adjustment #define SEC_NUM_PER_DAY (24 * 60 * 60) #define SEC_NUM_PER_HOUR (60 * 60) #define SEC_NUM_PER_MINUTE (60) static uint8_t month_day[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; // 平年 static uint8_t Leap_month_day[12] = {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; // 闰年 /** * @bref judge if it is a leap year * @para year to be judge * @return 1：leap year 0： nonleap year */ bool check_leap_year(uint16_t year) { if (year % 4) { return false; } else { if ((year % 100 == 0) && (year % 400 != 0)) { return false; } else { return true; } } } void cal_weekday(rtc_time *beijing_time) { uint32_t y, m, d, w; y = beijing_time->year; m = beijing_time->month; d = beijing_time->day; if ((m == 1) || (m == 2)) { m += 12; y--; } /* 把一月和二月看成是上一年的十三月和十四月，例：如果是2004-1-10则换算成：2003-13-10来代入公式计算。 以公元元年为参考，公元元年1月1日为星期一
程序如下：
  利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)
  */
  w = (d + 2 * m + 3 * (m + 1) / 5 + y + y / 4 - y / 100 + y / 400 + 1) % 7;

  beijing_time->week = (uint8_t)w;
}

void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time) {
  uint32_t totle_day_num;
  uint32_t current_sec_num;

  uint16_t remain_day;

  uint16_t temp_year;

  uint8_t *p = NULL;

  totle_day_num   = unixtime / SEC_NUM_PER_DAY; // The total number of days
  current_sec_num = unixtime % SEC_NUM_PER_DAY; // The number of seconds this day

  /* use the number of seconds this day, To calculate hour\minute\second */
  beijing_time->hour   = current_sec_num / SEC_NUM_PER_HOUR;
  beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;
  beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;

  /* Adjust the time zone and check whether the date is +1 */
  beijing_time->hour += 8;
  if (beijing_time->hour > 23) {
    beijing_time->hour -= 24;
    totle_day_num++;
  }

  /* calculate year */
  beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle
  remain_day         = totle_day_num % FOUR_YEAR_DAY;              // remaining day nym( < 4 year )

  /* calculate year & day */
  temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
  while (remain_day >= temp_year) {
    beijing_time->year++;
    remain_day -= temp_year;
    temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
  }

  /* Calculate specific dates(month\day)*/
  p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;
  remain_day++; // The actual day starts at 1
  beijing_time->month = 0;
  while (remain_day > *(p + beijing_time->month)) {
    remain_day -= *(p + beijing_time->month);
    beijing_time->month++;
  }

  beijing_time->month++; // The actual month starts at 1
  beijing_time->day = remain_day;

  /*利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/

  beijing_time->week =
      beijing_time->day + 2 * beijing_time->month + 3 * (beijing_time->month + 1) / 5 + beijing_time->year + beijing_time->year / 4 - beijing_time->year / 100 + beijing_time->year / 400;

  cal_weekday(beijing_time);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/common/timestamp/timestamp.h
================================================
/**
 * @file timestamp.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef _TIMESTAMP_
#define _TIMESTAMP_

#include "stdint.h"
#include "stddef.h"
#include "stdbool.h"

typedef struct _rtc_time_t
{
	uint16_t year;
	uint8_t month;
	uint8_t day;
	uint8_t week;
	uint8_t hour;
	uint8_t minute;
	uint8_t second;
}rtc_time;

void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);

#endif




================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/bl_hci_wrapper/bl_hci_wrapper.c
================================================
/*****************************************************************************************
 *
 * @file bl_hci_wrapper.c
 *
 * @brief Bouffalo Lab hci wrapper functions
 *
 * Copyright (C) Bouffalo Lab 2018
 *
 * History: 2018-08 crealted by llgong @ Shanghai
 *
 *****************************************************************************************/

#include "bl_hci_wrapper.h"
#include "byteorder.h"
#include "errno.h"
#include "hci_driver.h"
#include "hci_host.h"
#include "hci_onchip.h"
#include 
#include 

#define DATA_MSG_CNT 10

struct rx_msg_struct data_msg[DATA_MSG_CNT];
struct k_queue       msg_queue;
#if defined(BFLB_BLE_NOTIFY_ADV_DISCARDED)
extern void ble_controller_notify_adv_discarded(uint8_t *adv_bd_addr, uint8_t adv_type);
#endif

struct rx_msg_struct *bl_find_valid_data_msg() {
  struct rx_msg_struct empty_msg;
  memset(&empty_msg, 0, sizeof(struct rx_msg_struct));

  for (int i = 0; i < DATA_MSG_CNT; i++) {
    if (!memcmp(&data_msg[i], &empty_msg, sizeof(struct rx_msg_struct))) {
      return (data_msg + i);
    }
  }

  return NULL;
}

int bl_onchiphci_send_2_controller(struct net_buf *buf) {
  uint16_t       opcode;
  uint16_t       dest_id = 0x00;
  uint8_t        buf_type;
  uint8_t        pkt_type;
  hci_pkt_struct pkt;

  buf_type = bt_buf_get_type(buf);
  switch (buf_type) {
  case BT_BUF_CMD: {
    struct bt_hci_cmd_hdr *chdr;

    if (buf->len < sizeof(struct bt_hci_cmd_hdr)) {
      return -EINVAL;
    }

    chdr = (void *)buf->data;

    if (buf->len < chdr->param_len) {
      return -EINVAL;
    }

    pkt_type = BT_HCI_CMD;
    opcode   = sys_le16_to_cpu(chdr->opcode);
    // move buf to the payload
    net_buf_pull(buf, sizeof(struct bt_hci_cmd_hdr));
    switch (opcode) {
    // ble refer to hci_cmd_desc_tab_le, for the ones of which dest_ll is BLE_CTRL
    case BT_HCI_OP_LE_CONN_UPDATE:
    case BT_HCI_OP_LE_READ_CHAN_MAP:
    case BT_HCI_OP_LE_READ_REMOTE_FEATURES:
    case BT_HCI_OP_LE_START_ENCRYPTION:
    case BT_HCI_OP_LE_LTK_REQ_REPLY:
    case BT_HCI_OP_LE_LTK_REQ_NEG_REPLY:
    case BT_HCI_OP_LE_CONN_PARAM_REQ_REPLY:
    case BT_HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY:
    case BT_HCI_OP_LE_SET_DATA_LEN:
    case BT_HCI_OP_LE_READ_PHY:
    case BT_HCI_OP_LE_SET_PHY:
    // bredr identify link id, according to dest_id
    case BT_HCI_OP_READ_REMOTE_FEATURES:
    case BT_HCI_OP_READ_REMOTE_EXT_FEATURES:
    case BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE: {
      // dest_id is connectin handle
      dest_id = buf->data[0];
    }
    default:
      break;
    }
    pkt.p.hci_cmd.opcode    = opcode;
    pkt.p.hci_cmd.param_len = chdr->param_len;
    pkt.p.hci_cmd.params    = buf->data;

    break;
  }

  case BT_BUF_ACL_OUT: {
    struct bt_hci_acl_hdr *acl;
    // connhandle +l2cap field
    uint16_t connhdl_l2cf, tlt_len;

    if (buf->len < sizeof(struct bt_hci_acl_hdr)) {
      return -EINVAL;
    }

    pkt_type     = BT_HCI_ACL_DATA;
    acl          = (void *)buf->data;
    tlt_len      = sys_le16_to_cpu(acl->len);
    connhdl_l2cf = sys_le16_to_cpu(acl->handle);
    // move buf to the payload
    net_buf_pull(buf, sizeof(struct bt_hci_acl_hdr));

    if (buf->len < tlt_len) {
      return -EINVAL;
    }

    // get connection_handle
    dest_id                   = bt_acl_handle(connhdl_l2cf);
    pkt.p.acl_data.conhdl     = dest_id;
    pkt.p.acl_data.pb_bc_flag = bt_acl_flags(connhdl_l2cf);
    pkt.p.acl_data.len        = tlt_len;
    pkt.p.acl_data.buffer     = (uint8_t *)buf->data;

    break;
  }

  default:
    return -EINVAL;
  }

  return bt_onchiphci_send(pkt_type, dest_id, &pkt);
}

void bl_packet_to_host(uint8_t pkt_type, uint16_t src_id, uint8_t *param, uint8_t param_len, struct net_buf *buf) {
  uint16_t tlt_len;
  bool     prio            = true;
  uint8_t  nb_h2c_cmd_pkts = 0x01;

  uint8_t *buf_data = net_buf_tail(buf);
  bt_buf_set_rx_adv(buf, false);

  switch (pkt_type) {
  case BT_HCI_CMD_CMP_EVT: {
    tlt_len     = BT_HCI_EVT_CC_PARAM_OFFSET + param_len;
    *buf_data++ = BT_HCI_EVT_CMD_COMPLETE;
    *buf_data++ = BT_HCI_CCEVT_HDR_PARLEN + param_len;
    *buf_data++ = nb_h2c_cmd_pkts;
    sys_put_le16(src_id, buf_data);
    buf_data += 2;
    memcpy(buf_data, param, param_len);
    break;
  }
  case BT_HCI_CMD_STAT_EVT: {
    tlt_len     = BT_HCI_CSEVT_LEN;
    *buf_data++ = BT_HCI_EVT_CMD_STATUS;
    *buf_data++ = BT_HCI_CSVT_PARLEN;
    *buf_data++ = *(uint8_t *)param;
    *buf_data++ = nb_h2c_cmd_pkts;
    sys_put_le16(src_id, buf_data);
    break;
  }
  case BT_HCI_LE_EVT: {
    prio = false;
    bt_buf_set_type(buf, BT_BUF_EVT);
    if (param[0] == BT_HCI_EVT_LE_ADVERTISING_REPORT) {
      bt_buf_set_rx_adv(buf, true);
    }
    tlt_len     = BT_HCI_EVT_LE_PARAM_OFFSET + param_len;
    *buf_data++ = BT_HCI_EVT_LE_META_EVENT;
    *buf_data++ = param_len;
    memcpy(buf_data, param, param_len);
    break;
  }
  case BT_HCI_EVT: {
    if (src_id != BT_HCI_EVT_NUM_COMPLETED_PACKETS) {
      prio = false;
    }
    bt_buf_set_type(buf, BT_BUF_EVT);
    tlt_len     = BT_HCI_EVT_LE_PARAM_OFFSET + param_len;
    *buf_data++ = src_id;
    *buf_data++ = param_len;
    memcpy(buf_data, param, param_len);
    break;
  }
#if defined(CONFIG_BT_CONN)
  case BT_HCI_ACL_DATA: {
    prio = false;
    bt_buf_set_type(buf, BT_BUF_ACL_IN);
    tlt_len = bt_onchiphci_hanlde_rx_acl(param, buf_data);
    break;
  }
#endif
  default: {
    net_buf_unref(buf);
    return;
  }
  }

  net_buf_add(buf, tlt_len);

  if (prio) {
    bt_recv_prio(buf);
  } else {
    hci_driver_enque_recvq(buf);
  }
}

void bl_trigger_queued_msg() {
  struct net_buf       *buf = NULL;
  struct rx_msg_struct *msg = NULL;

  do {
    unsigned int lock = irq_lock();

    if (k_queue_is_empty(&msg_queue)) {
      irq_unlock(lock);
      break;
    }

    if (bt_buf_get_rx_avail_cnt() <= CONFIG_BT_RX_BUF_RSV_COUNT) {
      irq_unlock(lock);
      break;
    }

    buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
    if (!buf) {
      irq_unlock(lock);
      break;
    }

    msg = k_fifo_get(&msg_queue, K_NO_WAIT);

    BT_ASSERT(msg);

    bl_packet_to_host(msg->pkt_type, msg->src_id, msg->param, msg->param_len, buf);

    irq_unlock(lock);

    if (msg->param) {
      k_free(msg->param);
    }
    memset(msg, 0, sizeof(struct rx_msg_struct));

  } while (buf);
}

static void bl_onchiphci_rx_packet_handler(uint8_t pkt_type, uint16_t src_id, uint8_t *param, uint8_t param_len) {
  struct net_buf       *buf    = NULL;
  struct rx_msg_struct *rx_msg = NULL;

  if (pkt_type == BT_HCI_CMD_CMP_EVT || pkt_type == BT_HCI_CMD_STAT_EVT) {
    buf = bt_buf_get_cmd_complete(K_FOREVER);
    bl_packet_to_host(pkt_type, src_id, param, param_len, buf);
    return;
  }
#if defined(CONFIG_BT_OBSERVER) || defined(CONFIG_BT_CENTRAL) || defined(CONFIG_BT_ALLROLES)
  else if (pkt_type == BT_HCI_LE_EVT && param[0] == BT_HCI_EVT_LE_ADVERTISING_REPORT) {
    if (bt_buf_get_rx_avail_cnt() <= CONFIG_BT_RX_BUF_RSV_COUNT) {
      BT_INFO("Discard adv report.");
#if defined(BFLB_BLE_NOTIFY_ADV_DISCARDED)
      ble_controller_notify_adv_discarded(¶m[4], param[2]);
#endif
      return;
    }
    buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
    if (buf)
      bl_packet_to_host(pkt_type, src_id, param, param_len, buf);
    return;
  }
#endif /*(CONFIG_BT_OBSERVER || CONFIG_BT_CENTRAL || CONFIG_BT_ALLROLES)*/
  else {
    if (pkt_type != BT_HCI_ACL_DATA) {
      /* Using the reserved buf (CONFIG_BT_RX_BUF_RSV_COUNT) firstly. */
      buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_NO_WAIT);
      if (buf) {
        bl_packet_to_host(pkt_type, src_id, param, param_len, buf);
        return;
      }
    }

    rx_msg = bl_find_valid_data_msg();
  }

  BT_ASSERT(rx_msg);

  rx_msg->pkt_type  = pkt_type;
  rx_msg->src_id    = src_id;
  rx_msg->param_len = param_len;
  if (param_len) {
    rx_msg->param = k_malloc(param_len);
    memcpy(rx_msg->param, param, param_len);
  }

  k_fifo_put(&msg_queue, rx_msg);

  bl_trigger_queued_msg();
}

uint8_t bl_onchiphci_interface_init(void) {
  for (int i = 0; i < DATA_MSG_CNT; i++) {
    memset(data_msg + i, 0, sizeof(struct rx_msg_struct));
  }

  k_queue_init(&msg_queue, DATA_MSG_CNT);

  return bt_onchiphci_interface_init(bl_onchiphci_rx_packet_handler);
}

void bl_onchiphci_interface_deinit(void) {
  struct rx_msg_struct *msg;

  do {
    msg = k_fifo_get(&msg_queue, K_NO_WAIT);
    if (msg) {
      if (msg->param) {
        k_free(msg->param);
      }
    } else {
      break;
    }
  } while (1);

  k_queue_free(&msg_queue);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/bl_hci_wrapper/bl_hci_wrapper.h
================================================
#ifndef __BL_HCI_WRAPPER_H__
#define __BL_HCI_WRAPPER_H__

#include "bluetooth.h"
#include "net/buf.h"

struct rx_msg_struct {
  uint8_t  pkt_type;
  uint16_t src_id;
  uint8_t *param;
  uint8_t  param_len;
} __packed;

typedef enum { DATA_TYPE_COMMAND = 1, DATA_TYPE_ACL = 2, DATA_TYPE_SCO = 3, DATA_TYPE_EVENT = 4 } serial_data_type_t;

uint8_t bl_onchiphci_interface_init(void);
void    bl_onchiphci_interface_deinit(void);
void    bl_trigger_queued_msg(void);
int     bl_onchiphci_send_2_controller(struct net_buf *buf);

#endif //__BL_CONTROLLER_H__

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/atomic_c.c
================================================
/*
 * Copyright (c) 2016 Intel Corporation
 * Copyright (c) 2011-2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file Atomic ops in pure C
 *
 * This module provides the atomic operators for processors
 * which do not support native atomic operations.
 *
 * The atomic operations are guaranteed to be atomic with respect
 * to interrupt service routines, and to operations performed by peer
 * processors.
 *
 * (originally from x86's atomic.c)
 */

#include "bl_port.h"
#include 
// #include 
// #include 

/**
 *
 * @brief Atomic compare-and-set primitive
 *
 * This routine provides the compare-and-set operator. If the original value at
 *  equals , then  is stored at  and the
 * function returns 1.
 *
 * If the original value at  does not equal , then the store
 * is not done and the function returns 0.
 *
 * The reading of the original value at , the comparison,
 * and the write of the new value (if it occurs) all happen atomically with
 * respect to both interrupts and accesses of other processors to .
 *
 * @param target address to be tested
 * @param old_value value to compare against
 * @param new_value value to compare against
 * @return Returns 1 if  is written, 0 otherwise.
 */
int atomic_cas(atomic_t *target, atomic_val_t old_value, atomic_val_t new_value) {
  unsigned int key;
  int          ret = 0;

  key = irq_lock();

  if (*target == old_value) {
    *target = new_value;
    ret     = 1;
  }

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic addition primitive
 *
 * This routine provides the atomic addition operator. The  is
 * atomically added to the value at , placing the result at ,
 * and the old value from  is returned.
 *
 * @param target memory location to add to
 * @param value the value to add
 *
 * @return The previous value from 
 */
atomic_val_t atomic_add(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  *target += value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic subtraction primitive
 *
 * This routine provides the atomic subtraction operator. The  is
 * atomically subtracted from the value at , placing the result at
 * , and the old value from  is returned.
 *
 * @param target the memory location to subtract from
 * @param value the value to subtract
 *
 * @return The previous value from 
 */
atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  *target -= value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic increment primitive
 *
 * @param target memory location to increment
 *
 * This routine provides the atomic increment operator. The value at 
 * is atomically incremented by 1, and the old value from  is returned.
 *
 * @return The value from  before the increment
 */
atomic_val_t atomic_inc(atomic_t *target) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  (*target)++;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic decrement primitive
 *
 * @param target memory location to decrement
 *
 * This routine provides the atomic decrement operator. The value at 
 * is atomically decremented by 1, and the old value from  is returned.
 *
 * @return The value from  prior to the decrement
 */
atomic_val_t atomic_dec(atomic_t *target) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  (*target)--;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic get primitive
 *
 * @param target memory location to read from
 *
 * This routine provides the atomic get primitive to atomically read
 * a value from . It simply does an ordinary load.  Note that 
 * is expected to be aligned to a 4-byte boundary.
 *
 * @return The value read from 
 */
atomic_val_t atomic_get(const atomic_t *target) { return *target; }

/**
 *
 * @brief Atomic get-and-set primitive
 *
 * This routine provides the atomic set operator. The  is atomically
 * written at  and the previous value at  is returned.
 *
 * @param target the memory location to write to
 * @param value the value to write
 *
 * @return The previous value from 
 */
atomic_val_t atomic_set(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret     = *target;
  *target = value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic clear primitive
 *
 * This routine provides the atomic clear operator. The value of 0 is atomically
 * written at  and the previous value at  is returned. (Hence,
 * atomic_clear(pAtomicVar) is equivalent to atomic_set(pAtomicVar, 0).)
 *
 * @param target the memory location to write
 *
 * @return The previous value from 
 */
atomic_val_t atomic_clear(atomic_t *target) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret     = *target;
  *target = 0;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic bitwise inclusive OR primitive
 *
 * This routine provides the atomic bitwise inclusive OR operator. The 
 * is atomically bitwise OR'ed with the value at , placing the result
 * at , and the previous value at  is returned.
 *
 * @param target the memory location to be modified
 * @param value the value to OR
 *
 * @return The previous value from 
 */
atomic_val_t atomic_or(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  *target |= value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic bitwise exclusive OR (XOR) primitive
 *
 * This routine provides the atomic bitwise exclusive OR operator. The 
 * is atomically bitwise XOR'ed with the value at , placing the result
 * at , and the previous value at  is returned.
 *
 * @param target the memory location to be modified
 * @param value the value to XOR
 *
 * @return The previous value from 
 */
atomic_val_t atomic_xor(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  *target ^= value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic bitwise AND primitive
 *
 * This routine provides the atomic bitwise AND operator. The  is
 * atomically bitwise AND'ed with the value at , placing the result
 * at , and the previous value at  is returned.
 *
 * @param target the memory location to be modified
 * @param value the value to AND
 *
 * @return The previous value from 
 */
atomic_val_t atomic_and(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret = *target;
  *target &= value;

  irq_unlock(key);

  return ret;
}

/**
 *
 * @brief Atomic bitwise NAND primitive
 *
 * This routine provides the atomic bitwise NAND operator. The  is
 * atomically bitwise NAND'ed with the value at , placing the result
 * at , and the previous value at  is returned.
 *
 * @param target the memory location to be modified
 * @param value the value to NAND
 *
 * @return The previous value from 
 */
atomic_val_t atomic_nand(atomic_t *target, atomic_val_t value) {
  unsigned int key;
  atomic_val_t ret;

  key = irq_lock();

  ret     = *target;
  *target = ~(*target & value);

  irq_unlock(key);

  return ret;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/buf.c
================================================
/* buf.c - Buffer management */

/*
 * Copyright (c) 2015 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#define LOG_MODULE_NAME net_buf

#if !defined(BFLB_BLE)
#define LOG_LEVEL CONFIG_NET_BUF_LOG_LEVEL
#endif

#include 
// LOG_MODULE_REGISTER(LOG_MODULE_NAME);

#include 
#include 
#include 
#include 
#include 
#include 
#if defined(BFLB_BLE)
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#include "bl_port.h"
#endif
#include "bl_hci_wrapper.h"
#endif

#if (BFLB_STATIC_ALLOC_MEM)
#include "l2cap.h"
#endif

#if defined(CONFIG_NET_BUF_LOG)
#define NET_BUF_DBG(fmt, ...)  LOG_DBG("(%p) " fmt, k_current_get(), ##__VA_ARGS__)
#define NET_BUF_ERR(fmt, ...)  LOG_ERR(fmt, ##__VA_ARGS__)
#define NET_BUF_WARN(fmt, ...) LOG_WRN(fmt, ##__VA_ARGS__)
#define NET_BUF_INFO(fmt, ...) LOG_INF(fmt, ##__VA_ARGS__)
#define NET_BUF_ASSERT(cond)                                                                                                                                                                           \
  do {                                                                                                                                                                                                 \
    if (!(cond)) {                                                                                                                                                                                     \
      NET_BUF_ERR("assert: '" #cond "' failed");                                                                                                                                                       \
    }                                                                                                                                                                                                  \
  } while (0)
#else

#define NET_BUF_DBG(fmt, ...)
#define NET_BUF_ERR(fmt, ...)
#define NET_BUF_WARN(fmt, ...)
#define NET_BUF_INFO(fmt, ...)
#define NET_BUF_ASSERT(cond)
#endif /* CONFIG_NET_BUF_LOG */

#if defined(CONFIG_NET_BUF_WARN_ALLOC_INTERVAL) && (CONFIG_NET_BUF_WARN_ALLOC_INTERVAL > 0)
// #if CONFIG_NET_BUF_WARN_ALLOC_INTERVAL > 0
#define WARN_ALLOC_INTERVAL K_SECONDS(CONFIG_NET_BUF_WARN_ALLOC_INTERVAL)
#else
#define WARN_ALLOC_INTERVAL K_FOREVER
#endif

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
extern struct net_buf_pool hci_cmd_pool;
extern struct net_buf_pool hci_rx_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t hci_cmd_data_pool[CONFIG_BT_HCI_CMD_COUNT * BT_BUF_RX_SIZE];
__attribute__((section(".tcm_data"))) u8_t hci_rx_data_pool[CONFIG_BT_RX_BUF_COUNT * BT_BUF_RX_SIZE];
#endif
#if defined(CONFIG_BT_CONN)
extern struct net_buf_pool acl_tx_pool;
extern struct net_buf_pool num_complete_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t acl_tx_data_pool[CONFIG_BT_L2CAP_TX_BUF_COUNT * BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU)];
__attribute__((section(".tcm_data"))) u8_t num_complete_data_pool[1 * BT_BUF_RX_SIZE];
#endif
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
extern struct net_buf_pool prep_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t prep_data_pool[CONFIG_BT_ATT_PREPARE_COUNT * BT_ATT_MTU];
#endif
#endif
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
extern struct net_buf_pool acl_in_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t acl_in_data_pool[CONFIG_BT_ACL_RX_COUNT * ACL_IN_SIZE];
#endif
#endif
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
extern struct net_buf_pool frag_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t frag_data_pool[CONFIG_BT_L2CAP_TX_FRAG_COUNT * FRAG_SIZE];
#endif
#endif
#endif // CONFIG_BT_CONN
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
extern struct net_buf_pool discardable_pool;
#if (BFLB_STATIC_ALLOC_MEM)
__attribute__((section(".tcm_data"))) u8_t discardable_data_pool[CONFIG_BT_DISCARDABLE_BUF_COUNT * BT_BUF_RX_SIZE];
#endif
#endif
#ifdef CONFIG_BT_MESH
extern struct net_buf_pool adv_buf_pool;
extern struct net_buf_pool loopback_buf_pool;
#if defined(CONFIG_BT_MESH_FRIEND)
extern struct net_buf_pool friend_buf_pool;
#endif // CONFIG_BT_MESH_FRIEND
#endif
#if defined(CONFIG_BT_BREDR)
extern struct net_buf_pool br_sig_pool;
extern struct net_buf_pool sdp_pool;
extern struct net_buf_pool hf_pool;
extern struct net_buf_pool dummy_pool;
#endif

#if defined(CONFIG_AUTO_PTS)
extern struct net_buf_pool server_pool;
extern struct net_buf_pool data_pool;
#endif

struct net_buf_pool *_net_buf_pool_list[] = {
    &hci_cmd_pool,    &hci_rx_pool,

#if defined(CONFIG_BT_CONN)
    &acl_tx_pool,     &num_complete_pool,
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
    &prep_pool,
#endif
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
    &acl_in_pool,
#endif
#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0
    &frag_pool,
#endif
#endif // defined(CONFIG_BT_CONN)
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
    discardable_pool,
#endif
#ifdef CONFIG_BT_MESH
    &adv_buf_pool,    &loopback_buf_pool,
#if defined(CONFIG_BT_MESH_FRIEND)
    &friend_buf_pool,
#endif
#endif
#if defined(CONFIG_BT_BREDR)
    &sdp_pool,        &br_sig_pool,       &hf_pool, &dummy_pool,
#endif
#if defined(CONFIG_AUTO_PTS)
    &server_pool,     &data_pool,
#endif
};

#else
extern struct net_buf_pool _net_buf_pool_list[];
#endif // BFLB_DYNAMIC_ALLOC_MEM

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#if (BFLB_STATIC_ALLOC_MEM)
void net_buf_init(u8_t buf_type, struct net_buf_pool *buf_pool, u16_t buf_count, size_t data_size, destroy_cb_t destroy)
#else
void net_buf_init(struct net_buf_pool *buf_pool, u16_t buf_count, size_t data_size, destroy_cb_t destroy)
#endif
{
  struct net_buf_pool_fixed *buf_fixed;
  buf_pool->alloc             = (struct net_buf_data_alloc *)k_malloc(sizeof(struct net_buf_data_alloc));
  buf_pool->alloc->alloc_data = (struct net_buf_pool_fixed *)k_malloc(sizeof(struct net_buf_pool_fixed));

  buf_fixed = (struct net_buf_pool_fixed *)buf_pool->alloc->alloc_data;

  buf_pool->alloc->cb  = &net_buf_fixed_cb;
  buf_fixed->data_size = data_size;
#if (BFLB_STATIC_ALLOC_MEM)
  switch (buf_type) {
  case HCI_CMD:
    buf_fixed->data_pool = hci_cmd_data_pool;
    break;
  case HCI_RX:
    buf_fixed->data_pool = hci_rx_data_pool;
    break;
#if defined(CONFIG_BT_CONN)
  case ACL_TX:
    buf_fixed->data_pool = acl_tx_data_pool;
    break;
  case NUM_COMPLETE:
    buf_fixed->data_pool = num_complete_data_pool;
    break;
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  case PREP:
    buf_fixed->data_pool = prep_data_pool;
    break;
#endif
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  case ACL_IN:
    buf_fixed->data_pool = acl_in_data_pool;
    break;
#endif
#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0
  case FRAG:
    buf_fixed->data_pool = frag_data_pool;
    break;
#endif
#endif
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
  case DISCARDABLE:
    buf_fixed->data_pool = discardable_data_pool;
    break;
#endif
  default:
    break;
  }
#else
  buf_fixed->data_pool = (u8_t *)k_malloc(buf_count * data_size);
#endif
  buf_pool->__bufs       = (struct net_buf *)k_malloc(buf_count * sizeof(struct net_buf));
  buf_pool->buf_count    = buf_count;
  buf_pool->uninit_count = buf_count;
#if defined(CONFIG_NET_BUF_POOL_USAGE)
  buf_pool->avail_count = buf_count;
#endif
  buf_pool->destroy = destroy;

  k_lifo_init(&(buf_pool->free), buf_count);
}

void net_buf_deinit(struct net_buf_pool *buf_pool) {
  extern void bt_delete_queue(struct k_fifo * queue_to_del);
  bt_delete_queue((struct k_fifo *)(&(buf_pool->free)));

  struct net_buf_pool_fixed *buf_fixed = (struct net_buf_pool_fixed *)buf_pool->alloc->alloc_data;
#if !(BFLB_STATIC_ALLOC_MEM)
  k_free(buf_fixed->data_pool);
#endif
  k_free(buf_pool->__bufs);
  k_free(buf_pool->alloc->alloc_data);
  k_free(buf_pool->alloc);
}
#endif

struct net_buf_pool *net_buf_pool_get(int id) {
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
  return _net_buf_pool_list[id];
#else
  return &_net_buf_pool_list[id];
#endif
}

static int pool_id(struct net_buf_pool *pool) {
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
  int index;

  for (index = 0; index < (sizeof(_net_buf_pool_list) / 4); index++) {
    if (_net_buf_pool_list[index] == pool) {
      break;
    }
  }
  NET_BUF_ASSERT(index < (sizeof(_net_buf_pool_list) / 4));
  return index;
#else
  return pool - _net_buf_pool_list;
#endif
}

int net_buf_id(struct net_buf *buf) {
  struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);

  return buf - pool->__bufs;
}

static inline struct net_buf *pool_get_uninit(struct net_buf_pool *pool, u16_t uninit_count) {
  struct net_buf *buf;

  buf = &pool->__bufs[pool->buf_count - uninit_count];

  buf->pool_id = pool_id(pool);

  return buf;
}

void net_buf_reset(struct net_buf *buf) {
  NET_BUF_ASSERT(buf->flags == 0U);
  NET_BUF_ASSERT(buf->frags == NULL);

  net_buf_simple_reset(&buf->b);
}

#if !defined(BFLB_BLE)
static u8_t *generic_data_ref(struct net_buf *buf, u8_t *data) {
  u8_t *ref_count;

  ref_count = data - 1;
  (*ref_count)++;

  return data;
}

static u8_t *mem_pool_data_alloc(struct net_buf *buf, size_t *size, s32_t timeout) {
  struct net_buf_pool *buf_pool = net_buf_pool_get(buf->pool_id);
  struct k_mem_pool   *pool     = buf_pool->alloc->alloc_data;
  struct k_mem_block   block;
  u8_t                *ref_count;

  /* Reserve extra space for k_mem_block_id and ref-count (u8_t) */
  if (k_mem_pool_alloc(pool, &block, sizeof(struct k_mem_block_id) + 1 + *size, timeout)) {
    return NULL;
  }

  /* save the block descriptor info at the start of the actual block */
  memcpy(block.data, &block.id, sizeof(block.id));

  ref_count  = (u8_t *)block.data + sizeof(block.id);
  *ref_count = 1U;

  /* Return pointer to the byte following the ref count */
  return ref_count + 1;
}

static void mem_pool_data_unref(struct net_buf *buf, u8_t *data) {
  struct k_mem_block_id id;
  u8_t                 *ref_count;

  ref_count = data - 1;
  if (--(*ref_count)) {
    return;
  }

  /* Need to copy to local variable due to alignment */
  memcpy(&id, ref_count - sizeof(id), sizeof(id));
  k_mem_pool_free_id(&id);
}

const struct net_buf_data_cb net_buf_var_cb = {
    .alloc = mem_pool_data_alloc,
    .ref   = generic_data_ref,
    .unref = mem_pool_data_unref,
};
#endif

static u8_t *fixed_data_alloc(struct net_buf *buf, size_t *size, s32_t timeout) {
  struct net_buf_pool             *pool  = net_buf_pool_get(buf->pool_id);
  const struct net_buf_pool_fixed *fixed = pool->alloc->alloc_data;

  *size = MIN(fixed->data_size, *size);

  return fixed->data_pool + fixed->data_size * net_buf_id(buf);
}

static void fixed_data_unref(struct net_buf *buf, u8_t *data) { /* Nothing needed for fixed-size data pools */ }

const struct net_buf_data_cb net_buf_fixed_cb = {
    .alloc = fixed_data_alloc,
    .unref = fixed_data_unref,
};

#if defined(CONFIG_HEAP_MEM_POOL_SIZE) && (CONFIG_HEAP_MEM_POOL_SIZE > 0)

static u8_t *heap_data_alloc(struct net_buf *buf, size_t *size, s32_t timeout) {
  u8_t *ref_count;

  ref_count = k_malloc(1 + *size);
  if (!ref_count) {
    return NULL;
  }

  *ref_count = 1U;

  return ref_count + 1;
}

static void heap_data_unref(struct net_buf *buf, u8_t *data) {
  u8_t *ref_count;

  ref_count = data - 1;
  if (--(*ref_count)) {
    return;
  }

  k_free(ref_count);
}

static const struct net_buf_data_cb net_buf_heap_cb = {
    .alloc = heap_data_alloc,
    .ref   = generic_data_ref,
    .unref = heap_data_unref,
};

const struct net_buf_data_alloc net_buf_heap_alloc = {
    .cb = &net_buf_heap_cb,
};

#endif /* CONFIG_HEAP_MEM_POOL_SIZE > 0 */

static u8_t *data_alloc(struct net_buf *buf, size_t *size, s32_t timeout) {
  struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);

  return pool->alloc->cb->alloc(buf, size, timeout);
}

static u8_t *data_ref(struct net_buf *buf, u8_t *data) {
  struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);

  return pool->alloc->cb->ref(buf, data);
}

static void data_unref(struct net_buf *buf, u8_t *data) {
  struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);

  if (buf->flags & NET_BUF_EXTERNAL_DATA) {
    return;
  }

  pool->alloc->cb->unref(buf, data);
}

#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_len_debug(struct net_buf_pool *pool, size_t size, s32_t timeout, const char *func, int line)
#else
struct net_buf *net_buf_alloc_len(struct net_buf_pool *pool, size_t size, s32_t timeout)
#endif
{
  u32_t           alloc_start = k_uptime_get_32();
  struct net_buf *buf;
  unsigned int    key;

  NET_BUF_ASSERT(pool);

  NET_BUF_DBG("%s():%d: pool %p size %zu timeout %d", func, line, pool, size, timeout);

#if (BFLB_BT_CO_THREAD)
  extern struct k_thread co_thread_data;
  if (k_is_current_thread(&co_thread_data))
    timeout = K_NO_WAIT;
#endif

  /* We need to lock interrupts temporarily to prevent race conditions
   * when accessing pool->uninit_count.
   */
  key = irq_lock();

  /* If there are uninitialized buffers we're guaranteed to succeed
   * with the allocation one way or another.
   */
  if (pool->uninit_count) {
    u16_t uninit_count;

    /* If this is not the first access to the pool, we can
     * be opportunistic and try to fetch a previously used
     * buffer from the LIFO with K_NO_WAIT.
     */
    if (pool->uninit_count < pool->buf_count) {
      buf = k_lifo_get(&pool->free, K_NO_WAIT);
      if (buf) {
        irq_unlock(key);
        goto success;
      }
    }

    uninit_count = pool->uninit_count--;
    irq_unlock(key);

    buf = pool_get_uninit(pool, uninit_count);
    goto success;
  }

  irq_unlock(key);

#if defined(CONFIG_NET_BUF_LOG) && (CONFIG_NET_BUF_LOG_LEVEL >= LOG_LEVEL_WRN)
  if (timeout == K_FOREVER) {
    u32_t ref = k_uptime_get_32();
    buf       = k_lifo_get(&pool->free, K_NO_WAIT);
    while (!buf) {
#if defined(CONFIG_NET_BUF_POOL_USAGE)
      NET_BUF_WARN("%s():%d: Pool %s low on buffers.", func, line, pool->name);
#else
      NET_BUF_WARN("%s():%d: Pool %p low on buffers.", func, line, pool);
#endif
      buf = k_lifo_get(&pool->free, WARN_ALLOC_INTERVAL);
#if defined(CONFIG_NET_BUF_POOL_USAGE)
      NET_BUF_WARN("%s():%d: Pool %s blocked for %u secs", func, line, pool->name, (k_uptime_get_32() - ref) / MSEC_PER_SEC);
#else
      NET_BUF_WARN("%s():%d: Pool %p blocked for %u secs", func, line, pool, (k_uptime_get_32() - ref) / MSEC_PER_SEC);
#endif
    }
  } else {
    buf = k_lifo_get(&pool->free, timeout);
  }
#else
  buf = k_lifo_get(&pool->free, timeout);
#endif
  if (!buf) {
    NET_BUF_ERR("%s():%d: Failed to get free buffer", func, line);
    return NULL;
  }

success:
  NET_BUF_DBG("allocated buf %p", buf);

  if (size) {
    if (timeout != K_NO_WAIT && timeout != K_FOREVER) {
      u32_t diff = k_uptime_get_32() - alloc_start;

      timeout -= MIN(timeout, diff);
    }

    buf->__buf = data_alloc(buf, &size, timeout);
    if (!buf->__buf) {
      NET_BUF_ERR("%s():%d: Failed to allocate data", func, line);
      net_buf_destroy(buf);
      return NULL;
    }
  } else {
    buf->__buf = NULL;
  }

  buf->ref   = 1U;
  buf->flags = 0U;
  buf->frags = NULL;
  buf->size  = size;
  net_buf_reset(buf);

#if defined(CONFIG_NET_BUF_POOL_USAGE)
  pool->avail_count--;
  NET_BUF_ASSERT(pool->avail_count >= 0);
#endif

  return buf;
}

#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_fixed_debug(struct net_buf_pool *pool, s32_t timeout, const char *func, int line) {
  const struct net_buf_pool_fixed *fixed = pool->alloc->alloc_data;

  return net_buf_alloc_len_debug(pool, fixed->data_size, timeout, func, line);
}
#else
struct net_buf *net_buf_alloc_fixed(struct net_buf_pool *pool, s32_t timeout) {
  const struct net_buf_pool_fixed *fixed = pool->alloc->alloc_data;

  return net_buf_alloc_len(pool, fixed->data_size, timeout);
}
#endif

#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_with_data_debug(struct net_buf_pool *pool, void *data, size_t size, s32_t timeout, const char *func, int line)
#else
struct net_buf *net_buf_alloc_with_data(struct net_buf_pool *pool, void *data, size_t size, s32_t timeout)
#endif
{
  struct net_buf *buf;

#if defined(CONFIG_NET_BUF_LOG)
  buf = net_buf_alloc_len_debug(pool, 0, timeout, func, line);
#else
  buf = net_buf_alloc_len(pool, 0, timeout);
#endif
  if (!buf) {
    return NULL;
  }

  buf->__buf = data;
  buf->data  = data;
  buf->size  = size;
  buf->len   = size;
  buf->flags = NET_BUF_EXTERNAL_DATA;

  return buf;
}

#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_get_debug(struct k_fifo *fifo, s32_t timeout, const char *func, int line)
#else
struct net_buf *net_buf_get(struct k_fifo *fifo, s32_t timeout)
#endif
{
  struct net_buf *buf, *frag;

  NET_BUF_DBG("%s():%d: fifo %p timeout %d", func, line, fifo, timeout);

  buf = k_fifo_get(fifo, timeout);
  if (!buf) {
    return NULL;
  }

  NET_BUF_DBG("%s():%d: buf %p fifo %p", func, line, buf, fifo);

  /* Get any fragments belonging to this buffer */
  for (frag = buf; (frag->flags & NET_BUF_FRAGS); frag = frag->frags) {
    frag->frags = k_fifo_get(fifo, K_NO_WAIT);
    NET_BUF_ASSERT(frag->frags);

    /* The fragments flag is only for FIFO-internal usage */
    frag->flags &= ~NET_BUF_FRAGS;
  }

  /* Mark the end of the fragment list */
  frag->frags = NULL;

  return buf;
}

void net_buf_simple_init_with_data(struct net_buf_simple *buf, void *data, size_t size) {
  buf->__buf = data;
  buf->data  = data;
  buf->size  = size;
  buf->len   = size;
}

void net_buf_simple_reserve(struct net_buf_simple *buf, size_t reserve) {
  NET_BUF_ASSERT(buf);
  NET_BUF_ASSERT(buf->len == 0U);
  NET_BUF_DBG("buf %p reserve %zu", buf, reserve);

  buf->data = buf->__buf + reserve;
}

void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf) {
  struct net_buf *tail;
  unsigned int    key;

  NET_BUF_ASSERT(list);
  NET_BUF_ASSERT(buf);

  for (tail = buf; tail->frags; tail = tail->frags) {
    tail->flags |= NET_BUF_FRAGS;
  }

  key = irq_lock();
  sys_slist_append_list(list, &buf->node, &tail->node);
  irq_unlock(key);
}

struct net_buf *net_buf_slist_get(sys_slist_t *list) {
  struct net_buf *buf, *frag;
  unsigned int    key;

  NET_BUF_ASSERT(list);

  key = irq_lock();
  buf = (void *)sys_slist_get(list);
  irq_unlock(key);

  if (!buf) {
    return NULL;
  }

  /* Get any fragments belonging to this buffer */
  for (frag = buf; (frag->flags & NET_BUF_FRAGS); frag = frag->frags) {
    key         = irq_lock();
    frag->frags = (void *)sys_slist_get(list);
    irq_unlock(key);

    NET_BUF_ASSERT(frag->frags);

    /* The fragments flag is only for list-internal usage */
    frag->flags &= ~NET_BUF_FRAGS;
  }

  /* Mark the end of the fragment list */
  frag->frags = NULL;

  return buf;
}

void net_buf_put(struct k_fifo *fifo, struct net_buf *buf) {
  struct net_buf *tail;

  NET_BUF_ASSERT(fifo);
  NET_BUF_ASSERT(buf);

  for (tail = buf; tail->frags; tail = tail->frags) {
    tail->flags |= NET_BUF_FRAGS;
  }

  k_fifo_put_list(fifo, buf, tail);
}

#if defined(CONFIG_NET_BUF_LOG)
void net_buf_unref_debug(struct net_buf *buf, const char *func, int line)
#else
void net_buf_unref(struct net_buf *buf)
#endif
{
  NET_BUF_ASSERT(buf);

  while (buf) {
    struct net_buf      *frags = buf->frags;
    struct net_buf_pool *pool;

#if defined(CONFIG_NET_BUF_LOG)
    if (!buf->ref) {
      NET_BUF_ERR("%s():%d: buf %p double free", func, line, buf);
      return;
    }
#endif
    NET_BUF_DBG("buf %p ref %u pool_id %u frags %p", buf, buf->ref, buf->pool_id, buf->frags);

    unsigned int key = irq_lock(); /* Added by bouffalo lab, to protect ref decrease */
    if (--buf->ref > 0) {
      irq_unlock(key); /* Added by bouffalo lab */
      return;
    }
    irq_unlock(key); /* Added by bouffalo lab */

    if (buf->__buf) {
      data_unref(buf, buf->__buf);
      buf->__buf = NULL;
    }

    buf->data  = NULL;
    buf->frags = NULL;

    pool = net_buf_pool_get(buf->pool_id);

#if defined(CONFIG_NET_BUF_POOL_USAGE)
    pool->avail_count++;
    NET_BUF_ASSERT(pool->avail_count <= pool->buf_count);
#endif

    if (pool->destroy) {
      pool->destroy(buf);
    } else {
      net_buf_destroy(buf);
    }

    buf = frags;

#if defined(BFLB_BLE)
    if (pool == &hci_rx_pool) {
      bl_trigger_queued_msg();
      return;
    }
#endif
  }
}

struct net_buf *net_buf_ref(struct net_buf *buf) {
  NET_BUF_ASSERT(buf);

  NET_BUF_DBG("buf %p (old) ref %u pool_id %u", buf, buf->ref, buf->pool_id);

  unsigned int key = irq_lock(); /* Added by bouffalo lab,  to protect ref increase */
  buf->ref++;
  irq_unlock(key); /* Added by bouffalo lab */
  return buf;
}

struct net_buf *net_buf_clone(struct net_buf *buf, s32_t timeout) {
  u32_t                alloc_start = k_uptime_get_32();
  struct net_buf_pool *pool;
  struct net_buf      *clone;

  NET_BUF_ASSERT(buf);

  pool = net_buf_pool_get(buf->pool_id);

  clone = net_buf_alloc_len(pool, 0, timeout);
  if (!clone) {
    return NULL;
  }

  /* If the pool supports data referencing use that. Otherwise
   * we need to allocate new data and make a copy.
   */
  if (pool->alloc->cb->ref && !(buf->flags & NET_BUF_EXTERNAL_DATA)) {
    clone->__buf = data_ref(buf, buf->__buf);
    clone->data  = buf->data;
    clone->len   = buf->len;
    clone->size  = buf->size;
  } else {
    size_t size = buf->size;

    if (timeout != K_NO_WAIT && timeout != K_FOREVER) {
      u32_t diff = k_uptime_get_32() - alloc_start;

      timeout -= MIN(timeout, diff);
    }

    clone->__buf = data_alloc(clone, &size, timeout);
    if (!clone->__buf || size < buf->size) {
      net_buf_destroy(clone);
      return NULL;
    }

    clone->size = size;
    clone->data = clone->__buf + net_buf_headroom(buf);
    net_buf_add_mem(clone, buf->data, buf->len);
  }

  return clone;
}

struct net_buf *net_buf_frag_last(struct net_buf *buf) {
  NET_BUF_ASSERT(buf);

  while (buf->frags) {
    buf = buf->frags;
  }

  return buf;
}

void net_buf_frag_insert(struct net_buf *parent, struct net_buf *frag) {
  NET_BUF_ASSERT(parent);
  NET_BUF_ASSERT(frag);

  if (parent->frags) {
    net_buf_frag_last(frag)->frags = parent->frags;
  }
  /* Take ownership of the fragment reference */
  parent->frags = frag;
}

struct net_buf *net_buf_frag_add(struct net_buf *head, struct net_buf *frag) {
  NET_BUF_ASSERT(frag);

  if (!head) {
    return net_buf_ref(frag);
  }

  net_buf_frag_insert(net_buf_frag_last(head), frag);

  return head;
}

#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_frag_del_debug(struct net_buf *parent, struct net_buf *frag, const char *func, int line)
#else
struct net_buf *net_buf_frag_del(struct net_buf *parent, struct net_buf *frag)
#endif
{
  struct net_buf *next_frag;

  NET_BUF_ASSERT(frag);

  if (parent) {
    NET_BUF_ASSERT(parent->frags);
    NET_BUF_ASSERT(parent->frags == frag);
    parent->frags = frag->frags;
  }

  next_frag = frag->frags;

  frag->frags = NULL;

#if defined(CONFIG_NET_BUF_LOG)
  net_buf_unref_debug(frag, func, line);
#else
  net_buf_unref(frag);
#endif

  return next_frag;
}

size_t net_buf_linearize(void *dst, size_t dst_len, struct net_buf *src, size_t offset, size_t len) {
  struct net_buf *frag;
  size_t          to_copy;
  size_t          copied;

  len = MIN(len, dst_len);

  frag = src;

  /* find the right fragment to start copying from */
  while (frag && offset >= frag->len) {
    offset -= frag->len;
    frag = frag->frags;
  }

  /* traverse the fragment chain until len bytes are copied */
  copied = 0;
  while (frag && len > 0) {
    to_copy = MIN(len, frag->len - offset);
    memcpy((u8_t *)dst + copied, frag->data + offset, to_copy);

    copied += to_copy;

    /* to_copy is always <= len */
    len -= to_copy;
    frag = frag->frags;

    /* after the first iteration, this value will be 0 */
    offset = 0;
  }

  return copied;
}

/* This helper routine will append multiple bytes, if there is no place for
 * the data in current fragment then create new fragment and add it to
 * the buffer. It assumes that the buffer has at least one fragment.
 */
size_t net_buf_append_bytes(struct net_buf *buf, size_t len, const void *value, s32_t timeout, net_buf_allocator_cb allocate_cb, void *user_data) {
  struct net_buf *frag      = net_buf_frag_last(buf);
  size_t          added_len = 0;
  const u8_t     *value8    = value;

  do {
    u16_t count = MIN(len, net_buf_tailroom(frag));

    net_buf_add_mem(frag, value8, count);
    len -= count;
    added_len += count;
    value8 += count;

    if (len == 0) {
      return added_len;
    }

    frag = allocate_cb(timeout, user_data);
    if (!frag) {
      return added_len;
    }

    net_buf_frag_add(buf, frag);
  } while (1);

  /* Unreachable */
  return 0;
}

#if defined(CONFIG_NET_BUF_SIMPLE_LOG)
#define NET_BUF_SIMPLE_DBG(fmt, ...)  NET_BUF_DBG(fmt, ##__VA_ARGS__)
#define NET_BUF_SIMPLE_ERR(fmt, ...)  NET_BUF_ERR(fmt, ##__VA_ARGS__)
#define NET_BUF_SIMPLE_WARN(fmt, ...) NET_BUF_WARN(fmt, ##__VA_ARGS__)
#define NET_BUF_SIMPLE_INFO(fmt, ...) NET_BUF_INFO(fmt, ##__VA_ARGS__)
#define NET_BUF_SIMPLE_ASSERT(cond)   NET_BUF_ASSERT(cond)
#else
#define NET_BUF_SIMPLE_DBG(fmt, ...)
#define NET_BUF_SIMPLE_ERR(fmt, ...)
#define NET_BUF_SIMPLE_WARN(fmt, ...)
#define NET_BUF_SIMPLE_INFO(fmt, ...)
#define NET_BUF_SIMPLE_ASSERT(cond)
#endif /* CONFIG_NET_BUF_SIMPLE_LOG */

void net_buf_simple_clone(const struct net_buf_simple *original, struct net_buf_simple *clone) { memcpy(clone, original, sizeof(struct net_buf_simple)); }

void *net_buf_simple_add(struct net_buf_simple *buf, size_t len) {
  u8_t *tail = net_buf_simple_tail(buf);

  NET_BUF_SIMPLE_DBG("buf %p len %zu", buf, len);

  NET_BUF_SIMPLE_ASSERT(net_buf_simple_tailroom(buf) >= len);

  buf->len += len;
  return tail;
}

void *net_buf_simple_add_mem(struct net_buf_simple *buf, const void *mem, size_t len) {
  NET_BUF_SIMPLE_DBG("buf %p len %zu", buf, len);

  return memcpy(net_buf_simple_add(buf, len), mem, len);
}

u8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, u8_t val) {
  u8_t *u8;

  NET_BUF_SIMPLE_DBG("buf %p val 0x%02x", buf, val);

  u8  = net_buf_simple_add(buf, 1);
  *u8 = val;

  return u8;
}

void net_buf_simple_add_le16(struct net_buf_simple *buf, u16_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_le16(val, net_buf_simple_add(buf, sizeof(val)));
}

void net_buf_simple_add_be16(struct net_buf_simple *buf, u16_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_be16(val, net_buf_simple_add(buf, sizeof(val)));
}

void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_le24(val, net_buf_simple_add(buf, 3));
}

void net_buf_simple_add_be24(struct net_buf_simple *buf, uint32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_be24(val, net_buf_simple_add(buf, 3));
}

void net_buf_simple_add_le32(struct net_buf_simple *buf, u32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_le32(val, net_buf_simple_add(buf, sizeof(val)));
}

void net_buf_simple_add_be32(struct net_buf_simple *buf, u32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_be32(val, net_buf_simple_add(buf, sizeof(val)));
}

void *net_buf_simple_push(struct net_buf_simple *buf, size_t len) {
  NET_BUF_SIMPLE_DBG("buf %p len %zu", buf, len);

  NET_BUF_SIMPLE_ASSERT(net_buf_simple_headroom(buf) >= len);

  buf->data -= len;
  buf->len += len;
  return buf->data;
}

void net_buf_simple_push_le16(struct net_buf_simple *buf, u16_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_le16(val, net_buf_simple_push(buf, sizeof(val)));
}

void net_buf_simple_push_be16(struct net_buf_simple *buf, u16_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_be16(val, net_buf_simple_push(buf, sizeof(val)));
}

void net_buf_simple_push_u8(struct net_buf_simple *buf, u8_t val) {
  u8_t *data = net_buf_simple_push(buf, 1);

  *data = val;
}

void net_buf_simple_push_le24(struct net_buf_simple *buf, uint32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_le24(val, net_buf_simple_push(buf, 3));
}

void net_buf_simple_push_be24(struct net_buf_simple *buf, uint32_t val) {
  NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val);

  sys_put_be24(val, net_buf_simple_push(buf, 3));
}

void *net_buf_simple_pull(struct net_buf_simple *buf, size_t len) {
  NET_BUF_SIMPLE_DBG("buf %p len %zu", buf, len);

  NET_BUF_SIMPLE_ASSERT(buf->len >= len);

  buf->len -= len;
  return buf->data += len;
}

void *net_buf_simple_pull_mem(struct net_buf_simple *buf, size_t len) {
  void *data = buf->data;

  NET_BUF_SIMPLE_DBG("buf %p len %zu", buf, len);

  NET_BUF_SIMPLE_ASSERT(buf->len >= len);

  buf->len -= len;
  buf->data += len;

  return data;
}

u8_t net_buf_simple_pull_u8(struct net_buf_simple *buf) {
  u8_t val;

  val = buf->data[0];
  net_buf_simple_pull(buf, 1);

  return val;
}

u16_t net_buf_simple_pull_le16(struct net_buf_simple *buf) {
  u16_t val;

  val = UNALIGNED_GET((u16_t *)buf->data);
  net_buf_simple_pull(buf, sizeof(val));

  return sys_le16_to_cpu(val);
}

u16_t net_buf_simple_pull_be16(struct net_buf_simple *buf) {
  u16_t val;

  val = UNALIGNED_GET((u16_t *)buf->data);
  net_buf_simple_pull(buf, sizeof(val));

  return sys_be16_to_cpu(val);
}

u32_t net_buf_simple_pull_le32(struct net_buf_simple *buf) {
  u32_t val;

  val = UNALIGNED_GET((u32_t *)buf->data);
  net_buf_simple_pull(buf, sizeof(val));

  return sys_le32_to_cpu(val);
}

u32_t net_buf_simple_pull_be32(struct net_buf_simple *buf) {
  u32_t val;

  val = UNALIGNED_GET((u32_t *)buf->data);
  net_buf_simple_pull(buf, sizeof(val));

  return sys_be32_to_cpu(val);
}

size_t net_buf_simple_headroom(struct net_buf_simple *buf) { return buf->data - buf->__buf; }

size_t net_buf_simple_tailroom(struct net_buf_simple *buf) { return buf->size - net_buf_simple_headroom(buf) - buf->len; }


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/dec.c
================================================
/*
 * Copyright (c) 2019 Oticon A/S
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

u8_t u8_to_dec(char *buf, u8_t buflen, u8_t value) {
  u8_t divisor    = 100;
  u8_t num_digits = 0;
  u8_t digit;

  while (buflen > 0 && divisor > 0) {
    digit = value / divisor;
    if (digit != 0 || divisor == 1 || num_digits != 0) {
      *buf = (char)digit + '0';
      buf++;
      buflen--;
      num_digits++;
    }

    value -= digit * divisor;
    divisor /= 10;
  }

  if (buflen) {
    *buf = '\0';
  }

  return num_digits;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/dummy.c
================================================
/**
 * @file dummy.c
 * Static compilation checks.
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

#if defined(CONFIG_BT_HCI_HOST)
/* The Bluetooth subsystem requires the Tx thread to execute at higher priority
 * than the Rx thread as the Tx thread needs to process the acknowledgements
 * before new Rx data is processed. This is a necessity to correctly detect
 * transaction violations in ATT and SMP protocols.
 */
BUILD_ASSERT(CONFIG_BT_HCI_TX_PRIO < CONFIG_BT_RX_PRIO);
#endif

#if defined(CONFIG_BT_CTLR)
/* The Bluetooth Controller's priority receive thread priority shall be higher
 * than the Bluetooth Host's Tx and the Controller's receive thread priority.
 * This is required in order to dispatch Number of Completed Packets event
 * before any new data arrives on a connection to the Host threads.
 */
BUILD_ASSERT(CONFIG_BT_CTLR_RX_PRIO < CONFIG_BT_HCI_TX_PRIO);
#endif /* CONFIG_BT_CTLR */

/* Immediate logging is not supported with the software-based Link Layer
 * since it introduces ISR latency due to outputting log messages with
 * interrupts disabled.
 */
#if !defined(CONFIG_TEST) && !defined(CONFIG_ARCH_POSIX) && (defined(CONFIG_BT_LL_SW_SPLIT) || defined(CONFIG_BT_LL_SW_LEGACY))
BUILD_ASSERT_MSG(!IS_ENABLED(CONFIG_LOG_IMMEDIATE), "Immediate logging not "
                                                    "supported with the software Link Layer");
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/hex.c
================================================
/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
// #include 


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/atomic.h
================================================
/* atomic operations */

/*
 * Copyright (c) 1997-2015, Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __ATOMIC_H__
#define __ATOMIC_H__

#include 

#ifdef __cplusplus
extern "C" {
#endif

typedef int atomic_t;
typedef atomic_t atomic_val_t;

/**
 * @defgroup atomic_apis Atomic Services APIs
 * @ingroup kernel_apis
 * @{
 */

/**
 * @brief Atomic compare-and-set.
 *
 * This routine performs an atomic compare-and-set on @a target. If the current
 * value of @a target equals @a old_value, @a target is set to @a new_value.
 * If the current value of @a target does not equal @a old_value, @a target
 * is left unchanged.
 *
 * @param target Address of atomic variable.
 * @param old_value Original value to compare against.
 * @param new_value New value to store.
 * @return 1 if @a new_value is written, 0 otherwise.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline int atomic_cas(atomic_t *target, atomic_val_t old_value,
                             atomic_val_t new_value)
{
    return __atomic_compare_exchange_n(target, &old_value, new_value,
                                       0, __ATOMIC_SEQ_CST,
                                       __ATOMIC_SEQ_CST);
}
#else
extern int atomic_cas(atomic_t *target, atomic_val_t old_value,
                      atomic_val_t new_value);
#endif

/**
 *
 * @brief Atomic addition.
 *
 * This routine performs an atomic addition on @a target.
 *
 * @param target Address of atomic variable.
 * @param value Value to add.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_add(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_add(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic subtraction.
 *
 * This routine performs an atomic subtraction on @a target.
 *
 * @param target Address of atomic variable.
 * @param value Value to subtract.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_sub(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic increment.
 *
 * This routine performs an atomic increment by 1 on @a target.
 *
 * @param target Address of atomic variable.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_inc(atomic_t *target)
{
    return atomic_add(target, 1);
}
#else
extern atomic_val_t atomic_inc(atomic_t *target);
#endif

/**
 *
 * @brief Atomic decrement.
 *
 * This routine performs an atomic decrement by 1 on @a target.
 *
 * @param target Address of atomic variable.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_dec(atomic_t *target)
{
    return atomic_sub(target, 1);
}
#else
extern atomic_val_t atomic_dec(atomic_t *target);
#endif

/**
 *
 * @brief Atomic get.
 *
 * This routine performs an atomic read on @a target.
 *
 * @param target Address of atomic variable.
 *
 * @return Value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_get(const atomic_t *target)
{
    return __atomic_load_n(target, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_get(const atomic_t *target);
#endif

/**
 *
 * @brief Atomic get-and-set.
 *
 * This routine atomically sets @a target to @a value and returns
 * the previous value of @a target.
 *
 * @param target Address of atomic variable.
 * @param value Value to write to @a target.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_set(atomic_t *target, atomic_val_t value)
{
    /* This builtin, as described by Intel, is not a traditional
	 * test-and-set operation, but rather an atomic exchange operation. It
	 * writes value into *ptr, and returns the previous contents of *ptr.
	 */
    return __atomic_exchange_n(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_set(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic clear.
 *
 * This routine atomically sets @a target to zero and returns its previous
 * value. (Hence, it is equivalent to atomic_set(target, 0).)
 *
 * @param target Address of atomic variable.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_clear(atomic_t *target)
{
    return atomic_set(target, 0);
}
#else
extern atomic_val_t atomic_clear(atomic_t *target);
#endif

/**
 *
 * @brief Atomic bitwise inclusive OR.
 *
 * This routine atomically sets @a target to the bitwise inclusive OR of
 * @a target and @a value.
 *
 * @param target Address of atomic variable.
 * @param value Value to OR.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_or(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_or(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_or(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic bitwise exclusive OR (XOR).
 *
 * This routine atomically sets @a target to the bitwise exclusive OR (XOR) of
 * @a target and @a value.
 *
 * @param target Address of atomic variable.
 * @param value Value to XOR
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_xor(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_xor(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_xor(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic bitwise AND.
 *
 * This routine atomically sets @a target to the bitwise AND of @a target
 * and @a value.
 *
 * @param target Address of atomic variable.
 * @param value Value to AND.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_and(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_and(atomic_t *target, atomic_val_t value);
#endif

/**
 *
 * @brief Atomic bitwise NAND.
 *
 * This routine atomically sets @a target to the bitwise NAND of @a target
 * and @a value. (This operation is equivalent to target = ~(target & value).)
 *
 * @param target Address of atomic variable.
 * @param value Value to NAND.
 *
 * @return Previous value of @a target.
 */
#ifdef CONFIG_ATOMIC_OPERATIONS_BUILTIN
static inline atomic_val_t atomic_nand(atomic_t *target, atomic_val_t value)
{
    return __atomic_fetch_nand(target, value, __ATOMIC_SEQ_CST);
}
#else
extern atomic_val_t atomic_nand(atomic_t *target, atomic_val_t value);
#endif

/**
 * @brief Initialize an atomic variable.
 *
 * This macro can be used to initialize an atomic variable. For example,
 * @code atomic_t my_var = ATOMIC_INIT(75); @endcode
 *
 * @param i Value to assign to atomic variable.
 */
#define ATOMIC_INIT(i) (i)

/**
 * @cond INTERNAL_HIDDEN
 */

#define ATOMIC_BITS            (sizeof(atomic_val_t) * 8)
#define ATOMIC_MASK(bit)       (1 << ((bit) & (ATOMIC_BITS - 1)))
#define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS))

/**
 * INTERNAL_HIDDEN @endcond
 */

/**
 * @brief Define an array of atomic variables.
 *
 * This macro defines an array of atomic variables containing at least
 * @a num_bits bits.
 *
 * @note
 * If used from file scope, the bits of the array are initialized to zero;
 * if used from within a function, the bits are left uninitialized.
 *
 * @param name Name of array of atomic variables.
 * @param num_bits Number of bits needed.
 */
#define ATOMIC_DEFINE(name, num_bits) \
    atomic_t name[1 + ((num_bits)-1) / ATOMIC_BITS]

/**
 * @brief Atomically test a bit.
 *
 * This routine tests whether bit number @a bit of @a target is set or not.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 *
 * @return 1 if the bit was set, 0 if it wasn't.
 */
static inline int atomic_test_bit(const atomic_t *target, int bit)
{
    atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit));

    return (1 & (val >> (bit & (ATOMIC_BITS - 1))));
}

/**
 * @brief Atomically test and clear a bit.
 *
 * Atomically clear bit number @a bit of @a target and return its old value.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 *
 * @return 1 if the bit was set, 0 if it wasn't.
 */
static inline int atomic_test_and_clear_bit(atomic_t *target, int bit)
{
    atomic_val_t mask = ATOMIC_MASK(bit);
    atomic_val_t old;

    old = atomic_and(ATOMIC_ELEM(target, bit), ~mask);

    return (old & mask) != 0;
}

/**
 * @brief Atomically set a bit.
 *
 * Atomically set bit number @a bit of @a target and return its old value.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 *
 * @return 1 if the bit was set, 0 if it wasn't.
 */
static inline int atomic_test_and_set_bit(atomic_t *target, int bit)
{
    atomic_val_t mask = ATOMIC_MASK(bit);
    atomic_val_t old;

    old = atomic_or(ATOMIC_ELEM(target, bit), mask);

    return (old & mask) != 0;
}

/**
 * @brief Atomically clear a bit.
 *
 * Atomically clear bit number @a bit of @a target.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 *
 * @return N/A
 */
static inline void atomic_clear_bit(atomic_t *target, int bit)
{
    atomic_val_t mask = ATOMIC_MASK(bit);

    atomic_and(ATOMIC_ELEM(target, bit), ~mask);
}

/**
 * @brief Atomically set a bit.
 *
 * Atomically set bit number @a bit of @a target.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 *
 * @return N/A
 */
static inline void atomic_set_bit(atomic_t *target, int bit)
{
    atomic_val_t mask = ATOMIC_MASK(bit);

    atomic_or(ATOMIC_ELEM(target, bit), mask);
}

/**
 * @brief Atomically set a bit to a given value.
 *
 * Atomically set bit number @a bit of @a target to value @a val.
 * The target may be a single atomic variable or an array of them.
 *
 * @param target Address of atomic variable or array.
 * @param bit Bit number (starting from 0).
 * @param val true for 1, false for 0.
 *
 * @return N/A
 */
static inline void atomic_set_bit_to(atomic_t *target, int bit, bool val)
{
    atomic_val_t mask = ATOMIC_MASK(bit);

    if (val) {
        (void)atomic_or(ATOMIC_ELEM(target, bit), mask);
    } else {
        (void)atomic_and(ATOMIC_ELEM(target, bit), ~mask);
    }
}

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __ATOMIC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/errno.h
================================================
/* errno.h - errno numbers */

/*
 * Copyright (c) 1984-1999, 2012 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Copyright (c) 1982, 1986 Regents of the University of California.
 * All rights reserved.  The Berkeley software License Agreement
 * specifies the terms and conditions for redistribution.
 *
 *	@(#)errno.h	7.1 (Berkeley) 6/4/86
 */

#ifndef __INCerrnoh
#define __INCerrnoh

#ifdef __cplusplus
extern "C" {
#endif

extern int *__errno(void);
#define errno (*__errno())

/*
 * POSIX Error codes
 */

#define EPERM        1  /* Not owner */
#define ENOENT       2  /* No such file or directory */
#define ESRCH        3  /* No such context */
#define EINTR        4  /* Interrupted system call */
#define EIO          5  /* I/O error */
#define ENXIO        6  /* No such device or address */
#define E2BIG        7  /* Arg list too long */
#define ENOEXEC      8  /* Exec format error */
#define EBADF        9  /* Bad file number */
#define ECHILD       10 /* No children */
#define EAGAIN       11 /* No more contexts */
#define ENOMEM       12 /* Not enough core */
#define EACCES       13 /* Permission denied */
#define EFAULT       14 /* Bad address */
#define ENOTEMPTY    15 /* Directory not empty */
#define EBUSY        16 /* Mount device busy */
#define EEXIST       17 /* File exists */
#define EXDEV        18 /* Cross-device link */
#define ENODEV       19 /* No such device */
#define ENOTDIR      20 /* Not a directory */
#define EISDIR       21 /* Is a directory */
#define EINVAL       22 /* Invalid argument */
#define ENFILE       23 /* File table overflow */
#define EMFILE       24 /* Too many open files */
#define ENOTTY       25 /* Not a typewriter */
#define ENAMETOOLONG 26 /* File name too long */
#define EFBIG        27 /* File too large */
#define ENOSPC       28 /* No space left on device */
#define ESPIPE       29 /* Illegal seek */
#define EROFS        30 /* Read-only file system */
#define EMLINK       31 /* Too many links */
#define EPIPE        32 /* Broken pipe */
#define EDEADLK      33 /* Resource deadlock avoided */
#define ENOLCK       34 /* No locks available */
#define ENOTSUP      35 /* Unsupported value */
#define EMSGSIZE     36 /* Message size */

/* ANSI math software */
#define EDOM   37 /* Argument too large */
#define ERANGE 38 /* Result too large */

/* ipc/network software */

/* argument errors */
#define EDESTADDRREQ    40 /* Destination address required */
#define EPROTOTYPE      41 /* Protocol wrong type for socket */
#define ENOPROTOOPT     42 /* Protocol not available */
#define EPROTONOSUPPORT 43 /* Protocol not supported */
#define ESOCKTNOSUPPORT 44 /* Socket type not supported */
#define EOPNOTSUPP      45 /* Operation not supported on socket */
#define EPFNOSUPPORT    46 /* Protocol family not supported */
#define EAFNOSUPPORT    47 /* Addr family not supported */
#define EADDRINUSE      48 /* Address already in use */
#define EADDRNOTAVAIL   49 /* Can't assign requested address */
#define ENOTSOCK        50 /* Socket operation on non-socket */

/* operational errors */
#define ENETUNREACH  51 /* Network is unreachable */
#define ENETRESET    52 /* Network dropped connection on reset */
#define ECONNABORTED 53 /* Software caused connection abort */
#define ECONNRESET   54 /* Connection reset by peer */
#define ENOBUFS      55 /* No buffer space available */
#define EISCONN      56 /* Socket is already connected */
#define ENOTCONN     57 /* Socket is not connected */
#define ESHUTDOWN    58 /* Can't send after socket shutdown */
#define ETOOMANYREFS 59 /* Too many references: can't splice */
#define ETIMEDOUT    60 /* Connection timed out */
#define ECONNREFUSED 61 /* Connection refused */
#define ENETDOWN     62 /* Network is down */
#define ETXTBSY      63 /* Text file busy */
#define ELOOP        64 /* Too many levels of symbolic links */
#define EHOSTUNREACH 65 /* No route to host */
#define ENOTBLK      66 /* Block device required */
#define EHOSTDOWN    67 /* Host is down */

/* non-blocking and interrupt i/o */
#define EINPROGRESS 68     /* Operation now in progress */
#define EALREADY    69     /* Operation already in progress */
#define EWOULDBLOCK EAGAIN /* Operation would block */

#define ENOSYS 71 /* Function not implemented */

/* aio errors (should be under posix) */
#define ECANCELED 72 /* Operation canceled */

#define ERRMAX 81

/* specific STREAMS errno values */

#define ENOSR   74 /* Insufficient memory */
#define ENOSTR  75 /* STREAMS device required */
#define EPROTO  76 /* Generic STREAMS error */
#define EBADMSG 77 /* Invalid STREAMS message */
#define ENODATA 78 /* Missing expected message data */
#define ETIME   79 /* STREAMS timeout occurred */
#define ENOMSG  80 /* Unexpected message type */

#ifdef __cplusplus
}
#endif

#endif /* __INCerrnoh */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/__assert.h
================================================
/*
 * Copyright (c) 2011-2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Debug aid
 *
 *
 * The __ASSERT() macro can be used inside kernel code.
 *
 * Assertions are enabled by setting the __ASSERT_ON symbol to a non-zero value.
 * There are two ways to do this:
 *   a) Use the ASSERT and ASSERT_LEVEL kconfig options
 *   b) Add "CFLAGS += -D__ASSERT_ON=" at the end of a project's Makefile
 * The Makefile method takes precedence over the kconfig option if both are
 * used.
 *
 * Specifying an assertion level of 1 causes the compiler to issue warnings that
 * the kernel contains debug-type __ASSERT() statements; this reminder is issued
 * since assertion code is not normally present in a final product. Specifying
 * assertion level 2 suppresses these warnings.
 *
 * The __ASSERT_EVAL() macro can also be used inside kernel code.
 *
 * It makes use of the __ASSERT() macro, but has some extra flexibility.  It
 * allows the developer to specify different actions depending whether the
 * __ASSERT() macro is enabled or not.  This can be particularly useful to
 * prevent the compiler from generating comments (errors, warnings or remarks)
 * about variables that are only used with __ASSERT() being assigned a value,
 * but otherwise unused when the __ASSERT() macro is disabled.
 *
 * Consider the following example:
 *
 * int  x;
 *
 * x = foo ();
 * __ASSERT (x != 0, "foo() returned zero!");
 *
 * If __ASSERT() is disabled, then 'x' is assigned a value, but never used.
 * This type of situation can be resolved using the __ASSERT_EVAL() macro.
 *
 * __ASSERT_EVAL ((void) foo(),
 *		  int x = foo(),
 *                x != 0,
 *                "foo() returned zero!");
 *
 * The first parameter tells __ASSERT_EVAL() what to do if __ASSERT() is
 * disabled.  The second parameter tells __ASSERT_EVAL() what to do if
 * __ASSERT() is enabled.  The third and fourth parameters are the parameters
 * it passes to __ASSERT().
 *
 * The __ASSERT_NO_MSG() macro can be used to perform an assertion that reports
 * the failed test and its location, but lacks additional debugging information
 * provided to assist the user in diagnosing the problem; its use is
 * discouraged.
 */

#ifndef ___ASSERT__H_
#define ___ASSERT__H_

#ifdef CONFIG_ASSERT
#ifndef __ASSERT_ON
#define __ASSERT_ON CONFIG_ASSERT_LEVEL
#endif
#endif

#ifdef __ASSERT_ON
#if (__ASSERT_ON < 0) || (__ASSERT_ON > 2)
#error "Invalid __ASSERT() level: must be between 0 and 2"
#endif

#if __ASSERT_ON
#include 
#define __ASSERT(test, fmt, ...)                       \
    do {                                               \
        if (!(test)) {                                 \
            printk("ASSERTION FAIL [%s] @ %s:%d:\n\t", \
                   _STRINGIFY(test),                   \
                   __FILE__,                           \
                   __LINE__);                          \
            printk(fmt, ##__VA_ARGS__);                \
            for (;;)                                   \
                ; /* spin thread */                    \
        }                                              \
    } while ((0))

#define __ASSERT_EVAL(expr1, expr2, test, fmt, ...) \
    do {                                            \
        expr2;                                      \
        __ASSERT(test, fmt, ##__VA_ARGS__);         \
    } while (0)

#if (__ASSERT_ON == 1)
#warning "__ASSERT() statements are ENABLED"
#endif
#else
#define __ASSERT(test, fmt, ...) \
    do { /* nothing */           \
    } while ((0))
#define __ASSERT_EVAL(expr1, expr2, test, fmt, ...) expr1
#endif
#else
#define __ASSERT(test, fmt, ...) \
    do { /* nothing */           \
    } while ((0))
#define __ASSERT_EVAL(expr1, expr2, test, fmt, ...) expr1
#endif

#define __ASSERT_NO_MSG(test) __ASSERT(test, "")

#endif /* ___ASSERT__H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/byteorder.h
================================================
/** @file
 *  @brief Byte order helpers.
 */

/*
 * Copyright (c) 2015-2016, Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __BYTEORDER_H__
#define __BYTEORDER_H__

#include 
#include 
#include 

#ifndef __BYTE_ORDER__
#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
#endif

/* Internal helpers only used by the sys_* APIs further below */
#define __bswap_16(x) ((u16_t)((((x) >> 8) & 0xff) | (((x)&0xff) << 8)))
#define __bswap_32(x) ((u32_t)((((x) >> 24) & 0xff) |  \
                               (((x) >> 8) & 0xff00) | \
                               (((x)&0xff00) << 8) |   \
                               (((x)&0xff) << 24)))
#define __bswap_64(x) ((u64_t)((((x) >> 56) & 0xff) |      \
                               (((x) >> 40) & 0xff00) |    \
                               (((x) >> 24) & 0xff0000) |  \
                               (((x) >> 8) & 0xff000000) | \
                               (((x)&0xff000000) << 8) |   \
                               (((x)&0xff0000) << 24) |    \
                               (((x)&0xff00) << 40) |      \
                               (((x)&0xff) << 56)))

/** @def sys_le16_to_cpu
 *  @brief Convert 16-bit integer from little-endian to host endianness.
 *
 *  @param val 16-bit integer in little-endian format.
 *
 *  @return 16-bit integer in host endianness.
 */

/** @def sys_cpu_to_le16
 *  @brief Convert 16-bit integer from host endianness to little-endian.
 *
 *  @param val 16-bit integer in host endianness.
 *
 *  @return 16-bit integer in little-endian format.
 */

/** @def sys_be16_to_cpu
 *  @brief Convert 16-bit integer from big-endian to host endianness.
 *
 *  @param val 16-bit integer in big-endian format.
 *
 *  @return 16-bit integer in host endianness.
 */

/** @def sys_cpu_to_be16
 *  @brief Convert 16-bit integer from host endianness to big-endian.
 *
 *  @param val 16-bit integer in host endianness.
 *
 *  @return 16-bit integer in big-endian format.
 */

/** @def sys_le32_to_cpu
 *  @brief Convert 32-bit integer from little-endian to host endianness.
 *
 *  @param val 32-bit integer in little-endian format.
 *
 *  @return 32-bit integer in host endianness.
 */

/** @def sys_cpu_to_le32
 *  @brief Convert 32-bit integer from host endianness to little-endian.
 *
 *  @param val 32-bit integer in host endianness.
 *
 *  @return 32-bit integer in little-endian format.
 */

/** @def sys_be32_to_cpu
 *  @brief Convert 32-bit integer from big-endian to host endianness.
 *
 *  @param val 32-bit integer in big-endian format.
 *
 *  @return 32-bit integer in host endianness.
 */

/** @def sys_cpu_to_be32
 *  @brief Convert 32-bit integer from host endianness to big-endian.
 *
 *  @param val 32-bit integer in host endianness.
 *
 *  @return 32-bit integer in big-endian format.
 */

#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define sys_le16_to_cpu(val) (val)
#define sys_cpu_to_le16(val) (val)
#define sys_be16_to_cpu(val) __bswap_16(val)
#define sys_cpu_to_be16(val) __bswap_16(val)
#define sys_le32_to_cpu(val) (val)
#define sys_cpu_to_le32(val) (val)
#define sys_le64_to_cpu(val) (val)
#define sys_cpu_to_le64(val) (val)
#define sys_be32_to_cpu(val) __bswap_32(val)
#define sys_cpu_to_be32(val) __bswap_32(val)
#define sys_be64_to_cpu(val) __bswap_64(val)
#define sys_cpu_to_be64(val) __bswap_64(val)
/********************************************************************************
** Macros to get and put bytes to a stream (Little Endian format).
*/
#define UINT32_TO_STREAM(p, u32)      \
    {                                 \
        *(p)++ = (u8_t)(u32);         \
        *(p)++ = (u8_t)((u32) >> 8);  \
        *(p)++ = (u8_t)((u32) >> 16); \
        *(p)++ = (u8_t)((u32) >> 24); \
    }
#define UINT24_TO_STREAM(p, u24)      \
    {                                 \
        *(p)++ = (u8_t)(u24);         \
        *(p)++ = (u8_t)((u24) >> 8);  \
        *(p)++ = (u8_t)((u24) >> 16); \
    }
#define UINT16_TO_STREAM(p, u16)     \
    {                                \
        *(p)++ = (u8_t)(u16);        \
        *(p)++ = (u8_t)((u16) >> 8); \
    }
#define UINT8_TO_STREAM(p, u8) \
    {                          \
        *(p)++ = (u8_t)(u8);   \
    }

#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
#define sys_le16_to_cpu(val) __bswap_16(val)
#define sys_cpu_to_le16(val) __bswap_16(val)
#define sys_be16_to_cpu(val) (val)
#define sys_cpu_to_be16(val) (val)
#define sys_le32_to_cpu(val) __bswap_32(val)
#define sys_cpu_to_le32(val) __bswap_32(val)
#define sys_le64_to_cpu(val) __bswap_64(val)
#define sys_cpu_to_le64(val) __bswap_64(val)
#define sys_be32_to_cpu(val) (val)
#define sys_cpu_to_be32(val) (val)
#define sys_be64_to_cpu(val) (val)
#define sys_cpu_to_be64(val) (val)
/********************************************************************************
** Macros to get and put bytes to a stream (Big Endian format)
*/
#define UINT32_TO_STREAM(p, u32)      \
    {                                 \
        *(p)++ = (u8_t)((u32) >> 24); \
        *(p)++ = (u8_t)((u32) >> 16); \
        *(p)++ = (u8_t)((u32) >> 8);  \
        *(p)++ = (u8_t)(u32);         \
    }
#define UINT24_TO_STREAM(p, u24)      \
    {                                 \
        *(p)++ = (u8_t)((u24) >> 16); \
        *(p)++ = (u8_t)((u24) >> 8);  \
        *(p)++ = (u8_t)(u24);         \
    }
#define UINT16_TO_STREAM(p, u16)     \
    {                                \
        *(p)++ = (u8_t)((u16) >> 8); \
        *(p)++ = (u8_t)(u16);        \
    }
#define UINT8_TO_STREAM(p, u8) \
    {                          \
        *(p)++ = (u8_t)(u8);   \
    }

#else
#error "Unknown byte order"
#endif

/**
 *  @brief Put a 16-bit integer as big-endian to arbitrary location.
 *
 *  Put a 16-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in big-endian format.
 *
 *  @param val 16-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_be16(u16_t val, u8_t dst[2])
{
    dst[0] = val >> 8;
    dst[1] = val;
}

/**
 *  @brief Put a 24-bit integer as big-endian to arbitrary location.
 *
 *  Put a 24-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in big-endian format.
 *
 *  @param val 24-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_be24(uint32_t val, uint8_t dst[3])
{
    dst[0] = val >> 16;
    sys_put_be16(val, &dst[1]);
}

/**
 *  @brief Put a 32-bit integer as big-endian to arbitrary location.
 *
 *  Put a 32-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in big-endian format.
 *
 *  @param val 32-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_be32(u32_t val, u8_t dst[4])
{
    sys_put_be16(val >> 16, dst);
    sys_put_be16(val, &dst[2]);
}

/**
 *  @brief Put a 16-bit integer as little-endian to arbitrary location.
 *
 *  Put a 16-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in little-endian format.
 *
 *  @param val 16-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_le16(u16_t val, u8_t dst[2])
{
    dst[0] = val;
    dst[1] = val >> 8;
}

/**
 *  @brief Put a 24-bit integer as little-endian to arbitrary location.
 *
 *  Put a 24-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in littel-endian format.
 *
 *  @param val 24-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_le24(uint32_t val, uint8_t dst[3])
{
    sys_put_le16(val, dst);
    dst[2] = val >> 16;
}

/**
 *  @brief Put a 32-bit integer as little-endian to arbitrary location.
 *
 *  Put a 32-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in little-endian format.
 *
 *  @param val 32-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_le32(u32_t val, u8_t dst[4])
{
    sys_put_le16(val, dst);
    sys_put_le16(val >> 16, &dst[2]);
}

/**
 *  @brief Put a 64-bit integer as little-endian to arbitrary location.
 *
 *  Put a 64-bit integer, originally in host endianness, to a
 *  potentially unaligned memory location in little-endian format.
 *
 *  @param val 64-bit integer in host endianness.
 *  @param dst Destination memory address to store the result.
 */
static inline void sys_put_le64(u64_t val, u8_t dst[8])
{
    sys_put_le32(val, dst);
    sys_put_le32(val >> 32, &dst[4]);
}

/**
 *  @brief Get a 16-bit integer stored in big-endian format.
 *
 *  Get a 16-bit integer, stored in big-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the big-endian 16-bit integer to get.
 *
 *  @return 16-bit integer in host endianness.
 */
static inline u16_t sys_get_be16(const u8_t src[2])
{
    return ((u16_t)src[0] << 8) | src[1];
}

/**
 *  @brief Get a 24-bit integer stored in big-endian format.
 *
 *  Get a 24-bit integer, stored in big-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the big-endian 24-bit integer to get.
 *
 *  @return 24-bit integer in host endianness.
 */
static inline uint32_t sys_get_be24(const uint8_t src[3])
{
    return ((uint32_t)src[0] << 16) | sys_get_be16(&src[1]);
}

/**
 *  @brief Get a 32-bit integer stored in big-endian format.
 *
 *  Get a 32-bit integer, stored in big-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the big-endian 32-bit integer to get.
 *
 *  @return 32-bit integer in host endianness.
 */
static inline u32_t sys_get_be32(const u8_t src[4])
{
    return ((u32_t)sys_get_be16(&src[0]) << 16) | sys_get_be16(&src[2]);
}

/**
 *  @brief Get a 16-bit integer stored in little-endian format.
 *
 *  Get a 16-bit integer, stored in little-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the little-endian 16-bit integer to get.
 *
 *  @return 16-bit integer in host endianness.
 */
static inline u16_t sys_get_le16(const u8_t src[2])
{
    return ((u16_t)src[1] << 8) | src[0];
}

/**
 *  @brief Get a 24-bit integer stored in big-endian format.
 *
 *  Get a 24-bit integer, stored in big-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the big-endian 24-bit integer to get.
 *
 *  @return 24-bit integer in host endianness.
 */
static inline uint32_t sys_get_le24(const uint8_t src[3])
{
    return ((uint32_t)src[2] << 16) | sys_get_le16(&src[0]);
}

/**
 *  @brief Get a 32-bit integer stored in little-endian format.
 *
 *  Get a 32-bit integer, stored in little-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the little-endian 32-bit integer to get.
 *
 *  @return 32-bit integer in host endianness.
 */
static inline u32_t sys_get_le32(const u8_t src[4])
{
    return ((u32_t)sys_get_le16(&src[2]) << 16) | sys_get_le16(&src[0]);
}

/**
 *  @brief Get a 64-bit integer stored in little-endian format.
 *
 *  Get a 64-bit integer, stored in little-endian format in a potentially
 *  unaligned memory location, and convert it to the host endianness.
 *
 *  @param src Location of the little-endian 64-bit integer to get.
 *
 *  @return 64-bit integer in host endianness.
 */
static inline u64_t sys_get_le64(const u8_t src[8])
{
    return ((u64_t)sys_get_le32(&src[4]) << 32) | sys_get_le32(&src[0]);
}

/**
 * @brief Swap one buffer content into another
 *
 * Copy the content of src buffer into dst buffer in reversed order,
 * i.e.: src[n] will be put in dst[end-n]
 * Where n is an index and 'end' the last index in both arrays.
 * The 2 memory pointers must be pointing to different areas, and have
 * a minimum size of given length.
 *
 * @param dst A valid pointer on a memory area where to copy the data in
 * @param src A valid pointer on a memory area where to copy the data from
 * @param length Size of both dst and src memory areas
 */
static inline void sys_memcpy_swap(void *dst, const void *src, size_t length)
{
    __ASSERT(((src < dst && (src + length) <= dst) ||
              (src > dst && (dst + length) <= src)),
             "Source and destination buffers must not overlap");

    src += length - 1;

    for (; length > 0; length--) {
        *((u8_t *)dst++) = *((u8_t *)src--);
    }
}

/**
 * @brief Swap buffer content
 *
 * In-place memory swap, where final content will be reversed.
 * I.e.: buf[n] will be put in buf[end-n]
 * Where n is an index and 'end' the last index of buf.
 *
 * @param buf A valid pointer on a memory area to swap
 * @param length Size of buf memory area
 */
static inline void sys_mem_swap(void *buf, size_t length)
{
    size_t i;

    for (i = 0; i < (length / 2); i++) {
        u8_t tmp = ((u8_t *)buf)[i];

        ((u8_t *)buf)[i] = ((u8_t *)buf)[length - 1 - i];
        ((u8_t *)buf)[length - 1 - i] = tmp;
    }
}

#endif /* __BYTEORDER_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/dlist.h
================================================
/*
 * Copyright (c) 2013-2015 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Doubly-linked list implementation
 *
 * Doubly-linked list implementation using inline macros/functions.
 * This API is not thread safe, and thus if a list is used across threads,
 * calls to functions must be protected with synchronization primitives.
 *
 * The lists are expected to be initialized such that both the head and tail
 * pointers point to the list itself.  Initializing the lists in such a fashion
 * simplifies the adding and removing of nodes to/from the list.
 */

#ifndef _misc_dlist__h_
#define _misc_dlist__h_

#include 

#ifdef __cplusplus
extern "C" {
#endif

struct _dnode {
    union {
        struct _dnode *head; /* ptr to head of list (sys_dlist_t) */
        struct _dnode *next; /* ptr to next node    (sys_dnode_t) */
    };
    union {
        struct _dnode *tail; /* ptr to tail of list (sys_dlist_t) */
        struct _dnode *prev; /* ptr to previous node (sys_dnode_t) */
    };
};

typedef struct _dnode sys_dlist_t;
typedef struct _dnode sys_dnode_t;

/**
 * @brief Provide the primitive to iterate on a list
 * Note: the loop is unsafe and thus __dn should not be removed
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_DLIST_FOR_EACH_NODE(l, n) {
 *         
 *     }
 *
 * This and other SYS_DLIST_*() macros are not thread safe.
 *
 * @param __dl A pointer on a sys_dlist_t to iterate on
 * @param __dn A sys_dnode_t pointer to peek each node of the list
 */
#define SYS_DLIST_FOR_EACH_NODE(__dl, __dn)      \
    for (__dn = sys_dlist_peek_head(__dl); __dn; \
         __dn = sys_dlist_peek_next(__dl, __dn))

/**
 * @brief Provide the primitive to iterate on a list, from a node in the list
 * Note: the loop is unsafe and thus __dn should not be removed
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_DLIST_ITERATE_FROM_NODE(l, n) {
 *         
 *     }
 *
 * Like SYS_DLIST_FOR_EACH_NODE(), but __dn already contains a node in the list
 * where to start searching for the next entry from. If NULL, it starts from
 * the head.
 *
 * This and other SYS_DLIST_*() macros are not thread safe.
 *
 * @param __dl A pointer on a sys_dlist_t to iterate on
 * @param __dn A sys_dnode_t pointer to peek each node of the list;
 *             it contains the starting node, or NULL to start from the head
 */
#define SYS_DLIST_ITERATE_FROM_NODE(__dl, __dn)                                              \
    for (__dn = __dn ? sys_dlist_peek_next_no_check(__dl, __dn) : sys_dlist_peek_head(__dl); \
         __dn;                                                                               \
         __dn = sys_dlist_peek_next(__dl, __dn))

/**
 * @brief Provide the primitive to safely iterate on a list
 * Note: __dn can be removed, it will not break the loop.
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_DLIST_FOR_EACH_NODE_SAFE(l, n, s) {
 *         
 *     }
 *
 * This and other SYS_DLIST_*() macros are not thread safe.
 *
 * @param __dl A pointer on a sys_dlist_t to iterate on
 * @param __dn A sys_dnode_t pointer to peek each node of the list
 * @param __dns A sys_dnode_t pointer for the loop to run safely
 */
#define SYS_DLIST_FOR_EACH_NODE_SAFE(__dl, __dn, __dns) \
    for (__dn = sys_dlist_peek_head(__dl),              \
        __dns = sys_dlist_peek_next(__dl, __dn);        \
         __dn; __dn = __dns,                            \
        __dns = sys_dlist_peek_next(__dl, __dn))

/*
 * @brief Provide the primitive to resolve the container of a list node
 * Note: it is safe to use with NULL pointer nodes
 *
 * @param __dn A pointer on a sys_dnode_t to get its container
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_dnode_t within the container struct
 */
#define SYS_DLIST_CONTAINER(__dn, __cn, __n) \
    (__dn ? CONTAINER_OF(__dn, __typeof__(*__cn), __n) : NULL)
/*
 * @brief Provide the primitive to peek container of the list head
 *
 * @param __dl A pointer on a sys_dlist_t to peek
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_dnode_t within the container struct
 */
#define SYS_DLIST_PEEK_HEAD_CONTAINER(__dl, __cn, __n) \
    SYS_DLIST_CONTAINER(sys_dlist_peek_head(__dl), __cn, __n)

/*
 * @brief Provide the primitive to peek the next container
 *
 * @param __dl A pointer on a sys_dlist_t to peek
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_dnode_t within the container struct
 */
#define SYS_DLIST_PEEK_NEXT_CONTAINER(__dl, __cn, __n)                     \
    ((__cn) ? SYS_DLIST_CONTAINER(sys_dlist_peek_next(__dl, &(__cn->__n)), \
                                  __cn, __n) :                             \
              NULL)

/**
 * @brief Provide the primitive to iterate on a list under a container
 * Note: the loop is unsafe and thus __cn should not be detached
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_DLIST_FOR_EACH_CONTAINER(l, c, n) {
 *         
 *     }
 *
 * @param __dl A pointer on a sys_dlist_t to iterate on
 * @param __cn A pointer to peek each entry of the list
 * @param __n The field name of sys_dnode_t within the container struct
 */
#define SYS_DLIST_FOR_EACH_CONTAINER(__dl, __cn, __n)                 \
    for (__cn = SYS_DLIST_PEEK_HEAD_CONTAINER(__dl, __cn, __n); __cn; \
         __cn = SYS_DLIST_PEEK_NEXT_CONTAINER(__dl, __cn, __n))

/**
 * @brief Provide the primitive to safely iterate on a list under a container
 * Note: __cn can be detached, it will not break the loop.
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_DLIST_FOR_EACH_CONTAINER_SAFE(l, c, cn, n) {
 *         
 *     }
 *
 * @param __dl A pointer on a sys_dlist_t to iterate on
 * @param __cn A pointer to peek each entry of the list
 * @param __cns A pointer for the loop to run safely
 * @param __n The field name of sys_dnode_t within the container struct
 */
#define SYS_DLIST_FOR_EACH_CONTAINER_SAFE(__dl, __cn, __cns, __n) \
    for (__cn = SYS_DLIST_PEEK_HEAD_CONTAINER(__dl, __cn, __n),   \
        __cns = SYS_DLIST_PEEK_NEXT_CONTAINER(__dl, __cn, __n);   \
         __cn;                                                    \
         __cn = __cns,                                            \
        __cns = SYS_DLIST_PEEK_NEXT_CONTAINER(__dl, __cn, __n))

/**
 * @brief initialize list
 *
 * @param list the doubly-linked list
 *
 * @return N/A
 */

static inline void sys_dlist_init(sys_dlist_t *list)
{
    list->head = (sys_dnode_t *)list;
    list->tail = (sys_dnode_t *)list;
}

#define SYS_DLIST_STATIC_INIT(ptr_to_list) \
    {                                      \
        { (ptr_to_list) },                 \
        {                                  \
            (ptr_to_list)                  \
        }                                  \
    }

/**
 * @brief check if a node is the list's head
 *
 * @param list the doubly-linked list to operate on
 * @param node the node to check
 *
 * @return 1 if node is the head, 0 otherwise
 */

static inline int sys_dlist_is_head(sys_dlist_t *list, sys_dnode_t *node)
{
    return list->head == node;
}

/**
 * @brief check if a node is the list's tail
 *
 * @param list the doubly-linked list to operate on
 * @param node the node to check
 *
 * @return 1 if node is the tail, 0 otherwise
 */

static inline int sys_dlist_is_tail(sys_dlist_t *list, sys_dnode_t *node)
{
    return list->tail == node;
}

/**
 * @brief check if the list is empty
 *
 * @param list the doubly-linked list to operate on
 *
 * @return 1 if empty, 0 otherwise
 */

static inline int sys_dlist_is_empty(sys_dlist_t *list)
{
    return list->head == list;
}

/**
 * @brief check if more than one node present
 *
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 *
 * @return 1 if multiple nodes, 0 otherwise
 */

static inline int sys_dlist_has_multiple_nodes(sys_dlist_t *list)
{
    return list->head != list->tail;
}

/**
 * @brief get a reference to the head item in the list
 *
 * @param list the doubly-linked list to operate on
 *
 * @return a pointer to the head element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_head(sys_dlist_t *list)
{
    return sys_dlist_is_empty(list) ? NULL : list->head;
}

/**
 * @brief get a reference to the head item in the list
 *
 * The list must be known to be non-empty.
 *
 * @param list the doubly-linked list to operate on
 *
 * @return a pointer to the head element
 */

static inline sys_dnode_t *sys_dlist_peek_head_not_empty(sys_dlist_t *list)
{
    return list->head;
}

/**
 * @brief get a reference to the next item in the list, node is not NULL
 *
 * Faster than sys_dlist_peek_next() if node is known not to be NULL.
 *
 * @param list the doubly-linked list to operate on
 * @param node the node from which to get the next element in the list
 *
 * @return a pointer to the next element from a node, NULL if node is the tail
 */

static inline sys_dnode_t *sys_dlist_peek_next_no_check(sys_dlist_t *list,
                                                        sys_dnode_t *node)
{
    return (node == list->tail) ? NULL : node->next;
}

/**
 * @brief get a reference to the next item in the list
 *
 * @param list the doubly-linked list to operate on
 * @param node the node from which to get the next element in the list
 *
 * @return a pointer to the next element from a node, NULL if node is the tail
 * or NULL (when node comes from reading the head of an empty list).
 */

static inline sys_dnode_t *sys_dlist_peek_next(sys_dlist_t *list,
                                               sys_dnode_t *node)
{
    return node ? sys_dlist_peek_next_no_check(list, node) : NULL;
}

/**
 * @brief get a reference to the tail item in the list
 *
 * @param list the doubly-linked list to operate on
 *
 * @return a pointer to the tail element, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_peek_tail(sys_dlist_t *list)
{
    return sys_dlist_is_empty(list) ? NULL : list->tail;
}

/**
 * @brief add node to tail of list
 *
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 * @param node the element to append
 *
 * @return N/A
 */

static inline void sys_dlist_append(sys_dlist_t *list, sys_dnode_t *node)
{
    node->next = list;
    node->prev = list->tail;

    list->tail->next = node;
    list->tail = node;
}

/**
 * @brief add node to head of list
 *
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 * @param node the element to append
 *
 * @return N/A
 */

static inline void sys_dlist_prepend(sys_dlist_t *list, sys_dnode_t *node)
{
    node->next = list->head;
    node->prev = list;

    list->head->prev = node;
    list->head = node;
}

/**
 * @brief insert node after a node
 *
 * Insert a node after a specified node in a list.
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 * @param insert_point the insert point in the list: if NULL, insert at head
 * @param node the element to append
 *
 * @return N/A
 */

static inline void sys_dlist_insert_after(sys_dlist_t *list,
                                          sys_dnode_t *insert_point, sys_dnode_t *node)
{
    if (!insert_point) {
        sys_dlist_prepend(list, node);
    } else {
        node->next = insert_point->next;
        node->prev = insert_point;
        insert_point->next->prev = node;
        insert_point->next = node;
    }
}

/**
 * @brief insert node before a node
 *
 * Insert a node before a specified node in a list.
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 * @param insert_point the insert point in the list: if NULL, insert at tail
 * @param node the element to insert
 *
 * @return N/A
 */

static inline void sys_dlist_insert_before(sys_dlist_t *list,
                                           sys_dnode_t *insert_point, sys_dnode_t *node)
{
    if (!insert_point) {
        sys_dlist_append(list, node);
    } else {
        node->prev = insert_point->prev;
        node->next = insert_point;
        insert_point->prev->next = node;
        insert_point->prev = node;
    }
}

/**
 * @brief insert node at position
 *
 * Insert a node in a location depending on a external condition. The cond()
 * function checks if the node is to be inserted _before_ the current node
 * against which it is checked.
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 * @param node the element to insert
 * @param cond a function that determines if the current node is the correct
 *             insert point
 * @param data parameter to cond()
 *
 * @return N/A
 */

static inline void sys_dlist_insert_at(sys_dlist_t *list, sys_dnode_t *node,
                                       int (*cond)(sys_dnode_t *, void *), void *data)
{
    if (sys_dlist_is_empty(list)) {
        sys_dlist_append(list, node);
    } else {
        sys_dnode_t *pos = sys_dlist_peek_head(list);

        while (pos && !cond(pos, data)) {
            pos = sys_dlist_peek_next(list, pos);
        }
        sys_dlist_insert_before(list, pos, node);
    }
}

/**
 * @brief remove a specific node from a list
 *
 * The list is implicit from the node. The node must be part of a list.
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param node the node to remove
 *
 * @return N/A
 */

static inline void sys_dlist_remove(sys_dnode_t *node)
{
    node->prev->next = node->next;
    node->next->prev = node->prev;
}

/**
 * @brief get the first node in a list
 *
 * This and other sys_dlist_*() functions are not thread safe.
 *
 * @param list the doubly-linked list to operate on
 *
 * @return the first node in the list, NULL if list is empty
 */

static inline sys_dnode_t *sys_dlist_get(sys_dlist_t *list)
{
    sys_dnode_t *node;

    if (sys_dlist_is_empty(list)) {
        return NULL;
    }

    node = list->head;
    sys_dlist_remove(node);
    return node;
}

#ifdef __cplusplus
}
#endif

#endif /* _misc_dlist__h_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/printk.h
================================================
/* printk.h - low-level debug output */

/*
 * Copyright (c) 2010-2012, 2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef _PRINTK_H_
#define _PRINTK_H_

#include 
#include 
#include 

#include 

#ifdef __cplusplus
extern "C" {
#endif

#define snprintk snprintf
#define printk   printf

#ifdef __cplusplus
}
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/slist.h
================================================
/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 *
 * @brief Single-linked list implementation
 *
 * Single-linked list implementation using inline macros/functions.
 * This API is not thread safe, and thus if a list is used across threads,
 * calls to functions must be protected with synchronization primitives.
 */

#ifndef __SLIST_H__
#define __SLIST_H__

#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif

struct _snode {
    struct _snode *next;
};

typedef struct _snode sys_snode_t;

struct _slist {
    sys_snode_t *head;
    sys_snode_t *tail;
};

typedef struct _slist sys_slist_t;

/**
 * @brief Provide the primitive to iterate on a list
 * Note: the loop is unsafe and thus __sn should not be removed
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_SLIST_FOR_EACH_NODE(l, n) {
 *         
 *     }
 *
 * This and other SYS_SLIST_*() macros are not thread safe.
 *
 * @param __sl A pointer on a sys_slist_t to iterate on
 * @param __sn A sys_snode_t pointer to peek each node of the list
 */
#define SYS_SLIST_FOR_EACH_NODE(__sl, __sn)      \
    for (__sn = sys_slist_peek_head(__sl); __sn; \
         __sn = sys_slist_peek_next(__sn))

/**
 * @brief Provide the primitive to iterate on a list, from a node in the list
 * Note: the loop is unsafe and thus __sn should not be removed
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_SLIST_ITERATE_FROM_NODE(l, n) {
 *         
 *     }
 *
 * Like SYS_SLIST_FOR_EACH_NODE(), but __dn already contains a node in the list
 * where to start searching for the next entry from. If NULL, it starts from
 * the head.
 *
 * This and other SYS_SLIST_*() macros are not thread safe.
 *
 * @param __sl A pointer on a sys_slist_t to iterate on
 * @param __sn A sys_snode_t pointer to peek each node of the list
 *             it contains the starting node, or NULL to start from the head
 */
#define SYS_SLIST_ITERATE_FROM_NODE(__sl, __sn)                                        \
    for (__sn = __sn ? sys_slist_peek_next_no_check(__sn) : sys_slist_peek_head(__sl); \
         __sn;                                                                         \
         __sn = sys_slist_peek_next(__sn))

/**
 * @brief Provide the primitive to safely iterate on a list
 * Note: __sn can be removed, it will not break the loop.
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_SLIST_FOR_EACH_NODE_SAFE(l, n, s) {
 *         
 *     }
 *
 * This and other SYS_SLIST_*() macros are not thread safe.
 *
 * @param __sl A pointer on a sys_slist_t to iterate on
 * @param __sn A sys_snode_t pointer to peek each node of the list
 * @param __sns A sys_snode_t pointer for the loop to run safely
 */
#define SYS_SLIST_FOR_EACH_NODE_SAFE(__sl, __sn, __sns) \
    for (__sn = sys_slist_peek_head(__sl),              \
        __sns = sys_slist_peek_next(__sn);              \
         __sn; __sn = __sns,                            \
        __sns = sys_slist_peek_next(__sn))

/*
 * @brief Provide the primitive to resolve the container of a list node
 * Note: it is safe to use with NULL pointer nodes
 *
 * @param __ln A pointer on a sys_node_t to get its container
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_node_t within the container struct
 */
#define SYS_SLIST_CONTAINER(__ln, __cn, __n) \
    ((__ln) ? CONTAINER_OF((__ln), __typeof__(*(__cn)), __n) : NULL)
/*
 * @brief Provide the primitive to peek container of the list head
 *
 * @param __sl A pointer on a sys_slist_t to peek
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_node_t within the container struct
 */
#define SYS_SLIST_PEEK_HEAD_CONTAINER(__sl, __cn, __n) \
    SYS_SLIST_CONTAINER(sys_slist_peek_head(__sl), __cn, __n)

/*
 * @brief Provide the primitive to peek container of the list tail
 *
 * @param __sl A pointer on a sys_slist_t to peek
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_node_t within the container struct
 */
#define SYS_SLIST_PEEK_TAIL_CONTAINER(__sl, __cn, __n) \
    SYS_SLIST_CONTAINER(sys_slist_peek_tail(__sl), __cn, __n)

/*
 * @brief Provide the primitive to peek the next container
 *
 * @param __cn Container struct type pointer
 * @param __n The field name of sys_node_t within the container struct
 */

#define SYS_SLIST_PEEK_NEXT_CONTAINER(__cn, __n)                       \
    ((__cn) ? SYS_SLIST_CONTAINER(sys_slist_peek_next(&((__cn)->__n)), \
                                  __cn, __n) :                         \
              NULL)

/**
 * @brief Provide the primitive to iterate on a list under a container
 * Note: the loop is unsafe and thus __cn should not be detached
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_SLIST_FOR_EACH_CONTAINER(l, c, n) {
 *         
 *     }
 *
 * @param __sl A pointer on a sys_slist_t to iterate on
 * @param __cn A pointer to peek each entry of the list
 * @param __n The field name of sys_node_t within the container struct
 */
#define SYS_SLIST_FOR_EACH_CONTAINER(__sl, __cn, __n)                 \
    for (__cn = SYS_SLIST_PEEK_HEAD_CONTAINER(__sl, __cn, __n); __cn; \
         __cn = SYS_SLIST_PEEK_NEXT_CONTAINER(__cn, __n))

/**
 * @brief Provide the primitive to safely iterate on a list under a container
 * Note: __cn can be detached, it will not break the loop.
 *
 * User _MUST_ add the loop statement curly braces enclosing its own code:
 *
 *     SYS_SLIST_FOR_EACH_NODE_SAFE(l, c, cn, n) {
 *         
 *     }
 *
 * @param __sl A pointer on a sys_slist_t to iterate on
 * @param __cn A pointer to peek each entry of the list
 * @param __cns A pointer for the loop to run safely
 * @param __n The field name of sys_node_t within the container struct
 */
#define SYS_SLIST_FOR_EACH_CONTAINER_SAFE(__sl, __cn, __cns, __n) \
    for (__cn = SYS_SLIST_PEEK_HEAD_CONTAINER(__sl, __cn, __n),   \
        __cns = SYS_SLIST_PEEK_NEXT_CONTAINER(__cn, __n);         \
         __cn;                                                    \
         __cn = __cns, __cns = SYS_SLIST_PEEK_NEXT_CONTAINER(__cn, __n))

/**
 * @brief Initialize a list
 *
 * @param list A pointer on the list to initialize
 */
static inline void sys_slist_init(sys_slist_t *list)
{
    list->head = NULL;
    list->tail = NULL;
}

#define SYS_SLIST_STATIC_INIT(ptr_to_list) \
    {                                      \
        NULL, NULL                         \
    }

/**
 * @brief Test if the given list is empty
 *
 * @param list A pointer on the list to test
 *
 * @return a boolean, true if it's empty, false otherwise
 */
static inline bool sys_slist_is_empty(sys_slist_t *list)
{
    return (!list->head);
}

/**
 * @brief Peek the first node from the list
 *
 * @param list A point on the list to peek the first node from
 *
 * @return A pointer on the first node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_head(sys_slist_t *list)
{
    return list->head;
}

/**
 * @brief Peek the last node from the list
 *
 * @param list A point on the list to peek the last node from
 *
 * @return A pointer on the last node of the list (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_tail(sys_slist_t *list)
{
    return list->tail;
}

/**
 * @brief Peek the next node from current node, node is not NULL
 *
 * Faster then sys_slist_peek_next() if node is known not to be NULL.
 *
 * @param node A pointer on the node where to peek the next node
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next_no_check(sys_snode_t *node)
{
    return node->next;
}

/**
 * @brief Peek the next node from current node
 *
 * @param node A pointer on the node where to peek the next node
 *
 * @return a pointer on the next node (or NULL if none)
 */
static inline sys_snode_t *sys_slist_peek_next(sys_snode_t *node)
{
    return node ? sys_slist_peek_next_no_check(node) : NULL;
}

/**
 * @brief Prepend a node to the given list
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param node A pointer on the node to prepend
 */
static inline void sys_slist_prepend(sys_slist_t *list,
                                     sys_snode_t *node)
{
    node->next = list->head;
    list->head = node;

    if (!list->tail) {
        list->tail = list->head;
    }
}

/**
 * @brief Append a node to the given list
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param node A pointer on the node to append
 */
static inline void sys_slist_append(sys_slist_t *list,
                                    sys_snode_t *node)
{
    node->next = NULL;

    if (!list->tail) {
        list->tail = node;
        list->head = node;
    } else {
        list->tail->next = node;
        list->tail = node;
    }
}

/**
 * @brief Append a list to the given list
 *
 * Append a singly-linked, NULL-terminated list consisting of nodes containing
 * the pointer to the next node as the first element of a node, to @a list.
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param head A pointer to the first element of the list to append
 * @param tail A pointer to the last element of the list to append
 */
static inline void sys_slist_append_list(sys_slist_t *list,
                                         void *head, void *tail)
{
    if (!list->tail) {
        list->head = (sys_snode_t *)head;
        list->tail = (sys_snode_t *)tail;
    } else {
        list->tail->next = (sys_snode_t *)head;
        list->tail = (sys_snode_t *)tail;
    }
}

/**
 * @brief merge two slists, appending the second one to the first
 *
 * When the operation is completed, the appending list is empty.
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param list_to_append A pointer to the list to append.
 */
static inline void sys_slist_merge_slist(sys_slist_t *list,
                                         sys_slist_t *list_to_append)
{
    sys_slist_append_list(list, list_to_append->head,
                          list_to_append->tail);
    sys_slist_init(list_to_append);
}

/**
 * @brief Insert a node to the given list
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param prev A pointer on the previous node
 * @param node A pointer on the node to insert
 */
static inline void sys_slist_insert(sys_slist_t *list,
                                    sys_snode_t *prev,
                                    sys_snode_t *node)
{
    if (!prev) {
        sys_slist_prepend(list, node);
    } else if (!prev->next) {
        sys_slist_append(list, node);
    } else {
        node->next = prev->next;
        prev->next = node;
    }
}

/**
 * @brief Fetch and remove the first node of the given list
 *
 * List must be known to be non-empty.
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 *
 * @return A pointer to the first node of the list
 */
static inline sys_snode_t *sys_slist_get_not_empty(sys_slist_t *list)
{
    sys_snode_t *node = list->head;

    list->head = node->next;
    if (list->tail == node) {
        list->tail = list->head;
    }

    return node;
}

/**
 * @brief Fetch and remove the first node of the given list
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 *
 * @return A pointer to the first node of the list (or NULL if empty)
 */
static inline sys_snode_t *sys_slist_get(sys_slist_t *list)
{
    return sys_slist_is_empty(list) ? NULL : sys_slist_get_not_empty(list);
}

/**
 * @brief Remove a node
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param prev_node A pointer on the previous node
 *        (can be NULL, which means the node is the list's head)
 * @param node A pointer on the node to remove
 */
static inline void sys_slist_remove(sys_slist_t *list,
                                    sys_snode_t *prev_node,
                                    sys_snode_t *node)
{
    if (!prev_node) {
        list->head = node->next;

        /* Was node also the tail? */
        if (list->tail == node) {
            list->tail = list->head;
        }
    } else {
        prev_node->next = node->next;

        /* Was node the tail? */
        if (list->tail == node) {
            list->tail = prev_node;
        }
    }

    node->next = NULL;
}

/**
 * @brief Find and remove a node from a list
 *
 * This and other sys_slist_*() functions are not thread safe.
 *
 * @param list A pointer on the list to affect
 * @param node A pointer on the node to remove from the list
 *
 * @return true if node was removed
 */
static inline bool sys_slist_find_and_remove(sys_slist_t *list,
                                             sys_snode_t *node)
{
    sys_snode_t *prev = NULL;
    sys_snode_t *test;

    SYS_SLIST_FOR_EACH_NODE(list, test)
    {
        if (test == node) {
            sys_slist_remove(list, prev, node);
            return true;
        }

        prev = test;
    }

    return false;
}

#ifdef __cplusplus
}
#endif

#endif /* __SLIST_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/stack.h
================================================
/**
 * @file stack.h
 * Stack usage analysis helpers
 */

/*
 * Copyright (c) 2015 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _MISC_STACK_H_
#define _MISC_STACK_H_

#include 

#if defined(CONFIG_INIT_STACKS)
static inline size_t stack_unused_space_get(const char *stack, size_t size)
{
    size_t unused = 0;
    int i;

#ifdef CONFIG_STACK_SENTINEL
    /* First 4 bytes of the stack buffer reserved for the sentinel
	 * value, it won't be 0xAAAAAAAA for thread stacks.
	 */
    stack += 4;
#endif

    /* TODO Currently all supported platforms have stack growth down and
	 * there is no Kconfig option to configure it so this always build
	 * "else" branch.  When support for platform with stack direction up
	 * (or configurable direction) is added this check should be confirmed
	 * that correct Kconfig option is used.
	 */
#if defined(STACK_GROWS_UP)
    for (i = size - 1; i >= 0; i--) {
        if ((unsigned char)stack[i] == 0xaa) {
            unused++;
        } else {
            break;
        }
    }
#else
    for (i = 0; i < size; i++) {
        if ((unsigned char)stack[i] == 0xaa) {
            unused++;
        } else {
            break;
        }
    }
#endif
    return unused;
}
#else
static inline size_t stack_unused_space_get(const char *stack, size_t size)
{
    return 0;
}
#endif

#if defined(CONFIG_INIT_STACKS) && defined(CONFIG_PRINTK)
static inline void stack_analyze(const char *name, const char *stack,
                                 unsigned int size)
{
    unsigned int pcnt, unused = 0;

    unused = stack_unused_space_get(stack, size);

    /* Calculate the real size reserved for the stack */
    pcnt = ((size - unused) * 100) / size;

    printk("%s (real size %u):\tunused %u\tusage %u / %u (%u %%)\n", name,
           size, unused, size - unused, size, pcnt);
}
#else
static inline void stack_analyze(const char *name, const char *stack,
                                 unsigned int size)
{
}
#endif

#define STACK_ANALYZE(name, sym)                    \
    stack_analyze(name, K_THREAD_STACK_BUFFER(sym), \
                  K_THREAD_STACK_SIZEOF(sym))

#endif /* _MISC_STACK_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/util.h
================================================
/*
 * Copyright (c) 2011-2014, Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Misc utilities
 *
 * Misc utilities usable by the kernel and application code.
 */

#ifndef _UTIL__H_
#define _UTIL__H_

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include 
#if defined(BFLB_BLE)
#include 
#include "utils_string.h"
#endif

/* Helper to pass a int as a pointer or vice-versa.
 * Those are available for 32 bits architectures:
 */
#define POINTER_TO_UINT(x) ((u32_t)(x))
#define UINT_TO_POINTER(x) ((void *)(x))
#define POINTER_TO_INT(x)  ((s32_t)(x))
#define INT_TO_POINTER(x)  ((void *)(x))

/* Evaluates to 0 if cond is true-ish; compile error otherwise */
#define ZERO_OR_COMPILE_ERROR(cond) ((int)sizeof(char[1 - 2 * !(cond)]) - 1)

/* Evaluates to 0 if array is an array; compile error if not array (e.g.
 * pointer)
 */
#define IS_ARRAY(array)                                  \
    ZERO_OR_COMPILE_ERROR(                               \
        !__builtin_types_compatible_p(__typeof__(array), \
                                      __typeof__(&(array)[0])))

/* Evaluates to number of elements in an array; compile error if not
 * an array (e.g. pointer)
 */
#define ARRAY_SIZE(array)              \
    ((unsigned long)(IS_ARRAY(array) + \
                     (sizeof(array) / sizeof((array)[0]))))

/* Evaluates to 1 if ptr is part of array, 0 otherwise; compile error if
 * "array" argument is not an array (e.g. "ptr" and "array" mixed up)
 */
#define PART_OF_ARRAY(array, ptr) \
    ((ptr) && ((ptr) >= &array[0] && (ptr) < &array[ARRAY_SIZE(array)]))

#define CONTAINER_OF(ptr, type, field) \
    ((type *)(((char *)(ptr)) - offsetof(type, field)))

/* round "x" up/down to next multiple of "align" (which must be a power of 2) */
#define ROUND_UP(x, align)                               \
    (((unsigned long)(x) + ((unsigned long)align - 1)) & \
     ~((unsigned long)align - 1))
#define ROUND_DOWN(x, align) ((unsigned long)(x) & ~((unsigned long)align - 1))

#define ceiling_fraction(numerator, divider) \
    (((numerator) + ((divider)-1)) / (divider))

#ifdef INLINED
#define INLINE inline
#else
#define INLINE
#endif

#ifndef MAX
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif

#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif

void get_bytearray_from_string(char **params, uint8_t *result, int array_size);
void get_uint8_from_string(char **params, uint8_t *result);
void get_uint16_from_string(char **params, uint16_t *result);
void get_uint32_from_string(char **params, uint32_t *result);
void reverse_bytearray(uint8_t *src, uint8_t *result, int array_size);
void reverse_bytearray(uint8_t *src, uint8_t *result, int array_size);
unsigned int find_lsb_set(uint32_t data);

static inline int is_power_of_two(unsigned int x)
{
    return (x != 0) && !(x & (x - 1));
}

static inline s64_t arithmetic_shift_right(s64_t value, u8_t shift)
{
    s64_t sign_ext;

    if (shift == 0) {
        return value;
    }

    /* extract sign bit */
    sign_ext = (value >> 63) & 1;

    /* make all bits of sign_ext be the same as the value's sign bit */
    sign_ext = -sign_ext;

    /* shift value and fill opened bit positions with sign bit */
    return (value >> shift) | (sign_ext << (64 - shift));
}

#endif /* !_ASMLANGUAGE */

/* KB, MB, GB */
#define KB(x) ((x) << 10)
#define MB(x) (KB(x) << 10)
#define GB(x) (MB(x) << 10)

/* KHZ, MHZ */
#define KHZ(x) ((x)*1000)
#define MHZ(x) (KHZ(x) * 1000)

#define BIT_MASK(n) (BIT(n) - 1)

/**
 * @brief Check for macro definition in compiler-visible expressions
 *
 * This trick was pioneered in Linux as the config_enabled() macro.
 * The madness has the effect of taking a macro value that may be
 * defined to "1" (e.g. CONFIG_MYFEATURE), or may not be defined at
 * all and turning it into a literal expression that can be used at
 * "runtime".  That is, it works similarly to
 * "defined(CONFIG_MYFEATURE)" does except that it is an expansion
 * that can exist in a standard expression and be seen by the compiler
 * and optimizer.  Thus much ifdef usage can be replaced with cleaner
 * expressions like:
 *
 *     if (IS_ENABLED(CONFIG_MYFEATURE))
 *             myfeature_enable();
 *
 * INTERNAL
 * First pass just to expand any existing macros, we need the macro
 * value to be e.g. a literal "1" at expansion time in the next macro,
 * not "(1)", etc...  Standard recursive expansion does not work.
 */
#define IS_ENABLED(config_macro) _IS_ENABLED1(config_macro)

/* Now stick on a "_XXXX" prefix, it will now be "_XXXX1" if config_macro
 * is "1", or just "_XXXX" if it's undefined.
 *   ENABLED:   _IS_ENABLED2(_XXXX1)
 *   DISABLED   _IS_ENABLED2(_XXXX)
 */
#define _IS_ENABLED1(config_macro) _IS_ENABLED2(_XXXX##config_macro)

/* Here's the core trick, we map "_XXXX1" to "_YYYY," (i.e. a string
 * with a trailing comma), so it has the effect of making this a
 * two-argument tuple to the preprocessor only in the case where the
 * value is defined to "1"
 *   ENABLED:    _YYYY,    <--- note comma!
 *   DISABLED:   _XXXX
 */
#define _XXXX1 _YYYY,

/* Then we append an extra argument to fool the gcc preprocessor into
 * accepting it as a varargs macro.
 *                         arg1   arg2  arg3
 *   ENABLED:   _IS_ENABLED3(_YYYY,    1,    0)
 *   DISABLED   _IS_ENABLED3(_XXXX 1,  0)
 */
#define _IS_ENABLED2(one_or_two_args) _IS_ENABLED3(one_or_two_args 1, 0)

/* And our second argument is thus now cooked to be 1 in the case
 * where the value is defined to 1, and 0 if not:
 */
#define _IS_ENABLED3(ignore_this, val, ...) val

/**
 * Macros for doing code-generation with the preprocessor.
 *
 * Generally it is better to generate code with the preprocessor than
 * to copy-paste code or to generate code with the build system /
 * python script's etc.
 *
 * http://stackoverflow.com/a/12540675
 */
#define UTIL_EMPTY(...)
#define UTIL_DEFER(...)    __VA_ARGS__ UTIL_EMPTY()
#define UTIL_OBSTRUCT(...) __VA_ARGS__ UTIL_DEFER(UTIL_EMPTY)()
#define UTIL_EXPAND(...)   __VA_ARGS__

#define UTIL_EVAL(...)  UTIL_EVAL1(UTIL_EVAL1(UTIL_EVAL1(__VA_ARGS__)))
#define UTIL_EVAL1(...) UTIL_EVAL2(UTIL_EVAL2(UTIL_EVAL2(__VA_ARGS__)))
#define UTIL_EVAL2(...) UTIL_EVAL3(UTIL_EVAL3(UTIL_EVAL3(__VA_ARGS__)))
#define UTIL_EVAL3(...) UTIL_EVAL4(UTIL_EVAL4(UTIL_EVAL4(__VA_ARGS__)))
#define UTIL_EVAL4(...) UTIL_EVAL5(UTIL_EVAL5(UTIL_EVAL5(__VA_ARGS__)))
#define UTIL_EVAL5(...) __VA_ARGS__

#define UTIL_CAT(a, ...)           UTIL_PRIMITIVE_CAT(a, __VA_ARGS__)
#define UTIL_PRIMITIVE_CAT(a, ...) a##__VA_ARGS__

#define UTIL_INC(x) UTIL_PRIMITIVE_CAT(UTIL_INC_, x)
#define UTIL_INC_0  1
#define UTIL_INC_1  2
#define UTIL_INC_2  3
#define UTIL_INC_3  4
#define UTIL_INC_4  5
#define UTIL_INC_5  6
#define UTIL_INC_6  7
#define UTIL_INC_7  8
#define UTIL_INC_8  9
#define UTIL_INC_9  10
#define UTIL_INC_10 11
#define UTIL_INC_11 12
#define UTIL_INC_12 13
#define UTIL_INC_13 14
#define UTIL_INC_14 15
#define UTIL_INC_15 16
#define UTIL_INC_16 17
#define UTIL_INC_17 18
#define UTIL_INC_18 19
#define UTIL_INC_19 19

#define UTIL_DEC(x) UTIL_PRIMITIVE_CAT(UTIL_DEC_, x)
#define UTIL_DEC_0  0
#define UTIL_DEC_1  0
#define UTIL_DEC_2  1
#define UTIL_DEC_3  2
#define UTIL_DEC_4  3
#define UTIL_DEC_5  4
#define UTIL_DEC_6  5
#define UTIL_DEC_7  6
#define UTIL_DEC_8  7
#define UTIL_DEC_9  8
#define UTIL_DEC_10 9
#define UTIL_DEC_11 10
#define UTIL_DEC_12 11
#define UTIL_DEC_13 12
#define UTIL_DEC_14 13
#define UTIL_DEC_15 14
#define UTIL_DEC_16 15
#define UTIL_DEC_17 16
#define UTIL_DEC_18 17
#define UTIL_DEC_19 18

#define UTIL_CHECK_N(x, n, ...) n
#define UTIL_CHECK(...)         UTIL_CHECK_N(__VA_ARGS__, 0, )

#define UTIL_NOT(x) UTIL_CHECK(UTIL_PRIMITIVE_CAT(UTIL_NOT_, x))
#define UTIL_NOT_0  ~, 1,

#define UTIL_COMPL(b) UTIL_PRIMITIVE_CAT(UTIL_COMPL_, b)
#define UTIL_COMPL_0  1
#define UTIL_COMPL_1  0

#define UTIL_BOOL(x) UTIL_COMPL(UTIL_NOT(x))

#define UTIL_IIF(c)        UTIL_PRIMITIVE_CAT(UTIL_IIF_, c)
#define UTIL_IIF_0(t, ...) __VA_ARGS__
#define UTIL_IIF_1(t, ...) t

#define UTIL_IF(c) UTIL_IIF(UTIL_BOOL(c))

#define UTIL_EAT(...)
#define UTIL_EXPAND(...) __VA_ARGS__
#define UTIL_WHEN(c)     UTIL_IF(c) \
(UTIL_EXPAND, UTIL_EAT)

#define UTIL_REPEAT(count, macro, ...)           \
    UTIL_WHEN(count)                             \
    (                                            \
        UTIL_OBSTRUCT(UTIL_REPEAT_INDIRECT)()(   \
            UTIL_DEC(count), macro, __VA_ARGS__) \
            UTIL_OBSTRUCT(macro)(                \
                UTIL_DEC(count), __VA_ARGS__))
#define UTIL_REPEAT_INDIRECT() UTIL_REPEAT

/**
 * Generates a sequence of code.
 * Useful for generating code like;
 *
 * NRF_PWM0, NRF_PWM1, NRF_PWM2,
 *
 * @arg LEN: The length of the sequence. Must be defined and less than
 * 20.
 *
 * @arg F(i, F_ARG): A macro function that accepts two arguments.
 *  F is called repeatedly, the first argument
 *  is the index in the sequence, and the second argument is the third
 *  argument given to UTIL_LISTIFY.
 *
 * Example:
 *
 *    \#define FOO(i, _) NRF_PWM ## i ,
 *    { UTIL_LISTIFY(PWM_COUNT, FOO) }
 *    // The above two lines will generate the below:
 *    { NRF_PWM0 , NRF_PWM1 , }
 *
 * @note Calling UTIL_LISTIFY with undefined arguments has undefined
 * behaviour.
 */
#define UTIL_LISTIFY(LEN, F, F_ARG) UTIL_EVAL(UTIL_REPEAT(LEN, F, F_ARG))

#if defined(BFLB_BLE)
/**
 * @brief      Convert a single character into a hexadecimal nibble.
 *
 * @param[in]  c     The character to convert
 * @param      x     The address of storage for the converted number.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int char2hex(char c, u8_t *x);

/**
 * @brief      Convert a single hexadecimal nibble into a character.
 *
 * @param[in]  c     The number to convert
 * @param      x     The address of storage for the converted character.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int hex2char(u8_t x, char *c);

/**
 * @brief      Convert a binary array into string representation.
 *
 * @param[in]  buf     The binary array to convert
 * @param[in]  buflen  The length of the binary array to convert
 * @param[out] hex     Address of where to store the string representation.
 * @param[in]  hexlen  Size of the storage area for string representation.
 *
 * @return     The length of the converted string, or 0 if an error occurred.
 */
size_t bin2hex(const u8_t *buf, size_t buflen, char *hex, size_t hexlen);

/*
 * Convert hex string to byte string
 * Return number of bytes written to buf, or 0 on error
 * @return     The length of the converted array, or 0 if an error occurred.
 */

/**
 * @brief      Convert a hexadecimal string into a binary array.
 *
 * @param[in]  hex     The hexadecimal string to convert
 * @param[in]  hexlen  The length of the hexadecimal string to convert.
 * @param[out] buf     Address of where to store the binary data
 * @param[in]  buflen  Size of the storage area for binary data
 *
 * @return     The length of the binary array , or 0 if an error occurred.
 */
size_t hex2bin(const char *hex, size_t hexlen, u8_t *buf, size_t buflen);

/**
 * @brief      Convert a u8_t into decimal string representation.
 *
 * Convert a u8_t value into ASCII decimal string representation.
 * The string is terminated if there is enough space in buf.
 *
 * @param[out] buf     Address of where to store the string representation.
 * @param[in]  buflen  Size of the storage area for string representation.
 * @param[in]  value   The value to convert to decimal string
 *
 * @return     The length of the converted string (excluding terminator if
 *             any), or 0 if an error occurred.
 */
u8_t u8_to_dec(char *buf, u8_t buflen, u8_t value);
#endif //#if defined(BFLB_BLE)
#ifdef __cplusplus
}
#endif

#endif /* _UTIL__H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/misc/utils_string.h
================================================
#ifndef __UTILS_STRING_H__
#define __UTILS_STRING_H__
void get_bytearray_from_string(char **params, uint8_t *result, int array_size);
void get_uint8_from_string(char **params, uint8_t *result);
void get_uint16_from_string(char **params, uint16_t *result);
void get_uint32_from_string(char **params, uint32_t *result);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/net/buf.h
================================================
/** @file
 *  @brief Buffer management.
 */

/*
 * Copyright (c) 2015 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef __NET_BUF_H
#define __NET_BUF_H

#include 
#include 
#include 
#include 
#include "../../port/include/ble_config.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Network buffer library
 * @defgroup net_buf Network Buffer Library
 * @ingroup networking
 * @{
 */

/* Alignment needed for various parts of the buffer definition */
#define __net_buf_align __aligned(sizeof(int))

/** @def NET_BUF_SIMPLE_DEFINE
 *  @brief Define a net_buf_simple stack variable.
 *
 *  This is a helper macro which is used to define a net_buf_simple object
 *  on the stack.
 *
 *  @param _name Name of the net_buf_simple object.
 *  @param _size Maximum data storage for the buffer.
 */
#define NET_BUF_SIMPLE_DEFINE(_name, _size) \
    u8_t net_buf_data_##_name[_size];       \
    struct net_buf_simple _name = {         \
        .data = net_buf_data_##_name,       \
        .len = 0,                           \
        .size = _size,                      \
        .__buf = net_buf_data_##_name,      \
    }

/** @def NET_BUF_SIMPLE_DEFINE_STATIC
 *  @brief Define a static net_buf_simple variable.
 *
 *  This is a helper macro which is used to define a static net_buf_simple
 *  object.
 *
 *  @param _name Name of the net_buf_simple object.
 *  @param _size Maximum data storage for the buffer.
 */
#define NET_BUF_SIMPLE_DEFINE_STATIC(_name, _size)        \
    static /*__noinit*/ u8_t net_buf_data_##_name[_size]; \
    static struct net_buf_simple _name = {                \
        .data = net_buf_data_##_name,                     \
        .len = 0,                                         \
        .size = _size,                                    \
        .__buf = net_buf_data_##_name,                    \
    }

#if (BFLB_STATIC_ALLOC_MEM)
enum {
    HCI_CMD = 0,
    HCI_RX,
    NUM_COMPLETE,
    ACL_IN,
    DISCARDABLE,
    ACL_TX,
    FRAG,
    PREP,

};
#endif
/** @brief Simple network buffer representation.
 *
 *  This is a simpler variant of the net_buf object (in fact net_buf uses
 *  net_buf_simple internally). It doesn't provide any kind of reference
 *  counting, user data, dynamic allocation, or in general the ability to
 *  pass through kernel objects such as FIFOs.
 *
 *  The main use of this is for scenarios where the meta-data of the normal
 *  net_buf isn't needed and causes too much overhead. This could be e.g.
 *  when the buffer only needs to be allocated on the stack or when the
 *  access to and lifetime of the buffer is well controlled and constrained.
 *
 */
struct net_buf_simple {
    /** Pointer to the start of data in the buffer. */
    u8_t *data;

    /** Length of the data behind the data pointer. */
    u16_t len;

    /** Amount of data that this buffer can store. */
    u16_t size;

    /** Start of the data storage. Not to be accessed directly
	 *  (the data pointer should be used instead).
	 */
    u8_t *__buf;
};

/** @def NET_BUF_SIMPLE
 *  @brief Define a net_buf_simple stack variable and get a pointer to it.
 *
 *  This is a helper macro which is used to define a net_buf_simple object on
 *  the stack and the get a pointer to it as follows:
 *
 *  struct net_buf_simple *my_buf = NET_BUF_SIMPLE(10);
 *
 *  After creating the object it needs to be initialized by calling
 *  net_buf_simple_init().
 *
 *  @param _size Maximum data storage for the buffer.
 *
 *  @return Pointer to stack-allocated net_buf_simple object.
 */
#define NET_BUF_SIMPLE(_size)             \
    ((struct net_buf_simple *)(&(struct { \
        struct net_buf_simple buf;        \
        u8_t data[_size] __net_buf_align; \
    }){                                   \
        .buf.size = _size,                \
    }))

/** @brief Initialize a net_buf_simple object.
 *
 *  This needs to be called after creating a net_buf_simple object using
 *  the NET_BUF_SIMPLE macro.
 *
 *  @param buf Buffer to initialize.
 *  @param reserve_head Headroom to reserve.
 */
static inline void net_buf_simple_init(struct net_buf_simple *buf,
                                       size_t reserve_head)
{
    if (!buf->__buf) {
        buf->__buf = (u8_t *)buf + sizeof(*buf);
    }

    buf->data = buf->__buf + reserve_head;
    buf->len = 0;
}

/**
 * @brief Initialize a net_buf_simple object with data.
 *
 * Initialized buffer object with external data.
 *
 * @param buf Buffer to initialize.
 * @param data External data pointer
 * @param size Amount of data the pointed data buffer if able to fit.
 */
void net_buf_simple_init_with_data(struct net_buf_simple *buf,
                                   void *data, size_t size);

/**

 *  @brief Reset buffer
 *
 *  Reset buffer data so it can be reused for other purposes.
 *
 *  @param buf Buffer to reset.
 */
static inline void net_buf_simple_reset(struct net_buf_simple *buf)
{
    buf->len = 0;
    buf->data = buf->__buf;
}

/**
 * Clone buffer state, using the same data buffer.
 *
 * Initializes a buffer to point to the same data as an existing buffer.
 * Allows operations on the same data without altering the length and
 * offset of the original.
 *
 * @param original Buffer to clone.
 * @param clone The new clone.
 */
void net_buf_simple_clone(const struct net_buf_simple *original,
                          struct net_buf_simple *clone);

/**
 *  @brief Prepare data to be added at the end of the buffer
 *
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to increment the length with.
 *
 *  @return The original tail of the buffer.
 */
void *net_buf_simple_add(struct net_buf_simple *buf, size_t len);

/**
 *  @brief Copy bytes from memory to the end of the buffer
 *
 *  Copies the given number of bytes to the end of the buffer. Increments the
 *  data length of the  buffer to account for more data at the end.
 *
 *  @param buf Buffer to update.
 *  @param mem Location of data to be added.
 *  @param len Length of data to be added
 *
 *  @return The original tail of the buffer.
 */
void *net_buf_simple_add_mem(struct net_buf_simple *buf, const void *mem,
                             size_t len);

/**
 *  @brief Add (8-bit) byte at the end of the buffer
 *
 *  Adds a byte at the end of the buffer. Increments the data length of
 *  the  buffer to account for more data at the end.
 *
 *  @param buf Buffer to update.
 *  @param val byte value to be added.
 *
 *  @return Pointer to the value added
 */
u8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, u8_t val);

/**
 *  @brief Add 16-bit value at the end of the buffer
 *
 *  Adds 16-bit value in little endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be added.
 */
void net_buf_simple_add_le16(struct net_buf_simple *buf, u16_t val);

/**
 *  @brief Add 16-bit value at the end of the buffer
 *
 *  Adds 16-bit value in big endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be added.
 */
void net_buf_simple_add_be16(struct net_buf_simple *buf, u16_t val);

/**
 * @brief Add 24-bit value at the end of the buffer
 *
 * Adds 24-bit value in little endian format at the end of buffer.
 * Increments the data length of a buffer to account for more data
 * at the end.
 *
 * @param buf Buffer to update.
 * @param val 24-bit value to be added.
 */
void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val);

/**
 * @brief Add 24-bit value at the end of the buffer
 *
 * Adds 24-bit value in big endian format at the end of buffer.
 * Increments the data length of a buffer to account for more data
 * at the end.
 *
 * @param buf Buffer to update.
 * @param val 24-bit value to be added.
 */
void net_buf_simple_add_be24(struct net_buf_simple *buf, uint32_t val);

/**
 *  @brief Add 32-bit value at the end of the buffer
 *
 *  Adds 32-bit value in little endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 32-bit value to be added.
 */
void net_buf_simple_add_le32(struct net_buf_simple *buf, u32_t val);

/**
 *  @brief Add 32-bit value at the end of the buffer
 *
 *  Adds 32-bit value in big endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 32-bit value to be added.
 */
void net_buf_simple_add_be32(struct net_buf_simple *buf, u32_t val);

/**
 *  @brief Push data to the beginning of the buffer.
 *
 *  Modifies the data pointer and buffer length to account for more data
 *  in the beginning of the buffer.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to add to the beginning.
 *
 *  @return The new beginning of the buffer data.
 */
void *net_buf_simple_push(struct net_buf_simple *buf, size_t len);

/**
 *  @brief Push 16-bit value to the beginning of the buffer
 *
 *  Adds 16-bit value in little endian format to the beginning of the
 *  buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be pushed to the buffer.
 */
void net_buf_simple_push_le16(struct net_buf_simple *buf, u16_t val);

/**
 *  @brief Push 16-bit value to the beginning of the buffer
 *
 *  Adds 16-bit value in big endian format to the beginning of the
 *  buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be pushed to the buffer.
 */
void net_buf_simple_push_be16(struct net_buf_simple *buf, u16_t val);

/**
 *  @brief Push 8-bit value to the beginning of the buffer
 *
 *  Adds 8-bit value the beginning of the buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 8-bit value to be pushed to the buffer.
 */
void net_buf_simple_push_u8(struct net_buf_simple *buf, u8_t val);

/**
 * @brief Push 24-bit value to the beginning of the buffer
 *
 * Adds 24-bit value in little endian format to the beginning of the
 * buffer.
 *
 * @param buf Buffer to update.
 * @param val 24-bit value to be pushed to the buffer.
 */
void net_buf_simple_push_le24(struct net_buf_simple *buf, uint32_t val);

/**
 * @brief Push 24-bit value to the beginning of the buffer
 *
 * Adds 24-bit value in big endian format to the beginning of the
 * buffer.
 *
 * @param buf Buffer to update.
 * @param val 24-bit value to be pushed to the buffer.
 */
void net_buf_simple_push_be24(struct net_buf_simple *buf, uint32_t val);

/**
 *  @brief Remove data from the beginning of the buffer.
 *
 *  Removes data from the beginning of the buffer by modifying the data
 *  pointer and buffer length.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to remove.
 *
 *  @return New beginning of the buffer data.
 */
void *net_buf_simple_pull(struct net_buf_simple *buf, size_t len);

/**
 * @brief Remove data from the beginning of the buffer.
 *
 * Removes data from the beginning of the buffer by modifying the data
 * pointer and buffer length.
 *
 * @param buf Buffer to update.
 * @param len Number of bytes to remove.
 *
 * @return Pointer to the old location of the buffer data.
 */
void *net_buf_simple_pull_mem(struct net_buf_simple *buf, size_t len);

/**
 *  @brief Remove a 8-bit value from the beginning of the buffer
 *
 *  Same idea as with net_buf_simple_pull(), but a helper for operating
 *  on 8-bit values.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return The 8-bit removed value
 */
u8_t net_buf_simple_pull_u8(struct net_buf_simple *buf);

/**
 *  @brief Remove and convert 16 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_simple_pull(), but a helper for operating
 *  on 16-bit little endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 16-bit value converted from little endian to host endian.
 */
u16_t net_buf_simple_pull_le16(struct net_buf_simple *buf);

/**
 *  @brief Remove and convert 16 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_simple_pull(), but a helper for operating
 *  on 16-bit big endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 16-bit value converted from big endian to host endian.
 */
u16_t net_buf_simple_pull_be16(struct net_buf_simple *buf);

/**
 *  @brief Remove and convert 32 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_simple_pull(), but a helper for operating
 *  on 32-bit little endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 32-bit value converted from little endian to host endian.
 */
u32_t net_buf_simple_pull_le32(struct net_buf_simple *buf);

/**
 *  @brief Remove and convert 32 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_simple_pull(), but a helper for operating
 *  on 32-bit big endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 32-bit value converted from big endian to host endian.
 */
u32_t net_buf_simple_pull_be32(struct net_buf_simple *buf);

/**
 *  @brief Get the tail pointer for a buffer.
 *
 *  Get a pointer to the end of the data in a buffer.
 *
 *  @param buf Buffer.
 *
 *  @return Tail pointer for the buffer.
 */
static inline u8_t *net_buf_simple_tail(struct net_buf_simple *buf)
{
    return buf->data + buf->len;
}

/**
 *  @brief Check buffer headroom.
 *
 *  Check how much free space there is in the beginning of the buffer.
 *
 *  buf A valid pointer on a buffer
 *
 *  @return Number of bytes available in the beginning of the buffer.
 */
size_t net_buf_simple_headroom(struct net_buf_simple *buf);

/**
 *  @brief Check buffer tailroom.
 *
 *  Check how much free space there is at the end of the buffer.
 *
 *  @param buf A valid pointer on a buffer
 *
 *  @return Number of bytes available at the end of the buffer.
 */
size_t net_buf_simple_tailroom(struct net_buf_simple *buf);

/**
 *  @brief Parsing state of a buffer.
 *
 *  This is used for temporarily storing the parsing state of a buffer
 *  while giving control of the parsing to a routine which we don't
 *  control.
 */
struct net_buf_simple_state {
    /** Offset of the data pointer from the beginning of the storage */
    u16_t offset;
    /** Length of data */
    u16_t len;
};

/**
 *  @brief Save the parsing state of a buffer.
 *
 *  Saves the parsing state of a buffer so it can be restored later.
 *
 *  @param buf Buffer from which the state should be saved.
 *  @param state Storage for the state.
 */
static inline void net_buf_simple_save(struct net_buf_simple *buf,
                                       struct net_buf_simple_state *state)
{
    state->offset = net_buf_simple_headroom(buf);
    state->len = buf->len;
}

/**
 *  @brief Restore the parsing state of a buffer.
 *
 *  Restores the parsing state of a buffer from a state previously stored
 *  by net_buf_simple_save().
 *
 *  @param buf Buffer to which the state should be restored.
 *  @param state Stored state.
 */
static inline void net_buf_simple_restore(struct net_buf_simple *buf,
                                          struct net_buf_simple_state *state)
{
    buf->data = buf->__buf + state->offset;
    buf->len = state->len;
}

/** Flag indicating that the buffer has associated fragments. Only used
  * internally by the buffer handling code while the buffer is inside a
  * FIFO, meaning this never needs to be explicitly set or unset by the
  * net_buf API user. As long as the buffer is outside of a FIFO, i.e.
  * in practice always for the user for this API, the buf->frags pointer
  * should be used instead.
  */
#define NET_BUF_FRAGS BIT(0)
/** Flag indicating that the buffer's associated data pointer, points to
 * externally allocated memory. Therefore once ref goes down to zero, the
 * pointed data will not need to be deallocated. This never needs to be
 * explicitly set or unet by the net_buf API user. Such net_buf is
 * exclusively instantiated via net_buf_alloc_with_data() function.
 * Reference count mechanism however will behave the same way, and ref
 * count going to 0 will free the net_buf but no the data pointer in it.
 */
#define NET_BUF_EXTERNAL_DATA BIT(1)

/** @brief Network buffer representation.
  *
  * This struct is used to represent network buffers. Such buffers are
  * normally defined through the NET_BUF_POOL_*_DEFINE() APIs and allocated
  * using the net_buf_alloc() API.
  */
struct net_buf {
    union {
        /** Allow placing the buffer into sys_slist_t */
        sys_snode_t node;

        /** Fragments associated with this buffer. */
        struct net_buf *frags;
    };

    /** Reference count. */
    u8_t ref;

    /** Bit-field of buffer flags. */
    u8_t flags;

    /** Where the buffer should go when freed up. */
    u8_t pool_id;

    /* Union for convenience access to the net_buf_simple members, also
	 * preserving the old API.
	 */
    union {
        /* The ABI of this struct must match net_buf_simple */
        struct {
            /** Pointer to the start of data in the buffer. */
            u8_t *data;

            /** Length of the data behind the data pointer. */
            u16_t len;

            /** Amount of data that this buffer can store. */
            u16_t size;

            /** Start of the data storage. Not to be accessed
			 *  directly (the data pointer should be used
			 *  instead).
			 */
            u8_t *__buf;
        };

        struct net_buf_simple b;
    };

    /** System metadata for this buffer. */
    u8_t user_data[CONFIG_NET_BUF_USER_DATA_SIZE] __net_buf_align;
};

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
typedef void (*destroy_cb_t)(struct net_buf *buf);
#endif

struct net_buf_data_cb {
    u8_t *(*alloc)(struct net_buf *buf, size_t *size, s32_t timeout);
    u8_t *(*ref)(struct net_buf *buf, u8_t *data);
    void (*unref)(struct net_buf *buf, u8_t *data);
};

struct net_buf_data_alloc {
    const struct net_buf_data_cb *cb;
    void *alloc_data;
};

struct net_buf_pool {
    /** LIFO to place the buffer into when free */
    struct k_lifo free;

/** Number of buffers in pool */
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
    u16_t buf_count;
#else
    const u16_t buf_count;
#endif
    /** Number of uninitialized buffers */
    u16_t uninit_count;

#if defined(CONFIG_NET_BUF_POOL_USAGE)
    /** Amount of available buffers in the pool. */
    s16_t avail_count;

    /** Total size of the pool. */
    const u16_t pool_size;

    /** Name of the pool. Used when printing pool information. */
    const char *name;
#endif /* CONFIG_NET_BUF_POOL_USAGE */
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
    /** Optional destroy callback when buffer is freed. */
    void (*destroy)(struct net_buf *buf);

    /** Data allocation handlers. */
    struct net_buf_data_alloc *alloc;

    /** Start of buffer storage array */
    struct net_buf *__bufs;
#else
    /** Optional destroy callback when buffer is freed. */
    void (*const destroy)(struct net_buf *buf);

    /** Data allocation handlers. */
    const struct net_buf_data_alloc *alloc;

    /** Start of buffer storage array */
    struct net_buf *const __bufs;
#endif
};

#if defined(CONFIG_NET_BUF_POOL_USAGE)
#define NET_BUF_POOL_INITIALIZER(_pool, _alloc, _bufs, _count, _destroy) \
    {                                                                    \
        .alloc = _alloc,                                                 \
        .free = _K_LIFO_INITIALIZER(_pool.free),                         \
        .__bufs = _bufs,                                                 \
        .buf_count = _count,                                             \
        .uninit_count = _count,                                          \
        .avail_count = _count,                                           \
        .destroy = _destroy,                                             \
        .name = STRINGIFY(_pool),                                        \
    }
#else
#define NET_BUF_POOL_INITIALIZER(_pool, _alloc, _bufs, _count, _destroy) \
    {                                                                    \
        .alloc = _alloc,                                                 \
        .free = _K_LIFO_INITIALIZER(_pool.free),                         \
        .__bufs = _bufs,                                                 \
        .buf_count = _count,                                             \
        .uninit_count = _count,                                          \
        .destroy = _destroy,                                             \
    }
#endif /* CONFIG_NET_BUF_POOL_USAGE */

extern const struct net_buf_data_alloc net_buf_heap_alloc;

/** @def NET_BUF_POOL_HEAP_DEFINE
 *  @brief Define a new pool for buffers using the heap for the data.
 *
 *  Defines a net_buf_pool struct and the necessary memory storage (array of
 *  structs) for the needed amount of buffers. After this, the buffers can be
 *  accessed from the pool through net_buf_alloc. The pool is defined as a
 *  static variable, so if it needs to be exported outside the current module
 *  this needs to happen with the help of a separate pointer rather than an
 *  extern declaration.
 *
 *  The data payload of the buffers will be allocated from the heap using
 *  k_malloc, so CONFIG_HEAP_MEM_POOL_SIZE must be set to a positive value.
 *  This kind of pool does not support blocking on the data allocation, so
 *  the timeout passed to net_buf_alloc will be always treated as K_NO_WAIT
 *  when trying to allocate the data. This means that allocation failures,
 *  i.e. NULL returns, must always be handled cleanly.
 *
 *  If provided with a custom destroy callback, this callback is
 *  responsible for eventually calling net_buf_destroy() to complete the
 *  process of returning the buffer to the pool.
 *
 *  @param _name      Name of the pool variable.
 *  @param _count     Number of buffers in the pool.
 *  @param _destroy   Optional destroy callback when buffer is freed.
 */
#define NET_BUF_POOL_HEAP_DEFINE(_name, _count, _destroy)        \
    static struct net_buf net_buf_##_name[_count] __noinit;      \
    struct net_buf_pool _name __net_buf_align                    \
        __in_section(_net_buf_pool, static, _name) =             \
            NET_BUF_POOL_INITIALIZER(_name, &net_buf_heap_alloc, \
                                     net_buf_##_name, _count, _destroy)

struct net_buf_pool_fixed {
    size_t data_size;
    u8_t *data_pool;
};

extern const struct net_buf_data_cb net_buf_fixed_cb;

/** @def NET_BUF_POOL_FIXED_DEFINE
 *  @brief Define a new pool for buffers based on fixed-size data
 *
 *  Defines a net_buf_pool struct and the necessary memory storage (array of
 *  structs) for the needed amount of buffers. After this, the buffers can be
 *  accessed from the pool through net_buf_alloc. The pool is defined as a
 *  static variable, so if it needs to be exported outside the current module
 *  this needs to happen with the help of a separate pointer rather than an
 *  extern declaration.
 *
 *  The data payload of the buffers will be allocated from a byte array
 *  of fixed sized chunks. This kind of pool does not support blocking on
 *  the data allocation, so the timeout passed to net_buf_alloc will be
 *  always treated as K_NO_WAIT when trying to allocate the data. This means
 *  that allocation failures, i.e. NULL returns, must always be handled
 *  cleanly.
 *
 *  If provided with a custom destroy callback, this callback is
 *  responsible for eventually calling net_buf_destroy() to complete the
 *  process of returning the buffer to the pool.
 *
 *  @param _name      Name of the pool variable.
 *  @param _count     Number of buffers in the pool.
 *  @param _data_size Maximum data payload per buffer.
 *  @param _destroy   Optional destroy callback when buffer is freed.
 */
#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
#define NET_BUF_POOL_FIXED_DEFINE(_name, _count, _data_size, _destroy)     \
    static struct net_buf net_buf_##_name[_count];                         \
    static u8_t net_buf_data_##_name[_count][_data_size];                  \
    static const struct net_buf_pool_fixed net_buf_fixed_##_name = {       \
        .data_size = _data_size,                                           \
        .data_pool = (u8_t *)net_buf_data_##_name,                         \
    };                                                                     \
    static const struct net_buf_data_alloc net_buf_fixed_alloc_##_name = { \
        .cb = &net_buf_fixed_cb,                                           \
        .alloc_data = (void *)&net_buf_fixed_##_name,                      \
    };                                                                     \
    struct net_buf_pool _name __net_buf_align                              \
        __in_section(_net_buf_pool, static, _name) =                       \
            NET_BUF_POOL_INITIALIZER(_name, &net_buf_fixed_alloc_##_name,  \
                                     net_buf_##_name, _count, _destroy)
#endif

#if (!BFLB_BLE)
extern const struct net_buf_data_cb net_buf_var_cb;

/** @def NET_BUF_POOL_VAR_DEFINE
 *  @brief Define a new pool for buffers with variable size payloads
 *
 *  Defines a net_buf_pool struct and the necessary memory storage (array of
 *  structs) for the needed amount of buffers. After this, the buffers can be
 *  accessed from the pool through net_buf_alloc. The pool is defined as a
 *  static variable, so if it needs to be exported outside the current module
 *  this needs to happen with the help of a separate pointer rather than an
 *  extern declaration.
 *
 *  The data payload of the buffers will be based on a memory pool from which
 *  variable size payloads may be allocated.
 *
 *  If provided with a custom destroy callback, this callback is
 *  responsible for eventually calling net_buf_destroy() to complete the
 *  process of returning the buffer to the pool.
 *
 *  @param _name      Name of the pool variable.
 *  @param _count     Number of buffers in the pool.
 *  @param _data_size Total amount of memory available for data payloads.
 *  @param _destroy   Optional destroy callback when buffer is freed.
 */
#define NET_BUF_POOL_VAR_DEFINE(_name, _count, _data_size, _destroy)      \
    static struct net_buf _net_buf_##_name[_count] __noinit;              \
    K_MEM_POOL_DEFINE(net_buf_mem_pool_##_name, 16, _data_size, 1, 4);    \
    static const struct net_buf_data_alloc net_buf_data_alloc_##_name = { \
        .cb = &net_buf_var_cb,                                            \
        .alloc_data = &net_buf_mem_pool_##_name,                          \
    };                                                                    \
    struct net_buf_pool _name __net_buf_align                             \
        __in_section(_net_buf_pool, static, _name) =                      \
            NET_BUF_POOL_INITIALIZER(_name, &net_buf_data_alloc_##_name,  \
                                     _net_buf_##_name, _count, _destroy)
#endif

#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
/** @def NET_BUF_POOL_DEFINE
 *  @brief Define a new pool for buffers
 *
 *  Defines a net_buf_pool struct and the necessary memory storage (array of
 *  structs) for the needed amount of buffers. After this,the buffers can be
 *  accessed from the pool through net_buf_alloc. The pool is defined as a
 *  static variable, so if it needs to be exported outside the current module
 *  this needs to happen with the help of a separate pointer rather than an
 *  extern declaration.
 *
 *  If provided with a custom destroy callback this callback is
 *  responsible for eventually calling net_buf_destroy() to complete the
 *  process of returning the buffer to the pool.
 *
 *  @param _name     Name of the pool variable.
 *  @param _count    Number of buffers in the pool.
 *  @param _size     Maximum data size for each buffer.
 *  @param _ud_size  Amount of user data space to reserve.
 *  @param _destroy  Optional destroy callback when buffer is freed.
 */
#define NET_BUF_POOL_DEFINE(_name, _count, _size, _ud_size, _destroy) \
    BUILD_ASSERT(_ud_size <= CONFIG_NET_BUF_USER_DATA_SIZE);          \
    NET_BUF_POOL_FIXED_DEFINE(_name, _count, _size, _destroy)
#endif

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#if (BFLB_STATIC_ALLOC_MEM)
void net_buf_init(u8_t buf_type, struct net_buf_pool *buf_pool, u16_t buf_count, size_t data_size, destroy_cb_t destroy);
#else
void net_buf_init(struct net_buf_pool *buf_pool, u16_t buf_count, size_t data_size, destroy_cb_t destroy);
#endif
void net_buf_deinit(struct net_buf_pool *buf_pool);
#endif
/**
 *  @brief Looks up a pool based on its ID.
 *
 *  @param id Pool ID (e.g. from buf->pool_id).
 *
 *  @return Pointer to pool.
 */
struct net_buf_pool *net_buf_pool_get(int id);

/**
 *  @brief Get a zero-based index for a buffer.
 *
 *  This function will translate a buffer into a zero-based index,
 *  based on its placement in its buffer pool. This can be useful if you
 *  want to associate an external array of meta-data contexts with the
 *  buffers of a pool.
 *
 *  @param buf  Network buffer.
 *
 *  @return Zero-based index for the buffer.
 */
int net_buf_id(struct net_buf *buf);

/**
 *  @brief Allocate a new buffer from a pool.
 *
 *  Allocate a new buffer from a pool.
 *
 *  @param pool Which pool to allocate the buffer from.
 *  @param timeout Affects the action taken should the pool be empty.
 *         If K_NO_WAIT, then return immediately. If K_FOREVER, then
 *         wait as long as necessary. Otherwise, wait up to the specified
 *         number of milliseconds before timing out. Note that some types
 *         of data allocators do not support blocking (such as the HEAP
 *         type). In this case it's still possible for net_buf_alloc() to
 *         fail (return NULL) even if it was given K_FOREVER.
 *
 *  @return New buffer or NULL if out of buffers.
 */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_fixed_debug(struct net_buf_pool *pool,
                                          s32_t timeout, const char *func,
                                          int line);
#define net_buf_alloc_fixed(_pool, _timeout) \
    net_buf_alloc_fixed_debug(_pool, _timeout, __func__, __LINE__)
#else
struct net_buf *net_buf_alloc_fixed(struct net_buf_pool *pool, s32_t timeout);
#endif

#define net_buf_alloc(_pool, _timeout) net_buf_alloc_fixed(_pool, _timeout)

/**
 *  @brief Allocate a new buffer from a pool.
 *
 *  Allocate a new buffer from a pool.
 *
 *  @param pool Which pool to allocate the buffer from.
 *  @param size Amount of data the buffer must be able to fit.
 *  @param timeout Affects the action taken should the pool be empty.
 *         If K_NO_WAIT, then return immediately. If K_FOREVER, then
 *         wait as long as necessary. Otherwise, wait up to the specified
 *         number of milliseconds before timing out. Note that some types
 *         of data allocators do not support blocking (such as the HEAP
 *         type). In this case it's still possible for net_buf_alloc() to
 *         fail (return NULL) even if it was given K_FOREVER.
 *
 *  @return New buffer or NULL if out of buffers.
 */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_len_debug(struct net_buf_pool *pool, size_t size,
                                        s32_t timeout, const char *func,
                                        int line);
#define net_buf_alloc_len(_pool, _size, _timeout) \
    net_buf_alloc_len_debug(_pool, _size, _timeout, __func__, __LINE__)
#else
struct net_buf *net_buf_alloc_len(struct net_buf_pool *pool, size_t size,
                                  s32_t timeout);
#endif

/**
 *  @brief Allocate a new buffer from a pool but with external data pointer.
 *
 *  Allocate a new buffer from a pool, where the data pointer comes from the
 *  user and not from the pool.
 *
 *  @param pool Which pool to allocate the buffer from.
 *  @param data External data pointer
 *  @param size Amount of data the pointed data buffer if able to fit.
 *  @param timeout Affects the action taken should the pool be empty.
 *         If K_NO_WAIT, then return immediately. If K_FOREVER, then
 *         wait as long as necessary. Otherwise, wait up to the specified
 *         number of milliseconds before timing out. Note that some types
 *         of data allocators do not support blocking (such as the HEAP
 *         type). In this case it's still possible for net_buf_alloc() to
 *         fail (return NULL) even if it was given K_FOREVER.
 *
 *  @return New buffer or NULL if out of buffers.
 */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_alloc_with_data_debug(struct net_buf_pool *pool,
                                              void *data, size_t size,
                                              s32_t timeout, const char *func,
                                              int line);
#define net_buf_alloc_with_data(_pool, _data_, _size, _timeout)   \
    net_buf_alloc_with_data_debug(_pool, _data_, _size, _timeout, \
                                  __func__, __LINE__)
#else
struct net_buf *net_buf_alloc_with_data(struct net_buf_pool *pool,
                                        void *data, size_t size,
                                        s32_t timeout);
#endif

/**
 *  @brief Get a buffer from a FIFO.
 *
 *  Get buffer from a FIFO.
 *
 *  @param fifo Which FIFO to take the buffer from.
 *  @param timeout Affects the action taken should the FIFO be empty.
 *         If K_NO_WAIT, then return immediately. If K_FOREVER, then wait as
 *         long as necessary. Otherwise, wait up to the specified number of
 *         milliseconds before timing out.
 *
 *  @return New buffer or NULL if the FIFO is empty.
 */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_get_debug(struct k_fifo *fifo, s32_t timeout,
                                  const char *func, int line);
#define net_buf_get(_fifo, _timeout) \
    net_buf_get_debug(_fifo, _timeout, __func__, __LINE__)
#else
struct net_buf *net_buf_get(struct k_fifo *fifo, s32_t timeout);
#endif

/**
 *  @brief Destroy buffer from custom destroy callback
 *
 *  This helper is only intended to be used from custom destroy callbacks.
 *  If no custom destroy callback is given to NET_BUF_POOL_*_DEFINE() then
 *  there is no need to use this API.
 *
 *  @param buf Buffer to destroy.
 */
static inline void net_buf_destroy(struct net_buf *buf)
{
    struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);

    k_lifo_put(&pool->free, buf);
}

/**
 *  @brief Reset buffer
 *
 *  Reset buffer data and flags so it can be reused for other purposes.
 *
 *  @param buf Buffer to reset.
 */
void net_buf_reset(struct net_buf *buf);

/**
 *  @brief Initialize buffer with the given headroom.
 *
 *  Initializes a buffer with a given headroom. The buffer is not expected to
 *  contain any data when this API is called.
 *
 *  @param buf Buffer to initialize.
 *  @param reserve How much headroom to reserve.
 */
void net_buf_simple_reserve(struct net_buf_simple *buf, size_t reserve);

/**
 *  @brief Put a buffer into a list
 *
 *  Put a buffer to the end of a list. If the buffer contains follow-up
 *  fragments this function will take care of inserting them as well
 *  into the list.
 *
 *  @param list Which list to append the buffer to.
 *  @param buf Buffer.
 */
void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf);

/**
 *  @brief Get a buffer from a list.
 *
 *  Get buffer from a list. If the buffer had any fragments, these will
 *  automatically be recovered from the list as well and be placed to
 *  the buffer's fragment list.
 *
 *  @param list Which list to take the buffer from.
 *
 *  @return New buffer or NULL if the FIFO is empty.
 */
struct net_buf *net_buf_slist_get(sys_slist_t *list);

/**
 *  @brief Put a buffer into a FIFO
 *
 *  Put a buffer to the end of a FIFO. If the buffer contains follow-up
 *  fragments this function will take care of inserting them as well
 *  into the FIFO.
 *
 *  @param fifo Which FIFO to put the buffer to.
 *  @param buf Buffer.
 */
void net_buf_put(struct k_fifo *fifo, struct net_buf *buf);

/**
 *  @brief Decrements the reference count of a buffer.
 *
 *  Decrements the reference count of a buffer and puts it back into the
 *  pool if the count reaches zero.
 *
 *  @param buf A valid pointer on a buffer
 */
#if defined(CONFIG_NET_BUF_LOG)
void net_buf_unref_debug(struct net_buf *buf, const char *func, int line);
#define net_buf_unref(_buf) \
    net_buf_unref_debug(_buf, __func__, __LINE__)
#else
void net_buf_unref(struct net_buf *buf);
#endif

/**
 *  @brief Increment the reference count of a buffer.
 *
 *  @param buf A valid pointer on a buffer
 *
 *  @return the buffer newly referenced
 */
struct net_buf *net_buf_ref(struct net_buf *buf);

/**
 *  @brief Duplicate buffer
 *
 *  Duplicate given buffer including any data and headers currently stored.
 *
 *  @param buf A valid pointer on a buffer
 *  @param timeout Affects the action taken should the pool be empty.
 *         If K_NO_WAIT, then return immediately. If K_FOREVER, then
 *         wait as long as necessary. Otherwise, wait up to the specified
 *         number of milliseconds before timing out.
 *
 *  @return Duplicated buffer or NULL if out of buffers.
 */
struct net_buf *net_buf_clone(struct net_buf *buf, s32_t timeout);

/**
 *  @brief Get a pointer to the user data of a buffer.
 *
 *  @param buf A valid pointer on a buffer
 *
 *  @return Pointer to the user data of the buffer.
 */
static inline void *net_buf_user_data(const struct net_buf *buf)
{
    return (void *)buf->user_data;
}

/** @def net_buf_reserve
 *  @brief Initialize buffer with the given headroom.
 *
 *  Initializes a buffer with a given headroom. The buffer is not expected to
 *  contain any data when this API is called.
 *
 *  @param buf Buffer to initialize.
 *  @param reserve How much headroom to reserve.
 */
#define net_buf_reserve(buf, reserve) net_buf_simple_reserve(&(buf)->b, \
                                                             reserve)

/**
 *  @def net_buf_add
 *  @brief Prepare data to be added at the end of the buffer
 *
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to increment the length with.
 *
 *  @return The original tail of the buffer.
 */
#define net_buf_add(buf, len) net_buf_simple_add(&(buf)->b, len)

/**
 *  @def net_buf_add_mem
 *  @brief Copy bytes from memory to the end of the buffer
 *
 *  Copies the given number of bytes to the end of the buffer. Increments the
 *  data length of the  buffer to account for more data at the end.
 *
 *  @param buf Buffer to update.
 *  @param mem Location of data to be added.
 *  @param len Length of data to be added
 *
 *  @return The original tail of the buffer.
 */
#define net_buf_add_mem(buf, mem, len) net_buf_simple_add_mem(&(buf)->b, \
                                                              mem, len)

/**
 *  @def net_buf_add_u8
 *  @brief Add (8-bit) byte at the end of the buffer
 *
 *  Adds a byte at the end of the buffer. Increments the data length of
 *  the  buffer to account for more data at the end.
 *
 *  @param buf Buffer to update.
 *  @param val byte value to be added.
 *
 *  @return Pointer to the value added
 */
#define net_buf_add_u8(buf, val) net_buf_simple_add_u8(&(buf)->b, val)

/**
 *  @def net_buf_add_le16
 *  @brief Add 16-bit value at the end of the buffer
 *
 *  Adds 16-bit value in little endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be added.
 */
#define net_buf_add_le16(buf, val) net_buf_simple_add_le16(&(buf)->b, val)

/**
 *  @def net_buf_add_be16
 *  @brief Add 16-bit value at the end of the buffer
 *
 *  Adds 16-bit value in big endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be added.
 */
#define net_buf_add_be16(buf, val) net_buf_simple_add_be16(&(buf)->b, val)

/**
 *  @def net_buf_add_le32
 *  @brief Add 32-bit value at the end of the buffer
 *
 *  Adds 32-bit value in little endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 32-bit value to be added.
 */
#define net_buf_add_le32(buf, val) net_buf_simple_add_le32(&(buf)->b, val)

/**
 *  @def net_buf_add_be32
 *  @brief Add 32-bit value at the end of the buffer
 *
 *  Adds 32-bit value in big endian format at the end of buffer.
 *  Increments the data length of a buffer to account for more data
 *  at the end.
 *
 *  @param buf Buffer to update.
 *  @param val 32-bit value to be added.
 */
#define net_buf_add_be32(buf, val) net_buf_simple_add_be32(&(buf)->b, val)

/**
 *  @def net_buf_push
 *  @brief Push data to the beginning of the buffer.
 *
 *  Modifies the data pointer and buffer length to account for more data
 *  in the beginning of the buffer.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to add to the beginning.
 *
 *  @return The new beginning of the buffer data.
 */
#define net_buf_push(buf, len) net_buf_simple_push(&(buf)->b, len)

/**
 *  @def net_buf_push_le16
 *  @brief Push 16-bit value to the beginning of the buffer
 *
 *  Adds 16-bit value in little endian format to the beginning of the
 *  buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be pushed to the buffer.
 */
#define net_buf_push_le16(buf, val) net_buf_simple_push_le16(&(buf)->b, val)

/**
 *  @def net_buf_push_be16
 *  @brief Push 16-bit value to the beginning of the buffer
 *
 *  Adds 16-bit value in little endian format to the beginning of the
 *  buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 16-bit value to be pushed to the buffer.
 */
#define net_buf_push_be16(buf, val) net_buf_simple_push_be16(&(buf)->b, val)

/**
 *  @def net_buf_push_u8
 *  @brief Push 8-bit value to the beginning of the buffer
 *
 *  Adds 8-bit value the beginning of the buffer.
 *
 *  @param buf Buffer to update.
 *  @param val 8-bit value to be pushed to the buffer.
 */
#define net_buf_push_u8(buf, val) net_buf_simple_push_u8(&(buf)->b, val)

/**
 *  @def net_buf_pull
 *  @brief Remove data from the beginning of the buffer.
 *
 *  Removes data from the beginning of the buffer by modifying the data
 *  pointer and buffer length.
 *
 *  @param buf Buffer to update.
 *  @param len Number of bytes to remove.
 *
 *  @return New beginning of the buffer data.
 */
#define net_buf_pull(buf, len) net_buf_simple_pull(&(buf)->b, len)

/**
 * @def net_buf_pull_mem
 * @brief Remove data from the beginning of the buffer.
 *
 * Removes data from the beginning of the buffer by modifying the data
 * pointer and buffer length.
 *
 * @param buf Buffer to update.
 * @param len Number of bytes to remove.
 *
 * @return Pointer to the old beginning of the buffer data.
 */
#define net_buf_pull_mem(buf, len) net_buf_simple_pull_mem(&(buf)->b, len)

/**
 *  @def net_buf_pull_u8
 *  @brief Remove a 8-bit value from the beginning of the buffer
 *
 *  Same idea as with net_buf_pull(), but a helper for operating on
 *  8-bit values.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return The 8-bit removed value
 */
#define net_buf_pull_u8(buf) net_buf_simple_pull_u8(&(buf)->b)

/**
 *  @def net_buf_pull_le16
 *  @brief Remove and convert 16 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_pull(), but a helper for operating on
 *  16-bit little endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 16-bit value converted from little endian to host endian.
 */
#define net_buf_pull_le16(buf) net_buf_simple_pull_le16(&(buf)->b)

/**
 *  @def net_buf_pull_be16
 *  @brief Remove and convert 16 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_pull(), but a helper for operating on
 *  16-bit big endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 16-bit value converted from big endian to host endian.
 */
#define net_buf_pull_be16(buf) net_buf_simple_pull_be16(&(buf)->b)

/**
 *  @def net_buf_pull_le32
 *  @brief Remove and convert 32 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_pull(), but a helper for operating on
 *  32-bit little endian data.
 *
 *  @param buf A valid pointer on a buffer.
 *
 *  @return 32-bit value converted from little endian to host endian.
 */
#define net_buf_pull_le32(buf) net_buf_simple_pull_le32(&(buf)->b)

/**
 *  @def net_buf_pull_be32
 *  @brief Remove and convert 32 bits from the beginning of the buffer.
 *
 *  Same idea as with net_buf_pull(), but a helper for operating on
 *  32-bit big endian data.
 *
 *  @param buf A valid pointer on a buffer
 *
 *  @return 32-bit value converted from big endian to host endian.
 */
#define net_buf_pull_be32(buf) net_buf_simple_pull_be32(&(buf)->b)

/**
 *  @def net_buf_tailroom
 *  @brief Check buffer tailroom.
 *
 *  Check how much free space there is at the end of the buffer.
 *
 *  @param buf A valid pointer on a buffer
 *
 *  @return Number of bytes available at the end of the buffer.
 */
#define net_buf_tailroom(buf) net_buf_simple_tailroom(&(buf)->b)

/**
 *  @def net_buf_headroom
 *  @brief Check buffer headroom.
 *
 *  Check how much free space there is in the beginning of the buffer.
 *
 *  buf A valid pointer on a buffer
 *
 *  @return Number of bytes available in the beginning of the buffer.
 */
#define net_buf_headroom(buf) net_buf_simple_headroom(&(buf)->b)

/**
 *  @def net_buf_tail
 *  @brief Get the tail pointer for a buffer.
 *
 *  Get a pointer to the end of the data in a buffer.
 *
 *  @param buf Buffer.
 *
 *  @return Tail pointer for the buffer.
 */
#define net_buf_tail(buf) net_buf_simple_tail(&(buf)->b)

/** @brief Find the last fragment in the fragment list.
 *
 * @return Pointer to last fragment in the list.
 */
struct net_buf *net_buf_frag_last(struct net_buf *frags);

/** @brief Insert a new fragment to a chain of bufs.
 *
 *  Insert a new fragment into the buffer fragments list after the parent.
 *
 *  Note: This function takes ownership of the fragment reference so the
 *  caller is not required to unref.
 *
 *  @param parent Parent buffer/fragment.
 *  @param frag Fragment to insert.
 */
void net_buf_frag_insert(struct net_buf *parent, struct net_buf *frag);

/** @brief Add a new fragment to the end of a chain of bufs.
 *
 *  Append a new fragment into the buffer fragments list.
 *
 *  Note: This function takes ownership of the fragment reference so the
 *  caller is not required to unref.
 *
 *  @param head Head of the fragment chain.
 *  @param frag Fragment to add.
 *
 *  @return New head of the fragment chain. Either head (if head
 *          was non-NULL) or frag (if head was NULL).
 */
struct net_buf *net_buf_frag_add(struct net_buf *head, struct net_buf *frag);

/** @brief Delete existing fragment from a chain of bufs.
 *
 *  @param parent Parent buffer/fragment, or NULL if there is no parent.
 *  @param frag Fragment to delete.
 *
 *  @return Pointer to the buffer following the fragment, or NULL if it
 *          had no further fragments.
 */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *net_buf_frag_del_debug(struct net_buf *parent,
                                       struct net_buf *frag,
                                       const char *func, int line);
#define net_buf_frag_del(_parent, _frag) \
    net_buf_frag_del_debug(_parent, _frag, __func__, __LINE__)
#else
struct net_buf *net_buf_frag_del(struct net_buf *parent, struct net_buf *frag);
#endif

/**
 * @brief Copy len bytes from src starting from offset to dst buffer
 *
 * This routine assumes that dst is large enough to store @a len bytes
 * starting from offset at src.
 *
 * @param dst Destination buffer
 * @param dst_len Destination buffer max length
 * @param src Source buffer that may be fragmented
 * @param offset Starting point to copy from
 * @param len Number of bytes to copy
 * @return number of bytes copied if everything is ok
 * @return -ENOMEM on error
 */
size_t net_buf_linearize(void *dst, size_t dst_len, struct net_buf *src,
                         size_t offset, size_t len);

/**
 * @typedef net_buf_allocator_cb
 * @brief Network buffer allocator callback.
 *
 * @details The allocator callback is called when net_buf_append_bytes
 * needs to allocate a new net_buf.
 *
 * @param timeout Affects the action taken should the net buf pool be empty.
 *        If K_NO_WAIT, then return immediately. If K_FOREVER, then
 *        wait as long as necessary. Otherwise, wait up to the specified
 *        number of milliseconds before timing out.
 * @param user_data The user data given in net_buf_append_bytes call.
 * @return pointer to allocated net_buf or NULL on error.
 */
typedef struct net_buf *(*net_buf_allocator_cb)(s32_t timeout, void *user_data);

/**
 * @brief Append data to a list of net_buf
 *
 * @details Append data to a net_buf. If there is not enough space in the
 * net_buf then more net_buf will be added, unless there are no free net_buf
 * and timeout occurs.
 *
 * @param buf Network buffer.
 * @param len Total length of input data
 * @param value Data to be added
 * @param timeout Timeout is passed to the net_buf allocator callback.
 * @param allocate_cb When a new net_buf is required, use this callback.
 * @param user_data A user data pointer to be supplied to the allocate_cb.
 *        This pointer is can be anything from a mem_pool or a net_pkt, the
 *        logic is left up to the allocate_cb function.
 *
 * @return Length of data actually added. This may be less than input
 *         length if other timeout than K_FOREVER was used, and there
 *         were no free fragments in a pool to accommodate all data.
 */
size_t net_buf_append_bytes(struct net_buf *buf, size_t len,
                            const void *value, s32_t timeout,
                            net_buf_allocator_cb allocate_cb, void *user_data);

/**
 * @brief Skip N number of bytes in a net_buf
 *
 * @details Skip N number of bytes starting from fragment's offset. If the total
 * length of data is placed in multiple fragments, this function will skip from
 * all fragments until it reaches N number of bytes.  Any fully skipped buffers
 * are removed from the net_buf list.
 *
 * @param buf Network buffer.
 * @param len Total length of data to be skipped.
 *
 * @return Pointer to the fragment or
 *         NULL and pos is 0 after successful skip,
 *         NULL and pos is 0xffff otherwise.
 */
static inline struct net_buf *net_buf_skip(struct net_buf *buf, u16_t len)
{
    while (buf && len--) {
        net_buf_pull_u8(buf);
        if (!buf->len) {
            buf = net_buf_frag_del(NULL, buf);
        }
    }

    return buf;
}

/** @brief Calculate amount of bytes stored in fragments.
 *
 *  Calculates the total amount of data stored in the given buffer and the
 *  fragments linked to it.
 *
 *  @param buf Buffer to start off with.
 *
 *  @return Number of bytes in the buffer and its fragments.
 */
static inline size_t net_buf_frags_len(struct net_buf *buf)
{
    size_t bytes = 0;

    while (buf) {
        bytes += buf->len;
        buf = buf->frags;
    }

    return bytes;
}

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __NET_BUF_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/toolchain/common.h
================================================
/*
 * Copyright (c) 2010-2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_COMMON_H_
#define ZEPHYR_INCLUDE_TOOLCHAIN_COMMON_H_
/**
 * @file
 * @brief Common toolchain abstraction
 *
 * Macros to abstract compiler capabilities (common to all toolchains).
 */

/* Abstract use of extern keyword for compatibility between C and C++ */
#ifdef __cplusplus
#define EXTERN_C extern "C"
#else
#define EXTERN_C extern
#endif

/* Use TASK_ENTRY_CPP to tag task entry points defined in C++ files. */

#ifdef __cplusplus
#define TASK_ENTRY_CPP extern "C"
#endif

/*
 * Generate a reference to an external symbol.
 * The reference indicates to the linker that the symbol is required
 * by the module containing the reference and should be included
 * in the image if the module is in the image.
 *
 * The assembler directive ".set" is used to define a local symbol.
 * No memory is allocated, and the local symbol does not appear in
 * the symbol table.
 */

#ifdef _ASMLANGUAGE
#define REQUIRES(sym) .set sym##_Requires, sym
#else
#define REQUIRES(sym) __asm__(".set " #sym "_Requires, " #sym "\n\t");
#endif

#ifdef _ASMLANGUAGE
#define SECTION .section
#endif

#define CONFIG_RISCV 1
/*
 * If the project is being built for speed (i.e. not for minimum size) then
 * align functions and branches in executable sections to improve performance.
 */

#ifdef _ASMLANGUAGE

#if defined(CONFIG_X86)

#ifdef PERF_OPT
#define PERFOPT_ALIGN .balign 16
#else
#define PERFOPT_ALIGN .balign 1
#endif

#elif defined(CONFIG_ARM)

#define PERFOPT_ALIGN .balign 4

#elif defined(CONFIG_ARC)

#define PERFOPT_ALIGN .balign 4

#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || \
    defined(CONFIG_XTENSA)
#define PERFOPT_ALIGN .balign 4

#elif defined(CONFIG_ARCH_POSIX)

#else

#error Architecture unsupported

#endif

#define GC_SECTION(sym) SECTION.text.##sym, "ax"

#endif /* _ASMLANGUAGE */

/* force inlining a function */

#if !defined(_ASMLANGUAGE)
#ifdef CONFIG_COVERAGE
/*
     * The always_inline attribute forces a function to be inlined,
     * even ignoring -fno-inline. So for code coverage, do not
     * force inlining of these functions to keep their bodies around
     * so their number of executions can be counted.
     *
     * Note that "inline" is kept here for kobject_hash.c and
     * priv_stacks_hash.c. These are built without compiler flags
     * used for coverage. ALWAYS_INLINE cannot be empty as compiler
     * would complain about unused functions. Attaching unused
     * attribute would result in their text sections ballon more than
     * 10 times in size, as those functions are kept in text section.
     * So just keep "inline" here.
     */
#define ALWAYS_INLINE inline
#else
#define ALWAYS_INLINE inline __attribute__((always_inline))
#endif
#endif

#define Z_STRINGIFY(x) #x
#define STRINGIFY(s)   Z_STRINGIFY(s)

/* concatenate the values of the arguments into one */
#define _DO_CONCAT(x, y) x##y
#define _CONCAT(x, y)    _DO_CONCAT(x, y)

/* Additionally used as a sentinel by gen_syscalls.py to identify what
 * functions are system calls
 *
 * Note POSIX unit tests don't still generate the system call stubs, so
 * until https://github.com/zephyrproject-rtos/zephyr/issues/5006 is
 * fixed via possibly #4174, we introduce this hack -- which will
 * disallow us to test system calls in POSIX unit testing (currently
 * not used).
 */
#ifndef ZTEST_UNITTEST
#define __syscall static inline
#else
#define __syscall
#endif /* #ifndef ZTEST_UNITTEST */

#ifndef BUILD_ASSERT
/* compile-time assertion that makes the build fail */
#define BUILD_ASSERT(EXPR)                                  \
    enum _CONCAT(__build_assert_enum, __COUNTER__) {        \
        _CONCAT(__build_assert, __COUNTER__) = 1 / !!(EXPR) \
    }
#endif
#ifndef BUILD_ASSERT_MSG
/* build assertion with message -- common implementation swallows message. */
#define BUILD_ASSERT_MSG(EXPR, MSG) BUILD_ASSERT(EXPR)
#endif

/*
 * This is meant to be used in conjunction with __in_section() and similar
 * where scattered structure instances are concatened together by the linker
 * and walked by the code at run time just like a contiguous array of such
 * structures.
 *
 * Assemblers and linkers may insert alignment padding by default whose
 * size is larger than the natural alignment for those structures when
 * gathering various section segments together, messing up the array walk.
 * To prevent this, we need to provide an explicit alignment not to rely
 * on the default that might just work by luck.
 *
 * Alignment statements in  linker scripts are not sufficient as
 * the assembler may add padding by itself to each segment when switching
 * between sections within the same file even if it merges many such segments
 * into a single section in the end.
 */
#define Z_DECL_ALIGN(type) __aligned(__alignof(type)) type

/*
 * Convenience helper combining __in_section() and Z_DECL_ALIGN().
 * The section name is the struct type prepended with an underscore.
 * The subsection is "static" and the subsubsection is the variable name.
 */
#define Z_STRUCT_SECTION_ITERABLE(struct_type, name) \
    Z_DECL_ALIGN(struct struct_type)                 \
    name                                             \
        __in_section(_##struct_type, static, name) __used

/*
 * Itterator for structure instances gathered by Z_STRUCT_SECTION_ITERABLE().
 * The linker must provide a __list_start symbol and a
 * __list_end symbol to mark the start and the end of the
 * list of struct objects to iterate over.
 */
#define Z_STRUCT_SECTION_FOREACH(struct_type, iterator)               \
    extern struct struct_type _CONCAT(_##struct_type, _list_start)[]; \
    extern struct struct_type _CONCAT(_##struct_type, _list_end)[];   \
    for (struct struct_type *iterator =                               \
             _CONCAT(_##struct_type, _list_start);                    \
         ({ __ASSERT(iterator <= _CONCAT(_##struct_type, _list_end), \
			 "unexpected list end location"); \
		iterator < _CONCAT(_##struct_type, _list_end); });                                                       \
         iterator++)

#endif /* ZEPHYR_INCLUDE_TOOLCHAIN_COMMON_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/toolchain/gcc.h
================================================
/*
 * Copyright (c) 2010-2014,2017 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_GCC_H_
#define ZEPHYR_INCLUDE_TOOLCHAIN_GCC_H_

/**
 * @file
 * @brief GCC toolchain abstraction
 *
 * Macros to abstract compiler capabilities for GCC toolchain.
 */

/*
 * Older versions of GCC do not define __BYTE_ORDER__, so it must be manually
 * detected and defined using arch-specific definitions.
 */

#ifndef _LINKER

#ifndef __ORDER_BIG_ENDIAN__
#define __ORDER_BIG_ENDIAN__ (1)
#endif

#ifndef __ORDER_LITTLE_ENDIAN__
#define __ORDER_LITTLE_ENDIAN__ (2)
#endif

#ifndef __BYTE_ORDER__
#if defined(__BIG_ENDIAN__) || defined(__ARMEB__) ||  \
    defined(__THUMBEB__) || defined(__AARCH64EB__) || \
    defined(__MIPSEB__) || defined(__TC32EB__)

#define __BYTE_ORDER__ __ORDER_BIG_ENDIAN__

#elif defined(__LITTLE_ENDIAN__) || defined(__ARMEL__) || \
    defined(__THUMBEL__) || defined(__AARCH64EL__) ||     \
    defined(__MIPSEL__) || defined(__TC32EL__)

#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__

#else
#error "__BYTE_ORDER__ is not defined and cannot be automatically resolved"
#endif
#endif

/* C++11 has static_assert built in */
#ifdef __cplusplus
#define BUILD_ASSERT(EXPR)          static_assert(EXPR, "")
#define BUILD_ASSERT_MSG(EXPR, MSG) static_assert(EXPR, MSG)
/*
 * GCC 4.6 and higher have the C11 _Static_assert built in, and its
 * output is easier to understand than the common BUILD_ASSERT macros.
 */
#elif (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)) || \
    (__STDC_VERSION__) >= 201100
#define BUILD_ASSERT(EXPR)          _Static_assert(EXPR, "")
#define BUILD_ASSERT_MSG(EXPR, MSG) _Static_assert(EXPR, MSG)
#endif

#include 
#include 

#define ALIAS_OF(of) __attribute__((alias(#of)))

#define FUNC_ALIAS(real_func, new_alias, return_type) \
    return_type new_alias() ALIAS_OF(real_func)

#if defined(CONFIG_ARCH_POSIX)
#include 

/*let's not segfault if this were to happen for some reason*/
#define CODE_UNREACHABLE                                                    \
    {                                                                       \
        posix_print_error_and_exit("CODE_UNREACHABLE reached from %s:%d\n", \
                                   __FILE__, __LINE__);                     \
        __builtin_unreachable();                                            \
    }
#else
#define CODE_UNREACHABLE __builtin_unreachable()
#endif
#define FUNC_NORETURN __attribute__((__noreturn__))

/* The GNU assembler for Cortex-M3 uses # for immediate values, not
 * comments, so the @nobits# trick does not work.
 */
#if defined(CONFIG_ARM)
#define _NODATA_SECTION(segment) __attribute__((section(#segment)))
#else
#define _NODATA_SECTION(segment) \
    __attribute__((section(#segment ",\"wa\",@nobits#")))
#endif

/* Unaligned access */
#define UNALIGNED_GET(p)                     \
    __extension__({                          \
        struct __attribute__((__packed__)) { \
            __typeof__(*(p)) __v;            \
        } *__p = (__typeof__(__p))(p);       \
        __p->__v;                            \
    })

#if __GNUC__ >= 7 && defined(CONFIG_ARM)

/* Version of UNALIGNED_PUT() which issues a compiler_barrier() after
 * the store. It is required to workaround an apparent optimization
 * bug in GCC for ARM Cortex-M3 and higher targets, when multiple
 * byte, half-word and word stores (strb, strh, str instructions),
 * which support unaligned access, can be coalesced into store double
 * (strd) instruction, which doesn't support unaligned access (the
 * compilers in question do this optimization ignoring __packed__
 * attribute).
 */
#define UNALIGNED_PUT(v, p)                  \
    do {                                     \
        struct __attribute__((__packed__)) { \
            __typeof__(*p) __v;              \
        } *__p = (__typeof__(__p))(p);       \
        __p->__v = (v);                      \
        compiler_barrier();                  \
    } while (false)

#else

#define UNALIGNED_PUT(v, p)                  \
    do {                                     \
        struct __attribute__((__packed__)) { \
            __typeof__(*p) __v;              \
        } *__p = (__typeof__(__p))(p);       \
        __p->__v = (v);                      \
    } while (false)

#endif

/* Double indirection to ensure section names are expanded before
 * stringification
 */
#define __GENERIC_SECTION(segment) __attribute__((section(STRINGIFY(segment))))
#define Z_GENERIC_SECTION(segment) __GENERIC_SECTION(segment)

#define ___in_section(a, b, c) \
    __attribute__((section("." Z_STRINGIFY(a) "." Z_STRINGIFY(b) "." Z_STRINGIFY(c))))
#define __in_section(a, b, c) ___in_section(a, b, c)

#define __in_section_unique(seg) ___in_section(seg, __FILE__, __COUNTER__)

/* When using XIP, using '__ramfunc' places a function into RAM instead
 * of FLASH. Make sure '__ramfunc' is defined only when
 * CONFIG_ARCH_HAS_RAMFUNC_SUPPORT is defined, so that the compiler can
 * report an error if '__ramfunc' is used but the architecture does not
 * support it.
 */
#if !defined(CONFIG_XIP)
#define __ramfunc
#elif defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
#define __ramfunc __attribute__((noinline)) \
__attribute__((long_call, section(".ramfunc")))
#endif /* !CONFIG_XIP */

#ifndef __packed
#define __packed __attribute__((__packed__))
#endif
#ifndef __aligned
#define __aligned(x) __attribute__((__aligned__(x)))
#endif
#define __may_alias __attribute__((__may_alias__))
#ifndef __printf_like
#define __printf_like(f, a) __attribute__((format(printf, f, a)))
#endif
#define __used __attribute__((__used__))
#ifndef __deprecated
#define __deprecated __attribute__((deprecated))
#endif
#define ARG_UNUSED(x) (void)(x)

#ifndef likely
#define likely(x) __builtin_expect((bool)!!(x), true)
#endif
#ifndef unlikely
#define unlikely(x) __builtin_expect((bool)!!(x), false)
#endif

#define popcount(x) __builtin_popcount(x)

#ifndef __weak
#define __weak __attribute__((__weak__))
#endif
#define __unused __attribute__((__unused__))

/* Builtins with availability that depend on the compiler version. */
#if __GNUC__ >= 5
#define HAS_BUILTIN___builtin_add_overflow 1
#define HAS_BUILTIN___builtin_sub_overflow 1
#define HAS_BUILTIN___builtin_mul_overflow 1
#define HAS_BUILTIN___builtin_div_overflow 1
#endif
#if __GNUC__ >= 4
#define HAS_BUILTIN___builtin_clz   1
#define HAS_BUILTIN___builtin_clzl  1
#define HAS_BUILTIN___builtin_clzll 1
#define HAS_BUILTIN___builtin_ctz   1
#define HAS_BUILTIN___builtin_ctzl  1
#define HAS_BUILTIN___builtin_ctzll 1
#endif

/* Be *very* careful with this, you cannot filter out with -wno-deprecated,
 * which has implications for -Werror
 */
#define __DEPRECATED_MACRO _Pragma("GCC warning \"Macro is deprecated\"")

/* These macros allow having ARM asm functions callable from thumb */

#if defined(_ASMLANGUAGE)

#ifdef CONFIG_ARM

#if defined(CONFIG_ISA_THUMB2)

#define FUNC_CODE() .thumb;
#define FUNC_INSTR(a)

#elif defined(CONFIG_ISA_ARM)

#define FUNC_CODE() .code 32
#define FUNC_INSTR(a)

#else

#error unknown instruction set

#endif /* ISA */

#else

#define FUNC_CODE()
#define FUNC_INSTR(a)

#endif /* !CONFIG_ARM */

#endif /* _ASMLANGUAGE */

/*
 * These macros are used to declare assembly language symbols that need
 * to be typed properly(func or data) to be visible to the OMF tool.
 * So that the build tool could mark them as an entry point to be linked
 * correctly.  This is an elfism. Use #if 0 for a.out.
 */

#if defined(_ASMLANGUAGE)

#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || defined(CONFIG_XTENSA)
#define GTEXT(sym) \
    .global sym;   \
    .type sym, % function
#define GDATA(sym) \
    .global sym;   \
    .type sym, % object
#define WTEXT(sym) \
    .weak sym;     \
    .type sym, % function
#define WDATA(sym) \
    .weak sym;     \
    .type sym, % object
#elif defined(CONFIG_ARC)
/*
 * Need to use assembly macros because ';' is interpreted as the start of
 * a single line comment in the ARC assembler.
 */

.macro glbl_text symbol
    .globl \symbol
    .type \symbol,
    % function
            .endm

            .macro glbl_data symbol
            .globl \symbol
            .type \symbol,
    % object
            .endm

            .macro weak_data symbol
            .weak \symbol
            .type \symbol,
    % object
            .endm

#define GTEXT(sym) glbl_text sym
#define GDATA(sym) glbl_data sym
#define WDATA(sym) weak_data sym

#else /* !CONFIG_ARM && !CONFIG_ARC */
#define GTEXT(sym) \
    .globl sym;    \
    .type sym, @function
#define GDATA(sym) \
    .globl sym;    \
    .type sym, @object
#endif

/*
 * These macros specify the section in which a given function or variable
 * resides.
 *
 * - SECTION_FUNC	allows only one function to reside in a sub-section
 * - SECTION_SUBSEC_FUNC allows multiple functions to reside in a sub-section
 *   This ensures that garbage collection only discards the section
 *   if all functions in the sub-section are not referenced.
 */

#if defined(CONFIG_ARC)
/*
 * Need to use assembly macros because ';' is interpreted as the start of
 * a single line comment in the ARC assembler.
 *
 * Also, '\()' is needed in the .section directive of these macros for
 * correct substitution of the 'section' variable.
 */

.macro section_var section, symbol.section.\section\().\symbol
	\symbol :.endm

               .macro section_func section,
    symbol
        .section.\section\()
        .\symbol,
    "ax" FUNC_CODE()
        PERFOPT_ALIGN
	\symbol : FUNC_INSTR(\symbol)
                .endm

                .macro section_subsec_func section,
    subsection, symbol.section.\section\().\subsection, "ax" PERFOPT_ALIGN
	\symbol :.endm

#define SECTION_VAR(sect, sym)  section_var sect, sym
#define SECTION_FUNC(sect, sym) section_func sect, sym
#define SECTION_SUBSEC_FUNC(sect, subsec, sym) \
    section_subsec_func sect, subsec, sym
#else /* !CONFIG_ARC */

#define SECTION_VAR(sect, sym) \
    .section.sect.##sym;       \
    sym:
#define SECTION_FUNC(sect, sym) \
    .section.sect.sym, "ax";    \
    FUNC_CODE()                 \
    PERFOPT_ALIGN;              \
    sym:                        \
    FUNC_INSTR(sym)
#define SECTION_SUBSEC_FUNC(sect, subsec, sym) \
    .section.sect.subsec, "ax";                \
    PERFOPT_ALIGN;                             \
    sym:

#endif /* CONFIG_ARC */

#endif /* _ASMLANGUAGE */

#if defined(CONFIG_ARM) && defined(_ASMLANGUAGE)
#if defined(CONFIG_ISA_THUMB2)
/* '.syntax unified' is a gcc-ism used in thumb-2 asm files */
#define _ASM_FILE_PROLOGUE \
    .text;                 \
    .syntax unified;       \
    .thumb
#else
#define _ASM_FILE_PROLOGUE \
    .text;                 \
    .code 32
#endif
#endif

/*
 * These macros generate absolute symbols for GCC
 */

/* create an extern reference to the absolute symbol */

#define GEN_OFFSET_EXTERN(name) extern const char name[]

#define GEN_ABS_SYM_BEGIN(name) \
    EXTERN_C void name(void);   \
    void name(void)             \
    {
#define GEN_ABS_SYM_END }

#if defined(CONFIG_ARM)

/*
 * GNU/ARM backend does not have a proper operand modifier which does not
 * produces prefix # followed by value, such as %0 for PowerPC, Intel, and
 * MIPS. The workaround performed here is using %B0 which converts
 * the value to ~(value). Thus "n"(~(value)) is set in operand constraint
 * to output (value) in the ARM specific GEN_OFFSET macro.
 */

#define GEN_ABSOLUTE_SYM(name, value)           \
    __asm__(".globl\t" #name "\n\t.equ\t" #name \
            ",%B0"                              \
            "\n\t.type\t" #name ",%%object"     \
            :                                   \
            : "n"(~(value)))

#elif defined(CONFIG_X86) || defined(CONFIG_ARC)

#define GEN_ABSOLUTE_SYM(name, value)           \
    __asm__(".globl\t" #name "\n\t.equ\t" #name \
            ",%c0"                              \
            "\n\t.type\t" #name ",@object"      \
            :                                   \
            : "n"(value))

#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || defined(CONFIG_XTENSA)

/* No special prefixes necessary for constants in this arch AFAICT */
#define GEN_ABSOLUTE_SYM(name, value)           \
    __asm__(".globl\t" #name "\n\t.equ\t" #name \
            ",%0"                               \
            "\n\t.type\t" #name ",%%object"     \
            :                                   \
            : "n"(value))

#elif defined(CONFIG_ARCH_POSIX)
#define GEN_ABSOLUTE_SYM(name, value)           \
    __asm__(".globl\t" #name "\n\t.equ\t" #name \
            ",%c0"                              \
            "\n\t.type\t" #name ",@object"      \
            :                                   \
            : "n"(value))
#else
#error processor architecture not supported
#endif

#define compiler_barrier()                    \
    do {                                      \
        __asm__ __volatile__("" ::            \
                                 : "memory"); \
    } while (false)

/** @brief Return larger value of two provided expressions.
 *
 * Macro ensures that expressions are evaluated only once.
 *
 * @note Macro has limited usage compared to the standard macro as it cannot be
 *	 used:
 *	 - to generate constant integer, e.g. __aligned(Z_MAX(4,5))
 *	 - static variable, e.g. array like static u8_t array[Z_MAX(...)];
 */
#define Z_MAX(a, b) ({                             \
    /* random suffix to avoid naming conflict */   \
    __typeof__(a) _value_a_ = (a);                 \
    __typeof__(b) _value_b_ = (b);                 \
    _value_a_ > _value_b_ ? _value_a_ : _value_b_; \
})

/** @brief Return smaller value of two provided expressions.
 *
 * Macro ensures that expressions are evaluated only once. See @ref Z_MAX for
 * macro limitations.
 */
#define Z_MIN(a, b) ({                             \
    /* random suffix to avoid naming conflict */   \
    __typeof__(a) _value_a_ = (a);                 \
    __typeof__(b) _value_b_ = (b);                 \
    _value_a_ < _value_b_ ? _value_a_ : _value_b_; \
})

#endif /* !_LINKER */
#endif /* ZEPHYR_INCLUDE_TOOLCHAIN_GCC_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/toolchain/xcc.h
================================================
/*
 * Copyright (c) 2017 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_XCC_H_
#define ZEPHYR_INCLUDE_TOOLCHAIN_XCC_H_

/* toolchain/gcc.h errors out if __BYTE_ORDER__ cannot be determined
 * there. However, __BYTE_ORDER__ is actually being defined later in
 * this file. So define __BYTE_ORDER__ to skip the check in gcc.h
 * and undefine after including gcc.h.
 */
#define __BYTE_ORDER__
#include 
#undef __BYTE_ORDER__

#include 

/* XCC doesn't support __COUNTER__ but this should be good enough */
#define __COUNTER__ __LINE__

#undef __in_section_unique
#define __in_section_unique(seg) \
    __attribute__((section("." STRINGIFY(seg) "." STRINGIFY(__COUNTER__))))

#ifndef __GCC_LINKER_CMD__
#include 

/*
 * XCC does not define the following macros with the expected names, but the
 * HAL defines similar ones. Thus we include it and define the missing macros
 * ourselves.
 */
#if XCHAL_MEMORY_ORDER == XTHAL_BIGENDIAN
#define __BYTE_ORDER__ __ORDER_BIG_ENDIAN__
#elif XCHAL_MEMORY_ORDER == XTHAL_LITTLEENDIAN
#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
#else
#error "Cannot determine __BYTE_ORDER__"
#endif

#endif /* __GCC_LINKER_CMD__ */

#define __builtin_unreachable()              \
    do {                                     \
        __ASSERT(false, "Unreachable code"); \
    } while (true)

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/toolchain.h
================================================
/*
 * Copyright (c) 2010-2014, Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Macros to abstract toolchain specific capabilities
 *
 * This file contains various macros to abstract compiler capabilities that
 * utilize toolchain specific attributes and/or pragmas.
 */

#ifndef _TOOLCHAIN_H
#define _TOOLCHAIN_H

#if defined(__XCC__)
#include 
#elif defined(__GNUC__) || (defined(_LINKER) && defined(__GCC_LINKER_CMD__))
#include 
#else
#include 
#endif

#endif /* _TOOLCHAIN_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/work_q.h
================================================
#ifndef WORK_Q_H
#define WORK_Q_H
#include "atomic.h"
#include "zephyr.h"

#if defined(BFLB_BLE)
struct k_work_q {
    struct k_fifo fifo;
};

typedef struct {
    bl_timer_t timer;
    struct k_delayed_work *delay_work;
} timer_rec_d;

int k_work_q_start();

enum {
    K_WORK_STATE_PENDING,
    K_WORK_STATE_PERIODIC,
};
struct k_work;
/* work define*/
typedef void (*k_work_handler_t)(struct k_work *work);
struct k_work {
    void *_reserved;
    k_work_handler_t handler;
    atomic_t flags[1];
};

#define _K_WORK_INITIALIZER(work_handler) \
    {                                     \
        ._reserved = NULL,                \
        .handler = work_handler,          \
        .flags = { 0 }                    \
    }

#define K_WORK_INITIALIZER __DEPRECATED_MACRO _K_WORK_INITIALIZER

int k_work_init(struct k_work *work, k_work_handler_t handler);
void k_work_submit(struct k_work *work);

/*delay work define*/
struct k_delayed_work {
    struct k_work work;
    struct k_work_q *work_q;
    k_timer_t timer;
};

void k_delayed_work_init(struct k_delayed_work *work, k_work_handler_t handler);
int k_delayed_work_submit(struct k_delayed_work *work, uint32_t delay);
/* Added by bouffalolab */
int k_delayed_work_submit_periodic(struct k_delayed_work *work, s32_t period);
int k_delayed_work_cancel(struct k_delayed_work *work);
s32_t k_delayed_work_remaining_get(struct k_delayed_work *work);
void k_delayed_work_del_timer(struct k_delayed_work *work);
/* Added by bouffalolab */
int k_delayed_work_free(struct k_delayed_work *work);
#endif
#endif /* WORK_Q_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/include/zephyr/types.h
================================================
/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __Z_TYPES_H__
#define __Z_TYPES_H__

#include 

#ifdef __cplusplus
extern "C" {
#endif

typedef signed char s8_t;
typedef signed short s16_t;
typedef int32_t s32_t;
typedef signed long long s64_t;

typedef unsigned char u8_t;
typedef unsigned short u16_t;
typedef uint32_t u32_t;
typedef unsigned long long u64_t;

#ifdef __cplusplus
}
#endif

#endif /* __Z_TYPES_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/log.c
================================================
/* log.c - logging helpers */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Helper for printk parameters to convert from binary to hex.
 * We declare multiple buffers so the helper can be used multiple times
 * in a single printk call.
 */

#include 
#include 
#include 
#include 
#include 
#include 

const char *bt_hex_real(const void *buf, size_t len) {
  static const char hex[] = "0123456789abcdef";
#if defined(CONFIG_BT_DEBUG_MONITOR)
  static char str[512];
#else
  static char str[128];
#endif
  const u8_t *b = buf;
  int         i;

  len = MIN(len, (sizeof(str) - 1) / 2);

  for (i = 0; i < len; i++) {
    str[i * 2]     = hex[b[i] >> 4];
    str[i * 2 + 1] = hex[b[i] & 0xf];
  }

  str[i * 2] = '\0';

  return str;
}

const char *bt_addr_str_real(const bt_addr_t *addr) {
  static char str[BT_ADDR_STR_LEN];

  bt_addr_to_str(addr, str, sizeof(str));

  return str;
}

const char *bt_addr_le_str_real(const bt_addr_le_t *addr) {
  static char str[BT_ADDR_LE_STR_LEN];

  bt_addr_le_to_str(addr, str, sizeof(str));

  return str;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/log.h
================================================
/** @file
 *  @brief Bluetooth subsystem logging helpers.
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef __BT_LOG_H
#define __BT_LOG_H

#if defined(BL_MCU_SDK)
#include "bflb_platform.h"
#endif

#include 

#include 
#include 

#include "FreeRTOS.h"
#include "FreeRTOSConfig.h"
#include "task.h"

#ifdef __cplusplus
extern "C" {
#endif

#if !defined(BT_DBG_ENABLED)
#define BT_DBG_ENABLED 1
#endif

#if BT_DBG_ENABLED
#define LOG_LEVEL LOG_LEVEL_DBG
#else
#define LOG_LEVEL CONFIG_BT_LOG_LEVEL
#endif

// LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);

#if defined(BFLB_BLE)

#if defined(BL_MCU_SDK)
#define BT_DBG(fmt, ...)  // bflb_platform_printf(fmt", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_ERR(fmt, ...)  bflb_platform_printf(fmt ", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_WARN(fmt, ...) bflb_platform_printf(fmt ", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_INFO(fmt, ...) // bflb_platform_printf(fmt", %s\r\n", ##__VA_ARGS__, __func__)
#else
#define BT_DBG(fmt, ...)  // printf(fmt", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_ERR(fmt, ...)  printf(fmt ", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_WARN(fmt, ...) printf(fmt ", %s\r\n", ##__VA_ARGS__, __func__)
#define BT_INFO(fmt, ...) // printf(fmt", %s\r\n", ##__VA_ARGS__, __func__)
#endif

#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_BT_MESH_PTS)
#if defined(BL_MCU_SDK)
#define BT_PTS(fmt, ...) bflb_platform_printf(fmt "\r\n", ##__VA_ARGS__)
#else
#define BT_PTS(fmt, ...) printf(fmt "\r\n", ##__VA_ARGS__)
#endif
#endif

#else /*BFLB_BLE*/

#define BT_DBG(fmt, ...)  LOG_DBG(fmt, ##__VA_ARGS__)
#define BT_ERR(fmt, ...)  LOG_ERR(fmt, ##__VA_ARGS__)
#define BT_WARN(fmt, ...) LOG_WRN(fmt, ##__VA_ARGS__)
#define BT_INFO(fmt, ...) LOG_INF(fmt, ##__VA_ARGS__)

#if defined(CONFIG_BT_ASSERT_VERBOSE)
#define BT_ASSERT_PRINT(fmt, ...) printk(fmt, ##__VA_ARGS__)
#else
#define BT_ASSERT_PRINT(fmt, ...)
#endif /* CONFIG_BT_ASSERT_VERBOSE */

#if defined(CONFIG_BT_ASSERT_PANIC)
#define BT_ASSERT_DIE k_panic
#else
#define BT_ASSERT_DIE k_oops
#endif /* CONFIG_BT_ASSERT_PANIC */

#endif /*BFLB_BLE*/

#if defined(CONFIG_BT_ASSERT)
#if defined(BFLB_BLE)
extern void user_vAssertCalled(void);
#define BT_ASSERT(cond)                                                                                                                                                                                \
  if ((cond) == 0)                                                                                                                                                                                     \
  user_vAssertCalled()
#else
#define BT_ASSERT(cond)                                                                                                                                                                                \
  if (!(cond)) {                                                                                                                                                                                       \
    BT_ASSERT_PRINT("assert: '" #cond "' failed\n");                                                                                                                                                   \
    BT_ASSERT_DIE();                                                                                                                                                                                   \
  }
#endif /*BFLB_BLE*/
#else
#if defined(BFLB_BLE)
#define BT_ASSERT(cond)
#else
#define BT_ASSERT(cond) __ASSERT_NO_MSG(cond)
#endif /*BFLB_BLE*/
#endif /* CONFIG_BT_ASSERT*/

#define BT_HEXDUMP_DBG(_data, _length, _str) LOG_HEXDUMP_DBG((const u8_t *)_data, _length, _str)

#if defined(BFLB_BLE)
static inline char *log_strdup(const char *str) { return (char *)str; }
#endif

/* NOTE: These helper functions always encodes into the same buffer storage.
 * It is the responsibility of the user of this function to copy the information
 * in this string if needed.
 */
const char *bt_hex_real(const void *buf, size_t len);
const char *bt_addr_str_real(const bt_addr_t *addr);
const char *bt_addr_le_str_real(const bt_addr_le_t *addr);

/* NOTE: log_strdup does not guarantee a duplication of the string.
 * It is therefore still the responsibility of the user to handle the
 * restrictions in the underlying function call.
 */
#define bt_hex(buf, len)     log_strdup(bt_hex_real(buf, len))
#define bt_addr_str(addr)    log_strdup(bt_addr_str_real(addr))
#define bt_addr_le_str(addr) log_strdup(bt_addr_le_str_real(addr))

#ifdef __cplusplus
}
#endif

#endif /* __BT_LOG_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/poll.c
================================================
/*
 * Copyright (c) 2017 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 *
 * @brief Kernel asynchronous event polling interface.
 *
 * This polling mechanism allows waiting on multiple events concurrently,
 * either events triggered directly, or from kernel objects or other kernel
 * constructs.
 */

#include 

#include 
#include 
#include 
#include 
#include 

struct k_sem g_poll_sem;

void k_poll_event_init(struct k_poll_event *event, u32_t type, int mode, void *obj) {
  __ASSERT(mode == K_POLL_MODE_NOTIFY_ONLY, "only NOTIFY_ONLY mode is supported\n");
  __ASSERT(type < (1 << _POLL_NUM_TYPES), "invalid type\n");
  __ASSERT(obj, "must provide an object\n");

  event->poller = NULL;
  /* event->tag is left uninitialized: the user will set it if needed */
  event->type   = type;
  event->state  = K_POLL_STATE_NOT_READY;
  event->mode   = mode;
  event->unused = 0;
  event->obj    = obj;
}

/* must be called with interrupts locked */
static inline int is_condition_met(struct k_poll_event *event, u32_t *state) {
  switch (event->type) {
  case K_POLL_TYPE_SEM_AVAILABLE:
    if (k_sem_count_get(event->sem) > 0) {
      *state = K_POLL_STATE_SEM_AVAILABLE;
      return 1;
    }
    break;
  case K_POLL_TYPE_DATA_AVAILABLE:
    if (!k_queue_is_empty(event->queue)) {
      *state = K_POLL_STATE_FIFO_DATA_AVAILABLE;
      return 1;
    }
    break;
  case K_POLL_TYPE_SIGNAL:
    if (event->signal->signaled) {
      *state = K_POLL_STATE_SIGNALED;
      return 1;
    }
    break;
  case K_POLL_TYPE_IGNORE:
    return 0;
  default:
    __ASSERT(0, "invalid event type (0x%x)\n", event->type);
    break;
  }

  return 0;
}

static inline void add_event(sys_dlist_t *events, struct k_poll_event *event, struct _poller *poller) { sys_dlist_append(events, &event->_node); }

/* must be called with interrupts locked */
static inline int register_event(struct k_poll_event *event, struct _poller *poller) {
  switch (event->type) {
  case K_POLL_TYPE_SEM_AVAILABLE:
    __ASSERT(event->sem, "invalid semaphore\n");
    add_event(&event->sem->poll_events, event, poller);
    break;
  case K_POLL_TYPE_DATA_AVAILABLE:
    __ASSERT(event->queue, "invalid queue\n");
    add_event(&event->queue->poll_events, event, poller);
    break;
  case K_POLL_TYPE_SIGNAL:
    __ASSERT(event->signal, "invalid poll signal\n");
    add_event(&event->signal->poll_events, event, poller);
    break;
  case K_POLL_TYPE_IGNORE:
    /* nothing to do */
    break;
  default:
    __ASSERT(0, "invalid event type\n");
    break;
  }

  event->poller = poller;

  return 0;
}

/* must be called with interrupts locked */
static inline void clear_event_registration(struct k_poll_event *event) {
  event->poller = NULL;

  switch (event->type) {
  case K_POLL_TYPE_SEM_AVAILABLE:
    __ASSERT(event->sem, "invalid semaphore\n");
    sys_dlist_remove(&event->_node);
    break;
  case K_POLL_TYPE_DATA_AVAILABLE:
    __ASSERT(event->queue, "invalid queue\n");
    sys_dlist_remove(&event->_node);
    break;
  case K_POLL_TYPE_SIGNAL:
    __ASSERT(event->signal, "invalid poll signal\n");
    sys_dlist_remove(&event->_node);
    break;
  case K_POLL_TYPE_IGNORE:
    /* nothing to do */
    break;
  default:
    __ASSERT(0, "invalid event type\n");
    break;
  }
}

/* must be called with interrupts locked */
static inline void clear_event_registrations(struct k_poll_event *events, int last_registered, unsigned int key) {
  for (; last_registered >= 0; last_registered--) {
    clear_event_registration(&events[last_registered]);
    irq_unlock(key);
    key = irq_lock();
  }
}

static inline void set_event_ready(struct k_poll_event *event, u32_t state) {
  event->poller = NULL;
  event->state |= state;
}

#if (BFLB_BT_CO_THREAD)
static bool polling_events(struct k_poll_event *events, int num_events, int total_evt_array_cnt, s32_t timeout, int *last_registered)
#else
static bool polling_events(struct k_poll_event *events, int num_events, s32_t timeout, int *last_registered)
#endif
{
  int          rc;
  bool         polling = true;
  unsigned int key;

#if (BFLB_BT_CO_THREAD)
  for (int ii = 0; ii < total_evt_array_cnt; ii++) {
    if (ii >= num_events && ii != total_evt_array_cnt - 1)
      continue;
#else
  for (int ii = 0; ii < num_events; ii++) {
#endif
    u32_t state;
    key = irq_lock();
    if (is_condition_met(&events[ii], &state)) {
      set_event_ready(&events[ii], state);
      polling = false;
    } else if (timeout != K_NO_WAIT && polling) {
      rc = register_event(&events[ii], NULL);
      if (rc == 0) {
        ++(*last_registered);
      } else {
        __ASSERT(0, "unexpected return code\n");
      }
    }
    irq_unlock(key);
  }
  return polling;
}

#if (BFLB_BT_CO_THREAD)
int k_poll(struct k_poll_event *events, int num_events, int total_evt_array_cnt, s32_t timeout, u8_t *to_process)
#else
int k_poll(struct k_poll_event *events, int num_events, s32_t timeout)
#endif
{
  __ASSERT(events, "NULL events\n");
  __ASSERT(num_events > 0, "zero events\n");

  int          last_registered = -1;
  unsigned int key;
  bool         polling = true;

  /* find events whose condition is already fulfilled */
#if (BFLB_BT_CO_THREAD)
  polling = polling_events(events, num_events, total_evt_array_cnt, timeout, &last_registered);
#else
  polling = polling_events(events, num_events, timeout, &last_registered);
#endif

  if (polling == false) {
    goto exit;
  }
#if (BFLB_BT_CO_THREAD)
  if (timeout != K_NO_WAIT)
#endif
  {
    k_sem_take(&g_poll_sem, timeout);
    last_registered = -1;
#if (BFLB_BT_CO_THREAD)
    polling = polling_events(events, num_events, total_evt_array_cnt, timeout, &last_registered);
#else
    polling_events(events, num_events, timeout, &last_registered);
#endif
  }

#if (BFLB_BT_CO_THREAD)
  if (to_process)
    *to_process = polling ? 0 : 1;
#endif
exit:
  key = irq_lock();
  clear_event_registrations(events, last_registered, key);
  irq_unlock(key);
  return 0;
}

/* must be called with interrupts locked */
static int _signal_poll_event(struct k_poll_event *event, u32_t state, int *must_reschedule) {
  *must_reschedule = 0;
  set_event_ready(event, state);
  return 0;
}

int k_poll_signal_raise(struct k_poll_signal *signal, int result) {
  unsigned int         key = irq_lock();
  struct k_poll_event *poll_event;
  int                  must_reschedule;

  signal->result   = result;
  signal->signaled = 1;

  poll_event = (struct k_poll_event *)sys_dlist_get(&signal->poll_events);
  if (!poll_event) {
    irq_unlock(key);
    return 0;
  }

  int rc = _signal_poll_event(poll_event, K_POLL_STATE_SIGNALED, &must_reschedule);

  k_sem_give(&g_poll_sem);
  irq_unlock(key);
  return rc;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/rpa.c
================================================
/**
 * @file rpa.c
 * Resolvable Private Address Generation and Resolution
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

#include <../include/bluetooth/crypto.h>
#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_RPA)
#define LOG_MODULE_NAME bt_rpa
#include "log.h"

#if defined(CONFIG_BT_CTLR_PRIVACY) || defined(CONFIG_BT_PRIVACY) || defined(CONFIG_BT_SMP)
static int ah(const u8_t irk[16], const u8_t r[3], u8_t out[3]) {
  u8_t res[16];
  int  err;

  BT_DBG("irk %s", bt_hex(irk, 16));
  BT_DBG("r %s", bt_hex(r, 3));

  /* r' = padding || r */
  memcpy(res, r, 3);
  (void)memset(res + 3, 0, 13);

  err = bt_encrypt_le(irk, res, res);
  if (err) {
    return err;
  }

  /* The output of the random address function ah is:
   *      ah(h, r) = e(k, r') mod 2^24
   * The output of the security function e is then truncated to 24 bits
   * by taking the least significant 24 bits of the output of e as the
   * result of ah.
   */
  memcpy(out, res, 3);

  return 0;
}
#endif

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CTLR_PRIVACY)
bool bt_rpa_irk_matches(const u8_t irk[16], const bt_addr_t *addr) {
  u8_t hash[3];
  int  err;

  BT_DBG("IRK %s bdaddr %s", bt_hex(irk, 16), bt_addr_str(addr));

  err = ah(irk, addr->val + 3, hash);
  if (err) {
    return false;
  }

  return !memcmp(addr->val, hash, 3);
}
#endif

#if defined(CONFIG_BT_PRIVACY) || defined(CONFIG_BT_CTLR_PRIVACY)
int bt_rpa_create(const u8_t irk[16], bt_addr_t *rpa) {
  int err;

  err = bt_rand(rpa->val + 3, 3);
  if (err) {
    return err;
  }

  BT_ADDR_SET_RPA(rpa);

  err = ah(irk, rpa->val + 3, rpa->val);
  if (err) {
    return err;
  }

  BT_DBG("Created RPA %s", bt_addr_str((bt_addr_t *)rpa->val));

  return 0;
}
#else
int bt_rpa_create(const u8_t irk[16], bt_addr_t *rpa) { return -ENOTSUP; }
#endif /* CONFIG_BT_PRIVACY */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/rpa.h
================================================
/* rpa.h - Bluetooth Resolvable Private Addresses (RPA) generation and
 * resolution
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "bluetooth.h"
#include "hci_host.h"

bool bt_rpa_irk_matches(const u8_t irk[16], const bt_addr_t *addr);
int  bt_rpa_create(const u8_t irk[16], bt_addr_t *rpa);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/Kconfig
================================================
# Kconfig - Cryptography primitive options for TinyCrypt version 2.0

#
# Copyright (c) 2015 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#

config TINYCRYPT
	bool
	prompt "TinyCrypt Support"
	default n
	help
	This option enables the TinyCrypt cryptography library.

config TINYCRYPT_CTR_PRNG
	bool
	prompt "PRNG in counter mode"
	depends on TINYCRYPT
	default n
	help
	This option enables support for the pseudo-random number
	generator in counter mode.

config TINYCRYPT_SHA256
	bool
	prompt "SHA-256 Hash function support"
	depends on TINYCRYPT
	default n
	help
	This option enables support for SHA-256
	hash function primitive.

config TINYCRYPT_SHA256_HMAC
	bool
	prompt "HMAC (via SHA256) message auth support"
	depends on TINYCRYPT_SHA256
	default n
	help
	This option enables support for HMAC using SHA-256
	message authentication code.

config TINYCRYPT_SHA256_HMAC_PRNG
	bool
	prompt "PRNG (via HMAC-SHA256) support"
	depends on TINYCRYPT_SHA256_HMAC
	default n
	help
	This option enables support for pseudo-random number
	generator.

config TINYCRYPT_ECC_DH
	bool
	prompt "ECC_DH anonymous key agreement protocol"
	depends on TINYCRYPT
	select ENTROPY_GENERATOR
	default n
	help
	This option enables support for the Elliptic curve
	Diffie-Hellman anonymous key agreement protocol.

	Enabling ECC requires a cryptographically secure random number
	generator.

config TINYCRYPT_ECC_DSA
	bool
	prompt "ECC_DSA digital signature algorithm"
	depends on TINYCRYPT
	select ENTROPY_GENERATOR
	default n
	help
	This option enables support for the Elliptic Curve Digital
	Signature Algorithm (ECDSA).

	Enabling ECC requires a cryptographically secure random number
	generator.

config TINYCRYPT_AES
	bool
	prompt "AES-128 decrypt/encrypt"
	depends on TINYCRYPT
	default n
	help
	This option enables support for AES-128 decrypt and encrypt.

config TINYCRYPT_AES_CBC
	bool
	prompt "AES-128 block cipher"
	depends on TINYCRYPT_AES
	default n
	help
	This option enables support for AES-128 block cipher mode.

config TINYCRYPT_AES_CTR
	bool
	prompt "AES-128 counter mode"
	depends on TINYCRYPT_AES
	default n
	help
	This option enables support for AES-128 counter mode.

config TINYCRYPT_AES_CCM
	bool
	prompt "AES-128 CCM mode"
	depends on TINYCRYPT_AES
	default n
	help
	This option enables support for AES-128 CCM mode.

config TINYCRYPT_AES_CMAC
	bool
	prompt "AES-128 CMAC mode"
	depends on TINYCRYPT_AES
	default n
	help
	This option enables support for AES-128 CMAC mode.


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/README
================================================
The TinyCrypt library in Zephyr is a downstream of an externally maintained
open source project.  The original upstream code can be found at:

https://github.com/01org/tinycrypt

At revision c214460d7f760e2a75908cb41000afcc0bfca282, version 0.2.7

Any changes to the local version should include Zephyr's TinyCrypt
maintainer in the review.  That can be found via the git history.

The following is the license information for this code:

================================================================================

                     TinyCrypt Cryptographic Library

================================================================================

          Copyright (c) 2017, Intel Corporation. All rights reserved.         

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

  - Redistributions of source code must retain the above copyright notice, this 
      list of conditions and the following disclaimer.
      
  - Redistributions in binary form must reproduce the above copyright notice, 
      this list of conditions and the following disclaimer in the documentation 
      and/or other materials provided with the distribution.
      
  - Neither the name of the Intel Corporation nor the names of its contributors 
      may be used to endorse or promote products derived from this software 
      without specific prior written permission. 


THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

================================================================================

Copyright (c) 2013, Kenneth MacKay
All rights reserved.

https://github.com/kmackay/micro-ecc

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
 * Redistributions of source code must retain the above copyright notice, this
   list of conditions and the following disclaimer.
 * Redistributions in binary form must reproduce the above copyright notice,
   this list of conditions and the following disclaimer in the documentation
   and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/aes.h
================================================
/* aes.h - TinyCrypt interface to an AES-128 implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief -- Interface to an AES-128 implementation.
 *
 *  Overview:   AES-128 is a NIST approved block cipher specified in
 *              FIPS 197. Block ciphers are deterministic algorithms that
 *              perform a transformation specified by a symmetric key in fixed-
 *              length data sets, also called blocks.
 *
 *  Security:   AES-128 provides approximately 128 bits of security.
 *
 *  Usage:      1) call tc_aes128_set_encrypt/decrypt_key to set the key.
 *
 *              2) call tc_aes_encrypt/decrypt to process the data.
 */

#ifndef __TC_AES_H__
#define __TC_AES_H__

#include 

#ifdef __cplusplus
extern "C" {
#endif

#define Nb                (4)  /* number of columns (32-bit words) comprising the state */
#define Nk                (4)  /* number of 32-bit words comprising the key */
#define Nr                (10) /* number of rounds */
#define TC_AES_BLOCK_SIZE (Nb * Nk)
#define TC_AES_KEY_SIZE   (Nb * Nk)

typedef struct tc_aes_key_sched_struct {
    unsigned int words[Nb * (Nr + 1)];
} * TCAesKeySched_t;

/**
 *  @brief Set AES-128 encryption key
 *  Uses key k to initialize s
 *  @return  returns TC_CRYPTO_SUCCESS (1)
 *           returns TC_CRYPTO_FAIL (0) if: s == NULL or k == NULL
 *  @note       This implementation skips the additional steps required for keys
 *              larger than 128 bits, and must not be used for AES-192 or
 *              AES-256 key schedule -- see FIPS 197 for details
 *  @param      s IN/OUT -- initialized struct tc_aes_key_sched_struct
 *  @param      k IN -- points to the AES key
 */
int tc_aes128_set_encrypt_key(TCAesKeySched_t s, const uint8_t *k);

/**
 *  @brief AES-128 Encryption procedure
 *  Encrypts contents of in buffer into out buffer under key;
 *              schedule s
 *  @note Assumes s was initialized by aes_set_encrypt_key;
 *              out and in point to 16 byte buffers
 *  @return  returns TC_CRYPTO_SUCCESS (1)
 *           returns TC_CRYPTO_FAIL (0) if: out == NULL or in == NULL or s == NULL
 *  @param out IN/OUT -- buffer to receive ciphertext block
 *  @param in IN -- a plaintext block to encrypt
 *  @param s IN -- initialized AES key schedule
 */
int tc_aes_encrypt(uint8_t *out, const uint8_t *in,
                   const TCAesKeySched_t s);

/**
 *  @brief Set the AES-128 decryption key
 *  Uses key k to initialize s
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if: s == NULL or k == NULL
 *  @note       This is the implementation of the straightforward inverse cipher
 *              using the cipher documented in FIPS-197 figure 12, not the
 *              equivalent inverse cipher presented in Figure 15
 *  @warning    This routine skips the additional steps required for keys larger
 *              than 128, and must not be used for AES-192 or AES-256 key
 *              schedule -- see FIPS 197 for details
 *  @param s  IN/OUT -- initialized struct tc_aes_key_sched_struct
 *  @param k  IN -- points to the AES key
 */
int tc_aes128_set_decrypt_key(TCAesKeySched_t s, const uint8_t *k);

/**
 *  @brief AES-128 Encryption procedure
 *  Decrypts in buffer into out buffer under key schedule s
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if: out is NULL or in is NULL or s is NULL
 *  @note   Assumes s was initialized by aes_set_encrypt_key
 *          out and in point to 16 byte buffers
 *  @param out IN/OUT -- buffer to receive ciphertext block
 *  @param in IN -- a plaintext block to encrypt
 *  @param s IN -- initialized AES key schedule
 */
int tc_aes_decrypt(uint8_t *out, const uint8_t *in,
                   const TCAesKeySched_t s);

#ifdef __cplusplus
}
#endif

#endif /* __TC_AES_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/cbc_mode.h
================================================
/* cbc_mode.h - TinyCrypt interface to a CBC mode implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to a CBC mode implementation.
 *
 *  Overview: CBC (for "cipher block chaining") mode is a NIST approved mode of
 *            operation defined in SP 800-38a. It can be used with any block
 *            cipher to provide confidentiality of strings whose lengths are
 *            multiples of the block_size of the underlying block cipher.
 *            TinyCrypt hard codes AES as the block cipher.
 *
 *  Security: CBC mode provides data confidentiality given that the maximum
 *            number q of blocks encrypted under a single key satisfies
 *            q < 2^63, which is not a practical constraint (it is considered a
 *            good practice to replace the encryption when q == 2^56). CBC mode
 *            provides NO data integrity.
 *
 *            CBC mode assumes that the IV value input into the
 *            tc_cbc_mode_encrypt is randomly generated. The TinyCrypt library
 *            provides HMAC-PRNG module, which generates suitable IVs. Other
 *            methods for generating IVs are acceptable, provided that the
 *            values of the IVs generated appear random to any adversary,
 *            including someone with complete knowledge of the system design.
 *
 *            The randomness property on which CBC mode's security depends is
 *            the unpredictability of the IV. Since it is unpredictable, this
 *            means in practice that CBC mode requires that the IV is stored
 *            somehow with the ciphertext in order to recover the plaintext.
 *
 *            TinyCrypt CBC encryption prepends the IV to the ciphertext,
 *            because this affords a more efficient (few buffers) decryption.
 *            Hence tc_cbc_mode_encrypt assumes the ciphertext buffer is always
 *            16 bytes larger than the plaintext buffer.
 *
 *  Requires: AES-128
 *
 *  Usage:    1) call tc_cbc_mode_encrypt to encrypt data.
 *
 *            2) call tc_cbc_mode_decrypt to decrypt data.
 *
 */

#ifndef __TC_CBC_MODE_H__
#define __TC_CBC_MODE_H__

#include "aes.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 *  @brief CBC encryption procedure
 *  CBC encrypts inlen bytes of the in buffer into the out buffer
 *  using the encryption key schedule provided, prepends iv to out
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL or
 *                in == NULL or
 *                ctr == NULL or
 *                sched == NULL or
 *                inlen == 0 or
 *                (inlen % TC_AES_BLOCK_SIZE) != 0 or
 *                (outlen % TC_AES_BLOCK_SIZE) != 0 or
 *                outlen != inlen + TC_AES_BLOCK_SIZE
 *  @note Assumes: - sched has been configured by aes_set_encrypt_key
 *              - iv contains a 16 byte random string
 *              - out buffer is large enough to hold the ciphertext + iv
 *              - out buffer is a contiguous buffer
 *              - in holds the plaintext and is a contiguous buffer
 *              - inlen gives the number of bytes in the in buffer
 *  @param out IN/OUT -- buffer to receive the ciphertext
 *  @param outlen IN -- length of ciphertext buffer in bytes
 *  @param in IN -- plaintext to encrypt
 *  @param inlen IN -- length of plaintext buffer in bytes
 *  @param iv IN -- the IV for the this encrypt/decrypt
 *  @param sched IN --  AES key schedule for this encrypt
 */
int tc_cbc_mode_encrypt(uint8_t *out, unsigned int outlen, const uint8_t *in,
                        unsigned int inlen, const uint8_t *iv,
                        const TCAesKeySched_t sched);

/**
 * @brief CBC decryption procedure
 * CBC decrypts inlen bytes of the in buffer into the out buffer
 * using the provided encryption key schedule
 * @return returns TC_CRYPTO_SUCCESS (1)
 *         returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL or
 *                in == NULL or
 *                sched == NULL or
 *                inlen == 0 or
 *                outlen == 0 or
 *                (inlen % TC_AES_BLOCK_SIZE) != 0 or
 *                (outlen % TC_AES_BLOCK_SIZE) != 0 or
 *                outlen != inlen + TC_AES_BLOCK_SIZE
 * @note Assumes:- in == iv + ciphertext, i.e. the iv and the ciphertext are
 *                contiguous. This allows for a very efficient decryption
 *                algorithm that would not otherwise be possible
 *              - sched was configured by aes_set_decrypt_key
 *              - out buffer is large enough to hold the decrypted plaintext
 *              and is a contiguous buffer
 *              - inlen gives the number of bytes in the in buffer
 * @param out IN/OUT -- buffer to receive decrypted data
 * @param outlen IN -- length of plaintext buffer in bytes
 * @param in IN -- ciphertext to decrypt, including IV
 * @param inlen IN -- length of ciphertext buffer in bytes
 * @param iv IN -- the IV for the this encrypt/decrypt
 * @param sched IN --  AES key schedule for this decrypt
 *
 */
int tc_cbc_mode_decrypt(uint8_t *out, unsigned int outlen, const uint8_t *in,
                        unsigned int inlen, const uint8_t *iv,
                        const TCAesKeySched_t sched);

#ifdef __cplusplus
}
#endif

#endif /* __TC_CBC_MODE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ccm_mode.h
================================================
/* ccm_mode.h - TinyCrypt interface to a CCM mode implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to a CCM mode implementation.
 *
 *  Overview: CCM (for "Counter with CBC-MAC") mode is a NIST approved mode of
 *            operation defined in SP 800-38C.
 *
 *            TinyCrypt CCM implementation accepts:
 *
 *            1) Both non-empty payload and associated data (it encrypts and
 *            authenticates the payload and also authenticates the associated
 *            data);
 *            2) Non-empty payload and empty associated data (it encrypts and
 *            authenticates the payload);
 *            3) Non-empty associated data and empty payload (it degenerates to
 *            an authentication mode on the associated data).
 *
 *            TinyCrypt CCM implementation accepts associated data of any length
 *            between 0 and (2^16 - 2^8) bytes.
 *
 *  Security: The mac length parameter is an important parameter to estimate the
 *            security against collision attacks (that aim at finding different
 *            messages that produce the same authentication tag). TinyCrypt CCM
 *            implementation accepts any even integer between 4 and 16, as
 *            suggested in SP 800-38C.
 *
 *            RFC-3610, which also specifies CCM, presents a few relevant
 *            security suggestions, such as: it is recommended for most
 *            applications to use a mac length greater than 8. Besides, the
 *            usage of the same nonce for two different messages which are
 *            encrypted with the same key destroys the security of CCM mode.
 *
 *  Requires: AES-128
 *
 *  Usage:    1) call tc_ccm_config to configure.
 *
 *            2) call tc_ccm_mode_encrypt to encrypt data and generate tag.
 *
 *            3) call tc_ccm_mode_decrypt to decrypt data and verify tag.
 */

#ifndef __TC_CCM_MODE_H__
#define __TC_CCM_MODE_H__

#include "aes.h"
#include 

#ifdef __cplusplus
extern "C" {
#endif

/* max additional authenticated size in bytes: 2^16 - 2^8 = 65280 */
#define TC_CCM_AAD_MAX_BYTES 0xff00

/* max message size in bytes: 2^(8L) = 2^16 = 65536 */
#define TC_CCM_PAYLOAD_MAX_BYTES 0x10000

/* struct tc_ccm_mode_struct represents the state of a CCM computation */
typedef struct tc_ccm_mode_struct {
    TCAesKeySched_t sched; /* AES key schedule */
    uint8_t *nonce;        /* nonce required by CCM */
    unsigned int mlen;     /* mac length in bytes (parameter t in SP-800 38C) */
} * TCCcmMode_t;

/**
 * @brief CCM configuration procedure
 * @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                c == NULL or
 *                sched == NULL or
 *                nonce == NULL or
 *                mlen != {4, 6, 8, 10, 12, 16}
 * @param c -- CCM state
 * @param sched IN -- AES key schedule
 * @param nonce IN - nonce
 * @param nlen -- nonce length in bytes
 * @param mlen -- mac length in bytes (parameter t in SP-800 38C)
 */
int tc_ccm_config(TCCcmMode_t c, TCAesKeySched_t sched, uint8_t *nonce,
                  unsigned int nlen, unsigned int mlen);

/**
 * @brief CCM tag generation and encryption procedure
 * @return returns TC_CRYPTO_SUCCESS (1)
 *         returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL or
 *                c == NULL or
 *                ((plen > 0) and (payload == NULL)) or
 *                ((alen > 0) and (associated_data == NULL)) or
 *                (alen >= TC_CCM_AAD_MAX_BYTES) or
 *                (plen >= TC_CCM_PAYLOAD_MAX_BYTES) or
 *                (olen < plen + maclength)
 *
 * @param out OUT -- encrypted data
 * @param olen IN -- output length in bytes
 * @param associated_data IN -- associated data
 * @param alen IN -- associated data length in bytes
 * @param payload IN -- payload
 * @param plen IN -- payload length in bytes
 * @param c IN -- CCM state
 *
 * @note: out buffer should be at least (plen + c->mlen) bytes long.
 *
 * @note: The sequence b for encryption is formatted as follows:
 *        b = [FLAGS | nonce | counter ], where:
 *          FLAGS is 1 byte long
 *          nonce is 13 bytes long
 *          counter is 2 bytes long
 *        The byte FLAGS is composed by the following 8 bits:
 *          0-2 bits: used to represent the value of q-1
 *          3-7 btis: always 0's
 *
 * @note: The sequence b for authentication is formatted as follows:
 *        b = [FLAGS | nonce | length(mac length)], where:
 *          FLAGS is 1 byte long
 *          nonce is 13 bytes long
 *          length(mac length) is 2 bytes long
 *        The byte FLAGS is composed by the following 8 bits:
 *          0-2 bits: used to represent the value of q-1
 *          3-5 bits: mac length (encoded as: (mlen-2)/2)
 *          6: Adata (0 if alen == 0, and 1 otherwise)
 *          7: always 0
 */
int tc_ccm_generation_encryption(uint8_t *out, unsigned int olen,
                                 const uint8_t *associated_data,
                                 unsigned int alen, const uint8_t *payload,
                                 unsigned int plen, TCCcmMode_t c);

/**
 * @brief CCM decryption and tag verification procedure
 * @return returns TC_CRYPTO_SUCCESS (1)
 *         returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL or
 *                c == NULL or
 *                ((plen > 0) and (payload == NULL)) or
 *                ((alen > 0) and (associated_data == NULL)) or
 *                (alen >= TC_CCM_AAD_MAX_BYTES) or
 *                (plen >= TC_CCM_PAYLOAD_MAX_BYTES) or
 *                (olen < plen - c->mlen)
 *
 * @param out OUT -- decrypted data
 * @param associated_data IN -- associated data
 * @param alen IN -- associated data length in bytes
 * @param payload IN -- payload
 * @param plen IN -- payload length in bytes
 * @param c IN -- CCM state
 *
 * @note: out buffer should be at least (plen - c->mlen) bytes long.
 *
 * @note: The sequence b for encryption is formatted as follows:
 *        b = [FLAGS | nonce | counter ], where:
 *          FLAGS is 1 byte long
 *          nonce is 13 bytes long
 *          counter is 2 bytes long
 *        The byte FLAGS is composed by the following 8 bits:
 *          0-2 bits: used to represent the value of q-1
 *          3-7 btis: always 0's
 *
 * @note: The sequence b for authentication is formatted as follows:
 *        b = [FLAGS | nonce | length(mac length)], where:
 *          FLAGS is 1 byte long
 *          nonce is 13 bytes long
 *          length(mac length) is 2 bytes long
 *        The byte FLAGS is composed by the following 8 bits:
 *          0-2 bits: used to represent the value of q-1
 *          3-5 bits: mac length (encoded as: (mlen-2)/2)
 *          6: Adata (0 if alen == 0, and 1 otherwise)
 *          7: always 0
 */
int tc_ccm_decryption_verification(uint8_t *out, unsigned int olen,
                                   const uint8_t *associated_data,
                                   unsigned int alen, const uint8_t *payload, unsigned int plen,
                                   TCCcmMode_t c);

#ifdef __cplusplus
}
#endif

#endif /* __TC_CCM_MODE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/cmac_mode.h
================================================
/*  cmac_mode.h -- interface to a CMAC implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to a CMAC implementation.
 *
 *  Overview: CMAC is defined NIST in SP 800-38B, and is the standard algorithm
 *            for computing a MAC using a block cipher. It can compute the MAC
 *            for a byte string of any length. It is distinguished from CBC-MAC
 *            in the processing of the final message block; CMAC uses a
 *            different technique to compute the final message block is full
 *            size or only partial, while CBC-MAC uses the same technique for
 *            both. This difference permits CMAC to be applied to variable
 *            length messages, while all messages authenticated by CBC-MAC must
 *            be the same length.
 *
 *  Security: AES128-CMAC mode of operation offers 64 bits of security against
 *            collision attacks. Note however that an external attacker cannot
 *            generate the tags him/herself without knowing the MAC key. In this
 *            sense, to attack the collision property of AES128-CMAC, an
 *            external attacker would need the cooperation of the legal user to
 *            produce an exponentially high number of tags (e.g. 2^64) to
 *            finally be able to look for collisions and benefit from them. As
 *            an extra precaution, the current implementation allows to at most
 *            2^48 calls to the tc_cmac_update function before re-calling
 *            tc_cmac_setup (allowing a new key to be set), as suggested in
 *            Appendix B of SP 800-38B.
 *
 *  Requires: AES-128
 *
 *  Usage:   This implementation provides a "scatter-gather" interface, so that
 *           the CMAC value can be computed incrementally over a message
 *           scattered in different segments throughout memory. Experience shows
 *           this style of interface tends to minimize the burden of programming
 *           correctly. Like all symmetric key operations, it is session
 *           oriented.
 *
 *           To begin a CMAC session, use tc_cmac_setup to initialize a struct
 *           tc_cmac_struct with encryption key and buffer. Our implementation
 *           always assume that the AES key to be the same size as the block
 *           cipher block size. Once setup, this data structure can be used for
 *           many CMAC computations.
 *
 *           Once the state has been setup with a key, computing the CMAC of
 *           some data requires three steps:
 *
 *           (1) first use tc_cmac_init to initialize a new CMAC computation.
 *           (2) next mix all of the data into the CMAC computation state using
 *               tc_cmac_update. If all of the data resides in a single data
 *               segment then only one tc_cmac_update call is needed; if data
 *               is scattered throughout memory in n data segments, then n calls
 *               will be needed. CMAC IS ORDER SENSITIVE, to be able to detect
 *               attacks that swap bytes, so the order in which data is mixed
 *               into the state is critical!
 *           (3) Once all of the data for a message has been mixed, use
 *               tc_cmac_final to compute the CMAC tag value.
 *
 *           Steps (1)-(3) can be repeated as many times as you want to CMAC
 *           multiple messages. A practical limit is 2^48 1K messages before you
 *           have to change the key.
 *
 *           Once you are done computing CMAC with a key, it is a good idea to
 *           destroy the state so an attacker cannot recover the key; use
 *           tc_cmac_erase to accomplish this.
 */

#ifndef __TC_CMAC_MODE_H__
#define __TC_CMAC_MODE_H__

#include 

#include 

#ifdef __cplusplus
extern "C" {
#endif

/* padding for last message block */
#define TC_CMAC_PADDING 0x80

/* struct tc_cmac_struct represents the state of a CMAC computation */
typedef struct tc_cmac_struct {
    /* initialization vector */
    uint8_t iv[TC_AES_BLOCK_SIZE];
    /* used if message length is a multiple of block_size bytes */
    uint8_t K1[TC_AES_BLOCK_SIZE];
    /* used if message length isn't a multiple block_size bytes */
    uint8_t K2[TC_AES_BLOCK_SIZE];
    /* where to put bytes that didn't fill a block */
    uint8_t leftover[TC_AES_BLOCK_SIZE];
    /* identifies the encryption key */
    unsigned int keyid;
    /* next available leftover location */
    unsigned int leftover_offset;
    /* AES key schedule */
    TCAesKeySched_t sched;
    /* calls to tc_cmac_update left before re-key */
    uint64_t countdown;
} * TCCmacState_t;

/**
 * @brief Configures the CMAC state to use the given AES key
 * @return returns TC_CRYPTO_SUCCESS (1) after having configured the CMAC state
 *         returns TC_CRYPTO_FAIL (0) if:
 *              s == NULL or
 *              key == NULL
 *
 * @param s IN/OUT -- the state to set up
 * @param key IN -- the key to use
 * @param sched IN -- AES key schedule
 */
int tc_cmac_setup(TCCmacState_t s, const uint8_t *key,
                  TCAesKeySched_t sched);

/**
 * @brief Erases the CMAC state
 * @return returns TC_CRYPTO_SUCCESS (1) after having configured the CMAC state
 *         returns TC_CRYPTO_FAIL (0) if:
 *              s == NULL
 *
 * @param s IN/OUT -- the state to erase
 */
int tc_cmac_erase(TCCmacState_t s);

/**
 * @brief Initializes a new CMAC computation
 * @return returns TC_CRYPTO_SUCCESS (1) after having initialized the CMAC state
 *         returns TC_CRYPTO_FAIL (0) if:
 *              s == NULL
 *
 * @param s IN/OUT -- the state to initialize
 */
int tc_cmac_init(TCCmacState_t s);

/**
 * @brief Incrementally computes CMAC over the next data segment
 * @return returns TC_CRYPTO_SUCCESS (1) after successfully updating the CMAC state
 *         returns TC_CRYPTO_FAIL (0) if:
 *              s == NULL or
 *              if data == NULL when dlen > 0
 *
 * @param s IN/OUT -- the CMAC state
 * @param data IN -- the next data segment to MAC
 * @param dlen IN -- the length of data in bytes
 */
int tc_cmac_update(TCCmacState_t s, const uint8_t *data, size_t dlen);

/**
 * @brief Generates the tag from the CMAC state
 * @return returns TC_CRYPTO_SUCCESS (1) after successfully generating the tag
 *         returns TC_CRYPTO_FAIL (0) if:
 *              tag == NULL or
 *              s == NULL
 *
 * @param tag OUT -- the CMAC tag
 * @param s IN -- CMAC state
 */
int tc_cmac_final(uint8_t *tag, TCCmacState_t s);

#ifdef __cplusplus
}
#endif

#endif /* __TC_CMAC_MODE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/constants.h
================================================
/* constants.h - TinyCrypt interface to constants */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief -- Interface to constants.
 *
 */

#ifndef __TC_CONSTANTS_H__
#define __TC_CONSTANTS_H__

#ifdef __cplusplus
extern "C" {
#endif

#include 

#ifndef NULL
#define NULL ((void *)0)
#endif

#define TC_CRYPTO_SUCCESS 1
#define TC_CRYPTO_FAIL    0

#define TC_ZERO_BYTE 0x00

#ifdef __cplusplus
}
#endif

#endif /* __TC_CONSTANTS_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ctr_mode.h
================================================
/* ctr_mode.h - TinyCrypt interface to CTR mode */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to CTR mode.
 *
 *  Overview:  CTR (pronounced "counter") mode is a NIST approved mode of
 *             operation defined in SP 800-38a. It can be used with any
 *             block cipher to provide confidentiality of strings of any
 *             length. TinyCrypt hard codes AES128 as the block cipher.
 *
 *  Security:  CTR mode achieves confidentiality only if the counter value is
 *             never reused with a same encryption key. If the counter is
 *             repeated, than an adversary might be able to defeat the scheme.
 *
 *             A usual method to ensure different counter values refers to
 *             initialize the counter in a given value (0, for example) and
 *             increases it every time a new block is enciphered. This naturally
 *             leaves to a limitation on the number q of blocks that can be
 *             enciphered using a same key: q < 2^(counter size).
 *
 *             TinyCrypt uses a counter of 32 bits. This means that after 2^32
 *             block encryptions, the counter will be reused (thus losing CBC
 *             security). 2^32 block encryptions should be enough for most of
 *             applications targeting constrained devices. Applications intended
 *             to encrypt a larger number of blocks must replace the key after
 *             2^32 block encryptions.
 *
 *             CTR mode provides NO data integrity.
 *
 *  Requires: AES-128
 *
 *  Usage:     1) call tc_ctr_mode to process the data to encrypt/decrypt.
 *
 */

#ifndef __TC_CTR_MODE_H__
#define __TC_CTR_MODE_H__

#include "aes.h"
#include "constants.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 *  @brief CTR mode encryption/decryption procedure.
 *  CTR mode encrypts (or decrypts) inlen bytes from in buffer into out buffer
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL or
 *                in == NULL or
 *                ctr == NULL or
 *                sched == NULL or
 *                inlen == 0 or
 *                outlen == 0 or
 *                inlen != outlen
 *  @note Assumes:- The current value in ctr has NOT been used with sched
 *              - out points to inlen bytes
 *              - in points to inlen bytes
 *              - ctr is an integer counter in littleEndian format
 *              - sched was initialized by aes_set_encrypt_key
 * @param out OUT -- produced ciphertext (plaintext)
 * @param outlen IN -- length of ciphertext buffer in bytes
 * @param in IN -- data to encrypt (or decrypt)
 * @param inlen IN -- length of input data in bytes
 * @param ctr IN/OUT -- the current counter value
 * @param sched IN -- an initialized AES key schedule
 */
int tc_ctr_mode(uint8_t *out, unsigned int outlen, const uint8_t *in,
                unsigned int inlen, uint8_t *ctr, const TCAesKeySched_t sched);

#ifdef __cplusplus
}
#endif

#endif /* __TC_CTR_MODE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ctr_prng.h
================================================
/* ctr_prng.h - TinyCrypt interface to a CTR-PRNG implementation */

/*
 * Copyright (c) 2016, Chris Morrison
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to a CTR-PRNG implementation.
 *
 *  Overview:   A pseudo-random number generator (PRNG) generates a sequence
 *              of numbers that have a distribution close to the one expected
 *              for a sequence of truly random numbers. The NIST Special
 *              Publication 800-90A specifies several mechanisms to generate
 *              sequences of pseudo random numbers, including the CTR-PRNG one
 *              which is based on AES. TinyCrypt implements CTR-PRNG with
 *              AES-128.
 *
 *  Security:   A cryptographically secure PRNG depends on the existence of an
 *              entropy source to provide a truly random seed as well as the
 *              security of the primitives used as the building blocks (AES-128
 *              in this instance).
 *
 *  Requires:   - AES-128
 *
 *  Usage:      1) call tc_ctr_prng_init to seed the prng context
 *
 *              2) call tc_ctr_prng_reseed to mix in additional entropy into
 *              the prng context
 *
 *              3) call tc_ctr_prng_generate to output the pseudo-random data
 *
 *              4) call tc_ctr_prng_uninstantiate to zero out the prng context
 */

#ifndef __TC_CTR_PRNG_H__
#define __TC_CTR_PRNG_H__

#include "aes.h"

#define TC_CTR_PRNG_RESEED_REQ -1

#ifdef __cplusplus
extern "C" {
#endif

typedef struct {
    /* updated each time another BLOCKLEN_BYTES bytes are produced */
    uint8_t V[TC_AES_BLOCK_SIZE];

    /* updated whenever the PRNG is reseeded */
    struct tc_aes_key_sched_struct key;

    /* number of requests since initialization/reseeding */
    uint64_t reseedCount;
} TCCtrPrng_t;

/**
 *  @brief CTR-PRNG initialization procedure
 *  Initializes prng context with entropy and personalization string (if any)
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                ctx == NULL,
 *                entropy == NULL,
 *                entropyLen < (TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE)
 *  @note       Only the first (TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE) bytes of
 *              both the entropy and personalization inputs are used -
 *              supplying additional bytes has no effect.
 *  @param ctx IN/OUT -- the PRNG context to initialize
 *  @param entropy IN -- entropy used to seed the PRNG
 *  @param entropyLen IN -- entropy length in bytes
 *  @param personalization IN -- personalization string used to seed the PRNG
 *  (may be null)
 *  @param plen IN -- personalization length in bytes
 *
 */
int tc_ctr_prng_init(TCCtrPrng_t *const ctx,
                     uint8_t const *const entropy,
                     unsigned int entropyLen,
                     uint8_t const *const personalization,
                     unsigned int pLen);

/**
 *  @brief CTR-PRNG reseed procedure
 *  Mixes entropy and additional_input into the prng context
 *  @return returns  TC_CRYPTO_SUCCESS (1)
 *  returns TC_CRYPTO_FAIL (0) if:
 *          ctx == NULL,
 *          entropy == NULL,
 *          entropylen < (TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE)
 *  @note It is better to reseed an existing prng context rather than
 *        re-initialise, so that any existing entropy in the context is
 *        presereved.  This offers some protection against undetected failures
 *        of the entropy source.
 *  @note Assumes tc_ctr_prng_init has been called for ctx
 *  @param ctx IN/OUT -- the PRNG state
 *  @param entropy IN -- entropy to mix into the prng
 *  @param entropylen IN -- length of entropy in bytes
 *  @param additional_input IN -- additional input to the prng (may be null)
 *  @param additionallen IN -- additional input length in bytes
 */
int tc_ctr_prng_reseed(TCCtrPrng_t *const ctx,
                       uint8_t const *const entropy,
                       unsigned int entropyLen,
                       uint8_t const *const additional_input,
                       unsigned int additionallen);

/**
 *  @brief CTR-PRNG generate procedure
 *  Generates outlen pseudo-random bytes into out buffer, updates prng
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CTR_PRNG_RESEED_REQ (-1) if a reseed is needed
 *             returns TC_CRYPTO_FAIL (0) if:
 *                ctx == NULL,
 *                out == NULL,
 *                outlen >= 2^16
 *  @note Assumes tc_ctr_prng_init has been called for ctx
 *  @param ctx IN/OUT -- the PRNG context
 *  @param additional_input IN -- additional input to the prng (may be null)
 *  @param additionallen IN -- additional input length in bytes
 *  @param out IN/OUT -- buffer to receive output
 *  @param outlen IN -- size of out buffer in bytes
 */
int tc_ctr_prng_generate(TCCtrPrng_t *const ctx,
                         uint8_t const *const additional_input,
                         unsigned int additionallen,
                         uint8_t *const out,
                         unsigned int outlen);

/**
 *  @brief CTR-PRNG uninstantiate procedure
 *  Zeroes the internal state of the supplied prng context
 *  @return none
 *  @param ctx IN/OUT -- the PRNG context
 */
void tc_ctr_prng_uninstantiate(TCCtrPrng_t *const ctx);

#ifdef __cplusplus
}
#endif

#endif /* __TC_CTR_PRNG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ecc.h
================================================
/* ecc.h - TinyCrypt interface to common ECC functions */

/* Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief -- Interface to common ECC functions.
 *
 *  Overview: This software is an implementation of common functions
 *            necessary to elliptic curve cryptography. This implementation uses
 *            curve NIST p-256.
 *
 *  Security: The curve NIST p-256 provides approximately 128 bits of security.
 *
 */

#ifndef __TC_UECC_H__
#define __TC_UECC_H__

#include 

#ifdef __cplusplus
extern "C" {
#endif

/* Word size (4 bytes considering 32-bits architectures) */
#define uECC_WORD_SIZE 4

/* setting max number of calls to prng: */
#ifndef uECC_RNG_MAX_TRIES
#define uECC_RNG_MAX_TRIES 64
#endif

/* defining data types to store word and bit counts: */
typedef int8_t wordcount_t;
typedef int16_t bitcount_t;
/* defining data type for comparison result: */
typedef int8_t cmpresult_t;
/* defining data type to store ECC coordinate/point in 32bits words: */
typedef unsigned int uECC_word_t;
/* defining data type to store an ECC coordinate/point in 64bits words: */
typedef uint64_t uECC_dword_t;

/* defining masks useful for ecc computations: */
#define HIGH_BIT_SET         0x80000000
#define uECC_WORD_BITS       32
#define uECC_WORD_BITS_SHIFT 5
#define uECC_WORD_BITS_MASK  0x01F

/* Number of words of 32 bits to represent an element of the the curve p-256: */
#define NUM_ECC_WORDS 8
/* Number of bytes to represent an element of the the curve p-256: */
#define NUM_ECC_BYTES (uECC_WORD_SIZE * NUM_ECC_WORDS)

/* structure that represents an elliptic curve (e.g. p256):*/
struct uECC_Curve_t;
typedef const struct uECC_Curve_t *uECC_Curve;
struct uECC_Curve_t {
    wordcount_t num_words;
    wordcount_t num_bytes;
    bitcount_t num_n_bits;
    uECC_word_t p[NUM_ECC_WORDS];
    uECC_word_t n[NUM_ECC_WORDS];
    uECC_word_t G[NUM_ECC_WORDS * 2];
    uECC_word_t b[NUM_ECC_WORDS];
    void (*double_jacobian)(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *Z1,
                            uECC_Curve curve);
    void (*x_side)(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve);
    void (*mmod_fast)(uECC_word_t *result, uECC_word_t *product);
};

/*
 * @brief computes doubling of point ion jacobian coordinates, in place.
 * @param X1 IN/OUT -- x coordinate
 * @param Y1 IN/OUT -- y coordinate
 * @param Z1 IN/OUT -- z coordinate
 * @param curve IN -- elliptic curve
 */
void double_jacobian_default(uECC_word_t *X1, uECC_word_t *Y1,
                             uECC_word_t *Z1, uECC_Curve curve);

/*
 * @brief Computes x^3 + ax + b. result must not overlap x.
 * @param result OUT -- x^3 + ax + b
 * @param x IN -- value of x
 * @param curve IN -- elliptic curve
 */
void x_side_default(uECC_word_t *result, const uECC_word_t *x,
                    uECC_Curve curve);

/*
 * @brief Computes result = product % curve_p
 * from http://www.nsa.gov/ia/_files/nist-routines.pdf
 * @param result OUT -- product % curve_p
 * @param product IN -- value to be reduced mod curve_p
 */
void vli_mmod_fast_secp256r1(unsigned int *result, unsigned int *product);

/* Bytes to words ordering: */
#define BYTES_TO_WORDS_8(a, b, c, d, e, f, g, h) 0x##d##c##b##a, 0x##h##g##f##e
#define BYTES_TO_WORDS_4(a, b, c, d)             0x##d##c##b##a
#define BITS_TO_WORDS(num_bits) \
    ((num_bits + ((uECC_WORD_SIZE * 8) - 1)) / (uECC_WORD_SIZE * 8))
#define BITS_TO_BYTES(num_bits) ((num_bits + 7) / 8)

/* definition of curve NIST p-256: */
static const struct uECC_Curve_t curve_secp256r1 = {
    NUM_ECC_WORDS,
    NUM_ECC_BYTES,
    256,
    /* num_n_bits */ { BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF), BYTES_TO_WORDS_8(FF, FF, FF, FF, 00, 00, 00, 00), BYTES_TO_WORDS_8(00, 00, 00, 00, 00, 00, 00, 00), BYTES_TO_WORDS_8(01, 00, 00, 00, FF, FF, FF, FF) },
    { BYTES_TO_WORDS_8(51, 25, 63, FC, C2, CA, B9, F3),
      BYTES_TO_WORDS_8(84, 9E, 17, A7, AD, FA, E6, BC),
      BYTES_TO_WORDS_8(FF, FF, FF, FF, FF, FF, FF, FF),
      BYTES_TO_WORDS_8(00, 00, 00, 00, FF, FF, FF, FF) },
    { BYTES_TO_WORDS_8(96, C2, 98, D8, 45, 39, A1, F4),
      BYTES_TO_WORDS_8(A0, 33, EB, 2D, 81, 7D, 03, 77),
      BYTES_TO_WORDS_8(F2, 40, A4, 63, E5, E6, BC, F8),
      BYTES_TO_WORDS_8(47, 42, 2C, E1, F2, D1, 17, 6B),

      BYTES_TO_WORDS_8(F5, 51, BF, 37, 68, 40, B6, CB),
      BYTES_TO_WORDS_8(CE, 5E, 31, 6B, 57, 33, CE, 2B),
      BYTES_TO_WORDS_8(16, 9E, 0F, 7C, 4A, EB, E7, 8E),
      BYTES_TO_WORDS_8(9B, 7F, 1A, FE, E2, 42, E3, 4F) },
    { BYTES_TO_WORDS_8(4B, 60, D2, 27, 3E, 3C, CE, 3B),
      BYTES_TO_WORDS_8(F6, B0, 53, CC, B0, 06, 1D, 65),
      BYTES_TO_WORDS_8(BC, 86, 98, 76, 55, BD, EB, B3),
      BYTES_TO_WORDS_8(E7, 93, 3A, AA, D8, 35, C6, 5A) },
    &double_jacobian_default,
    &x_side_default,
    &vli_mmod_fast_secp256r1
};

uECC_Curve uECC_secp256r1(void);

/*
 * @brief Generates a random integer in the range 0 < random < top.
 * Both random and top have num_words words.
 * @param random OUT -- random integer in the range 0 < random < top
 * @param top IN -- upper limit
 * @param num_words IN -- number of words
 * @return a random integer in the range 0 < random < top
 */
int uECC_generate_random_int(uECC_word_t *random, const uECC_word_t *top,
                             wordcount_t num_words);

/* uECC_RNG_Function type
 * The RNG function should fill 'size' random bytes into 'dest'. It should
 * return 1 if 'dest' was filled with random data, or 0 if the random data could
 * not be generated. The filled-in values should be either truly random, or from
 * a cryptographically-secure PRNG.
 *
 * A correctly functioning RNG function must be set (using uECC_set_rng())
 * before calling uECC_make_key() or uECC_sign().
 *
 * Setting a correctly functioning RNG function improves the resistance to
 * side-channel attacks for uECC_shared_secret().
 *
 * A correct RNG function is set by default. If you are building on another
 * POSIX-compliant system that supports /dev/random or /dev/urandom, you can
 * define uECC_POSIX to use the predefined RNG.
 */
typedef int (*uECC_RNG_Function)(uint8_t *dest, unsigned int size);

/*
 * @brief Set the function that will be used to generate random bytes. The RNG
 * function should return 1 if the random data was generated, or 0 if the random
 * data could not be generated.
 *
 * @note On platforms where there is no predefined RNG function, this must be
 * called before uECC_make_key() or uECC_sign() are used.
 *
 * @param rng_function IN -- function that will be used to generate random bytes
 */
void uECC_set_rng(uECC_RNG_Function rng_function);

/*
 * @brief provides current uECC_RNG_Function.
 * @return Returns the function that will be used to generate random bytes.
 */
uECC_RNG_Function uECC_get_rng(void);

/*
 * @brief computes the size of a private key for the curve in bytes.
 * @param curve IN -- elliptic curve
 * @return size of a private key for the curve in bytes.
 */
int uECC_curve_private_key_size(uECC_Curve curve);

/*
 * @brief computes the size of a public key for the curve in bytes.
 * @param curve IN -- elliptic curve
 * @return the size of a public key for the curve in bytes.
 */
int uECC_curve_public_key_size(uECC_Curve curve);

/*
 * @brief Compute the corresponding public key for a private key.
 * @param private_key IN -- The private key to compute the public key for
 * @param public_key OUT -- Will be filled in with the corresponding public key
 * @param curve
 * @return Returns 1 if key was computed successfully, 0 if an error occurred.
 */
int uECC_compute_public_key(const uint8_t *private_key,
                            uint8_t *public_key, uECC_Curve curve);

/*
 * @brief Compute public-key.
 * @return corresponding public-key.
 * @param result OUT -- public-key
 * @param private_key IN -- private-key
 * @param curve IN -- elliptic curve
 */
uECC_word_t EccPoint_compute_public_key(uECC_word_t *result,
                                        uECC_word_t *private_key, uECC_Curve curve);

/*
 * @brief Regularize the bitcount for the private key so that attackers cannot
 * use a side channel attack to learn the number of leading zeros.
 * @return Regularized k
 * @param k IN -- private-key
 * @param k0 IN/OUT -- regularized k
 * @param k1 IN/OUT -- regularized k
 * @param curve IN -- elliptic curve
 */
uECC_word_t regularize_k(const uECC_word_t *const k, uECC_word_t *k0,
                         uECC_word_t *k1, uECC_Curve curve);

/*
 * @brief Point multiplication algorithm using Montgomery's ladder with co-Z
 * coordinates. See http://eprint.iacr.org/2011/338.pdf.
 * @note Result may overlap point.
 * @param result OUT -- returns scalar*point
 * @param point IN -- elliptic curve point
 * @param scalar IN -- scalar
 * @param initial_Z IN -- initial value for z
 * @param num_bits IN -- number of bits in scalar
 * @param curve IN -- elliptic curve
 */
void EccPoint_mult(uECC_word_t *result, const uECC_word_t *point,
                   const uECC_word_t *scalar, const uECC_word_t *initial_Z,
                   bitcount_t num_bits, uECC_Curve curve);

/*
 * @brief Constant-time comparison to zero - secure way to compare long integers
 * @param vli IN -- very long integer
 * @param num_words IN -- number of words in the vli
 * @return 1 if vli == 0, 0 otherwise.
 */
uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words);

/*
 * @brief Check if 'point' is the point at infinity
 * @param point IN -- elliptic curve point
 * @param curve IN -- elliptic curve
 * @return if 'point' is the point at infinity, 0 otherwise.
 */
uECC_word_t EccPoint_isZero(const uECC_word_t *point, uECC_Curve curve);

/*
 * @brief computes the sign of left - right, in constant time.
 * @param left IN -- left term to be compared
 * @param right IN -- right term to be compared
 * @param num_words IN -- number of words
 * @return the sign of left - right
 */
cmpresult_t uECC_vli_cmp(const uECC_word_t *left, const uECC_word_t *right,
                         wordcount_t num_words);

/*
 * @brief computes sign of left - right, not in constant time.
 * @note should not be used if inputs are part of a secret
 * @param left IN -- left term to be compared
 * @param right IN -- right term to be compared
 * @param num_words IN -- number of words
 * @return the sign of left - right
 */
cmpresult_t uECC_vli_cmp_unsafe(const uECC_word_t *left, const uECC_word_t *right,
                                wordcount_t num_words);

/*
 * @brief Computes result = (left - right) % mod.
 * @note Assumes that (left < mod) and (right < mod), and that result does not
 * overlap mod.
 * @param result OUT -- (left - right) % mod
 * @param left IN -- leftright term in modular subtraction
 * @param right IN -- right term in modular subtraction
 * @param mod IN -- mod
 * @param num_words IN -- number of words
 */
void uECC_vli_modSub(uECC_word_t *result, const uECC_word_t *left,
                     const uECC_word_t *right, const uECC_word_t *mod,
                     wordcount_t num_words);

/*
 * @brief Computes P' = (x1', y1', Z3), P + Q = (x3, y3, Z3) or
 * P => P', Q => P + Q
 * @note assumes Input P = (x1, y1, Z), Q = (x2, y2, Z)
 * @param X1 IN -- x coordinate of P
 * @param Y1 IN -- y coordinate of P
 * @param X2 IN -- x coordinate of Q
 * @param Y2 IN -- y coordinate of Q
 * @param curve IN -- elliptic curve
 */
void XYcZ_add(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *X2,
              uECC_word_t *Y2, uECC_Curve curve);

/*
 * @brief Computes (x1 * z^2, y1 * z^3)
 * @param X1 IN -- previous x1 coordinate
 * @param Y1 IN -- previous y1 coordinate
 * @param Z IN -- z value
 * @param curve IN -- elliptic curve
 */
void apply_z(uECC_word_t *X1, uECC_word_t *Y1, const uECC_word_t *const Z,
             uECC_Curve curve);

/*
 * @brief Check if bit is set.
 * @return Returns nonzero if bit 'bit' of vli is set.
 * @warning It is assumed that the value provided in 'bit' is within the
 * boundaries of the word-array 'vli'.
 * @note The bit ordering layout assumed for vli is: {31, 30, ..., 0},
 * {63, 62, ..., 32}, {95, 94, ..., 64}, {127, 126,..., 96} for a vli consisting
 * of 4 uECC_word_t elements.
 */
uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit);

/*
 * @brief Computes result = product % mod, where product is 2N words long.
 * @param result OUT -- product % mod
 * @param mod IN -- module
 * @param num_words IN -- number of words
 * @warning Currently only designed to work for curve_p or curve_n.
 */
void uECC_vli_mmod(uECC_word_t *result, uECC_word_t *product,
                   const uECC_word_t *mod, wordcount_t num_words);

/*
 * @brief Computes modular product (using curve->mmod_fast)
 * @param result OUT -- (left * right) mod % curve_p
 * @param left IN -- left term in product
 * @param right IN -- right term in product
 * @param curve IN -- elliptic curve
 */
void uECC_vli_modMult_fast(uECC_word_t *result, const uECC_word_t *left,
                           const uECC_word_t *right, uECC_Curve curve);

/*
 * @brief Computes result = left - right.
 * @note Can modify in place.
 * @param result OUT -- left - right
 * @param left IN -- left term in subtraction
 * @param right IN -- right term in subtraction
 * @param num_words IN -- number of words
 * @return borrow
 */
uECC_word_t uECC_vli_sub(uECC_word_t *result, const uECC_word_t *left,
                         const uECC_word_t *right, wordcount_t num_words);

/*
 * @brief Constant-time comparison function(secure way to compare long ints)
 * @param left IN -- left term in comparison
 * @param right IN -- right term in comparison
 * @param num_words IN -- number of words
 * @return Returns 0 if left == right, 1 otherwise.
 */
uECC_word_t uECC_vli_equal(const uECC_word_t *left, const uECC_word_t *right,
                           wordcount_t num_words);

/*
 * @brief Computes (left * right) % mod
 * @param result OUT -- (left * right) % mod
 * @param left IN -- left term in product
 * @param right IN -- right term in product
 * @param mod IN -- mod
 * @param num_words IN -- number of words
 */
void uECC_vli_modMult(uECC_word_t *result, const uECC_word_t *left,
                      const uECC_word_t *right, const uECC_word_t *mod,
                      wordcount_t num_words);

/*
 * @brief Computes (1 / input) % mod
 * @note All VLIs are the same size.
 * @note See "Euclid's GCD to Montgomery Multiplication to the Great Divide"
 * @param result OUT -- (1 / input) % mod
 * @param input IN -- value to be modular inverted
 * @param mod IN -- mod
 * @param num_words -- number of words
 */
void uECC_vli_modInv(uECC_word_t *result, const uECC_word_t *input,
                     const uECC_word_t *mod, wordcount_t num_words);

/*
 * @brief Sets dest = src.
 * @param dest OUT -- destination buffer
 * @param src IN --  origin buffer
 * @param num_words IN -- number of words
 */
void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src,
                  wordcount_t num_words);

/*
 * @brief Computes (left + right) % mod.
 * @note Assumes that (left < mod) and right < mod), and that result does not
 * overlap mod.
 * @param result OUT -- (left + right) % mod.
 * @param left IN -- left term in addition
 * @param right IN -- right term in addition
 * @param mod IN -- mod
 * @param num_words IN -- number of words
 */
void uECC_vli_modAdd(uECC_word_t *result, const uECC_word_t *left,
                     const uECC_word_t *right, const uECC_word_t *mod,
                     wordcount_t num_words);

/*
 * @brief Counts the number of bits required to represent vli.
 * @param vli IN -- very long integer
 * @param max_words IN -- number of words
 * @return number of bits in given vli
 */
bitcount_t uECC_vli_numBits(const uECC_word_t *vli,
                            const wordcount_t max_words);

/*
 * @brief Erases (set to 0) vli
 * @param vli IN -- very long integer
 * @param num_words IN -- number of words
 */
void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words);

/*
 * @brief check if it is a valid point in the curve
 * @param point IN -- point to be checked
 * @param curve IN -- elliptic curve
 * @return 0 if point is valid
 * @exception returns -1 if it is a point at infinity
 * @exception returns -2 if x or y is smaller than p,
 * @exception returns -3 if y^2 != x^3 + ax + b.
 */
int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve);

/*
 * @brief Check if a public key is valid.
 * @param public_key IN -- The public key to be checked.
 * @return returns 0 if the public key is valid
 * @exception returns -1 if it is a point at infinity
 * @exception returns -2 if x or y is smaller than p,
 * @exception returns -3 if y^2 != x^3 + ax + b.
 * @exception returns -4 if public key is the group generator.
 *
 * @note Note that you are not required to check for a valid public key before
 * using any other uECC functions. However, you may wish to avoid spending CPU
 * time computing a shared secret or verifying a signature using an invalid
 * public key.
 */
int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve);

/*
  * @brief Converts an integer in uECC native format to big-endian bytes.
  * @param bytes OUT -- bytes representation
  * @param num_bytes IN -- number of bytes
  * @param native IN -- uECC native representation
  */
void uECC_vli_nativeToBytes(uint8_t *bytes, int num_bytes,
                            const unsigned int *native);

/*
 * @brief Converts big-endian bytes to an integer in uECC native format.
 * @param native OUT -- uECC native representation
 * @param bytes IN -- bytes representation
 * @param num_bytes IN -- number of bytes
 */
void uECC_vli_bytesToNative(unsigned int *native, const uint8_t *bytes,
                            int num_bytes);

#ifdef __cplusplus
}
#endif

#endif /* __TC_UECC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ecc_dh.h
================================================
/* ecc_dh.h - TinyCrypt interface to EC-DH implementation */

/*
 * Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/* Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief -- Interface to EC-DH implementation.
 *
 *  Overview: This software is an implementation of EC-DH. This implementation
 *            uses curve NIST p-256.
 *
 *  Security: The curve NIST p-256 provides approximately 128 bits of security.
 */

#ifndef __TC_ECC_DH_H__
#define __TC_ECC_DH_H__

#include "ecc.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Create a public/private key pair.
 * @return returns TC_CRYPTO_SUCCESS (1) if the key pair was generated successfully
 *         returns TC_CRYPTO_FAIL (0) if error while generating key pair
 *
 * @param p_public_key OUT -- Will be filled in with the public key. Must be at
 * least 2 * the curve size (in bytes) long. For curve secp256r1, p_public_key
 * must be 64 bytes long.
 * @param p_private_key OUT -- Will be filled in with the private key. Must be as
 * long as the curve order (for secp256r1, p_private_key must be 32 bytes long).
 *
 * @note side-channel countermeasure: algorithm strengthened against timing
 * attack.
 * @warning A cryptographically-secure PRNG function must be set (using
 * uECC_set_rng()) before calling uECC_make_key().
 */
int uECC_make_key(uint8_t *p_public_key, uint8_t *p_private_key, uECC_Curve curve);

#ifdef ENABLE_TESTS

/**
 * @brief Create a public/private key pair given a specific d.
 *
 * @note THIS FUNCTION SHOULD BE CALLED ONLY FOR TEST PURPOSES. Refer to
 * uECC_make_key() function for real applications.
 */
int uECC_make_key_with_d(uint8_t *p_public_key, uint8_t *p_private_key,
                         unsigned int *d, uECC_Curve curve);
#endif

/**
 * @brief Compute a shared secret given your secret key and someone else's
 * public key.
 * @return returns TC_CRYPTO_SUCCESS (1) if the shared secret was computed successfully
 *         returns TC_CRYPTO_FAIL (0) otherwise
 *
 * @param p_secret OUT -- Will be filled in with the shared secret value. Must be
 * the same size as the curve size (for curve secp256r1, secret must be 32 bytes
 * long.
 * @param p_public_key IN -- The public key of the remote party.
 * @param p_private_key IN -- Your private key.
 *
 * @warning It is recommended to use the output of uECC_shared_secret() as the
 * input of a recommended Key Derivation Function (see NIST SP 800-108) in
 * order to produce a cryptographically secure symmetric key.
 */
int uECC_shared_secret(const uint8_t *p_public_key, const uint8_t *p_private_key,
                       uint8_t *p_secret, uECC_Curve curve);

#ifdef __cplusplus
}
#endif

#endif /* __TC_ECC_DH_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ecc_dsa.h
================================================
/* ecc_dh.h - TinyCrypt interface to EC-DSA implementation */

/*
 * Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief -- Interface to EC-DSA implementation.
 *
 *  Overview: This software is an implementation of EC-DSA. This implementation
 *            uses curve NIST p-256.
 *
 *  Security: The curve NIST p-256 provides approximately 128 bits of security.
 *
 *  Usage:  - To sign: Compute a hash of the data you wish to sign (SHA-2 is
 *          recommended) and pass it in to ecdsa_sign function along with your
 *          private key and a random number. You must use a new non-predictable
 *          random number to generate each new signature.
 *          - To verify a signature: Compute the hash of the signed data using
 *          the same hash as the signer and pass it to this function along with
 *          the signer's public key and the signature values (r and s).
 */

#ifndef __TC_ECC_DSA_H__
#define __TC_ECC_DSA_H__

#include "ecc.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Generate an ECDSA signature for a given hash value.
 * @return returns TC_CRYPTO_SUCCESS (1) if the signature generated successfully
 *         returns TC_CRYPTO_FAIL (0) if an error occurred.
 *
 * @param p_private_key IN -- Your private key.
 * @param p_message_hash IN -- The hash of the message to sign.
 * @param p_hash_size IN -- The size of p_message_hash in bytes.
 * @param p_signature OUT -- Will be filled in with the signature value. Must be
 * at least 2 * curve size long (for secp256r1, signature must be 64 bytes long).
 *
 * @warning A cryptographically-secure PRNG function must be set (using
 * uECC_set_rng()) before calling uECC_sign().
 * @note Usage: Compute a hash of the data you wish to sign (SHA-2 is
 * recommended) and pass it in to this function along with your private key.
 * @note side-channel countermeasure: algorithm strengthened against timing
 * attack.
 */
int uECC_sign(const uint8_t *p_private_key, const uint8_t *p_message_hash,
              unsigned p_hash_size, uint8_t *p_signature, uECC_Curve curve);

#ifdef ENABLE_TESTS
/*
 * THIS FUNCTION SHOULD BE CALLED FOR TEST PURPOSES ONLY.
 * Refer to uECC_sign() function for real applications.
 */
int uECC_sign_with_k(const uint8_t *private_key, const uint8_t *message_hash,
                     unsigned int hash_size, uECC_word_t *k, uint8_t *signature,
                     uECC_Curve curve);
#endif

/**
 * @brief Verify an ECDSA signature.
 * @return returns TC_SUCCESS (1) if the signature is valid
 * 	   returns TC_FAIL (0) if the signature is invalid.
 *
 * @param p_public_key IN -- The signer's public key.
 * @param p_message_hash IN -- The hash of the signed data.
 * @param p_hash_size IN -- The size of p_message_hash in bytes.
 * @param p_signature IN -- The signature values.
 *
 * @note Usage: Compute the hash of the signed data using the same hash as the
 * signer and pass it to this function along with the signer's public key and
 * the signature values (hash_size and signature).
 */
int uECC_verify(const uint8_t *p_public_key, const uint8_t *p_message_hash,
                unsigned int p_hash_size, const uint8_t *p_signature, uECC_Curve curve);

#ifdef __cplusplus
}
#endif

#endif /* __TC_ECC_DSA_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/ecc_platform_specific.h
================================================
/*  uECC_platform_specific.h - Interface to platform specific functions*/

/* Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  * Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.*/

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 *  uECC_platform_specific.h -- Interface to platform specific functions
 */

#ifndef __UECC_PLATFORM_SPECIFIC_H_
#define __UECC_PLATFORM_SPECIFIC_H_

/*
 * The RNG function should fill 'size' random bytes into 'dest'. It should
 * return 1 if 'dest' was filled with random data, or 0 if the random data could
 * not be generated. The filled-in values should be either truly random, or from
 * a cryptographically-secure PRNG.
 *
 * A cryptographically-secure PRNG function must be set (using uECC_set_rng())
 * before calling uECC_make_key() or uECC_sign().
 *
 * Setting a cryptographically-secure PRNG function improves the resistance to
 * side-channel attacks for uECC_shared_secret().
 *
 * A correct PRNG function is set by default (default_RNG_defined = 1) and works
 * for some platforms, such as Unix and Linux. For other platforms, you may need
 * to provide another PRNG function.
*/
#define default_RNG_defined 1

int default_CSPRNG(uint8_t *dest, unsigned int size);

#endif /* __UECC_PLATFORM_SPECIFIC_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/hmac.h
================================================
/* hmac.h - TinyCrypt interface to an HMAC implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to an HMAC implementation.
 *
 *  Overview:   HMAC is a message authentication code based on hash functions.
 *              TinyCrypt hard codes SHA-256 as the hash function. A message
 *              authentication code based on hash functions is also called a
 *              keyed cryptographic hash function since it performs a
 *              transformation specified by a key in an arbitrary length data
 *              set into a fixed length data set (also called tag).
 *
 *  Security:   The security of the HMAC depends on the length of the key and
 *              on the security of the hash function. Note that HMAC primitives
 *              are much less affected by collision attacks than their
 *              corresponding hash functions.
 *
 *  Requires:   SHA-256
 *
 *  Usage:      1) call tc_hmac_set_key to set the HMAC key.
 *
 *              2) call tc_hmac_init to initialize a struct hash_state before
 *              processing the data.
 *
 *              3) call tc_hmac_update to process the next input segment;
 *              tc_hmac_update can be called as many times as needed to process
 *              all of the segments of the input; the order is important.
 *
 *              4) call tc_hmac_final to out put the tag.
 */

#ifndef __TC_HMAC_H__
#define __TC_HMAC_H__

#include "sha256.h"

#ifdef __cplusplus
extern "C" {
#endif

struct tc_hmac_state_struct {
    /* the internal state required by h */
    struct tc_sha256_state_struct hash_state;
    /* HMAC key schedule */
    uint8_t key[2 * TC_SHA256_BLOCK_SIZE];
};
typedef struct tc_hmac_state_struct *TCHmacState_t;

/**
 *  @brief HMAC set key procedure
 *  Configures ctx to use key
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if
 *                ctx == NULL or
 *                key == NULL or
 *                key_size == 0
 * @param ctx IN/OUT -- the struct tc_hmac_state_struct to initial
 * @param key IN -- the HMAC key to configure
 * @param key_size IN -- the HMAC key size
 */
int tc_hmac_set_key(TCHmacState_t ctx, const uint8_t *key,
                    unsigned int key_size);

/**
 * @brief HMAC init procedure
 * Initializes ctx to begin the next HMAC operation
 * @return returns TC_CRYPTO_SUCCESS (1)
 *         returns TC_CRYPTO_FAIL (0) if: ctx == NULL or key == NULL
 * @param ctx IN/OUT -- struct tc_hmac_state_struct buffer to init
 */
int tc_hmac_init(TCHmacState_t ctx);

/**
 *  @brief HMAC update procedure
 *  Mixes data_length bytes addressed by data into state
 *  @return returns TC_CRYPTO_SUCCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if: ctx == NULL or key == NULL
 *  @note Assumes state has been initialized by tc_hmac_init
 *  @param ctx IN/OUT -- state of HMAC computation so far
 *  @param data IN -- data to incorporate into state
 *  @param data_length IN -- size of data in bytes
 */
int tc_hmac_update(TCHmacState_t ctx, const void *data,
                   unsigned int data_length);

/**
 *  @brief HMAC final procedure
 *  Writes the HMAC tag into the tag buffer
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                tag == NULL or
 *                ctx == NULL or
 *                key == NULL or
 *                taglen != TC_SHA256_DIGEST_SIZE
 *  @note ctx is erased before exiting. This should never be changed/removed.
 *  @note Assumes the tag bufer is at least sizeof(hmac_tag_size(state)) bytes
 *  state has been initialized by tc_hmac_init
 *  @param tag IN/OUT -- buffer to receive computed HMAC tag
 *  @param taglen IN -- size of tag in bytes
 *  @param ctx IN/OUT -- the HMAC state for computing tag
 */
int tc_hmac_final(uint8_t *tag, unsigned int taglen, TCHmacState_t ctx);

#ifdef __cplusplus
}
#endif

#endif /*__TC_HMAC_H__*/


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/hmac_prng.h
================================================
/* hmac_prng.h - TinyCrypt interface to an HMAC-PRNG implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to an HMAC-PRNG implementation.
 *
 *  Overview:   A pseudo-random number generator (PRNG) generates a sequence
 *              of numbers that have a distribution close to the one expected
 *              for a sequence of truly random numbers. The NIST Special
 *              Publication 800-90A specifies several mechanisms to generate
 *              sequences of pseudo random numbers, including the HMAC-PRNG one
 *              which is based on HMAC. TinyCrypt implements HMAC-PRNG with
 *              certain modifications from the NIST SP 800-90A spec.
 *
 *  Security:   A cryptographically secure PRNG depends on the existence of an
 *              entropy source to provide a truly random seed as well as the
 *              security of the primitives used as the building blocks (HMAC and
 *              SHA256, for TinyCrypt).
 *
 *              The NIST SP 800-90A standard tolerates a null personalization,
 *              while TinyCrypt requires a non-null personalization. This is
 *              because a personalization string (the host name concatenated
 *              with a time stamp, for example) is easily computed and might be
 *              the last line of defense against failure of the entropy source.
 *
 *  Requires:   - SHA-256
 *              - HMAC
 *
 *  Usage:      1) call tc_hmac_prng_init to set the HMAC key and process the
 *              personalization data.
 *
 *              2) call tc_hmac_prng_reseed to process the seed and additional
 *              input.
 *
 *              3) call tc_hmac_prng_generate to out put the pseudo-random data.
 */

#ifndef __TC_HMAC_PRNG_H__
#define __TC_HMAC_PRNG_H__

#include "sha256.h"
#include "hmac.h"

#ifdef __cplusplus
extern "C" {
#endif

#define TC_HMAC_PRNG_RESEED_REQ -1

struct tc_hmac_prng_struct {
    /* the HMAC instance for this PRNG */
    struct tc_hmac_state_struct h;
    /* the PRNG key */
    uint8_t key[TC_SHA256_DIGEST_SIZE];
    /* PRNG state */
    uint8_t v[TC_SHA256_DIGEST_SIZE];
    /* calls to tc_hmac_prng_generate left before re-seed */
    unsigned int countdown;
};

typedef struct tc_hmac_prng_struct *TCHmacPrng_t;

/**
 *  @brief HMAC-PRNG initialization procedure
 *  Initializes prng with personalization, disables tc_hmac_prng_generate
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                prng == NULL,
 *                personalization == NULL,
 *                plen > MAX_PLEN
 *  @note Assumes: - personalization != NULL.
 *              The personalization is a platform unique string (e.g., the host
 *              name) and is the last line of defense against failure of the
 *              entropy source
 *  @warning    NIST SP 800-90A specifies 3 items as seed material during
 *              initialization: entropy seed, personalization, and an optional
 *              nonce. TinyCrypts requires instead a non-null personalization
 *              (which is easily computed) and indirectly requires an entropy
 *              seed (since the reseed function is mandatorily called after
 *              init)
 *  @param prng IN/OUT -- the PRNG state to initialize
 *  @param personalization IN -- personalization string
 *  @param plen IN -- personalization length in bytes
 */
int tc_hmac_prng_init(TCHmacPrng_t prng,
                      const uint8_t *personalization,
                      unsigned int plen);

/**
 *  @brief HMAC-PRNG reseed procedure
 *  Mixes seed into prng, enables tc_hmac_prng_generate
 *  @return returns  TC_CRYPTO_SUCCESS (1)
 *  	    returns TC_CRYPTO_FAIL (0) if:
 *          prng == NULL,
 *          seed == NULL,
 *          seedlen < MIN_SLEN,
 *          seendlen > MAX_SLEN,
 *          additional_input != (const uint8_t *) 0 && additionallen == 0,
 *          additional_input != (const uint8_t *) 0 && additionallen > MAX_ALEN
 *  @note Assumes:- tc_hmac_prng_init has been called for prng
 *              - seed has sufficient entropy.
 *
 *  @param prng IN/OUT -- the PRNG state
 *  @param seed IN -- entropy to mix into the prng
 *  @param seedlen IN -- length of seed in bytes
 *  @param additional_input IN -- additional input to the prng
 *  @param additionallen IN -- additional input length in bytes
 */
int tc_hmac_prng_reseed(TCHmacPrng_t prng, const uint8_t *seed,
                        unsigned int seedlen, const uint8_t *additional_input,
                        unsigned int additionallen);

/**
 *  @brief HMAC-PRNG generate procedure
 *  Generates outlen pseudo-random bytes into out buffer, updates prng
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_HMAC_PRNG_RESEED_REQ (-1) if a reseed is needed
 *          returns TC_CRYPTO_FAIL (0) if:
 *                out == NULL,
 *                prng == NULL,
 *                outlen == 0,
 *                outlen >= MAX_OUT
 *  @note Assumes tc_hmac_prng_init has been called for prng
 *  @param out IN/OUT -- buffer to receive output
 *  @param outlen IN -- size of out buffer in bytes
 *  @param prng IN/OUT -- the PRNG state
 */
int tc_hmac_prng_generate(uint8_t *out, unsigned int outlen, TCHmacPrng_t prng);

#ifdef __cplusplus
}
#endif

#endif /* __TC_HMAC_PRNG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/sha256.h
================================================
/* sha256.h - TinyCrypt interface to a SHA-256 implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to a SHA-256 implementation.
 *
 *  Overview:   SHA-256 is a NIST approved cryptographic hashing algorithm
 *              specified in FIPS 180. A hash algorithm maps data of arbitrary
 *              size to data of fixed length.
 *
 *  Security:   SHA-256 provides 128 bits of security against collision attacks
 *              and 256 bits of security against pre-image attacks. SHA-256 does
 *              NOT behave like a random oracle, but it can be used as one if
 *              the string being hashed is prefix-free encoded before hashing.
 *
 *  Usage:      1) call tc_sha256_init to initialize a struct
 *              tc_sha256_state_struct before hashing a new string.
 *
 *              2) call tc_sha256_update to hash the next string segment;
 *              tc_sha256_update can be called as many times as needed to hash
 *              all of the segments of a string; the order is important.
 *
 *              3) call tc_sha256_final to out put the digest from a hashing
 *              operation.
 */

#ifndef __TC_SHA256_H__
#define __TC_SHA256_H__

#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif

#define TC_SHA256_BLOCK_SIZE   (64)
#define TC_SHA256_DIGEST_SIZE  (32)
#define TC_SHA256_STATE_BLOCKS (TC_SHA256_DIGEST_SIZE / 4)

struct tc_sha256_state_struct {
    unsigned int iv[TC_SHA256_STATE_BLOCKS];
    uint64_t bits_hashed;
    uint8_t leftover[TC_SHA256_BLOCK_SIZE];
    size_t leftover_offset;
};

typedef struct tc_sha256_state_struct *TCSha256State_t;

/**
 *  @brief SHA256 initialization procedure
 *  Initializes s
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if s == NULL
 *  @param s Sha256 state struct
 */
int tc_sha256_init(TCSha256State_t s);

/**
 *  @brief SHA256 update procedure
 *  Hashes data_length bytes addressed by data into state s
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                s == NULL,
 *                s->iv == NULL,
 *                data == NULL
 *  @note Assumes s has been initialized by tc_sha256_init
 *  @warning The state buffer 'leftover' is left in memory after processing
 *           If your application intends to have sensitive data in this
 *           buffer, remind to erase it after the data has been processed
 *  @param s Sha256 state struct
 *  @param data message to hash
 *  @param datalen length of message to hash
 */
int tc_sha256_update(TCSha256State_t s, const uint8_t *data, size_t datalen);

/**
 *  @brief SHA256 final procedure
 *  Inserts the completed hash computation into digest
 *  @return returns TC_CRYPTO_SUCCESS (1)
 *          returns TC_CRYPTO_FAIL (0) if:
 *                s == NULL,
 *                s->iv == NULL,
 *                digest == NULL
 *  @note Assumes: s has been initialized by tc_sha256_init
 *        digest points to at least TC_SHA256_DIGEST_SIZE bytes
 *  @warning The state buffer 'leftover' is left in memory after processing
 *           If your application intends to have sensitive data in this
 *           buffer, remind to erase it after the data has been processed
 *  @param digest unsigned eight bit integer
 *  @param Sha256 state struct
 */
int tc_sha256_final(uint8_t *digest, TCSha256State_t s);

#ifdef __cplusplus
}
#endif

#endif /* __TC_SHA256_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/include/tinycrypt/utils.h
================================================
/* utils.h - TinyCrypt interface to platform-dependent run-time operations */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

/**
 * @file
 * @brief Interface to platform-dependent run-time operations.
 *
 */

#ifndef __TC_UTILS_H__
#define __TC_UTILS_H__

#include 
#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Copy the the buffer 'from' to the buffer 'to'.
 * @return returns TC_CRYPTO_SUCCESS (1)
 *         returns TC_CRYPTO_FAIL (0) if:
 *                from_len > to_len.
 *
 * @param to OUT -- destination buffer
 * @param to_len IN -- length of destination buffer
 * @param from IN -- origin buffer
 * @param from_len IN -- length of origin buffer
 */
unsigned int _copy(uint8_t *to, unsigned int to_len,
                   const uint8_t *from, unsigned int from_len);

/**
 * @brief Set the value 'val' into the buffer 'to', 'len' times.
 *
 * @param to OUT -- destination buffer
 * @param val IN -- value to be set in 'to'
 * @param len IN -- number of times the value will be copied
 */
void _set(void *to, uint8_t val, unsigned int len);

/**
 * @brief Set the value 'val' into the buffer 'to', 'len' times, in a way
 *         which does not risk getting optimized out by the compiler
 *        In cases where the compiler does not set __GNUC__ and where the
 *         optimization level removes the memset, it may be necessary to
 *         implement a _set_secure function and define the
 *         TINYCRYPT_ARCH_HAS_SET_SECURE, which then can ensure that the
 *         memset does not get optimized out.
 *
 * @param to OUT -- destination buffer
 * @param val IN -- value to be set in 'to'
 * @param len IN -- number of times the value will be copied
 */
#ifdef TINYCRYPT_ARCH_HAS_SET_SECURE
extern void _set_secure(void *to, uint8_t val, unsigned int len);
#else /* ! TINYCRYPT_ARCH_HAS_SET_SECURE */
static inline void _set_secure(void *to, uint8_t val, unsigned int len)
{
    (void)memset(to, val, len);
#ifdef __GNUC__
    __asm__ __volatile__("" ::"g"(to)
                         : "memory");
#endif /* __GNUC__ */
}
#endif /* TINYCRYPT_ARCH_HAS_SET_SECURE */

/*
 * @brief AES specific doubling function, which utilizes
 * the finite field used by AES.
 * @return Returns a^2
 *
 * @param a IN/OUT -- value to be doubled
 */
uint8_t _double_byte(uint8_t a);

/*
 * @brief Constant-time algorithm to compare if two sequences of bytes are equal
 * @return Returns 0 if equal, and non-zero otherwise
 *
 * @param a IN -- sequence of bytes a
 * @param b IN -- sequence of bytes b
 * @param size IN -- size of sequences a and b
 */
int _compare(const uint8_t *a, const uint8_t *b, size_t size);

#ifdef __cplusplus
}
#endif

#endif /* __TC_UTILS_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/aes_decrypt.c
================================================
/* aes_decrypt.c - TinyCrypt implementation of AES decryption procedure */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include 
#include 
#include 

static const uint8_t inv_sbox[256] = {
    0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
    0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
    0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
    0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
    0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
    0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
    0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
    0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};

int tc_aes128_set_decrypt_key(TCAesKeySched_t s, const uint8_t *k) { return tc_aes128_set_encrypt_key(s, k); }

#define mult8(a) (_double_byte(_double_byte(_double_byte(a))))
#define mult9(a) (mult8(a) ^ (a))
#define multb(a) (mult8(a) ^ _double_byte(a) ^ (a))
#define multd(a) (mult8(a) ^ _double_byte(_double_byte(a)) ^ (a))
#define multe(a) (mult8(a) ^ _double_byte(_double_byte(a)) ^ _double_byte(a))

static inline void mult_row_column(uint8_t *out, const uint8_t *in) {
  out[0] = multe(in[0]) ^ multb(in[1]) ^ multd(in[2]) ^ mult9(in[3]);
  out[1] = mult9(in[0]) ^ multe(in[1]) ^ multb(in[2]) ^ multd(in[3]);
  out[2] = multd(in[0]) ^ mult9(in[1]) ^ multe(in[2]) ^ multb(in[3]);
  out[3] = multb(in[0]) ^ multd(in[1]) ^ mult9(in[2]) ^ multe(in[3]);
}

static inline void inv_mix_columns(uint8_t *s) {
  uint8_t t[Nb * Nk];

  mult_row_column(t, s);
  mult_row_column(&t[Nb], s + Nb);
  mult_row_column(&t[2 * Nb], s + (2 * Nb));
  mult_row_column(&t[3 * Nb], s + (3 * Nb));
  (void)_copy(s, sizeof(t), t, sizeof(t));
}

static inline void add_round_key(uint8_t *s, const unsigned int *k) {
  s[0] ^= (uint8_t)(k[0] >> 24);
  s[1] ^= (uint8_t)(k[0] >> 16);
  s[2] ^= (uint8_t)(k[0] >> 8);
  s[3] ^= (uint8_t)(k[0]);
  s[4] ^= (uint8_t)(k[1] >> 24);
  s[5] ^= (uint8_t)(k[1] >> 16);
  s[6] ^= (uint8_t)(k[1] >> 8);
  s[7] ^= (uint8_t)(k[1]);
  s[8] ^= (uint8_t)(k[2] >> 24);
  s[9] ^= (uint8_t)(k[2] >> 16);
  s[10] ^= (uint8_t)(k[2] >> 8);
  s[11] ^= (uint8_t)(k[2]);
  s[12] ^= (uint8_t)(k[3] >> 24);
  s[13] ^= (uint8_t)(k[3] >> 16);
  s[14] ^= (uint8_t)(k[3] >> 8);
  s[15] ^= (uint8_t)(k[3]);
}

static inline void inv_sub_bytes(uint8_t *s) {
  unsigned int i;

  for (i = 0; i < (Nb * Nk); ++i) {
    s[i] = inv_sbox[s[i]];
  }
}

/*
 * This inv_shift_rows also implements the matrix flip required for
 * inv_mix_columns, but performs it here to reduce the number of memory
 * operations.
 */
static inline void inv_shift_rows(uint8_t *s) {
  uint8_t t[Nb * Nk];

  t[0]  = s[0];
  t[1]  = s[13];
  t[2]  = s[10];
  t[3]  = s[7];
  t[4]  = s[4];
  t[5]  = s[1];
  t[6]  = s[14];
  t[7]  = s[11];
  t[8]  = s[8];
  t[9]  = s[5];
  t[10] = s[2];
  t[11] = s[15];
  t[12] = s[12];
  t[13] = s[9];
  t[14] = s[6];
  t[15] = s[3];
  (void)_copy(s, sizeof(t), t, sizeof(t));
}

int tc_aes_decrypt(uint8_t *out, const uint8_t *in, const TCAesKeySched_t s) {
  uint8_t      state[Nk * Nb];
  unsigned int i;

  if (out == (uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  } else if (in == (const uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  } else if (s == (TCAesKeySched_t)0) {
    return TC_CRYPTO_FAIL;
  }

  (void)_copy(state, sizeof(state), in, sizeof(state));

  add_round_key(state, s->words + Nb * Nr);

  for (i = Nr - 1; i > 0; --i) {
    inv_shift_rows(state);
    inv_sub_bytes(state);
    add_round_key(state, s->words + Nb * i);
    inv_mix_columns(state);
  }

  inv_shift_rows(state);
  inv_sub_bytes(state);
  add_round_key(state, s->words);

  (void)_copy(out, sizeof(state), state, sizeof(state));

  /*zeroing out the state buffer */
  _set(state, TC_ZERO_BYTE, sizeof(state));

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/aes_encrypt.c
================================================
/* aes_encrypt.c - TinyCrypt implementation of AES encryption procedure */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "aes.h"
#include "constants.h"
#include "utils.h"

static const uint8_t sbox[256] = {
    0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
    0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
    0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
    0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
    0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
    0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
    0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
    0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};

static inline unsigned int rotword(unsigned int a) { return (((a) >> 24) | ((a) << 8)); }

#define subbyte(a, o) (sbox[((a) >> (o)) & 0xff] << (o))
#define subword(a)    (subbyte(a, 24) | subbyte(a, 16) | subbyte(a, 8) | subbyte(a, 0))

int tc_aes128_set_encrypt_key(TCAesKeySched_t s, const uint8_t *k) {
  const unsigned int rconst[11] = {0x00000000, 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000, 0x1b000000, 0x36000000};
  unsigned int       i;
  unsigned int       t;

  if (s == (TCAesKeySched_t)0) {
    return TC_CRYPTO_FAIL;
  } else if (k == (const uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  }

  for (i = 0; i < Nk; ++i) {
    s->words[i] = (k[Nb * i] << 24) | (k[Nb * i + 1] << 16) | (k[Nb * i + 2] << 8) | (k[Nb * i + 3]);
  }

  for (; i < (Nb * (Nr + 1)); ++i) {
    t = s->words[i - 1];
    if ((i % Nk) == 0) {
      t = subword(rotword(t)) ^ rconst[i / Nk];
    }
    s->words[i] = s->words[i - Nk] ^ t;
  }

  return TC_CRYPTO_SUCCESS;
}

static inline void add_round_key(uint8_t *s, const unsigned int *k) {
  s[0] ^= (uint8_t)(k[0] >> 24);
  s[1] ^= (uint8_t)(k[0] >> 16);
  s[2] ^= (uint8_t)(k[0] >> 8);
  s[3] ^= (uint8_t)(k[0]);
  s[4] ^= (uint8_t)(k[1] >> 24);
  s[5] ^= (uint8_t)(k[1] >> 16);
  s[6] ^= (uint8_t)(k[1] >> 8);
  s[7] ^= (uint8_t)(k[1]);
  s[8] ^= (uint8_t)(k[2] >> 24);
  s[9] ^= (uint8_t)(k[2] >> 16);
  s[10] ^= (uint8_t)(k[2] >> 8);
  s[11] ^= (uint8_t)(k[2]);
  s[12] ^= (uint8_t)(k[3] >> 24);
  s[13] ^= (uint8_t)(k[3] >> 16);
  s[14] ^= (uint8_t)(k[3] >> 8);
  s[15] ^= (uint8_t)(k[3]);
}

static inline void sub_bytes(uint8_t *s) {
  unsigned int i;

  for (i = 0; i < (Nb * Nk); ++i) {
    s[i] = sbox[s[i]];
  }
}

#define triple(a) (_double_byte(a) ^ (a))

static inline void mult_row_column(uint8_t *out, const uint8_t *in) {
  out[0] = _double_byte(in[0]) ^ triple(in[1]) ^ in[2] ^ in[3];
  out[1] = in[0] ^ _double_byte(in[1]) ^ triple(in[2]) ^ in[3];
  out[2] = in[0] ^ in[1] ^ _double_byte(in[2]) ^ triple(in[3]);
  out[3] = triple(in[0]) ^ in[1] ^ in[2] ^ _double_byte(in[3]);
}

static inline void mix_columns(uint8_t *s) {
  uint8_t t[Nb * Nk];

  mult_row_column(t, s);
  mult_row_column(&t[Nb], s + Nb);
  mult_row_column(&t[2 * Nb], s + (2 * Nb));
  mult_row_column(&t[3 * Nb], s + (3 * Nb));
  (void)_copy(s, sizeof(t), t, sizeof(t));
}

/*
 * This shift_rows also implements the matrix flip required for mix_columns, but
 * performs it here to reduce the number of memory operations.
 */
static inline void shift_rows(uint8_t *s) {
  uint8_t t[Nb * Nk];

  t[0]  = s[0];
  t[1]  = s[5];
  t[2]  = s[10];
  t[3]  = s[15];
  t[4]  = s[4];
  t[5]  = s[9];
  t[6]  = s[14];
  t[7]  = s[3];
  t[8]  = s[8];
  t[9]  = s[13];
  t[10] = s[2];
  t[11] = s[7];
  t[12] = s[12];
  t[13] = s[1];
  t[14] = s[6];
  t[15] = s[11];
  (void)_copy(s, sizeof(t), t, sizeof(t));
}

int tc_aes_encrypt(uint8_t *out, const uint8_t *in, const TCAesKeySched_t s) {
  uint8_t      state[Nk * Nb];
  unsigned int i;

  if (out == (uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  } else if (in == (const uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  } else if (s == (TCAesKeySched_t)0) {
    return TC_CRYPTO_FAIL;
  }

  (void)_copy(state, sizeof(state), in, sizeof(state));
  add_round_key(state, s->words);

  for (i = 0; i < (Nr - 1); ++i) {
    sub_bytes(state);
    shift_rows(state);
    mix_columns(state);
    add_round_key(state, s->words + Nb * (i + 1));
  }

  sub_bytes(state);
  shift_rows(state);
  add_round_key(state, s->words + Nb * (i + 1));

  (void)_copy(out, sizeof(state), state, sizeof(state));

  /* zeroing out the state buffer */
  _set(state, TC_ZERO_BYTE, sizeof(state));

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/cbc_mode.c
================================================
/* cbc_mode.c - TinyCrypt implementation of CBC mode encryption & decryption */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "cbc_mode.h"
#include "constants.h"
#include "utils.h"

int tc_cbc_mode_encrypt(uint8_t *out, unsigned int outlen, const uint8_t *in, unsigned int inlen, const uint8_t *iv, const TCAesKeySched_t sched) {
  uint8_t      buffer[TC_AES_BLOCK_SIZE];
  unsigned int n, m;

  /* input sanity check: */
  if (out == (uint8_t *)0 || in == (const uint8_t *)0 || sched == (TCAesKeySched_t)0 || inlen == 0 || outlen == 0 || (inlen % TC_AES_BLOCK_SIZE) != 0 || (outlen % TC_AES_BLOCK_SIZE) != 0 ||
      outlen != inlen + TC_AES_BLOCK_SIZE) {
    return TC_CRYPTO_FAIL;
  }

  /* copy iv to the buffer */
  (void)_copy(buffer, TC_AES_BLOCK_SIZE, iv, TC_AES_BLOCK_SIZE);
  /* copy iv to the output buffer */
  (void)_copy(out, TC_AES_BLOCK_SIZE, iv, TC_AES_BLOCK_SIZE);
  out += TC_AES_BLOCK_SIZE;

  for (n = m = 0; n < inlen; ++n) {
    buffer[m++] ^= *in++;
    if (m == TC_AES_BLOCK_SIZE) {
      (void)tc_aes_encrypt(buffer, buffer, sched);
      (void)_copy(out, TC_AES_BLOCK_SIZE, buffer, TC_AES_BLOCK_SIZE);
      out += TC_AES_BLOCK_SIZE;
      m = 0;
    }
  }

  return TC_CRYPTO_SUCCESS;
}

int tc_cbc_mode_decrypt(uint8_t *out, unsigned int outlen, const uint8_t *in, unsigned int inlen, const uint8_t *iv, const TCAesKeySched_t sched) {
  uint8_t        buffer[TC_AES_BLOCK_SIZE];
  const uint8_t *p;
  unsigned int   n, m;

  /* sanity check the inputs */
  if (out == (uint8_t *)0 || in == (const uint8_t *)0 || sched == (TCAesKeySched_t)0 || inlen == 0 || outlen == 0 || (inlen % TC_AES_BLOCK_SIZE) != 0 || (outlen % TC_AES_BLOCK_SIZE) != 0 ||
      outlen != inlen) {
    return TC_CRYPTO_FAIL;
  }

  /*
   * Note that in == iv + ciphertext, i.e. the iv and the ciphertext are
   * contiguous. This allows for a very efficient decryption algorithm
   * that would not otherwise be possible.
   */
  p = iv;
  for (n = m = 0; n < outlen; ++n) {
    if ((n % TC_AES_BLOCK_SIZE) == 0) {
      (void)tc_aes_decrypt(buffer, in, sched);
      in += TC_AES_BLOCK_SIZE;
      m = 0;
    }
    *out++ = buffer[m++] ^ *p++;
  }

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ccm_mode.c
================================================
/* ccm_mode.c - TinyCrypt implementation of CCM mode */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "ccm_mode.h"
#include "constants.h"
#include "utils.h"

#include 

int tc_ccm_config(TCCcmMode_t c, TCAesKeySched_t sched, uint8_t *nonce, unsigned int nlen, unsigned int mlen) {
  /* input sanity check: */
  if (c == (TCCcmMode_t)0 || sched == (TCAesKeySched_t)0 || nonce == (uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  } else if (nlen != 13) {
    return TC_CRYPTO_FAIL; /* The allowed nonce size is: 13. See documentation.*/
  } else if ((mlen < 4) || (mlen > 16) || (mlen & 1)) {
    return TC_CRYPTO_FAIL; /* The allowed mac sizes are: 4, 6, 8, 10, 12, 14, 16.*/
  }

  c->mlen  = mlen;
  c->sched = sched;
  c->nonce = nonce;

  return TC_CRYPTO_SUCCESS;
}

/**
 * Variation of CBC-MAC mode used in CCM.
 */
static void ccm_cbc_mac(uint8_t *T, const uint8_t *data, unsigned int dlen, unsigned int flag, TCAesKeySched_t sched) {
  unsigned int i;

  if (flag > 0) {
    T[0] ^= (uint8_t)(dlen >> 8);
    T[1] ^= (uint8_t)(dlen);
    dlen += 2;
    i = 2;
  } else {
    i = 0;
  }

  while (i < dlen) {
    T[i++ % (Nb * Nk)] ^= *data++;
    if (((i % (Nb * Nk)) == 0) || dlen == i) {
      (void)tc_aes_encrypt(T, T, sched);
    }
  }
}

/**
 * Variation of CTR mode used in CCM.
 * The CTR mode used by CCM is slightly different than the conventional CTR
 * mode (the counter is increased before encryption, instead of after
 * encryption). Besides, it is assumed that the counter is stored in the last
 * 2 bytes of the nonce.
 */
static int ccm_ctr_mode(uint8_t *out, unsigned int outlen, const uint8_t *in, unsigned int inlen, uint8_t *ctr, const TCAesKeySched_t sched) {
  uint8_t      buffer[TC_AES_BLOCK_SIZE];
  uint8_t      nonce[TC_AES_BLOCK_SIZE];
  uint16_t     block_num;
  unsigned int i;

  /* input sanity check: */
  if (out == (uint8_t *)0 || in == (uint8_t *)0 || ctr == (uint8_t *)0 || sched == (TCAesKeySched_t)0 || inlen == 0 || outlen == 0 || outlen != inlen) {
    return TC_CRYPTO_FAIL;
  }

  /* copy the counter to the nonce */
  (void)_copy(nonce, sizeof(nonce), ctr, sizeof(nonce));

  /* select the last 2 bytes of the nonce to be incremented */
  block_num = (uint16_t)((nonce[14] << 8) | (nonce[15]));
  for (i = 0; i < inlen; ++i) {
    if ((i % (TC_AES_BLOCK_SIZE)) == 0) {
      block_num++;
      nonce[14] = (uint8_t)(block_num >> 8);
      nonce[15] = (uint8_t)(block_num);
      if (!tc_aes_encrypt(buffer, nonce, sched)) {
        return TC_CRYPTO_FAIL;
      }
    }
    /* update the output */
    *out++ = buffer[i % (TC_AES_BLOCK_SIZE)] ^ *in++;
  }

  /* update the counter */
  ctr[14] = nonce[14];
  ctr[15] = nonce[15];

  return TC_CRYPTO_SUCCESS;
}

int tc_ccm_generation_encryption(uint8_t *out, unsigned int olen, const uint8_t *associated_data, unsigned int alen, const uint8_t *payload, unsigned int plen, TCCcmMode_t c) {
  /* input sanity check: */
  if ((out == (uint8_t *)0) || (c == (TCCcmMode_t)0) || ((plen > 0) && (payload == (uint8_t *)0)) || ((alen > 0) && (associated_data == (uint8_t *)0)) ||
      (alen >= TC_CCM_AAD_MAX_BYTES) ||     /* associated data size unsupported */
      (plen >= TC_CCM_PAYLOAD_MAX_BYTES) || /* payload size unsupported */
      (olen < (plen + c->mlen))) {          /* invalid output buffer size */
    return TC_CRYPTO_FAIL;
  }

  uint8_t      b[Nb * Nk];
  uint8_t      tag[Nb * Nk];
  unsigned int i;

  /* GENERATING THE AUTHENTICATION TAG: */

  /* formatting the sequence b for authentication: */
  b[0] = ((alen > 0) ? 0x40 : 0) | (((c->mlen - 2) / 2 << 3)) | (1);
  for (i = 1; i <= 13; ++i) {
    b[i] = c->nonce[i - 1];
  }
  b[14] = (uint8_t)(plen >> 8);
  b[15] = (uint8_t)(plen);

  /* computing the authentication tag using cbc-mac: */
  (void)tc_aes_encrypt(tag, b, c->sched);
  if (alen > 0) {
    ccm_cbc_mac(tag, associated_data, alen, 1, c->sched);
  }
  if (plen > 0) {
    ccm_cbc_mac(tag, payload, plen, 0, c->sched);
  }

  /* ENCRYPTION: */

  /* formatting the sequence b for encryption: */
  b[0]  = 1; /* q - 1 = 2 - 1 = 1 */
  b[14] = b[15] = TC_ZERO_BYTE;

  /* encrypting payload using ctr mode: */
  ccm_ctr_mode(out, plen, payload, plen, b, c->sched);

  b[14] = b[15] = TC_ZERO_BYTE; /* restoring initial counter for ctr_mode (0):*/

  /* encrypting b and adding the tag to the output: */
  (void)tc_aes_encrypt(b, b, c->sched);
  out += plen;
  for (i = 0; i < c->mlen; ++i) {
    *out++ = tag[i] ^ b[i];
  }

  return TC_CRYPTO_SUCCESS;
}

int tc_ccm_decryption_verification(uint8_t *out, unsigned int olen, const uint8_t *associated_data, unsigned int alen, const uint8_t *payload, unsigned int plen, TCCcmMode_t c) {
  /* input sanity check: */
  if ((out == (uint8_t *)0) || (c == (TCCcmMode_t)0) || ((plen > 0) && (payload == (uint8_t *)0)) || ((alen > 0) && (associated_data == (uint8_t *)0)) ||
      (alen >= TC_CCM_AAD_MAX_BYTES) ||     /* associated data size unsupported */
      (plen >= TC_CCM_PAYLOAD_MAX_BYTES) || /* payload size unsupported */
      (olen < plen - c->mlen)) {            /* invalid output buffer size */
    return TC_CRYPTO_FAIL;
  }

  uint8_t      b[Nb * Nk];
  uint8_t      tag[Nb * Nk];
  unsigned int i;

  /* DECRYPTION: */

  /* formatting the sequence b for decryption: */
  b[0] = 1; /* q - 1 = 2 - 1 = 1 */
  for (i = 1; i < 14; ++i) {
    b[i] = c->nonce[i - 1];
  }
  b[14] = b[15] = TC_ZERO_BYTE; /* initial counter value is 0 */

  /* decrypting payload using ctr mode: */
  ccm_ctr_mode(out, plen - c->mlen, payload, plen - c->mlen, b, c->sched);

  b[14] = b[15] = TC_ZERO_BYTE; /* restoring initial counter value (0) */

  /* encrypting b and restoring the tag from input: */
  (void)tc_aes_encrypt(b, b, c->sched);
  for (i = 0; i < c->mlen; ++i) {
    tag[i] = *(payload + plen - c->mlen + i) ^ b[i];
  }

  /* VERIFYING THE AUTHENTICATION TAG: */

  /* formatting the sequence b for authentication: */
  b[0] = ((alen > 0) ? 0x40 : 0) | (((c->mlen - 2) / 2 << 3)) | (1);
  for (i = 1; i < 14; ++i) {
    b[i] = c->nonce[i - 1];
  }
  b[14] = (uint8_t)((plen - c->mlen) >> 8);
  b[15] = (uint8_t)(plen - c->mlen);

  /* computing the authentication tag using cbc-mac: */
  (void)tc_aes_encrypt(b, b, c->sched);
  if (alen > 0) {
    ccm_cbc_mac(b, associated_data, alen, 1, c->sched);
  }
  if (plen > 0) {
    ccm_cbc_mac(b, out, plen - c->mlen, 0, c->sched);
  }

  /* comparing the received tag and the computed one: */
  if (_compare(b, tag, c->mlen) == 0) {
    return TC_CRYPTO_SUCCESS;
  } else {
    /* erase the decrypted buffer in case of mac validation failure: */
    _set(out, 0, plen - c->mlen);
    return TC_CRYPTO_FAIL;
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/cmac_mode.c
================================================
/* cmac_mode.c - TinyCrypt CMAC mode implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "cmac_mode.h"
#include "aes.h"
#include "constants.h"
#include "utils.h"

/* max number of calls until change the key (2^48).*/
static const uint64_t MAX_CALLS = ((uint64_t)1 << 48);

/*
 *  gf_wrap -- In our implementation, GF(2^128) is represented as a 16 byte
 *  array with byte 0 the most significant and byte 15 the least significant.
 *  High bit carry reduction is based on the primitive polynomial
 *
 *                     X^128 + X^7 + X^2 + X + 1,
 *
 *  which leads to the reduction formula X^128 = X^7 + X^2 + X + 1. Indeed,
 *  since 0 = (X^128 + X^7 + X^2 + 1) mod (X^128 + X^7 + X^2 + X + 1) and since
 *  addition of polynomials with coefficients in Z/Z(2) is just XOR, we can
 *  add X^128 to both sides to get
 *
 *       X^128 = (X^7 + X^2 + X + 1) mod (X^128 + X^7 + X^2 + X + 1)
 *
 *  and the coefficients of the polynomial on the right hand side form the
 *  string 1000 0111 = 0x87, which is the value of gf_wrap.
 *
 *  This gets used in the following way. Doubling in GF(2^128) is just a left
 *  shift by 1 bit, except when the most significant bit is 1. In the latter
 *  case, the relation X^128 = X^7 + X^2 + X + 1 says that the high order bit
 *  that overflows beyond 128 bits can be replaced by addition of
 *  X^7 + X^2 + X + 1 <--> 0x87 to the low order 128 bits. Since addition
 *  in GF(2^128) is represented by XOR, we therefore only have to XOR 0x87
 *  into the low order byte after a left shift when the starting high order
 *  bit is 1.
 */
const unsigned char gf_wrap = 0x87;

/*
 *  assumes: out != NULL and points to a GF(2^n) value to receive the
 *            doubled value;
 *           in != NULL and points to a 16 byte GF(2^n) value
 *            to double;
 *           the in and out buffers do not overlap.
 *  effects: doubles the GF(2^n) value pointed to by "in" and places
 *           the result in the GF(2^n) value pointed to by "out."
 */
void gf_double(uint8_t *out, uint8_t *in) {
  /* start with low order byte */
  uint8_t *x = in + (TC_AES_BLOCK_SIZE - 1);

  /* if msb == 1, we need to add the gf_wrap value, otherwise add 0 */
  uint8_t carry = (in[0] >> 7) ? gf_wrap : 0;

  out += (TC_AES_BLOCK_SIZE - 1);
  for (;;) {
    *out-- = (*x << 1) ^ carry;
    if (x == in) {
      break;
    }
    carry = *x-- >> 7;
  }
}

int tc_cmac_setup(TCCmacState_t s, const uint8_t *key, TCAesKeySched_t sched) {
  /* input sanity check: */
  if (s == (TCCmacState_t)0 || key == (const uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  }

  /* put s into a known state */
  _set(s, 0, sizeof(*s));
  s->sched = sched;

  /* configure the encryption key used by the underlying block cipher */
  tc_aes128_set_encrypt_key(s->sched, key);

  /* compute s->K1 and s->K2 from s->iv using s->keyid */
  _set(s->iv, 0, TC_AES_BLOCK_SIZE);
  tc_aes_encrypt(s->iv, s->iv, s->sched);
  gf_double(s->K1, s->iv);
  gf_double(s->K2, s->K1);

  /* reset s->iv to 0 in case someone wants to compute now */
  tc_cmac_init(s);

  return TC_CRYPTO_SUCCESS;
}

int tc_cmac_erase(TCCmacState_t s) {
  if (s == (TCCmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  /* destroy the current state */
  _set(s, 0, sizeof(*s));

  return TC_CRYPTO_SUCCESS;
}

int tc_cmac_init(TCCmacState_t s) {
  /* input sanity check: */
  if (s == (TCCmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  /* CMAC starts with an all zero initialization vector */
  _set(s->iv, 0, TC_AES_BLOCK_SIZE);

  /* and the leftover buffer is empty */
  _set(s->leftover, 0, TC_AES_BLOCK_SIZE);
  s->leftover_offset = 0;

  /* Set countdown to max number of calls allowed before re-keying: */
  s->countdown = MAX_CALLS;

  return TC_CRYPTO_SUCCESS;
}

int tc_cmac_update(TCCmacState_t s, const uint8_t *data, size_t data_length) {
  unsigned int i;

  /* input sanity check: */
  if (s == (TCCmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }
  if (data_length == 0) {
    return TC_CRYPTO_SUCCESS;
  }
  if (data == (const uint8_t *)0) {
    return TC_CRYPTO_FAIL;
  }

  if (s->countdown == 0) {
    return TC_CRYPTO_FAIL;
  }

  s->countdown--;

  if (s->leftover_offset > 0) {
    /* last data added to s didn't end on a TC_AES_BLOCK_SIZE byte boundary */
    size_t remaining_space = TC_AES_BLOCK_SIZE - s->leftover_offset;

    if (data_length < remaining_space) {
      /* still not enough data to encrypt this time either */
      _copy(&s->leftover[s->leftover_offset], data_length, data, data_length);
      s->leftover_offset += data_length;
      return TC_CRYPTO_SUCCESS;
    }
    /* leftover block is now full; encrypt it first */
    _copy(&s->leftover[s->leftover_offset], remaining_space, data, remaining_space);
    data_length -= remaining_space;
    data += remaining_space;
    s->leftover_offset = 0;

    for (i = 0; i < TC_AES_BLOCK_SIZE; ++i) {
      s->iv[i] ^= s->leftover[i];
    }
    tc_aes_encrypt(s->iv, s->iv, s->sched);
  }

  /* CBC encrypt each (except the last) of the data blocks */
  while (data_length > TC_AES_BLOCK_SIZE) {
    for (i = 0; i < TC_AES_BLOCK_SIZE; ++i) {
      s->iv[i] ^= data[i];
    }
    tc_aes_encrypt(s->iv, s->iv, s->sched);
    data += TC_AES_BLOCK_SIZE;
    data_length -= TC_AES_BLOCK_SIZE;
  }

  if (data_length > 0) {
    /* save leftover data for next time */
    _copy(s->leftover, data_length, data, data_length);
    s->leftover_offset = data_length;
  }

  return TC_CRYPTO_SUCCESS;
}

int tc_cmac_final(uint8_t *tag, TCCmacState_t s) {
  uint8_t     *k;
  unsigned int i;

  /* input sanity check: */
  if (tag == (uint8_t *)0 || s == (TCCmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  if (s->leftover_offset == TC_AES_BLOCK_SIZE) {
    /* the last message block is a full-sized block */
    k = (uint8_t *)s->K1;
  } else {
    /* the final message block is not a full-sized  block */
    size_t remaining = TC_AES_BLOCK_SIZE - s->leftover_offset;

    _set(&s->leftover[s->leftover_offset], 0, remaining);
    s->leftover[s->leftover_offset] = TC_CMAC_PADDING;
    k                               = (uint8_t *)s->K2;
  }
  for (i = 0; i < TC_AES_BLOCK_SIZE; ++i) {
    s->iv[i] ^= s->leftover[i] ^ k[i];
  }

  tc_aes_encrypt(tag, s->iv, s->sched);

  /* erasing state: */
  tc_cmac_erase(s);

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ctr_mode.c
================================================
/* ctr_mode.c - TinyCrypt CTR mode implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "ctr_mode.h"
#include "constants.h"
#include "utils.h"

int tc_ctr_mode(uint8_t *out, unsigned int outlen, const uint8_t *in, unsigned int inlen, uint8_t *ctr, const TCAesKeySched_t sched) {
  uint8_t      buffer[TC_AES_BLOCK_SIZE];
  uint8_t      nonce[TC_AES_BLOCK_SIZE];
  unsigned int block_num;
  unsigned int i;

  /* input sanity check: */
  if (out == (uint8_t *)0 || in == (uint8_t *)0 || ctr == (uint8_t *)0 || sched == (TCAesKeySched_t)0 || inlen == 0 || outlen == 0 || outlen != inlen) {
    return TC_CRYPTO_FAIL;
  }

  /* copy the ctr to the nonce */
  (void)_copy(nonce, sizeof(nonce), ctr, sizeof(nonce));

  /* select the last 4 bytes of the nonce to be incremented */
  block_num = (nonce[12] << 24) | (nonce[13] << 16) | (nonce[14] << 8) | (nonce[15]);
  for (i = 0; i < inlen; ++i) {
    if ((i % (TC_AES_BLOCK_SIZE)) == 0) {
      /* encrypt data using the current nonce */
      if (tc_aes_encrypt(buffer, nonce, sched)) {
        block_num++;
        nonce[12] = (uint8_t)(block_num >> 24);
        nonce[13] = (uint8_t)(block_num >> 16);
        nonce[14] = (uint8_t)(block_num >> 8);
        nonce[15] = (uint8_t)(block_num);
      } else {
        return TC_CRYPTO_FAIL;
      }
    }
    /* update the output */
    *out++ = buffer[i % (TC_AES_BLOCK_SIZE)] ^ *in++;
  }

  /* update the counter */
  ctr[12] = nonce[12];
  ctr[13] = nonce[13];
  ctr[14] = nonce[14];
  ctr[15] = nonce[15];

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ctr_prng.c
================================================
/* ctr_prng.c - TinyCrypt implementation of CTR-PRNG */

/*
 * Copyright (c) 2016, Chris Morrison
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#include "ctr_prng.h"
#include "constants.h"
#include "utils.h"
#include 

/*
 * This PRNG is based on the CTR_DRBG described in Recommendation for Random
 * Number Generation Using Deterministic Random Bit Generators,
 * NIST SP 800-90A Rev. 1.
 *
 * Annotations to particular steps (e.g. 10.2.1.2 Step 1) refer to the steps
 * described in that document.
 *
 */

/**
 *  @brief Array incrementer
 *  Treats the supplied array as one contiguous number (MSB in arr[0]), and
 *  increments it by one
 *  @return none
 *  @param arr IN/OUT -- array to be incremented
 *  @param len IN -- size of arr in bytes
 */
static void arrInc(uint8_t arr[], unsigned int len) {
  unsigned int i;
  if (0 != arr) {
    for (i = len; i > 0U; i--) {
      if (++arr[i - 1] != 0U) {
        break;
      }
    }
  }
}

/**
 *  @brief CTR PRNG update
 *  Updates the internal state of supplied the CTR PRNG context
 *  increments it by one
 *  @return none
 *  @note Assumes: providedData is (TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE) bytes long
 *  @param ctx IN/OUT -- CTR PRNG state
 *  @param providedData IN -- data used when updating the internal state
 */
static void tc_ctr_prng_update(TCCtrPrng_t *const ctx, uint8_t const *const providedData) {
  if (0 != ctx) {
    /* 10.2.1.2 step 1 */
    uint8_t      temp[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE];
    unsigned int len = 0U;

    /* 10.2.1.2 step 2 */
    while (len < sizeof temp) {
      unsigned int blocklen = sizeof(temp) - len;
      uint8_t      output_block[TC_AES_BLOCK_SIZE];

      /* 10.2.1.2 step 2.1 */
      arrInc(ctx->V, sizeof ctx->V);

      /* 10.2.1.2 step 2.2 */
      if (blocklen > TC_AES_BLOCK_SIZE) {
        blocklen = TC_AES_BLOCK_SIZE;
      }
      (void)tc_aes_encrypt(output_block, ctx->V, &ctx->key);

      /* 10.2.1.2 step 2.3/step 3 */
      memcpy(&(temp[len]), output_block, blocklen);

      len += blocklen;
    }

    /* 10.2.1.2 step 4 */
    if (0 != providedData) {
      unsigned int i;
      for (i = 0U; i < sizeof temp; i++) {
        temp[i] ^= providedData[i];
      }
    }

    /* 10.2.1.2 step 5 */
    (void)tc_aes128_set_encrypt_key(&ctx->key, temp);

    /* 10.2.1.2 step 6 */
    memcpy(ctx->V, &(temp[TC_AES_KEY_SIZE]), TC_AES_BLOCK_SIZE);
  }
}

int tc_ctr_prng_init(TCCtrPrng_t *const ctx, uint8_t const *const entropy, unsigned int entropyLen, uint8_t const *const personalization, unsigned int pLen) {
  int          result = TC_CRYPTO_FAIL;
  unsigned int i;
  uint8_t      personalization_buf[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE] = {0U};
  uint8_t      seed_material[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE];
  uint8_t      zeroArr[TC_AES_BLOCK_SIZE] = {0U};

  if (0 != personalization) {
    /* 10.2.1.3.1 step 1 */
    unsigned int len = pLen;
    if (len > sizeof personalization_buf) {
      len = sizeof personalization_buf;
    }

    /* 10.2.1.3.1 step 2 */
    memcpy(personalization_buf, personalization, len);
  }

  if ((0 != ctx) && (0 != entropy) && (entropyLen >= sizeof seed_material)) {
    /* 10.2.1.3.1 step 3 */
    memcpy(seed_material, entropy, sizeof seed_material);
    for (i = 0U; i < sizeof seed_material; i++) {
      seed_material[i] ^= personalization_buf[i];
    }

    /* 10.2.1.3.1 step 4 */
    (void)tc_aes128_set_encrypt_key(&ctx->key, zeroArr);

    /* 10.2.1.3.1 step 5 */
    memset(ctx->V, 0x00, sizeof ctx->V);

    /* 10.2.1.3.1 step 6 */
    tc_ctr_prng_update(ctx, seed_material);

    /* 10.2.1.3.1 step 7 */
    ctx->reseedCount = 1U;

    result = TC_CRYPTO_SUCCESS;
  }
  return result;
}

int tc_ctr_prng_reseed(TCCtrPrng_t *const ctx, uint8_t const *const entropy, unsigned int entropyLen, uint8_t const *const additional_input, unsigned int additionallen) {
  unsigned int i;
  int          result                                                    = TC_CRYPTO_FAIL;
  uint8_t      additional_input_buf[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE] = {0U};
  uint8_t      seed_material[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE];

  if (0 != additional_input) {
    /* 10.2.1.4.1 step 1 */
    unsigned int len = additionallen;
    if (len > sizeof additional_input_buf) {
      len = sizeof additional_input_buf;
    }

    /* 10.2.1.4.1 step 2 */
    memcpy(additional_input_buf, additional_input, len);
  }

  unsigned int seedlen = (unsigned int)TC_AES_KEY_SIZE + (unsigned int)TC_AES_BLOCK_SIZE;
  if ((0 != ctx) && (entropyLen >= seedlen)) {
    /* 10.2.1.4.1 step 3 */
    memcpy(seed_material, entropy, sizeof seed_material);
    for (i = 0U; i < sizeof seed_material; i++) {
      seed_material[i] ^= additional_input_buf[i];
    }

    /* 10.2.1.4.1 step 4 */
    tc_ctr_prng_update(ctx, seed_material);

    /* 10.2.1.4.1 step 5 */
    ctx->reseedCount = 1U;

    result = TC_CRYPTO_SUCCESS;
  }
  return result;
}

int tc_ctr_prng_generate(TCCtrPrng_t *const ctx, uint8_t const *const additional_input, unsigned int additionallen, uint8_t *const out, unsigned int outlen) {
  /* 2^48 - see section 10.2.1 */
  static const uint64_t MAX_REQS_BEFORE_RESEED = 0x1000000000000ULL;

  /* 2^19 bits - see section 10.2.1 */
  static const unsigned int MAX_BYTES_PER_REQ = 65536U;

  unsigned int result = TC_CRYPTO_FAIL;

  if ((0 != ctx) && (0 != out) && (outlen < MAX_BYTES_PER_REQ)) {
    /* 10.2.1.5.1 step 1 */
    if (ctx->reseedCount > MAX_REQS_BEFORE_RESEED) {
      result = TC_CTR_PRNG_RESEED_REQ;
    } else {
      uint8_t additional_input_buf[TC_AES_KEY_SIZE + TC_AES_BLOCK_SIZE] = {0U};
      if (0 != additional_input) {
        /* 10.2.1.5.1 step 2  */
        unsigned int len = additionallen;
        if (len > sizeof additional_input_buf) {
          len = sizeof additional_input_buf;
        }
        memcpy(additional_input_buf, additional_input, len);
        tc_ctr_prng_update(ctx, additional_input_buf);
      }

      /* 10.2.1.5.1 step 3 - implicit */

      /* 10.2.1.5.1 step 4 */
      unsigned int len = 0U;
      while (len < outlen) {
        unsigned int blocklen = outlen - len;
        uint8_t      output_block[TC_AES_BLOCK_SIZE];

        /* 10.2.1.5.1 step 4.1 */
        arrInc(ctx->V, sizeof ctx->V);

        /* 10.2.1.5.1 step 4.2 */
        (void)tc_aes_encrypt(output_block, ctx->V, &ctx->key);

        /* 10.2.1.5.1 step 4.3/step 5 */
        if (blocklen > TC_AES_BLOCK_SIZE) {
          blocklen = TC_AES_BLOCK_SIZE;
        }
        memcpy(&(out[len]), output_block, blocklen);

        len += blocklen;
      }

      /* 10.2.1.5.1 step 6 */
      tc_ctr_prng_update(ctx, additional_input_buf);

      /* 10.2.1.5.1 step 7 */
      ctx->reseedCount++;

      /* 10.2.1.5.1 step 8 */
      result = TC_CRYPTO_SUCCESS;
    }
  }

  return result;
}

void tc_ctr_prng_uninstantiate(TCCtrPrng_t *const ctx) {
  if (0 != ctx) {
    memset(ctx->key.words, 0x00, sizeof ctx->key.words);
    memset(ctx->V, 0x00, sizeof ctx->V);
    ctx->reseedCount = 0U;
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ecc.c
================================================
/* ecc.c - TinyCrypt implementation of common ECC functions */

/*
 * Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 * * Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 * * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "ecc.h"
#include "../include/tinycrypt/ecc.h"
#include "ecc_platform_specific.h"
#include 

/* IMPORTANT: Make sure a cryptographically-secure PRNG is set and the platform
 * has access to enough entropy in order to feed the PRNG regularly. */
#if default_RNG_defined
static uECC_RNG_Function g_rng_function = &default_CSPRNG;
#else
static uECC_RNG_Function g_rng_function = 0;
#endif

void uECC_set_rng(uECC_RNG_Function rng_function) { g_rng_function = rng_function; }

uECC_RNG_Function uECC_get_rng(void) { return g_rng_function; }

int uECC_curve_private_key_size(uECC_Curve curve) { return BITS_TO_BYTES(curve->num_n_bits); }

int uECC_curve_public_key_size(uECC_Curve curve) { return 2 * curve->num_bytes; }

void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words) {
  wordcount_t i;
  for (i = 0; i < num_words; ++i) {
    vli[i] = 0;
  }
}

uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words) {
  uECC_word_t bits = 0;
  wordcount_t i;
  for (i = 0; i < num_words; ++i) {
    bits |= vli[i];
  }
  return (bits == 0);
}

uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit) { return (vli[bit >> uECC_WORD_BITS_SHIFT] & ((uECC_word_t)1 << (bit & uECC_WORD_BITS_MASK))); }

/* Counts the number of words in vli. */
static wordcount_t vli_numDigits(const uECC_word_t *vli, const wordcount_t max_words) {
  wordcount_t i;
  /* Search from the end until we find a non-zero digit. We do it in reverse
   * because we expect that most digits will be nonzero. */
  for (i = max_words - 1; i >= 0 && vli[i] == 0; --i) {
  }

  return (i + 1);
}

bitcount_t uECC_vli_numBits(const uECC_word_t *vli, const wordcount_t max_words) {
  uECC_word_t i;
  uECC_word_t digit;

  wordcount_t num_digits = vli_numDigits(vli, max_words);
  if (num_digits == 0) {
    return 0;
  }

  digit = vli[num_digits - 1];
  for (i = 0; digit; ++i) {
    digit >>= 1;
  }

  return (((bitcount_t)(num_digits - 1) << uECC_WORD_BITS_SHIFT) + i);
}

void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src, wordcount_t num_words) {
  wordcount_t i;

  for (i = 0; i < num_words; ++i) {
    dest[i] = src[i];
  }
}

cmpresult_t uECC_vli_cmp_unsafe(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  wordcount_t i;

  for (i = num_words - 1; i >= 0; --i) {
    if (left[i] > right[i]) {
      return 1;
    } else if (left[i] < right[i]) {
      return -1;
    }
  }
  return 0;
}

uECC_word_t uECC_vli_equal(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  uECC_word_t diff = 0;
  wordcount_t i;

  for (i = num_words - 1; i >= 0; --i) {
    diff |= (left[i] ^ right[i]);
  }
  return !(diff == 0);
}

uECC_word_t cond_set(uECC_word_t p_true, uECC_word_t p_false, unsigned int cond) { return (p_true * (cond)) | (p_false * (!cond)); }

/* Computes result = left - right, returning borrow, in constant time.
 * Can modify in place. */
uECC_word_t uECC_vli_sub(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  uECC_word_t borrow = 0;
  wordcount_t i;
  for (i = 0; i < num_words; ++i) {
    uECC_word_t diff = left[i] - right[i] - borrow;
    uECC_word_t val  = (diff > left[i]);
    borrow           = cond_set(val, borrow, (diff != left[i]));

    result[i] = diff;
  }
  return borrow;
}

/* Computes result = left + right, returning carry, in constant time.
 * Can modify in place. */
static uECC_word_t uECC_vli_add(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  uECC_word_t carry = 0;
  wordcount_t i;
  for (i = 0; i < num_words; ++i) {
    uECC_word_t sum = left[i] + right[i] + carry;
    uECC_word_t val = (sum < left[i]);
    carry           = cond_set(val, carry, (sum != left[i]));
    result[i]       = sum;
  }
  return carry;
}

cmpresult_t uECC_vli_cmp(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  uECC_word_t tmp[NUM_ECC_WORDS];
  uECC_word_t neg   = !!uECC_vli_sub(tmp, left, right, num_words);
  uECC_word_t equal = uECC_vli_isZero(tmp, num_words);
  return (!equal - 2 * neg);
}

/* Computes vli = vli >> 1. */
static void uECC_vli_rshift1(uECC_word_t *vli, wordcount_t num_words) {
  uECC_word_t *end   = vli;
  uECC_word_t  carry = 0;

  vli += num_words;
  while (vli-- > end) {
    uECC_word_t temp = *vli;
    *vli             = (temp >> 1) | carry;
    carry            = temp << (uECC_WORD_BITS - 1);
  }
}

static void muladd(uECC_word_t a, uECC_word_t b, uECC_word_t *r0, uECC_word_t *r1, uECC_word_t *r2) {
  uECC_dword_t p   = (uECC_dword_t)a * b;
  uECC_dword_t r01 = ((uECC_dword_t)(*r1) << uECC_WORD_BITS) | *r0;
  r01 += p;
  *r2 += (r01 < p);
  *r1 = r01 >> uECC_WORD_BITS;
  *r0 = (uECC_word_t)r01;
}

/* Computes result = left * right. Result must be 2 * num_words long. */
static void uECC_vli_mult(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words) {
  uECC_word_t r0 = 0;
  uECC_word_t r1 = 0;
  uECC_word_t r2 = 0;
  wordcount_t i, k;

  /* Compute each digit of result in sequence, maintaining the carries. */
  for (k = 0; k < num_words; ++k) {
    for (i = 0; i <= k; ++i) {
      muladd(left[i], right[k - i], &r0, &r1, &r2);
    }

    result[k] = r0;
    r0        = r1;
    r1        = r2;
    r2        = 0;
  }

  for (k = num_words; k < num_words * 2 - 1; ++k) {
    for (i = (k + 1) - num_words; i < num_words; ++i) {
      muladd(left[i], right[k - i], &r0, &r1, &r2);
    }
    result[k] = r0;
    r0        = r1;
    r1        = r2;
    r2        = 0;
  }
  result[num_words * 2 - 1] = r0;
}

void uECC_vli_modAdd(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t carry = uECC_vli_add(result, left, right, num_words);
  if (carry || uECC_vli_cmp_unsafe(mod, result, num_words) != 1) {
    /* result > mod (result = mod + remainder), so subtract mod to get
     * remainder. */
    uECC_vli_sub(result, result, mod, num_words);
  }
}

void uECC_vli_modSub(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t l_borrow = uECC_vli_sub(result, left, right, num_words);
  if (l_borrow) {
    /* In this case, result == -diff == (max int) - diff. Since -x % d == d - x,
     * we can get the correct result from result + mod (with overflow). */
    uECC_vli_add(result, result, mod, num_words);
  }
}

/* Computes result = product % mod, where product is 2N words long. */
/* Currently only designed to work for curve_p or curve_n. */
void uECC_vli_mmod(uECC_word_t *result, uECC_word_t *product, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t  mod_multiple[2 * NUM_ECC_WORDS];
  uECC_word_t  tmp[2 * NUM_ECC_WORDS];
  uECC_word_t *v[2] = {tmp, product};
  uECC_word_t  index;

  /* Shift mod so its highest set bit is at the maximum position. */
  bitcount_t  shift      = (num_words * 2 * uECC_WORD_BITS) - uECC_vli_numBits(mod, num_words);
  wordcount_t word_shift = shift / uECC_WORD_BITS;
  wordcount_t bit_shift  = shift % uECC_WORD_BITS;
  uECC_word_t carry      = 0;
  uECC_vli_clear(mod_multiple, word_shift);
  if (bit_shift > 0) {
    for (index = 0; index < (uECC_word_t)num_words; ++index) {
      mod_multiple[word_shift + index] = (mod[index] << bit_shift) | carry;
      carry                            = mod[index] >> (uECC_WORD_BITS - bit_shift);
    }
  } else {
    uECC_vli_set(mod_multiple + word_shift, mod, num_words);
  }

  for (index = 1; shift >= 0; --shift) {
    uECC_word_t borrow = 0;
    wordcount_t i;
    for (i = 0; i < num_words * 2; ++i) {
      uECC_word_t diff = v[index][i] - mod_multiple[i] - borrow;
      if (diff != v[index][i]) {
        borrow = (diff > v[index][i]);
      }
      v[1 - index][i] = diff;
    }
    /* Swap the index if there was no borrow */
    index = !(index ^ borrow);
    uECC_vli_rshift1(mod_multiple, num_words);
    mod_multiple[num_words - 1] |= mod_multiple[num_words] << (uECC_WORD_BITS - 1);
    uECC_vli_rshift1(mod_multiple + num_words, num_words);
  }
  uECC_vli_set(result, v[index], num_words);
}

void uECC_vli_modMult(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t product[2 * NUM_ECC_WORDS];
  uECC_vli_mult(product, left, right, num_words);
  uECC_vli_mmod(result, product, mod, num_words);
}

void uECC_vli_modMult_fast(uECC_word_t *result, const uECC_word_t *left, const uECC_word_t *right, uECC_Curve curve) {
  uECC_word_t product[2 * NUM_ECC_WORDS];
  uECC_vli_mult(product, left, right, curve->num_words);

  curve->mmod_fast(result, product);
}

static void uECC_vli_modSquare_fast(uECC_word_t *result, const uECC_word_t *left, uECC_Curve curve) { uECC_vli_modMult_fast(result, left, left, curve); }

#define EVEN(vli) (!(vli[0] & 1))

static void vli_modInv_update(uECC_word_t *uv, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t carry = 0;

  if (!EVEN(uv)) {
    carry = uECC_vli_add(uv, uv, mod, num_words);
  }
  uECC_vli_rshift1(uv, num_words);
  if (carry) {
    uv[num_words - 1] |= HIGH_BIT_SET;
  }
}

void uECC_vli_modInv(uECC_word_t *result, const uECC_word_t *input, const uECC_word_t *mod, wordcount_t num_words) {
  uECC_word_t a[NUM_ECC_WORDS], b[NUM_ECC_WORDS];
  uECC_word_t u[NUM_ECC_WORDS], v[NUM_ECC_WORDS];
  cmpresult_t cmpResult;

  if (uECC_vli_isZero(input, num_words)) {
    uECC_vli_clear(result, num_words);
    return;
  }

  uECC_vli_set(a, input, num_words);
  uECC_vli_set(b, mod, num_words);
  uECC_vli_clear(u, num_words);
  u[0] = 1;
  uECC_vli_clear(v, num_words);
  while ((cmpResult = uECC_vli_cmp_unsafe(a, b, num_words)) != 0) {
    if (EVEN(a)) {
      uECC_vli_rshift1(a, num_words);
      vli_modInv_update(u, mod, num_words);
    } else if (EVEN(b)) {
      uECC_vli_rshift1(b, num_words);
      vli_modInv_update(v, mod, num_words);
    } else if (cmpResult > 0) {
      uECC_vli_sub(a, a, b, num_words);
      uECC_vli_rshift1(a, num_words);
      if (uECC_vli_cmp_unsafe(u, v, num_words) < 0) {
        uECC_vli_add(u, u, mod, num_words);
      }
      uECC_vli_sub(u, u, v, num_words);
      vli_modInv_update(u, mod, num_words);
    } else {
      uECC_vli_sub(b, b, a, num_words);
      uECC_vli_rshift1(b, num_words);
      if (uECC_vli_cmp_unsafe(v, u, num_words) < 0) {
        uECC_vli_add(v, v, mod, num_words);
      }
      uECC_vli_sub(v, v, u, num_words);
      vli_modInv_update(v, mod, num_words);
    }
  }
  uECC_vli_set(result, u, num_words);
}

/* ------ Point operations ------ */

void double_jacobian_default(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *Z1, uECC_Curve curve) {
  /* t1 = X, t2 = Y, t3 = Z */
  uECC_word_t t4[NUM_ECC_WORDS];
  uECC_word_t t5[NUM_ECC_WORDS];
  wordcount_t num_words = curve->num_words;

  if (uECC_vli_isZero(Z1, num_words)) {
    return;
  }

  uECC_vli_modSquare_fast(t4, Y1, curve);   /* t4 = y1^2 */
  uECC_vli_modMult_fast(t5, X1, t4, curve); /* t5 = x1*y1^2 = A */
  uECC_vli_modSquare_fast(t4, t4, curve);   /* t4 = y1^4 */
  uECC_vli_modMult_fast(Y1, Y1, Z1, curve); /* t2 = y1*z1 = z3 */
  uECC_vli_modSquare_fast(Z1, Z1, curve);   /* t3 = z1^2 */

  uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = x1 + z1^2 */
  uECC_vli_modAdd(Z1, Z1, Z1, curve->p, num_words); /* t3 = 2*z1^2 */
  uECC_vli_modSub(Z1, X1, Z1, curve->p, num_words); /* t3 = x1 - z1^2 */
  uECC_vli_modMult_fast(X1, X1, Z1, curve);         /* t1 = x1^2 - z1^4 */

  uECC_vli_modAdd(Z1, X1, X1, curve->p, num_words); /* t3 = 2*(x1^2 - z1^4) */
  uECC_vli_modAdd(X1, X1, Z1, curve->p, num_words); /* t1 = 3*(x1^2 - z1^4) */
  if (uECC_vli_testBit(X1, 0)) {
    uECC_word_t l_carry = uECC_vli_add(X1, X1, curve->p, num_words);
    uECC_vli_rshift1(X1, num_words);
    X1[num_words - 1] |= l_carry << (uECC_WORD_BITS - 1);
  } else {
    uECC_vli_rshift1(X1, num_words);
  }

  /* t1 = 3/2*(x1^2 - z1^4) = B */
  uECC_vli_modSquare_fast(Z1, X1, curve);           /* t3 = B^2 */
  uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - A */
  uECC_vli_modSub(Z1, Z1, t5, curve->p, num_words); /* t3 = B^2 - 2A = x3 */
  uECC_vli_modSub(t5, t5, Z1, curve->p, num_words); /* t5 = A - x3 */
  uECC_vli_modMult_fast(X1, X1, t5, curve);         /* t1 = B * (A - x3) */
  /* t4 = B * (A - x3) - y1^4 = y3: */
  uECC_vli_modSub(t4, X1, t4, curve->p, num_words);

  uECC_vli_set(X1, Z1, num_words);
  uECC_vli_set(Z1, Y1, num_words);
  uECC_vli_set(Y1, t4, num_words);
}

void x_side_default(uECC_word_t *result, const uECC_word_t *x, uECC_Curve curve) {
  uECC_word_t _3[NUM_ECC_WORDS] = {3}; /* -a = 3 */
  wordcount_t num_words         = curve->num_words;

  uECC_vli_modSquare_fast(result, x, curve);                /* r = x^2 */
  uECC_vli_modSub(result, result, _3, curve->p, num_words); /* r = x^2 - 3 */
  uECC_vli_modMult_fast(result, result, x, curve);          /* r = x^3 - 3x */
  /* r = x^3 - 3x + b: */
  uECC_vli_modAdd(result, result, curve->b, curve->p, num_words);
}

uECC_Curve uECC_secp256r1(void) { return &curve_secp256r1; }

void vli_mmod_fast_secp256r1(unsigned int *result, unsigned int *product) {
  unsigned int tmp[NUM_ECC_WORDS];
  int          carry;

  /* t */
  uECC_vli_set(result, product, NUM_ECC_WORDS);

  /* s1 */
  tmp[0] = tmp[1] = tmp[2] = 0;
  tmp[3]                   = product[11];
  tmp[4]                   = product[12];
  tmp[5]                   = product[13];
  tmp[6]                   = product[14];
  tmp[7]                   = product[15];
  carry                    = uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
  carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);

  /* s2 */
  tmp[3] = product[12];
  tmp[4] = product[13];
  tmp[5] = product[14];
  tmp[6] = product[15];
  tmp[7] = 0;
  carry += uECC_vli_add(tmp, tmp, tmp, NUM_ECC_WORDS);
  carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);

  /* s3 */
  tmp[0] = product[8];
  tmp[1] = product[9];
  tmp[2] = product[10];
  tmp[3] = tmp[4] = tmp[5] = 0;
  tmp[6]                   = product[14];
  tmp[7]                   = product[15];
  carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);

  /* s4 */
  tmp[0] = product[9];
  tmp[1] = product[10];
  tmp[2] = product[11];
  tmp[3] = product[13];
  tmp[4] = product[14];
  tmp[5] = product[15];
  tmp[6] = product[13];
  tmp[7] = product[8];
  carry += uECC_vli_add(result, result, tmp, NUM_ECC_WORDS);

  /* d1 */
  tmp[0] = product[11];
  tmp[1] = product[12];
  tmp[2] = product[13];
  tmp[3] = tmp[4] = tmp[5] = 0;
  tmp[6]                   = product[8];
  tmp[7]                   = product[10];
  carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);

  /* d2 */
  tmp[0] = product[12];
  tmp[1] = product[13];
  tmp[2] = product[14];
  tmp[3] = product[15];
  tmp[4] = tmp[5] = 0;
  tmp[6]          = product[9];
  tmp[7]          = product[11];
  carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);

  /* d3 */
  tmp[0] = product[13];
  tmp[1] = product[14];
  tmp[2] = product[15];
  tmp[3] = product[8];
  tmp[4] = product[9];
  tmp[5] = product[10];
  tmp[6] = 0;
  tmp[7] = product[12];
  carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);

  /* d4 */
  tmp[0] = product[14];
  tmp[1] = product[15];
  tmp[2] = 0;
  tmp[3] = product[9];
  tmp[4] = product[10];
  tmp[5] = product[11];
  tmp[6] = 0;
  tmp[7] = product[13];
  carry -= uECC_vli_sub(result, result, tmp, NUM_ECC_WORDS);

  if (carry < 0) {
    do {
      carry += uECC_vli_add(result, result, curve_secp256r1.p, NUM_ECC_WORDS);
    } while (carry < 0);
  } else {
    while (carry || uECC_vli_cmp_unsafe(curve_secp256r1.p, result, NUM_ECC_WORDS) != 1) {
      carry -= uECC_vli_sub(result, result, curve_secp256r1.p, NUM_ECC_WORDS);
    }
  }
}

uECC_word_t EccPoint_isZero(const uECC_word_t *point, uECC_Curve curve) { return uECC_vli_isZero(point, curve->num_words * 2); }

void apply_z(uECC_word_t *X1, uECC_word_t *Y1, const uECC_word_t *const Z, uECC_Curve curve) {
  uECC_word_t t1[NUM_ECC_WORDS];

  uECC_vli_modSquare_fast(t1, Z, curve);    /* z^2 */
  uECC_vli_modMult_fast(X1, X1, t1, curve); /* x1 * z^2 */
  uECC_vli_modMult_fast(t1, t1, Z, curve);  /* z^3 */
  uECC_vli_modMult_fast(Y1, Y1, t1, curve); /* y1 * z^3 */
}

/* P = (x1, y1) => 2P, (x2, y2) => P' */
static void XYcZ_initial_double(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *X2, uECC_word_t *Y2, const uECC_word_t *const initial_Z, uECC_Curve curve) {
  uECC_word_t z[NUM_ECC_WORDS];
  wordcount_t num_words = curve->num_words;
  if (initial_Z) {
    uECC_vli_set(z, initial_Z, num_words);
  } else {
    uECC_vli_clear(z, num_words);
    z[0] = 1;
  }

  uECC_vli_set(X2, X1, num_words);
  uECC_vli_set(Y2, Y1, num_words);

  apply_z(X1, Y1, z, curve);
  curve->double_jacobian(X1, Y1, z, curve);
  apply_z(X2, Y2, z, curve);
}

void XYcZ_add(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *X2, uECC_word_t *Y2, uECC_Curve curve) {
  /* t1 = X1, t2 = Y1, t3 = X2, t4 = Y2 */
  uECC_word_t t5[NUM_ECC_WORDS];
  wordcount_t num_words = curve->num_words;

  uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */
  uECC_vli_modSquare_fast(t5, t5, curve);           /* t5 = (x2 - x1)^2 = A */
  uECC_vli_modMult_fast(X1, X1, t5, curve);         /* t1 = x1*A = B */
  uECC_vli_modMult_fast(X2, X2, t5, curve);         /* t3 = x2*A = C */
  uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y2 - y1 */
  uECC_vli_modSquare_fast(t5, Y2, curve);           /* t5 = (y2 - y1)^2 = D */

  uECC_vli_modSub(t5, t5, X1, curve->p, num_words); /* t5 = D - B */
  uECC_vli_modSub(t5, t5, X2, curve->p, num_words); /* t5 = D - B - C = x3 */
  uECC_vli_modSub(X2, X2, X1, curve->p, num_words); /* t3 = C - B */
  uECC_vli_modMult_fast(Y1, Y1, X2, curve);         /* t2 = y1*(C - B) */
  uECC_vli_modSub(X2, X1, t5, curve->p, num_words); /* t3 = B - x3 */
  uECC_vli_modMult_fast(Y2, Y2, X2, curve);         /* t4 = (y2 - y1)*(B - x3) */
  uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y3 */

  uECC_vli_set(X2, t5, num_words);
}

/* Input P = (x1, y1, Z), Q = (x2, y2, Z)
   Output P + Q = (x3, y3, Z3), P - Q = (x3', y3', Z3)
   or P => P - Q, Q => P + Q
 */
static void XYcZ_addC(uECC_word_t *X1, uECC_word_t *Y1, uECC_word_t *X2, uECC_word_t *Y2, uECC_Curve curve) {
  /* t1 = X1, t2 = Y1, t3 = X2, t4 = Y2 */
  uECC_word_t t5[NUM_ECC_WORDS];
  uECC_word_t t6[NUM_ECC_WORDS];
  uECC_word_t t7[NUM_ECC_WORDS];
  wordcount_t num_words = curve->num_words;

  uECC_vli_modSub(t5, X2, X1, curve->p, num_words); /* t5 = x2 - x1 */
  uECC_vli_modSquare_fast(t5, t5, curve);           /* t5 = (x2 - x1)^2 = A */
  uECC_vli_modMult_fast(X1, X1, t5, curve);         /* t1 = x1*A = B */
  uECC_vli_modMult_fast(X2, X2, t5, curve);         /* t3 = x2*A = C */
  uECC_vli_modAdd(t5, Y2, Y1, curve->p, num_words); /* t5 = y2 + y1 */
  uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words); /* t4 = y2 - y1 */

  uECC_vli_modSub(t6, X2, X1, curve->p, num_words); /* t6 = C - B */
  uECC_vli_modMult_fast(Y1, Y1, t6, curve);         /* t2 = y1 * (C - B) = E */
  uECC_vli_modAdd(t6, X1, X2, curve->p, num_words); /* t6 = B + C */
  uECC_vli_modSquare_fast(X2, Y2, curve);           /* t3 = (y2 - y1)^2 = D */
  uECC_vli_modSub(X2, X2, t6, curve->p, num_words); /* t3 = D - (B + C) = x3 */

  uECC_vli_modSub(t7, X1, X2, curve->p, num_words); /* t7 = B - x3 */
  uECC_vli_modMult_fast(Y2, Y2, t7, curve);         /* t4 = (y2 - y1)*(B - x3) */
  /* t4 = (y2 - y1)*(B - x3) - E = y3: */
  uECC_vli_modSub(Y2, Y2, Y1, curve->p, num_words);

  uECC_vli_modSquare_fast(t7, t5, curve);           /* t7 = (y2 + y1)^2 = F */
  uECC_vli_modSub(t7, t7, t6, curve->p, num_words); /* t7 = F - (B + C) = x3' */
  uECC_vli_modSub(t6, t7, X1, curve->p, num_words); /* t6 = x3' - B */
  uECC_vli_modMult_fast(t6, t6, t5, curve);         /* t6 = (y2+y1)*(x3' - B) */
  /* t2 = (y2+y1)*(x3' - B) - E = y3': */
  uECC_vli_modSub(Y1, t6, Y1, curve->p, num_words);

  uECC_vli_set(X1, t7, num_words);
}

void EccPoint_mult(uECC_word_t *result, const uECC_word_t *point, const uECC_word_t *scalar, const uECC_word_t *initial_Z, bitcount_t num_bits, uECC_Curve curve) {
  /* R0 and R1 */
  uECC_word_t Rx[2][NUM_ECC_WORDS];
  uECC_word_t Ry[2][NUM_ECC_WORDS];
  uECC_word_t z[NUM_ECC_WORDS];
  bitcount_t  i;
  uECC_word_t nb;
  wordcount_t num_words = curve->num_words;

  uECC_vli_set(Rx[1], point, num_words);
  uECC_vli_set(Ry[1], point + num_words, num_words);

  XYcZ_initial_double(Rx[1], Ry[1], Rx[0], Ry[0], initial_Z, curve);

  for (i = num_bits - 2; i > 0; --i) {
    nb = !uECC_vli_testBit(scalar, i);
    XYcZ_addC(Rx[1 - nb], Ry[1 - nb], Rx[nb], Ry[nb], curve);
    XYcZ_add(Rx[nb], Ry[nb], Rx[1 - nb], Ry[1 - nb], curve);
  }

  nb = !uECC_vli_testBit(scalar, 0);
  XYcZ_addC(Rx[1 - nb], Ry[1 - nb], Rx[nb], Ry[nb], curve);

  /* Find final 1/Z value. */
  uECC_vli_modSub(z, Rx[1], Rx[0], curve->p, num_words); /* X1 - X0 */
  uECC_vli_modMult_fast(z, z, Ry[1 - nb], curve);        /* Yb * (X1 - X0) */
  uECC_vli_modMult_fast(z, z, point, curve);             /* xP * Yb * (X1 - X0) */
  uECC_vli_modInv(z, z, curve->p, num_words);            /* 1 / (xP * Yb * (X1 - X0))*/
  /* yP / (xP * Yb * (X1 - X0)) */
  uECC_vli_modMult_fast(z, z, point + num_words, curve);
  /* Xb * yP / (xP * Yb * (X1 - X0)) */
  uECC_vli_modMult_fast(z, z, Rx[1 - nb], curve);
  /* End 1/Z calculation */

  XYcZ_add(Rx[nb], Ry[nb], Rx[1 - nb], Ry[1 - nb], curve);
  apply_z(Rx[0], Ry[0], z, curve);

  uECC_vli_set(result, Rx[0], num_words);
  uECC_vli_set(result + num_words, Ry[0], num_words);
}

uECC_word_t regularize_k(const uECC_word_t *const k, uECC_word_t *k0, uECC_word_t *k1, uECC_Curve curve) {
  wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits);

  bitcount_t num_n_bits = curve->num_n_bits;

  uECC_word_t carry = uECC_vli_add(k0, k, curve->n, num_n_words) || (num_n_bits < ((bitcount_t)num_n_words * uECC_WORD_SIZE * 8) && uECC_vli_testBit(k0, num_n_bits));

  uECC_vli_add(k1, k0, curve->n, num_n_words);

  return carry;
}

uECC_word_t EccPoint_compute_public_key(uECC_word_t *result, uECC_word_t *private_key, uECC_Curve curve) {
  uECC_word_t  tmp1[NUM_ECC_WORDS];
  uECC_word_t  tmp2[NUM_ECC_WORDS];
  uECC_word_t *p2[2] = {tmp1, tmp2};
  uECC_word_t  carry;

  /* Regularize the bitcount for the private key so that attackers cannot
   * use a side channel attack to learn the number of leading zeros. */
  carry = regularize_k(private_key, tmp1, tmp2, curve);

  EccPoint_mult(result, curve->G, p2[!carry], 0, curve->num_n_bits + 1, curve);

  if (EccPoint_isZero(result, curve)) {
    return 0;
  }
  return 1;
}

/* Converts an integer in uECC native format to big-endian bytes. */
void uECC_vli_nativeToBytes(uint8_t *bytes, int num_bytes, const unsigned int *native) {
  wordcount_t i;
  for (i = 0; i < num_bytes; ++i) {
    unsigned b = num_bytes - 1 - i;
    bytes[i]   = native[b / uECC_WORD_SIZE] >> (8 * (b % uECC_WORD_SIZE));
  }
}

/* Converts big-endian bytes to an integer in uECC native format. */
void uECC_vli_bytesToNative(unsigned int *native, const uint8_t *bytes, int num_bytes) {
  wordcount_t i;
  uECC_vli_clear(native, (num_bytes + (uECC_WORD_SIZE - 1)) / uECC_WORD_SIZE);
  for (i = 0; i < num_bytes; ++i) {
    unsigned b = num_bytes - 1 - i;
    native[b / uECC_WORD_SIZE] |= (uECC_word_t)bytes[i] << (8 * (b % uECC_WORD_SIZE));
  }
}

int uECC_generate_random_int(uECC_word_t *random, const uECC_word_t *top, wordcount_t num_words) {
  uECC_word_t mask = (uECC_word_t)-1;
  uECC_word_t tries;
  bitcount_t  num_bits = uECC_vli_numBits(top, num_words);

  if (!g_rng_function) {
    return 0;
  }

  for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) {
    if (!g_rng_function((uint8_t *)random, num_words * uECC_WORD_SIZE)) {
      return 0;
    }
    random[num_words - 1] &= mask >> ((bitcount_t)(num_words * uECC_WORD_SIZE * 8 - num_bits));
    if (!uECC_vli_isZero(random, num_words) && uECC_vli_cmp(top, random, num_words) == 1) {
      return 1;
    }
  }
  return 0;
}

int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve) {
  uECC_word_t tmp1[NUM_ECC_WORDS];
  uECC_word_t tmp2[NUM_ECC_WORDS];
  wordcount_t num_words = curve->num_words;

  /* The point at infinity is invalid. */
  if (EccPoint_isZero(point, curve)) {
    return -1;
  }

  /* x and y must be smaller than p. */
  if (uECC_vli_cmp_unsafe(curve->p, point, num_words) != 1 || uECC_vli_cmp_unsafe(curve->p, point + num_words, num_words) != 1) {
    return -2;
  }

  uECC_vli_modSquare_fast(tmp1, point + num_words, curve);
  curve->x_side(tmp2, point, curve); /* tmp2 = x^3 + ax + b */

  /* Make sure that y^2 == x^3 + ax + b */
  if (uECC_vli_equal(tmp1, tmp2, num_words) != 0)
    return -3;

  return 0;
}

int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve) {
  uECC_word_t _public[NUM_ECC_WORDS * 2];

  uECC_vli_bytesToNative(_public, public_key, curve->num_bytes);
  uECC_vli_bytesToNative(_public + curve->num_words, public_key + curve->num_bytes, curve->num_bytes);

  if (uECC_vli_cmp_unsafe(_public, curve->G, NUM_ECC_WORDS * 2) == 0) {
    return -4;
  }

  return uECC_valid_point(_public, curve);
}

int uECC_compute_public_key(const uint8_t *private_key, uint8_t *public_key, uECC_Curve curve) {
  uECC_word_t _private[NUM_ECC_WORDS];
  uECC_word_t _public[NUM_ECC_WORDS * 2];

  uECC_vli_bytesToNative(_private, private_key, BITS_TO_BYTES(curve->num_n_bits));

  /* Make sure the private key is in the range [1, n-1]. */
  if (uECC_vli_isZero(_private, BITS_TO_WORDS(curve->num_n_bits))) {
    return 0;
  }

  if (uECC_vli_cmp(curve->n, _private, BITS_TO_WORDS(curve->num_n_bits)) != 1) {
    return 0;
  }

  /* Compute public key. */
  if (!EccPoint_compute_public_key(_public, _private, curve)) {
    return 0;
  }

  uECC_vli_nativeToBytes(public_key, curve->num_bytes, _public);
  uECC_vli_nativeToBytes(public_key + curve->num_bytes, curve->num_bytes, _public + curve->num_words);
  return 1;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ecc_dh.c
================================================
/* ec_dh.c - TinyCrypt implementation of EC-DH */

/*
 * Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  * Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */
#include "ecc_dh.h"
#include "constants.h"
#include "ecc.h"
#if defined(BFLB_BLE)
#include "utils.h"
#endif
#include 
#if defined(BL_MCU_SDK)
#include "ecc_platform_specific.h"
#endif

#if default_RNG_defined
static uECC_RNG_Function g_rng_function = &default_CSPRNG;
#else
static uECC_RNG_Function g_rng_function = 0;
#endif

int uECC_make_key_with_d(uint8_t *public_key, uint8_t *private_key, unsigned int *d, uECC_Curve curve) {
  uECC_word_t _private[NUM_ECC_WORDS];
  uECC_word_t _public[NUM_ECC_WORDS * 2];

  /* This function is designed for test purposes-only (such as validating NIST
   * test vectors) as it uses a provided value for d instead of generating
   * it uniformly at random. */
  memcpy(_private, d, NUM_ECC_BYTES);

  /* Computing public-key from private: */
  if (EccPoint_compute_public_key(_public, _private, curve)) {
    /* Converting buffers to correct bit order: */
    uECC_vli_nativeToBytes(private_key, BITS_TO_BYTES(curve->num_n_bits), _private);
    uECC_vli_nativeToBytes(public_key, curve->num_bytes, _public);
    uECC_vli_nativeToBytes(public_key + curve->num_bytes, curve->num_bytes, _public + curve->num_words);

    /* erasing temporary buffer used to store secret: */
    _set_secure(_private, 0, NUM_ECC_BYTES);

    return 1;
  }
  return 0;
}

int uECC_make_key(uint8_t *public_key, uint8_t *private_key, uECC_Curve curve) {
  uECC_word_t _random[NUM_ECC_WORDS * 2];
  uECC_word_t _private[NUM_ECC_WORDS];
  uECC_word_t _public[NUM_ECC_WORDS * 2];
  uECC_word_t tries;

  for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) {
    /* Generating _private uniformly at random: */
    uECC_RNG_Function rng_function = uECC_get_rng();
    if (!rng_function || !rng_function((uint8_t *)_random, 2 * NUM_ECC_WORDS * uECC_WORD_SIZE)) {
      return 0;
    }

    /* computing modular reduction of _random (see FIPS 186.4 B.4.1): */
    uECC_vli_mmod(_private, _random, curve->n, BITS_TO_WORDS(curve->num_n_bits));

    /* Computing public-key from private: */
    if (EccPoint_compute_public_key(_public, _private, curve)) {
      /* Converting buffers to correct bit order: */
      uECC_vli_nativeToBytes(private_key, BITS_TO_BYTES(curve->num_n_bits), _private);
      uECC_vli_nativeToBytes(public_key, curve->num_bytes, _public);
      uECC_vli_nativeToBytes(public_key + curve->num_bytes, curve->num_bytes, _public + curve->num_words);

      /* erasing temporary buffer that stored secret: */
      _set_secure(_private, 0, NUM_ECC_BYTES);

      return 1;
    }
  }
  return 0;
}

int uECC_shared_secret(const uint8_t *public_key, const uint8_t *private_key, uint8_t *secret, uECC_Curve curve) {
  uECC_word_t _public[NUM_ECC_WORDS * 2];
  uECC_word_t _private[NUM_ECC_WORDS];

  uECC_word_t  tmp[NUM_ECC_WORDS];
  uECC_word_t *p2[2]     = {_private, tmp};
  uECC_word_t *initial_Z = 0;
  uECC_word_t  carry;
  wordcount_t  num_words = curve->num_words;
  wordcount_t  num_bytes = curve->num_bytes;
  int          r;

  /* Converting buffers to correct bit order: */
  uECC_vli_bytesToNative(_private, private_key, BITS_TO_BYTES(curve->num_n_bits));
  uECC_vli_bytesToNative(_public, public_key, num_bytes);
  uECC_vli_bytesToNative(_public + num_words, public_key + num_bytes, num_bytes);

  /* Regularize the bitcount for the private key so that attackers cannot use a
   * side channel attack to learn the number of leading zeros. */
  carry = regularize_k(_private, _private, tmp, curve);

  /* If an RNG function was specified, try to get a random initial Z value to
   * improve protection against side-channel attacks. */
  if (g_rng_function) {
    if (!uECC_generate_random_int(p2[carry], curve->p, num_words)) {
      r = 0;
      goto clear_and_out;
    }
    initial_Z = p2[carry];
  }

  EccPoint_mult(_public, _public, p2[!carry], initial_Z, curve->num_n_bits + 1, curve);

  uECC_vli_nativeToBytes(secret, num_bytes, _public);
  r = !EccPoint_isZero(_public, curve);

clear_and_out:
  /* erasing temporary buffer used to store secret: */
  _set_secure(p2, 0, sizeof(p2));
  _set_secure(tmp, 0, sizeof(tmp));
  _set_secure(_private, 0, sizeof(_private));

  return r;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ecc_dsa.c
================================================
/* ec_dsa.c - TinyCrypt implementation of EC-DSA */

/* Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  * Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.*/

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "ecc_dsa.h"
#include "constants.h"
#include "ecc.h"
#if defined(BL_MCU_SDK)
#include "ecc_platform_specific.h"
#endif

#if default_RNG_defined
static uECC_RNG_Function g_rng_function = &default_CSPRNG;
#else
static uECC_RNG_Function g_rng_function = 0;
#endif

static void bits2int(uECC_word_t *native, const uint8_t *bits, unsigned bits_size, uECC_Curve curve) {
  unsigned     num_n_bytes = BITS_TO_BYTES(curve->num_n_bits);
  unsigned     num_n_words = BITS_TO_WORDS(curve->num_n_bits);
  int          shift;
  uECC_word_t  carry;
  uECC_word_t *ptr;

  if (bits_size > num_n_bytes) {
    bits_size = num_n_bytes;
  }

  uECC_vli_clear(native, num_n_words);
  uECC_vli_bytesToNative(native, bits, bits_size);
  if (bits_size * 8 <= (unsigned)curve->num_n_bits) {
    return;
  }
  shift = bits_size * 8 - curve->num_n_bits;
  carry = 0;
  ptr   = native + num_n_words;
  while (ptr-- > native) {
    uECC_word_t temp = *ptr;
    *ptr             = (temp >> shift) | carry;
    carry            = temp << (uECC_WORD_BITS - shift);
  }

  /* Reduce mod curve_n */
  if (uECC_vli_cmp_unsafe(curve->n, native, num_n_words) != 1) {
    uECC_vli_sub(native, native, curve->n, num_n_words);
  }
}

int uECC_sign_with_k(const uint8_t *private_key, const uint8_t *message_hash, unsigned hash_size, uECC_word_t *k, uint8_t *signature, uECC_Curve curve) {
  uECC_word_t  tmp[NUM_ECC_WORDS];
  uECC_word_t  s[NUM_ECC_WORDS];
  uECC_word_t *k2[2]     = {tmp, s};
  uECC_word_t *initial_Z = 0;
  uECC_word_t  p[NUM_ECC_WORDS * 2];
  uECC_word_t  carry;
  wordcount_t  num_words   = curve->num_words;
  wordcount_t  num_n_words = BITS_TO_WORDS(curve->num_n_bits);
  bitcount_t   num_n_bits  = curve->num_n_bits;

  /* Make sure 0 < k < curve_n */
  if (uECC_vli_isZero(k, num_words) || uECC_vli_cmp(curve->n, k, num_n_words) != 1) {
    return 0;
  }

  carry = regularize_k(k, tmp, s, curve);
  /* If an RNG function was specified, try to get a random initial Z value to improve
     protection against side-channel attacks. */
  if (g_rng_function) {
    if (!uECC_generate_random_int(k2[carry], curve->p, num_words)) {
      return 0;
    }
    initial_Z = k2[carry];
  }
  EccPoint_mult(p, curve->G, k2[!carry], initial_Z, num_n_bits + 1, curve);
  if (uECC_vli_isZero(p, num_words)) {
    return 0;
  }

  /* If an RNG function was specified, get a random number
      to prevent side channel analysis of k. */
  if (!g_rng_function) {
    uECC_vli_clear(tmp, num_n_words);
    tmp[0] = 1;
  } else if (!uECC_generate_random_int(tmp, curve->n, num_n_words)) {
    return 0;
  }

  /* Prevent side channel analysis of uECC_vli_modInv() to determine
      bits of k / the private key by premultiplying by a random number */
  uECC_vli_modMult(k, k, tmp, curve->n, num_n_words); /* k' = rand * k */
  uECC_vli_modInv(k, k, curve->n, num_n_words);       /* k = 1 / k' */
  uECC_vli_modMult(k, k, tmp, curve->n, num_n_words); /* k = 1 / k */

  uECC_vli_nativeToBytes(signature, curve->num_bytes, p); /* store r */

  /* tmp = d: */
  uECC_vli_bytesToNative(tmp, private_key, BITS_TO_BYTES(curve->num_n_bits));

  s[num_n_words - 1] = 0;
  uECC_vli_set(s, p, num_words);
  uECC_vli_modMult(s, tmp, s, curve->n, num_n_words); /* s = r*d */

  bits2int(tmp, message_hash, hash_size, curve);
  uECC_vli_modAdd(s, tmp, s, curve->n, num_n_words); /* s = e + r*d */
  uECC_vli_modMult(s, s, k, curve->n, num_n_words);  /* s = (e + r*d) / k */
  if (uECC_vli_numBits(s, num_n_words) > (bitcount_t)curve->num_bytes * 8) {
    return 0;
  }

  uECC_vli_nativeToBytes(signature + curve->num_bytes, curve->num_bytes, s);
  return 1;
}

int uECC_sign(const uint8_t *private_key, const uint8_t *message_hash, unsigned hash_size, uint8_t *signature, uECC_Curve curve) {
  uECC_word_t _random[2 * NUM_ECC_WORDS];
  uECC_word_t k[NUM_ECC_WORDS];
  uECC_word_t tries;

  for (tries = 0; tries < uECC_RNG_MAX_TRIES; ++tries) {
    /* Generating _random uniformly at random: */
    uECC_RNG_Function rng_function = uECC_get_rng();
    if (!rng_function || !rng_function((uint8_t *)_random, 2 * NUM_ECC_WORDS * uECC_WORD_SIZE)) {
      return 0;
    }

    // computing k as modular reduction of _random (see FIPS 186.4 B.5.1):
    uECC_vli_mmod(k, _random, curve->n, BITS_TO_WORDS(curve->num_n_bits));

    if (uECC_sign_with_k(private_key, message_hash, hash_size, k, signature, curve)) {
      return 1;
    }
  }
  return 0;
}

static bitcount_t smax(bitcount_t a, bitcount_t b) { return (a > b ? a : b); }

int uECC_verify(const uint8_t *public_key, const uint8_t *message_hash, unsigned hash_size, const uint8_t *signature, uECC_Curve curve) {
  uECC_word_t        u1[NUM_ECC_WORDS], u2[NUM_ECC_WORDS];
  uECC_word_t        z[NUM_ECC_WORDS];
  uECC_word_t        sum[NUM_ECC_WORDS * 2];
  uECC_word_t        rx[NUM_ECC_WORDS];
  uECC_word_t        ry[NUM_ECC_WORDS];
  uECC_word_t        tx[NUM_ECC_WORDS];
  uECC_word_t        ty[NUM_ECC_WORDS];
  uECC_word_t        tz[NUM_ECC_WORDS];
  const uECC_word_t *points[4];
  const uECC_word_t *point;
  bitcount_t         num_bits;
  bitcount_t         i;

  uECC_word_t _public[NUM_ECC_WORDS * 2];
  uECC_word_t r[NUM_ECC_WORDS], s[NUM_ECC_WORDS];
  wordcount_t num_words   = curve->num_words;
  wordcount_t num_n_words = BITS_TO_WORDS(curve->num_n_bits);

  rx[num_n_words - 1] = 0;
  r[num_n_words - 1]  = 0;
  s[num_n_words - 1]  = 0;

  uECC_vli_bytesToNative(_public, public_key, curve->num_bytes);
  uECC_vli_bytesToNative(_public + num_words, public_key + curve->num_bytes, curve->num_bytes);
  uECC_vli_bytesToNative(r, signature, curve->num_bytes);
  uECC_vli_bytesToNative(s, signature + curve->num_bytes, curve->num_bytes);

  /* r, s must not be 0. */
  if (uECC_vli_isZero(r, num_words) || uECC_vli_isZero(s, num_words)) {
    return 0;
  }

  /* r, s must be < n. */
  if (uECC_vli_cmp_unsafe(curve->n, r, num_n_words) != 1 || uECC_vli_cmp_unsafe(curve->n, s, num_n_words) != 1) {
    return 0;
  }

  /* Calculate u1 and u2. */
  uECC_vli_modInv(z, s, curve->n, num_n_words); /* z = 1/s */
  u1[num_n_words - 1] = 0;
  bits2int(u1, message_hash, hash_size, curve);
  uECC_vli_modMult(u1, u1, z, curve->n, num_n_words); /* u1 = e/s */
  uECC_vli_modMult(u2, r, z, curve->n, num_n_words);  /* u2 = r/s */

  /* Calculate sum = G + Q. */
  uECC_vli_set(sum, _public, num_words);
  uECC_vli_set(sum + num_words, _public + num_words, num_words);
  uECC_vli_set(tx, curve->G, num_words);
  uECC_vli_set(ty, curve->G + num_words, num_words);
  uECC_vli_modSub(z, sum, tx, curve->p, num_words); /* z = x2 - x1 */
  XYcZ_add(tx, ty, sum, sum + num_words, curve);
  uECC_vli_modInv(z, z, curve->p, num_words); /* z = 1/z */
  apply_z(sum, sum + num_words, z, curve);

  /* Use Shamir's trick to calculate u1*G + u2*Q */
  points[0] = 0;
  points[1] = curve->G;
  points[2] = _public;
  points[3] = sum;
  num_bits  = smax(uECC_vli_numBits(u1, num_n_words), uECC_vli_numBits(u2, num_n_words));

  point = points[(!!uECC_vli_testBit(u1, num_bits - 1)) | ((!!uECC_vli_testBit(u2, num_bits - 1)) << 1)];
  uECC_vli_set(rx, point, num_words);
  uECC_vli_set(ry, point + num_words, num_words);
  uECC_vli_clear(z, num_words);
  z[0] = 1;

  for (i = num_bits - 2; i >= 0; --i) {
    uECC_word_t index;
    curve->double_jacobian(rx, ry, z, curve);

    index = (!!uECC_vli_testBit(u1, i)) | ((!!uECC_vli_testBit(u2, i)) << 1);
    point = points[index];
    if (point) {
      uECC_vli_set(tx, point, num_words);
      uECC_vli_set(ty, point + num_words, num_words);
      apply_z(tx, ty, z, curve);
      uECC_vli_modSub(tz, rx, tx, curve->p, num_words); /* Z = x2 - x1 */
      XYcZ_add(tx, ty, rx, ry, curve);
      uECC_vli_modMult_fast(z, z, tz, curve);
    }
  }

  uECC_vli_modInv(z, z, curve->p, num_words); /* Z = 1/Z */
  apply_z(rx, ry, z, curve);

  /* v = x1 (mod n) */
  if (uECC_vli_cmp_unsafe(curve->n, rx, num_n_words) != 1) {
    uECC_vli_sub(rx, rx, curve->n, num_n_words);
  }

  /* Accept only if v == r. */
  return (int)(uECC_vli_equal(rx, r, num_words) == 0);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/ecc_platform_specific.c
================================================
/*  uECC_platform_specific.c - Implementation of platform specific functions*/

/* Copyright (c) 2014, Kenneth MacKay
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  * Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.*/

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 *  uECC_platform_specific.c -- Implementation of platform specific functions
 */

#if defined(unix) || defined(__linux__) || defined(__unix__) || defined(__unix) | (defined(__APPLE__) && defined(__MACH__)) || defined(uECC_POSIX)

/* Some POSIX-like system with /dev/urandom or /dev/random. */
#include 
#include 
#include 

#include 

#ifndef O_CLOEXEC
#define O_CLOEXEC 0
#endif

int default_CSPRNG(uint8_t *dest, unsigned int size) {
  /* input sanity check: */
  if (dest == (uint8_t *)0 || (size <= 0))
    return 0;

  int fd = open("/dev/urandom", O_RDONLY | O_CLOEXEC);
  if (fd == -1) {
    fd = open("/dev/random", O_RDONLY | O_CLOEXEC);
    if (fd == -1) {
      return 0;
    }
  }

  char  *ptr  = (char *)dest;
  size_t left = (size_t)size;
  while (left > 0) {
    ssize_t bytes_read = read(fd, ptr, left);
    if (bytes_read <= 0) { // read failed
      close(fd);
      return 0;
    }
    left -= bytes_read;
    ptr += bytes_read;
  }

  close(fd);
  return 1;
}

#endif /* platform */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/hmac.c
================================================
/* hmac.c - TinyCrypt implementation of the HMAC algorithm */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "hmac.h"
#include "constants.h"
#include "utils.h"

static void rekey(uint8_t *key, const uint8_t *new_key, unsigned int key_size) {
  const uint8_t inner_pad = (uint8_t)0x36;
  const uint8_t outer_pad = (uint8_t)0x5c;
  unsigned int  i;

  for (i = 0; i < key_size; ++i) {
    key[i]                        = inner_pad ^ new_key[i];
    key[i + TC_SHA256_BLOCK_SIZE] = outer_pad ^ new_key[i];
  }
  for (; i < TC_SHA256_BLOCK_SIZE; ++i) {
    key[i]                        = inner_pad;
    key[i + TC_SHA256_BLOCK_SIZE] = outer_pad;
  }
}

int tc_hmac_set_key(TCHmacState_t ctx, const uint8_t *key, unsigned int key_size) {
  /* Input sanity check */
  if (ctx == (TCHmacState_t)0 || key == (const uint8_t *)0 || key_size == 0) {
    return TC_CRYPTO_FAIL;
  }

  const uint8_t               dummy_key[TC_SHA256_BLOCK_SIZE];
  struct tc_hmac_state_struct dummy_state;

  if (key_size <= TC_SHA256_BLOCK_SIZE) {
    /*
     * The next three calls are dummy calls just to avoid
     * certain timing attacks. Without these dummy calls,
     * adversaries would be able to learn whether the key_size is
     * greater than TC_SHA256_BLOCK_SIZE by measuring the time
     * consumed in this process.
     */
    (void)tc_sha256_init(&dummy_state.hash_state);
    (void)tc_sha256_update(&dummy_state.hash_state, dummy_key, key_size);
    (void)tc_sha256_final(&dummy_state.key[TC_SHA256_DIGEST_SIZE], &dummy_state.hash_state);

    /* Actual code for when key_size <= TC_SHA256_BLOCK_SIZE: */
    rekey(ctx->key, key, key_size);
  } else {
    (void)tc_sha256_init(&ctx->hash_state);
    (void)tc_sha256_update(&ctx->hash_state, key, key_size);
    (void)tc_sha256_final(&ctx->key[TC_SHA256_DIGEST_SIZE], &ctx->hash_state);
    rekey(ctx->key, &ctx->key[TC_SHA256_DIGEST_SIZE], TC_SHA256_DIGEST_SIZE);
  }

  return TC_CRYPTO_SUCCESS;
}

int tc_hmac_init(TCHmacState_t ctx) {
  /* input sanity check: */
  if (ctx == (TCHmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  (void)tc_sha256_init(&ctx->hash_state);
  (void)tc_sha256_update(&ctx->hash_state, ctx->key, TC_SHA256_BLOCK_SIZE);

  return TC_CRYPTO_SUCCESS;
}

int tc_hmac_update(TCHmacState_t ctx, const void *data, unsigned int data_length) {
  /* input sanity check: */
  if (ctx == (TCHmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  (void)tc_sha256_update(&ctx->hash_state, data, data_length);

  return TC_CRYPTO_SUCCESS;
}

int tc_hmac_final(uint8_t *tag, unsigned int taglen, TCHmacState_t ctx) {
  /* input sanity check: */
  if (tag == (uint8_t *)0 || taglen != TC_SHA256_DIGEST_SIZE || ctx == (TCHmacState_t)0) {
    return TC_CRYPTO_FAIL;
  }

  (void)tc_sha256_final(tag, &ctx->hash_state);

  (void)tc_sha256_init(&ctx->hash_state);
  (void)tc_sha256_update(&ctx->hash_state, &ctx->key[TC_SHA256_BLOCK_SIZE], TC_SHA256_BLOCK_SIZE);
  (void)tc_sha256_update(&ctx->hash_state, tag, TC_SHA256_DIGEST_SIZE);
  (void)tc_sha256_final(tag, &ctx->hash_state);

  /* destroy the current state */
  _set(ctx, 0, sizeof(*ctx));

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/hmac_prng.c
================================================
/* hmac_prng.c - TinyCrypt implementation of HMAC-PRNG */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "hmac_prng.h"
#include "constants.h"
#include "hmac.h"
#include "utils.h"

/*
 * min bytes in the seed string.
 * MIN_SLEN*8 must be at least the expected security level.
 */
static const unsigned int MIN_SLEN = 32;

/*
 * max bytes in the seed string;
 * SP800-90A specifies a maximum of 2^35 bits (i.e., 2^32 bytes).
 */
static const unsigned int MAX_SLEN = UINT32_MAX;

/*
 * max bytes in the personalization string;
 * SP800-90A specifies a maximum of 2^35 bits (i.e., 2^32 bytes).
 */
static const unsigned int MAX_PLEN = UINT32_MAX;

/*
 * max bytes in the additional_info string;
 * SP800-90A specifies a maximum of 2^35 bits (i.e., 2^32 bytes).
 */
static const unsigned int MAX_ALEN = UINT32_MAX;

/*
 * max number of generates between re-seeds;
 * TinyCrypt accepts up to (2^32 - 1) which is the maximal value of
 * a 32-bit unsigned int variable, while SP800-90A specifies a maximum of 2^48.
 */
static const unsigned int MAX_GENS = UINT32_MAX;

/*
 * maximum bytes per generate call;
 * SP800-90A specifies a maximum up to 2^19.
 */
static const unsigned int MAX_OUT = (1 << 19);

/*
 * Assumes: prng != NULL
 */
static void update(TCHmacPrng_t prng, const uint8_t *data, unsigned int datalen, const uint8_t *additional_data, unsigned int additional_datalen) {
  const uint8_t separator0 = 0x00;
  const uint8_t separator1 = 0x01;

  /* configure the new prng key into the prng's instance of hmac */
  tc_hmac_set_key(&prng->h, prng->key, sizeof(prng->key));

  /* use current state, e and separator 0 to compute a new prng key: */
  (void)tc_hmac_init(&prng->h);
  (void)tc_hmac_update(&prng->h, prng->v, sizeof(prng->v));
  (void)tc_hmac_update(&prng->h, &separator0, sizeof(separator0));

  if (data && datalen)
    (void)tc_hmac_update(&prng->h, data, datalen);
  if (additional_data && additional_datalen)
    (void)tc_hmac_update(&prng->h, additional_data, additional_datalen);

  (void)tc_hmac_final(prng->key, sizeof(prng->key), &prng->h);

  /* configure the new prng key into the prng's instance of hmac */
  (void)tc_hmac_set_key(&prng->h, prng->key, sizeof(prng->key));

  /* use the new key to compute a new state variable v */
  (void)tc_hmac_init(&prng->h);
  (void)tc_hmac_update(&prng->h, prng->v, sizeof(prng->v));
  (void)tc_hmac_final(prng->v, sizeof(prng->v), &prng->h);

  if (data == 0 || datalen == 0)
    return;

  /* configure the new prng key into the prng's instance of hmac */
  tc_hmac_set_key(&prng->h, prng->key, sizeof(prng->key));

  /* use current state, e and separator 1 to compute a new prng key: */
  (void)tc_hmac_init(&prng->h);
  (void)tc_hmac_update(&prng->h, prng->v, sizeof(prng->v));
  (void)tc_hmac_update(&prng->h, &separator1, sizeof(separator1));
  (void)tc_hmac_update(&prng->h, data, datalen);
  if (additional_data && additional_datalen)
    (void)tc_hmac_update(&prng->h, additional_data, additional_datalen);
  (void)tc_hmac_final(prng->key, sizeof(prng->key), &prng->h);

  /* configure the new prng key into the prng's instance of hmac */
  (void)tc_hmac_set_key(&prng->h, prng->key, sizeof(prng->key));

  /* use the new key to compute a new state variable v */
  (void)tc_hmac_init(&prng->h);
  (void)tc_hmac_update(&prng->h, prng->v, sizeof(prng->v));
  (void)tc_hmac_final(prng->v, sizeof(prng->v), &prng->h);
}

int tc_hmac_prng_init(TCHmacPrng_t prng, const uint8_t *personalization, unsigned int plen) {
  /* input sanity check: */
  if (prng == (TCHmacPrng_t)0 || personalization == (uint8_t *)0 || plen > MAX_PLEN) {
    return TC_CRYPTO_FAIL;
  }

  /* put the generator into a known state: */
  _set(prng->key, 0x00, sizeof(prng->key));
  _set(prng->v, 0x01, sizeof(prng->v));

  update(prng, personalization, plen, 0, 0);

  /* force a reseed before allowing tc_hmac_prng_generate to succeed: */
  prng->countdown = 0;

  return TC_CRYPTO_SUCCESS;
}

int tc_hmac_prng_reseed(TCHmacPrng_t prng, const uint8_t *seed, unsigned int seedlen, const uint8_t *additional_input, unsigned int additionallen) {
  /* input sanity check: */
  if (prng == (TCHmacPrng_t)0 || seed == (const uint8_t *)0 || seedlen < MIN_SLEN || seedlen > MAX_SLEN) {
    return TC_CRYPTO_FAIL;
  }

  if (additional_input != (const uint8_t *)0) {
    /*
     * Abort if additional_input is provided but has inappropriate
     * length
     */
    if (additionallen == 0 || additionallen > MAX_ALEN) {
      return TC_CRYPTO_FAIL;
    } else {
      /* call update for the seed and additional_input */
      update(prng, seed, seedlen, additional_input, additionallen);
    }
  } else {
    /* call update only for the seed */
    update(prng, seed, seedlen, 0, 0);
  }

  /* ... and enable hmac_prng_generate */
  prng->countdown = MAX_GENS;

  return TC_CRYPTO_SUCCESS;
}

int tc_hmac_prng_generate(uint8_t *out, unsigned int outlen, TCHmacPrng_t prng) {
  unsigned int bufferlen;

  /* input sanity check: */
  if (out == (uint8_t *)0 || prng == (TCHmacPrng_t)0 || outlen == 0 || outlen > MAX_OUT) {
    return TC_CRYPTO_FAIL;
  } else if (prng->countdown == 0) {
    return TC_HMAC_PRNG_RESEED_REQ;
  }

  prng->countdown--;

  while (outlen != 0) {
    /* configure the new prng key into the prng's instance of hmac */
    tc_hmac_set_key(&prng->h, prng->key, sizeof(prng->key));

    /* operate HMAC in OFB mode to create "random" outputs */
    (void)tc_hmac_init(&prng->h);
    (void)tc_hmac_update(&prng->h, prng->v, sizeof(prng->v));
    (void)tc_hmac_final(prng->v, sizeof(prng->v), &prng->h);

    bufferlen = (TC_SHA256_DIGEST_SIZE > outlen) ? outlen : TC_SHA256_DIGEST_SIZE;
    (void)_copy(out, bufferlen, prng->v, bufferlen);

    out += bufferlen;
    outlen = (outlen > TC_SHA256_DIGEST_SIZE) ? (outlen - TC_SHA256_DIGEST_SIZE) : 0;
  }

  /* block future PRNG compromises from revealing past state */
  update(prng, 0, 0, 0, 0);

  return TC_CRYPTO_SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/sha256.c
================================================
/* sha256.c - TinyCrypt SHA-256 crypto hash algorithm implementation */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "sha256.h"
#include "constants.h"
#include "utils.h"

static void compress(unsigned int *iv, const uint8_t *data);

int tc_sha256_init(TCSha256State_t s) {
  /* input sanity check: */
  if (s == (TCSha256State_t)0) {
    return TC_CRYPTO_FAIL;
  }

  /*
   * Setting the initial state values.
   * These values correspond to the first 32 bits of the fractional parts
   * of the square roots of the first 8 primes: 2, 3, 5, 7, 11, 13, 17
   * and 19.
   */
  _set((uint8_t *)s, 0x00, sizeof(*s));
  s->iv[0] = 0x6a09e667;
  s->iv[1] = 0xbb67ae85;
  s->iv[2] = 0x3c6ef372;
  s->iv[3] = 0xa54ff53a;
  s->iv[4] = 0x510e527f;
  s->iv[5] = 0x9b05688c;
  s->iv[6] = 0x1f83d9ab;
  s->iv[7] = 0x5be0cd19;

  return TC_CRYPTO_SUCCESS;
}

int tc_sha256_update(TCSha256State_t s, const uint8_t *data, size_t datalen) {
  /* input sanity check: */
  if (s == (TCSha256State_t)0 || data == (void *)0) {
    return TC_CRYPTO_FAIL;
  } else if (datalen == 0) {
    return TC_CRYPTO_SUCCESS;
  }

  while (datalen-- > 0) {
    s->leftover[s->leftover_offset++] = *(data++);
    if (s->leftover_offset >= TC_SHA256_BLOCK_SIZE) {
      compress(s->iv, s->leftover);
      s->leftover_offset = 0;
      s->bits_hashed += (TC_SHA256_BLOCK_SIZE << 3);
    }
  }

  return TC_CRYPTO_SUCCESS;
}

int tc_sha256_final(uint8_t *digest, TCSha256State_t s) {
  unsigned int i;

  /* input sanity check: */
  if (digest == (uint8_t *)0 || s == (TCSha256State_t)0) {
    return TC_CRYPTO_FAIL;
  }

  s->bits_hashed += (s->leftover_offset << 3);

  s->leftover[s->leftover_offset++] = 0x80; /* always room for one byte */
  if (s->leftover_offset > (sizeof(s->leftover) - 8)) {
    /* there is not room for all the padding in this block */
    _set(s->leftover + s->leftover_offset, 0x00, sizeof(s->leftover) - s->leftover_offset);
    compress(s->iv, s->leftover);
    s->leftover_offset = 0;
  }

  /* add the padding and the length in big-Endian format */
  _set(s->leftover + s->leftover_offset, 0x00, sizeof(s->leftover) - 8 - s->leftover_offset);
  s->leftover[sizeof(s->leftover) - 1] = (uint8_t)(s->bits_hashed);
  s->leftover[sizeof(s->leftover) - 2] = (uint8_t)(s->bits_hashed >> 8);
  s->leftover[sizeof(s->leftover) - 3] = (uint8_t)(s->bits_hashed >> 16);
  s->leftover[sizeof(s->leftover) - 4] = (uint8_t)(s->bits_hashed >> 24);
  s->leftover[sizeof(s->leftover) - 5] = (uint8_t)(s->bits_hashed >> 32);
  s->leftover[sizeof(s->leftover) - 6] = (uint8_t)(s->bits_hashed >> 40);
  s->leftover[sizeof(s->leftover) - 7] = (uint8_t)(s->bits_hashed >> 48);
  s->leftover[sizeof(s->leftover) - 8] = (uint8_t)(s->bits_hashed >> 56);

  /* hash the padding and length */
  compress(s->iv, s->leftover);

  /* copy the iv out to digest */
  for (i = 0; i < TC_SHA256_STATE_BLOCKS; ++i) {
    unsigned int t = *((unsigned int *)&s->iv[i]);
    *digest++      = (uint8_t)(t >> 24);
    *digest++      = (uint8_t)(t >> 16);
    *digest++      = (uint8_t)(t >> 8);
    *digest++      = (uint8_t)(t);
  }

  /* destroy the current state */
  _set(s, 0, sizeof(*s));

  return TC_CRYPTO_SUCCESS;
}

/*
 * Initializing SHA-256 Hash constant words K.
 * These values correspond to the first 32 bits of the fractional parts of the
 * cube roots of the first 64 primes between 2 and 311.
 */
static const unsigned int k256[64] = {0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74,
                                      0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, 0x983e5152, 0xa831c66d,
                                      0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e,
                                      0x92722c85, 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
                                      0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2};

static inline unsigned int ROTR(unsigned int a, unsigned int n) { return (((a) >> n) | ((a) << (32 - n))); }

#define Sigma0(a) (ROTR((a), 2) ^ ROTR((a), 13) ^ ROTR((a), 22))
#define Sigma1(a) (ROTR((a), 6) ^ ROTR((a), 11) ^ ROTR((a), 25))
#define sigma0(a) (ROTR((a), 7) ^ ROTR((a), 18) ^ ((a) >> 3))
#define sigma1(a) (ROTR((a), 17) ^ ROTR((a), 19) ^ ((a) >> 10))

#define Ch(a, b, c)  (((a) & (b)) ^ ((~(a)) & (c)))
#define Maj(a, b, c) (((a) & (b)) ^ ((a) & (c)) ^ ((b) & (c)))

static inline unsigned int BigEndian(const uint8_t **c) {
  unsigned int n = 0;

  n = (((unsigned int)(*((*c)++))) << 24);
  n |= ((unsigned int)(*((*c)++)) << 16);
  n |= ((unsigned int)(*((*c)++)) << 8);
  n |= ((unsigned int)(*((*c)++)));
  return n;
}

static void compress(unsigned int *iv, const uint8_t *data) {
  unsigned int a, b, c, d, e, f, g, h;
  unsigned int s0, s1;
  unsigned int t1, t2;
  unsigned int work_space[16];
  unsigned int n;
  unsigned int i;

  a = iv[0];
  b = iv[1];
  c = iv[2];
  d = iv[3];
  e = iv[4];
  f = iv[5];
  g = iv[6];
  h = iv[7];

  for (i = 0; i < 16; ++i) {
    n  = BigEndian(&data);
    t1 = work_space[i] = n;
    t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    t2 = Sigma0(a) + Maj(a, b, c);
    h  = g;
    g  = f;
    f  = e;
    e  = d + t1;
    d  = c;
    c  = b;
    b  = a;
    a  = t1 + t2;
  }

  for (; i < 64; ++i) {
    s0 = work_space[(i + 1) & 0x0f];
    s0 = sigma0(s0);
    s1 = work_space[(i + 14) & 0x0f];
    s1 = sigma1(s1);

    t1 = work_space[i & 0xf] += s0 + s1 + work_space[(i + 9) & 0xf];
    t1 += h + Sigma1(e) + Ch(e, f, g) + k256[i];
    t2 = Sigma0(a) + Maj(a, b, c);
    h  = g;
    g  = f;
    f  = e;
    e  = d + t1;
    d  = c;
    c  = b;
    b  = a;
    a  = t1 + t2;
  }

  iv[0] += a;
  iv[1] += b;
  iv[2] += c;
  iv[3] += d;
  iv[4] += e;
  iv[5] += f;
  iv[6] += g;
  iv[7] += h;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/tinycrypt/source/utils.c
================================================
/* utils.c - TinyCrypt platform-dependent run-time operations */

/*
 *  Copyright (C) 2017 by Intel Corporation, All Rights Reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *    - Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *    - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 *    - Neither the name of Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 */

#include "utils.h"
#include "constants.h"

#include 

#define MASK_TWENTY_SEVEN 0x1b

unsigned int _copy(uint8_t *to, unsigned int to_len, const uint8_t *from, unsigned int from_len) {
  if (from_len <= to_len) {
    (void)memcpy(to, from, from_len);
    return from_len;
  } else {
    return TC_CRYPTO_FAIL;
  }
}

void _set(void *to, uint8_t val, unsigned int len) { (void)memset(to, val, len); }

/*
 * Doubles the value of a byte for values up to 127.
 */
uint8_t _double_byte(uint8_t a) { return ((a << 1) ^ ((a >> 7) * MASK_TWENTY_SEVEN)); }

int _compare(const uint8_t *a, const uint8_t *b, size_t size) {
  const uint8_t *tempa  = a;
  const uint8_t *tempb  = b;
  uint8_t        result = 0;

  for (unsigned int i = 0; i < size; i++) {
    result |= tempa[i] ^ tempb[i];
  }
  return result;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/utils.c
================================================
/*****************************************************************************************
 *
 * @file utils.c
 *
 * @brief entry
 *
 * Copyright (C) Bouffalo Lab 2019
 *
 * History: 2019-11 crealted by Lanlan Gong @ Shanghai
 *
 *****************************************************************************************/
#include 
#include 
#include 

void reverse_bytearray(uint8_t *src, uint8_t *result, int array_size) {
  for (int i = 0; i < array_size; i++) {
    result[array_size - i - 1] = src[i];
  }
}

unsigned int find_msb_set(uint32_t data) {
  uint32_t count = 0;
  uint32_t mask  = 0x80000000;

  if (!data) {
    return 0;
  }
  while ((data & mask) == 0) {
    count += 1u;
    mask = mask >> 1u;
  }
  return (32 - count);
}

unsigned int find_lsb_set(uint32_t data) {
  uint32_t count = 0;
  uint32_t mask  = 0x00000001;

  if (!data) {
    return 0;
  }
  while ((data & mask) == 0) {
    count += 1u;
    mask = mask << 1u;
  }
  return (1 + count);
}

int char2hex(char c, uint8_t *x) {
  if (c >= '0' && c <= '9') {
    *x = c - '0';
  } else if (c >= 'a' && c <= 'f') {
    *x = c - 'a' + 10;
  } else if (c >= 'A' && c <= 'F') {
    *x = c - 'A' + 10;
  } else {
    return -1;
  }

  return 0;
}

int hex2char(uint8_t x, char *c) {
  if (x <= 9) {
    *c = x + '0';
  } else if (x <= 15) {
    *c = x - 10 + 'a';
  } else {
    return -1;
  }

  return 0;
}

size_t bin2hex(const uint8_t *buf, size_t buflen, char *hex, size_t hexlen) {
  if ((hexlen + 1) < buflen * 2) {
    return 0;
  }

  for (size_t i = 0; i < buflen; i++) {
    if (hex2char(buf[i] >> 4, &hex[2 * i]) < 0) {
      return 0;
    }
    if (hex2char(buf[i] & 0xf, &hex[2 * i + 1]) < 0) {
      return 0;
    }
  }

  hex[2 * buflen] = '\0';
  return 2 * buflen;
}

size_t hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen) {
  uint8_t dec;

  if (buflen < hexlen / 2 + hexlen % 2) {
    return 0;
  }

  /* if hexlen is uneven, insert leading zero nibble */
  if (hexlen % 2) {
    if (char2hex(hex[0], &dec) < 0) {
      return 0;
    }
    buf[0] = dec;
    hex++;
    buf++;
  }

  /* regular hex conversion */
  for (size_t i = 0; i < hexlen / 2; i++) {
    if (char2hex(hex[2 * i], &dec) < 0) {
      return 0;
    }
    buf[i] = dec << 4;

    if (char2hex(hex[2 * i + 1], &dec) < 0) {
      return 0;
    }
    buf[i] += dec;
  }

  return hexlen / 2 + hexlen % 2;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/common/work_q.c
================================================
/*
 * Copyright (c) 2016 Intel Corporation
 * Copyright (c) 2016 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 *
 * Workqueue support functions
 */

#include "errno.h"
#include 
#include 

struct k_thread work_q_thread;
#if !defined(BFLB_BLE)
static BT_STACK_NOINIT(work_q_stack, CONFIG_BT_WORK_QUEUE_STACK_SIZE);
#endif
struct k_work_q g_work_queue_main;

static void k_work_submit_to_queue(struct k_work_q *work_q, struct k_work *work) {
  if (!atomic_test_and_set_bit(work->flags, K_WORK_STATE_PENDING)) {
    k_fifo_put(&work_q->fifo, work);
#if (BFLB_BT_CO_THREAD)
    extern struct k_sem g_poll_sem;
    k_sem_give(&g_poll_sem);
#endif
  }
}

#if defined(BFLB_BLE)
#if (BFLB_BT_CO_THREAD)
void handle_work_queue(void) {
  struct k_work *work;
  work = k_fifo_get(&g_work_queue_main.fifo, K_NO_WAIT);

  if (atomic_test_and_clear_bit(work->flags, K_WORK_STATE_PENDING)) {
    work->handler(work);
  }
}
#else
static void work_queue_main(void *p1) {
  struct k_work *work;
  UNUSED(p1);

  while (1) {
    work = k_fifo_get(&g_work_queue_main.fifo, K_FOREVER);

    if (atomic_test_and_clear_bit(work->flags, K_WORK_STATE_PENDING)) {
      work->handler(work);
    }

    k_yield();
  }
}

int k_work_q_start(void) {
  k_fifo_init(&g_work_queue_main.fifo, 20);
  return k_thread_create(&work_q_thread, "work_q_thread", CONFIG_BT_WORK_QUEUE_STACK_SIZE, work_queue_main, CONFIG_BT_WORK_QUEUE_PRIO);
}
#endif

int k_work_init(struct k_work *work, k_work_handler_t handler) {
  ASSERT(work, "work is NULL");

  atomic_clear(work->flags);
  work->handler = handler;
  return 0;
}

void k_work_submit(struct k_work *work) { k_work_submit_to_queue(&g_work_queue_main, work); }

static void work_timeout(void *timer) {
  /* Parameter timer type is */
  struct k_delayed_work *w = (struct k_delayed_work *)k_timer_get_id(timer);
  if (w->work_q == NULL) {
    return;
  }

  /* submit work to workqueue */
  if (!atomic_test_bit(w->work.flags, K_WORK_STATE_PERIODIC)) {
    k_work_submit_to_queue(w->work_q, &w->work);
    /* detach from workqueue, for cancel to return appropriate status */
    w->work_q = NULL;
  } else {
    /* For periodic timer, restart it.*/
    k_timer_reset(&w->timer);
    k_work_submit_to_queue(w->work_q, &w->work);
  }
}

void k_delayed_work_init(struct k_delayed_work *work, k_work_handler_t handler) {
  ASSERT(work, "delay work is NULL");
  /* Added by bouffalolab */
  k_work_init(&work->work, handler);
  k_timer_init(&work->timer, work_timeout, work);
  work->work_q = NULL;
}

static int k_delayed_work_submit_to_queue(struct k_work_q *work_q, struct k_delayed_work *work, uint32_t delay) {
  int err;

  /* Work cannot be active in multiple queues */
  if (work->work_q && work->work_q != work_q) {
    err = -EADDRINUSE;
    goto done;
  }

  /* Cancel if work has been submitted */
  if (work->work_q == work_q) {
    err = k_delayed_work_cancel(work);

    if (err < 0) {
      goto done;
    }
  }

  if (!delay) {
    /* Submit work if no ticks is 0 */
    k_work_submit_to_queue(work_q, &work->work);
    work->work_q = NULL;
  } else {
    /* Add timeout */
    /* Attach workqueue so the timeout callback can submit it */
    k_timer_start(&work->timer, delay);
    work->work_q = work_q;
  }

  err = 0;

done:
  return err;
}

int k_delayed_work_submit(struct k_delayed_work *work, uint32_t delay) {
  atomic_clear_bit(work->work.flags, K_WORK_STATE_PERIODIC);
  return k_delayed_work_submit_to_queue(&g_work_queue_main, work, delay);
}

/* Added by bouffalolab */
int k_delayed_work_submit_periodic(struct k_delayed_work *work, s32_t period) {
  atomic_set_bit(work->work.flags, K_WORK_STATE_PERIODIC);
  return k_delayed_work_submit_to_queue(&g_work_queue_main, work, period);
}

int k_delayed_work_cancel(struct k_delayed_work *work) {
  int err = 0;

  if (atomic_test_bit(work->work.flags, K_WORK_STATE_PENDING)) {
    err = -EINPROGRESS;
    goto exit;
  }

  if (!work->work_q) {
    err = -EINVAL;
    goto exit;
  }

  k_timer_stop(&work->timer);
  work->work_q         = NULL;
  work->timer.timeout  = 0;
  work->timer.start_ms = 0;

exit:
  return err;
}

s32_t k_delayed_work_remaining_get(struct k_delayed_work *work) {
  int32_t    remain;
  k_timer_t *timer;

  if (work == NULL) {
    return 0;
  }

  timer  = &work->timer;
  remain = timer->timeout - (k_now_ms() - timer->start_ms);
  if (remain < 0) {
    remain = 0;
  }
  return remain;
}

void k_delayed_work_del_timer(struct k_delayed_work *work) {
  if (NULL == work || NULL == work->timer.timer.hdl)
    return;

  k_timer_delete(&work->timer);
  work->timer.timer.hdl = NULL;
}

/* Added by bouffalolab */
int k_delayed_work_free(struct k_delayed_work *work) {
  int err = 0;

  if (atomic_test_bit(work->work.flags, K_WORK_STATE_PENDING)) {
    err = -EINPROGRESS;
    goto exit;
  }

  k_delayed_work_del_timer(work);
  work->work_q         = NULL;
  work->timer.timeout  = 0;
  work->timer.start_ms = 0;

exit:
  return err;
}

#else
static void work_q_main(void *work_q_ptr, void *p2, void *p3) {
  struct k_work_q *work_q = work_q_ptr;

  ARG_UNUSED(p2);
  ARG_UNUSED(p3);

  while (1) {
    struct k_work   *work;
    k_work_handler_t handler;

    work = k_queue_get(&work_q->queue, K_FOREVER);
    if (!work) {
      continue;
    }

    handler = work->handler;

    /* Reset pending state so it can be resubmitted by handler */
    if (atomic_test_and_clear_bit(work->flags, K_WORK_STATE_PENDING)) {
      handler(work);
    }

    /* Make sure we don't hog up the CPU if the FIFO never (or
     * very rarely) gets empty.
     */
    k_yield();
  }
}

void k_work_q_start(struct k_work_q *work_q, k_thread_stack_t *stack, size_t stack_size, int prio) {
  k_queue_init(&work_q->queue, 20);
  k_thread_create(&work_q->thread, stack, stack_size, work_q_main, work_q, 0, 0, prio, 0, 0);
  _k_object_init(work_q);
}

#ifdef CONFIG_SYS_CLOCK_EXISTS
static void work_timeout(struct _timeout *t) {
  struct k_delayed_work *w = CONTAINER_OF(t, struct k_delayed_work, timeout);

  /* submit work to workqueue */
  k_work_submit_to_queue(w->work_q, &w->work);
}

void k_delayed_work_init(struct k_delayed_work *work, k_work_handler_t handler) {
  k_work_init(&work->work, handler);
  _init_timeout(&work->timeout, work_timeout);
  work->work_q = NULL;

  _k_object_init(work);
}

int k_delayed_work_submit_to_queue(struct k_work_q *work_q, struct k_delayed_work *work, s32_t delay) {
  unsigned int key = irq_lock();
  int          err;

  /* Work cannot be active in multiple queues */
  if (work->work_q && work->work_q != work_q) {
    err = -EADDRINUSE;
    goto done;
  }

  /* Cancel if work has been submitted */
  if (work->work_q == work_q) {
    err = k_delayed_work_cancel(work);
    if (err < 0) {
      goto done;
    }
  }

  /* Attach workqueue so the timeout callback can submit it */
  work->work_q = work_q;

  if (!delay) {
    /* Submit work if no ticks is 0 */
    k_work_submit_to_queue(work_q, &work->work);
  } else {
    /* Add timeout */
    _add_timeout(NULL, &work->timeout, NULL, _TICK_ALIGN + _ms_to_ticks(delay));
  }

  err = 0;

done:
  irq_unlock(key);

  return err;
}

int k_delayed_work_cancel(struct k_delayed_work *work) {
  unsigned int key = irq_lock();

  if (!work->work_q) {
    irq_unlock(key);
    return -EINVAL;
  }

  if (k_work_pending(&work->work)) {
    /* Remove from the queue if already submitted */
    if (!k_queue_remove(&work->work_q->queue, &work->work)) {
      irq_unlock(key);
      return -EINVAL;
    }
  } else {
    _abort_timeout(&work->timeout);
  }

  /* Detach from workqueue */
  work->work_q = NULL;

  atomic_clear_bit(work->work.flags, K_WORK_STATE_PENDING);
  irq_unlock(key);

  return 0;
}
#endif /* CONFIG_SYS_CLOCK_EXISTS */
#endif /* BFLB_BLE */

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/hci_onchip/hci_driver.c
================================================
/*
 * Copyright (c) 2016 Nordic Semiconductor ASA
 * Copyright (c) 2016 Vinayak Kariappa Chettimada
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 

#include 
// #include 
// #include 
// #include 
// #include 
#include 

#include 
#include 
#include 

#include 
#include 
#include 

#ifdef CONFIG_CLOCK_CONTROL_NRF5
#include 
#endif

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_DRIVER)
#include "log.h"

// #include "util/util.h"
// #include "hal/ccm.h"
// #include "hal/radio.h"
// #include "ll_sw/pdu.h"
// #include "ll_sw/ctrl.h"
#include "hci_internal.h"
// #include "init.h"
// #include "hal/debug.h"
#if defined(BFLB_BLE)
#include "bl_hci_wrapper.h"
#endif

#define NODE_RX(_node) CONTAINER_OF(_node, struct radio_pdu_node_rx, hdr.onion.node)

#if !defined(BFLB_BLE)
static K_SEM_DEFINE(sem_prio_recv, 0, BT_UINT_MAX);
#endif

K_FIFO_DEFINE(recv_fifo);
#if !defined(BFLB_BLE)
struct k_thread prio_recv_thread_data;
static BT_STACK_NOINIT(prio_recv_thread_stack, CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE);
#endif

struct k_thread recv_thread_data;
#if !defined(BFLB_BLE)
static BT_STACK_NOINIT(recv_thread_stack, CONFIG_BT_RX_STACK_SIZE);
#endif

#if defined(CONFIG_INIT_STACKS)
static u32_t prio_ts;
static u32_t rx_ts;
#endif

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
static struct k_poll_signal hbuf_signal = K_POLL_SIGNAL_INITIALIZER(hbuf_signal);
static sys_slist_t          hbuf_pend;
static s32_t                hbuf_count;
#endif

#if !defined(BFLB_BLE)
static void prio_recv_thread(void *p1, void *p2, void *p3) {
  while (1) {
    struct radio_pdu_node_rx *node_rx;
    u8_t                      num_cmplt;
    u16_t                     handle;

    while ((num_cmplt = radio_rx_get(&node_rx, &handle))) {
#if defined(CONFIG_BT_CONN)
      struct net_buf *buf;

      buf = bt_buf_get_rx(BT_BUF_EVT, K_FOREVER);
      hci_num_cmplt_encode(buf, handle, num_cmplt);
      BT_DBG("Num Complete: 0x%04x:%u", handle, num_cmplt);
      bt_recv_prio(buf);
      k_yield();
#endif
    }

    if (node_rx) {
      radio_rx_dequeue();

      BT_DBG("RX node enqueue");
      k_fifo_put(&recv_fifo, node_rx);

      continue;
    }

    BT_DBG("sem take...");
    k_sem_take(&sem_prio_recv, K_FOREVER);
    BT_DBG("sem taken");

#if defined(CONFIG_INIT_STACKS)
    if (k_uptime_get_32() - prio_ts > K_SECONDS(5)) {
      STACK_ANALYZE("prio recv thread stack", prio_recv_thread_stack);
      prio_ts = k_uptime_get_32();
    }
#endif
  }
}

static inline struct net_buf *encode_node(struct radio_pdu_node_rx *node_rx, s8_t class) {
  struct net_buf *buf = NULL;

  /* Check if we need to generate an HCI event or ACL data */
  switch (class) {
  case HCI_CLASS_EVT_DISCARDABLE:
  case HCI_CLASS_EVT_REQUIRED:
  case HCI_CLASS_EVT_CONNECTION:
    if (class == HCI_CLASS_EVT_DISCARDABLE) {
      buf = bt_buf_get_rx(BT_BUF_EVT, K_NO_WAIT);
    } else {
      buf = bt_buf_get_rx(BT_BUF_EVT, K_FOREVER);
    }
    if (buf) {
      hci_evt_encode(node_rx, buf);
    }
    break;
#if defined(CONFIG_BT_CONN)
  case HCI_CLASS_ACL_DATA:
    /* generate ACL data */
    buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
    hci_acl_encode(node_rx, buf);
    break;
#endif
  default:
    LL_ASSERT(0);
    break;
  }

  radio_rx_fc_set(node_rx->hdr.handle, 0);
  node_rx->hdr.onion.next = 0;
  radio_rx_mem_release(&node_rx);

  return buf;
}

static inline struct net_buf *process_node(struct radio_pdu_node_rx *node_rx) {
  s8_t class          = hci_get_class(node_rx);
  struct net_buf *buf = NULL;

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  if (hbuf_count != -1) {
    bool pend = !sys_slist_is_empty(&hbuf_pend);

    /* controller to host flow control enabled */
    switch (class) {
    case HCI_CLASS_EVT_DISCARDABLE:
    case HCI_CLASS_EVT_REQUIRED:
      break;
    case HCI_CLASS_EVT_CONNECTION:
      /* for conn-related events, only pend is relevant */
      hbuf_count = 1;
      /* fallthrough */
    case HCI_CLASS_ACL_DATA:
      if (pend || !hbuf_count) {
        sys_slist_append(&hbuf_pend, &node_rx->hdr.onion.node);
        BT_DBG("FC: Queuing item: %d", class);
        return NULL;
      }
      break;
    default:
      LL_ASSERT(0);
      break;
    }
  }
#endif

  /* process regular node from radio */
  buf = encode_node(node_rx, class);

  return buf;
}

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
static inline struct net_buf *process_hbuf(struct radio_pdu_node_rx *n) {
  /* shadow total count in case of preemption */
  struct radio_pdu_node_rx *node_rx    = NULL;
  s32_t                     hbuf_total = hci_hbuf_total;
  struct net_buf           *buf        = NULL;
  sys_snode_t              *node       = NULL;
  s8_t class;
  int reset;

  reset = atomic_test_and_clear_bit(&hci_state_mask, HCI_STATE_BIT_RESET);
  if (reset) {
    /* flush queue, no need to free, the LL has already done it */
    sys_slist_init(&hbuf_pend);
  }

  if (hbuf_total <= 0) {
    hbuf_count = -1;
    return NULL;
  }

  /* available host buffers */
  hbuf_count = hbuf_total - (hci_hbuf_sent - hci_hbuf_acked);

  /* host acked ACL packets, try to dequeue from hbuf */
  node = sys_slist_peek_head(&hbuf_pend);
  if (!node) {
    return NULL;
  }

  /* Return early if this iteration already has a node to process */
  node_rx = NODE_RX(node);
  class   = hci_get_class(node_rx);
  if (n) {
    if (class == HCI_CLASS_EVT_CONNECTION || (class == HCI_CLASS_ACL_DATA && hbuf_count)) {
      /* node to process later, schedule an iteration */
      BT_DBG("FC: signalling");
      k_poll_signal_raise(&hbuf_signal, 0x0);
    }
    return NULL;
  }

  switch (class) {
  case HCI_CLASS_EVT_CONNECTION:
    BT_DBG("FC: dequeueing event");
    (void)sys_slist_get(&hbuf_pend);
    break;
  case HCI_CLASS_ACL_DATA:
    if (hbuf_count) {
      BT_DBG("FC: dequeueing ACL data");
      (void)sys_slist_get(&hbuf_pend);
    } else {
      /* no buffers, HCI will signal */
      node = NULL;
    }
    break;
  case HCI_CLASS_EVT_DISCARDABLE:
  case HCI_CLASS_EVT_REQUIRED:
  default:
    LL_ASSERT(0);
    break;
  }

  if (node) {
    buf = encode_node(node_rx, class);
    /* Update host buffers after encoding */
    hbuf_count = hbuf_total - (hci_hbuf_sent - hci_hbuf_acked);
    /* next node */
    node = sys_slist_peek_head(&hbuf_pend);
    if (node) {
      node_rx = NODE_RX(node);
      class   = hci_get_class(node_rx);

      if (class == HCI_CLASS_EVT_CONNECTION || (class == HCI_CLASS_ACL_DATA && hbuf_count)) {
        /* more to process, schedule an
         * iteration
         */
        BT_DBG("FC: signalling");
        k_poll_signal_raise(&hbuf_signal, 0x0);
      }
    }
  }

  return buf;
}
#endif
#endif

#if defined(BFLB_BLE)
static void recv_thread(void *p1) {
  UNUSED(p1);
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  /* @todo: check if the events structure really needs to be static */
  static struct k_poll_event events[2] = {
      K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &hbuf_signal, 0),
      K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &recv_fifo, 0),
  };
#endif

  while (1) {
#if defined(BFLB_BLE)
    struct net_buf *buf = NULL;
    buf                 = net_buf_get(&recv_fifo, K_FOREVER);
    if (buf) {
      BT_DBG("Calling bt_recv(%p)", buf);
      bt_recv(buf);
    }
#else
    struct radio_pdu_node_rx *node_rx = NULL;
    struct net_buf           *buf     = NULL;

    BT_DBG("blocking");
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
    int err;

    err = k_poll(events, 2, K_FOREVER);
    LL_ASSERT(err == 0);
    if (events[0].state == K_POLL_STATE_SIGNALED) {
      events[0].signal->signaled = 0;
    } else if (events[1].state == K_POLL_STATE_FIFO_DATA_AVAILABLE) {
      node_rx = k_fifo_get(events[1].fifo, 0);
    }

    events[0].state = K_POLL_STATE_NOT_READY;
    events[1].state = K_POLL_STATE_NOT_READY;

    /* process host buffers first if any */
    buf = process_hbuf(node_rx);

#else
    node_rx = k_fifo_get(&recv_fifo, K_FOREVER);
#endif
    BT_DBG("unblocked");

    if (node_rx && !buf) {
      /* process regular node from radio */
      buf = process_node(node_rx);
    }

    if (buf) {
      if (buf->len) {
        BT_DBG("Packet in: type:%u len:%u", bt_buf_get_type(buf), buf->len);
        bt_recv(buf);
      } else {
        net_buf_unref(buf);
      }
    }
#endif
    k_yield();

#if defined(CONFIG_INIT_STACKS)
    if (k_uptime_get_32() - rx_ts > K_SECONDS(5)) {
      STACK_ANALYZE("recv thread stack", recv_thread_stack);
      rx_ts = k_uptime_get_32();
    }
#endif
  }
}
#endif

#if !defined(BFLB_BLE)
static int cmd_handle(struct net_buf *buf) {
  struct net_buf *evt;

  evt = hci_cmd_handle(buf);
  if (evt) {
    BT_DBG("Replying with event of %u bytes", evt->len);
    bt_recv_prio(evt);
  }
}

#if defined(CONFIG_BT_CONN)
static int acl_handle(struct net_buf *buf) {
  struct net_buf *evt;
  int             err;

  err = hci_acl_handle(buf, &evt);
  if (evt) {
    BT_DBG("Replying with event of %u bytes", evt->len);
    bt_recv_prio(evt);
  }

  return err;
}
#endif /* CONFIG_BT_CONN */
#endif

static int hci_driver_send(struct net_buf *buf) {
#if !defined(BFLB_BLE)
  u8_t type;
#endif
  int err;

  BT_DBG("enter");

  if (!buf->len) {
    BT_ERR("Empty HCI packet");
    return -EINVAL;
  }

#if defined(BFLB_BLE)
  err = bl_onchiphci_send_2_controller(buf);
  net_buf_unref(buf);
  return err;
#else
  type = bt_buf_get_type(buf);
  switch (type) {
#if defined(CONFIG_BT_CONN)
  case BT_BUF_ACL_OUT:
    err = acl_handle(buf);
    break;
#endif /* CONFIG_BT_CONN */
  case BT_BUF_CMD:
    err = cmd_handle(buf);

    break;
  default:
    BT_ERR("Unknown HCI type %u", type);
    return -EINVAL;
  }

  if (!err) {
    net_buf_unref(buf);
  } else {
  }

  BT_DBG("exit: %d", err);
#endif
  return err;
}

static int hci_driver_open(void) {
#if !defined(BFLB_BLE)
  u32_t err;

  DEBUG_INIT();
  k_sem_init(&sem_prio_recv, 0, BT_UINT_MAX);

  err = ll_init(&sem_prio_recv);

  if (err) {
    BT_ERR("LL initialization failed: %u", err);
    return err;
  }
#endif

#if !defined(BFLB_BLE)
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  hci_init(&hbuf_signal);
#else
  hci_init(NULL);
#endif
#endif
#if (!BFLB_BT_CO_THREAD)
  k_fifo_init(&recv_fifo, 20);
#endif
#if defined(BFLB_BLE)
#if (!BFLB_BT_CO_THREAD)
  k_thread_create(&recv_thread_data, "recv_thread", CONFIG_BT_RX_STACK_SIZE /*K_THREAD_STACK_SIZEOF(recv_thread_stack)*/, recv_thread, K_PRIO_COOP(CONFIG_BT_RX_PRIO));
#endif
#else
  k_thread_create(&prio_recv_thread_data, prio_recv_thread_stack, K_THREAD_STACK_SIZEOF(prio_recv_thread_stack), prio_recv_thread, NULL, NULL, NULL, K_PRIO_COOP(CONFIG_BT_CTLR_RX_PRIO), 0, K_NO_WAIT);
#endif

  BT_DBG("Success.");

  return 0;
}

void hci_driver_enque_recvq(struct net_buf *buf) {
  net_buf_put(&recv_fifo, buf);
#if (BFLB_BT_CO_THREAD)
  extern struct k_sem g_poll_sem;
  k_sem_give(&g_poll_sem);
#endif
}

static const struct bt_hci_driver drv = {
    .name = "Controller",
    .bus  = BT_HCI_DRIVER_BUS_VIRTUAL,
    .open = hci_driver_open,
    .send = hci_driver_send,
};

#if defined(BFLB_BLE)
int hci_driver_init(void) {
  bt_hci_driver_register(&drv);

  return 0;
}
#else
static int _hci_driver_init(struct device *unused) {
  ARG_UNUSED(unused);

  bt_hci_driver_register(&drv);

  return 0;
}
// SYS_INIT(_hci_driver_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/hci_onchip/hci_internal.h
================================================
/*
 * Copyright (c) 2016 Nordic Semiconductor ASA
 * Copyright (c) 2016 Vinayak Kariappa Chettimada
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _HCI_CONTROLLER_H_
#define _HCI_CONTROLLER_H_

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
extern s32_t hci_hbuf_total;
extern u32_t hci_hbuf_sent;
extern u32_t hci_hbuf_acked;
extern atomic_t hci_state_mask;

#define HCI_STATE_BIT_RESET 0
#endif

#define HCI_CLASS_EVT_REQUIRED    0
#define HCI_CLASS_EVT_DISCARDABLE 1
#define HCI_CLASS_EVT_CONNECTION  2
#define HCI_CLASS_ACL_DATA        3

#if defined(CONFIG_SOC_FAMILY_NRF5)
#define BT_HCI_VS_HW_PLAT BT_HCI_VS_HW_PLAT_NORDIC
#if defined(CONFIG_SOC_SERIES_NRF51X)
#define BT_HCI_VS_HW_VAR BT_HCI_VS_HW_VAR_NORDIC_NRF51X;
#elif defined(CONFIG_SOC_SERIES_NRF52X)
#define BT_HCI_VS_HW_VAR BT_HCI_VS_HW_VAR_NORDIC_NRF52X;
#endif
#else
#define BT_HCI_VS_HW_PLAT 0
#define BT_HCI_VS_HW_VAR  0
#endif /* CONFIG_SOC_FAMILY_NRF5 */

void hci_init(struct k_poll_signal *signal_host_buf);
struct net_buf *hci_cmd_handle(struct net_buf *cmd);
#if !defined(BFLB_BLE)
void hci_evt_encode(struct radio_pdu_node_rx *node_rx, struct net_buf *buf);
s8_t hci_get_class(struct radio_pdu_node_rx *node_rx);
#if defined(CONFIG_BT_CONN)
int hci_acl_handle(struct net_buf *acl, struct net_buf **evt);
void hci_acl_encode(struct radio_pdu_node_rx *node_rx, struct net_buf *buf);
void hci_num_cmplt_encode(struct net_buf *buf, u16_t handle, u8_t num);
#endif
#endif //!defined(BFLB_BLE)
#endif /* _HCI_CONTROLLER_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/at.c
================================================
/**
 * @file at.c
 * Generic AT command handling library implementation
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 

#include "at.h"

static void next_list(struct at_client *at) {
  if (at->buf[at->pos] == ',') {
    at->pos++;
  }
}

int at_check_byte(struct net_buf *buf, char check_byte) {
  const unsigned char *str = buf->data;

  if (*str != check_byte) {
    return -EINVAL;
  }
  net_buf_pull(buf, 1);

  return 0;
}

static void skip_space(struct at_client *at) {
  while (at->buf[at->pos] == ' ') {
    at->pos++;
  }
}

int at_get_number(struct at_client *at, uint32_t *val) {
  uint32_t i;

  skip_space(at);

  for (i = 0U, *val = 0U; isdigit((unsigned char)at->buf[at->pos]); at->pos++, i++) {
    *val = *val * 10U + at->buf[at->pos] - '0';
  }

  if (i == 0U) {
    return -ENODATA;
  }

  next_list(at);
  return 0;
}

static bool str_has_prefix(const char *str, const char *prefix) {
  if (strncmp(str, prefix, strlen(prefix)) != 0) {
    return false;
  }

  return true;
}

static int at_parse_result(const char *str, struct net_buf *buf, enum at_result *result) {
  /* Map the result and check for end lf */
  if ((!strncmp(str, "OK", 2)) && (at_check_byte(buf, '\n') == 0)) {
    *result = AT_RESULT_OK;
    return 0;
  }

  if ((!strncmp(str, "ERROR", 5)) && (at_check_byte(buf, '\n')) == 0) {
    *result = AT_RESULT_ERROR;
    return 0;
  }

  return -ENOMSG;
}

static int get_cmd_value(struct at_client *at, struct net_buf *buf, char stop_byte, enum at_cmd_state cmd_state) {
  int         cmd_len = 0;
  uint8_t     pos     = at->pos;
  const char *str     = (char *)buf->data;

  while (cmd_len < buf->len && at->pos != at->buf_max_len) {
    if (*str != stop_byte) {
      at->buf[at->pos++] = *str;
      cmd_len++;
      str++;
      pos = at->pos;
    } else {
      cmd_len++;
      at->buf[at->pos] = '\0';
      at->pos          = 0U;
      at->cmd_state    = cmd_state;
      break;
    }
  }
  net_buf_pull(buf, cmd_len);

  if (pos == at->buf_max_len) {
    return -ENOBUFS;
  }

  return 0;
}

static int get_response_string(struct at_client *at, struct net_buf *buf, char stop_byte, enum at_state state) {
  int         cmd_len = 0;
  uint8_t     pos     = at->pos;
  const char *str     = (char *)buf->data;

  while (cmd_len < buf->len && at->pos != at->buf_max_len) {
    if (*str != stop_byte) {
      at->buf[at->pos++] = *str;
      cmd_len++;
      str++;
      pos = at->pos;
    } else {
      cmd_len++;
      at->buf[at->pos] = '\0';
      at->pos          = 0U;
      at->state        = state;
      break;
    }
  }
  net_buf_pull(buf, cmd_len);

  if (pos == at->buf_max_len) {
    return -ENOBUFS;
  }

  return 0;
}

static void reset_buffer(struct at_client *at) {
  (void)memset(at->buf, 0, at->buf_max_len);
  at->pos = 0U;
}

static int at_state_start(struct at_client *at, struct net_buf *buf) {
  int err;

  err = at_check_byte(buf, '\r');
  if (err < 0) {
    return err;
  }
  at->state = AT_STATE_START_CR;

  return 0;
}

static int at_state_start_cr(struct at_client *at, struct net_buf *buf) {
  int err;

  err = at_check_byte(buf, '\n');
  if (err < 0) {
    return err;
  }
  at->state = AT_STATE_START_LF;

  return 0;
}

static int at_state_start_lf(struct at_client *at, struct net_buf *buf) {
  reset_buffer(at);
  if (at_check_byte(buf, '+') == 0) {
    at->state = AT_STATE_GET_CMD_STRING;
    return 0;
  } else if (isalpha(*buf->data)) {
    at->state = AT_STATE_GET_RESULT_STRING;
    return 0;
  }

  return -ENODATA;
}

static int at_state_get_cmd_string(struct at_client *at, struct net_buf *buf) { return get_response_string(at, buf, ':', AT_STATE_PROCESS_CMD); }

static bool is_cmer(struct at_client *at) {
  if (strncmp(at->buf, "CME ERROR", 9) == 0) {
    return true;
  }

  return false;
}

static int at_state_process_cmd(struct at_client *at, struct net_buf *buf) {
  if (is_cmer(at)) {
    at->state = AT_STATE_PROCESS_AG_NW_ERR;
    return 0;
  }

  if (at->resp) {
    at->resp(at, buf);
    at->resp = NULL;
    return 0;
  }
  at->state = AT_STATE_UNSOLICITED_CMD;
  return 0;
}

static int at_state_get_result_string(struct at_client *at, struct net_buf *buf) { return get_response_string(at, buf, '\r', AT_STATE_PROCESS_RESULT); }

static bool is_ring(struct at_client *at) {
  if (strncmp(at->buf, "RING", 4) == 0) {
    return true;
  }

  return false;
}

static int at_state_process_result(struct at_client *at, struct net_buf *buf) {
  enum at_cme    cme_err;
  enum at_result result;

  if (is_ring(at)) {
    at->state = AT_STATE_UNSOLICITED_CMD;
    return 0;
  }

  if (at_parse_result(at->buf, buf, &result) == 0) {
    if (at->finish) {
      /* cme_err is 0 - Is invalid until result is
       * AT_RESULT_CME_ERROR
       */
      cme_err = 0;
      at->finish(at, result, cme_err);
    }
  }

  /* Reset the state to process unsolicited response */
  at->cmd_state = AT_CMD_START;
  at->state     = AT_STATE_START;

  return 0;
}

int cme_handle(struct at_client *at) {
  enum at_cme cme_err;
  uint32_t    val;

  if (!at_get_number(at, &val) && val <= CME_ERROR_NETWORK_NOT_ALLOWED) {
    cme_err = val;
  } else {
    cme_err = CME_ERROR_UNKNOWN;
  }

  if (at->finish) {
    at->finish(at, AT_RESULT_CME_ERROR, cme_err);
  }

  return 0;
}

static int at_state_process_ag_nw_err(struct at_client *at, struct net_buf *buf) {
  at->cmd_state = AT_CMD_GET_VALUE;
  return at_parse_cmd_input(at, buf, NULL, cme_handle, AT_CMD_TYPE_NORMAL);
}

static int at_state_unsolicited_cmd(struct at_client *at, struct net_buf *buf) {
  if (at->unsolicited) {
    return at->unsolicited(at, buf);
  }

  return -ENODATA;
}

/* The order of handler function should match the enum at_state */
static handle_parse_input_t parser_cb[] = {
    at_state_start,             /* AT_STATE_START */
    at_state_start_cr,          /* AT_STATE_START_CR */
    at_state_start_lf,          /* AT_STATE_START_LF */
    at_state_get_cmd_string,    /* AT_STATE_GET_CMD_STRING */
    at_state_process_cmd,       /* AT_STATE_PROCESS_CMD */
    at_state_get_result_string, /* AT_STATE_GET_RESULT_STRING */
    at_state_process_result,    /* AT_STATE_PROCESS_RESULT */
    at_state_process_ag_nw_err, /* AT_STATE_PROCESS_AG_NW_ERR */
    at_state_unsolicited_cmd    /* AT_STATE_UNSOLICITED_CMD */
};

int at_parse_input(struct at_client *at, struct net_buf *buf) {
  int ret;

  while (buf->len) {
    if (at->state < AT_STATE_START || at->state >= AT_STATE_END) {
      return -EINVAL;
    }
    ret = parser_cb[at->state](at, buf);
    if (ret < 0) {
      /* Reset the state in case of error */
      at->cmd_state = AT_CMD_START;
      at->state     = AT_STATE_START;
      return ret;
    }
  }

  return 0;
}

static int at_cmd_start(struct at_client *at, struct net_buf *buf, const char *prefix, parse_val_t func, enum at_cmd_type type) {
  if (!str_has_prefix(at->buf, prefix)) {
    if (type == AT_CMD_TYPE_NORMAL) {
      at->state = AT_STATE_UNSOLICITED_CMD;
    }
    return -ENODATA;
  }

  if (type == AT_CMD_TYPE_OTHER) {
    /* Skip for Other type such as ..RING.. which does not have
     * values to get processed.
     */
    at->cmd_state = AT_CMD_PROCESS_VALUE;
  } else {
    at->cmd_state = AT_CMD_GET_VALUE;
  }

  return 0;
}

static int at_cmd_get_value(struct at_client *at, struct net_buf *buf, const char *prefix, parse_val_t func, enum at_cmd_type type) {
  /* Reset buffer before getting the values */
  reset_buffer(at);
  return get_cmd_value(at, buf, '\r', AT_CMD_PROCESS_VALUE);
}

static int at_cmd_process_value(struct at_client *at, struct net_buf *buf, const char *prefix, parse_val_t func, enum at_cmd_type type) {
  int ret;

  ret           = func(at);
  at->cmd_state = AT_CMD_STATE_END_LF;

  return ret;
}

static int at_cmd_state_end_lf(struct at_client *at, struct net_buf *buf, const char *prefix, parse_val_t func, enum at_cmd_type type) {
  int err;

  err = at_check_byte(buf, '\n');
  if (err < 0) {
    return err;
  }

  at->cmd_state = AT_CMD_START;
  at->state     = AT_STATE_START;
  return 0;
}

/* The order of handler function should match the enum at_cmd_state */
static handle_cmd_input_t cmd_parser_cb[] = {
    at_cmd_start,         /* AT_CMD_START */
    at_cmd_get_value,     /* AT_CMD_GET_VALUE */
    at_cmd_process_value, /* AT_CMD_PROCESS_VALUE */
    at_cmd_state_end_lf   /* AT_CMD_STATE_END_LF */
};

int at_parse_cmd_input(struct at_client *at, struct net_buf *buf, const char *prefix, parse_val_t func, enum at_cmd_type type) {
  int ret;

  while (buf->len) {
    if (at->cmd_state < AT_CMD_START || at->cmd_state >= AT_CMD_STATE_END) {
      return -EINVAL;
    }
    ret = cmd_parser_cb[at->cmd_state](at, buf, prefix, func, type);
    if (ret < 0) {
      return ret;
    }
    /* Check for main state, the end of cmd parsing and return. */
    if (at->state == AT_STATE_START) {
      return 0;
    }
  }

  return 0;
}

int at_has_next_list(struct at_client *at) { return at->buf[at->pos] != '\0'; }

int at_open_list(struct at_client *at) {
  skip_space(at);

  /* The list shall start with '(' open parenthesis */
  if (at->buf[at->pos] != '(') {
    return -ENODATA;
  }
  at->pos++;

  return 0;
}

int at_close_list(struct at_client *at) {
  skip_space(at);

  if (at->buf[at->pos] != ')') {
    return -ENODATA;
  }
  at->pos++;

  next_list(at);

  return 0;
}

int at_list_get_string(struct at_client *at, char *name, uint8_t len) {
  int i = 0;

  skip_space(at);

  if (at->buf[at->pos] != '"') {
    return -ENODATA;
  }
  at->pos++;

  while (at->buf[at->pos] != '\0' && at->buf[at->pos] != '"') {
    if (i == len) {
      return -ENODATA;
    }
    name[i++] = at->buf[at->pos++];
  }

  if (i == len) {
    return -ENODATA;
  }

  name[i] = '\0';

  if (at->buf[at->pos] != '"') {
    return -ENODATA;
  }
  at->pos++;

  skip_space(at);
  next_list(at);

  return 0;
}

int at_list_get_range(struct at_client *at, uint32_t *min, uint32_t *max) {
  uint32_t low, high;
  int      ret;

  ret = at_get_number(at, &low);
  if (ret < 0) {
    return ret;
  }

  if (at->buf[at->pos] == '-') {
    at->pos++;
    goto out;
  }

  if (!isdigit((unsigned char)at->buf[at->pos])) {
    return -ENODATA;
  }
out:
  ret = at_get_number(at, &high);
  if (ret < 0) {
    return ret;
  }

  *min = low;
  *max = high;

  next_list(at);

  return 0;
}

void at_register_unsolicited(struct at_client *at, at_resp_cb_t unsolicited) { at->unsolicited = unsolicited; }

void at_register(struct at_client *at, at_resp_cb_t resp, at_finish_cb_t finish) {
  at->resp   = resp;
  at->finish = finish;
  at->state  = AT_STATE_START;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/at.h
================================================
/** @file at.h
 *  @brief Internal APIs for AT command handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

enum at_result {
    AT_RESULT_OK,
    AT_RESULT_ERROR,
    AT_RESULT_CME_ERROR
};

enum at_cme {
    CME_ERROR_AG_FAILURE = 0,
    CME_ERROR_NO_CONNECTION_TO_PHONE = 1,
    CME_ERROR_OPERATION_NOT_ALLOWED = 3,
    CME_ERROR_OPERATION_NOT_SUPPORTED = 4,
    CME_ERROR_PH_SIM_PIN_REQUIRED = 5,
    CME_ERROR_SIM_NOT_INSERTED = 10,
    CME_ERROR_SIM_PIN_REQUIRED = 11,
    CME_ERROR_SIM_PUK_REQUIRED = 12,
    CME_ERROR_SIM_FAILURE = 13,
    CME_ERROR_SIM_BUSY = 14,
    CME_ERROR_INCORRECT_PASSWORD = 16,
    CME_ERROR_SIM_PIN2_REQUIRED = 17,
    CME_ERROR_SIM_PUK2_REQUIRED = 18,
    CME_ERROR_MEMORY_FULL = 20,
    CME_ERROR_INVALID_INDEX = 21,
    CME_ERROR_MEMORY_FAILURE = 23,
    CME_ERROR_TEXT_STRING_TOO_LONG = 24,
    CME_ERROR_INVALID_CHARS_IN_TEXT_STRING = 25,
    CME_ERROR_DIAL_STRING_TO_LONG = 26,
    CME_ERROR_INVALID_CHARS_IN_DIAL_STRING = 27,
    CME_ERROR_NO_NETWORK_SERVICE = 30,
    CME_ERROR_NETWORK_TIMEOUT = 31,
    CME_ERROR_NETWORK_NOT_ALLOWED = 32,
    CME_ERROR_UNKNOWN = 33,
};

enum at_state {
    AT_STATE_START,
    AT_STATE_START_CR,
    AT_STATE_START_LF,
    AT_STATE_GET_CMD_STRING,
    AT_STATE_PROCESS_CMD,
    AT_STATE_GET_RESULT_STRING,
    AT_STATE_PROCESS_RESULT,
    AT_STATE_PROCESS_AG_NW_ERR,
    AT_STATE_UNSOLICITED_CMD,
    AT_STATE_END
};

enum at_cmd_state {
    AT_CMD_START,
    AT_CMD_GET_VALUE,
    AT_CMD_PROCESS_VALUE,
    AT_CMD_STATE_END_LF,
    AT_CMD_STATE_END
};

enum at_cmd_type {
    AT_CMD_TYPE_NORMAL,
    AT_CMD_TYPE_UNSOLICITED,
    AT_CMD_TYPE_OTHER
};

struct at_client;

/* Callback at_resp_cb_t used to parse response value received for the
 * particular AT command. Eg: +CIND=
 */
typedef int (*at_resp_cb_t)(struct at_client *at, struct net_buf *buf);

/* Callback at_finish_cb used to monitor the success or failure of the AT
 * command received from server.
 * Argument 'cme_err' is valid only when argument 'result' is equal to
 * AT_RESULT_CME_ERROR
 */
typedef int (*at_finish_cb_t)(struct at_client *at, enum at_result result,
                              enum at_cme cme_err);
typedef int (*parse_val_t)(struct at_client *at);
typedef int (*handle_parse_input_t)(struct at_client *at, struct net_buf *buf);
typedef int (*handle_cmd_input_t)(struct at_client *at, struct net_buf *buf,
                                  const char *prefix, parse_val_t func,
                                  enum at_cmd_type type);

struct at_client {
    char *buf;
    uint8_t pos;
    uint8_t buf_max_len;
    uint8_t state;
    uint8_t cmd_state;
    at_resp_cb_t resp;
    at_resp_cb_t unsolicited;
    at_finish_cb_t finish;
};

/* Register the callback functions */
void at_register(struct at_client *at, at_resp_cb_t resp,
                 at_finish_cb_t finish);
void at_register_unsolicited(struct at_client *at, at_resp_cb_t unsolicited);
int at_get_number(struct at_client *at, uint32_t *val);
/* This parsing will only works for non-fragmented net_buf */
int at_parse_input(struct at_client *at, struct net_buf *buf);
/* This command parsing will only works for non-fragmented net_buf */
int at_parse_cmd_input(struct at_client *at, struct net_buf *buf,
                       const char *prefix, parse_val_t func,
                       enum at_cmd_type type);
int at_check_byte(struct net_buf *buf, char check_byte);
int at_list_get_range(struct at_client *at, uint32_t *min, uint32_t *max);
int at_list_get_string(struct at_client *at, char *name, uint8_t len);
int at_close_list(struct at_client *at);
int at_open_list(struct at_client *at);
int at_has_next_list(struct at_client *at);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/att.c
================================================
/* att.c - Attribute protocol handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 

#include 
#include 

#include 
#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_ATT)
#include "log.h"

#include "hci_core.h"

#include "conn_internal.h"
#include "l2cap_internal.h"
#include "smp.h"

#include "att_internal.h"
#include "gatt_internal.h"

#define ATT_CHAN(_ch)  CONTAINER_OF(_ch, struct bt_att, chan.chan)
#define ATT_REQ(_node) CONTAINER_OF(_node, struct bt_att_req, node)

#define ATT_CMD_MASK 0x40

#define ATT_TIMEOUT K_SECONDS(30)

typedef enum __packed {
  ATT_COMMAND,
  ATT_REQUEST,
  ATT_RESPONSE,
  ATT_NOTIFICATION,
  ATT_CONFIRMATION,
  ATT_INDICATION,
  ATT_UNKNOWN,
} att_type_t;

static att_type_t att_op_get_type(u8_t op);

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
struct bt_attr_data {
  u16_t handle;
  u16_t offset;
};

#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
/* Pool for incoming ATT packets */
NET_BUF_POOL_DEFINE(prep_pool, CONFIG_BT_ATT_PREPARE_COUNT, BT_ATT_MTU, sizeof(struct bt_attr_data), NULL);
#else
struct net_buf_pool prep_pool;
#endif
#endif /* CONFIG_BT_ATT_PREPARE_COUNT */

enum {
  ATT_PENDING_RSP,
  ATT_PENDING_CFM,
  ATT_DISCONNECTED,

  /* Total number of flags - must be at the end of the enum */
  ATT_NUM_FLAGS,
};

/* ATT channel specific context */
struct bt_att {
  /* The channel this context is associated with */
  struct bt_l2cap_le_chan chan;
  ATOMIC_DEFINE(flags, ATT_NUM_FLAGS);
  struct bt_att_req    *req;
  sys_slist_t           reqs;
  struct k_delayed_work timeout_work;
  struct k_sem          tx_sem;
  struct k_fifo         tx_queue;
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  struct k_fifo prep_queue;
#endif
};

#if defined(CONFIG_BT_STACK_PTS)
extern volatile u8_t event_flag;
#endif

static struct bt_att     bt_req_pool[CONFIG_BT_MAX_CONN];
static struct bt_att_req cancel;

#if defined(CONFIG_BLE_AT_CMD)
static u16_t mtu_size = BT_ATT_MTU;
void         set_mtu_size(u16_t size) { mtu_size = size; }
#endif

static void att_req_destroy(struct bt_att_req *req) {
  BT_DBG("req %p", req);

  if (req->buf) {
    net_buf_unref(req->buf);
  }

  if (req->destroy) {
    req->destroy(req);
  }

  (void)memset(req, 0, sizeof(*req));
}

static struct bt_att *att_get(struct bt_conn *conn) {
  struct bt_l2cap_chan *chan;

  chan = bt_l2cap_le_lookup_tx_cid(conn, BT_L2CAP_CID_ATT);
  __ASSERT(chan, "No ATT channel found");

  return CONTAINER_OF(chan, struct bt_att, chan);
}

static bt_conn_tx_cb_t att_cb(struct net_buf *buf);

static int att_send(struct bt_conn *conn, struct net_buf *buf, bt_conn_tx_cb_t cb, void *user_data) {
  struct bt_att_hdr *hdr;

  hdr = (void *)buf->data;

  BT_DBG("code 0x%02x", hdr->code);

#if defined(CONFIG_BT_SMP) && defined(CONFIG_BT_SIGNING)
  if (hdr->code == BT_ATT_OP_SIGNED_WRITE_CMD) {
    int err;

    err = bt_smp_sign(conn, buf);
    if (err) {
      BT_ERR("Error signing data");
      net_buf_unref(buf);
      return err;
    }
  }
#endif
  return bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, buf, cb ? cb : att_cb(buf), user_data);
}

void att_pdu_sent(struct bt_conn *conn, void *user_data) {
  struct bt_att  *att = att_get(conn);
  struct net_buf *buf;

  BT_DBG("conn %p att %p", conn, att);

  while ((buf = net_buf_get(&att->tx_queue, K_NO_WAIT))) {
    /* Check if the queued buf is a request */
    if (att->req && att->req->buf == buf) {
      /* Save request state so it can be resent */
      net_buf_simple_save(&att->req->buf->b, &att->req->state);
    }

    if (!att_send(conn, buf, NULL, NULL)) {
      return;
    }
  }

  k_sem_give(&att->tx_sem);
}

void att_cfm_sent(struct bt_conn *conn, void *user_data) {
  struct bt_att *att = att_get(conn);

  BT_DBG("conn %p att %p", conn, att);

  if (IS_ENABLED(CONFIG_BT_ATT_ENFORCE_FLOW)) {
    atomic_clear_bit(att->flags, ATT_PENDING_CFM);
  }

  att_pdu_sent(conn, user_data);
}

void att_rsp_sent(struct bt_conn *conn, void *user_data) {
  struct bt_att *att = att_get(conn);

  BT_DBG("conn %p att %p", conn, att);

  if (IS_ENABLED(CONFIG_BT_ATT_ENFORCE_FLOW)) {
    atomic_clear_bit(att->flags, ATT_PENDING_RSP);
  }

  att_pdu_sent(conn, user_data);
}

void att_req_sent(struct bt_conn *conn, void *user_data) {
  struct bt_att *att = att_get(conn);

  BT_DBG("conn %p att %p att->req %p", conn, att, att->req);

  /* Start timeout work */
  if (att->req) {
    k_delayed_work_submit(&att->timeout_work, ATT_TIMEOUT);
  }

  att_pdu_sent(conn, user_data);
}

static bt_conn_tx_cb_t att_cb(struct net_buf *buf) {
  switch (att_op_get_type(buf->data[0])) {
  case ATT_RESPONSE:
    return att_rsp_sent;
  case ATT_CONFIRMATION:
    return att_cfm_sent;
  case ATT_REQUEST:
  case ATT_INDICATION:
    return att_req_sent;
  default:
    return att_pdu_sent;
  }
}

static void send_err_rsp(struct bt_conn *conn, u8_t req, u16_t handle, u8_t err) {
  struct bt_att_error_rsp *rsp;
  struct net_buf          *buf;

  /* Ignore opcode 0x00 */
  if (!req) {
    return;
  }

  buf = bt_att_create_pdu(conn, BT_ATT_OP_ERROR_RSP, sizeof(*rsp));
  if (!buf) {
    return;
  }

  rsp          = net_buf_add(buf, sizeof(*rsp));
  rsp->request = req;
  rsp->handle  = sys_cpu_to_le16(handle);
  rsp->error   = err;

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, buf, att_rsp_sent, NULL);
}

static u8_t att_mtu_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn                 *conn = att->chan.chan.conn;
  struct bt_att_exchange_mtu_req *req;
  struct bt_att_exchange_mtu_rsp *rsp;
  struct net_buf                 *pdu;
  u16_t                           mtu_client, mtu_server;

  req = (void *)buf->data;

  mtu_client = sys_le16_to_cpu(req->mtu);

  BT_DBG("Client MTU %u", mtu_client);

  /* Check if MTU is valid */
  if (mtu_client < BT_ATT_DEFAULT_LE_MTU) {
    return BT_ATT_ERR_INVALID_PDU;
  }

  pdu = bt_att_create_pdu(conn, BT_ATT_OP_MTU_RSP, sizeof(*rsp));
  if (!pdu) {
    return BT_ATT_ERR_UNLIKELY;
  }

  mtu_server = BT_ATT_MTU;

  BT_DBG("Server MTU %u", mtu_server);

  rsp      = net_buf_add(pdu, sizeof(*rsp));
  rsp->mtu = sys_cpu_to_le16(mtu_server);

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, pdu, att_rsp_sent, NULL);

  /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part F] page 484:
   *
   * A device's Exchange MTU Request shall contain the same MTU as the
   * device's Exchange MTU Response (i.e. the MTU shall be symmetric).
   */
  att->chan.rx.mtu = MIN(mtu_client, mtu_server);
  att->chan.tx.mtu = att->chan.rx.mtu;

  BT_DBG("Negotiated MTU %u", att->chan.rx.mtu);

#if defined(BFLB_BLE_MTU_CHANGE_CB)
  if (att->chan.chan.ops->mtu_changed)
    att->chan.chan.ops->mtu_changed(&(att->chan.chan), att->chan.rx.mtu);
#endif

  return 0;
}

static inline bool att_is_connected(struct bt_att *att) { return (att->chan.chan.conn->state != BT_CONN_CONNECTED || !atomic_test_bit(att->flags, ATT_DISCONNECTED)); }

static int att_send_req(struct bt_att *att, struct bt_att_req *req) {
  int err;

  __ASSERT_NO_MSG(req);
  __ASSERT_NO_MSG(req->func);
  __ASSERT_NO_MSG(!att->req);

  BT_DBG("req %p", req);

  att->req = req;

  if (k_sem_take(&att->tx_sem, K_NO_WAIT) < 0) {
    k_fifo_put(&att->tx_queue, req->buf);
    return 0;
  }

  /* Save request state so it can be resent */
  net_buf_simple_save(&req->buf->b, &req->state);

  /* Keep a reference for resending in case of an error */
  err = bt_l2cap_send_cb(att->chan.chan.conn, BT_L2CAP_CID_ATT, net_buf_ref(req->buf), att_cb(req->buf), NULL);
  if (err) {
    net_buf_unref(req->buf);
    req->buf = NULL;
    return err;
  }

  return 0;
}

static void att_process(struct bt_att *att) {
  sys_snode_t *node;

  BT_DBG("");

  /* Pull next request from the list */
  node = sys_slist_get(&att->reqs);
  if (!node) {
    return;
  }

  att_send_req(att, ATT_REQ(node));
}

static u8_t att_handle_rsp(struct bt_att *att, void *pdu, u16_t len, u8_t err) {
  bt_att_func_t func;

  BT_DBG("err 0x%02x len %u: %s", err, len, bt_hex(pdu, len));

  /* Cancel timeout if ongoing */
  k_delayed_work_cancel(&att->timeout_work);

  if (!att->req) {
    BT_WARN("No pending ATT request");
    goto process;
  }

  /* Check if request has been cancelled */
  if (att->req == &cancel) {
    att->req = NULL;
    goto process;
  }

  /* Release original buffer */
  if (att->req->buf) {
    net_buf_unref(att->req->buf);
    att->req->buf = NULL;
  }

  /* Reset func so it can be reused by the callback */
  func           = att->req->func;
  att->req->func = NULL;

  if (func) {
    func(att->chan.chan.conn, err, pdu, len, att->req);
  }

  /* Don't destroy if callback had reused the request */
  if (!att->req->func) {
    att_req_destroy(att->req);
  }

  att->req = NULL;

process:
  /* Process pending requests */
  att_process(att);

  return 0;
}

#if defined(CONFIG_BT_GATT_CLIENT)
static u8_t att_mtu_rsp(struct bt_att *att, struct net_buf *buf) {
  struct bt_att_exchange_mtu_rsp *rsp;
  u16_t                           mtu;

  if (!att) {
    return 0;
  }

  rsp = (void *)buf->data;

  mtu = sys_le16_to_cpu(rsp->mtu);

  BT_DBG("Server MTU %u", mtu);

  /* Check if MTU is valid */
  if (mtu < BT_ATT_DEFAULT_LE_MTU) {
    return att_handle_rsp(att, NULL, 0, BT_ATT_ERR_INVALID_PDU);
  }

  att->chan.rx.mtu = MIN(mtu, BT_ATT_MTU);

  /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part F] page 484:
   *
   * A device's Exchange MTU Request shall contain the same MTU as the
   * device's Exchange MTU Response (i.e. the MTU shall be symmetric).
   */
  att->chan.tx.mtu = att->chan.rx.mtu;

  BT_DBG("Negotiated MTU %u", att->chan.rx.mtu);

  return att_handle_rsp(att, rsp, buf->len, 0);
}
#endif /* CONFIG_BT_GATT_CLIENT */

static bool range_is_valid(u16_t start, u16_t end, u16_t *err) {
  /* Handle 0 is invalid */
  if (!start || !end) {
    if (err) {
      *err = 0U;
    }
    return false;
  }

  /* Check if range is valid */
  if (start > end) {
    if (err) {
      *err = start;
    }
    return false;
  }

  return true;
}

struct find_info_data {
  struct bt_att               *att;
  struct net_buf              *buf;
  struct bt_att_find_info_rsp *rsp;
  union {
    struct bt_att_info_16  *info16;
    struct bt_att_info_128 *info128;
  };
};

static u8_t find_info_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct find_info_data *data = user_data;
  struct bt_att         *att  = data->att;

  BT_DBG("handle 0x%04x", attr->handle);

  /* Initialize rsp at first entry */
  if (!data->rsp) {
    data->rsp         = net_buf_add(data->buf, sizeof(*data->rsp));
    data->rsp->format = (attr->uuid->type == BT_UUID_TYPE_16) ? BT_ATT_INFO_16 : BT_ATT_INFO_128;
  }

  switch (data->rsp->format) {
  case BT_ATT_INFO_16:
    if (attr->uuid->type != BT_UUID_TYPE_16) {
      return BT_GATT_ITER_STOP;
    }

    /* Fast forward to next item position */
    data->info16         = net_buf_add(data->buf, sizeof(*data->info16));
    data->info16->handle = sys_cpu_to_le16(attr->handle);
    data->info16->uuid   = sys_cpu_to_le16(BT_UUID_16(attr->uuid)->val);

    if (att->chan.tx.mtu - data->buf->len > sizeof(*data->info16)) {
      return BT_GATT_ITER_CONTINUE;
    }

    break;
  case BT_ATT_INFO_128:
    if (attr->uuid->type != BT_UUID_TYPE_128) {
      return BT_GATT_ITER_STOP;
    }

    /* Fast forward to next item position */
    data->info128         = net_buf_add(data->buf, sizeof(*data->info128));
    data->info128->handle = sys_cpu_to_le16(attr->handle);
    memcpy(data->info128->uuid, BT_UUID_128(attr->uuid)->val, sizeof(data->info128->uuid));

    if (att->chan.tx.mtu - data->buf->len > sizeof(*data->info128)) {
      return BT_GATT_ITER_CONTINUE;
    }
  }

  return BT_GATT_ITER_STOP;
}

static u8_t att_find_info_rsp(struct bt_att *att, u16_t start_handle, u16_t end_handle) {
  struct bt_conn       *conn = att->chan.chan.conn;
  struct find_info_data data;

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_FIND_INFO_RSP, 0);
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att = att;
  bt_gatt_foreach_attr(start_handle, end_handle, find_info_cb, &data);

  if (!data.rsp) {
    net_buf_unref(data.buf);
    /* Respond since handle is set */
    send_err_rsp(conn, BT_ATT_OP_FIND_INFO_REQ, start_handle, BT_ATT_ERR_ATTRIBUTE_NOT_FOUND);
    return 0;
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}

static u8_t att_find_info_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn              *conn = att->chan.chan.conn;
  struct bt_att_find_info_req *req;
  u16_t                        start_handle, end_handle, err_handle;

  req = (void *)buf->data;

  start_handle = sys_le16_to_cpu(req->start_handle);
  end_handle   = sys_le16_to_cpu(req->end_handle);

  BT_DBG("start_handle 0x%04x end_handle 0x%04x", start_handle, end_handle);

  if (!range_is_valid(start_handle, end_handle, &err_handle)) {
    send_err_rsp(conn, BT_ATT_OP_FIND_INFO_REQ, err_handle, BT_ATT_ERR_INVALID_HANDLE);
    return 0;
  }

  return att_find_info_rsp(att, start_handle, end_handle);
}

struct find_type_data {
  struct bt_att              *att;
  struct net_buf             *buf;
  struct bt_att_handle_group *group;
  const void                 *value;
  u8_t                        value_len;
  u8_t                        err;
};

static u8_t find_type_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct find_type_data *data = user_data;
  struct bt_att         *att  = data->att;
  struct bt_conn        *conn = att->chan.chan.conn;
  int                    read;
  u8_t                   uuid[16];

  /* Skip secondary services */
  if (!bt_uuid_cmp(attr->uuid, BT_UUID_GATT_SECONDARY)) {
    goto skip;
  }

  /* Update group end_handle if not a primary service */
  if (bt_uuid_cmp(attr->uuid, BT_UUID_GATT_PRIMARY)) {
    if (data->group && attr->handle > sys_le16_to_cpu(data->group->end_handle)) {
      data->group->end_handle = sys_cpu_to_le16(attr->handle);
    }
    return BT_GATT_ITER_CONTINUE;
  }

  BT_DBG("handle 0x%04x", attr->handle);

  /* stop if there is no space left */
  if (att->chan.tx.mtu - data->buf->len < sizeof(*data->group)) {
    return BT_GATT_ITER_STOP;
  }

  /* Read attribute value and store in the buffer */
  read = attr->read(conn, attr, uuid, sizeof(uuid), 0);
  if (read < 0) {
    /*
     * Since we don't know if it is the service with requested UUID,
     * we cannot respond with an error to this request.
     */
    goto skip;
  }

  /* Check if data matches */
  if (read != data->value_len) {
    /* Use bt_uuid_cmp() to compare UUIDs of different form. */
    struct bt_uuid_128 ref_uuid;
    struct bt_uuid_128 recvd_uuid;

    if (!bt_uuid_create(&recvd_uuid.uuid, data->value, data->value_len)) {
      BT_WARN("Unable to create UUID: size %u", data->value_len);
      goto skip;
    }
    if (!bt_uuid_create(&ref_uuid.uuid, uuid, read)) {
      BT_WARN("Unable to create UUID: size %d", read);
      goto skip;
    }
    if (bt_uuid_cmp(&recvd_uuid.uuid, &ref_uuid.uuid)) {
      goto skip;
    }
  } else if (memcmp(data->value, uuid, read)) {
    goto skip;
  }

  /* If service has been found, error should be cleared */
  data->err = 0x00;

  /* Fast forward to next item position */
  data->group               = net_buf_add(data->buf, sizeof(*data->group));
  data->group->start_handle = sys_cpu_to_le16(attr->handle);
  data->group->end_handle   = sys_cpu_to_le16(attr->handle);

  /* continue to find the end_handle */
  return BT_GATT_ITER_CONTINUE;

skip:
  data->group = NULL;
  return BT_GATT_ITER_CONTINUE;
}

static u8_t att_find_type_rsp(struct bt_att *att, u16_t start_handle, u16_t end_handle, const void *value, u8_t value_len) {
  struct bt_conn       *conn = att->chan.chan.conn;
  struct find_type_data data;

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_FIND_TYPE_RSP, 0);
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att       = att;
  data.group     = NULL;
  data.value     = value;
  data.value_len = value_len;

  /* Pre-set error in case no service will be found */
  data.err = BT_ATT_ERR_ATTRIBUTE_NOT_FOUND;

  bt_gatt_foreach_attr(start_handle, end_handle, find_type_cb, &data);

  /* If error has not been cleared, no service has been found */
  if (data.err) {
    net_buf_unref(data.buf);
    /* Respond since handle is set */
    send_err_rsp(conn, BT_ATT_OP_FIND_TYPE_REQ, start_handle, data.err);

#if defined(CONFIG_BT_STACK_PTS)
    /*PTS sends a request to the iut discover all primary services it contains */
    if (event_flag == att_find_by_type_value_ind) {
      BT_PTS("rsp err : [%d] start_handle = [0x%04x]\r\n", data.err, start_handle);
    }
#endif
    return 0;
  }

#if defined(CONFIG_BT_STACK_PTS)
  /*when PTS sends a request to the iut discover all primary services it contains, set event flag
   * to @att_find_by_type_value_ind make it easy for the user to check whether the messages is correct in the console.
   */
  if (event_flag == att_find_by_type_value_ind) {
    u8_t  i       = 0;
    u8_t *req_val = (u8_t *)data.value;
    u8_t  src[20];

    (void)memcpy(src, req_val, data.value_len);

    BT_PTS("uuid = [");
    for (i = 0; i < value_len; i++) {
      BT_PTS("%02x", src[value_len - 1 - i]);
    }
    BT_PTS("]\r\n");

    BT_PTS("start_handle = [0x%04x] end_handle = [0x%04x]\r\n", data.buf->data[1] | data.buf->data[2] << 8, data.buf->data[3] | data.buf->data[4] << 8);
  }
#endif

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}

static u8_t att_find_type_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn              *conn = att->chan.chan.conn;
  struct bt_att_find_type_req *req;
  u16_t                        start_handle, end_handle, err_handle, type;
  u8_t                        *value;

  req = net_buf_pull_mem(buf, sizeof(*req));

  start_handle = sys_le16_to_cpu(req->start_handle);
  end_handle   = sys_le16_to_cpu(req->end_handle);
  type         = sys_le16_to_cpu(req->type);
  value        = buf->data;

  BT_DBG("start_handle 0x%04x end_handle 0x%04x type %u", start_handle, end_handle, type);

  if (!range_is_valid(start_handle, end_handle, &err_handle)) {
    send_err_rsp(conn, BT_ATT_OP_FIND_TYPE_REQ, err_handle, BT_ATT_ERR_INVALID_HANDLE);
    return 0;
  }

  /* The Attribute Protocol Find By Type Value Request shall be used with
   * the Attribute Type parameter set to the UUID for "Primary Service"
   * and the Attribute Value set to the 16-bit Bluetooth UUID or 128-bit
   * UUID for the specific primary service.
   */
  if (bt_uuid_cmp(BT_UUID_DECLARE_16(type), BT_UUID_GATT_PRIMARY)) {
    send_err_rsp(conn, BT_ATT_OP_FIND_TYPE_REQ, start_handle, BT_ATT_ERR_ATTRIBUTE_NOT_FOUND);
    return 0;
  }

  return att_find_type_rsp(att, start_handle, end_handle, value, buf->len);
}

static u8_t err_to_att(int err) {
  BT_DBG("%d", err);

  if (err < 0 && err >= -0xff) {
    return -err;
  }

  return BT_ATT_ERR_UNLIKELY;
}

struct read_type_data {
  struct bt_att               *att;
  struct bt_uuid              *uuid;
  struct net_buf              *buf;
  struct bt_att_read_type_rsp *rsp;
  struct bt_att_data          *item;
  u8_t                         err;
};

static u8_t read_type_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct read_type_data *data = user_data;
  struct bt_att         *att  = data->att;
  struct bt_conn        *conn = att->chan.chan.conn;
  int                    read;

  /* Skip if doesn't match */
  if (bt_uuid_cmp(attr->uuid, data->uuid)) {
    return BT_GATT_ITER_CONTINUE;
  }

  BT_DBG("handle 0x%04x", attr->handle);

  /*
   * If an attribute in the set of requested attributes would cause an
   * Error Response then this attribute cannot be included in a
   * Read By Type Response and the attributes before this attribute
   * shall be returned
   *
   * If the first attribute in the set of requested attributes would
   * cause an Error Response then no other attributes in the requested
   * attributes can be considered.
   */
  data->err = bt_gatt_check_perm(conn, attr, BT_GATT_PERM_READ_MASK);
  if (data->err) {
    if (data->rsp->len) {
      data->err = 0x00;
    }
    return BT_GATT_ITER_STOP;
  }

  /*
   * If any attribute is founded in handle range it means that error
   * should be changed from pre-set: attr not found error to no error.
   */
  data->err = 0x00;

  /* Fast forward to next item position */
  data->item         = net_buf_add(data->buf, sizeof(*data->item));
  data->item->handle = sys_cpu_to_le16(attr->handle);

  /* Read attribute value and store in the buffer */
  read = attr->read(conn, attr, data->buf->data + data->buf->len, att->chan.tx.mtu - data->buf->len, 0);
  if (read < 0) {
    data->err = err_to_att(read);
    return BT_GATT_ITER_STOP;
  }

  if (!data->rsp->len) {
    /* Set len to be the first item found */
    data->rsp->len = read + sizeof(*data->item);
  } else if (data->rsp->len != read + sizeof(*data->item)) {
    /* All items should have the same size */
    data->buf->len -= sizeof(*data->item);
    return BT_GATT_ITER_STOP;
  }

  net_buf_add(data->buf, read);

  /* return true only if there are still space for more items */
  return att->chan.tx.mtu - data->buf->len > data->rsp->len ? BT_GATT_ITER_CONTINUE : BT_GATT_ITER_STOP;
}

static u8_t att_read_type_rsp(struct bt_att *att, struct bt_uuid *uuid, u16_t start_handle, u16_t end_handle) {
  struct bt_conn       *conn = att->chan.chan.conn;
  struct read_type_data data;

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_TYPE_RSP, sizeof(*data.rsp));
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att      = att;
  data.uuid     = uuid;
  data.rsp      = net_buf_add(data.buf, sizeof(*data.rsp));
  data.rsp->len = 0U;

  /* Pre-set error if no attr will be found in handle */
  data.err = BT_ATT_ERR_ATTRIBUTE_NOT_FOUND;

  bt_gatt_foreach_attr(start_handle, end_handle, read_type_cb, &data);

  if (data.err) {
    net_buf_unref(data.buf);
    /* Response here since handle is set */
    send_err_rsp(conn, BT_ATT_OP_READ_TYPE_REQ, start_handle, data.err);
    return 0;
  }

#if defined(CONFIG_BT_STACK_PTS)
  if (event_flag == att_read_by_type_ind)
    BT_PTS("handle : [0x%04x]\r\n", data.rsp->data->handle);
#endif

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}

static u8_t att_read_type_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn              *conn = att->chan.chan.conn;
  struct bt_att_read_type_req *req;
  u16_t                        start_handle, end_handle, err_handle;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;
  u8_t uuid_len = buf->len - sizeof(*req);

  /* Type can only be UUID16 or UUID128 */
  if (uuid_len != 2 && uuid_len != 16) {
    return BT_ATT_ERR_INVALID_PDU;
  }

  req = net_buf_pull_mem(buf, sizeof(*req));

  start_handle = sys_le16_to_cpu(req->start_handle);
  end_handle   = sys_le16_to_cpu(req->end_handle);
  if (!bt_uuid_create(&u.uuid, req->uuid, uuid_len)) {
    return BT_ATT_ERR_UNLIKELY;
  }

  BT_DBG("start_handle 0x%04x end_handle 0x%04x type %s", start_handle, end_handle, bt_uuid_str(&u.uuid));

  if (!range_is_valid(start_handle, end_handle, &err_handle)) {
    send_err_rsp(conn, BT_ATT_OP_READ_TYPE_REQ, err_handle, BT_ATT_ERR_INVALID_HANDLE);
    return 0;
  }

  return att_read_type_rsp(att, &u.uuid, start_handle, end_handle);
}

struct read_data {
  struct bt_att          *att;
  u16_t                   offset;
  struct net_buf         *buf;
  struct bt_att_read_rsp *rsp;
  u8_t                    err;
};

static u8_t read_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct read_data *data = user_data;
  struct bt_att    *att  = data->att;
  struct bt_conn   *conn = att->chan.chan.conn;
  int               read;

  BT_DBG("handle 0x%04x", attr->handle);

  data->rsp = net_buf_add(data->buf, sizeof(*data->rsp));

  /*
   * If any attribute is founded in handle range it means that error
   * should be changed from pre-set: invalid handle error to no error.
   */
  data->err = 0x00;

  /* Check attribute permissions */
  data->err = bt_gatt_check_perm(conn, attr, BT_GATT_PERM_READ_MASK);
  if (data->err) {
    return BT_GATT_ITER_STOP;
  }

  /* Read attribute value and store in the buffer */
  read = attr->read(conn, attr, data->buf->data + data->buf->len, att->chan.tx.mtu - data->buf->len, data->offset);
  if (read < 0) {
    data->err = err_to_att(read);
    return BT_GATT_ITER_STOP;
  }

  net_buf_add(data->buf, read);

  return BT_GATT_ITER_CONTINUE;
}

static u8_t att_read_rsp(struct bt_att *att, u8_t op, u8_t rsp, u16_t handle, u16_t offset) {
  struct bt_conn  *conn = att->chan.chan.conn;
  struct read_data data;

  if (!bt_gatt_change_aware(conn, true)) {
    return BT_ATT_ERR_DB_OUT_OF_SYNC;
  }

  if (!handle) {
    return BT_ATT_ERR_INVALID_HANDLE;
  }

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, rsp, 0);
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att    = att;
  data.offset = offset;

  /* Pre-set error if no attr will be found in handle */
  data.err = BT_ATT_ERR_INVALID_HANDLE;

  bt_gatt_foreach_attr(handle, handle, read_cb, &data);

  /* In case of error discard data and respond with an error */
  if (data.err) {
    net_buf_unref(data.buf);
    /* Respond here since handle is set */
    send_err_rsp(conn, op, handle, data.err);
    return 0;
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}

static u8_t att_read_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_att_read_req *req;
  u16_t                   handle;

  req = (void *)buf->data;

  handle = sys_le16_to_cpu(req->handle);

  BT_DBG("handle 0x%04x", handle);

  return att_read_rsp(att, BT_ATT_OP_READ_REQ, BT_ATT_OP_READ_RSP, handle, 0);
}

static u8_t att_read_blob_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_att_read_blob_req *req;
  u16_t                        handle, offset;

  req = (void *)buf->data;

  handle = sys_le16_to_cpu(req->handle);
  offset = sys_le16_to_cpu(req->offset);

  BT_DBG("handle 0x%04x offset %u", handle, offset);

  return att_read_rsp(att, BT_ATT_OP_READ_BLOB_REQ, BT_ATT_OP_READ_BLOB_RSP, handle, offset);
}

#if defined(CONFIG_BT_GATT_READ_MULTIPLE)
static u8_t att_read_mult_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn  *conn = att->chan.chan.conn;
  struct read_data data;
  u16_t            handle;

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_MULT_RSP, 0);
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att = att;

  while (buf->len >= sizeof(u16_t)) {
    handle = net_buf_pull_le16(buf);

    BT_DBG("handle 0x%04x ", handle);

    /* An Error Response shall be sent by the server in response to
     * the Read Multiple Request [....] if a read operation is not
     * permitted on any of the Characteristic Values.
     *
     * If handle is not valid then return invalid handle error.
     * If handle is found error will be cleared by read_cb.
     */
    data.err = BT_ATT_ERR_INVALID_HANDLE;

    bt_gatt_foreach_attr(handle, handle, read_cb, &data);

    /* Stop reading in case of error */
    if (data.err) {
      net_buf_unref(data.buf);
      /* Respond here since handle is set */
      send_err_rsp(conn, BT_ATT_OP_READ_MULT_REQ, handle, data.err);
      return 0;
    }
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}
#endif /* CONFIG_BT_GATT_READ_MULTIPLE */

struct read_group_data {
  struct bt_att                *att;
  struct bt_uuid               *uuid;
  struct net_buf               *buf;
  struct bt_att_read_group_rsp *rsp;
  struct bt_att_group_data     *group;
};

static u8_t read_group_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct read_group_data *data = user_data;
  struct bt_att          *att  = data->att;
  struct bt_conn         *conn = att->chan.chan.conn;
  int                     read;

  /* Update group end_handle if attribute is not a service */
  if (bt_uuid_cmp(attr->uuid, BT_UUID_GATT_PRIMARY) && bt_uuid_cmp(attr->uuid, BT_UUID_GATT_SECONDARY)) {
    if (data->group && attr->handle > sys_le16_to_cpu(data->group->end_handle)) {
      data->group->end_handle = sys_cpu_to_le16(attr->handle);
    }
    return BT_GATT_ITER_CONTINUE;
  }

  /* If Group Type don't match skip */
  if (bt_uuid_cmp(attr->uuid, data->uuid)) {
    data->group = NULL;
    return BT_GATT_ITER_CONTINUE;
  }

  BT_DBG("handle 0x%04x", attr->handle);

  /* Stop if there is no space left */
  if (data->rsp->len && att->chan.tx.mtu - data->buf->len < data->rsp->len) {
    return BT_GATT_ITER_STOP;
  }

  /* Fast forward to next group position */
  data->group = net_buf_add(data->buf, sizeof(*data->group));

  /* Initialize group handle range */
  data->group->start_handle = sys_cpu_to_le16(attr->handle);
  data->group->end_handle   = sys_cpu_to_le16(attr->handle);

  /* Read attribute value and store in the buffer */
  read = attr->read(conn, attr, data->buf->data + data->buf->len, att->chan.tx.mtu - data->buf->len, 0);
  if (read < 0) {
    /* TODO: Handle read errors */
    return BT_GATT_ITER_STOP;
  }

  if (!data->rsp->len) {
    /* Set len to be the first group found */
    data->rsp->len = read + sizeof(*data->group);
  } else if (data->rsp->len != read + sizeof(*data->group)) {
    /* All groups entries should have the same size */
    data->buf->len -= sizeof(*data->group);
    return false;
  }

  net_buf_add(data->buf, read);

  /* Continue to find the end handle */
  return BT_GATT_ITER_CONTINUE;
}

static u8_t att_read_group_rsp(struct bt_att *att, struct bt_uuid *uuid, u16_t start_handle, u16_t end_handle) {
  struct bt_conn        *conn = att->chan.chan.conn;
  struct read_group_data data;

  (void)memset(&data, 0, sizeof(data));

  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_GROUP_RSP, sizeof(*data.rsp));
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  data.att      = att;
  data.uuid     = uuid;
  data.rsp      = net_buf_add(data.buf, sizeof(*data.rsp));
  data.rsp->len = 0U;
  data.group    = NULL;

  bt_gatt_foreach_attr(start_handle, end_handle, read_group_cb, &data);

  if (!data.rsp->len) {
    net_buf_unref(data.buf);
    /* Respond here since handle is set */
    send_err_rsp(conn, BT_ATT_OP_READ_GROUP_REQ, start_handle, BT_ATT_ERR_ATTRIBUTE_NOT_FOUND);
    return 0;
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}

static u8_t att_read_group_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn               *conn = att->chan.chan.conn;
  struct bt_att_read_group_req *req;
  u16_t                         start_handle, end_handle, err_handle;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;
  u8_t uuid_len = buf->len - sizeof(*req);

  /* Type can only be UUID16 or UUID128 */
  if (uuid_len != 2 && uuid_len != 16) {
    return BT_ATT_ERR_INVALID_PDU;
  }

  req = net_buf_pull_mem(buf, sizeof(*req));

  start_handle = sys_le16_to_cpu(req->start_handle);
  end_handle   = sys_le16_to_cpu(req->end_handle);

  if (!bt_uuid_create(&u.uuid, req->uuid, uuid_len)) {
    return BT_ATT_ERR_UNLIKELY;
  }

  BT_DBG("start_handle 0x%04x end_handle 0x%04x type %s", start_handle, end_handle, bt_uuid_str(&u.uuid));

  if (!range_is_valid(start_handle, end_handle, &err_handle)) {
    send_err_rsp(conn, BT_ATT_OP_READ_GROUP_REQ, err_handle, BT_ATT_ERR_INVALID_HANDLE);
    return 0;
  }

  /* Core v4.2, Vol 3, sec 2.5.3 Attribute Grouping:
   * Not all of the grouping attributes can be used in the ATT
   * Read By Group Type Request. The "Primary Service" and "Secondary
   * Service" grouping types may be used in the Read By Group Type
   * Request. The "Characteristic" grouping type shall not be used in
   * the ATT Read By Group Type Request.
   */
  if (bt_uuid_cmp(&u.uuid, BT_UUID_GATT_PRIMARY) && bt_uuid_cmp(&u.uuid, BT_UUID_GATT_SECONDARY)) {
    send_err_rsp(conn, BT_ATT_OP_READ_GROUP_REQ, start_handle, BT_ATT_ERR_UNSUPPORTED_GROUP_TYPE);
    return 0;
  }

  return att_read_group_rsp(att, &u.uuid, start_handle, end_handle);
}

struct write_data {
  struct bt_conn *conn;
  struct net_buf *buf;
  u8_t            req;
  const void     *value;
  u16_t           len;
  u16_t           offset;
  u8_t            err;
};

static u8_t write_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct write_data *data = user_data;
  int                write;
  u8_t               flags = 0U;

  BT_DBG("handle 0x%04x offset %u", attr->handle, data->offset);

  /* Check attribute permissions */
  data->err = bt_gatt_check_perm(data->conn, attr, BT_GATT_PERM_WRITE_MASK);
  if (data->err) {
    return BT_GATT_ITER_STOP;
  }

  /* Set command flag if not a request */
  if (!data->req) {
    flags |= BT_GATT_WRITE_FLAG_CMD;
  }

  /* Write attribute value */
  write = attr->write(data->conn, attr, data->value, data->len, data->offset, flags);
  if (write < 0 || write != data->len) {
    data->err = err_to_att(write);
    return BT_GATT_ITER_STOP;
  }

  data->err = 0U;

  return BT_GATT_ITER_CONTINUE;
}

static u8_t att_write_rsp(struct bt_conn *conn, u8_t req, u8_t rsp, u16_t handle, u16_t offset, const void *value, u16_t len) {
  struct write_data data;

  if (!bt_gatt_change_aware(conn, req ? true : false)) {
    return BT_ATT_ERR_DB_OUT_OF_SYNC;
  }

  if (!handle) {
    return BT_ATT_ERR_INVALID_HANDLE;
  }

  (void)memset(&data, 0, sizeof(data));

  /* Only allocate buf if required to respond */
  if (rsp) {
    data.buf = bt_att_create_pdu(conn, rsp, 0);
    if (!data.buf) {
      return BT_ATT_ERR_UNLIKELY;
    }
  }

  data.conn   = conn;
  data.req    = req;
  data.offset = offset;
  data.value  = value;
  data.len    = len;
  data.err    = BT_ATT_ERR_INVALID_HANDLE;

  bt_gatt_foreach_attr(handle, handle, write_cb, &data);

  if (data.err) {
    /* In case of error discard data and respond with an error */
    if (rsp) {
      net_buf_unref(data.buf);
      /* Respond here since handle is set */
      send_err_rsp(conn, req, handle, data.err);
    }
    return req == BT_ATT_OP_EXEC_WRITE_REQ ? data.err : 0;
  }

  if (data.buf) {
    (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);
  }

  return 0;
}

static u8_t att_write_req(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn *conn = att->chan.chan.conn;
  u16_t           handle;

  handle = net_buf_pull_le16(buf);

  BT_DBG("handle 0x%04x", handle);

  return att_write_rsp(conn, BT_ATT_OP_WRITE_REQ, BT_ATT_OP_WRITE_RSP, handle, 0, buf->data, buf->len);
}

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
struct prep_data {
  struct bt_conn *conn;
  struct net_buf *buf;
  const void     *value;
  u16_t           len;
  u16_t           offset;
  u8_t            err;
};

static u8_t prep_write_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct prep_data    *data = user_data;
  struct bt_attr_data *attr_data;
  int                  write;

  BT_DBG("handle 0x%04x offset %u", attr->handle, data->offset);

  /* Check attribute permissions */
  data->err = bt_gatt_check_perm(data->conn, attr, BT_GATT_PERM_WRITE_MASK);
  if (data->err) {
    return BT_GATT_ITER_STOP;
  }

  /* Check if attribute requires handler to accept the data */
  if (!(attr->perm & BT_GATT_PERM_PREPARE_WRITE)) {
    goto append;
  }

  /* Write attribute value to check if device is authorized */
  write = attr->write(data->conn, attr, data->value, data->len, data->offset, BT_GATT_WRITE_FLAG_PREPARE);
  if (write != 0) {
    data->err = err_to_att(write);
    return BT_GATT_ITER_STOP;
  }

append:
  /* Copy data into the outstanding queue */
  data->buf = net_buf_alloc(&prep_pool, K_NO_WAIT);
  if (!data->buf) {
    data->err = BT_ATT_ERR_PREPARE_QUEUE_FULL;
    return BT_GATT_ITER_STOP;
  }

  attr_data         = net_buf_user_data(data->buf);
  attr_data->handle = attr->handle;
  attr_data->offset = data->offset;

  net_buf_add_mem(data->buf, data->value, data->len);

  data->err = 0U;

  return BT_GATT_ITER_CONTINUE;
}

static u8_t att_prep_write_rsp(struct bt_att *att, u16_t handle, u16_t offset, const void *value, u16_t len) {
  struct bt_conn                  *conn = att->chan.chan.conn;
  struct prep_data                 data;
  struct bt_att_prepare_write_rsp *rsp;

  if (!bt_gatt_change_aware(conn, true)) {
    return BT_ATT_ERR_DB_OUT_OF_SYNC;
  }

  if (!handle) {
    return BT_ATT_ERR_INVALID_HANDLE;
  }

  (void)memset(&data, 0, sizeof(data));

  data.conn   = conn;
  data.offset = offset;
  data.value  = value;
  data.len    = len;
  data.err    = BT_ATT_ERR_INVALID_HANDLE;

  bt_gatt_foreach_attr(handle, handle, prep_write_cb, &data);

  if (data.err) {
    /* Respond here since handle is set */
    send_err_rsp(conn, BT_ATT_OP_PREPARE_WRITE_REQ, handle, data.err);
    return 0;
  }

  BT_DBG("buf %p handle 0x%04x offset %u", data.buf, handle, offset);

  /* Store buffer in the outstanding queue */
  net_buf_put(&att->prep_queue, data.buf);

  /* Generate response */
  data.buf = bt_att_create_pdu(conn, BT_ATT_OP_PREPARE_WRITE_RSP, 0);
  if (!data.buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  rsp         = net_buf_add(data.buf, sizeof(*rsp));
  rsp->handle = sys_cpu_to_le16(handle);
  rsp->offset = sys_cpu_to_le16(offset);
  net_buf_add(data.buf, len);
  memcpy(rsp->value, value, len);

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, data.buf, att_rsp_sent, NULL);

  return 0;
}
#endif /* CONFIG_BT_ATT_PREPARE_COUNT */

static u8_t att_prepare_write_req(struct bt_att *att, struct net_buf *buf) {
#if CONFIG_BT_ATT_PREPARE_COUNT == 0
  return BT_ATT_ERR_NOT_SUPPORTED;
#else
  struct bt_att_prepare_write_req *req;
  u16_t                            handle, offset;

  req = net_buf_pull_mem(buf, sizeof(*req));

  handle = sys_le16_to_cpu(req->handle);
  offset = sys_le16_to_cpu(req->offset);

  BT_DBG("handle 0x%04x offset %u", handle, offset);

  return att_prep_write_rsp(att, handle, offset, buf->data, buf->len);
#endif /* CONFIG_BT_ATT_PREPARE_COUNT */
}

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
static u8_t att_exec_write_rsp(struct bt_att *att, u8_t flags) {
  struct bt_conn *conn = att->chan.chan.conn;
  struct net_buf *buf;
  u8_t            err = 0U;

  while ((buf = net_buf_get(&att->prep_queue, K_NO_WAIT))) {
    struct bt_attr_data *data = net_buf_user_data(buf);

    BT_DBG("buf %p handle 0x%04x offset %u", buf, data->handle, data->offset);

    /* Just discard the data if an error was set */
    if (!err && flags == BT_ATT_FLAG_EXEC) {
      err = att_write_rsp(conn, BT_ATT_OP_EXEC_WRITE_REQ, 0, data->handle, data->offset, buf->data, buf->len);
      if (err) {
        /* Respond here since handle is set */
        send_err_rsp(conn, BT_ATT_OP_EXEC_WRITE_REQ, data->handle, err);
      }
    }

    net_buf_unref(buf);
  }

  if (err) {
    return 0;
  }

  /* Generate response */
  buf = bt_att_create_pdu(conn, BT_ATT_OP_EXEC_WRITE_RSP, 0);
  if (!buf) {
    return BT_ATT_ERR_UNLIKELY;
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, buf, att_rsp_sent, NULL);

  return 0;
}
#endif /* CONFIG_BT_ATT_PREPARE_COUNT */

static u8_t att_exec_write_req(struct bt_att *att, struct net_buf *buf) {
#if CONFIG_BT_ATT_PREPARE_COUNT == 0
  return BT_ATT_ERR_NOT_SUPPORTED;
#else
  struct bt_att_exec_write_req *req;

  req = (void *)buf->data;

  BT_DBG("flags 0x%02x", req->flags);

  return att_exec_write_rsp(att, req->flags);
#endif /* CONFIG_BT_ATT_PREPARE_COUNT */
}

static u8_t att_write_cmd(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn *conn = att->chan.chan.conn;
  u16_t           handle;

  handle = net_buf_pull_le16(buf);

  BT_DBG("handle 0x%04x", handle);

  return att_write_rsp(conn, 0, 0, handle, 0, buf->data, buf->len);
}

#if defined(CONFIG_BT_SIGNING)
static u8_t att_signed_write_cmd(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn                 *conn = att->chan.chan.conn;
  struct bt_att_signed_write_cmd *req;
  u16_t                           handle;
  int                             err;

  req = (void *)buf->data;

  handle = sys_le16_to_cpu(req->handle);

  BT_DBG("handle 0x%04x", handle);

  /* Verifying data requires full buffer including attribute header */
  net_buf_push(buf, sizeof(struct bt_att_hdr));
  err = bt_smp_sign_verify(conn, buf);
  if (err) {
    BT_ERR("Error verifying data");
    /* No response for this command */
    return 0;
  }

  net_buf_pull(buf, sizeof(struct bt_att_hdr));
  net_buf_pull(buf, sizeof(*req));

  return att_write_rsp(conn, 0, 0, handle, 0, buf->data, buf->len - sizeof(struct bt_att_signature));
}
#endif /* CONFIG_BT_SIGNING */

#if defined(CONFIG_BT_GATT_CLIENT)
#if defined(CONFIG_BT_SMP)
static int att_change_security(struct bt_conn *conn, u8_t err) {
  bt_security_t sec;

  switch (err) {
  case BT_ATT_ERR_INSUFFICIENT_ENCRYPTION:
    if (conn->sec_level >= BT_SECURITY_L2)
      return -EALREADY;
    sec = BT_SECURITY_L2;
    break;
  case BT_ATT_ERR_AUTHENTICATION:
    if (conn->sec_level < BT_SECURITY_L2) {
      /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part C]
       * page 375:
       *
       * If an LTK is not available, the service request
       * shall be rejected with the error code 'Insufficient
       * Authentication'.
       * Note: When the link is not encrypted, the error code
       * "Insufficient Authentication" does not indicate that
       * MITM protection is required.
       */
      sec = BT_SECURITY_L2;
    } else if (conn->sec_level < BT_SECURITY_L3) {
      /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part C]
       * page 375:
       *
       * If an authenticated pairing is required but only an
       * unauthenticated pairing has occurred and the link is
       * currently encrypted, the service request shall be
       * rejected with the error code 'Insufficient
       * Authentication'.
       * Note: When unauthenticated pairing has occurred and
       * the link is currently encrypted, the error code
       * 'Insufficient Authentication' indicates that MITM
       * protection is required.
       */
      sec = BT_SECURITY_L3;
    } else if (conn->sec_level < BT_SECURITY_L4) {
      /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part C]
       * page 375:
       *
       * If LE Secure Connections authenticated pairing is
       * required but LE legacy pairing has occurred and the
       * link is currently encrypted, the service request
       * shall be rejected with the error code ''Insufficient
       * Authentication'.
       */
      sec = BT_SECURITY_L4;
    } else {
      return -EALREADY;
    }
    break;
  default:
    return -EINVAL;
  }

  return bt_conn_set_security(conn, sec);
}
#endif /* CONFIG_BT_SMP */

static u8_t att_error_rsp(struct bt_att *att, struct net_buf *buf) {
  struct bt_att_error_rsp *rsp;
  u8_t                     err;

  rsp = (void *)buf->data;

  BT_DBG("request 0x%02x handle 0x%04x error 0x%02x", rsp->request, sys_le16_to_cpu(rsp->handle), rsp->error);

  /* Don't retry if there is no req pending or it has been cancelled */
  if (!att->req || att->req == &cancel) {
    err = BT_ATT_ERR_UNLIKELY;
    goto done;
  }

  if (att->req->buf) {
    /* Restore state to be resent */
    net_buf_simple_restore(&att->req->buf->b, &att->req->state);
  }

  err = rsp->error;
#if defined(CONFIG_BT_SMP)
  if (att->req->retrying) {
    goto done;
  }

  /* Check if security needs to be changed */
  if (!att_change_security(att->chan.chan.conn, err)) {
    att->req->retrying = true;
    /* Wait security_changed: TODO: Handle fail case */
    return 0;
  }
#endif /* CONFIG_BT_SMP */

done:
  return att_handle_rsp(att, NULL, 0, err);
}

static u8_t att_handle_find_info_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_find_type_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_read_type_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_read_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_read_blob_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

#if defined(CONFIG_BT_GATT_READ_MULTIPLE)
static u8_t att_handle_read_mult_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}
#endif /* CONFIG_BT_GATT_READ_MULTIPLE */

static u8_t att_handle_read_group_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_write_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_prepare_write_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_handle_exec_write_rsp(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static u8_t att_notify(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn *conn = att->chan.chan.conn;
  u16_t           handle;

  handle = net_buf_pull_le16(buf);
  BT_DBG("handle 0x%04x", handle);

  bt_gatt_notification(conn, handle, buf->data, buf->len);
  return 0;
}

static u8_t att_indicate(struct bt_att *att, struct net_buf *buf) {
  struct bt_conn *conn = att->chan.chan.conn;
  u16_t           handle;

  handle = net_buf_pull_le16(buf);

  BT_DBG("handle 0x%04x", handle);

  bt_gatt_notification(conn, handle, buf->data, buf->len);

  buf = bt_att_create_pdu(conn, BT_ATT_OP_CONFIRM, 0);
  if (!buf) {
    return 0;
  }

  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, buf, att_cfm_sent, NULL);

  return 0;
}
#endif /* CONFIG_BT_GATT_CLIENT */

static u8_t att_confirm(struct bt_att *att, struct net_buf *buf) {
  BT_DBG("");

  return att_handle_rsp(att, buf->data, buf->len, 0);
}

static const struct att_handler {
  u8_t       op;
  u8_t       expect_len;
  att_type_t type;
  u8_t (*func)(struct bt_att *att, struct net_buf *buf);
} handlers[] = {
    {          BT_ATT_OP_MTU_REQ,                              sizeof(struct bt_att_exchange_mtu_req),      ATT_REQUEST,                  att_mtu_req},
    {    BT_ATT_OP_FIND_INFO_REQ,                                 sizeof(struct bt_att_find_info_req),      ATT_REQUEST,            att_find_info_req},
    {    BT_ATT_OP_FIND_TYPE_REQ,                                 sizeof(struct bt_att_find_type_req),      ATT_REQUEST,            att_find_type_req},
    {    BT_ATT_OP_READ_TYPE_REQ,                                 sizeof(struct bt_att_read_type_req),      ATT_REQUEST,            att_read_type_req},
    {         BT_ATT_OP_READ_REQ,                                      sizeof(struct bt_att_read_req),      ATT_REQUEST,                 att_read_req},
    {    BT_ATT_OP_READ_BLOB_REQ,                                 sizeof(struct bt_att_read_blob_req),      ATT_REQUEST,            att_read_blob_req},
#if defined(CONFIG_BT_GATT_READ_MULTIPLE)
    {    BT_ATT_OP_READ_MULT_REQ,                                        BT_ATT_READ_MULT_MIN_LEN_REQ,      ATT_REQUEST,            att_read_mult_req},
#endif  /* CONFIG_BT_GATT_READ_MULTIPLE */
    {   BT_ATT_OP_READ_GROUP_REQ,                                sizeof(struct bt_att_read_group_req),      ATT_REQUEST,           att_read_group_req},
    {        BT_ATT_OP_WRITE_REQ,                                     sizeof(struct bt_att_write_req),      ATT_REQUEST,                att_write_req},
    {BT_ATT_OP_PREPARE_WRITE_REQ,                             sizeof(struct bt_att_prepare_write_req),      ATT_REQUEST,        att_prepare_write_req},
    {   BT_ATT_OP_EXEC_WRITE_REQ,                                sizeof(struct bt_att_exec_write_req),      ATT_REQUEST,           att_exec_write_req},
    {          BT_ATT_OP_CONFIRM,                                                                   0, ATT_CONFIRMATION,                  att_confirm},
    {        BT_ATT_OP_WRITE_CMD,                                     sizeof(struct bt_att_write_cmd),      ATT_COMMAND,                att_write_cmd},
#if defined(CONFIG_BT_SIGNING)
    { BT_ATT_OP_SIGNED_WRITE_CMD, (sizeof(struct bt_att_write_cmd) + sizeof(struct bt_att_signature)),      ATT_COMMAND,         att_signed_write_cmd},
#endif  /* CONFIG_BT_SIGNING */
#if defined(CONFIG_BT_GATT_CLIENT)
    {        BT_ATT_OP_ERROR_RSP,                                     sizeof(struct bt_att_error_rsp),     ATT_RESPONSE,                att_error_rsp},
    {          BT_ATT_OP_MTU_RSP,                              sizeof(struct bt_att_exchange_mtu_rsp),     ATT_RESPONSE,                  att_mtu_rsp},
    {    BT_ATT_OP_FIND_INFO_RSP,                                 sizeof(struct bt_att_find_info_rsp),     ATT_RESPONSE,     att_handle_find_info_rsp},
    {    BT_ATT_OP_FIND_TYPE_RSP,                                 sizeof(struct bt_att_find_type_rsp),     ATT_RESPONSE,     att_handle_find_type_rsp},
    {    BT_ATT_OP_READ_TYPE_RSP,                                 sizeof(struct bt_att_read_type_rsp),     ATT_RESPONSE,     att_handle_read_type_rsp},
    {         BT_ATT_OP_READ_RSP,                                      sizeof(struct bt_att_read_rsp),     ATT_RESPONSE,          att_handle_read_rsp},
    {    BT_ATT_OP_READ_BLOB_RSP,                                 sizeof(struct bt_att_read_blob_rsp),     ATT_RESPONSE,     att_handle_read_blob_rsp},
#if defined(CONFIG_BT_GATT_READ_MULTIPLE)
    {    BT_ATT_OP_READ_MULT_RSP,                                 sizeof(struct bt_att_read_mult_rsp),     ATT_RESPONSE,     att_handle_read_mult_rsp},
#endif  /* CONFIG_BT_GATT_READ_MULTIPLE */
    {   BT_ATT_OP_READ_GROUP_RSP,                                sizeof(struct bt_att_read_group_rsp),     ATT_RESPONSE,    att_handle_read_group_rsp},
    {        BT_ATT_OP_WRITE_RSP,                                                                   0,     ATT_RESPONSE,         att_handle_write_rsp},
    {BT_ATT_OP_PREPARE_WRITE_RSP,                             sizeof(struct bt_att_prepare_write_rsp),     ATT_RESPONSE, att_handle_prepare_write_rsp},
    {   BT_ATT_OP_EXEC_WRITE_RSP,                                                                   0,     ATT_RESPONSE,    att_handle_exec_write_rsp},
    {           BT_ATT_OP_NOTIFY,                                        sizeof(struct bt_att_notify), ATT_NOTIFICATION,                   att_notify},
    {         BT_ATT_OP_INDICATE,                                      sizeof(struct bt_att_indicate),   ATT_INDICATION,                 att_indicate},
#endif  /* CONFIG_BT_GATT_CLIENT */
};

static att_type_t att_op_get_type(u8_t op) {
  switch (op) {
  case BT_ATT_OP_MTU_REQ:
  case BT_ATT_OP_FIND_INFO_REQ:
  case BT_ATT_OP_FIND_TYPE_REQ:
  case BT_ATT_OP_READ_TYPE_REQ:
  case BT_ATT_OP_READ_REQ:
  case BT_ATT_OP_READ_BLOB_REQ:
  case BT_ATT_OP_READ_MULT_REQ:
  case BT_ATT_OP_READ_GROUP_REQ:
  case BT_ATT_OP_WRITE_REQ:
  case BT_ATT_OP_PREPARE_WRITE_REQ:
  case BT_ATT_OP_EXEC_WRITE_REQ:
    return ATT_REQUEST;
  case BT_ATT_OP_CONFIRM:
    return ATT_CONFIRMATION;
  case BT_ATT_OP_WRITE_CMD:
  case BT_ATT_OP_SIGNED_WRITE_CMD:
    return ATT_COMMAND;
  case BT_ATT_OP_ERROR_RSP:
  case BT_ATT_OP_MTU_RSP:
  case BT_ATT_OP_FIND_INFO_RSP:
  case BT_ATT_OP_FIND_TYPE_RSP:
  case BT_ATT_OP_READ_TYPE_RSP:
  case BT_ATT_OP_READ_RSP:
  case BT_ATT_OP_READ_BLOB_RSP:
  case BT_ATT_OP_READ_MULT_RSP:
  case BT_ATT_OP_READ_GROUP_RSP:
  case BT_ATT_OP_WRITE_RSP:
  case BT_ATT_OP_PREPARE_WRITE_RSP:
  case BT_ATT_OP_EXEC_WRITE_RSP:
    return ATT_RESPONSE;
  case BT_ATT_OP_NOTIFY:
    return ATT_NOTIFICATION;
  case BT_ATT_OP_INDICATE:
    return ATT_INDICATION;
  }

  if (op & ATT_CMD_MASK) {
    return ATT_COMMAND;
  }

  return ATT_UNKNOWN;
}

static int bt_att_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_att            *att = ATT_CHAN(chan);
  struct bt_att_hdr        *hdr;
  const struct att_handler *handler;
  u8_t                      err;
  size_t                    i;

  if (buf->len < sizeof(*hdr)) {
    BT_ERR("Too small ATT PDU received");
    return 0;
  }

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  BT_DBG("Received ATT code 0x%02x len %u", hdr->code, buf->len);

  for (i = 0, handler = NULL; i < ARRAY_SIZE(handlers); i++) {
    if (hdr->code == handlers[i].op) {
      handler = &handlers[i];
      break;
    }
  }

  if (!handler) {
    BT_WARN("Unhandled ATT code 0x%02x", hdr->code);
    if (att_op_get_type(hdr->code) != ATT_COMMAND) {
      send_err_rsp(chan->conn, hdr->code, 0, BT_ATT_ERR_NOT_SUPPORTED);
    }
    return 0;
  }

  if (IS_ENABLED(CONFIG_BT_ATT_ENFORCE_FLOW)) {
    if (handler->type == ATT_REQUEST && atomic_test_and_set_bit(att->flags, ATT_PENDING_RSP)) {
      BT_WARN("Ignoring unexpected request");
      return 0;
    } else if (handler->type == ATT_INDICATION && atomic_test_and_set_bit(att->flags, ATT_PENDING_CFM)) {
      BT_WARN("Ignoring unexpected indication");
      return 0;
    }
  }

  if (buf->len < handler->expect_len) {
    BT_ERR("Invalid len %u for code 0x%02x", buf->len, hdr->code);
    err = BT_ATT_ERR_INVALID_PDU;
  } else {
    err = handler->func(att, buf);
  }

  if (handler->type == ATT_REQUEST && err) {
    BT_DBG("ATT error 0x%02x", err);
    send_err_rsp(chan->conn, hdr->code, 0, err);
  }

  return 0;
}

static struct bt_att *att_chan_get(struct bt_conn *conn) {
  struct bt_l2cap_chan *chan;
  struct bt_att        *att;

  if (conn->state != BT_CONN_CONNECTED) {
    BT_WARN("Not connected");
    return NULL;
  }

  chan = bt_l2cap_le_lookup_rx_cid(conn, BT_L2CAP_CID_ATT);
  if (!chan) {
    BT_ERR("Unable to find ATT channel");
    return NULL;
  }

  att = ATT_CHAN(chan);
  if (atomic_test_bit(att->flags, ATT_DISCONNECTED)) {
    BT_WARN("ATT context flagged as disconnected");
    return NULL;
  }

  return att;
}

struct net_buf *bt_att_create_pdu(struct bt_conn *conn, u8_t op, size_t len) {
  struct bt_att_hdr *hdr;
  struct net_buf    *buf;
  struct bt_att     *att;

  att = att_chan_get(conn);
  if (!att) {
    return NULL;
  }

  if (len + sizeof(op) > att->chan.tx.mtu) {
    BT_WARN("ATT MTU exceeded, max %u, wanted %zu", att->chan.tx.mtu, len + sizeof(op));
    return NULL;
  }

  switch (att_op_get_type(op)) {
  case ATT_RESPONSE:
  case ATT_CONFIRMATION:
    /* Use a timeout only when responding/confirming */
    buf = bt_l2cap_create_pdu_timeout(NULL, 0, ATT_TIMEOUT);
    break;
  default:
    buf = bt_l2cap_create_pdu(NULL, 0);
  }

  if (!buf) {
    BT_ERR("Unable to allocate buffer for op 0x%02x", op);
    return NULL;
  }

  hdr       = net_buf_add(buf, sizeof(*hdr));
  hdr->code = op;

  return buf;
}

static void att_reset(struct bt_att *att) {
  struct bt_att_req *req, *tmp;
  int                i;
  struct net_buf    *buf;

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  /* Discard queued buffers */
  while ((buf = k_fifo_get(&att->prep_queue, K_NO_WAIT))) {
    net_buf_unref(buf);
  }
#endif /* CONFIG_BT_ATT_PREPARE_COUNT > 0 */

  while ((buf = k_fifo_get(&att->tx_queue, K_NO_WAIT))) {
    net_buf_unref(buf);
  }

  atomic_set_bit(att->flags, ATT_DISCONNECTED);

  /* Ensure that any waiters are woken up */
  for (i = 0; i < CONFIG_BT_ATT_TX_MAX; i++) {
    k_sem_give(&att->tx_sem);
  }

  /* Notify pending requests */
  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&att->reqs, req, tmp, node) {
    if (req->func) {
      req->func(NULL, BT_ATT_ERR_UNLIKELY, NULL, 0, req);
    }

    att_req_destroy(req);
  }

  /* Reset list */
  sys_slist_init(&att->reqs);

  if (!att->req) {
    return;
  }

  /* Notify outstanding request */
  att_handle_rsp(att, NULL, 0, BT_ATT_ERR_UNLIKELY);
}

static void att_timeout(struct k_work *work) {
  struct bt_att           *att = CONTAINER_OF(work, struct bt_att, timeout_work);
  struct bt_l2cap_le_chan *ch  = &att->chan;

  BT_ERR("ATT Timeout");

  /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part F] page 480:
   *
   * A transaction not completed within 30 seconds shall time out. Such a
   * transaction shall be considered to have failed and the local higher
   * layers shall be informed of this failure. No more attribute protocol
   * requests, commands, indications or notifications shall be sent to the
   * target device on this ATT Bearer.
   */
  att_reset(att);

  /* Consider the channel disconnected */
  bt_gatt_disconnected(ch->chan.conn);
  ch->chan.conn = NULL;
}

static void bt_att_connected(struct bt_l2cap_chan *chan) {
  struct bt_att           *att = ATT_CHAN(chan);
  struct bt_l2cap_le_chan *ch  = BT_L2CAP_LE_CHAN(chan);

  BT_DBG("chan %p cid 0x%04x", ch, ch->tx.cid);

  k_fifo_init(&att->tx_queue, 20);
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  k_fifo_init(&att->prep_queue, 20);
#endif

  ch->tx.mtu = BT_ATT_DEFAULT_LE_MTU;
  ch->rx.mtu = BT_ATT_DEFAULT_LE_MTU;

  k_delayed_work_init(&att->timeout_work, att_timeout);
  sys_slist_init(&att->reqs);
}

static void bt_att_disconnected(struct bt_l2cap_chan *chan) {
  struct bt_att           *att = ATT_CHAN(chan);
  struct bt_l2cap_le_chan *ch  = BT_L2CAP_LE_CHAN(chan);

  BT_DBG("chan %p cid 0x%04x", ch, ch->tx.cid);

  att_reset(att);

  bt_gatt_disconnected(ch->chan.conn);

#ifdef BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
  if (att->timeout_work.timer.timer.hdl)
    k_delayed_work_del_timer(&att->timeout_work);

  if (att->tx_queue._queue.hdl) {
    k_queue_free(&att->tx_queue._queue);
    att->tx_queue._queue.hdl = NULL;
  }

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  if (att->prep_queue._queue.hdl) {
    k_queue_free(&att->prep_queue._queue);
    att->prep_queue._queue.hdl = NULL;
  }
#endif

  if (att->tx_sem.sem.hdl)
    k_sem_delete(&att->tx_sem);
#endif
}

#if defined(CONFIG_BT_SMP)
static void bt_att_encrypt_change(struct bt_l2cap_chan *chan, u8_t hci_status) {
  struct bt_att           *att  = ATT_CHAN(chan);
  struct bt_l2cap_le_chan *ch   = BT_L2CAP_LE_CHAN(chan);
  struct bt_conn          *conn = ch->chan.conn;

  BT_DBG("chan %p conn %p handle %u sec_level 0x%02x status 0x%02x", ch, conn, conn->handle, conn->sec_level, hci_status);

  /*
   * If status (HCI status of security procedure) is non-zero, notify
   * outstanding request about security failure.
   */
  if (hci_status) {
    att_handle_rsp(att, NULL, 0, BT_ATT_ERR_AUTHENTICATION);
    return;
  }

  bt_gatt_encrypt_change(conn);

  if (conn->sec_level == BT_SECURITY_L1) {
    return;
  }

  if (!att->req || !att->req->retrying) {
    return;
  }

#if (BFLB_BT_CO_THREAD)
  if (k_sem_take(&att->tx_sem, K_NO_WAIT) < 0) {
    k_fifo_put(&att->tx_queue, att->req->buf);
    return;
  }
#else
  k_sem_take(&att->tx_sem, K_FOREVER);
#endif
  if (!att_is_connected(att)) {
    BT_WARN("Disconnected");
    k_sem_give(&att->tx_sem);
    return;
  }

  BT_DBG("Retrying");

  /* Resend buffer */
  (void)bt_l2cap_send_cb(conn, BT_L2CAP_CID_ATT, att->req->buf, att_cb(att->req->buf), NULL);
  att->req->buf = NULL;
}
#endif /* CONFIG_BT_SMP */

#if defined(BFLB_BLE_MTU_CHANGE_CB)
void bt_att_mtu_changed(struct bt_l2cap_chan *chan, u16_t mtu) { bt_gatt_mtu_changed(chan->conn, mtu); }
#endif

static int bt_att_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) {
  int                             i;
  static struct bt_l2cap_chan_ops ops = {
      .connected    = bt_att_connected,
      .disconnected = bt_att_disconnected,
      .recv         = bt_att_recv,
#if defined(CONFIG_BT_SMP)
      .encrypt_change = bt_att_encrypt_change,
#endif /* CONFIG_BT_SMP */
#if defined(BFLB_BLE_MTU_CHANGE_CB)
      .mtu_changed = bt_att_mtu_changed,
#endif
  };

  BT_DBG("conn %p handle %u", conn, conn->handle);

  for (i = 0; i < ARRAY_SIZE(bt_req_pool); i++) {
    struct bt_att *att = &bt_req_pool[i];

    if (att->chan.chan.conn) {
      continue;
    }

    (void)memset(att, 0, sizeof(*att));
    att->chan.chan.ops = &ops;
    k_sem_init(&att->tx_sem, CONFIG_BT_ATT_TX_MAX, CONFIG_BT_ATT_TX_MAX);

    *chan = &att->chan.chan;

    return 0;
  }

  BT_ERR("No available ATT context for conn %p", conn);

  return -ENOMEM;
}

BT_L2CAP_CHANNEL_DEFINE(att_fixed_chan, BT_L2CAP_CID_ATT, bt_att_accept);

void bt_att_init(void) {
#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
  static struct bt_l2cap_fixed_chan chan = {
      .cid    = BT_L2CAP_CID_ATT,
      .accept = bt_att_accept,
  };

  bt_l2cap_le_fixed_chan_register(&chan);
#endif

#if CONFIG_BT_ATT_PREPARE_COUNT > 0
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(PREP, &prep_pool, CONFIG_BT_ATT_PREPARE_COUNT, BT_ATT_MTU, NULL);
#else
  net_buf_init(&prep_pool, CONFIG_BT_ATT_PREPARE_COUNT, BT_ATT_MTU, NULL);
#endif
#endif
#endif

  bt_gatt_init();
}

u16_t bt_att_get_mtu(struct bt_conn *conn) {
  struct bt_att *att;

  att = att_chan_get(conn);
  if (!att) {
    return 0;
  }

  /* tx and rx MTU shall be symmetric */
  return att->chan.tx.mtu;
}

int bt_att_send(struct bt_conn *conn, struct net_buf *buf, bt_conn_tx_cb_t cb, void *user_data) {
  struct bt_att *att;
  int            err;

  __ASSERT_NO_MSG(conn);
  __ASSERT_NO_MSG(buf);

  att = att_chan_get(conn);
  if (!att) {
    net_buf_unref(buf);
    return -ENOTCONN;
  }

  /* Don't use tx_sem if caller has set it own callback */
  if (!cb) {
    /* Queue buffer to be send later */
    if (k_sem_take(&att->tx_sem, K_NO_WAIT) < 0) {
      k_fifo_put(&att->tx_queue, buf);
      return 0;
    }
  }

  err = att_send(conn, buf, cb, user_data);
  if (err) {
    if (!cb) {
      k_sem_give(&att->tx_sem);
    }
    return err;
  }

  return 0;
}

int bt_att_req_send(struct bt_conn *conn, struct bt_att_req *req) {
  struct bt_att *att;

  BT_DBG("conn %p req %p", conn, req);

  __ASSERT_NO_MSG(conn);
  __ASSERT_NO_MSG(req);

  att = att_chan_get(conn);
  if (!att) {
    net_buf_unref(req->buf);
    req->buf = NULL;
    return -ENOTCONN;
  }

  /* Check if there is a request outstanding */
  if (att->req) {
    /* Queue the request to be send later */
    sys_slist_append(&att->reqs, &req->node);
    return 0;
  }

  return att_send_req(att, req);
}

void bt_att_req_cancel(struct bt_conn *conn, struct bt_att_req *req) {
  struct bt_att *att;

  BT_DBG("req %p", req);

  if (!conn || !req) {
    return;
  }

  att = att_chan_get(conn);
  if (!att) {
    return;
  }

  /* Check if request is outstanding */
  if (att->req == req) {
    att->req = &cancel;
  } else {
    /* Remove request from the list */
    sys_slist_find_and_remove(&att->reqs, &req->node);
  }

  att_req_destroy(req);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/att_internal.h
================================================
/* att_internal.h - Attribute protocol handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#define BT_ATT_DEFAULT_LE_MTU 23

#if BT_L2CAP_RX_MTU < CONFIG_BT_L2CAP_TX_MTU
#define BT_ATT_MTU BT_L2CAP_RX_MTU
#else
#define BT_ATT_MTU CONFIG_BT_L2CAP_TX_MTU
#endif

struct bt_att_hdr {
    u8_t code;
} __packed;

#define BT_ATT_OP_ERROR_RSP 0x01
struct bt_att_error_rsp {
    u8_t request;
    u16_t handle;
    u8_t error;
} __packed;

#define BT_ATT_OP_MTU_REQ 0x02
struct bt_att_exchange_mtu_req {
    u16_t mtu;
} __packed;

#define BT_ATT_OP_MTU_RSP 0x03
struct bt_att_exchange_mtu_rsp {
    u16_t mtu;
} __packed;

/* Find Information Request */
#define BT_ATT_OP_FIND_INFO_REQ 0x04
struct bt_att_find_info_req {
    u16_t start_handle;
    u16_t end_handle;
} __packed;

/* Format field values for BT_ATT_OP_FIND_INFO_RSP */
#define BT_ATT_INFO_16  0x01
#define BT_ATT_INFO_128 0x02

struct bt_att_info_16 {
    u16_t handle;
    u16_t uuid;
} __packed;

struct bt_att_info_128 {
    u16_t handle;
    u8_t uuid[16];
} __packed;

/* Find Information Response */
#define BT_ATT_OP_FIND_INFO_RSP 0x05
struct bt_att_find_info_rsp {
    u8_t format;
    u8_t info[0];
} __packed;

/* Find By Type Value Request */
#define BT_ATT_OP_FIND_TYPE_REQ 0x06
struct bt_att_find_type_req {
    u16_t start_handle;
    u16_t end_handle;
    u16_t type;
    u8_t value[0];
} __packed;

struct bt_att_handle_group {
    u16_t start_handle;
    u16_t end_handle;
} __packed;

/* Find By Type Value Response */
#define BT_ATT_OP_FIND_TYPE_RSP 0x07
struct bt_att_find_type_rsp {
    struct bt_att_handle_group list[0];
} __packed;

/* Read By Type Request */
#define BT_ATT_OP_READ_TYPE_REQ 0x08
struct bt_att_read_type_req {
    u16_t start_handle;
    u16_t end_handle;
    u8_t uuid[0];
} __packed;

struct bt_att_data {
    u16_t handle;
    u8_t value[0];
} __packed;

/* Read By Type Response */
#define BT_ATT_OP_READ_TYPE_RSP 0x09
struct bt_att_read_type_rsp {
    u8_t len;
    struct bt_att_data data[0];
} __packed;

/* Read Request */
#define BT_ATT_OP_READ_REQ 0x0a
struct bt_att_read_req {
    u16_t handle;
} __packed;

/* Read Response */
#define BT_ATT_OP_READ_RSP 0x0b
struct bt_att_read_rsp {
    u8_t value[0];
} __packed;

/* Read Blob Request */
#define BT_ATT_OP_READ_BLOB_REQ 0x0c
struct bt_att_read_blob_req {
    u16_t handle;
    u16_t offset;
} __packed;

/* Read Blob Response */
#define BT_ATT_OP_READ_BLOB_RSP 0x0d
struct bt_att_read_blob_rsp {
    u8_t value[0];
} __packed;

/* Read Multiple Request */
#define BT_ATT_READ_MULT_MIN_LEN_REQ 0x04

#define BT_ATT_OP_READ_MULT_REQ 0x0e
struct bt_att_read_mult_req {
    u16_t handles[0];
} __packed;

/* Read Multiple Respose */
#define BT_ATT_OP_READ_MULT_RSP 0x0f
struct bt_att_read_mult_rsp {
    u8_t value[0];
} __packed;

/* Read by Group Type Request */
#define BT_ATT_OP_READ_GROUP_REQ 0x10
struct bt_att_read_group_req {
    u16_t start_handle;
    u16_t end_handle;
    u8_t uuid[0];
} __packed;

struct bt_att_group_data {
    u16_t start_handle;
    u16_t end_handle;
    u8_t value[0];
} __packed;

/* Read by Group Type Response */
#define BT_ATT_OP_READ_GROUP_RSP 0x11
struct bt_att_read_group_rsp {
    u8_t len;
    struct bt_att_group_data data[0];
} __packed;

/* Write Request */
#define BT_ATT_OP_WRITE_REQ 0x12
struct bt_att_write_req {
    u16_t handle;
    u8_t value[0];
} __packed;

/* Write Response */
#define BT_ATT_OP_WRITE_RSP 0x13

/* Prepare Write Request */
#define BT_ATT_OP_PREPARE_WRITE_REQ 0x16
struct bt_att_prepare_write_req {
    u16_t handle;
    u16_t offset;
    u8_t value[0];
} __packed;

/* Prepare Write Respond */
#define BT_ATT_OP_PREPARE_WRITE_RSP 0x17
struct bt_att_prepare_write_rsp {
    u16_t handle;
    u16_t offset;
    u8_t value[0];
} __packed;

/* Execute Write Request */
#define BT_ATT_FLAG_CANCEL 0x00
#define BT_ATT_FLAG_EXEC   0x01

#define BT_ATT_OP_EXEC_WRITE_REQ 0x18
struct bt_att_exec_write_req {
    u8_t flags;
} __packed;

/* Execute Write Response */
#define BT_ATT_OP_EXEC_WRITE_RSP 0x19

/* Handle Value Notification */
#define BT_ATT_OP_NOTIFY 0x1b
struct bt_att_notify {
    u16_t handle;
    u8_t value[0];
} __packed;

/* Handle Value Indication */
#define BT_ATT_OP_INDICATE 0x1d
struct bt_att_indicate {
    u16_t handle;
    u8_t value[0];
} __packed;

/* Handle Value Confirm */
#define BT_ATT_OP_CONFIRM 0x1e

struct bt_att_signature {
    u8_t value[12];
} __packed;

/* Write Command */
#define BT_ATT_OP_WRITE_CMD 0x52
struct bt_att_write_cmd {
    u16_t handle;
    u8_t value[0];
} __packed;

/* Signed Write Command */
#define BT_ATT_OP_SIGNED_WRITE_CMD 0xd2
struct bt_att_signed_write_cmd {
    u16_t handle;
    u8_t value[0];
} __packed;

void att_pdu_sent(struct bt_conn *conn, void *user_data);

void att_cfm_sent(struct bt_conn *conn, void *user_data);

void att_rsp_sent(struct bt_conn *conn, void *user_data);

void att_req_sent(struct bt_conn *conn, void *user_data);

void bt_att_init(void);
u16_t bt_att_get_mtu(struct bt_conn *conn);

#if defined(CONFIG_BLE_AT_CMD)
void set_mtu_size(u16_t size);
#endif

struct net_buf *bt_att_create_pdu(struct bt_conn *conn, u8_t op,
                                  size_t len);

/* Send ATT PDU over a connection */
int bt_att_send(struct bt_conn *conn, struct net_buf *buf, bt_conn_tx_cb_t cb,
                void *user_data);

/* Send ATT Request over a connection */
int bt_att_req_send(struct bt_conn *conn, struct bt_att_req *req);

/* Cancel ATT request */
void bt_att_req_cancel(struct bt_conn *conn, struct bt_att_req *req);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/avdtp_internal.h
================================================
/*
 * avdtp_internal.h - avdtp handling

 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

/* @brief A2DP ROLE's */
#define A2DP_SRC_ROLE 0x00
#define A2DP_SNK_ROLE 0x01

/* @brief AVDTP Role */
#define BT_AVDTP_INT 0x00
#define BT_AVDTP_ACP 0x01

#define BT_L2CAP_PSM_AVDTP 0x0019

/* AVDTP SIGNAL HEADER - Packet Type*/
#define BT_AVDTP_PACKET_TYPE_SINGLE   0x00
#define BT_AVDTP_PACKET_TYPE_START    0x01
#define BT_AVDTP_PACKET_TYPE_CONTINUE 0x02
#define BT_AVDTP_PACKET_TYPE_END      0x03

/* AVDTP SIGNAL HEADER - MESSAGE TYPE */
#define BT_AVDTP_CMD        0x00
#define BT_AVDTP_GEN_REJECT 0x01
#define BT_AVDTP_ACCEPT     0x02
#define BT_AVDTP_REJECT     0x03

/* @brief AVDTP SIGNAL HEADER - Signal Identifier */
#define BT_AVDTP_DISCOVER             0x01
#define BT_AVDTP_GET_CAPABILITIES     0x02
#define BT_AVDTP_SET_CONFIGURATION    0x03
#define BT_AVDTP_GET_CONFIGURATION    0x04
#define BT_AVDTP_RECONFIGURE          0x05
#define BT_AVDTP_OPEN                 0x06
#define BT_AVDTP_START                0x07
#define BT_AVDTP_CLOSE                0x08
#define BT_AVDTP_SUSPEND              0x09
#define BT_AVDTP_ABORT                0x0a
#define BT_AVDTP_SECURITY_CONTROL     0x0b
#define BT_AVDTP_GET_ALL_CAPABILITIES 0x0c
#define BT_AVDTP_DELAYREPORT          0x0d

/* @brief AVDTP STREAM STATE */
#define BT_AVDTP_STREAM_STATE_IDLE       0x01
#define BT_AVDTP_STREAM_STATE_CONFIGURED 0x02
#define BT_AVDTP_STREAM_STATE_OPEN       0x03
#define BT_AVDTP_STREAM_STATE_STREAMING  0x04
#define BT_AVDTP_STREAM_STATE_CLOSING    0x05

/* @brief AVDTP Media TYPE */
#define BT_AVDTP_SERVICE_CAT_MEDIA_TRANSPORT    0x01
#define BT_AVDTP_SERVICE_CAT_REPORTING          0x02
#define BT_AVDTP_SERVICE_CAT_RECOVERY           0x03
#define BT_AVDTP_SERVICE_CAT_CONTENT_PROTECTION 0x04
#define BT_AVDTP_SERVICE_CAT_HDR_COMPRESSION    0x05
#define BT_AVDTP_SERVICE_CAT_MULTIPLEXING       0x06
#define BT_AVDTP_SERVICE_CAT_MEDIA_CODEC        0x07
#define BT_AVDTP_SERVICE_CAT_DELAYREPORTING     0x08

/* @brief AVDTP Content Protection Capabilities */
#define BT_AVDTP_CONTENT_PROTECTION_MSB        0x00
#define BT_AVDTP_CONTENT_PROTECTION_LSB_DTCP   0x01
#define BT_AVDTP_CONTENT_PROTECTION_LSB_SCMS_T 0x02

/* AVDTP Error Codes */
#define BT_AVDTP_SUCCESS                        0x00
#define BT_AVDTP_ERR_BAD_HDR_FORMAT             0x01
#define BT_AVDTP_ERR_BAD_LENGTH                 0x11
#define BT_AVDTP_ERR_BAD_ACP_SEID               0x12
#define BT_AVDTP_ERR_SEP_IN_USE                 0x13
#define BT_AVDTP_ERR_SEP_NOT_IN_USE             0x14
#define BT_AVDTP_ERR_BAD_SERV_CATEGORY          0x17
#define BT_AVDTP_ERR_BAD_PAYLOAD_FORMAT         0x18
#define BT_AVDTP_ERR_NOT_SUPPORTED_COMMAND      0x19
#define BT_AVDTP_ERR_INVALID_CAPABILITIES       0x1a
#define BT_AVDTP_ERR_BAD_RECOVERY_TYPE          0x22
#define BT_AVDTP_ERR_BAD_MEDIA_TRANSPORT_FORMAT 0x23
#define BT_AVDTP_ERR_BAD_RECOVERY_FORMAT        0x25
#define BT_AVDTP_ERR_BAD_ROHC_FORMAT            0x26
#define BT_AVDTP_ERR_BAD_CP_FORMAT              0x27
#define BT_AVDTP_ERR_BAD_MULTIPLEXING_FORMAT    0x28
#define BT_AVDTP_ERR_UNSUPPORTED_CONFIGURAION   0x29
#define BT_AVDTP_ERR_BAD_STATE                  0x31

#define BT_AVDTP_MAX_MTU CONFIG_BT_L2CAP_RX_MTU

#define BT_AVDTP_MIN_SEID 0x01
#define BT_AVDTP_MAX_SEID 0x3E

struct bt_avdtp;
struct bt_avdtp_req;

typedef int (*bt_avdtp_func_t)(struct bt_avdtp *session,
                               struct bt_avdtp_req *req);

struct bt_avdtp_req {
    uint8_t sig;
    uint8_t tid;
    bt_avdtp_func_t func;
    struct k_delayed_work timeout_work;
};

struct bt_avdtp_single_sig_hdr {
    uint8_t hdr;
    uint8_t signal_id;
} __packed;

#define BT_AVDTP_SIG_HDR_LEN sizeof(struct bt_avdtp_single_sig_hdr)

struct bt_avdtp_ind_cb {
    /*
	 * discovery_ind;
	 * get_capabilities_ind;
	 * set_configuration_ind;
	 * open_ind;
	 * start_ind;
	 * suspend_ind;
	 * close_ind;
	 */
};

struct bt_avdtp_cap {
    uint8_t cat;
    uint8_t len;
    uint8_t data[0];
};

struct bt_avdtp_sep {
    uint8_t seid;
    uint8_t len;
    struct bt_avdtp_cap caps[0];
};

struct bt_avdtp_discover_params {
    struct bt_avdtp_req req;
    uint8_t status;
    struct bt_avdtp_sep *caps;
};

/** @brief Global AVDTP session structure. */
struct bt_avdtp {
    struct bt_l2cap_br_chan br_chan;
    struct bt_avdtp_stream *streams; /* List of AV streams */
    struct bt_avdtp_req *req;
};

struct bt_avdtp_event_cb {
    struct bt_avdtp_ind_cb *ind;
    int (*accept)(struct bt_conn *conn, struct bt_avdtp **session);
};

/* Initialize AVDTP layer*/
int bt_avdtp_init(void);

/* Application register with AVDTP layer */
int bt_avdtp_register(struct bt_avdtp_event_cb *cb);

/* AVDTP connect */
int bt_avdtp_connect(struct bt_conn *conn, struct bt_avdtp *session);

/* AVDTP disconnect */
int bt_avdtp_disconnect(struct bt_avdtp *session);

/* AVDTP SEP register function */
int bt_avdtp_register_sep(uint8_t media_type, uint8_t role,
                          struct bt_avdtp_seid_lsep *sep);

/* AVDTP Discover Request */
int bt_avdtp_discover(struct bt_avdtp *session,
                      struct bt_avdtp_discover_params *param);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/conn.c
================================================
/* conn.c - Bluetooth connection handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

#include 

#include 
#include 
#include 

#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_CONN)
#define LOG_MODULE_NAME bt_conn
#include "log.h"

#include "hci_core.h"

#include "conn_internal.h"
#include "keys.h"
#include "l2cap_internal.h"
#include "smp.h"

#include "att_internal.h"
#include "gatt_internal.h"
#if defined(BFLB_BLE)
#include "ble_config.h"

extern struct k_sem g_poll_sem;
#endif
struct tx_meta {
  struct bt_conn_tx *tx;
};

#define tx_data(buf) ((struct tx_meta *)net_buf_user_data(buf))

#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
NET_BUF_POOL_DEFINE(acl_tx_pool, CONFIG_BT_L2CAP_TX_BUF_COUNT, BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU), sizeof(struct tx_meta), NULL);
#else
struct net_buf_pool acl_tx_pool;
#endif

#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0

#if defined(BT_CTLR_TX_BUFFER_SIZE)
#define FRAG_SIZE BT_L2CAP_BUF_SIZE(BT_CTLR_TX_BUFFER_SIZE - 4)
#else
#define FRAG_SIZE BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU)
#endif

#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
/* Dedicated pool for fragment buffers in case queued up TX buffers don't
 * fit the controllers buffer size. We can't use the acl_tx_pool for the
 * fragmentation, since it's possible that pool is empty and all buffers
 * are queued up in the TX queue. In such a situation, trying to allocate
 * another buffer from the acl_tx_pool would result in a deadlock.
 */
NET_BUF_POOL_FIXED_DEFINE(frag_pool, CONFIG_BT_L2CAP_TX_FRAG_COUNT, FRAG_SIZE, NULL);
#else
struct net_buf_pool frag_pool;
#endif
#endif /* CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0 */

/* How long until we cancel HCI_LE_Create_Connection */
#define CONN_TIMEOUT K_SECONDS(CONFIG_BT_CREATE_CONN_TIMEOUT)

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
const struct bt_conn_auth_cb *bt_auth;
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

static struct bt_conn     conns[CONFIG_BT_MAX_CONN];
static struct bt_conn_cb *callback_list;

static struct bt_conn_tx conn_tx[CONFIG_BT_CONN_TX_MAX];
K_FIFO_DEFINE(free_tx);

#if defined(CONFIG_BT_BREDR)
static struct bt_conn sco_conns[CONFIG_BT_MAX_SCO_CONN];

enum pairing_method {
  LEGACY,          /* Legacy (pre-SSP) pairing */
  JUST_WORKS,      /* JustWorks pairing */
  PASSKEY_INPUT,   /* Passkey Entry input */
  PASSKEY_DISPLAY, /* Passkey Entry display */
  PASSKEY_CONFIRM, /* Passkey confirm */
};

/* based on table 5.7, Core Spec 4.2, Vol.3 Part C, 5.2.2.6 */
static const u8_t ssp_method[4 /* remote */][4 /* local */] = {
    {     JUST_WORKS,      JUST_WORKS, PASSKEY_INPUT, JUST_WORKS},
    {     JUST_WORKS, PASSKEY_CONFIRM, PASSKEY_INPUT, JUST_WORKS},
    {PASSKEY_DISPLAY, PASSKEY_DISPLAY, PASSKEY_INPUT, JUST_WORKS},
    {     JUST_WORKS,      JUST_WORKS,    JUST_WORKS, JUST_WORKS},
};
#endif /* CONFIG_BT_BREDR */

struct k_sem *bt_conn_get_pkts(struct bt_conn *conn) {
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR || !bt_dev.le.mtu) {
    return &bt_dev.br.pkts;
  }
#endif /* CONFIG_BT_BREDR */

  return &bt_dev.le.pkts;
}

static inline const char *state2str(bt_conn_state_t state) {
  switch (state) {
  case BT_CONN_DISCONNECTED:
    return "disconnected";
  case BT_CONN_CONNECT_SCAN:
    return "connect-scan";
  case BT_CONN_CONNECT_DIR_ADV:
    return "connect-dir-adv";
  case BT_CONN_CONNECT:
    return "connect";
  case BT_CONN_CONNECTED:
    return "connected";
  case BT_CONN_DISCONNECT:
    return "disconnect";
  default:
    return "(unknown)";
  }
}

static void notify_connected(struct bt_conn *conn) {
  struct bt_conn_cb *cb;

#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR && conn->err) {
    if (atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_ISCAN);
    }
    if (atomic_test_bit(bt_dev.flags, BT_DEV_PSCAN)) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_PSCAN);
    }
  }
#endif

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->connected) {
      cb->connected(conn, conn->err);
    }
  }

  if (conn->type == BT_CONN_TYPE_LE && !conn->err) {
    bt_gatt_connected(conn);
  }
}

void notify_disconnected(struct bt_conn *conn) {
  struct bt_conn_cb *cb;

#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    if (atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_ISCAN);
    }
    if (atomic_test_bit(bt_dev.flags, BT_DEV_PSCAN)) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_PSCAN);
    }
  }
#endif

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->disconnected) {
      cb->disconnected(conn, conn->err);
    }
  }
}

void notify_le_param_updated(struct bt_conn *conn) {
  struct bt_conn_cb *cb;

  /* If new connection parameters meet requirement of pending
   * parameters don't send slave conn param request anymore on timeout
   */
  if (atomic_test_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET) && conn->le.interval >= conn->le.interval_min && conn->le.interval <= conn->le.interval_max &&
      conn->le.latency == conn->le.pending_latency && conn->le.timeout == conn->le.pending_timeout) {
    atomic_clear_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET);
  }

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->le_param_updated) {
      cb->le_param_updated(conn, conn->le.interval, conn->le.latency, conn->le.timeout);
    }
  }
}

void notify_le_phy_updated(struct bt_conn *conn, u8_t tx_phy, u8_t rx_phy) {
  struct bt_conn_cb *cb;

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->le_phy_updated) {
      cb->le_phy_updated(conn, tx_phy, rx_phy);
    }
  }
}

bool le_param_req(struct bt_conn *conn, struct bt_le_conn_param *param) {
  struct bt_conn_cb *cb;

  if (!bt_le_conn_params_valid(param)) {
    return false;
  }

  for (cb = callback_list; cb; cb = cb->_next) {
    if (!cb->le_param_req) {
      continue;
    }

    if (!cb->le_param_req(conn, param)) {
      return false;
    }

    /* The callback may modify the parameters so we need to
     * double-check that it returned valid parameters.
     */
    if (!bt_le_conn_params_valid(param)) {
      return false;
    }
  }

  /* Default to accepting if there's no app callback */
  return true;
}

static int send_conn_le_param_update(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  BT_DBG("conn %p features 0x%02x params (%d-%d %d %d)", conn, conn->le.features[0], param->interval_min, param->interval_max, param->latency, param->timeout);

  /* Use LE connection parameter request if both local and remote support
   * it; or if local role is master then use LE connection update.
   */
  if ((BT_FEAT_LE_CONN_PARAM_REQ_PROC(bt_dev.le.features) && BT_FEAT_LE_CONN_PARAM_REQ_PROC(conn->le.features) && !atomic_test_bit(conn->flags, BT_CONN_SLAVE_PARAM_L2CAP)) ||
      (conn->role == BT_HCI_ROLE_MASTER)) {
    int rc;

    rc = bt_conn_le_conn_update(conn, param);

    /* store those in case of fallback to L2CAP */
    if (rc == 0) {
      conn->le.pending_latency = param->latency;
      conn->le.pending_timeout = param->timeout;
    }

    return rc;
  }

  /* If remote master does not support LL Connection Parameters Request
   * Procedure
   */
  return bt_l2cap_update_conn_param(conn, param);
}

static void tx_free(struct bt_conn_tx *tx) {
  tx->cb            = NULL;
  tx->user_data     = NULL;
  tx->pending_no_cb = 0U;
  k_fifo_put(&free_tx, tx);
}

static void tx_notify(struct bt_conn *conn) {
  BT_DBG("conn %p", conn);

  while (1) {
    struct bt_conn_tx *tx;
    unsigned int       key;
    bt_conn_tx_cb_t    cb;
    void              *user_data;

    key = irq_lock();
    if (sys_slist_is_empty(&conn->tx_complete)) {
      irq_unlock(key);
      break;
    }

    tx = (void *)sys_slist_get_not_empty(&conn->tx_complete);
    irq_unlock(key);

    BT_DBG("tx %p cb %p user_data %p", tx, tx->cb, tx->user_data);

    /* Copy over the params */
    cb        = tx->cb;
    user_data = tx->user_data;

    /* Free up TX notify since there may be user waiting */
    tx_free(tx);

    /* Run the callback, at this point it should be safe to
     * allocate new buffers since the TX should have been
     * unblocked by tx_free.
     */
    cb(conn, user_data);
  }
}

static void tx_complete_work(struct k_work *work) {
  struct bt_conn *conn = CONTAINER_OF(work, struct bt_conn, tx_complete_work);

  BT_DBG("conn %p", conn);

  tx_notify(conn);
}

static void conn_update_timeout(struct k_work *work) {
  struct bt_conn                *conn = CONTAINER_OF(work, struct bt_conn, update_work);
  const struct bt_le_conn_param *param;

  BT_DBG("conn %p", conn);

  if (conn->state == BT_CONN_DISCONNECTED) {
    bt_l2cap_disconnected(conn);
#if !defined(BFLB_BLE)
    notify_disconnected(conn);
#endif

    /* Release the reference we took for the very first
     * state transition.
     */
    bt_conn_unref(conn);
    return;
  }

  if (conn->type != BT_CONN_TYPE_LE) {
    return;
  }

  if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->role == BT_CONN_ROLE_MASTER) {
    /* we don't call bt_conn_disconnect as it would also clear
     * auto connect flag if it was set, instead just cancel
     * connection directly
     */
    bt_hci_cmd_send_sync(BT_HCI_OP_LE_CREATE_CONN_CANCEL, NULL, NULL);
    return;
  }

#if defined(CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS)
  /* if application set own params use those, otherwise use defaults */
  if (atomic_test_and_clear_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET)) {
    param = BT_LE_CONN_PARAM(conn->le.interval_min, conn->le.interval_max, conn->le.pending_latency, conn->le.pending_timeout);

    send_conn_le_param_update(conn, param);
  } else {
    param = BT_LE_CONN_PARAM(CONFIG_BT_PERIPHERAL_PREF_MIN_INT, CONFIG_BT_PERIPHERAL_PREF_MAX_INT, CONFIG_BT_PERIPHERAL_PREF_SLAVE_LATENCY, CONFIG_BT_PERIPHERAL_PREF_TIMEOUT);

    send_conn_le_param_update(conn, param);
  }
#else
  /* update only if application set own params */
  if (atomic_test_and_clear_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET)) {
    param = BT_LE_CONN_PARAM(conn->le.interval_min, conn->le.interval_max, conn->le.latency, conn->le.timeout);

    send_conn_le_param_update(conn, param);
  }
#endif

  atomic_set_bit(conn->flags, BT_CONN_SLAVE_PARAM_UPDATE);
}

#if defined(CONFIG_BT_AUDIO)
struct bt_conn *iso_conn_new(struct bt_conn *conns, size_t size) {
  struct bt_conn *conn = NULL;
  int             i;

  for (i = 0; i < size; i++) {
    if (atomic_cas(&conns[i].ref, 0, 1)) {
      conn = &conns[i];
      break;
    }
  }

  if (!conn) {
    return NULL;
  }

  (void)memset(conn, 0, offsetof(struct bt_conn, ref));

  return conn;
}
#endif

static struct bt_conn *conn_new(void) {
  struct bt_conn *conn = NULL;
  int             i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      conn = &conns[i];
      break;
    }
  }

  if (!conn) {
    return NULL;
  }

  (void)memset(conn, 0, sizeof(*conn));
  k_delayed_work_init(&conn->update_work, conn_update_timeout);

  k_work_init(&conn->tx_complete_work, tx_complete_work);

  atomic_set(&conn->ref, 1);

  return conn;
}

#if defined(BFLB_BLE)
bool le_check_valid_conn(void) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (atomic_get(&conns[i].ref)) {
      return true;
    }
  }

  return false;
}

#if defined(BFLB_HOST_ASSISTANT)
void bt_notify_disconnected(void) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (atomic_get(&conns[i].ref)) {
      conns[i].err = BT_HCI_ERR_UNSPECIFIED;
      notify_disconnected(&conns[i]);
    }
  }
}
#endif // #if defined(BFLB_HOST_ASSISTANT)
#endif

#if defined(CONFIG_BT_BREDR)
void bt_sco_cleanup(struct bt_conn *sco_conn) {
  bt_conn_unref(sco_conn->sco.acl);
  sco_conn->sco.acl = NULL;
  bt_conn_unref(sco_conn);
}

static struct bt_conn *sco_conn_new(void) {
  struct bt_conn *sco_conn = NULL;
  int             i;

  for (i = 0; i < ARRAY_SIZE(sco_conns); i++) {
    if (!atomic_get(&sco_conns[i].ref)) {
      sco_conn = &sco_conns[i];
      break;
    }
  }

  if (!sco_conn) {
    return NULL;
  }

  (void)memset(sco_conn, 0, sizeof(*sco_conn));

  atomic_set(&sco_conn->ref, 1);

  return sco_conn;
}

struct bt_conn *bt_conn_create_br(const bt_addr_t *peer, const struct bt_br_conn_param *param) {
  struct bt_hci_cp_connect *cp;
  struct bt_conn           *conn;
  struct net_buf           *buf;

  conn = bt_conn_lookup_addr_br(peer);
  if (conn) {
    switch (conn->state) {
    case BT_CONN_CONNECT:
    case BT_CONN_CONNECTED:
      return conn;
    default:
      bt_conn_unref(conn);
      return NULL;
    }
  }

  conn = bt_conn_add_br(peer);
  if (!conn) {
    return NULL;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT, sizeof(*cp));
  if (!buf) {
    bt_conn_unref(conn);
    return NULL;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  (void)memset(cp, 0, sizeof(*cp));

  memcpy(&cp->bdaddr, peer, sizeof(cp->bdaddr));
  cp->packet_type       = sys_cpu_to_le16(0xcc18); /* DM1 DH1 DM3 DH5 DM5 DH5 */
  cp->pscan_rep_mode    = 0x02;                    /* R2 */
  cp->allow_role_switch = param->allow_role_switch ? 0x01 : 0x00;
  cp->clock_offset      = 0x0000; /* TODO used cached clock offset */

  if (bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT, buf, NULL) < 0) {
    bt_conn_unref(conn);
    return NULL;
  }

  bt_conn_set_state(conn, BT_CONN_CONNECT);
  conn->role = BT_CONN_ROLE_MASTER;

  bt_conn_unref(conn);
  return conn;
}

struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer) {
  struct bt_hci_cp_setup_sync_conn *cp;
  struct bt_conn                   *sco_conn;
  struct net_buf                   *buf;
  int                               link_type;

  sco_conn = bt_conn_lookup_addr_sco(peer);
  if (sco_conn) {
    switch (sco_conn->state) {
    case BT_CONN_CONNECT:
    case BT_CONN_CONNECTED:
      return sco_conn;
    default:
      bt_conn_unref(sco_conn);
      return NULL;
    }
  }

  if (BT_FEAT_LMP_ESCO_CAPABLE(bt_dev.features)) {
    link_type = BT_HCI_ESCO;
  } else {
    link_type = BT_HCI_SCO;
  }

  sco_conn = bt_conn_add_sco(peer, link_type);
  if (!sco_conn) {
    return NULL;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_SETUP_SYNC_CONN, sizeof(*cp));
  if (!buf) {
    bt_sco_cleanup(sco_conn);
    return NULL;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  (void)memset(cp, 0, sizeof(*cp));

  BT_ERR("handle : %x", sco_conn->sco.acl->handle);

  cp->handle         = sco_conn->sco.acl->handle;
  cp->pkt_type       = sco_conn->sco.pkt_type;
  cp->tx_bandwidth   = 0x00001f40;
  cp->rx_bandwidth   = 0x00001f40;
  cp->max_latency    = 0x0007;
  cp->retrans_effort = 0x01;
  cp->content_format = BT_VOICE_CVSD_16BIT;

  if (bt_hci_cmd_send_sync(BT_HCI_OP_SETUP_SYNC_CONN, buf, NULL) < 0) {
    bt_sco_cleanup(sco_conn);
    return NULL;
  }

  bt_conn_set_state(sco_conn, BT_CONN_CONNECT);

  return sco_conn;
}

struct bt_conn *bt_conn_lookup_addr_sco(const bt_addr_t *peer) {
  int i;

  for (i = 0; i < ARRAY_SIZE(sco_conns); i++) {
    if (!atomic_get(&sco_conns[i].ref)) {
      continue;
    }

    if (sco_conns[i].type != BT_CONN_TYPE_SCO) {
      continue;
    }

    if (!bt_addr_cmp(peer, &sco_conns[i].sco.acl->br.dst)) {
      return bt_conn_ref(&sco_conns[i]);
    }
  }

  return NULL;
}

struct bt_conn *bt_conn_lookup_addr_br(const bt_addr_t *peer) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }

    if (conns[i].type != BT_CONN_TYPE_BR) {
      continue;
    }

    if (!bt_addr_cmp(peer, &conns[i].br.dst)) {
      return bt_conn_ref(&conns[i]);
    }
  }

  return NULL;
}

struct bt_conn *bt_conn_add_sco(const bt_addr_t *peer, int link_type) {
  struct bt_conn *sco_conn = sco_conn_new();

  if (!sco_conn) {
    return NULL;
  }

  sco_conn->sco.acl = bt_conn_lookup_addr_br(peer);
  sco_conn->type    = BT_CONN_TYPE_SCO;

  if (link_type == BT_HCI_SCO) {
    if (BT_FEAT_LMP_ESCO_CAPABLE(bt_dev.features)) {
      sco_conn->sco.pkt_type = (bt_dev.br.esco_pkt_type & ESCO_PKT_MASK);
    } else {
      sco_conn->sco.pkt_type = (bt_dev.br.esco_pkt_type & SCO_PKT_MASK);
    }
  } else if (link_type == BT_HCI_ESCO) {
    sco_conn->sco.pkt_type = (bt_dev.br.esco_pkt_type & ~EDR_ESCO_PKT_MASK);
  }

  return sco_conn;
}

struct bt_conn *bt_conn_add_br(const bt_addr_t *peer) {
  struct bt_conn *conn = conn_new();

  if (!conn) {
    return NULL;
  }

  bt_addr_copy(&conn->br.dst, peer);
  conn->type = BT_CONN_TYPE_BR;

  return conn;
}

static int pin_code_neg_reply(const bt_addr_t *bdaddr) {
  struct bt_hci_cp_pin_code_neg_reply *cp;
  struct net_buf                      *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_PIN_CODE_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);

  return bt_hci_cmd_send_sync(BT_HCI_OP_PIN_CODE_NEG_REPLY, buf, NULL);
}

static int pin_code_reply(struct bt_conn *conn, const char *pin, u8_t len) {
  struct bt_hci_cp_pin_code_reply *cp;
  struct net_buf                  *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_PIN_CODE_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  bt_addr_copy(&cp->bdaddr, &conn->br.dst);
  cp->pin_len = len;
  strncpy((char *)cp->pin_code, pin, sizeof(cp->pin_code));

  return bt_hci_cmd_send_sync(BT_HCI_OP_PIN_CODE_REPLY, buf, NULL);
}

int bt_conn_auth_pincode_entry(struct bt_conn *conn, const char *pin) {
  size_t len;

  if (!bt_auth) {
    return -EINVAL;
  }

  if (conn->type != BT_CONN_TYPE_BR) {
    return -EINVAL;
  }

  len = strlen(pin);
  if (len > 16) {
    return -EINVAL;
  }

  if (conn->required_sec_level == BT_SECURITY_L3 && len < 16) {
    BT_WARN("PIN code for %s is not 16 bytes wide", bt_addr_str(&conn->br.dst));
    return -EPERM;
  }

  /* Allow user send entered PIN to remote, then reset user state. */
  if (!atomic_test_and_clear_bit(conn->flags, BT_CONN_USER)) {
    return -EPERM;
  }

  if (len == 16) {
    atomic_set_bit(conn->flags, BT_CONN_BR_LEGACY_SECURE);
  }

  return pin_code_reply(conn, pin, len);
}

void bt_conn_pin_code_req(struct bt_conn *conn) {
  if (bt_auth && bt_auth->pincode_entry) {
    bool secure = false;

    if (conn->required_sec_level == BT_SECURITY_L3) {
      secure = true;
    }

    atomic_set_bit(conn->flags, BT_CONN_USER);
    atomic_set_bit(conn->flags, BT_CONN_BR_PAIRING);
    bt_auth->pincode_entry(conn, secure);
  } else {
    pin_code_neg_reply(&conn->br.dst);
  }
}

u8_t bt_conn_get_io_capa(void) {
  if (!bt_auth) {
    return BT_IO_NO_INPUT_OUTPUT;
  }

  if (bt_auth->passkey_confirm && bt_auth->passkey_display) {
    return BT_IO_DISPLAY_YESNO;
  }

  if (bt_auth->passkey_entry) {
    return BT_IO_KEYBOARD_ONLY;
  }

  if (bt_auth->passkey_display) {
    return BT_IO_DISPLAY_ONLY;
  }

  return BT_IO_NO_INPUT_OUTPUT;
}

static u8_t ssp_pair_method(const struct bt_conn *conn) { return ssp_method[conn->br.remote_io_capa][bt_conn_get_io_capa()]; }

u8_t bt_conn_ssp_get_auth(const struct bt_conn *conn) {
  /* Validate no bond auth request, and if valid use it. */
  if ((conn->br.remote_auth == BT_HCI_NO_BONDING) || ((conn->br.remote_auth == BT_HCI_NO_BONDING_MITM) && (ssp_pair_method(conn) > JUST_WORKS))) {
    return conn->br.remote_auth;
  }

  /* Local & remote have enough IO capabilities to get MITM protection. */
  if (ssp_pair_method(conn) > JUST_WORKS) {
    return conn->br.remote_auth | BT_MITM;
  }

  /* No MITM protection possible so ignore remote MITM requirement. */
  return (conn->br.remote_auth & ~BT_MITM);
}

static int ssp_confirm_reply(struct bt_conn *conn) {
  struct bt_hci_cp_user_confirm_reply *cp;
  struct net_buf                      *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_USER_CONFIRM_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, &conn->br.dst);

  return bt_hci_cmd_send_sync(BT_HCI_OP_USER_CONFIRM_REPLY, buf, NULL);
}

static int ssp_confirm_neg_reply(struct bt_conn *conn) {
  struct bt_hci_cp_user_confirm_reply *cp;
  struct net_buf                      *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_USER_CONFIRM_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, &conn->br.dst);

  return bt_hci_cmd_send_sync(BT_HCI_OP_USER_CONFIRM_NEG_REPLY, buf, NULL);
}

void bt_conn_ssp_auth_complete(struct bt_conn *conn, u8_t status) {
  if (!status) {
    bool bond = !atomic_test_bit(conn->flags, BT_CONN_BR_NOBOND);

    if (bt_auth && bt_auth->pairing_complete) {
      bt_auth->pairing_complete(conn, bond);
    }
  } else {
    if (bt_auth && bt_auth->pairing_failed) {
      bt_auth->pairing_failed(conn, status);
    }
  }
}

void bt_conn_ssp_auth(struct bt_conn *conn, u32_t passkey) {
  conn->br.pairing_method = ssp_pair_method(conn);

  /*
   * If local required security is HIGH then MITM is mandatory.
   * MITM protection is no achievable when SSP 'justworks' is applied.
   */
  if (conn->required_sec_level > BT_SECURITY_L2 && conn->br.pairing_method == JUST_WORKS) {
    BT_DBG("MITM protection infeasible for required security");
    ssp_confirm_neg_reply(conn);
    return;
  }

  switch (conn->br.pairing_method) {
  case PASSKEY_CONFIRM:
    atomic_set_bit(conn->flags, BT_CONN_USER);
    bt_auth->passkey_confirm(conn, passkey);
    break;
  case PASSKEY_DISPLAY:
    atomic_set_bit(conn->flags, BT_CONN_USER);
    bt_auth->passkey_display(conn, passkey);
    break;
  case PASSKEY_INPUT:
    atomic_set_bit(conn->flags, BT_CONN_USER);
    bt_auth->passkey_entry(conn);
    break;
  case JUST_WORKS:
    /*
     * When local host works as pairing acceptor and 'justworks'
     * model is applied then notify user about such pairing request.
     * [BT Core 4.2 table 5.7, Vol 3, Part C, 5.2.2.6]
     */
    if (bt_auth && bt_auth->pairing_confirm && !atomic_test_bit(conn->flags, BT_CONN_BR_PAIRING_INITIATOR)) {
      atomic_set_bit(conn->flags, BT_CONN_USER);
      bt_auth->pairing_confirm(conn);
      break;
    }
    ssp_confirm_reply(conn);
    break;
  default:
    break;
  }
}

static int ssp_passkey_reply(struct bt_conn *conn, unsigned int passkey) {
  struct bt_hci_cp_user_passkey_reply *cp;
  struct net_buf                      *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_USER_PASSKEY_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, &conn->br.dst);
  cp->passkey = sys_cpu_to_le32(passkey);

  return bt_hci_cmd_send_sync(BT_HCI_OP_USER_PASSKEY_REPLY, buf, NULL);
}

static int ssp_passkey_neg_reply(struct bt_conn *conn) {
  struct bt_hci_cp_user_passkey_neg_reply *cp;
  struct net_buf                          *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_USER_PASSKEY_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, &conn->br.dst);

  return bt_hci_cmd_send_sync(BT_HCI_OP_USER_PASSKEY_NEG_REPLY, buf, NULL);
}

static int bt_hci_connect_br_cancel(struct bt_conn *conn) {
  struct bt_hci_cp_connect_cancel *cp;
  struct bt_hci_rp_connect_cancel *rp;
  struct net_buf                  *buf, *rsp;
  int                              err;

  buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT_CANCEL, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  memcpy(&cp->bdaddr, &conn->br.dst, sizeof(cp->bdaddr));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT_CANCEL, buf, &rsp);
  if (err) {
    return err;
  }

  rp = (void *)rsp->data;

  err = rp->status ? -EIO : 0;

  net_buf_unref(rsp);

  return err;
}

static int conn_auth(struct bt_conn *conn) {
  struct bt_hci_cp_auth_requested *auth;
  struct net_buf                  *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_AUTH_REQUESTED, sizeof(*auth));
  if (!buf) {
    return -ENOBUFS;
  }

  auth         = net_buf_add(buf, sizeof(*auth));
  auth->handle = sys_cpu_to_le16(conn->handle);

  atomic_set_bit(conn->flags, BT_CONN_BR_PAIRING_INITIATOR);

  return bt_hci_cmd_send_sync(BT_HCI_OP_AUTH_REQUESTED, buf, NULL);
}
#endif /* CONFIG_BT_BREDR */

#if defined(CONFIG_BT_SMP)
void bt_conn_identity_resolved(struct bt_conn *conn) {
  const bt_addr_le_t *rpa;
  struct bt_conn_cb  *cb;

  if (conn->role == BT_HCI_ROLE_MASTER) {
    rpa = &conn->le.resp_addr;
  } else {
    rpa = &conn->le.init_addr;
  }

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->identity_resolved) {
      cb->identity_resolved(conn, rpa, &conn->le.dst);
    }
  }
}

int bt_conn_le_start_encryption(struct bt_conn *conn, u8_t rand[8], u8_t ediv[2], const u8_t *ltk, size_t len) {
  struct bt_hci_cp_le_start_encryption *cp;
  struct net_buf                       *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_START_ENCRYPTION, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(conn->handle);
  memcpy(&cp->rand, rand, sizeof(cp->rand));
  memcpy(&cp->ediv, ediv, sizeof(cp->ediv));

  memcpy(cp->ltk, ltk, len);
  if (len < sizeof(cp->ltk)) {
    (void)memset(cp->ltk + len, 0, sizeof(cp->ltk) - len);
  }

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_START_ENCRYPTION, buf, NULL);
}
#endif /* CONFIG_BT_SMP */

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
u8_t bt_conn_enc_key_size(struct bt_conn *conn) {
  // GATT/SR/GAR/BV-04-C
  //  if the connection instance is valid
  if (!conn) {
    return 0;
  }

  if (!conn->encrypt) {
    return 0;
  }

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    struct bt_hci_cp_read_encryption_key_size *cp;
    struct bt_hci_rp_read_encryption_key_size *rp;
    struct net_buf                            *buf;
    struct net_buf                            *rsp;
    u8_t                                       key_size;

    buf = bt_hci_cmd_create(BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE, sizeof(*cp));
    if (!buf) {
      return 0;
    }

    cp         = net_buf_add(buf, sizeof(*cp));
    cp->handle = sys_cpu_to_le16(conn->handle);

    if (bt_hci_cmd_send_sync(BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE, buf, &rsp)) {
      return 0;
    }

    rp = (void *)rsp->data;

    key_size = rp->status ? 0 : rp->key_size;

    net_buf_unref(rsp);

    return key_size;
  }

  if (IS_ENABLED(CONFIG_BT_SMP)) {
    return conn->le.keys ? conn->le.keys->enc_size : 0;
  }

  return 0;
}

void bt_conn_security_changed(struct bt_conn *conn, enum bt_security_err err) {
  struct bt_conn_cb *cb;

  for (cb = callback_list; cb; cb = cb->_next) {
    if (cb->security_changed) {
      cb->security_changed(conn, conn->sec_level, err);
    }
  }
#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
  if (!err && conn->sec_level >= BT_SECURITY_L2) {
    bt_keys_update_usage(conn->id, bt_conn_get_dst(conn));
  }
#endif
}

static int start_security(struct bt_conn *conn) {
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    if (atomic_test_bit(conn->flags, BT_CONN_BR_PAIRING)) {
      return -EBUSY;
    }

    if (conn->required_sec_level > BT_SECURITY_L3) {
      return -ENOTSUP;
    }

    if (bt_conn_get_io_capa() == BT_IO_NO_INPUT_OUTPUT && conn->required_sec_level > BT_SECURITY_L2) {
      return -EINVAL;
    }

    return conn_auth(conn);
  }
#endif /* CONFIG_BT_BREDR */

  if (IS_ENABLED(CONFIG_BT_SMP)) {
    return bt_smp_start_security(conn);
  }

  return -EINVAL;
}

int bt_conn_set_security(struct bt_conn *conn, bt_security_t sec) {
  int err;

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  if (IS_ENABLED(CONFIG_BT_SMP_SC_ONLY) && sec < BT_SECURITY_L4) {
    return -EOPNOTSUPP;
  }

  /* nothing to do */
  if (conn->sec_level >= sec || conn->required_sec_level >= sec) {
    return 0;
  }

  atomic_set_bit_to(conn->flags, BT_CONN_FORCE_PAIR, sec & BT_SECURITY_FORCE_PAIR);
  conn->required_sec_level = sec & ~BT_SECURITY_FORCE_PAIR;

  err = start_security(conn);

  /* reset required security level in case of error */
  if (err) {
    conn->required_sec_level = conn->sec_level;
  }

  return err;
}

bt_security_t bt_conn_get_security(struct bt_conn *conn) { return conn->sec_level; }
#else
bt_security_t bt_conn_get_security(struct bt_conn *conn) { return BT_SECURITY_L1; }
#endif /* CONFIG_BT_SMP */

void bt_conn_cb_register(struct bt_conn_cb *cb) {
  cb->_next     = callback_list;
  callback_list = cb;
}

void bt_conn_reset_rx_state(struct bt_conn *conn) {
  if (!conn->rx_len) {
    return;
  }

  net_buf_unref(conn->rx);
  conn->rx     = NULL;
  conn->rx_len = 0U;
}

void bt_conn_recv(struct bt_conn *conn, struct net_buf *buf, u8_t flags) {
  struct bt_l2cap_hdr *hdr;
  u16_t                len;

  /* Make sure we notify any pending TX callbacks before processing
   * new data for this connection.
   */
  tx_notify(conn);

  BT_DBG("handle %u len %u flags %02x", conn->handle, buf->len, flags);

  /* Check packet boundary flags */
  switch (flags) {
  case BT_ACL_START:
    hdr = (void *)buf->data;
    len = sys_le16_to_cpu(hdr->len);

    BT_DBG("First, len %u final %u", buf->len, len);

    if (conn->rx_len) {
      BT_ERR("Unexpected first L2CAP frame");
      bt_conn_reset_rx_state(conn);
    }

    conn->rx_len = (sizeof(*hdr) + len) - buf->len;
    BT_DBG("rx_len %u", conn->rx_len);
    if (conn->rx_len) {
      conn->rx = buf;
      return;
    }

    break;
  case BT_ACL_CONT:
    if (!conn->rx_len) {
      BT_ERR("Unexpected L2CAP continuation");
      bt_conn_reset_rx_state(conn);
      net_buf_unref(buf);
      return;
    }

    if (buf->len > conn->rx_len) {
      BT_ERR("L2CAP data overflow");
      bt_conn_reset_rx_state(conn);
      net_buf_unref(buf);
      return;
    }

    BT_DBG("Cont, len %u rx_len %u", buf->len, conn->rx_len);

    if (buf->len > net_buf_tailroom(conn->rx)) {
      BT_ERR("Not enough buffer space for L2CAP data");
      bt_conn_reset_rx_state(conn);
      net_buf_unref(buf);
      return;
    }

    net_buf_add_mem(conn->rx, buf->data, buf->len);
    conn->rx_len -= buf->len;
    net_buf_unref(buf);

    if (conn->rx_len) {
      return;
    }

    buf          = conn->rx;
    conn->rx     = NULL;
    conn->rx_len = 0U;

    break;
  default:
    BT_ERR("Unexpected ACL flags (0x%02x)", flags);
    bt_conn_reset_rx_state(conn);
    net_buf_unref(buf);
    return;
  }

  hdr = (void *)buf->data;
  len = sys_le16_to_cpu(hdr->len);

  if (sizeof(*hdr) + len != buf->len) {
    BT_ERR("ACL len mismatch (%u != %u)", len, buf->len);
    net_buf_unref(buf);
    return;
  }

  BT_DBG("Successfully parsed %u byte L2CAP packet", buf->len);

  bt_l2cap_recv(conn, buf);
}

static struct bt_conn_tx *conn_tx_alloc(void) {
  /* The TX context always get freed in the system workqueue,
   * so if we're in the same workqueue but there are no immediate
   * contexts available, there's no chance we'll get one by waiting.
   */
#if !defined(BFLB_BLE)
  if (k_current_get() == &k_sys_work_q.thread) {
    return k_fifo_get(&free_tx, K_NO_WAIT);
  }
#endif
  if (IS_ENABLED(CONFIG_BT_DEBUG_CONN)) {
    struct bt_conn_tx *tx = k_fifo_get(&free_tx, K_NO_WAIT);

    if (tx) {
      return tx;
    }

    BT_WARN("Unable to get an immediate free conn_tx");
  }

  return k_fifo_get(&free_tx, K_FOREVER);
}

int bt_conn_send_cb(struct bt_conn *conn, struct net_buf *buf, bt_conn_tx_cb_t cb, void *user_data) {
  struct bt_conn_tx *tx;

  BT_DBG("conn handle %u buf len %u cb %p user_data %p", conn->handle, buf->len, cb, user_data);

  if (conn->state != BT_CONN_CONNECTED) {
    BT_ERR("not connected!");
    net_buf_unref(buf);
    return -ENOTCONN;
  }

  if (cb) {
    tx = conn_tx_alloc();
    if (!tx) {
      BT_ERR("Unable to allocate TX context");
      net_buf_unref(buf);
      return -ENOBUFS;
    }

    /* Verify that we're still connected after blocking */
    if (conn->state != BT_CONN_CONNECTED) {
      BT_WARN("Disconnected while allocating context");
      net_buf_unref(buf);
      tx_free(tx);
      return -ENOTCONN;
    }

    tx->cb            = cb;
    tx->user_data     = user_data;
    tx->pending_no_cb = 0U;

    tx_data(buf)->tx = tx;
  } else {
    tx_data(buf)->tx = NULL;
  }

#if (BFLB_BT_CO_THREAD)
  if (k_is_current_thread(bt_get_co_thread()))
    bt_conn_process_tx(conn, buf);
  else
    net_buf_put(&conn->tx_queue, buf);
#if defined(BFLB_BLE)
  k_sem_give(&g_poll_sem);
#endif
#else // BFLB_BT_CO_THREAD

  net_buf_put(&conn->tx_queue, buf);
#if defined(BFLB_BLE)
  k_sem_give(&g_poll_sem);
#endif
#endif // BFLB_BT_CO_THREAD
  return 0;
}

static bool send_frag(struct bt_conn *conn, struct net_buf *buf, u8_t flags, bool always_consume) {
  struct bt_conn_tx     *tx = tx_data(buf)->tx;
  struct bt_hci_acl_hdr *hdr;
  u32_t                 *pending_no_cb;
  unsigned int           key;
  int                    err;

  BT_DBG("conn %p buf %p len %u flags 0x%02x", conn, buf, buf->len, flags);

  /* Wait until the controller can accept ACL packets */
  k_sem_take(bt_conn_get_pkts(conn), K_FOREVER);

  /* Check for disconnection while waiting for pkts_sem */
  if (conn->state != BT_CONN_CONNECTED) {
    goto fail;
  }

  hdr         = net_buf_push(buf, sizeof(*hdr));
  hdr->handle = sys_cpu_to_le16(bt_acl_handle_pack(conn->handle, flags));
  hdr->len    = sys_cpu_to_le16(buf->len - sizeof(*hdr));

  /* Add to pending, it must be done before bt_buf_set_type */
  key = irq_lock();
  if (tx) {
    sys_slist_append(&conn->tx_pending, &tx->node);
  } else {
    struct bt_conn_tx *tail_tx;

    tail_tx = (void *)sys_slist_peek_tail(&conn->tx_pending);
    if (tail_tx) {
      pending_no_cb = &tail_tx->pending_no_cb;
    } else {
      pending_no_cb = &conn->pending_no_cb;
    }

    (*pending_no_cb)++;
  }
  irq_unlock(key);

  bt_buf_set_type(buf, BT_BUF_ACL_OUT);

  err = bt_send(buf);
  if (err) {
    BT_ERR("Unable to send to driver (err %d)", err);
    key = irq_lock();
    /* Roll back the pending TX info */
    if (tx) {
      sys_slist_find_and_remove(&conn->tx_pending, &tx->node);
    } else {
      __ASSERT_NO_MSG(*pending_no_cb > 0);
      (*pending_no_cb)--;
    }
    irq_unlock(key);
    goto fail;
  }

  return true;

fail:
  k_sem_give(bt_conn_get_pkts(conn));
  if (tx) {
    tx_free(tx);
  }

  if (always_consume) {
    net_buf_unref(buf);
  }
  return false;
}

static inline u16_t conn_mtu(struct bt_conn *conn) {
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR || !bt_dev.le.mtu) {
    return bt_dev.br.mtu;
  }
#endif /* CONFIG_BT_BREDR */

  return bt_dev.le.mtu;
}

static struct net_buf *create_frag(struct bt_conn *conn, struct net_buf *buf) {
  struct net_buf *frag;
  u16_t           frag_len;

#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0
  frag = bt_conn_create_pdu(&frag_pool, 0);
#else
  frag = bt_conn_create_pdu(NULL, 0);
#endif

  if (conn->state != BT_CONN_CONNECTED) {
    net_buf_unref(frag);
    return NULL;
  }

  /* Fragments never have a TX completion callback */
  tx_data(frag)->tx = NULL;

  frag_len = MIN(conn_mtu(conn), net_buf_tailroom(frag));

  net_buf_add_mem(frag, buf->data, frag_len);
  net_buf_pull(buf, frag_len);

  return frag;
}

static bool send_buf(struct bt_conn *conn, struct net_buf *buf) {
  struct net_buf *frag;

  BT_DBG("conn %p buf %p len %u", conn, buf, buf->len);

  /* Send directly if the packet fits the ACL MTU */
  if (buf->len <= conn_mtu(conn)) {
    return send_frag(conn, buf, BT_ACL_START_NO_FLUSH, false);
  }

  /* Create & enqueue first fragment */
  frag = create_frag(conn, buf);
  if (!frag) {
    return false;
  }

  if (!send_frag(conn, frag, BT_ACL_START_NO_FLUSH, true)) {
    return false;
  }

  /*
   * Send the fragments. For the last one simply use the original
   * buffer (which works since we've used net_buf_pull on it.
   */
  while (buf->len > conn_mtu(conn)) {
    frag = create_frag(conn, buf);
    if (!frag) {
      return false;
    }

    if (!send_frag(conn, frag, BT_ACL_CONT, true)) {
      return false;
    }
  }

  return send_frag(conn, buf, BT_ACL_CONT, false);
}

static struct k_poll_signal conn_change = K_POLL_SIGNAL_INITIALIZER(conn_change);

static void conn_cleanup(struct bt_conn *conn) {
  struct net_buf *buf;

  /* Give back any allocated buffers */
  while ((buf = net_buf_get(&conn->tx_queue, K_NO_WAIT))) {
    if (tx_data(buf)->tx) {
      tx_free(tx_data(buf)->tx);
    }

    net_buf_unref(buf);
  }

  __ASSERT(sys_slist_is_empty(&conn->tx_pending), "Pending TX packets");
  __ASSERT_NO_MSG(conn->pending_no_cb == 0);

  bt_conn_reset_rx_state(conn);

  k_delayed_work_submit(&conn->update_work, K_NO_WAIT);

#ifdef BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
  k_queue_free(&conn->tx_queue._queue);
  // k_queue_free(&conn->tx_notify._queue);
  conn->tx_queue._queue.hdl = NULL;
  // conn->tx_notify._queue.hdl = NULL;
  if (conn->update_work.timer.timer.hdl)
    k_delayed_work_del_timer(&conn->update_work);
#endif
}

int bt_conn_prepare_events(struct k_poll_event events[]) {
  int i, ev_count = 0;

  BT_DBG("");

  conn_change.signaled = 0U;
  k_poll_event_init(&events[ev_count++], K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &conn_change);

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    struct bt_conn *conn = &conns[i];

    if (!atomic_get(&conn->ref)) {
      continue;
    }

    if (conn->state == BT_CONN_DISCONNECTED && atomic_test_and_clear_bit(conn->flags, BT_CONN_CLEANUP)) {
      conn_cleanup(conn);
      continue;
    }

    if (conn->state != BT_CONN_CONNECTED) {
      continue;
    }

    BT_DBG("Adding conn %p to poll list", conn);

    k_poll_event_init(&events[ev_count], K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &conn->tx_queue);
    events[ev_count++].tag = BT_EVENT_CONN_TX_QUEUE;
  }

  return ev_count;
}

#if (BFLB_BT_CO_THREAD)
void bt_conn_process_tx(struct bt_conn *conn, struct net_buf *tx_buf)
#else
void bt_conn_process_tx(struct bt_conn *conn)
#endif
{
  struct net_buf *buf;

  BT_DBG("conn %p", conn);

  if (conn->state == BT_CONN_DISCONNECTED && atomic_test_and_clear_bit(conn->flags, BT_CONN_CLEANUP)) {
    BT_DBG("handle %u disconnected - cleaning up", conn->handle);
    conn_cleanup(conn);
    return;
  }
#if (BFLB_BT_CO_THREAD)
  if (tx_buf)
    buf = tx_buf;
  else
    buf = net_buf_get(&conn->tx_queue, K_NO_WAIT);
#else
  /* Get next ACL packet for connection */
  buf = net_buf_get(&conn->tx_queue, K_NO_WAIT);
#endif
  BT_ASSERT(buf);
  if (!send_buf(conn, buf)) {
    net_buf_unref(buf);
  }
}

struct bt_conn *bt_conn_add_le(u8_t id, const bt_addr_le_t *peer) {
  struct bt_conn *conn = conn_new();

  if (!conn) {
    return NULL;
  }

  conn->id = id;
  bt_addr_le_copy(&conn->le.dst, peer);
#if defined(CONFIG_BT_SMP)
  conn->sec_level          = BT_SECURITY_L1;
  conn->required_sec_level = BT_SECURITY_L1;
#endif /* CONFIG_BT_SMP */
  conn->type            = BT_CONN_TYPE_LE;
  conn->le.interval_min = BT_GAP_INIT_CONN_INT_MIN;
  conn->le.interval_max = BT_GAP_INIT_CONN_INT_MAX;

  return conn;
}

static void process_unack_tx(struct bt_conn *conn) {
  /* Return any unacknowledged packets */
  while (1) {
    struct bt_conn_tx *tx;
    sys_snode_t       *node;
    unsigned int       key;

    key = irq_lock();

    if (conn->pending_no_cb) {
      conn->pending_no_cb--;
      irq_unlock(key);
      k_sem_give(bt_conn_get_pkts(conn));
      continue;
    }

    node = sys_slist_get(&conn->tx_pending);
    irq_unlock(key);

    if (!node) {
      break;
    }

    tx = CONTAINER_OF(node, struct bt_conn_tx, node);

    key                 = irq_lock();
    conn->pending_no_cb = tx->pending_no_cb;
    tx->pending_no_cb   = 0U;
    irq_unlock(key);

    tx_free(tx);

    k_sem_give(bt_conn_get_pkts(conn));
  }
}

void bt_conn_set_state(struct bt_conn *conn, bt_conn_state_t state) {
  bt_conn_state_t old_state;

  BT_DBG("%s -> %s", state2str(conn->state), state2str(state));

  if (conn->state == state) {
    BT_WARN("no transition");
    return;
  }

  old_state   = conn->state;
  conn->state = state;

  /* Actions needed for exiting the old state */
  switch (old_state) {
  case BT_CONN_DISCONNECTED:
    /* Take a reference for the first state transition after
     * bt_conn_add_le() and keep it until reaching DISCONNECTED
     * again.
     */
    bt_conn_ref(conn);
    break;
  case BT_CONN_CONNECT:
    if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->type == BT_CONN_TYPE_LE) {
      k_delayed_work_cancel(&conn->update_work);
    }
    break;
  default:
    break;
  }

  /* Actions needed for entering the new state */
  switch (conn->state) {
  case BT_CONN_CONNECTED:
    if (conn->type == BT_CONN_TYPE_SCO) {
      /* TODO: Notify sco connected */
      break;
    }
    k_fifo_init(&conn->tx_queue, 20);
    k_poll_signal_raise(&conn_change, 0);

    sys_slist_init(&conn->channels);

    bt_l2cap_connected(conn);
    notify_connected(conn);
    break;
  case BT_CONN_DISCONNECTED:
    if (conn->type == BT_CONN_TYPE_SCO) {
      /* TODO: Notify sco disconnected */
      bt_conn_unref(conn);
      break;
    }
    /* Notify disconnection and queue a dummy buffer to wake
     * up and stop the tx thread for states where it was
     * running.
     */
    if (old_state == BT_CONN_CONNECTED || old_state == BT_CONN_DISCONNECT) {
      process_unack_tx(conn);
      tx_notify(conn);

      /* Cancel Connection Update if it is pending */
      if (conn->type == BT_CONN_TYPE_LE) {
        k_delayed_work_cancel(&conn->update_work);
      }

      atomic_set_bit(conn->flags, BT_CONN_CLEANUP);
      k_poll_signal_raise(&conn_change, 0);
      /* The last ref will be dropped during cleanup */
    } else if (old_state == BT_CONN_CONNECT) {
      /* conn->err will be set in this case */
      notify_connected(conn);
      bt_conn_unref(conn);
    } else if (old_state == BT_CONN_CONNECT_SCAN) {
      /* this indicate LE Create Connection failed */
      if (conn->err) {
        notify_connected(conn);
      }

      bt_conn_unref(conn);
    } else if (old_state == BT_CONN_CONNECT_DIR_ADV) {
      /* this indicate Directed advertising stopped */
      if (conn->err) {
        notify_connected(conn);
      }

      bt_conn_unref(conn);
    }

    break;
  case BT_CONN_CONNECT_SCAN:
    break;
  case BT_CONN_CONNECT_DIR_ADV:
    break;
  case BT_CONN_CONNECT:
    if (conn->type == BT_CONN_TYPE_SCO) {
      break;
    }
    /*
     * Timer is needed only for LE. For other link types controller
     * will handle connection timeout.
     */
    if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->type == BT_CONN_TYPE_LE) {
      k_delayed_work_submit(&conn->update_work, CONN_TIMEOUT);
    }

    break;
  case BT_CONN_DISCONNECT:
    break;
  default:
    BT_WARN("no valid (%u) state was set", state);

    break;
  }
}

struct bt_conn *bt_conn_lookup_handle(u16_t handle) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }

    /* We only care about connections with a valid handle */
    if (conns[i].state != BT_CONN_CONNECTED && conns[i].state != BT_CONN_DISCONNECT) {
      continue;
    }

    if (conns[i].handle == handle) {
      return bt_conn_ref(&conns[i]);
    }
  }

#if defined(CONFIG_BT_BREDR)
  for (i = 0; i < ARRAY_SIZE(sco_conns); i++) {
    if (!atomic_get(&sco_conns[i].ref)) {
      continue;
    }

    /* We only care about connections with a valid handle */
    if (sco_conns[i].state != BT_CONN_CONNECTED && sco_conns[i].state != BT_CONN_DISCONNECT) {
      continue;
    }

    if (sco_conns[i].handle == handle) {
      return bt_conn_ref(&sco_conns[i]);
    }
  }
#endif

  return NULL;
}

int bt_conn_addr_le_cmp(const struct bt_conn *conn, const bt_addr_le_t *peer) {
  /* Check against conn dst address as it may be the identity address */
  if (!bt_addr_le_cmp(peer, &conn->le.dst)) {
    return 0;
  }

  /* Check against initial connection address */
  if (conn->role == BT_HCI_ROLE_MASTER) {
    return bt_addr_le_cmp(peer, &conn->le.resp_addr);
  }

  return bt_addr_le_cmp(peer, &conn->le.init_addr);
}

struct bt_conn *bt_conn_lookup_addr_le(u8_t id, const bt_addr_le_t *peer) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }

    if (conns[i].type != BT_CONN_TYPE_LE) {
      continue;
    }

    if (conns[i].id == id && !bt_conn_addr_le_cmp(&conns[i], peer)) {
      return bt_conn_ref(&conns[i]);
    }
  }

  return NULL;
}

struct bt_conn *bt_conn_lookup_state_le(const bt_addr_le_t *peer, const bt_conn_state_t state) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }

    if (conns[i].type != BT_CONN_TYPE_LE) {
      continue;
    }

    if (peer && bt_conn_addr_le_cmp(&conns[i], peer)) {
      continue;
    }

    if (conns[i].state == state) {
      return bt_conn_ref(&conns[i]);
    }
  }

  return NULL;
}

void bt_conn_foreach(int type, void (*func)(struct bt_conn *conn, void *data), void *data) {
  int i;

  for (i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }

    if (!(conns[i].type & type)) {
      continue;
    }

    func(&conns[i], data);
  }
#if defined(CONFIG_BT_BREDR)
  if (type & BT_CONN_TYPE_SCO) {
    for (i = 0; i < ARRAY_SIZE(sco_conns); i++) {
      if (!atomic_get(&sco_conns[i].ref)) {
        continue;
      }

      func(&sco_conns[i], data);
    }
  }
#endif /* defined(CONFIG_BT_BREDR) */
}

static void disconnect_all(struct bt_conn *conn, void *data) {
  u8_t *id = (u8_t *)data;

  if (conn->id == *id && conn->state == BT_CONN_CONNECTED) {
    bt_conn_disconnect(conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
  }
}

void bt_conn_disconnect_all(u8_t id) { bt_conn_foreach(BT_CONN_TYPE_ALL, disconnect_all, &id); }

struct bt_conn *bt_conn_ref(struct bt_conn *conn) {
  atomic_inc(&conn->ref);

  BT_DBG("handle %u ref %u", conn->handle, atomic_get(&conn->ref));

  return conn;
}

void bt_conn_unref(struct bt_conn *conn) {
  atomic_dec(&conn->ref);

  BT_DBG("handle %u ref %u", conn->handle, atomic_get(&conn->ref));
}

const bt_addr_le_t *bt_conn_get_dst(const struct bt_conn *conn) { return &conn->le.dst; }

int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info) {
  info->type = conn->type;
  info->role = conn->role;
  info->id   = conn->id;

  switch (conn->type) {
  case BT_CONN_TYPE_LE:
    info->le.dst = &conn->le.dst;
    info->le.src = &bt_dev.id_addr[conn->id];
    if (conn->role == BT_HCI_ROLE_MASTER) {
      info->le.local  = &conn->le.init_addr;
      info->le.remote = &conn->le.resp_addr;
    } else {
      info->le.local  = &conn->le.resp_addr;
      info->le.remote = &conn->le.init_addr;
    }
    info->le.interval = conn->le.interval;
    info->le.latency  = conn->le.latency;
    info->le.timeout  = conn->le.timeout;
    return 0;
#if defined(CONFIG_BT_BREDR)
  case BT_CONN_TYPE_BR:
    info->br.dst = &conn->br.dst;
    return 0;
#endif
  }

  return -EINVAL;
}

int bt_conn_get_remote_dev_info(struct bt_conn_info *info) {
  int link_num = 0;

  for (int i = 0; i < ARRAY_SIZE(conns); i++) {
    if (!atomic_get(&conns[i].ref)) {
      continue;
    }
    bt_conn_get_info(&conns[i], &info[link_num]);
    link_num++;
  }

  return link_num;
}

static int bt_hci_disconnect(struct bt_conn *conn, u8_t reason) {
  struct net_buf              *buf;
  struct bt_hci_cp_disconnect *disconn;
  int                          err;

  buf = bt_hci_cmd_create(BT_HCI_OP_DISCONNECT, sizeof(*disconn));
  if (!buf) {
    return -ENOBUFS;
  }

  disconn         = net_buf_add(buf, sizeof(*disconn));
  disconn->handle = sys_cpu_to_le16(conn->handle);
  disconn->reason = reason;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_DISCONNECT, buf, NULL);
  if (err) {
    return err;
  }

  bt_conn_set_state(conn, BT_CONN_DISCONNECT);

  return 0;
}

#if defined(CONFIG_BT_STACK_PTS)
int pts_bt_conn_le_param_update(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  BT_DBG("conn %p features 0x%02x params (%d-%d %d %d)", conn, conn->le.features[0], param->interval_min, param->interval_max, param->latency, param->timeout);

  /* Check if there's a need to update conn params */
  if (conn->le.interval >= param->interval_min && conn->le.interval <= param->interval_max && conn->le.latency == param->latency && conn->le.timeout == param->timeout) {
    return -EALREADY;
  }

  /* Cancel any pending update */
  k_delayed_work_cancel(&conn->update_work);

  return bt_l2cap_update_conn_param(conn, param);
}
#endif
int bt_conn_le_param_update(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  BT_DBG("conn %p features 0x%02x params (%d-%d %d %d)", conn, conn->le.features[0], param->interval_min, param->interval_max, param->latency, param->timeout);

  /* Check if there's a need to update conn params */
  if (conn->le.interval >= param->interval_min && conn->le.interval <= param->interval_max && conn->le.latency == param->latency && conn->le.timeout == param->timeout) {
    atomic_clear_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET);
    return -EALREADY;
  }

  if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->role == BT_CONN_ROLE_MASTER) {
    return send_conn_le_param_update(conn, param);
  }

  if (IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
    /* if slave conn param update timer expired just send request */
    if (atomic_test_bit(conn->flags, BT_CONN_SLAVE_PARAM_UPDATE)) {
      return send_conn_le_param_update(conn, param);
    }

    /* store new conn params to be used by update timer */
    conn->le.interval_min    = param->interval_min;
    conn->le.interval_max    = param->interval_max;
    conn->le.pending_latency = param->latency;
    conn->le.pending_timeout = param->timeout;
    atomic_set_bit(conn->flags, BT_CONN_SLAVE_PARAM_SET);
  }

  return 0;
}

int bt_conn_disconnect(struct bt_conn *conn, u8_t reason) {
  /* Disconnection is initiated by us, so auto connection shall
   * be disabled. Otherwise the passive scan would be enabled
   * and we could send LE Create Connection as soon as the remote
   * starts advertising.
   */
#if !defined(CONFIG_BT_WHITELIST)
  if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->type == BT_CONN_TYPE_LE) {
    bt_le_set_auto_conn(&conn->le.dst, NULL);
  }
#endif /* !defined(CONFIG_BT_WHITELIST) */

  switch (conn->state) {
  case BT_CONN_CONNECT_SCAN:
    conn->err = reason;
    bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
    if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
      bt_le_scan_update(false);
    }
    return 0;
  case BT_CONN_CONNECT_DIR_ADV:
    conn->err = reason;
    bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
    if (IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
      /* User should unref connection object when receiving
       * error in connection callback.
       */
      return bt_le_adv_stop();
    }
    return 0;
  case BT_CONN_CONNECT:
#if defined(CONFIG_BT_BREDR)
    if (conn->type == BT_CONN_TYPE_BR) {
      return bt_hci_connect_br_cancel(conn);
    }
#endif /* CONFIG_BT_BREDR */

    if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
      k_delayed_work_cancel(&conn->update_work);
      return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CREATE_CONN_CANCEL, NULL, NULL);
    }

    return 0;
  case BT_CONN_CONNECTED:
    return bt_hci_disconnect(conn, reason);
  case BT_CONN_DISCONNECT:
    return 0;
  case BT_CONN_DISCONNECTED:
  default:
    return -ENOTCONN;
  }
}

#if defined(CONFIG_BT_CENTRAL)
static void bt_conn_set_param_le(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  conn->le.interval_min = param->interval_min;
  conn->le.interval_max = param->interval_max;
  conn->le.latency      = param->latency;
  conn->le.timeout      = param->timeout;

#if defined(CONFIG_BT_STACK_PTS)
  conn->le.own_adder_type = param->own_address_type;
#endif
}

#if defined(CONFIG_BT_WHITELIST)
int bt_conn_create_auto_le(const struct bt_le_conn_param *param) {
  struct bt_conn *conn;
  int             err;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EINVAL;
  }

  if (!bt_le_conn_params_valid(param)) {
    return -EINVAL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return -EINVAL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_AUTO_CONN)) {
    return -EALREADY;
  }

  if (!bt_dev.le.wl_entries) {
    return -EINVAL;
  }

  /* Don't start initiator if we have general discovery procedure. */
  conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT_SCAN);
  if (conn) {
    bt_conn_unref(conn);
    return -EINVAL;
  }

  /* Don't start initiator if we have direct discovery procedure. */
  conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT);
  if (conn) {
    bt_conn_unref(conn);
    return -EINVAL;
  }

  err = bt_le_auto_conn(param);
  if (err) {
    BT_ERR("Failed to start whitelist scan");
    return err;
  }

  return 0;
}

int bt_conn_create_auto_stop(void) {
  int err;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EINVAL;
  }

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_AUTO_CONN)) {
    return -EINVAL;
  }

  err = bt_le_auto_conn_cancel();
  if (err) {
    BT_ERR("Failed to stop initiator");
    return err;
  }

  return 0;
}
#endif /* defined(CONFIG_BT_WHITELIST) */

struct bt_conn *bt_conn_create_le(const bt_addr_le_t *peer, const struct bt_le_conn_param *param) {
  struct bt_conn *conn;
  bt_addr_le_t    dst;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return NULL;
  }

  if (!bt_le_conn_params_valid(param)) {
    return NULL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return NULL;
  }

  if (IS_ENABLED(CONFIG_BT_WHITELIST) && atomic_test_bit(bt_dev.flags, BT_DEV_AUTO_CONN)) {
    return NULL;
  }

  conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, peer);
  if (conn) {
    switch (conn->state) {
    case BT_CONN_CONNECT_SCAN:
      bt_conn_set_param_le(conn, param);
      return conn;
    case BT_CONN_CONNECT:
    case BT_CONN_CONNECTED:
      return conn;
    case BT_CONN_DISCONNECTED:
      BT_WARN("Found valid but disconnected conn object");
      goto start_scan;
    default:
      bt_conn_unref(conn);
      return NULL;
    }
  }

  if (peer->type == BT_ADDR_LE_PUBLIC_ID || peer->type == BT_ADDR_LE_RANDOM_ID) {
    bt_addr_le_copy(&dst, peer);
    dst.type -= BT_ADDR_LE_PUBLIC_ID;
  } else {
    bt_addr_le_copy(&dst, bt_lookup_id_addr(BT_ID_DEFAULT, peer));
  }

  /* Only default identity supported for now */
  conn = bt_conn_add_le(BT_ID_DEFAULT, &dst);
  if (!conn) {
    return NULL;
  }

start_scan:
  bt_conn_set_param_le(conn, param);

  bt_conn_set_state(conn, BT_CONN_CONNECT_SCAN);

  bt_le_scan_update(true);

  return conn;
}

#if !defined(CONFIG_BT_WHITELIST)
int bt_le_set_auto_conn(const bt_addr_le_t *addr, const struct bt_le_conn_param *param) {
  struct bt_conn *conn;

  if (param && !bt_le_conn_params_valid(param)) {
    return -EINVAL;
  }

  /* Only default identity is supported */
  conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, addr);
  if (!conn) {
    conn = bt_conn_add_le(BT_ID_DEFAULT, addr);
    if (!conn) {
      return -ENOMEM;
    }
  }

  if (param) {
    bt_conn_set_param_le(conn, param);

    if (!atomic_test_and_set_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
      bt_conn_ref(conn);
    }
  } else {
    if (atomic_test_and_clear_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
      bt_conn_unref(conn);
      if (conn->state == BT_CONN_CONNECT_SCAN) {
        bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
      }
    }
  }

  if (conn->state == BT_CONN_DISCONNECTED && atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    if (param) {
      bt_conn_set_state(conn, BT_CONN_CONNECT_SCAN);
    }
    bt_le_scan_update(false);
  }

  bt_conn_unref(conn);

  return 0;
}
#endif /* !defined(CONFIG_BT_WHITELIST) */
#endif /* CONFIG_BT_CENTRAL */

#if defined(CONFIG_BT_PERIPHERAL)
struct bt_conn *bt_conn_create_slave_le(const bt_addr_le_t *peer, const struct bt_le_adv_param *param) {
  int                    err;
  struct bt_conn        *conn;
  struct bt_le_adv_param param_int;

  memcpy(¶m_int, param, sizeof(param_int));
  param_int.options |= (BT_LE_ADV_OPT_CONNECTABLE | BT_LE_ADV_OPT_ONE_TIME);

  conn = bt_conn_lookup_addr_le(param->id, peer);
  if (conn) {
    switch (conn->state) {
    case BT_CONN_CONNECT_DIR_ADV:
      /* Handle the case when advertising is stopped with
       * bt_le_adv_stop function
       */
      err = bt_le_adv_start_internal(¶m_int, NULL, 0, NULL, 0, peer);
      if (err && (err != -EALREADY)) {
        BT_WARN("Directed advertising could not be"
                " started: %d",
                err);
        bt_conn_unref(conn);
        return NULL;
      }
      __attribute__((fallthrough));
    case BT_CONN_CONNECT:
    case BT_CONN_CONNECTED:
      return conn;
    case BT_CONN_DISCONNECTED:
      BT_WARN("Found valid but disconnected conn object");
      goto start_adv;
    default:
      bt_conn_unref(conn);
      return NULL;
    }
  }

  conn = bt_conn_add_le(param->id, peer);
  if (!conn) {
    return NULL;
  }

start_adv:
  bt_conn_set_state(conn, BT_CONN_CONNECT_DIR_ADV);

  err = bt_le_adv_start_internal(¶m_int, NULL, 0, NULL, 0, peer);
  if (err) {
    BT_WARN("Directed advertising could not be started: %d", err);

    bt_conn_unref(conn);
    return NULL;
  }

  return conn;
}
#endif /* CONFIG_BT_PERIPHERAL */

int bt_conn_le_conn_update(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  struct hci_cp_le_conn_update *conn_update;
  struct net_buf               *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CONN_UPDATE, sizeof(*conn_update));
  if (!buf) {
    return -ENOBUFS;
  }

  conn_update = net_buf_add(buf, sizeof(*conn_update));
  (void)memset(conn_update, 0, sizeof(*conn_update));
  conn_update->handle              = sys_cpu_to_le16(conn->handle);
  conn_update->conn_interval_min   = sys_cpu_to_le16(param->interval_min);
  conn_update->conn_interval_max   = sys_cpu_to_le16(param->interval_max);
  conn_update->conn_latency        = sys_cpu_to_le16(param->latency);
  conn_update->supervision_timeout = sys_cpu_to_le16(param->timeout);

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CONN_UPDATE, buf, NULL);
}

struct net_buf *bt_conn_create_pdu_timeout(struct net_buf_pool *pool, size_t reserve, s32_t timeout) {
  struct net_buf *buf;

  /*
   * PDU must not be allocated from ISR as we block with 'K_FOREVER'
   * during the allocation
   */
  __ASSERT_NO_MSG(!k_is_in_isr());

  if (!pool) {
    pool = &acl_tx_pool;
  }

  if (IS_ENABLED(CONFIG_BT_DEBUG_CONN)) {
    buf = net_buf_alloc(pool, K_NO_WAIT);
    if (!buf) {
      BT_WARN("Unable to allocate buffer with K_NO_WAIT");
      buf = net_buf_alloc(pool, timeout);
    }
  } else {
    buf = net_buf_alloc(pool, timeout);
  }

  if (!buf) {
    BT_WARN("Unable to allocate buffer: timeout %d", timeout);
    return NULL;
  }

  reserve += sizeof(struct bt_hci_acl_hdr) + BT_BUF_RESERVE;
  net_buf_reserve(buf, reserve);

  return buf;
}

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb) {
  if (!cb) {
    bt_auth = NULL;
    return 0;
  }

  if (bt_auth) {
    return -EALREADY;
  }

  /* The cancel callback must always be provided if the app provides
   * interactive callbacks.
   */
  if (!cb->cancel && (cb->passkey_display || cb->passkey_entry || cb->passkey_confirm ||
#if defined(CONFIG_BT_BREDR)
                      cb->pincode_entry ||
#endif
                      cb->pairing_confirm)) {
    return -EINVAL;
  }

  bt_auth = cb;
  return 0;
}

int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey) {
  if (!bt_auth) {
    return -EINVAL;
  }

  if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
    bt_smp_auth_passkey_entry(conn, passkey);
    return 0;
  }

#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    /* User entered passkey, reset user state. */
    if (!atomic_test_and_clear_bit(conn->flags, BT_CONN_USER)) {
      return -EPERM;
    }

    if (conn->br.pairing_method == PASSKEY_INPUT) {
      return ssp_passkey_reply(conn, passkey);
    }
  }
#endif /* CONFIG_BT_BREDR */

  return -EINVAL;
}

int bt_conn_auth_passkey_confirm(struct bt_conn *conn) {
  if (!bt_auth) {
    return -EINVAL;
  }

  if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
    return bt_smp_auth_passkey_confirm(conn);
  }

#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    /* Allow user confirm passkey value, then reset user state. */
    if (!atomic_test_and_clear_bit(conn->flags, BT_CONN_USER)) {
      return -EPERM;
    }

    return ssp_confirm_reply(conn);
  }
#endif /* CONFIG_BT_BREDR */

  return -EINVAL;
}

int bt_conn_auth_cancel(struct bt_conn *conn) {
  if (!bt_auth) {
    return -EINVAL;
  }

  if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
    return bt_smp_auth_cancel(conn);
  }

#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    /* Allow user cancel authentication, then reset user state. */
    if (!atomic_test_and_clear_bit(conn->flags, BT_CONN_USER)) {
      return -EPERM;
    }

    switch (conn->br.pairing_method) {
    case JUST_WORKS:
    case PASSKEY_CONFIRM:
      return ssp_confirm_neg_reply(conn);
    case PASSKEY_INPUT:
      return ssp_passkey_neg_reply(conn);
    case PASSKEY_DISPLAY:
      return bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
    case LEGACY:
      return pin_code_neg_reply(&conn->br.dst);
    default:
      break;
    }
  }
#endif /* CONFIG_BT_BREDR */

  return -EINVAL;
}

int bt_conn_auth_pairing_confirm(struct bt_conn *conn) {
  if (!bt_auth) {
    return -EINVAL;
  }

  switch (conn->type) {
#if defined(CONFIG_BT_SMP)
  case BT_CONN_TYPE_LE:
    return bt_smp_auth_pairing_confirm(conn);
#endif /* CONFIG_BT_SMP */
#if defined(CONFIG_BT_BREDR)
  case BT_CONN_TYPE_BR:
    return ssp_confirm_reply(conn);
#endif /* CONFIG_BT_BREDR */
  default:
    return -EINVAL;
  }
}
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

u8_t bt_conn_index(struct bt_conn *conn) {
  u8_t index = conn - conns;

  __ASSERT(index < CONFIG_BT_MAX_CONN, "Invalid bt_conn pointer");
  return index;
}

struct bt_conn *bt_conn_lookup_id(u8_t id) {
  struct bt_conn *conn;

  if (id >= ARRAY_SIZE(conns)) {
    return NULL;
  }

  conn = &conns[id];

  if (!atomic_get(&conn->ref)) {
    return NULL;
  }

  return bt_conn_ref(conn);
}

int bt_conn_init(void) {
#if defined(CONFIG_BT_SMP)
  int err;
#endif
  int i;

#if defined(BFLB_BLE)
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(ACL_TX, &acl_tx_pool, CONFIG_BT_L2CAP_TX_BUF_COUNT, BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU), NULL);
#else
  net_buf_init(&acl_tx_pool, CONFIG_BT_L2CAP_TX_BUF_COUNT, BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU), NULL);
#endif
#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(FRAG, &frag_pool, CONFIG_BT_L2CAP_TX_FRAG_COUNT, FRAG_SIZE, NULL);
#else
  net_buf_init(&frag_pool, CONFIG_BT_L2CAP_TX_FRAG_COUNT, FRAG_SIZE, NULL);
#endif
#endif
#else // BFLB_DYNAMIC_ALLOC_MEM
  struct net_buf_pool num_complete_pool;
  struct net_buf_pool acl_tx_pool;
#if CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0
  struct net_buf_pool frag_pool;
#endif
#endif // BFLB_DYNAMIC_ALLOC_MEM
  k_fifo_init(&free_tx, 20);
#endif
  for (i = 0; i < ARRAY_SIZE(conn_tx); i++) {
    k_fifo_put(&free_tx, &conn_tx[i]);
  }

  bt_att_init();

#if defined(CONFIG_BT_SMP)
  err = bt_smp_init();
  if (err) {
    return err;
  }
#endif

  bt_l2cap_init();

  /* Initialize background scan */
  if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
    for (i = 0; i < ARRAY_SIZE(conns); i++) {
      struct bt_conn *conn = &conns[i];

      if (!atomic_get(&conn->ref)) {
        continue;
      }

      if (atomic_test_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
        /* Only the default identity is supported */
        conn->id = BT_ID_DEFAULT;
        bt_conn_set_state(conn, BT_CONN_CONNECT_SCAN);
      }
    }
  }

  return 0;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/conn_internal.h
================================================
/** @file
 *  @brief Internal APIs for Bluetooth connection handling.
 */

/*
 * Copyright (c) 2015 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
typedef enum __packed {
    BT_CONN_DISCONNECTED,
    BT_CONN_CONNECT_SCAN,
    BT_CONN_CONNECT_DIR_ADV,
    BT_CONN_CONNECT,
    BT_CONN_CONNECTED,
    BT_CONN_DISCONNECT,
} bt_conn_state_t;

/* bt_conn flags: the flags defined here represent connection parameters */
enum {
    BT_CONN_AUTO_CONNECT,
    BT_CONN_BR_LEGACY_SECURE,     /* 16 digits legacy PIN tracker */
    BT_CONN_USER,                 /* user I/O when pairing */
    BT_CONN_BR_PAIRING,           /* BR connection in pairing context */
    BT_CONN_BR_NOBOND,            /* SSP no bond pairing tracker */
    BT_CONN_BR_PAIRING_INITIATOR, /* local host starts authentication */
    BT_CONN_CLEANUP,              /* Disconnected, pending cleanup */
    BT_CONN_AUTO_PHY_UPDATE,      /* Auto-update PHY */
    BT_CONN_SLAVE_PARAM_UPDATE,   /* If slave param update timer fired */
    BT_CONN_SLAVE_PARAM_SET,      /* If slave param were set from app */
    BT_CONN_SLAVE_PARAM_L2CAP,    /* If should force L2CAP for CPUP */
    BT_CONN_FORCE_PAIR,           /* Pairing even with existing keys. */

    BT_CONN_AUTO_PHY_COMPLETE, /* Auto-initiated PHY procedure done */
    BT_CONN_AUTO_FEATURE_EXCH, /* Auto-initiated LE Feat done */
    BT_CONN_AUTO_VERSION_INFO, /* Auto-initiated LE version done */

    /* Total number of flags - must be at the end of the enum */
    BT_CONN_NUM_FLAGS,
};

struct bt_conn_le {
    bt_addr_le_t dst;

    bt_addr_le_t init_addr;
    bt_addr_le_t resp_addr;

    u16_t interval;
    u16_t interval_min;
    u16_t interval_max;

    u16_t latency;
    u16_t timeout;
    u16_t pending_latency;
    u16_t pending_timeout;

    u8_t features[8];

    struct bt_keys *keys;

#if defined(CONFIG_BT_STACK_PTS)
    u8_t own_adder_type;
#endif
};

#if defined(CONFIG_BT_BREDR)
/* For now reserve space for 2 pages of LMP remote features */
#define LMP_MAX_PAGES 2

struct bt_conn_br {
    bt_addr_t dst;
    u8_t remote_io_capa;
    u8_t remote_auth;
    u8_t pairing_method;
    /* remote LMP features pages per 8 bytes each */
    u8_t features[LMP_MAX_PAGES][8];

    struct bt_keys_link_key *link_key;
};

struct bt_conn_sco {
    /* Reference to ACL Connection */
    struct bt_conn *acl;
    u16_t pkt_type;
};
#endif

struct bt_conn_iso {
    /* Reference to ACL Connection */
    struct bt_conn *acl;
    /* CIG ID */
    uint8_t cig_id;
    /* CIS ID */
    uint8_t cis_id;
};

typedef void (*bt_conn_tx_cb_t)(struct bt_conn *conn, void *user_data);

struct bt_conn_tx {
    sys_snode_t node;

    bt_conn_tx_cb_t cb;
    void *user_data;

    /* Number of pending packets without a callback after this one */
    u32_t pending_no_cb;
};

struct bt_conn {
    u16_t handle;
    u8_t type;
    u8_t role;

    ATOMIC_DEFINE(flags, BT_CONN_NUM_FLAGS);

    /* Which local identity address this connection uses */
    u8_t id;

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
    bt_security_t sec_level;
    bt_security_t required_sec_level;
    u8_t encrypt;
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

    /* Connection error or reason for disconnect */
    u8_t err;

    bt_conn_state_t state;

    u16_t rx_len;
    struct net_buf *rx;

    /* Sent but not acknowledged TX packets with a callback */
    sys_slist_t tx_pending;
    /* Sent but not acknowledged TX packets without a callback before
	 * the next packet (if any) in tx_pending.
	 */
    u32_t pending_no_cb;

    /* Completed TX for which we need to call the callback */
    sys_slist_t tx_complete;
    struct k_work tx_complete_work;

    /* Queue for outgoing ACL data */
    struct k_fifo tx_queue;

    /* Active L2CAP channels */
    sys_slist_t channels;

    atomic_t ref;

    /* Delayed work for connection update and other deferred tasks */
    struct k_delayed_work update_work;

    union {
        struct bt_conn_le le;
#if defined(CONFIG_BT_BREDR)
        struct bt_conn_br br;
        struct bt_conn_sco sco;
#endif
#if defined(CONFIG_BT_AUDIO)
        struct bt_conn_iso iso;
#endif
    };

#if defined(CONFIG_BT_REMOTE_VERSION)
    struct bt_conn_rv {
        u8_t version;
        u16_t manufacturer;
        u16_t subversion;
    } rv;
#endif
};

void bt_conn_reset_rx_state(struct bt_conn *conn);

/* Process incoming data for a connection */
void bt_conn_recv(struct bt_conn *conn, struct net_buf *buf, u8_t flags);

/* Send data over a connection */
int bt_conn_send_cb(struct bt_conn *conn, struct net_buf *buf,
                    bt_conn_tx_cb_t cb, void *user_data);

static inline int bt_conn_send(struct bt_conn *conn, struct net_buf *buf)
{
    return bt_conn_send_cb(conn, buf, NULL, NULL);
}

/* Add a new LE connection */
struct bt_conn *bt_conn_add_le(u8_t id, const bt_addr_le_t *peer);

/** Connection parameters for ISO connections */
struct bt_iso_create_param {
    uint8_t id;
    uint8_t num_conns;
    struct bt_conn **conns;
    struct bt_iso_chan **chans;
};

/* Bind ISO connections parameters */
int bt_conn_bind_iso(struct bt_iso_create_param *param);

/* Connect ISO connections */
int bt_conn_connect_iso(struct bt_conn **conns, uint8_t num_conns);

/* Add a new ISO connection */
struct bt_conn *bt_conn_add_iso(struct bt_conn *acl);

/* Cleanup ISO references */
void bt_iso_cleanup(struct bt_conn *iso_conn);

/* Allocate new ISO connection */
struct bt_conn *iso_conn_new(struct bt_conn *conns, size_t size);

/* Add a new BR/EDR connection */
struct bt_conn *bt_conn_add_br(const bt_addr_t *peer);

/* Add a new SCO connection */
struct bt_conn *bt_conn_add_sco(const bt_addr_t *peer, int link_type);

/* Cleanup SCO references */
void bt_sco_cleanup(struct bt_conn *sco_conn);

/* Look up an existing sco connection by BT address */
struct bt_conn *bt_conn_lookup_addr_sco(const bt_addr_t *peer);

/* Look up an existing connection by BT address */
struct bt_conn *bt_conn_lookup_addr_br(const bt_addr_t *peer);

void bt_conn_pin_code_req(struct bt_conn *conn);
u8_t bt_conn_get_io_capa(void);
u8_t bt_conn_ssp_get_auth(const struct bt_conn *conn);
void bt_conn_ssp_auth(struct bt_conn *conn, u32_t passkey);
void bt_conn_ssp_auth_complete(struct bt_conn *conn, u8_t status);

void bt_conn_disconnect_all(u8_t id);

/* Look up an existing connection */
struct bt_conn *bt_conn_lookup_handle(u16_t handle);

/* Compare an address with bt_conn destination address */
int bt_conn_addr_le_cmp(const struct bt_conn *conn, const bt_addr_le_t *peer);

/* Helpers for identifying & looking up connections based on the the index to
 * the connection list. This is useful for O(1) lookups, but can't be used
 * e.g. as the handle since that's assigned to us by the controller.
 */
#define BT_CONN_ID_INVALID 0xff
struct bt_conn *bt_conn_lookup_id(u8_t id);

/* Look up a connection state. For BT_ADDR_LE_ANY, returns the first connection
 * with the specific state
 */
struct bt_conn *bt_conn_lookup_state_le(const bt_addr_le_t *peer,
                                        const bt_conn_state_t state);

/* Set connection object in certain state and perform action related to state */
void bt_conn_set_state(struct bt_conn *conn, bt_conn_state_t state);

int bt_conn_le_conn_update(struct bt_conn *conn,
                           const struct bt_le_conn_param *param);

void notify_remote_info(struct bt_conn *conn);

void notify_le_param_updated(struct bt_conn *conn);

void notify_le_phy_updated(struct bt_conn *conn, u8_t tx_phy, u8_t rx_phy);

bool le_param_req(struct bt_conn *conn, struct bt_le_conn_param *param);

#if defined(CONFIG_BT_SMP)
/* rand and ediv should be in BT order */
int bt_conn_le_start_encryption(struct bt_conn *conn, u8_t rand[8],
                                u8_t ediv[2], const u8_t *ltk, size_t len);

/* Notify higher layers that RPA was resolved */
void bt_conn_identity_resolved(struct bt_conn *conn);
#endif /* CONFIG_BT_SMP */

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
/* Notify higher layers that connection security changed */
void bt_conn_security_changed(struct bt_conn *conn, enum bt_security_err err);
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

/* Prepare a PDU to be sent over a connection */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *bt_conn_create_pdu_timeout_debug(struct net_buf_pool *pool,
                                                 size_t reserve, s32_t timeout,
                                                 const char *func, int line);
#define bt_conn_create_pdu_timeout(_pool, _reserve, _timeout)   \
    bt_conn_create_pdu_timeout_debug(_pool, _reserve, _timeout, \
                                     __func__, __LINE__)

#define bt_conn_create_pdu(_pool, _reserve)                      \
    bt_conn_create_pdu_timeout_debug(_pool, _reserve, K_FOREVER, \
                                     __func__, __line__)
#else
struct net_buf *bt_conn_create_pdu_timeout(struct net_buf_pool *pool,
                                           size_t reserve, s32_t timeout);

#define bt_conn_create_pdu(_pool, _reserve) \
    bt_conn_create_pdu_timeout(_pool, _reserve, K_FOREVER)
#endif

/* Prepare a PDU to be sent over a connection */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *bt_conn_create_frag_timeout_debug(size_t reserve, s32_t timeout,
                                                  const char *func, int line);

#define bt_conn_create_frag_timeout(_reserve, _timeout)   \
    bt_conn_create_frag_timeout_debug(_reserve, _timeout, \
                                      __func__, __LINE__)

#define bt_conn_create_frag(_reserve)                      \
    bt_conn_create_frag_timeout_debug(_reserve, K_FOREVER, \
                                      __func__, __LINE__)
#else
struct net_buf *bt_conn_create_frag_timeout(size_t reserve, s32_t timeout);

#define bt_conn_create_frag(_reserve) \
    bt_conn_create_frag_timeout(_reserve, K_FOREVER)
#endif

/* Initialize connection management */
int bt_conn_init(void);

/* Selects based on connecton type right semaphore for ACL packets */
struct k_sem *bt_conn_get_pkts(struct bt_conn *conn);

/* k_poll related helpers for the TX thread */
int bt_conn_prepare_events(struct k_poll_event events[]);

#if (BFLB_BT_CO_THREAD)
void bt_conn_process_tx(struct bt_conn *conn, struct net_buf *tx_buf);
#else
void bt_conn_process_tx(struct bt_conn *conn);
#endif

#if defined(BFLB_BLE)
/** @brief Get connection handle for a connection.
 *
 * @param conn Connection object.
 * @param conn_handle Place to store the Connection handle.
 *
 * @return 0 on success or negative error value on failure.
 */
int bt_hci_get_conn_handle(const struct bt_conn *conn, u16_t *conn_handle);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/crypto.c
================================================
/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 

#include 
#include 

#include 
#include 
#include 

#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_HCI_CORE)
#define LOG_MODULE_NAME bt_crypto
#include "log.h"

#include "hci_core.h"

static struct tc_hmac_prng_struct prng;

static int prng_reseed(struct tc_hmac_prng_struct *h) {
  u8_t  seed[32];
  s64_t extra;
  int   ret, i;

  for (i = 0; i < (sizeof(seed) / 8); i++) {
    struct bt_hci_rp_le_rand *rp;
    struct net_buf           *rsp;

    ret = bt_hci_cmd_send_sync(BT_HCI_OP_LE_RAND, NULL, &rsp);
    if (ret) {
      return ret;
    }

    rp = (void *)rsp->data;
    memcpy(&seed[i * 8], rp->rand, 8);

    net_buf_unref(rsp);
  }

  extra = k_uptime_get();

  ret = tc_hmac_prng_reseed(h, seed, sizeof(seed), (u8_t *)&extra, sizeof(extra));
  if (ret == TC_CRYPTO_FAIL) {
    BT_ERR("Failed to re-seed PRNG");
    return -EIO;
  }

  return 0;
}

int prng_init(void) {
  struct bt_hci_rp_le_rand *rp;
  struct net_buf           *rsp;
  int                       ret;

  /* Check first that HCI_LE_Rand is supported */
  if (!BT_CMD_TEST(bt_dev.supported_commands, 27, 7)) {
    return -ENOTSUP;
  }

  ret = bt_hci_cmd_send_sync(BT_HCI_OP_LE_RAND, NULL, &rsp);
  if (ret) {
    return ret;
  }

  rp = (void *)rsp->data;

  ret = tc_hmac_prng_init(&prng, rp->rand, sizeof(rp->rand));

  net_buf_unref(rsp);

  if (ret == TC_CRYPTO_FAIL) {
    BT_ERR("Failed to initialize PRNG");
    return -EIO;
  }

  /* re-seed is needed after init */
  return prng_reseed(&prng);
}

int bt_rand(void *buf, size_t len) {
#if !defined(CONFIG_BT_GEN_RANDOM_BY_SW)
  k_get_random_byte_array(buf, len);
  return 0;
#else
  int ret;
  ret = tc_hmac_prng_generate(buf, len, &prng);
  if (ret == TC_HMAC_PRNG_RESEED_REQ) {
    ret = prng_reseed(&prng);
    if (ret) {
      return ret;
    }

    ret = tc_hmac_prng_generate(buf, len, &prng);
  }

  if (ret == TC_CRYPTO_SUCCESS) {
    return 0;
  }

  return -EIO;
#endif
}

int bt_encrypt_le(const u8_t key[16], const u8_t plaintext[16], u8_t enc_data[16]) {
  struct tc_aes_key_sched_struct s;
  u8_t                           tmp[16];

  BT_DBG("key %s", bt_hex(key, 16));
  BT_DBG("plaintext %s", bt_hex(plaintext, 16));

  sys_memcpy_swap(tmp, key, 16);

  if (tc_aes128_set_encrypt_key(&s, tmp) == TC_CRYPTO_FAIL) {
    return -EINVAL;
  }

  sys_memcpy_swap(tmp, plaintext, 16);

  if (tc_aes_encrypt(enc_data, tmp, &s) == TC_CRYPTO_FAIL) {
    return -EINVAL;
  }

  sys_mem_swap(enc_data, 16);

  BT_DBG("enc_data %s", bt_hex(enc_data, 16));

  return 0;
}

int bt_encrypt_be(const u8_t key[16], const u8_t plaintext[16], u8_t enc_data[16]) {
  struct tc_aes_key_sched_struct s;

  BT_DBG("key %s", bt_hex(key, 16));
  BT_DBG("plaintext %s", bt_hex(plaintext, 16));

  if (tc_aes128_set_encrypt_key(&s, key) == TC_CRYPTO_FAIL) {
    return -EINVAL;
  }

  if (tc_aes_encrypt(enc_data, plaintext, &s) == TC_CRYPTO_FAIL) {
    return -EINVAL;
  }

  BT_DBG("enc_data %s", bt_hex(enc_data, 16));

  return 0;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/crypto.h
================================================
/*
 * Copyright (c) 2016-2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

int prng_init(void);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/ecc.h
================================================
/* ecc.h - ECDH helpers */
#include "types.h"
/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*  @brief Container for public key callback */
struct bt_pub_key_cb {
  /** @brief Callback type for Public Key generation.
   *
   *  Used to notify of the local public key or that the local key is not
   *  available (either because of a failure to read it or because it is
   *  being regenerated).
   *
   *  @param key The local public key, or NULL in case of no key.
   */
  void (*func)(const uint8_t key[64]);

  struct bt_pub_key_cb *_next;
};

/*  @brief Generate a new Public Key.
 *
 *  Generate a new ECC Public Key. The callback will persist even after the
 *  key has been generated, and will be used to notify of new generation
 *  processes (NULL as key).
 *
 *  @param cb Callback to notify the new key, or NULL to request an update
 *            without registering any new callback.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_pub_key_gen(struct bt_pub_key_cb *cb);

/*  @brief Get the current Public Key.
 *
 *  Get the current ECC Public Key.
 *
 *  @return Current key, or NULL if not available.
 */
const uint8_t *bt_pub_key_get(void);

/*  @typedef bt_dh_key_cb_t
 *  @brief Callback type for DH Key calculation.
 *
 *  Used to notify of the calculated DH Key.
 *
 *  @param key The DH Key, or NULL in case of failure.
 */
typedef void (*bt_dh_key_cb_t)(const uint8_t key[32]);

/*  @brief Calculate a DH Key from a remote Public Key.
 *
 *  Calculate a DH Key from the remote Public Key.
 *
 *  @param remote_pk Remote Public Key.
 *  @param cb Callback to notify the calculated key.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_dh_key_gen(const uint8_t remote_pk[64], bt_dh_key_cb_t cb);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/gatt.c
================================================
/* gatt.c - Generic Attribute Profile handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

#include 

#if defined(CONFIG_BT_GATT_CACHING)
#include 
#include 

#include 

#include 
#include 
#endif /* CONFIG_BT_GATT_CACHING */
#include 
#include 
#include 
#include 
#include 
#if defined(BFLB_BLE)
#include "ble_config.h"
#include 
#endif

#if defined(CONFIG_BT_STACK_PTS)
extern u8_t event_flag;
#endif

#ifdef BT_DBG_ENABLED
#undef BT_DBG_ENABLED
#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_GATT)
#else
#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_GATT)
#endif

#define LOG_MODULE_NAME bt_gatt
#include "log.h"

#include "hci_core.h"

#include "conn_internal.h"
#include "keys.h"
#include "l2cap_internal.h"
#include "settings.h"
#include "smp.h"

#include "att_internal.h"

#include "gatt_internal.h"

#define SC_TIMEOUT      K_MSEC(10)
#define CCC_STORE_DELAY K_SECONDS(1)

#define DB_HASH_TIMEOUT K_MSEC(10)

static u16_t last_static_handle;

/* Persistent storage format for GATT CCC */
struct ccc_store {
  u16_t handle;
  u16_t value;
};

#if defined(CONFIG_BT_GATT_CLIENT)
static sys_slist_t subscriptions;
#if defined(BFLB_BLE_NOTIFY_ALL)
bt_notification_all_cb_t gatt_notify_all_cb;
#endif
#if defined(BFLB_BLE_DISCOVER_ONGOING)
uint8_t    discover_ongoing = BT_GATT_ITER_STOP;
extern int bt_gatt_discover_continue(struct bt_conn *conn, struct bt_gatt_discover_params *params);
#endif
#endif /* CONFIG_BT_GATT_CLIENT */

static const u16_t gap_appearance = CONFIG_BT_DEVICE_APPEARANCE;

#if defined(CONFIG_BT_GATT_DYNAMIC_DB)
static sys_slist_t db;
#endif /* CONFIG_BT_GATT_DYNAMIC_DB */

static atomic_t init;

#if defined(BFLB_BLE_MTU_CHANGE_CB)
bt_gatt_mtu_changed_cb_t gatt_mtu_changed_cb;
#endif

static ssize_t read_name(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  const char *name = bt_get_name();

  return bt_gatt_attr_read(conn, attr, buf, len, offset, name, strlen(name));
}

#if defined(CONFIG_BT_DEVICE_NAME_GATT_WRITABLE)

static ssize_t write_name(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags) {
  char value[CONFIG_BT_DEVICE_NAME_MAX] = {};

  if (offset) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
  }

  if (len >= sizeof(value)) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
  }

  memcpy(value, buf, len);

  bt_set_name(value);

  return len;
}

#endif /* CONFIG_BT_DEVICE_NAME_GATT_WRITABLE */

static ssize_t read_appearance(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  u16_t appearance = sys_cpu_to_le16(gap_appearance);

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &appearance, sizeof(appearance));
}

#if defined(CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS)
/* This checks if the range entered is valid */
BUILD_ASSERT(!(CONFIG_BT_PERIPHERAL_PREF_MIN_INT > 3200 && CONFIG_BT_PERIPHERAL_PREF_MIN_INT < 0xffff));
BUILD_ASSERT(!(CONFIG_BT_PERIPHERAL_PREF_MAX_INT > 3200 && CONFIG_BT_PERIPHERAL_PREF_MAX_INT < 0xffff));
BUILD_ASSERT(!(CONFIG_BT_PERIPHERAL_PREF_TIMEOUT > 3200 && CONFIG_BT_PERIPHERAL_PREF_TIMEOUT < 0xffff));
BUILD_ASSERT((CONFIG_BT_PERIPHERAL_PREF_MIN_INT == 0xffff) || (CONFIG_BT_PERIPHERAL_PREF_MIN_INT <= CONFIG_BT_PERIPHERAL_PREF_MAX_INT));

static ssize_t read_ppcp(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct __packed {
    u16_t min_int;
    u16_t max_int;
    u16_t latency;
    u16_t timeout;
  } ppcp;

  ppcp.min_int = sys_cpu_to_le16(CONFIG_BT_PERIPHERAL_PREF_MIN_INT);
  ppcp.max_int = sys_cpu_to_le16(CONFIG_BT_PERIPHERAL_PREF_MAX_INT);
  ppcp.latency = sys_cpu_to_le16(CONFIG_BT_PERIPHERAL_PREF_SLAVE_LATENCY);
  ppcp.timeout = sys_cpu_to_le16(CONFIG_BT_PERIPHERAL_PREF_TIMEOUT);

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &ppcp, sizeof(ppcp));
}
#endif

#if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PRIVACY)
static ssize_t read_central_addr_res(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  u8_t central_addr_res = BT_GATT_CENTRAL_ADDR_RES_SUPP;

  return bt_gatt_attr_read(conn, attr, buf, len, offset, ¢ral_addr_res, sizeof(central_addr_res));
}
#endif /* CONFIG_BT_CENTRAL && CONFIG_BT_PRIVACY */

#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
static struct bt_gatt_attr gap_attrs[] = {
#else
BT_GATT_SERVICE_DEFINE(_2_gap_svc,
#endif
    BT_GATT_PRIMARY_SERVICE(BT_UUID_GAP),

#if defined(CONFIG_BT_DEVICE_NAME_GATT_WRITABLE)
    /* Require pairing for writes to device name */
    BT_GATT_CHARACTERISTIC(BT_UUID_GAP_DEVICE_NAME, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, read_name, write_name, bt_dev.name),
#else
                       BT_GATT_CHARACTERISTIC(BT_UUID_GAP_DEVICE_NAME, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_name, NULL, NULL),
#endif /* CONFIG_BT_DEVICE_NAME_GATT_WRITABLE */
    BT_GATT_CHARACTERISTIC(BT_UUID_GAP_APPEARANCE, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_appearance, NULL, NULL),
#if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PRIVACY)
    BT_GATT_CHARACTERISTIC(BT_UUID_CENTRAL_ADDR_RES, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_central_addr_res, NULL, NULL),
#endif /* CONFIG_BT_CENTRAL && CONFIG_BT_PRIVACY */
#if defined(CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS)
    BT_GATT_CHARACTERISTIC(BT_UUID_GAP_PPCP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_ppcp, NULL, NULL),
#endif
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
};
#else
);
#endif

#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
static struct bt_gatt_service gap_svc = BT_GATT_SERVICE(gap_attrs);
#endif

struct sc_data {
  u16_t start;
  u16_t end;
} __packed;

struct gatt_sc_cfg {
  u8_t         id;
  bt_addr_le_t peer;
  struct {
    u16_t start;
    u16_t end;
  } data;
};

#define SC_CFG_MAX (CONFIG_BT_MAX_PAIRED + CONFIG_BT_MAX_CONN)
static struct gatt_sc_cfg sc_cfg[SC_CFG_MAX];
BUILD_ASSERT(sizeof(struct sc_data) == sizeof(sc_cfg[0].data));

static struct gatt_sc_cfg *find_sc_cfg(u8_t id, bt_addr_le_t *addr) {
  BT_DBG("id: %u, addr: %s", id, bt_addr_le_str(addr));

  for (size_t i = 0; i < ARRAY_SIZE(sc_cfg); i++) {
    if (id == sc_cfg[i].id && !bt_addr_le_cmp(&sc_cfg[i].peer, addr)) {
      return &sc_cfg[i];
    }
  }

  return NULL;
}

static void sc_store(struct gatt_sc_cfg *cfg) {
  char key[BT_SETTINGS_KEY_MAX];
  int  err;

  if (cfg->id) {
    char id_str[4];

    u8_to_dec(id_str, sizeof(id_str), cfg->id);
    bt_settings_encode_key(key, sizeof(key), "sc", &cfg->peer, id_str);
  } else {
    bt_settings_encode_key(key, sizeof(key), "sc", &cfg->peer, NULL);
  }

  err = settings_save_one(key, (u8_t *)&cfg->data, sizeof(cfg->data));
  if (err) {
    BT_ERR("failed to store SC (err %d)", err);
    return;
  }

  BT_DBG("stored SC for %s (%s, 0x%04x-0x%04x)", bt_addr_le_str(&cfg->peer), log_strdup(key), cfg->data.start, cfg->data.end);
}

static void sc_clear(struct gatt_sc_cfg *cfg) {
  BT_DBG("peer %s", bt_addr_le_str(&cfg->peer));

  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    bool modified = false;

    if (cfg->data.start || cfg->data.end) {
      modified = true;
    }

    if (modified && bt_addr_le_is_bonded(cfg->id, &cfg->peer)) {
      char key[BT_SETTINGS_KEY_MAX];
      int  err;

      if (cfg->id) {
        char id_str[4];

        u8_to_dec(id_str, sizeof(id_str), cfg->id);
        bt_settings_encode_key(key, sizeof(key), "sc", &cfg->peer, id_str);
      } else {
        bt_settings_encode_key(key, sizeof(key), "sc", &cfg->peer, NULL);
      }

      err = settings_delete(key);
      if (err) {
        BT_ERR("failed to delete SC (err %d)", err);
      } else {
        BT_DBG("deleted SC for %s (%s)", bt_addr_le_str(&cfg->peer), log_strdup(key));
      }
    }
  }

  memset(cfg, 0, sizeof(*cfg));
}

static void sc_reset(struct gatt_sc_cfg *cfg) {
  BT_DBG("peer %s", bt_addr_le_str(&cfg->peer));

  memset(&cfg->data, 0, sizeof(cfg->data));

  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    sc_store(cfg);
  }
}

static bool update_range(u16_t *start, u16_t *end, u16_t new_start, u16_t new_end) {
  BT_DBG("start 0x%04x end 0x%04x new_start 0x%04x new_end 0x%04x", *start, *end, new_start, new_end);

  /* Check if inside existing range */
  if (new_start >= *start && new_end <= *end) {
    return false;
  }

  /* Update range */
  if (*start > new_start) {
    *start = new_start;
  }

  if (*end < new_end) {
    *end = new_end;
  }

  return true;
}

static void sc_save(u8_t id, bt_addr_le_t *peer, u16_t start, u16_t end) {
  struct gatt_sc_cfg *cfg;
  bool                modified = false;

  BT_DBG("peer %s start 0x%04x end 0x%04x", bt_addr_le_str(peer), start, end);

  cfg = find_sc_cfg(id, peer);
  if (!cfg) {
    /* Find and initialize a free sc_cfg entry */
    cfg = find_sc_cfg(BT_ID_DEFAULT, BT_ADDR_LE_ANY);
    if (!cfg) {
      BT_ERR("unable to save SC: no cfg left");
      return;
    }

    cfg->id = id;
    bt_addr_le_copy(&cfg->peer, peer);
  }

  /* Check if there is any change stored */
  if (!(cfg->data.start || cfg->data.end)) {
    cfg->data.start = start;
    cfg->data.end   = end;
    modified        = true;
    goto done;
  }

  modified = update_range(&cfg->data.start, &cfg->data.end, start, end);

done:
  if (IS_ENABLED(CONFIG_BT_SETTINGS) && modified && bt_addr_le_is_bonded(cfg->id, &cfg->peer)) {
    sc_store(cfg);
  }
}

static bool sc_ccc_cfg_write(struct bt_conn *conn, const struct bt_gatt_attr *attr, u16_t value) {
  BT_DBG("value 0x%04x", value);

  if (value == BT_GATT_CCC_INDICATE) {
    /* Create a new SC configuration entry if subscribed */
    sc_save(conn->id, &conn->le.dst, 0, 0);
  } else {
    struct gatt_sc_cfg *cfg;

    /* Clear SC configuration if unsubscribed */
    cfg = find_sc_cfg(conn->id, &conn->le.dst);
    if (cfg) {
      sc_clear(cfg);
    }
  }

  return true;
}

static struct _bt_gatt_ccc sc_ccc = BT_GATT_CCC_INITIALIZER(NULL, sc_ccc_cfg_write, NULL);

#if defined(CONFIG_BT_GATT_CACHING)
enum {
  CF_CHANGE_AWARE, /* Client is changed aware */
  CF_OUT_OF_SYNC,  /* Client is out of sync */

  /* Total number of flags - must be at the end of the enum */
  CF_NUM_FLAGS,
};

#define CF_ROBUST_CACHING(_cfg) (_cfg->data[0] & BIT(0))

struct gatt_cf_cfg {
  u8_t         id;
  bt_addr_le_t peer;
  u8_t         data[1];
  ATOMIC_DEFINE(flags, CF_NUM_FLAGS);
};

#define CF_CFG_MAX (CONFIG_BT_MAX_PAIRED + CONFIG_BT_MAX_CONN)
static struct gatt_cf_cfg cf_cfg[CF_CFG_MAX] = {};

static struct gatt_cf_cfg *find_cf_cfg(struct bt_conn *conn) {
  int i;

  for (i = 0; i < ARRAY_SIZE(cf_cfg); i++) {
    if (!conn) {
      if (!bt_addr_le_cmp(&cf_cfg[i].peer, BT_ADDR_LE_ANY)) {
        return &cf_cfg[i];
      }
    } else if (!bt_conn_addr_le_cmp(conn, &cf_cfg[i].peer)) {
      return &cf_cfg[i];
    }
  }

  return NULL;
}

static ssize_t cf_read(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct gatt_cf_cfg *cfg;
  u8_t                data[1] = {};

  cfg = find_cf_cfg(conn);
  if (cfg) {
    memcpy(data, cfg->data, sizeof(data));
  }

  return bt_gatt_attr_read(conn, attr, buf, len, offset, data, sizeof(data));
}

static bool cf_set_value(struct gatt_cf_cfg *cfg, const u8_t *value, u16_t len) {
  u16_t i;
  u8_t  last_byte = 1U;
  u8_t  last_bit  = 1U;

  /* Validate the bits */
  for (i = 0U; i < len && i < last_byte; i++) {
    u8_t chg_bits = value[i] ^ cfg->data[i];
    u8_t bit;

    for (bit = 0U; bit < last_bit; bit++) {
      /* A client shall never clear a bit it has set */
      if ((BIT(bit) & chg_bits) && (BIT(bit) & cfg->data[i])) {
        return false;
      }
    }
  }

  /* Set the bits for each octect */
  for (i = 0U; i < len && i < last_byte; i++) {
    cfg->data[i] |= value[i] & ((1 << last_bit) - 1);
    BT_DBG("byte %u: data 0x%02x value 0x%02x", i, cfg->data[i], value[i]);
  }

  return true;
}

static ssize_t cf_write(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags) {
  struct gatt_cf_cfg *cfg;
  const u8_t         *value = buf;

  if (offset > sizeof(cfg->data)) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
  }

  if (offset + len > sizeof(cfg->data)) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
  }

  cfg = find_cf_cfg(conn);
  if (!cfg) {
    cfg = find_cf_cfg(NULL);
  }

  if (!cfg) {
    BT_WARN("No space to store Client Supported Features");
    return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
  }

  BT_DBG("handle 0x%04x len %u", attr->handle, len);

  if (!cf_set_value(cfg, value, len)) {
    return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
  }

  bt_addr_le_copy(&cfg->peer, &conn->le.dst);
  atomic_set_bit(cfg->flags, CF_CHANGE_AWARE);

  return len;
}

static u8_t           db_hash[16];
struct k_delayed_work db_hash_work;

struct gen_hash_state {
  struct tc_cmac_struct state;
  int                   err;
};

static u8_t gen_hash_m(const struct bt_gatt_attr *attr, void *user_data) {
  struct gen_hash_state *state = user_data;
  struct bt_uuid_16     *u16;
  u8_t                   data[16];
  ssize_t                len;
  u16_t                  value;

  if (attr->uuid->type != BT_UUID_TYPE_16)
    return BT_GATT_ITER_CONTINUE;

  u16 = (struct bt_uuid_16 *)attr->uuid;

  switch (u16->val) {
  /* Attributes to hash: handle + UUID + value */
  case 0x2800: /* GATT Primary Service */
  case 0x2801: /* GATT Secondary Service */
  case 0x2802: /* GATT Include Service */
  case 0x2803: /* GATT Characteristic */
  case 0x2900: /* GATT Characteristic Extended Properties */
    value = sys_cpu_to_le16(attr->handle);
    if (tc_cmac_update(&state->state, (uint8_t *)&value, sizeof(attr->handle)) == TC_CRYPTO_FAIL) {
      state->err = -EINVAL;
      return BT_GATT_ITER_STOP;
    }

    value = sys_cpu_to_le16(u16->val);
    if (tc_cmac_update(&state->state, (uint8_t *)&value, sizeof(u16->val)) == TC_CRYPTO_FAIL) {
      state->err = -EINVAL;
      return BT_GATT_ITER_STOP;
    }

    len = attr->read(NULL, attr, data, sizeof(data), 0);
    if (len < 0) {
      state->err = len;
      return BT_GATT_ITER_STOP;
    }

    if (tc_cmac_update(&state->state, data, len) == TC_CRYPTO_FAIL) {
      state->err = -EINVAL;
      return BT_GATT_ITER_STOP;
    }

    break;
  /* Attributes to hash: handle + UUID */
  case 0x2901: /* GATT Characteristic User Descriptor */
  case 0x2902: /* GATT Client Characteristic Configuration */
  case 0x2903: /* GATT Server Characteristic Configuration */
  case 0x2904: /* GATT Characteristic Presentation Format */
  case 0x2905: /* GATT Characteristic Aggregated Format */
    value = sys_cpu_to_le16(attr->handle);
    if (tc_cmac_update(&state->state, (uint8_t *)&value, sizeof(attr->handle)) == TC_CRYPTO_FAIL) {
      state->err = -EINVAL;
      return BT_GATT_ITER_STOP;
    }

    value = sys_cpu_to_le16(u16->val);
    if (tc_cmac_update(&state->state, (uint8_t *)&value, sizeof(u16->val)) == TC_CRYPTO_FAIL) {
      state->err = -EINVAL;
      return BT_GATT_ITER_STOP;
    }
    break;
  default:
    return BT_GATT_ITER_CONTINUE;
  }

  return BT_GATT_ITER_CONTINUE;
}

static void db_hash_store(void) {
  int err;

  err = settings_save_one("bt/hash", &db_hash, sizeof(db_hash));
  if (err) {
    BT_ERR("Failed to save Database Hash (err %d)", err);
  }

  BT_DBG("Database Hash stored");
}

static void db_hash_gen(bool store) {
  u8_t                           key[16] = {};
  struct tc_aes_key_sched_struct sched;
  struct gen_hash_state          state;

  if (tc_cmac_setup(&state.state, key, &sched) == TC_CRYPTO_FAIL) {
    BT_ERR("Unable to setup AES CMAC");
    return;
  }

  bt_gatt_foreach_attr(0x0001, 0xffff, gen_hash_m, &state);

  if (tc_cmac_final(db_hash, &state.state) == TC_CRYPTO_FAIL) {
    BT_ERR("Unable to calculate hash");
    return;
  }

  /**
   * Core 5.1 does not state the endianess of the hash.
   * However Vol 3, Part F, 3.3.1 says that multi-octet Characteristic
   * Values shall be LE unless otherwise defined. PTS expects hash to be
   * in little endianess as well. bt_smp_aes_cmac calculates the hash in
   * big endianess so we have to swap.
   */
  sys_mem_swap(db_hash, sizeof(db_hash));

#if !defined(BFLB_BLE)
  BT_HEXDUMP_DBG(db_hash, sizeof(db_hash), "Hash: ");
#endif

  if (IS_ENABLED(CONFIG_BT_SETTINGS) && store) {
    db_hash_store();
  }
}

static void db_hash_process(struct k_work *work) { db_hash_gen(true); }

static ssize_t db_hash_read(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  /* Check if db_hash is already pending in which case it shall be
   * generated immediately instead of waiting the work to complete.
   */
  if (k_delayed_work_remaining_get(&db_hash_work)) {
    k_delayed_work_cancel(&db_hash_work);
    db_hash_gen(true);
  }

  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2347:
   * 2.5.2.1 Robust Caching
   * A connected client becomes change-aware when...
   * The client reads the Database Hash characteristic and then the server
   * receives another ATT request from the client.
   */
  bt_gatt_change_aware(conn, true);

  return bt_gatt_attr_read(conn, attr, buf, len, offset, db_hash, sizeof(db_hash));
}

static void clear_cf_cfg(struct gatt_cf_cfg *cfg) {
  bt_addr_le_copy(&cfg->peer, BT_ADDR_LE_ANY);
  memset(cfg->data, 0, sizeof(cfg->data));
  atomic_set(cfg->flags, 0);
}

static void remove_cf_cfg(struct bt_conn *conn) {
  struct gatt_cf_cfg *cfg;

  cfg = find_cf_cfg(conn);
  if (!cfg) {
    return;
  }

  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2405:
   * For clients with a trusted relationship, the characteristic value
   * shall be persistent across connections. For clients without a
   * trusted relationship the characteristic value shall be set to the
   * default value at each connection.
   */
  if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
    clear_cf_cfg(cfg);
  } else {
    /* Update address in case it has changed */
    bt_addr_le_copy(&cfg->peer, &conn->le.dst);
  }
}
#endif /* CONFIG_BT_GATT_CACHING */

#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
static struct bt_gatt_attr gatt_attrs[] = {
#else
BT_GATT_SERVICE_DEFINE(_1_gatt_svc,
#endif
    BT_GATT_PRIMARY_SERVICE(BT_UUID_GATT),

#if defined(CONFIG_BT_GATT_SERVICE_CHANGED)
    /* Bluetooth 5.0, Vol3 Part G:
     * The Service Changed characteristic Attribute Handle on the server
     * shall not change if the server has a trusted relationship with any
     * client.
     */
    BT_GATT_CHARACTERISTIC(BT_UUID_GATT_SC, BT_GATT_CHRC_INDICATE, BT_GATT_PERM_NONE, NULL, NULL, NULL),

    BT_GATT_CCC_MANAGED(&sc_ccc, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),

#if defined(CONFIG_BT_GATT_CACHING)
    BT_GATT_CHARACTERISTIC(BT_UUID_GATT_CLIENT_FEATURES, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, cf_read, cf_write, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_GATT_DB_HASH, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, db_hash_read, NULL, NULL),
#endif /* CONFIG_BT_GATT_CACHING */
#endif /* CONFIG_BT_GATT_SERVICE_CHANGED */
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
};
#else
);
#endif

#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
static struct bt_gatt_service gatt_svc = BT_GATT_SERVICE(gatt_attrs);
#endif

#if defined(CONFIG_BT_GATT_DYNAMIC_DB)
static u8_t found_attr(const struct bt_gatt_attr *attr, void *user_data) {
  const struct bt_gatt_attr **found = user_data;

  *found = attr;

  return BT_GATT_ITER_STOP;
}

static const struct bt_gatt_attr *find_attr(uint16_t handle) {
  const struct bt_gatt_attr *attr = NULL;

  bt_gatt_foreach_attr(handle, handle, found_attr, &attr);

  return attr;
}

static void gatt_insert(struct bt_gatt_service *svc, u16_t last_handle) {
  struct bt_gatt_service *tmp, *prev = NULL;

  if (last_handle == 0 || svc->attrs[0].handle > last_handle) {
    sys_slist_append(&db, &svc->node);
    return;
  }

  /* DB shall always have its service in ascending order */
  SYS_SLIST_FOR_EACH_CONTAINER(&db, tmp, node) {
    if (tmp->attrs[0].handle > svc->attrs[0].handle) {
      if (prev) {
        sys_slist_insert(&db, &prev->node, &svc->node);
      } else {
        sys_slist_prepend(&db, &svc->node);
      }
      return;
    }

    prev = tmp;
  }
}

static int gatt_register(struct bt_gatt_service *svc) {
  struct bt_gatt_service *last;
  u16_t                   handle, last_handle;
  struct bt_gatt_attr    *attrs = svc->attrs;
  u16_t                   count = svc->attr_count;

  if (sys_slist_is_empty(&db)) {
    handle      = last_static_handle;
    last_handle = 0;
    goto populate;
  }

  last        = SYS_SLIST_PEEK_TAIL_CONTAINER(&db, last, node);
  handle      = last->attrs[last->attr_count - 1].handle;
  last_handle = handle;

populate:
  /* Populate the handles and append them to the list */
  for (; attrs && count; attrs++, count--) {
    if (!attrs->handle) {
      /* Allocate handle if not set already */
      attrs->handle = ++handle;
    } else if (attrs->handle > handle) {
      /* Use existing handle if valid */
      handle = attrs->handle;
    } else if (find_attr(attrs->handle)) {
      /* Service has conflicting handles */
      BT_ERR("Unable to register handle 0x%04x", attrs->handle);
      return -EINVAL;
    }

    BT_DBG("attr %p handle 0x%04x uuid %s perm 0x%02x", attrs, attrs->handle, bt_uuid_str(attrs->uuid), attrs->perm);
  }

  gatt_insert(svc, last_handle);

  return 0;
}
#endif /* CONFIG_BT_GATT_DYNAMIC_DB */

enum {
  SC_RANGE_CHANGED,    /* SC range changed */
  SC_INDICATE_PENDING, /* SC indicate pending */

  /* Total number of flags - must be at the end of the enum */
  SC_NUM_FLAGS,
};

static struct gatt_sc {
  struct bt_gatt_indicate_params params;
  u16_t                          start;
  u16_t                          end;
  struct k_delayed_work          work;
  ATOMIC_DEFINE(flags, SC_NUM_FLAGS);
} gatt_sc;

static void sc_indicate_rsp(struct bt_conn *conn, const struct bt_gatt_attr *attr, u8_t err) {
#if defined(CONFIG_BT_GATT_CACHING)
  struct gatt_cf_cfg *cfg;
#endif

  BT_DBG("err 0x%02x", err);

  atomic_clear_bit(gatt_sc.flags, SC_INDICATE_PENDING);

  /* Check if there is new change in the meantime */
  if (atomic_test_bit(gatt_sc.flags, SC_RANGE_CHANGED)) {
    /* Reschedule without any delay since it is waiting already */
    k_delayed_work_submit(&gatt_sc.work, K_NO_WAIT);
  }

#if defined(CONFIG_BT_GATT_CACHING)
  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2347:
   * 2.5.2.1 Robust Caching
   * A connected client becomes change-aware when...
   * The client receives and confirms a Service Changed indication.
   */
  cfg = find_cf_cfg(conn);
  if (cfg && CF_ROBUST_CACHING(cfg)) {
    atomic_set_bit(cfg->flags, CF_CHANGE_AWARE);
    BT_DBG("%s change-aware", bt_addr_le_str(&cfg->peer));
  }
#endif
}

static void sc_process(struct k_work *work) {
  struct gatt_sc *sc = CONTAINER_OF(work, struct gatt_sc, work);
  u16_t           sc_range[2];

  __ASSERT(!atomic_test_bit(sc->flags, SC_INDICATE_PENDING), "Indicate already pending");

  BT_DBG("start 0x%04x end 0x%04x", sc->start, sc->end);

  sc_range[0] = sys_cpu_to_le16(sc->start);
  sc_range[1] = sys_cpu_to_le16(sc->end);

  atomic_clear_bit(sc->flags, SC_RANGE_CHANGED);
  sc->start = 0U;
  sc->end   = 0U;
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  sc->params.attr = &gatt_attrs[2];
#else
  sc->params.attr = &_1_gatt_svc.attrs[2];
#endif
  sc->params.func = sc_indicate_rsp;
  sc->params.data = &sc_range[0];
  sc->params.len  = sizeof(sc_range);

  if (bt_gatt_indicate(NULL, &sc->params)) {
    /* No connections to indicate */
    return;
  }

  atomic_set_bit(sc->flags, SC_INDICATE_PENDING);
}

#if defined(CONFIG_BT_STACK_PTS)
int service_change_test(struct bt_gatt_indicate_params *params, const struct bt_conn *con) {
  u16_t sc_range[2];

  if (!params->attr) {
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
    params->attr = &gatt_attrs[2];
#else
    params->attr = &_1_gatt_svc.attrs[2];
#endif
  }
  sc_range[0] = 0x000e;
  sc_range[1] = 0x001e;

  params->data = &sc_range[0];
  params->len  = sizeof(sc_range);

  return bt_gatt_indicate(con, params);
}

#endif

#if defined(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE)
static struct gatt_ccc_store {
  struct bt_conn       *conn_list[CONFIG_BT_MAX_CONN];
  struct k_delayed_work work;
} gatt_ccc_store;

static bool gatt_ccc_conn_is_queued(struct bt_conn *conn) { return (conn == gatt_ccc_store.conn_list[bt_conn_index(conn)]); }

static void gatt_ccc_conn_unqueue(struct bt_conn *conn) {
  u8_t index = bt_conn_index(conn);

  if (gatt_ccc_store.conn_list[index] != NULL) {
    bt_conn_unref(gatt_ccc_store.conn_list[index]);
    gatt_ccc_store.conn_list[index] = NULL;
  }
}

static bool gatt_ccc_conn_queue_is_empty(void) {
  for (size_t i = 0; i < CONFIG_BT_MAX_CONN; i++) {
    if (gatt_ccc_store.conn_list[i]) {
      return false;
    }
  }

  return true;
}

static void ccc_delayed_store(struct k_work *work) {
  struct gatt_ccc_store *ccc_store = CONTAINER_OF(work, struct gatt_ccc_store, work);

  for (size_t i = 0; i < CONFIG_BT_MAX_CONN; i++) {
    struct bt_conn *conn = ccc_store->conn_list[i];

    if (!conn) {
      continue;
    }

    if (bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
      bt_gatt_store_ccc(conn->id, &conn->le.dst);
      bt_conn_unref(conn);
      ccc_store->conn_list[i] = NULL;
    }
  }
}
#endif

void bt_gatt_init(void) {
  if (!atomic_cas(&init, 0, 1)) {
    return;
  }

#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  /* Register mandatory services */
  gatt_register(&gap_svc);
  gatt_register(&gatt_svc);

#else
  Z_STRUCT_SECTION_FOREACH(bt_gatt_service_static, svc) { last_static_handle += svc->attr_count; }
#endif

#if defined(CONFIG_BT_GATT_CACHING)
  k_delayed_work_init(&db_hash_work, db_hash_process);

  /* Submit work to Generate initial hash as there could be static
   * services already in the database.
   */
  k_delayed_work_submit(&db_hash_work, DB_HASH_TIMEOUT);
#endif /* CONFIG_BT_GATT_CACHING */

  if (IS_ENABLED(CONFIG_BT_GATT_SERVICE_CHANGED)) {
    k_delayed_work_init(&gatt_sc.work, sc_process);
    if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
      /* Make sure to not send SC indications until SC
       * settings are loaded
       */
      atomic_set_bit(gatt_sc.flags, SC_INDICATE_PENDING);
    }
  }

#if defined(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE)
  k_delayed_work_init(&gatt_ccc_store.work, ccc_delayed_store);
#endif
}

#if defined(BFLB_BLE)
void bt_gatt_deinit(void) {
#if defined(CONFIG_BT_GATT_CACHING)
  k_delayed_work_del_timer(&db_hash_work);
#endif

  if (IS_ENABLED(CONFIG_BT_GATT_SERVICE_CHANGED)) {
    k_delayed_work_del_timer(&gatt_sc.work);
  }

#if defined(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE)
  k_delayed_work_del_timer(&gatt_ccc_store.work);
#endif
}
#endif

#if defined(CONFIG_BT_GATT_DYNAMIC_DB) || (defined(CONFIG_BT_GATT_CACHING) && defined(CONFIG_BT_SETTINGS))
static void sc_indicate(u16_t start, u16_t end) {
  BT_DBG("start 0x%04x end 0x%04x", start, end);

#if defined(BFLB_BLE_PATCH_SET_SCRANGE_CHAGD_ONLY_IN_CONNECTED_STATE)
  struct bt_conn *conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECTED);
  if (conn) {
#endif
    if (!atomic_test_and_set_bit(gatt_sc.flags, SC_RANGE_CHANGED)) {
      gatt_sc.start = start;
      gatt_sc.end   = end;
      goto submit;
    }
#if defined(BFLB_BLE_PATCH_SET_SCRANGE_CHAGD_ONLY_IN_CONNECTED_STATE)
  }
#endif

  if (!update_range(&gatt_sc.start, &gatt_sc.end, start, end)) {
    return;
  }

submit:
  if (atomic_test_bit(gatt_sc.flags, SC_INDICATE_PENDING)) {
    BT_DBG("indicate pending, waiting until complete...");
    return;
  }

#if defined(BFLB_BLE_PATCH_SET_SCRANGE_CHAGD_ONLY_IN_CONNECTED_STATE)
  if (conn) {
#endif
    /* Reschedule since the range has changed */
    k_delayed_work_submit(&gatt_sc.work, SC_TIMEOUT);
#if defined(BFLB_BLE_PATCH_SET_SCRANGE_CHAGD_ONLY_IN_CONNECTED_STATE)
    bt_conn_unref(conn);
  }
#endif
}
#endif /* BT_GATT_DYNAMIC_DB || (BT_GATT_CACHING && BT_SETTINGS) */

#if defined(CONFIG_BT_GATT_DYNAMIC_DB)
static void db_changed(void) {
#if defined(CONFIG_BT_GATT_CACHING)
  int i;

  k_delayed_work_submit(&db_hash_work, DB_HASH_TIMEOUT);

  for (i = 0; i < ARRAY_SIZE(cf_cfg); i++) {
    struct gatt_cf_cfg *cfg = &cf_cfg[i];

    if (!bt_addr_le_cmp(&cfg->peer, BT_ADDR_LE_ANY)) {
      continue;
    }

    if (CF_ROBUST_CACHING(cfg)) {
      /* Core Spec 5.1 | Vol 3, Part G, 2.5.2.1 Robust Caching
       *... the database changes again before the client
       * becomes change-aware in which case the error response
       * shall be sent again.
       */
      atomic_clear_bit(cfg->flags, CF_OUT_OF_SYNC);
      if (atomic_test_and_clear_bit(cfg->flags, CF_CHANGE_AWARE)) {
        BT_DBG("%s change-unaware", bt_addr_le_str(&cfg->peer));
      }
    }
  }
#endif
}

int bt_gatt_service_register(struct bt_gatt_service *svc) {
  int err;

  __ASSERT(svc, "invalid parameters\n");
  __ASSERT(svc->attrs, "invalid parameters\n");
  __ASSERT(svc->attr_count, "invalid parameters\n");

  /* Init GATT core services */
  bt_gatt_init();

  /* Do no allow to register mandatory services twice */
  if (!bt_uuid_cmp(svc->attrs[0].uuid, BT_UUID_GAP) || !bt_uuid_cmp(svc->attrs[0].uuid, BT_UUID_GATT)) {
    return -EALREADY;
  }

  err = gatt_register(svc);
  if (err < 0) {
    return err;
  }

  sc_indicate(svc->attrs[0].handle, svc->attrs[svc->attr_count - 1].handle);

  db_changed();

  return 0;
}

int bt_gatt_service_unregister(struct bt_gatt_service *svc) {
  __ASSERT(svc, "invalid parameters\n");

  if (!sys_slist_find_and_remove(&db, &svc->node)) {
    return -ENOENT;
  }

  sc_indicate(svc->attrs[0].handle, svc->attrs[svc->attr_count - 1].handle);

  db_changed();

  return 0;
}
#endif /* CONFIG_BT_GATT_DYNAMIC_DB */

ssize_t bt_gatt_attr_read(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t buf_len, u16_t offset, const void *value, u16_t value_len) {
  u16_t len;
#if defined(CONFIG_BT_STACK_PTS)
  u8_t *data = NULL;
  u8_t  i    = 0;
#endif

  if (offset > value_len) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
  }

  len = MIN(buf_len, value_len - offset);

  BT_DBG("handle 0x%04x offset %u length %u", attr->handle, offset, len);

  memcpy(buf, (u8_t *)value + offset, len);

#if defined(CONFIG_BT_STACK_PTS)
  /* PTS sends a request to iut read all primary services it contains.
   * Set event flags to avoid comflicts when other test cases need to add reference codes.
   */
  if (event_flag == att_read_by_group_type_ind) {
    data = (u8_t *)buf;
    for (i = 0; i < len; i++) {
      BT_PTS("%s:handle = [0x%04x], data[%d] = [0x%x]\r\n", __func__, attr->handle, i, data[i]);
    }
  }
#endif

  return len;
}

ssize_t bt_gatt_attr_read_service(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct bt_uuid *uuid = attr->user_data;

  if (uuid->type == BT_UUID_TYPE_16) {
    u16_t uuid16 = sys_cpu_to_le16(BT_UUID_16(uuid)->val);

    return bt_gatt_attr_read(conn, attr, buf, len, offset, &uuid16, 2);
  }

  return bt_gatt_attr_read(conn, attr, buf, len, offset, BT_UUID_128(uuid)->val, 16);
}

struct gatt_incl {
  u16_t start_handle;
  u16_t end_handle;
  u16_t uuid16;
} __packed;

static u8_t get_service_handles(const struct bt_gatt_attr *attr, void *user_data) {
  struct gatt_incl *include = user_data;

  /* Stop if attribute is a service */
  if (!bt_uuid_cmp(attr->uuid, BT_UUID_GATT_PRIMARY) || !bt_uuid_cmp(attr->uuid, BT_UUID_GATT_SECONDARY)) {
    return BT_GATT_ITER_STOP;
  }

  include->end_handle = attr->handle;

  return BT_GATT_ITER_CONTINUE;
}

#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
static u16_t find_static_attr(const struct bt_gatt_attr *attr) {
  u16_t handle = 1;

  Z_STRUCT_SECTION_FOREACH(bt_gatt_service_static, static_svc) {
    for (int i = 0; i < static_svc->attr_count; i++, handle++) {
      if (attr == &static_svc->attrs[i]) {
        return handle;
      }
    }
  }

  return 0;
}
#endif

ssize_t bt_gatt_attr_read_included(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct bt_gatt_attr *incl = attr->user_data;
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  u16_t handle = incl->handle;
#else
  u16_t handle = incl->handle ?: find_static_attr(incl);
#endif
  struct bt_uuid  *uuid = incl->user_data;
  struct gatt_incl pdu;
  u8_t             value_len;

  /* first attr points to the start handle */
  pdu.start_handle = sys_cpu_to_le16(handle);
  value_len        = sizeof(pdu.start_handle) + sizeof(pdu.end_handle);

  /*
   * Core 4.2, Vol 3, Part G, 3.2,
   * The Service UUID shall only be present when the UUID is a
   * 16-bit Bluetooth UUID.
   */
  if (uuid->type == BT_UUID_TYPE_16) {
    pdu.uuid16 = sys_cpu_to_le16(BT_UUID_16(uuid)->val);
    value_len += sizeof(pdu.uuid16);
  }

  /* Lookup for service end handle */
  bt_gatt_foreach_attr(handle + 1, 0xffff, get_service_handles, &pdu);

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &pdu, value_len);
}

struct gatt_chrc {
  u8_t  properties;
  u16_t value_handle;
  union {
    u16_t uuid16;
    u8_t  uuid[16];
  };
} __packed;

uint16_t bt_gatt_attr_value_handle(const struct bt_gatt_attr *attr) {
  u16_t handle = 0;

  if ((attr != NULL) && (attr->read == bt_gatt_attr_read_chrc)) {
    struct bt_gatt_chrc *chrc = attr->user_data;

    handle = chrc->value_handle;
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
    if (handle == 0) {
      /* Fall back to Zephyr value handle policy */
      handle = (attr->handle ?: find_static_attr(attr)) + 1U;
    }
#endif
  }

  return handle;
}

ssize_t bt_gatt_attr_read_chrc(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct bt_gatt_chrc *chrc = attr->user_data;
  struct gatt_chrc     pdu;
  u8_t                 value_len;

  pdu.properties = chrc->properties;
  /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] page 534:
   * 3.3.2 Characteristic Value Declaration
   * The Characteristic Value declaration contains the value of the
   * characteristic. It is the first Attribute after the characteristic
   * declaration. All characteristic definitions shall have a
   * Characteristic Value declaration.
   */
  pdu.value_handle = sys_cpu_to_le16(bt_gatt_attr_value_handle(attr));

  value_len = sizeof(pdu.properties) + sizeof(pdu.value_handle);

  if (chrc->uuid->type == BT_UUID_TYPE_16) {
    pdu.uuid16 = sys_cpu_to_le16(BT_UUID_16(chrc->uuid)->val);
    value_len += 2U;
  } else {
    memcpy(pdu.uuid, BT_UUID_128(chrc->uuid)->val, 16);
    value_len += 16U;
  }

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &pdu, value_len);
}

static u8_t gatt_foreach_iter(const struct bt_gatt_attr *attr, u16_t start_handle, u16_t end_handle, const struct bt_uuid *uuid, const void *attr_data, uint16_t *num_matches, bt_gatt_attr_func_t func,
                              void *user_data) {
  u8_t result;

  /* Stop if over the requested range */
  if (attr->handle > end_handle) {
    return BT_GATT_ITER_STOP;
  }

  /* Check if attribute handle is within range */
  if (attr->handle < start_handle) {
    return BT_GATT_ITER_CONTINUE;
  }

  /* Match attribute UUID if set */
  if (uuid && bt_uuid_cmp(uuid, attr->uuid)) {
    return BT_GATT_ITER_CONTINUE;
  }

  /* Match attribute user_data if set */
  if (attr_data && attr_data != attr->user_data) {
    return BT_GATT_ITER_CONTINUE;
  }

  *num_matches -= 1;

  result = func(attr, user_data);

  if (!*num_matches) {
    return BT_GATT_ITER_STOP;
  }

  return result;
}

static void foreach_attr_type_dyndb(u16_t start_handle, u16_t end_handle, const struct bt_uuid *uuid, const void *attr_data, uint16_t num_matches, bt_gatt_attr_func_t func, void *user_data) {
#if defined(CONFIG_BT_GATT_DYNAMIC_DB)
  int i;

  struct bt_gatt_service *svc;

  SYS_SLIST_FOR_EACH_CONTAINER(&db, svc, node) {
    struct bt_gatt_service *next;

    next = SYS_SLIST_PEEK_NEXT_CONTAINER(svc, node);
    if (next) {
      /* Skip ahead if start is not within service handles */
      if (next->attrs[0].handle <= start_handle) {
        continue;
      }
    }

    for (i = 0; i < svc->attr_count; i++) {
      struct bt_gatt_attr *attr = &svc->attrs[i];

      if (gatt_foreach_iter(attr, start_handle, end_handle, uuid, attr_data, &num_matches, func, user_data) == BT_GATT_ITER_STOP) {
        return;
      }
    }
  }
#endif /* CONFIG_BT_GATT_DYNAMIC_DB */
}

void bt_gatt_foreach_attr_type(u16_t start_handle, u16_t end_handle, const struct bt_uuid *uuid, const void *attr_data, uint16_t num_matches, bt_gatt_attr_func_t func, void *user_data) {
  int i;

  if (!num_matches) {
    num_matches = UINT16_MAX;
  }
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  if (start_handle <= last_static_handle) {
    u16_t handle = 1;

    Z_STRUCT_SECTION_FOREACH(bt_gatt_service_static, static_svc) {
      /* Skip ahead if start is not within service handles */
      if (handle + static_svc->attr_count < start_handle) {
        handle += static_svc->attr_count;
        continue;
      }

      for (i = 0; i < static_svc->attr_count; i++, handle++) {
        struct bt_gatt_attr attr;

        memcpy(&attr, &static_svc->attrs[i], sizeof(attr));

        attr.handle = handle;

        if (gatt_foreach_iter(&attr, start_handle, end_handle, uuid, attr_data, &num_matches, func, user_data) == BT_GATT_ITER_STOP) {
          return;
        }
      }
    }
  }
#endif
  /* Iterate over dynamic db */
  foreach_attr_type_dyndb(start_handle, end_handle, uuid, attr_data, num_matches, func, user_data);
}

static u8_t find_next(const struct bt_gatt_attr *attr, void *user_data) {
  struct bt_gatt_attr **next = user_data;

  *next = (struct bt_gatt_attr *)attr;

  return BT_GATT_ITER_STOP;
}

struct bt_gatt_attr *bt_gatt_attr_next(const struct bt_gatt_attr *attr) {
  struct bt_gatt_attr *next = NULL;
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  u16_t handle = attr->handle;
#else
  u16_t handle = attr->handle ?: find_static_attr(attr);
#endif
  bt_gatt_foreach_attr(handle + 1, handle + 1, find_next, &next);

  return next;
}

static void clear_ccc_cfg(struct bt_gatt_ccc_cfg *cfg) {
  bt_addr_le_copy(&cfg->peer, BT_ADDR_LE_ANY);
  cfg->id    = 0U;
  cfg->value = 0U;
}

static struct bt_gatt_ccc_cfg *find_ccc_cfg(const struct bt_conn *conn, struct _bt_gatt_ccc *ccc) {
  for (size_t i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    if (conn) {
      if (conn->id == ccc->cfg[i].id && !bt_conn_addr_le_cmp(conn, &ccc->cfg[i].peer)) {
        return &ccc->cfg[i];
      }
    } else if (!bt_addr_le_cmp(&ccc->cfg[i].peer, BT_ADDR_LE_ANY)) {
      return &ccc->cfg[i];
    }
  }

  return NULL;
}

ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  struct _bt_gatt_ccc          *ccc = attr->user_data;
  const struct bt_gatt_ccc_cfg *cfg;
  u16_t                         value;

  cfg = find_ccc_cfg(conn, ccc);
  if (cfg) {
    value = sys_cpu_to_le16(cfg->value);
  } else {
    /* Default to disable if there is no cfg for the peer */
    value = 0x0000;
  }

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &value, sizeof(value));
}

static void gatt_ccc_changed(const struct bt_gatt_attr *attr, struct _bt_gatt_ccc *ccc) {
  int   i;
  u16_t value = 0x0000;

  for (i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    if (ccc->cfg[i].value > value) {
      value = ccc->cfg[i].value;
    }
  }

  BT_DBG("ccc %p value 0x%04x", ccc, value);

  if (value != ccc->value) {
    ccc->value = value;
    if (ccc->cfg_changed) {
      ccc->cfg_changed(attr, value);
    }
  }
}

ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags) {
  struct _bt_gatt_ccc    *ccc = attr->user_data;
  struct bt_gatt_ccc_cfg *cfg;
  u16_t                   value;

  if (offset) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
  }

  if (!len || len > sizeof(u16_t)) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
  }

  if (len < sizeof(u16_t)) {
    value = *(u8_t *)buf;
  } else {
    value = sys_get_le16(buf);
  }

  cfg = find_ccc_cfg(conn, ccc);
  if (!cfg) {
    /* If there's no existing entry, but the new value is zero,
     * we don't need to do anything, since a disabled CCC is
     * behavioraly the same as no written CCC.
     */
    if (!value) {
      return len;
    }

    cfg = find_ccc_cfg(NULL, ccc);
    if (!cfg) {
      BT_WARN("No space to store CCC cfg");
      return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
    }

    bt_addr_le_copy(&cfg->peer, &conn->le.dst);
    cfg->id = conn->id;
  }

  /* Confirm write if cfg is managed by application */
  if (ccc->cfg_write && !ccc->cfg_write(conn, attr, value)) {
    return BT_GATT_ERR(BT_ATT_ERR_WRITE_NOT_PERMITTED);
  }

  cfg->value = value;

  BT_DBG("handle 0x%04x value %u", attr->handle, cfg->value);

  /* Update cfg if don't match */
  if (cfg->value != ccc->value) {
    gatt_ccc_changed(attr, ccc);

#if defined(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE)
    if ((!gatt_ccc_conn_is_queued(conn)) && bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
      /* Store the connection with the same index it has in
       * the conns array
       */
      gatt_ccc_store.conn_list[bt_conn_index(conn)] = bt_conn_ref(conn);
      k_delayed_work_submit(&gatt_ccc_store.work, CCC_STORE_DELAY);
    }
#endif
  }

  /* Disabled CCC is the same as no configured CCC, so clear the entry */
  if (!value) {
    clear_ccc_cfg(cfg);
  }

  return len;
}

ssize_t bt_gatt_attr_read_cep(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  const struct bt_gatt_cep *value = attr->user_data;
  u16_t                     props = sys_cpu_to_le16(value->properties);

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &props, sizeof(props));
}

ssize_t bt_gatt_attr_read_cud(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  const char *value = attr->user_data;

  return bt_gatt_attr_read(conn, attr, buf, len, offset, value, strlen(value));
}

ssize_t bt_gatt_attr_read_cpf(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  const struct bt_gatt_cpf *value = attr->user_data;

  return bt_gatt_attr_read(conn, attr, buf, len, offset, value, sizeof(*value));
}

struct notify_data {
  int   err;
  u16_t type;
  union {
    struct bt_gatt_notify_params   *nfy_params;
    struct bt_gatt_indicate_params *ind_params;
  };
};

static int gatt_notify(struct bt_conn *conn, u16_t handle, struct bt_gatt_notify_params *params) {
  struct net_buf       *buf;
  struct bt_att_notify *nfy;

#if defined(CONFIG_BT_GATT_ENFORCE_CHANGE_UNAWARE)
  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2350:
   * Except for the Handle Value indication, the  server shall not send
   * notifications and indications to such a client until it becomes
   * change-aware.
   */
  if (!bt_gatt_change_aware(conn, false)) {
    return -EAGAIN;
  }
#endif

  buf = bt_att_create_pdu(conn, BT_ATT_OP_NOTIFY, sizeof(*nfy) + params->len);
  if (!buf) {
    BT_WARN("No buffer available to send notification");
    return -ENOMEM;
  }

  BT_DBG("conn %p handle 0x%04x", conn, handle);

  nfy         = net_buf_add(buf, sizeof(*nfy));
  nfy->handle = sys_cpu_to_le16(handle);

  net_buf_add(buf, params->len);
  memcpy(nfy->value, params->data, params->len);

  return bt_att_send(conn, buf, params->func, params->user_data);
}

static void gatt_indicate_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_indicate_params *params = user_data;

  params->func(conn, params->attr, err);
}

static int gatt_send(struct bt_conn *conn, struct net_buf *buf, bt_att_func_t func, void *params, bt_att_destroy_t destroy) {
  int err;

  if (params) {
    struct bt_att_req *req = params;
    req->buf               = buf;
    req->func              = func;
    req->destroy           = destroy;

    err = bt_att_req_send(conn, req);
  } else {
    err = bt_att_send(conn, buf, NULL, NULL);
  }

  if (err) {
    BT_ERR("Error sending ATT PDU: %d", err);
  }

  return err;
}

static int gatt_indicate(struct bt_conn *conn, u16_t handle, struct bt_gatt_indicate_params *params) {
  struct net_buf         *buf;
  struct bt_att_indicate *ind;

#if defined(CONFIG_BT_GATT_ENFORCE_CHANGE_UNAWARE)
  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2350:
   * Except for the Handle Value indication, the  server shall not send
   * notifications and indications to such a client until it becomes
   * change-aware.
   */
  if (!(params->func && (params->func == sc_indicate_rsp || params->func == sc_restore_rsp)) && !bt_gatt_change_aware(conn, false)) {
    return -EAGAIN;
  }
#endif

  buf = bt_att_create_pdu(conn, BT_ATT_OP_INDICATE, sizeof(*ind) + params->len);
  if (!buf) {
    BT_WARN("No buffer available to send indication");
    return -ENOMEM;
  }

  BT_DBG("conn %p handle 0x%04x", conn, handle);

  ind         = net_buf_add(buf, sizeof(*ind));
  ind->handle = sys_cpu_to_le16(handle);

  net_buf_add(buf, params->len);
  memcpy(ind->value, params->data, params->len);

  if (!params->func) {
    return gatt_send(conn, buf, NULL, NULL, NULL);
  }

  return gatt_send(conn, buf, gatt_indicate_rsp, params, NULL);
}

static u8_t notify_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct notify_data  *data = user_data;
  struct _bt_gatt_ccc *ccc;
  size_t               i;

  /* Check attribute user_data must be of type struct _bt_gatt_ccc */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  /* Save Service Changed data if peer is not connected */
  if (IS_ENABLED(CONFIG_BT_GATT_SERVICE_CHANGED) && ccc == &sc_ccc) {
    for (i = 0; i < ARRAY_SIZE(sc_cfg); i++) {
      struct gatt_sc_cfg *cfg = &sc_cfg[i];
      struct bt_conn     *conn;

      if (!bt_addr_le_cmp(&cfg->peer, BT_ADDR_LE_ANY)) {
        continue;
      }

      conn = bt_conn_lookup_state_le(&cfg->peer, BT_CONN_CONNECTED);
      if (!conn) {
        struct sc_data *sc;

        sc = (struct sc_data *)data->ind_params->data;
        sc_save(cfg->id, &cfg->peer, sys_le16_to_cpu(sc->start), sys_le16_to_cpu(sc->end));
        continue;
      }
      bt_conn_unref(conn);
    }
  }

  /* Notify all peers configured */
  for (i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    struct bt_gatt_ccc_cfg *cfg = &ccc->cfg[i];
    struct bt_conn         *conn;
    int                     err;

    /* Check if config value matches data type since consolidated
     * value may be for a different peer.
     */
    if (cfg->value != data->type) {
      continue;
    }

    conn = bt_conn_lookup_addr_le(cfg->id, &cfg->peer);
    if (!conn) {
      continue;
    }

    if (conn->state != BT_CONN_CONNECTED) {
      bt_conn_unref(conn);
      continue;
    }

    /* Confirm match if cfg is managed by application */
    if (ccc->cfg_match && !ccc->cfg_match(conn, attr)) {
      bt_conn_unref(conn);
      continue;
    }

    if (data->type == BT_GATT_CCC_INDICATE) {
      err = gatt_indicate(conn, attr->handle - 1, data->ind_params);
    } else {
      err = gatt_notify(conn, attr->handle - 1, data->nfy_params);
    }

    bt_conn_unref(conn);

    if (err < 0) {
      return BT_GATT_ITER_STOP;
    }

    data->err = 0;
  }

  return BT_GATT_ITER_CONTINUE;
}

static u8_t match_uuid(const struct bt_gatt_attr *attr, void *user_data) {
  const struct bt_gatt_attr **found = user_data;

  *found = attr;

  return BT_GATT_ITER_STOP;
}

int bt_gatt_notify_cb(struct bt_conn *conn, struct bt_gatt_notify_params *params) {
  struct notify_data         data;
  const struct bt_gatt_attr *attr;
  u16_t                      handle;

  __ASSERT(params, "invalid parameters\n");
  __ASSERT(params->attr, "invalid parameters\n");

  attr = params->attr;

  if (conn && conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  handle = attr->handle ?: find_static_attr(attr);
#endif
  if (!handle) {
    return -ENOENT;
  }

  /* Lookup UUID if it was given */
  if (params->uuid) {
    attr = NULL;

    bt_gatt_foreach_attr_type(handle, 0xffff, params->uuid, NULL, 1, match_uuid, &attr);
    if (!attr) {
      return -ENOENT;
    }
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
    handle = attr->handle ?: find_static_attr(attr);
#endif
    if (!handle) {
      return -ENOENT;
    }
  }

  /* Check if attribute is a characteristic then adjust the handle */
  if (!bt_uuid_cmp(attr->uuid, BT_UUID_GATT_CHRC)) {
    struct bt_gatt_chrc *chrc = attr->user_data;

    if (!(chrc->properties & BT_GATT_CHRC_NOTIFY)) {
      return -EINVAL;
    }

    handle = bt_gatt_attr_value_handle(attr);
  }

  if (conn) {
    return gatt_notify(conn, handle, params);
  }

  data.err        = -ENOTCONN;
  data.type       = BT_GATT_CCC_NOTIFY;
  data.nfy_params = params;

  bt_gatt_foreach_attr_type(handle, 0xffff, BT_UUID_GATT_CCC, NULL, 1, notify_cb, &data);

  return data.err;
}

int bt_gatt_indicate(struct bt_conn *conn, struct bt_gatt_indicate_params *params) {
  struct notify_data         data;
  const struct bt_gatt_attr *attr;
  u16_t                      handle;

  __ASSERT(params, "invalid parameters\n");
  __ASSERT(params->attr, "invalid parameters\n");

  attr = params->attr;

  if (conn && conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  handle = attr->handle ?: find_static_attr(attr);
#endif
  if (!handle) {
    return -ENOENT;
  }

  /* Lookup UUID if it was given */
  if (params->uuid) {
    attr = NULL;

    bt_gatt_foreach_attr_type(handle, 0xffff, params->uuid, NULL, 1, match_uuid, &attr);
    if (!attr) {
      return -ENOENT;
    }
#if !defined(BFLB_BLE_DISABLE_STATIC_ATTR)
    handle = attr->handle ?: find_static_attr(attr);
#endif
    if (!handle) {
      return -ENOENT;
    }
  }

  /* Check if attribute is a characteristic then adjust the handle */
  if (!bt_uuid_cmp(attr->uuid, BT_UUID_GATT_CHRC)) {
    struct bt_gatt_chrc *chrc = params->attr->user_data;

    if (!(chrc->properties & BT_GATT_CHRC_INDICATE)) {
      return -EINVAL;
    }

    handle = bt_gatt_attr_value_handle(params->attr);
  }

  if (conn) {
    return gatt_indicate(conn, handle, params);
  }

  data.err        = -ENOTCONN;
  data.type       = BT_GATT_CCC_INDICATE;
  data.ind_params = params;

  bt_gatt_foreach_attr_type(handle, 0xffff, BT_UUID_GATT_CCC, NULL, 1, notify_cb, &data);

  return data.err;
}

u16_t bt_gatt_get_mtu(struct bt_conn *conn) { return bt_att_get_mtu(conn); }

u8_t bt_gatt_check_perm(struct bt_conn *conn, const struct bt_gatt_attr *attr, u8_t mask) {
  if ((mask & BT_GATT_PERM_READ) && (!(attr->perm & BT_GATT_PERM_READ_MASK) || !attr->read)) {
    return BT_ATT_ERR_READ_NOT_PERMITTED;
  }

  if ((mask & BT_GATT_PERM_WRITE) && (!(attr->perm & BT_GATT_PERM_WRITE_MASK) || !attr->write)) {
    return BT_ATT_ERR_WRITE_NOT_PERMITTED;
  }

  mask &= attr->perm;
  if (mask & BT_GATT_PERM_AUTHEN_MASK) {
    if (bt_conn_get_security(conn) < BT_SECURITY_L3) {
      return BT_ATT_ERR_AUTHENTICATION;
    }
  }

  if ((mask & BT_GATT_PERM_ENCRYPT_MASK)) {
#if defined(CONFIG_BT_SMP)
    if (!conn->encrypt) {
      return BT_ATT_ERR_INSUFFICIENT_ENCRYPTION;
    }
#else
    return BT_ATT_ERR_INSUFFICIENT_ENCRYPTION;
#endif /* CONFIG_BT_SMP */
  }

  return 0;
}

static void sc_restore_rsp(struct bt_conn *conn, const struct bt_gatt_attr *attr, u8_t err) {
#if defined(CONFIG_BT_GATT_CACHING)
  struct gatt_cf_cfg *cfg;
#endif

  BT_DBG("err 0x%02x", err);

#if defined(CONFIG_BT_GATT_CACHING)
  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2347:
   * 2.5.2.1 Robust Caching
   * A connected client becomes change-aware when...
   * The client receives and confirms a Service Changed indication.
   */
  cfg = find_cf_cfg(conn);
  if (cfg && CF_ROBUST_CACHING(cfg)) {
    atomic_set_bit(cfg->flags, CF_CHANGE_AWARE);
    BT_DBG("%s change-aware", bt_addr_le_str(&cfg->peer));
  }
#endif
}

static struct bt_gatt_indicate_params sc_restore_params[CONFIG_BT_MAX_CONN];

static void sc_restore(struct bt_conn *conn) {
  struct gatt_sc_cfg *cfg;
  u16_t               sc_range[2];
  u8_t                index;

  cfg = find_sc_cfg(conn->id, &conn->le.dst);
  if (!cfg) {
    BT_DBG("no SC data found");
    return;
  }

  if (!(cfg->data.start || cfg->data.end)) {
    return;
  }

  BT_DBG("peer %s start 0x%04x end 0x%04x", bt_addr_le_str(&cfg->peer), cfg->data.start, cfg->data.end);

  sc_range[0] = sys_cpu_to_le16(cfg->data.start);
  sc_range[1] = sys_cpu_to_le16(cfg->data.end);

  index = bt_conn_index(conn);
#if defined(BFLB_BLE_DISABLE_STATIC_ATTR)
  sc_restore_params[index].attr = &gatt_attrs[2];
#else
  sc_restore_params[index].attr = &_1_gatt_svc.attrs[2];
#endif
  sc_restore_params[index].func = sc_restore_rsp;
  sc_restore_params[index].data = &sc_range[0];
  sc_restore_params[index].len  = sizeof(sc_range);

  if (bt_gatt_indicate(conn, &sc_restore_params[index])) {
    BT_ERR("SC restore indication failed");
  }

  /* Reset config data */
  sc_reset(cfg);
}

struct conn_data {
  struct bt_conn *conn;
  bt_security_t   sec;
};

static u8_t update_ccc(const struct bt_gatt_attr *attr, void *user_data) {
  struct conn_data    *data = user_data;
  struct bt_conn      *conn = data->conn;
  struct _bt_gatt_ccc *ccc;
  size_t               i;
  u8_t                 err;

  /* Check attribute user_data must be of type struct _bt_gatt_ccc */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  for (i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    /* Ignore configuration for different peer */
    if (bt_conn_addr_le_cmp(conn, &ccc->cfg[i].peer)) {
      continue;
    }

    /* Check if attribute requires encryption/authentication */
    err = bt_gatt_check_perm(conn, attr, BT_GATT_PERM_WRITE_MASK);
    if (err) {
      bt_security_t sec;

      if (err == BT_ATT_ERR_WRITE_NOT_PERMITTED) {
        BT_WARN("CCC %p not writable", attr);
        continue;
      }

      sec = BT_SECURITY_L2;

      if (err == BT_ATT_ERR_AUTHENTICATION) {
        sec = BT_SECURITY_L3;
      }

      /* Check if current security is enough */
      if (IS_ENABLED(CONFIG_BT_SMP) && bt_conn_get_security(conn) < sec) {
        if (data->sec < sec) {
          data->sec = sec;
        }
        continue;
      }
    }

    if (ccc->cfg[i].value) {
      gatt_ccc_changed(attr, ccc);
      if (IS_ENABLED(CONFIG_BT_GATT_SERVICE_CHANGED) && ccc == &sc_ccc) {
        sc_restore(conn);
      }
      return BT_GATT_ITER_CONTINUE;
    }
  }

  return BT_GATT_ITER_CONTINUE;
}

static u8_t disconnected_cb(const struct bt_gatt_attr *attr, void *user_data) {
  struct bt_conn      *conn = user_data;
  struct _bt_gatt_ccc *ccc;
  bool                 value_used;
  size_t               i;

  /* Check attribute user_data must be of type struct _bt_gatt_ccc */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  /* If already disabled skip */
  if (!ccc->value) {
    return BT_GATT_ITER_CONTINUE;
  }

  /* Checking if all values are disabled */
  value_used = false;

  for (i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    struct bt_gatt_ccc_cfg *cfg = &ccc->cfg[i];

    /* Ignore configurations with disabled value */
    if (!cfg->value) {
      continue;
    }

    if (conn->id != cfg->id || bt_conn_addr_le_cmp(conn, &cfg->peer)) {
      struct bt_conn *tmp;

      /* Skip if there is another peer connected */
      tmp = bt_conn_lookup_addr_le(cfg->id, &cfg->peer);
      if (tmp) {
        if (tmp->state == BT_CONN_CONNECTED) {
          value_used = true;
        }

        bt_conn_unref(tmp);
      }
    } else {
      /* Clear value if not paired */
      if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
        clear_ccc_cfg(cfg);
      } else {
        /* Update address in case it has changed */
        bt_addr_le_copy(&cfg->peer, &conn->le.dst);
      }
    }
  }

  /* If all values are now disabled, reset value while disconnected */
  if (!value_used) {
    ccc->value = 0U;
    if (ccc->cfg_changed) {
      ccc->cfg_changed(attr, ccc->value);
    }

    BT_DBG("ccc %p reseted", ccc);
  }

  return BT_GATT_ITER_CONTINUE;
}

bool bt_gatt_is_subscribed(struct bt_conn *conn, const struct bt_gatt_attr *attr, u16_t ccc_value) {
  const struct _bt_gatt_ccc *ccc;

  __ASSERT(conn, "invalid parameter\n");
  __ASSERT(attr, "invalid parameter\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return false;
  }

  /* Check if attribute is a characteristic declaration */
  if (!bt_uuid_cmp(attr->uuid, BT_UUID_GATT_CHRC)) {
    struct bt_gatt_chrc *chrc = attr->user_data;

    if (!(chrc->properties & (BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_INDICATE))) {
      /* Characteristic doesn't support subscription */
      return false;
    }

    attr = bt_gatt_attr_next(attr);
  }

  /* Check if attribute is a characteristic value */
  if (bt_uuid_cmp(attr->uuid, BT_UUID_GATT_CCC) != 0) {
    attr = bt_gatt_attr_next(attr);
  }

  /* Check if the attribute is the CCC Descriptor */
  if (bt_uuid_cmp(attr->uuid, BT_UUID_GATT_CCC) != 0) {
    return false;
  }

  ccc = attr->user_data;

  /* Check if the connection is subscribed */
  for (size_t i = 0; i < BT_GATT_CCC_MAX; i++) {
    if (conn->id == ccc->cfg[i].id && !bt_conn_addr_le_cmp(conn, &ccc->cfg[i].peer) && (ccc_value & ccc->cfg[i].value)) {
      return true;
    }
  }

  return false;
}

#if defined(CONFIG_BT_GATT_CLIENT)
#if defined(BFLB_BLE_NOTIFY_ALL)
void bt_gatt_register_notification_callback(bt_notification_all_cb_t cb) { gatt_notify_all_cb = cb; }
#endif
void bt_gatt_notification(struct bt_conn *conn, u16_t handle, const void *data, u16_t length) {
  struct bt_gatt_subscribe_params *params, *tmp;

  BT_DBG("handle 0x%04x length %u", handle, length);
#if defined(BFLB_BLE_NOTIFY_ALL)
  if (gatt_notify_all_cb) {
    gatt_notify_all_cb(conn, handle, data, length);
  }
#endif
  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&subscriptions, params, tmp, node) {
    if (bt_conn_addr_le_cmp(conn, ¶ms->_peer) || handle != params->value_handle) {
      continue;
    }

    if (params->notify(conn, params, data, length) == BT_GATT_ITER_STOP) {
      bt_gatt_unsubscribe(conn, params);
    }
  }
}

static void update_subscription(struct bt_conn *conn, struct bt_gatt_subscribe_params *params) {
  if (params->_peer.type == BT_ADDR_LE_PUBLIC) {
    return;
  }

  /* Update address */
  bt_addr_le_copy(¶ms->_peer, &conn->le.dst);
}

static void gatt_subscription_remove(struct bt_conn *conn, sys_snode_t *prev, struct bt_gatt_subscribe_params *params) {
  /* Remove subscription from the list*/
  sys_slist_remove(&subscriptions, prev, ¶ms->node);

  params->notify(conn, params, NULL, 0);
}

static void remove_subscriptions(struct bt_conn *conn) {
  struct bt_gatt_subscribe_params *params, *tmp;
  sys_snode_t                     *prev = NULL;

  /* Lookup existing subscriptions */
  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&subscriptions, params, tmp, node) {
    if (bt_conn_addr_le_cmp(conn, ¶ms->_peer)) {
      prev = ¶ms->node;
      continue;
    }

    if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst) || (atomic_test_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_VOLATILE))) {
      /* Remove subscription */
      params->value = 0U;
      gatt_subscription_remove(conn, prev, params);
    } else {
      update_subscription(conn, params);
      prev = ¶ms->node;
    }
  }
}

static void gatt_mtu_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_exchange_params *params = user_data;

  params->func(conn, err, params);
}
#if defined(CONFIG_BLE_AT_CMD)
int bt_at_gatt_exchange_mtu(struct bt_conn *conn, struct bt_gatt_exchange_params *params, u16_t mtu_size) {
  struct bt_att_exchange_mtu_req *req;
  struct net_buf                 *buf;
  u16_t                           mtu;

  __ASSERT(conn, "invalid parameter\n");
  __ASSERT(params && params->func, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  buf = bt_att_create_pdu(conn, BT_ATT_OP_MTU_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  mtu = mtu_size;

#if defined(CONFIG_BLE_AT_CMD)
  set_mtu_size(mtu);
#endif

  BT_DBG("Client MTU %u", mtu);

  req      = net_buf_add(buf, sizeof(*req));
  req->mtu = sys_cpu_to_le16(mtu);

  return gatt_send(conn, buf, gatt_mtu_rsp, params, NULL);
}
#endif

int bt_gatt_exchange_mtu(struct bt_conn *conn, struct bt_gatt_exchange_params *params) {
  struct bt_att_exchange_mtu_req *req;
  struct net_buf                 *buf;
  u16_t                           mtu;

  __ASSERT(conn, "invalid parameter\n");
  __ASSERT(params && params->func, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  buf = bt_att_create_pdu(conn, BT_ATT_OP_MTU_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  mtu = BT_ATT_MTU;

  BT_DBG("Client MTU %u", mtu);

  req      = net_buf_add(buf, sizeof(*req));
  req->mtu = sys_cpu_to_le16(mtu);

  return gatt_send(conn, buf, gatt_mtu_rsp, params, NULL);
}

static void gatt_discover_next(struct bt_conn *conn, u16_t last_handle, struct bt_gatt_discover_params *params) {
  /* Skip if last_handle is not set */
  if (!last_handle)
    goto discover;

  /* Continue from the last found handle */
  params->start_handle = last_handle;
  if (params->start_handle < UINT16_MAX) {
    params->start_handle++;
  } else {
    goto done;
  }

  /* Stop if over the range or the requests */
  if (params->start_handle > params->end_handle) {
    goto done;
  }

discover:
  /* Discover next range */
#if defined(BFLB_BLE_DISCOVER_ONGOING)
  if (!bt_gatt_discover_continue(conn, params)) {
#else
  if (!bt_gatt_discover(conn, params)) {
#endif
    return;
  }

done:
  params->func(conn, NULL, params);
#if defined(BFLB_BLE_DISCOVER_ONGOING)
  discover_ongoing = BT_GATT_ITER_STOP;
#endif
}

static void gatt_find_type_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  const struct bt_att_find_type_rsp *rsp    = pdu;
  struct bt_gatt_discover_params    *params = user_data;
  u8_t                               i;
  u16_t                              end_handle = 0U, start_handle;

  BT_DBG("err 0x%02x", err);

  if (err) {
    goto done;
  }

  /* Parse attributes found */
  for (i = 0U; length >= sizeof(rsp->list[i]); i++, length -= sizeof(rsp->list[i])) {
    struct bt_gatt_attr        attr = {};
    struct bt_gatt_service_val value;

    start_handle = sys_le16_to_cpu(rsp->list[i].start_handle);
    end_handle   = sys_le16_to_cpu(rsp->list[i].end_handle);

    BT_DBG("start_handle 0x%04x end_handle 0x%04x", start_handle, end_handle);

    if (params->type == BT_GATT_DISCOVER_PRIMARY) {
      attr.uuid = BT_UUID_GATT_PRIMARY;
    } else {
      attr.uuid = BT_UUID_GATT_SECONDARY;
    }

    value.end_handle = end_handle;
    value.uuid       = params->uuid;

    attr.handle    = start_handle;
    attr.user_data = &value;

    if (params->func(conn, &attr, params) == BT_GATT_ITER_STOP) {
#if defined(BFLB_BLE_DISCOVER_ONGOING)
      discover_ongoing = BT_GATT_ITER_STOP;
#endif
      return;
    }
  }

  /* Stop if could not parse the whole PDU */
  if (length > 0) {
    goto done;
  }

  gatt_discover_next(conn, end_handle, params);

  return;
done:
  params->func(conn, NULL, params);
#if defined(BFLB_BLE_DISCOVER_ONGOING)
  discover_ongoing = BT_GATT_ITER_STOP;
#endif
}

static int gatt_find_type(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  struct net_buf              *buf;
  struct bt_att_find_type_req *req;
  struct bt_uuid              *uuid;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_FIND_TYPE_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->start_handle = sys_cpu_to_le16(params->start_handle);
  req->end_handle   = sys_cpu_to_le16(params->end_handle);

  if (params->type == BT_GATT_DISCOVER_PRIMARY) {
    uuid = BT_UUID_GATT_PRIMARY;
  } else {
    uuid = BT_UUID_GATT_SECONDARY;
  }

  req->type = sys_cpu_to_le16(BT_UUID_16(uuid)->val);

  BT_DBG("uuid %s start_handle 0x%04x end_handle 0x%04x", bt_uuid_str(params->uuid), params->start_handle, params->end_handle);

  switch (params->uuid->type) {
  case BT_UUID_TYPE_16:
    net_buf_add_le16(buf, BT_UUID_16(params->uuid)->val);
    break;
  case BT_UUID_TYPE_128:
    net_buf_add_mem(buf, BT_UUID_128(params->uuid)->val, 16);
    break;
  default:
    BT_ERR("Unknown UUID type %u", params->uuid->type);
    net_buf_unref(buf);
    return -EINVAL;
  }

  return gatt_send(conn, buf, gatt_find_type_rsp, params, NULL);
}

static void read_included_uuid_cb(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_discover_params *params = user_data;
  struct bt_gatt_include          value;
  struct bt_gatt_attr            *attr;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_128 u128;
  } u;

  if (length != 16U) {
    BT_ERR("Invalid data len %u", length);
    params->func(conn, NULL, params);
    return;
  }

  value.start_handle = params->_included.start_handle;
  value.end_handle   = params->_included.end_handle;
  value.uuid         = &u.uuid;
  u.uuid.type        = BT_UUID_TYPE_128;
  memcpy(u.u128.val, pdu, length);

  BT_DBG("handle 0x%04x uuid %s start_handle 0x%04x "
         "end_handle 0x%04x\n",
         params->_included.attr_handle, bt_uuid_str(&u.uuid), value.start_handle, value.end_handle);

  /* Skip if UUID is set but doesn't match */
  if (params->uuid && bt_uuid_cmp(&u.uuid, params->uuid)) {
    goto next;
  }

  attr         = (&(struct bt_gatt_attr){
              .uuid      = BT_UUID_GATT_INCLUDE,
              .user_data = &value,
  });
  attr->handle = params->_included.attr_handle;

  if (params->func(conn, attr, params) == BT_GATT_ITER_STOP) {
    return;
  }
next:
  gatt_discover_next(conn, params->start_handle, params);

  return;
}

static int read_included_uuid(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  struct net_buf         *buf;
  struct bt_att_read_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(params->_included.start_handle);

  BT_DBG("handle 0x%04x", params->_included.start_handle);

  return gatt_send(conn, buf, read_included_uuid_cb, params, NULL);
}

static u16_t parse_include(struct bt_conn *conn, const void *pdu, struct bt_gatt_discover_params *params, u16_t length) {
  const struct bt_att_read_type_rsp *rsp    = pdu;
  u16_t                              handle = 0U;
  struct bt_gatt_include             value;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;

  /* Data can be either in UUID16 or UUID128 */
  switch (rsp->len) {
  case 8: /* UUID16 */
    u.uuid.type = BT_UUID_TYPE_16;
    break;
  case 6: /* UUID128 */
    /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] page 550
     * To get the included service UUID when the included service
     * uses a 128-bit UUID, the Read Request is used.
     */
    u.uuid.type = BT_UUID_TYPE_128;
    break;
  default:
    BT_ERR("Invalid data len %u", rsp->len);
    goto done;
  }

  /* Parse include found */
  for (length--, pdu = rsp->data; length >= rsp->len; length -= rsp->len, pdu = (const u8_t *)pdu + rsp->len) {
    struct bt_gatt_attr      *attr;
    const struct bt_att_data *data = pdu;
    struct gatt_incl         *incl = (void *)data->value;

    handle = sys_le16_to_cpu(data->handle);
    /* Handle 0 is invalid */
    if (!handle) {
      goto done;
    }

    /* Convert include data, bt_gatt_incl and gatt_incl
     * have different formats so the conversion have to be done
     * field by field.
     */
    value.start_handle = sys_le16_to_cpu(incl->start_handle);
    value.end_handle   = sys_le16_to_cpu(incl->end_handle);

    switch (u.uuid.type) {
    case BT_UUID_TYPE_16:
      value.uuid = &u.uuid;
      u.u16.val  = sys_le16_to_cpu(incl->uuid16);
      break;
    case BT_UUID_TYPE_128:
      params->_included.attr_handle  = handle;
      params->_included.start_handle = value.start_handle;
      params->_included.end_handle   = value.end_handle;

      return read_included_uuid(conn, params);
    }

    BT_DBG("handle 0x%04x uuid %s start_handle 0x%04x "
           "end_handle 0x%04x\n",
           handle, bt_uuid_str(&u.uuid), value.start_handle, value.end_handle);

    /* Skip if UUID is set but doesn't match */
    if (params->uuid && bt_uuid_cmp(&u.uuid, params->uuid)) {
      continue;
    }

    attr         = (&(struct bt_gatt_attr){
                .uuid      = BT_UUID_GATT_INCLUDE,
                .user_data = &value,
    });
    attr->handle = handle;

    if (params->func(conn, attr, params) == BT_GATT_ITER_STOP) {
      return 0;
    }
  }

  /* Whole PDU read without error */
  if (length == 0U && handle) {
    return handle;
  }

done:
  params->func(conn, NULL, params);
  return 0;
}

#define BT_GATT_CHRC(_uuid, _handle, _props)                                                                                                                                                           \
  BT_GATT_ATTRIBUTE(BT_UUID_GATT_CHRC, BT_GATT_PERM_READ, bt_gatt_attr_read_chrc, NULL,                                                                                                                \
                    (&(struct bt_gatt_chrc){                                                                                                                                                           \
                        .uuid         = _uuid,                                                                                                                                                         \
                        .value_handle = _handle,                                                                                                                                                       \
                        .properties   = _props,                                                                                                                                                        \
                    }))

static u16_t parse_characteristic(struct bt_conn *conn, const void *pdu, struct bt_gatt_discover_params *params, u16_t length) {
  const struct bt_att_read_type_rsp *rsp    = pdu;
  u16_t                              handle = 0U;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;

  /* Data can be either in UUID16 or UUID128 */
  switch (rsp->len) {
  case 7: /* UUID16 */
    u.uuid.type = BT_UUID_TYPE_16;
    break;
  case 21: /* UUID128 */
    u.uuid.type = BT_UUID_TYPE_128;
    break;
  default:
    BT_ERR("Invalid data len %u", rsp->len);
    goto done;
  }

  /* Parse characteristics found */
  for (length--, pdu = rsp->data; length >= rsp->len; length -= rsp->len, pdu = (const u8_t *)pdu + rsp->len) {
    struct bt_gatt_attr      *attr;
    const struct bt_att_data *data = pdu;
    struct gatt_chrc         *chrc = (void *)data->value;

    handle = sys_le16_to_cpu(data->handle);
    /* Handle 0 is invalid */
    if (!handle) {
      goto done;
    }

    switch (u.uuid.type) {
    case BT_UUID_TYPE_16:
      u.u16.val = sys_le16_to_cpu(chrc->uuid16);
      break;
    case BT_UUID_TYPE_128:
      memcpy(u.u128.val, chrc->uuid, sizeof(chrc->uuid));
      break;
    }

    BT_DBG("handle 0x%04x uuid %s properties 0x%02x", handle, bt_uuid_str(&u.uuid), chrc->properties);

#if defined(CONFIG_BT_STACK_PTS)
    if (event_flag != gatt_discover_chara) {
      /* Skip if UUID is set but doesn't match */
      if (params->uuid && bt_uuid_cmp(&u.uuid, params->uuid))
        continue;
    }
#else
    /* Skip if UUID is set but doesn't match */
    if (params->uuid && bt_uuid_cmp(&u.uuid, params->uuid)) {
      continue;
    }
#endif

    attr         = (&(struct bt_gatt_attr)BT_GATT_CHRC(&u.uuid, chrc->value_handle, chrc->properties));
    attr->handle = handle;

    if (params->func(conn, attr, params) == BT_GATT_ITER_STOP) {
      return 0;
    }
  }

  /* Whole PDU read without error */
  if (length == 0U && handle) {
    return handle;
  }

done:
  params->func(conn, NULL, params);
  return 0;
}

static void gatt_read_type_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_discover_params *params = user_data;
  u16_t                           handle;

  BT_DBG("err 0x%02x", err);

  if (err) {
    params->func(conn, NULL, params);
#if defined(BFLB_BLE_DISCOVER_ONGOING)
    discover_ongoing = BT_GATT_ITER_STOP;
#endif
    return;
  }

  if (params->type == BT_GATT_DISCOVER_INCLUDE) {
    handle = parse_include(conn, pdu, params, length);
  } else {
    handle = parse_characteristic(conn, pdu, params, length);
  }

  if (!handle) {
#if defined(BFLB_BLE_DISCOVER_ONGOING)
    discover_ongoing = BT_GATT_ITER_STOP;
#endif
    return;
  }

  gatt_discover_next(conn, handle, params);
}

static int gatt_read_type(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  struct net_buf              *buf;
  struct bt_att_read_type_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_TYPE_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->start_handle = sys_cpu_to_le16(params->start_handle);
  req->end_handle   = sys_cpu_to_le16(params->end_handle);

  if (params->type == BT_GATT_DISCOVER_INCLUDE) {
    net_buf_add_le16(buf, BT_UUID_16(BT_UUID_GATT_INCLUDE)->val);
  } else {
    net_buf_add_le16(buf, BT_UUID_16(BT_UUID_GATT_CHRC)->val);
  }

  BT_DBG("start_handle 0x%04x end_handle 0x%04x", params->start_handle, params->end_handle);

  return gatt_send(conn, buf, gatt_read_type_rsp, params, NULL);
}

static u16_t parse_service(struct bt_conn *conn, const void *pdu, struct bt_gatt_discover_params *params, u16_t length) {
  const struct bt_att_read_group_rsp *rsp = pdu;
  u16_t                               start_handle, end_handle = 0U;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;

  /* Data can be either in UUID16 or UUID128 */
  switch (rsp->len) {
  case 6: /* UUID16 */
    u.uuid.type = BT_UUID_TYPE_16;
    break;
  case 20: /* UUID128 */
    u.uuid.type = BT_UUID_TYPE_128;
    break;
  default:
    BT_ERR("Invalid data len %u", rsp->len);
    goto done;
  }

  /* Parse services found */
  for (length--, pdu = rsp->data; length >= rsp->len; length -= rsp->len, pdu = (const u8_t *)pdu + rsp->len) {
    struct bt_gatt_attr             attr = {};
    struct bt_gatt_service_val      value;
    const struct bt_att_group_data *data = pdu;

    start_handle = sys_le16_to_cpu(data->start_handle);
    if (!start_handle) {
      goto done;
    }

    end_handle = sys_le16_to_cpu(data->end_handle);
    if (!end_handle || end_handle < start_handle) {
      goto done;
    }

    switch (u.uuid.type) {
    case BT_UUID_TYPE_16:
      memcpy(&u.u16.val, data->value, sizeof(u.u16.val));
      u.u16.val = sys_le16_to_cpu(u.u16.val);
      break;
    case BT_UUID_TYPE_128:
      memcpy(u.u128.val, data->value, sizeof(u.u128.val));
      break;
    }

    BT_DBG("start_handle 0x%04x end_handle 0x%04x uuid %s", start_handle, end_handle, bt_uuid_str(&u.uuid));

    if (params->type == BT_GATT_DISCOVER_PRIMARY) {
      attr.uuid = BT_UUID_GATT_PRIMARY;
    } else {
      attr.uuid = BT_UUID_GATT_SECONDARY;
    }

    value.end_handle = end_handle;
    value.uuid       = &u.uuid;

    attr.handle    = start_handle;
    attr.user_data = &value;

    if (params->func(conn, &attr, params) == BT_GATT_ITER_STOP) {
      return 0;
    }
  }

  /* Whole PDU read without error */
  if (length == 0U && end_handle) {
    return end_handle;
  }

done:
  params->func(conn, NULL, params);
  return 0;
}

static void gatt_read_group_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_discover_params *params = user_data;
  u16_t                           handle;

  BT_DBG("err 0x%02x", err);

  if (err) {
    params->func(conn, NULL, params);
#if defined(BFLB_BLE_DISCOVER_ONGOING)
    discover_ongoing = BT_GATT_ITER_STOP;
#endif
    return;
  }

  handle = parse_service(conn, pdu, params, length);
  if (!handle) {
#if defined(BFLB_BLE_DISCOVER_ONGOING)
    discover_ongoing = BT_GATT_ITER_STOP;
#endif
    return;
  }

  gatt_discover_next(conn, handle, params);
}

static int gatt_read_group(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  struct net_buf               *buf;
  struct bt_att_read_group_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_GROUP_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->start_handle = sys_cpu_to_le16(params->start_handle);
  req->end_handle   = sys_cpu_to_le16(params->end_handle);

  if (params->type == BT_GATT_DISCOVER_PRIMARY) {
    net_buf_add_le16(buf, BT_UUID_16(BT_UUID_GATT_PRIMARY)->val);
  } else {
    net_buf_add_le16(buf, BT_UUID_16(BT_UUID_GATT_SECONDARY)->val);
  }

  BT_DBG("start_handle 0x%04x end_handle 0x%04x", params->start_handle, params->end_handle);

  return gatt_send(conn, buf, gatt_read_group_rsp, params, NULL);
}

static void gatt_find_info_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  const struct bt_att_find_info_rsp *rsp    = pdu;
  struct bt_gatt_discover_params    *params = user_data;
  u16_t                              handle = 0U;
  u16_t                              len;
  union {
    const struct bt_att_info_16  *i16;
    const struct bt_att_info_128 *i128;
  } info;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_128 u128;
  } u;
  int  i;
  bool skip = false;

  BT_DBG("err 0x%02x", err);

  if (err) {
    goto done;
  }

  /* Data can be either in UUID16 or UUID128 */
  switch (rsp->format) {
  case BT_ATT_INFO_16:
    u.uuid.type = BT_UUID_TYPE_16;
    len         = sizeof(*info.i16);
    break;
  case BT_ATT_INFO_128:
    u.uuid.type = BT_UUID_TYPE_128;
    len         = sizeof(*info.i128);
    break;
  default:
    BT_ERR("Invalid format %u", rsp->format);
    goto done;
  }

  length--;

  /* Check if there is a least one descriptor in the response */
  if (length < len) {
    goto done;
  }

  /* Parse descriptors found */
  for (i = length / len, pdu = rsp->info; i != 0; i--, pdu = (const u8_t *)pdu + len) {
    struct bt_gatt_attr *attr;

    info.i16 = pdu;
    handle   = sys_le16_to_cpu(info.i16->handle);

    if (skip) {
      skip = false;
      continue;
    }

    switch (u.uuid.type) {
    case BT_UUID_TYPE_16:
      u.u16.val = sys_le16_to_cpu(info.i16->uuid);
      break;
    case BT_UUID_TYPE_128:
      memcpy(u.u128.val, info.i128->uuid, 16);
      break;
    }

    BT_DBG("handle 0x%04x uuid %s", handle, bt_uuid_str(&u.uuid));

    /* Skip if UUID is set but doesn't match */
    if (params->uuid && bt_uuid_cmp(&u.uuid, params->uuid)) {
      continue;
    }

    if (params->type == BT_GATT_DISCOVER_DESCRIPTOR) {
      /* Skip attributes that are not considered
       * descriptors.
       */
      if (!bt_uuid_cmp(&u.uuid, BT_UUID_GATT_PRIMARY) || !bt_uuid_cmp(&u.uuid, BT_UUID_GATT_SECONDARY) || !bt_uuid_cmp(&u.uuid, BT_UUID_GATT_INCLUDE)) {
        continue;
      }

      /* If Characteristic Declaration skip ahead as the next
       * entry must be its value.
       */
      if (!bt_uuid_cmp(&u.uuid, BT_UUID_GATT_CHRC)) {
        skip = true;
        continue;
      }
    }

    attr         = (&(struct bt_gatt_attr)BT_GATT_DESCRIPTOR(&u.uuid, 0, NULL, NULL, NULL));
    attr->handle = handle;

    if (params->func(conn, attr, params) == BT_GATT_ITER_STOP) {
#if defined(BFLB_BLE_DISCOVER_ONGOING)
      discover_ongoing = BT_GATT_ITER_STOP;
#endif
      return;
    }
  }

  gatt_discover_next(conn, handle, params);

  return;

done:
  params->func(conn, NULL, params);
#if defined(BFLB_BLE_DISCOVER_ONGOING)
  discover_ongoing = BT_GATT_ITER_STOP;
#endif
}

static int gatt_find_info(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  struct net_buf              *buf;
  struct bt_att_find_info_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_FIND_INFO_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->start_handle = sys_cpu_to_le16(params->start_handle);
  req->end_handle   = sys_cpu_to_le16(params->end_handle);

  BT_DBG("start_handle 0x%04x end_handle 0x%04x", params->start_handle, params->end_handle);

  return gatt_send(conn, buf, gatt_find_info_rsp, params, NULL);
}

int bt_gatt_discover(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(params && params->func, "invalid parameters\n");
  __ASSERT((params->start_handle && params->end_handle), "invalid parameters\n");
  __ASSERT((params->start_handle <= params->end_handle), "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

#if defined(BFLB_BLE_DISCOVER_ONGOING)
  if (discover_ongoing != BT_GATT_ITER_STOP) {
    return -EINPROGRESS;
  }
  discover_ongoing = BT_GATT_ITER_CONTINUE;

  return bt_gatt_discover_continue(conn, params);
}
int bt_gatt_discover_continue(struct bt_conn *conn, struct bt_gatt_discover_params *params) {
#endif
  switch (params->type) {
  case BT_GATT_DISCOVER_PRIMARY:
  case BT_GATT_DISCOVER_SECONDARY:
    if (params->uuid) {
      return gatt_find_type(conn, params);
    }
    return gatt_read_group(conn, params);
  case BT_GATT_DISCOVER_INCLUDE:
  case BT_GATT_DISCOVER_CHARACTERISTIC:
    return gatt_read_type(conn, params);
  case BT_GATT_DISCOVER_DESCRIPTOR:
    /* Only descriptors can be filtered */
    if (params->uuid && (!bt_uuid_cmp(params->uuid, BT_UUID_GATT_PRIMARY) || !bt_uuid_cmp(params->uuid, BT_UUID_GATT_SECONDARY) || !bt_uuid_cmp(params->uuid, BT_UUID_GATT_INCLUDE) ||
                         !bt_uuid_cmp(params->uuid, BT_UUID_GATT_CHRC))) {
      return -EINVAL;
    }

#if defined(BFLB_BLE)
    __attribute__((fallthrough));
#endif

    /* Fallthrough. */
  case BT_GATT_DISCOVER_ATTRIBUTE:
    return gatt_find_info(conn, params);
  default:
    BT_ERR("Invalid discovery type: %u", params->type);
  }

  return -EINVAL;
}

static void parse_read_by_uuid(struct bt_conn *conn, struct bt_gatt_read_params *params, const void *pdu, u16_t length) {
  const struct bt_att_read_type_rsp *rsp = pdu;

  /* Parse values found */
  for (length--, pdu = rsp->data; length; length -= rsp->len, pdu = (const u8_t *)pdu + rsp->len) {
    const struct bt_att_data *data = pdu;
    u16_t                     handle;
    u16_t                     len;

    handle = sys_le16_to_cpu(data->handle);

    /* Handle 0 is invalid */
    if (!handle) {
      BT_ERR("Invalid handle");
      return;
    }

    len = rsp->len > length ? length - 2 : rsp->len - 2;

    BT_DBG("handle 0x%04x len %u value %u", handle, rsp->len, len);

    /* Update start_handle */
    params->by_uuid.start_handle = handle;

    if (params->func(conn, 0, params, data->value, len) == BT_GATT_ITER_STOP) {
      return;
    }

    /* Check if long attribute */
    if (rsp->len > length) {
      break;
    }

    /* Stop if it's the last handle to be read */
    if (params->by_uuid.start_handle == params->by_uuid.end_handle) {
      params->func(conn, 0, params, NULL, 0);
      return;
    }

    params->by_uuid.start_handle++;
  }

  /* Continue reading the attributes */
  if (bt_gatt_read(conn, params) < 0) {
    params->func(conn, BT_ATT_ERR_UNLIKELY, params, NULL, 0);
  }
}

static void gatt_read_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_read_params *params = user_data;

  BT_DBG("err 0x%02x", err);

  if (err || !length) {
    params->func(conn, err, params, NULL, 0);
    return;
  }

  if (!params->handle_count) {
    parse_read_by_uuid(conn, params, pdu, length);
    return;
  }

  if (params->func(conn, 0, params, pdu, length) == BT_GATT_ITER_STOP) {
    return;
  }

  /*
   * Core Spec 4.2, Vol. 3, Part G, 4.8.1
   * If the Characteristic Value is greater than (ATT_MTU - 1) octets
   * in length, the Read Long Characteristic Value procedure may be used
   * if the rest of the Characteristic Value is required.
   */
  if (length < (bt_att_get_mtu(conn) - 1)) {
    params->func(conn, 0, params, NULL, 0);
    return;
  }

  params->single.offset += length;

  /* Continue reading the attribute */
  if (bt_gatt_read(conn, params) < 0) {
    params->func(conn, BT_ATT_ERR_UNLIKELY, params, NULL, 0);
  }
}

static int gatt_read_blob(struct bt_conn *conn, struct bt_gatt_read_params *params) {
  struct net_buf              *buf;
  struct bt_att_read_blob_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_BLOB_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(params->single.handle);
  req->offset = sys_cpu_to_le16(params->single.offset);

  BT_DBG("handle 0x%04x offset 0x%04x", params->single.handle, params->single.offset);

  return gatt_send(conn, buf, gatt_read_rsp, params, NULL);
}

static int gatt_read_uuid(struct bt_conn *conn, struct bt_gatt_read_params *params) {
  struct net_buf              *buf;
  struct bt_att_read_type_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_TYPE_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->start_handle = sys_cpu_to_le16(params->by_uuid.start_handle);
  req->end_handle   = sys_cpu_to_le16(params->by_uuid.end_handle);

  if (params->by_uuid.uuid->type == BT_UUID_TYPE_16) {
    net_buf_add_le16(buf, BT_UUID_16(params->by_uuid.uuid)->val);
  } else {
    net_buf_add_mem(buf, BT_UUID_128(params->by_uuid.uuid)->val, 16);
  }

  BT_DBG("start_handle 0x%04x end_handle 0x%04x uuid %s", params->by_uuid.start_handle, params->by_uuid.end_handle, bt_uuid_str(params->by_uuid.uuid));

  return gatt_send(conn, buf, gatt_read_rsp, params, NULL);
}

#if defined(CONFIG_BT_GATT_READ_MULTIPLE)
static void gatt_read_multiple_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_read_params *params = user_data;

  BT_DBG("err 0x%02x", err);

  if (err || !length) {
    params->func(conn, err, params, NULL, 0);
    return;
  }

  params->func(conn, 0, params, pdu, length);

  /* mark read as complete since read multiple is single response */
  params->func(conn, 0, params, NULL, 0);
}

static int gatt_read_multiple(struct bt_conn *conn, struct bt_gatt_read_params *params) {
  struct net_buf *buf;
  u8_t            i;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_MULT_REQ, params->handle_count * sizeof(u16_t));
  if (!buf) {
    return -ENOMEM;
  }

  for (i = 0U; i < params->handle_count; i++) {
    net_buf_add_le16(buf, params->handles[i]);
  }

  return gatt_send(conn, buf, gatt_read_multiple_rsp, params, NULL);
}
#else
static int gatt_read_multiple(struct bt_conn *conn, struct bt_gatt_read_params *params) { return -ENOTSUP; }
#endif /* CONFIG_BT_GATT_READ_MULTIPLE */

int bt_gatt_read(struct bt_conn *conn, struct bt_gatt_read_params *params) {
  struct net_buf         *buf;
  struct bt_att_read_req *req;

  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(params && params->func, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  if (params->handle_count == 0) {
    return gatt_read_uuid(conn, params);
  }

  if (params->handle_count > 1) {
    return gatt_read_multiple(conn, params);
  }

  if (params->single.offset) {
    return gatt_read_blob(conn, params);
  }

  buf = bt_att_create_pdu(conn, BT_ATT_OP_READ_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(params->single.handle);

  BT_DBG("handle 0x%04x", params->single.handle);

  return gatt_send(conn, buf, gatt_read_rsp, params, NULL);
}

static void gatt_write_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_write_params *params = user_data;

  BT_DBG("err 0x%02x", err);

  params->func(conn, err, params);
}

int bt_gatt_write_without_response_cb(struct bt_conn *conn, u16_t handle, const void *data, u16_t length, bool sign, bt_gatt_complete_func_t func, void *user_data) {
  struct net_buf          *buf;
  struct bt_att_write_cmd *cmd;

  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(handle, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

#if defined(CONFIG_BT_SMP)
  if (conn->encrypt) {
    /* Don't need to sign if already encrypted */
    sign = false;
  }
#endif

  if (sign) {
    buf = bt_att_create_pdu(conn, BT_ATT_OP_SIGNED_WRITE_CMD, sizeof(*cmd) + length + 12);
  } else {
    buf = bt_att_create_pdu(conn, BT_ATT_OP_WRITE_CMD, sizeof(*cmd) + length);
  }
  if (!buf) {
    return -ENOMEM;
  }

  cmd         = net_buf_add(buf, sizeof(*cmd));
  cmd->handle = sys_cpu_to_le16(handle);
  memcpy(cmd->value, data, length);
  net_buf_add(buf, length);

  BT_DBG("handle 0x%04x length %u", handle, length);

  return bt_att_send(conn, buf, func, user_data);
}

static int gatt_exec_write(struct bt_conn *conn, struct bt_gatt_write_params *params) {
  struct net_buf               *buf;
  struct bt_att_exec_write_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_EXEC_WRITE_REQ, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req = net_buf_add(buf, sizeof(*req));
#if defined(CONFIG_BT_STACK_PTS)
  if (event_flag == gatt_cancel_write_req)
    req->flags = BT_ATT_FLAG_CANCEL;
  else
    req->flags = BT_ATT_FLAG_EXEC;
#else
  req->flags = BT_ATT_FLAG_EXEC;
#endif

  BT_DBG("");

  return gatt_send(conn, buf, gatt_write_rsp, params, NULL);
}

static void gatt_prepare_write_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_write_params *params = user_data;

  BT_DBG("err 0x%02x", err);

  /* Don't continue in case of error */
  if (err) {
    params->func(conn, err, params);
    return;
  }
  /* If there is no more data execute */
  if (!params->length) {
    gatt_exec_write(conn, params);
    return;
  }

  /* Write next chunk */
  bt_gatt_write(conn, params);
}

static int gatt_prepare_write(struct bt_conn *conn, struct bt_gatt_write_params *params)

{
  struct net_buf                  *buf;
  struct bt_att_prepare_write_req *req;
  u16_t                            len;

  len = MIN(params->length, bt_att_get_mtu(conn) - sizeof(*req) - 1);

  buf = bt_att_create_pdu(conn, BT_ATT_OP_PREPARE_WRITE_REQ, sizeof(*req) + len);
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(params->handle);
  req->offset = sys_cpu_to_le16(params->offset);
  memcpy(req->value, params->data, len);
  net_buf_add(buf, len);

  /* Update params */
  params->offset += len;
  params->data = (const u8_t *)params->data + len;
  params->length -= len;

  BT_DBG("handle 0x%04x offset %u len %u", params->handle, params->offset, params->length);

  return gatt_send(conn, buf, gatt_prepare_write_rsp, params, NULL);
}

#if defined(CONFIG_BT_STACK_PTS)
int bt_gatt_prepare_write(struct bt_conn *conn, struct bt_gatt_write_params *params) { return gatt_prepare_write(conn, params); }
#endif

int bt_gatt_write(struct bt_conn *conn, struct bt_gatt_write_params *params) {
  struct net_buf          *buf;
  struct bt_att_write_req *req;

  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(params && params->func, "invalid parameters\n");
  __ASSERT(params->handle, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  /* Use Prepare Write if offset is set or Long Write is required */
  if (params->offset || params->length > (bt_att_get_mtu(conn) - sizeof(*req) - 1)) {
    return gatt_prepare_write(conn, params);
  }

  buf = bt_att_create_pdu(conn, BT_ATT_OP_WRITE_REQ, sizeof(*req) + params->length);
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(params->handle);
  memcpy(req->value, params->data, params->length);
  net_buf_add(buf, params->length);

  BT_DBG("handle 0x%04x length %u", params->handle, params->length);

  return gatt_send(conn, buf, gatt_write_rsp, params, NULL);
}

static void gatt_subscription_add(struct bt_conn *conn, struct bt_gatt_subscribe_params *params) {
  bt_addr_le_copy(¶ms->_peer, &conn->le.dst);

  /* Prepend subscription */
  sys_slist_prepend(&subscriptions, ¶ms->node);
}

static void gatt_write_ccc_rsp(struct bt_conn *conn, u8_t err, const void *pdu, u16_t length, void *user_data) {
  struct bt_gatt_subscribe_params *params = user_data;

  BT_DBG("err 0x%02x", err);

  atomic_clear_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_WRITE_PENDING);

  /* if write to CCC failed we remove subscription and notify app */
  if (err) {
    sys_snode_t *node, *tmp, *prev = NULL;
    UNUSED(prev);

    SYS_SLIST_FOR_EACH_NODE_SAFE(&subscriptions, node, tmp) {
      if (node == ¶ms->node) {
        gatt_subscription_remove(conn, tmp, params);
        break;
      }

      prev = node;
    }
  } else if (!params->value) {
    /* Notify with NULL data to complete unsubscribe */
    params->notify(conn, params, NULL, 0);
  }
#if defined(BFLB_BLE_PATCH_NOTIFY_WRITE_CCC_RSP)
  else {
    params->notify(conn, params, NULL, 0);
  }
#endif
}

static int gatt_write_ccc(struct bt_conn *conn, u16_t handle, u16_t value, bt_att_func_t func, struct bt_gatt_subscribe_params *params) {
  struct net_buf          *buf;
  struct bt_att_write_req *req;

  buf = bt_att_create_pdu(conn, BT_ATT_OP_WRITE_REQ, sizeof(*req) + sizeof(u16_t));
  if (!buf) {
    return -ENOMEM;
  }

  req         = net_buf_add(buf, sizeof(*req));
  req->handle = sys_cpu_to_le16(handle);
  net_buf_add_le16(buf, value);

  BT_DBG("handle 0x%04x value 0x%04x", handle, value);

  atomic_set_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_WRITE_PENDING);

  return gatt_send(conn, buf, func, params, NULL);
}

int bt_gatt_subscribe(struct bt_conn *conn, struct bt_gatt_subscribe_params *params) {
  struct bt_gatt_subscribe_params *tmp;
  bool                             has_subscription = false;

  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(params && params->notify, "invalid parameters\n");
  __ASSERT(params->value, "invalid parameters\n");
  __ASSERT(params->ccc_handle, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  /* Lookup existing subscriptions */
  SYS_SLIST_FOR_EACH_CONTAINER(&subscriptions, tmp, node) {
    /* Fail if entry already exists */
    if (tmp == params) {
      return -EALREADY;
    }

    /* Check if another subscription exists */
    if (!bt_conn_addr_le_cmp(conn, &tmp->_peer) && tmp->value_handle == params->value_handle && tmp->value >= params->value) {
      has_subscription = true;
    }
  }

  /* Skip write if already subscribed */
  if (!has_subscription) {
    int err;

    err = gatt_write_ccc(conn, params->ccc_handle, params->value, gatt_write_ccc_rsp, params);
    if (err) {
      return err;
    }
  }

  /*
   * Add subscription before write complete as some implementation were
   * reported to send notification before reply to CCC write.
   */
  gatt_subscription_add(conn, params);

  return 0;
}

int bt_gatt_unsubscribe(struct bt_conn *conn, struct bt_gatt_subscribe_params *params) {
  struct bt_gatt_subscribe_params *tmp, *next;
  bool                             has_subscription = false, found = false;
  sys_snode_t                     *prev = NULL;

  __ASSERT(conn, "invalid parameters\n");
  __ASSERT(params, "invalid parameters\n");

  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  /* Lookup existing subscriptions */
  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&subscriptions, tmp, next, node) {
    /* Remove subscription */
    if (params == tmp) {
      found = true;
      sys_slist_remove(&subscriptions, prev, &tmp->node);
      /* Attempt to cancel if write is pending */
      if (atomic_test_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_WRITE_PENDING)) {
        bt_gatt_cancel(conn, params);
      }
      continue;
    } else {
      prev = &tmp->node;
    }

    /* Check if there still remains any other subscription */
    if (!bt_conn_addr_le_cmp(conn, &tmp->_peer) && tmp->value_handle == params->value_handle) {
      has_subscription = true;
    }
  }

  if (!found) {
    return -EINVAL;
  }

  if (has_subscription) {
    /* Notify with NULL data to complete unsubscribe */
    params->notify(conn, params, NULL, 0);
    return 0;
  }

  params->value = 0x0000;

  return gatt_write_ccc(conn, params->ccc_handle, params->value, gatt_write_ccc_rsp, params);
}

void bt_gatt_cancel(struct bt_conn *conn, void *params) { bt_att_req_cancel(conn, params); }

static void add_subscriptions(struct bt_conn *conn) {
  struct bt_gatt_subscribe_params *params;

  /* Lookup existing subscriptions */
  SYS_SLIST_FOR_EACH_CONTAINER(&subscriptions, params, node) {
    if (bt_conn_addr_le_cmp(conn, ¶ms->_peer)) {
      continue;
    }

    /* Force write to CCC to workaround devices that don't track
     * it properly.
     */
    gatt_write_ccc(conn, params->ccc_handle, params->value, gatt_write_ccc_rsp, params);
  }
}

#endif /* CONFIG_BT_GATT_CLIENT */

#define CCC_STORE_MAX 48

static struct bt_gatt_ccc_cfg *ccc_find_cfg(struct _bt_gatt_ccc *ccc, const bt_addr_le_t *addr, u8_t id) {
  for (size_t i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
    if (id == ccc->cfg[i].id && !bt_addr_le_cmp(&ccc->cfg[i].peer, addr)) {
      return &ccc->cfg[i];
    }
  }

  return NULL;
}

struct addr_with_id {
  const bt_addr_le_t *addr;
  u8_t                id;
};

struct ccc_load {
  struct addr_with_id addr_with_id;
  struct ccc_store   *entry;
  size_t              count;
};

static void ccc_clear(struct _bt_gatt_ccc *ccc, const bt_addr_le_t *addr, u8_t id) {
  struct bt_gatt_ccc_cfg *cfg;

  cfg = ccc_find_cfg(ccc, addr, id);
  if (!cfg) {
    BT_DBG("Unable to clear CCC: cfg not found");
    return;
  }

  clear_ccc_cfg(cfg);
}

static u8_t ccc_load(const struct bt_gatt_attr *attr, void *user_data) {
  struct ccc_load        *load = user_data;
  struct _bt_gatt_ccc    *ccc;
  struct bt_gatt_ccc_cfg *cfg;

  /* Check if attribute is a CCC */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  /* Clear if value was invalidated */
  if (!load->entry) {
    ccc_clear(ccc, load->addr_with_id.addr, load->addr_with_id.id);
    return BT_GATT_ITER_CONTINUE;
  } else if (!load->count) {
    return BT_GATT_ITER_STOP;
  }

  /* Skip if value is not for the given attribute */
  if (load->entry->handle != attr->handle) {
    /* If attribute handle is bigger then it means
     * the attribute no longer exists and cannot
     * be restored.
     */
    if (load->entry->handle < attr->handle) {
      BT_DBG("Unable to restore CCC: handle 0x%04x cannot be"
             " found",
             load->entry->handle);
      goto next;
    }
    return BT_GATT_ITER_CONTINUE;
  }

  BT_DBG("Restoring CCC: handle 0x%04x value 0x%04x", load->entry->handle, load->entry->value);

  cfg = ccc_find_cfg(ccc, load->addr_with_id.addr, load->addr_with_id.id);
  if (!cfg) {
    cfg = ccc_find_cfg(ccc, BT_ADDR_LE_ANY, 0);
    if (!cfg) {
      BT_DBG("Unable to restore CCC: no cfg left");
      goto next;
    }
    bt_addr_le_copy(&cfg->peer, load->addr_with_id.addr);
    cfg->id = load->addr_with_id.id;
  }

  cfg->value = load->entry->value;

next:
  load->entry++;
  load->count--;

  return load->count ? BT_GATT_ITER_CONTINUE : BT_GATT_ITER_STOP;
}

#if defined(BFLB_BLE)
static int ccc_set(const char *key, u8_t id, bt_addr_le_t *addr)
#else
static int ccc_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg)
#endif
{
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    struct ccc_store ccc_store[CCC_STORE_MAX];
    struct ccc_load  load;
#if defined(BFLB_BLE)
    size_t len;
    int    err;
#else
    bt_addr_le_t addr;
    const char  *next;
    int          len, err;
#endif

#if defined(BFLB_BLE)
    err = bt_settings_get_bin(key, (u8_t *)ccc_store, CCC_STORE_MAX, &len);
    if (err)
      return err;

    load.addr_with_id.id   = id;
    load.addr_with_id.addr = addr;
    load.entry             = ccc_store;
    load.count             = len / sizeof(*ccc_store);
#else
    settings_name_next(name, &next);

    if (!name) {
      BT_ERR("Insufficient number of arguments");
      return -EINVAL;
    } else if (!next) {
      load.addr_with_id.id = BT_ID_DEFAULT;
    } else {
      load.addr_with_id.id = strtol(next, NULL, 10);
    }

    err = bt_settings_decode_key(name, &addr);
    if (err) {
      BT_ERR("Unable to decode address %s", log_strdup(name));
      return -EINVAL;
    }

    load.addr_with_id.addr = &addr;

    if (len_rd) {
      len = read_cb(cb_arg, ccc_store, sizeof(ccc_store));

      if (len < 0) {
        BT_ERR("Failed to decode value (err %d)", len);
        return len;
      }

      load.entry = ccc_store;
      load.count = len / sizeof(*ccc_store);

      for (int i = 0; i < load.count; i++) {
        BT_DBG("Read CCC: handle 0x%04x value 0x%04x", ccc_store[i].handle, ccc_store[i].value);
      }
    } else {
      load.entry = NULL;
      load.count = 0;
    }
#endif

    bt_gatt_foreach_attr(0x0001, 0xffff, ccc_load, &load);

    BT_DBG("Restored CCC for id:%x"
           "PRIu8"
           " addr:%s",
           load.addr_with_id.id, bt_addr_le_str(load.addr_with_id.addr));
  }

  return 0;
}

#if !defined(BFLB_BLE)
#if !IS_ENABLED(CONFIG_BT_SETTINGS_CCC_LAZY_LOADING)
/* Only register the ccc_set settings handler when not loading on-demand */
SETTINGS_STATIC_HANDLER_DEFINE(bt_ccc, "bt/ccc", NULL, ccc_set, NULL, NULL);
#endif /* CONFIG_BT_SETTINGS_CCC_LAZY_LOADING */
#endif

#if !defined(BFLB_BLE)
static int ccc_set_direct(const char *key, size_t len, settings_read_cb read_cb, void *cb_arg, void *param) {
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    const char *name;

    BT_DBG("key: %s", log_strdup((const char *)param));

    /* Only "bt/ccc" settings should ever come here */
    if (!settings_name_steq((const char *)param, "bt/ccc", &name)) {
      BT_ERR("Invalid key");
      return -EINVAL;
    }

    return ccc_set(name, len, read_cb, cb_arg);
  }
  return 0;
}
#endif

#if defined(BFLB_BLE)
#if defined(CONFIG_BT_GATT_SERVICE_CHANGED)
#if defined(CONFIG_BT_SETTINGS)
static int sc_set(u8_t id, bt_addr_le_t *addr);
static int sc_commit(void);
#endif
#endif
#endif
void bt_gatt_connected(struct bt_conn *conn) {
  struct conn_data data;

  BT_DBG("conn %p", conn);

  data.conn = conn;
  data.sec  = BT_SECURITY_L1;

  /* Load CCC settings from backend if bonded */
  if (IS_ENABLED(CONFIG_BT_SETTINGS_CCC_LAZY_LOADING) && bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
    char key[BT_SETTINGS_KEY_MAX];

    if (conn->id) {
      char id_str[4];

      u8_to_dec(id_str, sizeof(id_str), conn->id);
      bt_settings_encode_key(key, sizeof(key), "ccc", &conn->le.dst, id_str);
    } else {
      bt_settings_encode_key(key, sizeof(key), "ccc", &conn->le.dst, NULL);
    }
#if defined(BFLB_BLE)
    ccc_set(key, conn->id, &conn->le.dst);
#else
    settings_load_subtree_direct(key, ccc_set_direct, (void *)key);
#endif
  }

  bt_gatt_foreach_attr(0x0001, 0xffff, update_ccc, &data);

  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part C page 2192:
   *
   * 10.3.1.1 Handling of GATT indications and notifications
   *
   * A client requests a server to send indications and notifications
   * by appropriately configuring the server via a Client Characteristic
   * Configuration Descriptor. Since the configuration is persistent
   * across a disconnection and reconnection, security requirements must
   * be checked against the configuration upon a reconnection before
   * sending indications or notifications. When a server reconnects to a
   * client to send an indication or notification for which security is
   * required, the server shall initiate or request encryption with the
   * client prior to sending an indication or notification. If the client
   * does not have an LTK indicating that the client has lost the bond,
   * enabling encryption will fail.
   */
  if (IS_ENABLED(CONFIG_BT_SMP) && bt_conn_get_security(conn) < data.sec) {
    bt_conn_set_security(conn, data.sec);
  }

#if defined(CONFIG_BT_GATT_CLIENT)
  add_subscriptions(conn);
#endif /* CONFIG_BT_GATT_CLIENT */

#if defined(BFLB_BLE)
#if defined(CONFIG_BT_GATT_SERVICE_CHANGED)
#if defined(CONFIG_BT_SETTINGS)
  sc_set(conn->id, &conn->le.dst);
  sc_commit();
#endif
#endif
#endif
}

void bt_gatt_encrypt_change(struct bt_conn *conn) {
  struct conn_data data;

  BT_DBG("conn %p", conn);

  data.conn = conn;
  data.sec  = BT_SECURITY_L1;

  bt_gatt_foreach_attr(0x0001, 0xffff, update_ccc, &data);
}

bool bt_gatt_change_aware(struct bt_conn *conn, bool req) {
#if defined(CONFIG_BT_GATT_CACHING)
  struct gatt_cf_cfg *cfg;

  cfg = find_cf_cfg(conn);
  if (!cfg || !CF_ROBUST_CACHING(cfg)) {
    return true;
  }

  if (atomic_test_bit(cfg->flags, CF_CHANGE_AWARE)) {
    return true;
  }

  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2350:
   * If a change-unaware client sends an ATT command, the server shall
   * ignore it.
   */
  if (!req) {
    return false;
  }

  /* BLUETOOTH CORE SPECIFICATION Version 5.1 | Vol 3, Part G page 2347:
   * 2.5.2.1 Robust Caching
   * A connected client becomes change-aware when...
   * The server sends the client a response with the error code set to
   * Database Out Of Sync and then the server receives another ATT
   * request from the client.
   */
  if (atomic_test_bit(cfg->flags, CF_OUT_OF_SYNC)) {
    atomic_clear_bit(cfg->flags, CF_OUT_OF_SYNC);
    atomic_set_bit(cfg->flags, CF_CHANGE_AWARE);
    BT_DBG("%s change-aware", bt_addr_le_str(&cfg->peer));
    return true;
  }

  atomic_set_bit(cfg->flags, CF_OUT_OF_SYNC);

  return false;
#else
  return true;
#endif
}

static int bt_gatt_store_cf(struct bt_conn *conn) {
#if defined(CONFIG_BT_GATT_CACHING)
  struct gatt_cf_cfg *cfg;
  char                key[BT_SETTINGS_KEY_MAX];
  char               *str;
  size_t              len;
  int                 err;

  cfg = find_cf_cfg(conn);
  if (!cfg) {
    /* No cfg found, just clear it */
    BT_DBG("No config for CF");
    str = NULL;
    len = 0;
  } else {
    str = (char *)cfg->data;
    len = sizeof(cfg->data);

    if (conn->id) {
      char id_str[4];

      u8_to_dec(id_str, sizeof(id_str), conn->id);
      bt_settings_encode_key(key, sizeof(key), "cf", &conn->le.dst, id_str);
    }
  }

  if (!cfg || !conn->id) {
    bt_settings_encode_key(key, sizeof(key), "cf", &conn->le.dst, NULL);
  }

#if defined(BFLB_BLE)
  err = settings_save_one(key, (u8_t *)str, len);
#else
  err = settings_save_one(key, str, len);
#endif
  if (err) {
    BT_ERR("Failed to store Client Features (err %d)", err);
    return err;
  }

  BT_DBG("Stored CF for %s (%s)", bt_addr_le_str(&conn->le.dst), log_strdup(key));
#endif /* CONFIG_BT_GATT_CACHING */
  return 0;
}

void bt_gatt_disconnected(struct bt_conn *conn) {
  BT_DBG("conn %p", conn);
  bt_gatt_foreach_attr(0x0001, 0xffff, disconnected_cb, conn);

#if defined(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE)
  gatt_ccc_conn_unqueue(conn);

  if (gatt_ccc_conn_queue_is_empty()) {
    k_delayed_work_cancel(&gatt_ccc_store.work);
  }
#endif

  if (IS_ENABLED(CONFIG_BT_SETTINGS) && bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
    bt_gatt_store_ccc(conn->id, &conn->le.dst);
    bt_gatt_store_cf(conn);
  }

#if defined(CONFIG_BT_GATT_CLIENT)
  remove_subscriptions(conn);
#endif /* CONFIG_BT_GATT_CLIENT */

#if defined(CONFIG_BT_GATT_CACHING)
  remove_cf_cfg(conn);
#endif
}

#if defined(BFLB_BLE_MTU_CHANGE_CB)
void bt_gatt_mtu_changed(struct bt_conn *conn, u16_t mtu) {
  if (gatt_mtu_changed_cb)
    gatt_mtu_changed_cb(conn, (int)mtu);
}

void bt_gatt_register_mtu_callback(bt_gatt_mtu_changed_cb_t cb) { gatt_mtu_changed_cb = cb; }
#endif

#if defined(CONFIG_BT_SETTINGS)

struct ccc_save {
  struct addr_with_id addr_with_id;
  struct ccc_store    store[CCC_STORE_MAX];
  size_t              count;
};

static u8_t ccc_save(const struct bt_gatt_attr *attr, void *user_data) {
  struct ccc_save        *save = user_data;
  struct _bt_gatt_ccc    *ccc;
  struct bt_gatt_ccc_cfg *cfg;

  /* Check if attribute is a CCC */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  /* Check if there is a cfg for the peer */
  cfg = ccc_find_cfg(ccc, save->addr_with_id.addr, save->addr_with_id.id);
  if (!cfg) {
    return BT_GATT_ITER_CONTINUE;
  }

  BT_DBG("Storing CCCs handle 0x%04x value 0x%04x", attr->handle, cfg->value);

  save->store[save->count].handle = attr->handle;
  save->store[save->count].value  = cfg->value;
  save->count++;

  return BT_GATT_ITER_CONTINUE;
}

int bt_gatt_store_ccc(u8_t id, const bt_addr_le_t *addr) {
  struct ccc_save save;
  char            key[BT_SETTINGS_KEY_MAX];
  size_t          len;
  char           *str;
  int             err;

  save.addr_with_id.addr = addr;
  save.addr_with_id.id   = id;
  save.count             = 0;

  bt_gatt_foreach_attr(0x0001, 0xffff, ccc_save, &save);

  if (id) {
    char id_str[4];

    u8_to_dec(id_str, sizeof(id_str), id);
    bt_settings_encode_key(key, sizeof(key), "ccc", (bt_addr_le_t *)addr, id_str);
  } else {
    bt_settings_encode_key(key, sizeof(key), "ccc", (bt_addr_le_t *)addr, NULL);
  }

  if (save.count) {
    str = (char *)save.store;
    len = save.count * sizeof(*save.store);
  } else {
    /* No entries to encode, just clear */
    str = NULL;
    len = 0;
  }

  err = settings_save_one(key, (const u8_t *)str, len);
  if (err) {
    BT_ERR("Failed to store CCCs (err %d)", err);
    return err;
  }

  BT_DBG("Stored CCCs for %s (%s)", bt_addr_le_str(addr), log_strdup(key));
  if (len) {
    for (int i = 0; i < save.count; i++) {
      BT_DBG("  CCC: handle 0x%04x value 0x%04x", save.store[i].handle, save.store[i].value);
    }
  } else {
    BT_DBG("  CCC: NULL");
  }

  return 0;
}

static u8_t remove_peer_from_attr(const struct bt_gatt_attr *attr, void *user_data) {
  const struct addr_with_id *addr_with_id = user_data;
  struct _bt_gatt_ccc       *ccc;
  struct bt_gatt_ccc_cfg    *cfg;

  /* Check if attribute is a CCC */
  if (attr->write != bt_gatt_attr_write_ccc) {
    return BT_GATT_ITER_CONTINUE;
  }

  ccc = attr->user_data;

  /* Check if there is a cfg for the peer */
  cfg = ccc_find_cfg(ccc, addr_with_id->addr, addr_with_id->id);
  if (cfg) {
    memset(cfg, 0, sizeof(*cfg));
  }

  return BT_GATT_ITER_CONTINUE;
}

static int bt_gatt_clear_ccc(u8_t id, const bt_addr_le_t *addr) {
  char                key[BT_SETTINGS_KEY_MAX];
  struct addr_with_id addr_with_id = {
      .addr = addr,
      .id   = id,
  };

  if (id) {
    char id_str[4];

    u8_to_dec(id_str, sizeof(id_str), id);
    bt_settings_encode_key(key, sizeof(key), "ccc", (bt_addr_le_t *)addr, id_str);
  } else {
    bt_settings_encode_key(key, sizeof(key), "ccc", (bt_addr_le_t *)addr, NULL);
  }

  bt_gatt_foreach_attr(0x0001, 0xffff, remove_peer_from_attr, &addr_with_id);

  return settings_delete(key);
}

#if defined(CONFIG_BT_GATT_CACHING)
static struct gatt_cf_cfg *find_cf_cfg_by_addr(const bt_addr_le_t *addr) {
  int i;

  for (i = 0; i < ARRAY_SIZE(cf_cfg); i++) {
    if (!bt_addr_le_cmp(addr, &cf_cfg[i].peer)) {
      return &cf_cfg[i];
    }
  }

  return NULL;
}
#endif /* CONFIG_BT_GATT_CACHING */

static int bt_gatt_clear_cf(u8_t id, const bt_addr_le_t *addr) {
#if defined(CONFIG_BT_GATT_CACHING)
  char                key[BT_SETTINGS_KEY_MAX];
  struct gatt_cf_cfg *cfg;

  if (id) {
    char id_str[4];

    u8_to_dec(id_str, sizeof(id_str), id);
    bt_settings_encode_key(key, sizeof(key), "cf", (bt_addr_le_t *)addr, id_str);
  } else {
    bt_settings_encode_key(key, sizeof(key), "cf", (bt_addr_le_t *)addr, NULL);
  }

  cfg = find_cf_cfg_by_addr(addr);
  if (cfg) {
    clear_cf_cfg(cfg);
  }

  return settings_delete(key);
#endif /* CONFIG_BT_GATT_CACHING */
  return 0;
}

static int sc_clear_by_addr(u8_t id, const bt_addr_le_t *addr) {
  if (IS_ENABLED(CONFIG_BT_GATT_SERVICE_CHANGED)) {
    struct gatt_sc_cfg *cfg;

    cfg = find_sc_cfg(id, (bt_addr_le_t *)addr);
    if (cfg) {
      sc_clear(cfg);
    }
  }
  return 0;
}

static void bt_gatt_clear_subscriptions(const bt_addr_le_t *addr) {
#if defined(CONFIG_BT_GATT_CLIENT)
  struct bt_gatt_subscribe_params *params, *tmp;
  sys_snode_t                     *prev = NULL;

  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&subscriptions, params, tmp, node) {
    if (bt_addr_le_cmp(addr, ¶ms->_peer)) {
      prev = ¶ms->node;
      continue;
    }
    params->value = 0U;
    gatt_subscription_remove(NULL, prev, params);
  }
#endif /* CONFIG_BT_GATT_CLIENT */
}

int bt_gatt_clear(u8_t id, const bt_addr_le_t *addr) {
  int err;

  err = bt_gatt_clear_ccc(id, addr);
  if (err < 0) {
    return err;
  }

  err = sc_clear_by_addr(id, addr);
  if (err < 0) {
    return err;
  }

  err = bt_gatt_clear_cf(id, addr);
  if (err < 0) {
    return err;
  }

  bt_gatt_clear_subscriptions(addr);

  return 0;
}

#if defined(CONFIG_BT_GATT_SERVICE_CHANGED)
#if defined(BFLB_BLE)
static int sc_set(u8_t id, bt_addr_le_t *addr)
#else
static int sc_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg)
#endif
{
  struct gatt_sc_cfg *cfg;
#if !defined(BFLB_BLE)
  u8_t         id;
  bt_addr_le_t addr;
  int          len, err;
  const char  *next;
#endif

#if defined(BFLB_BLE)
  int  err;
  char key[BT_SETTINGS_KEY_MAX];

  cfg = find_sc_cfg(id, addr);
  if (!cfg) {
    /* Find and initialize a free sc_cfg entry */
    cfg = find_sc_cfg(BT_ID_DEFAULT, BT_ADDR_LE_ANY);
    if (!cfg) {
      BT_ERR("Unable to restore SC: no cfg left");
      return -ENOMEM;
    }

    cfg->id = id;
    bt_addr_le_copy(&cfg->peer, addr);
  }

  if (id) {
    char id_str[4];

    u8_to_dec(id_str, sizeof(id_str), id);
    bt_settings_encode_key(key, sizeof(key), "sc", addr, id_str);
  } else {
    bt_settings_encode_key(key, sizeof(key), "sc", addr, NULL);
  }

  err = bt_settings_get_bin(key, (u8_t *)cfg, sizeof(*cfg), NULL);
  if (err)
    memset(cfg, 0, sizeof(*cfg));
  return err;
#else
  if (!name) {
    BT_ERR("Insufficient number of arguments");
    return -EINVAL;
  }

  err = bt_settings_decode_key(name, &addr);
  if (err) {
    BT_ERR("Unable to decode address %s", log_strdup(name));
    return -EINVAL;
  }

  settings_name_next(name, &next);

  if (!next) {
    id = BT_ID_DEFAULT;
  } else {
    id = strtol(next, NULL, 10);
  }

  cfg = find_sc_cfg(id, &addr);
  if (!cfg && len_rd) {
    /* Find and initialize a free sc_cfg entry */
    cfg = find_sc_cfg(BT_ID_DEFAULT, BT_ADDR_LE_ANY);
    if (!cfg) {
      BT_ERR("Unable to restore SC: no cfg left");
      return -ENOMEM;
    }

    cfg->id = id;
    bt_addr_le_copy(&cfg->peer, &addr);
  }

  if (len_rd) {
    len = read_cb(cb_arg, &cfg->data, sizeof(cfg->data));
    if (len < 0) {
      BT_ERR("Failed to decode value (err %d)", len);
      return len;
    }
    BT_DBG("Read SC: len %d", len);

    BT_DBG("Restored SC for %s", bt_addr_le_str(&addr));
  } else if (cfg) {
    /* Clear configuration */
    memset(cfg, 0, sizeof(*cfg));

    BT_DBG("Removed SC for %s", bt_addr_le_str(&addr));
  }

  return 0;
#endif
}

static int sc_commit(void) {
  atomic_clear_bit(gatt_sc.flags, SC_INDICATE_PENDING);

  if (atomic_test_bit(gatt_sc.flags, SC_RANGE_CHANGED)) {
    /* Schedule SC indication since the range has changed */
    k_delayed_work_submit(&gatt_sc.work, SC_TIMEOUT);
  }

  return 0;
}

#if !defined(BFLB_BLE)
SETTINGS_STATIC_HANDLER_DEFINE(bt_sc, "bt/sc", NULL, sc_set, sc_commit, NULL);
#endif
#endif /* CONFIG_BT_GATT_SERVICE_CHANGED */

#if defined(CONFIG_BT_GATT_CACHING)
static int cf_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) {
  struct gatt_cf_cfg *cfg;
  bt_addr_le_t        addr;
  int                 len, err;

  if (!name) {
    BT_ERR("Insufficient number of arguments");
    return -EINVAL;
  }

  err = bt_settings_decode_key(name, &addr);
  if (err) {
    BT_ERR("Unable to decode address %s", log_strdup(name));
    return -EINVAL;
  }

  cfg = find_cf_cfg_by_addr(&addr);
  if (!cfg) {
    cfg = find_cf_cfg(NULL);
    if (!cfg) {
      BT_ERR("Unable to restore CF: no cfg left");
      return 0;
    }
  }

  if (len_rd) {
    len = read_cb(cb_arg, cfg->data, sizeof(cfg->data));
    if (len < 0) {
      BT_ERR("Failed to decode value (err %d)", len);
      return len;
    }

    BT_DBG("Read CF: len %d", len);
  } else {
    clear_cf_cfg(cfg);
  }

  BT_DBG("Restored CF for %s", bt_addr_le_str(&addr));

  return 0;
}

SETTINGS_STATIC_HANDLER_DEFINE(bt_cf, "bt/cf", NULL, cf_set, NULL, NULL);

static u8_t stored_hash[16];

static int db_hash_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) {
  int len;

  len = read_cb(cb_arg, stored_hash, sizeof(stored_hash));
  if (len < 0) {
    BT_ERR("Failed to decode value (err %d)", len);
    return len;
  }

  BT_HEXDUMP_DBG(stored_hash, sizeof(stored_hash), "Stored Hash: ");

  return 0;
}

static int db_hash_commit(void) {
  /* Stop work and generate the hash */
  if (k_delayed_work_remaining_get(&db_hash_work)) {
    k_delayed_work_cancel(&db_hash_work);
    db_hash_gen(false);
  }

  /* Check if hash matches then skip SC update */
  if (!memcmp(stored_hash, db_hash, sizeof(stored_hash))) {
    BT_DBG("Database Hash matches");
    k_delayed_work_cancel(&gatt_sc.work);
    return 0;
  }

  BT_HEXDUMP_DBG(db_hash, sizeof(db_hash), "New Hash: ");

  /**
   * GATT database has been modified since last boot, likely due to
   * a firmware update or a dynamic service that was not re-registered on
   * boot. Indicate Service Changed to all bonded devices for the full
   * database range to invalidate client-side cache and force discovery on
   * reconnect.
   */
  sc_indicate(0x0001, 0xffff);

  /* Hash did not match overwrite with current hash */
  db_hash_store();

  return 0;
}

SETTINGS_STATIC_HANDLER_DEFINE(bt_hash, "bt/hash", NULL, db_hash_set, db_hash_commit, NULL);
#endif /*CONFIG_BT_GATT_CACHING */
#endif /* CONFIG_BT_SETTINGS */

#if defined(CONFIG_BT_GATT_DYNAMIC_DB)
uint16_t bt_gatt_get_last_handle(void) {
  struct bt_gatt_service *last;
  u16_t                   handle, last_handle;

  if (sys_slist_is_empty(&db)) {
    handle      = last_static_handle;
    last_handle = handle;
    goto last;
  }

  last        = SYS_SLIST_PEEK_TAIL_CONTAINER(&db, last, node);
  handle      = last->attrs[last->attr_count - 1].handle;
  last_handle = handle;
last:
  return last_handle;
}
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/gatt_internal.h
================================================
/** @file
 *  @brief Internal API for Generic Attribute Profile handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#define BT_GATT_CENTRAL_ADDR_RES_NOT_SUPP 0
#define BT_GATT_CENTRAL_ADDR_RES_SUPP     1

#include 

#define BT_GATT_PERM_READ_MASK (BT_GATT_PERM_READ |         \
                                BT_GATT_PERM_READ_ENCRYPT | \
                                BT_GATT_PERM_READ_AUTHEN)
#define BT_GATT_PERM_WRITE_MASK (BT_GATT_PERM_WRITE |         \
                                 BT_GATT_PERM_WRITE_ENCRYPT | \
                                 BT_GATT_PERM_WRITE_AUTHEN)
#define BT_GATT_PERM_ENCRYPT_MASK (BT_GATT_PERM_READ_ENCRYPT | \
                                   BT_GATT_PERM_WRITE_ENCRYPT)
#define BT_GATT_PERM_AUTHEN_MASK (BT_GATT_PERM_READ_AUTHEN | \
                                  BT_GATT_PERM_WRITE_AUTHEN)

void bt_gatt_init(void);
#if defined(BFLB_BLE)
void bt_gatt_deinit(void);
#endif
void bt_gatt_connected(struct bt_conn *conn);
void bt_gatt_encrypt_change(struct bt_conn *conn);
void bt_gatt_disconnected(struct bt_conn *conn);

bool bt_gatt_change_aware(struct bt_conn *conn, bool req);

int bt_gatt_store_ccc(u8_t id, const bt_addr_le_t *addr);

int bt_gatt_clear(u8_t id, const bt_addr_le_t *addr);

#if defined(BFLB_BLE_MTU_CHANGE_CB)
void bt_gatt_mtu_changed(struct bt_conn *conn, u16_t mtu);
#endif

#if defined(CONFIG_BT_GATT_CLIENT)
void bt_gatt_notification(struct bt_conn *conn, u16_t handle,
                          const void *data, u16_t length);
#else
static inline void bt_gatt_notification(struct bt_conn *conn, u16_t handle,
                                        const void *data, u16_t length)
{
}
#endif /* CONFIG_BT_GATT_CLIENT */

struct bt_gatt_attr;

/* Check attribute permission */
u8_t bt_gatt_check_perm(struct bt_conn *conn, const struct bt_gatt_attr *attr,
                        u8_t mask);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hci_core.c
================================================
/* hci_core.c - HCI core Bluetooth handling */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
// #include 

#include 
#include 
#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_CORE)
#include "log.h"

#include "ecc.h"
#include "hci_core.h"
#include "hci_ecc.h"
#include "keys.h"
#include "monitor.h"
#include "rpa.h"

#include "../include/bluetooth/crypto.h"
#include "conn_internal.h"
#include "crypto.h"
#include "gatt_internal.h"
#include "l2cap_internal.h"
#include "settings.h"
#include "smp.h"
#if defined(BFLB_BLE)
#include "bl_hci_wrapper.h"
#include "ble_lib_api.h"
#if defined(BL602)
#include "bl602_hbn.h"
#elif defined(BL702)
#include "bl702_hbn.h"
#elif defined(BL606P) || defined(BL616)
#include "bl606p_hbn.h"
#elif defined(BL808) // no bl808_hbn.h currently, comment it out temporarily
#include "bl808_hbn.h"
#endif
#include "work_q.h"
#endif
#if defined(CONFIG_BLE_MULTI_ADV)
#include "multi_adv.h"
#endif /* CONFIG_BLE_MULTI_ADV */

/* Peripheral timeout to initialize Connection Parameter Update procedure */
#define CONN_UPDATE_TIMEOUT K_SECONDS(CONFIG_BT_CONN_PARAM_UPDATE_TIMEOUT)
#define RPA_TIMEOUT         K_SECONDS(CONFIG_BT_RPA_TIMEOUT)

#define HCI_CMD_TIMEOUT K_SECONDS(10)

extern struct k_fifo   recv_fifo;
extern struct k_work_q g_work_queue_main;
/* Stacks for the threads */
#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
static struct k_thread rx_thread_data;
static K_THREAD_STACK_DEFINE(rx_thread_stack, CONFIG_BT_RX_STACK_SIZE);
#endif
#if (BFLB_BT_CO_THREAD)
struct k_thread co_thread_data;
static void     process_events(struct k_poll_event *ev, int count, int total_evt_array_cnt);
static void     send_cmd(struct net_buf *tx_buf);
#else
static struct k_thread tx_thread_data;
#endif
#if !defined(BFLB_BLE)
static K_THREAD_STACK_DEFINE(tx_thread_stack, CONFIG_BT_HCI_TX_STACK_SIZE);
#endif

static void init_work(struct k_work *work);

struct bt_dev bt_dev = {
    .init = _K_WORK_INITIALIZER(init_work),
/* Give cmd_sem allowing to send first HCI_Reset cmd, the only
 * exception is if the controller requests to wait for an
 * initial Command Complete for NOP.
 */
#if defined(BFLB_BLE)
#if !defined(CONFIG_BT_WAIT_NOP)
    .ncmd_sem = _K_SEM_INITIALIZER(bt_dev.ncmd_sem, 1, 1),
#else
    .ncmd_sem = _K_SEM_INITIALIZER(bt_dev.ncmd_sem, 0, 1),
#endif
    .cmd_tx_queue = _K_FIFO_INITIALIZER(bt_dev.cmd_tx_queue),
#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
    .rx_queue = Z_FIFO_INITIALIZER(bt_dev.rx_queue),
#endif
#else // BFLB_BLE
#if !defined(CONFIG_BT_WAIT_NOP)
    .ncmd_sem = Z_SEM_INITIALIZER(bt_dev.ncmd_sem, 1, 1),
#else
    .ncmd_sem = Z_SEM_INITIALIZER(bt_dev.ncmd_sem, 0, 1),
#endif
    .cmd_tx_queue = Z_FIFO_INITIALIZER(bt_dev.cmd_tx_queue),
#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
    .rx_queue = Z_FIFO_INITIALIZER(bt_dev.rx_queue),
#endif
#endif
};

static bt_ready_cb_t ready_cb;

static bt_le_scan_cb_t *scan_dev_found_cb;

u8_t adv_ch_map = 0x7;

#if defined(CONFIG_BT_HCI_VS_EVT_USER)
static bt_hci_vnd_evt_cb_t *hci_vnd_evt_cb;
#endif /* CONFIG_BT_HCI_VS_EVT_USER */

#if defined(CONFIG_BT_ECC)
static u8_t                  pub_key[64];
static struct bt_pub_key_cb *pub_key_cb;
static bt_dh_key_cb_t        dh_key_cb;
#endif /* CONFIG_BT_ECC */

#if defined(CONFIG_BT_BREDR)
static bt_br_discovery_cb_t   *discovery_cb;
struct bt_br_discovery_result *discovery_results;
static size_t                  discovery_results_size;
static size_t                  discovery_results_count;
#endif /* CONFIG_BT_BREDR */

#if defined(CONFIG_BT_STACK_PTS)
bt_addr_le_t  pts_addr;
volatile u8_t event_flag = 0;
#endif

#if defined(BFLB_HOST_ASSISTANT)
struct blhast_cb *host_assist_cb;
#endif

#if (BFLB_BT_CO_THREAD)
#if defined(CONFIG_BT_CONN)
/* command FIFO + conn_change signal +tx queue + rxqueue + workQueue + MAX_CONN */
#define EV_COUNT (4 + CONFIG_BT_MAX_CONN)
#else
/* command FIFO */
#define EV_COUNT 2
#endif
#else
#if defined(CONFIG_BT_CONN)
/* command FIFO + conn_change signal + MAX_CONN */
#define EV_COUNT (2 + CONFIG_BT_MAX_CONN)
#else
/* command FIFO */
#define EV_COUNT 1
#endif
#endif // BFLB_BT_CO_THREAD

struct cmd_state_set {
  atomic_t *target;
  int       bit;
  bool      val;
};

#if defined(BFLB_RELEASE_CMD_SEM_IF_CONN_DISC)
void hci_release_conn_related_cmd(void);
#endif

void cmd_state_set_init(struct cmd_state_set *state, atomic_t *target, int bit, bool val) {
  state->target = target;
  state->bit    = bit;
  state->val    = val;
}

struct cmd_data {
  /** HCI status of the command completion */
  u8_t status;

  /** The command OpCode that the buffer contains */
  u16_t opcode;

  /** The state to update when command completes with success. */
  struct cmd_state_set *state;
#if (BFLB_BT_CO_THREAD)
  uint8_t sync_state;
#endif
  /** Used by bt_hci_cmd_send_sync. */
  struct k_sem *sync;
};

struct acl_data {
  /** BT_BUF_ACL_IN */
  u8_t type;

  /* Index into the bt_conn storage array */
  u8_t id;

  /** ACL connection handle */
  u16_t handle;
};

#if defined(BFLB_BLE)
extern struct k_sem g_poll_sem;
#endif

__attribute__((section(".tcm_data"))) static struct cmd_data cmd_data[CONFIG_BT_HCI_CMD_COUNT];

#define cmd(buf) (&cmd_data[net_buf_id(buf)])
#define acl(buf) ((struct acl_data *)net_buf_user_data(buf))

/* HCI command buffers. Derive the needed size from BT_BUF_RX_SIZE since
 * the same buffer is also used for the response.
 */
#define CMD_BUF_SIZE BT_BUF_RX_SIZE
#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_HCI_CMD_COUNT, CMD_BUF_SIZE, NULL);

NET_BUF_POOL_FIXED_DEFINE(hci_rx_pool, CONFIG_BT_RX_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#if defined(CONFIG_BT_CONN)
/* Dedicated pool for HCI_Number_of_Completed_Packets. This event is always
 * consumed synchronously by bt_recv_prio() so a single buffer is enough.
 * Having a dedicated pool for it ensures that exhaustion of the RX pool
 * cannot block the delivery of this priority event.
 */
NET_BUF_POOL_FIXED_DEFINE(num_complete_pool, 1, BT_BUF_RX_SIZE, NULL);
#endif /* CONFIG_BT_CONN */

#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
NET_BUF_POOL_FIXED_DEFINE(discardable_pool, CONFIG_BT_DISCARDABLE_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#endif /* CONFIG_BT_DISCARDABLE_BUF_COUNT */
#else
struct net_buf_pool hci_cmd_pool;
struct net_buf_pool hci_rx_pool;
#if defined(CONFIG_BT_CONN)
struct net_buf_pool num_complete_pool;
#endif
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
struct net_buf_pool discardable_pool;
#endif
#endif /*!defined(BFLB_DYNAMIC_ALLOC_MEM)*/

#if defined CONFIG_BT_HFP
extern bool hfp_codec_msbc;
#endif

struct event_handler {
  u8_t event;
  u8_t min_len;
  void (*handler)(struct net_buf *buf);
};

#define EVENT_HANDLER(_evt, _handler, _min_len)                                                                                                                                                        \
  {                                                                                                                                                                                                    \
      .event   = _evt,                                                                                                                                                                                 \
      .handler = _handler,                                                                                                                                                                             \
      .min_len = _min_len,                                                                                                                                                                             \
  }

static inline void handle_event(u8_t event, struct net_buf *buf, const struct event_handler *handlers, size_t num_handlers) {
  size_t i;

  for (i = 0; i < num_handlers; i++) {
    const struct event_handler *handler = &handlers[i];

    if (handler->event != event) {
      continue;
    }

    if (buf->len < handler->min_len) {
      BT_ERR("Too small (%u bytes) event 0x%02x", buf->len, event);
      return;
    }

    handler->handler(buf);
    return;
  }

  BT_WARN("Unhandled event 0x%02x len %u: %s", event, buf->len, bt_hex(buf->data, buf->len));
}

static inline bool is_wl_empty(void) {
#if defined(CONFIG_BT_WHITELIST)
  return !bt_dev.le.wl_entries;
#else
  return true;
#endif /* defined(CONFIG_BT_WHITELIST) */
}

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
static void report_completed_packet(struct net_buf *buf) {
  struct bt_hci_cp_host_num_completed_packets *cp;
  u16_t                                        handle = acl(buf)->handle;
  struct bt_hci_handle_count                  *hc;
  struct bt_conn                              *conn;

  net_buf_destroy(buf);

  /* Do nothing if controller to host flow control is not supported */
  if (!BT_CMD_TEST(bt_dev.supported_commands, 10, 5)) {
    return;
  }

  conn = bt_conn_lookup_id(acl(buf)->id);
  if (!conn) {
    BT_WARN("Unable to look up conn with id 0x%02x", acl(buf)->id);
    return;
  }

  if (conn->state != BT_CONN_CONNECTED && conn->state != BT_CONN_DISCONNECT) {
    BT_WARN("Not reporting packet for non-connected conn");
    bt_conn_unref(conn);
    return;
  }

  bt_conn_unref(conn);

  BT_DBG("Reporting completed packet for handle %u", handle);

  buf = bt_hci_cmd_create(BT_HCI_OP_HOST_NUM_COMPLETED_PACKETS, sizeof(*cp) + sizeof(*hc));
  if (!buf) {
    BT_ERR("Unable to allocate new HCI command");
    return;
  }

  cp              = net_buf_add(buf, sizeof(*cp));
  cp->num_handles = sys_cpu_to_le16(1);

  hc         = net_buf_add(buf, sizeof(*hc));
  hc->handle = sys_cpu_to_le16(handle);
  hc->count  = sys_cpu_to_le16(1);

  bt_hci_cmd_send(BT_HCI_OP_HOST_NUM_COMPLETED_PACKETS, buf);
}

#define ACL_IN_SIZE BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_RX_MTU)
#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
NET_BUF_POOL_DEFINE(acl_in_pool, CONFIG_BT_ACL_RX_COUNT, ACL_IN_SIZE, sizeof(struct acl_data), report_completed_packet);
#else
struct net_buf_pool acl_in_pool;
#endif
#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */

struct net_buf *bt_hci_cmd_create(u16_t opcode, u8_t param_len) {
  struct bt_hci_cmd_hdr *hdr;
  struct net_buf        *buf;

  BT_DBG("opcode 0x%04x param_len %u", opcode, param_len);

  buf = net_buf_alloc(&hci_cmd_pool, K_FOREVER);
  __ASSERT_NO_MSG(buf);

  BT_DBG("buf %p", buf);

  net_buf_reserve(buf, BT_BUF_RESERVE);

  bt_buf_set_type(buf, BT_BUF_CMD);

  cmd(buf)->opcode = opcode;
  cmd(buf)->sync   = NULL;
  cmd(buf)->state  = NULL;

  hdr            = net_buf_add(buf, sizeof(*hdr));
  hdr->opcode    = sys_cpu_to_le16(opcode);
  hdr->param_len = param_len;

  return buf;
}

int bt_hci_cmd_send(u16_t opcode, struct net_buf *buf) {
  if (!buf) {
    buf = bt_hci_cmd_create(opcode, 0);
    if (!buf) {
      return -ENOBUFS;
    }
  }

  BT_DBG("opcode 0x%04x len %u", opcode, buf->len);

  /* Host Number of Completed Packets can ignore the ncmd value
   * and does not generate any cmd complete/status events.
   */
  if (opcode == BT_HCI_OP_HOST_NUM_COMPLETED_PACKETS) {
    int err;

    err = bt_send(buf);
    if (err) {
      BT_ERR("Unable to send to driver (err %d)", err);
      net_buf_unref(buf);
    }

    return err;
  }

  net_buf_put(&bt_dev.cmd_tx_queue, buf);
#if defined(BFLB_BLE)
  k_sem_give(&g_poll_sem);
#endif
  return 0;
}

#if (BFLB_BT_CO_THREAD)
struct k_thread *bt_get_co_thread(void) { return &co_thread_data; }

static void bt_hci_sync_check(struct net_buf *buf) {
  static struct k_poll_event events[EV_COUNT] = {
      [0]            = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &g_work_queue_main.fifo, BT_EVENT_WORK_QUEUE),
      [1]            = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &bt_dev.cmd_tx_queue, BT_EVENT_CMD_TX),
      [EV_COUNT - 1] = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &recv_fifo, BT_EVENT_RX_QUEUE),
  };

  uint32_t time_start = k_uptime_get_32();
  send_cmd(buf);

  while (1) {
    int  ev_count, err;
    u8_t to_process = 0;

    events[0].state            = K_POLL_STATE_NOT_READY;
    events[1].state            = K_POLL_STATE_NOT_READY;
    events[EV_COUNT - 1].state = K_POLL_STATE_NOT_READY;
    ev_count                   = 2;

    if (IS_ENABLED(CONFIG_BT_CONN)) {
      ev_count += bt_conn_prepare_events(&events[2]);
    }
    err = k_poll(events, ev_count, EV_COUNT, K_NO_WAIT, &to_process);
    BT_ASSERT(err == 0);
    if (to_process)
      process_events(events, ev_count, EV_COUNT);

    if ((cmd(buf)->sync_state == BT_CMD_SYNC_TX_DONE) || (k_uptime_get_32() - time_start) >= HCI_CMD_TIMEOUT) {
      break;
    }
  }
}
#endif

#if defined(BFLB_HOST_ASSISTANT)
extern void blhast_bt_reset(void);
uint16_t    hci_cmd_to_cnt = 0;
#endif
int bt_hci_cmd_send_sync(u16_t opcode, struct net_buf *buf, struct net_buf **rsp) {
  struct k_sem sync_sem;
  int          err;
#if (BFLB_BT_CO_THREAD)
  bool is_bt_co_thread = k_is_current_thread(&co_thread_data);
#endif

  if (!buf) {
    buf = bt_hci_cmd_create(opcode, 0);
    if (!buf) {
      return -ENOBUFS;
    }
  }

  BT_DBG("buf %p opcode 0x%04x len %u", buf, opcode, buf->len);

#if (BFLB_BT_CO_THREAD)
  if (is_bt_co_thread) {
    cmd(buf)->sync_state = BT_CMD_SYNC_TX;
    cmd(buf)->sync       = NULL;
  } else {
    k_sem_init(&sync_sem, 0, 1);
    cmd(buf)->sync       = &sync_sem;
    cmd(buf)->sync_state = BT_CMD_SYNC_NONE;
  }
#else
  k_sem_init(&sync_sem, 0, 1);
  cmd(buf)->sync = &sync_sem;
#endif

#if defined(BFLB_BLE)
  /*Assign a initial value to status in order to check if hci cmd timeout*/
  cmd(buf)->status = 0xff;
#endif

  /* Make sure the buffer stays around until the command completes */
  net_buf_ref(buf);

#if (BFLB_BT_CO_THREAD)
  if (is_bt_co_thread)
    bt_hci_sync_check(buf);
  else {
    net_buf_put(&bt_dev.cmd_tx_queue, buf);
#if defined(BFLB_BLE)
    k_sem_give(&g_poll_sem);
#endif
    err = k_sem_take(&sync_sem, HCI_CMD_TIMEOUT);
#ifdef BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
    k_sem_delete(&sync_sem);
#endif
    __ASSERT(err == 0, "k_sem_take failed with err %d", err);
  }
#else
  net_buf_put(&bt_dev.cmd_tx_queue, buf);
#if defined(BFLB_BLE)
  k_sem_give(&g_poll_sem);
#endif
  err = k_sem_take(&sync_sem, HCI_CMD_TIMEOUT);
#ifdef BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
  k_sem_delete(&sync_sem);
#endif
  __ASSERT(err == 0, "k_sem_take failed with err %d", err);
#endif // #if (BFLB_BT_CO_THREAD)

  BT_DBG("opcode 0x%04x status 0x%02x", opcode, cmd(buf)->status);

  if (cmd(buf)->status) {
    switch (cmd(buf)->status) {
    case BT_HCI_ERR_CONN_LIMIT_EXCEEDED:
      err = -ECONNREFUSED;
      break;
#if defined(BFLB_BLE)
    case 0xff:
      err = -ETIME;
      BT_ERR("k_sem_take timeout with opcode 0x%04x", opcode);
#if (defined(BL602) || defined(BL702)) && defined(BFLB_HOST_ASSISTANT)
      BT_ERR("Restart and restore bt");
      hci_cmd_to_cnt++;
      if (cmd(buf)->state) {
        struct cmd_state_set *update = cmd(buf)->state;
        atomic_set_bit_to(update->target, update->bit, update->val);
      }
      blhast_bt_reset();
#else
      BT_ASSERT(err == 0);
#endif
      break;
#endif
    default:
      err = -EIO;
      break;
    }

    net_buf_unref(buf);
  } else {
    err = 0;
    if (rsp) {
      *rsp = buf;
    } else {
      net_buf_unref(buf);
    }
  }

  return err;
}

#if defined(CONFIG_BT_OBSERVER) || defined(CONFIG_BT_CONN)
const bt_addr_le_t *bt_lookup_id_addr(u8_t id, const bt_addr_le_t *addr) {
  if (IS_ENABLED(CONFIG_BT_SMP)) {
    struct bt_keys *keys;

    keys = bt_keys_find_irk(id, addr);
    if (keys) {
      BT_DBG("Identity %s matched RPA %s", bt_addr_le_str(&keys->addr), bt_addr_le_str(addr));
      return &keys->addr;
    }
  }

  return addr;
}
#endif /* CONFIG_BT_OBSERVER || CONFIG_BT_CONN */

static int set_advertise_enable(bool enable) {
  struct net_buf      *buf;
  struct cmd_state_set state;
  int                  err;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_ADV_ENABLE, 1);
  if (!buf) {
    return -ENOBUFS;
  }

  if (enable) {
    net_buf_add_u8(buf, BT_HCI_LE_ADV_ENABLE);
  } else {
    net_buf_add_u8(buf, BT_HCI_LE_ADV_DISABLE);
  }

  cmd_state_set_init(&state, bt_dev.flags, BT_DEV_ADVERTISING, enable);
  cmd(buf)->state = &state;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_ADV_ENABLE, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}

static int set_random_address(const bt_addr_t *addr) {
  struct net_buf *buf;
  int             err;

#if defined(CONFIG_BT_STACK_PTS)
  BT_PTS("set random address %s", bt_addr_str(addr));
#else
  BT_DBG("%s", bt_addr_str(addr));
#endif

  /* Do nothing if we already have the right address */
  if (!bt_addr_cmp(addr, &bt_dev.random_addr.a)) {
    return 0;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_RANDOM_ADDRESS, sizeof(*addr));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, addr, sizeof(*addr));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_RANDOM_ADDRESS, buf, NULL);
  if (err) {
    return err;
  }

  bt_addr_copy(&bt_dev.random_addr.a, addr);
  bt_dev.random_addr.type = BT_ADDR_LE_RANDOM;

  return 0;
}

int bt_addr_from_str(const char *str, bt_addr_t *addr) {
  int  i, j;
  u8_t tmp;

  if (strlen(str) != 17U) {
    return -EINVAL;
  }

  for (i = 5, j = 1; *str != '\0'; str++, j++) {
    if (!(j % 3) && (*str != ':')) {
      return -EINVAL;
    } else if (*str == ':') {
      i--;
      continue;
    }

    addr->val[i] = addr->val[i] << 4;

    if (char2hex(*str, &tmp) < 0) {
      return -EINVAL;
    }

    addr->val[i] |= tmp;
  }

  return 0;
}

int bt_addr_le_from_str(const char *str, const char *type, bt_addr_le_t *addr) {
  int err;

  err = bt_addr_from_str(str, &addr->a);
  if (err < 0) {
    return err;
  }

  if (!strcmp(type, "public") || !strcmp(type, "(public)")) {
    addr->type = BT_ADDR_LE_PUBLIC;
  } else if (!strcmp(type, "random") || !strcmp(type, "(random)")) {
    addr->type = BT_ADDR_LE_RANDOM;
  } else if (!strcmp(type, "public-id") || !strcmp(type, "(public-id)")) {
    addr->type = BT_ADDR_LE_PUBLIC_ID;
  } else if (!strcmp(type, "random-id") || !strcmp(type, "(random-id)")) {
    addr->type = BT_ADDR_LE_RANDOM_ID;
  } else {
    return -EINVAL;
  }

  return 0;
}

#if defined(CONFIG_BT_PRIVACY)
/* this function sets new RPA only if current one is no longer valid */
static int le_set_private_addr(u8_t id) {
  bt_addr_t rpa;
  int       err;

  /* check if RPA is valid */
  if (atomic_test_bit(bt_dev.flags, BT_DEV_RPA_VALID)) {
    return 0;
  }

  err = bt_rpa_create(bt_dev.irk[id], &rpa);
  if (!err) {
    err = set_random_address(&rpa);
    if (!err) {
      atomic_set_bit(bt_dev.flags, BT_DEV_RPA_VALID);
    }
  }

  /* restart timer even if failed to set new RPA */
  k_delayed_work_submit(&bt_dev.rpa_update, RPA_TIMEOUT);

  return err;
}

static void rpa_timeout(struct k_work *work) {
  int err_adv = 0, err_scan = 0;

  BT_DBG("");

  /* Invalidate RPA */
  atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);

  /*
   * we need to update rpa only if advertising is ongoing, with
   * BT_DEV_KEEP_ADVERTISING flag is handled in disconnected event
   */
  if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    /* make sure new address is used */
    set_advertise_enable(false);
    err_adv = le_set_private_addr(bt_dev.adv_id);
    set_advertise_enable(true);
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_ACTIVE_SCAN)) {
    /* TODO do we need to toggle scan? */
    err_scan = le_set_private_addr(BT_ID_DEFAULT);
  }

  /* If both advertising and scanning is active, le_set_private_addr
   * will fail. In this case, set back RPA_VALID so that if either of
   * advertising or scanning was restarted by application then
   * le_set_private_addr in the public API call path will not retry
   * set_random_address. This is needed so as to be able to stop and
   * restart either of the role by the application after rpa_timeout.
   */
  if (err_adv || err_scan) {
    atomic_set_bit(bt_dev.flags, BT_DEV_RPA_VALID);
  }
}

#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
static int le_set_non_resolv_private_addr(u8_t id) {
  bt_addr_t nrpa;
  int       err;

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SETTED_NON_RESOLV_ADDR)) {
    return 0;
  }

  err = bt_rand(nrpa.val, sizeof(nrpa.val));
  if (err) {
    return err;
  }

  nrpa.val[5] &= 0x3f;
  atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);
  return set_random_address(&nrpa);
}

int le_set_non_resolv_private_addr_ext(u8_t id, bt_addr_t *addr) {
  bt_addr_t *nrpa = addr;
  int        err;

  err = bt_rand(nrpa->val, sizeof(nrpa->val));
  if (err) {
    return err;
  }

  nrpa->val[5] &= 0x3f;
  atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);
  return set_random_address(nrpa);
}
#endif

#else
static int le_set_private_addr(u8_t id) {
  bt_addr_t nrpa;
  int       err;

  err = bt_rand(nrpa.val, sizeof(nrpa.val));
  if (err) {
    return err;
  }

  nrpa.val[5] &= 0x3f;

  return set_random_address(&nrpa);
}
#endif

#if defined(CONFIG_BT_OBSERVER)
static int set_le_scan_enable(u8_t enable) {
  struct bt_hci_cp_le_set_scan_enable *cp;
  struct net_buf                      *buf;
  struct cmd_state_set                 state;
  int                                  err;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_SCAN_ENABLE, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  if (enable == BT_HCI_LE_SCAN_ENABLE) {
    cp->filter_dup = atomic_test_bit(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP);
  } else {
    cp->filter_dup = BT_HCI_LE_SCAN_FILTER_DUP_DISABLE;
  }

  cp->enable = enable;

  cmd_state_set_init(&state, bt_dev.flags, BT_DEV_SCANNING, enable == BT_HCI_LE_SCAN_ENABLE);
  cmd(buf)->state = &state;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_SCAN_ENABLE, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}
#endif /* CONFIG_BT_OBSERVER */

#if defined(CONFIG_BT_CONN)
static void hci_acl(struct net_buf *buf) {
  struct bt_hci_acl_hdr *hdr;
  u16_t                  handle, len;
  struct bt_conn        *conn;
  u8_t                   flags;

  BT_DBG("buf %p", buf);

  BT_ASSERT(buf->len >= sizeof(*hdr));

  hdr    = net_buf_pull_mem(buf, sizeof(*hdr));
  len    = sys_le16_to_cpu(hdr->len);
  handle = sys_le16_to_cpu(hdr->handle);
  flags  = bt_acl_flags(handle);

  acl(buf)->handle = bt_acl_handle(handle);
  acl(buf)->id     = BT_CONN_ID_INVALID;

  BT_DBG("handle %u len %u flags %u", acl(buf)->handle, len, flags);

  if (buf->len != len) {
    BT_ERR("ACL data length mismatch (%u != %u)", buf->len, len);
    net_buf_unref(buf);
    return;
  }

  conn = bt_conn_lookup_handle(acl(buf)->handle);
  if (!conn) {
    BT_ERR("Unable to find conn for handle %u", acl(buf)->handle);
    net_buf_unref(buf);
    return;
  }

  acl(buf)->id = bt_conn_index(conn);

  bt_conn_recv(conn, buf, flags);
  bt_conn_unref(conn);
}

static void hci_data_buf_overflow(struct net_buf *buf) {
  struct bt_hci_evt_data_buf_overflow *evt = (void *)buf->data;

  BT_WARN("Data buffer overflow (link type 0x%02x)", evt->link_type);
  // avoid compiler warning if BT_WARN is empty
  (void)evt;
}

static void hci_num_completed_packets(struct net_buf *buf) {
  struct bt_hci_evt_num_completed_packets *evt = (void *)buf->data;
  int                                      i;

  BT_DBG("num_handles %u", evt->num_handles);

  for (i = 0; i < evt->num_handles; i++) {
    u16_t           handle, count;
    struct bt_conn *conn;
    unsigned int    key;

    handle = sys_le16_to_cpu(evt->h[i].handle);
    count  = sys_le16_to_cpu(evt->h[i].count);

    BT_DBG("handle %u count %u", handle, count);

    key = irq_lock();

    conn = bt_conn_lookup_handle(handle);
    if (!conn) {
      irq_unlock(key);
      BT_ERR("No connection for handle %u", handle);
      continue;
    }

    irq_unlock(key);

    while (count--) {
      struct bt_conn_tx *tx;
      sys_snode_t       *node;

      key = irq_lock();

      if (conn->pending_no_cb) {
        conn->pending_no_cb--;
        irq_unlock(key);
        k_sem_give(bt_conn_get_pkts(conn));
        continue;
      }

      node = sys_slist_get(&conn->tx_pending);
      irq_unlock(key);

      if (!node) {
        BT_ERR("packets count mismatch");
        break;
      }

      tx = CONTAINER_OF(node, struct bt_conn_tx, node);

      key                 = irq_lock();
      conn->pending_no_cb = tx->pending_no_cb;
      tx->pending_no_cb   = 0U;
      sys_slist_append(&conn->tx_complete, &tx->node);
      irq_unlock(key);

      k_work_submit(&conn->tx_complete_work);
      k_sem_give(bt_conn_get_pkts(conn));
#if defined(BFLB_BLE)
      k_sem_give(&g_poll_sem);
#endif
    }

    bt_conn_unref(conn);
  }
}

#if defined(CONFIG_BT_CENTRAL)
#if defined(CONFIG_BT_WHITELIST)
int bt_le_auto_conn(const struct bt_le_conn_param *conn_param) {
  struct net_buf                  *buf;
  struct cmd_state_set             state;
  struct bt_hci_cp_le_create_conn *cp;
  u8_t                             own_addr_type;
  int                              err;

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
    err = set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
    if (err) {
      return err;
    }
  }

#if defined(CONFIG_BT_STACK_PTS)
  if (conn_param->own_address_type != BT_ADDR_LE_PUBLIC) {
#endif

    if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
      err = le_set_private_addr(BT_ID_DEFAULT);
      if (err) {
        return err;
      }
      if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
        own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
      } else {
        own_addr_type = BT_ADDR_LE_RANDOM;
      }
    } else {
      const bt_addr_le_t *addr = &bt_dev.id_addr[BT_ID_DEFAULT];

      /* If Static Random address is used as Identity address we
       * need to restore it before creating connection. Otherwise
       * NRPA used for active scan could be used for connection.
       */
      if (addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&addr->a);
        if (err) {
          return err;
        }
      }

      own_addr_type = addr->type;
    }

#if defined(CONFIG_BT_STACK_PTS)
  } else {
    own_addr_type = conn_param->own_address_type;
  }
#endif

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CREATE_CONN, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  (void)memset(cp, 0, sizeof(*cp));

  cp->filter_policy = BT_HCI_LE_CREATE_CONN_FP_WHITELIST;
  cp->own_addr_type = own_addr_type;

  /* User Initiated procedure use fast scan parameters. */
  cp->scan_interval = sys_cpu_to_le16(BT_GAP_SCAN_FAST_INTERVAL);
  cp->scan_window   = sys_cpu_to_le16(BT_GAP_SCAN_FAST_WINDOW);

  cp->conn_interval_min   = sys_cpu_to_le16(conn_param->interval_min);
  cp->conn_interval_max   = sys_cpu_to_le16(conn_param->interval_max);
  cp->conn_latency        = sys_cpu_to_le16(conn_param->latency);
  cp->supervision_timeout = sys_cpu_to_le16(conn_param->timeout);

  cmd_state_set_init(&state, bt_dev.flags, BT_DEV_AUTO_CONN, true);
  cmd(buf)->state = &state;

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CREATE_CONN, buf, NULL);
}

int bt_le_auto_conn_cancel(void) {
  struct net_buf      *buf;
  struct cmd_state_set state;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CREATE_CONN_CANCEL, 0);

  cmd_state_set_init(&state, bt_dev.flags, BT_DEV_AUTO_CONN, false);
  cmd(buf)->state = &state;

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CREATE_CONN_CANCEL, buf, NULL);
}
#endif /* defined(CONFIG_BT_WHITELIST) */

static int hci_le_create_conn(const struct bt_conn *conn) {
  struct net_buf                  *buf;
  struct bt_hci_cp_le_create_conn *cp;
  u8_t                             own_addr_type;
  const bt_addr_le_t              *peer_addr;
  int                              err;

#if defined(CONFIG_BT_STACK_PTS)
  if (conn->le.own_adder_type == BT_ADDR_LE_PUBLIC || conn->le.own_adder_type == BT_ADDR_LE_PUBLIC_ID) {
    own_addr_type = conn->le.own_adder_type;
    goto start_connect;
  }

#endif

  if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
    err = le_set_private_addr(conn->id);
    if (err) {
      return err;
    }
#if defined(BFLB_BLE)
    /*Use random type at the first time*/
    own_addr_type = BT_ADDR_LE_RANDOM;
#if defined(CONFIG_BT_STACK_PTS)
    if (conn->le.own_adder_type == BT_ADDR_LE_RANDOM_ID) {
      own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
    }
#endif
#else
    if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
      own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
    } else {
      own_addr_type = BT_ADDR_LE_RANDOM;
    }
#endif
  } else {
    /* If Static Random address is used as Identity address we
     * need to restore it before creating connection. Otherwise
     * NRPA used for active scan could be used for connection.
     */
    const bt_addr_le_t *own_addr = &bt_dev.id_addr[conn->id];

    if (own_addr->type == BT_ADDR_LE_RANDOM) {
      err = set_random_address(&own_addr->a);
      if (err) {
        return err;
      }
    }

    own_addr_type = own_addr->type;
  }

#if defined(CONFIG_BT_STACK_PTS)
start_connect:
#endif
  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CREATE_CONN, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  (void)memset(cp, 0, sizeof(*cp));

  /* Interval == window for continuous scanning */
  cp->scan_interval = sys_cpu_to_le16(BT_GAP_SCAN_FAST_INTERVAL);
  cp->scan_window   = cp->scan_interval;

  peer_addr = &conn->le.dst;

#if defined(CONFIG_BT_SMP)
  if (!bt_dev.le.rl_size || bt_dev.le.rl_entries > bt_dev.le.rl_size) {
    /* Host resolving is used, use the RPA directly. */
    peer_addr = &conn->le.resp_addr;
  }
#endif

  bt_addr_le_copy(&cp->peer_addr, peer_addr);
  cp->own_addr_type       = own_addr_type;
  cp->conn_interval_min   = sys_cpu_to_le16(conn->le.interval_min);
  cp->conn_interval_max   = sys_cpu_to_le16(conn->le.interval_max);
  cp->conn_latency        = sys_cpu_to_le16(conn->le.latency);
  cp->supervision_timeout = sys_cpu_to_le16(conn->le.timeout);

#if defined(CONFIG_BT_STACK_PTS)
  if (event_flag == dir_connect_req) {
    bt_addr_le_copy(&cp->peer_addr, &pts_addr);

    cp->filter_policy = 0;
    cp->own_addr_type = BT_ADDR_LE_PUBLIC;

    /* User Initiated procedure use fast scan parameters. */
    cp->scan_interval = sys_cpu_to_le16(BT_GAP_SCAN_FAST_INTERVAL);
    cp->scan_window   = sys_cpu_to_le16(BT_GAP_SCAN_FAST_WINDOW);
  }
#endif
  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CREATE_CONN, buf, NULL);
}
#endif /* CONFIG_BT_CENTRAL */

static void hci_disconn_complete(struct net_buf *buf) {
  struct bt_hci_evt_disconn_complete *evt    = (void *)buf->data;
  u16_t                               handle = sys_le16_to_cpu(evt->handle);
  struct bt_conn                     *conn;

  BT_DBG("status 0x%02x handle %u reason 0x%02x", evt->status, handle, evt->reason);

  if (evt->status) {
    return;
  }

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to look up conn with handle %u", handle);
    goto advertise;
  }

  conn->err = evt->reason;

  /* Check stacks usage */
#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
  STACK_ANALYZE("rx stack", rx_thread_stack);
#endif
#if !defined(BFLB_BLE)
  STACK_ANALYZE("tx stack", tx_thread_stack);
#endif

  bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
  conn->handle = 0U;

  if (conn->type != BT_CONN_TYPE_LE) {
#if defined(CONFIG_BT_BREDR)
    if (conn->type == BT_CONN_TYPE_SCO) {
      bt_sco_cleanup(conn);
      return;
    }
    /*
     * If only for one connection session bond was set, clear keys
     * database row for this connection.
     */
    if (conn->type == BT_CONN_TYPE_BR && atomic_test_and_clear_bit(conn->flags, BT_CONN_BR_NOBOND)) {
      bt_keys_link_key_clear(conn->br.link_key);
    }
#endif
    bt_conn_unref(conn);
#if defined(CONFIG_BT_BREDR)
    notify_disconnected(conn);
#endif
    return;
  }

#if defined(CONFIG_BT_CENTRAL) && !defined(CONFIG_BT_WHITELIST)
  if (atomic_test_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
    bt_conn_set_state(conn, BT_CONN_CONNECT_SCAN);
    bt_le_scan_update(false);
  }
#endif /* defined(CONFIG_BT_CENTRAL) && !defined(CONFIG_BT_WHITELIST) */

  bt_conn_unref(conn);

#if defined(BFLB_BLE_PATCH_CLEAN_UP_CONNECT_REF)
  atomic_clear(&conn->ref);
#endif

#if defined(BFLB_RELEASE_CMD_SEM_IF_CONN_DISC)
  hci_release_conn_related_cmd();
#endif

#if defined(BFLB_BLE)
  notify_disconnected(conn);
#endif

#if defined(CONFIG_BLE_RECONNECT_TEST)
  if (conn->role == BT_CONN_ROLE_MASTER) {
    struct bt_le_conn_param param = {
        .interval_min = BT_GAP_INIT_CONN_INT_MIN,
        .interval_max = BT_GAP_INIT_CONN_INT_MAX,
        .latency      = 0,
        .timeout      = 400,
    };

    if (bt_conn_create_le(&conn->le.dst, ¶m)) {
      BT_DBG("Reconnecting. \n");
    } else {
      BT_DBG("Reconnect fail. \n");
    }
  }
#endif

advertise:
  if (atomic_test_bit(bt_dev.flags, BT_DEV_KEEP_ADVERTISING) && !atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
      le_set_private_addr(bt_dev.adv_id);
    }

    set_advertise_enable(true);
  }
}

static int hci_le_read_remote_features(struct bt_conn *conn) {
  struct bt_hci_cp_le_read_remote_features *cp;
  struct net_buf                           *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_READ_REMOTE_FEATURES, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(conn->handle);
  bt_hci_cmd_send(BT_HCI_OP_LE_READ_REMOTE_FEATURES, buf);

  return 0;
}

/* LE Data Length Change Event is optional so this function just ignore
 * error and stack will continue to use default values.
 */
static void hci_le_set_data_len(struct bt_conn *conn) {
  struct bt_hci_rp_le_read_max_data_len *rp;
  struct bt_hci_cp_le_set_data_len      *cp;
  struct net_buf                        *buf, *rsp;
  u16_t                                  tx_octets, tx_time;
  int                                    err;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_MAX_DATA_LEN, NULL, &rsp);
  if (err) {
    BT_ERR("Failed to read DLE max data len");
    return;
  }

  rp        = (void *)rsp->data;
  tx_octets = sys_le16_to_cpu(rp->max_tx_octets);
  tx_time   = sys_le16_to_cpu(rp->max_tx_time);
  net_buf_unref(rsp);

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_DATA_LEN, sizeof(*cp));
  if (!buf) {
    BT_ERR("Failed to create LE Set Data Length Command");
    return;
  }

  cp            = net_buf_add(buf, sizeof(*cp));
  cp->handle    = sys_cpu_to_le16(conn->handle);
  cp->tx_octets = sys_cpu_to_le16(tx_octets);
  cp->tx_time   = sys_cpu_to_le16(tx_time);
  err           = bt_hci_cmd_send(BT_HCI_OP_LE_SET_DATA_LEN, buf);
  if (err) {
    BT_ERR("Failed to send LE Set Data Length Command");
  }
}

int bt_le_set_data_len(struct bt_conn *conn, u16_t tx_octets, u16_t tx_time) {
  struct bt_hci_cp_le_set_data_len *cp;
  struct net_buf                   *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_DATA_LEN, sizeof(*cp));
  if (!buf) {
    BT_ERR("bt_le_set_data_len, Failed to create LE Set Data Length Command");
    return -ENOBUFS;
  }

  cp            = net_buf_add(buf, sizeof(*cp));
  cp->handle    = sys_cpu_to_le16(conn->handle);
  cp->tx_octets = sys_cpu_to_le16(tx_octets);
  cp->tx_time   = sys_cpu_to_le16(tx_time);

  return bt_hci_cmd_send(BT_HCI_OP_LE_SET_DATA_LEN, buf);
}

int hci_le_set_phy(struct bt_conn *conn, uint8_t all_phys, uint8_t pref_tx_phy, uint8_t pref_rx_phy, uint8_t phy_opts) {
  struct bt_hci_cp_le_set_phy *cp;
  struct net_buf              *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_PHY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp           = net_buf_add(buf, sizeof(*cp));
  cp->handle   = sys_cpu_to_le16(conn->handle);
  cp->all_phys = all_phys;
  cp->tx_phys  = pref_tx_phy;
  cp->rx_phys  = pref_rx_phy;
  cp->phy_opts = phy_opts;

  return bt_hci_cmd_send(BT_HCI_OP_LE_SET_PHY, buf);
}

int hci_le_set_default_phy(u8_t default_phy) {
  struct bt_hci_cp_le_set_default_phy *cp;
  struct net_buf                      *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_DEFAULT_PHY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp           = net_buf_add(buf, sizeof(*cp));
  cp->all_phys = 0U;
  cp->tx_phys  = default_phy;
  cp->rx_phys  = default_phy;
  bt_hci_cmd_send(BT_HCI_OP_LE_SET_DEFAULT_PHY, buf);

  return 0;
}

static void slave_update_conn_param(struct bt_conn *conn) {
  if (!IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
    return;
  }

  /* don't start timer again on PHY update etc */
  if (atomic_test_bit(conn->flags, BT_CONN_SLAVE_PARAM_UPDATE)) {
    return;
  }

  /*
   * Core 4.2 Vol 3, Part C, 9.3.12.2
   * The Peripheral device should not perform a Connection Parameter
   * Update procedure within 5 s after establishing a connection.
   */
  k_delayed_work_submit(&conn->update_work, CONN_UPDATE_TIMEOUT);
}

#if defined(CONFIG_BT_SMP)
static void update_pending_id(struct bt_keys *keys, void *data) {
  if (keys->flags & BT_KEYS_ID_PENDING_ADD) {
    keys->flags &= ~BT_KEYS_ID_PENDING_ADD;
    bt_id_add(keys);
    return;
  }

  if (keys->flags & BT_KEYS_ID_PENDING_DEL) {
    keys->flags &= ~BT_KEYS_ID_PENDING_DEL;
    bt_id_del(keys);
    return;
  }
}
#endif

static struct bt_conn *find_pending_connect(bt_addr_le_t *peer_addr) {
  struct bt_conn *conn;

  /*
   * Make lookup to check if there's a connection object in
   * CONNECT or DIR_ADV state associated with passed peer LE address.
   */
  conn = bt_conn_lookup_state_le(peer_addr, BT_CONN_CONNECT);
  if (conn) {
    return conn;
  }

  return bt_conn_lookup_state_le(peer_addr, BT_CONN_CONNECT_DIR_ADV);
}

static void enh_conn_complete(struct bt_hci_evt_le_enh_conn_complete *evt) {
  u16_t           handle = sys_le16_to_cpu(evt->handle);
  bt_addr_le_t    peer_addr, id_addr;
  struct bt_conn *conn;
  int             err;

  BT_DBG("status 0x%02x handle %u role %u %s", evt->status, handle, evt->role, bt_addr_le_str(&evt->peer_addr));

#if defined(CONFIG_BT_SMP)
  if (atomic_test_and_clear_bit(bt_dev.flags, BT_DEV_ID_PENDING)) {
    bt_keys_foreach(BT_KEYS_IRK, update_pending_id, NULL);
  }
#endif

  if (evt->status) {
    /*
     * If there was an error we are only interested in pending
     * connection. There is no need to check ID address as
     * only one connection can be in that state.
     *
     * Depending on error code address might not be valid anyway.
     */
    conn = find_pending_connect(NULL);
    if (!conn) {
      return;
    }

    conn->err = evt->status;

    if (IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
      /*
       * Handle advertising timeout after high duty directed
       * advertising.
       */
      if (conn->err == BT_HCI_ERR_ADV_TIMEOUT) {
        atomic_clear_bit(bt_dev.flags, BT_DEV_ADVERTISING);
        bt_conn_set_state(conn, BT_CONN_DISCONNECTED);

        goto done;
      }
    }

    if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
      /*
       * Handle cancellation of outgoing connection attempt.
       */
      if (conn->err == BT_HCI_ERR_UNKNOWN_CONN_ID) {
        /* We notify before checking autoconnect flag
         * as application may choose to change it from
         * callback.
         */
        bt_conn_set_state(conn, BT_CONN_DISCONNECTED);

#if !defined(CONFIG_BT_WHITELIST)
        /* Check if device is marked for autoconnect. */
        if (atomic_test_bit(conn->flags, BT_CONN_AUTO_CONNECT)) {
          bt_conn_set_state(conn, BT_CONN_CONNECT_SCAN);
        }
#endif /* !defined(CONFIG_BT_WHITELIST) */
        goto done;
      }
    }

    BT_WARN("Unexpected status 0x%02x", evt->status);

    bt_conn_unref(conn);

    return;
  }

  bt_addr_le_copy(&id_addr, &evt->peer_addr);

  /* Translate "enhanced" identity address type to normal one */
  if (id_addr.type == BT_ADDR_LE_PUBLIC_ID || id_addr.type == BT_ADDR_LE_RANDOM_ID) {
    id_addr.type -= BT_ADDR_LE_PUBLIC_ID;
    bt_addr_copy(&peer_addr.a, &evt->peer_rpa);
    peer_addr.type = BT_ADDR_LE_RANDOM;
  } else {
    bt_addr_le_copy(&peer_addr, &evt->peer_addr);
  }

  conn = find_pending_connect(&id_addr);

  if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && evt->role == BT_HCI_ROLE_SLAVE) {
    /*
     * clear advertising even if we are not able to add connection
     * object to keep host in sync with controller state
     */
    atomic_clear_bit(bt_dev.flags, BT_DEV_ADVERTISING);

    /* for slave we may need to add new connection */
    if (!conn) {
      conn = bt_conn_add_le(bt_dev.adv_id, &id_addr);
    }
  }

  if (IS_ENABLED(CONFIG_BT_CENTRAL) && IS_ENABLED(CONFIG_BT_WHITELIST) && evt->role == BT_HCI_ROLE_MASTER) {
    /* for whitelist initiator me may need to add new connection. */
    if (!conn) {
      conn = bt_conn_add_le(BT_ID_DEFAULT, &id_addr);
    }
  }

  if (!conn) {
    BT_ERR("Unable to add new conn for handle %u", handle);
    return;
  }

  conn->handle = handle;
  bt_addr_le_copy(&conn->le.dst, &id_addr);
  conn->le.interval = sys_le16_to_cpu(evt->interval);
  conn->le.latency  = sys_le16_to_cpu(evt->latency);
  conn->le.timeout  = sys_le16_to_cpu(evt->supv_timeout);
  conn->role        = evt->role;
  conn->err         = 0U;

  /*
   * Use connection address (instead of identity address) as initiator
   * or responder address. Only slave needs to be updated. For master all
   * was set during outgoing connection creation.
   */
  if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn->role == BT_HCI_ROLE_SLAVE) {
    bt_addr_le_copy(&conn->le.init_addr, &peer_addr);

    if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
#if defined(BFLB_BLE_PATCH_DHKEY_CHECK_FAILED)
      if (memcmp(&evt->local_rpa, BT_ADDR_ANY, sizeof(bt_addr_t)))
        bt_addr_copy(&conn->le.resp_addr.a, &evt->local_rpa);
      else
        bt_addr_copy(&conn->le.resp_addr.a, &bt_dev.random_addr.a);
#else
      bt_addr_copy(&conn->le.resp_addr.a, &evt->local_rpa);
#endif
      conn->le.resp_addr.type = BT_ADDR_LE_RANDOM;
    } else {
      bt_addr_le_copy(&conn->le.resp_addr, &bt_dev.id_addr[conn->id]);
    }

#if defined(CONFIG_BT_STACK_PTS)
    if (atomic_test_and_clear_bit(bt_dev.flags, BT_DEV_ADV_ADDRESS_IS_PUBLIC)) {
      bt_addr_le_copy(&conn->le.resp_addr, &bt_dev.id_addr[conn->id]);
    }
#endif

    /* if the controller supports, lets advertise for another
     * slave connection.
     * check for connectable advertising state is sufficient as
     * this is how this le connection complete for slave occurred.
     */
    if (atomic_test_bit(bt_dev.flags, BT_DEV_KEEP_ADVERTISING) && BT_LE_STATES_SLAVE_CONN_ADV(bt_dev.le.states)) {
      if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
        le_set_private_addr(bt_dev.adv_id);
      }

      set_advertise_enable(true);
    }
  }

  if (IS_ENABLED(CONFIG_BT_CENTRAL) && conn->role == BT_HCI_ROLE_MASTER) {
    if (IS_ENABLED(CONFIG_BT_WHITELIST) && atomic_test_bit(bt_dev.flags, BT_DEV_AUTO_CONN)) {
      conn->id = BT_ID_DEFAULT;
      atomic_clear_bit(bt_dev.flags, BT_DEV_AUTO_CONN);
    }

    bt_addr_le_copy(&conn->le.resp_addr, &peer_addr);

    if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
#if defined(BFLB_BLE_PATCH_DHKEY_CHECK_FAILED)
      if (memcmp(&evt->local_rpa, BT_ADDR_ANY, sizeof(bt_addr_t)))
        bt_addr_copy(&conn->le.init_addr.a, &evt->local_rpa);
      else
        bt_addr_copy(&conn->le.init_addr.a, &bt_dev.random_addr.a);
#else
      bt_addr_copy(&conn->le.init_addr.a, &evt->local_rpa);
#endif
      conn->le.init_addr.type = BT_ADDR_LE_RANDOM;
    } else {
      bt_addr_le_copy(&conn->le.init_addr, &bt_dev.id_addr[conn->id]);
    }

#if defined(CONFIG_BT_STACK_PTS)
    if (conn->le.own_adder_type == BT_ADDR_LE_PUBLIC_ID) {
      bt_addr_le_copy(&conn->le.init_addr, &bt_dev.id_addr[conn->id]);
    }
#endif
  }

  bt_conn_set_state(conn, BT_CONN_CONNECTED);

  /*
   * it is possible that connection was disconnected directly from
   * connected callback so we must check state before doing connection
   * parameters update
   */
  if (conn->state != BT_CONN_CONNECTED) {
    goto done;
  }

  if ((evt->role == BT_HCI_ROLE_MASTER) || BT_FEAT_LE_SLAVE_FEATURE_XCHG(bt_dev.le.features)) {
    err = hci_le_read_remote_features(conn);
    if (!err) {
      goto done;
    }
  }

  if (IS_ENABLED(CONFIG_BT_AUTO_PHY_UPDATE) && BT_FEAT_LE_PHY_2M(bt_dev.le.features)) {
    err = hci_le_set_phy(conn, 0U, BT_HCI_LE_PHY_PREFER_2M, BT_HCI_LE_PHY_PREFER_2M, BT_HCI_LE_PHY_CODED_ANY);
    if (!err) {
      atomic_set_bit(conn->flags, BT_CONN_AUTO_PHY_UPDATE);
      goto done;
    }
  }

  if (IS_ENABLED(CONFIG_BT_DATA_LEN_UPDATE) && BT_FEAT_LE_DLE(bt_dev.le.features)) {
    hci_le_set_data_len(conn);
  }

  if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn->role == BT_CONN_ROLE_SLAVE) {
    slave_update_conn_param(conn);
  }

done:
  bt_conn_unref(conn);
  if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
    bt_le_scan_update(false);
  }
}

static void le_enh_conn_complete(struct net_buf *buf) { enh_conn_complete((void *)buf->data); }

static void le_legacy_conn_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_conn_complete    *evt = (void *)buf->data;
  struct bt_hci_evt_le_enh_conn_complete enh;
  const bt_addr_le_t                    *id_addr;

  BT_DBG("status 0x%02x role %u %s", evt->status, evt->role, bt_addr_le_str(&evt->peer_addr));

  enh.status         = evt->status;
  enh.handle         = evt->handle;
  enh.role           = evt->role;
  enh.interval       = evt->interval;
  enh.latency        = evt->latency;
  enh.supv_timeout   = evt->supv_timeout;
  enh.clock_accuracy = evt->clock_accuracy;

  bt_addr_le_copy(&enh.peer_addr, &evt->peer_addr);

  if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
    bt_addr_copy(&enh.local_rpa, &bt_dev.random_addr.a);
  } else {
    bt_addr_copy(&enh.local_rpa, BT_ADDR_ANY);
  }

  if (evt->role == BT_HCI_ROLE_SLAVE) {
    id_addr = bt_lookup_id_addr(bt_dev.adv_id, &enh.peer_addr);
  } else {
    id_addr = bt_lookup_id_addr(BT_ID_DEFAULT, &enh.peer_addr);
  }

  if (id_addr != &enh.peer_addr) {
    bt_addr_copy(&enh.peer_rpa, &enh.peer_addr.a);
    bt_addr_le_copy(&enh.peer_addr, id_addr);
    enh.peer_addr.type += BT_ADDR_LE_PUBLIC_ID;
  } else {
    bt_addr_copy(&enh.peer_rpa, BT_ADDR_ANY);
  }

  enh_conn_complete(&enh);
}

static void le_remote_feat_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_remote_feat_complete *evt    = (void *)buf->data;
  u16_t                                      handle = sys_le16_to_cpu(evt->handle);
  struct bt_conn                            *conn;

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    return;
  }

  if (!evt->status) {
    memcpy(conn->le.features, evt->features, sizeof(conn->le.features));
  }

  if (IS_ENABLED(CONFIG_BT_AUTO_PHY_UPDATE) && BT_FEAT_LE_PHY_2M(bt_dev.le.features) && BT_FEAT_LE_PHY_2M(conn->le.features)) {
    int err;

    err = hci_le_set_phy(conn, 0U, BT_HCI_LE_PHY_PREFER_2M, BT_HCI_LE_PHY_PREFER_2M, BT_HCI_LE_PHY_CODED_ANY);
    if (!err) {
      atomic_set_bit(conn->flags, BT_CONN_AUTO_PHY_UPDATE);
      goto done;
    }
  }

  if (IS_ENABLED(CONFIG_BT_DATA_LEN_UPDATE) && BT_FEAT_LE_DLE(bt_dev.le.features) && BT_FEAT_LE_DLE(conn->le.features)) {
    hci_le_set_data_len(conn);
  }

#if !defined(CONFIG_BT_STACK_PTS)
  if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn->role == BT_CONN_ROLE_SLAVE) {
    slave_update_conn_param(conn);
  }
#endif
done:
  bt_conn_unref(conn);
}

#if defined(CONFIG_BT_DATA_LEN_UPDATE)
static void le_data_len_change(struct net_buf *buf) {
  struct bt_hci_evt_le_data_len_change *evt           = (void *)buf->data;
  u16_t                                 max_tx_octets = sys_le16_to_cpu(evt->max_tx_octets);
  u16_t                                 max_rx_octets = sys_le16_to_cpu(evt->max_rx_octets);
  u16_t                                 max_tx_time   = sys_le16_to_cpu(evt->max_tx_time);
  u16_t                                 max_rx_time   = sys_le16_to_cpu(evt->max_rx_time);
  u16_t                                 handle        = sys_le16_to_cpu(evt->handle);
  struct bt_conn                       *conn;

  UNUSED(max_tx_octets);
  UNUSED(max_rx_octets);
  UNUSED(max_tx_time);
  UNUSED(max_rx_time);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    return;
  }

  BT_DBG("max. tx: %u (%uus), max. rx: %u (%uus)", max_tx_octets, max_tx_time, max_rx_octets, max_rx_time);

  /* TODO use those */

  bt_conn_unref(conn);
}
#endif /* CONFIG_BT_DATA_LEN_UPDATE */

#if defined(CONFIG_BT_PHY_UPDATE)
static void le_phy_update_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_phy_update_complete *evt    = (void *)buf->data;
  u16_t                                     handle = sys_le16_to_cpu(evt->handle);
  struct bt_conn                           *conn;

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    return;
  }

  BT_DBG("PHY updated: status: 0x%02x, tx: %u, rx: %u", evt->status, evt->tx_phy, evt->rx_phy);

  notify_le_phy_updated(conn, evt->tx_phy, evt->rx_phy);

  if (!IS_ENABLED(CONFIG_BT_AUTO_PHY_UPDATE) || !atomic_test_and_clear_bit(conn->flags, BT_CONN_AUTO_PHY_UPDATE)) {
    goto done;
  }

  if (IS_ENABLED(CONFIG_BT_DATA_LEN_UPDATE) && BT_FEAT_LE_DLE(bt_dev.le.features) && BT_FEAT_LE_DLE(conn->le.features)) {
    hci_le_set_data_len(conn);
  }

  if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn->role == BT_CONN_ROLE_SLAVE) {
    slave_update_conn_param(conn);
  }

done:
  bt_conn_unref(conn);
}
#endif /* CONFIG_BT_PHY_UPDATE */

bool bt_le_conn_params_valid(const struct bt_le_conn_param *param) {
  /* All limits according to BT Core spec 5.0 [Vol 2, Part E, 7.8.12] */

  if (param->interval_min > param->interval_max || param->interval_min < 6 || param->interval_max > 3200) {
    return false;
  }

  if (param->latency > 499) {
    return false;
  }

  if (param->timeout < 10 || param->timeout > 3200 || ((param->timeout * 4U) <= ((1 + param->latency) * param->interval_max))) {
    return false;
  }

  return true;
}

static void le_conn_param_neg_reply(u16_t handle, u8_t reason) {
  struct bt_hci_cp_le_conn_param_req_neg_reply *cp;
  struct net_buf                               *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    BT_ERR("Unable to allocate buffer");
    return;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(handle);
  cp->reason = sys_cpu_to_le16(reason);

  bt_hci_cmd_send(BT_HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY, buf);
}

static int le_conn_param_req_reply(u16_t handle, const struct bt_le_conn_param *param) {
  struct bt_hci_cp_le_conn_param_req_reply *cp;
  struct net_buf                           *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_CONN_PARAM_REQ_REPLY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  (void)memset(cp, 0, sizeof(*cp));

  cp->handle       = sys_cpu_to_le16(handle);
  cp->interval_min = sys_cpu_to_le16(param->interval_min);
  cp->interval_max = sys_cpu_to_le16(param->interval_max);
  cp->latency      = sys_cpu_to_le16(param->latency);
  cp->timeout      = sys_cpu_to_le16(param->timeout);

  return bt_hci_cmd_send(BT_HCI_OP_LE_CONN_PARAM_REQ_REPLY, buf);
}

static void le_conn_param_req(struct net_buf *buf) {
  struct bt_hci_evt_le_conn_param_req *evt = (void *)buf->data;
  struct bt_le_conn_param              param;
  struct bt_conn                      *conn;
  u16_t                                handle;

  handle             = sys_le16_to_cpu(evt->handle);
  param.interval_min = sys_le16_to_cpu(evt->interval_min);
  param.interval_max = sys_le16_to_cpu(evt->interval_max);
  param.latency      = sys_le16_to_cpu(evt->latency);
  param.timeout      = sys_le16_to_cpu(evt->timeout);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    le_conn_param_neg_reply(handle, BT_HCI_ERR_UNKNOWN_CONN_ID);
    return;
  }

  if (!le_param_req(conn, ¶m)) {
    le_conn_param_neg_reply(handle, BT_HCI_ERR_INVALID_LL_PARAM);
  } else {
    le_conn_param_req_reply(handle, ¶m);
  }

  bt_conn_unref(conn);
}

static void le_conn_update_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_conn_update_complete *evt = (void *)buf->data;
  struct bt_conn                            *conn;
  u16_t                                      handle;

  handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("status 0x%02x, handle %u", evt->status, handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    return;
  }

  if (!evt->status) {
    conn->le.interval = sys_le16_to_cpu(evt->interval);
    conn->le.latency  = sys_le16_to_cpu(evt->latency);
    conn->le.timeout  = sys_le16_to_cpu(evt->supv_timeout);
    notify_le_param_updated(conn);
  } else if (evt->status == BT_HCI_ERR_UNSUPP_REMOTE_FEATURE && conn->role == BT_HCI_ROLE_SLAVE && !atomic_test_and_set_bit(conn->flags, BT_CONN_SLAVE_PARAM_L2CAP)) {
    /* CPR not supported, let's try L2CAP CPUP instead */
    struct bt_le_conn_param param;

    param.interval_min = conn->le.interval_min;
    param.interval_max = conn->le.interval_max;
    param.latency      = conn->le.pending_latency;
    param.timeout      = conn->le.pending_timeout;

    bt_l2cap_update_conn_param(conn, ¶m);
  }

  bt_conn_unref(conn);
}

#if defined(CONFIG_BT_CENTRAL)
static void check_pending_conn(const bt_addr_le_t *id_addr, const bt_addr_le_t *addr, u8_t evtype) {
  struct bt_conn *conn;

  /* No connections are allowed during explicit scanning */
  if (atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return;
  }

  /* Return if event is not connectable */
  if (evtype != BT_LE_ADV_IND && evtype != BT_LE_ADV_DIRECT_IND) {
    return;
  }

  conn = bt_conn_lookup_state_le(id_addr, BT_CONN_CONNECT_SCAN);
  if (!conn) {
    return;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING) && set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE)) {
    goto failed;
  }

  bt_addr_le_copy(&conn->le.resp_addr, addr);
  if (hci_le_create_conn(conn)) {
    goto failed;
  }

  bt_conn_set_state(conn, BT_CONN_CONNECT);
  bt_conn_unref(conn);
  return;

failed:
  conn->err = BT_HCI_ERR_UNSPECIFIED;
  bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
  bt_conn_unref(conn);
  bt_le_scan_update(false);
}
#endif /* CONFIG_BT_CENTRAL */

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
static int set_flow_control(void) {
  struct bt_hci_cp_host_buffer_size *hbs;
  struct net_buf                    *buf;
  int                                err;

  /* Check if host flow control is actually supported */
  if (!BT_CMD_TEST(bt_dev.supported_commands, 10, 5)) {
    BT_WARN("Controller to host flow control not supported");
    return 0;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_HOST_BUFFER_SIZE, sizeof(*hbs));
  if (!buf) {
    return -ENOBUFS;
  }

  hbs = net_buf_add(buf, sizeof(*hbs));
  (void)memset(hbs, 0, sizeof(*hbs));
  hbs->acl_mtu  = sys_cpu_to_le16(CONFIG_BT_L2CAP_RX_MTU + sizeof(struct bt_l2cap_hdr));
  hbs->acl_pkts = sys_cpu_to_le16(CONFIG_BT_ACL_RX_COUNT);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_HOST_BUFFER_SIZE, buf, NULL);
  if (err) {
    return err;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_SET_CTL_TO_HOST_FLOW, 1);
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_u8(buf, BT_HCI_CTL_TO_HOST_FLOW_ENABLE);
  return bt_hci_cmd_send_sync(BT_HCI_OP_SET_CTL_TO_HOST_FLOW, buf, NULL);
}
#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */

static int bt_clear_all_pairings(u8_t id) {
  bt_conn_disconnect_all(id);

  if (IS_ENABLED(CONFIG_BT_SMP)) {
    bt_keys_clear_all(id);
  }

  if (IS_ENABLED(CONFIG_BT_BREDR)) {
    bt_keys_link_key_clear_addr(NULL);
  }

  return 0;
}

int bt_unpair(u8_t id, const bt_addr_le_t *addr) {
  struct bt_keys *keys = NULL;
  struct bt_conn *conn;

  if (id >= CONFIG_BT_ID_MAX) {
    return -EINVAL;
  }

  if (!addr || !bt_addr_le_cmp(addr, BT_ADDR_LE_ANY)) {
    return bt_clear_all_pairings(id);
  }

  conn = bt_conn_lookup_addr_le(id, addr);
  if (conn) {
    /* Clear the conn->le.keys pointer since we'll invalidate it,
     * and don't want any subsequent code (like disconnected
     * callbacks) accessing it.
     */
    if (conn->type == BT_CONN_TYPE_LE) {
      keys          = conn->le.keys;
      conn->le.keys = NULL;
    }

    bt_conn_disconnect(conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
    bt_conn_unref(conn);
  }

  if (IS_ENABLED(CONFIG_BT_BREDR)) {
    /* LE Public may indicate BR/EDR as well */
    if (addr->type == BT_ADDR_LE_PUBLIC) {
      bt_keys_link_key_clear_addr(&addr->a);
    }
  }

  if (IS_ENABLED(CONFIG_BT_SMP)) {
    if (!keys) {
      keys = bt_keys_find_addr(id, addr);
    }

    if (keys) {
      bt_keys_clear(keys);
    }
  }

  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    bt_gatt_clear(id, addr);
  }

  return 0;
}

#endif /* CONFIG_BT_CONN */

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
static enum bt_security_err security_err_get(u8_t hci_err) {
  switch (hci_err) {
  case BT_HCI_ERR_SUCCESS:
    return BT_SECURITY_ERR_SUCCESS;
  case BT_HCI_ERR_AUTH_FAIL:
    return BT_SECURITY_ERR_AUTH_FAIL;
  case BT_HCI_ERR_PIN_OR_KEY_MISSING:
    return BT_SECURITY_ERR_PIN_OR_KEY_MISSING;
  case BT_HCI_ERR_PAIRING_NOT_SUPPORTED:
    return BT_SECURITY_ERR_PAIR_NOT_SUPPORTED;
  case BT_HCI_ERR_PAIRING_NOT_ALLOWED:
    return BT_SECURITY_ERR_PAIR_NOT_ALLOWED;
  case BT_HCI_ERR_INVALID_PARAM:
    return BT_SECURITY_ERR_INVALID_PARAM;
  default:
    return BT_SECURITY_ERR_UNSPECIFIED;
  }
}

static void reset_pairing(struct bt_conn *conn) {
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    atomic_clear_bit(conn->flags, BT_CONN_BR_PAIRING);
    atomic_clear_bit(conn->flags, BT_CONN_BR_PAIRING_INITIATOR);
    atomic_clear_bit(conn->flags, BT_CONN_BR_LEGACY_SECURE);
  }
#endif /* CONFIG_BT_BREDR */

  /* Reset required security level to current operational */
  conn->required_sec_level = conn->sec_level;
}
#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) */

#if defined(CONFIG_BT_BREDR)
static int reject_conn(const bt_addr_t *bdaddr, u8_t reason) {
  struct bt_hci_cp_reject_conn_req *cp;
  struct net_buf                   *buf;
  int                               err;

  buf = bt_hci_cmd_create(BT_HCI_OP_REJECT_CONN_REQ, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  cp->reason = reason;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_REJECT_CONN_REQ, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}

static int accept_sco_conn(const bt_addr_t *bdaddr, struct bt_conn *sco_conn) {
  struct bt_hci_cp_accept_sync_conn_req *cp;
  struct net_buf                        *buf;
  int                                    err;

  buf = bt_hci_cmd_create(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  cp->pkt_type = sco_conn->sco.pkt_type;

  cp->tx_bandwidth   = 0x00001f40;
  cp->rx_bandwidth   = 0x00001f40;
  cp->max_latency    = 0x0007;
  cp->retrans_effort = 0x01;
  cp->content_format = BT_VOICE_CVSD_16BIT;
#if defined CONFIG_BT_HFP
  if (!hfp_codec_msbc) {
    cp->max_latency    = 0x000d;
    cp->retrans_effort = 0x02;
    cp->content_format = BT_VOICE_MSBC_16BIT;
    BT_DBG("eSCO air coding mSBC!");
  }
#endif
  err = bt_hci_cmd_send_sync(BT_HCI_OP_ACCEPT_SYNC_CONN_REQ, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}

static int accept_conn(const bt_addr_t *bdaddr) {
  struct bt_hci_cp_accept_conn_req *cp;
  struct net_buf                   *buf;
  int                               err;

  buf = bt_hci_cmd_create(BT_HCI_OP_ACCEPT_CONN_REQ, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  cp->role = BT_HCI_ROLE_SLAVE;

  err = bt_hci_cmd_send_sync(BT_HCI_OP_ACCEPT_CONN_REQ, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}

static void bt_esco_conn_req(struct bt_hci_evt_conn_request *evt) {
  struct bt_conn *sco_conn;

  sco_conn = bt_conn_add_sco(&evt->bdaddr, evt->link_type);
  if (!sco_conn) {
    reject_conn(&evt->bdaddr, BT_HCI_ERR_INSUFFICIENT_RESOURCES);
    return;
  }

  if (accept_sco_conn(&evt->bdaddr, sco_conn)) {
    BT_ERR("Error accepting connection from %s", bt_addr_str(&evt->bdaddr));
    reject_conn(&evt->bdaddr, BT_HCI_ERR_UNSPECIFIED);
    bt_sco_cleanup(sco_conn);
    return;
  }

  sco_conn->role = BT_HCI_ROLE_SLAVE;
  bt_conn_set_state(sco_conn, BT_CONN_CONNECT);
  bt_conn_unref(sco_conn);
}

static void conn_req(struct net_buf *buf) {
  struct bt_hci_evt_conn_request *evt = (void *)buf->data;
  struct bt_conn                 *conn;

  BT_DBG("conn req from %s, type 0x%02x", bt_addr_str(&evt->bdaddr), evt->link_type);

  if (evt->link_type != BT_HCI_ACL) {
    bt_esco_conn_req(evt);
    return;
  }

  conn = bt_conn_add_br(&evt->bdaddr);
  if (!conn) {
    reject_conn(&evt->bdaddr, BT_HCI_ERR_INSUFFICIENT_RESOURCES);
    return;
  }

  accept_conn(&evt->bdaddr);
  conn->role = BT_HCI_ROLE_SLAVE;
  bt_conn_set_state(conn, BT_CONN_CONNECT);
  bt_conn_unref(conn);
}

static bool br_sufficient_key_size(struct bt_conn *conn) {
  struct bt_hci_cp_read_encryption_key_size *cp;
  struct bt_hci_rp_read_encryption_key_size *rp;
  struct net_buf                            *buf, *rsp;
  u8_t                                       key_size;
  int                                        err;

  buf = bt_hci_cmd_create(BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE, sizeof(*cp));
  if (!buf) {
    BT_ERR("Failed to allocate command buffer");
    return false;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(conn->handle);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE, buf, &rsp);
  if (err) {
    BT_ERR("Failed to read encryption key size (err %d)", err);
    return false;
  }

  if (rsp->len < sizeof(*rp)) {
    BT_ERR("Too small command complete for encryption key size");
    net_buf_unref(rsp);
    return false;
  }

  rp       = (void *)rsp->data;
  key_size = rp->key_size;
  net_buf_unref(rsp);

  BT_DBG("Encryption key size is %u", key_size);

  if (conn->sec_level == BT_SECURITY_L4) {
    return key_size == BT_HCI_ENCRYPTION_KEY_SIZE_MAX;
  }

  return key_size >= BT_HCI_ENCRYPTION_KEY_SIZE_MIN;
}

static bool update_sec_level_br(struct bt_conn *conn) {
  if (!conn->encrypt) {
    conn->sec_level = BT_SECURITY_L1;
    return true;
  }

  if (conn->br.link_key) {
    if (conn->br.link_key->flags & BT_LINK_KEY_AUTHENTICATED) {
      if (conn->encrypt == 0x02) {
        conn->sec_level = BT_SECURITY_L4;
      } else {
        conn->sec_level = BT_SECURITY_L3;
      }
    } else {
      conn->sec_level = BT_SECURITY_L2;
    }
  } else {
    BT_WARN("No BR/EDR link key found");
    conn->sec_level = BT_SECURITY_L2;
  }

  if (!br_sufficient_key_size(conn)) {
    BT_ERR("Encryption key size is not sufficient");
    bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
    return false;
  }

  if (conn->required_sec_level > conn->sec_level) {
    BT_ERR("Failed to set required security level");
    bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
    return false;
  }

  return true;
}

static void synchronous_conn_complete(struct net_buf *buf) {
  struct bt_hci_evt_sync_conn_complete *evt = (void *)buf->data;
  struct bt_conn                       *sco_conn;
  u16_t                                 handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("status 0x%02x, handle %u, type 0x%02x", evt->status, handle, evt->link_type);

  sco_conn = bt_conn_lookup_addr_sco(&evt->bdaddr);
  if (!sco_conn) {
    BT_ERR("Unable to find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  if (evt->status) {
    sco_conn->err = evt->status;
    bt_conn_set_state(sco_conn, BT_CONN_DISCONNECTED);
    bt_conn_unref(sco_conn);
    return;
  }

  sco_conn->handle = handle;
  bt_conn_set_state(sco_conn, BT_CONN_CONNECTED);
  bt_conn_unref(sco_conn);
}

static void conn_complete(struct net_buf *buf) {
  struct bt_hci_evt_conn_complete       *evt = (void *)buf->data;
  struct bt_conn                        *conn;
  struct bt_hci_cp_read_remote_features *cp;
  u16_t                                  handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("status 0x%02x, handle %u, type 0x%02x", evt->status, handle, evt->link_type);

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Unable to find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  if (evt->status) {
    conn->err = evt->status;
    bt_conn_set_state(conn, BT_CONN_DISCONNECTED);
    bt_conn_unref(conn);
    return;
  }

  conn->handle  = handle;
  conn->err     = 0U;
  conn->encrypt = evt->encr_enabled;

  if (!update_sec_level_br(conn)) {
    bt_conn_unref(conn);
    return;
  }

  bt_conn_set_state(conn, BT_CONN_CONNECTED);
  bt_conn_unref(conn);

  buf = bt_hci_cmd_create(BT_HCI_OP_READ_REMOTE_FEATURES, sizeof(*cp));
  if (!buf) {
    return;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = evt->handle;

  bt_hci_cmd_send_sync(BT_HCI_OP_READ_REMOTE_FEATURES, buf, NULL);
}

static void pin_code_req(struct net_buf *buf) {
  struct bt_hci_evt_pin_code_req *evt = (void *)buf->data;
  struct bt_conn                 *conn;

  BT_DBG("");

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  bt_conn_pin_code_req(conn);
  bt_conn_unref(conn);
}

static void link_key_notify(struct net_buf *buf) {
  struct bt_hci_evt_link_key_notify *evt = (void *)buf->data;
  struct bt_conn                    *conn;

  printf("bredr link key: ");
  for (int i = 0; i < 16; i++) {
    printf("0x%02x ", evt->link_key[i]);
  }
  printf("\n");

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  BT_DBG("%s, link type 0x%02x", bt_addr_str(&evt->bdaddr), evt->key_type);

  if (!conn->br.link_key) {
    conn->br.link_key = bt_keys_get_link_key(&evt->bdaddr);
  }
  if (!conn->br.link_key) {
    BT_ERR("Can't update keys for %s", bt_addr_str(&evt->bdaddr));
    bt_conn_unref(conn);
    return;
  }

  /* clear any old Link Key flags */
  conn->br.link_key->flags = 0U;

  switch (evt->key_type) {
  case BT_LK_COMBINATION:
    /*
     * Setting Combination Link Key as AUTHENTICATED means it was
     * successfully generated by 16 digits wide PIN code.
     */
    if (atomic_test_and_clear_bit(conn->flags, BT_CONN_BR_LEGACY_SECURE)) {
      conn->br.link_key->flags |= BT_LINK_KEY_AUTHENTICATED;
    }
    memcpy(conn->br.link_key->val, evt->link_key, 16);
    break;
  case BT_LK_AUTH_COMBINATION_P192:
    conn->br.link_key->flags |= BT_LINK_KEY_AUTHENTICATED;
    /* fall through */
    __attribute__((fallthrough));
  case BT_LK_UNAUTH_COMBINATION_P192:
    /* Mark no-bond so that link-key is removed on disconnection */
    if (bt_conn_ssp_get_auth(conn) < BT_HCI_DEDICATED_BONDING) {
      atomic_set_bit(conn->flags, BT_CONN_BR_NOBOND);
    }

    memcpy(conn->br.link_key->val, evt->link_key, 16);
    break;
  case BT_LK_AUTH_COMBINATION_P256:
    conn->br.link_key->flags |= BT_LINK_KEY_AUTHENTICATED;
    /* fall through */
    __attribute__((fallthrough));
  case BT_LK_UNAUTH_COMBINATION_P256:
    conn->br.link_key->flags |= BT_LINK_KEY_SC;

    /* Mark no-bond so that link-key is removed on disconnection */
    if (bt_conn_ssp_get_auth(conn) < BT_HCI_DEDICATED_BONDING) {
      atomic_set_bit(conn->flags, BT_CONN_BR_NOBOND);
    }

    memcpy(conn->br.link_key->val, evt->link_key, 16);
    break;
  default:
    BT_WARN("Unsupported Link Key type %u", evt->key_type);
    (void)memset(conn->br.link_key->val, 0, sizeof(conn->br.link_key->val));
    break;
  }

  bt_conn_unref(conn);
}

static void link_key_neg_reply(const bt_addr_t *bdaddr) {
  struct bt_hci_cp_link_key_neg_reply *cp;
  struct net_buf                      *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_LINK_KEY_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    BT_ERR("Out of command buffers");
    return;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  bt_hci_cmd_send_sync(BT_HCI_OP_LINK_KEY_NEG_REPLY, buf, NULL);
}

static void link_key_reply(const bt_addr_t *bdaddr, const u8_t *lk) {
  struct bt_hci_cp_link_key_reply *cp;
  struct net_buf                  *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_LINK_KEY_REPLY, sizeof(*cp));
  if (!buf) {
    BT_ERR("Out of command buffers");
    return;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  memcpy(cp->link_key, lk, 16);
  bt_hci_cmd_send_sync(BT_HCI_OP_LINK_KEY_REPLY, buf, NULL);
}

static void link_key_req(struct net_buf *buf) {
  struct bt_hci_evt_link_key_req *evt = (void *)buf->data;
  struct bt_conn                 *conn;

  BT_DBG("%s", bt_addr_str(&evt->bdaddr));

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    link_key_neg_reply(&evt->bdaddr);
    return;
  }

  if (!conn->br.link_key) {
    conn->br.link_key = bt_keys_find_link_key(&evt->bdaddr);
  }

  if (!conn->br.link_key) {
    link_key_neg_reply(&evt->bdaddr);
    bt_conn_unref(conn);
    return;
  }

  /*
   * Enforce regenerate by controller stronger link key since found one
   * in database not covers requested security level.
   */
  if (!(conn->br.link_key->flags & BT_LINK_KEY_AUTHENTICATED) && conn->required_sec_level > BT_SECURITY_L2) {
    link_key_neg_reply(&evt->bdaddr);
    bt_conn_unref(conn);
    return;
  }

  link_key_reply(&evt->bdaddr, conn->br.link_key->val);
  bt_conn_unref(conn);
}

static void io_capa_neg_reply(const bt_addr_t *bdaddr, const u8_t reason) {
  struct bt_hci_cp_io_capability_neg_reply *cp;
  struct net_buf                           *resp_buf;

  resp_buf = bt_hci_cmd_create(BT_HCI_OP_IO_CAPABILITY_NEG_REPLY, sizeof(*cp));
  if (!resp_buf) {
    BT_ERR("Out of command buffers");
    return;
  }

  cp = net_buf_add(resp_buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, bdaddr);
  cp->reason = reason;
  bt_hci_cmd_send_sync(BT_HCI_OP_IO_CAPABILITY_NEG_REPLY, resp_buf, NULL);
}

static void io_capa_resp(struct net_buf *buf) {
  struct bt_hci_evt_io_capa_resp *evt = (void *)buf->data;
  struct bt_conn                 *conn;

  BT_DBG("remote %s, IOcapa 0x%02x, auth 0x%02x", bt_addr_str(&evt->bdaddr), evt->capability, evt->authentication);

  if (evt->authentication > BT_HCI_GENERAL_BONDING_MITM) {
    BT_ERR("Invalid remote authentication requirements");
    io_capa_neg_reply(&evt->bdaddr, BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL);
    return;
  }

  if (evt->capability > BT_IO_NO_INPUT_OUTPUT) {
    BT_ERR("Invalid remote io capability requirements");
    io_capa_neg_reply(&evt->bdaddr, BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL);
    return;
  }

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Unable to find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  conn->br.remote_io_capa = evt->capability;
  conn->br.remote_auth    = evt->authentication;
  atomic_set_bit(conn->flags, BT_CONN_BR_PAIRING);
  bt_conn_unref(conn);
}

static void io_capa_req(struct net_buf *buf) {
  struct bt_hci_evt_io_capa_req        *evt = (void *)buf->data;
  struct net_buf                       *resp_buf;
  struct bt_conn                       *conn;
  struct bt_hci_cp_io_capability_reply *cp;
  u8_t                                  auth;

  BT_DBG("");

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  resp_buf = bt_hci_cmd_create(BT_HCI_OP_IO_CAPABILITY_REPLY, sizeof(*cp));
  if (!resp_buf) {
    BT_ERR("Out of command buffers");
    bt_conn_unref(conn);
    return;
  }

  /*
   * Set authentication requirements when acting as pairing initiator to
   * 'dedicated bond' with MITM protection set if local IO capa
   * potentially allows it, and for acceptor, based on local IO capa and
   * remote's authentication set.
   */
  if (atomic_test_bit(conn->flags, BT_CONN_BR_PAIRING_INITIATOR)) {
    if (bt_conn_get_io_capa() != BT_IO_NO_INPUT_OUTPUT) {
      auth = BT_HCI_DEDICATED_BONDING_MITM;
    } else {
      auth = BT_HCI_DEDICATED_BONDING;
    }
  } else {
    auth = bt_conn_ssp_get_auth(conn);
  }

  cp = net_buf_add(resp_buf, sizeof(*cp));
  bt_addr_copy(&cp->bdaddr, &evt->bdaddr);
  cp->capability     = bt_conn_get_io_capa();
  cp->authentication = auth;
  cp->oob_data       = 0U;
  bt_hci_cmd_send_sync(BT_HCI_OP_IO_CAPABILITY_REPLY, resp_buf, NULL);
  bt_conn_unref(conn);
}

static void ssp_complete(struct net_buf *buf) {
  struct bt_hci_evt_ssp_complete *evt = (void *)buf->data;
  struct bt_conn                 *conn;

  BT_DBG("status 0x%02x", evt->status);

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  bt_conn_ssp_auth_complete(conn, security_err_get(evt->status));
  if (evt->status) {
    bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
  }

  bt_conn_unref(conn);
}

static void user_confirm_req(struct net_buf *buf) {
  struct bt_hci_evt_user_confirm_req *evt = (void *)buf->data;
  struct bt_conn                     *conn;

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  bt_conn_ssp_auth(conn, sys_le32_to_cpu(evt->passkey));
  bt_conn_unref(conn);
}

static void user_passkey_notify(struct net_buf *buf) {
  struct bt_hci_evt_user_passkey_notify *evt = (void *)buf->data;
  struct bt_conn                        *conn;

  BT_DBG("");

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  bt_conn_ssp_auth(conn, sys_le32_to_cpu(evt->passkey));
  bt_conn_unref(conn);
}

static void user_passkey_req(struct net_buf *buf) {
  struct bt_hci_evt_user_passkey_req *evt = (void *)buf->data;
  struct bt_conn                     *conn;

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  bt_conn_ssp_auth(conn, 0);
  bt_conn_unref(conn);
}

struct discovery_priv {
  u16_t clock_offset;
  u8_t  pscan_rep_mode;
  u8_t  resolving;
} __packed;

static int request_name(const bt_addr_t *addr, u8_t pscan, u16_t offset) {
  struct bt_hci_cp_remote_name_request *cp;
  struct net_buf                       *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_REMOTE_NAME_REQUEST, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  bt_addr_copy(&cp->bdaddr, addr);
  cp->pscan_rep_mode = pscan;
  cp->reserved       = 0x00; /* reserver, should be set to 0x00 */
  cp->clock_offset   = offset;

  return bt_hci_cmd_send_sync(BT_HCI_OP_REMOTE_NAME_REQUEST, buf, NULL);
}

bredr_name_callback name_callback = NULL;
int                 remote_name_req(const bt_addr_t *addr, bredr_name_callback cb) {
  u8_t  pscan        = 0x01;
  u16_t clock_offset = 0x00;

  name_callback = cb;

  return request_name(addr, pscan, clock_offset);
}

void remote_name_complete(u8_t *name) {
  if (name_callback) {
    name_callback((const char *)name);
  }
}

#define EIR_SHORT_NAME    0x08
#define EIR_COMPLETE_NAME 0x09

static bool eir_has_name(const u8_t *eir) {
  int len = 240;

  while (len) {
    if (len < 2) {
      break;
    };

    /* Look for early termination */
    if (!eir[0]) {
      break;
    }

    /* Check if field length is correct */
    if (eir[0] > len - 1) {
      break;
    }

    switch (eir[1]) {
    case EIR_SHORT_NAME:
    case EIR_COMPLETE_NAME:
      if (eir[0] > 1) {
        return true;
      }
      break;
    default:
      break;
    }

    /* Parse next AD Structure */
    len -= eir[0] + 1;
    eir += eir[0] + 1;
  }

  return false;
}

static void report_discovery_results(void) {
  bool resolving_names = false;
  int  i;

  for (i = 0; i < discovery_results_count; i++) {
    struct discovery_priv *priv;

    priv = (struct discovery_priv *)&discovery_results[i]._priv;

    if (eir_has_name(discovery_results[i].eir)) {
      continue;
    }

    if (request_name(&discovery_results[i].addr, priv->pscan_rep_mode, priv->clock_offset)) {
      continue;
    }

    priv->resolving = 1U;
    resolving_names = true;
  }

  if (resolving_names) {
    return;
  }

  atomic_clear_bit(bt_dev.flags, BT_DEV_INQUIRY);

  discovery_cb(discovery_results, discovery_results_count);

  discovery_cb            = NULL;
  discovery_results       = NULL;
  discovery_results_size  = 0;
  discovery_results_count = 0;
}

static void inquiry_complete(struct net_buf *buf) {
  struct bt_hci_evt_inquiry_complete *evt = (void *)buf->data;

  if (evt->status) {
    BT_ERR("Failed to complete inquiry");
  }

  report_discovery_results();
}

static struct bt_br_discovery_result *get_result_slot(const bt_addr_t *addr, s8_t rssi) {
  struct bt_br_discovery_result *result = NULL;
  size_t                         i;

  /* check if already present in results */
  for (i = 0; i < discovery_results_count; i++) {
    if (!bt_addr_cmp(addr, &discovery_results[i].addr)) {
      return &discovery_results[i];
    }
  }

  /* Pick a new slot (if available) */
  if (discovery_results_count < discovery_results_size) {
    bt_addr_copy(&discovery_results[discovery_results_count].addr, addr);
    return &discovery_results[discovery_results_count++];
  }

  /* ignore if invalid RSSI */
  if (rssi == 0xff) {
    return NULL;
  }

  /*
   * Pick slot with smallest RSSI that is smaller then passed RSSI
   * TODO handle TX if present
   */
  for (i = 0; i < discovery_results_size; i++) {
    if (discovery_results[i].rssi > rssi) {
      continue;
    }

    if (!result || result->rssi > discovery_results[i].rssi) {
      result = &discovery_results[i];
    }
  }

  if (result) {
    BT_DBG("Reusing slot (old %s rssi %d dBm)", bt_addr_str(&result->addr), result->rssi);

    bt_addr_copy(&result->addr, addr);
  }

  return result;
}

static void inquiry_result_with_rssi(struct net_buf *buf) {
  u8_t num_reports = net_buf_pull_u8(buf);

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_INQUIRY)) {
    return;
  }

  BT_DBG("number of results: %u", num_reports);

  while (num_reports--) {
    struct bt_hci_evt_inquiry_result_with_rssi *evt;
    struct bt_br_discovery_result              *result;
    struct discovery_priv                      *priv;

    if (buf->len < sizeof(*evt)) {
      BT_ERR("Unexpected end to buffer");
      return;
    }

    evt = net_buf_pull_mem(buf, sizeof(*evt));
    BT_DBG("%s rssi %d dBm", bt_addr_str(&evt->addr), evt->rssi);

    result = get_result_slot(&evt->addr, evt->rssi);
    if (!result) {
      return;
    }

    priv                 = (struct discovery_priv *)&result->_priv;
    priv->pscan_rep_mode = evt->pscan_rep_mode;
    priv->clock_offset   = evt->clock_offset;

    memcpy(result->cod, evt->cod, 3);
    result->rssi = evt->rssi;

    /* we could reuse slot so make sure EIR is cleared */
    (void)memset(result->eir, 0, sizeof(result->eir));
  }
}

static void extended_inquiry_result(struct net_buf *buf) {
  struct bt_hci_evt_extended_inquiry_result *evt = (void *)buf->data;
  struct bt_br_discovery_result             *result;
  struct discovery_priv                     *priv;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_INQUIRY)) {
    return;
  }

  BT_DBG("%s rssi %d dBm", bt_addr_str(&evt->addr), evt->rssi);

  result = get_result_slot(&evt->addr, evt->rssi);
  if (!result) {
    return;
  }

  priv                 = (struct discovery_priv *)&result->_priv;
  priv->pscan_rep_mode = evt->pscan_rep_mode;
  priv->clock_offset   = evt->clock_offset;

  result->rssi = evt->rssi;
  memcpy(result->cod, evt->cod, 3);
  memcpy(result->eir, evt->eir, sizeof(result->eir));
}

static void remote_name_request_complete(struct net_buf *buf) {
  struct bt_hci_evt_remote_name_req_complete *evt = (void *)buf->data;
  struct bt_br_discovery_result              *result;
  struct discovery_priv                      *priv;
  int                                         eir_len = 240;
  u8_t                                       *eir;
  int                                         i;
  BT_DBG("remote name:%s", evt->name);

  if (evt->name) {
    remote_name_complete(evt->name);
  }

  result = get_result_slot(&evt->bdaddr, 0xff);
  if (!result) {
    return;
  }

  priv            = (struct discovery_priv *)&result->_priv;
  priv->resolving = 0U;

  if (evt->status) {
    goto check_names;
  }

  eir = result->eir;

  while (eir_len) {
    if (eir_len < 2) {
      break;
    };

    /* Look for early termination */
    if (!eir[0]) {
      size_t name_len;

      eir_len -= 2;

      /* name is null terminated */
      name_len = strlen((const char *)evt->name);

      if (name_len > eir_len) {
        eir[0] = eir_len + 1;
        eir[1] = EIR_SHORT_NAME;
      } else {
        eir[0] = name_len + 1;
        eir[1] = EIR_SHORT_NAME;
      }

      memcpy(&eir[2], evt->name, eir[0] - 1);

      break;
    }

    /* Check if field length is correct */
    if (eir[0] > eir_len - 1) {
      break;
    }

    /* next EIR Structure */
    eir_len -= eir[0] + 1;
    eir += eir[0] + 1;
  }

check_names:
  /* if still waiting for names */
  for (i = 0; i < discovery_results_count; i++) {
    struct discovery_priv *priv;

    priv = (struct discovery_priv *)&discovery_results[i]._priv;

    if (priv->resolving) {
      return;
    }
  }

  /* all names resolved, report discovery results */
  atomic_clear_bit(bt_dev.flags, BT_DEV_INQUIRY);

  discovery_cb(discovery_results, discovery_results_count);

  discovery_cb            = NULL;
  discovery_results       = NULL;
  discovery_results_size  = 0;
  discovery_results_count = 0;
}

static void link_encr(const u16_t handle) {
  struct bt_hci_cp_set_conn_encrypt *encr;
  struct net_buf                    *buf;

  BT_DBG("");

  buf = bt_hci_cmd_create(BT_HCI_OP_SET_CONN_ENCRYPT, sizeof(*encr));
  if (!buf) {
    BT_ERR("Out of command buffers");
    return;
  }

  encr          = net_buf_add(buf, sizeof(*encr));
  encr->handle  = sys_cpu_to_le16(handle);
  encr->encrypt = 0x01;

  bt_hci_cmd_send_sync(BT_HCI_OP_SET_CONN_ENCRYPT, buf, NULL);
}

static void auth_complete(struct net_buf *buf) {
  struct bt_hci_evt_auth_complete *evt = (void *)buf->data;
  struct bt_conn                  *conn;
  u16_t                            handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("status 0x%02x, handle %u", evt->status, handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Can't find conn for handle %u", handle);
    return;
  }

  if (evt->status) {
    if (conn->state == BT_CONN_CONNECTED) {
      /*
       * Inform layers above HCI about non-zero authentication
       * status to make them able cleanup pending jobs.
       */
      bt_l2cap_encrypt_change(conn, evt->status);
    }
    reset_pairing(conn);
  } else {
    link_encr(handle);
  }

  bt_conn_unref(conn);
}

static void read_remote_features_complete(struct net_buf *buf) {
  struct bt_hci_evt_remote_features         *evt    = (void *)buf->data;
  u16_t                                      handle = sys_le16_to_cpu(evt->handle);
  struct bt_hci_cp_read_remote_ext_features *cp;
  struct bt_conn                            *conn;

  BT_DBG("status 0x%02x handle %u", evt->status, handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Can't find conn for handle %u", handle);
    return;
  }

  if (evt->status) {
    goto done;
  }

  memcpy(conn->br.features[0], evt->features, sizeof(evt->features));

  if (!BT_FEAT_EXT_FEATURES(conn->br.features)) {
    goto done;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_READ_REMOTE_EXT_FEATURES, sizeof(*cp));
  if (!buf) {
    goto done;
  }

  /* Read remote host features (page 1) */
  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = evt->handle;
  cp->page   = 0x01;

  bt_hci_cmd_send_sync(BT_HCI_OP_READ_REMOTE_EXT_FEATURES, buf, NULL);

done:
  bt_conn_unref(conn);
}

static void read_remote_ext_features_complete(struct net_buf *buf) {
  struct bt_hci_evt_remote_ext_features *evt    = (void *)buf->data;
  u16_t                                  handle = sys_le16_to_cpu(evt->handle);
  struct bt_conn                        *conn;

  BT_DBG("status 0x%02x handle %u", evt->status, handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Can't find conn for handle %u", handle);
    return;
  }

  if (!evt->status && evt->page == 0x01) {
    memcpy(conn->br.features[1], evt->features, sizeof(conn->br.features[1]));
  }

  bt_conn_unref(conn);
}

static void role_change(struct net_buf *buf) {
  struct bt_hci_evt_role_change *evt = (void *)buf->data;
  struct bt_conn                *conn;

  BT_DBG("status 0x%02x role %u addr %s", evt->status, evt->role, bt_addr_str(&evt->bdaddr));

  if (evt->status) {
    return;
  }

  conn = bt_conn_lookup_addr_br(&evt->bdaddr);
  if (!conn) {
    BT_ERR("Can't find conn for %s", bt_addr_str(&evt->bdaddr));
    return;
  }

  if (evt->role) {
    conn->role = BT_CONN_ROLE_SLAVE;
  } else {
    conn->role = BT_CONN_ROLE_MASTER;
  }

  bt_conn_unref(conn);
}
#endif /* CONFIG_BT_BREDR */

#if defined(CONFIG_BT_SMP)
static int le_set_privacy_mode(const bt_addr_le_t *addr, u8_t mode) {
  struct bt_hci_cp_le_set_privacy_mode cp;
  struct net_buf                      *buf;
  int                                  err;

  /* Check if set privacy mode command is supported */
  if (!BT_CMD_TEST(bt_dev.supported_commands, 39, 2)) {
    BT_WARN("Set privacy mode command is not supported");
    return 0;
  }

  BT_DBG("addr %s mode 0x%02x", bt_addr_le_str(addr), mode);

  bt_addr_le_copy(&cp.id_addr, addr);
  cp.mode = mode;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_PRIVACY_MODE, sizeof(cp));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &cp, sizeof(cp));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_PRIVACY_MODE, buf, NULL);
  if (err) {
    return err;
  }

  return 0;
}
#if defined(CONFIG_BT_STACK_PTS)
int addr_res_enable(u8_t enable)
#else
static int addr_res_enable(u8_t enable)
#endif
{
  struct net_buf *buf;

  BT_DBG("%s", enable ? "enabled" : "disabled");

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_ADDR_RES_ENABLE, 1);
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_u8(buf, enable);

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_ADDR_RES_ENABLE, buf, NULL);
}

#if defined(CONFIG_BT_STACK_PTS)
int hci_id_add(const bt_addr_le_t *addr, u8_t val[16])
#else
static int hci_id_add(const bt_addr_le_t *addr, u8_t val[16])
#endif
{
  struct bt_hci_cp_le_add_dev_to_rl *cp;
  struct net_buf                    *buf;

  BT_DBG("addr %s", bt_addr_le_str(addr));

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_ADD_DEV_TO_RL, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_le_copy(&cp->peer_id_addr, addr);
  memcpy(cp->peer_irk, val, 16);

#if defined(CONFIG_BT_PRIVACY)
  memcpy(cp->local_irk, bt_dev.irk, 16);
#else
  (void)memset(cp->local_irk, 0, 16);
#endif

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_ADD_DEV_TO_RL, buf, NULL);
}

void bt_id_add(struct bt_keys *keys) {
  bool adv_enabled;
#if defined(CONFIG_BT_OBSERVER)
  bool scan_enabled;
#endif /* CONFIG_BT_OBSERVER */
  struct bt_conn *conn;
  int             err;

  BT_DBG("addr %s", bt_addr_le_str(&keys->addr));

  /* Nothing to be done if host-side resolving is used */
  if (!bt_dev.le.rl_size || bt_dev.le.rl_entries > bt_dev.le.rl_size) {
    bt_dev.le.rl_entries++;
    return;
  }

  conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT);
  if (conn) {
    atomic_set_bit(bt_dev.flags, BT_DEV_ID_PENDING);
    keys->flags |= BT_KEYS_ID_PENDING_ADD;
    bt_conn_unref(conn);
    return;
  }

  adv_enabled = atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING);
  if (adv_enabled) {
    set_advertise_enable(false);
  }

#if defined(CONFIG_BT_OBSERVER)
  scan_enabled = atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING);
  if (scan_enabled) {
    set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
  }
#endif /* CONFIG_BT_OBSERVER */

  /* If there are any existing entries address resolution will be on */
  if (bt_dev.le.rl_entries) {
    err = addr_res_enable(BT_HCI_ADDR_RES_DISABLE);
    if (err) {
      BT_WARN("Failed to disable address resolution");
      goto done;
    }
  }

  if (bt_dev.le.rl_entries == bt_dev.le.rl_size) {
    BT_WARN("Resolving list size exceeded. Switching to host.");

    err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_CLEAR_RL, NULL, NULL);
    if (err) {
      BT_ERR("Failed to clear resolution list");
      goto done;
    }

    bt_dev.le.rl_entries++;

    goto done;
  }

  err = hci_id_add(&keys->addr, keys->irk.val);
  if (err) {
    BT_ERR("Failed to add IRK to controller");
    goto done;
  }

  bt_dev.le.rl_entries++;

  /*
   * According to Core Spec. 5.0 Vol 1, Part A 5.4.5 Privacy Feature
   *
   * By default, network privacy mode is used when private addresses are
   * resolved and generated by the Controller, so advertising packets from
   * peer devices that contain private addresses will only be accepted.
   * By changing to the device privacy mode device is only concerned about
   * its privacy and will accept advertising packets from peer devices
   * that contain their identity address as well as ones that contain
   * a private address, even if the peer device has distributed its IRK in
   * the past.
   */
  err = le_set_privacy_mode(&keys->addr, BT_HCI_LE_PRIVACY_MODE_DEVICE);
  if (err) {
    BT_ERR("Failed to set privacy mode");
    goto done;
  }

done:
  addr_res_enable(BT_HCI_ADDR_RES_ENABLE);

#if defined(CONFIG_BT_OBSERVER)
  if (scan_enabled) {
    set_le_scan_enable(BT_HCI_LE_SCAN_ENABLE);
  }
#endif /* CONFIG_BT_OBSERVER */

  if (adv_enabled) {
    set_advertise_enable(true);
  }
}

static void keys_add_id(struct bt_keys *keys, void *data) { hci_id_add(&keys->addr, keys->irk.val); }

void bt_id_del(struct bt_keys *keys) {
  struct bt_hci_cp_le_rem_dev_from_rl *cp;
  bool                                 adv_enabled;
#if defined(CONFIG_BT_OBSERVER)
  bool scan_enabled;
#endif /* CONFIG_BT_OBSERVER */
  struct bt_conn *conn;
  struct net_buf *buf;
  int             err;

  BT_DBG("addr %s", bt_addr_le_str(&keys->addr));

  if (!bt_dev.le.rl_size || bt_dev.le.rl_entries > bt_dev.le.rl_size + 1) {
    bt_dev.le.rl_entries--;
    return;
  }

  conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT);
  if (conn) {
    atomic_set_bit(bt_dev.flags, BT_DEV_ID_PENDING);
    keys->flags |= BT_KEYS_ID_PENDING_DEL;
    bt_conn_unref(conn);
    return;
  }

  adv_enabled = atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING);
  if (adv_enabled) {
    set_advertise_enable(false);
  }

#if defined(CONFIG_BT_OBSERVER)
  scan_enabled = atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING);
  if (scan_enabled) {
    set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
  }
#endif /* CONFIG_BT_OBSERVER */

  err = addr_res_enable(BT_HCI_ADDR_RES_DISABLE);
  if (err) {
    BT_ERR("Disabling address resolution failed (err %d)", err);
    goto done;
  }

  /* We checked size + 1 earlier, so here we know we can fit again */
  if (bt_dev.le.rl_entries > bt_dev.le.rl_size) {
    bt_dev.le.rl_entries--;
    keys->keys &= ~BT_KEYS_IRK;
    bt_keys_foreach(BT_KEYS_IRK, keys_add_id, NULL);
    goto done;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_REM_DEV_FROM_RL, sizeof(*cp));
  if (!buf) {
    goto done;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_le_copy(&cp->peer_id_addr, &keys->addr);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_REM_DEV_FROM_RL, buf, NULL);
  if (err) {
    BT_ERR("Failed to remove IRK from controller");
    goto done;
  }

  bt_dev.le.rl_entries--;

done:
  /* Only re-enable if there are entries to do resolving with */
  if (bt_dev.le.rl_entries) {
    addr_res_enable(BT_HCI_ADDR_RES_ENABLE);
  }

#if defined(CONFIG_BT_OBSERVER)
  if (scan_enabled) {
    set_le_scan_enable(BT_HCI_LE_SCAN_ENABLE);
  }
#endif /* CONFIG_BT_OBSERVER */

  if (adv_enabled) {
    set_advertise_enable(true);
  }
}

static void update_sec_level(struct bt_conn *conn) {
  if (!conn->encrypt) {
    conn->sec_level = BT_SECURITY_L1;
    return;
  }

  if (conn->le.keys && (conn->le.keys->flags & BT_KEYS_AUTHENTICATED)) {
    if (conn->le.keys->flags & BT_KEYS_SC && conn->le.keys->enc_size == BT_SMP_MAX_ENC_KEY_SIZE) {
      conn->sec_level = BT_SECURITY_L4;
    } else {
      conn->sec_level = BT_SECURITY_L3;
    }
  } else {
    conn->sec_level = BT_SECURITY_L2;
  }

  if (conn->required_sec_level > conn->sec_level) {
    BT_ERR("Failed to set required security level");
    bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
  }
}
#endif /* CONFIG_BT_SMP */

#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
static void hci_encrypt_change(struct net_buf *buf) {
  struct bt_hci_evt_encrypt_change *evt    = (void *)buf->data;
  u16_t                             handle = sys_le16_to_cpu(evt->handle);
  struct bt_conn                   *conn;

  BT_DBG("status 0x%02x handle %u encrypt 0x%02x", evt->status, handle, evt->encrypt);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to look up conn with handle %u", handle);
    return;
  }

  if (evt->status) {
    reset_pairing(conn);
    bt_l2cap_encrypt_change(conn, evt->status);
    bt_conn_security_changed(conn, security_err_get(evt->status));
    bt_conn_unref(conn);
    return;
  }

  conn->encrypt = evt->encrypt;

#if defined(CONFIG_BT_SMP)
  if (conn->type == BT_CONN_TYPE_LE) {
    /*
     * we update keys properties only on successful encryption to
     * avoid losing valid keys if encryption was not successful.
     *
     * Update keys with last pairing info for proper sec level
     * update. This is done only for LE transport, for BR/EDR keys
     * are updated on HCI 'Link Key Notification Event'
     */
    if (conn->encrypt) {
      bt_smp_update_keys(conn);
    }
    update_sec_level(conn);
  }
#endif /* CONFIG_BT_SMP */
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    if (!update_sec_level_br(conn)) {
      bt_conn_unref(conn);
      return;
    }

    if (IS_ENABLED(CONFIG_BT_SMP)) {
      /*
       * Start SMP over BR/EDR if we are pairing and are
       * master on the link
       */
      if (atomic_test_bit(conn->flags, BT_CONN_BR_PAIRING) && conn->role == BT_CONN_ROLE_MASTER) {
        bt_smp_br_send_pairing_req(conn);
      }
    }
  }
#endif /* CONFIG_BT_BREDR */
  reset_pairing(conn);

  bt_l2cap_encrypt_change(conn, evt->status);
  bt_conn_security_changed(conn, BT_SECURITY_ERR_SUCCESS);

  bt_conn_unref(conn);
}

static void hci_encrypt_key_refresh_complete(struct net_buf *buf) {
  struct bt_hci_evt_encrypt_key_refresh_complete *evt = (void *)buf->data;
  struct bt_conn                                 *conn;
  u16_t                                           handle;

  handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("status 0x%02x handle %u", evt->status, handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to look up conn with handle %u", handle);
    return;
  }

  if (evt->status) {
    reset_pairing(conn);
    bt_l2cap_encrypt_change(conn, evt->status);
    bt_conn_security_changed(conn, security_err_get(evt->status));
    bt_conn_unref(conn);
    return;
  }

  /*
   * Update keys with last pairing info for proper sec level update.
   * This is done only for LE transport. For BR/EDR transport keys are
   * updated on HCI 'Link Key Notification Event', therefore update here
   * only security level based on available keys and encryption state.
   */
#if defined(CONFIG_BT_SMP)
  if (conn->type == BT_CONN_TYPE_LE) {
    bt_smp_update_keys(conn);
    update_sec_level(conn);
  }
#endif /* CONFIG_BT_SMP */
#if defined(CONFIG_BT_BREDR)
  if (conn->type == BT_CONN_TYPE_BR) {
    if (!update_sec_level_br(conn)) {
      bt_conn_unref(conn);
      return;
    }
  }
#endif /* CONFIG_BT_BREDR */

  reset_pairing(conn);
  bt_l2cap_encrypt_change(conn, evt->status);
  bt_conn_security_changed(conn, BT_SECURITY_ERR_SUCCESS);
  bt_conn_unref(conn);
}
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

#if defined(CONFIG_BT_SMP)
static void le_ltk_neg_reply(u16_t handle) {
  struct bt_hci_cp_le_ltk_req_neg_reply *cp;
  struct net_buf                        *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_LTK_REQ_NEG_REPLY, sizeof(*cp));
  if (!buf) {
    BT_ERR("Out of command buffers");

    return;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(handle);

  bt_hci_cmd_send(BT_HCI_OP_LE_LTK_REQ_NEG_REPLY, buf);
}

static void le_ltk_reply(u16_t handle, u8_t *ltk) {
  struct bt_hci_cp_le_ltk_req_reply *cp;
  struct net_buf                    *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_LTK_REQ_REPLY, sizeof(*cp));
  if (!buf) {
    BT_ERR("Out of command buffers");
    return;
  }

  cp         = net_buf_add(buf, sizeof(*cp));
  cp->handle = sys_cpu_to_le16(handle);
  memcpy(cp->ltk, ltk, sizeof(cp->ltk));

  bt_hci_cmd_send(BT_HCI_OP_LE_LTK_REQ_REPLY, buf);
}

static void le_ltk_request(struct net_buf *buf) {
  struct bt_hci_evt_le_ltk_request *evt = (void *)buf->data;
  struct bt_conn                   *conn;
  u16_t                             handle;
  u8_t                              ltk[16];

  handle = sys_le16_to_cpu(evt->handle);

  BT_DBG("handle %u", handle);

  conn = bt_conn_lookup_handle(handle);
  if (!conn) {
    BT_ERR("Unable to lookup conn for handle %u", handle);
    return;
  }

  if (bt_smp_request_ltk(conn, evt->rand, evt->ediv, ltk)) {
    le_ltk_reply(handle, ltk);
  } else {
    le_ltk_neg_reply(handle);
  }

  bt_conn_unref(conn);
}
#endif /* CONFIG_BT_SMP */

#if defined(CONFIG_BT_ECC)
static void le_pkey_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_p256_public_key_complete *evt = (void *)buf->data;
  struct bt_pub_key_cb                          *cb;

  BT_DBG("status: 0x%02x", evt->status);

  atomic_clear_bit(bt_dev.flags, BT_DEV_PUB_KEY_BUSY);

  if (!evt->status) {
    memcpy(pub_key, evt->key, 64);
    atomic_set_bit(bt_dev.flags, BT_DEV_HAS_PUB_KEY);
  }

  for (cb = pub_key_cb; cb; cb = cb->_next) {
    cb->func(evt->status ? NULL : pub_key);
  }

  pub_key_cb = NULL;
}

static void le_dhkey_complete(struct net_buf *buf) {
  struct bt_hci_evt_le_generate_dhkey_complete *evt = (void *)buf->data;

  BT_DBG("status: 0x%02x", evt->status);

  if (dh_key_cb) {
    dh_key_cb(evt->status ? NULL : evt->dhkey);
    dh_key_cb = NULL;
  }
}
#endif /* CONFIG_BT_ECC */

static void hci_reset_complete(struct net_buf *buf) {
  u8_t     status = buf->data[0];
  atomic_t flags;

  BT_DBG("status 0x%02x", status);

  if (status) {
    return;
  }

  scan_dev_found_cb = NULL;
#if defined(CONFIG_BT_BREDR)
  discovery_cb            = NULL;
  discovery_results       = NULL;
  discovery_results_size  = 0;
  discovery_results_count = 0;
#endif /* CONFIG_BT_BREDR */

  flags = (atomic_get(bt_dev.flags) & BT_DEV_PERSISTENT_FLAGS);
  atomic_set(bt_dev.flags, flags);
}

static void hci_cmd_done(u16_t opcode, u8_t status, struct net_buf *buf) {
  BT_DBG("opcode 0x%04x status 0x%02x buf %p", opcode, status, buf);

  if (net_buf_pool_get(buf->pool_id) != &hci_cmd_pool) {
    BT_WARN("opcode 0x%04x pool id %u pool %p != &hci_cmd_pool %p", opcode, buf->pool_id, net_buf_pool_get(buf->pool_id), &hci_cmd_pool);
    return;
  }

  if (cmd(buf)->opcode != opcode) {
    BT_WARN("OpCode 0x%04x completed instead of expected 0x%04x", opcode, cmd(buf)->opcode);
  }

  if (cmd(buf)->state && !status) {
    struct cmd_state_set *update = cmd(buf)->state;

    atomic_set_bit_to(update->target, update->bit, update->val);
  }

#if (BFLB_BT_CO_THREAD)
  /* If the command was synchronous wake up bt_hci_cmd_send_sync() */
  if (cmd(buf)->sync || cmd(buf)->sync_state) {
    cmd(buf)->status = status;
    if (cmd(buf)->sync_state)
      cmd(buf)->sync_state = BT_CMD_SYNC_TX_DONE;
    else
      k_sem_give(cmd(buf)->sync);
  }
#else
  if (cmd(buf)->sync) {
    cmd(buf)->status = status;
    k_sem_give(cmd(buf)->sync);
  }
#endif // BFLB_BT_CO_THREAD
}

static void hci_cmd_complete(struct net_buf *buf) {
  struct bt_hci_evt_cmd_complete *evt;
  u8_t                            status, ncmd;
  u16_t                           opcode;

  evt    = net_buf_pull_mem(buf, sizeof(*evt));
  ncmd   = evt->ncmd;
  opcode = sys_le16_to_cpu(evt->opcode);

  BT_DBG("opcode 0x%04x", opcode);

  /* All command return parameters have a 1-byte status in the
   * beginning, so we can safely make this generalization.
   */
  status = buf->data[0];

  hci_cmd_done(opcode, status, buf);

  /* Allow next command to be sent */
  if (ncmd) {
    k_sem_give(&bt_dev.ncmd_sem);
  }
}

static void hci_cmd_status(struct net_buf *buf) {
  struct bt_hci_evt_cmd_status *evt;
  u16_t                         opcode;
  u8_t                          ncmd;

  evt    = net_buf_pull_mem(buf, sizeof(*evt));
  opcode = sys_le16_to_cpu(evt->opcode);
  ncmd   = evt->ncmd;

  BT_DBG("opcode 0x%04x", opcode);

  hci_cmd_done(opcode, evt->status, buf);

  /* Allow next command to be sent */
  if (ncmd) {
    k_sem_give(&bt_dev.ncmd_sem);
  }
}

#if defined(CONFIG_BT_OBSERVER)
static int start_le_scan(u8_t scan_type, u16_t interval, u16_t window) {
  struct bt_hci_cp_le_set_scan_param set_param;
  struct net_buf                    *buf;
  int                                err;

  (void)memset(&set_param, 0, sizeof(set_param));

  set_param.scan_type = scan_type;

  /* for the rest parameters apply default values according to
   *  spec 4.2, vol2, part E, 7.8.10
   */
  set_param.interval = sys_cpu_to_le16(interval);
  set_param.window   = sys_cpu_to_le16(window);

  if (IS_ENABLED(CONFIG_BT_WHITELIST) && atomic_test_bit(bt_dev.flags, BT_DEV_SCAN_WL)) {
    set_param.filter_policy = BT_HCI_LE_SCAN_FP_USE_WHITELIST;
  } else {
    set_param.filter_policy = BT_HCI_LE_SCAN_FP_NO_WHITELIST;
  }

  if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
    err = le_set_private_addr(BT_ID_DEFAULT);
    if (err) {
      return err;
    }

    if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
      set_param.addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
    } else {
      set_param.addr_type = BT_ADDR_LE_RANDOM;
    }
  } else {
    set_param.addr_type = bt_dev.id_addr[0].type;

    /* Use NRPA unless identity has been explicitly requested
     * (through Kconfig), or if there is no advertising ongoing.
     */
    if (!IS_ENABLED(CONFIG_BT_SCAN_WITH_IDENTITY) && scan_type == BT_HCI_LE_SCAN_ACTIVE && !atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
      err = le_set_private_addr(BT_ID_DEFAULT);
      if (err) {
        return err;
      }

      set_param.addr_type = BT_ADDR_LE_RANDOM;
    } else if (set_param.addr_type == BT_ADDR_LE_RANDOM) {
      err = set_random_address(&bt_dev.id_addr[0].a);
      if (err) {
        return err;
      }
    }
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_SCAN_PARAM, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_SCAN_PARAM, buf, NULL);

  err = set_le_scan_enable(BT_HCI_LE_SCAN_ENABLE);
  if (err) {
    return err;
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ACTIVE_SCAN, scan_type == BT_HCI_LE_SCAN_ACTIVE);

  return 0;
}

#if defined(CONFIG_BT_STACK_PTS)
static int start_le_scan_with_isrpa(u8_t scan_type, u16_t interval, u16_t window, u8_t addre_type) {
  struct bt_hci_cp_le_set_scan_param set_param;
  struct net_buf                    *buf;
  int                                err = 0;

  memset(&set_param, 0, sizeof(set_param));

  set_param.scan_type = scan_type;

  /* for the rest parameters apply default values according to
   *  spec 4.2, vol2, part E, 7.8.10
   */
  set_param.interval      = sys_cpu_to_le16(interval);
  set_param.window        = sys_cpu_to_le16(window);
  set_param.filter_policy = 0x00;

  if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
    if (addre_type == 1)
      err = le_set_private_addr(BT_ID_DEFAULT);
    else if (addre_type == 0)
      err = le_set_non_resolv_private_addr(BT_ID_DEFAULT);
    if (err) {
      return err;
    }

    if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
      if (addre_type == 2)
        set_param.addr_type = BT_ADDR_LE_PUBLIC;
      if (addre_type == 1)
        set_param.addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
      else if (addre_type == 0)
        set_param.addr_type = BT_ADDR_LE_RANDOM;
    } else {
      set_param.addr_type = BT_ADDR_LE_RANDOM;
    }
  } else {
    set_param.addr_type = bt_dev.id_addr[0].type;

    /* Use NRPA unless identity has been explicitly requested
     * (through Kconfig), or if there is no advertising ongoing.
     */
    if (!IS_ENABLED(CONFIG_BT_SCAN_WITH_IDENTITY) && scan_type == BT_HCI_LE_SCAN_ACTIVE && !atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
      err = le_set_private_addr(BT_ID_DEFAULT);
      if (err) {
        return err;
      }

      set_param.addr_type = BT_ADDR_LE_RANDOM;
    }
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_SCAN_PARAM, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_SCAN_PARAM, buf, NULL);

  err = set_le_scan_enable(BT_HCI_LE_SCAN_ENABLE);
  if (err) {
    return err;
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ACTIVE_SCAN, scan_type == BT_HCI_LE_SCAN_ACTIVE);

  return 0;
}

#endif

int bt_le_scan_update(bool fast_scan) {
  if (atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return 0;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
    int err;

    err = set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
    if (err) {
      return err;
    }
  }

  if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
    u16_t           interval, window;
    struct bt_conn *conn;

    /* don't restart scan if we have pending connection */
    conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT);
    if (conn) {
      bt_conn_unref(conn);
      return 0;
    }

    conn = bt_conn_lookup_state_le(NULL, BT_CONN_CONNECT_SCAN);
    if (!conn) {
      return 0;
    }

    // atomic_set_bit(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP);
    atomic_clear_bit(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP);

    bt_conn_unref(conn);

    if (fast_scan) {
      interval = BT_GAP_SCAN_FAST_INTERVAL;
      window   = BT_GAP_SCAN_FAST_WINDOW;
    } else {
      interval = CONFIG_BT_BACKGROUND_SCAN_INTERVAL;
      window   = CONFIG_BT_BACKGROUND_SCAN_WINDOW;
    }

    return start_le_scan(BT_HCI_LE_SCAN_PASSIVE, interval, window);
  }

  return 0;
}

void bt_data_parse(struct net_buf_simple *ad, bool (*func)(struct bt_data *data, void *user_data), void *user_data) {
  while (ad->len > 1) {
    struct bt_data data;
    u8_t           len;

    len = net_buf_simple_pull_u8(ad);
    if (len == 0U) {
      /* Early termination */
      return;
    }

    if (len > ad->len) {
      BT_WARN("Malformed data");
      return;
    }

    data.type     = net_buf_simple_pull_u8(ad);
    data.data_len = len - 1;
    data.data     = ad->data;

    if (!func(&data, user_data)) {
      return;
    }

    net_buf_simple_pull(ad, len - 1);
  }
}

static void le_adv_report(struct net_buf *buf) {
  u8_t                                   num_reports = net_buf_pull_u8(buf);
  struct bt_hci_evt_le_advertising_info *info;

  BT_DBG("Adv number of reports %u", num_reports);

  while (num_reports--) {
    bt_addr_le_t id_addr;
    s8_t         rssi;

    if (buf->len < sizeof(*info)) {
      BT_ERR("Unexpected end of buffer");
      break;
    }

    info = net_buf_pull_mem(buf, sizeof(*info));
    rssi = info->data[info->length];

    BT_DBG("%s event %u, len %u, rssi %d dBm", bt_addr_le_str(&info->addr), info->evt_type, info->length, rssi);

    if (info->addr.type == BT_ADDR_LE_PUBLIC_ID || info->addr.type == BT_ADDR_LE_RANDOM_ID) {
      bt_addr_le_copy(&id_addr, &info->addr);
      id_addr.type -= BT_ADDR_LE_PUBLIC_ID;
    } else {
      bt_addr_le_copy(&id_addr, bt_lookup_id_addr(bt_dev.adv_id, &info->addr));
    }

    if (scan_dev_found_cb) {
      struct net_buf_simple_state state;

      net_buf_simple_save(&buf->b, &state);

      buf->len = info->length;
      scan_dev_found_cb(&id_addr, rssi, info->evt_type, &buf->b);

      net_buf_simple_restore(&buf->b, &state);
    }

#if defined(CONFIG_BT_CENTRAL)
    check_pending_conn(&id_addr, &info->addr, info->evt_type);
#endif /* CONFIG_BT_CENTRAL */

    net_buf_pull(buf, info->length + sizeof(rssi));
  }
}
#endif /* CONFIG_BT_OBSERVER */

int bt_hci_get_conn_handle(const struct bt_conn *conn, u16_t *conn_handle) {
  if (conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  *conn_handle = conn->handle;
  return 0;
}

#if defined(CONFIG_BT_HCI_VS_EVT_USER)
int bt_hci_register_vnd_evt_cb(bt_hci_vnd_evt_cb_t cb) {
  hci_vnd_evt_cb = cb;
  return 0;
}
#endif /* CONFIG_BT_HCI_VS_EVT_USER */

static void hci_vendor_event(struct net_buf *buf) {
  bool handled = false;

#if defined(CONFIG_BT_HCI_VS_EVT_USER)
  if (hci_vnd_evt_cb) {
    struct net_buf_simple_state state;

    net_buf_simple_save(&buf->b, &state);

    handled = (hci_vnd_evt_cb)(&buf->b);

    net_buf_simple_restore(&buf->b, &state);
  }
#endif /* CONFIG_BT_HCI_VS_EVT_USER */

  if (IS_ENABLED(CONFIG_BT_HCI_VS_EXT) && !handled) {
    /* do nothing at present time */
    BT_WARN("Unhandled vendor-specific event: %s", bt_hex(buf->data, buf->len));
  }
}

static const struct event_handler meta_events[] = {
#if defined(CONFIG_BT_OBSERVER)
    EVENT_HANDLER(BT_HCI_EVT_LE_ADVERTISING_REPORT, le_adv_report, sizeof(struct bt_hci_evt_le_advertising_report)),
#endif /* CONFIG_BT_OBSERVER */
#if defined(CONFIG_BT_CONN)
    EVENT_HANDLER(BT_HCI_EVT_LE_CONN_COMPLETE, le_legacy_conn_complete, sizeof(struct bt_hci_evt_le_conn_complete)),
    EVENT_HANDLER(BT_HCI_EVT_LE_ENH_CONN_COMPLETE, le_enh_conn_complete, sizeof(struct bt_hci_evt_le_enh_conn_complete)),
    EVENT_HANDLER(BT_HCI_EVT_LE_CONN_UPDATE_COMPLETE, le_conn_update_complete, sizeof(struct bt_hci_evt_le_conn_update_complete)),
    EVENT_HANDLER(BT_HCI_EV_LE_REMOTE_FEAT_COMPLETE, le_remote_feat_complete, sizeof(struct bt_hci_evt_le_remote_feat_complete)),
    EVENT_HANDLER(BT_HCI_EVT_LE_CONN_PARAM_REQ, le_conn_param_req, sizeof(struct bt_hci_evt_le_conn_param_req)),
#if defined(CONFIG_BT_DATA_LEN_UPDATE)
    EVENT_HANDLER(BT_HCI_EVT_LE_DATA_LEN_CHANGE, le_data_len_change, sizeof(struct bt_hci_evt_le_data_len_change)),
#endif /* CONFIG_BT_DATA_LEN_UPDATE */
#if defined(CONFIG_BT_PHY_UPDATE)
    EVENT_HANDLER(BT_HCI_EVT_LE_PHY_UPDATE_COMPLETE, le_phy_update_complete, sizeof(struct bt_hci_evt_le_phy_update_complete)),
#endif /* CONFIG_BT_PHY_UPDATE */
#endif /* CONFIG_BT_CONN */
#if defined(CONFIG_BT_SMP)
    EVENT_HANDLER(BT_HCI_EVT_LE_LTK_REQUEST, le_ltk_request, sizeof(struct bt_hci_evt_le_ltk_request)),
#endif /* CONFIG_BT_SMP */
#if defined(CONFIG_BT_ECC)
    EVENT_HANDLER(BT_HCI_EVT_LE_P256_PUBLIC_KEY_COMPLETE, le_pkey_complete, sizeof(struct bt_hci_evt_le_p256_public_key_complete)),
    EVENT_HANDLER(BT_HCI_EVT_LE_GENERATE_DHKEY_COMPLETE, le_dhkey_complete, sizeof(struct bt_hci_evt_le_generate_dhkey_complete)),
#endif /* CONFIG_BT_SMP */
};

static void hci_le_meta_event(struct net_buf *buf) {
  struct bt_hci_evt_le_meta_event *evt;

  evt = net_buf_pull_mem(buf, sizeof(*evt));

  BT_DBG("subevent 0x%02x", evt->subevent);

  handle_event(evt->subevent, buf, meta_events, ARRAY_SIZE(meta_events));
}

static const struct event_handler normal_events[] = {
    EVENT_HANDLER(BT_HCI_EVT_VENDOR, hci_vendor_event, sizeof(struct bt_hci_evt_vs)),
    EVENT_HANDLER(BT_HCI_EVT_LE_META_EVENT, hci_le_meta_event, sizeof(struct bt_hci_evt_le_meta_event)),
#if defined(CONFIG_BT_BREDR)
    EVENT_HANDLER(BT_HCI_EVT_CONN_REQUEST, conn_req, sizeof(struct bt_hci_evt_conn_request)),
    EVENT_HANDLER(BT_HCI_EVT_CONN_COMPLETE, conn_complete, sizeof(struct bt_hci_evt_conn_complete)),
    EVENT_HANDLER(BT_HCI_EVT_PIN_CODE_REQ, pin_code_req, sizeof(struct bt_hci_evt_pin_code_req)),
    EVENT_HANDLER(BT_HCI_EVT_LINK_KEY_NOTIFY, link_key_notify, sizeof(struct bt_hci_evt_link_key_notify)),
    EVENT_HANDLER(BT_HCI_EVT_LINK_KEY_REQ, link_key_req, sizeof(struct bt_hci_evt_link_key_req)),
    EVENT_HANDLER(BT_HCI_EVT_IO_CAPA_RESP, io_capa_resp, sizeof(struct bt_hci_evt_io_capa_resp)),
    EVENT_HANDLER(BT_HCI_EVT_IO_CAPA_REQ, io_capa_req, sizeof(struct bt_hci_evt_io_capa_req)),
    EVENT_HANDLER(BT_HCI_EVT_SSP_COMPLETE, ssp_complete, sizeof(struct bt_hci_evt_ssp_complete)),
    EVENT_HANDLER(BT_HCI_EVT_USER_CONFIRM_REQ, user_confirm_req, sizeof(struct bt_hci_evt_user_confirm_req)),
    EVENT_HANDLER(BT_HCI_EVT_USER_PASSKEY_NOTIFY, user_passkey_notify, sizeof(struct bt_hci_evt_user_passkey_notify)),
    EVENT_HANDLER(BT_HCI_EVT_USER_PASSKEY_REQ, user_passkey_req, sizeof(struct bt_hci_evt_user_passkey_req)),
    EVENT_HANDLER(BT_HCI_EVT_INQUIRY_COMPLETE, inquiry_complete, sizeof(struct bt_hci_evt_inquiry_complete)),
    EVENT_HANDLER(BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI, inquiry_result_with_rssi, sizeof(struct bt_hci_evt_inquiry_result_with_rssi)),
    EVENT_HANDLER(BT_HCI_EVT_EXTENDED_INQUIRY_RESULT, extended_inquiry_result, sizeof(struct bt_hci_evt_extended_inquiry_result)),
    EVENT_HANDLER(BT_HCI_EVT_REMOTE_NAME_REQ_COMPLETE, remote_name_request_complete, sizeof(struct bt_hci_evt_remote_name_req_complete)),
    EVENT_HANDLER(BT_HCI_EVT_AUTH_COMPLETE, auth_complete, sizeof(struct bt_hci_evt_auth_complete)),
    EVENT_HANDLER(BT_HCI_EVT_REMOTE_FEATURES, read_remote_features_complete, sizeof(struct bt_hci_evt_remote_features)),
    EVENT_HANDLER(BT_HCI_EVT_REMOTE_EXT_FEATURES, read_remote_ext_features_complete, sizeof(struct bt_hci_evt_remote_ext_features)),
    EVENT_HANDLER(BT_HCI_EVT_ROLE_CHANGE, role_change, sizeof(struct bt_hci_evt_role_change)),
    EVENT_HANDLER(BT_HCI_EVT_SYNC_CONN_COMPLETE, synchronous_conn_complete, sizeof(struct bt_hci_evt_sync_conn_complete)),
#endif /* CONFIG_BT_BREDR */
#if defined(CONFIG_BT_CONN)
    EVENT_HANDLER(BT_HCI_EVT_DISCONN_COMPLETE, hci_disconn_complete, sizeof(struct bt_hci_evt_disconn_complete)),
#endif /* CONFIG_BT_CONN */
#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
    EVENT_HANDLER(BT_HCI_EVT_ENCRYPT_CHANGE, hci_encrypt_change, sizeof(struct bt_hci_evt_encrypt_change)),
    EVENT_HANDLER(BT_HCI_EVT_ENCRYPT_KEY_REFRESH_COMPLETE, hci_encrypt_key_refresh_complete, sizeof(struct bt_hci_evt_encrypt_key_refresh_complete)),
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */
};

static void hci_event(struct net_buf *buf) {
  struct bt_hci_evt_hdr *hdr;

  BT_ASSERT(buf->len >= sizeof(*hdr));

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  BT_DBG("event 0x%02x", hdr->evt);
  BT_ASSERT(!bt_hci_evt_is_prio(hdr->evt));

  handle_event(hdr->evt, buf, normal_events, ARRAY_SIZE(normal_events));

  net_buf_unref(buf);
}

#if (BFLB_BT_CO_THREAD)
static void send_cmd(struct net_buf *tx_buf)
#else
static void send_cmd(void)
#endif
{
  struct net_buf *buf;
  int             err;

#if (BFLB_BT_CO_THREAD)
  if (tx_buf) {
    buf = tx_buf;
  } else {
    buf = net_buf_get(&bt_dev.cmd_tx_queue, K_NO_WAIT);
  }
#else
  /* Get next command */
  BT_DBG("calling net_buf_get");
  buf = net_buf_get(&bt_dev.cmd_tx_queue, K_NO_WAIT);
#endif
  BT_ASSERT(buf);

  /* Wait until ncmd > 0 */
  BT_DBG("calling sem_take_wait");
  k_sem_take(&bt_dev.ncmd_sem, K_FOREVER);

  /* Clear out any existing sent command */
  if (bt_dev.sent_cmd) {
    BT_ERR("Uncleared pending sent_cmd");
    net_buf_unref(bt_dev.sent_cmd);
    bt_dev.sent_cmd = NULL;
  }

  bt_dev.sent_cmd = net_buf_ref(buf);

  BT_DBG("Sending command 0x%04x (buf %p) to driver", cmd(buf)->opcode, buf);

  err = bt_send(buf);
  if (err) {
    BT_ERR("Unable to send to driver (err %d)", err);
    k_sem_give(&bt_dev.ncmd_sem);
    hci_cmd_done(cmd(buf)->opcode, BT_HCI_ERR_UNSPECIFIED, buf);
    net_buf_unref(bt_dev.sent_cmd);
    bt_dev.sent_cmd = NULL;
    net_buf_unref(buf);
  }
}

#if (BFLB_BT_CO_THREAD)
static void handle_rx_queue(void) {
  struct net_buf *buf = NULL;
  buf                 = net_buf_get(&recv_fifo, K_NO_WAIT);
  if (buf) {
    BT_DBG("Calling bt_recv(%p)", buf);
    bt_recv(buf);
  }
}
#endif

#if (BFLB_BT_CO_THREAD)
static void process_events(struct k_poll_event *ev, int count, int total_evt_array_cnt)
#else
static void process_events(struct k_poll_event *ev, int count)
#endif
{
  BT_DBG("count %d", count);
#if (BFLB_BT_CO_THREAD)
  for (int ii = 0; ii < total_evt_array_cnt; ev++, ii++) {
    if (ii >= count && ii != total_evt_array_cnt - 1)
      continue;
#else
  for (; count; ev++, count--) {
#endif
    BT_DBG("ev->state %u", ev->state);
    switch (ev->state) {
    case K_POLL_STATE_SIGNALED:
      break;
    case K_POLL_STATE_FIFO_DATA_AVAILABLE:
      if (ev->tag == BT_EVENT_CMD_TX) {
#if (BFLB_BT_CO_THREAD)
        send_cmd(NULL);
#else
        send_cmd();
#endif
      }
#if (BFLB_BT_CO_THREAD)
      else if (ev->tag == BT_EVENT_RX_QUEUE) {
        handle_rx_queue();
      } else if (ev->tag == BT_EVENT_WORK_QUEUE) {
        extern void handle_work_queue(void);
        handle_work_queue();
      }
#endif
      else if (IS_ENABLED(CONFIG_BT_CONN)) {
        struct bt_conn *conn;

        if (ev->tag == BT_EVENT_CONN_TX_QUEUE) {
          conn = CONTAINER_OF(ev->fifo, struct bt_conn, tx_queue);
#if (BFLB_BT_CO_THREAD)
          bt_conn_process_tx(conn, NULL);
#else
          bt_conn_process_tx(conn);
#endif
        }
      }
      break;
    case K_POLL_STATE_NOT_READY:
      break;
    default:
      BT_WARN("Unexpected k_poll event state %u", ev->state);
      break;
    }
  }
}

#if (BFLB_BT_CO_THREAD)
static void bt_co_thread(void *p1, void *p2, void *p3) {
  static struct k_poll_event events[EV_COUNT] = {

      [0]            = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &g_work_queue_main.fifo, BT_EVENT_WORK_QUEUE),
      [1]            = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &bt_dev.cmd_tx_queue, BT_EVENT_CMD_TX),
      [EV_COUNT - 1] = K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &recv_fifo, BT_EVENT_RX_QUEUE),
  };

  BT_DBG("Started");

  while (1) {
    int ev_count, err;

    events[0].state            = K_POLL_STATE_NOT_READY;
    events[1].state            = K_POLL_STATE_NOT_READY;
    events[EV_COUNT - 1].state = K_POLL_STATE_NOT_READY;
    ev_count                   = 2;

    if (IS_ENABLED(CONFIG_BT_CONN)) {
      ev_count += bt_conn_prepare_events(&events[2]);
    }

    BT_DBG("Calling k_poll with %d events", ev_count);

    err = k_poll(events, ev_count, EV_COUNT, K_FOREVER, NULL);

    BT_ASSERT(err == 0);

    process_events(events, ev_count, EV_COUNT);

    /* Make sure we don't hog the CPU if there's all the time
     * some ready events.
     */
    k_yield();
  }
}
#else

#if defined(BFLB_BLE)
static void hci_tx_thread(void *p1)
#else
static void hci_tx_thread(void *p1, void *p2, void *p3)
#endif
{
  static struct k_poll_event events[EV_COUNT] = {
      K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE, K_POLL_MODE_NOTIFY_ONLY, &bt_dev.cmd_tx_queue, BT_EVENT_CMD_TX),
  };

  BT_DBG("Started");

  while (1) {
    int ev_count, err;

    events[0].state = K_POLL_STATE_NOT_READY;
    ev_count        = 1;

    if (IS_ENABLED(CONFIG_BT_CONN)) {
      ev_count += bt_conn_prepare_events(&events[1]);
    }

    BT_DBG("Calling k_poll with %d events", ev_count);

    err = k_poll(events, ev_count, K_FOREVER);
    BT_ASSERT(err == 0);

    process_events(events, ev_count);

    /* Make sure we don't hog the CPU if there's all the time
     * some ready events.
     */
    k_yield();
  }
}
#endif // BFLB_BT_CO_THREAD

static void read_local_ver_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_local_version_info *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  bt_dev.hci_version    = rp->hci_version;
  bt_dev.hci_revision   = sys_le16_to_cpu(rp->hci_revision);
  bt_dev.lmp_version    = rp->lmp_version;
  bt_dev.lmp_subversion = sys_le16_to_cpu(rp->lmp_subversion);
  bt_dev.manufacturer   = sys_le16_to_cpu(rp->manufacturer);
}

static void read_bdaddr_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_bd_addr *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  if (!bt_addr_cmp(&rp->bdaddr, BT_ADDR_ANY) || !bt_addr_cmp(&rp->bdaddr, BT_ADDR_NONE)) {
    BT_DBG("Controller has no public address");
    return;
  }

  bt_addr_copy(&bt_dev.id_addr[0].a, &rp->bdaddr);
  bt_dev.id_addr[0].type = BT_ADDR_LE_PUBLIC;
  bt_dev.id_count        = 1U;
}

static void read_le_features_complete(struct net_buf *buf) {
  struct bt_hci_rp_le_read_local_features *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  memcpy(bt_dev.le.features, rp->features, sizeof(bt_dev.le.features));
}

#if defined(CONFIG_BT_BREDR)
static void read_buffer_size_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_buffer_size *rp = (void *)buf->data;
  u16_t                              pkts;

  BT_DBG("status 0x%02x", rp->status);

  bt_dev.br.mtu = sys_le16_to_cpu(rp->acl_max_len);
  pkts          = sys_le16_to_cpu(rp->acl_max_num);

  BT_DBG("ACL BR/EDR buffers: pkts %u mtu %u", pkts, bt_dev.br.mtu);

  k_sem_init(&bt_dev.br.pkts, pkts, pkts);
}
#elif defined(CONFIG_BT_CONN)
static void read_buffer_size_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_buffer_size *rp = (void *)buf->data;
  u16_t                              pkts;

  BT_DBG("status 0x%02x", rp->status);

  /* If LE-side has buffers we can ignore the BR/EDR values */
  if (bt_dev.le.mtu) {
    return;
  }

  bt_dev.le.mtu = sys_le16_to_cpu(rp->acl_max_len);
  pkts          = sys_le16_to_cpu(rp->acl_max_num);

  BT_DBG("ACL BR/EDR buffers: pkts %u mtu %u", pkts, bt_dev.le.mtu);

  k_sem_init(&bt_dev.le.pkts, pkts, pkts);
}
#endif

#if defined(CONFIG_BT_CONN)
static void le_read_buffer_size_complete(struct net_buf *buf) {
  struct bt_hci_rp_le_read_buffer_size *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  bt_dev.le.mtu = sys_le16_to_cpu(rp->le_max_len);
  if (!bt_dev.le.mtu) {
    return;
  }

  BT_DBG("ACL LE buffers: pkts %u mtu %u", rp->le_max_num, bt_dev.le.mtu);

  k_sem_init(&bt_dev.le.pkts, rp->le_max_num, rp->le_max_num);
}
#endif

static void read_supported_commands_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_supported_commands *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  memcpy(bt_dev.supported_commands, rp->commands, sizeof(bt_dev.supported_commands));

  /*
   * Report "LE Read Local P-256 Public Key" and "LE Generate DH Key" as
   * supported if TinyCrypt ECC is used for emulation.
   */
  if (IS_ENABLED(CONFIG_BT_TINYCRYPT_ECC)) {
    bt_dev.supported_commands[34] |= 0x02;
    bt_dev.supported_commands[34] |= 0x04;
  }
}

static void read_local_features_complete(struct net_buf *buf) {
  struct bt_hci_rp_read_local_features *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  memcpy(bt_dev.features[0], rp->features, sizeof(bt_dev.features[0]));
}

static void le_read_supp_states_complete(struct net_buf *buf) {
  struct bt_hci_rp_le_read_supp_states *rp = (void *)buf->data;

  BT_DBG("status 0x%02x", rp->status);

  bt_dev.le.states = sys_get_le64(rp->le_states);
}

#if defined(CONFIG_BT_SMP)
static void le_read_resolving_list_size_complete(struct net_buf *buf) {
  struct bt_hci_rp_le_read_rl_size *rp = (void *)buf->data;

  BT_DBG("Resolving List size %u", rp->rl_size);

  bt_dev.le.rl_size = rp->rl_size;
}
#endif /* defined(CONFIG_BT_SMP) */

#if defined(CONFIG_BT_WHITELIST)
static void le_read_wl_size_complete(struct net_buf *buf) {
  struct bt_hci_rp_le_read_wl_size *rp = (struct bt_hci_rp_le_read_wl_size *)buf->data;

  BT_DBG("Whitelist size %u", rp->wl_size);

  bt_dev.le.wl_size = rp->wl_size;
}
#endif

static int common_init(void) {
  struct net_buf *rsp;
  int             err;

  if (!(bt_dev.drv->quirks & BT_QUIRK_NO_RESET)) {
    /* Send HCI_RESET */
    err = bt_hci_cmd_send_sync(BT_HCI_OP_RESET, NULL, &rsp);
    if (err) {
      return err;
    }
    hci_reset_complete(rsp);
    net_buf_unref(rsp);
  }

  /* Read Local Supported Features */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_LOCAL_FEATURES, NULL, &rsp);
  if (err) {
    return err;
  }
  read_local_features_complete(rsp);
  net_buf_unref(rsp);

  /* Read Local Version Information */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_LOCAL_VERSION_INFO, NULL, &rsp);
  if (err) {
    return err;
  }
  read_local_ver_complete(rsp);
  net_buf_unref(rsp);

  /* Read Bluetooth Address */
  if (!atomic_test_bit(bt_dev.flags, BT_DEV_USER_ID_ADDR)) {
    err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_BD_ADDR, NULL, &rsp);
    if (err) {
      return err;
    }
    read_bdaddr_complete(rsp);
    net_buf_unref(rsp);
  }

  /* Read Local Supported Commands */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_SUPPORTED_COMMANDS, NULL, &rsp);
  if (err) {
    return err;
  }
  read_supported_commands_complete(rsp);
  net_buf_unref(rsp);

  if (IS_ENABLED(CONFIG_BT_HOST_CRYPTO)) {
    /* Initialize the PRNG so that it is safe to use it later
     * on in the initialization process.
     */
    err = prng_init();
    if (err) {
      return err;
    }
  }

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  err = set_flow_control();
  if (err) {
    return err;
  }
#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */

  return 0;
}

static int le_set_event_mask(void) {
  struct bt_hci_cp_le_set_event_mask *cp_mask;
  struct net_buf                     *buf;
  u64_t                               mask = 0U;

  /* Set LE event mask */
  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_EVENT_MASK, sizeof(*cp_mask));
  if (!buf) {
    return -ENOBUFS;
  }

  cp_mask = net_buf_add(buf, sizeof(*cp_mask));

  mask |= BT_EVT_MASK_LE_ADVERTISING_REPORT;

  if (IS_ENABLED(CONFIG_BT_CONN)) {
    if (IS_ENABLED(CONFIG_BT_SMP) && BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
      mask |= BT_EVT_MASK_LE_ENH_CONN_COMPLETE;
    } else {
      mask |= BT_EVT_MASK_LE_CONN_COMPLETE;
    }

    mask |= BT_EVT_MASK_LE_CONN_UPDATE_COMPLETE;
    mask |= BT_EVT_MASK_LE_REMOTE_FEAT_COMPLETE;

    if (BT_FEAT_LE_CONN_PARAM_REQ_PROC(bt_dev.le.features)) {
      mask |= BT_EVT_MASK_LE_CONN_PARAM_REQ;
    }

    if (IS_ENABLED(CONFIG_BT_DATA_LEN_UPDATE) && BT_FEAT_LE_DLE(bt_dev.le.features)) {
      mask |= BT_EVT_MASK_LE_DATA_LEN_CHANGE;
    }

    if (IS_ENABLED(CONFIG_BT_PHY_UPDATE) && (BT_FEAT_LE_PHY_2M(bt_dev.le.features) || BT_FEAT_LE_PHY_CODED(bt_dev.le.features))) {
      mask |= BT_EVT_MASK_LE_PHY_UPDATE_COMPLETE;
    }
  }

  if (IS_ENABLED(CONFIG_BT_SMP) && BT_FEAT_LE_ENCR(bt_dev.le.features)) {
    mask |= BT_EVT_MASK_LE_LTK_REQUEST;
  }

  /*
   * If "LE Read Local P-256 Public Key" and "LE Generate DH Key" are
   * supported we need to enable events generated by those commands.
   */
  if (IS_ENABLED(CONFIG_BT_ECC) && (BT_CMD_TEST(bt_dev.supported_commands, 34, 1)) && (BT_CMD_TEST(bt_dev.supported_commands, 34, 2))) {
    mask |= BT_EVT_MASK_LE_P256_PUBLIC_KEY_COMPLETE;
    mask |= BT_EVT_MASK_LE_GENERATE_DHKEY_COMPLETE;
  }

  sys_put_le64(mask, cp_mask->events);
  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_EVENT_MASK, buf, NULL);
}

static int le_init(void) {
  struct bt_hci_cp_write_le_host_supp *cp_le;
  struct net_buf                      *buf, *rsp;
  int                                  err;

  /* For now we only support LE capable controllers */
  if (!BT_FEAT_LE(bt_dev.features)) {
    BT_ERR("Non-LE capable controller detected!");
    return -ENODEV;
  }

  /* Read Low Energy Supported Features */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_LOCAL_FEATURES, NULL, &rsp);
  if (err) {
    return err;
  }
  read_le_features_complete(rsp);
  net_buf_unref(rsp);

#if defined(CONFIG_BT_CONN)
  /* Read LE Buffer Size */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_BUFFER_SIZE, NULL, &rsp);
  if (err) {
    return err;
  }
  le_read_buffer_size_complete(rsp);
  net_buf_unref(rsp);
#endif

  if (BT_FEAT_BREDR(bt_dev.features)) {
    buf = bt_hci_cmd_create(BT_HCI_OP_LE_WRITE_LE_HOST_SUPP, sizeof(*cp_le));
    if (!buf) {
      return -ENOBUFS;
    }

    cp_le = net_buf_add(buf, sizeof(*cp_le));

    /* Explicitly enable LE for dual-mode controllers */
    cp_le->le    = 0x01;
    cp_le->simul = 0x00;
    err          = bt_hci_cmd_send_sync(BT_HCI_OP_LE_WRITE_LE_HOST_SUPP, buf, NULL);
    if (err) {
      return err;
    }
  }

  /* Read LE Supported States */
  if (BT_CMD_LE_STATES(bt_dev.supported_commands)) {
    err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_SUPP_STATES, NULL, &rsp);
    if (err) {
      return err;
    }
    le_read_supp_states_complete(rsp);
    net_buf_unref(rsp);
  }

  if (IS_ENABLED(CONFIG_BT_CONN) && IS_ENABLED(CONFIG_BT_DATA_LEN_UPDATE) && BT_FEAT_LE_DLE(bt_dev.le.features)) {
    struct bt_hci_cp_le_write_default_data_len *cp;
    struct bt_hci_rp_le_read_max_data_len      *rp;
    u16_t                                       tx_octets, tx_time;

    err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_MAX_DATA_LEN, NULL, &rsp);
    if (err) {
      return err;
    }

    rp        = (void *)rsp->data;
    tx_octets = sys_le16_to_cpu(rp->max_tx_octets);
    tx_time   = sys_le16_to_cpu(rp->max_tx_time);
    net_buf_unref(rsp);

    buf = bt_hci_cmd_create(BT_HCI_OP_LE_WRITE_DEFAULT_DATA_LEN, sizeof(*cp));
    if (!buf) {
      return -ENOBUFS;
    }

    cp                = net_buf_add(buf, sizeof(*cp));
    cp->max_tx_octets = sys_cpu_to_le16(tx_octets);
    cp->max_tx_time   = sys_cpu_to_le16(tx_time);

    err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_WRITE_DEFAULT_DATA_LEN, buf, NULL);
    if (err) {
      return err;
    }
  }

#if defined(CONFIG_BT_SMP)
  if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
#if defined(CONFIG_BT_PRIVACY)
    struct bt_hci_cp_le_set_rpa_timeout *cp;

    buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_RPA_TIMEOUT, sizeof(*cp));
    if (!buf) {
      return -ENOBUFS;
    }

    cp              = net_buf_add(buf, sizeof(*cp));
    cp->rpa_timeout = sys_cpu_to_le16(CONFIG_BT_RPA_TIMEOUT);
    err             = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_RPA_TIMEOUT, buf, NULL);
    if (err) {
      return err;
    }
#endif /* defined(CONFIG_BT_PRIVACY) */

    err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_RL_SIZE, NULL, &rsp);
    if (err) {
      return err;
    }
    le_read_resolving_list_size_complete(rsp);
    net_buf_unref(rsp);
  }
#endif

#if defined(CONFIG_BT_WHITELIST)
  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_READ_WL_SIZE, NULL, &rsp);
  if (err) {
    return err;
  }

  le_read_wl_size_complete(rsp);
  net_buf_unref(rsp);
#endif /* defined(CONFIG_BT_WHITELIST) */

  return le_set_event_mask();
}

#if defined(CONFIG_BT_BREDR)
static int read_ext_features(void) {
  int i;

  /* Read Local Supported Extended Features */
  for (i = 1; i < LMP_FEAT_PAGES_COUNT; i++) {
    struct bt_hci_cp_read_local_ext_features *cp;
    struct bt_hci_rp_read_local_ext_features *rp;
    struct net_buf                           *buf, *rsp;
    int                                       err;

    buf = bt_hci_cmd_create(BT_HCI_OP_READ_LOCAL_EXT_FEATURES, sizeof(*cp));
    if (!buf) {
      return -ENOBUFS;
    }

    cp       = net_buf_add(buf, sizeof(*cp));
    cp->page = i;

    err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_LOCAL_EXT_FEATURES, buf, &rsp);
    if (err) {
      return err;
    }

    rp = (void *)rsp->data;

    memcpy(&bt_dev.features[i], rp->ext_features, sizeof(bt_dev.features[i]));

    if (rp->max_page <= i) {
      net_buf_unref(rsp);
      break;
    }

    net_buf_unref(rsp);
  }

  return 0;
}

void device_supported_pkt_type(void) {
  /* Device supported features and sco packet types */
  if (BT_FEAT_HV2_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_HV2);
  }

  if (BT_FEAT_HV3_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_HV3);
  }

  if (BT_FEAT_LMP_ESCO_CAPABLE(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_EV3);
  }

  if (BT_FEAT_EV4_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_EV4);
  }

  if (BT_FEAT_EV5_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_EV5);
  }

  if (BT_FEAT_2EV3_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_2EV3);
  }

  if (BT_FEAT_3EV3_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_3EV3);
  }

  if (BT_FEAT_3SLOT_PKT(bt_dev.features)) {
    bt_dev.br.esco_pkt_type |= (HCI_PKT_TYPE_ESCO_2EV5 | HCI_PKT_TYPE_ESCO_3EV5);
  }
}

static int br_init(void) {
  struct net_buf                               *buf;
  struct bt_hci_cp_write_ssp_mode              *ssp_cp;
  struct bt_hci_cp_write_class_of_device       *cod_cp;
  struct bt_hci_cp_write_inquiry_scan_activity *inq_scan_act_cp;
  struct bt_hci_cp_write_inquiry_scan_type     *inq_scan_cp;
  struct bt_hci_cp_write_page_scan_type        *page_scan_cp;
  struct bt_hci_cp_write_inquiry_mode          *inq_cp;
  struct bt_hci_write_local_name               *name_cp;
  int                                           err;

  /* Read extended local features */
  if (BT_FEAT_EXT_FEATURES(bt_dev.features)) {
    err = read_ext_features();
    if (err) {
      return err;
    }
  }

  /* Add local supported packet types to bt_dev */
  device_supported_pkt_type();

  /* Get BR/EDR buffer size */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_BUFFER_SIZE, NULL, &buf);
  if (err) {
    return err;
  }

  read_buffer_size_complete(buf);
  net_buf_unref(buf);

  /* Set SSP mode */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_SSP_MODE, sizeof(*ssp_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  ssp_cp       = net_buf_add(buf, sizeof(*ssp_cp));
  ssp_cp->mode = 0x01;
  err          = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_SSP_MODE, buf, NULL);
  if (err) {
    return err;
  }

  /* Write Class of Device */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_CLASS_OF_DEVICE, sizeof(*cod_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cod_cp     = net_buf_add(buf, sizeof(*cod_cp));
  u8_t cd[3] = {0x14, 0x04, 0x24};
  memcpy(cod_cp->cod, cd, 3);
  err = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_CLASS_OF_DEVICE, buf, NULL);
  if (err) {
    return err;
  }

  /* Write Inquiry Scan Activity */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_INQUIRY_SCAN_ACTIVITY, sizeof(*inq_scan_act_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  inq_scan_act_cp           = net_buf_add(buf, sizeof(*inq_scan_act_cp));
  inq_scan_act_cp->interval = 0x0400;
  inq_scan_act_cp->window   = 0x0012;
  err                       = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_INQUIRY_SCAN_ACTIVITY, buf, NULL);
  if (err) {
    return err;
  }

  /* Write Inquiry Scan type with Interlaced */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_INQUIRY_SCAN_TYPE, sizeof(*inq_scan_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  inq_scan_cp       = net_buf_add(buf, sizeof(*inq_scan_cp));
  inq_scan_cp->type = 0x01;
  err               = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_INQUIRY_SCAN_TYPE, buf, NULL);
  if (err) {
    return err;
  }

  /* Write Page Scan type with Interlaced */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_PAGE_SCAN_TYPE, sizeof(*page_scan_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  page_scan_cp       = net_buf_add(buf, sizeof(*page_scan_cp));
  page_scan_cp->type = 0x01;
  err                = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_PAGE_SCAN_TYPE, buf, NULL);
  if (err) {
    return err;
  }

  /* Enable Inquiry results with RSSI or extended Inquiry */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_INQUIRY_MODE, sizeof(*inq_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  inq_cp       = net_buf_add(buf, sizeof(*inq_cp));
  inq_cp->mode = 0x02;
  err          = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_INQUIRY_MODE, buf, NULL);
  if (err) {
    return err;
  }

  /* Set local name */
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_LOCAL_NAME, sizeof(*name_cp));
  if (!buf) {
    return -ENOBUFS;
  }

  name_cp = net_buf_add(buf, sizeof(*name_cp));
  strncpy((char *)name_cp->local_name, CONFIG_BT_DEVICE_NAME, sizeof(name_cp->local_name));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_LOCAL_NAME, buf, NULL);
  if (err) {
    return err;
  }

  /* Set page timeout*/
  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_PAGE_TIMEOUT, sizeof(u16_t));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_le16(buf, CONFIG_BT_PAGE_TIMEOUT);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_PAGE_TIMEOUT, buf, NULL);
  if (err) {
    return err;
  }

  /* Enable BR/EDR SC if supported */
  if (BT_FEAT_SC(bt_dev.features)) {
    struct bt_hci_cp_write_sc_host_supp *sc_cp;

    buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_SC_HOST_SUPP, sizeof(*sc_cp));
    if (!buf) {
      return -ENOBUFS;
    }

    sc_cp             = net_buf_add(buf, sizeof(*sc_cp));
    sc_cp->sc_support = 0x01;

    err = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_SC_HOST_SUPP, buf, NULL);
    if (err) {
      return err;
    }
  }

  return 0;
}
#else
static int br_init(void) {
#if defined(CONFIG_BT_CONN)
  struct net_buf *rsp;
  int             err;

  if (bt_dev.le.mtu) {
    return 0;
  }

  /* Use BR/EDR buffer size if LE reports zero buffers */
  err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_BUFFER_SIZE, NULL, &rsp);
  if (err) {
    return err;
  }

  read_buffer_size_complete(rsp);
  net_buf_unref(rsp);
#endif /* CONFIG_BT_CONN */

  return 0;
}
#endif

static int set_event_mask(void) {
  struct bt_hci_cp_set_event_mask *ev;
  struct net_buf                  *buf;
  u64_t                            mask = 0U;

  buf = bt_hci_cmd_create(BT_HCI_OP_SET_EVENT_MASK, sizeof(*ev));
  if (!buf) {
    return -ENOBUFS;
  }

  ev = net_buf_add(buf, sizeof(*ev));

  if (IS_ENABLED(CONFIG_BT_BREDR)) {
    /* Since we require LE support, we can count on a
     * Bluetooth 4.0 feature set
     */
    mask |= BT_EVT_MASK_INQUIRY_COMPLETE;
    mask |= BT_EVT_MASK_CONN_COMPLETE;
    mask |= BT_EVT_MASK_CONN_REQUEST;
    mask |= BT_EVT_MASK_AUTH_COMPLETE;
    mask |= BT_EVT_MASK_REMOTE_NAME_REQ_COMPLETE;
    mask |= BT_EVT_MASK_REMOTE_FEATURES;
    mask |= BT_EVT_MASK_ROLE_CHANGE;
    mask |= BT_EVT_MASK_PIN_CODE_REQ;
    mask |= BT_EVT_MASK_LINK_KEY_REQ;
    mask |= BT_EVT_MASK_LINK_KEY_NOTIFY;
    mask |= BT_EVT_MASK_INQUIRY_RESULT_WITH_RSSI;
    mask |= BT_EVT_MASK_REMOTE_EXT_FEATURES;
    mask |= BT_EVT_MASK_SYNC_CONN_COMPLETE;
    mask |= BT_EVT_MASK_EXTENDED_INQUIRY_RESULT;
    mask |= BT_EVT_MASK_IO_CAPA_REQ;
    mask |= BT_EVT_MASK_IO_CAPA_RESP;
    mask |= BT_EVT_MASK_USER_CONFIRM_REQ;
    mask |= BT_EVT_MASK_USER_PASSKEY_REQ;
    mask |= BT_EVT_MASK_SSP_COMPLETE;
    mask |= BT_EVT_MASK_USER_PASSKEY_NOTIFY;
  }

  mask |= BT_EVT_MASK_HARDWARE_ERROR;
  mask |= BT_EVT_MASK_DATA_BUFFER_OVERFLOW;
  mask |= BT_EVT_MASK_LE_META_EVENT;

  if (IS_ENABLED(CONFIG_BT_CONN)) {
    mask |= BT_EVT_MASK_DISCONN_COMPLETE;
    mask |= BT_EVT_MASK_REMOTE_VERSION_INFO;
  }

  if (IS_ENABLED(CONFIG_BT_SMP) && BT_FEAT_LE_ENCR(bt_dev.le.features)) {
    mask |= BT_EVT_MASK_ENCRYPT_CHANGE;
    mask |= BT_EVT_MASK_ENCRYPT_KEY_REFRESH_COMPLETE;
  }

  sys_put_le64(mask, ev->events);
  return bt_hci_cmd_send_sync(BT_HCI_OP_SET_EVENT_MASK, buf, NULL);
}

static inline int create_random_addr(bt_addr_le_t *addr) {
  addr->type = BT_ADDR_LE_RANDOM;

  return bt_rand(addr->a.val, 6);
}

int bt_addr_le_create_nrpa(bt_addr_le_t *addr) {
  int err;

  err = create_random_addr(addr);
  if (err) {
    return err;
  }

  BT_ADDR_SET_NRPA(&addr->a);

  return 0;
}

int bt_addr_le_create_static(bt_addr_le_t *addr) {
  int err;

  err = create_random_addr(addr);
  if (err) {
    return err;
  }

  BT_ADDR_SET_STATIC(&addr->a);

  return 0;
}

#if defined(CONFIG_BT_DEBUG)
#if 0
static const char *ver_str(u8_t ver)
{
	const char * const str[] = {
		"1.0b", "1.1", "1.2", "2.0", "2.1", "3.0", "4.0", "4.1", "4.2",
		"5.0", "5.1",
	};

	if (ver < ARRAY_SIZE(str)) {
		return str[ver];
	}

	return "unknown";
}
#endif

static void bt_dev_show_info(void) {
#if 0
	int i;

	BT_INFO("Identity%s: %s", bt_dev.id_count > 1 ? "[0]" : "",
		bt_addr_le_str(&bt_dev.id_addr[0]));

	for (i = 1; i < bt_dev.id_count; i++) {
		BT_INFO("Identity[%d]: %s",
			i, bt_addr_le_str(&bt_dev.id_addr[i]));
	}

	BT_INFO("HCI: version %s (0x%02x) revision 0x%04x, manufacturer 0x%04x",
		ver_str(bt_dev.hci_version), bt_dev.hci_version,
		bt_dev.hci_revision, bt_dev.manufacturer);
	BT_INFO("LMP: version %s (0x%02x) subver 0x%04x",
		ver_str(bt_dev.lmp_version), bt_dev.lmp_version,
		bt_dev.lmp_subversion);
#endif
}
#else
static inline void bt_dev_show_info(void) {}
#endif /* CONFIG_BT_DEBUG */

#if defined(CONFIG_BT_HCI_VS_EXT)
#if defined(CONFIG_BT_DEBUG)
static const char *vs_hw_platform(u16_t platform) {
  static const char *const plat_str[] = {"reserved", "Intel Corporation", "Nordic Semiconductor", "NXP Semiconductors"};

  if (platform < ARRAY_SIZE(plat_str)) {
    return plat_str[platform];
  }

  return "unknown";
}

static const char *vs_hw_variant(u16_t platform, u16_t variant) {
  static const char *const nordic_str[] = {"reserved", "nRF51x", "nRF52x", "nRF53x"};

  if (platform != BT_HCI_VS_HW_PLAT_NORDIC) {
    return "unknown";
  }

  if (variant < ARRAY_SIZE(nordic_str)) {
    return nordic_str[variant];
  }

  return "unknown";
}

static const char *vs_fw_variant(u8_t variant) {
  static const char *const var_str[] = {
      "Standard Bluetooth controller",
      "Vendor specific controller",
      "Firmware loader",
      "Rescue image",
  };

  if (variant < ARRAY_SIZE(var_str)) {
    return var_str[variant];
  }

  return "unknown";
}
#endif /* CONFIG_BT_DEBUG */

static void hci_vs_init(void) {
  union {
    struct bt_hci_rp_vs_read_version_info       *info;
    struct bt_hci_rp_vs_read_supported_commands *cmds;
    struct bt_hci_rp_vs_read_supported_features *feat;
  } rp;
  struct net_buf *rsp;
  int             err;

  /* If heuristics is enabled, try to guess HCI VS support by looking
   * at the HCI version and identity address. We haven't tried to set
   * a static random address yet at this point, so the identity will
   * either be zeroes or a valid public address.
   */
  if (IS_ENABLED(CONFIG_BT_HCI_VS_EXT_DETECT) &&
      (bt_dev.hci_version < BT_HCI_VERSION_5_0 || (!atomic_test_bit(bt_dev.flags, BT_DEV_USER_ID_ADDR) && bt_addr_le_cmp(&bt_dev.id_addr[0], BT_ADDR_LE_ANY)))) {
    BT_WARN("Controller doesn't seem to support Zephyr vendor HCI");
    return;
  }

  err = bt_hci_cmd_send_sync(BT_HCI_OP_VS_READ_VERSION_INFO, NULL, &rsp);
  if (err) {
    BT_WARN("Vendor HCI extensions not available");
    return;
  }

#if defined(CONFIG_BT_DEBUG)
  rp.info = (void *)rsp->data;
  BT_INFO("HW Platform: %s (0x%04x)", vs_hw_platform(sys_le16_to_cpu(rp.info->hw_platform)), sys_le16_to_cpu(rp.info->hw_platform));
  BT_INFO("HW Variant: %s (0x%04x)", vs_hw_variant(sys_le16_to_cpu(rp.info->hw_platform), sys_le16_to_cpu(rp.info->hw_variant)), sys_le16_to_cpu(rp.info->hw_variant));
  BT_INFO("Firmware: %s (0x%02x) Version %u.%u Build %u", vs_fw_variant(rp.info->fw_variant), rp.info->fw_variant, rp.info->fw_version, sys_le16_to_cpu(rp.info->fw_revision),
          sys_le32_to_cpu(rp.info->fw_build));
#endif /* CONFIG_BT_DEBUG */

  net_buf_unref(rsp);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_VS_READ_SUPPORTED_COMMANDS, NULL, &rsp);
  if (err) {
    BT_WARN("Failed to read supported vendor features");
    return;
  }

  rp.cmds = (void *)rsp->data;
  memcpy(bt_dev.vs_commands, rp.cmds->commands, BT_DEV_VS_CMDS_MAX);
  net_buf_unref(rsp);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_VS_READ_SUPPORTED_FEATURES, NULL, &rsp);
  if (err) {
    BT_WARN("Failed to read supported vendor commands");
    return;
  }

  rp.feat = (void *)rsp->data;
  memcpy(bt_dev.vs_features, rp.feat->features, BT_DEV_VS_FEAT_MAX);
  net_buf_unref(rsp);
}
#endif /* CONFIG_BT_HCI_VS_EXT */

static int host_hci_init(void) {
  int err;

  err = common_init();
  if (err) {
    return err;
  }

  err = le_init();
  if (err) {
    return err;
  }

  if (BT_FEAT_BREDR(bt_dev.features)) {
    err = br_init();
    if (err) {
      return err;
    }
  } else if (IS_ENABLED(CONFIG_BT_BREDR)) {
    BT_ERR("Non-BR/EDR controller detected");
    return -EIO;
  }

  err = set_event_mask();
  if (err) {
    return err;
  }

#if defined(CONFIG_BT_HCI_VS_EXT)
  hci_vs_init();
#endif

  if (!IS_ENABLED(CONFIG_BT_SETTINGS) && !bt_dev.id_count) {
    BT_DBG("No public address. Trying to set static random.");
    err = bt_setup_id_addr();
    if (err) {
      BT_ERR("Unable to set identity address");
      return err;
    }
  }

  return 0;
}

int bt_send(struct net_buf *buf) {
  BT_DBG("buf %p len %u type %u", buf, buf->len, bt_buf_get_type(buf));

  bt_monitor_send(bt_monitor_opcode(buf), buf->data, buf->len);

  if (IS_ENABLED(CONFIG_BT_TINYCRYPT_ECC)) {
    return bt_hci_ecc_send(buf);
  }

  return bt_dev.drv->send(buf);
}

int bt_recv(struct net_buf *buf) {
  bt_monitor_send(bt_monitor_opcode(buf), buf->data, buf->len);

  BT_DBG("buf %p len %u", buf, buf->len);

  switch (bt_buf_get_type(buf)) {
#if defined(CONFIG_BT_CONN)
  case BT_BUF_ACL_IN:
#if defined(CONFIG_BT_RECV_IS_RX_THREAD)
    hci_acl(buf);
#else
    net_buf_put(&bt_dev.rx_queue, buf);
#endif
    return 0;
#endif /* BT_CONN */
  case BT_BUF_EVT:
#if defined(CONFIG_BT_RECV_IS_RX_THREAD)
    hci_event(buf);
#else
    net_buf_put(&bt_dev.rx_queue, buf);
#endif
    return 0;
  default:
    BT_ERR("Invalid buf type %u", bt_buf_get_type(buf));
    net_buf_unref(buf);
    return -EINVAL;
  }
}

static const struct event_handler prio_events[] = {
    EVENT_HANDLER(BT_HCI_EVT_CMD_COMPLETE, hci_cmd_complete, sizeof(struct bt_hci_evt_cmd_complete)),
    EVENT_HANDLER(BT_HCI_EVT_CMD_STATUS, hci_cmd_status, sizeof(struct bt_hci_evt_cmd_status)),
#if defined(CONFIG_BT_CONN)
    EVENT_HANDLER(BT_HCI_EVT_DATA_BUF_OVERFLOW, hci_data_buf_overflow, sizeof(struct bt_hci_evt_data_buf_overflow)),
    EVENT_HANDLER(BT_HCI_EVT_NUM_COMPLETED_PACKETS, hci_num_completed_packets, sizeof(struct bt_hci_evt_num_completed_packets)),
#endif /* CONFIG_BT_CONN */
};

int bt_recv_prio(struct net_buf *buf) {
  struct bt_hci_evt_hdr *hdr;

  bt_monitor_send(bt_monitor_opcode(buf), buf->data, buf->len);

  BT_ASSERT(bt_buf_get_type(buf) == BT_BUF_EVT);
  BT_ASSERT(buf->len >= sizeof(*hdr));

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  BT_ASSERT(bt_hci_evt_is_prio(hdr->evt));

  handle_event(hdr->evt, buf, prio_events, ARRAY_SIZE(prio_events));

  net_buf_unref(buf);

  return 0;
}

int bt_hci_driver_register(const struct bt_hci_driver *drv) {
  if (bt_dev.drv) {
    return -EALREADY;
  }

  if (!drv->open || !drv->send) {
    return -EINVAL;
  }

  bt_dev.drv = drv;

  BT_DBG("Registered %s", drv->name ? drv->name : "");

  bt_monitor_new_index(BT_MONITOR_TYPE_PRIMARY, drv->bus, BT_ADDR_ANY, drv->name ? drv->name : "bt0");

  return 0;
}

#if defined(CONFIG_BT_PRIVACY)
static int irk_init(void) {
#if (BFLB_FIXED_IRK)
  // use fixed irk
  memset(&bt_dev.irk[0], 0x11, 16);
  return 0;
#endif
#if defined(BFLB_BLE_PATCH_SETTINGS_LOAD)
  u8_t empty_irk[16];
  int  err;
  /*local irk has been loaded from flash in bt_enable, check if irk is null*/
  memset(empty_irk, 0, 16);
  if (memcmp(bt_dev.irk[0], empty_irk, 16) != 0)
    return 0;

  err = bt_rand(&bt_dev.irk[0], 16);

  return err;
#else
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    BT_DBG("Expecting settings to handle local IRK");
  } else {
    int err;

    err = bt_rand(&bt_dev.irk[0], 16);
    if (err) {
      return err;
    }

    BT_WARN("Using temporary IRK");
  }

  return 0;
#endif
}
#endif /* CONFIG_BT_PRIVACY */
void bt_finalize_init(void) {
  atomic_set_bit(bt_dev.flags, BT_DEV_READY);

  if (IS_ENABLED(CONFIG_BT_OBSERVER)) {
    bt_le_scan_update(false);
  }

  bt_dev_show_info();
}

#if defined(BFLB_HOST_ASSISTANT)
extern void blhast_init(struct blhast_cb *cb);
#endif
static int bt_init(void) {
  int err;
#if defined(CONFIG_BT_STACK_PTS)
  u8_t dbg_irk[16];
#endif
/*Make sure that freertos is running when set info into flash, because Semaphore is used in ef_set_env*/
#if defined(BFLB_BLE_PATCH_SETTINGS_LOAD)
  char empty_name[CONFIG_BT_DEVICE_NAME_MAX];
  memset(empty_name, 0, CONFIG_BT_DEVICE_NAME_MAX);

  if (!memcmp(bt_dev.name, empty_name, CONFIG_BT_DEVICE_NAME_MAX))
    bt_set_name(CONFIG_BT_DEVICE_NAME);
#endif

#if defined(BFLB_BLE)
  err = bl_onchiphci_interface_init();
  if (err) {
    return err;
  }
#if defined(BFLB_HOST_ASSISTANT)
  blhast_init(host_assist_cb);
#endif
#endif

  err = host_hci_init();
  if (err) {
    return err;
  }
  if (IS_ENABLED(CONFIG_BT_CONN)) {
    err = bt_conn_init();
    if (err) {
      return err;
    }
  }

#if defined(CONFIG_BT_PRIVACY)
  err = irk_init();
  if (err) {
    return err;
  }
#if defined(CONFIG_BT_STACK_PTS)
  reverse_bytearray(bt_dev.irk[0], dbg_irk, sizeof(dbg_irk));
  BT_PTS("Local IRK %s public identity bdaddr %s", bt_hex(dbg_irk, 16), bt_addr_str(&(bt_dev.id_addr[0].a)));
#endif

  k_delayed_work_init(&bt_dev.rpa_update, rpa_timeout);
#endif

#if defined(CONFIG_BT_SMP)
#if defined(BFLB_BLE_PATCH_SETTINGS_LOAD)
#if defined(CFG_SLEEP)
  if (HBN_Get_Status_Flag() == 0)
#endif
  {
    if (!bt_keys_load())
      keys_commit();
  }
#endif
#endif // CONFIG_BT_SMP
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    if (!bt_dev.id_count) {
      BT_INFO("No ID address. App must call settings_load()");
      return 0;
    }

    atomic_set_bit(bt_dev.flags, BT_DEV_PRESET_ID);
  }

  bt_finalize_init();
  return 0;
}

static void init_work(struct k_work *work) {
  int err;

  err = bt_init();
  if (ready_cb) {
    ready_cb(err);
  }
}

#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
static void hci_rx_thread(void) {
  struct net_buf *buf;

  BT_DBG("started");

  while (1) {
    BT_DBG("calling fifo_get_wait");
    buf = net_buf_get(&bt_dev.rx_queue, K_FOREVER);

    BT_DBG("buf %p type %u len %u", buf, bt_buf_get_type(buf), buf->len);

    switch (bt_buf_get_type(buf)) {
#if defined(CONFIG_BT_CONN)
    case BT_BUF_ACL_IN:
      hci_acl(buf);
      break;
#endif /* CONFIG_BT_CONN */
    case BT_BUF_EVT:
      hci_event(buf);
      break;
    default:
      BT_ERR("Unknown buf type %u", bt_buf_get_type(buf));
      net_buf_unref(buf);
      break;
    }

    /* Make sure we don't hog the CPU if the rx_queue never
     * gets empty.
     */
    k_yield();
  }
}
#endif /* !CONFIG_BT_RECV_IS_RX_THREAD */

int bt_enable(bt_ready_cb_t cb) {
  int err;

  if (!bt_dev.drv) {
    BT_ERR("No HCI driver registered");
    return -ENODEV;
  }

  if (atomic_test_and_set_bit(bt_dev.flags, BT_DEV_ENABLE)) {
    return -EALREADY;
  }

#if defined(BFLB_BLE)
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(HCI_CMD, &hci_cmd_pool, CONFIG_BT_HCI_CMD_COUNT, CMD_BUF_SIZE, NULL);
  net_buf_init(HCI_RX, &hci_rx_pool, CONFIG_BT_RX_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#else
  net_buf_init(&hci_cmd_pool, CONFIG_BT_HCI_CMD_COUNT, CMD_BUF_SIZE, NULL);
  net_buf_init(&hci_rx_pool, CONFIG_BT_RX_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#endif
#if defined(CONFIG_BT_CONN)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(NUM_COMPLETE, &num_complete_pool, 1, BT_BUF_RX_SIZE, NULL);
#else
  net_buf_init(&num_complete_pool, 1, BT_BUF_RX_SIZE, NULL);
#endif
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(ACL_IN, &acl_in_pool, CONFIG_BT_ACL_RX_COUNT, ACL_IN_SIZE, report_completed_packet);
#else
  net_buf_init(&acl_in_pool, CONFIG_BT_ACL_RX_COUNT, ACL_IN_SIZE, report_completed_packet);
#endif
#endif // CONFIG_BT_HCI_ACL_FLOW_CONTROL
#endif // CONFIG_BT_CONN
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
#if (BFLB_STATIC_ALLOC_MEM)
  net_buf_init(DISCARDABLE, &discardable_pool, CONFIG_BT_DISCARDABLE_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#else
  net_buf_init(&discardable_pool, CONFIG_BT_DISCARDABLE_BUF_COUNT, BT_BUF_RX_SIZE, NULL);
#endif
#endif
#endif

  k_work_init(&bt_dev.init, init_work);
#if (BFLB_BT_CO_THREAD)
  k_fifo_init(&g_work_queue_main.fifo, 20);
#else
  k_work_q_start();
#endif
#if !defined(CONFIG_BT_WAIT_NOP)
  k_sem_init(&bt_dev.ncmd_sem, 1, 1);
#else
  k_sem_init(&bt_dev.ncmd_sem, 0, 1);
#endif
  k_fifo_init(&bt_dev.cmd_tx_queue, 20);
#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
  k_fifo_init(&bt_dev.rx_queue, 20);
#endif

  k_sem_init(&g_poll_sem, 0, 1);
#if (BFLB_BT_CO_THREAD)
  // need to initialize recv_fifo before create bt_co_thread
  k_fifo_init(&recv_fifo, 20);
#endif
#endif

#if defined(BFLB_BLE_PATCH_SETTINGS_LOAD)
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
#if defined(CFG_SLEEP)
/* When using eflash_loader upprade firmware and softreset,
 * HBN_Get_Status_Flag() is 0x594c440b. so comment this line. */
// if( HBN_Get_Status_Flag() == 0)
#endif
    bt_local_info_load();
  }
#else
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    err = bt_settings_init();
    if (err) {
      return err;
    }
  } else {
    bt_set_name(CONFIG_BT_DEVICE_NAME);
  }
#endif

  ready_cb = cb;

  /* TX thread */
#if defined(BFLB_BLE)
#if (BFLB_BT_CO_THREAD)
  k_thread_create(&co_thread_data, "bt_co_thread", CONFIG_BT_CO_STACK_SIZE, bt_co_thread, CONFIG_BT_CO_TASK_PRIO);
#else
  k_thread_create(&tx_thread_data, "hci_tx_thread", CONFIG_BT_HCI_TX_STACK_SIZE, hci_tx_thread, CONFIG_BT_HCI_TX_PRIO);
#endif
#else
  k_thread_create(&tx_thread_data, tx_thread_stack, K_THREAD_STACK_SIZEOF(tx_thread_stack), hci_tx_thread, NULL, NULL, NULL, K_PRIO_COOP(CONFIG_BT_HCI_TX_PRIO), 0, K_NO_WAIT);
  k_thread_name_set(&tx_thread_data, "BT TX");
#endif

#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
  /* RX thread */
#if defined(BFLB_BLE)
  k_thread_create(&rx_thread_data, "hci_rx_thread", CONFIG_BT_HCI_RX_STACK_SIZE /*K_THREAD_STACK_SIZEOF(rx_thread_stack)*/, (k_thread_entry_t)hci_rx_thread, CONFIG_BT_RX_PRIO);
#else
  k_thread_create(&rx_thread_data, rx_thread_stack, K_THREAD_STACK_SIZEOF(rx_thread_stack), (k_thread_entry_t)hci_rx_thread, NULL, NULL, NULL, K_PRIO_COOP(CONFIG_BT_RX_PRIO), 0, K_NO_WAIT);
  k_thread_name_set(&rx_thread_data, "BT RX");
#endif // BFLB_BLE
#endif

  if (IS_ENABLED(CONFIG_BT_TINYCRYPT_ECC)) {
    bt_hci_ecc_init();
  }

  err = bt_dev.drv->open();
  if (err) {
    BT_ERR("HCI driver open failed (%d)", err);
    return err;
  }

#if !defined(BFLB_BLE)
  if (!cb) {
    return bt_init();
  }
#endif

#if defined(CONFIG_BLE_MULTI_ADV)
  bt_le_multi_adv_thread_init();
#endif

  k_work_submit(&bt_dev.init);
  return 0;
}

struct bt_ad {
  const struct bt_data *data;
  size_t                len;
};

#if defined(BFLB_BLE)
bool le_check_valid_scan(void) { return atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN); }
#endif

#if defined(BFLB_DISABLE_BT)
extern struct k_thread recv_thread_data;
extern struct k_thread work_q_thread;
extern struct k_fifo   free_tx;
#if defined(CONFIG_BT_SMP)
extern struct k_sem sc_local_pkey_ready;
#endif

void bt_delete_queue(struct k_fifo *queue_to_del) {
  struct net_buf *buf = NULL;
  buf                 = net_buf_get(queue_to_del, K_NO_WAIT);
  while (buf) {
    net_buf_unref(buf);
    buf = net_buf_get(queue_to_del, K_NO_WAIT);
  }

  k_queue_free(&(queue_to_del->_queue));
}

#if defined(BFLB_DYNAMIC_ALLOC_MEM) && (CONFIG_BT_CONN)
extern struct net_buf_pool acl_tx_pool;
extern struct net_buf_pool prep_pool;
#if defined(CONFIG_BT_BREDR)
extern struct net_buf_pool br_sig_pool;
extern struct net_buf_pool sdp_pool;
#if defined CONFIG_BT_HFP
extern struct net_buf_pool hf_pool;
extern struct net_buf_pool dummy_pool;
#endif
#endif
#endif

int bt_disable_action(void) {
#if defined(CONFIG_BT_PRIVACY)
  k_delayed_work_del_timer(&bt_dev.rpa_update);
#endif
#if defined(CONFIG_BT_CONN)
  bt_gatt_deinit();
#endif
  // delete queue, not delete hci_cmd_pool.free/hci_rx_pool.free/acl_tx_pool.free which store released buffers.
  bt_delete_queue(&recv_fifo);
  bt_delete_queue(&g_work_queue_main.fifo);
  bt_delete_queue(&bt_dev.cmd_tx_queue);
#if defined(CONFIG_BT_CONN)
  k_queue_free((struct k_queue *)&free_tx);
#endif
  // delete sem
  k_sem_delete(&bt_dev.ncmd_sem);
  k_sem_delete(&g_poll_sem);
#if defined(CONFIG_BT_SMP)
  k_sem_delete(&sc_local_pkey_ready);
#endif
#if defined(CONFIG_BT_CONN)
  k_sem_delete(&bt_dev.le.pkts);
#endif

  atomic_clear_bit(bt_dev.flags, BT_DEV_ENABLE);

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
  net_buf_deinit(&hci_cmd_pool);
  net_buf_deinit(&hci_rx_pool);
#if defined(CONFIG_BT_CONN)
  net_buf_deinit(&acl_tx_pool);
  net_buf_deinit(&num_complete_pool);
#if CONFIG_BT_ATT_PREPARE_COUNT > 0
  net_buf_deinit(&prep_pool);
#endif
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  net_buf_deinit(&acl_in_pool);
#endif
#if (CONFIG_BT_L2CAP_TX_FRAG_COUNT > 0)
  net_buf_deinit(&frag_pool);
#endif
#if defined(CONFIG_BT_BREDR)
  net_buf_deinit(&br_sig_pool);
  net_buf_deinit(&sdp_pool);
#if defined CONFIG_BT_HFP
  net_buf_deinit(&hf_pool);
  net_buf_deinit(&dummy_pool);
#endif
#endif
#endif // defined(CONFIG_BT_CONN)
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
  net_buf_deinit(&discardable_pool);
#endif
#endif // defined(BFLB_DYNAMIC_ALLOC_MEM)

  bl_onchiphci_interface_deinit();

  // delete task
  ble_controller_deinit();
#if (BFLB_BT_CO_THREAD)
  k_thread_delete(&co_thread_data);
#else
  k_thread_delete(&tx_thread_data);
  k_thread_delete(&work_q_thread);
  k_thread_delete(&recv_thread_data);
#endif

  return 0;
}

int bt_disable(void) {
  if (
#if defined(CONFIG_BT_CONN)
      le_check_valid_conn() ||
#endif
      atomic_test_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN) || atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -1;
  } else
    return bt_disable_action();
}
#endif

static int set_ad(u16_t hci_op, const struct bt_ad *ad, size_t ad_len) {
  struct bt_hci_cp_le_set_adv_data *set_data;
  struct net_buf                   *buf;
  int                               c, i;

  buf = bt_hci_cmd_create(hci_op, sizeof(*set_data));
  if (!buf) {
    return -ENOBUFS;
  }

  set_data = net_buf_add(buf, sizeof(*set_data));

  (void)memset(set_data, 0, sizeof(*set_data));

  for (c = 0; c < ad_len; c++) {
    const struct bt_data *data = ad[c].data;

    for (i = 0; i < ad[c].len; i++) {
      int  len  = data[i].data_len;
      u8_t type = data[i].type;

      /* Check if ad fit in the remaining buffer */
      if (set_data->len + len + 2 > 31) {
        len = 31 - (set_data->len + 2);
        if (type != BT_DATA_NAME_COMPLETE || !len) {
          net_buf_unref(buf);
          BT_ERR("Too big advertising data");
          return -EINVAL;
        }
        type = BT_DATA_NAME_SHORTENED;
      }

      set_data->data[set_data->len++] = len + 1;
      set_data->data[set_data->len++] = type;

      memcpy(&set_data->data[set_data->len], data[i].data, len);
      set_data->len += len;
    }
  }

  return bt_hci_cmd_send_sync(hci_op, buf, NULL);
}

int bt_set_name(const char *name) {
#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
  size_t len = strlen(name);
#if !defined(BFLB_BLE)
  int err;
#endif
  if (len >= sizeof(bt_dev.name)) {
    return -ENOMEM;
  }

  if (!strcmp(bt_dev.name, name)) {
    return 0;
  }

  strncpy(bt_dev.name, name, sizeof(bt_dev.name));

  /* Update advertising name if in use */
  if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING_NAME)) {
    struct bt_data data[] = {BT_DATA(BT_DATA_NAME_COMPLETE, name, strlen(name))};
    struct bt_ad   sd     = {data, ARRAY_SIZE(data)};

    set_ad(BT_HCI_OP_LE_SET_SCAN_RSP_DATA, &sd, 1);

    /* Make sure the new name is set */
    if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
      set_advertise_enable(false);
      set_advertise_enable(true);
    }
  }

  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
#if defined(BFLB_BLE)
#if defined(CFG_SLEEP)
    if (HBN_Get_Status_Flag() == 0)
#endif
      bt_settings_save_name();
#else
    err = settings_save_one("bt/name", bt_dev.name, len);
    if (err) {
      BT_WARN("Unable to store name");
    }
#endif
  }

  return 0;
#else
  return -ENOMEM;
#endif
}

const char *bt_get_name(void) {
#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
  return bt_dev.name;
#else
  return CONFIG_BT_DEVICE_NAME;
#endif
}

int bt_set_id_addr(const bt_addr_le_t *addr) {
  bt_addr_le_t non_const_addr;

  if (atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    BT_ERR("Setting identity not allowed after bt_enable()");
    return -EBUSY;
  }

  bt_addr_le_copy(&non_const_addr, addr);

  return bt_id_create(&non_const_addr, NULL);
}

void bt_id_get(bt_addr_le_t *addrs, size_t *count) {
  size_t to_copy = MIN(*count, bt_dev.id_count);

  memcpy(addrs, bt_dev.id_addr, to_copy * sizeof(bt_addr_le_t));
  *count = to_copy;
}

static int id_find(const bt_addr_le_t *addr) {
  u8_t id;

  for (id = 0U; id < bt_dev.id_count; id++) {
    if (!bt_addr_le_cmp(addr, &bt_dev.id_addr[id])) {
      return id;
    }
  }

  return -ENOENT;
}

static void id_create(u8_t id, bt_addr_le_t *addr, u8_t *irk) {
  if (addr && bt_addr_le_cmp(addr, BT_ADDR_LE_ANY)) {
    bt_addr_le_copy(&bt_dev.id_addr[id], addr);
  } else {
    bt_addr_le_t new_addr;

    do {
      bt_addr_le_create_static(&new_addr);
      /* Make sure we didn't generate a duplicate */
    } while (id_find(&new_addr) >= 0);

    bt_addr_le_copy(&bt_dev.id_addr[id], &new_addr);

    if (addr) {
      bt_addr_le_copy(addr, &bt_dev.id_addr[id]);
    }
  }

#if defined(CONFIG_BT_PRIVACY)
  {
    u8_t zero_irk[16] = {0};

    if (irk && memcmp(irk, zero_irk, 16)) {
      memcpy(&bt_dev.irk[id], irk, 16);
    } else {
      bt_rand(&bt_dev.irk[id], 16);
      if (irk) {
        memcpy(irk, &bt_dev.irk[id], 16);
      }
    }
  }
#endif
  /* Only store if stack was already initialized. Before initialization
   * we don't know the flash content, so it's potentially harmful to
   * try to write anything there.
   */
  if (IS_ENABLED(CONFIG_BT_SETTINGS) && atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    bt_settings_save_id();
  }
}

int bt_id_create(bt_addr_le_t *addr, u8_t *irk) {
  int new_id;

  if (addr && bt_addr_le_cmp(addr, BT_ADDR_LE_ANY)) {
    if (addr->type != BT_ADDR_LE_RANDOM || !BT_ADDR_IS_STATIC(&addr->a)) {
      BT_ERR("Only static random identity address supported");
      return -EINVAL;
    }

    if (id_find(addr) >= 0) {
      return -EALREADY;
    }
  }

  if (!IS_ENABLED(CONFIG_BT_PRIVACY) && irk) {
    return -EINVAL;
  }

  if (bt_dev.id_count == ARRAY_SIZE(bt_dev.id_addr)) {
    return -ENOMEM;
  }

  new_id = bt_dev.id_count++;
  if (new_id == BT_ID_DEFAULT && !atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    atomic_set_bit(bt_dev.flags, BT_DEV_USER_ID_ADDR);
  }

  id_create(new_id, addr, irk);

  return new_id;
}

int bt_id_reset(u8_t id, bt_addr_le_t *addr, u8_t *irk) {
  if (addr && bt_addr_le_cmp(addr, BT_ADDR_LE_ANY)) {
    if (addr->type != BT_ADDR_LE_RANDOM || !BT_ADDR_IS_STATIC(&addr->a)) {
      BT_ERR("Only static random identity address supported");
      return -EINVAL;
    }

    if (id_find(addr) >= 0) {
      return -EALREADY;
    }
  }

  if (!IS_ENABLED(CONFIG_BT_PRIVACY) && irk) {
    return -EINVAL;
  }

  if (id == BT_ID_DEFAULT || id >= bt_dev.id_count) {
    return -EINVAL;
  }

  if (id == bt_dev.adv_id && atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EBUSY;
  }

  if (IS_ENABLED(CONFIG_BT_CONN) && bt_addr_le_cmp(&bt_dev.id_addr[id], BT_ADDR_LE_ANY)) {
    int err;

    err = bt_unpair(id, NULL);
    if (err) {
      return err;
    }
  }

  id_create(id, addr, irk);

  return id;
}

int bt_id_delete(u8_t id) {
  if (id == BT_ID_DEFAULT || id >= bt_dev.id_count) {
    return -EINVAL;
  }

  if (!bt_addr_le_cmp(&bt_dev.id_addr[id], BT_ADDR_LE_ANY)) {
    return -EALREADY;
  }

  if (id == bt_dev.adv_id && atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EBUSY;
  }

  if (IS_ENABLED(CONFIG_BT_CONN)) {
    int err;

    err = bt_unpair(id, NULL);
    if (err) {
      return err;
    }
  }

#if defined(CONFIG_BT_PRIVACY)
  (void)memset(bt_dev.irk[id], 0, 16);
#endif
  bt_addr_le_copy(&bt_dev.id_addr[id], BT_ADDR_LE_ANY);

  if (id == bt_dev.id_count - 1) {
    bt_dev.id_count--;
  }

  if (IS_ENABLED(CONFIG_BT_SETTINGS) && atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    bt_settings_save_id();
  }

  return 0;
}

#if defined(CONFIG_BT_HCI_VS_EXT)
static uint8_t bt_read_static_addr(bt_addr_le_t *addr) {
  struct bt_hci_rp_vs_read_static_addrs *rp;
  struct net_buf                        *rsp;
  int                                    err, i;
  u8_t                                   cnt;
  if (!(bt_dev.vs_commands[1] & BIT(0))) {
    BT_WARN("Read Static Addresses command not available");
    return 0;
  }

  err = bt_hci_cmd_send_sync(BT_HCI_OP_VS_READ_STATIC_ADDRS, NULL, &rsp);
  if (err) {
    BT_WARN("Failed to read static addresses");
    return 0;
  }
  rp  = (void *)rsp->data;
  cnt = MIN(rp->num_addrs, CONFIG_BT_ID_MAX);

  for (i = 0; i < cnt; i++) {
    addr[i].type = BT_ADDR_LE_RANDOM;
    bt_addr_copy(&addr[i].a, &rp->a[i].bdaddr);
  }
  net_buf_unref(rsp);
  if (!cnt) {
    BT_WARN("No static addresses stored in controller");
  }
  return cnt;
}
#elif defined(CONFIG_BT_CTLR)
uint8_t bt_read_static_addr(bt_addr_le_t *addr);
#endif /* CONFIG_BT_HCI_VS_EXT */

int bt_setup_id_addr(void) {
#if defined(CONFIG_BT_HCI_VS_EXT) || defined(CONFIG_BT_CTLR)
  /* Only read the addresses if the user has not already configured one or
   * more identities (!bt_dev.id_count).
   */
  if (!bt_dev.id_count) {
    bt_addr_le_t addrs[CONFIG_BT_ID_MAX];

    bt_dev.id_count = bt_read_static_addr(addrs);
    if (bt_dev.id_count) {
      int i;

      for (i = 0; i < bt_dev.id_count; i++) {
        id_create(i, &addrs[i], NULL);
      }

      return set_random_address(&bt_dev.id_addr[0].a);
    }
  }
#endif
  return bt_id_create(NULL, NULL);
}

bool bt_addr_le_is_bonded(u8_t id, const bt_addr_le_t *addr) {
  if (IS_ENABLED(CONFIG_BT_SMP)) {
    struct bt_keys *keys = bt_keys_find_addr(id, addr);

    /* if there are any keys stored then device is bonded */
    return keys && keys->keys;
  } else {
    return false;
  }
}

static bool valid_adv_param(const struct bt_le_adv_param *param, bool dir_adv) {
  if (param->id >= bt_dev.id_count || !bt_addr_le_cmp(&bt_dev.id_addr[param->id], BT_ADDR_LE_ANY)) {
    return false;
  }

#if !defined(BFLB_BLE)
  if (!(param->options & BT_LE_ADV_OPT_CONNECTABLE)) {
    /*
     * BT Core 4.2 [Vol 2, Part E, 7.8.5]
     * The Advertising_Interval_Min and Advertising_Interval_Max
     * shall not be set to less than 0x00A0 (100 ms) if the
     * Advertising_Type is set to ADV_SCAN_IND or ADV_NONCONN_IND.
     */
    if (bt_dev.hci_version < BT_HCI_VERSION_5_0 && param->interval_min < 0x00a0) {
      return false;
    }
  }
#endif

  if (is_wl_empty() && ((param->options & BT_LE_ADV_OPT_FILTER_SCAN_REQ) || (param->options & BT_LE_ADV_OPT_FILTER_CONN))) {
    return false;
  }

  if ((param->options & BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY) || !dir_adv) {
    if (param->interval_min > param->interval_max ||
#if !defined(BFLB_BLE)
        param->interval_min < 0x0020 ||
#endif
        param->interval_max > 0x4000) {
      return false;
    }
  }

  return true;
}

static inline bool ad_has_name(const struct bt_data *ad, size_t ad_len) {
  int i;

  for (i = 0; i < ad_len; i++) {
    if (ad[i].type == BT_DATA_NAME_COMPLETE || ad[i].type == BT_DATA_NAME_SHORTENED) {
      return true;
    }
  }

  return false;
}

static int le_adv_update(const struct bt_data *ad, size_t ad_len, const struct bt_data *sd, size_t sd_len, bool connectable, bool use_name) {
  struct bt_ad   d[2] = {};
  struct bt_data data;
  int            err;

  d[0].data = ad;
  d[0].len  = ad_len;

  err = set_ad(BT_HCI_OP_LE_SET_ADV_DATA, d, 1);
  if (err) {
    return err;
  }

  d[0].data = sd;
  d[0].len  = sd_len;

  if (use_name) {
    const char *name;

    if (sd) {
      /* Cannot use name if name is already set */
      if (ad_has_name(sd, sd_len)) {
        return -EINVAL;
      }
    }

    name = bt_get_name();
    data = (struct bt_data)BT_DATA(BT_DATA_NAME_COMPLETE, name, strlen(name));

    d[1].data = &data;
    d[1].len  = 1;
  }

  /*
   * We need to set SCAN_RSP when enabling advertising type that
   * allows for Scan Requests.
   *
   * If any data was not provided but we enable connectable
   * undirected advertising sd needs to be cleared from values set
   * by previous calls.
   * Clearing sd is done by calling set_ad() with NULL data and
   * zero len.
   * So following condition check is unusual but correct.
   */
  if (d[0].data || d[1].data || connectable) {
    err = set_ad(BT_HCI_OP_LE_SET_SCAN_RSP_DATA, d, 2);
    if (err) {
      return err;
    }
  }

  return 0;
}

int bt_le_adv_update_data(const struct bt_data *ad, size_t ad_len, const struct bt_data *sd, size_t sd_len) {
  bool connectable, use_name;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EAGAIN;
  }

  connectable = atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING_CONNECTABLE);
  use_name    = atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING_NAME);

  return le_adv_update(ad, ad_len, sd, sd_len, connectable, use_name);
}

int bt_le_adv_start_internal(const struct bt_le_adv_param *param, const struct bt_data *ad, size_t ad_len, const struct bt_data *sd, size_t sd_len, const bt_addr_le_t *peer) {
  struct bt_hci_cp_le_set_adv_param set_param;
  const bt_addr_le_t               *id_addr;
  struct net_buf                   *buf;
  bool                              dir_adv = (peer != NULL);
  int                               err     = 0;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EAGAIN;
  }

  if (!valid_adv_param(param, dir_adv)) {
    return -EINVAL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EALREADY;
  }

  (void)memset(&set_param, 0, sizeof(set_param));

  set_param.min_interval = sys_cpu_to_le16(param->interval_min);
  set_param.max_interval = sys_cpu_to_le16(param->interval_max);
  set_param.channel_map  = adv_ch_map;

  if (bt_dev.adv_id != param->id) {
    atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);
  }

#if defined(CONFIG_BT_WHITELIST)
  if ((param->options & BT_LE_ADV_OPT_FILTER_SCAN_REQ) && (param->options & BT_LE_ADV_OPT_FILTER_CONN)) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_BOTH;
  } else if (param->options & BT_LE_ADV_OPT_FILTER_SCAN_REQ) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_SCAN_REQ;
  } else if (param->options & BT_LE_ADV_OPT_FILTER_CONN) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_CONN_IND;
  } else {
#else
  {
#endif /* defined(CONFIG_BT_WHITELIST) */
    set_param.filter_policy = BT_LE_ADV_FP_NO_WHITELIST;
  }

  /* Set which local identity address we're advertising with */
  bt_dev.adv_id = param->id;
  id_addr       = &bt_dev.id_addr[param->id];

  if (param->options & BT_LE_ADV_OPT_CONNECTABLE) {
    if (IS_ENABLED(CONFIG_BT_PRIVACY) && !(param->options & BT_LE_ADV_OPT_USE_IDENTITY)) {
#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
      if (param->addr_type == BT_ADDR_LE_RANDOM_ID)
        err = le_set_private_addr(param->id);
      else if (param->addr_type == BT_ADDR_LE_RANDOM)
        err = le_set_non_resolv_private_addr(param->id);
#else
      err = le_set_private_addr(param->id);
#endif
      if (err) {
        return err;
      }

      if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
        set_param.own_addr_type = param->addr_type;
#else
        set_param.own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
#endif
      } else {
        set_param.own_addr_type = BT_ADDR_LE_RANDOM;
      }
    } else {
      /*
       * If Static Random address is used as Identity
       * address we need to restore it before advertising
       * is enabled. Otherwise NRPA used for active scan
       * could be used for advertising.
       */
      if (id_addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&id_addr->a);
        if (err) {
          return err;
        }
      }

      set_param.own_addr_type = id_addr->type;
    }

    if (dir_adv) {
      if (param->options & BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY) {
        set_param.type = BT_LE_ADV_DIRECT_IND_LOW_DUTY;
      } else {
        set_param.type = BT_LE_ADV_DIRECT_IND;
      }

      bt_addr_le_copy(&set_param.direct_addr, peer);

      if (IS_ENABLED(CONFIG_BT_SMP) && !IS_ENABLED(CONFIG_BT_PRIVACY) && BT_FEAT_LE_PRIVACY(bt_dev.le.features) && (param->options & BT_LE_ADV_OPT_DIR_ADDR_RPA)) {
        /* This will not use RPA for our own address
         * since we have set zeroed out the local IRK.
         */
        set_param.own_addr_type |= BT_HCI_OWN_ADDR_RPA_MASK;
      }
    } else {
      set_param.type = BT_LE_ADV_IND;
    }
  } else {
    if (param->options & BT_LE_ADV_OPT_USE_IDENTITY) {
      if (id_addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&id_addr->a);
      }

      set_param.own_addr_type = id_addr->type;
    } else {
#if defined(BFLB_BLE) && !defined(CONFIG_BT_MESH)
#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
      if (param->addr_type == BT_ADDR_LE_RANDOM_ID)
        err = le_set_private_addr(param->id);
      else if (param->addr_type == BT_ADDR_LE_RANDOM)
        err = le_set_non_resolv_private_addr(param->id);
#else
// #if !defined(CONFIG_BT_ADV_WITH_PUBLIC_ADDR)
// err = le_set_private_addr(param->id);
// #endif
#endif // CONFIG_BT_STACK_PTS
#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
      set_param.own_addr_type = param->addr_type;
#else
      // set_param.own_addr_type = BT_ADDR_LE_RANDOM;
      // #if defined(CONFIG_BT_ADV_WITH_PUBLIC_ADDR)
      set_param.own_addr_type = BT_ADDR_LE_PUBLIC;
// #endif
#endif
#endif
    }

    if (err) {
      return err;
    }

    if (sd) {
      set_param.type = BT_LE_ADV_SCAN_IND;
    } else {
      set_param.type = BT_LE_ADV_NONCONN_IND;
    }
  }

#if defined(CONFIG_BT_STACK_PTS)
  if (set_param.own_addr_type == BT_ADDR_LE_PUBLIC) {
    atomic_set_bit(bt_dev.flags, BT_DEV_ADV_ADDRESS_IS_PUBLIC);
  }
#endif

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_ADV_PARAM, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_ADV_PARAM, buf, NULL);
  if (err) {
    return err;
  }

  if (!dir_adv) {
    err = le_adv_update(ad, ad_len, sd, sd_len, param->options & BT_LE_ADV_OPT_CONNECTABLE, param->options & BT_LE_ADV_OPT_USE_NAME);
    if (err) {
      return err;
    }
  }

  err = set_advertise_enable(true);
  if (err) {
    return err;
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_KEEP_ADVERTISING, !(param->options & BT_LE_ADV_OPT_ONE_TIME));

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ADVERTISING_NAME, param->options & BT_LE_ADV_OPT_USE_NAME);

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ADVERTISING_CONNECTABLE, param->options & BT_LE_ADV_OPT_CONNECTABLE);

#if defined(BFLB_HOST_ASSISTANT)
  if (!atomic_test_bit(bt_dev.flags, BT_DEV_ASSIST_RUN) && host_assist_cb && host_assist_cb->le_adv_cb)
    host_assist_cb->le_adv_cb(param, ad, ad_len, sd, sd_len);
#endif

  return 0;
}
#if defined(BFLB_BLE)
int bt_le_read_rssi(u16_t handle, int8_t *rssi) {
  struct bt_hci_cp_read_rssi *le_rssi;
  struct bt_hci_rp_read_rssi *rsp_rssi;
  struct net_buf             *buf;
  struct net_buf             *rsp;
  int                         ret;

  buf = bt_hci_cmd_create(BT_HCI_OP_READ_RSSI, sizeof(*le_rssi));
  if (!buf) {
    return -ENOBUFS;
  }

  le_rssi = net_buf_add(buf, sizeof(*le_rssi));
  memset(le_rssi, 0, sizeof(*le_rssi));

  le_rssi->handle = handle;

  ret = bt_hci_cmd_send_sync(BT_HCI_OP_READ_RSSI, buf, &rsp);

  if (ret) {
    return ret;
  }

  rsp_rssi = (struct bt_hci_rp_read_rssi *)rsp->data;
  *rssi    = rsp_rssi->rssi;

  net_buf_unref(rsp);

  return ret;
}

int set_adv_enable(bool enable) {
  int err;
  err = set_advertise_enable(enable);
  if (err) {
    return err;
  }

  return 0;
}

int set_adv_param(const struct bt_le_adv_param *param) {
  struct bt_hci_cp_le_set_adv_param set_param;
  const bt_addr_le_t               *id_addr;
  struct net_buf                   *buf;
  int                               err = 0;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EAGAIN;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EALREADY;
  }

  (void)memset(&set_param, 0, sizeof(set_param));

  set_param.min_interval = sys_cpu_to_le16(param->interval_min);
  set_param.max_interval = sys_cpu_to_le16(param->interval_max);
  set_param.channel_map  = 0x07;

  if (bt_dev.adv_id != param->id) {
    atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);
  }

#if defined(CONFIG_BT_WHITELIST)
  if ((param->options & BT_LE_ADV_OPT_FILTER_SCAN_REQ) && (param->options & BT_LE_ADV_OPT_FILTER_CONN)) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_BOTH;
  } else if (param->options & BT_LE_ADV_OPT_FILTER_SCAN_REQ) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_SCAN_REQ;
  } else if (param->options & BT_LE_ADV_OPT_FILTER_CONN) {
    set_param.filter_policy = BT_LE_ADV_FP_WHITELIST_CONN_IND;
  } else {
#else
  {
#endif /* defined(CONFIG_BT_WHITELIST) */
    set_param.filter_policy = BT_LE_ADV_FP_NO_WHITELIST;
  }

  /* Set which local identity address we're advertising with */
  bt_dev.adv_id = param->id;
  id_addr       = &bt_dev.id_addr[param->id];

  if (param->options & BT_LE_ADV_OPT_CONNECTABLE) {
    if (IS_ENABLED(CONFIG_BT_PRIVACY) && !(param->options & BT_LE_ADV_OPT_USE_IDENTITY)) {
#if defined(CONFIG_BT_STACK_PTS)
      if (param->addr_type == BT_ADDR_TYPE_RPA)
        err = le_set_private_addr(param->id);
      else if (param->addr_type == BT_ADDR_TYPE_NON_RPA)
        err = le_set_non_resolv_private_addr(param->id);
#else
      err = le_set_private_addr(param->id);
#endif
      if (err) {
        return err;
      }

      if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
#if defined(CONFIG_BT_STACK_PTS)
        if (param->addr_type == BT_ADDR_LE_PUBLIC)
          set_param.own_addr_type = BT_ADDR_LE_PUBLIC;
        if (param->addr_type == BT_ADDR_TYPE_RPA)
          set_param.own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
        else if (param->addr_type == BT_ADDR_TYPE_NON_RPA)
          set_param.own_addr_type = BT_ADDR_LE_RANDOM;
#else
        set_param.own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
#endif
      } else {
        set_param.own_addr_type = BT_ADDR_LE_RANDOM;
      }
    } else {
      /*
       * If Static Random address is used as Identity
       * address we need to restore it before advertising
       * is enabled. Otherwise NRPA used for active scan
       * could be used for advertising.
       */
      if (id_addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&id_addr->a);
        if (err) {
          return err;
        }
      }

      set_param.own_addr_type = id_addr->type;
    }

    set_param.type = BT_LE_ADV_IND;

  } else {
    if (param->options & BT_LE_ADV_OPT_USE_IDENTITY) {
      if (id_addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&id_addr->a);
      }

      set_param.own_addr_type = id_addr->type;
    } else {
#if defined(BFLB_BLE) && !defined(CONFIG_BT_MESH)
#if defined(CONFIG_BT_STACK_PTS)
      if (param->addr_type == BT_ADDR_TYPE_RPA)
        err = le_set_private_addr(param->id);
      else if (param->addr_type == BT_ADDR_TYPE_NON_RPA)
        err = le_set_non_resolv_private_addr(param->id);
#else
      err = le_set_private_addr(param->id);
#endif // CONFIG_BT_STACK_PTS
#if defined(CONFIG_BT_STACK_PTS)
      if (param->addr_type == BT_ADDR_LE_PUBLIC)
        set_param.own_addr_type = BT_ADDR_LE_PUBLIC;
      else
#endif
        set_param.own_addr_type = BT_ADDR_LE_RANDOM;
#endif
    }

    if (err) {
      return err;
    }

    set_param.type = BT_LE_ADV_NONCONN_IND;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_ADV_PARAM, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_ADV_PARAM, buf, NULL);
  if (err) {
    return err;
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_KEEP_ADVERTISING, !(param->options & BT_LE_ADV_OPT_ONE_TIME));

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ADVERTISING_NAME, param->options & BT_LE_ADV_OPT_USE_NAME);

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ADVERTISING_CONNECTABLE, param->options & BT_LE_ADV_OPT_CONNECTABLE);

  return 0;
}

int set_ad_and_rsp_d(u16_t hci_op, u8_t *data, u32_t ad_len) {
  struct net_buf *buf;
  u32_t           len;
  u8_t            size;

  if (BT_HCI_OP_LE_SET_ADV_DATA == hci_op) {
    size = sizeof(struct bt_hci_cp_le_set_adv_data);

  } else if (BT_HCI_OP_LE_SET_SCAN_RSP_DATA == hci_op) {
    size = sizeof(struct bt_hci_cp_le_set_scan_rsp_data);

  } else
    return -ENOTSUP;

  buf = bt_hci_cmd_create(hci_op, size);
  if (!buf) {
    return -ENOBUFS;
  }

  if (BT_HCI_OP_LE_SET_ADV_DATA == hci_op) {
    struct bt_hci_cp_le_set_adv_data *set_data = net_buf_add(buf, size);
    memset(set_data, 0, size);
    set_data->len = ad_len;

    if (set_data->len > 30) {
      len = 30 - (set_data->len);
      if (!len) {
        net_buf_unref(buf);
        return -ENOBUFS;
      }
    }

    memcpy(set_data->data, data, set_data->len);

  } else if (BT_HCI_OP_LE_SET_SCAN_RSP_DATA == hci_op) {
    struct bt_hci_cp_le_set_scan_rsp_data *set_data = net_buf_add(buf, size);
    memset(set_data, 0, size);

    set_data->len = ad_len;

    if (set_data->len > 30) {
      len = 30 - (set_data->len);
      if (!len) {
        net_buf_unref(buf);
        return -ENOBUFS;
      }
    }

    memcpy(set_data->data, data, set_data->len);

  } else
    return -ENOBUFS;

  return bt_hci_cmd_send_sync(hci_op, buf, NULL);
}

int set_adv_channel_map(u8_t channel) {
  int err = 0;

  if (channel >= 1 && channel <= 7) {
    adv_ch_map = channel;
  } else {
    err = -1;
  }

  return err;
}

int bt_get_local_public_address(bt_addr_le_t *adv_addr) {
  int err = 0;

  bt_addr_le_copy(adv_addr, bt_dev.id_addr);
  return err;
}

int bt_get_local_ramdon_address(bt_addr_le_t *adv_addr) {
  int err = 0;

  bt_addr_le_copy(adv_addr, &bt_dev.random_addr);
  return err;
}
#endif

int bt_le_adv_start(const struct bt_le_adv_param *param, const struct bt_data *ad, size_t ad_len, const struct bt_data *sd, size_t sd_len) {
  if (param->options & BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY) {
    return -EINVAL;
  }

  return bt_le_adv_start_internal(param, ad, ad_len, sd, sd_len, NULL);
}

int bt_le_adv_stop(void) {
  int err;

  /* Make sure advertising is not re-enabled later even if it's not
   * currently enabled (i.e. BT_DEV_ADVERTISING is not set).
   */
  atomic_clear_bit(bt_dev.flags, BT_DEV_KEEP_ADVERTISING);

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return 0;
  }

  err = set_advertise_enable(false);
  if (err) {
    return err;
  }

  if (!IS_ENABLED(CONFIG_BT_PRIVACY)) {
    /* If active scan is ongoing set NRPA */
    if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING) && atomic_test_bit(bt_dev.flags, BT_DEV_ACTIVE_SCAN)) {
      le_set_private_addr(bt_dev.adv_id);
    }
  }

  return 0;
}

#if defined(CONFIG_BLE_MULTI_ADV)
static int set_ad_data(u16_t hci_op, const uint8_t *ad_data, int ad_len) {
  struct bt_hci_cp_le_set_adv_data *set_data;
  struct net_buf                   *buf;

  buf = bt_hci_cmd_create(hci_op, sizeof(*set_data));
  if (!buf) {
    return -ENOBUFS;
  }

  if (ad_len > 31)
    return -EINVAL;

  set_data = net_buf_add(buf, sizeof(*set_data));

  memset(set_data, 0, sizeof(*set_data));
  memcpy(set_data->data, ad_data, ad_len);
  set_data->len = ad_len;

  return bt_hci_cmd_send_sync(hci_op, buf, NULL);
}

int bt_le_adv_start_instant(const struct bt_le_adv_param *param, const uint8_t *ad_data, size_t ad_len, const uint8_t *sd_data, size_t sd_len) {
  struct bt_hci_cp_le_set_adv_param set_param;
  struct net_buf                   *buf;
  const bt_addr_le_t               *id_addr;
  int                               err;

  bt_le_adv_stop();

  if (!valid_adv_param(param, false)) {
    return -EINVAL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_ADVERTISING)) {
    return -EALREADY;
  }

  err = set_ad_data(BT_HCI_OP_LE_SET_ADV_DATA, ad_data, ad_len);
  if (err) {
    return err;
  }

  /*
   * We need to set SCAN_RSP when enabling advertising type that allows
   * for Scan Requests.
   *
   * If sd was not provided but we enable connectable undirected
   * advertising sd needs to be cleared from values set by previous calls.
   * Clearing sd is done by calling set_ad() with NULL data and zero len.
   * So following condition check is unusual but correct.
   */
  if (sd_len || (param->options & BT_LE_ADV_OPT_CONNECTABLE)) {
    err = set_ad_data(BT_HCI_OP_LE_SET_SCAN_RSP_DATA, sd_data, sd_len);
    if (err) {
      return err;
    }
  }

  memset(&set_param, 0, sizeof(set_param));

  set_param.min_interval = sys_cpu_to_le16(param->interval_min);
  set_param.max_interval = sys_cpu_to_le16(param->interval_max);
  set_param.channel_map  = 0x07;

  bt_dev.adv_id = param->id;
  id_addr       = &bt_dev.id_addr[param->id];

  if (param->options & BT_LE_ADV_OPT_CONNECTABLE) {
    if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
      err = le_set_private_addr(bt_dev.adv_id);
      if (err) {
        return err;
      }

      if (BT_FEAT_LE_PRIVACY(bt_dev.le.features)) {
        set_param.own_addr_type = BT_HCI_OWN_ADDR_RPA_OR_RANDOM;
      } else {
        set_param.own_addr_type = BT_ADDR_LE_RANDOM;
      }
    } else {
      /*
       * If Static Random address is used as Identity
       * address we need to restore it before advertising
       * is enabled. Otherwise NRPA used for active scan
       * could be used for advertising.
       */
      if (id_addr->type == BT_ADDR_LE_RANDOM) {
        err = set_random_address(&id_addr->a);
        if (err) {
          return err;
        }
      }
      set_param.own_addr_type = id_addr->type;
    }

    set_param.type = BT_LE_ADV_IND;
  } else {
    if (sd_len) {
      set_param.type = BT_LE_ADV_SCAN_IND;
    } else {
      set_param.type = BT_LE_ADV_NONCONN_IND;
    }
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_ADV_PARAM, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_ADV_PARAM, buf, NULL);
  if (err) {
    return err;
  }

  err = set_advertise_enable(true);
  if (err) {
    return err;
  }

  if (!(param->options & BT_LE_ADV_OPT_ONE_TIME)) {
    atomic_set_bit(bt_dev.flags, BT_DEV_KEEP_ADVERTISING);
  }

  return 0;
}
#endif // CONFIG_BLE_MULTI_ADV

#if defined(CONFIG_BT_OBSERVER)
static bool valid_le_scan_param(const struct bt_le_scan_param *param) {
  if (param->type != BT_HCI_LE_SCAN_PASSIVE && param->type != BT_HCI_LE_SCAN_ACTIVE) {
    return false;
  }

  if (param->filter_dup & ~(BT_LE_SCAN_FILTER_DUPLICATE | BT_LE_SCAN_FILTER_WHITELIST)) {
    return false;
  }

  if (is_wl_empty() && param->filter_dup & BT_LE_SCAN_FILTER_WHITELIST) {
    return false;
  }

  if (param->interval < 0x0004 || param->interval > 0x4000) {
    return false;
  }

  if (param->window < 0x0004 || param->window > 0x4000) {
    return false;
  }

  if (param->window > param->interval) {
    return false;
  }

  return true;
}

#if defined(CONFIG_BT_STACK_PTS)
int bt_le_pts_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb, u8_t addre_type) {
  int err;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EAGAIN;
  }

  /* Check that the parameters have valid values */
  if (!valid_le_scan_param(param)) {
    return -EINVAL;
  }

  /* Return if active scan is already enabled */
  if (atomic_test_and_set_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return -EALREADY;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
    err = set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
    if (err) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
      return err;
    }
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP, param->filter_dup & BT_LE_SCAN_FILTER_DUPLICATE);

#if defined(CONFIG_BT_WHITELIST)
  atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_WL, param->filter_dup & BT_LE_SCAN_FILTER_WHITELIST);
#endif /* defined(CONFIG_BT_WHITELIST) */

  err = start_le_scan_with_isrpa(param->type, param->interval, param->window, addre_type);

  if (err) {
    atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
    return err;
  }

  scan_dev_found_cb = cb;

  return 0;
}
#endif
int bt_le_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb)

{
  int err;

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    return -EAGAIN;
  }

  /* Check that the parameters have valid values */
  if (!valid_le_scan_param(param)) {
    return -EINVAL;
  }

  /* Return if active scan is already enabled */
  if (atomic_test_and_set_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return -EALREADY;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_SCANNING)) {
    err = set_le_scan_enable(BT_HCI_LE_SCAN_DISABLE);
    if (err) {
      atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
      return err;
    }
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_FILTER_DUP, param->filter_dup & BT_LE_SCAN_FILTER_DUPLICATE);

#if defined(CONFIG_BT_WHITELIST)
  atomic_set_bit_to(bt_dev.flags, BT_DEV_SCAN_WL, param->filter_dup & BT_LE_SCAN_FILTER_WHITELIST);
#endif /* defined(CONFIG_BT_WHITELIST) */

  err = start_le_scan(param->type, param->interval, param->window);
  if (err) {
    atomic_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN);
    return err;
  }

  scan_dev_found_cb = cb;

#if defined(BFLB_HOST_ASSISTANT)
  if (!atomic_test_bit(bt_dev.flags, BT_DEV_ASSIST_RUN) && host_assist_cb && host_assist_cb->le_scan_cb)
    host_assist_cb->le_scan_cb(param, cb);
#endif

  return 0;
}

int bt_le_scan_stop(void) {
  /* Return if active scanning is already disabled */
  if (!atomic_test_and_clear_bit(bt_dev.flags, BT_DEV_EXPLICIT_SCAN)) {
    return -EALREADY;
  }

  scan_dev_found_cb = NULL;

  return bt_le_scan_update(false);
}
#endif /* CONFIG_BT_OBSERVER */

#if defined(CONFIG_BT_WHITELIST)
int bt_le_whitelist_add(const bt_addr_le_t *addr) {
  struct bt_hci_cp_le_add_dev_to_wl *cp;
  struct net_buf                    *buf;
  int                                err;

  if (!(bt_dev.le.wl_entries < bt_dev.le.wl_size)) {
    return -ENOMEM;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_ADD_DEV_TO_WL, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_le_copy(&cp->addr, addr);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_ADD_DEV_TO_WL, buf, NULL);
  if (err) {
    BT_ERR("Failed to add device to whitelist");

    return err;
  }

  bt_dev.le.wl_entries++;

  return 0;
}

int bt_le_whitelist_rem(const bt_addr_le_t *addr) {
  struct bt_hci_cp_le_rem_dev_from_wl *cp;
  struct net_buf                      *buf;
  int                                  err;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_REM_DEV_FROM_WL, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  bt_addr_le_copy(&cp->addr, addr);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_REM_DEV_FROM_WL, buf, NULL);
  if (err) {
    BT_ERR("Failed to remove device from whitelist");
    return err;
  }

  bt_dev.le.wl_entries--;
  return 0;
}

int bt_le_whitelist_clear(void) {
  int err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_CLEAR_WL, NULL, NULL);

  if (err) {
    BT_ERR("Failed to clear whitelist");
    return err;
  }

  bt_dev.le.wl_entries = 0;
  return 0;
}
#endif /* defined(CONFIG_BT_WHITELIST) */

int bt_le_set_chan_map(u8_t chan_map[5]) {
  struct bt_hci_cp_le_set_host_chan_classif *cp;
  struct net_buf                            *buf;

  if (!IS_ENABLED(CONFIG_BT_CENTRAL)) {
    return -ENOTSUP;
  }

  if (!BT_CMD_TEST(bt_dev.supported_commands, 27, 3)) {
    BT_WARN("Set Host Channel Classification command is "
            "not supported");
    return -ENOTSUP;
  }

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_HOST_CHAN_CLASSIF, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  memcpy(&cp->ch_map[0], &chan_map[0], 4);
  cp->ch_map[4] = chan_map[4] & BIT_MASK(5);

  return bt_hci_cmd_send_sync(BT_HCI_OP_LE_SET_HOST_CHAN_CLASSIF, buf, NULL);
}
#if defined(CONFIG_SET_TX_PWR)
int bt_set_tx_pwr(int8_t power) {
  struct bt_hci_cp_vs_set_tx_pwr set_param;
  struct net_buf                *buf;
  int                            err;

  if (power < 0 || power > 20)
    return BT_HCI_ERR_INVALID_PARAM;

  memset(&set_param, 0, sizeof(set_param));

  set_param.power = power;

  buf = bt_hci_cmd_create(BT_HCI_OP_VS_SET_TX_PWR, sizeof(set_param));
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_mem(buf, &set_param, sizeof(set_param));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_VS_SET_TX_PWR, buf, NULL);

  if (err) {
    return err;
  }

  return 0;
}
#endif

int bt_buf_get_rx_avail_cnt(void) { return (k_queue_get_cnt(&hci_rx_pool.free._queue) + hci_rx_pool.uninit_count); }

struct net_buf *bt_buf_get_rx(enum bt_buf_type type, s32_t timeout) {
  struct net_buf *buf;

  __ASSERT(type == BT_BUF_EVT || type == BT_BUF_ACL_IN, "Invalid buffer type requested");

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
  if (type == BT_BUF_EVT) {
    buf = net_buf_alloc(&hci_rx_pool, timeout);
  } else {
    buf = net_buf_alloc(&acl_in_pool, timeout);
  }
#else
  buf = net_buf_alloc(&hci_rx_pool, timeout);
#endif

  if (buf) {
    net_buf_reserve(buf, BT_BUF_RESERVE);
    bt_buf_set_type(buf, type);
  }

  return buf;
}

struct net_buf *bt_buf_get_cmd_complete(s32_t timeout) {
  struct net_buf *buf;
  unsigned int    key;

  key             = irq_lock();
  buf             = bt_dev.sent_cmd;
  bt_dev.sent_cmd = NULL;
  irq_unlock(key);

  BT_DBG("sent_cmd %p", buf);

  if (buf) {
    bt_buf_set_type(buf, BT_BUF_EVT);
    buf->len = 0U;
    net_buf_reserve(buf, BT_BUF_RESERVE);

    return buf;
  }

  return bt_buf_get_rx(BT_BUF_EVT, timeout);
}

struct net_buf *bt_buf_get_evt(u8_t evt, bool discardable, s32_t timeout) {
  switch (evt) {
#if defined(CONFIG_BT_CONN)
  case BT_HCI_EVT_NUM_COMPLETED_PACKETS: {
    struct net_buf *buf;

    buf = net_buf_alloc(&num_complete_pool, timeout);
    if (buf) {
      net_buf_reserve(buf, BT_BUF_RESERVE);
      bt_buf_set_type(buf, BT_BUF_EVT);
    }

    return buf;
  }
#endif /* CONFIG_BT_CONN */
  case BT_HCI_EVT_CMD_COMPLETE:
  case BT_HCI_EVT_CMD_STATUS:
    return bt_buf_get_cmd_complete(timeout);
  default:
#if defined(CONFIG_BT_DISCARDABLE_BUF_COUNT)
    if (discardable) {
      struct net_buf *buf;

      buf = net_buf_alloc(&discardable_pool, timeout);
      if (buf) {
        net_buf_reserve(buf, BT_BUF_RESERVE);
        bt_buf_set_type(buf, BT_BUF_EVT);
      }

      return buf;
    }
#endif /* CONFIG_BT_DISCARDABLE_BUF_COUNT */

    return bt_buf_get_rx(BT_BUF_EVT, timeout);
  }
}

#if defined(CONFIG_BT_BREDR)
static int br_start_inquiry(const struct bt_br_discovery_param *param) {
  const u8_t                iac[3] = {0x33, 0x8b, 0x9e};
  struct bt_hci_op_inquiry *cp;
  struct net_buf           *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_INQUIRY, sizeof(*cp));
  if (!buf) {
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));

  cp->length  = param->length;
  cp->num_rsp = 0xff; /* we limit discovery only by time */

  memcpy(cp->lap, iac, 3);
  if (param->limited) {
    cp->lap[0] = 0x00;
  }

  return bt_hci_cmd_send_sync(BT_HCI_OP_INQUIRY, buf, NULL);
}

static bool valid_br_discov_param(const struct bt_br_discovery_param *param, size_t num_results) {
  if (!num_results || num_results > 255) {
    return false;
  }

  if (!param->length || param->length > 0x30) {
    return false;
  }

  return true;
}

int bt_br_discovery_start(const struct bt_br_discovery_param *param, struct bt_br_discovery_result *results, size_t cnt, bt_br_discovery_cb_t cb) {
  int err;

  BT_DBG("");

  if (!valid_br_discov_param(param, cnt)) {
    return -EINVAL;
  }

  if (atomic_test_bit(bt_dev.flags, BT_DEV_INQUIRY)) {
    return -EALREADY;
  }

  err = br_start_inquiry(param);
  if (err) {
    return err;
  }

  atomic_set_bit(bt_dev.flags, BT_DEV_INQUIRY);

  (void)memset(results, 0, sizeof(*results) * cnt);

  discovery_cb            = cb;
  discovery_results       = results;
  discovery_results_size  = cnt;
  discovery_results_count = 0;

  return 0;
}

int bt_br_discovery_stop(void) {
  int err;
  int i;

  BT_DBG("");

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_INQUIRY)) {
    return -EALREADY;
  }

  err = bt_hci_cmd_send_sync(BT_HCI_OP_INQUIRY_CANCEL, NULL, NULL);
  if (err) {
    return err;
  }

  for (i = 0; i < discovery_results_count; i++) {
    struct discovery_priv               *priv;
    struct bt_hci_cp_remote_name_cancel *cp;
    struct net_buf                      *buf;

    priv = (struct discovery_priv *)&discovery_results[i]._priv;

    if (!priv->resolving) {
      continue;
    }

    buf = bt_hci_cmd_create(BT_HCI_OP_REMOTE_NAME_CANCEL, sizeof(*cp));
    if (!buf) {
      continue;
    }

    cp = net_buf_add(buf, sizeof(*cp));
    bt_addr_copy(&cp->bdaddr, &discovery_results[i].addr);

    bt_hci_cmd_send_sync(BT_HCI_OP_REMOTE_NAME_CANCEL, buf, NULL);
  }

  atomic_clear_bit(bt_dev.flags, BT_DEV_INQUIRY);

  discovery_cb            = NULL;
  discovery_results       = NULL;
  discovery_results_size  = 0;
  discovery_results_count = 0;

  return 0;
}

static int write_scan_enable(u8_t scan) {
  struct net_buf *buf;
  int             err;

  BT_DBG("type %u", scan);

  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_SCAN_ENABLE, 1);
  if (!buf) {
    return -ENOBUFS;
  }

  net_buf_add_u8(buf, scan);
  err = bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_SCAN_ENABLE, buf, NULL);
  if (err) {
    return err;
  }

  atomic_set_bit_to(bt_dev.flags, BT_DEV_ISCAN, (scan & BT_BREDR_SCAN_INQUIRY));
  atomic_set_bit_to(bt_dev.flags, BT_DEV_PSCAN, (scan & BT_BREDR_SCAN_PAGE));

  return 0;
}

int bt_br_set_connectable(bool enable) {
  if (enable) {
    if (atomic_test_bit(bt_dev.flags, BT_DEV_PSCAN)) {
      return -EALREADY;
    } else {
      return write_scan_enable(BT_BREDR_SCAN_PAGE);
    }
  } else {
    if (!atomic_test_bit(bt_dev.flags, BT_DEV_PSCAN)) {
      return -EALREADY;
    } else {
      return write_scan_enable(BT_BREDR_SCAN_DISABLED);
    }
  }
}

int bt_br_set_discoverable(bool enable) {
  if (enable) {
    if (atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
      return -EALREADY;
    }

    if (!atomic_test_bit(bt_dev.flags, BT_DEV_PSCAN)) {
      return -EPERM;
    }

    return write_scan_enable(BT_BREDR_SCAN_INQUIRY | BT_BREDR_SCAN_PAGE);
  } else {
    if (!atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
      return -EALREADY;
    }

    return write_scan_enable(BT_BREDR_SCAN_PAGE);
  }
}

int bt_br_write_eir(u8_t rec, u8_t *data) {
  struct bt_hci_cp_write_ext_inquiry_resp *ext_ir;
  struct net_buf                          *buf;

  buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_EXT_INQUIRY_RESP, sizeof(*ext_ir));
  if (!buf) {
    return -ENOBUFS;
  }

  ext_ir = net_buf_add(buf, sizeof(*ext_ir));
  memset(ext_ir, 0, sizeof(*ext_ir));

  ext_ir->rec = rec;
  memcpy(ext_ir->eir, data, strlen((char *)data));

  return bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_EXT_INQUIRY_RESP, buf, NULL);
}

#endif /* CONFIG_BT_BREDR */

#if defined(CONFIG_BT_ECC)
int bt_pub_key_gen(struct bt_pub_key_cb *new_cb) {
  int err;

  /*
   * We check for both "LE Read Local P-256 Public Key" and
   * "LE Generate DH Key" support here since both commands are needed for
   * ECC support. If "LE Generate DH Key" is not supported then there
   * is no point in reading local public key.
   */
  if (!BT_CMD_TEST(bt_dev.supported_commands, 34, 1) || !BT_CMD_TEST(bt_dev.supported_commands, 34, 2)) {
    BT_WARN("ECC HCI commands not available");
    return -ENOTSUP;
  }

#if defined(BFLB_BLE_PATCH_AVOID_DUPLI_PUBKEY_CB)
  struct bt_pub_key_cb *cb;
  struct bt_pub_key_cb *valid_cb;
  bool                  existed = false;

  if (pub_key_cb) {
    cb       = pub_key_cb;
    valid_cb = cb;
    while (cb) {
      if (new_cb->func == cb->func) {
        existed = true;
        break;
      }

      valid_cb = cb;
      cb       = cb->_next;
    }

    if (!existed) {
      valid_cb->_next = new_cb;
    }
  } else {
    pub_key_cb = new_cb;
  }
#else
  new_cb->_next = pub_key_cb;
  pub_key_cb    = new_cb;
#endif

  if (atomic_test_and_set_bit(bt_dev.flags, BT_DEV_PUB_KEY_BUSY)) {
    return 0;
  }

  atomic_clear_bit(bt_dev.flags, BT_DEV_HAS_PUB_KEY);

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_P256_PUBLIC_KEY, NULL, NULL);
  if (err) {
    BT_ERR("Sending LE P256 Public Key command failed");
    atomic_clear_bit(bt_dev.flags, BT_DEV_PUB_KEY_BUSY);
    pub_key_cb = NULL;
    return err;
  }

  return 0;
}

const u8_t *bt_pub_key_get(void) {
  if (atomic_test_bit(bt_dev.flags, BT_DEV_HAS_PUB_KEY)) {
    return pub_key;
  }

  return NULL;
}

int bt_dh_key_gen(const u8_t remote_pk[64], bt_dh_key_cb_t cb) {
  struct bt_hci_cp_le_generate_dhkey *cp;
  struct net_buf                     *buf;
  int                                 err;

  if (dh_key_cb || atomic_test_bit(bt_dev.flags, BT_DEV_PUB_KEY_BUSY)) {
    return -EBUSY;
  }

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_HAS_PUB_KEY)) {
    return -EADDRNOTAVAIL;
  }

  dh_key_cb = cb;

  buf = bt_hci_cmd_create(BT_HCI_OP_LE_GENERATE_DHKEY, sizeof(*cp));
  if (!buf) {
    dh_key_cb = NULL;
    return -ENOBUFS;
  }

  cp = net_buf_add(buf, sizeof(*cp));
  memcpy(cp->key, remote_pk, sizeof(cp->key));

  err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_GENERATE_DHKEY, buf, NULL);
  if (err) {
    dh_key_cb = NULL;
    return err;
  }

  return 0;
}
#endif /* CONFIG_BT_ECC */

#if defined(CONFIG_BT_BREDR)
int bt_br_oob_get_local(struct bt_br_oob *oob) {
  bt_addr_copy(&oob->addr, &bt_dev.id_addr[0].a);

  return 0;
}
#endif /* CONFIG_BT_BREDR */

int bt_le_oob_get_local(u8_t id, struct bt_le_oob *oob) {
  int err;

  if (id >= CONFIG_BT_ID_MAX) {
    return -EINVAL;
  }

  if (IS_ENABLED(CONFIG_BT_PRIVACY)) {
    /* Invalidate RPA so a new one is generated */
    atomic_clear_bit(bt_dev.flags, BT_DEV_RPA_VALID);

    err = le_set_private_addr(id);
    if (err) {
      return err;
    }

    bt_addr_le_copy(&oob->addr, &bt_dev.random_addr);
  } else {
    bt_addr_le_copy(&oob->addr, &bt_dev.id_addr[id]);
  }

  if (IS_ENABLED(CONFIG_BT_SMP)) {
    err = bt_smp_le_oob_generate_sc_data(&oob->le_sc_data);
    if (err) {
      return err;
    }
  }

  return 0;
}

#if defined(CONFIG_BT_SMP)
int bt_le_oob_set_sc_data(struct bt_conn *conn, const struct bt_le_oob_sc_data *oobd_local, const struct bt_le_oob_sc_data *oobd_remote) {
  return bt_smp_le_oob_set_sc_data(conn, oobd_local, oobd_remote);
}

int bt_le_oob_get_sc_data(struct bt_conn *conn, const struct bt_le_oob_sc_data **oobd_local, const struct bt_le_oob_sc_data **oobd_remote) {
  return bt_smp_le_oob_get_sc_data(conn, oobd_local, oobd_remote);
}
#endif

#if defined(BFLB_RELEASE_CMD_SEM_IF_CONN_DISC)
void hci_release_conn_related_cmd(void) {
  u16_t opcode;

  (void)opcode;

  if (bt_dev.sent_cmd) {
    opcode = cmd(bt_dev.sent_cmd)->opcode;
    switch (opcode) {
    case BT_HCI_OP_LE_SET_DATA_LEN:
    case BT_HCI_OP_LE_READ_REMOTE_FEATURES:
    case BT_HCI_OP_LE_SET_DEFAULT_PHY:
    case BT_HCI_OP_LE_SET_PHY:
    case BT_HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY:
    case BT_HCI_OP_LE_CONN_PARAM_REQ_REPLY:
    case BT_HCI_OP_LE_LTK_REQ_NEG_REPLY:
    case BT_HCI_OP_LE_LTK_REQ_REPLY: {
      k_sem_give(&bt_dev.ncmd_sem);
      hci_cmd_done(opcode, BT_HCI_ERR_UNSPECIFIED, bt_dev.sent_cmd);
      net_buf_unref(bt_dev.sent_cmd);
      bt_dev.sent_cmd = NULL;
    } break;
    default:
      break;
    }
  }
}
#endif

#if defined(BFLB_HOST_ASSISTANT)
#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
int bt_set_flow_control(void) { return set_flow_control(); }
#endif
int bt_set_event_mask(void) { return set_event_mask(); }

int bt_le_set_event_mask(void) { return le_set_event_mask(); }

void bt_hci_reset_complete(struct net_buf *buf) { hci_reset_complete(buf); }

void bt_register_host_assist_cb(struct blhast_cb *cb) { host_assist_cb = cb; }
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hci_core.h
================================================
/* hci_core.h - Bluetooth HCI core access */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* LL connection parameters */
#define LE_CONN_LATENCY 0x0000
#define LE_CONN_TIMEOUT 0x002a

#if defined(CONFIG_BT_BREDR)
#define LMP_FEAT_PAGES_COUNT 3
#else
#define LMP_FEAT_PAGES_COUNT 1
#endif

/* SCO  settings */
#define BT_VOICE_CVSD_16BIT 0x0060
#define BT_VOICE_MSBC_16BIT 0x0063

#if (BFLB_BT_CO_THREAD)
enum {
    BT_CMD_SYNC_NONE = 0,
    BT_CMD_SYNC_TX = 1,
    BT_CMD_SYNC_TX_DONE = 2
};
#endif

/* k_poll event tags */
enum {
    BT_EVENT_CMD_TX,
    BT_EVENT_CONN_TX_QUEUE,
#if (BFLB_BT_CO_THREAD)
    BT_EVENT_RX_QUEUE,
    BT_EVENT_WORK_QUEUE,
#endif
};

/* bt_dev flags: the flags defined here represent BT controller state */
enum {
    BT_DEV_ENABLE,
    BT_DEV_READY,
    BT_DEV_PRESET_ID,
    BT_DEV_USER_ID_ADDR,
    BT_DEV_HAS_PUB_KEY,
    BT_DEV_PUB_KEY_BUSY,

    BT_DEV_ADVERTISING,
    BT_DEV_ADVERTISING_NAME,
    BT_DEV_ADVERTISING_CONNECTABLE,
    BT_DEV_KEEP_ADVERTISING,
    BT_DEV_SCANNING,
    BT_DEV_EXPLICIT_SCAN,
    BT_DEV_ACTIVE_SCAN,
    BT_DEV_SCAN_FILTER_DUP,
    BT_DEV_SCAN_WL,
    BT_DEV_AUTO_CONN,

    BT_DEV_RPA_VALID,

    BT_DEV_ID_PENDING,

#if defined(CONFIG_BT_BREDR)
    BT_DEV_ISCAN,
    BT_DEV_PSCAN,
    BT_DEV_INQUIRY,
#endif /* CONFIG_BT_BREDR */

#if defined(CONFIG_BT_STACK_PTS)
    BT_DEV_ADV_ADDRESS_IS_PUBLIC,
#endif

#if defined(CONFIG_AUTO_PTS)
    BT_DEV_SETTED_NON_RESOLV_ADDR, //The non-reslovable address have been set.
#endif

#if defined(BFLB_HOST_ASSISTANT)
    BT_DEV_ASSIST_RUN,
#endif

    /* Total number of flags - must be at the end of the enum */
    BT_DEV_NUM_FLAGS,
};

/* Flags which should not be cleared upon HCI_Reset */
#define BT_DEV_PERSISTENT_FLAGS (BIT(BT_DEV_ENABLE) |    \
                                 BIT(BT_DEV_PRESET_ID) | \
                                 BIT(BT_DEV_USER_ID_ADDR))

struct bt_dev_le {
    /* LE features */
    u8_t features[8];
    /* LE states */
    u64_t states;

#if defined(CONFIG_BT_CONN)
    /* Controller buffer information */
    u16_t mtu;
    struct k_sem pkts;
#endif /* CONFIG_BT_CONN */

#if defined(CONFIG_BT_SMP)
    /* Size of the the controller resolving list */
    u8_t rl_size;
    /* Number of entries in the resolving list. rl_entries > rl_size
	 * means that host-side resolving is used.
	 */
    u8_t rl_entries;
#endif /* CONFIG_BT_SMP */

#if defined(CONFIG_BT_WHITELIST)
    /* Size of the controller whitelist. */
    u8_t wl_size;
    /* Number of entries in the resolving list. */
    u8_t wl_entries;
#endif /* CONFIG_BT_WHITELIST */
};

#if defined(CONFIG_BT_BREDR)
struct bt_dev_br {
    /* Max controller's acceptable ACL packet length */
    u16_t mtu;
    struct k_sem pkts;
    u16_t esco_pkt_type;
};
#endif

/* The theoretical max for these is 8 and 64, but there's no point
 * in allocating the full memory if we only support a small subset.
 * These values must be updated whenever the host implementation is
 * extended beyond the current values.
 */
#define BT_DEV_VS_FEAT_MAX 1
#define BT_DEV_VS_CMDS_MAX 2

/* State tracking for the local Bluetooth controller */
struct bt_dev {
    /* Local Identity Address(es) */
    bt_addr_le_t id_addr[CONFIG_BT_ID_MAX];
    u8_t id_count;

    /* ID Address used for advertising */
    u8_t adv_id;

    /* Current local Random Address */
    bt_addr_le_t random_addr;

    /* Controller version & manufacturer information */
    u8_t hci_version;
    u8_t lmp_version;
    u16_t hci_revision;
    u16_t lmp_subversion;
    u16_t manufacturer;

    /* LMP features (pages 0, 1, 2) */
    u8_t features[LMP_FEAT_PAGES_COUNT][8];

    /* Supported commands */
    u8_t supported_commands[64];

#if defined(CONFIG_BT_HCI_VS_EXT)
    /* Vendor HCI support */
    u8_t vs_features[BT_DEV_VS_FEAT_MAX];
    u8_t vs_commands[BT_DEV_VS_CMDS_MAX];
#endif

    struct k_work init;

    ATOMIC_DEFINE(flags, BT_DEV_NUM_FLAGS);

    /* LE controller specific features */
    struct bt_dev_le le;

#if defined(CONFIG_BT_BREDR)
    /* BR/EDR controller specific features */
    struct bt_dev_br br;
#endif

    /* Number of commands controller can accept */
    struct k_sem ncmd_sem;

    /* Last sent HCI command */
    struct net_buf *sent_cmd;

#if !defined(CONFIG_BT_RECV_IS_RX_THREAD)
    /* Queue for incoming HCI events & ACL data */
    struct k_fifo rx_queue;
#endif

    /* Queue for outgoing HCI commands */
    struct k_fifo cmd_tx_queue;

    /* Registered HCI driver */
    const struct bt_hci_driver *drv;

#if defined(CONFIG_BT_PRIVACY)
    /* Local Identity Resolving Key */
    u8_t irk[CONFIG_BT_ID_MAX][16];

    /* Work used for RPA rotation */
    struct k_delayed_work rpa_update;
#endif

    /* Local Name */
#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
    char name[CONFIG_BT_DEVICE_NAME_MAX + 1];
#endif
};

#if defined(CONFIG_BT_STACK_PTS)
typedef enum __packed {
    dir_connect_req = 0x01, /*Send a direct connection require while the Lower test enters direct mode .*/

    ad_type_service_uuid = 0x02,
    ad_type_local_name = 0x03,
    ad_type_flags = 0x04,
    ad_type_manu_data = 0x05,
    ad_type_tx_power_level = 0x06,
    ad_type_service_data = 0x07,
    ad_type_appearance = 0x08,

    gatt_discover_chara = 0x09,
    gatt_exec_write_req = 0x0a,
    gatt_cancel_write_req = 0x0b,
    att_read_by_group_type_ind = 0x0c, /* CASE : GATT/SR/GAD/BV-01-C. Indicate PTS sends a GATT discover all primary services request to iut */
    att_find_by_type_value_ind = 0x0d, /* CASE : GATT/SR/GAD/BV-02-C. Indicate PTS sends a request to iut for discover it contains Primary Services by Service UUID */
    att_read_by_type_ind = 0x0e,       /* CASE : GATT/SR/GAD/BV-04-C. Indicate PTS sends a request to iut for discover all characteristics of a specified service.*/

    own_addr_type_random = 0x0f
} event_id;

#endif

extern struct bt_dev bt_dev;
#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
extern const struct bt_conn_auth_cb *bt_auth;
#endif /* CONFIG_BT_SMP || CONFIG_BT_BREDR */

bool bt_le_conn_params_valid(const struct bt_le_conn_param *param);

int bt_le_scan_update(bool fast_scan);

int bt_le_auto_conn(const struct bt_le_conn_param *conn_param);
int bt_le_auto_conn_cancel(void);

bool bt_addr_le_is_bonded(u8_t id, const bt_addr_le_t *addr);
const bt_addr_le_t *bt_lookup_id_addr(u8_t id, const bt_addr_le_t *addr);

int bt_send(struct net_buf *buf);

/* Don't require everyone to include keys.h */
struct bt_keys;
void bt_id_add(struct bt_keys *keys);
void bt_id_del(struct bt_keys *keys);

int bt_setup_id_addr(void);
void bt_finalize_init(void);

int bt_le_adv_start_internal(const struct bt_le_adv_param *param,
                             const struct bt_data *ad, size_t ad_len,
                             const struct bt_data *sd, size_t sd_len,
                             const bt_addr_le_t *peer);
#if defined(CONFIG_BLE_MULTI_ADV)
int bt_le_adv_start_instant(const struct bt_le_adv_param *param,
                            const uint8_t *ad_data, size_t ad_len,
                            const uint8_t *sd_data, size_t sd_len);
#endif

#if defined(BFLB_BLE)

int bt_le_read_rssi(u16_t handle, int8_t *rssi);
int set_ad_and_rsp_d(u16_t hci_op, u8_t *data, u32_t ad_len);
int set_adv_enable(bool enable);
int set_adv_param(const struct bt_le_adv_param *param);
int set_adv_channel_map(u8_t channel);
int bt_get_local_public_address(bt_addr_le_t *adv_addr);
int bt_get_local_ramdon_address(bt_addr_le_t *adv_addr);
int bt_le_set_data_len(struct bt_conn *conn, u16_t tx_octets, u16_t tx_time);
int hci_le_set_phy(struct bt_conn *conn, uint8_t all_phys,
                   uint8_t pref_tx_phy, uint8_t pref_rx_phy, uint8_t phy_opts);
int hci_le_set_default_phy(u8_t default_phy);

#if defined(CONFIG_SET_TX_PWR)
int bt_set_tx_pwr(int8_t power);
#endif

#if defined(BFLB_HOST_ASSISTANT)
struct blhast_cb {
    void (*le_scan_cb)(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb);
    void (*le_adv_cb)(const struct bt_le_adv_param *param, const struct bt_data *ad,
                      size_t ad_len, const struct bt_data *sd, size_t sd_len);
};
int bt_set_flow_control(void);
int bt_set_event_mask(void);
int bt_le_set_event_mask(void);
void bt_hci_reset_complete(struct net_buf *buf);
void bt_register_host_assist_cb(struct blhast_cb *cb);
#endif

typedef void (*bredr_name_callback)(const char *name);
int remote_name_req(const bt_addr_t *addr, bredr_name_callback cb);

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hci_ecc.c
================================================
/**
 * @file hci_ecc.c
 * HCI ECC emulation
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

#include <../include/bluetooth/crypto.h>
#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_CORE)
#include "log.h"

#include "hci_ecc.h"
#ifdef CONFIG_BT_HCI_RAW
#include "hci_raw_internal.h"
#include 
#else
#include "hci_core.h"
#endif

static struct k_thread ecc_thread_data;
#if !defined(BFLB_BLE)
static BT_STACK_NOINIT(ecc_thread_stack, 1024);
#endif

/* based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */
static const u32_t debug_private_key[8] = {0xcd3c1abd, 0x5899b8a6, 0xeb40b799, 0x4aff607b, 0xd2103f50, 0x74c9b3e3, 0xa3c55f38, 0x3f49f6d4};

#if defined(CONFIG_BT_USE_DEBUG_KEYS)
static const u8_t debug_public_key[64] = {0xe6, 0x9d, 0x35, 0x0e, 0x48, 0x01, 0x03, 0xcc, 0xdb, 0xfd, 0xf4, 0xac, 0x11, 0x91, 0xf4, 0xef, 0xb9, 0xa5, 0xf9, 0xe9, 0xa7, 0x83,
                                          0x2c, 0x5e, 0x2c, 0xbe, 0x97, 0xf2, 0xd2, 0x03, 0xb0, 0x20, 0x8b, 0xd2, 0x89, 0x15, 0xd0, 0x8e, 0x1c, 0x74, 0x24, 0x30, 0xed, 0x8f,
                                          0xc2, 0x45, 0x63, 0x76, 0x5c, 0x15, 0x52, 0x5a, 0xbf, 0x9a, 0x32, 0x63, 0x6d, 0xeb, 0x2a, 0x65, 0x49, 0x9c, 0x80, 0xdc};
#endif

enum {
  PENDING_PUB_KEY,
  PENDING_DHKEY,

  /* Total number of flags - must be at the end of the enum */
  NUM_FLAGS,
};

static ATOMIC_DEFINE(flags, NUM_FLAGS);

static K_SEM_DEFINE(cmd_sem, 0, 1);

static struct {
  u8_t private_key[32];

  union {
    u8_t pk[64];
    u8_t dhkey[32];
  };
} ecc;

static void send_cmd_status(u16_t opcode, u8_t status) {
  struct bt_hci_evt_cmd_status *evt;
  struct bt_hci_evt_hdr        *hdr;
  struct net_buf               *buf;

  BT_DBG("opcode %x status %x", opcode, status);

  buf = bt_buf_get_evt(BT_HCI_EVT_CMD_STATUS, false, K_FOREVER);
  bt_buf_set_type(buf, BT_BUF_EVT);

  hdr      = net_buf_add(buf, sizeof(*hdr));
  hdr->evt = BT_HCI_EVT_CMD_STATUS;
  hdr->len = sizeof(*evt);

  evt         = net_buf_add(buf, sizeof(*evt));
  evt->ncmd   = 1U;
  evt->opcode = sys_cpu_to_le16(opcode);
  evt->status = status;

  bt_recv_prio(buf);
}

static u8_t generate_keys(void) {
#if !defined(CONFIG_BT_USE_DEBUG_KEYS)
  do {
    int rc;

    rc = uECC_make_key(ecc.pk, ecc.private_key, &curve_secp256r1);
    if (rc == TC_CRYPTO_FAIL) {
      BT_ERR("Failed to create ECC public/private pair");
      return BT_HCI_ERR_UNSPECIFIED;
    }

    /* make sure generated key isn't debug key */
  } while (memcmp(ecc.private_key, debug_private_key, 32) == 0);
#else
  sys_memcpy_swap(&ecc.pk, debug_public_key, 32);
  sys_memcpy_swap(&ecc.pk[32], &debug_public_key[32], 32);
  sys_memcpy_swap(ecc.private_key, debug_private_key, 32);
#endif
  return 0;
}

static void emulate_le_p256_public_key_cmd(void) {
  struct bt_hci_evt_le_p256_public_key_complete *evt;
  struct bt_hci_evt_le_meta_event               *meta;
  struct bt_hci_evt_hdr                         *hdr;
  struct net_buf                                *buf;
  u8_t                                           status;

  BT_DBG("");

  status = generate_keys();

  buf = bt_buf_get_rx(BT_BUF_EVT, K_FOREVER);

  hdr      = net_buf_add(buf, sizeof(*hdr));
  hdr->evt = BT_HCI_EVT_LE_META_EVENT;
  hdr->len = sizeof(*meta) + sizeof(*evt);

  meta           = net_buf_add(buf, sizeof(*meta));
  meta->subevent = BT_HCI_EVT_LE_P256_PUBLIC_KEY_COMPLETE;

  evt         = net_buf_add(buf, sizeof(*evt));
  evt->status = status;

  if (status) {
    (void)memset(evt->key, 0, sizeof(evt->key));
  } else {
    /* Convert X and Y coordinates from big-endian (provided
     * by crypto API) to little endian HCI.
     */
    sys_memcpy_swap(evt->key, ecc.pk, 32);
    sys_memcpy_swap(&evt->key[32], &ecc.pk[32], 32);
  }

  atomic_clear_bit(flags, PENDING_PUB_KEY);

  bt_recv(buf);
}

static void emulate_le_generate_dhkey(void) {
  struct bt_hci_evt_le_generate_dhkey_complete *evt;
  struct bt_hci_evt_le_meta_event              *meta;
  struct bt_hci_evt_hdr                        *hdr;
  struct net_buf                               *buf;
  int                                           ret;

  ret = uECC_valid_public_key(ecc.pk, &curve_secp256r1);
  if (ret < 0) {
    BT_ERR("public key is not valid (ret %d)", ret);
    ret = TC_CRYPTO_FAIL;
  } else {
    ret = uECC_shared_secret(ecc.pk, ecc.private_key, ecc.dhkey, &curve_secp256r1);
  }

  buf = bt_buf_get_rx(BT_BUF_EVT, K_FOREVER);

  hdr      = net_buf_add(buf, sizeof(*hdr));
  hdr->evt = BT_HCI_EVT_LE_META_EVENT;
  hdr->len = sizeof(*meta) + sizeof(*evt);

  meta           = net_buf_add(buf, sizeof(*meta));
  meta->subevent = BT_HCI_EVT_LE_GENERATE_DHKEY_COMPLETE;

  evt = net_buf_add(buf, sizeof(*evt));

  if (ret == TC_CRYPTO_FAIL) {
    evt->status = BT_HCI_ERR_UNSPECIFIED;
    (void)memset(evt->dhkey, 0, sizeof(evt->dhkey));
  } else {
    evt->status = 0U;
    /* Convert from big-endian (provided by crypto API) to
     * little-endian HCI.
     */
    sys_memcpy_swap(evt->dhkey, ecc.dhkey, sizeof(ecc.dhkey));
  }

  atomic_clear_bit(flags, PENDING_DHKEY);

  bt_recv(buf);
}

#if defined(BFLB_BLE)
static void ecc_thread(void *p1)
#else
static void ecc_thread(void *p1, void *p2, void *p3)
#endif
{
  while (true) {
    k_sem_take(&cmd_sem, K_FOREVER);

    if (atomic_test_bit(flags, PENDING_PUB_KEY)) {
      emulate_le_p256_public_key_cmd();
    } else if (atomic_test_bit(flags, PENDING_DHKEY)) {
      emulate_le_generate_dhkey();
    } else {
      __ASSERT(0, "Unhandled ECC command");
    }
#if !defined(BFLB_BLE)
    STACK_ANALYZE("ecc stack", ecc_thread_stack);
#endif
  }
}

static void clear_ecc_events(struct net_buf *buf) {
  struct bt_hci_cp_le_set_event_mask *cmd;

  cmd = (void *)(buf->data + sizeof(struct bt_hci_cmd_hdr));

  /*
   * don't enable controller ECC events as those will be generated from
   * emulation code
   */
  cmd->events[0] &= ~0x80; /* LE Read Local P-256 PKey Compl */
  cmd->events[1] &= ~0x01; /* LE Generate DHKey Compl Event */
}

static void le_gen_dhkey(struct net_buf *buf) {
  struct bt_hci_cp_le_generate_dhkey *cmd;
  u8_t                                status;

  if (atomic_test_bit(flags, PENDING_PUB_KEY)) {
    status = BT_HCI_ERR_CMD_DISALLOWED;
    goto send_status;
  }

  if (buf->len < sizeof(struct bt_hci_cp_le_generate_dhkey)) {
    status = BT_HCI_ERR_INVALID_PARAM;
    goto send_status;
  }

  if (atomic_test_and_set_bit(flags, PENDING_DHKEY)) {
    status = BT_HCI_ERR_CMD_DISALLOWED;
    goto send_status;
  }

  cmd = (void *)buf->data;
  /* Convert X and Y coordinates from little-endian HCI to
   * big-endian (expected by the crypto API).
   */
  sys_memcpy_swap(ecc.pk, cmd->key, 32);
  sys_memcpy_swap(&ecc.pk[32], &cmd->key[32], 32);
  k_sem_give(&cmd_sem);
  status = BT_HCI_ERR_SUCCESS;

send_status:
  net_buf_unref(buf);
  send_cmd_status(BT_HCI_OP_LE_GENERATE_DHKEY, status);
}

static void le_p256_pub_key(struct net_buf *buf) {
  u8_t status;

  net_buf_unref(buf);

  if (atomic_test_bit(flags, PENDING_DHKEY)) {
    status = BT_HCI_ERR_CMD_DISALLOWED;
  } else if (atomic_test_and_set_bit(flags, PENDING_PUB_KEY)) {
    status = BT_HCI_ERR_CMD_DISALLOWED;
  } else {
    k_sem_give(&cmd_sem);
    status = BT_HCI_ERR_SUCCESS;
  }

  send_cmd_status(BT_HCI_OP_LE_P256_PUBLIC_KEY, status);
}

int bt_hci_ecc_send(struct net_buf *buf) {
  if (bt_buf_get_type(buf) == BT_BUF_CMD) {
    struct bt_hci_cmd_hdr *chdr = (void *)buf->data;

    switch (sys_le16_to_cpu(chdr->opcode)) {
    case BT_HCI_OP_LE_P256_PUBLIC_KEY:
      net_buf_pull(buf, sizeof(*chdr));
      le_p256_pub_key(buf);
      return 0;
    case BT_HCI_OP_LE_GENERATE_DHKEY:
      net_buf_pull(buf, sizeof(*chdr));
      le_gen_dhkey(buf);
      return 0;
    case BT_HCI_OP_LE_SET_EVENT_MASK:
      clear_ecc_events(buf);
      break;
    default:
      break;
    }
  }

  return bt_dev.drv->send(buf);
}

int default_CSPRNG(u8_t *dst, unsigned int len) { return !bt_rand(dst, len); }

void bt_hci_ecc_init(void) {
#if defined(BFLB_BLE)
  k_sem_init(&cmd_sem, 0, 1);
  k_thread_create(&ecc_thread_data, "ecc_thread", CONFIG_BT_HCI_ECC_STACK_SIZE, ecc_thread, CONFIG_BT_WORK_QUEUE_PRIO);
#else
  k_thread_create(&ecc_thread_data, ecc_thread_stack, K_THREAD_STACK_SIZEOF(ecc_thread_stack), ecc_thread, NULL, NULL, NULL, K_PRIO_PREEMPT(10), 0, K_NO_WAIT);
  k_thread_name_set(&ecc_thread_data, "BT ECC");
#endif
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hci_ecc.h
================================================
/* hci_ecc.h - HCI ECC emulation */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

void bt_hci_ecc_init(void);
int bt_hci_ecc_send(struct net_buf *buf);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hfp_hf.c
================================================
/* hfp_hf.c - Hands free Profile - Handsfree side handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include 
#include 
#include 
#include 
#include 
#include 

#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_HFP_HF)
#define LOG_MODULE_NAME bt_hfp_hf
#include "log.h"

#include 
#include 
#include 

#include "at.h"
#include "conn_internal.h"
#include "hci_core.h"
#include "hfp_internal.h"
#include "l2cap_internal.h"
#include "rfcomm_internal.h"

#define MAX_IND_STR_LEN 17

struct bt_hfp_hf_cb *bt_hf;
bool                 hfp_codec_msbc = 0;

#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
NET_BUF_POOL_FIXED_DEFINE(hf_pool, CONFIG_BT_MAX_CONN + 1, BT_RFCOMM_BUF_SIZE(BT_HF_CLIENT_MAX_PDU), NULL);
#else
struct net_buf_pool hf_pool;
#endif

static struct bt_hfp_hf bt_hfp_hf_pool[CONFIG_BT_MAX_CONN];

static struct bt_sdp_attribute hfp_attrs[] = {
    BT_SDP_NEW_SERVICE,
    BT_SDP_LIST(BT_SDP_ATTR_SVCLASS_ID_LIST, BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 10),
                BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3), BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE(BT_SDP_UUID16), BT_SDP_ARRAY_16(BT_SDP_HANDSFREE_SVCLASS)}, )},
                                      {BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3), BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE(BT_SDP_UUID16), BT_SDP_ARRAY_16(BT_SDP_GENERIC_AUDIO_SVCLASS)}, )}, )),
    BT_SDP_LIST(BT_SDP_ATTR_PROTO_DESC_LIST, BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 12),
                BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3), BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE(BT_SDP_UUID16), BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP)}, )},
                                      {BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 5), BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE(BT_SDP_UUID16), BT_SDP_ARRAY_16(BT_SDP_PROTO_RFCOMM)},
                                                                                                   {BT_SDP_TYPE_SIZE(BT_SDP_UINT8), BT_SDP_ARRAY_16(BT_RFCOMM_CHAN_HFP_HF)})}, )),
    BT_SDP_LIST(BT_SDP_ATTR_PROFILE_DESC_LIST, BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 8),
                BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), BT_SDP_DATA_ELEM_LIST({BT_SDP_TYPE_SIZE(BT_SDP_UUID16), BT_SDP_ARRAY_16(BT_SDP_HANDSFREE_SVCLASS)},
                                                                                                   {BT_SDP_TYPE_SIZE(BT_SDP_UINT16), BT_SDP_ARRAY_16(0x0107)}, )}, )),
    BT_SDP_SERVICE_NAME("hands-free"),
    /*
        "SupportedFeatures" attribute bit mapping for the HF
        bit 0: EC and/or NR function
        bit 1: Call waiting or three-way calling
        bit 2: CLI presentation capability
        bit 3: Voice recognition activation
        bit 4: Remote volume control
        bit 5: Wide band speech
        bit 6: Enhanced Voice Recognition Status
        bit 7: Voice Recognition Text
        */
    BT_SDP_SUPPORTED_FEATURES(0x0035),
};

static struct bt_sdp_record hfp_rec = BT_SDP_RECORD(hfp_attrs);

/* The order should follow the enum hfp_hf_ag_indicators */
static const struct {
  char    *name;
  uint32_t min;
  uint32_t max;
} ag_ind[] = {
    {  "service", 0, 1}, /* HF_SERVICE_IND */
    {     "call", 0, 1}, /* HF_CALL_IND */
    {"callsetup", 0, 3}, /* HF_CALL_SETUP_IND */
    { "callheld", 0, 2}, /* HF_CALL_HELD_IND */
    {   "signal", 0, 5}, /* HF_SINGNAL_IND */
    {     "roam", 0, 1}, /* HF_ROAM_IND */
    {  "battchg", 0, 5}  /* HF_BATTERY_IND */
};

static void connected(struct bt_conn *conn) { BT_DBG("HFP HF Connected!"); }

static void disconnected(struct bt_conn *conn) { BT_DBG("HFP HF Disconnected!"); }

static void service(struct bt_conn *conn, uint32_t value) { BT_DBG("Service indicator value: %u", value); }

static void call(struct bt_conn *conn, uint32_t value) { BT_DBG("Call indicator value: %u", value); }

static void call_setup(struct bt_conn *conn, uint32_t value) { BT_DBG("Call Setup indicator value: %u", value); }

static void call_held(struct bt_conn *conn, uint32_t value) { BT_DBG("Call Held indicator value: %u", value); }

static void signal(struct bt_conn *conn, uint32_t value) { BT_DBG("Signal indicator value: %u", value); }

static void roam(struct bt_conn *conn, uint32_t value) { BT_DBG("Roaming indicator value: %u", value); }

static void battery(struct bt_conn *conn, uint32_t value) { BT_DBG("Battery indicator value: %u", value); }

static void ring_cb(struct bt_conn *conn) { BT_DBG("Incoming Call..."); }

static struct bt_hfp_hf_cb hf_cb = {
    .connected       = connected,
    .disconnected    = disconnected,
    .service         = service,
    .call            = call,
    .call_setup      = call_setup,
    .call_held       = call_held,
    .signal          = signal,
    .roam            = roam,
    .battery         = battery,
    .ring_indication = ring_cb,
};

void hf_slc_error(struct at_client *hf_at) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               err;

  BT_ERR("SLC error: disconnecting");
  err = bt_rfcomm_dlc_disconnect(&hf->rfcomm_dlc);
  if (err) {
    BT_ERR("Rfcomm: Unable to disconnect :%d", -err);
  }
}

int hfp_hf_send_cmd(struct bt_hfp_hf *hf, at_resp_cb_t resp, at_finish_cb_t finish, const char *format, ...) {
  struct net_buf *buf;
  va_list         vargs;
  int             ret;

  /* register the callbacks */
  at_register(&hf->at, resp, finish);

  buf = bt_rfcomm_create_pdu(&hf_pool);
  if (!buf) {
    BT_ERR("No Buffers!");
    return -ENOMEM;
  }

  va_start(vargs, format);
  ret = vsnprintf((char *)buf->data, (net_buf_tailroom(buf) - 1), format, vargs);
  if (ret < 0) {
    BT_ERR("Unable to format variable arguments");
    return ret;
  }
  va_end(vargs);

  net_buf_add(buf, ret);
  net_buf_add_u8(buf, '\r');

  ret = bt_rfcomm_dlc_send(&hf->rfcomm_dlc, buf);
  if (ret < 0) {
    BT_ERR("Rfcomm send error :(%d)", ret);
    return ret;
  }

  return 0;
}

int brsf_handle(struct at_client *hf_at) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  uint32_t          val;
  int               ret;

  ret = at_get_number(hf_at, &val);
  if (ret < 0) {
    BT_ERR("Error getting value");
    return ret;
  }

  hf->ag_features = val;

  return 0;
}

int brsf_resp(struct at_client *hf_at, struct net_buf *buf) {
  int err;

  BT_DBG("");

  err = at_parse_cmd_input(hf_at, buf, "BRSF", brsf_handle, AT_CMD_TYPE_NORMAL);
  if (err < 0) {
    /* Returning negative value is avoided before SLC connection
     * established.
     */
    BT_ERR("Error parsing CMD input");
    hf_slc_error(hf_at);
  }

  return 0;
}

static void cind_handle_values(struct at_client *hf_at, uint32_t index, char *name, uint32_t min, uint32_t max) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               i;

  BT_DBG("index: %u, name: %s, min: %u, max:%u", index, name, min, max);

  for (i = 0; i < ARRAY_SIZE(ag_ind); i++) {
    if (strcmp(name, ag_ind[i].name) != 0) {
      continue;
    }
    if (min != ag_ind[i].min || max != ag_ind[i].max) {
      BT_ERR("%s indicator min/max value not matching", name);
    }

    hf->ind_table[index] = i;
    break;
  }
}

int cind_handle(struct at_client *hf_at) {
  uint32_t index = 0U;

  /* Parsing Example: CIND: ("call",(0,1)) etc.. */
  while (at_has_next_list(hf_at)) {
    char     name[MAX_IND_STR_LEN];
    uint32_t min, max;

    if (at_open_list(hf_at) < 0) {
      BT_ERR("Could not get open list");
      goto error;
    }

    if (at_list_get_string(hf_at, name, sizeof(name)) < 0) {
      BT_ERR("Could not get string");
      goto error;
    }

    if (at_open_list(hf_at) < 0) {
      BT_ERR("Could not get open list");
      goto error;
    }

    if (at_list_get_range(hf_at, &min, &max) < 0) {
      BT_ERR("Could not get range");
      goto error;
    }

    if (at_close_list(hf_at) < 0) {
      BT_ERR("Could not get close list");
      goto error;
    }

    if (at_close_list(hf_at) < 0) {
      BT_ERR("Could not get close list");
      goto error;
    }

    cind_handle_values(hf_at, index, name, min, max);
    index++;
  }

  return 0;
error:
  BT_ERR("Error on CIND response");
  hf_slc_error(hf_at);
  return -EINVAL;
}

int cind_resp(struct at_client *hf_at, struct net_buf *buf) {
  int err;

  err = at_parse_cmd_input(hf_at, buf, "CIND", cind_handle, AT_CMD_TYPE_NORMAL);
  if (err < 0) {
    BT_ERR("Error parsing CMD input");
    hf_slc_error(hf_at);
  }

  return 0;
}

void ag_indicator_handle_values(struct at_client *hf_at, uint32_t index, uint32_t value) {
  struct bt_hfp_hf *hf   = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  struct bt_conn   *conn = hf->rfcomm_dlc.session->br_chan.chan.conn;

  BT_DBG("Index :%u, Value :%u", index, value);

  if (index >= ARRAY_SIZE(ag_ind)) {
    BT_ERR("Max only %lu indicators are supported", ARRAY_SIZE(ag_ind));
    return;
  }

  if (value > ag_ind[hf->ind_table[index]].max || value < ag_ind[hf->ind_table[index]].min) {
    BT_ERR("Indicators out of range - value: %u", value);
    return;
  }

  switch (hf->ind_table[index]) {
  case HF_SERVICE_IND:
    if (bt_hf->service) {
      bt_hf->service(conn, value);
    }
    break;
  case HF_CALL_IND:
    if (bt_hf->call) {
      bt_hf->call(conn, value);
    }
    break;
  case HF_CALL_SETUP_IND:
    if (bt_hf->call_setup) {
      bt_hf->call_setup(conn, value);
    }
    break;
  case HF_CALL_HELD_IND:
    if (bt_hf->call_held) {
      bt_hf->call_held(conn, value);
    }
    break;
  case HF_SINGNAL_IND:
    if (bt_hf->signal) {
      bt_hf->signal(conn, value);
    }
    break;
  case HF_ROAM_IND:
    if (bt_hf->roam) {
      bt_hf->roam(conn, value);
    }
    break;
  case HF_BATTERY_IND:
    if (bt_hf->battery) {
      bt_hf->battery(conn, value);
    }
    break;
  default:
    BT_ERR("Unknown AG indicator");
    break;
  }
}

int cind_status_handle(struct at_client *hf_at) {
  uint32_t index = 0U;

  while (at_has_next_list(hf_at)) {
    uint32_t value;
    int      ret;

    ret = at_get_number(hf_at, &value);
    if (ret < 0) {
      BT_ERR("could not get the value");
      return ret;
    }

    ag_indicator_handle_values(hf_at, index, value);

    index++;
  }

  return 0;
}

int cind_status_resp(struct at_client *hf_at, struct net_buf *buf) {
  int err;

  err = at_parse_cmd_input(hf_at, buf, "CIND", cind_status_handle, AT_CMD_TYPE_NORMAL);
  if (err < 0) {
    BT_ERR("Error parsing CMD input");
    hf_slc_error(hf_at);
  }

  return 0;
}

int ciev_handle(struct at_client *hf_at) {
  uint32_t index, value;
  int      ret;

  ret = at_get_number(hf_at, &index);
  if (ret < 0) {
    BT_ERR("could not get the Index");
    return ret;
  }
  /* The first element of the list shall have 1 */
  if (!index) {
    BT_ERR("Invalid index value '0'");
    return 0;
  }

  ret = at_get_number(hf_at, &value);
  if (ret < 0) {
    BT_ERR("could not get the value");
    return ret;
  }

  ag_indicator_handle_values(hf_at, (index - 1), value);

  return 0;
}

int ring_handle(struct at_client *hf_at) {
  struct bt_hfp_hf *hf   = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  struct bt_conn   *conn = hf->rfcomm_dlc.session->br_chan.chan.conn;

  if (bt_hf->ring_indication) {
    bt_hf->ring_indication(conn);
  }

  return 0;
}

int bcs_handle(struct at_client *hf_at) {
  uint32_t value;
  int      ret;

  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);

  ret = at_get_number(hf_at, &value);
  if (ret < 0) {
    BT_ERR("could not get the value");
    return ret;
  }
  if (value == 1) {
    if (hfp_hf_send_cmd(hf, NULL, NULL, "AT+BCS=1") < 0) {
      BT_ERR("Error Sending AT+BCS=1");
    }
  } else if (value == 2) {
    if (hfp_hf_send_cmd(hf, NULL, NULL, "AT+BCS=2") < 0) {
      BT_ERR("Error Sending AT+BCS=2");
    } else {
      hfp_codec_msbc = 1;
    }
  } else {
    BT_WARN("Invail BCS value !");
  }

  return 0;
}

static const struct unsolicited {
  const char      *cmd;
  enum at_cmd_type type;
  int (*func)(struct at_client *hf_at);
} handlers[] = {
    {"CIEV", AT_CMD_TYPE_UNSOLICITED, ciev_handle},
    {"RING",       AT_CMD_TYPE_OTHER, ring_handle},
    { "BCS", AT_CMD_TYPE_UNSOLICITED,  bcs_handle}
};

static const struct unsolicited *hfp_hf_unsol_lookup(struct at_client *hf_at) {
  int i;

  for (i = 0; i < ARRAY_SIZE(handlers); i++) {
    if (!strncmp(hf_at->buf, handlers[i].cmd, strlen(handlers[i].cmd))) {
      return &handlers[i];
    }
  }

  return NULL;
}

int unsolicited_cb(struct at_client *hf_at, struct net_buf *buf) {
  const struct unsolicited *handler;

  handler = hfp_hf_unsol_lookup(hf_at);
  if (!handler) {
    BT_ERR("Unhandled unsolicited response");
    return -ENOMSG;
  }

  if (!at_parse_cmd_input(hf_at, buf, handler->cmd, handler->func, handler->type)) {
    return 0;
  }

  return -ENOMSG;
}

int cmd_complete(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf             *hf   = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  struct bt_conn               *conn = hf->rfcomm_dlc.session->br_chan.chan.conn;
  struct bt_hfp_hf_cmd_complete cmd  = {0};

  BT_DBG("");

  switch (result) {
  case AT_RESULT_OK:
    cmd.type = HFP_HF_CMD_OK;
    break;
  case AT_RESULT_ERROR:
    cmd.type = HFP_HF_CMD_ERROR;
    break;
  case AT_RESULT_CME_ERROR:
    cmd.type = HFP_HF_CMD_CME_ERROR;
    cmd.cme  = cme_err;
    break;
  default:
    BT_ERR("Unknown error code");
    cmd.type = HFP_HF_CMD_UNKNOWN_ERROR;
    break;
  }

  if (bt_hf->cmd_complete_cb) {
    bt_hf->cmd_complete_cb(conn, &cmd);
  }

  return 0;
}

int cmee_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);

  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    return -EINVAL;
  }

  if (hfp_hf_send_cmd(hf, NULL, NULL, "AT+NREC=0") < 0) {
    BT_ERR("Error Sending AT+NREC");
  }

  return 0;
}

static void slc_completed(struct at_client *hf_at) {
  struct bt_hfp_hf *hf   = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  struct bt_conn   *conn = hf->rfcomm_dlc.session->br_chan.chan.conn;

  if (bt_hf->connected) {
    bt_hf->connected(conn);
  }

  if (hfp_hf_send_cmd(hf, NULL, cmee_finish, "AT+CMEE=1") < 0) {
    BT_ERR("Error Sending AT+CMEE");
  }
}

int cmer_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    hf_slc_error(hf_at);
    return -EINVAL;
  }

  slc_completed(hf_at);

  return 0;
}

int cind_status_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               err;

  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    hf_slc_error(hf_at);
    return -EINVAL;
  }

  at_register_unsolicited(hf_at, unsolicited_cb);
  err = hfp_hf_send_cmd(hf, NULL, cmer_finish, "AT+CMER=3,0,0,1");
  if (err < 0) {
    hf_slc_error(hf_at);
    return err;
  }

  return 0;
}

int cind_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               err;

  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    hf_slc_error(hf_at);
    return -EINVAL;
  }

  err = hfp_hf_send_cmd(hf, cind_status_resp, cind_status_finish, "AT+CIND?");
  if (err < 0) {
    hf_slc_error(hf_at);
    return err;
  }

  return 0;
}

int bac_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               err;

  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    hf_slc_error(hf_at);
    return -EINVAL;
  }

  err = hfp_hf_send_cmd(hf, cind_resp, cind_finish, "AT+CIND=?");
  if (err < 0) {
    hf_slc_error(hf_at);
    return err;
  }

  return 0;
}

int brsf_finish(struct at_client *hf_at, enum at_result result, enum at_cme cme_err) {
  struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
  int               err;

  if (result != AT_RESULT_OK) {
    BT_ERR("SLC Connection ERROR in response");
    hf_slc_error(hf_at);
    return -EINVAL;
  }

  err = hfp_hf_send_cmd(hf, NULL, bac_finish, "AT+BAC=1,2");
  if (err < 0) {
    hf_slc_error(hf_at);
    return err;
  }

  return 0;
}

int hf_slc_establish(struct bt_hfp_hf *hf) {
  int err;

  BT_DBG("");

  err = hfp_hf_send_cmd(hf, brsf_resp, brsf_finish, "AT+BRSF=%u", hf->hf_features);
  if (err < 0) {
    hf_slc_error(&hf->at);
    return err;
  }

  return 0;
}

static struct bt_hfp_hf *bt_hfp_hf_lookup_bt_conn(struct bt_conn *conn) {
  int i;

  for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) {
    struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i];

    if (hf->rfcomm_dlc.session->br_chan.chan.conn == conn) {
      return hf;
    }
  }

  return NULL;
}

int bt_hfp_hf_send_cmd(struct bt_conn *conn, enum bt_hfp_hf_at_cmd cmd) {
  struct bt_hfp_hf *hf;
  int               err;

  BT_DBG("");

  if (!conn) {
    BT_ERR("Invalid connection");
    return -ENOTCONN;
  }

  hf = bt_hfp_hf_lookup_bt_conn(conn);
  if (!hf) {
    BT_ERR("No HF connection found");
    return -ENOTCONN;
  }

  switch (cmd) {
  case BT_HFP_HF_ATA:
    err = hfp_hf_send_cmd(hf, NULL, cmd_complete, "ATA");
    if (err < 0) {
      BT_ERR("Failed ATA");
      return err;
    }
    break;
  case BT_HFP_HF_AT_CHUP:
    err = hfp_hf_send_cmd(hf, NULL, cmd_complete, "AT+CHUP");
    if (err < 0) {
      BT_ERR("Failed AT+CHUP");
      return err;
    }
    break;
  default:
    BT_ERR("Invalid AT Command");
    return -EINVAL;
  }

  return 0;
}

static void hfp_hf_connected(struct bt_rfcomm_dlc *dlc) {
  struct bt_hfp_hf *hf = CONTAINER_OF(dlc, struct bt_hfp_hf, rfcomm_dlc);

  BT_DBG("hf connected");

  BT_ASSERT(hf);
  hf_slc_establish(hf);
}

static void hfp_hf_disconnected(struct bt_rfcomm_dlc *dlc) {
  struct bt_conn *conn = dlc->session->br_chan.chan.conn;

  BT_DBG("hf disconnected!");
  if (bt_hf->disconnected) {
    bt_hf->disconnected(conn);
  }
}

static void hfp_hf_recv(struct bt_rfcomm_dlc *dlc, struct net_buf *buf) {
  struct bt_hfp_hf *hf = CONTAINER_OF(dlc, struct bt_hfp_hf, rfcomm_dlc);

  if (at_parse_input(&hf->at, buf) < 0) {
    BT_ERR("Parsing failed");
  }
}

static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc) {
  int                             i;
  static struct bt_rfcomm_dlc_ops ops = {
      .connected    = hfp_hf_connected,
      .disconnected = hfp_hf_disconnected,
      .recv         = hfp_hf_recv,
  };

  BT_DBG("conn %p", conn);

  for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) {
    struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i];
    int               j;

    if (hf->rfcomm_dlc.session) {
      continue;
    }

    hf->at.buf         = hf->hf_buffer;
    hf->at.buf_max_len = HF_MAX_BUF_LEN;

    hf->rfcomm_dlc.ops = &ops;
    hf->rfcomm_dlc.mtu = BT_HFP_MAX_MTU;

    *dlc = &hf->rfcomm_dlc;

    /* Set the supported features*/
    hf->hf_features = BT_HFP_HF_SUPPORTED_FEATURES;

    for (j = 0; j < HF_MAX_AG_INDICATORS; j++) {
      hf->ind_table[j] = -1;
    }

    return 0;
  }

  BT_ERR("Unable to establish HF connection (%p)", conn);

  return -ENOMEM;
}

int bt_hfp_hf_init(void) {
  int err;

#if defined(BFLB_DYNAMIC_ALLOC_MEM)
  net_buf_init(&hf_pool, CONFIG_BT_MAX_CONN + 1, BT_RFCOMM_BUF_SIZE(BT_HF_CLIENT_MAX_PDU), NULL);
#endif

  bt_hf = &hf_cb;

  static struct bt_rfcomm_server chan = {
      .channel = BT_RFCOMM_CHAN_HFP_HF,
      .accept  = bt_hfp_hf_accept,
  };

  bt_rfcomm_server_register(&chan);

  /* Register SDP record */
  err = bt_sdp_register_service(&hfp_rec);
  if (err < 0) {
    BT_ERR("HFP regist sdp record failed");
  }
  BT_DBG("HFP initialized successfully.");
  return err;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/hfp_internal.h
================================================
/** @file
 *  @brief Internal APIs for Bluetooth Handsfree profile handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#define BT_HFP_MAX_MTU       140
#define BT_HF_CLIENT_MAX_PDU BT_HFP_MAX_MTU

/* HFP AG Features */
#define BT_HFP_AG_FEATURE_3WAY_CALL   0x00000001 /* Three-way calling */
#define BT_HFP_AG_FEATURE_ECNR        0x00000002 /* EC and/or NR function */
#define BT_HFP_AG_FEATURE_VOICE_RECG  0x00000004 /* Voice recognition */
#define BT_HFP_AG_INBAND_RING_TONE    0x00000008 /* In-band ring capability */
#define BT_HFP_AG_VOICE_TAG           0x00000010 /* Attach no. to voice tag */
#define BT_HFP_AG_FEATURE_REJECT_CALL 0x00000020 /* Ability to reject call */
#define BT_HFP_AG_FEATURE_ECS         0x00000040 /* Enhanced call status */
#define BT_HFP_AG_FEATURE_ECC         0x00000080 /* Enhanced call control */
#define BT_HFP_AG_FEATURE_EXT_ERR     0x00000100 /* Extented error codes */
#define BT_HFP_AG_FEATURE_CODEC_NEG   0x00000200 /* Codec negotiation */
#define BT_HFP_AG_FEATURE_HF_IND      0x00000400 /* HF Indicators */
#define BT_HFP_AG_FEARTURE_ESCO_S4    0x00000800 /* eSCO S4 Settings */

/* HFP HF Features */
#define BT_HFP_HF_FEATURE_ECNR       0x00000001 /* EC and/or NR */
#define BT_HFP_HF_FEATURE_3WAY_CALL  0x00000002 /* Three-way calling */
#define BT_HFP_HF_FEATURE_CLI        0x00000004 /* CLI presentation */
#define BT_HFP_HF_FEATURE_VOICE_RECG 0x00000008 /* Voice recognition */
#define BT_HFP_HF_FEATURE_VOLUME     0x00000010 /* Remote volume control */
#define BT_HFP_HF_FEATURE_ECS        0x00000020 /* Enhanced call status */
#define BT_HFP_HF_FEATURE_ECC        0x00000040 /* Enhanced call control */
#define BT_HFP_HF_FEATURE_CODEC_NEG  0x00000080 /* CODEC Negotiation */
#define BT_HFP_HF_FEATURE_HF_IND     0x00000100 /* HF Indicators */
#define BT_HFP_HF_FEATURE_ESCO_S4    0x00000200 /* eSCO S4 Settings */

/* HFP HF Supported features */
#define BT_HFP_HF_SUPPORTED_FEATURES (BT_HFP_HF_FEATURE_ECNR |   \
                                      BT_HFP_HF_FEATURE_CLI |    \
                                      BT_HFP_HF_FEATURE_VOLUME | \
                                      BT_HFP_HF_FEATURE_CODEC_NEG)

#define HF_MAX_BUF_LEN       BT_HF_CLIENT_MAX_PDU
#define HF_MAX_AG_INDICATORS 20

struct bt_hfp_hf {
    struct bt_rfcomm_dlc rfcomm_dlc;
    char hf_buffer[HF_MAX_BUF_LEN];
    struct at_client at;
    uint32_t hf_features;
    uint32_t ag_features;
    int8_t ind_table[HF_MAX_AG_INDICATORS];
};

enum hfp_hf_ag_indicators {
    HF_SERVICE_IND,
    HF_CALL_IND,
    HF_CALL_SETUP_IND,
    HF_CALL_HELD_IND,
    HF_SINGNAL_IND,
    HF_ROAM_IND,
    HF_BATTERY_IND
};


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/iso_internal.h
================================================
/** @file
 *  @brief Internal APIs for Bluetooth ISO handling.
 */

/*
 * Copyright (c) 2020 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

#define BT_ISO_DATA_PATH_DISABLED 0xFF

struct iso_data {
    /** BT_BUF_ISO_IN */
    uint8_t type;

    /* Index into the bt_conn storage array */
    uint8_t index;

    /** ISO connection handle */
    uint16_t handle;

    /** ISO timestamp */
    uint32_t ts;
};

#define iso(buf) ((struct iso_data *)net_buf_user_data(buf))

#if defined(CONFIG_BT_MAX_ISO_CONN)
extern struct bt_conn iso_conns[CONFIG_BT_MAX_ISO_CONN];
#endif

/* Process ISO buffer */
void hci_iso(struct net_buf *buf);

/* Allocates RX buffer */
struct net_buf *bt_iso_get_rx(uint32_t timeout);

/* Create new ISO connecting */
struct bt_conn *iso_new(void);

/* Process CIS Estabilished event */
void hci_le_cis_estabilished(struct net_buf *buf);

/* Process CIS Request event */
void hci_le_cis_req(struct net_buf *buf);

/* Notify ISO channels of a new connection */
int bt_iso_accept(struct bt_conn *conn);

/* Notify ISO channels of a new connection */
void bt_iso_connected(struct bt_conn *conn);

/* Notify ISO channels of a disconnect event */
void bt_iso_disconnected(struct bt_conn *conn);

/* Allocate ISO PDU */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *bt_iso_create_pdu_timeout_debug(struct net_buf_pool *pool,
                                                size_t reserve,
                                                k_timeout_t timeout,
                                                const char *func, int line);
#define bt_iso_create_pdu_timeout(_pool, _reserve, _timeout)   \
    bt_iso_create_pdu_timeout_debug(_pool, _reserve, _timeout, \
                                    __func__, __LINE__)

#define bt_iso_create_pdu(_pool, _reserve)                      \
    bt_iso_create_pdu_timeout_debug(_pool, _reserve, K_FOREVER, \
                                    __func__, __line__)
#else
struct net_buf *bt_iso_create_pdu_timeout(struct net_buf_pool *pool,
                                          size_t reserve, uint32_t timeout);

#define bt_iso_create_pdu(_pool, _reserve) \
    bt_iso_create_pdu_timeout(_pool, _reserve, K_FOREVER)
#endif

/* Allocate ISO Fragment */
#if defined(CONFIG_NET_BUF_LOG)
struct net_buf *bt_iso_create_frag_timeout_debug(size_t reserve,
                                                 k_timeout_t timeout,
                                                 const char *func, int line);

#define bt_iso_create_frag_timeout(_reserve, _timeout)   \
    bt_iso_create_frag_timeout_debug(_reserve, _timeout, \
                                     __func__, __LINE__)

#define bt_iso_create_frag(_reserve)                      \
    bt_iso_create_frag_timeout_debug(_reserve, K_FOREVER, \
                                     __func__, __LINE__)
#else
struct net_buf *bt_iso_create_frag_timeout(size_t reserve, uint32_t timeout);

#define bt_iso_create_frag(_reserve) \
    bt_iso_create_frag_timeout(_reserve, K_FOREVER)
#endif

#if defined(CONFIG_BT_AUDIO_DEBUG_ISO)
void bt_iso_chan_set_state_debug(struct bt_iso_chan *chan, uint8_t state,
                                 const char *func, int line);
#define bt_iso_chan_set_state(_chan, _state) \
    bt_iso_chan_set_state_debug(_chan, _state, __func__, __LINE__)
#else
void bt_iso_chan_set_state(struct bt_iso_chan *chan, uint8_t state);
#endif /* CONFIG_BT_AUDIO_DEBUG_ISO */

/* Process incoming data for a connection */
void bt_iso_recv(struct bt_conn *conn, struct net_buf *buf, uint8_t flags);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/keys.c
================================================
/* keys.c - Bluetooth key handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 

#include 
#include 
#include 

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_KEYS)
#include "log.h"

#include "gatt_internal.h"
#include "hci_core.h"
#include "keys.h"
#include "rpa.h"
#include "settings.h"
#include "smp.h"
#if defined(BFLB_BLE)
#if defined(CONFIG_BT_SETTINGS)
#include "easyflash.h"
#endif
#endif

static struct bt_keys key_pool[CONFIG_BT_MAX_PAIRED];

#define BT_KEYS_STORAGE_LEN_COMPAT (BT_KEYS_STORAGE_LEN - sizeof(uint32_t))

#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
static u32_t           aging_counter_val;
static struct bt_keys *last_keys_updated;
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */

struct bt_keys *bt_keys_get_addr(u8_t id, const bt_addr_le_t *addr) {
  struct bt_keys *keys;
  int             i;
  size_t          first_free_slot = ARRAY_SIZE(key_pool);

  BT_DBG("%s", bt_addr_le_str(addr));

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    keys = &key_pool[i];

    if (keys->id == id && !bt_addr_le_cmp(&keys->addr, addr)) {
      return keys;
    }

    if (first_free_slot == ARRAY_SIZE(key_pool) && (!bt_addr_le_cmp(&keys->addr, BT_ADDR_LE_ANY) || !keys->enc_size)) {
      first_free_slot = i;
    }
  }

#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
  if (first_free_slot == ARRAY_SIZE(key_pool)) {
    struct bt_keys *oldest = &key_pool[0];

    for (i = 1; i < ARRAY_SIZE(key_pool); i++) {
      struct bt_keys *current = &key_pool[i];

      if (current->aging_counter < oldest->aging_counter) {
        oldest = current;
      }
    }

    bt_unpair(oldest->id, &oldest->addr);
    if (!bt_addr_le_cmp(&oldest->addr, BT_ADDR_LE_ANY)) {
      first_free_slot = oldest - &key_pool[0];
    }
  }

#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
  if (first_free_slot < ARRAY_SIZE(key_pool)) {
    keys     = &key_pool[first_free_slot];
    keys->id = id;
    bt_addr_le_copy(&keys->addr, addr);
#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
    keys->aging_counter = ++aging_counter_val;
    last_keys_updated   = keys;
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
    BT_DBG("created %p for %s", keys, bt_addr_le_str(addr));
    return keys;
  }

  BT_DBG("unable to create keys for %s", bt_addr_le_str(addr));

  return NULL;
}

void bt_foreach_bond(u8_t id, void (*func)(const struct bt_bond_info *info, void *user_data), void *user_data) {
  int i;

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    struct bt_keys *keys = &key_pool[i];

    if (keys->keys && keys->id == id) {
      struct bt_bond_info info;

      bt_addr_le_copy(&info.addr, &keys->addr);
      func(&info, user_data);
    }
  }
}

void bt_keys_foreach(int type, void (*func)(struct bt_keys *keys, void *data), void *data) {
  int i;

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    if ((key_pool[i].keys & type)) {
      func(&key_pool[i], data);
    }
  }
}

struct bt_keys *bt_keys_find(int type, u8_t id, const bt_addr_le_t *addr) {
  int i;

  BT_DBG("type %d %s", type, bt_addr_le_str(addr));

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    if ((key_pool[i].keys & type) && key_pool[i].id == id && !bt_addr_le_cmp(&key_pool[i].addr, addr)) {
      return &key_pool[i];
    }
  }

  return NULL;
}

struct bt_keys *bt_keys_get_type(int type, u8_t id, const bt_addr_le_t *addr) {
  struct bt_keys *keys;

  BT_DBG("type %d %s", type, bt_addr_le_str(addr));

  keys = bt_keys_find(type, id, addr);
  if (keys) {
    return keys;
  }

  keys = bt_keys_get_addr(id, addr);
  if (!keys) {
    return NULL;
  }

  bt_keys_add_type(keys, type);

  return keys;
}

struct bt_keys *bt_keys_find_irk(u8_t id, const bt_addr_le_t *addr) {
  int i;

  BT_DBG("%s", bt_addr_le_str(addr));

  if (!bt_addr_le_is_rpa(addr)) {
    return NULL;
  }

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    if (!(key_pool[i].keys & BT_KEYS_IRK)) {
      continue;
    }

    if (key_pool[i].id == id && !bt_addr_cmp(&addr->a, &key_pool[i].irk.rpa)) {
      BT_DBG("cached RPA %s for %s", bt_addr_str(&key_pool[i].irk.rpa), bt_addr_le_str(&key_pool[i].addr));
      return &key_pool[i];
    }
  }

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    if (!(key_pool[i].keys & BT_KEYS_IRK)) {
      continue;
    }

    if (key_pool[i].id != id) {
      continue;
    }

    if (bt_rpa_irk_matches(key_pool[i].irk.val, &addr->a)) {
      BT_DBG("RPA %s matches %s", bt_addr_str(&key_pool[i].irk.rpa), bt_addr_le_str(&key_pool[i].addr));

      bt_addr_copy(&key_pool[i].irk.rpa, &addr->a);

      return &key_pool[i];
    }
  }

  BT_DBG("No IRK for %s", bt_addr_le_str(addr));

  return NULL;
}

struct bt_keys *bt_keys_find_addr(u8_t id, const bt_addr_le_t *addr) {
  int i;

  BT_DBG("%s", bt_addr_le_str(addr));

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    if (key_pool[i].id == id && !bt_addr_le_cmp(&key_pool[i].addr, addr)) {
      return &key_pool[i];
    }
  }

  return NULL;
}

#if defined(CONFIG_BLE_AT_CMD)
bt_addr_le_t *bt_get_keys_address(u8_t id) {
  bt_addr_le_t addr;

  memset(&addr, 0, sizeof(bt_addr_le_t));
  if (id < ARRAY_SIZE(key_pool)) {
    if (bt_addr_le_cmp(&key_pool[id].addr, &addr)) {
      return &key_pool[id].addr;
    }
  }

  return NULL;
}
#endif

void bt_keys_add_type(struct bt_keys *keys, int type) { keys->keys |= type; }

void bt_keys_clear(struct bt_keys *keys) {
#if defined(BFLB_BLE)
  if (keys->keys & BT_KEYS_IRK) {
    bt_id_del(keys);
  }

  memset(keys, 0, sizeof(*keys));

#if defined(CONFIG_BT_SETTINGS)
  ef_del_env(NV_KEY_POOL);
#endif
#else
  BT_DBG("%s (keys 0x%04x)", bt_addr_le_str(&keys->addr), keys->keys);

  if (keys->keys & BT_KEYS_IRK) {
    bt_id_del(keys);
  }

  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    char key[BT_SETTINGS_KEY_MAX];

    /* Delete stored keys from flash */
    if (keys->id) {
      char id[4];

      u8_to_dec(id, sizeof(id), keys->id);
      bt_settings_encode_key(key, sizeof(key), "keys", &keys->addr, id);
    } else {
      bt_settings_encode_key(key, sizeof(key), "keys", &keys->addr, NULL);
    }

    BT_DBG("Deleting key %s", log_strdup(key));
    settings_delete(key);
  }

  (void)memset(keys, 0, sizeof(*keys));
#endif
}

static void keys_clear_id(struct bt_keys *keys, void *data) {
  u8_t *id = data;

  if (*id == keys->id) {
    if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
      bt_gatt_clear(*id, &keys->addr);
    }

    bt_keys_clear(keys);
  }
}

void bt_keys_clear_all(u8_t id) { bt_keys_foreach(BT_KEYS_ALL, keys_clear_id, &id); }

#if defined(CONFIG_BT_SETTINGS)
int bt_keys_store(struct bt_keys *keys) {
#if defined(BFLB_BLE)
  int err;
  err = bt_settings_set_bin(NV_KEY_POOL, (const u8_t *)&key_pool[0], sizeof(key_pool));
  return err;
#else
  char  val[BT_SETTINGS_SIZE(BT_KEYS_STORAGE_LEN)];
  char  key[BT_SETTINGS_KEY_MAX];
  char *str;
  int   err;

  str = settings_str_from_bytes(keys->storage_start, BT_KEYS_STORAGE_LEN, val, sizeof(val));
  if (!str) {
    BT_ERR("Unable to encode bt_keys as value");
    return -EINVAL;
  }

  if (keys->id) {
    char id[4];

    u8_to_dec(id, sizeof(id), keys->id);
    bt_settings_encode_key(key, sizeof(key), "keys", &keys->addr, id);
  } else {
    bt_settings_encode_key(key, sizeof(key), "keys", &keys->addr, NULL);
  }

  err = settings_save_one(key, keys->storage_start, BT_KEYS_STORAGE_LEN);
  if (err) {
    BT_ERR("Failed to save keys (err %d)", err);
    return err;
  }

  BT_DBG("Stored keys for %s (%s)", bt_addr_le_str(&keys->addr), log_strdup(key));

  return 0;
#endif // BFLB_BLE
}

#if !defined(BFLB_BLE)
static int keys_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) {
  struct bt_keys *keys;
  bt_addr_le_t    addr;
  u8_t            id;
  size_t          len;
  int             err;
  char            val[BT_KEYS_STORAGE_LEN];
  const char     *next;

  if (!name) {
    BT_ERR("Insufficient number of arguments");
    return -EINVAL;
  }

  len = read_cb(cb_arg, val, sizeof(val));
  if (len < 0) {
    BT_ERR("Failed to read value (err %zu)", len);
    return -EINVAL;
  }

  BT_DBG("name %s val %s", log_strdup(name), (len) ? bt_hex(val, sizeof(val)) : "(null)");

  err = bt_settings_decode_key(name, &addr);
  if (err) {
    BT_ERR("Unable to decode address %s", name);
    return -EINVAL;
  }

  settings_name_next(name, &next);

  if (!next) {
    id = BT_ID_DEFAULT;
  } else {
    id = strtol(next, NULL, 10);
  }

  if (!len) {
    keys = bt_keys_find(BT_KEYS_ALL, id, &addr);
    if (keys) {
      (void)memset(keys, 0, sizeof(*keys));
      BT_DBG("Cleared keys for %s", bt_addr_le_str(&addr));
    } else {
      BT_WARN("Unable to find deleted keys for %s", bt_addr_le_str(&addr));
    }

    return 0;
  }

  keys = bt_keys_get_addr(id, &addr);
  if (!keys) {
    BT_ERR("Failed to allocate keys for %s", bt_addr_le_str(&addr));
    return -ENOMEM;
  }
  if (len != BT_KEYS_STORAGE_LEN) {
    do {
      /* Load shorter structure for compatibility with old
       * records format with no counter.
       */
      if (IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST) && len == BT_KEYS_STORAGE_LEN_COMPAT) {
        BT_WARN("Keys for %s have no aging counter", bt_addr_le_str(&addr));
        memcpy(keys->storage_start, val, len);
        continue;
      }

      BT_ERR("Invalid key length %zu != %zu", len, BT_KEYS_STORAGE_LEN);
      bt_keys_clear(keys);

      return -EINVAL;
    } while (0);
  } else {
    memcpy(keys->storage_start, val, len);
  }

  BT_DBG("Successfully restored keys for %s", bt_addr_le_str(&addr));
#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
  if (aging_counter_val < keys->aging_counter) {
    aging_counter_val = keys->aging_counter;
  }
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
  return 0;
}
#endif //!(BFLB_BLE)

static void id_add(struct bt_keys *keys, void *user_data) { bt_id_add(keys); }

#if defined(BFLB_BLE)
int keys_commit(void)
#else
static int keys_commit(void)
#endif
{
  BT_DBG("");

  /* We do this in commit() rather than add() since add() may get
   * called multiple times for the same address, especially if
   * the keys were already removed.
   */
  bt_keys_foreach(BT_KEYS_IRK, id_add, NULL);

  return 0;
}

// SETTINGS_STATIC_HANDLER_DEFINE(bt_keys, "bt/keys", NULL, keys_set, keys_commit,
//			       NULL);

#if defined(BFLB_BLE)
int bt_keys_load(void) { return bt_settings_get_bin(NV_KEY_POOL, (u8_t *)&key_pool[0], sizeof(key_pool), NULL); }
#endif

#endif /* CONFIG_BT_SETTINGS */

#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
void bt_keys_update_usage(u8_t id, const bt_addr_le_t *addr) {
  struct bt_keys *keys = bt_keys_find_addr(id, addr);

  if (!keys) {
    return;
  }

  if (last_keys_updated == keys) {
    return;
  }

  keys->aging_counter = ++aging_counter_val;
  last_keys_updated   = keys;

  BT_DBG("Aging counter for %s is set to %u", bt_addr_le_str(addr), keys->aging_counter);

  if (IS_ENABLED(CONFIG_BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING)) {
    bt_keys_store(keys);
  }
}

#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/keys.h
================================================
/* keys.h - Bluetooth key handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

enum {
    BT_KEYS_SLAVE_LTK = BIT(0),
    BT_KEYS_IRK = BIT(1),
    BT_KEYS_LTK = BIT(2),
    BT_KEYS_LOCAL_CSRK = BIT(3),
    BT_KEYS_REMOTE_CSRK = BIT(4),
    BT_KEYS_LTK_P256 = BIT(5),

    BT_KEYS_ALL = (BT_KEYS_SLAVE_LTK | BT_KEYS_IRK |
                   BT_KEYS_LTK | BT_KEYS_LOCAL_CSRK |
                   BT_KEYS_REMOTE_CSRK | BT_KEYS_LTK_P256),
};

enum {
    BT_KEYS_AUTHENTICATED = BIT(0),
    BT_KEYS_DEBUG = BIT(1),
    BT_KEYS_ID_PENDING_ADD = BIT(2),
    BT_KEYS_ID_PENDING_DEL = BIT(3),
    BT_KEYS_SC = BIT(4),
};

struct bt_ltk {
    u8_t rand[8];
    u8_t ediv[2];
    u8_t val[16];
};

struct bt_irk {
    u8_t val[16];
    bt_addr_t rpa;
};

struct bt_csrk {
    u8_t val[16];
    u32_t cnt;
};

struct bt_keys {
    u8_t id;
    bt_addr_le_t addr;
#if !defined(BFLB_BLE)
    u8_t storage_start[0];
#endif
    u8_t enc_size;
    u8_t flags;
    u16_t keys;
    struct bt_ltk ltk;
    struct bt_irk irk;
#if defined(CONFIG_BT_SIGNING)
    struct bt_csrk local_csrk;
    struct bt_csrk remote_csrk;
#endif /* BT_SIGNING */
#if !defined(CONFIG_BT_SMP_SC_PAIR_ONLY)
    struct bt_ltk slave_ltk;
#endif /* CONFIG_BT_SMP_SC_PAIR_ONLY */
#if (defined(CONFIG_BT_KEYS_OVERWRITE_OLDEST))
    u32_t aging_counter;
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
};

#if !defined(BFLB_BLE)
#define BT_KEYS_STORAGE_LEN (sizeof(struct bt_keys) - \
                             offsetof(struct bt_keys, storage_start))
#endif

void bt_keys_foreach(int type, void (*func)(struct bt_keys *keys, void *data),
                     void *data);

struct bt_keys *bt_keys_get_addr(u8_t id, const bt_addr_le_t *addr);
struct bt_keys *bt_keys_get_type(int type, u8_t id, const bt_addr_le_t *addr);
struct bt_keys *bt_keys_find(int type, u8_t id, const bt_addr_le_t *addr);
struct bt_keys *bt_keys_find_irk(u8_t id, const bt_addr_le_t *addr);
struct bt_keys *bt_keys_find_addr(u8_t id, const bt_addr_le_t *addr);
#if defined(CONFIG_BLE_AT_CMD)
bt_addr_le_t *bt_get_keys_address(u8_t id);
#endif

void bt_keys_add_type(struct bt_keys *keys, int type);
void bt_keys_clear(struct bt_keys *keys);
void bt_keys_clear_all(u8_t id);
#if defined(BFLB_BLE)
int keys_commit(void);
int bt_keys_load(void);
#endif

#if defined(CONFIG_BT_SETTINGS)
int bt_keys_store(struct bt_keys *keys);
#else
static inline int bt_keys_store(struct bt_keys *keys)
{
    return 0;
}
#endif

enum {
    BT_LINK_KEY_AUTHENTICATED = BIT(0),
    BT_LINK_KEY_DEBUG = BIT(1),
    BT_LINK_KEY_SC = BIT(2),
};

struct bt_keys_link_key {
    bt_addr_t addr;
    u8_t flags;
    u8_t val[16];
};

struct bt_keys_link_key *bt_keys_get_link_key(const bt_addr_t *addr);
struct bt_keys_link_key *bt_keys_find_link_key(const bt_addr_t *addr);
void bt_keys_link_key_clear(struct bt_keys_link_key *link_key);
void bt_keys_link_key_clear_addr(const bt_addr_t *addr);

/* This function is used to signal that the key has been used for paring */
/* It updates the aging counter and saves it to flash if configuration option */
/* BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING is enabled */
void bt_keys_update_usage(u8_t id, const bt_addr_le_t *addr);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/keys_br.c
================================================
/* keys_br.c - Bluetooth BR/EDR key handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 

#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_KEYS)
#define LOG_MODULE_NAME bt_keys_br
#include "log.h"

#include "hci_core.h"
#include "keys.h"
#include "settings.h"

static struct bt_keys_link_key key_pool[CONFIG_BT_MAX_PAIRED];

#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
static uint32_t                 aging_counter_val;
static struct bt_keys_link_key *last_keys_updated;
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */

struct bt_keys_link_key *bt_keys_find_link_key(const bt_addr_t *addr) {
  struct bt_keys_link_key *key;
  int                      i;

  BT_DBG("%s", bt_addr_str(addr));

  for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
    key = &key_pool[i];

    if (!bt_addr_cmp(&key->addr, addr)) {
      return key;
    }
  }

  return NULL;
}

struct bt_keys_link_key *bt_keys_get_link_key(const bt_addr_t *addr) {
  struct bt_keys_link_key *key;

  key = bt_keys_find_link_key(addr);
  if (key) {
    return key;
  }

  key = bt_keys_find_link_key(BT_ADDR_ANY);
#if 0 // IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST) //MBHJ
	if (!key) {
		int i;

		key = &key_pool[0];
		for (i = 1; i < ARRAY_SIZE(key_pool); i++) {
			struct bt_keys_link_key *current = &key_pool[i];

			if (current->aging_counter < key->aging_counter) {
				key = current;
			}
		}

		if (key) {
			bt_keys_link_key_clear(key);
		}
	}
#endif

  if (key) {
    bt_addr_copy(&key->addr, addr);
#if 0 // IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST) //MBHJ
		key->aging_counter = ++aging_counter_val;
		last_keys_updated = key;
#endif
    BT_DBG("created %p for %s", key, bt_addr_str(addr));
    return key;
  }

  BT_DBG("unable to create keys for %s", bt_addr_str(addr));

  return NULL;
}

void bt_keys_link_key_clear(struct bt_keys_link_key *link_key) {
  if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
    char         key[BT_SETTINGS_KEY_MAX];
    bt_addr_le_t le_addr;

    le_addr.type = BT_ADDR_LE_PUBLIC;
    bt_addr_copy(&le_addr.a, &link_key->addr);
    bt_settings_encode_key(key, sizeof(key), "link_key", &le_addr, NULL);
    settings_delete(key);
  }

  BT_DBG("%s", bt_addr_str(&link_key->addr));
  (void)memset(link_key, 0, sizeof(*link_key));
}

void bt_keys_link_key_clear_addr(const bt_addr_t *addr) {
  int                      i;
  struct bt_keys_link_key *key;

  if (!addr) {
    for (i = 0; i < ARRAY_SIZE(key_pool); i++) {
      key = &key_pool[i];
      bt_keys_link_key_clear(key);
    }
    return;
  }

  key = bt_keys_find_link_key(addr);
  if (key) {
    bt_keys_link_key_clear(key);
  }
}

void bt_keys_link_key_store(struct bt_keys_link_key *link_key) {
#if 0 // MBHJ
	if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
		int err;
		char key[BT_SETTINGS_KEY_MAX];
		bt_addr_le_t le_addr;

		le_addr.type = BT_ADDR_LE_PUBLIC;
		bt_addr_copy(&le_addr.a, &link_key->addr);
		bt_settings_encode_key(key, sizeof(key), "link_key",
				       &le_addr, NULL);

		err = settings_save_one(key, link_key->storage_start,
					BT_KEYS_LINK_KEY_STORAGE_LEN);
		if (err) {
			BT_ERR("Failed to svae link key (err %d)", err);
		}
	}
#endif
}

#if defined(CONFIG_BT_SETTINGS)

static int link_key_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) {
  int                      err;
  ssize_t                  len;
  bt_addr_le_t             le_addr;
  struct bt_keys_link_key *link_key;
  char                     val[BT_KEYS_LINK_KEY_STORAGE_LEN];

  if (!name) {
    BT_ERR("Insufficient number of arguments");
    return -EINVAL;
  }

  len = read_cb(cb_arg, val, sizeof(val));
  if (len < 0) {
    BT_ERR("Failed to read value (err %zu)", len);
    return -EINVAL;
  }

  BT_DBG("name %s val %s", log_strdup(name), len ? bt_hex(val, sizeof(val)) : "(null)");

  err = bt_settings_decode_key(name, &le_addr);
  if (err) {
    BT_ERR("Unable to decode address %s", name);
    return -EINVAL;
  }

  link_key = bt_keys_get_link_key(&le_addr.a);
  if (len != BT_KEYS_LINK_KEY_STORAGE_LEN) {
    if (link_key) {
      bt_keys_link_key_clear(link_key);
      BT_DBG("Clear keys for %s", bt_addr_le_str(&le_addr));
    } else {
      BT_WARN("Unable to find deleted keys for %s", bt_addr_le_str(&le_addr));
    }

    return 0;
  }

  memcpy(link_key->storage_start, val, len);
  BT_DBG("Successfully restored link key for %s", bt_addr_le_str(&le_addr));
#if IS_ENABLED(CONFIG_BT_KEYS_OVERWRITE_OLDEST)
  if (aging_counter_val < link_key->aging_counter) {
    aging_counter_val = link_key->aging_counter;
  }
#endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */

  return 0;
}

static int link_key_commit(void) { return 0; }

SETTINGS_STATIC_HANDLER_DEFINE(bt_link_key, "bt/link_key", NULL, link_key_set, link_key_commit, NULL);

void bt_keys_link_key_update_usage(const bt_addr_t *addr) {
  struct bt_keys_link_key *link_key = bt_keys_find_link_key(addr);

  if (!link_key) {
    return;
  }

  if (last_keys_updated == link_key) {
    return;
  }

  link_key->aging_counter = ++aging_counter_val;
  last_keys_updated       = link_key;

  BT_DBG("Aging counter for %s is set to %u", bt_addr_str(addr), link_key->aging_counter);

  if (IS_ENABLED(CONFIG_BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING)) {
    bt_keys_link_key_store(link_key);
  }
}

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/l2cap.c
================================================
/* l2cap.c - L2CAP handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 
#include 

#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_L2CAP)
#define LOG_MODULE_NAME bt_l2cap
#include "log.h"

#include "conn_internal.h"
#include "hci_core.h"
#include "l2cap_internal.h"

#include "ble_config.h"

#define LE_CHAN_RTX(_w) CONTAINER_OF(_w, struct bt_l2cap_le_chan, chan.rtx_work)
#define CHAN_RX(_w)     CONTAINER_OF(_w, struct bt_l2cap_le_chan, rx_work)

#define L2CAP_LE_MIN_MTU 23

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
#define L2CAP_LE_MAX_CREDITS (CONFIG_BT_ACL_RX_COUNT - 1)
#else
#define L2CAP_LE_MAX_CREDITS (CONFIG_BT_RX_BUF_COUNT - 1)
#endif

#define L2CAP_LE_CID_DYN_START    0x0040
#define L2CAP_LE_CID_DYN_END      0x007f
#define L2CAP_LE_CID_IS_DYN(_cid) (_cid >= L2CAP_LE_CID_DYN_START && _cid <= L2CAP_LE_CID_DYN_END)

#define L2CAP_LE_PSM_FIXED_START 0x0001
#define L2CAP_LE_PSM_FIXED_END   0x007f
#define L2CAP_LE_PSM_DYN_START   0x0080
#define L2CAP_LE_PSM_DYN_END     0x00ff

#define L2CAP_CONN_TIMEOUT K_SECONDS(40)
#define L2CAP_DISC_TIMEOUT K_SECONDS(2)

#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
static sys_slist_t le_channels;
#endif

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
/* Size of MTU is based on the maximum amount of data the buffer can hold
 * excluding ACL and driver headers.
 */
#define L2CAP_MAX_LE_MPS BT_L2CAP_RX_MTU
/* For now use MPS - SDU length to disable segmentation */
#define L2CAP_MAX_LE_MTU (L2CAP_MAX_LE_MPS - 2)

#define l2cap_lookup_ident(conn, ident) __l2cap_lookup_ident(conn, ident, false)
#define l2cap_remove_ident(conn, ident) __l2cap_lookup_ident(conn, ident, true)

static sys_slist_t servers;

#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

/* L2CAP signalling channel specific context */
struct bt_l2cap {
  /* The channel this context is associated with */
  struct bt_l2cap_le_chan chan;
};

static struct bt_l2cap bt_l2cap_pool[CONFIG_BT_MAX_CONN];

static u8_t get_ident(void) {
  static u8_t ident;

  ident++;
  /* handle integer overflow (0 is not valid) */
  if (!ident) {
    ident++;
  }

  return ident;
}

#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
void bt_l2cap_le_fixed_chan_register(struct bt_l2cap_fixed_chan *chan) {
  BT_DBG("CID 0x%04x", chan->cid);

  sys_slist_append(&le_channels, &chan->node);
}
#endif

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static struct bt_l2cap_le_chan *l2cap_chan_alloc_cid(struct bt_conn *conn, struct bt_l2cap_chan *chan) {
  struct bt_l2cap_le_chan *ch = BT_L2CAP_LE_CHAN(chan);
  u16_t                    cid;

  /*
   * No action needed if there's already a CID allocated, e.g. in
   * the case of a fixed channel.
   */
  if (ch && ch->rx.cid > 0) {
    return ch;
  }

  for (cid = L2CAP_LE_CID_DYN_START; cid <= L2CAP_LE_CID_DYN_END; cid++) {
    if (ch && !bt_l2cap_le_lookup_rx_cid(conn, cid)) {
      ch->rx.cid = cid;
      return ch;
    }
  }

  return NULL;
}

static struct bt_l2cap_le_chan *__l2cap_lookup_ident(struct bt_conn *conn, u16_t ident, bool remove) {
  struct bt_l2cap_chan *chan;
  sys_snode_t          *prev = NULL;

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
    if (chan->ident == ident) {
      if (remove) {
        sys_slist_remove(&conn->channels, prev, &chan->node);
      }
      return BT_L2CAP_LE_CHAN(chan);
    }

    prev = &chan->node;
  }

  return NULL;
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

void bt_l2cap_chan_remove(struct bt_conn *conn, struct bt_l2cap_chan *ch) {
  struct bt_l2cap_chan *chan;
  sys_snode_t          *prev = NULL;

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
    if (chan == ch) {
      sys_slist_remove(&conn->channels, prev, &chan->node);
      return;
    }

    prev = &chan->node;
  }
}

const char *bt_l2cap_chan_state_str(bt_l2cap_chan_state_t state) {
  switch (state) {
  case BT_L2CAP_DISCONNECTED:
    return "disconnected";
  case BT_L2CAP_CONNECT:
    return "connect";
  case BT_L2CAP_CONFIG:
    return "config";
  case BT_L2CAP_CONNECTED:
    return "connected";
  case BT_L2CAP_DISCONNECT:
    return "disconnect";
  default:
    return "unknown";
  }
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
#if defined(CONFIG_BT_DEBUG_L2CAP)
void bt_l2cap_chan_set_state_debug(struct bt_l2cap_chan *chan, bt_l2cap_chan_state_t state, const char *func, int line) {
  BT_DBG("chan %p psm 0x%04x %s -> %s", chan, chan->psm, bt_l2cap_chan_state_str(chan->state), bt_l2cap_chan_state_str(state));

  /* check transitions validness */
  switch (state) {
  case BT_L2CAP_DISCONNECTED:
    /* regardless of old state always allows this state */
    break;
  case BT_L2CAP_CONNECT:
    if (chan->state != BT_L2CAP_DISCONNECTED) {
      BT_WARN("%s()%d: invalid transition", func, line);
    }
    break;
  case BT_L2CAP_CONFIG:
    if (chan->state != BT_L2CAP_CONNECT) {
      BT_WARN("%s()%d: invalid transition", func, line);
    }
    break;
  case BT_L2CAP_CONNECTED:
    if (chan->state != BT_L2CAP_CONFIG && chan->state != BT_L2CAP_CONNECT) {
      BT_WARN("%s()%d: invalid transition", func, line);
    }
    break;
  case BT_L2CAP_DISCONNECT:
    if (chan->state != BT_L2CAP_CONFIG && chan->state != BT_L2CAP_CONNECTED) {
      BT_WARN("%s()%d: invalid transition", func, line);
    }
    break;
  default:
    BT_ERR("%s()%d: unknown (%u) state was set", func, line, state);
    return;
  }

  chan->state = state;
}
#else
void bt_l2cap_chan_set_state(struct bt_l2cap_chan *chan, bt_l2cap_chan_state_t state) { chan->state = state; }
#endif /* CONFIG_BT_DEBUG_L2CAP */
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

void bt_l2cap_chan_del(struct bt_l2cap_chan *chan) {
  BT_DBG("conn %p chan %p", chan->conn, chan);

  if (!chan->conn) {
    goto destroy;
  }

  if (chan->ops->disconnected) {
    chan->ops->disconnected(chan);
  }

  chan->conn = NULL;

destroy:
#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
  /* Reset internal members of common channel */
  bt_l2cap_chan_set_state(chan, BT_L2CAP_DISCONNECTED);
  chan->psm = 0U;
#endif

  if (chan->destroy) {
    chan->destroy(chan);
  }

#ifdef BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
  if (chan->rtx_work.timer.timer.hdl)
    k_delayed_work_del_timer(&chan->rtx_work);
#endif
}

static void l2cap_rtx_timeout(struct k_work *work) {
  struct bt_l2cap_le_chan *chan = LE_CHAN_RTX(work);

  BT_ERR("chan %p timeout", chan);

  bt_l2cap_chan_remove(chan->chan.conn, &chan->chan);
  bt_l2cap_chan_del(&chan->chan);
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static void l2cap_chan_le_recv(struct bt_l2cap_le_chan *chan, struct net_buf *buf);

static void l2cap_rx_process(struct k_work *work) {
  struct bt_l2cap_le_chan *ch = CHAN_RX(work);
  struct net_buf          *buf;

  while ((buf = net_buf_get(&ch->rx_queue, K_NO_WAIT))) {
    BT_DBG("ch %p buf %p", ch, buf);
    l2cap_chan_le_recv(ch, buf);
    net_buf_unref(buf);
  }
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

void bt_l2cap_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan, bt_l2cap_chan_destroy_t destroy) {
  /* Attach channel to the connection */
  sys_slist_append(&conn->channels, &chan->node);
  chan->conn    = conn;
  chan->destroy = destroy;

  BT_DBG("conn %p chan %p", conn, chan);
}

static bool l2cap_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan, bt_l2cap_chan_destroy_t destroy) {
  struct bt_l2cap_le_chan *ch;

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
  ch = l2cap_chan_alloc_cid(conn, chan);
#else
  ch = BT_L2CAP_LE_CHAN(chan);
#endif

  if (!ch) {
    BT_ERR("Unable to allocate L2CAP CID");
    return false;
  }

  k_delayed_work_init(&chan->rtx_work, l2cap_rtx_timeout);

  bt_l2cap_chan_add(conn, chan, destroy);

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
  if (L2CAP_LE_CID_IS_DYN(ch->rx.cid)) {
    k_work_init(&ch->rx_work, l2cap_rx_process);
    k_fifo_init(&ch->rx_queue, 20);
    bt_l2cap_chan_set_state(chan, BT_L2CAP_CONNECT);
  }
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

  return true;
}

void bt_l2cap_connected(struct bt_conn *conn) {
#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
  struct bt_l2cap_fixed_chan *fchan;
#endif
  struct bt_l2cap_chan *chan;

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    bt_l2cap_br_connected(conn);
    return;
  }

#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
  SYS_SLIST_FOR_EACH_CONTAINER(&le_channels, fchan, node) {
#else
  Z_STRUCT_SECTION_FOREACH(bt_l2cap_fixed_chan, fchan) {
#endif
    struct bt_l2cap_le_chan *ch;

    if (fchan->accept(conn, &chan) < 0) {
      continue;
    }

    ch = BT_L2CAP_LE_CHAN(chan);

    /* Fill up remaining fixed channel context attached in
     * fchan->accept()
     */
    ch->rx.cid = fchan->cid;
    ch->tx.cid = fchan->cid;

    if (!l2cap_chan_add(conn, chan, NULL)) {
      return;
    }

    if (chan->ops->connected) {
      chan->ops->connected(chan);
    }

    /* Always set output status to fixed channels */
    atomic_set_bit(chan->status, BT_L2CAP_STATUS_OUT);

    if (chan->ops->status) {
      chan->ops->status(chan, chan->status);
    }
  }
}

void bt_l2cap_disconnected(struct bt_conn *conn) {
  struct bt_l2cap_chan *chan, *next;

  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&conn->channels, chan, next, node) { bt_l2cap_chan_del(chan); }
}

static struct net_buf *l2cap_create_le_sig_pdu(struct net_buf *buf, u8_t code, u8_t ident, u16_t len) {
  struct bt_l2cap_sig_hdr *hdr;

  /* Don't wait more than the minimum RTX timeout of 2 seconds */
  buf = bt_l2cap_create_pdu_timeout(NULL, 0, K_SECONDS(2));
  if (!buf) {
    /* If it was not possible to allocate a buffer within the
     * timeout return NULL.
     */
    BT_ERR("Unable to allocate buffer for op 0x%02x", code);
    return NULL;
  }

  hdr        = net_buf_add(buf, sizeof(*hdr));
  hdr->code  = code;
  hdr->ident = ident;
  hdr->len   = sys_cpu_to_le16(len);

  return buf;
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static void l2cap_chan_send_req(struct bt_l2cap_le_chan *chan, struct net_buf *buf, s32_t timeout) {
  /* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part A] page 126:
   *
   * The value of this timer is implementation-dependent but the minimum
   * initial value is 1 second and the maximum initial value is 60
   * seconds. One RTX timer shall exist for each outstanding signaling
   * request, including each Echo Request. The timer disappears on the
   * final expiration, when the response is received, or the physical
   * link is lost.
   */
  if (timeout) {
    k_delayed_work_submit(&chan->chan.rtx_work, timeout);
  } else {
    k_delayed_work_cancel(&chan->chan.rtx_work);
  }

  bt_l2cap_send(chan->chan.conn, BT_L2CAP_CID_LE_SIG, buf);
}

static int l2cap_le_conn_req(struct bt_l2cap_le_chan *ch) {
  struct net_buf              *buf;
  struct bt_l2cap_le_conn_req *req;

  ch->chan.ident = get_ident();

  buf = l2cap_create_le_sig_pdu(NULL, BT_L2CAP_LE_CONN_REQ, ch->chan.ident, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req          = net_buf_add(buf, sizeof(*req));
  req->psm     = sys_cpu_to_le16(ch->chan.psm);
  req->scid    = sys_cpu_to_le16(ch->rx.cid);
  req->mtu     = sys_cpu_to_le16(ch->rx.mtu);
  req->mps     = sys_cpu_to_le16(ch->rx.mps);
  req->credits = sys_cpu_to_le16(ch->rx.init_credits);

  l2cap_chan_send_req(ch, buf, L2CAP_CONN_TIMEOUT);

  return 0;
}

static void l2cap_le_encrypt_change(struct bt_l2cap_chan *chan, u8_t status) {
  /* Skip channels already connected or with a pending request */
  if (chan->state != BT_L2CAP_CONNECT || chan->ident) {
    return;
  }

  if (status) {
    bt_l2cap_chan_remove(chan->conn, chan);
    bt_l2cap_chan_del(chan);
    return;
  }

  /* Retry to connect */
  l2cap_le_conn_req(BT_L2CAP_LE_CHAN(chan));
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

void bt_l2cap_encrypt_change(struct bt_conn *conn, u8_t hci_status) {
  struct bt_l2cap_chan *chan;

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    l2cap_br_encrypt_change(conn, hci_status);
    return;
  }

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
    l2cap_le_encrypt_change(chan, hci_status);
#endif

    if (chan->ops->encrypt_change) {
      chan->ops->encrypt_change(chan, hci_status);
    }
  }
}

struct net_buf *bt_l2cap_create_pdu_timeout(struct net_buf_pool *pool, size_t reserve, s32_t timeout) { return bt_conn_create_pdu_timeout(pool, sizeof(struct bt_l2cap_hdr) + reserve, timeout); }

int bt_l2cap_send_cb(struct bt_conn *conn, u16_t cid, struct net_buf *buf, bt_conn_tx_cb_t cb, void *user_data) {
  struct bt_l2cap_hdr *hdr;

  BT_DBG("conn %p cid %u len %zu", conn, cid, net_buf_frags_len(buf));

  hdr      = net_buf_push(buf, sizeof(*hdr));
  hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
  hdr->cid = sys_cpu_to_le16(cid);

  return bt_conn_send_cb(conn, buf, cb, user_data);
}

static void l2cap_send_reject(struct bt_conn *conn, u8_t ident, u16_t reason, void *data, u8_t data_len) {
  struct bt_l2cap_cmd_reject *rej;
  struct net_buf             *buf;

  buf = l2cap_create_le_sig_pdu(NULL, BT_L2CAP_CMD_REJECT, ident, sizeof(*rej) + data_len);
  if (!buf) {
    return;
  }

  rej         = net_buf_add(buf, sizeof(*rej));
  rej->reason = sys_cpu_to_le16(reason);

  if (data) {
    net_buf_add_mem(buf, data, data_len);
  }

  bt_l2cap_send(conn, BT_L2CAP_CID_LE_SIG, buf);
}

static void le_conn_param_rsp(struct bt_l2cap *l2cap, struct net_buf *buf) {
  struct bt_l2cap_conn_param_rsp *rsp = (void *)buf->data;

  if (buf->len < sizeof(*rsp)) {
    BT_ERR("Too small LE conn param rsp");
    return;
  }

  BT_DBG("LE conn param rsp result %u", sys_le16_to_cpu(rsp->result));
}

static void le_conn_param_update_req(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn                 *conn = l2cap->chan.chan.conn;
  struct bt_le_conn_param         param;
  struct bt_l2cap_conn_param_rsp *rsp;
  struct bt_l2cap_conn_param_req *req = (void *)buf->data;
  bool                            accepted;

  if (buf->len < sizeof(*req)) {
    BT_ERR("Too small LE conn update param req");
    return;
  }

  if (conn->role != BT_HCI_ROLE_MASTER) {
    l2cap_send_reject(conn, ident, BT_L2CAP_REJ_NOT_UNDERSTOOD, NULL, 0);
    return;
  }

  param.interval_min = sys_le16_to_cpu(req->min_interval);
  param.interval_max = sys_le16_to_cpu(req->max_interval);
  param.latency      = sys_le16_to_cpu(req->latency);
  param.timeout      = sys_le16_to_cpu(req->timeout);

  BT_DBG("min 0x%04x max 0x%04x latency: 0x%04x timeout: 0x%04x", param.interval_min, param.interval_max, param.latency, param.timeout);

  buf = l2cap_create_le_sig_pdu(buf, BT_L2CAP_CONN_PARAM_RSP, ident, sizeof(*rsp));
  if (!buf) {
    return;
  }

  accepted = le_param_req(conn, ¶m);

  rsp = net_buf_add(buf, sizeof(*rsp));
  if (accepted) {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_CONN_PARAM_ACCEPTED);
  } else {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_CONN_PARAM_REJECTED);
  }

  bt_l2cap_send(conn, BT_L2CAP_CID_LE_SIG, buf);

  if (accepted) {
    bt_conn_le_conn_update(conn, ¶m);
  }
}

struct bt_l2cap_chan *bt_l2cap_le_lookup_tx_cid(struct bt_conn *conn, u16_t cid) {
  struct bt_l2cap_chan *chan;

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
    if (BT_L2CAP_LE_CHAN(chan)->tx.cid == cid) {
      return chan;
    }
  }

  return NULL;
}

struct bt_l2cap_chan *bt_l2cap_le_lookup_rx_cid(struct bt_conn *conn, u16_t cid) {
  struct bt_l2cap_chan *chan;

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
    if (BT_L2CAP_LE_CHAN(chan)->rx.cid == cid) {
      return chan;
    }
  }

  return NULL;
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static struct bt_l2cap_server *l2cap_server_lookup_psm(u16_t psm) {
  struct bt_l2cap_server *server;

  SYS_SLIST_FOR_EACH_CONTAINER(&servers, server, node) {
    if (server->psm == psm) {
      return server;
    }
  }

  return NULL;
}

int bt_l2cap_server_register(struct bt_l2cap_server *server) {
  if (!server->accept) {
    return -EINVAL;
  }

  if (server->psm) {
    if (server->psm < L2CAP_LE_PSM_FIXED_START || server->psm > L2CAP_LE_PSM_DYN_END) {
      return -EINVAL;
    }

    /* Check if given PSM is already in use */
    if (l2cap_server_lookup_psm(server->psm)) {
      BT_DBG("PSM already registered");
      return -EADDRINUSE;
    }
  } else {
    u16_t psm;

    for (psm = L2CAP_LE_PSM_DYN_START; psm <= L2CAP_LE_PSM_DYN_END; psm++) {
      if (!l2cap_server_lookup_psm(psm)) {
        break;
      }
    }

    if (psm > L2CAP_LE_PSM_DYN_END) {
      BT_WARN("No free dynamic PSMs available");
      return -EADDRNOTAVAIL;
    }

    BT_DBG("Allocated PSM 0x%04x for new server", psm);
    server->psm = psm;
  }

  if (server->sec_level > BT_SECURITY_L4) {
    return -EINVAL;
  } else if (server->sec_level < BT_SECURITY_L1) {
    /* Level 0 is only applicable for BR/EDR */
    server->sec_level = BT_SECURITY_L1;
  }

  BT_DBG("PSM 0x%04x", server->psm);

  sys_slist_append(&servers, &server->node);

  return 0;
}

static void l2cap_chan_rx_init(struct bt_l2cap_le_chan *chan) {
  BT_DBG("chan %p", chan);

  /* Use existing MTU if defined */
  if (!chan->rx.mtu) {
    chan->rx.mtu = L2CAP_MAX_LE_MTU;
  }

  /* Use existing credits if defined */
  if (!chan->rx.init_credits) {
    if (chan->chan.ops->alloc_buf) {
      /* Auto tune credits to receive a full packet */
      chan->rx.init_credits = (chan->rx.mtu + (L2CAP_MAX_LE_MPS - 1)) / L2CAP_MAX_LE_MPS;
    } else {
      chan->rx.init_credits = L2CAP_LE_MAX_CREDITS;
    }
  }

  /* MPS shall not be bigger than MTU + 2 as the remaining bytes cannot
   * be used.
   */
  chan->rx.mps = MIN(chan->rx.mtu + 2, L2CAP_MAX_LE_MPS);
  k_sem_init(&chan->rx.credits, 0, BT_UINT_MAX);

  if (BT_DBG_ENABLED && chan->rx.init_credits * chan->rx.mps < chan->rx.mtu + 2) {
    BT_WARN("Not enough credits for a full packet");
  }
}

static void l2cap_chan_tx_init(struct bt_l2cap_le_chan *chan) {
  BT_DBG("chan %p", chan);

  (void)memset(&chan->tx, 0, sizeof(chan->tx));
  k_sem_init(&chan->tx.credits, 0, BT_UINT_MAX);
  k_fifo_init(&chan->tx_queue, 20);
}

static void l2cap_chan_tx_give_credits(struct bt_l2cap_le_chan *chan, u16_t credits) {
  BT_DBG("chan %p credits %u", chan, credits);

  while (credits--) {
    k_sem_give(&chan->tx.credits);
  }

  if (atomic_test_and_set_bit(chan->chan.status, BT_L2CAP_STATUS_OUT) && chan->chan.ops->status) {
    chan->chan.ops->status(&chan->chan, chan->chan.status);
  }
}

static void l2cap_chan_rx_give_credits(struct bt_l2cap_le_chan *chan, u16_t credits) {
  BT_DBG("chan %p credits %u", chan, credits);

  while (credits--) {
    k_sem_give(&chan->rx.credits);
  }
}

static void l2cap_chan_destroy(struct bt_l2cap_chan *chan) {
  struct bt_l2cap_le_chan *ch = BT_L2CAP_LE_CHAN(chan);
  struct net_buf          *buf;

  BT_DBG("chan %p cid 0x%04x", ch, ch->rx.cid);

  /* Cancel ongoing work */
  k_delayed_work_cancel(&chan->rtx_work);

  if (ch->tx_buf) {
    net_buf_unref(ch->tx_buf);
    ch->tx_buf = NULL;
  }

  /* Remove buffers on the TX queue */
  while ((buf = net_buf_get(&ch->tx_queue, K_NO_WAIT))) {
    net_buf_unref(buf);
  }

  /* Remove buffers on the RX queue */
  while ((buf = net_buf_get(&ch->rx_queue, K_NO_WAIT))) {
    net_buf_unref(buf);
  }

  /* Destroy segmented SDU if it exists */
  if (ch->_sdu) {
    net_buf_unref(ch->_sdu);
    ch->_sdu     = NULL;
    ch->_sdu_len = 0U;
  }
}

static u16_t le_err_to_result(int err) {
  switch (err) {
  case -ENOMEM:
    return BT_L2CAP_LE_ERR_NO_RESOURCES;
  case -EACCES:
    return BT_L2CAP_LE_ERR_AUTHORIZATION;
  case -EPERM:
    return BT_L2CAP_LE_ERR_KEY_SIZE;
  case -ENOTSUP:
    /* This handle the cases where a fixed channel is registered but
     * for some reason (e.g. controller not suporting a feature)
     * cannot be used.
     */
    return BT_L2CAP_LE_ERR_PSM_NOT_SUPP;
  default:
    return BT_L2CAP_LE_ERR_UNACCEPT_PARAMS;
  }
}

static void le_conn_req(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn              *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_chan        *chan;
  struct bt_l2cap_server      *server;
  struct bt_l2cap_le_conn_req *req = (void *)buf->data;
  struct bt_l2cap_le_conn_rsp *rsp;
  u16_t                        psm, scid, mtu, mps, credits;
  int                          err;

  if (buf->len < sizeof(*req)) {
    BT_ERR("Too small LE conn req packet size");
    return;
  }

  psm     = sys_le16_to_cpu(req->psm);
  scid    = sys_le16_to_cpu(req->scid);
  mtu     = sys_le16_to_cpu(req->mtu);
  mps     = sys_le16_to_cpu(req->mps);
  credits = sys_le16_to_cpu(req->credits);

  BT_DBG("psm 0x%02x scid 0x%04x mtu %u mps %u credits %u", psm, scid, mtu, mps, credits);

  if (mtu < L2CAP_LE_MIN_MTU || mps < L2CAP_LE_MIN_MTU) {
    BT_ERR("Invalid LE-Conn Req params");
    return;
  }

  buf = l2cap_create_le_sig_pdu(buf, BT_L2CAP_LE_CONN_RSP, ident, sizeof(*rsp));
  if (!buf) {
    return;
  }

  rsp = net_buf_add(buf, sizeof(*rsp));
  (void)memset(rsp, 0, sizeof(*rsp));

  /* Check if there is a server registered */
  server = l2cap_server_lookup_psm(psm);
  if (!server) {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_LE_ERR_PSM_NOT_SUPP);
    goto rsp;
  }

/* Check if connection has minimum required security level */
#if defined(CONFIG_BT_SMP)
  if (conn->sec_level < server->sec_level) {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_LE_ERR_AUTHENTICATION);
    goto rsp;
  }
#endif

  if (!L2CAP_LE_CID_IS_DYN(scid)) {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_LE_ERR_INVALID_SCID);
    goto rsp;
  }

  chan = bt_l2cap_le_lookup_tx_cid(conn, scid);
  if (chan) {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_LE_ERR_SCID_IN_USE);
    goto rsp;
  }

  /* Request server to accept the new connection and allocate the
   * channel.
   */
  err = server->accept(conn, &chan);
  if (err < 0) {
    rsp->result = sys_cpu_to_le16(le_err_to_result(err));
    goto rsp;
  }

  chan->required_sec_level = server->sec_level;

  if (l2cap_chan_add(conn, chan, l2cap_chan_destroy)) {
    struct bt_l2cap_le_chan *ch = BT_L2CAP_LE_CHAN(chan);

    /* Init TX parameters */
    l2cap_chan_tx_init(ch);
    ch->tx.cid          = scid;
    ch->tx.mps          = mps;
    ch->tx.mtu          = mtu;
    ch->tx.init_credits = credits;
    l2cap_chan_tx_give_credits(ch, credits);

    /* Init RX parameters */
    l2cap_chan_rx_init(ch);
    l2cap_chan_rx_give_credits(ch, ch->rx.init_credits);

    /* Set channel PSM */
    chan->psm = server->psm;

    /* Update state */
    bt_l2cap_chan_set_state(chan, BT_L2CAP_CONNECTED);

    if (chan->ops->connected) {
      chan->ops->connected(chan);
    }

    /* Prepare response protocol data */
    rsp->dcid    = sys_cpu_to_le16(ch->rx.cid);
    rsp->mps     = sys_cpu_to_le16(ch->rx.mps);
    rsp->mtu     = sys_cpu_to_le16(ch->rx.mtu);
    rsp->credits = sys_cpu_to_le16(ch->rx.init_credits);
    rsp->result  = BT_L2CAP_LE_SUCCESS;
  } else {
    rsp->result = sys_cpu_to_le16(BT_L2CAP_LE_ERR_NO_RESOURCES);
  }
rsp:
  bt_l2cap_send(conn, BT_L2CAP_CID_LE_SIG, buf);
}

static struct bt_l2cap_le_chan *l2cap_remove_rx_cid(struct bt_conn *conn, u16_t cid) {
  struct bt_l2cap_chan *chan;
  sys_snode_t          *prev = NULL;

  /* Protect fixed channels against accidental removal */
  if (!L2CAP_LE_CID_IS_DYN(cid)) {
    return NULL;
  }

  SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
    if (BT_L2CAP_LE_CHAN(chan)->rx.cid == cid) {
      sys_slist_remove(&conn->channels, prev, &chan->node);
      return BT_L2CAP_LE_CHAN(chan);
    }

    prev = &chan->node;
  }

  return NULL;
}

static void le_disconn_req(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn              *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_le_chan     *chan;
  struct bt_l2cap_disconn_req *req = (void *)buf->data;
  struct bt_l2cap_disconn_rsp *rsp;
  u16_t                        dcid;

  if (buf->len < sizeof(*req)) {
    BT_ERR("Too small LE conn req packet size");
    return;
  }

  dcid = sys_le16_to_cpu(req->dcid);

  BT_DBG("dcid 0x%04x scid 0x%04x", dcid, sys_le16_to_cpu(req->scid));

  chan = l2cap_remove_rx_cid(conn, dcid);
  if (!chan) {
    struct bt_l2cap_cmd_reject_cid_data data;

    data.scid = req->scid;
    data.dcid = req->dcid;

    l2cap_send_reject(conn, ident, BT_L2CAP_REJ_INVALID_CID, &data, sizeof(data));
    return;
  }

  buf = l2cap_create_le_sig_pdu(buf, BT_L2CAP_DISCONN_RSP, ident, sizeof(*rsp));
  if (!buf) {
    return;
  }

  rsp       = net_buf_add(buf, sizeof(*rsp));
  rsp->dcid = sys_cpu_to_le16(chan->rx.cid);
  rsp->scid = sys_cpu_to_le16(chan->tx.cid);

  bt_l2cap_chan_del(&chan->chan);

  bt_l2cap_send(conn, BT_L2CAP_CID_LE_SIG, buf);
}

#if defined(CONFIG_BT_SMP)
static int l2cap_change_security(struct bt_l2cap_le_chan *chan, u16_t err) {
  switch (err) {
  case BT_L2CAP_LE_ERR_ENCRYPTION:
    if (chan->chan.required_sec_level >= BT_SECURITY_L2) {
      return -EALREADY;
    }
    chan->chan.required_sec_level = BT_SECURITY_L2;
    break;
  case BT_L2CAP_LE_ERR_AUTHENTICATION:
    if (chan->chan.required_sec_level < BT_SECURITY_L2) {
      chan->chan.required_sec_level = BT_SECURITY_L2;
    } else if (chan->chan.required_sec_level < BT_SECURITY_L3) {
      chan->chan.required_sec_level = BT_SECURITY_L3;
    } else if (chan->chan.required_sec_level < BT_SECURITY_L4) {
      chan->chan.required_sec_level = BT_SECURITY_L4;
    } else {
      return -EALREADY;
    }
    break;
  default:
    return -EINVAL;
  }

  return bt_conn_set_security(chan->chan.conn, chan->chan.required_sec_level);
}
#endif // CONFIG_BT_SMP

static void le_conn_rsp(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn              *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_le_chan     *chan;
  struct bt_l2cap_le_conn_rsp *rsp = (void *)buf->data;
  u16_t                        dcid, mtu, mps, credits, result;

  if (buf->len < sizeof(*rsp)) {
    BT_ERR("Too small LE conn rsp packet size");
    return;
  }

  dcid    = sys_le16_to_cpu(rsp->dcid);
  mtu     = sys_le16_to_cpu(rsp->mtu);
  mps     = sys_le16_to_cpu(rsp->mps);
  credits = sys_le16_to_cpu(rsp->credits);
  result  = sys_le16_to_cpu(rsp->result);

  BT_DBG("dcid 0x%04x mtu %u mps %u credits %u result 0x%04x", dcid, mtu, mps, credits, result);

  /* Keep the channel in case of security errors */
  if (result == BT_L2CAP_LE_SUCCESS || result == BT_L2CAP_LE_ERR_AUTHENTICATION || result == BT_L2CAP_LE_ERR_ENCRYPTION) {
    chan = l2cap_lookup_ident(conn, ident);
  } else {
    chan = l2cap_remove_ident(conn, ident);
  }

  if (!chan) {
    BT_ERR("Cannot find channel for ident %u", ident);
    return;
  }

  /* Cancel RTX work */
  k_delayed_work_cancel(&chan->chan.rtx_work);

  /* Reset ident since it got a response */
  chan->chan.ident = 0U;

  switch (result) {
  case BT_L2CAP_LE_SUCCESS:
    chan->tx.cid = dcid;
    chan->tx.mtu = mtu;
    chan->tx.mps = mps;

    /* Update state */
    bt_l2cap_chan_set_state(&chan->chan, BT_L2CAP_CONNECTED);

    if (chan->chan.ops->connected) {
      chan->chan.ops->connected(&chan->chan);
    }

    /* Give credits */
    l2cap_chan_tx_give_credits(chan, credits);
    l2cap_chan_rx_give_credits(chan, chan->rx.init_credits);

    break;
  case BT_L2CAP_LE_ERR_AUTHENTICATION:
  case BT_L2CAP_LE_ERR_ENCRYPTION:
#if defined(CONFIG_BT_SMP)
    /* If security needs changing wait it to be completed */
    if (l2cap_change_security(chan, result) == 0) {
      return;
    }
#endif
    bt_l2cap_chan_remove(conn, &chan->chan);
    __attribute__((fallthrough));
  default:
    bt_l2cap_chan_del(&chan->chan);
  }
}

static void le_disconn_rsp(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn              *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_le_chan     *chan;
  struct bt_l2cap_disconn_rsp *rsp = (void *)buf->data;
  u16_t                        scid;

  if (buf->len < sizeof(*rsp)) {
    BT_ERR("Too small LE disconn rsp packet size");
    return;
  }

  scid = sys_le16_to_cpu(rsp->scid);

  BT_DBG("dcid 0x%04x scid 0x%04x", sys_le16_to_cpu(rsp->dcid), scid);

  chan = l2cap_remove_rx_cid(conn, scid);
  if (!chan) {
    return;
  }

  bt_l2cap_chan_del(&chan->chan);
}

static inline struct net_buf *l2cap_alloc_seg(struct net_buf *buf) {
  struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id);
  struct net_buf      *seg;

  /* Try to use original pool if possible */
  seg = net_buf_alloc(pool, K_NO_WAIT);
  if (seg) {
    net_buf_reserve(seg, BT_L2CAP_CHAN_SEND_RESERVE);
    return seg;
  }

  /* Fallback to using global connection tx pool */
  return bt_l2cap_create_pdu(NULL, 0);
}

static struct net_buf *l2cap_chan_create_seg(struct bt_l2cap_le_chan *ch, struct net_buf *buf, size_t sdu_hdr_len) {
  struct net_buf *seg;
  u16_t           headroom;
  u16_t           len;

  /* Segment if data (+ data headroom) is bigger than MPS */
  if (buf->len + sdu_hdr_len > ch->tx.mps) {
    goto segment;
  }

  headroom = BT_L2CAP_CHAN_SEND_RESERVE + sdu_hdr_len;

  /* Check if original buffer has enough headroom and don't have any
   * fragments.
   */
  if (net_buf_headroom(buf) >= headroom && !buf->frags) {
    if (sdu_hdr_len) {
      /* Push SDU length if set */
      net_buf_push_le16(buf, net_buf_frags_len(buf));
    }
    return net_buf_ref(buf);
  }

segment:
  seg = l2cap_alloc_seg(buf);
  if (!seg) {
    return NULL;
  }

  if (sdu_hdr_len) {
    net_buf_add_le16(seg, net_buf_frags_len(buf));
  }

  /* Don't send more that TX MPS including SDU length */
  len = MIN(net_buf_tailroom(seg), ch->tx.mps - sdu_hdr_len);
  /* Limit if original buffer is smaller than the segment */
  len = MIN(buf->len, len);
  net_buf_add_mem(seg, buf->data, len);
  net_buf_pull(buf, len);

  BT_DBG("ch %p seg %p len %u", ch, seg, seg->len);

  return seg;
}

void l2cap_chan_sdu_sent(struct bt_conn *conn, void *user_data) {
  struct bt_l2cap_chan *chan = user_data;

  BT_DBG("conn %p chan %p", conn, chan);

  if (chan->ops->sent) {
    chan->ops->sent(chan);
  }
}

static int l2cap_chan_le_send(struct bt_l2cap_le_chan *ch, struct net_buf *buf, u16_t sdu_hdr_len) {
  struct net_buf *seg;
  int             len;

  /* Wait for credits */
  if (k_sem_take(&ch->tx.credits, K_NO_WAIT)) {
    BT_DBG("No credits to transmit packet");
    return -EAGAIN;
  }

  seg = l2cap_chan_create_seg(ch, buf, sdu_hdr_len);
  if (!seg) {
    return -ENOMEM;
  }

  /* Channel may have been disconnected while waiting for a buffer */
  if (!ch->chan.conn) {
    net_buf_unref(buf);
    return -ECONNRESET;
  }

  BT_DBG("ch %p cid 0x%04x len %u credits %u", ch, ch->tx.cid, seg->len, k_sem_count_get(&ch->tx.credits));

  len = seg->len - sdu_hdr_len;

  /* Set a callback if there is no data left in the buffer and sent
   * callback has been set.
   */
  if ((buf == seg || !buf->len) && ch->chan.ops->sent) {
    bt_l2cap_send_cb(ch->chan.conn, ch->tx.cid, seg, l2cap_chan_sdu_sent, &ch->chan);
  } else {
    bt_l2cap_send(ch->chan.conn, ch->tx.cid, seg);
  }

  /* Check if there is no credits left clear output status and notify its
   * change.
   */
  if (!k_sem_count_get(&ch->tx.credits)) {
    atomic_clear_bit(ch->chan.status, BT_L2CAP_STATUS_OUT);
    if (ch->chan.ops->status) {
      ch->chan.ops->status(&ch->chan, ch->chan.status);
    }
  }

  return len;
}

static int l2cap_chan_le_send_sdu(struct bt_l2cap_le_chan *ch, struct net_buf **buf, u16_t sent) {
  int             ret, total_len;
  struct net_buf *frag;

  total_len = net_buf_frags_len(*buf) + sent;

  if (total_len > ch->tx.mtu) {
    return -EMSGSIZE;
  }

  frag = *buf;
  if (!frag->len && frag->frags) {
    frag = frag->frags;
  }

  if (!sent) {
    /* Add SDU length for the first segment */
    ret = l2cap_chan_le_send(ch, frag, BT_L2CAP_SDU_HDR_LEN);
    if (ret < 0) {
      if (ret == -EAGAIN) {
        /* Store sent data into user_data */
        memcpy(net_buf_user_data(frag), &sent, sizeof(sent));
      }
      *buf = frag;
      return ret;
    }
    sent = ret;
  }

  /* Send remaining segments */
  for (ret = 0; sent < total_len; sent += ret) {
    /* Proceed to next fragment */
    if (!frag->len) {
      frag = net_buf_frag_del(NULL, frag);
    }

    ret = l2cap_chan_le_send(ch, frag, 0);
    if (ret < 0) {
      if (ret == -EAGAIN) {
        /* Store sent data into user_data */
        memcpy(net_buf_user_data(frag), &sent, sizeof(sent));
      }
      *buf = frag;
      return ret;
    }
  }

  BT_DBG("ch %p cid 0x%04x sent %u total_len %u", ch, ch->tx.cid, sent, total_len);

  net_buf_unref(frag);

  return ret;
}

static struct net_buf *l2cap_chan_le_get_tx_buf(struct bt_l2cap_le_chan *ch) {
  struct net_buf *buf;

  /* Return current buffer */
  if (ch->tx_buf) {
    buf        = ch->tx_buf;
    ch->tx_buf = NULL;
    return buf;
  }

  return net_buf_get(&ch->tx_queue, K_NO_WAIT);
}

static void l2cap_chan_le_send_resume(struct bt_l2cap_le_chan *ch) {
  struct net_buf *buf;

  /* Resume tx in case there are buffers in the queue */
  while ((buf = l2cap_chan_le_get_tx_buf(ch))) {
#if defined(BFLB_BLE)
    int sent = *((int *)net_buf_user_data(buf));
#else
    u16_t sent = *((u16_t *)net_buf_user_data(buf));
#endif

    BT_DBG("buf %p sent %u", buf, sent);

    sent = l2cap_chan_le_send_sdu(ch, &buf, sent);
    if (sent < 0) {
      if (sent == -EAGAIN) {
        ch->tx_buf = buf;
      }
      break;
    }
  }
}

static void le_credits(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn             *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_chan       *chan;
  struct bt_l2cap_le_credits *ev = (void *)buf->data;
  struct bt_l2cap_le_chan    *ch;
  u16_t                       credits, cid;

  if (buf->len < sizeof(*ev)) {
    BT_ERR("Too small LE Credits packet size");
    return;
  }

  cid     = sys_le16_to_cpu(ev->cid);
  credits = sys_le16_to_cpu(ev->credits);

  BT_DBG("cid 0x%04x credits %u", cid, credits);

  chan = bt_l2cap_le_lookup_tx_cid(conn, cid);
  if (!chan) {
    BT_ERR("Unable to find channel of LE Credits packet");
    return;
  }

  ch = BT_L2CAP_LE_CHAN(chan);

  if (k_sem_count_get(&ch->tx.credits) + credits > UINT16_MAX) {
    BT_ERR("Credits overflow");
    bt_l2cap_chan_disconnect(chan);
    return;
  }

  l2cap_chan_tx_give_credits(ch, credits);

  BT_DBG("chan %p total credits %u", ch, k_sem_count_get(&ch->tx.credits));

  l2cap_chan_le_send_resume(ch);
}

static void reject_cmd(struct bt_l2cap *l2cap, u8_t ident, struct net_buf *buf) {
  struct bt_conn          *conn = l2cap->chan.chan.conn;
  struct bt_l2cap_le_chan *chan;

  /* Check if there is a outstanding channel */
  chan = l2cap_remove_ident(conn, ident);
  if (!chan) {
    return;
  }

  bt_l2cap_chan_del(&chan->chan);
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

static int l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_l2cap         *l2cap = CONTAINER_OF(chan, struct bt_l2cap, chan);
  struct bt_l2cap_sig_hdr *hdr;
  u16_t                    len;

  if (buf->len < sizeof(*hdr)) {
    BT_ERR("Too small L2CAP signaling PDU");
    return 0;
  }

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  len = sys_le16_to_cpu(hdr->len);

  BT_DBG("Signaling code 0x%02x ident %u len %u", hdr->code, hdr->ident, len);

  if (buf->len != len) {
    BT_ERR("L2CAP length mismatch (%u != %u)", buf->len, len);
    return 0;
  }

  if (!hdr->ident) {
    BT_ERR("Invalid ident value in L2CAP PDU");
    return 0;
  }

  switch (hdr->code) {
  case BT_L2CAP_CONN_PARAM_RSP:
    le_conn_param_rsp(l2cap, buf);
    break;
#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
  case BT_L2CAP_LE_CONN_REQ:
    le_conn_req(l2cap, hdr->ident, buf);
    break;
  case BT_L2CAP_LE_CONN_RSP:
    le_conn_rsp(l2cap, hdr->ident, buf);
    break;
  case BT_L2CAP_DISCONN_REQ:
    le_disconn_req(l2cap, hdr->ident, buf);
    break;
  case BT_L2CAP_DISCONN_RSP:
    le_disconn_rsp(l2cap, hdr->ident, buf);
    break;
  case BT_L2CAP_LE_CREDITS:
    le_credits(l2cap, hdr->ident, buf);
    break;
  case BT_L2CAP_CMD_REJECT:
    reject_cmd(l2cap, hdr->ident, buf);
    break;
#else
  case BT_L2CAP_CMD_REJECT:
    /* Ignored */
    break;
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */
  case BT_L2CAP_CONN_PARAM_REQ:
    if (IS_ENABLED(CONFIG_BT_CENTRAL)) {
      le_conn_param_update_req(l2cap, hdr->ident, buf);
      break;
    }
#if defined(BFLB_BLE)
    __attribute__((fallthrough));
#endif

  /* Fall-through */
  default:
    BT_WARN("Unknown L2CAP PDU code 0x%02x", hdr->code);
    l2cap_send_reject(chan->conn, hdr->ident, BT_L2CAP_REJ_NOT_UNDERSTOOD, NULL, 0);
    break;
  }

  return 0;
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static void l2cap_chan_send_credits(struct bt_l2cap_le_chan *chan, struct net_buf *buf, u16_t credits) {
  struct bt_l2cap_le_credits *ev;

  /* Cap the number of credits given */
  if (credits > chan->rx.init_credits) {
    credits = chan->rx.init_credits;
  }

  l2cap_chan_rx_give_credits(chan, credits);

  buf = l2cap_create_le_sig_pdu(buf, BT_L2CAP_LE_CREDITS, get_ident(), sizeof(*ev));
  if (!buf) {
    return;
  }

  ev          = net_buf_add(buf, sizeof(*ev));
  ev->cid     = sys_cpu_to_le16(chan->rx.cid);
  ev->credits = sys_cpu_to_le16(credits);

  bt_l2cap_send(chan->chan.conn, BT_L2CAP_CID_LE_SIG, buf);

  BT_DBG("chan %p credits %u", chan, k_sem_count_get(&chan->rx.credits));
}

static void l2cap_chan_update_credits(struct bt_l2cap_le_chan *chan, struct net_buf *buf) {
  s16_t credits;

  /* Restore enough credits to complete the sdu */
  credits = ((chan->_sdu_len - net_buf_frags_len(buf)) + (chan->rx.mps - 1)) / chan->rx.mps;
  credits -= k_sem_count_get(&chan->rx.credits);
  if (credits <= 0) {
    return;
  }

  l2cap_chan_send_credits(chan, buf, credits);
}

int bt_l2cap_chan_recv_complete(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_l2cap_le_chan *ch   = BT_L2CAP_LE_CHAN(chan);
  struct bt_conn          *conn = chan->conn;
  u16_t                    credits;

  __ASSERT_NO_MSG(chan);
  __ASSERT_NO_MSG(buf);

  if (!conn) {
    return -ENOTCONN;
  }

  if (conn->type != BT_CONN_TYPE_LE) {
    return -ENOTSUP;
  }

  BT_DBG("chan %p buf %p", chan, buf);

  /* Restore credits used by packet */
  memcpy(&credits, net_buf_user_data(buf), sizeof(credits));

  l2cap_chan_send_credits(ch, buf, credits);

  net_buf_unref(buf);

  return 0;
}

static struct net_buf *l2cap_alloc_frag(s32_t timeout, void *user_data) {
  struct bt_l2cap_le_chan *chan = user_data;
  struct net_buf          *frag = NULL;

  frag = chan->chan.ops->alloc_buf(&chan->chan);
  if (!frag) {
    return NULL;
  }

  BT_DBG("frag %p tailroom %zu", frag, net_buf_tailroom(frag));

  return frag;
}

static void l2cap_chan_le_recv_sdu(struct bt_l2cap_le_chan *chan, struct net_buf *buf, u16_t seg) {
  int err;

  BT_DBG("chan %p len %zu", chan, net_buf_frags_len(buf));

  /* Receiving complete SDU, notify channel and reset SDU buf */
  err = chan->chan.ops->recv(&chan->chan, buf);
  if (err < 0) {
    if (err != -EINPROGRESS) {
      BT_ERR("err %d", err);
      bt_l2cap_chan_disconnect(&chan->chan);
      net_buf_unref(buf);
    }
    return;
  }

  l2cap_chan_send_credits(chan, buf, seg);
  net_buf_unref(buf);
}

static void l2cap_chan_le_recv_seg(struct bt_l2cap_le_chan *chan, struct net_buf *buf) {
  u16_t len;
  u16_t seg = 0U;

  len = net_buf_frags_len(chan->_sdu);
  if (len) {
    memcpy(&seg, net_buf_user_data(chan->_sdu), sizeof(seg));
  }

  if (len + buf->len > chan->_sdu_len) {
    BT_ERR("SDU length mismatch");
    bt_l2cap_chan_disconnect(&chan->chan);
    return;
  }

  seg++;
  /* Store received segments in user_data */
  memcpy(net_buf_user_data(chan->_sdu), &seg, sizeof(seg));

  BT_DBG("chan %p seg %d len %zu", chan, seg, net_buf_frags_len(buf));

  /* Append received segment to SDU */
  len = net_buf_append_bytes(chan->_sdu, buf->len, buf->data, K_NO_WAIT, l2cap_alloc_frag, chan);
  if (len != buf->len) {
    BT_ERR("Unable to store SDU");
    bt_l2cap_chan_disconnect(&chan->chan);
    return;
  }

  if (net_buf_frags_len(chan->_sdu) < chan->_sdu_len) {
    /* Give more credits if remote has run out of them, this
     * should only happen if the remote cannot fully utilize the
     * MPS for some reason.
     */
    if (!k_sem_count_get(&chan->rx.credits) && seg == chan->rx.init_credits) {
      l2cap_chan_update_credits(chan, buf);
    }
    return;
  }

  buf            = chan->_sdu;
  chan->_sdu     = NULL;
  chan->_sdu_len = 0U;

  l2cap_chan_le_recv_sdu(chan, buf, seg);
}

static void l2cap_chan_le_recv(struct bt_l2cap_le_chan *chan, struct net_buf *buf) {
  u16_t sdu_len;
  int   err;

  if (k_sem_take(&chan->rx.credits, K_NO_WAIT)) {
    BT_ERR("No credits to receive packet");
    bt_l2cap_chan_disconnect(&chan->chan);
    return;
  }

  /* Check if segments already exist */
  if (chan->_sdu) {
    l2cap_chan_le_recv_seg(chan, buf);
    return;
  }

  sdu_len = net_buf_pull_le16(buf);

  BT_DBG("chan %p len %u sdu_len %u", chan, buf->len, sdu_len);

  if (sdu_len > chan->rx.mtu) {
    BT_ERR("Invalid SDU length");
    bt_l2cap_chan_disconnect(&chan->chan);
    return;
  }

  /* Always allocate buffer from the channel if supported. */
  if (chan->chan.ops->alloc_buf) {
    chan->_sdu = chan->chan.ops->alloc_buf(&chan->chan);
    if (!chan->_sdu) {
      BT_ERR("Unable to allocate buffer for SDU");
      bt_l2cap_chan_disconnect(&chan->chan);
      return;
    }
    chan->_sdu_len = sdu_len;
    l2cap_chan_le_recv_seg(chan, buf);
    return;
  }

  err = chan->chan.ops->recv(&chan->chan, buf);
  if (err) {
    if (err != -EINPROGRESS) {
      BT_ERR("err %d", err);
      bt_l2cap_chan_disconnect(&chan->chan);
    }
    return;
  }

  l2cap_chan_send_credits(chan, buf, 1);
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

static void l2cap_chan_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) {
#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
  struct bt_l2cap_le_chan *ch = BT_L2CAP_LE_CHAN(chan);

  if (L2CAP_LE_CID_IS_DYN(ch->rx.cid)) {
    net_buf_put(&ch->rx_queue, net_buf_ref(buf));
    k_work_submit(&ch->rx_work);
    return;
  }
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */

  BT_DBG("chan %p len %u", chan, buf->len);

  chan->ops->recv(chan, buf);
  net_buf_unref(buf);
}

void bt_l2cap_recv(struct bt_conn *conn, struct net_buf *buf) {
  struct bt_l2cap_hdr  *hdr;
  struct bt_l2cap_chan *chan;
  u16_t                 cid;

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    bt_l2cap_br_recv(conn, buf);
    return;
  }

  if (buf->len < sizeof(*hdr)) {
    BT_ERR("Too small L2CAP PDU received");
    net_buf_unref(buf);
    return;
  }

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  cid = sys_le16_to_cpu(hdr->cid);

  BT_DBG("Packet for CID %u len %u", cid, buf->len);

  chan = bt_l2cap_le_lookup_rx_cid(conn, cid);
  if (!chan) {
    BT_WARN("Ignoring data for unknown CID 0x%04x", cid);
    net_buf_unref(buf);
    return;
  }

  l2cap_chan_recv(chan, buf);
}

int bt_l2cap_update_conn_param(struct bt_conn *conn, const struct bt_le_conn_param *param) {
  struct bt_l2cap_conn_param_req *req;
  struct net_buf                 *buf;

  buf = l2cap_create_le_sig_pdu(NULL, BT_L2CAP_CONN_PARAM_REQ, get_ident(), sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req               = net_buf_add(buf, sizeof(*req));
  req->min_interval = sys_cpu_to_le16(param->interval_min);
  req->max_interval = sys_cpu_to_le16(param->interval_max);
  req->latency      = sys_cpu_to_le16(param->latency);
  req->timeout      = sys_cpu_to_le16(param->timeout);

  bt_l2cap_send(conn, BT_L2CAP_CID_LE_SIG, buf);

  return 0;
}

static void l2cap_connected(struct bt_l2cap_chan *chan) { BT_DBG("ch %p cid 0x%04x", BT_L2CAP_LE_CHAN(chan), BT_L2CAP_LE_CHAN(chan)->rx.cid); }

static void l2cap_disconnected(struct bt_l2cap_chan *chan) { BT_DBG("ch %p cid 0x%04x", BT_L2CAP_LE_CHAN(chan), BT_L2CAP_LE_CHAN(chan)->rx.cid); }

static int l2cap_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) {
  int                             i;
  static struct bt_l2cap_chan_ops ops = {
      .connected    = l2cap_connected,
      .disconnected = l2cap_disconnected,
      .recv         = l2cap_recv,
  };

  BT_DBG("conn %p handle %u", conn, conn->handle);

  for (i = 0; i < ARRAY_SIZE(bt_l2cap_pool); i++) {
    struct bt_l2cap *l2cap = &bt_l2cap_pool[i];

    if (l2cap->chan.chan.conn) {
      continue;
    }

    l2cap->chan.chan.ops = &ops;
    *chan                = &l2cap->chan.chan;

    return 0;
  }

  BT_ERR("No available L2CAP context for conn %p", conn);

  return -ENOMEM;
}

BT_L2CAP_CHANNEL_DEFINE(le_fixed_chan, BT_L2CAP_CID_LE_SIG, l2cap_accept);

void bt_l2cap_init(void) {
#if defined(BFLB_BLE_DISABLE_STATIC_CHANNEL)
  static struct bt_l2cap_fixed_chan chan = {
      .cid    = BT_L2CAP_CID_LE_SIG,
      .accept = l2cap_accept,
  };

  bt_l2cap_le_fixed_chan_register(&chan);
#endif
  if (IS_ENABLED(CONFIG_BT_BREDR)) {
    bt_l2cap_br_init();
  }
}

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
static int l2cap_le_connect(struct bt_conn *conn, struct bt_l2cap_le_chan *ch, u16_t psm) {
  if (psm < L2CAP_LE_PSM_FIXED_START || psm > L2CAP_LE_PSM_DYN_END) {
    return -EINVAL;
  }

  l2cap_chan_tx_init(ch);
  l2cap_chan_rx_init(ch);

  if (!l2cap_chan_add(conn, &ch->chan, l2cap_chan_destroy)) {
    return -ENOMEM;
  }

  ch->chan.psm = psm;

  return l2cap_le_conn_req(ch);
}

int bt_l2cap_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan, u16_t psm) {
  BT_DBG("conn %p chan %p psm 0x%04x", conn, chan, psm);

  if (!conn || conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  if (!chan) {
    return -EINVAL;
  }

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    return bt_l2cap_br_chan_connect(conn, chan, psm);
  }

  if (chan->required_sec_level > BT_SECURITY_L4) {
    return -EINVAL;
  } else if (chan->required_sec_level == BT_SECURITY_L0) {
    chan->required_sec_level = BT_SECURITY_L1;
  }

  return l2cap_le_connect(conn, BT_L2CAP_LE_CHAN(chan), psm);
}

int bt_l2cap_chan_disconnect(struct bt_l2cap_chan *chan) {
  struct bt_conn              *conn = chan->conn;
  struct net_buf              *buf;
  struct bt_l2cap_disconn_req *req;
  struct bt_l2cap_le_chan     *ch;

  if (!conn) {
    return -ENOTCONN;
  }

  if (IS_ENABLED(CONFIG_BT_BREDR) && conn->type == BT_CONN_TYPE_BR) {
    return bt_l2cap_br_chan_disconnect(chan);
  }

  ch = BT_L2CAP_LE_CHAN(chan);

  BT_DBG("chan %p scid 0x%04x dcid 0x%04x", chan, ch->rx.cid, ch->tx.cid);

  ch->chan.ident = get_ident();

  buf = l2cap_create_le_sig_pdu(NULL, BT_L2CAP_DISCONN_REQ, ch->chan.ident, sizeof(*req));
  if (!buf) {
    return -ENOMEM;
  }

  req       = net_buf_add(buf, sizeof(*req));
  req->dcid = sys_cpu_to_le16(ch->rx.cid);
  req->scid = sys_cpu_to_le16(ch->tx.cid);

  l2cap_chan_send_req(ch, buf, L2CAP_DISC_TIMEOUT);
  bt_l2cap_chan_set_state(chan, BT_L2CAP_DISCONNECT);

  return 0;
}

int bt_l2cap_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  int err;

  if (!buf) {
    return -EINVAL;
  }

  BT_DBG("chan %p buf %p len %zu", chan, buf, net_buf_frags_len(buf));

  if (!chan->conn || chan->conn->state != BT_CONN_CONNECTED) {
    return -ENOTCONN;
  }

  if (IS_ENABLED(CONFIG_BT_BREDR) && chan->conn->type == BT_CONN_TYPE_BR) {
    return bt_l2cap_br_chan_send(chan, buf);
  }

  err = l2cap_chan_le_send_sdu(BT_L2CAP_LE_CHAN(chan), &buf, 0);
  if (err < 0) {
    if (err == -EAGAIN) {
      /* Queue buffer to be sent later */
      net_buf_put(&(BT_L2CAP_LE_CHAN(chan))->tx_queue, buf);
      return *((u16_t *)net_buf_user_data(buf));
    }
    BT_ERR("failed to send message %d", err);
  }

  return err;
}
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/l2cap_internal.h
================================================
/** @file
 *  @brief Internal APIs for Bluetooth L2CAP handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

enum l2cap_conn_list_action {
    BT_L2CAP_CHAN_LOOKUP,
    BT_L2CAP_CHAN_DETACH,
};

#define BT_L2CAP_CID_BR_SIG 0x0001
#define BT_L2CAP_CID_ATT    0x0004
#define BT_L2CAP_CID_LE_SIG 0x0005
#define BT_L2CAP_CID_SMP    0x0006
#define BT_L2CAP_CID_BR_SMP 0x0007

#define BT_L2CAP_PSM_RFCOMM 0x0003

struct bt_l2cap_hdr {
    u16_t len;
    u16_t cid;
} __packed;

struct bt_l2cap_sig_hdr {
    u8_t code;
    u8_t ident;
    u16_t len;
} __packed;

#define BT_L2CAP_REJ_NOT_UNDERSTOOD 0x0000
#define BT_L2CAP_REJ_MTU_EXCEEDED   0x0001
#define BT_L2CAP_REJ_INVALID_CID    0x0002

#define BT_L2CAP_CMD_REJECT 0x01
struct bt_l2cap_cmd_reject {
    u16_t reason;
    u8_t data[0];
} __packed;

struct bt_l2cap_cmd_reject_cid_data {
    u16_t scid;
    u16_t dcid;
} __packed;

#define BT_L2CAP_CONN_REQ 0x02
struct bt_l2cap_conn_req {
    u16_t psm;
    u16_t scid;
} __packed;

/* command statuses in reposnse */
#define BT_L2CAP_CS_NO_INFO     0x0000
#define BT_L2CAP_CS_AUTHEN_PEND 0x0001

/* valid results in conn response on BR/EDR */
#define BT_L2CAP_BR_SUCCESS          0x0000
#define BT_L2CAP_BR_PENDING          0x0001
#define BT_L2CAP_BR_ERR_PSM_NOT_SUPP 0x0002
#define BT_L2CAP_BR_ERR_SEC_BLOCK    0x0003
#define BT_L2CAP_BR_ERR_NO_RESOURCES 0x0004
#define BT_L2CAP_BR_ERR_INVALID_SCID 0x0006
#define BT_L2CAP_BR_ERR_SCID_IN_USE  0x0007

#define BT_L2CAP_CONN_RSP 0x03
struct bt_l2cap_conn_rsp {
    u16_t dcid;
    u16_t scid;
    u16_t result;
    u16_t status;
} __packed;

#define BT_L2CAP_CONF_SUCCESS  0x0000
#define BT_L2CAP_CONF_UNACCEPT 0x0001
#define BT_L2CAP_CONF_REJECT   0x0002

#define BT_L2CAP_CONF_REQ 0x04
struct bt_l2cap_conf_req {
    u16_t dcid;
    u16_t flags;
    u8_t data[0];
} __packed;

#define BT_L2CAP_CONF_RSP 0x05
struct bt_l2cap_conf_rsp {
    u16_t scid;
    u16_t flags;
    u16_t result;
    u8_t data[0];
} __packed;

/* Option type used by MTU config request data */
#define BT_L2CAP_CONF_OPT_MTU 0x01
/* Options bits selecting most significant bit (hint) in type field */
#define BT_L2CAP_CONF_HINT 0x80
#define BT_L2CAP_CONF_MASK 0x7f

struct bt_l2cap_conf_opt {
    u8_t type;
    u8_t len;
    u8_t data[0];
} __packed;

#define BT_L2CAP_DISCONN_REQ 0x06
struct bt_l2cap_disconn_req {
    u16_t dcid;
    u16_t scid;
} __packed;

#define BT_L2CAP_DISCONN_RSP 0x07
struct bt_l2cap_disconn_rsp {
    u16_t dcid;
    u16_t scid;
} __packed;

#define BT_L2CAP_INFO_FEAT_MASK  0x0002
#define BT_L2CAP_INFO_FIXED_CHAN 0x0003

#define BT_L2CAP_INFO_REQ 0x0a
struct bt_l2cap_info_req {
    u16_t type;
} __packed;

/* info result */
#define BT_L2CAP_INFO_SUCCESS 0x0000
#define BT_L2CAP_INFO_NOTSUPP 0x0001

#define BT_L2CAP_INFO_RSP 0x0b
struct bt_l2cap_info_rsp {
    u16_t type;
    u16_t result;
    u8_t data[0];
} __packed;

#define BT_L2CAP_CONN_PARAM_REQ 0x12
struct bt_l2cap_conn_param_req {
    u16_t min_interval;
    u16_t max_interval;
    u16_t latency;
    u16_t timeout;
} __packed;

#define BT_L2CAP_CONN_PARAM_ACCEPTED 0x0000
#define BT_L2CAP_CONN_PARAM_REJECTED 0x0001

#define BT_L2CAP_CONN_PARAM_RSP 0x13
struct bt_l2cap_conn_param_rsp {
    u16_t result;
} __packed;

#define BT_L2CAP_LE_CONN_REQ 0x14
struct bt_l2cap_le_conn_req {
    u16_t psm;
    u16_t scid;
    u16_t mtu;
    u16_t mps;
    u16_t credits;
} __packed;

/* valid results in conn response on LE */
#define BT_L2CAP_LE_SUCCESS             0x0000
#define BT_L2CAP_LE_ERR_PSM_NOT_SUPP    0x0002
#define BT_L2CAP_LE_ERR_NO_RESOURCES    0x0004
#define BT_L2CAP_LE_ERR_AUTHENTICATION  0x0005
#define BT_L2CAP_LE_ERR_AUTHORIZATION   0x0006
#define BT_L2CAP_LE_ERR_KEY_SIZE        0x0007
#define BT_L2CAP_LE_ERR_ENCRYPTION      0x0008
#define BT_L2CAP_LE_ERR_INVALID_SCID    0x0009
#define BT_L2CAP_LE_ERR_SCID_IN_USE     0x000A
#define BT_L2CAP_LE_ERR_UNACCEPT_PARAMS 0x000B

#define BT_L2CAP_LE_CONN_RSP 0x15
struct bt_l2cap_le_conn_rsp {
    u16_t dcid;
    u16_t mtu;
    u16_t mps;
    u16_t credits;
    u16_t result;
};

#define BT_L2CAP_LE_CREDITS 0x16
struct bt_l2cap_le_credits {
    u16_t cid;
    u16_t credits;
} __packed;

#define BT_L2CAP_SDU_HDR_LEN 2

#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
#define BT_L2CAP_RX_MTU CONFIG_BT_L2CAP_RX_MTU
#else
#define BT_L2CAP_RX_MTU (CONFIG_BT_RX_BUF_LEN - \
                         BT_HCI_ACL_HDR_SIZE - BT_L2CAP_HDR_SIZE)
#endif

struct bt_l2cap_fixed_chan {
    u16_t cid;
    int (*accept)(struct bt_conn *conn, struct bt_l2cap_chan **chan);
    sys_snode_t node;
};

#define BT_L2CAP_CHANNEL_DEFINE(_name, _cid, _accept)               \
    const Z_STRUCT_SECTION_ITERABLE(bt_l2cap_fixed_chan, _name) = { \
        .cid = _cid,                                                \
        .accept = _accept,                                          \
    }

/* Need a name different than bt_l2cap_fixed_chan for a different section */
struct bt_l2cap_br_fixed_chan {
    u16_t cid;
    int (*accept)(struct bt_conn *conn, struct bt_l2cap_chan **chan);
};

#define BT_L2CAP_BR_CHANNEL_DEFINE(_name, _cid, _accept)               \
    const Z_STRUCT_SECTION_ITERABLE(bt_l2cap_br_fixed_chan, _name) = { \
        .cid = _cid,                                                   \
        .accept = _accept,                                             \
    }

void l2cap_chan_sdu_sent(struct bt_conn *conn, void *user_data);
/* Register a fixed L2CAP channel for L2CAP */
void bt_l2cap_le_fixed_chan_register(struct bt_l2cap_fixed_chan *chan);

/* Notify L2CAP channels of a new connection */
void bt_l2cap_connected(struct bt_conn *conn);

/* Notify L2CAP channels of a disconnect event */
void bt_l2cap_disconnected(struct bt_conn *conn);

/* Add channel to the connection */
void bt_l2cap_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan,
                       bt_l2cap_chan_destroy_t destroy);

/* Remove channel from the connection */
void bt_l2cap_chan_remove(struct bt_conn *conn, struct bt_l2cap_chan *chan);

/* Delete channel */
void bt_l2cap_chan_del(struct bt_l2cap_chan *chan);

const char *bt_l2cap_chan_state_str(bt_l2cap_chan_state_t state);

#if defined(CONFIG_BT_DEBUG_L2CAP)
void bt_l2cap_chan_set_state_debug(struct bt_l2cap_chan *chan,
                                   bt_l2cap_chan_state_t state,
                                   const char *func, int line);
#define bt_l2cap_chan_set_state(_chan, _state) \
    bt_l2cap_chan_set_state_debug(_chan, _state, __func__, __LINE__)
#else
void bt_l2cap_chan_set_state(struct bt_l2cap_chan *chan,
                             bt_l2cap_chan_state_t state);
#endif /* CONFIG_BT_DEBUG_L2CAP */

/*
 * Notify L2CAP channels of a change in encryption state passing additionally
 * HCI status of performed security procedure.
 */
void bt_l2cap_encrypt_change(struct bt_conn *conn, u8_t hci_status);

/* Prepare an L2CAP PDU to be sent over a connection */
struct net_buf *bt_l2cap_create_pdu_timeout(struct net_buf_pool *pool,
                                            size_t reserve, s32_t timeout);

#define bt_l2cap_create_pdu(_pool, _reserve) \
    bt_l2cap_create_pdu_timeout(_pool, _reserve, K_FOREVER)

/* Prepare a L2CAP Response PDU to be sent over a connection */
struct net_buf *bt_l2cap_create_rsp(struct net_buf *buf, size_t reserve);

/* Send L2CAP PDU over a connection
 *
 * Buffer ownership is transferred to stack so either in case of success
 * or error the buffer will be unref internally.
 *
 * Calling this from RX thread is assumed to never fail so the return can be
 * ignored.
 */
int bt_l2cap_send_cb(struct bt_conn *conn, u16_t cid, struct net_buf *buf,
                     bt_conn_tx_cb_t cb, void *user_data);

static inline void bt_l2cap_send(struct bt_conn *conn, u16_t cid,
                                 struct net_buf *buf)
{
    bt_l2cap_send_cb(conn, cid, buf, NULL, NULL);
}

/* Receive a new L2CAP PDU from a connection */
void bt_l2cap_recv(struct bt_conn *conn, struct net_buf *buf);

/* Perform connection parameter update request */
int bt_l2cap_update_conn_param(struct bt_conn *conn,
                               const struct bt_le_conn_param *param);

/* Initialize L2CAP and supported channels */
void bt_l2cap_init(void);

/* Lookup channel by Transmission CID */
struct bt_l2cap_chan *bt_l2cap_le_lookup_tx_cid(struct bt_conn *conn,
                                                u16_t cid);

/* Lookup channel by Receiver CID */
struct bt_l2cap_chan *bt_l2cap_le_lookup_rx_cid(struct bt_conn *conn,
                                                u16_t cid);

/* Initialize BR/EDR L2CAP signal layer */
void bt_l2cap_br_init(void);

/* Register fixed channel */
void bt_l2cap_br_fixed_chan_register(struct bt_l2cap_fixed_chan *chan);

/* Notify BR/EDR L2CAP channels about established new ACL connection */
void bt_l2cap_br_connected(struct bt_conn *conn);

/* Lookup BR/EDR L2CAP channel by Receiver CID */
struct bt_l2cap_chan *bt_l2cap_br_lookup_rx_cid(struct bt_conn *conn,
                                                u16_t cid);

/* Disconnects dynamic channel */
int bt_l2cap_br_chan_disconnect(struct bt_l2cap_chan *chan);

/* Make connection to peer psm server */
int bt_l2cap_br_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan,
                             u16_t psm);

/* Send packet data to connected peer */
int bt_l2cap_br_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf);

/*
 * Handle security level changed on link passing HCI status of performed
 * security procedure.
 */
void l2cap_br_encrypt_change(struct bt_conn *conn, u8_t hci_status);

/* Handle received data */
void bt_l2cap_br_recv(struct bt_conn *conn, struct net_buf *buf);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/monitor.c
================================================
/** @file
 *  @brief Custom logging over UART
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#if defined(CONFIG_BT_DEBUG_MONITOR)

#include "monitor.h"
#include "log.h"
#include 
#include 

void bt_monitor_send(uint16_t opcode, const void *data, size_t len) {
  const uint8_t *buf = data;
  unsigned int   key = irq_lock();
  BT_WARN("[Hci]:pkt_type:[0x%x],pkt_data:[%s]\r\n", opcode, bt_hex(buf, len));
  irq_unlock(key);
}

void bt_monitor_new_index(uint8_t type, uint8_t bus, bt_addr_t *addr, const char *name) {}
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/monitor.h
================================================
/** @file
 *  @brief Custom monitor protocol logging over UART
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#if defined(CONFIG_BT_DEBUG_MONITOR)

#define BT_MONITOR_NEW_INDEX    0
#define BT_MONITOR_DEL_INDEX    1
#define BT_MONITOR_COMMAND_PKT  2
#define BT_MONITOR_EVENT_PKT    3
#define BT_MONITOR_ACL_TX_PKT   4
#define BT_MONITOR_ACL_RX_PKT   5
#define BT_MONITOR_SCO_TX_PKT   6
#define BT_MONITOR_SCO_RX_PKT   7
#define BT_MONITOR_OPEN_INDEX   8
#define BT_MONITOR_CLOSE_INDEX  9
#define BT_MONITOR_INDEX_INFO   10
#define BT_MONITOR_VENDOR_DIAG  11
#define BT_MONITOR_SYSTEM_NOTE  12
#define BT_MONITOR_USER_LOGGING 13
#define BT_MONITOR_NOP          255

#define BT_MONITOR_TYPE_PRIMARY 0
#define BT_MONITOR_TYPE_AMP     1

/* Extended header types */
#define BT_MONITOR_COMMAND_DROPS 1
#define BT_MONITOR_EVENT_DROPS   2
#define BT_MONITOR_ACL_RX_DROPS  3
#define BT_MONITOR_ACL_TX_DROPS  4
#define BT_MONITOR_SCO_RX_DROPS  5
#define BT_MONITOR_SCO_TX_DROPS  6
#define BT_MONITOR_OTHER_DROPS   7
#define BT_MONITOR_TS32          8

#define BT_MONITOR_BASE_HDR_LEN 6

#if defined(CONFIG_BT_BREDR)
#define BT_MONITOR_EXT_HDR_MAX 19
#else
#define BT_MONITOR_EXT_HDR_MAX 15
#endif

struct bt_monitor_hdr {
    u16_t data_len;
    u16_t opcode;
    u8_t flags;
    u8_t hdr_len;

    u8_t ext[BT_MONITOR_EXT_HDR_MAX];
} __packed;

struct bt_monitor_ts32 {
    u8_t type;
    u32_t ts32;
} __packed;

struct bt_monitor_new_index {
    u8_t type;
    u8_t bus;
    u8_t bdaddr[6];
    char name[8];
} __packed;

struct bt_monitor_user_logging {
    u8_t priority;
    u8_t ident_len;
} __packed;

static inline u8_t bt_monitor_opcode(struct net_buf *buf)
{
    switch (bt_buf_get_type(buf)) {
        case BT_BUF_CMD:
            return BT_MONITOR_COMMAND_PKT;
        case BT_BUF_EVT:
            return BT_MONITOR_EVENT_PKT;
        case BT_BUF_ACL_OUT:
            return BT_MONITOR_ACL_TX_PKT;
        case BT_BUF_ACL_IN:
            return BT_MONITOR_ACL_RX_PKT;
        default:
            return BT_MONITOR_NOP;
    }
}

void bt_monitor_send(u16_t opcode, const void *data, size_t len);

void bt_monitor_new_index(u8_t type, u8_t bus, bt_addr_t *addr,
                          const char *name);

#else /* !CONFIG_BT_DEBUG_MONITOR */

#define bt_monitor_send(opcode, data, len)
#define bt_monitor_new_index(type, bus, addr, name)

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/multi_adv.c
================================================
/*
 * xx
 */

#include 
#include 

// #include 
#include 
#include 

#include "log.h"
#include "multi_adv.h"
#include "work_q.h"

static struct multi_adv_instant   g_multi_adv_list[MAX_MULTI_ADV_INSTANT];
static struct multi_adv_scheduler g_multi_adv_scheduler;
static struct k_delayed_work      g_multi_adv_timer;

void multi_adv_schedule_timeslot(struct multi_adv_scheduler *adv_scheduler);
int  multi_adv_schedule_timer_stop(void);

int multi_adv_get_instant_num(void) {
  int                       i, num = 0;
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    if (inst[i].inuse_flag)
      num++;
  }
  return num;
}

struct multi_adv_instant *multi_adv_alloc_unused_instant(void) {
  int                       i;
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    if (inst[i].inuse_flag == 0) {
      inst[i].inuse_flag = 1;
      inst[i].instant_id = i + 1;
      return &(inst[i]);
    }
  }
  return 0;
}

int multi_adv_delete_instant_by_id(int instant_id) {
  int                       i;
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    if ((inst[i].inuse_flag) && (instant_id == (inst[i].instant_id))) {
      inst[i].inuse_flag = 0;
      return 0;
    }
  }
  return -1;
}

struct multi_adv_instant *multi_adv_find_instant_by_id(int instant_id) {
  int                       i;
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    if ((inst[i].inuse_flag) && (instant_id == (inst[i].instant_id))) {
      return &(inst[i]);
    }
  }
  return 0;
}

struct multi_adv_instant *multi_adv_find_instant_by_order(int order) {
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  if (inst[order].inuse_flag) {
    return &(inst[order]);
  }
  return 0;
}

int multi_adv_set_ad_data(uint8_t *ad_data, const struct bt_data *ad, size_t ad_len) {
  int i, len;

  memset(ad_data, 0, MAX_AD_DATA_LEN);
  len = 0;
  for (i = 0; i < ad_len; i++) {
    /* Check if ad fit in the remaining buffer */
    if (len + ad[i].data_len + 2 > MAX_AD_DATA_LEN) {
      break;
    }

    ad_data[len++] = ad[i].data_len + 1;
    ad_data[len++] = ad[i].type;

    memcpy(&ad_data[len], ad[i].data, ad[i].data_len);
    len += ad[i].data_len;
  }

  return len;
}

int change_to_tick(int min_interval, int max_interval) {
  int tick;

  if (max_interval / SLOT_PER_PERIOD != min_interval / SLOT_PER_PERIOD) {
    tick = min_interval / SLOT_PER_PERIOD;
    if (min_interval % SLOT_PER_PERIOD)
      tick++;
  } else {
    tick = min_interval / SLOT_PER_PERIOD;
  }
  if (tick <= 1)
    tick = 1;

  return tick;
}

int calculate_min_multi(int a, int b) {
  int x = a, y = b, z;

  while (y != 0) {
    z = x % y;
    x = y;
    y = z;
  }

  return a * b / x;
}

void multi_adv_reorder(int inst_num, uint16_t inst_interval[], uint8_t inst_order[]) {
  int i, j;

  for (i = 0; i < inst_num; i++) {
    int max     = inst_interval[0];
    int max_idx = 0;
    int temp;

    for (j = 1; j < inst_num - i; j++) {
      if (max < inst_interval[j]) {
        max     = inst_interval[j];
        max_idx = j;
      }
    }

    temp                            = inst_interval[inst_num - i - 1];
    inst_interval[inst_num - i - 1] = inst_interval[max_idx];
    inst_interval[max_idx]          = temp;

    temp                         = inst_order[inst_num - i - 1];
    inst_order[inst_num - i - 1] = inst_order[max_idx];
    inst_order[max_idx]          = temp;
  }
}

int calculate_offset(uint16_t interval[], uint16_t offset[], int num, int duration) {
  int i, j, k, curr_offset = 0;
  int curr_max_instants, min_max_instants, instants;
  int offset_range;

  offset_range = interval[num];
  if (offset_range > duration)
    offset_range = duration;

  if (num == 0)
    return 0;

  min_max_instants = 0x7fffffff;
  /* using 0-interval-1 as offset */
  for (i = 0; i < offset_range; i++) {
    curr_max_instants = 0;
    /* search slot form 0 - duration to get the max instants number */
    for (j = 0; j < duration; j++) {
      /* get instant number in each slot */
      instants = 0;
      for (k = 0; k < num; k++) {
        if (j % interval[k] == offset[k]) {
          instants++;
        }
      }
      if (j % interval[num] == i)
        instants++;
      if (curr_max_instants < instants) {
        curr_max_instants = instants;
      }
    }

    /* check if min max instants */
    if (min_max_instants > curr_max_instants) {
      min_max_instants = curr_max_instants;
      curr_offset      = i;
    }
  }
  return curr_offset;
}

void multi_adv_schedule_table(int inst_num, uint16_t inst_interval[], uint16_t inst_offset[]) {
  int i, min_multi, last_min_multi;
  /* calculate min multi */
  last_min_multi = min_multi = inst_interval[0];
  for (i = 1; i < inst_num; i++) {
    min_multi = calculate_min_multi(min_multi, inst_interval[i]);
    if (min_multi > MAX_MIN_MULTI) {
      min_multi = last_min_multi;
      break;
    }
    last_min_multi = min_multi;
  }

  /* offset calcute for schedule just for small interval range */
  for (i = 0; i < inst_num; i++) {
    inst_offset[i] = calculate_offset(inst_interval, inst_offset, i, min_multi);
  }
}

int multi_adv_start_adv_instant(struct multi_adv_instant *adv_instant) {
  int ret;

  ret = bt_le_adv_start_instant(&adv_instant->param, adv_instant->ad, adv_instant->ad_len, adv_instant->sd, adv_instant->sd_len);
  if (ret) {
    BT_WARN("adv start instant failed: inst_id %d, err %d\r\n", adv_instant->instant_id, ret);
  }
  return ret;
}

void multi_adv_schedule_timer_handle(void) {
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;

  multi_adv_schedule_timer_stop();
  if (adv_scheduler->schedule_state == SCHEDULE_STOP)
    return;

  adv_scheduler->slot_clock  = adv_scheduler->next_slot_clock;
  adv_scheduler->slot_offset = adv_scheduler->next_slot_offset;

  multi_adv_schedule_timeslot(adv_scheduler);
  return;
}

void multi_adv_schedule_timer_callback(struct k_work *timer) {
  multi_adv_schedule_timer_handle();
  return;
}

int multi_adv_schedule_timer_start(int timeout) {
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;
  multi_adv_schedule_timer_stop();

  k_delayed_work_submit(&g_multi_adv_timer, timeout);
  adv_scheduler->schedule_timer_active = 1;

  return 1;
}

int multi_adv_schedule_timer_stop(void) {
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;

  if (adv_scheduler->schedule_timer_active) {
    k_delayed_work_cancel(&g_multi_adv_timer);
    adv_scheduler->schedule_timer_active = 0;
  }
  return 0;
}

void multi_adv_schedule_timeslot(struct multi_adv_scheduler *adv_scheduler) {
  int                       i, inst_num;
  int                       inst_clk, inst_off, match, insts = 0, next_slot, min_next_slot;
  struct multi_adv_instant *adv_instant;
  uint16_t                  inst_interval[MAX_MULTI_ADV_INSTANT];
  uint16_t                  inst_offset[MAX_MULTI_ADV_INSTANT];
  uint8_t                   inst_order[MAX_MULTI_ADV_INSTANT];
  uint8_t                   match_order[MAX_MULTI_ADV_INSTANT];

  inst_num = 0;
  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    adv_instant = multi_adv_find_instant_by_order(i);
    if (adv_instant) {
      inst_interval[inst_num] = adv_instant->instant_interval;
      inst_offset[inst_num]   = adv_instant->instant_offset;
      inst_order[inst_num]    = i;
      inst_num++;
    }
  }

  inst_clk = adv_scheduler->slot_clock;
  inst_off = adv_scheduler->slot_offset;
  match    = 0;
  for (i = 0; i < inst_num; i++) {
    if ((inst_clk % inst_interval[i]) == inst_offset[i]) {
      match_order[match] = i;
      match++;
    }
  }

  BT_DBG("multi_adv_schedule_timeslot, num = %d, match = %d", inst_num, match);
  if (match) {
    int offset_per_instant, diff;
    offset_per_instant = TIME_PRIOD_MS / match;
    diff               = inst_off - (inst_off + offset_per_instant / 2) / offset_per_instant * offset_per_instant; // TODO may be error

    /* means this is the time to start */
    if (diff <= 2) {
      insts = (inst_off + offset_per_instant / 2) / offset_per_instant;

      /* start instant */
      adv_instant = multi_adv_find_instant_by_order(inst_order[match_order[insts]]);
      if (adv_instant)
        multi_adv_start_adv_instant(adv_instant);
    }

    /* next instant in the same slot */
    if (match - insts > 1) {
      adv_scheduler->next_slot_offset = adv_scheduler->slot_offset + offset_per_instant;
      adv_scheduler->next_slot_clock  = adv_scheduler->slot_clock;

      if ((adv_scheduler->next_slot_offset >= (TIME_PRIOD_MS - 2)) && (adv_scheduler->slot_offset <= (TIME_PRIOD_MS + 2))) {
        adv_scheduler->next_slot_clock++;
        adv_scheduler->next_slot_offset = 0;
      }
      multi_adv_schedule_timer_start(offset_per_instant);
      return;
    }
  }

  /* next instant not in the same slot */
  min_next_slot = 0x7fffffff;
  for (i = 0; i < inst_num; i++) {
    if (inst_clk - inst_offset[i] < 0) {
      match = 0;
    } else {
      match = (inst_clk - inst_offset[i]) / inst_interval[i] + 1;
    }
    next_slot = match * inst_interval[i] + inst_offset[i];
    if (next_slot < min_next_slot) {
      min_next_slot = next_slot;
    }
  }
  adv_scheduler->next_slot_offset = 0;
  adv_scheduler->next_slot_clock  = min_next_slot;

  next_slot = (adv_scheduler->next_slot_clock - adv_scheduler->slot_clock) * TIME_PRIOD_MS + (adv_scheduler->next_slot_offset - adv_scheduler->slot_offset);
  multi_adv_schedule_timer_start(next_slot);
  return;
}

void multi_adv_schedule_stop(void) {
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;

  multi_adv_schedule_timer_stop();
  adv_scheduler->schedule_state = SCHEDULE_STOP;
}

void multi_adv_schedule_start(void) {
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;

  /* get all instant and calculate ticks and */
  if (adv_scheduler->schedule_state == SCHEDULE_START) {
    multi_adv_schedule_stop();
  }

  /* reinit scheduler */
  adv_scheduler->slot_clock     = 0;
  adv_scheduler->slot_offset    = 0;
  adv_scheduler->schedule_state = SCHEDULE_START;
  multi_adv_schedule_timeslot(adv_scheduler);
}

void multi_adv_new_schedule(void) {
  int                         i;
  struct multi_adv_instant   *adv_instant, *high_duty_instant;
  struct multi_adv_scheduler *adv_scheduler = &g_multi_adv_scheduler;
  uint16_t                    inst_offset[MAX_MULTI_ADV_INSTANT];
  uint16_t                    inst_interval[MAX_MULTI_ADV_INSTANT];
  uint8_t                     inst_order[MAX_MULTI_ADV_INSTANT];
  int                         inst_num = 0;

  if (adv_scheduler->schedule_state == SCHEDULE_START) {
    multi_adv_schedule_stop();
  }
  /* get all instant and calculate ticks and */
  high_duty_instant = 0;
  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    adv_instant = multi_adv_find_instant_by_order(i);
    if (adv_instant) {
      /* if high duty cycle adv found */
      if (adv_instant->param.interval_min < HIGH_DUTY_CYCLE_INTERVAL) {
        high_duty_instant = adv_instant;
        break;
      }

      inst_interval[inst_num] = change_to_tick(adv_instant->param.interval_min, adv_instant->param.interval_max);
      inst_order[inst_num]    = i;
      inst_num++;
    }
  }

  if (high_duty_instant) {
    BT_WARN("High Duty Cycle Instants, id = %d, interval = %d\n", adv_instant->instant_id, adv_instant->param.interval_min);
    multi_adv_start_adv_instant(adv_instant);
    return;
  }

  /* instant number equal 0 and 1 */
  if (inst_num == 0) {
    bt_le_adv_stop();
    return;
  }
  if (inst_num == 1) {
    adv_instant = multi_adv_find_instant_by_order(inst_order[0]);
    if (!adv_instant)
      return;
    multi_adv_start_adv_instant(adv_instant);
    return;
  }

  /* reorder by inst_interval */
  multi_adv_reorder(inst_num, inst_interval, inst_order);

  /* calcuate schedule table */
  multi_adv_schedule_table(inst_num, inst_interval, inst_offset);

  /* set interval and offset to instant */
  for (i = 0; i < inst_num; i++) {
    adv_instant = multi_adv_find_instant_by_order(inst_order[i]);
    if (!adv_instant) {
      continue;
    }
    adv_instant->instant_interval = inst_interval[i];
    adv_instant->instant_offset   = inst_offset[i];

    BT_WARN("adv_instant id = %d, interval = %d, offset = %d\n", adv_instant->instant_id, adv_instant->instant_interval, adv_instant->instant_offset);
  }

  multi_adv_schedule_start();
}

int bt_le_multi_adv_thread_init(void) {
  /* timer and event init */
  k_delayed_work_init(&g_multi_adv_timer, multi_adv_schedule_timer_callback);
  return 0;
}

int bt_le_multi_adv_start(const struct bt_le_adv_param *param, const struct bt_data *ad, size_t ad_len, const struct bt_data *sd, size_t sd_len, int *instant_id) {
  int                       instant_num;
  struct multi_adv_instant *adv_instant;

  instant_num = multi_adv_get_instant_num();
  if (instant_num >= MAX_MULTI_ADV_INSTANT)
    return -1;

  adv_instant = multi_adv_alloc_unused_instant();
  if (adv_instant == 0)
    return -1;

  memcpy(&(adv_instant->param), param, sizeof(struct bt_le_adv_param));

  adv_instant->ad_len = multi_adv_set_ad_data(adv_instant->ad, ad, ad_len);
  adv_instant->sd_len = multi_adv_set_ad_data(adv_instant->sd, sd, sd_len);

  multi_adv_new_schedule();

  *instant_id = adv_instant->instant_id;
  return 0;
}

int bt_le_multi_adv_stop(int instant_id) {
  if (multi_adv_find_instant_by_id(instant_id) == 0)
    return -1;

  BT_WARN("%s id[%d]\n", __func__, instant_id);
  multi_adv_delete_instant_by_id(instant_id);
  multi_adv_new_schedule();

  return 0;
}

bool bt_le_multi_adv_id_is_vaild(int instant_id) {
  int                       i;
  struct multi_adv_instant *inst = &(g_multi_adv_list[0]);

  for (i = 0; i < MAX_MULTI_ADV_INSTANT; i++) {
    if ((inst[i].inuse_flag) && (instant_id == (inst[i].instant_id))) {
      return true;
    }
  }
  return false;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/multi_adv.h
================================================
/*
 * xx
 */

#ifndef _MULTI_ADV_H_
#define _MULTI_ADV_H_

#define MAX_MULTI_ADV_INSTANT 4
#define MAX_AD_DATA_LEN       31

#define TIME_PRIOD_MS   (10 * (MAX_MULTI_ADV_INSTANT - 2))
#define SLOT_PER_PERIOD (TIME_PRIOD_MS * 8 / 5)

#define MAX_MIN_MULTI (30000 / TIME_PRIOD_MS)

#define HIGH_DUTY_CYCLE_INTERVAL (20 * 8 / 5)

struct multi_adv_instant {
    uint8_t inuse_flag;

    /* for parameters  */
    struct bt_le_adv_param param;
    uint8_t ad[MAX_AD_DATA_LEN];
    uint8_t ad_len;
    uint8_t sd[MAX_AD_DATA_LEN];
    uint8_t sd_len;

    /* own address maybe used */
    bt_addr_t own_addr;
    uint8_t own_addr_valid;

    /* for schedule */
    int instant_id;
    int instant_interval;
    int instant_offset;
    uint32_t clock;
    uint32_t clock_instant_offset;
    uint32_t clock_instant_total;
    uint32_t next_wakeup_time;
};

typedef enum {
    SCHEDULE_IDLE,
    SCHEDULE_READY,
    SCHEDULE_START,
    SCHEDULE_STOP,
} SCHEDULE_STATE;

struct multi_adv_scheduler {
    SCHEDULE_STATE schedule_state;
    uint8_t schedule_timer_active;
    uint32_t slot_clock;
    uint16_t slot_offset;
    uint16_t next_slot_offset;
    uint32_t next_slot_clock;
};

int bt_le_multi_adv_thread_init(void);
int bt_le_multi_adv_start(const struct bt_le_adv_param *param,
                          const struct bt_data *ad, size_t ad_len,
                          const struct bt_data *sd, size_t sd_len, int *instant_id);
int bt_le_multi_adv_stop(int instant_id);

bool bt_le_multi_adv_id_is_vaild(int instant_id);

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/rfcomm_internal.h
================================================
/** @file
 *  @brief Internal APIs for Bluetooth RFCOMM handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

typedef enum {
    BT_RFCOMM_CFC_UNKNOWN,
    BT_RFCOMM_CFC_NOT_SUPPORTED,
    BT_RFCOMM_CFC_SUPPORTED,
} __packed bt_rfcomm_cfc_t;

/* RFCOMM signalling connection specific context */
struct bt_rfcomm_session {
    /* L2CAP channel this context is associated with */
    struct bt_l2cap_br_chan br_chan;
    /* Response Timeout eXpired (RTX) timer */
    struct k_delayed_work rtx_work;
    /* Binary sem for aggregate fc */
    struct k_sem fc;
    struct bt_rfcomm_dlc *dlcs;
    uint16_t mtu;
    uint8_t state;
    bt_rfcomm_role_t role;
    bt_rfcomm_cfc_t cfc;
};

enum {
    BT_RFCOMM_STATE_IDLE,
    BT_RFCOMM_STATE_INIT,
    BT_RFCOMM_STATE_SECURITY_PENDING,
    BT_RFCOMM_STATE_CONNECTING,
    BT_RFCOMM_STATE_CONNECTED,
    BT_RFCOMM_STATE_CONFIG,
    BT_RFCOMM_STATE_USER_DISCONNECT,
    BT_RFCOMM_STATE_DISCONNECTING,
    BT_RFCOMM_STATE_DISCONNECTED,
};

struct bt_rfcomm_hdr {
    uint8_t address;
    uint8_t control;
    uint8_t length;
} __packed;

#define BT_RFCOMM_SABM 0x2f
#define BT_RFCOMM_UA   0x63
#define BT_RFCOMM_UIH  0xef

struct bt_rfcomm_msg_hdr {
    uint8_t type;
    uint8_t len;
} __packed;

#define BT_RFCOMM_PN 0x20
struct bt_rfcomm_pn {
    uint8_t dlci;
    uint8_t flow_ctrl;
    uint8_t priority;
    uint8_t ack_timer;
    uint16_t mtu;
    uint8_t max_retrans;
    uint8_t credits;
} __packed;

#define BT_RFCOMM_MSC 0x38
struct bt_rfcomm_msc {
    uint8_t dlci;
    uint8_t v24_signal;
} __packed;

#define BT_RFCOMM_DISC 0x43
#define BT_RFCOMM_DM   0x0f

#define BT_RFCOMM_RLS 0x14
struct bt_rfcomm_rls {
    uint8_t dlci;
    uint8_t line_status;
} __packed;

#define BT_RFCOMM_RPN 0x24
struct bt_rfcomm_rpn {
    uint8_t dlci;
    uint8_t baud_rate;
    uint8_t line_settings;
    uint8_t flow_control;
    uint8_t xon_char;
    uint8_t xoff_char;
    uint16_t param_mask;
} __packed;

#define BT_RFCOMM_TEST 0x08
#define BT_RFCOMM_NSC  0x04

#define BT_RFCOMM_FCON  0x28
#define BT_RFCOMM_FCOFF 0x18

/* Default RPN Settings */
#define BT_RFCOMM_RPN_BAUD_RATE_9600 0x03
#define BT_RFCOMM_RPN_DATA_BITS_8    0x03
#define BT_RFCOMM_RPN_STOP_BITS_1    0x00
#define BT_RFCOMM_RPN_PARITY_NONE    0x00
#define BT_RFCOMM_RPN_FLOW_NONE      0x00
#define BT_RFCOMM_RPN_XON_CHAR       0x11
#define BT_RFCOMM_RPN_XOFF_CHAR      0x13

/* Set 1 to all the param mask except reserved */
#define BT_RFCOMM_RPN_PARAM_MASK_ALL 0x3f7f

#define BT_RFCOMM_SET_LINE_SETTINGS(data, stop, parity) ((data & 0x3) |        \
                                                         ((stop & 0x1) << 2) | \
                                                         ((parity & 0x7) << 3))

/* DV = 1 IC = 0 RTR = 1 RTC = 1 FC = 0 EXT = 0 */
#define BT_RFCOMM_DEFAULT_V24_SIG 0x8d

#define BT_RFCOMM_GET_FC(v24_signal) (((v24_signal)&0x02) >> 1)

#define BT_RFCOMM_SIG_MIN_MTU 23
#define BT_RFCOMM_SIG_MAX_MTU 32767

#define BT_RFCOMM_CHECK_MTU(mtu) (!!((mtu) >= BT_RFCOMM_SIG_MIN_MTU && \
                                     (mtu) <= BT_RFCOMM_SIG_MAX_MTU))

/* Helper to calculate needed outgoing buffer size.
 * Length in rfcomm header can be two bytes depending on user data length.
 * One byte in the tail should be reserved for FCS.
 */
#define BT_RFCOMM_BUF_SIZE(mtu) (BT_BUF_RESERVE +                           \
                                 BT_HCI_ACL_HDR_SIZE + BT_L2CAP_HDR_SIZE +  \
                                 sizeof(struct bt_rfcomm_hdr) + 1 + (mtu) + \
                                 BT_RFCOMM_FCS_SIZE)

#define BT_RFCOMM_GET_DLCI(addr)       (((addr)&0xfc) >> 2)
#define BT_RFCOMM_GET_FRAME_TYPE(ctrl) ((ctrl)&0xef)
#define BT_RFCOMM_GET_MSG_TYPE(type)   (((type)&0xfc) >> 2)
#define BT_RFCOMM_GET_MSG_CR(type)     (((type)&0x02) >> 1)
#define BT_RFCOMM_GET_LEN(len)         (((len)&0xfe) >> 1)
#define BT_RFCOMM_GET_CHANNEL(dlci)    ((dlci) >> 1)
#define BT_RFCOMM_GET_PF(ctrl)         (((ctrl)&0x10) >> 4)

#define BT_RFCOMM_SET_ADDR(dlci, cr) ((((dlci)&0x3f) << 2) | \
                                      ((cr) << 1) | 0x01)
#define BT_RFCOMM_SET_CTRL(type, pf)     (((type)&0xef) | ((pf) << 4))
#define BT_RFCOMM_SET_LEN_8(len)         (((len) << 1) | 1)
#define BT_RFCOMM_SET_LEN_16(len)        ((len) << 1)
#define BT_RFCOMM_SET_MSG_TYPE(type, cr) (((type) << 2) | (cr << 1) | 0x01)

#define BT_RFCOMM_LEN_EXTENDED(len) (!((len)&0x01))

/* For CR in UIH Packet header
 * Initiating station have the C/R bit set to 1 and those sent by the
 * responding station have the C/R bit set to 0
 */
#define BT_RFCOMM_UIH_CR(role) ((role) == BT_RFCOMM_ROLE_INITIATOR)

/* For CR in Non UIH Packet header
 * Command
 * Initiator --> Responder 1
 * Responder --> Initiator 0
 * Response
 * Initiator --> Responder 0
 * Responder --> Initiator 1
 */
#define BT_RFCOMM_CMD_CR(role)  ((role) == BT_RFCOMM_ROLE_INITIATOR)
#define BT_RFCOMM_RESP_CR(role) ((role) == BT_RFCOMM_ROLE_ACCEPTOR)

/* For CR in MSG header
 * If the C/R bit is set to 1 the message is a command,
 * if it is set to 0 the message is a response.
 */
#define BT_RFCOMM_MSG_CMD_CR  1
#define BT_RFCOMM_MSG_RESP_CR 0

#define BT_RFCOMM_DLCI(role, channel) ((((channel)&0x1f) << 1) | \
                                       ((role) == BT_RFCOMM_ROLE_ACCEPTOR))

/* Excluding ext bit */
#define BT_RFCOMM_MAX_LEN_8 127

/* Length can be 2 bytes depending on data size */
#define BT_RFCOMM_HDR_SIZE (sizeof(struct bt_rfcomm_hdr) + 1)
#define BT_RFCOMM_FCS_SIZE 1

#define BT_RFCOMM_FCS_LEN_UIH     2
#define BT_RFCOMM_FCS_LEN_NON_UIH 3

/* For non UIH packets
 * The P bit set to 1 shall be used to solicit a response frame with the
 * F bit set to 1 from the other station.
 */
#define BT_RFCOMM_PF_NON_UIH 1

/* For UIH packets
 * Both stations set the P-bit to 0
 * If credit based flow control is used, If P/F is 1 then one credit byte
 * will be there after control in the frame else no credit byte.
 */
#define BT_RFCOMM_PF_UIH           0
#define BT_RFCOMM_PF_UIH_CREDIT    1
#define BT_RFCOMM_PF_UIH_NO_CREDIT 0

#define BT_RFCOMM_PN_CFC_CMD  0xf0
#define BT_RFCOMM_PN_CFC_RESP 0xe0

/* Initialize RFCOMM signal layer */
void bt_rfcomm_init(void);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/sdp.c
================================================
/** @file
 *  @brief Service Discovery Protocol handling.
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 

#include <../bluetooth/buf.h>
#include <../bluetooth/sdp.h>

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_SDP)
#define LOG_MODULE_NAME bt_sdp
#include "log.h"

#include "conn_internal.h"
#include "hci_core.h"
#include "l2cap_internal.h"
#include "sdp_internal.h"

#define SDP_PSM 0x0001

#define SDP_CHAN(_ch) CONTAINER_OF(_ch, struct bt_sdp, chan.chan)

#define IN_RANGE(val, min, max) (val >= min && val <= max)

#define SDP_DATA_MTU 200

#define SDP_MTU (SDP_DATA_MTU + sizeof(struct bt_sdp_hdr))

#define MAX_NUM_ATT_ID_FILTER 10

#define SDP_SERVICE_HANDLE_BASE 0x10000

#define SDP_DATA_ELEM_NEST_LEVEL_MAX 5

/* Size of Cont state length */
#define SDP_CONT_STATE_LEN_SIZE 1

/* 1 byte for the no. of services searched till this response */
/* 2 bytes for the total no. of matching records */
#define SDP_SS_CONT_STATE_SIZE 3

/* 1 byte for the no. of attributes searched till this response */
#define SDP_SA_CONT_STATE_SIZE 1

/* 1 byte for the no. of services searched till this response */
/* 1 byte for the no. of attributes searched till this response */
#define SDP_SSA_CONT_STATE_SIZE 2

#define SDP_INVALID 0xff

struct bt_sdp {
  struct bt_l2cap_br_chan chan;
  struct k_fifo           partial_resp_queue;
  /* TODO: Allow more than one pending request */
};

static struct bt_sdp_record *db;
static uint8_t               num_services;

static struct bt_sdp bt_sdp_pool[CONFIG_BT_MAX_CONN];

/* Pool for outgoing SDP packets */
#if !defined(BFLB_DYNAMIC_ALLOC_MEM)
NET_BUF_POOL_FIXED_DEFINE(sdp_pool, CONFIG_BT_MAX_CONN, BT_L2CAP_BUF_SIZE(SDP_MTU), NULL);
#else
struct net_buf_pool sdp_pool;
#endif

#define SDP_CLIENT_CHAN(_ch) CONTAINER_OF(_ch, struct bt_sdp_client, chan.chan)

#define SDP_CLIENT_MTU 64

struct bt_sdp_client {
  struct bt_l2cap_br_chan chan;
  /* list of waiting to be resolved UUID params */
  sys_slist_t reqs;
  /* required SDP transaction ID */
  uint16_t tid;
  /* UUID params holder being now resolved */
  const struct bt_sdp_discover_params *param;
  /* PDU continuation state object */
  struct bt_sdp_pdu_cstate cstate;
  /* buffer for collecting record data */
  struct net_buf *rec_buf;
};

static struct bt_sdp_client bt_sdp_client_pool[CONFIG_BT_MAX_CONN];

enum {
  BT_SDP_ITER_STOP,
  BT_SDP_ITER_CONTINUE,
};

struct search_state {
  uint16_t att_list_size;
  uint8_t  current_svc;
  uint8_t  last_att;
  bool     pkt_full;
};

struct select_attrs_data {
  struct bt_sdp_record        *rec;
  struct net_buf              *rsp_buf;
  struct bt_sdp               *sdp;
  struct bt_sdp_data_elem_seq *seq;
  struct search_state         *state;
  uint32_t                    *filter;
  uint16_t                     max_att_len;
  uint16_t                     att_list_len;
  uint8_t                      cont_state_size;
  uint8_t                      num_filters;
  bool                         new_service;
};

/* @typedef bt_sdp_attr_func_t
 *  @brief SDP attribute iterator callback.
 *
 *  @param attr Attribute found.
 *  @param att_idx Index of the found attribute in the attribute database.
 *  @param user_data Data given.
 *
 *  @return BT_SDP_ITER_CONTINUE if should continue to the next attribute
 *  or BT_SDP_ITER_STOP to stop.
 */
typedef uint8_t (*bt_sdp_attr_func_t)(struct bt_sdp_attribute *attr, uint8_t att_idx, void *user_data);

/* @typedef bt_sdp_svc_func_t
 * @brief SDP service record iterator callback.
 *
 * @param rec Service record found.
 * @param user_data Data given.
 *
 * @return BT_SDP_ITER_CONTINUE if should continue to the next service record
 *  or BT_SDP_ITER_STOP to stop.
 */
typedef uint8_t (*bt_sdp_svc_func_t)(struct bt_sdp_record *rec, void *user_data);

/* @brief Callback for SDP connection
 *
 *  Gets called when an SDP connection is established
 *
 *  @param chan L2CAP channel
 *
 *  @return None
 */
static void bt_sdp_connected(struct bt_l2cap_chan *chan) {
  struct bt_l2cap_br_chan *ch = CONTAINER_OF(chan, struct bt_l2cap_br_chan, chan);

  struct bt_sdp *sdp = CONTAINER_OF(ch, struct bt_sdp, chan);

  BT_DBG("chan %p cid 0x%04x", ch, ch->tx.cid);

  k_fifo_init(&sdp->partial_resp_queue, 20); // MBHJ
}

/** @brief Callback for SDP disconnection
 *
 *  Gets called when an SDP connection is terminated
 *
 *  @param chan L2CAP channel
 *
 *  @return None
 */
static void bt_sdp_disconnected(struct bt_l2cap_chan *chan) {
  struct bt_l2cap_br_chan *ch = CONTAINER_OF(chan, struct bt_l2cap_br_chan, chan);

  struct bt_sdp *sdp = CONTAINER_OF(ch, struct bt_sdp, chan);

  BT_DBG("chan %p cid 0x%04x", ch, ch->tx.cid);

  (void)memset(sdp, 0, sizeof(*sdp));
}

/* @brief Creates an SDP PDU
 *
 *  Creates an empty SDP PDU and returns the buffer
 *
 *  @param None
 *
 *  @return Pointer to the net_buf buffer
 */
static struct net_buf *bt_sdp_create_pdu(void) { return bt_l2cap_create_pdu(&sdp_pool, sizeof(struct bt_sdp_hdr)); }

/* @brief Sends out an SDP PDU
 *
 *  Sends out an SDP PDU after adding the relevant header
 *
 *  @param chan L2CAP channel
 *  @param buf Buffer to be sent out
 *  @param op Opcode to be used in the packet header
 *  @param tid Transaction ID to be used in the packet header
 *
 *  @return None
 */
static void bt_sdp_send(struct bt_l2cap_chan *chan, struct net_buf *buf, uint8_t op, uint16_t tid) {
  struct bt_sdp_hdr *hdr;
  uint16_t           param_len = buf->len;

  hdr            = net_buf_push(buf, sizeof(struct bt_sdp_hdr));
  hdr->op_code   = op;
  hdr->tid       = tid;
  hdr->param_len = sys_cpu_to_be16(param_len);

  bt_l2cap_chan_send(chan, buf);
}

/* @brief Sends an error response PDU
 *
 *  Creates and sends an error response PDU
 *
 *  @param chan L2CAP channel
 *  @param err Error code to be sent in the packet
 *  @param tid Transaction ID to be used in the packet header
 *
 *  @return None
 */
static void send_err_rsp(struct bt_l2cap_chan *chan, uint16_t err, uint16_t tid) {
  struct net_buf *buf;

  BT_DBG("tid %u, error %u", tid, err);

  buf = bt_sdp_create_pdu();

  net_buf_add_be16(buf, err);

  bt_sdp_send(chan, buf, BT_SDP_ERROR_RSP, tid);
}

/* @brief Parses data elements from a net_buf
 *
 * Parses the first data element from a buffer and splits it into type, size,
 * data. Used for parsing incoming requests. Net buf is advanced to the data
 * part of the element.
 *
 * @param buf Buffer to be advanced
 * @param data_elem Pointer to the parsed data element structure
 *
 * @return 0 for success, or relevant error code
 */
static uint16_t parse_data_elem(struct net_buf *buf, struct bt_sdp_data_elem *data_elem) {
  uint8_t size_field_len = 0U; /* Space used to accommodate the size */

  if (buf->len < 1) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  data_elem->type = net_buf_pull_u8(buf);

  switch (data_elem->type & BT_SDP_TYPE_DESC_MASK) {
  case BT_SDP_UINT8:
  case BT_SDP_INT8:
  case BT_SDP_UUID_UNSPEC:
  case BT_SDP_BOOL:
    data_elem->data_size = BIT(data_elem->type & BT_SDP_SIZE_DESC_MASK);
    break;
  case BT_SDP_TEXT_STR_UNSPEC:
  case BT_SDP_SEQ_UNSPEC:
  case BT_SDP_ALT_UNSPEC:
  case BT_SDP_URL_STR_UNSPEC:
    size_field_len = BIT((data_elem->type & BT_SDP_SIZE_DESC_MASK) - BT_SDP_SIZE_INDEX_OFFSET);
    if (buf->len < size_field_len) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }
    switch (size_field_len) {
    case 1:
      data_elem->data_size = net_buf_pull_u8(buf);
      break;
    case 2:
      data_elem->data_size = net_buf_pull_be16(buf);
      break;
    case 4:
      data_elem->data_size = net_buf_pull_be32(buf);
      break;
    default:
      BT_WARN("Invalid size in remote request");
      return BT_SDP_INVALID_SYNTAX;
    }
    break;
  default:
    BT_WARN("Invalid type in remote request");
    return BT_SDP_INVALID_SYNTAX;
  }

  if (buf->len < data_elem->data_size) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  data_elem->total_size = data_elem->data_size + size_field_len + 1;
  data_elem->data       = buf->data;

  return 0;
}

/* @brief Searches for an UUID within an attribute
 *
 * Searches for an UUID within an attribute. If the attribute has data element
 * sequences, it recursively searches within them as well. On finding a match
 * with the UUID, it sets the found flag.
 *
 * @param elem Attribute to be used as the search space (haystack)
 * @param uuid UUID to be looked for (needle)
 * @param found Flag set to true if the UUID is found (to be returned)
 * @param nest_level Used to limit the extent of recursion into nested data
 *  elements, to avoid potential stack overflows
 *
 * @return Size of the last data element that has been searched
 *  (used in recursion)
 */
static uint32_t search_uuid(struct bt_sdp_data_elem *elem, struct bt_uuid *uuid, bool *found, uint8_t nest_level) {
  const uint8_t *cur_elem;
  uint32_t       seq_size, size;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_32  u32;
    struct bt_uuid_128 u128;
  } u;

  if (*found) {
    return 0;
  }

  /* Limit recursion depth to avoid stack overflows */
  if (nest_level == SDP_DATA_ELEM_NEST_LEVEL_MAX) {
    return 0;
  }

  seq_size = elem->data_size;
  cur_elem = elem->data;

  if ((elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_UUID_UNSPEC) {
    if (seq_size == 2U) {
      u.uuid.type = BT_UUID_TYPE_16;
      u.u16.val   = *((uint16_t *)cur_elem);
      if (!bt_uuid_cmp(&u.uuid, uuid)) {
        *found = true;
      }
    } else if (seq_size == 4U) {
      u.uuid.type = BT_UUID_TYPE_32;
      u.u32.val   = *((uint32_t *)cur_elem);
      if (!bt_uuid_cmp(&u.uuid, uuid)) {
        *found = true;
      }
    } else if (seq_size == 16U) {
      u.uuid.type = BT_UUID_TYPE_128;
      memcpy(u.u128.val, cur_elem, seq_size);
      if (!bt_uuid_cmp(&u.uuid, uuid)) {
        *found = true;
      }
    } else {
      BT_WARN("Invalid UUID size in local database");
      BT_ASSERT(0);
    }
  }

  if ((elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_SEQ_UNSPEC || (elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_ALT_UNSPEC) {
    do {
      /* Recursively parse data elements */
      size = search_uuid((struct bt_sdp_data_elem *)cur_elem, uuid, found, nest_level + 1);
      if (*found) {
        return 0;
      }
      cur_elem += sizeof(struct bt_sdp_data_elem);
      seq_size -= size;
    } while (seq_size);
  }

  return elem->total_size;
}

/* @brief SDP service record iterator.
 *
 * Iterate over service records from a starting point.
 *
 * @param func Callback function.
 * @param user_data Data to pass to the callback.
 *
 * @return Pointer to the record where the iterator stopped, or NULL if all
 *  records are covered
 */
static struct bt_sdp_record *bt_sdp_foreach_svc(bt_sdp_svc_func_t func, void *user_data) {
  struct bt_sdp_record *rec = db;

  while (rec) {
    if (func(rec, user_data) == BT_SDP_ITER_STOP) {
      break;
    }

    rec = rec->next;
  }
  return rec;
}

/* @brief Inserts a service record into a record pointer list
 *
 * Inserts a service record into a record pointer list
 *
 * @param rec The current service record.
 * @param user_data Pointer to the destination record list.
 *
 * @return BT_SDP_ITER_CONTINUE to move on to the next record.
 */
static uint8_t insert_record(struct bt_sdp_record *rec, void *user_data) {
  struct bt_sdp_record **rec_list = user_data;

  rec_list[rec->index] = rec;

  return BT_SDP_ITER_CONTINUE;
}

/* @brief Looks for matching UUIDs in a list of service records
 *
 * Parses out a sequence of UUIDs from an input buffer, and checks if a record
 * in the list contains all the UUIDs. If it doesn't, the record is removed
 * from the list, so the list contains only the records which has all the
 * input UUIDs in them.
 *
 * @param buf Incoming buffer containing all the UUIDs to be matched
 * @param matching_recs List of service records to use for storing matching
 * records
 *
 * @return 0 for success, or relevant error code
 */
static uint16_t find_services(struct net_buf *buf, struct bt_sdp_record **matching_recs) {
  struct bt_sdp_data_elem data_elem;
  struct bt_sdp_record   *record;
  uint32_t                uuid_list_size;
  uint16_t                res;
  uint8_t                 att_idx, rec_idx = 0U;
  bool                    found;
  union {
    struct bt_uuid     uuid;
    struct bt_uuid_16  u16;
    struct bt_uuid_32  u32;
    struct bt_uuid_128 u128;
  } u;

  res = parse_data_elem(buf, &data_elem);
  if (res) {
    return res;
  }

  if (((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_SEQ_UNSPEC) && ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_ALT_UNSPEC)) {
    BT_WARN("Invalid type %x in service search pattern", data_elem.type);
    return BT_SDP_INVALID_SYNTAX;
  }

  uuid_list_size = data_elem.data_size;

  bt_sdp_foreach_svc(insert_record, matching_recs);

  /* Go over the sequence of UUIDs, and match one UUID at a time */
  while (uuid_list_size) {
    res = parse_data_elem(buf, &data_elem);
    if (res) {
      return res;
    }

    if ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_UUID_UNSPEC) {
      BT_WARN("Invalid type %u in service search pattern", data_elem.type);
      return BT_SDP_INVALID_SYNTAX;
    }

    if (buf->len < data_elem.data_size) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }

    if (data_elem.data_size == 2U) {
      u.uuid.type = BT_UUID_TYPE_16;
      u.u16.val   = net_buf_pull_be16(buf);
    } else if (data_elem.data_size == 4U) {
      u.uuid.type = BT_UUID_TYPE_32;
      u.u32.val   = net_buf_pull_be32(buf);
    } else if (data_elem.data_size == 16U) {
      u.uuid.type = BT_UUID_TYPE_128;
      sys_memcpy_swap(u.u128.val, buf->data, data_elem.data_size);
      net_buf_pull(buf, data_elem.data_size);
    } else {
      BT_WARN("Invalid UUID len %u in service search pattern", data_elem.data_size);
      net_buf_pull(buf, data_elem.data_size);
    }

    uuid_list_size -= data_elem.total_size;

    /* Go over the list of services, and look for a service which
     * doesn't have this UUID
     */
    for (rec_idx = 0U; rec_idx < num_services; rec_idx++) {
      record = matching_recs[rec_idx];

      if (!record) {
        continue;
      }

      found = false;

      /* Search for the UUID in all the attrs of the svc */
      for (att_idx = 0U; att_idx < record->attr_count; att_idx++) {
        search_uuid(&record->attrs[att_idx].val, &u.uuid, &found, 1);
        if (found) {
          break;
        }
      }

      /* Remove the record from the list if it doesn't have
       * the UUID
       */
      if (!found) {
        matching_recs[rec_idx] = NULL;
      }
    }
  }

  return 0;
}

/* @brief Handler for Service Search Request
 *
 * Parses, processes and responds to a Service Search Request
 *
 * @param sdp Pointer to the SDP structure
 * @param buf Request net buf
 * @param tid Transaction ID
 *
 * @return 0 for success, or relevant error code
 */
static uint16_t sdp_svc_search_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid) {
  struct bt_sdp_svc_rsp *rsp;
  struct net_buf        *resp_buf;
  struct bt_sdp_record  *record;
  struct bt_sdp_record  *matching_recs[BT_SDP_MAX_SERVICES];
  uint16_t               max_rec_count, total_recs = 0U, current_recs = 0U, res;
  uint8_t                cont_state_size, cont_state = 0U, idx = 0U, count = 0U;
  bool                   pkt_full = false;

  res = find_services(buf, matching_recs);
  if (res) {
    /* Error in parsing */
    return res;
  }

  if (buf->len < 3) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  max_rec_count   = net_buf_pull_be16(buf);
  cont_state_size = net_buf_pull_u8(buf);

  /* Zero out the matching services beyond max_rec_count */
  for (idx = 0U; idx < num_services; idx++) {
    if (count == max_rec_count) {
      matching_recs[idx] = NULL;
      continue;
    }

    if (matching_recs[idx]) {
      count++;
    }
  }

  /* We send out only SDP_SS_CONT_STATE_SIZE bytes continuation state in
   * responses, so expect only SDP_SS_CONT_STATE_SIZE bytes in requests
   */
  if (cont_state_size) {
    if (cont_state_size != SDP_SS_CONT_STATE_SIZE) {
      BT_WARN("Invalid cont state size %u", cont_state_size);
      return BT_SDP_INVALID_CSTATE;
    }

    if (buf->len < cont_state_size) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }

    cont_state = net_buf_pull_u8(buf);
    /* We include total_recs in the continuation state. We calculate
     * it once and preserve it across all the partial responses
     */
    total_recs = net_buf_pull_be16(buf);
  }

  BT_DBG("max_rec_count %u, cont_state %u", max_rec_count, cont_state);

  resp_buf = bt_sdp_create_pdu();
  rsp      = net_buf_add(resp_buf, sizeof(*rsp));

  for (; cont_state < num_services; cont_state++) {
    record = matching_recs[cont_state];

    if (!record) {
      continue;
    }

    /* Calculate total recs only if it is first packet */
    if (!cont_state_size) {
      total_recs++;
    }

    if (pkt_full) {
      continue;
    }

    /* 4 bytes per Service Record Handle */
    /* 4 bytes for ContinuationState */
    if ((MIN(SDP_MTU, sdp->chan.tx.mtu) - resp_buf->len) < (4 + 4 + sizeof(struct bt_sdp_hdr))) {
      pkt_full = true;
    }

    if (pkt_full) {
      /* Packet exhausted: Add continuation state and break */
      BT_DBG("Packet full, num_services_covered %u", cont_state);
      net_buf_add_u8(resp_buf, SDP_SS_CONT_STATE_SIZE);
      net_buf_add_u8(resp_buf, cont_state);

      /* If it is the first packet of a partial response,
       * continue dry-running to calculate total_recs.
       * Else break
       */
      if (cont_state_size) {
        break;
      }

      continue;
    }

    /* Add the service record handle to the packet */
    net_buf_add_be32(resp_buf, record->handle);
    current_recs++;
  }

  /* Add 0 continuation state if packet is exhausted */
  if (!pkt_full) {
    net_buf_add_u8(resp_buf, 0);
  } else {
    net_buf_add_be16(resp_buf, total_recs);
  }

  rsp->total_recs   = sys_cpu_to_be16(total_recs);
  rsp->current_recs = sys_cpu_to_be16(current_recs);

  BT_DBG("Sending response, len %u", resp_buf->len);
  bt_sdp_send(&sdp->chan.chan, resp_buf, BT_SDP_SVC_SEARCH_RSP, tid);

  return 0;
}

/* @brief Copies an attribute into an outgoing buffer
 *
 *  Copies an attribute into a buffer. Recursively calls itself for complex
 *  attributes.
 *
 *  @param elem Attribute to be copied to the buffer
 *  @param buf Buffer where the attribute is to be copied
 *
 *  @return Size of the last data element that has been searched
 *  (used in recursion)
 */
static uint32_t copy_attribute(struct bt_sdp_data_elem *elem, struct net_buf *buf, uint8_t nest_level) {
  const uint8_t *cur_elem;
  uint32_t       size, seq_size, total_size;

  /* Limit recursion depth to avoid stack overflows */
  if (nest_level == SDP_DATA_ELEM_NEST_LEVEL_MAX) {
    return 0;
  }

  seq_size   = elem->data_size;
  total_size = elem->total_size;
  cur_elem   = elem->data;

  /* Copy the header */
  net_buf_add_u8(buf, elem->type);

  switch (total_size - (seq_size + 1U)) {
  case 1:
    net_buf_add_u8(buf, elem->data_size);
    break;
  case 2:
    net_buf_add_be16(buf, elem->data_size);
    break;
  case 4:
    net_buf_add_be32(buf, elem->data_size);
    break;
  }

  /* Recursively parse (till the last element is not another data element)
   * and then fill the elements
   */
  if ((elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_SEQ_UNSPEC || (elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_ALT_UNSPEC) {
    do {
      size = copy_attribute((struct bt_sdp_data_elem *)cur_elem, buf, nest_level + 1);
      cur_elem += sizeof(struct bt_sdp_data_elem);
      seq_size -= size;
    } while (seq_size);
  } else if ((elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_UINT8 || (elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_INT8 || (elem->type & BT_SDP_TYPE_DESC_MASK) == BT_SDP_UUID_UNSPEC) {
    if (seq_size == 1U) {
      net_buf_add_u8(buf, *((uint8_t *)elem->data));
    } else if (seq_size == 2U) {
      net_buf_add_be16(buf, *((uint16_t *)elem->data));
    } else if (seq_size == 4U) {
      net_buf_add_be32(buf, *((uint32_t *)elem->data));
    } else {
      /* TODO: Convert 32bit and 128bit values to big-endian*/
      net_buf_add_mem(buf, elem->data, seq_size);
    }
  } else {
    net_buf_add_mem(buf, elem->data, seq_size);
  }

  return total_size;
}

/* @brief SDP attribute iterator.
 *
 *  Iterate over attributes of a service record from a starting index.
 *
 *  @param record Service record whose attributes are to be iterated over.
 *  @param idx Index in the attribute list from where to start.
 *  @param func Callback function.
 *  @param user_data Data to pass to the callback.
 *
 *  @return Index of the attribute where the iterator stopped
 */
static uint8_t bt_sdp_foreach_attr(struct bt_sdp_record *record, uint8_t idx, bt_sdp_attr_func_t func, void *user_data) {
  for (; idx < record->attr_count; idx++) {
    if (func(&record->attrs[idx], idx, user_data) == BT_SDP_ITER_STOP) {
      break;
    }
  }

  return idx;
}

/* @brief Check if an attribute matches a range, and include it in the response
 *
 *  Checks if an attribute matches a given attribute ID or range, and if so,
 *  includes it in the response packet
 *
 *  @param attr The current attribute
 *  @param att_idx Index of the current attribute in the database
 *  @param user_data Pointer to the structure containing response packet, byte
 *   count, states, etc
 *
 *  @return BT_SDP_ITER_CONTINUE if should continue to the next attribute
 *   or BT_SDP_ITER_STOP to stop.
 */
static uint8_t select_attrs(struct bt_sdp_attribute *attr, uint8_t att_idx, void *user_data) {
  struct select_attrs_data *sad = user_data;
  uint16_t                  att_id_lower, att_id_upper, att_id_cur, space;
  uint32_t                  attr_size, seq_size;
  uint8_t                   idx_filter;

  for (idx_filter = 0U; idx_filter < sad->num_filters; idx_filter++) {
    att_id_lower = (sad->filter[idx_filter] >> 16);
    att_id_upper = (sad->filter[idx_filter]);
    att_id_cur   = attr->id;

    /* Check for range values */
    if (att_id_lower != 0xffff && (!IN_RANGE(att_id_cur, att_id_lower, att_id_upper))) {
      continue;
    }

    /* Check for match values */
    if (att_id_lower == 0xffff && att_id_cur != att_id_upper) {
      continue;
    }

    /* Attribute ID matches */

    /* 3 bytes for Attribute ID */
    attr_size = 3 + attr->val.total_size;

    /* If this is the first attribute of the service, then we need
     * to account for the space required to add the per-service
     * data element sequence header as well.
     */
    if ((sad->state->current_svc != sad->rec->index) && sad->new_service) {
      /* 3 bytes for Per-Service Data Elem Seq declaration */
      seq_size = attr_size + 3;
    } else {
      seq_size = attr_size;
    }

    if (sad->rsp_buf) {
      space = MIN(SDP_MTU, sad->sdp->chan.tx.mtu) - sad->rsp_buf->len - sizeof(struct bt_sdp_hdr);

      if ((!sad->state->pkt_full) && ((seq_size > sad->max_att_len) || (space < seq_size + sad->cont_state_size))) {
        /* Packet exhausted */
        sad->state->pkt_full = true;
      }
    }

    /* Keep filling data only if packet is not exhausted */
    if (!sad->state->pkt_full && sad->rsp_buf) {
      /* Add Per-Service Data Element Seq declaration once
       * only when we are starting from the first attribute
       */
      if (!sad->seq && (sad->state->current_svc != sad->rec->index)) {
        sad->seq       = net_buf_add(sad->rsp_buf, sizeof(*sad->seq));
        sad->seq->type = BT_SDP_SEQ16;
        sad->seq->size = 0U;
      }

      /* Add attribute ID */
      net_buf_add_u8(sad->rsp_buf, BT_SDP_UINT16);
      net_buf_add_be16(sad->rsp_buf, att_id_cur);

      /* Add attribute value */
      copy_attribute(&attr->val, sad->rsp_buf, 1);

      sad->max_att_len -= seq_size;
      sad->att_list_len += seq_size;
      sad->state->last_att    = att_idx;
      sad->state->current_svc = sad->rec->index;
    }

    if (sad->seq) {
      /* Keep adding the sequence size if this packet contains
       * the Per-Service Data Element Seq declaration header
       */
      sad->seq->size += attr_size;
      sad->state->att_list_size += seq_size;
    } else {
      /* Keep adding the total attr lists size if:
       * It's a dry-run, calculating the total attr lists size
       */
      sad->state->att_list_size += seq_size;
    }

    sad->new_service = false;
    break;
  }

  /* End the search if:
   * 1. We have exhausted the packet
   * AND
   * 2. This packet doesn't contain the service element declaration header
   * AND
   * 3. This is not a dry-run (then we look for other attrs that match)
   */
  if (sad->state->pkt_full && !sad->seq && sad->rsp_buf) {
    return BT_SDP_ITER_STOP;
  }

  return BT_SDP_ITER_CONTINUE;
}

/* @brief Creates attribute list in the given buffer
 *
 *  Populates the attribute list of a service record in the buffer. To be used
 *  for responding to Service Attribute and Service Search Attribute requests
 *
 *  @param sdp Pointer to the SDP structure
 *  @param record Service record whose attributes are to be included in the
 *   response
 *  @param filter Attribute values/ranges to be used as a filter
 *  @param num_filters Number of elements in the attribute filter
 *  @param max_att_len Maximum size of attributes to be included in the response
 *  @param cont_state_size No. of additional continuation state bytes to keep
 *   space for in the packet. This will vary based on the type of the request
 *  @param next_att Starting position of the search in the service's attr list
 *  @param state State of the overall search
 *  @param rsp_buf Response buffer which is filled in
 *
 *  @return len Length of the attribute list created
 */
static uint16_t create_attr_list(struct bt_sdp *sdp, struct bt_sdp_record *record, uint32_t *filter, uint8_t num_filters, uint16_t max_att_len, uint8_t cont_state_size, uint8_t next_att,
                                 struct search_state *state, struct net_buf *rsp_buf) {
  struct select_attrs_data sad;
  uint8_t                  idx_att;

  sad.num_filters     = num_filters;
  sad.rec             = record;
  sad.rsp_buf         = rsp_buf;
  sad.sdp             = sdp;
  sad.max_att_len     = max_att_len;
  sad.cont_state_size = cont_state_size;
  sad.seq             = NULL;
  sad.filter          = filter;
  sad.state           = state;
  sad.att_list_len    = 0U;
  sad.new_service     = true;

  idx_att = bt_sdp_foreach_attr(sad.rec, next_att, select_attrs, &sad);

  if (sad.seq) {
    sad.seq->size = sys_cpu_to_be16(sad.seq->size);
  }

  return sad.att_list_len;
}

/* @brief Extracts the attribute search list from a buffer
 *
 *  Parses a buffer to extract the attribute search list (list of attribute IDs
 *  and ranges) which are to be used to filter attributes.
 *
 *  @param buf Buffer to be parsed for extracting the attribute search list
 *  @param filter Empty list of 4byte filters that are filled in. For attribute
 *   IDs, the lower 2 bytes contain the ID and the upper 2 bytes are set to
 *   0xFFFF. For attribute ranges, the lower 2bytes indicate the start ID and
 *   the upper 2bytes indicate the end ID
 *  @param num_filters No. of filter elements filled in (to be returned)
 *
 *  @return 0 for success, or relevant error code
 */
static uint16_t get_att_search_list(struct net_buf *buf, uint32_t *filter, uint8_t *num_filters) {
  struct bt_sdp_data_elem data_elem;
  uint16_t                res;
  uint32_t                size;

  *num_filters = 0U;
  res          = parse_data_elem(buf, &data_elem);
  if (res) {
    return res;
  }

  size = data_elem.data_size;

  while (size) {
    res = parse_data_elem(buf, &data_elem);
    if (res) {
      return res;
    }

    if ((data_elem.type & BT_SDP_TYPE_DESC_MASK) != BT_SDP_UINT8) {
      BT_WARN("Invalid type %u in attribute ID list", data_elem.type);
      return BT_SDP_INVALID_SYNTAX;
    }

    if (buf->len < data_elem.data_size) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }

    /* This is an attribute ID */
    if (data_elem.data_size == 2U) {
      filter[(*num_filters)++] = 0xffff0000 | net_buf_pull_be16(buf);
    }

    /* This is an attribute ID range */
    if (data_elem.data_size == 4U) {
      filter[(*num_filters)++] = net_buf_pull_be32(buf);
    }

    size -= data_elem.total_size;
  }

  return 0;
}

/* @brief Check if a given handle matches that of the current service
 *
 *  Checks if a given handle matches that of the current service
 *
 *  @param rec The current service record
 *  @param user_data Pointer to the service record handle to be matched
 *
 *  @return BT_SDP_ITER_CONTINUE if should continue to the next record
 *   or BT_SDP_ITER_STOP to stop.
 */
static uint8_t find_handle(struct bt_sdp_record *rec, void *user_data) {
  uint32_t *svc_rec_hdl = user_data;

  if (rec->handle == *svc_rec_hdl) {
    return BT_SDP_ITER_STOP;
  }

  return BT_SDP_ITER_CONTINUE;
}

/* @brief Handler for Service Attribute Request
 *
 *  Parses, processes and responds to a Service Attribute Request
 *
 *  @param sdp Pointer to the SDP structure
 *  @param buf Request buffer
 *  @param tid Transaction ID
 *
 *  @return 0 for success, or relevant error code
 */
static uint16_t sdp_svc_att_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid) {
  uint32_t               filter[MAX_NUM_ATT_ID_FILTER];
  struct search_state    state = {.current_svc = SDP_INVALID, .last_att = SDP_INVALID, .pkt_full = false};
  struct bt_sdp_record  *record;
  struct bt_sdp_att_rsp *rsp;
  struct net_buf        *rsp_buf;
  uint32_t               svc_rec_hdl;
  uint16_t               max_att_len, res, att_list_len;
  uint8_t                num_filters, cont_state_size, next_att = 0U;

  if (buf->len < 6) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  svc_rec_hdl = net_buf_pull_be32(buf);
  max_att_len = net_buf_pull_be16(buf);

  /* Set up the filters */
  res = get_att_search_list(buf, filter, &num_filters);
  if (res) {
    /* Error in parsing */
    return res;
  }

  if (buf->len < 1) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  cont_state_size = net_buf_pull_u8(buf);

  /* We only send out 1 byte continuation state in responses,
   * so expect only 1 byte in requests
   */
  if (cont_state_size) {
    if (cont_state_size != SDP_SA_CONT_STATE_SIZE) {
      BT_WARN("Invalid cont state size %u", cont_state_size);
      return BT_SDP_INVALID_CSTATE;
    }

    if (buf->len < cont_state_size) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }

    state.last_att = net_buf_pull_u8(buf) + 1;
    next_att       = state.last_att;
  }

  BT_DBG("svc_rec_hdl %u, max_att_len 0x%04x, cont_state %u", svc_rec_hdl, max_att_len, next_att);

  /* Find the service */
  record = bt_sdp_foreach_svc(find_handle, &svc_rec_hdl);

  if (!record) {
    BT_WARN("Handle %u not found", svc_rec_hdl);
    return BT_SDP_INVALID_RECORD_HANDLE;
  }

  /* For partial responses, restore the search state */
  if (cont_state_size) {
    state.current_svc = record->index;
  }

  rsp_buf = bt_sdp_create_pdu();
  rsp     = net_buf_add(rsp_buf, sizeof(*rsp));

  /* cont_state_size should include 1 byte header */
  att_list_len = create_attr_list(sdp, record, filter, num_filters, max_att_len, SDP_SA_CONT_STATE_SIZE + 1, next_att, &state, rsp_buf);

  if (!att_list_len) {
    /* For empty responses, add an empty data element sequence */
    net_buf_add_u8(rsp_buf, BT_SDP_SEQ8);
    net_buf_add_u8(rsp_buf, 0);
    att_list_len = 2U;
  }

  /* Add continuation state */
  if (state.pkt_full) {
    BT_DBG("Packet full, state.last_att %u", state.last_att);
    net_buf_add_u8(rsp_buf, 1);
    net_buf_add_u8(rsp_buf, state.last_att);
  } else {
    net_buf_add_u8(rsp_buf, 0);
  }

  rsp->att_list_len = sys_cpu_to_be16(att_list_len);

  BT_DBG("Sending response, len %u", rsp_buf->len);
  bt_sdp_send(&sdp->chan.chan, rsp_buf, BT_SDP_SVC_ATTR_RSP, tid);

  return 0;
}

/* @brief Handler for Service Search Attribute Request
 *
 *  Parses, processes and responds to a Service Search Attribute Request
 *
 *  @param sdp Pointer to the SDP structure
 *  @param buf Request buffer
 *  @param tid Transaction ID
 *
 *  @return 0 for success, or relevant error code
 */
static uint16_t sdp_svc_search_att_req(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid) {
  uint32_t                     filter[MAX_NUM_ATT_ID_FILTER];
  struct bt_sdp_record        *matching_recs[BT_SDP_MAX_SERVICES];
  struct search_state          state = {.att_list_size = 0, .current_svc = SDP_INVALID, .last_att = SDP_INVALID, .pkt_full = false};
  struct net_buf              *rsp_buf, *rsp_buf_cpy;
  struct bt_sdp_record        *record;
  struct bt_sdp_att_rsp       *rsp;
  struct bt_sdp_data_elem_seq *seq = NULL;
  uint16_t                     max_att_len, res, att_list_len         = 0U;
  uint8_t                      num_filters, cont_state_size, next_svc = 0U, next_att = 0U;
  bool                         dry_run = false;

  res = find_services(buf, matching_recs);
  if (res) {
    return res;
  }

  if (buf->len < 2) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  max_att_len = net_buf_pull_be16(buf);

  /* Set up the filters */
  res = get_att_search_list(buf, filter, &num_filters);

  if (res) {
    /* Error in parsing */
    return res;
  }

  if (buf->len < 1) {
    BT_WARN("Malformed packet");
    return BT_SDP_INVALID_SYNTAX;
  }

  cont_state_size = net_buf_pull_u8(buf);

  /* We only send out 2 bytes continuation state in responses,
   * so expect only 2 bytes in requests
   */
  if (cont_state_size) {
    if (cont_state_size != SDP_SSA_CONT_STATE_SIZE) {
      BT_WARN("Invalid cont state size %u", cont_state_size);
      return BT_SDP_INVALID_CSTATE;
    }

    if (buf->len < cont_state_size) {
      BT_WARN("Malformed packet");
      return BT_SDP_INVALID_SYNTAX;
    }

    state.current_svc = net_buf_pull_u8(buf);
    state.last_att    = net_buf_pull_u8(buf) + 1;
    next_svc          = state.current_svc;
    next_att          = state.last_att;
  }

  BT_DBG("max_att_len 0x%04x, state.current_svc %u, state.last_att %u", max_att_len, state.current_svc, state.last_att);

  rsp_buf = bt_sdp_create_pdu();

  rsp = net_buf_add(rsp_buf, sizeof(*rsp));

  /* Add headers only if this is not a partial response */
  if (!cont_state_size) {
    seq       = net_buf_add(rsp_buf, sizeof(*seq));
    seq->type = BT_SDP_SEQ16;
    seq->size = 0U;

    /* 3 bytes for Outer Data Element Sequence declaration */
    att_list_len = 3U;
  }

  rsp_buf_cpy = rsp_buf;

  for (; next_svc < num_services; next_svc++) {
    record = matching_recs[next_svc];

    if (!record) {
      continue;
    }

    att_list_len += create_attr_list(sdp, record, filter, num_filters, max_att_len, SDP_SSA_CONT_STATE_SIZE + 1, next_att, &state, rsp_buf_cpy);

    /* Check if packet is full and not dry run */
    if (state.pkt_full && !dry_run) {
      BT_DBG("Packet full, state.last_att %u", state.last_att);
      dry_run = true;

      /* Add continuation state */
      net_buf_add_u8(rsp_buf, 2);
      net_buf_add_u8(rsp_buf, state.current_svc);
      net_buf_add_u8(rsp_buf, state.last_att);

      /* Break if it's not a partial response, else dry-run
       * Dry run: Look for other services that match
       */
      if (cont_state_size) {
        break;
      }

      rsp_buf_cpy = NULL;
    }

    next_att = 0U;
  }

  if (!dry_run) {
    if (!att_list_len) {
      /* For empty responses, add an empty data elem seq */
      net_buf_add_u8(rsp_buf, BT_SDP_SEQ8);
      net_buf_add_u8(rsp_buf, 0);
      att_list_len = 2U;
    }
    /* Search exhausted */
    net_buf_add_u8(rsp_buf, 0);
  }

  rsp->att_list_len = sys_cpu_to_be16(att_list_len);
  if (seq) {
    seq->size = sys_cpu_to_be16(state.att_list_size);
  }

  BT_DBG("Sending response, len %u", rsp_buf->len);
  bt_sdp_send(&sdp->chan.chan, rsp_buf, BT_SDP_SVC_SEARCH_ATTR_RSP, tid);

  return 0;
}

static const struct {
  uint8_t op_code;
  uint16_t (*func)(struct bt_sdp *sdp, struct net_buf *buf, uint16_t tid);
} handlers[] = {
    {     BT_SDP_SVC_SEARCH_REQ,     sdp_svc_search_req},
    {       BT_SDP_SVC_ATTR_REQ,        sdp_svc_att_req},
    {BT_SDP_SVC_SEARCH_ATTR_REQ, sdp_svc_search_att_req},
};

/* @brief Callback for SDP data receive
 *
 *  Gets called when an SDP PDU is received. Calls the corresponding handler
 *  based on the op code of the PDU.
 *
 *  @param chan L2CAP channel
 *  @param buf Received PDU
 *
 *  @return None
 */
static int bt_sdp_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_l2cap_br_chan *ch  = CONTAINER_OF(chan, struct bt_l2cap_br_chan, chan);
  struct bt_sdp           *sdp = CONTAINER_OF(ch, struct bt_sdp, chan);
  struct bt_sdp_hdr       *hdr;
  uint16_t                 err = BT_SDP_INVALID_SYNTAX;
  size_t                   i;

  BT_DBG("chan %p, ch %p, cid 0x%04x", chan, ch, ch->tx.cid);

  BT_ASSERT(sdp);

  if (buf->len < sizeof(*hdr)) {
    BT_ERR("Too small SDP PDU received");
    return 0;
  }

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  BT_DBG("Received SDP code 0x%02x len %u", hdr->op_code, buf->len);

  if (sys_cpu_to_be16(hdr->param_len) != buf->len) {
    err = BT_SDP_INVALID_PDU_SIZE;
  } else {
    for (i = 0; i < ARRAY_SIZE(handlers); i++) {
      if (hdr->op_code != handlers[i].op_code) {
        continue;
      }

      err = handlers[i].func(sdp, buf, hdr->tid);
      break;
    }
  }

  if (err) {
    BT_WARN("SDP error 0x%02x", err);
    send_err_rsp(chan, err, hdr->tid);
  }

  return 0;
}

/* @brief Callback for SDP connection accept
 *
 *  Gets called when an incoming SDP connection needs to be authorized.
 *  Registers the L2CAP callbacks and allocates an SDP context to the connection
 *
 *  @param conn BT connection object
 *  @param chan L2CAP channel structure (to be returned)
 *
 *  @return 0 for success, or relevant error code
 */
static int bt_sdp_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) {
  static const struct bt_l2cap_chan_ops ops = {
      .connected    = bt_sdp_connected,
      .disconnected = bt_sdp_disconnected,
      .recv         = bt_sdp_recv,
  };
  int i;

  BT_DBG("conn %p", conn);

  for (i = 0; i < ARRAY_SIZE(bt_sdp_pool); i++) {
    struct bt_sdp *sdp = &bt_sdp_pool[i];

    if (sdp->chan.chan.conn) {
      continue;
    }

    sdp->chan.chan.ops = &ops;
    sdp->chan.rx.mtu   = SDP_MTU;

    *chan = &sdp->chan.chan;

    return 0;
  }

  BT_ERR("No available SDP context for conn %p", conn);

  return -ENOMEM;
}

void bt_sdp_init(void) {
#if defined(BFLB_DYNAMIC_ALLOC_MEM)
  net_buf_init(&sdp_pool, CONFIG_BT_MAX_CONN, BT_L2CAP_BUF_SIZE(SDP_MTU), NULL);
#endif
  static struct bt_l2cap_server server = {
      .psm       = SDP_PSM,
      .accept    = bt_sdp_accept,
      .sec_level = BT_SECURITY_L0,
  };
  int res;

  res = bt_l2cap_br_server_register(&server);
  if (res) {
    BT_ERR("L2CAP server registration failed with error %d", res);
  }
}

int bt_sdp_register_service(struct bt_sdp_record *service) {
  uint32_t handle = SDP_SERVICE_HANDLE_BASE;

  if (!service) {
    BT_ERR("No service record specified");
    return 0;
  }

  if (num_services == BT_SDP_MAX_SERVICES) {
    BT_ERR("Reached max allowed registrations");
    return -ENOMEM;
  }

  if (db) {
    handle = db->handle + 1;
  }

  service->next                               = db;
  service->index                              = num_services++;
  service->handle                             = handle;
  *((uint32_t *)(service->attrs[0].val.data)) = handle;
  db                                          = service;

  BT_DBG("Service registered at %u", handle);

  return 0;
}

#define GET_PARAM(__node) CONTAINER_OF(__node, struct bt_sdp_discover_params, _node)

/* ServiceSearchAttribute PDU, ref to BT Core 4.2, Vol 3, part B, 4.7.1 */
static int sdp_client_ssa_search(struct bt_sdp_client *session) {
  const struct bt_sdp_discover_params *param;
  struct bt_sdp_hdr                   *hdr;
  struct net_buf                      *buf;

  /*
   * Select proper user params, if session->param is invalid it means
   * getting new UUID from top of to be resolved params list. Otherwise
   * the context is in a middle of partial SDP PDU responses and cached
   * value from context can be used.
   */
  if (!session->param) {
    param = GET_PARAM(sys_slist_peek_head(&session->reqs));
  } else {
    param = session->param;
  }

  if (!param) {
    BT_WARN("No UUIDs to be resolved on remote");
    return -EINVAL;
  }

  buf = bt_l2cap_create_pdu(&sdp_pool, 0);

  hdr = net_buf_add(buf, sizeof(*hdr));

  hdr->op_code = BT_SDP_SVC_SEARCH_ATTR_REQ;
  /* BT_SDP_SEQ8 means length of sequence is on additional next byte */
  net_buf_add_u8(buf, BT_SDP_SEQ8);

  switch (param->uuid->type) {
  case BT_UUID_TYPE_16:
    /* Seq length */
    net_buf_add_u8(buf, 0x03);
    /* Seq type */
    net_buf_add_u8(buf, BT_SDP_UUID16);
    /* Seq value */
    net_buf_add_be16(buf, BT_UUID_16(param->uuid)->val);
    break;
  case BT_UUID_TYPE_32:
    net_buf_add_u8(buf, 0x05);
    net_buf_add_u8(buf, BT_SDP_UUID32);
    net_buf_add_be32(buf, BT_UUID_32(param->uuid)->val);
    break;
  case BT_UUID_TYPE_128:
    net_buf_add_u8(buf, 0x11);
    net_buf_add_u8(buf, BT_SDP_UUID128);
    net_buf_add_mem(buf, BT_UUID_128(param->uuid)->val, ARRAY_SIZE(BT_UUID_128(param->uuid)->val));
    break;
  default:
    BT_ERR("Unknown UUID type %u", param->uuid->type);
    return -EINVAL;
  }

  /* Set attribute max bytes count to be returned from server */
  net_buf_add_be16(buf, BT_SDP_MAX_ATTR_LEN);
  /*
   * Sequence definition where data is sequence of elements and where
   * additional next byte points the size of elements within
   */
  net_buf_add_u8(buf, BT_SDP_SEQ8);
  net_buf_add_u8(buf, 0x05);
  /* Data element definition for two following 16bits range elements */
  net_buf_add_u8(buf, BT_SDP_UINT32);
  /* Get all attributes. It enables filter out wanted only attributes */
  net_buf_add_be16(buf, 0x0000);
  net_buf_add_be16(buf, 0xffff);

  /*
   * Update and validate PDU ContinuationState. Initial SSA Request has
   * zero length continuation state since no interaction has place with
   * server so far, otherwise use the original state taken from remote's
   * last response PDU that is cached by SDP client context.
   */
  if (session->cstate.length == 0U) {
    net_buf_add_u8(buf, 0x00);
  } else {
    net_buf_add_u8(buf, session->cstate.length);
    net_buf_add_mem(buf, session->cstate.data, session->cstate.length);
  }

  /* set overall PDU length */
  hdr->param_len = sys_cpu_to_be16(buf->len - sizeof(*hdr));

  /* Update context param to the one being resolving now */
  session->param = param;
  session->tid++;
  hdr->tid = sys_cpu_to_be16(session->tid);

  return bt_l2cap_chan_send(&session->chan.chan, buf);
}

static void sdp_client_params_iterator(struct bt_sdp_client *session) {
  struct bt_l2cap_chan          *chan = &session->chan.chan;
  struct bt_sdp_discover_params *param, *tmp;

  SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&session->reqs, param, tmp, _node) {
    if (param != session->param) {
      continue;
    }

    BT_DBG("");

    /* Remove already checked UUID node */
    sys_slist_remove(&session->reqs, NULL, ¶m->_node);
    /* Invalidate cached param in context */
    session->param = NULL;
    /* Reset continuation state in current context */
    (void)memset(&session->cstate, 0, sizeof(session->cstate));

    /* Check if there's valid next UUID */
    if (!sys_slist_is_empty(&session->reqs)) {
      sdp_client_ssa_search(session);
      return;
    }

    /* No UUID items, disconnect channel */
    bt_l2cap_chan_disconnect(chan);
    break;
  }
}

static uint16_t sdp_client_get_total(struct bt_sdp_client *session, struct net_buf *buf, uint16_t *total) {
  uint16_t pulled;
  uint8_t  seq;

  /*
   * Pull value of total octets of all attributes available to be
   * collected when response gets completed for given UUID. Such info can
   * be get from the very first response frame after initial SSA request
   * was sent. For subsequent calls related to the same SSA request input
   * buf and in/out function parameters stays neutral.
   */
  if (session->cstate.length == 0U) {
    seq    = net_buf_pull_u8(buf);
    pulled = 1U;
    switch (seq) {
    case BT_SDP_SEQ8:
      *total = net_buf_pull_u8(buf);
      pulled += 1U;
      break;
    case BT_SDP_SEQ16:
      *total = net_buf_pull_be16(buf);
      pulled += 2U;
      break;
    default:
      BT_WARN("Sequence type 0x%02x not handled", seq);
      *total = 0U;
      break;
    }

    BT_DBG("Total %u octets of all attributes", *total);
  } else {
    pulled = 0U;
    *total = 0U;
  }

  return pulled;
}

static uint16_t get_record_len(struct net_buf *buf) {
  uint16_t len;
  uint8_t  seq;

  seq = net_buf_pull_u8(buf);

  switch (seq) {
  case BT_SDP_SEQ8:
    len = net_buf_pull_u8(buf);
    break;
  case BT_SDP_SEQ16:
    len = net_buf_pull_be16(buf);
    break;
  default:
    BT_WARN("Sequence type 0x%02x not handled", seq);
    len = 0U;
    break;
  }

  BT_DBG("Record len %u", len);

  return len;
}

enum uuid_state {
  UUID_NOT_RESOLVED,
  UUID_RESOLVED,
};

static void sdp_client_notify_result(struct bt_sdp_client *session, enum uuid_state state) {
  struct bt_conn             *conn = session->chan.chan.conn;
  struct bt_sdp_client_result result;
  uint16_t                    rec_len;
  uint8_t                     user_ret;

  result.uuid = session->param->uuid;

  if (state == UUID_NOT_RESOLVED) {
    result.resp_buf         = NULL;
    result.next_record_hint = false;
    session->param->func(conn, &result);
    return;
  }

  while (session->rec_buf->len) {
    struct net_buf_simple_state buf_state;

    rec_len = get_record_len(session->rec_buf);
    /* tell the user about multi record resolution */
    if (session->rec_buf->len > rec_len) {
      result.next_record_hint = true;
    } else {
      result.next_record_hint = false;
    }

    /* save the original session buffer */
    net_buf_simple_save(&session->rec_buf->b, &buf_state);
    /* initialize internal result buffer instead of memcpy */
    result.resp_buf = session->rec_buf;
    /*
     * Set user internal result buffer length as same as record
     * length to fake user. User will see the individual record
     * length as rec_len insted of whole session rec_buf length.
     */
    result.resp_buf->len = rec_len;

    user_ret = session->param->func(conn, &result);

    /* restore original session buffer */
    net_buf_simple_restore(&session->rec_buf->b, &buf_state);
    /*
     * sync session buffer data length with next record chunk not
     * send to user so far
     */
    net_buf_pull(session->rec_buf, rec_len);
    if (user_ret == BT_SDP_DISCOVER_UUID_STOP) {
      break;
    }
  }
}

static int sdp_client_receive(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_sdp_client     *session = SDP_CLIENT_CHAN(chan);
  struct bt_sdp_hdr        *hdr;
  struct bt_sdp_pdu_cstate *cstate;
  uint16_t                  len, tid, frame_len;
  uint16_t                  total;

  BT_DBG("session %p buf %p", session, buf);

  if (buf->len < sizeof(*hdr)) {
    BT_ERR("Too small SDP PDU");
    return 0;
  }

  hdr = net_buf_pull_mem(buf, sizeof(*hdr));
  if (hdr->op_code == BT_SDP_ERROR_RSP) {
    BT_INFO("Error SDP PDU response");
    return 0;
  }

  len = sys_be16_to_cpu(hdr->param_len);
  tid = sys_be16_to_cpu(hdr->tid);

  BT_DBG("SDP PDU tid %u len %u", tid, len);

  if (buf->len != len) {
    BT_ERR("SDP PDU length mismatch (%u != %u)", buf->len, len);
    return 0;
  }

  if (tid != session->tid) {
    BT_ERR("Mismatch transaction ID value in SDP PDU");
    return 0;
  }

  switch (hdr->op_code) {
  case BT_SDP_SVC_SEARCH_ATTR_RSP:
    /* Get number of attributes in this frame. */
    frame_len = net_buf_pull_be16(buf);
    /* Check valid buf len for attribute list and cont state */
    if (buf->len < frame_len + SDP_CONT_STATE_LEN_SIZE) {
      BT_ERR("Invalid frame payload length");
      return 0;
    }
    /* Check valid range of attributes length */
    if (frame_len < 2) {
      BT_ERR("Invalid attributes data length");
      return 0;
    }

    /* Get PDU continuation state */
    cstate = (struct bt_sdp_pdu_cstate *)(buf->data + frame_len);

    if (cstate->length > BT_SDP_MAX_PDU_CSTATE_LEN) {
      BT_ERR("Invalid SDP PDU Continuation State length %u", cstate->length);
      return 0;
    }

    if ((frame_len + SDP_CONT_STATE_LEN_SIZE + cstate->length) > buf->len) {
      BT_ERR("Invalid frame payload length");
      return 0;
    }

    /*
     * No record found for given UUID. The check catches case when
     * current response frame has Continuation State shortest and
     * valid and this is the first response frame as well.
     */
    if (frame_len == 2U && cstate->length == 0U && session->cstate.length == 0U) {
      BT_DBG("record for UUID 0x%s not found", bt_uuid_str(session->param->uuid));
      /* Call user UUID handler */
      sdp_client_notify_result(session, UUID_NOT_RESOLVED);
      net_buf_pull(buf, frame_len + sizeof(cstate->length));
      goto iterate;
    }

    /* Get total value of all attributes to be collected */
    frame_len -= sdp_client_get_total(session, buf, &total);

    if (total > net_buf_tailroom(session->rec_buf)) {
      BT_WARN("Not enough room for getting records data");
      goto iterate;
    }

    net_buf_add_mem(session->rec_buf, buf->data, frame_len);
    net_buf_pull(buf, frame_len);

    /*
     * check if current response says there's next portion to be
     * fetched
     */
    if (cstate->length) {
      /* Cache original Continuation State in context */
      memcpy(&session->cstate, cstate, sizeof(struct bt_sdp_pdu_cstate));

      net_buf_pull(buf, cstate->length + sizeof(cstate->length));

      /* Request for next portion of attributes data */
      sdp_client_ssa_search(session);
      break;
    }

    net_buf_pull(buf, sizeof(cstate->length));

    BT_DBG("UUID 0x%s resolved", bt_uuid_str(session->param->uuid));
    sdp_client_notify_result(session, UUID_RESOLVED);
  iterate:
    /* Get next UUID and start resolving it */
    sdp_client_params_iterator(session);
    break;
  default:
    BT_DBG("PDU 0x%0x response not handled", hdr->op_code);
    break;
  }

  return 0;
}

static int sdp_client_chan_connect(struct bt_sdp_client *session) { return bt_l2cap_br_chan_connect(session->chan.chan.conn, &session->chan.chan, SDP_PSM); }

static struct net_buf *sdp_client_alloc_buf(struct bt_l2cap_chan *chan) {
  struct bt_sdp_client *session = SDP_CLIENT_CHAN(chan);
  struct net_buf       *buf;

  BT_DBG("session %p chan %p", session, chan);

  session->param = GET_PARAM(sys_slist_peek_head(&session->reqs));

  buf = net_buf_alloc(session->param->pool, K_FOREVER);
  __ASSERT_NO_MSG(buf);

  return buf;
}

static void sdp_client_connected(struct bt_l2cap_chan *chan) {
  struct bt_sdp_client *session = SDP_CLIENT_CHAN(chan);

  BT_DBG("session %p chan %p connected", session, chan);

  session->rec_buf = chan->ops->alloc_buf(chan);

  sdp_client_ssa_search(session);
}

static void sdp_client_disconnected(struct bt_l2cap_chan *chan) {
  struct bt_sdp_client *session = SDP_CLIENT_CHAN(chan);

  BT_DBG("session %p chan %p disconnected", session, chan);

  net_buf_unref(session->rec_buf);

  /*
   * Reset session excluding L2CAP channel member. Let's the channel
   * resets autonomous.
   */
  (void)memset(&session->reqs, 0, sizeof(*session) - sizeof(session->chan));
}

static const struct bt_l2cap_chan_ops sdp_client_chan_ops = {
    .connected    = sdp_client_connected,
    .disconnected = sdp_client_disconnected,
    .recv         = sdp_client_receive,
    .alloc_buf    = sdp_client_alloc_buf,
};

static struct bt_sdp_client *sdp_client_new_session(struct bt_conn *conn) {
  int i;

  for (i = 0; i < ARRAY_SIZE(bt_sdp_client_pool); i++) {
    struct bt_sdp_client *session = &bt_sdp_client_pool[i];
    int                   err;

    if (session->chan.chan.conn) {
      continue;
    }

    sys_slist_init(&session->reqs);

    session->chan.chan.ops  = &sdp_client_chan_ops;
    session->chan.chan.conn = conn;
    session->chan.rx.mtu    = SDP_CLIENT_MTU;

    err = sdp_client_chan_connect(session);
    if (err) {
      (void)memset(session, 0, sizeof(*session));
      BT_ERR("Cannot connect %d", err);
      return NULL;
    }

    return session;
  }

  BT_ERR("No available SDP client context");

  return NULL;
}

static struct bt_sdp_client *sdp_client_get_session(struct bt_conn *conn) {
  int i;

  for (i = 0; i < ARRAY_SIZE(bt_sdp_client_pool); i++) {
    if (bt_sdp_client_pool[i].chan.chan.conn == conn) {
      return &bt_sdp_client_pool[i];
    }
  }

  /*
   * Try to allocate session context since not found in pool and attempt
   * connect to remote SDP endpoint.
   */
  return sdp_client_new_session(conn);
}

int bt_sdp_discover(struct bt_conn *conn, const struct bt_sdp_discover_params *params) {
  struct bt_sdp_client *session;

  if (!params || !params->uuid || !params->func || !params->pool) {
    BT_WARN("Invalid user params");
    return -EINVAL;
  }

  session = sdp_client_get_session(conn);
  if (!session) {
    return -ENOMEM;
  }

  sys_slist_append(&session->reqs, (sys_snode_t *)¶ms->_node);

  return 0;
}

/* Helper getting length of data determined by DTD for integers */
static inline ssize_t sdp_get_int_len(const uint8_t *data, size_t len) {
  BT_ASSERT(data);

  switch (data[0]) {
  case BT_SDP_DATA_NIL:
    return 1;
  case BT_SDP_BOOL:
  case BT_SDP_INT8:
  case BT_SDP_UINT8:
    if (len < 2) {
      break;
    }

    return 2;
  case BT_SDP_INT16:
  case BT_SDP_UINT16:
    if (len < 3) {
      break;
    }

    return 3;
  case BT_SDP_INT32:
  case BT_SDP_UINT32:
    if (len < 5) {
      break;
    }

    return 5;
  case BT_SDP_INT64:
  case BT_SDP_UINT64:
    if (len < 9) {
      break;
    }

    return 9;
  case BT_SDP_INT128:
  case BT_SDP_UINT128:
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x", data[0]);
    return -EINVAL;
  }

  BT_ERR("Too short buffer length %zu", len);
  return -EMSGSIZE;
}

/* Helper getting length of data determined by DTD for UUID */
static inline ssize_t sdp_get_uuid_len(const uint8_t *data, size_t len) {
  BT_ASSERT(data);

  switch (data[0]) {
  case BT_SDP_UUID16:
    if (len < 3) {
      break;
    }

    return 3;
  case BT_SDP_UUID32:
    if (len < 5) {
      break;
    }

    return 5;
  case BT_SDP_UUID128:
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x", data[0]);
    return -EINVAL;
  }

  BT_ERR("Too short buffer length %zu", len);
  return -EMSGSIZE;
}

/* Helper getting length of data determined by DTD for strings */
static inline ssize_t sdp_get_str_len(const uint8_t *data, size_t len) {
  const uint8_t *pnext;

  BT_ASSERT(data);

  /* validate len for pnext safe use to read next 8bit value */
  if (len < 2) {
    goto err;
  }

  pnext = data + sizeof(uint8_t);

  switch (data[0]) {
  case BT_SDP_TEXT_STR8:
  case BT_SDP_URL_STR8:
    if (len < (2 + pnext[0])) {
      break;
    }

    return 2 + pnext[0];
  case BT_SDP_TEXT_STR16:
  case BT_SDP_URL_STR16:
    /* validate len for pnext safe use to read 16bit value */
    if (len < 3) {
      break;
    }

    if (len < (3 + sys_get_be16(pnext))) {
      break;
    }

    return 3 + sys_get_be16(pnext);
  case BT_SDP_TEXT_STR32:
  case BT_SDP_URL_STR32:
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x", data[0]);
    return -EINVAL;
  }
err:
  BT_ERR("Too short buffer length %zu", len);
  return -EMSGSIZE;
}

/* Helper getting length of data determined by DTD for sequences */
static inline ssize_t sdp_get_seq_len(const uint8_t *data, size_t len) {
  const uint8_t *pnext;

  BT_ASSERT(data);

  /* validate len for pnext safe use to read 8bit bit value */
  if (len < 2) {
    goto err;
  }

  pnext = data + sizeof(uint8_t);

  switch (data[0]) {
  case BT_SDP_SEQ8:
  case BT_SDP_ALT8:
    if (len < (2 + pnext[0])) {
      break;
    }

    return 2 + pnext[0];
  case BT_SDP_SEQ16:
  case BT_SDP_ALT16:
    /* validate len for pnext safe use to read 16bit value */
    if (len < 3) {
      break;
    }

    if (len < (3 + sys_get_be16(pnext))) {
      break;
    }

    return 3 + sys_get_be16(pnext);
  case BT_SDP_SEQ32:
  case BT_SDP_ALT32:
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x", data[0]);
    return -EINVAL;
  }
err:
  BT_ERR("Too short buffer length %zu", len);
  return -EMSGSIZE;
}

/* Helper getting length of attribute value data */
static ssize_t sdp_get_attr_value_len(const uint8_t *data, size_t len) {
  BT_ASSERT(data);

  BT_DBG("Attr val DTD 0x%02x", data[0]);

  switch (data[0]) {
  case BT_SDP_DATA_NIL:
  case BT_SDP_BOOL:
  case BT_SDP_UINT8:
  case BT_SDP_UINT16:
  case BT_SDP_UINT32:
  case BT_SDP_UINT64:
  case BT_SDP_UINT128:
  case BT_SDP_INT8:
  case BT_SDP_INT16:
  case BT_SDP_INT32:
  case BT_SDP_INT64:
  case BT_SDP_INT128:
    return sdp_get_int_len(data, len);
  case BT_SDP_UUID16:
  case BT_SDP_UUID32:
  case BT_SDP_UUID128:
    return sdp_get_uuid_len(data, len);
  case BT_SDP_TEXT_STR8:
  case BT_SDP_TEXT_STR16:
  case BT_SDP_TEXT_STR32:
  case BT_SDP_URL_STR8:
  case BT_SDP_URL_STR16:
  case BT_SDP_URL_STR32:
    return sdp_get_str_len(data, len);
  case BT_SDP_SEQ8:
  case BT_SDP_SEQ16:
  case BT_SDP_SEQ32:
  case BT_SDP_ALT8:
  case BT_SDP_ALT16:
  case BT_SDP_ALT32:
    return sdp_get_seq_len(data, len);
  default:
    BT_ERR("Unknown DTD 0x%02x", data[0]);
    return -EINVAL;
  }
}

/* Type holding UUID item and related to it specific information. */
struct bt_sdp_uuid_desc {
  union {
    struct bt_uuid    uuid;
    struct bt_uuid_16 uuid16;
    struct bt_uuid_32 uuid32;
  };
  uint16_t attr_id;
  uint8_t *params;
  uint16_t params_len;
};

/* Generic attribute item collector. */
struct bt_sdp_attr_item {
  /*  Attribute identifier. */
  uint16_t attr_id;
  /*  Address of beginning attribute value taken from original buffer
   *  holding response from server.
   */
  uint8_t *val;
  /*  Says about the length of attribute value. */
  uint16_t len;
};

static int bt_sdp_get_attr(const struct net_buf *buf, struct bt_sdp_attr_item *attr, uint16_t attr_id) {
  uint8_t *data;
  uint16_t id;

  data = buf->data;
  while (data - buf->data < buf->len) {
    ssize_t dlen;

    /* data need to point to attribute id descriptor field (DTD)*/
    if (data[0] != BT_SDP_UINT16) {
      BT_ERR("Invalid descriptor 0x%02x", data[0]);
      return -EINVAL;
    }

    data += sizeof(uint8_t);
    id = sys_get_be16(data);
    BT_DBG("Attribute ID 0x%04x", id);
    data += sizeof(uint16_t);

    dlen = sdp_get_attr_value_len(data, buf->len - (data - buf->data));
    if (dlen < 0) {
      BT_ERR("Invalid attribute value data");
      return -EINVAL;
    }

    if (id == attr_id) {
      BT_DBG("Attribute ID 0x%04x Value found", id);
      /*
       * Initialize attribute value buffer data using selected
       * data slice from original buffer.
       */
      attr->val     = data;
      attr->len     = dlen;
      attr->attr_id = id;
      return 0;
    }

    data += dlen;
  }

  return -ENOENT;
}

/* reads SEQ item length, moves input buffer data reader forward */
static ssize_t sdp_get_seq_len_item(uint8_t **data, size_t len) {
  const uint8_t *pnext;

  BT_ASSERT(data);
  BT_ASSERT(*data);

  /* validate len for pnext safe use to read 8bit bit value */
  if (len < 2) {
    goto err;
  }

  pnext = *data + sizeof(uint8_t);

  switch (*data[0]) {
  case BT_SDP_SEQ8:
    if (len < (2 + pnext[0])) {
      break;
    }

    *data += 2;
    return pnext[0];
  case BT_SDP_SEQ16:
    /* validate len for pnext safe use to read 16bit value */
    if (len < 3) {
      break;
    }

    if (len < (3 + sys_get_be16(pnext))) {
      break;
    }

    *data += 3;
    return sys_get_be16(pnext);
  case BT_SDP_SEQ32:
    /* validate len for pnext safe use to read 32bit value */
    if (len < 5) {
      break;
    }

    if (len < (5 + sys_get_be32(pnext))) {
      break;
    }

    *data += 5;
    return sys_get_be32(pnext);
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x", *data[0]);
    return -EINVAL;
  }
err:
  BT_ERR("Too short buffer length %zu", len);
  return -EMSGSIZE;
}

static int sdp_get_uuid_data(const struct bt_sdp_attr_item *attr, struct bt_sdp_uuid_desc *pd, uint16_t proto_profile) {
  /* get start address of attribute value */
  uint8_t *p = attr->val;
  ssize_t  slen;

  BT_ASSERT(p);

  /* Attribute value is a SEQ, get length of parent SEQ frame */
  slen = sdp_get_seq_len_item(&p, attr->len);
  if (slen < 0) {
    return slen;
  }

  /* start reading stacked UUIDs in analyzed sequences tree */
  while (p - attr->val < attr->len) {
    size_t to_end, left = 0;

    /* to_end tells how far to the end of input buffer */
    to_end = attr->len - (p - attr->val);
    /* how long is current UUID's item data associated to */
    slen = sdp_get_seq_len_item(&p, to_end);
    if (slen < 0) {
      return slen;
    }

    /* left tells how far is to the end of current UUID */
    left = slen;

    /* check if at least DTD + UUID16 can be read safely */
    if (left < 3) {
      return -EMSGSIZE;
    }

    /* check DTD and get stacked UUID value */
    switch (p[0]) {
    case BT_SDP_UUID16:
      memcpy(&pd->uuid16, BT_UUID_DECLARE_16(sys_get_be16(++p)), sizeof(struct bt_uuid_16));
      p += sizeof(uint16_t);
      left -= sizeof(uint16_t);
      break;
    case BT_SDP_UUID32:
      /* check if valid UUID32 can be read safely */
      if (left < 5) {
        return -EMSGSIZE;
      }

      memcpy(&pd->uuid32, BT_UUID_DECLARE_32(sys_get_be32(++p)), sizeof(struct bt_uuid_32));
      p += sizeof(uint32_t);
      left -= sizeof(uint32_t);
      break;
    default:
      BT_ERR("Invalid/unhandled DTD 0x%02x\n", p[0]);
      return -EINVAL;
    }

    /* include last DTD in p[0] size itself updating left */
    left -= sizeof(p[0]);

    /*
     * Check if current UUID value matches input one given by user.
     * If found save it's location and length and return.
     */
    if ((proto_profile == BT_UUID_16(&pd->uuid)->val) || (proto_profile == BT_UUID_32(&pd->uuid)->val)) {
      pd->params     = p;
      pd->params_len = left;

      BT_DBG("UUID 0x%s found", bt_uuid_str(&pd->uuid));
      return 0;
    }

    /* skip left octets to point beginning of next UUID in tree */
    p += left;
  }

  BT_DBG("Value 0x%04x not found", proto_profile);
  return -ENOENT;
}

/*
 * Helper extracting specific parameters associated with UUID node given in
 * protocol descriptor list or profile descriptor list.
 */
static int sdp_get_param_item(struct bt_sdp_uuid_desc *pd_item, uint16_t *param) {
  const uint8_t *p       = pd_item->params;
  bool           len_err = false;

  BT_ASSERT(p);

  BT_DBG("Getting UUID's 0x%s params", bt_uuid_str(&pd_item->uuid));

  switch (p[0]) {
  case BT_SDP_UINT8:
    /* check if 8bits value can be read safely */
    if (pd_item->params_len < 2) {
      len_err = true;
      break;
    }
    *param = (++p)[0];
    p += sizeof(uint8_t);
    break;
  case BT_SDP_UINT16:
    /* check if 16bits value can be read safely */
    if (pd_item->params_len < 3) {
      len_err = true;
      break;
    }
    *param = sys_get_be16(++p);
    p += sizeof(uint16_t);
    break;
  case BT_SDP_UINT32:
    /* check if 32bits value can be read safely */
    if (pd_item->params_len < 5) {
      len_err = true;
      break;
    }
    *param = sys_get_be32(++p);
    p += sizeof(uint32_t);
    break;
  default:
    BT_ERR("Invalid/unhandled DTD 0x%02x\n", p[0]);
    return -EINVAL;
  }
  /*
   * Check if no more data than already read is associated with UUID. In
   * valid case after getting parameter we should reach data buf end.
   */
  if (p - pd_item->params != pd_item->params_len || len_err) {
    BT_DBG("Invalid param buffer length");
    return -EMSGSIZE;
  }

  return 0;
}

int bt_sdp_get_proto_param(const struct net_buf *buf, enum bt_sdp_proto proto, uint16_t *param) {
  struct bt_sdp_attr_item attr;
  struct bt_sdp_uuid_desc pd;
  int                     res;

  if (proto != BT_SDP_PROTO_RFCOMM && proto != BT_SDP_PROTO_L2CAP) {
    BT_ERR("Invalid protocol specifier");
    return -EINVAL;
  }

  res = bt_sdp_get_attr(buf, &attr, BT_SDP_ATTR_PROTO_DESC_LIST);
  if (res < 0) {
    BT_WARN("Attribute 0x%04x not found, err %d", BT_SDP_ATTR_PROTO_DESC_LIST, res);
    return res;
  }

  res = sdp_get_uuid_data(&attr, &pd, proto);
  if (res < 0) {
    BT_WARN("Protocol specifier 0x%04x not found, err %d", proto, res);
    return res;
  }

  return sdp_get_param_item(&pd, param);
}

int bt_sdp_get_profile_version(const struct net_buf *buf, uint16_t profile, uint16_t *version) {
  struct bt_sdp_attr_item attr;
  struct bt_sdp_uuid_desc pd;
  int                     res;

  res = bt_sdp_get_attr(buf, &attr, BT_SDP_ATTR_PROFILE_DESC_LIST);
  if (res < 0) {
    BT_WARN("Attribute 0x%04x not found, err %d", BT_SDP_ATTR_PROFILE_DESC_LIST, res);
    return res;
  }

  res = sdp_get_uuid_data(&attr, &pd, profile);
  if (res < 0) {
    BT_WARN("Profile 0x%04x not found, err %d", profile, res);
    return res;
  }

  return sdp_get_param_item(&pd, version);
}

int bt_sdp_get_features(const struct net_buf *buf, uint16_t *features) {
  struct bt_sdp_attr_item attr;
  const uint8_t          *p;
  int                     res;

  res = bt_sdp_get_attr(buf, &attr, BT_SDP_ATTR_SUPPORTED_FEATURES);
  if (res < 0) {
    BT_WARN("Attribute 0x%04x not found, err %d", BT_SDP_ATTR_SUPPORTED_FEATURES, res);
    return res;
  }

  p = attr.val;
  BT_ASSERT(p);

  if (p[0] != BT_SDP_UINT16) {
    BT_ERR("Invalid DTD 0x%02x", p[0]);
    return -EINVAL;
  }

  /* assert 16bit can be read safely */
  if (attr.len < 3) {
    BT_ERR("Data length too short %u", attr.len);
    return -EMSGSIZE;
  }

  *features = sys_get_be16(++p);
  p += sizeof(uint16_t);

  if (p - attr.val != attr.len) {
    BT_ERR("Invalid data length %u", attr.len);
    return -EMSGSIZE;
  }

  return 0;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/sdp_internal.h
================================================
/* sdp_internal.h - Service Discovery Protocol handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * The PDU identifiers of SDP packets between client and server
 */
#define BT_SDP_ERROR_RSP           0x01
#define BT_SDP_SVC_SEARCH_REQ      0x02
#define BT_SDP_SVC_SEARCH_RSP      0x03
#define BT_SDP_SVC_ATTR_REQ        0x04
#define BT_SDP_SVC_ATTR_RSP        0x05
#define BT_SDP_SVC_SEARCH_ATTR_REQ 0x06
#define BT_SDP_SVC_SEARCH_ATTR_RSP 0x07

/*
 * Some additions to support service registration.
 * These are outside the scope of the Bluetooth specification
 */
#define BT_SDP_SVC_REGISTER_REQ 0x75
#define BT_SDP_SVC_REGISTER_RSP 0x76
#define BT_SDP_SVC_UPDATE_REQ   0x77
#define BT_SDP_SVC_UPDATE_RSP   0x78
#define BT_SDP_SVC_REMOVE_REQ   0x79
#define BT_SDP_SVC_REMOVE_RSP   0x80

/*
 * SDP Error codes
 */
#define BT_SDP_INVALID_VERSION       0x0001
#define BT_SDP_INVALID_RECORD_HANDLE 0x0002
#define BT_SDP_INVALID_SYNTAX        0x0003
#define BT_SDP_INVALID_PDU_SIZE      0x0004
#define BT_SDP_INVALID_CSTATE        0x0005

#define BT_SDP_MAX_SERVICES 10

struct bt_sdp_data_elem_seq {
    uint8_t type;  /* Type: Will be data element sequence */
    uint16_t size; /* We only support 2 byte sizes for now */
} __packed;

struct bt_sdp_hdr {
    uint8_t op_code;
    uint16_t tid;
    uint16_t param_len;
} __packed;

struct bt_sdp_svc_rsp {
    uint16_t total_recs;
    uint16_t current_recs;
} __packed;

struct bt_sdp_att_rsp {
    uint16_t att_list_len;
} __packed;

/* Allowed attributes length in SSA Request PDU to be taken from server */
#define BT_SDP_MAX_ATTR_LEN 0xffff

/* Max allowed length of PDU Continuation State */
#define BT_SDP_MAX_PDU_CSTATE_LEN 16

/* Type mapping SDP PDU Continuation State */
struct bt_sdp_pdu_cstate {
    uint8_t length;
    uint8_t data[BT_SDP_MAX_PDU_CSTATE_LEN];
} __packed;

void bt_sdp_init(void);


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/settings.c
================================================
/*
 * Copyright (c) 2018 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_SETTINGS)
#define LOG_MODULE_NAME bt_settings
#include "log.h"

#include "gatt.h"
#include "hci_core.h"
#include "keys.h"
#include "settings.h"
#if defined(BFLB_BLE)
#include 
#if defined(CONFIG_BT_SETTINGS)
#include "easyflash.h"
#endif
#include "portable.h"
#include 
#endif

#if defined(CONFIG_BT_SETTINGS_USE_PRINTK)
void bt_settings_encode_key(char *path, size_t path_size, const char *subsys, bt_addr_le_t *addr, const char *key) {
  if (key) {
    snprintk(path, path_size, "bt/%s/%02x%02x%02x%02x%02x%02x%u/%s", subsys, addr->a.val[5], addr->a.val[4], addr->a.val[3], addr->a.val[2], addr->a.val[1], addr->a.val[0], addr->type, key);
  } else {
    snprintk(path, path_size, "bt/%s/%02x%02x%02x%02x%02x%02x%u", subsys, addr->a.val[5], addr->a.val[4], addr->a.val[3], addr->a.val[2], addr->a.val[1], addr->a.val[0], addr->type);
  }

  BT_DBG("Encoded path %s", log_strdup(path));
}
#else
void bt_settings_encode_key(char *path, size_t path_size, const char *subsys, bt_addr_le_t *addr, const char *key) {
  size_t len = 3;

  /* Skip if path_size is less than 3; strlen("bt/") */
  if (len < path_size) {
    /* Key format:
     *  "bt///", "/" is optional
     */
    strcpy(path, "bt/");
    strncpy(&path[len], subsys, path_size - len);
    len = strlen(path);
    if (len < path_size) {
      path[len] = '/';
      len++;
    }

    for (s8_t i = 5; i >= 0 && len < path_size; i--) {
      len += bin2hex(&addr->a.val[i], 1, &path[len], path_size - len);
    }

    if (len < path_size) {
      /* Type can be either BT_ADDR_LE_PUBLIC or
       * BT_ADDR_LE_RANDOM (value 0 or 1)
       */
      path[len] = '0' + addr->type;
      len++;
    }

    if (key && len < path_size) {
      path[len] = '/';
      len++;
      strncpy(&path[len], key, path_size - len);
      len += strlen(&path[len]);
    }

    if (len >= path_size) {
      /* Truncate string */
      path[path_size - 1] = '\0';
    }
  } else if (path_size > 0) {
    *path = '\0';
  }

  BT_DBG("Encoded path %s", log_strdup(path));
}
#endif

#if !defined(BFLB_BLE)
int bt_settings_decode_key(const char *key, bt_addr_le_t *addr) {
  if (settings_name_next(key, NULL) != 13) {
    return -EINVAL;
  }

  if (key[12] == '0') {
    addr->type = BT_ADDR_LE_PUBLIC;
  } else if (key[12] == '1') {
    addr->type = BT_ADDR_LE_RANDOM;
  } else {
    return -EINVAL;
  }

  for (u8_t i = 0; i < 6; i++) {
    hex2bin(&key[i * 2], 2, &addr->a.val[5 - i], 1);
  }

  BT_DBG("Decoded %s as %s", log_strdup(key), bt_addr_le_str(addr));

  return 0;
}

static int set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) {
  ssize_t     len;
  const char *next;

  if (!name) {
    BT_ERR("Insufficient number of arguments");
    return -ENOENT;
  }

  len = settings_name_next(name, &next);

  if (!strncmp(name, "id", len)) {
    /* Any previously provided identities supersede flash */
    if (atomic_test_bit(bt_dev.flags, BT_DEV_PRESET_ID)) {
      BT_WARN("Ignoring identities stored in flash");
      return 0;
    }

    len = read_cb(cb_arg, &bt_dev.id_addr, sizeof(bt_dev.id_addr));
    if (len < sizeof(bt_dev.id_addr[0])) {
      if (len < 0) {
        BT_ERR("Failed to read ID address from storage"
               " (err %zu)",
               len);
      } else {
        BT_ERR("Invalid length ID address in storage");
        BT_HEXDUMP_DBG(&bt_dev.id_addr, len, "data read");
      }
      (void)memset(bt_dev.id_addr, 0, sizeof(bt_dev.id_addr));
      bt_dev.id_count = 0U;
    } else {
      int i;

      bt_dev.id_count = len / sizeof(bt_dev.id_addr[0]);
      for (i = 0; i < bt_dev.id_count; i++) {
        BT_DBG("ID[%d] %s", i, bt_addr_le_str(&bt_dev.id_addr[i]));
      }
    }

    return 0;
  }

#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
  if (!strncmp(name, "name", len)) {
    len = read_cb(cb_arg, &bt_dev.name, sizeof(bt_dev.name) - 1);
    if (len < 0) {
      BT_ERR("Failed to read device name from storage"
             " (err %zu)",
             len);
    } else {
      bt_dev.name[len] = '\0';

      BT_DBG("Name set to %s", log_strdup(bt_dev.name));
    }
    return 0;
  }
#endif

#if defined(CONFIG_BT_PRIVACY)
  if (!strncmp(name, "irk", len)) {
    len = read_cb(cb_arg, bt_dev.irk, sizeof(bt_dev.irk));
    if (len < sizeof(bt_dev.irk[0])) {
      if (len < 0) {
        BT_ERR("Failed to read IRK from storage"
               " (err %zu)",
               len);
      } else {
        BT_ERR("Invalid length IRK in storage");
        (void)memset(bt_dev.irk, 0, sizeof(bt_dev.irk));
      }
    } else {
      int i, count;

      count = len / sizeof(bt_dev.irk[0]);
      for (i = 0; i < count; i++) {
        BT_DBG("IRK[%d] %s", i, bt_hex(bt_dev.irk[i], 16));
      }
    }

    return 0;
  }
#endif /* CONFIG_BT_PRIVACY */

  return -ENOENT;
}

#define ID_DATA_LEN(array) (bt_dev.id_count * sizeof(array[0]))

static void save_id(struct k_work *work) {
  int err;
  BT_INFO("Saving ID");
  err = settings_save_one("bt/id", &bt_dev.id_addr, ID_DATA_LEN(bt_dev.id_addr));
  if (err) {
    BT_ERR("Failed to save ID (err %d)", err);
  }

#if defined(CONFIG_BT_PRIVACY)
  err = settings_save_one("bt/irk", bt_dev.irk, ID_DATA_LEN(bt_dev.irk));
  if (err) {
    BT_ERR("Failed to save IRK (err %d)", err);
  }
#endif
}

K_WORK_DEFINE(save_id_work, save_id);
#endif //! BFLB_BLE
#if defined(BFLB_BLE)
#if defined(CONFIG_BT_SETTINGS)
bool ef_ready_flag = false;
int  bt_check_if_ef_ready() {
  int err = 0;

  if (!ef_ready_flag) {
    err = easyflash_init();
    if (!err)
      ef_ready_flag = true;
  }

  return err;
}

int bt_settings_set_bin(const char *key, const uint8_t *value, size_t length) {
  int err;

  err = bt_check_if_ef_ready();
  if (err)
    return err;

  err = ef_set_env_blob(key, value, length);

  return err;
}

int bt_settings_get_bin(const char *key, u8_t *value, size_t exp_len, size_t *real_len) {
  int    err;
  size_t rlen;

  err = bt_check_if_ef_ready();
  if (err)
    return err;

  rlen = ef_get_env_blob(key, value, exp_len, NULL);

  if (real_len)
    *real_len = rlen;

  return 0;
}

int settings_delete(const char *key) { return ef_del_env(key); }

int settings_save_one(const char *key, const u8_t *value, size_t length) { return bt_settings_set_bin(key, value, length); }
#endif // CONFIG_BT_SETTINGS
#endif

void bt_settings_save_id(void) {
#if defined(BFLB_BLE)
#if defined(CONFIG_BT_SETTINGS)
  if (bt_check_if_ef_ready())
    return;
  bt_settings_set_bin(NV_LOCAL_ID_ADDR, (const u8_t *)&bt_dev.id_addr[0], sizeof(bt_addr_le_t) * CONFIG_BT_ID_MAX);
#if defined(CONFIG_BT_PRIVACY)
  bt_settings_set_bin(NV_LOCAL_IRK, (const u8_t *)&bt_dev.irk[0], 16 * CONFIG_BT_ID_MAX);
#endif // CONFIG_BT_PRIVACY
#endif // CONFIG_BT_SETTINGS
#else
  k_work_submit(&save_id_work);
#endif
}

#if defined(BFLB_BLE)
#if defined(CONFIG_BT_SETTINGS)
void bt_settings_save_name(void) { bt_settings_set_bin(NV_LOCAL_NAME, (u8_t *)bt_dev.name, strlen(bt_dev.name) + 1); }

void bt_local_info_load(void) {
  if (bt_check_if_ef_ready())
    return;
#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
  bt_settings_get_bin(NV_LOCAL_NAME, (u8_t *)bt_dev.name, CONFIG_BT_DEVICE_NAME_MAX, NULL);
#endif
  bt_settings_get_bin(NV_LOCAL_ID_ADDR, (u8_t *)&bt_dev.id_addr[0], sizeof(bt_addr_le_t) * CONFIG_BT_ID_MAX, NULL);
#if defined(CONFIG_BT_PRIVACY)
  bt_settings_get_bin(NV_LOCAL_IRK, (u8_t *)&bt_dev.irk[0][0], 16 * CONFIG_BT_ID_MAX, NULL);
#endif
}
#endif // CONFIG_BT_SETTINGS
#endif

#if !defined(BFLB_BLE)
static int commit(void) {
  BT_DBG("");

#if defined(CONFIG_BT_DEVICE_NAME_DYNAMIC)
  if (bt_dev.name[0] == '\0') {
    bt_set_name(CONFIG_BT_DEVICE_NAME);
  }
#endif
  if (!bt_dev.id_count) {
    int err;

    err = bt_setup_id_addr();
    if (err) {
      BT_ERR("Unable to setup an identity address");
      return err;
    }
  }

  /* Make sure that the identities created by bt_id_create after
   * bt_enable is saved to persistent storage. */
  if (!atomic_test_bit(bt_dev.flags, BT_DEV_PRESET_ID)) {
    bt_settings_save_id();
  }

  if (!atomic_test_bit(bt_dev.flags, BT_DEV_READY)) {
    bt_finalize_init();
  }

  return 0;
}

SETTINGS_STATIC_HANDLER_DEFINE(bt, "bt", NULL, set, commit, NULL);

#endif //! BFLB_BLE

int bt_settings_init(void) {
#if defined(BFLB_BLE)
  return 0;
#else
  int err;

  BT_DBG("");

  err = settings_subsys_init();
  if (err) {
    BT_ERR("settings_subsys_init failed (err %d)", err);
    return err;
  }

  return 0;
#endif
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/settings.h
================================================
/*
 * Copyright (c) 2018 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#if defined(BFLB_BLE)
#include "addr.h"
#endif

/* Max settings key length (with all components) */
#define BT_SETTINGS_KEY_MAX 36

/* Base64-encoded string buffer size of in_size bytes */
#define BT_SETTINGS_SIZE(in_size) ((((((in_size)-1) / 3) * 4) + 4) + 1)

/* Helpers for keys containing a bdaddr */
void bt_settings_encode_key(char *path, size_t path_size, const char *subsys,
                            bt_addr_le_t *addr, const char *key);
int bt_settings_decode_key(const char *key, bt_addr_le_t *addr);

void bt_settings_save_id(void);

int bt_settings_init(void);

#if defined(BFLB_BLE)
#define NV_LOCAL_NAME    "LOCAL_NAME"
#define NV_LOCAL_ID_ADDR "LOCAL_ID_ADDR"
#define NV_LOCAL_IRK     "LOCAL_IRK"
#define NV_KEY_POOL      "KEY_POOL"
#define NV_IMG_info      "IMG_INFO"

int bt_settings_get_bin(const char *key, u8_t *value, size_t exp_len, size_t *real_len);
int bt_settings_set_bin(const char *key, const u8_t *value, size_t length);
int settings_delete(const char *key);
int settings_save_one(const char *key, const u8_t *value, size_t length);
void bt_settings_save_name(void);
void bt_local_info_load(void);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/smp.h
================================================
/**
 * @file smp.h
 * Security Manager Protocol implementation header
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

struct bt_smp_hdr {
    u8_t code;
} __packed;

#define BT_SMP_ERR_PASSKEY_ENTRY_FAILED      0x01
#define BT_SMP_ERR_OOB_NOT_AVAIL             0x02
#define BT_SMP_ERR_AUTH_REQUIREMENTS         0x03
#define BT_SMP_ERR_CONFIRM_FAILED            0x04
#define BT_SMP_ERR_PAIRING_NOTSUPP           0x05
#define BT_SMP_ERR_ENC_KEY_SIZE              0x06
#define BT_SMP_ERR_CMD_NOTSUPP               0x07
#define BT_SMP_ERR_UNSPECIFIED               0x08
#define BT_SMP_ERR_REPEATED_ATTEMPTS         0x09
#define BT_SMP_ERR_INVALID_PARAMS            0x0a
#define BT_SMP_ERR_DHKEY_CHECK_FAILED        0x0b
#define BT_SMP_ERR_NUMERIC_COMP_FAILED       0x0c
#define BT_SMP_ERR_BREDR_PAIRING_IN_PROGRESS 0x0d
#define BT_SMP_ERR_CROSS_TRANSP_NOT_ALLOWED  0x0e

#define BT_SMP_IO_DISPLAY_ONLY     0x00
#define BT_SMP_IO_DISPLAY_YESNO    0x01
#define BT_SMP_IO_KEYBOARD_ONLY    0x02
#define BT_SMP_IO_NO_INPUT_OUTPUT  0x03
#define BT_SMP_IO_KEYBOARD_DISPLAY 0x04

#define BT_SMP_OOB_DATA_MASK   0x01
#define BT_SMP_OOB_NOT_PRESENT 0x00
#define BT_SMP_OOB_PRESENT     0x01

#define BT_SMP_MIN_ENC_KEY_SIZE 7
#define BT_SMP_MAX_ENC_KEY_SIZE 16

#define BT_SMP_DIST_ENC_KEY  0x01
#define BT_SMP_DIST_ID_KEY   0x02
#define BT_SMP_DIST_SIGN     0x04
#define BT_SMP_DIST_LINK_KEY 0x08

#define BT_SMP_DIST_MASK 0x0f

#define BT_SMP_AUTH_NONE     0x00
#define BT_SMP_AUTH_BONDING  0x01
#define BT_SMP_AUTH_MITM     0x04
#define BT_SMP_AUTH_SC       0x08
#define BT_SMP_AUTH_KEYPRESS 0x10
#define BT_SMP_AUTH_CT2      0x20

#define BT_SMP_CMD_PAIRING_REQ 0x01
#define BT_SMP_CMD_PAIRING_RSP 0x02
struct bt_smp_pairing {
    u8_t io_capability;
    u8_t oob_flag;
    u8_t auth_req;
    u8_t max_key_size;
    u8_t init_key_dist;
    u8_t resp_key_dist;
} __packed;

#define BT_SMP_CMD_PAIRING_CONFIRM 0x03
struct bt_smp_pairing_confirm {
    u8_t val[16];
} __packed;

#define BT_SMP_CMD_PAIRING_RANDOM 0x04
struct bt_smp_pairing_random {
    u8_t val[16];
} __packed;

#define BT_SMP_CMD_PAIRING_FAIL 0x05
struct bt_smp_pairing_fail {
    u8_t reason;
} __packed;

#define BT_SMP_CMD_ENCRYPT_INFO 0x06
struct bt_smp_encrypt_info {
    u8_t ltk[16];
} __packed;

#define BT_SMP_CMD_MASTER_IDENT 0x07
struct bt_smp_master_ident {
    u8_t ediv[2];
    u8_t rand[8];
} __packed;

#define BT_SMP_CMD_IDENT_INFO 0x08
struct bt_smp_ident_info {
    u8_t irk[16];
} __packed;

#define BT_SMP_CMD_IDENT_ADDR_INFO 0x09
struct bt_smp_ident_addr_info {
    bt_addr_le_t addr;
} __packed;

#define BT_SMP_CMD_SIGNING_INFO 0x0a
struct bt_smp_signing_info {
    u8_t csrk[16];
} __packed;

#define BT_SMP_CMD_SECURITY_REQUEST 0x0b
struct bt_smp_security_request {
    u8_t auth_req;
} __packed;

#define BT_SMP_CMD_PUBLIC_KEY 0x0c
struct bt_smp_public_key {
    u8_t x[32];
    u8_t y[32];
} __packed;

#define BT_SMP_DHKEY_CHECK 0x0d
struct bt_smp_dhkey_check {
    u8_t e[16];
} __packed;

int bt_smp_start_security(struct bt_conn *conn);
bool bt_smp_request_ltk(struct bt_conn *conn, u64_t rand, u16_t ediv,
                        u8_t *ltk);

void bt_smp_update_keys(struct bt_conn *conn);

int bt_smp_br_send_pairing_req(struct bt_conn *conn);

int bt_smp_init(void);

int bt_smp_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey);
int bt_smp_auth_passkey_confirm(struct bt_conn *conn);
int bt_smp_auth_pairing_confirm(struct bt_conn *conn);
int bt_smp_auth_cancel(struct bt_conn *conn);

int bt_smp_le_oob_generate_sc_data(struct bt_le_oob_sc_data *le_sc_oob);
int bt_smp_le_oob_set_sc_data(struct bt_conn *conn,
                              const struct bt_le_oob_sc_data *oobd_local,
                              const struct bt_le_oob_sc_data *oobd_remote);
int bt_smp_le_oob_get_sc_data(struct bt_conn *conn,
                              const struct bt_le_oob_sc_data **oobd_local,
                              const struct bt_le_oob_sc_data **oobd_remote);

/** brief Verify signed message
 *
 *  @param conn Bluetooth connection
 *  @param buf received packet buffer with message and signature
 *
 *  @return 0 in success, error code otherwise
 */
int bt_smp_sign_verify(struct bt_conn *conn, struct net_buf *buf);

/** brief Sign message
 *
 *  @param conn Bluetooth connection
 *  @param buf message buffer
 *
 *  @return 0 in success, error code otherwise
 */
int bt_smp_sign(struct bt_conn *conn, struct net_buf *buf);

#if defined(CONFIG_AUTO_PTS)
int bt_le_oob_set_legacy_tk(struct bt_conn *conn, const uint8_t *tk);
#endif

#if defined(CONFIG_BLE_AT_CMD)
struct smp_parameters {
    u8_t auth;
    u8_t iocap;
    u16_t key_size;
    u8_t init_key;
    u8_t rsp_key;
    u8_t set;
};

struct smp_parameters user_smp_paras;
int ble_set_smp_paramters(const struct smp_parameters *paras);
int ble_get_smp_paramters(const struct bt_conn *conn, struct smp_parameters *paras);
#endif
#if defined(BFLB_BLE_SMP_LOCAL_AUTH)
void smp_set_auth(u8_t auth);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/smp_null.c
================================================
/**
 * @file smp_null.c
 * Security Manager Protocol stub
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 

#include <../include/bluetooth/buf.h>
#include 
#include 

#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_HCI_CORE)
#define LOG_MODULE_NAME bt_smp
#include "log.h"

#include "conn_internal.h"
#include "hci_core.h"
#include "l2cap_internal.h"
#include "smp.h"

static struct bt_l2cap_le_chan bt_smp_pool[CONFIG_BT_MAX_CONN];

int bt_smp_sign_verify(struct bt_conn *conn, struct net_buf *buf) { return -ENOTSUP; }

int bt_smp_sign(struct bt_conn *conn, struct net_buf *buf) { return -ENOTSUP; }

static int bt_smp_recv(struct bt_l2cap_chan *chan, struct net_buf *buf) {
  struct bt_conn             *conn = chan->conn;
  struct bt_smp_pairing_fail *rsp;
  struct bt_smp_hdr          *hdr;

  /* If a device does not support pairing then it shall respond with
   * a Pairing Failed command with the reason set to "Pairing Not
   * Supported" when any command is received.
   * Core Specification Vol. 3, Part H, 3.3
   */

  buf = bt_l2cap_create_pdu(NULL, 0);
  /* NULL is not a possible return due to K_FOREVER */

  hdr       = net_buf_add(buf, sizeof(*hdr));
  hdr->code = BT_SMP_CMD_PAIRING_FAIL;

  rsp         = net_buf_add(buf, sizeof(*rsp));
  rsp->reason = BT_SMP_ERR_PAIRING_NOTSUPP;

  bt_l2cap_send(conn, BT_L2CAP_CID_SMP, buf);

  return 0;
}

static int bt_smp_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan) {
  int                             i;
  static struct bt_l2cap_chan_ops ops = {
      .recv = bt_smp_recv,
  };

  BT_DBG("conn %p handle %u", conn, conn->handle);

  for (i = 0; i < ARRAY_SIZE(bt_smp_pool); i++) {
    struct bt_l2cap_le_chan *smp = &bt_smp_pool[i];

    if (smp->chan.conn) {
      continue;
    }

    smp->chan.ops = &ops;

    *chan = &smp->chan;

    return 0;
  }

  BT_ERR("No available SMP context for conn %p", conn);

  return -ENOMEM;
}

BT_L2CAP_CHANNEL_DEFINE(smp_fixed_chan, BT_L2CAP_CID_SMP, bt_smp_accept);

int bt_smp_init(void) { return 0; }


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/host/uuid.c
================================================
/* uuid.c - Bluetooth UUID handling */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 

#include 

#define UUID_16_BASE_OFFSET 12

/* TODO: Decide whether to continue using BLE format or switch to RFC 4122 */

/* Base UUID : 0000[0000]-0000-1000-8000-00805F9B34FB
 * 0x2800    : 0000[2800]-0000-1000-8000-00805F9B34FB
 *  little endian 0x2800 : [00 28] -> no swapping required
 *  big endian 0x2800    : [28 00] -> swapping required
 */
static const struct bt_uuid_128 uuid128_base = {.uuid = {BT_UUID_TYPE_128}, .val = {BT_UUID_128_ENCODE(0x00000000, 0x0000, 0x1000, 0x8000, 0x00805F9B34FB)}};

static void uuid_to_uuid128(const struct bt_uuid *src, struct bt_uuid_128 *dst) {
  switch (src->type) {
  case BT_UUID_TYPE_16:
    *dst = uuid128_base;
    sys_put_le16(BT_UUID_16(src)->val, &dst->val[UUID_16_BASE_OFFSET]);
    return;
  case BT_UUID_TYPE_32:
    *dst = uuid128_base;
    sys_put_le32(BT_UUID_32(src)->val, &dst->val[UUID_16_BASE_OFFSET]);
    return;
  case BT_UUID_TYPE_128:
    memcpy(dst, src, sizeof(*dst));
    return;
  }
}

static int uuid128_cmp(const struct bt_uuid *u1, const struct bt_uuid *u2) {
  struct bt_uuid_128 uuid1, uuid2;

  uuid_to_uuid128(u1, &uuid1);
  uuid_to_uuid128(u2, &uuid2);

  return memcmp(uuid1.val, uuid2.val, 16);
}

int bt_uuid_cmp(const struct bt_uuid *u1, const struct bt_uuid *u2) {
  /* Convert to 128 bit if types don't match */
  if (u1->type != u2->type) {
    return uuid128_cmp(u1, u2);
  }

  switch (u1->type) {
  case BT_UUID_TYPE_16:
    return (int)BT_UUID_16(u1)->val - (int)BT_UUID_16(u2)->val;
  case BT_UUID_TYPE_32:
    return (int)BT_UUID_32(u1)->val - (int)BT_UUID_32(u2)->val;
  case BT_UUID_TYPE_128:
    return memcmp(BT_UUID_128(u1)->val, BT_UUID_128(u2)->val, 16);
  }

  return -EINVAL;
}

bool bt_uuid_create(struct bt_uuid *uuid, const u8_t *data, u8_t data_len) {
  /* Copy UUID from packet data/internal variable to internal bt_uuid */
  switch (data_len) {
  case 2:
    uuid->type            = BT_UUID_TYPE_16;
    BT_UUID_16(uuid)->val = sys_get_le16(data);
    break;
  case 4:
    uuid->type            = BT_UUID_TYPE_32;
    BT_UUID_32(uuid)->val = sys_get_le32(data);
    break;
  case 16:
    uuid->type = BT_UUID_TYPE_128;
    memcpy(&BT_UUID_128(uuid)->val, data, 16);
    break;
  default:
    return false;
  }
  return true;
}

#if defined(CONFIG_BT_DEBUG)
void bt_uuid_to_str(const struct bt_uuid *uuid, char *str, size_t len) {
  u32_t tmp1, tmp5;
  u16_t tmp0, tmp2, tmp3, tmp4;

  switch (uuid->type) {
  case BT_UUID_TYPE_16:
    snprintk(str, len, "%04x", BT_UUID_16(uuid)->val);
    break;
  case BT_UUID_TYPE_32:
    snprintk(str, len, "%04x", BT_UUID_32(uuid)->val);
    break;
  case BT_UUID_TYPE_128:
    memcpy(&tmp0, &BT_UUID_128(uuid)->val[0], sizeof(tmp0));
    memcpy(&tmp1, &BT_UUID_128(uuid)->val[2], sizeof(tmp1));
    memcpy(&tmp2, &BT_UUID_128(uuid)->val[6], sizeof(tmp2));
    memcpy(&tmp3, &BT_UUID_128(uuid)->val[8], sizeof(tmp3));
    memcpy(&tmp4, &BT_UUID_128(uuid)->val[10], sizeof(tmp4));
    memcpy(&tmp5, &BT_UUID_128(uuid)->val[12], sizeof(tmp5));

    snprintk(str, len, "%08x-%04x-%04x-%04x-%08x%04x", tmp5, tmp4, tmp3, tmp2, tmp1, tmp0);
    break;
  default:
    (void)memset(str, 0, len);
    return;
  }
}

const char *bt_uuid_str_real(const struct bt_uuid *uuid) {
  static char str[37];

  bt_uuid_to_str(uuid, str, sizeof(str));

  return str;
}
#endif /* CONFIG_BT_DEBUG */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/a2dp-codec.h
================================================
/** @file
 * @brief Advance Audio Distribution Profile - SBC Codec header.
 */
/*
 * SPDX-License-Identifier: Apache-2.0
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_A2DP_CODEC_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_A2DP_CODEC_H_

#ifdef __cplusplus
extern "C" {
#endif

/* Sampling Frequency */
#define A2DP_SBC_SAMP_FREQ_16000 BIT(7)
#define A2DP_SBC_SAMP_FREQ_32000 BIT(6)
#define A2DP_SBC_SAMP_FREQ_44100 BIT(5)
#define A2DP_SBC_SAMP_FREQ_48000 BIT(4)

/* Channel Mode */
#define A2DP_SBC_CH_MODE_MONO  BIT(3)
#define A2DP_SBC_CH_MODE_DUAL  BIT(2)
#define A2DP_SBC_CH_MODE_STREO BIT(1)
#define A2DP_SBC_CH_MODE_JOINT BIT(0)

/* Block Length */
#define A2DP_SBC_BLK_LEN_4  BIT(7)
#define A2DP_SBC_BLK_LEN_8  BIT(6)
#define A2DP_SBC_BLK_LEN_12 BIT(5)
#define A2DP_SBC_BLK_LEN_16 BIT(4)

/* Subbands */
#define A2DP_SBC_SUBBAND_4 BIT(3)
#define A2DP_SBC_SUBBAND_8 BIT(2)

/* Allocation Method */
#define A2DP_SBC_ALLOC_MTHD_SNR      BIT(1)
#define A2DP_SBC_ALLOC_MTHD_LOUDNESS BIT(0)

#define BT_A2DP_SBC_SAMP_FREQ(preset)  ((preset->config[0] >> 4) & 0x0f)
#define BT_A2DP_SBC_CHAN_MODE(preset)  ((preset->config[0]) & 0x0f)
#define BT_A2DP_SBC_BLK_LEN(preset)    ((preset->config[1] >> 4) & 0x0f)
#define BT_A2DP_SBC_SUB_BAND(preset)   ((preset->config[1] >> 2) & 0x03)
#define BT_A2DP_SBC_ALLOC_MTHD(preset) ((preset->config[1]) & 0x03)

/** @brief SBC Codec */
struct bt_a2dp_codec_sbc_params {
    /** First two octets of configuration */
    uint8_t config[2];
    /** Minimum Bitpool Value */
    uint8_t min_bitpool;
    /** Maximum Bitpool Value */
    uint8_t max_bitpool;
} __packed;

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_A2DP_CODEC_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/a2dp.h
================================================
/** @file
 * @brief Advance Audio Distribution Profile header.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_A2DP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_A2DP_H_

#include 

#ifdef __cplusplus
extern "C" {
#endif

/** @brief Stream Structure */
struct bt_a2dp_stream {
    /* TODO */
};

/** @brief Codec ID */
enum bt_a2dp_codec_id {
    /** Codec SBC */
    BT_A2DP_SBC = 0x00,
    /** Codec MPEG-1 */
    BT_A2DP_MPEG1 = 0x01,
    /** Codec MPEG-2 */
    BT_A2DP_MPEG2 = 0x02,
    /** Codec ATRAC */
    BT_A2DP_ATRAC = 0x04,
    /** Codec Non-A2DP */
    BT_A2DP_VENDOR = 0xff
};

/** @brief Media Codec Type */
enum MEDIA_CODEC_TYPE {
    /** SBC codec type */
    BT_A2DP_CODEC_TYPE_SBC = 0x00,
    /** AAC codec type */
    BT_A2DP_CODEC_TYPE_AAC = 0x02,
    /** AAC codec type */
    BT_A2DP_CODEC_TYPE_VENDOR = 0xff,
};

/** @brief Preset for the endpoint */
struct bt_a2dp_preset {
    /** Length of preset */
    uint8_t len;
    /** Preset */
    uint8_t preset[0];
};

/** @brief Stream End Point */
struct bt_a2dp_endpoint {
    /** Code ID */
    uint8_t codec_id;
    /** Stream End Point Information */
    struct bt_avdtp_seid_lsep info;
    /** Pointer to preset codec chosen */
    struct bt_a2dp_preset *preset;
    /** Capabilities */
    struct bt_a2dp_preset *caps;
};

/** @brief Stream End Point Media Type */
enum MEDIA_TYPE {
    /** Audio Media Type */
    BT_A2DP_AUDIO = 0x00,
    /** Video Media Type */
    BT_A2DP_VIDEO = 0x01,
    /** Multimedia Media Type */
    BT_A2DP_MULTIMEDIA = 0x02
};

/** @brief Stream End Point Role */
enum ROLE_TYPE {
    /** Source Role */
    BT_A2DP_SOURCE = 0,
    /** Sink Role */
    BT_A2DP_SINK = 1
};

/** @brief A2DP structure */
struct bt_a2dp;

/** @brief A2DP Connect.
 *
 *  This function is to be called after the conn parameter is obtained by
 *  performing a GAP procedure. The API is to be used to establish A2DP
 *  connection between devices.
 *
 *  @param conn Pointer to bt_conn structure.
 *
 *  @return pointer to struct bt_a2dp in case of success or NULL in case
 *  of error.
 */
struct bt_a2dp *bt_a2dp_connect(struct bt_conn *conn);

/** @brief Endpoint Registration.
 *
 *  This function is used for registering the stream end points. The user has
 *  to take care of allocating the memory, the preset pointer and then pass the
 *  required arguments. Also, only one sep can be registered at a time.
 *
 *  @param endpoint Pointer to bt_a2dp_endpoint structure.
 *  @param media_type Media type that the Endpoint is.
 *  @param role Role of Endpoint.
 *
 *  @return 0 in case of success and error code in case of error.
 */
int bt_a2dp_register_endpoint(struct bt_a2dp_endpoint *endpoint,
                              uint8_t media_type, uint8_t role);

/** @brief SBC decode init.
 *
 *  @return 0 in case of success and error code in case of error.
 */
int a2dp_sbc_decode_init();

/** @brief SBC decode process.
 *
 *  @return 0 in case of success and error code in case of error.
 */
int a2dp_sbc_decode_process(uint8_t *media_data, uint16_t data_len);

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_A2DP_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/addr.h
================================================
/** @file
 *  @brief Bluetooth device address definitions and utilities.
 */

/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ADDR_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ADDR_H_

#include 

#ifdef __cplusplus
extern "C" {
#endif

#define BT_ADDR_LE_PUBLIC    0x00
#define BT_ADDR_LE_RANDOM    0x01
#define BT_ADDR_LE_PUBLIC_ID 0x02
#define BT_ADDR_LE_RANDOM_ID 0x03

/** Bluetooth Device Address */
typedef struct {
    u8_t val[6];
} bt_addr_t;

/** Bluetooth LE Device Address */
typedef struct {
    u8_t type;
    bt_addr_t a;
} bt_addr_le_t;

#define BT_ADDR_ANY  (&(bt_addr_t){ { 0, 0, 0, 0, 0, 0 } })
#define BT_ADDR_NONE (&(bt_addr_t){ \
    { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } })
#define BT_ADDR_LE_ANY  (&(bt_addr_le_t){ 0, { { 0, 0, 0, 0, 0, 0 } } })
#define BT_ADDR_LE_NONE (&(bt_addr_le_t){ 0, \
                                          { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } } })

static inline int bt_addr_cmp(const bt_addr_t *a, const bt_addr_t *b)
{
    return memcmp(a, b, sizeof(*a));
}

static inline int bt_addr_le_cmp(const bt_addr_le_t *a, const bt_addr_le_t *b)
{
    return memcmp(a, b, sizeof(*a));
}

static inline void bt_addr_copy(bt_addr_t *dst, const bt_addr_t *src)
{
    memcpy(dst, src, sizeof(*dst));
}

static inline void bt_addr_le_copy(bt_addr_le_t *dst, const bt_addr_le_t *src)
{
    memcpy(dst, src, sizeof(*dst));
}

#define BT_ADDR_IS_RPA(a)    (((a)->val[5] & 0xc0) == 0x40)
#define BT_ADDR_IS_NRPA(a)   (((a)->val[5] & 0xc0) == 0x00)
#define BT_ADDR_IS_STATIC(a) (((a)->val[5] & 0xc0) == 0xc0)

#define BT_ADDR_SET_RPA(a)    ((a)->val[5] = (((a)->val[5] & 0x3f) | 0x40))
#define BT_ADDR_SET_NRPA(a)   ((a)->val[5] &= 0x3f)
#define BT_ADDR_SET_STATIC(a) ((a)->val[5] |= 0xc0)

int bt_addr_le_create_nrpa(bt_addr_le_t *addr);
int bt_addr_le_create_static(bt_addr_le_t *addr);

static inline bool bt_addr_le_is_rpa(const bt_addr_le_t *addr)
{
    if (addr->type != BT_ADDR_LE_RANDOM) {
        return false;
    }

    return BT_ADDR_IS_RPA(&addr->a);
}

static inline bool bt_addr_le_is_identity(const bt_addr_le_t *addr)
{
    if (addr->type == BT_ADDR_LE_PUBLIC) {
        return true;
    }

    return BT_ADDR_IS_STATIC(&addr->a);
}

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_ADDR_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/att.h
================================================
/** @file
 *  @brief Attribute Protocol handling.
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ATT_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ATT_H_

#ifdef __cplusplus
extern "C" {
#endif

#include 

/* Error codes for Error response PDU */
#define BT_ATT_ERR_INVALID_HANDLE          0x01
#define BT_ATT_ERR_READ_NOT_PERMITTED      0x02
#define BT_ATT_ERR_WRITE_NOT_PERMITTED     0x03
#define BT_ATT_ERR_INVALID_PDU             0x04
#define BT_ATT_ERR_AUTHENTICATION          0x05
#define BT_ATT_ERR_NOT_SUPPORTED           0x06
#define BT_ATT_ERR_INVALID_OFFSET          0x07
#define BT_ATT_ERR_AUTHORIZATION           0x08
#define BT_ATT_ERR_PREPARE_QUEUE_FULL      0x09
#define BT_ATT_ERR_ATTRIBUTE_NOT_FOUND     0x0a
#define BT_ATT_ERR_ATTRIBUTE_NOT_LONG      0x0b
#define BT_ATT_ERR_ENCRYPTION_KEY_SIZE     0x0c
#define BT_ATT_ERR_INVALID_ATTRIBUTE_LEN   0x0d
#define BT_ATT_ERR_UNLIKELY                0x0e
#define BT_ATT_ERR_INSUFFICIENT_ENCRYPTION 0x0f
#define BT_ATT_ERR_UNSUPPORTED_GROUP_TYPE  0x10
#define BT_ATT_ERR_INSUFFICIENT_RESOURCES  0x11
#define BT_ATT_ERR_DB_OUT_OF_SYNC          0x12
#define BT_ATT_ERR_VALUE_NOT_ALLOWED       0x13

/* Common Profile Error Codes (from CSS) */
#define BT_ATT_ERR_WRITE_REQ_REJECTED    0xfc
#define BT_ATT_ERR_CCC_IMPROPER_CONF     0xfd
#define BT_ATT_ERR_PROCEDURE_IN_PROGRESS 0xfe
#define BT_ATT_ERR_OUT_OF_RANGE          0xff

typedef void (*bt_att_func_t)(struct bt_conn *conn, u8_t err,
                              const void *pdu, u16_t length,
                              void *user_data);
typedef void (*bt_att_destroy_t)(void *user_data);

/* ATT request context */
struct bt_att_req {
    sys_snode_t node;
    bt_att_func_t func;
    bt_att_destroy_t destroy;
    struct net_buf_simple_state state;
    struct net_buf *buf;
#if defined(CONFIG_BT_SMP)
    bool retrying;
#endif /* CONFIG_BT_SMP */
};

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_ATT_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/avdtp.h
================================================
/** @file
 * @brief Audio/Video Distribution Transport Protocol header.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AVDTP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_AVDTP_H_

#ifdef __cplusplus
extern "C" {
#endif

/** @brief AVDTP SEID Information */
struct bt_avdtp_seid_info {
    /** Stream End Point ID */
    uint8_t id : 6;
    /** End Point usage status */
    uint8_t inuse : 1;
    /** Reserved */
    uint8_t rfa0 : 1;
    /** Media-type of the End Point */
    uint8_t media_type : 4;
    /** TSEP of the End Point */
    uint8_t tsep : 1;
    /** Reserved */
    uint8_t rfa1 : 3;
} __packed;

/** @brief AVDTP Local SEP*/
struct bt_avdtp_seid_lsep {
    /** Stream End Point information */
    struct bt_avdtp_seid_info sep;
    /** Pointer to next local Stream End Point structure */
    struct bt_avdtp_seid_lsep *next;
};

/** @brief AVDTP Stream */
struct bt_avdtp_stream {
    struct bt_l2cap_br_chan chan;   /* Transport Channel*/
    struct bt_avdtp_seid_info lsep; /* Configured Local SEP */
    struct bt_avdtp_seid_info rsep; /* Configured Remote SEP*/
    uint8_t state;                  /* current state of the stream */
    struct bt_avdtp_stream *next;
};

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_AVDTP_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/bluetooth.h
================================================
/** @file
 *  @brief Bluetooth subsystem core APIs.
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_BLUETOOTH_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_BLUETOOTH_H_

/**
 * @brief Bluetooth APIs
 * @defgroup bluetooth Bluetooth APIs
 * @{
 */

#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
//#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Generic Access Profile
 * @defgroup bt_gap Generic Access Profile
 * @ingroup bluetooth
 * @{
 */

/** @def BT_ID_DEFAULT
 *
 *  Convenience macro for specifying the default identity. This helps
 *  make the code more readable, especially when only one identity is
 *  supported.
 */
#define BT_ID_DEFAULT 0

/**
 * @typedef bt_ready_cb_t
 * @brief Callback for notifying that Bluetooth has been enabled.
 *
 *  @param err zero on success or (negative) error code otherwise.
 */
typedef void (*bt_ready_cb_t)(int err);

/** @brief Enable Bluetooth
 *
 *  Enable Bluetooth. Must be the called before any calls that
 *  require communication with the local Bluetooth hardware.
 *
 *  @param cb Callback to notify completion or NULL to perform the
 *  enabling synchronously.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_enable(bt_ready_cb_t cb);

/** @brief Set Bluetooth Device Name
 *
 *  Set Bluetooth GAP Device Name.
 *
 *  @param name New name
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_set_name(const char *name);

/** @brief Get Bluetooth Device Name
 *
 *  Get Bluetooth GAP Device Name.
 *
 *  @return Bluetooth Device Name
 */
const char *bt_get_name(void);

/** @brief Set the local Identity Address
 *
 *  Allows setting the local Identity Address from the application.
 *  This API must be called before calling bt_enable(). Calling it at any
 *  other time will cause it to fail. In most cases the application doesn't
 *  need to use this API, however there are a few valid cases where
 *  it can be useful (such as for testing).
 *
 *  At the moment, the given address must be a static random address. In the
 *  future support for public addresses may be added.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_set_id_addr(const bt_addr_le_t *addr);

/** @brief Get the currently configured identities.
 *
 *  Returns an array of the currently configured identity addresses. To
 *  make sure all available identities can be retrieved, the number of
 *  elements in the @a addrs array should be CONFIG_BT_ID_MAX. The identity
 *  identifier that some APIs expect (such as advertising parameters) is
 *  simply the index of the identity in the @a addrs array.
 *
 *  Note: Deleted identities may show up as BT_LE_ADDR_ANY in the returned
 *  array.
 *
 *  @param addrs Array where to store the configured identities.
 *  @param count Should be initialized to the array size. Once the function
 *               returns it will contain the number of returned identities.
 */
void bt_id_get(bt_addr_le_t *addrs, size_t *count);

/** @brief Create a new identity.
 *
 *  Create a new identity using the given address and IRK. This function
 *  can be called before calling bt_enable(), in which case it can be used
 *  to override the controller's public address (in case it has one). However,
 *  the new identity will only be stored persistently in flash when this API
 *  is used after bt_enable(). The reason is that the persistent settings
 *  are loaded after bt_enable() and would therefore cause potential conflicts
 *  with the stack blindly overwriting what's stored in flash. The identity
 *  will also not be written to flash in case a pre-defined address is
 *  provided, since in such a situation the app clearly has some place it got
 *  the address from and will be able to repeat the procedure on every power
 *  cycle, i.e. it would be redundant to also store the information in flash.
 *
 *  If the application wants to have the stack randomly generate identities
 *  and store them in flash for later recovery, the way to do it would be
 *  to first initialize the stack (using bt_enable), then call settings_load(),
 *  and after that check with bt_id_get() how many identities were recovered.
 *  If an insufficient amount of identities were recovered the app may then
 *  call bt_id_create() to create new ones.
 *
 *  @param addr Address to use for the new identity. If NULL or initialized
 *              to BT_ADDR_LE_ANY the stack will generate a new static
 *              random address for the identity and copy it to the given
 *              parameter upon return from this function (in case the
 *              parameter was non-NULL).
 *  @param irk  Identity Resolving Key (16 bytes) to be used with this
 *              identity. If set to all zeroes or NULL, the stack will
 *              generate a random IRK for the identity and copy it back
 *              to the parameter upon return from this function (in case
 *              the parameter was non-NULL). If privacy support
 *              (CONFIG_BT_PRIVACY) is not enabled this parameter must
 *              be NULL.
 *
 *  @return Identity identifier (>= 0) in case of success, or a negative
 *          error code on failure.
 */
int bt_id_create(bt_addr_le_t *addr, u8_t *irk);

/** @brief Reset/reclaim an identity for reuse.
 *
 *  The semantics of the @a addr and @a irk parameters of this function
 *  are the same as with bt_id_create(). The difference is the first
 *  @a id parameter that needs to be an existing identity (if it doesn't
 *  exist this function will return an error). When given an existing
 *  identity this function will disconnect any connections created using it,
 *  remove any pairing keys or other data associated with it, and then create
 *  a new identity in the same slot, based on the @a addr and @a irk
 *  parameters.
 *
 *  Note: the default identity (BT_ID_DEFAULT) cannot be reset, i.e. this
 *  API will return an error if asked to do that.
 *
 *  @param id   Existing identity identifier.
 *  @param addr Address to use for the new identity. If NULL or initialized
 *              to BT_ADDR_LE_ANY the stack will generate a new static
 *              random address for the identity and copy it to the given
 *              parameter upon return from this function (in case the
 *              parameter was non-NULL).
 *  @param irk  Identity Resolving Key (16 bytes) to be used with this
 *              identity. If set to all zeroes or NULL, the stack will
 *              generate a random IRK for the identity and copy it back
 *              to the parameter upon return from this function (in case
 *              the parameter was non-NULL). If privacy support
 *              (CONFIG_BT_PRIVACY) is not enabled this parameter must
 *              be NULL.
 *
 *  @return Identity identifier (>= 0) in case of success, or a negative
 *          error code on failure.
 */
int bt_id_reset(u8_t id, bt_addr_le_t *addr, u8_t *irk);

/** @brief Delete an identity.
 *
 *  When given a valid identity this function will disconnect any connections
 *  created using it, remove any pairing keys or other data associated with
 *  it, and then flag is as deleted, so that it can not be used for any
 *  operations. To take back into use the slot the identity was occupying the
 *  bt_id_reset() API needs to be used.
 *
 *  Note: the default identity (BT_ID_DEFAULT) cannot be deleted, i.e. this
 *  API will return an error if asked to do that.
 *
 *  @param id   Existing identity identifier.
 *
 *  @return 0 in case of success, or a negative error code on failure.
 */
int bt_id_delete(u8_t id);

/* Advertising API */

/** Description of different data types that can be encoded into
  * advertising data. Used to form arrays that are passed to the
  * bt_le_adv_start() function.
  */
struct bt_data {
    u8_t type;
    u8_t data_len;
    const u8_t *data;
};

/** @brief Helper to declare elements of bt_data arrays
 *
 *  This macro is mainly for creating an array of struct bt_data
 *  elements which is then passed to bt_le_adv_start().
 *
 *  @param _type Type of advertising data field
 *  @param _data Pointer to the data field payload
 *  @param _data_len Number of bytes behind the _data pointer
 */
#define BT_DATA(_type, _data, _data_len) \
    {                                    \
        .type = (_type),                 \
        .data_len = (_data_len),         \
        .data = (const u8_t *)(_data),   \
    }

/** @brief Helper to declare elements of bt_data arrays
 *
 *  This macro is mainly for creating an array of struct bt_data
 *  elements which is then passed to bt_le_adv_start().
 *
 *  @param _type Type of advertising data field
 *  @param _bytes Variable number of single-byte parameters
 */
#define BT_DATA_BYTES(_type, _bytes...)  \
    BT_DATA(_type, ((u8_t[]){ _bytes }), \
            sizeof((u8_t[]){ _bytes }))

/** Advertising options */
enum {
    /** Convenience value when no options are specified. */
    BT_LE_ADV_OPT_NONE = 0,

    /** Advertise as connectable. Type of advertising is determined by
	 * providing SCAN_RSP data and/or enabling local privacy support.
	 */
    BT_LE_ADV_OPT_CONNECTABLE = BIT(0),

    /** Don't try to resume connectable advertising after a connection.
	 *  This option is only meaningful when used together with
	 *  BT_LE_ADV_OPT_CONNECTABLE. If set the advertising will be stopped
	 *  when bt_le_adv_stop() is called or when an incoming (slave)
	 *  connection happens. If this option is not set the stack will
	 *  take care of keeping advertising enabled even as connections
	 *  occur.
	 */
    /* if defined CONFIG_BLE_MULTI_ADV , Only support adv one time.*/
    BT_LE_ADV_OPT_ONE_TIME = BIT(1),

    /** Advertise using the identity address as the own address.
	 *  @warning This will compromise the privacy of the device, so care
	 *           must be taken when using this option.
	 */
    BT_LE_ADV_OPT_USE_IDENTITY = BIT(2),

    /** Advertise using GAP device name */
    BT_LE_ADV_OPT_USE_NAME = BIT(3),

    /** Use low duty directed advertising mode, otherwise high duty mode
	 *  will be used. This option is only effective when used with
	 *  bt_conn_create_slave_le().
	 */
    BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY = BIT(4),

    /** Enable use of Resolvable Private Address (RPA) as the target address
	 *  in directed advertisements when CONFIG_BT_PRIVACY is not enabled.
	 *  This is required if the remote device is privacy-enabled and
	 *  supports address resolution of the target address in directed
	 *  advertisement.
	 *  It is the responsibility of the application to check that the remote
	 *  device supports address resolution of directed advertisements by
	 *  reading its Central Address Resolution characteristic.
	 */
    BT_LE_ADV_OPT_DIR_ADDR_RPA = BIT(5),

    /** Use whitelist to filter devices that can request scan response
	 *  data.
	 */
    BT_LE_ADV_OPT_FILTER_SCAN_REQ = BIT(6),

    /** Use whitelist to filter devices that can connect. */
    BT_LE_ADV_OPT_FILTER_CONN = BIT(7),
};

/** LE Advertising Parameters. */
struct bt_le_adv_param {
    /** Local identity */
    u8_t id;

    /** Bit-field of advertising options */
    u8_t options;

    /** Minimum Advertising Interval (N * 0.625) */
    u16_t interval_min;

    /** Maximum Advertising Interval (N * 0.625) */
    u16_t interval_max;

#if defined(CONFIG_BT_STACK_PTS) || defined(CONFIG_AUTO_PTS)
    u8_t addr_type;
#endif
};

/** Helper to declare advertising parameters inline
  *
  * @param _options   Advertising Options
  * @param _int_min   Minimum advertising interval
  * @param _int_max   Maximum advertising interval
  */
#define BT_LE_ADV_PARAM(_options, _int_min, _int_max) \
    (&(struct bt_le_adv_param){                       \
        .options = (_options),                        \
        .interval_min = (_int_min),                   \
        .interval_max = (_int_max),                   \
    })

#define BT_LE_ADV_CONN BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE, \
                                       BT_GAP_ADV_FAST_INT_MIN_2, \
                                       BT_GAP_ADV_FAST_INT_MAX_2)

#define BT_LE_ADV_CONN_NAME BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | \
                                                BT_LE_ADV_OPT_USE_NAME, \
                                            BT_GAP_ADV_FAST_INT_MIN_2,  \
                                            BT_GAP_ADV_FAST_INT_MAX_2)

#define BT_LE_ADV_CONN_DIR_LOW_DUTY                                      \
    BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | BT_LE_ADV_OPT_ONE_TIME | \
                        BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY,                 \
                    BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2)

#define BT_LE_ADV_CONN_DIR BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | \
                                               BT_LE_ADV_OPT_ONE_TIME, \
                                           0, 0)

#define BT_LE_ADV_NCONN BT_LE_ADV_PARAM(0, BT_GAP_ADV_FAST_INT_MIN_2, \
                                        BT_GAP_ADV_FAST_INT_MAX_2)

#define BT_LE_ADV_NCONN_NAME BT_LE_ADV_PARAM(BT_LE_ADV_OPT_USE_NAME,    \
                                             BT_GAP_ADV_FAST_INT_MIN_2, \
                                             BT_GAP_ADV_FAST_INT_MAX_2)

/** @brief Start advertising
 *
 *  Set advertisement data, scan response data, advertisement parameters
 *  and start advertising.
 *
 *  @param param Advertising parameters.
 *  @param ad Data to be used in advertisement packets.
 *  @param ad_len Number of elements in ad
 *  @param sd Data to be used in scan response packets.
 *  @param sd_len Number of elements in sd
 *
 *  @return Zero on success or (negative) error code otherwise.
 *  @return -ECONNREFUSED When connectable advertising is requested and there
 *			  is already maximum number of connections established.
 *			  This error code is only guaranteed when using Zephyr
 *			  controller, for other controllers code returned in
 *			  this case may be -EIO.
 */
int bt_le_adv_start(const struct bt_le_adv_param *param,
                    const struct bt_data *ad, size_t ad_len,
                    const struct bt_data *sd, size_t sd_len);

/** @brief Update advertising
 *
 *  Update advertisement and scan response data.
 *
 *  @param ad Data to be used in advertisement packets.
 *  @param ad_len Number of elements in ad
 *  @param sd Data to be used in scan response packets.
 *  @param sd_len Number of elements in sd
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_le_adv_update_data(const struct bt_data *ad, size_t ad_len,
                          const struct bt_data *sd, size_t sd_len);

/** @brief Stop advertising
 *
 *  Stops ongoing advertising.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_le_adv_stop(void);

/** @typedef bt_le_scan_cb_t
 *  @brief Callback type for reporting LE scan results.
 *
 *  A function of this type is given to the bt_le_scan_start() function
 *  and will be called for any discovered LE device.
 *
 *  @param addr Advertiser LE address and type.
 *  @param rssi Strength of advertiser signal.
 *  @param adv_type Type of advertising response from advertiser.
 *  @param buf Buffer containing advertiser data.
 */
typedef void bt_le_scan_cb_t(const bt_addr_le_t *addr, s8_t rssi,
                             u8_t adv_type, struct net_buf_simple *buf);

enum {
    /* Filter duplicates. */
    BT_LE_SCAN_FILTER_DUPLICATE = BIT(0),

    /* Filter using whitelist. */
    BT_LE_SCAN_FILTER_WHITELIST = BIT(1),

    /* Filter using extended filter policies. */
    BT_LE_SCAN_FILTER_EXTENDED = BIT(2),
};

enum {
    /* Scan without requesting additional information from advertisers. */
    BT_LE_SCAN_TYPE_PASSIVE = 0x00,

    /* Scan and request additional information from advertisers. */
    BT_LE_SCAN_TYPE_ACTIVE = 0x01,
};

/** LE scan parameters */
struct bt_le_scan_param {
    /** Scan type (BT_LE_SCAN_TYPE_ACTIVE or BT_LE_SCAN_TYPE_PASSIVE) */
    u8_t type;

    /** Bit-field of scanning filter options. */
    u8_t filter_dup;

    /** Scan interval (N * 0.625 ms) */
    u16_t interval;

    /** Scan window (N * 0.625 ms) */
    u16_t window;
};

/** Helper to declare scan parameters inline
  *
  * @param _type     Scan Type, BT_LE_SCAN_TYPE_ACTIVE or
  *                  BT_LE_SCAN_TYPE_PASSIVE.
  * @param _filter   Filter options
  * @param _interval Scan Interval (N * 0.625 ms)
  * @param _window   Scan Window (N * 0.625 ms)
  */
#define BT_LE_SCAN_PARAM(_type, _filter, _interval, _window) \
    (&(struct bt_le_scan_param){                             \
        .type = (_type),                                     \
        .filter_dup = (_filter),                             \
        .interval = (_interval),                             \
        .window = (_window),                                 \
    })

/** Helper macro to enable active scanning to discover new devices. */
#define BT_LE_SCAN_ACTIVE BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_ACTIVE,      \
                                           BT_LE_SCAN_FILTER_DUPLICATE, \
                                           BT_GAP_SCAN_FAST_INTERVAL,   \
                                           BT_GAP_SCAN_FAST_WINDOW)

/** Helper macro to enable passive scanning to discover new devices.
 *
 * This macro should be used if information required for device identification
 * (e.g., UUID) are known to be placed in Advertising Data.
 */
#define BT_LE_SCAN_PASSIVE BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_PASSIVE,     \
                                            BT_LE_SCAN_FILTER_DUPLICATE, \
                                            BT_GAP_SCAN_FAST_INTERVAL,   \
                                            BT_GAP_SCAN_FAST_WINDOW)

/** @brief Start (LE) scanning
 *
 *  Start LE scanning with given parameters and provide results through
 *  the specified callback.
 *
 *  @param param Scan parameters.
 *  @param cb Callback to notify scan results.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
#if defined(CONFIG_BT_STACK_PTS)
int bt_le_pts_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb, u8_t addre_type);
#endif
int bt_le_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb);

/** @brief Stop (LE) scanning.
 *
 *  Stops ongoing LE scanning.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_le_scan_stop(void);

/** @brief Add device (LE) to whitelist.
 *
 *  Add peer device LE address to the whitelist.
 *
 *  @note The whitelist cannot be modified when an LE role is using
 *  the whitelist, i.e advertiser or scanner using a whitelist or automatic
 *  connecting to devices using whitelist.
 *
 *  @param addr Bluetooth LE identity address.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error.
 */
int bt_le_whitelist_add(const bt_addr_le_t *addr);

/** @brief Remove device (LE) from whitelist.
 *
 *  Remove peer device LE address from the whitelist.
 *
 *  @note The whitelist cannot be modified when an LE role is using
 *  the whitelist, i.e advertiser or scanner using a whitelist or automatic
 *  connecting to devices using whitelist.
 *
 *  @param addr Bluetooth LE identity address.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error.
 */
int bt_le_whitelist_rem(const bt_addr_le_t *addr);

/** @brief Clear whitelist.
 *
 *  Clear all devices from the whitelist.
 *
 *  @note The whitelist cannot be modified when an LE role is using
 *  the whitelist, i.e advertiser or scanner using a whitelist or automatic
 *  connecting to devices using whitelist.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error.
 */
int bt_le_whitelist_clear(void);

/** @brief Set (LE) channel map.
 *
 * @param chan_map Channel map.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_le_set_chan_map(u8_t chan_map[5]);

/** @brief Helper for parsing advertising (or EIR or OOB) data.
 *
 *  A helper for parsing the basic data types used for Extended Inquiry
 *  Response (EIR), Advertising Data (AD), and OOB data blocks. The most
 *  common scenario is to call this helper on the advertising data
 *  received in the callback that was given to bt_le_scan_start().
 *
 *  @param ad        Advertising data as given to the bt_le_scan_cb_t callback.
 *  @param func      Callback function which will be called for each element
 *                   that's found in the data. The callback should return
 *                   true to continue parsing, or false to stop parsing.
 *  @param user_data User data to be passed to the callback.
 */
void bt_data_parse(struct net_buf_simple *ad,
                   bool (*func)(struct bt_data *data, void *user_data),
                   void *user_data);

/** OOB data that is specific for LE SC pairing method. */
struct bt_le_oob_sc_data {
    /** Random Number. */
    u8_t r[16];

    /** Confirm Value. */
    u8_t c[16];
};

/** General OOB data. */
struct bt_le_oob {
    /** LE address. If local privacy is enabled this is Resolvable Private
	 *  Address.
	 */
    bt_addr_le_t addr;

    /** OOB data that are relevant for LESC pairing. */
    struct bt_le_oob_sc_data le_sc_data;
};

/**
 * @brief Get LE local Out Of Band information
 *
 * This function allows to get local information that are useful for Out Of Band
 * pairing or connection creation process.
 *
 * If privacy is enabled this will result in generating new Resolvable Private
 * Address that is valid for CONFIG_BT_RPA_TIMEOUT seconds. This address
 * will be used for advertising, active scanning and connection creation.
 *
 * @param id  Local identity, in most cases BT_ID_DEFAULT.
 * @param oob LE related information
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_le_oob_get_local(u8_t id, struct bt_le_oob *oob);

/** @brief BR/EDR discovery result structure */
struct bt_br_discovery_result {
    /** private */
    u8_t _priv[4];

    /** Remote device address */
    bt_addr_t addr;

    /** RSSI from inquiry */
    s8_t rssi;

    /** Class of Device */
    u8_t cod[3];

    /** Extended Inquiry Response */
    u8_t eir[240];
};

/** @typedef bt_br_discovery_cb_t
 *  @brief Callback type for reporting BR/EDR discovery (inquiry)
 *         results.
 *
 *  A callback of this type is given to the bt_br_discovery_start()
 *  function and will be called at the end of the discovery with
 *  information about found devices populated in the results array.
 *
 *  @param results Storage used for discovery results
 *  @param count Number of valid discovery results.
 */
typedef void bt_br_discovery_cb_t(struct bt_br_discovery_result *results,
                                  size_t count);

/** BR/EDR discovery parameters */
struct bt_br_discovery_param {
    /** Maximum length of the discovery in units of 1.28 seconds.
	 *  Valid range is 0x01 - 0x30.
	 */
    u8_t length;

    /** True if limited discovery procedure is to be used. */
    bool limited;
};

/** @brief Start BR/EDR discovery
 *
 *  Start BR/EDR discovery (inquiry) and provide results through the specified
 *  callback. When bt_br_discovery_cb_t is called it indicates that discovery
 *  has completed. If more inquiry results were received during session than
 *  fits in provided result storage, only ones with highest RSSI will be
 *  reported.
 *
 *  @param param Discovery parameters.
 *  @param results Storage for discovery results.
 *  @param count Number of results in storage. Valid range: 1-255.
 *  @param cb Callback to notify discovery results.
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_br_discovery_start(const struct bt_br_discovery_param *param,
                          struct bt_br_discovery_result *results, size_t count,
                          bt_br_discovery_cb_t cb);

/** @brief Stop BR/EDR discovery.
 *
 *  Stops ongoing BR/EDR discovery. If discovery was stopped by this call
 *  results won't be reported
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_br_discovery_stop(void);

int bt_disable(void);

struct bt_br_oob {
    /** BR/EDR address. */
    bt_addr_t addr;
};

/**
 * @brief Get BR/EDR local Out Of Band information
 *
 * This function allows to get local controller information that are useful
 * for Out Of Band pairing or connection creation process.
 *
 * @param oob Out Of Band information
 */
int bt_br_oob_get_local(struct bt_br_oob *oob);

/** @def BT_ADDR_STR_LEN
 *
 *  @brief Recommended length of user string buffer for Bluetooth address
 *
 *  @details The recommended length guarantee the output of address
 *  conversion will not lose valuable information about address being
 *  processed.
 */
#define BT_ADDR_STR_LEN 18

/** @def BT_ADDR_LE_STR_LEN
 *
 *  @brief Recommended length of user string buffer for Bluetooth LE address
 *
 *  @details The recommended length guarantee the output of address
 *  conversion will not lose valuable information about address being
 *  processed.
 */
#define BT_ADDR_LE_STR_LEN 30

/** @brief Converts binary Bluetooth address to string.
 *
 *  @param addr Address of buffer containing binary Bluetooth address.
 *  @param str Address of user buffer with enough room to store formatted
 *  string containing binary address.
 *  @param len Length of data to be copied to user string buffer. Refer to
 *  BT_ADDR_STR_LEN about recommended value.
 *
 *  @return Number of successfully formatted bytes from binary address.
 */
static inline int bt_addr_to_str(const bt_addr_t *addr, char *str, size_t len)
{
    return snprintk(str, len, "%02X:%02X:%02X:%02X:%02X:%02X",
                    addr->val[5], addr->val[4], addr->val[3],
                    addr->val[2], addr->val[1], addr->val[0]);
}

/** @brief Converts binary LE Bluetooth address to string.
 *
 *  @param addr Address of buffer containing binary LE Bluetooth address.
 *  @param str Address of user buffer with enough room to store
 *  formatted string containing binary LE address.
 *  @param len Length of data to be copied to user string buffer. Refer to
 *  BT_ADDR_LE_STR_LEN about recommended value.
 *
 *  @return Number of successfully formatted bytes from binary address.
 */
static inline int bt_addr_le_to_str(const bt_addr_le_t *addr, char *str,
                                    size_t len)
{
    char type[10];

    switch (addr->type) {
        case BT_ADDR_LE_PUBLIC:
            strcpy(type, "public");
            break;
        case BT_ADDR_LE_RANDOM:
            strcpy(type, "random");
            break;
        case BT_ADDR_LE_PUBLIC_ID:
            strcpy(type, "public-id");
            break;
        case BT_ADDR_LE_RANDOM_ID:
            strcpy(type, "random-id");
            break;
        default:
            snprintk(type, sizeof(type), "0x%02x", addr->type);
            break;
    }

    return snprintk(str, len, "%02X:%02X:%02X:%02X:%02X:%02X (%s)",
                    addr->a.val[5], addr->a.val[4], addr->a.val[3],
                    addr->a.val[2], addr->a.val[1], addr->a.val[0], type);
}

/**
 * @brief Convert Bluetooth address from string to binary.
 *
 * @param[in]  str   The string representation of a Bluetooth address.
 * @param[out] addr  Address of buffer to store the Bluetooth address
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_addr_from_str(const char *str, bt_addr_t *addr);

/**
 * @brief Convert LE Bluetooth address from string to binary.
 *
 * @param[in]  str   The string representation of an LE Bluetooth address.
 * @param[in]  type  The string representation of the LE Bluetooth address type.
 * @param[out] addr  Address of buffer to store the LE Bluetooth address
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_addr_le_from_str(const char *str, const char *type, bt_addr_le_t *addr);

/** @brief Enable/disable set controller in discoverable state.
 *
 *  Allows make local controller to listen on INQUIRY SCAN channel and responds
 *  to devices making general inquiry. To enable this state it's mandatory
 *  to first be in connectable state.
 *
 *  @param enable Value allowing/disallowing controller to become discoverable.
 *
 *  @return Negative if fail set to requested state or requested state has been
 *  already set. Zero if done successfully.
 */
int bt_br_set_discoverable(bool enable);

/** @brief Enable/disable set controller in connectable state.
 *
 *  Allows make local controller to be connectable. It means the controller
 *  start listen to devices requests on PAGE SCAN channel. If disabled also
 *  resets discoverability if was set.
 *
 *  @param enable Value allowing/disallowing controller to be connectable.
 *
 *  @return Negative if fail set to requested state or requested state has been
 *  already set. Zero if done successfully.
 */
int bt_br_set_connectable(bool enable);

/** Clear pairing information.
  *
  * @param id    Local identity (mostly just BT_ID_DEFAULT).
  * @param addr  Remote address, NULL or BT_ADDR_LE_ANY to clear all remote
  *              devices.
  *
  * @return 0 on success or negative error value on failure.
  */
int bt_unpair(u8_t id, const bt_addr_le_t *addr);

/** Information about a bond with a remote device. */
struct bt_bond_info {
    /** Address of the remote device. */
    bt_addr_le_t addr;
};

/** Iterate through all existing bonds.
  *
  * @param id         Local identity (mostly just BT_ID_DEFAULT).
  * @param func       Function to call for each bond.
  * @param user_data  Data to pass to the callback function.
  */
void bt_foreach_bond(u8_t id, void (*func)(const struct bt_bond_info *info, void *user_data),
                     void *user_data);

/**
  * write extern inquiry response.
  */
int bt_br_write_eir(u8_t rec, u8_t *data);
/**
 * @}
 */

#ifdef __cplusplus
}
#endif
/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_BLUETOOTH_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/buf.h
================================================
/** @file
 *  @brief Bluetooth data buffer API
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_BLUETOOTH_BUF_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_BUF_H_

/**
 * @brief Data buffers
 * @defgroup bt_buf Data buffers
 * @ingroup bluetooth
 * @{
 */

#include 
#include 
#include 

/** Possible types of buffers passed around the Bluetooth stack */
enum bt_buf_type {
    /** HCI command */
    BT_BUF_CMD,
    /** HCI event */
    BT_BUF_EVT,
    /** Outgoing ACL data */
    BT_BUF_ACL_OUT,
    /** Incoming ACL data */
    BT_BUF_ACL_IN,
    /** Outgoing ISO data */
    BT_BUF_ISO_OUT,
    /** Incoming ISO data */
    BT_BUF_ISO_IN,
};

/** Minimum amount of user data size for buffers passed to the stack. */
#define BT_BUF_USER_DATA_MIN 4

#if defined(CONFIG_BT_HCI_RAW)
#define BT_BUF_RESERVE MAX(CONFIG_BT_HCI_RESERVE, CONFIG_BT_HCI_RAW_RESERVE)
#else
#define BT_BUF_RESERVE CONFIG_BT_HCI_RESERVE
#endif

/** Data size neeed for HCI RX buffers */
#define BT_BUF_RX_SIZE (BT_BUF_RESERVE + CONFIG_BT_RX_BUF_LEN)

int bt_buf_get_rx_avail_cnt(void);

/** Allocate a buffer for incoming data
 *
 *  This will set the buffer type so bt_buf_set_type() does not need to
 *  be explicitly called before bt_recv_prio().
 *
 *  @param type    Type of buffer. Only BT_BUF_EVT and BT_BUF_ACL_IN are
 *                 allowed.
 *  @param timeout Timeout in milliseconds, or one of the special values
 *                 K_NO_WAIT and K_FOREVER.
 *  @return A new buffer.
 */
struct net_buf *bt_buf_get_rx(enum bt_buf_type type, s32_t timeout);

/** Allocate a buffer for an HCI Command Complete/Status Event
 *
 *  This will set the buffer type so bt_buf_set_type() does not need to
 *  be explicitly called before bt_recv_prio().
 *
 *  @param timeout Timeout in milliseconds, or one of the special values
 *                 K_NO_WAIT and K_FOREVER.
 *  @return A new buffer.
 */
struct net_buf *bt_buf_get_cmd_complete(s32_t timeout);

/** Allocate a buffer for an HCI Event
 *
 *  This will set the buffer type so bt_buf_set_type() does not need to
 *  be explicitly called before bt_recv_prio() or bt_recv().
 *
 *  @param evt          HCI event code
 *  @param discardable  Whether the driver considers the event discardable.
 *  @param timeout      Timeout in milliseconds, or one of the special values
 *                      K_NO_WAIT and K_FOREVER.
 *  @return A new buffer.
 */
struct net_buf *bt_buf_get_evt(u8_t evt, bool discardable, s32_t timeout);

/** Set the buffer type
 *
 *  @param buf   Bluetooth buffer
 *  @param type  The BT_* type to set the buffer to
 */
static inline void bt_buf_set_type(struct net_buf *buf, enum bt_buf_type type)
{
    *(u8_t *)net_buf_user_data(buf) = type;
}

#if defined(BFLB_BLE)
static inline void bt_buf_set_rx_adv(struct net_buf *buf, bool is_adv)
{
    u8_t *usr_data = (u8_t *)net_buf_user_data(buf);
    usr_data++;
    *usr_data = is_adv;
}

static inline u8_t bt_buf_check_rx_adv(struct net_buf *buf)
{
    u8_t *usr_data = (u8_t *)net_buf_user_data(buf);
    usr_data++;
    return (*usr_data);
}
#endif

/** Get the buffer type
 *
 *  @param buf   Bluetooth buffer
 *
 *  @return The BT_* type to of the buffer
 */
static inline enum bt_buf_type bt_buf_get_type(struct net_buf *buf)
{
    /* De-referencing the pointer from net_buf_user_data(buf) as a
	 * pointer to an enum causes issues on qemu_x86 because the true
	 * size is 8-bit, but the enum is 32-bit on qemu_x86. So we put in
	 * a temporary cast to 8-bit to ensure only 8 bits are read from
	 * the pointer.
	 */
    return (enum bt_buf_type)(*(u8_t *)net_buf_user_data(buf));
}

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_BUF_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/conn.h
================================================
/** @file
 *  @brief Bluetooth connection handling
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_CONN_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_CONN_H_

/**
 * @brief Connection management
 * @defgroup bt_conn Connection management
 * @ingroup bluetooth
 * @{
 */

#include 
#include 
#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif

/** Opaque type representing a connection to a remote device */
struct bt_conn;

/** Connection parameters for LE connections */
struct bt_le_conn_param {
    u16_t interval_min;
    u16_t interval_max;
    u16_t latency;
    u16_t timeout;

#if defined(CONFIG_BT_STACK_PTS)
    u8_t own_address_type;
#endif
};

/** Helper to declare connection parameters inline
  *
  * @param int_min  Minimum Connection Interval (N * 1.25 ms)
  * @param int_max  Maximum Connection Interval (N * 1.25 ms)
  * @param lat      Connection Latency
  * @param to       Supervision Timeout (N * 10 ms)
  */
#define BT_LE_CONN_PARAM(int_min, int_max, lat, to) \
    (&(struct bt_le_conn_param){                    \
        .interval_min = (int_min),                  \
        .interval_max = (int_max),                  \
        .latency = (lat),                           \
        .timeout = (to),                            \
    })

/** Default LE connection parameters:
  *   Connection Interval: 30-50 ms
  *   Latency: 0
  *   Timeout: 4 s
  */
#define BT_LE_CONN_PARAM_DEFAULT BT_LE_CONN_PARAM(BT_GAP_INIT_CONN_INT_MIN, \
                                                  BT_GAP_INIT_CONN_INT_MAX, \
                                                  0, 400)
/** @brief Increment a connection's reference count.
 *
 *  Increment the reference count of a connection object.
 *
 *  @param conn Connection object.
 *
 *  @return Connection object with incremented reference count.
 */
struct bt_conn *bt_conn_ref(struct bt_conn *conn);

/** @brief Decrement a connection's reference count.
 *
 *  Decrement the reference count of a connection object.
 *
 *  @param conn Connection object.
 */
void bt_conn_unref(struct bt_conn *conn);

/** @brief Iterate through all existing connections.
 *
 * @param type  Connection Type
 * @param func  Function to call for each connection.
 * @param data  Data to pass to the callback function.
 */
void bt_conn_foreach(int type, void (*func)(struct bt_conn *conn, void *data),
                     void *data);

/** @brief Look up an existing connection by address.
 *
 *  Look up an existing connection based on the remote address.
 *
 *  @param id   Local identity (in most cases BT_ID_DEFAULT).
 *  @param peer Remote address.
 *
 *  @return Connection object or NULL if not found. The caller gets a
 *  new reference to the connection object which must be released with
 *  bt_conn_unref() once done using the object.
 */
struct bt_conn *bt_conn_lookup_addr_le(u8_t id, const bt_addr_le_t *peer);

#if defined(BFLB_BLE)
bool le_check_valid_conn(void);
void notify_disconnected(struct bt_conn *conn);
#if defined(BFLB_HOST_ASSISTANT)
void bt_notify_disconnected(void);
#endif
#endif

/** @brief Get destination (peer) address of a connection.
 *
 *  @param conn Connection object.
 *
 *  @return Destination address.
 */
const bt_addr_le_t *bt_conn_get_dst(const struct bt_conn *conn);

/** @brief Get array index of a connection
 *
 *  This function is used to map bt_conn to index of an array of
 *  connections. The array has CONFIG_BT_MAX_CONN elements.
 *
 *  @param conn Connection object.
 *
 *  @return Index of the connection object.
 *  The range of the returned value is 0..CONFIG_BT_MAX_CONN-1
 */
u8_t bt_conn_index(struct bt_conn *conn);

/** Connection Type */
enum {
    /** LE Connection Type */
    BT_CONN_TYPE_LE = BIT(0),
    /** BR/EDR Connection Type */
    BT_CONN_TYPE_BR = BIT(1),
    /** SCO Connection Type */
    BT_CONN_TYPE_SCO = BIT(2),
    /** ISO Connection Type */
    BT_CONN_TYPE_ISO = BIT(3),
    /** All Connection Type */
    BT_CONN_TYPE_ALL = BT_CONN_TYPE_LE | BT_CONN_TYPE_BR |
                       BT_CONN_TYPE_SCO | BT_CONN_TYPE_ISO,
};

/** LE Connection Info Structure */
struct bt_conn_le_info {
    /** Source (Local) Identity Address */
    const bt_addr_le_t *src;
    /** Destination (Remote) Identity Address or remote Resolvable Private
	 *  Address (RPA) before identity has been resolved.
	 */
    const bt_addr_le_t *dst;
    /** Local device address used during connection setup. */
    const bt_addr_le_t *local;
    /** Remote device address used during connection setup. */
    const bt_addr_le_t *remote;
    u16_t interval; /** Connection interval */
    u16_t latency;  /** Connection slave latency */
    u16_t timeout;  /** Connection supervision timeout */
};

/** BR/EDR Connection Info Structure */
struct bt_conn_br_info {
    const bt_addr_t *dst; /** Destination (Remote) BR/EDR address */
};

/** Connection role (master or slave) */
enum {
    BT_CONN_ROLE_MASTER,
    BT_CONN_ROLE_SLAVE,
};

/** @brief Connection Info Structure
 *
 *
 *  @param type Connection Type
 *  @param role Connection Role
 *  @param id Which local identity the connection was created with
 *  @param le LE Connection specific Info
 *  @param br BR/EDR Connection specific Info
 */
struct bt_conn_info {
    u8_t type;

    u8_t role;

    u8_t id;

    union {
        struct bt_conn_le_info le;

        struct bt_conn_br_info br;
    };
};

/** @brief Get connection info
 *
 *  @param conn Connection object.
 *  @param info Connection info object.
 *
 *  @return Zero on success or (negative) error code on failure.
 */
int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info);

/** @brief Get connected devices' info
 *
 *  @param info Connection info object.
 *
 *  @return Connected device number.
 */
int bt_conn_get_remote_dev_info(struct bt_conn_info *info);

/** @brief Update the connection parameters.
 *
 *  @param conn Connection object.
 *  @param param Updated connection parameters.
 *
 *  @return Zero on success or (negative) error code on failure.
 */
#if defined(CONFIG_BT_STACK_PTS)
int pts_bt_conn_le_param_update(struct bt_conn *conn,
                                const struct bt_le_conn_param *param);
#endif
int bt_conn_le_param_update(struct bt_conn *conn,
                            const struct bt_le_conn_param *param);
/** @brief Disconnect from a remote device or cancel pending connection.
 *
 *  Disconnect an active connection with the specified reason code or cancel
 *  pending outgoing connection.
 *
 *  @param conn Connection to disconnect.
 *  @param reason Reason code for the disconnection.
 *
 *  @return Zero on success or (negative) error code on failure.
 */
int bt_conn_disconnect(struct bt_conn *conn, u8_t reason);

/** @brief Initiate an LE connection to a remote device.
 *
 *  Allows initiate new LE link to remote peer using its address.
 *  Returns a new reference that the the caller is responsible for managing.
 *
 *  This uses the General Connection Establishment procedure.
 *
 *  @param peer  Remote address.
 *  @param param Initial connection parameters.
 *
 *  @return Valid connection object on success or NULL otherwise.
 */
struct bt_conn *bt_conn_create_le(const bt_addr_le_t *peer,
                                  const struct bt_le_conn_param *param);

/** @brief Automatically connect to remote devices in whitelist.
 *
 *  This uses the Auto Connection Establishment procedure.
 *
 *  @param param Initial connection parameters.
 *
 *  @return Zero on success or (negative) error code on failure.
 */
int bt_conn_create_auto_le(const struct bt_le_conn_param *param);

/** @brief Stop automatic connect creation.
 *
 *  @return Zero on success or (negative) error code on failure.
 */
int bt_conn_create_auto_stop(void);

/** @brief Automatically connect to remote device if it's in range.
 *
 *  This function enables/disables automatic connection initiation.
 *  Every time the device loses the connection with peer, this connection
 *  will be re-established if connectable advertisement from peer is received.
 *
 *  Note: Auto connect is disabled during explicit scanning.
 *
 *  @param addr Remote Bluetooth address.
 *  @param param If non-NULL, auto connect is enabled with the given
 *  parameters. If NULL, auto connect is disabled.
 *
 *  @return Zero on success or error code otherwise.
 */
int bt_le_set_auto_conn(const bt_addr_le_t *addr,
                        const struct bt_le_conn_param *param);

/** @brief Initiate directed advertising to a remote device
 *
 *  Allows initiating a new LE connection to remote peer with the remote
 *  acting in central role and the local device in peripheral role.
 *
 *  The advertising type will either be BT_LE_ADV_DIRECT_IND, or
 *  BT_LE_ADV_DIRECT_IND_LOW_DUTY if the BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY
 *  option was used as part of the advertising parameters.
 *
 *  In case of high duty cycle this will result in a callback with
 *  connected() with a new connection or with an error.
 *
 *  The advertising may be canceled with bt_conn_disconnect().
 *
 *  Returns a new reference that the the caller is responsible for managing.
 *
 *  @param peer  Remote address.
 *  @param param Directed advertising parameters.
 *
 *  @return Valid connection object on success or NULL otherwise.
 */
struct bt_conn *bt_conn_create_slave_le(const bt_addr_le_t *peer,
                                        const struct bt_le_adv_param *param);

/** Security level. */
typedef enum __packed {
    /** Level 0: Only for BR/EDR special cases, like SDP */
    BT_SECURITY_L0,
    /** Level 1: No encryption and no authentication. */
    BT_SECURITY_L1,
    /** Level 2: Encryption and no authentication (no MITM). */
    BT_SECURITY_L2,
    /** Level 3: Encryption and authentication (MITM). */
    BT_SECURITY_L3,
    /** Level 4: Authenticated Secure Connections and 128-bit key. */
    BT_SECURITY_L4,

    BT_SECURITY_NONE __deprecated = BT_SECURITY_L0,
    BT_SECURITY_LOW __deprecated = BT_SECURITY_L1,
    BT_SECURITY_MEDIUM __deprecated = BT_SECURITY_L2,
    BT_SECURITY_HIGH __deprecated = BT_SECURITY_L3,
    BT_SECURITY_FIPS __deprecated = BT_SECURITY_L4,

    /** Bit to force new pairing procedure, bit-wise OR with requested
	 *  security level.
	 */
    BT_SECURITY_FORCE_PAIR = BIT(7),
} bt_security_t;

/** @brief Set security level for a connection.
 *
 *  This function enable security (encryption) for a connection. If device is
 *  already paired with sufficiently strong key encryption will be enabled. If
 *  link is already encrypted with sufficiently strong key this function does
 *  nothing.
 *
 *  If device is not paired pairing will be initiated. If device is paired and
 *  keys are too weak but input output capabilities allow for strong enough keys
 *  pairing will be initiated.
 *
 *  This function may return error if required level of security is not possible
 *  to achieve due to local or remote device limitation (e.g., input output
 *  capabilities), or if the maximum number of paired devices has been reached.
 *
 *  This function may return error if the pairing procedure has already been
 *  initiated by the local device or the peer device.
 *
 *  @param conn Connection object.
 *  @param sec Requested security level.
 *
 *  @return 0 on success or negative error
 */
int bt_conn_set_security(struct bt_conn *conn, bt_security_t sec);

/** @brief Get security level for a connection.
 *
 *  @return Connection security level
 */
bt_security_t bt_conn_get_security(struct bt_conn *conn);

static inline int __deprecated bt_conn_security(struct bt_conn *conn,
                                                bt_security_t sec)
{
    return bt_conn_set_security(conn, sec);
}

/** @brief Get encryption key size.
 *
 *  This function gets encryption key size.
 *  If there is no security (encryption) enabled 0 will be returned.
 *
 *  @param conn Existing connection object.
 *
 *  @return Encryption key size.
 */
u8_t bt_conn_enc_key_size(struct bt_conn *conn);

enum bt_security_err {
    /** Security procedure successful. */
    BT_SECURITY_ERR_SUCCESS,

    /** Authentication failed. */
    BT_SECURITY_ERR_AUTH_FAIL,

    /** PIN or encryption key is missing. */
    BT_SECURITY_ERR_PIN_OR_KEY_MISSING,

    /** OOB data is not available.  */
    BT_SECURITY_ERR_OOB_NOT_AVAILABLE,

    /** The requested security level could not be reached. */
    BT_SECURITY_ERR_AUTH_REQUIREMENT,

    /** Pairing is not supported */
    BT_SECURITY_ERR_PAIR_NOT_SUPPORTED,

    /** Pairing is not allowed. */
    BT_SECURITY_ERR_PAIR_NOT_ALLOWED,

    /** Invalid parameters. */
    BT_SECURITY_ERR_INVALID_PARAM,

    /** Pairing failed but the exact reason could not be specified. */
    BT_SECURITY_ERR_UNSPECIFIED,
};

/** @brief Connection callback structure.
 *
 *  This structure is used for tracking the state of a connection.
 *  It is registered with the help of the bt_conn_cb_register() API.
 *  It's permissible to register multiple instances of this @ref bt_conn_cb
 *  type, in case different modules of an application are interested in
 *  tracking the connection state. If a callback is not of interest for
 *  an instance, it may be set to NULL and will as a consequence not be
 *  used for that instance.
 */
struct bt_conn_cb {
    /** @brief A new connection has been established.
	 *
	 *  This callback notifies the application of a new connection.
	 *  In case the err parameter is non-zero it means that the
	 *  connection establishment failed.
	 *
	 *  @param conn New connection object.
	 *  @param err HCI error. Zero for success, non-zero otherwise.
	 *
	 *  @p err can mean either of the following:
	 *  - @ref BT_HCI_ERR_UNKNOWN_CONN_ID Creating the connection started by
	 *    @ref bt_conn_create_le was canceled either by the user through
	 *    @ref bt_conn_disconnect or by the timeout in the host through
	 *    :option:`CONFIG_BT_CREATE_CONN_TIMEOUT`.
	 *  - @p BT_HCI_ERR_ADV_TIMEOUT Directed advertiser started by @ref
	 *    bt_conn_create_slave_le with high duty cycle timed out after 1.28
	 *    seconds.
	 */
    void (*connected)(struct bt_conn *conn, u8_t err);

    /** @brief A connection has been disconnected.
	 *
	 *  This callback notifies the application that a connection
	 *  has been disconnected.
	 *
	 *  @param conn Connection object.
	 *  @param reason HCI reason for the disconnection.
	 */
    void (*disconnected)(struct bt_conn *conn, u8_t reason);

    /** @brief LE connection parameter update request.
	 *
	 *  This callback notifies the application that a remote device
	 *  is requesting to update the connection parameters. The
	 *  application accepts the parameters by returning true, or
	 *  rejects them by returning false. Before accepting, the
	 *  application may also adjust the parameters to better suit
	 *  its needs.
	 *
	 *  It is recommended for an application to have just one of these
	 *  callbacks for simplicity. However, if an application registers
	 *  multiple it needs to manage the potentially different
	 *  requirements for each callback. Each callback gets the
	 *  parameters as returned by previous callbacks, i.e. they are not
	 *  necessarily the same ones as the remote originally sent.
	 *
	 *  @param conn Connection object.
	 *  @param param Proposed connection parameters.
	 *
	 *  @return true to accept the parameters, or false to reject them.
	 */
    bool (*le_param_req)(struct bt_conn *conn,
                         struct bt_le_conn_param *param);

    /** @brief The parameters for an LE connection have been updated.
	 *
	 *  This callback notifies the application that the connection
	 *  parameters for an LE connection have been updated.
	 *
	 *  @param conn Connection object.
	 *  @param interval Connection interval.
	 *  @param latency Connection latency.
	 *  @param timeout Connection supervision timeout.
	 */
    void (*le_param_updated)(struct bt_conn *conn, u16_t interval,
                             u16_t latency, u16_t timeout);

    /** @brief The PHY of the connection has changed.
	 *
	 *  This callback notifies the application that the PHY of the
	 *  connection has changed.
	 *
	 *  @param conn Connection object.
	 *  @param tx_phy Transmit phy.
	 *  @param rx_phy Receive phy.
	 */
    void (*le_phy_updated)(struct bt_conn *conn, u8_t tx_phy, u8_t rx_phy);
#if defined(CONFIG_BT_SMP)
    /** @brief Remote Identity Address has been resolved.
	 *
	 *  This callback notifies the application that a remote
	 *  Identity Address has been resolved
	 *
	 *  @param conn Connection object.
	 *  @param rpa Resolvable Private Address.
	 *  @param identity Identity Address.
	 */
    void (*identity_resolved)(struct bt_conn *conn,
                              const bt_addr_le_t *rpa,
                              const bt_addr_le_t *identity);
#endif /* CONFIG_BT_SMP */
#if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR)
    /** @brief The security level of a connection has changed.
	 *
	 *  This callback notifies the application that the security level
	 *  of a connection has changed.
	 *
	 *  @param conn Connection object.
	 *  @param level New security level of the connection.
	 *  @param err Security error. Zero for success, non-zero otherwise.
	 */
    void (*security_changed)(struct bt_conn *conn, bt_security_t level,
                             enum bt_security_err err);
#endif /* defined(CONFIG_BT_SMP) || defined(CONFIG_BT_BREDR) */
    struct bt_conn_cb *_next;
};

#if defined(CONFIG_BT_STACK_PTS)
typedef enum {
    SMP_AUTH_NO_BONDING_MITM = 1,
    SMP_IO_CAP_DISPLAY_ONLY = 2,
    SMP_AUTH_NO_MITM = 3,
    SMP_AUTH_NO_BONDING_MITM_IO_DISPLAY_ONLY = 4,
    SMP_IO_KEYBOARD_ONLY = 5,
    SMP_IO_NO_INPUT_OUTPUT = 6,
    SMP_PARING_INVALID_PUBLIC_KEY = 7,
} smp_test_id;

void bt_set_mitm(bool enable);
void bt_set_smpflag(smp_test_id id);
void bt_clear_smpflag(smp_test_id id);
#endif

/** @brief Register connection callbacks.
 *
 *  Register callbacks to monitor the state of connections.
 *
 *  @param cb Callback struct.
 */
void bt_conn_cb_register(struct bt_conn_cb *cb);

/** Enable/disable bonding.
 *
 *  Set/clear the Bonding flag in the Authentication Requirements of
 *  SMP Pairing Request/Response data.
 *  The initial value of this flag depends on BT_BONDABLE Kconfig setting.
 *  For the vast majority of applications calling this function shouldn't be
 *  needed.
 *
 *  @param enable Value allowing/disallowing to be bondable.
 */
void bt_set_bondable(bool enable);

/** Allow/disallow remote OOB data to be used for pairing.
 *
 *  Set/clear the OOB data flag for SMP Pairing Request/Response data.
 *  The initial value of this flag depends on BT_OOB_DATA_PRESENT Kconfig
 *  setting.
 *
 *  @param enable Value allowing/disallowing remote OOB data.
 */
void bt_set_oob_data_flag(bool enable);

/**
 * @brief Set OOB data during LE SC pairing procedure
 *
 * This function allows to set OOB data during the LE SC pairing procedure. The
 * function should only be called in response to the oob_data_request() callback
 * provided that LE SC method is used for pairing.
 *
 * The user should submit OOB data according to the information received in the
 * callback. This may yield three different configurations: with only local OOB
 * data present, with only remote OOB data present or with both local and
 * remote OOB data present.
 *
 * @param conn Connection object
 * @param oobd_local Local OOB data or NULL if not present
 * @param oobd_remote Remote OOB data or NULL if not present
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_le_oob_set_sc_data(struct bt_conn *conn,
                          const struct bt_le_oob_sc_data *oobd_local,
                          const struct bt_le_oob_sc_data *oobd_remote);

/**
 * @brief Get OOB data used for LE SC pairing procedure
 *
 * This function allows to get OOB data during the LE SC pairing procedure that
 * were set by the bt_le_oob_set_sc_data() API.
 *
 *  Note: The OOB data will only be available as long as the connection object
 *  associated with it is valid.
 *
 * @param conn Connection object
 * @param oobd_local Local OOB data or NULL if not set
 * @param oobd_remote Remote OOB data or NULL if not set
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_le_oob_get_sc_data(struct bt_conn *conn,
                          const struct bt_le_oob_sc_data **oobd_local,
                          const struct bt_le_oob_sc_data **oobd_remote);

/** @def BT_PASSKEY_INVALID
 *
 *  Special passkey value that can be used to disable a previously
 *  set fixed passkey.
 */
#define BT_PASSKEY_INVALID 0xffffffff

/** @brief Set a fixed passkey to be used for pairing.
 *
 *  This API is only available when the CONFIG_BT_FIXED_PASSKEY
 *  configuration option has been enabled.
 *
 *  Sets a fixed passkey to be used for pairing. If set, the
 *  pairing_confim() callback will be called for all incoming pairings.
 *
 *  @param passkey A valid passkey (0 - 999999) or BT_PASSKEY_INVALID
 *                 to disable a previously set fixed passkey.
 *
 *  @return 0 on success or a negative error code on failure.
 */
int bt_passkey_set(unsigned int passkey);

/** Info Structure for OOB pairing */
struct bt_conn_oob_info {
    /** Type of OOB pairing method */
    enum {
        /** LE legacy pairing */
        BT_CONN_OOB_LE_LEGACY,

        /** LE SC pairing */
        BT_CONN_OOB_LE_SC,
    } type;

    union {
        /** LESC OOB pairing parameters */
        struct {
            /** OOB data configuration */
            enum {
                /** Local OOB data requested */
                BT_CONN_OOB_LOCAL_ONLY,

                /** Remote OOB data requested */
                BT_CONN_OOB_REMOTE_ONLY,

                /** Both local and remote OOB data requested */
                BT_CONN_OOB_BOTH_PEERS,

                /** No OOB data requested */
                BT_CONN_OOB_NO_DATA,
            } oob_config;
        } lesc;
    };
};

/** Authenticated pairing callback structure */
struct bt_conn_auth_cb {
    /** @brief Display a passkey to the user.
	 *
	 *  When called the application is expected to display the given
	 *  passkey to the user, with the expectation that the passkey will
	 *  then be entered on the peer device. The passkey will be in the
	 *  range of 0 - 999999, and is expected to be padded with zeroes so
	 *  that six digits are always shown. E.g. the value 37 should be
	 *  shown as 000037.
	 *
	 *  This callback may be set to NULL, which means that the local
	 *  device lacks the ability do display a passkey. If set
	 *  to non-NULL the cancel callback must also be provided, since
	 *  this is the only way the application can find out that it should
	 *  stop displaying the passkey.
	 *
	 *  @param conn Connection where pairing is currently active.
	 *  @param passkey Passkey to show to the user.
	 */
    void (*passkey_display)(struct bt_conn *conn, unsigned int passkey);

    /** @brief Request the user to enter a passkey.
	 *
	 *  When called the user is expected to enter a passkey. The passkey
	 *  must be in the range of 0 - 999999, and should be expected to
	 *  be zero-padded, as that's how the peer device will typically be
	 *  showing it (e.g. 37 would be shown as 000037).
	 *
	 *  Once the user has entered the passkey its value should be given
	 *  to the stack using the bt_conn_auth_passkey_entry() API.
	 *
	 *  This callback may be set to NULL, which means that the local
	 *  device lacks the ability to enter a passkey. If set to non-NULL
	 *  the cancel callback must also be provided, since this is the
	 *  only way the application can find out that it should stop
	 *  requesting the user to enter a passkey.
	 *
	 *  @param conn Connection where pairing is currently active.
	 */
    void (*passkey_entry)(struct bt_conn *conn);

    /** @brief Request the user to confirm a passkey.
	 *
	 *  When called the user is expected to confirm that the given
	 *  passkey is also shown on the peer device.. The passkey will
	 *  be in the range of 0 - 999999, and should be zero-padded to
	 *  always be six digits (e.g. 37 would be shown as 000037).
	 *
	 *  Once the user has confirmed the passkey to match, the
	 *  bt_conn_auth_passkey_confirm() API should be called. If the
	 *  user concluded that the passkey doesn't match the
	 *  bt_conn_auth_cancel() API should be called.
	 *
	 *  This callback may be set to NULL, which means that the local
	 *  device lacks the ability to confirm a passkey. If set to non-NULL
	 *  the cancel callback must also be provided, since this is the
	 *  only way the application can find out that it should stop
	 *  requesting the user to confirm a passkey.
	 *
	 *  @param conn Connection where pairing is currently active.
	 *  @param passkey Passkey to be confirmed.
	 */
    void (*passkey_confirm)(struct bt_conn *conn, unsigned int passkey);

    /** @brief Request the user to provide OOB data.
	 *
	 *  When called the user is expected to provide OOB data. The required
	 *  data are indicated by the information structure.
	 *
	 *  For LESC OOB pairing method, the user should provide local OOB data,
	 *  remote OOB data or both depending on their availability. Their value
	 *  should be given to the stack using the bt_le_oob_set_sc_data() API.
	 *
	 *  This callback must be set to non-NULL in order to support OOB
	 *  pairing.
	 *
	 *  @param conn Connection where pairing is currently active.
	 *  @param info OOB pairing information.
	 */
    void (*oob_data_request)(struct bt_conn *conn,
                             struct bt_conn_oob_info *info);

    /** @brief Cancel the ongoing user request.
	 *
	 *  This callback will be called to notify the application that it
	 *  should cancel any previous user request (passkey display, entry
	 *  or confirmation).
	 *
	 *  This may be set to NULL, but must always be provided whenever the
	 *  passkey_display, passkey_entry passkey_confirm or pairing_confirm
	 *  callback has been provided.
	 *
	 *  @param conn Connection where pairing is currently active.
	 */
    void (*cancel)(struct bt_conn *conn);

    /** @brief Request confirmation for an incoming pairing.
	 *
	 *  This callback will be called to confirm an incoming pairing
	 *  request where none of the other user callbacks is applicable.
	 *
	 *  If the user decides to accept the pairing the
	 *  bt_conn_auth_pairing_confirm() API should be called. If the
	 *  user decides to reject the pairing the bt_conn_auth_cancel() API
	 *  should be called.
	 *
	 *  This callback may be set to NULL, which means that the local
	 *  device lacks the ability to confirm a pairing request. If set
	 *  to non-NULL the cancel callback must also be provided, since
	 *  this is the only way the application can find out that it should
	 *  stop requesting the user to confirm a pairing request.
	 *
	 *  @param conn Connection where pairing is currently active.
	 */
    void (*pairing_confirm)(struct bt_conn *conn);

#if defined(CONFIG_BT_BREDR)
    /** @brief Request the user to enter a passkey.
	 *
	 *  This callback will be called for a BR/EDR (Bluetooth Classic)
	 *  connection where pairing is being performed. Once called the
	 *  user is expected to enter a PIN code with a length between
	 *  1 and 16 digits. If the @a highsec parameter is set to true
	 *  the PIN code must be 16 digits long.
	 *
	 *  Once entered, the PIN code should be given to the stack using
	 *  the bt_conn_auth_pincode_entry() API.
	 *
	 *  This callback may be set to NULL, however in that case pairing
	 *  over BR/EDR will not be possible. If provided, the cancel
	 *  callback must be provided as well.
	 *
	 *  @param conn Connection where pairing is currently active.
	 *  @param highsec true if 16 digit PIN is required.
	 */
    void (*pincode_entry)(struct bt_conn *conn, bool highsec);
#endif

    /** @brief notify that pairing process was complete.
	 *
	 * This callback notifies the application that the pairing process
	 * has been completed.
	 *
	 * @param conn Connection object.
	 * @param bonded pairing is bonded or not.
	 */
    void (*pairing_complete)(struct bt_conn *conn, bool bonded);

    /** @brief notify that pairing process has failed.
	 *
	 * @param conn Connection object.
	 * @param reason Pairing failed reason
	 */
    void (*pairing_failed)(struct bt_conn *conn,
                           enum bt_security_err reason);
};

/** @brief Register authentication callbacks.
 *
 *  Register callbacks to handle authenticated pairing. Passing NULL
 *  unregisters a previous callbacks structure.
 *
 *  @param cb Callback struct.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb);

/** @brief Reply with entered passkey.
 *
 *  This function should be called only after passkey_entry callback from
 *  bt_conn_auth_cb structure was called.
 *
 *  @param conn Connection object.
 *  @param passkey Entered passkey.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey);

/** @brief Cancel ongoing authenticated pairing.
 *
 *  This function allows to cancel ongoing authenticated pairing.
 *
 *  @param conn Connection object.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_cancel(struct bt_conn *conn);

/** @brief Reply if passkey was confirmed to match by user.
 *
 *  This function should be called only after passkey_confirm callback from
 *  bt_conn_auth_cb structure was called.
 *
 *  @param conn Connection object.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_passkey_confirm(struct bt_conn *conn);

/** @brief Reply if incoming pairing was confirmed by user.
 *
 *  This function should be called only after pairing_confirm callback from
 *  bt_conn_auth_cb structure was called if user confirmed incoming pairing.
 *
 *  @param conn Connection object.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_pairing_confirm(struct bt_conn *conn);

/** @brief Reply with entered PIN code.
 *
 *  This function should be called only after PIN code callback from
 *  bt_conn_auth_cb structure was called. It's for legacy 2.0 devices.
 *
 *  @param conn Connection object.
 *  @param pin Entered PIN code.
 *
 *  @return Zero on success or negative error code otherwise
 */
int bt_conn_auth_pincode_entry(struct bt_conn *conn, const char *pin);

/** Connection parameters for BR/EDR connections */
struct bt_br_conn_param {
    bool allow_role_switch;
};

/** Helper to declare BR/EDR connection parameters inline
  *
  * @param role_switch True if role switch is allowed
  */
#define BT_BR_CONN_PARAM(role_switch)       \
    (&(struct bt_br_conn_param){            \
        .allow_role_switch = (role_switch), \
    })

/** Default BR/EDR connection parameters:
  *   Role switch allowed
  */
#define BT_BR_CONN_PARAM_DEFAULT BT_BR_CONN_PARAM(true)

/** @brief Initiate an BR/EDR connection to a remote device.
 *
 *  Allows initiate new BR/EDR link to remote peer using its address.
 *  Returns a new reference that the the caller is responsible for managing.
 *
 *  @param peer  Remote address.
 *  @param param Initial connection parameters.
 *
 *  @return Valid connection object on success or NULL otherwise.
 */
struct bt_conn *bt_conn_create_br(const bt_addr_t *peer,
                                  const struct bt_br_conn_param *param);

/** @brief Initiate an SCO connection to a remote device.
 *
 *  Allows initiate new SCO link to remote peer using its address.
 *  Returns a new reference that the the caller is responsible for managing.
 *
 *  @param peer  Remote address.
 *
 *  @return Valid connection object on success or NULL otherwise.
 */
struct bt_conn *bt_conn_create_sco(const bt_addr_t *peer);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_CONN_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/crypto.h
================================================
/** @file
 *  @brief Bluetooth subsystem crypto APIs.
 */

/*
 * Copyright (c) 2017 Nordic Semiconductor ASA
 * Copyright (c) 2015-2017 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_CRYPTO_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_CRYPTO_H_

/**
 * @brief Cryptography
 * @defgroup bt_crypto Cryptography
 * @ingroup bluetooth
 * @{
 */

#include 

#ifdef __cplusplus
extern "C" {
#endif

/** @brief Generate random data.
 *
 *  A random number generation helper which utilizes the Bluetooth
 *  controller's own RNG.
 *
 *  @param buf Buffer to insert the random data
 *  @param len Length of random data to generate
 *
 *  @return Zero on success or error code otherwise, positive in case
 *  of protocol error or negative (POSIX) in case of stack internal error
 */
int bt_rand(void *buf, size_t len);

/** @brief AES encrypt little-endian data.
 *
 *  An AES encrypt helper is used to request the Bluetooth controller's own
 *  hardware to encrypt the plaintext using the key and returns the encrypted
 *  data.
 *
 *  @param key 128 bit LS byte first key for the encryption of the plaintext
 *  @param plaintext 128 bit LS byte first plaintext data block to be encrypted
 *  @param enc_data 128 bit LS byte first encrypted data block
 *
 *  @return Zero on success or error code otherwise.
 */
int bt_encrypt_le(const u8_t key[16], const u8_t plaintext[16],
                  u8_t enc_data[16]);

/** @brief AES encrypt big-endian data.
 *
 *  An AES encrypt helper is used to request the Bluetooth controller's own
 *  hardware to encrypt the plaintext using the key and returns the encrypted
 *  data.
 *
 *  @param key 128 bit MS byte first key for the encryption of the plaintext
 *  @param plaintext 128 bit MS byte first plaintext data block to be encrypted
 *  @param enc_data 128 bit MS byte first encrypted data block
 *
 *  @return Zero on success or error code otherwise.
 */
int bt_encrypt_be(const u8_t key[16], const u8_t plaintext[16],
                  u8_t enc_data[16]);

#ifdef __cplusplus
}
#endif
/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_CRYPTO_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/gap.h
================================================
/** @file
 *  @brief Bluetooth Generic Access Profile defines and Assigned Numbers.
 */

/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_BLUETOOTH_GAP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_GAP_H_

#ifdef __cplusplus
extern "C" {
#endif

/* Company Identifiers (see Bluetooth Assigned Numbers) */
#define BT_COMP_ID_LF 0x05f1 /* The Linux Foundation */

/* EIR/AD data type definitions */
#define BT_DATA_FLAGS                0x01 /* AD flags */
#define BT_DATA_UUID16_SOME          0x02 /* 16-bit UUID, more available */
#define BT_DATA_UUID16_ALL           0x03 /* 16-bit UUID, all listed */
#define BT_DATA_UUID32_SOME          0x04 /* 32-bit UUID, more available */
#define BT_DATA_UUID32_ALL           0x05 /* 32-bit UUID, all listed */
#define BT_DATA_UUID128_SOME         0x06 /* 128-bit UUID, more available */
#define BT_DATA_UUID128_ALL          0x07 /* 128-bit UUID, all listed */
#define BT_DATA_NAME_SHORTENED       0x08 /* Shortened name */
#define BT_DATA_NAME_COMPLETE        0x09 /* Complete name */
#define BT_DATA_TX_POWER             0x0a /* Tx Power */
#define BT_DATA_SM_TK_VALUE          0x10 /* Security Manager TK Value */
#define BT_DATA_SM_OOB_FLAGS         0x11 /* Security Manager OOB Flags */
#define BT_DATA_SOLICIT16            0x14 /* Solicit UUIDs, 16-bit */
#define BT_DATA_SOLICIT128           0x15 /* Solicit UUIDs, 128-bit */
#define BT_DATA_SVC_DATA16           0x16 /* Service data, 16-bit UUID */
#define BT_DATA_GAP_APPEARANCE       0x19 /* GAP appearance */
#define BT_DATA_LE_BT_DEVICE_ADDRESS 0x1b /* LE Bluetooth Device Address */
#define BT_DATA_LE_ROLE              0x1c /* LE Role */
#define BT_DATA_SOLICIT32            0x1f /* Solicit UUIDs, 32-bit */
#define BT_DATA_SVC_DATA32           0x20 /* Service data, 32-bit UUID */
#define BT_DATA_SVC_DATA128          0x21 /* Service data, 128-bit UUID */
#define BT_DATA_LE_SC_CONFIRM_VALUE  0x22 /* LE SC Confirmation Value */
#define BT_DATA_LE_SC_RANDOM_VALUE   0x23 /* LE SC Random Value */
#define BT_DATA_URI                  0x24 /* URI */
#define BT_DATA_MESH_PROV            0x29 /* Mesh Provisioning PDU */
#define BT_DATA_MESH_MESSAGE         0x2a /* Mesh Networking PDU */
#define BT_DATA_MESH_BEACON          0x2b /* Mesh Beacon */

#define BT_DATA_MANUFACTURER_DATA 0xff /* Manufacturer Specific Data */

#define BT_LE_AD_LIMITED  0x01 /* Limited Discoverable */
#define BT_LE_AD_GENERAL  0x02 /* General Discoverable */
#define BT_LE_AD_NO_BREDR 0x04 /* BR/EDR not supported */

/* Defined GAP timers */
#define BT_GAP_SCAN_FAST_INTERVAL   0x0060 /* 60 ms    */
#define BT_GAP_SCAN_FAST_WINDOW     0x0030 /* 30 ms    */
#define BT_GAP_SCAN_SLOW_INTERVAL_1 0x0800 /* 1.28 s   */
#define BT_GAP_SCAN_SLOW_WINDOW_1   0x0012 /* 11.25 ms */
#define BT_GAP_SCAN_SLOW_INTERVAL_2 0x1000 /* 2.56 s   */
#define BT_GAP_SCAN_SLOW_WINDOW_2   0x0012 /* 11.25 ms */

#if defined(BFLB_BLE)
#define CONFIG_BT_BACKGROUND_SCAN_INTERVAL 0x0800
#define CONFIG_BT_BACKGROUND_SCAN_WINDOW   0x0012
#define BT_GAP_ADV_FAST_INT_MIN_3          0x0020 /* 20 ms   */
#define BT_GAP_ADV_FAST_INT_MAX_3          0x0020 /* 20 ms   */
#endif

#define BT_GAP_ADV_FAST_INT_MIN_1 0x0030 /* 30 ms    */
#define BT_GAP_ADV_FAST_INT_MAX_1 0x0060 /* 60 ms    */
#define BT_GAP_ADV_FAST_INT_MIN_2 0x00a0 /* 100 ms   */
#define BT_GAP_ADV_FAST_INT_MAX_2 0x00f0 /* 150 ms   */

#define BT_GAP_ADV_SLOW_INT_MIN  0x0640 /* 1 s      */
#define BT_GAP_ADV_SLOW_INT_MAX  0x0780 /* 1.2 s    */
#define BT_GAP_INIT_CONN_INT_MIN 0x0018 /* 30 ms    */
#define BT_GAP_INIT_CONN_INT_MAX 0x0028 /* 50 ms    */

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_GAP_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/gatt.h
================================================
/** @file
 *  @brief Generic Attribute Profile handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_GATT_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_GATT_H_

/**
 * @brief Generic Attribute Profile (GATT)
 * @defgroup bt_gatt Generic Attribute Profile (GATT)
 * @ingroup bluetooth
 * @{
 */

#include 
#include 
#include 
#include 
#include 
#include 
#ifdef __cplusplus
extern "C" {
#endif

/* GATT attribute permission bit field values */
enum {
    /** No operations supported, e.g. for notify-only */
    BT_GATT_PERM_NONE = 0,

    /** Attribute read permission. */
    BT_GATT_PERM_READ = BIT(0),

    /** Attribute write permission. */
    BT_GATT_PERM_WRITE = BIT(1),

    /** Attribute read permission with encryption.
	 *
	 *  If set, requires encryption for read access.
	 */
    BT_GATT_PERM_READ_ENCRYPT = BIT(2),

    /** Attribute write permission with encryption.
	 *
	 *  If set, requires encryption for write access.
	 */
    BT_GATT_PERM_WRITE_ENCRYPT = BIT(3),

    /** Attribute read permission with authentication.
	 *
	 *  If set, requires encryption using authenticated link-key for read
	 *  access.
	 */
    BT_GATT_PERM_READ_AUTHEN = BIT(4),

    /** Attribute write permission with authentication.
	 *
	 *  If set, requires encryption using authenticated link-key for write
	 *  access.
	 */
    BT_GATT_PERM_WRITE_AUTHEN = BIT(5),

    /** Attribute prepare write permission.
	 *
	 *  If set, allows prepare writes with use of BT_GATT_WRITE_FLAG_PREPARE
	 *  passed to write callback.
	 */
    BT_GATT_PERM_PREPARE_WRITE = BIT(6),
};

/**  @def BT_GATT_ERR
  *  @brief Construct error return value for attribute read and write callbacks.
  *
  *  @param _att_err ATT error code
  *
  *  @return Appropriate error code for the attribute callbacks.
  *
  */
#define BT_GATT_ERR(_att_err) (-(_att_err))

/* GATT attribute write flags */
enum {
    /** Attribute prepare write flag
	 *
	 * If set, write callback should only check if the device is
	 * authorized but no data shall be written.
	 */
    BT_GATT_WRITE_FLAG_PREPARE = BIT(0),

    /** Attribute write command flag
	 *
	 * If set, indicates that write operation is a command (Write without
	 * response) which doesn't generate any response.
	 */
    BT_GATT_WRITE_FLAG_CMD = BIT(1),
};

/** @brief GATT Attribute structure. */
struct bt_gatt_attr {
    /** Attribute UUID */
    const struct bt_uuid *uuid;

    /** Attribute read callback
	 *
	 *  The callback can also be used locally to read the contents of the
	 *  attribute in which case no connection will be set.
	 *
	 *  @param conn   The connection that is requesting to read
	 *  @param attr   The attribute that's being read
	 *  @param buf    Buffer to place the read result in
	 *  @param len    Length of data to read
	 *  @param offset Offset to start reading from
	 *
	 *  @return Number fo bytes read, or in case of an error
	 *          BT_GATT_ERR() with a specific ATT error code.
	 */
    ssize_t (*read)(struct bt_conn *conn,
                    const struct bt_gatt_attr *attr,
                    void *buf, u16_t len,
                    u16_t offset);

    /** Attribute write callback
	 *
	 *  The callback can also be used locally to read the contents of the
	 *  attribute in which case no connection will be set.
	 *
	 *  @param conn   The connection that is requesting to write
	 *  @param attr   The attribute that's being written
	 *  @param buf    Buffer with the data to write
	 *  @param len    Number of bytes in the buffer
	 *  @param offset Offset to start writing from
	 *  @param flags  Flags (BT_GATT_WRITE_*)
	 *
	 *  @return Number of bytes written, or in case of an error
	 *          BT_GATT_ERR() with a specific ATT error code.
	 */
    ssize_t (*write)(struct bt_conn *conn,
                     const struct bt_gatt_attr *attr,
                     const void *buf, u16_t len,
                     u16_t offset, u8_t flags);

    /** Attribute user data */
    void *user_data;
    /** Attribute handle */
    u16_t handle;
    /** Attribute permissions */
    u8_t perm;
};

/** @brief GATT Service structure */
struct bt_gatt_service_static {
    /** Service Attributes */
    const struct bt_gatt_attr *attrs;
    /** Service Attribute count */
    size_t attr_count;
};

/** @brief GATT Service structure */
struct bt_gatt_service {
    /** Service Attributes */
    struct bt_gatt_attr *attrs;
    /** Service Attribute count */
    size_t attr_count;
    sys_snode_t node;
};

/** @brief Service Attribute Value. */
struct bt_gatt_service_val {
    /** Service UUID. */
    const struct bt_uuid *uuid;
    /** Service end handle. */
    u16_t end_handle;
};

/** @brief Include Attribute Value. */
struct bt_gatt_include {
    /** Service UUID. */
    const struct bt_uuid *uuid;
    /** Service start handle. */
    u16_t start_handle;
    /** Service end handle. */
    u16_t end_handle;
};

/* Characteristic Properties Bit field values */

/** @def BT_GATT_CHRC_BROADCAST
 *  @brief Characteristic broadcast property.
 *
 *  If set, permits broadcasts of the Characteristic Value using Server
 *  Characteristic Configuration Descriptor.
 */
#define BT_GATT_CHRC_BROADCAST 0x01
/** @def BT_GATT_CHRC_READ
 *  @brief Characteristic read property.
 *
 *  If set, permits reads of the Characteristic Value.
 */
#define BT_GATT_CHRC_READ 0x02
/** @def BT_GATT_CHRC_WRITE_WITHOUT_RESP
 *  @brief Characteristic write without response property.
 *
 *  If set, permits write of the Characteristic Value without response.
 */
#define BT_GATT_CHRC_WRITE_WITHOUT_RESP 0x04
/** @def BT_GATT_CHRC_WRITE
 *  @brief Characteristic write with response property.
 *
 *  If set, permits write of the Characteristic Value with response.
 */
#define BT_GATT_CHRC_WRITE 0x08
/** @def BT_GATT_CHRC_NOTIFY
 *  @brief Characteristic notify property.
 *
 *  If set, permits notifications of a Characteristic Value without
 *  acknowledgment.
 */
#define BT_GATT_CHRC_NOTIFY 0x10
/** @def BT_GATT_CHRC_INDICATE
 *  @brief Characteristic indicate property.
 *
 * If set, permits indications of a Characteristic Value with acknowledgment.
 */
#define BT_GATT_CHRC_INDICATE 0x20
/** @def BT_GATT_CHRC_AUTH
 *  @brief Characteristic Authenticated Signed Writes property.
 *
 *  If set, permits signed writes to the Characteristic Value.
 */
#define BT_GATT_CHRC_AUTH 0x40
/** @def BT_GATT_CHRC_EXT_PROP
 *  @brief Characteristic Extended Properties property.
 *
 * If set, additional characteristic properties are defined in the
 * Characteristic Extended Properties Descriptor.
 */
#define BT_GATT_CHRC_EXT_PROP 0x80

/** @brief Characteristic Attribute Value. */
struct bt_gatt_chrc {
    /** Characteristic UUID. */
    const struct bt_uuid *uuid;
    /** Characteristic Value handle. */
    u16_t value_handle;
    /** Characteristic properties. */
    u8_t properties;
};

/* Characteristic Extended Properties Bit field values */
#define BT_GATT_CEP_RELIABLE_WRITE 0x0001
#define BT_GATT_CEP_WRITABLE_AUX   0x0002

/** @brief Characteristic Extended Properties Attribute Value. */
struct bt_gatt_cep {
    /** Characteristic Extended properties */
    u16_t properties;
};

/* Client Characteristic Configuration Values */

/** @def BT_GATT_CCC_NOTIFY
 *  @brief Client Characteristic Configuration Notification.
 *
 *  If set, changes to Characteristic Value shall be notified.
 */
#define BT_GATT_CCC_NOTIFY 0x0001
/** @def BT_GATT_CCC_INDICATE
 *  @brief Client Characteristic Configuration Indication.
 *
 *  If set, changes to Characteristic Value shall be indicated.
 */
#define BT_GATT_CCC_INDICATE 0x0002

/* Client Characteristic Configuration Attribute Value */
struct bt_gatt_ccc {
    /** Client Characteristic Configuration flags */
    u16_t flags;
};

/** @brief GATT Characteristic Presentation Format Attribute Value. */
struct bt_gatt_cpf {
    /** Format of the value of the characteristic */
    u8_t format;
    /** Exponent field to determine how the value of this characteristic is
	 * further formatted
	 */
    s8_t exponent;
    /** Unit of the characteristic */
    u16_t unit;
    /** Name space of the description */
    u8_t name_space;
    /** Description of the characteristic as defined in a higher layer profile */
    u16_t description;
} __packed;

/**
 * @defgroup bt_gatt_server GATT Server APIs
 * @ingroup bt_gatt
 * @{
 */

/** @brief Register GATT service.
 *
 *  Register GATT service. Applications can make use of
 *  macros such as BT_GATT_PRIMARY_SERVICE, BT_GATT_CHARACTERISTIC,
 *  BT_GATT_DESCRIPTOR, etc.
 *
 *  @param svc Service containing the available attributes
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_service_register(struct bt_gatt_service *svc);

/** @brief Unregister GATT service.
 * *
 *  @param svc Service to be unregistered.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_service_unregister(struct bt_gatt_service *svc);

enum {
    BT_GATT_ITER_STOP = 0,
    BT_GATT_ITER_CONTINUE,
};

/** @typedef bt_gatt_attr_func_t
 *  @brief Attribute iterator callback.
 *
 *  @param attr Attribute found.
 *  @param user_data Data given.
 *
 *  @return BT_GATT_ITER_CONTINUE if should continue to the next attribute
 *  or BT_GATT_ITER_STOP to stop.
 */
typedef u8_t (*bt_gatt_attr_func_t)(const struct bt_gatt_attr *attr,
                                    void *user_data);

/** @brief Attribute iterator by type.
 *
 *  Iterate attributes in the given range matching given UUID and/or data.
 *
 *  @param start_handle Start handle.
 *  @param end_handle End handle.
 *  @param uuid UUID to match, passing NULL skips UUID matching.
 *  @param attr_data Attribute data to match, passing NULL skips data matching.
 *  @param num_matches Number matches, passing 0 makes it unlimited.
 *  @param func Callback function.
 *  @param user_data Data to pass to the callback.
 */
void bt_gatt_foreach_attr_type(u16_t start_handle, u16_t end_handle,
                               const struct bt_uuid *uuid,
                               const void *attr_data, uint16_t num_matches,
                               bt_gatt_attr_func_t func,
                               void *user_data);

/** @brief Attribute iterator.
 *
 *  Iterate attributes in the given range.
 *
 *  @param start_handle Start handle.
 *  @param end_handle End handle.
 *  @param func Callback function.
 *  @param user_data Data to pass to the callback.
 */
static inline void bt_gatt_foreach_attr(u16_t start_handle, u16_t end_handle,
                                        bt_gatt_attr_func_t func,
                                        void *user_data)
{
    bt_gatt_foreach_attr_type(start_handle, end_handle, NULL, NULL, 0, func,
                              user_data);
}

/** @brief Iterate to the next attribute
 *
 *  Iterate to the next attribute following a given attribute.
 *
 *  @param attr Current Attribute.
 *
 *  @return The next attribute or NULL if it cannot be found.
 */
struct bt_gatt_attr *bt_gatt_attr_next(const struct bt_gatt_attr *attr);

/** @brief Get the handle of the characteristic value descriptor.
 *
 * @param attr A Characteristic Attribute
 *
 * @return the handle of the corresponding Characteristic Value.  The
 * value will be zero (the invalid handle) if @p attr was not a
 * characteristic attribute.
 */
uint16_t bt_gatt_attr_value_handle(const struct bt_gatt_attr *attr);

/** @brief Generic Read Attribute value helper.
 *
 *  Read attribute value from local database storing the result into buffer.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value.
 *  @param buf_len Buffer length.
 *  @param offset Start offset.
 *  @param value Attribute value.
 *  @param value_len Length of the attribute value.
 *
 *  @return int number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read(struct bt_conn *conn, const struct bt_gatt_attr *attr,
                          void *buf, u16_t buf_len, u16_t offset,
                          const void *value, u16_t value_len);

/** @brief Read Service Attribute helper.
 *
 *  Read service attribute value from local database storing the result into
 *  buffer after encoding it.
 *  NOTE: Only use this with attributes which user_data is a bt_uuid.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value read.
 *  @param len Buffer length.
 *  @param offset Start offset.
 *
 *  @return int number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_service(struct bt_conn *conn,
                                  const struct bt_gatt_attr *attr,
                                  void *buf, u16_t len, u16_t offset);

/** @def BT_GATT_SERVICE_DEFINE
 *  @brief Statically define and register a service.
 *
 *  Helper macro to statically define and register a service.
 *
 *  @param _name Service name.
 */
#define BT_GATT_SERVICE_DEFINE(_name, ...)                           \
    const struct bt_gatt_attr attr_##_name[] = { __VA_ARGS__ };      \
    const Z_STRUCT_SECTION_ITERABLE(bt_gatt_service_static, _name) = \
        BT_GATT_SERVICE(attr_##_name)

/** @def BT_GATT_SERVICE
 *  @brief Service Structure Declaration Macro.
 *
 *  Helper macro to declare a service structure.
 *
 *  @param _attrs Service attributes.
 */
#define BT_GATT_SERVICE(_attrs)           \
    {                                     \
        .attrs = _attrs,                  \
        .attr_count = ARRAY_SIZE(_attrs), \
    }

/** @def BT_GATT_PRIMARY_SERVICE
 *  @brief Primary Service Declaration Macro.
 *
 *  Helper macro to declare a primary service attribute.
 *
 *  @param _service Service attribute value.
 */
#define BT_GATT_PRIMARY_SERVICE(_service)                      \
    BT_GATT_ATTRIBUTE(BT_UUID_GATT_PRIMARY, BT_GATT_PERM_READ, \
                      bt_gatt_attr_read_service, NULL, _service)

/** @def BT_GATT_SECONDARY_SERVICE
 *  @brief Secondary Service Declaration Macro.
 *
 *  Helper macro to declare a secondary service attribute.
 *
 *  @param _service Service attribute value.
 */
#define BT_GATT_SECONDARY_SERVICE(_service)                      \
    BT_GATT_ATTRIBUTE(BT_UUID_GATT_SECONDARY, BT_GATT_PERM_READ, \
                      bt_gatt_attr_read_service, NULL, _service)

/** @brief Read Include Attribute helper.
 *
 *  Read include service attribute value from local database storing the result
 *  into buffer after encoding it.
 *  NOTE: Only use this with attributes which user_data is a bt_gatt_include.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value read.
 *  @param len Buffer length.
 *  @param offset Start offset.
 *
 *  @return int number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_included(struct bt_conn *conn,
                                   const struct bt_gatt_attr *attr,
                                   void *buf, u16_t len, u16_t offset);

/** @def BT_GATT_INCLUDE_SERVICE
 *  @brief Include Service Declaration Macro.
 *
 *  Helper macro to declare database internal include service attribute.
 *
 *  @param _service_incl the first service attribute of service to include
 */
#define BT_GATT_INCLUDE_SERVICE(_service_incl)                 \
    BT_GATT_ATTRIBUTE(BT_UUID_GATT_INCLUDE, BT_GATT_PERM_READ, \
                      bt_gatt_attr_read_included, NULL, _service_incl)

/** @brief Read Characteristic Attribute helper.
 *
 *  Read characteristic attribute value from local database storing the result
 *  into buffer after encoding it.
 *  NOTE: Only use this with attributes which user_data is a bt_gatt_chrc.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value read.
 *  @param len Buffer length.
 *  @param offset Start offset.
 *
 *  @return number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_chrc(struct bt_conn *conn,
                               const struct bt_gatt_attr *attr, void *buf,
                               u16_t len, u16_t offset);

#define BT_GATT_CHRC_INIT(_uuid, _handle, _props) \
    {                                             \
        .uuid = _uuid,                            \
        .value_handle = _handle,                  \
        .properties = _props,                     \
    }

/** @def BT_GATT_CHARACTERISTIC
 *  @brief Characteristic and Value Declaration Macro.
 *
 *  Helper macro to declare a characteristic attribute along with its
 *  attribute value.
 *
 *  @param _uuid Characteristic attribute uuid.
 *  @param _props Characteristic attribute properties.
 *  @param _perm Characteristic Attribute access permissions.
 *  @param _read Characteristic Attribute read callback.
 *  @param _write Characteristic Attribute write callback.
 *  @param _value Characteristic Attribute value.
 */
#define BT_GATT_CHARACTERISTIC(_uuid, _props, _perm, _read, _write, _value) \
    BT_GATT_ATTRIBUTE(BT_UUID_GATT_CHRC, BT_GATT_PERM_READ,                 \
                      bt_gatt_attr_read_chrc, NULL,                         \
                      ((struct bt_gatt_chrc[]){                             \
                          BT_GATT_CHRC_INIT(_uuid, 0U, _props),             \
                      })),                                                  \
        BT_GATT_ATTRIBUTE(_uuid, _perm, _read, _write, _value)

#if IS_ENABLED(CONFIG_BT_SETTINGS_CCC_LAZY_LOADING)
#define BT_GATT_CCC_MAX (CONFIG_BT_MAX_CONN)
#else
#define BT_GATT_CCC_MAX (CONFIG_BT_MAX_PAIRED + CONFIG_BT_MAX_CONN)
#endif

/** @brief GATT CCC configuration entry.
 *  @param id   Local identity, BT_ID_DEFAULT in most cases.
 *  @param peer Remote peer address
 *  @param value Configuration value.
 *  @param data Configuration pointer data.
 */
struct bt_gatt_ccc_cfg {
    u8_t id;
    bt_addr_le_t peer;
    u16_t value;
};

/* Internal representation of CCC value */
struct _bt_gatt_ccc {
    struct bt_gatt_ccc_cfg cfg[BT_GATT_CCC_MAX];
    u16_t value;
    void (*cfg_changed)(const struct bt_gatt_attr *attr,
                        u16_t value);
    bool (*cfg_write)(struct bt_conn *conn,
                      const struct bt_gatt_attr *attr,
                      u16_t value);
    bool (*cfg_match)(struct bt_conn *conn,
                      const struct bt_gatt_attr *attr);
};

/** @brief Read Client Characteristic Configuration Attribute helper.
 *
 *  Read CCC attribute value from local database storing the result into buffer
 *  after encoding it.
 *  NOTE: Only use this with attributes which user_data is a _bt_gatt_ccc.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value read.
 *  @param len Buffer length.
 *  @param offset Start offset.
 *
 *  @return number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn,
                              const struct bt_gatt_attr *attr, void *buf,
                              u16_t len, u16_t offset);

/** @brief Write Client Characteristic Configuration Attribute helper.
 *
 *  Write value in the buffer into CCC attribute.
 *  NOTE: Only use this with attributes which user_data is a _bt_gatt_ccc.
 *
 *  @param conn Connection object.
 *  @param attr Attribute to read.
 *  @param buf Buffer to store the value read.
 *  @param len Buffer length.
 *  @param offset Start offset.
 *  @param flags Write flags.
 *
 *  @return number of bytes written in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
                               const struct bt_gatt_attr *attr, const void *buf,
                               u16_t len, u16_t offset, u8_t flags);

/** @def BT_GATT_CCC_INITIALIZER
 *  @brief Initialize Client Characteristic Configuration Declaration Macro.
 *
 *  Helper macro to initialize a Managed CCC attribute value.
 *
 *  @param _changed Configuration changed callback.
 *  @param _write Configuration write callback.
 *  @param _match Configuration match callback.
 */
#define BT_GATT_CCC_INITIALIZER(_changed, _write, _match) \
    {                                                     \
        .cfg = {},                                        \
        .cfg_changed = _changed,                          \
        .cfg_write = _write,                              \
        .cfg_match = _match,                              \
    }

/** @def BT_GATT_CCC_MANAGED
 *  @brief Managed Client Characteristic Configuration Declaration Macro.
 *
 *  Helper macro to declare a Managed CCC attribute.
 *
 *  @param _ccc CCC attribute user data, shall point to a _bt_gatt_ccc.
 *  @param _perm CCC access permissions.
 */
#define BT_GATT_CCC_MANAGED(_ccc, _perm)                             \
    BT_GATT_ATTRIBUTE(BT_UUID_GATT_CCC, _perm,                       \
                      bt_gatt_attr_read_ccc, bt_gatt_attr_write_ccc, \
                      _ccc)

/** @def BT_GATT_CCC
 *  @brief Client Characteristic Configuration Declaration Macro.
 *
 *  Helper macro to declare a CCC attribute.
 *
 *  @param _changed Configuration changed callback.
 *  @param _perm CCC access permissions.
 */
#define BT_GATT_CCC(_changed, _perm)                                         \
    BT_GATT_CCC_MANAGED((&(struct _bt_gatt_ccc)                              \
                             BT_GATT_CCC_INITIALIZER(_changed, NULL, NULL)), \
                        _perm)

/** @brief Read Characteristic Extended Properties Attribute helper
 *
 *  Read CEP attribute value from local database storing the result into buffer
 *  after encoding it.
 *  NOTE: Only use this with attributes which user_data is a bt_gatt_cep.
 *
 *  @param conn Connection object
 *  @param attr Attribute to read
 *  @param buf Buffer to store the value read
 *  @param len Buffer length
 *  @param offset Start offset
 *
 *  @return number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_cep(struct bt_conn *conn,
                              const struct bt_gatt_attr *attr, void *buf,
                              u16_t len, u16_t offset);

/** @def BT_GATT_CEP
 *  @brief Characteristic Extended Properties Declaration Macro.
 *
 *  Helper macro to declare a CEP attribute.
 *
 *  @param _value Descriptor attribute value.
 */
#define BT_GATT_CEP(_value)                                 \
    BT_GATT_DESCRIPTOR(BT_UUID_GATT_CEP, BT_GATT_PERM_READ, \
                       bt_gatt_attr_read_cep, NULL, (void *)_value)

/** @brief Read Characteristic User Description Descriptor Attribute helper
 *
 *  Read CUD attribute value from local database storing the result into buffer
 *  after encoding it.
 *  NOTE: Only use this with attributes which user_data is a NULL-terminated C
 *  string.
 *
 *  @param conn Connection object
 *  @param attr Attribute to read
 *  @param buf Buffer to store the value read
 *  @param len Buffer length
 *  @param offset Start offset
 *
 *  @return number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_cud(struct bt_conn *conn,
                              const struct bt_gatt_attr *attr, void *buf,
                              u16_t len, u16_t offset);

/** @def BT_GATT_CUD
 *  @brief Characteristic User Format Descriptor Declaration Macro.
 *
 *  Helper macro to declare a CUD attribute.
 *
 *  @param _value User description NULL-terminated C string.
 *  @param _perm Descriptor attribute access permissions.
 */
#define BT_GATT_CUD(_value, _perm)                                     \
    BT_GATT_DESCRIPTOR(BT_UUID_GATT_CUD, _perm, bt_gatt_attr_read_cud, \
                       NULL, (void *)_value)

/** @brief Read Characteristic Presentation format Descriptor Attribute helper
 *
 *  Read CPF attribute value from local database storing the result into buffer
 *  after encoding it.
 *  NOTE: Only use this with attributes which user_data is a bt_gatt_pf.
 *
 *  @param conn Connection object
 *  @param attr Attribute to read
 *  @param buf Buffer to store the value read
 *  @param len Buffer length
 *  @param offset Start offset
 *
 *  @return number of bytes read in case of success or negative values in
 *  case of error.
 */
ssize_t bt_gatt_attr_read_cpf(struct bt_conn *conn,
                              const struct bt_gatt_attr *attr, void *buf,
                              u16_t len, u16_t offset);

/** @def BT_GATT_CPF
 *  @brief Characteristic Presentation Format Descriptor Declaration Macro.
 *
 *  Helper macro to declare a CPF attribute.
 *
 *  @param _value Descriptor attribute value.
 */
#define BT_GATT_CPF(_value)                                 \
    BT_GATT_DESCRIPTOR(BT_UUID_GATT_CPF, BT_GATT_PERM_READ, \
                       bt_gatt_attr_read_cpf, NULL, (void *)_value)

/** @def BT_GATT_DESCRIPTOR
 *  @brief Descriptor Declaration Macro.
 *
 *  Helper macro to declare a descriptor attribute.
 *
 *  @param _uuid Descriptor attribute uuid.
 *  @param _perm Descriptor attribute access permissions.
 *  @param _read Descriptor attribute read callback.
 *  @param _write Descriptor attribute write callback.
 *  @param _value Descriptor attribute value.
 */
#define BT_GATT_DESCRIPTOR(_uuid, _perm, _read, _write, _value) \
    BT_GATT_ATTRIBUTE(_uuid, _perm, _read, _write, _value)

/** @def BT_GATT_ATTRIBUTE
 *  @brief Attribute Declaration Macro.
 *
 *  Helper macro to declare an attribute.
 *
 *  @param _uuid Attribute uuid.
 *  @param _perm Attribute access permissions.
 *  @param _read Attribute read callback.
 *  @param _write Attribute write callback.
 *  @param _value Attribute value.
 */
#define BT_GATT_ATTRIBUTE(_uuid, _perm, _read, _write, _value) \
    {                                                          \
        .uuid = _uuid,                                         \
        .read = _read,                                         \
        .write = _write,                                       \
        .user_data = _value,                                   \
        .handle = 0,                                           \
        .perm = _perm,                                         \
    }

/** @brief Notification complete result callback.
 *
 *  @param conn Connection object.
 */
typedef void (*bt_gatt_complete_func_t)(struct bt_conn *conn, void *user_data);

struct bt_gatt_notify_params {
    /** Notification Attribute UUID type */
    const struct bt_uuid *uuid;
    /** Notification Attribute object*/
    const struct bt_gatt_attr *attr;
    /** Notification Value data */
    const void *data;
    /** Notification Value length */
    u16_t len;
    /** Notification Value callback */
    bt_gatt_complete_func_t func;
    /** Notification Value callback user data */
    void *user_data;
};
#if defined(CONFIG_BLE_AT_CMD)
int bt_gatt_notify_at_cb(struct bt_conn *conn, struct bt_gatt_notify_params *params, u16_t attr_handle);
#endif

/** @brief Notify attribute value change.
 *
 *  This function works in the same way as @ref bt_gatt_notify.
 *  With the addition that after sending the notification the
 *  callback function will be called.
 *
 *  The callback is run from System Workqueue context.
 *
 *  Alternatively it is possible to notify by UUID by setting it on the
 *  parameters, when using this method the attribute given is used as the
 *  start range when looking up for possible matches.
 *
 *  @param conn Connection object.
 *  @param params Notification parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_notify_cb(struct bt_conn *conn,
                      struct bt_gatt_notify_params *params);

/** @brief Notify attribute value change.
 *
 *  Send notification of attribute value change, if connection is NULL notify
 *  all peer that have notification enabled via CCC otherwise do a direct
 *  notification only the given connection.
 *
 *  The attribute object on the parameters can be the so called Characteristic
 *  Declaration, which is usually declared with BT_GATT_CHARACTERISTIC followed
 *  by BT_GATT_CCC, or the Characteristic Value Declaration which is
 *  automatically created after the Characteristic Declaration when using
 *  BT_GATT_CHARACTERISTIC.
 *
 *  @param conn Connection object.
 *  @param attr Characteristic or Characteristic Value attribute.
 *  @param data Pointer to Attribute data.
 *  @param len Attribute value length.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
static inline int bt_gatt_notify(struct bt_conn *conn,
                                 const struct bt_gatt_attr *attr,
                                 const void *data, u16_t len)
{
    struct bt_gatt_notify_params params;

    memset(¶ms, 0, sizeof(params));

    params.attr = attr;
    params.data = data;
    params.len = len;

    return bt_gatt_notify_cb(conn, ¶ms);
}

/** @typedef bt_gatt_indicate_func_t
 *  @brief Indication complete result callback.
 *
 *  @param conn Connection object.
 *  @param attr Attribute object.
 *  @param err ATT error code
 *
 *  @return 0 in case of success or negative value in case of error.
 */
typedef void (*bt_gatt_indicate_func_t)(struct bt_conn *conn,
                                        const struct bt_gatt_attr *attr,
                                        u8_t err);

/** @brief GATT Indicate Value parameters */
struct bt_gatt_indicate_params {
    struct bt_att_req _req;
    /** Notification Attribute UUID type */
    const struct bt_uuid *uuid;
    /** Indicate Attribute object*/
    const struct bt_gatt_attr *attr;
    /** Indicate Value callback */
    bt_gatt_indicate_func_t func;
    /** Indicate Value data*/
    const void *data;
    /** Indicate Value length*/
    u16_t len;
};

/** @brief Indicate attribute value change.
 *
 *  Send an indication of attribute value change. if connection is NULL
 *  indicate all peer that have notification enabled via CCC otherwise do a
 *  direct indication only the given connection.
 *
 *  The attribute object on the parameters can be the so called Characteristic
 *  Declaration, which is usually declared with BT_GATT_CHARACTERISTIC followed
 *  by BT_GATT_CCC, or the Characteristic Value Declaration which is
 *  automatically created after the Characteristic Declaration when using
 *  BT_GATT_CHARACTERISTIC.
 *
 *  The callback is run from System Workqueue context.
 *
 *  Alternatively it is possible to indicate by UUID by setting it on the
 *  parameters, when using this method the attribute given is used as the
 *  start range when looking up for possible matches.
 *
 *  Note: This procedure is asynchronous therefore the parameters need to
 *  remains valid while it is active.
 *
 *  @param conn Connection object.
 *  @param params Indicate parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_indicate(struct bt_conn *conn,
                     struct bt_gatt_indicate_params *params);

#if defined(CONFIG_BT_STACK_PTS)
int service_change_test(struct bt_gatt_indicate_params *params, const struct bt_conn *con);

#endif
/** @brief Check if connection have subscribed to attribute
 *
 *  Check if connection has subscribed to attribute value change.
 *
 *  The attribute object can be the so called Characteristic Declaration,
 *  which is usually declared with BT_GATT_CHARACTERISTIC followed
 *  by BT_GATT_CCC, or the Characteristic Value Declaration which is
 *  automatically created after the Characteristic Declaration when using
 *  BT_GATT_CHARACTERISTIC, or the Client Characteristic Configuration
 *  Descriptor (CCCD) which is created by BT_GATT_CCC.
 *
 *  @param conn Connection object.
 *  @param attr Attribute object.
 *  @param ccc_value The subscription type, either notifications or indications.
 *
 *  @return true if the attribute object has been subscribed.
 */
bool bt_gatt_is_subscribed(struct bt_conn *conn,
                           const struct bt_gatt_attr *attr, u16_t ccc_value);

/** @brief Get ATT MTU for a connection
 *
 *  Get negotiated ATT connection MTU, note that this does not equal the largest
 *  amount of attribute data that can be transferred within a single packet.
 *
 *  @param conn Connection object.
 *
 *  @return MTU in bytes
 */
u16_t bt_gatt_get_mtu(struct bt_conn *conn);

/** @} */

/**
 * @defgroup bt_gatt_client GATT Client APIs
 * @ingroup bt_gatt
 * @{
 */

/** @brief GATT Exchange MTU parameters */
struct bt_gatt_exchange_params {
    struct bt_att_req _req;
    /** Response callback */
    void (*func)(struct bt_conn *conn, u8_t err,
                 struct bt_gatt_exchange_params *params);
};

/** @brief Exchange MTU
 *
 *  This client procedure can be used to set the MTU to the maximum possible
 *  size the buffers can hold.
 *
 *  NOTE: Shall only be used once per connection.
 *
 *  @param conn Connection object.
 *  @param params Exchange MTU parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_exchange_mtu(struct bt_conn *conn,
                         struct bt_gatt_exchange_params *params);

#if defined(CONFIG_BLE_AT_CMD)
int bt_at_gatt_exchange_mtu(struct bt_conn *conn, struct bt_gatt_exchange_params *params, u16_t mtu_size);
#endif

struct bt_gatt_discover_params;

/** @typedef bt_gatt_discover_func_t
 *  @brief Discover attribute callback function.
 *
 *  @param conn Connection object.
 *  @param attr Attribute found.
 *  @param params Discovery parameters given.
 *
 *  If discovery procedure has completed this callback will be called with
 *  attr set to NULL. This will not happen if procedure was stopped by returning
 *  BT_GATT_ITER_STOP. The attribute is read-only and cannot be cached without
 *  copying its contents.
 *
 *  @return BT_GATT_ITER_CONTINUE if should continue attribute discovery
 *  or BT_GATT_ITER_STOP to stop discovery procedure.
 */
typedef u8_t (*bt_gatt_discover_func_t)(struct bt_conn *conn,
                                        const struct bt_gatt_attr *attr,
                                        struct bt_gatt_discover_params *params);

/* GATT Discover types */
enum {
    /** Discover Primary Services. */
    BT_GATT_DISCOVER_PRIMARY,
    /** Discover Secondary Services. */
    BT_GATT_DISCOVER_SECONDARY,
    /** Discover Included Services. */
    BT_GATT_DISCOVER_INCLUDE,
    /** Discover Characteristic Values.
	 *
	 *  Discover Characteristic Value and its properties.
	 */
    BT_GATT_DISCOVER_CHARACTERISTIC,
    /** Discover Descriptors.
	 *
	 *  Discover Attributes which are not services or characteristics.
	 *
	 *  Note: The use of this type of discover is not recommended for
	 *  discovering in ranges across multiple services/characteristics
	 *  as it may incur in extra round trips.
	 */
    BT_GATT_DISCOVER_DESCRIPTOR,
    /** Discover Attributes.
	 *
	 *  Discover Attributes of any type.
	 *
	 *  Note: The use of this type of discover is not recommended for
	 *  discovering in ranges across multiple services/characteristics as
	 *  it may incur in more round trips.
	 */
    BT_GATT_DISCOVER_ATTRIBUTE,
};

/** @brief GATT Discover Attributes parameters */
struct bt_gatt_discover_params {
    struct bt_att_req _req;
    /** Discover UUID type */
    struct bt_uuid *uuid;
    /** Discover attribute callback */
    bt_gatt_discover_func_t func;
    union {
        struct {
            /** Include service attribute declaration handle */
            u16_t attr_handle;
            /** Included service start handle */
            u16_t start_handle;
            /** Included service end handle */
            u16_t end_handle;
        } _included;
        /** Discover start handle */
        u16_t start_handle;
    };
    /** Discover end handle */
    u16_t end_handle;
    /** Discover type */
    u8_t type;
};

/** @brief GATT Discover function
 *
 *  This procedure is used by a client to discover attributes on a server.
 *
 *  Primary Service Discovery: Procedure allows to discover specific Primary
 *                             Service based on UUID.
 *  Include Service Discovery: Procedure allows to discover all Include Services
 *                             within specified range.
 *  Characteristic Discovery:  Procedure allows to discover all characteristics
 *                             within specified handle range as well as
 *                             discover characteristics with specified UUID.
 *  Descriptors Discovery:     Procedure allows to discover all characteristic
 *                             descriptors within specified range.
 *
 *  For each attribute found the callback is called which can then decide
 *  whether to continue discovering or stop.
 *
 *  Note: This procedure is asynchronous therefore the parameters need to
 *  remains valid while it is active.
 *
 *  @param conn Connection object.
 *  @param params Discover parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_discover(struct bt_conn *conn,
                     struct bt_gatt_discover_params *params);

struct bt_gatt_read_params;

/** @typedef bt_gatt_read_func_t
 *  @brief Read callback function
 *
 *  @param conn Connection object.
 *  @param err ATT error code.
 *  @param params Read parameters used.
 *  @param data Attribute value data. NULL means read has completed.
 *  @param length Attribute value length.
 */
typedef u8_t (*bt_gatt_read_func_t)(struct bt_conn *conn, u8_t err,
                                    struct bt_gatt_read_params *params,
                                    const void *data, u16_t length);

/** @brief GATT Read parameters
 *  @param func Read attribute callback
 *  @param handle_count If equals to 1 single.handle and single.offset
 *                      are used.  If >1 Read Multiple Characteristic
 *                      Values is performed and handles are used.
 *                      If equals to 0 by_uuid is used for Read Using
 *                      Characteristic UUID.
 *  @param handle Attribute handle
 *  @param offset Attribute data offset
 *  @param handles Handles to read in Read Multiple Characteristic Values
 *  @param start_handle First requested handle number
 *  @param end_handle Last requested handle number
 *  @param uuid 2 or 16 octet UUID
 */
struct bt_gatt_read_params {
    struct bt_att_req _req;
    bt_gatt_read_func_t func;
    size_t handle_count;
    union {
        struct {
            u16_t handle;
            u16_t offset;
        } single;
        u16_t *handles;
        struct {
            u16_t start_handle;
            u16_t end_handle;
            struct bt_uuid *uuid;
        } by_uuid;
    };
};

/** @brief Read Attribute Value by handle
 *
 *  This procedure read the attribute value and return it to the callback.
 *
 *  When reading attributes by UUID the callback can be called multiple times
 *  depending on how many instances of given the UUID exists with the
 *  start_handle being updated for each instance.
 *
 *  If an instance does contain a long value which cannot be read entirely the
 *  caller will need to read the remaining data separately using the handle and
 *  offset.
 *
 *  Note: This procedure is asynchronous therefore the parameters need to
 *  remains valid while it is active.
 *
 *  @param conn Connection object.
 *  @param params Read parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_read(struct bt_conn *conn, struct bt_gatt_read_params *params);

struct bt_gatt_write_params;

/** @typedef bt_gatt_write_func_t
 *  @brief Write callback function
 *
 *  @param conn Connection object.
 *  @param err ATT error code.
 *  @param params Write parameters used.
 */
typedef void (*bt_gatt_write_func_t)(struct bt_conn *conn, u8_t err,
                                     struct bt_gatt_write_params *params);

/** @brief GATT Write parameters */
struct bt_gatt_write_params {
    struct bt_att_req _req;
    /** Response callback */
    bt_gatt_write_func_t func;
    /** Attribute handle */
    u16_t handle;
    /** Attribute data offset */
    u16_t offset;
    /** Data to be written */
    const void *data;
    /** Length of the data */
    u16_t length;
};

/** @brief Write Attribute Value by handle
 *
 * This procedure write the attribute value and return the result in the
 * callback.
 *
 * Note: This procedure is asynchronous therefore the parameters need to
 *  remains valid while it is active.
 *
 * @param conn Connection object.
 * @param params Write parameters.
 *
 * @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_write(struct bt_conn *conn, struct bt_gatt_write_params *params);

#if defined(CONFIG_BT_STACK_PTS)
int bt_gatt_prepare_write(struct bt_conn *conn,
                          struct bt_gatt_write_params *params);

#endif

/** @brief Write Attribute Value by handle without response with callback.
 *
 * This function works in the same way as @ref bt_gatt_write_without_response.
 * With the addition that after sending the write the callback function will be
 * called.
 *
 * The callback is run from System Workqueue context.
 *
 * Note: By using a callback it also disable the internal flow control
 * which would prevent sending multiple commands without waiting for their
 * transmissions to complete, so if that is required the caller shall not
 * submit more data until the callback is called.
 *
 * @param conn Connection object.
 * @param handle Attribute handle.
 * @param data Data to be written.
 * @param length Data length.
 * @param sign Whether to sign data
 * @param func Transmission complete callback.
 * @param user_data User data to be passed back to callback.
 *
 * @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_write_without_response_cb(struct bt_conn *conn, u16_t handle,
                                      const void *data, u16_t length,
                                      bool sign, bt_gatt_complete_func_t func,
                                      void *user_data);

/** @brief Write Attribute Value by handle without response
 *
 * This procedure write the attribute value without requiring an
 * acknowledgment that the write was successfully performed
 *
 * @param conn Connection object.
 * @param handle Attribute handle.
 * @param data Data to be written.
 * @param length Data length.
 * @param sign Whether to sign data
 *
 * @return 0 in case of success or negative value in case of error.
 */
static inline int bt_gatt_write_without_response(struct bt_conn *conn,
                                                 u16_t handle, const void *data,
                                                 u16_t length, bool sign)
{
    return bt_gatt_write_without_response_cb(conn, handle, data, length,
                                             sign, NULL, NULL);
}

struct bt_gatt_subscribe_params;

/** @typedef bt_gatt_notify_func_t
 *  @brief Notification callback function
 *
 *  @param conn Connection object. May be NULL, indicating that the peer is
 *              being unpaired
 *  @param params Subscription parameters.
 *  @param data Attribute value data. If NULL then subscription was removed.
 *  @param length Attribute value length.
 */
typedef u8_t (*bt_gatt_notify_func_t)(struct bt_conn *conn,
                                      struct bt_gatt_subscribe_params *params,
                                      const void *data, u16_t length);

/* Subscription flags */
enum {
    /** Persistence flag
	 *
	 * If set, indicates that the subscription is not saved
	 * on the GATT server side. Therefore, upon disconnection,
	 * the subscription will be automatically removed
	 * from the client's subscriptions list and
	 * when the client reconnects, it will have to
	 * issue a new subscription.
	 */
    BT_GATT_SUBSCRIBE_FLAG_VOLATILE,

    /** Write pending flag
	 *
	 * If set, indicates write operation is pending waiting remote end to
	 * respond.
	 */
    BT_GATT_SUBSCRIBE_FLAG_WRITE_PENDING,

    BT_GATT_SUBSCRIBE_NUM_FLAGS
};

/** @brief GATT Subscribe parameters */
struct bt_gatt_subscribe_params {
    struct bt_att_req _req;
    bt_addr_le_t _peer;
    /** Notification value callback */
    bt_gatt_notify_func_t notify;
    /** Subscribe value handle */
    u16_t value_handle;
    /** Subscribe CCC handle */
    u16_t ccc_handle;
    /** Subscribe value */
    u16_t value;
    /** Subscription flags */
    ATOMIC_DEFINE(flags, BT_GATT_SUBSCRIBE_NUM_FLAGS);

    sys_snode_t node;
};

/** @brief Subscribe Attribute Value Notification
 *
 *  This procedure subscribe to value notification using the Client
 *  Characteristic Configuration handle.
 *  If notification received subscribe value callback is called to return
 *  notified value. One may then decide whether to unsubscribe directly from
 *  this callback. Notification callback with NULL data will not be called if
 *  subscription was removed by this method.
 *
 *  Note: This procedure is asynchronous therefore the parameters need to
 *  remains valid while it is active.
 *
 *  @param conn Connection object.
 *  @param params Subscribe parameters.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_subscribe(struct bt_conn *conn,
                      struct bt_gatt_subscribe_params *params);

/** @brief Unsubscribe Attribute Value Notification
 *
 * This procedure unsubscribe to value notification using the Client
 * Characteristic Configuration handle. Notification callback with NULL data
 * will be called if subscription was removed by this call, until then the
 * parameters cannot be reused.
 *
 * @param conn Connection object.
 * @param params Subscribe parameters.
 *
 * @return 0 in case of success or negative value in case of error.
 */
int bt_gatt_unsubscribe(struct bt_conn *conn,
                        struct bt_gatt_subscribe_params *params);

/** @brief Cancel GATT pending request
 *
 *  @param conn Connection object.
 *  @param params Requested params address.
 */
void bt_gatt_cancel(struct bt_conn *conn, void *params);

#if defined(BFLB_BLE_MTU_CHANGE_CB)
typedef void (*bt_gatt_mtu_changed_cb_t)(struct bt_conn *conn, int mtu);
void bt_gatt_register_mtu_callback(bt_gatt_mtu_changed_cb_t cb);
#endif
#if defined(CONFIG_BT_GATT_CLIENT)
#if defined(BFLB_BLE_NOTIFY_ALL)
typedef void (*bt_notification_all_cb_t)(struct bt_conn *conn, u16_t handle, const void *data, u16_t length);
void bt_gatt_register_notification_callback(bt_notification_all_cb_t cb);
#endif
#endif
#if defined(BFLB_BLE)
/** @brief load gatt ccc from flash
 *
 *  @param void.
 *  @param void.
 */
void bt_gatt_ccc_load(void);
#endif

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_GATT_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/hci_err.h
================================================
/** @file
 *  @brief Bluetooth Host Control Interface status codes.
 */

/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_HCI_STATUS_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_HCI_STATUS_H_

#ifdef __cplusplus
extern "C" {
#endif

/* HCI Error Codes, BT Core spec [Vol 2, Part D]. */
#define BT_HCI_ERR_SUCCESS                  0x00
#define BT_HCI_ERR_UNKNOWN_CMD              0x01
#define BT_HCI_ERR_UNKNOWN_CONN_ID          0x02
#define BT_HCI_ERR_HW_FAILURE               0x03
#define BT_HCI_ERR_PAGE_TIMEOUT             0x04
#define BT_HCI_ERR_AUTH_FAIL                0x05
#define BT_HCI_ERR_PIN_OR_KEY_MISSING       0x06
#define BT_HCI_ERR_MEM_CAPACITY_EXCEEDED    0x07
#define BT_HCI_ERR_CONN_TIMEOUT             0x08
#define BT_HCI_ERR_CONN_LIMIT_EXCEEDED      0x09
#define BT_HCI_ERR_SYNC_CONN_LIMIT_EXCEEDED 0x0a
#define BT_HCI_ERR_CONN_ALREADY_EXISTS      0x0b
#define BT_HCI_ERR_CMD_DISALLOWED           0x0c
#define BT_HCI_ERR_INSUFFICIENT_RESOURCES   0x0d
#define BT_HCI_ERR_INSUFFICIENT_SECURITY    0x0e
#define BT_HCI_ERR_BD_ADDR_UNACCEPTABLE     0x0f
#define BT_HCI_ERR_CONN_ACCEPT_TIMEOUT      0x10
#define BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL 0x11
#define BT_HCI_ERR_INVALID_PARAM            0x12
#define BT_HCI_ERR_REMOTE_USER_TERM_CONN    0x13
#define BT_HCI_ERR_REMOTE_LOW_RESOURCES     0x14
#define BT_HCI_ERR_REMOTE_POWER_OFF         0x15
#define BT_HCI_ERR_LOCALHOST_TERM_CONN      0x16
#define BT_HCI_ERR_PAIRING_NOT_ALLOWED      0x18
#define BT_HCI_ERR_UNSUPP_REMOTE_FEATURE    0x1a
#define BT_HCI_ERR_INVALID_LL_PARAM         0x1e
#define BT_HCI_ERR_UNSPECIFIED              0x1f
#define BT_HCI_ERR_UNSUPP_LL_PARAM_VAL      0x20
#define BT_HCI_ERR_LL_RESP_TIMEOUT          0x22
#define BT_HCI_ERR_LL_PROC_COLLISION        0x23
#define BT_HCI_ERR_INSTANT_PASSED           0x28
#define BT_HCI_ERR_PAIRING_NOT_SUPPORTED    0x29
#define BT_HCI_ERR_DIFF_TRANS_COLLISION     0x2a
#define BT_HCI_ERR_UNACCEPT_CONN_PARAM      0x3b
#define BT_HCI_ERR_ADV_TIMEOUT              0x3c
#define BT_HCI_ERR_TERM_DUE_TO_MIC_FAIL     0x3d
#define BT_HCI_ERR_CONN_FAIL_TO_ESTAB       0x3e

#define BT_HCI_ERR_AUTHENTICATION_FAIL __DEPRECATED_MACRO BT_HCI_ERR_AUTH_FAIL

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_HCI_STATUS_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/hci_host.h
================================================
/* hci.h - Bluetooth Host Control Interface definitions */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef __BT_HCI_HOST_H
#define __BT_HCI_HOST_H

#include 
#include 
#include 
#include 
#include 
#include 
#include 

#if defined(BFLB_BLE)
#include 
#endif

#ifdef __cplusplus
extern "C" {
#endif

/* Special own address types for LL privacy (used in adv & scan parameters) */
#define BT_HCI_OWN_ADDR_RPA_OR_PUBLIC 0x02
#define BT_HCI_OWN_ADDR_RPA_OR_RANDOM 0x03
#define BT_HCI_OWN_ADDR_RPA_MASK      0x02

#define BT_ENC_KEY_SIZE_MIN 0x07
#define BT_ENC_KEY_SIZE_MAX 0x10

struct bt_hci_evt_hdr {
    u8_t evt;
    u8_t len;
} __packed;
#define BT_HCI_EVT_HDR_SIZE 2

#define BT_ACL_START_NO_FLUSH 0x00
#define BT_ACL_CONT           0x01
#define BT_ACL_START          0x02

#define bt_acl_handle(h)         ((h)&0x0fff)
#define bt_acl_flags(h)          ((h) >> 12)
#define bt_acl_handle_pack(h, f) ((h) | ((f) << 12))

struct bt_hci_acl_hdr {
    u16_t handle;
    u16_t len;
} __packed;
#define BT_HCI_ACL_HDR_SIZE 4

#define BT_ISO_START  0x00
#define BT_ISO_CONT   0x01
#define BT_ISO_SINGLE 0x02
#define BT_ISO_END    0x03

#define bt_iso_handle(h)   ((h)&0x0fff)
#define bt_iso_flags(h)    ((h) >> 12)
#define bt_iso_flags_pb(f) ((f)&0x0003)
#define bt_iso_flags_ts(f) (((f) >> 2) & 0x0001)
#define bt_iso_pack_flags(pb, ts) \
    (((pb)&0x0003) | (((ts)&0x0001) << 2))
#define bt_iso_handle_pack(h, pb, ts) \
    ((h) | (bt_iso_pack_flags(pb, ts) << 12))

#define BT_ISO_DATA_VALID   0x00
#define BT_ISO_DATA_INVALID 0x01
#define BT_ISO_DATA_NOP     0x02

#define bt_iso_pkt_len(h)         ((h)&0x3fff)
#define bt_iso_pkt_flags(h)       ((h) >> 14)
#define bt_iso_pkt_len_pack(h, f) ((h) | ((f) << 14))

struct bt_hci_iso_data_hdr {
    uint16_t sn;
    uint16_t slen;
} __packed;
#define BT_HCI_ISO_DATA_HDR_SIZE 4

struct bt_hci_iso_ts_data_hdr {
    uint32_t ts;
    struct bt_hci_iso_data_hdr data;
} __packed;
#define BT_HCI_ISO_TS_DATA_HDR_SIZE 8

struct bt_hci_iso_hdr {
    uint16_t handle;
    uint16_t len;
} __packed;
#define BT_HCI_ISO_HDR_SIZE 4

struct bt_hci_cmd_hdr {
    u16_t opcode;
    u8_t param_len;
} __packed;
#define BT_HCI_CMD_HDR_SIZE 3

/* Supported Commands */
#define BT_CMD_TEST(cmd, octet, bit) (cmd[octet] & BIT(bit))
#define BT_CMD_LE_STATES(cmd)        BT_CMD_TEST(cmd, 28, 3)

#define BT_FEAT_TEST(feat, page, octet, bit) (feat[page][octet] & BIT(bit))

#define BT_FEAT_BREDR(feat)        !BT_FEAT_TEST(feat, 0, 4, 5)
#define BT_FEAT_LE(feat)           BT_FEAT_TEST(feat, 0, 4, 6)
#define BT_FEAT_EXT_FEATURES(feat) BT_FEAT_TEST(feat, 0, 7, 7)
#define BT_FEAT_HOST_SSP(feat)     BT_FEAT_TEST(feat, 1, 0, 0)
#define BT_FEAT_SC(feat)           BT_FEAT_TEST(feat, 2, 1, 0)

#define BT_FEAT_LMP_ESCO_CAPABLE(feat) BT_FEAT_TEST(feat, 0, 3, 7)
#define BT_FEAT_HV2_PKT(feat)          BT_FEAT_TEST(feat, 0, 1, 4)
#define BT_FEAT_HV3_PKT(feat)          BT_FEAT_TEST(feat, 0, 1, 5)
#define BT_FEAT_EV4_PKT(feat)          BT_FEAT_TEST(feat, 0, 4, 0)
#define BT_FEAT_EV5_PKT(feat)          BT_FEAT_TEST(feat, 0, 4, 1)
#define BT_FEAT_2EV3_PKT(feat)         BT_FEAT_TEST(feat, 0, 5, 5)
#define BT_FEAT_3EV3_PKT(feat)         BT_FEAT_TEST(feat, 0, 5, 6)
#define BT_FEAT_3SLOT_PKT(feat)        BT_FEAT_TEST(feat, 0, 5, 7)

/* LE features */
#define BT_LE_FEAT_BIT_ENC                     0
#define BT_LE_FEAT_BIT_CONN_PARAM_REQ          1
#define BT_LE_FEAT_BIT_EXT_REJ_IND             2
#define BT_LE_FEAT_BIT_SLAVE_FEAT_REQ          3
#define BT_LE_FEAT_BIT_PING                    4
#define BT_LE_FEAT_BIT_DLE                     5
#define BT_LE_FEAT_BIT_PRIVACY                 6
#define BT_LE_FEAT_BIT_EXT_SCAN                7
#define BT_LE_FEAT_BIT_PHY_2M                  8
#define BT_LE_FEAT_BIT_SMI_TX                  9
#define BT_LE_FEAT_BIT_SMI_RX                  10
#define BT_LE_FEAT_BIT_PHY_CODED               11
#define BT_LE_FEAT_BIT_ADV_EXT                 12
#define BT_LE_FEAT_BIT_ADV_PER                 13
#define BT_LE_FEAT_BIT_CHAN_SEL_ALGO_2         14
#define BT_LE_FEAT_BIT_PWR_CLASS_1             15
#define BT_LE_FEAT_BIT_MIN_USED_CHAN_PROC      16
#define BT_LE_FEAT_BIT_CONN_CTE_REQ            17
#define BT_LE_FEAT_BIT_CONN_CTE_RESP           18
#define BT_LE_FEAT_BIT_CONNECTIONLESS_CTE_TX   19
#define BT_LE_FEAT_BIT_CONNECTIONLESS_CTE_RX   20
#define BT_LE_FEAT_BIT_ANT_SWITCH_TX_AOD       21
#define BT_LE_FEAT_BIT_ANT_SWITCH_RX_AOA       22
#define BT_LE_FEAT_BIT_RX_CTE                  23
#define BT_LE_FEAT_BIT_PAST_SEND               24
#define BT_LE_FEAT_BIT_PAST_RECV               25
#define BT_LE_FEAT_BIT_SCA_UPDATE              26
#define BT_LE_FEAT_BIT_REMOTE_PUB_KEY_VALIDATE 27
#define BT_LE_FEAT_BIT_CIS_MASTER              28
#define BT_LE_FEAT_BIT_CIS_SLAVE               29
#define BT_LE_FEAT_BIT_ISO_BROADCASTER         30
#define BT_LE_FEAT_BIT_SYNC_RECEIVER           31
#define BT_LE_FEAT_BIT_ISO_CHANNELS            32
#define BT_LE_FEAT_BIT_PWR_CTRL_REQ            33
#define BT_LE_FEAT_BIT_PWR_CHG_IND             34
#define BT_LE_FEAT_BIT_PATH_LOSS_MONITOR       35

#define BT_LE_FEAT_TEST(feat, n) (feat[(n) >> 3] & \
                                  BIT((n)&7))

#define BT_FEAT_LE_ENCR(feat) BT_LE_FEAT_TEST(feat, \
                                              BT_LE_FEAT_BIT_ENC)
#define BT_FEAT_LE_CONN_PARAM_REQ_PROC(feat) BT_LE_FEAT_TEST(feat, \
                                                             BT_LE_FEAT_BIT_CONN_PARAM_REQ)
#define BT_FEAT_LE_SLAVE_FEATURE_XCHG(feat) BT_LE_FEAT_TEST(feat, \
                                                            BT_LE_FEAT_BIT_SLAVE_FEAT_REQ)
#define BT_FEAT_LE_DLE(feat) BT_LE_FEAT_TEST(feat, \
                                             BT_LE_FEAT_BIT_DLE)
#define BT_FEAT_LE_PHY_2M(feat) BT_LE_FEAT_TEST(feat, \
                                                BT_LE_FEAT_BIT_PHY_2M)
#define BT_FEAT_LE_PHY_CODED(feat) BT_LE_FEAT_TEST(feat, \
                                                   BT_LE_FEAT_BIT_PHY_CODED)
#define BT_FEAT_LE_PRIVACY(feat) BT_LE_FEAT_TEST(feat, \
                                                 BT_LE_FEAT_BIT_PRIVACY)
#define BT_FEAT_LE_EXT_ADV(feat) BT_LE_FEAT_TEST(feat, \
                                                 BT_LE_FEAT_BIT_EXT_ADV)
#define BT_FEAT_LE_EXT_PER_ADV(feat) BT_LE_FEAT_TEST(feat, \
                                                     BT_LE_FEAT_BIT_PER_ADV)
#define BT_FEAT_LE_CONNECTIONLESS_CTE_TX(feat) BT_LE_FEAT_TEST(feat, \
                                                               BT_LE_FEAT_BIT_CONNECTIONLESS_CTE_TX)
#define BT_FEAT_LE_ANT_SWITCH_TX_AOD(feat) BT_LE_FEAT_TEST(feat, \
                                                           BT_LE_FEAT_BIT_ANT_SWITCH_TX_AOD)
#define BT_FEAT_LE_PAST_SEND(feat) BT_LE_FEAT_TEST(feat, \
                                                   BT_LE_FEAT_BIT_PAST_SEND)
#define BT_FEAT_LE_PAST_RECV(feat) BT_LE_FEAT_TEST(feat, \
                                                   BT_LE_FEAT_BIT_PAST_RECV)
#define BT_FEAT_LE_CIS_MASTER(feat) BT_LE_FEAT_TEST(feat, \
                                                    BT_LE_FEAT_BIT_CIS_MASTER)
#define BT_FEAT_LE_CIS_SLAVE(feat) BT_LE_FEAT_TEST(feat, \
                                                   BT_LE_FEAT_BIT_CIS_SLAVE)
#define BT_FEAT_LE_ISO_BROADCASTER(feat) BT_LE_FEAT_TEST(feat, \
                                                         BT_LE_FEAT_BIT_ISO_BROADCASTER)
#define BT_FEAT_LE_SYNC_RECEIVER(feat) BT_LE_FEAT_TEST(feat, \
                                                       BT_LE_FEAT_BIT_SYNC_RECEIVER)
#define BT_FEAT_LE_ISO_CHANNELS(feat) BT_LE_FEAT_TEST(feat, \
                                                      BT_LE_FEAT_BIT_ISO_CHANNELS)

#define BT_FEAT_LE_CIS(feat) (BT_FEAT_LE_CIS_MASTER(feat) | \
                              BT_FEAT_LE_CIS_SLAVE(feat))
#define BT_FEAT_LE_BIS(feat) (BT_FEAT_LE_ISO_BROADCASTER(feat) | \
                              BT_FEAT_LE_SYNC_RECEIVER(feat))
#define BT_FEAT_LE_ISO(feat) (BT_FEAT_LE_CIS(feat) | \
                              BT_FEAT_LE_BIS(feat))

/* LE States */
#define BT_LE_STATES_SLAVE_CONN_ADV(states) (states & 0x0000004000000000)

/* Bonding/authentication types */
#define BT_HCI_NO_BONDING             0x00
#define BT_HCI_NO_BONDING_MITM        0x01
#define BT_HCI_DEDICATED_BONDING      0x02
#define BT_HCI_DEDICATED_BONDING_MITM 0x03
#define BT_HCI_GENERAL_BONDING        0x04
#define BT_HCI_GENERAL_BONDING_MITM   0x05

/*
 * MITM protection is enabled in SSP authentication requirements octet when
 * LSB bit is set.
 */
#define BT_MITM 0x01

/* I/O capabilities */
#define BT_IO_DISPLAY_ONLY    0x00
#define BT_IO_DISPLAY_YESNO   0x01
#define BT_IO_KEYBOARD_ONLY   0x02
#define BT_IO_NO_INPUT_OUTPUT 0x03

/* SCO packet types */
#define HCI_PKT_TYPE_HV1 0x0020
#define HCI_PKT_TYPE_HV2 0x0040
#define HCI_PKT_TYPE_HV3 0x0080

/* eSCO packet types */
#define HCI_PKT_TYPE_ESCO_HV1  0x0001
#define HCI_PKT_TYPE_ESCO_HV2  0x0002
#define HCI_PKT_TYPE_ESCO_HV3  0x0004
#define HCI_PKT_TYPE_ESCO_EV3  0x0008
#define HCI_PKT_TYPE_ESCO_EV4  0x0010
#define HCI_PKT_TYPE_ESCO_EV5  0x0020
#define HCI_PKT_TYPE_ESCO_2EV3 0x0040
#define HCI_PKT_TYPE_ESCO_3EV3 0x0080
#define HCI_PKT_TYPE_ESCO_2EV5 0x0100
#define HCI_PKT_TYPE_ESCO_3EV5 0x0200

#define ESCO_PKT_MASK (HCI_PKT_TYPE_ESCO_HV1 | \
                       HCI_PKT_TYPE_ESCO_HV2 | \
                       HCI_PKT_TYPE_ESCO_HV3)
#define SCO_PKT_MASK (HCI_PKT_TYPE_HV1 | \
                      HCI_PKT_TYPE_HV2 | \
                      HCI_PKT_TYPE_HV3)
#define EDR_ESCO_PKT_MASK (HCI_PKT_TYPE_ESCO_2EV3 | \
                           HCI_PKT_TYPE_ESCO_3EV3 | \
                           HCI_PKT_TYPE_ESCO_2EV5 | \
                           HCI_PKT_TYPE_ESCO_3EV5)

/* HCI BR/EDR link types */
#define BT_HCI_SCO  0x00
#define BT_HCI_ACL  0x01
#define BT_HCI_ESCO 0x02

/* OpCode Group Fields */
#define BT_OGF_LINK_CTRL 0x01
#define BT_OGF_BASEBAND  0x03
#define BT_OGF_INFO      0x04
#define BT_OGF_STATUS    0x05
#define BT_OGF_LE        0x08
#define BT_OGF_VS        0x3f

/* Construct OpCode from OGF and OCF */
#define BT_OP(ogf, ocf) ((ocf) | ((ogf) << 10))

/* Invalid opcode */
#define BT_OP_NOP 0x0000

/* Obtain OGF from OpCode */
#define BT_OGF(opcode) (((opcode) >> 10) & BIT_MASK(6))
/* Obtain OCF from OpCode */
#define BT_OCF(opcode) ((opcode)&BIT_MASK(10))

#define BT_HCI_OP_INQUIRY BT_OP(BT_OGF_LINK_CTRL, 0x0001)
struct bt_hci_op_inquiry {
    u8_t lap[3];
    u8_t length;
    u8_t num_rsp;
} __packed;

#define BT_HCI_OP_INQUIRY_CANCEL BT_OP(BT_OGF_LINK_CTRL, 0x0002)

#define BT_HCI_OP_CONNECT BT_OP(BT_OGF_LINK_CTRL, 0x0005)
struct bt_hci_cp_connect {
    bt_addr_t bdaddr;
    u16_t packet_type;
    u8_t pscan_rep_mode;
    u8_t reserved;
    u16_t clock_offset;
    u8_t allow_role_switch;
} __packed;

#define BT_HCI_OP_DISCONNECT BT_OP(BT_OGF_LINK_CTRL, 0x0006)
struct bt_hci_cp_disconnect {
    u16_t handle;
    u8_t reason;
} __packed;

#define BT_HCI_OP_CONNECT_CANCEL BT_OP(BT_OGF_LINK_CTRL, 0x0008)
struct bt_hci_cp_connect_cancel {
    bt_addr_t bdaddr;
} __packed;
struct bt_hci_rp_connect_cancel {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_ACCEPT_CONN_REQ BT_OP(BT_OGF_LINK_CTRL, 0x0009)
struct bt_hci_cp_accept_conn_req {
    bt_addr_t bdaddr;
    u8_t role;
} __packed;

#define BT_HCI_OP_SETUP_SYNC_CONN BT_OP(BT_OGF_LINK_CTRL, 0x0028)
struct bt_hci_cp_setup_sync_conn {
    u16_t handle;
    u32_t tx_bandwidth;
    u32_t rx_bandwidth;
    u16_t max_latency;
    u16_t content_format;
    u8_t retrans_effort;
    u16_t pkt_type;
} __packed;

#define BT_HCI_OP_ACCEPT_SYNC_CONN_REQ BT_OP(BT_OGF_LINK_CTRL, 0x0029)
struct bt_hci_cp_accept_sync_conn_req {
    bt_addr_t bdaddr;
    u32_t tx_bandwidth;
    u32_t rx_bandwidth;
    u16_t max_latency;
    u16_t content_format;
    u8_t retrans_effort;
    u16_t pkt_type;
} __packed;

#define BT_HCI_OP_REJECT_CONN_REQ BT_OP(BT_OGF_LINK_CTRL, 0x000a)
struct bt_hci_cp_reject_conn_req {
    bt_addr_t bdaddr;
    u8_t reason;
} __packed;

#define BT_HCI_OP_LINK_KEY_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x000b)
struct bt_hci_cp_link_key_reply {
    bt_addr_t bdaddr;
    u8_t link_key[16];
} __packed;

#define BT_HCI_OP_LINK_KEY_NEG_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x000c)
struct bt_hci_cp_link_key_neg_reply {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_PIN_CODE_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x000d)
struct bt_hci_cp_pin_code_reply {
    bt_addr_t bdaddr;
    u8_t pin_len;
    u8_t pin_code[16];
} __packed;
struct bt_hci_rp_pin_code_reply {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_PIN_CODE_NEG_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x000e)
struct bt_hci_cp_pin_code_neg_reply {
    bt_addr_t bdaddr;
} __packed;
struct bt_hci_rp_pin_code_neg_reply {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_AUTH_REQUESTED BT_OP(BT_OGF_LINK_CTRL, 0x0011)
struct bt_hci_cp_auth_requested {
    u16_t handle;
} __packed;

#define BT_HCI_OP_SET_CONN_ENCRYPT BT_OP(BT_OGF_LINK_CTRL, 0x0013)
struct bt_hci_cp_set_conn_encrypt {
    u16_t handle;
    u8_t encrypt;
} __packed;

#define BT_HCI_OP_REMOTE_NAME_REQUEST BT_OP(BT_OGF_LINK_CTRL, 0x0019)
struct bt_hci_cp_remote_name_request {
    bt_addr_t bdaddr;
    u8_t pscan_rep_mode;
    u8_t reserved;
    u16_t clock_offset;
} __packed;

#define BT_HCI_OP_REMOTE_NAME_CANCEL BT_OP(BT_OGF_LINK_CTRL, 0x001a)
struct bt_hci_cp_remote_name_cancel {
    bt_addr_t bdaddr;
} __packed;
struct bt_hci_rp_remote_name_cancel {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_READ_REMOTE_FEATURES BT_OP(BT_OGF_LINK_CTRL, 0x001b)
struct bt_hci_cp_read_remote_features {
    u16_t handle;
} __packed;

#define BT_HCI_OP_READ_REMOTE_EXT_FEATURES BT_OP(BT_OGF_LINK_CTRL, 0x001c)
struct bt_hci_cp_read_remote_ext_features {
    u16_t handle;
    u8_t page;
} __packed;

#define BT_HCI_OP_READ_REMOTE_VERSION_INFO BT_OP(BT_OGF_LINK_CTRL, 0x001d)
struct bt_hci_cp_read_remote_version_info {
    u16_t handle;
} __packed;

#define BT_HCI_OP_IO_CAPABILITY_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x002b)
struct bt_hci_cp_io_capability_reply {
    bt_addr_t bdaddr;
    u8_t capability;
    u8_t oob_data;
    u8_t authentication;
} __packed;

#define BT_HCI_OP_USER_CONFIRM_REPLY     BT_OP(BT_OGF_LINK_CTRL, 0x002c)
#define BT_HCI_OP_USER_CONFIRM_NEG_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x002d)
struct bt_hci_cp_user_confirm_reply {
    bt_addr_t bdaddr;
} __packed;
struct bt_hci_rp_user_confirm_reply {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_USER_PASSKEY_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x002e)
struct bt_hci_cp_user_passkey_reply {
    bt_addr_t bdaddr;
    u32_t passkey;
} __packed;

#define BT_HCI_OP_USER_PASSKEY_NEG_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x002f)
struct bt_hci_cp_user_passkey_neg_reply {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_OP_IO_CAPABILITY_NEG_REPLY BT_OP(BT_OGF_LINK_CTRL, 0x0034)
struct bt_hci_cp_io_capability_neg_reply {
    bt_addr_t bdaddr;
    u8_t reason;
} __packed;

#define BT_HCI_OP_SET_EVENT_MASK BT_OP(BT_OGF_BASEBAND, 0x0001)
struct bt_hci_cp_set_event_mask {
    u8_t events[8];
} __packed;

#define BT_HCI_OP_RESET BT_OP(BT_OGF_BASEBAND, 0x0003)

#define BT_HCI_OP_WRITE_LOCAL_NAME BT_OP(BT_OGF_BASEBAND, 0x0013)
struct bt_hci_write_local_name {
    u8_t local_name[248];
} __packed;

#define BT_HCI_OP_WRITE_PAGE_TIMEOUT BT_OP(BT_OGF_BASEBAND, 0x0018)

#define BT_HCI_OP_WRITE_SCAN_ENABLE BT_OP(BT_OGF_BASEBAND, 0x001a)
#define BT_BREDR_SCAN_DISABLED      0x00
#define BT_BREDR_SCAN_INQUIRY       0x01
#define BT_BREDR_SCAN_PAGE          0x02

#define BT_HCI_OP_WRITE_INQUIRY_SCAN_ACTIVITY BT_OP(BT_OGF_BASEBAND, 0x001e)
struct bt_hci_cp_write_inquiry_scan_activity {
    u16_t interval;
    u16_t window;
} __packed;

#define BT_HCI_OP_WRITE_CLASS_OF_DEVICE BT_OP(BT_OGF_BASEBAND, 0x0024)
struct bt_hci_cp_write_class_of_device {
    u8_t cod[3];
} __packed;

#define BT_TX_POWER_LEVEL_CURRENT     0x00
#define BT_TX_POWER_LEVEL_MAX         0x01
#define BT_HCI_OP_READ_TX_POWER_LEVEL BT_OP(BT_OGF_BASEBAND, 0x002d)
struct bt_hci_cp_read_tx_power_level {
    u16_t handle;
    u8_t type;
} __packed;

struct bt_hci_rp_read_tx_power_level {
    u8_t status;
    u16_t handle;
    s8_t tx_power_level;
} __packed;

#define BT_HCI_CTL_TO_HOST_FLOW_DISABLE 0x00
#define BT_HCI_CTL_TO_HOST_FLOW_ENABLE  0x01
#define BT_HCI_OP_SET_CTL_TO_HOST_FLOW  BT_OP(BT_OGF_BASEBAND, 0x0031)
struct bt_hci_cp_set_ctl_to_host_flow {
    u8_t flow_enable;
} __packed;

#define BT_HCI_OP_HOST_BUFFER_SIZE BT_OP(BT_OGF_BASEBAND, 0x0033)
struct bt_hci_cp_host_buffer_size {
    u16_t acl_mtu;
    u8_t sco_mtu;
    u16_t acl_pkts;
    u16_t sco_pkts;
} __packed;

struct bt_hci_handle_count {
    u16_t handle;
    u16_t count;
} __packed;

#define BT_HCI_OP_HOST_NUM_COMPLETED_PACKETS BT_OP(BT_OGF_BASEBAND, 0x0035)
struct bt_hci_cp_host_num_completed_packets {
    u8_t num_handles;
    struct bt_hci_handle_count h[0];
} __packed;

#define BT_HCI_OP_WRITE_INQUIRY_SCAN_TYPE BT_OP(BT_OGF_BASEBAND, 0x0043)
struct bt_hci_cp_write_inquiry_scan_type {
    u8_t type;
} __packed;

#define BT_HCI_OP_WRITE_INQUIRY_MODE BT_OP(BT_OGF_BASEBAND, 0x0045)
struct bt_hci_cp_write_inquiry_mode {
    u8_t mode;
} __packed;

#define BT_HCI_OP_WRITE_PAGE_SCAN_TYPE BT_OP(BT_OGF_BASEBAND, 0x0047)
struct bt_hci_cp_write_page_scan_type {
    u8_t type;
} __packed;

#define BT_HCI_OP_WRITE_EXT_INQUIRY_RESP BT_OP(BT_OGF_BASEBAND, 0x0052)
struct bt_hci_cp_write_ext_inquiry_resp {
    u8_t rec;
    u8_t eir[240];
} __packed;

#define BT_HCI_OP_WRITE_SSP_MODE BT_OP(BT_OGF_BASEBAND, 0x0056)
struct bt_hci_cp_write_ssp_mode {
    u8_t mode;
} __packed;

#define BT_HCI_OP_SET_EVENT_MASK_PAGE_2 BT_OP(BT_OGF_BASEBAND, 0x0063)
struct bt_hci_cp_set_event_mask_page_2 {
    u8_t events_page_2[8];
} __packed;

#define BT_HCI_OP_LE_WRITE_LE_HOST_SUPP BT_OP(BT_OGF_BASEBAND, 0x006d)
struct bt_hci_cp_write_le_host_supp {
    u8_t le;
    u8_t simul;
} __packed;

#define BT_HCI_OP_WRITE_SC_HOST_SUPP BT_OP(BT_OGF_BASEBAND, 0x007a)
struct bt_hci_cp_write_sc_host_supp {
    u8_t sc_support;
} __packed;

#define BT_HCI_OP_READ_AUTH_PAYLOAD_TIMEOUT BT_OP(BT_OGF_BASEBAND, 0x007b)
struct bt_hci_cp_read_auth_payload_timeout {
    u16_t handle;
} __packed;

struct bt_hci_rp_read_auth_payload_timeout {
    u8_t status;
    u16_t handle;
    u16_t auth_payload_timeout;
} __packed;

#define BT_HCI_OP_WRITE_AUTH_PAYLOAD_TIMEOUT BT_OP(BT_OGF_BASEBAND, 0x007c)
struct bt_hci_cp_write_auth_payload_timeout {
    u16_t handle;
    u16_t auth_payload_timeout;
} __packed;

struct bt_hci_rp_write_auth_payload_timeout {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_CONFIGURE_DATA_PATH BT_OP(BT_OGF_BASEBAND, 0x0083)
struct bt_hci_cp_configure_data_path {
    uint8_t data_path_dir;
    uint8_t data_path_id;
    uint8_t vs_config_len;
    uint8_t vs_config[0];
} __packed;

struct bt_hci_rp_configure_data_path {
    uint8_t status;
} __packed;

/* HCI version from Assigned Numbers */
#define BT_HCI_VERSION_1_0B 0
#define BT_HCI_VERSION_1_1  1
#define BT_HCI_VERSION_1_2  2
#define BT_HCI_VERSION_2_0  3
#define BT_HCI_VERSION_2_1  4
#define BT_HCI_VERSION_3_0  5
#define BT_HCI_VERSION_4_0  6
#define BT_HCI_VERSION_4_1  7
#define BT_HCI_VERSION_4_2  8
#define BT_HCI_VERSION_5_0  9
#define BT_HCI_VERSION_5_1  10
#define BT_HCI_VERSION_5_2  11

#define BT_HCI_OP_READ_LOCAL_VERSION_INFO BT_OP(BT_OGF_INFO, 0x0001)
struct bt_hci_rp_read_local_version_info {
    u8_t status;
    u8_t hci_version;
    u16_t hci_revision;
    u8_t lmp_version;
    u16_t manufacturer;
    u16_t lmp_subversion;
} __packed;

#define BT_HCI_OP_READ_SUPPORTED_COMMANDS BT_OP(BT_OGF_INFO, 0x0002)
struct bt_hci_rp_read_supported_commands {
    u8_t status;
    u8_t commands[64];
} __packed;

#define BT_HCI_OP_READ_LOCAL_EXT_FEATURES BT_OP(BT_OGF_INFO, 0x0004)
struct bt_hci_cp_read_local_ext_features {
    u8_t page;
};
struct bt_hci_rp_read_local_ext_features {
    u8_t status;
    u8_t page;
    u8_t max_page;
    u8_t ext_features[8];
} __packed;

#define BT_HCI_OP_READ_LOCAL_FEATURES BT_OP(BT_OGF_INFO, 0x0003)
struct bt_hci_rp_read_local_features {
    u8_t status;
    u8_t features[8];
} __packed;

#define BT_HCI_OP_READ_BUFFER_SIZE BT_OP(BT_OGF_INFO, 0x0005)
struct bt_hci_rp_read_buffer_size {
    u8_t status;
    u16_t acl_max_len;
    u8_t sco_max_len;
    u16_t acl_max_num;
    u16_t sco_max_num;
} __packed;

#define BT_HCI_OP_READ_BD_ADDR BT_OP(BT_OGF_INFO, 0x0009)
struct bt_hci_rp_read_bd_addr {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

/* logic transport type bits as returned when reading supported codecs */
#define BT_HCI_CODEC_TRANSPORT_MASK_BREDR_ACL BIT(0)
#define BT_HCI_CODEC_TRANSPORT_MASK_BREDR_SCO BIT(1)
#define BT_HCI_CODEC_TRANSPORT_MASK_LE_CIS    BIT(2)
#define BT_HCI_CODEC_TRANSPORT_MASK_LE_BIS    BIT(3)

/* logic transport types for reading codec capabilities and controller delays */
#define BT_HCI_LOGICAL_TRANSPORT_TYPE_BREDR_ACL 0x00
#define BT_HCI_LOGICAL_TRANSPORT_TYPE_BREDR_SCO 0x01
#define BT_HCI_LOGICAL_TRANSPORT_TYPE_LE_CIS    0x02
#define BT_HCI_LOGICAL_TRANSPORT_TYPE_LE_BIS    0x03

/* audio datapath directions */
#define BT_HCI_DATAPATH_DIR_HOST_TO_CTLR 0x00
#define BT_HCI_DATAPATH_DIR_CTLR_TO_HOST 0x01

/* coding format assigned numbers, used for codec IDs */
#define BT_HCI_CODING_FORMAT_ULAW_LOG    0x00
#define BT_HCI_CODING_FORMAT_ALAW_LOG    0x01
#define BT_HCI_CODING_FORMAT_CVSD        0x02
#define BT_HCI_CODING_FORMAT_TRANSPARENT 0x03
#define BT_HCI_CODING_FORMAT_LINEAR_PCM  0x04
#define BT_HCI_CODING_FORMAT_MSBC        0x05
#define BT_HCI_CODING_FORMAT_VS          0xFF

#define BT_HCI_OP_READ_CODECS BT_OP(BT_OGF_INFO, 0x000b)
struct bt_hci_std_codec_info {
    uint8_t codec_id;
} __packed;
struct bt_hci_std_codecs {
    uint8_t num_codecs;
    struct bt_hci_std_codec_info codec_info[0];
} __packed;
struct bt_hci_vs_codec_info {
    uint16_t company_id;
    uint16_t codec_id;
} __packed;
struct bt_hci_vs_codecs {
    uint8_t num_codecs;
    struct bt_hci_vs_codec_info codec_info[0];
} __packed;
struct bt_hci_rp_read_codecs {
    uint8_t status;
    /* other fields filled in dynamically */
    uint8_t codecs[0];
} __packed;

#define BT_HCI_OP_READ_CODECS_V2 BT_OP(BT_OGF_INFO, 0x000d)
struct bt_hci_std_codec_info_v2 {
    uint8_t codec_id;
    uint8_t transports; /* bitmap */
} __packed;
struct bt_hci_std_codecs_v2 {
    uint8_t num_codecs;
    struct bt_hci_std_codec_info_v2 codec_info[0];
} __packed;
struct bt_hci_vs_codec_info_v2 {
    uint16_t company_id;
    uint16_t codec_id;
    uint8_t transports; /* bitmap */
} __packed;
struct bt_hci_vs_codecs_v2 {
    uint8_t num_codecs;
    struct bt_hci_vs_codec_info_v2 codec_info[0];
} __packed;
struct bt_hci_rp_read_codecs_v2 {
    uint8_t status;
    /* other fields filled in dynamically */
    uint8_t codecs[0];
} __packed;

struct bt_hci_cp_codec_id {
    uint8_t coding_format;
    uint16_t company_id;
    uint16_t vs_codec_id;
} __packed;

#define BT_HCI_OP_READ_CODEC_CAPABILITIES BT_OP(BT_OGF_INFO, 0x000e)
struct bt_hci_cp_read_codec_capabilities {
    struct bt_hci_cp_codec_id codec_id;
    uint8_t transport;
    uint8_t direction;
} __packed;
struct bt_hci_codec_capability_info {
    uint8_t length;
    uint8_t data[0];
} __packed;
struct bt_hci_rp_read_codec_capabilities {
    uint8_t status;
    uint8_t num_capabilities;
    /* other fields filled in dynamically */
    uint8_t capabilities[0];
} __packed;

#define BT_HCI_OP_READ_CTLR_DELAY BT_OP(BT_OGF_INFO, 0x000f)
struct bt_hci_cp_read_ctlr_delay {
    struct bt_hci_cp_codec_id codec_id;
    uint8_t transport;
    uint8_t direction;
    uint8_t codec_config_len;
    uint8_t codec_config[0];
} __packed;
struct bt_hci_rp_read_ctlr_delay {
    uint8_t status;
    uint8_t min_ctlr_delay[3];
    uint8_t max_ctlr_delay[3];
} __packed;

#define BT_HCI_OP_READ_RSSI BT_OP(BT_OGF_STATUS, 0x0005)
struct bt_hci_cp_read_rssi {
    u16_t handle;
} __packed;
struct bt_hci_rp_read_rssi {
    u8_t status;
    u16_t handle;
    s8_t rssi;
} __packed;

#define BT_HCI_ENCRYPTION_KEY_SIZE_MIN 7
#define BT_HCI_ENCRYPTION_KEY_SIZE_MAX 16

#define BT_HCI_OP_READ_ENCRYPTION_KEY_SIZE BT_OP(BT_OGF_STATUS, 0x0008)
struct bt_hci_cp_read_encryption_key_size {
    u16_t handle;
} __packed;
struct bt_hci_rp_read_encryption_key_size {
    u8_t status;
    u16_t handle;
    u8_t key_size;
} __packed;

/* BLE */

#define BT_HCI_OP_LE_SET_EVENT_MASK BT_OP(BT_OGF_LE, 0x0001)
struct bt_hci_cp_le_set_event_mask {
    u8_t events[8];
} __packed;

#define BT_HCI_OP_LE_READ_BUFFER_SIZE BT_OP(BT_OGF_LE, 0x0002)
struct bt_hci_rp_le_read_buffer_size {
    u8_t status;
    u16_t le_max_len;
    u8_t le_max_num;
} __packed;

#define BT_HCI_OP_LE_READ_LOCAL_FEATURES BT_OP(BT_OGF_LE, 0x0003)
struct bt_hci_rp_le_read_local_features {
    u8_t status;
    u8_t features[8];
} __packed;

#define BT_HCI_OP_LE_SET_RANDOM_ADDRESS BT_OP(BT_OGF_LE, 0x0005)
struct bt_hci_cp_le_set_random_address {
    bt_addr_t bdaddr;
} __packed;

/* Advertising types */
#define BT_LE_ADV_IND                 0x00
#define BT_LE_ADV_DIRECT_IND          0x01
#define BT_LE_ADV_SCAN_IND            0x02
#define BT_LE_ADV_NONCONN_IND         0x03
#define BT_LE_ADV_DIRECT_IND_LOW_DUTY 0x04
/* Needed in advertising reports when getting info about */
#define BT_LE_ADV_SCAN_RSP 0x04

#define BT_LE_ADV_FP_NO_WHITELIST       0x00
#define BT_LE_ADV_FP_WHITELIST_SCAN_REQ 0x01
#define BT_LE_ADV_FP_WHITELIST_CONN_IND 0x02
#define BT_LE_ADV_FP_WHITELIST_BOTH     0x03

#define BT_HCI_OP_LE_SET_ADV_PARAM BT_OP(BT_OGF_LE, 0x0006)
struct bt_hci_cp_le_set_adv_param {
    u16_t min_interval;
    u16_t max_interval;
    u8_t type;
    u8_t own_addr_type;
    bt_addr_le_t direct_addr;
    u8_t channel_map;
    u8_t filter_policy;
} __packed;

#define BT_HCI_OP_LE_READ_ADV_CHAN_TX_POWER BT_OP(BT_OGF_LE, 0x0007)
struct bt_hci_rp_le_read_chan_tx_power {
    u8_t status;
    s8_t tx_power_level;
} __packed;

#define BT_HCI_OP_LE_SET_ADV_DATA BT_OP(BT_OGF_LE, 0x0008)
struct bt_hci_cp_le_set_adv_data {
    u8_t len;
    u8_t data[31];
} __packed;

#define BT_HCI_OP_LE_SET_SCAN_RSP_DATA BT_OP(BT_OGF_LE, 0x0009)
struct bt_hci_cp_le_set_scan_rsp_data {
    u8_t len;
    u8_t data[31];
} __packed;

#define BT_HCI_LE_ADV_DISABLE 0x00
#define BT_HCI_LE_ADV_ENABLE  0x01

#define BT_HCI_OP_LE_SET_ADV_ENABLE BT_OP(BT_OGF_LE, 0x000a)
struct bt_hci_cp_le_set_adv_enable {
    u8_t enable;
} __packed;

/* Scan types */
#define BT_HCI_OP_LE_SET_SCAN_PARAM BT_OP(BT_OGF_LE, 0x000b)
#define BT_HCI_LE_SCAN_PASSIVE      0x00
#define BT_HCI_LE_SCAN_ACTIVE       0x01

#define BT_HCI_LE_SCAN_FP_NO_WHITELIST  0x00
#define BT_HCI_LE_SCAN_FP_USE_WHITELIST 0x01

struct bt_hci_cp_le_set_scan_param {
    u8_t scan_type;
    u16_t interval;
    u16_t window;
    u8_t addr_type;
    u8_t filter_policy;
} __packed;

#define BT_HCI_OP_LE_SET_SCAN_ENABLE BT_OP(BT_OGF_LE, 0x000c)

#define BT_HCI_LE_SCAN_DISABLE 0x00
#define BT_HCI_LE_SCAN_ENABLE  0x01

#define BT_HCI_LE_SCAN_FILTER_DUP_DISABLE 0x00
#define BT_HCI_LE_SCAN_FILTER_DUP_ENABLE  0x01

struct bt_hci_cp_le_set_scan_enable {
    u8_t enable;
    u8_t filter_dup;
} __packed;

#define BT_HCI_OP_LE_CREATE_CONN BT_OP(BT_OGF_LE, 0x000d)

#define BT_HCI_LE_CREATE_CONN_FP_DIRECT    0x00
#define BT_HCI_LE_CREATE_CONN_FP_WHITELIST 0x01

struct bt_hci_cp_le_create_conn {
    u16_t scan_interval;
    u16_t scan_window;
    u8_t filter_policy;
    bt_addr_le_t peer_addr;
    u8_t own_addr_type;
    u16_t conn_interval_min;
    u16_t conn_interval_max;
    u16_t conn_latency;
    u16_t supervision_timeout;
    u16_t min_ce_len;
    u16_t max_ce_len;
} __packed;

#define BT_HCI_OP_LE_CREATE_CONN_CANCEL BT_OP(BT_OGF_LE, 0x000e)

#define BT_HCI_OP_LE_READ_WL_SIZE BT_OP(BT_OGF_LE, 0x000f)
struct bt_hci_rp_le_read_wl_size {
    u8_t status;
    u8_t wl_size;
} __packed;

#define BT_HCI_OP_LE_CLEAR_WL BT_OP(BT_OGF_LE, 0x0010)

#define BT_HCI_OP_LE_ADD_DEV_TO_WL BT_OP(BT_OGF_LE, 0x0011)
struct bt_hci_cp_le_add_dev_to_wl {
    bt_addr_le_t addr;
} __packed;

#define BT_HCI_OP_LE_REM_DEV_FROM_WL BT_OP(BT_OGF_LE, 0x0012)
struct bt_hci_cp_le_rem_dev_from_wl {
    bt_addr_le_t addr;
} __packed;

#define BT_HCI_OP_LE_CONN_UPDATE BT_OP(BT_OGF_LE, 0x0013)
struct hci_cp_le_conn_update {
    u16_t handle;
    u16_t conn_interval_min;
    u16_t conn_interval_max;
    u16_t conn_latency;
    u16_t supervision_timeout;
    u16_t min_ce_len;
    u16_t max_ce_len;
} __packed;

#define BT_HCI_OP_LE_SET_HOST_CHAN_CLASSIF BT_OP(BT_OGF_LE, 0x0014)
struct bt_hci_cp_le_set_host_chan_classif {
    u8_t ch_map[5];
} __packed;

#define BT_HCI_OP_LE_READ_CHAN_MAP BT_OP(BT_OGF_LE, 0x0015)
struct bt_hci_cp_le_read_chan_map {
    u16_t handle;
} __packed;
struct bt_hci_rp_le_read_chan_map {
    u8_t status;
    u16_t handle;
    u8_t ch_map[5];
} __packed;

#define BT_HCI_OP_LE_READ_REMOTE_FEATURES BT_OP(BT_OGF_LE, 0x0016)
struct bt_hci_cp_le_read_remote_features {
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_ENCRYPT BT_OP(BT_OGF_LE, 0x0017)
struct bt_hci_cp_le_encrypt {
    u8_t key[16];
    u8_t plaintext[16];
} __packed;
struct bt_hci_rp_le_encrypt {
    u8_t status;
    u8_t enc_data[16];
} __packed;

#define BT_HCI_OP_LE_RAND BT_OP(BT_OGF_LE, 0x0018)
struct bt_hci_rp_le_rand {
    u8_t status;
    u8_t rand[8];
} __packed;

#define BT_HCI_OP_LE_START_ENCRYPTION BT_OP(BT_OGF_LE, 0x0019)
struct bt_hci_cp_le_start_encryption {
    u16_t handle;
    u64_t rand;
    u16_t ediv;
    u8_t ltk[16];
} __packed;

#define BT_HCI_OP_LE_LTK_REQ_REPLY BT_OP(BT_OGF_LE, 0x001a)
struct bt_hci_cp_le_ltk_req_reply {
    u16_t handle;
    u8_t ltk[16];
} __packed;
struct bt_hci_rp_le_ltk_req_reply {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_LTK_REQ_NEG_REPLY BT_OP(BT_OGF_LE, 0x001b)
struct bt_hci_cp_le_ltk_req_neg_reply {
    u16_t handle;
} __packed;
struct bt_hci_rp_le_ltk_req_neg_reply {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_READ_SUPP_STATES BT_OP(BT_OGF_LE, 0x001c)
struct bt_hci_rp_le_read_supp_states {
    u8_t status;
    u8_t le_states[8];
} __packed;

#define BT_HCI_OP_LE_RX_TEST BT_OP(BT_OGF_LE, 0x001d)
struct bt_hci_cp_le_rx_test {
    u8_t rx_ch;
} __packed;

#define BT_HCI_OP_LE_TX_TEST BT_OP(BT_OGF_LE, 0x001e)
struct bt_hci_cp_le_tx_test {
    u8_t tx_ch;
    u8_t test_data_len;
    u8_t pkt_payload;
} __packed;

#define BT_HCI_OP_LE_TEST_END BT_OP(BT_OGF_LE, 0x001f)
struct bt_hci_rp_le_test_end {
    u8_t status;
    u16_t rx_pkt_count;
} __packed;

#define BT_HCI_OP_LE_CONN_PARAM_REQ_REPLY BT_OP(BT_OGF_LE, 0x0020)
struct bt_hci_cp_le_conn_param_req_reply {
    u16_t handle;
    u16_t interval_min;
    u16_t interval_max;
    u16_t latency;
    u16_t timeout;
    u16_t min_ce_len;
    u16_t max_ce_len;
} __packed;
struct bt_hci_rp_le_conn_param_req_reply {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY BT_OP(BT_OGF_LE, 0x0021)
struct bt_hci_cp_le_conn_param_req_neg_reply {
    u16_t handle;
    u8_t reason;
} __packed;
struct bt_hci_rp_le_conn_param_req_neg_reply {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_SET_DATA_LEN BT_OP(BT_OGF_LE, 0x0022)
struct bt_hci_cp_le_set_data_len {
    u16_t handle;
    u16_t tx_octets;
    u16_t tx_time;
} __packed;
struct bt_hci_rp_le_set_data_len {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_READ_DEFAULT_DATA_LEN BT_OP(BT_OGF_LE, 0x0023)
struct bt_hci_rp_le_read_default_data_len {
    u8_t status;
    u16_t max_tx_octets;
    u16_t max_tx_time;
} __packed;

#define BT_HCI_OP_LE_WRITE_DEFAULT_DATA_LEN BT_OP(BT_OGF_LE, 0x0024)
struct bt_hci_cp_le_write_default_data_len {
    u16_t max_tx_octets;
    u16_t max_tx_time;
} __packed;

#define BT_HCI_OP_LE_P256_PUBLIC_KEY BT_OP(BT_OGF_LE, 0x0025)

#define BT_HCI_OP_LE_GENERATE_DHKEY BT_OP(BT_OGF_LE, 0x0026)
struct bt_hci_cp_le_generate_dhkey {
    u8_t key[64];
} __packed;

#define BT_HCI_OP_LE_ADD_DEV_TO_RL BT_OP(BT_OGF_LE, 0x0027)
struct bt_hci_cp_le_add_dev_to_rl {
    bt_addr_le_t peer_id_addr;
    u8_t peer_irk[16];
    u8_t local_irk[16];
} __packed;

#define BT_HCI_OP_LE_REM_DEV_FROM_RL BT_OP(BT_OGF_LE, 0x0028)
struct bt_hci_cp_le_rem_dev_from_rl {
    bt_addr_le_t peer_id_addr;
} __packed;

#define BT_HCI_OP_LE_CLEAR_RL BT_OP(BT_OGF_LE, 0x0029)

#define BT_HCI_OP_LE_READ_RL_SIZE BT_OP(BT_OGF_LE, 0x002a)
struct bt_hci_rp_le_read_rl_size {
    u8_t status;
    u8_t rl_size;
} __packed;

#define BT_HCI_OP_LE_READ_PEER_RPA BT_OP(BT_OGF_LE, 0x002b)
struct bt_hci_cp_le_read_peer_rpa {
    bt_addr_le_t peer_id_addr;
} __packed;
struct bt_hci_rp_le_read_peer_rpa {
    u8_t status;
    bt_addr_t peer_rpa;
} __packed;

#define BT_HCI_OP_LE_READ_LOCAL_RPA BT_OP(BT_OGF_LE, 0x002c)
struct bt_hci_cp_le_read_local_rpa {
    bt_addr_le_t peer_id_addr;
} __packed;
struct bt_hci_rp_le_read_local_rpa {
    u8_t status;
    bt_addr_t local_rpa;
} __packed;

#define BT_HCI_ADDR_RES_DISABLE 0x00
#define BT_HCI_ADDR_RES_ENABLE  0x01

#define BT_HCI_OP_LE_SET_ADDR_RES_ENABLE BT_OP(BT_OGF_LE, 0x002d)
struct bt_hci_cp_le_set_addr_res_enable {
    u8_t enable;
} __packed;

#define BT_HCI_OP_LE_SET_RPA_TIMEOUT BT_OP(BT_OGF_LE, 0x002e)
struct bt_hci_cp_le_set_rpa_timeout {
    u16_t rpa_timeout;
} __packed;

#define BT_HCI_OP_LE_READ_MAX_DATA_LEN BT_OP(BT_OGF_LE, 0x002f)
struct bt_hci_rp_le_read_max_data_len {
    u8_t status;
    u16_t max_tx_octets;
    u16_t max_tx_time;
    u16_t max_rx_octets;
    u16_t max_rx_time;
} __packed;

#define BT_HCI_LE_PHY_1M    0x01
#define BT_HCI_LE_PHY_2M    0x02
#define BT_HCI_LE_PHY_CODED 0x03

#define BT_HCI_OP_LE_READ_PHY BT_OP(BT_OGF_LE, 0x0030)
struct bt_hci_cp_le_read_phy {
    u16_t handle;
} __packed;
struct bt_hci_rp_le_read_phy {
    u8_t status;
    u16_t handle;
    u8_t tx_phy;
    u8_t rx_phy;
} __packed;

#define BT_HCI_LE_PHY_TX_ANY BIT(0)
#define BT_HCI_LE_PHY_RX_ANY BIT(1)

#define BT_HCI_LE_PHY_PREFER_1M    BIT(0)
#define BT_HCI_LE_PHY_PREFER_2M    BIT(1)
#define BT_HCI_LE_PHY_PREFER_CODED BIT(2)

#define BT_HCI_OP_LE_SET_DEFAULT_PHY BT_OP(BT_OGF_LE, 0x0031)
struct bt_hci_cp_le_set_default_phy {
    u8_t all_phys;
    u8_t tx_phys;
    u8_t rx_phys;
} __packed;

#define BT_HCI_LE_PHY_CODED_ANY 0x00
#define BT_HCI_LE_PHY_CODED_S2  0x01
#define BT_HCI_LE_PHY_CODED_S8  0x02

#define BT_HCI_OP_LE_SET_PHY BT_OP(BT_OGF_LE, 0x0032)
struct bt_hci_cp_le_set_phy {
    u16_t handle;
    u8_t all_phys;
    u8_t tx_phys;
    u8_t rx_phys;
    u16_t phy_opts;
} __packed;

#define BT_HCI_LE_MOD_INDEX_STANDARD 0x00
#define BT_HCI_LE_MOD_INDEX_STABLE   0x01

#define BT_HCI_OP_LE_ENH_RX_TEST BT_OP(BT_OGF_LE, 0x0033)
struct bt_hci_cp_le_enh_rx_test {
    u8_t rx_ch;
    u8_t phy;
    u8_t mod_index;
} __packed;

/* Extends BT_HCI_LE_PHY */
#define BT_HCI_LE_TX_PHY_CODED_S8 0x03
#define BT_HCI_LE_TX_PHY_CODED_S2 0x04

#define BT_HCI_OP_LE_ENH_TX_TEST BT_OP(BT_OGF_LE, 0x0034)
struct bt_hci_cp_le_enh_tx_test {
    u8_t tx_ch;
    u8_t test_data_len;
    u8_t pkt_payload;
    u8_t phy;
} __packed;

#define BT_HCI_OP_LE_SET_ADV_SET_RANDOM_ADDR BT_OP(BT_OGF_LE, 0x0035)
struct bt_hci_cp_le_set_adv_set_random_addr {
    u8_t handle;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_LE_ADV_PROP_CONN       BIT(0)
#define BT_HCI_LE_ADV_PROP_SCAN       BIT(1)
#define BT_HCI_LE_ADV_PROP_DIRECT     BIT(2)
#define BT_HCI_LE_ADV_PROP_HI_DC_CONN BIT(3)
#define BT_HCI_LE_ADV_PROP_LEGACY     BIT(4)
#define BT_HCI_LE_ADV_PROP_ANON       BIT(5)
#define BT_HCI_LE_ADV_PROP_TX_POWER   BIT(6)

#define BT_HCI_LE_ADV_SCAN_REQ_ENABLE  1
#define BT_HCI_LE_ADV_SCAN_REQ_DISABLE 0

#define BT_HCI_LE_ADV_TX_POWER_NO_PREF 0x7F

#define BT_HCI_LE_ADV_HANDLE_MAX 0xEF

#define BT_HCI_OP_LE_SET_EXT_ADV_PARAM BT_OP(BT_OGF_LE, 0x0036)
struct bt_hci_cp_le_set_ext_adv_param {
    u8_t handle;
    u16_t props;
    u8_t prim_min_interval[3];
    u8_t prim_max_interval[3];
    u8_t prim_channel_map;
    u8_t own_addr_type;
    bt_addr_le_t peer_addr;
    u8_t filter_policy;
    s8_t tx_power;
    u8_t prim_adv_phy;
    u8_t sec_adv_max_skip;
    u8_t sec_adv_phy;
    u8_t sid;
    u8_t scan_req_notify_enable;
} __packed;
struct bt_hci_rp_le_set_ext_adv_param {
    u8_t status;
    s8_t tx_power;
} __packed;

#define BT_HCI_LE_EXT_ADV_OP_INTERM_FRAG    0x00
#define BT_HCI_LE_EXT_ADV_OP_FIRST_FRAG     0x01
#define BT_HCI_LE_EXT_ADV_OP_LAST_FRAG      0x02
#define BT_HCI_LE_EXT_ADV_OP_COMPLETE_DATA  0x03
#define BT_HCI_LE_EXT_ADV_OP_UNCHANGED_DATA 0x04

#define BT_HCI_LE_EXT_ADV_FRAG_ENABLED  0x00
#define BT_HCI_LE_EXT_ADV_FRAG_DISABLED 0x01

#define BT_HCI_LE_EXT_ADV_FRAG_MAX_LEN 251

#define BT_HCI_OP_LE_SET_EXT_ADV_DATA BT_OP(BT_OGF_LE, 0x0037)
struct bt_hci_cp_le_set_ext_adv_data {
    u8_t handle;
    u8_t op;
    u8_t frag_pref;
    u8_t len;
    u8_t data[251];
} __packed;

#define BT_HCI_OP_LE_SET_EXT_SCAN_RSP_DATA BT_OP(BT_OGF_LE, 0x0038)
struct bt_hci_cp_le_set_ext_scan_rsp_data {
    u8_t handle;
    u8_t op;
    u8_t frag_pref;
    u8_t len;
    u8_t data[251];
} __packed;

#define BT_HCI_OP_LE_SET_EXT_ADV_ENABLE BT_OP(BT_OGF_LE, 0x0039)
struct bt_hci_ext_adv_set {
    u8_t handle;
    u16_t duration;
    u8_t max_ext_adv_evts;
} __packed;

struct bt_hci_cp_le_set_ext_adv_enable {
    u8_t enable;
    u8_t set_num;
    struct bt_hci_ext_adv_set s[0];
} __packed;

#define BT_HCI_OP_LE_READ_MAX_ADV_DATA_LEN BT_OP(BT_OGF_LE, 0x003a)
struct bt_hci_rp_le_read_max_adv_data_len {
    u8_t status;
    u16_t max_adv_data_len;
} __packed;

#define BT_HCI_OP_LE_READ_NUM_ADV_SETS BT_OP(BT_OGF_LE, 0x003b)
struct bt_hci_rp_le_read_num_adv_sets {
    u8_t status;
    u8_t num_sets;
} __packed;

#define BT_HCI_OP_LE_REMOVE_ADV_SET BT_OP(BT_OGF_LE, 0x003c)
struct bt_hci_cp_le_remove_adv_set {
    u8_t handle;
} __packed;

#define BT_HCI_OP_CLEAR_ADV_SETS BT_OP(BT_OGF_LE, 0x003d)

#define BT_HCI_OP_LE_SET_PER_ADV_PARAM BT_OP(BT_OGF_LE, 0x003e)
struct bt_hci_cp_le_set_per_adv_param {
    u8_t handle;
    u16_t min_interval;
    u16_t max_interval;
    u16_t props;
} __packed;

#define BT_HCI_LE_PER_ADV_OP_INTERM_FRAG   0x00
#define BT_HCI_LE_PER_ADV_OP_FIRST_FRAG    0x01
#define BT_HCI_LE_PER_ADV_OP_LAST_FRAG     0x02
#define BT_HCI_LE_PER_ADV_OP_COMPLETE_DATA 0x03

#define BT_HCI_LE_PER_ADV_FRAG_MAX_LEN 252

#define BT_HCI_OP_LE_SET_PER_ADV_DATA BT_OP(BT_OGF_LE, 0x003f)
struct bt_hci_cp_le_set_per_adv_data {
    u8_t handle;
    u8_t op;
    u8_t len;
    u8_t data[251];
} __packed;

#define BT_HCI_OP_LE_SET_PER_ADV_ENABLE BT_OP(BT_OGF_LE, 0x0040)
struct bt_hci_cp_le_set_per_adv_enable {
    u8_t enable;
    u8_t handle;
} __packed;

#define BT_HCI_OP_LE_SET_EXT_SCAN_PARAM BT_OP(BT_OGF_LE, 0x0041)
struct bt_hci_ext_scan_phy {
    u8_t type;
    u16_t interval;
    u16_t window;
} __packed;

#define BT_HCI_LE_EXT_SCAN_PHY_1M    BIT(0)
#define BT_HCI_LE_EXT_SCAN_PHY_2M    BIT(1)
#define BT_HCI_LE_EXT_SCAN_PHY_CODED BIT(2)

struct bt_hci_cp_le_set_ext_scan_param {
    u8_t own_addr_type;
    u8_t filter_policy;
    u8_t phys;
    struct bt_hci_ext_scan_phy p[0];
} __packed;

/* Extends BT_HCI_LE_SCAN_FILTER_DUP */
#define BT_HCI_LE_EXT_SCAN_FILTER_DUP_ENABLE_RESET 0x02

#define BT_HCI_OP_LE_SET_EXT_SCAN_ENABLE BT_OP(BT_OGF_LE, 0x0042)
struct bt_hci_cp_le_set_ext_scan_enable {
    u8_t enable;
    u8_t filter_dup;
    u16_t duration;
    u16_t period;
} __packed;

#define BT_HCI_OP_LE_EXT_CREATE_CONN BT_OP(BT_OGF_LE, 0x0043)
struct bt_hci_ext_conn_phy {
    u16_t interval;
    u16_t window;
    u16_t conn_interval_min;
    u16_t conn_interval_max;
    u16_t conn_latency;
    u16_t supervision_timeout;
    u16_t min_ce_len;
    u16_t max_ce_len;
} __packed;

struct bt_hci_cp_le_ext_create_conn {
    u8_t filter_policy;
    u8_t own_addr_type;
    bt_addr_le_t peer_addr;
    u8_t phys;
    struct bt_hci_ext_conn_phy p[0];
} __packed;

#define BT_HCI_LE_PER_ADV_CREATE_SYNC_FP_USE_LIST         BIT(0)
#define BT_HCI_LE_PER_ADV_CREATE_SYNC_FP_REPORTS_DISABLED BIT(1)

#define BT_HCI_LE_PER_ADV_CREATE_SYNC_CTE_TYPE_NO_AOA     BIT(0)
#define BT_HCI_LE_PER_ADV_CREATE_SYNC_CTE_TYPE_NO_AOD_1US BIT(1)
#define BT_HCI_LE_PER_ADV_CREATE_SYNC_CTE_TYPE_NO_AOD_2US BIT(2)
#define BT_HCI_LE_PER_ADV_CREATE_SYNC_CTE_TYPE_NO_CTE     BIT(3)
#define BT_HCI_LE_PER_ADV_CREATE_SYNC_CTE_TYPE_ONLY_CTE   BIT(4)

#define BT_HCI_OP_LE_PER_ADV_CREATE_SYNC BT_OP(BT_OGF_LE, 0x0044)
struct bt_hci_cp_le_per_adv_create_sync {
    u8_t filter_policy;
    u8_t sid;
    bt_addr_le_t addr;
    u16_t skip;
    u16_t sync_timeout;
    u8_t unused;
} __packed;

#define BT_HCI_OP_LE_PER_ADV_CREATE_SYNC_CANCEL BT_OP(BT_OGF_LE, 0x0045)

#define BT_HCI_OP_LE_PER_ADV_TERMINATE_SYNC BT_OP(BT_OGF_LE, 0x0046)
struct bt_hci_cp_le_per_adv_terminate_sync {
    u16_t handle;
} __packed;

#define BT_HCI_OP_LE_ADD_DEV_TO_PER_ADV_LIST BT_OP(BT_OGF_LE, 0x0047)
struct bt_hci_cp_le_add_dev_to_per_adv_list {
    bt_addr_le_t addr;
    u8_t sid;
} __packed;

#define BT_HCI_OP_LE_REM_DEV_FROM_PER_ADV_LIST BT_OP(BT_OGF_LE, 0x0048)
struct bt_hci_cp_le_rem_dev_from_per_adv_list {
    bt_addr_le_t addr;
    u8_t sid;
} __packed;

#define BT_HCI_OP_LE_CLEAR_PER_ADV_LIST BT_OP(BT_OGF_LE, 0x0049)

#define BT_HCI_OP_LE_READ_PER_ADV_LIST_SIZE BT_OP(BT_OGF_LE, 0x004a)
struct bt_hci_rp_le_read_per_adv_list_size {
    u8_t status;
    u8_t list_size;
} __packed;

#define BT_HCI_OP_LE_READ_TX_POWER BT_OP(BT_OGF_LE, 0x004b)
struct bt_hci_rp_le_read_tx_power {
    u8_t status;
    s8_t min_tx_power;
    s8_t max_tx_power;
} __packed;

#define BT_HCI_OP_LE_READ_RF_PATH_COMP BT_OP(BT_OGF_LE, 0x004c)
struct bt_hci_rp_le_read_rf_path_comp {
    u8_t status;
    s16_t tx_path_comp;
    s16_t rx_path_comp;
} __packed;

#define BT_HCI_OP_LE_WRITE_RF_PATH_COMP BT_OP(BT_OGF_LE, 0x004d)
struct bt_hci_cp_le_write_rf_path_comp {
    s16_t tx_path_comp;
    s16_t rx_path_comp;
} __packed;

#define BT_HCI_LE_PRIVACY_MODE_NETWORK 0x00
#define BT_HCI_LE_PRIVACY_MODE_DEVICE  0x01

#define BT_HCI_OP_LE_SET_PRIVACY_MODE BT_OP(BT_OGF_LE, 0x004e)
struct bt_hci_cp_le_set_privacy_mode {
    bt_addr_le_t id_addr;
    u8_t mode;
} __packed;

#define BT_HCI_OP_LE_SET_CL_CTE_TX_ENABLE BT_OP(BT_OGF_LE, 0x0052)
struct bt_hci_cp_le_set_cl_cte_tx_enable {
    uint8_t handle;
    uint8_t cte_enable;
} __packed;

/* Min and max Constant Tone Extension length in 8us units */
#define BT_HCI_LE_CTE_LEN_MIN 0x2
#define BT_HCI_LE_CTE_LEN_MAX 0x14

#define BT_HCI_LE_AOA_CTE     0x1
#define BT_HCI_LE_AOD_CTE_1US 0x2
#define BT_HCI_LE_AOD_CTE_2US 0x3

#define BT_HCI_LE_CTE_COUNT_MIN 0x1
#define BT_HCI_LE_CTE_COUNT_MAX 0x10

#define BT_HCI_OP_LE_SET_CL_CTE_TX_PARAMS BT_OP(BT_OGF_LE, 0x0051)
struct bt_hci_cp_le_set_cl_cte_tx_params {
    uint8_t handle;
    uint8_t cte_len;
    uint8_t cte_type;
    uint8_t cte_count;
    uint8_t switch_pattern_len;
    uint8_t ant_ids[0];
} __packed;

#define BT_HCI_LE_AOA_CTE_RSP     BIT(0)
#define BT_HCI_LE_AOD_CTE_RSP_1US BIT(1)
#define BT_HCI_LE_AOD_CTE_RSP_2US BIT(2)

#define BT_HCI_LE_SWITCH_PATTERN_LEN_MIN 0x2
#define BT_HCI_LE_SWITCH_PATTERN_LEN_MAX 0x4B

#define BT_HCI_OP_LE_SET_CONN_CTE_TX_PARAMS BT_OP(BT_OGF_LE, 0x0055)
struct bt_hci_cp_le_set_conn_cte_tx_params {
    uint16_t handle;
    uint8_t cte_types;
    uint8_t switch_pattern_len;
    uint8_t ant_id[0];
} __packed;

struct bt_hci_rp_le_set_conn_cte_tx_params {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_LE_1US_AOD_TX BIT(0)
#define BT_HCI_LE_1US_AOD_RX BIT(1)
#define BT_HCI_LE_1US_AOA_RX BIT(2)

#define BT_HCI_LE_NUM_ANT_MIN 0x1
#define BT_HCI_LE_NUM_ANT_MAX 0x4B

#define BT_HCI_LE_MAX_SWITCH_PATTERN_LEN_MIN 0x2
#define BT_HCI_LE_MAX_SWITCH_PATTERN_LEN_MAX 0x4B

#define BT_HCI_LE_MAX_CTE_LEN_MIN 0x2
#define BT_HCI_LE_MAX_CTE_LEN_MAX 0x14

#define BT_HCI_OP_LE_READ_ANT_INFO BT_OP(BT_OGF_LE, 0x0058)
struct bt_hci_rp_le_read_ant_info {
    uint8_t status;
    uint8_t switch_sample_rates;
    uint8_t num_ant;
    uint8_t max_switch_pattern_len;
    uint8_t max_cte_len;
};

#define BT_HCI_OP_LE_SET_PER_ADV_RECV_ENABLE BT_OP(BT_OGF_LE, 0x0059)
struct bt_hci_cp_le_set_per_adv_recv_enable {
    uint16_t handle;
    uint8_t enable;
} __packed;

#define BT_HCI_OP_LE_PER_ADV_SYNC_TRANSFER BT_OP(BT_OGF_LE, 0x005a)
struct bt_hci_cp_le_per_adv_sync_transfer {
    uint16_t conn_handle;
    uint16_t service_data;
    uint16_t sync_handle;
} __packed;

struct bt_hci_rp_le_per_adv_sync_transfer {
    uint8_t status;
    uint16_t conn_handle;
} __packed;

#define BT_HCI_OP_LE_PER_ADV_SET_INFO_TRANSFER BT_OP(BT_OGF_LE, 0x005b)
struct bt_hci_cp_le_per_adv_set_info_transfer {
    uint16_t conn_handle;
    uint16_t service_data;
    uint8_t adv_handle;
} __packed;

struct bt_hci_rp_le_per_adv_set_info_transfer {
    uint8_t status;
    uint16_t conn_handle;
} __packed;

#define BT_HCI_LE_PAST_MODE_NO_SYNC    0x00
#define BT_HCI_LE_PAST_MODE_NO_REPORTS 0x01
#define BT_HCI_LE_PAST_MODE_SYNC       0x02

#define BT_HCI_LE_PAST_CTE_TYPE_NO_AOA     BIT(0)
#define BT_HCI_LE_PAST_CTE_TYPE_NO_AOD_1US BIT(1)
#define BT_HCI_LE_PAST_CTE_TYPE_NO_AOD_2US BIT(2)
#define BT_HCI_LE_PAST_CTE_TYPE_NO_CTE     BIT(3)
#define BT_HCI_LE_PAST_CTE_TYPE_ONLY_CTE   BIT(4)

#define BT_HCI_OP_LE_PAST_PARAM BT_OP(BT_OGF_LE, 0x005c)
struct bt_hci_cp_le_past_param {
    uint16_t conn_handle;
    uint8_t mode;
    uint16_t skip;
    uint16_t timeout;
    uint8_t cte_type;
} __packed;

struct bt_hci_rp_le_past_param {
    uint8_t status;
    uint16_t conn_handle;
} __packed;

#define BT_HCI_OP_LE_DEFAULT_PAST_PARAM BT_OP(BT_OGF_LE, 0x005d)
struct bt_hci_cp_le_default_past_param {
    uint8_t mode;
    uint16_t skip;
    uint16_t timeout;
    uint8_t cte_type;
} __packed;

struct bt_hci_rp_le_default_past_param {
    uint8_t status;
} __packed;

#define BT_HCI_OP_LE_READ_BUFFER_SIZE_V2 BT_OP(BT_OGF_LE, 0x0060)
struct bt_hci_rp_le_read_buffer_size_v2 {
    uint8_t status;
    uint16_t acl_mtu;
    uint8_t acl_max_pkt;
    uint16_t iso_mtu;
    uint8_t iso_max_pkt;
} __packed;

#define BT_HCI_OP_LE_READ_ISO_TX_SYNC BT_OP(BT_OGF_LE, 0x0061)
struct bt_hci_cp_le_read_iso_tx_sync {
    uint16_t handle;
} __packed;

struct bt_hci_rp_le_read_iso_tx_sync {
    uint8_t status;
    uint16_t handle;
    uint16_t seq;
    uint32_t timestamp;
    uint8_t offset[3];
} __packed;

#define BT_HCI_OP_LE_SET_CIG_PARAMS BT_OP(BT_OGF_LE, 0x0062)
struct bt_hci_cis_params {
    uint8_t cis_id;
    uint16_t m_sdu;
    uint16_t s_sdu;
    uint8_t m_phy;
    uint8_t s_phy;
    uint8_t m_rtn;
    uint8_t s_rtn;
} __packed;

struct bt_hci_cp_le_set_cig_params {
    uint8_t cig_id;
    uint8_t m_interval[3];
    uint8_t s_interval[3];
    uint8_t sca;
    uint8_t packing;
    uint8_t framing;
    uint16_t m_latency;
    uint16_t s_latency;
    uint8_t num_cis;
    struct bt_hci_cis_params cis[0];
} __packed;

struct bt_hci_rp_le_set_cig_params {
    uint8_t status;
    uint8_t cig_id;
    uint8_t num_handles;
    uint16_t handle[0];
} __packed;

#define BT_HCI_OP_LE_SET_CIG_PARAMS_TEST BT_OP(BT_OGF_LE, 0x0063)
struct bt_hci_cis_params_test {
    uint8_t cis_id;
    uint8_t nse;
    uint16_t m_sdu;
    uint16_t s_sdu;
    uint16_t m_pdu;
    uint16_t s_pdu;
    uint8_t m_phy;
    uint8_t s_phy;
    uint8_t m_bn;
    uint8_t s_bn;
} __packed;

struct bt_hci_cp_le_set_cig_params_test {
    uint8_t cig_id;
    uint8_t m_interval[3];
    uint8_t s_interval[3];
    uint8_t m_ft;
    uint8_t s_ft;
    uint16_t iso_interval;
    uint8_t sca;
    uint8_t packing;
    uint8_t framing;
    uint8_t num_cis;
    struct bt_hci_cis_params_test cis[0];
} __packed;

struct bt_hci_rp_le_set_cig_params_test {
    uint8_t status;
    uint8_t cig_id;
    uint8_t num_handles;
    uint16_t handle[0];
} __packed;

#define BT_HCI_OP_LE_CREATE_CIS BT_OP(BT_OGF_LE, 0x0064)
struct bt_hci_cis {
    uint16_t cis_handle;
    uint16_t acl_handle;
} __packed;

struct bt_hci_cp_le_create_cis {
    uint8_t num_cis;
    struct bt_hci_cis cis[0];
} __packed;

#define BT_HCI_OP_LE_REMOVE_CIG BT_OP(BT_OGF_LE, 0x0065)
struct bt_hci_cp_le_remove_cig {
    uint8_t cig_id;
} __packed;

struct bt_hci_rp_le_remove_cig {
    uint8_t status;
    uint8_t cig_id;
} __packed;

#define BT_HCI_OP_LE_ACCEPT_CIS BT_OP(BT_OGF_LE, 0x0066)
struct bt_hci_cp_le_accept_cis {
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_REJECT_CIS BT_OP(BT_OGF_LE, 0x0067)
struct bt_hci_cp_le_reject_cis {
    uint16_t handle;
    uint8_t reason;
} __packed;

struct bt_hci_rp_le_reject_cis {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_CREATE_BIG BT_OP(BT_OGF_LE, 0x0068)
struct bt_hci_cp_le_create_big {
    uint8_t big_handle;
    uint8_t adv_handle;
    uint8_t num_bis;
    uint8_t sdu_interval[3];
    uint16_t max_sdu;
    uint16_t max_latency;
    uint8_t rtn;
    uint8_t phy;
    uint8_t packing;
    uint8_t framing;
    uint8_t encryption;
    uint8_t bcode[16];
} __packed;

#define BT_HCI_OP_LE_CREATE_BIG_TEST BT_OP(BT_OGF_LE, 0x0069)
struct bt_hci_cp_le_create_big_test {
    uint8_t big_handle;
    uint8_t adv_handle;
    uint8_t num_bis;
    uint8_t sdu_interval[3];
    uint16_t iso_interval;
    uint8_t nse;
    uint16_t max_sdu;
    uint16_t max_pdu;
    uint8_t phy;
    uint8_t packing;
    uint8_t framing;
    uint8_t bn;
    uint8_t irc;
    uint8_t pto;
    uint8_t encryption;
    uint8_t bcode[16];
} __packed;

#define BT_HCI_OP_LE_TERMINATE_BIG BT_OP(BT_OGF_LE, 0x006a)
struct bt_hci_cp_le_terminate_big {
    uint8_t big_handle;
    uint8_t reason;
} __packed;

#define BT_HCI_OP_LE_BIG_CREATE_SYNC BT_OP(BT_OGF_LE, 0x006b)
struct bt_hci_cp_le_big_create_sync {
    uint8_t big_handle;
    uint16_t sync_handle;
    uint8_t encryption;
    uint8_t bcode[16];
    uint8_t mse;
    uint16_t sync_timeout;
    uint8_t num_bis;
    uint8_t bis[0];
} __packed;

#define BT_HCI_OP_LE_BIG_TERMINATE_SYNC BT_OP(BT_OGF_LE, 0x006c)
struct bt_hci_cp_le_big_terminate_sync {
    uint8_t big_handle;
} __packed;

struct bt_hci_rp_le_big_terminate_sync {
    uint8_t status;
    uint8_t big_handle;
} __packed;

#define BT_HCI_OP_LE_REQ_PEER_SC BT_OP(BT_OGF_LE, 0x006d)
struct bt_hci_cp_le_req_peer_sca {
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_SETUP_ISO_PATH BT_OP(BT_OGF_LE, 0x006e)
struct bt_hci_cp_le_setup_iso_path {
    uint16_t handle;
    uint8_t path_dir;
    uint8_t path_id;
    struct bt_hci_cp_codec_id codec_id;
    uint8_t controller_delay[3];
    uint8_t codec_config_len;
    uint8_t codec_config[0];
} __packed;

struct bt_hci_rp_le_setup_iso_path {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_REMOVE_ISO_PATH BT_OP(BT_OGF_LE, 0x006f)
struct bt_hci_cp_le_remove_iso_path {
    uint16_t handle;
    uint8_t path_dir;
} __packed;

struct bt_hci_rp_le_remove_iso_path {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_ISO_TRANSMIT_TEST BT_OP(BT_OGF_LE, 0x0070)
struct bt_hci_cp_le_iso_transmit_test {
    uint16_t handle;
    uint8_t payload_type;
} __packed;

struct bt_hci_rp_le_iso_transmit_test {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_ISO_RECEIVE_TEST BT_OP(BT_OGF_LE, 0x0071)
struct bt_hci_cp_le_iso_receive_test {
    uint16_t handle;
    uint8_t payload_type;
} __packed;

struct bt_hci_rp_le_iso_receive_test {
    uint8_t status;
    uint16_t handle;
} __packed;

#define BT_HCI_OP_LE_ISO_READ_TEST_COUNTERS BT_OP(BT_OGF_LE, 0x0072)
struct bt_hci_cp_le_read_test_counters {
    uint16_t handle;
} __packed;

struct bt_hci_rp_le_read_test_counters {
    uint8_t status;
    uint16_t handle;
    uint32_t received_cnt;
    uint32_t missed_cnt;
    uint32_t failed_cnt;
} __packed;

#define BT_HCI_OP_LE_ISO_TEST_END BT_OP(BT_OGF_LE, 0x0073)
struct bt_hci_cp_le_iso_test_end {
    uint16_t handle;
} __packed;

struct bt_hci_rp_le_iso_test_end {
    uint8_t status;
    uint16_t handle;
    uint32_t received_cnt;
    uint32_t missed_cnt;
    uint32_t failed_cnt;
} __packed;

#define BT_HCI_OP_LE_SET_HOST_FEATURE BT_OP(BT_OGF_LE, 0x0074)
struct bt_hci_cp_le_set_host_feature {
    uint8_t bit_number;
    uint8_t bit_value;
} __packed;

struct bt_hci_rp_le_set_host_feature {
    uint8_t status;
} __packed;

#define BT_HCI_OP_LE_READ_ISO_LINK_QUALITY BT_OP(BT_OGF_LE, 0x0075)
struct bt_hci_cp_le_read_iso_link_quality {
    uint16_t handle;
} __packed;

struct bt_hci_rp_le_read_iso_link_quality {
    uint8_t status;
    uint16_t handle;
    uint32_t tx_unacked_packets;
    uint32_t tx_flushed_packets;
    uint32_t tx_last_subevent_packets;
    uint32_t retransmitted_packets;
    uint32_t crc_error_packets;
    uint32_t rx_unreceived_packets;
    uint32_t duplicate_packets;
} __packed;

/* Event definitions */
#if defined(BFLB_BLE)
#define BT_HCI_EVT_CC_PARAM_OFFSET 0x05
#define BT_HCI_CCEVT_HDR_PARLEN    0x03
#define BT_HCI_CSEVT_LEN           0x06
#define BT_HCI_CSVT_PARLEN         0x04
#define BT_HCI_EVT_LE_PARAM_OFFSET 0x02
#endif

#define BT_HCI_EVT_UNKNOWN 0x00
#define BT_HCI_EVT_VENDOR  0xff

#define BT_HCI_EVT_INQUIRY_COMPLETE 0x01
struct bt_hci_evt_inquiry_complete {
    u8_t status;
} __packed;

#define BT_HCI_EVT_CONN_COMPLETE 0x03
struct bt_hci_evt_conn_complete {
    u8_t status;
    u16_t handle;
    bt_addr_t bdaddr;
    u8_t link_type;
    u8_t encr_enabled;
} __packed;

#define BT_HCI_EVT_CONN_REQUEST 0x04
struct bt_hci_evt_conn_request {
    bt_addr_t bdaddr;
    u8_t dev_class[3];
    u8_t link_type;
} __packed;

#define BT_HCI_EVT_DISCONN_COMPLETE 0x05
struct bt_hci_evt_disconn_complete {
    u8_t status;
    u16_t handle;
    u8_t reason;
} __packed;

#define BT_HCI_EVT_AUTH_COMPLETE 0x06
struct bt_hci_evt_auth_complete {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_EVT_REMOTE_NAME_REQ_COMPLETE 0x07
struct bt_hci_evt_remote_name_req_complete {
    u8_t status;
    bt_addr_t bdaddr;
    u8_t name[248];
} __packed;

#define BT_HCI_EVT_ENCRYPT_CHANGE 0x08
struct bt_hci_evt_encrypt_change {
    u8_t status;
    u16_t handle;
    u8_t encrypt;
} __packed;

#define BT_HCI_EVT_REMOTE_FEATURES 0x0b
struct bt_hci_evt_remote_features {
    u8_t status;
    u16_t handle;
    u8_t features[8];
} __packed;

#define BT_HCI_EVT_REMOTE_VERSION_INFO 0x0c
struct bt_hci_evt_remote_version_info {
    u8_t status;
    u16_t handle;
    u8_t version;
    u16_t manufacturer;
    u16_t subversion;
} __packed;

#define BT_HCI_EVT_CMD_COMPLETE 0x0e
struct bt_hci_evt_cmd_complete {
    u8_t ncmd;
    u16_t opcode;
} __packed;

struct bt_hci_evt_cc_status {
    u8_t status;
} __packed;

#define BT_HCI_EVT_CMD_STATUS 0x0f
struct bt_hci_evt_cmd_status {
    u8_t status;
    u8_t ncmd;
    u16_t opcode;
} __packed;

#define BT_HCI_EVT_HARDWARE_ERROR 0x10
struct bt_hci_evt_hardware_error {
    uint8_t hardware_code;
} __packed;

#define BT_HCI_EVT_ROLE_CHANGE 0x12
struct bt_hci_evt_role_change {
    u8_t status;
    bt_addr_t bdaddr;
    u8_t role;
} __packed;

#define BT_HCI_EVT_NUM_COMPLETED_PACKETS 0x13
struct bt_hci_evt_num_completed_packets {
    u8_t num_handles;
    struct bt_hci_handle_count h[0];
} __packed;

#define BT_HCI_EVT_PIN_CODE_REQ 0x16
struct bt_hci_evt_pin_code_req {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_EVT_LINK_KEY_REQ 0x17
struct bt_hci_evt_link_key_req {
    bt_addr_t bdaddr;
} __packed;

/* Link Key types */
#define BT_LK_COMBINATION             0x00
#define BT_LK_LOCAL_UNIT              0x01
#define BT_LK_REMOTE_UNIT             0x02
#define BT_LK_DEBUG_COMBINATION       0x03
#define BT_LK_UNAUTH_COMBINATION_P192 0x04
#define BT_LK_AUTH_COMBINATION_P192   0x05
#define BT_LK_CHANGED_COMBINATION     0x06
#define BT_LK_UNAUTH_COMBINATION_P256 0x07
#define BT_LK_AUTH_COMBINATION_P256   0x08

#define BT_HCI_EVT_LINK_KEY_NOTIFY 0x18
struct bt_hci_evt_link_key_notify {
    bt_addr_t bdaddr;
    u8_t link_key[16];
    u8_t key_type;
} __packed;

/* Overflow link types */
#define BT_OVERFLOW_LINK_SYNCH 0x00
#define BT_OVERFLOW_LINK_ACL   0x01

#define BT_HCI_EVT_DATA_BUF_OVERFLOW 0x1a
struct bt_hci_evt_data_buf_overflow {
    u8_t link_type;
} __packed;

#define BT_HCI_EVT_INQUIRY_RESULT_WITH_RSSI 0x22
struct bt_hci_evt_inquiry_result_with_rssi {
    bt_addr_t addr;
    u8_t pscan_rep_mode;
    u8_t reserved;
    u8_t cod[3];
    u16_t clock_offset;
    s8_t rssi;
} __packed;

#define BT_HCI_EVT_REMOTE_EXT_FEATURES 0x23
struct bt_hci_evt_remote_ext_features {
    u8_t status;
    u16_t handle;
    u8_t page;
    u8_t max_page;
    u8_t features[8];
} __packed;

#define BT_HCI_EVT_SYNC_CONN_COMPLETE 0x2c
struct bt_hci_evt_sync_conn_complete {
    u8_t status;
    u16_t handle;
    bt_addr_t bdaddr;
    u8_t link_type;
    u8_t tx_interval;
    u8_t retansmission_window;
    u16_t rx_pkt_length;
    u16_t tx_pkt_length;
    u8_t air_mode;
} __packed;

#define BT_HCI_EVT_EXTENDED_INQUIRY_RESULT 0x2f
struct bt_hci_evt_extended_inquiry_result {
    u8_t num_reports;
    bt_addr_t addr;
    u8_t pscan_rep_mode;
    u8_t reserved;
    u8_t cod[3];
    u16_t clock_offset;
    s8_t rssi;
    u8_t eir[240];
} __packed;

#define BT_HCI_EVT_ENCRYPT_KEY_REFRESH_COMPLETE 0x30
struct bt_hci_evt_encrypt_key_refresh_complete {
    u8_t status;
    u16_t handle;
} __packed;

#define BT_HCI_EVT_IO_CAPA_REQ 0x31
struct bt_hci_evt_io_capa_req {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_EVT_IO_CAPA_RESP 0x32
struct bt_hci_evt_io_capa_resp {
    bt_addr_t bdaddr;
    u8_t capability;
    u8_t oob_data;
    u8_t authentication;
} __packed;

#define BT_HCI_EVT_USER_CONFIRM_REQ 0x33
struct bt_hci_evt_user_confirm_req {
    bt_addr_t bdaddr;
    u32_t passkey;
} __packed;

#define BT_HCI_EVT_USER_PASSKEY_REQ 0x34
struct bt_hci_evt_user_passkey_req {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_EVT_SSP_COMPLETE 0x36
struct bt_hci_evt_ssp_complete {
    u8_t status;
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_EVT_USER_PASSKEY_NOTIFY 0x3b
struct bt_hci_evt_user_passkey_notify {
    bt_addr_t bdaddr;
    u32_t passkey;
} __packed;

#define BT_HCI_EVT_LE_META_EVENT 0x3e
struct bt_hci_evt_le_meta_event {
    u8_t subevent;
} __packed;

#define BT_HCI_EVT_AUTH_PAYLOAD_TIMEOUT_EXP 0x57
struct bt_hci_evt_auth_payload_timeout_exp {
    u16_t handle;
} __packed;

#define BT_HCI_ROLE_MASTER 0x00
#define BT_HCI_ROLE_SLAVE  0x01

#define BT_HCI_EVT_LE_CONN_COMPLETE 0x01
struct bt_hci_evt_le_conn_complete {
    u8_t status;
    u16_t handle;
    u8_t role;
    bt_addr_le_t peer_addr;
    u16_t interval;
    u16_t latency;
    u16_t supv_timeout;
    u8_t clock_accuracy;
} __packed;

#define BT_HCI_EVT_LE_ADVERTISING_REPORT 0x02
struct bt_hci_evt_le_advertising_info {
    u8_t evt_type;
    bt_addr_le_t addr;
    u8_t length;
    u8_t data[0];
} __packed;
struct bt_hci_evt_le_advertising_report {
    u8_t num_reports;
    struct bt_hci_evt_le_advertising_info adv_info[0];
} __packed;

#define BT_HCI_EVT_LE_CONN_UPDATE_COMPLETE 0x03
struct bt_hci_evt_le_conn_update_complete {
    u8_t status;
    u16_t handle;
    u16_t interval;
    u16_t latency;
    u16_t supv_timeout;
} __packed;

#define BT_HCI_EV_LE_REMOTE_FEAT_COMPLETE 0x04
struct bt_hci_evt_le_remote_feat_complete {
    u8_t status;
    u16_t handle;
    u8_t features[8];
} __packed;

#define BT_HCI_EVT_LE_LTK_REQUEST 0x05
struct bt_hci_evt_le_ltk_request {
    u16_t handle;
    u64_t rand;
    u16_t ediv;
} __packed;

#define BT_HCI_EVT_LE_CONN_PARAM_REQ 0x06
struct bt_hci_evt_le_conn_param_req {
    u16_t handle;
    u16_t interval_min;
    u16_t interval_max;
    u16_t latency;
    u16_t timeout;
} __packed;

#define BT_HCI_EVT_LE_DATA_LEN_CHANGE 0x07
struct bt_hci_evt_le_data_len_change {
    u16_t handle;
    u16_t max_tx_octets;
    u16_t max_tx_time;
    u16_t max_rx_octets;
    u16_t max_rx_time;
} __packed;

#define BT_HCI_EVT_LE_P256_PUBLIC_KEY_COMPLETE 0x08
struct bt_hci_evt_le_p256_public_key_complete {
    u8_t status;
    u8_t key[64];
} __packed;

#define BT_HCI_EVT_LE_GENERATE_DHKEY_COMPLETE 0x09
struct bt_hci_evt_le_generate_dhkey_complete {
    u8_t status;
    u8_t dhkey[32];
} __packed;

#define BT_HCI_EVT_LE_ENH_CONN_COMPLETE 0x0a
struct bt_hci_evt_le_enh_conn_complete {
    u8_t status;
    u16_t handle;
    u8_t role;
    bt_addr_le_t peer_addr;
    bt_addr_t local_rpa;
    bt_addr_t peer_rpa;
    u16_t interval;
    u16_t latency;
    u16_t supv_timeout;
    u8_t clock_accuracy;
} __packed;

#define BT_HCI_EVT_LE_DIRECT_ADV_REPORT 0x0b
struct bt_hci_evt_le_direct_adv_info {
    u8_t evt_type;
    bt_addr_le_t addr;
    bt_addr_le_t dir_addr;
    s8_t rssi;
} __packed;
struct bt_hci_evt_le_direct_adv_report {
    u8_t num_reports;
    struct bt_hci_evt_le_direct_adv_info direct_adv_info[0];
} __packed;

#define BT_HCI_EVT_LE_PHY_UPDATE_COMPLETE 0x0c
struct bt_hci_evt_le_phy_update_complete {
    u8_t status;
    u16_t handle;
    u8_t tx_phy;
    u8_t rx_phy;
} __packed;

#define BT_HCI_EVT_LE_EXT_ADVERTISING_REPORT 0x0d

#define BT_HCI_LE_ADV_EVT_TYPE_CONN     BIT(0)
#define BT_HCI_LE_ADV_EVT_TYPE_SCAN     BIT(1)
#define BT_HCI_LE_ADV_EVT_TYPE_DIRECT   BIT(2)
#define BT_HCI_LE_ADV_EVT_TYPE_SCAN_RSP BIT(3)
#define BT_HCI_LE_ADV_EVT_TYPE_LEGACY   BIT(4)

#define BT_HCI_LE_ADV_EVT_TYPE_DATA_STATUS(ev_type)   (((ev_type) >> 5) & 0x03)
#define BT_HCI_LE_ADV_EVT_TYPE_DATA_STATUS_COMPLETE   0
#define BT_HCI_LE_ADV_EVT_TYPE_DATA_STATUS_PARTIAL    1
#define BT_HCI_LE_ADV_EVT_TYPE_DATA_STATUS_INCOMPLETE 2

struct bt_hci_evt_le_ext_advertising_info {
    u8_t evt_type;
    bt_addr_le_t addr;
    u8_t prim_phy;
    u8_t sec_phy;
    u8_t sid;
    s8_t tx_power;
    s8_t rssi;
    u16_t interval;
    bt_addr_le_t direct_addr;
    u8_t length;
    u8_t data[0];
} __packed;
struct bt_hci_evt_le_ext_advertising_report {
    u8_t num_reports;
    struct bt_hci_evt_le_ext_advertising_info adv_info[0];
} __packed;

#define BT_HCI_EVT_LE_PER_ADV_SYNC_ESTABLISHED 0x0e
struct bt_hci_evt_le_per_adv_sync_established {
    u8_t status;
    u16_t handle;
    u8_t sid;
    bt_addr_le_t adv_addr;
    u8_t phy;
    u16_t interval;
    u8_t clock_accuracy;
} __packed;

#define BT_HCI_EVT_LE_PER_ADVERTISING_REPORT 0x0f
struct bt_hci_evt_le_per_advertising_report {
    u16_t handle;
    s8_t tx_power;
    s8_t rssi;
    u8_t unused;
    u8_t data_status;
    u8_t length;
    u8_t data[0];
} __packed;

#define BT_HCI_EVT_LE_PER_ADV_SYNC_LOST 0x10
struct bt_hci_evt_le_per_adv_sync_lost {
    u16_t handle;
} __packed;

#define BT_HCI_EVT_LE_SCAN_TIMEOUT 0x11

#define BT_HCI_EVT_LE_ADV_SET_TERMINATED 0x12
struct bt_hci_evt_le_per_adv_set_terminated {
    u8_t status;
    u8_t adv_handle;
    u16_t conn_handle;
    u8_t num_completed_ext_adv_evts;
} __packed;

#define BT_HCI_EVT_LE_SCAN_REQ_RECEIVED 0x13
struct bt_hci_evt_le_scan_req_received {
    u8_t handle;
    bt_addr_le_t addr;
} __packed;

#define BT_HCI_LE_CHAN_SEL_ALGO_1 0x00
#define BT_HCI_LE_CHAN_SEL_ALGO_2 0x01

#define BT_HCI_EVT_LE_CHAN_SEL_ALGO 0x14
struct bt_hci_evt_le_chan_sel_algo {
    u16_t handle;
    u8_t chan_sel_algo;
} __packed;

#define BT_HCI_EVT_LE_PAST_RECEIVED 0x18
struct bt_hci_evt_le_past_received {
    uint8_t status;
    uint16_t conn_handle;
    uint16_t service_data;
    uint16_t sync_handle;
    uint8_t adv_sid;
    bt_addr_le_t addr;
    uint8_t phy;
    uint16_t interval;
    uint8_t clock_accuracy;
} __packed;

#define BT_HCI_EVT_LE_CIS_ESTABLISHED 0x19
struct bt_hci_evt_le_cis_established {
    uint8_t status;
    uint16_t conn_handle;
    uint8_t cig_sync_delay[3];
    uint8_t cis_sync_delay[3];
    uint8_t m_latency[3];
    uint8_t s_latency[3];
    uint8_t m_phy;
    uint8_t s_phy;
    uint8_t nse;
    uint8_t m_bn;
    uint8_t s_bn;
    uint8_t m_ft;
    uint8_t s_ft;
    uint16_t m_max_pdu;
    uint16_t s_max_pdu;
    uint16_t interval;
} __packed;

#define BT_HCI_EVT_LE_CIS_REQ 0x1a
struct bt_hci_evt_le_cis_req {
    uint16_t acl_handle;
    uint16_t cis_handle;
    uint8_t cig_id;
    uint8_t cis_id;
} __packed;

#define BT_HCI_EVT_LE_BIG_COMPLETE 0x1b
struct bt_hci_evt_le_big_complete {
    uint8_t status;
    uint8_t big_handle;
    uint8_t sync_delay[3];
    uint8_t latency[3];
    uint8_t phy;
    uint8_t nse;
    uint8_t bn;
    uint8_t pto;
    uint8_t irc;
    uint16_t max_pdu;
    uint8_t num_bis;
    uint16_t handle[0];
} __packed;

#define BT_HCI_EVT_LE_BIG_TERMINATE 0x1c
struct bt_hci_evt_le_big_terminate {
    uint8_t big_handle;
    uint8_t reason;
} __packed;

#define BT_HCI_EVT_LE_BIG_SYNC_ESTABLISHED 0x1d
struct bt_hci_evt_le_big_sync_established {
    uint8_t status;
    uint8_t big_handle;
    uint8_t latency[3];
    uint8_t nse;
    uint8_t bn;
    uint8_t pto;
    uint8_t irc;
    uint16_t max_pdu;
    uint8_t num_bis;
    uint16_t handle[0];
} __packed;

#define BT_HCI_EVT_LE_BIG_SYNC_LOST 0x1e
struct bt_hci_evt_le_big_sync_lost {
    uint8_t big_handle;
    uint8_t reason;
} __packed;

#define BT_HCI_EVT_LE_REQ_PEER_SCA_COMPLETE 0x1f
struct bt_hci_evt_le_req_peer_sca_complete {
    uint8_t status;
    uint16_t handle;
    uint8_t sca;
} __packed;

#define BT_HCI_EVT_LE_BIGINFO_ADV_REPORT 0x22
struct bt_hci_evt_le_biginfo_adv_report {
    uint16_t sync_handle;
    uint8_t num_bis;
    uint8_t nse;
    uint16_t iso_interval;
    uint8_t bn;
    uint8_t pto;
    uint8_t irc;
    uint16_t max_pdu;
    uint8_t sdu_interval[3];
    uint16_t max_sdu;
    uint8_t phy;
    uint8_t framing;
    uint8_t encryption;
} __packed;

/* Event mask bits */

#define BT_EVT_BIT(n) (1ULL << (n))

#define BT_EVT_MASK_INQUIRY_COMPLETE             BT_EVT_BIT(0)
#define BT_EVT_MASK_CONN_COMPLETE                BT_EVT_BIT(2)
#define BT_EVT_MASK_CONN_REQUEST                 BT_EVT_BIT(3)
#define BT_EVT_MASK_DISCONN_COMPLETE             BT_EVT_BIT(4)
#define BT_EVT_MASK_AUTH_COMPLETE                BT_EVT_BIT(5)
#define BT_EVT_MASK_REMOTE_NAME_REQ_COMPLETE     BT_EVT_BIT(6)
#define BT_EVT_MASK_ENCRYPT_CHANGE               BT_EVT_BIT(7)
#define BT_EVT_MASK_REMOTE_FEATURES              BT_EVT_BIT(10)
#define BT_EVT_MASK_REMOTE_VERSION_INFO          BT_EVT_BIT(11)
#define BT_EVT_MASK_HARDWARE_ERROR               BT_EVT_BIT(15)
#define BT_EVT_MASK_ROLE_CHANGE                  BT_EVT_BIT(17)
#define BT_EVT_MASK_PIN_CODE_REQ                 BT_EVT_BIT(21)
#define BT_EVT_MASK_LINK_KEY_REQ                 BT_EVT_BIT(22)
#define BT_EVT_MASK_LINK_KEY_NOTIFY              BT_EVT_BIT(23)
#define BT_EVT_MASK_DATA_BUFFER_OVERFLOW         BT_EVT_BIT(25)
#define BT_EVT_MASK_INQUIRY_RESULT_WITH_RSSI     BT_EVT_BIT(33)
#define BT_EVT_MASK_REMOTE_EXT_FEATURES          BT_EVT_BIT(34)
#define BT_EVT_MASK_SYNC_CONN_COMPLETE           BT_EVT_BIT(43)
#define BT_EVT_MASK_EXTENDED_INQUIRY_RESULT      BT_EVT_BIT(46)
#define BT_EVT_MASK_ENCRYPT_KEY_REFRESH_COMPLETE BT_EVT_BIT(47)
#define BT_EVT_MASK_IO_CAPA_REQ                  BT_EVT_BIT(48)
#define BT_EVT_MASK_IO_CAPA_RESP                 BT_EVT_BIT(49)
#define BT_EVT_MASK_USER_CONFIRM_REQ             BT_EVT_BIT(50)
#define BT_EVT_MASK_USER_PASSKEY_REQ             BT_EVT_BIT(51)
#define BT_EVT_MASK_SSP_COMPLETE                 BT_EVT_BIT(53)
#define BT_EVT_MASK_USER_PASSKEY_NOTIFY          BT_EVT_BIT(58)
#define BT_EVT_MASK_LE_META_EVENT                BT_EVT_BIT(61)

/* Page 2 */
#define BT_EVT_MASK_PHY_LINK_COMPLETE           BT_EVT_BIT(0)
#define BT_EVT_MASK_CH_SELECTED_COMPLETE        BT_EVT_BIT(1)
#define BT_EVT_MASK_DISCONN_PHY_LINK_COMPLETE   BT_EVT_BIT(2)
#define BT_EVT_MASK_PHY_LINK_LOSS_EARLY_WARN    BT_EVT_BIT(3)
#define BT_EVT_MASK_PHY_LINK_RECOVERY           BT_EVT_BIT(4)
#define BT_EVT_MASK_LOG_LINK_COMPLETE           BT_EVT_BIT(5)
#define BT_EVT_MASK_DISCONN_LOG_LINK_COMPLETE   BT_EVT_BIT(6)
#define BT_EVT_MASK_FLOW_SPEC_MODIFY_COMPLETE   BT_EVT_BIT(7)
#define BT_EVT_MASK_NUM_COMPLETE_DATA_BLOCKS    BT_EVT_BIT(8)
#define BT_EVT_MASK_AMP_START_TEST              BT_EVT_BIT(9)
#define BT_EVT_MASK_AMP_TEST_END                BT_EVT_BIT(10)
#define BT_EVT_MASK_AMP_RX_REPORT               BT_EVT_BIT(11)
#define BT_EVT_MASK_AMP_SR_MODE_CHANGE_COMPLETE BT_EVT_BIT(12)
#define BT_EVT_MASK_AMP_STATUS_CHANGE           BT_EVT_BIT(13)
#define BT_EVT_MASK_TRIGG_CLOCK_CAPTURE         BT_EVT_BIT(14)
#define BT_EVT_MASK_SYNCH_TRAIN_COMPLETE        BT_EVT_BIT(15)
#define BT_EVT_MASK_SYNCH_TRAIN_RX              BT_EVT_BIT(16)
#define BT_EVT_MASK_CL_SLAVE_BC_RX              BT_EVT_BIT(17)
#define BT_EVT_MASK_CL_SLAVE_BC_TIMEOUT         BT_EVT_BIT(18)
#define BT_EVT_MASK_TRUNC_PAGE_COMPLETE         BT_EVT_BIT(19)
#define BT_EVT_MASK_SLAVE_PAGE_RSP_TIMEOUT      BT_EVT_BIT(20)
#define BT_EVT_MASK_CL_SLAVE_BC_CH_MAP_CHANGE   BT_EVT_BIT(21)
#define BT_EVT_MASK_INQUIRY_RSP_NOT             BT_EVT_BIT(22)
#define BT_EVT_MASK_AUTH_PAYLOAD_TIMEOUT_EXP    BT_EVT_BIT(23)
#define BT_EVT_MASK_SAM_STATUS_CHANGE           BT_EVT_BIT(24)

#define BT_EVT_MASK_LE_CONN_COMPLETE            BT_EVT_BIT(0)
#define BT_EVT_MASK_LE_ADVERTISING_REPORT       BT_EVT_BIT(1)
#define BT_EVT_MASK_LE_CONN_UPDATE_COMPLETE     BT_EVT_BIT(2)
#define BT_EVT_MASK_LE_REMOTE_FEAT_COMPLETE     BT_EVT_BIT(3)
#define BT_EVT_MASK_LE_LTK_REQUEST              BT_EVT_BIT(4)
#define BT_EVT_MASK_LE_CONN_PARAM_REQ           BT_EVT_BIT(5)
#define BT_EVT_MASK_LE_DATA_LEN_CHANGE          BT_EVT_BIT(6)
#define BT_EVT_MASK_LE_P256_PUBLIC_KEY_COMPLETE BT_EVT_BIT(7)
#define BT_EVT_MASK_LE_GENERATE_DHKEY_COMPLETE  BT_EVT_BIT(8)
#define BT_EVT_MASK_LE_ENH_CONN_COMPLETE        BT_EVT_BIT(9)
#define BT_EVT_MASK_LE_DIRECT_ADV_REPORT        BT_EVT_BIT(10)
#define BT_EVT_MASK_LE_PHY_UPDATE_COMPLETE      BT_EVT_BIT(11)
#define BT_EVT_MASK_LE_EXT_ADVERTISING_REPORT   BT_EVT_BIT(12)
#define BT_EVT_MASK_LE_PER_ADV_SYNC_ESTABLISHED BT_EVT_BIT(13)
#define BT_EVT_MASK_LE_PER_ADVERTISING_REPORT   BT_EVT_BIT(14)
#define BT_EVT_MASK_LE_PER_ADV_SYNC_LOST        BT_EVT_BIT(15)
#define BT_EVT_MASK_LE_SCAN_TIMEOUT             BT_EVT_BIT(16)
#define BT_EVT_MASK_LE_ADV_SET_TERMINATED       BT_EVT_BIT(17)
#define BT_EVT_MASK_LE_SCAN_REQ_RECEIVED        BT_EVT_BIT(18)
#define BT_EVT_MASK_LE_CHAN_SEL_ALGO            BT_EVT_BIT(19)
#define BT_EVT_MASK_LE_PAST_RECEIVED            BT_EVT_BIT(23)
#define BT_EVT_MASK_LE_CIS_ESTABLISHED          BT_EVT_BIT(24)
#define BT_EVT_MASK_LE_CIS_REQ                  BT_EVT_BIT(25)
#define BT_EVT_MASK_LE_BIG_COMPLETE             BT_EVT_BIT(26)
#define BT_EVT_MASK_LE_BIG_TERMINATED           BT_EVT_BIT(27)
#define BT_EVT_MASK_LE_BIG_SYNC_ESTABLISHED     BT_EVT_BIT(28)
#define BT_EVT_MASK_LE_BIG_SYNC_LOST            BT_EVT_BIT(29)
#define BT_EVT_MASK_LE_REQ_PEER_SCA_COMPLETE    BT_EVT_BIT(30)
#define BT_EVT_MASK_LE_PATH_LOSS_THRESHOLD      BT_EVT_BIT(31)
#define BT_EVT_MASK_LE_TRANSMIT_POWER_REPORTING BT_EVT_BIT(32)
#define BT_EVT_MASK_LE_BIGINFO_ADV_REPORT       BT_EVT_BIT(33)

/** Allocate a HCI command buffer.
  *
  * This function allocates a new buffer for a HCI command. It is given
  * the OpCode (encoded e.g. using the BT_OP macro) and the total length
  * of the parameters. Upon successful return the buffer is ready to have
  * the parameters encoded into it.
  *
  * @param opcode     Command OpCode.
  * @param param_len  Length of command parameters.
  *
  * @return Newly allocated buffer.
  */
struct net_buf *bt_hci_cmd_create(u16_t opcode, u8_t param_len);

/** Send a HCI command asynchronously.
  *
  * This function is used for sending a HCI command asynchronously. It can
  * either be called for a buffer created using bt_hci_cmd_create(), or
  * if the command has no parameters a NULL can be passed instead. The
  * sending of the command will happen asynchronously, i.e. upon successful
  * return from this function the caller only knows that it was queued
  * successfully.
  *
  * If synchronous behavior, and retrieval of the Command Complete parameters
  * is desired, the bt_hci_cmd_send_sync() API should be used instead.
  *
  * @param opcode Command OpCode.
  * @param buf    Command buffer or NULL (if no parameters).
  *
  * @return 0 on success or negative error value on failure.
  */
int bt_hci_cmd_send(u16_t opcode, struct net_buf *buf);

/** Send a HCI command synchronously.
  *
  * This function is used for sending a HCI command synchronously. It can
  * either be called for a buffer created using bt_hci_cmd_create(), or
  * if the command has no parameters a NULL can be passed instead.
  *
  * The function will block until a Command Status or a Command Complete
  * event is returned. If either of these have a non-zero status the function
  * will return a negative error code and the response reference will not
  * be set. If the command completed successfully and a non-NULL rsp parameter
  * was given, this parameter will be set to point to a buffer containing
  * the response parameters.
  *
  * @param opcode Command OpCode.
  * @param buf    Command buffer or NULL (if no parameters).
  * @param rsp    Place to store a reference to the command response. May
  *               be NULL if the caller is not interested in the response
  *               parameters. If non-NULL is passed the caller is responsible
  *               for calling net_buf_unref() on the buffer when done parsing
  *               it.
  *
  * @return 0 on success or negative error value on failure.
  */
int bt_hci_cmd_send_sync(u16_t opcode, struct net_buf *buf,
                         struct net_buf **rsp);

//declare bt_hci_get_conn_handle in conn_internal.h to pass compile
#if !defined(BFLB_BLE)
/** @brief Get connection handle for a connection.
 *
 * @param conn Connection object.
 * @param conn_handle Place to store the Connection handle.
 *
 * @return 0 on success or negative error value on failure.
 */
int bt_hci_get_conn_handle(const struct bt_conn *conn, u16_t *conn_handle);
#endif

/** @typedef bt_hci_vnd_evt_cb_t
  * @brief Callback type for vendor handling of HCI Vendor-Specific Events.
  *
  * A function of this type is registered with bt_hci_register_vnd_evt_cb()
  * and will be called for any HCI Vendor-Specific Event.
  *
  * @param buf Buffer containing event parameters.
  *
  * @return true if the function handles the event or false to defer the
  *         handling of this event back to the stack.
  */
typedef bool bt_hci_vnd_evt_cb_t(struct net_buf_simple *buf);

/** Register user callback for HCI Vendor-Specific Events
  *
  * @param cb Callback to be called when the stack receives a
  *           HCI Vendor-Specific Event.
  *
  * @return 0 on success or negative error value on failure.
  */
int bt_hci_register_vnd_evt_cb(bt_hci_vnd_evt_cb_t cb);

#if (BFLB_BT_CO_THREAD)
struct k_thread *bt_get_co_thread(void);
#endif

#ifdef __cplusplus
}
#endif

#endif /* __BT_HCI_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/hci_raw.h
================================================
/** @file
 *  @brief Bluetooth HCI RAW channel handling
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_HCI_RAW_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_HCI_RAW_H_

/**
 * @brief HCI RAW channel
 * @defgroup hci_raw HCI RAW channel
 * @ingroup bluetooth
 * @{
 */

#ifdef __cplusplus
extern "C" {
#endif

/** @brief Send packet to the Bluetooth controller
 *
 * Send packet to the Bluetooth controller. Caller needs to
 * implement netbuf pool.
 *
 * @param buf netbuf packet to be send
 *
 * @return Zero on success or (negative) error code otherwise.
 */
int bt_send(struct net_buf *buf);

/** @brief Enable Bluetooth RAW channel
 *
 *  Enable Bluetooth RAW HCI channel.
 *
 *  @param rx_queue netbuf queue where HCI packets received from the Bluetooth
 *  controller are to be queued. The queue is defined in the caller while
 *  the available buffers pools are handled in the stack.
 *
 *  @return Zero on success or (negative) error code otherwise.
 */
int bt_enable_raw(struct k_fifo *rx_queue);

#ifdef __cplusplus
}
#endif
/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_HCI_RAW_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/hci_vs.h
================================================
/* hci_vs.h - Bluetooth Host Control Interface Vendor Specific definitions */

/*
 * Copyright (c) 2017-2018 Nordic Semiconductor ASA
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_HCI_VS_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_HCI_VS_H_

#include 

#ifdef __cplusplus
extern "C" {
#endif

#define BT_HCI_VS_HW_PLAT_INTEL  0x0001
#define BT_HCI_VS_HW_PLAT_NORDIC 0x0002
#define BT_HCI_VS_HW_PLAT_NXP    0x0003

#define BT_HCI_VS_HW_VAR_NORDIC_NRF51X 0x0001
#define BT_HCI_VS_HW_VAR_NORDIC_NRF52X 0x0002
#define BT_HCI_VS_HW_VAR_NORDIC_NRF53X 0x0003

#define BT_HCI_VS_FW_VAR_STANDARD_CTLR 0x0001
#define BT_HCI_VS_FW_VAR_VS_CTLR       0x0002
#define BT_HCI_VS_FW_VAR_FW_LOADER     0x0003
#define BT_HCI_VS_FW_VAR_RESCUE_IMG    0x0004

#if !defined(BFLB_BLE)
#define BT_HCI_OP_VS_READ_VERSION_INFO BT_OP(BT_OGF_VS, 0x0001)
struct bt_hci_rp_vs_read_version_info {
    u8_t status;
    u16_t hw_platform;
    u16_t hw_variant;
    u8_t fw_variant;
    u8_t fw_version;
    u16_t fw_revision;
    u32_t fw_build;
} __packed;

#define BT_HCI_OP_VS_READ_SUPPORTED_COMMANDS BT_OP(BT_OGF_VS, 0x0002)
struct bt_hci_rp_vs_read_supported_commands {
    u8_t status;
    u8_t commands[64];
} __packed;

#define BT_HCI_OP_VS_READ_SUPPORTED_FEATURES BT_OP(BT_OGF_VS, 0x0003)
struct bt_hci_rp_vs_read_supported_features {
    u8_t status;
    u8_t features[8];
} __packed;

#define BT_HCI_OP_VS_SET_EVENT_MASK BT_OP(BT_OGF_VS, 0x0004)
struct bt_hci_cp_vs_set_event_mask {
    u8_t event_mask[8];
} __packed;

#define BT_HCI_VS_RESET_SOFT 0x00
#define BT_HCI_VS_RESET_HARD 0x01
#define BT_HCI_OP_VS_RESET   BT_OP(BT_OGF_VS, 0x0005)
struct bt_hci_cp_vs_reset {
    u8_t type;
} __packed;

#define BT_HCI_OP_VS_WRITE_BD_ADDR BT_OP(BT_OGF_VS, 0x0006)
struct bt_hci_cp_vs_write_bd_addr {
    bt_addr_t bdaddr;
} __packed;

#define BT_HCI_VS_TRACE_DISABLED 0x00
#define BT_HCI_VS_TRACE_ENABLED  0x01

#define BT_HCI_VS_TRACE_HCI_EVTS      0x00
#define BT_HCI_VS_TRACE_VDC           0x01
#define BT_HCI_OP_VS_SET_TRACE_ENABLE BT_OP(BT_OGF_VS, 0x0007)
struct bt_hci_cp_vs_set_trace_enable {
    u8_t enable;
    u8_t type;
} __packed;

#define BT_HCI_OP_VS_READ_BUILD_INFO BT_OP(BT_OGF_VS, 0x0008)
struct bt_hci_rp_vs_read_build_info {
    u8_t status;
    u8_t info[0];
} __packed;

struct bt_hci_vs_static_addr {
    bt_addr_t bdaddr;
    u8_t ir[16];
} __packed;

#define BT_HCI_OP_VS_READ_STATIC_ADDRS BT_OP(BT_OGF_VS, 0x0009)
struct bt_hci_rp_vs_read_static_addrs {
    u8_t status;
    u8_t num_addrs;
    struct bt_hci_vs_static_addr a[0];
} __packed;

#define BT_HCI_OP_VS_READ_KEY_HIERARCHY_ROOTS BT_OP(BT_OGF_VS, 0x000a)
struct bt_hci_rp_vs_read_key_hierarchy_roots {
    u8_t status;
    u8_t ir[16];
    u8_t er[16];
} __packed;

#define BT_HCI_OP_VS_READ_CHIP_TEMP BT_OP(BT_OGF_VS, 0x000b)
struct bt_hci_rp_vs_read_chip_temp {
    u8_t status;
    s8_t temps;
} __packed;

struct bt_hci_vs_cmd {
    u16_t vendor_id;
    u16_t opcode_base;
} __packed;

#define BT_HCI_VS_VID_ANDROID             0x0001
#define BT_HCI_VS_VID_MICROSOFT           0x0002
#define BT_HCI_OP_VS_READ_HOST_STACK_CMDS BT_OP(BT_OGF_VS, 0x000c)
struct bt_hci_rp_vs_read_host_stack_cmds {
    u8_t status;
    u8_t num_cmds;
    struct bt_hci_vs_cmd c[0];
} __packed;

#define BT_HCI_VS_SCAN_REQ_REPORTS_DISABLED 0x00
#define BT_HCI_VS_SCAN_REQ_REPORTS_ENABLED  0x01
#define BT_HCI_OP_VS_SET_SCAN_REQ_REPORTS   BT_OP(BT_OGF_VS, 0x000d)
struct bt_hci_cp_vs_set_scan_req_reports {
    u8_t enable;
} __packed;
#endif //BFLB_BLE

#if defined(CONFIG_SET_TX_PWR)
#define BT_HCI_OP_VS_SET_TX_PWR BT_OP(BT_OGF_VS, 0x0061)
struct bt_hci_cp_vs_set_tx_pwr {
    int8_t power;
} __packed;
#endif

/* Events */

struct bt_hci_evt_vs {
    u8_t subevent;
} __packed;

#define BT_HCI_EVT_VS_FATAL_ERROR 0x02
struct bt_hci_evt_vs_fatal_error {
    u64_t pc;
    u8_t err_info[0];
} __packed;

#define BT_HCI_VS_TRACE_LMP_TX      0x01
#define BT_HCI_VS_TRACE_LMP_RX      0x02
#define BT_HCI_VS_TRACE_LLCP_TX     0x03
#define BT_HCI_VS_TRACE_LLCP_RX     0x04
#define BT_HCI_VS_TRACE_LE_CONN_IND 0x05
#define BT_HCI_EVT_VS_TRACE_INFO    0x03
struct bt_hci_evt_vs_trace_info {
    u8_t type;
    u8_t data[0];
} __packed;

#define BT_HCI_EVT_VS_SCAN_REQ_RX 0x04
struct bt_hci_evt_vs_scan_req_rx {
    bt_addr_le_t addr;
    s8_t rssi;
} __packed;

/* Event mask bits */

#define BT_EVT_MASK_VS_FATAL_ERROR BT_EVT_BIT(1)
#define BT_EVT_MASK_VS_TRACE_INFO  BT_EVT_BIT(2)
#define BT_EVT_MASK_VS_SCAN_REQ_RX BT_EVT_BIT(3)

/* Mesh HCI commands */
#define BT_HCI_MESH_REVISION 0x01

#define BT_HCI_OP_VS_MESH      BT_OP(BT_OGF_VS, 0x0042)
#define BT_HCI_MESH_EVT_PREFIX 0xF0

struct bt_hci_cp_mesh {
    u8_t opcode;
} __packed;

#define BT_HCI_OC_MESH_GET_OPTS 0x00
struct bt_hci_rp_mesh_get_opts {
    u8_t status;
    u8_t opcode;
    u8_t revision;
    u8_t ch_map;
    s8_t min_tx_power;
    s8_t max_tx_power;
    u8_t max_scan_filter;
    u8_t max_filter_pattern;
    u8_t max_adv_slot;
    u8_t max_tx_window;
    u8_t evt_prefix_len;
    u8_t evt_prefix;
} __packed;

#define BT_HCI_MESH_PATTERN_LEN_MAX 0x0f

#define BT_HCI_OC_MESH_SET_SCAN_FILTER 0x01
struct bt_hci_mesh_pattern {
    u8_t pattern_len;
    u8_t pattern[0];
} __packed;

struct bt_hci_cp_mesh_set_scan_filter {
    u8_t scan_filter;
    u8_t filter_dup;
    u8_t num_patterns;
    struct bt_hci_mesh_pattern patterns[0];
} __packed;
struct bt_hci_rp_mesh_set_scan_filter {
    u8_t status;
    u8_t opcode;
    u8_t scan_filter;
} __packed;

#define BT_HCI_OC_MESH_ADVERTISE 0x02
struct bt_hci_cp_mesh_advertise {
    u8_t adv_slot;
    u8_t own_addr_type;
    bt_addr_t random_addr;
    u8_t ch_map;
    s8_t tx_power;
    u8_t min_tx_delay;
    u8_t max_tx_delay;
    u8_t retx_count;
    u8_t retx_interval;
    u8_t scan_delay;
    u16_t scan_duration;
    u8_t scan_filter;
    u8_t data_len;
    u8_t data[31];
} __packed;
struct bt_hci_rp_mesh_advertise {
    u8_t status;
    u8_t opcode;
    u8_t adv_slot;
} __packed;

#define BT_HCI_OC_MESH_ADVERTISE_TIMED 0x03
struct bt_hci_cp_mesh_advertise_timed {
    u8_t adv_slot;
    u8_t own_addr_type;
    bt_addr_t random_addr;
    u8_t ch_map;
    s8_t tx_power;
    u8_t retx_count;
    u8_t retx_interval;
    u32_t instant;
    u16_t tx_delay;
    u16_t tx_window;
    u8_t data_len;
    u8_t data[31];
} __packed;
struct bt_hci_rp_mesh_advertise_timed {
    u8_t status;
    u8_t opcode;
    u8_t adv_slot;
} __packed;

#define BT_HCI_OC_MESH_ADVERTISE_CANCEL 0x04
struct bt_hci_cp_mesh_advertise_cancel {
    u8_t adv_slot;
} __packed;
struct bt_hci_rp_mesh_advertise_cancel {
    u8_t status;
    u8_t opcode;
    u8_t adv_slot;
} __packed;

#define BT_HCI_OC_MESH_SET_SCANNING 0x05
struct bt_hci_cp_mesh_set_scanning {
    u8_t enable;
    u8_t ch_map;
    u8_t scan_filter;
} __packed;
struct bt_hci_rp_mesh_set_scanning {
    u8_t status;
    u8_t opcode;
} __packed;

/* Events */
struct bt_hci_evt_mesh {
    u8_t prefix;
    u8_t subevent;
} __packed;

#define BT_HCI_EVT_MESH_ADV_COMPLETE 0x00
struct bt_hci_evt_mesh_adv_complete {
    u8_t adv_slot;
} __packed;

#define BT_HCI_EVT_MESH_SCANNING_REPORT 0x01
struct bt_hci_evt_mesh_scan_report {
    bt_addr_le_t addr;
    u8_t chan;
    s8_t rssi;
    u32_t instant;
    u8_t data_len;
    u8_t data[0];
} __packed;
struct bt_hci_evt_mesh_scanning_report {
    u8_t num_reports;
    struct bt_hci_evt_mesh_scan_report reports[0];
} __packed;

#ifdef __cplusplus
}
#endif

#endif /* __BT_HCI_VS_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/hfp_hf.h
================================================
/** @file
 *  @brief Handsfree Profile handling.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_HFP_HF_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_HFP_HF_H_

/**
 * @brief Hands Free Profile (HFP)
 * @defgroup bt_hfp Hands Free Profile (HFP)
 * @ingroup bluetooth
 * @{
 */

#include 

#ifdef __cplusplus
extern "C" {
#endif

/* AT Commands */
enum bt_hfp_hf_at_cmd {
    BT_HFP_HF_ATA,
    BT_HFP_HF_AT_CHUP,
};

/*
 * Command complete types for the application
 */
#define HFP_HF_CMD_OK            0
#define HFP_HF_CMD_ERROR         1
#define HFP_HF_CMD_CME_ERROR     2
#define HFP_HF_CMD_UNKNOWN_ERROR 4

/** @brief HFP HF Command completion field */
struct bt_hfp_hf_cmd_complete {
    /* Command complete status */
    uint8_t type;
    /* CME error number to be added */
    uint8_t cme;
};

/** @brief HFP profile application callback */
struct bt_hfp_hf_cb {
    /** HF connected callback to application
	 *
	 *  If this callback is provided it will be called whenever the
	 *  connection completes.
	 *
	 *  @param conn Connection object.
	 */
    void (*connected)(struct bt_conn *conn);
    /** HF disconnected callback to application
	 *
	 *  If this callback is provided it will be called whenever the
	 *  connection gets disconnected, including when a connection gets
	 *  rejected or cancelled or any error in SLC establisment.
	 *
	 *  @param conn Connection object.
	 */
    void (*disconnected)(struct bt_conn *conn);
    /** HF indicator Callback
	 *
	 *  This callback provides service indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value service indicator value received from the AG.
	 */
    void (*service)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback provides call indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value call indicator value received from the AG.
	 */
    void (*call)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback provides call setup indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value call setup indicator value received from the AG.
	 */
    void (*call_setup)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback provides call held indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value call held indicator value received from the AG.
	 */
    void (*call_held)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback provides signal indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value signal indicator value received from the AG.
	 */
    void (*signal)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback provides roaming indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value roaming indicator value received from the AG.
	 */
    void (*roam)(struct bt_conn *conn, uint32_t value);
    /** HF indicator Callback
	 *
	 *  This callback battery service indicator value to the application
	 *
	 *  @param conn Connection object.
	 *  @param value battery indicator value received from the AG.
	 */
    void (*battery)(struct bt_conn *conn, uint32_t value);
    /** HF incoming call Ring indication callback to application
	 *
	 *  If this callback is provided it will be called whenever there
	 *  is an incoming call.
	 *
	 *  @param conn Connection object.
	 */
    void (*ring_indication)(struct bt_conn *conn);
    /** HF notify command completed callback to application
	 *
	 *  The command sent from the application is notified about its status
	 *
	 *  @param conn Connection object.
	 *  @param cmd structure contains status of the command including cme.
	 */
    void (*cmd_complete_cb)(struct bt_conn *conn,
                            struct bt_hfp_hf_cmd_complete *cmd);
};

/**
* @brief Initialize HFP_HF layer
*/
int bt_hfp_hf_init(void);

/** @brief Handsfree client Send AT
 *
 *  Send specific AT commands to handsfree client profile.
 *
 *  @param conn Connection object.
 *  @param cmd AT command to be sent.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_hfp_hf_send_cmd(struct bt_conn *conn, enum bt_hfp_hf_at_cmd cmd);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_HFP_HF_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/iso.h
================================================
/** @file
 *  @brief Bluetooth ISO handling
 */

/*
 * Copyright (c) 2020 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_ISO_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_ISO_H_

/**
 * @brief ISO
 * @defgroup bt_iso ISO
 * @ingroup bluetooth
 * @{
 */

#ifdef __cplusplus
extern "C" {
#endif

#include 
#include 
#include 
#include 

/** @def BT_ISO_CHAN_SEND_RESERVE
 *  @brief Headroom needed for outgoing buffers
 */
#define BT_ISO_CHAN_SEND_RESERVE (CONFIG_BT_HCI_RESERVE + \
                                  BT_HCI_ISO_HDR_SIZE +   \
                                  BT_HCI_ISO_DATA_HDR_SIZE)

struct bt_iso_chan;

/** @brief Life-span states of ISO channel. Used only by internal APIs
 *  dealing with setting channel to proper state depending on operational
 *  context.
 */
enum {
    /** Channel disconnected */
    BT_ISO_DISCONNECTED,
    /** Channel bound to a connection */
    BT_ISO_BOUND,
    /** Channel in connecting state */
    BT_ISO_CONNECT,
    /** Channel ready for upper layer traffic on it */
    BT_ISO_CONNECTED,
    /** Channel in disconnecting state */
    BT_ISO_DISCONNECT,
};

/** @brief ISO Channel structure. */
struct bt_iso_chan {
    /** Channel connection reference */
    struct bt_conn *conn;
    /** Channel operations reference */
    struct bt_iso_chan_ops *ops;
    /** Channel QoS reference */
    struct bt_iso_chan_qos *qos;
    /** Channel data path reference*/
    struct bt_iso_chan_path *path;
    sys_snode_t node;
    uint8_t state;
    bt_security_t required_sec_level;
};

/** @brief Audio QoS direction */
enum {
    BT_ISO_CHAN_QOS_IN,
    BT_ISO_CHAN_QOS_OUT,
    BT_ISO_CHAN_QOS_INOUT
};

/** @brief ISO Channel QoS structure. */
struct bt_iso_chan_qos {
    /** @brief Channel direction
	 *
	 *  Possible values: BT_ISO_CHAN_QOS_IN, BT_ISO_CHAN_QOS_OUT or
	 *  BT_ISO_CHAN_QOS_INOUT.
	 */
    uint8_t dir;
    /** Channel interval */
    uint32_t interval;
    /** Channel SCA */
    uint8_t sca;
    /** Channel packing mode */
    uint8_t packing;
    /** Channel framing mode */
    uint8_t framing;
    /** Channel Latency */
    uint16_t latency;
    /** Channel SDU */
    uint8_t sdu;
    /** Channel PHY */
    uint8_t phy;
    /** Channel Retransmission Number */
    uint8_t rtn;
};

/** @brief ISO Channel Data Path structure. */
struct bt_iso_chan_path {
    /** Default path ID */
    uint8_t pid;
    /** Coding Format */
    uint8_t format;
    /** Company ID */
    uint16_t cid;
    /** Vendor-defined Codec ID */
    uint16_t vid;
    /** Controller Delay */
    uint32_t delay;
    /** Codec Configuration length*/
    uint8_t cc_len;
    /** Codec Configuration */
    uint8_t cc[0];
};

/** @brief ISO Channel operations structure. */
struct bt_iso_chan_ops {
    /** @brief Channel connected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  connection completes.
	 *
	 *  @param chan The channel that has been connected
	 */
    void (*connected)(struct bt_iso_chan *chan);

    /** @brief Channel disconnected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  channel is disconnected, including when a connection gets
	 *  rejected.
	 *
	 *  @param chan The channel that has been Disconnected
	 */
    void (*disconnected)(struct bt_iso_chan *chan);

    /** @brief Channel alloc_buf callback
	 *
	 *  If this callback is provided the channel will use it to allocate
	 *  buffers to store incoming data.
	 *
	 *  @param chan The channel requesting a buffer.
	 *
	 *  @return Allocated buffer.
	 */
    struct net_buf *(*alloc_buf)(struct bt_iso_chan *chan);

    /** @brief Channel recv callback
	 *
	 *  @param chan The channel receiving data.
	 *  @param buf Buffer containing incoming data.
	 */
    void (*recv)(struct bt_iso_chan *chan, struct net_buf *buf);
};

/** @brief ISO Server structure. */
struct bt_iso_server {
    /** Required minimim security level */
    bt_security_t sec_level;

    /** @brief Server accept callback
	 *
	 *  This callback is called whenever a new incoming connection requires
	 *  authorization.
	 *
	 *  @param conn The connection that is requesting authorization
	 *  @param chan Pointer to receive the allocated channel
	 *
	 *  @return 0 in case of success or negative value in case of error.
	 */
    int (*accept)(struct bt_conn *conn, struct bt_iso_chan **chan);
};

/** @brief Register ISO server.
 *
 *  Register ISO server, each new connection is authorized using the accept()
 *  callback which in case of success shall allocate the channel structure
 *  to be used by the new connection.
 *
 *  @param server Server structure.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_iso_server_register(struct bt_iso_server *server);

/** @brief Bind ISO channels
 *
 *  Bind ISO channels with existing ACL connections, Channel objects passed
 *  (over an address of it) shouldn't be instantiated in application as
 *  standalone.
 *
 *  @param conns Array of ACL connection objects
 *  @param num_conns Number of connection objects
 *  @param chans Array of ISO Channel objects to be created
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_iso_chan_bind(struct bt_conn **conns, uint8_t num_conns,
                     struct bt_iso_chan **chans);

/** @brief Connect ISO channels
 *
 *  Connect ISO channels, once the connection is completed each channel
 *  connected() callback will be called. If the connection is rejected
 *  disconnected() callback is called instead.
 *  Channel object passed (over an address of it) as second parameter shouldn't
 *  be instantiated in application as standalone.
 *
 *  @param chans Array of ISO channel objects
 *  @param num_chans Number of channel objects
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_iso_chan_connect(struct bt_iso_chan **chans, uint8_t num_chans);

/** @brief Disconnect ISO channel
 *
 *  Disconnect ISO channel, if the connection is pending it will be
 *  canceled and as a result the channel disconnected() callback is called.
 *  Regarding to input parameter, to get details see reference description
 *  to bt_iso_chan_connect() API above.
 *
 *  @param chan Channel object.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_iso_chan_disconnect(struct bt_iso_chan *chan);

/** @brief Send data to ISO channel
 *
 *  Send data from buffer to the channel. If credits are not available, buf will
 *  be queued and sent as and when credits are received from peer.
 *  Regarding to first input parameter, to get details see reference description
 *  to bt_iso_chan_connect() API above.
 *
 *  @param chan Channel object.
 *  @param buf Buffer containing data to be sent.
 *
 *  @return Bytes sent in case of success or negative value in case of error.
 */
int bt_iso_chan_send(struct bt_iso_chan *chan, struct net_buf *buf);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_ISO_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/l2cap.h
================================================
/** @file
 *  @brief Bluetooth L2CAP handling
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_L2CAP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_L2CAP_H_

/**
 * @brief L2CAP
 * @defgroup bt_l2cap L2CAP
 * @ingroup bluetooth
 * @{
 */

#include <../bluetooth/buf.h>
#include 
#include 
#ifdef __cplusplus
extern "C" {
#endif

/* L2CAP header size, used for buffer size calculations */
#define BT_L2CAP_HDR_SIZE 4

/** @def BT_L2CAP_BUF_SIZE
 *
 *   Helper to calculate needed outgoing buffer size, useful e.g. for
 *   creating buffer pools.
 *
 *   @param mtu Needed L2CAP MTU.
 *
 *   @return Needed buffer size to match the requested L2CAP MTU.
 */
#define BT_L2CAP_BUF_SIZE(mtu) (BT_BUF_RESERVE +                          \
                                BT_HCI_ACL_HDR_SIZE + BT_L2CAP_HDR_SIZE + \
                                (mtu))

struct bt_l2cap_chan;

/** @typedef bt_l2cap_chan_destroy_t
 *  @brief Channel destroy callback
 *
 *  @param chan Channel object.
 */
typedef void (*bt_l2cap_chan_destroy_t)(struct bt_l2cap_chan *chan);

/** @brief Life-span states of L2CAP CoC channel. Used only by internal APIs
 *  dealing with setting channel to proper state depending on operational
 *  context.
 */
typedef enum bt_l2cap_chan_state {
    /** Channel disconnected */
    BT_L2CAP_DISCONNECTED,
    /** Channel in connecting state */
    BT_L2CAP_CONNECT,
    /** Channel in config state, BR/EDR specific */
    BT_L2CAP_CONFIG,
    /** Channel ready for upper layer traffic on it */
    BT_L2CAP_CONNECTED,
    /** Channel in disconnecting state */
    BT_L2CAP_DISCONNECT,

} __packed bt_l2cap_chan_state_t;

/** @brief Status of L2CAP channel. */
typedef enum bt_l2cap_chan_status {
    /** Channel output status */
    BT_L2CAP_STATUS_OUT,

    /* Total number of status - must be at the end of the enum */
    BT_L2CAP_NUM_STATUS,
} __packed bt_l2cap_chan_status_t;

/** @brief L2CAP Channel structure. */
struct bt_l2cap_chan {
    /** Channel connection reference */
    struct bt_conn *conn;
    /** Channel operations reference */
    struct bt_l2cap_chan_ops *ops;
    sys_snode_t node;
    bt_l2cap_chan_destroy_t destroy;
    /* Response Timeout eXpired (RTX) timer */
    struct k_delayed_work rtx_work;
    ATOMIC_DEFINE(status, BT_L2CAP_NUM_STATUS);

#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
    bt_l2cap_chan_state_t state;
    /** Remote PSM to be connected */
    u16_t psm;
    /** Helps match request context during CoC */
    u8_t ident;
    bt_security_t required_sec_level;
#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */
};

/** @brief LE L2CAP Endpoint structure. */
struct bt_l2cap_le_endpoint {
    /** Endpoint CID */
    u16_t cid;
    /** Endpoint Maximum Transmission Unit */
    u16_t mtu;
    /** Endpoint Maximum PDU payload Size */
    u16_t mps;
    /** Endpoint initial credits */
    u16_t init_credits;
    /** Endpoint credits */
    struct k_sem credits;
};

/** @brief LE L2CAP Channel structure. */
struct bt_l2cap_le_chan {
    /** Common L2CAP channel reference object */
    struct bt_l2cap_chan chan;
    /** Channel Receiving Endpoint */
    struct bt_l2cap_le_endpoint rx;
    /** Channel Transmission Endpoint */
    struct bt_l2cap_le_endpoint tx;
    /** Channel Transmission queue */
    struct k_fifo tx_queue;
    /** Channel Pending Transmission buffer  */
    struct net_buf *tx_buf;
    /** Segment SDU packet from upper layer */
    struct net_buf *_sdu;
    u16_t _sdu_len;

    struct k_work rx_work;
    struct k_fifo rx_queue;
};

/** @def BT_L2CAP_LE_CHAN(_ch)
 *  @brief Helper macro getting container object of type bt_l2cap_le_chan
 *  address having the same container chan member address as object in question.
 *
 *  @param _ch Address of object of bt_l2cap_chan type
 *
 *  @return Address of in memory bt_l2cap_le_chan object type containing
 *  the address of in question object.
 */
#define BT_L2CAP_LE_CHAN(_ch) CONTAINER_OF(_ch, struct bt_l2cap_le_chan, chan)

/** @brief BREDR L2CAP Endpoint structure. */
struct bt_l2cap_br_endpoint {
    /** Endpoint CID */
    u16_t cid;
    /** Endpoint Maximum Transmission Unit */
    u16_t mtu;
};

/** @brief BREDR L2CAP Channel structure. */
struct bt_l2cap_br_chan {
    /** Common L2CAP channel reference object */
    struct bt_l2cap_chan chan;
    /** Channel Receiving Endpoint */
    struct bt_l2cap_br_endpoint rx;
    /** Channel Transmission Endpoint */
    struct bt_l2cap_br_endpoint tx;
    /* For internal use only */
    atomic_t flags[1];
};

/** @brief L2CAP Channel operations structure. */
struct bt_l2cap_chan_ops {
    /** Channel connected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  connection completes.
	 *
	 *  @param chan The channel that has been connected
	 */
    void (*connected)(struct bt_l2cap_chan *chan);

    /** Channel disconnected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  channel is disconnected, including when a connection gets
	 *  rejected.
	 *
	 *  @param chan The channel that has been Disconnected
	 */
    void (*disconnected)(struct bt_l2cap_chan *chan);

    /** Channel encrypt_change callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  security level changed (indirectly link encryption done) or
	 *  authentication procedure fails. In both cases security initiator
	 *  and responder got the final status (HCI status) passed by
	 *  related to encryption and authentication events from local host's
	 *  controller.
	 *
	 *  @param chan The channel which has made encryption status changed.
	 *  @param status HCI status of performed security procedure caused
	 *  by channel security requirements. The value is populated
	 *  by HCI layer and set to 0 when success and to non-zero (reference to
	 *  HCI Error Codes) when security/authentication failed.
	 */
    void (*encrypt_change)(struct bt_l2cap_chan *chan, u8_t hci_status);

    /** Channel alloc_buf callback
	 *
	 *  If this callback is provided the channel will use it to allocate
	 *  buffers to store incoming data.
	 *
	 *  @param chan The channel requesting a buffer.
	 *
	 *  @return Allocated buffer.
	 */
    struct net_buf *(*alloc_buf)(struct bt_l2cap_chan *chan);

    /** Channel recv callback
	 *
	 *  @param chan The channel receiving data.
	 *  @param buf Buffer containing incoming data.
	 *
	 *  @return 0 in case of success or negative value in case of error.
	 *  If -EINPROGRESS is returned user has to confirm once the data has
	 *  been processed by calling bt_l2cap_chan_recv_complete passing back
	 *  the buffer received with its original user_data which contains the
	 *  number of segments/credits used by the packet.
	 */
    int (*recv)(struct bt_l2cap_chan *chan, struct net_buf *buf);

    /*  Channel sent callback
	 *
	 *  If this callback is provided it will be called whenever a SDU has
	 *  been completely sent.
	 *
	 *  @param chan The channel which has sent data.
	 */
    void (*sent)(struct bt_l2cap_chan *chan);

    /*  Channel status callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  channel status changes.
	 *
	 *  @param chan The channel which status changed
	 *  @param status The channel status
	 */
    void (*status)(struct bt_l2cap_chan *chan, atomic_t *status);

#if defined(BFLB_BLE_MTU_CHANGE_CB)
    void (*mtu_changed)(struct bt_l2cap_chan *chan, u16_t mtu);
#endif
};

/** @def BT_L2CAP_CHAN_SEND_RESERVE
 *  @brief Headroom needed for outgoing buffers
 */
#define BT_L2CAP_CHAN_SEND_RESERVE (BT_BUF_RESERVE + 4 + 4)

/** @brief L2CAP Server structure. */
struct bt_l2cap_server {
    /** Server PSM. Possible values:
	 *
	 *  0               A dynamic value will be auto-allocated when
	 *                  bt_l2cap_server_register() is called.
	 *
	 *  0x0001-0x007f   Standard, Bluetooth SIG-assigned fixed values.
	 *
	 *  0x0080-0x00ff   Dynamically allocated. May be pre-set by the
	 *                  application before server registration (not
	 *                  recommended however), or auto-allocated by the
	 *                  stack if the app gave 0 as the value.
	 */
    u16_t psm;

    /** Required minimim security level */
    bt_security_t sec_level;

    /** Server accept callback
	 *
	 *  This callback is called whenever a new incoming connection requires
	 *  authorization.
	 *
	 *  @param conn The connection that is requesting authorization
	 *  @param chan Pointer to received the allocated channel
	 *
	 *  @return 0 in case of success or negative value in case of error.
	 *  Possible return values:
	 *  -ENOMEM if no available space for new channel.
	 *  -EACCES if application did not authorize the connection.
	 *  -EPERM if encryption key size is too short.
	 */
    int (*accept)(struct bt_conn *conn, struct bt_l2cap_chan **chan);

    sys_snode_t node;
};

/** @brief Register L2CAP server.
 *
 *  Register L2CAP server for a PSM, each new connection is authorized using
 *  the accept() callback which in case of success shall allocate the channel
 *  structure to be used by the new connection.
 *
 *  For fixed, SIG-assigned PSMs (in the range 0x0001-0x007f) the PSM should
 *  be assigned to server->psm before calling this API. For dynamic PSMs
 *  (in the range 0x0080-0x00ff) server->psm may be pre-set to a given value
 *  (this is however not recommended) or be left as 0, in which case upon
 *  return a newly allocated value will have been assigned to it. For
 *  dynamically allocated values the expectation is that it's exposed through
 *  a GATT service, and that's how L2CAP clients discover how to connect to
 *  the server.
 *
 *  @param server Server structure.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_l2cap_server_register(struct bt_l2cap_server *server);

/** @brief Register L2CAP server on BR/EDR oriented connection.
 *
 *  Register L2CAP server for a PSM, each new connection is authorized using
 *  the accept() callback which in case of success shall allocate the channel
 *  structure to be used by the new connection.
 *
 *  @param server Server structure.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_l2cap_br_server_register(struct bt_l2cap_server *server);

/** @brief Connect L2CAP channel
 *
 *  Connect L2CAP channel by PSM, once the connection is completed channel
 *  connected() callback will be called. If the connection is rejected
 *  disconnected() callback is called instead.
 *  Channel object passed (over an address of it) as second parameter shouldn't
 *  be instantiated in application as standalone. Instead of, application should
 *  create transport dedicated L2CAP objects, i.e. type of bt_l2cap_le_chan for
 *  LE and/or type of bt_l2cap_br_chan for BR/EDR. Then pass to this API
 *  the location (address) of bt_l2cap_chan type object which is a member
 *  of both transport dedicated objects.
 *
 *  @param conn Connection object.
 *  @param chan Channel object.
 *  @param psm Channel PSM to connect to.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_l2cap_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan,
                          u16_t psm);

/** @brief Disconnect L2CAP channel
 *
 *  Disconnect L2CAP channel, if the connection is pending it will be
 *  canceled and as a result the channel disconnected() callback is called.
 *  Regarding to input parameter, to get details see reference description
 *  to bt_l2cap_chan_connect() API above.
 *
 *  @param chan Channel object.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_l2cap_chan_disconnect(struct bt_l2cap_chan *chan);

/** @brief Send data to L2CAP channel
 *
 *  Send data from buffer to the channel. If credits are not available, buf will
 *  be queued and sent as and when credits are received from peer.
 *  Regarding to first input parameter, to get details see reference description
 *  to bt_l2cap_chan_connect() API above.
 *
 *  @return Bytes sent in case of success or negative value in case of error.
 */
int bt_l2cap_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf);

/** @brief Complete receiving L2CAP channel data
 *
 * Complete the reception of incoming data. This shall only be called if the
 * channel recv callback has returned -EINPROGRESS to process some incoming
 * data. The buffer shall contain the original user_data as that is used for
 * storing the credits/segments used by the packet.
 *
 * @param chan Channel object.
 * @param buf Buffer containing the data.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_l2cap_chan_recv_complete(struct bt_l2cap_chan *chan,
                                struct net_buf *buf);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_L2CAP_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/rfcomm.h
================================================
/** @file
 *  @brief Bluetooth RFCOMM handling
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_RFCOMM_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_RFCOMM_H_

/**
 * @brief RFCOMM
 * @defgroup bt_rfcomm RFCOMM
 * @ingroup bluetooth
 * @{
 */

#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif

/* RFCOMM channels (1-30): pre-allocated for profiles to avoid conflicts */
enum {
    BT_RFCOMM_CHAN_HFP_HF = 1,
    BT_RFCOMM_CHAN_HFP_AG,
    BT_RFCOMM_CHAN_HSP_AG,
    BT_RFCOMM_CHAN_HSP_HS,
    BT_RFCOMM_CHAN_SPP,
};

struct bt_rfcomm_dlc;

/** @brief RFCOMM DLC operations structure. */
struct bt_rfcomm_dlc_ops {
    /** DLC connected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  connection completes.
	 *
	 *  @param dlc The dlc that has been connected
	 */
    void (*connected)(struct bt_rfcomm_dlc *dlc);

    /** DLC disconnected callback
	 *
	 *  If this callback is provided it will be called whenever the
	 *  dlc is disconnected, including when a connection gets
	 *  rejected or cancelled (both incoming and outgoing)
	 *
	 *  @param dlc The dlc that has been Disconnected
	 */
    void (*disconnected)(struct bt_rfcomm_dlc *dlc);

    /** DLC recv callback
	 *
	 *  @param dlc The dlc receiving data.
	 *  @param buf Buffer containing incoming data.
	 */
    void (*recv)(struct bt_rfcomm_dlc *dlc, struct net_buf *buf);
};

/** @brief Role of RFCOMM session and dlc. Used only by internal APIs
 */
typedef enum bt_rfcomm_role {
    BT_RFCOMM_ROLE_ACCEPTOR,
    BT_RFCOMM_ROLE_INITIATOR
} __packed bt_rfcomm_role_t;

/** @brief RFCOMM DLC structure. */
struct bt_rfcomm_dlc {
    /* Response Timeout eXpired (RTX) timer */
    struct k_delayed_work rtx_work;

    /* Queue for outgoing data */
    struct k_fifo tx_queue;

    /* TX credits, Reuse as a binary sem for MSC FC if CFC is not enabled */
    struct k_sem tx_credits;

    struct bt_rfcomm_session *session;
    struct bt_rfcomm_dlc_ops *ops;
    struct bt_rfcomm_dlc *_next;

    bt_security_t required_sec_level;
    bt_rfcomm_role_t role;

    uint16_t mtu;
    uint8_t dlci;
    uint8_t state;
    uint8_t rx_credit;

    /* Stack & kernel data for TX thread */
    struct k_thread tx_thread;
    //K_KERNEL_STACK_MEMBER(stack, 256); //MBHJ
};

struct bt_rfcomm_server {
    /** Server Channel */
    uint8_t channel;

    /** Server accept callback
	 *
	 *  This callback is called whenever a new incoming connection requires
	 *  authorization.
	 *
	 *  @param conn The connection that is requesting authorization
	 *  @param dlc Pointer to received the allocated dlc
	 *
	 *  @return 0 in case of success or negative value in case of error.
	 */
    int (*accept)(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc);

    struct bt_rfcomm_server *_next;
};

/** @brief Register RFCOMM server
 *
 *  Register RFCOMM server for a channel, each new connection is authorized
 *  using the accept() callback which in case of success shall allocate the dlc
 *  structure to be used by the new connection.
 *
 *  @param server Server structure.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_rfcomm_server_register(struct bt_rfcomm_server *server);

/** @brief Connect RFCOMM channel
 *
 *  Connect RFCOMM dlc by channel, once the connection is completed dlc
 *  connected() callback will be called. If the connection is rejected
 *  disconnected() callback is called instead.
 *
 *  @param conn Connection object.
 *  @param dlc Dlc object.
 *  @param channel Server channel to connect to.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_rfcomm_dlc_connect(struct bt_conn *conn, struct bt_rfcomm_dlc *dlc,
                          uint8_t channel);

/** @brief Send data to RFCOMM
 *
 *  Send data from buffer to the dlc. Length should be less than or equal to
 *  mtu.
 *
 *  @param dlc Dlc object.
 *  @param buf Data buffer.
 *
 *  @return Bytes sent in case of success or negative value in case of error.
 */
int bt_rfcomm_dlc_send(struct bt_rfcomm_dlc *dlc, struct net_buf *buf);

/** @brief Disconnect RFCOMM dlc
 *
 *  Disconnect RFCOMM dlc, if the connection is pending it will be
 *  canceled and as a result the dlc disconnected() callback is called.
 *
 *  @param dlc Dlc object.
 *
 *  @return 0 in case of success or negative value in case of error.
 */
int bt_rfcomm_dlc_disconnect(struct bt_rfcomm_dlc *dlc);

/** @brief Allocate the buffer from pool after reserving head room for RFCOMM,
 *  L2CAP and ACL headers.
 *
 *  @param pool Which pool to take the buffer from.
 *
 *  @return New buffer.
 */
struct net_buf *bt_rfcomm_create_pdu(struct net_buf_pool *pool);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_RFCOMM_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/sdp.h
================================================
/** @file
 *  @brief Service Discovery Protocol handling.
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_SDP_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_SDP_H_

/**
 * @brief Service Discovery Protocol (SDP)
 * @defgroup bt_sdp Service Discovery Protocol (SDP)
 * @ingroup bluetooth
 * @{
 */

#include <../bluetooth/uuid.h>
#include <../bluetooth/conn.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * All definitions are based on Bluetooth Assigned Numbers
 * of the Bluetooth Specification
 */

/*
 * Service class identifiers of standard services and service groups
 */
#define BT_SDP_SDP_SERVER_SVCLASS           0x1000
#define BT_SDP_BROWSE_GRP_DESC_SVCLASS      0x1001
#define BT_SDP_PUBLIC_BROWSE_GROUP          0x1002
#define BT_SDP_SERIAL_PORT_SVCLASS          0x1101
#define BT_SDP_LAN_ACCESS_SVCLASS           0x1102
#define BT_SDP_DIALUP_NET_SVCLASS           0x1103
#define BT_SDP_IRMC_SYNC_SVCLASS            0x1104
#define BT_SDP_OBEX_OBJPUSH_SVCLASS         0x1105
#define BT_SDP_OBEX_FILETRANS_SVCLASS       0x1106
#define BT_SDP_IRMC_SYNC_CMD_SVCLASS        0x1107
#define BT_SDP_HEADSET_SVCLASS              0x1108
#define BT_SDP_CORDLESS_TELEPHONY_SVCLASS   0x1109
#define BT_SDP_AUDIO_SOURCE_SVCLASS         0x110a
#define BT_SDP_AUDIO_SINK_SVCLASS           0x110b
#define BT_SDP_AV_REMOTE_TARGET_SVCLASS     0x110c
#define BT_SDP_ADVANCED_AUDIO_SVCLASS       0x110d
#define BT_SDP_AV_REMOTE_SVCLASS            0x110e
#define BT_SDP_AV_REMOTE_CONTROLLER_SVCLASS 0x110f
#define BT_SDP_INTERCOM_SVCLASS             0x1110
#define BT_SDP_FAX_SVCLASS                  0x1111
#define BT_SDP_HEADSET_AGW_SVCLASS          0x1112
#define BT_SDP_WAP_SVCLASS                  0x1113
#define BT_SDP_WAP_CLIENT_SVCLASS           0x1114
#define BT_SDP_PANU_SVCLASS                 0x1115
#define BT_SDP_NAP_SVCLASS                  0x1116
#define BT_SDP_GN_SVCLASS                   0x1117
#define BT_SDP_DIRECT_PRINTING_SVCLASS      0x1118
#define BT_SDP_REFERENCE_PRINTING_SVCLASS   0x1119
#define BT_SDP_IMAGING_SVCLASS              0x111a
#define BT_SDP_IMAGING_RESPONDER_SVCLASS    0x111b
#define BT_SDP_IMAGING_ARCHIVE_SVCLASS      0x111c
#define BT_SDP_IMAGING_REFOBJS_SVCLASS      0x111d
#define BT_SDP_HANDSFREE_SVCLASS            0x111e
#define BT_SDP_HANDSFREE_AGW_SVCLASS        0x111f
#define BT_SDP_DIRECT_PRT_REFOBJS_SVCLASS   0x1120
#define BT_SDP_REFLECTED_UI_SVCLASS         0x1121
#define BT_SDP_BASIC_PRINTING_SVCLASS       0x1122
#define BT_SDP_PRINTING_STATUS_SVCLASS      0x1123
#define BT_SDP_HID_SVCLASS                  0x1124
#define BT_SDP_HCR_SVCLASS                  0x1125
#define BT_SDP_HCR_PRINT_SVCLASS            0x1126
#define BT_SDP_HCR_SCAN_SVCLASS             0x1127
#define BT_SDP_CIP_SVCLASS                  0x1128
#define BT_SDP_VIDEO_CONF_GW_SVCLASS        0x1129
#define BT_SDP_UDI_MT_SVCLASS               0x112a
#define BT_SDP_UDI_TA_SVCLASS               0x112b
#define BT_SDP_AV_SVCLASS                   0x112c
#define BT_SDP_SAP_SVCLASS                  0x112d
#define BT_SDP_PBAP_PCE_SVCLASS             0x112e
#define BT_SDP_PBAP_PSE_SVCLASS             0x112f
#define BT_SDP_PBAP_SVCLASS                 0x1130
#define BT_SDP_MAP_MSE_SVCLASS              0x1132
#define BT_SDP_MAP_MCE_SVCLASS              0x1133
#define BT_SDP_MAP_SVCLASS                  0x1134
#define BT_SDP_GNSS_SVCLASS                 0x1135
#define BT_SDP_GNSS_SERVER_SVCLASS          0x1136
#define BT_SDP_MPS_SC_SVCLASS               0x113a
#define BT_SDP_MPS_SVCLASS                  0x113b
#define BT_SDP_PNP_INFO_SVCLASS             0x1200
#define BT_SDP_GENERIC_NETWORKING_SVCLASS   0x1201
#define BT_SDP_GENERIC_FILETRANS_SVCLASS    0x1202
#define BT_SDP_GENERIC_AUDIO_SVCLASS        0x1203
#define BT_SDP_GENERIC_TELEPHONY_SVCLASS    0x1204
#define BT_SDP_UPNP_SVCLASS                 0x1205
#define BT_SDP_UPNP_IP_SVCLASS              0x1206
#define BT_SDP_UPNP_PAN_SVCLASS             0x1300
#define BT_SDP_UPNP_LAP_SVCLASS             0x1301
#define BT_SDP_UPNP_L2CAP_SVCLASS           0x1302
#define BT_SDP_VIDEO_SOURCE_SVCLASS         0x1303
#define BT_SDP_VIDEO_SINK_SVCLASS           0x1304
#define BT_SDP_VIDEO_DISTRIBUTION_SVCLASS   0x1305
#define BT_SDP_HDP_SVCLASS                  0x1400
#define BT_SDP_HDP_SOURCE_SVCLASS           0x1401
#define BT_SDP_HDP_SINK_SVCLASS             0x1402
#define BT_SDP_GENERIC_ACCESS_SVCLASS       0x1800
#define BT_SDP_GENERIC_ATTRIB_SVCLASS       0x1801
#define BT_SDP_APPLE_AGENT_SVCLASS          0x2112

/*
 * Attribute identifier codes
 */
#define BT_SDP_SERVER_RECORD_HANDLE 0x0000

/*
 * Possible values for attribute-id are listed below.
 * See SDP Spec, section "Service Attribute Definitions" for more details.
 */
#define BT_SDP_ATTR_RECORD_HANDLE          0x0000
#define BT_SDP_ATTR_SVCLASS_ID_LIST        0x0001
#define BT_SDP_ATTR_RECORD_STATE           0x0002
#define BT_SDP_ATTR_SERVICE_ID             0x0003
#define BT_SDP_ATTR_PROTO_DESC_LIST        0x0004
#define BT_SDP_ATTR_BROWSE_GRP_LIST        0x0005
#define BT_SDP_ATTR_LANG_BASE_ATTR_ID_LIST 0x0006
#define BT_SDP_ATTR_SVCINFO_TTL            0x0007
#define BT_SDP_ATTR_SERVICE_AVAILABILITY   0x0008
#define BT_SDP_ATTR_PROFILE_DESC_LIST      0x0009
#define BT_SDP_ATTR_DOC_URL                0x000a
#define BT_SDP_ATTR_CLNT_EXEC_URL          0x000b
#define BT_SDP_ATTR_ICON_URL               0x000c
#define BT_SDP_ATTR_ADD_PROTO_DESC_LIST    0x000d

#define BT_SDP_ATTR_GROUP_ID                0x0200
#define BT_SDP_ATTR_IP_SUBNET               0x0200
#define BT_SDP_ATTR_VERSION_NUM_LIST        0x0200
#define BT_SDP_ATTR_SUPPORTED_FEATURES_LIST 0x0200
#define BT_SDP_ATTR_GOEP_L2CAP_PSM          0x0200
#define BT_SDP_ATTR_SVCDB_STATE             0x0201

#define BT_SDP_ATTR_MPSD_SCENARIOS   0x0200
#define BT_SDP_ATTR_MPMD_SCENARIOS   0x0201
#define BT_SDP_ATTR_MPS_DEPENDENCIES 0x0202

#define BT_SDP_ATTR_SERVICE_VERSION             0x0300
#define BT_SDP_ATTR_EXTERNAL_NETWORK            0x0301
#define BT_SDP_ATTR_SUPPORTED_DATA_STORES_LIST  0x0301
#define BT_SDP_ATTR_DATA_EXCHANGE_SPEC          0x0301
#define BT_SDP_ATTR_NETWORK                     0x0301
#define BT_SDP_ATTR_FAX_CLASS1_SUPPORT          0x0302
#define BT_SDP_ATTR_REMOTE_AUDIO_VOLUME_CONTROL 0x0302
#define BT_SDP_ATTR_MCAP_SUPPORTED_PROCEDURES   0x0302
#define BT_SDP_ATTR_FAX_CLASS20_SUPPORT         0x0303
#define BT_SDP_ATTR_SUPPORTED_FORMATS_LIST      0x0303
#define BT_SDP_ATTR_FAX_CLASS2_SUPPORT          0x0304
#define BT_SDP_ATTR_AUDIO_FEEDBACK_SUPPORT      0x0305
#define BT_SDP_ATTR_NETWORK_ADDRESS             0x0306
#define BT_SDP_ATTR_WAP_GATEWAY                 0x0307
#define BT_SDP_ATTR_HOMEPAGE_URL                0x0308
#define BT_SDP_ATTR_WAP_STACK_TYPE              0x0309
#define BT_SDP_ATTR_SECURITY_DESC               0x030a
#define BT_SDP_ATTR_NET_ACCESS_TYPE             0x030b
#define BT_SDP_ATTR_MAX_NET_ACCESSRATE          0x030c
#define BT_SDP_ATTR_IP4_SUBNET                  0x030d
#define BT_SDP_ATTR_IP6_SUBNET                  0x030e
#define BT_SDP_ATTR_SUPPORTED_CAPABILITIES      0x0310
#define BT_SDP_ATTR_SUPPORTED_FEATURES          0x0311
#define BT_SDP_ATTR_SUPPORTED_FUNCTIONS         0x0312
#define BT_SDP_ATTR_TOTAL_IMAGING_DATA_CAPACITY 0x0313
#define BT_SDP_ATTR_SUPPORTED_REPOSITORIES      0x0314
#define BT_SDP_ATTR_MAS_INSTANCE_ID             0x0315
#define BT_SDP_ATTR_SUPPORTED_MESSAGE_TYPES     0x0316
#define BT_SDP_ATTR_PBAP_SUPPORTED_FEATURES     0x0317
#define BT_SDP_ATTR_MAP_SUPPORTED_FEATURES      0x0317

#define BT_SDP_ATTR_SPECIFICATION_ID 0x0200
#define BT_SDP_ATTR_VENDOR_ID        0x0201
#define BT_SDP_ATTR_PRODUCT_ID       0x0202
#define BT_SDP_ATTR_VERSION          0x0203
#define BT_SDP_ATTR_PRIMARY_RECORD   0x0204
#define BT_SDP_ATTR_VENDOR_ID_SOURCE 0x0205

#define BT_SDP_ATTR_HID_DEVICE_RELEASE_NUMBER 0x0200
#define BT_SDP_ATTR_HID_PARSER_VERSION        0x0201
#define BT_SDP_ATTR_HID_DEVICE_SUBCLASS       0x0202
#define BT_SDP_ATTR_HID_COUNTRY_CODE          0x0203
#define BT_SDP_ATTR_HID_VIRTUAL_CABLE         0x0204
#define BT_SDP_ATTR_HID_RECONNECT_INITIATE    0x0205
#define BT_SDP_ATTR_HID_DESCRIPTOR_LIST       0x0206
#define BT_SDP_ATTR_HID_LANG_ID_BASE_LIST     0x0207
#define BT_SDP_ATTR_HID_SDP_DISABLE           0x0208
#define BT_SDP_ATTR_HID_BATTERY_POWER         0x0209
#define BT_SDP_ATTR_HID_REMOTE_WAKEUP         0x020a
#define BT_SDP_ATTR_HID_PROFILE_VERSION       0x020b
#define BT_SDP_ATTR_HID_SUPERVISION_TIMEOUT   0x020c
#define BT_SDP_ATTR_HID_NORMALLY_CONNECTABLE  0x020d
#define BT_SDP_ATTR_HID_BOOT_DEVICE           0x020e

/*
 * These identifiers are based on the SDP spec stating that
 * "base attribute id of the primary (universal) language must be 0x0100"
 *
 * Other languages should have their own offset; e.g.:
 * #define XXXLangBase yyyy
 * #define AttrServiceName_XXX 0x0000+XXXLangBase
 */
#define BT_SDP_PRIMARY_LANG_BASE 0x0100

#define BT_SDP_ATTR_SVCNAME_PRIMARY  (0x0000 + BT_SDP_PRIMARY_LANG_BASE)
#define BT_SDP_ATTR_SVCDESC_PRIMARY  (0x0001 + BT_SDP_PRIMARY_LANG_BASE)
#define BT_SDP_ATTR_PROVNAME_PRIMARY (0x0002 + BT_SDP_PRIMARY_LANG_BASE)

/*
 * The Data representation in SDP PDUs (pps 339, 340 of BT SDP Spec)
 * These are the exact data type+size descriptor values
 * that go into the PDU buffer.
 *
 * The datatype (leading 5bits) + size descriptor (last 3 bits)
 * is 8 bits. The size descriptor is critical to extract the
 * right number of bytes for the data value from the PDU.
 *
 * For most basic types, the datatype+size descriptor is
 * straightforward. However for constructed types and strings,
 * the size of the data is in the next "n" bytes following the
 * 8 bits (datatype+size) descriptor. Exactly what the "n" is
 * specified in the 3 bits of the data size descriptor.
 *
 * TextString and URLString can be of size 2^{8, 16, 32} bytes
 * DataSequence and DataSequenceAlternates can be of size 2^{8, 16, 32}
 * The size are computed post-facto in the API and are not known apriori
 */
#define BT_SDP_DATA_NIL        0x00
#define BT_SDP_UINT8           0x08
#define BT_SDP_UINT16          0x09
#define BT_SDP_UINT32          0x0a
#define BT_SDP_UINT64          0x0b
#define BT_SDP_UINT128         0x0c
#define BT_SDP_INT8            0x10
#define BT_SDP_INT16           0x11
#define BT_SDP_INT32           0x12
#define BT_SDP_INT64           0x13
#define BT_SDP_INT128          0x14
#define BT_SDP_UUID_UNSPEC     0x18
#define BT_SDP_UUID16          0x19
#define BT_SDP_UUID32          0x1a
#define BT_SDP_UUID128         0x1c
#define BT_SDP_TEXT_STR_UNSPEC 0x20
#define BT_SDP_TEXT_STR8       0x25
#define BT_SDP_TEXT_STR16      0x26
#define BT_SDP_TEXT_STR32      0x27
#define BT_SDP_BOOL            0x28
#define BT_SDP_SEQ_UNSPEC      0x30
#define BT_SDP_SEQ8            0x35
#define BT_SDP_SEQ16           0x36
#define BT_SDP_SEQ32           0x37
#define BT_SDP_ALT_UNSPEC      0x38
#define BT_SDP_ALT8            0x3d
#define BT_SDP_ALT16           0x3e
#define BT_SDP_ALT32           0x3f
#define BT_SDP_URL_STR_UNSPEC  0x40
#define BT_SDP_URL_STR8        0x45
#define BT_SDP_URL_STR16       0x46
#define BT_SDP_URL_STR32       0x47

#define BT_SDP_TYPE_DESC_MASK    0xf8
#define BT_SDP_SIZE_DESC_MASK    0x07
#define BT_SDP_SIZE_INDEX_OFFSET 5

/** @brief SDP Generic Data Element Value. */
struct bt_sdp_data_elem {
    uint8_t type;
    uint32_t data_size;
    uint32_t total_size;
    const void *data;
};

/** @brief SDP Attribute Value. */
struct bt_sdp_attribute {
    uint16_t id;                 /* Attribute ID */
    struct bt_sdp_data_elem val; /* Attribute data */
};

/** @brief SDP Service Record Value. */
struct bt_sdp_record {
    uint32_t handle;                /* Redundant, for quick ref */
    struct bt_sdp_attribute *attrs; /* Base addr of attr array */
    size_t attr_count;              /* Number of attributes */
    uint8_t index;                  /* Index of the record in LL */
    struct bt_sdp_record *next;
};

/*
 * ---------------------------------------------------    ------------------
 * | Service Hdl | Attr list ptr | Attr count | Next | -> | Service Hdl | ...
 * ---------------------------------------------------    ------------------
 */

/** @def BT_SDP_ARRAY_8
 *  @brief Declare an array of 8-bit elements in an attribute.
 */
#define BT_SDP_ARRAY_8(...) ((uint8_t[]){ __VA_ARGS__ })

/** @def BT_SDP_ARRAY_16
 *  @brief Declare an array of 16-bit elements in an attribute.
 */
#define BT_SDP_ARRAY_16(...) ((uint16_t[]){ __VA_ARGS__ })

/** @def BT_SDP_ARRAY_32
 *  @brief Declare an array of 32-bit elements in an attribute.
 */
#define BT_SDP_ARRAY_32(...) ((uint32_t[]){ __VA_ARGS__ })

/** @def BT_SDP_TYPE_SIZE
 *  @brief Declare a fixed-size data element header.
 *
 *  @param _type Data element header containing type and size descriptors.
 */
#define BT_SDP_TYPE_SIZE(_type) .type = _type,                                   \
                                .data_size = BIT(_type & BT_SDP_SIZE_DESC_MASK), \
                                .total_size = BIT(_type & BT_SDP_SIZE_DESC_MASK) + 1

/** @def BT_SDP_TYPE_SIZE_VAR
 *  @brief Declare a variable-size data element header.
 *
 *  @param _type Data element header containing type and size descriptors.
 *  @param _size The actual size of the data.
 */
#define BT_SDP_TYPE_SIZE_VAR(_type, _size) .type = _type, .data_size = _size, .total_size = BIT((_type & BT_SDP_SIZE_DESC_MASK) - BT_SDP_SIZE_INDEX_OFFSET) + _size + 1

/** @def BT_SDP_DATA_ELEM_LIST
 *  @brief Declare a list of data elements.
 */
#define BT_SDP_DATA_ELEM_LIST(...) ((struct bt_sdp_data_elem[]){ __VA_ARGS__ })

/** @def BT_SDP_NEW_SERVICE
 *  @brief SDP New Service Record Declaration Macro.
 *
 *  Helper macro to declare a new service record.
 *  Default attributes: Record Handle, Record State,
 *  Language Base, Root Browse Group
 *
 */
#define BT_SDP_NEW_SERVICE                                                       \
    {                                                                            \
        BT_SDP_ATTR_RECORD_HANDLE,                                               \
        { BT_SDP_TYPE_SIZE(BT_SDP_UINT32), BT_SDP_ARRAY_32(0) }                  \
    },                                                                           \
        { BT_SDP_ATTR_RECORD_STATE,                                              \
          { BT_SDP_TYPE_SIZE(BT_SDP_UINT32), BT_SDP_ARRAY_32(0) } },             \
        { BT_SDP_ATTR_LANG_BASE_ATTR_ID_LIST,                                    \
          {                                                                      \
              BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 9),                              \
              BT_SDP_DATA_ELEM_LIST(                                             \
                  { BT_SDP_TYPE_SIZE(BT_SDP_UINT16), BT_SDP_ARRAY_8('n', 'e') }, \
                  { BT_SDP_TYPE_SIZE(BT_SDP_UINT16), BT_SDP_ARRAY_16(106) },     \
                  { BT_SDP_TYPE_SIZE(BT_SDP_UINT16),                             \
                    BT_SDP_ARRAY_16(BT_SDP_PRIMARY_LANG_BASE) }),                \
          } },                                                                   \
    {                                                                            \
        BT_SDP_ATTR_BROWSE_GRP_LIST,                                             \
        {                                                                        \
            BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),                                \
                BT_SDP_DATA_ELEM_LIST(                                           \
                    { BT_SDP_TYPE_SIZE(BT_SDP_UUID16),                           \
                      BT_SDP_ARRAY_16(BT_SDP_PUBLIC_BROWSE_GROUP) }, ),          \
        }                                                                        \
    }

/** @def BT_SDP_LIST
 *  @brief Generic SDP List Attribute Declaration Macro.
 *
 *  Helper macro to declare a list attribute.
 *
 *  @param _att_id List Attribute ID.
 *  @param _data_elem_seq Data element sequence for the list.
 *  @param _type_size SDP type and size descriptor.
 */
#define BT_SDP_LIST(_att_id, _type_size, _data_elem_seq) \
    {                                                    \
        _att_id,                                         \
        {                                                \
            _type_size, _data_elem_seq                   \
        }                                                \
    }

/** @def BT_SDP_SERVICE_ID
 *  @brief SDP Service ID Attribute Declaration Macro.
 *
 *  Helper macro to declare a service ID attribute.
 *
 *  @param _uuid Service ID 16bit UUID.
 */
#define BT_SDP_SERVICE_ID(_uuid)                                         \
    {                                                                    \
        BT_SDP_ATTR_SERVICE_ID,                                          \
        {                                                                \
            BT_SDP_TYPE_SIZE(BT_SDP_UUID16), &((struct bt_uuid_16)_uuid) \
        }                                                                \
    }

/** @def BT_SDP_SERVICE_NAME
 *  @brief SDP Name Attribute Declaration Macro.
 *
 *  Helper macro to declare a service name attribute.
 *
 *  @param _name Service name as a string (up to 256 chars).
 */
#define BT_SDP_SERVICE_NAME(_name)                                             \
    {                                                                          \
        BT_SDP_ATTR_SVCNAME_PRIMARY,                                           \
        {                                                                      \
            BT_SDP_TYPE_SIZE_VAR(BT_SDP_TEXT_STR8, (sizeof(_name) - 1)), _name \
        }                                                                      \
    }

/** @def BT_SDP_SUPPORTED_FEATURES
 *  @brief SDP Supported Features Attribute Declaration Macro.
 *
 *  Helper macro to declare supported features of a profile/protocol.
 *
 *  @param _features Feature mask as 16bit unsigned integer.
 */
#define BT_SDP_SUPPORTED_FEATURES(_features)                            \
    {                                                                   \
        BT_SDP_ATTR_SUPPORTED_FEATURES,                                 \
        {                                                               \
            BT_SDP_TYPE_SIZE(BT_SDP_UINT16), BT_SDP_ARRAY_16(_features) \
        }                                                               \
    }

/** @def BT_SDP_RECORD
 *  @brief SDP Service Declaration Macro.
 *
 *  Helper macro to declare a service.
 *
 *  @param _attrs List of attributes for the service record.
 */
#define BT_SDP_RECORD(_attrs)               \
    {                                       \
        .attrs = _attrs,                    \
        .attr_count = ARRAY_SIZE((_attrs)), \
    }

/* Server API */

/** @brief Register a Service Record.
 *
 *  Register a Service Record. Applications can make use of
 *  macros such as BT_SDP_DECLARE_SERVICE, BT_SDP_LIST,
 *  BT_SDP_SERVICE_ID, BT_SDP_SERVICE_NAME, etc.
 *  A service declaration must start with BT_SDP_NEW_SERVICE.
 *
 *  @param service Service record declared using BT_SDP_DECLARE_SERVICE.
 *
 * @return 0 in case of success or negative value in case of error.
 */
int bt_sdp_register_service(struct bt_sdp_record *service);

/* Client API */

/** @brief Generic SDP Client Query Result data holder */
struct bt_sdp_client_result {
    /* buffer containing unparsed SDP record result for given UUID */
    struct net_buf *resp_buf;
    /* flag pointing that there are more result chunks for given UUID */
    bool next_record_hint;
    /* Reference to UUID object on behalf one discovery was started */
    const struct bt_uuid *uuid;
};

/** @brief Helper enum to be used as return value of bt_sdp_discover_func_t.
 *  The value informs the caller to perform further pending actions or stop them.
 */
enum {
    BT_SDP_DISCOVER_UUID_STOP = 0,
    BT_SDP_DISCOVER_UUID_CONTINUE,
};

/** @typedef bt_sdp_discover_func_t
 *
 *  @brief Callback type reporting to user that there is a resolved result
 *  on remote for given UUID and the result record buffer can be used by user
 *  for further inspection.
 *
 *  A function of this type is given by the user to the bt_sdp_discover_params
 *  object. It'll be called on each valid record discovery completion for given
 *  UUID. When UUID resolution gives back no records then NULL is passed
 *  to the user. Otherwise user can get valid record(s) and then the internal
 *  hint 'next record' is set to false saying the UUID resolution is complete or
 *  the hint can be set by caller to true meaning that next record is available
 *  for given UUID.
 *  The returned function value allows the user to control retrieving follow-up
 *  resolved records if any. If the user doesn't want to read more resolved
 *  records for given UUID since current record data fulfills its requirements
 *  then should return BT_SDP_DISCOVER_UUID_STOP. Otherwise returned value means
 *  more subcall iterations are allowable.
 *
 *  @param conn Connection object identifying connection to queried remote.
 *  @param result Object pointing to logical unparsed SDP record collected on
 *  base of response driven by given UUID.
 *
 *  @return BT_SDP_DISCOVER_UUID_STOP in case of no more need to read next
 *  record data and continue discovery for given UUID. By returning
 *  BT_SDP_DISCOVER_UUID_CONTINUE user allows this discovery continuation.
 */
typedef uint8_t (*bt_sdp_discover_func_t)(struct bt_conn *conn, struct bt_sdp_client_result *result);

/** @brief Main user structure used in SDP discovery of remote. */
struct bt_sdp_discover_params {
    sys_snode_t _node;
    /** UUID (service) to be discovered on remote SDP entity */
    const struct bt_uuid *uuid;
    /** Discover callback to be called on resolved SDP record */
    bt_sdp_discover_func_t func;
    /** Memory buffer enabled by user for SDP query results  */
    struct net_buf_pool *pool;
};

/** @brief Allows user to start SDP discovery session.
 *
 *  The function performs SDP service discovery on remote server driven by user
 *  delivered discovery parameters. Discovery session is made as soon as
 *  no SDP transaction is ongoing between peers and if any then this one
 *  is queued to be processed at discovery completion of previous one.
 *  On the service discovery completion the callback function will be
 *  called to get feedback to user about findings.
 *
 * @param conn Object identifying connection to remote.
 * @param params SDP discovery parameters.
 *
 * @return 0 in case of success or negative value in case of error.
 */

int bt_sdp_discover(struct bt_conn *conn,
                    const struct bt_sdp_discover_params *params);

/** @brief Release waiting SDP discovery request.
 *
 *  It can cancel valid waiting SDP client request identified by SDP discovery
 *  parameters object.
 *
 * @param conn Object identifying connection to remote.
 * @param params SDP discovery parameters.
 *
 * @return 0 in case of success or negative value in case of error.
 */
int bt_sdp_discover_cancel(struct bt_conn *conn,
                           const struct bt_sdp_discover_params *params);

/* Helper types & functions for SDP client to get essential data from server */

/** @brief Protocols to be asked about specific parameters */
enum bt_sdp_proto {
    BT_SDP_PROTO_RFCOMM = 0x0003,
    BT_SDP_PROTO_L2CAP = 0x0100,
};

/** @brief Give to user parameter value related to given stacked protocol UUID.
 *
 *  API extracts specific parameter associated with given protocol UUID
 *  available in Protocol Descriptor List attribute.
 *
 *  @param buf Original buffered raw record data.
 *  @param proto Known protocol to be checked like RFCOMM or L2CAP.
 *  @param param On success populated by found parameter value.
 *
 *  @return 0 on success when specific parameter associated with given protocol
 *  value is found, or negative if error occurred during processing.
 */
int bt_sdp_get_proto_param(const struct net_buf *buf, enum bt_sdp_proto proto,
                           uint16_t *param);

/** @brief Get profile version.
 *
 *  Helper API extracting remote profile version number. To get it proper
 *  generic profile parameter needs to be selected usually listed in SDP
 *  Interoperability Requirements section for given profile specification.
 *
 *  @param buf Original buffered raw record data.
 *  @param profile Profile family identifier the profile belongs.
 *  @param version On success populated by found version number.
 *
 *  @return 0 on success, negative value if error occurred during processing.
 */
int bt_sdp_get_profile_version(const struct net_buf *buf, uint16_t profile,
                               uint16_t *version);

/** @brief Get SupportedFeatures attribute value
 *
 *  Allows if exposed by remote retrieve SupportedFeature attribute.
 *
 *  @param buf Buffer holding original raw record data from remote.
 *  @param features On success object to be populated with SupportedFeature
 *  mask.
 *
 *  @return 0 on success if feature found and valid, negative in case any error
 */
int bt_sdp_get_features(const struct net_buf *buf, uint16_t *features);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_SDP_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/bluetooth/uuid.h
================================================
/** @file
 *  @brief Bluetooth UUID handling
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_BLUETOOTH_UUID_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_UUID_H_

/**
 * @brief UUIDs
 * @defgroup bt_uuid UUIDs
 * @ingroup bluetooth
 * @{
 */

#include 

#ifdef __cplusplus
extern "C" {
#endif

/** @brief Bluetooth UUID types */
enum {
    BT_UUID_TYPE_16,
    BT_UUID_TYPE_32,
    BT_UUID_TYPE_128,
};

/** @brief This is a 'tentative' type and should be used as a pointer only */
struct bt_uuid {
    u8_t type;
};

struct bt_uuid_16 {
    struct bt_uuid uuid;
    u16_t val;
};

struct bt_uuid_32 {
    struct bt_uuid uuid;
    u32_t val;
};

struct bt_uuid_128 {
    struct bt_uuid uuid;
    u8_t val[16];
};

#define BT_UUID_INIT_16(value)       \
    {                                \
        .uuid = { BT_UUID_TYPE_16 }, \
        .val = (value),              \
    }

#define BT_UUID_INIT_32(value)       \
    {                                \
        .uuid = { BT_UUID_TYPE_32 }, \
        .val = (value),              \
    }

#define BT_UUID_INIT_128(value...)    \
    {                                 \
        .uuid = { BT_UUID_TYPE_128 }, \
        .val = { value },             \
    }

#define BT_UUID_DECLARE_16(value) \
    ((struct bt_uuid *)((struct bt_uuid_16[]){ BT_UUID_INIT_16(value) }))
#define BT_UUID_DECLARE_32(value) \
    ((struct bt_uuid *)((struct bt_uuid_32[]){ BT_UUID_INIT_32(value) }))
#define BT_UUID_DECLARE_128(value...) \
    ((struct bt_uuid *)((struct bt_uuid_128[]){ BT_UUID_INIT_128(value) }))

#define BT_UUID_16(__u)  CONTAINER_OF(__u, struct bt_uuid_16, uuid)
#define BT_UUID_32(__u)  CONTAINER_OF(__u, struct bt_uuid_32, uuid)
#define BT_UUID_128(__u) CONTAINER_OF(__u, struct bt_uuid_128, uuid)

/**
 * @brief Encode 128 bit UUID into an array values
 *
 * Helper macro to initialize a 128-bit UUID value from the UUID format.
 * Can be combined with BT_UUID_DECLARE_128 to declare a 128-bit UUID from
 * the readable form of UUIDs.
 *
 * Example for how to declare the UUID `6E400001-B5A3-F393-E0A9-E50E24DCCA9E`
 *
 * @code
 * BT_UUID_DECLARE_128(
 *       BT_UUID_128_ENCODE(0x6E400001, 0xB5A3, 0xF393, 0xE0A9, 0xE50E24DCCA9E))
 * @endcode
 *
 * Just replace the hyphen by the comma and add `0x` prefixes.
 *
 * @param w32 First part of the UUID (32 bits)
 * @param w1  Second part of the UUID (16 bits)
 * @param w2  Third part of the UUID (16 bits)
 * @param w3  Fourth part of the UUID (16 bits)
 * @param w48 Fifth part of the UUID (48 bits)
 *
 * @return The comma separated values for UUID 128 initializer that
 *         may be used directly as an argument for
 *         @ref BT_UUID_INIT_128 or @ref BT_UUID_DECLARE_128
 */
#define BT_UUID_128_ENCODE(w32, w1, w2, w3, w48) \
    (((w48) >> 0) & 0xFF),                       \
        (((w48) >> 8) & 0xFF),                   \
        (((w48) >> 16) & 0xFF),                  \
        (((w48) >> 24) & 0xFF),                  \
        (((w48) >> 32) & 0xFF),                  \
        (((w48) >> 40) & 0xFF),                  \
        (((w3) >> 0) & 0xFF),                    \
        (((w3) >> 8) & 0xFF),                    \
        (((w2) >> 0) & 0xFF),                    \
        (((w2) >> 8) & 0xFF),                    \
        (((w1) >> 0) & 0xFF),                    \
        (((w1) >> 8) & 0xFF),                    \
        (((w32) >> 0) & 0xFF),                   \
        (((w32) >> 8) & 0xFF),                   \
        (((w32) >> 16) & 0xFF),                  \
        (((w32) >> 24) & 0xFF)

#define BT_UUID_SCPS BT_UUID_DECLARE_16(0x1813)

/** @def BT_UUID_GAP
 *  @brief Generic Access
 */
#define BT_UUID_GAP BT_UUID_DECLARE_16(0x1800)
/** @def BT_UUID_GATT
 *  @brief Generic Attribute
 */
#define BT_UUID_GATT BT_UUID_DECLARE_16(0x1801)
/** @def BT_UUID_CTS
 *  @brief Current Time Service
 */
#define BT_UUID_CTS BT_UUID_DECLARE_16(0x1805)
/** @def BT_UUID_HTS
 *  @brief Health Thermometer Service
 */
#define BT_UUID_HTS BT_UUID_DECLARE_16(0x1809)
/** @def BT_UUID_DIS
 *  @brief Device Information Service
 */
#define BT_UUID_DIS BT_UUID_DECLARE_16(0x180a)
/** @def BT_UUID_HRS
 *  @brief Heart Rate Service
 */
#define BT_UUID_HRS BT_UUID_DECLARE_16(0x180d)
/** @def BT_UUID_BAS
 *  @brief Battery Service
 */
#define BT_UUID_BAS BT_UUID_DECLARE_16(0x180f)
/** @def BT_UUID_HIDS
 *  @brief HID Service
 */
#define BT_UUID_HIDS BT_UUID_DECLARE_16(0x1812)
/** @def BT_UUID_CSC
 *  @brief Cycling Speed and Cadence Service
 */
#define BT_UUID_CSC BT_UUID_DECLARE_16(0x1816)
/** @def BT_UUID_ESS
 *  @brief Environmental Sensing Service
 */
#define BT_UUID_ESS BT_UUID_DECLARE_16(0x181a)
/** @def BT_UUID_IPSS
 *  @brief IP Support Service
 */
#define BT_UUID_IPSS BT_UUID_DECLARE_16(0x1820)
/** @def BT_UUID_MESH_PROV
 *  @brief Mesh Provisioning Service
 */
#define BT_UUID_MESH_PROV BT_UUID_DECLARE_16(0x1827)
/** @def BT_UUID_MESH_PROXY
 *  @brief Mesh Proxy Service
 */
#define BT_UUID_MESH_PROXY BT_UUID_DECLARE_16(0x1828)
/** @def BT_UUID_GATT_PRIMARY
 *  @brief GATT Primary Service
 */
#define BT_UUID_GATT_PRIMARY BT_UUID_DECLARE_16(0x2800)
/** @def BT_UUID_GATT_SECONDARY
 *  @brief GATT Secondary Service
 */
#define BT_UUID_GATT_SECONDARY BT_UUID_DECLARE_16(0x2801)
/** @def BT_UUID_GATT_INCLUDE
 *  @brief GATT Include Service
 */
#define BT_UUID_GATT_INCLUDE BT_UUID_DECLARE_16(0x2802)
/** @def BT_UUID_GATT_CHRC
 *  @brief GATT Characteristic
 */
#define BT_UUID_GATT_CHRC BT_UUID_DECLARE_16(0x2803)
/** @def BT_UUID_GATT_CEP
 *  @brief GATT Characteristic Extended Properties
 */
#define BT_UUID_GATT_CEP BT_UUID_DECLARE_16(0x2900)
/** @def BT_UUID_GATT_CUD
 *  @brief GATT Characteristic User Description
 */
#define BT_UUID_GATT_CUD BT_UUID_DECLARE_16(0x2901)
/** @def BT_UUID_GATT_CCC
 *  @brief GATT Client Characteristic Configuration
 */
#define BT_UUID_GATT_CCC BT_UUID_DECLARE_16(0x2902)
/** @def BT_UUID_GATT_SCC
 *  @brief GATT Server Characteristic Configuration
 */
#define BT_UUID_GATT_SCC BT_UUID_DECLARE_16(0x2903)
/** @def BT_UUID_GATT_CPF
 *  @brief GATT Characteristic Presentation Format
 */
#define BT_UUID_GATT_CPF BT_UUID_DECLARE_16(0x2904)
/** @def BT_UUID_VALID_RANGE
 *  @brief Valid Range Descriptor
 */
#define BT_UUID_VALID_RANGE BT_UUID_DECLARE_16(0x2906)
/** @def BT_UUID_HIDS_EXT_REPORT
 *  @brief HID External Report Descriptor
 */
#define BT_UUID_HIDS_EXT_REPORT BT_UUID_DECLARE_16(0x2907)
/** @def BT_UUID_HIDS_REPORT_REF
 *  @brief HID Report Reference Descriptor
 */
#define BT_UUID_HIDS_REPORT_REF BT_UUID_DECLARE_16(0x2908)
/** @def BT_UUID_ES_CONFIGURATION
 *  @brief Environmental Sensing Configuration Descriptor
 */
#define BT_UUID_ES_CONFIGURATION BT_UUID_DECLARE_16(0x290b)
/** @def BT_UUID_ES_MEASUREMENT
 *  @brief Environmental Sensing Measurement Descriptor
 */
#define BT_UUID_ES_MEASUREMENT BT_UUID_DECLARE_16(0x290c)
/** @def BT_UUID_ES_TRIGGER_SETTING
 *  @brief Environmental Sensing Trigger Setting Descriptor
 */
#define BT_UUID_ES_TRIGGER_SETTING BT_UUID_DECLARE_16(0x290d)
/** @def BT_UUID_GAP_DEVICE_NAME
 *  @brief GAP Characteristic Device Name
 */
#define BT_UUID_GAP_DEVICE_NAME BT_UUID_DECLARE_16(0x2a00)
/** @def BT_UUID_GAP_APPEARANCE
 *  @brief GAP Characteristic Appearance
 */
#define BT_UUID_GAP_APPEARANCE BT_UUID_DECLARE_16(0x2a01)
/** @def BT_UUID_GAP_PPCP
 *  @brief GAP Characteristic Peripheral Preferred Connection Parameters
 */
#define BT_UUID_GAP_PPCP BT_UUID_DECLARE_16(0x2a04)
/** @def BT_UUID_GATT_SC
 *  @brief GATT Characteristic Service Changed
 */
#define BT_UUID_GATT_SC BT_UUID_DECLARE_16(0x2a05)
/** @def BT_UUID_BAS_BATTERY_LEVEL
 *  @brief BAS Characteristic Battery Level
 */
#define BT_UUID_BAS_BATTERY_LEVEL BT_UUID_DECLARE_16(0x2a19)
/** @def BT_UUID_HTS_MEASUREMENT
 *  @brief HTS Characteristic Measurement Value
 */
#define BT_UUID_HTS_MEASUREMENT BT_UUID_DECLARE_16(0x2a1c)
/** @def BT_UUID_HIDS_BOOT_KB_IN_REPORT
 *  @brief HID Characteristic Boot Keyboard Input Report
 */
#define BT_UUID_HIDS_BOOT_KB_IN_REPORT BT_UUID_DECLARE_16(0x2a22)
/** @def BT_UUID_DIS_SYSTEM_ID
 *  @brief DIS Characteristic System ID
 */
#define BT_UUID_DIS_SYSTEM_ID BT_UUID_DECLARE_16(0x2a23)
/** @def BT_UUID_DIS_MODEL_NUMBER
 *  @brief DIS Characteristic Model Number String
 */
#define BT_UUID_DIS_MODEL_NUMBER BT_UUID_DECLARE_16(0x2a24)
/** @def BT_UUID_DIS_SERIAL_NUMBER
 *  @brief DIS Characteristic Serial Number String
 */
#define BT_UUID_DIS_SERIAL_NUMBER BT_UUID_DECLARE_16(0x2a25)
/** @def BT_UUID_DIS_FIRMWARE_REVISION
 *  @brief DIS Characteristic Firmware Revision String
 */
#define BT_UUID_DIS_FIRMWARE_REVISION BT_UUID_DECLARE_16(0x2a26)
/** @def BT_UUID_DIS_HARDWARE_REVISION
 *  @brief DIS Characteristic Hardware Revision String
 */
#define BT_UUID_DIS_HARDWARE_REVISION BT_UUID_DECLARE_16(0x2a27)
/** @def BT_UUID_DIS_SOFTWARE_REVISION
 *  @brief DIS Characteristic Software Revision String
 */
#define BT_UUID_DIS_SOFTWARE_REVISION BT_UUID_DECLARE_16(0x2a28)
/** @def BT_UUID_DIS_MANUFACTURER_NAME
 *  @brief DIS Characteristic Manufacturer Name String
 */
#define BT_UUID_DIS_MANUFACTURER_NAME BT_UUID_DECLARE_16(0x2a29)
/** @def BT_UUID_DIS_PNP_ID
 *  @brief DIS Characteristic PnP ID
 */

#define BT_UUID_SCPS_SCAN_INTVL_WIN BT_UUID_DECLARE_16(0x2a4f)

#define BT_UUID_DIS_PNP_ID BT_UUID_DECLARE_16(0x2a50)
/** @def BT_UUID_CTS_CURRENT_TIME
 *  @brief CTS Characteristic Current Time
 */
#define BT_UUID_CTS_CURRENT_TIME BT_UUID_DECLARE_16(0x2a2b)
/** @def BT_UUID_MAGN_DECLINATION
 *  @brief Magnetic Declination Characteristic
 */
#define BT_UUID_MAGN_DECLINATION BT_UUID_DECLARE_16(0x2a2c)
/** @def BT_UUID_HIDS_BOOT_KB_OUT_REPORT
 *  @brief HID Boot Keyboard Output Report Characteristic
 */
#define BT_UUID_HIDS_BOOT_KB_OUT_REPORT BT_UUID_DECLARE_16(0x2a32)
/** @def BT_UUID_HIDS_BOOT_MOUSE_IN_REPORT
 *  @brief HID Boot Mouse Input Report Characteristic
 */
#define BT_UUID_HIDS_BOOT_MOUSE_IN_REPORT BT_UUID_DECLARE_16(0x2a33)
/** @def BT_UUID_HRS_MEASUREMENT
 *  @brief HRS Characteristic Measurement Interval
 */
#define BT_UUID_HRS_MEASUREMENT BT_UUID_DECLARE_16(0x2a37)
/** @def BT_UUID_HRS_BODY_SENSOR
 *  @brief HRS Characteristic Body Sensor Location
 */
#define BT_UUID_HRS_BODY_SENSOR BT_UUID_DECLARE_16(0x2a38)
/** @def BT_UUID_HRS_CONTROL_POINT
 *  @brief HRS Characteristic Control Point
 */
#define BT_UUID_HRS_CONTROL_POINT BT_UUID_DECLARE_16(0x2a39)
/** @def BT_UUID_HIDS_INFO
 *  @brief HID Information Characteristic
 */
#define BT_UUID_HIDS_INFO BT_UUID_DECLARE_16(0x2a4a)
/** @def BT_UUID_HIDS_REPORT_MAP
 *  @brief HID Report Map Characteristic
 */
#define BT_UUID_HIDS_REPORT_MAP BT_UUID_DECLARE_16(0x2a4b)
/** @def BT_UUID_HIDS_CTRL_POINT
 *  @brief HID Control Point Characteristic
 */
#define BT_UUID_HIDS_CTRL_POINT BT_UUID_DECLARE_16(0x2a4c)
/** @def BT_UUID_HIDS_REPORT
 *  @brief HID Report Characteristic
 */
#define BT_UUID_HIDS_REPORT BT_UUID_DECLARE_16(0x2a4d)
/** @def BT_UUID_HIDS_PROTOCOL_MODE
 *  @brief HID Protocol Mode Characteristic
 */
#define BT_UUID_HIDS_PROTOCOL_MODE BT_UUID_DECLARE_16(0x2a4e)
/** @def BT_UUID_CSC_MEASUREMENT
 *  @brief CSC Measurement Characteristic
 */
#define BT_UUID_CSC_MEASUREMENT BT_UUID_DECLARE_16(0x2a5b)
/** @def BT_UUID_CSC_FEATURE
 *  @brief CSC Feature Characteristic
 */
#define BT_UUID_CSC_FEATURE BT_UUID_DECLARE_16(0x2a5c)
/** @def BT_UUID_SENSOR_LOCATION
 *  @brief Sensor Location Characteristic
 */
#define BT_UUID_SENSOR_LOCATION BT_UUID_DECLARE_16(0x2a5d)
/** @def BT_UUID_SC_CONTROL_POINT
 *  @brief SC Control Point Characteristic
 */
#define BT_UUID_SC_CONTROL_POINT BT_UUID_DECLARE_16(0x2a55)
/** @def BT_UUID_ELEVATION
 *  @brief Elevation Characteristic
 */
#define BT_UUID_ELEVATION BT_UUID_DECLARE_16(0x2a6c)
/** @def BT_UUID_PRESSURE
 *  @brief Pressure Characteristic
 */
#define BT_UUID_PRESSURE BT_UUID_DECLARE_16(0x2a6d)
/** @def BT_UUID_TEMPERATURE
 *  @brief Temperature Characteristic
 */
#define BT_UUID_TEMPERATURE BT_UUID_DECLARE_16(0x2a6e)
/** @def BT_UUID_HUMIDITY
 *  @brief Humidity Characteristic
 */
#define BT_UUID_HUMIDITY BT_UUID_DECLARE_16(0x2a6f)
/** @def BT_UUID_TRUE_WIND_SPEED
 *  @brief True Wind Speed Characteristic
 */
#define BT_UUID_TRUE_WIND_SPEED BT_UUID_DECLARE_16(0x2a70)
/** @def BT_UUID_TRUE_WIND_DIR
 *  @brief True Wind Direction Characteristic
 */
#define BT_UUID_TRUE_WIND_DIR BT_UUID_DECLARE_16(0x2a71)
/** @def BT_UUID_APPARENT_WIND_SPEED
 *  @brief Apparent Wind Speed Characteristic
 */
#define BT_UUID_APPARENT_WIND_SPEED BT_UUID_DECLARE_16(0x2a72)
/** @def BT_UUID_APPARENT_WIND_DIR
 *  @brief Apparent Wind Direction Characteristic
 */
#define BT_UUID_APPARENT_WIND_DIR BT_UUID_DECLARE_16(0x2a73)
/** @def BT_UUID_GUST_FACTOR
 *  @brief Gust Factor Characteristic
 */
#define BT_UUID_GUST_FACTOR BT_UUID_DECLARE_16(0x2a74)
/** @def BT_UUID_POLLEN_CONCENTRATION
 *  @brief Pollen Concentration Characteristic
 */
#define BT_UUID_POLLEN_CONCENTRATION BT_UUID_DECLARE_16(0x2a75)
/** @def BT_UUID_UV_INDEX
 *  @brief UV Index Characteristic
 */
#define BT_UUID_UV_INDEX BT_UUID_DECLARE_16(0x2a76)
/** @def BT_UUID_IRRADIANCE
 *  @brief Irradiance Characteristic
 */
#define BT_UUID_IRRADIANCE BT_UUID_DECLARE_16(0x2a77)
/** @def BT_UUID_RAINFALL
 *  @brief Rainfall Characteristic
 */
#define BT_UUID_RAINFALL BT_UUID_DECLARE_16(0x2a78)
/** @def BT_UUID_WIND_CHILL
 *  @brief Wind Chill Characteristic
 */
#define BT_UUID_WIND_CHILL BT_UUID_DECLARE_16(0x2a79)
/** @def BT_UUID_HEAT_INDEX
 *  @brief Heat Index Characteristic
 */
#define BT_UUID_HEAT_INDEX BT_UUID_DECLARE_16(0x2a7a)
/** @def BT_UUID_DEW_POINT
 *  @brief Dew Point Characteristic
 */
#define BT_UUID_DEW_POINT BT_UUID_DECLARE_16(0x2a7b)
/** @def BT_UUID_DESC_VALUE_CHANGED
 *  @brief Descriptor Value Changed Characteristic
 */
#define BT_UUID_DESC_VALUE_CHANGED BT_UUID_DECLARE_16(0x2a7d)
/** @def BT_UUID_MAGN_FLUX_DENSITY_2D
 *  @brief Magnetic Flux Density - 2D Characteristic
 */
#define BT_UUID_MAGN_FLUX_DENSITY_2D BT_UUID_DECLARE_16(0x2aa0)
/** @def BT_UUID_MAGN_FLUX_DENSITY_3D
 *  @brief Magnetic Flux Density - 3D Characteristic
 */
#define BT_UUID_MAGN_FLUX_DENSITY_3D BT_UUID_DECLARE_16(0x2aa1)
/** @def BT_UUID_BAR_PRESSURE_TREND
 *  @brief Barometric Pressure Trend Characteristic
 */
#define BT_UUID_BAR_PRESSURE_TREND BT_UUID_DECLARE_16(0x2aa3)
/** @def BT_UUID_CENTRAL_ADDR_RES
 *  @brief Central Address Resolution Characteristic
 */
#define BT_UUID_CENTRAL_ADDR_RES BT_UUID_DECLARE_16(0x2aa6)
/** @def BT_UUID_MESH_PROV_DATA_IN
 *  @brief Mesh Provisioning Data In
 */
#define BT_UUID_MESH_PROV_DATA_IN BT_UUID_DECLARE_16(0x2adb)
/** @def BT_UUID_MESH_PROV_DATA_OUT
 *  @brief Mesh Provisioning Data Out
 */
#define BT_UUID_MESH_PROV_DATA_OUT BT_UUID_DECLARE_16(0x2adc)
/** @def BT_UUID_MESH_PROXY_DATA_IN
 *  @brief Mesh Proxy Data In
 */
#define BT_UUID_MESH_PROXY_DATA_IN BT_UUID_DECLARE_16(0x2add)
/** @def BT_UUID_MESH_PROXY_DATA_OUT
 *  @brief Mesh Proxy Data Out
 */
#define BT_UUID_MESH_PROXY_DATA_OUT BT_UUID_DECLARE_16(0x2ade)
/** @def BT_UUID_GATT_CLIENT_FEATURES
 *  @brief Client Supported Features
 */
#define BT_UUID_GATT_CLIENT_FEATURES BT_UUID_DECLARE_16(0x2b29)
/** @def BT_UUID_GATT_DB_HASH
 *  @brief Database Hash
 */
#define BT_UUID_GATT_DB_HASH BT_UUID_DECLARE_16(0x2b2a)

#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_GAP_SLAVER_CONFIG_READ_CHARC)
#define BT_UUID_PTS                    BT_UUID_DECLARE_16(0x2b2b)
#define BT_UUID_PTS_CHAR_READ_AUTHEN   BT_UUID_DECLARE_16(0x2b2c)
#define BT_UUID_PTS_CHAR_READ_NOPERM   BT_UUID_DECLARE_16(0x2b2d)
#define BT_UUID_PTS_CHAR_READ_LONGVAL  BT_UUID_DECLARE_16(0x2b2e)
#define BT_UUID_PTS_CHAR_READ_L_NOPERM BT_UUID_DECLARE_16(0x2b2f)
#define BT_UUID_PTS_CHAR_READ_LVAL_REF BT_UUID_DECLARE_16(0x2b30)
#endif

#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_GAP_SLAVER_CONFIG_WRITE_CHARC)
#define BT_UUID_PTS_CHAR_WRITE_VALUE    BT_UUID_DECLARE_16(0x2b31)
#define BT_UUID_PTS_CHAR_WRITE_AUTHEN   BT_UUID_DECLARE_16(0x2b32)
#define BT_UUID_PTS_CHAR_WRITE_LONGVAL  BT_UUID_DECLARE_16(0x2b33)
#define BT_UUID_PTS_CHAR_WRITE_NORSP    BT_UUID_DECLARE_16(0x2b34)
#define BT_UUID_PTS_CHAR_WRITE_2LONGVAL BT_UUID_DECLARE_16(0x2b35)
#define BT_UUID_PTS_CHAR_WRITE_L_DES    BT_UUID_DECLARE_16(0x2b36)
#endif

#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_GAP_SLAVER_CONFIG_NOTIFY_CHARC)
#define BT_UUID_PTS_CHAR_NOTIFY_CHAR BT_UUID_DECLARE_16(0x2b37)
#endif

#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_GAP_SLAVER_CONFIG_INDICATE_CHARC)
#define BT_UUID_PTS_CHAR_INDICATE_CHAR BT_UUID_DECLARE_16(0x2b38)
#endif

#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_TEST_CASE_INSUFFICIENT_KEY)
#define BT_UUID_PTS_ENC_KEY BT_UUID_DECLARE_16(0x2b3a)
#endif
#if defined(CONFIG_BT_STACK_PTS) && defined(PTS_CHARC_LEN_EQUAL_MTU_SIZE)
#define BT_UUID_PTS_READ_MTU_SIZE_CHAR BT_UUID_DECLARE_16(0x2b3b)
#endif

#if defined(CONFIG_BT_STACK_PTS)
#define BT_UUID_PTS_AUTH_CHAR BT_UUID_DECLARE_16(0x2b39)
#endif

/*
 * Protocol UUIDs
 */
#define BT_UUID_SDP       BT_UUID_DECLARE_16(0x0001)
#define BT_UUID_UDP       BT_UUID_DECLARE_16(0x0002)
#define BT_UUID_RFCOMM    BT_UUID_DECLARE_16(0x0003)
#define BT_UUID_TCP       BT_UUID_DECLARE_16(0x0004)
#define BT_UUID_TCS_BIN   BT_UUID_DECLARE_16(0x0005)
#define BT_UUID_TCS_AT    BT_UUID_DECLARE_16(0x0006)
#define BT_UUID_ATT       BT_UUID_DECLARE_16(0x0007)
#define BT_UUID_OBEX      BT_UUID_DECLARE_16(0x0008)
#define BT_UUID_IP        BT_UUID_DECLARE_16(0x0009)
#define BT_UUID_FTP       BT_UUID_DECLARE_16(0x000a)
#define BT_UUID_HTTP      BT_UUID_DECLARE_16(0x000c)
#define BT_UUID_BNEP      BT_UUID_DECLARE_16(0x000f)
#define BT_UUID_UPNP      BT_UUID_DECLARE_16(0x0010)
#define BT_UUID_HIDP      BT_UUID_DECLARE_16(0x0011)
#define BT_UUID_HCRP_CTRL BT_UUID_DECLARE_16(0x0012)
#define BT_UUID_HCRP_DATA BT_UUID_DECLARE_16(0x0014)
#define BT_UUID_HCRP_NOTE BT_UUID_DECLARE_16(0x0016)
#define BT_UUID_AVCTP     BT_UUID_DECLARE_16(0x0017)
#define BT_UUID_AVDTP     BT_UUID_DECLARE_16(0x0019)
#define BT_UUID_CMTP      BT_UUID_DECLARE_16(0x001b)
#define BT_UUID_UDI       BT_UUID_DECLARE_16(0x001d)
#define BT_UUID_MCAP_CTRL BT_UUID_DECLARE_16(0x001e)
#define BT_UUID_MCAP_DATA BT_UUID_DECLARE_16(0x001f)
#define BT_UUID_L2CAP     BT_UUID_DECLARE_16(0x0100)

/** @brief Compare Bluetooth UUIDs.
 *
 *  Compares 2 Bluetooth UUIDs, if the types are different both UUIDs are
 *  first converted to 128 bits format before comparing.
 *
 *  @param u1 First Bluetooth UUID to compare
 *  @param u2 Second Bluetooth UUID to compare
 *
 *  @return negative value if @a u1 < @a u2, 0 if @a u1 == @a u2, else positive
 */
int bt_uuid_cmp(const struct bt_uuid *u1, const struct bt_uuid *u2);

/** @brief Create a bt_uuid from a little-endian data buffer.
 *
 *  Create a bt_uuid from a little-endian data buffer. The data_len parameter
 *  is used to determine whether the UUID is in 16, 32 or 128 bit format
 *  (length 2, 4 or 16). Note: 32 bit format is not allowed over the air.
 *
 *  @param uuid Pointer to the bt_uuid variable
 *  @param data pointer to UUID stored in little-endian data buffer
 *  @param data_len length of the UUID in the data buffer
 *
 *  @return true if the data was valid and the UUID was successfully created.
 */
bool bt_uuid_create(struct bt_uuid *uuid, const u8_t *data, u8_t data_len);

#if defined(CONFIG_BT_DEBUG)
/** @brief Convert Bluetooth UUID to string.
 *
 *  Converts Bluetooth UUID to string. UUID has to be in 16 bits or 128 bits
 *  format.
 *
 *  @param uuid Bluetooth UUID
 *  @param str pointer where to put converted string
 *  @param len length of str
 *
 *  @return N/A
 */
void bt_uuid_to_str(const struct bt_uuid *uuid, char *str, size_t len);

const char *bt_uuid_str_real(const struct bt_uuid *uuid);

/** @def bt_uuid_str
 *  @brief Convert Bluetooth UUID to string in place.
 *
 *  Converts Bluetooth UUID to string in place. UUID has to be in 16 bits or
 *  128 bits format.
 *
 *  @param uuid Bluetooth UUID
 *
 *  @return String representation of the UUID given
 */
#define bt_uuid_str(_uuid) log_strdup(bt_uuid_str_real(_uuid))
#else
static inline void bt_uuid_to_str(const struct bt_uuid *uuid, char *str,
                                  size_t len)
{
    if (len > 0) {
        str[0] = '\0';
    }
}

static inline const char *bt_uuid_str(const struct bt_uuid *uuid)
{
    return "";
}
#endif /* CONFIG_BT_DEBUG */

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_UUID_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/include/drivers/bluetooth/hci_driver.h
================================================
/** @file
 *  @brief Bluetooth HCI driver API.
 */

/*
 * Copyright (c) 2015-2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DRIVERS_BLUETOOTH_HCI_DRIVER_H_
#define ZEPHYR_INCLUDE_DRIVERS_BLUETOOTH_HCI_DRIVER_H_

/**
 * @brief HCI drivers
 * @defgroup bt_hci_driver HCI drivers
 * @ingroup bluetooth
 * @{
 */

#include 
#include 
#include <../../bluetooth/buf.h>

#ifdef __cplusplus
extern "C" {
#endif

enum {
    /* The host should never send HCI_Reset */
    BT_QUIRK_NO_RESET = BIT(0),
};

/**
 * @brief Check if an HCI event is high priority or not.
 *
 * Helper for the HCI driver to know which events are ok to be passed
 * through the RX thread and which must be given to bt_recv_prio() from
 * another context (e.g. ISR). If this function returns true it's safe
 * to pass the event through the RX thread, however if it returns false
 * then this risks a deadlock.
 *
 * @param evt HCI event code.
 *
 * @return true if the event can be processed in the RX thread, false
 *         if it cannot.
 */
static inline bool bt_hci_evt_is_prio(u8_t evt)
{
    switch (evt) {
        case BT_HCI_EVT_CMD_COMPLETE:
        case BT_HCI_EVT_CMD_STATUS:
            /* fallthrough */
#if defined(CONFIG_BT_CONN)
        case BT_HCI_EVT_NUM_COMPLETED_PACKETS:
        case BT_HCI_EVT_DATA_BUF_OVERFLOW:
#endif
            return true;
        default:
            return false;
    }
}

/**
 * @brief Receive data from the controller/HCI driver.
 *
 * This is the main function through which the HCI driver provides the
 * host with data from the controller. The buffer needs to have its type
 * set with the help of bt_buf_set_type() before calling this API. This API
 * should not be used for so-called high priority HCI events, which should
 * instead be delivered to the host stack through bt_recv_prio().
 *
 * @param buf Network buffer containing data from the controller.
 *
 * @return 0 on success or negative error number on failure.
 */
int bt_recv(struct net_buf *buf);

/**
 * @brief Receive high priority data from the controller/HCI driver.
 *
 * This is the same as bt_recv(), except that it should be used for
 * so-called high priority HCI events. There's a separate
 * bt_hci_evt_is_prio() helper that can be used to identify which events
 * are high priority.
 *
 * As with bt_recv(), the buffer needs to have its type set with the help of
 * bt_buf_set_type() before calling this API. The only exception is so called
 * high priority HCI events which should be delivered to the host stack through
 * bt_recv_prio() instead.
 *
 * @param buf Network buffer containing data from the controller.
 *
 * @return 0 on success or negative error number on failure.
 */
int bt_recv_prio(struct net_buf *buf);

/** Possible values for the 'bus' member of the bt_hci_driver struct */
enum bt_hci_driver_bus {
    BT_HCI_DRIVER_BUS_VIRTUAL = 0,
    BT_HCI_DRIVER_BUS_USB = 1,
    BT_HCI_DRIVER_BUS_PCCARD = 2,
    BT_HCI_DRIVER_BUS_UART = 3,
    BT_HCI_DRIVER_BUS_RS232 = 4,
    BT_HCI_DRIVER_BUS_PCI = 5,
    BT_HCI_DRIVER_BUS_SDIO = 6,
    BT_HCI_DRIVER_BUS_SPI = 7,
    BT_HCI_DRIVER_BUS_I2C = 8,
    BT_HCI_DRIVER_BUS_IPM = 9,
};

/**
 * @brief Abstraction which represents the HCI transport to the controller.
 *
 * This struct is used to represent the HCI transport to the Bluetooth
 * controller.
 */
struct bt_hci_driver {
    /** Name of the driver */
    const char *name;

    /** Bus of the transport (BT_HCI_DRIVER_BUS_*) */
    enum bt_hci_driver_bus bus;

    /** Specific controller quirks. These are set by the HCI driver
	 *  and acted upon by the host. They can either be statically
	 *  set at buildtime, or set at runtime before the HCI driver's
	 *  open() callback returns.
	 */
    u32_t quirks;

    /**
	 * @brief Open the HCI transport.
	 *
	 * Opens the HCI transport for operation. This function must not
	 * return until the transport is ready for operation, meaning it
	 * is safe to start calling the send() handler.
	 *
	 * If the driver uses its own RX thread, i.e.
	 * CONFIG_BT_RECV_IS_RX_THREAD is set, then this
	 * function is expected to start that thread.
	 *
	 * @return 0 on success or negative error number on failure.
	 */
    int (*open)(void);

    /**
	 * @brief Send HCI buffer to controller.
	 *
	 * Send an HCI command or ACL data to the controller. The exact
	 * type of the data can be checked with the help of bt_buf_get_type().
	 *
	 * @note This function must only be called from a cooperative thread.
	 *
	 * @param buf Buffer containing data to be sent to the controller.
	 *
	 * @return 0 on success or negative error number on failure.
	 */
    int (*send)(struct net_buf *buf);
};

/**
 * @brief Register a new HCI driver to the Bluetooth stack.
 *
 * This needs to be called before any application code runs. The bt_enable()
 * API will fail if there is no driver registered.
 *
 * @param drv A bt_hci_driver struct representing the driver.
 *
 * @return 0 on success or negative error number on failure.
 */
int bt_hci_driver_register(const struct bt_hci_driver *drv);

#if !defined(BFLB_BLE) /*Don't use*/
/**
 * @brief Setup the HCI transport, which usually means to reset the
 * Bluetooth IC.
 *
 * @note A weak version of this function is included in the H4 driver, so
 *       defining it is optional per board.
 *
 * @param dev The device structure for the bus connecting to the IC
 *
 * @return 0 on success, negative error value on failure
 */
int bt_hci_transport_setup(struct device *dev);
#endif

#if defined(BFLB_BLE)
/**
 * @brief enqueue buffer to hci received queue.
 * @param buf Buffer containing data received from firmware.
 */
void hci_driver_enque_recvq(struct net_buf *buf);

int hci_driver_init(void);

#endif //#if (BFLB_BLE)

#ifdef __cplusplus
}
#endif

#endif /* __BT_HCI_DRIVER_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/port/bl_port.c
================================================
#include 
#include 
#include 

#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BLUETOOTH_DEBUG_CORE)

#include "atomic.h"
#include 
#include 
#include 
#include 

#include "errno.h"
#include 
#include 
#include 
#include 
#include 

#if defined(BL_MCU_SDK)
#define TRNG_LOOP_COUNTER (17)
extern BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len);
extern BL_Err_Type Sec_Eng_Trng_Enable(void);
int                bl_rand();
#else
extern int bl_rand();
#endif

int ble_rand() {
#if defined(CONFIG_HW_SEC_ENG_DISABLE)
  return random();
#else
  return bl_rand();
#endif
}

#if defined(BL_MCU_SDK)
int bl_rand() {
  unsigned int val;
  int          counter = 0;
  int32_t      ret     = 0;
  do {
    ret = Sec_Eng_Trng_Get_Random((uint8_t *)&val, 4);
    if (ret < -1) {
      return -1;
    }
    if ((counter++) > TRNG_LOOP_COUNTER) {
      break;
    }
  } while (0 == val);
  val >>= 1; // leave signe bit alone
  return val;
}
#endif

void k_queue_init(struct k_queue *queue, int size) {
  // int size = 20;
  uint8_t blk_size = sizeof(void *);

  queue->hdl = xQueueCreate(size, blk_size);
  BT_ASSERT(queue->hdl != NULL);

  sys_dlist_init(&queue->poll_events);
}

void k_queue_insert(struct k_queue *queue, void *prev, void *data) {
  BaseType_t ret;
  (void)ret;

  ret = xQueueSend(queue->hdl, &data, portMAX_DELAY);
  BT_ASSERT(ret == pdPASS);
}

void k_queue_append(struct k_queue *queue, void *data) { k_queue_insert(queue, NULL, data); }

void k_queue_insert_from_isr(struct k_queue *queue, void *prev, void *data) {
  BaseType_t xHigherPriorityTaskWoken;

  xQueueSendFromISR(queue->hdl, &data, &xHigherPriorityTaskWoken);
  if (xHigherPriorityTaskWoken == pdTRUE) {
    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
  }
}

void k_queue_append_from_isr(struct k_queue *queue, void *data) { k_queue_insert_from_isr(queue, NULL, data); }

void k_queue_free(struct k_queue *queue) {
  if (NULL == queue || NULL == queue->hdl) {
    BT_ERR("Queue is NULL\n");
    return;
  }

  vQueueDelete(queue->hdl);
  queue->hdl = NULL;
  return;
}

void k_queue_prepend(struct k_queue *queue, void *data) { k_queue_insert(queue, NULL, data); }

void k_queue_append_list(struct k_queue *queue, void *head, void *tail) {
  struct net_buf *buf_tail = (struct net_buf *)head;

  for (buf_tail = (struct net_buf *)head; buf_tail; buf_tail = buf_tail->frags) {
    k_queue_append(queue, buf_tail);
  }
}

void *k_queue_get(struct k_queue *queue, s32_t timeout) {
  void        *msg = NULL;
  unsigned int t   = timeout;
  BaseType_t   ret;

  (void)ret;

  if (timeout == K_FOREVER) {
    t = BL_WAIT_FOREVER;
  } else if (timeout == K_NO_WAIT) {
    t = BL_NO_WAIT;
  }

  ret = xQueueReceive(queue->hdl, &msg, t == BL_WAIT_FOREVER ? portMAX_DELAY : ms2tick(t));
  if (ret == pdPASS) {
    return msg;
  } else {
    return NULL;
  }
}

int k_queue_is_empty(struct k_queue *queue) { return uxQueueMessagesWaiting(queue->hdl) ? 0 : 1; }

int k_queue_get_cnt(struct k_queue *queue) { return uxQueueMessagesWaiting(queue->hdl); }

int k_sem_init(struct k_sem *sem, unsigned int initial_count, unsigned int limit) {
  if (NULL == sem) {
    BT_ERR("sem is NULL\n");
    return -EINVAL;
  }

  sem->sem.hdl = xSemaphoreCreateCounting(limit, initial_count);
  sys_dlist_init(&sem->poll_events);
  return 0;
}

int k_sem_take(struct k_sem *sem, uint32_t timeout) {
  BaseType_t   ret;
  unsigned int t = timeout;

  (void)ret;
  if (timeout == K_FOREVER) {
    t = BL_WAIT_FOREVER;
  } else if (timeout == K_NO_WAIT) {
    t = BL_NO_WAIT;
  }

  if (NULL == sem) {
    return -1;
  }

  ret = xSemaphoreTake(sem->sem.hdl, t == BL_WAIT_FOREVER ? portMAX_DELAY : ms2tick(t));
  return ret == pdPASS ? 0 : -1;
}

int k_sem_give(struct k_sem *sem) {
  BaseType_t ret;
  (void)ret;

  if (NULL == sem) {
    BT_ERR("sem is NULL\n");
    return -EINVAL;
  }

  ret = xSemaphoreGive(sem->sem.hdl);
  return ret == pdPASS ? 0 : -1;
}

int k_sem_delete(struct k_sem *sem) {
  if (NULL == sem || NULL == sem->sem.hdl) {
    BT_ERR("sem is NULL\n");
    return -EINVAL;
  }

  vSemaphoreDelete(sem->sem.hdl);
  sem->sem.hdl = NULL;
  return 0;
}

unsigned int k_sem_count_get(struct k_sem *sem) { return uxQueueMessagesWaiting(sem->sem.hdl); }

void k_mutex_init(struct k_mutex *mutex) {
  if (NULL == mutex) {
    BT_ERR("mutex is NULL\n");
    return;
  }

  mutex->mutex.hdl = xSemaphoreCreateMutex();
  BT_ASSERT(mutex->mutex.hdl != NULL);
  sys_dlist_init(&mutex->poll_events);
}

int64_t k_uptime_get() { return k_now_ms(); }

u32_t k_uptime_get_32(void) { return (u32_t)k_now_ms(); }

int k_thread_create(struct k_thread *new_thread, const char *name, size_t stack_size, k_thread_entry_t entry, int prio) {
  stack_size /= sizeof(StackType_t);
  xTaskCreate(entry, name, stack_size, NULL, prio, (void *)(&new_thread->task));

  return new_thread->task ? 0 : -1;
}

void k_thread_delete(struct k_thread *thread) {
  if (NULL == thread || 0 == thread->task) {
    BT_ERR("task is NULL\n");
    return;
  }

  vTaskDelete((void *)(thread->task));
  thread->task = 0;
  return;
}

bool k_is_current_thread(struct k_thread *thread) {
  eTaskState thread_state = eTaskGetState((void *)(thread->task));
  if (thread_state == eRunning)
    return true;
  else
    return false;
}

int k_yield(void) {
  taskYIELD();
  return 0;
}

void k_sleep(s32_t dur_ms) {
  TickType_t ticks;
  ticks = pdMS_TO_TICKS(dur_ms);
  vTaskDelay(ticks);
}

unsigned int irq_lock(void) {
  taskENTER_CRITICAL();
  return 1;
}

void irq_unlock(unsigned int key) { taskEXIT_CRITICAL(); }

int k_is_in_isr(void) {
#if defined(ARCH_RISCV)
  return (xPortIsInsideInterrupt());
#else
  /* IRQs + PendSV (14) + SYSTICK (15) are interrupts. */
  return (__get_IPSR() > 13);
#endif

  return 0;
}

void k_timer_init(k_timer_t *timer, k_timer_handler_t handle, void *args) {
  BT_ASSERT(timer != NULL);
  timer->handler = handle;
  timer->args    = args;
  /* Set args as timer id */
  timer->timer.hdl = xTimerCreate("Timer", pdMS_TO_TICKS(1000), 0, args, (TimerCallbackFunction_t)(timer->handler));
  BT_ASSERT(timer->timer.hdl != NULL);
}

void *k_timer_get_id(void *hdl) { return pvTimerGetTimerID((TimerHandle_t)hdl); }

void k_timer_start(k_timer_t *timer, uint32_t timeout) {
  BaseType_t ret;
  (void)ret;

  BT_ASSERT(timer != NULL);
  timer->timeout  = timeout;
  timer->start_ms = k_now_ms();

  ret = xTimerChangePeriod(timer->timer.hdl, pdMS_TO_TICKS(timeout), 0);
  BT_ASSERT(ret == pdPASS);
  ret = xTimerStart(timer->timer.hdl, 0);
  BT_ASSERT(ret == pdPASS);
}

void k_timer_reset(k_timer_t *timer) {
  BaseType_t ret;

  (void)ret;
  BT_ASSERT(timer != NULL);

  ret = xTimerReset(timer->timer.hdl, 0);
  BT_ASSERT(ret == pdPASS);
}

void k_timer_stop(k_timer_t *timer) {
  BaseType_t ret;

  (void)ret;
  BT_ASSERT(timer != NULL);

  ret = xTimerStop(timer->timer.hdl, 0);
  BT_ASSERT(ret == pdPASS);
}

void k_timer_delete(k_timer_t *timer) {
  BaseType_t ret;
  (void)ret;

  BT_ASSERT(timer != NULL);

  ret = xTimerDelete(timer->timer.hdl, 0);
  BT_ASSERT(ret == pdPASS);
}

long long k_now_ms(void) { return (long long)(xTaskGetTickCount() * 1000) / configTICK_RATE_HZ; }

void k_get_random_byte_array(uint8_t *buf, size_t len) {
  // ble_rand() return a word, but *buf may not be word-aligned
  for (int i = 0; i < len; i++) {
    *(buf + i) = (uint8_t)(ble_rand() & 0xFF);
  }
}

void *k_malloc(size_t size) {
#if defined(CFG_USE_PSRAM)
  return pvPortMallocPsram(size);
#else
  return pvPortMalloc(size);
#endif /* CFG_USE_PSRAM */
}

void k_free(void *buf) {
#if defined(CFG_USE_PSRAM)
  return vPortFreePsram(buf);
#else
  return vPortFree(buf);
#endif
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/port/include/bl_port.h
================================================
#ifndef BL_PORT_H
#define BL_PORT_H
#if defined(BL_MCU_SDK)
#include "misc.h"
#endif
#include "ble_config.h"
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include "bl_port.h"

#define BT_UINT_MAX     0xffffffff
#define BL_WAIT_FOREVER 0xffffffffu
#define BL_NO_WAIT      0x0
#define ms2tick         pdMS_TO_TICKS

typedef struct {
    void *hdl;
} bl_hdl_t;

typedef bl_hdl_t _queue_t;
typedef bl_hdl_t _sem_t;
typedef uint32_t _stack_element_t;
typedef bl_hdl_t _mutex_t;
typedef bl_hdl_t bl_timer_t;
typedef uint32_t _task_t;

#define _POLL_EVENT_OBJ_INIT(obj) \
    .poll_events = SYS_DLIST_STATIC_INIT(&obj.poll_events),
#define _POLL_EVENT sys_dlist_t poll_events

#define _K_SEM_INITIALIZER(obj, initial_count, count_limit) \
    {                                                       \
    }

#define K_SEM_INITIALIZER DEPRECATED_MACRO _K_SEM_INITIALIZER

#define K_SEM_DEFINE(name, initial_count, count_limit) \
    struct k_sem name                                  \
        __in_section(_k_sem, static, name) =           \
            _K_SEM_INITIALIZER(name, initial_count, count_limit)

#define K_MUTEX_DEFINE(name)                   \
    struct k_mutex name                        \
        __in_section(_k_mutex, static, name) = \
            _K_MUTEX_INITIALIZER(name)

typedef sys_dlist_t _wait_q_t;

struct k_queue {
    void *hdl;
    sys_dlist_t poll_events;
};

/*attention: this is intialied as zero,the queue variable shoule use k_queue_init\k_lifo_init\k_fifo_init again*/
#define _K_QUEUE_INITIALIZER(obj) \
    {                             \
        0                         \
    }
#define K_QUEUE_INITIALIZER DEPRECATED_MACRO _K_QUEUE_INITIALIZER

void k_queue_init(struct k_queue *queue, int size);
void k_queue_free(struct k_queue *queue);
void k_queue_append(struct k_queue *queue, void *data);
void k_queue_prepend(struct k_queue *queue, void *data);
void k_queue_insert(struct k_queue *queue, void *prev, void *data);
void k_queue_append_list(struct k_queue *queue, void *head, void *tail);
void *k_queue_get(struct k_queue *queue, s32_t timeout);
int k_queue_is_empty(struct k_queue *queue);
int k_queue_get_cnt(struct k_queue *queue);

struct k_lifo {
    struct k_queue _queue;
};

#define _K_LIFO_INITIALIZER(obj)                   \
    {                                              \
        ._queue = _K_QUEUE_INITIALIZER(obj._queue) \
    }

#define K_LIFO_INITIALIZER DEPRECATED_MACRO _K_LIFO_INITIALIZER

#define k_lifo_init(lifo, size) \
    k_queue_init((struct k_queue *)lifo, size)

#define k_lifo_put(lifo, data) \
    k_queue_prepend((struct k_queue *)lifo, data)

#define k_lifo_get(lifo, timeout) \
    k_queue_get((struct k_queue *)lifo, timeout)

#define K_LIFO_DEFINE(name)                    \
    struct k_lifo name                         \
        __in_section(_k_queue, static, name) = \
            _K_LIFO_INITIALIZER(name)

struct k_fifo {
    struct k_queue _queue;
};

#define _K_FIFO_INITIALIZER(obj)                   \
    {                                              \
        ._queue = _K_QUEUE_INITIALIZER(obj._queue) \
    }
#define K_FIFO_INITIALIZER DEPRECATED_MACRO _K_FIFO_INITIALIZER

#define k_fifo_init(fifo, size) \
    k_queue_init((struct k_queue *)fifo, size)

#define k_fifo_put(fifo, data) \
    k_queue_append((struct k_queue *)fifo, data)

#define k_fifo_put_from_isr(fifo, data) \
    k_queue_append_from_isr((struct k_queue *)fifo, data)

#define k_fifo_put_list(fifo, head, tail) \
    k_queue_append_list((struct k_queue *)fifo, head, tail)

#define k_fifo_get(fifo, timeout) \
    k_queue_get((struct k_queue *)fifo, timeout)

#define K_FIFO_DEFINE(name)                    \
    struct k_fifo name                         \
        __in_section(_k_queue, static, name) = \
            _K_FIFO_INITIALIZER(name)

/* sem define*/
struct k_sem {
    _sem_t sem;
    sys_dlist_t poll_events;
};

/**
 * @brief Initialize a semaphore.
 */
int k_sem_init(struct k_sem *sem, unsigned int initial_count, unsigned int limit);

/**
 * @brief Take a semaphore.
 */
int k_sem_take(struct k_sem *sem, uint32_t timeout);

/**
 * @brief Give a semaphore.
 */
int k_sem_give(struct k_sem *sem);

/**
 * @brief Delete a semaphore.
 */
int k_sem_delete(struct k_sem *sem);

/**
 * @brief Get a semaphore's count.
 */
unsigned int k_sem_count_get(struct k_sem *sem);

struct k_mutex {
    _mutex_t mutex;
    sys_dlist_t poll_events;
};

typedef void (*k_timer_handler_t)(void *timer);

typedef struct k_timer {
    bl_timer_t timer;
    k_timer_handler_t handler;
    void *args;
    uint32_t timeout;
    uint32_t start_ms;
} k_timer_t;

/**
 * @brief Initialize a timer.
 */
void k_timer_init(k_timer_t *timer, k_timer_handler_t handle, void *args);

void *k_timer_get_id(void *hdl);

/**
 * @brief Start a timer.
 *
 */
void k_timer_start(k_timer_t *timer, uint32_t timeout);

void k_timer_reset(k_timer_t *timer);

/**
 * @brief Stop a timer.
 */
void k_timer_stop(k_timer_t *timer);

/**
 * @brief Delete a timer.
 *
 */
void k_timer_delete(k_timer_t *timer);

/*time define*/
#define MSEC_PER_SEC 1000
#define K_MSEC(ms)   (ms)
#define K_SECONDS(s) K_MSEC((s)*MSEC_PER_SEC)
#define K_MINUTES(m) K_SECONDS((m)*60)
#define K_HOURS(h)   K_MINUTES((h)*60)

#define K_PRIO_COOP(x) x

/**
 * @brief Get time now.
 *
 * @return time(in milliseconds)
 */
int64_t k_uptime_get();
u32_t k_uptime_get_32(void);

struct k_thread {
    _task_t task;
};

typedef _stack_element_t k_thread_stack_t;

inline void k_call_stacks_analyze(void)
{
}

#define K_THREAD_STACK_DEFINE(sym, size) _stack_element_t sym[size]
#define K_THREAD_STACK_SIZEOF(sym)       sizeof(sym)

static inline char *K_THREAD_STACK_BUFFER(k_thread_stack_t *sym)
{
    return (char *)sym;
}

typedef void (*k_thread_entry_t)(void *args);

int k_thread_create(struct k_thread *new_thread, const char *name,
                    size_t stack_size, k_thread_entry_t entry,
                    int prio);

void k_thread_delete(struct k_thread *new_thread);

bool k_is_current_thread(struct k_thread *thread);

/**
 * @brief Yield the current thread.
 */
int k_yield();

/**
 * @brief suspend the current thread for a certain time
 */

void k_sleep(s32_t duration);

/**
 * @brief Lock interrupts.
 */
unsigned int irq_lock();

/**
 * @brief Unlock interrupts.
 */
void irq_unlock(unsigned int key);

int k_is_in_isr(void);

#ifdef BIT
#undef BIT
#define BIT(n) (1UL << (n))
#else
#define BIT(n) (1UL << (n))
#endif

long long k_now_ms(void);
void k_get_random_byte_array(uint8_t *buf, size_t len);
void *k_malloc(size_t size);
void k_free(void *buf);
#endif /* BL_PORT_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/port/include/ble_config.h
================================================
#ifndef BLE_CONFIG_H
#define BLE_CONFIG_H

#include "FreeRTOSConfig.h"

/**
 * CONFIG_BLUETOOTH: Enable the bluetooh stack
 */
// #ifndef CONFIG_BLUETOOTH
// #error "CONFIG_BLUETOOTH not defined,this header shoudn't include"
// #endif

#ifdef CONFIG_BT_BONDABLE
#undef CONFIG_BT_BONDABLE
#define CONFIG_BT_BONDABLE 1
#endif

#define CONFIG_BT_SMP_ALLOW_UNAUTH_OVERWRITE 1

#if defined(CONFIG_BT_STACK_PTS)

#ifndef PTS_CHARC_LEN_EQUAL_MTU_SIZE
#define PTS_CHARC_LEN_EQUAL_MTU_SIZE
#endif

// #ifndef  CONFIG_BT_STACK_PTS_SM_SLA_KDU_BI_01
// #define  CONFIG_BT_STACK_PTS_SM_SLA_KDU_BI_01
// #endif

// #ifndef  PTS_GAP_SLAVER_CONFIG_READ_CHARC
// #define  PTS_GAP_SLAVER_CONFIG_READ_CHARC
// #endif

// #ifndef  PTS_GAP_SLAVER_CONFIG_WRITE_CHARC
// #define  PTS_GAP_SLAVER_CONFIG_WRITE_CHARC
// #endif

// #ifndef  PTS_GAP_SLAVER_CONFIG_NOTIFY_CHARC
// #define  PTS_GAP_SLAVER_CONFIG_NOTIFY_CHARC
// #endif

// #ifndef  PTS_GAP_SLAVER_CONFIG_INDICATE_CHARC
// #define  PTS_GAP_SLAVER_CONFIG_INDICATE_CHARC
// #endif
#define CONFIG_BT_GATT_READ_MULTIPLE 1
#endif

/**
 * CONFIG_BT_HCI_RX_STACK_SIZE: rx thread stack size
 */
#ifndef CONFIG_BT_HCI_RX_STACK_SIZE
#define CONFIG_BT_HCI_RX_STACK_SIZE 512
#endif

/**
 * BL_BLE_CO_THREAD: combine tx rx thread
 */
#define BFLB_BT_CO_THREAD 1

#if (BFLB_BT_CO_THREAD)
#define CONFIG_BT_CO_TASK_PRIO (configMAX_PRIORITIES - 3)
#if defined(CONFIG_BT_MESH)
#define CONFIG_BT_CO_STACK_SIZE 3072 // 2048//1536//1024
#else
#define CONFIG_BT_CO_STACK_SIZE 2048 // 2048//1536//1024
#endif
#endif

#ifndef CONFIG_BT_RX_STACK_SIZE
#if defined(CONFIG_BT_MESH)
#define CONFIG_BT_RX_STACK_SIZE 3072 // 2048//1536//1024
#else
#if !defined(CONFIG_BT_CONN)
#define CONFIG_BT_RX_STACK_SIZE 1024
#else
#define CONFIG_BT_RX_STACK_SIZE 2048 // 1536//1024
#endif
#endif
#endif

#ifndef CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE
#define CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE 156
#endif

#define CONFIG_BT_HCI_ECC_STACK_SIZE 384

#ifndef CONFIG_BT_RX_PRIO
#define CONFIG_BT_RX_PRIO (configMAX_PRIORITIES - 4)
#endif
/**
 * CONFIG_BT: Tx thread stack size
 */

#ifndef CONFIG_BT_HCI_TX_STACK_SIZE
#if !defined(CONFIG_BT_CONN)
#define CONFIG_BT_HCI_TX_STACK_SIZE 1024
#else
#define CONFIG_BT_HCI_TX_STACK_SIZE 1536 // 1024//200
#endif
#endif

/**
 * CONFIG_BT_HCI_TX_PRIO: tx thread priority
 */
#ifndef CONFIG_BT_HCI_TX_PRIO
#define CONFIG_BT_HCI_TX_PRIO (configMAX_PRIORITIES - 3)
#endif

#ifndef CONFIG_BT_CTLR_RX_PRIO
#define CONFIG_BT_CTLR_RX_PRIO (configMAX_PRIORITIES - 4)
#endif

/**
 * CONFIG_BT_HCI_CMD_COUNT: hci cmd buffer count,range 2 to 64
 */
#ifndef CONFIG_BT_HCI_CMD_COUNT
#define CONFIG_BT_HCI_CMD_COUNT 2
#endif

/**
 * CONFIG_BT_RX_BUF_COUNT: number of buffer for incoming ACL packages or HCI
 * events,range 2 to 255
 */
#ifndef CONFIG_BT_RX_BUF_COUNT

#if defined(CONFIG_BT_MESH)
#define CONFIG_BT_RX_BUF_COUNT 10
#else
#define CONFIG_BT_RX_BUF_COUNT 5
#endif // CONFIG_BT_MESH
#endif

/**
 * CONFIG_BT_RX_BUF_RSV_COUNT: number of buffer that HCI_LE_EVENT reserved
 * events,range 1 to CONFIG_BT_RX_BUF_COUNT
 */
#define CONFIG_BT_RX_BUF_RSV_COUNT (1)
#if (CONFIG_BT_RX_BUF_RSV_COUNT >= CONFIG_BT_RX_BUF_COUNT)
#error "CONFIG_BT_RX_BUF_RSV_COUNT config error"
#endif

/**
 * CONFIG_BT_RX_BUF_LEN: the max length for rx buffer
 * range 73 to 2000
 */
#ifndef CONFIG_BT_RX_BUF_LEN
#if defined(CONFIG_BT_BREDR)
#define CONFIG_BT_RX_BUF_LEN 680 // CONFIG_BT_L2CAP_RX_MTU + 4 + 4
#else
#define CONFIG_BT_RX_BUF_LEN 255 // 108 //76
#endif
#endif

/**
 * CONFIG_BT_CENTRAL: Enable central Role
 */
#ifdef CONFIG_BT_CENTRAL
#undef CONFIG_BT_CENTRAL
#define CONFIG_BT_CENTRAL 1
#endif

/**
 * CONFIG_BT_WHITELIST : Enable autoconnect whilt list device */
#ifndef CONFIG_BT_WHITELIST
#define CONFIG_BT_WHITELIST 1
#endif

/**
 * CONFIG_BT_PERIPHERAL: Enable peripheral Role
 */
#ifdef CONFIG_BT_PERIPHERAL
#undef CONFIG_BT_PERIPHERAL
#define CONFIG_BT_PERIPHERAL 1
#endif

#if defined(CONFIG_BT_CENTRAL) || defined(CONFIG_BT_PERIPHERAL)
#undef CONFIG_BT_CONN
#define CONFIG_BT_CONN 1
#endif

#ifdef CONFIG_BT_CONN

#ifndef CONFIG_BT_CREATE_CONN_TIMEOUT
#define CONFIG_BT_CREATE_CONN_TIMEOUT 3
#endif

#if defined(BFLB_BLE)
#ifndef CONFIG_BT_CONN_PARAM_UPDATE_TIMEOUT
#define CONFIG_BT_CONN_PARAM_UPDATE_TIMEOUT 5
#endif
#endif
/**
 * CONFIG_BLUETOOTH_L2CAP_TX_BUF_COUNT: number of buffer for outgoing L2CAP packages
 * range 2 to 255
 */
#ifndef CONFIG_BT_L2CAP_TX_BUF_COUNT
#define CONFIG_BT_L2CAP_TX_BUF_COUNT CFG_BLE_TX_BUFF_DATA
#endif

/**
 * CONFIG_BT_L2CAP_TX_MTU: Max L2CAP MTU for L2CAP tx buffer
 * range 65 to 2000 if SMP enabled,otherwise range 23 to 2000
 */
#ifndef CONFIG_BT_L2CAP_TX_MTU
#ifdef CONFIG_BT_SMP
#define CONFIG_BT_L2CAP_TX_MTU 247 // 96 //65
#else
#define CONFIG_BT_L2CAP_TX_MTU 247 // 23
#endif
#endif

/**
 * CONFIG_BT_L2CAP_TX_USER_DATA_SIZE: the max length for L2CAP tx buffer user data size
 * range 4 to 65535
 */
#ifndef CONFIG_BT_L2CAP_TX_USER_DATA_SIZE
#define CONFIG_BT_L2CAP_TX_USER_DATA_SIZE 4
#endif

#if defined(CONFIG_BT_STACK_PTS) && (defined(PTS_GAP_SLAVER_CONFIG_WRITE_CHARC) || defined(PTS_TEST_CASE_INSUFFICIENT_KEY))
#define CONFIG_BT_ATT_PREPARE_COUNT 64
#else
/**
 * CONFIG_BT_ATT_PREPARE_COUNT: Number of buffers available for ATT prepare write, setting
 * this to 0 disables GATT long/reliable writes.
 * range 0 to 64
 */
#ifndef CONFIG_BT_ATT_PREPARE_COUNT
#define CONFIG_BT_ATT_PREPARE_COUNT 0
#endif
#endif

/**
 *  CONFIG_BLUETOOTH_SMP:Eable the Security Manager Protocol
 *  (SMP), making it possible to pair devices over LE
 */
#ifdef CONFIG_BT_SMP
#undef CONFIG_BT_SMP
#define CONFIG_BT_SMP 1

/**
 *  CONFIG_BT_SIGNING:enables data signing which is used for transferring
 *  authenticated data in an unencrypted connection
 */
#ifdef CONFIG_BT_SIGNING
#undef CONFIG_BT_SIGNING
#define CONFIG_BT_SIGNING 1
#endif

/**
 *  CONFIG_BT_SMP_SC_ONLY:enables support for Secure Connection Only Mode. In this
 *  mode device shall only use Security Mode 1 Level 4 with exception
 *  for services that only require Security Mode 1 Level 1 (no security).
 *  Security Mode 1 Level 4 stands for authenticated LE Secure Connections
 *  pairing with encryption. Enabling this option disables legacy pairing
 */
#ifdef CONFIG_BT_SMP_SC_ONLY
#undef CONFIG_BT_SMP_SC_ONLY
#define CONFIG_BT_SMP_SC_ONLY 1
#endif

/**
 *  CONFIG_BT_USE_DEBUG_KEYS:This option places Security Manager in
 *  a Debug Mode. In this mode predefined
 *  Diffie-Hellman private/public key pair is used as described
 *  in Core Specification Vol. 3, Part H, 2.3.5.6.1. This option should
 *  only be enabled for debugging and should never be used in production.
 *  If this option is enabled anyone is able to decipher encrypted air
 *  traffic.
 */
#ifdef CONFIG_BT_USE_DEBUG_KEYS
#ifndef CONFIG_BT_TINYCRYPT_ECC
#error "CONFIG_BT_USE_DEBUG_KEYS depends on CONFIG_BT_TINYCRYPT_ECC"
#endif
#undef CONFIG_BT_USE_DEBUG_KEYS
#define CONFIG_BT_USE_DEBUG_KEYS 1
#endif

/**
 *  CONFIG_BT_L2CAP_DYNAMIC_CHANNEL:enables support for LE Connection
 *  oriented Channels,allowing the creation of dynamic L2CAP Channels
 */
#ifdef CONFIG_BT_L2CAP_DYNAMIC_CHANNEL
#undef CONFIG_BT_L2CAP_DYNAMIC_CHANNEL
#define CONFIG_BT_L2CAP_DYNAMIC_CHANNEL 1
#endif

#endif

/**
 *   CONFIG_BT_PRIVACY:Enable local Privacy Feature support. This makes it possible
 *   to use Resolvable Private Addresses (RPAs).
 */
#ifdef CONFIG_BT_PRIVACY
#ifndef CONFIG_BT_SMP
#error "CONFIG_BT_PRIVACY depends on CONFIG_BT_SMP"
#endif
#undef CONFIG_BT_PRIVACY
#define CONFIG_BT_PRIVACY 1

/**
 * CONFIG_BT_RPA_TIMEOUT:Resolvable Private Address timeout
 * range 1 to 65535,seconds
 */
#ifndef CONFIG_BT_RPA_TIMEOUT
#if defined(CONFIG_AUTO_PTS)
#define CONFIG_BT_RPA_TIMEOUT 60
#else
#define CONFIG_BT_RPA_TIMEOUT 900
#endif
#endif
#endif

/**
 *  CONFIG_BT_GATT_DYNAMIC_DB:enables GATT services to be added dynamically to database
 */
#ifdef CONFIG_BT_GATT_DYNAMIC_DB
#undef CONFIG_BT_GATT_DYNAMIC_DB
#define CONFIG_BT_GATT_DYNAMIC_DB 1
#endif

/**
 *  CONFIG_BT_GATT_CLIENT:GATT client role support
 */
#ifdef CONFIG_BT_GATT_CLIENT
#undef CONFIG_BT_GATT_CLIENT
#define CONFIG_BT_GATT_CLIENT 1
#endif

/**
 *  CONFIG_BT_MAX_PAIRED:Maximum number of paired devices
 *  range 1 to 128
 */
#ifndef CONFIG_BT_MAX_PAIRED
#define CONFIG_BT_MAX_PAIRED CONFIG_BT_MAX_CONN
#endif
#endif

/**
 * If this option is set TinyCrypt library is used for emulating the
 * ECDH HCI commands and events needed by e.g. LE Secure Connections.
 * In builds including the BLE Host, if not set the controller crypto is
 * used for ECDH and if the controller doesn't support the required HCI
 * commands the LE Secure Connections support will be disabled.
 * In builds including the HCI Raw interface and the BLE Controller, this
 * option injects support for the 2 HCI commands required for LE Secure
 * Connections so that Hosts can make use of those
 */
#ifdef CONFIG_BT_TINYCRYPT_ECC
#undef CONFIG_BT_TINYCRYPT_ECC
#define CONFIG_BT_TINYCRYPT_ECC 1
#endif
/**
 *  CONFIG_BLUETOOTH_MAX_CONN:Maximum number of connections
 *  range 1 to 128
 */
#ifndef CONFIG_BT_MAX_CONN
#define CONFIG_BT_MAX_CONN CFG_CON
#endif

/**
 *  CONFIG_BT_DEVICE_NAME:Bluetooth device name. Name can be up
 *  to 248 bytes long (excluding NULL termination). Can be empty string
 */
#ifndef CONFIG_BT_DEVICE_NAME
#if defined(CONFIG_AUTO_PTS)
#define CONFIG_BT_DEVICE_NAME "AUTO_PTS_TEST0123456789012345"
#else
#if defined(BL602)
#define CONFIG_BT_DEVICE_NAME "BL602-BLE-DEV"
#elif defined(BL702)
#define CONFIG_BT_DEVICE_NAME "BL702-BLE-DEV"
#else
#define CONFIG_BT_DEVICE_NAME "BTBLE-DEV"
#endif
#endif
#endif
/**
 *  CONFIG_BT_CONTROLLER_NAME:Bluetooth controller name.
 */
#ifndef CONFIG_BT_CONTROLLER_NAME
#if defined(BL602)
#define CONFIG_BT_CONTROLLER_NAME "BL602-BLE-DEV"
#else
#define CONFIG_BT_CONTROLLER_NAME "BL702-BLE-DEV"
#endif
#endif

/**
 *  CONFIG_BT_MAX_SCO_CONN:Maximum number of simultaneous SCO connections.
 */
#ifndef CONFIG_BT_MAX_SCO_CONN
#define CONFIG_BT_MAX_SCO_CONN CONFIG_MAX_SCO
#endif

/**
 *  CONFIG_BT_WORK_QUEUE_STACK_SIZE:Work queue stack size.
 */
#ifndef CONFIG_BT_WORK_QUEUE_STACK_SIZE
#ifndef CONFIG_BT_MESH
#define CONFIG_BT_WORK_QUEUE_STACK_SIZE 1536 // 1280//512
#else
#if !defined(CONFIG_BT_CONN)
#define CONFIG_BT_WORK_QUEUE_STACK_SIZE 1024
#else
#define CONFIG_BT_WORK_QUEUE_STACK_SIZE 2048
#endif /* CONFIG_BT_MESH */
#endif
#endif

/**
 *  CONFIG_BT_WORK_QUEUE_PRIO:Work queue priority.
 */
#ifndef CONFIG_BT_WORK_QUEUE_PRIO
#define CONFIG_BT_WORK_QUEUE_PRIO (configMAX_PRIORITIES - 2)
#endif

/**
 *  CONFIG_BT_HCI_RESERVE:Headroom that the driver needs for sending and receiving buffers.
 */
#ifndef CONFIG_BT_HCI_RESERVE
#ifdef CONFIG_BLUETOOTH_H4
#define CONFIG_BT_HCI_RESERVE 0
#elif defined(CONFIG_BLUETOOTH_H5) || defined(CONFIG_BLUETOOTH_SPI)
#define CONFIG_BT_HCI_RESERVE 1
#else
#define CONFIG_BT_HCI_RESERVE 1
#endif
#endif

/**
 *  CONFIG_BLUETOOTH_DEBUG_LOG:Enable bluetooth debug log.
 */
#if defined(BFLB_BLE)
#if defined(CFG_BLE_STACK_DBG_PRINT)
#undef CONFIG_BT_DEBUG
#define CONFIG_BT_DEBUG 1
#endif
#else
#ifdef CONFIG_BT_DEBUG_LOG
#undef CONFIG_BT_DEBUG_LOG
#define CONFIG_BT_DEBUG_LOG 1
#undef CONFIG_BT_DEBUG
#define CONFIG_BT_DEBUG 1
#endif
#endif
/**
 *  CONFIG_BT_DEBUG_L2CAP:Enable bluetooth l2cap debug log.
 */
#ifdef CONFIG_BT_DEBUG_L2CAP
#undef CONFIG_BT_DEBUG_L2CAP
#define CONFIG_BT_DEBUG_L2CAP 1
#endif

/**
 *  CONFIG_BT_DEBUG_CONN:Enable bluetooth conn debug log.
 */
#ifdef CONFIG_BT_DEBUG_CONN
#undef CONFIG_BT_DEBUG_CONN
#define CONFIG_BT_DEBUG_CONN 1
#endif

/**
 *  CONFIG_BT_DEBUG_ATT:Enable bluetooth att debug log.
 */
#ifdef CONFIG_BT_DEBUG_ATT
#undef CONFIG_BT_DEBUG_ATT
#define CONFIG_BT_DEBUG_ATT 1
#endif

/**
 *  CONFIG_BT_DEBUG_GATT:Enable bluetooth gatt debug log.
 */
#ifdef CONFIG_BT_DEBUG_GATT
#undef CONFIG_BT_DEBUG_GATT
#define CONFIG_BT_DEBUG_GATT 1
#endif

/**
 *  CONFIG_BT_DEBUG_HCI_CORE:Enable bluetooth hci core debug log.
 */
#ifdef CONFIG_BT_DEBUG_HCI_CORE
#undef CONFIG_BT_DEBUG_HCI_CORE
#define CONFIG_BT_DEBUG_HCI_CORE 1
#endif

/**
 *  CONFIG_BT_DEBUG_HCI_DRIVER:Enable bluetooth hci driver debug log.
 */
#ifdef CONFIG_BT_DEBUG_HCI_DRIVER
#undef CONFIG_BT_DEBUG_HCI_DRIVER
#define CONFIG_BT_DEBUG_HCI_DRIVER 1
#endif

/**
 *  CONFIG_BT_TEST:Enable bluetooth test.
 */
#ifdef CONFIG_BT_TEST
#undef CONFIG_BT_TEST
#define CONFIG_BT_TEST 1
#endif

/**
 *  CONFIG_BT_DEBUG_CORE:Enable bluetooth core debug log.
 */
#ifdef CONFIG_BT_DEBUG_CORE
#undef CONFIG_BT_DEBUG_CORE
#define CONFIG_BT_DEBUG_CORE 1
#endif

#ifndef CONFIG_BT_ATT_TX_MAX
/*
 *  Take throuthput test into consideration, set att tx max the same with lowstack tx buffer count.
 *  att semaphore determine the max numble packets can send to lowsatck at once.
 */
#define CONFIG_BT_ATT_TX_MAX 10
#endif

#ifndef CONFIG_BT_CONN_TX_MAX
/*
 *  Take throuthput test into consideration, set upperstack conn tx max the same with lowstack tx buffer count.
 */
#define CONFIG_BT_CONN_TX_MAX 10
#endif

#ifndef CONFIG_BT_DEVICE_APPEARANCE
#define CONFIG_BT_DEVICE_APPEARANCE 833
#endif

#if defined(BFLB_BLE)
#ifndef CONFIG_BT_RECV_IS_RX_THREAD
#define CONFIG_BT_RECV_IS_RX_THREAD
#endif

#ifndef CONFIG_NET_BUF_USER_DATA_SIZE
#define CONFIG_NET_BUF_USER_DATA_SIZE 10
#endif

#ifndef CONFIG_BT_ID_MAX
#define CONFIG_BT_ID_MAX 1
#endif

// #define PTS_GAP_SLAVER_CONFIG_NOTIFY_CHARC 1

#ifndef CONFIG_BT_L2CAP_TX_FRAG_COUNT
#define CONFIG_BT_L2CAP_TX_FRAG_COUNT 0
#endif

#ifndef CONFIG_BT_DEVICE_NAME_DYNAMIC
#define CONFIG_BT_DEVICE_NAME_DYNAMIC 1
#endif

// max lenght of ADV payload is 37 bytes (by BT core spec)
// AdvA field takes up 6 bytes
// if only Local Name is appended, then max lenght of Local Name shall be
// 37-6-2=31 bytes, where UUID of Local Name takes up 2 bytes
#define CONFIG_BT_DEVICE_NAME_MAX 29

#if defined(CONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS)
#define CONFIG_BT_PERIPHERAL_PREF_MIN_INT       0x0018
#define CONFIG_BT_PERIPHERAL_PREF_MAX_INT       0x0028
#define CONFIG_BT_PERIPHERAL_PREF_SLAVE_LATENCY 0
#define CONFIG_BT_PERIPHERAL_PREF_TIMEOUT       400
#endif

#ifndef CONFIG_BT_PHY_UPDATE
#define CONFIG_BT_PHY_UPDATE 1
#endif

#if defined(CONFIG_BT_BREDR)
#define CONFIG_BT_PAGE_TIMEOUT 0x2000 // 5.12s
#define CONFIG_BT_L2CAP_RX_MTU 672

#ifndef CONFIG_BT_RFCOMM_TX_STACK_SIZE
#define CONFIG_BT_RFCOMM_TX_STACK_SIZE 1024
#endif
#ifndef CONFIG_BT_RFCOMM_TX_PRIO
#define CONFIG_BT_RFCOMM_TX_PRIO (configMAX_PRIORITIES - 5)
#endif

#define PCM_PRINTF 0
#endif

#if defined(CONFIG_BT_AUDIO)
#define CONFIG_BT_MAX_ISO_CONN 8 // range 1 to 64

#endif

/*******************************Bouffalo Lab Modification******************************/

// #define BFLB_BLE_DISABLE_STATIC_ATTR
// #define BFLB_BLE_DISABLE_STATIC_CHANNEL
#define BFLB_DISABLE_BT
#define BFLB_FIXED_IRK 0
#define BFLB_DYNAMIC_ALLOC_MEM
#if defined(CFG_BLE_PDS) && defined(BL702) && defined(BFLB_BLE) && defined(BFLB_DYNAMIC_ALLOC_MEM)
#define BFLB_STATIC_ALLOC_MEM 1
#else
#define BFLB_STATIC_ALLOC_MEM 0
#endif
#define CONFIG_BT_SCAN_WITH_IDENTITY 1

#if defined(CONFIG_AUTO_PTS)
#define CONFIG_BT_L2CAP_DYNAMIC_CHANNEL
#define CONFIG_BT_DEVICE_NAME_GATT_WRITABLE 1
#define CONFIG_BT_GATT_SERVICE_CHANGED      1
#define CONFIG_BT_GATT_CACHING              1
#define CONFIG_BT_SCAN_WITH_IDENTITY        1
// #define CONFIG_BT_ADV_WITH_PUBLIC_ADDR 1
#define CONFIG_BT_ATT_PREPARE_COUNT 64
#endif
#endif // BFLB_BLE

/*******************************Bouffalo Lab Patch******************************/
/*Fix the issue that DHKEY_check_failed error happens in smp procedure if CONFIG_BT_PRIVACY is enabled.*/
#define BFLB_BLE_PATCH_DHKEY_CHECK_FAILED
/*To notify upper layer that write_ccc is completed*/
#define BFLB_BLE_PATCH_NOTIFY_WRITE_CCC_RSP
/*Timer/Queue/Sem allocated during connection establishment is not released when disconnection
happens, which cause memory leak issue.*/
#define BFLB_BLE_PATCH_FREE_ALLOCATED_BUFFER_IN_OS
/*To avoid duplicated pubkey callback.*/
#define BFLB_BLE_PATCH_AVOID_DUPLI_PUBKEY_CB
/*The flag @conn_ref is not clean up after disconnect*/
// #define BFLB_BLE_PATCH_CLEAN_UP_CONNECT_REF
#if !defined(CONFIG_AUTO_PTS)
/*To avoid sevice changed indication sent at the very beginning, without any new service added.*/
#define BFLB_BLE_PATCH_SET_SCRANGE_CHAGD_ONLY_IN_CONNECTED_STATE
#endif
#ifdef CONFIG_BT_SETTINGS
/*Semaphore is used during flash operation. Make sure that freertos has already run up when it
  intends to write information to flash.*/
#define BFLB_BLE_PATCH_SETTINGS_LOAD
#endif
#define BFLB_BLE_SMP_LOCAL_AUTH
#define BFLB_BLE_MTU_CHANGE_CB
#if defined(CFG_BT_RESET)
#define BFLB_HOST_ASSISTANT
#endif

#define BFLB_RELEASE_CMD_SEM_IF_CONN_DISC
/*Fix the issue when local auth_req is 0(no boinding),
BT_SMP_DIST_ENC_KEY bit is not cleared while remote ENC_KEY is received.*/
#define BFLB_BLE_PATCH_CLEAR_REMOTE_KEY_BIT

#if defined(CONFIG_BT_CENTRAL) || defined(CONFIG_BT_OBSERVER)
#if defined(BL602) || defined(BL702)
#define BFLB_BLE_NOTIFY_ADV_DISCARDED
#endif
#endif

#if defined(CONFIG_BT_CENTRAL)
#define BFLB_BLE_NOTIFY_ALL
#define BFLB_BLE_DISCOVER_ONGOING
#endif

#endif /* BLE_CONFIG_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/port/include/zephyr.h
================================================
#ifndef ZEPHYR_H
#define ZEPHYR_H
#include 
#include 

#include 
#include 
#include 
#include "bl_port.h"
#include "work_q.h"

#if defined(__cplusplus)
extern "C" {
#endif

#define _STRINGIFY(x) #x
#if 0
#define ___in_section(a, b, c) \
    __attribute__((section("." _STRINGIFY(a) "." _STRINGIFY(b) "." _STRINGIFY(c))))

#endif
#define ARG_UNUSED(x) (void)(x)

#ifndef __aligned
#define __aligned(x) __attribute__((__aligned__(x)))
#endif

#ifndef __printf_like
#define __printf_like(f, a) __attribute__((format(printf, f, a)))
#endif
#define STACK_ALIGN 4

#define ASSERT(test, fmt, ...)

#define K_FOREVER -1
#define K_NO_WAIT 0

/* Unaligned access */
#define UNALIGNED_GET(p)                     \
    __extension__({                          \
        struct __attribute__((__packed__)) { \
            __typeof__(*(p)) __v;            \
        } *__p = (__typeof__(__p))(p);       \
        __p->__v;                            \
    })

#ifndef UNUSED
#define UNUSED(x) (void)x
#endif

enum _poll_types_bits {
    _POLL_TYPE_IGNORE,
    _POLL_TYPE_SIGNAL,
    _POLL_TYPE_SEM_AVAILABLE,
    _POLL_TYPE_DATA_AVAILABLE,
    _POLL_NUM_TYPES
};

#define _POLL_TYPE_BIT(type) (1 << ((type)-1))

enum _poll_states_bits {
    _POLL_STATE_NOT_READY,
    _POLL_STATE_SIGNALED,
    _POLL_STATE_SEM_AVAILABLE,
    _POLL_STATE_DATA_AVAILABLE,
    _POLL_NUM_STATES
};

#define _POLL_STATE_BIT(state) (1 << ((state)-1))

#define _POLL_EVENT_NUM_UNUSED_BITS                             \
    (32 - (0 + 8                                    /* tag */   \
           + _POLL_NUM_TYPES + _POLL_NUM_STATES + 1 /* modes */ \
           ))

#define K_POLL_SIGNAL_INITIALIZER(obj)                          \
    {                                                           \
        .poll_events = SYS_DLIST_STATIC_INIT(&obj.poll_events), \
        .signaled = 0,                                          \
        .result = 0,                                            \
    }

struct k_poll_event {
    sys_dnode_t _node;
    struct _poller *poller;
    u32_t tag : 8;
    u32_t type : _POLL_NUM_TYPES;
    u32_t state : _POLL_NUM_STATES;
    u32_t mode : 1;
    u32_t unused : _POLL_EVENT_NUM_UNUSED_BITS;
    union {
        void *obj;
        struct k_poll_signal *signal;
        struct k_sem *sem;
        struct k_fifo *fifo;
        struct k_queue *queue;
    };
};

struct k_poll_signal {
    sys_dlist_t poll_events;
    unsigned int signaled;
    int result;
};

#define K_POLL_STATE_NOT_READY           0
#define K_POLL_STATE_EADDRINUSE          1
#define K_POLL_STATE_SIGNALED            2
#define K_POLL_STATE_SEM_AVAILABLE       3
#define K_POLL_STATE_DATA_AVAILABLE      4
#define K_POLL_STATE_FIFO_DATA_AVAILABLE K_POLL_STATE_DATA_AVAILABLE

#define K_POLL_TYPE_IGNORE              0
#define K_POLL_TYPE_SIGNAL              1
#define K_POLL_TYPE_SEM_AVAILABLE       2
#define K_POLL_TYPE_DATA_AVAILABLE      3
#define K_POLL_TYPE_FIFO_DATA_AVAILABLE K_POLL_TYPE_DATA_AVAILABLE

#define K_POLL_EVENT_STATIC_INITIALIZER(event_type, event_mode, event_obj, \
                                        event_tag)                         \
    {                                                                      \
        .type = event_type,                                                \
        .tag = event_tag,                                                  \
        .state = K_POLL_STATE_NOT_READY,                                   \
        .mode = event_mode,                                                \
        .unused = 0,                                                       \
        { .obj = event_obj },                                              \
    }

extern int k_poll_signal_raise(struct k_poll_signal *signal, int result);
#if (BFLB_BT_CO_THREAD)
extern int k_poll(struct k_poll_event *events, int num_events, int total_evt_array_cnt, s32_t timeout, u8_t *to_process);
#else
extern int k_poll(struct k_poll_event *events, int num_events, s32_t timeout);
#endif
extern void k_poll_event_init(struct k_poll_event *event, u32_t type, int mode, void *obj);

/* public - polling modes */
enum k_poll_modes {
    /* polling thread does not take ownership of objects when available */
    K_POLL_MODE_NOTIFY_ONLY = 0,

    K_POLL_NUM_MODES
};

#define k_oops()

//void k_sleep(s32_t duration);

#if defined(__cplusplus)
}
#endif

#endif /* ZEPHYR_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/bas.c
================================================
/** @file
 *  @brief GATT Battery Service
 */

/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 

#include "bas.h"
#include "bluetooth.h"
#include "conn.h"
#include "gatt.h"
#include "uuid.h"

#if !defined(BFLB_BLE)
#define LOG_LEVEL CONFIG_BT_GATT_BAS_LOG_LEVEL
#include 
LOG_MODULE_REGISTER(bas);
#endif

static u8_t battery_level = 100U;

static void blvl_ccc_cfg_changed(const struct bt_gatt_attr *attr, u16_t value) {
  ARG_UNUSED(attr);

  bool notif_enabled = (value == BT_GATT_CCC_NOTIFY);

#if !defined(BFLB_BLE)
  LOG_INF("BAS Notifications %s", notif_enabled ? "enabled" : "disabled");
#endif
}

static ssize_t read_blvl(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  u8_t lvl8 = battery_level;

  return bt_gatt_attr_read(conn, attr, buf, len, offset, &lvl8, sizeof(lvl8));
}

static struct bt_gatt_attr attrs[] = {
    BT_GATT_PRIMARY_SERVICE(BT_UUID_BAS),
    BT_GATT_CHARACTERISTIC(BT_UUID_BAS_BATTERY_LEVEL, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, BT_GATT_PERM_READ, read_blvl, NULL, &battery_level),
    BT_GATT_CCC(blvl_ccc_cfg_changed, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE),
    BT_GATT_DESCRIPTOR(BT_UUID_HIDS_REPORT_REF, BT_GATT_PERM_READ, NULL, NULL, NULL),
};

struct bt_gatt_service bas = BT_GATT_SERVICE(attrs);

void bas_init(void) { bt_gatt_service_register(&bas); }

u8_t bt_gatt_bas_get_battery_level(void) { return battery_level; }

int bt_gatt_bas_set_battery_level(u8_t level) {
  int rc;

  if (level > 100U) {
    return -EINVAL;
  }

  battery_level = level;

  rc = bt_gatt_notify(NULL, &bas.attrs[1], &level, sizeof(level));

  return rc == -ENOTCONN ? 0 : rc;
}

#if !defined(BFLB_BLE)
SYS_INIT(bas_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/bas.h
================================================
/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_BAS_H_
#define ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_BAS_H_

/**
 * @brief Battery Service (BAS)
 * @defgroup bt_gatt_bas Battery Service (BAS)
 * @ingroup bluetooth
 * @{
 *
 * [Experimental] Users should note that the APIs can change
 * as a part of ongoing development.
 */

#ifdef __cplusplus
extern "C" {
#endif

#include 

void bas_init(void);

/** @brief Read battery level value.
 *
 * Read the characteristic value of the battery level
 *
 *  @return The battery level in percent.
 */
u8_t bt_gatt_bas_get_battery_level(void);

/** @brief Update battery level value.
 *
 * Update the characteristic value of the battery level
 * This will send a GATT notification to all current subscribers.
 *
 *  @param level The battery level in percent.
 *
 *  @return Zero in case of success and error code in case of error.
 */
int bt_gatt_bas_set_battery_level(u8_t level);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif /* ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_BAS_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/dis.c
================================================
/** @file
 *  @brief GATT Device Information Service
 */

/*
 * Copyright (c) 2019 Demant
 * Copyright (c) 2018 Nordic Semiconductor ASA
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 
#include 
#include 
#include 
#include 

#include "settings.h"

#include "bluetooth.h"
#include "conn.h"
#include "dis.h"
#include "gatt.h"
#include "hci_host.h"
#include "uuid.h"

#if !defined(BFLB_BLE)
#define BT_DBG_ENABLED  IS_ENABLED(CONFIG_BT_DEBUG_SERVICE)
#define LOG_MODULE_NAME bt_dis
#include "log.h"
#endif

#if CONFIG_BT_GATT_DIS_PNP
struct dis_pnp {
  u8_t  pnp_vid_src;
  u16_t pnp_vid;
  u16_t pnp_pid;
  u16_t pnp_ver;
} __packed;

#if defined(BFLB_BLE)
#if defined(BL702)
#define CONFIG_BT_GATT_DIS_MODEL "BL702_BLE_MODEL"
#elif defined(BL602)
#define CONFIG_BT_GATT_DIS_MODEL "BL602_BLE_MODEL"
#else
#define CONFIG_BT_GATT_DIS_MODEL
#endif

#define CONFIG_BT_GATT_DIS_MANUF             "Bouffalo Lab"
#define CONFIG_BT_GATT_DIS_SERIAL_NUMBER_STR "G0G0U40690230TFC"
#define CONFIG_BT_GATT_DIS_FW_REV_STR        "52512901"
#define CONFIG_BT_GATT_DIS_HW_REV_STR        "0001"
#define CONFIG_BT_GATT_DIS_SW_REV_STR        "123"

#define CONFIG_BT_GATT_DIS_PNP_VID 0x07AF
#define CONFIG_BT_GATT_DIS_PNP_PID 0x707
#define CONFIG_BT_GATT_DIS_PNP_VER 0x0000
#endif

static struct dis_pnp dis_pnp_id = {
    .pnp_vid_src = DIS_PNP_VID_SRC,
    .pnp_vid     = CONFIG_BT_GATT_DIS_PNP_VID,
    .pnp_pid     = CONFIG_BT_GATT_DIS_PNP_PID,
    .pnp_ver     = CONFIG_BT_GATT_DIS_PNP_VER,
};
#endif

#if defined(CONFIG_BT_GATT_DIS_SETTINGS)
static u8_t dis_model[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_MODEL;
static u8_t dis_manuf[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_MANUF;
#if defined(CONFIG_BT_GATT_DIS_SERIAL_NUMBER)
static u8_t dis_serial_number[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_SERIAL_NUMBER_STR;
#endif
#if defined(CONFIG_BT_GATT_DIS_FW_REV)
static u8_t dis_fw_rev[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_FW_REV_STR;
#endif
#if defined(CONFIG_BT_GATT_DIS_HW_REV)
static u8_t dis_hw_rev[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_HW_REV_STR;
#endif
#if defined(CONFIG_BT_GATT_DIS_SW_REV)
static u8_t dis_sw_rev[CONFIG_BT_GATT_DIS_STR_MAX] = CONFIG_BT_GATT_DIS_SW_REV_STR;
#endif

#define BT_GATT_DIS_MODEL_REF             dis_model
#define BT_GATT_DIS_MANUF_REF             dis_manuf
#define BT_GATT_DIS_SERIAL_NUMBER_STR_REF dis_serial_number
#define BT_GATT_DIS_FW_REV_STR_REF        dis_fw_rev
#define BT_GATT_DIS_HW_REV_STR_REF        dis_hw_rev
#define BT_GATT_DIS_SW_REV_STR_REF        dis_sw_rev

#else /* CONFIG_BT_GATT_DIS_SETTINGS */

#define BT_GATT_DIS_MODEL_REF             CONFIG_BT_GATT_DIS_MODEL
#define BT_GATT_DIS_MANUF_REF             CONFIG_BT_GATT_DIS_MANUF
#define BT_GATT_DIS_SERIAL_NUMBER_STR_REF CONFIG_BT_GATT_DIS_SERIAL_NUMBER_STR
#define BT_GATT_DIS_FW_REV_STR_REF        CONFIG_BT_GATT_DIS_FW_REV_STR
#define BT_GATT_DIS_HW_REV_STR_REF        CONFIG_BT_GATT_DIS_HW_REV_STR
#define BT_GATT_DIS_SW_REV_STR_REF        CONFIG_BT_GATT_DIS_SW_REV_STR

#endif /* CONFIG_BT_GATT_DIS_SETTINGS */

static ssize_t read_str(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  return bt_gatt_attr_read(conn, attr, buf, len, offset, attr->user_data, strlen(attr->user_data));
}

#if CONFIG_BT_GATT_DIS_PNP
static ssize_t read_pnp_id(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  return bt_gatt_attr_read(conn, attr, buf, len, offset, &dis_pnp_id, sizeof(dis_pnp_id));
}
#endif

/* Device Information Service Declaration */
static struct bt_gatt_attr attrs[] = {

    BT_GATT_PRIMARY_SERVICE(BT_UUID_DIS),

    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_MODEL_NUMBER, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_MODEL_REF),
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_MANUFACTURER_NAME, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_MANUF_REF),
#if CONFIG_BT_GATT_DIS_PNP
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_PNP_ID, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_pnp_id, NULL, &dis_pnp_id),
#endif

#if defined(CONFIG_BT_GATT_DIS_SERIAL_NUMBER)
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_SERIAL_NUMBER, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_SERIAL_NUMBER_STR_REF),
#endif
#if defined(CONFIG_BT_GATT_DIS_FW_REV)
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_FIRMWARE_REVISION, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_FW_REV_STR_REF),
#endif
#if defined(CONFIG_BT_GATT_DIS_HW_REV)
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_HARDWARE_REVISION, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_HW_REV_STR_REF),
#endif
#if defined(CONFIG_BT_GATT_DIS_SW_REV)
    BT_GATT_CHARACTERISTIC(BT_UUID_DIS_SOFTWARE_REVISION, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_str, NULL, BT_GATT_DIS_SW_REV_STR_REF),
#endif

};

static struct bt_gatt_service dis_svc = BT_GATT_SERVICE(attrs);

void dis_init(u8_t vid_src, u16_t vid, u16_t pid, u16_t pid_ver) {
  dis_pnp_id.pnp_vid_src = vid_src;
  dis_pnp_id.pnp_vid     = vid;
  dis_pnp_id.pnp_pid     = pid;
  dis_pnp_id.pnp_ver     = pid_ver;
  bt_gatt_service_register(&dis_svc);
}

#if defined(CONFIG_BT_SETTINGS) && defined(CONFIG_BT_GATT_DIS_SETTINGS)
static int dis_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *store) {
  int         len, nlen;
  const char *next;

  nlen = settings_name_next(name, &next);
  if (!strncmp(name, "manuf", nlen)) {
    len = read_cb(store, &dis_manuf, sizeof(dis_manuf) - 1);
    if (len < 0) {
      BT_ERR("Failed to read manufacturer from storage"
             " (err %d)",
             len);
    } else {
      dis_manuf[len] = '\0';

      BT_DBG("Manufacturer set to %s", dis_manuf);
    }
    return 0;
  }
  if (!strncmp(name, "model", nlen)) {
    len = read_cb(store, &dis_model, sizeof(dis_model) - 1);
    if (len < 0) {
      BT_ERR("Failed to read model from storage"
             " (err %d)",
             len);
    } else {
      dis_model[len] = '\0';

      BT_DBG("Model set to %s", dis_model);
    }
    return 0;
  }
#if defined(CONFIG_BT_GATT_DIS_SERIAL_NUMBER)
  if (!strncmp(name, "serial", nlen)) {
    len = read_cb(store, &dis_serial_number, sizeof(dis_serial_number) - 1);
    if (len < 0) {
      BT_ERR("Failed to read serial number from storage"
             " (err %d)",
             len);
    } else {
      dis_serial_number[len] = '\0';

      BT_DBG("Serial number set to %s", dis_serial_number);
    }
    return 0;
  }
#endif
#if defined(CONFIG_BT_GATT_DIS_FW_REV)
  if (!strncmp(name, "fw", nlen)) {
    len = read_cb(store, &dis_fw_rev, sizeof(dis_fw_rev) - 1);
    if (len < 0) {
      BT_ERR("Failed to read firmware revision from storage"
             " (err %d)",
             len);
    } else {
      dis_fw_rev[len] = '\0';

      BT_DBG("Firmware revision set to %s", dis_fw_rev);
    }
    return 0;
  }
#endif
#if defined(CONFIG_BT_GATT_DIS_HW_REV)
  if (!strncmp(name, "hw", nlen)) {
    len = read_cb(store, &dis_hw_rev, sizeof(dis_hw_rev) - 1);
    if (len < 0) {
      BT_ERR("Failed to read hardware revision from storage"
             " (err %d)",
             len);
    } else {
      dis_hw_rev[len] = '\0';

      BT_DBG("Hardware revision set to %s", dis_hw_rev);
    }
    return 0;
  }
#endif
#if defined(CONFIG_BT_GATT_DIS_SW_REV)
  if (!strncmp(name, "sw", nlen)) {
    len = read_cb(store, &dis_sw_rev, sizeof(dis_sw_rev) - 1);
    if (len < 0) {
      BT_ERR("Failed to read software revision from storage"
             " (err %d)",
             len);
    } else {
      dis_sw_rev[len] = '\0';

      BT_DBG("Software revision set to %s", dis_sw_rev);
    }
    return 0;
  }
#endif
  return 0;
}

SETTINGS_STATIC_HANDLER_DEFINE(bt_dis, "bt/dis", NULL, dis_set, NULL, NULL);
#endif /* CONFIG_BT_GATT_DIS_SETTINGS && CONFIG_BT_SETTINGS*/


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/dis.h
================================================
/** @file
 *  @brief GATT Device Information Service
 */

/*
 * Copyright (c) 2018 Nordic Semiconductor ASA
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _DIS_H_
#define _DIS_H_

#ifdef __cplusplus
extern "C" {
#endif

#define AR_VENDOR_ID  0x0001
#define AR_PRODUCT_ID 0x0002

enum {
    DIS_PNP_VID_SRC = 0x01,
    USB_IMPL_VID
};
void dis_init(u8_t vid_src, u16_t vid, u16_t pid, u16_t pnp_ver);
#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/hog.c
================================================
/** @file
 *  @brief HoG Service sample
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include 

#include 
#include 
#include 
#include 
#include 

#include "log.h"
#include 
#include 
#include 
#include 

#include "hog.h"

enum {
  HIDS_REMOTE_WAKE          = BIT(0),
  HIDS_NORMALLY_CONNECTABLE = BIT(1),
};

struct hids_info {
  uint16_t version; /* version number of base USB HID Specification */
  uint8_t  code;    /* country HID Device hardware is localized for. */
  uint8_t  flags;
} __packed;

struct hids_report {
  uint8_t id;   /* report id */
  uint8_t type; /* report type */
} __packed;

static struct hids_info info = {
    .version = 0x0000,
    .code    = 0x00,
    .flags   = HIDS_NORMALLY_CONNECTABLE,
};

enum {
  HIDS_INPUT   = 0x01,
  HIDS_OUTPUT  = 0x02,
  HIDS_FEATURE = 0x03,
};

static struct hids_report input = {
    .id   = 0x01,
    .type = HIDS_INPUT,
};

static uint8_t simulate_input;
static uint8_t ctrl_point;
static uint8_t report_map[] = {
    0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */
    0x09, 0x02, /* Usage (Mouse) */
    0xA1, 0x01, /* Collection (Application) */
    0x09, 0x01, /*   Usage (Pointer) */
    0xA1, 0x00, /*   Collection (Physical) */
    0x05, 0x09, /*     Usage Page (Button) */
    0x19, 0x01, /*     Usage Minimum (0x01) */
    0x29, 0x03, /*     Usage Maximum (0x03) */
    0x15, 0x00, /*     Logical Minimum (0) */
    0x25, 0x01, /*     Logical Maximum (1) */
    0x95, 0x03, /*     Report Count (3) */
    0x75, 0x01, /*     Report Size (1) */
    0x81, 0x02, /*     Input (Data,Var,Abs,No Wrap,Linear,...) */
    0x95, 0x01, /*     Report Count (1) */
    0x75, 0x05, /*     Report Size (5) */
    0x81, 0x03, /*     Input (Const,Var,Abs,No Wrap,Linear,...) */
    0x05, 0x01, /*     Usage Page (Generic Desktop Ctrls) */
    0x09, 0x30, /*     Usage (X) */
    0x09, 0x31, /*     Usage (Y) */
    0x15, 0x81, /*     Logical Minimum (129) */
    0x25, 0x7F, /*     Logical Maximum (127) */
    0x75, 0x08, /*     Report Size (8) */
    0x95, 0x02, /*     Report Count (2) */
    0x81, 0x06, /*     Input (Data,Var,Rel,No Wrap,Linear,...) */
    0xC0,       /*   End Collection */
    0xC0,       /* End Collection */
};

static ssize_t read_info(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) {
  return bt_gatt_attr_read(conn, attr, buf, len, offset, attr->user_data, sizeof(struct hids_info));
}

static ssize_t read_report_map(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) {
  return bt_gatt_attr_read(conn, attr, buf, len, offset, report_map, sizeof(report_map));
}

static ssize_t read_report(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) {
  return bt_gatt_attr_read(conn, attr, buf, len, offset, attr->user_data, sizeof(struct hids_report));
}

static void input_ccc_changed(const struct bt_gatt_attr *attr, uint16_t value) {
  simulate_input = (value == BT_GATT_CCC_NOTIFY) ? 1 : 0;
  BT_WARN("simulate_input = [%d]\r\n", simulate_input);
}

static ssize_t read_input_report(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) { return bt_gatt_attr_read(conn, attr, buf, len, offset, NULL, 0); }

static ssize_t write_ctrl_point(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, uint16_t len, uint16_t offset, uint8_t flags) {
  uint8_t *value = attr->user_data;

  if (offset + len > sizeof(ctrl_point)) {
    return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
  }

  memcpy(value + offset, buf, len);

  return len;
}

/* HID Service Declaration */
static struct bt_gatt_attr attrs[] = {
    BT_GATT_PRIMARY_SERVICE(BT_UUID_HIDS),
    BT_GATT_CHARACTERISTIC(BT_UUID_HIDS_INFO, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_info, NULL, &info),
    BT_GATT_CHARACTERISTIC(BT_UUID_HIDS_REPORT_MAP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, read_report_map, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_HIDS_REPORT, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, BT_GATT_PERM_READ_AUTHEN, read_input_report, NULL, NULL),
    BT_GATT_CCC(input_ccc_changed, BT_GATT_PERM_READ_AUTHEN | BT_GATT_PERM_WRITE_AUTHEN),
    BT_GATT_DESCRIPTOR(BT_UUID_HIDS_REPORT_REF, BT_GATT_PERM_READ, read_report, NULL, &input),
    BT_GATT_CHARACTERISTIC(BT_UUID_HIDS_CTRL_POINT, BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_WRITE, NULL, write_ctrl_point, &ctrl_point),
};

struct hids_remote_key {
  u8_t  hid_page;
  u16_t hid_usage;
} __packed;

static struct hids_remote_key remote_kbd_map_tab[] = {
    {HID_PAGE_KBD, Key_a_or_A2},
    {HID_PAGE_KBD,  Key_b_or_B},
    {HID_PAGE_KBD,  Key_c_or_C},
};

int hog_notify(struct bt_conn *conn, uint16_t hid_usage, uint8_t press) {
  struct bt_gatt_attr    *attr;
  struct hids_remote_key *remote_key = NULL;
  u8_t                    len        = 4, data[4];

  for (int i = 0; i < (sizeof(remote_kbd_map_tab) / sizeof(remote_kbd_map_tab[0])); i++) {
    if (remote_kbd_map_tab[i].hid_usage == hid_usage) {
      remote_key = &remote_kbd_map_tab[i];
      break;
    }
  }

  if (!remote_key)
    return EINVAL;

  if (remote_key->hid_page == HID_PAGE_KBD) {
    attr = &attrs[BT_CHAR_BLE_HID_REPORT_ATTR_VAL_INDEX];
    len  = 3;
  } else
    return EINVAL;

  sys_put_le16(hid_usage, data);
  data[2] = 0;
  data[3] = 0;

  if (!press) {
    memset(data, 0, len);
  }

  return bt_gatt_notify(conn, attr, data, len);
}

struct bt_gatt_service hog_srv = BT_GATT_SERVICE(attrs);

void hog_init(void) { bt_gatt_service_register(&hog_srv); }


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/hog.h
================================================
/** @file
 *  @brief HoG Service sample
 */

/*
 * Copyright (c) 2016 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef _HOG_H_
#define _HOG_H_
#ifdef __cplusplus
extern "C" {
#endif

#include 
#define HID_PAGE_KBD  0x07
#define HID_PAGE_CONS 0x0C

#define BT_CHAR_BLE_HID_INFO_ATTR_VAL_INDEX       (2)
#define BT_CHAR_BLE_HID_REPORT_MAP_ATTR_VAL_INDEX (4)
#define BT_CHAR_BLE_HID_REPORT_ATTR_VAL_INDEX     (6)
#define BT_CHAR_BLE_HID_CTRL_POINT_ATTR_VAL_INDEX (10)

enum hid_usage {
    Key_a_or_A2 = 0x0004,
    Key_b_or_B,
    Key_c_or_C
};

void hog_init(void);
int hog_notify(struct bt_conn *conn, uint16_t hid_usage, uint8_t press);

#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/oad/oad.h
================================================
#ifndef __OAD_H__
#define __OAD_H__

#include "types.h"
#include "hci_host.h"
#include "work_q.h"

#define LOCAL_MANU_CODE 0x2c00
#define LOCAL_FILE_VER  00000001

#define OAD_OPCODE_SIZE 1
//00070000-0745-4650-8d93-df59be2fc10a
#define BT_UUID_OAD BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x00070000, 0x0745, 0x4650, 0x8d93, 0xdf59be2fc10a))
//00070001-0745-4650-8d93-df59be2fc10a
#define BT_UUID_OAD_DATA_IN BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x00070001, 0x0745, 0x4650, 0x8d93, 0xdf59be2fc10a))
//00070002-0745-4650-8d93-df59be2fc10a
#define BT_UUID_OAD_DATA_OUT BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x00070002, 0x0745, 0x4650, 0x8d93, 0xdf59be2fc10a))

enum {
    OAD_SUCC = 0x00,
    OAD_ABORT,
    OAD_INVALID_IMAG,
    OAD_REQ_MORE_DATA,
    OAD_MALORMED_CMD,
    OAD_UPGRD_CMPLT,
    OAD_CHECK_HASH256_FAIL,
};

enum {
    OAD_CMD_IMAG_IDENTITY = 0x00,
    OAD_CMD_IMAG_BLOCK_REQ,
    OAD_CMD_IMAG_BLOCK_RESP,
    OAD_CMD_IMAG_UPGRD_END,
    OAD_CMD_IMAG_INFO,
};

struct oad_file_info {
    u16_t manu_code;
    u32_t file_ver;
} __packed;

#if defined(CONFIG_BT_SETTINGS)
struct oad_ef_info {
    struct oad_file_info file_info;
    u32_t file_offset;
    u32_t last_wflash_addr;
    u32_t upgrd_crc32;
} __packed;

#endif

struct oad_env_tag {
    struct oad_file_info file_info;
    u32_t cur_file_size;
    u32_t upgrd_file_ver;
    u32_t upgrd_file_size;
    u32_t upgrd_offset;
    u32_t upgrd_crc32;

    struct k_delayed_work upgrd_work;
    u32_t new_img_addr;
    u32_t w_img_end_addr;

    u32_t hosal_offset;
};

struct oad_image_identity_t {
    struct oad_file_info file_info;
    u32_t file_size;
    u32_t crc32;
} __packed;

struct oad_block_req_t {
    struct oad_file_info file_info;
    u32_t file_offset;
} __packed;

#define OAD_BLK_RSP_DATA_OFFSET 12
struct oad_block_rsp_t {
    uint8_t status;
    struct oad_file_info file_info;
    u32_t file_offset;
    u8_t data_size;
    u8_t *pdata;
} __packed;

struct oad_upgrd_end_t {
    u8_t status;
    struct oad_file_info file_info;
} __packed;

#endif //__OAD_H__


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/oad/oad_client.h
================================================
#ifndef __BLE_OAD_H__
#define __BLE_OAD_H__
#include "gatt.h"
#include "Conn_internal.h"
#include "oad.h"

enum {
    OAD_CMDPROC_START = 0x00,
    OAD_CMDPROC_IMAGE_IDENTITY,
    OAD_CMDPROC_BLOCK_REQ,
    OAD_CMDPROC_BLOCK_RESP,
    OAD_CMDPROC_UPGRD_END,
};

struct oad_cmdproc_block_req_t {
    struct oad_file_info file_info;
    uint32_t file_offset;
    uint8_t data_len;
} __packed;

struct oad_cmdproc_upgrd_end_t {
    uint8_t status;
    struct oad_file_info file_info;
} __packed;

struct oad_cmdproc_req_t {
    uint8_t cmd_id;
    union {
        struct oad_file_info file_info;
        struct oad_cmdproc_block_req_t block_req;
        struct oad_cmdproc_upgrd_end_t upgrd_end;
    } q;
} __packed;

enum {
    CMDPROC_TYPE_OAD = 0x00,
    CMDPROC_TYPE_MAX
};

void oad_client_notify_handler(void *buf, u16_t len);
void oad_send_image_identity_to_servicer(struct bt_conn *conn, u8_t *data, u16_t len);
void oad_send_block_resp_to_servicer(struct bt_conn *conn, u8_t *data, u8_t len);
void oad_cli_register(void);

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/oad/oad_main.h
================================================
#ifndef __OAD_API_H__
#define __OAD_API_H__

#include 

typedef bool (*app_check_oad_cb)(u32_t cur_file_ver, u32_t new_file_ver);
void oad_service_enable(app_check_oad_cb cb);
void ota_finish(struct k_work *work);
#endif //__OAD_API_H__

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/oad/oad_service.h
================================================
#ifndef __OAD_SERVICE_H__
#define __OAD_SERVICE_H__

#include "types.h"
#include "gatt.h"

typedef void (*oad_upper_recv_cb)(struct bt_conn *conn, const u8_t *data, u16_t len);
typedef void (*oad_disc_cb)(struct bt_conn *conn, u8_t reason);
void bt_oad_register_recv_cb(oad_upper_recv_cb cb);
void bt_oad_register_disc_cb(oad_disc_cb cb);
void bt_oad_service_enable(void);
void bt_oad_servkce_disable(void);
void bt_oad_notify(struct bt_conn *conn, const void *data, u16_t len);
#endif //__OAD_SERVICE_H__

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/scps.c
================================================
/**
 ****************************************************************************************
 *
 * @file Scps.c
 *
 * @brief Bouffalo Lab GATT Scan Parameters Service implementation
 *
 * Copyright (C) Bouffalo Lab 2019
 *
 * History: 2019-08 crealted by llgong @ Shanghai
 *
 ****************************************************************************************
 */
#include "scps.h"
#include "bluetooth.h"
#include "byteorder.h"
#include "gatt.h"
#include "uuid.h"

struct scan_intvl_win {
  u16_t scan_intvl;
  u16_t scan_win;
} __packed;

static struct scan_intvl_win intvl_win = {
    .scan_intvl = BT_GAP_SCAN_FAST_INTERVAL,
    .scan_win   = BT_GAP_SCAN_FAST_WINDOW,
};

static ssize_t scan_intvl_win_write(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags) {
  const u8_t *data     = buf;
  intvl_win.scan_intvl = sys_get_le16(data);
  data += 2;
  intvl_win.scan_win = sys_get_le16(data);

  return len;
}

static struct bt_gatt_attr attrs[] = {BT_GATT_PRIMARY_SERVICE(BT_UUID_SCPS),
                                      BT_GATT_CHARACTERISTIC(BT_UUID_SCPS_SCAN_INTVL_WIN, BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_NONE, NULL, NULL, &intvl_win)};

static struct bt_gatt_service scps = BT_GATT_SERVICE(attrs);

bool scps_init(u16_t scan_intvl, u16_t scan_win) {
  int err;

  if (scan_intvl < 0x0004 || scan_intvl > 0x4000) {
    return false;
  }

  if (scan_win < 0x0004 || scan_win > 0x4000) {
    return false;
  }

  if (scan_win > scan_intvl) {
    return false;
  }

  intvl_win.scan_intvl = scan_intvl;
  intvl_win.scan_win   = scan_win;

  err = bt_gatt_service_register(&scps);

  return err ? false : true;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/ble_stack/services/scps.h
================================================
#ifndef INCLUDE_BLUETOOTH_SERVICES_SCPS_H_
#define INCLUDE_BLUETOOTH_SERVICES_SCPS_H_

/**
 * @brief Scan Parameters Service (SCPS)
 * @defgroup bt_gatt_scps Scan Parameters Service (SCPS)
 * @ingroup bluetooth
 * @{
 *
 * [Experimental] Users should note that the APIs can change
 * as a part of ongoing development.
 */

#ifdef __cplusplus
extern "C" {
#endif

#include 
#include 
bool scps_init(u16_t scan_itvl, u16_t scan_win);

#ifdef __cplusplus
}
#endif

/**
 * @}
 */

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/blecontroller/ble_inc/ble_lib_api.h
================================================
#ifndef BLE_LIB_API_H_
#define BLE_LIB_API_H_

#include 
#include 

void ble_controller_init(uint8_t task_priority);
void ble_controller_deinit(void);
#if !defined(CFG_FREERTOS) && !defined(CFG_AOS)
void blecontroller_main(void);
#endif
#if defined(CFG_BT_RESET)
void ble_controller_reset(void);
#endif
char *ble_controller_get_lib_ver(void);

// if 0, success.
// if -1, fail,
int8_t ble_controller_set_scan_filter_table_size(uint8_t size);

// return sleep duration, in unit of 1/32768s
// if 0, means not allow sleep
// if -1, means allow sleep, but there is no end of sleep interrupt (ble core deep sleep is not enabled)
int32_t ble_controller_sleep(void);
void    ble_controller_sleep_restore(void);
bool    ble_controller_sleep_is_ongoing(void);

void ble_controller_set_tx_pwr(int ble_tx_power);
void ble_rf_set_tx_channel(uint16_t tx_channel);

#if defined(CONFIG_BLE_MFG)
enum { BLE_TEST_TX = 0x00, BLE_TEST_RX, BLE_TEST_RXTX, BLE_TEST_END };

/// HCI LE Receiver Test Command parameters structure
struct le_rx_test_cmd {
  /// RX frequency for Rx test
  uint8_t rx_freq;
};

/// HCI LE Transmitter Test Command parameters structure
struct le_tx_test_cmd {
  /// TX frequency for Tx test
  uint8_t tx_freq;
  /// TX test data length
  uint8_t test_data_len;
  /// TX test payload type - see enum
  uint8_t pk_payload_type;
};

struct le_enhanced_rx_test_cmd {
  /// RX frequency for Rx test
  uint8_t rx_freq;
  /// RX PHY for Rx test
  uint8_t rx_phy;
  /// Modulation index: Assume transmitter will have a standard or stable modulation index
  uint8_t modulation_index;
};

/// HCI LE Enhanced Transmitter Test Command parameters structure
struct le_enhanced_tx_test_cmd {
  /// TX frequency for Tx test
  uint8_t tx_freq;
  /// TX test data length
  uint8_t test_data_len;
  /// TX test payload type - see enum
  uint8_t pk_payload_type;
  /// TX PHY for Rx test
  uint8_t tx_phy;
};

int     le_rx_test_cmd_handler(uint16_t src_id, void *param, bool from_hci);
int     le_tx_test_cmd_handler(uint16_t src_id, void *param, bool from_hci);
int     le_test_end_cmd_handler(bool from_hci);
uint8_t le_get_direct_test_type(void);
void    le_test_mode_custom_aa(uint32_t access_code);

#if defined(CONFIG_BLE_MFG_HCI_CMD)
int reset_cmd_handler(void);
#endif
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/blecontroller/ble_inc/hci_onchip.h
================================================
#ifndef HCI_ONCHIP_H_
#define HCI_ONCHIP_H_

enum {
    BT_HCI_CMD,
    BT_HCI_ACL_DATA,
    BT_HCI_CMD_CMP_EVT,
    BT_HCI_CMD_STAT_EVT,
    BT_HCI_LE_EVT,
    BT_HCI_EVT
};

typedef struct {
    uint16_t opcode;
    uint8_t *params;
    uint8_t param_len;
} bl_hci_cmd_struct;

typedef struct {
    /// connection handle
    uint16_t conhdl;
    /// broadcast and packet boundary flag
    uint8_t pb_bc_flag;
    /// length of the data
    uint16_t len;
    uint8_t *buffer;
} bl_hci_acl_data_tx;

typedef struct {
    union {
        bl_hci_cmd_struct hci_cmd;
        bl_hci_acl_data_tx acl_data;
    } p;
} hci_pkt_struct;

typedef void (*bt_hci_recv_cb)(uint8_t pkt_type, uint16_t src_id, uint8_t *param, uint8_t param_len);

uint8_t bt_onchiphci_interface_init(bt_hci_recv_cb cb);
int8_t bt_onchiphci_send(uint8_t pkt_type, uint16_t dest_id, hci_pkt_struct *pkt);
uint8_t bt_onchiphci_hanlde_rx_acl(void *param, uint8_t *host_buf_data);

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/ble/blecontroller/lib/README.md
================================================
# blecontroller lib information

## BL702

1. `libblecontroller_702_m0s0sp` BL702 support BLE scan feature and BLE PDS(power down sleep) feature.
1. `libblecontroller_702_m0s1` 1 BLE connection is supported, BL702 can only be slave in this connection.
1. `libblecontroller_702_m0s1p` Based on libblecontroller_702_m0s1, add BLE PDS(power down sleep) feature.
1. `libblecontroller_702_m0s1s` Based on libblecontroller_702_m0s1, add BLE scan feature.
1. `libblecontroller_702_m1s1` 1 BLE connection is supported, BL702 can be master or slave in this connection.
1. `libblecontroller_702_m16s1` 16 BLE connections are suppprted, BL702 can be master or slave in each connection.


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/freertos_risc_v_chip_specific_extensions.h
================================================
/*
 * FreeRTOS Kernel V10.2.1
 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

/*
 * The FreeRTOS kernel's RISC-V port is split between the the code that is
 * common across all currently supported RISC-V chips (implementations of the
 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
 *
 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
 *   is common to all currently supported RISC-V chips.  There is only one
 *   portASM.S file because the same file is built for all RISC-V target chips.
 *
 * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
 *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
 *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
 *   as there are multiple RISC-V chip implementations.
 *
 * !!!NOTE!!!
 * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
 * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
 * compiler's!) include path.  For example, if the chip in use includes a core
 * local interrupter (CLINT) and does not include any chip specific register
 * extensions then add the path below to the assembler's include path:
 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
 *
 */

#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
#define __FREERTOS_RISC_V_EXTENSIONS_H__

#define portasmHAS_CLINT               1
#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */

.macro portasmSAVE_ADDITIONAL_REGISTERS
    /* No additional registers to save, so this macro does nothing. */
    .endm

    /* Restore the additional registers found on the Pulpino. */
    .macro portasmRESTORE_ADDITIONAL_REGISTERS
    /* No additional registers to restore, so this macro does nothing. */
    .endm

#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/port.c
================================================
/*
 * FreeRTOS Kernel V10.2.1
 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

/*-----------------------------------------------------------
 * Implementation of functions defined in portable.h for the RISC-V RV32 port.
 *----------------------------------------------------------*/

/* Scheduler includes. */
#include "FreeRTOS.h"
#include "portmacro.h"
#include "task.h"

#ifndef configCLINT_BASE_ADDRESS
#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.
#endif

/* Let the user override the pre-loading of the initial LR with the address of
prvTaskExitError() in case it messes up unwinding of the stack in the
debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif

/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
to use a statically allocated array as the interrupt stack.  Alternative leave
configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
linker variable names __freertos_irq_stack_top has the same value as the top
of the stack used by main.  Using the linker script method will repurpose the
stack that was used by main before the scheduler was started for use as the
interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS
static __attribute__((aligned(16))) StackType_t xISRStack[configISR_STACK_SIZE_WORDS] = {0};
const StackType_t                               xISRStackTop                          = (StackType_t) & (xISRStack[configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK]);
#else
extern const uint32_t __freertos_irq_stack_top[];
const StackType_t     xISRStackTop = (StackType_t)__freertos_irq_stack_top;
#endif

/*
 * Setup the timer to generate the tick interrupts.  The implementation in this
 * file is weak to allow application writers to change the timer used to
 * generate the tick interrupt.
 */
void vPortSetupTimerInterrupt(void) __attribute__((weak));

/*-----------------------------------------------------------*/

/* Used to program the machine timer compare register. */
uint64_t                 ullNextTime                         = 0ULL;
const uint64_t          *pullNextTime                        = &ullNextTime;
const size_t             uxTimerIncrementsForOneTick         = (size_t)(configCPU_CLOCK_HZ / configTICK_RATE_HZ); /* Assumes increment won't go over 32-bits. */
volatile uint64_t *const pullMachineTimerCompareRegisterBase = (volatile uint64_t *const)(configCLINT_BASE_ADDRESS + 0x4000);
volatile uint64_t       *pullMachineTimerCompareRegister     = 0;
BaseType_t               TrapNetCounter                      = 0;
const BaseType_t        *pTrapNetCounter                     = &TrapNetCounter;

/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
stack checking.  A problem in the ISR stack will trigger an assert, not call the
stack overflow hook function (because the stack overflow hook is specific to a
task stack, not the ISR stack). */
#if (configCHECK_FOR_STACK_OVERFLOW > 2)
#warning This path not tested, or even compiled yet.
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
the task stacks, and so will legitimately appear in many positions within
the ISR stack. */
#define portISR_STACK_FILL_BYTE 0xee

static const uint8_t ucExpectedStackBytes[] = {portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
                                               portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
                                               portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,
                                               portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE};

#define portCHECK_ISR_STACK() configASSERT((memcmp((void *)xISRStack, (void *)ucExpectedStackBytes, sizeof(ucExpectedStackBytes)) == 0))
#else
/* Define the function away. */
#define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */

/*-----------------------------------------------------------*/

#if (configCLINT_BASE_ADDRESS != 0)

void vPortSetupTimerInterrupt(void) {
  uint32_t                 ulCurrentTimeHigh, ulCurrentTimeLow;
  volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(configCLINT_BASE_ADDRESS + 0xBFFC);
  volatile uint32_t *const pulTimeLow  = (volatile uint32_t *const)(configCLINT_BASE_ADDRESS + 0xBFF8);
  volatile uint32_t        ulHartId    = 0;

  __asm volatile("csrr %0, mhartid" : "=r"(ulHartId));
  pullMachineTimerCompareRegister = &(pullMachineTimerCompareRegisterBase[ulHartId]);

  do {
    ulCurrentTimeHigh = *pulTimeHigh;
    ulCurrentTimeLow  = *pulTimeLow;
  } while (ulCurrentTimeHigh != *pulTimeHigh);

  ullNextTime = (uint64_t)ulCurrentTimeHigh;
  ullNextTime <<= 32ULL;
  ullNextTime |= (uint64_t)ulCurrentTimeLow;
  ullNextTime += (uint64_t)uxTimerIncrementsForOneTick;
  *pullMachineTimerCompareRegister = ullNextTime;

  /* Prepare the time to use after the next tick interrupt. */
  ullNextTime += (uint64_t)uxTimerIncrementsForOneTick;
}

#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
/*-----------------------------------------------------------*/

BaseType_t xPortStartScheduler(void) {
  extern void xPortStartFirstTask(void);

#if (configASSERT_DEFINED == 1)
  {
    volatile uint32_t mtvec = 0;

    /* Check the least significant two bits of mtvec are 00 - indicating
    single vector mode. */
    __asm volatile("csrr %0, mtvec" : "=r"(mtvec));
    // configASSERT( ( mtvec & 0x03UL ) == 0 );

    /* Check alignment of the interrupt stack - which is the same as the
    stack that was being used by main() prior to the scheduler being
    started. */
    configASSERT((xISRStackTop & portBYTE_ALIGNMENT_MASK) == 0);
  }
#endif /* configASSERT_DEFINED */

  /* If there is a CLINT then it is ok to use the default implementation
  in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
  configure whichever clock is to be used to generate the tick interrupt. */
  vPortSetupTimerInterrupt();

#if (configCLINT_BASE_ADDRESS != 0)
  {
    /* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
    for external interrupt.  _RB_ What happens here when mtime is not present as
    with pulpino? */
    __asm volatile("csrs mie, %0" ::"r"(0x880));
  }
#else
  {
    /* Enable external interrupts. */
    __asm volatile("csrs mie, %0" ::"r"(0x800));
  }
#endif /* configCLINT_BASE_ADDRESS */

  *(uint8_t *)(0x02800400 + 7) = 1;
  xPortStartFirstTask();

  /* Should not get here as after calling xPortStartFirstTask() only tasks
  should be executing. */
  return pdFAIL;
}
/*-----------------------------------------------------------*/

void vPortEndScheduler(void) {
  /* Not implemented. */
  for (;;)
    ;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portASM.S
================================================
/*
 * FreeRTOS Kernel V10.2.1
 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

/*
 * The FreeRTOS kernel's RISC-V port is split between the the code that is
 * common across all currently supported RISC-V chips (implementations of the
 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
 *
 * + The code that is common to all RISC-V chips is implemented in
 *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
 *   portASM.S file because the same file is used no matter which RISC-V chip is
 *   in use.
 *
 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
 *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
 *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
 *   RISC-V chip that both includes a standard CLINT and does not add to the
 *   base set of RISC-V registers.  There are additional
 *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
 *   that do not include a standard CLINT or do add to the base set of RISC-V
 *   registers.
 *
 * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
 * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
 * header file ensure the path to the correct header file is in the assembler's
 * include path.
 *
 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
 * that include a standard CLINT and do not add to the base set of RISC-V
 * registers.
 *
 */
#if __riscv_xlen == 64
	#define portWORD_SIZE 8
	#define store_x sd
	#define load_x ld
#elif __riscv_xlen == 32
	#define store_x sw
	#define load_x lw
	#define portWORD_SIZE 4
#else
	#error Assembler did not define __riscv_xlen
#endif

#include "freertos_risc_v_chip_specific_extensions.h"

/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
#ifndef portasmHAS_CLINT
	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
#endif

#ifndef portasmHANDLE_INTERRUPT
	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
#endif

/* Only the standard core registers are stored by default.  Any additional
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
at the top of this file. */
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )

.global xPortStartFirstTask
.global freertos_risc_v_trap_handler
.global pxPortInitialiseStack
.extern pxCurrentTCB
.extern ulPortTrapHandler
.extern vTaskSwitchContext
.extern xTaskIncrementTick
.extern Timer_IRQHandler
.extern pullMachineTimerCompareRegister
.extern pullNextTime
 .extern pTrapNetCounter
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
.extern xISRStackTop
.extern portasmHANDLE_INTERRUPT
.extern Trap_Handler

/*-----------------------------------------------------------*/

.align 8
.func
freertos_risc_v_trap_handler:
	addi sp, sp, -portCONTEXT_SIZE
	store_x x1, 1 * portWORD_SIZE( sp )
	store_x x5, 2 * portWORD_SIZE( sp )
	store_x x6, 3 * portWORD_SIZE( sp )
	store_x x7, 4 * portWORD_SIZE( sp )
	store_x x8, 5 * portWORD_SIZE( sp )
	store_x x9, 6 * portWORD_SIZE( sp )
	store_x x10, 7 * portWORD_SIZE( sp )
	store_x x11, 8 * portWORD_SIZE( sp )
	store_x x12, 9 * portWORD_SIZE( sp )
	store_x x13, 10 * portWORD_SIZE( sp )
	store_x x14, 11 * portWORD_SIZE( sp )
	store_x x15, 12 * portWORD_SIZE( sp )
	store_x x16, 13 * portWORD_SIZE( sp )
	store_x x17, 14 * portWORD_SIZE( sp )
	store_x x18, 15 * portWORD_SIZE( sp )
	store_x x19, 16 * portWORD_SIZE( sp )
	store_x x20, 17 * portWORD_SIZE( sp )
	store_x x21, 18 * portWORD_SIZE( sp )
	store_x x22, 19 * portWORD_SIZE( sp )
	store_x x23, 20 * portWORD_SIZE( sp )
	store_x x24, 21 * portWORD_SIZE( sp )
	store_x x25, 22 * portWORD_SIZE( sp )
	store_x x26, 23 * portWORD_SIZE( sp )
	store_x x27, 24 * portWORD_SIZE( sp )
	store_x x28, 25 * portWORD_SIZE( sp )
	store_x x29, 26 * portWORD_SIZE( sp )
	store_x x30, 27 * portWORD_SIZE( sp )
	store_x x31, 28 * portWORD_SIZE( sp )

	csrr t0, mstatus					/* Required for MPIE bit. */
	store_x t0, 29 * portWORD_SIZE( sp )

	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */

         load_x  t0, pTrapNetCounter
         lw   t1, 0( t0 )
         addi   t1, t1, 1
         store_x t1, 0( t0 )

	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */

	csrr a0, mcause
	csrr a1, mepc

	li t0, 0x80000FFF
	and a0, a0, t0
test_if_asynchronous:
	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */

handle_asynchronous:

#if( portasmHAS_CLINT != 0 )

	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */

		addi t0, x0, 1

		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
		bne a0, t1, test_if_external_interrupt

		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */

		#if( __riscv_xlen == 32 )

			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
			li t4, -1
			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
			sw t4, 0(t0)				/* Low word no smaller than old value to start with - will be overwritten below. */
			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register.  No smaller than new value. */
			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
			sw t6, 4(t1)				/* Store new high word of ullNextTime. */

		#endif /* __riscv_xlen == 32 */

		#if( __riscv_xlen == 64 )

			/* Update the 64-bit mtimer compare match value. */
			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
			sd t4, 0(t1)				/* Store ullNextTime. */

		#endif /* __riscv_xlen == 64 */

		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
		jal xTaskIncrementTick
		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
		jal vTaskSwitchContext
		j processed_source

	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
		//addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
		//bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */

#endif /* portasmHAS_CLINT */

	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
	j processed_source

handle_synchronous:
	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
	store_x a1, 0( sp )					/* Save updated exception return address. */

test_if_environment_call:
	li t0, 11 							/* 11 == environment call. */
	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
	jal vTaskSwitchContext
	j processed_source

is_exception:
	csrr t0, mcause						/* For viewing in the debugger only. */
	csrr t1, mepc						/* For viewing in the debugger only */
	csrr t2, mstatus
	load_x sp, xISRStackTop
	jal Trap_Handler
	j is_exception

as_yet_unhandled:
	csrr t0, mcause						/* For viewing in the debugger only. */
	j as_yet_unhandled

processed_source:

         load_x  t0, pTrapNetCounter
         lw   t1, 0 ( t0 )
         addi   t1, t1, -1
         store_x t1, 0( t0 )
         
	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */

	/* Load mret with the address of the next instruction in the task to run next. */
	load_x t0, 0( sp )
	csrw mepc, t0

	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */

	/* Load mstatus with the interrupt enable bits used by the task. */
	load_x  t0, 29 * portWORD_SIZE( sp )
	csrw mstatus, t0						/* Required for MPIE bit. */

	load_x  x1, 1 * portWORD_SIZE( sp )
	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
	addi sp, sp, portCONTEXT_SIZE

	mret
	.endfunc
/*-----------------------------------------------------------*/

.align 8
.func
xPortStartFirstTask:

#if( portasmHAS_CLINT != 0 )
	/* If there is a clint then interrupts can branch directly to the FreeRTOS
	trap handler.  Otherwise the interrupt controller will need to be configured
	outside of this file. */
	la t0, freertos_risc_v_trap_handler
	ori t0, t0, 2
	csrw mtvec, t0
#endif /* portasmHAS_CLILNT */

	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */

	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */

	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */

	load_x  t0, 29 * portWORD_SIZE( sp )	/* mstatus */
	addi t0, t0, 0x08						/* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
	csrrw  x0, mstatus, t0					/* Interrupts enabled from here! */

	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
	addi	sp, sp, portCONTEXT_SIZE
	ret
	.endfunc
/*-----------------------------------------------------------*/

/*
 * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
 * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
 * for the function is as per the other ports:
 * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
 *
 * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
 * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
 *
 * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
 *
 * Register		ABI Name	Description						Saver
 * x0			zero		Hard-wired zero					-
 * x1			ra			Return address					Caller
 * x2			sp			Stack pointer					Callee
 * x3			gp			Global pointer					-
 * x4			tp			Thread pointer					-
 * x5-7			t0-2		Temporaries						Caller
 * x8			s0/fp		Saved register/Frame pointer	Callee
 * x9			s1			Saved register					Callee
 * x10-11		a0-1		Function Arguments/return values Caller
 * x12-17		a2-7		Function arguments				Caller
 * x18-27		s2-11		Saved registers					Callee
 * x28-31		t3-6		Temporaries						Caller
 *
 * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
 * where the global and thread pointers are currently assumed to be constant so
 * are not saved:
 *
 * mstatus
 * x31
 * x30
 * x29
 * x28
 * x27
 * x26
 * x25
 * x24
 * x23
 * x22
 * x21
 * x20
 * x19
 * x18
 * x17
 * x16
 * x15
 * x14
 * x13
 * x12
 * x11
 * pvParameters
 * x9
 * x8
 * x7
 * x6
 * x5
 * portTASK_RETURN_ADDRESS
 * [chip specific registers go here]
 * pxCode
 */
.align 8
.func
pxPortInitialiseStack:

	csrr t0, mstatus					/* Obtain current mstatus value. */

#if 1
    li   t1, 0x1880
    or   t0, t0, t1                     /* MPP = 0b11, MPIE = 1 */
    andi t0, t0, 0xFFFFFFF7             /* !!! MIE = 0 !!! */
#else
	addi t1, x0, 0x188					/* Generate the value 0x1888, which are the MIE, MPIE and privilege bits to set in mstatus. */
	slli t1, t1, 4
	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
#endif

	addi a0, a0, -portWORD_SIZE
	store_x t0, 0(a0)					/* mstatus onto the stack. */
	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
	beq t0, x0, 1f						/* No more chip specific registers to save. */
	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
	j chip_specific_stack_frame			/* Until no more chip specific registers. */
1:
	addi a0, a0, -portWORD_SIZE
	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
	ret
	.endfunc
/*-----------------------------------------------------------*/


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/gcc/risc-v/bl702/portmacro.h
================================================
/*
 * FreeRTOS Kernel V10.2.1
 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

#ifndef PORTMACRO_H
#define PORTMACRO_H

#ifdef __cplusplus
extern "C" {
#endif

/*-----------------------------------------------------------
 * Port specific definitions.
 *
 * The settings in this file configure FreeRTOS correctly for the
 * given hardware and compiler.
 *
 * These settings should not be altered.
 *-----------------------------------------------------------
 */
#include "FreeRTOSConfig.h"
#include 
#include 

/* Type definitions. */
#if __riscv_xlen == 64
#define portSTACK_TYPE        uint64_t
#define portBASE_TYPE         int64_t
#define portUBASE_TYPE        uint64_t
#define portMAX_DELAY         (TickType_t)0xffffffffffffffffUL
#define portPOINTER_SIZE_TYPE uint64_t
#elif __riscv_xlen == 32
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE  int /* int32_t */
#define portUBASE_TYPE uint32_t
#define portMAX_DELAY  (TickType_t)0xffffffffUL
#ifdef __riscv_float_abi_single
/* better to use float replace double here,
 * so that it will generates floating point instructions
 */
#define portDOUBLE float /* double */
#else
#define portDOUBLE double
#endif
#else
#error Assembler did not define __riscv_xlen
#endif

typedef portSTACK_TYPE StackType_t;
typedef portBASE_TYPE  BaseType_t;
typedef portUBASE_TYPE UBaseType_t;
typedef portUBASE_TYPE TickType_t;

/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/

/* Architecture specifics. */
#define portSTACK_GROWTH   (-1)
#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#ifdef __riscv64
#error This is the RV32 port that has not yet been adapted for 64.
#define portBYTE_ALIGNMENT 16
#else
#define portBYTE_ALIGNMENT 16
#endif
/*-----------------------------------------------------------*/

/* Scheduler utilities. */
extern BaseType_t TrapNetCounter;
extern void       vTaskSwitchContext(void);
#define portYIELD() __asm volatile("ecall");
#define portEND_SWITCHING_ISR(xSwitchRequired) \
  if (xSwitchRequired)                         \
  vTaskSwitchContext()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/

/* Critical section management. */
#define portCRITICAL_NESTING_IN_TCB 1
extern void vTaskEnterCritical(void);
extern void vTaskExitCritical(void);

#define portSET_INTERRUPT_MASK_FROM_ISR()                     0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedStatusValue) (void)uxSavedStatusValue
#define portDISABLE_INTERRUPTS()                              __asm volatile("csrc mstatus, 8")
#define portENABLE_INTERRUPTS()                               __asm volatile("csrs mstatus, 8")
#define portENTER_CRITICAL()                                  vTaskEnterCritical()
#define portEXIT_CRITICAL()                                   vTaskExitCritical()

/*-----------------------------------------------------------*/

/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif

#if (configUSE_PORT_OPTIMISED_TASK_SELECTION == 1)

/* Check the configuration. */
#if (configMAX_PRIORITIES > 32)
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif

/* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
#define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities)  (uxReadyPriorities) &= ~(1UL << (uxPriority))

/*-----------------------------------------------------------*/

#define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - __builtin_clz(uxReadyPriorities))

#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

/*-----------------------------------------------------------*/

/* Task function macros as described on the FreeRTOS.org WEB site.  These are
not necessary for to use this port.  They are defined so the common demo files
(which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)

/*-----------------------------------------------------------*/

#define portNOP() __asm volatile(" nop ")

#define portINLINE __inline

#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__((always_inline))
#endif

#define portMEMORY_BARRIER() __asm volatile("" ::: "memory")

portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) { return TrapNetCounter ? 1 : 0; }

#ifdef __cplusplus
}
#endif

#endif /* PORTMACRO_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/freertos/portable/readme.txt
================================================
Each real time kernel port consists of three files that contain the core kernel
components and are common to every port, and one or more files that are
specific to a particular microcontroller and/or compiler.


+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
memory allocators as described on the http://www.FreeRTOS.org WEB site.

+ The other directories each contain files specific to a particular
microcontroller or compiler, where the directory name denotes the compiler
specific files the directory contains.



For example, if you are interested in the [compiler] port for the [architecture]
microcontroller, then the port specific files are contained in
FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
only port you are interested in then all the other directories can be
ignored.



================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/CMakeLists.txt
================================================
################# Add global include #################
list(APPEND ADD_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/core/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/dsp/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/nn/inc"
)
#######################################################

################# Add private include #################
list(APPEND ADD_PRIVATE_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/dsp/privateInc"
)
#######################################################

############## Add current dir source files ###########
file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/dsp/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/nn/*.c"
)
list(APPEND ADD_SRCS  ${sources})
# aux_source_directory(src ADD_SRCS)
# list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}")
#######################################################

########### Add required/dependent components #########
# list(APPEND ADD_REQUIREMENTS common)
#######################################################

############ Add static libs ##########################
#list(APPEND ADD_STATIC_LIB "libxxx.a")
#######################################################

############ Add dynamic libs #########################
# list(APPEND ADD_DYNAMIC_LIB "libxxx.so")
#######################################################

############ Add global compile option ################
#add components denpend on this component
list(APPEND ADD_DEFINITIONS -D__RISCV_FEATURE_MVE=0 -Wno-incompatible-pointer-types -Wno-parentheses)
#######################################################

############ Add private compile option ################
#add compile option for this component that won't affect other modules
# list(APPEND ADD_PRIVATE_DEFINITIONS )
#######################################################

generate_library()


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_compatiable.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_COMPATIABLE_H__
#define __CORE_COMPATIABLE_H__
/*!
 * @file     core_compatiable.h
 * @brief    ARM compatiable function definitions header file
 */
#ifdef __cplusplus
extern "C" {
#endif

/* ===== ARM Compatiable Functions ===== */
/**
 * \defgroup NMSIS_Core_ARMCompatiable_Functions   ARM Compatiable Functions
 * \ingroup  NMSIS_Core
 * \brief    A few functions that compatiable with ARM CMSIS-Core.
 * \details
 *
 * Here we provided a few functions that compatiable with ARM CMSIS-Core,
 * mostly used in the DSP and NN library.
 * @{
 */
/** \brief Instruction Synchronization Barrier, compatiable with ARM */
#define __ISB() __RWMB()

/** \brief Data Synchronization Barrier, compatiable with ARM */
#define __DSB() __RWMB()

/** \brief Data Memory Barrier, compatiable with ARM */
#define __DMB() __RWMB()

/** \brief LDRT Unprivileged (8 bit), ARM Compatiable */
#define __LDRBT(ptr) __LB((ptr))
/** \brief LDRT Unprivileged (16 bit), ARM Compatiable */
#define __LDRHT(ptr) __LH((ptr))
/** \brief LDRT Unprivileged (32 bit), ARM Compatiable */
#define __LDRT(ptr) __LW((ptr))

/** \brief STRT Unprivileged (8 bit), ARM Compatiable */
#define __STRBT(val, ptr) __SB((ptr), (val))
/** \brief STRT Unprivileged (16 bit), ARM Compatiable */
#define __STRHT(val, ptr) __SH((ptr), (val))
/** \brief STRT Unprivileged (32 bit), ARM Compatiable */
#define __STRT(val, ptr) __SW((ptr), (val))

/* ===== Saturation Operations ===== */
/**
 * \brief   Signed Saturate
 * \details Saturates a signed value.
 * \param [in]  value  Value to be saturated
 * \param [in]    sat  Bit position to saturate to (1..32)
 * \return             Saturated value
 */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __SSAT(val, sat) __RV_SCLIP32((val), (sat - 1))
#else
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
    if ((sat >= 1U) && (sat <= 32U)) {
        const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
        const int32_t min = -1 - max;
        if (val > max) {
            return max;
        } else if (val < min) {
            return min;
        }
    }
    return val;
}
#endif

/**
 * \brief   Unsigned Saturate
 * \details Saturates an unsigned value.
 * \param [in]  value  Value to be saturated
 * \param [in]    sat  Bit position to saturate to (0..31)
 * \return             Saturated value
 */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __USAT(val, sat) __RV_UCLIP32((val), (sat))
#else
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
    if (sat <= 31U) {
        const uint32_t max = ((1U << sat) - 1U);
        if (val > (int32_t)max) {
            return max;
        } else if (val < 0) {
            return 0U;
        }
    }
    return (uint32_t)val;
}
#endif
#if 0
/* ===== Data Processing Operations ===== */
/**
 * \brief   Reverse byte order (32 bit)
 * \details Reverses the byte order in unsigned integer value.
 * For example, 0x12345678 becomes 0x78563412.
 * \param [in]    value  Value to reverse
 * \return               Reversed value
 */
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
    uint32_t result;

    result = ((value & 0xff000000) >> 24) | ((value & 0x00ff0000) >> 8) | ((value & 0x0000ff00) << 8) | ((value & 0x000000ff) << 24);
    return result;
}

/**
 * \brief   Reverse byte order (16 bit)
 * \details Reverses the byte order within each halfword of a word.
 * For example, 0x12345678 becomes 0x34127856.
 * \param [in]    value  Value to reverse
 * \return               Reversed value
 */
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
{
    uint32_t result;
    result = ((value & 0xff000000) >> 8) | ((value & 0x00ff00000) << 8) | ((value & 0x0000ff00) >> 8) | ((value & 0x000000ff) << 8);

    return result;
}

/**
 * \brief   Reverse byte order (16 bit)
 * \details Reverses the byte order in a 16-bit value
 * and returns the signed 16-bit result.
 * For example, 0x0080 becomes 0x8000.
 * \param [in]    value  Value to reverse
 * \return               Reversed value
 */
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
    int16_t result;
    result = ((value & 0xff00) >> 8) | ((value & 0x00ff) << 8);
    return result;
}
#endif
/**
 * \brief   Rotate Right in unsigned value (32 bit)
 * \details Rotate Right (immediate) provides the value of
 * the contents of a register rotated by a variable number of bits.
 * \param [in]    op1  Value to rotate
 * \param [in]    op2  Number of Bits to rotate(0-31)
 * \return               Rotated value
 */
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
    op2 = op2 & 0x1F;
    if (op2 == 0U) {
        return op1;
    }
    return (op1 >> op2) | (op1 << (32U - op2));
}

/**
 * \brief   Reverse bit order of value
 * \details Reverses the bit order of the given value.
 * \param [in]    value  Value to reverse
 * \return               Reversed value
 */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __RBIT(value) __RV_BITREVI((value), 31)
#else
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
    uint32_t result;
    uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */

    result = value; /* r will be reversed bits of v; first get LSB of v */
    for (value >>= 1U; value != 0U; value >>= 1U) {
        result <<= 1U;
        result |= value & 1U;
        s--;
    }
    result <<= s; /* shift when v's highest bits are zero */
    return result;
}
#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */

/**
 * \brief   Count leading zeros
 * \details Counts the number of leading zeros of a data value.
 * \param [in]  data  Value to count the leading zeros
 * \return             number of leading zeros in value
 */
#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)
#define __CLZ(data) __RV_CLZ32(data)
#else
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
{
    uint8_t ret = 0;
    uint32_t temp = ~data;
    while (temp & 0x80000000) {
        temp <<= 1;
        ret++;
    }
    return ret;
}
#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */

/** @} */ /* End of Doxygen Group NMSIS_Core_ARMCompatiable_Functions */

#ifdef __cplusplus
}
#endif
#endif /* __CORE_COMPATIABLE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_base.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __CORE_FEATURE_BASE__
#define __CORE_FEATURE_BASE__
/*!
 * @file     core_feature_base.h
 * @brief    Base core feature API for Nuclei N/NX Core
 */
#include 
#include "riscv_encoding.h"

#ifdef __cplusplus
extern "C" {
#endif

/**
 * \defgroup NMSIS_Core_Registers     Register Define and Type Definitions
 * \brief   Type definitions and defines for core registers.
 *
 * @{
 */
#ifndef __RISCV_XLEN
/** \brief Refer to the width of an integer register in bits(either 32 or 64) */
#ifndef __riscv_xlen
#define __RISCV_XLEN 32
#else
#define __RISCV_XLEN __riscv_xlen
#endif
#endif /* __RISCV_XLEN */

/** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
#if __RISCV_XLEN == 32
typedef uint32_t rv_csr_t;
#elif __RISCV_XLEN == 64
typedef uint64_t rv_csr_t;
#else
typedef uint32_t rv_csr_t;
#endif
/** @} */ /* End of Doxygen Group NMSIS_Core_Registers */
/**
 * \defgroup NMSIS_Core_Base_Registers     Base Register Define and Type Definitions
 * \ingroup NMSIS_Core_Registers
 * \brief   Type definitions and defines for base core registers.
 *
 * @{
 */
/**
 * \brief  Union type to access MISA CSR register.
 */
typedef union {
    struct {
        rv_csr_t a          : 1; /*!< bit:     0  Atomic extension */
        rv_csr_t b          : 1; /*!< bit:     1  Tentatively reserved for Bit-Manipulation extension */
        rv_csr_t c          : 1; /*!< bit:     2  Compressed extension */
        rv_csr_t d          : 1; /*!< bit:     3  Double-precision floating-point extension */
        rv_csr_t e          : 1; /*!< bit:     4  RV32E base ISA */
        rv_csr_t f          : 1; /*!< bit:     5  Single-precision floating-point extension */
        rv_csr_t g          : 1; /*!< bit:     6  Additional standard extensions present */
        rv_csr_t h          : 1; /*!< bit:     7  Hypervisor extension */
        rv_csr_t i          : 1; /*!< bit:     8  RV32I/64I/128I base ISA */
        rv_csr_t j          : 1; /*!< bit:     9  Tentatively reserved for Dynamically Translated Languages extension */
        rv_csr_t _reserved1 : 1; /*!< bit:     10 Reserved  */
        rv_csr_t l          : 1; /*!< bit:     11 Tentatively reserved for Decimal Floating-Point extension  */
        rv_csr_t m          : 1; /*!< bit:     12 Integer Multiply/Divide extension */
        rv_csr_t n          : 1; /*!< bit:     13 User-level interrupts supported  */
        rv_csr_t _reserved2 : 1; /*!< bit:     14 Reserved  */
        rv_csr_t p          : 1; /*!< bit:     15 Tentatively reserved for Packed-SIMD extension  */
        rv_csr_t q          : 1; /*!< bit:     16 Quad-precision floating-point extension  */
        rv_csr_t _resreved3 : 1; /*!< bit:     17 Reserved  */
        rv_csr_t s          : 1; /*!< bit:     18 Supervisor mode implemented  */
        rv_csr_t t          : 1; /*!< bit:     19 Tentatively reserved for Transactional Memory extension  */
        rv_csr_t u          : 1; /*!< bit:     20 User mode implemented  */
        rv_csr_t v          : 1; /*!< bit:     21 Tentatively reserved for Vector extension  */
        rv_csr_t _reserved4 : 1; /*!< bit:     22 Reserved  */
        rv_csr_t x          : 1; /*!< bit:     23 Non-standard extensions present  */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved5 : 38; /*!< bit:     24..61 Reserved  */
        rv_csr_t mxl        : 2;  /*!< bit:     62..63 Machine XLEN  */
#else
        rv_csr_t _reserved5 : 6; /*!< bit:     24..29 Reserved  */
        rv_csr_t mxl        : 2; /*!< bit:     30..31 Machine XLEN  */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MISA_Type;

/**
 * \brief  Union type to access MSTATUS CSR register.
 */
typedef union {
    struct {
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved0 : 3;  /*!< bit:     0..2  Reserved */
        rv_csr_t mie        : 1;  /*!< bit:     3  Machine mode interrupt enable flag */
        rv_csr_t _reserved1 : 3;  /*!< bit:     4..6  Reserved */
        rv_csr_t mpie       : 1;  /*!< bit:     7  mirror of MIE flag */
        rv_csr_t _reserved2 : 3;  /*!< bit:     8..10  Reserved */
        rv_csr_t mpp        : 2;  /*!< bit:     11..12 mirror of Privilege Mode */
        rv_csr_t fs         : 2;  /*!< bit:     13..14 FS status flag */
        rv_csr_t xs         : 2;  /*!< bit:     15..16 XS status flag */
        rv_csr_t mprv       : 1;  /*!< bit:     Machine mode PMP */
        rv_csr_t _reserved3 : 14; /*!< bit:     18..31 Reserved */
        rv_csr_t uxl        : 2;  /*!< bit:     32..33 user mode xlen */
        rv_csr_t _reserved6 : 29; /*!< bit:     34..62 Reserved  */
        rv_csr_t sd         : 1;  /*!< bit:     Dirty status for XS or FS */
#else
        rv_csr_t _reserved0 : 1;  /*!< bit:     0  Reserved */
        rv_csr_t sie        : 1;  /*!< bit:     1  supervisor interrupt enable flag */
        rv_csr_t _reserved1 : 1;  /*!< bit:     2  Reserved */
        rv_csr_t mie        : 1;  /*!< bit:     3  Machine mode interrupt enable flag */
        rv_csr_t _reserved2 : 1;  /*!< bit:     4  Reserved */
        rv_csr_t spie       : 1;  /*!< bit:     3  Supervisor Privilede mode interrupt enable flag */
        rv_csr_t _reserved3 : 1;  /*!< bit:     Reserved */
        rv_csr_t mpie       : 1;  /*!< bit:     mirror of MIE flag */
        rv_csr_t _reserved4 : 3;  /*!< bit:     Reserved */
        rv_csr_t mpp        : 2;  /*!< bit:     mirror of Privilege Mode */
        rv_csr_t fs         : 2;  /*!< bit:     FS status flag */
        rv_csr_t xs         : 2;  /*!< bit:     XS status flag */
        rv_csr_t mprv       : 1;  /*!< bit:     Machine mode PMP */
        rv_csr_t sum        : 1;  /*!< bit:     Supervisor Mode load and store protection */
        rv_csr_t _reserved6 : 12; /*!< bit:     19..30 Reserved  */
        rv_csr_t sd         : 1;  /*!< bit:     Dirty status for XS or FS */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MSTATUS_Type;

/**
 * \brief  Union type to access MTVEC CSR register.
 */
typedef union {
    struct {
        rv_csr_t mode : 6; /*!< bit:     0..5   interrupt mode control */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t addr : 58; /*!< bit:     6..63  mtvec address */
#else
        rv_csr_t addr : 26; /*!< bit:     6..31  mtvec address */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MTVEC_Type;

/**
 * \brief  Union type to access MCAUSE CSR register.
 */
typedef union {
    struct {
        rv_csr_t exccode    : 12; /*!< bit:     11..0  exception or interrupt code */
        rv_csr_t _reserved0 : 4;  /*!< bit:     15..12  Reserved */
        rv_csr_t mpil       : 8;  /*!< bit:     23..16  Previous interrupt level */
        rv_csr_t _reserved1 : 3;  /*!< bit:     26..24  Reserved */
        rv_csr_t mpie       : 1;  /*!< bit:     27  Interrupt enable flag before enter interrupt */
        rv_csr_t mpp        : 2;  /*!< bit:     29..28  Privilede mode flag before enter interrupt */
        rv_csr_t minhv      : 1;  /*!< bit:     30  Machine interrupt vector table */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved2 : 32; /*!< bit:     31..62  Reserved */
        rv_csr_t interrupt  : 1;  /*!< bit:     63  trap type. 0 means exception and 1 means interrupt */
#else
        rv_csr_t interrupt : 1; /*!< bit:     31  trap type. 0 means exception and 1 means interrupt */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MCAUSE_Type;

/**
 * \brief  Union type to access MCOUNTINHIBIT CSR register.
 */
typedef union {
    struct {
        rv_csr_t cy         : 1; /*!< bit:     0     1 means disable mcycle counter */
        rv_csr_t _reserved0 : 1; /*!< bit:     1     Reserved */
        rv_csr_t ir         : 1; /*!< bit:     2     1 means disable minstret counter */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved1 : 61; /*!< bit:     3..63 Reserved */
#else
        rv_csr_t _reserved1 : 29; /*!< bit:     3..31 Reserved */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MCOUNTINHIBIT_Type;

/**
 * \brief  Union type to access MSUBM CSR register.
 */
typedef union {
    struct {
        rv_csr_t _reserved0 : 6; /*!< bit:     0..5   Reserved */
        rv_csr_t typ        : 2; /*!< bit:     6..7   current trap type */
        rv_csr_t ptyp       : 2; /*!< bit:     8..9   previous trap type */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved1 : 54; /*!< bit:     10..63 Reserved */
#else
        rv_csr_t _reserved1 : 22; /*!< bit:     10..31 Reserved */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MSUBM_Type;

/**
 * \brief  Union type to access MDCAUSE CSR register.
 */
typedef union {
    struct {
        rv_csr_t mdcause : 2;                   /*!< bit:     0..1   More detailed exception information as MCAUSE supplement */
        rv_csr_t _reserved0 : __RISCV_XLEN - 2; /*!< bit:     2..XLEN-1 Reserved */
    } b;                                        /*!< Structure used for bit  access */
    rv_csr_t d;                                 /*!< Type      used for csr data access */
} CSR_MDCAUSE_Type;

/**
 * \brief  Union type to access MMISC_CTRL CSR register.
 */
typedef union {
    struct {
        rv_csr_t _reserved0 : 3; /*!< bit:     0..2  Reserved */
        rv_csr_t bpu        : 1; /*!< bit:     3     dynamic prediction enable flag */
        rv_csr_t _reserved1 : 2; /*!< bit:     4..5  Reserved */
        rv_csr_t misalign   : 1; /*!< bit:     6     misaligned access support flag */
        rv_csr_t _reserved2 : 2; /*!< bit:     7..8  Reserved */
        rv_csr_t nmi_cause  : 1; /*!< bit:     9     mnvec control and nmi mcase exccode */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved3 : 54; /*!< bit:     10..63 Reserved */
#else
        rv_csr_t _reserved3 : 22; /*!< bit:     10..31 Reserved */
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MMISCCTRL_Type;

typedef CSR_MMISCCTRL_Type CSR_MMISCCTL_Type;

/**
 * \brief  Union type to access MCACHE_CTL CSR register.
 */
typedef union {
    struct {
        rv_csr_t ic_en          : 1; /*!< I-Cache enable */
        rv_csr_t ic_scpd_mod    : 1; /*!< Scratchpad mode, 0: Scratchpad as ICache Data RAM, 1: Scratchpad as ILM SRAM */
        rv_csr_t ic_ecc_en      : 1; /*!< I-Cache ECC enable */
        rv_csr_t ic_ecc_excp_en : 1; /*!< I-Cache 2bit ECC error exception enable */
        rv_csr_t ic_rwtecc      : 1; /*!< Control I-Cache Tag Ram ECC code injection */
        rv_csr_t ic_rwdecc      : 1; /*!< Control I-Cache Data Ram ECC code injection */
        rv_csr_t _reserved0     : 10;
        rv_csr_t dc_en          : 1; /*!< DCache enable */
        rv_csr_t dc_ecc_en      : 1; /*!< D-Cache ECC enable */
        rv_csr_t dc_ecc_excp_en : 1; /*!< D-Cache 2bit ECC error exception enable */
        rv_csr_t dc_rwtecc      : 1; /*!< Control D-Cache Tag Ram ECC code injection */
        rv_csr_t dc_rwdecc      : 1; /*!< Control D-Cache Data Ram ECC code injection */
        rv_csr_t _reserved1 : __RISCV_XLEN - 21;
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MCACHECTL_Type;

/**
 * \brief  Union type to access MSAVESTATUS CSR register.
 */
typedef union {
    struct {
        rv_csr_t mpie1      : 1; /*!< bit:     0     interrupt enable flag of fisrt level NMI/exception nestting */
        rv_csr_t mpp1       : 2; /*!< bit:     1..2  privilede mode of fisrt level NMI/exception nestting */
        rv_csr_t _reserved0 : 3; /*!< bit:     3..5  Reserved */
        rv_csr_t ptyp1      : 2; /*!< bit:     6..7  NMI/exception type of before first nestting */
        rv_csr_t mpie2      : 1; /*!< bit:     8     interrupt enable flag of second level NMI/exception nestting */
        rv_csr_t mpp2       : 2; /*!< bit:     9..10 privilede mode of second level NMI/exception nestting */
        rv_csr_t _reserved1 : 3; /*!< bit:     11..13     Reserved */
        rv_csr_t ptyp2      : 2; /*!< bit:     14..15     NMI/exception type of before second nestting */
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved2 : 48; /*!< bit:     16..63 Reserved*/
#else
        rv_csr_t _reserved2 : 16; /*!< bit:     16..31 Reserved*/
#endif
    } b;        /*!< Structure used for bit  access */
    rv_csr_t w; /*!< Type      used for csr data access */
} CSR_MSAVESTATUS_Type;

/**
 * \brief  Union type to access MILM_CTL CSR register.
 */
typedef union {
    struct {
        rv_csr_t ilm_en          : 1;         /*!< ILM enable */
        rv_csr_t ilm_ecc_en      : 1;         /*!< ILM ECC eanble */
        rv_csr_t ilm_ecc_excp_en : 1;         /*!< ILM ECC exception enable */
        rv_csr_t ilm_rwecc       : 1;         /*!< Control mecc_code write to ilm, simulate error injection */
        rv_csr_t _reserved0      : 6;         /*!< Reserved */
        rv_csr_t ilm_bpa : __RISCV_XLEN - 10; /*!< ILM base address */
    } b;                                      /*!< Structure used for bit  access */
    rv_csr_t d;                               /*!< Type      used for csr data access */
} CSR_MILMCTL_Type;

/**
 * \brief  Union type to access MDLM_CTL CSR register.
 */
typedef union {
    struct {
        rv_csr_t dlm_en          : 1;         /*!< DLM enable */
        rv_csr_t dlm_ecc_en      : 1;         /*!< DLM ECC eanble */
        rv_csr_t dlm_ecc_excp_en : 1;         /*!< DLM ECC exception enable */
        rv_csr_t dlm_rwecc       : 1;         /*!< Control mecc_code write to dlm, simulate error injection */
        rv_csr_t _reserved0      : 6;         /*!< Reserved */
        rv_csr_t dlm_bpa : __RISCV_XLEN - 10; /*!< DLM base address */
    } b;                                      /*!< Structure used for bit  access */
    rv_csr_t d;                               /*!< Type      used for csr data access */
} CSR_MDLMCTL_Type;

/**
 * \brief  Union type to access MCFG_INFO CSR register.
 */
typedef union {
    struct {
        rv_csr_t tee    : 1; /*!< TEE present */
        rv_csr_t ecc    : 1; /*!< ECC present */
        rv_csr_t clic   : 1; /*!< CLIC present */
        rv_csr_t plic   : 1; /*!< PLIC present */
        rv_csr_t fio    : 1; /*!< FIO present */
        rv_csr_t ppi    : 1; /*!< PPI present */
        rv_csr_t nice   : 1; /*!< NICE present */
        rv_csr_t ilm    : 1; /*!< ILM present */
        rv_csr_t dlm    : 1; /*!< DLM present */
        rv_csr_t icache : 1; /*!< ICache present */
        rv_csr_t dcache : 1; /*!< DCache present */
        rv_csr_t _reserved0 : __RISCV_XLEN - 11;
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MCFGINFO_Type;

/**
 * \brief  Union type to access MICFG_INFO CSR register.
 */
typedef union {
    struct {
        rv_csr_t set        : 4; /*!< I-Cache sets per way */
        rv_csr_t way        : 3; /*!< I-Cache way */
        rv_csr_t lsize      : 3; /*!< I-Cache line size */
        rv_csr_t cache_ecc  : 1; /*!< I-Cache ECC present */
        rv_csr_t _reserved0 : 5;
        rv_csr_t lm_size    : 5; /*!< ILM size, need to be 2^n size */
        rv_csr_t lm_xonly   : 1; /*!< ILM Execute only permission */
        rv_csr_t lm_ecc     : 1; /*!< ILM ECC present */
        rv_csr_t _reserved1 : __RISCV_XLEN - 23;
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MICFGINFO_Type;

/**
 * \brief  Union type to access MDCFG_INFO CSR register.
 */
typedef union {
    struct {
        rv_csr_t set        : 4; /*!< D-Cache sets per way */
        rv_csr_t way        : 3; /*!< D-Cache way */
        rv_csr_t lsize      : 3; /*!< D-Cache line size */
        rv_csr_t cache_ecc  : 1; /*!< D-Cache ECC present */
        rv_csr_t _reserved0 : 5;
        rv_csr_t lm_size    : 5; /*!< DLM size, need to be 2^n size */
        rv_csr_t lm_xonly   : 1; /*!< DLM Execute only permission */
        rv_csr_t lm_ecc     : 1; /*!< DLM ECC present */
        rv_csr_t _reserved1 : __RISCV_XLEN - 23;
    } b;        /*!< Structure used for bit  access */
    rv_csr_t d; /*!< Type      used for csr data access */
} CSR_MDCFGINFO_Type;

/**
 * \brief  Union type to access MPPICFG_INFO CSR register.
 */
typedef union {
    struct {
        rv_csr_t _reserved0 : 1;              /*!< Reserved */
        rv_csr_t ppi_size   : 5;              /*!< PPI size, need to be 2^n size */
        rv_csr_t _reserved1 : 4;              /*!< Reserved */
        rv_csr_t ppi_bpa : __RISCV_XLEN - 10; /*!< PPI base address */
    } b;                                      /*!< Structure used for bit  access */
    rv_csr_t d;                               /*!< Type      used for csr data access */
} CSR_MPPICFGINFO_Type;

/**
 * \brief  Union type to access MFIOCFG_INFO CSR register.
 */
typedef union {
    struct {
        rv_csr_t _reserved0 : 1;              /*!< Reserved */
        rv_csr_t fio_size   : 5;              /*!< FIO size, need to be 2^n size */
        rv_csr_t _reserved1 : 4;              /*!< Reserved */
        rv_csr_t fio_bpa : __RISCV_XLEN - 10; /*!< FIO base address */
    } b;                                      /*!< Structure used for bit  access */
    rv_csr_t d;                               /*!< Type      used for csr data access */
} CSR_MFIOCFGINFO_Type;

/**
 * \brief  Union type to access MECC_LOCK CSR register.
 */
typedef union {
    struct {
        rv_csr_t ecc_lock : 1;                  /*!< RW permission, ECC Lock configure */
        rv_csr_t _reserved0 : __RISCV_XLEN - 1; /*!< Reserved */
    } b;                                        /*!< Structure used for bit  access */
    rv_csr_t d;                                 /*!< Type      used for csr data access */
} CSR_MECCLOCK_Type;

/**
 * \brief  Union type to access MECC_CODE CSR register.
 */
typedef union {
    struct {
        rv_csr_t code       : 9;                 /*!< Used to inject ECC check code */
        rv_csr_t _reserved0 : 7;                 /*!< Reserved */
        rv_csr_t ramid      : 5;                 /*!< Indicate 2bit ECC error, software can clear these bits */
        rv_csr_t _reserved1 : 3;                 /*!< Reserved */
        rv_csr_t sramid     : 5;                 /*!< Indicate 1bit ECC error, software can clear these bits */
        rv_csr_t _reserved2 : __RISCV_XLEN - 29; /*!< Reserved */
    } b;                                         /*!< Structure used for bit  access */
    rv_csr_t d;                                  /*!< Type      used for csr data access */
} CSR_MECCCODE_Type;

/** @} */ /* End of Doxygen Group NMSIS_Core_Base_Registers */

/* ###########################  Core Function Access  ########################### */
/**
 * \defgroup NMSIS_Core_CSR_Register_Access    Core CSR Register Access
 * \ingroup  NMSIS_Core
 * \brief    Functions to access the Core CSR Registers
 * \details
 *
 * The following functions or macros provide access to Core CSR registers.
 * - \ref NMSIS_Core_CSR_Encoding
 * - \ref NMSIS_Core_CSR_Registers
 *   @{
 */

#ifndef __ASSEMBLY__

/**
 * \brief CSR operation Macro for csrrw instruction.
 * \details
 * Read the content of csr register to __v,
 * then write content of val into csr register, then return __v
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   value to store into the CSR register
 * \return the CSR register value before written
 */
#define __RV_CSR_SWAP(csr, val)                           \
    ({                                                    \
        register rv_csr_t __v = (unsigned long)(val);     \
        __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" \
                       : "=r"(__v)                        \
                       : "rK"(__v)                        \
                       : "memory");                       \
        __v;                                              \
    })

/**
 * \brief CSR operation Macro for csrr instruction.
 * \details
 * Read the content of csr register to __v and return it
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \return the CSR register value
 */
#define __RV_CSR_READ(csr)                        \
    ({                                            \
        register rv_csr_t __v;                    \
        __ASM volatile("csrr %0, " STRINGIFY(csr) \
                       : "=r"(__v)                \
                       :                          \
                       : "memory");               \
        __v;                                      \
    })

/**
 * \brief CSR operation Macro for csrw instruction.
 * \details
 * Write the content of val to csr register
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   value to store into the CSR register
 */
#define __RV_CSR_WRITE(csr, val)                     \
    ({                                               \
        register rv_csr_t __v = (rv_csr_t)(val);     \
        __ASM volatile("csrw " STRINGIFY(csr) ", %0" \
                       :                             \
                       : "rK"(__v)                   \
                       : "memory");                  \
    })

/**
 * \brief CSR operation Macro for csrrs instruction.
 * \details
 * Read the content of csr register to __v,
 * then set csr register to be __v | val, then return __v
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   Mask value to be used wih csrrs instruction
 * \return the CSR register value before written
 */
#define __RV_CSR_READ_SET(csr, val)                       \
    ({                                                    \
        register rv_csr_t __v = (rv_csr_t)(val);          \
        __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" \
                       : "=r"(__v)                        \
                       : "rK"(__v)                        \
                       : "memory");                       \
        __v;                                              \
    })

/**
 * \brief CSR operation Macro for csrs instruction.
 * \details
 * Set csr register to be csr_content | val
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   Mask value to be used wih csrs instruction
 */
#define __RV_CSR_SET(csr, val)                       \
    ({                                               \
        register rv_csr_t __v = (rv_csr_t)(val);     \
        __ASM volatile("csrs " STRINGIFY(csr) ", %0" \
                       :                             \
                       : "rK"(__v)                   \
                       : "memory");                  \
    })

/**
 * \brief CSR operation Macro for csrrc instruction.
 * \details
 * Read the content of csr register to __v,
 * then set csr register to be __v & ~val, then return __v
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   Mask value to be used wih csrrc instruction
 * \return the CSR register value before written
 */
#define __RV_CSR_READ_CLEAR(csr, val)                     \
    ({                                                    \
        register rv_csr_t __v = (rv_csr_t)(val);          \
        __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" \
                       : "=r"(__v)                        \
                       : "rK"(__v)                        \
                       : "memory");                       \
        __v;                                              \
    })

/**
 * \brief CSR operation Macro for csrc instruction.
 * \details
 * Set csr register to be csr_content & ~val
 * \param csr   CSR macro definition defined in
 *              \ref NMSIS_Core_CSR_Registers, eg. \ref CSR_MSTATUS
 * \param val   Mask value to be used wih csrc instruction
 */
#define __RV_CSR_CLEAR(csr, val)                     \
    ({                                               \
        register rv_csr_t __v = (rv_csr_t)(val);     \
        __ASM volatile("csrc " STRINGIFY(csr) ", %0" \
                       :                             \
                       : "rK"(__v)                   \
                       : "memory");                  \
    })
#endif /* __ASSEMBLY__ */
#if 0
/**
 * \brief   Enable IRQ Interrupts
 * \details Enables IRQ interrupts by setting the MIE-bit in the MSTATUS Register.
 * \remarks
 *          Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __enable_irq(void)
{
    __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE);
}

/**
 * \brief   Disable IRQ Interrupts
 * \details Disables IRQ interrupts by clearing the MIE-bit in the MSTATUS Register.
 * \remarks
 *          Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
    __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
}
#endif
/**
 * \brief   Read whole 64 bits value of mcycle counter
 * \details This function will read the whole 64 bits of MCYCLE register
 * \return  The whole 64 bits value of MCYCLE
 * \remarks It will work for both RV32 and RV64 to get full 64bits value of MCYCLE
 */
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;

    high0 = __RV_CSR_READ(CSR_MCYCLEH);
    low = __RV_CSR_READ(CSR_MCYCLE);
    high = __RV_CSR_READ(CSR_MCYCLEH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_MCYCLE);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
#endif
}

/**
 * \brief   Read whole 64 bits value of machine instruction-retired counter
 * \details This function will read the whole 64 bits of MINSTRET register
 * \return  The whole 64 bits value of MINSTRET
 * \remarks It will work for both RV32 and RV64 to get full 64bits value of MINSTRET
 */
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;

    high0 = __RV_CSR_READ(CSR_MINSTRETH);
    low = __RV_CSR_READ(CSR_MINSTRET);
    high = __RV_CSR_READ(CSR_MINSTRETH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_MINSTRET);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
#endif
}

/**
 * \brief   Read whole 64 bits value of real-time clock
 * \details This function will read the whole 64 bits of TIME register
 * \return  The whole 64 bits value of TIME CSR
 * \remarks It will work for both RV32 and RV64 to get full 64bits value of TIME
 * \attention only available when user mode available
 */
__STATIC_FORCEINLINE uint64_t __get_rv_time(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;

    high0 = __RV_CSR_READ(CSR_TIMEH);
    low = __RV_CSR_READ(CSR_TIME);
    high = __RV_CSR_READ(CSR_TIMEH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_TIME);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_TIME);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_TIME);
#endif
}

/** @} */ /* End of Doxygen Group NMSIS_Core_CSR_Register_Access */

/* ###########################  CPU Intrinsic Functions ########################### */
/**
 * \defgroup NMSIS_Core_CPU_Intrinsic   Intrinsic Functions for CPU Intructions
 * \ingroup  NMSIS_Core
 * \brief    Functions that generate RISC-V CPU instructions.
 * \details
 *
 * The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler.
 *   @{
 */
#if 0
/**
 * \brief   NOP Instruction
 * \details
 * No Operation does nothing.
 * This instruction can be used for code alignment purposes.
 */
__STATIC_FORCEINLINE void __NOP(void)
{
    __ASM volatile("nop");
}

/**
 * \brief   Wait For Interrupt
 * \details
 * Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction.
 * It will suspends execution until interrupt, NMI or Debug happened.
 * When Core is waked up by interrupt, if
 * 1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
 * 2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution
 */
__STATIC_FORCEINLINE void __WFI(void)
{
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
}

/**
 * \brief   Wait For Event
 * \details
 * Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction.
 * It will suspends execution until event, NMI or Debug happened.
 * When Core is waked up, Core will resume previous execution
 */
__STATIC_FORCEINLINE void __WFE(void)
{
    __RV_CSR_SET(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
}

/**
 * \brief   Breakpoint Instruction
 * \details
 * Causes the processor to enter Debug state.
 * Debug tools can use this to investigate system state
 * when the instruction at a particular address is reached.
 */
__STATIC_FORCEINLINE void __EBREAK(void)
{
    __ASM volatile("ebreak");
}

/**
 * \brief   Environment Call Instruction
 * \details
 * The ECALL instruction is used to make a service request to
 * the execution environment.
 */
__STATIC_FORCEINLINE void __ECALL(void)
{
    __ASM volatile("ecall");
}
#endif
/**
 * \brief WFI Sleep Mode enumeration
 */
typedef enum WFI_SleepMode {
    WFI_SHALLOW_SLEEP = 0, /*!< Shallow sleep mode, the core_clk will poweroff */
    WFI_DEEP_SLEEP = 1     /*!< Deep sleep mode, the core_clk and core_ano_clk will poweroff */
} WFI_SleepMode_Type;

/**
 * \brief   Set Sleep mode of WFI
 * \details
 * Set the SLEEPVALUE CSR register to control the
 * WFI Sleep mode.
 * \param[in] mode      The sleep mode to be set
 */
__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
{
    __RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
}

/**
 * \brief   Send TX Event
 * \details
 * Set the CSR TXEVT to control send a TX Event.
 * The Core will output signal tx_evt as output event signal.
 */
__STATIC_FORCEINLINE void __TXEVT(void)
{
    __RV_CSR_SET(CSR_TXEVT, 0x1);
}

/**
 * \brief   Enable MCYCLE counter
 * \details
 * Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter
 */
__STATIC_FORCEINLINE void __enable_mcycle_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}

/**
 * \brief   Disable MCYCLE counter
 * \details
 * Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter
 */
__STATIC_FORCEINLINE void __disable_mcycle_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}

/**
 * \brief   Enable MINSTRET counter
 * \details
 * Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter
 */
__STATIC_FORCEINLINE void __enable_minstret_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}

/**
 * \brief   Disable MINSTRET counter
 * \details
 * Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter
 */
__STATIC_FORCEINLINE void __disable_minstret_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}

/**
 * \brief   Enable MCYCLE & MINSTRET counter
 * \details
 * Clear the IR and CY bit of MCOUNTINHIBIT to 1 to enable MINSTRET & MCYCLE Counter
 */
__STATIC_FORCEINLINE void __enable_all_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY);
}

/**
 * \brief   Disable MCYCLE & MINSTRET counter
 * \details
 * Set the IR and CY bit of MCOUNTINHIBIT to 1 to disable MINSTRET & MCYCLE Counter
 */
__STATIC_FORCEINLINE void __disable_all_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR | MCOUNTINHIBIT_CY);
}

/**
 * \brief Execute fence instruction, p -> pred, s -> succ
 * \details
 * the FENCE instruction ensures that all memory accesses from instructions preceding
 * the fence in program order (the `predecessor set`) appear earlier in the global memory order than
 * memory accesses from instructions appearing after the fence in program order (the `successor set`).
 * For details, please refer to The RISC-V Instruction Set Manual
 * \param p     predecessor set, such as iorw, rw, r, w
 * \param s     successor set, such as iorw, rw, r, w
 **/
#define __FENCE(p, s) __ASM volatile("fence " #p "," #s \
                                     :                  \
                                     :                  \
                                     : "memory")

/**
 * \brief   Fence.i Instruction
 * \details
 * The FENCE.I instruction is used to synchronize the instruction
 * and data streams.
 */
__STATIC_FORCEINLINE void __FENCE_I(void)
{
    __ASM volatile("fence.i");
}

/** \brief Read & Write Memory barrier */
#define __RWMB() __FENCE(iorw, iorw)

/** \brief Read Memory barrier */
#define __RMB() __FENCE(ir, ir)

/** \brief Write Memory barrier */
#define __WMB() __FENCE(ow, ow)

/** \brief SMP Read & Write Memory barrier */
#define __SMP_RWMB() __FENCE(rw, rw)

/** \brief SMP Read Memory barrier */
#define __SMP_RMB() __FENCE(r, r)

/** \brief SMP Write Memory barrier */
#define __SMP_WMB() __FENCE(w, w)

/** \brief CPU relax for busy loop */
#define __CPU_RELAX() __ASM volatile("" \
                                     :  \
                                     :  \
                                     : "memory")

/* ===== Load/Store Operations ===== */
/**
 * \brief  Load 8bit value from address (8 bit)
 * \details Load 8 bit value.
 * \param [in]    addr  Address pointer to data
 * \return              value of type uint8_t at (*addr)
 */
__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
{
    uint8_t result;

    __ASM volatile("lb %0, 0(%1)"
                   : "=r"(result)
                   : "r"(addr));
    return result;
}

/**
 * \brief  Load 16bit value from address (16 bit)
 * \details Load 16 bit value.
 * \param [in]    addr  Address pointer to data
 * \return              value of type uint16_t at (*addr)
 */
__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
{
    uint16_t result;

    __ASM volatile("lh %0, 0(%1)"
                   : "=r"(result)
                   : "r"(addr));
    return result;
}

/**
 * \brief  Load 32bit value from address (32 bit)
 * \details Load 32 bit value.
 * \param [in]    addr  Address pointer to data
 * \return              value of type uint32_t at (*addr)
 */
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
{
    uint32_t result;

    __ASM volatile("lw %0, 0(%1)"
                   : "=r"(result)
                   : "r"(addr));
    return result;
}

#if __RISCV_XLEN != 32
/**
 * \brief  Load 64bit value from address (64 bit)
 * \details Load 64 bit value.
 * \param [in]    addr  Address pointer to data
 * \return              value of type uint64_t at (*addr)
 * \remarks RV64 only macro
 */
__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
{
    uint64_t result;
    __ASM volatile("ld %0, 0(%1)"
                   : "=r"(result)
                   : "r"(addr));
    return result;
}
#endif

/**
 * \brief  Write 8bit value to address (8 bit)
 * \details Write 8 bit value.
 * \param [in]    addr  Address pointer to data
 * \param [in]    val   Value to set
 */
__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
{
    __ASM volatile("sb %0, 0(%1)"
                   :
                   : "r"(val), "r"(addr));
}

/**
 * \brief  Write 16bit value to address (16 bit)
 * \details Write 16 bit value.
 * \param [in]    addr  Address pointer to data
 * \param [in]    val   Value to set
 */
__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
{
    __ASM volatile("sh %0, 0(%1)"
                   :
                   : "r"(val), "r"(addr));
}

/**
 * \brief  Write 32bit value to address (32 bit)
 * \details Write 32 bit value.
 * \param [in]    addr  Address pointer to data
 * \param [in]    val   Value to set
 */
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
{
    __ASM volatile("sw %0, 0(%1)"
                   :
                   : "r"(val), "r"(addr));
}

#if __RISCV_XLEN != 32
/**
 * \brief  Write 64bit value to address (64 bit)
 * \details Write 64 bit value.
 * \param [in]    addr  Address pointer to data
 * \param [in]    val   Value to set
 */
__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
{
    __ASM volatile("sd %0, 0(%1)"
                   :
                   : "r"(val), "r"(addr));
}
#endif

/**
 * \brief  Compare and Swap 32bit value using LR and SC
 * \details Compare old value with memory, if identical,
 * store new value in memory. Return the initial value in memory.
 * Success is indicated by comparing return value with OLD.
 * memory address, return 0 if successful, otherwise return !0
 * \param [in]    addr      Address pointer to data, address need to be 4byte aligned
 * \param [in]    oldval    Old value of the data in address
 * \param [in]    newval    New value to be stored into the address
 * \return  return the initial value in memory
 */
__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
{
    register uint32_t result;
    register uint32_t rc;

    __ASM volatile(
        "0:     lr.w %0, %2      \n"
        "       bne  %0, %z3, 1f \n"
        "       sc.w %1, %z4, %2 \n"
        "       bnez %1, 0b      \n"
        "1:\n"
        : "=&r"(result), "=&r"(rc), "+A"(*addr)
        : "r"(oldval), "r"(newval)
        : "memory");
    return result;
}

/**
 * \brief  Atomic Swap 32bit value into memory
 * \details Atomically swap new 32bit value into memory using amoswap.d.
 * \param [in]    addr      Address pointer to data, address need to be 4byte aligned
 * \param [in]    newval    New value to be stored into the address
 * \return  return the original value in memory
 */
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
{
    register uint32_t result;

    __ASM volatile("amoswap.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(newval)
                   : "memory");
    return result;
}

/**
 * \brief  Atomic Add with 32bit value
 * \details Atomically ADD 32bit value with value in memory using amoadd.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be ADDed
 * \return  return memory value + add value
 */
__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amoadd.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic And with 32bit value
 * \details Atomically AND 32bit value with value in memory using amoand.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be ANDed
 * \return  return memory value & and value
 */
__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amoand.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic OR with 32bit value
 * \details Atomically OR 32bit value with value in memory using amoor.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be ORed
 * \return  return memory value | and value
 */
__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amoor.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic XOR with 32bit value
 * \details Atomically XOR 32bit value with value in memory using amoxor.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be XORed
 * \return  return memory value ^ and value
 */
__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amoxor.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic unsigned MAX with 32bit value
 * \details Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be compared
 * \return  return the bigger value
 */
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
{
    register uint32_t result;

    __ASM volatile("amomaxu.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic signed MAX with 32bit value
 * \details Atomically signed max compare 32bit value with value in memory using amomax.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be compared
 * \return the bigger value
 */
__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amomax.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic unsigned MIN with 32bit value
 * \details Atomically unsigned min compare 32bit value with value in memory using amominu.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be compared
 * \return the smaller value
 */
__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
{
    register uint32_t result;

    __ASM volatile("amominu.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic signed MIN with 32bit value
 * \details Atomically signed min compare 32bit value with value in memory using amomin.d.
 * \param [in]    addr   Address pointer to data, address need to be 4byte aligned
 * \param [in]    value  value to be compared
 * \return  the smaller value
 */
__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
{
    register int32_t result;

    __ASM volatile("amomin.w %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

#if __RISCV_XLEN == 64
/**
 * \brief  Compare and Swap 64bit value using LR and SC
 * \details Compare old value with memory, if identical,
 * store new value in memory. Return the initial value in memory.
 * Success is indicated by comparing return value with OLD.
 * memory address, return 0 if successful, otherwise return !0
 * \param [in]    addr      Address pointer to data, address need to be 8byte aligned
 * \param [in]    oldval    Old value of the data in address
 * \param [in]    newval    New value to be stored into the address
 * \return  return the initial value in memory
 */
__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval)
{
    register uint64_t result;
    register uint64_t rc;

    __ASM volatile(
        "0:     lr.d %0, %2      \n"
        "       bne  %0, %z3, 1f \n"
        "       sc.d %1, %z4, %2 \n"
        "       bnez %1, 0b      \n"
        "1:\n"
        : "=&r"(result), "=&r"(rc), "+A"(*addr)
        : "r"(oldval), "r"(newval)
        : "memory");
    return result;
}

/**
 * \brief  Atomic Swap 64bit value into memory
 * \details Atomically swap new 64bit value into memory using amoswap.d.
 * \param [in]    addr      Address pointer to data, address need to be 8byte aligned
 * \param [in]    newval    New value to be stored into the address
 * \return  return the original value in memory
 */
__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval)
{
    register uint64_t result;

    __ASM volatile("amoswap.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(newval)
                   : "memory");
    return result;
}

/**
 * \brief  Atomic Add with 64bit value
 * \details Atomically ADD 64bit value with value in memory using amoadd.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be ADDed
 * \return  return memory value + add value
 */
__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amoadd.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic And with 64bit value
 * \details Atomically AND 64bit value with value in memory using amoand.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be ANDed
 * \return  return memory value & and value
 */
__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amoand.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic OR with 64bit value
 * \details Atomically OR 64bit value with value in memory using amoor.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be ORed
 * \return  return memory value | and value
 */
__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amoor.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic XOR with 64bit value
 * \details Atomically XOR 64bit value with value in memory using amoxor.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be XORed
 * \return  return memory value ^ and value
 */
__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amoxor.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic unsigned MAX with 64bit value
 * \details Atomically unsigned max compare 64bit value with value in memory using amomaxu.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be compared
 * \return  return the bigger value
 */
__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value)
{
    register uint64_t result;

    __ASM volatile("amomaxu.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic signed MAX with 64bit value
 * \details Atomically signed max compare 64bit value with value in memory using amomax.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be compared
 * \return the bigger value
 */
__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amomax.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic unsigned MIN with 64bit value
 * \details Atomically unsigned min compare 64bit value with value in memory using amominu.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be compared
 * \return the smaller value
 */
__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value)
{
    register uint64_t result;

    __ASM volatile("amominu.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}

/**
 * \brief  Atomic signed MIN with 64bit value
 * \details Atomically signed min compare 64bit value with value in memory using amomin.d.
 * \param [in]    addr   Address pointer to data, address need to be 8byte aligned
 * \param [in]    value  value to be compared
 * \return  the smaller value
 */
__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value)
{
    register int64_t result;

    __ASM volatile("amomin.d %0, %2, %1"
                   : "=r"(result), "+A"(*addr)
                   : "r"(value)
                   : "memory");
    return *addr;
}
#endif /* __RISCV_XLEN == 64  */

/** @} */ /* End of Doxygen Group NMSIS_Core_CPU_Intrinsic */

#ifdef __cplusplus
}
#endif
#endif /* __CORE_FEATURE_BASE__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_cache.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_CACHE_H__
#define __CORE_FEATURE_CACHE_H__
/*!
 * @file     core_feature_cache.h
 * @brief    Cache feature API header file for Nuclei N/NX Core
 */
/*
 * Cache Feature Configuration Macro:
 * 1. __ICACHE_PRESENT:  Define whether I-Cache Unit is present or not.
 *   * 0: Not present
 *   * 1: Present
 * 1. __DCACHE_PRESENT:  Define whether D-Cache Unit is present or not.
 *   * 0: Not present
 *   * 1: Present
 */
#ifdef __cplusplus
 extern "C" {
#endif

#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)) \
    || (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1))

/* ##########################  Cache functions  #################################### */
/**
 * \defgroup NMSIS_Core_Cache       Cache Functions
 * \brief    Functions that configure Instruction and Data Cache.
 * @{
 *
 * Nuclei provide Cache Control and Maintainence(CCM) for software to control and maintain
 * the internal L1 I/D Cache of the RISC-V Core, software can manage the cache flexibly to
 * meet the actual application scenarios.
 *
 * The CCM operations have 3 types: by single address, by all and flush pipeline.
 * The CCM operations are done via CSR registers, M/S/U mode has its own CSR registers to
 * do CCM operations. By default, CCM operations are not allowed in S/U mode, you can execute
 * \ref EnableSUCCM in M-Mode to enable it.
 *
 * * API names started with M, such as \ref MInvalICacheLine must be called in M-Mode only.
 * * API names started with S, such as \ref SInvalICacheLine should be called in S-Mode.
 * * API names started with U, such as \ref UInvalICacheLine should be called in U-Mode.
 *
 */


/**
 * \brief Cache CCM Operation Fail Info
 */
typedef enum CCM_OP_FINFO {
    CCM_OP_SUCCESS = 0x0,               /*!< Lock Succeed */
    CCM_OP_EXCEED_ERR = 0x1,            /*!< Exceed the the number of lockable ways(N-Way I/D-Cache, lockable is N-1) */
    CCM_OP_PERM_CHECK_ERR = 0x2,        /*!< PMP/sPMP/Page-Table X(I-Cache)/R(D-Cache) permission check failed, or belong to Device/Non-Cacheable address range */
    CCM_OP_REFILL_BUS_ERR = 0x3,        /*!< Refill has Bus Error */
    CCM_OP_ECC_ERR = 0x4                /*!< ECC Error */
} CCM_OP_FINFO_Type;

/**
 * \brief Cache CCM Command Types
 */
typedef enum CCM_CMD {
    CCM_DC_INVAL = 0x0,                 /*!< Unlock and invalidate D-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_DC_WB = 0x1,                    /*!< Flush the specific D-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_DC_WBINVAL = 0x2,               /*!< Unlock, flush and invalidate the specific D-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_DC_LOCK = 0x3,                  /*!< Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_DC_UNLOCK = 0x4,                /*!< Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_DC_WBINVAL_ALL = 0x6,           /*!< Unlock and flush and invalidate all the valid and dirty D-Cache lines */
    CCM_DC_WB_ALL = 0x7,                /*!< Flush all the valid and dirty D-Cache lines */
    CCM_DC_INVAL_ALL = 0x17,            /*!< Unlock and invalidate all the D-Cache lines */
    CCM_IC_INVAL = 0x8,                 /*!< Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_IC_LOCK = 0xb,                  /*!< Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_IC_UNLOCK = 0xc,                /*!< Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
    CCM_IC_INVAL_ALL = 0xd              /*!< Unlock and invalidate all the I-Cache lines */
} CCM_CMD_Type;

/**
 * \brief Cache Information Type
 */
typedef struct CacheInfo {
    uint32_t linesize;                  /*!< Cache Line size in bytes */
    uint32_t ways;                      /*!< Cache ways */
    uint32_t setperway;                 /*!< Cache set per way */
    uint32_t size;                      /*!< Cache total size in bytes */
} CacheInfo_Type;

#define CCM_SUEN_SUEN_Pos               0U                              /*!< CSR CCM_SUEN: SUEN bit Position */
#define CCM_SUEN_SUEN_Msk               (1UL << CCM_SUEN_SUEN_Pos)      /*!< CSR CCM_SUEN: SUEN Mask */

/**
 * \brief  Enable CCM operation in Supervisor/User Mode
 * \details
 * This function enable CCM operation in Supervisor/User Mode.
 * If enabled, CCM operations in supervisor/user mode will
 * be allowed.
 * \remarks
 * - This function can be called in M-Mode only.
 * \sa
 * - \ref DisableSUCCM
*/
__STATIC_FORCEINLINE void EnableSUCCM(void)
{
    __RV_CSR_SET(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk);
}

/**
 * \brief  Disable CCM operation in Supervisor/User Mode
 * \details
 * This function disable CCM operation in Supervisor/User Mode.
 * If not enabled, CCM operations in supervisor/user mode will
 * trigger a *illegal intruction* exception.
 * \remarks
 * - This function can be called in M-Mode only.
 * \sa
 * - \ref EnableSUCCM
*/
__STATIC_FORCEINLINE void DisableSUCCM(void)
{
    __RV_CSR_CLEAR(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk);
}

/**
 * \brief  Flush pipeline after CCM operation
 * \details
 * This function is used to flush pipeline after CCM operations
 * on Cache, it will ensure latest instructions or data can be
 * seen by pipeline.
 * \remarks
 * - This function can be called in M/S/U-Mode only.
*/
__STATIC_FORCEINLINE void FlushPipeCCM(void)
{
    __RV_CSR_WRITE(CSR_CCM_FPIPE, 0x1);
}
/** @} */ /* End of Doxygen Group NMSIS_Core_Cache */
#endif

#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)

/**
 * \defgroup NMSIS_Core_ICache      I-Cache Functions
 * \ingroup  NMSIS_Core_Cache
 * \brief    Functions that configure Instruction Cache.
 * @{
 */

/**
 * \brief  Enable ICache
 * \details
 * This function enable I-Cache
 * \remarks
 * - This function can be called in M-Mode only.
 * - This \ref CSR_MCACHE_CTL register control I Cache enable.
 * \sa
 * - \ref DisableICache
*/
__STATIC_FORCEINLINE void EnableICache(void)
{
    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}

/**
 * \brief  Disable ICache
 * \details
 * This function Disable I-Cache
 * \remarks
 * - This function can be called in M-Mode only.
 * - This \ref CSR_MCACHE_CTL register control I Cache enable.
 * \sa
 * - \ref EnableICache
 */
__STATIC_FORCEINLINE void DisableICache(void)
{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_IE);
}

/**
 * \brief  Get I-Cache Information
 * \details
 * This function get I-Cache Information
 * \remarks
 * - This function can be called in M-Mode only.
 * - You can use this function in combination with cache lines operations
 * \sa
 * - \ref GetDCacheInfo
 */
__STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info)
{
    if (info == NULL) {
        return -1;
    }
    CSR_MICFGINFO_Type csr_ccfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO);
    uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3;
    uint32_t info->ways = (1 + csr_ccfg.b.way);
    if (csr_ccfg.b.lsize == 0) {
        info->linesize = 0;
    } else {
        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
    }
    info->size = info->setperway * info->ways * info->linesize;
    return 0;
}

/**
 * \brief  Get D-Cache Information
 * \details
 * This function get D-Cache Information
 * \remarks
 * - This function can be called in M-Mode only.
 * - You can use this function in combination with cache lines operations
 * \sa
 * - \ref GetICacheInfo
 */
__STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
{
    if (info == NULL) {
        return -1;
    }
    CSR_MDCFGINFO_Type csr_ccfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO);
    uint32_t info->setperway = (1 << csr_ccfg.b.set) << 3;
    uint32_t info->ways = (1 + csr_ccfg.b.way);
    if (csr_ccfg.b.lsize == 0) {
        info->linesize = 0;
    } else {
        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
    }
    info->size = info->setperway * info->ways * info->linesize;
    return 0;
}

/**
 * \brief  Invalidate one I-Cache line specified by address in M-Mode
 * \details
 * This function unlock and invalidate one I-Cache line specified
 * by the address.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void MInvalICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL);
}

/**
 * \brief  Invalidate several I-Cache lines specified by address in M-Mode
 * \details
 * This function unlock and invalidate several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL);
        }
    }
}

/**
 * \brief  Invalidate one I-Cache line specified by address in S-Mode
 * \details
 * This function unlock and invalidate one I-Cache line specified
 * by the address.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void SInvalICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL);
}

/**
 * \brief  Invalidate several I-Cache lines specified by address in S-Mode
 * \details
 * This function unlock and invalidate several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL);
        }
    }
}

/**
 * \brief  Invalidate one I-Cache line specified by address in U-Mode
 * \details
 * This function unlock and invalidate one I-Cache line specified
 * by the address.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void UInvalICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL);
}

/**
 * \brief  Invalidate several I-Cache lines specified by address in U-Mode
 * \details
 * This function unlock and invalidate several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL);
        }
    }
}

/**
 * \brief  Lock one I-Cache line specified by address in M-Mode
 * \details
 * This function lock one I-Cache line specified by the address.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long MLockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK);
    return __RV_CSR_READ(CSR_CCM_MDATA);
}

/**
 * \brief  Lock several I-Cache lines specified by address in M-Mode
 * \details
 * This function lock several I-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_MDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Lock one I-Cache line specified by address in S-Mode
 * \details
 * This function lock one I-Cache line specified by the address.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long SLockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK);
    return __RV_CSR_READ(CSR_CCM_SDATA);
}

/**
 * \brief  Lock several I-Cache lines specified by address in S-Mode
 * \details
 * This function lock several I-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_SDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Lock one I-Cache line specified by address in U-Mode
 * \details
 * This function lock one I-Cache line specified by the address.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long ULockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK);
    return __RV_CSR_READ(CSR_CCM_UDATA);
}

/**
 * \brief  Lock several I-Cache lines specified by address in U-Mode
 * \details
 * This function lock several I-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_IC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_UDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Unlock one I-Cache line specified by address in M-Mode
 * \details
 * This function unlock one I-Cache line specified by the address.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void MUnlockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK);
}

/**
 * \brief  Unlock several I-Cache lines specified by address in M-Mode
 * \details
 * This function unlock several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_UNLOCK);
        }
    }
}

/**
 * \brief  Unlock one I-Cache line specified by address in S-Mode
 * \details
 * This function unlock one I-Cache line specified by the address.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void SUnlockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK);
}

/**
 * \brief  Unlock several I-Cache lines specified by address in S-Mode
 * \details
 * This function unlock several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_UNLOCK);
        }
    }
}

/**
 * \brief  Unlock one I-Cache line specified by address in U-Mode
 * \details
 * This function unlock one I-Cache line specified by the address.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void UUnlockICacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK);
}

/**
 * \brief  Unlock several I-Cache lines specified by address in U-Mode
 * \details
 * This function unlock several I-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_IC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_UNLOCK);
        }
    }
}

/**
 * \brief  Invalidate all I-Cache lines in M-Mode
 * \details
 * This function invalidate all I-Cache lines.
 * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void MInvalICache(void)
{
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_IC_INVAL_ALL);
}

/**
 * \brief  Invalidate all I-Cache lines in S-Mode
 * \details
 * This function invalidate all I-Cache lines.
 * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void SInvalICache(void)
{
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_IC_INVAL_ALL);
}

/**
 * \brief  Invalidate all I-Cache lines in U-Mode
 * \details
 * This function invalidate all I-Cache lines.
 * Command \ref CCM_IC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void UInvalICache(void)
{
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_IC_INVAL_ALL);
}

/** @} */ /* End of Doxygen Group NMSIS_Core_ICache */
#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */

#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
/**
 * \defgroup NMSIS_Core_DCache      D-Cache Functions
 * \ingroup  NMSIS_Core_Cache
 * \brief    Functions that configure Data Cache.
 * @{
 */
/**
 * \brief  Enable DCache
 * \details
 * This function enable D-Cache
 * \remarks
 * - This function can be called in M-Mode only.
 * - This \ref CSR_MCACHE_CTL register control D Cache enable.
 * \sa
 * - \ref DisableDCache
*/
__STATIC_FORCEINLINE void EnableDCache(void)
{
    __RV_CSR_SET(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}

/**
 * \brief  Disable DCache
 * \details
 * This function Disable D-Cache
 * \remarks
 * - This function can be called in M-Mode only.
 * - This \ref CSR_MCACHE_CTL register control D Cache enable.
 * \sa
 * - \ref EnableDCache
 */
__STATIC_FORCEINLINE void DisableDCache(void)
{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, CSR_MCACHE_CTL_DE);
}

/**
 * \brief  Invalidate one D-Cache line specified by address in M-Mode
 * \details
 * This function unlock and invalidate one D-Cache line specified
 * by the address.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void MInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL);
}

/**
 * \brief  Invalidate several D-Cache lines specified by address in M-Mode
 * \details
 * This function unlock and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL);
        }
    }
}

/**
 * \brief  Invalidate one D-Cache line specified by address in S-Mode
 * \details
 * This function unlock and invalidate one D-Cache line specified
 * by the address.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void SInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL);
}

/**
 * \brief  Invalidate several D-Cache lines specified by address in S-Mode
 * \details
 * This function unlock and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL);
        }
    }
}

/**
 * \brief  Invalidate one D-Cache line specified by address in U-Mode
 * \details
 * This function unlock and invalidate one D-Cache line specified
 * by the address.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void UInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL);
}

/**
 * \brief  Invalidate several D-Cache lines specified by address in U-Mode
 * \details
 * This function unlock and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_INVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 * \param [in]    cnt     count of cache lines to be invalidated
 */
__STATIC_FORCEINLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL);
        }
    }
}

/**
 * \brief  Flush one D-Cache line specified by address in M-Mode
 * \details
 * This function flush one D-Cache line specified by the address.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void MFlushDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB);
}

/**
 * \brief  Flush several D-Cache lines specified by address in M-Mode
 * \details
 * This function flush several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed
 * \param [in]    cnt     count of cache lines to be flushed
 */
__STATIC_FORCEINLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB);
        }
    }
}

/**
 * \brief  Flush one D-Cache line specified by address in S-Mode
 * \details
 * This function flush one D-Cache line specified by the address.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void SFlushDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB);
}

/**
 * \brief  Flush several D-Cache lines specified by address in S-Mode
 * \details
 * This function flush several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed
 * \param [in]    cnt     count of cache lines to be flushed
 */
__STATIC_FORCEINLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB);
        }
    }
}

/**
 * \brief  Flush one D-Cache line specified by address in U-Mode
 * \details
 * This function flush one D-Cache line specified by the address.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void UFlushDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB);
}

/**
 * \brief  Flush several D-Cache lines specified by address in U-Mode
 * \details
 * This function flush several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WB is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed
 * \param [in]    cnt     count of cache lines to be flushed
 */
__STATIC_FORCEINLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB);
        }
    }
}

/**
 * \brief  Flush and invalidate one D-Cache line specified by address in M-Mode
 * \details
 * This function flush and invalidate one D-Cache line specified by the address.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 */
__STATIC_FORCEINLINE void MFlushInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL);
}

/**
 * \brief  Flush and invalidate several D-Cache lines specified by address in M-Mode
 * \details
 * This function flush and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 * \param [in]    cnt     count of cache lines to be flushed and invalidated
 */
__STATIC_FORCEINLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL);
        }
    }
}

/**
 * \brief  Flush and invalidate one D-Cache line specified by address in S-Mode
 * \details
 * This function flush and invalidate one D-Cache line specified by the address.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 */
__STATIC_FORCEINLINE void SFlushInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL);
}

/**
 * \brief  Flush and invalidate several D-Cache lines specified by address in S-Mode
 * \details
 * This function flush and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 * \param [in]    cnt     count of cache lines to be flushed and invalidated
 */
__STATIC_FORCEINLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL);
        }
    }
}

/**
 * \brief  Flush and invalidate one D-Cache line specified by address in U-Mode
 * \details
 * This function flush and invalidate one D-Cache line specified by the address.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 */
__STATIC_FORCEINLINE void UFlushInvalDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL);
}

/**
 * \brief  Flush and invalidate several D-Cache lines specified by address in U-Mode
 * \details
 * This function flush and invalidate several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_WBINVAL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed and invalidated
 * \param [in]    cnt     count of cache lines to be flushed and invalidated
 */
__STATIC_FORCEINLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL);
        }
    }
}

/**
 * \brief  Lock one D-Cache line specified by address in M-Mode
 * \details
 * This function lock one D-Cache line specified by the address.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long MLockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK);
    return __RV_CSR_READ(CSR_CCM_MDATA);
}

/**
 * \brief  Lock several D-Cache lines specified by address in M-Mode
 * \details
 * This function lock several D-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_MDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Lock one D-Cache line specified by address in S-Mode
 * \details
 * This function lock one D-Cache line specified by the address.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long SLockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK);
    return __RV_CSR_READ(CSR_CCM_SDATA);
}

/**
 * \brief  Lock several D-Cache lines specified by address in S-Mode
 * \details
 * This function lock several D-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_SDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Lock one D-Cache line specified by address in U-Mode
 * \details
 * This function lock one D-Cache line specified by the address.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long ULockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK);
    return __RV_CSR_READ(CSR_CCM_UDATA);
}

/**
 * \brief  Lock several D-Cache lines specified by address in U-Mode
 * \details
 * This function lock several D-Cache lines specified by the address
 * and line count.
 * Command \ref CCM_DC_LOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be locked
 * \param [in]    cnt     count of cache lines to be locked
 * \return result of CCM lock operation, see enum \ref CCM_OP_FINFO
 */
__STATIC_FORCEINLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_LOCK);
        }
        return __RV_CSR_READ(CSR_CCM_UDATA);
    } else {
        return 0;
    }
}

/**
 * \brief  Unlock one D-Cache line specified by address in M-Mode
 * \details
 * This function unlock one D-Cache line specified by the address.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void MUnlockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK);
}

/**
 * \brief  Unlock several D-Cache lines specified by address in M-Mode
 * \details
 * This function unlock several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_MBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_UNLOCK);
        }
    }
}

/**
 * \brief  Unlock one D-Cache line specified by address in S-Mode
 * \details
 * This function unlock one D-Cache line specified by the address.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void SUnlockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK);
}

/**
 * \brief  Unlock several D-Cache lines specified by address in S-Mode
 * \details
 * This function unlock several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_SBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_UNLOCK);
        }
    }
}

/**
 * \brief  Unlock one D-Cache line specified by address in U-Mode
 * \details
 * This function unlock one D-Cache line specified by the address.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be unlocked
 */
__STATIC_FORCEINLINE void UUnlockDCacheLine(unsigned long addr)
{
    __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK);
}

/**
 * \brief  Unlock several D-Cache lines specified by address in U-Mode
 * \details
 * This function unlock several D-Cache lines specified
 * by the address and line count.
 * Command \ref CCM_DC_UNLOCK is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be unlocked
 * \param [in]    cnt     count of cache lines to be unlocked
 */
__STATIC_FORCEINLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
{
    if (cnt > 0) {
        unsigned long i;
        __RV_CSR_WRITE(CSR_CCM_UBEGINADDR, addr);
        for (i = 0; i < cnt; i++) {
            __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_UNLOCK);
        }
    }
}

/**
 * \brief  Invalidate all D-Cache lines in M-Mode
 * \details
 * This function invalidate all D-Cache lines.
 * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void MInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_INVAL_ALL);
}

/**
 * \brief  Invalidate all D-Cache lines in S-Mode
 * \details
 * This function invalidate all D-Cache lines.
 * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void SInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_INVAL_ALL);
}

/**
 * \brief  Invalidate all D-Cache lines in U-Mode
 * \details
 * This function invalidate all D-Cache lines.
 * In U-Mode, this operation will be automatically
 * translated to flush and invalidate operations by hardware.
 * Command \ref CCM_DC_INVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be invalidated
 */
__STATIC_FORCEINLINE void UInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_INVAL_ALL);
}

/**
 * \brief  Flush all D-Cache lines in M-Mode
 * \details
 * This function flush all D-Cache lines.
 * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void MFlushDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WB_ALL);
}

/**
 * \brief  Flush all D-Cache lines in S-Mode
 * \details
 * This function flush all D-Cache lines.
 * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void SFlushDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WB_ALL);
}

/**
 * \brief  Flush all D-Cache lines in U-Mode
 * \details
 * This function flush all D-Cache lines.
 * Command \ref CCM_DC_WB_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed
 */
__STATIC_FORCEINLINE void UFlushDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WB_ALL);
}

/**
 * \brief  Flush and invalidate all D-Cache lines in M-Mode
 * \details
 * This function flush and invalidate all D-Cache lines.
 * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_MCOMMAND.
 * \remarks
 * This function must be executed in M-Mode only.
 * \param [in]    addr    start address to be flushed and locked
 */
__STATIC_FORCEINLINE void MFlushInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_MCOMMAND, CCM_DC_WBINVAL_ALL);
}

/**
 * \brief  Flush and invalidate all D-Cache lines in S-Mode
 * \details
 * This function flush and invalidate all D-Cache lines.
 * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_SCOMMAND.
 * \remarks
 * This function must be executed in M/S-Mode only.
 * \param [in]    addr    start address to be flushed and locked
 */
__STATIC_FORCEINLINE void SFlushInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_SCOMMAND, CCM_DC_WBINVAL_ALL);
}

/**
 * \brief  Flush and invalidate all D-Cache lines in U-Mode
 * \details
 * This function flush and invalidate all D-Cache lines.
 * Command \ref CCM_DC_WBINVAL_ALL is written to CSR \ref CSR_CCM_UCOMMAND.
 * \remarks
 * This function must be executed in M/S/U-Mode only.
 * \param [in]    addr    start address to be flushed and locked
 */
__STATIC_FORCEINLINE void UFlushInvalDCache(void)
{
    __RV_CSR_WRITE(CSR_CCM_UCOMMAND, CCM_DC_WBINVAL_ALL);
}

/** @} */ /* End of Doxygen Group NMSIS_Core_DCache */
#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */

#ifdef __cplusplus
}
#endif
#endif /** __CORE_FEATURE_CACHE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_dsp.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_DSP__
#define __CORE_FEATURE_DSP__

/*!
 * @file     core_feature_dsp.h
 * @brief    DSP feature API header file for Nuclei N/NX Core
 */
/*
 * DSP Feature Configuration Macro:
 * 1. __DSP_PRESENT:  Define whether Digital Signal Processing Unit(DSP) is present or not
 *   * 0: Not present
 *   * 1: Present
 */
#ifdef __cplusplus
 extern "C" {
#endif

#if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1)

/* ###########################  CPU SIMD DSP Intrinsic Functions ########################### */
/**
 * \defgroup NMSIS_Core_DSP_Intrinsic   Intrinsic Functions for SIMD Instructions
 * \ingroup  NMSIS_Core
 * \brief    Functions that generate RISC-V DSP SIMD instructions.
 * \details
 *
 * The following functions generate specified RISC-V SIMD instructions that cannot be directly accessed by compiler.
 * * **DSP ISA Extension Instruction Summary**
 *   + **Shorthand Definitions**
 *     - r.H == rH1: r[31:16], r.L == r.H0: r[15:0]
 *     - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0]
 *     - r.B[x]: r[(x*8+7):(x*8+0)]
 *     - r.H[x]: r[(x*16+7):(x*16+0)]
 *     - r.W[x]: r[(x*32+31):(x*32+0)]
 *     - r[xU]: the upper 32-bit of a 64-bit number; xU represents the GPR number that contains this upper part 32-bit value.
 *     - r[xL]: the lower 32-bit of a 64-bit number; xL represents the GPR number that contains this lower part 32-bit value.
 *     - r[xU].r[xL]: a 64-bit number that is formed from a pair of GPRs.
 *     - s>>: signed arithmetic right shift:
 *     - u>>: unsigned logical right shift
 *     - SAT.Qn(): Saturate to the range of [-2^n, 2^n-1], if saturation happens, set PSW.OV.
 *     - SAT.Um(): Saturate to the range of [0, 2^m-1], if saturation happens, set PSW.OV.
 *     - RUND(): Indicate `rounding`, i.e., add 1 to the most significant discarded bit for right shift or MSW-type multiplication instructions.
 *     - Sign or Zero Extending functions:
 *       - SEm(data): Sign-Extend data to m-bit.:
 *       - ZEm(data): Zero-Extend data to m-bit.
 *     - ABS(x): Calculate the absolute value of `x`.
 *     - CONCAT(x,y): Concatinate `x` and `y` to form a value.
 *     - u<: Unsinged less than comparison.
 *     - u<=: Unsinged less than & equal comparison.
 *     - u>: Unsinged greater than comparison.
 *     - s*: Signed multiplication.
 *     - u*: Unsigned multiplication.
 *
 *   @{
 */
/** @} */ /* End of Doxygen Group NMSIS_Core_DSP_Intrinsic */


/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS      SIMD Data Processing Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    SIMD Data Processing Instructions
 * \details
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB      SIMD 16-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Add/Subtract Instructions
 * \details
 * Based on the combination of the types of the two 16-bit arithmetic operations, the SIMD 16-bit
 * add/subtract instructions can be classified into 6 main categories: Addition (two 16-bit addition),
 * Subtraction (two 16-bit subtraction), Crossed Add & Sub (one addition and one subtraction), and
 * Crossed Sub & Add (one subtraction and one addition), Straight Add & Sub (one addition and one
 * subtraction), and Straight Sub & Add (one subtraction and one addition).
 * Based on the way of how an overflow condition is handled, the SIMD 16-bit add/subtract
 * instructions can be classified into 5 groups: Wrap-around (dropping overflow), Signed Halving
 * (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed Saturation (clipping overflow),
 * and Unsigned Saturation.
 * Together, there are 30 SIMD 16-bit add/subtract instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB      SIMD 8-bit Addition & Subtraction Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Addition & Subtraction Instructions
 * \details
 * Based on the types of the four 8-bit arithmetic operations, the SIMD 8-bit add/subtract instructions
 * can be classified into 2 main categories: Addition (four 8-bit addition), and Subtraction (four 8-bit
 * subtraction).
 * Based on the way of how an overflow condition is handled for singed or unsigned operation, the
 * SIMD 8-bit add/subtract instructions can be classified into 5 groups: Wrap-around (dropping
 * overflow), Signed Halving (keeping overflow by dropping 1 LSB bit), Unsigned Halving, Signed
 * Saturation (clipping overflow), and Unsigned Saturation.
 * Together, there are 10 SIMD 8-bit add/subtract instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT      SIMD 16-bit Shift Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Shift Instructions
 * \details
 * there are 14 SIMD 16-bit shift instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT      SIMD 8-bit Shift Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Shift Instructions
 * \details
 *  there are 14 SIMD 8-bit shift instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP      SIMD 16-bit Compare Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Compare Instructions
 * \details
 *  there are 5 SIMD 16-bit Compare instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP      SIMD 8-bit Compare Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Compare Instructions
 * \details
 *  there are 5  SIMD 8-bit Compare instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY      SIMD 16-bit Multiply Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Multiply Instructions
 * \details
 * there are 6 SIMD 16-bit Multiply instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY      SIMD 8-bit Multiply Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Multiply Instructions
 * \details
 *  there are 6 SIMD 8-bit Multiply instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC      SIMD 16-bit Miscellaneous Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Miscellaneous Instructions
 * \details
 *  there are 10 SIMD 16-bit Misc instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC      SIMD 8-bit Miscellaneous Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Miscellaneous Instructions
 * \details
 *  there are 10 SIMD 8-bit Miscellaneous instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK      SIMD 8-bit Unpacking Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_SIMD_DATA_PROCESS
 * \brief    SIMD 8-bit Unpacking Instructions
 * \details
 *  there are 8 SIMD 8-bit Unpacking instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD      Non-SIMD Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    Non-SIMD Instructions
 * \details
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU      Non-SIMD Q15 saturation ALU Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
 * \brief    Non-SIMD Q15 saturation ALU Instructions
 * \details
 * there are 7 Non-SIMD Q15 saturation ALU Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU      Non-SIMD Q31 saturation ALU Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
 * \brief    Non-SIMD Q31 saturation ALU Instructions
 * \details
 *  there are Non-SIMD Q31 saturation ALU Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION      32-bit Computation Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
 * \brief    32-bit Computation Instructions
 * \details
 * there are 8 32-bit Computation Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC      OV (Overflow) flag Set/Clear Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
 * \brief    OV (Overflow) flag Set/Clear Instructions
 * \details
 * The following table lists the user instructions related to Overflow (OV) flag manipulation. there are 2 OV (Overflow) flag Set/Clear Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC      Non-SIMD Miscellaneous Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NON_SIMD
 * \brief    Non-SIMD Miscellaneous Instructions
 * \details
 * There are 13 Miscellaneous Instructions here.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS      Partial-SIMD Data Processing Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    Partial-SIMD Data Processing Instructions
 * \details
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK      SIMD 16-bit Packing Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    SIMD 16-bit Packing Instructions
 * \details
 * there are 4 SIMD16-bit Packing Instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC      Signed MSW 32x32 Multiply and Add Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    Signed MSW 32x32 Multiply and Add Instructions
 * \details
 *  there are 8 Signed MSW 32x32 Multiply and Add Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC      Signed MSW 32x16 Multiply and Add Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    Signed MSW 32x16 Multiply and Add Instructions
 * \details
 * there are 15 Signed MSW 32x16 Multiply and Add Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB      Signed 16-bit Multiply 32-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    Signed 16-bit Multiply 32-bit Add/Subtract Instructions
 * \details
 *  there are 18 Signed 16-bit Multiply 32-bit Add/Subtract Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB      Signed 16-bit Multiply 64-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    Signed 16-bit Multiply 64-bit Add/Subtract Instructions
 * \details
 *  there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC      Partial-SIMD Miscellaneous Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    Partial-SIMD Miscellaneous Instructions
 * \details
 *  there are  7 Partial-SIMD Miscellaneous Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD      8-bit Multiply with 32-bit Add Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_PART_SIMD_DATA_PROCESS
 * \brief    8-bit Multiply with 32-bit Add Instructions
 * \details
 * there are  3 8-bit Multiply with 32-bit Add Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_64B_PROFILE      64-bit Profile Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    64-bit Profile Instructions
 * \details
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB      64-bit Addition & Subtraction Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
 * \brief    64-bit Addition & Subtraction Instructions
 * \details
 * there are 10 64-bit Addition & Subtraction Instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB      32-bit Multiply with 64-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
 * \brief    32-bit Multiply with 64-bit Add/Subtract Instructions
 * \details
 *  there are 32-bit Multiply 64-bit Add/Subtract Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB      Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_64B_PROFILE
 * \brief    Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
 * \details
 * there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_ONLY      RV64 Only Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    RV64 Only Instructions
 * \details
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB      (RV64 Only) SIMD 32-bit Add/Subtract Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) SIMD 32-bit Add/Subtract Instructions
 * \details
 * The following tables list instructions that are only present in RV64.
 * There are 30 SIMD 32-bit addition or subtraction instructions.there are 4 SIMD16-bit Packing Instructions.
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT      (RV64 Only) SIMD 32-bit Shift Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) SIMD 32-bit Shift Instructions
 * \details
 *  there are 14 (RV64 Only) SIMD 32-bit Shift Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC      (RV64 Only) SIMD 32-bit Miscellaneous Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) SIMD 32-bit Miscellaneous Instructions
 * \details
 * there are 5  (RV64 Only) SIMD 32-bit Miscellaneous Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT      (RV64 Only) SIMD Q15 Saturating Multiply Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) SIMD Q15 Saturating Multiply Instructions
 * \details
 *  there are 9 (RV64 Only) SIMD Q15 saturating Multiply Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT      (RV64 Only) 32-bit Multiply Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) 32-bit Multiply Instructions
 * \details
 *  there is 3 RV64 Only) 32-bit Multiply Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD      (RV64 Only) 32-bit Multiply & Add Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) 32-bit Multiply & Add Instructions
 * \details
 *  there are  3 (RV64 Only) 32-bit Multiply & Add Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC      (RV64 Only) 32-bit Parallel Multiply & Add Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) 32-bit Parallel Multiply & Add Instructions
 * \details
 * there are 12 (RV64 Only) 32-bit Parallel Multiply & Add Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT      (RV64 Only) Non-SIMD 32-bit Shift Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    (RV64 Only) Non-SIMD 32-bit Shift Instructions
 * \details
 *  there are 1  (RV64 Only) Non-SIMD 32-bit Shift Instructions
 */

/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK      32-bit Packing Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic_RV64_ONLY
 * \brief    32-bit Packing Instructions
 * \details
 *  There are four 32-bit packing instructions here
 */

/* ===== Inline Function Start for 3.1. ADD8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief ADD8 (SIMD 8-bit Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * ADD8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit integer element additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 8-bit integer elements in Rs1 with the 8-bit integer elements
 * in Rs2, and then writes the 8-bit element results to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned addition.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = Rs1.B[x] + Rs2.B[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ADD8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("add8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.1. ADD8 ===== */

/* ===== Inline Function Start for 3.2. ADD16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief ADD16 (SIMD 16-bit Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * ADD16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 16-bit integer elements in Rs1 with the 16-bit integer
 * elements in Rs2, and then writes the 16-bit element results to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned addition.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = Rs1.H[x] + Rs2.H[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ADD16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("add16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.2. ADD16 ===== */

/* ===== Inline Function Start for 3.3. ADD64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief ADD64 (64-bit Addition)
 * \details
 * **Type**: 64-bit Profile
 *
 * **Syntax**:\n
 * ~~~
 * ADD64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add two 64-bit signed or unsigned integers.
 *
 * **RV32 Description**:\n
 * This instruction adds the 64-bit integer of an even/odd pair of registers specified
 * by Rs1(4,1) with the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1), and then
 * writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction has the same behavior as the ADD instruction in RV64I.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned addition.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 *  t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 *  a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 *  b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 *  R[t_H].R[t_L] = R[a_H].R[a_L] + R[b_H].R[b_L];
 * RV64:
 *  Rd = Rs1 + Rs2;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_ADD64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("add64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.3. ADD64 ===== */

/* ===== Inline Function Start for 3.4. AVE ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief AVE (Average with Rounding)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * AVE Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Calculate the average of the contents of two general registers.
 *
 * **Description**:\n
 * This instruction calculates the average value of two signed integers stored in Rs1 and
 * Rs2, rounds up a half-integer result to the nearest integer, and writes the result to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Sum = CONCAT(Rs1[MSB],Rs1[MSB:0]) + CONCAT(Rs2[MSB],Rs2[MSB:0]) + 1;
 * Rd = Sum[(MSB+1):1];
 * for RV32: MSB=31,
 * for RV64: MSB=63
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_AVE(long a, long b)
{
    register long result;
    __ASM volatile("ave %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.4. AVE ===== */

/* ===== Inline Function Start for 3.5. BITREV ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief BITREV (Bit Reverse)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * BITREV Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Reverse the bit positions of the source operand within a specified width starting from bit
 * 0. The reversed width is a variable from a GPR.
 *
 * **Description**:\n
 * This instruction reverses the bit positions of the content of Rs1. The reversed bit width
 * is calculated as Rs2[4:0]+1 (RV32) or Rs2[5:0]+1 (RV64). The upper bits beyond the reversed width
 * are filled with zeros. After the bit reverse operation, the result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * msb = Rs2[4:0]; (for RV32)
 * msb = Rs2[5:0]; (for RV64)
 * rev[0:msb] = Rs1[msb:0];
 * Rd = ZE(rev[msb:0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_BITREV(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("bitrev %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.5. BITREV ===== */

/* ===== Inline Function Start for 3.6. BITREVI ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief BITREVI (Bit Reverse Immediate)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * (RV32) BITREVI Rd, Rs1, imm[4:0]
 * (RV64) BITREVI Rd, Rs1, imm[5:0]
 * ~~~
 *
 * **Purpose**:\n
 * Reverse the bit positions of the source operand within a specified width starting from bit
 * 0. The reversed width is an immediate value.
 *
 * **Description**:\n
 * This instruction reverses the bit positions of the content of Rs1. The reversed bit width
 * is calculated as imm[4:0]+1 (RV32) or imm[5:0]+1 (RV64). The upper bits beyond the reversed width
 * are filled with zeros. After the bit reverse operation, the result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * msb = imm[4:0]; (RV32)
 * msb = imm[5:0]; (RV64)
 * rev[0:msb] = Rs1[msb:0];
 * Rd = ZE(rev[msb:0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_BITREVI(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("bitrevi %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.6. BITREVI ===== */

/* ===== Inline Function Start for 3.7. BPICK ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief BPICK (Bit-wise Pick)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * BPICK Rd, Rs1, Rs2, Rc
 * ~~~
 *
 * **Purpose**:\n
 * Select from two source operands based on a bit mask in the third operand.
 *
 * **Description**:\n
 * This instruction selects individual bits from Rs1 or Rs2, based on the bit mask value in
 * Rc. If a bit in Rc is 1, the corresponding bit is from Rs1; otherwise, the corresponding bit is from Rs2.
 * The selection results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd[x] = Rc[x]? Rs1[x] : Rs2[x];
 * for RV32, x=31...0
 * for RV64, x=63...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \param [in]  c    unsigned long type of value stored in c
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_BPICK(unsigned long a, unsigned long b, unsigned long c)
{
    register unsigned long result;
    __ASM volatile("bpick %0, %1, %2, %3" : "=r"(result) : "r"(a), "r"(b), "r"(c));
    return result;
}
/* ===== Inline Function End for 3.7. BPICK ===== */

/* ===== Inline Function Start for 3.8. CLROV ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC
 * \brief CLROV (Clear OV flag)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * CLROV # pseudo mnemonic
 * ~~~
 *
 * **Purpose**:\n
 * This pseudo instruction is an alias to `CSRRCI x0, ucode, 1` instruction.
 *
 *
 */
__STATIC_FORCEINLINE void __RV_CLROV(void)
{
    __ASM volatile("clrov ");
}
/* ===== Inline Function End for 3.8. CLROV ===== */

/* ===== Inline Function Start for 3.9. CLRS8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief CLRS8 (SIMD 8-bit Count Leading Redundant Sign)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLRS8 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of redundant sign bits of the 8-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the bits next to the sign bits of the 8-bit elements of Rs1, this instruction
 * counts the number of redundant sign bits and writes the result to the corresponding 8-bit elements
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.B[x];
 * cnt[x] = 0;
 * for (i = 6 to 0) {
 *   if (snum[x](i) == snum[x](7)) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.B[x] = cnt[x];
 * for RV32: x=3...0
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLRS8(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clrs8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.9. CLRS8 ===== */

/* ===== Inline Function Start for 3.10. CLRS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief CLRS16 (SIMD 16-bit Count Leading Redundant Sign)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLRS16 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of redundant sign bits of the 16-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the bits next to the sign bits of the 16-bit elements of Rs1, this
 * instruction counts the number of redundant sign bits and writes the result to the corresponding 16-
 * bit elements of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.H[x];
 * cnt[x] = 0;
 * for (i = 14 to 0) {
 *   if (snum[x](i) == snum[x](15)) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.H[x] = cnt[x];
 * for RV32: x=1...0
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLRS16(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clrs16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.10. CLRS16 ===== */

/* ===== Inline Function Start for 3.11. CLRS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief CLRS32 (SIMD 32-bit Count Leading Redundant Sign)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLRS32 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of redundant sign bits of the 32-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the bits next to the sign bits of the 32-bit elements of Rs1, this
 * instruction counts the number of redundant sign bits and writes the result to the corresponding 32-
 * bit elements of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.W[x];
 * cnt[x] = 0;
 * for (i = 30 to 0) {
 *   if (snum[x](i) == snum[x](31)) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.W[x] = cnt[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLRS32(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clrs32 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.11. CLRS32 ===== */

/* ===== Inline Function Start for 3.12. CLO8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief CLO8 (SIMD 8-bit Count Leading One)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLO8 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading one bits of the 8-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction
 * counts the number of leading one bits and writes the results to the corresponding 8-bit elements of
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.B[x];
 * cnt[x] = 0;
 *   for (i = 7 to 0) {
 *   if (snum[x](i) == 1) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.B[x] = cnt[x];
 * for RV32: x=3...0
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLO8(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clo8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.12. CLO8 ===== */

/* ===== Inline Function Start for 3.13. CLO16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief CLO16 (SIMD 16-bit Count Leading One)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLO16 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading one bits of the 16-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction
 * counts the number of leading one bits and writes the results to the corresponding 16-bit elements
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.H[x];
 * cnt[x] = 0;
 * for (i = 15 to 0) {
 *   if (snum[x](i) == 1) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.H[x] = cnt[x];
 * for RV32: x=1...0
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLO16(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clo16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.13. CLO16 ===== */

/* ===== Inline Function Start for 3.14. CLO32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief CLO32 (SIMD 32-bit Count Leading One)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLO32 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading one bits of the 32-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction
 * counts the number of leading one bits and writes the results to the corresponding 32-bit elements
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.W[x];
 * cnt[x] = 0;
 * for (i = 31 to 0) {
 *   if (snum[x](i) == 1) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.W[x] = cnt[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLO32(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clo32 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.14. CLO32 ===== */

/* ===== Inline Function Start for 3.15. CLZ8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief CLZ8 (SIMD 8-bit Count Leading Zero)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLZ8 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading zero bits of the 8-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 8-bit elements of Rs1, this instruction
 * counts the number of leading zero bits and writes the results to the corresponding 8-bit elements of
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.B[x];
 * cnt[x] = 0;
 * for (i = 7 to 0) {
 *   if (snum[x](i) == 0) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.B[x] = cnt[x];
 * for RV32: x=3...0
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLZ8(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clz8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.15. CLZ8 ===== */

/* ===== Inline Function Start for 3.16. CLZ16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief CLZ16 (SIMD 16-bit Count Leading Zero)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLZ16 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading zero bits of the 16-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 16-bit elements of Rs1, this instruction
 * counts the number of leading zero bits and writes the results to the corresponding 16-bit elements
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.H[x];
 * cnt[x] = 0;
 * for (i = 15 to 0) {
 *   if (snum[x](i) == 0) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.H[x] = cnt[x];
 * for RV32: x=1...0
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLZ16(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clz16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.16. CLZ16 ===== */

/* ===== Inline Function Start for 3.17. CLZ32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief CLZ32 (SIMD 32-bit Count Leading Zero)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CLZ32 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Count the number of leading zero bits of the 32-bit elements of a general register.
 *
 * **Description**:\n
 * Starting from the most significant bits of the 32-bit elements of Rs1, this instruction
 * counts the number of leading zero bits and writes the results to the corresponding 32-bit elements
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * snum[x] = Rs1.W[x];
 * cnt[x] = 0;
 * for (i = 31 to 0) {
 *   if (snum[x](i) == 0) {
 *     cnt[x] = cnt[x] + 1;
 *   } else {
 *     break;
 *   }
 * }
 * Rd.W[x] = cnt[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CLZ32(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("clz32 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.17. CLZ32 ===== */

/* ===== Inline Function Start for 3.18. CMPEQ8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
 * \brief CMPEQ8 (SIMD 8-bit Integer Compare Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CMPEQ8 Rs, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit integer elements equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit integer elements in Rs1 with the 8-bit integer
 * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFF; otherwise, the result is
 * 0x0. The 8-bit element comparison results are written to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned numbers.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] == Rs2.B[x])? 0xff : 0x0;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CMPEQ8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("cmpeq8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.18. CMPEQ8 ===== */

/* ===== Inline Function Start for 3.19. CMPEQ16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
 * \brief CMPEQ16 (SIMD 16-bit Integer Compare Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CMPEQ16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer elements equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit integer elements in Rs1 with the 16-bit integer
 * elements in Rs2 to see if they are equal. If they are equal, the result is 0xFFFF; otherwise, the result
 * is 0x0. The 16-bit element comparison results are written to Rt.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned numbers.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] == Rs2.H[x])? 0xffff : 0x0;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CMPEQ16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("cmpeq16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.19. CMPEQ16 ===== */

/* ===== Inline Function Start for 3.20. CRAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief CRAS16 (SIMD 16-bit Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CRAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit
 * chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with
 * the 16-bit integer element in [15:0] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit
 * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [31:16] of 32-bit chunks in
 * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32-
 * bit chunks in Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][15:0];
 * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][31:16];
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CRAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("cras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.20. CRAS16 ===== */

/* ===== Inline Function Start for 3.21. CRSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief CRSA16 (SIMD 16-bit Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * CRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit
 * chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit integer element in [15:0] of 32-bit chunks in Rs2
 * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of
 * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [31:16] of 32-bit chunks
 * in Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to
 * [15:0] of 32-bit chunks in Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][15:0];
 * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][31:16];
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CRSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("crsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.21. CRSA16 ===== */

/* ===== Inline Function Start for 3.22. INSB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief INSB (Insert Byte)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * (RV32) INSB Rd, Rs1, imm[1:0]
 * (RV64) INSB Rd, Rs1, imm[2:0]
 * ~~~
 *
 * **Purpose**:\n
 * Insert byte 0 of a 32-bit or 64-bit register into one of the byte elements of another register.
 *
 * **Description**:\n
 * This instruction inserts byte 0 of Rs1 into byte `imm[1:0]` (RV32) or `imm[2:0]` (RV64)
 * of Rd.
 *
 * **Operations**:\n
 * ~~~
 * bpos = imm[1:0]; (RV32)
 * bpos = imm[2:0]; (RV64)
 * Rd.B[bpos] = Rs1.B[0]
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_INSB(t, a, b)    \
    ({    \
        register unsigned long __t = (unsigned long)(t);    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("insb %0, %1, %2" : "+r"(__t) : "r"(__a), "K"(b));    \
        __t;    \
    })
/* ===== Inline Function End for 3.22. INSB ===== */

/* ===== Inline Function Start for 3.23. KABS8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief KABS8 (SIMD 8-bit Saturating Absolute)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KABS8 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of 8-bit signed integer elements simultaneously.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of 8-bit signed integer elements stored
 * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates
 * 0x7f as the output and sets the OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.B[x];
 * if (src == 0x80) {
 *   src = 0x7f;
 *   OV = 1;
 * } else if (src[7] == 1)
 *   src = -src;
 * }
 * Rd.B[x] = src;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KABS8(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("kabs8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.23. KABS8 ===== */

/* ===== Inline Function Start for 3.24. KABS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief KABS16 (SIMD 16-bit Saturating Absolute)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KABS16 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of 16-bit signed integer elements simultaneously.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of 16-bit signed integer elements stored
 * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction
 * generates 0x7fff as the output and sets the OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.H[x];
 * if (src == 0x8000) {
 *   src = 0x7fff;
 *   OV = 1;
 * } else if (src[15] == 1)
 *   src = -src;
 * }
 * Rd.H[x] = src;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KABS16(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("kabs16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.24. KABS16 ===== */

/* ===== Inline Function Start for 3.25. KABSW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KABSW (Scalar 32-bit Absolute Value with Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KABSW Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of a signed 32-bit integer in a general register.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of a signed 32-bit integer stored in Rs1.
 * The result is sign-extended (for RV64) and written to Rd. This instruction with the minimum
 * negative integer input of 0x80000000 will produce a saturated output of maximum positive integer
 * of 0x7fffffff and the OV flag will be set to 1.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs1.W[0] >= 0) {
 *   res = Rs1.W[0];
 * } else {
 *   If (Rs1.W[0] == 0x80000000) {
 *     res = 0x7fffffff;
 *     OV = 1;
 *   } else {
 *     res = -Rs1.W[0];
 *   }
 * }
 * Rd = SE32(res);
 * ~~~
 *
 * \param [in]  a    signed long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KABSW(signed long a)
{
    register unsigned long result;
    __ASM volatile("kabsw %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.25. KABSW ===== */

/* ===== Inline Function Start for 3.26. KADD8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief KADD8 (SIMD 8-bit Signed Saturating Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KADD8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
 * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they
 * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.B[x] + Rs2.B[x];
 * if (res[x] > 127) {
 *   res[x] = 127;
 *   OV = 1;
 * } else if (res[x] < -128) {
 *   res[x] = -128;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KADD8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.26. KADD8 ===== */

/* ===== Inline Function Start for 3.27. KADD16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KADD16 (SIMD 16-bit Signed Saturating Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KADD16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
 * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1),
 * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] + Rs2.H[x];
 * if (res[x] > 32767) {
 *   res[x] = 32767;
 *   OV = 1;
 * } else if (res[x] < -32768) {
 *   res[x] = -32768;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KADD16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.27. KADD16 ===== */

/* ===== Inline Function Start for 3.28. KADD64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief KADD64 (64-bit Signed Saturating Addition)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * KADD64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add two 64-bit signed integers. The result is saturated to the Q63 range.
 *
 * **RV32 Description**:\n
 * This instruction adds the 64-bit signed integer of an even/odd pair of registers
 * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by
 * Rs2(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the
 * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers
 * specified by Rd(4,1).
 * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed
 * integer in Rs2. If the result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the
 * range and the OV bit is set to 1. The saturated result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 *  t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 *  a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 *  b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 *  result = R[a_H].R[a_L] + R[b_H].R[b_L];
 *  if (result > (2^63)-1) {
 *    result = (2^63)-1; OV = 1;
 *  } else if (result < -2^63) {
 *    result = -2^63; OV = 1;
 *  }
 *  R[t_H].R[t_L] = result;
 * RV64:
 *  result = Rs1 + Rs2;
 *  if (result > (2^63)-1) {
 *    result = (2^63)-1; OV = 1;
 *  } else if (result < -2^63) {
 *    result = -2^63; OV = 1;
 *  }
 *  Rd = result;
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    long long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_KADD64(long long a, long long b)
{
    register long long result;
    __ASM volatile("kadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.28. KADD64 ===== */

/* ===== Inline Function Start for 3.29. KADDH ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief KADDH (Signed Addition with Q15 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KADDH Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add the signed lower 32-bit content of two registers with Q15 saturation.
 *
 * **Description**:\n
 * The signed lower 32-bit content of Rs1 is added with the signed lower 32-bit content of
 * Rs2. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then sign-
 * extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] + Rs2.W[0];
 * if (tmp > 32767) {
 *   res = 32767;
 *   OV = 1;
 * } else if (tmp < -32768) {
 *   res = -32768;
 *   OV = 1
 * } else {
 *   res = tmp;
 * }
 * Rd = SE(tmp[15:0]);
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KADDH(int a, int b)
{
    register long result;
    __ASM volatile("kaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.29. KADDH ===== */

/* ===== Inline Function Start for 3.30. KADDW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KADDW (Signed Addition with Q31 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KADDW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add the lower 32-bit signed content of two registers with Q31 saturation.
 *
 * **Description**:\n
 * The lower 32-bit signed content of Rs1 is added with the lower 32-bit signed content of
 * Rs2. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then sign-
 * extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] + Rs2.W[0];
 * if (tmp > (2^31)-1) {
 *   res = (2^31)-1;
 *   OV = 1;
 * } else if (tmp < -2^31) {
 *   res = -2^31;
 *   OV = 1
 * } else {
 *   res = tmp;
 * }
 * Rd = res[31:0]; // RV32
 * Rd = SE(res[31:0]) // RV64
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KADDW(int a, int b)
{
    register long result;
    __ASM volatile("kaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.30. KADDW ===== */

/* ===== Inline Function Start for 3.31. KCRAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KCRAS16 (SIMD 16-bit Signed Saturating Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KCRAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating addition and 16-bit signed integer element
 * saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-
 * bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it
 * subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed
 * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
 * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for
 * subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0];
 * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16];
 * for (res in [res1, res2]) {
 *   if (res > (2^15)-1) {
 *     res = (2^15)-1;
 *     OV = 1;
 *   } else if (res < -2^15) {
 *     res = -2^15;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KCRAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.31. KCRAS16 ===== */

/* ===== Inline Function Start for 3.32. KCRSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KCRSA16 (SIMD 16-bit Signed Saturating Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KCRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element
 * saturating addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit
 * chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks
 * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it
 * adds the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2 with the 16-bit signed
 * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
 * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd
 * for addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0];
 * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16];
 * for (res in [res1, res2]) {
 *   if (res > (2^15)-1) {
 *     res = (2^15)-1;
 *     OV = 1;
 *   } else if (res < -2^15) {
 *     res = -2^15;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KCRSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.32. KCRSA16 ===== */

/* ===== Inline Function Start for 3.33.1. KDMBB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMBB (Signed Saturating Double Multiply B16 x B16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
 * written into the destination register for RV32 or sign-extended to 64-bits and written into the
 * destination register for RV64. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
 * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
 * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 *   OV = 1;
 * }
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMBB(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("kdmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.33.1. KDMBB ===== */

/* ===== Inline Function Start for 3.33.2. KDMBT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMBT (Signed Saturating Double Multiply B16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
 * written into the destination register for RV32 or sign-extended to 64-bits and written into the
 * destination register for RV64. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
 * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
 * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 *   OV = 1;
 * }
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMBT(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("kdmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.33.2. KDMBT ===== */

/* ===== Inline Function Start for 3.33.3. KDMTT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMTT (Signed Saturating Double Multiply T16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result. The result is
 * written into the destination register for RV32 or sign-extended to 64-bits and written into the
 * destination register for RV64. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then written into Rd (sign-extended in
 * RV64). When both the two Q15 inputs are 0x8000, saturation will happen. The result will be
 * saturated to 0x7FFFFFFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   Rd = resQ31; // RV32
 *   Rd = SE(resQ31); // RV64
 *   OV = 1;
 * }
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMTT(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("kdmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.33.3. KDMTT ===== */

/* ===== Inline Function Start for 3.34.1. KDMABB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMABB (Signed Saturating Double Multiply Addition B16 x B16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
 * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
 * result into the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV flag is set to 1. The result after saturation is written to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd = Rd + resQ31; // RV32
 * resadd = Rd.W[0] + resQ31; // RV64
 * if (resadd > (2^31)-1) {
 *   resadd = (2^31)-1;
 *   OV = 1;
 * } else if (resadd < -2^31) {
 *   resadd = -2^31;
 *   OV = 1;
 * }
 * Rd = resadd; // RV32
 * Rd = SE(resadd); // RV64
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMABB(long t, unsigned int a, unsigned int b)
{
    __ASM volatile("kdmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.34.1. KDMABB ===== */

/* ===== Inline Function Start for 3.34.2. KDMABT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMABT (Signed Saturating Double Multiply Addition B16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
 * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
 * result into the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV flag is set to 1. The result after saturation is written to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd = Rd + resQ31; // RV32
 * resadd = Rd.W[0] + resQ31; // RV64
 * if (resadd > (2^31)-1) {
 *   resadd = (2^31)-1;
 *   OV = 1;
 * } else if (resadd < -2^31) {
 *   resadd = -2^31;
 *   OV = 1;
 * }
 * Rd = resadd; // RV32
 * Rd = SE(resadd); // RV64
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMABT(long t, unsigned int a, unsigned int b)
{
    __ASM volatile("kdmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.34.2. KDMABT ===== */

/* ===== Inline Function Start for 3.34.3. KDMATT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KDMATT (Signed Saturating Double Multiply Addition T16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then double and saturate the Q31 result, add the result
 * with the sign-extended lower 32-bit chunk destination register and write the saturated addition
 * result into the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then
 * doubled and saturated into a Q31 value. The Q31 value is then added with the content of Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV flag is set to 1. The result after saturation is written to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KDMABB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KDMABT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KDMATT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult = aop * bop;
 *   resQ31 = Mresult << 1;
 * } else {
 *   resQ31 = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd = Rd + resQ31; // RV32
 * resadd = Rd.W[0] + resQ31; // RV64
 * if (resadd > (2^31)-1) {
 *   resadd = (2^31)-1;
 *   OV = 1;
 * } else if (resadd < -2^31) {
 *   resadd = -2^31;
 *   OV = 1;
 * }
 * Rd = resadd; // RV32
 * Rd = SE(resadd); // RV64
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KDMATT(long t, unsigned int a, unsigned int b)
{
    __ASM volatile("kdmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.34.3. KDMATT ===== */

/* ===== Inline Function Start for 3.35.1. KHM8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
 * \brief KHM8 (SIMD Signed Saturating Q7 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KHM8 Rd, Rs1, Rs2
 * KHMX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
 * numbers again.
 *
 * **Description**:\n
 * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
 * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the
 * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
 * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2.
 * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
 * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
 * The result will be saturated to 0x7F and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * if (is `KHM8`) {
 *   op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
 *   op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
 * } else if (is `KHMX8`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x80 != aop | 0x80 != bop) {
 *     res = (aop s* bop) >> 7;
 *   } else {
 *     res= 0x7F;
 *     OV = 1;
 *   }
 * }
 * Rd.H[x/2] = concat(rest, resb);
 * for RV32, x=0,2
 * for RV64, x=0,2,4,6
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHM8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.35.1. KHM8 ===== */

/* ===== Inline Function Start for 3.35.2. KHMX8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
 * \brief KHMX8 (SIMD Signed Saturating Crossed Q7 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KHM8 Rd, Rs1, Rs2
 * KHMX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
 * numbers again.
 *
 * **Description**:\n
 * For the `KHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
 * For the `KHMX16` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1 with the
 * bottom 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
 * content of 16-bit chunks in Rs1 with the top 8-bit Q7 content of 16-bit chunks in Rs2.
 * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
 * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
 * The result will be saturated to 0x7F and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * if (is `KHM8`) {
 *   op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
 *   op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
 * } else if (is `KHMX8`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x80 != aop | 0x80 != bop) {
 *     res = (aop s* bop) >> 7;
 *   } else {
 *     res= 0x7F;
 *     OV = 1;
 *   }
 * }
 * Rd.H[x/2] = concat(rest, resb);
 * for RV32, x=0,2
 * for RV64, x=0,2,4,6
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHMX8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khmx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.35.2. KHMX8 ===== */

/* ===== Inline Function Start for 3.36.1. KHM16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
 * \brief KHM16 (SIMD Signed Saturating Q15 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KHM16 Rd, Rs1, Rs2
 * KHMX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
 * Q15 numbers again.
 *
 * **Description**:\n
 * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
 * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
 * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
 * Rs2.
 * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the
 * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15
 * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2.
 * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
 * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
 * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * if (is `KHM16`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
 * } else if (is `KHMX16`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x8000 != aop | 0x8000 != bop) {
 *     res = (aop s* bop) >> 15;
 *   } else {
 *     res= 0x7FFF;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x/2] = concat(rest, resb);
 * for RV32: x=0
 * for RV64: x=0,2
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHM16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.36.1. KHM16 ===== */

/* ===== Inline Function Start for 3.36.2. KHMX16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
 * \brief KHMX16 (SIMD Signed Saturating Crossed Q15 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KHM16 Rd, Rs1, Rs2
 * KHMX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
 * Q15 numbers again.
 *
 * **Description**:\n
 * For the `KHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
 * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
 * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
 * Rs2.
 * For the `KHMX16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in Rs1 with the
 * bottom 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom 16-bit Q15
 * content of 32-bit chunks in Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2.
 * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
 * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
 * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * if (is `KHM16`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
 * } else if (is `KHMX16`) {
 *   op1t = Rs1.H[x+1]; op2t = Rs2.H[x]; // Rs1 top
 *   op1b = Rs1.H[x]; op2b = Rs2.H[x+1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x8000 != aop | 0x8000 != bop) {
 *     res = (aop s* bop) >> 15;
 *   } else {
 *     res= 0x7FFF;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x/2] = concat(rest, resb);
 * for RV32: x=0
 * for RV64: x=0,2
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHMX16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khmx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.36.2. KHMX16 ===== */

/* ===== Inline Function Start for 3.37.1. KHMBB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief KHMBB (Signed Saturating Half Multiply B16 x B16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
 * number again and saturate the Q15 result into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
 * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd = SE32(res[15:0]); // Rv32
 * Rd = SE64(res[15:0]); // RV64
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KHMBB(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("khmbb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.37.1. KHMBB ===== */

/* ===== Inline Function Start for 3.37.2. KHMBT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief KHMBT (Signed Saturating Half Multiply B16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
 * number again and saturate the Q15 result into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
 * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd = SE32(res[15:0]); // Rv32
 * Rd = SE64(res[15:0]); // RV64
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KHMBT(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("khmbt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.37.2. KHMBT ===== */

/* ===== Inline Function Start for 3.37.3. KHMTT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief KHMTT (Signed Saturating Half Multiply T16 x T16)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 number contents of two 16-bit data in the corresponding portion
 * of the lower 32-bit chunk in registers and then right-shift 15 bits to turn the Q30 result into a Q15
 * number again and saturate the Q15 result into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs1 with
 * the top or bottom 16-bit Q15 content of the lower 32-bit portion in Rs2. The Q30 result is then right-
 * shifted 15-bits and saturated into a Q15 value. The Q15 value is then sing-extended and written into
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * aop = Rs1.H[0]; bop = Rs2.H[0]; // KHMBB
 * aop = Rs1.H[0]; bop = Rs2.H[1]; // KHMBT
 * aop = Rs1.H[1]; bop = Rs2.H[1]; // KHMTT
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd = SE32(res[15:0]); // Rv32
 * Rd = SE64(res[15:0]); // RV64
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KHMTT(unsigned int a, unsigned int b)
{
    register long result;
    __ASM volatile("khmtt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.37.3. KHMTT ===== */

/* ===== Inline Function Start for 3.38.1. KMABB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMABB (SIMD Saturating Signed Multiply Bottom Halfs & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMABB Rd, Rs1, Rs2
 * KMABT Rd, Rs1, Rs2
 * KMATT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
 * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
 * third register. The addition result may be saturated and is written to the third register.
 * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
 * * KMABT rd.W[x] + bottom*top (per 32-bit element)
 * * KMATT rd.W[x] + top*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2.
 * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2.
 * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2.
 * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
 * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
 * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMABB(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmabb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.38.1. KMABB ===== */

/* ===== Inline Function Start for 3.38.2. KMABT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMABT (SIMD Saturating Signed Multiply Bottom & Top Halfs & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMABB Rd, Rs1, Rs2
 * KMABT Rd, Rs1, Rs2
 * KMATT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
 * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
 * third register. The addition result may be saturated and is written to the third register.
 * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
 * * KMABT rd.W[x] + bottom*top (per 32-bit element)
 * * KMATT rd.W[x] + top*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2.
 * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2.
 * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2.
 * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
 * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
 * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMABT(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmabt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.38.2. KMABT ===== */

/* ===== Inline Function Start for 3.38.3. KMATT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMATT (SIMD Saturating Signed Multiply Top Halfs & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMABB Rd, Rs1, Rs2
 * KMABT Rd, Rs1, Rs2
 * KMATT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of 32-bit elements in a register with the 16-bit content
 * of 32-bit elements in another register and add the result to the content of 32-bit elements in the
 * third register. The addition result may be saturated and is written to the third register.
 * * KMABB: rd.W[x] + bottom*bottom (per 32-bit element)
 * * KMABT rd.W[x] + bottom*top (per 32-bit element)
 * * KMATT rd.W[x] + top*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMABB` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2.
 * For the `KMABT` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2.
 * For the `KMATT` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2.
 * The multiplication result is added to the content of 32-bit elements in Rd. If the addition result is
 * beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to
 * 1. The results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]); // KMABB
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[1]); // KMABT
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]); // KMATT
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMATT(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmatt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.38.3. KMATT ===== */

/* ===== Inline Function Start for 3.39.1. KMADA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMADA (SIMD Saturating Signed Multiply Two Halfs and Two Adds)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMADA Rd, Rs1, Rs2
 * KMAXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds
 * the two 32-bit results and 32-bit elements in a third register together. The addition result may be
 * saturated.
 * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element)
 * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
 * elements in Rs2.
 * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying
 * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in
 * Rs2.
 * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit
 * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMADA
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMAXDA
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 * OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADA(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.39.1. KMADA ===== */

/* ===== Inline Function Start for 3.39.2. KMAXDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMAXDA (SIMD Saturating Signed Crossed Multiply Two Halfs and Two Adds)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMADA Rd, Rs1, Rs2
 * KMAXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then adds
 * the two 32-bit results and 32-bit elements in a third register together. The addition result may be
 * saturated.
 * * KMADA: rd.W[x] + top*top + bottom*bottom (per 32-bit element)
 * * KMAXDA: rd.W[x] + top*bottom + bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMADA instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
 * elements in Rs2.
 * For the `KMAXDA` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * bottom 16-bit content of 32-bit elements in Rs2 and then adds the result to the result of multiplying
 * the bottom 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit elements in
 * Rs2.
 * The result is added to the content of 32-bit elements in Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The 32-bit
 * results after saturation are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMADA
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMAXDA
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) + (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 * OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMAXDA(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmaxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.39.2. KMAXDA ===== */

/* ===== Inline Function Start for 3.40.1. KMADS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMADS (SIMD Saturating Signed Multiply Two Halfs & Subtract & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMADS Rd, Rs1, Rs2
 * KMADRS Rd, Rs1, Rs2
 * KMAXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the corresponding 32-bit elements in a third register. The addition result may be saturated.
 * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
 * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
 * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
 * elements in Rs2.
 * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
 * bit elements in Rs2.
 * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
 * elements in Rs2.
 * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
 * and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMADS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMADRS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * // KMAXDS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADS(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmads %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.40.1. KMADS ===== */

/* ===== Inline Function Start for 3.40.2. KMADRS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMADRS (SIMD Saturating Signed Multiply Two Halfs & Reverse Subtract & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMADS Rd, Rs1, Rs2
 * KMADRS Rd, Rs1, Rs2
 * KMAXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the corresponding 32-bit elements in a third register. The addition result may be saturated.
 * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
 * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
 * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
 * elements in Rs2.
 * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
 * bit elements in Rs2.
 * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
 * elements in Rs2.
 * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
 * and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMADS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMADRS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * // KMAXDS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADRS(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmadrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.40.2. KMADRS ===== */

/* ===== Inline Function Start for 3.40.3. KMAXDS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMAXDS (SIMD Saturating Signed Crossed Multiply Two Halfs & Subtract & Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMADS Rd, Rs1, Rs2
 * KMADRS Rd, Rs1, Rs2
 * KMAXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the corresponding 32-bit elements in a third register. The addition result may be saturated.
 * * KMADS: rd.W[x] + (top*top - bottom*bottom) (per 32-bit element)
 * * KMADRS: rd.W[x] + (bottom*bottom - top*top) (per 32-bit element)
 * * KMAXDS: rd.W[x] + (top*bottom - bottom*top) (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMADS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the bottom 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the top 16-bit content of 32-bit
 * elements in Rs2.
 * For the `KMADRS` instruction, it multiplies the top 16-bit content of 32-bit elements in Rs1 with the
 * top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-
 * bit elements in Rs2.
 * For the `KMAXDS` instruction, it multiplies the bottom 16-bit content of 32-bit elements in Rs1 with
 * the top 16-bit content of 32-bit elements in Rs2 and then subtracts the result from the result of
 * multiplying the top 16-bit content of 32-bit elements in Rs1 with the bottom 16-bit content of 32-bit
 * elements in Rs2.
 * The subtraction result is then added to the content of the corresponding 32-bit elements in Rd. If the
 * addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and
 * the OV bit is set to 1. The 32-bit results after saturation are written to Rd. The 16-bit contents of Rs1
 * and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMADS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMADRS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * // KMAXDS
 * res[x] = Rd.W[x] + (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMAXDS(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmaxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.40.3. KMAXDS ===== */

/* ===== Inline Function Start for 3.41. KMAR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief KMAR64 (Signed Multiply and Saturating Add to 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * KMAR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication
 * results to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
 * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds
 * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by
 * Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the Q63 number range (-2^63 <=
 * Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written back
 * to the even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
 * adds the 64-bit multiplication results to the 64-bit signed data of Rd with unlimited precision. If the
 * 64-bit addition result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range
 * and the OV bit is set to 1. The saturated result is written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * result = R[t_H].R[t_L] + (Rs1 * Rs2);
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * RV64:
 * // `result` has unlimited precision
 * result = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]);
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_KMAR64(long long t, long a, long b)
{
    __ASM volatile("kmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.41. KMAR64 ===== */

/* ===== Inline Function Start for 3.42.1. KMDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMDA (SIMD Signed Multiply Two Halfs and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMDA Rd, Rs1, Rs2
 * KMXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * adds the two 32-bit results together. The addition result may be saturated.
 * * KMDA: top*top + bottom*bottom (per 32-bit element)
 * * KMXDA: top*bottom + bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
 * bit elements of Rs2.
 * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the
 * 32-bit elements of Rs2.
 * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1.
 * The final results are written to Rd. The 16-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * if  Rs1.W[x]  !=  0x80008000)  or  (Rs2.W[x]  !=  0x80008000  {  //  KMDA  Rd.W[x]  =  Rs1.W[x].H[1]  *
 * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0])
 * +  (Rs1.W[x].H[0]  *  Rs2.W[x].H[1];  }  else  {  Rd.W[x]  =  0x7fffffff;  OV  =  1;  }  for  RV32:  x=0  for  RV64:
 * x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMDA(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.42.1. KMDA ===== */

/* ===== Inline Function Start for 3.42.2. KMXDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMXDA (SIMD Signed Crossed Multiply Two Halfs and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMDA Rd, Rs1, Rs2
 * KMXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * adds the two 32-bit results together. The addition result may be saturated.
 * * KMDA: top*top + bottom*bottom (per 32-bit element)
 * * KMXDA: top*bottom + bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
 * bit elements of Rs2.
 * For the `KMXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the
 * 32-bit elements of Rs2.
 * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^31-1.
 * The final results are written to Rd. The 16-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * if  Rs1.W[x]  !=  0x80008000)  or  (Rs2.W[x]  !=  0x80008000  {  //  KMDA  Rd.W[x]  =  Rs1.W[x].H[1]  *
 * Rs2.W[x].H[1]) + (Rs1.W[x].H[0] * Rs2.W[x].H[0]; // KMXDA Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[0])
 * +  (Rs1.W[x].H[0]  *  Rs2.W[x].H[1];  }  else  {  Rd.W[x]  =  0x7fffffff;  OV  =  1;  }  for  RV32:  x=0  for  RV64:
 * x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMXDA(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmxda %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.42.2. KMXDA ===== */

/* ===== Inline Function Start for 3.43.1. KMMAC ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KMMAC (SIMD Saturating MSW Signed Multiply Word and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAC Rd, Rs1, Rs2
 * KMMAC.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers and add the most significant
 * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are
 * saturated first and then written back to the third register. The `.u` form performs an additional
 * rounding up operation on the multiplication results before adding the most significant 32-bit part
 * of the results.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
 * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If
 * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range
 * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
 * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
 * adding a 1 to bit 31 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][63:32];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAC(long t, long a, long b)
{
    __ASM volatile("kmmac %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.43.1. KMMAC ===== */

/* ===== Inline Function Start for 3.43.2. KMMAC.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAC Rd, Rs1, Rs2
 * KMMAC.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers and add the most significant
 * 32-bit results with the signed 32-bit integer elements of a third register. The addition results are
 * saturated first and then written back to the third register. The `.u` form performs an additional
 * rounding up operation on the multiplication results before adding the most significant 32-bit part
 * of the results.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
 * and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If
 * the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range
 * and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
 * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
 * adding a 1 to bit 31 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][63:32];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAC_U(long t, long a, long b)
{
    __ASM volatile("kmmac.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.43.2. KMMAC.u ===== */

/* ===== Inline Function Start for 3.44.1. KMMAWB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWB (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWB Rd, Rs1, Rs2
 * KMMAWB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register and add the most significant 32-bit results with
 * the corresponding signed 32-bit elements of a third register. The addition result is written to the
 * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
 * results from the most significant discarded bit before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
 * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication
 * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
 * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
 * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
 * bit 15 of the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][47:16];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWB(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.44.1. KMMAWB ===== */

/* ===== Inline Function Start for 3.44.2. KMMAWB.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWB.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half and Add with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWB Rd, Rs1, Rs2
 * KMMAWB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register and add the most significant 32-bit results with
 * the corresponding signed 32-bit elements of a third register. The addition result is written to the
 * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
 * results from the most significant discarded bit before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
 * of the corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication
 * results with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
 * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
 * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
 * bit 15 of the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][47:16];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWB_U(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.44.2. KMMAWB.u ===== */

/* ===== Inline Function Start for 3.45.1. KMMAWB2 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWB2 Rd, Rs1, Rs2
 * KMMAWB2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and add the
 * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
 * register. The saturated addition result is written to the corresponding 32-bit elements of the third
 * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
 * before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
 * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
 * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
 * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
 * the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
 *   addop.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
 *   if (`.u` form) {
 *     Mres[x][47:14] = Mres[x][47:14] + 1;
 *   }
 *   addop.W[x] = Mres[x][46:15]; // doubling
 * }
 * res[x] = Rd.W[x] + addop.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWB2(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawb2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.45.1. KMMAWB2 ===== */

/* ===== Inline Function Start for 3.45.2. KMMAWB2.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 and Add with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWB2 Rd, Rs1, Rs2
 * KMMAWB2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and add the
 * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
 * register. The saturated addition result is written to the corresponding 32-bit elements of the third
 * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
 * before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
 * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
 * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
 * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
 * the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
 *   addop.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
 *   if (`.u` form) {
 *     Mres[x][47:14] = Mres[x][47:14] + 1;
 *   }
 *   addop.W[x] = Mres[x][46:15]; // doubling
 * }
 * res[x] = Rd.W[x] + addop.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWB2_U(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawb2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.45.2. KMMAWB2.u ===== */

/* ===== Inline Function Start for 3.46.1. KMMAWT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWT (SIMD Saturating MSW Signed Multiply Word and Top Half and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWT Rd, Rs1, Rs2
 * KMMAWT.u Rd Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the
 * corresponding 32-bit elements of another register and add the most significant 32-bit results with
 * the corresponding signed 32-bit elements of a third register. The addition results are written to the
 * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
 * results from the most significant discarded bit before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the
 * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results
 * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
 * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
 * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
 * bit 15 of the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][47:16];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWT(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.46.1. KMMAWT ===== */

/* ===== Inline Function Start for 3.46.2. KMMAWT.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWT.u (SIMD Saturating MSW Signed Multiply Word and Top Half and Add with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWT Rd, Rs1, Rs2
 * KMMAWT.u Rd Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the signed top 16-bit of the
 * corresponding 32-bit elements of another register and add the most significant 32-bit results with
 * the corresponding signed 32-bit elements of a third register. The addition results are written to the
 * corresponding 32-bit elements of the third register. The `.u` form rounds up the multiplication
 * results from the most significant discarded bit before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed top 16-bit of the
 * corresponding 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results
 * with the corresponding signed 32-bit elements of Rd. If the addition result is beyond the Q31
 * number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results
 * after saturation are written to the corresponding 32-bit elements of Rd. The `.u` form of the
 * instruction rounds up the most significant 32-bit of the 48-bit multiplication results by adding a 1 to
 * bit 15 of the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   res[x] = Rd.W[x] + Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] + Mres[x][47:16];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWT_U(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawt.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.46.2. KMMAWT.u ===== */

/* ===== Inline Function Start for 3.47.1. KMMAWT2 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWT2 Rd, Rs1, Rs2
 * KMMAWT2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and add the
 * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
 * register. The saturated addition result is written to the corresponding 32-bit elements of the third
 * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
 * before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
 * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
 * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
 * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
 * the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
 *   addop.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
 *   if (`.u` form) {
 *     Mres[x][47:14] = Mres[x][47:14] + 1;
 *   }
 *   addop.W[x] = Mres[x][46:15]; // doubling
 * }
 * res[x] = Rd.W[x] + addop.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWT2(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawt2 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.47.1. KMMAWT2 ===== */

/* ===== Inline Function Start for 3.47.2. KMMAWT2.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMAWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 and Add with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMAWT2 Rd, Rs1, Rs2
 * KMMAWT2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and add the
 * saturated most significant 32-bit results with the corresponding signed 32-bit elements of a third
 * register. The saturated addition result is written to the corresponding 32-bit elements of the third
 * register. The `.u` form rounds up the multiplication results from the most significant discarded bit
 * before the addition operations.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * adds the saturated most significant 32-bit Q31 multiplication results with the corresponding signed
 * 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to the
 * corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the most significant
 * 32-bit of the 48-bit Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of
 * the result before the addition operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
 *   addop.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
 *   if (`.u` form) {
 *     Mres[x][47:14] = Mres[x][47:14] + 1;
 *   }
 *   addop.W[x] = Mres[x][46:15]; // doubling
 * }
 * res[x] = Rd.W[x] + addop.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMAWT2_U(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmmawt2.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.47.2. KMMAWT2.u ===== */

/* ===== Inline Function Start for 3.48.1. KMMSB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMSB Rd, Rs1, Rs2
 * KMMSB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers and subtract the most
 * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results
 * are written to the third register. The `.u` form performs an additional rounding up operation on
 * the multiplication results before subtracting the most significant 32-bit part of the results.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
 * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of
 * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the
 * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
 * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
 * adding a 1 to bit 31 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   res[x] = Rd.W[x] - Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] - Mres[x][63:32];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMSB(long t, long a, long b)
{
    __ASM volatile("kmmsb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.48.1. KMMSB ===== */

/* ===== Inline Function Start for 3.48.2. KMMSB.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMSB Rd, Rs1, Rs2
 * KMMSB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers and subtract the most
 * significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results
 * are written to the third register. The `.u` form performs an additional rounding up operation on
 * the multiplication results before subtracting the most significant 32-bit part of the results.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2
 * and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of
 * Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the
 * range and the OV bit is set to 1. The results after saturation are written to Rd. The `.u` form of the
 * instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by
 * adding a 1 to bit 31 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   res[x] = Rd.W[x] - Round[x][32:1];
 * } else {
 *   res[x] = Rd.W[x] - Mres[x][63:32];
 * }
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMSB_U(long t, long a, long b)
{
    __ASM volatile("kmmsb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.48.2. KMMSB.u ===== */

/* ===== Inline Function Start for 3.49.1. KMMWB2 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMWB2 (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMWB2 Rd, Rs1, Rs2
 * KMMWB2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and write the
 * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
 * form rounds up the results from the most significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
 * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
 * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
 *   if (`.u` form) {
 *     Round[x][32:0] = Mres[x][46:14] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][46:15];
 *   }
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMWB2(long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmmwb2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.49.1. KMMWB2 ===== */

/* ===== Inline Function Start for 3.49.2. KMMWB2.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMWB2.u (SIMD Saturating MSW Signed Multiply Word and Bottom Half & 2 with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMWB2 Rd, Rs1, Rs2
 * KMMWB2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and write the
 * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
 * form rounds up the results from the most significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed bottom 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
 * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
 * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[0] == 0x8000)) {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[0];
 *   if (`.u` form) {
 *     Round[x][32:0] = Mres[x][46:14] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][46:15];
 *   }
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMWB2_U(long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmmwb2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.49.2. KMMWB2.u ===== */

/* ===== Inline Function Start for 3.50.1. KMMWT2 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMWT2 (SIMD Saturating MSW Signed Multiply Word and Top Half & 2)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMWT2 Rd, Rs1, Rs2
 * KMMWT2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and write the
 * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
 * form rounds up the results from the most significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
 * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
 * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
 *   if (`.u` form) {
 *     Round[x][32:0] = Mres[x][46:14] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][46:15];
 *   }
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMWT2(long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmmwt2 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.50.1. KMMWT2 ===== */

/* ===== Inline Function Start for 3.50.2. KMMWT2.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief KMMWT2.u (SIMD Saturating MSW Signed Multiply Word and Top Half & 2 with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMMWT2 Rd, Rs1, Rs2
 * KMMWT2.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, double the multiplication results and write the
 * saturated most significant 32-bit results to the corresponding 32-bit elements of a register. The `.u`
 * form rounds up the results from the most significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit Q31 elements of Rs1 with the signed top 16-bit Q15
 * content of the corresponding 32-bit elements of Rs2, doubles the Q46 results to Q47 numbers and
 * writes the saturated most significant 32-bit Q31 multiplication results to the corresponding 32-bit
 * elements of Rd. The `.u` form of the instruction rounds up the most significant 32-bit of the 48-bit
 * Q47 multiplication results by adding a 1 to bit 15 (i.e., bit 14 before doubling) of the results.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1.W[x] == 0x80000000) & (Rs2.W[x].H[1] == 0x8000)) {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * } else {
 *   Mres[x][47:0] = Rs1.W[x] s* Rs2.W[x].H[1];
 *   if (`.u` form) {
 *     Round[x][32:0] = Mres[x][46:14] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][46:15];
 *   }
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMMWT2_U(long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmmwt2.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.50.2. KMMWT2.u ===== */

/* ===== Inline Function Start for 3.51.1. KMSDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMSDA (SIMD Saturating Signed Multiply Two Halfs & Add & Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMSDA Rd, Rs1, Rs2
 * KMSXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The
 * subtraction result may be saturated.
 * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element)
 * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the
 * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2.
 * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32-
 * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The
 * 16-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMSDA
 * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMSXDA
 * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMSDA(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmsda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.51.1. KMSDA ===== */

/* ===== Inline Function Start for 3.51.2. KMSXDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief KMSXDA (SIMD Saturating Signed Crossed Multiply Two Halfs & Add & Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KMSDA Rd, Rs1, Rs2
 * KMSXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * subtracts the two 32-bit results from the corresponding 32-bit elements of a third register. The
 * subtraction result may be saturated.
 * * KMSDA: rd.W[x] - top*top - bottom*bottom (per 32-bit element)
 * * KMSXDA: rd.W[x] - top*bottom - bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `KMSDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `KMSXDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the
 * 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2.
 * The two 32-bit multiplication results are then subtracted from the content of the corresponding 32-
 * bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is
 * saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The
 * 16-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * // KMSDA
 * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * // KMSXDA
 * res[x] = Rd.W[x] - (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMSXDA(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmsxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.51.2. KMSXDA ===== */

/* ===== Inline Function Start for 3.52. KMSR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief KMSR64 (Signed Multiply and Saturating Subtract from 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * KMSR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication
 * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
 * saturated to the Q63 range and written back to the pair of registers (RV32) or the register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It
 * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers
 * specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the Q63
 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated
 * result is written back to the even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
 * subtracts the 64-bit multiplication results from the 64-bit signed data in Rd with unlimited
 * precision. If the 64-bit subtraction result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is
 * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * result = R[t_H].R[t_L] - (Rs1 * Rs2);
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * RV64:
 * // `result` has unlimited precision
 * result = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]);
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_KMSR64(long long t, long a, long b)
{
    __ASM volatile("kmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.52. KMSR64 ===== */

/* ===== Inline Function Start for 3.53. KSLLW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KSLLW (Saturating Shift Left Logical for Word)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSLLW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do logical left shift operation with saturation on a 32-bit word. The shift amount is a
 * variable from a GPR.
 *
 * **Description**:\n
 * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with
 * zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register. Any
 * shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated
 * to -2^31. And the saturated result is sign-extended and written to Rd. If any saturation is performed,
 * set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * res[(31+sa):0] = Rs1.W[0] << sa;
 * if (res > (2^31)-1) {
 *   res = 0x7fffffff; OV = 1;
 * } else if (res < -2^31) {
 *   res = 0x80000000; OV = 1;
 * }
 * Rd[31:0] = res[31:0]; // RV32
 * Rd[63:0] = SE(res[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KSLLW(long a, unsigned int b)
{
    register long result;
    __ASM volatile("ksllw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.53. KSLLW ===== */

/* ===== Inline Function Start for 3.54. KSLLIW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KSLLIW (Saturating Shift Left Logical Immediate for Word)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSLLIW Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do logical left shift operation with saturation on a 32-bit word. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * The first word data in Rs1 is left-shifted logically. The shifted out bits are filled with
 * zero and the shift amount is specified by the imm5u constant. Any shifted value greater than 2^31-1 is
 * saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated result is
 * sign-extended and written to Rd. If any saturation is performed, set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u;
 * res[(31+sa):0] = Rs1.W[0] << sa;
 * if (res > (2^31)-1) {
 *   res = 0x7fffffff; OV = 1;
 * } else if (res < -2^31) {
 *   res = 0x80000000; OV = 1;
 * }
 * Rd[31:0] = res[31:0]; // RV32
 * Rd[63:0] = SE(res[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
#define __RV_KSLLIW(a, b)    \
    ({    \
        register long result;    \
        register long __a = (long)(a);    \
        __ASM volatile("kslliw %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.54. KSLLIW ===== */

/* ===== Inline Function Start for 3.55. KSLL8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief KSLL8 (SIMD 8-bit Saturating Shift Left Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLL8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is a variable from a GPR.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
 * Any shifted value greater than 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is
 * saturated to -2^7. And the saturated results are written to Rd. If any saturation is performed, set OV
 * bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * if (sa != 0) {
 *   res[(7+sa):0] = Rs1.B[x] << sa;
 *   if (res > (2^7)-1) {
 *     res = 0x7f; OV = 1;
 *   } else if (res < -2^7) {
 *     res = 0x80; OV = 1;
 *   }
 *   Rd.B[x] = res[7:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLL8(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ksll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.55. KSLL8 ===== */

/* ===== Inline Function Start for 3.56. KSLLI8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief KSLLI8 (SIMD 8-bit Saturating Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLLI8 Rd, Rs1, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is an immediate value.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the imm3u constant. Any shifted value greater than
 * 2^7-1 is saturated to 2^7-1. Any shifted value smaller than -2^7 is saturated to -2^7. And the saturated
 * results are written to Rd. If any saturation is performed, set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * if (sa != 0) {
 *   res[(7+sa):0] = Rs1.B[x] << sa;
 *   if (res > (2^7)-1) {
 *     res = 0x7f; OV = 1;
 *   } else if (res < -2^7) {
 *     res = 0x80; OV = 1;
 *   }
 *   Rd.B[x] = res[7:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_KSLLI8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("kslli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.56. KSLLI8 ===== */

/* ===== Inline Function Start for 3.57. KSLL16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief KSLL16 (SIMD 16-bit Saturating Shift Left Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLL16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is a variable from a GPR.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the low-order 4-bits of the value in the Rs2 register.
 * Any shifted value greater than 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is
 * saturated to -2^15. And the saturated results are written to Rd. If any saturation is performed, set OV
 * bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * if (sa != 0) {
 *   res[(15+sa):0] = Rs1.H[x] << sa;
 *   if (res > (2^15)-1) {
 *     res = 0x7fff; OV = 1;
 *   } else if (res < -2^15) {
 *     res = 0x8000; OV = 1;
 *   }
 *   Rd.H[x] = res[15:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ksll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.57. KSLL16 ===== */

/* ===== Inline Function Start for 3.58. KSLLI16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief KSLLI16 (SIMD 16-bit Saturating Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLLI16 Rd, Rs1, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is an immediate value.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the imm4u constant. Any shifted value greater than
 * 2^15-1 is saturated to 2^15-1. Any shifted value smaller than -2^15 is saturated to -2^15. And the saturated
 * results are written to Rd. If any saturation is performed, set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4u[3:0];
 * if (sa != 0) {
 *   res[(15+sa):0] = Rs1.H[x] << sa;
 *   if (res > (2^15)-1) {
 *     res = 0x7fff; OV = 1;
 *   } else if (res < -2^15) {
 *     res = 0x8000; OV = 1;
 *   }
 *   Rd.H[x] = res[15:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_KSLLI16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("kslli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.58. KSLLI16 ===== */

/* ===== Inline Function Start for 3.59.1. KSLRA8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief KSLRA8 (SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA8 Rd, Rs1, Rs2
 * KSLRA8.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
 * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
 * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
 * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form
 * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[3:0] < 0) {
 *   sa = -Rs2[3:0];
 *   sa = (sa == 8)? 7 : sa;
 *   if (`.u` form) {
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else {
 *     Rd.B[x] = SE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   sa = Rs2[2:0];
 *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
 *   if (res > (2^7)-1) {
 *     res[7:0] = 0x7f; OV = 1;
 *   } else if (res < -2^7) {
 *     res[7:0] = 0x80; OV = 1;
 *   }
 *   Rd.B[x] = res[7:0];
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA8(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.59.1. KSLRA8 ===== */

/* ===== Inline Function Start for 3.59.2. KSLRA8.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief KSLRA8.u (SIMD 8-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA8 Rd, Rs1, Rs2
 * KSLRA8.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q7 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
 * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
 * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
 * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1]. For the `.u` form
 * of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[3:0] < 0) {
 *   sa = -Rs2[3:0];
 *   sa = (sa == 8)? 7 : sa;
 *   if (`.u` form) {
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else {
 *     Rd.B[x] = SE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   sa = Rs2[2:0];
 *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
 *   if (res > (2^7)-1) {
 *     res[7:0] = 0x7f; OV = 1;
 *   } else if (res < -2^7) {
 *     res[7:0] = 0x80; OV = 1;
 *   }
 *   Rd.B[x] = res[7:0];
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.59.2. KSLRA8.u ===== */

/* ===== Inline Function Start for 3.60.1. KSLRA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief KSLRA16 (SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA16 Rd, Rs1, Rs2
 * KSLRA16.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
 * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
 * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
 * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u`
 * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[4:0] < 0) {
 *   sa = -Rs2[4:0];
 *   sa = (sa == 16)? 15 : sa;
 *   if (`.u` form) {
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else {
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   sa = Rs2[3:0];
 *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
 *   if (res > (2^15)-1) {
 *     res[15:0] = 0x7fff; OV = 1;
 *   } else if (res < -2^15) {
 *     res[15:0] = 0x8000; OV = 1;
 *   }
 *   d.H[x] = res[15:0];
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.60.1. KSLRA16 ===== */

/* ===== Inline Function Start for 3.60.2. KSLRA16.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief KSLRA16.u (SIMD 16-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA16 Rd, Rs1, Rs2
 * KSLRA16.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q15 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
 * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
 * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
 * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1]. For the `.u`
 * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[4:0] < 0) {
 *   sa = -Rs2[4:0];
 *   sa = (sa == 16)? 15 : sa;
 *   if (`.u` form) {
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else {
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   sa = Rs2[3:0];
 *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
 *   if (res > (2^15)-1) {
 *     res[15:0] = 0x7fff; OV = 1;
 *   } else if (res < -2^15) {
 *     res[15:0] = 0x8000; OV = 1;
 *   }
 *   d.H[x] = res[15:0];
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.60.2. KSLRA16.u ===== */

/* ===== Inline Function Start for 3.61. KSLRAW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KSLRAW (Shift Left Logical with Q31 Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSLRAW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31
 * saturation for the left shift on a 32-bit data.
 *
 * **Description**:\n
 * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
 * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31].
 * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. After the shift
 * operation, the final result is bit-31 sign-extended and written to Rd. If any saturation happens, this
 * instruction sets the OV flag. The value of Rs2[31:6] will not affected the operation of this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[5:0] < 0) {
 *   sa = -Rs2[5:0];
 *   sa = (sa == 32)? 31 : sa;
 *   res[31:0] = Rs1.W[0] >>(arith) sa;
 * } else {
 *   sa = Rs2[5:0];
 *   tmp = Rs1.W[0] <<(logic) sa;
 *   if (tmp > (2^31)-1) {
 *     res[31:0] = (2^31)-1;
 *     OV = 1;
 *   } else if (tmp < -2^31) {
 *     res[31:0] = -2^31;
 *     OV = 1
 *   } else {
 *     res[31:0] = tmp[31:0];
 *   }
 * }
 * Rd = res[31:0]; // RV32
 * Rd = SE64(res[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KSLRAW(int a, int b)
{
    register long result;
    __ASM volatile("kslraw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.61. KSLRAW ===== */

/* ===== Inline Function Start for 3.62. KSLRAW.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KSLRAW.u (Shift Left Logical with Q31 Saturation or Rounding Shift Right Arithmetic)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSLRAW.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a logical left (positive) or arithmetic right (negative) shift operation with Q31
 * saturation for the left shift and a rounding up operation for the right shift on a 32-bit data.
 *
 * **Description**:\n
 * The lower 32-bit content of Rs1 is left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
 * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[5:0] clamped to the actual shift range of [0, 31].
 * The left-shifted result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. The right-shifted
 * result is added a 1 to the most significant discarded bit position for rounding effect. After the shift,
 * saturation, or rounding, the final result is bit-31 sign-extended and written to Rd. If any saturation
 * happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect the operation of this
 * instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[5:0] < 0) {
 *   sa = -Rs2[5:0];
 *   sa = (sa == 32)? 31 : sa;
 *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
 *   rst[31:0] = res[31:0];
 * } else {
 *   sa = Rs2[5:0];
 *   tmp = Rs1.W[0] <<(logic) sa;
 *   if (tmp > (2^31)-1) {
 *     rst[31:0] = (2^31)-1;
 *     OV = 1;
 *   } else if (tmp < -2^31) {
 *     rst[31:0] = -2^31;
 *     OV = 1
 *   } else {
 *     rst[31:0] = tmp[31:0];
 *   }
 * }
 * Rd = rst[31:0]; // RV32
 * Rd = SE64(rst[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KSLRAW_U(int a, int b)
{
    register long result;
    __ASM volatile("kslraw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.62. KSLRAW.u ===== */

/* ===== Inline Function Start for 3.63. KSTAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KSTAS16 (SIMD 16-bit Signed Saturating Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSTAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating addition and 16-bit signed integer element
 * saturating subtraction in a 32-bit chunk simultaneously. Operands are from corresponding
 * positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it
 * subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed
 * integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number
 * range (-2^15 <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit chunks in Rd for
 * subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16];
 * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0];
 * for (res in [res1, res2]) {
 *   if (res > (2^15)-1) {
 *     res = (2^15)-1;
 *     OV = 1;
 *   } else if (res < -2^15) {
 *     res = -2^15;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSTAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.63. KSTAS16 ===== */

/* ===== Inline Function Start for 3.64. KSTSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KSTSA16 (SIMD 16-bit Signed Saturating Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSTSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating subtraction and 16-bit signed integer element
 * saturating addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in
 * 32-bit chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks
 * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1; at the same time, it
 * adds the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2 with the 16-bit signed integer
 * element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the Q15 number range (-2^15
 * <= Q15 <= 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
 * written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of 32-bit chunks in Rd for
 * addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16];
 * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0];
 * for (res in [res1, res2]) {
 *   if (res > (2^15)-1) {
 *     res = (2^15)-1;
 *     OV = 1;
 *   } else if (res < -2^15) {
 *     res = -2^15;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSTSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.64. KSTSA16 ===== */

/* ===== Inline Function Start for 3.65. KSUB8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief KSUB8 (SIMD 8-bit Signed Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSUB8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
 * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 27
 * -1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.B[x] - Rs2.B[x];
 * if (res[x] > (2^7)-1) {
 *   res[x] = (2^7)-1;
 *   OV = 1;
 * } else if (res[x] < -2^7) {
 *   res[x] = -2^7;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSUB8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.65. KSUB8 ===== */

/* ===== Inline Function Start for 3.66. KSUB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief KSUB16 (SIMD 16-bit Signed Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KSUB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
 * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <=
 * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] - Rs2.H[x];
 * if (res[x] > (2^15)-1) {
 *   res[x] = (2^15)-1;
 *   OV = 1;
 * } else if (res[x] < -2^15) {
 *   res[x] = -2^15;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSUB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.66. KSUB16 ===== */

/* ===== Inline Function Start for 3.67. KSUB64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief KSUB64 (64-bit Signed Saturating Subtraction)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * KSUB64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 64-bit signed integer subtraction. The result is saturated to the Q63 range.
 *
 * **RV32 Description**:\n
 * This instruction subtracts the 64-bit signed integer of an even/odd pair of
 * registers specified by Rs2(4,1) from the 64-bit signed integer of an even/odd pair of registers
 * specified by Rs1(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is
 * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd
 * pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * This instruction subtracts the 64-bit signed integer of Rs2 from the 64-bit signed
 * integer of Rs1. If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated
 * to the range and the OV bit is set to 1. The saturated result is then written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 * result = R[a_H].R[a_L] - R[b_H].R[b_L];
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * RV64:
 * result = Rs1 - Rs2;
 * if (result > (2^63)-1) {
 *   result = (2^63)-1; OV = 1;
 * } else if (result < -2^63) {
 *   result = -2^63; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    long long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_KSUB64(long long a, long long b)
{
    register long long result;
    __ASM volatile("ksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.67. KSUB64 ===== */

/* ===== Inline Function Start for 3.68. KSUBH ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief KSUBH (Signed Subtraction with Q15 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSUBH Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract the signed lower 32-bit content of two registers with Q15 saturation.
 *
 * **Description**:\n
 * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit
 * content of Rs1. And the result is saturated to the 16-bit signed integer range of [-2^15, 2^15-1] and then
 * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] - Rs2.W[0];
 * if (tmp > (2^15)-1) {
 *   res = (2^15)-1;
 *   OV = 1;
 * } else if (tmp < -2^15) {
 *   res = -2^15;
 *   OV = 1
 * } else {
 *   res = tmp;
 * }
 * Rd = SE(res[15:0]);
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KSUBH(int a, int b)
{
    register long result;
    __ASM volatile("ksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.68. KSUBH ===== */

/* ===== Inline Function Start for 3.69. KSUBW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief KSUBW (Signed Subtraction with Q31 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * KSUBW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract the signed lower 32-bit content of two registers with Q31 saturation.
 *
 * **Description**:\n
 * The signed lower 32-bit content of Rs2 is subtracted from the signed lower 32-bit
 * content of Rs1. And the result is saturated to the 32-bit signed integer range of [-2^31, 2^31-1] and then
 * sign-extened and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] - Rs2.W[0];
 * if (tmp > (2^31)-1) {
 *   res = (2^31)-1;
 *   OV = 1;
 * } else if (tmp < -2^31) {
 * res = -2^31;
 *   OV = 1
 * } else {
 *   res = tmp;
 * }
 * Rd = res[31:0]; // RV32
 * Rd = SE(res[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KSUBW(int a, int b)
{
    register long result;
    __ASM volatile("ksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.69. KSUBW ===== */

/* ===== Inline Function Start for 3.70.1. KWMMUL ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KWMMUL Rd, Rs1, Rs2
 * KWMMUL.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit,
 * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally
 * rounds up the multiplication results from the most signification discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts
 * the multiplication results one bit to the left and takes the most significant 32-bit results. If the
 * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element
 * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u`
 * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit
 * 30 before the shift and saturation operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
 *   Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 *   if (`.u` form) {
 *     Round[x][33:0] = Mres[x][63:30] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][62:31];
 *   }
 * } else {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KWMMUL(long a, long b)
{
    register long result;
    __ASM volatile("kwmmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.70.1. KWMMUL ===== */

/* ===== Inline Function Start for 3.70.2. KWMMUL.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * KWMMUL Rd, Rs1, Rs2
 * KWMMUL.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit,
 * saturate, and write the most significant 32-bit results to a register. The `.u` form additionally
 * rounds up the multiplication results from the most signification discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts
 * the multiplication results one bit to the left and takes the most significant 32-bit results. If the
 * shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element
 * result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The `.u`
 * form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit
 * 30 before the shift and saturation operations.
 *
 * **Operations**:\n
 * ~~~
 * if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
 *   Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 *   if (`.u` form) {
 *     Round[x][33:0] = Mres[x][63:30] + 1;
 *     Rd.W[x] = Round[x][32:1];
 *   } else {
 *     Rd.W[x] = Mres[x][62:31];
 *   }
 * } else {
 *   Rd.W[x] = 0x7fffffff;
 *   OV = 1;
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KWMMUL_U(long a, long b)
{
    register long result;
    __ASM volatile("kwmmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.70.2. KWMMUL.u ===== */

/* ===== Inline Function Start for 3.71. MADDR32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief MADDR32 (Multiply and Add to 32-Bit Word)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MADDR32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit contents of two registers and add the lower 32-bit multiplication result
 * to the 32-bit content of a destination register. Write the final result back to the destination register.
 *
 * **Description**:\n
 * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2. It adds the
 * lower 32-bit multiplication result to the lower 32-bit content of Rd and writes the final result (RV32)
 * or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either signed or
 * unsigned integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mresult = Rs1 * Rs2;
 * Rd = Rd + Mresult.W[0];
 * RV64:
 * Mresult = Rs1.W[0] * Rs2.W[0];
 * tres[31:0] = Rd.W[0] + Mresult.W[0];
 * Rd = SE64(tres[31:0]);
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_MADDR32(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("maddr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.71. MADDR32 ===== */

/* ===== Inline Function Start for 3.72. MAXW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief MAXW (32-bit Signed Word Maximum)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MAXW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Get the larger value from the 32-bit contents of two general registers.
 *
 * **Description**:\n
 * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the
 * larger value as the result, and writes the result to Rd.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs1.W[0] >= Rs2.W[0]) {
 *   Rd = SE(Rs1.W[0]);
 * } else {
 *   Rd = SE(Rs2.W[0]);
 * }
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_MAXW(int a, int b)
{
    register long result;
    __ASM volatile("maxw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.72. MAXW ===== */

/* ===== Inline Function Start for 3.73. MINW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief MINW (32-bit Signed Word Minimum)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MINW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Get the smaller value from the 32-bit contents of two general registers.
 *
 * **Description**:\n
 * This instruction compares two signed 32-bit integers stored in Rs1 and Rs2, picks the
 * smaller value as the result, and writes the result to Rd.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs1.W[0] >= Rs2.W[0]) { Rd = SE(Rs2.W[0]); } else { Rd = SE(Rs1.W[0]); }
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_MINW(int a, int b)
{
    register long result;
    __ASM volatile("minw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.73. MINW ===== */

/* ===== Inline Function Start for 3.74. MSUBR32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief MSUBR32 (Multiply and Subtract from 32-Bit Word)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MSUBR32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit contents of two registers and subtract the lower 32-bit multiplication
 * result from the 32-bit content of a destination register. Write the final result back to the destination
 * register.
 *
 * **Description**:\n
 * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2, subtracts
 * the lower 32-bit multiplication result from the lower 32-bit content of Rd, then writes the final
 * result (RV32) or sign-extended result (RV64) back to Rd. The contents of Rs1 and Rs2 can be either
 * signed or unsigned integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mresult = Rs1 * Rs2;
 * Rd = Rd - Mresult.W[0];
 * RV64:
 * Mresult = Rs1.W[0] * Rs2.W[0];
 * tres[31:0] = Rd.W[0] - Mresult.W[0];
 * Rd = SE64(tres[31:0]);
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_MSUBR32(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("msubr32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.74. MSUBR32 ===== */

/* ===== Inline Function Start for 3.75. MULR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief MULR64 (Multiply Word Unsigned to 64-bit Data)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MULR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit unsigned integer contents of two registers and write the 64-bit result.
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit content of Rs1 with that of Rs2 and writes the 64-bit
 * multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d determines the
 * even/odd pair group of the two registers. Specifically, the register pair includes register 2d and
 * 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the lower 32-bit content of Rs1 with that of Rs2 and writes the 64-bit
 * multiplication result to Rd.
 * The lower 32-bit contents of Rs1 and Rs2 are treated as unsigned integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mresult = CONCAT(1`b0,Rs1) u* CONCAT(1`b0,Rs2);
 * R[Rd(4,1).1(0)][31:0] = Mresult[63:32];
 * R[Rd(4,1).0(0)][31:0] = Mresult[31:0];
 * RV64:
 * Rd = Mresult[63:0];
 * Mresult = CONCAT(1`b0,Rs1.W[0]) u* CONCAT(1`b0,Rs2.W[0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_MULR64(unsigned long a, unsigned long b)
{
    register unsigned long long result;
    __ASM volatile("mulr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.75. MULR64 ===== */

/* ===== Inline Function Start for 3.76. MULSR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief MULSR64 (Multiply Word Signed to 64-bit Data)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * MULSR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed integer contents of two registers and write the 64-bit result.
 *
 * **RV32 Description**:\n
 * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and
 * writes the 64-bit multiplication result to an even/odd pair of registers containing Rd. Rd(4,1) index d
 * determines the even/odd pair group of the two registers. Specifically, the register pair includes
 * register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the lower 32-bit content of Rs1 with the lower 32-bit content of Rs2 and
 * writes the 64-bit multiplication result to Rd.
 * The lower 32-bit contents of Rs1 and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mresult = Ra s* Rb;
 * R[Rd(4,1).1(0)][31:0] = Mresult[63:32];
 * R[Rd(4,1).0(0)][31:0] = Mresult[31:0];
 * RV64:
 * Mresult = Ra.W[0] s* Rb.W[0];
 * Rd = Mresult[63:0];
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_MULSR64(long a, long b)
{
    register long long result;
    __ASM volatile("mulsr64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.76. MULSR64 ===== */

/* ===== Inline Function Start for 3.77. PBSAD ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief PBSAD (Parallel Byte Sum of Absolute Difference)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PBSAD Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Calculate the sum of absolute difference of unsigned 8-bit data elements.
 *
 * **Description**:\n
 * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. Then
 * it adds the absolute value of each difference together and writes the result to Rd.
 *
 * **Operations**:\n
 * ~~~
 * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]);
 * Rd = SUM(absdiff[x]);
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PBSAD(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pbsad %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.77. PBSAD ===== */

/* ===== Inline Function Start for 3.78. PBSADA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief PBSADA (Parallel Byte Sum of Absolute Difference Accum)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PBSADA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Calculate the sum of absolute difference of four unsigned 8-bit data elements and
 * accumulate it into a register.
 *
 * **Description**:\n
 * This instruction subtracts the un-signed 8-bit elements of Rs2 from those of Rs1. It
 * then adds the absolute value of each difference together along with the content of Rd and writes the
 * accumulated result back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * absdiff[x] = ABS(Rs1.B[x] - Rs2.B[x]);
 * Rd = Rd + SUM(absdiff[x]);
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PBSADA(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("pbsada %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.78. PBSADA ===== */

/* ===== Inline Function Start for 3.79.1. PKBB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
 * \brief PKBB16 (Pack Two 16-bit Data from Both Bottom Half)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PKBB16 Rd, Rs1, Rs2
 * PKBT16 Rd, Rs1, Rs2
 * PKTT16 Rd, Rs1, Rs2
 * PKTB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 16-bit data from 32-bit chunks in two registers.
 * * PKBB16: bottom.bottom
 * * PKBT16 bottom.top
 * * PKTT16 top.top
 * * PKTB16 top.bottom
 *
 * **Description**:\n
 * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
 * Rd.W[x] [15:0].
 * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKBB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pkbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.79.1. PKBB16 ===== */

/* ===== Inline Function Start for 3.79.2. PKBT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
 * \brief PKBT16 (Pack Two 16-bit Data from Bottom and Top Half)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PKBB16 Rd, Rs1, Rs2
 * PKBT16 Rd, Rs1, Rs2
 * PKTT16 Rd, Rs1, Rs2
 * PKTB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 16-bit data from 32-bit chunks in two registers.
 * * PKBB16: bottom.bottom
 * * PKBT16 bottom.top
 * * PKTT16 top.top
 * * PKTB16 top.bottom
 *
 * **Description**:\n
 * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
 * Rd.W[x] [15:0].
 * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKBT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pkbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.79.2. PKBT16 ===== */

/* ===== Inline Function Start for 3.79.3. PKTT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
 * \brief PKTT16 (Pack Two 16-bit Data from Both Top Half)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PKBB16 Rd, Rs1, Rs2
 * PKBT16 Rd, Rs1, Rs2
 * PKTT16 Rd, Rs1, Rs2
 * PKTB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 16-bit data from 32-bit chunks in two registers.
 * * PKBB16: bottom.bottom
 * * PKBT16 bottom.top
 * * PKTT16 top.top
 * * PKTB16 top.bottom
 *
 * **Description**:\n
 * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
 * Rd.W[x] [15:0].
 * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKTT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pktt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.79.3. PKTT16 ===== */

/* ===== Inline Function Start for 3.79.4. PKTB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_PACK
 * \brief PKTB16 (Pack Two 16-bit Data from Top and Bottom Half)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * PKBB16 Rd, Rs1, Rs2
 * PKBT16 Rd, Rs1, Rs2
 * PKTT16 Rd, Rs1, Rs2
 * PKTB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 16-bit data from 32-bit chunks in two registers.
 * * PKBB16: bottom.bottom
 * * PKBT16 bottom.top
 * * PKTT16 top.top
 * * PKTB16 top.bottom
 *
 * **Description**:\n
 * (PKBB16) moves Rs1.W[x][15:0] to Rd.W[x][31:16] and moves Rs2.W[x] [15:0] to
 * Rd.W[x] [15:0].
 * (PKBT16) moves Rs1.W[x] [15:0] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTT16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [31:16] to Rd.W[x] [15:0].
 * (PKTB16) moves Rs1.W[x] [31:16] to Rd.W[x] [31:16] and moves Rs2.W[x] [15:0] to Rd.W[x] [15:0].
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][15:0]); // PKBB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][15:0], Rs2.W[x][31:16]); // PKBT16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][15:0]); // PKTB16
 * Rd.W[x][31:0] = CONCAT(Rs1.W[x][31:16], Rs2.W[x][31:16]); // PKTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKTB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pktb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.79.4. PKTB16 ===== */

/* ===== Inline Function Start for 3.80. RADD8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief RADD8 (SIMD 8-bit Signed Halving Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RADD8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer element additions simultaneously. The element results are halved
 * to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
 * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
 * Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7F, Rs2 = 0x7F, Rd = 0x7F
 * * Rs1 = 0x80, Rs2 = 0x80, Rd = 0x80
 * * Rs1 = 0x40, Rs2 = 0x80, Rd = 0xE0
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] + Rs2.B[x]) s>> 1; for RV32: x=3...0, for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RADD8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("radd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.80. RADD8 ===== */

/* ===== Inline Function Start for 3.81. RADD16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RADD16 (SIMD 16-bit Signed Halving Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RADD16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element additions simultaneously. The results are halved to avoid
 * overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
 * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
 * Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7FFF, Rs2 = 0x7FFF, Rd = 0x7FFF
 * * Rs1 = 0x8000, Rs2 = 0x8000, Rd = 0x8000
 * * Rs1 = 0x4000, Rs2 = 0x8000, Rd = 0xE000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) s>> 1; for RV32: x=1...0, for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RADD16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("radd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.81. RADD16 ===== */

/* ===== Inline Function Start for 3.82. RADD64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief RADD64 (64-bit Signed Halving Addition)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * RADD64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add two 64-bit signed integers. The result is halved to avoid overflow or saturation.
 *
 * **RV32 Description**:\n
 * This instruction adds the 64-bit signed integer of an even/odd pair of registers
 * specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by
 * Rs2(4,1). The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to an
 * even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed
 * integer in Rs2. The 64-bit addition result is first arithmetically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) s>> 1;
 * RV64:
 * Rd = (Rs1 + Rs2) s>> 1;
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    long long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_RADD64(long long a, long long b)
{
    register long long result;
    __ASM volatile("radd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.82. RADD64 ===== */

/* ===== Inline Function Start for 3.83. RADDW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief RADDW (32-bit Signed Halving Addition)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * RADDW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add 32-bit signed integers and the results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the first 32-bit signed integer in Rs1 with the first 32-bit signed
 * integer in Rs2. The result is first arithmetically right-shifted by 1 bit and then sign-extended and
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF, Rd = 0x7FFFFFFF
 * * Rs1 = 0x80000000, Rs2 = 0x80000000, Rd = 0x80000000
 * * Rs1 = 0x40000000, Rs2 = 0x80000000, Rd = 0xE0000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1;
 * RV64:
 * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) s>> 1;
 * Rd[63:0] = SE(resw[31:0]);
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_RADDW(int a, int b)
{
    register long result;
    __ASM volatile("raddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.83. RADDW ===== */

/* ===== Inline Function Start for 3.84. RCRAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RCRAS16 (SIMD 16-bit Signed Halving Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RCRAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in
 * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results
 * are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit signed integer element in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit
 * signed integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit signed integer element in
 * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and
 * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD16` and `RSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) s>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) s>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RCRAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.84. RCRAS16 ===== */

/* ===== Inline Function Start for 3.85. RCRSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RCRSA16 (SIMD 16-bit Signed Halving Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RCRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in
 * a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks. The results
 * are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer element in [15:0] of 32-bit chunks
 * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit
 * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in
 * [31:16] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and
 * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD16` and `RSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) s>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) s>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RCRSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.85. RCRSA16 ===== */

/* ===== Inline Function Start for 3.86. RDOV ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_OV_FLAG_SC
 * \brief RDOV (Read OV flag)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * RDOV Rd  # pseudo mnemonic
 * ~~~
 *
 * **Purpose**:\n
 * This pseudo instruction is an alias to `CSRR Rd, ucode` instruction which maps to the real
 * instruction of `CSRRS Rd, ucode, x0`.
 *
 *
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RDOV(void)
{
    register unsigned long result;
    __ASM volatile("rdov %0" : "=r"(result));
    return result;
}
/* ===== Inline Function End for 3.86. RDOV ===== */

/* ===== Inline Function Start for 3.87. RSTAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RSTAS16 (SIMD 16-bit Signed Halving Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RSTAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element addition and 16-bit signed integer element subtraction in
 * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The
 * results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit
 * signed integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit signed integer element in
 * [15:0] of 32-bit chunks in Rs1. The element results are first arithmetically right-shifted by 1 bit and
 * then written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD16` and `RSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) s>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) s>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSTAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.87. RSTAS16 ===== */

/* ===== Inline Function Start for 3.88. RSTSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RSTSA16 (SIMD 16-bit Signed Halving Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RSTSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element subtraction and 16-bit signed integer element addition in
 * a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit chunks. The
 * results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer element in [31:16] of 32-bit chunks
 * in Rs2 from the 16-bit signed integer element in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit
 * signed element integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit signed integer element in
 * [15:0] of 32-bit chunks in Rs2. The two results are first arithmetically right-shifted by 1 bit and then
 * written to [31:16] of 32-bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD16` and `RSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) s>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) s>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSTSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.88. RSTSA16 ===== */

/* ===== Inline Function Start for 3.89. RSUB8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief RSUB8 (SIMD 8-bit Signed Halving Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RSUB8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
 * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7F, Rs2 = 0x80, Rd = 0x7F
 * * Rs1 = 0x80, Rs2 = 0x7F, Rd = 0x80
 * * Rs1= 0x80, Rs2 = 0x40, Rd = 0xA0
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) s>> 1;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSUB8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rsub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.89. RSUB8 ===== */

/* ===== Inline Function Start for 3.90. RSUB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief RSUB16 (SIMD 16-bit Signed Halving Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * RSUB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
 * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFF, Rb = 0x8000, Rt = 0x7FFF
 * * Ra = 0x8000, Rb = 0x7FFF, Rt = 0x8000
 * * Ra = 0x8000, Rb = 0x4000, Rt = 0xA000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) s>> 1;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSUB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rsub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.90. RSUB16 ===== */

/* ===== Inline Function Start for 3.91. RSUB64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief RSUB64 (64-bit Signed Halving Subtraction)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * RSUB64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 64-bit signed integer subtraction. The result is halved to avoid overflow or
 * saturation.
 *
 * **RV32 Description**:\n
 * This instruction subtracts the 64-bit signed integer of an even/odd pair of
 * registers specified by Rb(4,1) from the 64-bit signed integer of an even/odd pair of registers
 * specified by Ra(4,1). The subtraction result is first arithmetically right-shifted by 1 bit and then
 * written to an even/odd pair of registers specified by Rt(4,1).
 * Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction subtracts the 64-bit signed integer in Rs2 from the 64-bit signed
 * integer in Rs1. The 64-bit subtraction result is first arithmetically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) s>> 1;
 * RV64:
 * Rd = (Rs1 - Rs2) s>> 1;
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    long long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_RSUB64(long long a, long long b)
{
    register long long result;
    __ASM volatile("rsub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.91. RSUB64 ===== */

/* ===== Inline Function Start for 3.92. RSUBW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief RSUBW (32-bit Signed Halving Subtraction)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * RSUBW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract 32-bit signed integers and the result is halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit
 * signed integer in Rs1. The result is first arithmetically right-shifted by 1 bit and then sign-extended
 * and written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7FFFFFFF, Rs2 = 0x80000000, Rd = 0x7FFFFFFF
 * * Rs1 = 0x80000000, Rs2 = 0x7FFFFFFF, Rd = 0x80000000
 * * Rs1 = 0x80000000, Rs2 = 0x40000000, Rd = 0xA0000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1;
 * RV64:
 * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) s>> 1;
 * Rd[63:0] = SE(resw[31:0]);
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_RSUBW(int a, int b)
{
    register long result;
    __ASM volatile("rsubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.92. RSUBW ===== */

/* ===== Inline Function Start for 3.93. SCLIP8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief SCLIP8 (SIMD 8-bit Signed Clip Value)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCLIP8 Rd, Rs1, imm3u[2:0]
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 8-bit signed integer elements of a register into a signed range simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 8-bit signed integer elements stored in Rs1 into a signed
 * integer range between 2^imm3u-1 and -2^imm3u, and writes the limited results to Rd. For example, if
 * imm3u is 3, the 8-bit input values should be saturated between 7 and -8. If saturation is performed,
 * set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.B[x];
 * if (src > (2^imm3u)-1) {
 *   src = (2^imm3u)-1;
 *   OV = 1;
 * } else if (src < -2^imm3u) {
 *   src = -2^imm3u;
 *   OV = 1;
 * }
 * Rd.B[x] = src
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SCLIP8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("sclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.93. SCLIP8 ===== */

/* ===== Inline Function Start for 3.94. SCLIP16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief SCLIP16 (SIMD 16-bit Signed Clip Value)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCLIP16 Rd, Rs1, imm4u[3:0]
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 16-bit signed integer elements of a register into a signed range simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 16-bit signed integer elements stored in Rs1 into a signed
 * integer range between 2imm4u-1 and -2imm4u, and writes the limited results to Rd. For example, if
 * imm4u is 3, the 16-bit input values should be saturated between 7 and -8. If saturation is performed,
 * set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.H[x];
 * if (src > (2^imm4u)-1) {
 *   src = (2^imm4u)-1;
 *   OV = 1;
 * } else if (src < -2^imm4u) {
 *   src = -2^imm4u;
 *   OV = 1;
 * }
 * Rd.H[x] = src
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SCLIP16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("sclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.94. SCLIP16 ===== */

/* ===== Inline Function Start for 3.95. SCLIP32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief SCLIP32 (SIMD 32-bit Signed Clip Value)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SCLIP32 Rd, Rs1, imm5u[4:0]
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 32-bit signed integer elements of a register into a signed range simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 32-bit signed integer elements stored in Rs1 into a signed
 * integer range between 2imm5u-1 and -2imm5u, and writes the limited results to Rd. For example, if
 * imm5u is 3, the 32-bit input values should be saturated between 7 and -8. If saturation is performed,
 * set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.W[x];
 * if (src > (2^imm5u)-1) {
 *   src = (2^imm5u)-1;
 *   OV = 1;
 * } else if (src < -2^imm5u) {
 *   src = -2^imm5u;
 *   OV = 1;
 * }
 * Rd.W[x] = src
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
#define __RV_SCLIP32(a, b)    \
    ({    \
        register long result;    \
        register long __a = (long)(a);    \
        __ASM volatile("sclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.95. SCLIP32 ===== */

/* ===== Inline Function Start for 3.96. SCMPLE8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
 * \brief SCMPLE8 (SIMD 8-bit Signed Compare Less Than & Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCMPLE8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer elements less than & equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
 * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is
 * true, the result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to
 * Rd
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] {le} Rs2.B[x])? 0xff : 0x0;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SCMPLE8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("scmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.96. SCMPLE8 ===== */

/* ===== Inline Function Start for 3.97. SCMPLE16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
 * \brief SCMPLE16 (SIMD 16-bit Signed Compare Less Than & Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCMPLE16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements less than & equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
 * signed integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it is
 * true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] {le} Rs2.H[x])? 0xffff : 0x0;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SCMPLE16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("scmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.97. SCMPLE16 ===== */

/* ===== Inline Function Start for 3.98. SCMPLT8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
 * \brief SCMPLT8 (SIMD 8-bit Signed Compare Less Than)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCMPLT8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer elements less than comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
 * signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
 * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? 0xff : 0x0;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SCMPLT8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("scmplt8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.98. SCMPLT8 ===== */

/* ===== Inline Function Start for 3.99. SCMPLT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
 * \brief SCMPLT16 (SIMD 16-bit Signed Compare Less Than)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SCMPLT16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements less than comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit signed integer elements in Rs1 with the two 16-
 * bit signed integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
 * result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? 0xffff : 0x0;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SCMPLT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("scmplt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.99. SCMPLT16 ===== */

/* ===== Inline Function Start for 3.100. SLL8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SLL8 (SIMD 8-bit Shift Left Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SLL8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left shift operations simultaneously. The shift amount is a
 * variable from a GPR.
 *
 * **Description**:\n
 * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
 * The shifted out bits are filled with zero and the shift amount is specified by the low-order 3-bits of
 * the value in the Rs2 register.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * Rd.B[x] = Rs1.B[x] << sa;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SLL8(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sll8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.100. SLL8 ===== */

/* ===== Inline Function Start for 3.101. SLLI8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SLLI8 (SIMD 8-bit Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SLLI8 Rd, Rs1, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left shift operations simultaneously. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * The 8-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
 * The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * Rd.B[x] = Rs1.B[x] << sa;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SLLI8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("slli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.101. SLLI8 ===== */

/* ===== Inline Function Start for 3.102. SLL16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SLL16 (SIMD 16-bit Shift Left Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SLL16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left shift operations simultaneously. The shift amount is a
 * variable from a GPR.
 *
 * **Description**:\n
 * The 16-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
 * The shifted out bits are filled with zero and the shift amount is specified by the low-order 4-bits of
 * the value in the Rs2 register.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * Rd.H[x] = Rs1.H[x] << sa;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sll16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.102. SLL16 ===== */

/* ===== Inline Function Start for 3.103. SLLI16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SLLI16 (SIMD 16-bit Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SLLI16 Rd, Rs1, imm4[3:0]
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit element logical left shift operations simultaneously. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * The 16-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with
 * zero and the shift amount is specified by the imm4[3:0] constant. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4[3:0];
 * Rd.H[x] = Rs1.H[x] << sa;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SLLI16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("slli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.103. SLLI16 ===== */

/* ===== Inline Function Start for 3.104. SMAL ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMAL (Signed Multiply Halfs & Add 64-bit)
 * \details
 * **Type**: Partial-SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMAL Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top
 * 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit
 * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
 * to another even/odd pair of registers (RV32) or a register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit
 * content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of
 * registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of
 * registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register-
 * pair are treated as signed integers.
 * Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit
 * content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64-
 * bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are
 * treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mres[31:0] = Rs2.H[1] * Rs2.H[0];
 * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); +
 * Idx2 = CONCAT(Rd(4,1),1'b0); Idx3 = CONCAT(Rd(4,1),1'b1);
 * R[Idx3].R[Idx2] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * RV64:
 * Mres[0][31:0] = Rs2.W[0].H[1] * Rs2.W[0].H[0];
 * Mres[1][31:0] = Rs2.W[1].H[1] * Rs2.W[1].H[0];
 * Rd = Rs1 + SE64(Mres[1][31:0]) + SE64(Mres[0][31:0]);
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMAL(long long a, unsigned long b)
{
    register long long result;
    __ASM volatile("smal %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.104. SMAL ===== */

/* ===== Inline Function Start for 3.105.1. SMALBB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALBB (Signed Multiply Bottom Halfs & Add 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALBB Rd, Rs1, Rs2
 * SMALBT Rd, Rs1, Rs2
 * SMALTT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
 * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
 * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
 * to the register-pair (RV32) or the register (RV64).
 * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
 * * SMALBT rt pair + bottom*top (all 32-bit elements)
 * * SMALTT rt pair + top*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2.
 * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
 * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
 * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * RV64:
 * // SMALBB
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
 * // SMALBT
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
 * // SMALTT
 * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALBB(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalbb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.105.1. SMALBB ===== */

/* ===== Inline Function Start for 3.105.2. SMALBT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALBB Rd, Rs1, Rs2
 * SMALBT Rd, Rs1, Rs2
 * SMALTT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
 * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
 * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
 * to the register-pair (RV32) or the register (RV64).
 * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
 * * SMALBT rt pair + bottom*top (all 32-bit elements)
 * * SMALTT rt pair + top*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2.
 * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
 * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
 * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * RV64:
 * // SMALBB
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
 * // SMALBT
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
 * // SMALTT
 * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALBT(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalbt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.105.2. SMALBT ===== */

/* ===== Inline Function Start for 3.105.3. SMALTT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALTT (Signed Multiply Top Halfs & Add 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALBB Rd, Rs1, Rs2
 * SMALBT Rd, Rs1, Rs2
 * SMALTT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit
 * content of the corresponding 32-bit elements of another register and add the results with a 64-bit
 * value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back
 * to the register-pair (RV32) or the register (RV64).
 * * SMALBB: rt pair + bottom*bottom (all 32-bit elements)
 * * SMALBT rt pair + bottom*top (all 32-bit elements)
 * * SMALTT rt pair + top*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2.
 * The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALBB` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALBT` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMALTT` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB
 * Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT
 * Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * RV64:
 * // SMALBB
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0];
 * // SMALBT
 * Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1];
 * // SMALTT
 * Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1];
 * Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1];
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALTT(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smaltt %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.105.3. SMALTT ===== */

/* ===== Inline Function Start for 3.106.1. SMALDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALDA Rd, Rs1, Rs2
 * SMALXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
 * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
 * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with
 * the top 16-bit content of Rs2 with unlimited precision.
 * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1
 * with the top 16-bit content of Rs2 with unlimited precision.
 * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-
 * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-
 * bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
 * bit elements of Rs2 with unlimited precision.
 * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
 * 32-bit elements of Rs2 with unlimited precision.
 * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The
 * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * // SMALDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
 * // SMALXDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]);
 * RV64:
 * // SMALDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMALXDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
 * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) +
 * SE64(Mres1[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALDA(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.106.1. SMALDA ===== */

/* ===== Inline Function Start for 3.106.2. SMALXDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALDA Rd, Rs1, Rs2
 * SMALXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
 * * SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
 * * SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with
 * the top 16-bit content of Rs2 with unlimited precision.
 * For the `SMALXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1
 * with the top 16-bit content of Rs2 with unlimited precision.
 * The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-
 * bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-
 * bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-
 * bit elements of Rs2 with unlimited precision.
 * For the `SMALXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
 * 32-bit elements of Rs2 with unlimited precision.
 * The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The
 * 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * RV32:
 * // SMALDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
 * // SMALXDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]);
 * RV64:
 * // SMALDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMALXDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
 * Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) +
 * SE64(Mres1[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALXDA(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.106.2. SMALXDA ===== */

/* ===== Inline Function Start for 3.107.1. SMALDS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALDS Rd, Rs1, Rs2
 * SMALDRS Rd, Rs1, Rs2
 * SMALXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
 * written back to the register-pair.
 * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
 * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
 * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the top 16-bit content of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
 * with the bottom 16-bit content of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the bottom 16-bit content of Rs2.
 * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
 * of the 32-bit elements of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
 * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * * RV64:
 * // SMALDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * // SMALDRS
 * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMALXDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALDS(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.107.1. SMALDS ===== */

/* ===== Inline Function Start for 3.107.2. SMALDRS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALDS Rd, Rs1, Rs2
 * SMALDRS Rd, Rs1, Rs2
 * SMALXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
 * written back to the register-pair.
 * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
 * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
 * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the top 16-bit content of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
 * with the bottom 16-bit content of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the bottom 16-bit content of Rs2.
 * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
 * of the 32-bit elements of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
 * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * * RV64:
 * // SMALDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * // SMALDRS
 * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMALXDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALDRS(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smaldrs %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.107.2. SMALDRS ===== */

/* ===== Inline Function Start for 3.107.3. SMALXDS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMALDS Rd, Rs1, Rs2
 * SMALDRS Rd, Rs1, Rs2
 * SMALXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results. Then add the subtraction result to
 * the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is
 * written back to the register-pair.
 * * SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
 * * SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
 * * SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the top 16-bit content of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content
 * of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1
 * with the bottom 16-bit content of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit
 * content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of
 * Rs1 with the bottom 16-bit content of Rs2.
 * The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by
 * Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and
 * Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * For the `SMALDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content
 * of the 32-bit elements of Rs2.
 * For the `SMALDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMALXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written
 * back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS
 * Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS
 * Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]);
 * * RV64:
 * // SMALDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * // SMALDRS
 * Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMALXDS
 * Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMALXDS(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smalxds %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.107.3. SMALXDS ===== */

/* ===== Inline Function Start for 3.108. SMAR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief SMAR64 (Signed Multiply and Add to 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMAR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed elements in two registers and add the 64-bit multiplication
 * result to the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is written
 * back to the pair of registers (RV32) or a register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It adds
 * the 64-bit multiplication result to the 64-bit signed data of an even/odd pair of registers specified by
 * Rd(4,1). The addition result is written back to the even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
 * adds the 64-bit multiplication results to the 64-bit signed data of Rd. The addition result is written
 * back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2);
 * * RV64:
 * Rd = Rd + (Rs1.W[0] * Rs2.W[0]) + (Rs1.W[1] * Rs2.W[1]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMAR64(long long t, long a, long b)
{
    __ASM volatile("smar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.108. SMAR64 ===== */

/* ===== Inline Function Start for 3.109. SMAQA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
 * \brief SMAQA (Signed Multiply Four Bytes with 32-bit Adds)
 * \details
 * **Type**: Partial-SIMD (Reduction)
 *
 * **Syntax**:\n
 * ~~~
 * SMAQA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do four signed 8-bit multiplications from 32-bit chunks of two registers; and then adds
 * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together.
 *
 * **Description**:\n
 * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four
 * signed 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the signed
 * content of the corresponding 32-bit chunks of Rd. The final results are written back to the
 * corresponding 32-bit chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] +
 *    (Rs1.W[x].B[3] s* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] s* Rs2.W[x].B[2]) +
 *    (Rs1.W[x].B[1] s* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] s* Rs2.W[x].B[0]);
 * Rd.W[x] = res[x];
 * for RV32: x=0,
 * for RV64: x=1,0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMAQA(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.109. SMAQA ===== */

/* ===== Inline Function Start for 3.110. SMAQA.SU ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
 * \brief SMAQA.SU (Signed and Unsigned Multiply Four Bytes with 32-bit Adds)
 * \details
 * **Type**: Partial-SIMD (Reduction)
 *
 * **Syntax**:\n
 * ~~~
 * SMAQA.SU Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do four `signed x unsigned` 8-bit multiplications from 32-bit chunks of two registers; and
 * then adds the four 16-bit results and the content of corresponding 32-bit chunks of a third register
 * together.
 *
 * **Description**:\n
 * This instruction multiplies the four signed 8-bit elements of 32-bit chunks of Rs1 with the four
 * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the
 * signed content of the corresponding 32-bit chunks of Rd. The final results are written back to the
 * corresponding 32-bit chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] +
 *    (Rs1.W[x].B[3] su* Rs2.W[x].B[3]) + (Rs1.W[x].B[2] su* Rs2.W[x].B[2]) +
 *    (Rs1.W[x].B[1] su* Rs2.W[x].B[1]) + (Rs1.W[x].B[0] su* Rs2.W[x].B[0]);
 * Rd.W[x] = res[x];
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMAQA_SU(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smaqa.su %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.110. SMAQA.SU ===== */

/* ===== Inline Function Start for 3.111. SMAX8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief SMAX8 (SIMD 8-bit Signed Maximum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMAX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
 * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] > Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMAX8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.111. SMAX8 ===== */

/* ===== Inline Function Start for 3.112. SMAX16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief SMAX16 (SIMD 16-bit Signed Maximum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMAX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
 * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] > Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMAX16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.112. SMAX16 ===== */

/* ===== Inline Function Start for 3.113.1. SMBB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMBB16 (SIMD Signed Multiply Bottom Half & Bottom Half)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMBB16 Rd, Rs1, Rs2
 * SMBT16 Rd, Rs1, Rs2
 * SMTT16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
 * bit content of the 32-bit elements of another register and write the result to a third register.
 * * SMBB16: W[x].bottom*W[x].bottom
 * * SMBT16: W[x].bottom *W[x].top
 * * SMTT16: W[x].top * W[x].top
 *
 * **Description**:\n
 * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMBB16(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.113.1. SMBB16 ===== */

/* ===== Inline Function Start for 3.113.2. SMBT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMBT16 (SIMD Signed Multiply Bottom Half & Top Half)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMBB16 Rd, Rs1, Rs2
 * SMBT16 Rd, Rs1, Rs2
 * SMTT16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
 * bit content of the 32-bit elements of another register and write the result to a third register.
 * * SMBB16: W[x].bottom*W[x].bottom
 * * SMBT16: W[x].bottom *W[x].top
 * * SMTT16: W[x].top * W[x].top
 *
 * **Description**:\n
 * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMBT16(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.113.2. SMBT16 ===== */

/* ===== Inline Function Start for 3.113.3. SMTT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMTT16 (SIMD Signed Multiply Top Half & Top Half)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMBB16 Rd, Rs1, Rs2
 * SMBT16 Rd, Rs1, Rs2
 * SMTT16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 16-bit content of the 32-bit elements of a register with the signed 16-
 * bit content of the 32-bit elements of another register and write the result to a third register.
 * * SMBB16: W[x].bottom*W[x].bottom
 * * SMBT16: W[x].bottom *W[x].top
 * * SMTT16: W[x].top * W[x].top
 *
 * **Description**:\n
 * For the `SMBB16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2.
 * For the `SMBT16` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMTT16` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2.
 * The multiplication results are written to Rd. The 16-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[0]; // SMBB16
 * Rd.W[x] = Rs1.W[x].H[0] * Rs2.W[x].H[1]; // SMBT16
 * Rd.W[x] = Rs1.W[x].H[1] * Rs2.W[x].H[1]; // SMTT16
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMTT16(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.113.3. SMTT16 ===== */

/* ===== Inline Function Start for 3.114.1. SMDS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMDS (SIMD Signed Multiply Two Halfs and Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMDS Rd, Rs1, Rs2
 * SMDRS Rd, Rs1, Rs2
 * SMXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results.
 * * SMDS: top*top - bottom*bottom (per 32-bit element)
 * * SMDRS: bottom*bottom - top*top (per 32-bit element)
 * * SMXDS: top*bottom - bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
 * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
 * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
 * 32-bit elements of Rs2.
 * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
 * multiplication are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * * SMDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * * SMDRS:
 * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * * SMXDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMDS(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.114.1. SMDS ===== */

/* ===== Inline Function Start for 3.114.2. SMDRS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMDRS (SIMD Signed Multiply Two Halfs and Reverse Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMDS Rd, Rs1, Rs2
 * SMDRS Rd, Rs1, Rs2
 * SMXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results.
 * * SMDS: top*top - bottom*bottom (per 32-bit element)
 * * SMDRS: bottom*bottom - top*top (per 32-bit element)
 * * SMXDS: top*bottom - bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
 * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
 * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
 * 32-bit elements of Rs2.
 * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
 * multiplication are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * * SMDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * * SMDRS:
 * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * * SMXDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMDRS(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smdrs %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.114.2. SMDRS ===== */

/* ===== Inline Function Start for 3.114.3. SMXDS ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_32B_ADDSUB
 * \brief SMXDS (SIMD Signed Crossed Multiply Two Halfs and Subtract)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMDS Rd, Rs1, Rs2
 * SMDRS Rd, Rs1, Rs2
 * SMXDS Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * perform a subtraction operation between the two 32-bit results.
 * * SMDS: top*top - bottom*bottom (per 32-bit element)
 * * SMDRS: bottom*bottom - top*top (per 32-bit element)
 * * SMXDS: top*bottom - bottom*top (per 32-bit element)
 *
 * **Description**:\n
 * For the `SMDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with
 * the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result
 * of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the
 * 32-bit elements of Rs2.
 * For the `SMDRS` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of
 * multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of
 * the 32-bit elements of Rs2.
 * For the `SMXDS` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the
 * result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit
 * content of the 32-bit elements of Rs2.
 * The subtraction result is written to the corresponding 32-bit element of Rd. The 16-bit contents of
 * multiplication are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * * SMDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[1]) - (Rs1.W[x].H[0] * Rs2.W[x].H[0]);
 * * SMDRS:
 * Rd.W[x] = (Rs1.W[x].H[0] * Rs2.W[x].H[0]) - (Rs1.W[x].H[1] * Rs2.W[x].H[1]);
 * * SMXDS:
 * Rd.W[x] = (Rs1.W[x].H[1] * Rs2.W[x].H[0]) - (Rs1.W[x].H[0] * Rs2.W[x].H[1]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMXDS(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smxds %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.114.3. SMXDS ===== */

/* ===== Inline Function Start for 3.115. SMIN8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief SMIN8 (SIMD 8-bit Signed Minimum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMIN8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer elements finding minimum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit signed integer elements in Rs1 with the 8-bit
 * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] < Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMIN8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smin8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.115. SMIN8 ===== */

/* ===== Inline Function Start for 3.116. SMIN16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief SMIN16 (SIMD 16-bit Signed Minimum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMIN16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements finding minimum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit signed integer elements in Rs1 with the 16-bit
 * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] < Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMIN16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smin16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.116. SMIN16 ===== */

/* ===== Inline Function Start for 3.117.1. SMMUL ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief SMMUL (SIMD MSW Signed Multiply Word)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMUL Rd, Rs1, Rs2
 * SMMUL.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed integer elements of two registers and write the most significant
 * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an
 * additional rounding up operation on the multiplication results before taking the most significant
 * 32-bit part of the results.
 *
 * **Description**:\n
 * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the
 * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit
 * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up
 * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.
 * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][63:32];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMUL(long a, long b)
{
    register long result;
    __ASM volatile("smmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.117.1. SMMUL ===== */

/* ===== Inline Function Start for 3.117.2. SMMUL.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X32_MAC
 * \brief SMMUL.u (SIMD MSW Signed Multiply Word with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMUL Rd, Rs1, Rs2
 * SMMUL.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed integer elements of two registers and write the most significant
 * 32-bit results to the corresponding 32-bit elements of a register. The `.u` form performs an
 * additional rounding up operation on the multiplication results before taking the most significant
 * 32-bit part of the results.
 *
 * **Description**:\n
 * This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the
 * most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit
 * elements of Rs1 and Rs2 are treated as signed integers. The `.u` form of the instruction rounds up
 * the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.
 * * For `smmul/RV32` instruction, it is an alias to `mulh/RV32` instruction.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][63:31] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][63:32];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMUL_U(long a, long b)
{
    register long result;
    __ASM volatile("smmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.117.2. SMMUL.u ===== */

/* ===== Inline Function Start for 3.118.1. SMMWB ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief SMMWB (SIMD MSW Signed Multiply Word and Bottom Half)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMWB Rd, Rs1, Rs2
 * SMMWB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
 * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
 * significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
 * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
 * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
 * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][47:16];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMWB(long a, unsigned long b)
{
    register long result;
    __ASM volatile("smmwb %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.118.1. SMMWB ===== */

/* ===== Inline Function Start for 3.118.2. SMMWB.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief SMMWB.u (SIMD MSW Signed Multiply Word and Bottom Half with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMWB Rd, Rs1, Rs2
 * SMMWB.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the bottom 16-bit of the
 * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
 * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
 * significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the signed bottom 16-bit content
 * of the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
 * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
 * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[0];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][47:16];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMWB_U(long a, unsigned long b)
{
    register long result;
    __ASM volatile("smmwb.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.118.2. SMMWB.u ===== */

/* ===== Inline Function Start for 3.119.1. SMMWT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief SMMWT (SIMD MSW Signed Multiply Word and Top Half)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMWT Rd, Rs1, Rs2
 * SMMWT.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
 * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
 * significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of
 * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
 * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
 * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][47:16];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMWT(long a, unsigned long b)
{
    register long result;
    __ASM volatile("smmwt %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.119.1. SMMWT ===== */

/* ===== Inline Function Start for 3.119.2. SMMWT.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_MSW_32X16_MAC
 * \brief SMMWT.u (SIMD MSW Signed Multiply Word and Top Half with Rounding)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMMWT Rd, Rs1, Rs2
 * SMMWT.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit integer elements of one register and the top 16-bit of the
 * corresponding 32-bit elements of another register, and write the most significant 32-bit results to
 * the corresponding 32-bit elements of a register. The `.u` form rounds up the results from the most
 * significant discarded bit.
 *
 * **Description**:\n
 * This instruction multiplies the signed 32-bit elements of Rs1 with the top signed 16-bit content of
 * the corresponding 32-bit elements of Rs2 and writes the most significant 32-bit multiplication
 * results to the corresponding 32-bit elements of Rd. The `.u` form of the instruction rounds up the
 * most significant 32-bit of the 48-bit multiplication results by adding a 1 to bit 15 of the results.
 *
 * **Operations**:\n
 * ~~~
 * Mres[x][47:0] = Rs1.W[x] * Rs2.W[x].H[1];
 * if (`.u` form) {
 *   Round[x][32:0] = Mres[x][47:15] + 1;
 *   Rd.W[x] = Round[x][32:1];
 * } else {
 *   Rd.W[x] = Mres[x][47:16];
 * }
 * for RV32: x=0
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMMWT_U(long a, unsigned long b)
{
    register long result;
    __ASM volatile("smmwt.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.119.2. SMMWT.u ===== */

/* ===== Inline Function Start for 3.120.1. SMSLDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMSLDA Rd, Rs1, Rs2
 * SMSLXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a
 * register (RV64). The subtraction result is written back to the register-pair.
 * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
 * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2.
 * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2.
 * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers
 * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit
 * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction
 * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated
 * as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * // SMSLDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
 * // SMSLXDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]);
 * * RV64:
 * // SMSLDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMSLXDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
 * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) -
 * SE64(Mres1[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMSLDA(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smslda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.120.1. SMSLDA ===== */

/* ===== Inline Function Start for 3.120.2. SMSLXDA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
 * \brief SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMSLDA Rd, Rs1, Rs2
 * SMSLXDA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then
 * subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a
 * register (RV64). The subtraction result is written back to the register-pair.
 * * SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
 * * SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
 *
 * **RV32 Description**:\n
 * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit
 * content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2.
 * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit
 * content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2.
 * The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers
 * specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit
 * values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers.
 * Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * For the `SMSLDA` instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1
 * with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * For the `SMSLXDA` instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with
 * the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of
 * the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2.
 * The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction
 * result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated
 * as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * // SMSLDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]);
 * // SMSLXDA
 * Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]);
 * Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]);
 * Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1);
 * R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]);
 * * RV64:
 * // SMSLDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]);
 * // SMSLXDA
 * Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]);
 * Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]);
 * Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]);
 * Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]);
 * Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) -
 * SE64(Mres1[1][31:0]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMSLXDA(long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("smslxda %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.120.2. SMSLXDA ===== */

/* ===== Inline Function Start for 3.121. SMSR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief SMSR64 (Signed Multiply and Subtract from 64- Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SMSR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit signed elements in two registers and subtract the 64-bit multiplication
 * results from the 64-bit signed data of a pair of registers (RV32) or a register (RV64). The result is
 * written back to the pair of registers (RV32) or a register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit signed data of Rs1 with that of Rs2. It
 * subtracts the 64-bit multiplication result from the 64-bit signed data of an even/odd pair of registers
 * specified by Rd(4,1). The subtraction result is written back to the even/odd pair of registers
 * specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit signed elements of Rs1 with that of Rs2. It
 * subtracts the 64-bit multiplication results from the 64-bit signed data of Rd. The subtraction result is
 * written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H].R[t_L] = R[t_H].R[t_L] - (Rs1 * Rs2);
 * * RV64:
 * Rd = Rd - (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]);
 * ~~~
 *
 * \param [in]  t    long long type of value stored in t
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    long type of value stored in b
 * \return value stored in long long type
 */
__STATIC_FORCEINLINE long long __RV_SMSR64(long long t, long a, long b)
{
    __ASM volatile("smsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.121. SMSR64 ===== */

/* ===== Inline Function Start for 3.122.1. SMUL8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
 * \brief SMUL8 (SIMD Signed 8-bit Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMUL8 Rd, Rs1, Rs2
 * SMULX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do signed 8-bit multiplications and generate four 16-bit results simultaneously.
 *
 * **RV32 Description**:\n
 * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
 * corresponding 8-bit data elements of Rs2.
 * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
 * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
 * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
 * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1).
 * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of
 * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom
 * part of Rs1.
 *
 * **RV64 Description**:\n
 * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
 * corresponding 8-bit data elements of Rs2.
 * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
 * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
 * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
 * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results
 * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from
 * the bottom part of Rs1.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * if (is `SMUL8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
 * } else if (is `SMULX8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
 * }
 * rest[x/2] = op1t[x/2] s* op2t[x/2];
 * resb[x/2] = op1b[x/2] s* op2b[x/2];
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1];
 * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0];
 * x = 0 and 2
 * * RV64:
 * if (is `SMUL8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
 * } else if (is `SMULX8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
 * }
 * rest[x/2] = op1t[x/2] s* op2t[x/2];
 * resb[x/2] = op1b[x/2] s* op2b[x/2];
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1];
 * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0];
 * x = 0 and 2
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_SMUL8(unsigned int a, unsigned int b)
{
    register unsigned long long result;
    __ASM volatile("smul8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.122.1. SMUL8 ===== */

/* ===== Inline Function Start for 3.122.2. SMULX8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MULTIPLY
 * \brief SMULX8 (SIMD Signed Crossed 8-bit Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMUL8 Rd, Rs1, Rs2
 * SMULX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do signed 8-bit multiplications and generate four 16-bit results simultaneously.
 *
 * **RV32 Description**:\n
 * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
 * corresponding 8-bit data elements of Rs2.
 * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
 * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
 * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
 * The four 16-bit results are then written into an even/odd pair of registers specified by Rd(4,1).
 * Rd(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the two 16-bit results calculated from the top part of
 * Rs1 and the even `2d` register of the pair contains the two 16-bit results calculated from the bottom
 * part of Rs1.
 *
 * **RV64 Description**:\n
 * For the `SMUL8` instruction, multiply the 8-bit data elements of Rs1 with the
 * corresponding 8-bit data elements of Rs2.
 * For the `SMULX8` instruction, multiply the first and second 8-bit data elements of Rs1 with the
 * second and first 8-bit data elements of Rs2. At the same time, multiply the third and fourth 8-bit data
 * elements of Rs1 with the fourth and third 8-bit data elements of Rs2.
 * The four 16-bit results are then written into Rd. The Rd.W[1] contains the two 16-bit results
 * calculated from the top part of Rs1 and the Rd.W[0] contains the two 16-bit results calculated from
 * the bottom part of Rs1.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * if (is `SMUL8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
 * } else if (is `SMULX8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
 * }
 * rest[x/2] = op1t[x/2] s* op2t[x/2];
 * resb[x/2] = op1b[x/2] s* op2b[x/2];
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H].H[1] = rest[1]; R[t_H].H[0] = resb[1];
 * R[t_L].H[1] = rest[0]; R[t_L].H[0] = resb[0];
 * x = 0 and 2
 * * RV64:
 * if (is `SMUL8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x+1]; // top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x]; // bottom
 * } else if (is `SMULX8`) {
 *   op1t[x/2] = Rs1.B[x+1]; op2t[x/2] = Rs2.B[x]; // Rs1 top
 *   op1b[x/2] = Rs1.B[x]; op2b[x/2] = Rs2.B[x+1]; // Rs1 bottom
 * }
 * rest[x/2] = op1t[x/2] s* op2t[x/2];
 * resb[x/2] = op1b[x/2] s* op2b[x/2];
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * Rd.W[1].H[1] = rest[1]; Rd.W[1].H[0] = resb[1];
 * Rd.W[0].H[1] = rest[0]; Rd.W[0].H[0] = resb[0];
 * x = 0 and 2
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_SMULX8(unsigned int a, unsigned int b)
{
    register unsigned long long result;
    __ASM volatile("smulx8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.122.2. SMULX8 ===== */

/* ===== Inline Function Start for 3.123.1. SMUL16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
 * \brief SMUL16 (SIMD Signed 16-bit Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMUL16 Rd, Rs1, Rs2
 * SMULX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do signed 16-bit multiplications and generate two 32-bit results simultaneously.
 *
 * **RV32 Description**:\n
 * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with
 * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1
 * with the bottom 16-bit Q15 content of Rs2.
 * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit
 * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16-
 * bit Q15 content of Rs2.
 * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1),
 * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes
 * register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and
 * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1.
 *
 * **RV64 Description**:\n
 * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower
 * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time,
 * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15
 * content of the lower 32-bit word in Rs2.
 * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1
 * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the
 * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the
 * lower 32-bit word in Rs2.
 * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the
 * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of
 * the lower 32-bit word in Rs1 is written to Rd.W[0]
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * if (is `SMUL16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
 * } else if (is `SMULX16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   res = aop s* bop;
 * }
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H] = rest;
 * R[t_L] = resb;
 * * RV64:
 * if (is `SMUL16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
 * } else if (is `SMULX16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   res = aop s* bop;
 * }
 * Rd.W[1] = rest;
 * Rd.W[0] = resb;
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_SMUL16(unsigned int a, unsigned int b)
{
    register unsigned long long result;
    __ASM volatile("smul16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.123.1. SMUL16 ===== */

/* ===== Inline Function Start for 3.123.2. SMULX16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MULTIPLY
 * \brief SMULX16 (SIMD Signed Crossed 16-bit Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SMUL16 Rd, Rs1, Rs2
 * SMULX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do signed 16-bit multiplications and generate two 32-bit results simultaneously.
 *
 * **RV32 Description**:\n
 * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of Rs1 with
 * the top 16-bit Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1
 * with the bottom 16-bit Q15 content of Rs2.
 * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of Rs1 with the bottom 16-bit
 * Q15 content of Rs2. At the same time, multiply the bottom 16-bit Q15 content of Rs1 with the top 16-
 * bit Q15 content of Rs2.
 * The two Q30 results are then written into an even/odd pair of registers specified by Rd(4,1). Rd(4,1),
 * i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes
 * register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the 32-bit result calculated from the top part of Rs1 and
 * the even `2d` register of the pair contains the 32-bit result calculated from the bottom part of Rs1.
 *
 * **RV64 Description**:\n
 * For the `SMUL16` instruction, multiply the top 16-bit Q15 content of the lower
 * 32-bit word in Rs1 with the top 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time,
 * multiply the bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the bottom 16-bit Q15
 * content of the lower 32-bit word in Rs2.
 * For the `SMULX16` instruction, multiply the top 16-bit Q15 content of the lower 32-bit word in Rs1
 * with the bottom 16-bit Q15 content of the lower 32-bit word in Rs2. At the same time, multiply the
 * bottom 16-bit Q15 content of the lower 32-bit word in Rs1 with the top 16-bit Q15 content of the
 * lower 32-bit word in Rs2.
 * The two 32-bit Q30 results are then written into Rd. The result calculated from the top 16-bit of the
 * lower 32-bit word in Rs1 is written to Rd.W[1]. And the result calculated from the bottom 16-bit of
 * the lower 32-bit word in Rs1 is written to Rd.W[0]
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * if (is `SMUL16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
 * } else if (is `SMULX16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   res = aop s* bop;
 * }
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H] = rest;
 * R[t_L] = resb;
 * * RV64:
 * if (is `SMUL16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[1]; // top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[0]; // bottom
 * } else if (is `SMULX16`) {
 *   op1t = Rs1.H[1]; op2t = Rs2.H[0]; // Rs1 top
 *   op1b = Rs1.H[0]; op2b = Rs2.H[1]; // Rs1 bottom
 * }
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   res = aop s* bop;
 * }
 * Rd.W[1] = rest;
 * Rd.W[0] = resb;
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_SMULX16(unsigned int a, unsigned int b)
{
    register unsigned long long result;
    __ASM volatile("smulx16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.123.2. SMULX16 ===== */

/* ===== Inline Function Start for 3.124. SRA.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief SRA.u (Rounding Shift Right Arithmetic)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SRA.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform an arithmetic right shift operation with rounding. The shift amount is a variable
 * from a GPR.
 *
 * **Description**:\n
 * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are
 * filled with the sign-bit and the shift amount is specified by the low-order 5-bits (RV32) or 6-bits
 * (RV64) of the Rs2 register. For the rounding operation, a value of 1 is added to the most significant
 * discarded bit of the data to calculate the final result. And the result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * sa = Rs2[4:0];
 * if (sa > 0) {
 *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
 *   Rd = res[31:0];
 * } else {
 *   Rd = Rs1;
 * }
 * * RV64:
 * sa = Rs2[5:0];
 * if (sa > 0) {
 *   res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1;
 *   Rd = res[63:0];
 * } else {
 *   Rd = Rs1;
 * }
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SRA_U(long a, unsigned int b)
{
    register long result;
    __ASM volatile("sra.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.124. SRA.u ===== */

/* ===== Inline Function Start for 3.125. SRAI.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief SRAI.u (Rounding Shift Right Arithmetic Immediate)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SRAI.u Rd, Rs1, imm6u[4:0] (RV32)
 * SRAI.u Rd, Rs1, imm6u[5:0] (RV64)
 * ~~~
 *
 * **Purpose**:\n
 * Perform an arithmetic right shift operation with rounding. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * This instruction right-shifts the content of Rs1 arithmetically. The shifted out bits are
 * filled with the sign-bit and the shift amount is specified by the imm6u[4:0] (RV32) or imm6u[5:0]
 * (RV64) constant . For the rounding operation, a value of 1 is added to the most significant discarded
 * bit of the data to calculate the final result. And the result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * sa = imm6u[4:0];
 * if (sa > 0) {
 *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
 *   Rd = res[31:0];
 * } else {
 *   Rd = Rs1;
 * }
 * * RV64:
 * sa = imm6u[5:0];
 * if (sa > 0) {
 *   res[63:-1] = SE65(Rs1[63:(sa-1)]) + 1;
 *   Rd = res[63:0];
 * } else {
 *   Rd = Rs1;
 * }
 * ~~~
 *
 * \param [in]  a    long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
#define __RV_SRAI_U(a, b)    \
    ({    \
        register long result;    \
        register long __a = (long)(a);    \
        __ASM volatile("srai.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.125. SRAI.u ===== */

/* ===== Inline Function Start for 3.126.1. SRA8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRA8 (SIMD 8-bit Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRA8 Rd, Rs1, Rs2
 * SRA8.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 8-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA8.u
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else { // SRA8
 *     Rd.B[x] = SE8(Rd.B[x][7:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA8(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.126.1. SRA8 ===== */

/* ===== Inline Function Start for 3.126.2. SRA8.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRA8.u (SIMD 8-bit Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRA8 Rd, Rs1, Rs2
 * SRA8.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 3-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 8-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA8.u
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else { // SRA8
 *     Rd.B[x] = SE8(Rd.B[x][7:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA8_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sra8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.126.2. SRA8.u ===== */

/* ===== Inline Function Start for 3.127.1. SRAI8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRAI8 (SIMD 8-bit Shift Right Arithmetic Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRAI8 Rd, Rs1, imm3u
 * SRAI8.u Rd, Rs1, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u
 * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 8-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA8.u
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else { // SRA8
 *     Rd.B[x] = SE8(Rd.B[x][7:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRAI8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srai8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.127.1. SRAI8 ===== */

/* ===== Inline Function Start for 3.127.2. SRAI8.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRAI8.u (SIMD 8-bit Rounding Shift Right Arithmetic Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRAI8 Rd, Rs1, imm3u
 * SRAI8.u Rd, Rs1, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit element arithmetic right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the imm3u
 * constant. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 8-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA8.u
 *     res[7:-1] = SE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[7:0];
 *   } else { // SRA8
 *     Rd.B[x] = SE8(Rd.B[x][7:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRAI8_U(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srai8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.127.2. SRAI8.u ===== */

/* ===== Inline Function Start for 3.128.1. SRA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRA16 (SIMD 16-bit Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRA16 Rd, Rs1, Rs2
 * SRA16.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 16-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * if (sa != 0) {
 *   if (`.u` form) { // SRA16.u
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else { // SRA16
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("sra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.128.1. SRA16 ===== */

/* ===== Inline Function Start for 3.128.2. SRA16.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRA16.u (SIMD 16-bit Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRA16 Rd, Rs1, Rs2
 * SRA16.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 4-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 16-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * if (sa != 0) {
 *   if (`.u` form) { // SRA16.u
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else { // SRA16
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("sra16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.128.2. SRA16.u ===== */

/* ===== Inline Function Start for 3.129.1. SRAI16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRAI16 (SIMD 16-bit Shift Right Arithmetic Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRAI16 Rd, Rs1, imm4u
 * SRAI16.u Rd, Rs1, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is
 * an immediate value. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the
 * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
 * significant discarded bit of each 16-bit data to calculate the final results. And the results are written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4u[3:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRAI16.u
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else { // SRAI16
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRAI16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srai16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.129.1. SRAI16 ===== */

/* ===== Inline Function Start for 3.129.2. SRAI16.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRAI16.u (SIMD 16-bit Rounding Shift Right Arithmetic Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRAI16 Rd, Rs1, imm4u
 * SRAI16.u Rd, Rs1, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements arithmetic right shift operations simultaneously. The shift amount is
 * an immediate value. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the 16-bit data elements. The shift amount is specified by the
 * imm4u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
 * significant discarded bit of each 16-bit data to calculate the final results. And the results are written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4u[3:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRAI16.u
 *     res[15:-1] = SE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[15:0];
 *   } else { // SRAI16
 *     Rd.H[x] = SE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRAI16_U(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srai16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.129.2. SRAI16.u ===== */

/* ===== Inline Function Start for 3.130.1. SRL8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRL8 (SIMD 8-bit Shift Right Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRL8 Rt, Ra, Rb
 * SRL8.u Rt, Ra, Rb
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
 * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
 * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded
 * bit of each 8-bit data element to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRL8.u
 *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[8:1];
 *   } else { // SRL8
 *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL8(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.130.1. SRL8 ===== */

/* ===== Inline Function Start for 3.130.2. SRL8.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRL8.u (SIMD 8-bit Rounding Shift Right Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRL8 Rt, Ra, Rb
 * SRL8.u Rt, Ra, Rb
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
 * filled with zero. The shift amount is specified by the low-order 3-bits of the value in the Rs2 register.
 * For the rounding operation of the `.u` form, a value of 1 is added to the most significant discarded
 * bit of each 8-bit data element to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRL8.u
 *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[8:1];
 *   } else { // SRL8
 *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL8_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl8.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.130.2. SRL8.u ===== */

/* ===== Inline Function Start for 3.131.1. SRLI8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRLI8 (SIMD 8-bit Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRLI8 Rt, Ra, imm3u
 * SRLI8.u Rt, Ra, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
 * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of
 * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to
 * calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI8.u
 *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[8:1];
 *   } else { // SRLI8
 *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRLI8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srli8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.131.1. SRLI8 ===== */

/* ===== Inline Function Start for 3.131.2. SRLI8.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
 * \brief SRLI8.u (SIMD 8-bit Rounding Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRLI8 Rt, Ra, imm3u
 * SRLI8.u Rt, Ra, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 8-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits are
 * filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of
 * the `.u` form, a value of 1 is added to the most significant discarded bit of each 8-bit data element to
 * calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm3u[2:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI8.u
 *     res[8:0] = ZE9(Rs1.B[x][7:sa-1]) + 1;
 *     Rd.B[x] = res[8:1];
 *   } else { // SRLI8
 *     Rd.B[x] = ZE8(Rs1.B[x][7:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRLI8_U(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srli8.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.131.2. SRLI8.u ===== */

/* ===== Inline Function Start for 3.132.1. SRL16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRL16 (SIMD 16-bit Shift Right Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRL16 Rt, Ra, Rb
 *  SRL16.u Rt, Ra, Rb
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2
 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 16-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRL16.u
 *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[16:1];
 *   } else { // SRL16
 *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.132.1. SRL16 ===== */

/* ===== Inline Function Start for 3.132.2. SRL16.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRL16.u (SIMD 16-bit Rounding Shift Right Logical)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRL16 Rt, Ra, Rb
 *  SRL16.u Rt, Ra, Rb
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The `.u` form performs additional rounding upoperations on the shifted results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the low-order 4-bits of the value in the Rs2
 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 16-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[3:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRL16.u
 *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[16:1];
 *   } else { // SRL16
 *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl16.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.132.2. SRL16.u ===== */

/* ===== Inline Function Start for 3.133.1. SRLI16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRLI16 (SIMD 16-bit Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRLI16 Rt, Ra, imm4u
 * SRLI16.u Rt, Ra, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding
 * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit
 * data element to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4u;
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI16.u
 *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[16:1];
 *   } else { // SRLI16
 *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRLI16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srli16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.133.1. SRLI16 ===== */

/* ===== Inline Function Start for 3.133.2. SRLI16.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
 * \brief SRLI16.u (SIMD 16-bit Rounding Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SRLI16 Rt, Ra, imm4u
 * SRLI16.u Rt, Ra, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 16-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the imm4u constant. For the rounding
 * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 16-bit
 * data element to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm4u;
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI16.u
 *     res[16:0] = ZE17(Rs1.H[x][15:sa-1]) + 1;
 *     Rd.H[x] = res[16:1];
 *   } else { // SRLI16
 *     Rd.H[x] = ZE16(Rs1.H[x][15:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_SRLI16_U(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("srli16.u %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.133.2. SRLI16.u ===== */

/* ===== Inline Function Start for 3.134. STAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief STAS16 (SIMD 16-bit Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * STAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element addition and 16-bit integer element subtraction in a 32-bit
 * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit integer element in [31:16] of 32-bit chunks in Rs1 with
 * the 16-bit integer element in [31:16] of 32-bit chunks in Rs2, and writes the result to [31:16] of 32-bit
 * chunks in Rd; at the same time, it subtracts the 16-bit integer element in [15:0] of 32-bit chunks in
 * Rs2 from the 16-bit integer element in [15:0] of 32-bit chunks, and writes the result to [15:0] of 32-
 * bit chunks in Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = Rs1.W[x][31:16] + Rs2.W[x][31:16];
 * Rd.W[x][15:0] = Rs1.W[x][15:0] - Rs2.W[x][15:0];
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_STAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("stas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.134. STAS16 ===== */

/* ===== Inline Function Start for 3.135. STSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief STSA16 (SIMD 16-bit Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * STSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element subtraction and 16-bit integer element addition in a 32-bit
 * chunk simultaneously. Operands are from corresponding positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit integer element in [31:16] of 32-bit chunks in Rs2
 * from the 16-bit integer element in [31:16] of 32-bit chunks in Rs1, and writes the result to [31:16] of
 * 32-bit chunks in Rd; at the same time, it adds the 16-bit integer element in [15:0] of 32-bit chunks in
 * Rs2 with the 16-bit integer element in [15:0] of 32-bit chunks in Rs1, and writes the result to [15:0] of
 * 32-bit chunks in Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = Rs1.W[x][31:16] - Rs2.W[x][31:16];
 * Rd.W[x][15:0] = Rs1.W[x][15:0] + Rs2.W[x][15:0];
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_STSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("stsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.135. STSA16 ===== */

/* ===== Inline Function Start for 3.136. SUB8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief SUB8 (SIMD 8-bit Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SUB8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit integer element subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit integer elements in Rs2 from the 8-bit integer
 * elements in Rs1, and then writes the result to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned subtraction.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = Rs1.B[x] - Rs2.B[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUB8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("sub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.136. SUB8 ===== */

/* ===== Inline Function Start for 3.137. SUB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief SUB16 (SIMD 16-bit Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * SUB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit integer element subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit integer elements in Rs2 from the 16-bit integer
 * elements in Rs1, and then writes the result to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned subtraction.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = Rs1.H[x] - Rs2.H[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("sub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.137. SUB16 ===== */

/* ===== Inline Function Start for 3.138. SUB64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief SUB64 (64-bit Subtraction)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * SUB64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 64-bit signed or unsigned integer subtraction.
 *
 * **RV32 Description**:\n
 * This instruction subtracts the 64-bit integer of an even/odd pair of registers
 * specified by Rs2(4,1) from the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1),
 * and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * This instruction subtracts the 64-bit integer of Rs2 from the 64-bit integer of Rs1,
 * and then writes the 64-bit result to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned subtraction.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 * R[t_H].R[t_L] = R[a_H].R[a_L] - R[b_H].R[b_L];
 * * RV64:
 * Rd = Rs1 - Rs2;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_SUB64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("sub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.138. SUB64 ===== */

/* ===== Inline Function Start for 3.139.1. SUNPKD810 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief SUNPKD810 (Signed Unpacking Bytes 1 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
 * of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
 * // SUNPKD810, x=1,y=0
 * // SUNPKD820, x=2,y=0
 * // SUNPKD830, x=3,y=0
 * // SUNPKD831, x=3,y=1
 * // SUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUNPKD810(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("sunpkd810 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.139.1. SUNPKD810 ===== */

/* ===== Inline Function Start for 3.139.2. SUNPKD820 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief SUNPKD820 (Signed Unpacking Bytes 2 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
 * of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
 * // SUNPKD810, x=1,y=0
 * // SUNPKD820, x=2,y=0
 * // SUNPKD830, x=3,y=0
 * // SUNPKD831, x=3,y=1
 * // SUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUNPKD820(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("sunpkd820 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.139.2. SUNPKD820 ===== */

/* ===== Inline Function Start for 3.139.3. SUNPKD830 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief SUNPKD830 (Signed Unpacking Bytes 3 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
 * of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
 * // SUNPKD810, x=1,y=0
 * // SUNPKD820, x=2,y=0
 * // SUNPKD830, x=3,y=0
 * // SUNPKD831, x=3,y=1
 * // SUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUNPKD830(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("sunpkd830 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.139.3. SUNPKD830 ===== */

/* ===== Inline Function Start for 3.139.4. SUNPKD831 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief SUNPKD831 (Signed Unpacking Bytes 3 & 1)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
 * of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
 * // SUNPKD810, x=1,y=0
 * // SUNPKD820, x=2,y=0
 * // SUNPKD830, x=3,y=0
 * // SUNPKD831, x=3,y=1
 * // SUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUNPKD831(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("sunpkd831 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.139.4. SUNPKD831 ===== */

/* ===== Inline Function Start for 3.139.5. SUNPKD832 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief SUNPKD832 (Signed Unpacking Bytes 3 & 2)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte *x and byte y* of 32-bit chunks in a register into two 16-bit signed halfwords
 * of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `SUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit signed halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = SE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = SE16(Rs1.W[m].B[y])
 * // SUNPKD810, x=1,y=0
 * // SUNPKD820, x=2,y=0
 * // SUNPKD830, x=3,y=0
 * // SUNPKD831, x=3,y=1
 * // SUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUNPKD832(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("sunpkd832 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.139.5. SUNPKD832 ===== */

/* ===== Inline Function Start for 3.140. SWAP8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief SWAP8 (Swap Byte within Halfword)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SWAP8 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Swap the bytes within each halfword of a register.
 *
 * **Description**:\n
 * This instruction swaps the bytes within each halfword of Rs1 and writes the result to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = CONCAT(Rs1.H[x][7:0],Rs1.H[x][15:8]);
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SWAP8(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("swap8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.140. SWAP8 ===== */

/* ===== Inline Function Start for 3.141. SWAP16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief SWAP16 (Swap Halfword within Word)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * SWAP16 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Swap the 16-bit halfwords within each word of a register.
 *
 * **Description**:\n
 * This instruction swaps the 16-bit halfwords within each word of Rs1 and writes the
 * result to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = CONCAT(Rs1.W[x][15:0],Rs1.H[x][31:16]);
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SWAP16(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("swap16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.141. SWAP16 ===== */

/* ===== Inline Function Start for 3.142. UCLIP8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief UCLIP8 (SIMD 8-bit Unsigned Clip Value)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCLIP8 Rt, Ra, imm3u
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 8-bit signed elements of a register into an unsigned range simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 8-bit signed elements stored in Rs1 into an unsigned integer
 * range between 2^imm3u-1 and 0, and writes the limited results to Rd. For example, if imm3u is 3, the 8-
 * bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.H[x];
 * if (src > (2^imm3u)-1) {
 *   src = (2^imm3u)-1;
 *   OV = 1;
 * } else if (src < 0) {
 *   src = 0;
 *   OV = 1;
 * }
 * Rd.H[x] = src;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_UCLIP8(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("uclip8 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.142. UCLIP8 ===== */

/* ===== Inline Function Start for 3.143. UCLIP16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief UCLIP16 (SIMD 16-bit Unsigned Clip Value)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCLIP16 Rt, Ra, imm4u
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 16-bit signed elements of a register into an unsigned range simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 16-bit signed elements stored in Rs1 into an unsigned
 * integer range between 2imm4u-1 and 0, and writes the limited results to Rd. For example, if imm4u is
 * 3, the 16-bit input values should be saturated between 7 and 0. If saturation is performed, set OV bit
 * to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.H[x];
 * if (src > (2^imm4u)-1) {
 *   src = (2^imm4u)-1;
 *   OV = 1;
 * } else if (src < 0) {
 *   src = 0;
 *   OV = 1;
 * }
 * Rd.H[x] = src;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_UCLIP16(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("uclip16 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.143. UCLIP16 ===== */

/* ===== Inline Function Start for 3.144. UCLIP32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_PART_SIMD_MISC
 * \brief UCLIP32 (SIMD 32-bit Unsigned Clip Value)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCLIP32 Rd, Rs1, imm5u[4:0]
 * ~~~
 *
 * **Purpose**:\n
 * Limit the 32-bit signed integer elements of a register into an unsigned range
 * simultaneously.
 *
 * **Description**:\n
 * This instruction limits the 32-bit signed integer elements stored in Rs1 into an
 * unsigned integer range between 2imm5u-1 and 0, and writes the limited results to Rd. For example, if
 * imm5u is 3, the 32-bit input values should be saturated between 7 and 0. If saturation is performed,
 * set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.W[x];
 * if (src > (2^imm5u)-1) {
 *   src = (2^imm5u)-1;
 *   OV = 1;
 * } else if (src < 0) {
 *   src = 0;
 *   OV = 1;
 * }
 * Rd.W[x] = src
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_UCLIP32(a, b)    \
    ({    \
        register unsigned long result;    \
        register unsigned long __a = (unsigned long)(a);    \
        __ASM volatile("uclip32 %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.144. UCLIP32 ===== */

/* ===== Inline Function Start for 3.145. UCMPLE8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
 * \brief UCMPLE8 (SIMD 8-bit Unsigned Compare Less Than & Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCMPLE8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer elements less than & equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
 * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it
 * is true, the result is 0xFF; otherwise, the result is 0x0. The four comparison results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] <=u Rs2.B[x])? 0xff : 0x0;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UCMPLE8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ucmple8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.145. UCMPLE8 ===== */

/* ===== Inline Function Start for 3.146. UCMPLE16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_CMP
 * \brief UCMPLE16 (SIMD 16-bit Unsigned Compare Less Than & Equal)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCMPLE16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer elements less than & equal comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit
 * unsigned integer elements in Rs2 to see if the one in Rs1 is less than or equal to the one in Rs2. If it
 * is true, the result is 0xFFFF; otherwise, the result is 0x0. The element comparison results are
 * written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] <=u Rs2.H[x])? 0xffff : 0x0;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UCMPLE16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ucmple16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.146. UCMPLE16 ===== */

/* ===== Inline Function Start for 3.147. UCMPLT8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_CMP
 * \brief UCMPLT8 (SIMD 8-bit Unsigned Compare Less Than)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UCMPLT8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer elements less than comparisons simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
 * unsigned integer elements in Rs2 to see if the one in Rs1 is less than the one in Rs2. If it is true, the
 * result is 0xFF; otherwise, the result is 0x0. The element comparison results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x]  (2^8)-1) {
 *   res[x] = (2^8)-1;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKADD8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.149. UKADD8 ===== */

/* ===== Inline Function Start for 3.150. UKADD16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKADD16 (SIMD 16-bit Unsigned Saturating Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKADD16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit
 * unsigned integer elements in Rs2. If any of the results are beyond the 16-bit unsigned number
 * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] + Rs2.H[x];
 * if (res[x] > (2^16)-1) {
 *   res[x] = (2^16)-1;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKADD16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.150. UKADD16 ===== */

/* ===== Inline Function Start for 3.151. UKADD64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief UKADD64 (64-bit Unsigned Saturating Addition)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * UKADD64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add two 64-bit unsigned integers. The result is saturated to the U64 range.
 *
 * **RV32 Description**:\n
 * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers
 * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by
 * Rs2(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the
 * range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers
 * specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned
 * integer in Rs2. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to
 * the range and the OV bit is set to 1. The saturated result is written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
 * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
 * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
 * result = R[a_H].R[a_L] + R[b_H].R[b_L];
 * if (result > (2^64)-1) {
 *   result = (2^64)-1; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * * RV64:
 * result = Rs1 + Rs2;
 * if (result > (2^64)-1) {
 *   result = (2^64)-1; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_UKADD64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("ukadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.151. UKADD64 ===== */

/* ===== Inline Function Start for 3.152. UKADDH ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief UKADDH (Unsigned Addition with U16 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * UKADDH Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add the unsigned lower 32-bit content of two registers with U16 saturation.
 *
 * **Description**:\n
 * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit
 * content of Rs2. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then
 * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] + Rs2.W[0];
 * if (tmp > (2^16)-1) {
 *   tmp = (2^16)-1;
 *   OV = 1;
 * }
 * Rd = SE(tmp[15:0]);
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKADDH(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ukaddh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.152. UKADDH ===== */

/* ===== Inline Function Start for 3.153. UKADDW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief UKADDW (Unsigned Addition with U32 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * UKADDW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add the unsigned lower 32-bit content of two registers with U32 saturation.
 *
 * **Description**:\n
 * The unsigned lower 32-bit content of Rs1 is added with the unsigned lower 32-bit
 * content of Rs2. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then
 * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] + Rs2.W[0];
 * if (tmp > (2^32)-1) {
 *   tmp[31:0] = (2^32)-1;
 *   OV = 1;
 * }
 * Rd = tmp[31:0]; // RV32
 * Rd = SE(tmp[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKADDW(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ukaddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.153. UKADDW ===== */

/* ===== Inline Function Start for 3.154. UKCRAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKCRAS16 (SIMD 16-bit Unsigned Saturating Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKCRAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned
 * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from crossed
 * positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2; at the same time, it
 * subtracts the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 from the 16-bit
 * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit
 * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1.
 * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit
 * chunks in Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] + Rs2.W[x][15:0];
 * res2 = Rs1.W[x][15:0] - Rs2.W[x][31:16];
 * if (res1 > (2^16)-1) {
 *   res1 = (2^16)-1;
 *   OV = 1;
 * }
 * if (res2 < 0) {
 *   res2 = 0;
 *   OV = 1;
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKCRAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.154. UKCRAS16 ===== */

/* ===== Inline Function Start for 3.155. UKCRSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKCRSA16 (SIMD 16-bit Unsigned Saturating Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKCRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned
 * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from crossed
 * positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer element in [15:0] of 32-bit
 * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the
 * same time, it adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2 with the 16-
 * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the
 * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set
 * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of
 * 32-bit chunks in Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] - Rs2.W[x][15:0];
 * res2 = Rs1.W[x][15:0] + Rs2.W[x][31:16];
 * if (res1 < 0) {
 *   res1 = 0;
 *   OV = 1;
 * } else if (res2 > (2^16)-1) {
 *   res2 = (2^16)-1;
 *   OV = 1;
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKCRSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.155. UKCRSA16 ===== */

/* ===== Inline Function Start for 3.156. UKMAR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief UKMAR64 (Unsigned Multiply and Saturating Add to 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * UKMAR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication
 * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is
 * saturated to the U64 range and written back to the pair of registers (RV32) or the register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
 * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers
 * specified by Rd(4,1) with unlimited precision. If the 64-bit addition result is beyond the U64 number
 * range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is
 * written back to the even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
 * It adds the 64-bit multiplication results to the 64-bit unsigned data in Rd with unlimited precision. If
 * the 64-bit addition result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the
 * range and the OV bit is set to 1. The saturated result is written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * result = R[t_H].R[t_L] + (Rs1 * Rs2);
 * if (result > (2^64)-1) {
 *   result = (2^64)-1; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * * RV64:
 * // `result` has unlimited precision
 * result = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]);
 * if (result > (2^64)-1) {
 *   result = (2^64)-1; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  t    unsigned long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_UKMAR64(unsigned long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("ukmar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.156. UKMAR64 ===== */

/* ===== Inline Function Start for 3.157. UKMSR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief UKMSR64 (Unsigned Multiply and Saturating Subtract from 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * UKMSR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit unsigned elements in two registers and subtract the 64-bit
 * multiplication results from the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64).
 * The result is saturated to the U64 range and written back to the pair of registers (RV32) or a register
 * (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
 * subtracts the 64-bit multiplication result from the 64-bit unsigned data of an even/odd pair of
 * registers specified by Rd(4,1) with unlimited precision. If the 64-bit subtraction result is beyond the
 * U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The
 * saturated result is written back to the even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
 * It subtracts the 64-bit multiplication results from the 64-bit unsigned data of Rd with unlimited
 * precision. If the 64-bit subtraction result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is
 * saturated to the range and the OV bit is set to 1. The saturated result is written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * result = R[t_H].R[t_L] - (Rs1 u* Rs2);
 * if (result < 0) {
 *   result = 0; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * * RV64:
 * // `result` has unlimited precision
 * result = Rd - (Rs1.W[0] u* Rs2.W[0]) - (Rs1.W[1] u* Rs2.W[1]);
 * if (result < 0) {
 *   result = 0; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  t    unsigned long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_UKMSR64(unsigned long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("ukmsr64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.157. UKMSR64 ===== */

/* ===== Inline Function Start for 3.158. UKSTAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKSTAS16 (SIMD 16-bit Unsigned Saturating Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKSTAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 16-bit unsigned integer element saturating addition and one 16-bit unsigned
 * integer element saturating subtraction in a 32-bit chunk simultaneously. Operands are from
 * corresponding positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer element in [31:16] of 32-bit chunks in
 * Rs1 with the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs2; at the same time, it
 * subtracts the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 from the 16-bit
 * unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the 16-bit
 * unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1.
 * The saturated results are written to [31:16] of 32-bit chunks in Rd for addition and [15:0] of 32-bit
 * chunks in Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] + Rs2.W[x][31:16];
 * res2 = Rs1.W[x][15:0] - Rs2.W[x][15:0];
 * if (res1 > (2^16)-1) {
 *   res1 = (2^16)-1;
 *   OV = 1;
 * }
 * if (res2 < 0) {
 *   res2 = 0;
 *   OV = 1;
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSTAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.158. UKSTAS16 ===== */

/* ===== Inline Function Start for 3.159. UKSTSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKSTSA16 (SIMD 16-bit Unsigned Saturating Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKSTSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 16-bit unsigned integer element saturating subtraction and one 16-bit unsigned
 * integer element saturating addition in a 32-bit chunk simultaneously. Operands are from
 * corresponding positions in 32-bit chunks.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer element in [31:16] of 32-bit
 * chunks in Rs2 from the 16-bit unsigned integer element in [31:16] of 32-bit chunks in Rs1; at the
 * same time, it adds the 16-bit unsigned integer element in [15:0] of 32-bit chunks in Rs2 with the 16-
 * bit unsigned integer element in [15:0] of 32-bit chunks in Rs1. If any of the results are beyond the
 * 16-bit unsigned number range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set
 * to 1. The saturated results are written to [31:16] of 32-bit chunks in Rd for subtraction and [15:0] of
 * 32-bit chunks in Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[x][31:16] - Rs2.W[x][31:16];
 * res2 = Rs1.W[x][15:0] + Rs2.W[x][15:0];
 * if (res1 < 0) {
 *   res1 = 0;
 *   OV = 1;
 * } else if (res2 > (2^16)-1) {
 *   res2 = (2^16)-1;
 *   OV = 1;
 * }
 * Rd.W[x][31:16] = res1;
 * Rd.W[x][15:0] = res2;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSTSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.159. UKSTSA16 ===== */

/* ===== Inline Function Start for 3.160. UKSUB8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief UKSUB8 (SIMD 8-bit Unsigned Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKSUB8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit
 * unsigned integer elements in Rs1. If any of the results are beyond the 8-bit unsigned number range
 * (0 <= RES <= 28-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
 * written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.B[x] - Rs2.B[x];
 * if (res[x] < 0) {
 *   res[x] = 0;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSUB8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.160. UKSUB8 ===== */

/* ===== Inline Function Start for 3.161. UKSUB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief UKSUB16 (SIMD 16-bit Unsigned Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UKSUB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit
 * unsigned integer elements in Rs1. If any of the results are beyond the 16-bit unsigned number
 * range (0 <= RES <= 2^16-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] - Rs2.H[x];
 * if (res[x] < 0) {
 *   res[x] = 0;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSUB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.161. UKSUB16 ===== */

/* ===== Inline Function Start for 3.162. UKSUB64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief UKSUB64 (64-bit Unsigned Saturating Subtraction)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * UKSUB64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 64-bit signed integer subtraction. The result is saturated to the U64 range.
 *
 * **RV32 Description**:\n
 * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of
 * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers
 * specified by Rs1(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is
 * saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd
 * pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the operand and the even `2d`
 * register of the pair contains the low 32-bit of the operand.
 *
 * **RV64 Description**:\n
 * This instruction subtracts the 64-bit unsigned integer of Rs2 from the 64-bit
 * unsigned integer of an even/odd pair of Rs1. If the 64-bit result is beyond the U64 number range (0 <=
 * U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
 * b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
 * result = R[a_H].R[a_L] - R[b_H].R[b_L];
 * if (result < 0) {
 *   result = 0; OV = 1;
 * }
 * R[t_H].R[t_L] = result;
 * * RV64
 * result = Rs1 - Rs2;
 * if (result < 0) {
 *   result = 0; OV = 1;
 * }
 * Rd = result;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_UKSUB64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("uksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.162. UKSUB64 ===== */

/* ===== Inline Function Start for 3.163. UKSUBH ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q15_SAT_ALU
 * \brief UKSUBH (Unsigned Subtraction with U16 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * UKSUBH Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract the unsigned lower 32-bit content of two registers with U16 saturation.
 *
 * **Description**:\n
 * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit
 * content of Rs1. And the result is saturated to the 16-bit unsigned integer range of [0, 2^16-1] and then
 * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] - Rs2.W[0];
 * if (tmp > (2^16)-1) {
 *   tmp = (2^16)-1;
 *   OV = 1;
 * }
 * else if (tmp < 0) {
 *   tmp = 0;
 *   OV = 1;
 * }
 * Rd = SE(tmp[15:0]);
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSUBH(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("uksubh %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.163. UKSUBH ===== */

/* ===== Inline Function Start for 3.164. UKSUBW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_Q31_SAT_ALU
 * \brief UKSUBW (Unsigned Subtraction with U32 Saturation)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * UKSUBW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract the unsigned lower 32-bit content of two registers with unsigned 32-bit
 * saturation.
 *
 * **Description**:\n
 * The unsigned lower 32-bit content of Rs2 is subtracted from the unsigned lower 32-bit
 * content of Rs1. And the result is saturated to the 32-bit unsigned integer range of [0, 2^32-1] and then
 * sign-extended and written to Rd. If saturation happens, this instruction sets the OV flag.
 *
 * **Operations**:\n
 * ~~~
 * tmp = Rs1.W[0] - Rs2.W[0];
 * if (tmp < 0) {
 *   tmp[31:0] = 0;
 *   OV = 1;
 * }
 * Rd = tmp[31:0]; // RV32
 * Rd = SE(tmp[31:0]); // RV64
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSUBW(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("uksubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.164. UKSUBW ===== */

/* ===== Inline Function Start for 3.165. UMAR64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_MULT_64B_ADDSUB
 * \brief UMAR64 (Unsigned Multiply and Add to 64-Bit Data)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * UMAR64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the 32-bit unsigned elements in two registers and add the 64-bit multiplication
 * results to the 64-bit unsigned data of a pair of registers (RV32) or a register (RV64). The result is
 * written back to the pair of registers (RV32) or a register (RV64).
 *
 * **RV32 Description**:\n
 * This instruction multiplies the 32-bit unsigned data of Rs1 with that of Rs2. It
 * adds the 64-bit multiplication result to the 64-bit unsigned data of an even/odd pair of registers
 * specified by Rd(4,1). The addition result is written back to the even/odd pair of registers specified by
 * Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction multiplies the 32-bit unsigned elements of Rs1 with that of Rs2.
 * It adds the 64-bit multiplication results to the 64-bit unsigned data of Rd. The addition result is
 * written back to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
 * R[t_H].R[t_L] = R[t_H].R[t_L] + (Rs1 * Rs2);
 * * RV64:
 * Rd = Rd + (Rs1.W[0] u* Rs2.W[0]) + (Rs1.W[1] u* Rs2.W[1]);
 * ~~~
 *
 * \param [in]  t    unsigned long long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_UMAR64(unsigned long long t, unsigned long a, unsigned long b)
{
    __ASM volatile("umar64 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.165. UMAR64 ===== */

/* ===== Inline Function Start for 3.166. UMAQA ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_8B_MULT_32B_ADD
 * \brief UMAQA (Unsigned Multiply Four Bytes with 32- bit Adds)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * UMAQA Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do four unsigned 8-bit multiplications from 32-bit chunks of two registers; and then adds
 * the four 16-bit results and the content of corresponding 32-bit chunks of a third register together.
 *
 * **Description**:\n
 * This instruction multiplies the four unsigned 8-bit elements of 32-bit chunks of Rs1 with the four
 * unsigned 8-bit elements of 32-bit chunks of Rs2 and then adds the four results together with the
 * unsigned content of the corresponding 32-bit chunks of Rd. The final results are written back to the
 * corresponding 32-bit chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rd.W[x] + (Rs1.W[x].B[3] u* Rs2.W[x].B[3]) +
 *          (Rs1.W[x].B[2] u* Rs2.W[x].B[2]) + (Rs1.W[x].B[1] u* Rs2.W[x].B[1]) +
 *          (Rs1.W[x].B[0] u* Rs2.W[x].B[0]);
 * Rd.W[x] = res[x];
 * for RV32: x=0,
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UMAQA(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("umaqa %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 3.166. UMAQA ===== */

/* ===== Inline Function Start for 3.167. UMAX8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief UMAX8 (SIMD 8-bit Unsigned Maximum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UMAX8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit unsigned integer elements in Rs1 with the four 8-
 * bit unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * two selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] >u Rs2.B[x])? Rs1.B[x] : Rs2.B[x];
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UMAX8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("umax8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.167. UMAX8 ===== */

/* ===== Inline Function Start for 3.168. UMAX16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_MISC
 * \brief UMAX16 (SIMD 16-bit Unsigned Maximum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UMAX16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 16-bit unsigned integer elements in Rs1 with the 16-bit
 * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] >u Rs2.H[x])? Rs1.H[x] : Rs2.H[x];
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UMAX16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("umax16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.168. UMAX16 ===== */

/* ===== Inline Function Start for 3.169. UMIN8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_MISC
 * \brief UMIN8 (SIMD 8-bit Unsigned Minimum)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * UMIN8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer elements finding minimum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 8-bit unsigned integer elements in Rs1 with the 8-bit
 * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] > 1;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URADD8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uradd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.174. URADD8 ===== */

/* ===== Inline Function Start for 3.175. URADD16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URADD16 (SIMD 16-bit Unsigned Halving Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URADD16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element additions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer elements in Rs1 with the 16-bit
 * unsigned integer elements in Rs2. The results are first logically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFF, Rb = 0x7FFF Rt = 0x7FFF
 * * Ra = 0x8000, Rb = 0x8000 Rt = 0x8000
 * * Ra = 0x4000, Rb = 0x8000 Rt = 0x6000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] + Rs2.H[x]) u>> 1;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URADD16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uradd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.175. URADD16 ===== */

/* ===== Inline Function Start for 3.176. URADD64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief URADD64 (64-bit Unsigned Halving Addition)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * URADD64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add two 64-bit unsigned integers. The result is halved to avoid overflow or saturation.
 *
 * **RV32 Description**:\n
 * This instruction adds the 64-bit unsigned integer of an even/odd pair of registers
 * specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by
 * Rs2(4,1). The 64-bit addition result is first logically right-shifted by 1 bit and then written to an
 * even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned
 * integer Rs2. The 64-bit addition result is first logically right-shifted by 1 bit and then written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
 * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
 * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
 * R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) u>> 1;
 * * RV64:
 * Rd = (Rs1 + Rs2) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_URADD64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("uradd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.176. URADD64 ===== */

/* ===== Inline Function Start for 3.177. URADDW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief URADDW (32-bit Unsigned Halving Addition)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * URADDW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Add 32-bit unsigned integers and the results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the first 32-bit unsigned integer in Rs1 with the first 32-bit
 * unsigned integer in Rs2. The result is first logically right-shifted by 1 bit and then sign-extended and
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFFFFFF, Rb = 0x7FFFFFFF Rt = 0x7FFFFFFF
 * * Ra = 0x80000000, Rb = 0x80000000 Rt = 0x80000000
 * * Ra = 0x40000000, Rb = 0x80000000 Rt = 0x60000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Rd[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1;
 * * RV64:
 * resw[31:0] = (Rs1[31:0] + Rs2[31:0]) u>> 1;
 * Rd[63:0] = SE(resw[31:0]);
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URADDW(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("uraddw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.177. URADDW ===== */

/* ===== Inline Function Start for 3.178. URCRAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URCRAS16 (SIMD 16-bit Unsigned Halving Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URCRAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element
 * subtraction in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
 * The results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1
 * with the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned
 * integer in [31:16] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks
 * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32-
 * bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD16` and `URSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][15:0]) u>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][31:16]) u>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URCRAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urcras16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.178. URCRAS16 ===== */

/* ===== Inline Function Start for 3.179. URCRSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URCRSA16 (SIMD 16-bit Unsigned Halving Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URCRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element
 * addition in a 32-bit chunk simultaneously. Operands are from crossed positions in 32-bit chunks.
 * The results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer in [15:0] of 32-bit chunks in Rs2
 * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned
 * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [31:16] of 32-bit chunks
 * in Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit
 * chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD16` and `URSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][15:0]) u>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][31:16]) u>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URCRSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urcrsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.179. URCRSA16 ===== */

/* ===== Inline Function Start for 3.180. URSTAS16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URSTAS16 (SIMD 16-bit Unsigned Halving Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URSTAS16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element addition and 16-bit unsigned integer element
 * subtraction in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit
 * chunks. The results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1
 * with the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2, and subtracts the 16-bit unsigned
 * integer in [15:0] of 32-bit chunks in Rs2 from the 16-bit unsigned integer in [15:0] of 32-bit chunks
 * in Rs1. The element results are first logically right-shifted by 1 bit and then written to [31:16] of 32-
 * bit chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD16` and `URSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] + Rs2.W[x][31:16]) u>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] - Rs2.W[x][15:0]) u>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSTAS16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urstas16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.180. URSTAS16 ===== */

/* ===== Inline Function Start for 3.181. URSTSA16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URSTSA16 (SIMD 16-bit Unsigned Halving Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URCRSA16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element subtraction and 16-bit unsigned integer element
 * addition in a 32-bit chunk simultaneously. Operands are from corresponding positions in 32-bit
 * chunks. The results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs2
 * from the 16-bit unsigned integer in [31:16] of 32-bit chunks in Rs1, and adds the 16-bit unsigned
 * integer in [15:0] of 32-bit chunks in Rs1 with the 16-bit unsigned integer in [15:0] of 32-bit chunks in
 * Rs2. The two results are first logically right-shifted by 1 bit and then written to [31:16] of 32-bit
 * chunks in Rd and [15:0] of 32-bit chunks in Rd.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD16` and `URSUB16` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:16] = (Rs1.W[x][31:16] - Rs2.W[x][31:16]) u>> 1;
 * Rd.W[x][15:0] = (Rs1.W[x][15:0] + Rs2.W[x][15:0]) u>> 1;
 * for RV32, x=0
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSTSA16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urstsa16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.181. URSTSA16 ===== */

/* ===== Inline Function Start for 3.182. URSUB8 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_ADDSUB
 * \brief URSUB8 (SIMD 8-bit Unsigned Halving Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URSUB8 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit unsigned integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit unsigned integer elements in Rs2 from the 8-bit
 * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7F, Rb = 0x80 Rt = 0xFF
 * * Ra = 0x80, Rb = 0x7F Rt = 0x00
 * * Ra = 0x80, Rb = 0x40 Rt = 0x20
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.B[x] = (Rs1.B[x] - Rs2.B[x]) u>> 1;
 * for RV32: x=3...0,
 * for RV64: x=7...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSUB8(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ursub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.182. URSUB8 ===== */

/* ===== Inline Function Start for 3.183. URSUB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_16B_ADDSUB
 * \brief URSUB16 (SIMD 16-bit Unsigned Halving Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * URSUB16 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit unsigned integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit unsigned integer elements in Rs2 from the 16-bit
 * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFF, Rb = 0x8000 Rt = 0xFFFF
 * * Ra = 0x8000, Rb = 0x7FFF Rt = 0x0000
 * * Ra = 0x8000, Rb = 0x4000 Rt = 0x2000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.H[x] = (Rs1.H[x] - Rs2.H[x]) u>> 1;
 * for RV32: x=1...0,
 * for RV64: x=3...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSUB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ursub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.183. URSUB16 ===== */

/* ===== Inline Function Start for 3.184. URSUB64 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_64B_ADDSUB
 * \brief URSUB64 (64-bit Unsigned Halving Subtraction)
 * \details
 * **Type**: DSP (64-bit Profile)
 *
 * **Syntax**:\n
 * ~~~
 * URSUB64 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 64-bit unsigned integer subtraction. The result is halved to avoid overflow or
 * saturation.
 *
 * **RV32 Description**:\n
 * This instruction subtracts the 64-bit unsigned integer of an even/odd pair of
 * registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers
 * specified by Rs1(4,1). The subtraction result is first logically right-shifted by 1 bit and then written
 * to an even/odd pair of registers specified by Rd(4,1).
 * Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair
 * includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the result and the even `2d` register
 * of the pair contains the low 32-bit of the result.
 *
 * **RV64 Description**:\n
 * This instruction subtracts the 64-bit unsigned integer in Rs2 from the 64-bit
 * unsigned integer in Rs1. The subtraction result is first logically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
 * a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
 * b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
 * R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) u>> 1;
 * * RV64:
 * Rd = (Rs1 - Rs2) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long long type of value stored in a
 * \param [in]  b    unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_URSUB64(unsigned long long a, unsigned long long b)
{
    register unsigned long long result;
    __ASM volatile("ursub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.184. URSUB64 ===== */

/* ===== Inline Function Start for 3.185. URSUBW ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_32B_COMPUTATION
 * \brief URSUBW (32-bit Unsigned Halving Subtraction)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * URSUBW Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Subtract 32-bit unsigned integers and the result is halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the first 32-bit signed integer in Rs2 from the first 32-bit
 * signed integer in Rs1. The result is first logically right-shifted by 1 bit and then sign-extended and
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0xFFFFFFFF
 * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x00000000
 * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0x20000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Rd[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1;
 * * RV64:
 * resw[31:0] = (Rs1[31:0] - Rs2[31:0]) u>> 1;
 * Rd[63:0] = SE(resw[31:0]);
 * ~~~
 *
 * \param [in]  a    unsigned int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSUBW(unsigned int a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ursubw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.185. URSUBW ===== */

/* ===== Inline Function Start for 3.186. WEXTI ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief WEXTI (Extract Word from 64-bit Immediate)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * WEXTI Rd, Rs1, #LSBloc
 * ~~~
 *
 * **Purpose**:\n
 * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or
 * a register (RV64) starting from a specified immediate LSB bit position.
 *
 * **RV32 Description**:\n
 * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified
 * by Rs1(4,1) starting from a specified immediate LSB bit position, #LSBloc. The extracted word is
 * written to Rd.
 * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d`
 * register of the pair contains the low 32-bit of the 64-bit value.
 *
 * **RV64 Description**:\n
 * This instruction extracts a 32-bit word from a 64-bit value in Rs1 starting from a specified
 * immediate LSB bit position, #LSBloc. The extracted word is sign-extended and written to lower 32-
 * bit of Rd.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs2(4,1),1'b1);
 * src[63:0] = Concat(R[Idx1], R[Idx0]);
 * Rd = src[31+LSBloc:LSBloc];
 * * RV64:
 * ExtractW = Rs1[31+LSBloc:LSBloc];
 * Rd = SE(ExtractW)
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
#define __RV_WEXTI(a, b)    \
    ({    \
        register unsigned long result;    \
        register long long __a = (long long)(a);    \
        __ASM volatile("wexti %0, %1, %2" : "=r"(result) : "r"(__a), "K"(b));    \
        result;    \
    })
/* ===== Inline Function End for 3.186. WEXTI ===== */

/* ===== Inline Function Start for 3.187. WEXT ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_NON_SIMD_MISC
 * \brief WEXT (Extract Word from 64-bit)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * WEXT Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Extract a 32-bit word from a 64-bit value stored in an even/odd pair of registers (RV32) or
 * a register (RV64) starting from a specified LSB bit position in a register.
 *
 * **RV32 Description**:\n
 * This instruction extracts a 32-bit word from a 64-bit value of an even/odd pair of registers specified
 * by Rs1(4,1) starting from a specified LSB bit position, specified in Rs2[4:0]. The extracted word is
 * written to Rd.
 * Rs1(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register
 * pair includes register 2d and 2d+1.
 * The odd `2d+1` register of the pair contains the high 32-bit of the 64-bit value and the even `2d`
 * register of the pair contains the low 32-bit of the 64-bit value.
 *
 * **Operations**:\n
 * ~~~
 * * RV32:
 * Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1);
 * src[63:0] = Concat(R[Idx1], R[Idx0]);
 * LSBloc = Rs2[4:0];
 * Rd = src[31+LSBloc:LSBloc];
 * * RV64:
 * LSBloc = Rs2[4:0];
 * ExtractW = Rs1[31+LSBloc:LSBloc];
 * Rd = SE(ExtractW)
 * ~~~
 *
 * \param [in]  a    long long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_WEXT(long long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("wext %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 3.187. WEXT ===== */

/* ===== Inline Function Start for 3.188.1. ZUNPKD810 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief ZUNPKD810 (Unsigned Unpacking Bytes 1 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * ZUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
 * halfwords of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
 * // ZUNPKD810, x=1,y=0
 * // ZUNPKD820, x=2,y=0
 * // ZUNPKD830, x=3,y=0
 * // ZUNPKD831, x=3,y=1
 * // ZUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD810(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("zunpkd810 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.188.1. ZUNPKD810 ===== */

/* ===== Inline Function Start for 3.188.2. ZUNPKD820 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief ZUNPKD820 (Unsigned Unpacking Bytes 2 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * ZUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
 * halfwords of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
 * // ZUNPKD810, x=1,y=0
 * // ZUNPKD820, x=2,y=0
 * // ZUNPKD830, x=3,y=0
 * // ZUNPKD831, x=3,y=1
 * // ZUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD820(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("zunpkd820 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.188.2. ZUNPKD820 ===== */

/* ===== Inline Function Start for 3.188.3. ZUNPKD830 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief ZUNPKD830 (Unsigned Unpacking Bytes 3 & 0)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * ZUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
 * halfwords of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
 * // ZUNPKD810, x=1,y=0
 * // ZUNPKD820, x=2,y=0
 * // ZUNPKD830, x=3,y=0
 * // ZUNPKD831, x=3,y=1
 * // ZUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD830(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("zunpkd830 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.188.3. ZUNPKD830 ===== */

/* ===== Inline Function Start for 3.188.4. ZUNPKD831 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief ZUNPKD831 (Unsigned Unpacking Bytes 3 & 1)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * ZUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
 * halfwords of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
 * // ZUNPKD810, x=1,y=0
 * // ZUNPKD820, x=2,y=0
 * // ZUNPKD830, x=3,y=0
 * // ZUNPKD831, x=3,y=1
 * // ZUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD831(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("zunpkd831 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.188.4. ZUNPKD831 ===== */

/* ===== Inline Function Start for 3.188.5. ZUNPKD832 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_SIMD_8B_UNPACK
 * \brief ZUNPKD832 (Unsigned Unpacking Bytes 3 & 2)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * ZUNPKD8xy Rd, Rs1
 * xy = {10, 20, 30, 31, 32}
 * ~~~
 *
 * **Purpose**:\n
 * Unpack byte x and byte y of 32-bit chunks in a register into two 16-bit unsigned
 * halfwords of 32-bit chunks in a register.
 *
 * **Description**:\n
 * For the `ZUNPKD8(x)(*y*)` instruction, it unpacks byte *x and byte y* of 32-bit chunks in Rs1 into
 * two 16-bit unsigned halfwords and writes the results to the top part and the bottom part of 32-bit
 * chunks in Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[m].H[1] = ZE16(Rs1.W[m].B[x])
 * Rd.W[m].H[0] = ZE16(Rs1.W[m].B[y])
 * // ZUNPKD810, x=1,y=0
 * // ZUNPKD820, x=2,y=0
 * // ZUNPKD830, x=3,y=0
 * // ZUNPKD831, x=3,y=1
 * // ZUNPKD832, x=3,y=2
 * for RV32: m=0,
 * for RV64: m=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ZUNPKD832(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("zunpkd832 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 3.188.5. ZUNPKD832 ===== */

#if (__RISCV_XLEN == 64) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)

/* ===== Inline Function Start for 4.1. ADD32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief ADD32 (SIMD 32-bit Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * ADD32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 32-bit integer elements in Rs1 with the 32-bit integer
 * elements in Rs2, and then writes the 32-bit element results to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned addition.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = Rs1.W[x] + Rs2.W[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_ADD32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("add32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.1. ADD32 ===== */

/* ===== Inline Function Start for 4.2. CRAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief CRAS32 (SIMD 32-bit Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * CRAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit
 * chunk simultaneously. Operands are from crossed 32-bit elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
 * integer element in [31:0] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts
 * the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and
 * writes the result to [31:0] of Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = Rs1.W[1] + Rs2.W[0];
 * Rd.W[0] = Rs1.W[0] - Rs2.W[1];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CRAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("cras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.2. CRAS32 ===== */

/* ===== Inline Function Start for 4.3. CRSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief CRSA32 (SIMD 32-bit Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * CRSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit
 * chunk simultaneously. Operands are from crossed 32-bit elements.
 * *Description: *
 * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element
 * in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit integer
 * element in [31:0] of Rs1 with the 32-bit integer element in [63:32] of Rs2, and writes the result to
 * [31:0] of Rd
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = Rs1.W[1] - Rs2.W[0];
 * Rd.W[0] = Rs1.W[0] + Rs2.W[1];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_CRSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("crsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.3. CRSA32 ===== */

/* ===== Inline Function Start for 4.4. KABS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
 * \brief KABS32 (Scalar 32-bit Absolute Value with Saturation)
 * \details
 * **Type**: DSP (RV64 Only)
24    20
19    15
14    12
11    7
KABS32
10010
Rs1
000
Rd
6    0
GE80B
1111111
 *
 * **Syntax**:\n
 * ~~~
 * KABS32 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of signed 32-bit integer elements in a general register.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of signed 32-bit integer elements stored
 * in Rs1. The results are written to Rd. This instruction with the minimum negative integer input of
 * 0x80000000 will produce a saturated output of maximum positive integer of 0x7fffffff and the OV
 * flag will be set to 1.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs1.W[x] >= 0) {
 *   res[x] = Rs1.W[x];
 * } else {
 *   If (Rs1.W[x] == 0x80000000) {
 *     res[x] = 0x7fffffff;
 *     OV = 1;
 *   } else {
 *     res[x] = -Rs1.W[x];
 *   }
 * }
 * Rd.W[x] = res[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KABS32(unsigned long a)
{
    register unsigned long result;
    __ASM volatile("kabs32 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for 4.4. KABS32 ===== */

/* ===== Inline Function Start for 4.5. KADD32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KADD32 (SIMD 32-bit Signed Saturating Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KADD32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed
 * integer elements in Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1),
 * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.W[x] + Rs2.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KADD32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.5. KADD32 ===== */

/* ===== Inline Function Start for 4.6. KCRAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KCRAS32 (SIMD 32-bit Signed Saturating Cross Addition & Subtraction)
 * \details
 * **Type**: SIM (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KCRAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element saturating addition and 32-bit signed integer element
 * saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
 * integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit integer element in [63:32] of
 * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number
 * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res[1] = Rs1.W[1] + Rs2.W[0];
 * res[0] = Rs1.W[0] - Rs2.W[1];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[1] = res[1];
 * Rd.W[0] = res[0];
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KCRAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.6. KCRAS32 ===== */

/* ===== Inline Function Start for 4.7. KCRSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KCRSA32 (SIMD 32-bit Signed Saturating Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KCRSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element
 * saturating addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements.
 * *Description: *
 * This instruction subtracts the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element
 * in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with the 32-bit
 * integer element in [63:32] of Rs2. If any of the results are beyond the Q31 number range (-2^31 <= Q31
 * <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
 * [63:32] of Rd for subtraction and [31:0] of Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res[1] = Rs1.W[1] - Rs2.W[0];
 * res[0] = Rs1.W[0] + Rs2.W[1];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[1] = res[1];
 * Rd.W[0] = res[0];
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KCRSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.7. KCRSA32 ===== */

/* ===== Inline Function Start for 4.8.1. KDMBB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMBB16 (SIMD Signed Saturating Double Multiply B16 x B16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
 * in the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
 * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
 * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
 * and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * Rd.W[z] = resQ31[z];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMBB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kdmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.8.1. KDMBB16 ===== */

/* ===== Inline Function Start for 4.8.2. KDMBT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMBT16 (SIMD Signed Saturating Double Multiply B16 x T16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
 * in the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
 * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
 * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
 * and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * Rd.W[z] = resQ31[z];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMBT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kdmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.8.2. KDMBT16 ===== */

/* ===== Inline Function Start for 4.8.3. KDMTT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMTT16 (SIMD Signed Saturating Double Multiply T16 x T16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results into the 32-bit chunks
 * in the destination register. If saturation happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portions in Rs2. The Q30 results are then doubled and
 * saturated into Q31 values. The Q31 values are then written into the 32-bit chunks in Rd. When both
 * the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated to 0x7FFFFFFF
 * and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * Rd.W[z] = resQ31[z];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMTT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kdmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.8.3. KDMTT16 ===== */

/* ===== Inline Function Start for 4.9.1. KDMABB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMABB16 (SIMD Signed Saturating Double Multiply Addition B16 x B16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
 * the values of the corresponding 32-bit chunks from the destination register and write the saturated
 * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
 * happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
 * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
 * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
 * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
 * are written back to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd[z] = Rd.W[z] + resQ31[z];
 * if (resadd[z] > (2^31)-1) {
 *   resadd[z] = (2^31)-1;
 *   OV = 1;
 * } else if (resadd[z] < -2^31) {
 *   resadd[z] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[z] = resadd[z];
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMABB16(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kdmabb16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.9.1. KDMABB16 ===== */

/* ===== Inline Function Start for 4.9.2. KDMABT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMABT16 (SIMD Signed Saturating Double Multiply Addition B16 x T16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
 * the values of the corresponding 32-bit chunks from the destination register and write the saturated
 * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
 * happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
 * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
 * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
 * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
 * are written back to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd[z] = Rd.W[z] + resQ31[z];
 * if (resadd[z] > (2^31)-1) {
 *   resadd[z] = (2^31)-1;
 *   OV = 1;
 * } else if (resadd[z] < -2^31) {
 *   resadd[z] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[z] = resadd[z];
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMABT16(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kdmabt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.9.2. KDMABT16 ===== */

/* ===== Inline Function Start for 4.9.3. KDMATT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KDMATT16 (SIMD Signed Saturating Double Multiply Addition T16 x T16)
 * \details
 * **Type**: SIMD (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * KDMAxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then double and saturate the Q31 results, add the results with
 * the values of the corresponding 32-bit chunks from the destination register and write the saturated
 * addition results back into the corresponding 32-bit chunks of the destination register. If saturation
 * happens, an overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the corresponding 32-bit portions in Rs2. The Q30 results are then
 * doubled and saturated into Q31 values. The Q31 values are then added with the content of the
 * corresponding 32-bit portions of Rd. If the addition results are beyond the Q31 number range (-2^31 <=
 * Q31 <= 2^31-1), they are saturated to the range and the OV flag is set to 1. The results after saturation
 * are written back to Rd.
 * When both the two Q15 inputs are 0x8000, saturation will happen and the overflow flag OV will be
 * set.
 *
 * **Operations**:\n
 * ~~~
 * // KDMABB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KDMABT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KDMATT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop[z] = Rs1.H[x]; bop[z] = Rs2.H[y];
 * If (0x8000 != aop[z] | 0x8000 != bop[z]) {
 *   Mresult[z] = aop[z] * bop[z];
 *   resQ31[z] = Mresult[z] << 1;
 * } else {
 *   resQ31[z] = 0x7FFFFFFF;
 *   OV = 1;
 * }
 * resadd[z] = Rd.W[z] + resQ31[z];
 * if (resadd[z] > (2^31)-1) {
 *   resadd[z] = (2^31)-1;
 *   OV = 1;
 * } else if (resadd[z] < -2^31) {
 *   resadd[z] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[z] = resadd[z];
 * ~~~
 *
 * \param [in]  t    unsigned long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KDMATT16(unsigned long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kdmatt16 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.9.3. KDMATT16 ===== */

/* ===== Inline Function Start for 4.10.1. KHMBB16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KHMBB16 (SIMD Signed Saturating Half Multiply B16 x B16)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
 * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop = Rs1.H[x]; bop = Rs2.H[y];
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd.W[z] = SE32(res[15:0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHMBB16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khmbb16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.10.1. KHMBB16 ===== */

/* ===== Inline Function Start for 4.10.2. KHMBT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KHMBT16 (SIMD Signed Saturating Half Multiply B16 x T16)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
 * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop = Rs1.H[x]; bop = Rs2.H[y];
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd.W[z] = SE32(res[15:0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHMBT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khmbt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.10.2. KHMBT16 ===== */

/* ===== Inline Function Start for 4.10.3. KHMTT16 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_Q15_SAT_MULT
 * \brief KHMTT16 (SIMD Signed Saturating Half Multiply T16 x T16)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KHMxy16 Rd, Rs1, Rs2 (xy = BB, BT, TT)
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed Q15 integer contents of two 16-bit data in the corresponding portion
 * of the 32-bit chunks in registers and then right-shift 15 bits to turn the Q30 results into Q15
 * numbers again and saturate the Q15 results into the destination register. If saturation happens, an
 * overflow flag OV will be set.
 *
 * **Description**:\n
 * Multiply the top or bottom 16-bit Q15 content of the 32-bit portions in Rs1 with the top
 * or bottom 16-bit Q15 content of the 32-bit portion in Rs2. The Q30 results are then right-shifted 15-
 * bits and saturated into Q15 values. The 32-bit Q15 values are then written into the 32-bit chunks in
 * Rd. When both the two Q15 inputs are 0x8000, saturation will happen. The result will be saturated
 * to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * // KHMBB16: (x,y,z)=(0,0,0),(2,2,1)
 * // KHMBT16: (x,y,z)=(0,1,0),(2,3,1)
 * // KHMTT16: (x,y,z)=(1,1,0),(3,3,1)
 * aop = Rs1.H[x]; bop = Rs2.H[y];
 * If (0x8000 != aop | 0x8000 != bop) {
 *   Mresult[31:0] = aop * bop;
 *   res[15:0] = Mresult[30:15];
 * } else {
 *   res[15:0] = 0x7FFF;
 *   OV = 1;
 * }
 * Rd.W[z] = SE32(res[15:0]);
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KHMTT16(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("khmtt16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.10.3. KHMTT16 ===== */

/* ===== Inline Function Start for 4.11.1. KMABB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
 * \brief KMABB32 (Saturating Signed Multiply Bottom Words & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMABB32 Rd, Rs1, Rs2
 * KMABT32 Rd, Rs1, Rs2
 * KMATT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element in a register with the 32-bit element in another register
 * and add the result to the content of 64-bit data in the third register. The addition result may be
 * saturated and is written to the third register.
 * * KMABB32: rd + bottom*bottom
 * * KMABT32: rd + bottom*top
 * * KMATT32: rd + top*top
 *
 * **Description**:\n
 * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2.
 * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
 * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
 * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
 *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
 *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
 *  if (res > (2^63)-1) {
 *    res = (2^63)-1;
 *    OV = 1;
 *  } else if (res < -2^63) {
 *    res = -2^63;
 *    OV = 1;
 *  }
 *  Rd = res;
 * *Exceptions:* None
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMABB32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmabb32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.11.1. KMABB32 ===== */

/* ===== Inline Function Start for 4.11.2. KMABT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
 * \brief KMABT32 (Saturating Signed Multiply Bottom & Top Words & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMABB32 Rd, Rs1, Rs2
 * KMABT32 Rd, Rs1, Rs2
 * KMATT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element in a register with the 32-bit element in another register
 * and add the result to the content of 64-bit data in the third register. The addition result may be
 * saturated and is written to the third register.
 * * KMABB32: rd + bottom*bottom
 * * KMABT32: rd + bottom*top
 * * KMATT32: rd + top*top
 *
 * **Description**:\n
 * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2.
 * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
 * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
 * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
 *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
 *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
 *  if (res > (2^63)-1) {
 *    res = (2^63)-1;
 *    OV = 1;
 *  } else if (res < -2^63) {
 *    res = -2^63;
 *    OV = 1;
 *  }
 *  Rd = res;
 * *Exceptions:* None
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMABT32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmabt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.11.2. KMABT32 ===== */

/* ===== Inline Function Start for 4.11.3. KMATT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT_ADD
 * \brief KMATT32 (Saturating Signed Multiply Top Words & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMABB32 Rd, Rs1, Rs2
 * KMABT32 Rd, Rs1, Rs2
 * KMATT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element in a register with the 32-bit element in another register
 * and add the result to the content of 64-bit data in the third register. The addition result may be
 * saturated and is written to the third register.
 * * KMABB32: rd + bottom*bottom
 * * KMABT32: rd + bottom*top
 * * KMATT32: rd + top*top
 *
 * **Description**:\n
 * For the `KMABB32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2.
 * For the `KMABT32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * For the `KMATT32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2.
 * The multiplication result is added to the content of 64-bit data in Rd. If the addition result is beyond
 * the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The
 * result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[0] * Rs2.W[0]); // KMABB32
 *  res = Rd + (Rs1.W[0] * Rs2.W[1]); // KMABT32
 *  res = Rd + (Rs1.W[1] * Rs2.W[1]); // KMATT32
 *  if (res > (2^63)-1) {
 *    res = (2^63)-1;
 *    OV = 1;
 *  } else if (res < -2^63) {
 *    res = -2^63;
 *    OV = 1;
 *  }
 *  Rd = res;
 * *Exceptions:* None
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMATT32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmatt32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.11.3. KMATT32 ===== */

/* ===== Inline Function Start for 4.12.1. KMADA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMADA32 (Saturating Signed Multiply Two Words and Two Adds)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMADA32 Rd, Rs1, Rs2
 * KMAXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the
 * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated.
 * * KMADA32: rd + top*top + bottom*bottom
 * * KMAXDA32: rd + top*bottom + bottom*top
 *
 * **Description**:\n
 * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-
 * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1
 * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction.
 * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1
 * with the top 32-bit element in Rs2.
 * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63
 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit
 * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32
 * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADA32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmada32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.12.1. KMADA32 ===== */

/* ===== Inline Function Start for 4.12.2. KMAXDA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMAXDA32 (Saturating Signed Crossed Multiply Two Words and Two Adds)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMADA32 Rd, Rs1, Rs2
 * KMAXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from 32-bit data in two registers; and then adds the
 * two 64-bit results and 64-bit data in a third register together. The addition result may be saturated.
 * * KMADA32: rd + top*top + bottom*bottom
 * * KMAXDA32: rd + top*bottom + bottom*top
 *
 * **Description**:\n
 * For the `KMADA32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-
 * bit element in Rs2 and then adds the result to the result of multiplying the top 32-bit element in Rs1
 * with the top 32-bit element in Rs2. It is actually an alias of the `KMAR64` instruction.
 * For the `KMAXDA32` instruction, it multiplies the top 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2 and then adds the result to the result of multiplying the bottom 32-bit element in Rs1
 * with the top 32-bit element in Rs2.
 * The result is added to the content of 64-bit data in Rd. If the addition result is beyond the Q63
 * number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The 64-bit
 * result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[1] * Rs2.w[1]) + (Rs1.W[0] * Rs2.W[0]); // KMADA32
 * res = Rd + (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMAXDA32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMAXDA32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmaxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.12.2. KMAXDA32 ===== */

/* ===== Inline Function Start for 4.13.1. KMDA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMDA32 (Signed Multiply Two Words and Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMDA32 Rd, Rs1, Rs2
 * KMXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
 * adds the two 64-bit results together. The addition result may be saturated.
 * * KMDA32: top*top + bottom*bottom
 * * KMXDA32: top*bottom + bottom*top
 *
 * **Description**:\n
 * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
 * with the top 32-bit element of Rs2.
 * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
 * with the bottom 32-bit element of Rs2.
 * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1.
 * The final result is written to Rd. The 32-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) {
 *   Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32
 *   Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32
 * } else {
 *   Rd = 0x7fffffffffffffff;
 *   OV = 1;
 * }
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMDA32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.13.1. KMDA32 ===== */

/* ===== Inline Function Start for 4.13.2. KMXDA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMXDA32 (Signed Crossed Multiply Two Words and Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMDA32 Rd, Rs1, Rs2
 * KMXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
 * adds the two 64-bit results together. The addition result may be saturated.
 * * KMDA32: top*top + bottom*bottom
 * * KMXDA32: top*bottom + bottom*top
 *
 * **Description**:\n
 * For the `KMDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
 * with the top 32-bit element of Rs2.
 * For the `KMXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then adds the result to the result of multiplying the top 32-bit element of Rs1
 * with the bottom 32-bit element of Rs2.
 * The addition result is checked for saturation. If saturation happens, the result is saturated to 2^63-1.
 * The final result is written to Rd. The 32-bit contents are treated as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * if ((Rs1 != 0x8000000080000000) or (Rs2 != 0x8000000080000000)) {
 *   Rd = (Rs1.W[1] * Rs2.W[1]) + (Rs1.W[0] * Rs2.W[0]); // KMDA32
 *   Rd = (Rs1.W[1] * Rs2.W[0]) + (Rs1.W[0] * Rs2.W[1]); // KMXDA32
 * } else {
 *   Rd = 0x7fffffffffffffff;
 *   OV = 1;
 * }
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMXDA32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("kmxda32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.13.2. KMXDA32 ===== */

/* ===== Inline Function Start for 4.14.1. KMADS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMADS32 (Saturating Signed Multiply Two Words & Subtract & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMADS32 Rd, Rs1, Rs2
 * KMADRS32 Rd, Rs1, Rs2
 * KMAXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
 * 64-bit data in a third register. The addition result may be saturated.
 * * KMADS32: rd + (top*top - bottom*bottom)
 * * KMADRS32: rd + (bottom*bottom - top*top)
 * * KMAXDS32: rd + (top*bottom - bottom*top)
 *
 * **Description**:\n
 * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the top 32-bit element in Rs2.
 * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element in Rs1 with the bottom 32-bit element in Rs2.
 * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the bottom 32-bit element in Rs2.
 * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
 * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
 * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
 * as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADS32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmads32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.14.1. KMADS32 ===== */

/* ===== Inline Function Start for 4.14.2. KMADRS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMADRS32 (Saturating Signed Multiply Two Words & Reverse Subtract & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMADS32 Rd, Rs1, Rs2
 * KMADRS32 Rd, Rs1, Rs2
 * KMAXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
 * 64-bit data in a third register. The addition result may be saturated.
 * * KMADS32: rd + (top*top - bottom*bottom)
 * * KMADRS32: rd + (bottom*bottom - top*top)
 * * KMAXDS32: rd + (top*bottom - bottom*top)
 *
 * **Description**:\n
 * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the top 32-bit element in Rs2.
 * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element in Rs1 with the bottom 32-bit element in Rs2.
 * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the bottom 32-bit element in Rs2.
 * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
 * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
 * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
 * as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMADRS32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmadrs32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.14.2. KMADRS32 ===== */

/* ===== Inline Function Start for 4.14.3. KMAXDS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMAXDS32 (Saturating Signed Crossed Multiply Two Words & Subtract & Add)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMADS32 Rd, Rs1, Rs2
 * KMADRS32 Rd, Rs1, Rs2
 * KMAXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from 32-bit elements in two registers; and then
 * perform a subtraction operation between the two 64-bit results. Then add the subtraction result to
 * 64-bit data in a third register. The addition result may be saturated.
 * * KMADS32: rd + (top*top - bottom*bottom)
 * * KMADRS32: rd + (bottom*bottom - top*top)
 * * KMAXDS32: rd + (top*bottom - bottom*top)
 *
 * **Description**:\n
 * For the `KMADS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the bottom 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the top 32-bit element in Rs2.
 * For the `KMADRS32` instruction, it multiplies the top 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element in Rs1 with the bottom 32-bit element in Rs2.
 * For the `KMAXDS32` instruction, it multiplies the bottom 32-bit element in Rs1 with the top 32-bit
 * element in Rs2 and then subtracts the result from the result of multiplying the top 32-bit element in
 * Rs1 with the bottom 32-bit element in Rs2.
 * The subtraction result is then added to the content of 64-bit data in Rd. If the addition result is
 * beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to
 * 1. The 64-bit result after saturation is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated
 * as signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd + (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMADS32
 * res = Rd + (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // KMADRS32
 * res = Rd + (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMAXDS32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMAXDS32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmaxds32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.14.3. KMAXDS32 ===== */

/* ===== Inline Function Start for 4.15.1. KMSDA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMSDA32 (Saturating Signed Multiply Two Words & Add & Subtract)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMSDA32 Rd, Rs1, Rs2
 * KMSXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
 * subtracts the two 64-bit results from a third register. The subtraction result may be saturated.
 * * KMSDA: rd - top*top - bottom*bottom
 * * KMSXDA: rd - top*bottom - bottom*top
 *
 * **Description**:\n
 * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2.
 * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2.
 * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction
 * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit
 * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32
 * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMSDA32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmsda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.15.1. KMSDA32 ===== */

/* ===== Inline Function Start for 4.15.2. KMSXDA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief KMSXDA32 (Saturating Signed Crossed Multiply Two Words & Add & Subtract)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KMSDA32 Rd, Rs1, Rs2
 * KMSXDA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the 32-bit element of two registers; and then
 * subtracts the two 64-bit results from a third register. The subtraction result may be saturated.
 * * KMSDA: rd - top*top - bottom*bottom
 * * KMSXDA: rd - top*bottom - bottom*top
 *
 * **Description**:\n
 * For the `KMSDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and multiplies the top 32-bit element of Rs1 with the top 32-bit element of Rs2.
 * For the `KMSXDA32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and multiplies the top 32-bit element of Rs1 with the bottom 32-bit element of Rs2.
 * The two 64-bit multiplication results are then subtracted from the content of Rd. If the subtraction
 * result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit
 * is set to 1. The result after saturation is written to Rd. The 32-bit contents are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rd - (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // KMSDA32
 * res = Rd - (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // KMSXDA32
 * if (res > (2^63)-1) {
 *   res = (2^63)-1;
 *   OV = 1;
 * } else if (res < -2^63) {
 *   res = -2^63;
 *   OV = 1;
 * }
 * Rd = res;
 * ~~~
 *
 * \param [in]  t    long type of value stored in t
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_KMSXDA32(long t, unsigned long a, unsigned long b)
{
    __ASM volatile("kmsxda32 %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
    return t;
}
/* ===== Inline Function End for 4.15.2. KMSXDA32 ===== */

/* ===== Inline Function Start for 4.16. KSLL32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief KSLL32 (SIMD 32-bit Saturating Shift Left Logical)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSLL32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is a variable from a GPR.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the low-order 5-bits of the value in the Rs2 register.
 * Any shifted value greater than 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is
 * saturated to -2^31. And the saturated results are written to Rd. If any saturation is performed, set OV
 * bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * if (sa != 0) {
 *   res[(31+sa):0] = Rs1.W[x] << sa;
 *   if (res > (2^31)-1) {
 *     res = 0x7fffffff; OV = 1;
 *   } else if (res < -2^31) {
 *     res = 0x80000000; OV = 1;
 *   }
 *   Rd.W[x] = res[31:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLL32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("ksll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.16. KSLL32 ===== */

/* ===== Inline Function Start for 4.17. KSLLI32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief KSLLI32 (SIMD 32-bit Saturating Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSLLI32 Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical left shift operations with saturation simultaneously. The shift
 * amount is an immediate value.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are left-shifted logically. The shifted out bits are filled
 * with zero and the shift amount is specified by the imm5u constant. Any shifted value greater than
 * 2^31-1 is saturated to 2^31-1. Any shifted value smaller than -2^31 is saturated to -2^31. And the saturated
 * results are written to Rd. If any saturation is performed, set OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 * if (sa != 0) {
 *   res[(31+sa):0] = Rs1.W[x] << sa;
 *   if (res > (2^31)-1) {
 *     res = 0x7fffffff; OV = 1;
 *   } else if (res < -2^31) {
 *     res = 0x80000000; OV = 1;
 *   }
 *   Rd.W[x] = res[31:0];
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLLI32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("kslli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.17. KSLLI32 ===== */

/* ===== Inline Function Start for 4.18.1. KSLRA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief KSLRA32 (SIMD 32-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA32 Rd, Rs1, Rs2
 * KSLRA32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
 * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be
 * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`.
 * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u`
 * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[5:0] < 0) {
 *   sa = -Rs2[5:0];
 *   sa = (sa == 32)? 31 : sa;
 *   if (`.u` form) {
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   } else {
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   sa = Rs2[4:0];
 *   res[(31+sa):0] = Rs1.W[x] <<(logic) sa;
 *   if (res > (2^31)-1) {
 *     res[31:0] = 0x7fffffff; OV = 1;
 *   } else if (res < -2^31) {
 *     res[31:0] = 0x80000000; OV = 1;
 *   }
 *   Rd.W[x] = res[31:0];
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA32(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.18.1. KSLRA32 ===== */

/* ===== Inline Function Start for 4.18.2. KSLRA32.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief KSLRA32.u (SIMD 32-bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSLRA32 Rd, Rs1, Rs2
 * KSLRA32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q31 saturation for the left shift. The `.u` form performs additional rounding up operations for the
 * right shift.
 *
 * **Description**:\n
 * The 32-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [-25, 25-1]. A positive Rs2[5:0] means
 * logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[5:0]. However, the behavior of `Rs2[5:0]==-25 (0x20)` is defined to be
 * equivalent to the behavior of `Rs2[5:0]==-(25-1) (0x21)`.
 * The left-shifted results are saturated to the 32-bit signed integer range of [-2^31, 2^31-1]. For the `.u`
 * form of the instruction, the right-shifted results are added a 1 to the most significant discarded bit
 * position for rounding effect. After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[5:0] < 0) {
 *   sa = -Rs2[5:0];
 *   sa = (sa == 32)? 31 : sa;
 *   if (`.u` form) {
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   } else {
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   sa = Rs2[4:0];
 *   res[(31+sa):0] = Rs1.W[x] <<(logic) sa;
 *   if (res > (2^31)-1) {
 *     res[31:0] = 0x7fffffff; OV = 1;
 *   } else if (res < -2^31) {
 *     res[31:0] = 0x80000000; OV = 1;
 *   }
 *   Rd.W[x] = res[31:0];
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U(unsigned long a, int b)
{
    register unsigned long result;
    __ASM volatile("kslra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.18.2. KSLRA32.u ===== */

/* ===== Inline Function Start for 4.19. KSTAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KSTAS32 (SIMD 32-bit Signed Saturating Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSTAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element saturating addition and 32-bit signed integer element
 * saturating subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit
 * elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
 * integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit integer element in [31:0] of
 * Rs2 from the 32-bit integer element in [31:0] of Rs1. If any of the results are beyond the Q31 number
 * range (-2^31 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to [63:32] of Rd for addition and [31:0] of Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res[1] = Rs1.W[1] + Rs2.W[1];
 * res[0] = Rs1.W[0] - Rs2.W[0];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[1] = res[1];
 * Rd.W[0] = res[0];
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSTAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.19. KSTAS32 ===== */

/* ===== Inline Function Start for 4.20. KSTSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KSTSA32 (SIMD 32-bit Signed Saturating Straight Subtraction & Addition)
 * \details
 * **Type**: SIM (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSTSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element saturating subtraction and 32-bit signed integer element
 * saturating addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit
 * elements.
 * *Description: *
 * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer
 * element in [63:32] of Rs1; at the same time, it adds the 32-bit integer element in [31:0] of Rs1 with
 * the 32-bit integer element in [31:0] of Rs2. If any of the results are beyond the Q31 number range (-
 * 231 <= Q31 <= 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are
 * written to [63:32] of Rd for subtraction and [31:0] of Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res[1] = Rs1.W[1] - Rs2.W[1];
 * res[0] = Rs1.W[0] + Rs2.W[0];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[1] = res[1];
 * Rd.W[0] = res[0];
 * for RV64, x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSTSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("kstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.20. KSTSA32 ===== */

/* ===== Inline Function Start for 4.21. KSUB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief KSUB32 (SIMD 32-bit Signed Saturating Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * KSUB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit
 * signed integer elements in Rs1. If any of the results are beyond the Q31 number range (-2^31 <= Q31 <=
 * 2^31-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.W[x] - Rs2.W[x];
 * if (res[x] > (2^31)-1) {
 *   res[x] = (2^31)-1;
 *   OV = 1;
 * } else if (res[x] < -2^31) {
 *   res[x] = -2^31;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_KSUB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.21. KSUB32 ===== */

/* ===== Inline Function Start for 4.22.1. PKBB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
 * \brief PKBB32 (Pack Two 32-bit Data from Both Bottom Half)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * PKBB32 Rd, Rs1, Rs2
 * PKBT32 Rd, Rs1, Rs2
 * PKTT32 Rd, Rs1, Rs2
 * PKTB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 32-bit data from 64-bit chunks in two registers.
 * * PKBB32: bottom.bottom
 * * PKBT32: bottom.top
 * * PKTT32: top.top
 * * PKTB32: top.bottom
 *
 * **Description**:\n
 * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 *
 * **Operations**:\n
 * ~~~
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKBB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pkbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.22.1. PKBB32 ===== */

/* ===== Inline Function Start for 4.22.2. PKBT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
 * \brief PKBT32 (Pack Two 32-bit Data from Bottom and Top Half)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * PKBB32 Rd, Rs1, Rs2
 * PKBT32 Rd, Rs1, Rs2
 * PKTT32 Rd, Rs1, Rs2
 * PKTB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 32-bit data from 64-bit chunks in two registers.
 * * PKBB32: bottom.bottom
 * * PKBT32: bottom.top
 * * PKTT32: top.top
 * * PKTB32: top.bottom
 *
 * **Description**:\n
 * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 *
 * **Operations**:\n
 * ~~~
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKBT32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pkbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.22.2. PKBT32 ===== */

/* ===== Inline Function Start for 4.22.3. PKTT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
 * \brief PKTT32 (Pack Two 32-bit Data from Both Top Half)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * PKBB32 Rd, Rs1, Rs2
 * PKBT32 Rd, Rs1, Rs2
 * PKTT32 Rd, Rs1, Rs2
 * PKTB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 32-bit data from 64-bit chunks in two registers.
 * * PKBB32: bottom.bottom
 * * PKBT32: bottom.top
 * * PKTT32: top.top
 * * PKTB32: top.bottom
 *
 * **Description**:\n
 * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 *
 * **Operations**:\n
 * ~~~
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKTT32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pktt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.22.3. PKTT32 ===== */

/* ===== Inline Function Start for 4.22.4. PKTB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PACK
 * \brief PKTB32 (Pack Two 32-bit Data from Top and Bottom Half)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * PKBB32 Rd, Rs1, Rs2
 * PKBT32 Rd, Rs1, Rs2
 * PKTT32 Rd, Rs1, Rs2
 * PKTB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Pack 32-bit data from 64-bit chunks in two registers.
 * * PKBB32: bottom.bottom
 * * PKBT32: bottom.top
 * * PKTT32: top.top
 * * PKTB32: top.bottom
 *
 * **Description**:\n
 * (PKBB32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 * (PKBT32) moves Rs1.W[0] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTT32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[1] to Rd.W[0].
 * (PKTB32) moves Rs1.W[1] to Rd.W[1] and moves Rs2.W[0] to Rd.W[0].
 *
 * **Operations**:\n
 * ~~~
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*0*_]); // PKBB32
 * Rd = CONCAT(Rs1.W[_*0*_], Rs2.W[_*1*_]); // PKBT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*1*_]); // PKTT32
 * Rd = CONCAT(Rs1.W[_*1*_], Rs2.W[_*0*_]); // PKTB32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_PKTB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("pktb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.22.4. PKTB32 ===== */

/* ===== Inline Function Start for 4.23. RADD32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RADD32 (SIMD 32-bit Signed Halving Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RADD32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element additions simultaneously. The results are halved to avoid
 * overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 32-bit signed integer elements in Rs1 with the 32-bit signed
 * integer elements in Rs2. The results are first arithmetically right-shifted by 1 bit and then written to
 * Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Rs1 = 0x7FFFFFFF, Rs2 = 0x7FFFFFFF Rd = 0x7FFFFFFF
 * * Rs1 = 0x80000000, Rs2 = 0x80000000 Rd = 0x80000000
 * * Rs1 = 0x40000000, Rs2 = 0x80000000 Rd = 0xE0000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] + Rs2.W[x]) s>> 1;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RADD32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("radd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.23. RADD32 ===== */

/* ===== Inline Function Start for 4.24. RCRAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RCRAS32 (SIMD 32-bit Signed Halving Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RCRAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in
 * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit
 * signed integer element in [31:0] of Rs2, and subtracts the 32-bit signed integer element in [63:32] of
 * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first
 * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd
 * for subtraction.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD32` and `RSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) s>> 1;
 * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) s>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RCRAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.24. RCRAS32 ===== */

/* ===== Inline Function Start for 4.25. RCRSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RCRSA32 (SIMD 32-bit Signed Halving Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RCRSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in
 * a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit signed integer element in [31:0] of Rs2 from the
 * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0]
 * of Rs1 with the 32-bit signed integer element in [63:32] of Rs2. The two results are first
 * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of
 * Rd for addition.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD32` and `RSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) s>> 1;
 * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) s>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RCRSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.25. RCRSA32 ===== */

/* ===== Inline Function Start for 4.26. RSTAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RSTAS32 (SIMD 32-bit Signed Halving Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RSTAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element addition and 32-bit signed integer element subtraction in
 * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are
 * halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 32-bit signed integer element in [63:32] of Rs1 with the 32-bit
 * signed integer element in [63:32] of Rs2, and subtracts the 32-bit signed integer element in [31:0] of
 * Rs2 from the 32-bit signed integer element in [31:0] of Rs1. The element results are first
 * arithmetically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd
 * for subtraction.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD32` and `RSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) s>> 1;
 * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) s>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSTAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.26. RSTAS32 ===== */

/* ===== Inline Function Start for 4.27. RSTSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RSTSA32 (SIMD 32-bit Signed Halving Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RSTSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element subtraction and 32-bit signed integer element addition in
 * a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The results are
 * halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit signed integer element in [63:32] of Rs2 from the
 * 32-bit signed integer element in [63:32] of Rs1, and adds the 32-bit signed element integer in [31:0]
 * of Rs1 with the 32-bit signed integer element in [31:0] of Rs2. The two results are first arithmetically
 * right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for addition.
 *
 * **Examples**:\n
 * ~~~
 * Please see `RADD32` and `RSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) s>> 1;
 * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) s>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSTSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.27. RSTSA32 ===== */

/* ===== Inline Function Start for 4.28. RSUB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief RSUB32 (SIMD 32-bit Signed Halving Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * RSUB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit signed integer elements in Rs2 from the 32-bit
 * signed integer elements in Rs1. The results are first arithmetically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFFFFFF, Rb = 0x80000000 Rt = 0x7FFFFFFF
 * * Ra = 0x80000000, Rb = 0x7FFFFFFF Rt = 0x80000000
 * * Ra = 0x80000000, Rb = 0x40000000 Rt = 0xA0000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) s>> 1;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_RSUB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("rsub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.28. RSUB32 ===== */

/* ===== Inline Function Start for 4.29. SLL32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SLL32 (SIMD 32-bit Shift Left Logical)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SLL32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical left shift operations simultaneously. The shift amount is a
 * variable from a GPR.
 *
 * **Description**:\n
 * The 32-bit elements in Rs1 are left-shifted logically. And the results are written to Rd.
 * The shifted out bits are filled with zero and the shift amount is specified by the low-order 5-bits of
 * the value in the Rs2 register.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * Rd.W[x] = Rs1.W[x] << sa;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SLL32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sll32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.29. SLL32 ===== */

/* ===== Inline Function Start for 4.30. SLLI32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SLLI32 (SIMD 32-bit Shift Left Logical Immediate)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SLLI32 Rd, Rs1, imm5u[4:0]
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit element logical left shift operations simultaneously. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * The 32-bit elements in Rs1 are left-shifted logically. The shifted out bits are filled with
 * zero and the shift amount is specified by the imm5u[4:0] constant. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 * Rd.W[x] = Rs1.W[x] << sa;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SLLI32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("slli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.30. SLLI32 ===== */

/* ===== Inline Function Start for 4.31. SMAX32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
 * \brief SMAX32 (SIMD 32-bit Signed Maximum)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMAX32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit
 * signed integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] > Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMAX32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.31. SMAX32 ===== */

/* ===== Inline Function Start for 4.32.1. SMBB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
 * \brief SMBB32 (Signed Multiply Bottom Word & Bottom Word)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMBB32 Rd, Rs1, Rs2
 * SMBT32 Rd, Rs1, Rs2
 * SMTT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
 * register and write the 64-bit result to a third register.
 * * SMBB32: bottom*bottom
 * * SMBT32: bottom*top
 * * SMTT32: top*top
 *
 * **Description**:\n
 * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2. It is actually an alias of `MULSR64` instruction.
 * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2.
 * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
 * of Rs2.
 * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
 * // SMTT32 Rd = res;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMBB32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smbb32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.32.1. SMBB32 ===== */

/* ===== Inline Function Start for 4.32.2. SMBT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
 * \brief SMBT32 (Signed Multiply Bottom Word & Top Word)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMBB32 Rd, Rs1, Rs2
 * SMBT32 Rd, Rs1, Rs2
 * SMTT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
 * register and write the 64-bit result to a third register.
 * * SMBB32: bottom*bottom
 * * SMBT32: bottom*top
 * * SMTT32: top*top
 *
 * **Description**:\n
 * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2. It is actually an alias of `MULSR64` instruction.
 * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2.
 * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
 * of Rs2.
 * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
 * // SMTT32 Rd = res;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMBT32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smbt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.32.2. SMBT32 ===== */

/* ===== Inline Function Start for 4.32.3. SMTT32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_MULT
 * \brief SMTT32 (Signed Multiply Top Word & Top Word)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMBB32 Rd, Rs1, Rs2
 * SMBT32 Rd, Rs1, Rs2
 * SMTT32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Multiply the signed 32-bit element of a register with the signed 32-bit element of another
 * register and write the 64-bit result to a third register.
 * * SMBB32: bottom*bottom
 * * SMBT32: bottom*top
 * * SMTT32: top*top
 *
 * **Description**:\n
 * For the `SMBB32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2. It is actually an alias of `MULSR64` instruction.
 * For the `SMBT32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2.
 * For the `SMTT32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit element
 * of Rs2.
 * The 64-bit multiplication result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as
 * signed integers.
 *
 * **Operations**:\n
 * ~~~
 * res = Rs1.W[0] * Rs2.W[0]; // SMBB32 res = Rs1.W[0] * Rs2.w[1]; // SMBT32 res = Rs1.W[1] * Rs2.W[1];
 * // SMTT32 Rd = res;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMTT32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smtt32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.32.3. SMTT32 ===== */

/* ===== Inline Function Start for 4.33.1. SMDS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief SMDS32 (Signed Multiply Two Words and Subtract)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMDS32 Rd, Rs1, Rs2
 * SMDRS32 Rd, Rs1, Rs2
 * SMXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
 * perform a subtraction operation between the two 64-bit results.
 * * SMDS32: top*top - bottom*bottom
 * * SMDRS32: bottom*bottom - top*top
 * * SMXDS32: top*bottom - bottom*top
 *
 * **Description**:\n
 * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the top 32-bit element of Rs2.
 * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element of Rs1 with the bottom 32-bit element of Rs2.
 * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the bottom 32-bit element of Rs2.
 * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMDS32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.33.1. SMDS32 ===== */

/* ===== Inline Function Start for 4.33.2. SMDRS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief SMDRS32 (Signed Multiply Two Words and Reverse Subtract)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMDS32 Rd, Rs1, Rs2
 * SMDRS32 Rd, Rs1, Rs2
 * SMXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
 * perform a subtraction operation between the two 64-bit results.
 * * SMDS32: top*top - bottom*bottom
 * * SMDRS32: bottom*bottom - top*top
 * * SMXDS32: top*bottom - bottom*top
 *
 * **Description**:\n
 * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the top 32-bit element of Rs2.
 * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element of Rs1 with the bottom 32-bit element of Rs2.
 * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the bottom 32-bit element of Rs2.
 * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMDRS32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smdrs32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.33.2. SMDRS32 ===== */

/* ===== Inline Function Start for 4.33.3. SMXDS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_32B_PARALLEL_MAC
 * \brief SMXDS32 (Signed Crossed Multiply Two Words and Subtract)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMDS32 Rd, Rs1, Rs2
 * SMDRS32 Rd, Rs1, Rs2
 * SMXDS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do two signed 32-bit multiplications from the l 32-bit element of two registers; and then
 * perform a subtraction operation between the two 64-bit results.
 * * SMDS32: top*top - bottom*bottom
 * * SMDRS32: bottom*bottom - top*top
 * * SMXDS32: top*bottom - bottom*top
 *
 * **Description**:\n
 * For the `SMDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the bottom 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the top 32-bit element of Rs2.
 * For the `SMDRS32` instruction, it multiplies the top 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the bottom 32-bit
 * element of Rs1 with the bottom 32-bit element of Rs2.
 * For the `SMXDS32` instruction, it multiplies the bottom 32-bit element of Rs1 with the top 32-bit
 * element of Rs2 and then subtracts the result from the result of multiplying the top 32-bit element of
 * Rs1 with the bottom 32-bit element of Rs2.
 * The subtraction result is written to Rd. The 32-bit contents of Rs1 and Rs2 are treated as signed
 * integers.
 *
 * **Operations**:\n
 * ~~~
 * Rt = (Rs1.W[1] * Rs2.W[1]) - (Rs1.W[0] * Rs2.W[0]); // SMDS32
 * Rt = (Rs1.W[0] * Rs2.W[0]) - (Rs1.W[1] * Rs2.W[1]); // SMDRS32
 * Rt = (Rs1.W[1] * Rs2.W[0]) - (Rs1.W[0] * Rs2.W[1]); // SMXDS32
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SMXDS32(unsigned long a, unsigned long b)
{
    register long result;
    __ASM volatile("smxds32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.33.3. SMXDS32 ===== */

/* ===== Inline Function Start for 4.34. SMIN32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
 * \brief SMIN32 (SIMD 32-bit Signed Minimum)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SMIN32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit signed integer elements finding minimum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 32-bit signed integer elements in Rs1 with the 32-bit
 * signed integer elements in Rs2 and selects the numbers that is less than the other one. The selected
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] < Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SMIN32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("smin32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.34. SMIN32 ===== */

/* ===== Inline Function Start for 4.35.1. SRA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRA32 (SIMD 32-bit Shift Right Arithmetic)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRA32 Rd, Rs1, Rs2
 * SRA32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 32-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA32.u
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRA32
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sra32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.35.1. SRA32 ===== */

/* ===== Inline Function Start for 4.35.2. SRA32.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRA32.u (SIMD 32-bit Rounding Shift Right Arithmetic)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRA32 Rd, Rs1, Rs2
 * SRA32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit element arithmetic right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the data elements. The shift amount is specified by the low-order
 * 5-bits of the value in the Rs2 register. For the rounding operation of the `.u` form, a value of 1 is
 * added to the most significant discarded bit of each 32-bit data element to calculate the final results.
 * And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA32.u
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRA32
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRA32_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("sra32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.35.2. SRA32.u ===== */

/* ===== Inline Function Start for 4.36.1. SRAI32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRAI32 (SIMD 32-bit Shift Right Arithmetic Immediate)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRAI32 Rd, Rs1, imm5u
 * SRAI32.u Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is
 * an immediate value. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the
 * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
 * significant discarded bit of each 32-bit data to calculate the final results. And the results are written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 *   if (sa > 0) {
 *   if (`.u` form) { // SRAI32.u
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRAI32
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRAI32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srai32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.36.1. SRAI32 ===== */

/* ===== Inline Function Start for 4.36.2. SRAI32.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRAI32.u (SIMD 32-bit Rounding Shift Right Arithmetic Immediate)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRAI32 Rd, Rs1, imm5u
 * SRAI32.u Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements arithmetic right shift operations simultaneously. The shift amount is
 * an immediate value. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted arithmetically, that is, the shifted out
 * bits are filled with the sign-bit of the 32-bit data elements. The shift amount is specified by the
 * imm5u constant. For the rounding operation of the `.u` form, a value of 1 is added to the most
 * significant discarded bit of each 32-bit data to calculate the final results. And the results are written
 * to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 *   if (sa > 0) {
 *   if (`.u` form) { // SRAI32.u
 *     res[31:-1] = SE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRAI32
 *     Rd.W[x] = SE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRAI32_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srai32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.36.2. SRAI32.u ===== */

/* ===== Inline Function Start for 4.37. SRAIW.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_NON_SIMD_32B_SHIFT
 * \brief SRAIW.u (Rounding Shift Right Arithmetic Immediate Word)
 * \details
 * **Type**: DSP (RV64 only)
 *
 * **Syntax**:\n
 * ~~~
 * SRAIW.u Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Perform a 32-bit arithmetic right shift operation with rounding. The shift amount is an
 * immediate value.
 *
 * **Description**:\n
 * This instruction right-shifts the lower 32-bit content of Rs1 arithmetically. The shifted
 * out bits are filled with the sign-bit Rs1(31) and the shift amount is specified by the imm5u constant.
 * For the rounding operation, a value of 1 is added to the most significant discarded bit of the data to
 * calculate the final result. And the result is sign-extended and written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u;
 * if (sa != 0) {
 *   res[31:-1] = SE33(Rs1[31:(sa-1)]) + 1;
 *   Rd = SE32(res[31:0]);
 * } else {
 *   Rd = SE32(Rs1.W[0]);
 * }
 * ~~~
 *
 * \param [in]  a    int type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in long type
 */
__STATIC_FORCEINLINE long __RV_SRAIW_U(int a, unsigned int b)
{
    register long result;
    __ASM volatile("sraiw.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.37. SRAIW.u ===== */

/* ===== Inline Function Start for 4.38.1. SRL32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRL32 (SIMD 32-bit Shift Right Logical)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRL32 Rd, Rs1, Rs2
 * SRL32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit element logical right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2
 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 32-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA32.u
 *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRA32
 *     Rd.W[x] = ZE32(Rs1.W[x][31:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.38.1. SRL32 ===== */

/* ===== Inline Function Start for 4.38.2. SRL32.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRL32.u (SIMD 32-bit Rounding Shift Right Logical)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRL32 Rd, Rs1, Rs2
 * SRL32.u Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit element logical right shift operations simultaneously. The shift amount is a
 * variable from a GPR. The `.u` form performs additional rounding up operations on the shifted
 * results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the low-order 5-bits of the value in the Rs2
 * register. For the rounding operation of the `.u` form, a value of 1 is added to the most significant
 * discarded bit of each 32-bit data element to calculate the final results. And the results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = Rs2[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRA32.u
 *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRA32
 *     Rd.W[x] = ZE32(Rs1.W[x][31:sa])
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRL32_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srl32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.38.2. SRL32.u ===== */

/* ===== Inline Function Start for 4.39.1. SRLI32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRLI32 (SIMD 32-bit Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRLI32 Rd, Rs1, imm5u
 * SRLI32.u Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding
 * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit
 * data to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI32.u
 *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRLI32
 *     Rd.W[x] = ZE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRLI32(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srli32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.39.1. SRLI32 ===== */

/* ===== Inline Function Start for 4.39.2. SRLI32.u ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
 * \brief SRLI32.u (SIMD 32-bit Rounding Shift Right Logical Immediate)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SRLI32 Rd, Rs1, imm5u
 * SRLI32.u Rd, Rs1, imm5u
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit elements logical right shift operations simultaneously. The shift amount is an
 * immediate value. The `.u` form performs additional rounding up operations on the shifted results.
 *
 * **Description**:\n
 * The 32-bit data elements in Rs1 are right-shifted logically, that is, the shifted out bits
 * are filled with zero. The shift amount is specified by the imm5u constant. For the rounding
 * operation of the `.u` form, a value of 1 is added to the most significant discarded bit of each 32-bit
 * data to calculate the final results. And the results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * sa = imm5u[4:0];
 * if (sa > 0) {
 *   if (`.u` form) { // SRLI32.u
 *     res[31:-1] = ZE33(Rs1.W[x][31:sa-1]) + 1;
 *     Rd.W[x] = res[31:0];
 *   else { // SRLI32
 *     Rd.W[x] = ZE32(Rs1.W[x][31:sa]);
 *   }
 * } else {
 *   Rd = Rs1;
 * }
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned int type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SRLI32_U(unsigned long a, unsigned int b)
{
    register unsigned long result;
    __ASM volatile("srli32.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.39.2. SRLI32.u ===== */

/* ===== Inline Function Start for 4.40. STAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief STAS32 (SIMD 32-bit Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * STAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element addition and 32-bit integer element subtraction in a 64-bit
 * chunk simultaneously. Operands are from corresponding 32-bit elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit integer element in [63:32] of Rs1 with the 32-bit
 * integer element in [63:32] of Rs2, and writes the result to [63:32] of Rd; at the same time, it subtracts
 * the 32-bit integer element in [31:0] of Rs2 from the 32-bit integer element in [31:0] of Rs1, and
 * writes the result to [31:0] of Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = Rs1.W[1] + Rs2.W[1];
 * Rd.W[0] = Rs1.W[0] - Rs2.W[0];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_STAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("stas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.40. STAS32 ===== */

/* ===== Inline Function Start for 4.41. STSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief STSA32 (SIMD 32-bit Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * STSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element subtraction and 32-bit integer element addition in a 64-bit
 * chunk simultaneously. Operands are from corresponding 32-bit elements.
 * *Description: *
 * This instruction subtracts the 32-bit integer element in [63:32] of Rs2 from the 32-bit integer
 * element in [63:32] of Rs1, and writes the result to [63:32] of Rd; at the same time, it adds the 32-bit
 * integer element in [31:0] of Rs1 with the 32-bit integer element in [31:0] of Rs2, and writes the result
 * to [31:0] of Rd
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned operations.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = Rs1.W[1] - Rs2.W[1];
 * Rd.W[0] = Rs1.W[0] + Rs2.W[0];
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_STSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("stsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.41. STSA32 ===== */

/* ===== Inline Function Start for 4.42. SUB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief SUB32 (SIMD 32-bit Subtraction)
 * \details
 * **Type**: DSP (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * SUB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit integer element subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit integer elements in Rs2 from the 32-bit integer
 * elements in Rs1, and then writes the results to Rd.
 *
 * **Note**:\n
 * This instruction can be used for either signed or unsigned subtraction.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = Rs1.W[x] - Rs2.W[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_SUB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("sub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.42. SUB32 ===== */

/* ===== Inline Function Start for 4.43. UKADD32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKADD32 (SIMD 32-bit Unsigned Saturating Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKADD32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 32-bit unsigned integer elements in Rs1 with the 32-bit
 * unsigned integer elements in Rs2. If any of the results are beyond the 32-bit unsigned number
 * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.W[x] + Rs2.W[x];
 * if (res[x] > (2^32)-1) {
 *   res[x] = (2^32)-1;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKADD32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukadd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.43. UKADD32 ===== */

/* ===== Inline Function Start for 4.44. UKCRAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKCRAS32 (SIMD 32-bit Unsigned Saturating Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKCRAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned
 * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from crossed
 * 32-bit elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
 * bit unsigned integer element in [31:0] of Rs2; at the same time, it subtracts the 32-bit unsigned
 * integer element in [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the
 * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
 * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and
 * [31:0] of Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[1] + Rs2.W[0];
 * res2 = Rs1.W[0] - Rs2.W[1];
 * if (res1 > (2^32)-1) {
 *   res1 = (2^32)-1;
 *   OV = 1;
 * }
 * if (res2 < 0) {
 *   res2 = 0;
 *   OV = 1;
 * }
 * Rd.W[1] = res1;
 * Rd.W[0] = res2;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKCRAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.44. UKCRAS32 ===== */

/* ===== Inline Function Start for 4.45. UKCRSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKCRSA32 (SIMD 32-bit Unsigned Saturating Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKCRSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned
 * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from crossed
 * 32-bit elements.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the
 * 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned
 * integer element in [63:32] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the
 * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
 * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and
 * [31:0] of Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[1] - Rs2.W[0];
 * res2 = Rs1.W[0] + Rs2.W[1];
 * if (res1 < 0) {
 *   res1 = 0;
 *   OV = 1;
 * } else if (res2 > (2^32)-1) {
 *   res2 = (2^32)-1;
 *   OV = 1;
 * }
 * Rd.W[1] = res1;
 * Rd.W[0] = res2;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKCRSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.45. UKCRSA32 ===== */

/* ===== Inline Function Start for 4.46. UKSTAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKSTAS32 (SIMD 32-bit Unsigned Saturating Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKSTAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 32-bit unsigned integer element saturating addition and one 32-bit unsigned
 * integer element saturating subtraction in a 64-bit chunk simultaneously. Operands are from
 * corresponding 32-bit elements.
 *
 * **Description**:\n
 * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
 * bit unsigned integer element in [63:32] of Rs2; at the same time, it subtracts the 32-bit unsigned
 * integer element in [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] Rs1. If any of the
 * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
 * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for addition and
 * [31:0] of Rd for subtraction.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[1] + Rs2.W[1];
 * res2 = Rs1.W[0] - Rs2.W[0];
 * if (res1 > (2^32)-1) {
 *   res1 = (2^32)-1;
 *   OV = 1;
 * }
 * if (res2 < 0) {
 *   res2 = 0;
 *   OV = 1;
 * }
 * Rd.W[1] = res1;
 * Rd.W[0] = res2;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSTAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.46. UKSTAS32 ===== */

/* ===== Inline Function Start for 4.47. UKSTSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKSTSA32 (SIMD 32-bit Unsigned Saturating Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKSTSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do one 32-bit unsigned integer element saturating subtraction and one 32-bit unsigned
 * integer element saturating addition in a 64-bit chunk simultaneously. Operands are from
 * corresponding 32-bit elements.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from
 * the 32-bit unsigned integer element in [63:32] of Rs1; at the same time, it adds the 32-bit unsigned
 * integer element in [31:0] of Rs2 with the 32-bit unsigned integer element in [31:0] Rs1. If any of the
 * results are beyond the 32-bit unsigned number range (0 <= RES <= 2^32-1), they are saturated to the
 * range and the OV bit is set to 1. The saturated results are written to [63:32] of Rd for subtraction and
 * [31:0] of Rd for addition.
 *
 * **Operations**:\n
 * ~~~
 * res1 = Rs1.W[1] - Rs2.W[1];
 * res2 = Rs1.W[0] + Rs2.W[0];
 * if (res1 < 0) {
 *   res1 = 0;
 *   OV = 1;
 * } else if (res2 > (2^32)-1) {
 *   res2 = (2^32)-1;
 *   OV = 1;
 * }
 * Rd.W[1] = res1;
 * Rd.W[0] = res2;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSTSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ukstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.47. UKSTSA32 ===== */

/* ===== Inline Function Start for 4.48. UKSUB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief UKSUB32 (SIMD 32-bit Unsigned Saturating Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UKSUB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit
 * unsigned integer elements in Rs1. If any of the results are beyond the 32-bit unsigned number
 * range (0 <= RES <= 2^32-1), they are saturated to the range and the OV bit is set to 1. The saturated
 * results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.W[x] - Rs2.W[x];
 * if (res[x] < 0) {
 *   res[x] = 0;
 *   OV = 1;
 * }
 * Rd.W[x] = res[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UKSUB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uksub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.48. UKSUB32 ===== */

/* ===== Inline Function Start for 4.49. UMAX32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
 * \brief UMAX32 (SIMD 32-bit Unsigned Maximum)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UMAX32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer elements finding maximum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit
 * unsigned integer elements in Rs2 and selects the numbers that is greater than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] u> Rs2.W[x])? Rs1.W[x] : Rs2.W[x];
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_UMAX32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("umax32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.49. UMAX32 ===== */

/* ===== Inline Function Start for 4.50. UMIN32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_MISC
 * \brief UMIN32 (SIMD 32-bit Unsigned Minimum)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * UMIN32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer elements finding minimum operations simultaneously.
 *
 * **Description**:\n
 * This instruction compares the 32-bit unsigned integer elements in Rs1 with the 32-bit
 * unsigned integer elements in Rs2 and selects the numbers that is less than the other one. The
 * selected results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] > 1;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URADD32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("uradd32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.51. URADD32 ===== */

/* ===== Inline Function Start for 4.52. URCRAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief URCRAS32 (SIMD 32-bit Unsigned Halving Cross Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * URCRAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element
 * subtraction in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The
 * results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
 * bit unsigned integer element in [31:0] of Rs2, and subtracts the 32-bit unsigned integer element in
 * [63:32] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first
 * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for
 * subtraction.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD32` and `URSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] + Rs2.W[0]) u>> 1;
 * Rd.W[0] = (Rs1.W[0] - Rs2.W[1]) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URCRAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urcras32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.52. URCRAS32 ===== */

/* ===== Inline Function Start for 4.53. URCRSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief URCRSA32 (SIMD 32-bit Unsigned Halving Cross Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * URCRSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element
 * addition in a 64-bit chunk simultaneously. Operands are from crossed 32-bit elements. The results
 * are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer element in [31:0] of Rs2 from the
 * 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer in
 * [31:0] of Rs1 with the 32-bit unsigned integer element in [63:32] of Rs2. The two results are first
 * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for
 * addition.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD32` and `URSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] - Rs2.W[0]) u>> 1;
 * Rd.W[0] = (Rs1.W[0] + Rs2.W[1]) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URCRSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urcrsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.53. URCRSA32 ===== */

/* ===== Inline Function Start for 4.54. URSTAS32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief URSTAS32 (SIMD 32-bit Unsigned Halving Straight Addition & Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * URSTAS32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element addition and 32-bit unsigned integer element
 * subtraction in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements.
 * The results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction adds the 32-bit unsigned integer element in [63:32] of Rs1 with the 32-
 * bit unsigned integer element in [63:32] of Rs2, and subtracts the 32-bit unsigned integer element in
 * [31:0] of Rs2 from the 32-bit unsigned integer element in [31:0] of Rs1. The element results are first
 * logically right-shifted by 1 bit and then written to [63:32] of Rd for addition and [31:0] of Rd for
 * subtraction.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD32` and `URSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] + Rs2.W[1]) u>> 1;
 * Rd.W[0] = (Rs1.W[0] - Rs2.W[0]) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSTAS32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urstas32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.54. URSTAS32 ===== */

/* ===== Inline Function Start for 4.55. URSTSA32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief URSTSA32 (SIMD 32-bit Unsigned Halving Straight Subtraction & Addition)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * URSTSA32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element subtraction and 32-bit unsigned integer element
 * addition in a 64-bit chunk simultaneously. Operands are from corresponding 32-bit elements. The
 * results are halved to avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer element in [63:32] of Rs2 from
 * the 32-bit unsigned integer element in [63:32] of Rs1, and adds the 32-bit unsigned element integer
 * in [31:0] of Rs1 with the 32-bit unsigned integer element in [31:0] of Rs2. The two results are first
 * logically right-shifted by 1 bit and then written to [63:32] of Rd for subtraction and [31:0] of Rd for
 * addition.
 *
 * **Examples**:\n
 * ~~~
 * Please see `URADD32` and `URSUB32` instructions.
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[1] = (Rs1.W[1] - Rs2.W[1]) u>> 1;
 * Rd.W[0] = (Rs1.W[0] + Rs2.W[0]) u>> 1;
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSTSA32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("urstsa32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.55. URSTSA32 ===== */

/* ===== Inline Function Start for 4.56. URSUB32 ===== */
/**
 * \ingroup NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_ADDSUB
 * \brief URSUB32 (SIMD 32-bit Unsigned Halving Subtraction)
 * \details
 * **Type**: SIMD (RV64 Only)
 *
 * **Syntax**:\n
 * ~~~
 * URSUB32 Rd, Rs1, Rs2
 * ~~~
 *
 * **Purpose**:\n
 * Do 32-bit unsigned integer element subtractions simultaneously. The results are halved to
 * avoid overflow or saturation.
 *
 * **Description**:\n
 * This instruction subtracts the 32-bit unsigned integer elements in Rs2 from the 32-bit
 * unsigned integer elements in Rs1. The results are first logically right-shifted by 1 bit and then
 * written to Rd.
 *
 * **Examples**:\n
 * ~~~
 * * Ra = 0x7FFFFFFF, Rb = 0x80000000, Rt = 0xFFFFFFFF
 * * Ra = 0x80000000, Rb = 0x7FFFFFFF, Rt = 0x00000000
 * * Ra = 0x80000000, Rb = 0x40000000, Rt = 0x20000000
 * ~~~
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x] = (Rs1.W[x] - Rs2.W[x]) u>> 1;
 * for RV64: x=1...0
 * ~~~
 *
 * \param [in]  a    unsigned long type of value stored in a
 * \param [in]  b    unsigned long type of value stored in b
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_URSUB32(unsigned long a, unsigned long b)
{
    register unsigned long result;
    __ASM volatile("ursub32 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for 4.56. URSUB32 ===== */

#endif /* __RISCV_XLEN == 64 */


#if (__RISCV_XLEN == 32) || defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
/* XXXXX Nuclei Extended DSP Instructions for RV32 XXXXX */
/**
 * \defgroup NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM      Nuclei Customized DSP Instructions
 * \ingroup  NMSIS_Core_DSP_Intrinsic
 * \brief    (RV32 only)Nuclei Customized DSP Instructions
 * \details  This is Nuclei customized DSP instructions only for RV32
 */
/* ===== Inline Function Start for A.1. DKHM8 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKHM8 (64-bit SIMD Signed Saturating Q7 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKHM8 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do Q7xQ7 element multiplications simultaneously. The Q14 results are then reduced to Q7
 * numbers again.
 *
 * **Description**:\n
 * For the `DKHM8` instruction, multiply the top 8-bit Q7 content of 16-bit chunks in Rs1
 * with the top 8-bit Q7 content of 16-bit chunks in Rs2. At the same time, multiply the bottom 8-bit Q7
 * content of 16-bit chunks in Rs1 with the bottom 8-bit Q7 content of 16-bit chunks in Rs2.
 *
 * The Q14 results are then right-shifted 7-bits and saturated into Q7 values. The Q7 results are then
 * written into Rd. When both the two Q7 inputs of a multiplication are 0x80, saturation will happen.
 * The result will be saturated to 0x7F and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * op1t = Rs1.B[x+1]; op2t = Rs2.B[x+1]; // top
 * op1b = Rs1.B[x]; op2b = Rs2.B[x]; // bottom
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x80 != aop | 0x80 != bop) {
 *     res = (aop s* bop) >> 7;
 *   } else {
 *     res= 0x7F;
 *     OV = 1;
 *   }
 * }
 * Rd.H[x/2] = concat(rest, resb);
 * for RV32, x=0,2,4,6
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKHM8(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dkhm8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.1. DKHM8 ===== */

/* ===== Inline Function Start for A.2. DKHM16 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKHM16 (64-bit SIMD Signed Saturating Q15 Multiply)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKHM16 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do Q15xQ15 element multiplications simultaneously. The Q30 results are then reduced to
 * Q15 numbers again.
 *
 * **Description**:\n
 * For the `DKHM16` instruction, multiply the top 16-bit Q15 content of 32-bit chunks in
 * Rs1 with the top 16-bit Q15 content of 32-bit chunks in Rs2. At the same time, multiply the bottom
 * 16-bit Q15 content of 32-bit chunks in Rs1 with the bottom 16-bit Q15 content of 32-bit chunks in
 * Rs2.
 *
 * The Q30 results are then right-shifted 15-bits and saturated into Q15 values. The Q15 results are
 * then written into Rd. When both the two Q15 inputs of a multiplication are 0x8000, saturation will
 * happen. The result will be saturated to 0x7FFF and the overflow flag OV will be set.
 *
 * **Operations**:\n
 * ~~~
 * op1t = Rs1.H[x+1]; op2t = Rs2.H[x+1]; // top
 * op1b = Rs1.H[x]; op2b = Rs2.H[x]; // bottom
 * for ((aop,bop,res) in [(op1t,op2t,rest), (op1b,op2b,resb)]) {
 *   if (0x8000 != aop | 0x8000 != bop) {
 *     res = (aop s* bop) >> 15;
 *   } else {
 *     res= 0x7FFF;
 *     OV = 1;
 *   }
 * }
 * Rd.W[x/2] = concat(rest, resb);
 * for RV32: x=0, 2
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKHM16(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dkhm16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.2. DKHM16 ===== */

/* ===== Inline Function Start for A.3. DKABS8 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKABS8 (64-bit SIMD 8-bit Saturating Absolute)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKABS8 Rd, Rs1
 * # Rd, Rs1 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of 8-bit signed integer elements simultaneously.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of 8-bit signed integer elements stored
 * in Rs1 and writes the element results to Rd. If the input number is 0x80, this instruction generates
 * 0x7f as the output and sets the OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.B[x];
 * if (src == 0x80) {
 *   src = 0x7f;
 *   OV = 1;
 * } else if (src[7] == 1)
 *   src = -src;
 * }
 * Rd.B[x] = src;
 * for RV32: x=7...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKABS8(unsigned long long a)
{
    unsigned long long result;
    __ASM volatile("dkabs8 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A.3. DKABS8 ===== */

/* ===== Inline Function Start for A.4. DKABS16 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKABS16 (64-bit SIMD 16-bit Saturating Absolute)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKABS16 Rd, Rs1
 * # Rd, Rs1 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Get the absolute value of 16-bit signed integer elements simultaneously.
 *
 * **Description**:\n
 * This instruction calculates the absolute value of 16-bit signed integer elements stored
 * in Rs1 and writes the element results to Rd. If the input number is 0x8000, this instruction
 * generates 0x7fff as the output and sets the OV bit to 1.
 *
 * **Operations**:\n
 * ~~~
 * src = Rs1.H[x];
 * if (src == 0x8000) {
 *   src = 0x7fff;
 *   OV = 1;
 * } else if (src[15] == 1)
 *   src = -src;
 * }
 * Rd.H[x] = src;
 * for RV32: x=3...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKABS16(unsigned long long a)
{
    unsigned long long result;
    __ASM volatile("dkabs16 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A.4. DKABS16 ===== */

/* ===== Inline Function Start for A.5. DKSLRA8 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKSLRA8 (64-bit SIMD 8-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKSLRA8 Rd, Rs1, Rs2
 * # Rd, Rs1 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q7 saturation for the left shift.
 *
 * **Description**:\n
 * The 8-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [-2^3, 2^3-1]. A positive Rs2[3:0] means
 * logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[3:0]. However, the behavior of `Rs2[3:0]==-2^3 (0x8)` is defined to be
 * equivalent to the behavior of `Rs2[3:0]==-(2^3-1) (0x9)`.
 * The left-shifted results are saturated to the 8-bit signed integer range of [-2^7, 2^7-1].
 * If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[3:0] < 0) {
 *   sa = -Rs2[3:0];
 *   sa = (sa == 8)? 7 : sa;
 *   Rd.B[x] = SE8(Rs1.B[x][7:sa]);
 * } else {
 *   sa = Rs2[2:0];
 *   res[(7+sa):0] = Rs1.B[x] <<(logic) sa;
 *   if (res > (2^7)-1) {
 *     res[7:0] = 0x7f; OV = 1;
 *   } else if (res < -2^7) {
 *     res[7:0] = 0x80; OV = 1;
 *   }
 *   Rd.B[x] = res[7:0];
 * }
 * for RV32: x=7...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA8(unsigned long long a, int b)
{
    unsigned long long result;
    __ASM volatile("dkslra8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.5. DKSLRA8 ===== */

/* ===== Inline Function Start for A.6. DKSLRA16 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKSLRA16 (64-bit SIMD 16-bit Shift Left Logical with Saturation or Shift Right Arithmetic)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKSLRA16 Rd, Rs1, Rs2
 * # Rd, Rs1 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit elements logical left (positive) or arithmetic right (negative) shift operation with
 * Q15 saturation for the left shift.
 *
 * **Description**:\n
 * The 16-bit data elements of Rs1 are left-shifted logically or right-shifted arithmetically
 * based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [-2^4, 2^4-1]. A positive Rs2[4:0] means
 * logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the
 * absolute value of Rs2[4:0]. However, the behavior of `Rs2[4:0]==-2^4 (0x10)` is defined to be
 * equivalent to the behavior of `Rs2[4:0]==-(2^4-1) (0x11)`.
 * The left-shifted results are saturated to the 16-bit signed integer range of [-2^15, 2^15-1].
 * After the shift, saturation, or rounding, the final results are written to
 * Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect
 * this instruction.
 *
 * **Operations**:\n
 * ~~~
 * if (Rs2[4:0] < 0) {
 *   sa = -Rs2[4:0];
 *   sa = (sa == 16)? 15 : sa;
 *   Rd.H[x] = SE16(Rs1.H[x][15:sa]);
 * } else {
 *   sa = Rs2[3:0];
 *   res[(15+sa):0] = Rs1.H[x] <<(logic) sa;
 *   if (res > (2^15)-1) {
 *     res[15:0] = 0x7fff; OV = 1;
 *   } else if (res < -2^15) {
 *     res[15:0] = 0x8000; OV = 1;
 *   }
 *   d.H[x] = res[15:0];
 * }
 * for RV32: x=3...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b int type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKSLRA16(unsigned long long a, int b)
{
    unsigned long long result;
    __ASM volatile("dkslra16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.6. DKSLRA16 ===== */

/* ===== Inline Function Start for A.7. DKADD8 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKADD8 (64-bit SIMD 8-bit Signed Saturating Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKADD8 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 8-bit signed integer elements in Rs1 with the 8-bit signed
 * integer elements in Rs2. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1), they
 * are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.B[x] + Rs2.B[x];
 * if (res[x] > 127) {
 *   res[x] = 127;
 *   OV = 1;
 * } else if (res[x] < -128) {
 *   res[x] = -128;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=7...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKADD8(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dkadd8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.7. DKADD8 ===== */

/* ===== Inline Function Start for A.8. DKADD16 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKADD16 (64-bit SIMD 16-bit Signed Saturating Addition)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKADD16 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer element saturating additions simultaneously.
 *
 * **Description**:\n
 * This instruction adds the 16-bit signed integer elements in Rs1 with the 16-bit signed
 * integer elements in Rs2. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <= 2^15-1),
 * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] + Rs2.H[x];
 * if (res[x] > 32767) {
 *   res[x] = 32767;
 *   OV = 1;
 * } else if (res[x] < -32768) {
 *   res[x] = -32768;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=3...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKADD16(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dkadd16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.8. DKADD16 ===== */

/* ===== Inline Function Start for A.10. DKSUB8 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKSUB8 (64-bit SIMD 8-bit Signed Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKSUB8 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 8-bit signed elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 8-bit signed integer elements in Rs2 from the 8-bit
 * signed integer elements in Rs1. If any of the results are beyond the Q7 number range (-2^7 <= Q7 <= 2^7-1),
 * they are saturated to the range and the OV bit is set to 1. The saturated results are written to Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.B[x] - Rs2.B[x];
 * if (res[x] > (2^7)-1) {
 *   res[x] = (2^7)-1;
 *   OV = 1;
 * } else if (res[x] < -2^7) {
 *   res[x] = -2^7;
 *   OV = 1;
 * }
 * Rd.B[x] = res[x];
 * for RV32: x=7...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKSUB8(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dksub8 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.9. DKSUB8 ===== */

/* ===== Inline Function Start for A.10. DKSUB16 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief DKSUB16 (64-bit SIMD 16-bit Signed Saturating Subtraction)
 * \details
 * **Type**: SIMD
 *
 * **Syntax**:\n
 * ~~~
 * DKSUB16 Rd, Rs1, Rs2
 * # Rd, Rs1, Rs2 are all even/odd pair of registers
 * ~~~
 *
 * **Purpose**:\n
 * Do 16-bit signed integer elements saturating subtractions simultaneously.
 *
 * **Description**:\n
 * This instruction subtracts the 16-bit signed integer elements in Rs2 from the 16-bit
 * signed integer elements in Rs1. If any of the results are beyond the Q15 number range (-2^15 <= Q15 <=
 * 2^15-1), they are saturated to the range and the OV bit is set to 1. The saturated results are written to
 * Rd.
 *
 * **Operations**:\n
 * ~~~
 * res[x] = Rs1.H[x] - Rs2.H[x];
 * if (res[x] > (2^15)-1) {
 *   res[x] = (2^15)-1;
 *   OV = 1;
 * } else if (res[x] < -2^15) {
 *   res[x] = -2^15;
 *   OV = 1;
 * }
 * Rd.H[x] = res[x];
 * for RV32: x=3...0,
 * ~~~
 *
 * \param [in]  a unsigned long long type of value stored in a
 * \param [in]  b unsigned long long type of value stored in b
 * \return value stored in unsigned long long type
 */
__STATIC_FORCEINLINE unsigned long long __RV_DKSUB16(unsigned long long a, unsigned long long b)
{
    unsigned long long result;
    __ASM volatile("dksub16 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
    return result;
}
/* ===== Inline Function End for A.10. DKSUB16 ===== */

/* ===== Inline Function Start for A.11.1. EXPD80 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief EXPD80 (Expand and Copy Byte 0 to 32bit)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * EXPD80 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
 *
 * **Description**:\n
 * Moves Rs1.B[0][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0], Rs1.B[0][7:0]);
 * for RV32: x=0
 * ~~~
 *
 * \param [in]  a unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_EXPD80(unsigned long a)
{
    unsigned long result;
    __ASM volatile("expd80 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A11.1. EXPD80 ===== */

/* ===== Inline Function Start for A.11.2. EXPD81 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief EXPD81 (Expand and Copy Byte 1 to 32bit)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * EXPD81 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
 *
 * **Description**:\n
 * Moves Rs1.B[1][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0], Rs1.B[1][7:0]);
 * for RV32: x=0
 * ~~~
 *
 * \param [in]  a unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_EXPD81(unsigned long a)
{
    unsigned long result;
    __ASM volatile("expd81 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A11.2. EXPD81 ===== */

/* ===== Inline Function Start for A.11.3. EXPD82 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief EXPD82 (Expand and Copy Byte 2 to 32bit)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * EXPD82 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
 *
 * **Description**:\n
 * Moves Rs1.B[2][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0], Rs1.B[2][7:0]);
 * for RV32: x=0
 * ~~~
 *
 * \param [in]  a unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_EXPD82(unsigned long a)
{
    unsigned long result;
    __ASM volatile("expd82 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A11.3. EXPD82 ===== */

/* ===== Inline Function Start for A.11.4. EXPD83 ===== */
/**
 * \ingroup  NMSIS_Core_DSP_Intrinsic_NUCLEI_CUSTOM
 * \brief EXPD83 (Expand and Copy Byte 3 to 32bit)
 * \details
 * **Type**: DSP
 *
 * **Syntax**:\n
 * ~~~
 * EXPD83 Rd, Rs1
 * ~~~
 *
 * **Purpose**:\n
 * Copy 8-bit data from 32-bit chunks into 4 bytes in a register.
 *
 * **Description**:\n
 * Moves Rs1.B[3][7:0] to Rd.[0][7:0], Rd.[1][7:0], Rd.[2][7:0], Rd.[3][7:0]
 *
 * **Operations**:\n
 * ~~~
 * Rd.W[x][31:0] = CONCAT(Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0], Rs1.B[3][7:0]);
 * for RV32: x=0
 * ~~~
 *
 * \param [in]  a unsigned long type of value stored in a
 * \return value stored in unsigned long type
 */
__STATIC_FORCEINLINE unsigned long __RV_EXPD83(unsigned long a)
{
    unsigned long result;
    __ASM volatile("expd83 %0, %1" : "=r"(result) : "r"(a));
    return result;
}
/* ===== Inline Function End for A11.4. EXPD83 ===== */
#endif /* __RISCV_XLEN == 32 */

#if defined(__RISCV_FEATURE_DSP) && (__RISCV_FEATURE_DSP == 1)
/* XXXXX ARM Compatiable SIMD API XXXXX */
/** \brief Q setting quad 8-bit saturating addition. */
#define __QADD8(x, y)               __RV_KADD8(x, y)
/** \brief Q setting quad 8-bit saturating subtract. */
#define __QSUB8(x, y)               __RV_KSUB8((x), (y))
/** \brief Q setting dual 16-bit saturating addition. */
#define __QADD16(x, y)              __RV_KADD16((x), (y))
/** \brief Dual 16-bit signed addition with halved results. */
#define __SHADD16(x, y)             __RV_RADD16((x), (y))
/** \brief Q setting dual 16-bit saturating subtract. */
#define __QSUB16(x, y)              __RV_KSUB16((x), (y))
/** \brief Dual 16-bit signed subtraction with halved results. */
#define __SHSUB16(x, y)             __RV_RSUB16((x), (y))
/** \brief Q setting dual 16-bit add and subtract with exchange. */
#define __QASX(x, y)                __RV_KCRAS16((x), (y))
/** \brief Dual 16-bit signed addition and subtraction with halved results.*/
#define __SHASX(x, y)               __RV_RCRAS16((x), (y))
/** \brief Q setting dual 16-bit subtract and add with exchange. */
#define __QSAX(x, y)                __RV_KCRSA16((x), (y))
/** \brief Dual 16-bit signed subtraction and addition with halved results.*/
#define __SHSAX(x, y)               __RV_RCRSA16((x), (y))
/** \brief Dual 16-bit signed multiply with exchange returning difference. */
#define __SMUSDX(x, y)              __RV_SMXDS((y), (x))
/** \brief Q setting sum of dual 16-bit signed multiply with exchange. */
__STATIC_FORCEINLINE int32_t __SMUADX (int32_t op1, int32_t op2)
{
    return (int32_t)__RV_KMXDA(op1, op2);
}
/** \brief Q setting saturating add. */
#define __QADD(x, y)                __RV_KADDW((x), (y))
/** \brief Q setting saturating subtract. */
#define __QSUB(x, y)                __RV_KSUBW((x), (y))
/** \brief Q setting dual 16-bit signed multiply with single 32-bit accumulator. */
__STATIC_FORCEINLINE int32_t __SMLAD(int32_t op1, int32_t op2, int32_t op3)
{
    return (int32_t)__RV_KMADA(op3, op1, op2);
}
/** \brief Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.  */
__STATIC_FORCEINLINE int32_t __SMLADX(int32_t op1, int32_t op2, int32_t op3)
{
    return (int32_t)__RV_KMAXDA(op3, op1, op2);
}
/** \brief Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.  */
__STATIC_FORCEINLINE int32_t __SMLSDX(int32_t op1, int32_t op2, int32_t op3)
{
    return (op3 - (int32_t)__RV_SMXDS(op1, op2));
}
/** \brief Dual 16-bit signed multiply with single 64-bit accumulator. */
__STATIC_FORCEINLINE int64_t __SMLALD(int32_t op1, int32_t op2, int64_t acc)
{
    return (int64_t)__RV_SMALDA(acc, op1, op2);
}
/** \brief Dual 16-bit signed multiply with exchange with single 64-bit accumulator.  */
__STATIC_FORCEINLINE int64_t __SMLALDX(int32_t op1, int32_t op2, int64_t acc)
{
    return (int64_t)__RV_SMALXDA(acc, op1, op2);
}
/** \brief Q setting sum of dual 16-bit signed multiply. */
__STATIC_FORCEINLINE int32_t __SMUAD(int32_t op1, int32_t op2)
{
    return (int32_t)__RV_KMDA(op1, op2);
}
/** \brief Dual 16-bit signed multiply returning difference. */
__STATIC_FORCEINLINE int32_t __SMUSD(int32_t op1, int32_t op2)
{
    return (int32_t)__RV_SMDRS(op1, op2);
}
/** \brief Dual extract 8-bits and sign extend each to 16-bits. */
#define __SXTB16(x)             __RV_SUNPKD820(x)
/** \brief Dual extracted 8-bit to 16-bit signed addition. TODO Need test */
__STATIC_FORCEINLINE int32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
    return __RV_ADD16(op1, __RV_SUNPKD820(op2));
}
#define __SXTAB16_RORn(ARG1, ARG2, ROTATE)        __SXTAB16(ARG1, __ROR(ARG2, ROTATE))

/** \brief 32-bit signed multiply with 32-bit truncated accumulator. */
__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
{
    int32_t mul;
    mul = (int32_t)__RV_SMMUL(op1, op2);
    return (op3 + mul);
}
#define __DKHM8                 __RV_DKHM8
#define __DKHM16                __RV_DKHM16
#define __DKSUB16               __RV_DKSUB16
#define __SMAQA                 __RV_SMAQA
#define __MULSR64               __RV_MULSR64
#define __DQADD8                __RV_DKADD8
#define __DQSUB8                __RV_DKSUB8
#define __DKADD16               __RV_DKADD16
#define __PKBB16                __RV_PKBB16
#define __DKSLRA16              __RV_DKSLRA16
#define __DKSLRA8               __RV_DKSLRA8
#define __KABSW                 __RV_KABSW
#define __DKABS8                __RV_DKABS8
#define __DKABS16               __RV_DKABS16
#define __SMALDA                __RV_SMALDA
#define __SMSLDA                __RV_SMSLDA
#define __SMALBB                __RV_SMALBB
#define __SUB64                 __RV_SUB64
#define __ADD64                 __RV_ADD64
#define __SMBB16                __RV_SMBB16
#define __SMBT16                __RV_SMBT16
#define __SMTT16                __RV_SMTT16
#define __EXPD80                __RV_EXPD80
#define __SMAX8                 __RV_SMAX8
#define __SMAX16                __RV_SMAX16
#define __PKTT16                __RV_PKTT16
#define __KADD16                __RV_KADD16
#define __SADD16                __RV_ADD16
#define __SSUB8                 __RV_KSUB8
#define __SADD8                 __RV_KADD8
#define __USAT16                __RV_UCLIP16

/** \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. */
#define __PKHBT(ARG1,ARG2,ARG3)     ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
                                    ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
/** \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. */
#define __PKHTB(ARG1,ARG2,ARG3)     ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
                                    ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

/** first rotate then extract. This is more suitable for arm compiler for it can rotate and extract in one command*/
#define __SXTB16_RORn(ARG1, ARG2)   __RV_SUNPKD820(__ROR(ARG1, ARG2))

#endif /* (__RISCV_FEATURE_DSP == 1) */

#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_FEATURE_DSP__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_eclic.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_ECLIC__
#define __CORE_FEATURE_ECLIC__
/*!
 * @file     core_feature_eclic.h
 * @brief    ECLIC feature API header file for Nuclei N/NX Core
 */
/*
 * ECLIC Feature Configuration Macro:
 * 1. __ECLIC_PRESENT:  Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not
 *   * 0: Not present
 *   * 1: Present
 * 2. __ECLIC_BASEADDR:  Base address of the ECLIC unit.
 * 3. ECLIC_GetInfoCtlbits():  Define the number of hardware bits are actually implemented in the clicintctl registers.
 *   Valid number is 1 - 8.
 * 4. __ECLIC_INTNUM  : Define the external interrupt number of ECLIC Unit
 *
 */
#ifdef __cplusplus
 extern "C" {
#endif

#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
/**
 * \defgroup NMSIS_Core_ECLIC_Registers     Register Define and Type Definitions Of ECLIC
 * \ingroup NMSIS_Core_Registers
 * \brief   Type definitions and defines for eclic registers.
 *
 * @{
 */

/**
 * \brief  Union type to access CLICFG configure register.
 */
typedef union
{
    struct {
        uint8_t _reserved0:1;                   /*!< bit:     0   Overflow condition code flag */
        uint8_t nlbits:4;                       /*!< bit:     29  Carry condition code flag */
        uint8_t _reserved1:2;                   /*!< bit:     30  Zero condition code flag */
        uint8_t _reserved2:1;                   /*!< bit:     31  Negative condition code flag */
    } b;                                        /*!< Structure used for bit  access */
    uint8_t w;                                  /*!< Type      used for byte access */
} CLICCFG_Type;

/**
 * \brief  Union type to access CLICINFO information register.
 */
typedef union {
    struct {
        uint32_t numint:13;                     /*!< bit:  0..12   number of maximum interrupt inputs supported */
        uint32_t version:8;                     /*!< bit:  13..20  20:17 for architecture version,16:13 for implementation version */
        uint32_t intctlbits:4;                  /*!< bit:  21..24  specifies how many hardware bits are actually implemented in the clicintctl registers */
        uint32_t _reserved0:7;                  /*!< bit:  25..31  Reserved */
    } b;                                        /*!< Structure used for bit  access */
    uint32_t w;                                 /*!< Type      used for word access */
} CLICINFO_Type;

/**
 * \brief Access to the structure of a vector interrupt controller.
 */
typedef struct {
    __IOM uint8_t  INTIP;                       /*!< Offset: 0x000 (R/W)  Interrupt set pending register */
    __IOM uint8_t  INTIE;                       /*!< Offset: 0x001 (R/W)  Interrupt set enable register */
    __IOM uint8_t  INTATTR;                     /*!< Offset: 0x002 (R/W)  Interrupt set attributes register */
    __IOM uint8_t  INTCTRL;                     /*!< Offset: 0x003 (R/W)  Interrupt configure register */
} CLIC_CTRL_Type;

typedef struct {
    __IOM uint8_t   CFG;                        /*!< Offset: 0x000 (R/W)  CLIC configuration register */
    uint8_t RESERVED0[3];
    __IM uint32_t  INFO;                        /*!< Offset: 0x004 (R/ )  CLIC information register */
    uint8_t RESERVED1[3];
    __IOM uint8_t  MTH;                         /*!< Offset: 0x00B (R/W)  CLIC machine mode threshold register */
    uint32_t RESERVED2[0x3FD];
    CLIC_CTRL_Type CTRL[4096];                  /*!< Offset: 0x1000 (R/W) CLIC register structure for INTIP, INTIE, INTATTR, INTCTL */
} CLIC_Type;

#define CLIC_CLICCFG_NLBIT_Pos                 1U                                       /*!< CLIC CLICCFG: NLBIT Position */
#define CLIC_CLICCFG_NLBIT_Msk                 (0xFUL << CLIC_CLICCFG_NLBIT_Pos)        /*!< CLIC CLICCFG: NLBIT Mask */

#define CLIC_CLICINFO_CTLBIT_Pos                21U                                     /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position */
#define CLIC_CLICINFO_CTLBIT_Msk                (0xFUL << CLIC_CLICINFO_CTLBIT_Pos)     /*!< CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask */

#define CLIC_CLICINFO_VER_Pos                  13U                                      /*!< CLIC CLICINFO: VERSION Position */
#define CLIC_CLICINFO_VER_Msk                  (0xFFUL << CLIC_CLICCFG_NLBIT_Pos)       /*!< CLIC CLICINFO: VERSION Mask */

#define CLIC_CLICINFO_NUM_Pos                  0U                                       /*!< CLIC CLICINFO: NUM Position */
#define CLIC_CLICINFO_NUM_Msk                  (0xFFFUL << CLIC_CLICINFO_NUM_Pos)       /*!< CLIC CLICINFO: NUM Mask */

#define CLIC_INTIP_IP_Pos                      0U                                       /*!< CLIC INTIP: IP Position */
#define CLIC_INTIP_IP_Msk                      (0x1UL << CLIC_INTIP_IP_Pos)             /*!< CLIC INTIP: IP Mask */

#define CLIC_INTIE_IE_Pos                      0U                                       /*!< CLIC INTIE: IE Position */
#define CLIC_INTIE_IE_Msk                      (0x1UL << CLIC_INTIE_IE_Pos)             /*!< CLIC INTIE: IE Mask */

#define CLIC_INTATTR_TRIG_Pos                  1U                                       /*!< CLIC INTATTR: TRIG Position */
#define CLIC_INTATTR_TRIG_Msk                  (0x3UL << CLIC_INTATTR_TRIG_Pos)         /*!< CLIC INTATTR: TRIG Mask */

#define CLIC_INTATTR_SHV_Pos                   0U                                       /*!< CLIC INTATTR: SHV Position */
#define CLIC_INTATTR_SHV_Msk                   (0x1UL << CLIC_INTATTR_SHV_Pos)          /*!< CLIC INTATTR: SHV Mask */

#define ECLIC_MAX_NLBITS                       8U                                       /*!< Max nlbit of the CLICINTCTLBITS */
#define ECLIC_MODE_MTVEC_Msk                   3U                                       /*!< ECLIC Mode mask for MTVT CSR Register */

#define ECLIC_NON_VECTOR_INTERRUPT             0x0                                      /*!< Non-Vector Interrupt Mode of ECLIC */
#define ECLIC_VECTOR_INTERRUPT                 0x1                                      /*!< Vector Interrupt Mode of ECLIC */

/**\brief ECLIC Trigger Enum for different Trigger Type */
typedef enum ECLIC_TRIGGER {
    ECLIC_LEVEL_TRIGGER = 0x0,          /*!< Level Triggerred, trig[0] = 0 */
    ECLIC_POSTIVE_EDGE_TRIGGER = 0x1,   /*!< Postive/Rising Edge Triggered, trig[0] = 1, trig[1] = 0 */
    ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3,   /*!< Negtive/Falling Edge Triggered, trig[0] = 1, trig[1] = 1 */
    ECLIC_MAX_TRIGGER = 0x3             /*!< MAX Supported Trigger Mode */
} ECLIC_TRIGGER_Type;

#ifndef __ECLIC_BASEADDR
/* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in  */
#error "__ECLIC_BASEADDR is not defined, please check!"
#endif

#ifndef __ECLIC_INTCTLBITS
/* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */
#define __ECLIC_INTCTLBITS                  (__ECLIC_GetInfoCtlbits())
#endif

/* ECLIC Memory mapping of Device */
#define ECLIC_BASE                          __ECLIC_BASEADDR                            /*!< ECLIC Base Address */
#define ECLIC                               ((CLIC_Type *) ECLIC_BASE)                  /*!< CLIC configuration struct */

/** @} */ /* end of group NMSIS_Core_ECLIC_Registers */

/* ##########################   ECLIC functions  #################################### */
/**
 * \defgroup   NMSIS_Core_IntExc        Interrupts and Exceptions
 * \brief Functions that manage interrupts and exceptions via the ECLIC.
 *
 * @{
 */

/**
 * \brief  Definition of IRQn numbers
 * \details
 * The core interrupt enumeration names for IRQn values are defined in the file .h.
 * - Interrupt ID(IRQn) from 0 to 18 are reserved for core internal interrupts.
 * - Interrupt ID(IRQn) start from 19 represent device-specific external interrupts.
 * - The first device-specific interrupt has the IRQn value 19.
 *
 * The table below describes the core interrupt names and their availability in various Nuclei Cores.
 */
/* The following enum IRQn definition in this file
 * is only used for doxygen documentation generation,
 * The .h is the real file to define it by vendor
 */
#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
typedef enum IRQn {
    /* ========= Nuclei N/NX Core Specific Interrupt Numbers  =========== */
    /* Core Internal Interrupt IRQn definitions */
    Reserved0_IRQn            =   0,              /*!<  Internal reserved */
    Reserved1_IRQn            =   1,              /*!<  Internal reserved */
    Reserved2_IRQn            =   2,              /*!<  Internal reserved */
    SysTimerSW_IRQn           =   3,              /*!<  System Timer SW interrupt */
    Reserved3_IRQn            =   4,              /*!<  Internal reserved */
    Reserved4_IRQn            =   5,              /*!<  Internal reserved */
    Reserved5_IRQn            =   6,              /*!<  Internal reserved */
    SysTimer_IRQn             =   7,              /*!<  System Timer Interrupt */
    Reserved6_IRQn            =   8,              /*!<  Internal reserved */
    Reserved7_IRQn            =   9,              /*!<  Internal reserved */
    Reserved8_IRQn            =  10,              /*!<  Internal reserved */
    Reserved9_IRQn            =  11,              /*!<  Internal reserved */
    Reserved10_IRQn           =  12,              /*!<  Internal reserved */
    Reserved11_IRQn           =  13,              /*!<  Internal reserved */
    Reserved12_IRQn           =  14,              /*!<  Internal reserved */
    Reserved13_IRQn           =  15,              /*!<  Internal reserved */
    Reserved14_IRQn           =  16,              /*!<  Internal reserved */
    Reserved15_IRQn           =  17,              /*!<  Internal reserved */
    Reserved16_IRQn           =  18,              /*!<  Internal reserved */

    /* ========= Device Specific Interrupt Numbers  =================== */
    /* ToDo: add here your device specific external interrupt numbers.
     * 19~max(NUM_INTERRUPT, 1023) is reserved number for user.
     * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT.
     * According the interrupt handlers defined in startup_Device.S
     * eg.: Interrupt for Timer#1       eclic_tim1_handler   ->   TIM1_IRQn */
    FirstDeviceSpecificInterrupt_IRQn    = 19,    /*!< First Device Specific Interrupt */
    SOC_INT_MAX,                                  /*!< Number of total interrupts */
} IRQn_Type;
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */

#ifdef NMSIS_ECLIC_VIRTUAL
    #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE
        #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h"
    #endif
    #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#else
    #define ECLIC_SetCfgNlbits            __ECLIC_SetCfgNlbits
    #define ECLIC_GetCfgNlbits            __ECLIC_GetCfgNlbits
    #define ECLIC_GetInfoVer              __ECLIC_GetInfoVer
    #define ECLIC_GetInfoCtlbits          __ECLIC_GetInfoCtlbits
    #define ECLIC_GetInfoNum              __ECLIC_GetInfoNum
    #define ECLIC_SetMth                  __ECLIC_SetMth
    #define ECLIC_GetMth                  __ECLIC_GetMth
    #define ECLIC_EnableIRQ               __ECLIC_EnableIRQ
    #define ECLIC_GetEnableIRQ            __ECLIC_GetEnableIRQ
    #define ECLIC_DisableIRQ              __ECLIC_DisableIRQ
    #define ECLIC_SetPendingIRQ           __ECLIC_SetPendingIRQ
    #define ECLIC_GetPendingIRQ           __ECLIC_GetPendingIRQ
    #define ECLIC_ClearPendingIRQ         __ECLIC_ClearPendingIRQ
    #define ECLIC_SetTrigIRQ              __ECLIC_SetTrigIRQ
    #define ECLIC_GetTrigIRQ              __ECLIC_GetTrigIRQ
    #define ECLIC_SetShvIRQ               __ECLIC_SetShvIRQ
    #define ECLIC_GetShvIRQ               __ECLIC_GetShvIRQ
    #define ECLIC_SetCtrlIRQ              __ECLIC_SetCtrlIRQ
    #define ECLIC_GetCtrlIRQ              __ECLIC_GetCtrlIRQ
    #define ECLIC_SetLevelIRQ             __ECLIC_SetLevelIRQ
    #define ECLIC_GetLevelIRQ             __ECLIC_GetLevelIRQ
    #define ECLIC_SetPriorityIRQ          __ECLIC_SetPriorityIRQ
    #define ECLIC_GetPriorityIRQ          __ECLIC_GetPriorityIRQ

#endif /* NMSIS_ECLIC_VIRTUAL */

#ifdef NMSIS_VECTAB_VIRTUAL
    #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE
        #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h"
    #endif
    #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
    #define ECLIC_SetVector              __ECLIC_SetVector
    #define ECLIC_GetVector              __ECLIC_GetVector
#endif  /* (NMSIS_VECTAB_VIRTUAL) */

/**
 * \brief  Set nlbits value
 * \details
 * This function set the nlbits value of CLICCFG register.
 * \param [in]    nlbits    nlbits value
 * \remarks
 * - nlbits is used to set the width of level in the CLICINTCTL[i].
 * \sa
 * - \ref ECLIC_GetCfgNlbits
 */
__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
{
    ECLIC->CFG &= ~CLIC_CLICCFG_NLBIT_Msk;
    ECLIC->CFG |= (uint8_t)((nlbits <CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
}

/**
 * \brief  Get the ECLIC version number
 * \details
 * This function gets the hardware version information from CLICINFO register.
 * \return   hardware version number in CLICINFO register.
 * \remarks
 * - This function gets harware version information from CLICINFO register.
 * - Bit 20:17 for architecture version, bit 16:13 for implementation version.
 * \sa
 * - \ref ECLIC_GetInfoNum
*/
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
}

/**
 * \brief  Get CLICINTCTLBITS
 * \details
 * This function gets CLICINTCTLBITS from CLICINFO register.
 * \return  CLICINTCTLBITS from CLICINFO register.
 * \remarks
 * - In the CLICINTCTL[i] registers, with 2 <= CLICINTCTLBITS <= 8.
 * - The implemented bits are kept left-justified in the most-significant bits of each 8-bit
 *   CLICINTCTL[I] register, with the lower unimplemented bits treated as hardwired to 1.
 * \sa
 * - \ref ECLIC_GetInfoNum
 */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
}

/**
 * \brief  Get number of maximum interrupt inputs supported
 * \details
 * This function gets number of maximum interrupt inputs supported from CLICINFO register.
 * \return  number of maximum interrupt inputs supported from CLICINFO register.
 * \remarks
 * - This function gets number of maximum interrupt inputs supported from CLICINFO register.
 * - The num_interrupt field specifies the actual number of maximum interrupt inputs supported in this implementation.
 * \sa
 * - \ref ECLIC_GetInfoCtlbits
 */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
}

/**
 * \brief  Set Machine Mode Interrupt Level Threshold
 * \details
 * This function sets machine mode interrupt level threshold.
 * \param [in]  mth       Interrupt Level Threshold.
 * \sa
 * - \ref ECLIC_GetMth
 */
__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
{
    ECLIC->MTH = mth;
}

/**
 * \brief  Get Machine Mode Interrupt Level Threshold
 * \details
 * This function gets machine mode interrupt level threshold.
 * \return       Interrupt Level Threshold.
 * \sa
 * - \ref ECLIC_SetMth
 */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
{
    return (ECLIC->MTH);
}


/**
 * \brief  Enable a specific interrupt
 * \details
 * This function enables the specific interrupt \em IRQn.
 * \param [in]  IRQn  Interrupt number
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_DisableIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}

/**
 * \brief  Get a specific interrupt enable status
 * \details
 * This function returns the interrupt enable status for the specific interrupt \em IRQn.
 * \param [in]  IRQn  Interrupt number
 * \returns
 * - 0  Interrupt is not enabled
 * - 1  Interrupt is pending
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_EnableIRQ
 * - \ref ECLIC_DisableIRQ
 */
__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
{
    return((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}

/**
 * \brief  Disable a specific interrupt
 * \details
 * This function disables the specific interrupt \em IRQn.
 * \param [in]  IRQn  Number of the external interrupt to disable
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_EnableIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}

/**
 * \brief  Get the pending specific interrupt
 * \details
 * This function returns the pending status of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \returns
 * - 0  Interrupt is not pending
 * - 1  Interrupt is pending
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_SetPendingIRQ
 * - \ref ECLIC_ClearPendingIRQ
 */
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
{
    return((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}

/**
 * \brief  Set a specific interrupt to pending
 * \details
 * This function sets the pending bit for the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_GetPendingIRQ
 * - \ref ECLIC_ClearPendingIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}

/**
 * \brief  Clear a specific interrupt from pending
 * \details
 * This function removes the pending state of the specific interrupt \em IRQn.
 * \em IRQn cannot be a negative number.
 * \param [in]      IRQn  Interrupt number
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_SetPendingIRQ
 * - \ref ECLIC_GetPendingIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIP &= ~ CLIC_INTIP_IP_Msk;
}

/**
 * \brief  Set trigger mode and polarity for a specific interrupt
 * \details
 * This function set trigger mode and polarity of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      trig
 *                   - 00  level trigger, \ref ECLIC_LEVEL_TRIGGER
 *                   - 01  positive edge trigger, \ref ECLIC_POSTIVE_EDGE_TRIGGER
 *                   - 02  level trigger, \ref ECLIC_LEVEL_TRIGGER
 *                   - 03  negative edge trigger, \ref ECLIC_NEGTIVE_EDGE_TRIGGER
 * \remarks
 * - IRQn must not be negative.
 *
 * \sa
 * - \ref ECLIC_GetTrigIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
{
    ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_TRIG_Msk;
    ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(trig<CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk)>>CLIC_INTATTR_TRIG_Pos));
}

/**
 * \brief  Set interrupt working mode for a specific interrupt
 * \details
 * This function set selective hardware vector or non-vector working mode of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      shv
 *                        - 0  non-vector mode, \ref ECLIC_NON_VECTOR_INTERRUPT
 *                        - 1  vector mode, \ref ECLIC_VECTOR_INTERRUPT
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_GetShvIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
{
    ECLIC->CTRL[IRQn].INTATTR &= ~CLIC_INTATTR_SHV_Msk;
    ECLIC->CTRL[IRQn].INTATTR |= (uint8_t)(shv<CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk)>>CLIC_INTATTR_SHV_Pos));
}

/**
 * \brief  Modify ECLIC Interrupt Input Control Register for a specific interrupt
 * \details
 * This function modify ECLIC Interrupt Input Control(CLICINTCTL[i]) register of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      intctrl  Set value for CLICINTCTL[i] register
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_GetCtrlIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
{
    ECLIC->CTRL[IRQn].INTCTRL = intctrl;
}

/**
 * \brief  Get ECLIC Interrupt Input Control Register value for a specific interrupt
 * \details
 * This function modify ECLIC Interrupt Input Control register of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \return       value of ECLIC Interrupt Input Control register
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_SetCtrlIRQ
 */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
{
    return (ECLIC->CTRL[IRQn].INTCTRL);
}

/**
 * \brief  Set ECLIC Interrupt level of a specific interrupt
 * \details
 * This function set interrupt level of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      lvl_abs   Interrupt level
 * \remarks
 * - IRQn must not be negative.
 * - If lvl_abs to be set is larger than the max level allowed, it will be force to be max level.
 * - When you set level value you need use clciinfo.nlbits to get the width of level.
 *   Then we could know the maximum of level. CLICINTCTLBITS is how many total bits are
 *   present in the CLICINTCTL register.
 * \sa
 * - \ref ECLIC_GetLevelIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;

    if (nlbits == 0) {
        return;
    }

    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t maxlvl = ((1 << nlbits) - 1);
    if (lvl_abs > maxlvl) {
        lvl_abs = maxlvl;
    }
    uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits);
    uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
    cur_ctrl = cur_ctrl << nlbits;
    cur_ctrl = cur_ctrl >> nlbits;
    __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl));
}

/**
 * \brief  Get ECLIC Interrupt level of a specific interrupt
 * \details
 * This function get interrupt level of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \return         Interrupt level
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_SetLevelIRQ
 */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;

    if (nlbits == 0) {
        return 0;
    }

    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn);
    uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits);
    return lvl_abs;
}

/**
 * \brief  Get ECLIC Interrupt priority of a specific interrupt
 * \details
 * This function get interrupt priority of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      pri   Interrupt priority
 * \remarks
 * - IRQn must not be negative.
 * - If pri to be set is larger than the max priority allowed, it will be force to be max priority.
 * - Priority width is CLICINTCTLBITS minus clciinfo.nlbits if clciinfo.nlbits
 *   is less than CLICINTCTLBITS. Otherwise priority width is 0.
 * \sa
 * - \ref ECLIC_GetPriorityIRQ
 */
__STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
        if (pri > maxpri) {
            pri = maxpri;
        }
        pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
        uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
        pri = pri | mask;
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
        cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
        cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
        __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri));
    }
}

/**
 * \brief  Get ECLIC Interrupt priority of a specific interrupt
 * \details
 * This function get interrupt priority of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \return   Interrupt priority
 * \remarks
 * - IRQn must not be negative.
 * \sa
 * - \ref ECLIC_SetPriorityIRQ
 */
__STATIC_FORCEINLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
        uint8_t pri = cur_ctrl << nlbits;
        pri = pri >> nlbits;
        pri = pri >> (ECLIC_MAX_NLBITS - intctlbits);
        return pri;
    } else {
        return 0;
    }
}

/**
 * \brief  Set Interrupt Vector of a specific interrupt
 * \details
 * This function set interrupt handler address of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \param [in]      vector   Interrupt handler address
 * \remarks
 * - IRQn must not be negative.
 * - You can set the \ref CSR_CSR_MTVT to set interrupt vector table entry address.
 * - If your vector table is placed in readonly section, the vector for IRQn will not be modified.
 *   For this case, you need to use the correct irq handler name defined in your vector table as
 *   your irq handler function name.
 * - This function will only work correctly when the vector table is placed in an read-write enabled section.
 * \sa
 * - \ref ECLIC_GetVector
 */
__STATIC_FORCEINLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
{
#if __RISCV_XLEN == 32
    volatile uint32_t vec_base;
    vec_base = ((uint32_t)__RV_CSR_READ(CSR_MTVT));
    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 4)) = vector;
#elif __RISCV_XLEN == 64
    volatile uint64_t vec_base;
    vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector;
#else // TODO Need cover for XLEN=128 case in future
    volatile uint64_t vec_base;
    vec_base = ((uint64_t)__RV_CSR_READ(CSR_MTVT));
    (* (unsigned long *) (vec_base + ((int32_t)IRQn) * 8)) = vector;
#endif
}

/**
 * \brief  Get Interrupt Vector of a specific interrupt
 * \details
 * This function get interrupt handler address of the specific interrupt \em IRQn.
 * \param [in]      IRQn  Interrupt number
 * \return        Interrupt handler address
 * \remarks
 * - IRQn must not be negative.
 * - You can read \ref CSR_CSR_MTVT to get interrupt vector table entry address.
 * \sa
 *     - \ref ECLIC_SetVector
 */
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
{
#if __RISCV_XLEN == 32
    return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*4));
#elif __RISCV_XLEN == 64
    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8));
#else // TODO Need cover for XLEN=128 case in future
    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT)+IRQn*8));
#endif
}

/**
 * \brief  Set Exception entry address
 * \details
 * This function set exception handler address to 'CSR_MTVEC'.
 * \param [in]      addr  Exception handler address
 * \remarks
 * - This function use to set exception handler address to 'CSR_MTVEC'. Address is 4 bytes align.
 * \sa
 * - \ref __get_exc_entry
 */
__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
{
    addr &= (rv_csr_t)(~0x3F);
    addr |= ECLIC_MODE_MTVEC_Msk;
    __RV_CSR_WRITE(CSR_MTVEC, addr);
}

/**
 * \brief  Get Exception entry address
 * \details
 * This function get exception handler address from 'CSR_MTVEC'.
 * \return       Exception handler address
 * \remarks
 * - This function use to get exception handler address from 'CSR_MTVEC'. Address is 4 bytes align
 * \sa
 * - \ref __set_exc_entry
 */
__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
{
    unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
    return (addr & ~ECLIC_MODE_MTVEC_Msk);
}

/**
 * \brief  Set Non-vector interrupt entry address
 * \details
 * This function set Non-vector interrupt address.
 * \param [in]      addr  Non-vector interrupt entry address
 * \remarks
 * - This function use to set non-vector interrupt entry address to 'CSR_MTVT2' if
 * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then set address to 'CSR_MTVEC'
 * \sa
 * - \ref __get_nonvec_entry
 */
__STATIC_FORCEINLINE void __set_nonvec_entry(rv_csr_t addr)
{
    if (__RV_CSR_READ(CSR_MTVT2) & 0x1){
        __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
    } else {
        addr &= (rv_csr_t)(~0x3F);
        addr |= ECLIC_MODE_MTVEC_Msk;
        __RV_CSR_WRITE(CSR_MTVEC, addr);
    }
}

/**
 * \brief  Get Non-vector interrupt entry address
 * \details
 * This function get Non-vector interrupt address.
 * \return      Non-vector interrupt handler address
 * \remarks
 * - This function use to get non-vector interrupt entry address from 'CSR_MTVT2' if
 * - CSR_MTVT2 bit0 is 1. If 'CSR_MTVT2' bit0 is 0 then get address from 'CSR_MTVEC'.
 * \sa
 * - \ref __set_nonvec_entry
 */
__STATIC_FORCEINLINE rv_csr_t __get_nonvec_entry(void)
{
    if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
        return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
    } else {
        rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC);
        return (addr & ~ECLIC_MODE_MTVEC_Msk);
    }
}

/**
 * \brief  Get NMI interrupt entry from 'CSR_MNVEC'
 * \details
 * This function get NMI interrupt address from 'CSR_MNVEC'.
 * \return      NMI interrupt handler address
 * \remarks
 * - This function use to get NMI interrupt handler address from 'CSR_MNVEC'. If CSR_MMISC_CTL[9] = 1 'CSR_MNVEC'
 * - will be equal as mtvec. If CSR_MMISC_CTL[9] = 0 'CSR_MNVEC' will be equal as reset vector.
 * - NMI entry is defined via \ref CSR_MMISC_CTL, writing to \ref CSR_MNVEC will be ignored.
 */
__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
{
    return __RV_CSR_READ(CSR_MNVEC);
}

/**
 * \brief   Save necessary CSRs into variables for vector interrupt nesting
 * \details
 * This macro is used to declare variables which are used for saving
 * CSRs(MCAUSE, MEPC, MSUB), and it will read these CSR content into
 * these variables, it need to be used in a vector-interrupt if nesting
 * is required.
 * \remarks
 * - Interrupt will be enabled after this macro is called
 * - It need to be used together with \ref RESTORE_IRQ_CSR_CONTEXT
 * - Don't use variable names __mcause, __mpec, __msubm in your ISR code
 * - If you want to enable interrupt nesting feature for vector interrupt,
 * you can do it like this:
 * \code
 * // __INTERRUPT attribute will generates function entry and exit sequences suitable
 * // for use in an interrupt handler when this attribute is present
 * __INTERRUPT void eclic_mtip_handler(void)
 * {
 *     // Must call this to save CSRs
 *     SAVE_IRQ_CSR_CONTEXT();
 *     // !!!Interrupt is enabled here!!!
 *     // !!!Higher priority interrupt could nest it!!!
 *
 *     // put you own interrupt handling code here
 *
 *     // Must call this to restore CSRs
 *     RESTORE_IRQ_CSR_CONTEXT();
 * }
 * \endcode
 */
#define SAVE_IRQ_CSR_CONTEXT()                                              \
        rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE);                      \
        rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC);                          \
        rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM);                        \
        __enable_irq();

/**
 * \brief   Restore necessary CSRs from variables for vector interrupt nesting
 * \details
 * This macro is used restore CSRs(MCAUSE, MEPC, MSUB) from pre-defined variables
 * in \ref SAVE_IRQ_CSR_CONTEXT macro.
 * \remarks
 * - Interrupt will be disabled after this macro is called
 * - It need to be used together with \ref SAVE_IRQ_CSR_CONTEXT
 */
#define RESTORE_IRQ_CSR_CONTEXT()                                           \
        __disable_irq();                                                    \
        __RV_CSR_WRITE(CSR_MSUBM, __msubm);                                 \
        __RV_CSR_WRITE(CSR_MEPC, __mepc);                                   \
        __RV_CSR_WRITE(CSR_MCAUSE, __mcause);

/** @} */ /* End of Doxygen Group NMSIS_Core_IntExc */

#endif /* defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) */

#ifdef __cplusplus
}
#endif
#endif /** __CORE_FEATURE_ECLIC__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_fpu.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_FPU_H__
#define __CORE_FEATURE_FPU_H__
/*!
 * @file     core_feature_fpu.h
 * @brief    FPU feature API header file for Nuclei N/NX Core
 */
/*
 * FPU Feature Configuration Macro:
 * 1. __FPU_PRESENT:  Define whether Floating Point Unit(FPU) is present or not
 *   * 0: Not present
 *   * 1: Single precision FPU present, __RISCV_FLEN == 32
 *   * 2: Double precision FPU present, __RISCV_FLEN == 64
 */
#ifdef __cplusplus
 extern "C" {
#endif

/* ===== FPU Operations ===== */
/**
 * \defgroup NMSIS_Core_FPU_Functions   FPU Functions
 * \ingroup  NMSIS_Core
 * \brief    Functions that related to the RISC-V FPU (F and D extension).
 * \details
 *
 * Nuclei provided floating point unit by RISC-V F and D extension.
 * * `F extension` adds single-precision floating-point computational
 * instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32.
 *   The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide,
 *   and a floating-point control and status register fcsr, which contains the
 *   operating mode and exception status of the floating-point unit.
 * * `D extension` adds double-precision floating-point computational instructions
 * compliant with the IEEE 754-2008 arithmetic standard.
 *   The D extension widens the 32 floating-point registers, f0-f31, to 64 bits, __RISCV_FLEN = 64
 *   @{
 */
#if defined(__FPU_PRESENT) && (__FPU_PRESENT > 0)

#if __FPU_PRESENT == 1
  /** \brief Refer to the width of the floating point register in bits(either 32 or 64) */
  #define __RISCV_FLEN          32
#elif __FPU_PRESENT == 2
  #define __RISCV_FLEN          64
#else
  #define __RISCV_FLEN          __riscv_flen
#endif /* __FPU_PRESENT == 1 */

/** \brief Get FCSR CSR Register */
#define __get_FCSR()            __RV_CSR_READ(CSR_FCSR)
/** \brief Set FCSR CSR Register with val */
#define __set_FCSR(val)         __RV_CSR_WRITE(CSR_FCSR, (val))
/** \brief Get FRM CSR Register */
#define __get_FRM()             __RV_CSR_READ(CSR_FRM)
/** \brief Set FRM CSR Register with val */
#define __set_FRM(val)          __RV_CSR_WRITE(CSR_FRM, (val))
/** \brief Get FFLAGS CSR Register */
#define __get_FFLAGS()          __RV_CSR_READ(CSR_FFLAGS)
/** \brief Set FFLAGS CSR Register with val */
#define __set_FFLAGS(val)       __RV_CSR_WRITE(CSR_FFLAGS, (val))

/** \brief Enable FPU Unit */
#define __enable_FPU()          __RV_CSR_SET(CSR_MSTATUS, MSTATUS_FS)
/**
 * \brief Disable FPU Unit
 * \details
 * * We can save power by disable FPU Unit.
 * * When FPU Unit is disabled, any access to FPU related CSR registers
 * and FPU instructions will cause illegal Instuction Exception.
 * */
#define __disable_FPU()         __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)


/**
 * \brief   Load a single-precision value from memory into float point register freg using flw instruction
 * \details The FLW instruction loads a single-precision floating point value from memory
 * address (addr + ofs) into floating point register freg(f0-f31)
 * \param [in]    freg   The floating point register, eg. FREG(0), f0
 * \param [in]    addr   The memory base address, 4 byte aligned required
 * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
 * \remarks
 * * FLW and FSW operations need to make sure the address is 4 bytes aligned,
 *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
 * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical
 * NaNs are preserved
 *
 */
#define __RV_FLW(freg, addr, ofs)                              \
    ({                                                         \
        register rv_csr_t __addr = (rv_csr_t)(addr);           \
        __ASM volatile("flw " STRINGIFY(freg) ", %0(%1)  "     \
                     : : "I"(ofs), "r"(__addr)                 \
                     : "memory");                              \
    })

/**
 * \brief   Store a single-precision value from float point freg into memory using fsw instruction
 * \details The FSW instruction stores a single-precision value from floating point register to memory
 * \param [in]    freg   The floating point register(f0-f31), eg. FREG(0), f0
 * \param [in]    addr   The memory base address, 4 byte aligned required
 * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
 * \remarks
 * * FLW and FSW operations need to make sure the address is 4 bytes aligned,
 *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
 * * FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical
 * NaNs are preserved
 *
 */
#define __RV_FSW(freg, addr, ofs)                              \
    ({                                                         \
        register rv_csr_t __addr = (rv_csr_t)(addr);           \
        __ASM volatile("fsw " STRINGIFY(freg) ", %0(%1)  "     \
                     : : "I"(ofs), "r"(__addr)                 \
                     : "memory");                              \
    })

/**
 * \brief   Load a double-precision value from memory into float point register freg using fld instruction
 * \details The FLD instruction loads a double-precision floating point value from memory
 * address (addr + ofs) into floating point register freg(f0-f31)
 * \param [in]    freg   The floating point register, eg. FREG(0), f0
 * \param [in]    addr   The memory base address, 8 byte aligned required
 * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
 * \attention
 * * Function only available for double precision floating point unit, FLEN = 64
 * \remarks
 * * FLD and FSD operations need to make sure the address is 8 bytes aligned,
 *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
 * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical
 * NaNs are preserved.
 */
#define __RV_FLD(freg, addr, ofs)                              \
    ({                                                         \
        register rv_csr_t __addr = (rv_csr_t)(addr);           \
        __ASM volatile("fld " STRINGIFY(freg) ", %0(%1)  "     \
                     : : "I"(ofs), "r"(__addr)                 \
                     : "memory");                              \
    })

/**
 * \brief   Store a double-precision value from float point freg into memory using fsd instruction
 * \details The FSD instruction stores double-precision value from floating point register to memory
 * \param [in]    freg   The floating point register(f0-f31), eg. FREG(0), f0
 * \param [in]    addr   The memory base address, 8 byte aligned required
 * \param [in]    ofs    a 12-bit immediate signed byte offset value, should be an const value
 * \attention
 * * Function only available for double precision floating point unit, FLEN = 64
 * \remarks
 * * FLD and FSD operations need to make sure the address is 8 bytes aligned,
 *   otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
 * * FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical
 * NaNs are preserved.
 *
 */
#define __RV_FSD(freg, addr, ofs)                              \
    ({                                                         \
        register rv_csr_t __addr = (rv_csr_t)(addr);           \
        __ASM volatile("fsd " STRINGIFY(freg) ", %0(%1)  "     \
                     : : "I"(ofs), "r"(__addr)                 \
                     : "memory");                              \
    })

/**
 * \def __RV_FLOAD
 * \brief   Load a float point value from memory into float point register freg using flw/fld instruction
 * \details
 * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32):
 *   It will call \ref __RV_FLW to load a single-precision floating point value from memory to floating point register
 * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64):
 *   It will call \ref __RV_FLD to load a double-precision floating point value from memory to floating point register
 *
 * \attention
 * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent
 */
/**
 * \def __RV_FSTORE
 * \brief   Store a float value from float point freg into memory using fsw/fsd instruction
 * \details
 * * For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32):
 *   It will call \ref __RV_FSW to store floating point register into memory
 * * For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64):
 *   It will call \ref __RV_FSD to store floating point register into memory
 *
 * \attention
 * Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent
 */
#if __FPU_PRESENT == 1
#define __RV_FLOAD              __RV_FLW
#define __RV_FSTORE             __RV_FSW
/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */
typedef uint32_t rv_fpu_t;
#elif __FPU_PRESENT == 2
#define __RV_FLOAD              __RV_FLD
#define __RV_FSTORE             __RV_FSD
/** \brief Type of FPU register, depends on the FLEN defined in RISC-V */
typedef uint64_t rv_fpu_t;
#endif /* __FPU_PRESENT == 2 */

/**
 * \brief   Save FPU context into variables for interrupt nesting
 * \details
 * This macro is used to declare variables which are used for saving
 * FPU context, and it will store the nessary fpu registers into
 * these variables, it need to be used in a interrupt when in this
 * interrupt fpu registers are used.
 * \remarks
 * - It need to be used together with \ref RESTORE_FPU_CONTEXT
 * - Don't use variable names __fpu_context in your ISR code
 * - If you isr code will use fpu registers, and this interrupt is nested.
 * Then you can do it like this:
 * \code
 * void eclic_mtip_handler(void)
 * {
 *     // !!!Interrupt is enabled here!!!
 *     // !!!Higher priority interrupt could nest it!!!
 *
 *     // Necessary only when you need to use fpu registers
 *     // in this isr handler functions
 *     SAVE_FPU_CONTEXT();
 *
 *     // put you own interrupt handling code here
 *
 *     // pair of SAVE_FPU_CONTEXT()
 *     RESTORE_FPU_CONTEXT();
 * }
 * \endcode
 */
#define SAVE_FPU_CONTEXT()                                                  \
        rv_fpu_t __fpu_context[20];                                         \
        __RV_FSTORE(FREG(0),  __fpu_context, 0  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(1),  __fpu_context, 1  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(2),  __fpu_context, 2  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(3),  __fpu_context, 3  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(4),  __fpu_context, 4  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(5),  __fpu_context, 5  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(6),  __fpu_context, 6  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(7),  __fpu_context, 7  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(10), __fpu_context, 8  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(11), __fpu_context, 9  << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES);         \
        __RV_FSTORE(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES);

/**
 * \brief   Restore necessary fpu registers from variables for interrupt nesting
 * \details
 * This macro is used restore necessary fpu registers from pre-defined variables
 * in \ref SAVE_FPU_CONTEXT macro.
 * \remarks
 * - It need to be used together with \ref SAVE_FPU_CONTEXT
 */
#define RESTORE_FPU_CONTEXT()                                               \
        __RV_FLOAD(FREG(0),  __fpu_context, 0  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(1),  __fpu_context, 1  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(2),  __fpu_context, 2  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(3),  __fpu_context, 3  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(4),  __fpu_context, 4  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(5),  __fpu_context, 5  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(6),  __fpu_context, 6  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(7),  __fpu_context, 7  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(10), __fpu_context, 8  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(11), __fpu_context, 9  << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(12), __fpu_context, 10 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(13), __fpu_context, 11 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(14), __fpu_context, 12 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(15), __fpu_context, 13 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(16), __fpu_context, 14 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(17), __fpu_context, 15 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(28), __fpu_context, 16 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(29), __fpu_context, 17 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(30), __fpu_context, 18 << LOG_FPREGBYTES);          \
        __RV_FLOAD(FREG(31), __fpu_context, 19 << LOG_FPREGBYTES);
#else
#define SAVE_FPU_CONTEXT()
#define RESTORE_FPU_CONTEXT()
#endif /* __FPU_PRESENT > 0 */
/** @} */ /* End of Doxygen Group NMSIS_Core_FPU_Functions */

#ifdef __cplusplus
}
#endif
#endif /** __RISCV_EXT_FPU_H__  */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_pmp.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_PMP_H__
#define __CORE_FEATURE_PMP_H__
/*!
 * @file     core_feature_pmp.h
 * @brief    PMP feature API header file for Nuclei N/NX Core
 */
/*
 * PMP Feature Configuration Macro:
 * 1. __PMP_PRESENT:  Define whether Physical Memory Protection(PMP) is present or not
 *   * 0: Not present
 *   * 1: Present
 * 2. __PMP_ENTRY_NUM:  Define the number of PMP entries, only 8 or 16 is configurable.
 */
#ifdef __cplusplus
 extern "C" {
#endif

#if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1)
/* ===== PMP Operations ===== */
/**
 * \defgroup NMSIS_Core_PMP_Functions   PMP Functions
 * \ingroup  NMSIS_Core
 * \brief    Functions that related to the RISCV Phyiscal Memory Protection.
 * \details
 * Optional physical memory protection (PMP) unit provides per-hart machine-mode
 * control registers to allow physical memory access privileges (read, write, execute)
 * to be specified for each physical memory region.
 *
 * The PMP can supports region access control settings as small as four bytes.
 *
 *   @{
 */
#ifndef __PMP_ENTRY_NUM
/* numbers of PMP entries(__PMP_ENTRY_NUM) should be defined in  */
#error "__PMP_ENTRY_NUM is not defined, please check!"
#endif

/**
 * \brief   Get 8bit PMPxCFG Register by PMP entry index
 * \details Return the content of the PMPxCFG Register.
 * \param [in]    idx    PMP region index(0-15)
 * \return               PMPxCFG Register value
 */
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t idx)
{
    rv_csr_t pmpcfg = 0;

    if (idx >= __PMP_ENTRY_NUM) return 0;
#if __RISCV_XLEN == 32
    if (idx < 4) {
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
    } else if ((idx >=4) && (idx < 8)) {
        idx -= 4;
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG1);
    } else if ((idx >=8) && (idx < 12)) {
        idx -= 8;
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
    } else {
        idx -= 12;
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG3);
    }

    idx = idx << 3;
    return (uint8_t)((pmpcfg>>idx) & 0xFF);
#elif __RISCV_XLEN == 64
    if (idx < 8) {
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG0);
    } else {
        idx -= 8;
        pmpcfg = __RV_CSR_READ(CSR_PMPCFG2);
    }
    idx = idx << 3;
    return (uint8_t)((pmpcfg>>idx) & 0xFF);
#else
    // TODO Add RV128 Handling
    return 0;
#endif
}

/**
 * \brief   Set 8bit PMPxCFG by pmp entry index
 * \details Set the given pmpxcfg value to the PMPxCFG Register.
 * \param [in]    idx      PMPx region index(0-15)
 * \param [in]    pmpxcfg  PMPxCFG register value to set
 */
__STATIC_INLINE void __set_PMPxCFG(uint32_t idx, uint8_t pmpxcfg)
{
    rv_csr_t pmpcfgx = 0;
    if (idx >= __PMP_ENTRY_NUM) return;

#if __RISCV_XLEN == 32
    if (idx < 4) {
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx);
    } else if ((idx >=4) && (idx < 8)) {
        idx -= 4;
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG1);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfgx);
    } else if ((idx >=8) && (idx < 12)) {
        idx -= 8;
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx);
    } else {
        idx -= 12;
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG3);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFUL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfgx);
    }
#elif __RISCV_XLEN == 64
    if (idx < 8) {
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG0);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfgx);
    } else {
        idx -= 8;
        pmpcfgx = __RV_CSR_READ(CSR_PMPCFG2);
        idx = idx << 3;
        pmpcfgx = (pmpcfgx & ~(0xFFULL << idx)) | ((rv_csr_t)pmpxcfg << idx);
        __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfgx);
    }
#else
    // TODO Add RV128 Handling
#endif
}

/**
 * \brief   Get PMPCFGx Register by index
 * \details Return the content of the PMPCFGx Register.
 * \param [in]    idx    PMPCFG CSR index(0-3)
 * \return               PMPCFGx Register value
 * \remark
 * - For RV64, only idx = 0 and idx = 2 is allowed.
 *   pmpcfg0 and pmpcfg2 hold the configurations
 *   for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
 * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
 *   pmp0cfg–pmp15cfg for the 16 PMP entries
 */
__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t idx)
{
    switch (idx) {
        case 0: return __RV_CSR_READ(CSR_PMPCFG0);
        case 1: return __RV_CSR_READ(CSR_PMPCFG1);
        case 2: return __RV_CSR_READ(CSR_PMPCFG2);
        case 3: return __RV_CSR_READ(CSR_PMPCFG3);
        default: return 0;
    }
}

/**
 * \brief   Set PMPCFGx by index
 * \details Write the given value to the PMPCFGx Register.
 * \param [in]    idx      PMPCFG CSR index(0-3)
 * \param [in]    pmpcfg   PMPCFGx Register value to set
 * \remark
 * - For RV64, only idx = 0 and idx = 2 is allowed.
 *   pmpcfg0 and pmpcfg2 hold the configurations
 *   for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
 * - For RV32, pmpcfg0–pmpcfg3, hold the configurations
 *   pmp0cfg–pmp15cfg for the 16 PMP entries
 */
__STATIC_INLINE void __set_PMPCFGx(uint32_t idx, rv_csr_t pmpcfg)
{
    switch (idx) {
        case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break;
        case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break;
        case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break;
        case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break;
        default: return;
    }
}

/**
 * \brief   Get PMPADDRx Register by index
 * \details Return the content of the PMPADDRx Register.
 * \param [in]    idx    PMP region index(0-15)
 * \return               PMPADDRx Register value
 */
__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t idx)
{
    switch (idx) {
        case 0: return __RV_CSR_READ(CSR_PMPADDR0);
        case 1: return __RV_CSR_READ(CSR_PMPADDR1);
        case 2: return __RV_CSR_READ(CSR_PMPADDR2);
        case 3: return __RV_CSR_READ(CSR_PMPADDR3);
        case 4: return __RV_CSR_READ(CSR_PMPADDR4);
        case 5: return __RV_CSR_READ(CSR_PMPADDR5);
        case 6: return __RV_CSR_READ(CSR_PMPADDR6);
        case 7: return __RV_CSR_READ(CSR_PMPADDR7);
        case 8: return __RV_CSR_READ(CSR_PMPADDR8);
        case 9: return __RV_CSR_READ(CSR_PMPADDR9);
        case 10: return __RV_CSR_READ(CSR_PMPADDR10);
        case 11: return __RV_CSR_READ(CSR_PMPADDR11);
        case 12: return __RV_CSR_READ(CSR_PMPADDR12);
        case 13: return __RV_CSR_READ(CSR_PMPADDR13);
        case 14: return __RV_CSR_READ(CSR_PMPADDR14);
        case 15: return __RV_CSR_READ(CSR_PMPADDR15);
        default: return 0;
    }
}

/**
 * \brief   Set PMPADDRx by index
 * \details Write the given value to the PMPADDRx Register.
 * \param [in]    idx      PMP region index(0-15)
 * \param [in]    pmpaddr  PMPADDRx Register value to set
 */
__STATIC_INLINE void __set_PMPADDRx(uint32_t idx, rv_csr_t pmpaddr)
{
    switch (idx) {
        case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break;
        case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break;
        case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break;
        case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break;
        case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break;
        case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break;
        case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break;
        case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break;
        case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break;
        case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break;
        case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break;
        case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break;
        case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break;
        case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break;
        case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break;
        case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break;
        default: return;
    }
}
/** @} */ /* End of Doxygen Group NMSIS_Core_PMP_Functions */
#endif /* defined(__PMP_PRESENT) && (__PMP_PRESENT == 1) */

#ifdef __cplusplus
}
#endif
#endif /** __CORE_FEATURE_PMP_H__  */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/core_feature_timer.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_TIMER_H__
#define __CORE_FEATURE_TIMER_H__
/*!
 * @file     core_feature_timer.h
 * @brief    System Timer feature API header file for Nuclei N/NX Core
 */
/*
 * System Timer Feature Configuration Macro:
 * 1. __SYSTIMER_PRESENT:  Define whether Private System Timer is present or not.
 *   * 0: Not present
 *   * 1: Present
 * 2. __SYSTIMER_BASEADDR:  Define the base address of the System Timer.
 */
#ifdef __cplusplus
 extern "C" {
#endif

#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1)
/**
 * \defgroup NMSIS_Core_SysTimer_Registers     Register Define and Type Definitions Of System Timer
 * \ingroup NMSIS_Core_Registers
 * \brief   Type definitions and defines for system timer registers.
 *
 * @{
 */
/**
 * \brief  Structure type to access the System Timer (SysTimer).
 * \details
 * Structure definition to access the system timer(SysTimer).
 * \remarks
 * - MSFTRST register is introduced in Nuclei N Core version 1.3(\ref __NUCLEI_N_REV >= 0x0103)
 * - MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104)
 * - CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(\ref __NUCLEI_N_REV >= 0x0104)
 */
typedef struct {
    __IOM uint64_t MTIMER;                  /*!< Offset: 0x000 (R/W)  System Timer current value 64bits Register */
    __IOM uint64_t MTIMERCMP;               /*!< Offset: 0x008 (R/W)  System Timer compare Value 64bits Register */
    __IOM uint32_t RESERVED0[0x3F8];        /*!< Offset: 0x010 - 0xFEC Reserved */
    __IOM uint32_t MSFTRST;                 /*!< Offset: 0xFF0 (R/W)  System Timer Software Core Reset Register */
    __IOM uint32_t RESERVED1;               /*!< Offset: 0xFF4 Reserved */
    __IOM uint32_t MTIMECTL;                /*!< Offset: 0xFF8 (R/W)  System Timer Control Register, previously MSTOP register */
    __IOM uint32_t MSIP;                    /*!< Offset: 0xFFC (R/W)  System Timer SW interrupt Register */
} SysTimer_Type;

/* Timer Control / Status Register Definitions */
#define SysTimer_MTIMECTL_TIMESTOP_Pos      0U                                          /*!< SysTick Timer MTIMECTL: TIMESTOP bit Position */
#define SysTimer_MTIMECTL_TIMESTOP_Msk      (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos)     /*!< SysTick Timer MTIMECTL: TIMESTOP Mask */
#define SysTimer_MTIMECTL_CMPCLREN_Pos      1U                                          /*!< SysTick Timer MTIMECTL: CMPCLREN bit Position */
#define SysTimer_MTIMECTL_CMPCLREN_Msk      (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos)     /*!< SysTick Timer MTIMECTL: CMPCLREN Mask */
#define SysTimer_MTIMECTL_CLKSRC_Pos        2U                                          /*!< SysTick Timer MTIMECTL: CLKSRC bit Position */
#define SysTimer_MTIMECTL_CLKSRC_Msk        (1UL << SysTimer_MTIMECTL_CLKSRC_Pos)       /*!< SysTick Timer MTIMECTL: CLKSRC Mask */

#define SysTimer_MSIP_MSIP_Pos              0U                                          /*!< SysTick Timer MSIP: MSIP bit Position */
#define SysTimer_MSIP_MSIP_Msk              (1UL << SysTimer_MSIP_MSIP_Pos)             /*!< SysTick Timer MSIP: MSIP Mask */

#define SysTimer_MTIMER_Msk                 (0xFFFFFFFFFFFFFFFFULL)                     /*!< SysTick Timer MTIMER value Mask */
#define SysTimer_MTIMERCMP_Msk              (0xFFFFFFFFFFFFFFFFULL)                     /*!< SysTick Timer MTIMERCMP value Mask */
#define SysTimer_MTIMECTL_Msk               (0xFFFFFFFFUL)                              /*!< SysTick Timer MTIMECTL/MSTOP value Mask */
#define SysTimer_MSIP_Msk                   (0xFFFFFFFFUL)                              /*!< SysTick Timer MSIP   value Mask */
#define SysTimer_MSFTRST_Msk                (0xFFFFFFFFUL)                              /*!< SysTick Timer MSFTRST value Mask */

#define SysTimer_MSFRST_KEY                 (0x80000A5FUL)                              /*!< SysTick Timer Software Reset Request Key */

#ifndef __SYSTIMER_BASEADDR
/* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in  */
#error "__SYSTIMER_BASEADDR is not defined, please check!"
#endif
/* System Timer Memory mapping of Device  */
#define SysTimer_BASE                       __SYSTIMER_BASEADDR                         /*!< SysTick Base Address */
#define SysTimer                            ((SysTimer_Type *) SysTimer_BASE)           /*!< SysTick configuration struct */
/** @} */ /* end of group NMSIS_Core_SysTimer_Registers */

/* ##################################    SysTimer function  ############################################ */
/**
 * \defgroup NMSIS_Core_SysTimer SysTimer Functions
 * \brief    Functions that configure the Core System Timer.
 * @{
 */
/**
 * \brief  Set system timer load value
 * \details
 * This function set the system timer load value in MTIMER register.
 * \param [in]  value   value to set system timer MTIMER register.
 * \remarks
 * - Load value is 64bits wide.
 * - \ref SysTimer_GetLoadValue
 */
__STATIC_FORCEINLINE void SysTimer_SetLoadValue(uint64_t value)
{
    SysTimer->MTIMER = value;
}

/**
 * \brief  Get system timer load value
 * \details
 * This function get the system timer current value in MTIMER register.
 * \return  current value(64bit) of system timer MTIMER register.
 * \remarks
 * - Load value is 64bits wide.
 * - \ref SysTimer_SetLoadValue
 */
__STATIC_FORCEINLINE uint64_t SysTimer_GetLoadValue(void)
{
    return SysTimer->MTIMER;
}

/**
 * \brief  Set system timer compare value
 * \details
 * This function set the system Timer compare value in MTIMERCMP register.
 * \param [in]  value   compare value to set system timer MTIMERCMP register.
 * \remarks
 * - Compare value is 64bits wide.
 * - If compare value is larger than current value timer interrupt generate.
 * - Modify the load value or compare value less to clear the interrupt.
 * - \ref SysTimer_GetCompareValue
 */
__STATIC_FORCEINLINE void SysTimer_SetCompareValue(uint64_t value)
{
    SysTimer->MTIMERCMP = value;
}

/**
 * \brief  Get system timer compare value
 * \details
 * This function get the system timer compare value in MTIMERCMP register.
 * \return  compare value of system timer MTIMERCMP register.
 * \remarks
 * - Compare value is 64bits wide.
 * - \ref SysTimer_SetCompareValue
 */
__STATIC_FORCEINLINE uint64_t SysTimer_GetCompareValue(void)
{
    return SysTimer->MTIMERCMP;
}

/**
 * \brief  Enable system timer counter running
 * \details
 * Enable system timer counter running by clear
 * TIMESTOP bit in MTIMECTL register.
 */
__STATIC_FORCEINLINE void SysTimer_Start(void)
{
    SysTimer->MTIMECTL &= ~(SysTimer_MTIMECTL_TIMESTOP_Msk);
}

/**
 * \brief  Stop system timer counter running
 * \details
 * Stop system timer counter running by set
 * TIMESTOP bit in MTIMECTL register.
 */
__STATIC_FORCEINLINE void SysTimer_Stop(void)
{
    SysTimer->MTIMECTL |= SysTimer_MTIMECTL_TIMESTOP_Msk;
}

/**
 * \brief  Set system timer control value
 * \details
 * This function set the system timer MTIMECTL register value.
 * \param [in]  mctl    value to set MTIMECTL register
 * \remarks
 * - Bit TIMESTOP is used to start and stop timer.
 *   Clear TIMESTOP bit to 0 to start timer, otherwise to stop timer.
 * - Bit CMPCLREN is used to enable auto MTIMER clear to zero when MTIMER >= MTIMERCMP.
 *   Clear CMPCLREN bit to 0 to stop auto clear MTIMER feature, otherwise to enable it.
 * - Bit CLKSRC is used to select timer clock source.
 *   Clear CLKSRC bit to 0 to use *mtime_toggle_a*, otherwise use *core_clk_aon*
 * - \ref SysTimer_GetControlValue
 */
__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
{
    SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
}

/**
 * \brief  Get system timer control value
 * \details
 * This function get the system timer MTIMECTL register value.
 * \return  MTIMECTL register value
 * \remarks
 * - \ref SysTimer_SetControlValue
 */
__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
{
    return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
}

/**
 * \brief  Trigger or set software interrupt via system timer
 * \details
 * This function set the system timer MSIP bit in MSIP register.
 * \remarks
 * - Set system timer MSIP bit and generate a SW interrupt.
 * - \ref SysTimer_ClearSWIRQ
 * - \ref SysTimer_GetMsipValue
 */
__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
{
    SysTimer->MSIP |= SysTimer_MSIP_MSIP_Msk;
}

/**
 * \brief  Clear system timer software interrupt pending request
 * \details
 * This function clear the system timer MSIP bit in MSIP register.
 * \remarks
 * - Clear system timer MSIP bit in MSIP register to clear the software interrupt pending.
 * - \ref SysTimer_SetSWIRQ
 * - \ref SysTimer_GetMsipValue
 */
__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
{
    SysTimer->MSIP &= ~SysTimer_MSIP_MSIP_Msk;
}

/**
 * \brief  Get system timer MSIP register value
 * \details
 * This function get the system timer MSIP register value.
 * \return    Value of Timer MSIP register.
 * \remarks
 * - Bit0 is SW interrupt flag.
 *   Bit0 is 1 then SW interrupt set. Bit0 is 0 then SW interrupt clear.
 * - \ref SysTimer_SetSWIRQ
 * - \ref SysTimer_ClearSWIRQ
 */
__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
{
    return (uint32_t)(SysTimer->MSIP & SysTimer_MSIP_Msk);
}

/**
 * \brief  Set system timer MSIP register value
 * \details
 * This function set the system timer MSIP register value.
 * \param [in]  msip   value to set MSIP register
 */
__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
{
    SysTimer->MSIP = (msip & SysTimer_MSIP_Msk);
}

/**
 * \brief  Do software reset request
 * \details
 * This function will do software reset request through MTIMER
 * - Software need to write \ref SysTimer_MSFRST_KEY to generate software reset request
 * - The software request flag can be cleared by reset operation to clear
 * \remarks
 * - The software reset is sent to SoC, SoC need to generate reset signal and send back to Core
 * - This function will not return, it will do while(1) to wait the Core reset happened
 */
__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
{
    SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
    while(1);
}

#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) && defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
/**
 * \brief   System Tick Configuration
 * \details Initializes the System Timer and its non-vector interrupt, and starts the System Tick Timer.
 *
 *  In our default implementation, the timer counter will be set to zero, and it will start a timer compare non-vector interrupt
 *  when it matchs the ticks user set, during the timer interrupt user should reload the system tick using \ref SysTick_Reload function
 *  or similar function written by user, so it can produce period timer interrupt.
 * \param [in]  ticks  Number of ticks between two interrupts.
 * \return          0  Function succeeded.
 * \return          1  Function failed.
 * \remarks
 * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced,
 *   but we assume that the CMPCLREN bit is set to 0, so MTIMER register will not be
 *   auto cleared to 0 when MTIMER >= MTIMERCMP.
 * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the
 *   function \ref SysTick_Config is not included.
 * - In this case, the file .h must contain a vendor-specific implementation
 *   of this function.
 * - If user need this function to start a period timer interrupt, then in timer interrupt handler
 *   routine code, user should call \ref SysTick_Reload with ticks to reload the timer.
 * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0
 * \sa
 * - \ref SysTimer_SetCompareValue; SysTimer_SetLoadValue
 */
__STATIC_INLINE uint32_t SysTick_Config(uint64_t ticks)
{
    SysTimer_SetLoadValue(0);
    SysTimer_SetCompareValue(ticks);
    ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
    ECLIC_SetLevelIRQ(SysTimer_IRQn, 0);
    ECLIC_EnableIRQ(SysTimer_IRQn);
    return (0UL);
}

/**
 * \brief   System Tick Reload
 * \details Reload the System Timer Tick when the MTIMECMP reached TIME value
 *
 * \param [in]  ticks  Number of ticks between two interrupts.
 * \return          0  Function succeeded.
 * \return          1  Function failed.
 * \remarks
 * - For \ref __NUCLEI_N_REV >= 0x0104, the CMPCLREN bit in MTIMECTL is introduced,
 *   but for this \ref SysTick_Config function, we assume this CMPCLREN bit is set to 0,
 *   so in interrupt handler function, user still need to set the MTIMERCMP or MTIMER to reload
 *   the system tick, if vendor want to use this timer's auto clear feature, they can define
 *   \ref __Vendor_SysTickConfig to 1, and implement \ref SysTick_Config and \ref SysTick_Reload functions.
 * - When the variable \ref __Vendor_SysTickConfig is set to 1, then the
 *   function \ref SysTick_Reload is not included.
 * - In this case, the file .h must contain a vendor-specific implementation
 *   of this function.
 * - This function only available when __SYSTIMER_PRESENT == 1 and __ECLIC_PRESENT == 1 and __Vendor_SysTickConfig == 0
 * - Since the MTIMERCMP value might overflow, if overflowed, MTIMER will be set to 0, and MTIMERCMP set to ticks
 * \sa
 * - \ref SysTimer_SetCompareValue
 * - \ref SysTimer_SetLoadValue
 */
__STATIC_FORCEINLINE uint32_t SysTick_Reload(uint64_t ticks)
{
    uint64_t cur_ticks = SysTimer->MTIMER;
    uint64_t reload_ticks = ticks + cur_ticks;

    if (__USUALLY(reload_ticks > cur_ticks)) {
        SysTimer->MTIMERCMP = reload_ticks;
    } else {
        /* When added the ticks value, then the MTIMERCMP < TIMER,
         * which means the MTIMERCMP is overflowed,
         * so we need to reset the counter to zero */
        SysTimer->MTIMER = 0;
        SysTimer->MTIMERCMP = ticks;
    }

    return (0UL);
}

#endif /* defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) */
/** @} */ /* End of Doxygen Group NMSIS_Core_SysTimer */

#endif /* defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) */

#ifdef __cplusplus
}
#endif
#endif /** __CORE_FEATURE_TIMER_H__  */



================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_compiler.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __NMSIS_COMPILER_H
#define __NMSIS_COMPILER_H

#include 

/*!
 * @file     nmsis_compiler.h
 * @brief    NMSIS compiler generic header file
 */
#if defined ( __GNUC__ )
  /** GNU GCC Compiler */
  #include "nmsis_gcc.h"
#else
  #error Unknown compiler.
#endif


#endif /* __NMSIS_COMPILER_H */



================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_core.h
================================================
/*
 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
 * -- Adaptable modifications made for Nuclei Processors. --
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __NMSIS_CORE_H__
#define __NMSIS_CORE_H__

#include 

#ifdef __cplusplus
extern "C" {
#endif

#include "nmsis_version.h"

/**
 * \ingroup NMSIS_Core_VersionControl
 * @{
 */
/* The following enum __NUCLEI_N_REV/__NUCLEI_NX_REV definition in this file
 * is only used for doxygen documentation generation,
 * The .h is the real file to define it by vendor
 */
#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
/**
 * \brief Nuclei N class core revision number
 * \details
 * Reversion number format: [15:8] revision number, [7:0] patch number
 * \attention
 * This define is exclusive with \ref __NUCLEI_NX_REV
 */
#define __NUCLEI_N_REV (0x0104)
/**
 * \brief Nuclei NX class core revision number
 * \details
 * Reversion number format: [15:8] revision number, [7:0] patch number
 * \attention
 * This define is exclusive with \ref __NUCLEI_N_REV
 */
#define __NUCLEI_NX_REV (0x0100)
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
/** @} */ /* End of Group NMSIS_Core_VersionControl */

#include "nmsis_compiler.h" /* NMSIS compiler specific defines */

/* === Include Nuclei Core Related Headers === */
/* Include core base feature header file */
#include "core_feature_base.h"

#ifndef __NMSIS_GENERIC
/* Include core eclic feature header file */
#include "core_feature_eclic.h"
/* Include core systimer feature header file */
#include "core_feature_timer.h"
#endif

/* Include core fpu feature header file */
#include "core_feature_fpu.h"
/* Include core dsp feature header file */
#include "core_feature_dsp.h"
/* Include core pmp feature header file */
#include "core_feature_pmp.h"
/* Include core cache feature header file */
#include "core_feature_cache.h"

/* Include compatiable functions header file */
#include "core_compatiable.h"

#ifdef __cplusplus
}
#endif
#endif /* __NMSIS_CORE_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_gcc.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef __NMSIS_GCC_H__
#define __NMSIS_GCC_H__
/*!
 * @file     nmsis_gcc.h
 * @brief    NMSIS compiler GCC header file
 */
#include 
#include "riscv_encoding.h"

#ifdef __cplusplus
extern "C" {
#endif

/* #########################  Startup and Lowlevel Init  ######################## */
/**
 * \defgroup NMSIS_Core_CompilerControl    Compiler Control
 * \ingroup  NMSIS_Core
 * \brief    Compiler agnostic \#define symbols for generic c/c++ source code
 * \details
 *
 * The NMSIS-Core provides the header file nmsis_compiler.h with consistent \#define symbols for generate C or C++ source files that should be compiler agnostic.
 * Each NMSIS compliant compiler should support the functionality described in this section.
 *
 * The header file nmsis_compiler.h is also included by each Device Header File  so that these definitions are available.
 *   @{
 */
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"

/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif

/* NMSIS compiler specific defines */
/** \brief Pass information from the compiler to the assembler. */
#ifndef __ASM
#define __ASM __asm
#endif

/** \brief Recommend that function should be inlined by the compiler. */
#ifndef __INLINE
#define __INLINE inline
#endif

/** \brief Define a static function that may be inlined by the compiler. */
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif

/** \brief Define a static function that should be always inlined by the compiler. */
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif

/** \brief Inform the compiler that a function does not return. */
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif

/** \brief Inform that a variable shall be retained in executable image. */
#ifndef __USED
#define __USED __attribute__((used))
#endif

/** \brief restrict pointer qualifier to enable additional optimizations. */
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif

/** \brief specified the vector size of the variable, measured in bytes */
#ifndef __VECTOR_SIZE
#define __VECTOR_SIZE(x) __attribute__((vector_size(x)))
#endif

/** \brief Request smallest possible alignment. */
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif

/** \brief Request smallest possible alignment for a structure. */
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif

/** \brief Request smallest possible alignment for a union. */
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif

#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t write access */
__PACKED_STRUCT T_UINT16_WRITE
{
    uint16_t v;
};
#pragma GCC diagnostic pop
/** \brief Pointer for unaligned write of a uint16_t variable. */
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif

#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint16_t read access */
__PACKED_STRUCT T_UINT16_READ
{
    uint16_t v;
};
#pragma GCC diagnostic pop
/** \brief Pointer for unaligned read of a uint16_t variable. */
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif

#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t write access */
__PACKED_STRUCT T_UINT32_WRITE
{
    uint32_t v;
};
#pragma GCC diagnostic pop
/** \brief Pointer for unaligned write of a uint32_t variable. */
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif

#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
/** \brief Packed struct for unaligned uint32_t read access */
__PACKED_STRUCT T_UINT32_READ
{
    uint32_t v;
};
#pragma GCC diagnostic pop
/** \brief Pointer for unaligned read of a uint32_t variable. */
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif

/** \brief Minimum `x` bytes alignment for a variable. */
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif

/** \brief restrict pointer qualifier to enable additional optimizations. */
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif

/** \brief Barrier to prevent compiler from reordering instructions. */
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("" :: \
                                                : "memory")
#endif

/** \brief provide the compiler with branch prediction information, the branch is usually true */
#ifndef __USUALLY
#define __USUALLY(exp) __builtin_expect((exp), 1)
#endif

/** \brief provide the compiler with branch prediction information, the branch is rarely true */
#ifndef __RARELY
#define __RARELY(exp) __builtin_expect((exp), 0)
#endif

/** \brief Use this attribute to indicate that the specified function is an interrupt handler. */
#ifndef __INTERRUPT
#define __INTERRUPT __attribute__((interrupt))
#endif

/** @} */ /* End of Doxygen Group NMSIS_Core_CompilerControl */

/* IO definitions (access restrictions to peripheral registers) */
/**
 * \defgroup NMSIS_Core_PeriphAccess     Peripheral Access
 * \brief  Naming conventions and optional features for accessing peripherals.
 *
 * The section below describes the naming conventions, requirements, and optional features
 * for accessing device specific peripherals.
 * Most of the rules also apply to the core peripherals.
 *
 * The **Device Header File ** contains typically these definition
 * and also includes the core specific header files.
 *
 * @{
 */
/** \brief Defines 'read only' permissions */
#ifdef __cplusplus
#define __I volatile
#else
#define __I volatile const
#endif
/** \brief Defines 'write only' permissions */
#define __O volatile
/** \brief Defines 'read / write' permissions */
#define __IO volatile

/* following defines should be used for structure members */
/** \brief Defines 'read only' structure member permissions */
#define __IM volatile const
/** \brief Defines 'write only' structure member permissions */
#define __OM volatile
/** \brief Defines 'read/write' structure member permissions */
#define __IOM volatile

/**
 * \brief   Mask and shift a bit field value for use in a register bit range.
 * \details The macro \ref _VAL2FLD uses the #define's _Pos and _Msk of the related bit
 * field to shift bit-field values for assigning to a register.
 *
 * **Example**:
 * \code
 * ECLIC->CFG = _VAL2FLD(CLIC_CLICCFG_NLBIT, 3);
 * \endcode
 * \param[in] field  Name of the register bit field.
 * \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
 * \return           Masked and shifted value.
 */
#define _VAL2FLD(field, value) (((uint32_t)(value) << field##_Pos) & field##_Msk)

/**
 * \brief   Mask and shift a register value to extract a bit filed value.
 * \details The macro \ref _FLD2VAL uses the #define's _Pos and _Msk of the related bit
 * field to extract the value of a bit field from a register.
 *
 * **Example**:
 * \code
 * nlbits = _FLD2VAL(CLIC_CLICCFG_NLBIT, ECLIC->CFG);
 * \endcode
 * \param[in] field  Name of the register bit field.
 * \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
 * \return           Masked and shifted bit field value.
 */
#define _FLD2VAL(field, value) (((uint32_t)(value)&field##_Msk) >> field##_Pos)

    /** @} */ /* end of group NMSIS_Core_PeriphAccess */

#ifdef __cplusplus
}
#endif
#endif /* __NMSIS_GCC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/nmsis_version.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __NMSIS_VERSION_H
#define __NMSIS_VERSION_H

/**
 * \defgroup NMSIS_Core_VersionControl    Version Control
 * \ingroup  NMSIS_Core
 * \brief    Version \#define symbols for NMSIS release specific C/C++ source code
 * \details
 *
 * We followed the [semantic versioning 2.0.0](https://semver.org/) to control NMSIS version.
 * The version format is **MAJOR.MINOR.PATCH**, increment the:
 * 1. MAJOR version when you make incompatible API changes,
 * 2. MINOR version when you add functionality in a backwards compatible manner, and
 * 3. PATCH version when you make backwards compatible bug fixes.
 *
 * The header file `nmsis_version.h` is included by each core header so that these definitions are available.
 *
 * **Example Usage for NMSIS Version Check**:
 * \code
 *   #if defined(__NMSIS_VERSION) && (__NMSIS_VERSION >= 0x00010105)
 *      #warning "Yes, we have NMSIS 1.1.5 or later"
 *   #else
 *      #error "We need NMSIS 1.1.5 or later!"
 *   #endif
 * \endcode
 *
 * @{
 */

/*!
 * \file     nmsis_version.h
 * \brief    NMSIS Version definitions
 **/

/**
 * \brief   Represent the NMSIS major version
 * \details
 * The NMSIS major version can be used to
 * differentiate between NMSIS major releases.
 * */
#define __NMSIS_VERSION_MAJOR            (1U)

/**
 * \brief   Represent the NMSIS minor version
 * \details
 * The NMSIS minor version can be used to
 * query a NMSIS release update including new features.
 *
 **/
#define __NMSIS_VERSION_MINOR            (0U)

/**
 * \brief   Represent the NMSIS patch version
 * \details
 * The NMSIS patch version can be used to
 * show bug fixes in this package.
 **/
#define __NMSIS_VERSION_PATCH            (1U)
/**
 * \brief   Represent the NMSIS Version
 * \details
 * NMSIS Version format: **MAJOR.MINOR.PATCH**
 * * MAJOR: \ref __NMSIS_VERSION_MAJOR, stored in `bits [31:16]` of \ref __NMSIS_VERSION
 * * MINOR: \ref __NMSIS_VERSION_MINOR, stored in `bits [15:8]` of \ref __NMSIS_VERSION
 * * PATCH: \ref __NMSIS_VERSION_PATCH, stored in `bits [7:0]` of \ref __NMSIS_VERSION
 **/
#define __NMSIS_VERSION                  ((__NMSIS_VERSION_MAJOR << 16U) | (__NMSIS_VERSION_MINOR << 8) | __NMSIS_VERSION_PATCH)

/** @} */ /* End of Doxygen Group NMSIS_Core_VersionControl */
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_bits.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __RISCV_BITS_H__
#define __RISCV_BITS_H__

#ifdef __cplusplus
 extern "C" {
#endif

#if __riscv_xlen == 64
# define SLL32                  sllw
# define STORE                  sd
# define LOAD                   ld
# define LWU                    lwu
# define LOG_REGBYTES           3
#else
# define SLL32                  sll
# define STORE                  sw
# define LOAD                   lw
# define LWU                    lw
# define LOG_REGBYTES           2
#endif /* __riscv_xlen */

#define REGBYTES (1 << LOG_REGBYTES)

#if defined(__riscv_flen)
#if __riscv_flen == 64
# define FPSTORE                fsd
# define FPLOAD                 fld
# define LOG_FPREGBYTES         3
#else
# define FPSTORE                fsw
# define FPLOAD                 flw
# define LOG_FPREGBYTES         2
#endif /* __riscv_flen == 64 */
#define FPREGBYTES              (1 << LOG_FPREGBYTES)
#endif /* __riscv_flen */

#define __rv_likely(x)          __builtin_expect((x), 1)
#define __rv_unlikely(x)        __builtin_expect((x), 0)

#define __RV_ROUNDUP(a, b)      ((((a)-1)/(b)+1)*(b))
#define __RV_ROUNDDOWN(a, b)    ((a)/(b)*(b))

#define __RV_MAX(a, b)          ((a) > (b) ? (a) : (b))
#define __RV_MIN(a, b)          ((a) < (b) ? (a) : (b))
#define __RV_CLAMP(a, lo, hi)   MIN(MAX(a, lo), hi)

#define __RV_EXTRACT_FIELD(val, which)                  (((val) & (which)) / ((which) & ~((which)-1)))
#define __RV_INSERT_FIELD(val, which, fieldval)         (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))

#ifdef __ASSEMBLY__
#define _AC(X,Y)                X
#define _AT(T,X)                X
#else
#define __AC(X,Y)               (X##Y)
#define _AC(X,Y)                __AC(X,Y)
#define _AT(T,X)                ((T)(X))
#endif /* __ASSEMBLY__ */

#define _UL(x)                  (_AC(x, UL))
#define _ULL(x)                 (_AC(x, ULL))

#define _BITUL(x)               (_UL(1) << (x))
#define _BITULL(x)              (_ULL(1) << (x))

#define UL(x)                   (_UL(x))
#define ULL(x)                  (_ULL(x))

#define STR(x)                  XSTR(x)
#define XSTR(x)                 #x
#define __STR(s)                #s
#define STRINGIFY(s)            __STR(s)

#ifdef __cplusplus
}
#endif

#endif /** __RISCV_BITS_H__  */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/components/nmsis/core/inc/riscv_encoding.h
================================================
/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __RISCV_ENCODING_H__
#define __RISCV_ENCODING_H__

#include "riscv_bits.h"
#ifdef __cplusplus
 extern "C" {
#endif
/**
 * \defgroup NMSIS_Core_CSR_Encoding    Core CSR Encodings
 * \ingroup  NMSIS_Core
 * \brief    NMSIS Core CSR Encodings
 * \details
 *
 * The following macros are used for CSR encodings
 *   @{
 */
/* === Standard CSR bit mask === */
#define MSTATUS_UIE         0x00000001
#define MSTATUS_SIE         0x00000002
#define MSTATUS_HIE         0x00000004
#define MSTATUS_MIE         0x00000008
#define MSTATUS_UPIE        0x00000010
#define MSTATUS_SPIE        0x00000020
#define MSTATUS_HPIE        0x00000040
#define MSTATUS_MPIE        0x00000080
#define MSTATUS_SPP         0x00000100
#define MSTATUS_MPP         0x00001800
#define MSTATUS_FS          0x00006000
#define MSTATUS_XS          0x00018000
#define MSTATUS_MPRV        0x00020000
#define MSTATUS_PUM         0x00040000
#define MSTATUS_MXR         0x00080000
#define MSTATUS_VM          0x1F000000
#define MSTATUS32_SD        0x80000000
#define MSTATUS64_SD        0x8000000000000000

#define MSTATUS_FS_INITIAL  0x00002000
#define MSTATUS_FS_CLEAN    0x00004000
#define MSTATUS_FS_DIRTY    0x00006000

#define SSTATUS_UIE         0x00000001
#define SSTATUS_SIE         0x00000002
#define SSTATUS_UPIE        0x00000010
#define SSTATUS_SPIE        0x00000020
#define SSTATUS_SPP         0x00000100
#define SSTATUS_FS          0x00006000
#define SSTATUS_XS          0x00018000
#define SSTATUS_PUM         0x00040000
#define SSTATUS32_SD        0x80000000
#define SSTATUS64_SD        0x8000000000000000

#define CSR_MCACHE_CTL_IE   0x00000001
#define CSR_MCACHE_CTL_DE   0x00010000

#define DCSR_XDEBUGVER      (3U<<30)
#define DCSR_NDRESET        (1<<29)
#define DCSR_FULLRESET      (1<<28)
#define DCSR_EBREAKM        (1<<15)
#define DCSR_EBREAKH        (1<<14)
#define DCSR_EBREAKS        (1<<13)
#define DCSR_EBREAKU        (1<<12)
#define DCSR_STOPCYCLE      (1<<10)
#define DCSR_STOPTIME       (1<<9)
#define DCSR_CAUSE          (7<<6)
#define DCSR_DEBUGINT       (1<<5)
#define DCSR_HALT           (1<<3)
#define DCSR_STEP           (1<<2)
#define DCSR_PRV            (3<<0)

#define DCSR_CAUSE_NONE     0
#define DCSR_CAUSE_SWBP     1
#define DCSR_CAUSE_HWBP     2
#define DCSR_CAUSE_DEBUGINT 3
#define DCSR_CAUSE_STEP     4
#define DCSR_CAUSE_HALT     5

#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))

#define MCONTROL_SELECT     (1<<19)
#define MCONTROL_TIMING     (1<<18)
#define MCONTROL_ACTION     (0x3f<<12)
#define MCONTROL_CHAIN      (1<<11)
#define MCONTROL_MATCH      (0xf<<7)
#define MCONTROL_M          (1<<6)
#define MCONTROL_H          (1<<5)
#define MCONTROL_S          (1<<4)
#define MCONTROL_U          (1<<3)
#define MCONTROL_EXECUTE    (1<<2)
#define MCONTROL_STORE      (1<<1)
#define MCONTROL_LOAD       (1<<0)

#define MCONTROL_TYPE_NONE      0
#define MCONTROL_TYPE_MATCH     2

#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
#define MCONTROL_ACTION_DEBUG_MODE        1
#define MCONTROL_ACTION_TRACE_START       2
#define MCONTROL_ACTION_TRACE_STOP        3
#define MCONTROL_ACTION_TRACE_EMIT        4

#define MCONTROL_MATCH_EQUAL     0
#define MCONTROL_MATCH_NAPOT     1
#define MCONTROL_MATCH_GE        2
#define MCONTROL_MATCH_LT        3
#define MCONTROL_MATCH_MASK_LOW  4
#define MCONTROL_MATCH_MASK_HIGH 5

#define MIP_SSIP            (1 << IRQ_S_SOFT)
#define MIP_HSIP            (1 << IRQ_H_SOFT)
#define MIP_MSIP            (1 << IRQ_M_SOFT)
#define MIP_STIP            (1 << IRQ_S_TIMER)
#define MIP_HTIP            (1 << IRQ_H_TIMER)
#define MIP_MTIP            (1 << IRQ_M_TIMER)
#define MIP_SEIP            (1 << IRQ_S_EXT)
#define MIP_HEIP            (1 << IRQ_H_EXT)
#define MIP_MEIP            (1 << IRQ_M_EXT)

#define MIE_SSIE            MIP_SSIP
#define MIE_HSIE            MIP_HSIP
#define MIE_MSIE            MIP_MSIP
#define MIE_STIE            MIP_STIP
#define MIE_HTIE            MIP_HTIP
#define MIE_MTIE            MIP_MTIP
#define MIE_SEIE            MIP_SEIP
#define MIE_HEIE            MIP_HEIP
#define MIE_MEIE            MIP_MEIP

/* === P-ext CSR bit mask === */

#define UCODE_OV            (0x1)

/* === Nuclei custom CSR bit mask === */

#define WFE_WFE                     (0x1)
#define TXEVT_TXEVT                 (0x1)
#define SLEEPVALUE_SLEEPVALUE       (0x1)

#define MCOUNTINHIBIT_IR            (1<<2)
#define MCOUNTINHIBIT_CY            (1<<0)

#define MILM_CTL_ILM_BPA            (((1ULL<<((__riscv_xlen)-10))-1)<<10)
#define MILM_CTL_ILM_RWECC          (1<<3)
#define MILM_CTL_ILM_ECC_EXCP_EN    (1<<2)
#define MILM_CTL_ILM_ECC_EN         (1<<1)
#define MILM_CTL_ILM_EN             (1<<0)

#define MDLM_CTL_DLM_BPA            (((1ULL<<((__riscv_xlen)-10))-1)<<10)
#define MDLM_CTL_DLM_RWECC          (1<<3)
#define MDLM_CTL_DLM_ECC_EXCP_EN    (1<<2)
#define MDLM_CTL_DLM_ECC_EN         (1<<1)
#define MDLM_CTL_DLM_EN             (1<<0)

#define MSUBM_PTYP                  (0x3<<8)
#define MSUBM_TYP                   (0x3<<6)

#define MDCAUSE_MDCAUSE             (0x3)

#define MMISC_CTL_NMI_CAUSE_FFF     (1<<9)
#define MMISC_CTL_MISALIGN          (1<<6)
#define MMISC_CTL_BPU               (1<<3)

#define MCACHE_CTL_IC_EN            (1<<0)
#define MCACHE_CTL_IC_SCPD_MOD      (1<<1)
#define MCACHE_CTL_IC_ECC_EN        (1<<2)
#define MCACHE_CTL_IC_ECC_EXCP_EN   (1<<3)
#define MCACHE_CTL_IC_RWTECC        (1<<4)
#define MCACHE_CTL_IC_RWDECC        (1<<5)
#define MCACHE_CTL_DC_EN            (1<<16)
#define MCACHE_CTL_DC_ECC_EN        (1<<17)
#define MCACHE_CTL_DC_ECC_EXCP_EN   (1<<18)
#define MCACHE_CTL_DC_RWTECC        (1<<19)
#define MCACHE_CTL_DC_RWDECC        (1<<20)

#define MTVT2_MTVT2EN               (1<<0)
#define MTVT2_COMMON_CODE_ENTRY     (((1ULL<<((__riscv_xlen)-2))-1)<<2)

#define MCFG_INFO_TEE               (1<<0)
#define MCFG_INFO_ECC               (1<<1)
#define MCFG_INFO_CLIC              (1<<2)
#define MCFG_INFO_PLIC              (1<<3)
#define MCFG_INFO_FIO               (1<<4)
#define MCFG_INFO_PPI               (1<<5)
#define MCFG_INFO_NICE              (1<<6)
#define MCFG_INFO_ILM               (1<<7)
#define MCFG_INFO_DLM               (1<<8)
#define MCFG_INFO_ICACHE            (1<<9)
#define MCFG_INFO_DCACHE            (1<<10)

#define MICFG_IC_SET                (0xF<<0)
#define MICFG_IC_WAY                (0x7<<4)
#define MICFG_IC_LSIZE              (0x7<<7)
#define MICFG_IC_ECC                (0x1<<10)
#define MICFG_ILM_SIZE              (0x1F<<16)
#define MICFG_ILM_XONLY             (0x1<<21)
#define MICFG_ILM_ECC               (0x1<<22)

#define MDCFG_DC_SET                (0xF<<0)
#define MDCFG_DC_WAY                (0x7<<4)
#define MDCFG_DC_LSIZE              (0x7<<7)
#define MDCFG_DC_ECC                (0x1<<10)
#define MDCFG_DLM_SIZE              (0x1F<<16)
#define MDCFG_DLM_ECC               (0x1<<21)

#define MPPICFG_INFO_PPI_SIZE       (0x1F<<1)
#define MPPICFG_INFO_PPI_BPA        (((1ULL<<((__riscv_xlen)-10))-1)<<10)

#define MFIOCFG_INFO_FIO_SIZE       (0x1F<<1)
#define MFIOCFG_INFO_FIO_BPA        (((1ULL<<((__riscv_xlen)-10))-1)<<10)

#define MECC_LOCK_ECC_LOCK          (0x1)

#define MECC_CODE_CODE              (0x1FF)
#define MECC_CODE_RAMID             (0x1F<<16)
#define MECC_CODE_SRAMID            (0x1F<<24)

#define CCM_SUEN_SUEN               (0x1<<0)
#define CCM_DATA_DATA               (0x7<<0)
#define CCM_COMMAND_COMMAND         (0x1F<<0)

#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP

#define PRV_U 0
#define PRV_S 1
#define PRV_H 2
#define PRV_M 3

#define VM_MBARE 0
#define VM_MBB   1
#define VM_MBBID 2
#define VM_SV32  8
#define VM_SV39  9
#define VM_SV48  10

#define IRQ_S_SOFT   1
#define IRQ_H_SOFT   2
#define IRQ_M_SOFT   3
#define IRQ_S_TIMER  5
#define IRQ_H_TIMER  6
#define IRQ_M_TIMER  7
#define IRQ_S_EXT    9
#define IRQ_H_EXT    10
#define IRQ_M_EXT    11
#define IRQ_COP      12
#define IRQ_HOST     13


/* === FPU FRM Rounding Mode === */
/** FPU Round to Nearest, ties to Even*/
#define FRM_RNDMODE_RNE     0x0
/** FPU Round Towards Zero */
#define FRM_RNDMODE_RTZ     0x1
/** FPU Round Down (towards -inf) */
#define FRM_RNDMODE_RDN     0x2
/** FPU Round Up (towards +inf) */
#define FRM_RNDMODE_RUP     0x3
/** FPU Round to nearest, ties to Max Magnitude */
#define FRM_RNDMODE_RMM     0x4
/**
 * In instruction's rm, selects dynamic rounding mode.
 * In Rounding Mode register, Invalid */
#define FRM_RNDMODE_DYN     0x7

/* === FPU FFLAGS Accrued Exceptions === */
/** FPU Inexact */
#define FFLAGS_AE_NX        (1<<0)
/** FPU Underflow */
#define FFLAGS_AE_UF        (1<<1)
/** FPU Overflow */
#define FFLAGS_AE_OF        (1<<2)
/** FPU Divide by Zero */
#define FFLAGS_AE_DZ        (1<<3)
/** FPU Invalid Operation */
#define FFLAGS_AE_NV        (1<<4)

/** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
#define FREG(idx)           f##idx


/* === PMP CFG Bits === */
#define PMP_R                0x01
#define PMP_W                0x02
#define PMP_X                0x04
#define PMP_A                0x18
#define PMP_A_TOR            0x08
#define PMP_A_NA4            0x10
#define PMP_A_NAPOT          0x18
#define PMP_L                0x80

#define PMP_SHIFT            2
#define PMP_COUNT            16

// page table entry (PTE) fields
#define PTE_V     0x001 // Valid
#define PTE_R     0x002 // Read
#define PTE_W     0x004 // Write
#define PTE_X     0x008 // Execute
#define PTE_U     0x010 // User
#define PTE_G     0x020 // Global
#define PTE_A     0x040 // Accessed
#define PTE_D     0x080 // Dirty
#define PTE_SOFT  0x300 // Reserved for Software

#define PTE_PPN_SHIFT 10

#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

#ifdef __riscv

#ifdef __riscv64
# define MSTATUS_SD MSTATUS64_SD
# define SSTATUS_SD SSTATUS64_SD
# define RISCV_PGLEVEL_BITS 9
#else
# define MSTATUS_SD MSTATUS32_SD
# define SSTATUS_SD SSTATUS32_SD
# define RISCV_PGLEVEL_BITS 10
#endif /* __riscv64 */

#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)

#endif /* __riscv */

/**
 * \defgroup NMSIS_Core_CSR_Registers    Core CSR Registers
 * \ingroup  NMSIS_Core
 * \brief    NMSIS Core CSR Register Definitions
 * \details
 *
 * The following macros are used for CSR Register Defintions.
 *   @{
 */
/* === Standard RISC-V CSR Registers === */
#define CSR_USTATUS 0x0
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
#define CSR_FCSR 0x3
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_HPMCOUNTER3 0xc03
#define CSR_HPMCOUNTER4 0xc04
#define CSR_HPMCOUNTER5 0xc05
#define CSR_HPMCOUNTER6 0xc06
#define CSR_HPMCOUNTER7 0xc07
#define CSR_HPMCOUNTER8 0xc08
#define CSR_HPMCOUNTER9 0xc09
#define CSR_HPMCOUNTER10 0xc0a
#define CSR_HPMCOUNTER11 0xc0b
#define CSR_HPMCOUNTER12 0xc0c
#define CSR_HPMCOUNTER13 0xc0d
#define CSR_HPMCOUNTER14 0xc0e
#define CSR_HPMCOUNTER15 0xc0f
#define CSR_HPMCOUNTER16 0xc10
#define CSR_HPMCOUNTER17 0xc11
#define CSR_HPMCOUNTER18 0xc12
#define CSR_HPMCOUNTER19 0xc13
#define CSR_HPMCOUNTER20 0xc14
#define CSR_HPMCOUNTER21 0xc15
#define CSR_HPMCOUNTER22 0xc16
#define CSR_HPMCOUNTER23 0xc17
#define CSR_HPMCOUNTER24 0xc18
#define CSR_HPMCOUNTER25 0xc19
#define CSR_HPMCOUNTER26 0xc1a
#define CSR_HPMCOUNTER27 0xc1b
#define CSR_HPMCOUNTER28 0xc1c
#define CSR_HPMCOUNTER29 0xc1d
#define CSR_HPMCOUNTER30 0xc1e
#define CSR_HPMCOUNTER31 0xc1f
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
#define CSR_SBADADDR 0x143
#define CSR_SIP 0x144
#define CSR_SPTBR 0x180
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MBADADDR 0x343
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
#define CSR_PMPCFG3 0x3a3
#define CSR_PMPADDR0 0x3b0
#define CSR_PMPADDR1 0x3b1
#define CSR_PMPADDR2 0x3b2
#define CSR_PMPADDR3 0x3b3
#define CSR_PMPADDR4 0x3b4
#define CSR_PMPADDR5 0x3b5
#define CSR_PMPADDR6 0x3b6
#define CSR_PMPADDR7 0x3b7
#define CSR_PMPADDR8 0x3b8
#define CSR_PMPADDR9 0x3b9
#define CSR_PMPADDR10 0x3ba
#define CSR_PMPADDR11 0x3bb
#define CSR_PMPADDR12 0x3bc
#define CSR_PMPADDR13 0x3bd
#define CSR_PMPADDR14 0x3be
#define CSR_PMPADDR15 0x3bf
#define CSR_TSELECT 0x7a0
#define CSR_TDATA1 0x7a1
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH 0x7b2
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
#define CSR_MHPMCOUNTER5 0xb05
#define CSR_MHPMCOUNTER6 0xb06
#define CSR_MHPMCOUNTER7 0xb07
#define CSR_MHPMCOUNTER8 0xb08
#define CSR_MHPMCOUNTER9 0xb09
#define CSR_MHPMCOUNTER10 0xb0a
#define CSR_MHPMCOUNTER11 0xb0b
#define CSR_MHPMCOUNTER12 0xb0c
#define CSR_MHPMCOUNTER13 0xb0d
#define CSR_MHPMCOUNTER14 0xb0e
#define CSR_MHPMCOUNTER15 0xb0f
#define CSR_MHPMCOUNTER16 0xb10
#define CSR_MHPMCOUNTER17 0xb11
#define CSR_MHPMCOUNTER18 0xb12
#define CSR_MHPMCOUNTER19 0xb13
#define CSR_MHPMCOUNTER20 0xb14
#define CSR_MHPMCOUNTER21 0xb15
#define CSR_MHPMCOUNTER22 0xb16
#define CSR_MHPMCOUNTER23 0xb17
#define CSR_MHPMCOUNTER24 0xb18
#define CSR_MHPMCOUNTER25 0xb19
#define CSR_MHPMCOUNTER26 0xb1a
#define CSR_MHPMCOUNTER27 0xb1b
#define CSR_MHPMCOUNTER28 0xb1c
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
#define CSR_MHPMEVENT6 0x326
#define CSR_MHPMEVENT7 0x327
#define CSR_MHPMEVENT8 0x328
#define CSR_MHPMEVENT9 0x329
#define CSR_MHPMEVENT10 0x32a
#define CSR_MHPMEVENT11 0x32b
#define CSR_MHPMEVENT12 0x32c
#define CSR_MHPMEVENT13 0x32d
#define CSR_MHPMEVENT14 0x32e
#define CSR_MHPMEVENT15 0x32f
#define CSR_MHPMEVENT16 0x330
#define CSR_MHPMEVENT17 0x331
#define CSR_MHPMEVENT18 0x332
#define CSR_MHPMEVENT19 0x333
#define CSR_MHPMEVENT20 0x334
#define CSR_MHPMEVENT21 0x335
#define CSR_MHPMEVENT22 0x336
#define CSR_MHPMEVENT23 0x337
#define CSR_MHPMEVENT24 0x338
#define CSR_MHPMEVENT25 0x339
#define CSR_MHPMEVENT26 0x33a
#define CSR_MHPMEVENT27 0x33b
#define CSR_MHPMEVENT28 0x33c
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
#define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_HPMCOUNTER3H 0xc83
#define CSR_HPMCOUNTER4H 0xc84
#define CSR_HPMCOUNTER5H 0xc85
#define CSR_HPMCOUNTER6H 0xc86
#define CSR_HPMCOUNTER7H 0xc87
#define CSR_HPMCOUNTER8H 0xc88
#define CSR_HPMCOUNTER9H 0xc89
#define CSR_HPMCOUNTER10H 0xc8a
#define CSR_HPMCOUNTER11H 0xc8b
#define CSR_HPMCOUNTER12H 0xc8c
#define CSR_HPMCOUNTER13H 0xc8d
#define CSR_HPMCOUNTER14H 0xc8e
#define CSR_HPMCOUNTER15H 0xc8f
#define CSR_HPMCOUNTER16H 0xc90
#define CSR_HPMCOUNTER17H 0xc91
#define CSR_HPMCOUNTER18H 0xc92
#define CSR_HPMCOUNTER19H 0xc93
#define CSR_HPMCOUNTER20H 0xc94
#define CSR_HPMCOUNTER21H 0xc95
#define CSR_HPMCOUNTER22H 0xc96
#define CSR_HPMCOUNTER23H 0xc97
#define CSR_HPMCOUNTER24H 0xc98
#define CSR_HPMCOUNTER25H 0xc99
#define CSR_HPMCOUNTER26H 0xc9a
#define CSR_HPMCOUNTER27H 0xc9b
#define CSR_HPMCOUNTER28H 0xc9c
#define CSR_HPMCOUNTER29H 0xc9d
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
#define CSR_MHPMCOUNTER3H 0xb83
#define CSR_MHPMCOUNTER4H 0xb84
#define CSR_MHPMCOUNTER5H 0xb85
#define CSR_MHPMCOUNTER6H 0xb86
#define CSR_MHPMCOUNTER7H 0xb87
#define CSR_MHPMCOUNTER8H 0xb88
#define CSR_MHPMCOUNTER9H 0xb89
#define CSR_MHPMCOUNTER10H 0xb8a
#define CSR_MHPMCOUNTER11H 0xb8b
#define CSR_MHPMCOUNTER12H 0xb8c
#define CSR_MHPMCOUNTER13H 0xb8d
#define CSR_MHPMCOUNTER14H 0xb8e
#define CSR_MHPMCOUNTER15H 0xb8f
#define CSR_MHPMCOUNTER16H 0xb90
#define CSR_MHPMCOUNTER17H 0xb91
#define CSR_MHPMCOUNTER18H 0xb92
#define CSR_MHPMCOUNTER19H 0xb93
#define CSR_MHPMCOUNTER20H 0xb94
#define CSR_MHPMCOUNTER21H 0xb95
#define CSR_MHPMCOUNTER22H 0xb96
#define CSR_MHPMCOUNTER23H 0xb97
#define CSR_MHPMCOUNTER24H 0xb98
#define CSR_MHPMCOUNTER25H 0xb99
#define CSR_MHPMCOUNTER26H 0xb9a
#define CSR_MHPMCOUNTER27H 0xb9b
#define CSR_MHPMCOUNTER28H 0xb9c
#define CSR_MHPMCOUNTER29H 0xb9d
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f

/* === TEE CSR Registers === */
#define CSR_SPMPCFG0            0x1A0
#define CSR_SPMPCFG1            0x1A1
#define CSR_SPMPCFG2            0x1A2
#define CSR_SPMPCFG3            0x1A3
#define CSR_SPMPADDR0           0x1B0
#define CSR_SPMPADDR1           0x1B1
#define CSR_SPMPADDR2           0x1B2
#define CSR_SPMPADDR3           0x1B3
#define CSR_SPMPADDR4           0x1B4
#define CSR_SPMPADDR5           0x1B5
#define CSR_SPMPADDR6           0x1B6
#define CSR_SPMPADDR7           0x1B7
#define CSR_SPMPADDR8           0x1B8
#define CSR_SPMPADDR9           0x1B9
#define CSR_SPMPADDR10          0x1BA
#define CSR_SPMPADDR11          0x1BB
#define CSR_SPMPADDR12          0x1BC
#define CSR_SPMPADDR13          0x1BD
#define CSR_SPMPADDR14          0x1BE
#define CSR_SPMPADDR15          0x1BF

#define CSR_JALSNXTI            0x947
#define CSR_STVT2               0x948
#define CSR_PUSHSCAUSE          0x949
#define CSR_PUSHSEPC            0x94A


/* === CLIC CSR Registers === */
#define CSR_MTVT                0x307
#define CSR_MNXTI               0x345
#define CSR_MINTSTATUS          0x346
#define CSR_MSCRATCHCSW         0x348
#define CSR_MSCRATCHCSWL        0x349
#define CSR_MCLICBASE           0x350

/* === P-Extension Registers === */
#define CSR_UCODE               0x801

/* === Nuclei custom CSR Registers === */
#define CSR_MCOUNTINHIBIT       0x320
#define CSR_MILM_CTL            0x7C0
#define CSR_MDLM_CTL            0x7C1
#define CSR_MECC_CODE           0x7C2
#define CSR_MNVEC               0x7C3
#define CSR_MSUBM               0x7C4
#define CSR_MDCAUSE             0x7C9
#define CSR_MCACHE_CTL          0x7CA
#define CSR_MMISC_CTL           0x7D0
#define CSR_MSAVESTATUS         0x7D6
#define CSR_MSAVEEPC1           0x7D7
#define CSR_MSAVECAUSE1         0x7D8
#define CSR_MSAVEEPC2           0x7D9
#define CSR_MSAVECAUSE2         0x7DA
#define CSR_MSAVEDCAUSE1        0x7DB
#define CSR_MSAVEDCAUSE2        0x7DC
#define CSR_MTLB_CTL            0x7DD
#define CSR_MECC_LOCK           0x7DE
#define CSR_MFP16MODE           0x7E2
#define CSR_LSTEPFORC           0x7E9
#define CSR_PUSHMSUBM           0x7EB
#define CSR_MTVT2               0x7EC
#define CSR_JALMNXTI            0x7ED
#define CSR_PUSHMCAUSE          0x7EE
#define CSR_PUSHMEPC            0x7EF
#define CSR_MPPICFG_INFO        0x7F0
#define CSR_MFIOCFG_INFO        0x7F1
#define CSR_MSMPCFG_INFO        0x7F7
#define CSR_SLEEPVALUE          0x811
#define CSR_TXEVT               0x812
#define CSR_WFE                 0x810
#define CSR_MICFG_INFO          0xFC0
#define CSR_MDCFG_INFO          0xFC1
#define CSR_MCFG_INFO           0xFC2
#define CSR_MTLBCFG_INFO        0xFC3

/* === Nuclei CCM Registers === */
#define CSR_CCM_MBEGINADDR      0x7CB
#define CSR_CCM_MCOMMAND        0x7CC
#define CSR_CCM_MDATA           0x7CD
#define CSR_CCM_SUEN            0x7CE
#define CSR_CCM_SBEGINADDR      0x5CB
#define CSR_CCM_SCOMMAND        0x5CC
#define CSR_CCM_SDATA           0x5CD
#define CSR_CCM_UBEGINADDR      0x4CB
#define CSR_CCM_UCOMMAND        0x4CC
#define CSR_CCM_UDATA           0x4CD
#define CSR_CCM_FPIPE           0x4CF

/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/

/* Exception Code in MCAUSE CSR */
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FAULT_FETCH 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_BREAKPOINT 0x3
#define CAUSE_MISALIGNED_LOAD 0x4
#define CAUSE_FAULT_LOAD 0x5
#define CAUSE_MISALIGNED_STORE 0x6
#define CAUSE_FAULT_STORE 0x7
#define CAUSE_USER_ECALL 0x8
#define CAUSE_SUPERVISOR_ECALL 0x9
#define CAUSE_HYPERVISOR_ECALL 0xa
#define CAUSE_MACHINE_ECALL 0xb

/* Exception Subcode in MDCAUSE CSR */
#define DCAUSE_FAULT_FETCH_PMP      0x1
#define DCAUSE_FAULT_FETCH_INST     0x2

#define DCAUSE_FAULT_LOAD_PMP       0x1
#define DCAUSE_FAULT_LOAD_INST      0x2
#define DCAUSE_FAULT_LOAD_NICE      0x3

#define DCAUSE_FAULT_STORE_PMP      0x1
#define DCAUSE_FAULT_STORE_INST     0x2

/** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/

#ifdef __cplusplus
}
#endif
#endif /* __RISCV_ENCODING_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/CMakeLists.txt
================================================
################# Add global include #################
list(APPEND ADD_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/regs"
"${CMAKE_CURRENT_SOURCE_DIR}/startup"
"${CMAKE_CURRENT_SOURCE_DIR}"
)
#######################################################

################# Add private include #################
list(APPEND ADD_PRIVATE_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/default_config"
)
#######################################################

############## Add current dir source files ###########
file(GLOB_RECURSE sources
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/interrupt.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/system_bl702.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/entry.S"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/start_load.c"
)
list(APPEND ADD_SRCS  ${sources})
# aux_source_directory(src ADD_SRCS)
list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_snflash.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_romdriver.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_clock.c"
)
#######################################################

########### Add required/dependent components #########
list(APPEND ADD_REQUIREMENTS common)
#######################################################

############ Add static libs ##########################
#list(APPEND ADD_STATIC_LIB "lib/libtest.a")
#######################################################

############ Add dynamic libs #########################
# list(APPEND ADD_DYNAMIC_LIB "lib/arch/v831/libmaix_nn.so"
#                             "lib/arch/v831/libmaix_cam.so"
# )
#######################################################

############ Add global compile option ################
#add components denpend on this component
if(CONFIG_ROMAPI)
list(APPEND ADD_DEFINITIONS -DBFLB_USE_ROM_DRIVER)
endif()
if(CONFIG_HALAPI)
list(APPEND ADD_DEFINITIONS -DBFLB_USE_HAL_DRIVER)
endif()
list(APPEND ADD_DEFINITIONS -DARCH_RISCV)
#######################################################

############ Add private compile option ################
#add compile option for this component that won't affect other modules
# list(APPEND ADD_PRIVATE_DEFINITIONS -DAAAAA=1)
#######################################################

generate_library()


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
================================================
/****************************************************************************************
* @file bl702_flash.ld
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/

/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
/* INPUT(-lc) */
/* link with the standard GCC library */
/* INPUT(-lgcc) */
/* configure the entry point */
ENTRY(_enter)

StackSize = 0x1000; /*  4KB */
__EM_SIZE =8K;

MEMORY
{
    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1008K /*1024 - 8K header - 4K*2 for settings and logo*/
    itcm_memory (rx)  : ORIGIN = 0x22014000, LENGTH = 12K
    dtcm_memory (rx)  : ORIGIN = 0x42014000, LENGTH = 8K
    ram_memory  (!rx) : ORIGIN = 0x42016000, LENGTH = 72K
    rsvd_memory (!rx) : ORIGIN = 0x42028000, LENGTH = 1K
    ram2_memory (!rx) : ORIGIN = 0x42028400, LENGTH = (31K - __EM_SIZE)
    hbn_memory  (rx)  : ORIGIN = 0x40010000, LENGTH = 0xE00     /* hbn ram 4K used 3.5K*/
}

SECTIONS
{
    PROVIDE(__metal_chicken_bit = 0);

    .text :
    {
        . = ALIGN(4);
        __text_code_start__ = .;

        KEEP (*(.text.metal.init.enter))
        KEEP (*(SORT_NONE(.init)))
        /* section information for shell */
        . = ALIGN(4);
        __fsymtab_start = .;
        KEEP(*(FSymTab))
        __fsymtab_end = .;

        . = ALIGN(4);
        __vsymtab_start = .;
        KEEP(*(VSymTab))
        __vsymtab_end = .;

        /* section information for usb desc */
        . = ALIGN(4);
        _usb_desc_start = .;
        KEEP(*(usb_desc))
        . = ALIGN(4);
        _usb_desc_end = .;

        *(.text)
        *(.text.*)

        /*put .rodata**/
        *(EXCLUDE_FILE( *bl702_glb*.o* \
                        *bl702_pds*.o* \
                        *bl702_common*.o* \
                        *bl702_sf_cfg*.o* \
                        *bl702_sf_cfg_ext*.o* \
                        *bl702_sf_ctrl*.o* \
                        *bl702_sflash*.o* \
                        *bl702_sflash_ext*.o* \
                        *bl702_xip_sflash*.o* \
                        *bl702_xip_sflash_ext*.o* \
                        *bl702_ef_ctrl*.o*) .rodata*)

        *(.rodata)
        *(.rodata.*)

        *(.srodata)
        *(.srodata.*)

		_bt_gatt_service_static_list_start = .;
        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
        _bt_gatt_service_static_list_end = .;
        _bt_l2cap_fixed_chan_list_start = .;
        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
        _bt_l2cap_fixed_chan_list_end = .;

        . = ALIGN(4);
        __text_code_end__ = .;
    } > xip_memory
    .preinit_array  :
    {
        PROVIDE_HIDDEN (__preinit_array_start = .);
        KEEP (*(.preinit_array))
        PROVIDE_HIDDEN (__preinit_array_end = .);
    } >xip_memory AT>xip_memory
    .init_array     :
    {
        PROVIDE_HIDDEN (__init_array_start = .);
        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
        KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
        PROVIDE_HIDDEN (__init_array_end = .);
    } >xip_memory AT>xip_memory
    .fini_array     :
    {
        PROVIDE_HIDDEN (__fini_array_start = .);
        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
        KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
        PROVIDE_HIDDEN (__fini_array_end = .);
    } >xip_memory AT>xip_memory
  .ctors          :
  {
    /* gcc uses crtbegin.o to find the start of
     * the constructors, so we make sure it is
     * first.  Because this is a wildcard, it
     * doesn't matter if the user does not
     * actually link against crtbegin.o; the
     * linker won't look for a file to match a
     * wildcard.  The wildcard also means that it
     * doesn't matter which directory crtbegin.o
     * is in.
     */
    KEEP (*crtbegin.o(.ctors))
    KEEP (*crtbegin?.o(.ctors))
    /* We don't want to include the .ctor section from
     * the crtend.o file until after the sorted ctors.
     * The .ctor section from the crtend file contains the
     * end of ctors marker and it must be last
     */
    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
  } >xip_memory AT>xip_memory
  .dtors          :
  {
    KEEP (*crtbegin.o(.dtors))
    KEEP (*crtbegin?.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
  } >xip_memory AT>xip_memory
  .lalign         :
  {
    . = ALIGN(4);
    PROVIDE( _data_lma = . );
  } >xip_memory AT>xip_memory
    . = ALIGN(4);
    __itcm_load_addr = .;

    .itcm_region : AT (__itcm_load_addr)
    {
        . = ALIGN(4);
        __tcm_code_start__ = .;

        *(.tcm_code.*)
        *(.tcm_const.*)
        *(.sclock_rlt_code.*)
        *(.sclock_rlt_const.*)

        *bl702_glb*.o*(.rodata*)
        *bl702_pds*.o*(.rodata*)
        *bl702_common*.o*(.rodata*)
        *bl702_sf_cfg*.o*(.rodata*)
        *bl702_sf_cfg_ext*.o*(.rodata*)
        *bl702_sf_ctrl*.o*(.rodata*)
        *bl702_sflash*.o*(.rodata*)
        *bl702_sflash_ext*.o*(.rodata*)
        *bl702_xip_sflash*.o*(.rodata*)
        *bl702_xip_sflash_ext*.o*(.rodata*)
        *bl702_ef_ctrl*.o*(.rodata*)

        . = ALIGN(4);
        __tcm_code_end__ = .;
    } > dtcm_memory

    __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);

    .hbn_ram_region : AT (__hbn_load_addr)
    {
        . = ALIGN(4);
        __hbn_ram_start__ = .;
        *bl702_hbn_wakeup*.o*(.rodata*)
        *(.hbn_ram_code*)
        *(.hbn_ram_data)
        . = ALIGN(4);
        __hbn_ram_end__ = .;
    } > hbn_memory

    __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);

    .dtcm_region : AT (__dtcm_load_addr)
    {
        . = ALIGN(4);
        __tcm_data_start__ = .;

        *(.tcm_data)
        /* *finger_print.o(.data*) */

        . = ALIGN(4);
        __tcm_data_end__ = .;
    } > dtcm_memory
   

    /*************************************************************************/
    /* .stack_dummy section doesn't contains any symbols. It is only
     * used for linker to calculate size of stack sections, and assign
     * values to stack symbols later */
    .stack_dummy (NOLOAD):
    {
        . = ALIGN(0x4);
        . = . + StackSize;
        . = ALIGN(0x4);
    } > dtcm_memory

    /* Set stack top to end of RAM, and stack limit move down by
     * size of stack_dummy section */
    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
    PROVIDE( __freertos_irq_stack_top = __StackTop);
    __StackLimit = __StackTop - SIZEOF(.stack_dummy);

    /* Check if data + heap + stack exceeds RAM limit */
    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
    /*************************************************************************/

    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);

    .system_ram_data_region : AT (__system_ram_load_addr)
    {
        . = ALIGN(4);
        __system_ram_data_start__ = .;

        *(.system_ram)

        . = ALIGN(4);
        __system_ram_data_end__ = .;
    } > ram_memory

    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);

    /* Data section */
    RAM_DATA : AT (__ram_load_addr)
    {
        . = ALIGN(4);
        __ram_data_start__ = .;

        PROVIDE( __global_pointer$ = . + 0x800 );

        *(.data)
        *(.data.*)
        *(.sdata)
        *(.sdata.*)
        *(.sdata2)
        *(.sdata2.*)

        . = ALIGN(4);
        __ram_data_end__ = .;
    } > ram_memory

    .bss (NOLOAD) :
    {
        . = ALIGN(4);
        __bss_start__ = .;

        *(.bss*)
        *(.sbss*)
        *(COMMON)

        . = ALIGN(4);
        __bss_end__ = .;
    } > ram_memory

    .noinit_data (NOLOAD) :
    {
        . = ALIGN(4);
        __noinit_data_start__ = .;

        *(.noinit_data*)

        . = ALIGN(4);
        __noinit_data_end__ = .;
    } > ram_memory

    .heap (NOLOAD):
    {
        . = ALIGN(4);
        __HeapBase = .;

        KEEP(*(.heap*))

        . = ALIGN(4);
        __HeapLimit = .;
    } > ram_memory

    PROVIDE (__heap_min_size = 0x400);
    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);

    ASSERT((__HeapLimit -  __HeapBase ) >= __heap_min_size, "heap size is too short.")

    PROVIDE( _heap_start = ORIGIN(ram2_memory) );
    PROVIDE( _heap_size = LENGTH(ram2_memory) );
}



================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/cpu_flags.cmake
================================================
SET(CPU_ARCH "RISCV")
SET(MCPU "riscv-e24")
SET(MARCH "rv32imafc")
SET(MABI "ilp32f")

list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})

SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld)
SET(RAM_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_ram.ld)
SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld)

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/adc_config.h
================================================
#ifndef _ADC_CONFIG_H
#define _ADC_CONFIG_H

#define ADC_DATA_WIDIH_12 (0)

#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */
#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */

#define ADC_PGA_VCM          (0) /*!< ADC VCM value */
#define ADC_PGA_GAIN1        (0) /*!< PGA gain 1 */
#define ADC_PGA_GAIN2        (0) /*!< PGA gain 2 */
#define ADC_CHOP_MODE        (2) /*!< ADC chop mode select */
#define ADC_BIAS_SELECT      (0) /*!< ADC current form main bandgap or aon bandgap */
#define ADC_OFFSET_CALIB_EN  (0) /*!< Offset calibration enable */
#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/dac_config.h
================================================
#ifndef _DAC_CONFIG_H
#define _DAC_CONFIG_H

#define DAC_REF_SEL      (0)
#define DAC_EXT_REF_GPIO (7)

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/i2s_config.h
================================================
#ifndef _I2S_CONFIG_H
#define _I2S_CONFIG_H

#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ
#define I2S_DATA_ENDIAN       I2S_DATA_ENDIAN_MSB
#define I2S_MONO_CHANNEL      I2S_RX_MONO_MODE_RIGHT_CHANNEL
#define I2S_LR_EXCHANGE       DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/
#define I2S_FS_INVERT         DISABLE
#define I2S_BCLK_INVERT       DISABLE

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/default_config/uart_config.h
================================================
#ifndef _UART_CONFIG_H
#define _UART_CONFIG_H

#define UART_CTS_FLOWCONTROL_ENABLE  (0)
#define UART_RTS_FLOWCONTROL_ENABLE  (0)
#define UART_RX_DEGLITCH_ENABLE      (0)
#define UART_MSB_FIRST_ENABLE        (0)
#define UART_TX_SWCONTROL_ENABLE     (0)
#define UART_TX_LINMODE_ENABLE       (0)
#define UART_RX_LINMODE_ENABLE       (0)
#define UART_TX_BREAKBIT_CNT         (0)

#define UART_FIFO_MAX_LEN        128
#define UART_DEFAULT_RTO_TIMEOUT 100

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_adc.h
================================================
/**
 * @file hal_adc.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_ADC__H__
#define __HAL_ADC__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

#define DEVICE_CTRL_ADC_CHANNEL_START  0x10
#define DEVICE_CTRL_ADC_CHANNEL_STOP   0x11
#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12
#define DEVICE_CTRL_ADC_VBAT_ON        0x13
#define DEVICE_CTRL_ADC_VBAT_OFF       0x14
#define DEVICE_CTRL_ADC_TSEN_ON        0x15
#define DEVICE_CTRL_ADC_TSEN_OFF       0x16
#define DEVICE_CTRL_ADC_DATA_PARSE     0x17

enum adc_index_type {
#ifdef BSP_USING_ADC0
    ADC0_INDEX,
#endif
    ADC_MAX_INDEX
};

#define adc_channel_start(dev)        device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
#define adc_channel_stop(dev)         device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)

typedef enum {
    ADC_CHANNEL0,          /* ADC channel 0 */
    ADC_CHANNEL1,          /* ADC channel 1 */
    ADC_CHANNEL2,          /* ADC channel 2 */
    ADC_CHANNEL3,          /* ADC channel 3 */
    ADC_CHANNEL4,          /* ADC channel 4 */
    ADC_CHANNEL5,          /* ADC channel 5 */
    ADC_CHANNEL6,          /* ADC channel 6 */
    ADC_CHANNEL7,          /* ADC channel 7 */
    ADC_CHANNEL8,          /* ADC channel 8 */
    ADC_CHANNEL9,          /* ADC channel 9 */
    ADC_CHANNEL10,         /* ADC channel 10 */
    ADC_CHANNEL11,         /* ADC channel 11 */
    ADC_CHANNEL_DAC_OUTA,  /* DACA, ADC channel 12 */
    ADC_CHANNEL_DAC_OUTB,  /* DACB, ADC channel 13 */
    ADC_CHANNEL_TSEN_P,    /* TSenp, ADC channel 14 */
    ADC_CHANNEL_TSEN_N,    /* TSenn, ADC channel 15 */
    ADC_CHANNEL_VREF,      /* Vref, ADC channel 16 */
    ADC_CHANNEL_DCTEST,    /* DCTest, ADC channel 17 */
    ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */
    ADC_CHANNEL_SENP3,     /* SenVP3, ADC channel 19 */
    ADC_CHANNEL_SENP2,     /* SenVP2, ADC channel 20 */
    ADC_CHANNEL_SENP1,     /* SenVP1, ADC channel 21 */
    ADC_CHANNEL_SENP0,     /* SenVP0, ADC channel 22 */
    ADC_CHANNEL_GND,       /* GND, ADC channel 23 */
} adc_channel_t;

typedef enum {
    ADC_CLOCK_DIV_1,  /*!< ADC clock:on 32M clock is 32M */
    ADC_CLOCK_DIV_4,  /*!< ADC clock:on 32M clock is 8M */
    ADC_CLOCK_DIV_8,  /*!< ADC clock:on 32M clock is 4M */
    ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
    ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
    ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
    ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
    ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
} adc_clk_div_t;

typedef enum {
    ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */
    ADC_VREF_2V = 1,  /* ADC select 2V as reference voltage */
} adc_vref_t;

/**
 *  @brief ADC data width type definition
 */
typedef enum {
    ADC_DATA_WIDTH_12B,                  /*!< ADC 12 bits */
    ADC_DATA_WIDTH_14B_WITH_16_AVERAGE,  /*!< ADC 14 bits,and the value is average of 16 converts */
    ADC_DATA_WIDTH_14B_WITH_64_AVERAGE,  /*!< ADC 14 bits,and the value is average of 64 converts */
    ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
    ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
} adc_data_width_t;

/**
 *  @brief ADC FIFO threshold type definition
 */
typedef enum {
    ADC_FIFO_THRESHOLD_1BYTE,  /*!< ADC FIFO threshold is 1 */
    ADC_FIFO_THRESHOLD_4BYTE,  /*!< ADC FIFO threshold is 4 */
    ADC_FIFO_THRESHOLD_8BYTE,  /*!< ADC FIFO threshold is 8 */
    ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */
} adc_fifo_threshold_t;

/**
 *  @brief ADC PGA gain type definition
 */
typedef enum {
    ADC_GAIN_NONE, /*!< No PGA gain */
    ADC_GAIN_1,    /*!< PGA gain 1 */
    ADC_GAIN_2,    /*!< PGA gain 2 */
    ADC_GAIN_4,    /*!< PGA gain 4 */
    ADC_GAIN_8,    /*!< PGA gain 8 */
    ADC_GAIN_16,   /*!< PGA gain 16 */
    ADC_GAIN_32,   /*!< PGA gain 32 */
} adc_pga_gain_t;

enum adc_event_type {
    ADC_EVENT_UNDERRUN,
    ADC_EVENT_OVERRUN,
    ADC_EVENT_FIFO,
    ADC_EVENT_UNKNOWN
};

enum adc_it_type {
    ADC_UNDERRUN_IT = 1 << 2,
    ADC_OVERRUN_IT = 1 << 3,
    ADC_FIFO_IT = 1 << 5,
};

typedef struct {
    uint8_t *pos_channel;
    uint8_t *neg_channel;
    uint8_t num;
} adc_channel_cfg_t;

typedef struct {
    int8_t posChan; /*!< Positive channel */
    int8_t negChan; /*!< Negative channel */
    uint16_t value; /*!< ADC value */
    float volt;     /*!< ADC voltage result */
} adc_channel_val_t;

typedef struct
{
    uint32_t *input;
    adc_channel_val_t *output;
    uint32_t num;
} adc_data_parse_t;

typedef struct adc_device {
    struct device parent;
    adc_clk_div_t clk_div;     /* CLK is not more than 2Mhz */
    adc_vref_t vref;           /* ADC voltage reference*/
    bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */
    bool differential_mode;    /** Channel type: single-ended or differential. */
    adc_data_width_t data_width;
    adc_fifo_threshold_t fifo_threshold;
    adc_pga_gain_t gain;
    void *rx_dma;
} adc_device_t;

#define ADC_DEV(dev) ((adc_device_t *)dev)

int adc_register(enum adc_index_type index, const char *name);
int adc_trim_tsen(uint16_t *tsen_offset);
float adc_get_tsen(uint16_t tsen_offset);

#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_boot2.h
================================================
/**
 * *****************************************************************************
 * @file hal_boot2_custom.h
 * @version 0.1
 * @date 2021-07-17
 * @brief
 * *****************************************************************************
 * @attention
 *
 *  
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 *  Redistribution and use in source and binary forms, with or without modification,
 *  are permitted provided that the following conditions are met:
 *    1. Redistributions of source code must retain the above copyright notice,
 *       this list of conditions and the following disclaimer.
 *    2. Redistributions in binary form must reproduce the above copyright notice,
 *       this list of conditions and the following disclaimer in the documentation
 *       and/or other materials provided with the distribution.
 *    3. Neither the name of Bouffalo Lab nor the names of its contributors
 *       may be used to endorse or promote products derived from this software
 *       without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 *  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 *  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 *  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 *  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * *****************************************************************************
 */
#ifndef __HAL_BOOT2_H__
#define __HAL_BOOT2_H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_glb.h"

#define BL_TCM_BASE           BL702_TCM_BASE
#define BL_SYS_CLK_PLL        GLB_SYS_CLK_DLL144M
#define BL_SFLASH_CLK         GLB_SFLASH_CLK_72M
#define HAL_PLL_CFG_MAGICCODE "PCFG"

#define HAL_BOOT2_PK_HASH_SIZE                256 / 8
#define HAL_BOOT2_IMG_HASH_SIZE               256 / 8
#define HAL_BOOT2_ECC_KEYXSIZE                256 / 8
#define HAL_BOOT2_ECC_KEYYSIZE                256 / 8
#define HAL_BOOT2_SIGN_MAXSIZE                (2048 / 8)
#define HAL_BOOT2_DEADBEEF_VAL                0xdeadbeef
#define HAL_BOOT2_CPU0_MAGIC                  "BFNP"
#define HAL_BOOT2_CPU1_MAGIC                  "BFAP"
#define HAL_BOOT2_CP_FLAG                     0x02
#define HAL_BOOT2_MP_FLAG                     0x01
#define HAL_BOOT2_SP_FLAG                     0x00

#define HAL_BOOT2_SUPPORT_DECOMPRESS          1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_USB_IAP             0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM   1 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */

#define HAL_BOOT2_CPU_GROUP_MAX               1
#define HAL_BOOT2_CPU_MAX                     1
#define HAL_BOOT2_RAM_IMG_COUNT_MAX           0

#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER  4*1024  
typedef struct
{
    uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX];
    uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX];
    uint8_t hbn_check_sign;
    uint8_t rsvd[1];
    uint8_t chip_id[8];
    uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE];
    uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE];
    uint8_t uart_download_cfg;
    uint8_t sf_pin_cfg;
    uint8_t keep_dbg_port_closed;
    uint8_t boot_pin_cfg;
} boot2_efuse_hw_config;

struct __attribute__((packed, aligned(4))) hal_flash_config 
{
    uint32_t magicCode; /*'FCFG'*/
    SPI_Flash_Cfg_Type cfg;
    uint32_t crc32;
} ;

typedef struct
{
    uint8_t xtal_type;
    uint8_t pll_clk;
    uint8_t hclk_div;
    uint8_t bclk_div;

    uint8_t flash_clk_type;
    uint8_t flash_clk_div;
    uint8_t rsvd[2];
} hal_sys_clk_config;

typedef struct
{
    uint32_t magicCode; /*'PCFG'*/
    hal_sys_clk_config cfg;
    uint32_t crc32;
} hal_pll_config;


struct __attribute__((packed, aligned(4))) hal_basic_cfg_t {
    uint32_t sign_type          : 2; /* [1: 0]   for sign */
    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
    uint32_t key_sel            : 2; /* [5: 4]   key slot */
    uint32_t xts_mode           : 1; /* [6]      for xts mode */
    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
    uint32_t no_segment         : 1; /* [8]      no segment info */
    uint32_t boot2_enable       : 1; /* [9]      boot2 enable */
    uint32_t boot2_rollback     : 1; /* [10]     boot2 rollback */
    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
    uint32_t power_on_mm        : 1; /* [18]     power on mm */
    uint32_t em_sel             : 3; /* [21: 19] em_sel */
    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
    uint32_t icache_invalid     : 1; /* [29] icache invalid */
    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
    uint32_t fpga_halt_release  : 1; /* [31] FPGA halt release function */

    uint32_t group_image_offset;     /* flash controller offset */
    uint32_t aes_region_len;         /* aes region length */

    uint32_t img_len_cnt;            /* image length or segment count */
    uint32_t hash[8];                /* hash of the image */
};

struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t {
    uint8_t config_enable;          /* coinfig this cpu */
    uint8_t halt_cpu;               /* halt this cpu */
    uint8_t cache_enable  : 1;      /* cache setting */
    uint8_t cache_wa      : 1;      /* cache setting */
    uint8_t cache_wb      : 1;      /* cache setting */
    uint8_t cache_wt      : 1;      /* cache setting */
    uint8_t cache_way_dis : 4;      /* cache setting */
    uint8_t rsvd;

    uint32_t image_address_offset;  /* image address on flash */
    uint32_t boot_entry;            /* entry point of the m0 image */
    uint32_t msp_val;               /* msp value */
};


struct  hal_bootheader_t
{
    uint32_t magicCode; /*'BFXP'*/
    uint32_t rivison;
    struct hal_flash_config flash_cfg;
    hal_pll_config clk_cfg;
    __PACKED_UNION
    {
        __PACKED_STRUCT
        {
            uint32_t sign              : 2;  /* [1: 0]      for sign*/
            uint32_t encrypt_type      : 2;  /* [3: 2]      for encrypt */
            uint32_t key_sel           : 2;  /* [5: 4]      for key sel in boot interface*/
            uint32_t rsvd6_7           : 2;  /* [7: 6]      for encrypt*/
            uint32_t no_segment        : 1;  /* [8]         no segment info */
            uint32_t cache_enable      : 1;  /* [9]         for cache */
            uint32_t notLoadInBoot     : 1;  /* [10]        not load this img in bootrom */
            uint32_t aes_region_lock   : 1;  /* [11]        aes region lock */
            uint32_t cache_way_disable : 4;  /* [15: 12]    cache way disable info*/
            uint32_t crcIgnore         : 1;  /* [16]        ignore crc */
            uint32_t hash_ignore       : 1;  /* [17]        hash crc */
            uint32_t halt_cpu1         : 1;  /* [18]        halt ap */
            uint32_t rsvd19_31         : 13; /* [31:19]     rsvd */
        }
        bval;
        uint32_t wval;
    }
    bootCfg;

    __PACKED_UNION
    {
        uint32_t segment_cnt;
        uint32_t img_len;
    }
    img_segment_info;

    uint32_t bootEntry; /* entry point of the image*/
    __PACKED_UNION
    {
        uint32_t ram_addr;
        uint32_t flash_offset;
    }
    img_start;

    uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/

    uint32_t rsv1;
    uint32_t rsv2;
    uint32_t crc32;
} ;

typedef struct
{
    uint8_t img_valid;
    uint8_t pk_src;
    uint8_t rsvd[2];

    struct hal_basic_cfg_t basic_cfg;

    struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX];

    uint8_t aes_iv[16 + 4];                         //iv in boot header

    uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE];  //ec key in boot header
    uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE];  //ec key in boot header
    uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header
    uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header

    uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE];  //signature in boot header
    uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header

} boot2_image_config;

extern boot2_efuse_hw_config g_efuse_cfg;
extern uint8_t g_ps_mode;
extern uint32_t g_user_hash_ignored;
extern struct device *dev_check_hash;




uint32_t hal_boot2_custom(void);
void hal_boot2_reset_sec_eng(void);
void hal_boot2_sw_system_reset(void);
void hal_boot2_set_psmode_status(uint32_t flag);
uint32_t hal_boot2_get_psmode_status(void);
uint32_t hal_boot2_get_user_fw(void);
void hal_boot2_clr_user_fw(void);
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg);
int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg);
void hal_boot2_sboot_finish(void);
void hal_boot2_uart_gpio_init(void);
void hal_boot2_debug_uart_gpio_init(void);
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void);
#endif

void hal_boot2_debug_uart_gpio_deinit(void);
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data);
void hal_boot2_clean_cache(void);
BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg);
void hal_boot2_get_ram_img_cnt(char* img_name[],uint32_t *ram_img_cnt );
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len,uint8_t **hash);
void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr);
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr);
uint32_t hal_boot2_get_grp_count(void);
uint32_t hal_boot2_get_cpu_count(void);
uint32_t hal_boot2_get_feature_flag(void);
uint32_t hal_boot2_get_bootheader_offset(void);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_clock.h
================================================
/**
 * @file hal_clock.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_CLOCK__H__
#define __HAL_CLOCK__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "bl702_config.h"

/*XTAL_TYPE*/
#define XTAL_NONE         0
#define EXTERNAL_XTAL_32M 1
#define INTERNAL_RC_32M   2

/*CLOCK_32K_XTAL*/
#define EXTERNAL_XTAL_32K 0
#define INTERNAL_RC_32K   1

/*BSP_ROOT_CLOCK_SOURCE*/
#if XTAL_TYPE != EXTERNAL_XTAL_32M
#define ROOT_CLOCK_SOURCE_XCLK 0
#else
#define ROOT_CLOCK_SOURCE_XCLK 1
#endif
#define ROOT_CLOCK_SOURCE_PLL_57P6M 2
#define ROOT_CLOCK_SOURCE_PLL_96M   3
#define ROOT_CLOCK_SOURCE_PLL_144M  4
/*BSP_XXX_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_32K_CLK 5
#define ROOT_CLOCK_SOURCE_FCLK    6
#define ROOT_CLOCK_SOURCE_BCLK    7
#define ROOT_CLOCK_SOURCE_1K_CLK  8

/*BSP_AUDIO_PLL_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ  11
#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13

enum system_clock_type {
    SYSTEM_CLOCK_ROOT_CLOCK = 0, /* clock source before fclk_div*/
    SYSTEM_CLOCK_FCLK,           /* clock source after fclk_div*/
    SYSTEM_CLOCK_BCLK,           /* clock source after bclk_div*/
    SYSTEM_CLOCK_XCLK,           /* xtal clock*/
    SYSTEM_CLOCK_32K_CLK,
    SYSTEM_CLOCK_AUPLL,
};
enum peripheral_clock_type {
    PERIPHERAL_CLOCK_UART = 0,
    PERIPHERAL_CLOCK_SPI,
    PERIPHERAL_CLOCK_I2C,
    PERIPHERAL_CLOCK_ADC,
    PERIPHERAL_CLOCK_DAC,
    PERIPHERAL_CLOCK_I2S,
    PERIPHERAL_CLOCK_PWM,
    PERIPHERAL_CLOCK_CAM,
    PERIPHERAL_CLOCK_TIMER0,
    PERIPHERAL_CLOCK_TIMER1,
    PERIPHERAL_CLOCK_WDT,
};

void system_clock_init(void);
void peripheral_clock_init(void);
uint32_t system_clock_get(enum system_clock_type type);
uint32_t peripheral_clock_get(enum peripheral_clock_type type);
void system_mtimer_clock_init(void);
void system_mtimer_clock_reinit(void);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_common.h
================================================
/**
 * @file hal_common.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_COMMON__H__
#define __HAL_COMMON__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "bl702_common.h"

void cpu_global_irq_enable(void);
void cpu_global_irq_disable(void);
void hal_por_reset(void);
void hal_system_reset(void);
void hal_cpu_reset(void);
void hal_get_chip_id(uint8_t chip_id[8]);
void hal_enter_usb_iap(void);
void hal_jump2app(uint32_t flash_offset);
int hal_get_trng_seed(void);

#ifdef __cplusplus
}
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_dma.h
================================================
/**
 * @file hal_dma.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_DMA__H__
#define __HAL_DMA__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10
#define DEVICE_CTRL_DMA_CHANNEL_START      0x11
#define DEVICE_CTRL_DMA_CHANNEL_STOP       0x12
#define DEVICE_CTRL_DMA_CHANNEL_UPDATE     0x13
#define DEVICE_CTRL_DMA_CONFIG_SI          0x14
#define DEVICE_CTRL_DMA_CONFIG_DI          0x15

enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
    DMA0_CH0_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH1
    DMA0_CH1_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH2
    DMA0_CH2_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH3
    DMA0_CH3_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH4
    DMA0_CH4_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH5
    DMA0_CH5_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH6
    DMA0_CH6_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH7
    DMA0_CH7_INDEX,
#endif
    DMA_MAX_INDEX
};

#define dma_channel_start(dev)        device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL)
#define dma_channel_stop(dev)         device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL)
#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev)   device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL)

#define DMA_LLI_ONCE_MODE  0
#define DMA_LLI_CYCLE_MODE 1

#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */
#define DMA_ADDR_INCREMENT_ENABLE  1 /*!< Addr increment mode enable  */

#define DMA_TRANSFER_WIDTH_8BIT  0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2

#define DMA_BURST_INCR1  0
#define DMA_BURST_INCR4  1
#define DMA_BURST_INCR8  2
#define DMA_BURST_INCR16 3

#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
#define DMA_ADDR_I2C_TDR   (0x4000A300 + 0x88)
#define DMA_ADDR_I2C_RDR   (0x4000A300 + 0x8C)
#define DMA_ADDR_SPI_TDR   (0x4000A200 + 0x88)
#define DMA_ADDR_SPI_RDR   (0x4000A200 + 0x8C)
#define DMA_ADDR_I2S_TDR   (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR   (0x4000AA00 + 0x8C)
#define DMA_ADDR_ADC_RDR   (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR   (0x40002000 + 0X48)

#define DMA_REQUEST_NONE     0x00000000 /*!< DMA request peripheral:None */
#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */
#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */
#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */
#define DMA_REQUEST_I2C0_RX  0x00000006 /*!< DMA request peripheral:I2C RX */
#define DMA_REQUEST_I2C0_TX  0x00000007 /*!< DMA request peripheral:I2C TX */
#define DMA_REQUEST_SPI0_RX  0x0000000A /*!< DMA request peripheral:SPI RX */
#define DMA_REQUEST_SPI0_TX  0x0000000B /*!< DMA request peripheral:SPI TX */
#define DMA_REQUEST_I2S_RX   0x00000014 /*!< DMA request peripheral:I2S RX */
#define DMA_REQUEST_I2S_TX   0x00000015 /*!< DMA request peripheral:I2S TX */
#define DMA_REQUEST_ADC0     0x00000016 /*!< DMA request peripheral:ADC0 */
#define DMA_REQUEST_DAC0     0x00000017 /*!< DMA request peripheral:DAC0 */
#define DMA_REQUEST_USB_EP0  0x00000018 /*!< DMA request peripheral:USB EP0*/
#define DMA_REQUEST_USB_EP1  0x00000019 /*!< DMA request peripheral:USB EP1*/
#define DMA_REQUEST_USB_EP2  0x0000001A /*!< DMA request peripheral:USB EP2*/
#define DMA_REQUEST_USB_EP3  0x0000001B /*!< DMA request peripheral:USB EP3*/
#define DMA_REQUEST_USB_EP4  0x0000001C /*!< DMA request peripheral:USB EP4*/
#define DMA_REQUEST_USB_EP5  0x0000001D /*!< DMA request peripheral:USB EP5*/
#define DMA_REQUEST_USB_EP6  0x0000001E /*!< DMA request peripheral:USB EP6*/
#define DMA_REQUEST_USB_EP7  0x0000001F /*!< DMA request peripheral:USB EP7 */

/**
 *  @brief DMA transfer direction type definition
 */
typedef enum {
    DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */
    DMA_MEMORY_TO_PERIPH,     /*!< DMA transfer type:memory to peripheral */
    DMA_PERIPH_TO_MEMORY,     /*!< DMA transfer type:peripheral to memory */
    DMA_PERIPH_TO_PERIPH,     /*!< DMA transfer type:peripheral to peripheral */
} dma_transfer_dir_type;

typedef union {
    struct
    {
        uint32_t TransferSize : 12; /* [11: 0],        r/w,        0x0 */
        uint32_t SBSize       : 2;  /* [13:12],        r/w,        0x1 */
        uint32_t dst_min_mode : 1;  /* [   14],        r/w,        0x0 */
        uint32_t DBSize       : 2;  /* [16:15],        r/w,        0x1 */
        uint32_t dst_add_mode : 1;  /* [   17],        r/w,        0x0 */
        uint32_t SWidth       : 2;  /* [19:18],        r/w,        0x2 */
        uint32_t reserved_20  : 1;  /* [   20],       rsvd,        0x0 */
        uint32_t DWidth       : 2;  /* [22:21],        r/w,        0x2 */
        uint32_t fix_cnt      : 2;  /* [24:23],        r/w,        0x0 */
        uint32_t SLargerD     : 1;  /* [   25],        r/w,        0x0 */
        uint32_t SI           : 1;  /* [   26],        r/w,        0x1 */
        uint32_t DI           : 1;  /* [   27],        r/w,        0x1 */
        uint32_t Prot         : 3;  /* [30:28],        r/w,        0x0 */
        uint32_t I            : 1;  /* [   31],        r/w,        0x0 */
    } bits;
    uint32_t WORD;
} dma_control_data_t;

typedef struct
{
    uint32_t src_addr;
    uint32_t dst_addr;
    uint32_t nextlli;
    dma_control_data_t cfg;
} dma_lli_ctrl_t;

typedef struct dma_device {
    struct device parent;
    uint8_t id;
    uint8_t ch;
    uint8_t transfer_mode;
    uint8_t direction;
    uint32_t src_req;
    uint32_t dst_req;
    uint8_t src_addr_inc;
    uint8_t dst_addr_inc;
    uint8_t src_burst_size;
    uint8_t dst_burst_size;
    uint8_t src_width;
    uint8_t dst_width;
    uint8_t intr; /* private param */
    dma_lli_ctrl_t *lli_cfg;/* private param*/
} dma_device_t;

#define DMA_DEV(dev) ((dma_device_t *)dev)

int dma_register(enum dma_index_type index, const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);

#ifdef __cplusplus
}
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_flash.h
================================================
/**
 * @file hal_flash.h
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_FLASH__H__
#define __HAL_FLASH__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_sflash_ext.h"

#define FLASH_NOT_DETECT  0x10
#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE

uint32_t flash_get_jedecid(void);
BL_Err_Type flash_init(void);
BL_Err_Type flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
BL_Err_Type flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect);
#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_gpio.h
================================================
/**
 * @file hal_gpio.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_GPIO__H__
#define __HAL_GPIO__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "bl702_config.h"
#include "drv_device.h"
#include "hal_common.h"

enum gpio_pin_type {
  GPIO_PIN_0 = 0,
  GPIO_PIN_1,
  GPIO_PIN_2,
  GPIO_PIN_3,
  GPIO_PIN_4,
  GPIO_PIN_5,
  GPIO_PIN_6,
  GPIO_PIN_7,
  GPIO_PIN_8,
  GPIO_PIN_9,
  GPIO_PIN_10,
  GPIO_PIN_11,
  GPIO_PIN_12,
  GPIO_PIN_13,
  GPIO_PIN_14,
  GPIO_PIN_15,
  GPIO_PIN_16,
  GPIO_PIN_17,
  GPIO_PIN_18,
  GPIO_PIN_19,
  GPIO_PIN_20,
  GPIO_PIN_21,
  GPIO_PIN_22,
  GPIO_PIN_23,
  GPIO_PIN_24,
  GPIO_PIN_25,
  GPIO_PIN_26,
  GPIO_PIN_27,
  GPIO_PIN_28,
  GPIO_PIN_29,
  GPIO_PIN_30,
  GPIO_PIN_31,
  GPIO_PIN_MAX,
};

#define GPIO_OUTPUT_MODE                   0
#define GPIO_OUTPUT_PP_MODE                1
#define GPIO_OUTPUT_PD_MODE                2
#define GPIO_INPUT_MODE                    3
#define GPIO_INPUT_PU_MODE                 4
#define GPIO_INPUT_PD_MODE                 5
#define GPIO_ASYNC_RISING_TRIGER_INT_MODE  6
#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7
#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE     8
#define GPIO_ASYNC_LOW_LEVEL_INT_MODE      9
#define GPIO_SYNC_RISING_TRIGER_INT_MODE   10
#define GPIO_SYNC_FALLING_TRIGER_INT_MODE  11
#define GPIO_SYNC_HIGH_LEVEL_INT_MODE      12
#define GPIO_SYNC_LOW_LEVEL_INT_MODE       13
#define GPIO_HZ_MODE                       14

void gpio_set_mode(uint32_t pin, uint32_t mode);
void gpio_write(uint32_t pin, uint32_t value);
void gpio_toggle(uint32_t pin);
int  gpio_read(uint32_t pin);
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin));
void gpio_irq_enable(uint32_t pin, uint8_t enabled);

#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_i2c.h
================================================
/**
 * @file hal_i2c.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_I2C__H__
#define __HAL_I2C__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

enum i2c_index_type {
#ifdef BSP_USING_I2C0
    I2C0_INDEX,
#endif
    I2C_MAX_INDEX
};

#define I2C_WR      0x0000
#define I2C_RD      0x0001
#define I2C_RW_MASK 0x0001

#define SUB_ADDR_0BYTE 0x0010
#define SUB_ADDR_1BYTE 0x0020
#define SUB_ADDR_2BYTE 0x0040

#define I2C_HW_MODE 0
#define I2C_SW_MODE 1

typedef struct i2c_msg {
    uint8_t slaveaddr;
    uint32_t subaddr;
    uint16_t flags;
    uint16_t len;
    uint8_t *buf;
} i2c_msg_t;

typedef struct i2c_device {
    struct device parent;
    uint8_t id;
    uint8_t mode;
    uint32_t phase;
} i2c_device_t;

#define I2C_DEV(dev) ((i2c_device_t *)dev)

int i2c_register(enum i2c_index_type index, const char *name);
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);

#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
================================================
/**
 * @file hal_mtimer.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_MTIMER__H__
#define __HAL_MTIMER__H__

#include "stdint.h"

#ifdef __cplusplus
extern "C"{
#endif

void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
uint64_t mtimer_get_time_ms();
uint64_t mtimer_get_time_us();
void mtimer_delay_ms(uint32_t time);
void mtimer_delay_us(uint32_t time);

#ifdef __cplusplus
}
#endif

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm.h
================================================
/**
 * @file hal_pm.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_PM__H__
#define __HAL_PM__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "hal_common.h"

enum pm_pds_sleep_level {
    PM_PDS_LEVEL_0,
    PM_PDS_LEVEL_1,
    PM_PDS_LEVEL_2,
    PM_PDS_LEVEL_3,
    PM_PDS_LEVEL_4, /*do not recommend to use*/
    PM_PDS_LEVEL_5, /*do not recommend to use*/
    PM_PDS_LEVEL_6, /*do not recommend to use*/
    PM_PDS_LEVEL_7, /*do not recommend to use*/
    PM_PDS_LEVEL_31 = 31,
};

enum pm_hbn_sleep_level {
    PM_HBN_LEVEL_0,
    PM_HBN_LEVEL_1,
    PM_HBN_LEVEL_2,
};

enum pm_event_type {
    PM_HBN_WAKEUP_EVENT_NONE,
    PM_HBN_GPIO9_WAKEUP_EVENT,
    PM_HBN_GPIO10_WAKEUP_EVENT,
    PM_HBN_GPIO11_WAKEUP_EVENT,
    PM_HBN_GPIO12_WAKEUP_EVENT,
    PM_HBN_RTC_WAKEUP_EVENT,
    PM_HBN_BOR_WAKEUP_EVENT,
    PM_HBN_ACOMP0_WAKEUP_EVENT,
    PM_HBN_ACOMP1_WAKEUP_EVENT,
};

void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time);
void pm_hbn_enter_again(bool reset);
void pm_set_wakeup_callback(void (*wakeup_callback)(void));
enum pm_event_type pm_get_wakeup_event(void);
void pm_bor_init(void);
void pm_hbn_out0_irq_register(void);
void pm_hbn_out1_irq_register(void);
void pm_irq_callback(enum pm_event_type event);

#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_pm_util.h
================================================
/**
 * @file hal_pm_util.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_PM_UTIL_H__
#define __HAL_PM_UTIL_H__

#include "hal_common.h"

#define ATTR_PDS_RAM_SECTION       __attribute__((section(".pds_ram_code")))
#define ATTR_PDS_RAM_CONST_SECTION __attribute__((section(".pds_ram_data")))

uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles);
void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void));
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_rtc.h
================================================
/**
 * @file hal_rtc.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_RTC__H__
#define __HAL_RTC__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"

void rtc_init(uint64_t sleep_time);
void rtc_set_timestamp(uint64_t time_stamp);
uint64_t rtc_get_timestamp(void);

#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h
================================================
/**
 * @file hal_sec_aes.h
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_SEC_AES__H__
#define __HAL_SEC_AES__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"

typedef enum {
    SEC_AES_CBC,
    SEC_AES_CTR,
    SEC_AES_ECB
} sec_aes_type;

typedef enum {
    SEC_AES_KEY_128,
    SEC_AES_KEY_256,
    SEC_AES_KEY_192
} sec_aes_key_type;

typedef struct sec_aes_handle_t {
    sec_aes_type aes_type;
    sec_aes_key_type key_type;
} sec_aes_handle_t;

typedef enum {
    SEC_AES_DIR_ENCRYPT,
    SEC_AES_DIR_DECRYPT
} sec_aes_dir_type;

int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type);
int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir);
int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_deinit(sec_aes_handle_t *handle);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h
================================================
/**
 * @file hal_sec_dsa.h
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_SEC_DSA__H__
#define __HAL_SEC_DSA__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"

typedef struct sec_dsa_crt_cfg_tag {
    uint32_t *dP;
    uint32_t *dQ;
    uint32_t *qInv;
    uint32_t *p;
    uint32_t *invR_p;
    uint32_t *primeN_p;
    uint32_t *q;
    uint32_t *invR_q;
    uint32_t *primeN_q;
} sec_dsa_crt_cfg_t;

typedef struct
{
    uint32_t size;
    uint32_t crtSize;
    uint32_t *n;
    uint32_t *e;
    uint32_t *d;
    sec_dsa_crt_cfg_t crtCfg;
} sec_dsa_handle_t;

int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size);
int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r);
int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r);
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r);
int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
================================================
/**
 * @file hal_sec_ecdsa.h
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_SEC_ECDSA__H__
#define __HAL_SEC_ECDSA__H__

#ifdef __cplusplus
extern "C" {
#endif

#include "hal_common.h"

typedef enum {
    ECP_SECP256R1 = 0,
    ECP_SECP256K1 = 1,
    ECP_TYPE_MAX = 2,
} sec_ecp_type;

typedef struct
{
    sec_ecp_type ecpId;
    uint32_t *privateKey;
    uint32_t *publicKeyx;
    uint32_t *publicKeyy;
} sec_ecdsa_handle_t;

typedef struct
{
    sec_ecp_type ecpId;
} sec_ecdh_handle_t;

int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id);
int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle);
int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key);
int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);

int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id);
int sec_ecdh_deinit(sec_ecdh_handle_t *handle);
int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size);
int sec_eng_trng_enable(void);
void sec_eng_trng_disable(void);
int sec_eng_trng_read(uint8_t data[32]);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h
================================================
/**
 * @file hal_sec_hash.h
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_SEC_HASH__H__
#define __HAL_SEC_HASH__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

enum sec_hash_index_type {
    SEC_HASH0_INDEX,
    SEC_HASH_MAX_INDEX
};

enum sec_hash_type {
    SEC_HASH_SHA1,
    SEC_HASH_SHA224,
    SEC_HASH_SHA256,
    SEC_HASH_SHA384,
    SEC_HASH_SHA512,
    SEC_HASH_UNKNOWN
};

typedef struct sec_hash_device {
    struct device parent;
    uint32_t shaBuf[64 / 4];     /*!< Data not processed but in this temp buffer */
    uint32_t shaPadding[64 / 4]; /*!< Padding data */
    uint8_t type;                /*!< Sha has feed data */
} sec_hash_device_t;

typedef struct
{
    uint32_t shaBuf[64 / 4];     /*!< Data not processed but in this temp buffer */
    uint32_t shaPadding[64 / 4]; /*!< Padding data */
    uint8_t type;                /*!< Sha has feed data */
} sec_hash_handle_t;

int sec_hash_init(sec_hash_handle_t *handle, uint8_t type);
int sec_hash_deinit(sec_hash_handle_t *handle);
int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size);
int sec_hash_finish(sec_hash_handle_t *handle, void *buffer);
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name);
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name);

#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_uart.h
================================================
/**
 * @file hal_uart.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_UART__H__
#define __HAL_UART__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

#define UART_FIFO_LEN 128

#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
#define DEVICE_CTRL_UART_CLEAR_TX_FIFO 0x12
#define DEVICE_CTRL_UART_CLEAR_RX_FIFO 0x13

enum uart_index_type {
#ifdef BSP_USING_UART0
    UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
    UART1_INDEX,
#endif
    UART_MAX_INDEX
};

/*!
 *  @brief    UART data length settings
 *
 *  This enumeration defines the UART data lengths.
 */
typedef enum {
    UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */
    UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */
    UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */
    UART_DATA_LEN_8 = 3  /*!< Data length is 8 bits */
} uart_databits_t;

/*!
 *  @brief    UART stop bit settings
 *
 *  This enumeration defines the UART stop bits.
 */
typedef enum {
    UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */
    UART_STOP_ONE = 1,         /*!< 1 stop bit */
    UART_STOP_ONE_D_FIVE = 2,  /*!< 1.5 stop bit */
    UART_STOP_TWO = 3          /*!< 2 stop bits */
} uart_stopbits_t;

/*!
 *  @brief    UART parity type settings
 *
 *  This enumeration defines the UART parity types.
 */
typedef enum {
    UART_PAR_NONE = 0, /*!< No parity */
    UART_PAR_ODD = 1,  /*!< Parity bit is odd */
    UART_PAR_EVEN = 2, /*!< Parity bit is even */
} uart_parity_t;

enum uart_event_type {
    UART_EVENT_TX_END,
    UART_EVENT_TX_FIFO,
    UART_EVENT_RX_END,
    UART_EVENT_RX_FIFO,
    UART_EVENT_RTO,
    UART_EVENT_PCE,
    UART_EVENT_TX_FER,
    UART_EVENT_RX_FER,
    UART_EVENT_UNKNOWN
};

enum uart_it_type {
    UART_TX_END_IT = 1 << 0,
    UART_RX_END_IT = 1 << 1,
    UART_TX_FIFO_IT = 1 << 2,
    UART_RX_FIFO_IT = 1 << 3,
    UART_RTO_IT = 1 << 4,
    UART_PCE_IT = 1 << 5,
    UART_TX_FER_IT = 1 << 6,
    UART_RX_FER_IT = 1 << 7,
    UART_ALL_IT = 1 << 8
};

typedef struct
{
    uint32_t baudrate;
    uart_databits_t databits;
    uart_stopbits_t stopbits;
    uart_parity_t parity;
} uart_param_cfg_t;

typedef struct uart_device {
    struct device parent;
    uint8_t id;
    uint32_t baudrate;
    uart_databits_t databits;
    uart_stopbits_t stopbits;
    uart_parity_t parity;
    uint8_t fifo_threshold;
    void *tx_dma;
    void *rx_dma;
} uart_device_t;

#define UART_DEV(dev) ((uart_device_t *)dev)

int uart_register(enum uart_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_usb.h
================================================
/**
 * @file hal_usb.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_USB__H__
#define __HAL_USB__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "ring_buffer.h"
#include "drv_device.h"
#include "bl702_config.h"

#define DEVICE_CTRL_USB_DC_SET_ACK            0X10
#define DEVICE_CTRL_USB_DC_ENUM_ON            0X11
#define DEVICE_CTRL_USB_DC_ENUM_OFF           0X12
#define DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT 0x13
#define DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT 0x14
#define DEVICE_CTRL_USB_DC_SET_TX_DMA         0x15
#define DEVICE_CTRL_USB_DC_SET_RX_DMA         0x16

enum usb_index_type {
#ifdef BSP_USING_USB
    USB_INDEX,
#endif
    USB_MAX_INDEX
};

/**
 * USB endpoint Transfer Type mask.
 */
#define USBD_EP_TYPE_CTRL 0
#define USBD_EP_TYPE_ISOC 1
#define USBD_EP_TYPE_BULK 2
#define USBD_EP_TYPE_INTR 3
#define USBD_EP_TYPE_MASK 3

/**
 * USB endpoint direction and number.
 */
#define USB_EP_DIR_MASK 0x80U
#define USB_EP_DIR_IN   0x80U
#define USB_EP_DIR_OUT  0x00U

#define USB_EP_OUT_MSK 0x7FU
#define USB_EP_IN_MSK  0x80U

/** Get endpoint index (number) from endpoint address */
#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK)
/** Get direction from endpoint address */
#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK)
/** Get endpoint address from endpoint index and direction */
#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK))
/** True if the endpoint is an IN endpoint */
#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN)
/** True if the endpoint is an OUT endpoint */
#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT)

#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK)
#define USB_SET_EP_IN(ep)  (ep | USB_EP_IN_MSK)

#define USB_OUT_EP_NUM 8
#define USB_IN_EP_NUM  8

#define USB_CTRL_EP_MPS        64 /**< maximum packet size (MPS) for EP 0 */
#define USB_FS_MAX_PACKET_SIZE 64 /**< full speed MPS for bulk EP */

/* Default USB control EP, always 0 and 0x80 */
#define USB_CONTROL_OUT_EP0 0
#define USB_CONTROL_IN_EP0  0x80

#define USB_DC_EP_TYPE_CTRL 0x5 /*0*/
#define USB_DC_EP_TYPE_ISOC 0x2 /*1*/
#define USB_DC_EP_TYPE_BULK 0x4 /*2*/
#define USB_DC_EP_TYPE_INTR 0x0 /*3*/

#define USB_DC_EP1_IN_DR  (0x4000D800 + 0x118)
#define USB_DC_EP1_OUT_DR (0x4000D800 + 0x11c)
#define USB_DC_EP2_IN_DR  (0x4000D800 + 0x128)
#define USB_DC_EP2_OUT_DR (0x4000D800 + 0x12c)
#define USB_DC_EP3_IN_DR  (0x4000D800 + 0x138)
#define USB_DC_EP3_OUT_DR (0x4000D800 + 0x13c)
#define USB_DC_EP4_IN_DR  (0x4000D800 + 0x148)
#define USB_DC_EP4_OUT_DR (0x4000D800 + 0x14c)
#define USB_DC_EP5_IN_DR  (0x4000D800 + 0x158)
#define USB_DC_EP5_OUT_DR (0x4000D800 + 0x15c)
#define USB_DC_EP6_IN_DR  (0x4000D800 + 0x168)
#define USB_DC_EP6_OUT_DR (0x4000D800 + 0x16c)
#define USB_DC_EP7_IN_DR  (0x4000D800 + 0x178)
#define USB_DC_EP7_OUT_DR (0x4000D800 + 0x17c)

enum usb_dc_event_type {
    /** USB error reported by the controller */
    USB_DC_EVENT_ERROR,
    /** USB reset */
    USB_DC_EVENT_RESET,
    /** Start of Frame received */
    USB_DC_EVENT_SOF,
    /** USB connection established, hardware enumeration is completed */
    USB_DC_EVENT_CONNECTED,
    /** USB configuration done */
    USB_DC_EVENT_CONFIGURED,
    /** USB connection suspended by the HOST */
    USB_DC_EVENT_SUSPEND,
    /** USB connection lost */
    USB_DC_EVENT_DISCONNECTED,
    /** USB connection resumed by the HOST */
    USB_DC_EVENT_RESUME,

    /** USB interface selected */
    USB_DC_EVENT_SET_INTERFACE,
    /** USB interface selected */
    USB_DC_EVENT_SET_REMOTE_WAKEUP,
    /** USB interface selected */
    USB_DC_EVENT_CLEAR_REMOTE_WAKEUP,
    /** Set Feature ENDPOINT_HALT received */
    USB_DC_EVENT_SET_HALT,
    /** Clear Feature ENDPOINT_HALT received */
    USB_DC_EVENT_CLEAR_HALT,
    /** setup packet received */
    USB_DC_EVENT_SETUP_NOTIFY,
    /** ep0 in packet received */
    USB_DC_EVENT_EP0_IN_NOTIFY,
    /** ep0 out packet received */
    USB_DC_EVENT_EP0_OUT_NOTIFY,
    /** ep in packet except ep0 received */
    USB_DC_EVENT_EP_IN_NOTIFY,
    /** ep out packet except ep0 received */
    USB_DC_EVENT_EP_OUT_NOTIFY,
    /** Initial USB connection status */
    USB_DC_EVENT_UNKNOWN
};

enum usb_dc_ep_it_type {
    USB_SOF_IT = 1 << 0,
    USB_EP1_DATA_IN_IT = 1 << 10,
    USB_EP1_DATA_OUT_IT = 1 << 11,
    USB_EP2_DATA_IN_IT = 1 << 12,
    USB_EP2_DATA_OUT_IT = 1 << 13,
    USB_EP3_DATA_IN_IT = 1 << 14,
    USB_EP3_DATA_OUT_IT = 1 << 15,
    USB_EP4_DATA_IN_IT = 1 << 16,
    USB_EP4_DATA_OUT_IT = 1 << 17,
    USB_EP5_DATA_IN_IT = 1 << 18,
    USB_EP5_DATA_OUT_IT = 1 << 19,
    USB_EP6_DATA_IN_IT = 1 << 20,
    USB_EP6_DATA_OUT_IT = 1 << 21,
    USB_EP7_DATA_IN_IT = 1 << 22,
    USB_EP7_DATA_OUT_IT = 1 << 23,
};

enum usb_error_type {
    USB_DC_OK = 0,
    USB_DC_EP_DIR_ERR = 1,
    USB_DC_EP_EN_ERR = 2,
    USB_DC_EP_TIMEOUT_ERR = 3,
    USB_DC_ADDR_ERR = 4,
    USB_DC_RB_SIZE_SMALL_ERR = 5,
    USB_DC_ZLP_ERR = 6,
};
/**
 * @brief USB Endpoint Configuration.
 *
 * Structure containing the USB endpoint configuration.
 */
struct usb_dc_ep_cfg {
    /** The number associated with the EP in the device
     *  configuration structure
     *       IN  EP = 0x80 | \
     *       OUT EP = 0x00 | \
     */
    uint8_t ep_addr;
    /** Endpoint max packet size */
    uint16_t ep_mps;
    /** Endpoint Transfer Type.
     * May be Bulk, Interrupt, Control or Isochronous
     */
    uint8_t ep_type;
};

/*
 * USB endpoint  structure.
 */
typedef struct
{
    uint8_t ep_ena;
    uint32_t is_stalled;
    struct usb_dc_ep_cfg ep_cfg;
} usb_dc_ep_state_t;

typedef struct usb_dc_device {
    struct device parent;
    uint8_t id;
    usb_dc_ep_state_t in_ep[8];  /*!< IN endpoint parameters             */
    usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters            */
    void *tx_dma;
    void *rx_dma;
} usb_dc_device_t;

int usb_dc_register(enum usb_index_type index, const char *name);

int usb_dc_set_dev_address(const uint8_t addr);
int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg);
int usb_dc_ep_close(const uint8_t ep);
int usb_dc_ep_set_stall(const uint8_t ep);
int usb_dc_ep_clear_stall(const uint8_t ep);
int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled);
int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes);
int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
#ifdef __cplusplus
}
#endif
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/inc/hal_wdt.h
================================================
/**
 * @file hal_wdt.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __HAL_WDT__H__
#define __HAL_WDT__H__

#ifdef __cplusplus
extern "C"{
#endif

#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"

#define DEVICE_CTRL_GET_WDT_COUNTER (0x10)
#define DEVICE_CTRL_RST_WDT_COUNTER (0x11)
#define DEVICE_CTRL_GET_RST_STATUS  (0x12)
#define DEVICE_CTRL_CLR_RST_STATUS  (0x13)

enum wdt_index_type {
#ifdef BSP_USING_WDT
    WDT_INDEX,
#endif
    WDT_MAX_INDEX
};

enum wdt_event_type {
    WDT_EVENT,
    WDT_EVENT_UNKNOWN
};

typedef struct wdt_device {
    struct device parent;
    uint8_t id;
    uint32_t wdt_timeout;
} wdt_device_t;

#define WDT_DEV(dev) ((wdt_device_t *)dev)

int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);
int wdt_register(enum wdt_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_boot2.c
================================================
#include "hal_boot2.h"
#include "bl702_ef_ctrl.h"
#include "bl702_glb.h"
#include "bl702_hbn.h"
#include "bl702_xip_sflash.h"
#include "hal_flash.h"
#include "hal_gpio.h"
#include "hal_sec_hash.h"
#include "softcrc.h"
#include "tzc_sec_reg.h"

/**
 * @brief boot2 custom
 *
 * @param None
 * @return uint32
 */
uint32_t hal_boot2_custom(void) { return 0; }

/**
 * @brief get efuse Boot2 config
 *
 * @param g_efuse_cfg
 * @param
 * @param
 * @return None
 */
void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) {
  uint32_t tmp;
  uint32_t rootClk;
  uint8_t  hdiv = 0, bdiv = 0;

  /* save bclk fclk div and root clock sel */
  bdiv    = GLB_Get_BCLK_Div();
  hdiv    = GLB_Get_HCLK_Div();
  rootClk = BL_RD_REG(HBN_BASE, HBN_GLB);

  /* change root clock to rc32m for efuse operation */
  HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);

  /* Get sign and aes type*/
  EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted);
  /* Get hash:aes key slot 0 and slot1*/
  EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8);
  EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id);
  /* Get HBN check sign config */
  EF_Ctrl_Read_Sw_Usage(0, &tmp);
  efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01;

  /* restore bclk fclk div and root clock sel */
  GLB_Set_System_CLK_Div(hdiv, bdiv);
  BL_WR_REG(HBN_BASE, HBN_GLB, rootClk);
  __NOP();
  __NOP();
  __NOP();
  __NOP();
}
/**
 * @brief reset sec eng clock
 *
 * @return
 */
void hal_boot2_reset_sec_eng(void) { GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC); }

/**
 * @brief system soft reset
 *
 * @return
 */
void hal_boot2_sw_system_reset(void) { GLB_SW_System_Reset(); }

/**
 * @brief
 *
 * @param flag
 * @param
 * @param
 * @return
 */
void hal_boot2_set_psmode_status(uint32_t flag) { HBN_Set_Status_Flag(flag); }

/**
 * @brief
 *
 * @param
 * @param
 * @param
 * @return flag
 */
uint32_t hal_boot2_get_psmode_status(void) { return HBN_Get_Status_Flag(); }

/**
 * @brief
 *
 * @param
 * @param
 * @param
 * @return user define flag
 */
uint32_t hal_boot2_get_user_fw(void) { return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); }

/**
 * @brief clr user define flag
 *
 * @param
 * @param
 * @param
 * @return
 */
void hal_boot2_clr_user_fw(void) {
  uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET);
  *p          = 0;
}

/**
 * @brief hal_boot2_sboot_finish
 *
 * @return
 */
void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) {
  uint32_t tmp_val;

  tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);

  tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf);

  BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val);
}

/**
 * @brief hal_boot2_uart_gpio_init
 *
 * @return
 */
void hal_boot2_uart_gpio_init(void) {
  GLB_GPIO_Type gpios[] = {GPIO_PIN_14, GPIO_PIN_15};

  GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2);

  GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD); //  GPIO_FUN_UART1_TX
  GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD);
}

/**
 * @brief hal_boot2_pll_init
 *
 * @return
 */
void hal_boot2_debug_uart_gpio_init(void) {
  GLB_GPIO_Type gpios[] = {GPIO_PIN_17};

  GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1);

  GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
}

/**
 * @brief hal_boot2_debug_usb_port_init
 *
 * @return
 */
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void) {
  /* must do this , or usb can not be recognized */
  cpu_global_irq_disable();
  cpu_global_irq_enable();

  GLB_GPIO_Type gpios[] = {GPIO_PIN_7, GPIO_PIN_8};
  GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2);
}
#endif

/**
 * @brief hal_boot2_debug_uart_gpio_deinit
 *
 * @return
 */
void hal_boot2_debug_uart_gpio_deinit(void) {
  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
  GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}

/****************************************************************************/ /**
                                                                                * @brief  Check bootheader crc
                                                                                *
                                                                                * @param  data: bootheader data pointer
                                                                                *
                                                                                * @return boot_error_code type
                                                                                *
                                                                                *******************************************************************************/
static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) {
  uint32_t crc_pass = 0;
  uint32_t crc;

  if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) {
    // MSG("Crc ignored\r\n");
    crc_pass = 1;
  } else {
    crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32));

    if (header->crc32 == crc) {
      crc_pass = 1;
    }
  }
  return crc_pass;
}

/****************************************************************************/ /**
                                                                                * @brief  Check if the input public key is the same as  burned in the efuse
                                                                                *
                                                                                * @param  g_boot_img_cfg: Boot image config pointer
                                                                                * @param  data: Image data pointer
                                                                                *
                                                                                * @return boot_error_code type
                                                                                *
                                                                                *******************************************************************************/
int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) {
  struct hal_bootheader_t *header   = (struct hal_bootheader_t *)data;
  uint32_t                 crc_pass = 0;
  uint32_t                 i        = 0;
  uint32_t                *phash    = (uint32_t *)header->hash;

  crc_pass = hal_boot_check_bootheader(header);

  if (!crc_pass) {
    // MSG_ERR("bootheader crc error\r\n");
    // blsp_dump_data((uint8_t *)&crc, 4);
    return 0x0204;
  }

  if (header->bootCfg.bval.notLoadInBoot) {
    return 0x0202;
  }

  /* Get which CPU's img it is*/
  for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) {
    if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC, sizeof(header->magicCode))) {
      break;
    } else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC, sizeof(header->magicCode))) {
      break;
    }
  }

  if (i == HAL_BOOT2_CPU_MAX) {
    /* No cpu img magic match */
    // MSG_ERR("Magic code error\r\n");
    return 0x0203;
  }

  if (boot_img_cfg == NULL) {
    return 0;
  }

  boot_img_cfg->pk_src    = i;
  boot_img_cfg->img_valid = 0;

  /* Deal with pll config */

  /* Encrypt and sign */
  boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type;
  boot_img_cfg->basic_cfg.sign_type    = header->bootCfg.bval.sign;
  boot_img_cfg->basic_cfg.key_sel      = header->bootCfg.bval.key_sel;

  /* Xip relative */
  boot_img_cfg->basic_cfg.no_segment      = header->bootCfg.bval.no_segment;
  boot_img_cfg->cpu_cfg[0].cache_enable   = header->bootCfg.bval.cache_enable;
  boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock;
  // boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1;
  boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable;
  boot_img_cfg->basic_cfg.hash_ignore    = header->bootCfg.bval.hash_ignore;
  /* Firmware len*/
  boot_img_cfg->basic_cfg.img_len_cnt = header->img_segment_info.img_len;

  /* Boot entry and flash offset */
  boot_img_cfg->cpu_cfg[0].boot_entry        = header->bootEntry;
  boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset;

  boot_img_cfg->cpu_cfg[0].config_enable = 1;
  boot_img_cfg->cpu_cfg[0].halt_cpu      = 0;

  // MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type);

  /* Check encrypt and sign match*/
  if (g_efuse_cfg.encrypted[i] != 0) {
    if (boot_img_cfg->basic_cfg.encrypt_type == 0) {
      // MSG_ERR("Encrypt not fit\r\n");
      return 0x0205;
    }
  }

  if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) {
    // MSG_ERR("sign not fit\r\n");
    boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i];
    return 0x0206;
  }

  if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) {
    /* In HBN Mode, if user select to ignore hash and sign*/
    boot_img_cfg->basic_cfg.hash_ignore = 1;
  } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || g_efuse_cfg.sign[i] != 0) {
    /* If signed or user not really want to ignore, hash can't be ignored*/
    boot_img_cfg->basic_cfg.hash_ignore = 0;
  }

  if (g_user_hash_ignored) {
    boot_img_cfg->basic_cfg.hash_ignore = 1;
  }

  ARCH_MemCpy_Fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash));

  if (boot_img_cfg->basic_cfg.img_len_cnt == 0) {
    return 0x0207;
  }

  return 0;
}

void ATTR_TCM_SECTION hal_boot2_clean_cache(void) {
  /* no need clean again since hal_boot2_set_cache will also clean
    unused way,and bl702 no data cache except psram */
}

BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) {
  return flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, boot_img_cfg->cpu_cfg[0].cache_way_dis, boot_img_cfg->basic_cfg.group_image_offset);
}

/****************************************************************************/ /**
                                                                                * @brief  get the ram image name and count
                                                                                *
                                                                                * @param  img_name: ram image name in partition
                                                                                * @param  ram_img_cnt: ram image count that support boot from flash
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) { *ram_img_cnt = 0; }

/****************************************************************************/ /**
                                                                                * @brief  get the ram image info
                                                                                *
                                                                                * @param  data: bootheader information
                                                                                * @param  image_offset: ram image offset in flash(from of bootheader)
                                                                                * @param  img_len: ram image length
                                                                                * @param  hash: pointer to hash pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) { *img_len = 0; }

/****************************************************************************/ /**
                                                                                * @brief  release other cpu to boot up
                                                                                *
                                                                                * @param  core: core number
                                                                                * @param  boot_addr: boot address
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) {}

/****************************************************************************/ /**
                                                                                * @brief  get xip address according to flash addr
                                                                                *
                                                                                * @param  flash_addr: flash address
                                                                                *
                                                                                * @return XIP Address
                                                                                *
                                                                                *******************************************************************************/
uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) {
  uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset();
  if (flash_addr >= img_offset) {
    return BL702_FLASH_XIP_BASE + (flash_addr - img_offset);
  } else {
    return 0;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  get multi-group count
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return 1 for multi-group 0 for not
                                                                                *
                                                                                *******************************************************************************/
uint32_t hal_boot2_get_grp_count(void) { return 1; }

/****************************************************************************/ /**
                                                                                * @brief  get cpu count
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return 1 for multi-group 0 for not
                                                                                *
                                                                                *******************************************************************************/
uint32_t hal_boot2_get_cpu_count(void) { return 1; }

/****************************************************************************/ /**
                                                                                * @brief  get cpu count
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return 1 for multi-group 0 for not
                                                                                *
                                                                                *******************************************************************************/
uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) { return HAL_BOOT2_SP_FLAG; }

/****************************************************************************/ /**
                                                                                * @brief  get boot header offset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return bootheader offset
                                                                                *
                                                                                *******************************************************************************/
uint32_t hal_boot2_get_bootheader_offset(void) { return 0x00; }


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_clock.c
================================================
/**
 * @file hal_clock.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#include "hal_clock.h"
#include "bl702_glb.h"
#include "bl702_pwm.h"
#include "bl702_timer.h"

#if XTAL_TYPE != EXTERNAL_XTAL_32M
static void internal_rc32m_init(void) {
  uint32_t tmpVal;
  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
  BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);

  for (uint32_t i = 0; i < 20000; i++) {
    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
    if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
      break;
  }
}
#endif

static uint32_t mtimer_get_clk_src_div(void) { return (system_clock_get(SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1); }

static void peripheral_clock_gate_all() {
  uint32_t tmpVal;
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  // tmpVal &= (~(1 << BL_AHB_SLAVE1_GPIP));
  // tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC_DBG));
  // tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ1));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ2));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_DMA));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_EMAC));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_UART0));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_UART1));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_SPI));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_I2C));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_PWM));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_TMR));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_IRR));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_CKS));
  tmpVal &= (~(1 << 24)); // QDEC0
  tmpVal &= (~(1 << 25)); // QDEC1
  tmpVal &= (~(1 << 26)); // QDEC2/I2S
  tmpVal &= (~(1 << 27)); // KYS
  tmpVal &= (~(1 << BL_AHB_SLAVE1_USB));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_CAM));
  tmpVal &= (~(1 << BL_AHB_SLAVE1_MJPEG));
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}

void system_clock_init(void) {
#if XTAL_TYPE != EXTERNAL_XTAL_32M
  internal_rc32m_init();
  AON_Power_Off_XTAL();
#endif
  /*select root clock*/
  GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M
  /* fix 57.6M */
  SystemCoreClockSet(57.6 * 1000 * 1000);
#endif
  /*set fclk/hclk and bclk clock*/
  GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
  /* Set MTimer the same frequency as SystemCoreClock */
  GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#ifndef FAST_WAKEUP
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
  PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
#endif
#endif
#if XTAL_32K_TYPE == INTERNAL_RC_32K
  HBN_32K_Sel(HBN_32K_RC);
  HBN_Power_Off_Xtal_32K();
#else
  HBN_Power_On_Xtal_32K();
  HBN_32K_Sel(HBN_32K_XTAL);
#endif
#if XTAL_TYPE == EXTERNAL_XTAL_32M
  HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
#else
  HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
#endif
}

void peripheral_clock_init(void) {
  uint32_t tmpVal = 0;

  peripheral_clock_gate_all();

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
#if defined(BSP_USING_UART0)
  tmpVal |= (1 << BL_AHB_SLAVE1_UART0);
#endif
#if defined(BSP_USING_UART1)
  tmpVal |= (1 << BL_AHB_SLAVE1_UART1);
#endif
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
  GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, BSP_UART_CLOCK_DIV);
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
  GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV);
#else
#error "please select correct uart clock source"
#endif
#endif

#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
  tmpVal |= (1 << BL_AHB_SLAVE1_I2C);
  GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV);
#else
#error "please select correct i2c clock source"
#endif
#endif

#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
  tmpVal |= (1 << BL_AHB_SLAVE1_SPI);
  GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV);
#else
#error "please select correct spi clock source"
#endif
#endif

#if defined(BSP_USING_TIMER0)
  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
  /* Configure timer clock source */
  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_FCLK);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);

  /* Configure timer clock division */
  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  /* Configure timer clock source */
  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_XTAL);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);

  /* Configure timer clock division */
  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
  /* Configure timer clock source */
  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_32K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);

  /* Configure timer clock division */
  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
  /* Configure timer clock source */
  uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp          = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_1K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);

  /* Configure timer clock division */
  tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#else
#error "please select correct timer0 clock source"
#endif
#endif

#if defined(BSP_USING_TIMER1)
  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
  /* Configure timer clock source */
  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_FCLK);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);

  /* Configure timer clock division */
  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  /* Configure timer clock source */
  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_XTAL);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);

  /* Configure timer clock division */
  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
  /* Configure timer clock source */
  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_32K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);

  /* Configure timer clock division */
  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
  /* Configure timer clock source */
  uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmp1          = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_1K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);

  /* Configure timer clock division */
  tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#else
#error "please select correct timer1 clock source"
#endif
#endif

#if defined(BSP_USING_WDT)
  tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

#if BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
  /* Configure watchdog timer clock source */
  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_FCLK);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);

  /* Configure watchdog timer clock division */
  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  /* Configure watchdog timer clock source */
  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_XTAL);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);

  /* Configure watchdog timer clock division */
  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
  /* Configure watchdog timer clock source */
  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_32K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);

  /* Configure watchdog timer clock division */
  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
  /* Configure watchdog timer clock source */
  uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmpwdt          = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_1K);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);

  /* Configure watchdog timer clock division */
  tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#else
#error "please select correct watchdog timer clock source"
#endif
#endif

#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
  tmpVal |= (1 << BL_AHB_SLAVE1_PWM);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

  uint32_t timeoutCnt = 160 * 1000;
  uint32_t tmp_pwm;
  uint32_t PWMx;
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK

  for (int i = 0; i < 5; i++) {
    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i) * 0x20;
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));

    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return;
      }
    }
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_32K);
    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
    /* Config pwm division */
    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
  }
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK

  for (int i = 0; i < 5; i++) {
    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i) * 0x20;
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));

    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return;
      }
    }
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_BCLK);
    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
    /* Config pwm division */
    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
  }
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK

  for (int i = 0; i < 5; i++) {
    PWMx    = PWM_BASE + PWM_CHANNEL_OFFSET + (i) * 0x20;
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));

    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return;
      }
    }
    tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
    tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
    BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
    /* Config pwm division */
    BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV + 1);
  }
#else
#error "please select correct pwm clock source"
#endif
#endif

#if defined(BSP_USING_IR)
  tmpVal |= (1 << BL_AHB_SLAVE1_IRR);
  GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV);
#endif

#if defined(BSP_USING_I2S0)
  tmpVal |= (1 << BL_AHB_SLAVE1_I2S);
  GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
#endif

#if defined(BSP_USING_ADC0)
  tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
  GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV);
#else
#error "please select correct adc clock source"
#endif
#endif

#if defined(BSP_USING_DAC0)
  tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
  GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV + 1);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV + 1);
#else
#error "please select correct dac clock source"
#endif
#endif

#if defined(BSP_USING_CAM0)
  tmpVal |= (1 << BL_AHB_SLAVE1_CAM);
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
  GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
  GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
  GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#else
#error "please select correct camera clock source"
#endif
#endif

#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN)
#ifdef BSP_USING_KEYSCAN
  tmpVal |= (1 << 27);
#endif
#if defined(BSP_USING_QDEC0)
  tmpVal |= (1 << 24);
#endif
#if defined(BSP_USING_QDEC1)
  tmpVal |= (1 << 25);
#endif
#if defined(BSP_USING_QDEC2)
  tmpVal |= (1 << 26);
#endif
#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
  GLB_Set_QDEC_CLK(GLB_QDEC_CLK_F32K, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#elif BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
  GLB_Set_QDEC_CLK(GLB_QDEC_CLK_XCLK, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#else
#error "please select correct qdec or keyscan clock source"
#endif
#endif

#if defined(BSP_USING_USB)
  tmpVal |= (1 << BL_AHB_SLAVE1_USB);
  GLB_Set_USB_CLK(1);
#endif

#if defined(BSP_USING_DMA)
  tmpVal |= (1 << BL_AHB_SLAVE1_DMA);
#endif

  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}

uint32_t system_clock_get(enum system_clock_type type) {
  switch (type) {
  case SYSTEM_CLOCK_ROOT_CLOCK:
    if (GLB_Get_Root_CLK_Sel() == 0) {
      return 32 * 1000 * 1000;
    } else if (GLB_Get_Root_CLK_Sel() == 1)
      return 32 * 1000 * 1000;
    else {
      uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
      tmpVal          = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
      if (tmpVal == 0) {
        return 57.6 * 1000 * 1000;
      } else if (tmpVal == 1) {
        return 96 * 1000 * 1000;
      } else if (tmpVal == 2) {
        return 144 * 1000 * 1000;
      } else {
        return 0;
      }
    }
  case SYSTEM_CLOCK_FCLK:
    return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1);

  case SYSTEM_CLOCK_BCLK:
    return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1) / (GLB_Get_BCLK_Div() + 1);

  case SYSTEM_CLOCK_XCLK:
    return 32000000;
  case SYSTEM_CLOCK_32K_CLK:
    return 32000;
  case SYSTEM_CLOCK_AUPLL:
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
    if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
      return 12288000;
    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
      return 11289600;
    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ) {
      return 5644800;
    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ) {
      return 24576000;
    } else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
      return 24000000;
    }
#endif
  default:
    break;
  }

  return 0;
}

uint32_t peripheral_clock_get(enum peripheral_clock_type type) {
  uint32_t tmpVal;
  uint32_t div;

  switch (type) {
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
  case PERIPHERAL_CLOCK_UART:
    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);

    div = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
    div = BL_GET_REG_BITS_VAL(div, GLB_UART_CLK_DIV);
    if (tmpVal == HBN_UART_CLK_FCLK) {
      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
    } else if (tmpVal == HBN_UART_CLK_96M) {
      return 96000000 / (div + 1);
    }
#endif
#if defined(BSP_USING_SPI0)
  case PERIPHERAL_CLOCK_SPI:
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
    return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#if defined(BSP_USING_I2C0)
  case PERIPHERAL_CLOCK_I2C:
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
    return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#if defined(BSP_USING_I2S0)
  case PERIPHERAL_CLOCK_I2S:
    return system_clock_get(SYSTEM_CLOCK_AUPLL);
#endif
#if defined(BSP_USING_ADC0)
  case PERIPHERAL_CLOCK_ADC:
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
    if (tmpVal == GLB_ADC_CLK_AUDIO_PLL) {
      return system_clock_get(SYSTEM_CLOCK_AUPLL) / (div + 1);
    } else if (tmpVal == GLB_ADC_CLK_XCLK) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
    }
#endif
#if defined(BSP_USING_DAC0)
  case PERIPHERAL_CLOCK_DAC:
    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
    if (tmpVal == GLB_DAC_CLK_AUDIO_PLL) {
      return system_clock_get(SYSTEM_CLOCK_AUPLL) / div;
    } else if (tmpVal == GLB_DAC_CLK_XCLK) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
    }
#endif
#if defined(BSP_USING_TIMER0)
  case PERIPHERAL_CLOCK_TIMER0:
    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1);

    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
    div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR2);
    if (tmpVal == TIMER_CLKSRC_FCLK) {
      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_32K) {
      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_1K) {
      return 1000 / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
    }
#endif
#if defined(BSP_USING_TIMER1)
  case PERIPHERAL_CLOCK_TIMER1:
    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2);

    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
    div = BL_GET_REG_BITS_VAL(div, TIMER_TCDR3);
    if (tmpVal == TIMER_CLKSRC_FCLK) {
      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_32K) {
      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_1K) {
      return 1000 / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
    }
#endif
#if defined(BSP_USING_WDT)
  case PERIPHERAL_CLOCK_WDT:
    tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT);

    div = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
    div = BL_GET_REG_BITS_VAL(div, TIMER_WCDR);
    if (tmpVal == TIMER_CLKSRC_FCLK) {
      return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_32K) {
      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_1K) {
      return 1000 / (div + 1);
    } else if (tmpVal == TIMER_CLKSRC_XTAL) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
    }
#endif
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4)
  case PERIPHERAL_CLOCK_PWM:
    tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
    div    = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
    if (tmpVal == PWM_CLK_XCLK) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / div;
    } else if (tmpVal == PWM_CLK_BCLK) {
      return system_clock_get(SYSTEM_CLOCK_BCLK) / div;
    } else if (tmpVal == PWM_CLK_32K) {
      return system_clock_get(SYSTEM_CLOCK_32K_CLK) / div;
    }
#endif
#if defined(BSP_USING_CAM)
  case PERIPHERAL_CLOCK_CAM:
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
    div    = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);

    if (tmpVal == GLB_CAM_CLK_XCLK) {
      return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
    } else if (tmpVal == GLB_CAM_CLK_DLL96M) {
      return 96000000 / (div + 1);
    }
#endif
  default:

    break;
  }

  (void)(tmpVal);
  (void)(div);
  return 0;
}

void system_mtimer_clock_init(void) { GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); }

void system_mtimer_clock_reinit(void) {
  /* reinit clock to 10M */
  GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_common.c
================================================
/**
 * @file hal_common.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_common.h"
#include "bl702_ef_ctrl.h"
#include "bl702_l1c.h"
#include "bl702_romdriver.h"
#include "bl702_sec_eng.h"
#include "hbn_reg.h"

volatile uint32_t nesting = 0;

void ATTR_TCM_SECTION cpu_global_irq_enable(void) {
  nesting--;
  if (nesting == 0) {
    __enable_irq();
  }
}

void ATTR_TCM_SECTION cpu_global_irq_disable(void) {
  __disable_irq();
  nesting++;
}

void hal_por_reset(void) { RomDriver_GLB_SW_POR_Reset(); }

void hal_system_reset(void) { RomDriver_GLB_SW_System_Reset(); }

void hal_cpu_reset(void) { RomDriver_GLB_SW_CPU_Reset(); }

void hal_get_chip_id(uint8_t chip_id[8]) { EF_Ctrl_Read_MAC_Address(chip_id); }

void hal_enter_usb_iap(void) {
  BL_WR_WORD(HBN_BASE + HBN_RSV0_OFFSET, 0x00425355); //"\0BSU"

  arch_delay_ms(1000);
  RomDriver_GLB_SW_POR_Reset();
}

void ATTR_TCM_SECTION hal_jump2app(uint32_t flash_offset) {
  /*flash_offset from 48K to 3.98M*/
  if ((flash_offset >= 0xc000) && (flash_offset < (0x400000 - 20 * 1024))) {
    void (*app_main)(void) = (void (*)(void))0x23000000;
    BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
    L1C_Cache_Flush_Ext();
    app_main();
  } else {
    while (1) {
    }
  }
}

int hal_get_trng_seed(void) {
  uint32_t seed[8];
  uint32_t tmpVal;
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  tmpVal |= (1 << BL_AHB_SLAVE1_SEC);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

  Sec_Eng_Trng_Enable();
  Sec_Eng_Trng_Read((uint8_t *)seed);
  Sec_Eng_Trng_Disable();
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

  return seed[0];
}

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_dma.c
================================================
/**
 * @file hal_dma.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_dma.h"
#include "bl702_dma.h"

#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch) * 0x100)

static const uint32_t dma_channel_base[][8] = {
    {
     DMA_CHANNEL_BASE(DMA_BASE, 0),
     DMA_CHANNEL_BASE(DMA_BASE, 1),
     DMA_CHANNEL_BASE(DMA_BASE, 2),
     DMA_CHANNEL_BASE(DMA_BASE, 3),
     DMA_CHANNEL_BASE(DMA_BASE, 4),
     DMA_CHANNEL_BASE(DMA_BASE, 5),
     DMA_CHANNEL_BASE(DMA_BASE, 6),
     DMA_CHANNEL_BASE(DMA_BASE, 7),
     }
};

static void DMA0_IRQ(void);

static dma_device_t dmax_device[DMA_MAX_INDEX] = {
#ifdef BSP_USING_DMA0_CH0
    DMA0_CH0_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH1
    DMA0_CH1_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH2
    DMA0_CH2_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH3
    DMA0_CH3_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH4
    DMA0_CH4_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH5
    DMA0_CH5_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH6
    DMA0_CH6_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH7
    DMA0_CH7_CONFIG,
#endif
};
/**
 * @brief
 *
 * @param dev
 * @param oflag
 * @return int
 */
int dma_open(struct device *dev, uint16_t oflag) {
  dma_device_t        *dma_device = (dma_device_t *)dev;
  DMA_Channel_Cfg_Type chCfg      = {0};

  /* Disable all interrupt */
  DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
  CPU_Interrupt_Disable(DMA_ALL_IRQn);

  DMA_Disable();

  DMA_Channel_Disable(dma_device->ch);

  dma_device->intr     = 0;
  chCfg.ch             = dma_device->ch;
  chCfg.dir            = dma_device->direction;
  chCfg.srcPeriph      = dma_device->src_req;
  chCfg.dstPeriph      = dma_device->dst_req;
  chCfg.srcAddrInc     = dma_device->src_addr_inc;
  chCfg.destAddrInc    = dma_device->dst_addr_inc;
  chCfg.srcBurstSize   = dma_device->src_burst_size;
  chCfg.dstBurstSize   = dma_device->dst_burst_size;
  chCfg.srcTransfWidth = dma_device->src_width;
  chCfg.dstTransfWidth = dma_device->dst_width;
  DMA_Channel_Init(&chCfg);

  DMA_Enable();

  Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
  /* Enable dma interrupt*/
  CPU_Interrupt_Enable(DMA_ALL_IRQn);
  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @param cmd
 * @param args
 * @return int
 */
int dma_control(struct device *dev, int cmd, void *args) {
  dma_device_t *dma_device = (dma_device_t *)dev;

  switch (cmd) {
  case DEVICE_CTRL_SET_INT:
    /* Dma interrupt configuration */
    DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
    DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
    dma_device->intr = 1;
    break;

  case DEVICE_CTRL_CLR_INT:
    /* Dma interrupt configuration */
    DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
    DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
    dma_device->intr = 0;
    break;

  case DEVICE_CTRL_GET_INT:
    break;

  case DEVICE_CTRL_CONFIG:
    break;

  case DEVICE_CTRL_DMA_CHANNEL_UPDATE:
    DMA_LLI_Update(dma_device->ch, (uint32_t)args);
    break;

  case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS:
    return DMA_Channel_Is_Busy(dma_device->ch);

  case DEVICE_CTRL_DMA_CHANNEL_START:
    DMA_Channel_Enable(dma_device->ch);
    break;

  case DEVICE_CTRL_DMA_CHANNEL_STOP:
    DMA_Channel_Disable(dma_device->ch);
    break;
  case DEVICE_CTRL_DMA_CONFIG_SI: {
    uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
    tmpVal          = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)args) & 0x01);
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);

  } break;
  case DEVICE_CTRL_DMA_CONFIG_DI: {
    uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
    tmpVal          = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)args) & 0x01);
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);

  } break;
  default:
    break;
  }

  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @return int
 */
int dma_close(struct device *dev) {
  dma_device_t        *dma_device = (dma_device_t *)dev;
  DMA_Channel_Cfg_Type chCfg      = {0};

  DMA_Channel_Disable(dma_device->ch);
  DMA_Channel_Init(&chCfg);
  dma_device->intr = 0;
  return 0;
}

int dma_register(enum dma_index_type index, const char *name) {
  struct device *dev;

  if (DMA_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev = &(dmax_device[index].parent);

  dev->open    = dma_open;
  dev->close   = dma_close;
  dev->control = dma_control;
  // dev->write = dma_write;
  // dev->read = dma_read;

  dev->type   = DEVICE_CLASS_DMA;
  dev->handle = NULL;

  return device_register(dev, name);
}

/**
 * @brief
 *
 * @param dev
 * @param src_addr
 * @param dst_addr
 * @param transfer_size
 * @return int
 */
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) {
#ifdef BSP_USING_DMA
  uint32_t           malloc_count;
  uint32_t           remain_len;
  uint32_t           actual_transfer_len    = 0;
  uint32_t           actual_transfer_offset = 0;
  dma_control_data_t dma_ctrl_cfg;
  bool               intr = false;

  dma_device_t *dma_device = (dma_device_t *)dev;

  DMA_Channel_Disable(dma_device->ch);

  if (transfer_size == 0) {
    return 0;
  }

  switch (dma_device->src_width) {
  case DMA_TRANSFER_WIDTH_8BIT:
    actual_transfer_offset = 4095;
    actual_transfer_len    = transfer_size;
    break;
  case DMA_TRANSFER_WIDTH_16BIT:
    if (transfer_size % 2) {
      return -1;
    }
    actual_transfer_offset = 4095 << 1;
    actual_transfer_len    = transfer_size >> 1;
    break;
  case DMA_TRANSFER_WIDTH_32BIT:
    if (transfer_size % 4) {
      return -1;
    }

    actual_transfer_offset = 4095 << 2;
    actual_transfer_len    = transfer_size >> 2;
    break;

  default:
    return -3;
    break;
  }

  dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
  intr         = dma_device->intr;

  malloc_count = actual_transfer_len / 4095;
  remain_len   = actual_transfer_len % 4095;

  if (remain_len) {
    malloc_count++;
  }

  dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);

  if (dma_device->lli_cfg) {
    dma_ctrl_cfg.bits.TransferSize = 4095;
    dma_ctrl_cfg.bits.I            = 0;
    /*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
    for (uint32_t i = 0; i < malloc_count; i++) {
      dma_device->lli_cfg[i].src_addr = src_addr;
      dma_device->lli_cfg[i].dst_addr = dst_addr;
      dma_device->lli_cfg[i].nextlli  = 0;

      if (dma_ctrl_cfg.bits.SI) {
        src_addr += actual_transfer_offset;
      }

      if (dma_ctrl_cfg.bits.DI) {
        dst_addr += actual_transfer_offset;
      }

      if (i == malloc_count - 1) {
        if (remain_len) {
          dma_ctrl_cfg.bits.TransferSize = remain_len;
        }
        dma_ctrl_cfg.bits.I = intr;

        if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
          dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
        }
      }

      if (i) {
        dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
      }

      dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
    }
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli);
    BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD);
  } else {
    return -2;
  }
#endif
  return 0;
}

/**
 * @brief
 *
 * @param handle
 */
void dma_channel_isr(dma_device_t *handle) {
  uint32_t tmpVal;
  uint32_t intClr;

  /* Get DMA register */
  uint32_t DMAChs = DMA_BASE;

  if (!handle->parent.callback) {
    return;
  }

  tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
  if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) {
    /* Clear interrupt */
    tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
    intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
    intClr |= (1 << handle->ch);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
    BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
    handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED);
  }

  tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
  if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) {
    /*Clear interrupt */
    tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
    intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
    intClr |= (1 << handle->ch);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
    BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
    handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
  }
}
/**
 * @brief
 *
 */
void DMA0_IRQ(void) {
  for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
    dma_channel_isr(&dmax_device[i]);
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_flash.c
================================================
/**
 * @file hal_flash.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_flash.h"
#include "bl702_glb.h"
#include "bl702_sf_cfg.h"
#include "bl702_sf_cfg_ext.h"
#include "bl702_xip_sflash.h"
#include "bl702_xip_sflash_ext.h"

static uint32_t           g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;

/**
 * @brief flash_get_jedecid
 *
 * @return BL_Err_Type
 */
uint32_t flash_get_jedecid(void) {
  uint32_t jid = 0;

  jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
  return jid;
}

/**
 * @brief flash_get_cfg
 *
 * @return BL_Err_Type
 */
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) {
  *cfg_addr = (uint8_t *)&g_flash_cfg;
  *len      = sizeof(SPI_Flash_Cfg_Type);

  return SUCCESS;
}

/**
 * @brief flash_set_qspi_enable
 *
 * @return BL_Err_Type
 */
static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) {
  if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
    SFlash_Qspi_Enable(p_flash_cfg);
  }

  return SUCCESS;
}

/**
 * @brief flash_set_l1c_wrap
 *
 * @return BL_Err_Type
 */
static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) {
  if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
    L1C_Set_Wrap(DISABLE);
  } else {
    L1C_Set_Wrap(ENABLE);
    if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
      SFlash_SetBurstWrap(p_flash_cfg);
    }
  }

  return SUCCESS;
}

/**
 * @brief flash_config_init
 *
 * @return BL_Err_Type
 */
static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) {
  BL_Err_Type ret    = ERROR;
  uint32_t    jid    = 0;
  uint32_t    offset = 0;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  XIP_SFlash_State_Save(p_flash_cfg, &offset);
  SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
  arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
  jid &= 0xFFFFFF;
  g_jedec_id = jid;
  ret        = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
  if (ret == SUCCESS) {
    p_flash_cfg->mid = (jid & 0xff);
  }

  /* Set flash controler from p_flash_cfg */
  flash_set_qspi_enable(p_flash_cfg);
  flash_set_l1c_wrap(p_flash_cfg);
  XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief multi flash adapter
 *
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_init(void) {
  BL_Err_Type ret       = ERROR;
  uint8_t     clkDelay  = 1;
  uint8_t     clkInvert = 1;
  uint32_t    jedec_id  = 0;

  cpu_global_irq_disable();
  L1C_Cache_Flush_Ext();
  SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
  L1C_Cache_Flush_Ext();
  cpu_global_irq_enable();
  if (g_flash_cfg.mid != 0xff) {
    return SUCCESS;
  }
  clkDelay           = g_flash_cfg.clkDelay;
  clkInvert          = g_flash_cfg.clkInvert;
  g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;

  ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
#if 0
    MSG("flash ID = %08x\r\n", jedec_id);
    bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg));
    if (ret != SUCCESS) {
        MSG("flash config init fail!\r\n");
    }
#endif
  g_flash_cfg.clkDelay  = clkDelay;
  g_flash_cfg.clkInvert = clkInvert;

  return ret;
}

/**
 * @brief read jedec id
 *
 * @param data
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data) {
  uint32_t jid = 0;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, (uint8_t *)&jid);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();
  jid &= 0xFFFFFF;
  arch_memcpy(data, (void *)&jid, 4);

  return SUCCESS;
}

/**
 * @brief read flash data via xip
 *
 * @param addr
 * @param data
 * @param len
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len) {
  cpu_global_irq_disable();
  L1C_Cache_Flush_Ext();
  XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
  L1C_Cache_Flush_Ext();
  cpu_global_irq_enable();

  return SUCCESS;
}

/**
 * @brief flash read data
 *
 * @param addr
 * @param data
 * @param len
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len) {
  BL_Err_Type ret = ERROR;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  ret = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief flash write data
 *
 * @param addr
 * @param data
 * @param len
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len) {
  BL_Err_Type ret = ERROR;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  ret = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief flash erase
 *
 * @param startaddr
 * @param endaddr
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len) {
  BL_Err_Type ret = ERROR;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  ret = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, startaddr + len - 1);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief flash write protect set
 *
 * @param protect
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_write_protect_set(SFlash_Protect_Kh25v40_Type protect) {
  BL_Err_Type ret = ERROR;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  ret = XIP_SFlash_KH25V40_Write_Protect_Need_Lock(&g_flash_cfg, protect);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief flash clear status register
 *
 * @param None
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_clear_status_register(void) {
  BL_Err_Type ret = ERROR;

  cpu_global_irq_disable();
  XIP_SFlash_Opt_Enter();
  ret = XIP_SFlash_Clear_Status_Register_Need_Lock(&g_flash_cfg);
  XIP_SFlash_Opt_Exit();
  cpu_global_irq_enable();

  return ret;
}

/**
 * @brief set flash cache
 *
 * @param cont_read
 * @param cache_enable
 * @param cache_way_disable
 * @param flash_offset
 * @return BL_Err_Type
 */
BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) {
  uint32_t    tmp[1];
  BL_Err_Type stat;

  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);

  XIP_SFlash_Opt_Enter();
  /* To make it simple, exit cont read anyway */
  SFlash_Reset_Continue_Read(&g_flash_cfg);

  if (g_flash_cfg.cReadSupport == 0) {
    cont_read = 0;
  }

  if (cont_read == 1) {
    stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));

    if (SUCCESS != stat) {
      XIP_SFlash_Opt_Exit();
      return ERROR;
    }
  }

  /* Set default value */
  L1C_Cache_Enable_Set(0xf);

  if (cache_enable) {
    SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
    SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
  }
  XIP_SFlash_Opt_Exit();

  return SUCCESS;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_gpio.c
================================================
/**
 * @file hal_gpio.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_gpio.h"
#include "bl702_glb.h"
#include "bl702_gpio.h"

static void GPIO_IRQ(void);

struct gpio_int_cfg_private {
  slist_t  list;
  uint32_t pin;
  void (*cbfun)(uint32_t pin);
};

static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);

/**
 * @brief
 *
 * @param pin
 * @param mode
 */
void gpio_set_mode(uint32_t pin, uint32_t mode) {
  GLB_GPIO_Cfg_Type gpio_cfg;

  gpio_cfg.gpioFun = GPIO_FUN_GPIO;
  gpio_cfg.gpioPin = pin;
  gpio_cfg.drive   = 3;
  gpio_cfg.smtCtrl = 1;

  switch (mode) {
  case GPIO_OUTPUT_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
    gpio_cfg.pullType = GPIO_PULL_NONE;
    break;

  case GPIO_OUTPUT_PP_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
    gpio_cfg.pullType = GPIO_PULL_UP;
    break;

  case GPIO_OUTPUT_PD_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
    gpio_cfg.pullType = GPIO_PULL_DOWN;
    break;

  case GPIO_INPUT_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
    gpio_cfg.pullType = GPIO_PULL_NONE;
    break;

  case GPIO_INPUT_PU_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
    gpio_cfg.pullType = GPIO_PULL_UP;
    break;

  case GPIO_INPUT_PD_MODE:
    gpio_cfg.gpioMode = GPIO_MODE_INPUT;
    gpio_cfg.pullType = GPIO_PULL_DOWN;
    break;
  case GPIO_HZ_MODE:
    GLB_GPIO_Set_HZ(pin);
  default:
    CPU_Interrupt_Disable(GPIO_INT0_IRQn);
    GLB_GPIO_IntMask(pin, MASK);

    gpio_cfg.gpioMode = GPIO_MODE_INPUT;

    if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_DOWN;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
    }

    else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_UP;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
    }

    else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_DOWN;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
    }

    else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_UP;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
    }

    else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_DOWN;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
    }

    else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_UP;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
    }

    else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_DOWN;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
    }

    else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) {
      gpio_cfg.pullType = GPIO_PULL_UP;
      GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
    }

    else {
      return;
    }

    break;
  }

  GLB_GPIO_Init(&gpio_cfg);
}
/**
 * @brief
 *
 * @param pin
 * @param value
 */
void gpio_write(uint32_t pin, uint32_t value) {
  uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);

  if (value) {
    tmp |= (1 << pin);
  } else {
    tmp &= ~(1 << pin);
  }

  BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
}
/**
 * @brief
 *
 * @param pin
 */
void gpio_toggle(uint32_t pin) {
  uint32_t tmp = BL_RD_REG(GLB_BASE, GLB_GPIO_OUTPUT);
  tmp ^= (1 << pin);
  BL_WR_REG(GLB_BASE, GLB_GPIO_OUTPUT, tmp);
}
/**
 * @brief
 *
 * @param pin
 * @return int
 */
int gpio_read(uint32_t pin) { return ((BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin)) ? 1 : 0); }
/**
 * @brief
 *
 * @param pin
 * @param cbFun
 */
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) {
  struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
  int_cfg->cbfun                       = cbfun;
  int_cfg->pin                         = pin;
  slist_add_tail(&gpio_int_head, &int_cfg->list);
  CPU_Interrupt_Disable(GPIO_INT0_IRQn);
  Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ);
  CPU_Interrupt_Enable(GPIO_INT0_IRQn);
}
/**
 * @brief
 *
 * @param pin
 * @param enabled
 */
void gpio_irq_enable(uint32_t pin, uint8_t enabled) {
  if (enabled) {
    GLB_GPIO_IntMask(pin, UNMASK);
  } else {
    GLB_GPIO_IntMask(pin, MASK);
  }
}

static void GPIO_IRQ(void) {
  slist_t *i;
  uint32_t timeOut = 0;
#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
  slist_for_each(i, &gpio_int_head) {
    struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list);

    if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) {
      int_cfg->cbfun(int_cfg->pin);
      GLB_GPIO_IntClear(int_cfg->pin, SET);
      /* timeout check */
      timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;

      do {
        timeOut--;
      } while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut);

      if (!timeOut) {
        // MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
      }

      GLB_GPIO_IntClear(int_cfg->pin, RESET);
    }
  }
}

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_i2c.c
================================================
/**
 * @file hal_i2c.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_i2c.h"
#include "bl702_glb.h"
#include "bl702_i2c.h"

static i2c_device_t i2cx_device[I2C_MAX_INDEX] = {
#ifdef BSP_USING_I2C0
    I2C0_CONFIG,
#endif
#ifdef BSP_USING_I2C1
    I2C1_CONFIG,
#endif
};
/**
 * @brief
 *
 * @param dev
 * @param oflag
 * @return int
 */
int i2c_open(struct device *dev, uint16_t oflag) {
  i2c_device_t *i2c_device = (i2c_device_t *)dev;

  if (i2c_device->mode == I2C_HW_MODE) {
    I2C_SetPrd(i2c_device->id, i2c_device->phase);
  }

  return 0;
}

/**
 * @brief
 *
 * @param index
 * @param name
 * @param flag
 * @return int
 */
int i2c_register(enum i2c_index_type index, const char *name) {
  struct device *dev;

  if (I2C_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev = &(i2cx_device[index].parent);

  dev->open    = i2c_open;
  dev->close   = NULL;
  dev->control = NULL;
  dev->write   = NULL;
  dev->read    = NULL;

  dev->type   = DEVICE_CLASS_I2C;
  dev->handle = NULL;

  return device_register(dev, name);
}
/**
 * @brief
 *
 * @param dev
 * @param msgs
 * @param num
 * @return uint32_t
 */
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num) {
  i2c_msg_t       *msg;
  I2C_Transfer_Cfg i2cCfg = {0};

  i2c_device_t *i2c_device = (i2c_device_t *)dev;

  if (i2c_device->mode == I2C_HW_MODE) {
    for (uint32_t i = 0; i < num; i++) {
      msg                  = &msgs[i];
      i2cCfg.slaveAddr     = msg->slaveaddr;
      i2cCfg.stopEveryByte = DISABLE;
      i2cCfg.subAddr       = msg->subaddr;
      i2cCfg.dataSize      = msg->len;
      i2cCfg.data          = msg->buf;

      if (msg->flags & SUB_ADDR_0BYTE) {
        i2cCfg.subAddrSize = 0;
      } else if (msg->flags & SUB_ADDR_1BYTE) {
        i2cCfg.subAddrSize = 1;
      } else if (msg->flags & SUB_ADDR_2BYTE) {
        i2cCfg.subAddrSize = 2;
      }

      if ((msg->flags & I2C_RW_MASK) == I2C_WR) {
        return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg);
      } else if ((msg->flags & I2C_RW_MASK) == I2C_RD) {
        return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg);
      }
    }
  } else {
  }

  return 0;
}

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_mtimer.c
================================================
/**
 * @file hal_mtimer.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_mtimer.h"
#include "bl702_glb.h"
#include "risc-v/Core/Include/clic.h"

static void (*systick_callback)(void);
static uint64_t next_compare_tick = 0;
static uint64_t current_set_ticks = 0;

static void Systick_Handler(void) {
  *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
  systick_callback();
  next_compare_tick += current_set_ticks;
}

/**
 * @brief
 *
 * @param time
 * @param interruptFun
 */
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) {
  CPU_Interrupt_Disable(MTIME_IRQn);

  uint32_t                 ulCurrentTimeHigh, ulCurrentTimeLow;
  volatile uint32_t *const pulTimeHigh = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
  volatile uint32_t *const pulTimeLow  = (volatile uint32_t *const)(CLIC_CTRL_ADDR + CLIC_MTIME);
  volatile uint32_t        ulHartId    = 0;

  current_set_ticks = ticks;
  systick_callback  = interruptfun;

  __asm volatile("csrr %0, mhartid" : "=r"(ulHartId));

  do {
    ulCurrentTimeHigh = *pulTimeHigh;
    ulCurrentTimeLow  = *pulTimeLow;
  } while (ulCurrentTimeHigh != *pulTimeHigh);

  next_compare_tick = (uint64_t)ulCurrentTimeHigh;
  next_compare_tick <<= 32ULL;
  next_compare_tick |= (uint64_t)ulCurrentTimeLow;
  next_compare_tick += (uint64_t)current_set_ticks;

  *(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;

  /* Prepare the time to use after the next tick interrupt. */
  next_compare_tick += (uint64_t)current_set_ticks;

  Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler);
  CPU_Interrupt_Enable(MTIME_IRQn);
}

/**
 * @brief
 *
 * @return uint64_t
 */
uint64_t mtimer_get_time_ms() { return mtimer_get_time_us() / 1000; }
/**
 * @brief
 *
 * @return uint64_t
 */
uint64_t mtimer_get_time_us() {
  uint32_t tmpValLow, tmpValHigh, tmpValHigh1;

  do {
    tmpValLow   = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
    tmpValHigh  = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
    tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
  } while (tmpValHigh != tmpValHigh1);

  return (((uint64_t)tmpValHigh << 32) + tmpValLow);
}
/**
 * @brief
 *
 * @param time
 */
void mtimer_delay_ms(uint32_t time) {
  uint64_t cnt       = 0;
  uint32_t clock     = SystemCoreClockGet();
  uint64_t startTime = mtimer_get_time_ms();

  while (mtimer_get_time_ms() - startTime < time) {
    cnt++;

    /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
    if (cnt > (time * (clock >> (10 + 5))) * 2) {
      break;
    }
  }
}
/**
 * @brief
 *
 * @param time
 */
void mtimer_delay_us(uint32_t time) {
  uint64_t cnt       = 0;
  uint32_t clock     = SystemCoreClockGet();
  uint64_t startTime = mtimer_get_time_us();

  while (mtimer_get_time_us() - startTime < time) {
    cnt++;

    /* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
    if (cnt > (time * (clock >> (10 + 5))) * 2) {
      break;
    }
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm.c
================================================
/**
 * @file hal_pm.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_pm.h"
#include "bl702_glb.h"
#include "bl702_sflash.h"
#include "hal_clock.h"
#include "hal_flash.h"
#include "hal_rtc.h"
#include "risc-v/Core/Include/clic.h"

/* Cache Way Disable, will get from l1c register */
uint8_t cacheWayDisable = 0;

/* PSRAM IO Configuration, will get from glb register */
uint32_t psramIoCfg = 0;

/* Flash offset value, will get from sf_ctrl register */
uint32_t flash_offset = 0;

SPI_Flash_Cfg_Type *flash_cfg;

#define PM_PDS_FLASH_POWER_OFF   1
#define PM_PDS_DLL_POWER_OFF     1
#define PM_PDS_PLL_POWER_OFF     1
#define PM_PDS_RF_POWER_OFF      1
#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V
#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V

void HBN_OUT0_IRQ(void);
void HBN_OUT1_IRQ(void);

/** @defgroup  Hal_Power_Global_Variables
 *
 *  @brief PDS level config
 *  @{
 */
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel0 = {
    .pdsCtl =
        {
                 .pdsStart                = 1,
                 .sleepForever            = 0,
                 .xtalForceOff            = 0,
                 .saveWifiState           = 0,
                 .dcdc18Off               = 1,
                 .bgSysOff                = 1,
                 .gpioIePuPd              = 1,
                 .puFlash                 = 0,
                 .clkOff                  = 1,
                 .memStby                 = 1,
                 .swPuFlash               = 1,
                 .isolation               = 1,
                 .waitXtalRdy             = 0,
                 .pdsPwrOff               = 1,
                 .xtalOff                 = 0,
                 .socEnbForceOn           = 1,
                 .pdsRstSocEn             = 0,
                 .pdsRC32mOn              = 0,
                 .pdsLdoVselEn            = 0,
                 .pdsRamLowPowerWithClkEn = 1,
                 .cpu0WfiMask             = 0,
                 .ldo11Off                = 1,
                 .pdsForceRamClkEn        = 0,
                 .pdsLdoVol               = 0xA,
                 .pdsCtlRfSel             = 3,
                 .pdsCtlPllSel            = 0,
                 },
    .pdsCtl2 =
        {
                 .forceCpuPwrOff  = 0,
                 .forceBzPwrOff   = 0,
                 .forceUsbPwrOff  = 0,
                 .forceCpuIsoEn   = 0,
                 .forceBzIsoEn    = 0,
                 .forceUsbIsoEn   = 0,
                 .forceCpuPdsRst  = 0,
                 .forceBzPdsRst   = 0,
                 .forceUsbPdsRst  = 0,
                 .forceCpuMemStby = 0,
                 .forceBzMemStby  = 0,
                 .forceUsbMemStby = 0,
                 .forceCpuGateClk = 0,
                 .forceBzGateClk  = 0,
                 .forceUsbGateClk = 0,
                 },
    .pdsCtl3 =
        {
                 .forceMiscPwrOff  = 0,
                 .forceBlePwrOff   = 0,
                 .forceBleIsoEn    = 0,
                 .forceMiscPdsRst  = 0,
                 .forceBlePdsRst   = 0,
                 .forceMiscMemStby = 0,
                 .forceBleMemStby  = 0,
                 .forceMiscGateClk = 0,
                 .forceBleGateClk  = 0,
                 .CpuIsoEn         = 0,
                 .BzIsoEn          = 0,
                 .BleIsoEn         = 1,
                 .UsbIsoEn         = 0,
                 .MiscIsoEn        = 0,
                 },
    .pdsCtl4 = {
                 .cpuPwrOff     = 0,
                 .cpuRst        = 0,
                 .cpuMemStby    = 1,
                 .cpuGateClk    = 1,
                 .BzPwrOff      = 0,
                 .BzRst         = 0,
                 .BzMemStby     = 1,
                 .BzGateClk     = 1,
                 .BlePwrOff     = 1,
                 .BleRst        = 1,
                 .BleMemStby    = 1,
                 .BleGateClk    = 1,
                 .UsbPwrOff     = 0,
                 .UsbRst        = 0,
                 .UsbMemStby    = 1,
                 .UsbGateClk    = 1,
                 .MiscPwrOff    = 0,
                 .MiscRst       = 0,
                 .MiscMemStby   = 1,
                 .MiscGateClk   = 1,
                 .MiscAnaPwrOff = 1,
                 .MiscDigPwrOff = 1,
                 }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = {
    .pdsCtl =
        {
                 .pdsStart                = 1,
                 .sleepForever            = 0,
                 .xtalForceOff            = 0,
                 .saveWifiState           = 0,
                 .dcdc18Off               = 1,
                 .bgSysOff                = 1,
                 .gpioIePuPd              = 1,
                 .puFlash                 = 0,
                 .clkOff                  = 1,
                 .memStby                 = 1,
                 .swPuFlash               = 1,
                 .isolation               = 1,
                 .waitXtalRdy             = 0,
                 .pdsPwrOff               = 1,
                 .xtalOff                 = 0,
                 .socEnbForceOn           = 1,
                 .pdsRstSocEn             = 0,
                 .pdsRC32mOn              = 0,
                 .pdsLdoVselEn            = 0,
                 .pdsRamLowPowerWithClkEn = 1,
                 .cpu0WfiMask             = 0,
                 .ldo11Off                = 1,
                 .pdsForceRamClkEn        = 0,
                 .pdsLdoVol               = 0xA,
                 .pdsCtlRfSel             = 3,
                 .pdsCtlPllSel            = 0,
                 },
    .pdsCtl2 =
        {
                 .forceCpuPwrOff  = 0,
                 .forceBzPwrOff   = 0,
                 .forceUsbPwrOff  = 0,
                 .forceCpuIsoEn   = 0,
                 .forceBzIsoEn    = 0,
                 .forceUsbIsoEn   = 0,
                 .forceCpuPdsRst  = 0,
                 .forceBzPdsRst   = 0,
                 .forceUsbPdsRst  = 0,
                 .forceCpuMemStby = 0,
                 .forceBzMemStby  = 0,
                 .forceUsbMemStby = 0,
                 .forceCpuGateClk = 0,
                 .forceBzGateClk  = 0,
                 .forceUsbGateClk = 0,
                 },
    .pdsCtl3 =
        {
                 .forceMiscPwrOff  = 0,
                 .forceBlePwrOff   = 0,
                 .forceBleIsoEn    = 0,
                 .forceMiscPdsRst  = 0,
                 .forceBlePdsRst   = 0,
                 .forceMiscMemStby = 0,
                 .forceBleMemStby  = 0,
                 .forceMiscGateClk = 0,
                 .forceBleGateClk  = 0,
                 .CpuIsoEn         = 0,
                 .BzIsoEn          = 0,
                 .BleIsoEn         = 1,
                 .UsbIsoEn         = 1,
                 .MiscIsoEn        = 0,
                 },
    .pdsCtl4 = {
                 .cpuPwrOff     = 0,
                 .cpuRst        = 0,
                 .cpuMemStby    = 1,
                 .cpuGateClk    = 1,
                 .BzPwrOff      = 0,
                 .BzRst         = 0,
                 .BzMemStby     = 1,
                 .BzGateClk     = 1,
                 .BlePwrOff     = 1,
                 .BleRst        = 1,
                 .BleMemStby    = 1,
                 .BleGateClk    = 1,
                 .UsbPwrOff     = 1,
                 .UsbRst        = 1,
                 .UsbMemStby    = 1,
                 .UsbGateClk    = 1,
                 .MiscPwrOff    = 0,
                 .MiscRst       = 0,
                 .MiscMemStby   = 1,
                 .MiscGateClk   = 1,
                 .MiscAnaPwrOff = 1,
                 .MiscDigPwrOff = 1,
                 }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = {
    .pdsCtl =
        {
                 .pdsStart                = 1,
                 .sleepForever            = 0,
                 .xtalForceOff            = 0,
                 .saveWifiState           = 0,
                 .dcdc18Off               = 1,
                 .bgSysOff                = 1,
                 .gpioIePuPd              = 1,
                 .puFlash                 = 0,
                 .clkOff                  = 1,
                 .memStby                 = 1,
                 .swPuFlash               = 1,
                 .isolation               = 1,
                 .waitXtalRdy             = 0,
                 .pdsPwrOff               = 1,
                 .xtalOff                 = 0,
                 .socEnbForceOn           = 1,
                 .pdsRstSocEn             = 0,
                 .pdsRC32mOn              = 0,
                 .pdsLdoVselEn            = 0,
                 .pdsRamLowPowerWithClkEn = 1,
                 .cpu0WfiMask             = 0,
                 .ldo11Off                = 1,
                 .pdsForceRamClkEn        = 0,
                 .pdsLdoVol               = 0xA,
                 .pdsCtlRfSel             = 2,
                 .pdsCtlPllSel            = 0,
                 },
    .pdsCtl2 =
        {
                 .forceCpuPwrOff  = 0,
                 .forceBzPwrOff   = 0,
                 .forceUsbPwrOff  = 0,
                 .forceCpuIsoEn   = 0,
                 .forceBzIsoEn    = 0,
                 .forceUsbIsoEn   = 0,
                 .forceCpuPdsRst  = 0,
                 .forceBzPdsRst   = 0,
                 .forceUsbPdsRst  = 0,
                 .forceCpuMemStby = 0,
                 .forceBzMemStby  = 0,
                 .forceUsbMemStby = 0,
                 .forceCpuGateClk = 0,
                 .forceBzGateClk  = 0,
                 .forceUsbGateClk = 0,
                 },
    .pdsCtl3 =
        {
                 .forceMiscPwrOff  = 0,
                 .forceBlePwrOff   = 0,
                 .forceBleIsoEn    = 0,
                 .forceMiscPdsRst  = 0,
                 .forceBlePdsRst   = 0,
                 .forceMiscMemStby = 0,
                 .forceBleMemStby  = 0,
                 .forceMiscGateClk = 0,
                 .forceBleGateClk  = 0,
                 .CpuIsoEn         = 0,
                 .BzIsoEn          = 1,
                 .BleIsoEn         = 1,
                 .UsbIsoEn         = 0,
                 .MiscIsoEn        = 0,
                 },
    .pdsCtl4 = {
                 .cpuPwrOff     = 0,
                 .cpuRst        = 0,
                 .cpuMemStby    = 1,
                 .cpuGateClk    = 1,
                 .BzPwrOff      = 1,
                 .BzRst         = 1,
                 .BzMemStby     = 1,
                 .BzGateClk     = 1,
                 .BlePwrOff     = 1,
                 .BleRst        = 1,
                 .BleMemStby    = 1,
                 .BleGateClk    = 1,
                 .UsbPwrOff     = 0,
                 .UsbRst        = 0,
                 .UsbMemStby    = 1,
                 .UsbGateClk    = 1,
                 .MiscPwrOff    = 0,
                 .MiscRst       = 0,
                 .MiscMemStby   = 1,
                 .MiscGateClk   = 1,
                 .MiscAnaPwrOff = 1,
                 .MiscDigPwrOff = 1,
                 }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = {
    .pdsCtl =
        {
                 .pdsStart                = 1,
                 .sleepForever            = 0,
                 .xtalForceOff            = 0,
                 .saveWifiState           = 0,
                 .dcdc18Off               = 1,
                 .bgSysOff                = 1,
                 .gpioIePuPd              = 1,
                 .puFlash                 = 0,
                 .clkOff                  = 1,
                 .memStby                 = 1,
                 .swPuFlash               = 1,
                 .isolation               = 1,
                 .waitXtalRdy             = 0,
                 .pdsPwrOff               = 1,
                 .xtalOff                 = 0,
                 .socEnbForceOn           = 1,
                 .pdsRstSocEn             = 0,
                 .pdsRC32mOn              = 0,
                 .pdsLdoVselEn            = 0,
                 .pdsRamLowPowerWithClkEn = 1,
                 .cpu0WfiMask             = 0,
                 .ldo11Off                = 1,
                 .pdsForceRamClkEn        = 0,
                 .pdsLdoVol               = 0xA,
                 .pdsCtlRfSel             = 2,
                 .pdsCtlPllSel            = 0,
                 },
    .pdsCtl2 =
        {
                 .forceCpuPwrOff  = 0,
                 .forceBzPwrOff   = 0,
                 .forceUsbPwrOff  = 0,
                 .forceCpuIsoEn   = 0,
                 .forceBzIsoEn    = 0,
                 .forceUsbIsoEn   = 0,
                 .forceCpuPdsRst  = 0,
                 .forceBzPdsRst   = 0,
                 .forceUsbPdsRst  = 0,
                 .forceCpuMemStby = 0,
                 .forceBzMemStby  = 0,
                 .forceUsbMemStby = 0,
                 .forceCpuGateClk = 0,
                 .forceBzGateClk  = 0,
                 .forceUsbGateClk = 0,
                 },
    .pdsCtl3 =
        {
                 .forceMiscPwrOff  = 0,
                 .forceBlePwrOff   = 0,
                 .forceBleIsoEn    = 0,
                 .forceMiscPdsRst  = 0,
                 .forceBlePdsRst   = 0,
                 .forceMiscMemStby = 0,
                 .forceBleMemStby  = 0,
                 .forceMiscGateClk = 0,
                 .forceBleGateClk  = 0,
                 .CpuIsoEn         = 0,
                 .BzIsoEn          = 1,
                 .BleIsoEn         = 1,
                 .UsbIsoEn         = 1,
                 .MiscIsoEn        = 0,
                 },
    .pdsCtl4 = {
                 .cpuPwrOff     = 0,
                 .cpuRst        = 0,
                 .cpuMemStby    = 1,
                 .cpuGateClk    = 1,
                 .BzPwrOff      = 1,
                 .BzRst         = 1,
                 .BzMemStby     = 1,
                 .BzGateClk     = 1,
                 .BlePwrOff     = 1,
                 .BleRst        = 1,
                 .BleMemStby    = 1,
                 .BleGateClk    = 1,
                 .UsbPwrOff     = 1,
                 .UsbRst        = 1,
                 .UsbMemStby    = 1,
                 .UsbGateClk    = 1,
                 .MiscPwrOff    = 0,
                 .MiscRst       = 0,
                 .MiscMemStby   = 1,
                 .MiscGateClk   = 1,
                 .MiscAnaPwrOff = 1,
                 .MiscDigPwrOff = 1,
                 }
};
#if 0
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = {
    .pdsCtl = {
        .pdsStart = 1,
        .sleepForever = 0,
        .xtalForceOff = 0,
        .saveWifiState = 0,
        .dcdc18Off = 1,
        .bgSysOff = 1,
        .gpioIePuPd = 1,
        .puFlash = 0,
        .clkOff = 1,
        .memStby = 1,
        .swPuFlash = 1,
        .isolation = 1,
        .waitXtalRdy = 0,
        .pdsPwrOff = 1,
        .xtalOff = 0,
        .socEnbForceOn = 1,
        .pdsRstSocEn = 0,
        .pdsRC32mOn = 0,
        .pdsLdoVselEn = 0,
        .pdsRamLowPowerWithClkEn = 1,
        .cpu0WfiMask = 0,
        .ldo11Off = 1,
        .pdsForceRamClkEn = 0,
        .pdsLdoVol = 0xA,
        .pdsCtlRfSel = 3,
        .pdsCtlPllSel = 0,
    },
    .pdsCtl2 = {
        .forceCpuPwrOff = 0,
        .forceBzPwrOff = 0,
        .forceUsbPwrOff = 0,
        .forceCpuIsoEn = 0,
        .forceBzIsoEn = 0,
        .forceUsbIsoEn = 0,
        .forceCpuPdsRst = 0,
        .forceBzPdsRst = 0,
        .forceUsbPdsRst = 0,
        .forceCpuMemStby = 0,
        .forceBzMemStby = 0,
        .forceUsbMemStby = 0,
        .forceCpuGateClk = 0,
        .forceBzGateClk = 0,
        .forceUsbGateClk = 0,
    },
    .pdsCtl3 = {
        .forceMiscPwrOff = 0,
        .forceBlePwrOff = 0,
        .forceBleIsoEn = 0,
        .forceMiscPdsRst = 0,
        .forceBlePdsRst = 0,
        .forceMiscMemStby = 0,
        .forceBleMemStby = 0,
        .forceMiscGateClk = 0,
        .forceBleGateClk = 0,
        .CpuIsoEn = 1,
        .BzIsoEn = 0,
        .BleIsoEn = 1,
        .UsbIsoEn = 0,
        .MiscIsoEn = 0,
    },
    .pdsCtl4 = {
        .cpuPwrOff = 1,
        .cpuRst = 1,
        .cpuMemStby = 1,
        .cpuGateClk = 1,
        .BzPwrOff = 0,
        .BzRst = 0,
        .BzMemStby = 1,
        .BzGateClk = 1,
        .BlePwrOff = 1,
        .BleRst = 1,
        .BleMemStby = 1,
        .BleGateClk = 1,
        .UsbPwrOff = 0,
        .UsbRst = 0,
        .UsbMemStby = 1,
        .UsbGateClk = 1,
        .MiscPwrOff = 0,
        .MiscRst = 0,
        .MiscMemStby = 1,
        .MiscGateClk = 1,
        .MiscAnaPwrOff = 1,
        .MiscDigPwrOff = 1,
    }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel5 = {
    .pdsCtl = {
        .pdsStart = 1,
        .sleepForever = 0,
        .xtalForceOff = 0,
        .saveWifiState = 0,
        .dcdc18Off = 1,
        .bgSysOff = 1,
        .gpioIePuPd = 1,
        .puFlash = 0,
        .clkOff = 1,
        .memStby = 1,
        .swPuFlash = 1,
        .isolation = 1,
        .waitXtalRdy = 0,
        .pdsPwrOff = 1,
        .xtalOff = 0,
        .socEnbForceOn = 1,
        .pdsRstSocEn = 0,
        .pdsRC32mOn = 0,
        .pdsLdoVselEn = 0,
        .pdsRamLowPowerWithClkEn = 1,
        .cpu0WfiMask = 0,
        .ldo11Off = 1,
        .pdsForceRamClkEn = 0,
        .pdsLdoVol = 0xA,
        .pdsCtlRfSel = 3,
        .pdsCtlPllSel = 0,
    },
    .pdsCtl2 = {
        .forceCpuPwrOff = 0,
        .forceBzPwrOff = 0,
        .forceUsbPwrOff = 0,
        .forceCpuIsoEn = 0,
        .forceBzIsoEn = 0,
        .forceUsbIsoEn = 0,
        .forceCpuPdsRst = 0,
        .forceBzPdsRst = 0,
        .forceUsbPdsRst = 0,
        .forceCpuMemStby = 0,
        .forceBzMemStby = 0,
        .forceUsbMemStby = 0,
        .forceCpuGateClk = 0,
        .forceBzGateClk = 0,
        .forceUsbGateClk = 0,
    },
    .pdsCtl3 = {
        .forceMiscPwrOff = 0,
        .forceBlePwrOff = 0,
        .forceBleIsoEn = 0,
        .forceMiscPdsRst = 0,
        .forceBlePdsRst = 0,
        .forceMiscMemStby = 0,
        .forceBleMemStby = 0,
        .forceMiscGateClk = 0,
        .forceBleGateClk = 0,
        .CpuIsoEn = 1,
        .BzIsoEn = 0,
        .BleIsoEn = 1,
        .UsbIsoEn = 1,
        .MiscIsoEn = 0,
    },
    .pdsCtl4 = {
        .cpuPwrOff = 1,
        .cpuRst = 1,
        .cpuMemStby = 1,
        .cpuGateClk = 1,
        .BzPwrOff = 0,
        .BzRst = 0,
        .BzMemStby = 1,
        .BzGateClk = 1,
        .BlePwrOff = 1,
        .BleRst = 1,
        .BleMemStby = 1,
        .BleGateClk = 1,
        .UsbPwrOff = 1,
        .UsbRst = 1,
        .UsbMemStby = 1,
        .UsbGateClk = 1,
        .MiscPwrOff = 0,
        .MiscRst = 0,
        .MiscMemStby = 1,
        .MiscGateClk = 1,
        .MiscAnaPwrOff = 1,
        .MiscDigPwrOff = 1,
    }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel6 = {
    .pdsCtl = {
        .pdsStart = 1,
        .sleepForever = 0,
        .xtalForceOff = 0,
        .saveWifiState = 0,
        .dcdc18Off = 1,
        .bgSysOff = 1,
        .gpioIePuPd = 1,
        .puFlash = 0,
        .clkOff = 1,
        .memStby = 1,
        .swPuFlash = 1,
        .isolation = 1,
        .waitXtalRdy = 0,
        .pdsPwrOff = 1,
        .xtalOff = 0,
        .socEnbForceOn = 1,
        .pdsRstSocEn = 0,
        .pdsRC32mOn = 0,
        .pdsLdoVselEn = 0,
        .pdsRamLowPowerWithClkEn = 1,
        .cpu0WfiMask = 0,
        .ldo11Off = 1,
        .pdsForceRamClkEn = 0,
        .pdsLdoVol = 0xA,
        .pdsCtlRfSel = 2,
        .pdsCtlPllSel = 0,
    },
    .pdsCtl2 = {
        .forceCpuPwrOff = 0,
        .forceBzPwrOff = 0,
        .forceUsbPwrOff = 0,
        .forceCpuIsoEn = 0,
        .forceBzIsoEn = 0,
        .forceUsbIsoEn = 0,
        .forceCpuPdsRst = 0,
        .forceBzPdsRst = 0,
        .forceUsbPdsRst = 0,
        .forceCpuMemStby = 0,
        .forceBzMemStby = 0,
        .forceUsbMemStby = 0,
        .forceCpuGateClk = 0,
        .forceBzGateClk = 0,
        .forceUsbGateClk = 0,
    },
    .pdsCtl3 = {
        .forceMiscPwrOff = 0,
        .forceBlePwrOff = 0,
        .forceBleIsoEn = 0,
        .forceMiscPdsRst = 0,
        .forceBlePdsRst = 0,
        .forceMiscMemStby = 0,
        .forceBleMemStby = 0,
        .forceMiscGateClk = 0,
        .forceBleGateClk = 0,
        .CpuIsoEn = 1,
        .BzIsoEn = 1,
        .BleIsoEn = 1,
        .UsbIsoEn = 0,
        .MiscIsoEn = 0,
    },
    .pdsCtl4 = {
        .cpuPwrOff = 1,
        .cpuRst = 1,
        .cpuMemStby = 1,
        .cpuGateClk = 1,
        .BzPwrOff = 1,
        .BzRst = 1,
        .BzMemStby = 1,
        .BzGateClk = 1,
        .BlePwrOff = 1,
        .BleRst = 1,
        .BleMemStby = 1,
        .BleGateClk = 1,
        .UsbPwrOff = 0,
        .UsbRst = 0,
        .UsbMemStby = 1,
        .UsbGateClk = 1,
        .MiscPwrOff = 0,
        .MiscRst = 0,
        .MiscMemStby = 1,
        .MiscGateClk = 1,
        .MiscAnaPwrOff = 1,
        .MiscDigPwrOff = 1,
    }
};
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = {
    .pdsCtl = {
        .pdsStart = 1,
        .sleepForever = 0,
        .xtalForceOff = 0,
        .saveWifiState = 0,
        .dcdc18Off = 1,
        .bgSysOff = 1,
        .gpioIePuPd = 1,
        .puFlash = 0,
        .clkOff = 1,
        .memStby = 1,
        .swPuFlash = 1,
        .isolation = 1,
        .waitXtalRdy = 0,
        .pdsPwrOff = 1,
        .xtalOff = 0,
        .socEnbForceOn = 1,
        .pdsRstSocEn = 0,
        .pdsRC32mOn = 0,
        .pdsLdoVselEn = 0,
        .pdsRamLowPowerWithClkEn = 1,
        .cpu0WfiMask = 0,
        .ldo11Off = 1,
        .pdsForceRamClkEn = 0,
        .pdsLdoVol = 0xA,
        .pdsCtlRfSel = 2,
        .pdsCtlPllSel = 0,
    },
    .pdsCtl2 = {
        .forceCpuPwrOff = 0,
        .forceBzPwrOff = 0,
        .forceUsbPwrOff = 0,
        .forceCpuIsoEn = 0,
        .forceBzIsoEn = 0,
        .forceUsbIsoEn = 0,
        .forceCpuPdsRst = 0,
        .forceBzPdsRst = 0,
        .forceUsbPdsRst = 0,
        .forceCpuMemStby = 0,
        .forceBzMemStby = 0,
        .forceUsbMemStby = 0,
        .forceCpuGateClk = 0,
        .forceBzGateClk = 0,
        .forceUsbGateClk = 0,
    },
    .pdsCtl3 = {
        .forceMiscPwrOff = 0,
        .forceBlePwrOff = 0,
        .forceBleIsoEn = 0,
        .forceMiscPdsRst = 0,
        .forceBlePdsRst = 0,
        .forceMiscMemStby = 0,
        .forceBleMemStby = 0,
        .forceMiscGateClk = 0,
        .forceBleGateClk = 0,
        .CpuIsoEn = 1,
        .BzIsoEn = 1,
        .BleIsoEn = 1,
        .UsbIsoEn = 1,
        .MiscIsoEn = 0,
    },
    .pdsCtl4 = {
        .cpuPwrOff = 1,
        .cpuRst = 1,
        .cpuMemStby = 1,
        .cpuGateClk = 1,
        .BzPwrOff = 1,
        .BzRst = 1,
        .BzMemStby = 1,
        .BzGateClk = 1,
        .BlePwrOff = 1,
        .BleRst = 1,
        .BleMemStby = 1,
        .BleGateClk = 1,
        .UsbPwrOff = 1,
        .UsbRst = 1,
        .UsbMemStby = 1,
        .UsbGateClk = 1,
        .MiscPwrOff = 0,
        .MiscRst = 0,
        .MiscMemStby = 1,
        .MiscGateClk = 1,
        .MiscAnaPwrOff = 1,
        .MiscDigPwrOff = 1,
    }
};
#endif
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = {
    .pdsCtl =
        {
                 .pdsStart                = 1,
                 .sleepForever            = 0,
                 .xtalForceOff            = 0,
                 .saveWifiState           = 0,
                 .dcdc18Off               = 1,
                 .bgSysOff                = 1,
                 .gpioIePuPd              = 1,
                 .puFlash                 = 0,
                 .clkOff                  = 1,
                 .memStby                 = 1,
                 .swPuFlash               = 1,
                 .isolation               = 1,
                 .waitXtalRdy             = 0,
                 .pdsPwrOff               = 1,
                 .xtalOff                 = 0,
                 .socEnbForceOn           = 0,
                 .pdsRstSocEn             = 0,
                 .pdsRC32mOn              = 0,
                 .pdsLdoVselEn            = 0,
                 .pdsRamLowPowerWithClkEn = 1,
                 .cpu0WfiMask             = 0,
                 .ldo11Off                = 1,
                 .pdsForceRamClkEn        = 0,
                 .pdsLdoVol               = 0xA,
                 .pdsCtlRfSel             = 2,
                 .pdsCtlPllSel            = 0,
                 },
    .pdsCtl2 =
        {
                 .forceCpuPwrOff  = 0,
                 .forceBzPwrOff   = 0,
                 .forceUsbPwrOff  = 0,
                 .forceCpuIsoEn   = 0,
                 .forceBzIsoEn    = 0,
                 .forceUsbIsoEn   = 0,
                 .forceCpuPdsRst  = 0,
                 .forceBzPdsRst   = 0,
                 .forceUsbPdsRst  = 0,
                 .forceCpuMemStby = 0,
                 .forceBzMemStby  = 0,
                 .forceUsbMemStby = 0,
                 .forceCpuGateClk = 0,
                 .forceBzGateClk  = 0,
                 .forceUsbGateClk = 0,
                 },
    .pdsCtl3 =
        {
                 .forceMiscPwrOff  = 0,
                 .forceBlePwrOff   = 0,
                 .forceBleIsoEn    = 0,
                 .forceMiscPdsRst  = 0,
                 .forceBlePdsRst   = 0,
                 .forceMiscMemStby = 0,
                 .forceBleMemStby  = 0,
                 .forceMiscGateClk = 0,
                 .forceBleGateClk  = 0,
                 .CpuIsoEn         = 1,
                 .BzIsoEn          = 1,
                 .BleIsoEn         = 1,
                 .UsbIsoEn         = 1,
                 .MiscIsoEn        = 1,
                 },
    .pdsCtl4 = {
                 .cpuPwrOff     = 1,
                 .cpuRst        = 1,
                 .cpuMemStby    = 1,
                 .cpuGateClk    = 1,
                 .BzPwrOff      = 1,
                 .BzRst         = 1,
                 .BzMemStby     = 1,
                 .BzGateClk     = 1,
                 .BlePwrOff     = 1,
                 .BleRst        = 1,
                 .BleMemStby    = 1,
                 .BleGateClk    = 1,
                 .UsbPwrOff     = 1,
                 .UsbRst        = 1,
                 .UsbMemStby    = 1,
                 .UsbGateClk    = 1,
                 .MiscPwrOff    = 1,
                 .MiscRst       = 1,
                 .MiscMemStby   = 1,
                 .MiscGateClk   = 1,
                 .MiscAnaPwrOff = 1,
                 .MiscDigPwrOff = 1,
                 }
};

/****************************************************************************/ /**
                                                                                * @brief  PDS update flash_ctrl setting
                                                                                *
                                                                                * @param  fastClock: fast clock
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) {
  if (fastClock) {
    GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_72M, 0);
  } else {
    GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0);
  }

  SF_Ctrl_Set_Clock_Delay(fastClock);
}

ATTR_TCM_SECTION void pm_pds_enter_done(void) {
  __asm__ __volatile__("la     a2,     __ld_pds_bak_addr\n\t"
                       "sw     ra,     0(a2)\n\t");

  __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */
}
/**
 * @brief power management in pds(power down sleep) mode
 *
 * cpu's behavior after wakeup depend on psd level,see flow table if cpu off , cpu will reset after wakeup
 *
 *                      PD_CORE     PD_CORE_MISC_DIG    PD_CORE_MISC_ANA    PD_CORE_CPU     PD_BZ   PD_USB
 *          PDS0          ON               ON                  ON               ON            ON      ON
 *          PDS1          ON               ON                  ON               ON            ON      OFF
 *          PDS2          ON               ON                  ON               ON            OFF     ON
 *          PDS3          ON               ON                  ON               ON            OFF     OFF
 *          PDS4          ON               ON                  ON               OFF           ON      ON
 *          PDS5          ON               ON                  ON               OFF           ON      OFF
 *          PDS6          ON               ON                  ON               OFF           OFF     ON
 *          PDS7          ON               ON                  ON               OFF           OFF     OFF
 *          PDS31         ON               OFF                 OFF              OFF           OFF     OFF
 */
ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time) {
  PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL;
  uint32_t                 tmpVal;
  uint32_t                 flash_cfg_len;

  /* To make it simple and safe*/
  cpu_global_irq_disable();

  flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
  HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);

  PDS_WAKEUP_IRQHandler_Install();
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal &= ~(1 << 8); // unmask pds wakeup

  if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK) || !(BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1) == 0xffffffff)) {
    tmpVal |= (1 << 19); // enable gpio wakeup for pds
  }
  if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
    tmpVal |= (1 << 17); // enable hbn out0 wakeup for pds
  }

  if (sleep_time) {
    tmpVal |= (1 << 16); // unmask pds sleep time wakeup
  }
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  PDS_Set_Vddcore_GPIO_IntClear();
  PDS_IntClear();

  /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */
  CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);

  switch (pds_level) {
  case PM_PDS_LEVEL_0:
    pPdsCfg = &pdsCfgLevel0;
    break;
  case PM_PDS_LEVEL_1:
    pPdsCfg = &pdsCfgLevel1;
    break;
  case PM_PDS_LEVEL_2:
    pPdsCfg = &pdsCfgLevel2;
    break;
  case PM_PDS_LEVEL_3:
    pPdsCfg = &pdsCfgLevel3;
    break;
  case PM_PDS_LEVEL_4:
    return;
  case PM_PDS_LEVEL_5:
    return;
  case PM_PDS_LEVEL_6:
    return;
  case PM_PDS_LEVEL_7:
    return;
  case PM_PDS_LEVEL_31:
    pPdsCfg = &pdsCfgLevel31;
    break;
  default:
    return;
  }

#if PM_PDS_FLASH_POWER_OFF
  HBN_Power_Down_Flash(flash_cfg);
  /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */
  for (uint32_t pin = 23; pin <= 28; pin++) {
    GLB_GPIO_Set_HZ(pin);
  }
  /* SF io select from efuse value */
  uint32_t flash_select = BL_RD_WORD(0x40007074);
  if (((flash_select >> 26) & 7) == 0) {
    HBN_Set_Pad_23_28_Pullup();
  }
  pPdsCfg->pdsCtl.puFlash = 1;
#endif

#if PM_PDS_PLL_POWER_OFF
  PDS_Power_Off_PLL();
#endif
#if PM_PDS_DLL_POWER_OFF
  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
  AON_Power_Off_XTAL();
  GLB_Power_Off_DLL();
  PDS_Update_Flash_Ctrl_Setting(0);
#endif

  /* pds0-pds7 : ldo11rt_iload_sel=3 */
  /* pds31     : ldo11rt_iload_sel=1 */
  if (pds_level <= PM_PDS_LEVEL_7) {
    HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_25_250UA);
  } else if (pds_level == PM_PDS_LEVEL_31) {
    HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);
  } else {
    /* pdsLevel error */
  }

  pPdsCfg->pdsCtl.pdsLdoVol    = PM_PDS_LDO_LEVEL_DEFAULT;
  pPdsCfg->pdsCtl.pdsLdoVselEn = 1;

  if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
    pPdsCfg->pdsCtl.gpioIePuPd = 0;
  }

#if PM_PDS_RF_POWER_OFF == 0
  pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
#endif
  /* config  ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */
  AON_Set_LDO11_SOC_Sstart_Delay(0x2);

  PDS_Default_Level_Config(pPdsCfg, sleep_time);

  __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */

#if PM_PDS_PLL_POWER_OFF
  GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
  PDS_Update_Flash_Ctrl_Setting(1);
#endif

#if PM_PDS_FLASH_POWER_OFF
  HBN_Set_Pad_23_28_Pullnone();
  /* Init flash gpio */
  SF_Cfg_Init_Flash_Gpio(0, 1);

  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
  SFlash_Restore_From_Powerdown(flash_cfg, 0);
#endif

  cpu_global_irq_enable();
}

ATTR_TCM_SECTION void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time) {
  PDS_DEFAULT_LV_CFG_Type *pPdsCfg = &pdsCfgLevel31;
  uint32_t                 tmpVal;
  uint32_t                 flash_cfg_len;

  // Get cache way disable setting
  cacheWayDisable = (*(volatile uint32_t *)(L1C_BASE + 0x00) >> 8) & 0x0F;

  // Get psram io configuration
  psramIoCfg = *(volatile uint32_t *)(GLB_BASE + 0x88);

  // Get flash offset
  flash_offset = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET);

  /* To make it simple and safe*/
  cpu_global_irq_disable();

  flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
  HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);

  PDS_WAKEUP_IRQHandler_Install();
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal &= ~(1 << 8); // unmask pds wakeup

  if (!BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
    tmpVal |= (1 << 19); // enable gpio wakeup for pds
  }
  if (BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_REG_AON_PAD_IE_SMT)) {
    tmpVal |= (1 << 17); // enable hbn out0 wakeup for pds
  }

  if (sleep_time) {
    tmpVal |= (1 << 16); // unmask pds sleep time wakeup
  }
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  PDS_IntClear();

  /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */
  CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);

#if PM_PDS_FLASH_POWER_OFF
  HBN_Power_Down_Flash(flash_cfg);
  /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */
  for (uint32_t pin = 23; pin <= 28; pin++) {
    GLB_GPIO_Set_HZ(pin);
  }
  /* SF io select from efuse value */
  uint32_t flash_select = BL_RD_WORD(0x40007074);
  if (((flash_select >> 26) & 7) == 0) {
    HBN_Set_Pad_23_28_Pullup();
  }
  pPdsCfg->pdsCtl.puFlash = 1;
#endif

#if PM_PDS_PLL_POWER_OFF
  PDS_Power_Off_PLL();
#endif
#if PM_PDS_DLL_POWER_OFF
  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
  AON_Power_Off_XTAL();
  GLB_Power_Off_DLL();
  PDS_Update_Flash_Ctrl_Setting(0);
#endif

  /* pds31     : ldo11rt_iload_sel=1 */
  HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_10_100UA);

  pPdsCfg->pdsCtl.pdsLdoVol    = PM_PDS_LDO_LEVEL_DEFAULT;
  pPdsCfg->pdsCtl.pdsLdoVselEn = 1;

  if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
    pPdsCfg->pdsCtl.gpioIePuPd = 0;
  }

#if PM_PDS_RF_POWER_OFF == 0
  pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
#endif
  /* config  ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */
  AON_Set_LDO11_SOC_Sstart_Delay(0x2);

  PDS_Default_Level_Config(pPdsCfg, sleep_time);

  __asm__ __volatile__("csrr   a0,     mtvec\n\t"
                       "csrr   a1,     mstatus\n\t"
                       "la     a2,     __ld_pds_bak_addr\n\t"
                       "sw     sp,     1*4(a2)\n\t"
                       "sw     tp,     2*4(a2)\n\t"
                       "sw     t0,     3*4(a2)\n\t"
                       "sw     t1,     4*4(a2)\n\t"
                       "sw     t2,     5*4(a2)\n\t"
                       "sw     fp,     6*4(a2)\n\t"
                       "sw     s1,     7*4(a2)\n\t"
                       "sw     a0,     8*4(a2)\n\t"
                       "sw     a1,     9*4(a2)\n\t"
                       "sw     a3,     10*4(a2)\n\t"
                       "sw     a4,     11*4(a2)\n\t"
                       "sw     a5,     12*4(a2)\n\t"
                       "sw     a6,     13*4(a2)\n\t"
                       "sw     a7,     14*4(a2)\n\t"
                       "sw     s2,     15*4(a2)\n\t"
                       "sw     s3,     16*4(a2)\n\t"
                       "sw     s4,     17*4(a2)\n\t"
                       "sw     s5,     18*4(a2)\n\t"
                       "sw     s6,     19*4(a2)\n\t"
                       "sw     s7,     20*4(a2)\n\t"
                       "sw     s8,     21*4(a2)\n\t"
                       "sw     s9,     22*4(a2)\n\t"
                       "sw     s10,    23*4(a2)\n\t"
                       "sw     s11,    24*4(a2)\n\t"
                       "sw     t3,     25*4(a2)\n\t"
                       "sw     t4,     26*4(a2)\n\t"
                       "sw     t5,     27*4(a2)\n\t"
                       "sw     t6,     28*4(a2)\n\t");

  pm_pds_enter_done();

  cpu_global_irq_enable();

  // Get cache way disable setting
  *(volatile uint32_t *)(L1C_BASE + 0x00) &= ~(0x0F < 8);
  *(volatile uint32_t *)(L1C_BASE + 0x00) |= cacheWayDisable;

  // Get psram io configuration
  *(volatile uint32_t *)(GLB_BASE + 0x88) = psramIoCfg;
}
/**
 * @brief
 *
 * power management in hbn(hibernation) mode
 * cpu will reset after wakeup
 *
 * HBN_LEVEL   PD_AON       PD_AON_HNBRTC        PD_AON_HBNCORE        PD_CORE     PD_CORE_MISC_DIG    PD_CORE_MISC_ANA    PD_CORE_CPU     PD_BZ   PD_USB
 * HBN0          ON               ON                  ON                OFF            OFF                  OFF                 OFF         OFF     OFF
 * HBN1          ON               ON                  OFF               OFF            OFF                  OFF                 OFF         OFF     OFF
 * HBN2          ON               OFF                 OFF               OFF            OFF                  OFF                 OFF         OFF     OFF
 * @param hbn_level
 */
ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time) {
  uint32_t tmpVal;

  /* To make it simple and safe*/
  cpu_global_irq_disable();

  if (sleep_time && (hbn_level < PM_HBN_LEVEL_2)) {
    rtc_init(sleep_time); // sleep time,unit is second
  }

  if (hbn_level >= PM_HBN_LEVEL_2) {
    HBN_Power_Off_RC32K();
  } else {
    HBN_Power_On_RC32K();
  }

  HBN_Power_Down_Flash(NULL);
  /* SF io select from efuse value */
  uint32_t flash_select = BL_RD_WORD(0x40007074);
  if (((flash_select >> 26) & 7) == 0) {
    HBN_Set_Pad_23_28_Pullup();
  }

  /* Select RC32M */
  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
  /* power off xtal */
  AON_Power_Off_XTAL();
  GLB_Power_Off_DLL();
  PDS_Power_Off_PLL();

  /* HBN mode LDO level */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  /* Set HBN flag */
  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);

  /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
  switch (hbn_level) {
  case PM_HBN_LEVEL_0:
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case PM_HBN_LEVEL_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case PM_HBN_LEVEL_2:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;
  default:
    break;
  }

  /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0;
  *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0;

  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);

  /* Enable HBN mode */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  while (1) {
    BL702_Delay_MS(1000);
  }
}

ATTR_HBN_RAM_SECTION void pm_hbn_enter_again(bool reset) {
  uint32_t tmpVal;
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);

  if (!reset) {
    /* Enable HBN mode */
    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
  }

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
}

void pm_set_wakeup_callback(void (*wakeup_callback)(void)) {
  BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback);
  /* Set HBN flag */
  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
}

enum pm_event_type pm_get_wakeup_event(void) {
  if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO9)) {
    return PM_HBN_GPIO9_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
    return PM_HBN_GPIO10_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO11)) {
    return PM_HBN_GPIO11_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO12)) {
    return PM_HBN_GPIO12_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_PIR)) {
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_BOR)) {
    return PM_HBN_BOR_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP0)) {
    return PM_HBN_ACOMP0_WAKEUP_EVENT;
  } else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP1)) {
    return PM_HBN_ACOMP1_WAKEUP_EVENT;
  }

  return PM_HBN_WAKEUP_EVENT_NONE;
}

void pm_bor_init(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, HBN_BOR_THRES_2P4V);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, HBN_BOR_MODE_POR_INDEPENDENT);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}

void pm_hbn_out0_irq_register(void) {
  Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT0_IRQ);
  CPU_Interrupt_Enable(HBN_OUT0_IRQn);
}

void pm_hbn_out1_irq_register(void) {
  Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ);
  CPU_Interrupt_Enable(HBN_OUT1_IRQn);
}

void HBN_OUT0_IRQ(void) {
  if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
    HBN_Clear_IRQ(HBN_INT_GPIO9);
    pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT);
  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
    HBN_Clear_IRQ(HBN_INT_GPIO10);
    pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT);
  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
    HBN_Clear_IRQ(HBN_INT_GPIO11);
    pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT);
  } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
    HBN_Clear_IRQ(HBN_INT_GPIO12);
    pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT);
  } else {
    HBN_Clear_IRQ(HBN_INT_RTC);
    HBN_Clear_RTC_INT();
    pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT);
  }
}

void HBN_OUT1_IRQ(void) {
  /* PIR */
  if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
    HBN_Clear_IRQ(HBN_INT_PIR);
  }
  /* BOR */
  else if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
    HBN_Clear_IRQ(HBN_INT_BOR);
    pm_irq_callback(PM_HBN_BOR_WAKEUP_EVENT);
  }
  /* ACOMP0 */
  else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
    HBN_Clear_IRQ(HBN_INT_ACOMP0);
    pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT);
  }
  /* ACOMP1 */
  else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
    HBN_Clear_IRQ(HBN_INT_ACOMP1);
    pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT);
  }
}

__WEAK void pm_irq_callback(enum pm_event_type event) {}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_pm_util.c
================================================
/**
 * @file hal_pm_util.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#include "hal_pm_util.h"
#include "bl702_glb.h"
#include "bl702_romdriver.h"
#include "bl702_sf_ctrl.h"
#include "hal_clock.h"
#include "hal_pm.h"

/* Cache Way Disable, will get from l1c register */
extern uint8_t cacheWayDisable;

/* PSRAM IO Configuration, will get from glb register */
extern uint32_t psramIoCfg;

/* Flash offset value, will get from sf_ctrl register */
extern uint32_t flash_offset;

extern void pm_pds31_fast_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);

extern SPI_Flash_Cfg_Type *flash_cfg;

void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void);

void (*hardware_recovery)(void) = NULL;

/**
 * @brief hal_pds_enter_with_time_compensation
 *
 * @param pdsLevel pds level support 0~3,31
 * @param pdsSleepCycles user set sleep time, clock of pds_time is 32768hz
 * @return uint32_t actual sleep time(ms)
 *
 * @note If necessary，please application layer call vTaskStepTick，
 */
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles) {
  uint32_t rtcLowBeforeSleep = 0, rtcHighBeforeSleep = 0;
  uint32_t rtcLowAfterSleep = 0, rtcHighAfterSleep = 0;
  uint32_t actualSleepDuration_32768cycles = 0;
  uint32_t actualSleepDuration_ms          = 0;

  pm_set_wakeup_callback(pm_pds_fastboot_entry);

  HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep);

  pm_pds31_fast_mode_enter(pdsLevel, pdsSleepCycles);

  HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep);

  CHECK_PARAM((rtcHighAfterSleep - rtcHighBeforeSleep) <= 1); // make sure sleep less than 1 hour (2^32 us > 1 hour)

  actualSleepDuration_32768cycles = (rtcLowAfterSleep - rtcLowBeforeSleep);

  actualSleepDuration_ms = (actualSleepDuration_32768cycles >> 5) - (actualSleepDuration_32768cycles >> 11) - (actualSleepDuration_32768cycles >> 12);

  // vTaskStepTick(actualSleepDuration_ms);

  return actualSleepDuration_ms;
}
/**
 * @brief get delay value of spi flash init
 *
 * @param delay_index
 * @return uint8_t
 */
static uint8_t ATTR_PDS_RAM_SECTION bflb_spi_flash_get_delay_val(uint8_t delay_index) {
  switch (delay_index) {
  case 0:
    return 0x00;
  case 1:
    return 0x80;
  case 2:
    return 0xc0;
  case 3:
    return 0xe0;
  case 4:
    return 0xf0;
  case 5:
    return 0xf8;
  case 6:
    return 0xfc;
  case 7:
    return 0xfe;
  default:
    return 0x00;
  }
}
/**
 * @brief config spi flash
 *
 * @param pFlashCfg flash parameter
 */
static void ATTR_PDS_RAM_SECTION bflb_spi_flash_set_sf_ctrl(SPI_Flash_Cfg_Type *pFlashCfg) {
  SF_Ctrl_Cfg_Type sfCtrlCfg;
  uint8_t          delay_index;

  sfCtrlCfg.owner = SF_CTRL_OWNER_SAHB;

  /* bit0-3 for clk delay */
  sfCtrlCfg.clkDelay = (pFlashCfg->clkDelay & 0x0f);
  /* bit0 for clk invert */
  sfCtrlCfg.clkInvert = pFlashCfg->clkInvert & 0x01;
  /* bit1 for rx clk invert */
  sfCtrlCfg.rxClkInvert = (pFlashCfg->clkInvert >> 1) & 0x01;
  /* bit4-6 for do delay */
  delay_index       = (pFlashCfg->clkDelay >> 4) & 0x07;
  sfCtrlCfg.doDelay = bflb_spi_flash_get_delay_val(delay_index);
  /* bit2-4 for di delay */
  delay_index       = (pFlashCfg->clkInvert >> 2) & 0x07;
  sfCtrlCfg.diDelay = bflb_spi_flash_get_delay_val(delay_index);
  /* bit5-7 for oe delay */
  delay_index       = (pFlashCfg->clkInvert >> 5) & 0x07;
  sfCtrlCfg.oeDelay = bflb_spi_flash_get_delay_val(delay_index);

  RomDriver_SFlash_Init(&sfCtrlCfg);
}

/**
 * @brief
 *
 * @param media_boot
 * @return int32_t
 */
int32_t ATTR_PDS_RAM_SECTION pm_spi_flash_init(uint8_t media_boot) {
  uint32_t stat;
  uint32_t jdecId         = 0;
  uint32_t flash_read_try = 0;

  /*use fclk as flash clok */
  RomDriver_GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); // 32M
  RomDriver_SF_Ctrl_Set_Clock_Delay(0);

  bflb_spi_flash_set_sf_ctrl(flash_cfg);

  /* Wake flash up from power down */
  RomDriver_SFlash_Releae_Powerdown(flash_cfg);
  // ARCH_Delay_US(15*((pFlashCfg->pdDelay&0x7)+1));
  RomDriver_BL702_Delay_US(120);

  do {
    if (flash_read_try > 4) {
      // bflb_bootrom_printd("Flash read id TO\r\n");
      break;
    } else if (flash_read_try > 0) {
      RomDriver_BL702_Delay_US(500);
    }

    // bflb_bootrom_printd("reset flash\r\n");
    /* Exit form continous read for accepting command */
    RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
    /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
    RomDriver_SFlash_Software_Reset(flash_cfg);
    /* Disable burst may be removed(except for 80BV) and only work with winbond,but just for make sure */
    RomDriver_SFlash_Write_Enable(flash_cfg);
    /* For disable command that is setting register instaed of send command, we need write enable */
    RomDriver_SFlash_DisableBurstWrap(flash_cfg);

    stat = RomDriver_SFlash_SetSPIMode(SF_CTRL_SPI_MODE);
    if (SUCCESS != stat) {
      // bflb_bootrom_printe("enter spi mode fail %d\r\n", stat);
      // return BFLB_BOOTROM_FLASH_INIT_ERROR;
      return -1;
    }

    RomDriver_SFlash_GetJedecId(flash_cfg, (uint8_t *)&jdecId);

    /* Dummy disable burstwrap for make sure */
    RomDriver_SFlash_Write_Enable(flash_cfg);
    /* For disable command that is setting register instead of send command, we need write enable */
    RomDriver_SFlash_DisableBurstWrap(flash_cfg);

    jdecId = jdecId & 0xffffff;
    // bflb_bootrom_printd("ID =%08x\r\n", jdecId);
    flash_read_try++;
  } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);

  /*clear offset setting*/

  // reset image offset
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);

  /* set read mode */
  if ((flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
    stat = RomDriver_SFlash_Qspi_Enable(flash_cfg);
  }

  if (media_boot) {
    RomDriver_L1C_Set_Wrap(DISABLE);

    RomDriver_SFlash_Cache_Read_Enable(flash_cfg, flash_cfg->ioMode & 0xf, 0, 0x00);
  }

  return jdecId;
}

// can be placed in flash, here placed in pds section to reduce fast boot time
static void ATTR_PDS_RAM_SECTION pm_pds_restore_cpu_reg(void) {
  __asm__ __volatile__("la     a2,     __ld_pds_bak_addr\n\t"
                       "lw     ra,     0(a2)\n\t"
                       "lw     sp,     1*4(a2)\n\t"
                       "lw     tp,     2*4(a2)\n\t"
                       "lw     t0,     3*4(a2)\n\t"
                       "lw     t1,     4*4(a2)\n\t"
                       "lw     t2,     5*4(a2)\n\t"
                       "lw     fp,     6*4(a2)\n\t"
                       "lw     s1,     7*4(a2)\n\t"
                       "lw     a0,     8*4(a2)\n\t"
                       "lw     a1,     9*4(a2)\n\t"
                       "lw     a3,     10*4(a2)\n\t"
                       "lw     a4,     11*4(a2)\n\t"
                       "lw     a5,     12*4(a2)\n\t"
                       "lw     a6,     13*4(a2)\n\t"
                       "lw     a7,     14*4(a2)\n\t"
                       "lw     s2,     15*4(a2)\n\t"
                       "lw     s3,     16*4(a2)\n\t"
                       "lw     s4,     17*4(a2)\n\t"
                       "lw     s5,     18*4(a2)\n\t"
                       "lw     s6,     19*4(a2)\n\t"
                       "lw     s7,     20*4(a2)\n\t"
                       "lw     s8,     21*4(a2)\n\t"
                       "lw     s9,     22*4(a2)\n\t"
                       "lw     s10,    23*4(a2)\n\t"
                       "lw     s11,    24*4(a2)\n\t"
                       "lw     t3,     25*4(a2)\n\t"
                       "lw     t4,     26*4(a2)\n\t"
                       "lw     t5,     27*4(a2)\n\t"
                       "lw     t6,     28*4(a2)\n\t"
                       "csrw   mtvec,  a0\n\t"
                       "csrw   mstatus,a1\n\t"
                       "ret\n\t");
}
void ATTR_PDS_RAM_SECTION sf_io_select(void) {
  uint32_t tmpVal          = 0;
  uint8_t  flashCfg        = 0;
  uint8_t  psramCfg        = 0;
  uint8_t  isInternalFlash = 0;
  uint8_t  isInternalPsram = 0;

  /* SF io select from efuse value */
  tmpVal   = BL_RD_WORD(0x40007074);
  flashCfg = ((tmpVal >> 26) & 7);
  psramCfg = ((tmpVal >> 24) & 3);
  if (flashCfg == 1 || flashCfg == 2) {
    isInternalFlash = 1;
  } else {
    isInternalFlash = 0;
  }
  if (psramCfg == 1) {
    isInternalPsram = 1;
  } else {
    isInternalPsram = 0;
  }
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
  if (isInternalFlash == 1 && isInternalPsram == 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
  }
  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
}
// must be placed in pds section
void ATTR_PDS_RAM_SECTION pm_pds_fastboot_entry(void) {
  // reload gp register
  __asm__ __volatile__(".option push\n\t"
                       ".option norelax\n\t"
                       "la gp, __global_pointer$\n\t"
                       ".option pop\n\t");

#if XTAL_TYPE != INTERNAL_RC_32M
  /* power on Xtal_32M*/
  (*(volatile uint32_t *)(AON_BASE + AON_RF_TOP_AON_OFFSET)) |= (3 << 4);
#endif

  // recovery flash pad and param
  RomDriver_SF_Cfg_Init_Flash_Gpio(0, 1);
  pm_spi_flash_init(1);
  sf_io_select();

  /* Recovery hardware , include tcm , gpio and clock */
  if (hardware_recovery) {
    hardware_recovery();
  }

  // Restore cpu registers
  pm_pds_restore_cpu_reg();
}

void pm_set_hardware_recovery_callback(void (*hardware_recovery_cb)(void)) { hardware_recovery = hardware_recovery_cb; }

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_rtc.c
================================================
/**
 * @file hal_rtc.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_rtc.h"
#include "bl702_hbn.h"

static uint64_t current_timestamp = 0;
/**
 * @brief rtc init withc sleep time
 *
 * @param sleep_time
 */
void rtc_init(uint64_t sleep_time) {
  uint32_t tmpVal;
  uint32_t comp_l, comp_h;

  /* Clear & Disable RTC counter */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Clear RTC control bit0 */
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0);

  /* Get current RTC timer */
  /* Tigger RTC val read */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);

  /* Read RTC val */
  comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
  comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);

  /* calculate RTC Comp time */
  comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF);
  comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF);

  /* Set RTC Comp time  */
  BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l);
  BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Set interrupt delay option */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T);
  /* Set RTC compare mode */
  tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  /* Enable RTC Counter */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Set RTC control bit0 */
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
}

void rtc_set_timestamp(uint64_t time_stamp) { current_timestamp = time_stamp; }
/**
 * @bref Get rtc value
 *
 */
uint64_t rtc_get_timestamp(void) {
  uint32_t tmpVal;
  uint64_t time_l;
  uint64_t time_h;

  /* Tigger RTC val read */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);

  /* Read RTC val */
  time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
  time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);

  return (((time_h << 32 | time_l) >> 15) + current_timestamp);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_aes.c
================================================
/**
 * @file hal_sec_aes.c
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_sec_aes.h"
#include "bl702_sec_eng.h"

static SEC_Eng_AES_Ctx aesCtx;

int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type) {
  handle->aes_type = aes_tye;
  handle->key_type = key_type;

  return 0;
}

static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle) {
  SEC_ENG_AES_Key_Type type = 0;

  switch (handle->key_type) {
  case SEC_AES_KEY_128:
    type = SEC_ENG_AES_KEY_128BITS;
    break;

  case SEC_AES_KEY_256:
    type = SEC_ENG_AES_KEY_256BITS;
    break;

  case SEC_AES_KEY_192:
    type = SEC_ENG_AES_KEY_192BITS;
    break;

  default:
    return SEC_ENG_AES_KEY_128BITS;
  }

  return type;
}

int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir) {
  SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle);

  switch (handle->aes_type) {
  case SEC_AES_CBC:
    Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
    Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type, SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
    break;

  case SEC_AES_CTR:
    Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
    Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type, SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
    break;

  case SEC_AES_ECB:
    break;

  default:
    return -1;
  }

  /* if key len is 0, means key is from efuse and *key value is key_sel value */
  if (key_len == 0) {
    Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce);
  } else {
    Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce);
  }

  return 0;
}

int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) {
  if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
    return -1;
  }

  return 0;
}

int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) {
  if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) {
    return -1;
  }

  return 0;
}

int sec_aes_deinit(sec_aes_handle_t *handle) {
  Sec_Eng_AES_Finish(SEC_ENG_AES_ID0);

  memset(handle, 0, sizeof(sec_aes_handle_t));

  return 0;
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c
================================================
/**
 * @file hal_sec_dsa.c
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_sec_dsa.h"
#include "bl702_sec_eng.h"

// #define DSA_DBG                                   1
// #define DSA_DBG_DETAIL                            1
void bflb_platform_dump(uint8_t *data, uint32_t len);

#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL))
uint32_t pka_tmp[64] = {0};
#endif

/*
n=p*q;
F(n)=(p-1)*(q-1)
e*d%F(n)=1[e is public key and d is private key]
dP=d%(p-1)
dQ=d%(q-1)
m1=c^(dP)%p
m2=c^(dQ)%q
h=qInv*(m1-m2)%p
m=m2+h*q
m=c^d
*/
static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size) {
  switch (size) {
  case 64:
    return SEC_ENG_PKA_REG_SIZE_8;

  case 128:
    return SEC_ENG_PKA_REG_SIZE_16;

  case 256:
    return SEC_ENG_PKA_REG_SIZE_32;

  case 512:
    return SEC_ENG_PKA_REG_SIZE_64;

  case 768:
    return SEC_ENG_PKA_REG_SIZE_96;

  case 1024:
    return SEC_ENG_PKA_REG_SIZE_128;

  case 1536:
    return SEC_ENG_PKA_REG_SIZE_192;

  case 2048:
    return SEC_ENG_PKA_REG_SIZE_256;

  case 3072:
    return SEC_ENG_PKA_REG_SIZE_384;

  case 4096:
    return SEC_ENG_PKA_REG_SIZE_512;

  default:
    return SEC_ENG_PKA_REG_SIZE_32;
  }

  return SEC_ENG_PKA_REG_SIZE_32;
}

/* c code:
number = 1
base = a
while b:
    if b & 1:
        number = number * base % c
    b >>= 1
    base = base * base % c
return number
*/
int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r) {
  uint32_t                  i, j, k;
  uint32_t                  tmp;
  uint32_t                  isOne    = 0;
  uint8_t                  *p        = (uint8_t *)b;
  SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
  SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
  uint32_t                  dataSize = (size >> 3) >> 2;
#if 1
  uint8_t oneBuf[128] ALIGN4 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01};
#endif
  /* 0:c
   * 4:a
   * 5:number
   * 6&7:temp
   */

  /* base = a */
  Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);

  /* number = 1 */
  Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0);
  // Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
  MSG("number:\r\n");
  bflb_platform_dump(pka_tmp, dataSize * 4);
#endif

  Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);

  Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1);
  Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
  MSG("base:\r\n");
  bflb_platform_dump(pka_tmp, dataSize * 4);
#endif
  /* Remove zeros bytes*/
  k = 0;

  while (p[k] == 0 && k < (size >> 3)) {
    k++;
  }

  i = (size >> 3) - 1;

  for (; i >= k; i--) {
    tmp = p[i];
    j   = 0;

    for (j = 0; j < 8; j++) {
      isOne = tmp & (1 << j);

      if (isOne) {
        /* number = number * base % c */
        Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0);
        Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1);
#ifdef DSA_DBG
        Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize);
        MSG("number:\r\n");
        bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
      }

      /* base = base * base % c */
      Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0);
      Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1);
#ifdef DSA_DBG
      Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
      MSG("base:\r\n");
      bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
    }
  }

  Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize);
#ifdef DSA_DBG
  MSG("r:\r\n");
  bflb_platform_dump(r, dataSize * 4);
#endif
  return 0;
}

/*r=a^b%c*/
int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r) {
  SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
  SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
  uint32_t                  dataSize = (size >> 3) >> 2;

  /* 0:c
   * 1:NPrime_c
   * 2:invR_c
   * 4:a(mont domain)
   * 5:b
   * 6:a^b%c(mont domain)
   * 7:a^b%c(gf domain)
   * 10&11:2^size for GF2Mont*/
  Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0);
  Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1);
  Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1);

  /* change a into mont domain*/
  Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0);
  Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
  Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
  Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
  MSG("GF2Mont Result of a:\r\n");
  bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif

  Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0);
  /* a^b%c*/
  Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1);

  /* change result into gf domain*/
  Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
  Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
  /*index 2 is invertR*/
  Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0);
  Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize);
#ifdef DSA_DBG
  MSG("r:\r\n");
  bflb_platform_dump(r, dataSize /*dataSize*4*/);
#endif
  return 0;
}

/**
 * dP=d%(p-1)
 * dQ=d%(q-1)
 * qInv=qp^(1-1):qInv*q%p=1
 * invR_p*r%p=1(r is 1024/2048/256)
 * invR_q*r%q=1(r is 1024/2048/256)
 */
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r) {
  /*
   * m1 = pow(c, dP, p)
   * m2 = pow(c, dQ, q)
   * h = (qInv * (m1 - m2)) % p
   * m = m2 + h * q
   * */
  SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size);
  SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2);
  uint32_t                  dataSize = (size >> 3) >> 2;
#if 0
    uint8_t  m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14,
                       0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf,
                       0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07,
                       0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5
                      };
    uint8_t  m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee,
                       0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd,
                       0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2,
                       0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1
                      };
#else
  uint32_t m1[32];
  uint32_t m2[32];
#endif
  /*
   * 4:m1
   * 5:m2
   * 6:qInv
   * 7:p
   * 8:q
   * 9:h
   * 10&11:qInv*(m1-m2)
   */
  sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1);
  sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2);

  Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0);
  Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0);
  Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0);
  Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0);
  Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0);

  /*(m1 - m2)%p*/
  Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize);
  MSG("m1 - m2:\r\n");
  bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/);
#endif
  /* (qInv * (m1 - m2)) % p*/
  Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
  Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
  Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
  MSG("qInv * (m1 - m2):\r\n");
  bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
#endif
  Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize);
  MSG("h:\r\n");
  bflb_platform_dump(pka_tmp, dataSize * 4);
#endif

  /* h*q */
  Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1);
  Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1);
  Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1);
#ifdef DSA_DBG
  Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2);
  MSG("h*q:\r\n");
  bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/);
#endif
  /* m2 + h*q*/
  Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1);

  Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2);
#ifdef DSA_DBG
  MSG("r:\r\n");
  bflb_platform_dump(r, dataSize * 4 * 2);
#endif
  return 0;
}

int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size) {
  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();

  memset(handle, 0, sizeof(sec_dsa_handle_t));
  handle->size    = size;
  handle->crtSize = (size >> 1);

  return 0;
}

int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s) {
  uint32_t dsa_tmp[64] = {0};

  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();

  memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4);

  if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) {
    return 0;
  } else {
    return -1;
  }
}

/**
 */
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s) {
  uint32_t dsa_tmp[64];
  uint8_t  i            = 0;
  uint8_t  resultOffset = 0;

  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();

  if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) {
    resultOffset = (handle->size >> 5) - hashLenInWord;

    for (i = 0; i < hashLenInWord; i++) {
      if (dsa_tmp[resultOffset + i] != hash[i]) {
        return -1;
      }
    }

    return 0;
  } else {
    return -1;
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c
================================================
#include "hal_sec_ecdsa.h"
#include "bl702_sec_eng.h"

#define ECP_SECP256R1_REG_TYPE           SEC_ENG_PKA_REG_SIZE_32
#define ECP_SECP256R1_N_REG_INDEX        0
#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1
#define ECP_SECP256R1_INVR_N_REG_INDEX   2
#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3
#define ECP_SECP256R1_INVR_P_REG_INDEX   4
#define ECP_SECP256R1_SIZE               32
/* Used in verify */
#define ECP_SECP256R1_S_REG_INDEX     5
#define ECP_SECP256R1_BAR_S_REG_INDEX 6
#define ECP_SECP256R1_HASH_REG_INDEX  6 // use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp
#define ECP_SECP256R1_U1_REG_INDEX    7
#define ECP_SECP256R1_LT_REG_TYPE     SEC_ENG_PKA_REG_SIZE_64
#define ECP_SECP256R1_LT_REG_INDEX    7
#define ECP_SECP256R1_SLT_REG_TYPE    SEC_ENG_PKA_REG_SIZE_128
#define ECP_SECP256R1_SLT_REG_INDEX   3

// #define ECDSA_DBG                                   1
// #define ECDSA_DBG_DETAIL                            1

#define secp256r1
#define secp256k1
#define SEC_ECC_POINT_MUL_PARAM_CFG(G)                                                                                                                                                                 \
  sec_ecc_point_mul_cfg((uint32_t *)G##P, (uint32_t *)G##PrimeN_P, (uint32_t *)G##_1, (uint32_t *)G##_BAR2, (uint32_t *)G##_BAR3, (uint32_t *)G##_BAR4, (uint32_t *)G##_BAR8, (uint32_t *)G##_1P1,     \
                        (uint32_t *)G##_1M1)

#define SEC_ECC_BASIC_PARAM_CFG(G) sec_ecc_basic_parameter_cfg((uint32_t *)G##N, (uint32_t *)G##PrimeN_N, (uint32_t *)G##InvR_N)

void bflb_platform_dump(uint8_t *data, uint32_t len);

#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL))
uint32_t pka_tmp[32] = {0};
#endif
/********************************************** secp256r1 *******************************************/
const uint8_t secp256r1P[32] ALIGN4        = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
const uint8_t secp256r1B[32] ALIGN4        = {0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc,
                                              0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b};
const uint8_t secp256r1Gx[32] ALIGN4       = {0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2,
                                              0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96};
const uint8_t secp256r1Gy[32] ALIGN4       = {0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
                                              0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5};
const uint8_t secp256r1N[32] ALIGN4        = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51};
const uint8_t secp256r1PrimeN_N[32] ALIGN4 = {0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6,
                                              0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f};
const uint8_t secp256r1InvR_N[32] ALIGN4   = {0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25,
                                              0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79};
const uint8_t secp256r1PrimeN_P[32] ALIGN4 = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01};
const uint8_t secp256r1InvR_P[32] ALIGN4   = {0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02,
                                              0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00};
const uint8_t secp256r1_1[32] ALIGN4       = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01};
const uint8_t secp256r1_BAR2[32] ALIGN4    = {0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02};
const uint8_t secp256r1_BAR3[32] ALIGN4    = {0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03};
const uint8_t secp256r1_BAR4[32] ALIGN4    = {0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04};
const uint8_t secp256r1_BAR8[32] ALIGN4    = {0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08};
const uint8_t secp256r1_1P1[32] ALIGN4     = {0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02};
const uint8_t secp256r1_1M1[32] ALIGN4     = {0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
const uint8_t secp256r1_Zerox[32] ALIGN4   = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
const uint8_t secp256r1_Zeroy[32] ALIGN4   = {0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
                                              0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01};
const uint8_t secp256r1_Gx[32] ALIGN4      = {0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10,
                                              0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c};
const uint8_t secp256r1_Gy[32] ALIGN4      = {0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25,
                                              0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a};

/********************************************** secp256k1 *******************************************/
const uint8_t secp256k1P[32] ALIGN4        = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
                                              0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F};
const uint8_t secp256k1B[32] ALIGN4        = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07};
const uint8_t secp256k1Gx[32] ALIGN4       = {0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07,
                                              0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98};
const uint8_t secp256k1Gy[32] ALIGN4       = {0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
                                              0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5};
const uint8_t secp256k1N[32] ALIGN4        = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
                                              0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41};
const uint8_t secp256k1PrimeN_N[32] ALIGN4 = {0xd9, 0xe8, 0x89, 0xd,  0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5e,
                                              0x50, 0xa5, 0x1a, 0xc8, 0x34, 0xb9, 0xec, 0x24, 0x4b, 0xd,  0xff, 0x66, 0x55, 0x88, 0xb1, 0x3f};
const uint8_t secp256k1InvR_N[32] ALIGN4   = {0xd9, 0xe8, 0x89, 0xd,  0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5d,
                                              0x3b, 0xbb, 0xd4, 0x56, 0x7f, 0xa5, 0xc,  0x3c, 0x80, 0xfd, 0x22, 0x93, 0x80, 0x97, 0xc0, 0x16};
const uint8_t secp256k1PrimeN_P[32] ALIGN4 = {0xc9, 0xbd, 0x19, 0x5,  0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
                                              0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9,  0x1d, 0xd2, 0x25, 0x35, 0x31};
const uint8_t secp256k1InvR_P[32] ALIGN4   = {0xc9, 0xbd, 0x19, 0x5,  0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61,
                                              0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9,  0x1d, 0x8,  0x68, 0x19, 0x2a};
const uint8_t secp256k1_1[32] ALIGN4       = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01};
const uint8_t secp256k1_BAR2[32] ALIGN4    = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x07, 0xa2};
const uint8_t secp256k1_BAR3[32] ALIGN4    = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x73};
const uint8_t secp256k1_BAR4[32] ALIGN4    = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0f, 0x44};
const uint8_t secp256k1_BAR8[32] ALIGN4    = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x1e, 0x88};
const uint8_t secp256k1_1P1[32] ALIGN4     = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd2};
const uint8_t secp256k1_1M1[32] ALIGN4     = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd0};
const uint8_t secp256k1_Zerox[32] ALIGN4   = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
const uint8_t secp256k1_Zeroy[32] ALIGN4   = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                              0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd1};
const uint8_t secp256k1_Gx[32] ALIGN4      = {0x99, 0x81, 0xe6, 0x43, 0xe9, 0x08, 0x9f, 0x48, 0x97, 0x9f, 0x48, 0xc0, 0x33, 0xfd, 0x12, 0x9c,
                                              0x23, 0x1e, 0x29, 0x53, 0x29, 0xbc, 0x66, 0xdb, 0xd7, 0x36, 0x2e, 0x5a, 0x48, 0x7e, 0x20, 0x97};
const uint8_t secp256k1_Gy[32] ALIGN4      = {0xcf, 0x3f, 0x85, 0x1f, 0xd4, 0xa5, 0x82, 0xd6, 0x70, 0xb6, 0xb5, 0x9a, 0xac, 0x19, 0xc1, 0x36,
                                              0x8d, 0xfc, 0x5d, 0x5d, 0x1f, 0x1d, 0xc6, 0x4d, 0xb1, 0x5e, 0xa6, 0xd2, 0xd3, 0xdb, 0xab, 0xe2};

static BL_Err_Type sec_ecc_basic_parameter_cfg(uint32_t *n, uint32_t *prime_n, uint32_t *invr_n) {
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)n, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)prime_n, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)invr_n, ECP_SECP256R1_SIZE / 4, 0);
  return SUCCESS;
}
static BL_Err_Type sec_ecc_basic_parameter_init(uint8_t id) {
  if (id >= ECP_TYPE_MAX) {
    return ERROR;
  }

  if (id == ECP_SECP256R1) {
    SEC_ECC_BASIC_PARAM_CFG(secp256r1);
  } else if (id == ECP_SECP256K1) {
    SEC_ECC_BASIC_PARAM_CFG(secp256k1);
  }

  return SUCCESS;
}

static BL_Err_Type sec_ecc_point_mul_cfg(uint32_t *p, uint32_t *primeN_p, uint32_t *ori_1, uint32_t *bar2, uint32_t *bar3, uint32_t *bar4, uint32_t *bar8, uint32_t *bar1p1, uint32_t *bar1m1) {
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)p, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)primeN_p, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)ori_1, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)bar2, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)bar3, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)bar4, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)bar8, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)bar1p1, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)bar1m1, ECP_SECP256R1_SIZE / 4, 0);

  return SUCCESS;
}

static int sec_ecc_point_mul_init(uint8_t id) {
  if (id >= ECP_TYPE_MAX) {
    return ERROR;
  }

  if (id == ECP_SECP256R1) {
    SEC_ECC_POINT_MUL_PARAM_CFG(secp256r1);
  } else if (id == ECP_SECP256K1) {
    SEC_ECC_POINT_MUL_PARAM_CFG(secp256k1);
  }

  return SUCCESS;
}

static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf) {
  uint8_t res[4];

  /* index 2:BAR_Zero_x
   * index 3:BAR_Zero_y
   * index 4:BAR_Zero_z
   * index 5:BAR_G_x
   * index 6:BAR_G_y
   * index 7:BAR_G_z
   * index 8:1
   * index 9:2
   * index 10:3
   * index 11:4
   * index 12:8
   * index 19:1P1
   * index 20:1m1*/

  // cout = 1 if X1 = 0
  Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); // s0 < s1 => cout = 1
  // cout = 1 if Y1 < Bar_1p1
  Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19);
  // cout=1 if Y1 > Bar_1m1
  Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3);
  // cout =1 if Z1 = 0
  Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8);
  *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3];

  // cout = 1 if X2 = 0
  Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8);
  // cout = 1 if Y2 < Bar_1p1
  Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19);
  // cout = 1 if Y2 > Bar_1m1
  Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6);
  // cout = 1 if Z2 = 0
  Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8);
  *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3];
}

static void sec_ecdsa_copy_x2_to_x1(uint8_t id) {
  // X2->X1
  Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0);
  // Y2->Y1
  Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0);
  // Z2->Z1
  Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); // Caution!!! wait movdat ready to execute next command
}

static void sec_ecdsa_point_add(uint8_t id) {
  /* index 2:BAR_Zero_x
   * index 3:BAR_Zero_y
   * index 4:BAR_Zero_z
   * index 5:BAR_G_x
   * index 6:BAR_G_y
   * index 7:BAR_G_z
   * index 8:1
   * index 9:2
   * index 10:3
   * index 11:4
   * index 12:8
   * index 19:1P1
   * index 20:1m1*/

  // U1 = Y2*Z1
  // PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx
  Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0);

  // U2 = Y1*Z2
  // PKA_MMUL(0,3,14,3, 3,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0);

  // V1 = X2*Z1
  // PKA_MMUL(0,3,15,3, 5,3, 4,3,0);
  Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0);

  // V2 = X1*Z2
  // PKA_MMUL(0,3,16,3, 2,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0);

  // U = U1-U2
  // PKA_MSUB(0,3,13,3,13,3,14,3,0);
  Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0);

  // V = V1-V2
  // PKA_MSUB(0,3,15,3,15,3,16,3,0);
  Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0);

  // W = Z1*Z2
  // PKA_MMUL(0,3, 2,3, 4,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0);

  // V^2
  // PKA_MMUL(0,3, 3,3,15,3,15,3,0);
  Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0);

  // V^3
  // PKA_MMUL(0,3, 4,3, 3,3,15,3,0);
  Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0);

  // U^2
  // PKA_MMUL(0,3,17,3,13,3,13,3,0);
  Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0);

  // U^2*W
  // PKA_MMUL(0,3,17,3,17,3, 2,3,0);
  Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0);

  // U^2*W-V^3
  // PKA_MSUB(0,3,17,3,17,3, 4,3,0);
  Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0);

  // 2*V^2
  // PKA_MMUL(0,3,18,3, 9,3, 3,3,0);
  Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0);

  // 2*V^2*V2
  // PKA_MMUL(0,3,18,3,18,3,16,3,0);
  Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0);

  // A = U^2*W-V^3-2*V^2*V2
  // PKA_MSUB(0,3,18,3,17,3,18,3,0);
  Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0);

  // V^2*V2
  // PKA_MMUL(0,3, 3,3, 3,3,16,3,0);
  Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0);

  // V^3*U2
  // PKA_MMUL(0,3,14,3, 4,3,14,3,0);
  Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0);

  // Z3 = V^3*W
  // PKA_MMUL(0,3, 4,3, 4,3, 2,3,0);
  Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0);

  // X3 = V*A
  // PKA_MMUL(0,3, 2,3,15,3,18,3,0);
  Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0);

  // V^2*V2-A
  // PKA_MSUB(0,3, 3,3, 3,3,18,3,0);
  Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0);

  // U*(V^2*V2-A)
  // PKA_MMUL(0,3, 3,3,13,3, 3,3,0);
  Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0);

  // Y3 = U*(V^2*V2-A)-V^3*U2
  // PKA_MSUB(1,3, 3,3, 3,3,14,3,0);
  Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1);
}
/**
 * @brief calculate secp256r1's W
 *
 * @note index 13:W = 3X^2-3Z^2
 */
static void sec_ecdsa_cal_secp256r1_w(void) {
  // X1^2
  // PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx
  Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);

  // Z1^2
  // PKA_MMUL(0,3,14,3, 7,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0);

  // X1^2-Z1^2
  // PKA_MSUB(0,3,13,3,13,3,14,3,0);
  Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0);

  // W = 3*(X1^2-Z1^2)
  // PKA_MMUL(0,3,13,3,10,3,13,3,0);
  Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
}

/**
 * @brief calculate secp256k1's W
 *
 * @note index 13:W = 3X^2
 */
static void sec_ecdsa_cal_secp256k1_w(void) {
  // X1^2
  Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0);

  // W = 3* (X1^2)
  Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0);
}

static BL_Err_Type sec_ecdsa_point_double(sec_ecp_type id) {
  /* index 2:BAR_Zero_x
   * index 3:BAR_Zero_y
   * index 4:BAR_Zero_z
   * index 5:BAR_G_x
   * index 6:BAR_G_y
   * index 7:BAR_G_z
   * index 8:1
   * index 9:2
   * index 10:3
   * index 11:4
   * index 12:8
   * index 19:1P1
   * index 20:1m1*/

  if (id >= ECP_TYPE_MAX) {
    return ERROR;
  }

  if (id == ECP_SECP256R1) {
    sec_ecdsa_cal_secp256r1_w();
  } else if (id == ECP_SECP256K1) {
    sec_ecdsa_cal_secp256k1_w();
  }

  // S = Y1*Z1
  // PKA_MMUL(0,3,14,3, 6,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0);

  // X1*Y1
  // PKA_MMUL(0,3,15,3, 5,3, 6,3,0);
  Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0);

  // W^2
  // PKA_MMUL(0,3, 7,3,13,3,13,3,0);
  Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0);

  // B = X1*Y1*S
  // PKA_MMUL(0,3,15,3,15,3,14,3,0);
  Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0);

  // 8*B
  // PKA_MMUL(0,3, 5,3,12,3,15,3,0);
  Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0);

  // H = W^2-8*B
  // PKA_MSUB(0,3, 7,3, 7,3, 5,3,0);
  Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0);

  // 2*H
  // PKA_MMUL(0,3, 5,3, 9,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0);

  // X2 = 2*H*S
  // PKA_MMUL(0,3, 5,3, 5,3,14,3,0);
  Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0);

  // 4*B
  // PKA_MMUL(0,3,15,3,11,3,15,3,0);
  Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0);

  // S^2
  // PKA_MMUL(0,3,16,3,14,3,14,3,0);
  Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0);

  // 4*B-H
  // PKA_MSUB(0,3,15,3,15,3, 7,3,0);
  Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0);

  // Y1^2
  // PKA_MMUL(0,3, 6,3, 6,3, 6,3,0);
  Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0);

  // W*(4*B-H)
  // PKA_MMUL(0,3,15,3,15,3,13,3,0);
  Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0);

  // 8*Y1^2
  // PKA_MMUL(0,3, 6,3,12,3, 6,3,0);
  Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0);

  // 8*Y1^2*S^2
  // PKA_MMUL(0,3, 6,3, 6,3,16,3,0);
  Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0);

  // Y2 = W*(4*B-H)-8*Y1^2*S^2
  // PKA_MSUB(0,3, 6,3,15,3, 6,3,0);
  Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0);

  // S^3
  // PKA_MMUL(0,3, 7,3,14,3,16,3,0);
  Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0);

  // Z2 = 8*S^3
  // PKA_MMUL(1,3, 7,3,12,3, 7,3,0);
  Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1);

  return SUCCESS;
}
#ifdef ECDSA_DBG_DETAIL
static void sec_ecdsa_dump_temp_result() {
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("2=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("3=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("4=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);

  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("5=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("6=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("7=\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
}
#endif
static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m) {
  uint32_t i, j, k;
  uint32_t tmp;
  uint32_t isOne = 0;
  uint8_t *p     = (uint8_t *)m;
  uint8_t  pka_p1_eq_inf, pka_p2_eq_inf;

  /* Remove zeros bytes*/
  k = 0;

  while (p[k] == 0 && k < 31) {
    k++;
  }

  i = 31;

  for (; i >= k; i--) {
    tmp = p[i];
    j   = 0;

    for (j = 0; j < 8; j++) {
      isOne = tmp & (1 << j);

      if (isOne) {
        sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf);

        if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) {
          // sum = X2
          sec_ecdsa_copy_x2_to_x1(id);
#ifdef ECDSA_DBG_DETAIL
          MSG("sum = X2\r\n");
          sec_ecdsa_dump_temp_result();
#endif
        } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) {
          // sum = X1
          // MSG("sum = X1\r\n");
        } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) {
          // sum = X1 + X2
          sec_ecdsa_point_add(id);
#ifdef ECDSA_DBG_DETAIL
          MSG("sum = X1+X2\r\n");
          sec_ecdsa_dump_temp_result();
#endif
        } else {
          // MSG("Error! infinite point + infinite point\r\n");
          return -1;
        }
      }

      sec_ecdsa_point_double(id);
#ifdef ECDSA_DBG_DETAIL
      sec_ecdsa_dump_temp_result();
#endif
    }

    if (i == 0) {
      break;
    }
  }

  return 0;
}

/*cal d*G if pkX(pky)==NULL
 * cal d(bG) if pkX(pky)!=NULL */
static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) {
#ifdef ECDSA_DBG
  uint32_t pk_z[8];
#endif

  if (id >= ECP_TYPE_MAX) {
    return ERROR;
  }

  /* Pointer check */
  if (private_key == NULL) {
    return -1;
  }

  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();

  sec_ecc_basic_parameter_init(id);

  // Clear D[7]
  // PKA_CREG(1,4, 7,0);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);

  sec_ecc_point_mul_init(id);

  if (id == ECP_SECP256R1) {
    // X1
    // PKA_CTREG(3, 2,8,bar_Zero_x);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
    // Y1
    // PKA_CTREG(3, 3,8,bar_Zero_y);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    // X1
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256k1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
    // Y1
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256k1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
  }
  // Z1
  // PKA_CTREG(3, 4,8,bar_Zero_z);
  // PKA_MOVDAT(1,3, 4,3, 2);
  Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);

  if (pkX == NULL) {
    if (id == ECP_SECP256R1) {
      // X2
      // PKA_CTREG(3, 5,8,bar_G_x);
      Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
      // Y2
      // PKA_CTREG(3, 6,8,bar_G_y);
      Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
    } else if (id == ECP_SECP256K1) {
      // X2
      Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256k1_Gx, ECP_SECP256R1_SIZE / 4, 0);
      // Y2
      Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1_Gy, ECP_SECP256R1_SIZE / 4, 0);
    }
  } else {
    /* chaneg peer's public key to mont domain*/
    // PUB_x
    // PKA_CTREG(3, 5,8,PUB_x);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0);
    // bar_pub_x
    // PKA_GF2MONT(3, 5,3, 5);
    /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/
    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
    MSG("PK.x in Mont:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

    // PUB_y
    // PKA_CTREG(3, 6,8,PUB_y);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0);
    // bar_pub_y
    // PKA_GF2MONT(3, 6,3, 6);
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
    MSG("PK.y in Mont:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif
  }

  // Z2
  // PKA_CTREG(3, 7,8,bar_G_z);
  // PKA_MOVDAT(1,3, 7,3, 3);
  Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);
  /* Clear temp register since it's used in point-mul*/
  Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);

  sec_ecdsa_verify_point_mul(id, private_key);
  // get bar_u1_x
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u1_x\r\n");
  bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
#endif
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u1_y\r\n");
  bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
#endif
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4);
  MSG("bar_u1_z\r\n");
  bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE);
#endif

  // get R.x
  // R.z ^ -1
  Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
  if (id == ECP_SECP256R1) {
    // inv_r
    // PKA_CTREG(3, 6,8,inv_r);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
  }
  // R.z ^ -1
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  // PKA_MONT2GF(3, 5,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);

  // R.x (Montgomery to GF)
  // PKA_MONT2GF(3, 6,3, 2,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);

  // R.x (GF to Affine domain)
  // PKA_MONT2GF(3, 2,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("R.x=\r\n");
  bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
#endif
  if (id == ECP_SECP256R1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
  }

  Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("R.x%n=\r\n");
  bflb_platform_dump(pRx, ECP_SECP256R1_SIZE);
#endif
  if (id == ECP_SECP256R1) {
    /*after %n,re write p*/
    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256k1P, ECP_SECP256R1_SIZE / 4, 0);
  }

  // get R.y
  // R.z ^ -1
  Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
  // inv_r
  // PKA_CTREG(3, 6,8,inv_r);
  if (id == ECP_SECP256R1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
  }
  // R.z ^ -1
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  // PKA_MONT2GF(3, 5,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
  // R.x (Montgomery to GF)
  // PKA_MONT2GF(3, 6,3, 2,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);

  // R.x (GF to Affine domain)
  // PKA_MONT2GF(3, 2,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("R.y=\r\n");
  bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
#endif
  if (id == ECP_SECP256R1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
  } else if (id == ECP_SECP256K1) {
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0);
  }
  Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("R.y%n=\r\n");
  bflb_platform_dump(pRy, ECP_SECP256R1_SIZE);
#endif
  return 0;
}

static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len) {
  uint32_t i = 0;

  for (i = 0; i < len; i++) {
    if (a[i] != 0) {
      return 0;
    }
  }

  return 1;
}

static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len) {
  uint32_t i = 0, j = 0;

  for (i = 0; i < len; i++) {
    if (a[i] != 0) {
      break;
    }
  }

  for (j = 0; j < len; j++) {
    if (b[j] != 0) {
      break;
    }
  }

  if (i == len && j == len) {
    return (0);
  }

  if (i > j) {
    return (-1);
  }

  if (j > i) {
    return (1);
  }

  for (; i < len; i++) {
    if (a[i] > b[i]) {
      return (1);
    }

    if (a[i] < b[i]) {
      return (-1);
    }
  }

  return 0;
}

int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id) {
  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();
  Sec_Eng_Trng_Enable();

  handle->ecpId = id;

  return 0;
}

int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle) {
  Sec_Eng_PKA_Reset();

  return 0;
}

int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) {
  uint32_t bar_u1_x[8];
  uint32_t bar_u1_y[8];
  uint32_t bar_u1_z[8];
  uint32_t bar_u2_x[8];
  uint32_t bar_u2_y[8];
  uint32_t bar_u2_z[8];
  uint32_t pka_u1[8] = {0};
  uint32_t pka_u2[8] = {0};
  uint32_t i         = 0;

  /* Pointer check */
  if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) {
    return -1;
  }

  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();

  /*Step 0: make sure r and s are in range 1..n-1*/

  /* r and s should not be 0*/
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0);
  // cout = 1 if r = 0
  Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); // s0 < s1 => cout = 1

  if (i == 1) {
    return -1;
  }

  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
  // cout = 1 if r = 0
  Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); // s0 < s1 => cout = 1

  if (i == 1) {
    return -1;
  }

  sec_ecc_basic_parameter_init(handle->ecpId);

  /* r and s should not be 0*/
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
  // cout = 1 if r < N
  Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);

  if (i != 1) {
    return -1;
  }

  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
  // cout = 1 if r < N
  Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);

  if (i != 1) {
    return -1;
  }

  /* u1 = e / s mod n, u2 = r / s mod n
   * R = u1 G + u2 Q*/

  /* Step1: Get S^-1*/
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0);
  /* Change s to Mont domain */
  /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX,
                      ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("GF2Mont Result of s:\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

  /* Get S^-1 in Mont domain */
  Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("s^-1 in Mont:\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

  /* Change S^-1 into GF domain,now  ECP_SECP256R1_S_REG_INDEX store s^-1*/
  /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX,
                      ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("S^-1:\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

  /* Step2: Get u1*/
  // u1=hash(e)*s^-1;
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0);
  Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("u1:\r\n");
  bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE);
#endif

  /* Step3: Get u2*/
  // u2=r*s^-1;
  //  use hash and u1 temp register
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
  Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0);
  Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("u2:\r\n");
  bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE);
#endif

  /* Step4: Get u1*G*/

  // Clear D[7]
  // PKA_CREG(1,4, 7,0);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);

  sec_ecc_point_mul_init(handle->ecpId);

  // X1
  // PKA_CTREG(3, 2,8,bar_Zero_x);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
  // Y1
  // PKA_CTREG(3, 3,8,bar_Zero_y);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
  // Z1
  // PKA_CTREG(3, 4,8,bar_Zero_z);
  // PKA_MOVDAT(1,3, 4,3, 2);
  Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);

  // X2
  // PKA_CTREG(3, 5,8,bar_G_x);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0);
  // Y2
  // PKA_CTREG(3, 6,8,bar_G_y);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0);
  // Z2
  // PKA_CTREG(3, 7,8,bar_G_z);
  // PKA_MOVDAT(1,3, 7,3, 3);
  Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);

  sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1);
  // get bar_u1_x
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u1_x\r\n");
  bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE);
#endif
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u1_y\r\n");
  bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE);
#endif
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u1_z\r\n");
  bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE);
#endif

  /* Step4: Get u2*Q*/
  // X1
  // PKA_CTREG(3, 2,8,bar_Zero_x);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0);
  // Y1
  // PKA_CTREG(3, 3,8,bar_Zero_y);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0);
  // Z1
  // PKA_CTREG(3, 4,8,bar_Zero_z);
  // PKA_MOVDAT(1,3, 4,3, 2);
  Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1);

  // PUB_x
  // PKA_CTREG(3, 5,8,PUB_x);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0);
  // bar_pub_x
  // PKA_GF2MONT(3, 5,3, 5);
  /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/
  /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("PK.x in Mont:\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

  // PUB_y
  // PKA_CTREG(3, 6,8,PUB_y);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0);
  // bar_pub_y
  // PKA_GF2MONT(3, 6,3, 6);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
#ifdef ECDSA_DBG
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
  MSG("PK.y in Mont:\r\n");
  bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

  // bar_pub_z
  // PKA_CTREG(3, 7,8,PUB_z);
  // PKA_MOVDAT(1,3, 7,3, 3);
  Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1);

  /* Clear temp register since it's used in point-mul*/
  Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1);

  sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2);
  // get bar_u1_x
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u2_x\r\n");
  bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE);
#endif
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u2_y\r\n");
  bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE);
#endif
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("bar_u2_z\r\n");
  bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE);
#endif

  /* Step5: Get u1*G+u2*Q*/
  // move bar_u2_x
  // PKA_MOVDAT(0,3, 5,3, 2);
  Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0);
  // move bar_u2_y
  // PKA_MOVDAT(0,3, 6,3, 3);
  Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0);
  // move bar_u2_z
  // PKA_MOVDAT(1,3, 7,3, 4);
  Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1);

  // bar_u1_x
  // PKA_CTREG(3, 2,8,bar_u1_x);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0);
  // bar_u1_y
  // PKA_CTREG(3, 3,8,bar_u1_y);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0);
  // bar_u1_z
  // PKA_CTREG(3, 4,8,bar_u1_z);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0);

  // R = u1 * G + u2 * PUB
  // PKA_POINT_ADDITION();
  sec_ecdsa_point_add(handle->ecpId);

  /* Step6 Get R.x(R=u1G+u2P)*/
  // R.z ^ -1
  // PKA_MINV(0,3, 5,3, 4,3, 0);
  Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1);
  // inv_r
  // PKA_CTREG(3, 6,8,inv_r);
  Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0);
  // R.z ^ -1
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
  Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
  // PKA_MONT2GF(3, 5,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);

  // R.x (Montgomery to GF)
  // PKA_MONT2GF(3, 6,3, 2,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);

  // R.x (GF to Affine domain)
  // PKA_MONT2GF(3, 2,3, 5,3, 6);
  Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0);
  Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
  MSG("R.x=\r\n");
  bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE);
#endif

  /* Step7 check R.x=r*/
  /* Check Result */
  for (i = 0; i < 8; i++) {
    if (bar_u2_x[i] != r[i]) {
      return -1;
    }
  }

#ifdef ECDSA_DBG
  MSG("Verify success\r\n");
#endif
  return 0;
}

int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s) {
  uint32_t k[8];
  uint32_t Rx[8];
  uint32_t Ry[8];
  uint32_t KInvert[8];
  uint32_t maxTry1 = 100;

  /* Pointer check */
  if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) {
    return -1;
  }

  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();
  Sec_Eng_Trng_Enable();

  while (maxTry1--) {
    /* step 1 ,get random k*/
    if (random_k == NULL) {
      if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) {
        return -1;
      }
    } else {
      memcpy(k, random_k, 32);
    }

#ifdef ECDSA_DBG
    MSG("Random k:\r\n");
    bflb_platform_dump(k, ECP_SECP256R1_SIZE);
#endif

    /*step 2, calc R=kG*/
    if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) {
      return -1;
    }

    if (sec_ecc_is_zero((uint8_t *)Rx, 32)) {
      continue;
    }

    memcpy(r, Rx, 32);
#ifdef ECDSA_DBG
    MSG("r:\r\n");
    bflb_platform_dump(r, ECP_SECP256R1_SIZE);
#endif
    sec_ecc_basic_parameter_init(handle->ecpId);
    /* step 3,get k^-1*/
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
    /* Change k to Mont domain */
    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1);
    Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4);
    MSG("GF2Mont Result of k:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE);
#endif

    /* Get k^-1 in Mont domain */
    Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4);
    MSG("k^-1 in Mont:\r\n");
    bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE);
#endif

    /* Change k^-1 into GF domain,now  ECP_SECP256R1_S_REG_INDEX store k^-1*/
    /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/
    Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX,
                        ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX);
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
    MSG("k^-1:\r\n");
    bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE);
#endif

    /* Step 4,r*d     ((e + r * d) / k) */
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 5, 1);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
    MSG("r*d:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
#endif

    /* Step 5,e+r*d   ((e + r * d) / k) */
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 5, 1);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
    MSG("e+r*d:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
#endif

    /* Step 6,(e+r*d)*k^-1   ((e + r * d) / k) */
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 5, 1);
#ifdef ECDSA_DBG
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2);
    MSG("(e+r*d)*k^-1:\r\n");
    bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2);
#endif
    /*N write only this time,add following operation will not change this register*/
    Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0);
    Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1);
    Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4);
#ifdef ECDSA_DBG
    MSG("s:\r\n");
    bflb_platform_dump(s, ECP_SECP256R1_SIZE);
#endif

    /* Check s zero*/
    if (sec_ecc_is_zero((uint8_t *)s, 32)) {
      continue;
    }

    return 0;
  }

  return -1;
}

int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key) {
  if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) {
    return -1;
  }

  return 0;
}

int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) {
  return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy);
}

int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size) {
  uint32_t maxTry = 100;
  int32_t  ret    = 0;

  while (maxTry--) {
    ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size);

    if (ret < 0) {
      return -1;
    }

    if (maxRef != NULL) {
      if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) {
        return 0;
      }
    } else {
      return 0;
    }
  }

  return -1;
}

int sec_eng_trng_enable(void) { return Sec_Eng_Trng_Enable(); }

void sec_eng_trng_disable(void) { Sec_Eng_Trng_Disable(); }

int sec_eng_trng_read(uint8_t data[32]) { return Sec_Eng_Trng_Read(data); }

int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id) {
  Sec_Eng_PKA_Reset();
  Sec_Eng_PKA_BigEndian_Enable();
  Sec_Eng_Trng_Enable();

  handle->ecpId = id;

  return 0;
}

int sec_ecdh_deinit(sec_ecdh_handle_t *handle) {
  Sec_Eng_PKA_Reset();

  return 0;
}

int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) {
  return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy);
}

int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) {
  return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_sec_hash.c
================================================
/**
 * @file hal_sec_hash.c
 * @brief
 *
 * Copyright 2019-2030 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_sec_hash.h"
#include "bl702_sec_eng.h"

void SEC_SHA_IRQHandler(void);

static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = {0};

static SEC_Eng_SHA256_Ctx shaCtx;

static SEC_Eng_SHA256_Ctx sha256Ctx;

/**
 * @brief
 *
 * @param dev
 * @param oflag
 * @return int
 */
int sec_hash_open(struct device *dev, uint16_t oflag) {
  sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
  int                ret             = 0;

  switch (sec_hash_device->type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
    Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
    break;

  case SEC_HASH_SHA256:
    Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding);
    Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}
/**
 * @brief
 *
 * @param dev
 * @return int
 */
int sec_hash_close(struct device *dev) {
  // sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
  // memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash
  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @param cmd
 * @param args
 * @return int
 */
int sec_hash_control(struct device *dev, int cmd, void *args) { return 0; }

/**
 * @brief
 *
 * @param dev
 * @param pos
 * @param buffer
 * @param size
 * @return int
 */
int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) {
  sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
  int                ret             = 0;

  switch (sec_hash_device->type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
    break;

  case SEC_HASH_SHA256:
    Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}

/**
 * @brief
 *
 * @param dev
 * @param pos
 * @param buffer
 * @param size
 * @return int
 */
int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) {
  sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
  int                ret             = 0;

  switch (sec_hash_device->type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
    ret = 28;
    break;

  case SEC_HASH_SHA256:
    Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
    ret = 32;
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}

/**
 * @brief
 *
 * @param handle
 * @param type
 * @return int
 */
int sec_hash_init(sec_hash_handle_t *handle, uint8_t type) {
  int ret = 0;

  switch (type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    handle->type = type;
    Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, handle->shaBuf, handle->shaPadding);
    Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
    break;

  case SEC_HASH_SHA256:
    handle->type = type;
    Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, handle->shaBuf, handle->shaPadding);
    Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}
/**
 * @brief
 *
 * @param handle
 * @return int
 */
int sec_hash_deinit(sec_hash_handle_t *handle) {
  memset(handle->shaBuf, 0, sizeof(handle->shaBuf));
  memset(handle->shaPadding, 0, sizeof(handle->shaPadding));

  return 0;
}

/**
 * @brief
 *
 * @param handle
 * @param buffer
 * @param size
 * @return int
 */
int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size) {
  int ret = 0;

  switch (handle->type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
    break;

  case SEC_HASH_SHA256:
    Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size);
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}

/**
 * @brief
 *
 * @param handle
 * @param buffer
 * @return int
 */
int sec_hash_finish(sec_hash_handle_t *handle, void *buffer) {
  int ret = 0;

  switch (handle->type) {
  case SEC_HASH_SHA1:
    ret = -1;
    break;

  case SEC_HASH_SHA224:
    Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
    ret = 28;
    break;

  case SEC_HASH_SHA256:
    Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer);
    ret = 32;
    break;

  case SEC_HASH_SHA384:
  case SEC_HASH_SHA512:
    ret = -1;
    break;

  default:
    ret = -1;
    break;
  }

  return ret;
}

/**
 * @brief
 *
 * @param index
 * @param type
 * @param name
 * @param flag
 * @return int
 */
static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name) {
  struct device *dev;

  if (SEC_HASH_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev                          = &(sec_hashx_device[index].parent);
  sec_hashx_device[index].type = type;

  dev->open    = sec_hash_open;
  dev->close   = sec_hash_close;
  dev->control = sec_hash_control;
  dev->write   = sec_hash_write;
  dev->read    = sec_hash_read;

  dev->type   = DEVICE_CLASS_SEC_HASH;
  dev->handle = NULL;

  return device_register(dev, name);
}

/**
 * @brief
 *
 * @param index
 * @param name
 * @param flag
 * @return int
 */
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name) { return sec_hash_sha_register(index, SEC_HASH_SHA256, name); }

/**
 * @brief
 *
 * @param index
 * @param name
 * @param flag
 * @return int
 */
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name) { return sec_hash_sha_register(index, SEC_HASH_SHA224, name); }

/**
 * @brief
 *
 * @param handle
 */
void sec_hash_isr(void) {}

/**
 * @brief
 *
 */
void SEC_SHA_IRQ(void) { sec_hash_isr(); }

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_uart.c
================================================
/**
 * @file hal_uart.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_uart.h"
#include "bl702_glb.h"
#include "bl702_uart.h"
#include "hal_clock.h"
#include "hal_dma.h"
#include "uart_config.h"

#ifdef BSP_USING_UART0
static void UART0_IRQ(void);
#endif
#ifdef BSP_USING_UART1
static void UART1_IRQ(void);
#endif

static uart_device_t uartx_device[UART_MAX_INDEX] = {
#ifdef BSP_USING_UART0
    UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
    UART1_CONFIG,
#endif
};
/**
 * @brief
 *
 * @param dev
 * @param oflag
 * @return int
 */
int uart_open(struct device *dev, uint16_t oflag) {
  uart_device_t    *uart_device = (uart_device_t *)dev;
  UART_FifoCfg_Type fifoCfg     = {0};
  UART_CFG_Type     uart_cfg    = {0};

  /* disable all interrupt */
  UART_IntMask(uart_device->id, UART_INT_ALL, MASK);
  /* disable uart before config */
  UART_Disable(uart_device->id, UART_TXRX);

  uint32_t uart_clk           = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
  uart_cfg.baudRate           = uart_device->baudrate;
  uart_cfg.dataBits           = uart_device->databits;
  uart_cfg.stopBits           = uart_device->stopbits;
  uart_cfg.parity             = uart_device->parity;
  uart_cfg.uartClk            = uart_clk;
  uart_cfg.ctsFlowControl     = UART_CTS_FLOWCONTROL_ENABLE;
  uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
  uart_cfg.byteBitInverse     = UART_MSB_FIRST_ENABLE;
  uart_cfg.txSoftwareControl  = UART_TX_SWCONTROL_ENABLE;
  uart_cfg.txLinMode          = UART_TX_LINMODE_ENABLE;
  uart_cfg.rxLinMode          = UART_RX_LINMODE_ENABLE;
  uart_cfg.txBreakBitCnt      = UART_TX_BREAKBIT_CNT;
  uart_cfg.rxDeglitch         = ENABLE;

  /* uart init with default configuration */
  UART_Init(uart_device->id, &uart_cfg);

  /* Enable tx free run mode */
  UART_TxFreeRun(uart_device->id, ENABLE);
  /*set de-glitch function cycle count value*/
  UART_SetDeglitchCount(uart_device->id, 2);

  /* Set rx time-out value */
  UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT);

  fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold;
  fifoCfg.txFifoDmaEnable    = DISABLE;
  fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold;
  fifoCfg.rxFifoDmaEnable    = DISABLE;

  if (oflag & DEVICE_OFLAG_STREAM_TX) {
  }
  if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) {
#ifdef BSP_USING_UART0
    if (uart_device->id == UART0_ID) {
      Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
    }
#endif
#ifdef BSP_USING_UART1
    if (uart_device->id == UART1_ID) {
      Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
    }
#endif
  }
  if (oflag & DEVICE_OFLAG_DMA_TX) {
    fifoCfg.txFifoDmaEnable = ENABLE;
  }
  if (oflag & DEVICE_OFLAG_DMA_RX) {
    fifoCfg.rxFifoDmaEnable = ENABLE;
  }

  UART_FifoConfig(uart_device->id, &fifoCfg);
  /* enable uart */
  UART_Enable(uart_device->id, UART_TXRX);
  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @return int
 */
int uart_close(struct device *dev) {
  uart_device_t *uart_device = (uart_device_t *)dev;

  UART_Disable(uart_device->id, UART_TXRX);
  if (uart_device->id == 0) {
    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
  } else if (uart_device->id == 1) {
    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
  }
  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @param cmd
 * @param args
 * @return int
 */
int uart_control(struct device *dev, int cmd, void *args) {
  uart_device_t *uart_device = (uart_device_t *)dev;

  switch (cmd) {
  case DEVICE_CTRL_SET_INT /* constant-expression */: {
    uint32_t offset = __builtin_ctz((uint32_t)args);
    while (offset < 9) {
      if ((uint32_t)args & (1 << offset)) {
        UART_IntMask(uart_device->id, offset, UNMASK);
      }
      offset++;
    }
    if (uart_device->id == UART0_ID) {
      CPU_Interrupt_Enable(UART0_IRQn);
    } else if (uart_device->id == UART1_ID) {
      CPU_Interrupt_Enable(UART1_IRQn);
    }

    break;
  }
  case DEVICE_CTRL_CLR_INT /* constant-expression */: {
    uint32_t offset = __builtin_ctz((uint32_t)args);
    while (offset < 9) {
      if ((uint32_t)args & (1 << offset)) {
        UART_IntMask(uart_device->id, offset, MASK);
      }
      offset++;
    }
    if (uart_device->id == UART0_ID) {
      CPU_Interrupt_Disable(UART0_IRQn);
    } else if (uart_device->id == UART1_ID) {
      CPU_Interrupt_Disable(UART1_IRQn);
    }

    break;
  }
  case DEVICE_CTRL_GET_INT /* constant-expression */:
    /* code */
    break;
  case DEVICE_CTRL_RESUME /* constant-expression */:
    UART_Enable(uart_device->id, UART_TXRX);
    break;
  case DEVICE_CTRL_SUSPEND /* constant-expression */:
    UART_Disable(uart_device->id, UART_TXRX);
    break;
  case DEVICE_CTRL_CONFIG /* constant-expression */: {
    uart_param_cfg_t *cfg = (uart_param_cfg_t *)args;
    UART_CFG_Type     uart_cfg;

    uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);

    uart_cfg.uartClk            = uart_clk;
    uart_cfg.baudRate           = cfg->baudrate;
    uart_cfg.stopBits           = cfg->stopbits;
    uart_cfg.parity             = cfg->parity;
    uart_cfg.dataBits           = cfg->databits;
    uart_cfg.ctsFlowControl     = UART_CTS_FLOWCONTROL_ENABLE;
    uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
    uart_cfg.byteBitInverse     = UART_MSB_FIRST_ENABLE;
    uart_cfg.txSoftwareControl  = UART_TX_SWCONTROL_ENABLE;
    uart_cfg.txLinMode          = UART_TX_LINMODE_ENABLE;
    uart_cfg.rxLinMode          = UART_RX_LINMODE_ENABLE;
    uart_cfg.txBreakBitCnt      = UART_TX_BREAKBIT_CNT;
    uart_cfg.rxDeglitch         = ENABLE;
    UART_Init(uart_device->id, &uart_cfg);
    /*set de-glitch function cycle count value*/
    UART_SetDeglitchCount(uart_device->id, 2);
    break;
  }
  case DEVICE_CTRL_GET_CONFIG /* constant-expression */:
    break;
  case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
    uart_device->tx_dma = (struct device *)args;
    break;
  case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
    uart_device->rx_dma = (struct device *)args;
    break;
  case DEVICE_CTRL_TX_DMA_SUSPEND: {
    uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
    tmpVal          = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
    BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
    dev->oflag &= ~DEVICE_OFLAG_DMA_TX;
    break;
  }
  case DEVICE_CTRL_RX_DMA_SUSPEND: {
    uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
    tmpVal          = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
    BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
    dev->oflag &= ~DEVICE_OFLAG_DMA_RX;
    break;
  }
  case DEVICE_CTRL_TX_DMA_RESUME: {
    uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
    tmpVal          = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
    BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
    dev->oflag |= DEVICE_OFLAG_DMA_TX;
    break;
  }
  case DEVICE_CTRL_RX_DMA_RESUME: {
    uint32_t tmpVal = BL_RD_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0);
    tmpVal          = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
    BL_WR_REG(UART0_BASE + uart_device->id * 0x100, UART_FIFO_CONFIG_0, tmpVal);
    dev->oflag |= DEVICE_OFLAG_DMA_RX;
    break;
  }
  case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
    return UART_GetTxFifoCount(uart_device->id);
  case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
    return UART_GetRxFifoCount(uart_device->id);
  case DEVICE_CTRL_UART_CLEAR_TX_FIFO /* constant-expression */:
    return UART_TxFifoClear(uart_device->id);
  case DEVICE_CTRL_UART_CLEAR_RX_FIFO /* constant-expression */:
    return UART_RxFifoClear(uart_device->id);
  default:
    break;
  }

  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @param pos
 * @param buffer
 * @param size
 * @return int
 */
int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) {
  int            ret         = 0;
  uart_device_t *uart_device = (uart_device_t *)dev;
  if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
    struct device *dma_ch = (struct device *)uart_device->tx_dma;
    if (!dma_ch) {
      return -1;
    }

    if (uart_device->id == 0) {
      ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
      dma_channel_start(dma_ch);
    } else if (uart_device->id == 1) {
      ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
      dma_channel_start(dma_ch);
    }
    return ret;
  } else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
    return -2;
  } else {
    return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
  }
}
/**
 * @brief
 *
 * @param dev
 * @param pos
 * @param buffer
 * @param size
 * @return int
 */
int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) {
  int            ret         = -1;
  uart_device_t *uart_device = (uart_device_t *)dev;
  if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
    struct device *dma_ch = (struct device *)uart_device->rx_dma;
    if (!dma_ch) {
      return -1;
    }

    if (uart_device->id == 0) {
      ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size);
      dma_channel_start(dma_ch);
    } else if (uart_device->id == 1) {
      ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size);
      dma_channel_start(dma_ch);
    }
    return ret;
  } else if (dev->oflag & DEVICE_OFLAG_INT_RX) {
    return -2;
  } else {
    return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size);
  }
}
/**
 * @brief
 *
 * @param index
 * @param name
 * @param flag
 * @return int
 */
int uart_register(enum uart_index_type index, const char *name) {
  struct device *dev;

  if (UART_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev = &(uartx_device[index].parent);

  dev->open    = uart_open;
  dev->close   = uart_close;
  dev->control = uart_control;
  dev->write   = uart_write;
  dev->read    = uart_read;

  dev->type   = DEVICE_CLASS_UART;
  dev->handle = NULL;

  return device_register(dev, name);
}
/**
 * @brief
 *
 * @param handle
 */
void uart_isr(uart_device_t *handle) {
  uint32_t tmpVal  = 0;
  uint32_t maskVal = 0;
  uint32_t UARTx   = (UART0_BASE + handle->id * 0x100);

  tmpVal  = BL_RD_REG(UARTx, UART_INT_STS);
  maskVal = BL_RD_REG(UARTx, UART_INT_MASK);

  if (!handle->parent.callback) {
    return;
  }

  /* Length of uart tx data transfer arrived interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END);
  }

  /* Length of uart rx data transfer arrived interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END);
  }

  /* Tx fifo ready interrupt,auto-cleared when data is pushed */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) {
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO);
  }

  /* Rx fifo ready interrupt,auto-cleared when data is popped */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
    uint8_t buffer[UART_FIFO_MAX_LEN];
    uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
    if (len) {
      handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
    }
  }

  /* Rx time-out interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
    uint8_t buffer[UART_FIFO_MAX_LEN];
    uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
    if (len) {
      handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
    }
  }

  /* Rx parity check error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_PCE);
  }

  /* Tx fifo overflow/underflow error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FER);
  }

  /* Rx fifo overflow/underflow error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
    handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_FER);
  }
}

#ifdef BSP_USING_UART0
/**
 * @brief
 *
 */
void UART0_IRQ(void) { uart_isr(&uartx_device[UART0_INDEX]); }
#endif
#ifdef BSP_USING_UART1
/**
 * @brief
 *
 */
void UART1_IRQ(void) { uart_isr(&uartx_device[UART1_INDEX]); }
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_usb.c
================================================
/**
 * @file hal_usb.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_usb.h"
#include "bl702_dma.h"
#include "bl702_glb.h"
#include "bl702_usb.h"
#include "hal_dma.h"
#include "hal_mtimer.h"

#define USE_INTERNAL_TRANSCEIVER
// #define ENABLE_LPM_INT
// #define ENABLE_SOF3MS_INT
// #define ENABLE_ERROR_INT

#define MIN(a, b) (((a) < (b)) ? (a) : (b))

#define USB_DC_LOG_WRN(a, ...) // bflb_platform_printf(a, ##__VA_ARGS__)
#define USB_DC_LOG_DBG(a, ...)
#define USB_DC_LOG_ERR(a, ...) // bflb_platform_printf(a, ##__VA_ARGS__)
#define USB_DC_LOG(a, ...)

static usb_dc_device_t usb_fs_device;
static void            USB_FS_IRQ(void);

static dma_lli_ctrl_t usb_lli_list = {.src_addr              = 0,
                                      .dst_addr              = 0,
                                      .nextlli               = 0,
                                      .cfg.bits.fix_cnt      = 0,
                                      .cfg.bits.dst_min_mode = 0,
                                      .cfg.bits.dst_add_mode = 0,
                                      .cfg.bits.SI           = 0,
                                      .cfg.bits.DI           = 0,
                                      .cfg.bits.SWidth       = DMA_TRANSFER_WIDTH_8BIT,
                                      .cfg.bits.DWidth       = DMA_TRANSFER_WIDTH_8BIT,
                                      .cfg.bits.SBSize       = 0,
                                      .cfg.bits.DBSize       = 0,
                                      .cfg.bits.I            = 0,
                                      .cfg.bits.TransferSize = 0};

static void usb_set_power_up(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USB);
  BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
}

static void usb_set_power_off(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USB);
  BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
}

static uint8_t usb_ep_is_enabled(uint8_t ep) {
  uint8_t ep_idx = USB_EP_GET_IDX(ep);

  /* Check if ep enabled */
  if ((USB_EP_DIR_IS_OUT(ep)) && usb_fs_device.out_ep[ep_idx].ep_ena) {
    return 1;
  } else if ((USB_EP_DIR_IS_IN(ep)) && usb_fs_device.in_ep[ep_idx].ep_ena) {
    return 1;
  }

  return 0;
}

static void usb_xcvr_config(BL_Fun_Type NewState) {
  uint32_t tmpVal = 0;

  if (NewState != DISABLE) {
#if defined(USE_EXTERNAL_TRANSCEIVER)
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 0); // use external tranceiver
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
#elif defined(USE_INTERNAL_TRANSCEIVER)
#if 1
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 1); // 0 for 1.1 ls,1 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 2); // 1 for 1.1 ls
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 2); // 1 for 1.1 ls
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 2); // 1 for 1.1 ls
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 2); // 1 for 1.1 ls
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);

    ///* force BD=1, not use */
    // tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR);
    // tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO);
    // BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal);

    /* BD_voltage_thresdhold=2.8V */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);

#else
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SUS, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SPD, 0); // 0 for 1.1 ls,1 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_DATA_CONVERT, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_OEB_SEL, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_PMOS, 3);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ROUT_NMOS, 3);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_RISE, 1); // 4 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_P_FALL, 1); // 3 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_RISE, 1); // 4 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_SLEWRATE_M_FALL, 1); // 3 for 1.1 fs
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_RES_PULLUP_TUNE, 5);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_P, 2);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_V_HYS_M, 2);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);
#endif

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
#endif
  } else {
#ifdef USE_INTERNAL_TRANSCEIVER
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 0);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

    ///* force BD=1, not use */
    // tmpVal=BL_RD_REG(GLB_BASE,GLB_USB_XCVR);
    // tmpVal=BL_SET_REG_BIT(tmpVal,GLB_PU_USB_LDO);
    // BL_WR_REG(GLB_BASE,GLB_USB_XCVR,tmpVal);

    /* BD_voltage_thresdhold=2.8V */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_BD_VTH, 7);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);

#else
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_USB_USE_XCVR, 1); // use internal tranceiver
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR_CONFIG, tmpVal);

    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_USB, 1);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
#endif
  }
}

/**
 * @brief
 *
 * @param dev
 * @param oflag
 * @return int
 */
int usb_open(struct device *dev, uint16_t oflag) {
  USB_Config_Type usbCfg = {0};

  usb_set_power_off();
  mtimer_delay_ms(10);
  usb_set_power_up();

  usb_xcvr_config(DISABLE);
  usb_xcvr_config(ENABLE);

  CPU_Interrupt_Disable(USB_IRQn);

  usbCfg.DeviceAddress         = 0;
  usbCfg.EnumInEn              = ENABLE;
  usbCfg.EnumOutEn             = ENABLE;
  usbCfg.RomBaseDescriptorUsed = 0;
  usbCfg.SoftwareCtrl          = 1;
  usbCfg.EnumMaxPacketSize     = USB_CTRL_EP_MPS;

  /* Init Device */
  USB_Set_Config(DISABLE, &usbCfg);

  usb_fs_device.out_ep[0].ep_ena         = 1U;
  usb_fs_device.in_ep[0].ep_ena          = 1U;
  usb_fs_device.out_ep[0].ep_cfg.ep_mps  = USB_CTRL_EP_MPS;
  usb_fs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
  usb_fs_device.in_ep[0].ep_cfg.ep_mps   = USB_CTRL_EP_MPS;
  usb_fs_device.in_ep[0].ep_cfg.ep_type  = USBD_EP_TYPE_CTRL;

  /* USB interrupt enable config */
  BL_WR_REG(USB_BASE, USB_INT_EN, 0);
  USB_IntEn(USB_INT_RESET, ENABLE);          // 1
  USB_IntEn(USB_INT_EP0_SETUP_DONE, ENABLE); // 5
  USB_IntEn(USB_INT_EP0_IN_DONE, ENABLE);    // 7
  USB_IntEn(USB_INT_EP0_OUT_DONE, ENABLE);   // 9
  USB_IntEn(USB_INT_RESET_END, ENABLE);      // 27

  /* USB interrupt mask config */
  BL_WR_REG(USB_BASE, USB_INT_MASK, 0xffffffff);
  USB_IntMask(USB_INT_RESET, UNMASK);          // 1
  USB_IntMask(USB_INT_EP0_SETUP_DONE, UNMASK); // 5
  USB_IntMask(USB_INT_EP0_IN_DONE, UNMASK);    // 7
  USB_IntMask(USB_INT_EP0_OUT_DONE, UNMASK);   // 9
  USB_IntMask(USB_INT_RESET_END, UNMASK);      // 27

#ifdef ENABLE_LPM_INT
  USB_IntEn(USB_INT_LPM_PACKET, ENABLE);
  USB_IntEn(USB_INT_LPM_WAKEUP, ENABLE);
  USB_IntMask(USB_INT_LPM_PACKET, UNMASK);
  USB_IntMask(USB_INT_LPM_WAKEUP, UNMASK);

  USB_LPM_Enable();
  USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_ACK);

#endif

#ifdef ENABLE_SOF3MS_INT
  /* disable sof3ms until reset_end */
  USB_IntEn(USB_INT_LOST_SOF_3_TIMES, DISABLE);
  USB_IntMask(USB_INT_LOST_SOF_3_TIMES, MASK);

  /* recommended enable sof3ms after reset_end */
  USB_IntEn(USB_INT_LOST_SOF_3_TIMES, ENABLE);
  USB_IntMask(USB_INT_LOST_SOF_3_TIMES, UNMASK);
#endif

#ifdef ENABLE_ERROR_INT
  USB_IntEn(USB_INT_ERROR, ENABLE);
  USB_IntMask(USB_INT_ERROR, UNMASK);
#endif
  /*Clear pending interrupts*/
  USB_Clr_IntStatus(USB_INT_ALL);

  Interrupt_Handler_Register(USB_IRQn, USB_FS_IRQ);
  CPU_Interrupt_Enable(USB_IRQn);
  USB_Enable();

  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @return int
 */
int usb_close(struct device *dev) {
  /* disable all interrupts and force USB reset */
  CPU_Interrupt_Disable(USB_IRQn);
  USB_IntMask(USB_INT_LPM_WAKEUP, MASK);
  USB_IntMask(USB_INT_LPM_PACKET, MASK);

  USB_Disable();

  /* clear interrupt status register */
  USB_Clr_IntStatus(USB_INT_ALL);

  usb_set_power_off();

  usb_xcvr_config(DISABLE);
  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_USB);
  return 0;
}
/**
 * @brief
 *
 * @param dev
 * @param cmd
 * @param args
 * @return int
 */
int usb_control(struct device *dev, int cmd, void *args) {
  struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;

  switch (cmd) {
  case DEVICE_CTRL_SET_INT /* constant-expression */: {
    uint32_t offset = __builtin_ctz((uint32_t)args);

    while (offset < 24) {
      if ((uint32_t)args & (1 << offset)) {
        USB_IntEn(offset, ENABLE);
        USB_IntMask(offset, UNMASK);
      }

      offset++;
    }
    break;
  }
  case DEVICE_CTRL_CLR_INT /* constant-expression */: {
    uint32_t offset = __builtin_ctz((uint32_t)args);

    while (offset < 24) {
      if ((uint32_t)args & (1 << offset)) {
        USB_IntEn(offset, DISABLE);
        USB_IntMask(offset, MASK);
      }

      offset++;
    }
    break;
  }
  case DEVICE_CTRL_USB_DC_SET_ACK /* constant-expression */:
    USB_Set_EPx_Status(USB_EP_GET_IDX(((uint32_t)args) & 0x7f), USB_EP_STATUS_ACK);
    return 0;
  case DEVICE_CTRL_USB_DC_ENUM_ON: {
    uint32_t tmpVal;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 1);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
    return 0;
  }
  case DEVICE_CTRL_USB_DC_ENUM_OFF: {
    uint32_t tmpVal;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, 0);
    BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);
    return 0;
  }
  case DEVICE_CTRL_USB_DC_GET_EP_TX_FIFO_CNT:
    return USB_Get_EPx_TX_FIFO_CNT(((uint32_t)args) & 0x7f);

  case DEVICE_CTRL_USB_DC_GET_EP_RX_FIFO_CNT:
    return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f);
  case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
    usb_device->tx_dma = (struct device *)args;
    break;

  case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
    usb_device->rx_dma = (struct device *)args;
    break;

  case DEVICE_CTRL_USB_DC_SET_TX_DMA /* constant-expression */:
    USB_Set_EPx_TX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE);
    break;

  case DEVICE_CTRL_USB_DC_SET_RX_DMA /* constant-expression */:
    USB_Set_EPx_RX_DMA_Interface_Config(((uint32_t)args) & 0x7f, ENABLE);
    break;

  default:
    break;
  }

  return 0;
}

int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) {
  struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
  uint8_t               ep_idx     = USB_EP_GET_IDX(pos);

  if (usb_device->in_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) {
    uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x10;

    dma_channel_stop(usb_device->tx_dma);
    usb_lli_list.src_addr              = (uint32_t)buffer;
    usb_lli_list.dst_addr              = usb_ep_addr;
    usb_lli_list.cfg.bits.TransferSize = size;
    usb_lli_list.cfg.bits.DI           = 0;
    usb_lli_list.cfg.bits.SI           = 1;
    usb_lli_list.cfg.bits.SBSize       = DMA_BURST_SIZE_16;
    usb_lli_list.cfg.bits.DBSize       = DMA_BURST_SIZE_1;
    dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list));
    dma_channel_start(usb_device->tx_dma);
    return 0;
  } else {
  }

  return -1;
}

int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) {
  struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
  uint8_t               ep_idx     = USB_EP_GET_IDX(pos);

  if (usb_device->out_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC) {
    uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x1c;

    dma_channel_stop(usb_device->tx_dma);
    usb_lli_list.src_addr              = usb_ep_addr;
    usb_lli_list.dst_addr              = (uint32_t)buffer;
    usb_lli_list.cfg.bits.TransferSize = size;
    usb_lli_list.cfg.bits.DI           = 1;
    usb_lli_list.cfg.bits.SI           = 0;
    usb_lli_list.cfg.bits.SBSize       = DMA_BURST_SIZE_1;
    usb_lli_list.cfg.bits.DBSize       = DMA_BURST_SIZE_16;
    dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list));
    dma_channel_start(usb_device->rx_dma);
    return 0;
  } else {
  }

  return -1;
}

/**
 * @brief
 *
 * @param index
 * @param name
 * @param flag
 * @return int
 */
int usb_dc_register(enum usb_index_type index, const char *name) {
  struct device *dev;

  if (USB_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev = &(usb_fs_device.parent);

  dev->open    = usb_open;
  dev->close   = usb_close;
  dev->control = usb_control;
  dev->write   = usb_write;
  dev->read    = usb_read;

  dev->type   = DEVICE_CLASS_USB;
  dev->handle = NULL;

  return device_register(dev, name);
}

/**
 * @brief Set USB device address
 *
 * @param[in] addr Device address
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_set_dev_address(const uint8_t addr) {
  USB_Set_Device_Addr(addr);
  return 0;
}

/**
 * @brief configure and enable endpoint
 * This function sets endpoint configuration according to one specified in USB
 * endpoint descriptor and then enables it for data transfers.
 *
 * @param dev
 * @param ep_cfg  ep_cfg Endpoint
 * @return int
 */
int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg) {
  uint8_t        ep;
  EP_Config_Type epCfg;

  if (!ep_cfg) {
    return -1;
  }

  ep = ep_cfg->ep_addr;

  uint8_t ep_idx = USB_EP_GET_IDX(ep);

  USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type);

  if (ep_idx == 0) {
    return 0;
  }

  if (USB_EP_DIR_IS_OUT(ep)) {
    epCfg.dir                                   = EP_OUT;
    epCfg.EPMaxPacketSize                       = ep_cfg->ep_mps;
    usb_fs_device.out_ep[ep_idx].ep_cfg.ep_mps  = ep_cfg->ep_mps;
    usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type;
  } else {
    epCfg.dir                                  = EP_IN;
    epCfg.EPMaxPacketSize                      = ep_cfg->ep_mps;
    usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps  = ep_cfg->ep_mps;
    usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type;
  }

  switch (ep_cfg->ep_type) {
  case USBD_EP_TYPE_CTRL:
    epCfg.type = USB_DC_EP_TYPE_CTRL;
    break;

  case USBD_EP_TYPE_ISOC:
    epCfg.type = USB_DC_EP_TYPE_ISOC;
    break;

  case USBD_EP_TYPE_BULK:
    epCfg.type = USB_DC_EP_TYPE_BULK;
    break;

  case USBD_EP_TYPE_INTR:
    epCfg.type = USB_DC_EP_TYPE_INTR;
    break;

  default:
    return -1;
  }

  USB_Set_EPx_Config(ep_idx, &epCfg);

  if (USB_EP_DIR_IS_OUT(ep)) {
    /* Clear NAK and enable ep */
    USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
    usb_fs_device.out_ep[ep_idx].ep_ena = 1U;
  } else {
    // USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
    USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_NACK);
    usb_fs_device.in_ep[ep_idx].ep_ena = 1U;
  }

  return 0;
}

int usb_dc_ep_close(const uint8_t ep) { return 0; }

/**
 * @brief Set stall condition for the selected endpoint
 *
 * @param[in] ep Endpoint address corresponding to the one
 *               listed in the device configuration table
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_ep_set_stall(const uint8_t ep) {
  uint32_t tmpVal = 0;
  uint8_t  ep_idx = USB_EP_GET_IDX(ep);

  if (USB_EP_DIR_IS_OUT(ep)) {
    usb_fs_device.out_ep[ep_idx].is_stalled = 1U;
  } else {
    usb_fs_device.in_ep[ep_idx].is_stalled = 1U;
  }

  switch (ep_idx) {
  case 0:
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
    break;
  case 1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;
  case 2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;
  case 3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;
  case 4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;
  case 5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;
  case 6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;
  case 7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }
  return 0;
}
/**
 * @brief Clear stall condition for the selected endpoint
 *
 * @param[in] ep Endpoint address corresponding to the one
 *               listed in the device configuration table
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_ep_clear_stall(const uint8_t ep) {
  uint8_t  ep_idx = USB_EP_GET_IDX(ep);
  uint32_t tmpVal = 0;
  if (USB_EP_DIR_IS_OUT(ep)) {
    usb_fs_device.out_ep[ep_idx].is_stalled = 0;
  } else {
    usb_fs_device.in_ep[ep_idx].is_stalled = 0;
  }
  switch (ep_idx) {
  case 0:
    break;
  case 1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;
  case 2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;
  case 3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;
  case 4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;
  case 5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;
  case 6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;
  case 7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }
  return 0;
}

/**
 * @brief Check if the selected endpoint is stalled
 *
 * @param dev usb device
 * @param[in]  ep       Endpoint address corresponding to the one
 *                      listed in the device configuration table
 * @param[out] stalled  Endpoint stall status
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled) {
  uint8_t ep_idx = USB_EP_GET_IDX(ep);

  if (!stalled) {
    return -1;
  }

  *stalled = 0U;

  if (USB_EP_DIR_IS_OUT(ep)) {
    if ((USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL) && usb_fs_device.out_ep[ep_idx].is_stalled) {
      *stalled = 1U;
    }
  } else {
    if ((USB_Get_EPx_Status(ep_idx) & USB_EP_STATUS_STALL) && usb_fs_device.in_ep[ep_idx].is_stalled) {
      *stalled = 1U;
    }
  }

  return 0;
}

/**
 * @brief Write data to the specified endpoint
 *
 * This function is called to write data to the specified endpoint. The
 * supplied usbd_endpoint_callback function will be called when data is transmitted
 * out.
 *
 * @param dev
 * @param[in]  ep        Endpoint address corresponding to the one
 *                       listed in the device configuration table
 * @param[in]  data      Pointer to data to write
 * @param[in]  data_len  Length of the data requested to write. This may
 *                       be zero for a zero length status packet.
 * @param[out] ret_bytes Bytes scheduled for transmission. This value
 *                       may be NULL if the application expects all
 *                       bytes to be written
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) {
  uint8_t  ep_idx;
  uint32_t timeout = 0x00FFFFFF;
  uint32_t ep_tx_fifo_addr;

  ep_idx = USB_EP_GET_IDX(ep);

  /* Check if IN ep */
  if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) {
    return -USB_DC_EP_DIR_ERR;
  }

  /* Check if ep enabled */
  if (!usb_ep_is_enabled(ep)) {
    return -USB_DC_EP_EN_ERR;
  }

  if (!data && data_len) {
    USB_DC_LOG_ERR("data is null\r\n");
    return -USB_DC_ADDR_ERR;
  }

  /* Check if ep free */
  while (!USB_Is_EPx_RDY_Free(ep_idx) && (usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
    timeout--;

    if (!timeout) {
      USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
      return -USB_DC_EP_TIMEOUT_ERR;
    }
  }

  if (!data_len) {
    /* Zero length packet */
    if ((USB_EP_GET_IDX(ep) != 0)) {
      /* Clear NAK and enable ep */
      USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
      return USB_DC_OK;
    }
    return USB_DC_OK;
  }

  if (data_len > usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) {
    /* Check if transfer len is too big */
    data_len = usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps;
  }

  /* Wait for FIFO space available */
  do {
    uint32_t avail_space = USB_Get_EPx_TX_FIFO_CNT(ep_idx);

    if (avail_space >= usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps) {
      break;
    }

    // USB_DC_LOG_ERR("EP%d have remain data\r\n", ep_idx);
  } while (1);

  /*
   * Write data to FIFO, make sure that we are protected against
   * other USB register accesses.  According to "DesignWare Cores
   * USB 1.1/2.0 Device Subsystem-AHB/VCI Databook": "During FIFO
   * access, the application must not access the UDC/Subsystem
   * registers or vendor registers (for ULPI mode). After starting
   * to access a FIFO, the application must complete the transaction
   * before accessing the register."
   */
  ep_tx_fifo_addr = USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10;

  if ((data_len == 1) && (ep_idx == 0)) {
    USB_Set_EPx_Xfer_Size(EP_ID0, 1);
  } else if (ep_idx == 0) {
    USB_Set_EPx_Xfer_Size(EP_ID0, 64);
  }

  memcopy_to_fifo((void *)ep_tx_fifo_addr, (uint8_t *)data, data_len);
  /* Clear NAK and enable ep */
  if (USB_EP_GET_IDX(ep) != 0)
    USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
  USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len);

  if (ret_bytes) {
    *ret_bytes = data_len;
  }

  return USB_DC_OK;
}

/**
 * @brief Read data from the specified endpoint
 *
 * This is similar to usb_dc_ep_read, the difference being that, it doesn't
 * clear the endpoint NAKs so that the consumer is not bogged down by further
 * upcalls till he is done with the processing of the data. The caller should
 * reactivate ep by invoking usb_dc_ep_read_continue() do so.
 *
 * @param dev
 * @param[in]  ep           Endpoint address corresponding to the one
 *                          listed in the device configuration table
 * @param[in]  data         Pointer to data buffer to write to
 * @param[in]  max_data_len Max length of data to read
 * @param[out] read_bytes   Number of bytes read. If data is NULL and
 *                          max_data_len is 0 the number of bytes
 *                          available for read should be returned.
 *
 * @return 0 on success, negative errno code on fail.
 */
int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) {
  uint8_t  ep_idx = USB_EP_GET_IDX(ep);
  uint32_t read_count;
  uint32_t ep_rx_fifo_addr;
  uint32_t timeout = 0x00FFFFFF;

  /* Check if OUT ep */
  if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) {
    USB_DC_LOG_ERR("Wrong endpoint direction\r\n");
    return -USB_DC_EP_DIR_ERR;
  }

  /* Check if ep enabled */
  if (!usb_ep_is_enabled(ep)) {
    USB_DC_LOG_ERR("Not enabled endpoint\r\n");
    return -USB_DC_EP_EN_ERR;
  }

  if (!data && data_len) {
    USB_DC_LOG_ERR("data is null\r\n");
    return -USB_DC_ADDR_ERR;
  }

  /* Check if ep free */
  while (!USB_Is_EPx_RDY_Free(ep_idx) && (usb_fs_device.out_ep[ep_idx].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
    timeout--;

    if (!timeout) {
      USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
      return -USB_DC_EP_TIMEOUT_ERR;
    }
  }

  if (!data_len) {
    if ((USB_EP_GET_IDX(ep) != 0)) {
      /* Clear NAK and enable ep */
      USB_Set_EPx_Rdy(USB_EP_GET_IDX(ep));
      return USB_DC_OK;
    }
  }

  read_count = USB_Get_EPx_RX_FIFO_CNT(ep_idx);
  read_count = MIN(read_count, data_len);

  /* Data in the FIFOs is always stored per 8-bit word*/
  ep_rx_fifo_addr = (USB_BASE + USB_EP0_RX_FIFO_RDATA_OFFSET + ep_idx * 0x10);
  fifocopy_to_mem((void *)ep_rx_fifo_addr, data, read_count);
  USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, read_count);

  if (read_bytes) {
    *read_bytes = read_count;
  }

  return USB_DC_OK;
}
/**
 * @brief
 *
 * @param dev
 * @param rb
 * @param ep
 * @return int
 */
int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep) {
  uint8_t     ep_idx;
  uint8_t     recv_len;
  static bool overflow_flag = false;

  /* Check if OUT ep */
  if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) {
    USB_DC_LOG_ERR("Wrong endpoint direction\r\n");
    return -USB_DC_EP_DIR_ERR;
  }

  /* Check if ep enabled */
  if (!usb_ep_is_enabled(ep)) {
    return -USB_DC_EP_EN_ERR;
  }

  ep_idx = USB_EP_GET_IDX(ep);

  recv_len = USB_Get_EPx_RX_FIFO_CNT(ep_idx);

  /*if rx fifo count equal 0,it means last is send nack and ringbuffer is smaller than 64,
   * so,if ringbuffer is larger than 64,set ack to recv next data.
   */
  if (overflow_flag && (Ring_Buffer_Get_Empty_Length(rb) > 64) && (!recv_len)) {
    overflow_flag = false;
    USB_Set_EPx_Rdy(ep_idx);
    return 0;
  } else {
    uint32_t addr = USB_BASE + 0x11C + (ep_idx - 1) * 0x10;
    Ring_Buffer_Write_Callback(rb, recv_len, fifocopy_to_mem, (void *)addr);

    if (Ring_Buffer_Get_Empty_Length(rb) < 64) {
      overflow_flag = true;
      return -USB_DC_RB_SIZE_SMALL_ERR;
    }

    USB_Set_EPx_Rdy(ep_idx);
    return 0;
  }
}
/**
 * @brief
 *
 * @param dev
 * @param rb
 * @param ep
 * @return int
 */
int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep) {
  uint8_t         ep_idx;
  static bool     zlp_flag       = false;
  static uint32_t send_total_len = 0;

  ep_idx = USB_EP_GET_IDX(ep);

  /* Check if IN ep */
  if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) {
    return -USB_DC_EP_DIR_ERR;
  }

  /* Check if ep enabled */
  if (!usb_ep_is_enabled(ep)) {
    return -USB_DC_EP_EN_ERR;
  }

  uint32_t addr = USB_BASE + 0x118 + (ep_idx - 1) * 0x10;

  if (zlp_flag == false) {
    if ((USB_Get_EPx_TX_FIFO_CNT(ep_idx) == USB_FS_MAX_PACKET_SIZE) && Ring_Buffer_Get_Length(rb)) {
      uint32_t actual_len = Ring_Buffer_Read_Callback(rb, USB_FS_MAX_PACKET_SIZE, memcopy_to_fifo, (void *)addr);
      send_total_len += actual_len;

      if (!Ring_Buffer_Get_Length(rb) && (!(send_total_len % 64))) {
        zlp_flag = true;
      }

      USB_Set_EPx_Rdy(ep_idx);
      return 0;
    } else {
      return -USB_DC_RB_SIZE_SMALL_ERR;
    }
  } else {
    zlp_flag       = false;
    send_total_len = 0;
    USB_Set_EPx_Rdy(ep_idx);
    return -USB_DC_ZLP_ERR;
  }
}

/**
 * @brief
 *
 * @param device
 */
void usb_dc_isr(usb_dc_device_t *device) {
  USB_EP_ID epnum = EP_ID0;

  /* EP1_DONE -> EP2_DONE -> ...... -> EP7_DONE*/
  for (USB_INT_Type epint = USB_INT_EP1_DONE; epint <= USB_INT_EP7_DONE; epint += 2) {
    if (USB_Get_IntStatus(epint)) {
      epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
      if (!USB_Is_EPx_RDY_Free(epnum) && (device->out_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
        USB_DC_LOG_ERR("ep%d out busy\r\n", epnum);
        continue;
      }
      USB_Clr_IntStatus(epint);
      device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_OUT(epnum)), 0, USB_DC_EVENT_EP_OUT_NOTIFY);
    }
  }

  /* EP1_CMD -> EP2_CMD -> ...... -> EP7_CMD*/
  for (USB_INT_Type epint = USB_INT_EP1_CMD; epint <= USB_INT_EP7_CMD; epint += 2) {
    if (USB_Get_IntStatus(epint)) {
      epnum = (epint - USB_INT_EP0_OUT_CMD) >> 1;
      if (!USB_Is_EPx_RDY_Free(epnum) && (device->in_ep[epnum].ep_cfg.ep_type != USBD_EP_TYPE_ISOC)) {
        USB_DC_LOG_DBG("ep%d in busy\r\n", epnum);
        continue;
      }
      USB_Clr_IntStatus(epint);
      device->parent.callback(&device->parent, (void *)((uint32_t)USB_SET_EP_IN(epnum)), 0, USB_DC_EVENT_EP_IN_NOTIFY);
    }
  }

  /* EP0 setup done */
  if (USB_Get_IntStatus(USB_INT_EP0_SETUP_DONE)) {
    if (!USB_Is_EPx_RDY_Free(0)) {
      USB_DC_LOG_DBG("ep0 setup busy\r\n");
      return;
    }
    USB_Clr_IntStatus(USB_INT_EP0_SETUP_DONE);
    device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SETUP_NOTIFY);
    USB_Set_EPx_Rdy(EP_ID0);
    return;
  }

  /* EP0 in done */
  if (USB_Get_IntStatus(USB_INT_EP0_IN_DONE)) {
    if (!USB_Is_EPx_RDY_Free(0)) {
      USB_DC_LOG_DBG("ep0 in busy\r\n");
      return;
    }
    USB_Clr_IntStatus(USB_INT_EP0_IN_DONE);
    device->parent.callback(&device->parent, (void *)0x80, 0, USB_DC_EVENT_EP0_IN_NOTIFY);
    USB_Set_EPx_Rdy(EP_ID0);
    return;
  }

  /* EP0 out done */
  if (USB_Get_IntStatus(USB_INT_EP0_OUT_DONE)) {
    if (!USB_Is_EPx_RDY_Free(0)) {
      USB_DC_LOG_DBG("ep0 out busy\r\n");
      return;
    }
    USB_Clr_IntStatus(USB_INT_EP0_OUT_DONE);
    device->parent.callback(&device->parent, (void *)0x00, 0, USB_DC_EVENT_EP0_OUT_NOTIFY);
    USB_Set_EPx_Rdy(EP_ID0);
    return;
  }

  /* sof */
  if (USB_Get_IntStatus(USB_INT_SOF)) {
    USB_Clr_IntStatus(USB_INT_SOF);
    device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF);
    return;
  }

  /* reset */
  if (USB_Get_IntStatus(USB_INT_RESET)) {
    USB_Clr_IntStatus(USB_INT_RESET);
    device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_RESET);
    return;
  }

  /* reset end */
  if (USB_Get_IntStatus(USB_INT_RESET_END)) {
    USB_Clr_IntStatus(USB_INT_RESET_END);
    USB_Set_EPx_Rdy(EP_ID0);
    return;
  }

  /* vbus toggle */
  if (USB_Get_IntStatus(USB_INT_VBUS_TGL)) {
    USB_Clr_IntStatus(USB_INT_VBUS_TGL);
    return;
  }
#ifdef ENABLE_LPM_INT
  /* LPM wakeup */
  if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP)) {
    USB_Clr_IntStatus(USB_INT_LPM_WAKEUP);
    return;
  }

  /* LPM packet */
  if (USB_Get_IntStatus(USB_INT_LPM_PACKET)) {
    /*************************************/
    /* Force low-power mode in the macrocell */
    if (USB_Get_IntStatus(USB_INT_LPM_WAKEUP) == 0) {
    }

    /*************************************/
    USB_Clr_IntStatus(USB_INT_LPM_PACKET);
    return;
  }
#endif
#ifdef ENABLE_SOF3MS_INT
  /* lost 3 SOF */
  if (USB_Get_IntStatus(USB_INT_LOST_SOF_3_TIMES)) {
    USB_DC_LOG_ERR("Lost 3 SOFs\r\n");
    /*************************************/
    /*************************************/
    USB_Clr_IntStatus(USB_INT_LOST_SOF_3_TIMES);
    return;
  }
#endif
#ifdef ENABLE_ERROR_INT
  /* error */
  if (USB_Get_IntStatus(USB_INT_ERROR)) {
    USB_DC_LOG("USB bus error 0x%08x; EP2 fifo status 0x%08x\r\n", *(volatile uint32_t *)(0x4000D81C), *(volatile uint32_t *)(0x4000D920));
    /*************************************/
    /*************************************/
    device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_ERROR);
    USB_Clr_IntStatus(USB_INT_ERROR);
    return;
  }
#endif
}
/**
 * @brief
 *
 */
void USB_FS_IRQ(void) { usb_dc_isr(&usb_fs_device); }

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/hal_drv/src/hal_wdt.c
================================================
/**
 * @file hal_wdt.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "hal_wdt.h"
#include "bl702_timer.h"

#ifdef BSP_USING_WDT
void WDT_IRQ(void);
#endif

static wdt_device_t wdtx_device[WDT_MAX_INDEX] = {
#ifdef BSP_USING_WDT
    WDT_CONFIG,
#endif
};

int wdt_open(struct device *dev, uint16_t oflag) {
  // uint32_t tmpval;

  /* watchdog timer disable*/
  // tmpval = BL_RD_REG(TIMER_BASE, TIMER_WMER);
  // BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpval, TIMER_WE));
  // // MSG("wdt timeout %d \r\n", wdt_device->wdt_timeout);
  // /* Set watchdog timer match register value */
  // BL_WR_REG(TIMER_BASE, TIMER_WMR, (uint16_t)wdt_device->wdt_timeout);

  if (oflag & DEVICE_OFLAG_INT_TX) {
#ifdef BSP_USING_WDT
    wdt_device_t *wdt_device = (wdt_device_t *)dev;
    // WDT_IntMask(WDT_INT, UNMASK);
    if (wdt_device->id == 0) {
      Interrupt_Handler_Register(TIMER_WDT_IRQn, WDT_IRQ);
    }
#endif
  } else {
    WDT_IntMask(WDT_INT, MASK);
  }

  // /* enable watchdog timer */
  WDT_Enable();
  return 0;
}

int wdt_close(struct device *dev) {
  // wdt_device_t *wdt_device = (wdt_device_t *)(dev);
  WDT_Disable();
  return 0;
}

int wdt_control(struct device *dev, int cmd, void *args) {
  // wdt_device_t *wdt_device = (wdt_device_t *)dev;

  switch (cmd) {
  case DEVICE_CTRL_SET_INT: {
    WDT_IntMask(WDT_INT, UNMASK);
    CPU_Interrupt_Pending_Clear(TIMER_WDT_IRQn);
    CPU_Interrupt_Enable(TIMER_WDT_IRQn);
    break;
  }
  case DEVICE_CTRL_CLR_INT: {
    WDT_IntMask(WDT_INT, MASK);
    CPU_Interrupt_Disable(TIMER_WDT_IRQn);
    break;
  }
  case DEVICE_CTRL_CONFIG: {
    break;
  }
  case DEVICE_CTRL_RESUME: {
    WDT_Enable();
    break;
  }
  case DEVICE_CTRL_SUSPEND: {
    WDT_Disable();
    break;
  }
  case DEVICE_CTRL_GET_WDT_COUNTER: {
    return WDT_GetCounterValue();
    break;
  }
  case DEVICE_CTRL_RST_WDT_COUNTER: {
    WDT_ResetCounterValue();
    break;
  }
  case DEVICE_CTRL_GET_RST_STATUS: {
    return WDT_GetResetStatus();
    break;
  }
  case DEVICE_CTRL_CLR_RST_STATUS: {
    WDT_ClearResetStatus();
    break;
  }
  default:
    break;
  }

  return 0;
}

int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) {
  // wdt_device_t *wdt_device = (wdt_device_t *)dev;
  uint16_t wdt_timeout = (uint16_t)(uint32_t)buffer;

  WDT_Disable();
  WDT_SetCompValue(wdt_timeout);
  WDT_Enable();

  return 0;
}

int wdt_register(enum wdt_index_type index, const char *name) {
  struct device *dev;

  if (WDT_MAX_INDEX == 0) {
    return -DEVICE_EINVAL;
  }

  dev = &(wdtx_device[index].parent);

  dev->open    = wdt_open;
  dev->close   = wdt_close;
  dev->control = wdt_control;
  dev->write   = wdt_write;
  // dev->read = NULL;

  dev->status = DEVICE_UNREGISTER;
  dev->type   = DEVICE_CLASS_TIMER;
  dev->handle = NULL;

  return device_register(dev, name);
}

void wdt_isr(wdt_device_t *handle) {
  uint32_t tmpval;

  if (!handle->parent.callback) {
    return;
  }

  tmpval = BL_RD_REG(TIMER_BASE, TIMER_WICR);
  BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpval, TIMER_WICLR));

  handle->parent.callback(&handle->parent, NULL, 0, WDT_EVENT);
}

#ifdef BSP_USING_WDT
/**
 * @brief
 *
 */
void WDT_IRQ(void) { wdt_isr(&wdtx_device[WDT_INDEX]); }
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/aon_reg.h
================================================
/**
  ******************************************************************************
  * @file    aon_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __AON_REG_H__
#define __AON_REG_H__

#include "bl702.h"

/* 0x800 : aon */
#define AON_OFFSET                     (0x800)
#define AON_RESV                       AON_RESV
#define AON_RESV_POS                   (0U)
#define AON_RESV_LEN                   (8U)
#define AON_RESV_MSK                   (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
#define AON_RESV_UMSK                  (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
#define AON_PU_AON_DC_TBUF             AON_PU_AON_DC_TBUF
#define AON_PU_AON_DC_TBUF_POS         (12U)
#define AON_PU_AON_DC_TBUF_LEN         (1U)
#define AON_PU_AON_DC_TBUF_MSK         (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
#define AON_PU_AON_DC_TBUF_UMSK        (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
#define AON_LDO11_RT_PULLDOWN          AON_LDO11_RT_PULLDOWN
#define AON_LDO11_RT_PULLDOWN_POS      (20U)
#define AON_LDO11_RT_PULLDOWN_LEN      (1U)
#define AON_LDO11_RT_PULLDOWN_MSK      (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
#define AON_LDO11_RT_PULLDOWN_UMSK     (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
#define AON_LDO11_RT_PULLDOWN_SEL      AON_LDO11_RT_PULLDOWN_SEL
#define AON_LDO11_RT_PULLDOWN_SEL_POS  (21U)
#define AON_LDO11_RT_PULLDOWN_SEL_LEN  (1U)
#define AON_LDO11_RT_PULLDOWN_SEL_MSK  (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
#define AON_SW_PU_LDO11_RT             AON_SW_PU_LDO11_RT
#define AON_SW_PU_LDO11_RT_POS         (22U)
#define AON_SW_PU_LDO11_RT_LEN         (1U)
#define AON_SW_PU_LDO11_RT_MSK         (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
#define AON_SW_PU_LDO11_RT_UMSK        (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))

/* 0x804 : aon_common */
#define AON_COMMON_OFFSET         (0x804)
#define AON_TMUX_AON              AON_TMUX_AON
#define AON_TMUX_AON_POS          (0U)
#define AON_TMUX_AON_LEN          (3U)
#define AON_TMUX_AON_MSK          (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
#define AON_TMUX_AON_UMSK         (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
#define AON_TEN_AON               AON_TEN_AON
#define AON_TEN_AON_POS           (4U)
#define AON_TEN_AON_LEN           (1U)
#define AON_TEN_AON_MSK           (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
#define AON_TEN_AON_UMSK          (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
#define AON_DTEN_XTAL32K          AON_DTEN_XTAL32K
#define AON_DTEN_XTAL32K_POS      (5U)
#define AON_DTEN_XTAL32K_LEN      (1U)
#define AON_DTEN_XTAL32K_MSK      (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)
#define AON_DTEN_XTAL32K_UMSK     (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS))
#define AON_TEN_XTAL32K           AON_TEN_XTAL32K
#define AON_TEN_XTAL32K_POS       (6U)
#define AON_TEN_XTAL32K_LEN       (1U)
#define AON_TEN_XTAL32K_MSK       (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)
#define AON_TEN_XTAL32K_UMSK      (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS))
#define AON_TEN_VDDCORE_AON       AON_TEN_VDDCORE_AON
#define AON_TEN_VDDCORE_AON_POS   (8U)
#define AON_TEN_VDDCORE_AON_LEN   (1U)
#define AON_TEN_VDDCORE_AON_MSK   (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)
#define AON_TEN_VDDCORE_AON_UMSK  (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS))
#define AON_TEN_LDO11SOC_AON      AON_TEN_LDO11SOC_AON
#define AON_TEN_LDO11SOC_AON_POS  (9U)
#define AON_TEN_LDO11SOC_AON_LEN  (1U)
#define AON_TEN_LDO11SOC_AON_MSK  (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)
#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS))
#define AON_TEN_DCDC18_0_AON      AON_TEN_DCDC18_0_AON
#define AON_TEN_DCDC18_0_AON_POS  (10U)
#define AON_TEN_DCDC18_0_AON_LEN  (1U)
#define AON_TEN_DCDC18_0_AON_MSK  (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)
#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS))
#define AON_TEN_DCDC18_1_AON      AON_TEN_DCDC18_1_AON
#define AON_TEN_DCDC18_1_AON_POS  (11U)
#define AON_TEN_DCDC18_1_AON_LEN  (1U)
#define AON_TEN_DCDC18_1_AON_MSK  (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)
#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS))
#define AON_TEN_BG_SYS_AON        AON_TEN_BG_SYS_AON
#define AON_TEN_BG_SYS_AON_POS    (12U)
#define AON_TEN_BG_SYS_AON_LEN    (1U)
#define AON_TEN_BG_SYS_AON_MSK    (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
#define AON_TEN_BG_SYS_AON_UMSK   (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
#define AON_TEN_LDO15RF_AON       AON_TEN_LDO15RF_AON
#define AON_TEN_LDO15RF_AON_POS   (16U)
#define AON_TEN_LDO15RF_AON_LEN   (1U)
#define AON_TEN_LDO15RF_AON_MSK   (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
#define AON_TEN_LDO15RF_AON_UMSK  (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
#define AON_TEN_XTAL_AON          AON_TEN_XTAL_AON
#define AON_TEN_XTAL_AON_POS      (17U)
#define AON_TEN_XTAL_AON_LEN      (1U)
#define AON_TEN_XTAL_AON_MSK      (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
#define AON_TEN_XTAL_AON_UMSK     (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
#define AON_DTEN_XTAL_AON         AON_DTEN_XTAL_AON
#define AON_DTEN_XTAL_AON_POS     (18U)
#define AON_DTEN_XTAL_AON_LEN     (1U)
#define AON_DTEN_XTAL_AON_MSK     (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
#define AON_DTEN_XTAL_AON_UMSK    (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
#define AON_TEN_MBG_AON           AON_TEN_MBG_AON
#define AON_TEN_MBG_AON_POS       (19U)
#define AON_TEN_MBG_AON_LEN       (1U)
#define AON_TEN_MBG_AON_MSK       (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
#define AON_TEN_MBG_AON_UMSK      (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
#define AON_TEN_CIP_MISC_AON      AON_TEN_CIP_MISC_AON
#define AON_TEN_CIP_MISC_AON_POS  (20U)
#define AON_TEN_CIP_MISC_AON_LEN  (1U)
#define AON_TEN_CIP_MISC_AON_MSK  (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))

/* 0x808 : aon_misc */
#define AON_MISC_OFFSET        (0x808)
#define AON_SW_SOC_EN_AON      AON_SW_SOC_EN_AON
#define AON_SW_SOC_EN_AON_POS  (0U)
#define AON_SW_SOC_EN_AON_LEN  (1U)
#define AON_SW_SOC_EN_AON_MSK  (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
#define AON_SW_BZ_EN_AON       AON_SW_BZ_EN_AON
#define AON_SW_BZ_EN_AON_POS   (1U)
#define AON_SW_BZ_EN_AON_LEN   (1U)
#define AON_SW_BZ_EN_AON_MSK   (((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS)
#define AON_SW_BZ_EN_AON_UMSK  (~(((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS))

/* 0x810 : bg_sys_top */
#define AON_BG_SYS_TOP_OFFSET          (0x810)
#define AON_PMIP_RESV                  AON_PMIP_RESV
#define AON_PMIP_RESV_POS              (0U)
#define AON_PMIP_RESV_LEN              (8U)
#define AON_PMIP_RESV_MSK              (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)
#define AON_PMIP_RESV_UMSK             (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS))
#define AON_PU_BG_SYS_AON              AON_PU_BG_SYS_AON
#define AON_PU_BG_SYS_AON_POS          (8U)
#define AON_PU_BG_SYS_AON_LEN          (1U)
#define AON_PU_BG_SYS_AON_MSK          (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
#define AON_PU_BG_SYS_AON_UMSK         (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
#define AON_BG_SYS_START_CTRL_AON      AON_BG_SYS_START_CTRL_AON
#define AON_BG_SYS_START_CTRL_AON_POS  (12U)
#define AON_BG_SYS_START_CTRL_AON_LEN  (1U)
#define AON_BG_SYS_START_CTRL_AON_MSK  (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)
#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS))

/* 0x814 : dcdc18_top_0 */
#define AON_DCDC18_TOP_0_OFFSET            (0x814)
#define AON_DCDC18_VOUT_SEL_AON            AON_DCDC18_VOUT_SEL_AON
#define AON_DCDC18_VOUT_SEL_AON_POS        (1U)
#define AON_DCDC18_VOUT_SEL_AON_LEN        (5U)
#define AON_DCDC18_VOUT_SEL_AON_MSK        (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)
#define AON_DCDC18_VOUT_SEL_AON_UMSK       (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS))
#define AON_DCDC18_VPFM_AON                AON_DCDC18_VPFM_AON
#define AON_DCDC18_VPFM_AON_POS            (8U)
#define AON_DCDC18_VPFM_AON_LEN            (4U)
#define AON_DCDC18_VPFM_AON_MSK            (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)
#define AON_DCDC18_VPFM_AON_UMSK           (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS))
#define AON_DCDC18_OSC_2M_MODE_AON         AON_DCDC18_OSC_2M_MODE_AON
#define AON_DCDC18_OSC_2M_MODE_AON_POS     (12U)
#define AON_DCDC18_OSC_2M_MODE_AON_LEN     (1U)
#define AON_DCDC18_OSC_2M_MODE_AON_MSK     (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)
#define AON_DCDC18_OSC_2M_MODE_AON_UMSK    (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS))
#define AON_DCDC18_OSC_FREQ_TRIM_AON       AON_DCDC18_OSC_FREQ_TRIM_AON
#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS   (16U)
#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN   (4U)
#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK   (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)
#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK  (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS))
#define AON_DCDC18_SLOPE_CURR_SEL_AON      AON_DCDC18_SLOPE_CURR_SEL_AON
#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS  (20U)
#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN  (5U)
#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK  (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)
#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS))
#define AON_DCDC18_STOP_OSC_AON            AON_DCDC18_STOP_OSC_AON
#define AON_DCDC18_STOP_OSC_AON_POS        (25U)
#define AON_DCDC18_STOP_OSC_AON_LEN        (1U)
#define AON_DCDC18_STOP_OSC_AON_MSK        (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)
#define AON_DCDC18_STOP_OSC_AON_UMSK       (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS))
#define AON_DCDC18_SLOW_OSC_AON            AON_DCDC18_SLOW_OSC_AON
#define AON_DCDC18_SLOW_OSC_AON_POS        (26U)
#define AON_DCDC18_SLOW_OSC_AON_LEN        (1U)
#define AON_DCDC18_SLOW_OSC_AON_MSK        (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)
#define AON_DCDC18_SLOW_OSC_AON_UMSK       (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS))
#define AON_DCDC18_OSC_INHIBIT_T2_AON      AON_DCDC18_OSC_INHIBIT_T2_AON
#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS  (27U)
#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN  (1U)
#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK  (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)
#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS))
#define AON_DCDC18_SSTART_TIME_AON         AON_DCDC18_SSTART_TIME_AON
#define AON_DCDC18_SSTART_TIME_AON_POS     (28U)
#define AON_DCDC18_SSTART_TIME_AON_LEN     (2U)
#define AON_DCDC18_SSTART_TIME_AON_MSK     (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)
#define AON_DCDC18_SSTART_TIME_AON_UMSK    (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS))
#define AON_DCDC18_RDY_AON                 AON_DCDC18_RDY_AON
#define AON_DCDC18_RDY_AON_POS             (31U)
#define AON_DCDC18_RDY_AON_LEN             (1U)
#define AON_DCDC18_RDY_AON_MSK             (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)
#define AON_DCDC18_RDY_AON_UMSK            (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS))

/* 0x818 : dcdc18_top_1 */
#define AON_DCDC18_TOP_1_OFFSET           (0x818)
#define AON_DCDC18_FORCE_CS_ZVS_AON       AON_DCDC18_FORCE_CS_ZVS_AON
#define AON_DCDC18_FORCE_CS_ZVS_AON_POS   (0U)
#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN   (1U)
#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK   (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)
#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK  (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS))
#define AON_DCDC18_CS_DELAY_AON           AON_DCDC18_CS_DELAY_AON
#define AON_DCDC18_CS_DELAY_AON_POS       (1U)
#define AON_DCDC18_CS_DELAY_AON_LEN       (3U)
#define AON_DCDC18_CS_DELAY_AON_MSK       (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)
#define AON_DCDC18_CS_DELAY_AON_UMSK      (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS))
#define AON_DCDC18_ZVS_TD_OPT_AON         AON_DCDC18_ZVS_TD_OPT_AON
#define AON_DCDC18_ZVS_TD_OPT_AON_POS     (4U)
#define AON_DCDC18_ZVS_TD_OPT_AON_LEN     (3U)
#define AON_DCDC18_ZVS_TD_OPT_AON_MSK     (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)
#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK    (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS))
#define AON_DCDC18_NONOVERLAP_TD_AON      AON_DCDC18_NONOVERLAP_TD_AON
#define AON_DCDC18_NONOVERLAP_TD_AON_POS  (8U)
#define AON_DCDC18_NONOVERLAP_TD_AON_LEN  (5U)
#define AON_DCDC18_NONOVERLAP_TD_AON_MSK  (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)
#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS))
#define AON_DCDC18_RC_SEL_AON             AON_DCDC18_RC_SEL_AON
#define AON_DCDC18_RC_SEL_AON_POS         (16U)
#define AON_DCDC18_RC_SEL_AON_LEN         (4U)
#define AON_DCDC18_RC_SEL_AON_MSK         (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)
#define AON_DCDC18_RC_SEL_AON_UMSK        (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS))
#define AON_DCDC18_CHF_SEL_AON            AON_DCDC18_CHF_SEL_AON
#define AON_DCDC18_CHF_SEL_AON_POS        (20U)
#define AON_DCDC18_CHF_SEL_AON_LEN        (4U)
#define AON_DCDC18_CHF_SEL_AON_MSK        (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)
#define AON_DCDC18_CHF_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS))
#define AON_DCDC18_CFB_SEL_AON            AON_DCDC18_CFB_SEL_AON
#define AON_DCDC18_CFB_SEL_AON_POS        (24U)
#define AON_DCDC18_CFB_SEL_AON_LEN        (4U)
#define AON_DCDC18_CFB_SEL_AON_MSK        (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)
#define AON_DCDC18_CFB_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS))
#define AON_DCDC18_EN_ANTIRING_AON        AON_DCDC18_EN_ANTIRING_AON
#define AON_DCDC18_EN_ANTIRING_AON_POS    (28U)
#define AON_DCDC18_EN_ANTIRING_AON_LEN    (1U)
#define AON_DCDC18_EN_ANTIRING_AON_MSK    (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)
#define AON_DCDC18_EN_ANTIRING_AON_UMSK   (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS))
#define AON_DCDC18_PULLDOWN_AON           AON_DCDC18_PULLDOWN_AON
#define AON_DCDC18_PULLDOWN_AON_POS       (29U)
#define AON_DCDC18_PULLDOWN_AON_LEN       (1U)
#define AON_DCDC18_PULLDOWN_AON_MSK       (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)
#define AON_DCDC18_PULLDOWN_AON_UMSK      (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS))

/* 0x81C : ldo11soc_and_dctest */
#define AON_LDO11SOC_AND_DCTEST_OFFSET     (0x81C)
#define AON_PU_LDO11SOC_AON                AON_PU_LDO11SOC_AON
#define AON_PU_LDO11SOC_AON_POS            (0U)
#define AON_PU_LDO11SOC_AON_LEN            (1U)
#define AON_PU_LDO11SOC_AON_MSK            (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)
#define AON_PU_LDO11SOC_AON_UMSK           (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS))
#define AON_LDO11SOC_SSTART_SEL_AON        AON_LDO11SOC_SSTART_SEL_AON
#define AON_LDO11SOC_SSTART_SEL_AON_POS    (4U)
#define AON_LDO11SOC_SSTART_SEL_AON_LEN    (1U)
#define AON_LDO11SOC_SSTART_SEL_AON_MSK    (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)
#define AON_LDO11SOC_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS))
#define AON_LDO11SOC_SSTART_DELAY_AON      AON_LDO11SOC_SSTART_DELAY_AON
#define AON_LDO11SOC_SSTART_DELAY_AON_POS  (8U)
#define AON_LDO11SOC_SSTART_DELAY_AON_LEN  (2U)
#define AON_LDO11SOC_SSTART_DELAY_AON_MSK  (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)
#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS))
#define AON_LDO11SOC_PULLDOWN_AON          AON_LDO11SOC_PULLDOWN_AON
#define AON_LDO11SOC_PULLDOWN_AON_POS      (10U)
#define AON_LDO11SOC_PULLDOWN_AON_LEN      (1U)
#define AON_LDO11SOC_PULLDOWN_AON_MSK      (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)
#define AON_LDO11SOC_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS))
#define AON_LDO11SOC_PULLDOWN_SEL_AON      AON_LDO11SOC_PULLDOWN_SEL_AON
#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS  (11U)
#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN  (1U)
#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)
#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS))
#define AON_LDO11SOC_VTH_SEL_AON           AON_LDO11SOC_VTH_SEL_AON
#define AON_LDO11SOC_VTH_SEL_AON_POS       (12U)
#define AON_LDO11SOC_VTH_SEL_AON_LEN       (2U)
#define AON_LDO11SOC_VTH_SEL_AON_MSK       (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)
#define AON_LDO11SOC_VTH_SEL_AON_UMSK      (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS))
#define AON_LDO11SOC_CC_AON                AON_LDO11SOC_CC_AON
#define AON_LDO11SOC_CC_AON_POS            (24U)
#define AON_LDO11SOC_CC_AON_LEN            (2U)
#define AON_LDO11SOC_CC_AON_MSK            (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)
#define AON_LDO11SOC_CC_AON_UMSK           (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS))
#define AON_LDO11SOC_RDY_AON               AON_LDO11SOC_RDY_AON
#define AON_LDO11SOC_RDY_AON_POS           (28U)
#define AON_LDO11SOC_RDY_AON_LEN           (1U)
#define AON_LDO11SOC_RDY_AON_MSK           (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)
#define AON_LDO11SOC_RDY_AON_UMSK          (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS))
#define AON_LDO11SOC_POWER_GOOD_AON        AON_LDO11SOC_POWER_GOOD_AON
#define AON_LDO11SOC_POWER_GOOD_AON_POS    (29U)
#define AON_LDO11SOC_POWER_GOOD_AON_LEN    (1U)
#define AON_LDO11SOC_POWER_GOOD_AON_MSK    (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)
#define AON_LDO11SOC_POWER_GOOD_AON_UMSK   (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS))
#define AON_PU_VDDCORE_MISC_AON            AON_PU_VDDCORE_MISC_AON
#define AON_PU_VDDCORE_MISC_AON_POS        (30U)
#define AON_PU_VDDCORE_MISC_AON_LEN        (1U)
#define AON_PU_VDDCORE_MISC_AON_MSK        (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)
#define AON_PU_VDDCORE_MISC_AON_UMSK       (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS))
#define AON_PMIP_DC_TP_OUT_EN_AON          AON_PMIP_DC_TP_OUT_EN_AON
#define AON_PMIP_DC_TP_OUT_EN_AON_POS      (31U)
#define AON_PMIP_DC_TP_OUT_EN_AON_LEN      (1U)
#define AON_PMIP_DC_TP_OUT_EN_AON_MSK      (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK     (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))

/* 0x820 : psw_irrcv */
#define AON_PSW_IRRCV_OFFSET   (0x820)
#define AON_PU_IR_PSW_AON      AON_PU_IR_PSW_AON
#define AON_PU_IR_PSW_AON_POS  (0U)
#define AON_PU_IR_PSW_AON_LEN  (1U)
#define AON_PU_IR_PSW_AON_MSK  (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)
#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS))

/* 0x880 : rf_top_aon */
#define AON_RF_TOP_AON_OFFSET             (0x880)
#define AON_PU_MBG_AON                    AON_PU_MBG_AON
#define AON_PU_MBG_AON_POS                (0U)
#define AON_PU_MBG_AON_LEN                (1U)
#define AON_PU_MBG_AON_MSK                (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
#define AON_PU_MBG_AON_UMSK               (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
#define AON_PU_LDO15RF_AON                AON_PU_LDO15RF_AON
#define AON_PU_LDO15RF_AON_POS            (1U)
#define AON_PU_LDO15RF_AON_LEN            (1U)
#define AON_PU_LDO15RF_AON_MSK            (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
#define AON_PU_LDO15RF_AON_UMSK           (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
#define AON_PU_SFREG_AON                  AON_PU_SFREG_AON
#define AON_PU_SFREG_AON_POS              (2U)
#define AON_PU_SFREG_AON_LEN              (1U)
#define AON_PU_SFREG_AON_MSK              (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
#define AON_PU_SFREG_AON_UMSK             (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
#define AON_PU_XTAL_BUF_AON               AON_PU_XTAL_BUF_AON
#define AON_PU_XTAL_BUF_AON_POS           (4U)
#define AON_PU_XTAL_BUF_AON_LEN           (1U)
#define AON_PU_XTAL_BUF_AON_MSK           (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
#define AON_PU_XTAL_BUF_AON_UMSK          (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
#define AON_PU_XTAL_AON                   AON_PU_XTAL_AON
#define AON_PU_XTAL_AON_POS               (5U)
#define AON_PU_XTAL_AON_LEN               (1U)
#define AON_PU_XTAL_AON_MSK               (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
#define AON_PU_XTAL_AON_UMSK              (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
#define AON_LDO15RF_SSTART_SEL_AON        AON_LDO15RF_SSTART_SEL_AON
#define AON_LDO15RF_SSTART_SEL_AON_POS    (8U)
#define AON_LDO15RF_SSTART_SEL_AON_LEN    (1U)
#define AON_LDO15RF_SSTART_SEL_AON_MSK    (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
#define AON_LDO15RF_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
#define AON_LDO15RF_SSTART_DELAY_AON      AON_LDO15RF_SSTART_DELAY_AON
#define AON_LDO15RF_SSTART_DELAY_AON_POS  (9U)
#define AON_LDO15RF_SSTART_DELAY_AON_LEN  (2U)
#define AON_LDO15RF_SSTART_DELAY_AON_MSK  (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
#define AON_LDO15RF_PULLDOWN_AON          AON_LDO15RF_PULLDOWN_AON
#define AON_LDO15RF_PULLDOWN_AON_POS      (12U)
#define AON_LDO15RF_PULLDOWN_AON_LEN      (1U)
#define AON_LDO15RF_PULLDOWN_AON_MSK      (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
#define AON_LDO15RF_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
#define AON_LDO15RF_PULLDOWN_SEL_AON      AON_LDO15RF_PULLDOWN_SEL_AON
#define AON_LDO15RF_PULLDOWN_SEL_AON_POS  (13U)
#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN  (1U)
#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
#define AON_LDO15RF_VOUT_SEL_AON          AON_LDO15RF_VOUT_SEL_AON
#define AON_LDO15RF_VOUT_SEL_AON_POS      (16U)
#define AON_LDO15RF_VOUT_SEL_AON_LEN      (3U)
#define AON_LDO15RF_VOUT_SEL_AON_MSK      (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
#define AON_LDO15RF_VOUT_SEL_AON_UMSK     (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
#define AON_LDO15RF_CC_AON                AON_LDO15RF_CC_AON
#define AON_LDO15RF_CC_AON_POS            (24U)
#define AON_LDO15RF_CC_AON_LEN            (2U)
#define AON_LDO15RF_CC_AON_MSK            (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
#define AON_LDO15RF_CC_AON_UMSK           (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
#define AON_LDO15RF_BYPASS_AON            AON_LDO15RF_BYPASS_AON
#define AON_LDO15RF_BYPASS_AON_POS        (28U)
#define AON_LDO15RF_BYPASS_AON_LEN        (1U)
#define AON_LDO15RF_BYPASS_AON_MSK        (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
#define AON_LDO15RF_BYPASS_AON_UMSK       (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))

/* 0x884 : xtal_cfg */
#define AON_XTAL_CFG_OFFSET             (0x884)
#define AON_XTAL_BK_AON                 AON_XTAL_BK_AON
#define AON_XTAL_BK_AON_POS             (0U)
#define AON_XTAL_BK_AON_LEN             (2U)
#define AON_XTAL_BK_AON_MSK             (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
#define AON_XTAL_BK_AON_UMSK            (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
#define AON_XTAL_CAPCODE_EXTRA_AON      AON_XTAL_CAPCODE_EXTRA_AON
#define AON_XTAL_CAPCODE_EXTRA_AON_POS  (2U)
#define AON_XTAL_CAPCODE_EXTRA_AON_LEN  (1U)
#define AON_XTAL_CAPCODE_EXTRA_AON_MSK  (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
#define AON_XTAL_EXT_SEL_AON            AON_XTAL_EXT_SEL_AON
#define AON_XTAL_EXT_SEL_AON_POS        (3U)
#define AON_XTAL_EXT_SEL_AON_LEN        (1U)
#define AON_XTAL_EXT_SEL_AON_MSK        (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
#define AON_XTAL_EXT_SEL_AON_UMSK       (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
#define AON_XTAL_BUF_EN_AON             AON_XTAL_BUF_EN_AON
#define AON_XTAL_BUF_EN_AON_POS         (4U)
#define AON_XTAL_BUF_EN_AON_LEN         (4U)
#define AON_XTAL_BUF_EN_AON_MSK         (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
#define AON_XTAL_BUF_EN_AON_UMSK        (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
#define AON_XTAL_BUF_HP_AON             AON_XTAL_BUF_HP_AON
#define AON_XTAL_BUF_HP_AON_POS         (8U)
#define AON_XTAL_BUF_HP_AON_LEN         (4U)
#define AON_XTAL_BUF_HP_AON_MSK         (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
#define AON_XTAL_BUF_HP_AON_UMSK        (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
#define AON_XTAL_FAST_STARTUP_AON       AON_XTAL_FAST_STARTUP_AON
#define AON_XTAL_FAST_STARTUP_AON_POS   (12U)
#define AON_XTAL_FAST_STARTUP_AON_LEN   (1U)
#define AON_XTAL_FAST_STARTUP_AON_MSK   (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
#define AON_XTAL_FAST_STARTUP_AON_UMSK  (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
#define AON_XTAL_SLEEP_AON              AON_XTAL_SLEEP_AON
#define AON_XTAL_SLEEP_AON_POS          (13U)
#define AON_XTAL_SLEEP_AON_LEN          (1U)
#define AON_XTAL_SLEEP_AON_MSK          (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
#define AON_XTAL_SLEEP_AON_UMSK         (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
#define AON_XTAL_AMP_CTRL_AON           AON_XTAL_AMP_CTRL_AON
#define AON_XTAL_AMP_CTRL_AON_POS       (14U)
#define AON_XTAL_AMP_CTRL_AON_LEN       (2U)
#define AON_XTAL_AMP_CTRL_AON_MSK       (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
#define AON_XTAL_AMP_CTRL_AON_UMSK      (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
#define AON_XTAL_CAPCODE_OUT_AON        AON_XTAL_CAPCODE_OUT_AON
#define AON_XTAL_CAPCODE_OUT_AON_POS    (16U)
#define AON_XTAL_CAPCODE_OUT_AON_LEN    (6U)
#define AON_XTAL_CAPCODE_OUT_AON_MSK    (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
#define AON_XTAL_CAPCODE_OUT_AON_UMSK   (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
#define AON_XTAL_CAPCODE_IN_AON         AON_XTAL_CAPCODE_IN_AON
#define AON_XTAL_CAPCODE_IN_AON_POS     (22U)
#define AON_XTAL_CAPCODE_IN_AON_LEN     (6U)
#define AON_XTAL_CAPCODE_IN_AON_MSK     (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
#define AON_XTAL_CAPCODE_IN_AON_UMSK    (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
#define AON_XTAL_GM_BOOST_AON           AON_XTAL_GM_BOOST_AON
#define AON_XTAL_GM_BOOST_AON_POS       (28U)
#define AON_XTAL_GM_BOOST_AON_LEN       (2U)
#define AON_XTAL_GM_BOOST_AON_MSK       (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
#define AON_XTAL_GM_BOOST_AON_UMSK      (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
#define AON_XTAL_RDY_SEL_AON            AON_XTAL_RDY_SEL_AON
#define AON_XTAL_RDY_SEL_AON_POS        (30U)
#define AON_XTAL_RDY_SEL_AON_LEN        (2U)
#define AON_XTAL_RDY_SEL_AON_MSK        (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
#define AON_XTAL_RDY_SEL_AON_UMSK       (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))

/* 0x888 : tsen */
#define AON_TSEN_OFFSET               (0x888)
#define AON_TSEN_REFCODE_CORNER       AON_TSEN_REFCODE_CORNER
#define AON_TSEN_REFCODE_CORNER_POS   (0U)
#define AON_TSEN_REFCODE_CORNER_LEN   (12U)
#define AON_TSEN_REFCODE_CORNER_MSK   (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
#define AON_TSEN_REFCODE_CORNER_UMSK  (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
#define AON_TSEN_REFCODE_RFCAL        AON_TSEN_REFCODE_RFCAL
#define AON_TSEN_REFCODE_RFCAL_POS    (16U)
#define AON_TSEN_REFCODE_RFCAL_LEN    (12U)
#define AON_TSEN_REFCODE_RFCAL_MSK    (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
#define AON_TSEN_REFCODE_RFCAL_UMSK   (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
#define AON_XTAL_RDY                  AON_XTAL_RDY
#define AON_XTAL_RDY_POS              (28U)
#define AON_XTAL_RDY_LEN              (1U)
#define AON_XTAL_RDY_MSK              (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
#define AON_XTAL_RDY_UMSK             (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
#define AON_XTAL_INN_CFG_EN_AON       AON_XTAL_INN_CFG_EN_AON
#define AON_XTAL_INN_CFG_EN_AON_POS   (29U)
#define AON_XTAL_INN_CFG_EN_AON_LEN   (1U)
#define AON_XTAL_INN_CFG_EN_AON_MSK   (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
#define AON_XTAL_INN_CFG_EN_AON_UMSK  (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
#define AON_XTAL_RDY_INT_SEL_AON      AON_XTAL_RDY_INT_SEL_AON
#define AON_XTAL_RDY_INT_SEL_AON_POS  (30U)
#define AON_XTAL_RDY_INT_SEL_AON_LEN  (2U)
#define AON_XTAL_RDY_INT_SEL_AON_MSK  (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))

/* 0x900 : acomp0_ctrl */
#define AON_ACOMP0_CTRL_OFFSET    (0x900)
#define AON_ACOMP0_EN             AON_ACOMP0_EN
#define AON_ACOMP0_EN_POS         (0U)
#define AON_ACOMP0_EN_LEN         (1U)
#define AON_ACOMP0_EN_MSK         (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
#define AON_ACOMP0_EN_UMSK        (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
#define AON_ACOMP0_HYST_SELN      AON_ACOMP0_HYST_SELN
#define AON_ACOMP0_HYST_SELN_POS  (4U)
#define AON_ACOMP0_HYST_SELN_LEN  (3U)
#define AON_ACOMP0_HYST_SELN_MSK  (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
#define AON_ACOMP0_HYST_SELP      AON_ACOMP0_HYST_SELP
#define AON_ACOMP0_HYST_SELP_POS  (7U)
#define AON_ACOMP0_HYST_SELP_LEN  (3U)
#define AON_ACOMP0_HYST_SELP_MSK  (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
#define AON_ACOMP0_BIAS_PROG      AON_ACOMP0_BIAS_PROG
#define AON_ACOMP0_BIAS_PROG_POS  (10U)
#define AON_ACOMP0_BIAS_PROG_LEN  (2U)
#define AON_ACOMP0_BIAS_PROG_MSK  (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
#define AON_ACOMP0_LEVEL_SEL      AON_ACOMP0_LEVEL_SEL
#define AON_ACOMP0_LEVEL_SEL_POS  (12U)
#define AON_ACOMP0_LEVEL_SEL_LEN  (6U)
#define AON_ACOMP0_LEVEL_SEL_MSK  (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
#define AON_ACOMP0_NEG_SEL        AON_ACOMP0_NEG_SEL
#define AON_ACOMP0_NEG_SEL_POS    (18U)
#define AON_ACOMP0_NEG_SEL_LEN    (4U)
#define AON_ACOMP0_NEG_SEL_MSK    (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
#define AON_ACOMP0_NEG_SEL_UMSK   (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
#define AON_ACOMP0_POS_SEL        AON_ACOMP0_POS_SEL
#define AON_ACOMP0_POS_SEL_POS    (22U)
#define AON_ACOMP0_POS_SEL_LEN    (4U)
#define AON_ACOMP0_POS_SEL_MSK    (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
#define AON_ACOMP0_POS_SEL_UMSK   (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
#define AON_ACOMP0_MUXEN          AON_ACOMP0_MUXEN
#define AON_ACOMP0_MUXEN_POS      (26U)
#define AON_ACOMP0_MUXEN_LEN      (1U)
#define AON_ACOMP0_MUXEN_MSK      (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
#define AON_ACOMP0_MUXEN_UMSK     (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))

/* 0x904 : acomp1_ctrl */
#define AON_ACOMP1_CTRL_OFFSET    (0x904)
#define AON_ACOMP1_EN             AON_ACOMP1_EN
#define AON_ACOMP1_EN_POS         (0U)
#define AON_ACOMP1_EN_LEN         (1U)
#define AON_ACOMP1_EN_MSK         (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
#define AON_ACOMP1_EN_UMSK        (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
#define AON_ACOMP1_HYST_SELN      AON_ACOMP1_HYST_SELN
#define AON_ACOMP1_HYST_SELN_POS  (4U)
#define AON_ACOMP1_HYST_SELN_LEN  (3U)
#define AON_ACOMP1_HYST_SELN_MSK  (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
#define AON_ACOMP1_HYST_SELP      AON_ACOMP1_HYST_SELP
#define AON_ACOMP1_HYST_SELP_POS  (7U)
#define AON_ACOMP1_HYST_SELP_LEN  (3U)
#define AON_ACOMP1_HYST_SELP_MSK  (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
#define AON_ACOMP1_BIAS_PROG      AON_ACOMP1_BIAS_PROG
#define AON_ACOMP1_BIAS_PROG_POS  (10U)
#define AON_ACOMP1_BIAS_PROG_LEN  (2U)
#define AON_ACOMP1_BIAS_PROG_MSK  (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
#define AON_ACOMP1_LEVEL_SEL      AON_ACOMP1_LEVEL_SEL
#define AON_ACOMP1_LEVEL_SEL_POS  (12U)
#define AON_ACOMP1_LEVEL_SEL_LEN  (6U)
#define AON_ACOMP1_LEVEL_SEL_MSK  (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
#define AON_ACOMP1_NEG_SEL        AON_ACOMP1_NEG_SEL
#define AON_ACOMP1_NEG_SEL_POS    (18U)
#define AON_ACOMP1_NEG_SEL_LEN    (4U)
#define AON_ACOMP1_NEG_SEL_MSK    (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
#define AON_ACOMP1_NEG_SEL_UMSK   (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
#define AON_ACOMP1_POS_SEL        AON_ACOMP1_POS_SEL
#define AON_ACOMP1_POS_SEL_POS    (22U)
#define AON_ACOMP1_POS_SEL_LEN    (4U)
#define AON_ACOMP1_POS_SEL_MSK    (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
#define AON_ACOMP1_POS_SEL_UMSK   (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
#define AON_ACOMP1_MUXEN          AON_ACOMP1_MUXEN
#define AON_ACOMP1_MUXEN_POS      (26U)
#define AON_ACOMP1_MUXEN_LEN      (1U)
#define AON_ACOMP1_MUXEN_MSK      (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
#define AON_ACOMP1_MUXEN_UMSK     (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))

/* 0x908 : acomp_ctrl */
#define AON_ACOMP_CTRL_OFFSET    (0x908)
#define AON_ACOMP1_RSTN_ANA      AON_ACOMP1_RSTN_ANA
#define AON_ACOMP1_RSTN_ANA_POS  (0U)
#define AON_ACOMP1_RSTN_ANA_LEN  (1U)
#define AON_ACOMP1_RSTN_ANA_MSK  (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
#define AON_ACOMP0_RSTN_ANA      AON_ACOMP0_RSTN_ANA
#define AON_ACOMP0_RSTN_ANA_POS  (1U)
#define AON_ACOMP0_RSTN_ANA_LEN  (1U)
#define AON_ACOMP0_RSTN_ANA_MSK  (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
#define AON_ACOMP1_TEST_EN       AON_ACOMP1_TEST_EN
#define AON_ACOMP1_TEST_EN_POS   (8U)
#define AON_ACOMP1_TEST_EN_LEN   (1U)
#define AON_ACOMP1_TEST_EN_MSK   (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
#define AON_ACOMP1_TEST_EN_UMSK  (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
#define AON_ACOMP0_TEST_EN       AON_ACOMP0_TEST_EN
#define AON_ACOMP0_TEST_EN_POS   (9U)
#define AON_ACOMP0_TEST_EN_LEN   (1U)
#define AON_ACOMP0_TEST_EN_MSK   (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
#define AON_ACOMP0_TEST_EN_UMSK  (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
#define AON_ACOMP1_TEST_SEL      AON_ACOMP1_TEST_SEL
#define AON_ACOMP1_TEST_SEL_POS  (10U)
#define AON_ACOMP1_TEST_SEL_LEN  (2U)
#define AON_ACOMP1_TEST_SEL_MSK  (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
#define AON_ACOMP0_TEST_SEL      AON_ACOMP0_TEST_SEL
#define AON_ACOMP0_TEST_SEL_POS  (12U)
#define AON_ACOMP0_TEST_SEL_LEN  (2U)
#define AON_ACOMP0_TEST_SEL_MSK  (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
#define AON_ACOMP1_OUT_RAW       AON_ACOMP1_OUT_RAW
#define AON_ACOMP1_OUT_RAW_POS   (17U)
#define AON_ACOMP1_OUT_RAW_LEN   (1U)
#define AON_ACOMP1_OUT_RAW_MSK   (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
#define AON_ACOMP1_OUT_RAW_UMSK  (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
#define AON_ACOMP0_OUT_RAW       AON_ACOMP0_OUT_RAW
#define AON_ACOMP0_OUT_RAW_POS   (19U)
#define AON_ACOMP0_OUT_RAW_LEN   (1U)
#define AON_ACOMP0_OUT_RAW_MSK   (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
#define AON_ACOMP0_OUT_RAW_UMSK  (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
#define AON_ACOMP_RESERVED       AON_ACOMP_RESERVED
#define AON_ACOMP_RESERVED_POS   (24U)
#define AON_ACOMP_RESERVED_LEN   (8U)
#define AON_ACOMP_RESERVED_MSK   (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
#define AON_ACOMP_RESERVED_UMSK  (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))

/* 0x90C : gpadc_reg_cmd */
#define AON_GPADC_REG_CMD_OFFSET        (0x90C)
#define AON_GPADC_GLOBAL_EN             AON_GPADC_GLOBAL_EN
#define AON_GPADC_GLOBAL_EN_POS         (0U)
#define AON_GPADC_GLOBAL_EN_LEN         (1U)
#define AON_GPADC_GLOBAL_EN_MSK         (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
#define AON_GPADC_GLOBAL_EN_UMSK        (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
#define AON_GPADC_CONV_START            AON_GPADC_CONV_START
#define AON_GPADC_CONV_START_POS        (1U)
#define AON_GPADC_CONV_START_LEN        (1U)
#define AON_GPADC_CONV_START_MSK        (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
#define AON_GPADC_CONV_START_UMSK       (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
#define AON_GPADC_SOFT_RST              AON_GPADC_SOFT_RST
#define AON_GPADC_SOFT_RST_POS          (2U)
#define AON_GPADC_SOFT_RST_LEN          (1U)
#define AON_GPADC_SOFT_RST_MSK          (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
#define AON_GPADC_SOFT_RST_UMSK         (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
#define AON_GPADC_NEG_SEL               AON_GPADC_NEG_SEL
#define AON_GPADC_NEG_SEL_POS           (3U)
#define AON_GPADC_NEG_SEL_LEN           (5U)
#define AON_GPADC_NEG_SEL_MSK           (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
#define AON_GPADC_NEG_SEL_UMSK          (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
#define AON_GPADC_POS_SEL               AON_GPADC_POS_SEL
#define AON_GPADC_POS_SEL_POS           (8U)
#define AON_GPADC_POS_SEL_LEN           (5U)
#define AON_GPADC_POS_SEL_MSK           (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
#define AON_GPADC_POS_SEL_UMSK          (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
#define AON_GPADC_NEG_GND               AON_GPADC_NEG_GND
#define AON_GPADC_NEG_GND_POS           (13U)
#define AON_GPADC_NEG_GND_LEN           (1U)
#define AON_GPADC_NEG_GND_MSK           (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
#define AON_GPADC_NEG_GND_UMSK          (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
#define AON_GPADC_MICBIAS_EN            AON_GPADC_MICBIAS_EN
#define AON_GPADC_MICBIAS_EN_POS        (14U)
#define AON_GPADC_MICBIAS_EN_LEN        (1U)
#define AON_GPADC_MICBIAS_EN_MSK        (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
#define AON_GPADC_MICBIAS_EN_UMSK       (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
#define AON_GPADC_MICPGA_EN             AON_GPADC_MICPGA_EN
#define AON_GPADC_MICPGA_EN_POS         (15U)
#define AON_GPADC_MICPGA_EN_LEN         (1U)
#define AON_GPADC_MICPGA_EN_MSK         (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
#define AON_GPADC_MICPGA_EN_UMSK        (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
#define AON_GPADC_BYP_MICBOOST          AON_GPADC_BYP_MICBOOST
#define AON_GPADC_BYP_MICBOOST_POS      (16U)
#define AON_GPADC_BYP_MICBOOST_LEN      (1U)
#define AON_GPADC_BYP_MICBOOST_MSK      (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
#define AON_GPADC_BYP_MICBOOST_UMSK     (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
#define AON_GPADC_DWA_EN                AON_GPADC_DWA_EN
#define AON_GPADC_DWA_EN_POS            (18U)
#define AON_GPADC_DWA_EN_LEN            (1U)
#define AON_GPADC_DWA_EN_MSK            (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
#define AON_GPADC_DWA_EN_UMSK           (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
#define AON_GPADC_MIC2_DIFF             AON_GPADC_MIC2_DIFF
#define AON_GPADC_MIC2_DIFF_POS         (19U)
#define AON_GPADC_MIC2_DIFF_LEN         (1U)
#define AON_GPADC_MIC2_DIFF_MSK         (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
#define AON_GPADC_MIC2_DIFF_UMSK        (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
#define AON_GPADC_MIC1_DIFF             AON_GPADC_MIC1_DIFF
#define AON_GPADC_MIC1_DIFF_POS         (20U)
#define AON_GPADC_MIC1_DIFF_LEN         (1U)
#define AON_GPADC_MIC1_DIFF_MSK         (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
#define AON_GPADC_MIC1_DIFF_UMSK        (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
#define AON_GPADC_MIC_PGA2_GAIN         AON_GPADC_MIC_PGA2_GAIN
#define AON_GPADC_MIC_PGA2_GAIN_POS     (21U)
#define AON_GPADC_MIC_PGA2_GAIN_LEN     (2U)
#define AON_GPADC_MIC_PGA2_GAIN_MSK     (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
#define AON_GPADC_MIC_PGA2_GAIN_UMSK    (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
#define AON_GPADC_MICBOOST_32DB_EN      AON_GPADC_MICBOOST_32DB_EN
#define AON_GPADC_MICBOOST_32DB_EN_POS  (23U)
#define AON_GPADC_MICBOOST_32DB_EN_LEN  (1U)
#define AON_GPADC_MICBOOST_32DB_EN_MSK  (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
#define AON_GPADC_CHIP_SEN_PU           AON_GPADC_CHIP_SEN_PU
#define AON_GPADC_CHIP_SEN_PU_POS       (27U)
#define AON_GPADC_CHIP_SEN_PU_LEN       (1U)
#define AON_GPADC_CHIP_SEN_PU_MSK       (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
#define AON_GPADC_CHIP_SEN_PU_UMSK      (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
#define AON_GPADC_SEN_SEL               AON_GPADC_SEN_SEL
#define AON_GPADC_SEN_SEL_POS           (28U)
#define AON_GPADC_SEN_SEL_LEN           (2U)
#define AON_GPADC_SEN_SEL_MSK           (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
#define AON_GPADC_SEN_SEL_UMSK          (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
#define AON_GPADC_SEN_TEST_EN           AON_GPADC_SEN_TEST_EN
#define AON_GPADC_SEN_TEST_EN_POS       (30U)
#define AON_GPADC_SEN_TEST_EN_LEN       (1U)
#define AON_GPADC_SEN_TEST_EN_MSK       (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
#define AON_GPADC_SEN_TEST_EN_UMSK      (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))

/* 0x910 : gpadc_reg_config1 */
#define AON_GPADC_REG_CONFIG1_OFFSET (0x910)
#define AON_GPADC_CAL_OS_EN          AON_GPADC_CAL_OS_EN
#define AON_GPADC_CAL_OS_EN_POS      (0U)
#define AON_GPADC_CAL_OS_EN_LEN      (1U)
#define AON_GPADC_CAL_OS_EN_MSK      (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
#define AON_GPADC_CAL_OS_EN_UMSK     (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
#define AON_GPADC_CONT_CONV_EN       AON_GPADC_CONT_CONV_EN
#define AON_GPADC_CONT_CONV_EN_POS   (1U)
#define AON_GPADC_CONT_CONV_EN_LEN   (1U)
#define AON_GPADC_CONT_CONV_EN_MSK   (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
#define AON_GPADC_CONT_CONV_EN_UMSK  (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
#define AON_GPADC_RES_SEL            AON_GPADC_RES_SEL
#define AON_GPADC_RES_SEL_POS        (2U)
#define AON_GPADC_RES_SEL_LEN        (3U)
#define AON_GPADC_RES_SEL_MSK        (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
#define AON_GPADC_RES_SEL_UMSK       (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
#define AON_GPADC_VCM_SEL_EN         AON_GPADC_VCM_SEL_EN
#define AON_GPADC_VCM_SEL_EN_POS     (8U)
#define AON_GPADC_VCM_SEL_EN_LEN     (1U)
#define AON_GPADC_VCM_SEL_EN_MSK     (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)
#define AON_GPADC_VCM_SEL_EN_UMSK    (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS))
#define AON_GPADC_VCM_HYST_SEL       AON_GPADC_VCM_HYST_SEL
#define AON_GPADC_VCM_HYST_SEL_POS   (9U)
#define AON_GPADC_VCM_HYST_SEL_LEN   (1U)
#define AON_GPADC_VCM_HYST_SEL_MSK   (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)
#define AON_GPADC_VCM_HYST_SEL_UMSK  (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS))
#define AON_GPADC_LOWV_DET_EN        AON_GPADC_LOWV_DET_EN
#define AON_GPADC_LOWV_DET_EN_POS    (10U)
#define AON_GPADC_LOWV_DET_EN_LEN    (1U)
#define AON_GPADC_LOWV_DET_EN_MSK    (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)
#define AON_GPADC_LOWV_DET_EN_UMSK   (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS))
#define AON_GPADC_CLK_ANA_INV        AON_GPADC_CLK_ANA_INV
#define AON_GPADC_CLK_ANA_INV_POS    (17U)
#define AON_GPADC_CLK_ANA_INV_LEN    (1U)
#define AON_GPADC_CLK_ANA_INV_MSK    (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
#define AON_GPADC_CLK_ANA_INV_UMSK   (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
#define AON_GPADC_CLK_DIV_RATIO      AON_GPADC_CLK_DIV_RATIO
#define AON_GPADC_CLK_DIV_RATIO_POS  (18U)
#define AON_GPADC_CLK_DIV_RATIO_LEN  (3U)
#define AON_GPADC_CLK_DIV_RATIO_MSK  (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
#define AON_GPADC_SCAN_LENGTH        AON_GPADC_SCAN_LENGTH
#define AON_GPADC_SCAN_LENGTH_POS    (21U)
#define AON_GPADC_SCAN_LENGTH_LEN    (4U)
#define AON_GPADC_SCAN_LENGTH_MSK    (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
#define AON_GPADC_SCAN_LENGTH_UMSK   (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
#define AON_GPADC_SCAN_EN            AON_GPADC_SCAN_EN
#define AON_GPADC_SCAN_EN_POS        (25U)
#define AON_GPADC_SCAN_EN_LEN        (1U)
#define AON_GPADC_SCAN_EN_MSK        (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
#define AON_GPADC_SCAN_EN_UMSK       (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
#define AON_GPADC_DITHER_EN          AON_GPADC_DITHER_EN
#define AON_GPADC_DITHER_EN_POS      (26U)
#define AON_GPADC_DITHER_EN_LEN      (1U)
#define AON_GPADC_DITHER_EN_MSK      (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
#define AON_GPADC_DITHER_EN_UMSK     (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
#define AON_GPADC_V11_SEL            AON_GPADC_V11_SEL
#define AON_GPADC_V11_SEL_POS        (27U)
#define AON_GPADC_V11_SEL_LEN        (2U)
#define AON_GPADC_V11_SEL_MSK        (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
#define AON_GPADC_V11_SEL_UMSK       (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
#define AON_GPADC_V18_SEL            AON_GPADC_V18_SEL
#define AON_GPADC_V18_SEL_POS        (29U)
#define AON_GPADC_V18_SEL_LEN        (2U)
#define AON_GPADC_V18_SEL_MSK        (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
#define AON_GPADC_V18_SEL_UMSK       (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))

/* 0x914 : gpadc_reg_config2 */
#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
#define AON_GPADC_DIFF_MODE          AON_GPADC_DIFF_MODE
#define AON_GPADC_DIFF_MODE_POS      (2U)
#define AON_GPADC_DIFF_MODE_LEN      (1U)
#define AON_GPADC_DIFF_MODE_MSK      (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
#define AON_GPADC_DIFF_MODE_UMSK     (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
#define AON_GPADC_VREF_SEL           AON_GPADC_VREF_SEL
#define AON_GPADC_VREF_SEL_POS       (3U)
#define AON_GPADC_VREF_SEL_LEN       (1U)
#define AON_GPADC_VREF_SEL_MSK       (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
#define AON_GPADC_VREF_SEL_UMSK      (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
#define AON_GPADC_VBAT_EN            AON_GPADC_VBAT_EN
#define AON_GPADC_VBAT_EN_POS        (4U)
#define AON_GPADC_VBAT_EN_LEN        (1U)
#define AON_GPADC_VBAT_EN_MSK        (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
#define AON_GPADC_VBAT_EN_UMSK       (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
#define AON_GPADC_TSEXT_SEL          AON_GPADC_TSEXT_SEL
#define AON_GPADC_TSEXT_SEL_POS      (5U)
#define AON_GPADC_TSEXT_SEL_LEN      (1U)
#define AON_GPADC_TSEXT_SEL_MSK      (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
#define AON_GPADC_TSEXT_SEL_UMSK     (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
#define AON_GPADC_TS_EN              AON_GPADC_TS_EN
#define AON_GPADC_TS_EN_POS          (6U)
#define AON_GPADC_TS_EN_LEN          (1U)
#define AON_GPADC_TS_EN_MSK          (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
#define AON_GPADC_TS_EN_UMSK         (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
#define AON_GPADC_PGA_VCM            AON_GPADC_PGA_VCM
#define AON_GPADC_PGA_VCM_POS        (7U)
#define AON_GPADC_PGA_VCM_LEN        (2U)
#define AON_GPADC_PGA_VCM_MSK        (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
#define AON_GPADC_PGA_VCM_UMSK       (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
#define AON_GPADC_PGA_OS_CAL         AON_GPADC_PGA_OS_CAL
#define AON_GPADC_PGA_OS_CAL_POS     (9U)
#define AON_GPADC_PGA_OS_CAL_LEN     (4U)
#define AON_GPADC_PGA_OS_CAL_MSK     (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
#define AON_GPADC_PGA_OS_CAL_UMSK    (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
#define AON_GPADC_PGA_EN             AON_GPADC_PGA_EN
#define AON_GPADC_PGA_EN_POS         (13U)
#define AON_GPADC_PGA_EN_LEN         (1U)
#define AON_GPADC_PGA_EN_MSK         (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
#define AON_GPADC_PGA_EN_UMSK        (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
#define AON_GPADC_PGA_VCMI_EN        AON_GPADC_PGA_VCMI_EN
#define AON_GPADC_PGA_VCMI_EN_POS    (14U)
#define AON_GPADC_PGA_VCMI_EN_LEN    (1U)
#define AON_GPADC_PGA_VCMI_EN_MSK    (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
#define AON_GPADC_PGA_VCMI_EN_UMSK   (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
#define AON_GPADC_CHOP_MODE          AON_GPADC_CHOP_MODE
#define AON_GPADC_CHOP_MODE_POS      (15U)
#define AON_GPADC_CHOP_MODE_LEN      (2U)
#define AON_GPADC_CHOP_MODE_MSK      (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
#define AON_GPADC_CHOP_MODE_UMSK     (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
#define AON_GPADC_BIAS_SEL           AON_GPADC_BIAS_SEL
#define AON_GPADC_BIAS_SEL_POS       (17U)
#define AON_GPADC_BIAS_SEL_LEN       (1U)
#define AON_GPADC_BIAS_SEL_MSK       (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
#define AON_GPADC_BIAS_SEL_UMSK      (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
#define AON_GPADC_TEST_EN            AON_GPADC_TEST_EN
#define AON_GPADC_TEST_EN_POS        (18U)
#define AON_GPADC_TEST_EN_LEN        (1U)
#define AON_GPADC_TEST_EN_MSK        (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
#define AON_GPADC_TEST_EN_UMSK       (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
#define AON_GPADC_TEST_SEL           AON_GPADC_TEST_SEL
#define AON_GPADC_TEST_SEL_POS       (19U)
#define AON_GPADC_TEST_SEL_LEN       (3U)
#define AON_GPADC_TEST_SEL_MSK       (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
#define AON_GPADC_TEST_SEL_UMSK      (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
#define AON_GPADC_PGA2_GAIN          AON_GPADC_PGA2_GAIN
#define AON_GPADC_PGA2_GAIN_POS      (22U)
#define AON_GPADC_PGA2_GAIN_LEN      (3U)
#define AON_GPADC_PGA2_GAIN_MSK      (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
#define AON_GPADC_PGA2_GAIN_UMSK     (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
#define AON_GPADC_PGA1_GAIN          AON_GPADC_PGA1_GAIN
#define AON_GPADC_PGA1_GAIN_POS      (25U)
#define AON_GPADC_PGA1_GAIN_LEN      (3U)
#define AON_GPADC_PGA1_GAIN_MSK      (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
#define AON_GPADC_PGA1_GAIN_UMSK     (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
#define AON_GPADC_DLY_SEL            AON_GPADC_DLY_SEL
#define AON_GPADC_DLY_SEL_POS        (28U)
#define AON_GPADC_DLY_SEL_LEN        (3U)
#define AON_GPADC_DLY_SEL_MSK        (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
#define AON_GPADC_DLY_SEL_UMSK       (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
#define AON_GPADC_TSVBE_LOW          AON_GPADC_TSVBE_LOW
#define AON_GPADC_TSVBE_LOW_POS      (31U)
#define AON_GPADC_TSVBE_LOW_LEN      (1U)
#define AON_GPADC_TSVBE_LOW_MSK      (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
#define AON_GPADC_TSVBE_LOW_UMSK     (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))

/* 0x918 : adc converation sequence 1 */
#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
#define AON_GPADC_SCAN_POS_0          AON_GPADC_SCAN_POS_0
#define AON_GPADC_SCAN_POS_0_POS      (0U)
#define AON_GPADC_SCAN_POS_0_LEN      (5U)
#define AON_GPADC_SCAN_POS_0_MSK      (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
#define AON_GPADC_SCAN_POS_0_UMSK     (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
#define AON_GPADC_SCAN_POS_1          AON_GPADC_SCAN_POS_1
#define AON_GPADC_SCAN_POS_1_POS      (5U)
#define AON_GPADC_SCAN_POS_1_LEN      (5U)
#define AON_GPADC_SCAN_POS_1_MSK      (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
#define AON_GPADC_SCAN_POS_1_UMSK     (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
#define AON_GPADC_SCAN_POS_2          AON_GPADC_SCAN_POS_2
#define AON_GPADC_SCAN_POS_2_POS      (10U)
#define AON_GPADC_SCAN_POS_2_LEN      (5U)
#define AON_GPADC_SCAN_POS_2_MSK      (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
#define AON_GPADC_SCAN_POS_2_UMSK     (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
#define AON_GPADC_SCAN_POS_3          AON_GPADC_SCAN_POS_3
#define AON_GPADC_SCAN_POS_3_POS      (15U)
#define AON_GPADC_SCAN_POS_3_LEN      (5U)
#define AON_GPADC_SCAN_POS_3_MSK      (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
#define AON_GPADC_SCAN_POS_3_UMSK     (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
#define AON_GPADC_SCAN_POS_4          AON_GPADC_SCAN_POS_4
#define AON_GPADC_SCAN_POS_4_POS      (20U)
#define AON_GPADC_SCAN_POS_4_LEN      (5U)
#define AON_GPADC_SCAN_POS_4_MSK      (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
#define AON_GPADC_SCAN_POS_4_UMSK     (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
#define AON_GPADC_SCAN_POS_5          AON_GPADC_SCAN_POS_5
#define AON_GPADC_SCAN_POS_5_POS      (25U)
#define AON_GPADC_SCAN_POS_5_LEN      (5U)
#define AON_GPADC_SCAN_POS_5_MSK      (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
#define AON_GPADC_SCAN_POS_5_UMSK     (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))

/* 0x91C : adc converation sequence 2 */
#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
#define AON_GPADC_SCAN_POS_6          AON_GPADC_SCAN_POS_6
#define AON_GPADC_SCAN_POS_6_POS      (0U)
#define AON_GPADC_SCAN_POS_6_LEN      (5U)
#define AON_GPADC_SCAN_POS_6_MSK      (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
#define AON_GPADC_SCAN_POS_6_UMSK     (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
#define AON_GPADC_SCAN_POS_7          AON_GPADC_SCAN_POS_7
#define AON_GPADC_SCAN_POS_7_POS      (5U)
#define AON_GPADC_SCAN_POS_7_LEN      (5U)
#define AON_GPADC_SCAN_POS_7_MSK      (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
#define AON_GPADC_SCAN_POS_7_UMSK     (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
#define AON_GPADC_SCAN_POS_8          AON_GPADC_SCAN_POS_8
#define AON_GPADC_SCAN_POS_8_POS      (10U)
#define AON_GPADC_SCAN_POS_8_LEN      (5U)
#define AON_GPADC_SCAN_POS_8_MSK      (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
#define AON_GPADC_SCAN_POS_8_UMSK     (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
#define AON_GPADC_SCAN_POS_9          AON_GPADC_SCAN_POS_9
#define AON_GPADC_SCAN_POS_9_POS      (15U)
#define AON_GPADC_SCAN_POS_9_LEN      (5U)
#define AON_GPADC_SCAN_POS_9_MSK      (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
#define AON_GPADC_SCAN_POS_9_UMSK     (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
#define AON_GPADC_SCAN_POS_10         AON_GPADC_SCAN_POS_10
#define AON_GPADC_SCAN_POS_10_POS     (20U)
#define AON_GPADC_SCAN_POS_10_LEN     (5U)
#define AON_GPADC_SCAN_POS_10_MSK     (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
#define AON_GPADC_SCAN_POS_10_UMSK    (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
#define AON_GPADC_SCAN_POS_11         AON_GPADC_SCAN_POS_11
#define AON_GPADC_SCAN_POS_11_POS     (25U)
#define AON_GPADC_SCAN_POS_11_LEN     (5U)
#define AON_GPADC_SCAN_POS_11_MSK     (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
#define AON_GPADC_SCAN_POS_11_UMSK    (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))

/* 0x920 : adc converation sequence 3 */
#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
#define AON_GPADC_SCAN_NEG_0          AON_GPADC_SCAN_NEG_0
#define AON_GPADC_SCAN_NEG_0_POS      (0U)
#define AON_GPADC_SCAN_NEG_0_LEN      (5U)
#define AON_GPADC_SCAN_NEG_0_MSK      (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
#define AON_GPADC_SCAN_NEG_0_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
#define AON_GPADC_SCAN_NEG_1          AON_GPADC_SCAN_NEG_1
#define AON_GPADC_SCAN_NEG_1_POS      (5U)
#define AON_GPADC_SCAN_NEG_1_LEN      (5U)
#define AON_GPADC_SCAN_NEG_1_MSK      (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
#define AON_GPADC_SCAN_NEG_1_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
#define AON_GPADC_SCAN_NEG_2          AON_GPADC_SCAN_NEG_2
#define AON_GPADC_SCAN_NEG_2_POS      (10U)
#define AON_GPADC_SCAN_NEG_2_LEN      (5U)
#define AON_GPADC_SCAN_NEG_2_MSK      (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
#define AON_GPADC_SCAN_NEG_2_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
#define AON_GPADC_SCAN_NEG_3          AON_GPADC_SCAN_NEG_3
#define AON_GPADC_SCAN_NEG_3_POS      (15U)
#define AON_GPADC_SCAN_NEG_3_LEN      (5U)
#define AON_GPADC_SCAN_NEG_3_MSK      (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
#define AON_GPADC_SCAN_NEG_3_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
#define AON_GPADC_SCAN_NEG_4          AON_GPADC_SCAN_NEG_4
#define AON_GPADC_SCAN_NEG_4_POS      (20U)
#define AON_GPADC_SCAN_NEG_4_LEN      (5U)
#define AON_GPADC_SCAN_NEG_4_MSK      (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
#define AON_GPADC_SCAN_NEG_4_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
#define AON_GPADC_SCAN_NEG_5          AON_GPADC_SCAN_NEG_5
#define AON_GPADC_SCAN_NEG_5_POS      (25U)
#define AON_GPADC_SCAN_NEG_5_LEN      (5U)
#define AON_GPADC_SCAN_NEG_5_MSK      (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
#define AON_GPADC_SCAN_NEG_5_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))

/* 0x924 : adc converation sequence 4 */
#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
#define AON_GPADC_SCAN_NEG_6          AON_GPADC_SCAN_NEG_6
#define AON_GPADC_SCAN_NEG_6_POS      (0U)
#define AON_GPADC_SCAN_NEG_6_LEN      (5U)
#define AON_GPADC_SCAN_NEG_6_MSK      (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
#define AON_GPADC_SCAN_NEG_6_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
#define AON_GPADC_SCAN_NEG_7          AON_GPADC_SCAN_NEG_7
#define AON_GPADC_SCAN_NEG_7_POS      (5U)
#define AON_GPADC_SCAN_NEG_7_LEN      (5U)
#define AON_GPADC_SCAN_NEG_7_MSK      (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
#define AON_GPADC_SCAN_NEG_7_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
#define AON_GPADC_SCAN_NEG_8          AON_GPADC_SCAN_NEG_8
#define AON_GPADC_SCAN_NEG_8_POS      (10U)
#define AON_GPADC_SCAN_NEG_8_LEN      (5U)
#define AON_GPADC_SCAN_NEG_8_MSK      (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
#define AON_GPADC_SCAN_NEG_8_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
#define AON_GPADC_SCAN_NEG_9          AON_GPADC_SCAN_NEG_9
#define AON_GPADC_SCAN_NEG_9_POS      (15U)
#define AON_GPADC_SCAN_NEG_9_LEN      (5U)
#define AON_GPADC_SCAN_NEG_9_MSK      (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
#define AON_GPADC_SCAN_NEG_9_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
#define AON_GPADC_SCAN_NEG_10         AON_GPADC_SCAN_NEG_10
#define AON_GPADC_SCAN_NEG_10_POS     (20U)
#define AON_GPADC_SCAN_NEG_10_LEN     (5U)
#define AON_GPADC_SCAN_NEG_10_MSK     (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
#define AON_GPADC_SCAN_NEG_10_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
#define AON_GPADC_SCAN_NEG_11         AON_GPADC_SCAN_NEG_11
#define AON_GPADC_SCAN_NEG_11_POS     (25U)
#define AON_GPADC_SCAN_NEG_11_LEN     (5U)
#define AON_GPADC_SCAN_NEG_11_MSK     (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
#define AON_GPADC_SCAN_NEG_11_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))

/* 0x928 : gpadc_reg_status */
#define AON_GPADC_REG_STATUS_OFFSET (0x928)
#define AON_GPADC_DATA_RDY          AON_GPADC_DATA_RDY
#define AON_GPADC_DATA_RDY_POS      (0U)
#define AON_GPADC_DATA_RDY_LEN      (1U)
#define AON_GPADC_DATA_RDY_MSK      (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
#define AON_GPADC_DATA_RDY_UMSK     (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
#define AON_GPADC_RESERVED          AON_GPADC_RESERVED
#define AON_GPADC_RESERVED_POS      (16U)
#define AON_GPADC_RESERVED_LEN      (16U)
#define AON_GPADC_RESERVED_MSK      (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
#define AON_GPADC_RESERVED_UMSK     (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))

/* 0x92C : gpadc_reg_isr */
#define AON_GPADC_REG_ISR_OFFSET      (0x92C)
#define AON_GPADC_NEG_SATUR           AON_GPADC_NEG_SATUR
#define AON_GPADC_NEG_SATUR_POS       (0U)
#define AON_GPADC_NEG_SATUR_LEN       (1U)
#define AON_GPADC_NEG_SATUR_MSK       (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
#define AON_GPADC_NEG_SATUR_UMSK      (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
#define AON_GPADC_POS_SATUR           AON_GPADC_POS_SATUR
#define AON_GPADC_POS_SATUR_POS       (1U)
#define AON_GPADC_POS_SATUR_LEN       (1U)
#define AON_GPADC_POS_SATUR_MSK       (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
#define AON_GPADC_POS_SATUR_UMSK      (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
#define AON_GPADC_NEG_SATUR_CLR       AON_GPADC_NEG_SATUR_CLR
#define AON_GPADC_NEG_SATUR_CLR_POS   (4U)
#define AON_GPADC_NEG_SATUR_CLR_LEN   (1U)
#define AON_GPADC_NEG_SATUR_CLR_MSK   (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
#define AON_GPADC_NEG_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
#define AON_GPADC_POS_SATUR_CLR       AON_GPADC_POS_SATUR_CLR
#define AON_GPADC_POS_SATUR_CLR_POS   (5U)
#define AON_GPADC_POS_SATUR_CLR_LEN   (1U)
#define AON_GPADC_POS_SATUR_CLR_MSK   (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
#define AON_GPADC_POS_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
#define AON_GPADC_NEG_SATUR_MASK      AON_GPADC_NEG_SATUR_MASK
#define AON_GPADC_NEG_SATUR_MASK_POS  (8U)
#define AON_GPADC_NEG_SATUR_MASK_LEN  (1U)
#define AON_GPADC_NEG_SATUR_MASK_MSK  (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
#define AON_GPADC_POS_SATUR_MASK      AON_GPADC_POS_SATUR_MASK
#define AON_GPADC_POS_SATUR_MASK_POS  (9U)
#define AON_GPADC_POS_SATUR_MASK_LEN  (1U)
#define AON_GPADC_POS_SATUR_MASK_MSK  (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))

/* 0x930 : gpadc_reg_result */
#define AON_GPADC_REG_RESULT_OFFSET (0x930)
#define AON_GPADC_DATA_OUT          AON_GPADC_DATA_OUT
#define AON_GPADC_DATA_OUT_POS      (0U)
#define AON_GPADC_DATA_OUT_LEN      (26U)
#define AON_GPADC_DATA_OUT_MSK      (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
#define AON_GPADC_DATA_OUT_UMSK     (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))

/* 0x934 : gpadc_reg_raw_result */
#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
#define AON_GPADC_RAW_DATA              AON_GPADC_RAW_DATA
#define AON_GPADC_RAW_DATA_POS          (0U)
#define AON_GPADC_RAW_DATA_LEN          (12U)
#define AON_GPADC_RAW_DATA_MSK          (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
#define AON_GPADC_RAW_DATA_UMSK         (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))

/* 0x938 : gpadc_reg_define */
#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
#define AON_GPADC_OS_CAL_DATA       AON_GPADC_OS_CAL_DATA
#define AON_GPADC_OS_CAL_DATA_POS   (0U)
#define AON_GPADC_OS_CAL_DATA_LEN   (16U)
#define AON_GPADC_OS_CAL_DATA_MSK   (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
#define AON_GPADC_OS_CAL_DATA_UMSK  (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))

/* 0x93C : hbncore_resv0 */
#define AON_HBNCORE_RESV0_OFFSET    (0x93C)
#define AON_HBNCORE_RESV0_DATA      AON_HBNCORE_RESV0_DATA
#define AON_HBNCORE_RESV0_DATA_POS  (0U)
#define AON_HBNCORE_RESV0_DATA_LEN  (32U)
#define AON_HBNCORE_RESV0_DATA_MSK  (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))

/* 0x940 : hbncore_resv1 */
#define AON_HBNCORE_RESV1_OFFSET    (0x940)
#define AON_HBNCORE_RESV1_DATA      AON_HBNCORE_RESV1_DATA
#define AON_HBNCORE_RESV1_DATA_POS  (0U)
#define AON_HBNCORE_RESV1_DATA_LEN  (32U)
#define AON_HBNCORE_RESV1_DATA_MSK  (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))

struct aon_reg {
    /* 0x0  reserved */
    uint8_t RESERVED0x0[2048];

    /* 0x800 : aon */
    union {
        struct
        {
            uint32_t aon_resv              : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
            uint32_t pu_aon_dc_tbuf        : 1; /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_19        : 7; /* [19:13],       rsvd,        0x0 */
            uint32_t ldo11_rt_pulldown     : 1; /* [   20],        r/w,        0x0 */
            uint32_t ldo11_rt_pulldown_sel : 1; /* [   21],        r/w,        0x0 */
            uint32_t sw_pu_ldo11_rt        : 1; /* [   22],        r/w,        0x1 */
            uint32_t reserved_23_31        : 9; /* [31:23],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } aon;

    /* 0x804 : aon_common */
    union {
        struct
        {
            uint32_t tmux_aon         : 3;  /* [ 2: 0],        r/w,        0x0 */
            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t ten_aon          : 1;  /* [    4],        r/w,        0x0 */
            uint32_t dten_xtal32k     : 1;  /* [    5],        r/w,        0x0 */
            uint32_t ten_xtal32k      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7       : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t ten_vddcore_aon  : 1;  /* [    8],        r/w,        0x0 */
            uint32_t ten_ldo11soc_aon : 1;  /* [    9],        r/w,        0x0 */
            uint32_t ten_dcdc18_0_aon : 1;  /* [   10],        r/w,        0x0 */
            uint32_t ten_dcdc18_1_aon : 1;  /* [   11],        r/w,        0x0 */
            uint32_t ten_bg_sys_aon   : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_15   : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t ten_ldo15rf_aon  : 1;  /* [   16],        r/w,        0x0 */
            uint32_t ten_xtal_aon     : 1;  /* [   17],        r/w,        0x0 */
            uint32_t dten_xtal_aon    : 1;  /* [   18],        r/w,        0x0 */
            uint32_t ten_mbg_aon      : 1;  /* [   19],        r/w,        0x0 */
            uint32_t ten_cip_misc_aon : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } aon_common;

    /* 0x808 : aon_misc */
    union {
        struct
        {
            uint32_t sw_soc_en_aon : 1;  /* [    0],        r/w,        0x1 */
            uint32_t sw_bz_en_aon  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } aon_misc;

    /* 0x80c  reserved */
    uint8_t RESERVED0x80c[4];

    /* 0x810 : bg_sys_top */
    union {
        struct
        {
            uint32_t pmip_resv             : 8;  /* [ 7: 0],        r/w,        0x0 */
            uint32_t pu_bg_sys_aon         : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_11         : 3;  /* [11: 9],       rsvd,        0x0 */
            uint32_t bg_sys_start_ctrl_aon : 1;  /* [   12],        r/w,        0x1 */
            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } bg_sys_top;

    /* 0x814 : dcdc18_top_0 */
    union {
        struct
        {
            uint32_t reserved_0                : 1; /* [    0],       rsvd,        0x0 */
            uint32_t dcdc18_vout_sel_aon       : 5; /* [ 5: 1],        r/w,       0x1b */
            uint32_t reserved_6_7              : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t dcdc18_vpfm_aon           : 4; /* [11: 8],        r/w,        0x7 */
            uint32_t dcdc18_osc_2m_mode_aon    : 1; /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_15            : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t dcdc18_osc_freq_trim_aon  : 4; /* [19:16],        r/w,        0x8 */
            uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20],        r/w,        0x5 */
            uint32_t dcdc18_stop_osc_aon       : 1; /* [   25],        r/w,        0x1 */
            uint32_t dcdc18_slow_osc_aon       : 1; /* [   26],        r/w,        0x0 */
            uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [   27],        r/w,        0x1 */
            uint32_t dcdc18_sstart_time_aon    : 2; /* [29:28],        r/w,        0x0 */
            uint32_t reserved_30               : 1; /* [   30],       rsvd,        0x0 */
            uint32_t dcdc18_rdy_aon            : 1; /* [   31],          r,        0x1 */
        } BF;
        uint32_t WORD;
    } dcdc18_top_0;

    /* 0x818 : dcdc18_top_1 */
    union {
        struct
        {
            uint32_t dcdc18_force_cs_zvs_aon  : 1; /* [    0],        r/w,        0x0 */
            uint32_t dcdc18_cs_delay_aon      : 3; /* [ 3: 1],        r/w,        0x4 */
            uint32_t dcdc18_zvs_td_opt_aon    : 3; /* [ 6: 4],        r/w,        0x4 */
            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
            uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8],        r/w,        0x0 */
            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t dcdc18_rc_sel_aon        : 4; /* [19:16],        r/w,        0x8 */
            uint32_t dcdc18_chf_sel_aon       : 4; /* [23:20],        r/w,        0x1 */
            uint32_t dcdc18_cfb_sel_aon       : 4; /* [27:24],        r/w,        0x8 */
            uint32_t dcdc18_en_antiring_aon   : 1; /* [   28],        r/w,        0x1 */
            uint32_t dcdc18_pulldown_aon      : 1; /* [   29],        r/w,        0x0 */
            uint32_t reserved_30_31           : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } dcdc18_top_1;

    /* 0x81C : ldo11soc_and_dctest */
    union {
        struct
        {
            uint32_t pu_ldo11soc_aon           : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reserved_1_3              : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t ldo11soc_sstart_sel_aon   : 1;  /* [    4],        r/w,        0x1 */
            uint32_t reserved_5_7              : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t ldo11soc_sstart_delay_aon : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t ldo11soc_pulldown_aon     : 1;  /* [   10],        r/w,        0x0 */
            uint32_t ldo11soc_pulldown_sel_aon : 1;  /* [   11],        r/w,        0x1 */
            uint32_t ldo11soc_vth_sel_aon      : 2;  /* [13:12],        r/w,        0x1 */
            uint32_t reserved_14_23            : 10; /* [23:14],       rsvd,        0x0 */
            uint32_t ldo11soc_cc_aon           : 2;  /* [25:24],        r/w,        0x0 */
            uint32_t reserved_26_27            : 2;  /* [27:26],       rsvd,        0x0 */
            uint32_t ldo11soc_rdy_aon          : 1;  /* [   28],          r,        0x1 */
            uint32_t ldo11soc_power_good_aon   : 1;  /* [   29],          r,        0x1 */
            uint32_t pu_vddcore_misc_aon       : 1;  /* [   30],        r/w,        0x1 */
            uint32_t pmip_dc_tp_out_en_aon     : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ldo11soc_and_dctest;

    /* 0x820 : psw_irrcv */
    union {
        struct
        {
            uint32_t pu_ir_psw_aon : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psw_irrcv;

    /* 0x824  reserved */
    uint8_t RESERVED0x824[92];

    /* 0x880 : rf_top_aon */
    union {
        struct
        {
            uint32_t pu_mbg_aon               : 1; /* [    0],        r/w,        0x1 */
            uint32_t pu_ldo15rf_aon           : 1; /* [    1],        r/w,        0x1 */
            uint32_t pu_sfreg_aon             : 1; /* [    2],        r/w,        0x1 */
            uint32_t reserved_3               : 1; /* [    3],       rsvd,        0x0 */
            uint32_t pu_xtal_buf_aon          : 1; /* [    4],        r/w,        0x1 */
            uint32_t pu_xtal_aon              : 1; /* [    5],        r/w,        0x1 */
            uint32_t reserved_6_7             : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t ldo15rf_sstart_sel_aon   : 1; /* [    8],        r/w,        0x1 */
            uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9],        r/w,        0x0 */
            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
            uint32_t ldo15rf_pulldown_aon     : 1; /* [   12],        r/w,        0x0 */
            uint32_t ldo15rf_pulldown_sel_aon : 1; /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t ldo15rf_vout_sel_aon     : 3; /* [18:16],        r/w,        0x2 */
            uint32_t reserved_19_23           : 5; /* [23:19],       rsvd,        0x0 */
            uint32_t ldo15rf_cc_aon           : 2; /* [25:24],        r/w,        0x0 */
            uint32_t reserved_26_27           : 2; /* [27:26],       rsvd,        0x0 */
            uint32_t ldo15rf_bypass_aon       : 1; /* [   28],        r/w,        0x0 */
            uint32_t reserved_29_31           : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rf_top_aon;

    /* 0x884 : xtal_cfg */
    union {
        struct
        {
            uint32_t xtal_bk_aon            : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t xtal_capcode_extra_aon : 1; /* [    2],        r/w,        0x0 */
            uint32_t xtal_ext_sel_aon       : 1; /* [    3],        r/w,        0x0 */
            uint32_t xtal_buf_en_aon        : 4; /* [ 7: 4],        r/w,        0xf */
            uint32_t xtal_buf_hp_aon        : 4; /* [11: 8],        r/w,        0x0 */
            uint32_t xtal_fast_startup_aon  : 1; /* [   12],        r/w,        0x1 */
            uint32_t xtal_sleep_aon         : 1; /* [   13],        r/w,        0x1 */
            uint32_t xtal_amp_ctrl_aon      : 2; /* [15:14],        r/w,        0x3 */
            uint32_t xtal_capcode_out_aon   : 6; /* [21:16],        r/w,       0x10 */
            uint32_t xtal_capcode_in_aon    : 6; /* [27:22],        r/w,       0x10 */
            uint32_t xtal_gm_boost_aon      : 2; /* [29:28],        r/w,        0x3 */
            uint32_t xtal_rdy_sel_aon       : 2; /* [31:30],        r/w,        0x2 */
        } BF;
        uint32_t WORD;
    } xtal_cfg;

    /* 0x888 : tsen */
    union {
        struct
        {
            uint32_t tsen_refcode_corner  : 12; /* [11: 0],        r/w,      0x8ff */
            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t tsen_refcode_rfcal   : 12; /* [27:16],        r/w,      0x8ff */
            uint32_t xtal_rdy             : 1;  /* [   28],          r,        0x1 */
            uint32_t xtal_inn_cfg_en_aon  : 1;  /* [   29],        r/w,        0x1 */
            uint32_t xtal_rdy_int_sel_aon : 2;  /* [31:30],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } tsen;

    /* 0x88c  reserved */
    uint8_t RESERVED0x88c[116];

    /* 0x900 : acomp0_ctrl */
    union {
        struct
        {
            uint32_t acomp0_en        : 1; /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
            uint32_t acomp0_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
            uint32_t acomp0_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
            uint32_t acomp0_bias_prog : 2; /* [11:10],        r/w,        0x0 */
            uint32_t acomp0_level_sel : 6; /* [17:12],        r/w,        0x0 */
            uint32_t acomp0_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
            uint32_t acomp0_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
            uint32_t acomp0_muxen     : 1; /* [   26],        r/w,        0x0 */
            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } acomp0_ctrl;

    /* 0x904 : acomp1_ctrl */
    union {
        struct
        {
            uint32_t acomp1_en        : 1; /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
            uint32_t acomp1_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
            uint32_t acomp1_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
            uint32_t acomp1_bias_prog : 2; /* [11:10],        r/w,        0x0 */
            uint32_t acomp1_level_sel : 6; /* [17:12],        r/w,        0x0 */
            uint32_t acomp1_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
            uint32_t acomp1_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
            uint32_t acomp1_muxen     : 1; /* [   26],        r/w,        0x0 */
            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } acomp1_ctrl;

    /* 0x908 : acomp_ctrl */
    union {
        struct
        {
            uint32_t acomp1_rstn_ana : 1; /* [    0],        r/w,        0x1 */
            uint32_t acomp0_rstn_ana : 1; /* [    1],        r/w,        0x1 */
            uint32_t reserved_2_7    : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t acomp1_test_en  : 1; /* [    8],        r/w,        0x0 */
            uint32_t acomp0_test_en  : 1; /* [    9],        r/w,        0x0 */
            uint32_t acomp1_test_sel : 2; /* [11:10],        r/w,        0x0 */
            uint32_t acomp0_test_sel : 2; /* [13:12],        r/w,        0x0 */
            uint32_t reserved_14_16  : 3; /* [16:14],       rsvd,        0x0 */
            uint32_t acomp1_out_raw  : 1; /* [   17],          r,        0x0 */
            uint32_t reserved_18     : 1; /* [   18],       rsvd,        0x0 */
            uint32_t acomp0_out_raw  : 1; /* [   19],          r,        0x0 */
            uint32_t reserved_20_23  : 4; /* [23:20],       rsvd,        0x0 */
            uint32_t acomp_reserved  : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } acomp_ctrl;

    /* 0x90C : gpadc_reg_cmd */
    union {
        struct
        {
            uint32_t gpadc_global_en        : 1; /* [    0],        r/w,        0x0 */
            uint32_t gpadc_conv_start       : 1; /* [    1],        r/w,        0x0 */
            uint32_t gpadc_soft_rst         : 1; /* [    2],        r/w,        0x0 */
            uint32_t gpadc_neg_sel          : 5; /* [ 7: 3],        r/w,        0xf */
            uint32_t gpadc_pos_sel          : 5; /* [12: 8],        r/w,        0xf */
            uint32_t gpadc_neg_gnd          : 1; /* [   13],        r/w,        0x0 */
            uint32_t gpadc_micbias_en       : 1; /* [   14],        r/w,        0x0 */
            uint32_t gpadc_micpga_en        : 1; /* [   15],        r/w,        0x0 */
            uint32_t gpadc_byp_micboost     : 1; /* [   16],        r/w,        0x0 */
            uint32_t reserved_17            : 1; /* [   17],       rsvd,        0x0 */
            uint32_t gpadc_dwa_en           : 1; /* [   18],        r/w,        0x0 */
            uint32_t gpadc_mic2_diff        : 1; /* [   19],        r/w,        0x0 */
            uint32_t gpadc_mic1_diff        : 1; /* [   20],        r/w,        0x0 */
            uint32_t gpadc_mic_pga2_gain    : 2; /* [22:21],        r/w,        0x0 */
            uint32_t gpadc_micboost_32db_en : 1; /* [   23],        r/w,        0x0 */
            uint32_t reserved_24_26         : 3; /* [26:24],       rsvd,        0x0 */
            uint32_t gpadc_chip_sen_pu      : 1; /* [   27],        r/w,        0x0 */
            uint32_t gpadc_sen_sel          : 2; /* [29:28],        r/w,        0x0 */
            uint32_t gpadc_sen_test_en      : 1; /* [   30],        r/w,        0x0 */
            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_cmd;

    /* 0x910 : gpadc_reg_config1 */
    union {
        struct
        {
            uint32_t gpadc_cal_os_en     : 1; /* [    0],        r/w,        0x0 */
            uint32_t gpadc_cont_conv_en  : 1; /* [    1],        r/w,        0x1 */
            uint32_t gpadc_res_sel       : 3; /* [ 4: 2],        r/w,        0x0 */
            uint32_t reserved_5_7        : 3; /* [ 7: 5],       rsvd,        0x0 */
            uint32_t gpadc_vcm_sel_en    : 1; /* [    8],        r/w,        0x0 */
            uint32_t gpadc_vcm_hyst_sel  : 1; /* [    9],        r/w,        0x0 */
            uint32_t gpadc_lowv_det_en   : 1; /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_16      : 6; /* [16:11],       rsvd,        0x0 */
            uint32_t gpadc_clk_ana_inv   : 1; /* [   17],        r/w,        0x0 */
            uint32_t gpadc_clk_div_ratio : 3; /* [20:18],        r/w,        0x3 */
            uint32_t gpadc_scan_length   : 4; /* [24:21],        r/w,        0x0 */
            uint32_t gpadc_scan_en       : 1; /* [   25],        r/w,        0x0 */
            uint32_t gpadc_dither_en     : 1; /* [   26],        r/w,        0x0 */
            uint32_t gpadc_v11_sel       : 2; /* [28:27],        r/w,        0x0 */
            uint32_t gpadc_v18_sel       : 2; /* [30:29],        r/w,        0x0 */
            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_config1;

    /* 0x914 : gpadc_reg_config2 */
    union {
        struct
        {
            uint32_t reserved_0_1      : 2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t gpadc_diff_mode   : 1; /* [    2],        r/w,        0x0 */
            uint32_t gpadc_vref_sel    : 1; /* [    3],        r/w,        0x0 */
            uint32_t gpadc_vbat_en     : 1; /* [    4],        r/w,        0x0 */
            uint32_t gpadc_tsext_sel   : 1; /* [    5],        r/w,        0x0 */
            uint32_t gpadc_ts_en       : 1; /* [    6],        r/w,        0x0 */
            uint32_t gpadc_pga_vcm     : 2; /* [ 8: 7],        r/w,        0x2 */
            uint32_t gpadc_pga_os_cal  : 4; /* [12: 9],        r/w,        0x8 */
            uint32_t gpadc_pga_en      : 1; /* [   13],        r/w,        0x0 */
            uint32_t gpadc_pga_vcmi_en : 1; /* [   14],        r/w,        0x0 */
            uint32_t gpadc_chop_mode   : 2; /* [16:15],        r/w,        0x3 */
            uint32_t gpadc_bias_sel    : 1; /* [   17],        r/w,        0x0 */
            uint32_t gpadc_test_en     : 1; /* [   18],        r/w,        0x0 */
            uint32_t gpadc_test_sel    : 3; /* [21:19],        r/w,        0x0 */
            uint32_t gpadc_pga2_gain   : 3; /* [24:22],        r/w,        0x0 */
            uint32_t gpadc_pga1_gain   : 3; /* [27:25],        r/w,        0x0 */
            uint32_t gpadc_dly_sel     : 3; /* [30:28],        r/w,        0x0 */
            uint32_t gpadc_tsvbe_low   : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_config2;

    /* 0x918 : adc converation sequence 1 */
    union {
        struct
        {
            uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0],        r/w,        0xf */
            uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5],        r/w,        0xf */
            uint32_t gpadc_scan_pos_2 : 5; /* [14:10],        r/w,        0xf */
            uint32_t gpadc_scan_pos_3 : 5; /* [19:15],        r/w,        0xf */
            uint32_t gpadc_scan_pos_4 : 5; /* [24:20],        r/w,        0xf */
            uint32_t gpadc_scan_pos_5 : 5; /* [29:25],        r/w,        0xf */
            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_scn_pos1;

    /* 0x91C : adc converation sequence 2 */
    union {
        struct
        {
            uint32_t gpadc_scan_pos_6  : 5; /* [ 4: 0],        r/w,        0xf */
            uint32_t gpadc_scan_pos_7  : 5; /* [ 9: 5],        r/w,        0xf */
            uint32_t gpadc_scan_pos_8  : 5; /* [14:10],        r/w,        0xf */
            uint32_t gpadc_scan_pos_9  : 5; /* [19:15],        r/w,        0xf */
            uint32_t gpadc_scan_pos_10 : 5; /* [24:20],        r/w,        0xf */
            uint32_t gpadc_scan_pos_11 : 5; /* [29:25],        r/w,        0xf */
            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_scn_pos2;

    /* 0x920 : adc converation sequence 3 */
    union {
        struct
        {
            uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0],        r/w,        0xf */
            uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5],        r/w,        0xf */
            uint32_t gpadc_scan_neg_2 : 5; /* [14:10],        r/w,        0xf */
            uint32_t gpadc_scan_neg_3 : 5; /* [19:15],        r/w,        0xf */
            uint32_t gpadc_scan_neg_4 : 5; /* [24:20],        r/w,        0xf */
            uint32_t gpadc_scan_neg_5 : 5; /* [29:25],        r/w,        0xf */
            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_scn_neg1;

    /* 0x924 : adc converation sequence 4 */
    union {
        struct
        {
            uint32_t gpadc_scan_neg_6  : 5; /* [ 4: 0],        r/w,        0xf */
            uint32_t gpadc_scan_neg_7  : 5; /* [ 9: 5],        r/w,        0xf */
            uint32_t gpadc_scan_neg_8  : 5; /* [14:10],        r/w,        0xf */
            uint32_t gpadc_scan_neg_9  : 5; /* [19:15],        r/w,        0xf */
            uint32_t gpadc_scan_neg_10 : 5; /* [24:20],        r/w,        0xf */
            uint32_t gpadc_scan_neg_11 : 5; /* [29:25],        r/w,        0xf */
            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_scn_neg2;

    /* 0x928 : gpadc_reg_status */
    union {
        struct
        {
            uint32_t gpadc_data_rdy : 1;  /* [    0],          r,        0x0 */
            uint32_t reserved_1_15  : 15; /* [15: 1],       rsvd,        0x0 */
            uint32_t gpadc_reserved : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_status;

    /* 0x92C : gpadc_reg_isr */
    union {
        struct
        {
            uint32_t gpadc_neg_satur      : 1;  /* [    0],          r,        0x0 */
            uint32_t gpadc_pos_satur      : 1;  /* [    1],          r,        0x0 */
            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
            uint32_t gpadc_neg_satur_clr  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t gpadc_pos_satur_clr  : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t gpadc_neg_satur_mask : 1;  /* [    8],        r/w,        0x0 */
            uint32_t gpadc_pos_satur_mask : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10_31       : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_isr;

    /* 0x930 : gpadc_reg_result */
    union {
        struct
        {
            uint32_t gpadc_data_out : 26; /* [25: 0],          r,  0x1ef0000 */
            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_result;

    /* 0x934 : gpadc_reg_raw_result */
    union {
        struct
        {
            uint32_t gpadc_raw_data : 12; /* [11: 0],          r,        0x0 */
            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_raw_result;

    /* 0x938 : gpadc_reg_define */
    union {
        struct
        {
            uint32_t gpadc_os_cal_data : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_reg_define;

    /* 0x93C : hbncore_resv0 */
    union {
        struct
        {
            uint32_t hbncore_resv0_data : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } hbncore_resv0;

    /* 0x940 : hbncore_resv1 */
    union {
        struct
        {
            uint32_t hbncore_resv1_data : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } hbncore_resv1;
};

typedef volatile struct aon_reg aon_reg_t;

#endif /* __AON_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl702.h
================================================
#ifndef __BL702_H__
#define __BL702_H__

/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */

/** @addtogroup Configuration_section_for_RISCV
 * @{
 */

/**
 * @brief Configuration of the Processor and Core Peripherals
 */

/* fix 57.6M */
#define SystemCoreClockSet(val)                 \
  if ((int)val == (int)(57.6000 * 1000)) {      \
    BL_WR_WORD(0x4000F108, 57.6 * 1000 * 1000); \
  } else {                                      \
    BL_WR_WORD(0x4000F108, val);                \
  }
#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)

/**
 * @}
 */

/** @addtogroup Peripheral_interrupt_number_definition
 * @{
 */

#ifdef ARCH_ARM
#define IRQ_NUM_BASE 0
#endif

#ifdef ARCH_RISCV
#define IRQ_NUM_BASE 16
#endif
/**
 * @brief BL702 Interrupt Number Definition, according to the selected device
 *        in @ref Library_configuration_section
 */
typedef enum {
#ifdef ARCH_ARM
  /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  NonMaskableInt_IRQn   = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
  HardFault_IRQn        = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt                           */
  BusFault_IRQn         = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
  UsageFault_IRQn       = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
  SVCall_IRQn           = -5,  /*!< 11 Cortex-M4 SV Call Interrupt                                    */
  DebugMonitor_IRQn     = -4,  /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
  PendSV_IRQn           = -2,  /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
  SysTick_IRQn          = -1,  /*!< 15 Cortex-M4 System Tick Interrupt                                */
#endif
#ifdef ARCH_RISCV
  MSOFT_IRQn          = 3,  /*!< 3 RISCV machine software Interrupt                                */
  MTIME_IRQn          = 7,  /*!< 7 RISCV machine time Interrupt                                    */
  MEXT_IRQn           = 11, /*!< 11 RISCV external  Interrupt                                      */
  CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending  Interrupt                         */
#endif
  /******  BL702 specific Interrupt Numbers **********************************************************************/
  BMX_ERR_IRQn          = IRQ_NUM_BASE + 0,  /*!< BMX Error Interrupt                                               */
  BMX_TO_IRQn           = IRQ_NUM_BASE + 1,  /*!< BMX Timeout Interrupt                                             */
  L1C_BMX_ERR_IRQn      = IRQ_NUM_BASE + 2,  /*!< L1C BMX Error Interrupt                                           */
  L1C_BMX_TO_IRQn       = IRQ_NUM_BASE + 3,  /*!< L1C BMX Timeout Interrupt                                         */
  SEC_BMX_ERR_IRQn      = IRQ_NUM_BASE + 4,  /*!< SEC BMX Error Interrupt                                           */
  RF_TOP_INT0_IRQn      = IRQ_NUM_BASE + 5,  /*!< RF_TOP_INT0 Interrupt                                             */
  RF_TOP_INT1_IRQn      = IRQ_NUM_BASE + 6,  /*!< RF_TOP_INT1 Interrupt                                             */
  RESERVED0             = IRQ_NUM_BASE + 7,  /*!< RESERVED Interrupt                                                */
  DMA_BMX_ERR_IRQn      = IRQ_NUM_BASE + 8,  /*!< DMA BMX Error Interrupt                                           */
  SEC_GMAC_IRQn         = IRQ_NUM_BASE + 9,  /*!< SEC_ENG_GMAC_INT Interrupt                                        */
  SEC_CDET_IRQn         = IRQ_NUM_BASE + 10, /*!< SEC_ENG_CDET_INT Interrupt                                        */
  SEC_PKA_IRQn          = IRQ_NUM_BASE + 11, /*!< SEC_ENG_PKA_INT  Interrupt                                        */
  SEC_TRNG_IRQn         = IRQ_NUM_BASE + 12, /*!< SEC_ENG_TRNG_INT Interrupt                                        */
  SEC_AES_IRQn          = IRQ_NUM_BASE + 13, /*!< SEC_ENG_AES_INT  Interrupt                                        */
  SEC_SHA_IRQn          = IRQ_NUM_BASE + 14, /*!< SEC_ENG_SHA_INT  Interrupt                                        */
  DMA_ALL_IRQn          = IRQ_NUM_BASE + 15, /*!< DMA ALL Interrupt                                                 */
  MJPEG_IRQn            = IRQ_NUM_BASE + 16, /*!< MJPEG Interrupt                                                   */
  CAM_IRQn              = IRQ_NUM_BASE + 17, /*!< CAM Interrupt                                                     */
  I2S_IRQn              = IRQ_NUM_BASE + 18, /*!< I2S Interrupt                                                     */
  IRTX_IRQn             = IRQ_NUM_BASE + 19, /*!< IR TX Interrupt                                                   */
  IRRX_IRQn             = IRQ_NUM_BASE + 20, /*!< IR RX Interrupt                                                   */
  USB_IRQn              = IRQ_NUM_BASE + 21, /*!< USB Interrupt                                                     */
  EMAC_IRQn             = IRQ_NUM_BASE + 22, /*!< EMAC  Interrupt                                                   */
  SF_CTRL_IRQn          = IRQ_NUM_BASE + 23, /*!< SF_CTRL   Interrupt                                               */
  RESERVED1             = IRQ_NUM_BASE + 24, /*!< RESERVED  Interrupt                                               */
  GPADC_DMA_IRQn        = IRQ_NUM_BASE + 25, /*!< GPADC_DMA Interrupt                                               */
  EFUSE_IRQn            = IRQ_NUM_BASE + 26, /*!< Efuse Interrupt                                                   */
  SPI_IRQn              = IRQ_NUM_BASE + 27, /*!< SPI   Interrupt                                                   */
  RESERVED2             = IRQ_NUM_BASE + 28, /*!< RESERVED Interrupt                                                */
  UART0_IRQn            = IRQ_NUM_BASE + 29, /*!< UART  Interrupt                                                   */
  UART1_IRQn            = IRQ_NUM_BASE + 30, /*!< UART1 Interrupt                                                   */
  RESERVED3             = IRQ_NUM_BASE + 31, /*!< RESERVED Interrupt                                                */
  I2C_IRQn              = IRQ_NUM_BASE + 32, /*!< I2C   Interrupt                                                   */
  RESERVED4             = IRQ_NUM_BASE + 33, /*!< RESERVED Interrupt                                                */
  PWM_IRQn              = IRQ_NUM_BASE + 34, /*!< PWM   Interrupt                                                   */
  RESERVED5             = IRQ_NUM_BASE + 35, /*!< RESERVED Interrupt                                                */
  TIMER_CH0_IRQn        = IRQ_NUM_BASE + 36, /*!< Timer Channel 0 Interrupt                                         */
  TIMER_CH1_IRQn        = IRQ_NUM_BASE + 37, /*!< Timer Channel 1 Interrupt                                         */
  TIMER_WDT_IRQn        = IRQ_NUM_BASE + 38, /*!< Timer Watch Dog Interrupt                                         */
  KYS_IRQn              = IRQ_NUM_BASE + 39, /*!< KYS Interrupt                                                     */
  QDEC0_IRQn            = IRQ_NUM_BASE + 40, /*!< QDEC0 Interrupt                                                   */
  QDEC1_IRQn            = IRQ_NUM_BASE + 41, /*!< QDEC1 Interrupt                                                   */
  QDEC2_IRQn            = IRQ_NUM_BASE + 42, /*!< QDEC2 Interrupt                                                   */
  RESERVED6             = IRQ_NUM_BASE + 43, /*!< RESERVED Interrupt                                                */
  GPIO_INT0_IRQn        = IRQ_NUM_BASE + 44, /*!< GPIO_INT0 Interrupt                                               */
  TOUCH_IRQn            = IRQ_NUM_BASE + 45, /*!< TOUCH Interrupt                                                   */
  RESERVED7             = IRQ_NUM_BASE + 46, /*!< RESERVED Interrupt                                                */
  M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154_REQ Interrupt                                                */
  M154_IRQn             = IRQ_NUM_BASE + 48, /*!< M154 Interrupt                                                    */
  M154_AES_IRQn         = IRQ_NUM_BASE + 49, /*!< M154_AES Interrupt                                                */
  PDS_WAKEUP_IRQn       = IRQ_NUM_BASE + 50, /*!< PDS Wakeup Interrupt                                              */
  HBN_OUT0_IRQn         = IRQ_NUM_BASE + 51, /*!< Hibernate out 0 Interrupt                                         */
  HBN_OUT1_IRQn         = IRQ_NUM_BASE + 52, /*!< Hibernate out 1 Interrupt                                         */
  BOR_IRQn              = IRQ_NUM_BASE + 53, /*!< BOR Interrupt                                                     */
  WIFI_IRQn             = IRQ_NUM_BASE + 54, /*!< WIFI To CPU Interrupt                                             */
  BZ_PHY_IRQn           = IRQ_NUM_BASE + 55, /*!< BZ_PHY Interrupt                                                  */
  BLE_IRQn              = IRQ_NUM_BASE + 56, /*!< BLE Interrupt                                                     */
  MAC_TXRX_TIMER_IRQn   = IRQ_NUM_BASE + 57, /*!< mac_int_tx_rx_timer Interrupt                                     */
  MAC_TXRX_MISC_IRQn    = IRQ_NUM_BASE + 58, /*!< mac_int_tx_rx_misc Interrupt                                      */
  MAC_RX_TRG_IRQn       = IRQ_NUM_BASE + 59, /*!< mac_int_rx_trigger Interrupt                                      */
  MAC_TX_TRG_IRQn       = IRQ_NUM_BASE + 60, /*!< mac_int_tx_trigger Interrupt                                      */
  MAC_GEN_IRQn          = IRQ_NUM_BASE + 61, /*!< mac_int_gen Interrupt                                             */
  MAC_PORT_TRG_IRQn     = IRQ_NUM_BASE + 62, /*!< mac_int_port_trigger Interrupt                                    */
  WIFI_IPC_PUBLIC_IRQn  = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt                                         */
  IRQn_LAST,
} IRQn_Type;

/**
 * @brief BL702 Memory Map Definitions
 */
#define BL702_FLASH_XIP_BASE        0x23000000
#define BL702_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
#define BL702_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
#define BL702_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
#define BL702_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)

#define BL702_PSRAM_XIP_BASE        0x24000000
#define BL702_PSRAM_XIP_END         (0x24000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
#define BL702_PSRAM_XIP_REMAP0_END  (0x34000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
#define BL702_PSRAM_XIP_REMAP1_END  (0x44000000 + 16 * 1024 * 1024)
#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
#define BL702_PSRAM_XIP_REMAP2_END  (0x54000000 + 16 * 1024 * 1024)

#define BL702_WRAM_BASE        0x42020000
#define BL702_WRAM_END         (0x42020000 + 56 * 1024)
#define BL702_WRAM_REMAP0_BASE 0x22020000
#define BL702_WRAM_REMAP0_END  (0x22020000 + 56 * 1024)
#define BL702_WRAM_REMAP1_BASE 0x32020000
#define BL702_WRAM_REMAP1_END  (0x32020000 + 56 * 1024)
#define BL702_WRAM_REMAP2_BASE 0x52020000
#define BL702_WRAM_REMAP2_END  (0x52020000 + 56 * 1024)

#define BL702_TCM_BASE        0x22010000
#define BL702_TCM_END         (0x22010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP0_BASE 0x32010000
#define BL702_TCM_REMAP0_END  (0x32010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP1_BASE 0x42010000
#define BL702_TCM_REMAP1_END  (0x42010000 + (16 + 48) * 1024)
#define BL702_TCM_REMAP2_BASE 0x52010000
#define BL702_TCM_REMAP2_END  (0x52010000 + (16 + 48) * 1024)
/*@} end of group Memory_Map_Section */

/* BL702 peripherals base address */
#define GLB_BASE         ((uint32_t)0x40000000)
#define RF_BASE          ((uint32_t)0x40001000)
#define BZ_PHY_BASE      ((uint32_t)0x40001000)
#define BZ_PHY_AGC_BASE  ((uint32_t)0x40001000)
#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
#define EF_DATA_BASE     ((uint32_t)0x40007000)
#define EF_CTRL_BASE     ((uint32_t)0x40007000)
#define CCI_BASE         ((uint32_t)0x40008000)
#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
#define UART0_BASE       ((uint32_t)0x4000A000)
#define UART1_BASE       ((uint32_t)0x4000A100)
#define SPI_BASE         ((uint32_t)0x4000A200)
#define I2C_BASE         ((uint32_t)0x4000A300)
#define PWM_BASE         ((uint32_t)0x4000A400)
#define TIMER_BASE       ((uint32_t)0x4000A500)
#define IR_BASE          ((uint32_t)0x4000A600)
#define CKS_BASE         ((uint32_t)0x4000A700)
#define QDEC0_BASE       ((uint32_t)0x4000A800)
#define QDEC1_BASE       ((uint32_t)0x4000A840)
#define QDEC2_BASE       ((uint32_t)0x4000A880)
#define KYS_BASE         ((uint32_t)0x4000A900)
#define I2S_BASE         ((uint32_t)0x4000AA00)
#define CAM_BASE         ((uint32_t)0x4000AD00)
#define MJPEG_BASE       ((uint32_t)0x4000AE00)
#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
#define DMA_BASE         ((uint32_t)0x4000C000)
#define EMAC_BASE        ((uint32_t)0x4000D000)
#define USB_BASE         ((uint32_t)0x4000D800)
#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
#define MAC154_BASE      ((uint32_t)0x4C000000) /*!< MAC154 module base address */

#define HBN_RAM_BASE ((uint32_t)0x40010000)

typedef enum {
  BL_AHB_SLAVE1_GLB                = 0x00,
  BL_AHB_SLAVE1_MIX                = 0x01,
  BL_AHB_SLAVE1_GPIP               = 0x02,
  BL_AHB_SLAVE1_SEC_DBG            = 0x03,
  BL_AHB_SLAVE1_SEC                = 0x04,
  BL_AHB_SLAVE1_TZ1                = 0x05,
  BL_AHB_SLAVE1_TZ2                = 0x06,
  BL_AHB_SLAVE1_EFUSE              = 0x07,
  BL_AHB_SLAVE1_CCI                = 0x08,
  BL_AHB_SLAVE1_L1C                = 0x09,
  BL_AHB_SLAVE1_S1A_ALL            = 0x0A,
  BL_AHB_SLAVE1_SFC                = 0x0B,
  BL_AHB_SLAVE1_DMA                = 0x0C,
  BL_AHB_SLAVE1_EMAC               = 0x0D,
  BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
  BL_AHB_SLAVE1_RSVD0F             = 0x0F,
  BL_AHB_SLAVE1_UART0              = 0x10,
  BL_AHB_SLAVE1_UART1              = 0x11,
  BL_AHB_SLAVE1_SPI                = 0x12,
  BL_AHB_SLAVE1_I2C                = 0x13,
  BL_AHB_SLAVE1_PWM                = 0x14,
  BL_AHB_SLAVE1_TMR                = 0x15,
  BL_AHB_SLAVE1_IRR                = 0x16,
  BL_AHB_SLAVE1_CKS                = 0x17,
  BL_AHB_SLAVE1_QDEC               = 0x18,
  BL_AHB_SLAVE1_KYS                = 0x19,
  BL_AHB_SLAVE1_I2S                = 0x1A,
  BL_AHB_SLAVE1_RSVD1B             = 0x1B,
  BL_AHB_SLAVE1_USB                = 0x1C,
  BL_AHB_SLAVE1_CAM                = 0x1D,
  BL_AHB_SLAVE1_MJPEG              = 0x1E,
  BL_AHB_SLAVE1_MAX                = 0x1F,
} BL_AHB_Slave1_Type;

typedef enum {
  BL_AHB_SEC_ENG_AES0 = 0,
  BL_AHB_SEC_ENG_AES1,
  BL_AHB_SEC_ENG_SHA0,
  BL_AHB_SEC_ENG_SHA1,
} BL_AHB_Sec_Eng_Type;

typedef enum {
  BL_AHB_DMA0_CH0 = 0,
  BL_AHB_DMA0_CH1,
  BL_AHB_DMA0_CH2,
  BL_AHB_DMA0_CH3,
  BL_AHB_DMA0_CH4,
  BL_AHB_DMA0_CH5,
  BL_AHB_DMA0_CH6,
  BL_AHB_DMA0_CH7,
} BL_AHB_DMA0_CHNL_Type;

typedef enum {
  BL_AHB_SLAVE2_WIFI_CFG = 0,
  BL_AHB_SLAVE2_MAX,
} BL_AHB_Slave2_Type;

typedef enum {
  BL_AHB_SLAVE3_BLE = 0,
  BL_AHB_SLAVE3_MAX,
} BL_AHB_Slave3_Type;

typedef enum {
  BL_CORE_MASTER_IBUS_CPU = 0,
  BL_CORE_MASTER_DBUS_CPU,
  BL_CORE_MASTER_BUS_S2F,
  BL_CORE_MASTER_MAX,
} BL_Core_Master_Type;

typedef enum {
  BL_CORE_SLAVE0_DTCM_CPU = 0,
  BL_CORE_SLAVE0_MAX,
} BL_Core_Slave0_Type;

typedef enum {
  BL_CORE_SLAVE1_XIP_CPU = 0,
  BL_CORE_SLAVE1_ITCM_CPU,
  BL_CORE_SLAVE1_ROM,
  BL_CORE_SLAVE1_MAX,
} BL_Core_Slave1_Type;

typedef enum {
  BL_CORE_SLAVE2_F2S = 0,
  BL_CORE_SLAVE2_MAX,
} BL_Core_Slave2_Type;

/**
 * @}
 */
#include 
#include 

/**
 * @}
 */

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/bl70x_reg.svc
================================================


	
		
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
			
			
			
				
			
			
				
				
			
			
				
				
			
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
				
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
			
				
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
				
				
				
				
			
		
		
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
				
			
			
			
			
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
			
			
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
			
			
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
		
		
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
			
			
			
			
			
			
			
			
				
				
				
				
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
				
			
			
				
			
			
				
			
			
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
				
				
				
			
			
				
			
			
				
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
		
		
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
			
		
		
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
			
			
				
			
			
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
			
			
				
			
		
		
			
				
				
			
			
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
			
			
				
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
		
		
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
			
			
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
				
			
			
				
				
				
				
			
			
				
				
			
			
				
			
			
				
			
			
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
			
			
				
				
				
			
			
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
			
			
				
				
			
			
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
		
		
			
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
			
			
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
			
			
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
				
				
				
				
			
			
				
				
			
			
				
				
				
				
				
				
			
			
				
			
			
				
			
			
				
			
			
				
			
			
				
			
		
	


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cam_reg.h
================================================
/**
  ******************************************************************************
  * @file    cam_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __CAM_REG_H__
#define __CAM_REG_H__

#include "bl702.h"

/* 0x0 : dvp2axi_configue */
#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0)
#define CAM_REG_DVP_ENABLE          CAM_REG_DVP_ENABLE
#define CAM_REG_DVP_ENABLE_POS      (0U)
#define CAM_REG_DVP_ENABLE_LEN      (1U)
#define CAM_REG_DVP_ENABLE_MSK      (((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS)
#define CAM_REG_DVP_ENABLE_UMSK     (~(((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS))
#define CAM_REG_SW_MODE             CAM_REG_SW_MODE
#define CAM_REG_SW_MODE_POS         (1U)
#define CAM_REG_SW_MODE_LEN         (1U)
#define CAM_REG_SW_MODE_MSK         (((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS)
#define CAM_REG_SW_MODE_UMSK        (~(((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS))
#define CAM_REG_FRAM_VLD_POL        CAM_REG_FRAM_VLD_POL
#define CAM_REG_FRAM_VLD_POL_POS    (2U)
#define CAM_REG_FRAM_VLD_POL_LEN    (1U)
#define CAM_REG_FRAM_VLD_POL_MSK    (((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS)
#define CAM_REG_FRAM_VLD_POL_UMSK   (~(((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS))
#define CAM_REG_LINE_VLD_POL        CAM_REG_LINE_VLD_POL
#define CAM_REG_LINE_VLD_POL_POS    (3U)
#define CAM_REG_LINE_VLD_POL_LEN    (1U)
#define CAM_REG_LINE_VLD_POL_MSK    (((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS)
#define CAM_REG_LINE_VLD_POL_UMSK   (~(((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS))
#define CAM_REG_HBURST              CAM_REG_HBURST
#define CAM_REG_HBURST_POS          (4U)
#define CAM_REG_HBURST_LEN          (2U)
#define CAM_REG_HBURST_MSK          (((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS)
#define CAM_REG_HBURST_UMSK         (~(((1U << CAM_REG_HBURST_LEN) - 1) << CAM_REG_HBURST_POS))
#define CAM_REG_DVP_MODE            CAM_REG_DVP_MODE
#define CAM_REG_DVP_MODE_POS        (8U)
#define CAM_REG_DVP_MODE_LEN        (3U)
#define CAM_REG_DVP_MODE_MSK        (((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS)
#define CAM_REG_DVP_MODE_UMSK       (~(((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS))
#define CAM_REG_HW_MODE_FWRAP       CAM_REG_HW_MODE_FWRAP
#define CAM_REG_HW_MODE_FWRAP_POS   (11U)
#define CAM_REG_HW_MODE_FWRAP_LEN   (1U)
#define CAM_REG_HW_MODE_FWRAP_MSK   (((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS)
#define CAM_REG_HW_MODE_FWRAP_UMSK  (~(((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS))
#define CAM_REG_DROP_EN             CAM_REG_DROP_EN
#define CAM_REG_DROP_EN_POS         (12U)
#define CAM_REG_DROP_EN_LEN         (1U)
#define CAM_REG_DROP_EN_MSK         (((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS)
#define CAM_REG_DROP_EN_UMSK        (~(((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS))
#define CAM_REG_DROP_EVEN           CAM_REG_DROP_EVEN
#define CAM_REG_DROP_EVEN_POS       (13U)
#define CAM_REG_DROP_EVEN_LEN       (1U)
#define CAM_REG_DROP_EVEN_MSK       (((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS)
#define CAM_REG_DROP_EVEN_UMSK      (~(((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS))
#define CAM_REG_SUBSAMPLE_EN        CAM_REG_SUBSAMPLE_EN
#define CAM_REG_SUBSAMPLE_EN_POS    (14U)
#define CAM_REG_SUBSAMPLE_EN_LEN    (1U)
#define CAM_REG_SUBSAMPLE_EN_MSK    (((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS)
#define CAM_REG_SUBSAMPLE_EN_UMSK   (~(((1U << CAM_REG_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_SUBSAMPLE_EN_POS))
#define CAM_REG_SUBSAMPLE_EVEN      CAM_REG_SUBSAMPLE_EVEN
#define CAM_REG_SUBSAMPLE_EVEN_POS  (15U)
#define CAM_REG_SUBSAMPLE_EVEN_LEN  (1U)
#define CAM_REG_SUBSAMPLE_EVEN_MSK  (((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS)
#define CAM_REG_SUBSAMPLE_EVEN_UMSK (~(((1U << CAM_REG_SUBSAMPLE_EVEN_LEN) - 1) << CAM_REG_SUBSAMPLE_EVEN_POS))
#define CAM_REG_INTERLV_MODE        CAM_REG_INTERLV_MODE
#define CAM_REG_INTERLV_MODE_POS    (16U)
#define CAM_REG_INTERLV_MODE_LEN    (1U)
#define CAM_REG_INTERLV_MODE_MSK    (((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS)
#define CAM_REG_INTERLV_MODE_UMSK   (~(((1U << CAM_REG_INTERLV_MODE_LEN) - 1) << CAM_REG_INTERLV_MODE_POS))
#define CAM_REG_DVP_PIX_CLK_CG      CAM_REG_DVP_PIX_CLK_CG
#define CAM_REG_DVP_PIX_CLK_CG_POS  (20U)
#define CAM_REG_DVP_PIX_CLK_CG_LEN  (1U)
#define CAM_REG_DVP_PIX_CLK_CG_MSK  (((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS)
#define CAM_REG_DVP_PIX_CLK_CG_UMSK (~(((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS))
#define CAM_REG_DVP_WAIT_CYCLE      CAM_REG_DVP_WAIT_CYCLE
#define CAM_REG_DVP_WAIT_CYCLE_POS  (24U)
#define CAM_REG_DVP_WAIT_CYCLE_LEN  (8U)
#define CAM_REG_DVP_WAIT_CYCLE_MSK  (((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS)
#define CAM_REG_DVP_WAIT_CYCLE_UMSK (~(((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS))

/* 0x4 : dvp2ahb_addr_start_0 */
#define CAM_DVP2AHB_ADDR_START_0_OFFSET (0x4)
#define CAM_REG_ADDR_START_0            CAM_REG_ADDR_START_0
#define CAM_REG_ADDR_START_0_POS        (0U)
#define CAM_REG_ADDR_START_0_LEN        (32U)
#define CAM_REG_ADDR_START_0_MSK        (((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS)
#define CAM_REG_ADDR_START_0_UMSK       (~(((1U << CAM_REG_ADDR_START_0_LEN) - 1) << CAM_REG_ADDR_START_0_POS))

/* 0x8 : dvp2ahb_mem_bcnt_0 */
#define CAM_DVP2AHB_MEM_BCNT_0_OFFSET (0x8)
#define CAM_REG_MEM_BURST_CNT_0       CAM_REG_MEM_BURST_CNT_0
#define CAM_REG_MEM_BURST_CNT_0_POS   (0U)
#define CAM_REG_MEM_BURST_CNT_0_LEN   (32U)
#define CAM_REG_MEM_BURST_CNT_0_MSK   (((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS)
#define CAM_REG_MEM_BURST_CNT_0_UMSK  (~(((1U << CAM_REG_MEM_BURST_CNT_0_LEN) - 1) << CAM_REG_MEM_BURST_CNT_0_POS))

/* 0xC : dvp2ahb_frame_bcnt_0 */
#define CAM_DVP2AHB_FRAME_BCNT_0_OFFSET (0xC)
#define CAM_REG_FRAME_BURST_CNT_0       CAM_REG_FRAME_BURST_CNT_0
#define CAM_REG_FRAME_BURST_CNT_0_POS   (0U)
#define CAM_REG_FRAME_BURST_CNT_0_LEN   (32U)
#define CAM_REG_FRAME_BURST_CNT_0_MSK   (((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS)
#define CAM_REG_FRAME_BURST_CNT_0_UMSK  (~(((1U << CAM_REG_FRAME_BURST_CNT_0_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_0_POS))

/* 0x10 : dvp2ahb_addr_start_1 */
#define CAM_DVP2AHB_ADDR_START_1_OFFSET (0x10)
#define CAM_REG_ADDR_START_1            CAM_REG_ADDR_START_1
#define CAM_REG_ADDR_START_1_POS        (0U)
#define CAM_REG_ADDR_START_1_LEN        (32U)
#define CAM_REG_ADDR_START_1_MSK        (((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS)
#define CAM_REG_ADDR_START_1_UMSK       (~(((1U << CAM_REG_ADDR_START_1_LEN) - 1) << CAM_REG_ADDR_START_1_POS))

/* 0x14 : dvp2ahb_mem_bcnt_1 */
#define CAM_DVP2AHB_MEM_BCNT_1_OFFSET (0x14)
#define CAM_REG_MEM_BURST_CNT_1       CAM_REG_MEM_BURST_CNT_1
#define CAM_REG_MEM_BURST_CNT_1_POS   (0U)
#define CAM_REG_MEM_BURST_CNT_1_LEN   (32U)
#define CAM_REG_MEM_BURST_CNT_1_MSK   (((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS)
#define CAM_REG_MEM_BURST_CNT_1_UMSK  (~(((1U << CAM_REG_MEM_BURST_CNT_1_LEN) - 1) << CAM_REG_MEM_BURST_CNT_1_POS))

/* 0x18 : dvp2ahb_frame_bcnt_1 */
#define CAM_DVP2AHB_FRAME_BCNT_1_OFFSET (0x18)
#define CAM_REG_FRAME_BURST_CNT_1       CAM_REG_FRAME_BURST_CNT_1
#define CAM_REG_FRAME_BURST_CNT_1_POS   (0U)
#define CAM_REG_FRAME_BURST_CNT_1_LEN   (32U)
#define CAM_REG_FRAME_BURST_CNT_1_MSK   (((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS)
#define CAM_REG_FRAME_BURST_CNT_1_UMSK  (~(((1U << CAM_REG_FRAME_BURST_CNT_1_LEN) - 1) << CAM_REG_FRAME_BURST_CNT_1_POS))

/* 0x1C : dvp_status_and_error */
#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)
#define CAM_STS_NORMAL_INT_0            CAM_STS_NORMAL_INT_0
#define CAM_STS_NORMAL_INT_0_POS        (0U)
#define CAM_STS_NORMAL_INT_0_LEN        (1U)
#define CAM_STS_NORMAL_INT_0_MSK        (((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS)
#define CAM_STS_NORMAL_INT_0_UMSK       (~(((1U << CAM_STS_NORMAL_INT_0_LEN) - 1) << CAM_STS_NORMAL_INT_0_POS))
#define CAM_STS_NORMAL_INT_1            CAM_STS_NORMAL_INT_1
#define CAM_STS_NORMAL_INT_1_POS        (1U)
#define CAM_STS_NORMAL_INT_1_LEN        (1U)
#define CAM_STS_NORMAL_INT_1_MSK        (((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS)
#define CAM_STS_NORMAL_INT_1_UMSK       (~(((1U << CAM_STS_NORMAL_INT_1_LEN) - 1) << CAM_STS_NORMAL_INT_1_POS))
#define CAM_STS_MEM_INT_0               CAM_STS_MEM_INT_0
#define CAM_STS_MEM_INT_0_POS           (2U)
#define CAM_STS_MEM_INT_0_LEN           (1U)
#define CAM_STS_MEM_INT_0_MSK           (((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS)
#define CAM_STS_MEM_INT_0_UMSK          (~(((1U << CAM_STS_MEM_INT_0_LEN) - 1) << CAM_STS_MEM_INT_0_POS))
#define CAM_STS_MEM_INT_1               CAM_STS_MEM_INT_1
#define CAM_STS_MEM_INT_1_POS           (3U)
#define CAM_STS_MEM_INT_1_LEN           (1U)
#define CAM_STS_MEM_INT_1_MSK           (((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS)
#define CAM_STS_MEM_INT_1_UMSK          (~(((1U << CAM_STS_MEM_INT_1_LEN) - 1) << CAM_STS_MEM_INT_1_POS))
#define CAM_STS_FRAME_INT_0             CAM_STS_FRAME_INT_0
#define CAM_STS_FRAME_INT_0_POS         (4U)
#define CAM_STS_FRAME_INT_0_LEN         (1U)
#define CAM_STS_FRAME_INT_0_MSK         (((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS)
#define CAM_STS_FRAME_INT_0_UMSK        (~(((1U << CAM_STS_FRAME_INT_0_LEN) - 1) << CAM_STS_FRAME_INT_0_POS))
#define CAM_STS_FRAME_INT_1             CAM_STS_FRAME_INT_1
#define CAM_STS_FRAME_INT_1_POS         (5U)
#define CAM_STS_FRAME_INT_1_LEN         (1U)
#define CAM_STS_FRAME_INT_1_MSK         (((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS)
#define CAM_STS_FRAME_INT_1_UMSK        (~(((1U << CAM_STS_FRAME_INT_1_LEN) - 1) << CAM_STS_FRAME_INT_1_POS))
#define CAM_STS_FIFO_INT_0              CAM_STS_FIFO_INT_0
#define CAM_STS_FIFO_INT_0_POS          (6U)
#define CAM_STS_FIFO_INT_0_LEN          (1U)
#define CAM_STS_FIFO_INT_0_MSK          (((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS)
#define CAM_STS_FIFO_INT_0_UMSK         (~(((1U << CAM_STS_FIFO_INT_0_LEN) - 1) << CAM_STS_FIFO_INT_0_POS))
#define CAM_STS_FIFO_INT_1              CAM_STS_FIFO_INT_1
#define CAM_STS_FIFO_INT_1_POS          (7U)
#define CAM_STS_FIFO_INT_1_LEN          (1U)
#define CAM_STS_FIFO_INT_1_MSK          (((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS)
#define CAM_STS_FIFO_INT_1_UMSK         (~(((1U << CAM_STS_FIFO_INT_1_LEN) - 1) << CAM_STS_FIFO_INT_1_POS))
#define CAM_STS_HCNT_INT                CAM_STS_HCNT_INT
#define CAM_STS_HCNT_INT_POS            (8U)
#define CAM_STS_HCNT_INT_LEN            (1U)
#define CAM_STS_HCNT_INT_MSK            (((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS)
#define CAM_STS_HCNT_INT_UMSK           (~(((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS))
#define CAM_STS_VCNT_INT                CAM_STS_VCNT_INT
#define CAM_STS_VCNT_INT_POS            (9U)
#define CAM_STS_VCNT_INT_LEN            (1U)
#define CAM_STS_VCNT_INT_MSK            (((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS)
#define CAM_STS_VCNT_INT_UMSK           (~(((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS))
#define CAM_AHB_IDLE_0                  CAM_AHB_IDLE_0
#define CAM_AHB_IDLE_0_POS              (16U)
#define CAM_AHB_IDLE_0_LEN              (1U)
#define CAM_AHB_IDLE_0_MSK              (((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS)
#define CAM_AHB_IDLE_0_UMSK             (~(((1U << CAM_AHB_IDLE_0_LEN) - 1) << CAM_AHB_IDLE_0_POS))
#define CAM_AHB_IDLE_1                  CAM_AHB_IDLE_1
#define CAM_AHB_IDLE_1_POS              (17U)
#define CAM_AHB_IDLE_1_LEN              (1U)
#define CAM_AHB_IDLE_1_MSK              (((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS)
#define CAM_AHB_IDLE_1_UMSK             (~(((1U << CAM_AHB_IDLE_1_LEN) - 1) << CAM_AHB_IDLE_1_POS))
#define CAM_ST_DVP_IDLE                 CAM_ST_DVP_IDLE
#define CAM_ST_DVP_IDLE_POS             (19U)
#define CAM_ST_DVP_IDLE_LEN             (1U)
#define CAM_ST_DVP_IDLE_MSK             (((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS)
#define CAM_ST_DVP_IDLE_UMSK            (~(((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS))
#define CAM_FRAME_VALID_CNT_0           CAM_FRAME_VALID_CNT_0
#define CAM_FRAME_VALID_CNT_0_POS       (20U)
#define CAM_FRAME_VALID_CNT_0_LEN       (4U)
#define CAM_FRAME_VALID_CNT_0_MSK       (((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS)
#define CAM_FRAME_VALID_CNT_0_UMSK      (~(((1U << CAM_FRAME_VALID_CNT_0_LEN) - 1) << CAM_FRAME_VALID_CNT_0_POS))
#define CAM_FRAME_VALID_CNT_1           CAM_FRAME_VALID_CNT_1
#define CAM_FRAME_VALID_CNT_1_POS       (24U)
#define CAM_FRAME_VALID_CNT_1_LEN       (4U)
#define CAM_FRAME_VALID_CNT_1_MSK       (((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS)
#define CAM_FRAME_VALID_CNT_1_UMSK      (~(((1U << CAM_FRAME_VALID_CNT_1_LEN) - 1) << CAM_FRAME_VALID_CNT_1_POS))
#define CAM_ST_BUS_IDLE                 CAM_ST_BUS_IDLE
#define CAM_ST_BUS_IDLE_POS             (28U)
#define CAM_ST_BUS_IDLE_LEN             (1U)
#define CAM_ST_BUS_IDLE_MSK             (((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS)
#define CAM_ST_BUS_IDLE_UMSK            (~(((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS))
#define CAM_ST_BUS_FUNC                 CAM_ST_BUS_FUNC
#define CAM_ST_BUS_FUNC_POS             (29U)
#define CAM_ST_BUS_FUNC_LEN             (1U)
#define CAM_ST_BUS_FUNC_MSK             (((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS)
#define CAM_ST_BUS_FUNC_UMSK            (~(((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS))
#define CAM_ST_BUS_WAIT                 CAM_ST_BUS_WAIT
#define CAM_ST_BUS_WAIT_POS             (30U)
#define CAM_ST_BUS_WAIT_LEN             (1U)
#define CAM_ST_BUS_WAIT_MSK             (((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS)
#define CAM_ST_BUS_WAIT_UMSK            (~(((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS))
#define CAM_ST_BUS_FLSH                 CAM_ST_BUS_FLSH
#define CAM_ST_BUS_FLSH_POS             (31U)
#define CAM_ST_BUS_FLSH_LEN             (1U)
#define CAM_ST_BUS_FLSH_MSK             (((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS)
#define CAM_ST_BUS_FLSH_UMSK            (~(((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS))

/* 0x20 : dvp_frame_fifo_pop */
#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20)
#define CAM_RFIFO_POP_0               CAM_RFIFO_POP_0
#define CAM_RFIFO_POP_0_POS           (0U)
#define CAM_RFIFO_POP_0_LEN           (1U)
#define CAM_RFIFO_POP_0_MSK           (((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS)
#define CAM_RFIFO_POP_0_UMSK          (~(((1U << CAM_RFIFO_POP_0_LEN) - 1) << CAM_RFIFO_POP_0_POS))
#define CAM_RFIFO_POP_1               CAM_RFIFO_POP_1
#define CAM_RFIFO_POP_1_POS           (1U)
#define CAM_RFIFO_POP_1_LEN           (1U)
#define CAM_RFIFO_POP_1_MSK           (((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS)
#define CAM_RFIFO_POP_1_UMSK          (~(((1U << CAM_RFIFO_POP_1_LEN) - 1) << CAM_RFIFO_POP_1_POS))
#define CAM_REG_INT_NORMAL_CLR_0      CAM_REG_INT_NORMAL_CLR_0
#define CAM_REG_INT_NORMAL_CLR_0_POS  (4U)
#define CAM_REG_INT_NORMAL_CLR_0_LEN  (1U)
#define CAM_REG_INT_NORMAL_CLR_0_MSK  (((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS)
#define CAM_REG_INT_NORMAL_CLR_0_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_0_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_0_POS))
#define CAM_REG_INT_MEM_CLR_0         CAM_REG_INT_MEM_CLR_0
#define CAM_REG_INT_MEM_CLR_0_POS     (5U)
#define CAM_REG_INT_MEM_CLR_0_LEN     (1U)
#define CAM_REG_INT_MEM_CLR_0_MSK     (((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS)
#define CAM_REG_INT_MEM_CLR_0_UMSK    (~(((1U << CAM_REG_INT_MEM_CLR_0_LEN) - 1) << CAM_REG_INT_MEM_CLR_0_POS))
#define CAM_REG_INT_FRAME_CLR_0       CAM_REG_INT_FRAME_CLR_0
#define CAM_REG_INT_FRAME_CLR_0_POS   (6U)
#define CAM_REG_INT_FRAME_CLR_0_LEN   (1U)
#define CAM_REG_INT_FRAME_CLR_0_MSK   (((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS)
#define CAM_REG_INT_FRAME_CLR_0_UMSK  (~(((1U << CAM_REG_INT_FRAME_CLR_0_LEN) - 1) << CAM_REG_INT_FRAME_CLR_0_POS))
#define CAM_REG_INT_FIFO_CLR_0        CAM_REG_INT_FIFO_CLR_0
#define CAM_REG_INT_FIFO_CLR_0_POS    (7U)
#define CAM_REG_INT_FIFO_CLR_0_LEN    (1U)
#define CAM_REG_INT_FIFO_CLR_0_MSK    (((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS)
#define CAM_REG_INT_FIFO_CLR_0_UMSK   (~(((1U << CAM_REG_INT_FIFO_CLR_0_LEN) - 1) << CAM_REG_INT_FIFO_CLR_0_POS))
#define CAM_REG_INT_HCNT_CLR_0        CAM_REG_INT_HCNT_CLR_0
#define CAM_REG_INT_HCNT_CLR_0_POS    (8U)
#define CAM_REG_INT_HCNT_CLR_0_LEN    (1U)
#define CAM_REG_INT_HCNT_CLR_0_MSK    (((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS)
#define CAM_REG_INT_HCNT_CLR_0_UMSK   (~(((1U << CAM_REG_INT_HCNT_CLR_0_LEN) - 1) << CAM_REG_INT_HCNT_CLR_0_POS))
#define CAM_REG_INT_VCNT_CLR_0        CAM_REG_INT_VCNT_CLR_0
#define CAM_REG_INT_VCNT_CLR_0_POS    (9U)
#define CAM_REG_INT_VCNT_CLR_0_LEN    (1U)
#define CAM_REG_INT_VCNT_CLR_0_MSK    (((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS)
#define CAM_REG_INT_VCNT_CLR_0_UMSK   (~(((1U << CAM_REG_INT_VCNT_CLR_0_LEN) - 1) << CAM_REG_INT_VCNT_CLR_0_POS))
#define CAM_REG_INT_NORMAL_CLR_1      CAM_REG_INT_NORMAL_CLR_1
#define CAM_REG_INT_NORMAL_CLR_1_POS  (16U)
#define CAM_REG_INT_NORMAL_CLR_1_LEN  (1U)
#define CAM_REG_INT_NORMAL_CLR_1_MSK  (((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS)
#define CAM_REG_INT_NORMAL_CLR_1_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_1_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_1_POS))
#define CAM_REG_INT_MEM_CLR_1         CAM_REG_INT_MEM_CLR_1
#define CAM_REG_INT_MEM_CLR_1_POS     (17U)
#define CAM_REG_INT_MEM_CLR_1_LEN     (1U)
#define CAM_REG_INT_MEM_CLR_1_MSK     (((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS)
#define CAM_REG_INT_MEM_CLR_1_UMSK    (~(((1U << CAM_REG_INT_MEM_CLR_1_LEN) - 1) << CAM_REG_INT_MEM_CLR_1_POS))
#define CAM_REG_INT_FRAME_CLR_1       CAM_REG_INT_FRAME_CLR_1
#define CAM_REG_INT_FRAME_CLR_1_POS   (18U)
#define CAM_REG_INT_FRAME_CLR_1_LEN   (1U)
#define CAM_REG_INT_FRAME_CLR_1_MSK   (((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS)
#define CAM_REG_INT_FRAME_CLR_1_UMSK  (~(((1U << CAM_REG_INT_FRAME_CLR_1_LEN) - 1) << CAM_REG_INT_FRAME_CLR_1_POS))
#define CAM_REG_INT_FIFO_CLR_1        CAM_REG_INT_FIFO_CLR_1
#define CAM_REG_INT_FIFO_CLR_1_POS    (19U)
#define CAM_REG_INT_FIFO_CLR_1_LEN    (1U)
#define CAM_REG_INT_FIFO_CLR_1_MSK    (((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS)
#define CAM_REG_INT_FIFO_CLR_1_UMSK   (~(((1U << CAM_REG_INT_FIFO_CLR_1_LEN) - 1) << CAM_REG_INT_FIFO_CLR_1_POS))

/* 0x24 : snsr_control */
#define CAM_SNSR_CONTROL_OFFSET (0x24)
#define CAM_REG_CAM_RST         CAM_REG_CAM_RST
#define CAM_REG_CAM_RST_POS     (0U)
#define CAM_REG_CAM_RST_LEN     (1U)
#define CAM_REG_CAM_RST_MSK     (((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS)
#define CAM_REG_CAM_RST_UMSK    (~(((1U << CAM_REG_CAM_RST_LEN) - 1) << CAM_REG_CAM_RST_POS))
#define CAM_REG_CAM_PWDN        CAM_REG_CAM_PWDN
#define CAM_REG_CAM_PWDN_POS    (1U)
#define CAM_REG_CAM_PWDN_LEN    (1U)
#define CAM_REG_CAM_PWDN_MSK    (((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS)
#define CAM_REG_CAM_PWDN_UMSK   (~(((1U << CAM_REG_CAM_PWDN_LEN) - 1) << CAM_REG_CAM_PWDN_POS))

/* 0x28 : int_control */
#define CAM_INT_CONTROL_OFFSET          (0x28)
#define CAM_REG_INT_NORMAL_0_EN         CAM_REG_INT_NORMAL_0_EN
#define CAM_REG_INT_NORMAL_0_EN_POS     (0U)
#define CAM_REG_INT_NORMAL_0_EN_LEN     (1U)
#define CAM_REG_INT_NORMAL_0_EN_MSK     (((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS)
#define CAM_REG_INT_NORMAL_0_EN_UMSK    (~(((1U << CAM_REG_INT_NORMAL_0_EN_LEN) - 1) << CAM_REG_INT_NORMAL_0_EN_POS))
#define CAM_REG_INT_NORMAL_1_EN         CAM_REG_INT_NORMAL_1_EN
#define CAM_REG_INT_NORMAL_1_EN_POS     (1U)
#define CAM_REG_INT_NORMAL_1_EN_LEN     (1U)
#define CAM_REG_INT_NORMAL_1_EN_MSK     (((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS)
#define CAM_REG_INT_NORMAL_1_EN_UMSK    (~(((1U << CAM_REG_INT_NORMAL_1_EN_LEN) - 1) << CAM_REG_INT_NORMAL_1_EN_POS))
#define CAM_REG_INT_MEM_EN              CAM_REG_INT_MEM_EN
#define CAM_REG_INT_MEM_EN_POS          (2U)
#define CAM_REG_INT_MEM_EN_LEN          (1U)
#define CAM_REG_INT_MEM_EN_MSK          (((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS)
#define CAM_REG_INT_MEM_EN_UMSK         (~(((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS))
#define CAM_REG_INT_FRAME_EN            CAM_REG_INT_FRAME_EN
#define CAM_REG_INT_FRAME_EN_POS        (3U)
#define CAM_REG_INT_FRAME_EN_LEN        (1U)
#define CAM_REG_INT_FRAME_EN_MSK        (((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS)
#define CAM_REG_INT_FRAME_EN_UMSK       (~(((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS))
#define CAM_REG_INT_FIFO_EN             CAM_REG_INT_FIFO_EN
#define CAM_REG_INT_FIFO_EN_POS         (4U)
#define CAM_REG_INT_FIFO_EN_LEN         (1U)
#define CAM_REG_INT_FIFO_EN_MSK         (((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS)
#define CAM_REG_INT_FIFO_EN_UMSK        (~(((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS))
#define CAM_REG_INT_HCNT_EN             CAM_REG_INT_HCNT_EN
#define CAM_REG_INT_HCNT_EN_POS         (5U)
#define CAM_REG_INT_HCNT_EN_LEN         (1U)
#define CAM_REG_INT_HCNT_EN_MSK         (((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS)
#define CAM_REG_INT_HCNT_EN_UMSK        (~(((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS))
#define CAM_REG_INT_VCNT_EN             CAM_REG_INT_VCNT_EN
#define CAM_REG_INT_VCNT_EN_POS         (6U)
#define CAM_REG_INT_VCNT_EN_LEN         (1U)
#define CAM_REG_INT_VCNT_EN_MSK         (((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS)
#define CAM_REG_INT_VCNT_EN_UMSK        (~(((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS))
#define CAM_REG_FRAME_CNT_TRGR_INT      CAM_REG_FRAME_CNT_TRGR_INT
#define CAM_REG_FRAME_CNT_TRGR_INT_POS  (28U)
#define CAM_REG_FRAME_CNT_TRGR_INT_LEN  (4U)
#define CAM_REG_FRAME_CNT_TRGR_INT_MSK  (((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS)
#define CAM_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS))

/* 0x30 : hsync_control */
#define CAM_HSYNC_CONTROL_OFFSET     (0x30)
#define CAM_REG_HSYNC_ACT_END        CAM_REG_HSYNC_ACT_END
#define CAM_REG_HSYNC_ACT_END_POS    (0U)
#define CAM_REG_HSYNC_ACT_END_LEN    (16U)
#define CAM_REG_HSYNC_ACT_END_MSK    (((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS)
#define CAM_REG_HSYNC_ACT_END_UMSK   (~(((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS))
#define CAM_REG_HSYNC_ACT_START      CAM_REG_HSYNC_ACT_START
#define CAM_REG_HSYNC_ACT_START_POS  (16U)
#define CAM_REG_HSYNC_ACT_START_LEN  (16U)
#define CAM_REG_HSYNC_ACT_START_MSK  (((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS)
#define CAM_REG_HSYNC_ACT_START_UMSK (~(((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS))

/* 0x34 : vsync_control */
#define CAM_VSYNC_CONTROL_OFFSET     (0x34)
#define CAM_REG_VSYNC_ACT_END        CAM_REG_VSYNC_ACT_END
#define CAM_REG_VSYNC_ACT_END_POS    (0U)
#define CAM_REG_VSYNC_ACT_END_LEN    (16U)
#define CAM_REG_VSYNC_ACT_END_MSK    (((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS)
#define CAM_REG_VSYNC_ACT_END_UMSK   (~(((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS))
#define CAM_REG_VSYNC_ACT_START      CAM_REG_VSYNC_ACT_START
#define CAM_REG_VSYNC_ACT_START_POS  (16U)
#define CAM_REG_VSYNC_ACT_START_LEN  (16U)
#define CAM_REG_VSYNC_ACT_START_MSK  (((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS)
#define CAM_REG_VSYNC_ACT_START_UMSK (~(((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS))

/* 0x38 : frame_size_control */
#define CAM_FRAME_SIZE_CONTROL_OFFSET (0x38)
#define CAM_REG_TOTAL_HCNT            CAM_REG_TOTAL_HCNT
#define CAM_REG_TOTAL_HCNT_POS        (0U)
#define CAM_REG_TOTAL_HCNT_LEN        (16U)
#define CAM_REG_TOTAL_HCNT_MSK        (((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS)
#define CAM_REG_TOTAL_HCNT_UMSK       (~(((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS))
#define CAM_REG_TOTAL_VCNT            CAM_REG_TOTAL_VCNT
#define CAM_REG_TOTAL_VCNT_POS        (16U)
#define CAM_REG_TOTAL_VCNT_LEN        (16U)
#define CAM_REG_TOTAL_VCNT_MSK        (((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS)
#define CAM_REG_TOTAL_VCNT_UMSK       (~(((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS))

/* 0x40 : frame_start_addr0_0 */
#define CAM_FRAME_START_ADDR0_0_OFFSET (0x40)
#define CAM_FRAME_START_ADDR_0_0       CAM_FRAME_START_ADDR_0_0
#define CAM_FRAME_START_ADDR_0_0_POS   (0U)
#define CAM_FRAME_START_ADDR_0_0_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_0_MSK   (((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS)
#define CAM_FRAME_START_ADDR_0_0_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_0_POS))

/* 0x44 : frame_byte_cnt0_0 */
#define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44)
#define CAM_FRAME_BYTE_CNT_0_0       CAM_FRAME_BYTE_CNT_0_0
#define CAM_FRAME_BYTE_CNT_0_0_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_0_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_0_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS)
#define CAM_FRAME_BYTE_CNT_0_0_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_0_POS))

/* 0x48 : frame_start_addr0_1 */
#define CAM_FRAME_START_ADDR0_1_OFFSET (0x48)
#define CAM_FRAME_START_ADDR_0_1       CAM_FRAME_START_ADDR_0_1
#define CAM_FRAME_START_ADDR_0_1_POS   (0U)
#define CAM_FRAME_START_ADDR_0_1_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_1_MSK   (((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS)
#define CAM_FRAME_START_ADDR_0_1_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_1_LEN) - 1) << CAM_FRAME_START_ADDR_0_1_POS))

/* 0x4C : frame_byte_cnt0_1 */
#define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C)
#define CAM_FRAME_BYTE_CNT_0_1       CAM_FRAME_BYTE_CNT_0_1
#define CAM_FRAME_BYTE_CNT_0_1_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_1_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_1_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS)
#define CAM_FRAME_BYTE_CNT_0_1_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_1_POS))

/* 0x50 : frame_start_addr0_2 */
#define CAM_FRAME_START_ADDR0_2_OFFSET (0x50)
#define CAM_FRAME_START_ADDR_0_2       CAM_FRAME_START_ADDR_0_2
#define CAM_FRAME_START_ADDR_0_2_POS   (0U)
#define CAM_FRAME_START_ADDR_0_2_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_2_MSK   (((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS)
#define CAM_FRAME_START_ADDR_0_2_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_2_LEN) - 1) << CAM_FRAME_START_ADDR_0_2_POS))

/* 0x54 : frame_byte_cnt0_2 */
#define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54)
#define CAM_FRAME_BYTE_CNT_0_2       CAM_FRAME_BYTE_CNT_0_2
#define CAM_FRAME_BYTE_CNT_0_2_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_2_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_2_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS)
#define CAM_FRAME_BYTE_CNT_0_2_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_2_POS))

/* 0x58 : frame_start_addr0_3 */
#define CAM_FRAME_START_ADDR0_3_OFFSET (0x58)
#define CAM_FRAME_START_ADDR_0_3       CAM_FRAME_START_ADDR_0_3
#define CAM_FRAME_START_ADDR_0_3_POS   (0U)
#define CAM_FRAME_START_ADDR_0_3_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_3_MSK   (((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS)
#define CAM_FRAME_START_ADDR_0_3_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_3_LEN) - 1) << CAM_FRAME_START_ADDR_0_3_POS))

/* 0x5C : frame_byte_cnt0_3 */
#define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C)
#define CAM_FRAME_BYTE_CNT_0_3       CAM_FRAME_BYTE_CNT_0_3
#define CAM_FRAME_BYTE_CNT_0_3_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_3_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_3_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS)
#define CAM_FRAME_BYTE_CNT_0_3_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_3_POS))

/* 0x60 : frame_start_addr0_4 */
#define CAM_FRAME_START_ADDR0_4_OFFSET (0x60)
#define CAM_FRAME_START_ADDR_0_4       CAM_FRAME_START_ADDR_0_4
#define CAM_FRAME_START_ADDR_0_4_POS   (0U)
#define CAM_FRAME_START_ADDR_0_4_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_4_MSK   (((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS)
#define CAM_FRAME_START_ADDR_0_4_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_4_LEN) - 1) << CAM_FRAME_START_ADDR_0_4_POS))

/* 0x64 : frame_byte_cnt0_4 */
#define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64)
#define CAM_FRAME_BYTE_CNT_0_4       CAM_FRAME_BYTE_CNT_0_4
#define CAM_FRAME_BYTE_CNT_0_4_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_4_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_4_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS)
#define CAM_FRAME_BYTE_CNT_0_4_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_4_POS))

/* 0x68 : frame_start_addr0_5 */
#define CAM_FRAME_START_ADDR0_5_OFFSET (0x68)
#define CAM_FRAME_START_ADDR_0_5       CAM_FRAME_START_ADDR_0_5
#define CAM_FRAME_START_ADDR_0_5_POS   (0U)
#define CAM_FRAME_START_ADDR_0_5_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_5_MSK   (((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS)
#define CAM_FRAME_START_ADDR_0_5_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_5_LEN) - 1) << CAM_FRAME_START_ADDR_0_5_POS))

/* 0x6C : frame_byte_cnt0_5 */
#define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C)
#define CAM_FRAME_BYTE_CNT_0_5       CAM_FRAME_BYTE_CNT_0_5
#define CAM_FRAME_BYTE_CNT_0_5_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_5_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_5_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS)
#define CAM_FRAME_BYTE_CNT_0_5_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_5_POS))

/* 0x70 : frame_start_addr0_6 */
#define CAM_FRAME_START_ADDR0_6_OFFSET (0x70)
#define CAM_FRAME_START_ADDR_0_6       CAM_FRAME_START_ADDR_0_6
#define CAM_FRAME_START_ADDR_0_6_POS   (0U)
#define CAM_FRAME_START_ADDR_0_6_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_6_MSK   (((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS)
#define CAM_FRAME_START_ADDR_0_6_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_6_LEN) - 1) << CAM_FRAME_START_ADDR_0_6_POS))

/* 0x74 : frame_byte_cnt0_6 */
#define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74)
#define CAM_FRAME_BYTE_CNT_0_6       CAM_FRAME_BYTE_CNT_0_6
#define CAM_FRAME_BYTE_CNT_0_6_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_6_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_6_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS)
#define CAM_FRAME_BYTE_CNT_0_6_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_6_POS))

/* 0x78 : frame_start_addr0_7 */
#define CAM_FRAME_START_ADDR0_7_OFFSET (0x78)
#define CAM_FRAME_START_ADDR_0_7       CAM_FRAME_START_ADDR_0_7
#define CAM_FRAME_START_ADDR_0_7_POS   (0U)
#define CAM_FRAME_START_ADDR_0_7_LEN   (32U)
#define CAM_FRAME_START_ADDR_0_7_MSK   (((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS)
#define CAM_FRAME_START_ADDR_0_7_UMSK  (~(((1U << CAM_FRAME_START_ADDR_0_7_LEN) - 1) << CAM_FRAME_START_ADDR_0_7_POS))

/* 0x7C : frame_byte_cnt0_7 */
#define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C)
#define CAM_FRAME_BYTE_CNT_0_7       CAM_FRAME_BYTE_CNT_0_7
#define CAM_FRAME_BYTE_CNT_0_7_POS   (0U)
#define CAM_FRAME_BYTE_CNT_0_7_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_0_7_MSK   (((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS)
#define CAM_FRAME_BYTE_CNT_0_7_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_0_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_0_7_POS))

/* 0x80 : frame_start_addr1_0 */
#define CAM_FRAME_START_ADDR1_0_OFFSET (0x80)
#define CAM_FRAME_START_ADDR_1_0       CAM_FRAME_START_ADDR_1_0
#define CAM_FRAME_START_ADDR_1_0_POS   (0U)
#define CAM_FRAME_START_ADDR_1_0_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_0_MSK   (((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS)
#define CAM_FRAME_START_ADDR_1_0_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_0_LEN) - 1) << CAM_FRAME_START_ADDR_1_0_POS))

/* 0x84 : frame_byte_cnt1_0 */
#define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84)
#define CAM_FRAME_BYTE_CNT_1_0       CAM_FRAME_BYTE_CNT_1_0
#define CAM_FRAME_BYTE_CNT_1_0_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_0_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_0_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS)
#define CAM_FRAME_BYTE_CNT_1_0_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_0_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_0_POS))

/* 0x88 : frame_start_addr1_1 */
#define CAM_FRAME_START_ADDR1_1_OFFSET (0x88)
#define CAM_FRAME_START_ADDR_1_1       CAM_FRAME_START_ADDR_1_1
#define CAM_FRAME_START_ADDR_1_1_POS   (0U)
#define CAM_FRAME_START_ADDR_1_1_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_1_MSK   (((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS)
#define CAM_FRAME_START_ADDR_1_1_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_1_POS))

/* 0x8C : frame_byte_cnt1_1 */
#define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C)
#define CAM_FRAME_BYTE_CNT_1_1       CAM_FRAME_BYTE_CNT_1_1
#define CAM_FRAME_BYTE_CNT_1_1_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_1_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_1_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS)
#define CAM_FRAME_BYTE_CNT_1_1_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_1_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_1_POS))

/* 0x90 : frame_start_addr1_2 */
#define CAM_FRAME_START_ADDR1_2_OFFSET (0x90)
#define CAM_FRAME_START_ADDR_1_2       CAM_FRAME_START_ADDR_1_2
#define CAM_FRAME_START_ADDR_1_2_POS   (0U)
#define CAM_FRAME_START_ADDR_1_2_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_2_MSK   (((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS)
#define CAM_FRAME_START_ADDR_1_2_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_2_LEN) - 1) << CAM_FRAME_START_ADDR_1_2_POS))

/* 0x94 : frame_byte_cnt1_2 */
#define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94)
#define CAM_FRAME_BYTE_CNT_1_2       CAM_FRAME_BYTE_CNT_1_2
#define CAM_FRAME_BYTE_CNT_1_2_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_2_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_2_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS)
#define CAM_FRAME_BYTE_CNT_1_2_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_2_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_2_POS))

/* 0x98 : frame_start_addr1_3 */
#define CAM_FRAME_START_ADDR1_3_OFFSET (0x98)
#define CAM_FRAME_START_ADDR_1_3       CAM_FRAME_START_ADDR_1_3
#define CAM_FRAME_START_ADDR_1_3_POS   (0U)
#define CAM_FRAME_START_ADDR_1_3_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_3_MSK   (((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS)
#define CAM_FRAME_START_ADDR_1_3_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_3_LEN) - 1) << CAM_FRAME_START_ADDR_1_3_POS))

/* 0x9C : frame_byte_cnt1_3 */
#define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C)
#define CAM_FRAME_BYTE_CNT_1_3       CAM_FRAME_BYTE_CNT_1_3
#define CAM_FRAME_BYTE_CNT_1_3_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_3_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_3_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS)
#define CAM_FRAME_BYTE_CNT_1_3_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_3_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_3_POS))

/* 0xA0 : frame_start_addr1_4 */
#define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0)
#define CAM_FRAME_START_ADDR_1_4       CAM_FRAME_START_ADDR_1_4
#define CAM_FRAME_START_ADDR_1_4_POS   (0U)
#define CAM_FRAME_START_ADDR_1_4_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_4_MSK   (((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS)
#define CAM_FRAME_START_ADDR_1_4_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_4_LEN) - 1) << CAM_FRAME_START_ADDR_1_4_POS))

/* 0xA4 : frame_byte_cnt1_4 */
#define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4)
#define CAM_FRAME_BYTE_CNT_1_4       CAM_FRAME_BYTE_CNT_1_4
#define CAM_FRAME_BYTE_CNT_1_4_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_4_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_4_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS)
#define CAM_FRAME_BYTE_CNT_1_4_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_4_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_4_POS))

/* 0xA8 : frame_start_addr1_5 */
#define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8)
#define CAM_FRAME_START_ADDR_1_5       CAM_FRAME_START_ADDR_1_5
#define CAM_FRAME_START_ADDR_1_5_POS   (0U)
#define CAM_FRAME_START_ADDR_1_5_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_5_MSK   (((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS)
#define CAM_FRAME_START_ADDR_1_5_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_5_LEN) - 1) << CAM_FRAME_START_ADDR_1_5_POS))

/* 0xAC : frame_byte_cnt1_5 */
#define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC)
#define CAM_FRAME_BYTE_CNT_1_5       CAM_FRAME_BYTE_CNT_1_5
#define CAM_FRAME_BYTE_CNT_1_5_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_5_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_5_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS)
#define CAM_FRAME_BYTE_CNT_1_5_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_5_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_5_POS))

/* 0xB0 : frame_start_addr1_6 */
#define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0)
#define CAM_FRAME_START_ADDR_1_6       CAM_FRAME_START_ADDR_1_6
#define CAM_FRAME_START_ADDR_1_6_POS   (0U)
#define CAM_FRAME_START_ADDR_1_6_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_6_MSK   (((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS)
#define CAM_FRAME_START_ADDR_1_6_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_6_LEN) - 1) << CAM_FRAME_START_ADDR_1_6_POS))

/* 0xB4 : frame_byte_cnt1_6 */
#define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4)
#define CAM_FRAME_BYTE_CNT_1_6       CAM_FRAME_BYTE_CNT_1_6
#define CAM_FRAME_BYTE_CNT_1_6_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_6_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_6_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS)
#define CAM_FRAME_BYTE_CNT_1_6_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_6_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_6_POS))

/* 0xB8 : frame_start_addr1_7 */
#define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8)
#define CAM_FRAME_START_ADDR_1_7       CAM_FRAME_START_ADDR_1_7
#define CAM_FRAME_START_ADDR_1_7_POS   (0U)
#define CAM_FRAME_START_ADDR_1_7_LEN   (32U)
#define CAM_FRAME_START_ADDR_1_7_MSK   (((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS)
#define CAM_FRAME_START_ADDR_1_7_UMSK  (~(((1U << CAM_FRAME_START_ADDR_1_7_LEN) - 1) << CAM_FRAME_START_ADDR_1_7_POS))

/* 0xBC : frame_byte_cnt1_7 */
#define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC)
#define CAM_FRAME_BYTE_CNT_1_7       CAM_FRAME_BYTE_CNT_1_7
#define CAM_FRAME_BYTE_CNT_1_7_POS   (0U)
#define CAM_FRAME_BYTE_CNT_1_7_LEN   (32U)
#define CAM_FRAME_BYTE_CNT_1_7_MSK   (((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS)
#define CAM_FRAME_BYTE_CNT_1_7_UMSK  (~(((1U << CAM_FRAME_BYTE_CNT_1_7_LEN) - 1) << CAM_FRAME_BYTE_CNT_1_7_POS))

/* 0xFF0 : dvp_debug */
#define CAM_DVP_DEBUG_OFFSET     (0xFF0)
#define CAM_REG_DVP_DBG_EN       CAM_REG_DVP_DBG_EN
#define CAM_REG_DVP_DBG_EN_POS   (0U)
#define CAM_REG_DVP_DBG_EN_LEN   (1U)
#define CAM_REG_DVP_DBG_EN_MSK   (((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS)
#define CAM_REG_DVP_DBG_EN_UMSK  (~(((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS))
#define CAM_REG_DVP_DBG_SEL      CAM_REG_DVP_DBG_SEL
#define CAM_REG_DVP_DBG_SEL_POS  (1U)
#define CAM_REG_DVP_DBG_SEL_LEN  (3U)
#define CAM_REG_DVP_DBG_SEL_MSK  (((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS)
#define CAM_REG_DVP_DBG_SEL_UMSK (~(((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS))

/* 0xFFC : dvp_dummy_reg */
#define CAM_DVP_DUMMY_REG_OFFSET (0xFFC)

struct cam_reg {
    /* 0x0 : dvp2axi_configue */
    union {
        struct
        {
            uint32_t reg_dvp_enable     : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_sw_mode        : 1; /* [    1],        r/w,        0x0 */
            uint32_t reg_fram_vld_pol   : 1; /* [    2],        r/w,        0x1 */
            uint32_t reg_line_vld_pol   : 1; /* [    3],        r/w,        0x1 */
            uint32_t reg_hburst         : 2; /* [ 5: 4],        r/w,        0x3 */
            uint32_t reserved_6_7       : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_dvp_mode       : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reg_hw_mode_fwrap  : 1; /* [   11],        r/w,        0x1 */
            uint32_t reg_drop_en        : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_drop_even      : 1; /* [   13],        r/w,        0x0 */
            uint32_t reg_subsample_en   : 1; /* [   14],        r/w,        0x0 */
            uint32_t reg_subsample_even : 1; /* [   15],        r/w,        0x0 */
            uint32_t reg_interlv_mode   : 1; /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_19     : 3; /* [19:17],       rsvd,        0x0 */
            uint32_t reg_dvp_pix_clk_cg : 1; /* [   20],        r/w,        0x0 */
            uint32_t reserved_21_23     : 3; /* [23:21],       rsvd,        0x0 */
            uint32_t reg_dvp_wait_cycle : 8; /* [31:24],        r/w,       0x40 */
        } BF;
        uint32_t WORD;
    } dvp2axi_configue;

    /* 0x4 : dvp2ahb_addr_start_0 */
    union {
        struct
        {
            uint32_t reg_addr_start_0 : 32; /* [31: 0],        r/w, 0x80000000L */
        } BF;
        uint32_t WORD;
    } dvp2ahb_addr_start_0;

    /* 0x8 : dvp2ahb_mem_bcnt_0 */
    union {
        struct
        {
            uint32_t reg_mem_burst_cnt_0 : 32; /* [31: 0],        r/w,     0xc000 */
        } BF;
        uint32_t WORD;
    } dvp2ahb_mem_bcnt_0;

    /* 0xC : dvp2ahb_frame_bcnt_0 */
    union {
        struct
        {
            uint32_t reg_frame_burst_cnt_0 : 32; /* [31: 0],        r/w,     0xc000 */
        } BF;
        uint32_t WORD;
    } dvp2ahb_frame_bcnt_0;

    /* 0x10 : dvp2ahb_addr_start_1 */
    union {
        struct
        {
            uint32_t reg_addr_start_1 : 32; /* [31: 0],        r/w, 0x80000000L */
        } BF;
        uint32_t WORD;
    } dvp2ahb_addr_start_1;

    /* 0x14 : dvp2ahb_mem_bcnt_1 */
    union {
        struct
        {
            uint32_t reg_mem_burst_cnt_1 : 32; /* [31: 0],        r/w,     0xc000 */
        } BF;
        uint32_t WORD;
    } dvp2ahb_mem_bcnt_1;

    /* 0x18 : dvp2ahb_frame_bcnt_1 */
    union {
        struct
        {
            uint32_t reg_frame_burst_cnt_1 : 32; /* [31: 0],        r/w,     0xc000 */
        } BF;
        uint32_t WORD;
    } dvp2ahb_frame_bcnt_1;

    /* 0x1C : dvp_status_and_error */
    union {
        struct
        {
            uint32_t sts_normal_int_0  : 1; /* [    0],          r,        0x0 */
            uint32_t sts_normal_int_1  : 1; /* [    1],          r,        0x0 */
            uint32_t sts_mem_int_0     : 1; /* [    2],          r,        0x0 */
            uint32_t sts_mem_int_1     : 1; /* [    3],          r,        0x0 */
            uint32_t sts_frame_int_0   : 1; /* [    4],          r,        0x0 */
            uint32_t sts_frame_int_1   : 1; /* [    5],          r,        0x0 */
            uint32_t sts_fifo_int_0    : 1; /* [    6],          r,        0x0 */
            uint32_t sts_fifo_int_1    : 1; /* [    7],          r,        0x0 */
            uint32_t sts_hcnt_int      : 1; /* [    8],          r,        0x0 */
            uint32_t sts_vcnt_int      : 1; /* [    9],          r,        0x0 */
            uint32_t reserved_10_15    : 6; /* [15:10],       rsvd,        0x0 */
            uint32_t ahb_idle_0        : 1; /* [   16],          r,        0x1 */
            uint32_t ahb_idle_1        : 1; /* [   17],          r,        0x1 */
            uint32_t reserved_18       : 1; /* [   18],       rsvd,        0x0 */
            uint32_t st_dvp_idle       : 1; /* [   19],          r,        0x1 */
            uint32_t frame_valid_cnt_0 : 4; /* [23:20],          r,        0x0 */
            uint32_t frame_valid_cnt_1 : 4; /* [27:24],          r,        0x0 */
            uint32_t st_bus_idle       : 1; /* [   28],          r,        0x1 */
            uint32_t st_bus_func       : 1; /* [   29],          r,        0x0 */
            uint32_t st_bus_wait       : 1; /* [   30],          r,        0x0 */
            uint32_t st_bus_flsh       : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } dvp_status_and_error;

    /* 0x20 : dvp_frame_fifo_pop */
    union {
        struct
        {
            uint32_t rfifo_pop_0          : 1;  /* [    0],        w1p,        0x0 */
            uint32_t rfifo_pop_1          : 1;  /* [    1],        w1p,        0x0 */
            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
            uint32_t reg_int_normal_clr_0 : 1;  /* [    4],        w1p,        0x0 */
            uint32_t reg_int_mem_clr_0    : 1;  /* [    5],        w1p,        0x0 */
            uint32_t reg_int_frame_clr_0  : 1;  /* [    6],        w1p,        0x0 */
            uint32_t reg_int_fifo_clr_0   : 1;  /* [    7],        w1p,        0x0 */
            uint32_t reg_int_hcnt_clr_0   : 1;  /* [    8],        w1p,        0x0 */
            uint32_t reg_int_vcnt_clr_0   : 1;  /* [    9],        w1p,        0x0 */
            uint32_t reserved_10_15       : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t reg_int_normal_clr_1 : 1;  /* [   16],        w1p,        0x0 */
            uint32_t reg_int_mem_clr_1    : 1;  /* [   17],        w1p,        0x0 */
            uint32_t reg_int_frame_clr_1  : 1;  /* [   18],        w1p,        0x0 */
            uint32_t reg_int_fifo_clr_1   : 1;  /* [   19],        w1p,        0x0 */
            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } dvp_frame_fifo_pop;

    /* 0x24 : snsr_control */
    union {
        struct
        {
            uint32_t reg_cam_rst   : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reg_cam_pwdn  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } snsr_control;

    /* 0x28 : int_control */
    union {
        struct
        {
            uint32_t reg_int_normal_0_en    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_int_normal_1_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_int_mem_en         : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reg_int_frame_en       : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reg_int_fifo_en        : 1;  /* [    4],        r/w,        0x1 */
            uint32_t reg_int_hcnt_en        : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reg_int_vcnt_en        : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7_27          : 21; /* [27: 7],       rsvd,        0x0 */
            uint32_t reg_frame_cnt_trgr_int : 4;  /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } int_control;

    /* 0x2c  reserved */
    uint8_t RESERVED0x2c[4];

    /* 0x30 : hsync_control */
    union {
        struct
        {
            uint32_t reg_hsync_act_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t reg_hsync_act_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } hsync_control;

    /* 0x34 : vsync_control */
    union {
        struct
        {
            uint32_t reg_vsync_act_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t reg_vsync_act_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } vsync_control;

    /* 0x38 : frame_size_control */
    union {
        struct
        {
            uint32_t reg_total_hcnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_total_vcnt : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_size_control;

    /* 0x3c  reserved */
    uint8_t RESERVED0x3c[4];

    /* 0x40 : frame_start_addr0_0 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_0;

    /* 0x44 : frame_byte_cnt0_0 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_0;

    /* 0x48 : frame_start_addr0_1 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_1;

    /* 0x4C : frame_byte_cnt0_1 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_1;

    /* 0x50 : frame_start_addr0_2 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_2;

    /* 0x54 : frame_byte_cnt0_2 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_2;

    /* 0x58 : frame_start_addr0_3 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_3;

    /* 0x5C : frame_byte_cnt0_3 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_3;

    /* 0x60 : frame_start_addr0_4 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_4;

    /* 0x64 : frame_byte_cnt0_4 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_4;

    /* 0x68 : frame_start_addr0_5 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_5;

    /* 0x6C : frame_byte_cnt0_5 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_5;

    /* 0x70 : frame_start_addr0_6 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_6;

    /* 0x74 : frame_byte_cnt0_6 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_6;

    /* 0x78 : frame_start_addr0_7 */
    union {
        struct
        {
            uint32_t frame_start_addr_0_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr0_7;

    /* 0x7C : frame_byte_cnt0_7 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_0_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt0_7;

    /* 0x80 : frame_start_addr1_0 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_0;

    /* 0x84 : frame_byte_cnt1_0 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_0;

    /* 0x88 : frame_start_addr1_1 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_1;

    /* 0x8C : frame_byte_cnt1_1 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_1;

    /* 0x90 : frame_start_addr1_2 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_2;

    /* 0x94 : frame_byte_cnt1_2 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_2;

    /* 0x98 : frame_start_addr1_3 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_3;

    /* 0x9C : frame_byte_cnt1_3 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_3;

    /* 0xA0 : frame_start_addr1_4 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_4;

    /* 0xA4 : frame_byte_cnt1_4 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_4;

    /* 0xA8 : frame_start_addr1_5 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_5;

    /* 0xAC : frame_byte_cnt1_5 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_5;

    /* 0xB0 : frame_start_addr1_6 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_6;

    /* 0xB4 : frame_byte_cnt1_6 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_6;

    /* 0xB8 : frame_start_addr1_7 */
    union {
        struct
        {
            uint32_t frame_start_addr_1_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_start_addr1_7;

    /* 0xBC : frame_byte_cnt1_7 */
    union {
        struct
        {
            uint32_t frame_byte_cnt_1_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } frame_byte_cnt1_7;

    /* 0xc0  reserved */
    uint8_t RESERVED0xc0[3888];

    /* 0xFF0 : dvp_debug */
    union {
        struct
        {
            uint32_t reg_dvp_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_dvp_dbg_sel : 3;  /* [ 3: 1],        r/w,        0x0 */
            uint32_t reserved_4_31   : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } dvp_debug;

    /* 0xff4  reserved */
    uint8_t RESERVED0xff4[8];

    /* 0xFFC : dvp_dummy_reg */
    union {
        struct
        {
            uint32_t RESERVED_31_0 : 32; /* [31: 0],       rsvd, 0xf0f0f0f0L */
        } BF;
        uint32_t WORD;
    } dvp_dummy_reg;
};

typedef volatile struct cam_reg cam_reg_t;

#endif /* __CAM_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cci_reg.h
================================================
/**
  ******************************************************************************
  * @file    cci_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __CCI_REG_H__
#define __CCI_REG_H__

#include "bl702.h"

/* 0x0 : cci_cfg */
#define CCI_CFG_OFFSET              (0x0)
#define CCI_EN                      CCI_EN
#define CCI_EN_POS                  (0U)
#define CCI_EN_LEN                  (1U)
#define CCI_EN_MSK                  (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
#define CCI_EN_UMSK                 (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
#define CCI_SLV_SEL_CCI2            CCI_SLV_SEL_CCI2
#define CCI_SLV_SEL_CCI2_POS        (1U)
#define CCI_SLV_SEL_CCI2_LEN        (1U)
#define CCI_SLV_SEL_CCI2_MSK        (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
#define CCI_SLV_SEL_CCI2_UMSK       (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
#define CCI_MAS_SEL_CCI2            CCI_MAS_SEL_CCI2
#define CCI_MAS_SEL_CCI2_POS        (2U)
#define CCI_MAS_SEL_CCI2_LEN        (1U)
#define CCI_MAS_SEL_CCI2_MSK        (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
#define CCI_MAS_SEL_CCI2_UMSK       (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
#define CCI_MAS_HW_MODE             CCI_MAS_HW_MODE
#define CCI_MAS_HW_MODE_POS         (3U)
#define CCI_MAS_HW_MODE_LEN         (1U)
#define CCI_MAS_HW_MODE_MSK         (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
#define CCI_MAS_HW_MODE_UMSK        (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
#define CCI_REG_M_CCI_SCLK_EN       CCI_REG_M_CCI_SCLK_EN
#define CCI_REG_M_CCI_SCLK_EN_POS   (4U)
#define CCI_REG_M_CCI_SCLK_EN_LEN   (1U)
#define CCI_REG_M_CCI_SCLK_EN_MSK   (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
#define CCI_REG_M_CCI_SCLK_EN_UMSK  (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
#define CCI_REG_DIV_M_CCI_SCLK      CCI_REG_DIV_M_CCI_SCLK
#define CCI_REG_DIV_M_CCI_SCLK_POS  (5U)
#define CCI_REG_DIV_M_CCI_SCLK_LEN  (2U)
#define CCI_REG_DIV_M_CCI_SCLK_MSK  (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
#define CCI_CFG_CCI1_PRE_READ       CCI_CFG_CCI1_PRE_READ
#define CCI_CFG_CCI1_PRE_READ_POS   (7U)
#define CCI_CFG_CCI1_PRE_READ_LEN   (1U)
#define CCI_CFG_CCI1_PRE_READ_MSK   (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
#define CCI_CFG_CCI1_PRE_READ_UMSK  (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
#define CCI_REG_SCCI_CLK_INV        CCI_REG_SCCI_CLK_INV
#define CCI_REG_SCCI_CLK_INV_POS    (8U)
#define CCI_REG_SCCI_CLK_INV_LEN    (1U)
#define CCI_REG_SCCI_CLK_INV_MSK    (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
#define CCI_REG_SCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
#define CCI_REG_MCCI_CLK_INV        CCI_REG_MCCI_CLK_INV
#define CCI_REG_MCCI_CLK_INV_POS    (9U)
#define CCI_REG_MCCI_CLK_INV_LEN    (1U)
#define CCI_REG_MCCI_CLK_INV_MSK    (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
#define CCI_REG_MCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))

/* 0x4 : cci_addr */
#define CCI_ADDR_OFFSET       (0x4)
#define CCI_APB_CCI_ADDR      CCI_APB_CCI_ADDR
#define CCI_APB_CCI_ADDR_POS  (0U)
#define CCI_APB_CCI_ADDR_LEN  (32U)
#define CCI_APB_CCI_ADDR_MSK  (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))

/* 0x8 : cci_wdata */
#define CCI_WDATA_OFFSET       (0x8)
#define CCI_APB_CCI_WDATA      CCI_APB_CCI_WDATA
#define CCI_APB_CCI_WDATA_POS  (0U)
#define CCI_APB_CCI_WDATA_LEN  (32U)
#define CCI_APB_CCI_WDATA_MSK  (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))

/* 0xC : cci_rdata */
#define CCI_RDATA_OFFSET       (0xC)
#define CCI_APB_CCI_RDATA      CCI_APB_CCI_RDATA
#define CCI_APB_CCI_RDATA_POS  (0U)
#define CCI_APB_CCI_RDATA_LEN  (32U)
#define CCI_APB_CCI_RDATA_MSK  (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))

/* 0x10 : cci_ctl */
#define CCI_CTL_OFFSET      (0x10)
#define CCI_WRITE_FLAG      CCI_WRITE_FLAG
#define CCI_WRITE_FLAG_POS  (0U)
#define CCI_WRITE_FLAG_LEN  (1U)
#define CCI_WRITE_FLAG_MSK  (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
#define CCI_READ_FLAG       CCI_READ_FLAG
#define CCI_READ_FLAG_POS   (1U)
#define CCI_READ_FLAG_LEN   (1U)
#define CCI_READ_FLAG_MSK   (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
#define CCI_READ_FLAG_UMSK  (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
#define CCI_AHB_STATE       CCI_AHB_STATE
#define CCI_AHB_STATE_POS   (2U)
#define CCI_AHB_STATE_LEN   (2U)
#define CCI_AHB_STATE_MSK   (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
#define CCI_AHB_STATE_UMSK  (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))

struct cci_reg {
    /* 0x0 : cci_cfg */
    union {
        struct
        {
            uint32_t cci_en             : 1;  /* [    0],        r/w,        0x1 */
            uint32_t cci_slv_sel_cci2   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cci_mas_sel_cci2   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cci_mas_hw_mode    : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reg_m_cci_sclk_en  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_div_m_cci_sclk : 2;  /* [ 6: 5],        r/w,        0x1 */
            uint32_t cfg_cci1_pre_read  : 1;  /* [    7],        r/w,        0x0 */
            uint32_t reg_scci_clk_inv   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reg_mcci_clk_inv   : 1;  /* [    9],        r/w,        0x1 */
            uint32_t reserved_10_31     : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cci_cfg;

    /* 0x4 : cci_addr */
    union {
        struct
        {
            uint32_t apb_cci_addr : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } cci_addr;

    /* 0x8 : cci_wdata */
    union {
        struct
        {
            uint32_t apb_cci_wdata : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } cci_wdata;

    /* 0xC : cci_rdata */
    union {
        struct
        {
            uint32_t apb_cci_rdata : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } cci_rdata;

    /* 0x10 : cci_ctl */
    union {
        struct
        {
            uint32_t cci_write_flag : 1;  /* [    0],          r,        0x0 */
            uint32_t cci_read_flag  : 1;  /* [    1],          r,        0x0 */
            uint32_t ahb_state      : 2;  /* [ 3: 2],          r,        0x0 */
            uint32_t reserved_4_31  : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cci_ctl;
};

typedef volatile struct cci_reg cci_reg_t;

#endif /* __CCI_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/cks_reg.h
================================================
/**
  ******************************************************************************
  * @file    cks_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __CKS_REG_H__
#define __CKS_REG_H__

#include "bl702.h"

/* 0x0 : cks_config */
#define CKS_CONFIG_OFFSET         (0x0)
#define CKS_CR_CKS_CLR            CKS_CR_CKS_CLR
#define CKS_CR_CKS_CLR_POS        (0U)
#define CKS_CR_CKS_CLR_LEN        (1U)
#define CKS_CR_CKS_CLR_MSK        (((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS)
#define CKS_CR_CKS_CLR_UMSK       (~(((1U << CKS_CR_CKS_CLR_LEN) - 1) << CKS_CR_CKS_CLR_POS))
#define CKS_CR_CKS_BYTE_SWAP      CKS_CR_CKS_BYTE_SWAP
#define CKS_CR_CKS_BYTE_SWAP_POS  (1U)
#define CKS_CR_CKS_BYTE_SWAP_LEN  (1U)
#define CKS_CR_CKS_BYTE_SWAP_MSK  (((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS)
#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U << CKS_CR_CKS_BYTE_SWAP_LEN) - 1) << CKS_CR_CKS_BYTE_SWAP_POS))

/* 0x4 : data_in */
#define CKS_DATA_IN_OFFSET (0x4)
#define CKS_DATA_IN        CKS_DATA_IN
#define CKS_DATA_IN_POS    (0U)
#define CKS_DATA_IN_LEN    (8U)
#define CKS_DATA_IN_MSK    (((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS)
#define CKS_DATA_IN_UMSK   (~(((1U << CKS_DATA_IN_LEN) - 1) << CKS_DATA_IN_POS))

/* 0x8 : cks_out */
#define CKS_OUT_OFFSET (0x8)
#define CKS_OUT        CKS_OUT
#define CKS_OUT_POS    (0U)
#define CKS_OUT_LEN    (16U)
#define CKS_OUT_MSK    (((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS)
#define CKS_OUT_UMSK   (~(((1U << CKS_OUT_LEN) - 1) << CKS_OUT_POS))

struct cks_reg {
    /* 0x0 : cks_config */
    union {
        struct
        {
            uint32_t cr_cks_clr       : 1;  /* [    0],        w1c,        0x0 */
            uint32_t cr_cks_byte_swap : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cks_config;

    /* 0x4 : data_in */
    union {
        struct
        {
            uint32_t data_in       : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } data_in;

    /* 0x8 : cks_out */
    union {
        struct
        {
            uint32_t cks_out        : 16; /* [15: 0],          r,     0xffff */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cks_out;
};

typedef volatile struct cks_reg cks_reg_t;

#endif /* __CKS_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/dma_reg.h
================================================
/**
  ******************************************************************************
  * @file    dma_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __DMA_REG_H__
#define __DMA_REG_H__

#include "bl702.h"

/* 0x0 : DMA_IntStatus */
#define DMA_INTSTATUS_OFFSET (0x0)
#define DMA_INTSTATUS        DMA_INTSTATUS
#define DMA_INTSTATUS_POS    (0U)
#define DMA_INTSTATUS_LEN    (8U)
#define DMA_INTSTATUS_MSK    (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)
#define DMA_INTSTATUS_UMSK   (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS))

/* 0x4 : DMA_IntTCStatus */
#define DMA_INTTCSTATUS_OFFSET (0x4)
#define DMA_INTTCSTATUS        DMA_INTTCSTATUS
#define DMA_INTTCSTATUS_POS    (0U)
#define DMA_INTTCSTATUS_LEN    (8U)
#define DMA_INTTCSTATUS_MSK    (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)
#define DMA_INTTCSTATUS_UMSK   (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS))

/* 0x8 : DMA_IntTCClear */
#define DMA_INTTCCLEAR_OFFSET (0x8)
#define DMA_INTTCCLEAR        DMA_INTTCCLEAR
#define DMA_INTTCCLEAR_POS    (0U)
#define DMA_INTTCCLEAR_LEN    (8U)
#define DMA_INTTCCLEAR_MSK    (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)
#define DMA_INTTCCLEAR_UMSK   (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS))

/* 0xC : DMA_IntErrorStatus */
#define DMA_INTERRORSTATUS_OFFSET (0xC)
#define DMA_INTERRORSTATUS        DMA_INTERRORSTATUS
#define DMA_INTERRORSTATUS_POS    (0U)
#define DMA_INTERRORSTATUS_LEN    (8U)
#define DMA_INTERRORSTATUS_MSK    (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)
#define DMA_INTERRORSTATUS_UMSK   (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS))

/* 0x10 : DMA_IntErrClr */
#define DMA_INTERRCLR_OFFSET (0x10)
#define DMA_INTERRCLR        DMA_INTERRCLR
#define DMA_INTERRCLR_POS    (0U)
#define DMA_INTERRCLR_LEN    (8U)
#define DMA_INTERRCLR_MSK    (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)
#define DMA_INTERRCLR_UMSK   (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS))

/* 0x14 : DMA_RawIntTCStatus */
#define DMA_RAWINTTCSTATUS_OFFSET (0x14)
#define DMA_RAWINTTCSTATUS        DMA_RAWINTTCSTATUS
#define DMA_RAWINTTCSTATUS_POS    (0U)
#define DMA_RAWINTTCSTATUS_LEN    (8U)
#define DMA_RAWINTTCSTATUS_MSK    (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)
#define DMA_RAWINTTCSTATUS_UMSK   (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS))

/* 0x18 : DMA_RawIntErrorStatus */
#define DMA_RAWINTERRORSTATUS_OFFSET (0x18)
#define DMA_RAWINTERRORSTATUS        DMA_RAWINTERRORSTATUS
#define DMA_RAWINTERRORSTATUS_POS    (0U)
#define DMA_RAWINTERRORSTATUS_LEN    (8U)
#define DMA_RAWINTERRORSTATUS_MSK    (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)
#define DMA_RAWINTERRORSTATUS_UMSK   (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS))

/* 0x1C : DMA_EnbldChns */
#define DMA_ENBLDCHNS_OFFSET     (0x1C)
#define DMA_ENABLEDCHANNELS      DMA_ENABLEDCHANNELS
#define DMA_ENABLEDCHANNELS_POS  (0U)
#define DMA_ENABLEDCHANNELS_LEN  (8U)
#define DMA_ENABLEDCHANNELS_MSK  (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)
#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS))

/* 0x20 : DMA_SoftBReq */
#define DMA_SOFTBREQ_OFFSET (0x20)
#define DMA_SOFTBREQ        DMA_SOFTBREQ
#define DMA_SOFTBREQ_POS    (0U)
#define DMA_SOFTBREQ_LEN    (32U)
#define DMA_SOFTBREQ_MSK    (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)
#define DMA_SOFTBREQ_UMSK   (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS))

/* 0x24 : DMA_SoftSReq */
#define DMA_SOFTSREQ_OFFSET (0x24)
#define DMA_SOFTSREQ        DMA_SOFTSREQ
#define DMA_SOFTSREQ_POS    (0U)
#define DMA_SOFTSREQ_LEN    (32U)
#define DMA_SOFTSREQ_MSK    (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)
#define DMA_SOFTSREQ_UMSK   (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS))

/* 0x28 : DMA_SoftLBReq */
#define DMA_SOFTLBREQ_OFFSET (0x28)
#define DMA_SOFTLBREQ        DMA_SOFTLBREQ
#define DMA_SOFTLBREQ_POS    (0U)
#define DMA_SOFTLBREQ_LEN    (32U)
#define DMA_SOFTLBREQ_MSK    (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)
#define DMA_SOFTLBREQ_UMSK   (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS))

/* 0x2C : DMA_SoftLSReq */
#define DMA_SOFTLSREQ_OFFSET (0x2C)
#define DMA_SOFTLSREQ        DMA_SOFTLSREQ
#define DMA_SOFTLSREQ_POS    (0U)
#define DMA_SOFTLSREQ_LEN    (32U)
#define DMA_SOFTLSREQ_MSK    (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)
#define DMA_SOFTLSREQ_UMSK   (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS))

/* 0x30 : DMA_Top_Config */
#define DMA_TOP_CONFIG_OFFSET (0x30)
#define DMA_E                 DMA_E
#define DMA_E_POS             (0U)
#define DMA_E_LEN             (1U)
#define DMA_E_MSK             (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK            (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_M                 DMA_M
#define DMA_M_POS             (1U)
#define DMA_M_LEN             (1U)
#define DMA_M_MSK             (((1U << DMA_M_LEN) - 1) << DMA_M_POS)
#define DMA_M_UMSK            (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS))

/* 0x34 : DMA_Sync */
#define DMA_SYNC_OFFSET (0x34)
#define DMA_SYNC        DMA_SYNC
#define DMA_SYNC_POS    (0U)
#define DMA_SYNC_LEN    (32U)
#define DMA_SYNC_MSK    (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)
#define DMA_SYNC_UMSK   (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS))

#if 0
/* 0x100 : DMA_C0SrcAddr */
#define DMA_C0SRCADDR_OFFSET   (0x100)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x104 : DMA_C0DstAddr */
#define DMA_C0DSTADDR_OFFSET   (0x104)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x108 : DMA_C0LLI */
#define DMA_C0LLI_OFFSET       (0x108)
#define DMA_LLI                DMA_LLI
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x10C : DMA_C0Control */
#define DMA_C0CONTROL_OFFSET   (0x10C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (2U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (2U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SLARGERD           DMA_SLARGERD
#define DMA_SLARGERD_POS       (25U)
#define DMA_SLARGERD_LEN       (1U)
#define DMA_SLARGERD_MSK       (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)
#define DMA_SLARGERD_UMSK      (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x110 : DMA_C0Config */
#define DMA_C0CONFIG_OFFSET    (0x110)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
#define DMA_LLICOUNTER         DMA_LLICOUNTER
#define DMA_LLICOUNTER_POS     (20U)
#define DMA_LLICOUNTER_LEN     (10U)
#define DMA_LLICOUNTER_MSK     (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)
#define DMA_LLICOUNTER_UMSK    (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS))

/* 0x200 : DMA_C1SrcAddr */
#define DMA_C1SRCADDR_OFFSET   (0x200)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x204 : DMA_C1DstAddr */
#define DMA_C1DSTADDR_OFFSET   (0x204)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x208 : DMA_C1LLI */
#define DMA_C1LLI_OFFSET       (0x208)
#define DMA_LLI                DMA_LLI
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x20C : DMA_C1Control */
#define DMA_C1CONTROL_OFFSET   (0x20C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x210 : DMA_C1Config */
#define DMA_C1CONFIG_OFFSET    (0x210)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x300 : DMA_C2SrcAddr */
#define DMA_C2SRCADDR_OFFSET   (0x300)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x304 : DMA_C2DstAddr */
#define DMA_C2DSTADDR_OFFSET   (0x304)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x308 : DMA_C2LLI */
#define DMA_C2LLI_OFFSET       (0x308)
#define DMA_LLI                DMA_LLI
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x30C : DMA_C2Control */
#define DMA_C2CONTROL_OFFSET   (0x30C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x310 : DMA_C2Config */
#define DMA_C2CONFIG_OFFSET    (0x310)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x400 : DMA_C3SrcAddr */
#define DMA_C3SRCADDR_OFFSET   (0x400)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x404 : DMA_C3DstAddr */
#define DMA_C3DSTADDR_OFFSET   (0x404)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x408 : DMA_C3LLI */
#define DMA_C3LLI_OFFSET       (0x408)
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x40C : DMA_C3Control */
#define DMA_C3CONTROL_OFFSET   (0x40C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x410 : DMA_C3Config */
#define DMA_C3CONFIG_OFFSET    (0x410)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x500 : DMA_C4SrcAddr */
#define DMA_C4SRCADDR_OFFSET   (0x500)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x504 : DMA_C4DstAddr */
#define DMA_C4DSTADDR_OFFSET   (0x504)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x508 : DMA_C4LLI */
#define DMA_C4LLI_OFFSET       (0x508)
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x50C : DMA_C4Control */
#define DMA_C4CONTROL_OFFSET   (0x50C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x510 : DMA_C4Config */
#define DMA_C4CONFIG_OFFSET    (0x510)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x600 : DMA_C5SrcAddr */
#define DMA_C5SRCADDR_OFFSET   (0x600)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x604 : DMA_C5DstAddr */
#define DMA_C5DSTADDR_OFFSET   (0x604)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x608 : DMA_C5LLI */
#define DMA_C5LLI_OFFSET       (0x608)
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x60C : DMA_C5Control */
#define DMA_C5CONTROL_OFFSET   (0x60C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x610 : DMA_C5Config */
#define DMA_C5CONFIG_OFFSET    (0x610)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x700 : DMA_C6SrcAddr */
#define DMA_C6SRCADDR_OFFSET   (0x700)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x704 : DMA_C6DstAddr */
#define DMA_C6DSTADDR_OFFSET   (0x704)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x708 : DMA_C6LLI */
#define DMA_C6LLI_OFFSET       (0x708)
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x70C : DMA_C6Control */
#define DMA_C6CONTROL_OFFSET   (0x70C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x710 : DMA_C6Config */
#define DMA_C6CONFIG_OFFSET    (0x710)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))

/* 0x800 : DMA_C7SrcAddr */
#define DMA_C7SRCADDR_OFFSET   (0x800)
#define DMA_SRCADDR            DMA_SRCADDR
#define DMA_SRCADDR_POS        (0U)
#define DMA_SRCADDR_LEN        (32U)
#define DMA_SRCADDR_MSK        (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK       (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x804 : DMA_C7DstAddr */
#define DMA_C7DSTADDR_OFFSET   (0x804)
#define DMA_DSTADDR            DMA_DSTADDR
#define DMA_DSTADDR_POS        (0U)
#define DMA_DSTADDR_LEN        (32U)
#define DMA_DSTADDR_MSK        (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK       (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x808 : DMA_C7LLI */
#define DMA_C7LLI_OFFSET       (0x808)
#define DMA_LLI_POS            (0U)
#define DMA_LLI_LEN            (32U)
#define DMA_LLI_MSK            (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK           (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0x80C : DMA_C7Control */
#define DMA_C7CONTROL_OFFSET   (0x80C)
#define DMA_TRANSFERSIZE       DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS   (0U)
#define DMA_TRANSFERSIZE_LEN   (12U)
#define DMA_TRANSFERSIZE_MSK   (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK  (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE             DMA_SBSIZE
#define DMA_SBSIZE_POS         (12U)
#define DMA_SBSIZE_LEN         (2U)
#define DMA_SBSIZE_MSK         (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK        (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE       DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS   (14U)
#define DMA_DST_MIN_MODE_LEN   (1U)
#define DMA_DST_MIN_MODE_MSK   (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK  (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE             DMA_DBSIZE
#define DMA_DBSIZE_POS         (15U)
#define DMA_DBSIZE_LEN         (2U)
#define DMA_DBSIZE_MSK         (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK        (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE       DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS   (17U)
#define DMA_DST_ADD_MODE_LEN   (1U)
#define DMA_DST_ADD_MODE_MSK   (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK  (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH             DMA_SWIDTH
#define DMA_SWIDTH_POS         (18U)
#define DMA_SWIDTH_LEN         (3U)
#define DMA_SWIDTH_MSK         (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK        (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH             DMA_DWIDTH
#define DMA_DWIDTH_POS         (21U)
#define DMA_DWIDTH_LEN         (3U)
#define DMA_DWIDTH_MSK         (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK        (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT            DMA_FIX_CNT
#define DMA_FIX_CNT_POS        (23U)
#define DMA_FIX_CNT_LEN        (2U)
#define DMA_FIX_CNT_MSK        (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK       (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SI                 DMA_SI
#define DMA_SI_POS             (26U)
#define DMA_SI_LEN             (1U)
#define DMA_SI_MSK             (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK            (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                 DMA_DI
#define DMA_DI_POS             (27U)
#define DMA_DI_LEN             (1U)
#define DMA_DI_MSK             (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK            (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT               DMA_PROT
#define DMA_PROT_POS           (28U)
#define DMA_PROT_LEN           (3U)
#define DMA_PROT_MSK           (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK          (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                  DMA_I
#define DMA_I_POS              (31U)
#define DMA_I_LEN              (1U)
#define DMA_I_MSK              (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK             (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x810 : DMA_C7Config */
#define DMA_C7CONFIG_OFFSET    (0x810)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))


struct  dma_reg
{
    /* 0x0 : DMA_IntStatus */
    union
    {
        struct
        {
            uint32_t IntStatus                      :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_IntStatus;

    /* 0x4 : DMA_IntTCStatus */
    union
    {
        struct
        {
            uint32_t IntTCStatus                    :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_IntTCStatus;

    /* 0x8 : DMA_IntTCClear */
    union
    {
        struct
        {
            uint32_t IntTCClear                     :  8; /* [ 7: 0],          w,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_IntTCClear;

    /* 0xC : DMA_IntErrorStatus */
    union
    {
        struct
        {
            uint32_t IntErrorStatus                 :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_IntErrorStatus;

    /* 0x10 : DMA_IntErrClr */
    union
    {
        struct
        {
            uint32_t IntErrClr                      :  8; /* [ 7: 0],          w,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_IntErrClr;

    /* 0x14 : DMA_RawIntTCStatus */
    union
    {
        struct
        {
            uint32_t RawIntTCStatus                 :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_RawIntTCStatus;

    /* 0x18 : DMA_RawIntErrorStatus */
    union
    {
        struct
        {
            uint32_t RawIntErrorStatus              :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_RawIntErrorStatus;

    /* 0x1C : DMA_EnbldChns */
    union
    {
        struct
        {
            uint32_t EnabledChannels                :  8; /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31                  : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_EnbldChns;

    /* 0x20 : DMA_SoftBReq */
    union
    {
        struct
        {
            uint32_t SoftBReq                       : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_SoftBReq;

    /* 0x24 : DMA_SoftSReq */
    union
    {
        struct
        {
            uint32_t SoftSReq                       : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_SoftSReq;

    /* 0x28 : DMA_SoftLBReq */
    union
    {
        struct
        {
            uint32_t SoftLBReq                      : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_SoftLBReq;

    /* 0x2C : DMA_SoftLSReq */
    union
    {
        struct
        {
            uint32_t SoftLSReq                      : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_SoftLSReq;

    /* 0x30 : DMA_Top_Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t M                              :  1; /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_31                  : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_Top_Config;

    /* 0x34 : DMA_Sync */
    union
    {
        struct
        {
            uint32_t DMA_Sync                       : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_Sync;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[200];

    /* 0x100 : DMA_C0SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C0SrcAddr;

    /* 0x104 : DMA_C0DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C0DstAddr;

    /* 0x108 : DMA_C0LLI */
    union
    {
        struct
        {
            uint32_t LLI                            : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C0LLI;

    /* 0x10C : DMA_C0Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C0Control;

    /* 0x110 : DMA_C0Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19                    :  1; /* [   19],       rsvd,        0x0 */
            uint32_t LLICounter                     : 10; /* [29:20],          r,        0x0 */
            uint32_t reserved_30_31                 :  2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C0Config;

    /* 0x114  reserved */
    uint8_t RESERVED0x114[236];

    /* 0x200 : DMA_C1SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C1SrcAddr;

    /* 0x204 : DMA_C1DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C1DstAddr;

    /* 0x208 : DMA_C1LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C1LLI;

    /* 0x20C : DMA_C1Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C1Control;

    /* 0x210 : DMA_C1Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C1Config;

    /* 0x214  reserved */
    uint8_t RESERVED0x214[236];

    /* 0x300 : DMA_C2SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C2SrcAddr;

    /* 0x304 : DMA_C2DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C2DstAddr;

    /* 0x308 : DMA_C2LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C2LLI;

    /* 0x30C : DMA_C2Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C2Control;

    /* 0x310 : DMA_C2Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C2Config;

    /* 0x314  reserved */
    uint8_t RESERVED0x314[236];

    /* 0x400 : DMA_C3SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C3SrcAddr;

    /* 0x404 : DMA_C3DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C3DstAddr;

    /* 0x408 : DMA_C3LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C3LLI;

    /* 0x40C : DMA_C3Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C3Control;

    /* 0x410 : DMA_C3Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C3Config;

    /* 0x414  reserved */
    uint8_t RESERVED0x414[236];

    /* 0x500 : DMA_C4SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C4SrcAddr;

    /* 0x504 : DMA_C4DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C4DstAddr;

    /* 0x508 : DMA_C4LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C4LLI;

    /* 0x50C : DMA_C4Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C4Control;

    /* 0x510 : DMA_C4Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C4Config;

    /* 0x514  reserved */
    uint8_t RESERVED0x514[236];

    /* 0x600 : DMA_C5SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C5SrcAddr;

    /* 0x604 : DMA_C5DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C5DstAddr;

    /* 0x608 : DMA_C5LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C5LLI;

    /* 0x60C : DMA_C5Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C5Control;

    /* 0x610 : DMA_C5Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C5Config;

    /* 0x614  reserved */
    uint8_t RESERVED0x614[236];

    /* 0x700 : DMA_C6SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C6SrcAddr;

    /* 0x704 : DMA_C6DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C6DstAddr;

    /* 0x708 : DMA_C6LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C6LLI;

    /* 0x70C : DMA_C6Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C6Control;

    /* 0x710 : DMA_C6Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C6Config;

    /* 0x714  reserved */
    uint8_t RESERVED0x714[236];

    /* 0x800 : DMA_C7SrcAddr */
    union
    {
        struct
        {
            uint32_t SrcAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C7SrcAddr;

    /* 0x804 : DMA_C7DstAddr */
    union
    {
        struct
        {
            uint32_t DstAddr                        : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C7DstAddr;

    /* 0x808 : DMA_C7LLI */
    union
    {
        struct
        {
            uint32_t reserved_0_1                   :  2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t LLI                            : 30; /* [31: 2],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C7LLI;

    /* 0x80C : DMA_C7Control */
    union
    {
        struct
        {
            uint32_t TransferSize                   : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize                         :  2; /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode                   :  1; /* [   14],        r/w,        0x0 */
            uint32_t DBSize                         :  2; /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode                   :  1; /* [   17],        r/w,        0x0 */
            uint32_t SWidth                         :  2; /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20                    :  1; /* [   20],       rsvd,        0x0 */
            uint32_t DWidth                         :  2; /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt                        :  2; /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD                       :  1; /* [   25],        r/w,        0x0 */
            uint32_t SI                             :  1; /* [   26],        r/w,        0x1 */
            uint32_t DI                             :  1; /* [   27],        r/w,        0x1 */
            uint32_t Prot                           :  3; /* [30:28],        r/w,        0x0 */
            uint32_t I                              :  1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C7Control;

    /* 0x810 : DMA_C7Config */
    union
    {
        struct
        {
            uint32_t E                              :  1; /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral                  :  5; /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral                  :  5; /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl                      :  3; /* [13:11],        r/w,        0x0 */
            uint32_t IE                             :  1; /* [   14],        r/w,        0x0 */
            uint32_t ITC                            :  1; /* [   15],        r/w,        0x0 */
            uint32_t L                              :  1; /* [   16],        r/w,        0x0 */
            uint32_t A                              :  1; /* [   17],          r,        0x0 */
            uint32_t H                              :  1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19_31                 : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_C7Config;

};
#endif

typedef volatile struct dma_reg dma_reg_t;

/*Following is reg patch*/

/* 0x0 : DMA_SrcAddr */
#define DMA_SRCADDR_OFFSET (0x0)
#define DMA_SRCADDR        DMA_SRCADDR
#define DMA_SRCADDR_POS    (0U)
#define DMA_SRCADDR_LEN    (32U)
#define DMA_SRCADDR_MSK    (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)
#define DMA_SRCADDR_UMSK   (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS))

/* 0x4 : DMA_DstAddr */
#define DMA_DSTADDR_OFFSET (0x4)
#define DMA_DSTADDR        DMA_DSTADDR
#define DMA_DSTADDR_POS    (0U)
#define DMA_DSTADDR_LEN    (32U)
#define DMA_DSTADDR_MSK    (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)
#define DMA_DSTADDR_UMSK   (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS))

/* 0x8 : DMA_LLI */
#define DMA_LLI_OFFSET (0x8)
#define DMA_LLI        DMA_LLI
#define DMA_LLI_POS    (0U)
#define DMA_LLI_LEN    (32U)
#define DMA_LLI_MSK    (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)
#define DMA_LLI_UMSK   (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS))

/* 0xc : DMA_Control */
#define DMA_CONTROL_OFFSET    (0xc)
#define DMA_TRANSFERSIZE      DMA_TRANSFERSIZE
#define DMA_TRANSFERSIZE_POS  (0U)
#define DMA_TRANSFERSIZE_LEN  (12U)
#define DMA_TRANSFERSIZE_MSK  (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)
#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS))
#define DMA_SBSIZE            DMA_SBSIZE
#define DMA_SBSIZE_POS        (12U)
#define DMA_SBSIZE_LEN        (2U)
#define DMA_SBSIZE_MSK        (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)
#define DMA_SBSIZE_UMSK       (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS))
#define DMA_DST_MIN_MODE      DMA_DST_MIN_MODE
#define DMA_DST_MIN_MODE_POS  (14U)
#define DMA_DST_MIN_MODE_LEN  (1U)
#define DMA_DST_MIN_MODE_MSK  (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)
#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS))
#define DMA_DBSIZE            DMA_DBSIZE
#define DMA_DBSIZE_POS        (15U)
#define DMA_DBSIZE_LEN        (2U)
#define DMA_DBSIZE_MSK        (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)
#define DMA_DBSIZE_UMSK       (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS))
#define DMA_DST_ADD_MODE      DMA_DST_ADD_MODE
#define DMA_DST_ADD_MODE_POS  (17U)
#define DMA_DST_ADD_MODE_LEN  (1U)
#define DMA_DST_ADD_MODE_MSK  (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)
#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS))
#define DMA_SWIDTH            DMA_SWIDTH
#define DMA_SWIDTH_POS        (18U)
#define DMA_SWIDTH_LEN        (2U)
#define DMA_SWIDTH_MSK        (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)
#define DMA_SWIDTH_UMSK       (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS))
#define DMA_DWIDTH            DMA_DWIDTH
#define DMA_DWIDTH_POS        (21U)
#define DMA_DWIDTH_LEN        (2U)
#define DMA_DWIDTH_MSK        (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)
#define DMA_DWIDTH_UMSK       (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS))
#define DMA_FIX_CNT           DMA_FIX_CNT
#define DMA_FIX_CNT_POS       (23U)
#define DMA_FIX_CNT_LEN       (2U)
#define DMA_FIX_CNT_MSK       (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)
#define DMA_FIX_CNT_UMSK      (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS))
#define DMA_SLARGERD          DMA_SLARGERD
#define DMA_SLARGERD_POS      (25U)
#define DMA_SLARGERD_LEN      (1U)
#define DMA_SLARGERD_MSK      (((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS)
#define DMA_SLARGERD_UMSK     (~(((1U << DMA_SLARGERD_LEN) - 1) << DMA_SLARGERD_POS))
#define DMA_SI                DMA_SI
#define DMA_SI_POS            (26U)
#define DMA_SI_LEN            (1U)
#define DMA_SI_MSK            (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)
#define DMA_SI_UMSK           (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS))
#define DMA_DI                DMA_DI
#define DMA_DI_POS            (27U)
#define DMA_DI_LEN            (1U)
#define DMA_DI_MSK            (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)
#define DMA_DI_UMSK           (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS))
#define DMA_PROT              DMA_PROT
#define DMA_PROT_POS          (28U)
#define DMA_PROT_LEN          (3U)
#define DMA_PROT_MSK          (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)
#define DMA_PROT_UMSK         (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS))
#define DMA_I                 DMA_I
#define DMA_I_POS             (31U)
#define DMA_I_LEN             (1U)
#define DMA_I_MSK             (((1U << DMA_I_LEN) - 1) << DMA_I_POS)
#define DMA_I_UMSK            (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS))

/* 0x10 : DMA_Config */
#define DMA_CONFIG_OFFSET      (0x10)
#define DMA_E                  DMA_E
#define DMA_E_POS              (0U)
#define DMA_E_LEN              (1U)
#define DMA_E_MSK              (((1U << DMA_E_LEN) - 1) << DMA_E_POS)
#define DMA_E_UMSK             (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS))
#define DMA_SRCPERIPHERAL      DMA_SRCPERIPHERAL
#define DMA_SRCPERIPHERAL_POS  (1U)
#define DMA_SRCPERIPHERAL_LEN  (5U)
#define DMA_SRCPERIPHERAL_MSK  (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)
#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS))
#define DMA_DSTPERIPHERAL      DMA_DSTPERIPHERAL
#define DMA_DSTPERIPHERAL_POS  (6U)
#define DMA_DSTPERIPHERAL_LEN  (5U)
#define DMA_DSTPERIPHERAL_MSK  (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)
#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS))
#define DMA_FLOWCNTRL          DMA_FLOWCNTRL
#define DMA_FLOWCNTRL_POS      (11U)
#define DMA_FLOWCNTRL_LEN      (3U)
#define DMA_FLOWCNTRL_MSK      (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)
#define DMA_FLOWCNTRL_UMSK     (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS))
#define DMA_IE                 DMA_IE
#define DMA_IE_POS             (14U)
#define DMA_IE_LEN             (1U)
#define DMA_IE_MSK             (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)
#define DMA_IE_UMSK            (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS))
#define DMA_ITC                DMA_ITC
#define DMA_ITC_POS            (15U)
#define DMA_ITC_LEN            (1U)
#define DMA_ITC_MSK            (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)
#define DMA_ITC_UMSK           (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS))
#define DMA_L                  DMA_L
#define DMA_L_POS              (16U)
#define DMA_L_LEN              (1U)
#define DMA_L_MSK              (((1U << DMA_L_LEN) - 1) << DMA_L_POS)
#define DMA_L_UMSK             (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS))
#define DMA_A                  DMA_A
#define DMA_A_POS              (17U)
#define DMA_A_LEN              (1U)
#define DMA_A_MSK              (((1U << DMA_A_LEN) - 1) << DMA_A_POS)
#define DMA_A_UMSK             (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS))
#define DMA_H                  DMA_H
#define DMA_H_POS              (18U)
#define DMA_H_LEN              (1U)
#define DMA_H_MSK              (((1U << DMA_H_LEN) - 1) << DMA_H_POS)
#define DMA_H_UMSK             (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS))
#define DMA_LLICOUNTER         DMA_LLICOUNTER
#define DMA_LLICOUNTER_POS     (20U)
#define DMA_LLICOUNTER_LEN     (10U)
#define DMA_LLICOUNTER_MSK     (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)
#define DMA_LLICOUNTER_UMSK    (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS))

struct dma_channel_reg {
    /* 0x0 : DMA_SrcAddr */
    union {
        struct
        {
            uint32_t SrcAddr : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_SrcAddr;

    /* 0x4 : DMA_DstAddr */
    union {
        struct
        {
            uint32_t DstAddr : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_DstAddr;

    /* 0x8 : DMA_LLI */
    union {
        struct
        {
            uint32_t LLI : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_LLI;

    /* 0xc : DMA_Control */
    union {
        struct DMA_Control_Reg {
            uint32_t TransferSize : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t SBSize       : 2;  /* [13:12],        r/w,        0x1 */
            uint32_t dst_min_mode : 1;  /* [   14],        r/w,        0x0 */
            uint32_t DBSize       : 2;  /* [16:15],        r/w,        0x1 */
            uint32_t dst_add_mode : 1;  /* [   17],        r/w,        0x0 */
            uint32_t SWidth       : 2;  /* [19:18],        r/w,        0x2 */
            uint32_t reserved_20  : 1;  /* [   20],       rsvd,        0x0 */
            uint32_t DWidth       : 2;  /* [22:21],        r/w,        0x2 */
            uint32_t fix_cnt      : 2;  /* [24:23],        r/w,        0x0 */
            uint32_t SLargerD     : 1;  /* [   25],        r/w,        0x0 */
            uint32_t SI           : 1;  /* [   26],        r/w,        0x1 */
            uint32_t DI           : 1;  /* [   27],        r/w,        0x1 */
            uint32_t Prot         : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t I            : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_Control;

    /* 0x10 : DMA_Config */
    union {
        struct
        {
            uint32_t E              : 1;  /* [    0],        r/w,        0x0 */
            uint32_t SrcPeripheral  : 5;  /* [ 5: 1],        r/w,        0x0 */
            uint32_t DstPeripheral  : 5;  /* [10: 6],        r/w,        0x0 */
            uint32_t FlowCntrl      : 3;  /* [13:11],        r/w,        0x0 */
            uint32_t IE             : 1;  /* [   14],        r/w,        0x0 */
            uint32_t ITC            : 1;  /* [   15],        r/w,        0x0 */
            uint32_t L              : 1;  /* [   16],        r/w,        0x0 */
            uint32_t A              : 1;  /* [   17],          r,        0x0 */
            uint32_t H              : 1;  /* [   18],        r/w,        0x0 */
            uint32_t reserved_19    : 1;  /* [   19],       rsvd,        0x0 */
            uint32_t LLICounter     : 10; /* [29:20],          r,        0x0 */
            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } DMA_Config;
};

typedef volatile struct dma_channel_reg dma_channel_reg_t;

#define DMA_CHANNEL_OFFSET 0x100

#endif /* __DMA_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_ctrl_reg.h
================================================
/**
  ******************************************************************************
  * @file    ef_ctrl_reg.h
  * @version V1.2
  * @date    2020-04-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __EF_CTRL_REG_H__
#define __EF_CTRL_REG_H__

#include "bl702.h"

/* 0x800 : ef_if_ctrl_0 */
#define EF_CTRL_EF_IF_CTRL_0_OFFSET           (0x800)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE      EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS  (0U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN  (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK  (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE         EF_CTRL_EF_IF_0_AUTOLOAD_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS     (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN     (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK     (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK    (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
#define EF_CTRL_EF_IF_0_BUSY                  EF_CTRL_EF_IF_0_BUSY
#define EF_CTRL_EF_IF_0_BUSY_POS              (2U)
#define EF_CTRL_EF_IF_0_BUSY_LEN              (1U)
#define EF_CTRL_EF_IF_0_BUSY_MSK              (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
#define EF_CTRL_EF_IF_0_BUSY_UMSK             (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
#define EF_CTRL_EF_IF_0_RW                    EF_CTRL_EF_IF_0_RW
#define EF_CTRL_EF_IF_0_RW_POS                (3U)
#define EF_CTRL_EF_IF_0_RW_LEN                (1U)
#define EF_CTRL_EF_IF_0_RW_MSK                (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
#define EF_CTRL_EF_IF_0_RW_UMSK               (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
#define EF_CTRL_EF_IF_0_TRIG                  EF_CTRL_EF_IF_0_TRIG
#define EF_CTRL_EF_IF_0_TRIG_POS              (4U)
#define EF_CTRL_EF_IF_0_TRIG_LEN              (1U)
#define EF_CTRL_EF_IF_0_TRIG_MSK              (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
#define EF_CTRL_EF_IF_0_TRIG_UMSK             (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
#define EF_CTRL_EF_IF_0_MANUAL_EN             EF_CTRL_EF_IF_0_MANUAL_EN
#define EF_CTRL_EF_IF_0_MANUAL_EN_POS         (5U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN         (1U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK         (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
#define EF_CTRL_EF_IF_0_CYC_MODIFY            EF_CTRL_EF_IF_0_CYC_MODIFY
#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS        (6U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN        (1U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK        (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK       (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL          EF_CTRL_EF_CLK_SAHB_DATA_SEL
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS      (7U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN      (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK      (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK     (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CTRL          EF_CTRL_EF_IF_PROT_CODE_CTRL
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS      (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN      (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK      (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK     (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
#define EF_CTRL_EF_IF_POR_DIG                 EF_CTRL_EF_IF_POR_DIG
#define EF_CTRL_EF_IF_POR_DIG_POS             (16U)
#define EF_CTRL_EF_IF_POR_DIG_LEN             (1U)
#define EF_CTRL_EF_IF_POR_DIG_MSK             (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
#define EF_CTRL_EF_IF_POR_DIG_UMSK            (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE         EF_CTRL_EF_CLK_SAHB_DATA_GATE
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS     (17U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN     (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK     (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK    (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
#define EF_CTRL_EF_IF_AUTO_RD_EN              EF_CTRL_EF_IF_AUTO_RD_EN
#define EF_CTRL_EF_IF_AUTO_RD_EN_POS          (18U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN          (1U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK          (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK         (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK         EF_CTRL_EF_IF_CYC_MODIFY_LOCK
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS     (19U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN     (1U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK     (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK    (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
#define EF_CTRL_EF_IF_0_INT                   EF_CTRL_EF_IF_0_INT
#define EF_CTRL_EF_IF_0_INT_POS               (20U)
#define EF_CTRL_EF_IF_0_INT_LEN               (1U)
#define EF_CTRL_EF_IF_0_INT_MSK               (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
#define EF_CTRL_EF_IF_0_INT_UMSK              (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
#define EF_CTRL_EF_IF_0_INT_CLR               EF_CTRL_EF_IF_0_INT_CLR
#define EF_CTRL_EF_IF_0_INT_CLR_POS           (21U)
#define EF_CTRL_EF_IF_0_INT_CLR_LEN           (1U)
#define EF_CTRL_EF_IF_0_INT_CLR_MSK           (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
#define EF_CTRL_EF_IF_0_INT_CLR_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
#define EF_CTRL_EF_IF_0_INT_SET               EF_CTRL_EF_IF_0_INT_SET
#define EF_CTRL_EF_IF_0_INT_SET_POS           (22U)
#define EF_CTRL_EF_IF_0_INT_SET_LEN           (1U)
#define EF_CTRL_EF_IF_0_INT_SET_MSK           (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
#define EF_CTRL_EF_IF_0_INT_SET_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CYC           EF_CTRL_EF_IF_PROT_CODE_CYC
#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS       (24U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN       (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK       (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK      (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))

/* 0x804 : ef_if_cyc_0 */
#define EF_CTRL_EF_IF_CYC_0_OFFSET     (0x804)
#define EF_CTRL_EF_IF_CYC_RD_DMY       EF_CTRL_EF_IF_CYC_RD_DMY
#define EF_CTRL_EF_IF_CYC_RD_DMY_POS   (0U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN   (6U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
#define EF_CTRL_EF_IF_CYC_RD_DAT       EF_CTRL_EF_IF_CYC_RD_DAT
#define EF_CTRL_EF_IF_CYC_RD_DAT_POS   (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN   (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
#define EF_CTRL_EF_IF_CYC_RD_ADR       EF_CTRL_EF_IF_CYC_RD_ADR
#define EF_CTRL_EF_IF_CYC_RD_ADR_POS   (12U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN   (6U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
#define EF_CTRL_EF_IF_CYC_CS           EF_CTRL_EF_IF_CYC_CS
#define EF_CTRL_EF_IF_CYC_CS_POS       (18U)
#define EF_CTRL_EF_IF_CYC_CS_LEN       (6U)
#define EF_CTRL_EF_IF_CYC_CS_MSK       (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
#define EF_CTRL_EF_IF_CYC_CS_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_S      EF_CTRL_EF_IF_CYC_PD_CS_S
#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS  (24U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN  (8U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))

/* 0x808 : ef_if_cyc_1 */
#define EF_CTRL_EF_IF_CYC_1_OFFSET     (0x808)
#define EF_CTRL_EF_IF_CYC_PI           EF_CTRL_EF_IF_CYC_PI
#define EF_CTRL_EF_IF_CYC_PI_POS       (0U)
#define EF_CTRL_EF_IF_CYC_PI_LEN       (6U)
#define EF_CTRL_EF_IF_CYC_PI_MSK       (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
#define EF_CTRL_EF_IF_CYC_PI_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
#define EF_CTRL_EF_IF_CYC_PP           EF_CTRL_EF_IF_CYC_PP
#define EF_CTRL_EF_IF_CYC_PP_POS       (6U)
#define EF_CTRL_EF_IF_CYC_PP_LEN       (8U)
#define EF_CTRL_EF_IF_CYC_PP_MSK       (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
#define EF_CTRL_EF_IF_CYC_PP_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
#define EF_CTRL_EF_IF_CYC_WR_ADR       EF_CTRL_EF_IF_CYC_WR_ADR
#define EF_CTRL_EF_IF_CYC_WR_ADR_POS   (14U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN   (6U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
#define EF_CTRL_EF_IF_CYC_PS_CS        EF_CTRL_EF_IF_CYC_PS_CS
#define EF_CTRL_EF_IF_CYC_PS_CS_POS    (20U)
#define EF_CTRL_EF_IF_CYC_PS_CS_LEN    (6U)
#define EF_CTRL_EF_IF_CYC_PS_CS_MSK    (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK   (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_H      EF_CTRL_EF_IF_CYC_PD_CS_H
#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS  (26U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN  (6U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))

/* 0x80C : ef_if_0_manual */
#define EF_CTRL_EF_IF_0_MANUAL_OFFSET       (0x80C)
#define EF_CTRL_EF_IF_A                     EF_CTRL_EF_IF_A
#define EF_CTRL_EF_IF_A_POS                 (0U)
#define EF_CTRL_EF_IF_A_LEN                 (10U)
#define EF_CTRL_EF_IF_A_MSK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
#define EF_CTRL_EF_IF_A_UMSK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
#define EF_CTRL_EF_IF_PD                    EF_CTRL_EF_IF_PD
#define EF_CTRL_EF_IF_PD_POS                (10U)
#define EF_CTRL_EF_IF_PD_LEN                (1U)
#define EF_CTRL_EF_IF_PD_MSK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
#define EF_CTRL_EF_IF_PD_UMSK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
#define EF_CTRL_EF_IF_PS                    EF_CTRL_EF_IF_PS
#define EF_CTRL_EF_IF_PS_POS                (11U)
#define EF_CTRL_EF_IF_PS_LEN                (1U)
#define EF_CTRL_EF_IF_PS_MSK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
#define EF_CTRL_EF_IF_PS_UMSK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
#define EF_CTRL_EF_IF_STROBE                EF_CTRL_EF_IF_STROBE
#define EF_CTRL_EF_IF_STROBE_POS            (12U)
#define EF_CTRL_EF_IF_STROBE_LEN            (1U)
#define EF_CTRL_EF_IF_STROBE_MSK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
#define EF_CTRL_EF_IF_STROBE_UMSK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
#define EF_CTRL_EF_IF_PGENB                 EF_CTRL_EF_IF_PGENB
#define EF_CTRL_EF_IF_PGENB_POS             (13U)
#define EF_CTRL_EF_IF_PGENB_LEN             (1U)
#define EF_CTRL_EF_IF_PGENB_MSK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
#define EF_CTRL_EF_IF_PGENB_UMSK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
#define EF_CTRL_EF_IF_LOAD                  EF_CTRL_EF_IF_LOAD
#define EF_CTRL_EF_IF_LOAD_POS              (14U)
#define EF_CTRL_EF_IF_LOAD_LEN              (1U)
#define EF_CTRL_EF_IF_LOAD_MSK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
#define EF_CTRL_EF_IF_LOAD_UMSK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
#define EF_CTRL_EF_IF_CSB                   EF_CTRL_EF_IF_CSB
#define EF_CTRL_EF_IF_CSB_POS               (15U)
#define EF_CTRL_EF_IF_CSB_LEN               (1U)
#define EF_CTRL_EF_IF_CSB_MSK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
#define EF_CTRL_EF_IF_CSB_UMSK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
#define EF_CTRL_EF_IF_0_Q                   EF_CTRL_EF_IF_0_Q
#define EF_CTRL_EF_IF_0_Q_POS               (16U)
#define EF_CTRL_EF_IF_0_Q_LEN               (8U)
#define EF_CTRL_EF_IF_0_Q_MSK               (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
#define EF_CTRL_EF_IF_0_Q_UMSK              (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL      EF_CTRL_EF_IF_PROT_CODE_MANUAL
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS  (24U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN  (8U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))

/* 0x810 : ef_if_0_status */
#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
#define EF_CTRL_EF_IF_0_STATUS        EF_CTRL_EF_IF_0_STATUS
#define EF_CTRL_EF_IF_0_STATUS_POS    (0U)
#define EF_CTRL_EF_IF_0_STATUS_LEN    (32U)
#define EF_CTRL_EF_IF_0_STATUS_MSK    (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
#define EF_CTRL_EF_IF_0_STATUS_UMSK   (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))

/* 0x814 : ef_if_cfg_0 */
#define EF_CTRL_EF_IF_CFG_0_OFFSET         (0x814)
#define EF_CTRL_EF_IF_SF_AES_MODE          EF_CTRL_EF_IF_SF_AES_MODE
#define EF_CTRL_EF_IF_SF_AES_MODE_POS      (0U)
#define EF_CTRL_EF_IF_SF_AES_MODE_LEN      (2U)
#define EF_CTRL_EF_IF_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE      EF_CTRL_EF_IF_SBOOT_SIGN_MODE
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS  (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN  (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_EN             EF_CTRL_EF_IF_SBOOT_EN
#define EF_CTRL_EF_IF_SBOOT_EN_POS         (4U)
#define EF_CTRL_EF_IF_SBOOT_EN_LEN         (2U)
#define EF_CTRL_EF_IF_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
#define EF_CTRL_EF_IF_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
#define EF_CTRL_EF_IF_CPU1_ENC_EN          EF_CTRL_EF_IF_CPU1_ENC_EN
#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS      (6U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN      (1U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_IF_CPU0_ENC_EN          EF_CTRL_EF_IF_CPU0_ENC_EN
#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS      (7U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN      (1U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_IF_BOOT_SEL             EF_CTRL_EF_IF_BOOT_SEL
#define EF_CTRL_EF_IF_BOOT_SEL_POS         (8U)
#define EF_CTRL_EF_IF_BOOT_SEL_LEN         (4U)
#define EF_CTRL_EF_IF_BOOT_SEL_MSK         (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)
#define EF_CTRL_EF_IF_BOOT_SEL_UMSK        (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS))
#define EF_CTRL_EF_IF_SF_KEY_0_SEL         EF_CTRL_EF_IF_SF_KEY_0_SEL
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS     (12U)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN     (2U)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)
#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS))
#define EF_CTRL_EF_IF_SDU_DIS              EF_CTRL_EF_IF_SDU_DIS
#define EF_CTRL_EF_IF_SDU_DIS_POS          (14U)
#define EF_CTRL_EF_IF_SDU_DIS_LEN          (1U)
#define EF_CTRL_EF_IF_SDU_DIS_MSK          (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
#define EF_CTRL_EF_IF_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
#define EF_CTRL_EF_IF_BLE_DIS              EF_CTRL_EF_IF_BLE_DIS
#define EF_CTRL_EF_IF_BLE_DIS_POS          (15U)
#define EF_CTRL_EF_IF_BLE_DIS_LEN          (1U)
#define EF_CTRL_EF_IF_BLE_DIS_MSK          (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)
#define EF_CTRL_EF_IF_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS))
#define EF_CTRL_EF_IF_WIFI_DIS             EF_CTRL_EF_IF_WIFI_DIS
#define EF_CTRL_EF_IF_WIFI_DIS_POS         (16U)
#define EF_CTRL_EF_IF_WIFI_DIS_LEN         (1U)
#define EF_CTRL_EF_IF_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
#define EF_CTRL_EF_IF_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
#define EF_CTRL_EF_IF_0_KEY_ENC_EN         EF_CTRL_EF_IF_0_KEY_ENC_EN
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS     (17U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN     (1U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_IF_CAM_DIS              EF_CTRL_EF_IF_CAM_DIS
#define EF_CTRL_EF_IF_CAM_DIS_POS          (18U)
#define EF_CTRL_EF_IF_CAM_DIS_LEN          (1U)
#define EF_CTRL_EF_IF_CAM_DIS_MSK          (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
#define EF_CTRL_EF_IF_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
#define EF_CTRL_EF_IF_M154_DIS             EF_CTRL_EF_IF_M154_DIS
#define EF_CTRL_EF_IF_M154_DIS_POS         (19U)
#define EF_CTRL_EF_IF_M154_DIS_LEN         (1U)
#define EF_CTRL_EF_IF_M154_DIS_MSK         (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
#define EF_CTRL_EF_IF_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
#define EF_CTRL_EF_IF_CPU1_DIS             EF_CTRL_EF_IF_CPU1_DIS
#define EF_CTRL_EF_IF_CPU1_DIS_POS         (20U)
#define EF_CTRL_EF_IF_CPU1_DIS_LEN         (1U)
#define EF_CTRL_EF_IF_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
#define EF_CTRL_EF_IF_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS      EF_CTRL_EF_IF_CPU_RST_DBG_DIS
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS  (21U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN  (1U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_IF_SE_DBG_DIS           EF_CTRL_EF_IF_SE_DBG_DIS
#define EF_CTRL_EF_IF_SE_DBG_DIS_POS       (22U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN       (1U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS        EF_CTRL_EF_IF_EFUSE_DBG_DIS
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS    (23U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN    (1U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS       EF_CTRL_EF_IF_DBG_JTAG_1_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS   (24U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN   (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS       EF_CTRL_EF_IF_DBG_JTAG_0_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS   (26U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN   (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_IF_DBG_MODE             EF_CTRL_EF_IF_DBG_MODE
#define EF_CTRL_EF_IF_DBG_MODE_POS         (28U)
#define EF_CTRL_EF_IF_DBG_MODE_LEN         (4U)
#define EF_CTRL_EF_IF_DBG_MODE_MSK         (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
#define EF_CTRL_EF_IF_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))

/* 0x818 : ef_sw_cfg_0 */
#define EF_CTRL_EF_SW_CFG_0_OFFSET         (0x818)
#define EF_CTRL_EF_SW_SF_AES_MODE          EF_CTRL_EF_SW_SF_AES_MODE
#define EF_CTRL_EF_SW_SF_AES_MODE_POS      (0U)
#define EF_CTRL_EF_SW_SF_AES_MODE_LEN      (2U)
#define EF_CTRL_EF_SW_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE      EF_CTRL_EF_SW_SBOOT_SIGN_MODE
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS  (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN  (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_EN             EF_CTRL_EF_SW_SBOOT_EN
#define EF_CTRL_EF_SW_SBOOT_EN_POS         (4U)
#define EF_CTRL_EF_SW_SBOOT_EN_LEN         (2U)
#define EF_CTRL_EF_SW_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
#define EF_CTRL_EF_SW_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
#define EF_CTRL_EF_SW_CPU1_ENC_EN          EF_CTRL_EF_SW_CPU1_ENC_EN
#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS      (6U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN      (1U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_SW_CPU0_ENC_EN          EF_CTRL_EF_SW_CPU0_ENC_EN
#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS      (7U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN      (1U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_SW_SF_KEY_0_SEL         EF_CTRL_EF_SW_SF_KEY_0_SEL
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS     (12U)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN     (2U)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)
#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS))
#define EF_CTRL_EF_SW_SDU_DIS              EF_CTRL_EF_SW_SDU_DIS
#define EF_CTRL_EF_SW_SDU_DIS_POS          (14U)
#define EF_CTRL_EF_SW_SDU_DIS_LEN          (1U)
#define EF_CTRL_EF_SW_SDU_DIS_MSK          (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
#define EF_CTRL_EF_SW_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
#define EF_CTRL_EF_SW_BLE_DIS              EF_CTRL_EF_SW_BLE_DIS
#define EF_CTRL_EF_SW_BLE_DIS_POS          (15U)
#define EF_CTRL_EF_SW_BLE_DIS_LEN          (1U)
#define EF_CTRL_EF_SW_BLE_DIS_MSK          (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)
#define EF_CTRL_EF_SW_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS))
#define EF_CTRL_EF_SW_WIFI_DIS             EF_CTRL_EF_SW_WIFI_DIS
#define EF_CTRL_EF_SW_WIFI_DIS_POS         (16U)
#define EF_CTRL_EF_SW_WIFI_DIS_LEN         (1U)
#define EF_CTRL_EF_SW_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
#define EF_CTRL_EF_SW_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
#define EF_CTRL_EF_SW_0_KEY_ENC_EN         EF_CTRL_EF_SW_0_KEY_ENC_EN
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS     (17U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN     (1U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_SW_CAM_DIS              EF_CTRL_EF_SW_CAM_DIS
#define EF_CTRL_EF_SW_CAM_DIS_POS          (18U)
#define EF_CTRL_EF_SW_CAM_DIS_LEN          (1U)
#define EF_CTRL_EF_SW_CAM_DIS_MSK          (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
#define EF_CTRL_EF_SW_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
#define EF_CTRL_EF_SW_M154_DIS             EF_CTRL_EF_SW_M154_DIS
#define EF_CTRL_EF_SW_M154_DIS_POS         (19U)
#define EF_CTRL_EF_SW_M154_DIS_LEN         (1U)
#define EF_CTRL_EF_SW_M154_DIS_MSK         (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
#define EF_CTRL_EF_SW_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
#define EF_CTRL_EF_SW_CPU1_DIS             EF_CTRL_EF_SW_CPU1_DIS
#define EF_CTRL_EF_SW_CPU1_DIS_POS         (20U)
#define EF_CTRL_EF_SW_CPU1_DIS_LEN         (1U)
#define EF_CTRL_EF_SW_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
#define EF_CTRL_EF_SW_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS      EF_CTRL_EF_SW_CPU_RST_DBG_DIS
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS  (21U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN  (1U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_SW_SE_DBG_DIS           EF_CTRL_EF_SW_SE_DBG_DIS
#define EF_CTRL_EF_SW_SE_DBG_DIS_POS       (22U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN       (1U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS        EF_CTRL_EF_SW_EFUSE_DBG_DIS
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS    (23U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN    (1U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS       EF_CTRL_EF_SW_DBG_JTAG_1_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS   (24U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN   (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS       EF_CTRL_EF_SW_DBG_JTAG_0_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS   (26U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN   (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_SW_DBG_MODE             EF_CTRL_EF_SW_DBG_MODE
#define EF_CTRL_EF_SW_DBG_MODE_POS         (28U)
#define EF_CTRL_EF_SW_DBG_MODE_LEN         (4U)
#define EF_CTRL_EF_SW_DBG_MODE_MSK         (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
#define EF_CTRL_EF_SW_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))

/* 0x81C : ef_reserved */
#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
#define EF_CTRL_EF_RESERVED        EF_CTRL_EF_RESERVED
#define EF_CTRL_EF_RESERVED_POS    (0U)
#define EF_CTRL_EF_RESERVED_LEN    (32U)
#define EF_CTRL_EF_RESERVED_MSK    (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
#define EF_CTRL_EF_RESERVED_UMSK   (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))

/* 0x820 : ef_if_ana_trim_0 */
#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
#define EF_CTRL_EF_IF_ANA_TRIM_0        EF_CTRL_EF_IF_ANA_TRIM_0
#define EF_CTRL_EF_IF_ANA_TRIM_0_POS    (0U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN    (32U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK    (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)
#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK   (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS))

/* 0x824 : ef_if_sw_usage_0 */
#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
#define EF_CTRL_EF_IF_SW_USAGE_0        EF_CTRL_EF_IF_SW_USAGE_0
#define EF_CTRL_EF_IF_SW_USAGE_0_POS    (0U)
#define EF_CTRL_EF_IF_SW_USAGE_0_LEN    (32U)
#define EF_CTRL_EF_IF_SW_USAGE_0_MSK    (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK   (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))

/* 0xA00 : ef_crc_ctrl_0 */
#define EF_CTRL_EF_CRC_CTRL_0_OFFSET    (0xA00)
#define EF_CTRL_EF_CRC_BUSY             EF_CTRL_EF_CRC_BUSY
#define EF_CTRL_EF_CRC_BUSY_POS         (0U)
#define EF_CTRL_EF_CRC_BUSY_LEN         (1U)
#define EF_CTRL_EF_CRC_BUSY_MSK         (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
#define EF_CTRL_EF_CRC_BUSY_UMSK        (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
#define EF_CTRL_EF_CRC_TRIG             EF_CTRL_EF_CRC_TRIG
#define EF_CTRL_EF_CRC_TRIG_POS         (1U)
#define EF_CTRL_EF_CRC_TRIG_LEN         (1U)
#define EF_CTRL_EF_CRC_TRIG_MSK         (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
#define EF_CTRL_EF_CRC_TRIG_UMSK        (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
#define EF_CTRL_EF_CRC_EN               EF_CTRL_EF_CRC_EN
#define EF_CTRL_EF_CRC_EN_POS           (2U)
#define EF_CTRL_EF_CRC_EN_LEN           (1U)
#define EF_CTRL_EF_CRC_EN_MSK           (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
#define EF_CTRL_EF_CRC_EN_UMSK          (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
#define EF_CTRL_EF_CRC_MODE             EF_CTRL_EF_CRC_MODE
#define EF_CTRL_EF_CRC_MODE_POS         (3U)
#define EF_CTRL_EF_CRC_MODE_LEN         (1U)
#define EF_CTRL_EF_CRC_MODE_MSK         (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
#define EF_CTRL_EF_CRC_MODE_UMSK        (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
#define EF_CTRL_EF_CRC_ERROR            EF_CTRL_EF_CRC_ERROR
#define EF_CTRL_EF_CRC_ERROR_POS        (4U)
#define EF_CTRL_EF_CRC_ERROR_LEN        (1U)
#define EF_CTRL_EF_CRC_ERROR_MSK        (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
#define EF_CTRL_EF_CRC_ERROR_UMSK       (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
#define EF_CTRL_EF_CRC_DOUT_INV_EN      EF_CTRL_EF_CRC_DOUT_INV_EN
#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS  (5U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN  (1U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
#define EF_CTRL_EF_CRC_DOUT_ENDIAN      EF_CTRL_EF_CRC_DOUT_ENDIAN
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS  (6U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN  (1U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
#define EF_CTRL_EF_CRC_DIN_ENDIAN       EF_CTRL_EF_CRC_DIN_ENDIAN
#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS   (7U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN   (1U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK   (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK  (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
#define EF_CTRL_EF_CRC_INT              EF_CTRL_EF_CRC_INT
#define EF_CTRL_EF_CRC_INT_POS          (8U)
#define EF_CTRL_EF_CRC_INT_LEN          (1U)
#define EF_CTRL_EF_CRC_INT_MSK          (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
#define EF_CTRL_EF_CRC_INT_UMSK         (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
#define EF_CTRL_EF_CRC_INT_CLR          EF_CTRL_EF_CRC_INT_CLR
#define EF_CTRL_EF_CRC_INT_CLR_POS      (9U)
#define EF_CTRL_EF_CRC_INT_CLR_LEN      (1U)
#define EF_CTRL_EF_CRC_INT_CLR_MSK      (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
#define EF_CTRL_EF_CRC_INT_CLR_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
#define EF_CTRL_EF_CRC_INT_SET          EF_CTRL_EF_CRC_INT_SET
#define EF_CTRL_EF_CRC_INT_SET_POS      (10U)
#define EF_CTRL_EF_CRC_INT_SET_LEN      (1U)
#define EF_CTRL_EF_CRC_INT_SET_MSK      (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
#define EF_CTRL_EF_CRC_INT_SET_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
#define EF_CTRL_EF_CRC_LOCK             EF_CTRL_EF_CRC_LOCK
#define EF_CTRL_EF_CRC_LOCK_POS         (11U)
#define EF_CTRL_EF_CRC_LOCK_LEN         (1U)
#define EF_CTRL_EF_CRC_LOCK_MSK         (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
#define EF_CTRL_EF_CRC_LOCK_UMSK        (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
#define EF_CTRL_EF_CRC_SLP_N            EF_CTRL_EF_CRC_SLP_N
#define EF_CTRL_EF_CRC_SLP_N_POS        (16U)
#define EF_CTRL_EF_CRC_SLP_N_LEN        (16U)
#define EF_CTRL_EF_CRC_SLP_N_MSK        (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
#define EF_CTRL_EF_CRC_SLP_N_UMSK       (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))

/* 0xA04 : ef_crc_ctrl_1 */
#define EF_CTRL_EF_CRC_CTRL_1_OFFSET  (0xA04)
#define EF_CTRL_EF_CRC_DATA_0_EN      EF_CTRL_EF_CRC_DATA_0_EN
#define EF_CTRL_EF_CRC_DATA_0_EN_POS  (0U)
#define EF_CTRL_EF_CRC_DATA_0_EN_LEN  (32U)
#define EF_CTRL_EF_CRC_DATA_0_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))

/* 0xA08 : ef_crc_ctrl_2 */
#define EF_CTRL_EF_CRC_CTRL_2_OFFSET  (0xA08)
#define EF_CTRL_EF_CRC_DATA_1_EN      EF_CTRL_EF_CRC_DATA_1_EN
#define EF_CTRL_EF_CRC_DATA_1_EN_POS  (0U)
#define EF_CTRL_EF_CRC_DATA_1_EN_LEN  (32U)
#define EF_CTRL_EF_CRC_DATA_1_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))

/* 0xA0C : ef_crc_ctrl_3 */
#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
#define EF_CTRL_EF_CRC_IV            EF_CTRL_EF_CRC_IV
#define EF_CTRL_EF_CRC_IV_POS        (0U)
#define EF_CTRL_EF_CRC_IV_LEN        (32U)
#define EF_CTRL_EF_CRC_IV_MSK        (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
#define EF_CTRL_EF_CRC_IV_UMSK       (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))

/* 0xA10 : ef_crc_ctrl_4 */
#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
#define EF_CTRL_EF_CRC_GOLDEN        EF_CTRL_EF_CRC_GOLDEN
#define EF_CTRL_EF_CRC_GOLDEN_POS    (0U)
#define EF_CTRL_EF_CRC_GOLDEN_LEN    (32U)
#define EF_CTRL_EF_CRC_GOLDEN_MSK    (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
#define EF_CTRL_EF_CRC_GOLDEN_UMSK   (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))

/* 0xA14 : ef_crc_ctrl_5 */
#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
#define EF_CTRL_EF_CRC_DOUT          EF_CTRL_EF_CRC_DOUT
#define EF_CTRL_EF_CRC_DOUT_POS      (0U)
#define EF_CTRL_EF_CRC_DOUT_LEN      (32U)
#define EF_CTRL_EF_CRC_DOUT_MSK      (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
#define EF_CTRL_EF_CRC_DOUT_UMSK     (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))

struct ef_ctrl_reg {
    /* 0x0  reserved */
    uint8_t RESERVED0x0[2048];

    /* 0x800 : ef_if_ctrl_0 */
    union {
        struct
        {
            uint32_t ef_if_0_autoload_p1_done : 1; /* [    0],          r,        0x1 */
            uint32_t ef_if_0_autoload_done    : 1; /* [    1],          r,        0x1 */
            uint32_t ef_if_0_busy             : 1; /* [    2],          r,        0x0 */
            uint32_t ef_if_0_rw               : 1; /* [    3],        r/w,        0x0 */
            uint32_t ef_if_0_trig             : 1; /* [    4],        r/w,        0x0 */
            uint32_t ef_if_0_manual_en        : 1; /* [    5],        r/w,        0x0 */
            uint32_t ef_if_0_cyc_modify       : 1; /* [    6],        r/w,        0x0 */
            uint32_t ef_clk_sahb_data_sel     : 1; /* [    7],        r/w,        0x0 */
            uint32_t ef_if_prot_code_ctrl     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t ef_if_por_dig            : 1; /* [   16],        r/w,        0x0 */
            uint32_t ef_clk_sahb_data_gate    : 1; /* [   17],        r/w,        0x0 */
            uint32_t ef_if_auto_rd_en         : 1; /* [   18],        r/w,        0x1 */
            uint32_t ef_if_cyc_modify_lock    : 1; /* [   19],        r/w,        0x0 */
            uint32_t ef_if_0_int              : 1; /* [   20],          r,        0x0 */
            uint32_t ef_if_0_int_clr          : 1; /* [   21],        r/w,        0x1 */
            uint32_t ef_if_0_int_set          : 1; /* [   22],        r/w,        0x0 */
            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
            uint32_t ef_if_prot_code_cyc      : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_ctrl_0;

    /* 0x804 : ef_if_cyc_0 */
    union {
        struct
        {
            uint32_t ef_if_cyc_rd_dmy  : 6; /* [ 5: 0],        r/w,        0x0 */
            uint32_t ef_if_cyc_rd_dat  : 6; /* [11: 6],        r/w,        0x1 */
            uint32_t ef_if_cyc_rd_adr  : 6; /* [17:12],        r/w,        0x0 */
            uint32_t ef_if_cyc_cs      : 6; /* [23:18],        r/w,        0x0 */
            uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24],        r/w,       0x16 */
        } BF;
        uint32_t WORD;
    } ef_if_cyc_0;

    /* 0x808 : ef_if_cyc_1 */
    union {
        struct
        {
            uint32_t ef_if_cyc_pi      : 6; /* [ 5: 0],        r/w,        0x9 */
            uint32_t ef_if_cyc_pp      : 8; /* [13: 6],        r/w,       0x98 */
            uint32_t ef_if_cyc_wr_adr  : 6; /* [19:14],        r/w,        0x1 */
            uint32_t ef_if_cyc_ps_cs   : 6; /* [25:20],        r/w,        0x2 */
            uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_cyc_1;

    /* 0x80C : ef_if_0_manual */
    union {
        struct
        {
            uint32_t ef_if_a                : 10; /* [ 9: 0],        r/w,        0x0 */
            uint32_t ef_if_pd               : 1;  /* [   10],        r/w,        0x1 */
            uint32_t ef_if_ps               : 1;  /* [   11],        r/w,        0x0 */
            uint32_t ef_if_strobe           : 1;  /* [   12],        r/w,        0x0 */
            uint32_t ef_if_pgenb            : 1;  /* [   13],        r/w,        0x1 */
            uint32_t ef_if_load             : 1;  /* [   14],        r/w,        0x1 */
            uint32_t ef_if_csb              : 1;  /* [   15],        r/w,        0x1 */
            uint32_t ef_if_0_q              : 8;  /* [23:16],          r,        0x0 */
            uint32_t ef_if_prot_code_manual : 8;  /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_0_manual;

    /* 0x810 : ef_if_0_status */
    union {
        struct
        {
            uint32_t ef_if_0_status : 32; /* [31: 0],          r,     0xe400 */
        } BF;
        uint32_t WORD;
    } ef_if_0_status;

    /* 0x814 : ef_if_cfg_0 */
    union {
        struct
        {
            uint32_t ef_if_sf_aes_mode     : 2; /* [ 1: 0],          r,        0x0 */
            uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2],          r,        0x0 */
            uint32_t ef_if_sboot_en        : 2; /* [ 5: 4],          r,        0x0 */
            uint32_t ef_if_cpu1_enc_en     : 1; /* [    6],          r,        0x0 */
            uint32_t ef_if_cpu0_enc_en     : 1; /* [    7],          r,        0x0 */
            uint32_t ef_if_boot_sel        : 4; /* [11: 8],          r,        0x0 */
            uint32_t ef_if_sf_key_0_sel    : 2; /* [13:12],          r,        0x0 */
            uint32_t ef_if_sdu_dis         : 1; /* [   14],          r,        0x0 */
            uint32_t ef_if_ble_dis         : 1; /* [   15],          r,        0x0 */
            uint32_t ef_if_wifi_dis        : 1; /* [   16],          r,        0x0 */
            uint32_t ef_if_0_key_enc_en    : 1; /* [   17],          r,        0x0 */
            uint32_t ef_if_cam_dis         : 1; /* [   18],          r,        0x0 */
            uint32_t ef_if_m154_dis        : 1; /* [   19],          r,        0x0 */
            uint32_t ef_if_cpu1_dis        : 1; /* [   20],          r,        0x0 */
            uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [   21],          r,        0x0 */
            uint32_t ef_if_se_dbg_dis      : 1; /* [   22],          r,        0x0 */
            uint32_t ef_if_efuse_dbg_dis   : 1; /* [   23],          r,        0x0 */
            uint32_t ef_if_dbg_jtag_1_dis  : 2; /* [25:24],          r,        0x0 */
            uint32_t ef_if_dbg_jtag_0_dis  : 2; /* [27:26],          r,        0x0 */
            uint32_t ef_if_dbg_mode        : 4; /* [31:28],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_cfg_0;

    /* 0x818 : ef_sw_cfg_0 */
    union {
        struct
        {
            uint32_t ef_sw_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t ef_sw_sboot_en        : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t ef_sw_cpu1_enc_en     : 1; /* [    6],        r/w,        0x0 */
            uint32_t ef_sw_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
            uint32_t ef_sw_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
            uint32_t ef_sw_sdu_dis         : 1; /* [   14],        r/w,        0x0 */
            uint32_t ef_sw_ble_dis         : 1; /* [   15],        r/w,        0x0 */
            uint32_t ef_sw_wifi_dis        : 1; /* [   16],        r/w,        0x0 */
            uint32_t ef_sw_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
            uint32_t ef_sw_cam_dis         : 1; /* [   18],        r/w,        0x0 */
            uint32_t ef_sw_m154_dis        : 1; /* [   19],        r/w,        0x0 */
            uint32_t ef_sw_cpu1_dis        : 1; /* [   20],        r/w,        0x0 */
            uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [   21],        r/w,        0x0 */
            uint32_t ef_sw_se_dbg_dis      : 1; /* [   22],        r/w,        0x0 */
            uint32_t ef_sw_efuse_dbg_dis   : 1; /* [   23],        r/w,        0x0 */
            uint32_t ef_sw_dbg_jtag_1_dis  : 2; /* [25:24],        r/w,        0x0 */
            uint32_t ef_sw_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
            uint32_t ef_sw_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_sw_cfg_0;

    /* 0x81C : ef_reserved */
    union {
        struct
        {
            uint32_t ef_reserved : 32; /* [31: 0],        r/w,     0xffff */
        } BF;
        uint32_t WORD;
    } ef_reserved;

    /* 0x820 : ef_if_ana_trim_0 */
    union {
        struct
        {
            uint32_t ef_if_ana_trim_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_ana_trim_0;

    /* 0x824 : ef_if_sw_usage_0 */
    union {
        struct
        {
            uint32_t ef_if_sw_usage_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_if_sw_usage_0;

    /* 0x828  reserved */
    uint8_t RESERVED0x828[472];

    /* 0xA00 : ef_crc_ctrl_0 */
    union {
        struct
        {
            uint32_t ef_crc_busy        : 1;  /* [    0],          r,        0x0 */
            uint32_t ef_crc_trig        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ef_crc_en          : 1;  /* [    2],        r/w,        0x1 */
            uint32_t ef_crc_mode        : 1;  /* [    3],        r/w,        0x0 */
            uint32_t ef_crc_error       : 1;  /* [    4],          r,        0x0 */
            uint32_t ef_crc_dout_inv_en : 1;  /* [    5],        r/w,        0x1 */
            uint32_t ef_crc_dout_endian : 1;  /* [    6],        r/w,        0x0 */
            uint32_t ef_crc_din_endian  : 1;  /* [    7],        r/w,        0x0 */
            uint32_t ef_crc_int         : 1;  /* [    8],          r,        0x0 */
            uint32_t ef_crc_int_clr     : 1;  /* [    9],        r/w,        0x1 */
            uint32_t ef_crc_int_set     : 1;  /* [   10],        r/w,        0x0 */
            uint32_t ef_crc_lock        : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t ef_crc_slp_n       : 16; /* [31:16],        r/w,       0xff */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_0;

    /* 0xA04 : ef_crc_ctrl_1 */
    union {
        struct
        {
            uint32_t ef_crc_data_0_en : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_1;

    /* 0xA08 : ef_crc_ctrl_2 */
    union {
        struct
        {
            uint32_t ef_crc_data_1_en : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_2;

    /* 0xA0C : ef_crc_ctrl_3 */
    union {
        struct
        {
            uint32_t ef_crc_iv : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_3;

    /* 0xA10 : ef_crc_ctrl_4 */
    union {
        struct
        {
            uint32_t ef_crc_golden : 32; /* [31: 0],        r/w, 0xc2a8fa9dL */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_4;

    /* 0xA14 : ef_crc_ctrl_5 */
    union {
        struct
        {
            uint32_t ef_crc_dout : 32; /* [31: 0],          r, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } ef_crc_ctrl_5;
};

typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;

#endif /* __EF_CTRL_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ef_data_0_reg.h
================================================
/**
  ******************************************************************************
  * @file    ef_data_0_reg.h
  * @version V1.2
  * @date    2020-04-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __EF_DATA_0_REG_H__
#define __EF_DATA_0_REG_H__

#include "bl702.h"

/* 0x0 : ef_cfg_0 */
#define EF_DATA_0_EF_CFG_0_OFFSET         (0x0)
#define EF_DATA_0_EF_SF_AES_MODE          EF_DATA_0_EF_SF_AES_MODE
#define EF_DATA_0_EF_SF_AES_MODE_POS      (0U)
#define EF_DATA_0_EF_SF_AES_MODE_LEN      (2U)
#define EF_DATA_0_EF_SF_AES_MODE_MSK      (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
#define EF_DATA_0_EF_SF_AES_MODE_UMSK     (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
#define EF_DATA_0_EF_SBOOT_SIGN_MODE      EF_DATA_0_EF_SBOOT_SIGN_MODE
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS  (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN  (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK  (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_0_EF_SBOOT_EN             EF_DATA_0_EF_SBOOT_EN
#define EF_DATA_0_EF_SBOOT_EN_POS         (4U)
#define EF_DATA_0_EF_SBOOT_EN_LEN         (2U)
#define EF_DATA_0_EF_SBOOT_EN_MSK         (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
#define EF_DATA_0_EF_SBOOT_EN_UMSK        (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
#define EF_DATA_0_EF_CPU0_ENC_EN          EF_DATA_0_EF_CPU0_ENC_EN
#define EF_DATA_0_EF_CPU0_ENC_EN_POS      (7U)
#define EF_DATA_0_EF_CPU0_ENC_EN_LEN      (1U)
#define EF_DATA_0_EF_CPU0_ENC_EN_MSK      (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)
#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK     (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS))
#define EF_DATA_0_EF_BOOT_SEL             EF_DATA_0_EF_BOOT_SEL
#define EF_DATA_0_EF_BOOT_SEL_POS         (8U)
#define EF_DATA_0_EF_BOOT_SEL_LEN         (4U)
#define EF_DATA_0_EF_BOOT_SEL_MSK         (((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS)
#define EF_DATA_0_EF_BOOT_SEL_UMSK        (~(((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS))
#define EF_DATA_0_EF_SF_KEY_0_SEL         EF_DATA_0_EF_SF_KEY_0_SEL
#define EF_DATA_0_EF_SF_KEY_0_SEL_POS     (12U)
#define EF_DATA_0_EF_SF_KEY_0_SEL_LEN     (2U)
#define EF_DATA_0_EF_SF_KEY_0_SEL_MSK     (((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS)
#define EF_DATA_0_EF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS))
#define EF_DATA_0_EF_0_KEY_ENC_EN         EF_DATA_0_EF_0_KEY_ENC_EN
#define EF_DATA_0_EF_0_KEY_ENC_EN_POS     (17U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN     (1U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK     (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_0_EF_DBG_JTAG_0_DIS       EF_DATA_0_EF_DBG_JTAG_0_DIS
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS   (26U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN   (2U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK   (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_0_EF_DBG_MODE             EF_DATA_0_EF_DBG_MODE
#define EF_DATA_0_EF_DBG_MODE_POS         (28U)
#define EF_DATA_0_EF_DBG_MODE_LEN         (4U)
#define EF_DATA_0_EF_DBG_MODE_MSK         (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
#define EF_DATA_0_EF_DBG_MODE_UMSK        (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))

/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_0_EF_DBG_PWD_LOW        EF_DATA_0_EF_DBG_PWD_LOW
#define EF_DATA_0_EF_DBG_PWD_LOW_POS    (0U)
#define EF_DATA_0_EF_DBG_PWD_LOW_LEN    (32U)
#define EF_DATA_0_EF_DBG_PWD_LOW_MSK    (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK   (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))

/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_0_EF_DBG_PWD_HIGH        EF_DATA_0_EF_DBG_PWD_HIGH
#define EF_DATA_0_EF_DBG_PWD_HIGH_POS    (0U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN    (32U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK    (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK   (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))

/* 0xC : ef_ana_trim_0 */
#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_0_EF_ANA_TRIM_0        EF_DATA_0_EF_ANA_TRIM_0
#define EF_DATA_0_EF_ANA_TRIM_0_POS    (0U)
#define EF_DATA_0_EF_ANA_TRIM_0_LEN    (32U)
#define EF_DATA_0_EF_ANA_TRIM_0_MSK    (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)
#define EF_DATA_0_EF_ANA_TRIM_0_UMSK   (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS))

/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_0_EF_SW_USAGE_0        EF_DATA_0_EF_SW_USAGE_0
#define EF_DATA_0_EF_SW_USAGE_0_POS    (0U)
#define EF_DATA_0_EF_SW_USAGE_0_LEN    (32U)
#define EF_DATA_0_EF_SW_USAGE_0_MSK    (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
#define EF_DATA_0_EF_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))

/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_0_EF_WIFI_MAC_LOW        EF_DATA_0_EF_WIFI_MAC_LOW
#define EF_DATA_0_EF_WIFI_MAC_LOW_POS    (0U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN    (32U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK    (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK   (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))

/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_0_EF_WIFI_MAC_HIGH        EF_DATA_0_EF_WIFI_MAC_HIGH
#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS    (0U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN    (32U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK    (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK   (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))

/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_0_EF_KEY_SLOT_0_W0        EF_DATA_0_EF_KEY_SLOT_0_W0
#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))

/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_0_EF_KEY_SLOT_0_W1        EF_DATA_0_EF_KEY_SLOT_0_W1
#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))

/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_0_EF_KEY_SLOT_0_W2        EF_DATA_0_EF_KEY_SLOT_0_W2
#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))

/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_0_EF_KEY_SLOT_0_W3        EF_DATA_0_EF_KEY_SLOT_0_W3
#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))

/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_0_EF_KEY_SLOT_1_W0        EF_DATA_0_EF_KEY_SLOT_1_W0
#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))

/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_0_EF_KEY_SLOT_1_W1        EF_DATA_0_EF_KEY_SLOT_1_W1
#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))

/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_0_EF_KEY_SLOT_1_W2        EF_DATA_0_EF_KEY_SLOT_1_W2
#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))

/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_0_EF_KEY_SLOT_1_W3        EF_DATA_0_EF_KEY_SLOT_1_W3
#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))

/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_0_EF_KEY_SLOT_2_W0        EF_DATA_0_EF_KEY_SLOT_2_W0
#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))

/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_0_EF_KEY_SLOT_2_W1        EF_DATA_0_EF_KEY_SLOT_2_W1
#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))

/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_0_EF_KEY_SLOT_2_W2        EF_DATA_0_EF_KEY_SLOT_2_W2
#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))

/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_0_EF_KEY_SLOT_2_W3        EF_DATA_0_EF_KEY_SLOT_2_W3
#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))

/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_0_EF_KEY_SLOT_3_W0        EF_DATA_0_EF_KEY_SLOT_3_W0
#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))

/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_0_EF_KEY_SLOT_3_W1        EF_DATA_0_EF_KEY_SLOT_3_W1
#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))

/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_0_EF_KEY_SLOT_3_W2        EF_DATA_0_EF_KEY_SLOT_3_W2
#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))

/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_0_EF_KEY_SLOT_3_W3        EF_DATA_0_EF_KEY_SLOT_3_W3
#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))

/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_0_EF_KEY_SLOT_4_W0        EF_DATA_0_EF_KEY_SLOT_4_W0
#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS))

/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_0_EF_KEY_SLOT_4_W1        EF_DATA_0_EF_KEY_SLOT_4_W1
#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS))

/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_0_EF_KEY_SLOT_4_W2        EF_DATA_0_EF_KEY_SLOT_4_W2
#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS))

/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_0_EF_KEY_SLOT_4_W3        EF_DATA_0_EF_KEY_SLOT_4_W3
#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS))

/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_0_EF_KEY_SLOT_5_W0        EF_DATA_0_EF_KEY_SLOT_5_W0
#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS))

/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_0_EF_KEY_SLOT_5_W1        EF_DATA_0_EF_KEY_SLOT_5_W1
#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS))

/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_0_EF_KEY_SLOT_5_W2        EF_DATA_0_EF_KEY_SLOT_5_W2
#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS))

/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_0_EF_KEY_SLOT_5_W3        EF_DATA_0_EF_KEY_SLOT_5_W3
#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS    (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN    (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK    (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK   (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS))

/* 0x7C : ef_data_0_lock */
#define EF_DATA_0_LOCK_OFFSET               (0x7C)
#define EF_DATA_0_EF_ANA_TRIM_1             EF_DATA_0_EF_ANA_TRIM_1
#define EF_DATA_0_EF_ANA_TRIM_1_POS         (0U)
#define EF_DATA_0_EF_ANA_TRIM_1_LEN         (13U)
#define EF_DATA_0_EF_ANA_TRIM_1_MSK         (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)
#define EF_DATA_0_EF_ANA_TRIM_1_UMSK        (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L      EF_DATA_0_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS  (13U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN  (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L      EF_DATA_0_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS  (14U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN  (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_0_WR_LOCK_BOOT_MODE         EF_DATA_0_WR_LOCK_BOOT_MODE
#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS     (15U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN     (1U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK     (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK    (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_0_WR_LOCK_DBG_PWD           EF_DATA_0_WR_LOCK_DBG_PWD
#define EF_DATA_0_WR_LOCK_DBG_PWD_POS       (16U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN       (1U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_0        EF_DATA_0_WR_LOCK_SW_USAGE_0
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS    (17U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN    (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK    (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_0_WR_LOCK_WIFI_MAC          EF_DATA_0_WR_LOCK_WIFI_MAC
#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS      (18U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN      (1U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK      (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK     (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0        EF_DATA_0_WR_LOCK_KEY_SLOT_0
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS    (19U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN    (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1        EF_DATA_0_WR_LOCK_KEY_SLOT_1
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS    (20U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN    (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2        EF_DATA_0_WR_LOCK_KEY_SLOT_2
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS    (21U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN    (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3        EF_DATA_0_WR_LOCK_KEY_SLOT_3
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS    (22U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN    (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H      EF_DATA_0_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS  (23U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN  (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H      EF_DATA_0_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS  (24U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN  (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK  (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_0_RD_LOCK_DBG_PWD           EF_DATA_0_RD_LOCK_DBG_PWD
#define EF_DATA_0_RD_LOCK_DBG_PWD_POS       (25U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN       (1U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0        EF_DATA_0_RD_LOCK_KEY_SLOT_0
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS    (26U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1        EF_DATA_0_RD_LOCK_KEY_SLOT_1
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS    (27U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2        EF_DATA_0_RD_LOCK_KEY_SLOT_2
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS    (28U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3        EF_DATA_0_RD_LOCK_KEY_SLOT_3
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS    (29U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4        EF_DATA_0_RD_LOCK_KEY_SLOT_4
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS    (30U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5        EF_DATA_0_RD_LOCK_KEY_SLOT_5
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS    (31U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN    (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK    (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK   (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS))

struct ef_data_0_reg {
    /* 0x0 : ef_cfg_0 */
    union {
        struct
        {
            uint32_t ef_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t rsvd0              : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t rsvd1              : 1; /* [    6],        r/w,        0x0 */
            uint32_t ef_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
            uint32_t ef_boot_sel        : 4; /* [11: 8],        r/w,        0x0 */
            uint32_t ef_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
            uint32_t rsvd2              : 1; /* [   14],        r/w,        0x0 */
            uint32_t rsvd3              : 1; /* [   15],        r/w,        0x0 */
            uint32_t rsvd4              : 1; /* [   16],        r/w,        0x0 */
            uint32_t ef_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
            uint32_t rsvd5              : 1; /* [   18],        r/w,        0x0 */
            uint32_t rsvd6              : 1; /* [   19],        r/w,        0x0 */
            uint32_t rsvd7              : 1; /* [   20],        r/w,        0x0 */
            uint32_t rsvd8              : 1; /* [   21],        r/w,        0x0 */
            uint32_t rsvd9              : 1; /* [   22],        r/w,        0x0 */
            uint32_t rsvd10             : 1; /* [   23],        r/w,        0x0 */
            uint32_t rsvd11             : 2; /* [25:24],        r/w,        0x0 */
            uint32_t ef_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
            uint32_t ef_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_cfg_0;

    /* 0x4 : ef_dbg_pwd_low */
    union {
        struct
        {
            uint32_t ef_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_dbg_pwd_low;

    /* 0x8 : ef_dbg_pwd_high */
    union {
        struct
        {
            uint32_t ef_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_dbg_pwd_high;

    /* 0xC : ef_ana_trim_0 */
    union {
        struct
        {
            uint32_t ef_ana_trim_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_ana_trim_0;

    /* 0x10 : ef_sw_usage_0 */
    union {
        struct
        {
            uint32_t ef_sw_usage_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_sw_usage_0;

    /* 0x14 : ef_wifi_mac_low */
    union {
        struct
        {
            uint32_t ef_wifi_mac_low : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_wifi_mac_low;

    /* 0x18 : ef_wifi_mac_high */
    union {
        struct
        {
            uint32_t ef_wifi_mac_high : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_wifi_mac_high;

    /* 0x1C : ef_key_slot_0_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_0_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_0_w0;

    /* 0x20 : ef_key_slot_0_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_0_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_0_w1;

    /* 0x24 : ef_key_slot_0_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_0_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_0_w2;

    /* 0x28 : ef_key_slot_0_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_0_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_0_w3;

    /* 0x2C : ef_key_slot_1_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_1_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_1_w0;

    /* 0x30 : ef_key_slot_1_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_1_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_1_w1;

    /* 0x34 : ef_key_slot_1_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_1_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_1_w2;

    /* 0x38 : ef_key_slot_1_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_1_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_1_w3;

    /* 0x3C : ef_key_slot_2_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_2_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_2_w0;

    /* 0x40 : ef_key_slot_2_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_2_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_2_w1;

    /* 0x44 : ef_key_slot_2_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_2_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_2_w2;

    /* 0x48 : ef_key_slot_2_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_2_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_2_w3;

    /* 0x4C : ef_key_slot_3_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_3_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_3_w0;

    /* 0x50 : ef_key_slot_3_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_3_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_3_w1;

    /* 0x54 : ef_key_slot_3_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_3_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_3_w2;

    /* 0x58 : ef_key_slot_3_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_3_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_3_w3;

    /* 0x5C : ef_key_slot_4_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_4_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_4_w0;

    /* 0x60 : ef_key_slot_4_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_4_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_4_w1;

    /* 0x64 : ef_key_slot_4_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_4_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_4_w2;

    /* 0x68 : ef_key_slot_4_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_4_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_4_w3;

    /* 0x6C : ef_key_slot_5_w0 */
    union {
        struct
        {
            uint32_t ef_key_slot_5_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_5_w0;

    /* 0x70 : ef_key_slot_5_w1 */
    union {
        struct
        {
            uint32_t ef_key_slot_5_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_5_w1;

    /* 0x74 : ef_key_slot_5_w2 */
    union {
        struct
        {
            uint32_t ef_key_slot_5_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_5_w2;

    /* 0x78 : ef_key_slot_5_w3 */
    union {
        struct
        {
            uint32_t ef_key_slot_5_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_key_slot_5_w3;

    /* 0x7C : ef_data_0_lock */
    union {
        struct
        {
            uint32_t ef_ana_trim_1        : 13; /* [12: 0],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_4_l : 1;  /* [   13],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_5_l : 1;  /* [   14],        r/w,        0x0 */
            uint32_t wr_lock_boot_mode    : 1;  /* [   15],        r/w,        0x0 */
            uint32_t wr_lock_dbg_pwd      : 1;  /* [   16],        r/w,        0x0 */
            uint32_t wr_lock_sw_usage_0   : 1;  /* [   17],        r/w,        0x0 */
            uint32_t wr_lock_wifi_mac     : 1;  /* [   18],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_0   : 1;  /* [   19],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_1   : 1;  /* [   20],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_2   : 1;  /* [   21],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_3   : 1;  /* [   22],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_4_h : 1;  /* [   23],        r/w,        0x0 */
            uint32_t wr_lock_key_slot_5_h : 1;  /* [   24],        r/w,        0x0 */
            uint32_t rd_lock_dbg_pwd      : 1;  /* [   25],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_0   : 1;  /* [   26],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_1   : 1;  /* [   27],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_2   : 1;  /* [   28],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_3   : 1;  /* [   29],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_4   : 1;  /* [   30],        r/w,        0x0 */
            uint32_t rd_lock_key_slot_5   : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } ef_data_0_lock;
};

typedef volatile struct ef_data_0_reg ef_data_0_reg_t;

#endif /* __EF_DATA_0_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/emac_reg.h
================================================
/**
  ******************************************************************************
  * @file    emac_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __EMAC_REG_H__
#define __EMAC_REG_H__

#include "bl702.h"

/* 0x0 : MODE */
#define EMAC_MODE_OFFSET   (0x0)
#define EMAC_RXEN          EMAC_RXEN
#define EMAC_RXEN_POS      (0U)
#define EMAC_RXEN_LEN      (1U)
#define EMAC_RXEN_MSK      (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)
#define EMAC_RXEN_UMSK     (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS))
#define EMAC_TXEN          EMAC_TXEN
#define EMAC_TXEN_POS      (1U)
#define EMAC_TXEN_LEN      (1U)
#define EMAC_TXEN_MSK      (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)
#define EMAC_TXEN_UMSK     (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS))
#define EMAC_NOPRE         EMAC_NOPRE
#define EMAC_NOPRE_POS     (2U)
#define EMAC_NOPRE_LEN     (1U)
#define EMAC_NOPRE_MSK     (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)
#define EMAC_NOPRE_UMSK    (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS))
#define EMAC_BRO           EMAC_BRO
#define EMAC_BRO_POS       (3U)
#define EMAC_BRO_LEN       (1U)
#define EMAC_BRO_MSK       (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)
#define EMAC_BRO_UMSK      (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS))
#define EMAC_PRO           EMAC_PRO
#define EMAC_PRO_POS       (5U)
#define EMAC_PRO_LEN       (1U)
#define EMAC_PRO_MSK       (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)
#define EMAC_PRO_UMSK      (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS))
#define EMAC_IFG           EMAC_IFG
#define EMAC_IFG_POS       (6U)
#define EMAC_IFG_LEN       (1U)
#define EMAC_IFG_MSK       (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)
#define EMAC_IFG_UMSK      (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS))
#define EMAC_FULLD         EMAC_FULLD
#define EMAC_FULLD_POS     (10U)
#define EMAC_FULLD_LEN     (1U)
#define EMAC_FULLD_MSK     (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)
#define EMAC_FULLD_UMSK    (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS))
#define EMAC_CRCEN         EMAC_CRCEN
#define EMAC_CRCEN_POS     (13U)
#define EMAC_CRCEN_LEN     (1U)
#define EMAC_CRCEN_MSK     (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)
#define EMAC_CRCEN_UMSK    (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS))
#define EMAC_HUGEN         EMAC_HUGEN
#define EMAC_HUGEN_POS     (14U)
#define EMAC_HUGEN_LEN     (1U)
#define EMAC_HUGEN_MSK     (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)
#define EMAC_HUGEN_UMSK    (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS))
#define EMAC_PAD           EMAC_PAD
#define EMAC_PAD_POS       (15U)
#define EMAC_PAD_LEN       (1U)
#define EMAC_PAD_MSK       (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)
#define EMAC_PAD_UMSK      (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS))
#define EMAC_RECSMALL      EMAC_RECSMALL
#define EMAC_RECSMALL_POS  (16U)
#define EMAC_RECSMALL_LEN  (1U)
#define EMAC_RECSMALL_MSK  (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)
#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS))
#define EMAC_RMII_EN       EMAC_RMII_EN
#define EMAC_RMII_EN_POS   (17U)
#define EMAC_RMII_EN_LEN   (1U)
#define EMAC_RMII_EN_MSK   (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)
#define EMAC_RMII_EN_UMSK  (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS))

/* 0x4 : INT_SOURCE */
#define EMAC_INT_SOURCE_OFFSET (0x4)
#define EMAC_TXB               EMAC_TXB
#define EMAC_TXB_POS           (0U)
#define EMAC_TXB_LEN           (1U)
#define EMAC_TXB_MSK           (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)
#define EMAC_TXB_UMSK          (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS))
#define EMAC_TXE               EMAC_TXE
#define EMAC_TXE_POS           (1U)
#define EMAC_TXE_LEN           (1U)
#define EMAC_TXE_MSK           (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)
#define EMAC_TXE_UMSK          (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS))
#define EMAC_RXB               EMAC_RXB
#define EMAC_RXB_POS           (2U)
#define EMAC_RXB_LEN           (1U)
#define EMAC_RXB_MSK           (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)
#define EMAC_RXB_UMSK          (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS))
#define EMAC_RXE               EMAC_RXE
#define EMAC_RXE_POS           (3U)
#define EMAC_RXE_LEN           (1U)
#define EMAC_RXE_MSK           (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)
#define EMAC_RXE_UMSK          (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS))
#define EMAC_BUSY              EMAC_BUSY
#define EMAC_BUSY_POS          (4U)
#define EMAC_BUSY_LEN          (1U)
#define EMAC_BUSY_MSK          (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)
#define EMAC_BUSY_UMSK         (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS))
#define EMAC_TXC               EMAC_TXC
#define EMAC_TXC_POS           (5U)
#define EMAC_TXC_LEN           (1U)
#define EMAC_TXC_MSK           (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)
#define EMAC_TXC_UMSK          (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS))
#define EMAC_RXC               EMAC_RXC
#define EMAC_RXC_POS           (6U)
#define EMAC_RXC_LEN           (1U)
#define EMAC_RXC_MSK           (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)
#define EMAC_RXC_UMSK          (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS))

/* 0x8 : INT_MASK */
#define EMAC_INT_MASK_OFFSET (0x8)
#define EMAC_TXB_M           EMAC_TXB_M
#define EMAC_TXB_M_POS       (0U)
#define EMAC_TXB_M_LEN       (1U)
#define EMAC_TXB_M_MSK       (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)
#define EMAC_TXB_M_UMSK      (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS))
#define EMAC_TXE_M           EMAC_TXE_M
#define EMAC_TXE_M_POS       (1U)
#define EMAC_TXE_M_LEN       (1U)
#define EMAC_TXE_M_MSK       (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)
#define EMAC_TXE_M_UMSK      (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS))
#define EMAC_RXB_M           EMAC_RXB_M
#define EMAC_RXB_M_POS       (2U)
#define EMAC_RXB_M_LEN       (1U)
#define EMAC_RXB_M_MSK       (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)
#define EMAC_RXB_M_UMSK      (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS))
#define EMAC_RXE_M           EMAC_RXE_M
#define EMAC_RXE_M_POS       (3U)
#define EMAC_RXE_M_LEN       (1U)
#define EMAC_RXE_M_MSK       (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)
#define EMAC_RXE_M_UMSK      (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS))
#define EMAC_BUSY_M          EMAC_BUSY_M
#define EMAC_BUSY_M_POS      (4U)
#define EMAC_BUSY_M_LEN      (1U)
#define EMAC_BUSY_M_MSK      (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)
#define EMAC_BUSY_M_UMSK     (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS))
#define EMAC_TXC_M           EMAC_TXC_M
#define EMAC_TXC_M_POS       (5U)
#define EMAC_TXC_M_LEN       (1U)
#define EMAC_TXC_M_MSK       (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)
#define EMAC_TXC_M_UMSK      (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS))
#define EMAC_RXC_M           EMAC_RXC_M
#define EMAC_RXC_M_POS       (6U)
#define EMAC_RXC_M_LEN       (1U)
#define EMAC_RXC_M_MSK       (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)
#define EMAC_RXC_M_UMSK      (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS))

/* 0xC : IPGT */
#define EMAC_IPGT_OFFSET (0xC)
#define EMAC_IPGT        EMAC_IPGT
#define EMAC_IPGT_POS    (0U)
#define EMAC_IPGT_LEN    (7U)
#define EMAC_IPGT_MSK    (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)
#define EMAC_IPGT_UMSK   (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS))

/* 0x18 : PACKETLEN */
#define EMAC_PACKETLEN_OFFSET (0x18)
#define EMAC_MAXFL            EMAC_MAXFL
#define EMAC_MAXFL_POS        (0U)
#define EMAC_MAXFL_LEN        (16U)
#define EMAC_MAXFL_MSK        (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)
#define EMAC_MAXFL_UMSK       (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS))
#define EMAC_MINFL            EMAC_MINFL
#define EMAC_MINFL_POS        (16U)
#define EMAC_MINFL_LEN        (16U)
#define EMAC_MINFL_MSK        (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)
#define EMAC_MINFL_UMSK       (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS))

/* 0x1C : COLLCONFIG */
#define EMAC_COLLCONFIG_OFFSET (0x1C)
#define EMAC_COLLVALID         EMAC_COLLVALID
#define EMAC_COLLVALID_POS     (0U)
#define EMAC_COLLVALID_LEN     (6U)
#define EMAC_COLLVALID_MSK     (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)
#define EMAC_COLLVALID_UMSK    (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS))
#define EMAC_MAXRET            EMAC_MAXRET
#define EMAC_MAXRET_POS        (16U)
#define EMAC_MAXRET_LEN        (4U)
#define EMAC_MAXRET_MSK        (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)
#define EMAC_MAXRET_UMSK       (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS))

/* 0x20 : TX_BD_NUM */
#define EMAC_TX_BD_NUM_OFFSET (0x20)
#define EMAC_TXBDNUM          EMAC_TXBDNUM
#define EMAC_TXBDNUM_POS      (0U)
#define EMAC_TXBDNUM_LEN      (8U)
#define EMAC_TXBDNUM_MSK      (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)
#define EMAC_TXBDNUM_UMSK     (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS))
#define EMAC_TXBDPTR          EMAC_TXBDPTR
#define EMAC_TXBDPTR_POS      (16U)
#define EMAC_TXBDPTR_LEN      (7U)
#define EMAC_TXBDPTR_MSK      (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)
#define EMAC_TXBDPTR_UMSK     (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS))
#define EMAC_RXBDPTR          EMAC_RXBDPTR
#define EMAC_RXBDPTR_POS      (24U)
#define EMAC_RXBDPTR_LEN      (7U)
#define EMAC_RXBDPTR_MSK      (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)
#define EMAC_RXBDPTR_UMSK     (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS))

/* 0x28 : MIIMODE */
#define EMAC_MIIMODE_OFFSET (0x28)
#define EMAC_CLKDIV         EMAC_CLKDIV
#define EMAC_CLKDIV_POS     (0U)
#define EMAC_CLKDIV_LEN     (8U)
#define EMAC_CLKDIV_MSK     (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)
#define EMAC_CLKDIV_UMSK    (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS))
#define EMAC_MIINOPRE       EMAC_MIINOPRE
#define EMAC_MIINOPRE_POS   (8U)
#define EMAC_MIINOPRE_LEN   (1U)
#define EMAC_MIINOPRE_MSK   (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)
#define EMAC_MIINOPRE_UMSK  (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS))

/* 0x2C : MIICOMMAND */
#define EMAC_MIICOMMAND_OFFSET (0x2C)
#define EMAC_SCANSTAT          EMAC_SCANSTAT
#define EMAC_SCANSTAT_POS      (0U)
#define EMAC_SCANSTAT_LEN      (1U)
#define EMAC_SCANSTAT_MSK      (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)
#define EMAC_SCANSTAT_UMSK     (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS))
#define EMAC_RSTAT             EMAC_RSTAT
#define EMAC_RSTAT_POS         (1U)
#define EMAC_RSTAT_LEN         (1U)
#define EMAC_RSTAT_MSK         (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)
#define EMAC_RSTAT_UMSK        (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS))
#define EMAC_WCTRLDATA         EMAC_WCTRLDATA
#define EMAC_WCTRLDATA_POS     (2U)
#define EMAC_WCTRLDATA_LEN     (1U)
#define EMAC_WCTRLDATA_MSK     (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)
#define EMAC_WCTRLDATA_UMSK    (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS))

/* 0x30 : MIIADDRESS */
#define EMAC_MIIADDRESS_OFFSET (0x30)
#define EMAC_FIAD              EMAC_FIAD
#define EMAC_FIAD_POS          (0U)
#define EMAC_FIAD_LEN          (5U)
#define EMAC_FIAD_MSK          (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)
#define EMAC_FIAD_UMSK         (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS))
#define EMAC_RGAD              EMAC_RGAD
#define EMAC_RGAD_POS          (8U)
#define EMAC_RGAD_LEN          (5U)
#define EMAC_RGAD_MSK          (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)
#define EMAC_RGAD_UMSK         (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS))

/* 0x34 : MIITX_DATA */
#define EMAC_MIITX_DATA_OFFSET (0x34)
#define EMAC_CTRLDATA          EMAC_CTRLDATA
#define EMAC_CTRLDATA_POS      (0U)
#define EMAC_CTRLDATA_LEN      (16U)
#define EMAC_CTRLDATA_MSK      (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)
#define EMAC_CTRLDATA_UMSK     (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS))

/* 0x38 : MIIRX_DATA */
#define EMAC_MIIRX_DATA_OFFSET (0x38)
#define EMAC_PRSD              EMAC_PRSD
#define EMAC_PRSD_POS          (0U)
#define EMAC_PRSD_LEN          (16U)
#define EMAC_PRSD_MSK          (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)
#define EMAC_PRSD_UMSK         (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS))

/* 0x3C : MIISTATUS */
#define EMAC_MIISTATUS_OFFSET   (0x3C)
#define EMAC_MIIM_LINKFAIL      EMAC_MIIM_LINKFAIL
#define EMAC_MIIM_LINKFAIL_POS  (0U)
#define EMAC_MIIM_LINKFAIL_LEN  (1U)
#define EMAC_MIIM_LINKFAIL_MSK  (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)
#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS))
#define EMAC_MIIM_BUSY          EMAC_MIIM_BUSY
#define EMAC_MIIM_BUSY_POS      (1U)
#define EMAC_MIIM_BUSY_LEN      (1U)
#define EMAC_MIIM_BUSY_MSK      (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)
#define EMAC_MIIM_BUSY_UMSK     (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS))

/* 0x40 : MAC_ADDR0 */
#define EMAC_MAC_ADDR0_OFFSET (0x40)
#define EMAC_MAC_B5           EMAC_MAC_B5
#define EMAC_MAC_B5_POS       (0U)
#define EMAC_MAC_B5_LEN       (8U)
#define EMAC_MAC_B5_MSK       (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)
#define EMAC_MAC_B5_UMSK      (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS))
#define EMAC_MAC_B4           EMAC_MAC_B4
#define EMAC_MAC_B4_POS       (8U)
#define EMAC_MAC_B4_LEN       (8U)
#define EMAC_MAC_B4_MSK       (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)
#define EMAC_MAC_B4_UMSK      (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS))
#define EMAC_MAC_B3           EMAC_MAC_B3
#define EMAC_MAC_B3_POS       (16U)
#define EMAC_MAC_B3_LEN       (8U)
#define EMAC_MAC_B3_MSK       (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)
#define EMAC_MAC_B3_UMSK      (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS))
#define EMAC_MAC_B2           EMAC_MAC_B2
#define EMAC_MAC_B2_POS       (24U)
#define EMAC_MAC_B2_LEN       (8U)
#define EMAC_MAC_B2_MSK       (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)
#define EMAC_MAC_B2_UMSK      (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS))

/* 0x44 : MAC_ADDR1 */
#define EMAC_MAC_ADDR1_OFFSET (0x44)
#define EMAC_MAC_B1           EMAC_MAC_B1
#define EMAC_MAC_B1_POS       (0U)
#define EMAC_MAC_B1_LEN       (8U)
#define EMAC_MAC_B1_MSK       (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)
#define EMAC_MAC_B1_UMSK      (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS))
#define EMAC_MAC_B0           EMAC_MAC_B0
#define EMAC_MAC_B0_POS       (8U)
#define EMAC_MAC_B0_LEN       (8U)
#define EMAC_MAC_B0_MSK       (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)
#define EMAC_MAC_B0_UMSK      (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS))

/* 0x48 : HASH0_ADDR */
#define EMAC_HASH0_ADDR_OFFSET (0x48)
#define EMAC_HASH0             EMAC_HASH0
#define EMAC_HASH0_POS         (0U)
#define EMAC_HASH0_LEN         (32U)
#define EMAC_HASH0_MSK         (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)
#define EMAC_HASH0_UMSK        (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS))

/* 0x4C : HASH1_ADDR */
#define EMAC_HASH1_ADDR_OFFSET (0x4C)
#define EMAC_HASH1             EMAC_HASH1
#define EMAC_HASH1_POS         (0U)
#define EMAC_HASH1_LEN         (32U)
#define EMAC_HASH1_MSK         (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)
#define EMAC_HASH1_UMSK        (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS))

/* 0x50 : TXCTRL */
#define EMAC_TXCTRL_OFFSET  (0x50)
#define EMAC_TXPAUSETV      EMAC_TXPAUSETV
#define EMAC_TXPAUSETV_POS  (0U)
#define EMAC_TXPAUSETV_LEN  (16U)
#define EMAC_TXPAUSETV_MSK  (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)
#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS))
#define EMAC_TXPAUSERQ      EMAC_TXPAUSERQ
#define EMAC_TXPAUSERQ_POS  (16U)
#define EMAC_TXPAUSERQ_LEN  (1U)
#define EMAC_TXPAUSERQ_MSK  (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)
#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS))

struct emac_reg {
    /* 0x0 : MODE */
    union {
        struct
        {
            uint32_t RXEN           : 1; /* [    0],        r/w,        0x0 */
            uint32_t TXEN           : 1; /* [    1],        r/w,        0x0 */
            uint32_t NOPRE          : 1; /* [    2],        r/w,        0x0 */
            uint32_t BRO            : 1; /* [    3],        r/w,        0x1 */
            uint32_t rsvd_4         : 1; /* [    4],       rsvd,        0x0 */
            uint32_t PRO            : 1; /* [    5],        r/w,        0x0 */
            uint32_t IFG            : 1; /* [    6],        r/w,        0x0 */
            uint32_t rsvd_9_7       : 3; /* [ 9: 7],       rsvd,        0x0 */
            uint32_t FULLD          : 1; /* [   10],        r/w,        0x0 */
            uint32_t rsvd_12_11     : 2; /* [12:11],       rsvd,        0x0 */
            uint32_t CRCEN          : 1; /* [   13],        r/w,        0x1 */
            uint32_t HUGEN          : 1; /* [   14],        r/w,        0x0 */
            uint32_t PAD            : 1; /* [   15],        r/w,        0x1 */
            uint32_t RECSMALL       : 1; /* [   16],        r/w,        0x0 */
            uint32_t RMII_EN        : 1; /* [   17],        r/w,        0x0 */
            uint32_t rsvd_23_18     : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t reserved_24_31 : 8; /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MODE;

    /* 0x4 : INT_SOURCE */
    union {
        struct
        {
            uint32_t TXB           : 1;  /* [    0],        r/w,        0x0 */
            uint32_t TXE           : 1;  /* [    1],        r/w,        0x0 */
            uint32_t RXB           : 1;  /* [    2],        r/w,        0x0 */
            uint32_t RXE           : 1;  /* [    3],        r/w,        0x0 */
            uint32_t BUSY          : 1;  /* [    4],        r/w,        0x0 */
            uint32_t TXC           : 1;  /* [    5],        r/w,        0x0 */
            uint32_t RXC           : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } INT_SOURCE;

    /* 0x8 : INT_MASK */
    union {
        struct
        {
            uint32_t TXB_M         : 1;  /* [    0],        r/w,        0x1 */
            uint32_t TXE_M         : 1;  /* [    1],        r/w,        0x1 */
            uint32_t RXB_M         : 1;  /* [    2],        r/w,        0x1 */
            uint32_t RXE_M         : 1;  /* [    3],        r/w,        0x1 */
            uint32_t BUSY_M        : 1;  /* [    4],        r/w,        0x1 */
            uint32_t TXC_M         : 1;  /* [    5],        r/w,        0x1 */
            uint32_t RXC_M         : 1;  /* [    6],        r/w,        0x1 */
            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } INT_MASK;

    /* 0xC : IPGT */
    union {
        struct
        {
            uint32_t IPGT          : 7;  /* [ 6: 0],        r/w,       0x18 */
            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } IPGT;

    /* 0x10  reserved */
    uint8_t RESERVED0x10[8];

    /* 0x18 : PACKETLEN */
    union {
        struct
        {
            uint32_t MAXFL : 16; /* [15: 0],        r/w,      0x600 */
            uint32_t MINFL : 16; /* [31:16],        r/w,       0x40 */
        } BF;
        uint32_t WORD;
    } PACKETLEN;

    /* 0x1C : COLLCONFIG */
    union {
        struct
        {
            uint32_t COLLVALID      : 6;  /* [ 5: 0],        r/w,       0x3f */
            uint32_t reserved_6_15  : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t MAXRET         : 4;  /* [19:16],        r/w,        0xf */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } COLLCONFIG;

    /* 0x20 : TX_BD_NUM */
    union {
        struct
        {
            uint32_t TXBDNUM       : 8; /* [ 7: 0],        r/w,       0x40 */
            uint32_t reserved_8_15 : 8; /* [15: 8],       rsvd,        0x0 */
            uint32_t TXBDPTR       : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23   : 1; /* [   23],       rsvd,        0x0 */
            uint32_t RXBDPTR       : 7; /* [30:24],          r,        0x0 */
            uint32_t reserved_31   : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TX_BD_NUM;

    /* 0x24  reserved */
    uint8_t RESERVED0x24[4];

    /* 0x28 : MIIMODE */
    union {
        struct
        {
            uint32_t CLKDIV        : 8;  /* [ 7: 0],        r/w,       0x64 */
            uint32_t MIINOPRE      : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIIMODE;

    /* 0x2C : MIICOMMAND */
    union {
        struct
        {
            uint32_t SCANSTAT      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t RSTAT         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t WCTRLDATA     : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIICOMMAND;

    /* 0x30 : MIIADDRESS */
    union {
        struct
        {
            uint32_t FIAD           : 5;  /* [ 4: 0],        r/w,        0x0 */
            uint32_t reserved_5_7   : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t RGAD           : 5;  /* [12: 8],        r/w,        0x0 */
            uint32_t reserved_13_31 : 19; /* [31:13],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIIADDRESS;

    /* 0x34 : MIITX_DATA */
    union {
        struct
        {
            uint32_t CTRLDATA       : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIITX_DATA;

    /* 0x38 : MIIRX_DATA */
    union {
        struct
        {
            uint32_t PRSD           : 16; /* [15: 0],          r,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIIRX_DATA;

    /* 0x3C : MIISTATUS */
    union {
        struct
        {
            uint32_t MIIM_LINKFAIL : 1;  /* [    0],          r,        0x0 */
            uint32_t MIIM_BUSY     : 1;  /* [    1],          r,        0x0 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MIISTATUS;

    /* 0x40 : MAC_ADDR0 */
    union {
        struct
        {
            uint32_t MAC_B5 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t MAC_B4 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t MAC_B3 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t MAC_B2 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } MAC_ADDR0;

    /* 0x44 : MAC_ADDR1 */
    union {
        struct
        {
            uint32_t MAC_B1         : 8;  /* [ 7: 0],        r/w,        0x0 */
            uint32_t MAC_B0         : 8;  /* [15: 8],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MAC_ADDR1;

    /* 0x48 : HASH0_ADDR */
    union {
        struct
        {
            uint32_t HASH0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } HASH0_ADDR;

    /* 0x4C : HASH1_ADDR */
    union {
        struct
        {
            uint32_t HASH1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } HASH1_ADDR;

    /* 0x50 : TXCTRL */
    union {
        struct
        {
            uint32_t TXPAUSETV      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t TXPAUSERQ      : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31 : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TXCTRL;
};

typedef volatile struct emac_reg emac_reg_t;

#endif /* __EMAC_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/glb_reg.h
================================================
/**
  ******************************************************************************
  * @file    glb_reg.h
  * @version V1.2
  * @date    2020-07-08
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __GLB_REG_H__
#define __GLB_REG_H__

#include "bl702.h"

/* 0x0 : clk_cfg0 */
#define GLB_CLK_CFG0_OFFSET       (0x0)
#define GLB_REG_PLL_EN            GLB_REG_PLL_EN
#define GLB_REG_PLL_EN_POS        (0U)
#define GLB_REG_PLL_EN_LEN        (1U)
#define GLB_REG_PLL_EN_MSK        (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
#define GLB_REG_PLL_EN_UMSK       (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
#define GLB_REG_FCLK_EN           GLB_REG_FCLK_EN
#define GLB_REG_FCLK_EN_POS       (1U)
#define GLB_REG_FCLK_EN_LEN       (1U)
#define GLB_REG_FCLK_EN_MSK       (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
#define GLB_REG_FCLK_EN_UMSK      (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
#define GLB_REG_HCLK_EN           GLB_REG_HCLK_EN
#define GLB_REG_HCLK_EN_POS       (2U)
#define GLB_REG_HCLK_EN_LEN       (1U)
#define GLB_REG_HCLK_EN_MSK       (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
#define GLB_REG_HCLK_EN_UMSK      (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
#define GLB_REG_BCLK_EN           GLB_REG_BCLK_EN
#define GLB_REG_BCLK_EN_POS       (3U)
#define GLB_REG_BCLK_EN_LEN       (1U)
#define GLB_REG_BCLK_EN_MSK       (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
#define GLB_REG_BCLK_EN_UMSK      (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
#define GLB_REG_PLL_SEL           GLB_REG_PLL_SEL
#define GLB_REG_PLL_SEL_POS       (4U)
#define GLB_REG_PLL_SEL_LEN       (2U)
#define GLB_REG_PLL_SEL_MSK       (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
#define GLB_REG_PLL_SEL_UMSK      (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
#define GLB_HBN_ROOT_CLK_SEL      GLB_HBN_ROOT_CLK_SEL
#define GLB_HBN_ROOT_CLK_SEL_POS  (6U)
#define GLB_HBN_ROOT_CLK_SEL_LEN  (2U)
#define GLB_HBN_ROOT_CLK_SEL_MSK  (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
#define GLB_REG_HCLK_DIV          GLB_REG_HCLK_DIV
#define GLB_REG_HCLK_DIV_POS      (8U)
#define GLB_REG_HCLK_DIV_LEN      (8U)
#define GLB_REG_HCLK_DIV_MSK      (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
#define GLB_REG_HCLK_DIV_UMSK     (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
#define GLB_REG_BCLK_DIV          GLB_REG_BCLK_DIV
#define GLB_REG_BCLK_DIV_POS      (16U)
#define GLB_REG_BCLK_DIV_LEN      (8U)
#define GLB_REG_BCLK_DIV_MSK      (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
#define GLB_REG_BCLK_DIV_UMSK     (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
#define GLB_FCLK_SW_STATE         GLB_FCLK_SW_STATE
#define GLB_FCLK_SW_STATE_POS     (24U)
#define GLB_FCLK_SW_STATE_LEN     (3U)
#define GLB_FCLK_SW_STATE_MSK     (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
#define GLB_FCLK_SW_STATE_UMSK    (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
#define GLB_CHIP_RDY              GLB_CHIP_RDY
#define GLB_CHIP_RDY_POS          (27U)
#define GLB_CHIP_RDY_LEN          (1U)
#define GLB_CHIP_RDY_MSK          (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
#define GLB_CHIP_RDY_UMSK         (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
#define GLB_ID                    GLB_ID
#define GLB_ID_POS                (28U)
#define GLB_ID_LEN                (4U)
#define GLB_ID_MSK                (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
#define GLB_ID_UMSK               (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))

/* 0x4 : clk_cfg1 */
#define GLB_CLK_CFG1_OFFSET              (0x4)
#define GLB_QDEC_CLK_DIV                 GLB_QDEC_CLK_DIV
#define GLB_QDEC_CLK_DIV_POS             (0U)
#define GLB_QDEC_CLK_DIV_LEN             (5U)
#define GLB_QDEC_CLK_DIV_MSK             (((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS)
#define GLB_QDEC_CLK_DIV_UMSK            (~(((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS))
#define GLB_QDEC_CLK_SEL                 GLB_QDEC_CLK_SEL
#define GLB_QDEC_CLK_SEL_POS             (7U)
#define GLB_QDEC_CLK_SEL_LEN             (1U)
#define GLB_QDEC_CLK_SEL_MSK             (((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS)
#define GLB_QDEC_CLK_SEL_UMSK            (~(((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS))
#define GLB_USB_CLK_EN                   GLB_USB_CLK_EN
#define GLB_USB_CLK_EN_POS               (8U)
#define GLB_USB_CLK_EN_LEN               (1U)
#define GLB_USB_CLK_EN_MSK               (((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS)
#define GLB_USB_CLK_EN_UMSK              (~(((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS))
#define GLB_DLL_48M_DIV_EN               GLB_DLL_48M_DIV_EN
#define GLB_DLL_48M_DIV_EN_POS           (9U)
#define GLB_DLL_48M_DIV_EN_LEN           (1U)
#define GLB_DLL_48M_DIV_EN_MSK           (((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS)
#define GLB_DLL_48M_DIV_EN_UMSK          (~(((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS))
#define GLB_REG_I2S_CLK_SEL              GLB_REG_I2S_CLK_SEL
#define GLB_REG_I2S_CLK_SEL_POS          (12U)
#define GLB_REG_I2S_CLK_SEL_LEN          (1U)
#define GLB_REG_I2S_CLK_SEL_MSK          (((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS)
#define GLB_REG_I2S_CLK_SEL_UMSK         (~(((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS))
#define GLB_REG_I2S0_CLK_EN              GLB_REG_I2S0_CLK_EN
#define GLB_REG_I2S0_CLK_EN_POS          (13U)
#define GLB_REG_I2S0_CLK_EN_LEN          (1U)
#define GLB_REG_I2S0_CLK_EN_MSK          (((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS)
#define GLB_REG_I2S0_CLK_EN_UMSK         (~(((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS))
#define GLB_REG_I2S_0_REF_CLK_OE         GLB_REG_I2S_0_REF_CLK_OE
#define GLB_REG_I2S_0_REF_CLK_OE_POS     (14U)
#define GLB_REG_I2S_0_REF_CLK_OE_LEN     (1U)
#define GLB_REG_I2S_0_REF_CLK_OE_MSK     (((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS)
#define GLB_REG_I2S_0_REF_CLK_OE_UMSK    (~(((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS))
#define GLB_BLE_CLK_SEL                  GLB_BLE_CLK_SEL
#define GLB_BLE_CLK_SEL_POS              (16U)
#define GLB_BLE_CLK_SEL_LEN              (6U)
#define GLB_BLE_CLK_SEL_MSK              (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
#define GLB_BLE_CLK_SEL_UMSK             (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
#define GLB_BLE_EN                       GLB_BLE_EN
#define GLB_BLE_EN_POS                   (24U)
#define GLB_BLE_EN_LEN                   (1U)
#define GLB_BLE_EN_MSK                   (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
#define GLB_BLE_EN_UMSK                  (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
#define GLB_M154_ZBEN                    GLB_M154_ZBEN
#define GLB_M154_ZBEN_POS                (25U)
#define GLB_M154_ZBEN_LEN                (1U)
#define GLB_M154_ZBEN_MSK                (((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS)
#define GLB_M154_ZBEN_UMSK               (~(((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS))
#define GLB_REG_CAM_REF_CLK_EN           GLB_REG_CAM_REF_CLK_EN
#define GLB_REG_CAM_REF_CLK_EN_POS       (28U)
#define GLB_REG_CAM_REF_CLK_EN_LEN       (1U)
#define GLB_REG_CAM_REF_CLK_EN_MSK       (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)
#define GLB_REG_CAM_REF_CLK_EN_UMSK      (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS))
#define GLB_REG_CAM_REF_CLK_SRC_SEL      GLB_REG_CAM_REF_CLK_SRC_SEL
#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS  (29U)
#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN  (1U)
#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK  (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)
#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS))
#define GLB_REG_CAM_REF_CLK_DIV          GLB_REG_CAM_REF_CLK_DIV
#define GLB_REG_CAM_REF_CLK_DIV_POS      (30U)
#define GLB_REG_CAM_REF_CLK_DIV_LEN      (2U)
#define GLB_REG_CAM_REF_CLK_DIV_MSK      (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)
#define GLB_REG_CAM_REF_CLK_DIV_UMSK     (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS))

/* 0x8 : clk_cfg2 */
#define GLB_CLK_CFG2_OFFSET       (0x8)
#define GLB_UART_CLK_DIV          GLB_UART_CLK_DIV
#define GLB_UART_CLK_DIV_POS      (0U)
#define GLB_UART_CLK_DIV_LEN      (3U)
#define GLB_UART_CLK_DIV_MSK      (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
#define GLB_UART_CLK_DIV_UMSK     (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
#define GLB_UART_CLK_EN           GLB_UART_CLK_EN
#define GLB_UART_CLK_EN_POS       (4U)
#define GLB_UART_CLK_EN_LEN       (1U)
#define GLB_UART_CLK_EN_MSK       (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
#define GLB_UART_CLK_EN_UMSK      (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
#define GLB_HBN_UART_CLK_SEL      GLB_HBN_UART_CLK_SEL
#define GLB_HBN_UART_CLK_SEL_POS  (7U)
#define GLB_HBN_UART_CLK_SEL_LEN  (1U)
#define GLB_HBN_UART_CLK_SEL_MSK  (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
#define GLB_SF_CLK_DIV            GLB_SF_CLK_DIV
#define GLB_SF_CLK_DIV_POS        (8U)
#define GLB_SF_CLK_DIV_LEN        (3U)
#define GLB_SF_CLK_DIV_MSK        (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
#define GLB_SF_CLK_DIV_UMSK       (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
#define GLB_SF_CLK_EN             GLB_SF_CLK_EN
#define GLB_SF_CLK_EN_POS         (11U)
#define GLB_SF_CLK_EN_LEN         (1U)
#define GLB_SF_CLK_EN_MSK         (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
#define GLB_SF_CLK_EN_UMSK        (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
#define GLB_SF_CLK_SEL            GLB_SF_CLK_SEL
#define GLB_SF_CLK_SEL_POS        (12U)
#define GLB_SF_CLK_SEL_LEN        (2U)
#define GLB_SF_CLK_SEL_MSK        (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
#define GLB_SF_CLK_SEL_UMSK       (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
#define GLB_SF_CLK_SEL2           GLB_SF_CLK_SEL2
#define GLB_SF_CLK_SEL2_POS       (14U)
#define GLB_SF_CLK_SEL2_LEN       (2U)
#define GLB_SF_CLK_SEL2_MSK       (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
#define GLB_SF_CLK_SEL2_UMSK      (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
#define GLB_IR_CLK_DIV            GLB_IR_CLK_DIV
#define GLB_IR_CLK_DIV_POS        (16U)
#define GLB_IR_CLK_DIV_LEN        (6U)
#define GLB_IR_CLK_DIV_MSK        (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
#define GLB_IR_CLK_DIV_UMSK       (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
#define GLB_IR_CLK_EN             GLB_IR_CLK_EN
#define GLB_IR_CLK_EN_POS         (23U)
#define GLB_IR_CLK_EN_LEN         (1U)
#define GLB_IR_CLK_EN_MSK         (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
#define GLB_IR_CLK_EN_UMSK        (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
#define GLB_DMA_CLK_EN            GLB_DMA_CLK_EN
#define GLB_DMA_CLK_EN_POS        (24U)
#define GLB_DMA_CLK_EN_LEN        (8U)
#define GLB_DMA_CLK_EN_MSK        (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
#define GLB_DMA_CLK_EN_UMSK       (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))

/* 0xC : clk_cfg3 */
#define GLB_CLK_CFG3_OFFSET            (0xC)
#define GLB_SPI_CLK_DIV                GLB_SPI_CLK_DIV
#define GLB_SPI_CLK_DIV_POS            (0U)
#define GLB_SPI_CLK_DIV_LEN            (5U)
#define GLB_SPI_CLK_DIV_MSK            (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
#define GLB_SPI_CLK_DIV_UMSK           (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
#define GLB_CFG_SEL_ETH_REF_CLK_O      GLB_CFG_SEL_ETH_REF_CLK_O
#define GLB_CFG_SEL_ETH_REF_CLK_O_POS  (5U)
#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN  (1U)
#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)
#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS))
#define GLB_CFG_INV_ETH_REF_CLK_O      GLB_CFG_INV_ETH_REF_CLK_O
#define GLB_CFG_INV_ETH_REF_CLK_O_POS  (6U)
#define GLB_CFG_INV_ETH_REF_CLK_O_LEN  (1U)
#define GLB_CFG_INV_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)
#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS))
#define GLB_CFG_INV_ETH_TX_CLK         GLB_CFG_INV_ETH_TX_CLK
#define GLB_CFG_INV_ETH_TX_CLK_POS     (7U)
#define GLB_CFG_INV_ETH_TX_CLK_LEN     (1U)
#define GLB_CFG_INV_ETH_TX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)
#define GLB_CFG_INV_ETH_TX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS))
#define GLB_SPI_CLK_EN                 GLB_SPI_CLK_EN
#define GLB_SPI_CLK_EN_POS             (8U)
#define GLB_SPI_CLK_EN_LEN             (1U)
#define GLB_SPI_CLK_EN_MSK             (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
#define GLB_SPI_CLK_EN_UMSK            (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
#define GLB_CFG_INV_RF_TEST_CLK_O      GLB_CFG_INV_RF_TEST_CLK_O
#define GLB_CFG_INV_RF_TEST_CLK_O_POS  (9U)
#define GLB_CFG_INV_RF_TEST_CLK_O_LEN  (1U)
#define GLB_CFG_INV_RF_TEST_CLK_O_MSK  (((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS)
#define GLB_CFG_INV_RF_TEST_CLK_O_UMSK (~(((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS))
#define GLB_CFG_INV_ETH_RX_CLK         GLB_CFG_INV_ETH_RX_CLK
#define GLB_CFG_INV_ETH_RX_CLK_POS     (10U)
#define GLB_CFG_INV_ETH_RX_CLK_LEN     (1U)
#define GLB_CFG_INV_ETH_RX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)
#define GLB_CFG_INV_ETH_RX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS))
#define GLB_I2C_CLK_DIV                GLB_I2C_CLK_DIV
#define GLB_I2C_CLK_DIV_POS            (16U)
#define GLB_I2C_CLK_DIV_LEN            (8U)
#define GLB_I2C_CLK_DIV_MSK            (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
#define GLB_I2C_CLK_DIV_UMSK           (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
#define GLB_I2C_CLK_EN                 GLB_I2C_CLK_EN
#define GLB_I2C_CLK_EN_POS             (24U)
#define GLB_I2C_CLK_EN_LEN             (1U)
#define GLB_I2C_CLK_EN_MSK             (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
#define GLB_I2C_CLK_EN_UMSK            (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
#define GLB_CHIP_CLK_OUT_0_SEL         GLB_CHIP_CLK_OUT_0_SEL
#define GLB_CHIP_CLK_OUT_0_SEL_POS     (28U)
#define GLB_CHIP_CLK_OUT_0_SEL_LEN     (2U)
#define GLB_CHIP_CLK_OUT_0_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)
#define GLB_CHIP_CLK_OUT_0_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS))
#define GLB_CHIP_CLK_OUT_1_SEL         GLB_CHIP_CLK_OUT_1_SEL
#define GLB_CHIP_CLK_OUT_1_SEL_POS     (30U)
#define GLB_CHIP_CLK_OUT_1_SEL_LEN     (2U)
#define GLB_CHIP_CLK_OUT_1_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)
#define GLB_CHIP_CLK_OUT_1_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS))

/* 0x10 : swrst_cfg0 */
#define GLB_SWRST_CFG0_OFFSET (0x10)
#define GLB_SWRST_S00         GLB_SWRST_S00
#define GLB_SWRST_S00_POS     (0U)
#define GLB_SWRST_S00_LEN     (1U)
#define GLB_SWRST_S00_MSK     (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
#define GLB_SWRST_S00_UMSK    (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
#define GLB_SWRST_S01         GLB_SWRST_S01
#define GLB_SWRST_S01_POS     (1U)
#define GLB_SWRST_S01_LEN     (1U)
#define GLB_SWRST_S01_MSK     (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
#define GLB_SWRST_S01_UMSK    (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
#define GLB_SWRST_S20         GLB_SWRST_S20
#define GLB_SWRST_S20_POS     (4U)
#define GLB_SWRST_S20_LEN     (1U)
#define GLB_SWRST_S20_MSK     (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
#define GLB_SWRST_S20_UMSK    (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
#define GLB_SWRST_S30         GLB_SWRST_S30
#define GLB_SWRST_S30_POS     (8U)
#define GLB_SWRST_S30_LEN     (1U)
#define GLB_SWRST_S30_MSK     (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
#define GLB_SWRST_S30_UMSK    (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))

/* 0x14 : swrst_cfg1 */
#define GLB_SWRST_CFG1_OFFSET (0x14)
#define GLB_SWRST_S10         GLB_SWRST_S10
#define GLB_SWRST_S10_POS     (0U)
#define GLB_SWRST_S10_LEN     (1U)
#define GLB_SWRST_S10_MSK     (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
#define GLB_SWRST_S10_UMSK    (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
#define GLB_SWRST_S11         GLB_SWRST_S11
#define GLB_SWRST_S11_POS     (1U)
#define GLB_SWRST_S11_LEN     (1U)
#define GLB_SWRST_S11_MSK     (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
#define GLB_SWRST_S11_UMSK    (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
#define GLB_SWRST_S12         GLB_SWRST_S12
#define GLB_SWRST_S12_POS     (2U)
#define GLB_SWRST_S12_LEN     (1U)
#define GLB_SWRST_S12_MSK     (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
#define GLB_SWRST_S12_UMSK    (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
#define GLB_SWRST_S13         GLB_SWRST_S13
#define GLB_SWRST_S13_POS     (3U)
#define GLB_SWRST_S13_LEN     (1U)
#define GLB_SWRST_S13_MSK     (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
#define GLB_SWRST_S13_UMSK    (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
#define GLB_SWRST_S14         GLB_SWRST_S14
#define GLB_SWRST_S14_POS     (4U)
#define GLB_SWRST_S14_LEN     (1U)
#define GLB_SWRST_S14_MSK     (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
#define GLB_SWRST_S14_UMSK    (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
#define GLB_SWRST_S15         GLB_SWRST_S15
#define GLB_SWRST_S15_POS     (5U)
#define GLB_SWRST_S15_LEN     (1U)
#define GLB_SWRST_S15_MSK     (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
#define GLB_SWRST_S15_UMSK    (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
#define GLB_SWRST_S16         GLB_SWRST_S16
#define GLB_SWRST_S16_POS     (6U)
#define GLB_SWRST_S16_LEN     (1U)
#define GLB_SWRST_S16_MSK     (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
#define GLB_SWRST_S16_UMSK    (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
#define GLB_SWRST_S17         GLB_SWRST_S17
#define GLB_SWRST_S17_POS     (7U)
#define GLB_SWRST_S17_LEN     (1U)
#define GLB_SWRST_S17_MSK     (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
#define GLB_SWRST_S17_UMSK    (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
#define GLB_SWRST_S18         GLB_SWRST_S18
#define GLB_SWRST_S18_POS     (8U)
#define GLB_SWRST_S18_LEN     (1U)
#define GLB_SWRST_S18_MSK     (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
#define GLB_SWRST_S18_UMSK    (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
#define GLB_SWRST_S19         GLB_SWRST_S19
#define GLB_SWRST_S19_POS     (9U)
#define GLB_SWRST_S19_LEN     (1U)
#define GLB_SWRST_S19_MSK     (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
#define GLB_SWRST_S19_UMSK    (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
#define GLB_SWRST_S1A         GLB_SWRST_S1A
#define GLB_SWRST_S1A_POS     (10U)
#define GLB_SWRST_S1A_LEN     (1U)
#define GLB_SWRST_S1A_MSK     (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
#define GLB_SWRST_S1A_UMSK    (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
#define GLB_SWRST_S1B         GLB_SWRST_S1B
#define GLB_SWRST_S1B_POS     (11U)
#define GLB_SWRST_S1B_LEN     (1U)
#define GLB_SWRST_S1B_MSK     (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
#define GLB_SWRST_S1B_UMSK    (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
#define GLB_SWRST_S1C         GLB_SWRST_S1C
#define GLB_SWRST_S1C_POS     (12U)
#define GLB_SWRST_S1C_LEN     (1U)
#define GLB_SWRST_S1C_MSK     (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
#define GLB_SWRST_S1C_UMSK    (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
#define GLB_SWRST_S1D         GLB_SWRST_S1D
#define GLB_SWRST_S1D_POS     (13U)
#define GLB_SWRST_S1D_LEN     (1U)
#define GLB_SWRST_S1D_MSK     (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
#define GLB_SWRST_S1D_UMSK    (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
#define GLB_SWRST_S1E         GLB_SWRST_S1E
#define GLB_SWRST_S1E_POS     (14U)
#define GLB_SWRST_S1E_LEN     (1U)
#define GLB_SWRST_S1E_MSK     (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
#define GLB_SWRST_S1E_UMSK    (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
#define GLB_SWRST_S1F         GLB_SWRST_S1F
#define GLB_SWRST_S1F_POS     (15U)
#define GLB_SWRST_S1F_LEN     (1U)
#define GLB_SWRST_S1F_MSK     (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
#define GLB_SWRST_S1F_UMSK    (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
#define GLB_SWRST_S1A0        GLB_SWRST_S1A0
#define GLB_SWRST_S1A0_POS    (16U)
#define GLB_SWRST_S1A0_LEN    (1U)
#define GLB_SWRST_S1A0_MSK    (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
#define GLB_SWRST_S1A0_UMSK   (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
#define GLB_SWRST_S1A1        GLB_SWRST_S1A1
#define GLB_SWRST_S1A1_POS    (17U)
#define GLB_SWRST_S1A1_LEN    (1U)
#define GLB_SWRST_S1A1_MSK    (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
#define GLB_SWRST_S1A1_UMSK   (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
#define GLB_SWRST_S1A2        GLB_SWRST_S1A2
#define GLB_SWRST_S1A2_POS    (18U)
#define GLB_SWRST_S1A2_LEN    (1U)
#define GLB_SWRST_S1A2_MSK    (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
#define GLB_SWRST_S1A2_UMSK   (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
#define GLB_SWRST_S1A3        GLB_SWRST_S1A3
#define GLB_SWRST_S1A3_POS    (19U)
#define GLB_SWRST_S1A3_LEN    (1U)
#define GLB_SWRST_S1A3_MSK    (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
#define GLB_SWRST_S1A3_UMSK   (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
#define GLB_SWRST_S1A4        GLB_SWRST_S1A4
#define GLB_SWRST_S1A4_POS    (20U)
#define GLB_SWRST_S1A4_LEN    (1U)
#define GLB_SWRST_S1A4_MSK    (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
#define GLB_SWRST_S1A4_UMSK   (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
#define GLB_SWRST_S1A5        GLB_SWRST_S1A5
#define GLB_SWRST_S1A5_POS    (21U)
#define GLB_SWRST_S1A5_LEN    (1U)
#define GLB_SWRST_S1A5_MSK    (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
#define GLB_SWRST_S1A5_UMSK   (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
#define GLB_SWRST_S1A6        GLB_SWRST_S1A6
#define GLB_SWRST_S1A6_POS    (22U)
#define GLB_SWRST_S1A6_LEN    (1U)
#define GLB_SWRST_S1A6_MSK    (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
#define GLB_SWRST_S1A6_UMSK   (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
#define GLB_SWRST_S1A7        GLB_SWRST_S1A7
#define GLB_SWRST_S1A7_POS    (23U)
#define GLB_SWRST_S1A7_LEN    (1U)
#define GLB_SWRST_S1A7_MSK    (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
#define GLB_SWRST_S1A7_UMSK   (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
#define GLB_SWRST_S1A8        GLB_SWRST_S1A8
#define GLB_SWRST_S1A8_POS    (24U)
#define GLB_SWRST_S1A8_LEN    (1U)
#define GLB_SWRST_S1A8_MSK    (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)
#define GLB_SWRST_S1A8_UMSK   (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS))
#define GLB_SWRST_S1A9        GLB_SWRST_S1A9
#define GLB_SWRST_S1A9_POS    (25U)
#define GLB_SWRST_S1A9_LEN    (1U)
#define GLB_SWRST_S1A9_MSK    (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)
#define GLB_SWRST_S1A9_UMSK   (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS))
#define GLB_SWRST_S1AA        GLB_SWRST_S1AA
#define GLB_SWRST_S1AA_POS    (26U)
#define GLB_SWRST_S1AA_LEN    (1U)
#define GLB_SWRST_S1AA_MSK    (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)
#define GLB_SWRST_S1AA_UMSK   (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS))
#define GLB_SWRST_S1AB        GLB_SWRST_S1AB
#define GLB_SWRST_S1AB_POS    (27U)
#define GLB_SWRST_S1AB_LEN    (1U)
#define GLB_SWRST_S1AB_MSK    (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)
#define GLB_SWRST_S1AB_UMSK   (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS))
#define GLB_SWRST_S1AC        GLB_SWRST_S1AC
#define GLB_SWRST_S1AC_POS    (28U)
#define GLB_SWRST_S1AC_LEN    (1U)
#define GLB_SWRST_S1AC_MSK    (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)
#define GLB_SWRST_S1AC_UMSK   (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS))
#define GLB_SWRST_S1AD        GLB_SWRST_S1AD
#define GLB_SWRST_S1AD_POS    (29U)
#define GLB_SWRST_S1AD_LEN    (1U)
#define GLB_SWRST_S1AD_MSK    (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)
#define GLB_SWRST_S1AD_UMSK   (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS))
#define GLB_SWRST_S1AE        GLB_SWRST_S1AE
#define GLB_SWRST_S1AE_POS    (30U)
#define GLB_SWRST_S1AE_LEN    (1U)
#define GLB_SWRST_S1AE_MSK    (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)
#define GLB_SWRST_S1AE_UMSK   (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS))

/* 0x18 : swrst_cfg2 */
#define GLB_SWRST_CFG2_OFFSET         (0x18)
#define GLB_REG_CTRL_PWRON_RST        GLB_REG_CTRL_PWRON_RST
#define GLB_REG_CTRL_PWRON_RST_POS    (0U)
#define GLB_REG_CTRL_PWRON_RST_LEN    (1U)
#define GLB_REG_CTRL_PWRON_RST_MSK    (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
#define GLB_REG_CTRL_PWRON_RST_UMSK   (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
#define GLB_REG_CTRL_CPU_RESET        GLB_REG_CTRL_CPU_RESET
#define GLB_REG_CTRL_CPU_RESET_POS    (1U)
#define GLB_REG_CTRL_CPU_RESET_LEN    (1U)
#define GLB_REG_CTRL_CPU_RESET_MSK    (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
#define GLB_REG_CTRL_CPU_RESET_UMSK   (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
#define GLB_REG_CTRL_SYS_RESET        GLB_REG_CTRL_SYS_RESET
#define GLB_REG_CTRL_SYS_RESET_POS    (2U)
#define GLB_REG_CTRL_SYS_RESET_LEN    (1U)
#define GLB_REG_CTRL_SYS_RESET_MSK    (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
#define GLB_REG_CTRL_SYS_RESET_UMSK   (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
#define GLB_REG_CTRL_RESET_DUMMY      GLB_REG_CTRL_RESET_DUMMY
#define GLB_REG_CTRL_RESET_DUMMY_POS  (4U)
#define GLB_REG_CTRL_RESET_DUMMY_LEN  (4U)
#define GLB_REG_CTRL_RESET_DUMMY_MSK  (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
#define GLB_PKA_CLK_SEL               GLB_PKA_CLK_SEL
#define GLB_PKA_CLK_SEL_POS           (24U)
#define GLB_PKA_CLK_SEL_LEN           (1U)
#define GLB_PKA_CLK_SEL_MSK           (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
#define GLB_PKA_CLK_SEL_UMSK          (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))

/* 0x1C : swrst_cfg3 */
#define GLB_SWRST_CFG3_OFFSET (0x1C)

/* 0x20 : cgen_cfg0 */
#define GLB_CGEN_CFG0_OFFSET (0x20)
#define GLB_CGEN_M           GLB_CGEN_M
#define GLB_CGEN_M_POS       (0U)
#define GLB_CGEN_M_LEN       (8U)
#define GLB_CGEN_M_MSK       (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
#define GLB_CGEN_M_UMSK      (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))

/* 0x24 : cgen_cfg1 */
#define GLB_CGEN_CFG1_OFFSET (0x24)
#define GLB_CGEN_S1          GLB_CGEN_S1
#define GLB_CGEN_S1_POS      (0U)
#define GLB_CGEN_S1_LEN      (16U)
#define GLB_CGEN_S1_MSK      (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
#define GLB_CGEN_S1_UMSK     (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
#define GLB_CGEN_S1A         GLB_CGEN_S1A
#define GLB_CGEN_S1A_POS     (16U)
#define GLB_CGEN_S1A_LEN     (16U)
#define GLB_CGEN_S1A_MSK     (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
#define GLB_CGEN_S1A_UMSK    (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))

/* 0x28 : cgen_cfg2 */
#define GLB_CGEN_CFG2_OFFSET (0x28)
#define GLB_CGEN_S2          GLB_CGEN_S2
#define GLB_CGEN_S2_POS      (0U)
#define GLB_CGEN_S2_LEN      (1U)
#define GLB_CGEN_S2_MSK      (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
#define GLB_CGEN_S2_UMSK     (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
#define GLB_CGEN_S3          GLB_CGEN_S3
#define GLB_CGEN_S3_POS      (4U)
#define GLB_CGEN_S3_LEN      (1U)
#define GLB_CGEN_S3_MSK      (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
#define GLB_CGEN_S3_UMSK     (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))

/* 0x2C : cgen_cfg3 */
#define GLB_CGEN_CFG3_OFFSET (0x2C)

/* 0x30 : MBIST_CTL */
#define GLB_MBIST_CTL_OFFSET            (0x30)
#define GLB_IROM_MBIST_MODE             GLB_IROM_MBIST_MODE
#define GLB_IROM_MBIST_MODE_POS         (0U)
#define GLB_IROM_MBIST_MODE_LEN         (1U)
#define GLB_IROM_MBIST_MODE_MSK         (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
#define GLB_IROM_MBIST_MODE_UMSK        (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
#define GLB_HSRAM_MEM_MBIST_MODE        GLB_HSRAM_MEM_MBIST_MODE
#define GLB_HSRAM_MEM_MBIST_MODE_POS    (1U)
#define GLB_HSRAM_MEM_MBIST_MODE_LEN    (1U)
#define GLB_HSRAM_MEM_MBIST_MODE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS)
#define GLB_HSRAM_MEM_MBIST_MODE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS))
#define GLB_HSRAM_CACHE_MBIST_MODE      GLB_HSRAM_CACHE_MBIST_MODE
#define GLB_HSRAM_CACHE_MBIST_MODE_POS  (2U)
#define GLB_HSRAM_CACHE_MBIST_MODE_LEN  (1U)
#define GLB_HSRAM_CACHE_MBIST_MODE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS)
#define GLB_HSRAM_CACHE_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS))
#define GLB_TAG_MBIST_MODE              GLB_TAG_MBIST_MODE
#define GLB_TAG_MBIST_MODE_POS          (3U)
#define GLB_TAG_MBIST_MODE_LEN          (1U)
#define GLB_TAG_MBIST_MODE_MSK          (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
#define GLB_TAG_MBIST_MODE_UMSK         (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
#define GLB_OCRAM_MBIST_MODE            GLB_OCRAM_MBIST_MODE
#define GLB_OCRAM_MBIST_MODE_POS        (4U)
#define GLB_OCRAM_MBIST_MODE_LEN        (1U)
#define GLB_OCRAM_MBIST_MODE_MSK        (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
#define GLB_OCRAM_MBIST_MODE_UMSK       (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
#define GLB_EM_RAM_MBIST_MODE           GLB_EM_RAM_MBIST_MODE
#define GLB_EM_RAM_MBIST_MODE_POS       (5U)
#define GLB_EM_RAM_MBIST_MODE_LEN       (1U)
#define GLB_EM_RAM_MBIST_MODE_MSK       (((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS)
#define GLB_EM_RAM_MBIST_MODE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS))
#define GLB_REG_MBIST_RST_N             GLB_REG_MBIST_RST_N
#define GLB_REG_MBIST_RST_N_POS         (31U)
#define GLB_REG_MBIST_RST_N_LEN         (1U)
#define GLB_REG_MBIST_RST_N_MSK         (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
#define GLB_REG_MBIST_RST_N_UMSK        (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))

/* 0x34 : MBIST_STAT */
#define GLB_MBIST_STAT_OFFSET           (0x34)
#define GLB_IROM_MBIST_DONE             GLB_IROM_MBIST_DONE
#define GLB_IROM_MBIST_DONE_POS         (0U)
#define GLB_IROM_MBIST_DONE_LEN         (1U)
#define GLB_IROM_MBIST_DONE_MSK         (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
#define GLB_IROM_MBIST_DONE_UMSK        (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
#define GLB_HSRAM_MEM_MBIST_DONE        GLB_HSRAM_MEM_MBIST_DONE
#define GLB_HSRAM_MEM_MBIST_DONE_POS    (1U)
#define GLB_HSRAM_MEM_MBIST_DONE_LEN    (1U)
#define GLB_HSRAM_MEM_MBIST_DONE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS)
#define GLB_HSRAM_MEM_MBIST_DONE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS))
#define GLB_HSRAM_CACHE_MBIST_DONE      GLB_HSRAM_CACHE_MBIST_DONE
#define GLB_HSRAM_CACHE_MBIST_DONE_POS  (2U)
#define GLB_HSRAM_CACHE_MBIST_DONE_LEN  (1U)
#define GLB_HSRAM_CACHE_MBIST_DONE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS)
#define GLB_HSRAM_CACHE_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS))
#define GLB_TAG_MBIST_DONE              GLB_TAG_MBIST_DONE
#define GLB_TAG_MBIST_DONE_POS          (3U)
#define GLB_TAG_MBIST_DONE_LEN          (1U)
#define GLB_TAG_MBIST_DONE_MSK          (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
#define GLB_TAG_MBIST_DONE_UMSK         (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
#define GLB_OCRAM_MBIST_DONE            GLB_OCRAM_MBIST_DONE
#define GLB_OCRAM_MBIST_DONE_POS        (4U)
#define GLB_OCRAM_MBIST_DONE_LEN        (1U)
#define GLB_OCRAM_MBIST_DONE_MSK        (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
#define GLB_OCRAM_MBIST_DONE_UMSK       (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
#define GLB_EM_RAM_MBIST_DONE           GLB_EM_RAM_MBIST_DONE
#define GLB_EM_RAM_MBIST_DONE_POS       (5U)
#define GLB_EM_RAM_MBIST_DONE_LEN       (1U)
#define GLB_EM_RAM_MBIST_DONE_MSK       (((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS)
#define GLB_EM_RAM_MBIST_DONE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS))
#define GLB_IROM_MBIST_FAIL             GLB_IROM_MBIST_FAIL
#define GLB_IROM_MBIST_FAIL_POS         (16U)
#define GLB_IROM_MBIST_FAIL_LEN         (1U)
#define GLB_IROM_MBIST_FAIL_MSK         (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
#define GLB_IROM_MBIST_FAIL_UMSK        (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
#define GLB_HSRAM_MEM_MBIST_FAIL        GLB_HSRAM_MEM_MBIST_FAIL
#define GLB_HSRAM_MEM_MBIST_FAIL_POS    (17U)
#define GLB_HSRAM_MEM_MBIST_FAIL_LEN    (1U)
#define GLB_HSRAM_MEM_MBIST_FAIL_MSK    (((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS)
#define GLB_HSRAM_MEM_MBIST_FAIL_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS))
#define GLB_HSRAM_CACHE_MBIST_FAIL      GLB_HSRAM_CACHE_MBIST_FAIL
#define GLB_HSRAM_CACHE_MBIST_FAIL_POS  (18U)
#define GLB_HSRAM_CACHE_MBIST_FAIL_LEN  (1U)
#define GLB_HSRAM_CACHE_MBIST_FAIL_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS)
#define GLB_HSRAM_CACHE_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS))
#define GLB_TAG_MBIST_FAIL              GLB_TAG_MBIST_FAIL
#define GLB_TAG_MBIST_FAIL_POS          (19U)
#define GLB_TAG_MBIST_FAIL_LEN          (1U)
#define GLB_TAG_MBIST_FAIL_MSK          (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
#define GLB_TAG_MBIST_FAIL_UMSK         (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
#define GLB_OCRAM_MBIST_FAIL            GLB_OCRAM_MBIST_FAIL
#define GLB_OCRAM_MBIST_FAIL_POS        (20U)
#define GLB_OCRAM_MBIST_FAIL_LEN        (1U)
#define GLB_OCRAM_MBIST_FAIL_MSK        (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
#define GLB_OCRAM_MBIST_FAIL_UMSK       (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
#define GLB_EM_RAM_MBIST_FAIL           GLB_EM_RAM_MBIST_FAIL
#define GLB_EM_RAM_MBIST_FAIL_POS       (21U)
#define GLB_EM_RAM_MBIST_FAIL_LEN       (1U)
#define GLB_EM_RAM_MBIST_FAIL_MSK       (((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS)
#define GLB_EM_RAM_MBIST_FAIL_UMSK      (~(((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS))

/* 0x50 : bmx_cfg1 */
#define GLB_BMX_CFG1_OFFSET          (0x50)
#define GLB_BMX_TIMEOUT_EN           GLB_BMX_TIMEOUT_EN
#define GLB_BMX_TIMEOUT_EN_POS       (0U)
#define GLB_BMX_TIMEOUT_EN_LEN       (4U)
#define GLB_BMX_TIMEOUT_EN_MSK       (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
#define GLB_BMX_TIMEOUT_EN_UMSK      (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
#define GLB_BMX_ARB_MODE             GLB_BMX_ARB_MODE
#define GLB_BMX_ARB_MODE_POS         (4U)
#define GLB_BMX_ARB_MODE_LEN         (2U)
#define GLB_BMX_ARB_MODE_MSK         (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
#define GLB_BMX_ARB_MODE_UMSK        (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
#define GLB_BMX_ERR_EN               GLB_BMX_ERR_EN
#define GLB_BMX_ERR_EN_POS           (8U)
#define GLB_BMX_ERR_EN_LEN           (1U)
#define GLB_BMX_ERR_EN_MSK           (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
#define GLB_BMX_ERR_EN_UMSK          (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
#define GLB_BMX_BUSY_OPTION_DIS      GLB_BMX_BUSY_OPTION_DIS
#define GLB_BMX_BUSY_OPTION_DIS_POS  (9U)
#define GLB_BMX_BUSY_OPTION_DIS_LEN  (1U)
#define GLB_BMX_BUSY_OPTION_DIS_MSK  (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
#define GLB_BMX_GATING_DIS           GLB_BMX_GATING_DIS
#define GLB_BMX_GATING_DIS_POS       (10U)
#define GLB_BMX_GATING_DIS_LEN       (1U)
#define GLB_BMX_GATING_DIS_MSK       (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
#define GLB_BMX_GATING_DIS_UMSK      (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
#define GLB_HSEL_OPTION              GLB_HSEL_OPTION
#define GLB_HSEL_OPTION_POS          (12U)
#define GLB_HSEL_OPTION_LEN          (4U)
#define GLB_HSEL_OPTION_MSK          (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
#define GLB_HSEL_OPTION_UMSK         (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
#define GLB_PDS_APB_CFG              GLB_PDS_APB_CFG
#define GLB_PDS_APB_CFG_POS          (16U)
#define GLB_PDS_APB_CFG_LEN          (8U)
#define GLB_PDS_APB_CFG_MSK          (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
#define GLB_PDS_APB_CFG_UMSK         (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
#define GLB_HBN_APB_CFG              GLB_HBN_APB_CFG
#define GLB_HBN_APB_CFG_POS          (24U)
#define GLB_HBN_APB_CFG_LEN          (8U)
#define GLB_HBN_APB_CFG_MSK          (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
#define GLB_HBN_APB_CFG_UMSK         (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))

/* 0x54 : bmx_cfg2 */
#define GLB_BMX_CFG2_OFFSET       (0x54)
#define GLB_BMX_ERR_ADDR_DIS      GLB_BMX_ERR_ADDR_DIS
#define GLB_BMX_ERR_ADDR_DIS_POS  (0U)
#define GLB_BMX_ERR_ADDR_DIS_LEN  (1U)
#define GLB_BMX_ERR_ADDR_DIS_MSK  (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
#define GLB_BMX_ERR_DEC           GLB_BMX_ERR_DEC
#define GLB_BMX_ERR_DEC_POS       (4U)
#define GLB_BMX_ERR_DEC_LEN       (1U)
#define GLB_BMX_ERR_DEC_MSK       (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
#define GLB_BMX_ERR_DEC_UMSK      (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
#define GLB_BMX_ERR_TZ            GLB_BMX_ERR_TZ
#define GLB_BMX_ERR_TZ_POS        (5U)
#define GLB_BMX_ERR_TZ_LEN        (1U)
#define GLB_BMX_ERR_TZ_MSK        (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
#define GLB_BMX_ERR_TZ_UMSK       (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
#define GLB_REG_W_THRE_BMX        GLB_REG_W_THRE_BMX
#define GLB_REG_W_THRE_BMX_POS    (8U)
#define GLB_REG_W_THRE_BMX_LEN    (2U)
#define GLB_REG_W_THRE_BMX_MSK    (((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS)
#define GLB_REG_W_THRE_BMX_UMSK   (~(((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS))
#define GLB_REG_W_THRE_L1C        GLB_REG_W_THRE_L1C
#define GLB_REG_W_THRE_L1C_POS    (10U)
#define GLB_REG_W_THRE_L1C_LEN    (2U)
#define GLB_REG_W_THRE_L1C_MSK    (((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS)
#define GLB_REG_W_THRE_L1C_UMSK   (~(((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS))
#define GLB_BMX_DBG_SEL           GLB_BMX_DBG_SEL
#define GLB_BMX_DBG_SEL_POS       (28U)
#define GLB_BMX_DBG_SEL_LEN       (4U)
#define GLB_BMX_DBG_SEL_MSK       (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
#define GLB_BMX_DBG_SEL_UMSK      (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))

/* 0x58 : bmx_err_addr */
#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
#define GLB_BMX_ERR_ADDR        GLB_BMX_ERR_ADDR
#define GLB_BMX_ERR_ADDR_POS    (0U)
#define GLB_BMX_ERR_ADDR_LEN    (32U)
#define GLB_BMX_ERR_ADDR_MSK    (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
#define GLB_BMX_ERR_ADDR_UMSK   (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))

/* 0x5C : bmx_dbg_out */
#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
#define GLB_BMX_DBG_OUT        GLB_BMX_DBG_OUT
#define GLB_BMX_DBG_OUT_POS    (0U)
#define GLB_BMX_DBG_OUT_LEN    (32U)
#define GLB_BMX_DBG_OUT_MSK    (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
#define GLB_BMX_DBG_OUT_UMSK   (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))

/* 0x60 : rsv0 */
#define GLB_RSV0_OFFSET (0x60)

/* 0x64 : rsv1 */
#define GLB_RSV1_OFFSET (0x64)

/* 0x68 : rsv2 */
#define GLB_RSV2_OFFSET (0x68)

/* 0x6C : rsv3 */
#define GLB_RSV3_OFFSET (0x6C)

/* 0x70 : sram_ret */
#define GLB_SRAM_RET_OFFSET   (0x70)
#define GLB_REG_SRAM_RET      GLB_REG_SRAM_RET
#define GLB_REG_SRAM_RET_POS  (0U)
#define GLB_REG_SRAM_RET_LEN  (32U)
#define GLB_REG_SRAM_RET_MSK  (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))

/* 0x74 : sram_slp */
#define GLB_SRAM_SLP_OFFSET   (0x74)
#define GLB_REG_SRAM_SLP      GLB_REG_SRAM_SLP
#define GLB_REG_SRAM_SLP_POS  (0U)
#define GLB_REG_SRAM_SLP_LEN  (32U)
#define GLB_REG_SRAM_SLP_MSK  (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))

/* 0x78 : sram_parm */
#define GLB_SRAM_PARM_OFFSET   (0x78)
#define GLB_REG_SRAM_PARM      GLB_REG_SRAM_PARM
#define GLB_REG_SRAM_PARM_POS  (0U)
#define GLB_REG_SRAM_PARM_LEN  (32U)
#define GLB_REG_SRAM_PARM_MSK  (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))

/* 0x7C : seam_misc */
#define GLB_SEAM_MISC_OFFSET (0x7C)
#define GLB_EM_SEL           GLB_EM_SEL
#define GLB_EM_SEL_POS       (0U)
#define GLB_EM_SEL_LEN       (4U)
#define GLB_EM_SEL_MSK       (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
#define GLB_EM_SEL_UMSK      (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))

/* 0x80 : glb_parm */
#define GLB_PARM_OFFSET                   (0x80)
#define GLB_JTAG_SWAP_SET                 GLB_JTAG_SWAP_SET
#define GLB_JTAG_SWAP_SET_POS             (0U)
#define GLB_JTAG_SWAP_SET_LEN             (8U)
#define GLB_JTAG_SWAP_SET_MSK             (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
#define GLB_JTAG_SWAP_SET_UMSK            (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
#define GLB_CFG_SFLASH2_SWAP_IO0_IO3      GLB_CFG_SFLASH2_SWAP_IO0_IO3
#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS  (8U)
#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN  (1U)
#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_MSK  (((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS)
#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_UMSK (~(((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS))
#define GLB_CFG_SFLASH2_SWAP_CS_IO2       GLB_CFG_SFLASH2_SWAP_CS_IO2
#define GLB_CFG_SFLASH2_SWAP_CS_IO2_POS   (9U)
#define GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN   (1U)
#define GLB_CFG_SFLASH2_SWAP_CS_IO2_MSK   (((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS)
#define GLB_CFG_SFLASH2_SWAP_CS_IO2_UMSK  (~(((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS))
#define GLB_CFG_FLASH_SCENARIO            GLB_CFG_FLASH_SCENARIO
#define GLB_CFG_FLASH_SCENARIO_POS        (10U)
#define GLB_CFG_FLASH_SCENARIO_LEN        (2U)
#define GLB_CFG_FLASH_SCENARIO_MSK        (((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS)
#define GLB_CFG_FLASH_SCENARIO_UMSK       (~(((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS))
#define GLB_REG_SPI_0_MASTER_MODE         GLB_REG_SPI_0_MASTER_MODE
#define GLB_REG_SPI_0_MASTER_MODE_POS     (12U)
#define GLB_REG_SPI_0_MASTER_MODE_LEN     (1U)
#define GLB_REG_SPI_0_MASTER_MODE_MSK     (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
#define GLB_REG_SPI_0_MASTER_MODE_UMSK    (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
#define GLB_REG_SPI_0_SWAP                GLB_REG_SPI_0_SWAP
#define GLB_REG_SPI_0_SWAP_POS            (13U)
#define GLB_REG_SPI_0_SWAP_LEN            (1U)
#define GLB_REG_SPI_0_SWAP_MSK            (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
#define GLB_REG_SPI_0_SWAP_UMSK           (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
#define GLB_REG_CCI_USE_JTAG_PIN          GLB_REG_CCI_USE_JTAG_PIN
#define GLB_REG_CCI_USE_JTAG_PIN_POS      (16U)
#define GLB_REG_CCI_USE_JTAG_PIN_LEN      (1U)
#define GLB_REG_CCI_USE_JTAG_PIN_MSK      (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
#define GLB_REG_CCI_USE_JTAG_PIN_UMSK     (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS))
#define GLB_P1_ADC_TEST_WITH_CCI          GLB_P1_ADC_TEST_WITH_CCI
#define GLB_P1_ADC_TEST_WITH_CCI_POS      (17U)
#define GLB_P1_ADC_TEST_WITH_CCI_LEN      (1U)
#define GLB_P1_ADC_TEST_WITH_CCI_MSK      (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
#define GLB_P1_ADC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS))
#define GLB_P2_DAC_TEST_WITH_CCI          GLB_P2_DAC_TEST_WITH_CCI
#define GLB_P2_DAC_TEST_WITH_CCI_POS      (18U)
#define GLB_P2_DAC_TEST_WITH_CCI_LEN      (1U)
#define GLB_P2_DAC_TEST_WITH_CCI_MSK      (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
#define GLB_P2_DAC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS))
#define GLB_P3_CCI_USE_IO_0_2_7           GLB_P3_CCI_USE_IO_0_2_7
#define GLB_P3_CCI_USE_IO_0_2_7_POS       (19U)
#define GLB_P3_CCI_USE_IO_0_2_7_LEN       (1U)
#define GLB_P3_CCI_USE_IO_0_2_7_MSK       (((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS)
#define GLB_P3_CCI_USE_IO_0_2_7_UMSK      (~(((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS))
#define GLB_P4_ADC_TEST_WITH_JTAG         GLB_P4_ADC_TEST_WITH_JTAG
#define GLB_P4_ADC_TEST_WITH_JTAG_POS     (20U)
#define GLB_P4_ADC_TEST_WITH_JTAG_LEN     (1U)
#define GLB_P4_ADC_TEST_WITH_JTAG_MSK     (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)
#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS))
#define GLB_P5_DAC_TEST_WITH_JTAG         GLB_P5_DAC_TEST_WITH_JTAG
#define GLB_P5_DAC_TEST_WITH_JTAG_POS     (21U)
#define GLB_P5_DAC_TEST_WITH_JTAG_LEN     (1U)
#define GLB_P5_DAC_TEST_WITH_JTAG_MSK     (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)
#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS))
#define GLB_P6_JTAG_USE_IO_0_2_7          GLB_P6_JTAG_USE_IO_0_2_7
#define GLB_P6_JTAG_USE_IO_0_2_7_POS      (23U)
#define GLB_P6_JTAG_USE_IO_0_2_7_LEN      (1U)
#define GLB_P6_JTAG_USE_IO_0_2_7_MSK      (((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS)
#define GLB_P6_JTAG_USE_IO_0_2_7_UMSK     (~(((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS))
#define GLB_UART_SWAP_SET                 GLB_UART_SWAP_SET
#define GLB_UART_SWAP_SET_POS             (24U)
#define GLB_UART_SWAP_SET_LEN             (4U)
#define GLB_UART_SWAP_SET_MSK             (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
#define GLB_UART_SWAP_SET_UMSK            (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
#define GLB_REG_KYS_DRV_VAL               GLB_REG_KYS_DRV_VAL
#define GLB_REG_KYS_DRV_VAL_POS           (29U)
#define GLB_REG_KYS_DRV_VAL_LEN           (1U)
#define GLB_REG_KYS_DRV_VAL_MSK           (((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS)
#define GLB_REG_KYS_DRV_VAL_UMSK          (~(((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS))
#define GLB_REG_EXT_RST_SMT               GLB_REG_EXT_RST_SMT
#define GLB_REG_EXT_RST_SMT_POS           (30U)
#define GLB_REG_EXT_RST_SMT_LEN           (1U)
#define GLB_REG_EXT_RST_SMT_MSK           (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
#define GLB_REG_EXT_RST_SMT_UMSK          (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
#define GLB_PIN_SEL_EMAC_CAM              GLB_PIN_SEL_EMAC_CAM
#define GLB_PIN_SEL_EMAC_CAM_POS          (31U)
#define GLB_PIN_SEL_EMAC_CAM_LEN          (1U)
#define GLB_PIN_SEL_EMAC_CAM_MSK          (((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS)
#define GLB_PIN_SEL_EMAC_CAM_UMSK         (~(((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS))

/* 0x84 : PDM_CLK_CTRL */
#define GLB_PDM_CLK_CTRL_OFFSET   (0x84)
#define GLB_REG_PDM0_CLK_DIV      GLB_REG_PDM0_CLK_DIV
#define GLB_REG_PDM0_CLK_DIV_POS  (0U)
#define GLB_REG_PDM0_CLK_DIV_LEN  (6U)
#define GLB_REG_PDM0_CLK_DIV_MSK  (((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS)
#define GLB_REG_PDM0_CLK_DIV_UMSK (~(((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS))
#define GLB_REG_PDM0_CLK_EN       GLB_REG_PDM0_CLK_EN
#define GLB_REG_PDM0_CLK_EN_POS   (7U)
#define GLB_REG_PDM0_CLK_EN_LEN   (1U)
#define GLB_REG_PDM0_CLK_EN_MSK   (((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS)
#define GLB_REG_PDM0_CLK_EN_UMSK  (~(((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS))

/* 0x88 : GPIO_USE_PSRAM__IO */
#define GLB_GPIO_USE_PSRAM__IO_OFFSET  (0x88)
#define GLB_CFG_GPIO_USE_PSRAM_IO      GLB_CFG_GPIO_USE_PSRAM_IO
#define GLB_CFG_GPIO_USE_PSRAM_IO_POS  (0U)
#define GLB_CFG_GPIO_USE_PSRAM_IO_LEN  (6U)
#define GLB_CFG_GPIO_USE_PSRAM_IO_MSK  (((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS)
#define GLB_CFG_GPIO_USE_PSRAM_IO_UMSK (~(((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS))

/* 0x90 : CPU_CLK_CFG */
#define GLB_CPU_CLK_CFG_OFFSET      (0x90)
#define GLB_CPU_RTC_DIV             GLB_CPU_RTC_DIV
#define GLB_CPU_RTC_DIV_POS         (0U)
#define GLB_CPU_RTC_DIV_LEN         (17U)
#define GLB_CPU_RTC_DIV_MSK         (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
#define GLB_CPU_RTC_DIV_UMSK        (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
#define GLB_CPU_RTC_EN              GLB_CPU_RTC_EN
#define GLB_CPU_RTC_EN_POS          (18U)
#define GLB_CPU_RTC_EN_LEN          (1U)
#define GLB_CPU_RTC_EN_MSK          (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
#define GLB_CPU_RTC_EN_UMSK         (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
#define GLB_CPU_RTC_SEL             GLB_CPU_RTC_SEL
#define GLB_CPU_RTC_SEL_POS         (19U)
#define GLB_CPU_RTC_SEL_LEN         (1U)
#define GLB_CPU_RTC_SEL_MSK         (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
#define GLB_CPU_RTC_SEL_UMSK        (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
#define GLB_DEBUG_NDRESET_GATE      GLB_DEBUG_NDRESET_GATE
#define GLB_DEBUG_NDRESET_GATE_POS  (20U)
#define GLB_DEBUG_NDRESET_GATE_LEN  (1U)
#define GLB_DEBUG_NDRESET_GATE_MSK  (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))

/* 0xA4 : GPADC_32M_SRC_CTRL */
#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
#define GLB_GPADC_32M_CLK_DIV         GLB_GPADC_32M_CLK_DIV
#define GLB_GPADC_32M_CLK_DIV_POS     (0U)
#define GLB_GPADC_32M_CLK_DIV_LEN     (6U)
#define GLB_GPADC_32M_CLK_DIV_MSK     (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
#define GLB_GPADC_32M_CLK_DIV_UMSK    (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
#define GLB_GPADC_32M_CLK_SEL         GLB_GPADC_32M_CLK_SEL
#define GLB_GPADC_32M_CLK_SEL_POS     (7U)
#define GLB_GPADC_32M_CLK_SEL_LEN     (1U)
#define GLB_GPADC_32M_CLK_SEL_MSK     (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
#define GLB_GPADC_32M_CLK_SEL_UMSK    (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
#define GLB_GPADC_32M_DIV_EN          GLB_GPADC_32M_DIV_EN
#define GLB_GPADC_32M_DIV_EN_POS      (8U)
#define GLB_GPADC_32M_DIV_EN_LEN      (1U)
#define GLB_GPADC_32M_DIV_EN_MSK      (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
#define GLB_GPADC_32M_DIV_EN_UMSK     (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))

/* 0xA8 : DIG32K_WAKEUP_CTRL */
#define GLB_DIG32K_WAKEUP_CTRL_OFFSET   (0xA8)
#define GLB_DIG_32K_DIV                 GLB_DIG_32K_DIV
#define GLB_DIG_32K_DIV_POS             (0U)
#define GLB_DIG_32K_DIV_LEN             (11U)
#define GLB_DIG_32K_DIV_MSK             (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
#define GLB_DIG_32K_DIV_UMSK            (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
#define GLB_DIG_32K_EN                  GLB_DIG_32K_EN
#define GLB_DIG_32K_EN_POS              (12U)
#define GLB_DIG_32K_EN_LEN              (1U)
#define GLB_DIG_32K_EN_MSK              (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
#define GLB_DIG_32K_EN_UMSK             (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
#define GLB_DIG_32K_COMP                GLB_DIG_32K_COMP
#define GLB_DIG_32K_COMP_POS            (13U)
#define GLB_DIG_32K_COMP_LEN            (1U)
#define GLB_DIG_32K_COMP_MSK            (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
#define GLB_DIG_32K_COMP_UMSK           (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
#define GLB_DIG_512K_DIV                GLB_DIG_512K_DIV
#define GLB_DIG_512K_DIV_POS            (16U)
#define GLB_DIG_512K_DIV_LEN            (7U)
#define GLB_DIG_512K_DIV_MSK            (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
#define GLB_DIG_512K_DIV_UMSK           (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
#define GLB_DIG_512K_EN                 GLB_DIG_512K_EN
#define GLB_DIG_512K_EN_POS             (24U)
#define GLB_DIG_512K_EN_LEN             (1U)
#define GLB_DIG_512K_EN_MSK             (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
#define GLB_DIG_512K_EN_UMSK            (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
#define GLB_DIG_512K_COMP               GLB_DIG_512K_COMP
#define GLB_DIG_512K_COMP_POS           (25U)
#define GLB_DIG_512K_COMP_LEN           (1U)
#define GLB_DIG_512K_COMP_MSK           (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
#define GLB_DIG_512K_COMP_UMSK          (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
#define GLB_DIG_CLK_SRC_SEL             GLB_DIG_CLK_SRC_SEL
#define GLB_DIG_CLK_SRC_SEL_POS         (28U)
#define GLB_DIG_CLK_SRC_SEL_LEN         (2U)
#define GLB_DIG_CLK_SRC_SEL_MSK         (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
#define GLB_DIG_CLK_SRC_SEL_UMSK        (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
#define GLB_REG_EN_PLATFORM_WAKEUP      GLB_REG_EN_PLATFORM_WAKEUP
#define GLB_REG_EN_PLATFORM_WAKEUP_POS  (31U)
#define GLB_REG_EN_PLATFORM_WAKEUP_LEN  (1U)
#define GLB_REG_EN_PLATFORM_WAKEUP_MSK  (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))

/* 0xAC : WIFI_BT_COEX_CTRL */
#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
#define GLB_COEX_BT_CHANNEL          GLB_COEX_BT_CHANNEL
#define GLB_COEX_BT_CHANNEL_POS      (0U)
#define GLB_COEX_BT_CHANNEL_LEN      (7U)
#define GLB_COEX_BT_CHANNEL_MSK      (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
#define GLB_COEX_BT_CHANNEL_UMSK     (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
#define GLB_COEX_BT_PTI              GLB_COEX_BT_PTI
#define GLB_COEX_BT_PTI_POS          (7U)
#define GLB_COEX_BT_PTI_LEN          (4U)
#define GLB_COEX_BT_PTI_MSK          (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
#define GLB_COEX_BT_PTI_UMSK         (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
#define GLB_COEX_BT_BW               GLB_COEX_BT_BW
#define GLB_COEX_BT_BW_POS           (11U)
#define GLB_COEX_BT_BW_LEN           (1U)
#define GLB_COEX_BT_BW_MSK           (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
#define GLB_COEX_BT_BW_UMSK          (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
#define GLB_EN_GPIO_BT_COEX          GLB_EN_GPIO_BT_COEX
#define GLB_EN_GPIO_BT_COEX_POS      (12U)
#define GLB_EN_GPIO_BT_COEX_LEN      (1U)
#define GLB_EN_GPIO_BT_COEX_MSK      (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
#define GLB_EN_GPIO_BT_COEX_UMSK     (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))

/* 0xB0 : BZ_COEX_CTRL */
#define GLB_BZ_COEX_CTRL_OFFSET    (0xB0)
#define GLB_COEX_EN                GLB_COEX_EN
#define GLB_COEX_EN_POS            (0U)
#define GLB_COEX_EN_LEN            (1U)
#define GLB_COEX_EN_MSK            (((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS)
#define GLB_COEX_EN_UMSK           (~(((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS))
#define GLB_WLAN_EN                GLB_WLAN_EN
#define GLB_WLAN_EN_POS            (1U)
#define GLB_WLAN_EN_LEN            (1U)
#define GLB_WLAN_EN_MSK            (((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS)
#define GLB_WLAN_EN_UMSK           (~(((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS))
#define GLB_BLE_RX_IGNORE          GLB_BLE_RX_IGNORE
#define GLB_BLE_RX_IGNORE_POS      (2U)
#define GLB_BLE_RX_IGNORE_LEN      (1U)
#define GLB_BLE_RX_IGNORE_MSK      (((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS)
#define GLB_BLE_RX_IGNORE_UMSK     (~(((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS))
#define GLB_M154_RX_IGNORE         GLB_M154_RX_IGNORE
#define GLB_M154_RX_IGNORE_POS     (3U)
#define GLB_M154_RX_IGNORE_LEN     (1U)
#define GLB_M154_RX_IGNORE_MSK     (((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS)
#define GLB_M154_RX_IGNORE_UMSK    (~(((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS))
#define GLB_BZ_PRI_THR             GLB_BZ_PRI_THR
#define GLB_BZ_PRI_THR_POS         (4U)
#define GLB_BZ_PRI_THR_LEN         (4U)
#define GLB_BZ_PRI_THR_MSK         (((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS)
#define GLB_BZ_PRI_THR_UMSK        (~(((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS))
#define GLB_BZ_PRI_EN              GLB_BZ_PRI_EN
#define GLB_BZ_PRI_EN_POS          (8U)
#define GLB_BZ_PRI_EN_LEN          (1U)
#define GLB_BZ_PRI_EN_MSK          (((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS)
#define GLB_BZ_PRI_EN_UMSK         (~(((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS))
#define GLB_BZ_PRI_POL             GLB_BZ_PRI_POL
#define GLB_BZ_PRI_POL_POS         (9U)
#define GLB_BZ_PRI_POL_LEN         (1U)
#define GLB_BZ_PRI_POL_MSK         (((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS)
#define GLB_BZ_PRI_POL_UMSK        (~(((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS))
#define GLB_BZ_ACTIVE_POL          GLB_BZ_ACTIVE_POL
#define GLB_BZ_ACTIVE_POL_POS      (10U)
#define GLB_BZ_ACTIVE_POL_LEN      (1U)
#define GLB_BZ_ACTIVE_POL_MSK      (((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS)
#define GLB_BZ_ACTIVE_POL_UMSK     (~(((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS))
#define GLB_BZ_ABORT_POL           GLB_BZ_ABORT_POL
#define GLB_BZ_ABORT_POL_POS       (11U)
#define GLB_BZ_ABORT_POL_LEN       (1U)
#define GLB_BZ_ABORT_POL_MSK       (((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS)
#define GLB_BZ_ABORT_POL_UMSK      (~(((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS))
#define GLB_COEX_PRI               GLB_COEX_PRI
#define GLB_COEX_PRI_POS           (12U)
#define GLB_COEX_PRI_LEN           (1U)
#define GLB_COEX_PRI_MSK           (((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS)
#define GLB_COEX_PRI_UMSK          (~(((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS))
#define GLB_FORCE_M154_WIN         GLB_FORCE_M154_WIN
#define GLB_FORCE_M154_WIN_POS     (13U)
#define GLB_FORCE_M154_WIN_LEN     (1U)
#define GLB_FORCE_M154_WIN_MSK     (((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS)
#define GLB_FORCE_M154_WIN_UMSK    (~(((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS))
#define GLB_FORCE_BLE_WIN          GLB_FORCE_BLE_WIN
#define GLB_FORCE_BLE_WIN_POS      (14U)
#define GLB_FORCE_BLE_WIN_LEN      (1U)
#define GLB_FORCE_BLE_WIN_MSK      (((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS)
#define GLB_FORCE_BLE_WIN_UMSK     (~(((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS))
#define GLB_COEX_OPTION            GLB_COEX_OPTION
#define GLB_COEX_OPTION_POS        (15U)
#define GLB_COEX_OPTION_LEN        (1U)
#define GLB_COEX_OPTION_MSK        (((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS)
#define GLB_COEX_OPTION_UMSK       (~(((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS))
#define GLB_COEX_FORCE_CH          GLB_COEX_FORCE_CH
#define GLB_COEX_FORCE_CH_POS      (16U)
#define GLB_COEX_FORCE_CH_LEN      (7U)
#define GLB_COEX_FORCE_CH_MSK      (((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS)
#define GLB_COEX_FORCE_CH_UMSK     (~(((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS))
#define GLB_M154_RX_ABORT_DIS      GLB_M154_RX_ABORT_DIS
#define GLB_M154_RX_ABORT_DIS_POS  (24U)
#define GLB_M154_RX_ABORT_DIS_LEN  (1U)
#define GLB_M154_RX_ABORT_DIS_MSK  (((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS)
#define GLB_M154_RX_ABORT_DIS_UMSK (~(((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS))
#define GLB_M154_TX_ABORT_DIS      GLB_M154_TX_ABORT_DIS
#define GLB_M154_TX_ABORT_DIS_POS  (25U)
#define GLB_M154_TX_ABORT_DIS_LEN  (1U)
#define GLB_M154_TX_ABORT_DIS_MSK  (((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS)
#define GLB_M154_TX_ABORT_DIS_UMSK (~(((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS))
#define GLB_BLE_RX_ABORT_DIS       GLB_BLE_RX_ABORT_DIS
#define GLB_BLE_RX_ABORT_DIS_POS   (26U)
#define GLB_BLE_RX_ABORT_DIS_LEN   (1U)
#define GLB_BLE_RX_ABORT_DIS_MSK   (((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS)
#define GLB_BLE_RX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS))
#define GLB_BLE_TX_ABORT_DIS       GLB_BLE_TX_ABORT_DIS
#define GLB_BLE_TX_ABORT_DIS_POS   (27U)
#define GLB_BLE_TX_ABORT_DIS_LEN   (1U)
#define GLB_BLE_TX_ABORT_DIS_MSK   (((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS)
#define GLB_BLE_TX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS))
#define GLB_COEX_ARB               GLB_COEX_ARB
#define GLB_COEX_ARB_POS           (28U)
#define GLB_COEX_ARB_LEN           (4U)
#define GLB_COEX_ARB_MSK           (((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS)
#define GLB_COEX_ARB_UMSK          (~(((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS))

/* 0xC0 : UART_SIG_SEL_0 */
#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
#define GLB_UART_SIG_0_SEL        GLB_UART_SIG_0_SEL
#define GLB_UART_SIG_0_SEL_POS    (0U)
#define GLB_UART_SIG_0_SEL_LEN    (4U)
#define GLB_UART_SIG_0_SEL_MSK    (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
#define GLB_UART_SIG_0_SEL_UMSK   (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
#define GLB_UART_SIG_1_SEL        GLB_UART_SIG_1_SEL
#define GLB_UART_SIG_1_SEL_POS    (4U)
#define GLB_UART_SIG_1_SEL_LEN    (4U)
#define GLB_UART_SIG_1_SEL_MSK    (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
#define GLB_UART_SIG_1_SEL_UMSK   (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
#define GLB_UART_SIG_2_SEL        GLB_UART_SIG_2_SEL
#define GLB_UART_SIG_2_SEL_POS    (8U)
#define GLB_UART_SIG_2_SEL_LEN    (4U)
#define GLB_UART_SIG_2_SEL_MSK    (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
#define GLB_UART_SIG_2_SEL_UMSK   (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
#define GLB_UART_SIG_3_SEL        GLB_UART_SIG_3_SEL
#define GLB_UART_SIG_3_SEL_POS    (12U)
#define GLB_UART_SIG_3_SEL_LEN    (4U)
#define GLB_UART_SIG_3_SEL_MSK    (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
#define GLB_UART_SIG_3_SEL_UMSK   (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
#define GLB_UART_SIG_4_SEL        GLB_UART_SIG_4_SEL
#define GLB_UART_SIG_4_SEL_POS    (16U)
#define GLB_UART_SIG_4_SEL_LEN    (4U)
#define GLB_UART_SIG_4_SEL_MSK    (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
#define GLB_UART_SIG_4_SEL_UMSK   (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
#define GLB_UART_SIG_5_SEL        GLB_UART_SIG_5_SEL
#define GLB_UART_SIG_5_SEL_POS    (20U)
#define GLB_UART_SIG_5_SEL_LEN    (4U)
#define GLB_UART_SIG_5_SEL_MSK    (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
#define GLB_UART_SIG_5_SEL_UMSK   (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
#define GLB_UART_SIG_6_SEL        GLB_UART_SIG_6_SEL
#define GLB_UART_SIG_6_SEL_POS    (24U)
#define GLB_UART_SIG_6_SEL_LEN    (4U)
#define GLB_UART_SIG_6_SEL_MSK    (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
#define GLB_UART_SIG_6_SEL_UMSK   (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
#define GLB_UART_SIG_7_SEL        GLB_UART_SIG_7_SEL
#define GLB_UART_SIG_7_SEL_POS    (28U)
#define GLB_UART_SIG_7_SEL_LEN    (4U)
#define GLB_UART_SIG_7_SEL_MSK    (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
#define GLB_UART_SIG_7_SEL_UMSK   (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))

/* 0xD0 : DBG_SEL_LL */
#define GLB_DBG_SEL_LL_OFFSET    (0xD0)
#define GLB_REG_DBG_LL_CTRL      GLB_REG_DBG_LL_CTRL
#define GLB_REG_DBG_LL_CTRL_POS  (0U)
#define GLB_REG_DBG_LL_CTRL_LEN  (32U)
#define GLB_REG_DBG_LL_CTRL_MSK  (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))

/* 0xD4 : DBG_SEL_LH */
#define GLB_DBG_SEL_LH_OFFSET    (0xD4)
#define GLB_REG_DBG_LH_CTRL      GLB_REG_DBG_LH_CTRL
#define GLB_REG_DBG_LH_CTRL_POS  (0U)
#define GLB_REG_DBG_LH_CTRL_LEN  (32U)
#define GLB_REG_DBG_LH_CTRL_MSK  (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))

/* 0xD8 : DBG_SEL_HL */
#define GLB_DBG_SEL_HL_OFFSET    (0xD8)
#define GLB_REG_DBG_HL_CTRL      GLB_REG_DBG_HL_CTRL
#define GLB_REG_DBG_HL_CTRL_POS  (0U)
#define GLB_REG_DBG_HL_CTRL_LEN  (32U)
#define GLB_REG_DBG_HL_CTRL_MSK  (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))

/* 0xDC : DBG_SEL_HH */
#define GLB_DBG_SEL_HH_OFFSET    (0xDC)
#define GLB_REG_DBG_HH_CTRL      GLB_REG_DBG_HH_CTRL
#define GLB_REG_DBG_HH_CTRL_POS  (0U)
#define GLB_REG_DBG_HH_CTRL_LEN  (32U)
#define GLB_REG_DBG_HH_CTRL_MSK  (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))

/* 0xE0 : debug */
#define GLB_DEBUG_OFFSET  (0xE0)
#define GLB_DEBUG_OE      GLB_DEBUG_OE
#define GLB_DEBUG_OE_POS  (0U)
#define GLB_DEBUG_OE_LEN  (1U)
#define GLB_DEBUG_OE_MSK  (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
#define GLB_DEBUG_I       GLB_DEBUG_I
#define GLB_DEBUG_I_POS   (1U)
#define GLB_DEBUG_I_LEN   (31U)
#define GLB_DEBUG_I_MSK   (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
#define GLB_DEBUG_I_UMSK  (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))

/* 0x100 : GPIO_CFGCTL0 */
#define GLB_GPIO_CFGCTL0_OFFSET      (0x100)
#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
#define GLB_REG_GPIO_0_IE_POS        (0U)
#define GLB_REG_GPIO_0_IE_LEN        (1U)
#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
#define GLB_REG_GPIO_0_SMT_POS       (1U)
#define GLB_REG_GPIO_0_SMT_LEN       (1U)
#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
#define GLB_REG_GPIO_0_DRV_POS       (2U)
#define GLB_REG_GPIO_0_DRV_LEN       (2U)
#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
#define GLB_REG_GPIO_0_PU_POS        (4U)
#define GLB_REG_GPIO_0_PU_LEN        (1U)
#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
#define GLB_REG_GPIO_0_PD_POS        (5U)
#define GLB_REG_GPIO_0_PD_LEN        (1U)
#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
#define GLB_REG_GPIO_1_IE_POS        (16U)
#define GLB_REG_GPIO_1_IE_LEN        (1U)
#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
#define GLB_REG_GPIO_1_SMT_POS       (17U)
#define GLB_REG_GPIO_1_SMT_LEN       (1U)
#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
#define GLB_REG_GPIO_1_DRV_POS       (18U)
#define GLB_REG_GPIO_1_DRV_LEN       (2U)
#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
#define GLB_REG_GPIO_1_PU_POS        (20U)
#define GLB_REG_GPIO_1_PU_LEN        (1U)
#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
#define GLB_REG_GPIO_1_PD_POS        (21U)
#define GLB_REG_GPIO_1_PD_LEN        (1U)
#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))

/* 0x104 : GPIO_CFGCTL1 */
#define GLB_GPIO_CFGCTL1_OFFSET      (0x104)
#define GLB_REG_GPIO_2_IE            GLB_REG_GPIO_2_IE
#define GLB_REG_GPIO_2_IE_POS        (0U)
#define GLB_REG_GPIO_2_IE_LEN        (1U)
#define GLB_REG_GPIO_2_IE_MSK        (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
#define GLB_REG_GPIO_2_IE_UMSK       (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
#define GLB_REG_GPIO_2_SMT           GLB_REG_GPIO_2_SMT
#define GLB_REG_GPIO_2_SMT_POS       (1U)
#define GLB_REG_GPIO_2_SMT_LEN       (1U)
#define GLB_REG_GPIO_2_SMT_MSK       (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
#define GLB_REG_GPIO_2_SMT_UMSK      (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
#define GLB_REG_GPIO_2_DRV           GLB_REG_GPIO_2_DRV
#define GLB_REG_GPIO_2_DRV_POS       (2U)
#define GLB_REG_GPIO_2_DRV_LEN       (2U)
#define GLB_REG_GPIO_2_DRV_MSK       (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
#define GLB_REG_GPIO_2_DRV_UMSK      (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
#define GLB_REG_GPIO_2_PU            GLB_REG_GPIO_2_PU
#define GLB_REG_GPIO_2_PU_POS        (4U)
#define GLB_REG_GPIO_2_PU_LEN        (1U)
#define GLB_REG_GPIO_2_PU_MSK        (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
#define GLB_REG_GPIO_2_PU_UMSK       (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
#define GLB_REG_GPIO_2_PD            GLB_REG_GPIO_2_PD
#define GLB_REG_GPIO_2_PD_POS        (5U)
#define GLB_REG_GPIO_2_PD_LEN        (1U)
#define GLB_REG_GPIO_2_PD_MSK        (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
#define GLB_REG_GPIO_2_PD_UMSK       (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
#define GLB_REG_GPIO_2_FUNC_SEL      GLB_REG_GPIO_2_FUNC_SEL
#define GLB_REG_GPIO_2_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_2_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_2_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
#define GLB_REG_GPIO_3_IE            GLB_REG_GPIO_3_IE
#define GLB_REG_GPIO_3_IE_POS        (16U)
#define GLB_REG_GPIO_3_IE_LEN        (1U)
#define GLB_REG_GPIO_3_IE_MSK        (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
#define GLB_REG_GPIO_3_IE_UMSK       (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
#define GLB_REG_GPIO_3_SMT           GLB_REG_GPIO_3_SMT
#define GLB_REG_GPIO_3_SMT_POS       (17U)
#define GLB_REG_GPIO_3_SMT_LEN       (1U)
#define GLB_REG_GPIO_3_SMT_MSK       (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
#define GLB_REG_GPIO_3_SMT_UMSK      (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
#define GLB_REG_GPIO_3_DRV           GLB_REG_GPIO_3_DRV
#define GLB_REG_GPIO_3_DRV_POS       (18U)
#define GLB_REG_GPIO_3_DRV_LEN       (2U)
#define GLB_REG_GPIO_3_DRV_MSK       (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
#define GLB_REG_GPIO_3_DRV_UMSK      (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
#define GLB_REG_GPIO_3_PU            GLB_REG_GPIO_3_PU
#define GLB_REG_GPIO_3_PU_POS        (20U)
#define GLB_REG_GPIO_3_PU_LEN        (1U)
#define GLB_REG_GPIO_3_PU_MSK        (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
#define GLB_REG_GPIO_3_PU_UMSK       (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
#define GLB_REG_GPIO_3_PD            GLB_REG_GPIO_3_PD
#define GLB_REG_GPIO_3_PD_POS        (21U)
#define GLB_REG_GPIO_3_PD_LEN        (1U)
#define GLB_REG_GPIO_3_PD_MSK        (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
#define GLB_REG_GPIO_3_PD_UMSK       (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
#define GLB_REG_GPIO_3_FUNC_SEL      GLB_REG_GPIO_3_FUNC_SEL
#define GLB_REG_GPIO_3_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_3_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_3_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))

/* 0x108 : GPIO_CFGCTL2 */
#define GLB_GPIO_CFGCTL2_OFFSET      (0x108)
#define GLB_REG_GPIO_4_IE            GLB_REG_GPIO_4_IE
#define GLB_REG_GPIO_4_IE_POS        (0U)
#define GLB_REG_GPIO_4_IE_LEN        (1U)
#define GLB_REG_GPIO_4_IE_MSK        (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
#define GLB_REG_GPIO_4_IE_UMSK       (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
#define GLB_REG_GPIO_4_SMT           GLB_REG_GPIO_4_SMT
#define GLB_REG_GPIO_4_SMT_POS       (1U)
#define GLB_REG_GPIO_4_SMT_LEN       (1U)
#define GLB_REG_GPIO_4_SMT_MSK       (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
#define GLB_REG_GPIO_4_SMT_UMSK      (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
#define GLB_REG_GPIO_4_DRV           GLB_REG_GPIO_4_DRV
#define GLB_REG_GPIO_4_DRV_POS       (2U)
#define GLB_REG_GPIO_4_DRV_LEN       (2U)
#define GLB_REG_GPIO_4_DRV_MSK       (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
#define GLB_REG_GPIO_4_DRV_UMSK      (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
#define GLB_REG_GPIO_4_PU            GLB_REG_GPIO_4_PU
#define GLB_REG_GPIO_4_PU_POS        (4U)
#define GLB_REG_GPIO_4_PU_LEN        (1U)
#define GLB_REG_GPIO_4_PU_MSK        (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
#define GLB_REG_GPIO_4_PU_UMSK       (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
#define GLB_REG_GPIO_4_PD            GLB_REG_GPIO_4_PD
#define GLB_REG_GPIO_4_PD_POS        (5U)
#define GLB_REG_GPIO_4_PD_LEN        (1U)
#define GLB_REG_GPIO_4_PD_MSK        (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
#define GLB_REG_GPIO_4_PD_UMSK       (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
#define GLB_REG_GPIO_4_FUNC_SEL      GLB_REG_GPIO_4_FUNC_SEL
#define GLB_REG_GPIO_4_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_4_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_4_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
#define GLB_REG_GPIO_5_IE            GLB_REG_GPIO_5_IE
#define GLB_REG_GPIO_5_IE_POS        (16U)
#define GLB_REG_GPIO_5_IE_LEN        (1U)
#define GLB_REG_GPIO_5_IE_MSK        (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
#define GLB_REG_GPIO_5_IE_UMSK       (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
#define GLB_REG_GPIO_5_SMT           GLB_REG_GPIO_5_SMT
#define GLB_REG_GPIO_5_SMT_POS       (17U)
#define GLB_REG_GPIO_5_SMT_LEN       (1U)
#define GLB_REG_GPIO_5_SMT_MSK       (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
#define GLB_REG_GPIO_5_SMT_UMSK      (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
#define GLB_REG_GPIO_5_DRV           GLB_REG_GPIO_5_DRV
#define GLB_REG_GPIO_5_DRV_POS       (18U)
#define GLB_REG_GPIO_5_DRV_LEN       (2U)
#define GLB_REG_GPIO_5_DRV_MSK       (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
#define GLB_REG_GPIO_5_DRV_UMSK      (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
#define GLB_REG_GPIO_5_PU            GLB_REG_GPIO_5_PU
#define GLB_REG_GPIO_5_PU_POS        (20U)
#define GLB_REG_GPIO_5_PU_LEN        (1U)
#define GLB_REG_GPIO_5_PU_MSK        (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
#define GLB_REG_GPIO_5_PU_UMSK       (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
#define GLB_REG_GPIO_5_PD            GLB_REG_GPIO_5_PD
#define GLB_REG_GPIO_5_PD_POS        (21U)
#define GLB_REG_GPIO_5_PD_LEN        (1U)
#define GLB_REG_GPIO_5_PD_MSK        (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
#define GLB_REG_GPIO_5_PD_UMSK       (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
#define GLB_REG_GPIO_5_FUNC_SEL      GLB_REG_GPIO_5_FUNC_SEL
#define GLB_REG_GPIO_5_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_5_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_5_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))

/* 0x10C : GPIO_CFGCTL3 */
#define GLB_GPIO_CFGCTL3_OFFSET      (0x10C)
#define GLB_REG_GPIO_6_IE            GLB_REG_GPIO_6_IE
#define GLB_REG_GPIO_6_IE_POS        (0U)
#define GLB_REG_GPIO_6_IE_LEN        (1U)
#define GLB_REG_GPIO_6_IE_MSK        (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
#define GLB_REG_GPIO_6_IE_UMSK       (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
#define GLB_REG_GPIO_6_SMT           GLB_REG_GPIO_6_SMT
#define GLB_REG_GPIO_6_SMT_POS       (1U)
#define GLB_REG_GPIO_6_SMT_LEN       (1U)
#define GLB_REG_GPIO_6_SMT_MSK       (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
#define GLB_REG_GPIO_6_SMT_UMSK      (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
#define GLB_REG_GPIO_6_DRV           GLB_REG_GPIO_6_DRV
#define GLB_REG_GPIO_6_DRV_POS       (2U)
#define GLB_REG_GPIO_6_DRV_LEN       (2U)
#define GLB_REG_GPIO_6_DRV_MSK       (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
#define GLB_REG_GPIO_6_DRV_UMSK      (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
#define GLB_REG_GPIO_6_PU            GLB_REG_GPIO_6_PU
#define GLB_REG_GPIO_6_PU_POS        (4U)
#define GLB_REG_GPIO_6_PU_LEN        (1U)
#define GLB_REG_GPIO_6_PU_MSK        (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
#define GLB_REG_GPIO_6_PU_UMSK       (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
#define GLB_REG_GPIO_6_PD            GLB_REG_GPIO_6_PD
#define GLB_REG_GPIO_6_PD_POS        (5U)
#define GLB_REG_GPIO_6_PD_LEN        (1U)
#define GLB_REG_GPIO_6_PD_MSK        (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
#define GLB_REG_GPIO_6_PD_UMSK       (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
#define GLB_REG_GPIO_6_FUNC_SEL      GLB_REG_GPIO_6_FUNC_SEL
#define GLB_REG_GPIO_6_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_6_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_6_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
#define GLB_REG_GPIO_7_IE            GLB_REG_GPIO_7_IE
#define GLB_REG_GPIO_7_IE_POS        (16U)
#define GLB_REG_GPIO_7_IE_LEN        (1U)
#define GLB_REG_GPIO_7_IE_MSK        (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
#define GLB_REG_GPIO_7_IE_UMSK       (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
#define GLB_REG_GPIO_7_SMT           GLB_REG_GPIO_7_SMT
#define GLB_REG_GPIO_7_SMT_POS       (17U)
#define GLB_REG_GPIO_7_SMT_LEN       (1U)
#define GLB_REG_GPIO_7_SMT_MSK       (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
#define GLB_REG_GPIO_7_SMT_UMSK      (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
#define GLB_REG_GPIO_7_DRV           GLB_REG_GPIO_7_DRV
#define GLB_REG_GPIO_7_DRV_POS       (18U)
#define GLB_REG_GPIO_7_DRV_LEN       (2U)
#define GLB_REG_GPIO_7_DRV_MSK       (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
#define GLB_REG_GPIO_7_DRV_UMSK      (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
#define GLB_REG_GPIO_7_PU            GLB_REG_GPIO_7_PU
#define GLB_REG_GPIO_7_PU_POS        (20U)
#define GLB_REG_GPIO_7_PU_LEN        (1U)
#define GLB_REG_GPIO_7_PU_MSK        (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
#define GLB_REG_GPIO_7_PU_UMSK       (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
#define GLB_REG_GPIO_7_PD            GLB_REG_GPIO_7_PD
#define GLB_REG_GPIO_7_PD_POS        (21U)
#define GLB_REG_GPIO_7_PD_LEN        (1U)
#define GLB_REG_GPIO_7_PD_MSK        (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
#define GLB_REG_GPIO_7_PD_UMSK       (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
#define GLB_REG_GPIO_7_FUNC_SEL      GLB_REG_GPIO_7_FUNC_SEL
#define GLB_REG_GPIO_7_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_7_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_7_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))

/* 0x110 : GPIO_CFGCTL4 */
#define GLB_GPIO_CFGCTL4_OFFSET      (0x110)
#define GLB_REG_GPIO_8_IE            GLB_REG_GPIO_8_IE
#define GLB_REG_GPIO_8_IE_POS        (0U)
#define GLB_REG_GPIO_8_IE_LEN        (1U)
#define GLB_REG_GPIO_8_IE_MSK        (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
#define GLB_REG_GPIO_8_IE_UMSK       (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
#define GLB_REG_GPIO_8_SMT           GLB_REG_GPIO_8_SMT
#define GLB_REG_GPIO_8_SMT_POS       (1U)
#define GLB_REG_GPIO_8_SMT_LEN       (1U)
#define GLB_REG_GPIO_8_SMT_MSK       (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
#define GLB_REG_GPIO_8_SMT_UMSK      (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
#define GLB_REG_GPIO_8_DRV           GLB_REG_GPIO_8_DRV
#define GLB_REG_GPIO_8_DRV_POS       (2U)
#define GLB_REG_GPIO_8_DRV_LEN       (2U)
#define GLB_REG_GPIO_8_DRV_MSK       (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
#define GLB_REG_GPIO_8_DRV_UMSK      (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
#define GLB_REG_GPIO_8_PU            GLB_REG_GPIO_8_PU
#define GLB_REG_GPIO_8_PU_POS        (4U)
#define GLB_REG_GPIO_8_PU_LEN        (1U)
#define GLB_REG_GPIO_8_PU_MSK        (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
#define GLB_REG_GPIO_8_PU_UMSK       (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
#define GLB_REG_GPIO_8_PD            GLB_REG_GPIO_8_PD
#define GLB_REG_GPIO_8_PD_POS        (5U)
#define GLB_REG_GPIO_8_PD_LEN        (1U)
#define GLB_REG_GPIO_8_PD_MSK        (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
#define GLB_REG_GPIO_8_PD_UMSK       (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
#define GLB_REG_GPIO_8_FUNC_SEL      GLB_REG_GPIO_8_FUNC_SEL
#define GLB_REG_GPIO_8_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_8_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_8_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
#define GLB_REG_GPIO_9_IE            GLB_REG_GPIO_9_IE
#define GLB_REG_GPIO_9_IE_POS        (16U)
#define GLB_REG_GPIO_9_IE_LEN        (1U)
#define GLB_REG_GPIO_9_IE_MSK        (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
#define GLB_REG_GPIO_9_IE_UMSK       (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
#define GLB_REG_GPIO_9_SMT           GLB_REG_GPIO_9_SMT
#define GLB_REG_GPIO_9_SMT_POS       (17U)
#define GLB_REG_GPIO_9_SMT_LEN       (1U)
#define GLB_REG_GPIO_9_SMT_MSK       (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
#define GLB_REG_GPIO_9_SMT_UMSK      (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
#define GLB_REG_GPIO_9_DRV           GLB_REG_GPIO_9_DRV
#define GLB_REG_GPIO_9_DRV_POS       (18U)
#define GLB_REG_GPIO_9_DRV_LEN       (2U)
#define GLB_REG_GPIO_9_DRV_MSK       (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
#define GLB_REG_GPIO_9_DRV_UMSK      (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
#define GLB_REG_GPIO_9_PU            GLB_REG_GPIO_9_PU
#define GLB_REG_GPIO_9_PU_POS        (20U)
#define GLB_REG_GPIO_9_PU_LEN        (1U)
#define GLB_REG_GPIO_9_PU_MSK        (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
#define GLB_REG_GPIO_9_PU_UMSK       (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
#define GLB_REG_GPIO_9_PD            GLB_REG_GPIO_9_PD
#define GLB_REG_GPIO_9_PD_POS        (21U)
#define GLB_REG_GPIO_9_PD_LEN        (1U)
#define GLB_REG_GPIO_9_PD_MSK        (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
#define GLB_REG_GPIO_9_PD_UMSK       (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
#define GLB_REG_GPIO_9_FUNC_SEL      GLB_REG_GPIO_9_FUNC_SEL
#define GLB_REG_GPIO_9_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_9_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_9_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))

/* 0x114 : GPIO_CFGCTL5 */
#define GLB_GPIO_CFGCTL5_OFFSET       (0x114)
#define GLB_REG_GPIO_10_IE            GLB_REG_GPIO_10_IE
#define GLB_REG_GPIO_10_IE_POS        (0U)
#define GLB_REG_GPIO_10_IE_LEN        (1U)
#define GLB_REG_GPIO_10_IE_MSK        (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
#define GLB_REG_GPIO_10_IE_UMSK       (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
#define GLB_REG_GPIO_10_SMT           GLB_REG_GPIO_10_SMT
#define GLB_REG_GPIO_10_SMT_POS       (1U)
#define GLB_REG_GPIO_10_SMT_LEN       (1U)
#define GLB_REG_GPIO_10_SMT_MSK       (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
#define GLB_REG_GPIO_10_SMT_UMSK      (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
#define GLB_REG_GPIO_10_DRV           GLB_REG_GPIO_10_DRV
#define GLB_REG_GPIO_10_DRV_POS       (2U)
#define GLB_REG_GPIO_10_DRV_LEN       (2U)
#define GLB_REG_GPIO_10_DRV_MSK       (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
#define GLB_REG_GPIO_10_DRV_UMSK      (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
#define GLB_REG_GPIO_10_PU            GLB_REG_GPIO_10_PU
#define GLB_REG_GPIO_10_PU_POS        (4U)
#define GLB_REG_GPIO_10_PU_LEN        (1U)
#define GLB_REG_GPIO_10_PU_MSK        (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
#define GLB_REG_GPIO_10_PU_UMSK       (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
#define GLB_REG_GPIO_10_PD            GLB_REG_GPIO_10_PD
#define GLB_REG_GPIO_10_PD_POS        (5U)
#define GLB_REG_GPIO_10_PD_LEN        (1U)
#define GLB_REG_GPIO_10_PD_MSK        (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
#define GLB_REG_GPIO_10_PD_UMSK       (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
#define GLB_REG_GPIO_10_FUNC_SEL      GLB_REG_GPIO_10_FUNC_SEL
#define GLB_REG_GPIO_10_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_10_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_10_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
#define GLB_REG_GPIO_11_IE            GLB_REG_GPIO_11_IE
#define GLB_REG_GPIO_11_IE_POS        (16U)
#define GLB_REG_GPIO_11_IE_LEN        (1U)
#define GLB_REG_GPIO_11_IE_MSK        (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
#define GLB_REG_GPIO_11_IE_UMSK       (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
#define GLB_REG_GPIO_11_SMT           GLB_REG_GPIO_11_SMT
#define GLB_REG_GPIO_11_SMT_POS       (17U)
#define GLB_REG_GPIO_11_SMT_LEN       (1U)
#define GLB_REG_GPIO_11_SMT_MSK       (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
#define GLB_REG_GPIO_11_SMT_UMSK      (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
#define GLB_REG_GPIO_11_DRV           GLB_REG_GPIO_11_DRV
#define GLB_REG_GPIO_11_DRV_POS       (18U)
#define GLB_REG_GPIO_11_DRV_LEN       (2U)
#define GLB_REG_GPIO_11_DRV_MSK       (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
#define GLB_REG_GPIO_11_DRV_UMSK      (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
#define GLB_REG_GPIO_11_PU            GLB_REG_GPIO_11_PU
#define GLB_REG_GPIO_11_PU_POS        (20U)
#define GLB_REG_GPIO_11_PU_LEN        (1U)
#define GLB_REG_GPIO_11_PU_MSK        (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
#define GLB_REG_GPIO_11_PU_UMSK       (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
#define GLB_REG_GPIO_11_PD            GLB_REG_GPIO_11_PD
#define GLB_REG_GPIO_11_PD_POS        (21U)
#define GLB_REG_GPIO_11_PD_LEN        (1U)
#define GLB_REG_GPIO_11_PD_MSK        (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
#define GLB_REG_GPIO_11_PD_UMSK       (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
#define GLB_REG_GPIO_11_FUNC_SEL      GLB_REG_GPIO_11_FUNC_SEL
#define GLB_REG_GPIO_11_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_11_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_11_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))

/* 0x118 : GPIO_CFGCTL6 */
#define GLB_GPIO_CFGCTL6_OFFSET       (0x118)
#define GLB_REG_GPIO_12_IE            GLB_REG_GPIO_12_IE
#define GLB_REG_GPIO_12_IE_POS        (0U)
#define GLB_REG_GPIO_12_IE_LEN        (1U)
#define GLB_REG_GPIO_12_IE_MSK        (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
#define GLB_REG_GPIO_12_IE_UMSK       (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
#define GLB_REG_GPIO_12_SMT           GLB_REG_GPIO_12_SMT
#define GLB_REG_GPIO_12_SMT_POS       (1U)
#define GLB_REG_GPIO_12_SMT_LEN       (1U)
#define GLB_REG_GPIO_12_SMT_MSK       (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
#define GLB_REG_GPIO_12_SMT_UMSK      (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
#define GLB_REG_GPIO_12_DRV           GLB_REG_GPIO_12_DRV
#define GLB_REG_GPIO_12_DRV_POS       (2U)
#define GLB_REG_GPIO_12_DRV_LEN       (2U)
#define GLB_REG_GPIO_12_DRV_MSK       (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
#define GLB_REG_GPIO_12_DRV_UMSK      (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
#define GLB_REG_GPIO_12_PU            GLB_REG_GPIO_12_PU
#define GLB_REG_GPIO_12_PU_POS        (4U)
#define GLB_REG_GPIO_12_PU_LEN        (1U)
#define GLB_REG_GPIO_12_PU_MSK        (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
#define GLB_REG_GPIO_12_PU_UMSK       (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
#define GLB_REG_GPIO_12_PD            GLB_REG_GPIO_12_PD
#define GLB_REG_GPIO_12_PD_POS        (5U)
#define GLB_REG_GPIO_12_PD_LEN        (1U)
#define GLB_REG_GPIO_12_PD_MSK        (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
#define GLB_REG_GPIO_12_PD_UMSK       (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
#define GLB_REG_GPIO_12_FUNC_SEL      GLB_REG_GPIO_12_FUNC_SEL
#define GLB_REG_GPIO_12_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_12_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_12_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
#define GLB_REG_GPIO_13_IE            GLB_REG_GPIO_13_IE
#define GLB_REG_GPIO_13_IE_POS        (16U)
#define GLB_REG_GPIO_13_IE_LEN        (1U)
#define GLB_REG_GPIO_13_IE_MSK        (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
#define GLB_REG_GPIO_13_IE_UMSK       (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
#define GLB_REG_GPIO_13_SMT           GLB_REG_GPIO_13_SMT
#define GLB_REG_GPIO_13_SMT_POS       (17U)
#define GLB_REG_GPIO_13_SMT_LEN       (1U)
#define GLB_REG_GPIO_13_SMT_MSK       (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
#define GLB_REG_GPIO_13_SMT_UMSK      (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
#define GLB_REG_GPIO_13_DRV           GLB_REG_GPIO_13_DRV
#define GLB_REG_GPIO_13_DRV_POS       (18U)
#define GLB_REG_GPIO_13_DRV_LEN       (2U)
#define GLB_REG_GPIO_13_DRV_MSK       (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
#define GLB_REG_GPIO_13_DRV_UMSK      (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
#define GLB_REG_GPIO_13_PU            GLB_REG_GPIO_13_PU
#define GLB_REG_GPIO_13_PU_POS        (20U)
#define GLB_REG_GPIO_13_PU_LEN        (1U)
#define GLB_REG_GPIO_13_PU_MSK        (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
#define GLB_REG_GPIO_13_PU_UMSK       (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
#define GLB_REG_GPIO_13_PD            GLB_REG_GPIO_13_PD
#define GLB_REG_GPIO_13_PD_POS        (21U)
#define GLB_REG_GPIO_13_PD_LEN        (1U)
#define GLB_REG_GPIO_13_PD_MSK        (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
#define GLB_REG_GPIO_13_PD_UMSK       (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
#define GLB_REG_GPIO_13_FUNC_SEL      GLB_REG_GPIO_13_FUNC_SEL
#define GLB_REG_GPIO_13_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_13_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_13_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))

/* 0x11C : GPIO_CFGCTL7 */
#define GLB_GPIO_CFGCTL7_OFFSET       (0x11C)
#define GLB_REG_GPIO_14_IE            GLB_REG_GPIO_14_IE
#define GLB_REG_GPIO_14_IE_POS        (0U)
#define GLB_REG_GPIO_14_IE_LEN        (1U)
#define GLB_REG_GPIO_14_IE_MSK        (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
#define GLB_REG_GPIO_14_IE_UMSK       (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
#define GLB_REG_GPIO_14_SMT           GLB_REG_GPIO_14_SMT
#define GLB_REG_GPIO_14_SMT_POS       (1U)
#define GLB_REG_GPIO_14_SMT_LEN       (1U)
#define GLB_REG_GPIO_14_SMT_MSK       (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
#define GLB_REG_GPIO_14_SMT_UMSK      (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
#define GLB_REG_GPIO_14_DRV           GLB_REG_GPIO_14_DRV
#define GLB_REG_GPIO_14_DRV_POS       (2U)
#define GLB_REG_GPIO_14_DRV_LEN       (2U)
#define GLB_REG_GPIO_14_DRV_MSK       (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
#define GLB_REG_GPIO_14_DRV_UMSK      (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
#define GLB_REG_GPIO_14_PU            GLB_REG_GPIO_14_PU
#define GLB_REG_GPIO_14_PU_POS        (4U)
#define GLB_REG_GPIO_14_PU_LEN        (1U)
#define GLB_REG_GPIO_14_PU_MSK        (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
#define GLB_REG_GPIO_14_PU_UMSK       (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
#define GLB_REG_GPIO_14_PD            GLB_REG_GPIO_14_PD
#define GLB_REG_GPIO_14_PD_POS        (5U)
#define GLB_REG_GPIO_14_PD_LEN        (1U)
#define GLB_REG_GPIO_14_PD_MSK        (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
#define GLB_REG_GPIO_14_PD_UMSK       (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
#define GLB_REG_GPIO_14_FUNC_SEL      GLB_REG_GPIO_14_FUNC_SEL
#define GLB_REG_GPIO_14_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_14_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_14_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
#define GLB_REG_GPIO_15_IE            GLB_REG_GPIO_15_IE
#define GLB_REG_GPIO_15_IE_POS        (16U)
#define GLB_REG_GPIO_15_IE_LEN        (1U)
#define GLB_REG_GPIO_15_IE_MSK        (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
#define GLB_REG_GPIO_15_IE_UMSK       (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
#define GLB_REG_GPIO_15_SMT           GLB_REG_GPIO_15_SMT
#define GLB_REG_GPIO_15_SMT_POS       (17U)
#define GLB_REG_GPIO_15_SMT_LEN       (1U)
#define GLB_REG_GPIO_15_SMT_MSK       (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
#define GLB_REG_GPIO_15_SMT_UMSK      (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
#define GLB_REG_GPIO_15_DRV           GLB_REG_GPIO_15_DRV
#define GLB_REG_GPIO_15_DRV_POS       (18U)
#define GLB_REG_GPIO_15_DRV_LEN       (2U)
#define GLB_REG_GPIO_15_DRV_MSK       (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
#define GLB_REG_GPIO_15_DRV_UMSK      (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
#define GLB_REG_GPIO_15_PU            GLB_REG_GPIO_15_PU
#define GLB_REG_GPIO_15_PU_POS        (20U)
#define GLB_REG_GPIO_15_PU_LEN        (1U)
#define GLB_REG_GPIO_15_PU_MSK        (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
#define GLB_REG_GPIO_15_PU_UMSK       (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
#define GLB_REG_GPIO_15_PD            GLB_REG_GPIO_15_PD
#define GLB_REG_GPIO_15_PD_POS        (21U)
#define GLB_REG_GPIO_15_PD_LEN        (1U)
#define GLB_REG_GPIO_15_PD_MSK        (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
#define GLB_REG_GPIO_15_PD_UMSK       (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
#define GLB_REG_GPIO_15_FUNC_SEL      GLB_REG_GPIO_15_FUNC_SEL
#define GLB_REG_GPIO_15_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_15_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_15_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))

/* 0x120 : GPIO_CFGCTL8 */
#define GLB_GPIO_CFGCTL8_OFFSET       (0x120)
#define GLB_REG_GPIO_16_IE            GLB_REG_GPIO_16_IE
#define GLB_REG_GPIO_16_IE_POS        (0U)
#define GLB_REG_GPIO_16_IE_LEN        (1U)
#define GLB_REG_GPIO_16_IE_MSK        (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
#define GLB_REG_GPIO_16_IE_UMSK       (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
#define GLB_REG_GPIO_16_SMT           GLB_REG_GPIO_16_SMT
#define GLB_REG_GPIO_16_SMT_POS       (1U)
#define GLB_REG_GPIO_16_SMT_LEN       (1U)
#define GLB_REG_GPIO_16_SMT_MSK       (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
#define GLB_REG_GPIO_16_SMT_UMSK      (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
#define GLB_REG_GPIO_16_DRV           GLB_REG_GPIO_16_DRV
#define GLB_REG_GPIO_16_DRV_POS       (2U)
#define GLB_REG_GPIO_16_DRV_LEN       (2U)
#define GLB_REG_GPIO_16_DRV_MSK       (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
#define GLB_REG_GPIO_16_DRV_UMSK      (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
#define GLB_REG_GPIO_16_PU            GLB_REG_GPIO_16_PU
#define GLB_REG_GPIO_16_PU_POS        (4U)
#define GLB_REG_GPIO_16_PU_LEN        (1U)
#define GLB_REG_GPIO_16_PU_MSK        (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
#define GLB_REG_GPIO_16_PU_UMSK       (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
#define GLB_REG_GPIO_16_PD            GLB_REG_GPIO_16_PD
#define GLB_REG_GPIO_16_PD_POS        (5U)
#define GLB_REG_GPIO_16_PD_LEN        (1U)
#define GLB_REG_GPIO_16_PD_MSK        (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
#define GLB_REG_GPIO_16_PD_UMSK       (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
#define GLB_REG_GPIO_16_FUNC_SEL      GLB_REG_GPIO_16_FUNC_SEL
#define GLB_REG_GPIO_16_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_16_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_16_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
#define GLB_REG_GPIO_17_IE            GLB_REG_GPIO_17_IE
#define GLB_REG_GPIO_17_IE_POS        (16U)
#define GLB_REG_GPIO_17_IE_LEN        (1U)
#define GLB_REG_GPIO_17_IE_MSK        (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
#define GLB_REG_GPIO_17_IE_UMSK       (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
#define GLB_REG_GPIO_17_SMT           GLB_REG_GPIO_17_SMT
#define GLB_REG_GPIO_17_SMT_POS       (17U)
#define GLB_REG_GPIO_17_SMT_LEN       (1U)
#define GLB_REG_GPIO_17_SMT_MSK       (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
#define GLB_REG_GPIO_17_SMT_UMSK      (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
#define GLB_REG_GPIO_17_DRV           GLB_REG_GPIO_17_DRV
#define GLB_REG_GPIO_17_DRV_POS       (18U)
#define GLB_REG_GPIO_17_DRV_LEN       (2U)
#define GLB_REG_GPIO_17_DRV_MSK       (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
#define GLB_REG_GPIO_17_DRV_UMSK      (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
#define GLB_REG_GPIO_17_PU            GLB_REG_GPIO_17_PU
#define GLB_REG_GPIO_17_PU_POS        (20U)
#define GLB_REG_GPIO_17_PU_LEN        (1U)
#define GLB_REG_GPIO_17_PU_MSK        (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
#define GLB_REG_GPIO_17_PU_UMSK       (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
#define GLB_REG_GPIO_17_PD            GLB_REG_GPIO_17_PD
#define GLB_REG_GPIO_17_PD_POS        (21U)
#define GLB_REG_GPIO_17_PD_LEN        (1U)
#define GLB_REG_GPIO_17_PD_MSK        (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
#define GLB_REG_GPIO_17_PD_UMSK       (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
#define GLB_REG_GPIO_17_FUNC_SEL      GLB_REG_GPIO_17_FUNC_SEL
#define GLB_REG_GPIO_17_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_17_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_17_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))

/* 0x124 : GPIO_CFGCTL9 */
#define GLB_GPIO_CFGCTL9_OFFSET       (0x124)
#define GLB_REG_GPIO_18_IE            GLB_REG_GPIO_18_IE
#define GLB_REG_GPIO_18_IE_POS        (0U)
#define GLB_REG_GPIO_18_IE_LEN        (1U)
#define GLB_REG_GPIO_18_IE_MSK        (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
#define GLB_REG_GPIO_18_IE_UMSK       (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
#define GLB_REG_GPIO_18_SMT           GLB_REG_GPIO_18_SMT
#define GLB_REG_GPIO_18_SMT_POS       (1U)
#define GLB_REG_GPIO_18_SMT_LEN       (1U)
#define GLB_REG_GPIO_18_SMT_MSK       (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
#define GLB_REG_GPIO_18_SMT_UMSK      (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
#define GLB_REG_GPIO_18_DRV           GLB_REG_GPIO_18_DRV
#define GLB_REG_GPIO_18_DRV_POS       (2U)
#define GLB_REG_GPIO_18_DRV_LEN       (2U)
#define GLB_REG_GPIO_18_DRV_MSK       (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
#define GLB_REG_GPIO_18_DRV_UMSK      (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
#define GLB_REG_GPIO_18_PU            GLB_REG_GPIO_18_PU
#define GLB_REG_GPIO_18_PU_POS        (4U)
#define GLB_REG_GPIO_18_PU_LEN        (1U)
#define GLB_REG_GPIO_18_PU_MSK        (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
#define GLB_REG_GPIO_18_PU_UMSK       (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
#define GLB_REG_GPIO_18_PD            GLB_REG_GPIO_18_PD
#define GLB_REG_GPIO_18_PD_POS        (5U)
#define GLB_REG_GPIO_18_PD_LEN        (1U)
#define GLB_REG_GPIO_18_PD_MSK        (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
#define GLB_REG_GPIO_18_PD_UMSK       (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
#define GLB_REG_GPIO_18_FUNC_SEL      GLB_REG_GPIO_18_FUNC_SEL
#define GLB_REG_GPIO_18_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_18_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_18_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
#define GLB_REG_GPIO_19_IE            GLB_REG_GPIO_19_IE
#define GLB_REG_GPIO_19_IE_POS        (16U)
#define GLB_REG_GPIO_19_IE_LEN        (1U)
#define GLB_REG_GPIO_19_IE_MSK        (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
#define GLB_REG_GPIO_19_IE_UMSK       (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
#define GLB_REG_GPIO_19_SMT           GLB_REG_GPIO_19_SMT
#define GLB_REG_GPIO_19_SMT_POS       (17U)
#define GLB_REG_GPIO_19_SMT_LEN       (1U)
#define GLB_REG_GPIO_19_SMT_MSK       (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
#define GLB_REG_GPIO_19_SMT_UMSK      (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
#define GLB_REG_GPIO_19_DRV           GLB_REG_GPIO_19_DRV
#define GLB_REG_GPIO_19_DRV_POS       (18U)
#define GLB_REG_GPIO_19_DRV_LEN       (2U)
#define GLB_REG_GPIO_19_DRV_MSK       (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
#define GLB_REG_GPIO_19_DRV_UMSK      (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
#define GLB_REG_GPIO_19_PU            GLB_REG_GPIO_19_PU
#define GLB_REG_GPIO_19_PU_POS        (20U)
#define GLB_REG_GPIO_19_PU_LEN        (1U)
#define GLB_REG_GPIO_19_PU_MSK        (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
#define GLB_REG_GPIO_19_PU_UMSK       (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
#define GLB_REG_GPIO_19_PD            GLB_REG_GPIO_19_PD
#define GLB_REG_GPIO_19_PD_POS        (21U)
#define GLB_REG_GPIO_19_PD_LEN        (1U)
#define GLB_REG_GPIO_19_PD_MSK        (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
#define GLB_REG_GPIO_19_PD_UMSK       (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
#define GLB_REG_GPIO_19_FUNC_SEL      GLB_REG_GPIO_19_FUNC_SEL
#define GLB_REG_GPIO_19_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_19_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_19_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))

/* 0x128 : GPIO_CFGCTL10 */
#define GLB_GPIO_CFGCTL10_OFFSET      (0x128)
#define GLB_REG_GPIO_20_IE            GLB_REG_GPIO_20_IE
#define GLB_REG_GPIO_20_IE_POS        (0U)
#define GLB_REG_GPIO_20_IE_LEN        (1U)
#define GLB_REG_GPIO_20_IE_MSK        (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
#define GLB_REG_GPIO_20_IE_UMSK       (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
#define GLB_REG_GPIO_20_SMT           GLB_REG_GPIO_20_SMT
#define GLB_REG_GPIO_20_SMT_POS       (1U)
#define GLB_REG_GPIO_20_SMT_LEN       (1U)
#define GLB_REG_GPIO_20_SMT_MSK       (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
#define GLB_REG_GPIO_20_SMT_UMSK      (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
#define GLB_REG_GPIO_20_DRV           GLB_REG_GPIO_20_DRV
#define GLB_REG_GPIO_20_DRV_POS       (2U)
#define GLB_REG_GPIO_20_DRV_LEN       (2U)
#define GLB_REG_GPIO_20_DRV_MSK       (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
#define GLB_REG_GPIO_20_DRV_UMSK      (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
#define GLB_REG_GPIO_20_PU            GLB_REG_GPIO_20_PU
#define GLB_REG_GPIO_20_PU_POS        (4U)
#define GLB_REG_GPIO_20_PU_LEN        (1U)
#define GLB_REG_GPIO_20_PU_MSK        (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
#define GLB_REG_GPIO_20_PU_UMSK       (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
#define GLB_REG_GPIO_20_PD            GLB_REG_GPIO_20_PD
#define GLB_REG_GPIO_20_PD_POS        (5U)
#define GLB_REG_GPIO_20_PD_LEN        (1U)
#define GLB_REG_GPIO_20_PD_MSK        (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
#define GLB_REG_GPIO_20_PD_UMSK       (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
#define GLB_REG_GPIO_20_FUNC_SEL      GLB_REG_GPIO_20_FUNC_SEL
#define GLB_REG_GPIO_20_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_20_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_20_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
#define GLB_REG_GPIO_21_IE            GLB_REG_GPIO_21_IE
#define GLB_REG_GPIO_21_IE_POS        (16U)
#define GLB_REG_GPIO_21_IE_LEN        (1U)
#define GLB_REG_GPIO_21_IE_MSK        (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
#define GLB_REG_GPIO_21_IE_UMSK       (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
#define GLB_REG_GPIO_21_SMT           GLB_REG_GPIO_21_SMT
#define GLB_REG_GPIO_21_SMT_POS       (17U)
#define GLB_REG_GPIO_21_SMT_LEN       (1U)
#define GLB_REG_GPIO_21_SMT_MSK       (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
#define GLB_REG_GPIO_21_SMT_UMSK      (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
#define GLB_REG_GPIO_21_DRV           GLB_REG_GPIO_21_DRV
#define GLB_REG_GPIO_21_DRV_POS       (18U)
#define GLB_REG_GPIO_21_DRV_LEN       (2U)
#define GLB_REG_GPIO_21_DRV_MSK       (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
#define GLB_REG_GPIO_21_DRV_UMSK      (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
#define GLB_REG_GPIO_21_PU            GLB_REG_GPIO_21_PU
#define GLB_REG_GPIO_21_PU_POS        (20U)
#define GLB_REG_GPIO_21_PU_LEN        (1U)
#define GLB_REG_GPIO_21_PU_MSK        (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
#define GLB_REG_GPIO_21_PU_UMSK       (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
#define GLB_REG_GPIO_21_PD            GLB_REG_GPIO_21_PD
#define GLB_REG_GPIO_21_PD_POS        (21U)
#define GLB_REG_GPIO_21_PD_LEN        (1U)
#define GLB_REG_GPIO_21_PD_MSK        (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
#define GLB_REG_GPIO_21_PD_UMSK       (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
#define GLB_REG_GPIO_21_FUNC_SEL      GLB_REG_GPIO_21_FUNC_SEL
#define GLB_REG_GPIO_21_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_21_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_21_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))

/* 0x12C : GPIO_CFGCTL11 */
#define GLB_GPIO_CFGCTL11_OFFSET      (0x12C)
#define GLB_REG_GPIO_22_IE            GLB_REG_GPIO_22_IE
#define GLB_REG_GPIO_22_IE_POS        (0U)
#define GLB_REG_GPIO_22_IE_LEN        (1U)
#define GLB_REG_GPIO_22_IE_MSK        (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
#define GLB_REG_GPIO_22_IE_UMSK       (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
#define GLB_REG_GPIO_22_SMT           GLB_REG_GPIO_22_SMT
#define GLB_REG_GPIO_22_SMT_POS       (1U)
#define GLB_REG_GPIO_22_SMT_LEN       (1U)
#define GLB_REG_GPIO_22_SMT_MSK       (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
#define GLB_REG_GPIO_22_SMT_UMSK      (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
#define GLB_REG_GPIO_22_DRV           GLB_REG_GPIO_22_DRV
#define GLB_REG_GPIO_22_DRV_POS       (2U)
#define GLB_REG_GPIO_22_DRV_LEN       (2U)
#define GLB_REG_GPIO_22_DRV_MSK       (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
#define GLB_REG_GPIO_22_DRV_UMSK      (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
#define GLB_REG_GPIO_22_PU            GLB_REG_GPIO_22_PU
#define GLB_REG_GPIO_22_PU_POS        (4U)
#define GLB_REG_GPIO_22_PU_LEN        (1U)
#define GLB_REG_GPIO_22_PU_MSK        (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
#define GLB_REG_GPIO_22_PU_UMSK       (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
#define GLB_REG_GPIO_22_PD            GLB_REG_GPIO_22_PD
#define GLB_REG_GPIO_22_PD_POS        (5U)
#define GLB_REG_GPIO_22_PD_LEN        (1U)
#define GLB_REG_GPIO_22_PD_MSK        (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
#define GLB_REG_GPIO_22_PD_UMSK       (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
#define GLB_REG_GPIO_22_FUNC_SEL      GLB_REG_GPIO_22_FUNC_SEL
#define GLB_REG_GPIO_22_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_22_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_22_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
#define GLB_REG_GPIO_23_IE            GLB_REG_GPIO_23_IE
#define GLB_REG_GPIO_23_IE_POS        (16U)
#define GLB_REG_GPIO_23_IE_LEN        (1U)
#define GLB_REG_GPIO_23_IE_MSK        (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
#define GLB_REG_GPIO_23_IE_UMSK       (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
#define GLB_REG_GPIO_23_SMT           GLB_REG_GPIO_23_SMT
#define GLB_REG_GPIO_23_SMT_POS       (17U)
#define GLB_REG_GPIO_23_SMT_LEN       (1U)
#define GLB_REG_GPIO_23_SMT_MSK       (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
#define GLB_REG_GPIO_23_SMT_UMSK      (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
#define GLB_REG_GPIO_23_DRV           GLB_REG_GPIO_23_DRV
#define GLB_REG_GPIO_23_DRV_POS       (18U)
#define GLB_REG_GPIO_23_DRV_LEN       (2U)
#define GLB_REG_GPIO_23_DRV_MSK       (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
#define GLB_REG_GPIO_23_DRV_UMSK      (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
#define GLB_REG_GPIO_23_PU            GLB_REG_GPIO_23_PU
#define GLB_REG_GPIO_23_PU_POS        (20U)
#define GLB_REG_GPIO_23_PU_LEN        (1U)
#define GLB_REG_GPIO_23_PU_MSK        (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
#define GLB_REG_GPIO_23_PU_UMSK       (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
#define GLB_REG_GPIO_23_PD            GLB_REG_GPIO_23_PD
#define GLB_REG_GPIO_23_PD_POS        (21U)
#define GLB_REG_GPIO_23_PD_LEN        (1U)
#define GLB_REG_GPIO_23_PD_MSK        (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
#define GLB_REG_GPIO_23_PD_UMSK       (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
#define GLB_REG_GPIO_23_FUNC_SEL      GLB_REG_GPIO_23_FUNC_SEL
#define GLB_REG_GPIO_23_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_23_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_23_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)
#define GLB_REG_GPIO_23_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS))

/* 0x130 : GPIO_CFGCTL12 */
#define GLB_GPIO_CFGCTL12_OFFSET      (0x130)
#define GLB_REG_GPIO_24_IE            GLB_REG_GPIO_24_IE
#define GLB_REG_GPIO_24_IE_POS        (0U)
#define GLB_REG_GPIO_24_IE_LEN        (1U)
#define GLB_REG_GPIO_24_IE_MSK        (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
#define GLB_REG_GPIO_24_IE_UMSK       (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
#define GLB_REG_GPIO_24_SMT           GLB_REG_GPIO_24_SMT
#define GLB_REG_GPIO_24_SMT_POS       (1U)
#define GLB_REG_GPIO_24_SMT_LEN       (1U)
#define GLB_REG_GPIO_24_SMT_MSK       (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
#define GLB_REG_GPIO_24_SMT_UMSK      (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
#define GLB_REG_GPIO_24_DRV           GLB_REG_GPIO_24_DRV
#define GLB_REG_GPIO_24_DRV_POS       (2U)
#define GLB_REG_GPIO_24_DRV_LEN       (2U)
#define GLB_REG_GPIO_24_DRV_MSK       (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
#define GLB_REG_GPIO_24_DRV_UMSK      (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
#define GLB_REG_GPIO_24_PU            GLB_REG_GPIO_24_PU
#define GLB_REG_GPIO_24_PU_POS        (4U)
#define GLB_REG_GPIO_24_PU_LEN        (1U)
#define GLB_REG_GPIO_24_PU_MSK        (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
#define GLB_REG_GPIO_24_PU_UMSK       (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
#define GLB_REG_GPIO_24_PD            GLB_REG_GPIO_24_PD
#define GLB_REG_GPIO_24_PD_POS        (5U)
#define GLB_REG_GPIO_24_PD_LEN        (1U)
#define GLB_REG_GPIO_24_PD_MSK        (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
#define GLB_REG_GPIO_24_PD_UMSK       (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
#define GLB_REG_GPIO_24_FUNC_SEL      GLB_REG_GPIO_24_FUNC_SEL
#define GLB_REG_GPIO_24_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_24_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_24_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)
#define GLB_REG_GPIO_24_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS))
#define GLB_REG_GPIO_25_IE            GLB_REG_GPIO_25_IE
#define GLB_REG_GPIO_25_IE_POS        (16U)
#define GLB_REG_GPIO_25_IE_LEN        (1U)
#define GLB_REG_GPIO_25_IE_MSK        (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
#define GLB_REG_GPIO_25_IE_UMSK       (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
#define GLB_REG_GPIO_25_SMT           GLB_REG_GPIO_25_SMT
#define GLB_REG_GPIO_25_SMT_POS       (17U)
#define GLB_REG_GPIO_25_SMT_LEN       (1U)
#define GLB_REG_GPIO_25_SMT_MSK       (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
#define GLB_REG_GPIO_25_SMT_UMSK      (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
#define GLB_REG_GPIO_25_DRV           GLB_REG_GPIO_25_DRV
#define GLB_REG_GPIO_25_DRV_POS       (18U)
#define GLB_REG_GPIO_25_DRV_LEN       (2U)
#define GLB_REG_GPIO_25_DRV_MSK       (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
#define GLB_REG_GPIO_25_DRV_UMSK      (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
#define GLB_REG_GPIO_25_PU            GLB_REG_GPIO_25_PU
#define GLB_REG_GPIO_25_PU_POS        (20U)
#define GLB_REG_GPIO_25_PU_LEN        (1U)
#define GLB_REG_GPIO_25_PU_MSK        (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
#define GLB_REG_GPIO_25_PU_UMSK       (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
#define GLB_REG_GPIO_25_PD            GLB_REG_GPIO_25_PD
#define GLB_REG_GPIO_25_PD_POS        (21U)
#define GLB_REG_GPIO_25_PD_LEN        (1U)
#define GLB_REG_GPIO_25_PD_MSK        (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
#define GLB_REG_GPIO_25_PD_UMSK       (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
#define GLB_REG_GPIO_25_FUNC_SEL      GLB_REG_GPIO_25_FUNC_SEL
#define GLB_REG_GPIO_25_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_25_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_25_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)
#define GLB_REG_GPIO_25_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS))

/* 0x134 : GPIO_CFGCTL13 */
#define GLB_GPIO_CFGCTL13_OFFSET      (0x134)
#define GLB_REG_GPIO_26_IE            GLB_REG_GPIO_26_IE
#define GLB_REG_GPIO_26_IE_POS        (0U)
#define GLB_REG_GPIO_26_IE_LEN        (1U)
#define GLB_REG_GPIO_26_IE_MSK        (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
#define GLB_REG_GPIO_26_IE_UMSK       (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
#define GLB_REG_GPIO_26_SMT           GLB_REG_GPIO_26_SMT
#define GLB_REG_GPIO_26_SMT_POS       (1U)
#define GLB_REG_GPIO_26_SMT_LEN       (1U)
#define GLB_REG_GPIO_26_SMT_MSK       (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
#define GLB_REG_GPIO_26_SMT_UMSK      (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
#define GLB_REG_GPIO_26_DRV           GLB_REG_GPIO_26_DRV
#define GLB_REG_GPIO_26_DRV_POS       (2U)
#define GLB_REG_GPIO_26_DRV_LEN       (2U)
#define GLB_REG_GPIO_26_DRV_MSK       (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
#define GLB_REG_GPIO_26_DRV_UMSK      (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
#define GLB_REG_GPIO_26_PU            GLB_REG_GPIO_26_PU
#define GLB_REG_GPIO_26_PU_POS        (4U)
#define GLB_REG_GPIO_26_PU_LEN        (1U)
#define GLB_REG_GPIO_26_PU_MSK        (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
#define GLB_REG_GPIO_26_PU_UMSK       (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
#define GLB_REG_GPIO_26_PD            GLB_REG_GPIO_26_PD
#define GLB_REG_GPIO_26_PD_POS        (5U)
#define GLB_REG_GPIO_26_PD_LEN        (1U)
#define GLB_REG_GPIO_26_PD_MSK        (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
#define GLB_REG_GPIO_26_PD_UMSK       (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
#define GLB_REG_GPIO_26_FUNC_SEL      GLB_REG_GPIO_26_FUNC_SEL
#define GLB_REG_GPIO_26_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_26_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_26_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)
#define GLB_REG_GPIO_26_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS))
#define GLB_REG_GPIO_27_IE            GLB_REG_GPIO_27_IE
#define GLB_REG_GPIO_27_IE_POS        (16U)
#define GLB_REG_GPIO_27_IE_LEN        (1U)
#define GLB_REG_GPIO_27_IE_MSK        (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
#define GLB_REG_GPIO_27_IE_UMSK       (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
#define GLB_REG_GPIO_27_SMT           GLB_REG_GPIO_27_SMT
#define GLB_REG_GPIO_27_SMT_POS       (17U)
#define GLB_REG_GPIO_27_SMT_LEN       (1U)
#define GLB_REG_GPIO_27_SMT_MSK       (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
#define GLB_REG_GPIO_27_SMT_UMSK      (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
#define GLB_REG_GPIO_27_DRV           GLB_REG_GPIO_27_DRV
#define GLB_REG_GPIO_27_DRV_POS       (18U)
#define GLB_REG_GPIO_27_DRV_LEN       (2U)
#define GLB_REG_GPIO_27_DRV_MSK       (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
#define GLB_REG_GPIO_27_DRV_UMSK      (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
#define GLB_REG_GPIO_27_PU            GLB_REG_GPIO_27_PU
#define GLB_REG_GPIO_27_PU_POS        (20U)
#define GLB_REG_GPIO_27_PU_LEN        (1U)
#define GLB_REG_GPIO_27_PU_MSK        (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
#define GLB_REG_GPIO_27_PU_UMSK       (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
#define GLB_REG_GPIO_27_PD            GLB_REG_GPIO_27_PD
#define GLB_REG_GPIO_27_PD_POS        (21U)
#define GLB_REG_GPIO_27_PD_LEN        (1U)
#define GLB_REG_GPIO_27_PD_MSK        (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
#define GLB_REG_GPIO_27_PD_UMSK       (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
#define GLB_REG_GPIO_27_FUNC_SEL      GLB_REG_GPIO_27_FUNC_SEL
#define GLB_REG_GPIO_27_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_27_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_27_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)
#define GLB_REG_GPIO_27_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS))

/* 0x138 : GPIO_CFGCTL14 */
#define GLB_GPIO_CFGCTL14_OFFSET      (0x138)
#define GLB_REG_GPIO_28_IE            GLB_REG_GPIO_28_IE
#define GLB_REG_GPIO_28_IE_POS        (0U)
#define GLB_REG_GPIO_28_IE_LEN        (1U)
#define GLB_REG_GPIO_28_IE_MSK        (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
#define GLB_REG_GPIO_28_IE_UMSK       (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
#define GLB_REG_GPIO_28_SMT           GLB_REG_GPIO_28_SMT
#define GLB_REG_GPIO_28_SMT_POS       (1U)
#define GLB_REG_GPIO_28_SMT_LEN       (1U)
#define GLB_REG_GPIO_28_SMT_MSK       (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
#define GLB_REG_GPIO_28_SMT_UMSK      (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
#define GLB_REG_GPIO_28_DRV           GLB_REG_GPIO_28_DRV
#define GLB_REG_GPIO_28_DRV_POS       (2U)
#define GLB_REG_GPIO_28_DRV_LEN       (2U)
#define GLB_REG_GPIO_28_DRV_MSK       (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
#define GLB_REG_GPIO_28_DRV_UMSK      (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
#define GLB_REG_GPIO_28_PU            GLB_REG_GPIO_28_PU
#define GLB_REG_GPIO_28_PU_POS        (4U)
#define GLB_REG_GPIO_28_PU_LEN        (1U)
#define GLB_REG_GPIO_28_PU_MSK        (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
#define GLB_REG_GPIO_28_PU_UMSK       (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
#define GLB_REG_GPIO_28_PD            GLB_REG_GPIO_28_PD
#define GLB_REG_GPIO_28_PD_POS        (5U)
#define GLB_REG_GPIO_28_PD_LEN        (1U)
#define GLB_REG_GPIO_28_PD_MSK        (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
#define GLB_REG_GPIO_28_PD_UMSK       (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
#define GLB_REG_GPIO_28_FUNC_SEL      GLB_REG_GPIO_28_FUNC_SEL
#define GLB_REG_GPIO_28_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_28_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_28_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)
#define GLB_REG_GPIO_28_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS))
#define GLB_REG_GPIO_29_IE            GLB_REG_GPIO_29_IE
#define GLB_REG_GPIO_29_IE_POS        (16U)
#define GLB_REG_GPIO_29_IE_LEN        (1U)
#define GLB_REG_GPIO_29_IE_MSK        (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)
#define GLB_REG_GPIO_29_IE_UMSK       (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS))
#define GLB_REG_GPIO_29_SMT           GLB_REG_GPIO_29_SMT
#define GLB_REG_GPIO_29_SMT_POS       (17U)
#define GLB_REG_GPIO_29_SMT_LEN       (1U)
#define GLB_REG_GPIO_29_SMT_MSK       (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)
#define GLB_REG_GPIO_29_SMT_UMSK      (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS))
#define GLB_REG_GPIO_29_DRV           GLB_REG_GPIO_29_DRV
#define GLB_REG_GPIO_29_DRV_POS       (18U)
#define GLB_REG_GPIO_29_DRV_LEN       (2U)
#define GLB_REG_GPIO_29_DRV_MSK       (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)
#define GLB_REG_GPIO_29_DRV_UMSK      (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS))
#define GLB_REG_GPIO_29_PU            GLB_REG_GPIO_29_PU
#define GLB_REG_GPIO_29_PU_POS        (20U)
#define GLB_REG_GPIO_29_PU_LEN        (1U)
#define GLB_REG_GPIO_29_PU_MSK        (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)
#define GLB_REG_GPIO_29_PU_UMSK       (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS))
#define GLB_REG_GPIO_29_PD            GLB_REG_GPIO_29_PD
#define GLB_REG_GPIO_29_PD_POS        (21U)
#define GLB_REG_GPIO_29_PD_LEN        (1U)
#define GLB_REG_GPIO_29_PD_MSK        (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)
#define GLB_REG_GPIO_29_PD_UMSK       (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS))
#define GLB_REG_GPIO_29_FUNC_SEL      GLB_REG_GPIO_29_FUNC_SEL
#define GLB_REG_GPIO_29_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_29_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_29_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)
#define GLB_REG_GPIO_29_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS))

/* 0x13C : GPIO_CFGCTL15 */
#define GLB_GPIO_CFGCTL15_OFFSET      (0x13C)
#define GLB_REG_GPIO_30_IE            GLB_REG_GPIO_30_IE
#define GLB_REG_GPIO_30_IE_POS        (0U)
#define GLB_REG_GPIO_30_IE_LEN        (1U)
#define GLB_REG_GPIO_30_IE_MSK        (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)
#define GLB_REG_GPIO_30_IE_UMSK       (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS))
#define GLB_REG_GPIO_30_SMT           GLB_REG_GPIO_30_SMT
#define GLB_REG_GPIO_30_SMT_POS       (1U)
#define GLB_REG_GPIO_30_SMT_LEN       (1U)
#define GLB_REG_GPIO_30_SMT_MSK       (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)
#define GLB_REG_GPIO_30_SMT_UMSK      (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS))
#define GLB_REG_GPIO_30_DRV           GLB_REG_GPIO_30_DRV
#define GLB_REG_GPIO_30_DRV_POS       (2U)
#define GLB_REG_GPIO_30_DRV_LEN       (2U)
#define GLB_REG_GPIO_30_DRV_MSK       (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)
#define GLB_REG_GPIO_30_DRV_UMSK      (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS))
#define GLB_REG_GPIO_30_PU            GLB_REG_GPIO_30_PU
#define GLB_REG_GPIO_30_PU_POS        (4U)
#define GLB_REG_GPIO_30_PU_LEN        (1U)
#define GLB_REG_GPIO_30_PU_MSK        (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)
#define GLB_REG_GPIO_30_PU_UMSK       (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS))
#define GLB_REG_GPIO_30_PD            GLB_REG_GPIO_30_PD
#define GLB_REG_GPIO_30_PD_POS        (5U)
#define GLB_REG_GPIO_30_PD_LEN        (1U)
#define GLB_REG_GPIO_30_PD_MSK        (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)
#define GLB_REG_GPIO_30_PD_UMSK       (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS))
#define GLB_REG_GPIO_30_FUNC_SEL      GLB_REG_GPIO_30_FUNC_SEL
#define GLB_REG_GPIO_30_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_30_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_30_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)
#define GLB_REG_GPIO_30_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS))
#define GLB_REG_GPIO_31_IE            GLB_REG_GPIO_31_IE
#define GLB_REG_GPIO_31_IE_POS        (16U)
#define GLB_REG_GPIO_31_IE_LEN        (1U)
#define GLB_REG_GPIO_31_IE_MSK        (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)
#define GLB_REG_GPIO_31_IE_UMSK       (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS))
#define GLB_REG_GPIO_31_SMT           GLB_REG_GPIO_31_SMT
#define GLB_REG_GPIO_31_SMT_POS       (17U)
#define GLB_REG_GPIO_31_SMT_LEN       (1U)
#define GLB_REG_GPIO_31_SMT_MSK       (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)
#define GLB_REG_GPIO_31_SMT_UMSK      (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS))
#define GLB_REG_GPIO_31_DRV           GLB_REG_GPIO_31_DRV
#define GLB_REG_GPIO_31_DRV_POS       (18U)
#define GLB_REG_GPIO_31_DRV_LEN       (2U)
#define GLB_REG_GPIO_31_DRV_MSK       (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)
#define GLB_REG_GPIO_31_DRV_UMSK      (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS))
#define GLB_REG_GPIO_31_PU            GLB_REG_GPIO_31_PU
#define GLB_REG_GPIO_31_PU_POS        (20U)
#define GLB_REG_GPIO_31_PU_LEN        (1U)
#define GLB_REG_GPIO_31_PU_MSK        (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)
#define GLB_REG_GPIO_31_PU_UMSK       (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS))
#define GLB_REG_GPIO_31_PD            GLB_REG_GPIO_31_PD
#define GLB_REG_GPIO_31_PD_POS        (21U)
#define GLB_REG_GPIO_31_PD_LEN        (1U)
#define GLB_REG_GPIO_31_PD_MSK        (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)
#define GLB_REG_GPIO_31_PD_UMSK       (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS))
#define GLB_REG_GPIO_31_FUNC_SEL      GLB_REG_GPIO_31_FUNC_SEL
#define GLB_REG_GPIO_31_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_31_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_31_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)
#define GLB_REG_GPIO_31_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS))

/* 0x140 : GPIO_CFGCTL16 */
#define GLB_GPIO_CFGCTL16_OFFSET (0x140)
#define GLB_REG_GPIO_32_IE       GLB_REG_GPIO_32_IE
#define GLB_REG_GPIO_32_IE_POS   (0U)
#define GLB_REG_GPIO_32_IE_LEN   (1U)
#define GLB_REG_GPIO_32_IE_MSK   (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)
#define GLB_REG_GPIO_32_IE_UMSK  (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS))
#define GLB_REG_GPIO_32_SMT      GLB_REG_GPIO_32_SMT
#define GLB_REG_GPIO_32_SMT_POS  (1U)
#define GLB_REG_GPIO_32_SMT_LEN  (1U)
#define GLB_REG_GPIO_32_SMT_MSK  (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)
#define GLB_REG_GPIO_32_SMT_UMSK (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS))
#define GLB_REG_GPIO_32_DRV      GLB_REG_GPIO_32_DRV
#define GLB_REG_GPIO_32_DRV_POS  (2U)
#define GLB_REG_GPIO_32_DRV_LEN  (2U)
#define GLB_REG_GPIO_32_DRV_MSK  (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)
#define GLB_REG_GPIO_32_DRV_UMSK (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS))
#define GLB_REG_GPIO_32_PU       GLB_REG_GPIO_32_PU
#define GLB_REG_GPIO_32_PU_POS   (4U)
#define GLB_REG_GPIO_32_PU_LEN   (1U)
#define GLB_REG_GPIO_32_PU_MSK   (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)
#define GLB_REG_GPIO_32_PU_UMSK  (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS))
#define GLB_REG_GPIO_32_PD       GLB_REG_GPIO_32_PD
#define GLB_REG_GPIO_32_PD_POS   (5U)
#define GLB_REG_GPIO_32_PD_LEN   (1U)
#define GLB_REG_GPIO_32_PD_MSK   (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)
#define GLB_REG_GPIO_32_PD_UMSK  (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS))
#define GLB_REG_GPIO_33_IE       GLB_REG_GPIO_33_IE
#define GLB_REG_GPIO_33_IE_POS   (16U)
#define GLB_REG_GPIO_33_IE_LEN   (1U)
#define GLB_REG_GPIO_33_IE_MSK   (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)
#define GLB_REG_GPIO_33_IE_UMSK  (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS))
#define GLB_REG_GPIO_33_SMT      GLB_REG_GPIO_33_SMT
#define GLB_REG_GPIO_33_SMT_POS  (17U)
#define GLB_REG_GPIO_33_SMT_LEN  (1U)
#define GLB_REG_GPIO_33_SMT_MSK  (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)
#define GLB_REG_GPIO_33_SMT_UMSK (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS))
#define GLB_REG_GPIO_33_DRV      GLB_REG_GPIO_33_DRV
#define GLB_REG_GPIO_33_DRV_POS  (18U)
#define GLB_REG_GPIO_33_DRV_LEN  (2U)
#define GLB_REG_GPIO_33_DRV_MSK  (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)
#define GLB_REG_GPIO_33_DRV_UMSK (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS))
#define GLB_REG_GPIO_33_PU       GLB_REG_GPIO_33_PU
#define GLB_REG_GPIO_33_PU_POS   (20U)
#define GLB_REG_GPIO_33_PU_LEN   (1U)
#define GLB_REG_GPIO_33_PU_MSK   (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)
#define GLB_REG_GPIO_33_PU_UMSK  (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS))
#define GLB_REG_GPIO_33_PD       GLB_REG_GPIO_33_PD
#define GLB_REG_GPIO_33_PD_POS   (21U)
#define GLB_REG_GPIO_33_PD_LEN   (1U)
#define GLB_REG_GPIO_33_PD_MSK   (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)
#define GLB_REG_GPIO_33_PD_UMSK  (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS))

/* 0x144 : GPIO_CFGCTL17 */
#define GLB_GPIO_CFGCTL17_OFFSET (0x144)
#define GLB_REG_GPIO_34_IE       GLB_REG_GPIO_34_IE
#define GLB_REG_GPIO_34_IE_POS   (0U)
#define GLB_REG_GPIO_34_IE_LEN   (1U)
#define GLB_REG_GPIO_34_IE_MSK   (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)
#define GLB_REG_GPIO_34_IE_UMSK  (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS))
#define GLB_REG_GPIO_34_SMT      GLB_REG_GPIO_34_SMT
#define GLB_REG_GPIO_34_SMT_POS  (1U)
#define GLB_REG_GPIO_34_SMT_LEN  (1U)
#define GLB_REG_GPIO_34_SMT_MSK  (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)
#define GLB_REG_GPIO_34_SMT_UMSK (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS))
#define GLB_REG_GPIO_34_DRV      GLB_REG_GPIO_34_DRV
#define GLB_REG_GPIO_34_DRV_POS  (2U)
#define GLB_REG_GPIO_34_DRV_LEN  (2U)
#define GLB_REG_GPIO_34_DRV_MSK  (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)
#define GLB_REG_GPIO_34_DRV_UMSK (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS))
#define GLB_REG_GPIO_34_PU       GLB_REG_GPIO_34_PU
#define GLB_REG_GPIO_34_PU_POS   (4U)
#define GLB_REG_GPIO_34_PU_LEN   (1U)
#define GLB_REG_GPIO_34_PU_MSK   (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)
#define GLB_REG_GPIO_34_PU_UMSK  (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS))
#define GLB_REG_GPIO_34_PD       GLB_REG_GPIO_34_PD
#define GLB_REG_GPIO_34_PD_POS   (5U)
#define GLB_REG_GPIO_34_PD_LEN   (1U)
#define GLB_REG_GPIO_34_PD_MSK   (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)
#define GLB_REG_GPIO_34_PD_UMSK  (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS))
#define GLB_REG_GPIO_35_IE       GLB_REG_GPIO_35_IE
#define GLB_REG_GPIO_35_IE_POS   (16U)
#define GLB_REG_GPIO_35_IE_LEN   (1U)
#define GLB_REG_GPIO_35_IE_MSK   (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)
#define GLB_REG_GPIO_35_IE_UMSK  (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS))
#define GLB_REG_GPIO_35_SMT      GLB_REG_GPIO_35_SMT
#define GLB_REG_GPIO_35_SMT_POS  (17U)
#define GLB_REG_GPIO_35_SMT_LEN  (1U)
#define GLB_REG_GPIO_35_SMT_MSK  (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)
#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS))
#define GLB_REG_GPIO_35_DRV      GLB_REG_GPIO_35_DRV
#define GLB_REG_GPIO_35_DRV_POS  (18U)
#define GLB_REG_GPIO_35_DRV_LEN  (2U)
#define GLB_REG_GPIO_35_DRV_MSK  (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)
#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS))
#define GLB_REG_GPIO_35_PU       GLB_REG_GPIO_35_PU
#define GLB_REG_GPIO_35_PU_POS   (20U)
#define GLB_REG_GPIO_35_PU_LEN   (1U)
#define GLB_REG_GPIO_35_PU_MSK   (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)
#define GLB_REG_GPIO_35_PU_UMSK  (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS))
#define GLB_REG_GPIO_35_PD       GLB_REG_GPIO_35_PD
#define GLB_REG_GPIO_35_PD_POS   (21U)
#define GLB_REG_GPIO_35_PD_LEN   (1U)
#define GLB_REG_GPIO_35_PD_MSK   (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)
#define GLB_REG_GPIO_35_PD_UMSK  (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS))

/* 0x148 : GPIO_CFGCTL18 */
#define GLB_GPIO_CFGCTL18_OFFSET (0x148)
#define GLB_REG_GPIO_36_IE       GLB_REG_GPIO_36_IE
#define GLB_REG_GPIO_36_IE_POS   (0U)
#define GLB_REG_GPIO_36_IE_LEN   (1U)
#define GLB_REG_GPIO_36_IE_MSK   (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)
#define GLB_REG_GPIO_36_IE_UMSK  (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS))
#define GLB_REG_GPIO_36_SMT      GLB_REG_GPIO_36_SMT
#define GLB_REG_GPIO_36_SMT_POS  (1U)
#define GLB_REG_GPIO_36_SMT_LEN  (1U)
#define GLB_REG_GPIO_36_SMT_MSK  (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)
#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS))
#define GLB_REG_GPIO_36_DRV      GLB_REG_GPIO_36_DRV
#define GLB_REG_GPIO_36_DRV_POS  (2U)
#define GLB_REG_GPIO_36_DRV_LEN  (2U)
#define GLB_REG_GPIO_36_DRV_MSK  (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)
#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS))
#define GLB_REG_GPIO_36_PU       GLB_REG_GPIO_36_PU
#define GLB_REG_GPIO_36_PU_POS   (4U)
#define GLB_REG_GPIO_36_PU_LEN   (1U)
#define GLB_REG_GPIO_36_PU_MSK   (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)
#define GLB_REG_GPIO_36_PU_UMSK  (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS))
#define GLB_REG_GPIO_36_PD       GLB_REG_GPIO_36_PD
#define GLB_REG_GPIO_36_PD_POS   (5U)
#define GLB_REG_GPIO_36_PD_LEN   (1U)
#define GLB_REG_GPIO_36_PD_MSK   (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)
#define GLB_REG_GPIO_36_PD_UMSK  (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS))
#define GLB_REG_GPIO_37_IE       GLB_REG_GPIO_37_IE
#define GLB_REG_GPIO_37_IE_POS   (16U)
#define GLB_REG_GPIO_37_IE_LEN   (1U)
#define GLB_REG_GPIO_37_IE_MSK   (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)
#define GLB_REG_GPIO_37_IE_UMSK  (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS))
#define GLB_REG_GPIO_37_SMT      GLB_REG_GPIO_37_SMT
#define GLB_REG_GPIO_37_SMT_POS  (17U)
#define GLB_REG_GPIO_37_SMT_LEN  (1U)
#define GLB_REG_GPIO_37_SMT_MSK  (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)
#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS))
#define GLB_REG_GPIO_37_DRV      GLB_REG_GPIO_37_DRV
#define GLB_REG_GPIO_37_DRV_POS  (18U)
#define GLB_REG_GPIO_37_DRV_LEN  (2U)
#define GLB_REG_GPIO_37_DRV_MSK  (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)
#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS))
#define GLB_REG_GPIO_37_PU       GLB_REG_GPIO_37_PU
#define GLB_REG_GPIO_37_PU_POS   (20U)
#define GLB_REG_GPIO_37_PU_LEN   (1U)
#define GLB_REG_GPIO_37_PU_MSK   (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)
#define GLB_REG_GPIO_37_PU_UMSK  (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS))
#define GLB_REG_GPIO_37_PD       GLB_REG_GPIO_37_PD
#define GLB_REG_GPIO_37_PD_POS   (21U)
#define GLB_REG_GPIO_37_PD_LEN   (1U)
#define GLB_REG_GPIO_37_PD_MSK   (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)
#define GLB_REG_GPIO_37_PD_UMSK  (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS))

/* 0x180 : GPIO_CFGCTL30 */
#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
#define GLB_REG_GPIO_0_I         GLB_REG_GPIO_0_I
#define GLB_REG_GPIO_0_I_POS     (0U)
#define GLB_REG_GPIO_0_I_LEN     (1U)
#define GLB_REG_GPIO_0_I_MSK     (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
#define GLB_REG_GPIO_0_I_UMSK    (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
#define GLB_REG_GPIO_1_I         GLB_REG_GPIO_1_I
#define GLB_REG_GPIO_1_I_POS     (1U)
#define GLB_REG_GPIO_1_I_LEN     (1U)
#define GLB_REG_GPIO_1_I_MSK     (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
#define GLB_REG_GPIO_1_I_UMSK    (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
#define GLB_REG_GPIO_2_I         GLB_REG_GPIO_2_I
#define GLB_REG_GPIO_2_I_POS     (2U)
#define GLB_REG_GPIO_2_I_LEN     (1U)
#define GLB_REG_GPIO_2_I_MSK     (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
#define GLB_REG_GPIO_2_I_UMSK    (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
#define GLB_REG_GPIO_3_I         GLB_REG_GPIO_3_I
#define GLB_REG_GPIO_3_I_POS     (3U)
#define GLB_REG_GPIO_3_I_LEN     (1U)
#define GLB_REG_GPIO_3_I_MSK     (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
#define GLB_REG_GPIO_3_I_UMSK    (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
#define GLB_REG_GPIO_4_I         GLB_REG_GPIO_4_I
#define GLB_REG_GPIO_4_I_POS     (4U)
#define GLB_REG_GPIO_4_I_LEN     (1U)
#define GLB_REG_GPIO_4_I_MSK     (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
#define GLB_REG_GPIO_4_I_UMSK    (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
#define GLB_REG_GPIO_5_I         GLB_REG_GPIO_5_I
#define GLB_REG_GPIO_5_I_POS     (5U)
#define GLB_REG_GPIO_5_I_LEN     (1U)
#define GLB_REG_GPIO_5_I_MSK     (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
#define GLB_REG_GPIO_5_I_UMSK    (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
#define GLB_REG_GPIO_6_I         GLB_REG_GPIO_6_I
#define GLB_REG_GPIO_6_I_POS     (6U)
#define GLB_REG_GPIO_6_I_LEN     (1U)
#define GLB_REG_GPIO_6_I_MSK     (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
#define GLB_REG_GPIO_6_I_UMSK    (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
#define GLB_REG_GPIO_7_I         GLB_REG_GPIO_7_I
#define GLB_REG_GPIO_7_I_POS     (7U)
#define GLB_REG_GPIO_7_I_LEN     (1U)
#define GLB_REG_GPIO_7_I_MSK     (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
#define GLB_REG_GPIO_7_I_UMSK    (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
#define GLB_REG_GPIO_8_I         GLB_REG_GPIO_8_I
#define GLB_REG_GPIO_8_I_POS     (8U)
#define GLB_REG_GPIO_8_I_LEN     (1U)
#define GLB_REG_GPIO_8_I_MSK     (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
#define GLB_REG_GPIO_8_I_UMSK    (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
#define GLB_REG_GPIO_9_I         GLB_REG_GPIO_9_I
#define GLB_REG_GPIO_9_I_POS     (9U)
#define GLB_REG_GPIO_9_I_LEN     (1U)
#define GLB_REG_GPIO_9_I_MSK     (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
#define GLB_REG_GPIO_9_I_UMSK    (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
#define GLB_REG_GPIO_10_I        GLB_REG_GPIO_10_I
#define GLB_REG_GPIO_10_I_POS    (10U)
#define GLB_REG_GPIO_10_I_LEN    (1U)
#define GLB_REG_GPIO_10_I_MSK    (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
#define GLB_REG_GPIO_10_I_UMSK   (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
#define GLB_REG_GPIO_11_I        GLB_REG_GPIO_11_I
#define GLB_REG_GPIO_11_I_POS    (11U)
#define GLB_REG_GPIO_11_I_LEN    (1U)
#define GLB_REG_GPIO_11_I_MSK    (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
#define GLB_REG_GPIO_11_I_UMSK   (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
#define GLB_REG_GPIO_12_I        GLB_REG_GPIO_12_I
#define GLB_REG_GPIO_12_I_POS    (12U)
#define GLB_REG_GPIO_12_I_LEN    (1U)
#define GLB_REG_GPIO_12_I_MSK    (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
#define GLB_REG_GPIO_12_I_UMSK   (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
#define GLB_REG_GPIO_13_I        GLB_REG_GPIO_13_I
#define GLB_REG_GPIO_13_I_POS    (13U)
#define GLB_REG_GPIO_13_I_LEN    (1U)
#define GLB_REG_GPIO_13_I_MSK    (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
#define GLB_REG_GPIO_13_I_UMSK   (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
#define GLB_REG_GPIO_14_I        GLB_REG_GPIO_14_I
#define GLB_REG_GPIO_14_I_POS    (14U)
#define GLB_REG_GPIO_14_I_LEN    (1U)
#define GLB_REG_GPIO_14_I_MSK    (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
#define GLB_REG_GPIO_14_I_UMSK   (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
#define GLB_REG_GPIO_15_I        GLB_REG_GPIO_15_I
#define GLB_REG_GPIO_15_I_POS    (15U)
#define GLB_REG_GPIO_15_I_LEN    (1U)
#define GLB_REG_GPIO_15_I_MSK    (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
#define GLB_REG_GPIO_15_I_UMSK   (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
#define GLB_REG_GPIO_16_I        GLB_REG_GPIO_16_I
#define GLB_REG_GPIO_16_I_POS    (16U)
#define GLB_REG_GPIO_16_I_LEN    (1U)
#define GLB_REG_GPIO_16_I_MSK    (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
#define GLB_REG_GPIO_16_I_UMSK   (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
#define GLB_REG_GPIO_17_I        GLB_REG_GPIO_17_I
#define GLB_REG_GPIO_17_I_POS    (17U)
#define GLB_REG_GPIO_17_I_LEN    (1U)
#define GLB_REG_GPIO_17_I_MSK    (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
#define GLB_REG_GPIO_17_I_UMSK   (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
#define GLB_REG_GPIO_18_I        GLB_REG_GPIO_18_I
#define GLB_REG_GPIO_18_I_POS    (18U)
#define GLB_REG_GPIO_18_I_LEN    (1U)
#define GLB_REG_GPIO_18_I_MSK    (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
#define GLB_REG_GPIO_18_I_UMSK   (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
#define GLB_REG_GPIO_19_I        GLB_REG_GPIO_19_I
#define GLB_REG_GPIO_19_I_POS    (19U)
#define GLB_REG_GPIO_19_I_LEN    (1U)
#define GLB_REG_GPIO_19_I_MSK    (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
#define GLB_REG_GPIO_19_I_UMSK   (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
#define GLB_REG_GPIO_20_I        GLB_REG_GPIO_20_I
#define GLB_REG_GPIO_20_I_POS    (20U)
#define GLB_REG_GPIO_20_I_LEN    (1U)
#define GLB_REG_GPIO_20_I_MSK    (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
#define GLB_REG_GPIO_20_I_UMSK   (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
#define GLB_REG_GPIO_21_I        GLB_REG_GPIO_21_I
#define GLB_REG_GPIO_21_I_POS    (21U)
#define GLB_REG_GPIO_21_I_LEN    (1U)
#define GLB_REG_GPIO_21_I_MSK    (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
#define GLB_REG_GPIO_21_I_UMSK   (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
#define GLB_REG_GPIO_22_I        GLB_REG_GPIO_22_I
#define GLB_REG_GPIO_22_I_POS    (22U)
#define GLB_REG_GPIO_22_I_LEN    (1U)
#define GLB_REG_GPIO_22_I_MSK    (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
#define GLB_REG_GPIO_22_I_UMSK   (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
#define GLB_REG_GPIO_23_I        GLB_REG_GPIO_23_I
#define GLB_REG_GPIO_23_I_POS    (23U)
#define GLB_REG_GPIO_23_I_LEN    (1U)
#define GLB_REG_GPIO_23_I_MSK    (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)
#define GLB_REG_GPIO_23_I_UMSK   (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS))
#define GLB_REG_GPIO_24_I        GLB_REG_GPIO_24_I
#define GLB_REG_GPIO_24_I_POS    (24U)
#define GLB_REG_GPIO_24_I_LEN    (1U)
#define GLB_REG_GPIO_24_I_MSK    (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)
#define GLB_REG_GPIO_24_I_UMSK   (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS))
#define GLB_REG_GPIO_25_I        GLB_REG_GPIO_25_I
#define GLB_REG_GPIO_25_I_POS    (25U)
#define GLB_REG_GPIO_25_I_LEN    (1U)
#define GLB_REG_GPIO_25_I_MSK    (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)
#define GLB_REG_GPIO_25_I_UMSK   (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS))
#define GLB_REG_GPIO_26_I        GLB_REG_GPIO_26_I
#define GLB_REG_GPIO_26_I_POS    (26U)
#define GLB_REG_GPIO_26_I_LEN    (1U)
#define GLB_REG_GPIO_26_I_MSK    (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)
#define GLB_REG_GPIO_26_I_UMSK   (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS))
#define GLB_REG_GPIO_27_I        GLB_REG_GPIO_27_I
#define GLB_REG_GPIO_27_I_POS    (27U)
#define GLB_REG_GPIO_27_I_LEN    (1U)
#define GLB_REG_GPIO_27_I_MSK    (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)
#define GLB_REG_GPIO_27_I_UMSK   (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS))
#define GLB_REG_GPIO_28_I        GLB_REG_GPIO_28_I
#define GLB_REG_GPIO_28_I_POS    (28U)
#define GLB_REG_GPIO_28_I_LEN    (1U)
#define GLB_REG_GPIO_28_I_MSK    (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)
#define GLB_REG_GPIO_28_I_UMSK   (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS))
#define GLB_REG_GPIO_29_I        GLB_REG_GPIO_29_I
#define GLB_REG_GPIO_29_I_POS    (29U)
#define GLB_REG_GPIO_29_I_LEN    (1U)
#define GLB_REG_GPIO_29_I_MSK    (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)
#define GLB_REG_GPIO_29_I_UMSK   (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS))
#define GLB_REG_GPIO_30_I        GLB_REG_GPIO_30_I
#define GLB_REG_GPIO_30_I_POS    (30U)
#define GLB_REG_GPIO_30_I_LEN    (1U)
#define GLB_REG_GPIO_30_I_MSK    (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)
#define GLB_REG_GPIO_30_I_UMSK   (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS))
#define GLB_REG_GPIO_31_I        GLB_REG_GPIO_31_I
#define GLB_REG_GPIO_31_I_POS    (31U)
#define GLB_REG_GPIO_31_I_LEN    (1U)
#define GLB_REG_GPIO_31_I_MSK    (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)
#define GLB_REG_GPIO_31_I_UMSK   (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS))

/* 0x184 : GPIO_CFGCTL31 */
#define GLB_GPIO_CFGCTL31_OFFSET (0x184)

/* 0x188 : GPIO_CFGCTL32 */
#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
#define GLB_REG_GPIO_0_O         GLB_REG_GPIO_0_O
#define GLB_REG_GPIO_0_O_POS     (0U)
#define GLB_REG_GPIO_0_O_LEN     (1U)
#define GLB_REG_GPIO_0_O_MSK     (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
#define GLB_REG_GPIO_0_O_UMSK    (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
#define GLB_REG_GPIO_1_O         GLB_REG_GPIO_1_O
#define GLB_REG_GPIO_1_O_POS     (1U)
#define GLB_REG_GPIO_1_O_LEN     (1U)
#define GLB_REG_GPIO_1_O_MSK     (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
#define GLB_REG_GPIO_1_O_UMSK    (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
#define GLB_REG_GPIO_2_O         GLB_REG_GPIO_2_O
#define GLB_REG_GPIO_2_O_POS     (2U)
#define GLB_REG_GPIO_2_O_LEN     (1U)
#define GLB_REG_GPIO_2_O_MSK     (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
#define GLB_REG_GPIO_2_O_UMSK    (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
#define GLB_REG_GPIO_3_O         GLB_REG_GPIO_3_O
#define GLB_REG_GPIO_3_O_POS     (3U)
#define GLB_REG_GPIO_3_O_LEN     (1U)
#define GLB_REG_GPIO_3_O_MSK     (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
#define GLB_REG_GPIO_3_O_UMSK    (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
#define GLB_REG_GPIO_4_O         GLB_REG_GPIO_4_O
#define GLB_REG_GPIO_4_O_POS     (4U)
#define GLB_REG_GPIO_4_O_LEN     (1U)
#define GLB_REG_GPIO_4_O_MSK     (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
#define GLB_REG_GPIO_4_O_UMSK    (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
#define GLB_REG_GPIO_5_O         GLB_REG_GPIO_5_O
#define GLB_REG_GPIO_5_O_POS     (5U)
#define GLB_REG_GPIO_5_O_LEN     (1U)
#define GLB_REG_GPIO_5_O_MSK     (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
#define GLB_REG_GPIO_5_O_UMSK    (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
#define GLB_REG_GPIO_6_O         GLB_REG_GPIO_6_O
#define GLB_REG_GPIO_6_O_POS     (6U)
#define GLB_REG_GPIO_6_O_LEN     (1U)
#define GLB_REG_GPIO_6_O_MSK     (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
#define GLB_REG_GPIO_6_O_UMSK    (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
#define GLB_REG_GPIO_7_O         GLB_REG_GPIO_7_O
#define GLB_REG_GPIO_7_O_POS     (7U)
#define GLB_REG_GPIO_7_O_LEN     (1U)
#define GLB_REG_GPIO_7_O_MSK     (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
#define GLB_REG_GPIO_7_O_UMSK    (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
#define GLB_REG_GPIO_8_O         GLB_REG_GPIO_8_O
#define GLB_REG_GPIO_8_O_POS     (8U)
#define GLB_REG_GPIO_8_O_LEN     (1U)
#define GLB_REG_GPIO_8_O_MSK     (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
#define GLB_REG_GPIO_8_O_UMSK    (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
#define GLB_REG_GPIO_9_O         GLB_REG_GPIO_9_O
#define GLB_REG_GPIO_9_O_POS     (9U)
#define GLB_REG_GPIO_9_O_LEN     (1U)
#define GLB_REG_GPIO_9_O_MSK     (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
#define GLB_REG_GPIO_9_O_UMSK    (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
#define GLB_REG_GPIO_10_O        GLB_REG_GPIO_10_O
#define GLB_REG_GPIO_10_O_POS    (10U)
#define GLB_REG_GPIO_10_O_LEN    (1U)
#define GLB_REG_GPIO_10_O_MSK    (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
#define GLB_REG_GPIO_10_O_UMSK   (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
#define GLB_REG_GPIO_11_O        GLB_REG_GPIO_11_O
#define GLB_REG_GPIO_11_O_POS    (11U)
#define GLB_REG_GPIO_11_O_LEN    (1U)
#define GLB_REG_GPIO_11_O_MSK    (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
#define GLB_REG_GPIO_11_O_UMSK   (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
#define GLB_REG_GPIO_12_O        GLB_REG_GPIO_12_O
#define GLB_REG_GPIO_12_O_POS    (12U)
#define GLB_REG_GPIO_12_O_LEN    (1U)
#define GLB_REG_GPIO_12_O_MSK    (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
#define GLB_REG_GPIO_12_O_UMSK   (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
#define GLB_REG_GPIO_13_O        GLB_REG_GPIO_13_O
#define GLB_REG_GPIO_13_O_POS    (13U)
#define GLB_REG_GPIO_13_O_LEN    (1U)
#define GLB_REG_GPIO_13_O_MSK    (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
#define GLB_REG_GPIO_13_O_UMSK   (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
#define GLB_REG_GPIO_14_O        GLB_REG_GPIO_14_O
#define GLB_REG_GPIO_14_O_POS    (14U)
#define GLB_REG_GPIO_14_O_LEN    (1U)
#define GLB_REG_GPIO_14_O_MSK    (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
#define GLB_REG_GPIO_14_O_UMSK   (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
#define GLB_REG_GPIO_15_O        GLB_REG_GPIO_15_O
#define GLB_REG_GPIO_15_O_POS    (15U)
#define GLB_REG_GPIO_15_O_LEN    (1U)
#define GLB_REG_GPIO_15_O_MSK    (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
#define GLB_REG_GPIO_15_O_UMSK   (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
#define GLB_REG_GPIO_16_O        GLB_REG_GPIO_16_O
#define GLB_REG_GPIO_16_O_POS    (16U)
#define GLB_REG_GPIO_16_O_LEN    (1U)
#define GLB_REG_GPIO_16_O_MSK    (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
#define GLB_REG_GPIO_16_O_UMSK   (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
#define GLB_REG_GPIO_17_O        GLB_REG_GPIO_17_O
#define GLB_REG_GPIO_17_O_POS    (17U)
#define GLB_REG_GPIO_17_O_LEN    (1U)
#define GLB_REG_GPIO_17_O_MSK    (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
#define GLB_REG_GPIO_17_O_UMSK   (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
#define GLB_REG_GPIO_18_O        GLB_REG_GPIO_18_O
#define GLB_REG_GPIO_18_O_POS    (18U)
#define GLB_REG_GPIO_18_O_LEN    (1U)
#define GLB_REG_GPIO_18_O_MSK    (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
#define GLB_REG_GPIO_18_O_UMSK   (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
#define GLB_REG_GPIO_19_O        GLB_REG_GPIO_19_O
#define GLB_REG_GPIO_19_O_POS    (19U)
#define GLB_REG_GPIO_19_O_LEN    (1U)
#define GLB_REG_GPIO_19_O_MSK    (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
#define GLB_REG_GPIO_19_O_UMSK   (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
#define GLB_REG_GPIO_20_O        GLB_REG_GPIO_20_O
#define GLB_REG_GPIO_20_O_POS    (20U)
#define GLB_REG_GPIO_20_O_LEN    (1U)
#define GLB_REG_GPIO_20_O_MSK    (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
#define GLB_REG_GPIO_20_O_UMSK   (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
#define GLB_REG_GPIO_21_O        GLB_REG_GPIO_21_O
#define GLB_REG_GPIO_21_O_POS    (21U)
#define GLB_REG_GPIO_21_O_LEN    (1U)
#define GLB_REG_GPIO_21_O_MSK    (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
#define GLB_REG_GPIO_21_O_UMSK   (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
#define GLB_REG_GPIO_22_O        GLB_REG_GPIO_22_O
#define GLB_REG_GPIO_22_O_POS    (22U)
#define GLB_REG_GPIO_22_O_LEN    (1U)
#define GLB_REG_GPIO_22_O_MSK    (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
#define GLB_REG_GPIO_22_O_UMSK   (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
#define GLB_REG_GPIO_23_O        GLB_REG_GPIO_23_O
#define GLB_REG_GPIO_23_O_POS    (23U)
#define GLB_REG_GPIO_23_O_LEN    (1U)
#define GLB_REG_GPIO_23_O_MSK    (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)
#define GLB_REG_GPIO_23_O_UMSK   (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS))
#define GLB_REG_GPIO_24_O        GLB_REG_GPIO_24_O
#define GLB_REG_GPIO_24_O_POS    (24U)
#define GLB_REG_GPIO_24_O_LEN    (1U)
#define GLB_REG_GPIO_24_O_MSK    (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)
#define GLB_REG_GPIO_24_O_UMSK   (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS))
#define GLB_REG_GPIO_25_O        GLB_REG_GPIO_25_O
#define GLB_REG_GPIO_25_O_POS    (25U)
#define GLB_REG_GPIO_25_O_LEN    (1U)
#define GLB_REG_GPIO_25_O_MSK    (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)
#define GLB_REG_GPIO_25_O_UMSK   (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS))
#define GLB_REG_GPIO_26_O        GLB_REG_GPIO_26_O
#define GLB_REG_GPIO_26_O_POS    (26U)
#define GLB_REG_GPIO_26_O_LEN    (1U)
#define GLB_REG_GPIO_26_O_MSK    (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)
#define GLB_REG_GPIO_26_O_UMSK   (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS))
#define GLB_REG_GPIO_27_O        GLB_REG_GPIO_27_O
#define GLB_REG_GPIO_27_O_POS    (27U)
#define GLB_REG_GPIO_27_O_LEN    (1U)
#define GLB_REG_GPIO_27_O_MSK    (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)
#define GLB_REG_GPIO_27_O_UMSK   (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS))
#define GLB_REG_GPIO_28_O        GLB_REG_GPIO_28_O
#define GLB_REG_GPIO_28_O_POS    (28U)
#define GLB_REG_GPIO_28_O_LEN    (1U)
#define GLB_REG_GPIO_28_O_MSK    (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)
#define GLB_REG_GPIO_28_O_UMSK   (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS))
#define GLB_REG_GPIO_29_O        GLB_REG_GPIO_29_O
#define GLB_REG_GPIO_29_O_POS    (29U)
#define GLB_REG_GPIO_29_O_LEN    (1U)
#define GLB_REG_GPIO_29_O_MSK    (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)
#define GLB_REG_GPIO_29_O_UMSK   (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS))
#define GLB_REG_GPIO_30_O        GLB_REG_GPIO_30_O
#define GLB_REG_GPIO_30_O_POS    (30U)
#define GLB_REG_GPIO_30_O_LEN    (1U)
#define GLB_REG_GPIO_30_O_MSK    (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)
#define GLB_REG_GPIO_30_O_UMSK   (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS))
#define GLB_REG_GPIO_31_O        GLB_REG_GPIO_31_O
#define GLB_REG_GPIO_31_O_POS    (31U)
#define GLB_REG_GPIO_31_O_LEN    (1U)
#define GLB_REG_GPIO_31_O_MSK    (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)
#define GLB_REG_GPIO_31_O_UMSK   (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS))

/* 0x18C : GPIO_CFGCTL33 */
#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)

/* 0x190 : GPIO_CFGCTL34 */
#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
#define GLB_REG_GPIO_0_OE        GLB_REG_GPIO_0_OE
#define GLB_REG_GPIO_0_OE_POS    (0U)
#define GLB_REG_GPIO_0_OE_LEN    (1U)
#define GLB_REG_GPIO_0_OE_MSK    (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
#define GLB_REG_GPIO_0_OE_UMSK   (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
#define GLB_REG_GPIO_1_OE        GLB_REG_GPIO_1_OE
#define GLB_REG_GPIO_1_OE_POS    (1U)
#define GLB_REG_GPIO_1_OE_LEN    (1U)
#define GLB_REG_GPIO_1_OE_MSK    (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
#define GLB_REG_GPIO_1_OE_UMSK   (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
#define GLB_REG_GPIO_2_OE        GLB_REG_GPIO_2_OE
#define GLB_REG_GPIO_2_OE_POS    (2U)
#define GLB_REG_GPIO_2_OE_LEN    (1U)
#define GLB_REG_GPIO_2_OE_MSK    (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
#define GLB_REG_GPIO_2_OE_UMSK   (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
#define GLB_REG_GPIO_3_OE        GLB_REG_GPIO_3_OE
#define GLB_REG_GPIO_3_OE_POS    (3U)
#define GLB_REG_GPIO_3_OE_LEN    (1U)
#define GLB_REG_GPIO_3_OE_MSK    (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
#define GLB_REG_GPIO_3_OE_UMSK   (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
#define GLB_REG_GPIO_4_OE        GLB_REG_GPIO_4_OE
#define GLB_REG_GPIO_4_OE_POS    (4U)
#define GLB_REG_GPIO_4_OE_LEN    (1U)
#define GLB_REG_GPIO_4_OE_MSK    (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
#define GLB_REG_GPIO_4_OE_UMSK   (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
#define GLB_REG_GPIO_5_OE        GLB_REG_GPIO_5_OE
#define GLB_REG_GPIO_5_OE_POS    (5U)
#define GLB_REG_GPIO_5_OE_LEN    (1U)
#define GLB_REG_GPIO_5_OE_MSK    (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
#define GLB_REG_GPIO_5_OE_UMSK   (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
#define GLB_REG_GPIO_6_OE        GLB_REG_GPIO_6_OE
#define GLB_REG_GPIO_6_OE_POS    (6U)
#define GLB_REG_GPIO_6_OE_LEN    (1U)
#define GLB_REG_GPIO_6_OE_MSK    (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
#define GLB_REG_GPIO_6_OE_UMSK   (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
#define GLB_REG_GPIO_7_OE        GLB_REG_GPIO_7_OE
#define GLB_REG_GPIO_7_OE_POS    (7U)
#define GLB_REG_GPIO_7_OE_LEN    (1U)
#define GLB_REG_GPIO_7_OE_MSK    (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
#define GLB_REG_GPIO_7_OE_UMSK   (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
#define GLB_REG_GPIO_8_OE        GLB_REG_GPIO_8_OE
#define GLB_REG_GPIO_8_OE_POS    (8U)
#define GLB_REG_GPIO_8_OE_LEN    (1U)
#define GLB_REG_GPIO_8_OE_MSK    (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
#define GLB_REG_GPIO_8_OE_UMSK   (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
#define GLB_REG_GPIO_9_OE        GLB_REG_GPIO_9_OE
#define GLB_REG_GPIO_9_OE_POS    (9U)
#define GLB_REG_GPIO_9_OE_LEN    (1U)
#define GLB_REG_GPIO_9_OE_MSK    (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
#define GLB_REG_GPIO_9_OE_UMSK   (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
#define GLB_REG_GPIO_10_OE       GLB_REG_GPIO_10_OE
#define GLB_REG_GPIO_10_OE_POS   (10U)
#define GLB_REG_GPIO_10_OE_LEN   (1U)
#define GLB_REG_GPIO_10_OE_MSK   (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
#define GLB_REG_GPIO_10_OE_UMSK  (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
#define GLB_REG_GPIO_11_OE       GLB_REG_GPIO_11_OE
#define GLB_REG_GPIO_11_OE_POS   (11U)
#define GLB_REG_GPIO_11_OE_LEN   (1U)
#define GLB_REG_GPIO_11_OE_MSK   (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
#define GLB_REG_GPIO_11_OE_UMSK  (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
#define GLB_REG_GPIO_12_OE       GLB_REG_GPIO_12_OE
#define GLB_REG_GPIO_12_OE_POS   (12U)
#define GLB_REG_GPIO_12_OE_LEN   (1U)
#define GLB_REG_GPIO_12_OE_MSK   (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
#define GLB_REG_GPIO_12_OE_UMSK  (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
#define GLB_REG_GPIO_13_OE       GLB_REG_GPIO_13_OE
#define GLB_REG_GPIO_13_OE_POS   (13U)
#define GLB_REG_GPIO_13_OE_LEN   (1U)
#define GLB_REG_GPIO_13_OE_MSK   (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
#define GLB_REG_GPIO_13_OE_UMSK  (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
#define GLB_REG_GPIO_14_OE       GLB_REG_GPIO_14_OE
#define GLB_REG_GPIO_14_OE_POS   (14U)
#define GLB_REG_GPIO_14_OE_LEN   (1U)
#define GLB_REG_GPIO_14_OE_MSK   (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
#define GLB_REG_GPIO_14_OE_UMSK  (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
#define GLB_REG_GPIO_15_OE       GLB_REG_GPIO_15_OE
#define GLB_REG_GPIO_15_OE_POS   (15U)
#define GLB_REG_GPIO_15_OE_LEN   (1U)
#define GLB_REG_GPIO_15_OE_MSK   (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
#define GLB_REG_GPIO_15_OE_UMSK  (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
#define GLB_REG_GPIO_16_OE       GLB_REG_GPIO_16_OE
#define GLB_REG_GPIO_16_OE_POS   (16U)
#define GLB_REG_GPIO_16_OE_LEN   (1U)
#define GLB_REG_GPIO_16_OE_MSK   (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
#define GLB_REG_GPIO_16_OE_UMSK  (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
#define GLB_REG_GPIO_17_OE       GLB_REG_GPIO_17_OE
#define GLB_REG_GPIO_17_OE_POS   (17U)
#define GLB_REG_GPIO_17_OE_LEN   (1U)
#define GLB_REG_GPIO_17_OE_MSK   (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
#define GLB_REG_GPIO_17_OE_UMSK  (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
#define GLB_REG_GPIO_18_OE       GLB_REG_GPIO_18_OE
#define GLB_REG_GPIO_18_OE_POS   (18U)
#define GLB_REG_GPIO_18_OE_LEN   (1U)
#define GLB_REG_GPIO_18_OE_MSK   (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
#define GLB_REG_GPIO_18_OE_UMSK  (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
#define GLB_REG_GPIO_19_OE       GLB_REG_GPIO_19_OE
#define GLB_REG_GPIO_19_OE_POS   (19U)
#define GLB_REG_GPIO_19_OE_LEN   (1U)
#define GLB_REG_GPIO_19_OE_MSK   (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
#define GLB_REG_GPIO_19_OE_UMSK  (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
#define GLB_REG_GPIO_20_OE       GLB_REG_GPIO_20_OE
#define GLB_REG_GPIO_20_OE_POS   (20U)
#define GLB_REG_GPIO_20_OE_LEN   (1U)
#define GLB_REG_GPIO_20_OE_MSK   (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
#define GLB_REG_GPIO_20_OE_UMSK  (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
#define GLB_REG_GPIO_21_OE       GLB_REG_GPIO_21_OE
#define GLB_REG_GPIO_21_OE_POS   (21U)
#define GLB_REG_GPIO_21_OE_LEN   (1U)
#define GLB_REG_GPIO_21_OE_MSK   (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
#define GLB_REG_GPIO_21_OE_UMSK  (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
#define GLB_REG_GPIO_22_OE       GLB_REG_GPIO_22_OE
#define GLB_REG_GPIO_22_OE_POS   (22U)
#define GLB_REG_GPIO_22_OE_LEN   (1U)
#define GLB_REG_GPIO_22_OE_MSK   (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
#define GLB_REG_GPIO_22_OE_UMSK  (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
#define GLB_REG_GPIO_23_OE       GLB_REG_GPIO_23_OE
#define GLB_REG_GPIO_23_OE_POS   (23U)
#define GLB_REG_GPIO_23_OE_LEN   (1U)
#define GLB_REG_GPIO_23_OE_MSK   (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)
#define GLB_REG_GPIO_23_OE_UMSK  (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS))
#define GLB_REG_GPIO_24_OE       GLB_REG_GPIO_24_OE
#define GLB_REG_GPIO_24_OE_POS   (24U)
#define GLB_REG_GPIO_24_OE_LEN   (1U)
#define GLB_REG_GPIO_24_OE_MSK   (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)
#define GLB_REG_GPIO_24_OE_UMSK  (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS))
#define GLB_REG_GPIO_25_OE       GLB_REG_GPIO_25_OE
#define GLB_REG_GPIO_25_OE_POS   (25U)
#define GLB_REG_GPIO_25_OE_LEN   (1U)
#define GLB_REG_GPIO_25_OE_MSK   (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)
#define GLB_REG_GPIO_25_OE_UMSK  (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS))
#define GLB_REG_GPIO_26_OE       GLB_REG_GPIO_26_OE
#define GLB_REG_GPIO_26_OE_POS   (26U)
#define GLB_REG_GPIO_26_OE_LEN   (1U)
#define GLB_REG_GPIO_26_OE_MSK   (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)
#define GLB_REG_GPIO_26_OE_UMSK  (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS))
#define GLB_REG_GPIO_27_OE       GLB_REG_GPIO_27_OE
#define GLB_REG_GPIO_27_OE_POS   (27U)
#define GLB_REG_GPIO_27_OE_LEN   (1U)
#define GLB_REG_GPIO_27_OE_MSK   (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)
#define GLB_REG_GPIO_27_OE_UMSK  (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS))
#define GLB_REG_GPIO_28_OE       GLB_REG_GPIO_28_OE
#define GLB_REG_GPIO_28_OE_POS   (28U)
#define GLB_REG_GPIO_28_OE_LEN   (1U)
#define GLB_REG_GPIO_28_OE_MSK   (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)
#define GLB_REG_GPIO_28_OE_UMSK  (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS))
#define GLB_REG_GPIO_29_OE       GLB_REG_GPIO_29_OE
#define GLB_REG_GPIO_29_OE_POS   (29U)
#define GLB_REG_GPIO_29_OE_LEN   (1U)
#define GLB_REG_GPIO_29_OE_MSK   (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)
#define GLB_REG_GPIO_29_OE_UMSK  (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS))
#define GLB_REG_GPIO_30_OE       GLB_REG_GPIO_30_OE
#define GLB_REG_GPIO_30_OE_POS   (30U)
#define GLB_REG_GPIO_30_OE_LEN   (1U)
#define GLB_REG_GPIO_30_OE_MSK   (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)
#define GLB_REG_GPIO_30_OE_UMSK  (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS))
#define GLB_REG_GPIO_31_OE       GLB_REG_GPIO_31_OE
#define GLB_REG_GPIO_31_OE_POS   (31U)
#define GLB_REG_GPIO_31_OE_LEN   (1U)
#define GLB_REG_GPIO_31_OE_MSK   (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)
#define GLB_REG_GPIO_31_OE_UMSK  (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS))

/* 0x194 : GPIO_CFGCTL35 */
#define GLB_GPIO_CFGCTL35_OFFSET (0x194)

/* 0x1A0 : GPIO_INT_MASK1 */
#define GLB_GPIO_INT_MASK1_OFFSET   (0x1A0)
#define GLB_REG_GPIO_INT_MASK1      GLB_REG_GPIO_INT_MASK1
#define GLB_REG_GPIO_INT_MASK1_POS  (0U)
#define GLB_REG_GPIO_INT_MASK1_LEN  (32U)
#define GLB_REG_GPIO_INT_MASK1_MSK  (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))

/* 0x1A8 : GPIO_INT_STAT1 */
#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
#define GLB_GPIO_INT_STAT1        GLB_GPIO_INT_STAT1
#define GLB_GPIO_INT_STAT1_POS    (0U)
#define GLB_GPIO_INT_STAT1_LEN    (32U)
#define GLB_GPIO_INT_STAT1_MSK    (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
#define GLB_GPIO_INT_STAT1_UMSK   (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))

/* 0x1B0 : GPIO_INT_CLR1 */
#define GLB_GPIO_INT_CLR1_OFFSET   (0x1B0)
#define GLB_REG_GPIO_INT_CLR1      GLB_REG_GPIO_INT_CLR1
#define GLB_REG_GPIO_INT_CLR1_POS  (0U)
#define GLB_REG_GPIO_INT_CLR1_LEN  (32U)
#define GLB_REG_GPIO_INT_CLR1_MSK  (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))

/* 0x1C0 : GPIO_INT_MODE_SET1 */
#define GLB_GPIO_INT_MODE_SET1_OFFSET   (0x1C0)
#define GLB_REG_GPIO_INT_MODE_SET1      GLB_REG_GPIO_INT_MODE_SET1
#define GLB_REG_GPIO_INT_MODE_SET1_POS  (0U)
#define GLB_REG_GPIO_INT_MODE_SET1_LEN  (30U)
#define GLB_REG_GPIO_INT_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)
#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS))

/* 0x1C4 : GPIO_INT_MODE_SET2 */
#define GLB_GPIO_INT_MODE_SET2_OFFSET   (0x1C4)
#define GLB_REG_GPIO_INT_MODE_SET2      GLB_REG_GPIO_INT_MODE_SET2
#define GLB_REG_GPIO_INT_MODE_SET2_POS  (0U)
#define GLB_REG_GPIO_INT_MODE_SET2_LEN  (30U)
#define GLB_REG_GPIO_INT_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)
#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS))

/* 0x1C8 : GPIO_INT_MODE_SET3 */
#define GLB_GPIO_INT_MODE_SET3_OFFSET   (0x1C8)
#define GLB_REG_GPIO_INT_MODE_SET3      GLB_REG_GPIO_INT_MODE_SET3
#define GLB_REG_GPIO_INT_MODE_SET3_POS  (0U)
#define GLB_REG_GPIO_INT_MODE_SET3_LEN  (30U)
#define GLB_REG_GPIO_INT_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)
#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS))

/* 0x1CC : GPIO_INT_MODE_SET4 */
#define GLB_GPIO_INT_MODE_SET4_OFFSET   (0x1CC)
#define GLB_REG_GPIO_INT_MODE_SET4      GLB_REG_GPIO_INT_MODE_SET4
#define GLB_REG_GPIO_INT_MODE_SET4_POS  (0U)
#define GLB_REG_GPIO_INT_MODE_SET4_LEN  (6U)
#define GLB_REG_GPIO_INT_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS)
#define GLB_REG_GPIO_INT_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS))

/* 0x1D0 : GPIO_INT2_MASK1 */
#define GLB_GPIO_INT2_MASK1_OFFSET   (0x1D0)
#define GLB_REG_GPIO_INT2_MASK1      GLB_REG_GPIO_INT2_MASK1
#define GLB_REG_GPIO_INT2_MASK1_POS  (0U)
#define GLB_REG_GPIO_INT2_MASK1_LEN  (32U)
#define GLB_REG_GPIO_INT2_MASK1_MSK  (((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS)
#define GLB_REG_GPIO_INT2_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS))

/* 0x1D4 : GPIO_INT2_STAT1 */
#define GLB_GPIO_INT2_STAT1_OFFSET (0x1D4)
#define GLB_GPIO_INT2_STAT1        GLB_GPIO_INT2_STAT1
#define GLB_GPIO_INT2_STAT1_POS    (0U)
#define GLB_GPIO_INT2_STAT1_LEN    (32U)
#define GLB_GPIO_INT2_STAT1_MSK    (((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS)
#define GLB_GPIO_INT2_STAT1_UMSK   (~(((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS))

/* 0x1D8 : GPIO_INT2_CLR1 */
#define GLB_GPIO_INT2_CLR1_OFFSET   (0x1D8)
#define GLB_REG_GPIO_INT2_CLR1      GLB_REG_GPIO_INT2_CLR1
#define GLB_REG_GPIO_INT2_CLR1_POS  (0U)
#define GLB_REG_GPIO_INT2_CLR1_LEN  (32U)
#define GLB_REG_GPIO_INT2_CLR1_MSK  (((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS)
#define GLB_REG_GPIO_INT2_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS))

/* 0x1DC : GPIO_INT2_MODE_SET1 */
#define GLB_GPIO_INT2_MODE_SET1_OFFSET   (0x1DC)
#define GLB_REG_GPIO_INT2_MODE_SET1      GLB_REG_GPIO_INT2_MODE_SET1
#define GLB_REG_GPIO_INT2_MODE_SET1_POS  (0U)
#define GLB_REG_GPIO_INT2_MODE_SET1_LEN  (30U)
#define GLB_REG_GPIO_INT2_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS)
#define GLB_REG_GPIO_INT2_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS))

/* 0x1E0 : GPIO_INT2_MODE_SET2 */
#define GLB_GPIO_INT2_MODE_SET2_OFFSET   (0x1E0)
#define GLB_REG_GPIO_INT2_MODE_SET2      GLB_REG_GPIO_INT2_MODE_SET2
#define GLB_REG_GPIO_INT2_MODE_SET2_POS  (0U)
#define GLB_REG_GPIO_INT2_MODE_SET2_LEN  (30U)
#define GLB_REG_GPIO_INT2_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS)
#define GLB_REG_GPIO_INT2_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS))

/* 0x1E4 : GPIO_INT2_MODE_SET3 */
#define GLB_GPIO_INT2_MODE_SET3_OFFSET   (0x1E4)
#define GLB_REG_GPIO_INT2_MODE_SET3      GLB_REG_GPIO_INT2_MODE_SET3
#define GLB_REG_GPIO_INT2_MODE_SET3_POS  (0U)
#define GLB_REG_GPIO_INT2_MODE_SET3_LEN  (30U)
#define GLB_REG_GPIO_INT2_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS)
#define GLB_REG_GPIO_INT2_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS))

/* 0x1E8 : GPIO_INT2_MODE_SET4 */
#define GLB_GPIO_INT2_MODE_SET4_OFFSET   (0x1E8)
#define GLB_REG_GPIO_INT2_MODE_SET4      GLB_REG_GPIO_INT2_MODE_SET4
#define GLB_REG_GPIO_INT2_MODE_SET4_POS  (0U)
#define GLB_REG_GPIO_INT2_MODE_SET4_LEN  (6U)
#define GLB_REG_GPIO_INT2_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS)
#define GLB_REG_GPIO_INT2_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS))

/* 0x200 : dll */
#define GLB_DLL_OFFSET               (0x200)
#define GLB_DTEST_EN_DLL_REFCLK      GLB_DTEST_EN_DLL_REFCLK
#define GLB_DTEST_EN_DLL_REFCLK_POS  (0U)
#define GLB_DTEST_EN_DLL_REFCLK_LEN  (1U)
#define GLB_DTEST_EN_DLL_REFCLK_MSK  (((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS)
#define GLB_DTEST_EN_DLL_REFCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS))
#define GLB_DTEST_EN_DLL_OUTCLK      GLB_DTEST_EN_DLL_OUTCLK
#define GLB_DTEST_EN_DLL_OUTCLK_POS  (1U)
#define GLB_DTEST_EN_DLL_OUTCLK_LEN  (1U)
#define GLB_DTEST_EN_DLL_OUTCLK_MSK  (((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS)
#define GLB_DTEST_EN_DLL_OUTCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS))
#define GLB_TEN_DLL                  GLB_TEN_DLL
#define GLB_TEN_DLL_POS              (2U)
#define GLB_TEN_DLL_LEN              (1U)
#define GLB_TEN_DLL_MSK              (((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS)
#define GLB_TEN_DLL_UMSK             (~(((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS))
#define GLB_DLL_CLK_MMDIV_EN         GLB_DLL_CLK_MMDIV_EN
#define GLB_DLL_CLK_MMDIV_EN_POS     (3U)
#define GLB_DLL_CLK_MMDIV_EN_LEN     (1U)
#define GLB_DLL_CLK_MMDIV_EN_MSK     (((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS)
#define GLB_DLL_CLK_MMDIV_EN_UMSK    (~(((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS))
#define GLB_DLL_CLK_288M_EN          GLB_DLL_CLK_288M_EN
#define GLB_DLL_CLK_288M_EN_POS      (4U)
#define GLB_DLL_CLK_288M_EN_LEN      (1U)
#define GLB_DLL_CLK_288M_EN_MSK      (((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS)
#define GLB_DLL_CLK_288M_EN_UMSK     (~(((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS))
#define GLB_DLL_CLK_144M_EN          GLB_DLL_CLK_144M_EN
#define GLB_DLL_CLK_144M_EN_POS      (5U)
#define GLB_DLL_CLK_144M_EN_LEN      (1U)
#define GLB_DLL_CLK_144M_EN_MSK      (((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS)
#define GLB_DLL_CLK_144M_EN_UMSK     (~(((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS))
#define GLB_DLL_CLK_96M_EN           GLB_DLL_CLK_96M_EN
#define GLB_DLL_CLK_96M_EN_POS       (6U)
#define GLB_DLL_CLK_96M_EN_LEN       (1U)
#define GLB_DLL_CLK_96M_EN_MSK       (((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS)
#define GLB_DLL_CLK_96M_EN_UMSK      (~(((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS))
#define GLB_DLL_CLK_57P6M_EN         GLB_DLL_CLK_57P6M_EN
#define GLB_DLL_CLK_57P6M_EN_POS     (7U)
#define GLB_DLL_CLK_57P6M_EN_LEN     (1U)
#define GLB_DLL_CLK_57P6M_EN_MSK     (((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS)
#define GLB_DLL_CLK_57P6M_EN_UMSK    (~(((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS))
#define GLB_DLL_VCTRL_SEL            GLB_DLL_VCTRL_SEL
#define GLB_DLL_VCTRL_SEL_POS        (8U)
#define GLB_DLL_VCTRL_SEL_LEN        (3U)
#define GLB_DLL_VCTRL_SEL_MSK        (((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS)
#define GLB_DLL_VCTRL_SEL_UMSK       (~(((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS))
#define GLB_DLL_PRECHG_SEL           GLB_DLL_PRECHG_SEL
#define GLB_DLL_PRECHG_SEL_POS       (12U)
#define GLB_DLL_PRECHG_SEL_LEN       (1U)
#define GLB_DLL_PRECHG_SEL_MSK       (((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS)
#define GLB_DLL_PRECHG_SEL_UMSK      (~(((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS))
#define GLB_DLL_PRECHG_REG           GLB_DLL_PRECHG_REG
#define GLB_DLL_PRECHG_REG_POS       (13U)
#define GLB_DLL_PRECHG_REG_LEN       (1U)
#define GLB_DLL_PRECHG_REG_MSK       (((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS)
#define GLB_DLL_PRECHG_REG_UMSK      (~(((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS))
#define GLB_DLL_PRECHG_EN            GLB_DLL_PRECHG_EN
#define GLB_DLL_PRECHG_EN_POS        (14U)
#define GLB_DLL_PRECHG_EN_LEN        (1U)
#define GLB_DLL_PRECHG_EN_MSK        (((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS)
#define GLB_DLL_PRECHG_EN_UMSK       (~(((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS))
#define GLB_DLL_VCTRL_FORCE_EN       GLB_DLL_VCTRL_FORCE_EN
#define GLB_DLL_VCTRL_FORCE_EN_POS   (15U)
#define GLB_DLL_VCTRL_FORCE_EN_LEN   (1U)
#define GLB_DLL_VCTRL_FORCE_EN_MSK   (((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS)
#define GLB_DLL_VCTRL_FORCE_EN_UMSK  (~(((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS))
#define GLB_DLL_POST_DIV             GLB_DLL_POST_DIV
#define GLB_DLL_POST_DIV_POS         (16U)
#define GLB_DLL_POST_DIV_LEN         (4U)
#define GLB_DLL_POST_DIV_MSK         (((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS)
#define GLB_DLL_POST_DIV_UMSK        (~(((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS))
#define GLB_DLL_DELAY_SEL            GLB_DLL_DELAY_SEL
#define GLB_DLL_DELAY_SEL_POS        (20U)
#define GLB_DLL_DELAY_SEL_LEN        (2U)
#define GLB_DLL_DELAY_SEL_MSK        (((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS)
#define GLB_DLL_DELAY_SEL_UMSK       (~(((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS))
#define GLB_DLL_CP_OP_EN             GLB_DLL_CP_OP_EN
#define GLB_DLL_CP_OP_EN_POS         (22U)
#define GLB_DLL_CP_OP_EN_LEN         (1U)
#define GLB_DLL_CP_OP_EN_MSK         (((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS)
#define GLB_DLL_CP_OP_EN_UMSK        (~(((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS))
#define GLB_DLL_CP_HIZ               GLB_DLL_CP_HIZ
#define GLB_DLL_CP_HIZ_POS           (23U)
#define GLB_DLL_CP_HIZ_LEN           (1U)
#define GLB_DLL_CP_HIZ_MSK           (((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS)
#define GLB_DLL_CP_HIZ_UMSK          (~(((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS))
#define GLB_DLL_REFCLK_SEL           GLB_DLL_REFCLK_SEL
#define GLB_DLL_REFCLK_SEL_POS       (28U)
#define GLB_DLL_REFCLK_SEL_LEN       (1U)
#define GLB_DLL_REFCLK_SEL_MSK       (((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS)
#define GLB_DLL_REFCLK_SEL_UMSK      (~(((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS))
#define GLB_DLL_RESET                GLB_DLL_RESET
#define GLB_DLL_RESET_POS            (29U)
#define GLB_DLL_RESET_LEN            (1U)
#define GLB_DLL_RESET_MSK            (((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS)
#define GLB_DLL_RESET_UMSK           (~(((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS))
#define GLB_PU_DLL                   GLB_PU_DLL
#define GLB_PU_DLL_POS               (30U)
#define GLB_PU_DLL_LEN               (1U)
#define GLB_PU_DLL_MSK               (((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS)
#define GLB_PU_DLL_UMSK              (~(((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS))
#define GLB_PPU_DLL                  GLB_PPU_DLL
#define GLB_PPU_DLL_POS              (31U)
#define GLB_PPU_DLL_LEN              (1U)
#define GLB_PPU_DLL_MSK              (((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS)
#define GLB_PPU_DLL_UMSK             (~(((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS))

/* 0x224 : led_driver */
#define GLB_LED_DRIVER_OFFSET         (0x224)
#define GLB_LED_DIN_REG               GLB_LED_DIN_REG
#define GLB_LED_DIN_REG_POS           (0U)
#define GLB_LED_DIN_REG_LEN           (1U)
#define GLB_LED_DIN_REG_MSK           (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
#define GLB_LED_DIN_REG_UMSK          (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
#define GLB_LED_DIN_SEL               GLB_LED_DIN_SEL
#define GLB_LED_DIN_SEL_POS           (1U)
#define GLB_LED_DIN_SEL_LEN           (1U)
#define GLB_LED_DIN_SEL_MSK           (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
#define GLB_LED_DIN_SEL_UMSK          (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
#define GLB_LED_DIN_POLARITY_SEL      GLB_LED_DIN_POLARITY_SEL
#define GLB_LED_DIN_POLARITY_SEL_POS  (2U)
#define GLB_LED_DIN_POLARITY_SEL_LEN  (1U)
#define GLB_LED_DIN_POLARITY_SEL_MSK  (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS))
#define GLB_LEDDRV_IBIAS              GLB_LEDDRV_IBIAS
#define GLB_LEDDRV_IBIAS_POS          (4U)
#define GLB_LEDDRV_IBIAS_LEN          (4U)
#define GLB_LEDDRV_IBIAS_MSK          (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
#define GLB_LEDDRV_IBIAS_UMSK         (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
#define GLB_IR_RX_GPIO_SEL            GLB_IR_RX_GPIO_SEL
#define GLB_IR_RX_GPIO_SEL_POS        (8U)
#define GLB_IR_RX_GPIO_SEL_LEN        (4U)
#define GLB_IR_RX_GPIO_SEL_MSK        (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
#define GLB_IR_RX_GPIO_SEL_UMSK       (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
#define GLB_LEDDRV_OUT_EN             GLB_LEDDRV_OUT_EN
#define GLB_LEDDRV_OUT_EN_POS         (28U)
#define GLB_LEDDRV_OUT_EN_LEN         (2U)
#define GLB_LEDDRV_OUT_EN_MSK         (((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS)
#define GLB_LEDDRV_OUT_EN_UMSK        (~(((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS))
#define GLB_PU_LEDDRV                 GLB_PU_LEDDRV
#define GLB_PU_LEDDRV_POS             (31U)
#define GLB_PU_LEDDRV_LEN             (1U)
#define GLB_PU_LEDDRV_MSK             (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
#define GLB_PU_LEDDRV_UMSK            (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))

/* 0x228 : usb_xcvr */
#define GLB_USB_XCVR_OFFSET       (0x228)
#define GLB_USB_LDO_VFB           GLB_USB_LDO_VFB
#define GLB_USB_LDO_VFB_POS       (0U)
#define GLB_USB_LDO_VFB_LEN       (3U)
#define GLB_USB_LDO_VFB_MSK       (((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS)
#define GLB_USB_LDO_VFB_UMSK      (~(((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS))
#define GLB_PU_USB_LDO            GLB_PU_USB_LDO
#define GLB_PU_USB_LDO_POS        (3U)
#define GLB_PU_USB_LDO_LEN        (1U)
#define GLB_PU_USB_LDO_MSK        (((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS)
#define GLB_PU_USB_LDO_UMSK       (~(((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS))
#define GLB_USB_ROUT_NMOS         GLB_USB_ROUT_NMOS
#define GLB_USB_ROUT_NMOS_POS     (4U)
#define GLB_USB_ROUT_NMOS_LEN     (3U)
#define GLB_USB_ROUT_NMOS_MSK     (((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS)
#define GLB_USB_ROUT_NMOS_UMSK    (~(((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS))
#define GLB_USB_ROUT_PMOS         GLB_USB_ROUT_PMOS
#define GLB_USB_ROUT_PMOS_POS     (8U)
#define GLB_USB_ROUT_PMOS_LEN     (3U)
#define GLB_USB_ROUT_PMOS_MSK     (((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS)
#define GLB_USB_ROUT_PMOS_UMSK    (~(((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS))
#define GLB_USB_OEB_SEL           GLB_USB_OEB_SEL
#define GLB_USB_OEB_SEL_POS       (12U)
#define GLB_USB_OEB_SEL_LEN       (1U)
#define GLB_USB_OEB_SEL_MSK       (((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS)
#define GLB_USB_OEB_SEL_UMSK      (~(((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS))
#define GLB_USB_OEB_REG           GLB_USB_OEB_REG
#define GLB_USB_OEB_REG_POS       (13U)
#define GLB_USB_OEB_REG_LEN       (1U)
#define GLB_USB_OEB_REG_MSK       (((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS)
#define GLB_USB_OEB_REG_UMSK      (~(((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS))
#define GLB_USB_OEB               GLB_USB_OEB
#define GLB_USB_OEB_POS           (14U)
#define GLB_USB_OEB_LEN           (1U)
#define GLB_USB_OEB_MSK           (((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS)
#define GLB_USB_OEB_UMSK          (~(((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS))
#define GLB_USB_DATA_CONVERT      GLB_USB_DATA_CONVERT
#define GLB_USB_DATA_CONVERT_POS  (16U)
#define GLB_USB_DATA_CONVERT_LEN  (1U)
#define GLB_USB_DATA_CONVERT_MSK  (((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS)
#define GLB_USB_DATA_CONVERT_UMSK (~(((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS))
#define GLB_USB_ENUM              GLB_USB_ENUM
#define GLB_USB_ENUM_POS          (20U)
#define GLB_USB_ENUM_LEN          (1U)
#define GLB_USB_ENUM_MSK          (((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS)
#define GLB_USB_ENUM_UMSK         (~(((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS))
#define GLB_USB_SPD               GLB_USB_SPD
#define GLB_USB_SPD_POS           (21U)
#define GLB_USB_SPD_LEN           (1U)
#define GLB_USB_SPD_MSK           (((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS)
#define GLB_USB_SPD_UMSK          (~(((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS))
#define GLB_USB_SUS               GLB_USB_SUS
#define GLB_USB_SUS_POS           (22U)
#define GLB_USB_SUS_LEN           (1U)
#define GLB_USB_SUS_MSK           (((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS)
#define GLB_USB_SUS_UMSK          (~(((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS))
#define GLB_PU_USB                GLB_PU_USB
#define GLB_PU_USB_POS            (23U)
#define GLB_PU_USB_LEN            (1U)
#define GLB_PU_USB_MSK            (((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS)
#define GLB_PU_USB_UMSK           (~(((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS))
#define GLB_USB_BD                GLB_USB_BD
#define GLB_USB_BD_POS            (24U)
#define GLB_USB_BD_LEN            (1U)
#define GLB_USB_BD_MSK            (((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS)
#define GLB_USB_BD_UMSK           (~(((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS))
#define GLB_USB_VIM               GLB_USB_VIM
#define GLB_USB_VIM_POS           (25U)
#define GLB_USB_VIM_LEN           (1U)
#define GLB_USB_VIM_MSK           (((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS)
#define GLB_USB_VIM_UMSK          (~(((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS))
#define GLB_USB_VIP               GLB_USB_VIP
#define GLB_USB_VIP_POS           (26U)
#define GLB_USB_VIP_LEN           (1U)
#define GLB_USB_VIP_MSK           (((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS)
#define GLB_USB_VIP_UMSK          (~(((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS))
#define GLB_USB_RCV               GLB_USB_RCV
#define GLB_USB_RCV_POS           (27U)
#define GLB_USB_RCV_LEN           (1U)
#define GLB_USB_RCV_MSK           (((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS)
#define GLB_USB_RCV_UMSK          (~(((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS))

/* 0x22C : usb_xcvr_config */
#define GLB_USB_XCVR_CONFIG_OFFSET   (0x22C)
#define GLB_USB_V_HYS_M              GLB_USB_V_HYS_M
#define GLB_USB_V_HYS_M_POS          (0U)
#define GLB_USB_V_HYS_M_LEN          (2U)
#define GLB_USB_V_HYS_M_MSK          (((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS)
#define GLB_USB_V_HYS_M_UMSK         (~(((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS))
#define GLB_USB_V_HYS_P              GLB_USB_V_HYS_P
#define GLB_USB_V_HYS_P_POS          (2U)
#define GLB_USB_V_HYS_P_LEN          (2U)
#define GLB_USB_V_HYS_P_MSK          (((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS)
#define GLB_USB_V_HYS_P_UMSK         (~(((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS))
#define GLB_USB_BD_VTH               GLB_USB_BD_VTH
#define GLB_USB_BD_VTH_POS           (4U)
#define GLB_USB_BD_VTH_LEN           (3U)
#define GLB_USB_BD_VTH_MSK           (((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS)
#define GLB_USB_BD_VTH_UMSK          (~(((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS))
#define GLB_REG_USB_USE_XCVR         GLB_REG_USB_USE_XCVR
#define GLB_REG_USB_USE_XCVR_POS     (7U)
#define GLB_REG_USB_USE_XCVR_LEN     (1U)
#define GLB_REG_USB_USE_XCVR_MSK     (((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS)
#define GLB_REG_USB_USE_XCVR_UMSK    (~(((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS))
#define GLB_USB_STR_DRV              GLB_USB_STR_DRV
#define GLB_USB_STR_DRV_POS          (8U)
#define GLB_USB_STR_DRV_LEN          (3U)
#define GLB_USB_STR_DRV_MSK          (((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS)
#define GLB_USB_STR_DRV_UMSK         (~(((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS))
#define GLB_REG_USB_USE_CTRL         GLB_REG_USB_USE_CTRL
#define GLB_REG_USB_USE_CTRL_POS     (11U)
#define GLB_REG_USB_USE_CTRL_LEN     (1U)
#define GLB_REG_USB_USE_CTRL_MSK     (((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS)
#define GLB_REG_USB_USE_CTRL_UMSK    (~(((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS))
#define GLB_USB_RES_PULLUP_TUNE      GLB_USB_RES_PULLUP_TUNE
#define GLB_USB_RES_PULLUP_TUNE_POS  (12U)
#define GLB_USB_RES_PULLUP_TUNE_LEN  (3U)
#define GLB_USB_RES_PULLUP_TUNE_MSK  (((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS)
#define GLB_USB_RES_PULLUP_TUNE_UMSK (~(((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS))
#define GLB_USB_SLEWRATE_M_FALL      GLB_USB_SLEWRATE_M_FALL
#define GLB_USB_SLEWRATE_M_FALL_POS  (16U)
#define GLB_USB_SLEWRATE_M_FALL_LEN  (3U)
#define GLB_USB_SLEWRATE_M_FALL_MSK  (((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS)
#define GLB_USB_SLEWRATE_M_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS))
#define GLB_USB_SLEWRATE_M_RISE      GLB_USB_SLEWRATE_M_RISE
#define GLB_USB_SLEWRATE_M_RISE_POS  (20U)
#define GLB_USB_SLEWRATE_M_RISE_LEN  (3U)
#define GLB_USB_SLEWRATE_M_RISE_MSK  (((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS)
#define GLB_USB_SLEWRATE_M_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS))
#define GLB_USB_SLEWRATE_P_FALL      GLB_USB_SLEWRATE_P_FALL
#define GLB_USB_SLEWRATE_P_FALL_POS  (24U)
#define GLB_USB_SLEWRATE_P_FALL_LEN  (3U)
#define GLB_USB_SLEWRATE_P_FALL_MSK  (((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS)
#define GLB_USB_SLEWRATE_P_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS))
#define GLB_USB_SLEWRATE_P_RISE      GLB_USB_SLEWRATE_P_RISE
#define GLB_USB_SLEWRATE_P_RISE_POS  (28U)
#define GLB_USB_SLEWRATE_P_RISE_LEN  (3U)
#define GLB_USB_SLEWRATE_P_RISE_MSK  (((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS)
#define GLB_USB_SLEWRATE_P_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS))

/* 0x308 : gpdac_ctrl */
#define GLB_GPDAC_CTRL_OFFSET    (0x308)
#define GLB_GPDACA_RSTN_ANA      GLB_GPDACA_RSTN_ANA
#define GLB_GPDACA_RSTN_ANA_POS  (0U)
#define GLB_GPDACA_RSTN_ANA_LEN  (1U)
#define GLB_GPDACA_RSTN_ANA_MSK  (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
#define GLB_GPDACB_RSTN_ANA      GLB_GPDACB_RSTN_ANA
#define GLB_GPDACB_RSTN_ANA_POS  (1U)
#define GLB_GPDACB_RSTN_ANA_LEN  (1U)
#define GLB_GPDACB_RSTN_ANA_MSK  (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
#define GLB_GPDAC_TEST_EN        GLB_GPDAC_TEST_EN
#define GLB_GPDAC_TEST_EN_POS    (7U)
#define GLB_GPDAC_TEST_EN_LEN    (1U)
#define GLB_GPDAC_TEST_EN_MSK    (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
#define GLB_GPDAC_TEST_EN_UMSK   (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
#define GLB_GPDAC_REF_SEL        GLB_GPDAC_REF_SEL
#define GLB_GPDAC_REF_SEL_POS    (8U)
#define GLB_GPDAC_REF_SEL_LEN    (1U)
#define GLB_GPDAC_REF_SEL_MSK    (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
#define GLB_GPDAC_REF_SEL_UMSK   (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
#define GLB_GPDAC_TEST_SEL       GLB_GPDAC_TEST_SEL
#define GLB_GPDAC_TEST_SEL_POS   (9U)
#define GLB_GPDAC_TEST_SEL_LEN   (3U)
#define GLB_GPDAC_TEST_SEL_MSK   (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
#define GLB_GPDAC_TEST_SEL_UMSK  (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
#define GLB_GPDAC_RESERVED       GLB_GPDAC_RESERVED
#define GLB_GPDAC_RESERVED_POS   (24U)
#define GLB_GPDAC_RESERVED_LEN   (8U)
#define GLB_GPDAC_RESERVED_MSK   (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
#define GLB_GPDAC_RESERVED_UMSK  (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))

/* 0x30C : gpdac_actrl */
#define GLB_GPDAC_ACTRL_OFFSET  (0x30C)
#define GLB_GPDAC_A_EN          GLB_GPDAC_A_EN
#define GLB_GPDAC_A_EN_POS      (0U)
#define GLB_GPDAC_A_EN_LEN      (1U)
#define GLB_GPDAC_A_EN_MSK      (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
#define GLB_GPDAC_A_EN_UMSK     (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
#define GLB_GPDAC_IOA_EN        GLB_GPDAC_IOA_EN
#define GLB_GPDAC_IOA_EN_POS    (1U)
#define GLB_GPDAC_IOA_EN_LEN    (1U)
#define GLB_GPDAC_IOA_EN_MSK    (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
#define GLB_GPDAC_IOA_EN_UMSK   (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
#define GLB_GPDAC_A_RNG         GLB_GPDAC_A_RNG
#define GLB_GPDAC_A_RNG_POS     (18U)
#define GLB_GPDAC_A_RNG_LEN     (2U)
#define GLB_GPDAC_A_RNG_MSK     (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
#define GLB_GPDAC_A_RNG_UMSK    (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
#define GLB_GPDAC_A_OUTMUX      GLB_GPDAC_A_OUTMUX
#define GLB_GPDAC_A_OUTMUX_POS  (20U)
#define GLB_GPDAC_A_OUTMUX_LEN  (3U)
#define GLB_GPDAC_A_OUTMUX_MSK  (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))

/* 0x310 : gpdac_bctrl */
#define GLB_GPDAC_BCTRL_OFFSET  (0x310)
#define GLB_GPDAC_B_EN          GLB_GPDAC_B_EN
#define GLB_GPDAC_B_EN_POS      (0U)
#define GLB_GPDAC_B_EN_LEN      (1U)
#define GLB_GPDAC_B_EN_MSK      (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
#define GLB_GPDAC_B_EN_UMSK     (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
#define GLB_GPDAC_IOB_EN        GLB_GPDAC_IOB_EN
#define GLB_GPDAC_IOB_EN_POS    (1U)
#define GLB_GPDAC_IOB_EN_LEN    (1U)
#define GLB_GPDAC_IOB_EN_MSK    (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
#define GLB_GPDAC_IOB_EN_UMSK   (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
#define GLB_GPDAC_B_RNG         GLB_GPDAC_B_RNG
#define GLB_GPDAC_B_RNG_POS     (18U)
#define GLB_GPDAC_B_RNG_LEN     (2U)
#define GLB_GPDAC_B_RNG_MSK     (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
#define GLB_GPDAC_B_RNG_UMSK    (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
#define GLB_GPDAC_B_OUTMUX      GLB_GPDAC_B_OUTMUX
#define GLB_GPDAC_B_OUTMUX_POS  (20U)
#define GLB_GPDAC_B_OUTMUX_LEN  (3U)
#define GLB_GPDAC_B_OUTMUX_MSK  (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))

/* 0x314 : gpdac_data */
#define GLB_GPDAC_DATA_OFFSET (0x314)
#define GLB_GPDAC_B_DATA      GLB_GPDAC_B_DATA
#define GLB_GPDAC_B_DATA_POS  (0U)
#define GLB_GPDAC_B_DATA_LEN  (10U)
#define GLB_GPDAC_B_DATA_MSK  (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
#define GLB_GPDAC_A_DATA      GLB_GPDAC_A_DATA
#define GLB_GPDAC_A_DATA_POS  (16U)
#define GLB_GPDAC_A_DATA_LEN  (10U)
#define GLB_GPDAC_A_DATA_MSK  (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))

/* 0xE00 : chip_revision */
#define GLB_CHIP_REVISION_OFFSET (0xE00)
#define GLB_CHIP_REV             GLB_CHIP_REV
#define GLB_CHIP_REV_POS         (0U)
#define GLB_CHIP_REV_LEN         (4U)
#define GLB_CHIP_REV_MSK         (((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS)
#define GLB_CHIP_REV_UMSK        (~(((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS))

/* 0xF00 : tzc_glb_ctrl_0 */
#define GLB_TZC_GLB_CTRL_0_OFFSET             (0xF00)
#define GLB_TZC_GLB_SWRST_S00_LOCK            GLB_TZC_GLB_SWRST_S00_LOCK
#define GLB_TZC_GLB_SWRST_S00_LOCK_POS        (0U)
#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN        (1U)
#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S01_LOCK            GLB_TZC_GLB_SWRST_S01_LOCK
#define GLB_TZC_GLB_SWRST_S01_LOCK_POS        (1U)
#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN        (1U)
#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S30_LOCK            GLB_TZC_GLB_SWRST_S30_LOCK
#define GLB_TZC_GLB_SWRST_S30_LOCK_POS        (8U)
#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN        (1U)
#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK       GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS   (12U)
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN   (1U)
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK       GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS   (13U)
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN   (1U)
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK       GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS   (14U)
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN   (1U)
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK      GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS  (15U)
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN  (1U)
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK  (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
#define GLB_TZC_GLB_MISC_LOCK                 GLB_TZC_GLB_MISC_LOCK
#define GLB_TZC_GLB_MISC_LOCK_POS             (25U)
#define GLB_TZC_GLB_MISC_LOCK_LEN             (1U)
#define GLB_TZC_GLB_MISC_LOCK_MSK             (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
#define GLB_TZC_GLB_MISC_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
#define GLB_TZC_GLB_SRAM_LOCK                 GLB_TZC_GLB_SRAM_LOCK
#define GLB_TZC_GLB_SRAM_LOCK_POS             (26U)
#define GLB_TZC_GLB_SRAM_LOCK_LEN             (1U)
#define GLB_TZC_GLB_SRAM_LOCK_MSK             (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
#define GLB_TZC_GLB_SRAM_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
#define GLB_TZC_GLB_L2C_LOCK                  GLB_TZC_GLB_L2C_LOCK
#define GLB_TZC_GLB_L2C_LOCK_POS              (27U)
#define GLB_TZC_GLB_L2C_LOCK_LEN              (1U)
#define GLB_TZC_GLB_L2C_LOCK_MSK              (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
#define GLB_TZC_GLB_L2C_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
#define GLB_TZC_GLB_BMX_LOCK                  GLB_TZC_GLB_BMX_LOCK
#define GLB_TZC_GLB_BMX_LOCK_POS              (28U)
#define GLB_TZC_GLB_BMX_LOCK_LEN              (1U)
#define GLB_TZC_GLB_BMX_LOCK_MSK              (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
#define GLB_TZC_GLB_BMX_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
#define GLB_TZC_GLB_DBG_LOCK                  GLB_TZC_GLB_DBG_LOCK
#define GLB_TZC_GLB_DBG_LOCK_POS              (29U)
#define GLB_TZC_GLB_DBG_LOCK_LEN              (1U)
#define GLB_TZC_GLB_DBG_LOCK_MSK              (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
#define GLB_TZC_GLB_DBG_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
#define GLB_TZC_GLB_MBIST_LOCK                GLB_TZC_GLB_MBIST_LOCK
#define GLB_TZC_GLB_MBIST_LOCK_POS            (30U)
#define GLB_TZC_GLB_MBIST_LOCK_LEN            (1U)
#define GLB_TZC_GLB_MBIST_LOCK_MSK            (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
#define GLB_TZC_GLB_MBIST_LOCK_UMSK           (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
#define GLB_TZC_GLB_CLK_LOCK                  GLB_TZC_GLB_CLK_LOCK
#define GLB_TZC_GLB_CLK_LOCK_POS              (31U)
#define GLB_TZC_GLB_CLK_LOCK_LEN              (1U)
#define GLB_TZC_GLB_CLK_LOCK_MSK              (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
#define GLB_TZC_GLB_CLK_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))

/* 0xF04 : tzc_glb_ctrl_1 */
#define GLB_TZC_GLB_CTRL_1_OFFSET       (0xF04)
#define GLB_TZC_GLB_SWRST_S20_LOCK      GLB_TZC_GLB_SWRST_S20_LOCK
#define GLB_TZC_GLB_SWRST_S20_LOCK_POS  (0U)
#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S21_LOCK      GLB_TZC_GLB_SWRST_S21_LOCK
#define GLB_TZC_GLB_SWRST_S21_LOCK_POS  (1U)
#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S22_LOCK      GLB_TZC_GLB_SWRST_S22_LOCK
#define GLB_TZC_GLB_SWRST_S22_LOCK_POS  (2U)
#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S23_LOCK      GLB_TZC_GLB_SWRST_S23_LOCK
#define GLB_TZC_GLB_SWRST_S23_LOCK_POS  (3U)
#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S24_LOCK      GLB_TZC_GLB_SWRST_S24_LOCK
#define GLB_TZC_GLB_SWRST_S24_LOCK_POS  (4U)
#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S25_LOCK      GLB_TZC_GLB_SWRST_S25_LOCK
#define GLB_TZC_GLB_SWRST_S25_LOCK_POS  (5U)
#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S26_LOCK      GLB_TZC_GLB_SWRST_S26_LOCK
#define GLB_TZC_GLB_SWRST_S26_LOCK_POS  (6U)
#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S27_LOCK      GLB_TZC_GLB_SWRST_S27_LOCK
#define GLB_TZC_GLB_SWRST_S27_LOCK_POS  (7U)
#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S28_LOCK      GLB_TZC_GLB_SWRST_S28_LOCK
#define GLB_TZC_GLB_SWRST_S28_LOCK_POS  (8U)
#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S29_LOCK      GLB_TZC_GLB_SWRST_S29_LOCK
#define GLB_TZC_GLB_SWRST_S29_LOCK_POS  (9U)
#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2A_LOCK      GLB_TZC_GLB_SWRST_S2A_LOCK
#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS  (10U)
#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2B_LOCK      GLB_TZC_GLB_SWRST_S2B_LOCK
#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS  (11U)
#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2C_LOCK      GLB_TZC_GLB_SWRST_S2C_LOCK
#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS  (12U)
#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2D_LOCK      GLB_TZC_GLB_SWRST_S2D_LOCK
#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS  (13U)
#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2E_LOCK      GLB_TZC_GLB_SWRST_S2E_LOCK
#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS  (14U)
#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2F_LOCK      GLB_TZC_GLB_SWRST_S2F_LOCK
#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS  (15U)
#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S10_LOCK      GLB_TZC_GLB_SWRST_S10_LOCK
#define GLB_TZC_GLB_SWRST_S10_LOCK_POS  (16U)
#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S11_LOCK      GLB_TZC_GLB_SWRST_S11_LOCK
#define GLB_TZC_GLB_SWRST_S11_LOCK_POS  (17U)
#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S12_LOCK      GLB_TZC_GLB_SWRST_S12_LOCK
#define GLB_TZC_GLB_SWRST_S12_LOCK_POS  (18U)
#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S13_LOCK      GLB_TZC_GLB_SWRST_S13_LOCK
#define GLB_TZC_GLB_SWRST_S13_LOCK_POS  (19U)
#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S14_LOCK      GLB_TZC_GLB_SWRST_S14_LOCK
#define GLB_TZC_GLB_SWRST_S14_LOCK_POS  (20U)
#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S15_LOCK      GLB_TZC_GLB_SWRST_S15_LOCK
#define GLB_TZC_GLB_SWRST_S15_LOCK_POS  (21U)
#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S16_LOCK      GLB_TZC_GLB_SWRST_S16_LOCK
#define GLB_TZC_GLB_SWRST_S16_LOCK_POS  (22U)
#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S17_LOCK      GLB_TZC_GLB_SWRST_S17_LOCK
#define GLB_TZC_GLB_SWRST_S17_LOCK_POS  (23U)
#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S18_LOCK      GLB_TZC_GLB_SWRST_S18_LOCK
#define GLB_TZC_GLB_SWRST_S18_LOCK_POS  (24U)
#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S19_LOCK      GLB_TZC_GLB_SWRST_S19_LOCK
#define GLB_TZC_GLB_SWRST_S19_LOCK_POS  (25U)
#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1A_LOCK      GLB_TZC_GLB_SWRST_S1A_LOCK
#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS  (26U)
#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1B_LOCK      GLB_TZC_GLB_SWRST_S1B_LOCK
#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS  (27U)
#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1C_LOCK      GLB_TZC_GLB_SWRST_S1C_LOCK
#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS  (28U)
#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1D_LOCK      GLB_TZC_GLB_SWRST_S1D_LOCK
#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS  (29U)
#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1E_LOCK      GLB_TZC_GLB_SWRST_S1E_LOCK
#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS  (30U)
#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1F_LOCK      GLB_TZC_GLB_SWRST_S1F_LOCK
#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS  (31U)
#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN  (1U)
#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))

/* 0xF08 : tzc_glb_ctrl_2 */
#define GLB_TZC_GLB_CTRL_2_OFFSET     (0xF08)
#define GLB_TZC_GLB_GPIO_0_LOCK       GLB_TZC_GLB_GPIO_0_LOCK
#define GLB_TZC_GLB_GPIO_0_LOCK_POS   (0U)
#define GLB_TZC_GLB_GPIO_0_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_0_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
#define GLB_TZC_GLB_GPIO_1_LOCK       GLB_TZC_GLB_GPIO_1_LOCK
#define GLB_TZC_GLB_GPIO_1_LOCK_POS   (1U)
#define GLB_TZC_GLB_GPIO_1_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_1_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
#define GLB_TZC_GLB_GPIO_2_LOCK       GLB_TZC_GLB_GPIO_2_LOCK
#define GLB_TZC_GLB_GPIO_2_LOCK_POS   (2U)
#define GLB_TZC_GLB_GPIO_2_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_2_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
#define GLB_TZC_GLB_GPIO_3_LOCK       GLB_TZC_GLB_GPIO_3_LOCK
#define GLB_TZC_GLB_GPIO_3_LOCK_POS   (3U)
#define GLB_TZC_GLB_GPIO_3_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_3_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
#define GLB_TZC_GLB_GPIO_4_LOCK       GLB_TZC_GLB_GPIO_4_LOCK
#define GLB_TZC_GLB_GPIO_4_LOCK_POS   (4U)
#define GLB_TZC_GLB_GPIO_4_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_4_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
#define GLB_TZC_GLB_GPIO_5_LOCK       GLB_TZC_GLB_GPIO_5_LOCK
#define GLB_TZC_GLB_GPIO_5_LOCK_POS   (5U)
#define GLB_TZC_GLB_GPIO_5_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_5_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
#define GLB_TZC_GLB_GPIO_6_LOCK       GLB_TZC_GLB_GPIO_6_LOCK
#define GLB_TZC_GLB_GPIO_6_LOCK_POS   (6U)
#define GLB_TZC_GLB_GPIO_6_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_6_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
#define GLB_TZC_GLB_GPIO_7_LOCK       GLB_TZC_GLB_GPIO_7_LOCK
#define GLB_TZC_GLB_GPIO_7_LOCK_POS   (7U)
#define GLB_TZC_GLB_GPIO_7_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_7_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
#define GLB_TZC_GLB_GPIO_8_LOCK       GLB_TZC_GLB_GPIO_8_LOCK
#define GLB_TZC_GLB_GPIO_8_LOCK_POS   (8U)
#define GLB_TZC_GLB_GPIO_8_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_8_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
#define GLB_TZC_GLB_GPIO_9_LOCK       GLB_TZC_GLB_GPIO_9_LOCK
#define GLB_TZC_GLB_GPIO_9_LOCK_POS   (9U)
#define GLB_TZC_GLB_GPIO_9_LOCK_LEN   (1U)
#define GLB_TZC_GLB_GPIO_9_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
#define GLB_TZC_GLB_GPIO_10_LOCK      GLB_TZC_GLB_GPIO_10_LOCK
#define GLB_TZC_GLB_GPIO_10_LOCK_POS  (10U)
#define GLB_TZC_GLB_GPIO_10_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_10_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS))
#define GLB_TZC_GLB_GPIO_11_LOCK      GLB_TZC_GLB_GPIO_11_LOCK
#define GLB_TZC_GLB_GPIO_11_LOCK_POS  (11U)
#define GLB_TZC_GLB_GPIO_11_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_11_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS))
#define GLB_TZC_GLB_GPIO_12_LOCK      GLB_TZC_GLB_GPIO_12_LOCK
#define GLB_TZC_GLB_GPIO_12_LOCK_POS  (12U)
#define GLB_TZC_GLB_GPIO_12_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_12_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS))
#define GLB_TZC_GLB_GPIO_13_LOCK      GLB_TZC_GLB_GPIO_13_LOCK
#define GLB_TZC_GLB_GPIO_13_LOCK_POS  (13U)
#define GLB_TZC_GLB_GPIO_13_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_13_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS))
#define GLB_TZC_GLB_GPIO_14_LOCK      GLB_TZC_GLB_GPIO_14_LOCK
#define GLB_TZC_GLB_GPIO_14_LOCK_POS  (14U)
#define GLB_TZC_GLB_GPIO_14_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_14_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS))
#define GLB_TZC_GLB_GPIO_15_LOCK      GLB_TZC_GLB_GPIO_15_LOCK
#define GLB_TZC_GLB_GPIO_15_LOCK_POS  (15U)
#define GLB_TZC_GLB_GPIO_15_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_15_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS))
#define GLB_TZC_GLB_GPIO_16_LOCK      GLB_TZC_GLB_GPIO_16_LOCK
#define GLB_TZC_GLB_GPIO_16_LOCK_POS  (16U)
#define GLB_TZC_GLB_GPIO_16_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_16_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS))
#define GLB_TZC_GLB_GPIO_17_LOCK      GLB_TZC_GLB_GPIO_17_LOCK
#define GLB_TZC_GLB_GPIO_17_LOCK_POS  (17U)
#define GLB_TZC_GLB_GPIO_17_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_17_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS))
#define GLB_TZC_GLB_GPIO_18_LOCK      GLB_TZC_GLB_GPIO_18_LOCK
#define GLB_TZC_GLB_GPIO_18_LOCK_POS  (18U)
#define GLB_TZC_GLB_GPIO_18_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_18_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS))
#define GLB_TZC_GLB_GPIO_19_LOCK      GLB_TZC_GLB_GPIO_19_LOCK
#define GLB_TZC_GLB_GPIO_19_LOCK_POS  (19U)
#define GLB_TZC_GLB_GPIO_19_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_19_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS))
#define GLB_TZC_GLB_GPIO_20_LOCK      GLB_TZC_GLB_GPIO_20_LOCK
#define GLB_TZC_GLB_GPIO_20_LOCK_POS  (20U)
#define GLB_TZC_GLB_GPIO_20_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_20_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS))
#define GLB_TZC_GLB_GPIO_21_LOCK      GLB_TZC_GLB_GPIO_21_LOCK
#define GLB_TZC_GLB_GPIO_21_LOCK_POS  (21U)
#define GLB_TZC_GLB_GPIO_21_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_21_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS))
#define GLB_TZC_GLB_GPIO_22_LOCK      GLB_TZC_GLB_GPIO_22_LOCK
#define GLB_TZC_GLB_GPIO_22_LOCK_POS  (22U)
#define GLB_TZC_GLB_GPIO_22_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_22_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS))
#define GLB_TZC_GLB_GPIO_23_LOCK      GLB_TZC_GLB_GPIO_23_LOCK
#define GLB_TZC_GLB_GPIO_23_LOCK_POS  (23U)
#define GLB_TZC_GLB_GPIO_23_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_23_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS))
#define GLB_TZC_GLB_GPIO_24_LOCK      GLB_TZC_GLB_GPIO_24_LOCK
#define GLB_TZC_GLB_GPIO_24_LOCK_POS  (24U)
#define GLB_TZC_GLB_GPIO_24_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_24_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS))
#define GLB_TZC_GLB_GPIO_25_LOCK      GLB_TZC_GLB_GPIO_25_LOCK
#define GLB_TZC_GLB_GPIO_25_LOCK_POS  (25U)
#define GLB_TZC_GLB_GPIO_25_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_25_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS))
#define GLB_TZC_GLB_GPIO_26_LOCK      GLB_TZC_GLB_GPIO_26_LOCK
#define GLB_TZC_GLB_GPIO_26_LOCK_POS  (26U)
#define GLB_TZC_GLB_GPIO_26_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_26_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS))
#define GLB_TZC_GLB_GPIO_27_LOCK      GLB_TZC_GLB_GPIO_27_LOCK
#define GLB_TZC_GLB_GPIO_27_LOCK_POS  (27U)
#define GLB_TZC_GLB_GPIO_27_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_27_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS))
#define GLB_TZC_GLB_GPIO_28_LOCK      GLB_TZC_GLB_GPIO_28_LOCK
#define GLB_TZC_GLB_GPIO_28_LOCK_POS  (28U)
#define GLB_TZC_GLB_GPIO_28_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_28_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS))
#define GLB_TZC_GLB_GPIO_29_LOCK      GLB_TZC_GLB_GPIO_29_LOCK
#define GLB_TZC_GLB_GPIO_29_LOCK_POS  (29U)
#define GLB_TZC_GLB_GPIO_29_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_29_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS)
#define GLB_TZC_GLB_GPIO_29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS))
#define GLB_TZC_GLB_GPIO_30_LOCK      GLB_TZC_GLB_GPIO_30_LOCK
#define GLB_TZC_GLB_GPIO_30_LOCK_POS  (30U)
#define GLB_TZC_GLB_GPIO_30_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_30_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS)
#define GLB_TZC_GLB_GPIO_30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS))
#define GLB_TZC_GLB_GPIO_31_LOCK      GLB_TZC_GLB_GPIO_31_LOCK
#define GLB_TZC_GLB_GPIO_31_LOCK_POS  (31U)
#define GLB_TZC_GLB_GPIO_31_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_31_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS)
#define GLB_TZC_GLB_GPIO_31_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS))

/* 0xF0C : tzc_glb_ctrl_3 */
#define GLB_TZC_GLB_CTRL_3_OFFSET     (0xF0C)
#define GLB_TZC_GLB_GPIO_32_LOCK      GLB_TZC_GLB_GPIO_32_LOCK
#define GLB_TZC_GLB_GPIO_32_LOCK_POS  (0U)
#define GLB_TZC_GLB_GPIO_32_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_32_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS)
#define GLB_TZC_GLB_GPIO_32_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS))
#define GLB_TZC_GLB_GPIO_33_LOCK      GLB_TZC_GLB_GPIO_33_LOCK
#define GLB_TZC_GLB_GPIO_33_LOCK_POS  (1U)
#define GLB_TZC_GLB_GPIO_33_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_33_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS)
#define GLB_TZC_GLB_GPIO_33_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS))
#define GLB_TZC_GLB_GPIO_34_LOCK      GLB_TZC_GLB_GPIO_34_LOCK
#define GLB_TZC_GLB_GPIO_34_LOCK_POS  (2U)
#define GLB_TZC_GLB_GPIO_34_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_34_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS)
#define GLB_TZC_GLB_GPIO_34_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS))
#define GLB_TZC_GLB_GPIO_35_LOCK      GLB_TZC_GLB_GPIO_35_LOCK
#define GLB_TZC_GLB_GPIO_35_LOCK_POS  (3U)
#define GLB_TZC_GLB_GPIO_35_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_35_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS)
#define GLB_TZC_GLB_GPIO_35_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS))
#define GLB_TZC_GLB_GPIO_36_LOCK      GLB_TZC_GLB_GPIO_36_LOCK
#define GLB_TZC_GLB_GPIO_36_LOCK_POS  (4U)
#define GLB_TZC_GLB_GPIO_36_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_36_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS)
#define GLB_TZC_GLB_GPIO_36_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS))
#define GLB_TZC_GLB_GPIO_37_LOCK      GLB_TZC_GLB_GPIO_37_LOCK
#define GLB_TZC_GLB_GPIO_37_LOCK_POS  (5U)
#define GLB_TZC_GLB_GPIO_37_LOCK_LEN  (1U)
#define GLB_TZC_GLB_GPIO_37_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS)
#define GLB_TZC_GLB_GPIO_37_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS))

struct glb_reg {
    /* 0x0 : clk_cfg0 */
    union {
        struct
        {
            uint32_t reg_pll_en       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_fclk_en      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_hclk_en      : 1; /* [    2],        r/w,        0x1 */
            uint32_t reg_bclk_en      : 1; /* [    3],        r/w,        0x1 */
            uint32_t reg_pll_sel      : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t hbn_root_clk_sel : 2; /* [ 7: 6],          r,        0x0 */
            uint32_t reg_hclk_div     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_bclk_div     : 8; /* [23:16],        r/w,        0x0 */
            uint32_t fclk_sw_state    : 3; /* [26:24],          r,        0x0 */
            uint32_t chip_rdy         : 1; /* [   27],          r,        0x0 */
            uint32_t glb_id           : 4; /* [31:28],          r,        0x7 */
        } BF;
        uint32_t WORD;
    } clk_cfg0;

    /* 0x4 : clk_cfg1 */
    union {
        struct
        {
            uint32_t qdec_clk_div            : 5; /* [ 4: 0],        r/w,       0x1f */
            uint32_t reserved_5_6            : 2; /* [ 6: 5],       rsvd,        0x0 */
            uint32_t qdec_clk_sel            : 1; /* [    7],        r/w,        0x0 */
            uint32_t usb_clk_en              : 1; /* [    8],        r/w,        0x1 */
            uint32_t dll_48m_div_en          : 1; /* [    9],        r/w,        0x1 */
            uint32_t reserved_10_11          : 2; /* [11:10],       rsvd,        0x0 */
            uint32_t reg_i2s_clk_sel         : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_i2s0_clk_en         : 1; /* [   13],        r/w,        0x0 */
            uint32_t reg_i2s_0_ref_clk_oe    : 1; /* [   14],        r/w,        0x0 */
            uint32_t reserved_15             : 1; /* [   15],       rsvd,        0x0 */
            uint32_t ble_clk_sel             : 6; /* [21:16],        r/w,       0x10 */
            uint32_t reserved_22_23          : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t ble_en                  : 1; /* [   24],        r/w,        0x1 */
            uint32_t m154_zbEn               : 1; /* [   25],        r/w,        0x1 */
            uint32_t reserved_26_27          : 2; /* [27:26],       rsvd,        0x0 */
            uint32_t reg_cam_ref_clk_en      : 1; /* [   28],        r/w,        0x0 */
            uint32_t reg_cam_ref_clk_src_sel : 1; /* [   29],        r/w,        0x0 */
            uint32_t reg_cam_ref_clk_div     : 2; /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } clk_cfg1;

    /* 0x8 : clk_cfg2 */
    union {
        struct
        {
            uint32_t uart_clk_div     : 3; /* [ 2: 0],        r/w,        0x7 */
            uint32_t reserved_3       : 1; /* [    3],       rsvd,        0x0 */
            uint32_t uart_clk_en      : 1; /* [    4],        r/w,        0x1 */
            uint32_t reserved_5_6     : 2; /* [ 6: 5],       rsvd,        0x0 */
            uint32_t hbn_uart_clk_sel : 1; /* [    7],          r,        0x0 */
            uint32_t sf_clk_div       : 3; /* [10: 8],        r/w,        0x3 */
            uint32_t sf_clk_en        : 1; /* [   11],        r/w,        0x1 */
            uint32_t sf_clk_sel       : 2; /* [13:12],        r/w,        0x2 */
            uint32_t sf_clk_sel2      : 2; /* [15:14],        r/w,        0x0 */
            uint32_t ir_clk_div       : 6; /* [21:16],        r/w,        0xf */
            uint32_t reserved_22      : 1; /* [   22],       rsvd,        0x0 */
            uint32_t ir_clk_en        : 1; /* [   23],        r/w,        0x1 */
            uint32_t dma_clk_en       : 8; /* [31:24],        r/w,       0xff */
        } BF;
        uint32_t WORD;
    } clk_cfg2;

    /* 0xC : clk_cfg3 */
    union {
        struct
        {
            uint32_t spi_clk_div           : 5; /* [ 4: 0],        r/w,        0x3 */
            uint32_t cfg_sel_eth_ref_clk_o : 1; /* [    5],        r/w,        0x0 */
            uint32_t cfg_inv_eth_ref_clk_o : 1; /* [    6],        r/w,        0x1 */
            uint32_t cfg_inv_eth_tx_clk    : 1; /* [    7],        r/w,        0x1 */
            uint32_t spi_clk_en            : 1; /* [    8],        r/w,        0x1 */
            uint32_t cfg_inv_rf_test_clk_o : 1; /* [    9],        r/w,        0x1 */
            uint32_t cfg_inv_eth_rx_clk    : 1; /* [   10],        r/w,        0x1 */
            uint32_t reserved_11_15        : 5; /* [15:11],       rsvd,        0x0 */
            uint32_t i2c_clk_div           : 8; /* [23:16],        r/w,       0xff */
            uint32_t i2c_clk_en            : 1; /* [   24],        r/w,        0x1 */
            uint32_t reserved_25_27        : 3; /* [27:25],       rsvd,        0x0 */
            uint32_t chip_clk_out_0_sel    : 2; /* [29:28],        r/w,        0x0 */
            uint32_t chip_clk_out_1_sel    : 2; /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } clk_cfg3;

    /* 0x10 : swrst_cfg0 */
    union {
        struct
        {
            uint32_t swrst_s00     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t swrst_s01     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_3  : 2;  /* [ 3: 2],       rsvd,        0x0 */
            uint32_t swrst_s20     : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_7  : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t swrst_s30     : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } swrst_cfg0;

    /* 0x14 : swrst_cfg1 */
    union {
        struct
        {
            uint32_t swrst_s10   : 1; /* [    0],        r/w,        0x0 */
            uint32_t swrst_s11   : 1; /* [    1],        r/w,        0x0 */
            uint32_t swrst_s12   : 1; /* [    2],        r/w,        0x0 */
            uint32_t swrst_s13   : 1; /* [    3],        r/w,        0x0 */
            uint32_t swrst_s14   : 1; /* [    4],        r/w,        0x0 */
            uint32_t swrst_s15   : 1; /* [    5],        r/w,        0x0 */
            uint32_t swrst_s16   : 1; /* [    6],        r/w,        0x0 */
            uint32_t swrst_s17   : 1; /* [    7],        r/w,        0x0 */
            uint32_t swrst_s18   : 1; /* [    8],        r/w,        0x0 */
            uint32_t swrst_s19   : 1; /* [    9],        r/w,        0x0 */
            uint32_t swrst_s1a   : 1; /* [   10],        r/w,        0x0 */
            uint32_t swrst_s1b   : 1; /* [   11],        r/w,        0x0 */
            uint32_t swrst_s1c   : 1; /* [   12],        r/w,        0x0 */
            uint32_t swrst_s1d   : 1; /* [   13],        r/w,        0x0 */
            uint32_t swrst_s1e   : 1; /* [   14],        r/w,        0x0 */
            uint32_t swrst_s1f   : 1; /* [   15],        r/w,        0x0 */
            uint32_t swrst_s1a0  : 1; /* [   16],        r/w,        0x0 */
            uint32_t swrst_s1a1  : 1; /* [   17],        r/w,        0x0 */
            uint32_t swrst_s1a2  : 1; /* [   18],        r/w,        0x0 */
            uint32_t swrst_s1a3  : 1; /* [   19],        r/w,        0x0 */
            uint32_t swrst_s1a4  : 1; /* [   20],        r/w,        0x0 */
            uint32_t swrst_s1a5  : 1; /* [   21],        r/w,        0x0 */
            uint32_t swrst_s1a6  : 1; /* [   22],        r/w,        0x0 */
            uint32_t swrst_s1a7  : 1; /* [   23],        r/w,        0x0 */
            uint32_t swrst_s1a8  : 1; /* [   24],        r/w,        0x0 */
            uint32_t swrst_s1a9  : 1; /* [   25],        r/w,        0x0 */
            uint32_t swrst_s1aa  : 1; /* [   26],        r/w,        0x0 */
            uint32_t swrst_s1ab  : 1; /* [   27],        r/w,        0x0 */
            uint32_t swrst_s1ac  : 1; /* [   28],        r/w,        0x0 */
            uint32_t swrst_s1ad  : 1; /* [   29],        r/w,        0x0 */
            uint32_t swrst_s1ae  : 1; /* [   30],        r/w,        0x0 */
            uint32_t reserved_31 : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } swrst_cfg1;

    /* 0x18 : swrst_cfg2 */
    union {
        struct
        {
            uint32_t reg_ctrl_pwron_rst   : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_ctrl_cpu_reset   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reg_ctrl_sys_reset   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t reg_ctrl_reset_dummy : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t reserved_8_23        : 16; /* [23: 8],       rsvd,        0x0 */
            uint32_t pka_clk_sel          : 1;  /* [   24],        r/w,        0x0 */
            uint32_t reserved_25_31       : 7;  /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } swrst_cfg2;

    /* 0x1C : swrst_cfg3 */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } swrst_cfg3;

    /* 0x20 : cgen_cfg0 */
    union {
        struct
        {
            uint32_t cgen_m        : 8;  /* [ 7: 0],        r/w,       0xff */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cgen_cfg0;

    /* 0x24 : cgen_cfg1 */
    union {
        struct
        {
            uint32_t cgen_s1  : 16; /* [15: 0],        r/w,     0xcfff */
            uint32_t cgen_s1a : 16; /* [31:16],        r/w,     0x9b23 */
        } BF;
        uint32_t WORD;
    } cgen_cfg1;

    /* 0x28 : cgen_cfg2 */
    union {
        struct
        {
            uint32_t cgen_s2       : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3  : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t cgen_s3       : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_31 : 27; /* [31: 5],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cgen_cfg2;

    /* 0x2C : cgen_cfg3 */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cgen_cfg3;

    /* 0x30 : MBIST_CTL */
    union {
        struct
        {
            uint32_t irom_mbist_mode        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t hsram_mem_mbist_mode   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t hsram_cache_mbist_mode : 1;  /* [    2],        r/w,        0x0 */
            uint32_t tag_mbist_mode         : 1;  /* [    3],        r/w,        0x0 */
            uint32_t ocram_mbist_mode       : 1;  /* [    4],        r/w,        0x0 */
            uint32_t em_ram_mbist_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_30          : 25; /* [30: 6],       rsvd,        0x0 */
            uint32_t reg_mbist_rst_n        : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } MBIST_CTL;

    /* 0x34 : MBIST_STAT */
    union {
        struct
        {
            uint32_t irom_mbist_done        : 1;  /* [    0],          r,        0x0 */
            uint32_t hsram_mem_mbist_done   : 1;  /* [    1],          r,        0x0 */
            uint32_t hsram_cache_mbist_done : 1;  /* [    2],          r,        0x0 */
            uint32_t tag_mbist_done         : 1;  /* [    3],          r,        0x0 */
            uint32_t ocram_mbist_done       : 1;  /* [    4],          r,        0x0 */
            uint32_t em_ram_mbist_done      : 1;  /* [    5],          r,        0x0 */
            uint32_t reserved_6_15          : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t irom_mbist_fail        : 1;  /* [   16],          r,        0x0 */
            uint32_t hsram_mem_mbist_fail   : 1;  /* [   17],          r,        0x0 */
            uint32_t hsram_cache_mbist_fail : 1;  /* [   18],          r,        0x0 */
            uint32_t tag_mbist_fail         : 1;  /* [   19],          r,        0x0 */
            uint32_t ocram_mbist_fail       : 1;  /* [   20],          r,        0x0 */
            uint32_t em_ram_mbist_fail      : 1;  /* [   21],          r,        0x0 */
            uint32_t reserved_22_31         : 10; /* [31:22],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } MBIST_STAT;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[24];

    /* 0x50 : bmx_cfg1 */
    union {
        struct
        {
            uint32_t bmx_timeout_en      : 4; /* [ 3: 0],        r/w,        0x0 */
            uint32_t bmx_arb_mode        : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t bmx_err_en          : 1; /* [    8],        r/w,        0x0 */
            uint32_t bmx_busy_option_dis : 1; /* [    9],        r/w,        0x0 */
            uint32_t bmx_gating_dis      : 1; /* [   10],        r/w,        0x0 */
            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
            uint32_t hsel_option         : 4; /* [15:12],        r/w,        0x0 */
            uint32_t pds_apb_cfg         : 8; /* [23:16],        r/w,        0x0 */
            uint32_t hbn_apb_cfg         : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } bmx_cfg1;

    /* 0x54 : bmx_cfg2 */
    union {
        struct
        {
            uint32_t bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
            uint32_t bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
            uint32_t reserved_6_7     : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_w_thre_bmx   : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reg_w_thre_l1c   : 2;  /* [11:10],        r/w,        0x0 */
            uint32_t reserved_12_27   : 16; /* [27:12],       rsvd,        0x0 */
            uint32_t bmx_dbg_sel      : 4;  /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } bmx_cfg2;

    /* 0x58 : bmx_err_addr */
    union {
        struct
        {
            uint32_t bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } bmx_err_addr;

    /* 0x5C : bmx_dbg_out */
    union {
        struct
        {
            uint32_t bmx_dbg_out : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } bmx_dbg_out;

    /* 0x60 : rsv0 */
    union {
        struct
        {
            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rsv0;

    /* 0x64 : rsv1 */
    union {
        struct
        {
            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rsv1;

    /* 0x68 : rsv2 */
    union {
        struct
        {
            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rsv2;

    /* 0x6C : rsv3 */
    union {
        struct
        {
            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } rsv3;

    /* 0x70 : sram_ret */
    union {
        struct
        {
            uint32_t reg_sram_ret : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sram_ret;

    /* 0x74 : sram_slp */
    union {
        struct
        {
            uint32_t reg_sram_slp : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sram_slp;

    /* 0x78 : sram_parm */
    union {
        struct
        {
            uint32_t reg_sram_parm : 32; /* [31: 0],        r/w, 0x6a4c0c0c */
        } BF;
        uint32_t WORD;
    } sram_parm;

    /* 0x7C : seam_misc */
    union {
        struct
        {
            uint32_t em_sel        : 4;  /* [ 3: 0],        r/w,        0x3 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } seam_misc;

    /* 0x80 : glb_parm */
    union {
        struct
        {
            uint32_t jtag_swap_set            : 8; /* [ 7: 0],        r/w,        0x4 */
            uint32_t cfg_sflash2_swap_io0_io3 : 1; /* [    8],        r/w,        0x0 */
            uint32_t cfg_sflash2_swap_cs_io2  : 1; /* [    9],        r/w,        0x0 */
            uint32_t cfg_flash_scenario       : 2; /* [11:10],        r/w,        0x0 */
            uint32_t reg_spi_0_master_mode    : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_spi_0_swap           : 1; /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t reg_cci_use_jtag_pin     : 1; /* [   16],        r/w,        0x1 */
            uint32_t p1_adc_test_with_cci     : 1; /* [   17],        r/w,        0x0 */
            uint32_t p2_dac_test_with_cci     : 1; /* [   18],        r/w,        0x0 */
            uint32_t p3_cci_use_io_0_2_7      : 1; /* [   19],        r/w,        0x0 */
            uint32_t p4_adc_test_with_jtag    : 1; /* [   20],        r/w,        0x0 */
            uint32_t p5_dac_test_with_jtag    : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22              : 1; /* [   22],       rsvd,        0x0 */
            uint32_t p6_jtag_use_io_0_2_7     : 1; /* [   23],        r/w,        0x0 */
            uint32_t uart_swap_set            : 4; /* [27:24],        r/w,        0x0 */
            uint32_t reserved_28              : 1; /* [   28],       rsvd,        0x0 */
            uint32_t reg_kys_drv_val          : 1; /* [   29],        r/w,        0x0 */
            uint32_t reg_ext_rst_smt          : 1; /* [   30],        r/w,        0x0 */
            uint32_t pin_sel_emac_cam         : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } glb_parm;

    /* 0x84 : PDM_CLK_CTRL */
    union {
        struct
        {
            uint32_t reg_pdm0_clk_div : 6;  /* [ 5: 0],        r/w,        0x1 */
            uint32_t reserved_6       : 1;  /* [    6],       rsvd,        0x0 */
            uint32_t reg_pdm0_clk_en  : 1;  /* [    7],        r/w,        0x1 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDM_CLK_CTRL;

    /* 0x88 : GPIO_USE_PSRAM__IO */
    union {
        struct
        {
            uint32_t cfg_gpio_use_psram_io : 6;  /* [ 5: 0],        r/w,        0x0 */
            uint32_t reserved_6_31         : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_USE_PSRAM__IO;

    /* 0x8c  reserved */
    uint8_t RESERVED0x8c[4];

    /* 0x90 : CPU_CLK_CFG */
    union {
        struct
        {
            uint32_t cpu_rtc_div        : 17; /* [16: 0],        r/w,       0x10 */
            uint32_t reserved_17        : 1;  /* [   17],       rsvd,        0x0 */
            uint32_t cpu_rtc_en         : 1;  /* [   18],        r/w,        0x0 */
            uint32_t cpu_rtc_sel        : 1;  /* [   19],        r/w,        0x1 */
            uint32_t debug_ndreset_gate : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reserved_21_31     : 11; /* [31:21],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } CPU_CLK_CFG;

    /* 0x94  reserved */
    uint8_t RESERVED0x94[16];

    /* 0xA4 : GPADC_32M_SRC_CTRL */
    union {
        struct
        {
            uint32_t gpadc_32m_clk_div : 6;  /* [ 5: 0],        r/w,        0x2 */
            uint32_t reserved_6        : 1;  /* [    6],       rsvd,        0x0 */
            uint32_t gpadc_32m_clk_sel : 1;  /* [    7],        r/w,        0x0 */
            uint32_t gpadc_32m_div_en  : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_31     : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPADC_32M_SRC_CTRL;

    /* 0xA8 : DIG32K_WAKEUP_CTRL */
    union {
        struct
        {
            uint32_t dig_32k_div            : 11; /* [10: 0],        r/w,      0x3e8 */
            uint32_t reserved_11            : 1;  /* [   11],       rsvd,        0x0 */
            uint32_t dig_32k_en             : 1;  /* [   12],        r/w,        0x1 */
            uint32_t dig_32k_comp           : 1;  /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_15         : 2;  /* [15:14],       rsvd,        0x0 */
            uint32_t dig_512k_div           : 7;  /* [22:16],        r/w,       0x3e */
            uint32_t reserved_23            : 1;  /* [   23],       rsvd,        0x0 */
            uint32_t dig_512k_en            : 1;  /* [   24],        r/w,        0x1 */
            uint32_t dig_512k_comp          : 1;  /* [   25],        r/w,        0x1 */
            uint32_t reserved_26_27         : 2;  /* [27:26],       rsvd,        0x0 */
            uint32_t dig_clk_src_sel        : 2;  /* [29:28],        r/w,        0x0 */
            uint32_t reserved_30            : 1;  /* [   30],       rsvd,        0x0 */
            uint32_t reg_en_platform_wakeup : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DIG32K_WAKEUP_CTRL;

    /* 0xAC : WIFI_BT_COEX_CTRL */
    union {
        struct
        {
            uint32_t coex_bt_channel : 7;  /* [ 6: 0],        r/w,        0x0 */
            uint32_t coex_bt_pti     : 4;  /* [10: 7],        r/w,        0x0 */
            uint32_t coex_bt_bw      : 1;  /* [   11],        r/w,        0x0 */
            uint32_t en_gpio_bt_coex : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_31  : 19; /* [31:13],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WIFI_BT_COEX_CTRL;

    /* 0xB0 : BZ_COEX_CTRL */
    union {
        struct
        {
            uint32_t coex_en           : 1; /* [    0],        r/w,        0x0 */
            uint32_t wlan_en           : 1; /* [    1],        r/w,        0x0 */
            uint32_t ble_rx_ignore     : 1; /* [    2],        r/w,        0x0 */
            uint32_t m154_rx_ignore    : 1; /* [    3],        r/w,        0x0 */
            uint32_t bz_pri_thr        : 4; /* [ 7: 4],        r/w,        0x0 */
            uint32_t bz_pri_en         : 1; /* [    8],        r/w,        0x1 */
            uint32_t bz_pri_pol        : 1; /* [    9],        r/w,        0x1 */
            uint32_t bz_active_pol     : 1; /* [   10],        r/w,        0x1 */
            uint32_t bz_abort_pol      : 1; /* [   11],        r/w,        0x1 */
            uint32_t coex_pri          : 1; /* [   12],        r/w,        0x0 */
            uint32_t force_m154_win    : 1; /* [   13],        r/w,        0x0 */
            uint32_t force_ble_win     : 1; /* [   14],        r/w,        0x0 */
            uint32_t coex_option       : 1; /* [   15],        r/w,        0x0 */
            uint32_t coex_force_ch     : 7; /* [22:16],        r/w,        0x4 */
            uint32_t reserved_23       : 1; /* [   23],       rsvd,        0x0 */
            uint32_t m154_rx_abort_dis : 1; /* [   24],        r/w,        0x0 */
            uint32_t m154_tx_abort_dis : 1; /* [   25],        r/w,        0x0 */
            uint32_t ble_rx_abort_dis  : 1; /* [   26],        r/w,        0x0 */
            uint32_t ble_tx_abort_dis  : 1; /* [   27],        r/w,        0x0 */
            uint32_t coex_arb          : 4; /* [31:28],          r,        0x8 */
        } BF;
        uint32_t WORD;
    } BZ_COEX_CTRL;

    /* 0xb4  reserved */
    uint8_t RESERVED0xb4[12];

    /* 0xC0 : UART_SIG_SEL_0 */
    union {
        struct
        {
            uint32_t uart_sig_0_sel : 4; /* [ 3: 0],        r/w,        0x0 */
            uint32_t uart_sig_1_sel : 4; /* [ 7: 4],        r/w,        0x1 */
            uint32_t uart_sig_2_sel : 4; /* [11: 8],        r/w,        0x2 */
            uint32_t uart_sig_3_sel : 4; /* [15:12],        r/w,        0x3 */
            uint32_t uart_sig_4_sel : 4; /* [19:16],        r/w,        0x4 */
            uint32_t uart_sig_5_sel : 4; /* [23:20],        r/w,        0x5 */
            uint32_t uart_sig_6_sel : 4; /* [27:24],        r/w,        0x6 */
            uint32_t uart_sig_7_sel : 4; /* [31:28],        r/w,        0x7 */
        } BF;
        uint32_t WORD;
    } UART_SIG_SEL_0;

    /* 0xc4  reserved */
    uint8_t RESERVED0xc4[12];

    /* 0xD0 : DBG_SEL_LL */
    union {
        struct
        {
            uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DBG_SEL_LL;

    /* 0xD4 : DBG_SEL_LH */
    union {
        struct
        {
            uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DBG_SEL_LH;

    /* 0xD8 : DBG_SEL_HL */
    union {
        struct
        {
            uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DBG_SEL_HL;

    /* 0xDC : DBG_SEL_HH */
    union {
        struct
        {
            uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } DBG_SEL_HH;

    /* 0xE0 : debug */
    union {
        struct
        {
            uint32_t debug_oe : 1;  /* [    0],        r/w,        0x0 */
            uint32_t debug_i  : 31; /* [31: 1],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } debug;

    /* 0xe4  reserved */
    uint8_t RESERVED0xe4[28];

    /* 0x100 : GPIO_CFGCTL0 */
    union {
        struct
        {
            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL0;

    /* 0x104 : GPIO_CFGCTL1 */
    union {
        struct
        {
            uint32_t reg_gpio_2_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_2_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_2_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_2_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_2_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_2_func_sel : 5; /* [12: 8],        r/w,        0xe */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_3_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_3_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_3_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_3_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_3_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_3_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL1;

    /* 0x108 : GPIO_CFGCTL2 */
    union {
        struct
        {
            uint32_t reg_gpio_4_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_4_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_4_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_4_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_4_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_4_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_5_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_5_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_5_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_5_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_5_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_5_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL2;

    /* 0x10C : GPIO_CFGCTL3 */
    union {
        struct
        {
            uint32_t reg_gpio_6_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_6_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_6_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_6_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_6_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_6_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_7_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_7_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_7_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_7_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_7_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_7_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL3;

    /* 0x110 : GPIO_CFGCTL4 */
    union {
        struct
        {
            uint32_t reg_gpio_8_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_8_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_8_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_8_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_8_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_8_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_9_ie       : 1; /* [   16],        r/w,        0x0 */
            uint32_t reg_gpio_9_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_9_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_9_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_9_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_9_func_sel : 5; /* [28:24],        r/w,        0xe */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL4;

    /* 0x114 : GPIO_CFGCTL5 */
    union {
        struct
        {
            uint32_t reg_gpio_10_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_10_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_10_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_10_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_10_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_10_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_11_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_11_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_11_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_11_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_11_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_11_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL5;

    /* 0x118 : GPIO_CFGCTL6 */
    union {
        struct
        {
            uint32_t reg_gpio_12_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_12_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_12_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_12_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_12_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_12_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_13_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_13_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_13_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_13_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_13_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_13_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL6;

    /* 0x11C : GPIO_CFGCTL7 */
    union {
        struct
        {
            uint32_t reg_gpio_14_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_14_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_14_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_14_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_14_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_14_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_15_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_15_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_15_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_15_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_15_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_15_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL7;

    /* 0x120 : GPIO_CFGCTL8 */
    union {
        struct
        {
            uint32_t reg_gpio_16_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_16_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_16_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_16_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_16_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_16_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_17_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_17_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_17_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_17_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_17_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_17_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL8;

    /* 0x124 : GPIO_CFGCTL9 */
    union {
        struct
        {
            uint32_t reg_gpio_18_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_18_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_18_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_18_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_18_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_18_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_19_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_19_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_19_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_19_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_19_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_19_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL9;

    /* 0x128 : GPIO_CFGCTL10 */
    union {
        struct
        {
            uint32_t reg_gpio_20_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_20_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_20_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_20_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_20_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_20_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_21_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_21_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_21_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_21_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_21_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_21_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL10;

    /* 0x12C : GPIO_CFGCTL11 */
    union {
        struct
        {
            uint32_t reg_gpio_22_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_22_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_22_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_22_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_22_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_22_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_23_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_23_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_23_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_23_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_23_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_23_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL11;

    /* 0x130 : GPIO_CFGCTL12 */
    union {
        struct
        {
            uint32_t reg_gpio_24_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_24_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_24_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_24_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_24_pd       : 1; /* [    5],        r/w,        0x1 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_24_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_25_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_25_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_25_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_25_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_25_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_25_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL12;

    /* 0x134 : GPIO_CFGCTL13 */
    union {
        struct
        {
            uint32_t reg_gpio_26_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_26_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_26_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_26_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_26_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_26_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_27_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_27_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_27_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_27_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_27_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_27_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL13;

    /* 0x138 : GPIO_CFGCTL14 */
    union {
        struct
        {
            uint32_t reg_gpio_28_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_28_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_28_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_28_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_28_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_28_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_29_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_29_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_29_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_29_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_29_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_29_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL14;

    /* 0x13C : GPIO_CFGCTL15 */
    union {
        struct
        {
            uint32_t reg_gpio_30_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_30_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_30_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_30_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_30_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_30_func_sel : 5; /* [12: 8],        r/w,        0xb */
            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_31_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_31_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_31_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_31_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_31_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_31_func_sel : 5; /* [28:24],        r/w,        0xb */
            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL15;

    /* 0x140 : GPIO_CFGCTL16 */
    union {
        struct
        {
            uint32_t reg_gpio_32_ie  : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_32_smt : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_32_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_32_pu  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_32_pd  : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_33_ie  : 1;  /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_33_smt : 1;  /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_33_drv : 2;  /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_33_pu  : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_33_pd  : 1;  /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL16;

    /* 0x144 : GPIO_CFGCTL17 */
    union {
        struct
        {
            uint32_t reg_gpio_34_ie  : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_34_smt : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_34_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_34_pu  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_34_pd  : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_35_ie  : 1;  /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_35_smt : 1;  /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_35_drv : 2;  /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_35_pu  : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_35_pd  : 1;  /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL17;

    /* 0x148 : GPIO_CFGCTL18 */
    union {
        struct
        {
            uint32_t reg_gpio_36_ie  : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_36_smt : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_36_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_36_pu  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_36_pd  : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_37_ie  : 1;  /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_37_smt : 1;  /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_37_drv : 2;  /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_37_pu  : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_37_pd  : 1;  /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL18;

    /* 0x14c  reserved */
    uint8_t RESERVED0x14c[52];

    /* 0x180 : GPIO_CFGCTL30 */
    union {
        struct
        {
            uint32_t reg_gpio_0_i  : 1; /* [    0],          r,        0x0 */
            uint32_t reg_gpio_1_i  : 1; /* [    1],          r,        0x0 */
            uint32_t reg_gpio_2_i  : 1; /* [    2],          r,        0x0 */
            uint32_t reg_gpio_3_i  : 1; /* [    3],          r,        0x0 */
            uint32_t reg_gpio_4_i  : 1; /* [    4],          r,        0x0 */
            uint32_t reg_gpio_5_i  : 1; /* [    5],          r,        0x0 */
            uint32_t reg_gpio_6_i  : 1; /* [    6],          r,        0x0 */
            uint32_t reg_gpio_7_i  : 1; /* [    7],          r,        0x0 */
            uint32_t reg_gpio_8_i  : 1; /* [    8],          r,        0x0 */
            uint32_t reg_gpio_9_i  : 1; /* [    9],          r,        0x0 */
            uint32_t reg_gpio_10_i : 1; /* [   10],          r,        0x0 */
            uint32_t reg_gpio_11_i : 1; /* [   11],          r,        0x0 */
            uint32_t reg_gpio_12_i : 1; /* [   12],          r,        0x0 */
            uint32_t reg_gpio_13_i : 1; /* [   13],          r,        0x0 */
            uint32_t reg_gpio_14_i : 1; /* [   14],          r,        0x0 */
            uint32_t reg_gpio_15_i : 1; /* [   15],          r,        0x0 */
            uint32_t reg_gpio_16_i : 1; /* [   16],          r,        0x0 */
            uint32_t reg_gpio_17_i : 1; /* [   17],          r,        0x0 */
            uint32_t reg_gpio_18_i : 1; /* [   18],          r,        0x0 */
            uint32_t reg_gpio_19_i : 1; /* [   19],          r,        0x0 */
            uint32_t reg_gpio_20_i : 1; /* [   20],          r,        0x0 */
            uint32_t reg_gpio_21_i : 1; /* [   21],          r,        0x0 */
            uint32_t reg_gpio_22_i : 1; /* [   22],          r,        0x0 */
            uint32_t reg_gpio_23_i : 1; /* [   23],          r,        0x0 */
            uint32_t reg_gpio_24_i : 1; /* [   24],          r,        0x0 */
            uint32_t reg_gpio_25_i : 1; /* [   25],          r,        0x0 */
            uint32_t reg_gpio_26_i : 1; /* [   26],          r,        0x0 */
            uint32_t reg_gpio_27_i : 1; /* [   27],          r,        0x0 */
            uint32_t reg_gpio_28_i : 1; /* [   28],          r,        0x0 */
            uint32_t reg_gpio_29_i : 1; /* [   29],          r,        0x0 */
            uint32_t reg_gpio_30_i : 1; /* [   30],          r,        0x0 */
            uint32_t reg_gpio_31_i : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL30;

    /* 0x184 : GPIO_CFGCTL31 */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL31;

    /* 0x188 : GPIO_CFGCTL32 */
    union {
        struct
        {
            uint32_t reg_gpio_0_o  : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_gpio_1_o  : 1; /* [    1],        r/w,        0x0 */
            uint32_t reg_gpio_2_o  : 1; /* [    2],        r/w,        0x0 */
            uint32_t reg_gpio_3_o  : 1; /* [    3],        r/w,        0x0 */
            uint32_t reg_gpio_4_o  : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_5_o  : 1; /* [    5],        r/w,        0x0 */
            uint32_t reg_gpio_6_o  : 1; /* [    6],        r/w,        0x0 */
            uint32_t reg_gpio_7_o  : 1; /* [    7],        r/w,        0x0 */
            uint32_t reg_gpio_8_o  : 1; /* [    8],        r/w,        0x0 */
            uint32_t reg_gpio_9_o  : 1; /* [    9],        r/w,        0x0 */
            uint32_t reg_gpio_10_o : 1; /* [   10],        r/w,        0x0 */
            uint32_t reg_gpio_11_o : 1; /* [   11],        r/w,        0x0 */
            uint32_t reg_gpio_12_o : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_gpio_13_o : 1; /* [   13],        r/w,        0x0 */
            uint32_t reg_gpio_14_o : 1; /* [   14],        r/w,        0x0 */
            uint32_t reg_gpio_15_o : 1; /* [   15],        r/w,        0x0 */
            uint32_t reg_gpio_16_o : 1; /* [   16],        r/w,        0x0 */
            uint32_t reg_gpio_17_o : 1; /* [   17],        r/w,        0x0 */
            uint32_t reg_gpio_18_o : 1; /* [   18],        r/w,        0x0 */
            uint32_t reg_gpio_19_o : 1; /* [   19],        r/w,        0x0 */
            uint32_t reg_gpio_20_o : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_21_o : 1; /* [   21],        r/w,        0x0 */
            uint32_t reg_gpio_22_o : 1; /* [   22],        r/w,        0x0 */
            uint32_t reg_gpio_23_o : 1; /* [   23],        r/w,        0x0 */
            uint32_t reg_gpio_24_o : 1; /* [   24],        r/w,        0x0 */
            uint32_t reg_gpio_25_o : 1; /* [   25],        r/w,        0x0 */
            uint32_t reg_gpio_26_o : 1; /* [   26],        r/w,        0x0 */
            uint32_t reg_gpio_27_o : 1; /* [   27],        r/w,        0x0 */
            uint32_t reg_gpio_28_o : 1; /* [   28],        r/w,        0x0 */
            uint32_t reg_gpio_29_o : 1; /* [   29],        r/w,        0x0 */
            uint32_t reg_gpio_30_o : 1; /* [   30],        r/w,        0x0 */
            uint32_t reg_gpio_31_o : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL32;

    /* 0x18C : GPIO_CFGCTL33 */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL33;

    /* 0x190 : GPIO_CFGCTL34 */
    union {
        struct
        {
            uint32_t reg_gpio_0_oe  : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_gpio_1_oe  : 1; /* [    1],        r/w,        0x0 */
            uint32_t reg_gpio_2_oe  : 1; /* [    2],        r/w,        0x0 */
            uint32_t reg_gpio_3_oe  : 1; /* [    3],        r/w,        0x0 */
            uint32_t reg_gpio_4_oe  : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_5_oe  : 1; /* [    5],        r/w,        0x0 */
            uint32_t reg_gpio_6_oe  : 1; /* [    6],        r/w,        0x0 */
            uint32_t reg_gpio_7_oe  : 1; /* [    7],        r/w,        0x0 */
            uint32_t reg_gpio_8_oe  : 1; /* [    8],        r/w,        0x0 */
            uint32_t reg_gpio_9_oe  : 1; /* [    9],        r/w,        0x0 */
            uint32_t reg_gpio_10_oe : 1; /* [   10],        r/w,        0x0 */
            uint32_t reg_gpio_11_oe : 1; /* [   11],        r/w,        0x0 */
            uint32_t reg_gpio_12_oe : 1; /* [   12],        r/w,        0x0 */
            uint32_t reg_gpio_13_oe : 1; /* [   13],        r/w,        0x0 */
            uint32_t reg_gpio_14_oe : 1; /* [   14],        r/w,        0x0 */
            uint32_t reg_gpio_15_oe : 1; /* [   15],        r/w,        0x0 */
            uint32_t reg_gpio_16_oe : 1; /* [   16],        r/w,        0x0 */
            uint32_t reg_gpio_17_oe : 1; /* [   17],        r/w,        0x0 */
            uint32_t reg_gpio_18_oe : 1; /* [   18],        r/w,        0x0 */
            uint32_t reg_gpio_19_oe : 1; /* [   19],        r/w,        0x0 */
            uint32_t reg_gpio_20_oe : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_21_oe : 1; /* [   21],        r/w,        0x0 */
            uint32_t reg_gpio_22_oe : 1; /* [   22],        r/w,        0x0 */
            uint32_t reg_gpio_23_oe : 1; /* [   23],        r/w,        0x0 */
            uint32_t reg_gpio_24_oe : 1; /* [   24],        r/w,        0x0 */
            uint32_t reg_gpio_25_oe : 1; /* [   25],        r/w,        0x0 */
            uint32_t reg_gpio_26_oe : 1; /* [   26],        r/w,        0x0 */
            uint32_t reg_gpio_27_oe : 1; /* [   27],        r/w,        0x0 */
            uint32_t reg_gpio_28_oe : 1; /* [   28],        r/w,        0x0 */
            uint32_t reg_gpio_29_oe : 1; /* [   29],        r/w,        0x0 */
            uint32_t reg_gpio_30_oe : 1; /* [   30],        r/w,        0x0 */
            uint32_t reg_gpio_31_oe : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL34;

    /* 0x194 : GPIO_CFGCTL35 */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL35;

    /* 0x198  reserved */
    uint8_t RESERVED0x198[8];

    /* 0x1A0 : GPIO_INT_MASK1 */
    union {
        struct
        {
            uint32_t reg_gpio_int_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } GPIO_INT_MASK1;

    /* 0x1a4  reserved */
    uint8_t RESERVED0x1a4[4];

    /* 0x1A8 : GPIO_INT_STAT1 */
    union {
        struct
        {
            uint32_t gpio_int_stat1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_STAT1;

    /* 0x1ac  reserved */
    uint8_t RESERVED0x1ac[4];

    /* 0x1B0 : GPIO_INT_CLR1 */
    union {
        struct
        {
            uint32_t reg_gpio_int_clr1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_CLR1;

    /* 0x1b4  reserved */
    uint8_t RESERVED0x1b4[12];

    /* 0x1C0 : GPIO_INT_MODE_SET1 */
    union {
        struct
        {
            uint32_t reg_gpio_int_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_MODE_SET1;

    /* 0x1C4 : GPIO_INT_MODE_SET2 */
    union {
        struct
        {
            uint32_t reg_gpio_int_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_MODE_SET2;

    /* 0x1C8 : GPIO_INT_MODE_SET3 */
    union {
        struct
        {
            uint32_t reg_gpio_int_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_MODE_SET3;

    /* 0x1CC : GPIO_INT_MODE_SET4 */
    union {
        struct
        {
            uint32_t reg_gpio_int_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
            uint32_t reserved_6_31          : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT_MODE_SET4;

    /* 0x1D0 : GPIO_INT2_MASK1 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_MASK1;

    /* 0x1D4 : GPIO_INT2_STAT1 */
    union {
        struct
        {
            uint32_t gpio_int2_stat1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_STAT1;

    /* 0x1D8 : GPIO_INT2_CLR1 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_clr1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_CLR1;

    /* 0x1DC : GPIO_INT2_MODE_SET1 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_MODE_SET1;

    /* 0x1E0 : GPIO_INT2_MODE_SET2 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_MODE_SET2;

    /* 0x1E4 : GPIO_INT2_MODE_SET3 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_MODE_SET3;

    /* 0x1E8 : GPIO_INT2_MODE_SET4 */
    union {
        struct
        {
            uint32_t reg_gpio_int2_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
            uint32_t reserved_6_31           : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_INT2_MODE_SET4;

    /* 0x1ec  reserved */
    uint8_t RESERVED0x1ec[20];

    /* 0x200 : dll */
    union {
        struct
        {
            uint32_t dtest_en_dll_refclk : 1; /* [    0],        r/w,        0x0 */
            uint32_t dtest_en_dll_outclk : 1; /* [    1],        r/w,        0x0 */
            uint32_t ten_dll             : 1; /* [    2],        r/w,        0x0 */
            uint32_t dll_clk_mmdiv_en    : 1; /* [    3],        r/w,        0x0 */
            uint32_t dll_clk_288M_en     : 1; /* [    4],        r/w,        0x1 */
            uint32_t dll_clk_144M_en     : 1; /* [    5],        r/w,        0x1 */
            uint32_t dll_clk_96M_en      : 1; /* [    6],        r/w,        0x1 */
            uint32_t dll_clk_57p6M_en    : 1; /* [    7],        r/w,        0x1 */
            uint32_t dll_vctrl_sel       : 3; /* [10: 8],        r/w,        0x4 */
            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
            uint32_t dll_prechg_sel      : 1; /* [   12],        r/w,        0x0 */
            uint32_t dll_prechg_reg      : 1; /* [   13],        r/w,        0x1 */
            uint32_t dll_prechg_en       : 1; /* [   14],        r/w,        0x1 */
            uint32_t dll_vctrl_force_en  : 1; /* [   15],        r/w,        0x0 */
            uint32_t dll_post_div        : 4; /* [19:16],        r/w,        0x2 */
            uint32_t dll_delay_sel       : 2; /* [21:20],        r/w,        0x1 */
            uint32_t dll_cp_op_en        : 1; /* [   22],        r/w,        0x1 */
            uint32_t dll_cp_hiz          : 1; /* [   23],        r/w,        0x0 */
            uint32_t reserved_24_27      : 4; /* [27:24],       rsvd,        0x0 */
            uint32_t dll_refclk_sel      : 1; /* [   28],        r/w,        0x0 */
            uint32_t dll_reset           : 1; /* [   29],        r/w,        0x1 */
            uint32_t pu_dll              : 1; /* [   30],        r/w,        0x0 */
            uint32_t ppu_dll             : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } dll;

    /* 0x204  reserved */
    uint8_t RESERVED0x204[32];

    /* 0x224 : led_driver */
    union {
        struct
        {
            uint32_t led_din_reg          : 1;  /* [    0],        r/w,        0x0 */
            uint32_t led_din_sel          : 1;  /* [    1],        r/w,        0x0 */
            uint32_t led_din_polarity_sel : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t leddrv_ibias         : 4;  /* [ 7: 4],        r/w,        0x8 */
            uint32_t ir_rx_gpio_sel       : 4;  /* [11: 8],        r/w,        0x0 */
            uint32_t reserved_12_27       : 16; /* [27:12],       rsvd,        0x0 */
            uint32_t leddrv_out_en        : 2;  /* [29:28],        r/w,        0x3 */
            uint32_t reserved_30          : 1;  /* [   30],       rsvd,        0x0 */
            uint32_t pu_leddrv            : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } led_driver;

    /* 0x228 : usb_xcvr */
    union {
        struct
        {
            uint32_t usb_ldo_vfb      : 3; /* [ 2: 0],        r/w,        0x3 */
            uint32_t pu_usb_ldo       : 1; /* [    3],        r/w,        0x0 */
            uint32_t usb_rout_nmos    : 3; /* [ 6: 4],        r/w,        0x3 */
            uint32_t reserved_7       : 1; /* [    7],       rsvd,        0x0 */
            uint32_t usb_rout_pmos    : 3; /* [10: 8],        r/w,        0x3 */
            uint32_t reserved_11      : 1; /* [   11],       rsvd,        0x0 */
            uint32_t usb_oeb_sel      : 1; /* [   12],         rw,        0x0 */
            uint32_t usb_oeb_reg      : 1; /* [   13],         rw,        0x1 */
            uint32_t usb_oeb          : 1; /* [   14],          r,        0x1 */
            uint32_t reserved_15      : 1; /* [   15],       rsvd,        0x0 */
            uint32_t usb_data_convert : 1; /* [   16],         rw,        0x0 */
            uint32_t reserved_17_19   : 3; /* [19:17],       rsvd,        0x0 */
            uint32_t usb_enum         : 1; /* [   20],        r/w,        0x0 */
            uint32_t usb_spd          : 1; /* [   21],        r/w,        0x1 */
            uint32_t usb_sus          : 1; /* [   22],        r/w,        0x0 */
            uint32_t pu_usb           : 1; /* [   23],        r/w,        0x0 */
            uint32_t usb_bd           : 1; /* [   24],          r,        0x0 */
            uint32_t usb_vim          : 1; /* [   25],          r,        0x0 */
            uint32_t usb_vip          : 1; /* [   26],          r,        0x0 */
            uint32_t usb_rcv          : 1; /* [   27],          r,        0x0 */
            uint32_t reserved_28_31   : 4; /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_xcvr;

    /* 0x22C : usb_xcvr_config */
    union {
        struct
        {
            uint32_t usb_v_hys_m         : 2; /* [ 1: 0],        r/w,        0x1 */
            uint32_t usb_v_hys_p         : 2; /* [ 3: 2],        r/w,        0x1 */
            uint32_t usb_bd_vth          : 3; /* [ 6: 4],        r/w,        0x1 */
            uint32_t reg_usb_use_xcvr    : 1; /* [    7],        r/w,        0x1 */
            uint32_t usb_str_drv         : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reg_usb_use_ctrl    : 1; /* [   11],        r/w,        0x1 */
            uint32_t usb_res_pullup_tune : 3; /* [14:12],        r/w,        0x2 */
            uint32_t reserved_15         : 1; /* [   15],       rsvd,        0x0 */
            uint32_t usb_slewrate_m_fall : 3; /* [18:16],        r/w,        0x3 */
            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
            uint32_t usb_slewrate_m_rise : 3; /* [22:20],        r/w,        0x4 */
            uint32_t reserved_23         : 1; /* [   23],       rsvd,        0x0 */
            uint32_t usb_slewrate_p_fall : 3; /* [26:24],        r/w,        0x3 */
            uint32_t reserved_27         : 1; /* [   27],       rsvd,        0x0 */
            uint32_t usb_slewrate_p_rise : 3; /* [30:28],        r/w,        0x4 */
            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_xcvr_config;

    /* 0x230  reserved */
    uint8_t RESERVED0x230[216];

    /* 0x308 : gpdac_ctrl */
    union {
        struct
        {
            uint32_t gpdaca_rstn_ana : 1;  /* [    0],        r/w,        0x1 */
            uint32_t gpdacb_rstn_ana : 1;  /* [    1],        r/w,        0x1 */
            uint32_t reserved_2_6    : 5;  /* [ 6: 2],       rsvd,        0x0 */
            uint32_t gpdac_test_en   : 1;  /* [    7],        r/w,        0x0 */
            uint32_t gpdac_ref_sel   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t gpdac_test_sel  : 3;  /* [11: 9],        r/w,        0x0 */
            uint32_t reserved_12_23  : 12; /* [23:12],       rsvd,        0x0 */
            uint32_t gpdac_reserved  : 8;  /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } gpdac_ctrl;

    /* 0x30C : gpdac_actrl */
    union {
        struct
        {
            uint32_t gpdac_a_en     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t gpdac_ioa_en   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
            uint32_t gpdac_a_rng    : 2;  /* [19:18],        r/w,        0x3 */
            uint32_t gpdac_a_outmux : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpdac_actrl;

    /* 0x310 : gpdac_bctrl */
    union {
        struct
        {
            uint32_t gpdac_b_en     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t gpdac_iob_en   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
            uint32_t gpdac_b_rng    : 2;  /* [19:18],        r/w,        0x3 */
            uint32_t gpdac_b_outmux : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpdac_bctrl;

    /* 0x314 : gpdac_data */
    union {
        struct
        {
            uint32_t gpdac_b_data   : 10; /* [ 9: 0],        r/w,        0x0 */
            uint32_t reserved_10_15 : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t gpdac_a_data   : 10; /* [25:16],        r/w,        0x0 */
            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpdac_data;

    /* 0x318  reserved */
    uint8_t RESERVED0x318[2792];

    /* 0xE00 : chip_revision */
    union {
        struct
        {
            uint32_t chip_rev      : 4;  /* [ 3: 0],          r,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } chip_revision;

    /* 0xe04  reserved */
    uint8_t RESERVED0xe04[252];

    /* 0xF00 : tzc_glb_ctrl_0 */
    union {
        struct
        {
            uint32_t tzc_glb_swrst_s00_lock       : 1; /* [    0],          r,        0x0 */
            uint32_t tzc_glb_swrst_s01_lock       : 1; /* [    1],          r,        0x0 */
            uint32_t reserved_2_7                 : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t tzc_glb_swrst_s30_lock       : 1; /* [    8],          r,        0x0 */
            uint32_t reserved_9_11                : 3; /* [11: 9],       rsvd,        0x0 */
            uint32_t tzc_glb_ctrl_pwron_rst_lock  : 1; /* [   12],          r,        0x0 */
            uint32_t tzc_glb_ctrl_cpu_reset_lock  : 1; /* [   13],          r,        0x0 */
            uint32_t tzc_glb_ctrl_sys_reset_lock  : 1; /* [   14],          r,        0x0 */
            uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [   15],          r,        0x0 */
            uint32_t reserved_16_24               : 9; /* [24:16],       rsvd,        0x0 */
            uint32_t tzc_glb_misc_lock            : 1; /* [   25],          r,        0x0 */
            uint32_t tzc_glb_sram_lock            : 1; /* [   26],          r,        0x0 */
            uint32_t tzc_glb_l2c_lock             : 1; /* [   27],          r,        0x0 */
            uint32_t tzc_glb_bmx_lock             : 1; /* [   28],          r,        0x0 */
            uint32_t tzc_glb_dbg_lock             : 1; /* [   29],          r,        0x0 */
            uint32_t tzc_glb_mbist_lock           : 1; /* [   30],          r,        0x0 */
            uint32_t tzc_glb_clk_lock             : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_glb_ctrl_0;

    /* 0xF04 : tzc_glb_ctrl_1 */
    union {
        struct
        {
            uint32_t tzc_glb_swrst_s20_lock : 1; /* [    0],          r,        0x0 */
            uint32_t tzc_glb_swrst_s21_lock : 1; /* [    1],          r,        0x0 */
            uint32_t tzc_glb_swrst_s22_lock : 1; /* [    2],          r,        0x0 */
            uint32_t tzc_glb_swrst_s23_lock : 1; /* [    3],          r,        0x0 */
            uint32_t tzc_glb_swrst_s24_lock : 1; /* [    4],          r,        0x0 */
            uint32_t tzc_glb_swrst_s25_lock : 1; /* [    5],          r,        0x0 */
            uint32_t tzc_glb_swrst_s26_lock : 1; /* [    6],          r,        0x0 */
            uint32_t tzc_glb_swrst_s27_lock : 1; /* [    7],          r,        0x0 */
            uint32_t tzc_glb_swrst_s28_lock : 1; /* [    8],          r,        0x0 */
            uint32_t tzc_glb_swrst_s29_lock : 1; /* [    9],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2a_lock : 1; /* [   10],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2b_lock : 1; /* [   11],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2c_lock : 1; /* [   12],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2d_lock : 1; /* [   13],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2e_lock : 1; /* [   14],          r,        0x0 */
            uint32_t tzc_glb_swrst_s2f_lock : 1; /* [   15],          r,        0x0 */
            uint32_t tzc_glb_swrst_s10_lock : 1; /* [   16],          r,        0x0 */
            uint32_t tzc_glb_swrst_s11_lock : 1; /* [   17],          r,        0x0 */
            uint32_t tzc_glb_swrst_s12_lock : 1; /* [   18],          r,        0x0 */
            uint32_t tzc_glb_swrst_s13_lock : 1; /* [   19],          r,        0x0 */
            uint32_t tzc_glb_swrst_s14_lock : 1; /* [   20],          r,        0x0 */
            uint32_t tzc_glb_swrst_s15_lock : 1; /* [   21],          r,        0x0 */
            uint32_t tzc_glb_swrst_s16_lock : 1; /* [   22],          r,        0x0 */
            uint32_t tzc_glb_swrst_s17_lock : 1; /* [   23],          r,        0x0 */
            uint32_t tzc_glb_swrst_s18_lock : 1; /* [   24],          r,        0x0 */
            uint32_t tzc_glb_swrst_s19_lock : 1; /* [   25],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1a_lock : 1; /* [   26],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1b_lock : 1; /* [   27],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1c_lock : 1; /* [   28],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1d_lock : 1; /* [   29],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1e_lock : 1; /* [   30],          r,        0x0 */
            uint32_t tzc_glb_swrst_s1f_lock : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_glb_ctrl_1;

    /* 0xF08 : tzc_glb_ctrl_2 */
    union {
        struct
        {
            uint32_t tzc_glb_gpio_0_lock  : 1; /* [    0],          r,        0x0 */
            uint32_t tzc_glb_gpio_1_lock  : 1; /* [    1],          r,        0x0 */
            uint32_t tzc_glb_gpio_2_lock  : 1; /* [    2],          r,        0x0 */
            uint32_t tzc_glb_gpio_3_lock  : 1; /* [    3],          r,        0x0 */
            uint32_t tzc_glb_gpio_4_lock  : 1; /* [    4],          r,        0x0 */
            uint32_t tzc_glb_gpio_5_lock  : 1; /* [    5],          r,        0x0 */
            uint32_t tzc_glb_gpio_6_lock  : 1; /* [    6],          r,        0x0 */
            uint32_t tzc_glb_gpio_7_lock  : 1; /* [    7],          r,        0x0 */
            uint32_t tzc_glb_gpio_8_lock  : 1; /* [    8],          r,        0x0 */
            uint32_t tzc_glb_gpio_9_lock  : 1; /* [    9],          r,        0x0 */
            uint32_t tzc_glb_gpio_10_lock : 1; /* [   10],          r,        0x0 */
            uint32_t tzc_glb_gpio_11_lock : 1; /* [   11],          r,        0x0 */
            uint32_t tzc_glb_gpio_12_lock : 1; /* [   12],          r,        0x0 */
            uint32_t tzc_glb_gpio_13_lock : 1; /* [   13],          r,        0x0 */
            uint32_t tzc_glb_gpio_14_lock : 1; /* [   14],          r,        0x0 */
            uint32_t tzc_glb_gpio_15_lock : 1; /* [   15],          r,        0x0 */
            uint32_t tzc_glb_gpio_16_lock : 1; /* [   16],          r,        0x0 */
            uint32_t tzc_glb_gpio_17_lock : 1; /* [   17],          r,        0x0 */
            uint32_t tzc_glb_gpio_18_lock : 1; /* [   18],          r,        0x0 */
            uint32_t tzc_glb_gpio_19_lock : 1; /* [   19],          r,        0x0 */
            uint32_t tzc_glb_gpio_20_lock : 1; /* [   20],          r,        0x0 */
            uint32_t tzc_glb_gpio_21_lock : 1; /* [   21],          r,        0x0 */
            uint32_t tzc_glb_gpio_22_lock : 1; /* [   22],          r,        0x0 */
            uint32_t tzc_glb_gpio_23_lock : 1; /* [   23],          r,        0x0 */
            uint32_t tzc_glb_gpio_24_lock : 1; /* [   24],          r,        0x0 */
            uint32_t tzc_glb_gpio_25_lock : 1; /* [   25],          r,        0x0 */
            uint32_t tzc_glb_gpio_26_lock : 1; /* [   26],          r,        0x0 */
            uint32_t tzc_glb_gpio_27_lock : 1; /* [   27],          r,        0x0 */
            uint32_t tzc_glb_gpio_28_lock : 1; /* [   28],          r,        0x0 */
            uint32_t tzc_glb_gpio_29_lock : 1; /* [   29],          r,        0x0 */
            uint32_t tzc_glb_gpio_30_lock : 1; /* [   30],          r,        0x0 */
            uint32_t tzc_glb_gpio_31_lock : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_glb_ctrl_2;

    /* 0xF0C : tzc_glb_ctrl_3 */
    union {
        struct
        {
            uint32_t tzc_glb_gpio_32_lock : 1;  /* [    0],          r,        0x0 */
            uint32_t tzc_glb_gpio_33_lock : 1;  /* [    1],          r,        0x0 */
            uint32_t tzc_glb_gpio_34_lock : 1;  /* [    2],          r,        0x0 */
            uint32_t tzc_glb_gpio_35_lock : 1;  /* [    3],          r,        0x0 */
            uint32_t tzc_glb_gpio_36_lock : 1;  /* [    4],          r,        0x0 */
            uint32_t tzc_glb_gpio_37_lock : 1;  /* [    5],          r,        0x0 */
            uint32_t reserved_6_31        : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_glb_ctrl_3;
};

typedef volatile struct glb_reg glb_reg_t;

/*Following is reg patch*/

/* 0x0 : GPIO_CFGCTL */
#define GLB_GPIO_CFGCTL_OFFSET       (0x0)
#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
#define GLB_REG_GPIO_0_IE_POS        (0U)
#define GLB_REG_GPIO_0_IE_LEN        (1U)
#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
#define GLB_REG_GPIO_0_SMT_POS       (1U)
#define GLB_REG_GPIO_0_SMT_LEN       (1U)
#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
#define GLB_REG_GPIO_0_DRV_POS       (2U)
#define GLB_REG_GPIO_0_DRV_LEN       (2U)
#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
#define GLB_REG_GPIO_0_PU_POS        (4U)
#define GLB_REG_GPIO_0_PU_LEN        (1U)
#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
#define GLB_REG_GPIO_0_PD_POS        (5U)
#define GLB_REG_GPIO_0_PD_LEN        (1U)
#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
#define GLB_REG_GPIO_1_IE_POS        (16U)
#define GLB_REG_GPIO_1_IE_LEN        (1U)
#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
#define GLB_REG_GPIO_1_SMT_POS       (17U)
#define GLB_REG_GPIO_1_SMT_LEN       (1U)
#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
#define GLB_REG_GPIO_1_DRV_POS       (18U)
#define GLB_REG_GPIO_1_DRV_LEN       (2U)
#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
#define GLB_REG_GPIO_1_PU_POS        (20U)
#define GLB_REG_GPIO_1_PU_LEN        (1U)
#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
#define GLB_REG_GPIO_1_PD_POS        (21U)
#define GLB_REG_GPIO_1_PD_LEN        (1U)
#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))

struct glb_gpio_reg {
    /* 0x0 : GPIO_CFGCTL */
    union {
        struct
        {
            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } GPIO_CFGCTL;
};

typedef volatile struct glb_gpio_reg glb_gpio_reg_t;

#define GLB_GPIO_OFFSET           0x100
#define GLB_GPIO_INPUT_OFFSET     0x180
#define GLB_GPIO_OUTPUT_OFFSET    0x188
#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190

#endif /* __GLB_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/gpip_reg.h
================================================
/**
  ******************************************************************************
  * @file    gpip_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __GPIP_REG_H__
#define __GPIP_REG_H__

#include "bl702.h"

/* 0x0 : gpadc_config */
#define GPIP_GPADC_CONFIG_OFFSET           (0x0)
#define GPIP_GPADC_DMA_EN                  GPIP_GPADC_DMA_EN
#define GPIP_GPADC_DMA_EN_POS              (0U)
#define GPIP_GPADC_DMA_EN_LEN              (1U)
#define GPIP_GPADC_DMA_EN_MSK              (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
#define GPIP_GPADC_DMA_EN_UMSK             (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
#define GPIP_GPADC_FIFO_CLR                GPIP_GPADC_FIFO_CLR
#define GPIP_GPADC_FIFO_CLR_POS            (1U)
#define GPIP_GPADC_FIFO_CLR_LEN            (1U)
#define GPIP_GPADC_FIFO_CLR_MSK            (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
#define GPIP_GPADC_FIFO_CLR_UMSK           (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
#define GPIP_GPADC_FIFO_NE                 GPIP_GPADC_FIFO_NE
#define GPIP_GPADC_FIFO_NE_POS             (2U)
#define GPIP_GPADC_FIFO_NE_LEN             (1U)
#define GPIP_GPADC_FIFO_NE_MSK             (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
#define GPIP_GPADC_FIFO_NE_UMSK            (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
#define GPIP_GPADC_FIFO_FULL               GPIP_GPADC_FIFO_FULL
#define GPIP_GPADC_FIFO_FULL_POS           (3U)
#define GPIP_GPADC_FIFO_FULL_LEN           (1U)
#define GPIP_GPADC_FIFO_FULL_MSK           (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
#define GPIP_GPADC_FIFO_FULL_UMSK          (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
#define GPIP_GPADC_RDY                     GPIP_GPADC_RDY
#define GPIP_GPADC_RDY_POS                 (4U)
#define GPIP_GPADC_RDY_LEN                 (1U)
#define GPIP_GPADC_RDY_MSK                 (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
#define GPIP_GPADC_RDY_UMSK                (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
#define GPIP_GPADC_FIFO_OVERRUN            GPIP_GPADC_FIFO_OVERRUN
#define GPIP_GPADC_FIFO_OVERRUN_POS        (5U)
#define GPIP_GPADC_FIFO_OVERRUN_LEN        (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MSK        (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
#define GPIP_GPADC_FIFO_OVERRUN_UMSK       (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
#define GPIP_GPADC_FIFO_UNDERRUN           GPIP_GPADC_FIFO_UNDERRUN
#define GPIP_GPADC_FIFO_UNDERRUN_POS       (6U)
#define GPIP_GPADC_FIFO_UNDERRUN_LEN       (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MSK       (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_UMSK      (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
#define GPIP_GPADC_FIFO_RDY                GPIP_GPADC_FIFO_RDY
#define GPIP_GPADC_FIFO_RDY_POS            (7U)
#define GPIP_GPADC_FIFO_RDY_LEN            (1U)
#define GPIP_GPADC_FIFO_RDY_MSK            (((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS)
#define GPIP_GPADC_FIFO_RDY_UMSK           (~(((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS))
#define GPIP_GPADC_RDY_CLR                 GPIP_GPADC_RDY_CLR
#define GPIP_GPADC_RDY_CLR_POS             (8U)
#define GPIP_GPADC_RDY_CLR_LEN             (1U)
#define GPIP_GPADC_RDY_CLR_MSK             (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
#define GPIP_GPADC_RDY_CLR_UMSK            (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
#define GPIP_GPADC_FIFO_OVERRUN_CLR        GPIP_GPADC_FIFO_OVERRUN_CLR
#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS    (9U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN    (1U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK    (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK   (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_CLR       GPIP_GPADC_FIFO_UNDERRUN_CLR
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS   (10U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN   (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK   (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK  (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
#define GPIP_GPADC_RDY_MASK                GPIP_GPADC_RDY_MASK
#define GPIP_GPADC_RDY_MASK_POS            (12U)
#define GPIP_GPADC_RDY_MASK_LEN            (1U)
#define GPIP_GPADC_RDY_MASK_MSK            (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
#define GPIP_GPADC_RDY_MASK_UMSK           (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_OVERRUN_MASK       GPIP_GPADC_FIFO_OVERRUN_MASK
#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS   (13U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN   (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK   (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK  (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_MASK      GPIP_GPADC_FIFO_UNDERRUN_MASK
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS  (14U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN  (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK  (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_RDY_MASK           GPIP_GPADC_FIFO_RDY_MASK
#define GPIP_GPADC_FIFO_RDY_MASK_POS       (15U)
#define GPIP_GPADC_FIFO_RDY_MASK_LEN       (1U)
#define GPIP_GPADC_FIFO_RDY_MASK_MSK       (((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS)
#define GPIP_GPADC_FIFO_RDY_MASK_UMSK      (~(((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_DATA_COUNT         GPIP_GPADC_FIFO_DATA_COUNT
#define GPIP_GPADC_FIFO_DATA_COUNT_POS     (16U)
#define GPIP_GPADC_FIFO_DATA_COUNT_LEN     (6U)
#define GPIP_GPADC_FIFO_DATA_COUNT_MSK     (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK    (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
#define GPIP_GPADC_FIFO_THL                GPIP_GPADC_FIFO_THL
#define GPIP_GPADC_FIFO_THL_POS            (22U)
#define GPIP_GPADC_FIFO_THL_LEN            (2U)
#define GPIP_GPADC_FIFO_THL_MSK            (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
#define GPIP_GPADC_FIFO_THL_UMSK           (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))

/* 0x4 : gpadc_dma_rdata */
#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
#define GPIP_GPADC_DMA_RDATA        GPIP_GPADC_DMA_RDATA
#define GPIP_GPADC_DMA_RDATA_POS    (0U)
#define GPIP_GPADC_DMA_RDATA_LEN    (26U)
#define GPIP_GPADC_DMA_RDATA_MSK    (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
#define GPIP_GPADC_DMA_RDATA_UMSK   (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))

/* 0x40 : gpdac_config */
#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
#define GPIP_GPDAC_EN            GPIP_GPDAC_EN
#define GPIP_GPDAC_EN_POS        (0U)
#define GPIP_GPDAC_EN_LEN        (1U)
#define GPIP_GPDAC_EN_MSK        (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
#define GPIP_GPDAC_EN_UMSK       (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
#define GPIP_GPDAC_EN2           GPIP_GPDAC_EN2
#define GPIP_GPDAC_EN2_POS       (1U)
#define GPIP_GPDAC_EN2_LEN       (1U)
#define GPIP_GPDAC_EN2_MSK       (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)
#define GPIP_GPDAC_EN2_UMSK      (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS))
#define GPIP_DSM_MODE            GPIP_DSM_MODE
#define GPIP_DSM_MODE_POS        (4U)
#define GPIP_DSM_MODE_LEN        (2U)
#define GPIP_DSM_MODE_MSK        (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)
#define GPIP_DSM_MODE_UMSK       (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS))
#define GPIP_GPDAC_MODE          GPIP_GPDAC_MODE
#define GPIP_GPDAC_MODE_POS      (8U)
#define GPIP_GPDAC_MODE_LEN      (3U)
#define GPIP_GPDAC_MODE_MSK      (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
#define GPIP_GPDAC_MODE_UMSK     (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
#define GPIP_GPDAC_CH_A_SEL      GPIP_GPDAC_CH_A_SEL
#define GPIP_GPDAC_CH_A_SEL_POS  (16U)
#define GPIP_GPDAC_CH_A_SEL_LEN  (4U)
#define GPIP_GPDAC_CH_A_SEL_MSK  (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
#define GPIP_GPDAC_CH_B_SEL      GPIP_GPDAC_CH_B_SEL
#define GPIP_GPDAC_CH_B_SEL_POS  (20U)
#define GPIP_GPDAC_CH_B_SEL_LEN  (4U)
#define GPIP_GPDAC_CH_B_SEL_MSK  (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))

/* 0x44 : gpdac_dma_config */
#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
#define GPIP_GPDAC_DMA_TX_EN         GPIP_GPDAC_DMA_TX_EN
#define GPIP_GPDAC_DMA_TX_EN_POS     (0U)
#define GPIP_GPDAC_DMA_TX_EN_LEN     (1U)
#define GPIP_GPDAC_DMA_TX_EN_MSK     (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
#define GPIP_GPDAC_DMA_TX_EN_UMSK    (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
#define GPIP_GPDAC_DMA_FORMAT        GPIP_GPDAC_DMA_FORMAT
#define GPIP_GPDAC_DMA_FORMAT_POS    (4U)
#define GPIP_GPDAC_DMA_FORMAT_LEN    (2U)
#define GPIP_GPDAC_DMA_FORMAT_MSK    (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
#define GPIP_GPDAC_DMA_FORMAT_UMSK   (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))

/* 0x48 : gpdac_dma_wdata */
#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
#define GPIP_GPDAC_DMA_WDATA        GPIP_GPDAC_DMA_WDATA
#define GPIP_GPDAC_DMA_WDATA_POS    (0U)
#define GPIP_GPDAC_DMA_WDATA_LEN    (32U)
#define GPIP_GPDAC_DMA_WDATA_MSK    (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
#define GPIP_GPDAC_DMA_WDATA_UMSK   (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))

/* 0x4C : gpdac_tx_fifo_status */
#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
#define GPIP_TX_FIFO_EMPTY               GPIP_TX_FIFO_EMPTY
#define GPIP_TX_FIFO_EMPTY_POS           (0U)
#define GPIP_TX_FIFO_EMPTY_LEN           (1U)
#define GPIP_TX_FIFO_EMPTY_MSK           (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
#define GPIP_TX_FIFO_EMPTY_UMSK          (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
#define GPIP_TX_FIFO_FULL                GPIP_TX_FIFO_FULL
#define GPIP_TX_FIFO_FULL_POS            (1U)
#define GPIP_TX_FIFO_FULL_LEN            (1U)
#define GPIP_TX_FIFO_FULL_MSK            (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
#define GPIP_TX_FIFO_FULL_UMSK           (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
#define GPIP_TX_CS                       GPIP_TX_CS
#define GPIP_TX_CS_POS                   (2U)
#define GPIP_TX_CS_LEN                   (2U)
#define GPIP_TX_CS_MSK                   (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
#define GPIP_TX_CS_UMSK                  (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
#define GPIP_TXFIFORDPTR                 GPIP_TXFIFORDPTR
#define GPIP_TXFIFORDPTR_POS             (4U)
#define GPIP_TXFIFORDPTR_LEN             (3U)
#define GPIP_TXFIFORDPTR_MSK             (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
#define GPIP_TXFIFORDPTR_UMSK            (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
#define GPIP_TXFIFOWRPTR                 GPIP_TXFIFOWRPTR
#define GPIP_TXFIFOWRPTR_POS             (8U)
#define GPIP_TXFIFOWRPTR_LEN             (2U)
#define GPIP_TXFIFOWRPTR_MSK             (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
#define GPIP_TXFIFOWRPTR_UMSK            (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))

struct gpip_reg {
    /* 0x0 : gpadc_config */
    union {
        struct
        {
            uint32_t gpadc_dma_en             : 1; /* [    0],        r/w,        0x0 */
            uint32_t gpadc_fifo_clr           : 1; /* [    1],        w1c,        0x0 */
            uint32_t gpadc_fifo_ne            : 1; /* [    2],          r,        0x0 */
            uint32_t gpadc_fifo_full          : 1; /* [    3],          r,        0x0 */
            uint32_t gpadc_rdy                : 1; /* [    4],          r,        0x0 */
            uint32_t gpadc_fifo_overrun       : 1; /* [    5],          r,        0x0 */
            uint32_t gpadc_fifo_underrun      : 1; /* [    6],          r,        0x0 */
            uint32_t gpadc_fifo_rdy           : 1; /* [    7],          r,        0x0 */
            uint32_t gpadc_rdy_clr            : 1; /* [    8],        w1c,        0x0 */
            uint32_t gpadc_fifo_overrun_clr   : 1; /* [    9],        w1c,        0x0 */
            uint32_t gpadc_fifo_underrun_clr  : 1; /* [   10],        w1c,        0x0 */
            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
            uint32_t gpadc_rdy_mask           : 1; /* [   12],        r/w,        0x0 */
            uint32_t gpadc_fifo_overrun_mask  : 1; /* [   13],        r/w,        0x0 */
            uint32_t gpadc_fifo_underrun_mask : 1; /* [   14],        r/w,        0x0 */
            uint32_t gpadc_fifo_rdy_mask      : 1; /* [   15],        r/w,        0x1 */
            uint32_t gpadc_fifo_data_count    : 6; /* [21:16],          r,        0x0 */
            uint32_t gpadc_fifo_thl           : 2; /* [23:22],        r/w,        0x0 */
            uint32_t rsvd_31_24               : 8; /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_config;

    /* 0x4 : gpadc_dma_rdata */
    union {
        struct
        {
            uint32_t gpadc_dma_rdata : 26; /* [25: 0],          r,        0x0 */
            uint32_t rsvd_31_26      : 6;  /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpadc_dma_rdata;

    /* 0x8  reserved */
    uint8_t RESERVED0x8[56];

    /* 0x40 : gpdac_config */
    union {
        struct
        {
            uint32_t gpdac_en       : 1; /* [    0],        r/w,        0x0 */
            uint32_t gpdac_en2      : 1; /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_3   : 2; /* [ 3: 2],       rsvd,        0x0 */
            uint32_t dsm_mode       : 2; /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6_7   : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t gpdac_mode     : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reserved_11_15 : 5; /* [15:11],       rsvd,        0x0 */
            uint32_t gpdac_ch_a_sel : 4; /* [19:16],        r/w,        0x0 */
            uint32_t gpdac_ch_b_sel : 4; /* [23:20],        r/w,        0x0 */
            uint32_t rsvd_31_24     : 8; /* [31:24],       rsvd,        0xd */
        } BF;
        uint32_t WORD;
    } gpdac_config;

    /* 0x44 : gpdac_dma_config */
    union {
        struct
        {
            uint32_t gpdac_dma_tx_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t gpdac_dma_format : 2;  /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6_31    : 26; /* [31: 6],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpdac_dma_config;

    /* 0x48 : gpdac_dma_wdata */
    union {
        struct
        {
            uint32_t gpdac_dma_wdata : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } gpdac_dma_wdata;

    /* 0x4C : gpdac_tx_fifo_status */
    union {
        struct
        {
            uint32_t tx_fifo_empty  : 1;  /* [    0],          r,        0x0 */
            uint32_t tx_fifo_full   : 1;  /* [    1],          r,        0x0 */
            uint32_t tx_cs          : 2;  /* [ 3: 2],          r,        0x0 */
            uint32_t TxFifoRdPtr    : 3;  /* [ 6: 4],          r,        0x4 */
            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t TxFifoWrPtr    : 2;  /* [ 9: 8],          r,        0x0 */
            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } gpdac_tx_fifo_status;
};

typedef volatile struct gpip_reg gpip_reg_t;

#endif /* __GPIP_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/hbn_reg.h
================================================
/**
  ******************************************************************************
  * @file    hbn_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __HBN_REG_H__
#define __HBN_REG_H__

#include "bl702.h"

/* 0x0 : HBN_CTL */
#define HBN_CTL_OFFSET                (0x0)
#define HBN_RTC_CTL                   HBN_RTC_CTL
#define HBN_RTC_CTL_POS               (0U)
#define HBN_RTC_CTL_LEN               (7U)
#define HBN_RTC_CTL_MSK               (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
#define HBN_RTC_CTL_UMSK              (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
#define HBN_MODE                      HBN_MODE
#define HBN_MODE_POS                  (7U)
#define HBN_MODE_LEN                  (1U)
#define HBN_MODE_MSK                  (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
#define HBN_MODE_UMSK                 (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
#define HBN_TRAP_MODE                 HBN_TRAP_MODE
#define HBN_TRAP_MODE_POS             (8U)
#define HBN_TRAP_MODE_LEN             (1U)
#define HBN_TRAP_MODE_MSK             (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
#define HBN_TRAP_MODE_UMSK            (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
#define HBN_PWRDN_HBN_CORE            HBN_PWRDN_HBN_CORE
#define HBN_PWRDN_HBN_CORE_POS        (9U)
#define HBN_PWRDN_HBN_CORE_LEN        (1U)
#define HBN_PWRDN_HBN_CORE_MSK        (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
#define HBN_PWRDN_HBN_CORE_UMSK       (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
#define HBN_PWRDN_HBN_RTC             HBN_PWRDN_HBN_RTC
#define HBN_PWRDN_HBN_RTC_POS         (11U)
#define HBN_PWRDN_HBN_RTC_LEN         (1U)
#define HBN_PWRDN_HBN_RTC_MSK         (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
#define HBN_PWRDN_HBN_RTC_UMSK        (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
#define HBN_SW_RST                    HBN_SW_RST
#define HBN_SW_RST_POS                (12U)
#define HBN_SW_RST_LEN                (1U)
#define HBN_SW_RST_MSK                (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
#define HBN_SW_RST_UMSK               (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
#define HBN_DIS_PWR_OFF_LDO11         HBN_DIS_PWR_OFF_LDO11
#define HBN_DIS_PWR_OFF_LDO11_POS     (13U)
#define HBN_DIS_PWR_OFF_LDO11_LEN     (1U)
#define HBN_DIS_PWR_OFF_LDO11_MSK     (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
#define HBN_DIS_PWR_OFF_LDO11_UMSK    (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
#define HBN_DIS_PWR_OFF_LDO11_RT      HBN_DIS_PWR_OFF_LDO11_RT
#define HBN_DIS_PWR_OFF_LDO11_RT_POS  (14U)
#define HBN_DIS_PWR_OFF_LDO11_RT_LEN  (1U)
#define HBN_DIS_PWR_OFF_LDO11_RT_MSK  (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
#define HBN_LDO11_RT_VOUT_SEL         HBN_LDO11_RT_VOUT_SEL
#define HBN_LDO11_RT_VOUT_SEL_POS     (15U)
#define HBN_LDO11_RT_VOUT_SEL_LEN     (4U)
#define HBN_LDO11_RT_VOUT_SEL_MSK     (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
#define HBN_LDO11_RT_VOUT_SEL_UMSK    (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
#define HBN_LDO11_AON_VOUT_SEL        HBN_LDO11_AON_VOUT_SEL
#define HBN_LDO11_AON_VOUT_SEL_POS    (19U)
#define HBN_LDO11_AON_VOUT_SEL_LEN    (4U)
#define HBN_LDO11_AON_VOUT_SEL_MSK    (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
#define HBN_LDO11_AON_VOUT_SEL_UMSK   (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
#define HBN_PU_DCDC18_AON             HBN_PU_DCDC18_AON
#define HBN_PU_DCDC18_AON_POS         (23U)
#define HBN_PU_DCDC18_AON_LEN         (1U)
#define HBN_PU_DCDC18_AON_MSK         (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
#define HBN_PU_DCDC18_AON_UMSK        (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
#define HBN_RTC_DLY_OPTION            HBN_RTC_DLY_OPTION
#define HBN_RTC_DLY_OPTION_POS        (24U)
#define HBN_RTC_DLY_OPTION_LEN        (1U)
#define HBN_RTC_DLY_OPTION_MSK        (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
#define HBN_RTC_DLY_OPTION_UMSK       (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
#define HBN_PWR_ON_OPTION             HBN_PWR_ON_OPTION
#define HBN_PWR_ON_OPTION_POS         (25U)
#define HBN_PWR_ON_OPTION_LEN         (1U)
#define HBN_PWR_ON_OPTION_MSK         (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
#define HBN_PWR_ON_OPTION_UMSK        (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
#define HBN_SRAM_SLP_OPTION           HBN_SRAM_SLP_OPTION
#define HBN_SRAM_SLP_OPTION_POS       (26U)
#define HBN_SRAM_SLP_OPTION_LEN       (1U)
#define HBN_SRAM_SLP_OPTION_MSK       (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
#define HBN_SRAM_SLP_OPTION_UMSK      (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
#define HBN_SRAM_SLP                  HBN_SRAM_SLP
#define HBN_SRAM_SLP_POS              (27U)
#define HBN_SRAM_SLP_LEN              (1U)
#define HBN_SRAM_SLP_MSK              (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
#define HBN_SRAM_SLP_UMSK             (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
#define HBN_STATE                     HBN_STATE
#define HBN_STATE_POS                 (28U)
#define HBN_STATE_LEN                 (4U)
#define HBN_STATE_MSK                 (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
#define HBN_STATE_UMSK                (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))

/* 0x4 : HBN_TIME_L */
#define HBN_TIME_L_OFFSET (0x4)
#define HBN_TIME_L        HBN_TIME_L
#define HBN_TIME_L_POS    (0U)
#define HBN_TIME_L_LEN    (32U)
#define HBN_TIME_L_MSK    (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
#define HBN_TIME_L_UMSK   (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))

/* 0x8 : HBN_TIME_H */
#define HBN_TIME_H_OFFSET (0x8)
#define HBN_TIME_H        HBN_TIME_H
#define HBN_TIME_H_POS    (0U)
#define HBN_TIME_H_LEN    (8U)
#define HBN_TIME_H_MSK    (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
#define HBN_TIME_H_UMSK   (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))

/* 0xC : RTC_TIME_L */
#define HBN_RTC_TIME_L_OFFSET     (0xC)
#define HBN_RTC_TIME_LATCH_L      HBN_RTC_TIME_LATCH_L
#define HBN_RTC_TIME_LATCH_L_POS  (0U)
#define HBN_RTC_TIME_LATCH_L_LEN  (32U)
#define HBN_RTC_TIME_LATCH_L_MSK  (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))

/* 0x10 : RTC_TIME_H */
#define HBN_RTC_TIME_H_OFFSET     (0x10)
#define HBN_RTC_TIME_LATCH_H      HBN_RTC_TIME_LATCH_H
#define HBN_RTC_TIME_LATCH_H_POS  (0U)
#define HBN_RTC_TIME_LATCH_H_LEN  (8U)
#define HBN_RTC_TIME_LATCH_H_MSK  (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
#define HBN_RTC_TIME_LATCH        HBN_RTC_TIME_LATCH
#define HBN_RTC_TIME_LATCH_POS    (31U)
#define HBN_RTC_TIME_LATCH_LEN    (1U)
#define HBN_RTC_TIME_LATCH_MSK    (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
#define HBN_RTC_TIME_LATCH_UMSK   (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))

/* 0x14 : HBN_IRQ_MODE */
#define HBN_IRQ_MODE_OFFSET         (0x14)
#define HBN_PIN_WAKEUP_MODE         HBN_PIN_WAKEUP_MODE
#define HBN_PIN_WAKEUP_MODE_POS     (0U)
#define HBN_PIN_WAKEUP_MODE_LEN     (3U)
#define HBN_PIN_WAKEUP_MODE_MSK     (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
#define HBN_PIN_WAKEUP_MODE_UMSK    (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
#define HBN_PIN_WAKEUP_MASK         HBN_PIN_WAKEUP_MASK
#define HBN_PIN_WAKEUP_MASK_POS     (3U)
#define HBN_PIN_WAKEUP_MASK_LEN     (5U)
#define HBN_PIN_WAKEUP_MASK_MSK     (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
#define HBN_PIN_WAKEUP_MASK_UMSK    (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
#define HBN_REG_AON_PAD_IE_SMT      HBN_REG_AON_PAD_IE_SMT
#define HBN_REG_AON_PAD_IE_SMT_POS  (8U)
#define HBN_REG_AON_PAD_IE_SMT_LEN  (5U)
#define HBN_REG_AON_PAD_IE_SMT_MSK  (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
#define HBN_REG_EN_HW_PU_PD         HBN_REG_EN_HW_PU_PD
#define HBN_REG_EN_HW_PU_PD_POS     (16U)
#define HBN_REG_EN_HW_PU_PD_LEN     (1U)
#define HBN_REG_EN_HW_PU_PD_MSK     (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
#define HBN_REG_EN_HW_PU_PD_UMSK    (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
#define HBN_IRQ_BOR_EN              HBN_IRQ_BOR_EN
#define HBN_IRQ_BOR_EN_POS          (18U)
#define HBN_IRQ_BOR_EN_LEN          (1U)
#define HBN_IRQ_BOR_EN_MSK          (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
#define HBN_IRQ_BOR_EN_UMSK         (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
#define HBN_IRQ_ACOMP0_EN           HBN_IRQ_ACOMP0_EN
#define HBN_IRQ_ACOMP0_EN_POS       (20U)
#define HBN_IRQ_ACOMP0_EN_LEN       (2U)
#define HBN_IRQ_ACOMP0_EN_MSK       (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
#define HBN_IRQ_ACOMP0_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
#define HBN_IRQ_ACOMP1_EN           HBN_IRQ_ACOMP1_EN
#define HBN_IRQ_ACOMP1_EN_POS       (22U)
#define HBN_IRQ_ACOMP1_EN_LEN       (2U)
#define HBN_IRQ_ACOMP1_EN_MSK       (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
#define HBN_IRQ_ACOMP1_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
#define HBN_PIN_WAKEUP_SEL          HBN_PIN_WAKEUP_SEL
#define HBN_PIN_WAKEUP_SEL_POS      (24U)
#define HBN_PIN_WAKEUP_SEL_LEN      (3U)
#define HBN_PIN_WAKEUP_SEL_MSK      (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
#define HBN_PIN_WAKEUP_SEL_UMSK     (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
#define HBN_PIN_WAKEUP_EN           HBN_PIN_WAKEUP_EN
#define HBN_PIN_WAKEUP_EN_POS       (27U)
#define HBN_PIN_WAKEUP_EN_LEN       (1U)
#define HBN_PIN_WAKEUP_EN_MSK       (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
#define HBN_PIN_WAKEUP_EN_UMSK      (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))

/* 0x18 : HBN_IRQ_STAT */
#define HBN_IRQ_STAT_OFFSET (0x18)
#define HBN_IRQ_STAT        HBN_IRQ_STAT
#define HBN_IRQ_STAT_POS    (0U)
#define HBN_IRQ_STAT_LEN    (32U)
#define HBN_IRQ_STAT_MSK    (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
#define HBN_IRQ_STAT_UMSK   (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))

/* 0x1C : HBN_IRQ_CLR */
#define HBN_IRQ_CLR_OFFSET (0x1C)
#define HBN_IRQ_CLR        HBN_IRQ_CLR
#define HBN_IRQ_CLR_POS    (0U)
#define HBN_IRQ_CLR_LEN    (32U)
#define HBN_IRQ_CLR_MSK    (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
#define HBN_IRQ_CLR_UMSK   (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))

/* 0x20 : HBN_PIR_CFG */
#define HBN_PIR_CFG_OFFSET    (0x20)
#define HBN_PIR_HPF_SEL       HBN_PIR_HPF_SEL
#define HBN_PIR_HPF_SEL_POS   (0U)
#define HBN_PIR_HPF_SEL_LEN   (2U)
#define HBN_PIR_HPF_SEL_MSK   (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
#define HBN_PIR_HPF_SEL_UMSK  (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
#define HBN_PIR_LPF_SEL       HBN_PIR_LPF_SEL
#define HBN_PIR_LPF_SEL_POS   (2U)
#define HBN_PIR_LPF_SEL_LEN   (1U)
#define HBN_PIR_LPF_SEL_MSK   (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
#define HBN_PIR_LPF_SEL_UMSK  (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
#define HBN_PIR_DIS           HBN_PIR_DIS
#define HBN_PIR_DIS_POS       (4U)
#define HBN_PIR_DIS_LEN       (2U)
#define HBN_PIR_DIS_MSK       (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
#define HBN_PIR_DIS_UMSK      (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
#define HBN_PIR_EN            HBN_PIR_EN
#define HBN_PIR_EN_POS        (7U)
#define HBN_PIR_EN_LEN        (1U)
#define HBN_PIR_EN_MSK        (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
#define HBN_PIR_EN_UMSK       (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
#define HBN_GPADC_CGEN        HBN_GPADC_CGEN
#define HBN_GPADC_CGEN_POS    (8U)
#define HBN_GPADC_CGEN_LEN    (1U)
#define HBN_GPADC_CGEN_MSK    (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
#define HBN_GPADC_CGEN_UMSK   (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
#define HBN_GPADC_NOSYNC      HBN_GPADC_NOSYNC
#define HBN_GPADC_NOSYNC_POS  (9U)
#define HBN_GPADC_NOSYNC_LEN  (1U)
#define HBN_GPADC_NOSYNC_MSK  (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))

/* 0x24 : HBN_PIR_VTH */
#define HBN_PIR_VTH_OFFSET (0x24)
#define HBN_PIR_VTH        HBN_PIR_VTH
#define HBN_PIR_VTH_POS    (0U)
#define HBN_PIR_VTH_LEN    (14U)
#define HBN_PIR_VTH_MSK    (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
#define HBN_PIR_VTH_UMSK   (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))

/* 0x28 : HBN_PIR_INTERVAL */
#define HBN_PIR_INTERVAL_OFFSET (0x28)
#define HBN_PIR_INTERVAL        HBN_PIR_INTERVAL
#define HBN_PIR_INTERVAL_POS    (0U)
#define HBN_PIR_INTERVAL_LEN    (12U)
#define HBN_PIR_INTERVAL_MSK    (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
#define HBN_PIR_INTERVAL_UMSK   (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))

/* 0x2C : HBN_MISC */
#define HBN_MISC_OFFSET             (0x2C)
#define HBN_BOR_SEL                 HBN_BOR_SEL
#define HBN_BOR_SEL_POS             (0U)
#define HBN_BOR_SEL_LEN             (1U)
#define HBN_BOR_SEL_MSK             (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
#define HBN_BOR_SEL_UMSK            (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
#define HBN_BOR_VTH                 HBN_BOR_VTH
#define HBN_BOR_VTH_POS             (1U)
#define HBN_BOR_VTH_LEN             (1U)
#define HBN_BOR_VTH_MSK             (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
#define HBN_BOR_VTH_UMSK            (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
#define HBN_PU_BOR                  HBN_PU_BOR
#define HBN_PU_BOR_POS              (2U)
#define HBN_PU_BOR_LEN              (1U)
#define HBN_PU_BOR_MSK              (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
#define HBN_PU_BOR_UMSK             (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
#define HBN_R_BOR_OUT               HBN_R_BOR_OUT
#define HBN_R_BOR_OUT_POS           (3U)
#define HBN_R_BOR_OUT_LEN           (1U)
#define HBN_R_BOR_OUT_MSK           (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
#define HBN_R_BOR_OUT_UMSK          (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
#define HBN_FLASH_PULLUP_AON        HBN_FLASH_PULLUP_AON
#define HBN_FLASH_PULLUP_AON_POS    (16U)
#define HBN_FLASH_PULLUP_AON_LEN    (6U)
#define HBN_FLASH_PULLUP_AON_MSK    (((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS)
#define HBN_FLASH_PULLUP_AON_UMSK   (~(((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS))
#define HBN_FLASH_PULLDOWN_AON      HBN_FLASH_PULLDOWN_AON
#define HBN_FLASH_PULLDOWN_AON_POS  (24U)
#define HBN_FLASH_PULLDOWN_AON_LEN  (6U)
#define HBN_FLASH_PULLDOWN_AON_MSK  (((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS)
#define HBN_FLASH_PULLDOWN_AON_UMSK (~(((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS))

/* 0x30 : HBN_GLB */
#define HBN_GLB_OFFSET                    (0x30)
#define HBN_ROOT_CLK_SEL                  HBN_ROOT_CLK_SEL
#define HBN_ROOT_CLK_SEL_POS              (0U)
#define HBN_ROOT_CLK_SEL_LEN              (2U)
#define HBN_ROOT_CLK_SEL_MSK              (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
#define HBN_ROOT_CLK_SEL_UMSK             (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
#define HBN_UART_CLK_SEL                  HBN_UART_CLK_SEL
#define HBN_UART_CLK_SEL_POS              (2U)
#define HBN_UART_CLK_SEL_LEN              (1U)
#define HBN_UART_CLK_SEL_MSK              (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
#define HBN_UART_CLK_SEL_UMSK             (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
#define HBN_F32K_SEL                      HBN_F32K_SEL
#define HBN_F32K_SEL_POS                  (3U)
#define HBN_F32K_SEL_LEN                  (2U)
#define HBN_F32K_SEL_MSK                  (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
#define HBN_F32K_SEL_UMSK                 (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
#define HBN_PU_RC32K                      HBN_PU_RC32K
#define HBN_PU_RC32K_POS                  (5U)
#define HBN_PU_RC32K_LEN                  (1U)
#define HBN_PU_RC32K_MSK                  (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
#define HBN_PU_RC32K_UMSK                 (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
#define HBN_LDO11_RT_ILOAD_SEL            HBN_LDO11_RT_ILOAD_SEL
#define HBN_LDO11_RT_ILOAD_SEL_POS        (6U)
#define HBN_LDO11_RT_ILOAD_SEL_LEN        (2U)
#define HBN_LDO11_RT_ILOAD_SEL_MSK        (((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS)
#define HBN_LDO11_RT_ILOAD_SEL_UMSK       (~(((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS))
#define HBN_RESET_EVENT                   HBN_RESET_EVENT
#define HBN_RESET_EVENT_POS               (8U)
#define HBN_RESET_EVENT_LEN               (5U)
#define HBN_RESET_EVENT_MSK               (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
#define HBN_RESET_EVENT_UMSK              (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
#define HBN_CLEAR_RESET_EVENT             HBN_CLEAR_RESET_EVENT
#define HBN_CLEAR_RESET_EVENT_POS         (13U)
#define HBN_CLEAR_RESET_EVENT_LEN         (1U)
#define HBN_CLEAR_RESET_EVENT_MSK         (((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS)
#define HBN_CLEAR_RESET_EVENT_UMSK        (~(((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS))
#define HBN_SW_LDO11SOC_VOUT_SEL_AON      HBN_SW_LDO11SOC_VOUT_SEL_AON
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS  (16U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN  (4U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK  (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
#define HBN_SW_LDO11_RT_VOUT_SEL          HBN_SW_LDO11_RT_VOUT_SEL
#define HBN_SW_LDO11_RT_VOUT_SEL_POS      (24U)
#define HBN_SW_LDO11_RT_VOUT_SEL_LEN      (4U)
#define HBN_SW_LDO11_RT_VOUT_SEL_MSK      (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK     (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
#define HBN_SW_LDO11_AON_VOUT_SEL         HBN_SW_LDO11_AON_VOUT_SEL
#define HBN_SW_LDO11_AON_VOUT_SEL_POS     (28U)
#define HBN_SW_LDO11_AON_VOUT_SEL_LEN     (4U)
#define HBN_SW_LDO11_AON_VOUT_SEL_MSK     (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK    (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))

/* 0x34 : HBN_SRAM */
#define HBN_SRAM_OFFSET      (0x34)
#define HBN_RETRAM_EMA       HBN_RETRAM_EMA
#define HBN_RETRAM_EMA_POS   (0U)
#define HBN_RETRAM_EMA_LEN   (3U)
#define HBN_RETRAM_EMA_MSK   (((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS)
#define HBN_RETRAM_EMA_UMSK  (~(((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS))
#define HBN_RETRAM_EMAW      HBN_RETRAM_EMAW
#define HBN_RETRAM_EMAW_POS  (3U)
#define HBN_RETRAM_EMAW_LEN  (2U)
#define HBN_RETRAM_EMAW_MSK  (((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS)
#define HBN_RETRAM_EMAW_UMSK (~(((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS))
#define HBN_RETRAM_RET       HBN_RETRAM_RET
#define HBN_RETRAM_RET_POS   (6U)
#define HBN_RETRAM_RET_LEN   (1U)
#define HBN_RETRAM_RET_MSK   (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
#define HBN_RETRAM_RET_UMSK  (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
#define HBN_RETRAM_SLP       HBN_RETRAM_SLP
#define HBN_RETRAM_SLP_POS   (7U)
#define HBN_RETRAM_SLP_LEN   (1U)
#define HBN_RETRAM_SLP_MSK   (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
#define HBN_RETRAM_SLP_UMSK  (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))

/* 0x100 : HBN_RSV0 */
#define HBN_RSV0_OFFSET (0x100)
#define HBN_RSV0        HBN_RSV0
#define HBN_RSV0_POS    (0U)
#define HBN_RSV0_LEN    (32U)
#define HBN_RSV0_MSK    (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
#define HBN_RSV0_UMSK   (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))

/* 0x104 : HBN_RSV1 */
#define HBN_RSV1_OFFSET (0x104)
#define HBN_RSV1        HBN_RSV1
#define HBN_RSV1_POS    (0U)
#define HBN_RSV1_LEN    (32U)
#define HBN_RSV1_MSK    (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
#define HBN_RSV1_UMSK   (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))

/* 0x108 : HBN_RSV2 */
#define HBN_RSV2_OFFSET (0x108)
#define HBN_RSV2        HBN_RSV2
#define HBN_RSV2_POS    (0U)
#define HBN_RSV2_LEN    (32U)
#define HBN_RSV2_MSK    (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
#define HBN_RSV2_UMSK   (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))

/* 0x10C : HBN_RSV3 */
#define HBN_RSV3_OFFSET (0x10C)
#define HBN_RSV3        HBN_RSV3
#define HBN_RSV3_POS    (0U)
#define HBN_RSV3_LEN    (32U)
#define HBN_RSV3_MSK    (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
#define HBN_RSV3_UMSK   (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))

/* 0x200 : rc32k_ctrl0 */
#define HBN_RC32K_CTRL0_OFFSET         (0x200)
#define HBN_RC32K_CAL_DONE             HBN_RC32K_CAL_DONE
#define HBN_RC32K_CAL_DONE_POS         (0U)
#define HBN_RC32K_CAL_DONE_LEN         (1U)
#define HBN_RC32K_CAL_DONE_MSK         (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
#define HBN_RC32K_CAL_DONE_UMSK        (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
#define HBN_RC32K_RDY                  HBN_RC32K_RDY
#define HBN_RC32K_RDY_POS              (1U)
#define HBN_RC32K_RDY_LEN              (1U)
#define HBN_RC32K_RDY_MSK              (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
#define HBN_RC32K_RDY_UMSK             (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
#define HBN_RC32K_CAL_INPROGRESS       HBN_RC32K_CAL_INPROGRESS
#define HBN_RC32K_CAL_INPROGRESS_POS   (2U)
#define HBN_RC32K_CAL_INPROGRESS_LEN   (1U)
#define HBN_RC32K_CAL_INPROGRESS_MSK   (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
#define HBN_RC32K_CAL_INPROGRESS_UMSK  (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
#define HBN_RC32K_CAL_DIV              HBN_RC32K_CAL_DIV
#define HBN_RC32K_CAL_DIV_POS          (3U)
#define HBN_RC32K_CAL_DIV_LEN          (2U)
#define HBN_RC32K_CAL_DIV_MSK          (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
#define HBN_RC32K_CAL_DIV_UMSK         (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
#define HBN_RC32K_CAL_PRECHARGE        HBN_RC32K_CAL_PRECHARGE
#define HBN_RC32K_CAL_PRECHARGE_POS    (5U)
#define HBN_RC32K_CAL_PRECHARGE_LEN    (1U)
#define HBN_RC32K_CAL_PRECHARGE_MSK    (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
#define HBN_RC32K_CAL_PRECHARGE_UMSK   (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
#define HBN_RC32K_DIG_CODE_FR_CAL      HBN_RC32K_DIG_CODE_FR_CAL
#define HBN_RC32K_DIG_CODE_FR_CAL_POS  (6U)
#define HBN_RC32K_DIG_CODE_FR_CAL_LEN  (10U)
#define HBN_RC32K_DIG_CODE_FR_CAL_MSK  (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
#define HBN_RC32K_VREF_DLY             HBN_RC32K_VREF_DLY
#define HBN_RC32K_VREF_DLY_POS         (16U)
#define HBN_RC32K_VREF_DLY_LEN         (2U)
#define HBN_RC32K_VREF_DLY_MSK         (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
#define HBN_RC32K_VREF_DLY_UMSK        (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
#define HBN_RC32K_ALLOW_CAL            HBN_RC32K_ALLOW_CAL
#define HBN_RC32K_ALLOW_CAL_POS        (18U)
#define HBN_RC32K_ALLOW_CAL_LEN        (1U)
#define HBN_RC32K_ALLOW_CAL_MSK        (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
#define HBN_RC32K_ALLOW_CAL_UMSK       (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
#define HBN_RC32K_EXT_CODE_EN          HBN_RC32K_EXT_CODE_EN
#define HBN_RC32K_EXT_CODE_EN_POS      (19U)
#define HBN_RC32K_EXT_CODE_EN_LEN      (1U)
#define HBN_RC32K_EXT_CODE_EN_MSK      (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
#define HBN_RC32K_EXT_CODE_EN_UMSK     (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
#define HBN_RC32K_CAL_EN               HBN_RC32K_CAL_EN
#define HBN_RC32K_CAL_EN_POS           (20U)
#define HBN_RC32K_CAL_EN_LEN           (1U)
#define HBN_RC32K_CAL_EN_MSK           (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
#define HBN_RC32K_CAL_EN_UMSK          (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
#define HBN_RC32K_CODE_FR_EXT          HBN_RC32K_CODE_FR_EXT
#define HBN_RC32K_CODE_FR_EXT_POS      (22U)
#define HBN_RC32K_CODE_FR_EXT_LEN      (10U)
#define HBN_RC32K_CODE_FR_EXT_MSK      (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
#define HBN_RC32K_CODE_FR_EXT_UMSK     (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))

/* 0x204 : xtal32k */
#define HBN_XTAL32K_OFFSET            (0x204)
#define HBN_XTAL32K_HIZ_EN            HBN_XTAL32K_HIZ_EN
#define HBN_XTAL32K_HIZ_EN_POS        (0U)
#define HBN_XTAL32K_HIZ_EN_LEN        (1U)
#define HBN_XTAL32K_HIZ_EN_MSK        (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
#define HBN_XTAL32K_HIZ_EN_UMSK       (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
#define HBN_XTAL32K_LOWV_EN           HBN_XTAL32K_LOWV_EN
#define HBN_XTAL32K_LOWV_EN_POS       (1U)
#define HBN_XTAL32K_LOWV_EN_LEN       (1U)
#define HBN_XTAL32K_LOWV_EN_MSK       (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)
#define HBN_XTAL32K_LOWV_EN_UMSK      (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS))
#define HBN_XTAL32K_EXT_SEL           HBN_XTAL32K_EXT_SEL
#define HBN_XTAL32K_EXT_SEL_POS       (2U)
#define HBN_XTAL32K_EXT_SEL_LEN       (1U)
#define HBN_XTAL32K_EXT_SEL_MSK       (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
#define HBN_XTAL32K_EXT_SEL_UMSK      (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
#define HBN_XTAL32K_AMP_CTRL          HBN_XTAL32K_AMP_CTRL
#define HBN_XTAL32K_AMP_CTRL_POS      (3U)
#define HBN_XTAL32K_AMP_CTRL_LEN      (2U)
#define HBN_XTAL32K_AMP_CTRL_MSK      (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
#define HBN_XTAL32K_AMP_CTRL_UMSK     (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
#define HBN_XTAL32K_REG               HBN_XTAL32K_REG
#define HBN_XTAL32K_REG_POS           (5U)
#define HBN_XTAL32K_REG_LEN           (2U)
#define HBN_XTAL32K_REG_MSK           (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
#define HBN_XTAL32K_REG_UMSK          (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
#define HBN_XTAL32K_OUTBUF_STRE       HBN_XTAL32K_OUTBUF_STRE
#define HBN_XTAL32K_OUTBUF_STRE_POS   (7U)
#define HBN_XTAL32K_OUTBUF_STRE_LEN   (1U)
#define HBN_XTAL32K_OUTBUF_STRE_MSK   (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
#define HBN_XTAL32K_OUTBUF_STRE_UMSK  (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
#define HBN_XTAL32K_OTF_SHORT         HBN_XTAL32K_OTF_SHORT
#define HBN_XTAL32K_OTF_SHORT_POS     (8U)
#define HBN_XTAL32K_OTF_SHORT_LEN     (1U)
#define HBN_XTAL32K_OTF_SHORT_MSK     (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
#define HBN_XTAL32K_OTF_SHORT_UMSK    (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
#define HBN_XTAL32K_INV_STRE          HBN_XTAL32K_INV_STRE
#define HBN_XTAL32K_INV_STRE_POS      (9U)
#define HBN_XTAL32K_INV_STRE_LEN      (2U)
#define HBN_XTAL32K_INV_STRE_MSK      (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
#define HBN_XTAL32K_INV_STRE_UMSK     (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
#define HBN_XTAL32K_CAPBANK           HBN_XTAL32K_CAPBANK
#define HBN_XTAL32K_CAPBANK_POS       (11U)
#define HBN_XTAL32K_CAPBANK_LEN       (6U)
#define HBN_XTAL32K_CAPBANK_MSK       (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
#define HBN_XTAL32K_CAPBANK_UMSK      (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
#define HBN_XTAL32K_AC_CAP_SHORT      HBN_XTAL32K_AC_CAP_SHORT
#define HBN_XTAL32K_AC_CAP_SHORT_POS  (17U)
#define HBN_XTAL32K_AC_CAP_SHORT_LEN  (1U)
#define HBN_XTAL32K_AC_CAP_SHORT_MSK  (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
#define HBN_PU_XTAL32K_BUF            HBN_PU_XTAL32K_BUF
#define HBN_PU_XTAL32K_BUF_POS        (18U)
#define HBN_PU_XTAL32K_BUF_LEN        (1U)
#define HBN_PU_XTAL32K_BUF_MSK        (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
#define HBN_PU_XTAL32K_BUF_UMSK       (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
#define HBN_PU_XTAL32K                HBN_PU_XTAL32K
#define HBN_PU_XTAL32K_POS            (19U)
#define HBN_PU_XTAL32K_LEN            (1U)
#define HBN_PU_XTAL32K_MSK            (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
#define HBN_PU_XTAL32K_UMSK           (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))

struct hbn_reg {
    /* 0x0 : HBN_CTL */
    union {
        struct
        {
            uint32_t rtc_ctl                  : 7; /* [ 6: 0],        r/w,        0x0 */
            uint32_t hbn_mode                 : 1; /* [    7],          w,        0x0 */
            uint32_t trap_mode                : 1; /* [    8],          r,        0x0 */
            uint32_t pwrdn_hbn_core           : 1; /* [    9],        r/w,        0x0 */
            uint32_t reserved_10              : 1; /* [   10],       rsvd,        0x0 */
            uint32_t pwrdn_hbn_rtc            : 1; /* [   11],        r/w,        0x0 */
            uint32_t sw_rst                   : 1; /* [   12],        r/w,        0x0 */
            uint32_t hbn_dis_pwr_off_ldo11    : 1; /* [   13],        r/w,        0x0 */
            uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [   14],        r/w,        0x0 */
            uint32_t hbn_ldo11_rt_vout_sel    : 4; /* [18:15],        r/w,        0xa */
            uint32_t hbn_ldo11_aon_vout_sel   : 4; /* [22:19],        r/w,        0xa */
            uint32_t pu_dcdc18_aon            : 1; /* [   23],        r/w,        0x1 */
            uint32_t rtc_dly_option           : 1; /* [   24],        r/w,        0x0 */
            uint32_t pwr_on_option            : 1; /* [   25],        r/w,        0x0 */
            uint32_t sram_slp_option          : 1; /* [   26],        r/w,        0x0 */
            uint32_t sram_slp                 : 1; /* [   27],          r,        0x0 */
            uint32_t hbn_state                : 4; /* [31:28],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_CTL;

    /* 0x4 : HBN_TIME_L */
    union {
        struct
        {
            uint32_t hbn_time_l : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_TIME_L;

    /* 0x8 : HBN_TIME_H */
    union {
        struct
        {
            uint32_t hbn_time_h    : 8;  /* [ 7: 0],        r/w,        0x0 */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_TIME_H;

    /* 0xC : RTC_TIME_L */
    union {
        struct
        {
            uint32_t rtc_time_latch_l : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } RTC_TIME_L;

    /* 0x10 : RTC_TIME_H */
    union {
        struct
        {
            uint32_t rtc_time_latch_h : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_30    : 23; /* [30: 8],       rsvd,        0x0 */
            uint32_t rtc_time_latch   : 1;  /* [   31],          w,        0x0 */
        } BF;
        uint32_t WORD;
    } RTC_TIME_H;

    /* 0x14 : HBN_IRQ_MODE */
    union {
        struct
        {
            uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0],        r/w,        0x5 */
            uint32_t hbn_pin_wakeup_mask : 5; /* [ 7: 3],        r/w,        0x0 */
            uint32_t reg_aon_pad_ie_smt  : 5; /* [12: 8],        r/w,       0x1f */
            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t reg_en_hw_pu_pd     : 1; /* [   16],        r/w,        0x1 */
            uint32_t reserved_17         : 1; /* [   17],       rsvd,        0x0 */
            uint32_t irq_bor_en          : 1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
            uint32_t irq_acomp0_en       : 2; /* [21:20],        r/w,        0x0 */
            uint32_t irq_acomp1_en       : 2; /* [23:22],        r/w,        0x0 */
            uint32_t pin_wakeup_sel      : 3; /* [26:24],        r/w,        0x3 */
            uint32_t pin_wakeup_en       : 1; /* [   27],        r/w,        0x0 */
            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_IRQ_MODE;

    /* 0x18 : HBN_IRQ_STAT */
    union {
        struct
        {
            uint32_t irq_stat : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_IRQ_STAT;

    /* 0x1C : HBN_IRQ_CLR */
    union {
        struct
        {
            uint32_t irq_clr : 32; /* [31: 0],          w,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_IRQ_CLR;

    /* 0x20 : HBN_PIR_CFG */
    union {
        struct
        {
            uint32_t pir_hpf_sel    : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pir_lpf_sel    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3     : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t pir_dis        : 2;  /* [ 5: 4],        r/w,        0x0 */
            uint32_t reserved_6     : 1;  /* [    6],       rsvd,        0x0 */
            uint32_t pir_en         : 1;  /* [    7],        r/w,        0x0 */
            uint32_t gpadc_cgen     : 1;  /* [    8],        r/w,        0x0 */
            uint32_t gpadc_nosync   : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_PIR_CFG;

    /* 0x24 : HBN_PIR_VTH */
    union {
        struct
        {
            uint32_t pir_vth        : 14; /* [13: 0],        r/w,      0x3ff */
            uint32_t reserved_14_31 : 18; /* [31:14],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_PIR_VTH;

    /* 0x28 : HBN_PIR_INTERVAL */
    union {
        struct
        {
            uint32_t pir_interval   : 12; /* [11: 0],        r/w,      0xa3d */
            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_PIR_INTERVAL;

    /* 0x2C : HBN_MISC */
    union {
        struct
        {
            uint32_t bor_sel                : 1;  /* [    0],        r/w,        0x0 */
            uint32_t bor_vth                : 1;  /* [    1],        r/w,        0x1 */
            uint32_t pu_bor                 : 1;  /* [    2],        r/w,        0x0 */
            uint32_t r_bor_out              : 1;  /* [    3],          r,        0x0 */
            uint32_t reserved_4_15          : 12; /* [15: 4],       rsvd,        0x0 */
            uint32_t hbn_flash_pullup_aon   : 6;  /* [21:16],        r/w,        0x0 */
            uint32_t reserved_22_23         : 2;  /* [23:22],       rsvd,        0x0 */
            uint32_t hbn_flash_pulldown_aon : 6;  /* [29:24],        r/w,        0x0 */
            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_MISC;

    /* 0x30 : HBN_GLB */
    union {
        struct
        {
            uint32_t hbn_root_clk_sel         : 2; /* [ 1: 0],        r/w,        0x0 */
            uint32_t hbn_uart_clk_sel         : 1; /* [    2],        r/w,        0x0 */
            uint32_t hbn_f32k_sel             : 2; /* [ 4: 3],        r/w,        0x0 */
            uint32_t hbn_pu_rc32k             : 1; /* [    5],        r/w,        0x1 */
            uint32_t ldo11_rt_iload_sel       : 2; /* [ 7: 6],        r/w,        0x1 */
            uint32_t hbn_reset_event          : 5; /* [12: 8],          r,        0x0 */
            uint32_t hbn_clear_reset_event    : 1; /* [   13],        r/w,        0x0 */
            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16],        r/w,        0xa */
            uint32_t reserved_20_23           : 4; /* [23:20],       rsvd,        0x0 */
            uint32_t sw_ldo11_rt_vout_sel     : 4; /* [27:24],        r/w,        0xa */
            uint32_t sw_ldo11_aon_vout_sel    : 4; /* [31:28],        r/w,        0xa */
        } BF;
        uint32_t WORD;
    } HBN_GLB;

    /* 0x34 : HBN_SRAM */
    union {
        struct
        {
            uint32_t retram_ema    : 3;  /* [ 2: 0],        r/w,        0x3 */
            uint32_t retram_emaw   : 2;  /* [ 4: 3],        r/w,        0x1 */
            uint32_t reserved_5    : 1;  /* [    5],       rsvd,        0x0 */
            uint32_t retram_ret    : 1;  /* [    6],        r/w,        0x0 */
            uint32_t retram_slp    : 1;  /* [    7],        r/w,        0x0 */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_SRAM;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[200];

    /* 0x100 : HBN_RSV0 */
    union {
        struct
        {
            uint32_t HBN_RSV0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_RSV0;

    /* 0x104 : HBN_RSV1 */
    union {
        struct
        {
            uint32_t HBN_RSV1 : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } HBN_RSV1;

    /* 0x108 : HBN_RSV2 */
    union {
        struct
        {
            uint32_t HBN_RSV2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } HBN_RSV2;

    /* 0x10C : HBN_RSV3 */
    union {
        struct
        {
            uint32_t HBN_RSV3 : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } HBN_RSV3;

    /* 0x110  reserved */
    uint8_t RESERVED0x110[240];

    /* 0x200 : rc32k_ctrl0 */
    union {
        struct
        {
            uint32_t rc32k_cal_done        : 1;  /* [    0],          r,        0x1 */
            uint32_t rc32k_rdy             : 1;  /* [    1],          r,        0x1 */
            uint32_t rc32k_cal_inprogress  : 1;  /* [    2],          r,        0x0 */
            uint32_t rc32k_cal_div         : 2;  /* [ 4: 3],        r/w,        0x3 */
            uint32_t rc32k_cal_precharge   : 1;  /* [    5],          r,        0x0 */
            uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6],          r,      0x200 */
            uint32_t rc32k_vref_dly        : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t rc32k_allow_cal       : 1;  /* [   18],        r/w,        0x0 */
            uint32_t rc32k_ext_code_en     : 1;  /* [   19],        r/w,        0x1 */
            uint32_t rc32k_cal_en          : 1;  /* [   20],        r/w,        0x0 */
            uint32_t reserved_21           : 1;  /* [   21],       rsvd,        0x0 */
            uint32_t rc32k_code_fr_ext     : 10; /* [31:22],        r/w,      0x12c */
        } BF;
        uint32_t WORD;
    } rc32k_ctrl0;

    /* 0x204 : xtal32k */
    union {
        struct
        {
            uint32_t xtal32k_hiz_en       : 1;  /* [    0],        r/w,        0x0 */
            uint32_t xtal32k_lowv_en      : 1;  /* [    1],        r/w,        0x0 */
            uint32_t xtal32k_ext_sel      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t xtal32k_amp_ctrl     : 2;  /* [ 4: 3],        r/w,        0x1 */
            uint32_t xtal32k_reg          : 2;  /* [ 6: 5],        r/w,        0x1 */
            uint32_t xtal32k_outbuf_stre  : 1;  /* [    7],        r/w,        0x0 */
            uint32_t xtal32k_otf_short    : 1;  /* [    8],        r/w,        0x0 */
            uint32_t xtal32k_inv_stre     : 2;  /* [10: 9],        r/w,        0x1 */
            uint32_t xtal32k_capbank      : 6;  /* [16:11],        r/w,       0x20 */
            uint32_t xtal32k_ac_cap_short : 1;  /* [   17],        r/w,        0x1 */
            uint32_t pu_xtal32k_buf       : 1;  /* [   18],        r/w,        0x1 */
            uint32_t pu_xtal32k           : 1;  /* [   19],        r/w,        0x1 */
            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } xtal32k;
};

typedef volatile struct hbn_reg hbn_reg_t;

#endif /* __HBN_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2c_reg.h
================================================
/**
  ******************************************************************************
  * @file    i2c_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __I2C_REG_H__
#define __I2C_REG_H__

#include "bl702.h"

/* 0x0 : i2c_config */
#define I2C_CONFIG_OFFSET           (0x0)
#define I2C_CR_I2C_M_EN             I2C_CR_I2C_M_EN
#define I2C_CR_I2C_M_EN_POS         (0U)
#define I2C_CR_I2C_M_EN_LEN         (1U)
#define I2C_CR_I2C_M_EN_MSK         (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)
#define I2C_CR_I2C_M_EN_UMSK        (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS))
#define I2C_CR_I2C_PKT_DIR          I2C_CR_I2C_PKT_DIR
#define I2C_CR_I2C_PKT_DIR_POS      (1U)
#define I2C_CR_I2C_PKT_DIR_LEN      (1U)
#define I2C_CR_I2C_PKT_DIR_MSK      (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)
#define I2C_CR_I2C_PKT_DIR_UMSK     (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS))
#define I2C_CR_I2C_DEG_EN           I2C_CR_I2C_DEG_EN
#define I2C_CR_I2C_DEG_EN_POS       (2U)
#define I2C_CR_I2C_DEG_EN_LEN       (1U)
#define I2C_CR_I2C_DEG_EN_MSK       (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)
#define I2C_CR_I2C_DEG_EN_UMSK      (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS))
#define I2C_CR_I2C_SCL_SYNC_EN      I2C_CR_I2C_SCL_SYNC_EN
#define I2C_CR_I2C_SCL_SYNC_EN_POS  (3U)
#define I2C_CR_I2C_SCL_SYNC_EN_LEN  (1U)
#define I2C_CR_I2C_SCL_SYNC_EN_MSK  (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)
#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_EN      I2C_CR_I2C_SUB_ADDR_EN
#define I2C_CR_I2C_SUB_ADDR_EN_POS  (4U)
#define I2C_CR_I2C_SUB_ADDR_EN_LEN  (1U)
#define I2C_CR_I2C_SUB_ADDR_EN_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)
#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_BC      I2C_CR_I2C_SUB_ADDR_BC
#define I2C_CR_I2C_SUB_ADDR_BC_POS  (5U)
#define I2C_CR_I2C_SUB_ADDR_BC_LEN  (2U)
#define I2C_CR_I2C_SUB_ADDR_BC_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)
#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS))
#define I2C_CR_I2C_SLV_ADDR         I2C_CR_I2C_SLV_ADDR
#define I2C_CR_I2C_SLV_ADDR_POS     (8U)
#define I2C_CR_I2C_SLV_ADDR_LEN     (7U)
#define I2C_CR_I2C_SLV_ADDR_MSK     (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)
#define I2C_CR_I2C_SLV_ADDR_UMSK    (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS))
#define I2C_CR_I2C_PKT_LEN          I2C_CR_I2C_PKT_LEN
#define I2C_CR_I2C_PKT_LEN_POS      (16U)
#define I2C_CR_I2C_PKT_LEN_LEN      (8U)
#define I2C_CR_I2C_PKT_LEN_MSK      (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)
#define I2C_CR_I2C_PKT_LEN_UMSK     (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS))
#define I2C_CR_I2C_DEG_CNT          I2C_CR_I2C_DEG_CNT
#define I2C_CR_I2C_DEG_CNT_POS      (28U)
#define I2C_CR_I2C_DEG_CNT_LEN      (4U)
#define I2C_CR_I2C_DEG_CNT_MSK      (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)
#define I2C_CR_I2C_DEG_CNT_UMSK     (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS))

/* 0x4 : i2c_int_sts */
#define I2C_INT_STS_OFFSET       (0x4)
#define I2C_END_INT              I2C_END_INT
#define I2C_END_INT_POS          (0U)
#define I2C_END_INT_LEN          (1U)
#define I2C_END_INT_MSK          (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)
#define I2C_END_INT_UMSK         (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS))
#define I2C_TXF_INT              I2C_TXF_INT
#define I2C_TXF_INT_POS          (1U)
#define I2C_TXF_INT_LEN          (1U)
#define I2C_TXF_INT_MSK          (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)
#define I2C_TXF_INT_UMSK         (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS))
#define I2C_RXF_INT              I2C_RXF_INT
#define I2C_RXF_INT_POS          (2U)
#define I2C_RXF_INT_LEN          (1U)
#define I2C_RXF_INT_MSK          (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)
#define I2C_RXF_INT_UMSK         (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS))
#define I2C_NAK_INT              I2C_NAK_INT
#define I2C_NAK_INT_POS          (3U)
#define I2C_NAK_INT_LEN          (1U)
#define I2C_NAK_INT_MSK          (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)
#define I2C_NAK_INT_UMSK         (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS))
#define I2C_ARB_INT              I2C_ARB_INT
#define I2C_ARB_INT_POS          (4U)
#define I2C_ARB_INT_LEN          (1U)
#define I2C_ARB_INT_MSK          (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)
#define I2C_ARB_INT_UMSK         (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS))
#define I2C_FER_INT              I2C_FER_INT
#define I2C_FER_INT_POS          (5U)
#define I2C_FER_INT_LEN          (1U)
#define I2C_FER_INT_MSK          (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)
#define I2C_FER_INT_UMSK         (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS))
#define I2C_CR_I2C_END_MASK      I2C_CR_I2C_END_MASK
#define I2C_CR_I2C_END_MASK_POS  (8U)
#define I2C_CR_I2C_END_MASK_LEN  (1U)
#define I2C_CR_I2C_END_MASK_MSK  (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)
#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS))
#define I2C_CR_I2C_TXF_MASK      I2C_CR_I2C_TXF_MASK
#define I2C_CR_I2C_TXF_MASK_POS  (9U)
#define I2C_CR_I2C_TXF_MASK_LEN  (1U)
#define I2C_CR_I2C_TXF_MASK_MSK  (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)
#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS))
#define I2C_CR_I2C_RXF_MASK      I2C_CR_I2C_RXF_MASK
#define I2C_CR_I2C_RXF_MASK_POS  (10U)
#define I2C_CR_I2C_RXF_MASK_LEN  (1U)
#define I2C_CR_I2C_RXF_MASK_MSK  (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)
#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS))
#define I2C_CR_I2C_NAK_MASK      I2C_CR_I2C_NAK_MASK
#define I2C_CR_I2C_NAK_MASK_POS  (11U)
#define I2C_CR_I2C_NAK_MASK_LEN  (1U)
#define I2C_CR_I2C_NAK_MASK_MSK  (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)
#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS))
#define I2C_CR_I2C_ARB_MASK      I2C_CR_I2C_ARB_MASK
#define I2C_CR_I2C_ARB_MASK_POS  (12U)
#define I2C_CR_I2C_ARB_MASK_LEN  (1U)
#define I2C_CR_I2C_ARB_MASK_MSK  (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)
#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS))
#define I2C_CR_I2C_FER_MASK      I2C_CR_I2C_FER_MASK
#define I2C_CR_I2C_FER_MASK_POS  (13U)
#define I2C_CR_I2C_FER_MASK_LEN  (1U)
#define I2C_CR_I2C_FER_MASK_MSK  (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)
#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS))
#define I2C_CR_I2C_END_CLR       I2C_CR_I2C_END_CLR
#define I2C_CR_I2C_END_CLR_POS   (16U)
#define I2C_CR_I2C_END_CLR_LEN   (1U)
#define I2C_CR_I2C_END_CLR_MSK   (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)
#define I2C_CR_I2C_END_CLR_UMSK  (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS))
#define I2C_CR_I2C_NAK_CLR       I2C_CR_I2C_NAK_CLR
#define I2C_CR_I2C_NAK_CLR_POS   (19U)
#define I2C_CR_I2C_NAK_CLR_LEN   (1U)
#define I2C_CR_I2C_NAK_CLR_MSK   (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)
#define I2C_CR_I2C_NAK_CLR_UMSK  (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS))
#define I2C_CR_I2C_ARB_CLR       I2C_CR_I2C_ARB_CLR
#define I2C_CR_I2C_ARB_CLR_POS   (20U)
#define I2C_CR_I2C_ARB_CLR_LEN   (1U)
#define I2C_CR_I2C_ARB_CLR_MSK   (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)
#define I2C_CR_I2C_ARB_CLR_UMSK  (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS))
#define I2C_CR_I2C_END_EN        I2C_CR_I2C_END_EN
#define I2C_CR_I2C_END_EN_POS    (24U)
#define I2C_CR_I2C_END_EN_LEN    (1U)
#define I2C_CR_I2C_END_EN_MSK    (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)
#define I2C_CR_I2C_END_EN_UMSK   (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS))
#define I2C_CR_I2C_TXF_EN        I2C_CR_I2C_TXF_EN
#define I2C_CR_I2C_TXF_EN_POS    (25U)
#define I2C_CR_I2C_TXF_EN_LEN    (1U)
#define I2C_CR_I2C_TXF_EN_MSK    (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)
#define I2C_CR_I2C_TXF_EN_UMSK   (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS))
#define I2C_CR_I2C_RXF_EN        I2C_CR_I2C_RXF_EN
#define I2C_CR_I2C_RXF_EN_POS    (26U)
#define I2C_CR_I2C_RXF_EN_LEN    (1U)
#define I2C_CR_I2C_RXF_EN_MSK    (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)
#define I2C_CR_I2C_RXF_EN_UMSK   (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS))
#define I2C_CR_I2C_NAK_EN        I2C_CR_I2C_NAK_EN
#define I2C_CR_I2C_NAK_EN_POS    (27U)
#define I2C_CR_I2C_NAK_EN_LEN    (1U)
#define I2C_CR_I2C_NAK_EN_MSK    (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)
#define I2C_CR_I2C_NAK_EN_UMSK   (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS))
#define I2C_CR_I2C_ARB_EN        I2C_CR_I2C_ARB_EN
#define I2C_CR_I2C_ARB_EN_POS    (28U)
#define I2C_CR_I2C_ARB_EN_LEN    (1U)
#define I2C_CR_I2C_ARB_EN_MSK    (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)
#define I2C_CR_I2C_ARB_EN_UMSK   (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS))
#define I2C_CR_I2C_FER_EN        I2C_CR_I2C_FER_EN
#define I2C_CR_I2C_FER_EN_POS    (29U)
#define I2C_CR_I2C_FER_EN_LEN    (1U)
#define I2C_CR_I2C_FER_EN_MSK    (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)
#define I2C_CR_I2C_FER_EN_UMSK   (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS))

/* 0x8 : i2c_sub_addr */
#define I2C_SUB_ADDR_OFFSET         (0x8)
#define I2C_CR_I2C_SUB_ADDR_B0      I2C_CR_I2C_SUB_ADDR_B0
#define I2C_CR_I2C_SUB_ADDR_B0_POS  (0U)
#define I2C_CR_I2C_SUB_ADDR_B0_LEN  (8U)
#define I2C_CR_I2C_SUB_ADDR_B0_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)
#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS))
#define I2C_CR_I2C_SUB_ADDR_B1      I2C_CR_I2C_SUB_ADDR_B1
#define I2C_CR_I2C_SUB_ADDR_B1_POS  (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_LEN  (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)
#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS))
#define I2C_CR_I2C_SUB_ADDR_B2      I2C_CR_I2C_SUB_ADDR_B2
#define I2C_CR_I2C_SUB_ADDR_B2_POS  (16U)
#define I2C_CR_I2C_SUB_ADDR_B2_LEN  (8U)
#define I2C_CR_I2C_SUB_ADDR_B2_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)
#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS))
#define I2C_CR_I2C_SUB_ADDR_B3      I2C_CR_I2C_SUB_ADDR_B3
#define I2C_CR_I2C_SUB_ADDR_B3_POS  (24U)
#define I2C_CR_I2C_SUB_ADDR_B3_LEN  (8U)
#define I2C_CR_I2C_SUB_ADDR_B3_MSK  (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)
#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS))

/* 0xC : i2c_bus_busy */
#define I2C_BUS_BUSY_OFFSET          (0xC)
#define I2C_STS_I2C_BUS_BUSY         I2C_STS_I2C_BUS_BUSY
#define I2C_STS_I2C_BUS_BUSY_POS     (0U)
#define I2C_STS_I2C_BUS_BUSY_LEN     (1U)
#define I2C_STS_I2C_BUS_BUSY_MSK     (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)
#define I2C_STS_I2C_BUS_BUSY_UMSK    (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS))
#define I2C_CR_I2C_BUS_BUSY_CLR      I2C_CR_I2C_BUS_BUSY_CLR
#define I2C_CR_I2C_BUS_BUSY_CLR_POS  (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_LEN  (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_MSK  (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)
#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS))

/* 0x10 : i2c_prd_start */
#define I2C_PRD_START_OFFSET       (0x10)
#define I2C_CR_I2C_PRD_S_PH_0      I2C_CR_I2C_PRD_S_PH_0
#define I2C_CR_I2C_PRD_S_PH_0_POS  (0U)
#define I2C_CR_I2C_PRD_S_PH_0_LEN  (8U)
#define I2C_CR_I2C_PRD_S_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)
#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS))
#define I2C_CR_I2C_PRD_S_PH_1      I2C_CR_I2C_PRD_S_PH_1
#define I2C_CR_I2C_PRD_S_PH_1_POS  (8U)
#define I2C_CR_I2C_PRD_S_PH_1_LEN  (8U)
#define I2C_CR_I2C_PRD_S_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)
#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS))
#define I2C_CR_I2C_PRD_S_PH_2      I2C_CR_I2C_PRD_S_PH_2
#define I2C_CR_I2C_PRD_S_PH_2_POS  (16U)
#define I2C_CR_I2C_PRD_S_PH_2_LEN  (8U)
#define I2C_CR_I2C_PRD_S_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)
#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS))
#define I2C_CR_I2C_PRD_S_PH_3      I2C_CR_I2C_PRD_S_PH_3
#define I2C_CR_I2C_PRD_S_PH_3_POS  (24U)
#define I2C_CR_I2C_PRD_S_PH_3_LEN  (8U)
#define I2C_CR_I2C_PRD_S_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)
#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS))

/* 0x14 : i2c_prd_stop */
#define I2C_PRD_STOP_OFFSET        (0x14)
#define I2C_CR_I2C_PRD_P_PH_0      I2C_CR_I2C_PRD_P_PH_0
#define I2C_CR_I2C_PRD_P_PH_0_POS  (0U)
#define I2C_CR_I2C_PRD_P_PH_0_LEN  (8U)
#define I2C_CR_I2C_PRD_P_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)
#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS))
#define I2C_CR_I2C_PRD_P_PH_1      I2C_CR_I2C_PRD_P_PH_1
#define I2C_CR_I2C_PRD_P_PH_1_POS  (8U)
#define I2C_CR_I2C_PRD_P_PH_1_LEN  (8U)
#define I2C_CR_I2C_PRD_P_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)
#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS))
#define I2C_CR_I2C_PRD_P_PH_2      I2C_CR_I2C_PRD_P_PH_2
#define I2C_CR_I2C_PRD_P_PH_2_POS  (16U)
#define I2C_CR_I2C_PRD_P_PH_2_LEN  (8U)
#define I2C_CR_I2C_PRD_P_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)
#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS))
#define I2C_CR_I2C_PRD_P_PH_3      I2C_CR_I2C_PRD_P_PH_3
#define I2C_CR_I2C_PRD_P_PH_3_POS  (24U)
#define I2C_CR_I2C_PRD_P_PH_3_LEN  (8U)
#define I2C_CR_I2C_PRD_P_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)
#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS))

/* 0x18 : i2c_prd_data */
#define I2C_PRD_DATA_OFFSET        (0x18)
#define I2C_CR_I2C_PRD_D_PH_0      I2C_CR_I2C_PRD_D_PH_0
#define I2C_CR_I2C_PRD_D_PH_0_POS  (0U)
#define I2C_CR_I2C_PRD_D_PH_0_LEN  (8U)
#define I2C_CR_I2C_PRD_D_PH_0_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)
#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS))
#define I2C_CR_I2C_PRD_D_PH_1      I2C_CR_I2C_PRD_D_PH_1
#define I2C_CR_I2C_PRD_D_PH_1_POS  (8U)
#define I2C_CR_I2C_PRD_D_PH_1_LEN  (8U)
#define I2C_CR_I2C_PRD_D_PH_1_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)
#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS))
#define I2C_CR_I2C_PRD_D_PH_2      I2C_CR_I2C_PRD_D_PH_2
#define I2C_CR_I2C_PRD_D_PH_2_POS  (16U)
#define I2C_CR_I2C_PRD_D_PH_2_LEN  (8U)
#define I2C_CR_I2C_PRD_D_PH_2_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)
#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS))
#define I2C_CR_I2C_PRD_D_PH_3      I2C_CR_I2C_PRD_D_PH_3
#define I2C_CR_I2C_PRD_D_PH_3_POS  (24U)
#define I2C_CR_I2C_PRD_D_PH_3_LEN  (8U)
#define I2C_CR_I2C_PRD_D_PH_3_MSK  (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)
#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS))

/* 0x80 : i2c_fifo_config_0 */
#define I2C_FIFO_CONFIG_0_OFFSET   (0x80)
#define I2C_DMA_TX_EN              I2C_DMA_TX_EN
#define I2C_DMA_TX_EN_POS          (0U)
#define I2C_DMA_TX_EN_LEN          (1U)
#define I2C_DMA_TX_EN_MSK          (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)
#define I2C_DMA_TX_EN_UMSK         (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS))
#define I2C_DMA_RX_EN              I2C_DMA_RX_EN
#define I2C_DMA_RX_EN_POS          (1U)
#define I2C_DMA_RX_EN_LEN          (1U)
#define I2C_DMA_RX_EN_MSK          (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)
#define I2C_DMA_RX_EN_UMSK         (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS))
#define I2C_TX_FIFO_CLR            I2C_TX_FIFO_CLR
#define I2C_TX_FIFO_CLR_POS        (2U)
#define I2C_TX_FIFO_CLR_LEN        (1U)
#define I2C_TX_FIFO_CLR_MSK        (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)
#define I2C_TX_FIFO_CLR_UMSK       (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS))
#define I2C_RX_FIFO_CLR            I2C_RX_FIFO_CLR
#define I2C_RX_FIFO_CLR_POS        (3U)
#define I2C_RX_FIFO_CLR_LEN        (1U)
#define I2C_RX_FIFO_CLR_MSK        (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)
#define I2C_RX_FIFO_CLR_UMSK       (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS))
#define I2C_TX_FIFO_OVERFLOW       I2C_TX_FIFO_OVERFLOW
#define I2C_TX_FIFO_OVERFLOW_POS   (4U)
#define I2C_TX_FIFO_OVERFLOW_LEN   (1U)
#define I2C_TX_FIFO_OVERFLOW_MSK   (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)
#define I2C_TX_FIFO_OVERFLOW_UMSK  (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS))
#define I2C_TX_FIFO_UNDERFLOW      I2C_TX_FIFO_UNDERFLOW
#define I2C_TX_FIFO_UNDERFLOW_POS  (5U)
#define I2C_TX_FIFO_UNDERFLOW_LEN  (1U)
#define I2C_TX_FIFO_UNDERFLOW_MSK  (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)
#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS))
#define I2C_RX_FIFO_OVERFLOW       I2C_RX_FIFO_OVERFLOW
#define I2C_RX_FIFO_OVERFLOW_POS   (6U)
#define I2C_RX_FIFO_OVERFLOW_LEN   (1U)
#define I2C_RX_FIFO_OVERFLOW_MSK   (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)
#define I2C_RX_FIFO_OVERFLOW_UMSK  (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS))
#define I2C_RX_FIFO_UNDERFLOW      I2C_RX_FIFO_UNDERFLOW
#define I2C_RX_FIFO_UNDERFLOW_POS  (7U)
#define I2C_RX_FIFO_UNDERFLOW_LEN  (1U)
#define I2C_RX_FIFO_UNDERFLOW_MSK  (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)
#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS))

/* 0x84 : i2c_fifo_config_1 */
#define I2C_FIFO_CONFIG_1_OFFSET (0x84)
#define I2C_TX_FIFO_CNT          I2C_TX_FIFO_CNT
#define I2C_TX_FIFO_CNT_POS      (0U)
#define I2C_TX_FIFO_CNT_LEN      (2U)
#define I2C_TX_FIFO_CNT_MSK      (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)
#define I2C_TX_FIFO_CNT_UMSK     (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS))
#define I2C_RX_FIFO_CNT          I2C_RX_FIFO_CNT
#define I2C_RX_FIFO_CNT_POS      (8U)
#define I2C_RX_FIFO_CNT_LEN      (2U)
#define I2C_RX_FIFO_CNT_MSK      (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)
#define I2C_RX_FIFO_CNT_UMSK     (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS))
#define I2C_TX_FIFO_TH           I2C_TX_FIFO_TH
#define I2C_TX_FIFO_TH_POS       (16U)
#define I2C_TX_FIFO_TH_LEN       (1U)
#define I2C_TX_FIFO_TH_MSK       (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)
#define I2C_TX_FIFO_TH_UMSK      (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS))
#define I2C_RX_FIFO_TH           I2C_RX_FIFO_TH
#define I2C_RX_FIFO_TH_POS       (24U)
#define I2C_RX_FIFO_TH_LEN       (1U)
#define I2C_RX_FIFO_TH_MSK       (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)
#define I2C_RX_FIFO_TH_UMSK      (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS))

/* 0x88 : i2c_fifo_wdata */
#define I2C_FIFO_WDATA_OFFSET (0x88)
#define I2C_FIFO_WDATA        I2C_FIFO_WDATA
#define I2C_FIFO_WDATA_POS    (0U)
#define I2C_FIFO_WDATA_LEN    (32U)
#define I2C_FIFO_WDATA_MSK    (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)
#define I2C_FIFO_WDATA_UMSK   (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS))

/* 0x8C : i2c_fifo_rdata */
#define I2C_FIFO_RDATA_OFFSET (0x8C)
#define I2C_FIFO_RDATA        I2C_FIFO_RDATA
#define I2C_FIFO_RDATA_POS    (0U)
#define I2C_FIFO_RDATA_LEN    (32U)
#define I2C_FIFO_RDATA_MSK    (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)
#define I2C_FIFO_RDATA_UMSK   (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS))

struct i2c_reg {
    /* 0x0 : i2c_config */
    union {
        struct
        {
            uint32_t cr_i2c_m_en        : 1; /* [    0],        r/w,        0x0 */
            uint32_t cr_i2c_pkt_dir     : 1; /* [    1],        r/w,        0x1 */
            uint32_t cr_i2c_deg_en      : 1; /* [    2],        r/w,        0x0 */
            uint32_t cr_i2c_scl_sync_en : 1; /* [    3],        r/w,        0x1 */
            uint32_t cr_i2c_sub_addr_en : 1; /* [    4],        r/w,        0x0 */
            uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5],        r/w,        0x0 */
            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
            uint32_t cr_i2c_slv_addr    : 7; /* [14: 8],        r/w,        0x0 */
            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
            uint32_t cr_i2c_pkt_len     : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reserved_24_27     : 4; /* [27:24],       rsvd,        0x0 */
            uint32_t cr_i2c_deg_cnt     : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_config;

    /* 0x4 : i2c_int_sts */
    union {
        struct
        {
            uint32_t i2c_end_int     : 1; /* [    0],          r,        0x0 */
            uint32_t i2c_txf_int     : 1; /* [    1],          r,        0x0 */
            uint32_t i2c_rxf_int     : 1; /* [    2],          r,        0x0 */
            uint32_t i2c_nak_int     : 1; /* [    3],          r,        0x0 */
            uint32_t i2c_arb_int     : 1; /* [    4],          r,        0x0 */
            uint32_t i2c_fer_int     : 1; /* [    5],          r,        0x0 */
            uint32_t reserved_6_7    : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t cr_i2c_end_mask : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_i2c_txf_mask : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_i2c_rxf_mask : 1; /* [   10],        r/w,        0x1 */
            uint32_t cr_i2c_nak_mask : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_i2c_arb_mask : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_i2c_fer_mask : 1; /* [   13],        r/w,        0x1 */
            uint32_t reserved_14_15  : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t cr_i2c_end_clr  : 1; /* [   16],        w1c,        0x0 */
            uint32_t rsvd_17         : 1; /* [   17],       rsvd,        0x0 */
            uint32_t rsvd_18         : 1; /* [   18],       rsvd,        0x0 */
            uint32_t cr_i2c_nak_clr  : 1; /* [   19],        w1c,        0x0 */
            uint32_t cr_i2c_arb_clr  : 1; /* [   20],        w1c,        0x0 */
            uint32_t rsvd_21         : 1; /* [   21],       rsvd,        0x0 */
            uint32_t reserved_22_23  : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t cr_i2c_end_en   : 1; /* [   24],        r/w,        0x1 */
            uint32_t cr_i2c_txf_en   : 1; /* [   25],        r/w,        0x1 */
            uint32_t cr_i2c_rxf_en   : 1; /* [   26],        r/w,        0x1 */
            uint32_t cr_i2c_nak_en   : 1; /* [   27],        r/w,        0x1 */
            uint32_t cr_i2c_arb_en   : 1; /* [   28],        r/w,        0x1 */
            uint32_t cr_i2c_fer_en   : 1; /* [   29],        r/w,        0x1 */
            uint32_t reserved_30_31  : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_int_sts;

    /* 0x8 : i2c_sub_addr */
    union {
        struct
        {
            uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_sub_addr;

    /* 0xC : i2c_bus_busy */
    union {
        struct
        {
            uint32_t sts_i2c_bus_busy    : 1;  /* [    0],          r,        0x0 */
            uint32_t cr_i2c_bus_busy_clr : 1;  /* [    1],        w1c,        0x0 */
            uint32_t reserved_2_31       : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_bus_busy;

    /* 0x10 : i2c_prd_start */
    union {
        struct
        {
            uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
            uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8],        r/w,        0xf */
            uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16],        r/w,        0xf */
            uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } i2c_prd_start;

    /* 0x14 : i2c_prd_stop */
    union {
        struct
        {
            uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
            uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8],        r/w,        0xf */
            uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16],        r/w,        0xf */
            uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } i2c_prd_stop;

    /* 0x18 : i2c_prd_data */
    union {
        struct
        {
            uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0],        r/w,        0xf */
            uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8],        r/w,        0xf */
            uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16],        r/w,        0xf */
            uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } i2c_prd_data;

    /* 0x1c  reserved */
    uint8_t RESERVED0x1c[100];

    /* 0x80 : i2c_fifo_config_0 */
    union {
        struct
        {
            uint32_t i2c_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t i2c_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_fifo_config_0;

    /* 0x84 : i2c_fifo_config_1 */
    union {
        struct
        {
            uint32_t tx_fifo_cnt    : 2; /* [ 1: 0],          r,        0x2 */
            uint32_t reserved_2_7   : 6; /* [ 7: 2],       rsvd,        0x0 */
            uint32_t rx_fifo_cnt    : 2; /* [ 9: 8],          r,        0x0 */
            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
            uint32_t tx_fifo_th     : 1; /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_23 : 7; /* [23:17],       rsvd,        0x0 */
            uint32_t rx_fifo_th     : 1; /* [   24],        r/w,        0x0 */
            uint32_t reserved_25_31 : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_fifo_config_1;

    /* 0x88 : i2c_fifo_wdata */
    union {
        struct
        {
            uint32_t i2c_fifo_wdata : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } i2c_fifo_wdata;

    /* 0x8C : i2c_fifo_rdata */
    union {
        struct
        {
            uint32_t i2c_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } i2c_fifo_rdata;
};

typedef volatile struct i2c_reg i2c_reg_t;

#endif /* __I2C_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/i2s_reg.h
================================================
/**
  ******************************************************************************
  * @file    i2s_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __I2S_REG_H__
#define __I2S_REG_H__

#include "bl702.h"

/* 0x0 : i2s_config */
#define I2S_CONFIG_OFFSET       (0x0)
#define I2S_CR_I2S_M_EN         I2S_CR_I2S_M_EN
#define I2S_CR_I2S_M_EN_POS     (0U)
#define I2S_CR_I2S_M_EN_LEN     (1U)
#define I2S_CR_I2S_M_EN_MSK     (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)
#define I2S_CR_I2S_M_EN_UMSK    (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS))
#define I2S_CR_I2S_S_EN         I2S_CR_I2S_S_EN
#define I2S_CR_I2S_S_EN_POS     (1U)
#define I2S_CR_I2S_S_EN_LEN     (1U)
#define I2S_CR_I2S_S_EN_MSK     (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)
#define I2S_CR_I2S_S_EN_UMSK    (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS))
#define I2S_CR_I2S_TXD_EN       I2S_CR_I2S_TXD_EN
#define I2S_CR_I2S_TXD_EN_POS   (2U)
#define I2S_CR_I2S_TXD_EN_LEN   (1U)
#define I2S_CR_I2S_TXD_EN_MSK   (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)
#define I2S_CR_I2S_TXD_EN_UMSK  (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS))
#define I2S_CR_I2S_RXD_EN       I2S_CR_I2S_RXD_EN
#define I2S_CR_I2S_RXD_EN_POS   (3U)
#define I2S_CR_I2S_RXD_EN_LEN   (1U)
#define I2S_CR_I2S_RXD_EN_MSK   (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)
#define I2S_CR_I2S_RXD_EN_UMSK  (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS))
#define I2S_CR_MONO_MODE        I2S_CR_MONO_MODE
#define I2S_CR_MONO_MODE_POS    (4U)
#define I2S_CR_MONO_MODE_LEN    (1U)
#define I2S_CR_MONO_MODE_MSK    (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)
#define I2S_CR_MONO_MODE_UMSK   (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS))
#define I2S_CR_MUTE_MODE        I2S_CR_MUTE_MODE
#define I2S_CR_MUTE_MODE_POS    (5U)
#define I2S_CR_MUTE_MODE_LEN    (1U)
#define I2S_CR_MUTE_MODE_MSK    (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)
#define I2S_CR_MUTE_MODE_UMSK   (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS))
#define I2S_CR_FS_1T_MODE       I2S_CR_FS_1T_MODE
#define I2S_CR_FS_1T_MODE_POS   (6U)
#define I2S_CR_FS_1T_MODE_LEN   (1U)
#define I2S_CR_FS_1T_MODE_MSK   (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)
#define I2S_CR_FS_1T_MODE_UMSK  (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS))
#define I2S_CR_FS_4CH_MODE      I2S_CR_FS_4CH_MODE
#define I2S_CR_FS_4CH_MODE_POS  (7U)
#define I2S_CR_FS_4CH_MODE_LEN  (1U)
#define I2S_CR_FS_4CH_MODE_MSK  (((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS)
#define I2S_CR_FS_4CH_MODE_UMSK (~(((1U << I2S_CR_FS_4CH_MODE_LEN) - 1) << I2S_CR_FS_4CH_MODE_POS))
#define I2S_CR_FS_3CH_MODE      I2S_CR_FS_3CH_MODE
#define I2S_CR_FS_3CH_MODE_POS  (8U)
#define I2S_CR_FS_3CH_MODE_LEN  (1U)
#define I2S_CR_FS_3CH_MODE_MSK  (((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS)
#define I2S_CR_FS_3CH_MODE_UMSK (~(((1U << I2S_CR_FS_3CH_MODE_LEN) - 1) << I2S_CR_FS_3CH_MODE_POS))
#define I2S_CR_FRAME_SIZE       I2S_CR_FRAME_SIZE
#define I2S_CR_FRAME_SIZE_POS   (12U)
#define I2S_CR_FRAME_SIZE_LEN   (2U)
#define I2S_CR_FRAME_SIZE_MSK   (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)
#define I2S_CR_FRAME_SIZE_UMSK  (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS))
#define I2S_CR_DATA_SIZE        I2S_CR_DATA_SIZE
#define I2S_CR_DATA_SIZE_POS    (14U)
#define I2S_CR_DATA_SIZE_LEN    (2U)
#define I2S_CR_DATA_SIZE_MSK    (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)
#define I2S_CR_DATA_SIZE_UMSK   (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS))
#define I2S_CR_I2S_MODE         I2S_CR_I2S_MODE
#define I2S_CR_I2S_MODE_POS     (16U)
#define I2S_CR_I2S_MODE_LEN     (2U)
#define I2S_CR_I2S_MODE_MSK     (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)
#define I2S_CR_I2S_MODE_UMSK    (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS))
#define I2S_CR_ENDIAN           I2S_CR_ENDIAN
#define I2S_CR_ENDIAN_POS       (18U)
#define I2S_CR_ENDIAN_LEN       (1U)
#define I2S_CR_ENDIAN_MSK       (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)
#define I2S_CR_ENDIAN_UMSK      (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS))
#define I2S_CR_MONO_RX_CH       I2S_CR_MONO_RX_CH
#define I2S_CR_MONO_RX_CH_POS   (19U)
#define I2S_CR_MONO_RX_CH_LEN   (1U)
#define I2S_CR_MONO_RX_CH_MSK   (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)
#define I2S_CR_MONO_RX_CH_UMSK  (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS))
#define I2S_CR_OFS_CNT          I2S_CR_OFS_CNT
#define I2S_CR_OFS_CNT_POS      (20U)
#define I2S_CR_OFS_CNT_LEN      (5U)
#define I2S_CR_OFS_CNT_MSK      (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)
#define I2S_CR_OFS_CNT_UMSK     (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS))
#define I2S_CR_OFS_EN           I2S_CR_OFS_EN
#define I2S_CR_OFS_EN_POS       (25U)
#define I2S_CR_OFS_EN_LEN       (1U)
#define I2S_CR_OFS_EN_MSK       (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)
#define I2S_CR_OFS_EN_UMSK      (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS))

/* 0x4 : i2s_int_sts */
#define I2S_INT_STS_OFFSET       (0x4)
#define I2S_TXF_INT              I2S_TXF_INT
#define I2S_TXF_INT_POS          (0U)
#define I2S_TXF_INT_LEN          (1U)
#define I2S_TXF_INT_MSK          (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)
#define I2S_TXF_INT_UMSK         (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS))
#define I2S_RXF_INT              I2S_RXF_INT
#define I2S_RXF_INT_POS          (1U)
#define I2S_RXF_INT_LEN          (1U)
#define I2S_RXF_INT_MSK          (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)
#define I2S_RXF_INT_UMSK         (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS))
#define I2S_FER_INT              I2S_FER_INT
#define I2S_FER_INT_POS          (2U)
#define I2S_FER_INT_LEN          (1U)
#define I2S_FER_INT_MSK          (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)
#define I2S_FER_INT_UMSK         (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS))
#define I2S_CR_I2S_TXF_MASK      I2S_CR_I2S_TXF_MASK
#define I2S_CR_I2S_TXF_MASK_POS  (8U)
#define I2S_CR_I2S_TXF_MASK_LEN  (1U)
#define I2S_CR_I2S_TXF_MASK_MSK  (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)
#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS))
#define I2S_CR_I2S_RXF_MASK      I2S_CR_I2S_RXF_MASK
#define I2S_CR_I2S_RXF_MASK_POS  (9U)
#define I2S_CR_I2S_RXF_MASK_LEN  (1U)
#define I2S_CR_I2S_RXF_MASK_MSK  (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)
#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS))
#define I2S_CR_I2S_FER_MASK      I2S_CR_I2S_FER_MASK
#define I2S_CR_I2S_FER_MASK_POS  (10U)
#define I2S_CR_I2S_FER_MASK_LEN  (1U)
#define I2S_CR_I2S_FER_MASK_MSK  (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)
#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS))
#define I2S_CR_I2S_TXF_EN        I2S_CR_I2S_TXF_EN
#define I2S_CR_I2S_TXF_EN_POS    (24U)
#define I2S_CR_I2S_TXF_EN_LEN    (1U)
#define I2S_CR_I2S_TXF_EN_MSK    (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)
#define I2S_CR_I2S_TXF_EN_UMSK   (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS))
#define I2S_CR_I2S_RXF_EN        I2S_CR_I2S_RXF_EN
#define I2S_CR_I2S_RXF_EN_POS    (25U)
#define I2S_CR_I2S_RXF_EN_LEN    (1U)
#define I2S_CR_I2S_RXF_EN_MSK    (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)
#define I2S_CR_I2S_RXF_EN_UMSK   (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS))
#define I2S_CR_I2S_FER_EN        I2S_CR_I2S_FER_EN
#define I2S_CR_I2S_FER_EN_POS    (26U)
#define I2S_CR_I2S_FER_EN_LEN    (1U)
#define I2S_CR_I2S_FER_EN_MSK    (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)
#define I2S_CR_I2S_FER_EN_UMSK   (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS))

/* 0x10 : i2s_bclk_config */
#define I2S_BCLK_CONFIG_OFFSET (0x10)
#define I2S_CR_BCLK_DIV_L      I2S_CR_BCLK_DIV_L
#define I2S_CR_BCLK_DIV_L_POS  (0U)
#define I2S_CR_BCLK_DIV_L_LEN  (12U)
#define I2S_CR_BCLK_DIV_L_MSK  (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)
#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS))
#define I2S_CR_BCLK_DIV_H      I2S_CR_BCLK_DIV_H
#define I2S_CR_BCLK_DIV_H_POS  (16U)
#define I2S_CR_BCLK_DIV_H_LEN  (12U)
#define I2S_CR_BCLK_DIV_H_MSK  (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)
#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS))

/* 0x80 : i2s_fifo_config_0 */
#define I2S_FIFO_CONFIG_0_OFFSET   (0x80)
#define I2S_DMA_TX_EN              I2S_DMA_TX_EN
#define I2S_DMA_TX_EN_POS          (0U)
#define I2S_DMA_TX_EN_LEN          (1U)
#define I2S_DMA_TX_EN_MSK          (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)
#define I2S_DMA_TX_EN_UMSK         (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS))
#define I2S_DMA_RX_EN              I2S_DMA_RX_EN
#define I2S_DMA_RX_EN_POS          (1U)
#define I2S_DMA_RX_EN_LEN          (1U)
#define I2S_DMA_RX_EN_MSK          (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)
#define I2S_DMA_RX_EN_UMSK         (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS))
#define I2S_TX_FIFO_CLR            I2S_TX_FIFO_CLR
#define I2S_TX_FIFO_CLR_POS        (2U)
#define I2S_TX_FIFO_CLR_LEN        (1U)
#define I2S_TX_FIFO_CLR_MSK        (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)
#define I2S_TX_FIFO_CLR_UMSK       (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS))
#define I2S_RX_FIFO_CLR            I2S_RX_FIFO_CLR
#define I2S_RX_FIFO_CLR_POS        (3U)
#define I2S_RX_FIFO_CLR_LEN        (1U)
#define I2S_RX_FIFO_CLR_MSK        (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)
#define I2S_RX_FIFO_CLR_UMSK       (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS))
#define I2S_TX_FIFO_OVERFLOW       I2S_TX_FIFO_OVERFLOW
#define I2S_TX_FIFO_OVERFLOW_POS   (4U)
#define I2S_TX_FIFO_OVERFLOW_LEN   (1U)
#define I2S_TX_FIFO_OVERFLOW_MSK   (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)
#define I2S_TX_FIFO_OVERFLOW_UMSK  (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS))
#define I2S_TX_FIFO_UNDERFLOW      I2S_TX_FIFO_UNDERFLOW
#define I2S_TX_FIFO_UNDERFLOW_POS  (5U)
#define I2S_TX_FIFO_UNDERFLOW_LEN  (1U)
#define I2S_TX_FIFO_UNDERFLOW_MSK  (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)
#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS))
#define I2S_RX_FIFO_OVERFLOW       I2S_RX_FIFO_OVERFLOW
#define I2S_RX_FIFO_OVERFLOW_POS   (6U)
#define I2S_RX_FIFO_OVERFLOW_LEN   (1U)
#define I2S_RX_FIFO_OVERFLOW_MSK   (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)
#define I2S_RX_FIFO_OVERFLOW_UMSK  (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS))
#define I2S_RX_FIFO_UNDERFLOW      I2S_RX_FIFO_UNDERFLOW
#define I2S_RX_FIFO_UNDERFLOW_POS  (7U)
#define I2S_RX_FIFO_UNDERFLOW_LEN  (1U)
#define I2S_RX_FIFO_UNDERFLOW_MSK  (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)
#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS))
#define I2S_CR_FIFO_LR_MERGE       I2S_CR_FIFO_LR_MERGE
#define I2S_CR_FIFO_LR_MERGE_POS   (8U)
#define I2S_CR_FIFO_LR_MERGE_LEN   (1U)
#define I2S_CR_FIFO_LR_MERGE_MSK   (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)
#define I2S_CR_FIFO_LR_MERGE_UMSK  (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS))
#define I2S_CR_FIFO_LR_EXCHG       I2S_CR_FIFO_LR_EXCHG
#define I2S_CR_FIFO_LR_EXCHG_POS   (9U)
#define I2S_CR_FIFO_LR_EXCHG_LEN   (1U)
#define I2S_CR_FIFO_LR_EXCHG_MSK   (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)
#define I2S_CR_FIFO_LR_EXCHG_UMSK  (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS))
#define I2S_CR_FIFO_24B_LJ         I2S_CR_FIFO_24B_LJ
#define I2S_CR_FIFO_24B_LJ_POS     (10U)
#define I2S_CR_FIFO_24B_LJ_LEN     (1U)
#define I2S_CR_FIFO_24B_LJ_MSK     (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)
#define I2S_CR_FIFO_24B_LJ_UMSK    (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS))

/* 0x84 : i2s_fifo_config_1 */
#define I2S_FIFO_CONFIG_1_OFFSET (0x84)
#define I2S_TX_FIFO_CNT          I2S_TX_FIFO_CNT
#define I2S_TX_FIFO_CNT_POS      (0U)
#define I2S_TX_FIFO_CNT_LEN      (5U)
#define I2S_TX_FIFO_CNT_MSK      (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)
#define I2S_TX_FIFO_CNT_UMSK     (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS))
#define I2S_RX_FIFO_CNT          I2S_RX_FIFO_CNT
#define I2S_RX_FIFO_CNT_POS      (8U)
#define I2S_RX_FIFO_CNT_LEN      (5U)
#define I2S_RX_FIFO_CNT_MSK      (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)
#define I2S_RX_FIFO_CNT_UMSK     (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS))
#define I2S_TX_FIFO_TH           I2S_TX_FIFO_TH
#define I2S_TX_FIFO_TH_POS       (16U)
#define I2S_TX_FIFO_TH_LEN       (4U)
#define I2S_TX_FIFO_TH_MSK       (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)
#define I2S_TX_FIFO_TH_UMSK      (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS))
#define I2S_RX_FIFO_TH           I2S_RX_FIFO_TH
#define I2S_RX_FIFO_TH_POS       (24U)
#define I2S_RX_FIFO_TH_LEN       (4U)
#define I2S_RX_FIFO_TH_MSK       (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)
#define I2S_RX_FIFO_TH_UMSK      (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS))

/* 0x88 : i2s_fifo_wdata */
#define I2S_FIFO_WDATA_OFFSET (0x88)
#define I2S_FIFO_WDATA        I2S_FIFO_WDATA
#define I2S_FIFO_WDATA_POS    (0U)
#define I2S_FIFO_WDATA_LEN    (32U)
#define I2S_FIFO_WDATA_MSK    (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)
#define I2S_FIFO_WDATA_UMSK   (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS))

/* 0x8C : i2s_fifo_rdata */
#define I2S_FIFO_RDATA_OFFSET (0x8C)
#define I2S_FIFO_RDATA        I2S_FIFO_RDATA
#define I2S_FIFO_RDATA_POS    (0U)
#define I2S_FIFO_RDATA_LEN    (32U)
#define I2S_FIFO_RDATA_MSK    (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)
#define I2S_FIFO_RDATA_UMSK   (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS))

/* 0xFC : i2s_io_config */
#define I2S_IO_CONFIG_OFFSET     (0xFC)
#define I2S_CR_I2S_TXD_INV       I2S_CR_I2S_TXD_INV
#define I2S_CR_I2S_TXD_INV_POS   (0U)
#define I2S_CR_I2S_TXD_INV_LEN   (1U)
#define I2S_CR_I2S_TXD_INV_MSK   (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)
#define I2S_CR_I2S_TXD_INV_UMSK  (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS))
#define I2S_CR_I2S_RXD_INV       I2S_CR_I2S_RXD_INV
#define I2S_CR_I2S_RXD_INV_POS   (1U)
#define I2S_CR_I2S_RXD_INV_LEN   (1U)
#define I2S_CR_I2S_RXD_INV_MSK   (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)
#define I2S_CR_I2S_RXD_INV_UMSK  (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS))
#define I2S_CR_I2S_FS_INV        I2S_CR_I2S_FS_INV
#define I2S_CR_I2S_FS_INV_POS    (2U)
#define I2S_CR_I2S_FS_INV_LEN    (1U)
#define I2S_CR_I2S_FS_INV_MSK    (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)
#define I2S_CR_I2S_FS_INV_UMSK   (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS))
#define I2S_CR_I2S_BCLK_INV      I2S_CR_I2S_BCLK_INV
#define I2S_CR_I2S_BCLK_INV_POS  (3U)
#define I2S_CR_I2S_BCLK_INV_LEN  (1U)
#define I2S_CR_I2S_BCLK_INV_MSK  (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)
#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS))
#define I2S_CR_DEG_CNT           I2S_CR_DEG_CNT
#define I2S_CR_DEG_CNT_POS       (4U)
#define I2S_CR_DEG_CNT_LEN       (3U)
#define I2S_CR_DEG_CNT_MSK       (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)
#define I2S_CR_DEG_CNT_UMSK      (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS))
#define I2S_CR_DEG_EN            I2S_CR_DEG_EN
#define I2S_CR_DEG_EN_POS        (7U)
#define I2S_CR_DEG_EN_LEN        (1U)
#define I2S_CR_DEG_EN_MSK        (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)
#define I2S_CR_DEG_EN_UMSK       (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS))

struct i2s_reg {
    /* 0x0 : i2s_config */
    union {
        struct
        {
            uint32_t cr_i2s_m_en    : 1; /* [    0],        r/w,        0x0 */
            uint32_t cr_i2s_s_en    : 1; /* [    1],        r/w,        0x0 */
            uint32_t cr_i2s_txd_en  : 1; /* [    2],        r/w,        0x0 */
            uint32_t cr_i2s_rxd_en  : 1; /* [    3],        r/w,        0x0 */
            uint32_t cr_mono_mode   : 1; /* [    4],        r/w,        0x0 */
            uint32_t cr_mute_mode   : 1; /* [    5],        r/w,        0x0 */
            uint32_t cr_fs_1t_mode  : 1; /* [    6],        r/w,        0x0 */
            uint32_t cr_fs_4ch_mode : 1; /* [    7],        r/w,        0x0 */
            uint32_t cr_fs_3ch_mode : 1; /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_11  : 3; /* [11: 9],       rsvd,        0x0 */
            uint32_t cr_frame_size  : 2; /* [13:12],        r/w,        0x1 */
            uint32_t cr_data_size   : 2; /* [15:14],        r/w,        0x1 */
            uint32_t cr_i2s_mode    : 2; /* [17:16],        r/w,        0x0 */
            uint32_t cr_endian      : 1; /* [   18],        r/w,        0x0 */
            uint32_t cr_mono_rx_ch  : 1; /* [   19],        r/w,        0x0 */
            uint32_t cr_ofs_cnt     : 5; /* [24:20],        r/w,        0x0 */
            uint32_t cr_ofs_en      : 1; /* [   25],        r/w,        0x0 */
            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_config;

    /* 0x4 : i2s_int_sts */
    union {
        struct
        {
            uint32_t i2s_txf_int     : 1;  /* [    0],          r,        0x0 */
            uint32_t i2s_rxf_int     : 1;  /* [    1],          r,        0x0 */
            uint32_t i2s_fer_int     : 1;  /* [    2],          r,        0x0 */
            uint32_t reserved_3_7    : 5;  /* [ 7: 3],       rsvd,        0x0 */
            uint32_t cr_i2s_txf_mask : 1;  /* [    8],        r/w,        0x1 */
            uint32_t cr_i2s_rxf_mask : 1;  /* [    9],        r/w,        0x1 */
            uint32_t cr_i2s_fer_mask : 1;  /* [   10],        r/w,        0x1 */
            uint32_t reserved_11_23  : 13; /* [23:11],       rsvd,        0x0 */
            uint32_t cr_i2s_txf_en   : 1;  /* [   24],        r/w,        0x1 */
            uint32_t cr_i2s_rxf_en   : 1;  /* [   25],        r/w,        0x1 */
            uint32_t cr_i2s_fer_en   : 1;  /* [   26],        r/w,        0x1 */
            uint32_t reserved_27_31  : 5;  /* [31:27],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_int_sts;

    /* 0x8  reserved */
    uint8_t RESERVED0x8[8];

    /* 0x10 : i2s_bclk_config */
    union {
        struct
        {
            uint32_t cr_bclk_div_l  : 12; /* [11: 0],        r/w,        0x1 */
            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t cr_bclk_div_h  : 12; /* [27:16],        r/w,        0x1 */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_bclk_config;

    /* 0x14  reserved */
    uint8_t RESERVED0x14[108];

    /* 0x80 : i2s_fifo_config_0 */
    union {
        struct
        {
            uint32_t i2s_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t i2s_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t cr_fifo_lr_merge  : 1;  /* [    8],        r/w,        0x0 */
            uint32_t cr_fifo_lr_exchg  : 1;  /* [    9],        r/w,        0x0 */
            uint32_t cr_fifo_24b_lj    : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_31    : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_fifo_config_0;

    /* 0x84 : i2s_fifo_config_1 */
    union {
        struct
        {
            uint32_t tx_fifo_cnt    : 5; /* [ 4: 0],          r,       0x10 */
            uint32_t reserved_5_7   : 3; /* [ 7: 5],       rsvd,        0x0 */
            uint32_t rx_fifo_cnt    : 5; /* [12: 8],          r,        0x0 */
            uint32_t reserved_13_15 : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t tx_fifo_th     : 4; /* [19:16],        r/w,        0x0 */
            uint32_t reserved_20_23 : 4; /* [23:20],       rsvd,        0x0 */
            uint32_t rx_fifo_th     : 4; /* [27:24],        r/w,        0x0 */
            uint32_t reserved_28_31 : 4; /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_fifo_config_1;

    /* 0x88 : i2s_fifo_wdata */
    union {
        struct
        {
            uint32_t i2s_fifo_wdata : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } i2s_fifo_wdata;

    /* 0x8C : i2s_fifo_rdata */
    union {
        struct
        {
            uint32_t i2s_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_fifo_rdata;

    /* 0x90  reserved */
    uint8_t RESERVED0x90[108];

    /* 0xFC : i2s_io_config */
    union {
        struct
        {
            uint32_t cr_i2s_txd_inv  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_i2s_rxd_inv  : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_i2s_fs_inv   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_i2s_bclk_inv : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_deg_cnt      : 3;  /* [ 6: 4],        r/w,        0x0 */
            uint32_t cr_deg_en       : 1;  /* [    7],        r/w,        0x0 */
            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } i2s_io_config;
};

typedef volatile struct i2s_reg i2s_reg_t;

#endif /* __I2S_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/ir_reg.h
================================================
/**
  ******************************************************************************
  * @file    ir_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __IR_REG_H__
#define __IR_REG_H__

#include "bl702.h"

/* 0x0 : irtx_config */
#define IRTX_CONFIG_OFFSET            (0x0)
#define IR_CR_IRTX_EN                 IR_CR_IRTX_EN
#define IR_CR_IRTX_EN_POS             (0U)
#define IR_CR_IRTX_EN_LEN             (1U)
#define IR_CR_IRTX_EN_MSK             (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)
#define IR_CR_IRTX_EN_UMSK            (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS))
#define IR_CR_IRTX_OUT_INV            IR_CR_IRTX_OUT_INV
#define IR_CR_IRTX_OUT_INV_POS        (1U)
#define IR_CR_IRTX_OUT_INV_LEN        (1U)
#define IR_CR_IRTX_OUT_INV_MSK        (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)
#define IR_CR_IRTX_OUT_INV_UMSK       (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS))
#define IR_CR_IRTX_MOD_EN             IR_CR_IRTX_MOD_EN
#define IR_CR_IRTX_MOD_EN_POS         (2U)
#define IR_CR_IRTX_MOD_EN_LEN         (1U)
#define IR_CR_IRTX_MOD_EN_MSK         (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)
#define IR_CR_IRTX_MOD_EN_UMSK        (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS))
#define IR_CR_IRTX_SWM_EN             IR_CR_IRTX_SWM_EN
#define IR_CR_IRTX_SWM_EN_POS         (3U)
#define IR_CR_IRTX_SWM_EN_LEN         (1U)
#define IR_CR_IRTX_SWM_EN_MSK         (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)
#define IR_CR_IRTX_SWM_EN_UMSK        (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS))
#define IR_CR_IRTX_DATA_EN            IR_CR_IRTX_DATA_EN
#define IR_CR_IRTX_DATA_EN_POS        (4U)
#define IR_CR_IRTX_DATA_EN_LEN        (1U)
#define IR_CR_IRTX_DATA_EN_MSK        (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)
#define IR_CR_IRTX_DATA_EN_UMSK       (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS))
#define IR_CR_IRTX_LOGIC0_HL_INV      IR_CR_IRTX_LOGIC0_HL_INV
#define IR_CR_IRTX_LOGIC0_HL_INV_POS  (5U)
#define IR_CR_IRTX_LOGIC0_HL_INV_LEN  (1U)
#define IR_CR_IRTX_LOGIC0_HL_INV_MSK  (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)
#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS))
#define IR_CR_IRTX_LOGIC1_HL_INV      IR_CR_IRTX_LOGIC1_HL_INV
#define IR_CR_IRTX_LOGIC1_HL_INV_POS  (6U)
#define IR_CR_IRTX_LOGIC1_HL_INV_LEN  (1U)
#define IR_CR_IRTX_LOGIC1_HL_INV_MSK  (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)
#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS))
#define IR_CR_IRTX_HEAD_EN            IR_CR_IRTX_HEAD_EN
#define IR_CR_IRTX_HEAD_EN_POS        (8U)
#define IR_CR_IRTX_HEAD_EN_LEN        (1U)
#define IR_CR_IRTX_HEAD_EN_MSK        (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)
#define IR_CR_IRTX_HEAD_EN_UMSK       (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS))
#define IR_CR_IRTX_HEAD_HL_INV        IR_CR_IRTX_HEAD_HL_INV
#define IR_CR_IRTX_HEAD_HL_INV_POS    (9U)
#define IR_CR_IRTX_HEAD_HL_INV_LEN    (1U)
#define IR_CR_IRTX_HEAD_HL_INV_MSK    (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)
#define IR_CR_IRTX_HEAD_HL_INV_UMSK   (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS))
#define IR_CR_IRTX_TAIL_EN            IR_CR_IRTX_TAIL_EN
#define IR_CR_IRTX_TAIL_EN_POS        (10U)
#define IR_CR_IRTX_TAIL_EN_LEN        (1U)
#define IR_CR_IRTX_TAIL_EN_MSK        (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)
#define IR_CR_IRTX_TAIL_EN_UMSK       (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS))
#define IR_CR_IRTX_TAIL_HL_INV        IR_CR_IRTX_TAIL_HL_INV
#define IR_CR_IRTX_TAIL_HL_INV_POS    (11U)
#define IR_CR_IRTX_TAIL_HL_INV_LEN    (1U)
#define IR_CR_IRTX_TAIL_HL_INV_MSK    (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)
#define IR_CR_IRTX_TAIL_HL_INV_UMSK   (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS))
#define IR_CR_IRTX_DATA_NUM           IR_CR_IRTX_DATA_NUM
#define IR_CR_IRTX_DATA_NUM_POS       (12U)
#define IR_CR_IRTX_DATA_NUM_LEN       (6U)
#define IR_CR_IRTX_DATA_NUM_MSK       (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)
#define IR_CR_IRTX_DATA_NUM_UMSK      (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS))

/* 0x4 : irtx_int_sts */
#define IRTX_INT_STS_OFFSET      (0x4)
#define IRTX_END_INT             IRTX_END_INT
#define IRTX_END_INT_POS         (0U)
#define IRTX_END_INT_LEN         (1U)
#define IRTX_END_INT_MSK         (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)
#define IRTX_END_INT_UMSK        (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS))
#define IR_CR_IRTX_END_MASK      IR_CR_IRTX_END_MASK
#define IR_CR_IRTX_END_MASK_POS  (8U)
#define IR_CR_IRTX_END_MASK_LEN  (1U)
#define IR_CR_IRTX_END_MASK_MSK  (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)
#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS))
#define IR_CR_IRTX_END_CLR       IR_CR_IRTX_END_CLR
#define IR_CR_IRTX_END_CLR_POS   (16U)
#define IR_CR_IRTX_END_CLR_LEN   (1U)
#define IR_CR_IRTX_END_CLR_MSK   (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)
#define IR_CR_IRTX_END_CLR_UMSK  (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS))
#define IR_CR_IRTX_END_EN        IR_CR_IRTX_END_EN
#define IR_CR_IRTX_END_EN_POS    (24U)
#define IR_CR_IRTX_END_EN_LEN    (1U)
#define IR_CR_IRTX_END_EN_MSK    (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)
#define IR_CR_IRTX_END_EN_UMSK   (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS))

/* 0x8 : irtx_data_word0 */
#define IRTX_DATA_WORD0_OFFSET     (0x8)
#define IR_CR_IRTX_DATA_WORD0      IR_CR_IRTX_DATA_WORD0
#define IR_CR_IRTX_DATA_WORD0_POS  (0U)
#define IR_CR_IRTX_DATA_WORD0_LEN  (32U)
#define IR_CR_IRTX_DATA_WORD0_MSK  (((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS)
#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD0_LEN) - 1) << IR_CR_IRTX_DATA_WORD0_POS))

/* 0xC : irtx_data_word1 */
#define IRTX_DATA_WORD1_OFFSET     (0xC)
#define IR_CR_IRTX_DATA_WORD1      IR_CR_IRTX_DATA_WORD1
#define IR_CR_IRTX_DATA_WORD1_POS  (0U)
#define IR_CR_IRTX_DATA_WORD1_LEN  (32U)
#define IR_CR_IRTX_DATA_WORD1_MSK  (((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS)
#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U << IR_CR_IRTX_DATA_WORD1_LEN) - 1) << IR_CR_IRTX_DATA_WORD1_POS))

/* 0x10 : irtx_pulse_width */
#define IRTX_PULSE_WIDTH_OFFSET   (0x10)
#define IR_CR_IRTX_PW_UNIT        IR_CR_IRTX_PW_UNIT
#define IR_CR_IRTX_PW_UNIT_POS    (0U)
#define IR_CR_IRTX_PW_UNIT_LEN    (12U)
#define IR_CR_IRTX_PW_UNIT_MSK    (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)
#define IR_CR_IRTX_PW_UNIT_UMSK   (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS))
#define IR_CR_IRTX_MOD_PH0_W      IR_CR_IRTX_MOD_PH0_W
#define IR_CR_IRTX_MOD_PH0_W_POS  (16U)
#define IR_CR_IRTX_MOD_PH0_W_LEN  (8U)
#define IR_CR_IRTX_MOD_PH0_W_MSK  (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)
#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS))
#define IR_CR_IRTX_MOD_PH1_W      IR_CR_IRTX_MOD_PH1_W
#define IR_CR_IRTX_MOD_PH1_W_POS  (24U)
#define IR_CR_IRTX_MOD_PH1_W_LEN  (8U)
#define IR_CR_IRTX_MOD_PH1_W_MSK  (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)
#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS))

/* 0x14 : irtx_pw */
#define IRTX_PW_OFFSET               (0x14)
#define IR_CR_IRTX_LOGIC0_PH0_W      IR_CR_IRTX_LOGIC0_PH0_W
#define IR_CR_IRTX_LOGIC0_PH0_W_POS  (0U)
#define IR_CR_IRTX_LOGIC0_PH0_W_LEN  (4U)
#define IR_CR_IRTX_LOGIC0_PH0_W_MSK  (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)
#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS))
#define IR_CR_IRTX_LOGIC0_PH1_W      IR_CR_IRTX_LOGIC0_PH1_W
#define IR_CR_IRTX_LOGIC0_PH1_W_POS  (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_LEN  (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_MSK  (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)
#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS))
#define IR_CR_IRTX_LOGIC1_PH0_W      IR_CR_IRTX_LOGIC1_PH0_W
#define IR_CR_IRTX_LOGIC1_PH0_W_POS  (8U)
#define IR_CR_IRTX_LOGIC1_PH0_W_LEN  (4U)
#define IR_CR_IRTX_LOGIC1_PH0_W_MSK  (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)
#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS))
#define IR_CR_IRTX_LOGIC1_PH1_W      IR_CR_IRTX_LOGIC1_PH1_W
#define IR_CR_IRTX_LOGIC1_PH1_W_POS  (12U)
#define IR_CR_IRTX_LOGIC1_PH1_W_LEN  (4U)
#define IR_CR_IRTX_LOGIC1_PH1_W_MSK  (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)
#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS))
#define IR_CR_IRTX_HEAD_PH0_W        IR_CR_IRTX_HEAD_PH0_W
#define IR_CR_IRTX_HEAD_PH0_W_POS    (16U)
#define IR_CR_IRTX_HEAD_PH0_W_LEN    (4U)
#define IR_CR_IRTX_HEAD_PH0_W_MSK    (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)
#define IR_CR_IRTX_HEAD_PH0_W_UMSK   (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS))
#define IR_CR_IRTX_HEAD_PH1_W        IR_CR_IRTX_HEAD_PH1_W
#define IR_CR_IRTX_HEAD_PH1_W_POS    (20U)
#define IR_CR_IRTX_HEAD_PH1_W_LEN    (4U)
#define IR_CR_IRTX_HEAD_PH1_W_MSK    (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)
#define IR_CR_IRTX_HEAD_PH1_W_UMSK   (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS))
#define IR_CR_IRTX_TAIL_PH0_W        IR_CR_IRTX_TAIL_PH0_W
#define IR_CR_IRTX_TAIL_PH0_W_POS    (24U)
#define IR_CR_IRTX_TAIL_PH0_W_LEN    (4U)
#define IR_CR_IRTX_TAIL_PH0_W_MSK    (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)
#define IR_CR_IRTX_TAIL_PH0_W_UMSK   (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS))
#define IR_CR_IRTX_TAIL_PH1_W        IR_CR_IRTX_TAIL_PH1_W
#define IR_CR_IRTX_TAIL_PH1_W_POS    (28U)
#define IR_CR_IRTX_TAIL_PH1_W_LEN    (4U)
#define IR_CR_IRTX_TAIL_PH1_W_MSK    (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)
#define IR_CR_IRTX_TAIL_PH1_W_UMSK   (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS))

/* 0x40 : irtx_swm_pw_0 */
#define IRTX_SWM_PW_0_OFFSET     (0x40)
#define IR_CR_IRTX_SWM_PW_0      IR_CR_IRTX_SWM_PW_0
#define IR_CR_IRTX_SWM_PW_0_POS  (0U)
#define IR_CR_IRTX_SWM_PW_0_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_0_MSK  (((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS)
#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_0_LEN) - 1) << IR_CR_IRTX_SWM_PW_0_POS))

/* 0x44 : irtx_swm_pw_1 */
#define IRTX_SWM_PW_1_OFFSET     (0x44)
#define IR_CR_IRTX_SWM_PW_1      IR_CR_IRTX_SWM_PW_1
#define IR_CR_IRTX_SWM_PW_1_POS  (0U)
#define IR_CR_IRTX_SWM_PW_1_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_1_MSK  (((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS)
#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_1_LEN) - 1) << IR_CR_IRTX_SWM_PW_1_POS))

/* 0x48 : irtx_swm_pw_2 */
#define IRTX_SWM_PW_2_OFFSET     (0x48)
#define IR_CR_IRTX_SWM_PW_2      IR_CR_IRTX_SWM_PW_2
#define IR_CR_IRTX_SWM_PW_2_POS  (0U)
#define IR_CR_IRTX_SWM_PW_2_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_2_MSK  (((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS)
#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_2_LEN) - 1) << IR_CR_IRTX_SWM_PW_2_POS))

/* 0x4C : irtx_swm_pw_3 */
#define IRTX_SWM_PW_3_OFFSET     (0x4C)
#define IR_CR_IRTX_SWM_PW_3      IR_CR_IRTX_SWM_PW_3
#define IR_CR_IRTX_SWM_PW_3_POS  (0U)
#define IR_CR_IRTX_SWM_PW_3_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_3_MSK  (((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS)
#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_3_LEN) - 1) << IR_CR_IRTX_SWM_PW_3_POS))

/* 0x50 : irtx_swm_pw_4 */
#define IRTX_SWM_PW_4_OFFSET     (0x50)
#define IR_CR_IRTX_SWM_PW_4      IR_CR_IRTX_SWM_PW_4
#define IR_CR_IRTX_SWM_PW_4_POS  (0U)
#define IR_CR_IRTX_SWM_PW_4_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_4_MSK  (((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS)
#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_4_LEN) - 1) << IR_CR_IRTX_SWM_PW_4_POS))

/* 0x54 : irtx_swm_pw_5 */
#define IRTX_SWM_PW_5_OFFSET     (0x54)
#define IR_CR_IRTX_SWM_PW_5      IR_CR_IRTX_SWM_PW_5
#define IR_CR_IRTX_SWM_PW_5_POS  (0U)
#define IR_CR_IRTX_SWM_PW_5_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_5_MSK  (((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS)
#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_5_LEN) - 1) << IR_CR_IRTX_SWM_PW_5_POS))

/* 0x58 : irtx_swm_pw_6 */
#define IRTX_SWM_PW_6_OFFSET     (0x58)
#define IR_CR_IRTX_SWM_PW_6      IR_CR_IRTX_SWM_PW_6
#define IR_CR_IRTX_SWM_PW_6_POS  (0U)
#define IR_CR_IRTX_SWM_PW_6_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_6_MSK  (((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS)
#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_6_LEN) - 1) << IR_CR_IRTX_SWM_PW_6_POS))

/* 0x5C : irtx_swm_pw_7 */
#define IRTX_SWM_PW_7_OFFSET     (0x5C)
#define IR_CR_IRTX_SWM_PW_7      IR_CR_IRTX_SWM_PW_7
#define IR_CR_IRTX_SWM_PW_7_POS  (0U)
#define IR_CR_IRTX_SWM_PW_7_LEN  (32U)
#define IR_CR_IRTX_SWM_PW_7_MSK  (((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS)
#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U << IR_CR_IRTX_SWM_PW_7_LEN) - 1) << IR_CR_IRTX_SWM_PW_7_POS))

/* 0x80 : irrx_config */
#define IRRX_CONFIG_OFFSET      (0x80)
#define IR_CR_IRRX_EN           IR_CR_IRRX_EN
#define IR_CR_IRRX_EN_POS       (0U)
#define IR_CR_IRRX_EN_LEN       (1U)
#define IR_CR_IRRX_EN_MSK       (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)
#define IR_CR_IRRX_EN_UMSK      (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS))
#define IR_CR_IRRX_IN_INV       IR_CR_IRRX_IN_INV
#define IR_CR_IRRX_IN_INV_POS   (1U)
#define IR_CR_IRRX_IN_INV_LEN   (1U)
#define IR_CR_IRRX_IN_INV_MSK   (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)
#define IR_CR_IRRX_IN_INV_UMSK  (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS))
#define IR_CR_IRRX_MODE         IR_CR_IRRX_MODE
#define IR_CR_IRRX_MODE_POS     (2U)
#define IR_CR_IRRX_MODE_LEN     (2U)
#define IR_CR_IRRX_MODE_MSK     (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)
#define IR_CR_IRRX_MODE_UMSK    (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS))
#define IR_CR_IRRX_DEG_EN       IR_CR_IRRX_DEG_EN
#define IR_CR_IRRX_DEG_EN_POS   (4U)
#define IR_CR_IRRX_DEG_EN_LEN   (1U)
#define IR_CR_IRRX_DEG_EN_MSK   (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)
#define IR_CR_IRRX_DEG_EN_UMSK  (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS))
#define IR_CR_IRRX_DEG_CNT      IR_CR_IRRX_DEG_CNT
#define IR_CR_IRRX_DEG_CNT_POS  (8U)
#define IR_CR_IRRX_DEG_CNT_LEN  (4U)
#define IR_CR_IRRX_DEG_CNT_MSK  (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)
#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS))

/* 0x84 : irrx_int_sts */
#define IRRX_INT_STS_OFFSET      (0x84)
#define IRRX_END_INT             IRRX_END_INT
#define IRRX_END_INT_POS         (0U)
#define IRRX_END_INT_LEN         (1U)
#define IRRX_END_INT_MSK         (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)
#define IRRX_END_INT_UMSK        (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS))
#define IR_CR_IRRX_END_MASK      IR_CR_IRRX_END_MASK
#define IR_CR_IRRX_END_MASK_POS  (8U)
#define IR_CR_IRRX_END_MASK_LEN  (1U)
#define IR_CR_IRRX_END_MASK_MSK  (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)
#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS))
#define IR_CR_IRRX_END_CLR       IR_CR_IRRX_END_CLR
#define IR_CR_IRRX_END_CLR_POS   (16U)
#define IR_CR_IRRX_END_CLR_LEN   (1U)
#define IR_CR_IRRX_END_CLR_MSK   (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)
#define IR_CR_IRRX_END_CLR_UMSK  (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS))
#define IR_CR_IRRX_END_EN        IR_CR_IRRX_END_EN
#define IR_CR_IRRX_END_EN_POS    (24U)
#define IR_CR_IRRX_END_EN_LEN    (1U)
#define IR_CR_IRRX_END_EN_MSK    (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)
#define IR_CR_IRRX_END_EN_UMSK   (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS))

/* 0x88 : irrx_pw_config */
#define IRRX_PW_CONFIG_OFFSET   (0x88)
#define IR_CR_IRRX_DATA_TH      IR_CR_IRRX_DATA_TH
#define IR_CR_IRRX_DATA_TH_POS  (0U)
#define IR_CR_IRRX_DATA_TH_LEN  (16U)
#define IR_CR_IRRX_DATA_TH_MSK  (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)
#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS))
#define IR_CR_IRRX_END_TH       IR_CR_IRRX_END_TH
#define IR_CR_IRRX_END_TH_POS   (16U)
#define IR_CR_IRRX_END_TH_LEN   (16U)
#define IR_CR_IRRX_END_TH_MSK   (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)
#define IR_CR_IRRX_END_TH_UMSK  (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS))

/* 0x90 : irrx_data_count */
#define IRRX_DATA_COUNT_OFFSET    (0x90)
#define IR_STS_IRRX_DATA_CNT      IR_STS_IRRX_DATA_CNT
#define IR_STS_IRRX_DATA_CNT_POS  (0U)
#define IR_STS_IRRX_DATA_CNT_LEN  (7U)
#define IR_STS_IRRX_DATA_CNT_MSK  (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)
#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS))

/* 0x94 : irrx_data_word0 */
#define IRRX_DATA_WORD0_OFFSET      (0x94)
#define IR_STS_IRRX_DATA_WORD0      IR_STS_IRRX_DATA_WORD0
#define IR_STS_IRRX_DATA_WORD0_POS  (0U)
#define IR_STS_IRRX_DATA_WORD0_LEN  (32U)
#define IR_STS_IRRX_DATA_WORD0_MSK  (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)
#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS))

/* 0x98 : irrx_data_word1 */
#define IRRX_DATA_WORD1_OFFSET      (0x98)
#define IR_STS_IRRX_DATA_WORD1      IR_STS_IRRX_DATA_WORD1
#define IR_STS_IRRX_DATA_WORD1_POS  (0U)
#define IR_STS_IRRX_DATA_WORD1_LEN  (32U)
#define IR_STS_IRRX_DATA_WORD1_MSK  (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)
#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS))

/* 0xC0 : irrx_swm_fifo_config_0 */
#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0)
#define IR_RX_FIFO_CLR                IR_RX_FIFO_CLR
#define IR_RX_FIFO_CLR_POS            (0U)
#define IR_RX_FIFO_CLR_LEN            (1U)
#define IR_RX_FIFO_CLR_MSK            (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)
#define IR_RX_FIFO_CLR_UMSK           (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS))
#define IR_RX_FIFO_OVERFLOW           IR_RX_FIFO_OVERFLOW
#define IR_RX_FIFO_OVERFLOW_POS       (2U)
#define IR_RX_FIFO_OVERFLOW_LEN       (1U)
#define IR_RX_FIFO_OVERFLOW_MSK       (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)
#define IR_RX_FIFO_OVERFLOW_UMSK      (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS))
#define IR_RX_FIFO_UNDERFLOW          IR_RX_FIFO_UNDERFLOW
#define IR_RX_FIFO_UNDERFLOW_POS      (3U)
#define IR_RX_FIFO_UNDERFLOW_LEN      (1U)
#define IR_RX_FIFO_UNDERFLOW_MSK      (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)
#define IR_RX_FIFO_UNDERFLOW_UMSK     (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS))
#define IR_RX_FIFO_CNT                IR_RX_FIFO_CNT
#define IR_RX_FIFO_CNT_POS            (4U)
#define IR_RX_FIFO_CNT_LEN            (7U)
#define IR_RX_FIFO_CNT_MSK            (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)
#define IR_RX_FIFO_CNT_UMSK           (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS))

/* 0xC4 : irrx_swm_fifo_rdata */
#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4)
#define IR_RX_FIFO_RDATA           IR_RX_FIFO_RDATA
#define IR_RX_FIFO_RDATA_POS       (0U)
#define IR_RX_FIFO_RDATA_LEN       (16U)
#define IR_RX_FIFO_RDATA_MSK       (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)
#define IR_RX_FIFO_RDATA_UMSK      (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS))

struct ir_reg {
    /* 0x0 : irtx_config */
    union {
        struct
        {
            uint32_t cr_irtx_en            : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_irtx_out_inv       : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_irtx_mod_en        : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_irtx_swm_en        : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_irtx_data_en       : 1;  /* [    4],        r/w,        0x1 */
            uint32_t cr_irtx_logic0_hl_inv : 1;  /* [    5],        r/w,        0x0 */
            uint32_t cr_irtx_logic1_hl_inv : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7            : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t cr_irtx_head_en       : 1;  /* [    8],        r/w,        0x1 */
            uint32_t cr_irtx_head_hl_inv   : 1;  /* [    9],        r/w,        0x0 */
            uint32_t cr_irtx_tail_en       : 1;  /* [   10],        r/w,        0x1 */
            uint32_t cr_irtx_tail_hl_inv   : 1;  /* [   11],        r/w,        0x0 */
            uint32_t cr_irtx_data_num      : 6;  /* [17:12],        r/w,       0x1f */
            uint32_t reserved_18_31        : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_config;

    /* 0x4 : irtx_int_sts */
    union {
        struct
        {
            uint32_t irtx_end_int     : 1; /* [    0],          r,        0x0 */
            uint32_t reserved_1_7     : 7; /* [ 7: 1],       rsvd,        0x0 */
            uint32_t cr_irtx_end_mask : 1; /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_15    : 7; /* [15: 9],       rsvd,        0x0 */
            uint32_t cr_irtx_end_clr  : 1; /* [   16],        w1c,        0x0 */
            uint32_t reserved_17_23   : 7; /* [23:17],       rsvd,        0x0 */
            uint32_t cr_irtx_end_en   : 1; /* [   24],        r/w,        0x1 */
            uint32_t reserved_25_31   : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_int_sts;

    /* 0x8 : irtx_data_word0 */
    union {
        struct
        {
            uint32_t cr_irtx_data_word0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_data_word0;

    /* 0xC : irtx_data_word1 */
    union {
        struct
        {
            uint32_t cr_irtx_data_word1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_data_word1;

    /* 0x10 : irtx_pulse_width */
    union {
        struct
        {
            uint32_t cr_irtx_pw_unit   : 12; /* [11: 0],        r/w,      0x464 */
            uint32_t reserved_12_15    : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t cr_irtx_mod_ph0_w : 8;  /* [23:16],        r/w,       0x11 */
            uint32_t cr_irtx_mod_ph1_w : 8;  /* [31:24],        r/w,       0x22 */
        } BF;
        uint32_t WORD;
    } irtx_pulse_width;

    /* 0x14 : irtx_pw */
    union {
        struct
        {
            uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0],        r/w,        0x0 */
            uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4],        r/w,        0x0 */
            uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8],        r/w,        0x0 */
            uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12],        r/w,        0x2 */
            uint32_t cr_irtx_head_ph0_w   : 4; /* [19:16],        r/w,        0xf */
            uint32_t cr_irtx_head_ph1_w   : 4; /* [23:20],        r/w,        0x7 */
            uint32_t cr_irtx_tail_ph0_w   : 4; /* [27:24],        r/w,        0x0 */
            uint32_t cr_irtx_tail_ph1_w   : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_pw;

    /* 0x18  reserved */
    uint8_t RESERVED0x18[40];

    /* 0x40 : irtx_swm_pw_0 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_0;

    /* 0x44 : irtx_swm_pw_1 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_1;

    /* 0x48 : irtx_swm_pw_2 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_2;

    /* 0x4C : irtx_swm_pw_3 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_3;

    /* 0x50 : irtx_swm_pw_4 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_4;

    /* 0x54 : irtx_swm_pw_5 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_5;

    /* 0x58 : irtx_swm_pw_6 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_6;

    /* 0x5C : irtx_swm_pw_7 */
    union {
        struct
        {
            uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } irtx_swm_pw_7;

    /* 0x60  reserved */
    uint8_t RESERVED0x60[32];

    /* 0x80 : irrx_config */
    union {
        struct
        {
            uint32_t cr_irrx_en      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_irrx_in_inv  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t cr_irrx_mode    : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t cr_irrx_deg_en  : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_7    : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t cr_irrx_deg_cnt : 4;  /* [11: 8],        r/w,        0x0 */
            uint32_t reserved_12_31  : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_config;

    /* 0x84 : irrx_int_sts */
    union {
        struct
        {
            uint32_t irrx_end_int     : 1; /* [    0],          r,        0x0 */
            uint32_t reserved_1_7     : 7; /* [ 7: 1],       rsvd,        0x0 */
            uint32_t cr_irrx_end_mask : 1; /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_15    : 7; /* [15: 9],       rsvd,        0x0 */
            uint32_t cr_irrx_end_clr  : 1; /* [   16],        w1c,        0x0 */
            uint32_t reserved_17_23   : 7; /* [23:17],       rsvd,        0x0 */
            uint32_t cr_irrx_end_en   : 1; /* [   24],        r/w,        0x1 */
            uint32_t reserved_25_31   : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_int_sts;

    /* 0x88 : irrx_pw_config */
    union {
        struct
        {
            uint32_t cr_irrx_data_th : 16; /* [15: 0],        r/w,      0xd47 */
            uint32_t cr_irrx_end_th  : 16; /* [31:16],        r/w,     0x2327 */
        } BF;
        uint32_t WORD;
    } irrx_pw_config;

    /* 0x8c  reserved */
    uint8_t RESERVED0x8c[4];

    /* 0x90 : irrx_data_count */
    union {
        struct
        {
            uint32_t sts_irrx_data_cnt : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31     : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_data_count;

    /* 0x94 : irrx_data_word0 */
    union {
        struct
        {
            uint32_t sts_irrx_data_word0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_data_word0;

    /* 0x98 : irrx_data_word1 */
    union {
        struct
        {
            uint32_t sts_irrx_data_word1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_data_word1;

    /* 0x9c  reserved */
    uint8_t RESERVED0x9c[36];

    /* 0xC0 : irrx_swm_fifo_config_0 */
    union {
        struct
        {
            uint32_t rx_fifo_clr       : 1;  /* [    0],        w1c,        0x0 */
            uint32_t reserved_1        : 1;  /* [    1],       rsvd,        0x0 */
            uint32_t rx_fifo_overflow  : 1;  /* [    2],          r,        0x0 */
            uint32_t rx_fifo_underflow : 1;  /* [    3],          r,        0x0 */
            uint32_t rx_fifo_cnt       : 7;  /* [10: 4],          r,        0x0 */
            uint32_t reserved_11_31    : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_swm_fifo_config_0;

    /* 0xC4 : irrx_swm_fifo_rdata */
    union {
        struct
        {
            uint32_t rx_fifo_rdata  : 16; /* [15: 0],          r,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } irrx_swm_fifo_rdata;
};

typedef volatile struct ir_reg ir_reg_t;

#endif /* __IR_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/kys_reg.h
================================================
/**
  ******************************************************************************
  * @file    kys_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __KYS_REG_H__
#define __KYS_REG_H__

#include "bl702.h"

/* 0x0 : ks_ctrl */
#define KYS_KS_CTRL_OFFSET (0x0)
#define KYS_KS_EN          KYS_KS_EN
#define KYS_KS_EN_POS      (0U)
#define KYS_KS_EN_LEN      (1U)
#define KYS_KS_EN_MSK      (((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS)
#define KYS_KS_EN_UMSK     (~(((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS))
#define KYS_GHOST_EN       KYS_GHOST_EN
#define KYS_GHOST_EN_POS   (2U)
#define KYS_GHOST_EN_LEN   (1U)
#define KYS_GHOST_EN_MSK   (((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS)
#define KYS_GHOST_EN_UMSK  (~(((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS))
#define KYS_DEG_EN         KYS_DEG_EN
#define KYS_DEG_EN_POS     (3U)
#define KYS_DEG_EN_LEN     (1U)
#define KYS_DEG_EN_MSK     (((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS)
#define KYS_DEG_EN_UMSK    (~(((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS))
#define KYS_DEG_CNT        KYS_DEG_CNT
#define KYS_DEG_CNT_POS    (4U)
#define KYS_DEG_CNT_LEN    (4U)
#define KYS_DEG_CNT_MSK    (((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS)
#define KYS_DEG_CNT_UMSK   (~(((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS))
#define KYS_RC_EXT         KYS_RC_EXT
#define KYS_RC_EXT_POS     (8U)
#define KYS_RC_EXT_LEN     (2U)
#define KYS_RC_EXT_MSK     (((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS)
#define KYS_RC_EXT_UMSK    (~(((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS))
#define KYS_ROW_NUM        KYS_ROW_NUM
#define KYS_ROW_NUM_POS    (16U)
#define KYS_ROW_NUM_LEN    (3U)
#define KYS_ROW_NUM_MSK    (((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS)
#define KYS_ROW_NUM_UMSK   (~(((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS))
#define KYS_COL_NUM        KYS_COL_NUM
#define KYS_COL_NUM_POS    (20U)
#define KYS_COL_NUM_LEN    (5U)
#define KYS_COL_NUM_MSK    (((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS)
#define KYS_COL_NUM_UMSK   (~(((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS))

/* 0x10 : ks_int_en */
#define KYS_KS_INT_EN_OFFSET (0x10)
#define KYS_KS_INT_EN        KYS_KS_INT_EN
#define KYS_KS_INT_EN_POS    (0U)
#define KYS_KS_INT_EN_LEN    (1U)
#define KYS_KS_INT_EN_MSK    (((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS)
#define KYS_KS_INT_EN_UMSK   (~(((1U << KYS_KS_INT_EN_LEN) - 1) << KYS_KS_INT_EN_POS))

/* 0x14 : ks_int_sts */
#define KYS_KS_INT_STS_OFFSET  (0x14)
#define KYS_KEYCODE_VALID      KYS_KEYCODE_VALID
#define KYS_KEYCODE_VALID_POS  (0U)
#define KYS_KEYCODE_VALID_LEN  (4U)
#define KYS_KEYCODE_VALID_MSK  (((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS)
#define KYS_KEYCODE_VALID_UMSK (~(((1U << KYS_KEYCODE_VALID_LEN) - 1) << KYS_KEYCODE_VALID_POS))

/* 0x18 : keycode_clr */
#define KYS_KEYCODE_CLR_OFFSET (0x18)
#define KYS_KEYCODE_CLR        KYS_KEYCODE_CLR
#define KYS_KEYCODE_CLR_POS    (0U)
#define KYS_KEYCODE_CLR_LEN    (4U)
#define KYS_KEYCODE_CLR_MSK    (((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS)
#define KYS_KEYCODE_CLR_UMSK   (~(((1U << KYS_KEYCODE_CLR_LEN) - 1) << KYS_KEYCODE_CLR_POS))

/* 0x1C : keycode_value */
#define KYS_KEYCODE_VALUE_OFFSET (0x1C)
#define KYS_KEYCODE0             KYS_KEYCODE0
#define KYS_KEYCODE0_POS         (0U)
#define KYS_KEYCODE0_LEN         (8U)
#define KYS_KEYCODE0_MSK         (((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS)
#define KYS_KEYCODE0_UMSK        (~(((1U << KYS_KEYCODE0_LEN) - 1) << KYS_KEYCODE0_POS))
#define KYS_KEYCODE1             KYS_KEYCODE1
#define KYS_KEYCODE1_POS         (8U)
#define KYS_KEYCODE1_LEN         (8U)
#define KYS_KEYCODE1_MSK         (((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS)
#define KYS_KEYCODE1_UMSK        (~(((1U << KYS_KEYCODE1_LEN) - 1) << KYS_KEYCODE1_POS))
#define KYS_KEYCODE2             KYS_KEYCODE2
#define KYS_KEYCODE2_POS         (16U)
#define KYS_KEYCODE2_LEN         (8U)
#define KYS_KEYCODE2_MSK         (((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS)
#define KYS_KEYCODE2_UMSK        (~(((1U << KYS_KEYCODE2_LEN) - 1) << KYS_KEYCODE2_POS))
#define KYS_KEYCODE3             KYS_KEYCODE3
#define KYS_KEYCODE3_POS         (24U)
#define KYS_KEYCODE3_LEN         (8U)
#define KYS_KEYCODE3_MSK         (((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS)
#define KYS_KEYCODE3_UMSK        (~(((1U << KYS_KEYCODE3_LEN) - 1) << KYS_KEYCODE3_POS))

struct kys_reg {
    /* 0x0 : ks_ctrl */
    union {
        struct
        {
            uint32_t ks_en          : 1; /* [    0],        r/w,        0x0 */
            uint32_t reserved_1     : 1; /* [    1],       rsvd,        0x0 */
            uint32_t ghost_en       : 1; /* [    2],        r/w,        0x0 */
            uint32_t deg_en         : 1; /* [    3],        r/w,        0x0 */
            uint32_t deg_cnt        : 4; /* [ 7: 4],        r/w,        0x0 */
            uint32_t rc_ext         : 2; /* [ 9: 8],        r/w,        0x3 */
            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
            uint32_t row_num        : 3; /* [18:16],        r/w,        0x7 */
            uint32_t reserved_19    : 1; /* [   19],       rsvd,        0x0 */
            uint32_t col_num        : 5; /* [24:20],        r/w,       0x13 */
            uint32_t reserved_25_31 : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ks_ctrl;

    /* 0x4  reserved */
    uint8_t RESERVED0x4[12];

    /* 0x10 : ks_int_en */
    union {
        struct
        {
            uint32_t ks_int_en     : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ks_int_en;

    /* 0x14 : ks_int_sts */
    union {
        struct
        {
            uint32_t keycode_valid : 4;  /* [ 3: 0],          r,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ks_int_sts;

    /* 0x18 : keycode_clr */
    union {
        struct
        {
            uint32_t keycode_clr   : 4;  /* [ 3: 0],        w1c,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } keycode_clr;

    /* 0x1C : keycode_value */
    union {
        struct
        {
            uint32_t keycode0 : 8; /* [ 7: 0],          r,       0xff */
            uint32_t keycode1 : 8; /* [15: 8],          r,       0xff */
            uint32_t keycode2 : 8; /* [23:16],          r,       0xff */
            uint32_t keycode3 : 8; /* [31:24],          r,       0xff */
        } BF;
        uint32_t WORD;
    } keycode_value;
};

typedef volatile struct kys_reg kys_reg_t;

#endif /* __KYS_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/l1c_reg.h
================================================
/**
  ******************************************************************************
  * @file    l1c_reg.h
  * @version V1.2
  * @date    2020-07-08
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __L1C_REG_H__
#define __L1C_REG_H__

#include "bl702.h"

/* 0x0 : l1c_config */
#define L1C_CONFIG_OFFSET            (0x0)
#define L1C_CACHEABLE                L1C_CACHEABLE
#define L1C_CACHEABLE_POS            (0U)
#define L1C_CACHEABLE_LEN            (1U)
#define L1C_CACHEABLE_MSK            (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
#define L1C_CACHEABLE_UMSK           (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
#define L1C_CNT_EN                   L1C_CNT_EN
#define L1C_CNT_EN_POS               (1U)
#define L1C_CNT_EN_LEN               (1U)
#define L1C_CNT_EN_MSK               (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
#define L1C_CNT_EN_UMSK              (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
#define L1C_INVALID_EN               L1C_INVALID_EN
#define L1C_INVALID_EN_POS           (2U)
#define L1C_INVALID_EN_LEN           (1U)
#define L1C_INVALID_EN_MSK           (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
#define L1C_INVALID_EN_UMSK          (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
#define L1C_INVALID_DONE             L1C_INVALID_DONE
#define L1C_INVALID_DONE_POS         (3U)
#define L1C_INVALID_DONE_LEN         (1U)
#define L1C_INVALID_DONE_MSK         (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
#define L1C_INVALID_DONE_UMSK        (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
#define L1C_WT_EN                    L1C_WT_EN
#define L1C_WT_EN_POS                (4U)
#define L1C_WT_EN_LEN                (1U)
#define L1C_WT_EN_MSK                (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)
#define L1C_WT_EN_UMSK               (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS))
#define L1C_WB_EN                    L1C_WB_EN
#define L1C_WB_EN_POS                (5U)
#define L1C_WB_EN_LEN                (1U)
#define L1C_WB_EN_MSK                (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)
#define L1C_WB_EN_UMSK               (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS))
#define L1C_WA_EN                    L1C_WA_EN
#define L1C_WA_EN_POS                (6U)
#define L1C_WA_EN_LEN                (1U)
#define L1C_WA_EN_MSK                (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)
#define L1C_WA_EN_UMSK               (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS))
#define L1C_RANDOM_REPLACE           L1C_RANDOM_REPLACE
#define L1C_RANDOM_REPLACE_POS       (7U)
#define L1C_RANDOM_REPLACE_LEN       (1U)
#define L1C_RANDOM_REPLACE_MSK       (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)
#define L1C_RANDOM_REPLACE_UMSK      (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS))
#define L1C_WAY_DIS                  L1C_WAY_DIS
#define L1C_WAY_DIS_POS              (8U)
#define L1C_WAY_DIS_LEN              (4U)
#define L1C_WAY_DIS_MSK              (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
#define L1C_WAY_DIS_UMSK             (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
#define L1C_IROM_2T_ACCESS           L1C_IROM_2T_ACCESS
#define L1C_IROM_2T_ACCESS_POS       (12U)
#define L1C_IROM_2T_ACCESS_LEN       (1U)
#define L1C_IROM_2T_ACCESS_MSK       (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
#define L1C_IROM_2T_ACCESS_UMSK      (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
#define L1C_BYPASS                   L1C_BYPASS
#define L1C_BYPASS_POS               (14U)
#define L1C_BYPASS_LEN               (1U)
#define L1C_BYPASS_MSK               (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
#define L1C_BYPASS_UMSK              (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
#define L1C_BMX_ERR_EN               L1C_BMX_ERR_EN
#define L1C_BMX_ERR_EN_POS           (15U)
#define L1C_BMX_ERR_EN_LEN           (1U)
#define L1C_BMX_ERR_EN_MSK           (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
#define L1C_BMX_ERR_EN_UMSK          (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
#define L1C_BMX_ARB_MODE             L1C_BMX_ARB_MODE
#define L1C_BMX_ARB_MODE_POS         (16U)
#define L1C_BMX_ARB_MODE_LEN         (2U)
#define L1C_BMX_ARB_MODE_MSK         (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
#define L1C_BMX_ARB_MODE_UMSK        (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
#define L1C_BMX_TIMEOUT_EN           L1C_BMX_TIMEOUT_EN
#define L1C_BMX_TIMEOUT_EN_POS       (20U)
#define L1C_BMX_TIMEOUT_EN_LEN       (4U)
#define L1C_BMX_TIMEOUT_EN_MSK       (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
#define L1C_BMX_TIMEOUT_EN_UMSK      (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
#define L1C_BMX_BUSY_OPTION_DIS      L1C_BMX_BUSY_OPTION_DIS
#define L1C_BMX_BUSY_OPTION_DIS_POS  (24U)
#define L1C_BMX_BUSY_OPTION_DIS_LEN  (1U)
#define L1C_BMX_BUSY_OPTION_DIS_MSK  (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
#define L1C_EARLY_RESP_DIS           L1C_EARLY_RESP_DIS
#define L1C_EARLY_RESP_DIS_POS       (25U)
#define L1C_EARLY_RESP_DIS_LEN       (1U)
#define L1C_EARLY_RESP_DIS_MSK       (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
#define L1C_EARLY_RESP_DIS_UMSK      (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
#define L1C_WRAP_DIS                 L1C_WRAP_DIS
#define L1C_WRAP_DIS_POS             (26U)
#define L1C_WRAP_DIS_LEN             (1U)
#define L1C_WRAP_DIS_MSK             (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
#define L1C_WRAP_DIS_UMSK            (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
#define L1C_FLUSH_EN                 L1C_FLUSH_EN
#define L1C_FLUSH_EN_POS             (28U)
#define L1C_FLUSH_EN_LEN             (1U)
#define L1C_FLUSH_EN_MSK             (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)
#define L1C_FLUSH_EN_UMSK            (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS))
#define L1C_FLUSH_DONE               L1C_FLUSH_DONE
#define L1C_FLUSH_DONE_POS           (29U)
#define L1C_FLUSH_DONE_LEN           (1U)
#define L1C_FLUSH_DONE_MSK           (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)
#define L1C_FLUSH_DONE_UMSK          (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS))

/* 0x4 : hit_cnt_lsb */
#define L1C_HIT_CNT_LSB_OFFSET (0x4)
#define L1C_HIT_CNT_LSB        L1C_HIT_CNT_LSB
#define L1C_HIT_CNT_LSB_POS    (0U)
#define L1C_HIT_CNT_LSB_LEN    (32U)
#define L1C_HIT_CNT_LSB_MSK    (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
#define L1C_HIT_CNT_LSB_UMSK   (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))

/* 0x8 : hit_cnt_msb */
#define L1C_HIT_CNT_MSB_OFFSET (0x8)
#define L1C_HIT_CNT_MSB        L1C_HIT_CNT_MSB
#define L1C_HIT_CNT_MSB_POS    (0U)
#define L1C_HIT_CNT_MSB_LEN    (32U)
#define L1C_HIT_CNT_MSB_MSK    (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
#define L1C_HIT_CNT_MSB_UMSK   (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))

/* 0xC : miss_cnt */
#define L1C_MISS_CNT_OFFSET (0xC)
#define L1C_MISS_CNT        L1C_MISS_CNT
#define L1C_MISS_CNT_POS    (0U)
#define L1C_MISS_CNT_LEN    (32U)
#define L1C_MISS_CNT_MSK    (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
#define L1C_MISS_CNT_UMSK   (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))

/* 0x10 : l1c_misc */
#define L1C_MISC_OFFSET (0x10)
#define L1C_FSM         L1C_FSM
#define L1C_FSM_POS     (28U)
#define L1C_FSM_LEN     (3U)
#define L1C_FSM_MSK     (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)
#define L1C_FSM_UMSK    (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS))

/* 0x200 : l1c_bmx_err_addr_en */
#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
#define L1C_BMX_ERR_ADDR_DIS       L1C_BMX_ERR_ADDR_DIS
#define L1C_BMX_ERR_ADDR_DIS_POS   (0U)
#define L1C_BMX_ERR_ADDR_DIS_LEN   (1U)
#define L1C_BMX_ERR_ADDR_DIS_MSK   (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
#define L1C_BMX_ERR_ADDR_DIS_UMSK  (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
#define L1C_BMX_ERR_DEC            L1C_BMX_ERR_DEC
#define L1C_BMX_ERR_DEC_POS        (4U)
#define L1C_BMX_ERR_DEC_LEN        (1U)
#define L1C_BMX_ERR_DEC_MSK        (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
#define L1C_BMX_ERR_DEC_UMSK       (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
#define L1C_BMX_ERR_TZ             L1C_BMX_ERR_TZ
#define L1C_BMX_ERR_TZ_POS         (5U)
#define L1C_BMX_ERR_TZ_LEN         (1U)
#define L1C_BMX_ERR_TZ_MSK         (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
#define L1C_BMX_ERR_TZ_UMSK        (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
#define L1C_HSEL_OPTION            L1C_HSEL_OPTION
#define L1C_HSEL_OPTION_POS        (16U)
#define L1C_HSEL_OPTION_LEN        (4U)
#define L1C_HSEL_OPTION_MSK        (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
#define L1C_HSEL_OPTION_UMSK       (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))

/* 0x204 : l1c_bmx_err_addr */
#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
#define L1C_BMX_ERR_ADDR        L1C_BMX_ERR_ADDR
#define L1C_BMX_ERR_ADDR_POS    (0U)
#define L1C_BMX_ERR_ADDR_LEN    (32U)
#define L1C_BMX_ERR_ADDR_MSK    (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
#define L1C_BMX_ERR_ADDR_UMSK   (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))

/* 0x208 : irom1_misr_dataout_0 */
#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
#define L1C_IROM1_MISR_DATAOUT_0        L1C_IROM1_MISR_DATAOUT_0
#define L1C_IROM1_MISR_DATAOUT_0_POS    (0U)
#define L1C_IROM1_MISR_DATAOUT_0_LEN    (32U)
#define L1C_IROM1_MISR_DATAOUT_0_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
#define L1C_IROM1_MISR_DATAOUT_0_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))

/* 0x20C : irom1_misr_dataout_1 */
#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
#define L1C_IROM1_MISR_DATAOUT_1        L1C_IROM1_MISR_DATAOUT_1
#define L1C_IROM1_MISR_DATAOUT_1_POS    (0U)
#define L1C_IROM1_MISR_DATAOUT_1_LEN    (32U)
#define L1C_IROM1_MISR_DATAOUT_1_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)
#define L1C_IROM1_MISR_DATAOUT_1_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS))

/* 0x210 : cpu_clk_gate */
#define L1C_CPU_CLK_GATE_OFFSET       (0x210)
#define L1C_FORCE_E21_CLOCK_ON_0      L1C_FORCE_E21_CLOCK_ON_0
#define L1C_FORCE_E21_CLOCK_ON_0_POS  (0U)
#define L1C_FORCE_E21_CLOCK_ON_0_LEN  (1U)
#define L1C_FORCE_E21_CLOCK_ON_0_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
#define L1C_FORCE_E21_CLOCK_ON_1      L1C_FORCE_E21_CLOCK_ON_1
#define L1C_FORCE_E21_CLOCK_ON_1_POS  (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_LEN  (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
#define L1C_FORCE_E21_CLOCK_ON_2      L1C_FORCE_E21_CLOCK_ON_2
#define L1C_FORCE_E21_CLOCK_ON_2_POS  (2U)
#define L1C_FORCE_E21_CLOCK_ON_2_LEN  (1U)
#define L1C_FORCE_E21_CLOCK_ON_2_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))

struct l1c_reg {
    /* 0x0 : l1c_config */
    union {
        struct
        {
            uint32_t l1c_cacheable           : 1; /* [    0],        r/w,        0x0 */
            uint32_t l1c_cnt_en              : 1; /* [    1],        r/w,        0x0 */
            uint32_t l1c_invalid_en          : 1; /* [    2],        r/w,        0x0 */
            uint32_t l1c_invalid_done        : 1; /* [    3],          r,        0x0 */
            uint32_t l1c_wt_en               : 1; /* [    4],        r/w,        0x0 */
            uint32_t l1c_wb_en               : 1; /* [    5],        r/w,        0x1 */
            uint32_t l1c_wa_en               : 1; /* [    6],        r/w,        0x1 */
            uint32_t l1c_random_replace      : 1; /* [    7],        r/w,        0x0 */
            uint32_t l1c_way_dis             : 4; /* [11: 8],        r/w,        0xf */
            uint32_t irom_2t_access          : 1; /* [   12],        r/w,        0x0 */
            uint32_t reserved_13             : 1; /* [   13],       rsvd,        0x0 */
            uint32_t l1c_bypass              : 1; /* [   14],        r/w,        0x0 */
            uint32_t l1c_bmx_err_en          : 1; /* [   15],        r/w,        0x0 */
            uint32_t l1c_bmx_arb_mode        : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_19          : 2; /* [19:18],       rsvd,        0x0 */
            uint32_t l1c_bmx_timeout_en      : 4; /* [23:20],        r/w,        0x0 */
            uint32_t l1c_bmx_busy_option_dis : 1; /* [   24],        r/w,        0x0 */
            uint32_t early_resp_dis          : 1; /* [   25],        r/w,        0x1 */
            uint32_t wrap_dis                : 1; /* [   26],        r/w,        0x1 */
            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
            uint32_t l1c_flush_en            : 1; /* [   28],        r/w,        0x0 */
            uint32_t l1c_flush_done          : 1; /* [   29],          r,        0x0 */
            uint32_t reserved_31_30          : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } l1c_config;

    /* 0x4 : hit_cnt_lsb */
    union {
        struct
        {
            uint32_t hit_cnt_lsb : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } hit_cnt_lsb;

    /* 0x8 : hit_cnt_msb */
    union {
        struct
        {
            uint32_t hit_cnt_msb : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } hit_cnt_msb;

    /* 0xC : miss_cnt */
    union {
        struct
        {
            uint32_t miss_cnt : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } miss_cnt;

    /* 0x10 : l1c_misc */
    union {
        struct
        {
            uint32_t reserved_0_27 : 28; /* [27: 0],       rsvd,        0x0 */
            uint32_t l1c_fsm       : 3;  /* [30:28],          r,        0x0 */
            uint32_t reserved_31   : 1;  /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } l1c_misc;

    /* 0x14  reserved */
    uint8_t RESERVED0x14[492];

    /* 0x200 : l1c_bmx_err_addr_en */
    union {
        struct
        {
            uint32_t l1c_bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t l1c_bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
            uint32_t l1c_bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
            uint32_t reserved_6_15        : 10; /* [15: 6],       rsvd,        0x0 */
            uint32_t l1c_hsel_option      : 4;  /* [19:16],        r/w,        0x0 */
            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } l1c_bmx_err_addr_en;

    /* 0x204 : l1c_bmx_err_addr */
    union {
        struct
        {
            uint32_t l1c_bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } l1c_bmx_err_addr;

    /* 0x208 : irom1_misr_dataout_0 */
    union {
        struct
        {
            uint32_t irom1_misr_dataout_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } irom1_misr_dataout_0;

    /* 0x20C : irom1_misr_dataout_1 */
    union {
        struct
        {
            uint32_t irom1_misr_dataout_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } irom1_misr_dataout_1;

    /* 0x210 : cpu_clk_gate */
    union {
        struct
        {
            uint32_t force_e21_clock_on_0 : 1;  /* [    0],        r/w,        0x0 */
            uint32_t force_e21_clock_on_1 : 1;  /* [    1],        r/w,        0x0 */
            uint32_t force_e21_clock_on_2 : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31        : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } cpu_clk_gate;
};

typedef volatile struct l1c_reg l1c_reg_t;

#endif /* __L1C_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/mjpeg_reg.h
================================================
/**
  ******************************************************************************
  * @file    mjpeg_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __MJPEG_REG_H__
#define __MJPEG_REG_H__

#include "bl702.h"

/* 0x0 : mjpeg_control_1 */
#define MJPEG_CONTROL_1_OFFSET          (0x0)
#define MJPEG_REG_MJPEG_ENABLE          MJPEG_REG_MJPEG_ENABLE
#define MJPEG_REG_MJPEG_ENABLE_POS      (0U)
#define MJPEG_REG_MJPEG_ENABLE_LEN      (1U)
#define MJPEG_REG_MJPEG_ENABLE_MSK      (((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS)
#define MJPEG_REG_MJPEG_ENABLE_UMSK     (~(((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS))
#define MJPEG_REG_MJPEG_BIT_ORDER       MJPEG_REG_MJPEG_BIT_ORDER
#define MJPEG_REG_MJPEG_BIT_ORDER_POS   (1U)
#define MJPEG_REG_MJPEG_BIT_ORDER_LEN   (1U)
#define MJPEG_REG_MJPEG_BIT_ORDER_MSK   (((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS)
#define MJPEG_REG_MJPEG_BIT_ORDER_UMSK  (~(((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS))
#define MJPEG_REG_ORDER_U_EVEN          MJPEG_REG_ORDER_U_EVEN
#define MJPEG_REG_ORDER_U_EVEN_POS      (2U)
#define MJPEG_REG_ORDER_U_EVEN_LEN      (1U)
#define MJPEG_REG_ORDER_U_EVEN_MSK      (((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS)
#define MJPEG_REG_ORDER_U_EVEN_UMSK     (~(((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS))
#define MJPEG_REG_WR_OVER_STOP          MJPEG_REG_WR_OVER_STOP
#define MJPEG_REG_WR_OVER_STOP_POS      (3U)
#define MJPEG_REG_WR_OVER_STOP_LEN      (1U)
#define MJPEG_REG_WR_OVER_STOP_MSK      (((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS)
#define MJPEG_REG_WR_OVER_STOP_UMSK     (~(((1U << MJPEG_REG_WR_OVER_STOP_LEN) - 1) << MJPEG_REG_WR_OVER_STOP_POS))
#define MJPEG_REG_LAST_HF_WBLK_DMY      MJPEG_REG_LAST_HF_WBLK_DMY
#define MJPEG_REG_LAST_HF_WBLK_DMY_POS  (4U)
#define MJPEG_REG_LAST_HF_WBLK_DMY_LEN  (1U)
#define MJPEG_REG_LAST_HF_WBLK_DMY_MSK  (((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS)
#define MJPEG_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS))
#define MJPEG_REG_LAST_HF_HBLK_DMY      MJPEG_REG_LAST_HF_HBLK_DMY
#define MJPEG_REG_LAST_HF_HBLK_DMY_POS  (5U)
#define MJPEG_REG_LAST_HF_HBLK_DMY_LEN  (1U)
#define MJPEG_REG_LAST_HF_HBLK_DMY_MSK  (((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS)
#define MJPEG_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS))
#define MJPEG_REG_REFLECT_DMY           MJPEG_REG_REFLECT_DMY
#define MJPEG_REG_REFLECT_DMY_POS       (6U)
#define MJPEG_REG_REFLECT_DMY_LEN       (1U)
#define MJPEG_REG_REFLECT_DMY_MSK       (((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS)
#define MJPEG_REG_REFLECT_DMY_UMSK      (~(((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS))
#define MJPEG_REG_H_BUST                MJPEG_REG_H_BUST
#define MJPEG_REG_H_BUST_POS            (8U)
#define MJPEG_REG_H_BUST_LEN            (2U)
#define MJPEG_REG_H_BUST_MSK            (((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS)
#define MJPEG_REG_H_BUST_UMSK           (~(((1U << MJPEG_REG_H_BUST_LEN) - 1) << MJPEG_REG_H_BUST_POS))
#define MJPEG_REG_YUV_MODE              MJPEG_REG_YUV_MODE
#define MJPEG_REG_YUV_MODE_POS          (12U)
#define MJPEG_REG_YUV_MODE_LEN          (2U)
#define MJPEG_REG_YUV_MODE_MSK          (((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS)
#define MJPEG_REG_YUV_MODE_UMSK         (~(((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS))
#define MJPEG_REG_Q_MODE                MJPEG_REG_Q_MODE
#define MJPEG_REG_Q_MODE_POS            (16U)
#define MJPEG_REG_Q_MODE_LEN            (7U)
#define MJPEG_REG_Q_MODE_MSK            (((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS)
#define MJPEG_REG_Q_MODE_UMSK           (~(((1U << MJPEG_REG_Q_MODE_LEN) - 1) << MJPEG_REG_Q_MODE_POS))
#define MJPEG_REG_Y0_ORDER              MJPEG_REG_Y0_ORDER
#define MJPEG_REG_Y0_ORDER_POS          (24U)
#define MJPEG_REG_Y0_ORDER_LEN          (2U)
#define MJPEG_REG_Y0_ORDER_MSK          (((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS)
#define MJPEG_REG_Y0_ORDER_UMSK         (~(((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS))
#define MJPEG_REG_U0_ORDER              MJPEG_REG_U0_ORDER
#define MJPEG_REG_U0_ORDER_POS          (26U)
#define MJPEG_REG_U0_ORDER_LEN          (2U)
#define MJPEG_REG_U0_ORDER_MSK          (((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS)
#define MJPEG_REG_U0_ORDER_UMSK         (~(((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS))
#define MJPEG_REG_Y1_ORDER              MJPEG_REG_Y1_ORDER
#define MJPEG_REG_Y1_ORDER_POS          (28U)
#define MJPEG_REG_Y1_ORDER_LEN          (2U)
#define MJPEG_REG_Y1_ORDER_MSK          (((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS)
#define MJPEG_REG_Y1_ORDER_UMSK         (~(((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS))
#define MJPEG_REG_V0_ORDER              MJPEG_REG_V0_ORDER
#define MJPEG_REG_V0_ORDER_POS          (30U)
#define MJPEG_REG_V0_ORDER_LEN          (2U)
#define MJPEG_REG_V0_ORDER_MSK          (((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS)
#define MJPEG_REG_V0_ORDER_UMSK         (~(((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS))

/* 0x4 : mjpeg_control_2 */
#define MJPEG_CONTROL_2_OFFSET          (0x4)
#define MJPEG_REG_SW_FRAME              MJPEG_REG_SW_FRAME
#define MJPEG_REG_SW_FRAME_POS          (0U)
#define MJPEG_REG_SW_FRAME_LEN          (5U)
#define MJPEG_REG_SW_FRAME_MSK          (((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS)
#define MJPEG_REG_SW_FRAME_UMSK         (~(((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS))
#define MJPEG_REG_MJPEG_SW_MODE         MJPEG_REG_MJPEG_SW_MODE
#define MJPEG_REG_MJPEG_SW_MODE_POS     (8U)
#define MJPEG_REG_MJPEG_SW_MODE_LEN     (1U)
#define MJPEG_REG_MJPEG_SW_MODE_MSK     (((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS)
#define MJPEG_REG_MJPEG_SW_MODE_UMSK    (~(((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS))
#define MJPEG_REG_MJPEG_SW_RUN          MJPEG_REG_MJPEG_SW_RUN
#define MJPEG_REG_MJPEG_SW_RUN_POS      (9U)
#define MJPEG_REG_MJPEG_SW_RUN_LEN      (1U)
#define MJPEG_REG_MJPEG_SW_RUN_MSK      (((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS)
#define MJPEG_REG_MJPEG_SW_RUN_UMSK     (~(((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS))
#define MJPEG_REG_YY_DVP2AHB_LSEL       MJPEG_REG_YY_DVP2AHB_LSEL
#define MJPEG_REG_YY_DVP2AHB_LSEL_POS   (12U)
#define MJPEG_REG_YY_DVP2AHB_LSEL_LEN   (1U)
#define MJPEG_REG_YY_DVP2AHB_LSEL_MSK   (((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS)
#define MJPEG_REG_YY_DVP2AHB_LSEL_UMSK  (~(((1U << MJPEG_REG_YY_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_LSEL_POS))
#define MJPEG_REG_YY_DVP2AHB_FSEL       MJPEG_REG_YY_DVP2AHB_FSEL
#define MJPEG_REG_YY_DVP2AHB_FSEL_POS   (13U)
#define MJPEG_REG_YY_DVP2AHB_FSEL_LEN   (1U)
#define MJPEG_REG_YY_DVP2AHB_FSEL_MSK   (((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS)
#define MJPEG_REG_YY_DVP2AHB_FSEL_UMSK  (~(((1U << MJPEG_REG_YY_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_YY_DVP2AHB_FSEL_POS))
#define MJPEG_REG_UV_DVP2AHB_LSEL       MJPEG_REG_UV_DVP2AHB_LSEL
#define MJPEG_REG_UV_DVP2AHB_LSEL_POS   (14U)
#define MJPEG_REG_UV_DVP2AHB_LSEL_LEN   (1U)
#define MJPEG_REG_UV_DVP2AHB_LSEL_MSK   (((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS)
#define MJPEG_REG_UV_DVP2AHB_LSEL_UMSK  (~(((1U << MJPEG_REG_UV_DVP2AHB_LSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_LSEL_POS))
#define MJPEG_REG_UV_DVP2AHB_FSEL       MJPEG_REG_UV_DVP2AHB_FSEL
#define MJPEG_REG_UV_DVP2AHB_FSEL_POS   (15U)
#define MJPEG_REG_UV_DVP2AHB_FSEL_LEN   (1U)
#define MJPEG_REG_UV_DVP2AHB_FSEL_MSK   (((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS)
#define MJPEG_REG_UV_DVP2AHB_FSEL_UMSK  (~(((1U << MJPEG_REG_UV_DVP2AHB_FSEL_LEN) - 1) << MJPEG_REG_UV_DVP2AHB_FSEL_POS))
#define MJPEG_REG_MJPEG_WAIT_CYCLE      MJPEG_REG_MJPEG_WAIT_CYCLE
#define MJPEG_REG_MJPEG_WAIT_CYCLE_POS  (16U)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_LEN  (16U)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_MSK  (((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_UMSK (~(((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS))

/* 0x08 : mjpeg_yy_frame_addr */
#define MJPEG_YY_FRAME_ADDR_OFFSET   (0x08)
#define MJPEG_REG_YY_ADDR_START      MJPEG_REG_YY_ADDR_START
#define MJPEG_REG_YY_ADDR_START_POS  (0U)
#define MJPEG_REG_YY_ADDR_START_LEN  (32U)
#define MJPEG_REG_YY_ADDR_START_MSK  (((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS)
#define MJPEG_REG_YY_ADDR_START_UMSK (~(((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS))

/* 0x0C : mjpeg_uv_frame_addr */
#define MJPEG_UV_FRAME_ADDR_OFFSET   (0x0C)
#define MJPEG_REG_UV_ADDR_START      MJPEG_REG_UV_ADDR_START
#define MJPEG_REG_UV_ADDR_START_POS  (0U)
#define MJPEG_REG_UV_ADDR_START_LEN  (32U)
#define MJPEG_REG_UV_ADDR_START_MSK  (((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS)
#define MJPEG_REG_UV_ADDR_START_UMSK (~(((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS))

/* 0x10 : mjpeg_yuv_mem */
#define MJPEG_YUV_MEM_OFFSET       (0x10)
#define MJPEG_REG_YY_MEM_HBLK      MJPEG_REG_YY_MEM_HBLK
#define MJPEG_REG_YY_MEM_HBLK_POS  (0U)
#define MJPEG_REG_YY_MEM_HBLK_LEN  (13U)
#define MJPEG_REG_YY_MEM_HBLK_MSK  (((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS)
#define MJPEG_REG_YY_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS))
#define MJPEG_REG_UV_MEM_HBLK      MJPEG_REG_UV_MEM_HBLK
#define MJPEG_REG_UV_MEM_HBLK_POS  (16U)
#define MJPEG_REG_UV_MEM_HBLK_LEN  (13U)
#define MJPEG_REG_UV_MEM_HBLK_MSK  (((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS)
#define MJPEG_REG_UV_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS))

/* 0x14 : jpeg_frame_addr */
#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14)
#define MJPEG_REG_W_ADDR_START       MJPEG_REG_W_ADDR_START
#define MJPEG_REG_W_ADDR_START_POS   (0U)
#define MJPEG_REG_W_ADDR_START_LEN   (32U)
#define MJPEG_REG_W_ADDR_START_MSK   (((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS)
#define MJPEG_REG_W_ADDR_START_UMSK  (~(((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS))

/* 0x18 : jpeg_store_memory */
#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18)
#define MJPEG_REG_W_BURST_CNT          MJPEG_REG_W_BURST_CNT
#define MJPEG_REG_W_BURST_CNT_POS      (0U)
#define MJPEG_REG_W_BURST_CNT_LEN      (32U)
#define MJPEG_REG_W_BURST_CNT_MSK      (((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS)
#define MJPEG_REG_W_BURST_CNT_UMSK     (~(((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS))

/* 0x1C : mjpeg_control_3 */
#define MJPEG_CONTROL_3_OFFSET            (0x1C)
#define MJPEG_REG_INT_NORMAL_EN           MJPEG_REG_INT_NORMAL_EN
#define MJPEG_REG_INT_NORMAL_EN_POS       (0U)
#define MJPEG_REG_INT_NORMAL_EN_LEN       (1U)
#define MJPEG_REG_INT_NORMAL_EN_MSK       (((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS)
#define MJPEG_REG_INT_NORMAL_EN_UMSK      (~(((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS))
#define MJPEG_REG_INT_CAM_EN              MJPEG_REG_INT_CAM_EN
#define MJPEG_REG_INT_CAM_EN_POS          (1U)
#define MJPEG_REG_INT_CAM_EN_LEN          (1U)
#define MJPEG_REG_INT_CAM_EN_MSK          (((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS)
#define MJPEG_REG_INT_CAM_EN_UMSK         (~(((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS))
#define MJPEG_REG_INT_MEM_EN              MJPEG_REG_INT_MEM_EN
#define MJPEG_REG_INT_MEM_EN_POS          (2U)
#define MJPEG_REG_INT_MEM_EN_LEN          (1U)
#define MJPEG_REG_INT_MEM_EN_MSK          (((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS)
#define MJPEG_REG_INT_MEM_EN_UMSK         (~(((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS))
#define MJPEG_REG_INT_FRAME_EN            MJPEG_REG_INT_FRAME_EN
#define MJPEG_REG_INT_FRAME_EN_POS        (3U)
#define MJPEG_REG_INT_FRAME_EN_LEN        (1U)
#define MJPEG_REG_INT_FRAME_EN_MSK        (((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS)
#define MJPEG_REG_INT_FRAME_EN_UMSK       (~(((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS))
#define MJPEG_STS_NORMAL_INT              MJPEG_STS_NORMAL_INT
#define MJPEG_STS_NORMAL_INT_POS          (4U)
#define MJPEG_STS_NORMAL_INT_LEN          (1U)
#define MJPEG_STS_NORMAL_INT_MSK          (((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS)
#define MJPEG_STS_NORMAL_INT_UMSK         (~(((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS))
#define MJPEG_STS_CAM_INT                 MJPEG_STS_CAM_INT
#define MJPEG_STS_CAM_INT_POS             (5U)
#define MJPEG_STS_CAM_INT_LEN             (1U)
#define MJPEG_STS_CAM_INT_MSK             (((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS)
#define MJPEG_STS_CAM_INT_UMSK            (~(((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS))
#define MJPEG_STS_MEM_INT                 MJPEG_STS_MEM_INT
#define MJPEG_STS_MEM_INT_POS             (6U)
#define MJPEG_STS_MEM_INT_LEN             (1U)
#define MJPEG_STS_MEM_INT_MSK             (((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS)
#define MJPEG_STS_MEM_INT_UMSK            (~(((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS))
#define MJPEG_STS_FRAME_INT               MJPEG_STS_FRAME_INT
#define MJPEG_STS_FRAME_INT_POS           (7U)
#define MJPEG_STS_FRAME_INT_LEN           (1U)
#define MJPEG_STS_FRAME_INT_MSK           (((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS)
#define MJPEG_STS_FRAME_INT_UMSK          (~(((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS))
#define MJPEG_IDLE                        MJPEG_IDLE
#define MJPEG_IDLE_POS                    (8U)
#define MJPEG_IDLE_LEN                    (1U)
#define MJPEG_IDLE_MSK                    (((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS)
#define MJPEG_IDLE_UMSK                   (~(((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS))
#define MJPEG_FUNC                        MJPEG_FUNC
#define MJPEG_FUNC_POS                    (9U)
#define MJPEG_FUNC_LEN                    (1U)
#define MJPEG_FUNC_MSK                    (((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS)
#define MJPEG_FUNC_UMSK                   (~(((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS))
#define MJPEG_WAIT                        MJPEG_WAIT
#define MJPEG_WAIT_POS                    (10U)
#define MJPEG_WAIT_LEN                    (1U)
#define MJPEG_WAIT_MSK                    (((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS)
#define MJPEG_WAIT_UMSK                   (~(((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS))
#define MJPEG_FLSH                        MJPEG_FLSH
#define MJPEG_FLSH_POS                    (11U)
#define MJPEG_FLSH_LEN                    (1U)
#define MJPEG_FLSH_MSK                    (((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS)
#define MJPEG_FLSH_UMSK                   (~(((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS))
#define MJPEG_MANS                        MJPEG_MANS
#define MJPEG_MANS_POS                    (12U)
#define MJPEG_MANS_LEN                    (1U)
#define MJPEG_MANS_MSK                    (((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS)
#define MJPEG_MANS_UMSK                   (~(((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS))
#define MJPEG_MANF                        MJPEG_MANF
#define MJPEG_MANF_POS                    (13U)
#define MJPEG_MANF_LEN                    (1U)
#define MJPEG_MANF_MSK                    (((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS)
#define MJPEG_MANF_UMSK                   (~(((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS))
#define MJPEG_AHB_IDLE                    MJPEG_AHB_IDLE
#define MJPEG_AHB_IDLE_POS                (14U)
#define MJPEG_AHB_IDLE_LEN                (1U)
#define MJPEG_AHB_IDLE_MSK                (((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS)
#define MJPEG_AHB_IDLE_UMSK               (~(((1U << MJPEG_AHB_IDLE_LEN) - 1) << MJPEG_AHB_IDLE_POS))
#define MJPEG_REG_FRAME_CNT_TRGR_INT      MJPEG_REG_FRAME_CNT_TRGR_INT
#define MJPEG_REG_FRAME_CNT_TRGR_INT_POS  (16U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_LEN  (5U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_MSK  (((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS))
#define MJPEG_REG_INT_IDLE_EN             MJPEG_REG_INT_IDLE_EN
#define MJPEG_REG_INT_IDLE_EN_POS         (21U)
#define MJPEG_REG_INT_IDLE_EN_LEN         (1U)
#define MJPEG_REG_INT_IDLE_EN_MSK         (((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS)
#define MJPEG_REG_INT_IDLE_EN_UMSK        (~(((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS))
#define MJPEG_STS_IDLE_INT                MJPEG_STS_IDLE_INT
#define MJPEG_STS_IDLE_INT_POS            (22U)
#define MJPEG_STS_IDLE_INT_LEN            (1U)
#define MJPEG_STS_IDLE_INT_MSK            (((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS)
#define MJPEG_STS_IDLE_INT_UMSK           (~(((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS))
#define MJPEG_FRAME_VALID_CNT             MJPEG_FRAME_VALID_CNT
#define MJPEG_FRAME_VALID_CNT_POS         (24U)
#define MJPEG_FRAME_VALID_CNT_LEN         (5U)
#define MJPEG_FRAME_VALID_CNT_MSK         (((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS)
#define MJPEG_FRAME_VALID_CNT_UMSK        (~(((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS))
#define MJPEG_REG_INT_SWAP_EN             MJPEG_REG_INT_SWAP_EN
#define MJPEG_REG_INT_SWAP_EN_POS         (29U)
#define MJPEG_REG_INT_SWAP_EN_LEN         (1U)
#define MJPEG_REG_INT_SWAP_EN_MSK         (((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS)
#define MJPEG_REG_INT_SWAP_EN_UMSK        (~(((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS))
#define MJPEG_STS_SWAP_INT                MJPEG_STS_SWAP_INT
#define MJPEG_STS_SWAP_INT_POS            (30U)
#define MJPEG_STS_SWAP_INT_LEN            (1U)
#define MJPEG_STS_SWAP_INT_MSK            (((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS)
#define MJPEG_STS_SWAP_INT_UMSK           (~(((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS))

/* 0x20 : mjpeg_frame_fifo_pop */
#define MJPEG_FRAME_FIFO_POP_OFFSET   (0x20)
#define MJPEG_RFIFO_POP               MJPEG_RFIFO_POP
#define MJPEG_RFIFO_POP_POS           (0U)
#define MJPEG_RFIFO_POP_LEN           (1U)
#define MJPEG_RFIFO_POP_MSK           (((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS)
#define MJPEG_RFIFO_POP_UMSK          (~(((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS))
#define MJPEG_REG_W_SWAP_CLR          MJPEG_REG_W_SWAP_CLR
#define MJPEG_REG_W_SWAP_CLR_POS      (1U)
#define MJPEG_REG_W_SWAP_CLR_LEN      (1U)
#define MJPEG_REG_W_SWAP_CLR_MSK      (((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS)
#define MJPEG_REG_W_SWAP_CLR_UMSK     (~(((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS))
#define MJPEG_REG_INT_NORMAL_CLR      MJPEG_REG_INT_NORMAL_CLR
#define MJPEG_REG_INT_NORMAL_CLR_POS  (8U)
#define MJPEG_REG_INT_NORMAL_CLR_LEN  (1U)
#define MJPEG_REG_INT_NORMAL_CLR_MSK  (((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS)
#define MJPEG_REG_INT_NORMAL_CLR_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS))
#define MJPEG_REG_INT_CAM_CLR         MJPEG_REG_INT_CAM_CLR
#define MJPEG_REG_INT_CAM_CLR_POS     (9U)
#define MJPEG_REG_INT_CAM_CLR_LEN     (1U)
#define MJPEG_REG_INT_CAM_CLR_MSK     (((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS)
#define MJPEG_REG_INT_CAM_CLR_UMSK    (~(((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS))
#define MJPEG_REG_INT_MEM_CLR         MJPEG_REG_INT_MEM_CLR
#define MJPEG_REG_INT_MEM_CLR_POS     (10U)
#define MJPEG_REG_INT_MEM_CLR_LEN     (1U)
#define MJPEG_REG_INT_MEM_CLR_MSK     (((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS)
#define MJPEG_REG_INT_MEM_CLR_UMSK    (~(((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS))
#define MJPEG_REG_INT_FRAME_CLR       MJPEG_REG_INT_FRAME_CLR
#define MJPEG_REG_INT_FRAME_CLR_POS   (11U)
#define MJPEG_REG_INT_FRAME_CLR_LEN   (1U)
#define MJPEG_REG_INT_FRAME_CLR_MSK   (((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS)
#define MJPEG_REG_INT_FRAME_CLR_UMSK  (~(((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS))
#define MJPEG_REG_INT_IDLE_CLR        MJPEG_REG_INT_IDLE_CLR
#define MJPEG_REG_INT_IDLE_CLR_POS    (12U)
#define MJPEG_REG_INT_IDLE_CLR_LEN    (1U)
#define MJPEG_REG_INT_IDLE_CLR_MSK    (((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS)
#define MJPEG_REG_INT_IDLE_CLR_UMSK   (~(((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS))
#define MJPEG_REG_INT_SWAP_CLR        MJPEG_REG_INT_SWAP_CLR
#define MJPEG_REG_INT_SWAP_CLR_POS    (13U)
#define MJPEG_REG_INT_SWAP_CLR_LEN    (1U)
#define MJPEG_REG_INT_SWAP_CLR_MSK    (((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS)
#define MJPEG_REG_INT_SWAP_CLR_UMSK   (~(((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS))

/* 0x24 : mjpeg_frame_size */
#define MJPEG_FRAME_SIZE_OFFSET   (0x24)
#define MJPEG_REG_FRAME_WBLK      MJPEG_REG_FRAME_WBLK
#define MJPEG_REG_FRAME_WBLK_POS  (0U)
#define MJPEG_REG_FRAME_WBLK_LEN  (12U)
#define MJPEG_REG_FRAME_WBLK_MSK  (((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS)
#define MJPEG_REG_FRAME_WBLK_UMSK (~(((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS))
#define MJPEG_REG_FRAME_HBLK      MJPEG_REG_FRAME_HBLK
#define MJPEG_REG_FRAME_HBLK_POS  (16U)
#define MJPEG_REG_FRAME_HBLK_LEN  (12U)
#define MJPEG_REG_FRAME_HBLK_MSK  (((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS)
#define MJPEG_REG_FRAME_HBLK_UMSK (~(((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS))

/* 0x28 : mjpeg_header_byte */
#define MJPEG_HEADER_BYTE_OFFSET (0x28)
#define MJPEG_REG_HEAD_BYTE      MJPEG_REG_HEAD_BYTE
#define MJPEG_REG_HEAD_BYTE_POS  (0U)
#define MJPEG_REG_HEAD_BYTE_LEN  (12U)
#define MJPEG_REG_HEAD_BYTE_MSK  (((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS)
#define MJPEG_REG_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS))
#define MJPEG_REG_TAIL_EXP       MJPEG_REG_TAIL_EXP
#define MJPEG_REG_TAIL_EXP_POS   (16U)
#define MJPEG_REG_TAIL_EXP_LEN   (1U)
#define MJPEG_REG_TAIL_EXP_MSK   (((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS)
#define MJPEG_REG_TAIL_EXP_UMSK  (~(((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS))

/* 0x30 : mjpeg_swap_mode */
#define MJPEG_SWAP_MODE_OFFSET       (0x30)
#define MJPEG_REG_W_SWAP_MODE        MJPEG_REG_W_SWAP_MODE
#define MJPEG_REG_W_SWAP_MODE_POS    (0U)
#define MJPEG_REG_W_SWAP_MODE_LEN    (1U)
#define MJPEG_REG_W_SWAP_MODE_MSK    (((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS)
#define MJPEG_REG_W_SWAP_MODE_UMSK   (~(((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS))
#define MJPEG_STS_SWAP0_FULL         MJPEG_STS_SWAP0_FULL
#define MJPEG_STS_SWAP0_FULL_POS     (8U)
#define MJPEG_STS_SWAP0_FULL_LEN     (1U)
#define MJPEG_STS_SWAP0_FULL_MSK     (((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS)
#define MJPEG_STS_SWAP0_FULL_UMSK    (~(((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS))
#define MJPEG_STS_SWAP1_FULL         MJPEG_STS_SWAP1_FULL
#define MJPEG_STS_SWAP1_FULL_POS     (9U)
#define MJPEG_STS_SWAP1_FULL_LEN     (1U)
#define MJPEG_STS_SWAP1_FULL_MSK     (((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS)
#define MJPEG_STS_SWAP1_FULL_UMSK    (~(((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS))
#define MJPEG_STS_READ_SWAP_IDX      MJPEG_STS_READ_SWAP_IDX
#define MJPEG_STS_READ_SWAP_IDX_POS  (10U)
#define MJPEG_STS_READ_SWAP_IDX_LEN  (1U)
#define MJPEG_STS_READ_SWAP_IDX_MSK  (((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS)
#define MJPEG_STS_READ_SWAP_IDX_UMSK (~(((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS))
#define MJPEG_STS_SWAP_FSTART        MJPEG_STS_SWAP_FSTART
#define MJPEG_STS_SWAP_FSTART_POS    (11U)
#define MJPEG_STS_SWAP_FSTART_LEN    (1U)
#define MJPEG_STS_SWAP_FSTART_MSK    (((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS)
#define MJPEG_STS_SWAP_FSTART_UMSK   (~(((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS))
#define MJPEG_STS_SWAP_FEND          MJPEG_STS_SWAP_FEND
#define MJPEG_STS_SWAP_FEND_POS      (12U)
#define MJPEG_STS_SWAP_FEND_LEN      (1U)
#define MJPEG_STS_SWAP_FEND_MSK      (((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS)
#define MJPEG_STS_SWAP_FEND_UMSK     (~(((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS))

/* 0x34 : mjpeg_swap_bit_cnt */
#define MJPEG_SWAP_BIT_CNT_OFFSET         (0x34)
#define MJPEG_FRAME_SWAP_END_BIT_CNT      MJPEG_FRAME_SWAP_END_BIT_CNT
#define MJPEG_FRAME_SWAP_END_BIT_CNT_POS  (0U)
#define MJPEG_FRAME_SWAP_END_BIT_CNT_LEN  (32U)
#define MJPEG_FRAME_SWAP_END_BIT_CNT_MSK  (((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS)
#define MJPEG_FRAME_SWAP_END_BIT_CNT_UMSK (~(((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS))

/* 0x38 : mjpeg_paket_ctrl */
#define MJPEG_PAKET_CTRL_OFFSET       (0x38)
#define MJPEG_REG_PKET_EN             MJPEG_REG_PKET_EN
#define MJPEG_REG_PKET_EN_POS         (0U)
#define MJPEG_REG_PKET_EN_LEN         (1U)
#define MJPEG_REG_PKET_EN_MSK         (((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS)
#define MJPEG_REG_PKET_EN_UMSK        (~(((1U << MJPEG_REG_PKET_EN_LEN) - 1) << MJPEG_REG_PKET_EN_POS))
#define MJPEG_REG_JEND_TO_PEND        MJPEG_REG_JEND_TO_PEND
#define MJPEG_REG_JEND_TO_PEND_POS    (1U)
#define MJPEG_REG_JEND_TO_PEND_LEN    (1U)
#define MJPEG_REG_JEND_TO_PEND_MSK    (((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS)
#define MJPEG_REG_JEND_TO_PEND_UMSK   (~(((1U << MJPEG_REG_JEND_TO_PEND_LEN) - 1) << MJPEG_REG_JEND_TO_PEND_POS))
#define MJPEG_REG_PKET_BODY_BYTE      MJPEG_REG_PKET_BODY_BYTE
#define MJPEG_REG_PKET_BODY_BYTE_POS  (16U)
#define MJPEG_REG_PKET_BODY_BYTE_LEN  (16U)
#define MJPEG_REG_PKET_BODY_BYTE_MSK  (((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS)
#define MJPEG_REG_PKET_BODY_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_BODY_BYTE_LEN) - 1) << MJPEG_REG_PKET_BODY_BYTE_POS))

/* 0x3C : mjpeg_paket_head_tail */
#define MJPEG_PAKET_HEAD_TAIL_OFFSET  (0x3C)
#define MJPEG_REG_PKET_HEAD_BYTE      MJPEG_REG_PKET_HEAD_BYTE
#define MJPEG_REG_PKET_HEAD_BYTE_POS  (0U)
#define MJPEG_REG_PKET_HEAD_BYTE_LEN  (12U)
#define MJPEG_REG_PKET_HEAD_BYTE_MSK  (((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS)
#define MJPEG_REG_PKET_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_HEAD_BYTE_LEN) - 1) << MJPEG_REG_PKET_HEAD_BYTE_POS))
#define MJPEG_REG_PKET_TAIL_BYTE      MJPEG_REG_PKET_TAIL_BYTE
#define MJPEG_REG_PKET_TAIL_BYTE_POS  (16U)
#define MJPEG_REG_PKET_TAIL_BYTE_LEN  (12U)
#define MJPEG_REG_PKET_TAIL_BYTE_MSK  (((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS)
#define MJPEG_REG_PKET_TAIL_BYTE_UMSK (~(((1U << MJPEG_REG_PKET_TAIL_BYTE_LEN) - 1) << MJPEG_REG_PKET_TAIL_BYTE_POS))

/* 0x40 : mjpeg_Y_frame_read_status_1 */
#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40)
#define MJPEG_YY_MEM_HBLK_R                MJPEG_YY_MEM_HBLK_R
#define MJPEG_YY_MEM_HBLK_R_POS            (0U)
#define MJPEG_YY_MEM_HBLK_R_LEN            (13U)
#define MJPEG_YY_MEM_HBLK_R_MSK            (((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS)
#define MJPEG_YY_MEM_HBLK_R_UMSK           (~(((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS))
#define MJPEG_YY_FRM_HBLK_R                MJPEG_YY_FRM_HBLK_R
#define MJPEG_YY_FRM_HBLK_R_POS            (16U)
#define MJPEG_YY_FRM_HBLK_R_LEN            (13U)
#define MJPEG_YY_FRM_HBLK_R_MSK            (((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS)
#define MJPEG_YY_FRM_HBLK_R_UMSK           (~(((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS))

/* 0x44 : mjpeg_Y_frame_read_status_2 */
#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44)
#define MJPEG_YY_WBLK_R                    MJPEG_YY_WBLK_R
#define MJPEG_YY_WBLK_R_POS                (0U)
#define MJPEG_YY_WBLK_R_LEN                (13U)
#define MJPEG_YY_WBLK_R_MSK                (((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS)
#define MJPEG_YY_WBLK_R_UMSK               (~(((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS))
#define MJPEG_YY_MEM_RND_R                 MJPEG_YY_MEM_RND_R
#define MJPEG_YY_MEM_RND_R_POS             (16U)
#define MJPEG_YY_MEM_RND_R_LEN             (8U)
#define MJPEG_YY_MEM_RND_R_MSK             (((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS)
#define MJPEG_YY_MEM_RND_R_UMSK            (~(((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS))
#define MJPEG_YY_FRM_CNT_R                 MJPEG_YY_FRM_CNT_R
#define MJPEG_YY_FRM_CNT_R_POS             (24U)
#define MJPEG_YY_FRM_CNT_R_LEN             (8U)
#define MJPEG_YY_FRM_CNT_R_MSK             (((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS)
#define MJPEG_YY_FRM_CNT_R_UMSK            (~(((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS))

/* 0x48 : mjpeg_Y_frame_write_status */
#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48)
#define MJPEG_YY_MEM_HBLK_W               MJPEG_YY_MEM_HBLK_W
#define MJPEG_YY_MEM_HBLK_W_POS           (0U)
#define MJPEG_YY_MEM_HBLK_W_LEN           (13U)
#define MJPEG_YY_MEM_HBLK_W_MSK           (((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS)
#define MJPEG_YY_MEM_HBLK_W_UMSK          (~(((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS))
#define MJPEG_YY_MEM_RND_W                MJPEG_YY_MEM_RND_W
#define MJPEG_YY_MEM_RND_W_POS            (16U)
#define MJPEG_YY_MEM_RND_W_LEN            (8U)
#define MJPEG_YY_MEM_RND_W_MSK            (((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS)
#define MJPEG_YY_MEM_RND_W_UMSK           (~(((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS))
#define MJPEG_YY_FRM_CNT_W                MJPEG_YY_FRM_CNT_W
#define MJPEG_YY_FRM_CNT_W_POS            (24U)
#define MJPEG_YY_FRM_CNT_W_LEN            (8U)
#define MJPEG_YY_FRM_CNT_W_MSK            (((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS)
#define MJPEG_YY_FRM_CNT_W_UMSK           (~(((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS))

/* 0x4C : mjpeg_UV_frame_read_status_1 */
#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C)
#define MJPEG_UV_MEM_HBLK_R                 MJPEG_UV_MEM_HBLK_R
#define MJPEG_UV_MEM_HBLK_R_POS             (0U)
#define MJPEG_UV_MEM_HBLK_R_LEN             (13U)
#define MJPEG_UV_MEM_HBLK_R_MSK             (((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS)
#define MJPEG_UV_MEM_HBLK_R_UMSK            (~(((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS))
#define MJPEG_UV_FRM_HBLK_R                 MJPEG_UV_FRM_HBLK_R
#define MJPEG_UV_FRM_HBLK_R_POS             (16U)
#define MJPEG_UV_FRM_HBLK_R_LEN             (13U)
#define MJPEG_UV_FRM_HBLK_R_MSK             (((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS)
#define MJPEG_UV_FRM_HBLK_R_UMSK            (~(((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS))

/* 0x50 : mjpeg_UV_frame_read_status_2 */
#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50)
#define MJPEG_UV_WBLK_R                     MJPEG_UV_WBLK_R
#define MJPEG_UV_WBLK_R_POS                 (0U)
#define MJPEG_UV_WBLK_R_LEN                 (13U)
#define MJPEG_UV_WBLK_R_MSK                 (((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS)
#define MJPEG_UV_WBLK_R_UMSK                (~(((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS))
#define MJPEG_UV_MEM_RND_R                  MJPEG_UV_MEM_RND_R
#define MJPEG_UV_MEM_RND_R_POS              (16U)
#define MJPEG_UV_MEM_RND_R_LEN              (8U)
#define MJPEG_UV_MEM_RND_R_MSK              (((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS)
#define MJPEG_UV_MEM_RND_R_UMSK             (~(((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS))
#define MJPEG_UV_FRM_CNT_R                  MJPEG_UV_FRM_CNT_R
#define MJPEG_UV_FRM_CNT_R_POS              (24U)
#define MJPEG_UV_FRM_CNT_R_LEN              (8U)
#define MJPEG_UV_FRM_CNT_R_MSK              (((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS)
#define MJPEG_UV_FRM_CNT_R_UMSK             (~(((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS))

/* 0x54 : mjpeg_UV_frame_write_status */
#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54)
#define MJPEG_UV_MEM_HBLK_W                MJPEG_UV_MEM_HBLK_W
#define MJPEG_UV_MEM_HBLK_W_POS            (0U)
#define MJPEG_UV_MEM_HBLK_W_LEN            (13U)
#define MJPEG_UV_MEM_HBLK_W_MSK            (((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS)
#define MJPEG_UV_MEM_HBLK_W_UMSK           (~(((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS))
#define MJPEG_UV_MEM_RND_W                 MJPEG_UV_MEM_RND_W
#define MJPEG_UV_MEM_RND_W_POS             (16U)
#define MJPEG_UV_MEM_RND_W_LEN             (8U)
#define MJPEG_UV_MEM_RND_W_MSK             (((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS)
#define MJPEG_UV_MEM_RND_W_UMSK            (~(((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS))
#define MJPEG_UV_FRM_CNT_W                 MJPEG_UV_FRM_CNT_W
#define MJPEG_UV_FRM_CNT_W_POS             (24U)
#define MJPEG_UV_FRM_CNT_W_LEN             (8U)
#define MJPEG_UV_FRM_CNT_W_MSK             (((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS)
#define MJPEG_UV_FRM_CNT_W_UMSK            (~(((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS))

/* 0x80 : mjpeg_start_addr0 */
#define MJPEG_START_ADDR0_OFFSET      (0x80)
#define MJPEG_FRAME_START_ADDR_0      MJPEG_FRAME_START_ADDR_0
#define MJPEG_FRAME_START_ADDR_0_POS  (0U)
#define MJPEG_FRAME_START_ADDR_0_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_0_MSK  (((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS)
#define MJPEG_FRAME_START_ADDR_0_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS))

/* 0x84 : mjpeg_bit_cnt0 */
#define MJPEG_BIT_CNT0_OFFSET      (0x84)
#define MJPEG_FRAME_BIT_CNT_0      MJPEG_FRAME_BIT_CNT_0
#define MJPEG_FRAME_BIT_CNT_0_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_0_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_0_MSK  (((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS)
#define MJPEG_FRAME_BIT_CNT_0_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS))

/* 0x88 : mjpeg_start_addr1 */
#define MJPEG_START_ADDR1_OFFSET      (0x88)
#define MJPEG_FRAME_START_ADDR_1      MJPEG_FRAME_START_ADDR_1
#define MJPEG_FRAME_START_ADDR_1_POS  (0U)
#define MJPEG_FRAME_START_ADDR_1_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_1_MSK  (((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS)
#define MJPEG_FRAME_START_ADDR_1_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS))

/* 0x8C : mjpeg_bit_cnt1 */
#define MJPEG_BIT_CNT1_OFFSET      (0x8C)
#define MJPEG_FRAME_BIT_CNT_1      MJPEG_FRAME_BIT_CNT_1
#define MJPEG_FRAME_BIT_CNT_1_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_1_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_1_MSK  (((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS)
#define MJPEG_FRAME_BIT_CNT_1_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS))

/* 0x90 : mjpeg_start_addr2 */
#define MJPEG_START_ADDR2_OFFSET      (0x90)
#define MJPEG_FRAME_START_ADDR_2      MJPEG_FRAME_START_ADDR_2
#define MJPEG_FRAME_START_ADDR_2_POS  (0U)
#define MJPEG_FRAME_START_ADDR_2_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_2_MSK  (((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS)
#define MJPEG_FRAME_START_ADDR_2_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS))

/* 0x94 : mjpeg_bit_cnt2 */
#define MJPEG_BIT_CNT2_OFFSET      (0x94)
#define MJPEG_FRAME_BIT_CNT_2      MJPEG_FRAME_BIT_CNT_2
#define MJPEG_FRAME_BIT_CNT_2_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_2_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_2_MSK  (((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS)
#define MJPEG_FRAME_BIT_CNT_2_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS))

/* 0x98 : mjpeg_start_addr3 */
#define MJPEG_START_ADDR3_OFFSET      (0x98)
#define MJPEG_FRAME_START_ADDR_3      MJPEG_FRAME_START_ADDR_3
#define MJPEG_FRAME_START_ADDR_3_POS  (0U)
#define MJPEG_FRAME_START_ADDR_3_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_3_MSK  (((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS)
#define MJPEG_FRAME_START_ADDR_3_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS))

/* 0x9C : mjpeg_bit_cnt3 */
#define MJPEG_BIT_CNT3_OFFSET      (0x9C)
#define MJPEG_FRAME_BIT_CNT_3      MJPEG_FRAME_BIT_CNT_3
#define MJPEG_FRAME_BIT_CNT_3_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_3_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_3_MSK  (((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS)
#define MJPEG_FRAME_BIT_CNT_3_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS))

/* 0xA0 : mjpeg_start_addr4 */
#define MJPEG_START_ADDR4_OFFSET      (0xA0)
#define MJPEG_FRAME_START_ADDR_4      MJPEG_FRAME_START_ADDR_4
#define MJPEG_FRAME_START_ADDR_4_POS  (0U)
#define MJPEG_FRAME_START_ADDR_4_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_4_MSK  (((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS)
#define MJPEG_FRAME_START_ADDR_4_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_4_LEN) - 1) << MJPEG_FRAME_START_ADDR_4_POS))

/* 0xA4 : mjpeg_bit_cnt4 */
#define MJPEG_BIT_CNT4_OFFSET      (0xA4)
#define MJPEG_FRAME_BIT_CNT_4      MJPEG_FRAME_BIT_CNT_4
#define MJPEG_FRAME_BIT_CNT_4_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_4_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_4_MSK  (((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS)
#define MJPEG_FRAME_BIT_CNT_4_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_4_LEN) - 1) << MJPEG_FRAME_BIT_CNT_4_POS))

/* 0xA8 : mjpeg_start_addr5 */
#define MJPEG_START_ADDR5_OFFSET      (0xA8)
#define MJPEG_FRAME_START_ADDR_5      MJPEG_FRAME_START_ADDR_5
#define MJPEG_FRAME_START_ADDR_5_POS  (0U)
#define MJPEG_FRAME_START_ADDR_5_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_5_MSK  (((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS)
#define MJPEG_FRAME_START_ADDR_5_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_5_LEN) - 1) << MJPEG_FRAME_START_ADDR_5_POS))

/* 0xAC : mjpeg_bit_cnt5 */
#define MJPEG_BIT_CNT5_OFFSET      (0xAC)
#define MJPEG_FRAME_BIT_CNT_5      MJPEG_FRAME_BIT_CNT_5
#define MJPEG_FRAME_BIT_CNT_5_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_5_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_5_MSK  (((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS)
#define MJPEG_FRAME_BIT_CNT_5_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_5_LEN) - 1) << MJPEG_FRAME_BIT_CNT_5_POS))

/* 0xB0 : mjpeg_start_addr6 */
#define MJPEG_START_ADDR6_OFFSET      (0xB0)
#define MJPEG_FRAME_START_ADDR_6      MJPEG_FRAME_START_ADDR_6
#define MJPEG_FRAME_START_ADDR_6_POS  (0U)
#define MJPEG_FRAME_START_ADDR_6_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_6_MSK  (((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS)
#define MJPEG_FRAME_START_ADDR_6_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_6_LEN) - 1) << MJPEG_FRAME_START_ADDR_6_POS))

/* 0xB4 : mjpeg_bit_cnt6 */
#define MJPEG_BIT_CNT6_OFFSET      (0xB4)
#define MJPEG_FRAME_BIT_CNT_6      MJPEG_FRAME_BIT_CNT_6
#define MJPEG_FRAME_BIT_CNT_6_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_6_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_6_MSK  (((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS)
#define MJPEG_FRAME_BIT_CNT_6_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_6_LEN) - 1) << MJPEG_FRAME_BIT_CNT_6_POS))

/* 0xB8 : mjpeg_start_addr7 */
#define MJPEG_START_ADDR7_OFFSET      (0xB8)
#define MJPEG_FRAME_START_ADDR_7      MJPEG_FRAME_START_ADDR_7
#define MJPEG_FRAME_START_ADDR_7_POS  (0U)
#define MJPEG_FRAME_START_ADDR_7_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_7_MSK  (((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS)
#define MJPEG_FRAME_START_ADDR_7_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_7_LEN) - 1) << MJPEG_FRAME_START_ADDR_7_POS))

/* 0xBC : mjpeg_bit_cnt7 */
#define MJPEG_BIT_CNT7_OFFSET      (0xBC)
#define MJPEG_FRAME_BIT_CNT_7      MJPEG_FRAME_BIT_CNT_7
#define MJPEG_FRAME_BIT_CNT_7_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_7_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_7_MSK  (((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS)
#define MJPEG_FRAME_BIT_CNT_7_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_7_LEN) - 1) << MJPEG_FRAME_BIT_CNT_7_POS))

/* 0xC0 : mjpeg_start_addr_8 */
#define MJPEG_START_ADDR_8_OFFSET     (0xC0)
#define MJPEG_FRAME_START_ADDR_8      MJPEG_FRAME_START_ADDR_8
#define MJPEG_FRAME_START_ADDR_8_POS  (0U)
#define MJPEG_FRAME_START_ADDR_8_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_8_MSK  (((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS)
#define MJPEG_FRAME_START_ADDR_8_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_8_LEN) - 1) << MJPEG_FRAME_START_ADDR_8_POS))

/* 0xC4 : mjpeg_bit_cnt_8 */
#define MJPEG_BIT_CNT_8_OFFSET     (0xC4)
#define MJPEG_FRAME_BIT_CNT_8      MJPEG_FRAME_BIT_CNT_8
#define MJPEG_FRAME_BIT_CNT_8_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_8_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_8_MSK  (((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS)
#define MJPEG_FRAME_BIT_CNT_8_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_8_LEN) - 1) << MJPEG_FRAME_BIT_CNT_8_POS))

/* 0xC8 : mjpeg_start_addr_9 */
#define MJPEG_START_ADDR_9_OFFSET     (0xC8)
#define MJPEG_FRAME_START_ADDR_9      MJPEG_FRAME_START_ADDR_9
#define MJPEG_FRAME_START_ADDR_9_POS  (0U)
#define MJPEG_FRAME_START_ADDR_9_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_9_MSK  (((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS)
#define MJPEG_FRAME_START_ADDR_9_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_9_LEN) - 1) << MJPEG_FRAME_START_ADDR_9_POS))

/* 0xCC : mjpeg_bit_cnt_9 */
#define MJPEG_BIT_CNT_9_OFFSET     (0xCC)
#define MJPEG_FRAME_BIT_CNT_9      MJPEG_FRAME_BIT_CNT_9
#define MJPEG_FRAME_BIT_CNT_9_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_9_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_9_MSK  (((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS)
#define MJPEG_FRAME_BIT_CNT_9_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_9_LEN) - 1) << MJPEG_FRAME_BIT_CNT_9_POS))

/* 0xD0 : mjpeg_start_addr_a */
#define MJPEG_START_ADDR_A_OFFSET     (0xD0)
#define MJPEG_FRAME_START_ADDR_A      MJPEG_FRAME_START_ADDR_A
#define MJPEG_FRAME_START_ADDR_A_POS  (0U)
#define MJPEG_FRAME_START_ADDR_A_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_A_MSK  (((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS)
#define MJPEG_FRAME_START_ADDR_A_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_A_LEN) - 1) << MJPEG_FRAME_START_ADDR_A_POS))

/* 0xD4 : mjpeg_bit_cnt_a */
#define MJPEG_BIT_CNT_A_OFFSET     (0xD4)
#define MJPEG_FRAME_BIT_CNT_A      MJPEG_FRAME_BIT_CNT_A
#define MJPEG_FRAME_BIT_CNT_A_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_A_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_A_MSK  (((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS)
#define MJPEG_FRAME_BIT_CNT_A_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_A_LEN) - 1) << MJPEG_FRAME_BIT_CNT_A_POS))

/* 0xD8 : mjpeg_start_addr_b */
#define MJPEG_START_ADDR_B_OFFSET     (0xD8)
#define MJPEG_FRAME_START_ADDR_B      MJPEG_FRAME_START_ADDR_B
#define MJPEG_FRAME_START_ADDR_B_POS  (0U)
#define MJPEG_FRAME_START_ADDR_B_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_B_MSK  (((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS)
#define MJPEG_FRAME_START_ADDR_B_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_B_LEN) - 1) << MJPEG_FRAME_START_ADDR_B_POS))

/* 0xDC : mjpeg_bit_cnt_b */
#define MJPEG_BIT_CNT_B_OFFSET     (0xDC)
#define MJPEG_FRAME_BIT_CNT_B      MJPEG_FRAME_BIT_CNT_B
#define MJPEG_FRAME_BIT_CNT_B_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_B_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_B_MSK  (((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS)
#define MJPEG_FRAME_BIT_CNT_B_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_B_LEN) - 1) << MJPEG_FRAME_BIT_CNT_B_POS))

/* 0xE0 : mjpeg_start_addr_c */
#define MJPEG_START_ADDR_C_OFFSET     (0xE0)
#define MJPEG_FRAME_START_ADDR_C      MJPEG_FRAME_START_ADDR_C
#define MJPEG_FRAME_START_ADDR_C_POS  (0U)
#define MJPEG_FRAME_START_ADDR_C_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_C_MSK  (((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS)
#define MJPEG_FRAME_START_ADDR_C_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_C_LEN) - 1) << MJPEG_FRAME_START_ADDR_C_POS))

/* 0xE4 : mjpeg_bit_cnt_c */
#define MJPEG_BIT_CNT_C_OFFSET     (0xE4)
#define MJPEG_FRAME_BIT_CNT_C      MJPEG_FRAME_BIT_CNT_C
#define MJPEG_FRAME_BIT_CNT_C_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_C_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_C_MSK  (((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS)
#define MJPEG_FRAME_BIT_CNT_C_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_C_LEN) - 1) << MJPEG_FRAME_BIT_CNT_C_POS))

/* 0xE8 : mjpeg_start_addr_d */
#define MJPEG_START_ADDR_D_OFFSET     (0xE8)
#define MJPEG_FRAME_START_ADDR_D      MJPEG_FRAME_START_ADDR_D
#define MJPEG_FRAME_START_ADDR_D_POS  (0U)
#define MJPEG_FRAME_START_ADDR_D_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_D_MSK  (((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS)
#define MJPEG_FRAME_START_ADDR_D_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_D_LEN) - 1) << MJPEG_FRAME_START_ADDR_D_POS))

/* 0xEC : mjpeg_bit_cnt_d */
#define MJPEG_BIT_CNT_D_OFFSET     (0xEC)
#define MJPEG_FRAME_BIT_CNT_D      MJPEG_FRAME_BIT_CNT_D
#define MJPEG_FRAME_BIT_CNT_D_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_D_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_D_MSK  (((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS)
#define MJPEG_FRAME_BIT_CNT_D_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_D_LEN) - 1) << MJPEG_FRAME_BIT_CNT_D_POS))

/* 0xF0 : mjpeg_start_addr_e */
#define MJPEG_START_ADDR_E_OFFSET     (0xF0)
#define MJPEG_FRAME_START_ADDR_E      MJPEG_FRAME_START_ADDR_E
#define MJPEG_FRAME_START_ADDR_E_POS  (0U)
#define MJPEG_FRAME_START_ADDR_E_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_E_MSK  (((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS)
#define MJPEG_FRAME_START_ADDR_E_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_E_LEN) - 1) << MJPEG_FRAME_START_ADDR_E_POS))

/* 0xF4 : mjpeg_bit_cnt_e */
#define MJPEG_BIT_CNT_E_OFFSET     (0xF4)
#define MJPEG_FRAME_BIT_CNT_E      MJPEG_FRAME_BIT_CNT_E
#define MJPEG_FRAME_BIT_CNT_E_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_E_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_E_MSK  (((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS)
#define MJPEG_FRAME_BIT_CNT_E_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_E_LEN) - 1) << MJPEG_FRAME_BIT_CNT_E_POS))

/* 0xF8 : mjpeg_start_addr_f */
#define MJPEG_START_ADDR_F_OFFSET     (0xF8)
#define MJPEG_FRAME_START_ADDR_F      MJPEG_FRAME_START_ADDR_F
#define MJPEG_FRAME_START_ADDR_F_POS  (0U)
#define MJPEG_FRAME_START_ADDR_F_LEN  (32U)
#define MJPEG_FRAME_START_ADDR_F_MSK  (((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS)
#define MJPEG_FRAME_START_ADDR_F_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_F_LEN) - 1) << MJPEG_FRAME_START_ADDR_F_POS))

/* 0xFC : mjpeg_bit_cnt_f */
#define MJPEG_BIT_CNT_F_OFFSET     (0xFC)
#define MJPEG_FRAME_BIT_CNT_F      MJPEG_FRAME_BIT_CNT_F
#define MJPEG_FRAME_BIT_CNT_F_POS  (0U)
#define MJPEG_FRAME_BIT_CNT_F_LEN  (32U)
#define MJPEG_FRAME_BIT_CNT_F_MSK  (((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS)
#define MJPEG_FRAME_BIT_CNT_F_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_F_LEN) - 1) << MJPEG_FRAME_BIT_CNT_F_POS))

/* 0x100 : mjpeg_q_mode0 */
#define MJPEG_Q_MODE0_OFFSET      (0x100)
#define MJPEG_FRAME_Q_MODE_0      MJPEG_FRAME_Q_MODE_0
#define MJPEG_FRAME_Q_MODE_0_POS  (0U)
#define MJPEG_FRAME_Q_MODE_0_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_0_MSK  (((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS)
#define MJPEG_FRAME_Q_MODE_0_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_0_LEN) - 1) << MJPEG_FRAME_Q_MODE_0_POS))

/* 0x104 : mjpeg_q_mode1 */
#define MJPEG_Q_MODE1_OFFSET      (0x104)
#define MJPEG_FRAME_Q_MODE_1      MJPEG_FRAME_Q_MODE_1
#define MJPEG_FRAME_Q_MODE_1_POS  (0U)
#define MJPEG_FRAME_Q_MODE_1_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_1_MSK  (((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS)
#define MJPEG_FRAME_Q_MODE_1_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_1_LEN) - 1) << MJPEG_FRAME_Q_MODE_1_POS))

/* 0x108 : mjpeg_q_mode2 */
#define MJPEG_Q_MODE2_OFFSET      (0x108)
#define MJPEG_FRAME_Q_MODE_2      MJPEG_FRAME_Q_MODE_2
#define MJPEG_FRAME_Q_MODE_2_POS  (0U)
#define MJPEG_FRAME_Q_MODE_2_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_2_MSK  (((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS)
#define MJPEG_FRAME_Q_MODE_2_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_2_LEN) - 1) << MJPEG_FRAME_Q_MODE_2_POS))

/* 0x10C : mjpeg_q_mode3 */
#define MJPEG_Q_MODE3_OFFSET      (0x10C)
#define MJPEG_FRAME_Q_MODE_3      MJPEG_FRAME_Q_MODE_3
#define MJPEG_FRAME_Q_MODE_3_POS  (0U)
#define MJPEG_FRAME_Q_MODE_3_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_3_MSK  (((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS)
#define MJPEG_FRAME_Q_MODE_3_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_3_LEN) - 1) << MJPEG_FRAME_Q_MODE_3_POS))

/* 0x110 : mjpeg_q_mode4 */
#define MJPEG_Q_MODE4_OFFSET      (0x110)
#define MJPEG_FRAME_Q_MODE_4      MJPEG_FRAME_Q_MODE_4
#define MJPEG_FRAME_Q_MODE_4_POS  (0U)
#define MJPEG_FRAME_Q_MODE_4_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_4_MSK  (((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS)
#define MJPEG_FRAME_Q_MODE_4_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_4_LEN) - 1) << MJPEG_FRAME_Q_MODE_4_POS))

/* 0x114 : mjpeg_q_mode5 */
#define MJPEG_Q_MODE5_OFFSET      (0x114)
#define MJPEG_FRAME_Q_MODE_5      MJPEG_FRAME_Q_MODE_5
#define MJPEG_FRAME_Q_MODE_5_POS  (0U)
#define MJPEG_FRAME_Q_MODE_5_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_5_MSK  (((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS)
#define MJPEG_FRAME_Q_MODE_5_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_5_LEN) - 1) << MJPEG_FRAME_Q_MODE_5_POS))

/* 0x118 : mjpeg_q_mode6 */
#define MJPEG_Q_MODE6_OFFSET      (0x118)
#define MJPEG_FRAME_Q_MODE_6      MJPEG_FRAME_Q_MODE_6
#define MJPEG_FRAME_Q_MODE_6_POS  (0U)
#define MJPEG_FRAME_Q_MODE_6_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_6_MSK  (((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS)
#define MJPEG_FRAME_Q_MODE_6_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_6_LEN) - 1) << MJPEG_FRAME_Q_MODE_6_POS))

/* 0x11C : mjpeg_q_mode7 */
#define MJPEG_Q_MODE7_OFFSET      (0x11C)
#define MJPEG_FRAME_Q_MODE_7      MJPEG_FRAME_Q_MODE_7
#define MJPEG_FRAME_Q_MODE_7_POS  (0U)
#define MJPEG_FRAME_Q_MODE_7_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_7_MSK  (((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS)
#define MJPEG_FRAME_Q_MODE_7_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_7_LEN) - 1) << MJPEG_FRAME_Q_MODE_7_POS))

/* 0x120 : mjpeg_q_mode_8 */
#define MJPEG_Q_MODE_8_OFFSET     (0x120)
#define MJPEG_FRAME_Q_MODE_8      MJPEG_FRAME_Q_MODE_8
#define MJPEG_FRAME_Q_MODE_8_POS  (0U)
#define MJPEG_FRAME_Q_MODE_8_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_8_MSK  (((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS)
#define MJPEG_FRAME_Q_MODE_8_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_8_LEN) - 1) << MJPEG_FRAME_Q_MODE_8_POS))

/* 0x124 : mjpeg_q_mode_9 */
#define MJPEG_Q_MODE_9_OFFSET     (0x124)
#define MJPEG_FRAME_Q_MODE_9      MJPEG_FRAME_Q_MODE_9
#define MJPEG_FRAME_Q_MODE_9_POS  (0U)
#define MJPEG_FRAME_Q_MODE_9_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_9_MSK  (((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS)
#define MJPEG_FRAME_Q_MODE_9_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_9_LEN) - 1) << MJPEG_FRAME_Q_MODE_9_POS))

/* 0x128 : mjpeg_q_mode_a */
#define MJPEG_Q_MODE_A_OFFSET     (0x128)
#define MJPEG_FRAME_Q_MODE_A      MJPEG_FRAME_Q_MODE_A
#define MJPEG_FRAME_Q_MODE_A_POS  (0U)
#define MJPEG_FRAME_Q_MODE_A_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_A_MSK  (((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS)
#define MJPEG_FRAME_Q_MODE_A_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_A_LEN) - 1) << MJPEG_FRAME_Q_MODE_A_POS))

/* 0x12C : mjpeg_q_mode_b */
#define MJPEG_Q_MODE_B_OFFSET     (0x12C)
#define MJPEG_FRAME_Q_MODE_B      MJPEG_FRAME_Q_MODE_B
#define MJPEG_FRAME_Q_MODE_B_POS  (0U)
#define MJPEG_FRAME_Q_MODE_B_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_B_MSK  (((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS)
#define MJPEG_FRAME_Q_MODE_B_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_B_LEN) - 1) << MJPEG_FRAME_Q_MODE_B_POS))

/* 0x130 : mjpeg_q_mode_c */
#define MJPEG_Q_MODE_C_OFFSET     (0x130)
#define MJPEG_FRAME_Q_MODE_C      MJPEG_FRAME_Q_MODE_C
#define MJPEG_FRAME_Q_MODE_C_POS  (0U)
#define MJPEG_FRAME_Q_MODE_C_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_C_MSK  (((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS)
#define MJPEG_FRAME_Q_MODE_C_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_C_LEN) - 1) << MJPEG_FRAME_Q_MODE_C_POS))

/* 0x134 : mjpeg_q_mode_d */
#define MJPEG_Q_MODE_D_OFFSET     (0x134)
#define MJPEG_FRAME_Q_MODE_D      MJPEG_FRAME_Q_MODE_D
#define MJPEG_FRAME_Q_MODE_D_POS  (0U)
#define MJPEG_FRAME_Q_MODE_D_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_D_MSK  (((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS)
#define MJPEG_FRAME_Q_MODE_D_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_D_LEN) - 1) << MJPEG_FRAME_Q_MODE_D_POS))

/* 0x138 : mjpeg_q_mode_e */
#define MJPEG_Q_MODE_E_OFFSET     (0x138)
#define MJPEG_FRAME_Q_MODE_E      MJPEG_FRAME_Q_MODE_E
#define MJPEG_FRAME_Q_MODE_E_POS  (0U)
#define MJPEG_FRAME_Q_MODE_E_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_E_MSK  (((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS)
#define MJPEG_FRAME_Q_MODE_E_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_E_LEN) - 1) << MJPEG_FRAME_Q_MODE_E_POS))

/* 0x13C : mjpeg_q_mode_f */
#define MJPEG_Q_MODE_F_OFFSET     (0x13C)
#define MJPEG_FRAME_Q_MODE_F      MJPEG_FRAME_Q_MODE_F
#define MJPEG_FRAME_Q_MODE_F_POS  (0U)
#define MJPEG_FRAME_Q_MODE_F_LEN  (7U)
#define MJPEG_FRAME_Q_MODE_F_MSK  (((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS)
#define MJPEG_FRAME_Q_MODE_F_UMSK (~(((1U << MJPEG_FRAME_Q_MODE_F_LEN) - 1) << MJPEG_FRAME_Q_MODE_F_POS))

/* 0x1F0 : mjpeg_debug */
#define MJPEG_DEBUG_OFFSET           (0x1F0)
#define MJPEG_REG_MJPEG_DBG_EN       MJPEG_REG_MJPEG_DBG_EN
#define MJPEG_REG_MJPEG_DBG_EN_POS   (0U)
#define MJPEG_REG_MJPEG_DBG_EN_LEN   (1U)
#define MJPEG_REG_MJPEG_DBG_EN_MSK   (((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS)
#define MJPEG_REG_MJPEG_DBG_EN_UMSK  (~(((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS))
#define MJPEG_REG_MJPEG_DBG_SEL      MJPEG_REG_MJPEG_DBG_SEL
#define MJPEG_REG_MJPEG_DBG_SEL_POS  (4U)
#define MJPEG_REG_MJPEG_DBG_SEL_LEN  (4U)
#define MJPEG_REG_MJPEG_DBG_SEL_MSK  (((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS)
#define MJPEG_REG_MJPEG_DBG_SEL_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS))

/* 0x1FC : mjpeg_dummy_reg */
#define MJPEG_DUMMY_REG_OFFSET (0x1FC)
#define MJPEG_DUMMY_REG        MJPEG_DUMMY_REG
#define MJPEG_DUMMY_REG_POS    (0U)
#define MJPEG_DUMMY_REG_LEN    (32U)
#define MJPEG_DUMMY_REG_MSK    (((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS)
#define MJPEG_DUMMY_REG_UMSK   (~(((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS))

struct mjpeg_reg {
    /* 0x0 : mjpeg_control_1 */
    union {
        struct
        {
            uint32_t reg_mjpeg_enable     : 1; /* [    0],        r/w,        0x0 */
            uint32_t reg_mjpeg_bit_order  : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_order_u_even     : 1; /* [    2],        r/w,        0x1 */
            uint32_t reg_wr_over_stop     : 1; /* [    3],        r/w,        0x0 */
            uint32_t reg_last_hf_wblk_dmy : 1; /* [    4],        r/w,        0x0 */
            uint32_t reg_last_hf_hblk_dmy : 1; /* [    5],        r/w,        0x0 */
            uint32_t reg_reflect_dmy      : 1; /* [    6],        r/w,        0x0 */
            uint32_t reserved_7           : 1; /* [    7],       rsvd,        0x0 */
            uint32_t reg_h_bust           : 2; /* [ 9: 8],        r/w,        0x3 */
            uint32_t reserved_10_11       : 2; /* [11:10],       rsvd,        0x0 */
            uint32_t reg_yuv_mode         : 2; /* [13:12],        r/w,        0x0 */
            uint32_t reserved_14_15       : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t reg_q_mode           : 7; /* [22:16],        r/w,       0x32 */
            uint32_t reserved_23          : 1; /* [   23],       rsvd,        0x0 */
            uint32_t reg_y0_order         : 2; /* [25:24],        r/w,        0x0 */
            uint32_t reg_u0_order         : 2; /* [27:26],        r/w,        0x1 */
            uint32_t reg_y1_order         : 2; /* [29:28],        r/w,        0x2 */
            uint32_t reg_v0_order         : 2; /* [31:30],        r/w,        0x3 */
        } BF;
        uint32_t WORD;
    } mjpeg_control_1;

    /* 0x4 : mjpeg_control_2 */
    union {
        struct
        {
            uint32_t reg_sw_frame         : 5;  /* [ 4: 0],        r/w,        0x0 */
            uint32_t reserved_5_7         : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t reg_mjpeg_sw_mode    : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reg_mjpeg_sw_run     : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10_11       : 2;  /* [11:10],       rsvd,        0x0 */
            uint32_t reg_yy_dvp2ahb_lsel  : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reg_yy_dvp2ahb_fsel  : 1;  /* [   13],        r/w,        0x0 */
            uint32_t reg_uv_dvp2ahb_lsel  : 1;  /* [   14],        r/w,        0x0 */
            uint32_t reg_uv_dvp2ahb_fsel  : 1;  /* [   15],        r/w,        0x0 */
            uint32_t reg_mjpeg_wait_cycle : 16; /* [31:16],        r/w,      0x400 */
        } BF;
        uint32_t WORD;
    } mjpeg_control_2;

    /* 0x08 : mjpeg_yy_frame_addr */
    union {
        struct
        {
            uint32_t reg_yy_addr_start : 32; /* [31: 0],        r/w, 0x80000000L */
        } BF;
        uint32_t WORD;
    } mjpeg_yy_frame_addr;

    /* 0x0C : mjpeg_uv_frame_addr */
    union {
        struct
        {
            uint32_t reg_uv_addr_start : 32; /* [31: 0],        r/w, 0x80000000L */
        } BF;
        uint32_t WORD;
    } mjpeg_uv_frame_addr;

    /* 0x10 : mjpeg_yuv_mem */
    union {
        struct
        {
            uint32_t reg_yy_mem_hblk : 13; /* [12: 0],        r/w,        0x2 */
            uint32_t reserved_13_15  : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t reg_uv_mem_hblk : 13; /* [28:16],        r/w,        0x2 */
            uint32_t reserved_29_31  : 3;  /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_yuv_mem;

    /* 0x14 : jpeg_frame_addr */
    union {
        struct
        {
            uint32_t reg_w_addr_start : 32; /* [31: 0],        r/w, 0x80400000L */
        } BF;
        uint32_t WORD;
    } jpeg_frame_addr;

    /* 0x18 : jpeg_store_memory */
    union {
        struct
        {
            uint32_t reg_w_burst_cnt : 32; /* [31: 0],        r/w,     0x4000 */
        } BF;
        uint32_t WORD;
    } jpeg_store_memory;

    /* 0x1C : mjpeg_control_3 */
    union {
        struct
        {
            uint32_t reg_int_normal_en      : 1; /* [    0],        r/w,        0x1 */
            uint32_t reg_int_cam_en         : 1; /* [    1],        r/w,        0x1 */
            uint32_t reg_int_mem_en         : 1; /* [    2],        r/w,        0x0 */
            uint32_t reg_int_frame_en       : 1; /* [    3],        r/w,        0x0 */
            uint32_t sts_normal_int         : 1; /* [    4],          r,        0x0 */
            uint32_t sts_cam_int            : 1; /* [    5],          r,        0x0 */
            uint32_t sts_mem_int            : 1; /* [    6],          r,        0x0 */
            uint32_t sts_frame_int          : 1; /* [    7],          r,        0x0 */
            uint32_t mjpeg_idle             : 1; /* [    8],          r,        0x1 */
            uint32_t mjpeg_func             : 1; /* [    9],          r,        0x0 */
            uint32_t mjpeg_wait             : 1; /* [   10],          r,        0x0 */
            uint32_t mjpeg_flsh             : 1; /* [   11],          r,        0x0 */
            uint32_t mjpeg_mans             : 1; /* [   12],          r,        0x0 */
            uint32_t mjpeg_manf             : 1; /* [   13],          r,        0x0 */
            uint32_t ahb_idle               : 1; /* [   14],          r,        0x0 */
            uint32_t reserved_15            : 1; /* [   15],       rsvd,        0x0 */
            uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16],        r/w,        0x0 */
            uint32_t reg_int_idle_en        : 1; /* [   21],        r/w,        0x0 */
            uint32_t sts_idle_int           : 1; /* [   22],          r,        0x0 */
            uint32_t reserved_23            : 1; /* [   23],       rsvd,        0x0 */
            uint32_t frame_valid_cnt        : 5; /* [28:24],          r,        0x0 */
            uint32_t reg_int_swap_en        : 1; /* [   29],        r/w,        0x0 */
            uint32_t sts_swap_int           : 1; /* [   30],          r,        0x0 */
            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_control_3;

    /* 0x20 : mjpeg_frame_fifo_pop */
    union {
        struct
        {
            uint32_t rfifo_pop          : 1;  /* [    0],        w1p,        0x0 */
            uint32_t reg_w_swap_clr     : 1;  /* [    1],        w1p,        0x0 */
            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t reg_int_normal_clr : 1;  /* [    8],        w1p,        0x0 */
            uint32_t reg_int_cam_clr    : 1;  /* [    9],        w1p,        0x0 */
            uint32_t reg_int_mem_clr    : 1;  /* [   10],        w1p,        0x0 */
            uint32_t reg_int_frame_clr  : 1;  /* [   11],        w1p,        0x0 */
            uint32_t reg_int_idle_clr   : 1;  /* [   12],        w1p,        0x0 */
            uint32_t reg_int_swap_clr   : 1;  /* [   13],        w1p,        0x0 */
            uint32_t reserved_14_31     : 18; /* [31:14],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_frame_fifo_pop;

    /* 0x24 : mjpeg_frame_size */
    union {
        struct
        {
            uint32_t reg_frame_wblk : 12; /* [11: 0],        r/w,        0xf */
            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t reg_frame_hblk : 12; /* [27:16],        r/w,       0x14 */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_frame_size;

    /* 0x28 : mjpeg_header_byte */
    union {
        struct
        {
            uint32_t reg_head_byte  : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t reg_tail_exp   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31 : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_header_byte;

    /* 0x2c  reserved */
    uint8_t RESERVED0x2c[4];

    /* 0x30 : mjpeg_swap_mode */
    union {
        struct
        {
            uint32_t reg_w_swap_mode   : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_7      : 7;  /* [ 7: 1],       rsvd,        0x0 */
            uint32_t sts_swap0_full    : 1;  /* [    8],          r,        0x0 */
            uint32_t sts_swap1_full    : 1;  /* [    9],          r,        0x0 */
            uint32_t sts_read_swap_idx : 1;  /* [   10],          r,        0x0 */
            uint32_t sts_swap_fstart   : 1;  /* [   11],          r,        0x0 */
            uint32_t sts_swap_fend     : 1;  /* [   12],          r,        0x0 */
            uint32_t reserved_13_31    : 19; /* [31:13],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_swap_mode;

    /* 0x34 : mjpeg_swap_bit_cnt */
    union {
        struct
        {
            uint32_t frame_swap_end_bit_cnt : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_swap_bit_cnt;

    /* 0x38 : mjpeg_paket_ctrl */
    union {
        struct
        {
            uint32_t reg_pket_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_jend_to_pend   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_15      : 14; /* [15: 2],       rsvd,        0x0 */
            uint32_t reg_pket_body_byte : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_paket_ctrl;

    /* 0x3C : mjpeg_paket_head_tail */
    union {
        struct
        {
            uint32_t reg_pket_head_byte : 12; /* [11: 0],        r/w,        0x0 */
            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t reg_pket_tail_byte : 12; /* [27:16],        r/w,        0x0 */
            uint32_t reserved_28_31     : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_paket_head_tail;

    /* 0x40 : mjpeg_Y_frame_read_status_1 */
    union {
        struct
        {
            uint32_t yy_mem_hblk_r  : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t yy_frm_hblk_r  : 13; /* [28:16],          r,        0x0 */
            uint32_t reserved_29_31 : 3;  /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_Y_frame_read_status_1;

    /* 0x44 : mjpeg_Y_frame_read_status_2 */
    union {
        struct
        {
            uint32_t yy_wblk_r      : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t yy_mem_rnd_r   : 8;  /* [23:16],          r,        0x0 */
            uint32_t yy_frm_cnt_r   : 8;  /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_Y_frame_read_status_2;

    /* 0x48 : mjpeg_Y_frame_write_status */
    union {
        struct
        {
            uint32_t yy_mem_hblk_w  : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t yy_mem_rnd_w   : 8;  /* [23:16],          r,        0x0 */
            uint32_t yy_frm_cnt_w   : 8;  /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_Y_frame_write_status;

    /* 0x4C : mjpeg_UV_frame_read_status_1 */
    union {
        struct
        {
            uint32_t uv_mem_hblk_r  : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t uv_frm_hblk_r  : 13; /* [28:16],          r,        0x0 */
            uint32_t reserved_29_31 : 3;  /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_UV_frame_read_status_1;

    /* 0x50 : mjpeg_UV_frame_read_status_2 */
    union {
        struct
        {
            uint32_t uv_wblk_r      : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t uv_mem_rnd_r   : 8;  /* [23:16],          r,        0x0 */
            uint32_t uv_frm_cnt_r   : 8;  /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_UV_frame_read_status_2;

    /* 0x54 : mjpeg_UV_frame_write_status */
    union {
        struct
        {
            uint32_t uv_mem_hblk_w  : 13; /* [12: 0],          r,        0x0 */
            uint32_t reserved_13_15 : 3;  /* [15:13],       rsvd,        0x0 */
            uint32_t uv_mem_rnd_w   : 8;  /* [23:16],          r,        0x0 */
            uint32_t uv_frm_cnt_w   : 8;  /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_UV_frame_write_status;

    /* 0x58  reserved */
    uint8_t RESERVED0x58[40];

    /* 0x80 : mjpeg_start_addr0 */
    union {
        struct
        {
            uint32_t frame_start_addr_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr0;

    /* 0x84 : mjpeg_bit_cnt0 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt0;

    /* 0x88 : mjpeg_start_addr1 */
    union {
        struct
        {
            uint32_t frame_start_addr_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr1;

    /* 0x8C : mjpeg_bit_cnt1 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt1;

    /* 0x90 : mjpeg_start_addr2 */
    union {
        struct
        {
            uint32_t frame_start_addr_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr2;

    /* 0x94 : mjpeg_bit_cnt2 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt2;

    /* 0x98 : mjpeg_start_addr3 */
    union {
        struct
        {
            uint32_t frame_start_addr_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr3;

    /* 0x9C : mjpeg_bit_cnt3 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt3;

    /* 0xA0 : mjpeg_start_addr4 */
    union {
        struct
        {
            uint32_t frame_start_addr_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr4;

    /* 0xA4 : mjpeg_bit_cnt4 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt4;

    /* 0xA8 : mjpeg_start_addr5 */
    union {
        struct
        {
            uint32_t frame_start_addr_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr5;

    /* 0xAC : mjpeg_bit_cnt5 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt5;

    /* 0xB0 : mjpeg_start_addr6 */
    union {
        struct
        {
            uint32_t frame_start_addr_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr6;

    /* 0xB4 : mjpeg_bit_cnt6 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt6;

    /* 0xB8 : mjpeg_start_addr7 */
    union {
        struct
        {
            uint32_t frame_start_addr_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr7;

    /* 0xBC : mjpeg_bit_cnt7 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt7;

    /* 0xC0 : mjpeg_start_addr_8 */
    union {
        struct
        {
            uint32_t frame_start_addr_8 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_8;

    /* 0xC4 : mjpeg_bit_cnt_8 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_8 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_8;

    /* 0xC8 : mjpeg_start_addr_9 */
    union {
        struct
        {
            uint32_t frame_start_addr_9 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_9;

    /* 0xCC : mjpeg_bit_cnt_9 */
    union {
        struct
        {
            uint32_t frame_bit_cnt_9 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_9;

    /* 0xD0 : mjpeg_start_addr_a */
    union {
        struct
        {
            uint32_t frame_start_addr_a : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_a;

    /* 0xD4 : mjpeg_bit_cnt_a */
    union {
        struct
        {
            uint32_t frame_bit_cnt_a : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_a;

    /* 0xD8 : mjpeg_start_addr_b */
    union {
        struct
        {
            uint32_t frame_start_addr_b : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_b;

    /* 0xDC : mjpeg_bit_cnt_b */
    union {
        struct
        {
            uint32_t frame_bit_cnt_b : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_b;

    /* 0xE0 : mjpeg_start_addr_c */
    union {
        struct
        {
            uint32_t frame_start_addr_c : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_c;

    /* 0xE4 : mjpeg_bit_cnt_c */
    union {
        struct
        {
            uint32_t frame_bit_cnt_c : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_c;

    /* 0xE8 : mjpeg_start_addr_d */
    union {
        struct
        {
            uint32_t frame_start_addr_d : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_d;

    /* 0xEC : mjpeg_bit_cnt_d */
    union {
        struct
        {
            uint32_t frame_bit_cnt_d : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_d;

    /* 0xF0 : mjpeg_start_addr_e */
    union {
        struct
        {
            uint32_t frame_start_addr_e : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_e;

    /* 0xF4 : mjpeg_bit_cnt_e */
    union {
        struct
        {
            uint32_t frame_bit_cnt_e : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_e;

    /* 0xF8 : mjpeg_start_addr_f */
    union {
        struct
        {
            uint32_t frame_start_addr_f : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_start_addr_f;

    /* 0xFC : mjpeg_bit_cnt_f */
    union {
        struct
        {
            uint32_t frame_bit_cnt_f : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_bit_cnt_f;

    /* 0x100 : mjpeg_q_mode0 */
    union {
        struct
        {
            uint32_t frame_q_mode_0 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode0;

    /* 0x104 : mjpeg_q_mode1 */
    union {
        struct
        {
            uint32_t frame_q_mode_1 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode1;

    /* 0x108 : mjpeg_q_mode2 */
    union {
        struct
        {
            uint32_t frame_q_mode_2 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode2;

    /* 0x10C : mjpeg_q_mode3 */
    union {
        struct
        {
            uint32_t frame_q_mode_3 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode3;

    /* 0x110 : mjpeg_q_mode4 */
    union {
        struct
        {
            uint32_t frame_q_mode_4 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode4;

    /* 0x114 : mjpeg_q_mode5 */
    union {
        struct
        {
            uint32_t frame_q_mode_5 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode5;

    /* 0x118 : mjpeg_q_mode6 */
    union {
        struct
        {
            uint32_t frame_q_mode_6 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode6;

    /* 0x11C : mjpeg_q_mode7 */
    union {
        struct
        {
            uint32_t frame_q_mode_7 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode7;

    /* 0x120 : mjpeg_q_mode_8 */
    union {
        struct
        {
            uint32_t frame_q_mode_8 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_8;

    /* 0x124 : mjpeg_q_mode_9 */
    union {
        struct
        {
            uint32_t frame_q_mode_9 : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_9;

    /* 0x128 : mjpeg_q_mode_a */
    union {
        struct
        {
            uint32_t frame_q_mode_a : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_a;

    /* 0x12C : mjpeg_q_mode_b */
    union {
        struct
        {
            uint32_t frame_q_mode_b : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_b;

    /* 0x130 : mjpeg_q_mode_c */
    union {
        struct
        {
            uint32_t frame_q_mode_c : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_c;

    /* 0x134 : mjpeg_q_mode_d */
    union {
        struct
        {
            uint32_t frame_q_mode_d : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_d;

    /* 0x138 : mjpeg_q_mode_e */
    union {
        struct
        {
            uint32_t frame_q_mode_e : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_e;

    /* 0x13C : mjpeg_q_mode_f */
    union {
        struct
        {
            uint32_t frame_q_mode_f : 7;  /* [ 6: 0],          r,        0x0 */
            uint32_t reserved_7_31  : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_q_mode_f;

    /* 0x140  reserved */
    uint8_t RESERVED0x140[176];

    /* 0x1F0 : mjpeg_debug */
    union {
        struct
        {
            uint32_t reg_mjpeg_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3      : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t reg_mjpeg_dbg_sel : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_debug;

    /* 0x1f4  reserved */
    uint8_t RESERVED0x1f4[8];

    /* 0x1FC : mjpeg_dummy_reg */
    union {
        struct
        {
            uint32_t mjpeg_dummy_reg : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } mjpeg_dummy_reg;
};

typedef volatile struct mjpeg_reg mjpeg_reg_t;

#endif /* __MJPEG_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pdm_reg.h
================================================
/**
  ******************************************************************************
  * @file    pdm_reg.h
  * @version V1.2
  * @date    2020-02-13
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PDM_REG_H__
#define __PDM_REG_H__

#include "bl702.h"

/* 0x0 : pdm_datapath_config */
#define PDM_DATAPATH_CONFIG_OFFSET (0x0)
#define PDM_EN                     PDM_EN
#define PDM_EN_POS                 (0U)
#define PDM_EN_LEN                 (1U)
#define PDM_EN_MSK                 (((1U << PDM_EN_LEN) - 1) << PDM_EN_POS)
#define PDM_EN_UMSK                (~(((1U << PDM_EN_LEN) - 1) << PDM_EN_POS))
#define PDM_RX_SEL_128FS           PDM_RX_SEL_128FS
#define PDM_RX_SEL_128FS_POS       (2U)
#define PDM_RX_SEL_128FS_LEN       (1U)
#define PDM_RX_SEL_128FS_MSK       (((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS)
#define PDM_RX_SEL_128FS_UMSK      (~(((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS))
#define PDM_TX_SEL_128FS           PDM_TX_SEL_128FS
#define PDM_TX_SEL_128FS_POS       (3U)
#define PDM_TX_SEL_128FS_LEN       (1U)
#define PDM_TX_SEL_128FS_MSK       (((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS)
#define PDM_TX_SEL_128FS_UMSK      (~(((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS))
#define PDM_DC_MUL                 PDM_DC_MUL
#define PDM_DC_MUL_POS             (4U)
#define PDM_DC_MUL_LEN             (8U)
#define PDM_DC_MUL_MSK             (((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS)
#define PDM_DC_MUL_UMSK            (~(((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS))
#define PDM_SCALE_SEL              PDM_SCALE_SEL
#define PDM_SCALE_SEL_POS          (12U)
#define PDM_SCALE_SEL_LEN          (3U)
#define PDM_SCALE_SEL_MSK          (((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS)
#define PDM_SCALE_SEL_UMSK         (~(((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS))
#define PDM_DITHER_SEL             PDM_DITHER_SEL
#define PDM_DITHER_SEL_POS         (16U)
#define PDM_DITHER_SEL_LEN         (2U)
#define PDM_DITHER_SEL_MSK         (((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS)
#define PDM_DITHER_SEL_UMSK        (~(((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS))
#define PDM_FORCE_LR               PDM_FORCE_LR
#define PDM_FORCE_LR_POS           (20U)
#define PDM_FORCE_LR_LEN           (1U)
#define PDM_FORCE_LR_MSK           (((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS)
#define PDM_FORCE_LR_UMSK          (~(((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS))
#define PDM_FORCE_SEL              PDM_FORCE_SEL
#define PDM_FORCE_SEL_POS          (21U)
#define PDM_FORCE_SEL_LEN          (1U)
#define PDM_FORCE_SEL_MSK          (((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS)
#define PDM_FORCE_SEL_UMSK         (~(((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS))
#define PDM_DSD_SWAP               PDM_DSD_SWAP
#define PDM_DSD_SWAP_POS           (22U)
#define PDM_DSD_SWAP_LEN           (1U)
#define PDM_DSD_SWAP_MSK           (((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS)
#define PDM_DSD_SWAP_UMSK          (~(((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS))
#define PDM_OUT_DAT_DLY            PDM_OUT_DAT_DLY
#define PDM_OUT_DAT_DLY_POS        (24U)
#define PDM_OUT_DAT_DLY_LEN        (2U)
#define PDM_OUT_DAT_DLY_MSK        (((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS)
#define PDM_OUT_DAT_DLY_UMSK       (~(((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS))
#define PDM_OUT_SEL_DLY            PDM_OUT_SEL_DLY
#define PDM_OUT_SEL_DLY_POS        (26U)
#define PDM_OUT_SEL_DLY_LEN        (2U)
#define PDM_OUT_SEL_DLY_MSK        (((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS)
#define PDM_OUT_SEL_DLY_UMSK       (~(((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS))
#define PDM_OUT_SEL_INV            PDM_OUT_SEL_INV
#define PDM_OUT_SEL_INV_POS        (28U)
#define PDM_OUT_SEL_INV_LEN        (1U)
#define PDM_OUT_SEL_INV_MSK        (((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS)
#define PDM_OUT_SEL_INV_UMSK       (~(((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS))

/* 0x4 : pdm_dma_config */
#define PDM_DMA_CONFIG_OFFSET  (0x4)
#define PDM_DMA_RX_EN          PDM_DMA_RX_EN
#define PDM_DMA_RX_EN_POS      (0U)
#define PDM_DMA_RX_EN_LEN      (1U)
#define PDM_DMA_RX_EN_MSK      (((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS)
#define PDM_DMA_RX_EN_UMSK     (~(((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS))
#define PDM_RX_FORMAT          PDM_RX_FORMAT
#define PDM_RX_FORMAT_POS      (4U)
#define PDM_RX_FORMAT_LEN      (3U)
#define PDM_RX_FORMAT_MSK      (((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS)
#define PDM_RX_FORMAT_UMSK     (~(((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS))
#define PDM_DMA_TX_EN          PDM_DMA_TX_EN
#define PDM_DMA_TX_EN_POS      (8U)
#define PDM_DMA_TX_EN_LEN      (1U)
#define PDM_DMA_TX_EN_MSK      (((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS)
#define PDM_DMA_TX_EN_UMSK     (~(((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS))
#define PDM_TX_FORMAT          PDM_TX_FORMAT
#define PDM_TX_FORMAT_POS      (12U)
#define PDM_TX_FORMAT_LEN      (3U)
#define PDM_TX_FORMAT_MSK      (((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS)
#define PDM_TX_FORMAT_UMSK     (~(((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS))
#define PDM_TX_DATA_SHIFT      PDM_TX_DATA_SHIFT
#define PDM_TX_DATA_SHIFT_POS  (16U)
#define PDM_TX_DATA_SHIFT_LEN  (5U)
#define PDM_TX_DATA_SHIFT_MSK  (((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS)
#define PDM_TX_DATA_SHIFT_UMSK (~(((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS))

/* 0x8 : pdm_dma_wdata2 */
#define PDM_DMA_WDATA2_OFFSET (0x8)
#define PDM_DMA_WDATA2        PDM_DMA_WDATA2
#define PDM_DMA_WDATA2_POS    (0U)
#define PDM_DMA_WDATA2_LEN    (32U)
#define PDM_DMA_WDATA2_MSK    (((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS)
#define PDM_DMA_WDATA2_UMSK   (~(((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS))

/* 0x10 : pdm_dma_wdata */
#define PDM_DMA_WDATA_OFFSET (0x10)
#define PDM_DMA_WDATA        PDM_DMA_WDATA
#define PDM_DMA_WDATA_POS    (0U)
#define PDM_DMA_WDATA_LEN    (32U)
#define PDM_DMA_WDATA_MSK    (((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS)
#define PDM_DMA_WDATA_UMSK   (~(((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS))

/* 0x14 : pdm_dma_rdata */
#define PDM_DMA_RDATA_OFFSET (0x14)
#define PDM_DMA_RDATA        PDM_DMA_RDATA
#define PDM_DMA_RDATA_POS    (0U)
#define PDM_DMA_RDATA_LEN    (32U)
#define PDM_DMA_RDATA_MSK    (((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS)
#define PDM_DMA_RDATA_UMSK   (~(((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS))

/* 0x18 : pdm_tx_fifo_status */
#define PDM_TX_FIFO_STATUS_OFFSET (0x18)
#define PDM_TX_FIFO_EMPTY         PDM_TX_FIFO_EMPTY
#define PDM_TX_FIFO_EMPTY_POS     (0U)
#define PDM_TX_FIFO_EMPTY_LEN     (1U)
#define PDM_TX_FIFO_EMPTY_MSK     (((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS)
#define PDM_TX_FIFO_EMPTY_UMSK    (~(((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS))
#define PDM_TX_FIFO_FULL          PDM_TX_FIFO_FULL
#define PDM_TX_FIFO_FULL_POS      (1U)
#define PDM_TX_FIFO_FULL_LEN      (1U)
#define PDM_TX_FIFO_FULL_MSK      (((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS)
#define PDM_TX_FIFO_FULL_UMSK     (~(((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS))
#define PDM_TX_CS                 PDM_TX_CS
#define PDM_TX_CS_POS             (2U)
#define PDM_TX_CS_LEN             (2U)
#define PDM_TX_CS_MSK             (((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS)
#define PDM_TX_CS_UMSK            (~(((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS))
#define PDM_TXFIFORDPTR           PDM_TXFIFORDPTR
#define PDM_TXFIFORDPTR_POS       (4U)
#define PDM_TXFIFORDPTR_LEN       (3U)
#define PDM_TXFIFORDPTR_MSK       (((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS)
#define PDM_TXFIFORDPTR_UMSK      (~(((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS))
#define PDM_TXFIFOWRPTR           PDM_TXFIFOWRPTR
#define PDM_TXFIFOWRPTR_POS       (8U)
#define PDM_TXFIFOWRPTR_LEN       (2U)
#define PDM_TXFIFOWRPTR_MSK       (((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS)
#define PDM_TXFIFOWRPTR_UMSK      (~(((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS))
#define PDM_TX2_FIFO_EMPTY        PDM_TX2_FIFO_EMPTY
#define PDM_TX2_FIFO_EMPTY_POS    (16U)
#define PDM_TX2_FIFO_EMPTY_LEN    (1U)
#define PDM_TX2_FIFO_EMPTY_MSK    (((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS)
#define PDM_TX2_FIFO_EMPTY_UMSK   (~(((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS))
#define PDM_TX2_FIFO_FULL         PDM_TX2_FIFO_FULL
#define PDM_TX2_FIFO_FULL_POS     (17U)
#define PDM_TX2_FIFO_FULL_LEN     (1U)
#define PDM_TX2_FIFO_FULL_MSK     (((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS)
#define PDM_TX2_FIFO_FULL_UMSK    (~(((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS))
#define PDM_TX2_CS                PDM_TX2_CS
#define PDM_TX2_CS_POS            (18U)
#define PDM_TX2_CS_LEN            (2U)
#define PDM_TX2_CS_MSK            (((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS)
#define PDM_TX2_CS_UMSK           (~(((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS))
#define PDM_TX2FIFORDPTR          PDM_TX2FIFORDPTR
#define PDM_TX2FIFORDPTR_POS      (20U)
#define PDM_TX2FIFORDPTR_LEN      (3U)
#define PDM_TX2FIFORDPTR_MSK      (((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS)
#define PDM_TX2FIFORDPTR_UMSK     (~(((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS))
#define PDM_TX2FIFOWRPTR          PDM_TX2FIFOWRPTR
#define PDM_TX2FIFOWRPTR_POS      (24U)
#define PDM_TX2FIFOWRPTR_LEN      (2U)
#define PDM_TX2FIFOWRPTR_MSK      (((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS)
#define PDM_TX2FIFOWRPTR_UMSK     (~(((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS))

/* 0x1C : pdm_rx_fifo_status */
#define PDM_RX_FIFO_STATUS_OFFSET (0x1C)
#define PDM_RX_FIFO_EMPTY         PDM_RX_FIFO_EMPTY
#define PDM_RX_FIFO_EMPTY_POS     (0U)
#define PDM_RX_FIFO_EMPTY_LEN     (1U)
#define PDM_RX_FIFO_EMPTY_MSK     (((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS)
#define PDM_RX_FIFO_EMPTY_UMSK    (~(((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS))
#define PDM_RX_FIFO_FULL          PDM_RX_FIFO_FULL
#define PDM_RX_FIFO_FULL_POS      (1U)
#define PDM_RX_FIFO_FULL_LEN      (1U)
#define PDM_RX_FIFO_FULL_MSK      (((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS)
#define PDM_RX_FIFO_FULL_UMSK     (~(((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS))
#define PDM_RX_CS                 PDM_RX_CS
#define PDM_RX_CS_POS             (2U)
#define PDM_RX_CS_LEN             (2U)
#define PDM_RX_CS_MSK             (((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS)
#define PDM_RX_CS_UMSK            (~(((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS))
#define PDM_RXFIFORDPTR           PDM_RXFIFORDPTR
#define PDM_RXFIFORDPTR_POS       (4U)
#define PDM_RXFIFORDPTR_LEN       (2U)
#define PDM_RXFIFORDPTR_MSK       (((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS)
#define PDM_RXFIFORDPTR_UMSK      (~(((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS))
#define PDM_RXFIFOWRPTR           PDM_RXFIFOWRPTR
#define PDM_RXFIFOWRPTR_POS       (8U)
#define PDM_RXFIFOWRPTR_LEN       (3U)
#define PDM_RXFIFOWRPTR_MSK       (((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS)
#define PDM_RXFIFOWRPTR_UMSK      (~(((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS))

struct pdm_reg {
    /* 0x0 : pdm_datapath_config */
    union {
        struct
        {
            uint32_t pdm_en         : 1; /* [    0],        r/w,        0x0 */
            uint32_t reserved_1     : 1; /* [    1],       rsvd,        0x0 */
            uint32_t rx_sel_128fs   : 1; /* [    2],        r/w,        0x0 */
            uint32_t tx_sel_128fs   : 1; /* [    3],        r/w,        0x0 */
            uint32_t dc_mul         : 8; /* [11: 4],        r/w,       0x64 */
            uint32_t scale_sel      : 3; /* [14:12],        r/w,        0x5 */
            uint32_t reserved_15    : 1; /* [   15],       rsvd,        0x0 */
            uint32_t dither_sel     : 2; /* [17:16],        r/w,        0x1 */
            uint32_t reserved_18_19 : 2; /* [19:18],       rsvd,        0x0 */
            uint32_t force_lr       : 1; /* [   20],        r/w,        0x0 */
            uint32_t force_sel      : 1; /* [   21],        r/w,        0x0 */
            uint32_t dsd_swap       : 1; /* [   22],        r/w,        0x0 */
            uint32_t reserved_23    : 1; /* [   23],       rsvd,        0x0 */
            uint32_t out_dat_dly    : 2; /* [25:24],        r/w,        0x0 */
            uint32_t out_sel_dly    : 2; /* [27:26],        r/w,        0x0 */
            uint32_t out_sel_inv    : 1; /* [   28],        r/w,        0x0 */
            uint32_t rsvd_31_29     : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pdm_datapath_config;

    /* 0x4 : pdm_dma_config */
    union {
        struct
        {
            uint32_t pdm_dma_rx_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3   : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t rx_format      : 3;  /* [ 6: 4],        r/w,        0x3 */
            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t pdm_dma_tx_en  : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_11  : 3;  /* [11: 9],       rsvd,        0x0 */
            uint32_t tx_format      : 3;  /* [14:12],        r/w,        0x3 */
            uint32_t reserved_15    : 1;  /* [   15],       rsvd,        0x0 */
            uint32_t tx_data_shift  : 5;  /* [20:16],        r/w,        0x0 */
            uint32_t reserved_21_31 : 11; /* [31:21],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pdm_dma_config;

    /* 0x8 : pdm_dma_wdata2 */
    union {
        struct
        {
            uint32_t pdm_dma_wdata2 : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } pdm_dma_wdata2;

    /* 0xc  reserved */
    uint8_t RESERVED0xc[4];

    /* 0x10 : pdm_dma_wdata */
    union {
        struct
        {
            uint32_t pdm_dma_wdata : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } pdm_dma_wdata;

    /* 0x14 : pdm_dma_rdata */
    union {
        struct
        {
            uint32_t pdm_dma_rdata : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } pdm_dma_rdata;

    /* 0x18 : pdm_tx_fifo_status */
    union {
        struct
        {
            uint32_t tx_fifo_empty  : 1; /* [    0],          r,        0x0 */
            uint32_t tx_fifo_full   : 1; /* [    1],          r,        0x0 */
            uint32_t tx_cs          : 2; /* [ 3: 2],          r,        0x0 */
            uint32_t TxFifoRdPtr    : 3; /* [ 6: 4],          r,        0x4 */
            uint32_t reserved_7     : 1; /* [    7],       rsvd,        0x0 */
            uint32_t TxFifoWrPtr    : 2; /* [ 9: 8],          r,        0x0 */
            uint32_t reserved_10_15 : 6; /* [15:10],       rsvd,        0x0 */
            uint32_t tx2_fifo_empty : 1; /* [   16],          r,        0x0 */
            uint32_t tx2_fifo_full  : 1; /* [   17],          r,        0x0 */
            uint32_t tx2_cs         : 2; /* [19:18],          r,        0x0 */
            uint32_t Tx2FifoRdPtr   : 3; /* [22:20],          r,        0x4 */
            uint32_t reserved_23    : 1; /* [   23],       rsvd,        0x0 */
            uint32_t Tx2FifoWrPtr   : 2; /* [25:24],          r,        0x0 */
            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pdm_tx_fifo_status;

    /* 0x1C : pdm_rx_fifo_status */
    union {
        struct
        {
            uint32_t rx_fifo_empty  : 1;  /* [    0],          r,        0x1 */
            uint32_t rx_fifo_full   : 1;  /* [    1],          r,        0x0 */
            uint32_t rx_cs          : 2;  /* [ 3: 2],          r,        0x0 */
            uint32_t RxFifoRdPtr    : 2;  /* [ 5: 4],          r,        0x3 */
            uint32_t reserved_6_7   : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t RxFifoWrPtr    : 3;  /* [10: 8],          r,        0x0 */
            uint32_t reserved_11_31 : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pdm_rx_fifo_status;
};

typedef volatile struct pdm_reg pdm_reg_t;

#endif /* __PDM_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pds_reg.h
================================================
/**
  ******************************************************************************
  * @file    pds_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PDS_REG_H__
#define __PDS_REG_H__

#include "bl702.h"

/* 0x0 : PDS_CTL */
#define PDS_CTL_OFFSET                     (0x0)
#define PDS_START_PS                       PDS_START_PS
#define PDS_START_PS_POS                   (0U)
#define PDS_START_PS_LEN                   (1U)
#define PDS_START_PS_MSK                   (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
#define PDS_START_PS_UMSK                  (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
#define PDS_CR_SLEEP_FOREVER               PDS_CR_SLEEP_FOREVER
#define PDS_CR_SLEEP_FOREVER_POS           (1U)
#define PDS_CR_SLEEP_FOREVER_LEN           (1U)
#define PDS_CR_SLEEP_FOREVER_MSK           (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
#define PDS_CR_SLEEP_FOREVER_UMSK          (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
#define PDS_CR_XTAL_FORCE_OFF              PDS_CR_XTAL_FORCE_OFF
#define PDS_CR_XTAL_FORCE_OFF_POS          (2U)
#define PDS_CR_XTAL_FORCE_OFF_LEN          (1U)
#define PDS_CR_XTAL_FORCE_OFF_MSK          (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
#define PDS_CR_XTAL_FORCE_OFF_UMSK         (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
#define PDS_CR_WIFI_PDS_SAVE_STATE         PDS_CR_WIFI_PDS_SAVE_STATE
#define PDS_CR_WIFI_PDS_SAVE_STATE_POS     (3U)
#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN     (1U)
#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK     (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)
#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK    (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS))
#define PDS_CR_PDS_PD_DCDC18               PDS_CR_PDS_PD_DCDC18
#define PDS_CR_PDS_PD_DCDC18_POS           (4U)
#define PDS_CR_PDS_PD_DCDC18_LEN           (1U)
#define PDS_CR_PDS_PD_DCDC18_MSK           (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
#define PDS_CR_PDS_PD_DCDC18_UMSK          (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
#define PDS_CR_PDS_PD_BG_SYS               PDS_CR_PDS_PD_BG_SYS
#define PDS_CR_PDS_PD_BG_SYS_POS           (5U)
#define PDS_CR_PDS_PD_BG_SYS_LEN           (1U)
#define PDS_CR_PDS_PD_BG_SYS_MSK           (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
#define PDS_CR_PDS_PD_BG_SYS_UMSK          (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD      PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS  (6U)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN  (1U)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK  (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
#define PDS_CR_PDS_CTRL_PU_FLASH           PDS_CR_PDS_CTRL_PU_FLASH
#define PDS_CR_PDS_CTRL_PU_FLASH_POS       (7U)
#define PDS_CR_PDS_CTRL_PU_FLASH_LEN       (1U)
#define PDS_CR_PDS_CTRL_PU_FLASH_MSK       (((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS)
#define PDS_CR_PDS_CTRL_PU_FLASH_UMSK      (~(((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS))
#define PDS_CR_PDS_GATE_CLK                PDS_CR_PDS_GATE_CLK
#define PDS_CR_PDS_GATE_CLK_POS            (8U)
#define PDS_CR_PDS_GATE_CLK_LEN            (1U)
#define PDS_CR_PDS_GATE_CLK_MSK            (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
#define PDS_CR_PDS_GATE_CLK_UMSK           (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
#define PDS_CR_PDS_MEM_STBY                PDS_CR_PDS_MEM_STBY
#define PDS_CR_PDS_MEM_STBY_POS            (9U)
#define PDS_CR_PDS_MEM_STBY_LEN            (1U)
#define PDS_CR_PDS_MEM_STBY_MSK            (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
#define PDS_CR_PDS_MEM_STBY_UMSK           (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
#define PDS_CR_SW_PU_FLASH                 PDS_CR_SW_PU_FLASH
#define PDS_CR_SW_PU_FLASH_POS             (10U)
#define PDS_CR_SW_PU_FLASH_LEN             (1U)
#define PDS_CR_SW_PU_FLASH_MSK             (((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS)
#define PDS_CR_SW_PU_FLASH_UMSK            (~(((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS))
#define PDS_CR_PDS_ISO_EN                  PDS_CR_PDS_ISO_EN
#define PDS_CR_PDS_ISO_EN_POS              (11U)
#define PDS_CR_PDS_ISO_EN_LEN              (1U)
#define PDS_CR_PDS_ISO_EN_MSK              (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
#define PDS_CR_PDS_ISO_EN_UMSK             (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
#define PDS_CR_PDS_WAIT_XTAL_RDY           PDS_CR_PDS_WAIT_XTAL_RDY
#define PDS_CR_PDS_WAIT_XTAL_RDY_POS       (12U)
#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN       (1U)
#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK       (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK      (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
#define PDS_CR_PDS_PWR_OFF                 PDS_CR_PDS_PWR_OFF
#define PDS_CR_PDS_PWR_OFF_POS             (13U)
#define PDS_CR_PDS_PWR_OFF_LEN             (1U)
#define PDS_CR_PDS_PWR_OFF_MSK             (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
#define PDS_CR_PDS_PWR_OFF_UMSK            (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
#define PDS_CR_PDS_PD_XTAL                 PDS_CR_PDS_PD_XTAL
#define PDS_CR_PDS_PD_XTAL_POS             (14U)
#define PDS_CR_PDS_PD_XTAL_LEN             (1U)
#define PDS_CR_PDS_PD_XTAL_MSK             (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
#define PDS_CR_PDS_PD_XTAL_UMSK            (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
#define PDS_CR_PDS_SOC_ENB_FORCE_ON        PDS_CR_PDS_SOC_ENB_FORCE_ON
#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS    (15U)
#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN    (1U)
#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK    (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)
#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK   (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS))
#define PDS_CR_PDS_RST_SOC_EN              PDS_CR_PDS_RST_SOC_EN
#define PDS_CR_PDS_RST_SOC_EN_POS          (16U)
#define PDS_CR_PDS_RST_SOC_EN_LEN          (1U)
#define PDS_CR_PDS_RST_SOC_EN_MSK          (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)
#define PDS_CR_PDS_RST_SOC_EN_UMSK         (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS))
#define PDS_CR_PDS_RC32M_OFF_DIS           PDS_CR_PDS_RC32M_OFF_DIS
#define PDS_CR_PDS_RC32M_OFF_DIS_POS       (17U)
#define PDS_CR_PDS_RC32M_OFF_DIS_LEN       (1U)
#define PDS_CR_PDS_RC32M_OFF_DIS_MSK       (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK      (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
#define PDS_CR_PDS_LDO_VSEL_EN             PDS_CR_PDS_LDO_VSEL_EN
#define PDS_CR_PDS_LDO_VSEL_EN_POS         (18U)
#define PDS_CR_PDS_LDO_VSEL_EN_LEN         (1U)
#define PDS_CR_PDS_LDO_VSEL_EN_MSK         (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)
#define PDS_CR_PDS_LDO_VSEL_EN_UMSK        (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS))
#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN      PDS_CR_PDS_RAM_LP_WITH_CLK_EN
#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS  (19U)
#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN  (1U)
#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_MSK  (((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS)
#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS))
#define PDS_CR_NP_WFI_MASK                 PDS_CR_NP_WFI_MASK
#define PDS_CR_NP_WFI_MASK_POS             (21U)
#define PDS_CR_NP_WFI_MASK_LEN             (1U)
#define PDS_CR_NP_WFI_MASK_MSK             (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
#define PDS_CR_NP_WFI_MASK_UMSK            (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
#define PDS_CR_PDS_PD_LDO11                PDS_CR_PDS_PD_LDO11
#define PDS_CR_PDS_PD_LDO11_POS            (22U)
#define PDS_CR_PDS_PD_LDO11_LEN            (1U)
#define PDS_CR_PDS_PD_LDO11_MSK            (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
#define PDS_CR_PDS_PD_LDO11_UMSK           (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
#define PDS_CR_PDS_FORCE_RAM_CLK_EN        PDS_CR_PDS_FORCE_RAM_CLK_EN
#define PDS_CR_PDS_FORCE_RAM_CLK_EN_POS    (23U)
#define PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN    (1U)
#define PDS_CR_PDS_FORCE_RAM_CLK_EN_MSK    (((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS)
#define PDS_CR_PDS_FORCE_RAM_CLK_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS))
#define PDS_CR_PDS_LDO_VOL                 PDS_CR_PDS_LDO_VOL
#define PDS_CR_PDS_LDO_VOL_POS             (24U)
#define PDS_CR_PDS_LDO_VOL_LEN             (4U)
#define PDS_CR_PDS_LDO_VOL_MSK             (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)
#define PDS_CR_PDS_LDO_VOL_UMSK            (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS))
#define PDS_CR_PDS_CTRL_RF                 PDS_CR_PDS_CTRL_RF
#define PDS_CR_PDS_CTRL_RF_POS             (28U)
#define PDS_CR_PDS_CTRL_RF_LEN             (2U)
#define PDS_CR_PDS_CTRL_RF_MSK             (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
#define PDS_CR_PDS_CTRL_RF_UMSK            (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
#define PDS_CR_PDS_CTRL_PLL                PDS_CR_PDS_CTRL_PLL
#define PDS_CR_PDS_CTRL_PLL_POS            (30U)
#define PDS_CR_PDS_CTRL_PLL_LEN            (2U)
#define PDS_CR_PDS_CTRL_PLL_MSK            (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)
#define PDS_CR_PDS_CTRL_PLL_UMSK           (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS))

/* 0x4 : PDS_TIME1 */
#define PDS_TIME1_OFFSET           (0x4)
#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
#define PDS_CR_SLEEP_DURATION_POS  (0U)
#define PDS_CR_SLEEP_DURATION_LEN  (32U)
#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))

/* 0xC : PDS_INT */
#define PDS_INT_OFFSET                    (0xC)
#define PDS_RO_PDS_WAKE_INT               PDS_RO_PDS_WAKE_INT
#define PDS_RO_PDS_WAKE_INT_POS           (0U)
#define PDS_RO_PDS_WAKE_INT_LEN           (1U)
#define PDS_RO_PDS_WAKE_INT_MSK           (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
#define PDS_RO_PDS_WAKE_INT_UMSK          (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
#define PDS_RO_PDS_RF_DONE_INT            PDS_RO_PDS_RF_DONE_INT
#define PDS_RO_PDS_RF_DONE_INT_POS        (2U)
#define PDS_RO_PDS_RF_DONE_INT_LEN        (1U)
#define PDS_RO_PDS_RF_DONE_INT_MSK        (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
#define PDS_RO_PDS_RF_DONE_INT_UMSK       (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
#define PDS_RO_PDS_PLL_DONE_INT           PDS_RO_PDS_PLL_DONE_INT
#define PDS_RO_PDS_PLL_DONE_INT_POS       (3U)
#define PDS_RO_PDS_PLL_DONE_INT_LEN       (1U)
#define PDS_RO_PDS_PLL_DONE_INT_MSK       (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)
#define PDS_RO_PDS_PLL_DONE_INT_UMSK      (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS))
#define PDS_RESET_EVENT                   PDS_RESET_EVENT
#define PDS_RESET_EVENT_POS               (4U)
#define PDS_RESET_EVENT_LEN               (3U)
#define PDS_RESET_EVENT_MSK               (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
#define PDS_RESET_EVENT_UMSK              (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
#define PDS_CLR_RESET_EVENT               PDS_CLR_RESET_EVENT
#define PDS_CLR_RESET_EVENT_POS           (7U)
#define PDS_CLR_RESET_EVENT_LEN           (1U)
#define PDS_CLR_RESET_EVENT_MSK           (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
#define PDS_CLR_RESET_EVENT_UMSK          (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
#define PDS_CR_PDS_WAKE_INT_MASK          PDS_CR_PDS_WAKE_INT_MASK
#define PDS_CR_PDS_WAKE_INT_MASK_POS      (8U)
#define PDS_CR_PDS_WAKE_INT_MASK_LEN      (1U)
#define PDS_CR_PDS_WAKE_INT_MASK_MSK      (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
#define PDS_CR_PDS_WAKE_INT_MASK_UMSK     (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
#define PDS_CR_PDS_RF_DONE_INT_MASK       PDS_CR_PDS_RF_DONE_INT_MASK
#define PDS_CR_PDS_RF_DONE_INT_MASK_POS   (10U)
#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN   (1U)
#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK   (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK  (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
#define PDS_CR_PDS_PLL_DONE_INT_MASK      PDS_CR_PDS_PLL_DONE_INT_MASK
#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS  (11U)
#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN  (1U)
#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK  (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)
#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS))
#define PDS_CR_PDS_INT_CLR                PDS_CR_PDS_INT_CLR
#define PDS_CR_PDS_INT_CLR_POS            (15U)
#define PDS_CR_PDS_INT_CLR_LEN            (1U)
#define PDS_CR_PDS_INT_CLR_MSK            (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
#define PDS_CR_PDS_INT_CLR_UMSK           (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
#define PDS_CR_PDS_WAKEUP_SRC_EN          PDS_CR_PDS_WAKEUP_SRC_EN
#define PDS_CR_PDS_WAKEUP_SRC_EN_POS      (16U)
#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN      (8U)
#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK      (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK     (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
#define PDS_RO_PDS_WAKEUP_EVENT           PDS_RO_PDS_WAKEUP_EVENT
#define PDS_RO_PDS_WAKEUP_EVENT_POS       (24U)
#define PDS_RO_PDS_WAKEUP_EVENT_LEN       (8U)
#define PDS_RO_PDS_WAKEUP_EVENT_MSK       (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
#define PDS_RO_PDS_WAKEUP_EVENT_UMSK      (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))

/* 0x10 : PDS_CTL2 */
#define PDS_CTL2_OFFSET                    (0x10)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF        PDS_CR_PDS_FORCE_NP_PWR_OFF
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS    (0U)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_BZ_PWR_OFF        PDS_CR_PDS_FORCE_BZ_PWR_OFF
#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS    (2U)
#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_USB_PWR_OFF       PDS_CR_PDS_FORCE_USB_PWR_OFF
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS   (3U)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN   (1U)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_NP_ISO_EN         PDS_CR_PDS_FORCE_NP_ISO_EN
#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS     (4U)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN     (1U)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_BZ_ISO_EN         PDS_CR_PDS_FORCE_BZ_ISO_EN
#define PDS_CR_PDS_FORCE_BZ_ISO_EN_POS     (6U)
#define PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN     (1U)
#define PDS_CR_PDS_FORCE_BZ_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_BZ_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_USB_ISO_EN        PDS_CR_PDS_FORCE_USB_ISO_EN
#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS    (7U)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN    (1U)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_NP_PDS_RST        PDS_CR_PDS_FORCE_NP_PDS_RST
#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS    (8U)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN    (1U)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_BZ_PDS_RST        PDS_CR_PDS_FORCE_BZ_PDS_RST
#define PDS_CR_PDS_FORCE_BZ_PDS_RST_POS    (10U)
#define PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN    (1U)
#define PDS_CR_PDS_FORCE_BZ_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_BZ_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_USB_PDS_RST       PDS_CR_PDS_FORCE_USB_PDS_RST
#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS   (11U)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN   (1U)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_NP_MEM_STBY       PDS_CR_PDS_FORCE_NP_MEM_STBY
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS   (12U)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_BZ_MEM_STBY       PDS_CR_PDS_FORCE_BZ_MEM_STBY
#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS   (14U)
#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_USB_MEM_STBY      PDS_CR_PDS_FORCE_USB_MEM_STBY
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS  (15U)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN  (1U)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_NP_GATE_CLK       PDS_CR_PDS_FORCE_NP_GATE_CLK
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS   (16U)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
#define PDS_CR_PDS_FORCE_BZ_GATE_CLK       PDS_CR_PDS_FORCE_BZ_GATE_CLK
#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS   (18U)
#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS))
#define PDS_CR_PDS_FORCE_USB_GATE_CLK      PDS_CR_PDS_FORCE_USB_GATE_CLK
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS  (19U)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN  (1U)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))

/* 0x14 : PDS_CTL3 */
#define PDS_CTL3_OFFSET                     (0x14)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_BLE_PWR_OFF        PDS_CR_PDS_FORCE_BLE_PWR_OFF
#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS    (2U)
#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN    (1U)
#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS)
#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS))
#define PDS_CR_PDS_FORCE_BLE_ISO_EN         PDS_CR_PDS_FORCE_BLE_ISO_EN
#define PDS_CR_PDS_FORCE_BLE_ISO_EN_POS     (5U)
#define PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN     (1U)
#define PDS_CR_PDS_FORCE_BLE_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS)
#define PDS_CR_PDS_FORCE_BLE_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS))
#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_BLE_PDS_RST        PDS_CR_PDS_FORCE_BLE_PDS_RST
#define PDS_CR_PDS_FORCE_BLE_PDS_RST_POS    (8U)
#define PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN    (1U)
#define PDS_CR_PDS_FORCE_BLE_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS)
#define PDS_CR_PDS_FORCE_BLE_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS))
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_BLE_MEM_STBY       PDS_CR_PDS_FORCE_BLE_MEM_STBY
#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS   (11U)
#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN   (1U)
#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS)
#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS))
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
#define PDS_CR_PDS_FORCE_BLE_GATE_CLK       PDS_CR_PDS_FORCE_BLE_GATE_CLK
#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS   (14U)
#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN   (1U)
#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS)
#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS))
#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
#define PDS_CR_PDS_BZ_ISO_EN                PDS_CR_PDS_BZ_ISO_EN
#define PDS_CR_PDS_BZ_ISO_EN_POS            (27U)
#define PDS_CR_PDS_BZ_ISO_EN_LEN            (1U)
#define PDS_CR_PDS_BZ_ISO_EN_MSK            (((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS)
#define PDS_CR_PDS_BZ_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS))
#define PDS_CR_PDS_BLE_ISO_EN               PDS_CR_PDS_BLE_ISO_EN
#define PDS_CR_PDS_BLE_ISO_EN_POS           (28U)
#define PDS_CR_PDS_BLE_ISO_EN_LEN           (1U)
#define PDS_CR_PDS_BLE_ISO_EN_MSK           (((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS)
#define PDS_CR_PDS_BLE_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS))
#define PDS_CR_PDS_USB_ISO_EN               PDS_CR_PDS_USB_ISO_EN
#define PDS_CR_PDS_USB_ISO_EN_POS           (29U)
#define PDS_CR_PDS_USB_ISO_EN_LEN           (1U)
#define PDS_CR_PDS_USB_ISO_EN_MSK           (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
#define PDS_CR_PDS_USB_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))

/* 0x18 : PDS_CTL4 */
#define PDS_CTL4_OFFSET                  (0x18)
#define PDS_CR_PDS_NP_PWR_OFF            PDS_CR_PDS_NP_PWR_OFF
#define PDS_CR_PDS_NP_PWR_OFF_POS        (0U)
#define PDS_CR_PDS_NP_PWR_OFF_LEN        (1U)
#define PDS_CR_PDS_NP_PWR_OFF_MSK        (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
#define PDS_CR_PDS_NP_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
#define PDS_CR_PDS_NP_RESET              PDS_CR_PDS_NP_RESET
#define PDS_CR_PDS_NP_RESET_POS          (1U)
#define PDS_CR_PDS_NP_RESET_LEN          (1U)
#define PDS_CR_PDS_NP_RESET_MSK          (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
#define PDS_CR_PDS_NP_RESET_UMSK         (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
#define PDS_CR_PDS_NP_MEM_STBY           PDS_CR_PDS_NP_MEM_STBY
#define PDS_CR_PDS_NP_MEM_STBY_POS       (2U)
#define PDS_CR_PDS_NP_MEM_STBY_LEN       (1U)
#define PDS_CR_PDS_NP_MEM_STBY_MSK       (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
#define PDS_CR_PDS_NP_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
#define PDS_CR_PDS_NP_GATE_CLK           PDS_CR_PDS_NP_GATE_CLK
#define PDS_CR_PDS_NP_GATE_CLK_POS       (3U)
#define PDS_CR_PDS_NP_GATE_CLK_LEN       (1U)
#define PDS_CR_PDS_NP_GATE_CLK_MSK       (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
#define PDS_CR_PDS_NP_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
#define PDS_CR_PDS_BZ_PWR_OFF            PDS_CR_PDS_BZ_PWR_OFF
#define PDS_CR_PDS_BZ_PWR_OFF_POS        (12U)
#define PDS_CR_PDS_BZ_PWR_OFF_LEN        (1U)
#define PDS_CR_PDS_BZ_PWR_OFF_MSK        (((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS)
#define PDS_CR_PDS_BZ_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS))
#define PDS_CR_PDS_BZ_RESET              PDS_CR_PDS_BZ_RESET
#define PDS_CR_PDS_BZ_RESET_POS          (13U)
#define PDS_CR_PDS_BZ_RESET_LEN          (1U)
#define PDS_CR_PDS_BZ_RESET_MSK          (((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS)
#define PDS_CR_PDS_BZ_RESET_UMSK         (~(((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS))
#define PDS_CR_PDS_BZ_MEM_STBY           PDS_CR_PDS_BZ_MEM_STBY
#define PDS_CR_PDS_BZ_MEM_STBY_POS       (14U)
#define PDS_CR_PDS_BZ_MEM_STBY_LEN       (1U)
#define PDS_CR_PDS_BZ_MEM_STBY_MSK       (((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS)
#define PDS_CR_PDS_BZ_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS))
#define PDS_CR_PDS_BZ_GATE_CLK           PDS_CR_PDS_BZ_GATE_CLK
#define PDS_CR_PDS_BZ_GATE_CLK_POS       (15U)
#define PDS_CR_PDS_BZ_GATE_CLK_LEN       (1U)
#define PDS_CR_PDS_BZ_GATE_CLK_MSK       (((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS)
#define PDS_CR_PDS_BZ_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS))
#define PDS_CR_PDS_BLE_PWR_OFF           PDS_CR_PDS_BLE_PWR_OFF
#define PDS_CR_PDS_BLE_PWR_OFF_POS       (16U)
#define PDS_CR_PDS_BLE_PWR_OFF_LEN       (1U)
#define PDS_CR_PDS_BLE_PWR_OFF_MSK       (((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS)
#define PDS_CR_PDS_BLE_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS))
#define PDS_CR_PDS_BLE_RESET             PDS_CR_PDS_BLE_RESET
#define PDS_CR_PDS_BLE_RESET_POS         (17U)
#define PDS_CR_PDS_BLE_RESET_LEN         (1U)
#define PDS_CR_PDS_BLE_RESET_MSK         (((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS)
#define PDS_CR_PDS_BLE_RESET_UMSK        (~(((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS))
#define PDS_CR_PDS_BLE_MEM_STBY          PDS_CR_PDS_BLE_MEM_STBY
#define PDS_CR_PDS_BLE_MEM_STBY_POS      (18U)
#define PDS_CR_PDS_BLE_MEM_STBY_LEN      (1U)
#define PDS_CR_PDS_BLE_MEM_STBY_MSK      (((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS)
#define PDS_CR_PDS_BLE_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS))
#define PDS_CR_PDS_BLE_GATE_CLK          PDS_CR_PDS_BLE_GATE_CLK
#define PDS_CR_PDS_BLE_GATE_CLK_POS      (19U)
#define PDS_CR_PDS_BLE_GATE_CLK_LEN      (1U)
#define PDS_CR_PDS_BLE_GATE_CLK_MSK      (((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS)
#define PDS_CR_PDS_BLE_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS))
#define PDS_CR_PDS_USB_PWR_OFF           PDS_CR_PDS_USB_PWR_OFF
#define PDS_CR_PDS_USB_PWR_OFF_POS       (20U)
#define PDS_CR_PDS_USB_PWR_OFF_LEN       (1U)
#define PDS_CR_PDS_USB_PWR_OFF_MSK       (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
#define PDS_CR_PDS_USB_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
#define PDS_CR_PDS_USB_RESET             PDS_CR_PDS_USB_RESET
#define PDS_CR_PDS_USB_RESET_POS         (21U)
#define PDS_CR_PDS_USB_RESET_LEN         (1U)
#define PDS_CR_PDS_USB_RESET_MSK         (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
#define PDS_CR_PDS_USB_RESET_UMSK        (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
#define PDS_CR_PDS_USB_MEM_STBY          PDS_CR_PDS_USB_MEM_STBY
#define PDS_CR_PDS_USB_MEM_STBY_POS      (22U)
#define PDS_CR_PDS_USB_MEM_STBY_LEN      (1U)
#define PDS_CR_PDS_USB_MEM_STBY_MSK      (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
#define PDS_CR_PDS_USB_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
#define PDS_CR_PDS_USB_GATE_CLK          PDS_CR_PDS_USB_GATE_CLK
#define PDS_CR_PDS_USB_GATE_CLK_POS      (23U)
#define PDS_CR_PDS_USB_GATE_CLK_LEN      (1U)
#define PDS_CR_PDS_USB_GATE_CLK_MSK      (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
#define PDS_CR_PDS_USB_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
#define PDS_CR_PDS_MISC_PWR_OFF          PDS_CR_PDS_MISC_PWR_OFF
#define PDS_CR_PDS_MISC_PWR_OFF_POS      (24U)
#define PDS_CR_PDS_MISC_PWR_OFF_LEN      (1U)
#define PDS_CR_PDS_MISC_PWR_OFF_MSK      (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
#define PDS_CR_PDS_MISC_PWR_OFF_UMSK     (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
#define PDS_CR_PDS_MISC_RESET            PDS_CR_PDS_MISC_RESET
#define PDS_CR_PDS_MISC_RESET_POS        (25U)
#define PDS_CR_PDS_MISC_RESET_LEN        (1U)
#define PDS_CR_PDS_MISC_RESET_MSK        (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
#define PDS_CR_PDS_MISC_RESET_UMSK       (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
#define PDS_CR_PDS_MISC_MEM_STBY         PDS_CR_PDS_MISC_MEM_STBY
#define PDS_CR_PDS_MISC_MEM_STBY_POS     (26U)
#define PDS_CR_PDS_MISC_MEM_STBY_LEN     (1U)
#define PDS_CR_PDS_MISC_MEM_STBY_MSK     (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
#define PDS_CR_PDS_MISC_MEM_STBY_UMSK    (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
#define PDS_CR_PDS_MISC_GATE_CLK         PDS_CR_PDS_MISC_GATE_CLK
#define PDS_CR_PDS_MISC_GATE_CLK_POS     (27U)
#define PDS_CR_PDS_MISC_GATE_CLK_LEN     (1U)
#define PDS_CR_PDS_MISC_GATE_CLK_MSK     (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
#define PDS_CR_PDS_MISC_GATE_CLK_UMSK    (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
#define PDS_CR_PDS_MISC_ANA_PWR_OFF      PDS_CR_PDS_MISC_ANA_PWR_OFF
#define PDS_CR_PDS_MISC_ANA_PWR_OFF_POS  (30U)
#define PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN  (1U)
#define PDS_CR_PDS_MISC_ANA_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS)
#define PDS_CR_PDS_MISC_ANA_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS))
#define PDS_CR_PDS_MISC_DIG_PWR_OFF      PDS_CR_PDS_MISC_DIG_PWR_OFF
#define PDS_CR_PDS_MISC_DIG_PWR_OFF_POS  (31U)
#define PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN  (1U)
#define PDS_CR_PDS_MISC_DIG_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS)
#define PDS_CR_PDS_MISC_DIG_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS))

/* 0x1C : pds_stat */
#define PDS_STAT_OFFSET           (0x1C)
#define PDS_RO_PDS_STATE          PDS_RO_PDS_STATE
#define PDS_RO_PDS_STATE_POS      (0U)
#define PDS_RO_PDS_STATE_LEN      (4U)
#define PDS_RO_PDS_STATE_MSK      (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
#define PDS_RO_PDS_STATE_UMSK     (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
#define PDS_RO_PDS_RF_STATE       PDS_RO_PDS_RF_STATE
#define PDS_RO_PDS_RF_STATE_POS   (8U)
#define PDS_RO_PDS_RF_STATE_LEN   (4U)
#define PDS_RO_PDS_RF_STATE_MSK   (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
#define PDS_RO_PDS_RF_STATE_UMSK  (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
#define PDS_RO_PDS_PLL_STATE      PDS_RO_PDS_PLL_STATE
#define PDS_RO_PDS_PLL_STATE_POS  (16U)
#define PDS_RO_PDS_PLL_STATE_LEN  (2U)
#define PDS_RO_PDS_PLL_STATE_MSK  (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)
#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS))

/* 0x20 : pds_ram1 */
#define PDS_RAM1_OFFSET           (0x20)
#define PDS_CR_PDS_RAM_RET1N      PDS_CR_PDS_RAM_RET1N
#define PDS_CR_PDS_RAM_RET1N_POS  (0U)
#define PDS_CR_PDS_RAM_RET1N_LEN  (4U)
#define PDS_CR_PDS_RAM_RET1N_MSK  (((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS)
#define PDS_CR_PDS_RAM_RET1N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS))
#define PDS_CR_PDS_RAM_RET2N      PDS_CR_PDS_RAM_RET2N
#define PDS_CR_PDS_RAM_RET2N_POS  (4U)
#define PDS_CR_PDS_RAM_RET2N_LEN  (4U)
#define PDS_CR_PDS_RAM_RET2N_MSK  (((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS)
#define PDS_CR_PDS_RAM_RET2N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS))
#define PDS_CR_PDS_RAM_PGEN       PDS_CR_PDS_RAM_PGEN
#define PDS_CR_PDS_RAM_PGEN_POS   (8U)
#define PDS_CR_PDS_RAM_PGEN_LEN   (4U)
#define PDS_CR_PDS_RAM_PGEN_MSK   (((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS)
#define PDS_CR_PDS_RAM_PGEN_UMSK  (~(((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS))

/* 0x30 : pds_gpio_set_pu_pd */
#define PDS_GPIO_SET_PU_PD_OFFSET     (0x30)
#define PDS_CR_PDS_GPIO_22_17_PD      PDS_CR_PDS_GPIO_22_17_PD
#define PDS_CR_PDS_GPIO_22_17_PD_POS  (0U)
#define PDS_CR_PDS_GPIO_22_17_PD_LEN  (6U)
#define PDS_CR_PDS_GPIO_22_17_PD_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS)
#define PDS_CR_PDS_GPIO_22_17_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS))
#define PDS_CR_PDS_GPIO_22_17_PU      PDS_CR_PDS_GPIO_22_17_PU
#define PDS_CR_PDS_GPIO_22_17_PU_POS  (8U)
#define PDS_CR_PDS_GPIO_22_17_PU_LEN  (6U)
#define PDS_CR_PDS_GPIO_22_17_PU_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS)
#define PDS_CR_PDS_GPIO_22_17_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS))
#define PDS_CR_PDS_GPIO_28_23_PD      PDS_CR_PDS_GPIO_28_23_PD
#define PDS_CR_PDS_GPIO_28_23_PD_POS  (16U)
#define PDS_CR_PDS_GPIO_28_23_PD_LEN  (6U)
#define PDS_CR_PDS_GPIO_28_23_PD_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS)
#define PDS_CR_PDS_GPIO_28_23_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS))
#define PDS_CR_PDS_GPIO_28_23_PU      PDS_CR_PDS_GPIO_28_23_PU
#define PDS_CR_PDS_GPIO_28_23_PU_POS  (24U)
#define PDS_CR_PDS_GPIO_28_23_PU_LEN  (6U)
#define PDS_CR_PDS_GPIO_28_23_PU_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS)
#define PDS_CR_PDS_GPIO_28_23_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS))

/* 0x40 : pds_gpio_int */
#define PDS_GPIO_INT_OFFSET      (0x40)
#define PDS_GPIO_INT_MASK        PDS_GPIO_INT_MASK
#define PDS_GPIO_INT_MASK_POS    (0U)
#define PDS_GPIO_INT_MASK_LEN    (1U)
#define PDS_GPIO_INT_MASK_MSK    (((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS)
#define PDS_GPIO_INT_MASK_UMSK   (~(((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS))
#define PDS_GPIO_INT_STAT        PDS_GPIO_INT_STAT
#define PDS_GPIO_INT_STAT_POS    (1U)
#define PDS_GPIO_INT_STAT_LEN    (1U)
#define PDS_GPIO_INT_STAT_MSK    (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
#define PDS_GPIO_INT_STAT_UMSK   (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
#define PDS_GPIO_INT_CLR         PDS_GPIO_INT_CLR
#define PDS_GPIO_INT_CLR_POS     (2U)
#define PDS_GPIO_INT_CLR_LEN     (1U)
#define PDS_GPIO_INT_CLR_MSK     (((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS)
#define PDS_GPIO_INT_CLR_UMSK    (~(((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS))
#define PDS_GPIO_INT_MODE        PDS_GPIO_INT_MODE
#define PDS_GPIO_INT_MODE_POS    (4U)
#define PDS_GPIO_INT_MODE_LEN    (3U)
#define PDS_GPIO_INT_MODE_MSK    (((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS)
#define PDS_GPIO_INT_MODE_UMSK   (~(((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS))
#define PDS_GPIO_INT_SELECT      PDS_GPIO_INT_SELECT
#define PDS_GPIO_INT_SELECT_POS  (8U)
#define PDS_GPIO_INT_SELECT_LEN  (3U)
#define PDS_GPIO_INT_SELECT_MSK  (((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS)
#define PDS_GPIO_INT_SELECT_UMSK (~(((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS))

/* 0x300 : rc32m_ctrl0 */
#define PDS_RC32M_CTRL0_OFFSET         (0x300)
#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
#define PDS_RC32M_CAL_DONE_POS         (0U)
#define PDS_RC32M_CAL_DONE_LEN         (1U)
#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
#define PDS_RC32M_RDY                  PDS_RC32M_RDY
#define PDS_RC32M_RDY_POS              (1U)
#define PDS_RC32M_RDY_LEN              (1U)
#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
#define PDS_RC32M_CAL_DIV_POS          (3U)
#define PDS_RC32M_CAL_DIV_LEN          (2U)
#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
#define PDS_RC32M_ALLOW_CAL_POS        (17U)
#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
#define PDS_RC32M_REFCLK_HALF_POS      (18U)
#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
#define PDS_RC32M_CAL_EN_POS           (20U)
#define PDS_RC32M_CAL_EN_LEN           (1U)
#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
#define PDS_RC32M_PD                   PDS_RC32M_PD
#define PDS_RC32M_PD_POS               (21U)
#define PDS_RC32M_PD_LEN               (1U)
#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))

/* 0x304 : rc32m_ctrl1 */
#define PDS_RC32M_CTRL1_OFFSET      (0x304)
#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
#define PDS_RC32M_TEST_EN_POS       (0U)
#define PDS_RC32M_TEST_EN_LEN       (1U)
#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
#define PDS_RC32M_SOFT_RST_POS      (1U)
#define PDS_RC32M_SOFT_RST_LEN      (1U)
#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
#define PDS_RC32M_CLK_INV_POS       (3U)
#define PDS_RC32M_CLK_INV_LEN       (1U)
#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
#define PDS_RC32M_RESERVED_POS      (24U)
#define PDS_RC32M_RESERVED_LEN      (8U)
#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))

/* 0x400 : pu_rst_clkpll */
#define PDS_PU_RST_CLKPLL_OFFSET      (0x400)
#define PDS_CLKPLL_SDM_RESET          PDS_CLKPLL_SDM_RESET
#define PDS_CLKPLL_SDM_RESET_POS      (0U)
#define PDS_CLKPLL_SDM_RESET_LEN      (1U)
#define PDS_CLKPLL_SDM_RESET_MSK      (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)
#define PDS_CLKPLL_SDM_RESET_UMSK     (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS))
#define PDS_CLKPLL_RESET_POSTDIV      PDS_CLKPLL_RESET_POSTDIV
#define PDS_CLKPLL_RESET_POSTDIV_POS  (1U)
#define PDS_CLKPLL_RESET_POSTDIV_LEN  (1U)
#define PDS_CLKPLL_RESET_POSTDIV_MSK  (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)
#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS))
#define PDS_CLKPLL_RESET_FBDV         PDS_CLKPLL_RESET_FBDV
#define PDS_CLKPLL_RESET_FBDV_POS     (2U)
#define PDS_CLKPLL_RESET_FBDV_LEN     (1U)
#define PDS_CLKPLL_RESET_FBDV_MSK     (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)
#define PDS_CLKPLL_RESET_FBDV_UMSK    (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS))
#define PDS_CLKPLL_RESET_REFDIV       PDS_CLKPLL_RESET_REFDIV
#define PDS_CLKPLL_RESET_REFDIV_POS   (3U)
#define PDS_CLKPLL_RESET_REFDIV_LEN   (1U)
#define PDS_CLKPLL_RESET_REFDIV_MSK   (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)
#define PDS_CLKPLL_RESET_REFDIV_UMSK  (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS))
#define PDS_CLKPLL_PU_POSTDIV         PDS_CLKPLL_PU_POSTDIV
#define PDS_CLKPLL_PU_POSTDIV_POS     (4U)
#define PDS_CLKPLL_PU_POSTDIV_LEN     (1U)
#define PDS_CLKPLL_PU_POSTDIV_MSK     (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)
#define PDS_CLKPLL_PU_POSTDIV_UMSK    (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS))
#define PDS_CLKPLL_PU_FBDV            PDS_CLKPLL_PU_FBDV
#define PDS_CLKPLL_PU_FBDV_POS        (5U)
#define PDS_CLKPLL_PU_FBDV_LEN        (1U)
#define PDS_CLKPLL_PU_FBDV_MSK        (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)
#define PDS_CLKPLL_PU_FBDV_UMSK       (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS))
#define PDS_CLKPLL_PU_CLAMP_OP        PDS_CLKPLL_PU_CLAMP_OP
#define PDS_CLKPLL_PU_CLAMP_OP_POS    (6U)
#define PDS_CLKPLL_PU_CLAMP_OP_LEN    (1U)
#define PDS_CLKPLL_PU_CLAMP_OP_MSK    (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)
#define PDS_CLKPLL_PU_CLAMP_OP_UMSK   (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS))
#define PDS_CLKPLL_PU_PFD             PDS_CLKPLL_PU_PFD
#define PDS_CLKPLL_PU_PFD_POS         (7U)
#define PDS_CLKPLL_PU_PFD_LEN         (1U)
#define PDS_CLKPLL_PU_PFD_MSK         (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)
#define PDS_CLKPLL_PU_PFD_UMSK        (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS))
#define PDS_CLKPLL_PU_CP              PDS_CLKPLL_PU_CP
#define PDS_CLKPLL_PU_CP_POS          (8U)
#define PDS_CLKPLL_PU_CP_LEN          (1U)
#define PDS_CLKPLL_PU_CP_MSK          (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)
#define PDS_CLKPLL_PU_CP_UMSK         (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS))
#define PDS_PU_CLKPLL_SFREG           PDS_PU_CLKPLL_SFREG
#define PDS_PU_CLKPLL_SFREG_POS       (9U)
#define PDS_PU_CLKPLL_SFREG_LEN       (1U)
#define PDS_PU_CLKPLL_SFREG_MSK       (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)
#define PDS_PU_CLKPLL_SFREG_UMSK      (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS))
#define PDS_PU_CLKPLL                 PDS_PU_CLKPLL
#define PDS_PU_CLKPLL_POS             (10U)
#define PDS_PU_CLKPLL_LEN             (1U)
#define PDS_PU_CLKPLL_MSK             (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)
#define PDS_PU_CLKPLL_UMSK            (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS))

/* 0x404 : clkpll_top_ctrl */
#define PDS_CLKPLL_TOP_CTRL_OFFSET     (0x404)
#define PDS_CLKPLL_POSTDIV             PDS_CLKPLL_POSTDIV
#define PDS_CLKPLL_POSTDIV_POS         (0U)
#define PDS_CLKPLL_POSTDIV_LEN         (7U)
#define PDS_CLKPLL_POSTDIV_MSK         (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)
#define PDS_CLKPLL_POSTDIV_UMSK        (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS))
#define PDS_CLKPLL_REFDIV_RATIO        PDS_CLKPLL_REFDIV_RATIO
#define PDS_CLKPLL_REFDIV_RATIO_POS    (8U)
#define PDS_CLKPLL_REFDIV_RATIO_LEN    (4U)
#define PDS_CLKPLL_REFDIV_RATIO_MSK    (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)
#define PDS_CLKPLL_REFDIV_RATIO_UMSK   (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS))
#define PDS_CLKPLL_XTAL_RC32M_SEL      PDS_CLKPLL_XTAL_RC32M_SEL
#define PDS_CLKPLL_XTAL_RC32M_SEL_POS  (12U)
#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN  (1U)
#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK  (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)
#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS))
#define PDS_CLKPLL_REFCLK_SEL          PDS_CLKPLL_REFCLK_SEL
#define PDS_CLKPLL_REFCLK_SEL_POS      (16U)
#define PDS_CLKPLL_REFCLK_SEL_LEN      (1U)
#define PDS_CLKPLL_REFCLK_SEL_MSK      (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)
#define PDS_CLKPLL_REFCLK_SEL_UMSK     (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS))
#define PDS_CLKPLL_VG11_SEL            PDS_CLKPLL_VG11_SEL
#define PDS_CLKPLL_VG11_SEL_POS        (20U)
#define PDS_CLKPLL_VG11_SEL_LEN        (2U)
#define PDS_CLKPLL_VG11_SEL_MSK        (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)
#define PDS_CLKPLL_VG11_SEL_UMSK       (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS))
#define PDS_CLKPLL_RESV                PDS_CLKPLL_RESV
#define PDS_CLKPLL_RESV_POS            (24U)
#define PDS_CLKPLL_RESV_LEN            (2U)
#define PDS_CLKPLL_RESV_MSK            (((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS)
#define PDS_CLKPLL_RESV_UMSK           (~(((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS))

/* 0x408 : clkpll_cp */
#define PDS_CLKPLL_CP_OFFSET          (0x408)
#define PDS_CLKPLL_SEL_CP_BIAS        PDS_CLKPLL_SEL_CP_BIAS
#define PDS_CLKPLL_SEL_CP_BIAS_POS    (0U)
#define PDS_CLKPLL_SEL_CP_BIAS_LEN    (1U)
#define PDS_CLKPLL_SEL_CP_BIAS_MSK    (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)
#define PDS_CLKPLL_SEL_CP_BIAS_UMSK   (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS))
#define PDS_CLKPLL_ICP_5U             PDS_CLKPLL_ICP_5U
#define PDS_CLKPLL_ICP_5U_POS         (4U)
#define PDS_CLKPLL_ICP_5U_LEN         (2U)
#define PDS_CLKPLL_ICP_5U_MSK         (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)
#define PDS_CLKPLL_ICP_5U_UMSK        (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS))
#define PDS_CLKPLL_ICP_1U             PDS_CLKPLL_ICP_1U
#define PDS_CLKPLL_ICP_1U_POS         (6U)
#define PDS_CLKPLL_ICP_1U_LEN         (2U)
#define PDS_CLKPLL_ICP_1U_MSK         (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)
#define PDS_CLKPLL_ICP_1U_UMSK        (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS))
#define PDS_CLKPLL_INT_FRAC_SW        PDS_CLKPLL_INT_FRAC_SW
#define PDS_CLKPLL_INT_FRAC_SW_POS    (8U)
#define PDS_CLKPLL_INT_FRAC_SW_LEN    (1U)
#define PDS_CLKPLL_INT_FRAC_SW_MSK    (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)
#define PDS_CLKPLL_INT_FRAC_SW_UMSK   (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS))
#define PDS_CLKPLL_CP_STARTUP_EN      PDS_CLKPLL_CP_STARTUP_EN
#define PDS_CLKPLL_CP_STARTUP_EN_POS  (9U)
#define PDS_CLKPLL_CP_STARTUP_EN_LEN  (1U)
#define PDS_CLKPLL_CP_STARTUP_EN_MSK  (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)
#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS))
#define PDS_CLKPLL_CP_OPAMP_EN        PDS_CLKPLL_CP_OPAMP_EN
#define PDS_CLKPLL_CP_OPAMP_EN_POS    (10U)
#define PDS_CLKPLL_CP_OPAMP_EN_LEN    (1U)
#define PDS_CLKPLL_CP_OPAMP_EN_MSK    (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)
#define PDS_CLKPLL_CP_OPAMP_EN_UMSK   (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS))

/* 0x40C : clkpll_rz */
#define PDS_CLKPLL_RZ_OFFSET     (0x40C)
#define PDS_CLKPLL_C4_EN         PDS_CLKPLL_C4_EN
#define PDS_CLKPLL_C4_EN_POS     (0U)
#define PDS_CLKPLL_C4_EN_LEN     (1U)
#define PDS_CLKPLL_C4_EN_MSK     (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)
#define PDS_CLKPLL_C4_EN_UMSK    (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS))
#define PDS_CLKPLL_R4            PDS_CLKPLL_R4
#define PDS_CLKPLL_R4_POS        (4U)
#define PDS_CLKPLL_R4_LEN        (2U)
#define PDS_CLKPLL_R4_MSK        (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)
#define PDS_CLKPLL_R4_UMSK       (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS))
#define PDS_CLKPLL_R4_SHORT      PDS_CLKPLL_R4_SHORT
#define PDS_CLKPLL_R4_SHORT_POS  (8U)
#define PDS_CLKPLL_R4_SHORT_LEN  (1U)
#define PDS_CLKPLL_R4_SHORT_MSK  (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)
#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS))
#define PDS_CLKPLL_C3            PDS_CLKPLL_C3
#define PDS_CLKPLL_C3_POS        (12U)
#define PDS_CLKPLL_C3_LEN        (2U)
#define PDS_CLKPLL_C3_MSK        (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)
#define PDS_CLKPLL_C3_UMSK       (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS))
#define PDS_CLKPLL_CZ            PDS_CLKPLL_CZ
#define PDS_CLKPLL_CZ_POS        (14U)
#define PDS_CLKPLL_CZ_LEN        (2U)
#define PDS_CLKPLL_CZ_MSK        (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)
#define PDS_CLKPLL_CZ_UMSK       (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS))
#define PDS_CLKPLL_RZ            PDS_CLKPLL_RZ
#define PDS_CLKPLL_RZ_POS        (16U)
#define PDS_CLKPLL_RZ_LEN        (3U)
#define PDS_CLKPLL_RZ_MSK        (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)
#define PDS_CLKPLL_RZ_UMSK       (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS))

/* 0x410 : clkpll_fbdv */
#define PDS_CLKPLL_FBDV_OFFSET         (0x410)
#define PDS_CLKPLL_SEL_SAMPLE_CLK      PDS_CLKPLL_SEL_SAMPLE_CLK
#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS  (0U)
#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN  (2U)
#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK  (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)
#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS))
#define PDS_CLKPLL_SEL_FB_CLK          PDS_CLKPLL_SEL_FB_CLK
#define PDS_CLKPLL_SEL_FB_CLK_POS      (2U)
#define PDS_CLKPLL_SEL_FB_CLK_LEN      (2U)
#define PDS_CLKPLL_SEL_FB_CLK_MSK      (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)
#define PDS_CLKPLL_SEL_FB_CLK_UMSK     (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS))

/* 0x414 : clkpll_vco */
#define PDS_CLKPLL_VCO_OFFSET     (0x414)
#define PDS_CLKPLL_VCO_SPEED      PDS_CLKPLL_VCO_SPEED
#define PDS_CLKPLL_VCO_SPEED_POS  (0U)
#define PDS_CLKPLL_VCO_SPEED_LEN  (3U)
#define PDS_CLKPLL_VCO_SPEED_MSK  (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)
#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS))
#define PDS_CLKPLL_SHRTR          PDS_CLKPLL_SHRTR
#define PDS_CLKPLL_SHRTR_POS      (3U)
#define PDS_CLKPLL_SHRTR_LEN      (1U)
#define PDS_CLKPLL_SHRTR_MSK      (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)
#define PDS_CLKPLL_SHRTR_UMSK     (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS))

/* 0x418 : clkpll_sdm */
#define PDS_CLKPLL_SDM_OFFSET      (0x418)
#define PDS_CLKPLL_SDMIN           PDS_CLKPLL_SDMIN
#define PDS_CLKPLL_SDMIN_POS       (0U)
#define PDS_CLKPLL_SDMIN_LEN       (24U)
#define PDS_CLKPLL_SDMIN_MSK       (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)
#define PDS_CLKPLL_SDMIN_UMSK      (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS))
#define PDS_CLKPLL_DITHER_SEL      PDS_CLKPLL_DITHER_SEL
#define PDS_CLKPLL_DITHER_SEL_POS  (24U)
#define PDS_CLKPLL_DITHER_SEL_LEN  (2U)
#define PDS_CLKPLL_DITHER_SEL_MSK  (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)
#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS))
#define PDS_CLKPLL_SDM_FLAG        PDS_CLKPLL_SDM_FLAG
#define PDS_CLKPLL_SDM_FLAG_POS    (28U)
#define PDS_CLKPLL_SDM_FLAG_LEN    (1U)
#define PDS_CLKPLL_SDM_FLAG_MSK    (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)
#define PDS_CLKPLL_SDM_FLAG_UMSK   (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS))
#define PDS_CLKPLL_SDM_BYPASS      PDS_CLKPLL_SDM_BYPASS
#define PDS_CLKPLL_SDM_BYPASS_POS  (29U)
#define PDS_CLKPLL_SDM_BYPASS_LEN  (1U)
#define PDS_CLKPLL_SDM_BYPASS_MSK  (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)
#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS))

/* 0x41C : clkpll_output_en */
#define PDS_CLKPLL_OUTPUT_EN_OFFSET  (0x41C)
#define PDS_CLKPLL_EN_480M           PDS_CLKPLL_EN_480M
#define PDS_CLKPLL_EN_480M_POS       (0U)
#define PDS_CLKPLL_EN_480M_LEN       (1U)
#define PDS_CLKPLL_EN_480M_MSK       (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)
#define PDS_CLKPLL_EN_480M_UMSK      (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS))
#define PDS_CLKPLL_EN_240M           PDS_CLKPLL_EN_240M
#define PDS_CLKPLL_EN_240M_POS       (1U)
#define PDS_CLKPLL_EN_240M_LEN       (1U)
#define PDS_CLKPLL_EN_240M_MSK       (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)
#define PDS_CLKPLL_EN_240M_UMSK      (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS))
#define PDS_CLKPLL_EN_192M           PDS_CLKPLL_EN_192M
#define PDS_CLKPLL_EN_192M_POS       (2U)
#define PDS_CLKPLL_EN_192M_LEN       (1U)
#define PDS_CLKPLL_EN_192M_MSK       (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)
#define PDS_CLKPLL_EN_192M_UMSK      (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS))
#define PDS_CLKPLL_EN_160M           PDS_CLKPLL_EN_160M
#define PDS_CLKPLL_EN_160M_POS       (3U)
#define PDS_CLKPLL_EN_160M_LEN       (1U)
#define PDS_CLKPLL_EN_160M_MSK       (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)
#define PDS_CLKPLL_EN_160M_UMSK      (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS))
#define PDS_CLKPLL_EN_120M           PDS_CLKPLL_EN_120M
#define PDS_CLKPLL_EN_120M_POS       (4U)
#define PDS_CLKPLL_EN_120M_LEN       (1U)
#define PDS_CLKPLL_EN_120M_MSK       (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)
#define PDS_CLKPLL_EN_120M_UMSK      (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS))
#define PDS_CLKPLL_EN_96M            PDS_CLKPLL_EN_96M
#define PDS_CLKPLL_EN_96M_POS        (5U)
#define PDS_CLKPLL_EN_96M_LEN        (1U)
#define PDS_CLKPLL_EN_96M_MSK        (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)
#define PDS_CLKPLL_EN_96M_UMSK       (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS))
#define PDS_CLKPLL_EN_80M            PDS_CLKPLL_EN_80M
#define PDS_CLKPLL_EN_80M_POS        (6U)
#define PDS_CLKPLL_EN_80M_LEN        (1U)
#define PDS_CLKPLL_EN_80M_MSK        (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)
#define PDS_CLKPLL_EN_80M_UMSK       (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS))
#define PDS_CLKPLL_EN_48M            PDS_CLKPLL_EN_48M
#define PDS_CLKPLL_EN_48M_POS        (7U)
#define PDS_CLKPLL_EN_48M_LEN        (1U)
#define PDS_CLKPLL_EN_48M_MSK        (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)
#define PDS_CLKPLL_EN_48M_UMSK       (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS))
#define PDS_CLKPLL_EN_32M            PDS_CLKPLL_EN_32M
#define PDS_CLKPLL_EN_32M_POS        (8U)
#define PDS_CLKPLL_EN_32M_LEN        (1U)
#define PDS_CLKPLL_EN_32M_MSK        (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)
#define PDS_CLKPLL_EN_32M_UMSK       (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS))
#define PDS_CLKPLL_EN_DIV2_480M      PDS_CLKPLL_EN_DIV2_480M
#define PDS_CLKPLL_EN_DIV2_480M_POS  (9U)
#define PDS_CLKPLL_EN_DIV2_480M_LEN  (1U)
#define PDS_CLKPLL_EN_DIV2_480M_MSK  (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)
#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS))

/* 0x420 : clkpll_test_enable */
#define PDS_CLKPLL_TEST_ENABLE_OFFSET    (0x420)
#define PDS_DTEN_CLKPLL_POSTDIV_CLK      PDS_DTEN_CLKPLL_POSTDIV_CLK
#define PDS_DTEN_CLKPLL_POSTDIV_CLK_POS  (0U)
#define PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN  (1U)
#define PDS_DTEN_CLKPLL_POSTDIV_CLK_MSK  (((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS)
#define PDS_DTEN_CLKPLL_POSTDIV_CLK_UMSK (~(((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS))
#define PDS_DTEN_CLK96M                  PDS_DTEN_CLK96M
#define PDS_DTEN_CLK96M_POS              (1U)
#define PDS_DTEN_CLK96M_LEN              (1U)
#define PDS_DTEN_CLK96M_MSK              (((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS)
#define PDS_DTEN_CLK96M_UMSK             (~(((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS))
#define PDS_DTEN_CLK32M                  PDS_DTEN_CLK32M
#define PDS_DTEN_CLK32M_POS              (2U)
#define PDS_DTEN_CLK32M_LEN              (1U)
#define PDS_DTEN_CLK32M_MSK              (((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS)
#define PDS_DTEN_CLK32M_UMSK             (~(((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS))
#define PDS_DTEN_CLKPLL_FSDM             PDS_DTEN_CLKPLL_FSDM
#define PDS_DTEN_CLKPLL_FSDM_POS         (3U)
#define PDS_DTEN_CLKPLL_FSDM_LEN         (1U)
#define PDS_DTEN_CLKPLL_FSDM_MSK         (((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS)
#define PDS_DTEN_CLKPLL_FSDM_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS))
#define PDS_DTEN_CLKPLL_FREF             PDS_DTEN_CLKPLL_FREF
#define PDS_DTEN_CLKPLL_FREF_POS         (4U)
#define PDS_DTEN_CLKPLL_FREF_LEN         (1U)
#define PDS_DTEN_CLKPLL_FREF_MSK         (((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS)
#define PDS_DTEN_CLKPLL_FREF_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS))
#define PDS_DTEN_CLKPLL_FIN              PDS_DTEN_CLKPLL_FIN
#define PDS_DTEN_CLKPLL_FIN_POS          (5U)
#define PDS_DTEN_CLKPLL_FIN_LEN          (1U)
#define PDS_DTEN_CLKPLL_FIN_MSK          (((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS)
#define PDS_DTEN_CLKPLL_FIN_UMSK         (~(((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS))
#define PDS_TEN_CLKPLL_SFREG             PDS_TEN_CLKPLL_SFREG
#define PDS_TEN_CLKPLL_SFREG_POS         (6U)
#define PDS_TEN_CLKPLL_SFREG_LEN         (1U)
#define PDS_TEN_CLKPLL_SFREG_MSK         (((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS)
#define PDS_TEN_CLKPLL_SFREG_UMSK        (~(((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS))
#define PDS_TEN_CLKPLL                   PDS_TEN_CLKPLL
#define PDS_TEN_CLKPLL_POS               (7U)
#define PDS_TEN_CLKPLL_LEN               (1U)
#define PDS_TEN_CLKPLL_MSK               (((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS)
#define PDS_TEN_CLKPLL_UMSK              (~(((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS))
#define PDS_CLKPLL_DC_TP_OUT_EN          PDS_CLKPLL_DC_TP_OUT_EN
#define PDS_CLKPLL_DC_TP_OUT_EN_POS      (8U)
#define PDS_CLKPLL_DC_TP_OUT_EN_LEN      (1U)
#define PDS_CLKPLL_DC_TP_OUT_EN_MSK      (((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS)
#define PDS_CLKPLL_DC_TP_OUT_EN_UMSK     (~(((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS))

struct pds_reg {
    /* 0x0 : PDS_CTL */
    union {
        struct
        {
            uint32_t pds_start_ps              : 1; /* [    0],        w1p,        0x0 */
            uint32_t cr_sleep_forever          : 1; /* [    1],        r/w,        0x0 */
            uint32_t cr_xtal_force_off         : 1; /* [    2],        r/w,        0x0 */
            uint32_t cr_wifi_pds_save_state    : 1; /* [    3],        r/w,        0x0 */
            uint32_t cr_pds_pd_dcdc18          : 1; /* [    4],        r/w,        0x0 */
            uint32_t cr_pds_pd_bg_sys          : 1; /* [    5],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [    6],        r/w,        0x0 */
            uint32_t cr_pds_ctrl_pu_flash      : 1; /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_gate_clk           : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_pds_mem_stby           : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_sw_pu_flash            : 1; /* [   10],        r/w,        0x1 */
            uint32_t cr_pds_iso_en             : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_pds_wait_xtal_rdy      : 1; /* [   12],        r/w,        0x0 */
            uint32_t cr_pds_pwr_off            : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_pds_pd_xtal            : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_pds_soc_enb_force_on   : 1; /* [   15],        r/w,        0x0 */
            uint32_t cr_pds_rst_soc_en         : 1; /* [   16],        r/w,        0x0 */
            uint32_t cr_pds_rc32m_off_dis      : 1; /* [   17],        r/w,        0x0 */
            uint32_t cr_pds_ldo_vsel_en        : 1; /* [   18],        r/w,        0x0 */
            uint32_t cr_pds_ram_lp_with_clk_en : 1; /* [   19],        r/w,        0x0 */
            uint32_t reserved_20               : 1; /* [   20],       rsvd,        0x0 */
            uint32_t cr_np_wfi_mask            : 1; /* [   21],        r/w,        0x0 */
            uint32_t cr_pds_pd_ldo11           : 1; /* [   22],        r/w,        0x0 */
            uint32_t cr_pds_force_ram_clk_en   : 1; /* [   23],        r/w,        0x0 */
            uint32_t cr_pds_ldo_vol            : 4; /* [27:24],        r/w,        0xa */
            uint32_t cr_pds_ctrl_rf            : 2; /* [29:28],        r/w,        0x1 */
            uint32_t cr_pds_ctrl_pll           : 2; /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL;

    /* 0x4 : PDS_TIME1 */
    union {
        struct
        {
            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
        } BF;
        uint32_t WORD;
    } PDS_TIME1;

    /* 0x8  reserved */
    uint8_t RESERVED0x8[4];

    /* 0xC : PDS_INT */
    union {
        struct
        {
            uint32_t ro_pds_wake_int          : 1; /* [    0],          r,        0x0 */
            uint32_t reserved_1               : 1; /* [    1],       rsvd,        0x0 */
            uint32_t ro_pds_rf_done_int       : 1; /* [    2],          r,        0x0 */
            uint32_t ro_pds_pll_done_int      : 1; /* [    3],          r,        0x0 */
            uint32_t pds_reset_event          : 3; /* [ 6: 4],          r,        0x0 */
            uint32_t pds_clr_reset_event      : 1; /* [    7],          w,        0x0 */
            uint32_t cr_pds_wake_int_mask     : 1; /* [    8],        r/w,        0x0 */
            uint32_t reserved_9               : 1; /* [    9],       rsvd,        0x0 */
            uint32_t cr_pds_rf_done_int_mask  : 1; /* [   10],        r/w,        0x0 */
            uint32_t cr_pds_pll_done_int_mask : 1; /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_14           : 3; /* [14:12],       rsvd,        0x0 */
            uint32_t cr_pds_int_clr           : 1; /* [   15],        r/w,        0x0 */
            uint32_t cr_pds_wakeup_src_en     : 8; /* [23:16],        r/w,       0xff */
            uint32_t ro_pds_wakeup_event      : 8; /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_INT;

    /* 0x10 : PDS_CTL2 */
    union {
        struct
        {
            uint32_t cr_pds_force_np_pwr_off   : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1                : 1;  /* [    1],       rsvd,        0x0 */
            uint32_t cr_pds_force_bz_pwr_off   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_pwr_off  : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_pds_force_np_iso_en    : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5                : 1;  /* [    5],       rsvd,        0x0 */
            uint32_t cr_pds_force_bz_iso_en    : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_iso_en   : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_force_np_pds_rst   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9                : 1;  /* [    9],       rsvd,        0x0 */
            uint32_t cr_pds_force_bz_pds_rst   : 1;  /* [   10],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_pds_rst  : 1;  /* [   11],        r/w,        0x0 */
            uint32_t cr_pds_force_np_mem_stby  : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reserved_13               : 1;  /* [   13],       rsvd,        0x0 */
            uint32_t cr_pds_force_bz_mem_stby  : 1;  /* [   14],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_mem_stby : 1;  /* [   15],        r/w,        0x0 */
            uint32_t cr_pds_force_np_gate_clk  : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17               : 1;  /* [   17],       rsvd,        0x0 */
            uint32_t cr_pds_force_bz_gate_clk  : 1;  /* [   18],        r/w,        0x0 */
            uint32_t cr_pds_force_usb_gate_clk : 1;  /* [   19],        r/w,        0x0 */
            uint32_t reserved_20_31            : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL2;

    /* 0x14 : PDS_CTL3 */
    union {
        struct
        {
            uint32_t reserved_0                 : 1; /* [    0],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_pwr_off  : 1; /* [    1],        r/w,        0x0 */
            uint32_t cr_pds_force_ble_pwr_off   : 1; /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_4               : 2; /* [ 4: 3],       rsvd,        0x0 */
            uint32_t cr_pds_force_ble_iso_en    : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6                 : 1; /* [    6],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_pds_rst  : 1; /* [    7],        r/w,        0x0 */
            uint32_t cr_pds_force_ble_pds_rst   : 1; /* [    8],        r/w,        0x0 */
            uint32_t reserved_9                 : 1; /* [    9],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_mem_stby : 1; /* [   10],        r/w,        0x0 */
            uint32_t cr_pds_force_ble_mem_stby  : 1; /* [   11],        r/w,        0x0 */
            uint32_t reserved_12                : 1; /* [   12],       rsvd,        0x0 */
            uint32_t cr_pds_force_misc_gate_clk : 1; /* [   13],        r/w,        0x0 */
            uint32_t cr_pds_force_ble_gate_clk  : 1; /* [   14],        r/w,        0x0 */
            uint32_t reserved_15_23             : 9; /* [23:15],       rsvd,        0x0 */
            uint32_t cr_pds_np_iso_en           : 1; /* [   24],        r/w,        0x1 */
            uint32_t reserved_25_26             : 2; /* [26:25],       rsvd,        0x0 */
            uint32_t cr_pds_bz_iso_en           : 1; /* [   27],        r/w,        0x1 */
            uint32_t cr_pds_ble_iso_en          : 1; /* [   28],        r/w,        0x1 */
            uint32_t cr_pds_usb_iso_en          : 1; /* [   29],        r/w,        0x1 */
            uint32_t cr_pds_misc_iso_en         : 1; /* [   30],        r/w,        0x1 */
            uint32_t reserved_31                : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } PDS_CTL3;

    /* 0x18 : PDS_CTL4 */
    union {
        struct
        {
            uint32_t cr_pds_np_pwr_off       : 1; /* [    0],        r/w,        0x1 */
            uint32_t cr_pds_np_reset         : 1; /* [    1],        r/w,        0x1 */
            uint32_t cr_pds_np_mem_stby      : 1; /* [    2],        r/w,        0x1 */
            uint32_t cr_pds_np_gate_clk      : 1; /* [    3],        r/w,        0x1 */
            uint32_t reserved_4_11           : 8; /* [11: 4],       rsvd,        0x0 */
            uint32_t cr_pds_bz_pwr_off       : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_pds_bz_reset         : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_pds_bz_mem_stby      : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_pds_bz_gate_clk      : 1; /* [   15],        r/w,        0x1 */
            uint32_t cr_pds_ble_pwr_off      : 1; /* [   16],        r/w,        0x1 */
            uint32_t cr_pds_ble_reset        : 1; /* [   17],        r/w,        0x1 */
            uint32_t cr_pds_ble_mem_stby     : 1; /* [   18],        r/w,        0x1 */
            uint32_t cr_pds_ble_gate_clk     : 1; /* [   19],        r/w,        0x1 */
            uint32_t cr_pds_usb_pwr_off      : 1; /* [   20],        r/w,        0x1 */
            uint32_t cr_pds_usb_reset        : 1; /* [   21],        r/w,        0x1 */
            uint32_t cr_pds_usb_mem_stby     : 1; /* [   22],        r/w,        0x1 */
            uint32_t cr_pds_usb_gate_clk     : 1; /* [   23],        r/w,        0x1 */
            uint32_t cr_pds_misc_pwr_off     : 1; /* [   24],        r/w,        0x1 */
            uint32_t cr_pds_misc_reset       : 1; /* [   25],        r/w,        0x1 */
            uint32_t cr_pds_misc_mem_stby    : 1; /* [   26],        r/w,        0x1 */
            uint32_t cr_pds_misc_gate_clk    : 1; /* [   27],        r/w,        0x1 */
            uint32_t reserved_28_29          : 2; /* [29:28],       rsvd,        0x0 */
            uint32_t cr_pds_misc_ana_pwr_off : 1; /* [   30],        r/w,        0x1 */
            uint32_t cr_pds_misc_dig_pwr_off : 1; /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } PDS_CTL4;

    /* 0x1C : pds_stat */
    union {
        struct
        {
            uint32_t ro_pds_state     : 4;  /* [ 3: 0],          r,        0x0 */
            uint32_t reserved_4_7     : 4;  /* [ 7: 4],       rsvd,        0x0 */
            uint32_t ro_pds_rf_state  : 4;  /* [11: 8],          r,        0x0 */
            uint32_t reserved_12_15   : 4;  /* [15:12],       rsvd,        0x0 */
            uint32_t ro_pds_pll_state : 2;  /* [17:16],          r,        0x0 */
            uint32_t reserved_18_31   : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_stat;

    /* 0x20 : pds_ram1 */
    union {
        struct
        {
            uint32_t cr_pds_ram_ret1n : 4;  /* [ 3: 0],        r/w,        0xf */
            uint32_t cr_pds_ram_ret2n : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t cr_pds_ram_pgen  : 4;  /* [11: 8],        r/w,        0x0 */
            uint32_t reserved_12_31   : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_ram1;

    /* 0x24  reserved */
    uint8_t RESERVED0x24[12];

    /* 0x30 : pds_gpio_set_pu_pd */
    union {
        struct
        {
            uint32_t cr_pds_gpio_22_17_pd : 6; /* [ 5: 0],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_22_17_pu : 6; /* [13: 8],        r/w,        0x0 */
            uint32_t reserved_14_15       : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_28_23_pd : 6; /* [21:16],        r/w,        0x0 */
            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t cr_pds_gpio_28_23_pu : 6; /* [29:24],        r/w,        0x0 */
            uint32_t reserved_30_31       : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_set_pu_pd;

    /* 0x34  reserved */
    uint8_t RESERVED0x34[12];

    /* 0x40 : pds_gpio_int */
    union {
        struct
        {
            uint32_t pds_gpio_int_mask   : 1;  /* [    0],        r/w,        0x1 */
            uint32_t pds_gpio_int_stat   : 1;  /* [    1],          r,        0x0 */
            uint32_t pds_gpio_int_clr    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3          : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t pds_gpio_int_mode   : 3;  /* [ 6: 4],        r/w,        0x0 */
            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t pds_gpio_int_select : 3;  /* [10: 8],        r/w,        0x0 */
            uint32_t reserved_11_31      : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pds_gpio_int;

    /* 0x44  reserved */
    uint8_t RESERVED0x44[700];

    /* 0x300 : rc32m_ctrl0 */
    union {
        struct
        {
            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rc32m_ctrl0;

    /* 0x304 : rc32m_ctrl1 */
    union {
        struct
        {
            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } rc32m_ctrl1;

    /* 0x308  reserved */
    uint8_t RESERVED0x308[248];

    /* 0x400 : pu_rst_clkpll */
    union {
        struct
        {
            uint32_t clkpll_sdm_reset     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t clkpll_reset_postdiv : 1;  /* [    1],        r/w,        0x0 */
            uint32_t clkpll_reset_fbdv    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t clkpll_reset_refdiv  : 1;  /* [    3],        r/w,        0x0 */
            uint32_t clkpll_pu_postdiv    : 1;  /* [    4],        r/w,        0x1 */
            uint32_t clkpll_pu_fbdv       : 1;  /* [    5],        r/w,        0x1 */
            uint32_t clkpll_pu_clamp_op   : 1;  /* [    6],        r/w,        0x1 */
            uint32_t clkpll_pu_pfd        : 1;  /* [    7],        r/w,        0x1 */
            uint32_t clkpll_pu_cp         : 1;  /* [    8],        r/w,        0x1 */
            uint32_t pu_clkpll_sfreg      : 1;  /* [    9],        r/w,        0x0 */
            uint32_t pu_clkpll            : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pu_rst_clkpll;

    /* 0x404 : clkpll_top_ctrl */
    union {
        struct
        {
            uint32_t clkpll_postdiv        : 7; /* [ 6: 0],        r/w,       0x14 */
            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
            uint32_t clkpll_refdiv_ratio   : 4; /* [11: 8],        r/w,        0x4 */
            uint32_t clkpll_xtal_rc32m_sel : 1; /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_15        : 3; /* [15:13],       rsvd,        0x0 */
            uint32_t clkpll_refclk_sel     : 1; /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_19        : 3; /* [19:17],       rsvd,        0x0 */
            uint32_t clkpll_vg11_sel       : 2; /* [21:20],        r/w,        0x1 */
            uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t clkpll_resv           : 2; /* [25:24],        r/w,        0x1 */
            uint32_t reserved_26_31        : 6; /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_top_ctrl;

    /* 0x408 : clkpll_cp */
    union {
        struct
        {
            uint32_t clkpll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t clkpll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x0 */
            uint32_t clkpll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x1 */
            uint32_t clkpll_int_frac_sw   : 1;  /* [    8],        r/w,        0x1 */
            uint32_t clkpll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
            uint32_t clkpll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_cp;

    /* 0x40C : clkpll_rz */
    union {
        struct
        {
            uint32_t clkpll_c4_en    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3    : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t clkpll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t clkpll_r4_short : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_11   : 3;  /* [11: 9],       rsvd,        0x0 */
            uint32_t clkpll_c3       : 2;  /* [13:12],        r/w,        0x2 */
            uint32_t clkpll_cz       : 2;  /* [15:14],        r/w,        0x2 */
            uint32_t clkpll_rz       : 3;  /* [18:16],        r/w,        0x5 */
            uint32_t reserved_19_31  : 13; /* [31:19],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_rz;

    /* 0x410 : clkpll_fbdv */
    union {
        struct
        {
            uint32_t clkpll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
            uint32_t clkpll_sel_fb_clk     : 2;  /* [ 3: 2],        r/w,        0x1 */
            uint32_t reserved_4_31         : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_fbdv;

    /* 0x414 : clkpll_vco */
    union {
        struct
        {
            uint32_t clkpll_vco_speed : 3;  /* [ 2: 0],        r/w,        0x6 */
            uint32_t clkpll_shrtr     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_vco;

    /* 0x418 : clkpll_sdm */
    union {
        struct
        {
            uint32_t clkpll_sdmin      : 24; /* [23: 0],        r/w,   0x600000 */
            uint32_t clkpll_dither_sel : 2;  /* [25:24],        r/w,        0x0 */
            uint32_t reserved_26_27    : 2;  /* [27:26],       rsvd,        0x0 */
            uint32_t clkpll_sdm_flag   : 1;  /* [   28],        r/w,        0x1 */
            uint32_t clkpll_sdm_bypass : 1;  /* [   29],        r/w,        0x0 */
            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_sdm;

    /* 0x41C : clkpll_output_en */
    union {
        struct
        {
            uint32_t clkpll_en_480m      : 1;  /* [    0],        r/w,        0x0 */
            uint32_t clkpll_en_240m      : 1;  /* [    1],        r/w,        0x0 */
            uint32_t clkpll_en_192m      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t clkpll_en_160m      : 1;  /* [    3],        r/w,        0x0 */
            uint32_t clkpll_en_120m      : 1;  /* [    4],        r/w,        0x0 */
            uint32_t clkpll_en_96m       : 1;  /* [    5],        r/w,        0x0 */
            uint32_t clkpll_en_80m       : 1;  /* [    6],        r/w,        0x0 */
            uint32_t clkpll_en_48m       : 1;  /* [    7],        r/w,        0x0 */
            uint32_t clkpll_en_32m       : 1;  /* [    8],        r/w,        0x1 */
            uint32_t clkpll_en_div2_480m : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10_31      : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_output_en;

    /* 0x420 : clkpll_test_enable */
    union {
        struct
        {
            uint32_t dten_clkpll_postdiv_clk : 1;  /* [    0],        r/w,        0x0 */
            uint32_t dten_clk96M             : 1;  /* [    1],        r/w,        0x0 */
            uint32_t dten_clk32M             : 1;  /* [    2],        r/w,        0x0 */
            uint32_t dten_clkpll_fsdm        : 1;  /* [    3],        r/w,        0x0 */
            uint32_t dten_clkpll_fref        : 1;  /* [    4],        r/w,        0x0 */
            uint32_t dten_clkpll_fin         : 1;  /* [    5],        r/w,        0x0 */
            uint32_t ten_clkpll_sfreg        : 1;  /* [    6],        r/w,        0x0 */
            uint32_t ten_clkpll              : 1;  /* [    7],        r/w,        0x0 */
            uint32_t clkpll_dc_tp_out_en     : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reserved_9_31           : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } clkpll_test_enable;
};

typedef volatile struct pds_reg pds_reg_t;

#endif /* __PDS_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/pwm_reg.h
================================================
/**
  ******************************************************************************
  * @file    pwm_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PWM_REG_H__
#define __PWM_REG_H__

#include "bl702.h"

/* 0x0 : pwm_int_config */
#define PWM_INT_CONFIG_OFFSET  (0x0)
#define PWM_INTERRUPT_STS      PWM_INTERRUPT_STS
#define PWM_INTERRUPT_STS_POS  (0U)
#define PWM_INTERRUPT_STS_LEN  (6U)
#define PWM_INTERRUPT_STS_MSK  (((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS)
#define PWM_INTERRUPT_STS_UMSK (~(((1U << PWM_INTERRUPT_STS_LEN) - 1) << PWM_INTERRUPT_STS_POS))
#define PWM_INT_CLEAR          PWM_INT_CLEAR
#define PWM_INT_CLEAR_POS      (8U)
#define PWM_INT_CLEAR_LEN      (6U)
#define PWM_INT_CLEAR_MSK      (((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS)
#define PWM_INT_CLEAR_UMSK     (~(((1U << PWM_INT_CLEAR_LEN) - 1) << PWM_INT_CLEAR_POS))

/* 0x20 : pwm0_clkdiv */
#define PWM0_CLKDIV_OFFSET (0x20)
#define PWM_CLK_DIV        PWM_CLK_DIV
#define PWM_CLK_DIV_POS    (0U)
#define PWM_CLK_DIV_LEN    (16U)
#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0x24 : pwm0_thre1 */
#define PWM0_THRE1_OFFSET (0x24)
#define PWM_THRE1         PWM_THRE1
#define PWM_THRE1_POS     (0U)
#define PWM_THRE1_LEN     (16U)
#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0x28 : pwm0_thre2 */
#define PWM0_THRE2_OFFSET (0x28)
#define PWM_THRE2         PWM_THRE2
#define PWM_THRE2_POS     (0U)
#define PWM_THRE2_LEN     (16U)
#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0x2C : pwm0_period */
#define PWM0_PERIOD_OFFSET (0x2C)
#define PWM_PERIOD         PWM_PERIOD
#define PWM_PERIOD_POS     (0U)
#define PWM_PERIOD_LEN     (16U)
#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0x30 : pwm0_config */
#define PWM0_CONFIG_OFFSET    (0x30)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0x34 : pwm0_interrupt */
#define PWM0_INTERRUPT_OFFSET   (0x34)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

/* 0x40 : pwm1_clkdiv */
#define PWM1_CLKDIV_OFFSET (0x40)
#define PWM_CLK_DIV        PWM_CLK_DIV
#define PWM_CLK_DIV_POS    (0U)
#define PWM_CLK_DIV_LEN    (16U)
#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0x44 : pwm1_thre1 */
#define PWM1_THRE1_OFFSET (0x44)
#define PWM_THRE1         PWM_THRE1
#define PWM_THRE1_POS     (0U)
#define PWM_THRE1_LEN     (16U)
#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0x48 : pwm1_thre2 */
#define PWM1_THRE2_OFFSET (0x48)
#define PWM_THRE2         PWM_THRE2
#define PWM_THRE2_POS     (0U)
#define PWM_THRE2_LEN     (16U)
#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0x4C : pwm1_period */
#define PWM1_PERIOD_OFFSET (0x4C)
#define PWM_PERIOD         PWM_PERIOD
#define PWM_PERIOD_POS     (0U)
#define PWM_PERIOD_LEN     (16U)
#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0x50 : pwm1_config */
#define PWM1_CONFIG_OFFSET    (0x50)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0x54 : pwm1_interrupt */
#define PWM1_INTERRUPT_OFFSET   (0x54)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

/* 0x60 : pwm2_clkdiv */
#define PWM2_CLKDIV_OFFSET (0x60)
#define PWM_CLK_DIV        PWM_CLK_DIV
#define PWM_CLK_DIV_POS    (0U)
#define PWM_CLK_DIV_LEN    (16U)
#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0x64 : pwm2_thre1 */
#define PWM2_THRE1_OFFSET (0x64)
#define PWM_THRE1         PWM_THRE1
#define PWM_THRE1_POS     (0U)
#define PWM_THRE1_LEN     (16U)
#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0x68 : pwm2_thre2 */
#define PWM2_THRE2_OFFSET (0x68)
#define PWM_THRE2         PWM_THRE2
#define PWM_THRE2_POS     (0U)
#define PWM_THRE2_LEN     (16U)
#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0x6C : pwm2_period */
#define PWM2_PERIOD_OFFSET (0x6C)
#define PWM_PERIOD         PWM_PERIOD
#define PWM_PERIOD_POS     (0U)
#define PWM_PERIOD_LEN     (16U)
#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0x70 : pwm2_config */
#define PWM2_CONFIG_OFFSET    (0x70)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0x74 : pwm2_interrupt */
#define PWM2_INTERRUPT_OFFSET   (0x74)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

/* 0x80 : pwm3_clkdiv */
#define PWM3_CLKDIV_OFFSET (0x80)
#define PWM_CLK_DIV        PWM_CLK_DIV
#define PWM_CLK_DIV_POS    (0U)
#define PWM_CLK_DIV_LEN    (16U)
#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0x84 : pwm3_thre1 */
#define PWM3_THRE1_OFFSET (0x84)
#define PWM_THRE1         PWM_THRE1
#define PWM_THRE1_POS     (0U)
#define PWM_THRE1_LEN     (16U)
#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0x88 : pwm3_thre2 */
#define PWM3_THRE2_OFFSET (0x88)
#define PWM_THRE2         PWM_THRE2
#define PWM_THRE2_POS     (0U)
#define PWM_THRE2_LEN     (16U)
#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0x8C : pwm3_period */
#define PWM3_PERIOD_OFFSET (0x8C)
#define PWM_PERIOD         PWM_PERIOD
#define PWM_PERIOD_POS     (0U)
#define PWM_PERIOD_LEN     (16U)
#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0x90 : pwm3_config */
#define PWM3_CONFIG_OFFSET    (0x90)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0x94 : pwm3_interrupt */
#define PWM3_INTERRUPT_OFFSET   (0x94)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

/* 0xA0 : pwm4_clkdiv */
#define PWM4_CLKDIV_OFFSET (0xA0)
#define PWM_CLK_DIV        PWM_CLK_DIV
#define PWM_CLK_DIV_POS    (0U)
#define PWM_CLK_DIV_LEN    (16U)
#define PWM_CLK_DIV_MSK    (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK   (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0xA4 : pwm4_thre1 */
#define PWM4_THRE1_OFFSET (0xA4)
#define PWM_THRE1         PWM_THRE1
#define PWM_THRE1_POS     (0U)
#define PWM_THRE1_LEN     (16U)
#define PWM_THRE1_MSK     (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK    (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0xA8 : pwm4_thre2 */
#define PWM4_THRE2_OFFSET (0xA8)
#define PWM_THRE2         PWM_THRE2
#define PWM_THRE2_POS     (0U)
#define PWM_THRE2_LEN     (16U)
#define PWM_THRE2_MSK     (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK    (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0xAC : pwm4_period */
#define PWM4_PERIOD_OFFSET (0xAC)
#define PWM_PERIOD         PWM_PERIOD
#define PWM_PERIOD_POS     (0U)
#define PWM_PERIOD_LEN     (16U)
#define PWM_PERIOD_MSK     (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK    (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0xB0 : pwm4_config */
#define PWM4_CONFIG_OFFSET    (0xB0)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0xB4 : pwm4_interrupt */
#define PWM4_INTERRUPT_OFFSET   (0xB4)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

struct pwm_reg {
    /* 0x0 : pwm_int_config */
    union {
        struct
        {
            uint32_t pwm_interrupt_sts : 6;  /* [ 5: 0],          r,        0x0 */
            uint32_t reserved_6_7      : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t pwm_int_clear     : 6;  /* [13: 8],          w,        0x0 */
            uint32_t reserved_14_31    : 18; /* [31:14],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_int_config;

    /* 0x4  reserved */
    uint8_t RESERVED0x4[28];

    /* 0x20 : pwm0_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_clkdiv;

    /* 0x24 : pwm0_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_thre1;

    /* 0x28 : pwm0_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_thre2;

    /* 0x2C : pwm0_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_period;

    /* 0x30 : pwm0_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_config;

    /* 0x34 : pwm0_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm0_interrupt;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[8];

    /* 0x40 : pwm1_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_clkdiv;

    /* 0x44 : pwm1_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_thre1;

    /* 0x48 : pwm1_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_thre2;

    /* 0x4C : pwm1_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_period;

    /* 0x50 : pwm1_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_config;

    /* 0x54 : pwm1_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm1_interrupt;

    /* 0x58  reserved */
    uint8_t RESERVED0x58[8];

    /* 0x60 : pwm2_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_clkdiv;

    /* 0x64 : pwm2_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_thre1;

    /* 0x68 : pwm2_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_thre2;

    /* 0x6C : pwm2_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_period;

    /* 0x70 : pwm2_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_config;

    /* 0x74 : pwm2_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm2_interrupt;

    /* 0x78  reserved */
    uint8_t RESERVED0x78[8];

    /* 0x80 : pwm3_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_clkdiv;

    /* 0x84 : pwm3_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_thre1;

    /* 0x88 : pwm3_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_thre2;

    /* 0x8C : pwm3_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_period;

    /* 0x90 : pwm3_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_config;

    /* 0x94 : pwm3_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm3_interrupt;

    /* 0x98  reserved */
    uint8_t RESERVED0x98[8];

    /* 0xA0 : pwm4_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_clkdiv;

    /* 0xA4 : pwm4_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_thre1;

    /* 0xA8 : pwm4_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_thre2;

    /* 0xAC : pwm4_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_period;

    /* 0xB0 : pwm4_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_config;

    /* 0xB4 : pwm4_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm4_interrupt;
};

typedef volatile struct pwm_reg pwm_reg_t;

/*Following is reg patch*/

/* 0x0 : pwm_clkdiv */
#define PWM_CLKDIV_OFFSET (0x0)
#define PWM_CLK_DIV       PWM_CLK_DIV
#define PWM_CLK_DIV_POS   (0U)
#define PWM_CLK_DIV_LEN   (16U)
#define PWM_CLK_DIV_MSK   (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK  (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS))

/* 0x4 : pwm_thre1 */
#define PWM_THRE1_OFFSET (0x4)
#define PWM_THRE1        PWM_THRE1
#define PWM_THRE1_POS    (0U)
#define PWM_THRE1_LEN    (16U)
#define PWM_THRE1_MSK    (((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS)
#define PWM_THRE1_UMSK   (~(((1U << PWM_THRE1_LEN) - 1) << PWM_THRE1_POS))

/* 0x8 : pwm_thre2 */
#define PWM_THRE2_OFFSET (0x8)
#define PWM_THRE2        PWM_THRE2
#define PWM_THRE2_POS    (0U)
#define PWM_THRE2_LEN    (16U)
#define PWM_THRE2_MSK    (((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS)
#define PWM_THRE2_UMSK   (~(((1U << PWM_THRE2_LEN) - 1) << PWM_THRE2_POS))

/* 0xc : pwm_period */
#define PWM_PERIOD_OFFSET (0xc)
#define PWM_PERIOD        PWM_PERIOD
#define PWM_PERIOD_POS    (0U)
#define PWM_PERIOD_LEN    (16U)
#define PWM_PERIOD_MSK    (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK   (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS))

/* 0x10 : pwm_config */
#define PWM_CONFIG_OFFSET     (0x10)
#define PWM_REG_CLK_SEL       PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS   (0U)
#define PWM_REG_CLK_SEL_LEN   (2U)
#define PWM_REG_CLK_SEL_MSK   (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK  (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV           PWM_OUT_INV
#define PWM_OUT_INV_POS       (2U)
#define PWM_OUT_INV_LEN       (1U)
#define PWM_OUT_INV_MSK       (((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK      (~(((1U << PWM_OUT_INV_LEN) - 1) << PWM_OUT_INV_POS))
#define PWM_STOP_MODE         PWM_STOP_MODE
#define PWM_STOP_MODE_POS     (3U)
#define PWM_STOP_MODE_LEN     (1U)
#define PWM_STOP_MODE_MSK     (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK    (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL      PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS  (4U)
#define PWM_SW_FORCE_VAL_LEN  (1U)
#define PWM_SW_FORCE_VAL_MSK  (((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U << PWM_SW_FORCE_VAL_LEN) - 1) << PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE           PWM_SW_MODE
#define PWM_SW_MODE_POS       (5U)
#define PWM_SW_MODE_LEN       (1U)
#define PWM_SW_MODE_MSK       (((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK      (~(((1U << PWM_SW_MODE_LEN) - 1) << PWM_SW_MODE_POS))
#define PWM_STOP_EN           PWM_STOP_EN
#define PWM_STOP_EN_POS       (6U)
#define PWM_STOP_EN_LEN       (1U)
#define PWM_STOP_EN_MSK       (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK      (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS))
#define PWM_STS_TOP           PWM_STS_TOP
#define PWM_STS_TOP_POS       (7U)
#define PWM_STS_TOP_LEN       (1U)
#define PWM_STS_TOP_MSK       (((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK      (~(((1U << PWM_STS_TOP_LEN) - 1) << PWM_STS_TOP_POS))

/* 0x14 : pwm_interrupt */
#define PWM_INTERRUPT_OFFSET    (0x14)
#define PWM_INT_PERIOD_CNT      PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS  (0U)
#define PWM_INT_PERIOD_CNT_LEN  (16U)
#define PWM_INT_PERIOD_CNT_MSK  (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE          PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS      (16U)
#define PWM_INT_ENABLE_LEN      (1U)
#define PWM_INT_ENABLE_MSK      (((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK     (~(((1U << PWM_INT_ENABLE_LEN) - 1) << PWM_INT_ENABLE_POS))

struct pwm_channel_reg {
    /* 0x0 : pwm_clkdiv */
    union {
        struct
        {
            uint32_t pwm_clk_div    : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_clkdiv;

    /* 0x4 : pwm_thre1 */
    union {
        struct
        {
            uint32_t pwm_thre1      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_thre1;

    /* 0x8 : pwm_thre2 */
    union {
        struct
        {
            uint32_t pwm_thre2      : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_thre2;

    /* 0xc : pwm_period */
    union {
        struct
        {
            uint32_t pwm_period     : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_period;

    /* 0x10 : pwm_config */
    union {
        struct
        {
            uint32_t reg_clk_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t pwm_out_inv      : 1;  /* [    2],        r/w,        0x0 */
            uint32_t pwm_stop_mode    : 1;  /* [    3],        r/w,        0x1 */
            uint32_t pwm_sw_force_val : 1;  /* [    4],        r/w,        0x0 */
            uint32_t pwm_sw_mode      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t pwm_stop_en      : 1;  /* [    6],        r/w,        0x0 */
            uint32_t pwm_sts_top      : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_config;

    /* 0x14 : pwm_interrupt */
    union {
        struct
        {
            uint32_t pwm_int_period_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t pwm_int_enable     : 1;  /* [   16],        r/w,        0x0 */
            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } pwm_interrupt;
};

typedef volatile struct pwm_channel_reg pwm_channel_reg_t;

#define PWM_CHANNEL_OFFSET 0x20

#endif /* __PWM_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/qdec_reg.h
================================================
/**
  ******************************************************************************
  * @file    qdec_reg.h
  * @version V1.2
  * @date    2020-04-08
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __QDEC_REG_H__
#define __QDEC_REG_H__

#include "bl702.h"

/* 0x0 : qdec0_ctrl0 */
#define QDEC0_CTRL0_OFFSET   (0x0)
#define QDEC_EN              QDEC_EN
#define QDEC_EN_POS          (0U)
#define QDEC_EN_LEN          (1U)
#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN          QDEC_LED_EN
#define QDEC_LED_EN_POS      (1U)
#define QDEC_LED_EN_LEN      (1U)
#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL         QDEC_LED_POL
#define QDEC_LED_POL_POS     (2U)
#define QDEC_LED_POL_LEN     (1U)
#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN          QDEC_DEG_EN
#define QDEC_DEG_EN_POS      (3U)
#define QDEC_DEG_EN_LEN      (1U)
#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT         QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS     (4U)
#define QDEC_DEG_CNT_LEN     (4U)
#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS  (8U)
#define QDEC_SPL_PERIOD_LEN  (4U)
#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS  (12U)
#define QDEC_RPT_PERIOD_LEN  (16U)
#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))

/* 0x4 : qdec0_ctrl1 */
#define QDEC0_CTRL1_OFFSET   (0x4)
#define QDEC_ACC_MODE        QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS    (0U)
#define QDEC_ACC_MODE_LEN    (1U)
#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE        QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS    (1U)
#define QDEC_SPL_MODE_LEN    (1U)
#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE        QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS    (2U)
#define QDEC_RPT_MODE_LEN    (1U)
#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS  (3U)
#define QDEC_INPUT_SWAP_LEN  (1U)
#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS  (16U)
#define QDEC_LED_PERIOD_LEN  (9U)
#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))

/* 0x8 : qdec0_value */
#define QDEC0_VALUE_OFFSET (0x8)
#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS  (0U)
#define QDEC_ACC1_VAL_LEN  (16U)
#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS  (16U)
#define QDEC_ACC2_VAL_LEN  (4U)
#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL       QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS   (28U)
#define QDEC_SPL_VAL_LEN   (2U)
#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))

/* 0x10 : qdec0_int_en */
#define QDEC0_INT_EN_OFFSET   (0x10)
#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS   (0U)
#define QDEC_RPT_RDY_EN_LEN   (1U)
#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS   (1U)
#define QDEC_SPL_RDY_EN_LEN   (1U)
#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS   (2U)
#define QDEC_DBL_RDY_EN_LEN   (1U)
#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS  (3U)
#define QDEC_OVERFLOW_EN_LEN  (1U)
#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))

/* 0x14 : qdec0_int_sts */
#define QDEC0_INT_STS_OFFSET   (0x14)
#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS   (0U)
#define QDEC_RPT_RDY_STS_LEN   (1U)
#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS   (1U)
#define QDEC_SPL_RDY_STS_LEN   (1U)
#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS   (2U)
#define QDEC_DBL_RDY_STS_LEN   (1U)
#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS  (3U)
#define QDEC_OVERFLOW_STS_LEN  (1U)
#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))

/* 0x18 : qdec0_int_clr */
#define QDEC0_INT_CLR_OFFSET   (0x18)
#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS   (0U)
#define QDEC_RPT_RDY_CLR_LEN   (1U)
#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS   (1U)
#define QDEC_SPL_RDY_CLR_LEN   (1U)
#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS   (2U)
#define QDEC_DBL_RDY_CLR_LEN   (1U)
#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS  (3U)
#define QDEC_OVERFLOW_CLR_LEN  (1U)
#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))

/* 0x40 : qdec1_ctrl0 */
#define QDEC1_CTRL0_OFFSET   (0x40)
#define QDEC_EN              QDEC_EN
#define QDEC_EN_POS          (0U)
#define QDEC_EN_LEN          (1U)
#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN          QDEC_LED_EN
#define QDEC_LED_EN_POS      (1U)
#define QDEC_LED_EN_LEN      (1U)
#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL         QDEC_LED_POL
#define QDEC_LED_POL_POS     (2U)
#define QDEC_LED_POL_LEN     (1U)
#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN          QDEC_DEG_EN
#define QDEC_DEG_EN_POS      (3U)
#define QDEC_DEG_EN_LEN      (1U)
#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT         QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS     (4U)
#define QDEC_DEG_CNT_LEN     (4U)
#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS  (8U)
#define QDEC_SPL_PERIOD_LEN  (4U)
#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS  (12U)
#define QDEC_RPT_PERIOD_LEN  (16U)
#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))

/* 0x44 : qdec1_ctrl1 */
#define QDEC1_CTRL1_OFFSET   (0x44)
#define QDEC_ACC_MODE        QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS    (0U)
#define QDEC_ACC_MODE_LEN    (1U)
#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE        QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS    (1U)
#define QDEC_SPL_MODE_LEN    (1U)
#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE        QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS    (2U)
#define QDEC_RPT_MODE_LEN    (1U)
#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS  (3U)
#define QDEC_INPUT_SWAP_LEN  (1U)
#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS  (16U)
#define QDEC_LED_PERIOD_LEN  (9U)
#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))

/* 0x48 : qdec1_value */
#define QDEC1_VALUE_OFFSET (0x48)
#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS  (0U)
#define QDEC_ACC1_VAL_LEN  (16U)
#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS  (16U)
#define QDEC_ACC2_VAL_LEN  (4U)
#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL       QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS   (28U)
#define QDEC_SPL_VAL_LEN   (2U)
#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))

/* 0x50 : qdec1_int_en */
#define QDEC1_INT_EN_OFFSET   (0x50)
#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS   (0U)
#define QDEC_RPT_RDY_EN_LEN   (1U)
#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS   (1U)
#define QDEC_SPL_RDY_EN_LEN   (1U)
#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS   (2U)
#define QDEC_DBL_RDY_EN_LEN   (1U)
#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS  (3U)
#define QDEC_OVERFLOW_EN_LEN  (1U)
#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))

/* 0x54 : qdec1_int_sts */
#define QDEC1_INT_STS_OFFSET   (0x54)
#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS   (0U)
#define QDEC_RPT_RDY_STS_LEN   (1U)
#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS   (1U)
#define QDEC_SPL_RDY_STS_LEN   (1U)
#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS   (2U)
#define QDEC_DBL_RDY_STS_LEN   (1U)
#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS  (3U)
#define QDEC_OVERFLOW_STS_LEN  (1U)
#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))

/* 0x58 : qdec1_int_clr */
#define QDEC1_INT_CLR_OFFSET   (0x58)
#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS   (0U)
#define QDEC_RPT_RDY_CLR_LEN   (1U)
#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS   (1U)
#define QDEC_SPL_RDY_CLR_LEN   (1U)
#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS   (2U)
#define QDEC_DBL_RDY_CLR_LEN   (1U)
#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS  (3U)
#define QDEC_OVERFLOW_CLR_LEN  (1U)
#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))

/* 0x80 : qdec2_ctrl0 */
#define QDEC2_CTRL0_OFFSET   (0x80)
#define QDEC_EN              QDEC_EN
#define QDEC_EN_POS          (0U)
#define QDEC_EN_LEN          (1U)
#define QDEC_EN_MSK          (((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS)
#define QDEC_EN_UMSK         (~(((1U << QDEC_EN_LEN) - 1) << QDEC_EN_POS))
#define QDEC_LED_EN          QDEC_LED_EN
#define QDEC_LED_EN_POS      (1U)
#define QDEC_LED_EN_LEN      (1U)
#define QDEC_LED_EN_MSK      (((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS)
#define QDEC_LED_EN_UMSK     (~(((1U << QDEC_LED_EN_LEN) - 1) << QDEC_LED_EN_POS))
#define QDEC_LED_POL         QDEC_LED_POL
#define QDEC_LED_POL_POS     (2U)
#define QDEC_LED_POL_LEN     (1U)
#define QDEC_LED_POL_MSK     (((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS)
#define QDEC_LED_POL_UMSK    (~(((1U << QDEC_LED_POL_LEN) - 1) << QDEC_LED_POL_POS))
#define QDEC_DEG_EN          QDEC_DEG_EN
#define QDEC_DEG_EN_POS      (3U)
#define QDEC_DEG_EN_LEN      (1U)
#define QDEC_DEG_EN_MSK      (((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS)
#define QDEC_DEG_EN_UMSK     (~(((1U << QDEC_DEG_EN_LEN) - 1) << QDEC_DEG_EN_POS))
#define QDEC_DEG_CNT         QDEC_DEG_CNT
#define QDEC_DEG_CNT_POS     (4U)
#define QDEC_DEG_CNT_LEN     (4U)
#define QDEC_DEG_CNT_MSK     (((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS)
#define QDEC_DEG_CNT_UMSK    (~(((1U << QDEC_DEG_CNT_LEN) - 1) << QDEC_DEG_CNT_POS))
#define QDEC_SPL_PERIOD      QDEC_SPL_PERIOD
#define QDEC_SPL_PERIOD_POS  (8U)
#define QDEC_SPL_PERIOD_LEN  (4U)
#define QDEC_SPL_PERIOD_MSK  (((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS)
#define QDEC_SPL_PERIOD_UMSK (~(((1U << QDEC_SPL_PERIOD_LEN) - 1) << QDEC_SPL_PERIOD_POS))
#define QDEC_RPT_PERIOD      QDEC_RPT_PERIOD
#define QDEC_RPT_PERIOD_POS  (12U)
#define QDEC_RPT_PERIOD_LEN  (16U)
#define QDEC_RPT_PERIOD_MSK  (((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS)
#define QDEC_RPT_PERIOD_UMSK (~(((1U << QDEC_RPT_PERIOD_LEN) - 1) << QDEC_RPT_PERIOD_POS))

/* 0x84 : qdec2_ctrl1 */
#define QDEC2_CTRL1_OFFSET   (0x84)
#define QDEC_ACC_MODE        QDEC_ACC_MODE
#define QDEC_ACC_MODE_POS    (0U)
#define QDEC_ACC_MODE_LEN    (1U)
#define QDEC_ACC_MODE_MSK    (((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS)
#define QDEC_ACC_MODE_UMSK   (~(((1U << QDEC_ACC_MODE_LEN) - 1) << QDEC_ACC_MODE_POS))
#define QDEC_SPL_MODE        QDEC_SPL_MODE
#define QDEC_SPL_MODE_POS    (1U)
#define QDEC_SPL_MODE_LEN    (1U)
#define QDEC_SPL_MODE_MSK    (((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS)
#define QDEC_SPL_MODE_UMSK   (~(((1U << QDEC_SPL_MODE_LEN) - 1) << QDEC_SPL_MODE_POS))
#define QDEC_RPT_MODE        QDEC_RPT_MODE
#define QDEC_RPT_MODE_POS    (2U)
#define QDEC_RPT_MODE_LEN    (1U)
#define QDEC_RPT_MODE_MSK    (((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS)
#define QDEC_RPT_MODE_UMSK   (~(((1U << QDEC_RPT_MODE_LEN) - 1) << QDEC_RPT_MODE_POS))
#define QDEC_INPUT_SWAP      QDEC_INPUT_SWAP
#define QDEC_INPUT_SWAP_POS  (3U)
#define QDEC_INPUT_SWAP_LEN  (1U)
#define QDEC_INPUT_SWAP_MSK  (((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS)
#define QDEC_INPUT_SWAP_UMSK (~(((1U << QDEC_INPUT_SWAP_LEN) - 1) << QDEC_INPUT_SWAP_POS))
#define QDEC_LED_PERIOD      QDEC_LED_PERIOD
#define QDEC_LED_PERIOD_POS  (16U)
#define QDEC_LED_PERIOD_LEN  (9U)
#define QDEC_LED_PERIOD_MSK  (((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS)
#define QDEC_LED_PERIOD_UMSK (~(((1U << QDEC_LED_PERIOD_LEN) - 1) << QDEC_LED_PERIOD_POS))

/* 0x88 : qdec2_value */
#define QDEC2_VALUE_OFFSET (0x88)
#define QDEC_ACC1_VAL      QDEC_ACC1_VAL
#define QDEC_ACC1_VAL_POS  (0U)
#define QDEC_ACC1_VAL_LEN  (16U)
#define QDEC_ACC1_VAL_MSK  (((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS)
#define QDEC_ACC1_VAL_UMSK (~(((1U << QDEC_ACC1_VAL_LEN) - 1) << QDEC_ACC1_VAL_POS))
#define QDEC_ACC2_VAL      QDEC_ACC2_VAL
#define QDEC_ACC2_VAL_POS  (16U)
#define QDEC_ACC2_VAL_LEN  (4U)
#define QDEC_ACC2_VAL_MSK  (((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS)
#define QDEC_ACC2_VAL_UMSK (~(((1U << QDEC_ACC2_VAL_LEN) - 1) << QDEC_ACC2_VAL_POS))
#define QDEC_SPL_VAL       QDEC_SPL_VAL
#define QDEC_SPL_VAL_POS   (28U)
#define QDEC_SPL_VAL_LEN   (2U)
#define QDEC_SPL_VAL_MSK   (((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS)
#define QDEC_SPL_VAL_UMSK  (~(((1U << QDEC_SPL_VAL_LEN) - 1) << QDEC_SPL_VAL_POS))

/* 0x90 : qdec2_int_en */
#define QDEC2_INT_EN_OFFSET   (0x90)
#define QDEC_RPT_RDY_EN       QDEC_RPT_RDY_EN
#define QDEC_RPT_RDY_EN_POS   (0U)
#define QDEC_RPT_RDY_EN_LEN   (1U)
#define QDEC_RPT_RDY_EN_MSK   (((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS)
#define QDEC_RPT_RDY_EN_UMSK  (~(((1U << QDEC_RPT_RDY_EN_LEN) - 1) << QDEC_RPT_RDY_EN_POS))
#define QDEC_SPL_RDY_EN       QDEC_SPL_RDY_EN
#define QDEC_SPL_RDY_EN_POS   (1U)
#define QDEC_SPL_RDY_EN_LEN   (1U)
#define QDEC_SPL_RDY_EN_MSK   (((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS)
#define QDEC_SPL_RDY_EN_UMSK  (~(((1U << QDEC_SPL_RDY_EN_LEN) - 1) << QDEC_SPL_RDY_EN_POS))
#define QDEC_DBL_RDY_EN       QDEC_DBL_RDY_EN
#define QDEC_DBL_RDY_EN_POS   (2U)
#define QDEC_DBL_RDY_EN_LEN   (1U)
#define QDEC_DBL_RDY_EN_MSK   (((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS)
#define QDEC_DBL_RDY_EN_UMSK  (~(((1U << QDEC_DBL_RDY_EN_LEN) - 1) << QDEC_DBL_RDY_EN_POS))
#define QDEC_OVERFLOW_EN      QDEC_OVERFLOW_EN
#define QDEC_OVERFLOW_EN_POS  (3U)
#define QDEC_OVERFLOW_EN_LEN  (1U)
#define QDEC_OVERFLOW_EN_MSK  (((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS)
#define QDEC_OVERFLOW_EN_UMSK (~(((1U << QDEC_OVERFLOW_EN_LEN) - 1) << QDEC_OVERFLOW_EN_POS))

/* 0x94 : qdec2_int_sts */
#define QDEC2_INT_STS_OFFSET   (0x94)
#define QDEC_RPT_RDY_STS       QDEC_RPT_RDY_STS
#define QDEC_RPT_RDY_STS_POS   (0U)
#define QDEC_RPT_RDY_STS_LEN   (1U)
#define QDEC_RPT_RDY_STS_MSK   (((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS)
#define QDEC_RPT_RDY_STS_UMSK  (~(((1U << QDEC_RPT_RDY_STS_LEN) - 1) << QDEC_RPT_RDY_STS_POS))
#define QDEC_SPL_RDY_STS       QDEC_SPL_RDY_STS
#define QDEC_SPL_RDY_STS_POS   (1U)
#define QDEC_SPL_RDY_STS_LEN   (1U)
#define QDEC_SPL_RDY_STS_MSK   (((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS)
#define QDEC_SPL_RDY_STS_UMSK  (~(((1U << QDEC_SPL_RDY_STS_LEN) - 1) << QDEC_SPL_RDY_STS_POS))
#define QDEC_DBL_RDY_STS       QDEC_DBL_RDY_STS
#define QDEC_DBL_RDY_STS_POS   (2U)
#define QDEC_DBL_RDY_STS_LEN   (1U)
#define QDEC_DBL_RDY_STS_MSK   (((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS)
#define QDEC_DBL_RDY_STS_UMSK  (~(((1U << QDEC_DBL_RDY_STS_LEN) - 1) << QDEC_DBL_RDY_STS_POS))
#define QDEC_OVERFLOW_STS      QDEC_OVERFLOW_STS
#define QDEC_OVERFLOW_STS_POS  (3U)
#define QDEC_OVERFLOW_STS_LEN  (1U)
#define QDEC_OVERFLOW_STS_MSK  (((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS)
#define QDEC_OVERFLOW_STS_UMSK (~(((1U << QDEC_OVERFLOW_STS_LEN) - 1) << QDEC_OVERFLOW_STS_POS))

/* 0x98 : qdec2_int_clr */
#define QDEC2_INT_CLR_OFFSET   (0x98)
#define QDEC_RPT_RDY_CLR       QDEC_RPT_RDY_CLR
#define QDEC_RPT_RDY_CLR_POS   (0U)
#define QDEC_RPT_RDY_CLR_LEN   (1U)
#define QDEC_RPT_RDY_CLR_MSK   (((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS)
#define QDEC_RPT_RDY_CLR_UMSK  (~(((1U << QDEC_RPT_RDY_CLR_LEN) - 1) << QDEC_RPT_RDY_CLR_POS))
#define QDEC_SPL_RDY_CLR       QDEC_SPL_RDY_CLR
#define QDEC_SPL_RDY_CLR_POS   (1U)
#define QDEC_SPL_RDY_CLR_LEN   (1U)
#define QDEC_SPL_RDY_CLR_MSK   (((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS)
#define QDEC_SPL_RDY_CLR_UMSK  (~(((1U << QDEC_SPL_RDY_CLR_LEN) - 1) << QDEC_SPL_RDY_CLR_POS))
#define QDEC_DBL_RDY_CLR       QDEC_DBL_RDY_CLR
#define QDEC_DBL_RDY_CLR_POS   (2U)
#define QDEC_DBL_RDY_CLR_LEN   (1U)
#define QDEC_DBL_RDY_CLR_MSK   (((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS)
#define QDEC_DBL_RDY_CLR_UMSK  (~(((1U << QDEC_DBL_RDY_CLR_LEN) - 1) << QDEC_DBL_RDY_CLR_POS))
#define QDEC_OVERFLOW_CLR      QDEC_OVERFLOW_CLR
#define QDEC_OVERFLOW_CLR_POS  (3U)
#define QDEC_OVERFLOW_CLR_LEN  (1U)
#define QDEC_OVERFLOW_CLR_MSK  (((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS)
#define QDEC_OVERFLOW_CLR_UMSK (~(((1U << QDEC_OVERFLOW_CLR_LEN) - 1) << QDEC_OVERFLOW_CLR_POS))

struct qdec_reg {
    /* 0x0 : qdec0_ctrl0 */
    union {
        struct
        {
            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_ctrl0;

    /* 0x4 : qdec0_ctrl1 */
    union {
        struct
        {
            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_ctrl1;

    /* 0x8 : qdec0_value */
    union {
        struct
        {
            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_value;

    /* 0xc  reserved */
    uint8_t RESERVED0xc[4];

    /* 0x10 : qdec0_int_en */
    union {
        struct
        {
            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_int_en;

    /* 0x14 : qdec0_int_sts */
    union {
        struct
        {
            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_int_sts;

    /* 0x18 : qdec0_int_clr */
    union {
        struct
        {
            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec0_int_clr;

    /* 0x1c  reserved */
    uint8_t RESERVED0x1c[36];

    /* 0x40 : qdec1_ctrl0 */
    union {
        struct
        {
            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_ctrl0;

    /* 0x44 : qdec1_ctrl1 */
    union {
        struct
        {
            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_ctrl1;

    /* 0x48 : qdec1_value */
    union {
        struct
        {
            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_value;

    /* 0x4c  reserved */
    uint8_t RESERVED0x4c[4];

    /* 0x50 : qdec1_int_en */
    union {
        struct
        {
            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_int_en;

    /* 0x54 : qdec1_int_sts */
    union {
        struct
        {
            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_int_sts;

    /* 0x58 : qdec1_int_clr */
    union {
        struct
        {
            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec1_int_clr;

    /* 0x5c  reserved */
    uint8_t RESERVED0x5c[36];

    /* 0x80 : qdec2_ctrl0 */
    union {
        struct
        {
            uint32_t qdec_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t led_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t led_pol        : 1;  /* [    2],        r/w,        0x1 */
            uint32_t deg_en         : 1;  /* [    3],        r/w,        0x0 */
            uint32_t deg_cnt        : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t spl_period     : 4;  /* [11: 8],        r/w,        0x2 */
            uint32_t rpt_period     : 16; /* [27:12],        r/w,        0xa */
            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_ctrl0;

    /* 0x84 : qdec2_ctrl1 */
    union {
        struct
        {
            uint32_t acc_mode       : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_mode       : 1;  /* [    1],        r/w,        0x0 */
            uint32_t rpt_mode       : 1;  /* [    2],        r/w,        0x0 */
            uint32_t input_swap     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_15  : 12; /* [15: 4],       rsvd,        0x0 */
            uint32_t led_period     : 9;  /* [24:16],        r/w,        0x0 */
            uint32_t reserved_25_31 : 7;  /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_ctrl1;

    /* 0x88 : qdec2_value */
    union {
        struct
        {
            uint32_t acc1_val       : 16; /* [15: 0],          r,        0x0 */
            uint32_t acc2_val       : 4;  /* [19:16],          r,        0x0 */
            uint32_t reserved_20_27 : 8;  /* [27:20],       rsvd,        0x0 */
            uint32_t spl_val        : 2;  /* [29:28],          r,        0x0 */
            uint32_t reserved_30_31 : 2;  /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_value;

    /* 0x8c  reserved */
    uint8_t RESERVED0x8c[4];

    /* 0x90 : qdec2_int_en */
    union {
        struct
        {
            uint32_t rpt_rdy_en    : 1;  /* [    0],        r/w,        0x1 */
            uint32_t spl_rdy_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t dbl_rdy_en    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t overflow_en   : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_int_en;

    /* 0x94 : qdec2_int_sts */
    union {
        struct
        {
            uint32_t rpt_rdy_sts   : 1;  /* [    0],          r,        0x0 */
            uint32_t spl_rdy_sts   : 1;  /* [    1],          r,        0x0 */
            uint32_t dbl_rdy_sts   : 1;  /* [    2],          r,        0x0 */
            uint32_t overflow_sts  : 1;  /* [    3],          r,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_int_sts;

    /* 0x98 : qdec2_int_clr */
    union {
        struct
        {
            uint32_t rpt_rdy_clr   : 1;  /* [    0],        w1c,        0x0 */
            uint32_t spl_rdy_clr   : 1;  /* [    1],        w1c,        0x0 */
            uint32_t dbl_rdy_clr   : 1;  /* [    2],        w1c,        0x0 */
            uint32_t overflow_clr  : 1;  /* [    3],        w1c,        0x0 */
            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } qdec2_int_clr;
};

typedef volatile struct qdec_reg qdec_reg_t;

#endif /* __QDEC_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_dbg_reg.h
================================================
/**
  ******************************************************************************
  * @file    sec_dbg_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __SEC_DBG_REG_H__
#define __SEC_DBG_REG_H__

#include "bl702.h"

/* 0x0 : sd_chip_id_low */
#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0)
#define SEC_DBG_SD_CHIP_ID_LOW        SEC_DBG_SD_CHIP_ID_LOW
#define SEC_DBG_SD_CHIP_ID_LOW_POS    (0U)
#define SEC_DBG_SD_CHIP_ID_LOW_LEN    (32U)
#define SEC_DBG_SD_CHIP_ID_LOW_MSK    (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)
#define SEC_DBG_SD_CHIP_ID_LOW_UMSK   (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS))

/* 0x4 : sd_chip_id_high */
#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4)
#define SEC_DBG_SD_CHIP_ID_HIGH        SEC_DBG_SD_CHIP_ID_HIGH
#define SEC_DBG_SD_CHIP_ID_HIGH_POS    (0U)
#define SEC_DBG_SD_CHIP_ID_HIGH_LEN    (32U)
#define SEC_DBG_SD_CHIP_ID_HIGH_MSK    (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)
#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK   (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS))

/* 0x8 : sd_wifi_mac_low */
#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8)
#define SEC_DBG_SD_WIFI_MAC_LOW        SEC_DBG_SD_WIFI_MAC_LOW
#define SEC_DBG_SD_WIFI_MAC_LOW_POS    (0U)
#define SEC_DBG_SD_WIFI_MAC_LOW_LEN    (32U)
#define SEC_DBG_SD_WIFI_MAC_LOW_MSK    (((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS)
#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK   (~(((1U << SEC_DBG_SD_WIFI_MAC_LOW_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_LOW_POS))

/* 0xC : sd_wifi_mac_high */
#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC)
#define SEC_DBG_SD_WIFI_MAC_HIGH        SEC_DBG_SD_WIFI_MAC_HIGH
#define SEC_DBG_SD_WIFI_MAC_HIGH_POS    (0U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN    (32U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK    (((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS)
#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK   (~(((1U << SEC_DBG_SD_WIFI_MAC_HIGH_LEN) - 1) << SEC_DBG_SD_WIFI_MAC_HIGH_POS))

/* 0x10 : sd_dbg_pwd_low */
#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10)
#define SEC_DBG_SD_DBG_PWD_LOW        SEC_DBG_SD_DBG_PWD_LOW
#define SEC_DBG_SD_DBG_PWD_LOW_POS    (0U)
#define SEC_DBG_SD_DBG_PWD_LOW_LEN    (32U)
#define SEC_DBG_SD_DBG_PWD_LOW_MSK    (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)
#define SEC_DBG_SD_DBG_PWD_LOW_UMSK   (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS))

/* 0x14 : sd_dbg_pwd_high */
#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14)
#define SEC_DBG_SD_DBG_PWD_HIGH        SEC_DBG_SD_DBG_PWD_HIGH
#define SEC_DBG_SD_DBG_PWD_HIGH_POS    (0U)
#define SEC_DBG_SD_DBG_PWD_HIGH_LEN    (32U)
#define SEC_DBG_SD_DBG_PWD_HIGH_MSK    (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)
#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK   (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS))

/* 0x18 : sd_status */
#define SEC_DBG_SD_STATUS_OFFSET        (0x18)
#define SEC_DBG_SD_DBG_PWD_BUSY         SEC_DBG_SD_DBG_PWD_BUSY
#define SEC_DBG_SD_DBG_PWD_BUSY_POS     (0U)
#define SEC_DBG_SD_DBG_PWD_BUSY_LEN     (1U)
#define SEC_DBG_SD_DBG_PWD_BUSY_MSK     (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)
#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK    (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS))
#define SEC_DBG_SD_DBG_PWD_TRIG         SEC_DBG_SD_DBG_PWD_TRIG
#define SEC_DBG_SD_DBG_PWD_TRIG_POS     (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_LEN     (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_MSK     (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)
#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK    (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS))
#define SEC_DBG_SD_DBG_CCI_READ_EN      SEC_DBG_SD_DBG_CCI_READ_EN
#define SEC_DBG_SD_DBG_CCI_READ_EN_POS  (2U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN  (1U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK  (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)
#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS))
#define SEC_DBG_SD_DBG_CCI_CLK_SEL      SEC_DBG_SD_DBG_CCI_CLK_SEL
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS  (3U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN  (1U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK  (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS))
#define SEC_DBG_SD_DBG_PWD_CNT          SEC_DBG_SD_DBG_PWD_CNT
#define SEC_DBG_SD_DBG_PWD_CNT_POS      (4U)
#define SEC_DBG_SD_DBG_PWD_CNT_LEN      (20U)
#define SEC_DBG_SD_DBG_PWD_CNT_MSK      (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)
#define SEC_DBG_SD_DBG_PWD_CNT_UMSK     (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS))
#define SEC_DBG_SD_DBG_MODE             SEC_DBG_SD_DBG_MODE
#define SEC_DBG_SD_DBG_MODE_POS         (24U)
#define SEC_DBG_SD_DBG_MODE_LEN         (4U)
#define SEC_DBG_SD_DBG_MODE_MSK         (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)
#define SEC_DBG_SD_DBG_MODE_UMSK        (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS))
#define SEC_DBG_SD_DBG_ENA              SEC_DBG_SD_DBG_ENA
#define SEC_DBG_SD_DBG_ENA_POS          (28U)
#define SEC_DBG_SD_DBG_ENA_LEN          (4U)
#define SEC_DBG_SD_DBG_ENA_MSK          (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)
#define SEC_DBG_SD_DBG_ENA_UMSK         (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS))

/* 0x1C : sd_dbg_reserved */
#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C)
#define SEC_DBG_SD_DBG_RESERVED        SEC_DBG_SD_DBG_RESERVED
#define SEC_DBG_SD_DBG_RESERVED_POS    (0U)
#define SEC_DBG_SD_DBG_RESERVED_LEN    (32U)
#define SEC_DBG_SD_DBG_RESERVED_MSK    (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)
#define SEC_DBG_SD_DBG_RESERVED_UMSK   (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS))

struct sec_dbg_reg {
    /* 0x0 : sd_chip_id_low */
    union {
        struct
        {
            uint32_t sd_chip_id_low : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_chip_id_low;

    /* 0x4 : sd_chip_id_high */
    union {
        struct
        {
            uint32_t sd_chip_id_high : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_chip_id_high;

    /* 0x8 : sd_wifi_mac_low */
    union {
        struct
        {
            uint32_t sd_wifi_mac_low : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_wifi_mac_low;

    /* 0xC : sd_wifi_mac_high */
    union {
        struct
        {
            uint32_t sd_wifi_mac_high : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_wifi_mac_high;

    /* 0x10 : sd_dbg_pwd_low */
    union {
        struct
        {
            uint32_t sd_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_dbg_pwd_low;

    /* 0x14 : sd_dbg_pwd_high */
    union {
        struct
        {
            uint32_t sd_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_dbg_pwd_high;

    /* 0x18 : sd_status */
    union {
        struct
        {
            uint32_t sd_dbg_pwd_busy    : 1;  /* [    0],          r,        0x0 */
            uint32_t sd_dbg_pwd_trig    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t sd_dbg_cci_read_en : 1;  /* [    2],        r/w,        0x0 */
            uint32_t sd_dbg_cci_clk_sel : 1;  /* [    3],        r/w,        0x0 */
            uint32_t sd_dbg_pwd_cnt     : 20; /* [23: 4],          r,        0x0 */
            uint32_t sd_dbg_mode        : 4;  /* [27:24],          r,        0x0 */
            uint32_t sd_dbg_ena         : 4;  /* [31:28],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sd_status;

    /* 0x1C : sd_dbg_reserved */
    union {
        struct
        {
            uint32_t sd_dbg_reserved : 32; /* [31: 0],        r/w,     0xffff */
        } BF;
        uint32_t WORD;
    } sd_dbg_reserved;
};

typedef volatile struct sec_dbg_reg sec_dbg_reg_t;

#endif /* __SEC_DBG_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sec_eng_reg.h
================================================
/**
  ******************************************************************************
  * @file    sec_eng_reg.h
  * @version V1.2
  * @date    2020-04-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __SEC_ENG_REG_H__
#define __SEC_ENG_REG_H__

#include "bl702.h"

/* 0x0 : se_sha_0_ctrl */
#define SEC_ENG_SE_SHA_0_CTRL_OFFSET     (0x0)
#define SEC_ENG_SE_SHA_0_BUSY            SEC_ENG_SE_SHA_0_BUSY
#define SEC_ENG_SE_SHA_0_BUSY_POS        (0U)
#define SEC_ENG_SE_SHA_0_BUSY_LEN        (1U)
#define SEC_ENG_SE_SHA_0_BUSY_MSK        (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)
#define SEC_ENG_SE_SHA_0_BUSY_UMSK       (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS))
#define SEC_ENG_SE_SHA_0_TRIG_1T         SEC_ENG_SE_SHA_0_TRIG_1T
#define SEC_ENG_SE_SHA_0_TRIG_1T_POS     (1U)
#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN     (1U)
#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK     (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)
#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS))
#define SEC_ENG_SE_SHA_0_MODE            SEC_ENG_SE_SHA_0_MODE
#define SEC_ENG_SE_SHA_0_MODE_POS        (2U)
#define SEC_ENG_SE_SHA_0_MODE_LEN        (3U)
#define SEC_ENG_SE_SHA_0_MODE_MSK        (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)
#define SEC_ENG_SE_SHA_0_MODE_UMSK       (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS))
#define SEC_ENG_SE_SHA_0_EN              SEC_ENG_SE_SHA_0_EN
#define SEC_ENG_SE_SHA_0_EN_POS          (5U)
#define SEC_ENG_SE_SHA_0_EN_LEN          (1U)
#define SEC_ENG_SE_SHA_0_EN_MSK          (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)
#define SEC_ENG_SE_SHA_0_EN_UMSK         (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS))
#define SEC_ENG_SE_SHA_0_HASH_SEL        SEC_ENG_SE_SHA_0_HASH_SEL
#define SEC_ENG_SE_SHA_0_HASH_SEL_POS    (6U)
#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN    (1U)
#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)
#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS))
#define SEC_ENG_SE_SHA_0_INT             SEC_ENG_SE_SHA_0_INT
#define SEC_ENG_SE_SHA_0_INT_POS         (8U)
#define SEC_ENG_SE_SHA_0_INT_LEN         (1U)
#define SEC_ENG_SE_SHA_0_INT_MSK         (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)
#define SEC_ENG_SE_SHA_0_INT_UMSK        (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS))
#define SEC_ENG_SE_SHA_0_INT_CLR_1T      SEC_ENG_SE_SHA_0_INT_CLR_1T
#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS  (9U)
#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN  (1U)
#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)
#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS))
#define SEC_ENG_SE_SHA_0_INT_SET_1T      SEC_ENG_SE_SHA_0_INT_SET_1T
#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS  (10U)
#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN  (1U)
#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)
#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS))
#define SEC_ENG_SE_SHA_0_INT_MASK        SEC_ENG_SE_SHA_0_INT_MASK
#define SEC_ENG_SE_SHA_0_INT_MASK_POS    (11U)
#define SEC_ENG_SE_SHA_0_INT_MASK_LEN    (1U)
#define SEC_ENG_SE_SHA_0_INT_MASK_MSK    (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)
#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS))
#define SEC_ENG_SE_SHA_0_LINK_MODE       SEC_ENG_SE_SHA_0_LINK_MODE
#define SEC_ENG_SE_SHA_0_LINK_MODE_POS   (15U)
#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN   (1U)
#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK   (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)
#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK  (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS))
#define SEC_ENG_SE_SHA_0_MSG_LEN         SEC_ENG_SE_SHA_0_MSG_LEN
#define SEC_ENG_SE_SHA_0_MSG_LEN_POS     (16U)
#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN     (16U)
#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK     (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)
#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS))

/* 0x4 : se_sha_0_msa */
#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4)
#define SEC_ENG_SE_SHA_0_MSA        SEC_ENG_SE_SHA_0_MSA
#define SEC_ENG_SE_SHA_0_MSA_POS    (0U)
#define SEC_ENG_SE_SHA_0_MSA_LEN    (32U)
#define SEC_ENG_SE_SHA_0_MSA_MSK    (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)
#define SEC_ENG_SE_SHA_0_MSA_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS))

/* 0x8 : se_sha_0_status */
#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8)
#define SEC_ENG_SE_SHA_0_STATUS        SEC_ENG_SE_SHA_0_STATUS
#define SEC_ENG_SE_SHA_0_STATUS_POS    (0U)
#define SEC_ENG_SE_SHA_0_STATUS_LEN    (32U)
#define SEC_ENG_SE_SHA_0_STATUS_MSK    (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)
#define SEC_ENG_SE_SHA_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS))

/* 0xC : se_sha_0_endian */
#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET    (0xC)
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN      SEC_ENG_SE_SHA_0_DOUT_ENDIAN
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS  (0U)
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN  (1U)
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)
#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS))

/* 0x10 : se_sha_0_hash_l_0 */
#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10)
#define SEC_ENG_SE_SHA_0_HASH_L_0        SEC_ENG_SE_SHA_0_HASH_L_0
#define SEC_ENG_SE_SHA_0_HASH_L_0_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS))

/* 0x14 : se_sha_0_hash_l_1 */
#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14)
#define SEC_ENG_SE_SHA_0_HASH_L_1        SEC_ENG_SE_SHA_0_HASH_L_1
#define SEC_ENG_SE_SHA_0_HASH_L_1_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS))

/* 0x18 : se_sha_0_hash_l_2 */
#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18)
#define SEC_ENG_SE_SHA_0_HASH_L_2        SEC_ENG_SE_SHA_0_HASH_L_2
#define SEC_ENG_SE_SHA_0_HASH_L_2_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS))

/* 0x1C : se_sha_0_hash_l_3 */
#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C)
#define SEC_ENG_SE_SHA_0_HASH_L_3        SEC_ENG_SE_SHA_0_HASH_L_3
#define SEC_ENG_SE_SHA_0_HASH_L_3_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS))

/* 0x20 : se_sha_0_hash_l_4 */
#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20)
#define SEC_ENG_SE_SHA_0_HASH_L_4        SEC_ENG_SE_SHA_0_HASH_L_4
#define SEC_ENG_SE_SHA_0_HASH_L_4_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS))

/* 0x24 : se_sha_0_hash_l_5 */
#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24)
#define SEC_ENG_SE_SHA_0_HASH_L_5        SEC_ENG_SE_SHA_0_HASH_L_5
#define SEC_ENG_SE_SHA_0_HASH_L_5_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS))

/* 0x28 : se_sha_0_hash_l_6 */
#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28)
#define SEC_ENG_SE_SHA_0_HASH_L_6        SEC_ENG_SE_SHA_0_HASH_L_6
#define SEC_ENG_SE_SHA_0_HASH_L_6_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS))

/* 0x2C : se_sha_0_hash_l_7 */
#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C)
#define SEC_ENG_SE_SHA_0_HASH_L_7        SEC_ENG_SE_SHA_0_HASH_L_7
#define SEC_ENG_SE_SHA_0_HASH_L_7_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)
#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS))

/* 0x30 : se_sha_0_hash_h_0 */
#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30)
#define SEC_ENG_SE_SHA_0_HASH_H_0        SEC_ENG_SE_SHA_0_HASH_H_0
#define SEC_ENG_SE_SHA_0_HASH_H_0_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS))

/* 0x34 : se_sha_0_hash_h_1 */
#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34)
#define SEC_ENG_SE_SHA_0_HASH_H_1        SEC_ENG_SE_SHA_0_HASH_H_1
#define SEC_ENG_SE_SHA_0_HASH_H_1_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS))

/* 0x38 : se_sha_0_hash_h_2 */
#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38)
#define SEC_ENG_SE_SHA_0_HASH_H_2        SEC_ENG_SE_SHA_0_HASH_H_2
#define SEC_ENG_SE_SHA_0_HASH_H_2_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS))

/* 0x3C : se_sha_0_hash_h_3 */
#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C)
#define SEC_ENG_SE_SHA_0_HASH_H_3        SEC_ENG_SE_SHA_0_HASH_H_3
#define SEC_ENG_SE_SHA_0_HASH_H_3_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS))

/* 0x40 : se_sha_0_hash_h_4 */
#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40)
#define SEC_ENG_SE_SHA_0_HASH_H_4        SEC_ENG_SE_SHA_0_HASH_H_4
#define SEC_ENG_SE_SHA_0_HASH_H_4_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS))

/* 0x44 : se_sha_0_hash_h_5 */
#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44)
#define SEC_ENG_SE_SHA_0_HASH_H_5        SEC_ENG_SE_SHA_0_HASH_H_5
#define SEC_ENG_SE_SHA_0_HASH_H_5_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS))

/* 0x48 : se_sha_0_hash_h_6 */
#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48)
#define SEC_ENG_SE_SHA_0_HASH_H_6        SEC_ENG_SE_SHA_0_HASH_H_6
#define SEC_ENG_SE_SHA_0_HASH_H_6_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS))

/* 0x4C : se_sha_0_hash_h_7 */
#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C)
#define SEC_ENG_SE_SHA_0_HASH_H_7        SEC_ENG_SE_SHA_0_HASH_H_7
#define SEC_ENG_SE_SHA_0_HASH_H_7_POS    (0U)
#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN    (32U)
#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK    (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)
#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS))

/* 0x50 : se_sha_0_link */
#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50)
#define SEC_ENG_SE_SHA_0_LCA         SEC_ENG_SE_SHA_0_LCA
#define SEC_ENG_SE_SHA_0_LCA_POS     (0U)
#define SEC_ENG_SE_SHA_0_LCA_LEN     (32U)
#define SEC_ENG_SE_SHA_0_LCA_MSK     (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)
#define SEC_ENG_SE_SHA_0_LCA_UMSK    (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS))

/* 0xFC : se_sha_0_ctrl_prot */
#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC)
#define SEC_ENG_SE_SHA_PROT_EN            SEC_ENG_SE_SHA_PROT_EN
#define SEC_ENG_SE_SHA_PROT_EN_POS        (0U)
#define SEC_ENG_SE_SHA_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_SHA_PROT_EN_MSK        (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)
#define SEC_ENG_SE_SHA_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS))
#define SEC_ENG_SE_SHA_ID0_EN             SEC_ENG_SE_SHA_ID0_EN
#define SEC_ENG_SE_SHA_ID0_EN_POS         (1U)
#define SEC_ENG_SE_SHA_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_SHA_ID0_EN_MSK         (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)
#define SEC_ENG_SE_SHA_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS))
#define SEC_ENG_SE_SHA_ID1_EN             SEC_ENG_SE_SHA_ID1_EN
#define SEC_ENG_SE_SHA_ID1_EN_POS         (2U)
#define SEC_ENG_SE_SHA_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_SHA_ID1_EN_MSK         (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)
#define SEC_ENG_SE_SHA_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS))

/* 0x100 : se_aes_0_ctrl */
#define SEC_ENG_SE_AES_0_CTRL_OFFSET      (0x100)
#define SEC_ENG_SE_AES_0_BUSY             SEC_ENG_SE_AES_0_BUSY
#define SEC_ENG_SE_AES_0_BUSY_POS         (0U)
#define SEC_ENG_SE_AES_0_BUSY_LEN         (1U)
#define SEC_ENG_SE_AES_0_BUSY_MSK         (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)
#define SEC_ENG_SE_AES_0_BUSY_UMSK        (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS))
#define SEC_ENG_SE_AES_0_TRIG_1T          SEC_ENG_SE_AES_0_TRIG_1T
#define SEC_ENG_SE_AES_0_TRIG_1T_POS      (1U)
#define SEC_ENG_SE_AES_0_TRIG_1T_LEN      (1U)
#define SEC_ENG_SE_AES_0_TRIG_1T_MSK      (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)
#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK     (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS))
#define SEC_ENG_SE_AES_0_EN               SEC_ENG_SE_AES_0_EN
#define SEC_ENG_SE_AES_0_EN_POS           (2U)
#define SEC_ENG_SE_AES_0_EN_LEN           (1U)
#define SEC_ENG_SE_AES_0_EN_MSK           (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)
#define SEC_ENG_SE_AES_0_EN_UMSK          (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS))
#define SEC_ENG_SE_AES_0_MODE             SEC_ENG_SE_AES_0_MODE
#define SEC_ENG_SE_AES_0_MODE_POS         (3U)
#define SEC_ENG_SE_AES_0_MODE_LEN         (2U)
#define SEC_ENG_SE_AES_0_MODE_MSK         (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)
#define SEC_ENG_SE_AES_0_MODE_UMSK        (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS))
#define SEC_ENG_SE_AES_0_DEC_EN           SEC_ENG_SE_AES_0_DEC_EN
#define SEC_ENG_SE_AES_0_DEC_EN_POS       (5U)
#define SEC_ENG_SE_AES_0_DEC_EN_LEN       (1U)
#define SEC_ENG_SE_AES_0_DEC_EN_MSK       (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)
#define SEC_ENG_SE_AES_0_DEC_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS))
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL      SEC_ENG_SE_AES_0_DEC_KEY_SEL
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS  (6U)
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN  (1U)
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)
#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS))
#define SEC_ENG_SE_AES_0_HW_KEY_EN        SEC_ENG_SE_AES_0_HW_KEY_EN
#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS    (7U)
#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN    (1U)
#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK    (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)
#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK   (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS))
#define SEC_ENG_SE_AES_0_INT              SEC_ENG_SE_AES_0_INT
#define SEC_ENG_SE_AES_0_INT_POS          (8U)
#define SEC_ENG_SE_AES_0_INT_LEN          (1U)
#define SEC_ENG_SE_AES_0_INT_MSK          (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)
#define SEC_ENG_SE_AES_0_INT_UMSK         (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS))
#define SEC_ENG_SE_AES_0_INT_CLR_1T       SEC_ENG_SE_AES_0_INT_CLR_1T
#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS   (9U)
#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN   (1U)
#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK   (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)
#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS))
#define SEC_ENG_SE_AES_0_INT_SET_1T       SEC_ENG_SE_AES_0_INT_SET_1T
#define SEC_ENG_SE_AES_0_INT_SET_1T_POS   (10U)
#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN   (1U)
#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK   (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)
#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS))
#define SEC_ENG_SE_AES_0_INT_MASK         SEC_ENG_SE_AES_0_INT_MASK
#define SEC_ENG_SE_AES_0_INT_MASK_POS     (11U)
#define SEC_ENG_SE_AES_0_INT_MASK_LEN     (1U)
#define SEC_ENG_SE_AES_0_INT_MASK_MSK     (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)
#define SEC_ENG_SE_AES_0_INT_MASK_UMSK    (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS))
#define SEC_ENG_SE_AES_0_BLOCK_MODE       SEC_ENG_SE_AES_0_BLOCK_MODE
#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS   (12U)
#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN   (2U)
#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK   (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)
#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK  (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS))
#define SEC_ENG_SE_AES_0_IV_SEL           SEC_ENG_SE_AES_0_IV_SEL
#define SEC_ENG_SE_AES_0_IV_SEL_POS       (14U)
#define SEC_ENG_SE_AES_0_IV_SEL_LEN       (1U)
#define SEC_ENG_SE_AES_0_IV_SEL_MSK       (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)
#define SEC_ENG_SE_AES_0_IV_SEL_UMSK      (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS))
#define SEC_ENG_SE_AES_0_LINK_MODE        SEC_ENG_SE_AES_0_LINK_MODE
#define SEC_ENG_SE_AES_0_LINK_MODE_POS    (15U)
#define SEC_ENG_SE_AES_0_LINK_MODE_LEN    (1U)
#define SEC_ENG_SE_AES_0_LINK_MODE_MSK    (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)
#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK   (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS))
#define SEC_ENG_SE_AES_0_MSG_LEN          SEC_ENG_SE_AES_0_MSG_LEN
#define SEC_ENG_SE_AES_0_MSG_LEN_POS      (16U)
#define SEC_ENG_SE_AES_0_MSG_LEN_LEN      (16U)
#define SEC_ENG_SE_AES_0_MSG_LEN_MSK      (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)
#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS))

/* 0x104 : se_aes_0_msa */
#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104)
#define SEC_ENG_SE_AES_0_MSA        SEC_ENG_SE_AES_0_MSA
#define SEC_ENG_SE_AES_0_MSA_POS    (0U)
#define SEC_ENG_SE_AES_0_MSA_LEN    (32U)
#define SEC_ENG_SE_AES_0_MSA_MSK    (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)
#define SEC_ENG_SE_AES_0_MSA_UMSK   (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS))

/* 0x108 : se_aes_0_mda */
#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108)
#define SEC_ENG_SE_AES_0_MDA        SEC_ENG_SE_AES_0_MDA
#define SEC_ENG_SE_AES_0_MDA_POS    (0U)
#define SEC_ENG_SE_AES_0_MDA_LEN    (32U)
#define SEC_ENG_SE_AES_0_MDA_MSK    (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)
#define SEC_ENG_SE_AES_0_MDA_UMSK   (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS))

/* 0x10C : se_aes_0_status */
#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C)
#define SEC_ENG_SE_AES_0_STATUS        SEC_ENG_SE_AES_0_STATUS
#define SEC_ENG_SE_AES_0_STATUS_POS    (0U)
#define SEC_ENG_SE_AES_0_STATUS_LEN    (32U)
#define SEC_ENG_SE_AES_0_STATUS_MSK    (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)
#define SEC_ENG_SE_AES_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS))

/* 0x110 : se_aes_0_iv_0 */
#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110)
#define SEC_ENG_SE_AES_0_IV_0        SEC_ENG_SE_AES_0_IV_0
#define SEC_ENG_SE_AES_0_IV_0_POS    (0U)
#define SEC_ENG_SE_AES_0_IV_0_LEN    (32U)
#define SEC_ENG_SE_AES_0_IV_0_MSK    (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)
#define SEC_ENG_SE_AES_0_IV_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS))

/* 0x114 : se_aes_0_iv_1 */
#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114)
#define SEC_ENG_SE_AES_0_IV_1        SEC_ENG_SE_AES_0_IV_1
#define SEC_ENG_SE_AES_0_IV_1_POS    (0U)
#define SEC_ENG_SE_AES_0_IV_1_LEN    (32U)
#define SEC_ENG_SE_AES_0_IV_1_MSK    (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)
#define SEC_ENG_SE_AES_0_IV_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS))

/* 0x118 : se_aes_0_iv_2 */
#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118)
#define SEC_ENG_SE_AES_0_IV_2        SEC_ENG_SE_AES_0_IV_2
#define SEC_ENG_SE_AES_0_IV_2_POS    (0U)
#define SEC_ENG_SE_AES_0_IV_2_LEN    (32U)
#define SEC_ENG_SE_AES_0_IV_2_MSK    (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)
#define SEC_ENG_SE_AES_0_IV_2_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS))

/* 0x11C : se_aes_0_iv_3 */
#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C)
#define SEC_ENG_SE_AES_0_IV_3        SEC_ENG_SE_AES_0_IV_3
#define SEC_ENG_SE_AES_0_IV_3_POS    (0U)
#define SEC_ENG_SE_AES_0_IV_3_LEN    (32U)
#define SEC_ENG_SE_AES_0_IV_3_MSK    (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)
#define SEC_ENG_SE_AES_0_IV_3_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS))

/* 0x120 : se_aes_0_key_0 */
#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120)
#define SEC_ENG_SE_AES_0_KEY_0        SEC_ENG_SE_AES_0_KEY_0
#define SEC_ENG_SE_AES_0_KEY_0_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_0_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_0_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)
#define SEC_ENG_SE_AES_0_KEY_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS))

/* 0x124 : se_aes_0_key_1 */
#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124)
#define SEC_ENG_SE_AES_0_KEY_1        SEC_ENG_SE_AES_0_KEY_1
#define SEC_ENG_SE_AES_0_KEY_1_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_1_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_1_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)
#define SEC_ENG_SE_AES_0_KEY_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS))

/* 0x128 : se_aes_0_key_2 */
#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128)
#define SEC_ENG_SE_AES_0_KEY_2        SEC_ENG_SE_AES_0_KEY_2
#define SEC_ENG_SE_AES_0_KEY_2_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_2_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_2_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)
#define SEC_ENG_SE_AES_0_KEY_2_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS))

/* 0x12C : se_aes_0_key_3 */
#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C)
#define SEC_ENG_SE_AES_0_KEY_3        SEC_ENG_SE_AES_0_KEY_3
#define SEC_ENG_SE_AES_0_KEY_3_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_3_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_3_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)
#define SEC_ENG_SE_AES_0_KEY_3_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS))

/* 0x130 : se_aes_0_key_4 */
#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130)
#define SEC_ENG_SE_AES_0_KEY_4        SEC_ENG_SE_AES_0_KEY_4
#define SEC_ENG_SE_AES_0_KEY_4_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_4_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_4_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)
#define SEC_ENG_SE_AES_0_KEY_4_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS))

/* 0x134 : se_aes_0_key_5 */
#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134)
#define SEC_ENG_SE_AES_0_KEY_5        SEC_ENG_SE_AES_0_KEY_5
#define SEC_ENG_SE_AES_0_KEY_5_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_5_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_5_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)
#define SEC_ENG_SE_AES_0_KEY_5_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS))

/* 0x138 : se_aes_0_key_6 */
#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138)
#define SEC_ENG_SE_AES_0_KEY_6        SEC_ENG_SE_AES_0_KEY_6
#define SEC_ENG_SE_AES_0_KEY_6_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_6_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_6_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)
#define SEC_ENG_SE_AES_0_KEY_6_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS))

/* 0x13C : se_aes_0_key_7 */
#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C)
#define SEC_ENG_SE_AES_0_KEY_7        SEC_ENG_SE_AES_0_KEY_7
#define SEC_ENG_SE_AES_0_KEY_7_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_7_LEN    (32U)
#define SEC_ENG_SE_AES_0_KEY_7_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)
#define SEC_ENG_SE_AES_0_KEY_7_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS))

/* 0x140 : se_aes_0_key_sel_0 */
#define SEC_ENG_SE_AES_0_KEY_SEL_0_OFFSET (0x140)
#define SEC_ENG_SE_AES_0_KEY_SEL_0        SEC_ENG_SE_AES_0_KEY_SEL_0
#define SEC_ENG_SE_AES_0_KEY_SEL_0_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_SEL_0_LEN    (2U)
#define SEC_ENG_SE_AES_0_KEY_SEL_0_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS)
#define SEC_ENG_SE_AES_0_KEY_SEL_0_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_0_POS))

/* 0x144 : se_aes_0_key_sel_1 */
#define SEC_ENG_SE_AES_0_KEY_SEL_1_OFFSET (0x144)
#define SEC_ENG_SE_AES_0_KEY_SEL_1        SEC_ENG_SE_AES_0_KEY_SEL_1
#define SEC_ENG_SE_AES_0_KEY_SEL_1_POS    (0U)
#define SEC_ENG_SE_AES_0_KEY_SEL_1_LEN    (2U)
#define SEC_ENG_SE_AES_0_KEY_SEL_1_MSK    (((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS)
#define SEC_ENG_SE_AES_0_KEY_SEL_1_UMSK   (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_1_POS))

/* 0x148 : se_aes_0_endian */
#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET    (0x148)
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN      SEC_ENG_SE_AES_0_DOUT_ENDIAN
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS  (0U)
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN  (1U)
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)
#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS))
#define SEC_ENG_SE_AES_0_DIN_ENDIAN       SEC_ENG_SE_AES_0_DIN_ENDIAN
#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS   (1U)
#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN   (1U)
#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)
#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS))
#define SEC_ENG_SE_AES_0_KEY_ENDIAN       SEC_ENG_SE_AES_0_KEY_ENDIAN
#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS   (2U)
#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN   (1U)
#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)
#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS))
#define SEC_ENG_SE_AES_0_IV_ENDIAN        SEC_ENG_SE_AES_0_IV_ENDIAN
#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS    (3U)
#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN    (1U)
#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK    (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)
#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS))
#define SEC_ENG_SE_AES_0_CTR_LEN          SEC_ENG_SE_AES_0_CTR_LEN
#define SEC_ENG_SE_AES_0_CTR_LEN_POS      (30U)
#define SEC_ENG_SE_AES_0_CTR_LEN_LEN      (2U)
#define SEC_ENG_SE_AES_0_CTR_LEN_MSK      (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)
#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS))

/* 0x14C : se_aes_0_sboot */
#define SEC_ENG_SE_AES_0_SBOOT_OFFSET       (0x14C)
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL      SEC_ENG_SE_AES_0_SBOOT_KEY_SEL
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS  (0U)
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN  (1U)
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)
#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS))

/* 0x150 : se_aes_0_link */
#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150)
#define SEC_ENG_SE_AES_0_LCA         SEC_ENG_SE_AES_0_LCA
#define SEC_ENG_SE_AES_0_LCA_POS     (0U)
#define SEC_ENG_SE_AES_0_LCA_LEN     (32U)
#define SEC_ENG_SE_AES_0_LCA_MSK     (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)
#define SEC_ENG_SE_AES_0_LCA_UMSK    (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS))

/* 0x1FC : se_aes_0_ctrl_prot */
#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC)
#define SEC_ENG_SE_AES_PROT_EN            SEC_ENG_SE_AES_PROT_EN
#define SEC_ENG_SE_AES_PROT_EN_POS        (0U)
#define SEC_ENG_SE_AES_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_AES_PROT_EN_MSK        (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)
#define SEC_ENG_SE_AES_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS))
#define SEC_ENG_SE_AES_ID0_EN             SEC_ENG_SE_AES_ID0_EN
#define SEC_ENG_SE_AES_ID0_EN_POS         (1U)
#define SEC_ENG_SE_AES_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_AES_ID0_EN_MSK         (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)
#define SEC_ENG_SE_AES_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS))
#define SEC_ENG_SE_AES_ID1_EN             SEC_ENG_SE_AES_ID1_EN
#define SEC_ENG_SE_AES_ID1_EN_POS         (2U)
#define SEC_ENG_SE_AES_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_AES_ID1_EN_MSK         (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)
#define SEC_ENG_SE_AES_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS))

/* 0x200 : se_trng_0_ctrl_0 */
#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET       (0x200)
#define SEC_ENG_SE_TRNG_0_BUSY                SEC_ENG_SE_TRNG_0_BUSY
#define SEC_ENG_SE_TRNG_0_BUSY_POS            (0U)
#define SEC_ENG_SE_TRNG_0_BUSY_LEN            (1U)
#define SEC_ENG_SE_TRNG_0_BUSY_MSK            (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)
#define SEC_ENG_SE_TRNG_0_BUSY_UMSK           (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS))
#define SEC_ENG_SE_TRNG_0_TRIG_1T             SEC_ENG_SE_TRNG_0_TRIG_1T
#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS         (1U)
#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN         (1U)
#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK         (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)
#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK        (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS))
#define SEC_ENG_SE_TRNG_0_EN                  SEC_ENG_SE_TRNG_0_EN
#define SEC_ENG_SE_TRNG_0_EN_POS              (2U)
#define SEC_ENG_SE_TRNG_0_EN_LEN              (1U)
#define SEC_ENG_SE_TRNG_0_EN_MSK              (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)
#define SEC_ENG_SE_TRNG_0_EN_UMSK             (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS))
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T         SEC_ENG_SE_TRNG_0_DOUT_CLR_1T
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS     (3U)
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN     (1U)
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK     (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS))
#define SEC_ENG_SE_TRNG_0_HT_ERROR            SEC_ENG_SE_TRNG_0_HT_ERROR
#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS        (4U)
#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN        (1U)
#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK        (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)
#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK       (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS))
#define SEC_ENG_SE_TRNG_0_INT                 SEC_ENG_SE_TRNG_0_INT
#define SEC_ENG_SE_TRNG_0_INT_POS             (8U)
#define SEC_ENG_SE_TRNG_0_INT_LEN             (1U)
#define SEC_ENG_SE_TRNG_0_INT_MSK             (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)
#define SEC_ENG_SE_TRNG_0_INT_UMSK            (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS))
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T          SEC_ENG_SE_TRNG_0_INT_CLR_1T
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS      (9U)
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN      (1U)
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK      (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)
#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS))
#define SEC_ENG_SE_TRNG_0_INT_SET_1T          SEC_ENG_SE_TRNG_0_INT_SET_1T
#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS      (10U)
#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN      (1U)
#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK      (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)
#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS))
#define SEC_ENG_SE_TRNG_0_INT_MASK            SEC_ENG_SE_TRNG_0_INT_MASK
#define SEC_ENG_SE_TRNG_0_INT_MASK_POS        (11U)
#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN        (1U)
#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK        (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)
#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK       (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS))
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL      SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS  (13U)
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN  (1U)
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK  (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)
#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS))
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED       SEC_ENG_SE_TRNG_0_MANUAL_RESEED
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS   (14U)
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN   (1U)
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK   (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)
#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS))
#define SEC_ENG_SE_TRNG_0_MANUAL_EN           SEC_ENG_SE_TRNG_0_MANUAL_EN
#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS       (15U)
#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN       (1U)
#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK       (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)
#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS))

/* 0x204 : se_trng_0_status */
#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204)
#define SEC_ENG_SE_TRNG_0_STATUS        SEC_ENG_SE_TRNG_0_STATUS
#define SEC_ENG_SE_TRNG_0_STATUS_POS    (0U)
#define SEC_ENG_SE_TRNG_0_STATUS_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_STATUS_MSK    (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)
#define SEC_ENG_SE_TRNG_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS))

/* 0x208 : se_trng_0_dout_0 */
#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208)
#define SEC_ENG_SE_TRNG_0_DOUT_0        SEC_ENG_SE_TRNG_0_DOUT_0
#define SEC_ENG_SE_TRNG_0_DOUT_0_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS))

/* 0x20C : se_trng_0_dout_1 */
#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C)
#define SEC_ENG_SE_TRNG_0_DOUT_1        SEC_ENG_SE_TRNG_0_DOUT_1
#define SEC_ENG_SE_TRNG_0_DOUT_1_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS))

/* 0x210 : se_trng_0_dout_2 */
#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210)
#define SEC_ENG_SE_TRNG_0_DOUT_2        SEC_ENG_SE_TRNG_0_DOUT_2
#define SEC_ENG_SE_TRNG_0_DOUT_2_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS))

/* 0x214 : se_trng_0_dout_3 */
#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214)
#define SEC_ENG_SE_TRNG_0_DOUT_3        SEC_ENG_SE_TRNG_0_DOUT_3
#define SEC_ENG_SE_TRNG_0_DOUT_3_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS))

/* 0x218 : se_trng_0_dout_4 */
#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218)
#define SEC_ENG_SE_TRNG_0_DOUT_4        SEC_ENG_SE_TRNG_0_DOUT_4
#define SEC_ENG_SE_TRNG_0_DOUT_4_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS))

/* 0x21C : se_trng_0_dout_5 */
#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C)
#define SEC_ENG_SE_TRNG_0_DOUT_5        SEC_ENG_SE_TRNG_0_DOUT_5
#define SEC_ENG_SE_TRNG_0_DOUT_5_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS))

/* 0x220 : se_trng_0_dout_6 */
#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220)
#define SEC_ENG_SE_TRNG_0_DOUT_6        SEC_ENG_SE_TRNG_0_DOUT_6
#define SEC_ENG_SE_TRNG_0_DOUT_6_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS))

/* 0x224 : se_trng_0_dout_7 */
#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224)
#define SEC_ENG_SE_TRNG_0_DOUT_7        SEC_ENG_SE_TRNG_0_DOUT_7
#define SEC_ENG_SE_TRNG_0_DOUT_7_POS    (0U)
#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK    (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)
#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS))

/* 0x228 : se_trng_0_test */
#define SEC_ENG_SE_TRNG_0_TEST_OFFSET     (0x228)
#define SEC_ENG_SE_TRNG_0_TEST_EN         SEC_ENG_SE_TRNG_0_TEST_EN
#define SEC_ENG_SE_TRNG_0_TEST_EN_POS     (0U)
#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN     (1U)
#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK     (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)
#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK    (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS))
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN      SEC_ENG_SE_TRNG_0_CP_TEST_EN
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS  (1U)
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN  (1U)
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK  (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)
#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS))
#define SEC_ENG_SE_TRNG_0_CP_BYPASS       SEC_ENG_SE_TRNG_0_CP_BYPASS
#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS   (2U)
#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN   (1U)
#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK   (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)
#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS))
#define SEC_ENG_SE_TRNG_0_HT_DIS          SEC_ENG_SE_TRNG_0_HT_DIS
#define SEC_ENG_SE_TRNG_0_HT_DIS_POS      (3U)
#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN      (1U)
#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK      (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)
#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK     (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS))
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N      SEC_ENG_SE_TRNG_0_HT_ALARM_N
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS  (4U)
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN  (8U)
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)
#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS))

/* 0x22C : se_trng_0_ctrl_1 */
#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET     (0x22C)
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB      SEC_ENG_SE_TRNG_0_RESEED_N_LSB
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS  (0U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN  (32U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK  (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)
#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS))

/* 0x230 : se_trng_0_ctrl_2 */
#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET     (0x230)
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB      SEC_ENG_SE_TRNG_0_RESEED_N_MSB
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS  (0U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN  (16U)
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK  (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)
#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS))

/* 0x234 : se_trng_0_ctrl_3 */
#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234)
#define SEC_ENG_SE_TRNG_0_CP_RATIO      SEC_ENG_SE_TRNG_0_CP_RATIO
#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS  (0U)
#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN  (8U)
#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK  (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)
#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS))
#define SEC_ENG_SE_TRNG_0_HT_RCT_C      SEC_ENG_SE_TRNG_0_HT_RCT_C
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS  (8U)
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN  (8U)
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)
#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS))
#define SEC_ENG_SE_TRNG_0_HT_APT_C      SEC_ENG_SE_TRNG_0_HT_APT_C
#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS  (16U)
#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN  (10U)
#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)
#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS))
#define SEC_ENG_SE_TRNG_0_HT_OD_EN      SEC_ENG_SE_TRNG_0_HT_OD_EN
#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS  (26U)
#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN  (1U)
#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK  (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)
#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS))
#define SEC_ENG_SE_TRNG_0_ROSC_EN       SEC_ENG_SE_TRNG_0_ROSC_EN
#define SEC_ENG_SE_TRNG_0_ROSC_EN_POS   (31U)
#define SEC_ENG_SE_TRNG_0_ROSC_EN_LEN   (1U)
#define SEC_ENG_SE_TRNG_0_ROSC_EN_MSK   (((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS)
#define SEC_ENG_SE_TRNG_0_ROSC_EN_UMSK  (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS))

/* 0x240 : se_trng_0_test_out_0 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0        SEC_ENG_SE_TRNG_0_TEST_OUT_0
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS    (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS))

/* 0x244 : se_trng_0_test_out_1 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1        SEC_ENG_SE_TRNG_0_TEST_OUT_1
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS    (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS))

/* 0x248 : se_trng_0_test_out_2 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2        SEC_ENG_SE_TRNG_0_TEST_OUT_2
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS    (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS))

/* 0x24C : se_trng_0_test_out_3 */
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3        SEC_ENG_SE_TRNG_0_TEST_OUT_3
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS    (0U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN    (32U)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)
#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS))

/* 0x2FC : se_trng_0_ctrl_prot */
#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC)
#define SEC_ENG_SE_TRNG_PROT_EN            SEC_ENG_SE_TRNG_PROT_EN
#define SEC_ENG_SE_TRNG_PROT_EN_POS        (0U)
#define SEC_ENG_SE_TRNG_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_TRNG_PROT_EN_MSK        (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)
#define SEC_ENG_SE_TRNG_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS))
#define SEC_ENG_SE_TRNG_ID0_EN             SEC_ENG_SE_TRNG_ID0_EN
#define SEC_ENG_SE_TRNG_ID0_EN_POS         (1U)
#define SEC_ENG_SE_TRNG_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_TRNG_ID0_EN_MSK         (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)
#define SEC_ENG_SE_TRNG_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS))
#define SEC_ENG_SE_TRNG_ID1_EN             SEC_ENG_SE_TRNG_ID1_EN
#define SEC_ENG_SE_TRNG_ID1_EN_POS         (2U)
#define SEC_ENG_SE_TRNG_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_TRNG_ID1_EN_MSK         (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)
#define SEC_ENG_SE_TRNG_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS))

/* 0x300 : se_pka_0_ctrl_0 */
#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET      (0x300)
#define SEC_ENG_SE_PKA_0_DONE               SEC_ENG_SE_PKA_0_DONE
#define SEC_ENG_SE_PKA_0_DONE_POS           (0U)
#define SEC_ENG_SE_PKA_0_DONE_LEN           (1U)
#define SEC_ENG_SE_PKA_0_DONE_MSK           (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)
#define SEC_ENG_SE_PKA_0_DONE_UMSK          (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS))
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T        SEC_ENG_SE_PKA_0_DONE_CLR_1T
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS    (1U)
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN    (1U)
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK    (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)
#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS))
#define SEC_ENG_SE_PKA_0_BUSY               SEC_ENG_SE_PKA_0_BUSY
#define SEC_ENG_SE_PKA_0_BUSY_POS           (2U)
#define SEC_ENG_SE_PKA_0_BUSY_LEN           (1U)
#define SEC_ENG_SE_PKA_0_BUSY_MSK           (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)
#define SEC_ENG_SE_PKA_0_BUSY_UMSK          (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS))
#define SEC_ENG_SE_PKA_0_EN                 SEC_ENG_SE_PKA_0_EN
#define SEC_ENG_SE_PKA_0_EN_POS             (3U)
#define SEC_ENG_SE_PKA_0_EN_LEN             (1U)
#define SEC_ENG_SE_PKA_0_EN_MSK             (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)
#define SEC_ENG_SE_PKA_0_EN_UMSK            (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS))
#define SEC_ENG_SE_PKA_0_PROT_MD            SEC_ENG_SE_PKA_0_PROT_MD
#define SEC_ENG_SE_PKA_0_PROT_MD_POS        (4U)
#define SEC_ENG_SE_PKA_0_PROT_MD_LEN        (4U)
#define SEC_ENG_SE_PKA_0_PROT_MD_MSK        (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)
#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK       (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS))
#define SEC_ENG_SE_PKA_0_INT                SEC_ENG_SE_PKA_0_INT
#define SEC_ENG_SE_PKA_0_INT_POS            (8U)
#define SEC_ENG_SE_PKA_0_INT_LEN            (1U)
#define SEC_ENG_SE_PKA_0_INT_MSK            (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)
#define SEC_ENG_SE_PKA_0_INT_UMSK           (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS))
#define SEC_ENG_SE_PKA_0_INT_CLR_1T         SEC_ENG_SE_PKA_0_INT_CLR_1T
#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS     (9U)
#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN     (1U)
#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK     (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)
#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS))
#define SEC_ENG_SE_PKA_0_INT_SET            SEC_ENG_SE_PKA_0_INT_SET
#define SEC_ENG_SE_PKA_0_INT_SET_POS        (10U)
#define SEC_ENG_SE_PKA_0_INT_SET_LEN        (1U)
#define SEC_ENG_SE_PKA_0_INT_SET_MSK        (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)
#define SEC_ENG_SE_PKA_0_INT_SET_UMSK       (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS))
#define SEC_ENG_SE_PKA_0_INT_MASK           SEC_ENG_SE_PKA_0_INT_MASK
#define SEC_ENG_SE_PKA_0_INT_MASK_POS       (11U)
#define SEC_ENG_SE_PKA_0_INT_MASK_LEN       (1U)
#define SEC_ENG_SE_PKA_0_INT_MASK_MSK       (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)
#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK      (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS))
#define SEC_ENG_SE_PKA_0_ENDIAN             SEC_ENG_SE_PKA_0_ENDIAN
#define SEC_ENG_SE_PKA_0_ENDIAN_POS         (12U)
#define SEC_ENG_SE_PKA_0_ENDIAN_LEN         (1U)
#define SEC_ENG_SE_PKA_0_ENDIAN_MSK         (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)
#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK        (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS))
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD         SEC_ENG_SE_PKA_0_RAM_CLR_MD
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS     (13U)
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN     (1U)
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK     (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)
#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK    (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS))
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T      SEC_ENG_SE_PKA_0_STATUS_CLR_1T
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS  (15U)
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN  (1U)
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK  (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)
#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS))
#define SEC_ENG_SE_PKA_0_STATUS             SEC_ENG_SE_PKA_0_STATUS
#define SEC_ENG_SE_PKA_0_STATUS_POS         (16U)
#define SEC_ENG_SE_PKA_0_STATUS_LEN         (16U)
#define SEC_ENG_SE_PKA_0_STATUS_MSK         (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)
#define SEC_ENG_SE_PKA_0_STATUS_UMSK        (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS))

/* 0x30C : se_pka_0_seed */
#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C)
#define SEC_ENG_SE_PKA_0_SEED        SEC_ENG_SE_PKA_0_SEED
#define SEC_ENG_SE_PKA_0_SEED_POS    (0U)
#define SEC_ENG_SE_PKA_0_SEED_LEN    (32U)
#define SEC_ENG_SE_PKA_0_SEED_MSK    (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)
#define SEC_ENG_SE_PKA_0_SEED_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS))

/* 0x310 : se_pka_0_ctrl_1 */
#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310)
#define SEC_ENG_SE_PKA_0_HBURST        SEC_ENG_SE_PKA_0_HBURST
#define SEC_ENG_SE_PKA_0_HBURST_POS    (0U)
#define SEC_ENG_SE_PKA_0_HBURST_LEN    (3U)
#define SEC_ENG_SE_PKA_0_HBURST_MSK    (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)
#define SEC_ENG_SE_PKA_0_HBURST_UMSK   (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS))
#define SEC_ENG_SE_PKA_0_HBYPASS       SEC_ENG_SE_PKA_0_HBYPASS
#define SEC_ENG_SE_PKA_0_HBYPASS_POS   (3U)
#define SEC_ENG_SE_PKA_0_HBYPASS_LEN   (1U)
#define SEC_ENG_SE_PKA_0_HBYPASS_MSK   (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)
#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK  (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS))

/* 0x340 : se_pka_0_rw */
#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340)

/* 0x360 : se_pka_0_rw_burst */
#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360)

/* 0x3FC : se_pka_0_ctrl_prot */
#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC)
#define SEC_ENG_SE_PKA_PROT_EN            SEC_ENG_SE_PKA_PROT_EN
#define SEC_ENG_SE_PKA_PROT_EN_POS        (0U)
#define SEC_ENG_SE_PKA_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_PKA_PROT_EN_MSK        (((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS)
#define SEC_ENG_SE_PKA_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_PKA_PROT_EN_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_POS))
#define SEC_ENG_SE_PKA_ID0_EN             SEC_ENG_SE_PKA_ID0_EN
#define SEC_ENG_SE_PKA_ID0_EN_POS         (1U)
#define SEC_ENG_SE_PKA_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_PKA_ID0_EN_MSK         (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)
#define SEC_ENG_SE_PKA_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS))
#define SEC_ENG_SE_PKA_ID1_EN             SEC_ENG_SE_PKA_ID1_EN
#define SEC_ENG_SE_PKA_ID1_EN_POS         (2U)
#define SEC_ENG_SE_PKA_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_PKA_ID1_EN_MSK         (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)
#define SEC_ENG_SE_PKA_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS))

/* 0x400 : se_cdet_0_ctrl_0 */
#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET   (0x400)
#define SEC_ENG_SE_CDET_0_EN              SEC_ENG_SE_CDET_0_EN
#define SEC_ENG_SE_CDET_0_EN_POS          (0U)
#define SEC_ENG_SE_CDET_0_EN_LEN          (1U)
#define SEC_ENG_SE_CDET_0_EN_MSK          (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)
#define SEC_ENG_SE_CDET_0_EN_UMSK         (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS))
#define SEC_ENG_SE_CDET_0_ERROR           SEC_ENG_SE_CDET_0_ERROR
#define SEC_ENG_SE_CDET_0_ERROR_POS       (1U)
#define SEC_ENG_SE_CDET_0_ERROR_LEN       (1U)
#define SEC_ENG_SE_CDET_0_ERROR_MSK       (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)
#define SEC_ENG_SE_CDET_0_ERROR_UMSK      (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS))
#define SEC_ENG_SE_CDET_0_STATUS          SEC_ENG_SE_CDET_0_STATUS
#define SEC_ENG_SE_CDET_0_STATUS_POS      (2U)
#define SEC_ENG_SE_CDET_0_STATUS_LEN      (14U)
#define SEC_ENG_SE_CDET_0_STATUS_MSK      (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)
#define SEC_ENG_SE_CDET_0_STATUS_UMSK     (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS))
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX      SEC_ENG_SE_CDET_0_G_LOOP_MAX
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS  (16U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN  (8U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK  (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)
#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS))
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN      SEC_ENG_SE_CDET_0_G_LOOP_MIN
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS  (24U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN  (8U)
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK  (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)
#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS))

/* 0x404 : se_cdet_0_ctrl_1 */
#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404)
#define SEC_ENG_SE_CDET_0_T_LOOP_N      SEC_ENG_SE_CDET_0_T_LOOP_N
#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS  (0U)
#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN  (8U)
#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK  (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)
#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS))
#define SEC_ENG_SE_CDET_0_T_DLY_N       SEC_ENG_SE_CDET_0_T_DLY_N
#define SEC_ENG_SE_CDET_0_T_DLY_N_POS   (8U)
#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN   (8U)
#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK   (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)
#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK  (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS))
#define SEC_ENG_SE_CDET_0_G_SLP_N       SEC_ENG_SE_CDET_0_G_SLP_N
#define SEC_ENG_SE_CDET_0_G_SLP_N_POS   (16U)
#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN   (8U)
#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK   (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)
#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK  (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS))

/* 0x4FC : se_cdet_0_ctrl_prot */
#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC)
#define SEC_ENG_SE_CDET_PROT_EN            SEC_ENG_SE_CDET_PROT_EN
#define SEC_ENG_SE_CDET_PROT_EN_POS        (0U)
#define SEC_ENG_SE_CDET_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_CDET_PROT_EN_MSK        (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)
#define SEC_ENG_SE_CDET_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS))
#define SEC_ENG_SE_CDET_ID0_EN             SEC_ENG_SE_CDET_ID0_EN
#define SEC_ENG_SE_CDET_ID0_EN_POS         (1U)
#define SEC_ENG_SE_CDET_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_CDET_ID0_EN_MSK         (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)
#define SEC_ENG_SE_CDET_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS))
#define SEC_ENG_SE_CDET_ID1_EN             SEC_ENG_SE_CDET_ID1_EN
#define SEC_ENG_SE_CDET_ID1_EN_POS         (2U)
#define SEC_ENG_SE_CDET_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_CDET_ID1_EN_MSK         (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)
#define SEC_ENG_SE_CDET_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS))

/* 0x500 : se_gmac_0_ctrl_0 */
#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET   (0x500)
#define SEC_ENG_SE_GMAC_0_BUSY            SEC_ENG_SE_GMAC_0_BUSY
#define SEC_ENG_SE_GMAC_0_BUSY_POS        (0U)
#define SEC_ENG_SE_GMAC_0_BUSY_LEN        (1U)
#define SEC_ENG_SE_GMAC_0_BUSY_MSK        (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)
#define SEC_ENG_SE_GMAC_0_BUSY_UMSK       (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS))
#define SEC_ENG_SE_GMAC_0_TRIG_1T         SEC_ENG_SE_GMAC_0_TRIG_1T
#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS     (1U)
#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN     (1U)
#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK     (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)
#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS))
#define SEC_ENG_SE_GMAC_0_EN              SEC_ENG_SE_GMAC_0_EN
#define SEC_ENG_SE_GMAC_0_EN_POS          (2U)
#define SEC_ENG_SE_GMAC_0_EN_LEN          (1U)
#define SEC_ENG_SE_GMAC_0_EN_MSK          (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)
#define SEC_ENG_SE_GMAC_0_EN_UMSK         (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS))
#define SEC_ENG_SE_GMAC_0_INT             SEC_ENG_SE_GMAC_0_INT
#define SEC_ENG_SE_GMAC_0_INT_POS         (8U)
#define SEC_ENG_SE_GMAC_0_INT_LEN         (1U)
#define SEC_ENG_SE_GMAC_0_INT_MSK         (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)
#define SEC_ENG_SE_GMAC_0_INT_UMSK        (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS))
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T      SEC_ENG_SE_GMAC_0_INT_CLR_1T
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS  (9U)
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN  (1U)
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)
#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS))
#define SEC_ENG_SE_GMAC_0_INT_SET_1T      SEC_ENG_SE_GMAC_0_INT_SET_1T
#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS  (10U)
#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN  (1U)
#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)
#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS))
#define SEC_ENG_SE_GMAC_0_INT_MASK        SEC_ENG_SE_GMAC_0_INT_MASK
#define SEC_ENG_SE_GMAC_0_INT_MASK_POS    (11U)
#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN    (1U)
#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK    (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)
#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS))
#define SEC_ENG_SE_GMAC_0_T_ENDIAN        SEC_ENG_SE_GMAC_0_T_ENDIAN
#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS    (12U)
#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN    (1U)
#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)
#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS))
#define SEC_ENG_SE_GMAC_0_H_ENDIAN        SEC_ENG_SE_GMAC_0_H_ENDIAN
#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS    (13U)
#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN    (1U)
#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)
#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS))
#define SEC_ENG_SE_GMAC_0_X_ENDIAN        SEC_ENG_SE_GMAC_0_X_ENDIAN
#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS    (14U)
#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN    (1U)
#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK    (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)
#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS))

/* 0x504 : se_gmac_0_lca */
#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504)
#define SEC_ENG_SE_GMAC_0_LCA        SEC_ENG_SE_GMAC_0_LCA
#define SEC_ENG_SE_GMAC_0_LCA_POS    (0U)
#define SEC_ENG_SE_GMAC_0_LCA_LEN    (32U)
#define SEC_ENG_SE_GMAC_0_LCA_MSK    (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)
#define SEC_ENG_SE_GMAC_0_LCA_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS))

/* 0x508 : se_gmac_0_status */
#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508)
#define SEC_ENG_SE_GMAC_0_STATUS        SEC_ENG_SE_GMAC_0_STATUS
#define SEC_ENG_SE_GMAC_0_STATUS_POS    (0U)
#define SEC_ENG_SE_GMAC_0_STATUS_LEN    (32U)
#define SEC_ENG_SE_GMAC_0_STATUS_MSK    (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)
#define SEC_ENG_SE_GMAC_0_STATUS_UMSK   (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS))

/* 0x5FC : se_gmac_0_ctrl_prot */
#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC)
#define SEC_ENG_SE_GMAC_PROT_EN            SEC_ENG_SE_GMAC_PROT_EN
#define SEC_ENG_SE_GMAC_PROT_EN_POS        (0U)
#define SEC_ENG_SE_GMAC_PROT_EN_LEN        (1U)
#define SEC_ENG_SE_GMAC_PROT_EN_MSK        (((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS)
#define SEC_ENG_SE_GMAC_PROT_EN_UMSK       (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_POS))
#define SEC_ENG_SE_GMAC_ID0_EN             SEC_ENG_SE_GMAC_ID0_EN
#define SEC_ENG_SE_GMAC_ID0_EN_POS         (1U)
#define SEC_ENG_SE_GMAC_ID0_EN_LEN         (1U)
#define SEC_ENG_SE_GMAC_ID0_EN_MSK         (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)
#define SEC_ENG_SE_GMAC_ID0_EN_UMSK        (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS))
#define SEC_ENG_SE_GMAC_ID1_EN             SEC_ENG_SE_GMAC_ID1_EN
#define SEC_ENG_SE_GMAC_ID1_EN_POS         (2U)
#define SEC_ENG_SE_GMAC_ID1_EN_LEN         (1U)
#define SEC_ENG_SE_GMAC_ID1_EN_MSK         (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)
#define SEC_ENG_SE_GMAC_ID1_EN_UMSK        (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS))

/* 0xF00 : se_ctrl_prot_rd */
#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET  (0xF00)
#define SEC_ENG_SE_SHA_PROT_EN_RD       SEC_ENG_SE_SHA_PROT_EN_RD
#define SEC_ENG_SE_SHA_PROT_EN_RD_POS   (0U)
#define SEC_ENG_SE_SHA_PROT_EN_RD_LEN   (1U)
#define SEC_ENG_SE_SHA_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS)
#define SEC_ENG_SE_SHA_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_SHA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_RD_POS))
#define SEC_ENG_SE_SHA_ID0_EN_RD        SEC_ENG_SE_SHA_ID0_EN_RD
#define SEC_ENG_SE_SHA_ID0_EN_RD_POS    (1U)
#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN    (1U)
#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)
#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS))
#define SEC_ENG_SE_SHA_ID1_EN_RD        SEC_ENG_SE_SHA_ID1_EN_RD
#define SEC_ENG_SE_SHA_ID1_EN_RD_POS    (2U)
#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN    (1U)
#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)
#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS))
#define SEC_ENG_SE_AES_PROT_EN_RD       SEC_ENG_SE_AES_PROT_EN_RD
#define SEC_ENG_SE_AES_PROT_EN_RD_POS   (4U)
#define SEC_ENG_SE_AES_PROT_EN_RD_LEN   (1U)
#define SEC_ENG_SE_AES_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS)
#define SEC_ENG_SE_AES_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_AES_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_RD_POS))
#define SEC_ENG_SE_AES_ID0_EN_RD        SEC_ENG_SE_AES_ID0_EN_RD
#define SEC_ENG_SE_AES_ID0_EN_RD_POS    (5U)
#define SEC_ENG_SE_AES_ID0_EN_RD_LEN    (1U)
#define SEC_ENG_SE_AES_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)
#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS))
#define SEC_ENG_SE_AES_ID1_EN_RD        SEC_ENG_SE_AES_ID1_EN_RD
#define SEC_ENG_SE_AES_ID1_EN_RD_POS    (6U)
#define SEC_ENG_SE_AES_ID1_EN_RD_LEN    (1U)
#define SEC_ENG_SE_AES_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)
#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS))
#define SEC_ENG_SE_TRNG_PROT_EN_RD      SEC_ENG_SE_TRNG_PROT_EN_RD
#define SEC_ENG_SE_TRNG_PROT_EN_RD_POS  (8U)
#define SEC_ENG_SE_TRNG_PROT_EN_RD_LEN  (1U)
#define SEC_ENG_SE_TRNG_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS)
#define SEC_ENG_SE_TRNG_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_RD_POS))
#define SEC_ENG_SE_TRNG_ID0_EN_RD       SEC_ENG_SE_TRNG_ID0_EN_RD
#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS   (9U)
#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN   (1U)
#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)
#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS))
#define SEC_ENG_SE_TRNG_ID1_EN_RD       SEC_ENG_SE_TRNG_ID1_EN_RD
#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS   (10U)
#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN   (1U)
#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)
#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS))
#define SEC_ENG_SE_PKA_PROT_EN_RD       SEC_ENG_SE_PKA_PROT_EN_RD
#define SEC_ENG_SE_PKA_PROT_EN_RD_POS   (12U)
#define SEC_ENG_SE_PKA_PROT_EN_RD_LEN   (1U)
#define SEC_ENG_SE_PKA_PROT_EN_RD_MSK   (((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS)
#define SEC_ENG_SE_PKA_PROT_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_PKA_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_PROT_EN_RD_POS))
#define SEC_ENG_SE_PKA_ID0_EN_RD        SEC_ENG_SE_PKA_ID0_EN_RD
#define SEC_ENG_SE_PKA_ID0_EN_RD_POS    (13U)
#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN    (1U)
#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK    (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)
#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS))
#define SEC_ENG_SE_PKA_ID1_EN_RD        SEC_ENG_SE_PKA_ID1_EN_RD
#define SEC_ENG_SE_PKA_ID1_EN_RD_POS    (14U)
#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN    (1U)
#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK    (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)
#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK   (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS))
#define SEC_ENG_SE_CDET_PROT_EN_RD      SEC_ENG_SE_CDET_PROT_EN_RD
#define SEC_ENG_SE_CDET_PROT_EN_RD_POS  (16U)
#define SEC_ENG_SE_CDET_PROT_EN_RD_LEN  (1U)
#define SEC_ENG_SE_CDET_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS)
#define SEC_ENG_SE_CDET_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_RD_POS))
#define SEC_ENG_SE_CDET_ID0_EN_RD       SEC_ENG_SE_CDET_ID0_EN_RD
#define SEC_ENG_SE_CDET_ID0_EN_RD_POS   (17U)
#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN   (1U)
#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)
#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS))
#define SEC_ENG_SE_CDET_ID1_EN_RD       SEC_ENG_SE_CDET_ID1_EN_RD
#define SEC_ENG_SE_CDET_ID1_EN_RD_POS   (18U)
#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN   (1U)
#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)
#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS))
#define SEC_ENG_SE_GMAC_PROT_EN_RD      SEC_ENG_SE_GMAC_PROT_EN_RD
#define SEC_ENG_SE_GMAC_PROT_EN_RD_POS  (20U)
#define SEC_ENG_SE_GMAC_PROT_EN_RD_LEN  (1U)
#define SEC_ENG_SE_GMAC_PROT_EN_RD_MSK  (((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS)
#define SEC_ENG_SE_GMAC_PROT_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_PROT_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_PROT_EN_RD_POS))
#define SEC_ENG_SE_GMAC_ID0_EN_RD       SEC_ENG_SE_GMAC_ID0_EN_RD
#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS   (21U)
#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN   (1U)
#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK   (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)
#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS))
#define SEC_ENG_SE_GMAC_ID1_EN_RD       SEC_ENG_SE_GMAC_ID1_EN_RD
#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS   (22U)
#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN   (1U)
#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK   (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)
#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK  (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS))
#define SEC_ENG_SE_DBG_DIS              SEC_ENG_SE_DBG_DIS
#define SEC_ENG_SE_DBG_DIS_POS          (31U)
#define SEC_ENG_SE_DBG_DIS_LEN          (1U)
#define SEC_ENG_SE_DBG_DIS_MSK          (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)
#define SEC_ENG_SE_DBG_DIS_UMSK         (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS))

/* 0xF04 : se_ctrl_reserved_0 */
#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04)
#define SEC_ENG_SE_CTRL_RESERVED_0        SEC_ENG_SE_CTRL_RESERVED_0
#define SEC_ENG_SE_CTRL_RESERVED_0_POS    (0U)
#define SEC_ENG_SE_CTRL_RESERVED_0_LEN    (32U)
#define SEC_ENG_SE_CTRL_RESERVED_0_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)
#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS))

/* 0xF08 : se_ctrl_reserved_1 */
#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08)
#define SEC_ENG_SE_CTRL_RESERVED_1        SEC_ENG_SE_CTRL_RESERVED_1
#define SEC_ENG_SE_CTRL_RESERVED_1_POS    (0U)
#define SEC_ENG_SE_CTRL_RESERVED_1_LEN    (32U)
#define SEC_ENG_SE_CTRL_RESERVED_1_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)
#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS))

/* 0xF0C : se_ctrl_reserved_2 */
#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C)
#define SEC_ENG_SE_CTRL_RESERVED_2        SEC_ENG_SE_CTRL_RESERVED_2
#define SEC_ENG_SE_CTRL_RESERVED_2_POS    (0U)
#define SEC_ENG_SE_CTRL_RESERVED_2_LEN    (32U)
#define SEC_ENG_SE_CTRL_RESERVED_2_MSK    (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)
#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK   (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS))

struct sec_eng_reg {
    /* 0x0 : se_sha_0_ctrl */
    union {
        struct
        {
            uint32_t se_sha_0_busy       : 1;  /* [    0],          r,        0x0 */
            uint32_t se_sha_0_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_sha_0_mode       : 3;  /* [ 4: 2],        r/w,        0x0 */
            uint32_t se_sha_0_en         : 1;  /* [    5],        r/w,        0x0 */
            uint32_t se_sha_0_hash_sel   : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t se_sha_0_int        : 1;  /* [    8],          r,        0x0 */
            uint32_t se_sha_0_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_sha_0_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_sha_0_int_mask   : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_14      : 3;  /* [14:12],       rsvd,        0x0 */
            uint32_t se_sha_0_link_mode  : 1;  /* [   15],        r/w,        0x0 */
            uint32_t se_sha_0_msg_len    : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_ctrl;

    /* 0x4 : se_sha_0_msa */
    union {
        struct
        {
            uint32_t se_sha_0_msa : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_msa;

    /* 0x8 : se_sha_0_status */
    union {
        struct
        {
            uint32_t se_sha_0_status : 32; /* [31: 0],          r,       0x41 */
        } BF;
        uint32_t WORD;
    } se_sha_0_status;

    /* 0xC : se_sha_0_endian */
    union {
        struct
        {
            uint32_t se_sha_0_dout_endian : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reserved_1_31        : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_endian;

    /* 0x10 : se_sha_0_hash_l_0 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_0;

    /* 0x14 : se_sha_0_hash_l_1 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_1;

    /* 0x18 : se_sha_0_hash_l_2 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_2;

    /* 0x1C : se_sha_0_hash_l_3 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_3;

    /* 0x20 : se_sha_0_hash_l_4 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_4;

    /* 0x24 : se_sha_0_hash_l_5 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_5;

    /* 0x28 : se_sha_0_hash_l_6 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_6;

    /* 0x2C : se_sha_0_hash_l_7 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_l_7;

    /* 0x30 : se_sha_0_hash_h_0 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_0;

    /* 0x34 : se_sha_0_hash_h_1 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_1;

    /* 0x38 : se_sha_0_hash_h_2 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_2;

    /* 0x3C : se_sha_0_hash_h_3 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_3;

    /* 0x40 : se_sha_0_hash_h_4 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_4;

    /* 0x44 : se_sha_0_hash_h_5 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_5;

    /* 0x48 : se_sha_0_hash_h_6 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_6;

    /* 0x4C : se_sha_0_hash_h_7 */
    union {
        struct
        {
            uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_hash_h_7;

    /* 0x50 : se_sha_0_link */
    union {
        struct
        {
            uint32_t se_sha_0_lca : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_link;

    /* 0x54  reserved */
    uint8_t RESERVED0x54[168];

    /* 0xFC : se_sha_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_sha_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_sha_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_sha_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_0_ctrl_prot;

    /* 0x100 : se_aes_0_ctrl */
    union {
        struct
        {
            uint32_t se_aes_0_busy        : 1;  /* [    0],          r,        0x0 */
            uint32_t se_aes_0_trig_1t     : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_aes_0_en          : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_aes_0_mode        : 2;  /* [ 4: 3],        r/w,        0x0 */
            uint32_t se_aes_0_dec_en      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t se_aes_0_dec_key_sel : 1;  /* [    6],        r/w,        0x0 */
            uint32_t se_aes_0_hw_key_en   : 1;  /* [    7],        r/w,        0x0 */
            uint32_t se_aes_0_int         : 1;  /* [    8],          r,        0x0 */
            uint32_t se_aes_0_int_clr_1t  : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_aes_0_int_set_1t  : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_aes_0_int_mask    : 1;  /* [   11],        r/w,        0x0 */
            uint32_t se_aes_0_block_mode  : 2;  /* [13:12],        r/w,        0x0 */
            uint32_t se_aes_0_iv_sel      : 1;  /* [   14],        r/w,        0x0 */
            uint32_t se_aes_0_link_mode   : 1;  /* [   15],        r/w,        0x0 */
            uint32_t se_aes_0_msg_len     : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_ctrl;

    /* 0x104 : se_aes_0_msa */
    union {
        struct
        {
            uint32_t se_aes_0_msa : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_msa;

    /* 0x108 : se_aes_0_mda */
    union {
        struct
        {
            uint32_t se_aes_0_mda : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_mda;

    /* 0x10C : se_aes_0_status */
    union {
        struct
        {
            uint32_t se_aes_0_status : 32; /* [31: 0],          r,      0x100 */
        } BF;
        uint32_t WORD;
    } se_aes_0_status;

    /* 0x110 : se_aes_0_iv_0 */
    union {
        struct
        {
            uint32_t se_aes_0_iv_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_iv_0;

    /* 0x114 : se_aes_0_iv_1 */
    union {
        struct
        {
            uint32_t se_aes_0_iv_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_iv_1;

    /* 0x118 : se_aes_0_iv_2 */
    union {
        struct
        {
            uint32_t se_aes_0_iv_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_iv_2;

    /* 0x11C : se_aes_0_iv_3 */
    union {
        struct
        {
            uint32_t se_aes_0_iv_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_iv_3;

    /* 0x120 : se_aes_0_key_0 */
    union {
        struct
        {
            uint32_t se_aes_0_key_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_0;

    /* 0x124 : se_aes_0_key_1 */
    union {
        struct
        {
            uint32_t se_aes_0_key_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_1;

    /* 0x128 : se_aes_0_key_2 */
    union {
        struct
        {
            uint32_t se_aes_0_key_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_2;

    /* 0x12C : se_aes_0_key_3 */
    union {
        struct
        {
            uint32_t se_aes_0_key_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_3;

    /* 0x130 : se_aes_0_key_4 */
    union {
        struct
        {
            uint32_t se_aes_0_key_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_4;

    /* 0x134 : se_aes_0_key_5 */
    union {
        struct
        {
            uint32_t se_aes_0_key_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_5;

    /* 0x138 : se_aes_0_key_6 */
    union {
        struct
        {
            uint32_t se_aes_0_key_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_6;

    /* 0x13C : se_aes_0_key_7 */
    union {
        struct
        {
            uint32_t se_aes_0_key_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_7;

    /* 0x140 : se_aes_0_key_sel_0 */
    union {
        struct
        {
            uint32_t se_aes_0_key_sel_0 : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31      : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_sel_0;

    /* 0x144 : se_aes_0_key_sel_1 */
    union {
        struct
        {
            uint32_t se_aes_0_key_sel_1 : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31      : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_key_sel_1;

    /* 0x148 : se_aes_0_endian */
    union {
        struct
        {
            uint32_t se_aes_0_dout_endian : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_aes_0_din_endian  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_aes_0_key_endian  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t se_aes_0_iv_endian   : 1;  /* [    3],        r/w,        0x1 */
            uint32_t reserved_4_29        : 26; /* [29: 4],       rsvd,        0x0 */
            uint32_t se_aes_0_ctr_len     : 2;  /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_endian;

    /* 0x14C : se_aes_0_sboot */
    union {
        struct
        {
            uint32_t se_aes_0_sboot_key_sel : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_31          : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_sboot;

    /* 0x150 : se_aes_0_link */
    union {
        struct
        {
            uint32_t se_aes_0_lca : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_link;

    /* 0x154  reserved */
    uint8_t RESERVED0x154[168];

    /* 0x1FC : se_aes_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_aes_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_aes_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_aes_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_0_ctrl_prot;

    /* 0x200 : se_trng_0_ctrl_0 */
    union {
        struct
        {
            uint32_t se_trng_0_busy           : 1;  /* [    0],          r,        0x0 */
            uint32_t se_trng_0_trig_1t        : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_trng_0_en             : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_trng_0_dout_clr_1t    : 1;  /* [    3],        w1p,        0x0 */
            uint32_t se_trng_0_ht_error       : 1;  /* [    4],          r,        0x0 */
            uint32_t reserved_5_7             : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t se_trng_0_int            : 1;  /* [    8],          r,        0x0 */
            uint32_t se_trng_0_int_clr_1t     : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_trng_0_int_set_1t     : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_trng_0_int_mask       : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12              : 1;  /* [   12],       rsvd,        0x0 */
            uint32_t se_trng_0_manual_fun_sel : 1;  /* [   13],        r/w,        0x0 */
            uint32_t se_trng_0_manual_reseed  : 1;  /* [   14],        r/w,        0x0 */
            uint32_t se_trng_0_manual_en      : 1;  /* [   15],        r/w,        0x0 */
            uint32_t reserved_16_31           : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_ctrl_0;

    /* 0x204 : se_trng_0_status */
    union {
        struct
        {
            uint32_t se_trng_0_status : 32; /* [31: 0],          r,   0x100020 */
        } BF;
        uint32_t WORD;
    } se_trng_0_status;

    /* 0x208 : se_trng_0_dout_0 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_0;

    /* 0x20C : se_trng_0_dout_1 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_1;

    /* 0x210 : se_trng_0_dout_2 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_2;

    /* 0x214 : se_trng_0_dout_3 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_3;

    /* 0x218 : se_trng_0_dout_4 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_4;

    /* 0x21C : se_trng_0_dout_5 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_5;

    /* 0x220 : se_trng_0_dout_6 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_6;

    /* 0x224 : se_trng_0_dout_7 */
    union {
        struct
        {
            uint32_t se_trng_0_dout_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_dout_7;

    /* 0x228 : se_trng_0_test */
    union {
        struct
        {
            uint32_t se_trng_0_test_en    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t se_trng_0_cp_test_en : 1;  /* [    1],        r/w,        0x0 */
            uint32_t se_trng_0_cp_bypass  : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_trng_0_ht_dis     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t se_trng_0_ht_alarm_n : 8;  /* [11: 4],        r/w,        0x0 */
            uint32_t reserved_12_31       : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_test;

    /* 0x22C : se_trng_0_ctrl_1 */
    union {
        struct
        {
            uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0],        r/w,     0xffff */
        } BF;
        uint32_t WORD;
    } se_trng_0_ctrl_1;

    /* 0x230 : se_trng_0_ctrl_2 */
    union {
        struct
        {
            uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0],        r/w,       0xff */
            uint32_t reserved_16_31         : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_ctrl_2;

    /* 0x234 : se_trng_0_ctrl_3 */
    union {
        struct
        {
            uint32_t se_trng_0_cp_ratio : 8;  /* [ 7: 0],        r/w,        0x3 */
            uint32_t se_trng_0_ht_rct_c : 8;  /* [15: 8],        r/w,       0x42 */
            uint32_t se_trng_0_ht_apt_c : 10; /* [25:16],        r/w,      0x37a */
            uint32_t se_trng_0_ht_od_en : 1;  /* [   26],        r/w,        0x0 */
            uint32_t reserved_27_30     : 4;  /* [30:27],       rsvd,        0x0 */
            uint32_t se_trng_0_rosc_en  : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_ctrl_3;

    /* 0x238  reserved */
    uint8_t RESERVED0x238[8];

    /* 0x240 : se_trng_0_test_out_0 */
    union {
        struct
        {
            uint32_t se_trng_0_test_out_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_test_out_0;

    /* 0x244 : se_trng_0_test_out_1 */
    union {
        struct
        {
            uint32_t se_trng_0_test_out_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_test_out_1;

    /* 0x248 : se_trng_0_test_out_2 */
    union {
        struct
        {
            uint32_t se_trng_0_test_out_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_test_out_2;

    /* 0x24C : se_trng_0_test_out_3 */
    union {
        struct
        {
            uint32_t se_trng_0_test_out_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_test_out_3;

    /* 0x250  reserved */
    uint8_t RESERVED0x250[172];

    /* 0x2FC : se_trng_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_trng_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_trng_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_trng_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_0_ctrl_prot;

    /* 0x300 : se_pka_0_ctrl_0 */
    union {
        struct
        {
            uint32_t se_pka_0_done          : 1;  /* [    0],          r,        0x0 */
            uint32_t se_pka_0_done_clr_1t   : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_pka_0_busy          : 1;  /* [    2],          r,        0x0 */
            uint32_t se_pka_0_en            : 1;  /* [    3],        r/w,        0x0 */
            uint32_t se_pka_0_prot_md       : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t se_pka_0_int           : 1;  /* [    8],          r,        0x0 */
            uint32_t se_pka_0_int_clr_1t    : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_pka_0_int_set       : 1;  /* [   10],        r/w,        0x0 */
            uint32_t se_pka_0_int_mask      : 1;  /* [   11],        r/w,        0x0 */
            uint32_t se_pka_0_endian        : 1;  /* [   12],        r/w,        0x0 */
            uint32_t se_pka_0_ram_clr_md    : 1;  /* [   13],        r/w,        0x0 */
            uint32_t reserved_14            : 1;  /* [   14],       rsvd,        0x0 */
            uint32_t se_pka_0_status_clr_1t : 1;  /* [   15],        w1p,        0x0 */
            uint32_t se_pka_0_status        : 16; /* [31:16],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_ctrl_0;

    /* 0x304  reserved */
    uint8_t RESERVED0x304[8];

    /* 0x30C : se_pka_0_seed */
    union {
        struct
        {
            uint32_t se_pka_0_seed : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_seed;

    /* 0x310 : se_pka_0_ctrl_1 */
    union {
        struct
        {
            uint32_t se_pka_0_hburst  : 3;  /* [ 2: 0],        r/w,        0x5 */
            uint32_t se_pka_0_hbypass : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_ctrl_1;

    /* 0x314  reserved */
    uint8_t RESERVED0x314[44];

    /* 0x340 : se_pka_0_rw */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_rw;

    /* 0x344  reserved */
    uint8_t RESERVED0x344[28];

    /* 0x360 : se_pka_0_rw_burst */
    union {
        struct
        {
            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_rw_burst;

    /* 0x364  reserved */
    uint8_t RESERVED0x364[152];

    /* 0x3FC : se_pka_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_pka_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_pka_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_pka_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_pka_0_ctrl_prot;

    /* 0x400 : se_cdet_0_ctrl_0 */
    union {
        struct
        {
            uint32_t se_cdet_0_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t se_cdet_0_error      : 1;  /* [    1],          r,        0x0 */
            uint32_t se_cdet_0_status     : 14; /* [15: 2],          r,        0x1 */
            uint32_t se_cdet_0_g_loop_max : 8;  /* [23:16],        r/w,       0x64 */
            uint32_t se_cdet_0_g_loop_min : 8;  /* [31:24],        r/w,       0x21 */
        } BF;
        uint32_t WORD;
    } se_cdet_0_ctrl_0;

    /* 0x404 : se_cdet_0_ctrl_1 */
    union {
        struct
        {
            uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0],        r/w,       0x32 */
            uint32_t se_cdet_0_t_dly_n  : 8; /* [15: 8],        r/w,        0x3 */
            uint32_t se_cdet_0_g_slp_n  : 8; /* [23:16],        r/w,       0xff */
            uint32_t reserved_24_31     : 8; /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_cdet_0_ctrl_1;

    /* 0x408  reserved */
    uint8_t RESERVED0x408[244];

    /* 0x4FC : se_cdet_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_cdet_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_cdet_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_cdet_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_cdet_0_ctrl_prot;

    /* 0x500 : se_gmac_0_ctrl_0 */
    union {
        struct
        {
            uint32_t se_gmac_0_busy       : 1;  /* [    0],          r,        0x0 */
            uint32_t se_gmac_0_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_gmac_0_en         : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_7         : 5;  /* [ 7: 3],       rsvd,        0x0 */
            uint32_t se_gmac_0_int        : 1;  /* [    8],          r,        0x0 */
            uint32_t se_gmac_0_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_gmac_0_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_gmac_0_int_mask   : 1;  /* [   11],        r/w,        0x0 */
            uint32_t se_gmac_0_t_endian   : 1;  /* [   12],        r/w,        0x1 */
            uint32_t se_gmac_0_h_endian   : 1;  /* [   13],        r/w,        0x1 */
            uint32_t se_gmac_0_x_endian   : 1;  /* [   14],        r/w,        0x1 */
            uint32_t reserved_15_31       : 17; /* [31:15],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_gmac_0_ctrl_0;

    /* 0x504 : se_gmac_0_lca */
    union {
        struct
        {
            uint32_t se_gmac_0_lca : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_gmac_0_lca;

    /* 0x508 : se_gmac_0_status */
    union {
        struct
        {
            uint32_t se_gmac_0_status : 32; /* [31: 0],          r, 0xf1000000L */
        } BF;
        uint32_t WORD;
    } se_gmac_0_status;

    /* 0x50c  reserved */
    uint8_t RESERVED0x50c[240];

    /* 0x5FC : se_gmac_0_ctrl_prot */
    union {
        struct
        {
            uint32_t se_gmac_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_gmac_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_gmac_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_gmac_0_ctrl_prot;

    /* 0x600  reserved */
    uint8_t RESERVED0x600[2304];

    /* 0xF00 : se_ctrl_prot_rd */
    union {
        struct
        {
            uint32_t se_sha_prot_en_rd  : 1; /* [    0],          r,        0x1 */
            uint32_t se_sha_id0_en_rd   : 1; /* [    1],          r,        0x1 */
            uint32_t se_sha_id1_en_rd   : 1; /* [    2],          r,        0x1 */
            uint32_t reserved_3         : 1; /* [    3],       rsvd,        0x0 */
            uint32_t se_aes_prot_en_rd  : 1; /* [    4],          r,        0x1 */
            uint32_t se_aes_id0_en_rd   : 1; /* [    5],          r,        0x1 */
            uint32_t se_aes_id1_en_rd   : 1; /* [    6],          r,        0x1 */
            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
            uint32_t se_trng_prot_en_rd : 1; /* [    8],          r,        0x1 */
            uint32_t se_trng_id0_en_rd  : 1; /* [    9],          r,        0x1 */
            uint32_t se_trng_id1_en_rd  : 1; /* [   10],          r,        0x1 */
            uint32_t reserved_11        : 1; /* [   11],       rsvd,        0x0 */
            uint32_t se_pka_prot_en_rd  : 1; /* [   12],          r,        0x1 */
            uint32_t se_pka_id0_en_rd   : 1; /* [   13],          r,        0x1 */
            uint32_t se_pka_id1_en_rd   : 1; /* [   14],          r,        0x1 */
            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
            uint32_t se_cdet_prot_en_rd : 1; /* [   16],          r,        0x1 */
            uint32_t se_cdet_id0_en_rd  : 1; /* [   17],          r,        0x1 */
            uint32_t se_cdet_id1_en_rd  : 1; /* [   18],          r,        0x1 */
            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
            uint32_t se_gmac_prot_en_rd : 1; /* [   20],          r,        0x1 */
            uint32_t se_gmac_id0_en_rd  : 1; /* [   21],          r,        0x1 */
            uint32_t se_gmac_id1_en_rd  : 1; /* [   22],          r,        0x1 */
            uint32_t reserved_23_30     : 8; /* [30:23],       rsvd,        0x0 */
            uint32_t se_dbg_dis         : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_ctrl_prot_rd;

    /* 0xF04 : se_ctrl_reserved_0 */
    union {
        struct
        {
            uint32_t se_ctrl_reserved_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_ctrl_reserved_0;

    /* 0xF08 : se_ctrl_reserved_1 */
    union {
        struct
        {
            uint32_t se_ctrl_reserved_1 : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } se_ctrl_reserved_1;

    /* 0xF0C : se_ctrl_reserved_2 */
    union {
        struct
        {
            uint32_t se_ctrl_reserved_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_ctrl_reserved_2;
};

typedef volatile struct sec_eng_reg sec_eng_reg_t;

/*Following is reg patch*/

/* 0x0 : se_sha_ctrl */
#define SEC_ENG_SE_SHA_CTRL_OFFSET     (0x0)
#define SEC_ENG_SE_SHA_BUSY            SEC_ENG_SE_SHA_BUSY
#define SEC_ENG_SE_SHA_BUSY_POS        (0U)
#define SEC_ENG_SE_SHA_BUSY_LEN        (1U)
#define SEC_ENG_SE_SHA_BUSY_MSK        (((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS)
#define SEC_ENG_SE_SHA_BUSY_UMSK       (~(((1U << SEC_ENG_SE_SHA_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_BUSY_POS))
#define SEC_ENG_SE_SHA_TRIG_1T         SEC_ENG_SE_SHA_TRIG_1T
#define SEC_ENG_SE_SHA_TRIG_1T_POS     (1U)
#define SEC_ENG_SE_SHA_TRIG_1T_LEN     (1U)
#define SEC_ENG_SE_SHA_TRIG_1T_MSK     (((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS)
#define SEC_ENG_SE_SHA_TRIG_1T_UMSK    (~(((1U << SEC_ENG_SE_SHA_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_TRIG_1T_POS))
#define SEC_ENG_SE_SHA_MODE            SEC_ENG_SE_SHA_MODE
#define SEC_ENG_SE_SHA_MODE_POS        (2U)
#define SEC_ENG_SE_SHA_MODE_LEN        (3U)
#define SEC_ENG_SE_SHA_MODE_MSK        (((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS)
#define SEC_ENG_SE_SHA_MODE_UMSK       (~(((1U << SEC_ENG_SE_SHA_MODE_LEN) - 1) << SEC_ENG_SE_SHA_MODE_POS))
#define SEC_ENG_SE_SHA_EN              SEC_ENG_SE_SHA_EN
#define SEC_ENG_SE_SHA_EN_POS          (5U)
#define SEC_ENG_SE_SHA_EN_LEN          (1U)
#define SEC_ENG_SE_SHA_EN_MSK          (((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS)
#define SEC_ENG_SE_SHA_EN_UMSK         (~(((1U << SEC_ENG_SE_SHA_EN_LEN) - 1) << SEC_ENG_SE_SHA_EN_POS))
#define SEC_ENG_SE_SHA_HASH_SEL        SEC_ENG_SE_SHA_HASH_SEL
#define SEC_ENG_SE_SHA_HASH_SEL_POS    (6U)
#define SEC_ENG_SE_SHA_HASH_SEL_LEN    (1U)
#define SEC_ENG_SE_SHA_HASH_SEL_MSK    (((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS)
#define SEC_ENG_SE_SHA_HASH_SEL_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_HASH_SEL_POS))
#define SEC_ENG_SE_SHA_INT             SEC_ENG_SE_SHA_INT
#define SEC_ENG_SE_SHA_INT_POS         (8U)
#define SEC_ENG_SE_SHA_INT_LEN         (1U)
#define SEC_ENG_SE_SHA_INT_MSK         (((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS)
#define SEC_ENG_SE_SHA_INT_UMSK        (~(((1U << SEC_ENG_SE_SHA_INT_LEN) - 1) << SEC_ENG_SE_SHA_INT_POS))
#define SEC_ENG_SE_SHA_INT_CLR_1T      SEC_ENG_SE_SHA_INT_CLR_1T
#define SEC_ENG_SE_SHA_INT_CLR_1T_POS  (9U)
#define SEC_ENG_SE_SHA_INT_CLR_1T_LEN  (1U)
#define SEC_ENG_SE_SHA_INT_CLR_1T_MSK  (((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS)
#define SEC_ENG_SE_SHA_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_CLR_1T_POS))
#define SEC_ENG_SE_SHA_INT_SET_1T      SEC_ENG_SE_SHA_INT_SET_1T
#define SEC_ENG_SE_SHA_INT_SET_1T_POS  (10U)
#define SEC_ENG_SE_SHA_INT_SET_1T_LEN  (1U)
#define SEC_ENG_SE_SHA_INT_SET_1T_MSK  (((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS)
#define SEC_ENG_SE_SHA_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_INT_SET_1T_POS))
#define SEC_ENG_SE_SHA_INT_MASK        SEC_ENG_SE_SHA_INT_MASK
#define SEC_ENG_SE_SHA_INT_MASK_POS    (11U)
#define SEC_ENG_SE_SHA_INT_MASK_LEN    (1U)
#define SEC_ENG_SE_SHA_INT_MASK_MSK    (((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS)
#define SEC_ENG_SE_SHA_INT_MASK_UMSK   (~(((1U << SEC_ENG_SE_SHA_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_INT_MASK_POS))
#define SEC_ENG_SE_SHA_LINK_MODE       SEC_ENG_SE_SHA_LINK_MODE
#define SEC_ENG_SE_SHA_LINK_MODE_POS   (15U)
#define SEC_ENG_SE_SHA_LINK_MODE_LEN   (1U)
#define SEC_ENG_SE_SHA_LINK_MODE_MSK   (((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS)
#define SEC_ENG_SE_SHA_LINK_MODE_UMSK  (~(((1U << SEC_ENG_SE_SHA_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_LINK_MODE_POS))
#define SEC_ENG_SE_SHA_MSG_LEN         SEC_ENG_SE_SHA_MSG_LEN
#define SEC_ENG_SE_SHA_MSG_LEN_POS     (16U)
#define SEC_ENG_SE_SHA_MSG_LEN_LEN     (16U)
#define SEC_ENG_SE_SHA_MSG_LEN_MSK     (((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS)
#define SEC_ENG_SE_SHA_MSG_LEN_UMSK    (~(((1U << SEC_ENG_SE_SHA_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_MSG_LEN_POS))

/* 0x4 : se_sha_msa */
#define SEC_ENG_SE_SHA_MSA_OFFSET (0x4)
#define SEC_ENG_SE_SHA_MSA        SEC_ENG_SE_SHA_MSA
#define SEC_ENG_SE_SHA_MSA_POS    (0U)
#define SEC_ENG_SE_SHA_MSA_LEN    (32U)
#define SEC_ENG_SE_SHA_MSA_MSK    (((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS)
#define SEC_ENG_SE_SHA_MSA_UMSK   (~(((1U << SEC_ENG_SE_SHA_MSA_LEN) - 1) << SEC_ENG_SE_SHA_MSA_POS))

/* 0x8 : se_sha_status */
#define SEC_ENG_SE_SHA_STATUS_OFFSET (0x8)
#define SEC_ENG_SE_SHA_STATUS        SEC_ENG_SE_SHA_STATUS
#define SEC_ENG_SE_SHA_STATUS_POS    (0U)
#define SEC_ENG_SE_SHA_STATUS_LEN    (32U)
#define SEC_ENG_SE_SHA_STATUS_MSK    (((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS)
#define SEC_ENG_SE_SHA_STATUS_UMSK   (~(((1U << SEC_ENG_SE_SHA_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_STATUS_POS))

/* 0xc : se_sha_endian */
#define SEC_ENG_SE_SHA_ENDIAN_OFFSET    (0xc)
#define SEC_ENG_SE_SHA_DOUT_ENDIAN      SEC_ENG_SE_SHA_DOUT_ENDIAN
#define SEC_ENG_SE_SHA_DOUT_ENDIAN_POS  (0U)
#define SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN  (1U)
#define SEC_ENG_SE_SHA_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS)
#define SEC_ENG_SE_SHA_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_DOUT_ENDIAN_POS))

/* 0x10 : se_sha_hash_l_0 */
#define SEC_ENG_SE_SHA_HASH_L_0_OFFSET (0x10)
#define SEC_ENG_SE_SHA_HASH_L_0        SEC_ENG_SE_SHA_HASH_L_0
#define SEC_ENG_SE_SHA_HASH_L_0_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_0_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_0_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS)
#define SEC_ENG_SE_SHA_HASH_L_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_0_POS))

/* 0x14 : se_sha_hash_l_1 */
#define SEC_ENG_SE_SHA_HASH_L_1_OFFSET (0x14)
#define SEC_ENG_SE_SHA_HASH_L_1        SEC_ENG_SE_SHA_HASH_L_1
#define SEC_ENG_SE_SHA_HASH_L_1_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_1_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_1_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS)
#define SEC_ENG_SE_SHA_HASH_L_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_1_POS))

/* 0x18 : se_sha_hash_l_2 */
#define SEC_ENG_SE_SHA_HASH_L_2_OFFSET (0x18)
#define SEC_ENG_SE_SHA_HASH_L_2        SEC_ENG_SE_SHA_HASH_L_2
#define SEC_ENG_SE_SHA_HASH_L_2_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_2_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_2_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS)
#define SEC_ENG_SE_SHA_HASH_L_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_2_POS))

/* 0x1c : se_sha_hash_l_3 */
#define SEC_ENG_SE_SHA_HASH_L_3_OFFSET (0x1c)
#define SEC_ENG_SE_SHA_HASH_L_3        SEC_ENG_SE_SHA_HASH_L_3
#define SEC_ENG_SE_SHA_HASH_L_3_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_3_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_3_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS)
#define SEC_ENG_SE_SHA_HASH_L_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_3_POS))

/* 0x20 : se_sha_hash_l_4 */
#define SEC_ENG_SE_SHA_HASH_L_4_OFFSET (0x20)
#define SEC_ENG_SE_SHA_HASH_L_4        SEC_ENG_SE_SHA_HASH_L_4
#define SEC_ENG_SE_SHA_HASH_L_4_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_4_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_4_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS)
#define SEC_ENG_SE_SHA_HASH_L_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_4_POS))

/* 0x24 : se_sha_hash_l_5 */
#define SEC_ENG_SE_SHA_HASH_L_5_OFFSET (0x24)
#define SEC_ENG_SE_SHA_HASH_L_5        SEC_ENG_SE_SHA_HASH_L_5
#define SEC_ENG_SE_SHA_HASH_L_5_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_5_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_5_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS)
#define SEC_ENG_SE_SHA_HASH_L_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_5_POS))

/* 0x28 : se_sha_hash_l_6 */
#define SEC_ENG_SE_SHA_HASH_L_6_OFFSET (0x28)
#define SEC_ENG_SE_SHA_HASH_L_6        SEC_ENG_SE_SHA_HASH_L_6
#define SEC_ENG_SE_SHA_HASH_L_6_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_6_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_6_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS)
#define SEC_ENG_SE_SHA_HASH_L_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_6_POS))

/* 0x2c : se_sha_hash_l_7 */
#define SEC_ENG_SE_SHA_HASH_L_7_OFFSET (0x2c)
#define SEC_ENG_SE_SHA_HASH_L_7        SEC_ENG_SE_SHA_HASH_L_7
#define SEC_ENG_SE_SHA_HASH_L_7_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_L_7_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_L_7_MSK    (((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS)
#define SEC_ENG_SE_SHA_HASH_L_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_L_7_POS))

/* 0x30 : se_sha_hash_h_0 */
#define SEC_ENG_SE_SHA_HASH_H_0_OFFSET (0x30)
#define SEC_ENG_SE_SHA_HASH_H_0        SEC_ENG_SE_SHA_HASH_H_0
#define SEC_ENG_SE_SHA_HASH_H_0_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_0_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_0_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS)
#define SEC_ENG_SE_SHA_HASH_H_0_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_0_POS))

/* 0x34 : se_sha_hash_h_1 */
#define SEC_ENG_SE_SHA_HASH_H_1_OFFSET (0x34)
#define SEC_ENG_SE_SHA_HASH_H_1        SEC_ENG_SE_SHA_HASH_H_1
#define SEC_ENG_SE_SHA_HASH_H_1_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_1_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_1_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS)
#define SEC_ENG_SE_SHA_HASH_H_1_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_1_POS))

/* 0x38 : se_sha_hash_h_2 */
#define SEC_ENG_SE_SHA_HASH_H_2_OFFSET (0x38)
#define SEC_ENG_SE_SHA_HASH_H_2        SEC_ENG_SE_SHA_HASH_H_2
#define SEC_ENG_SE_SHA_HASH_H_2_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_2_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_2_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS)
#define SEC_ENG_SE_SHA_HASH_H_2_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_2_POS))

/* 0x3c : se_sha_hash_h_3 */
#define SEC_ENG_SE_SHA_HASH_H_3_OFFSET (0x3c)
#define SEC_ENG_SE_SHA_HASH_H_3        SEC_ENG_SE_SHA_HASH_H_3
#define SEC_ENG_SE_SHA_HASH_H_3_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_3_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_3_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS)
#define SEC_ENG_SE_SHA_HASH_H_3_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_3_POS))

/* 0x40 : se_sha_hash_h_4 */
#define SEC_ENG_SE_SHA_HASH_H_4_OFFSET (0x40)
#define SEC_ENG_SE_SHA_HASH_H_4        SEC_ENG_SE_SHA_HASH_H_4
#define SEC_ENG_SE_SHA_HASH_H_4_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_4_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_4_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS)
#define SEC_ENG_SE_SHA_HASH_H_4_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_4_POS))

/* 0x44 : se_sha_hash_h_5 */
#define SEC_ENG_SE_SHA_HASH_H_5_OFFSET (0x44)
#define SEC_ENG_SE_SHA_HASH_H_5        SEC_ENG_SE_SHA_HASH_H_5
#define SEC_ENG_SE_SHA_HASH_H_5_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_5_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_5_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS)
#define SEC_ENG_SE_SHA_HASH_H_5_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_5_POS))

/* 0x48 : se_sha_hash_h_6 */
#define SEC_ENG_SE_SHA_HASH_H_6_OFFSET (0x48)
#define SEC_ENG_SE_SHA_HASH_H_6        SEC_ENG_SE_SHA_HASH_H_6
#define SEC_ENG_SE_SHA_HASH_H_6_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_6_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_6_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS)
#define SEC_ENG_SE_SHA_HASH_H_6_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_6_POS))

/* 0x4c : se_sha_hash_h_7 */
#define SEC_ENG_SE_SHA_HASH_H_7_OFFSET (0x4c)
#define SEC_ENG_SE_SHA_HASH_H_7        SEC_ENG_SE_SHA_HASH_H_7
#define SEC_ENG_SE_SHA_HASH_H_7_POS    (0U)
#define SEC_ENG_SE_SHA_HASH_H_7_LEN    (32U)
#define SEC_ENG_SE_SHA_HASH_H_7_MSK    (((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS)
#define SEC_ENG_SE_SHA_HASH_H_7_UMSK   (~(((1U << SEC_ENG_SE_SHA_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_HASH_H_7_POS))

/* 0x50 : se_sha_link */
#define SEC_ENG_SE_SHA_LINK_OFFSET (0x50)
#define SEC_ENG_SE_SHA_LCA         SEC_ENG_SE_SHA_LCA
#define SEC_ENG_SE_SHA_LCA_POS     (0U)
#define SEC_ENG_SE_SHA_LCA_LEN     (32U)
#define SEC_ENG_SE_SHA_LCA_MSK     (((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS)
#define SEC_ENG_SE_SHA_LCA_UMSK    (~(((1U << SEC_ENG_SE_SHA_LCA_LEN) - 1) << SEC_ENG_SE_SHA_LCA_POS))

/* 0xfc : se_sha_ctrl_prot */
#define SEC_ENG_SE_SHA_CTRL_PROT_OFFSET (0xfc)
#define SEC_ENG_SE_SHA_PROT_EN          SEC_ENG_SE_SHA_PROT_EN
#define SEC_ENG_SE_SHA_PROT_EN_POS      (0U)
#define SEC_ENG_SE_SHA_PROT_EN_LEN      (1U)
#define SEC_ENG_SE_SHA_PROT_EN_MSK      (((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS)
#define SEC_ENG_SE_SHA_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_SHA_PROT_EN_LEN) - 1) << SEC_ENG_SE_SHA_PROT_EN_POS))
#define SEC_ENG_SE_SHA_ID0_EN           SEC_ENG_SE_SHA_ID0_EN
#define SEC_ENG_SE_SHA_ID0_EN_POS       (1U)
#define SEC_ENG_SE_SHA_ID0_EN_LEN       (1U)
#define SEC_ENG_SE_SHA_ID0_EN_MSK       (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)
#define SEC_ENG_SE_SHA_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS))
#define SEC_ENG_SE_SHA_ID1_EN           SEC_ENG_SE_SHA_ID1_EN
#define SEC_ENG_SE_SHA_ID1_EN_POS       (2U)
#define SEC_ENG_SE_SHA_ID1_EN_LEN       (1U)
#define SEC_ENG_SE_SHA_ID1_EN_MSK       (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)
#define SEC_ENG_SE_SHA_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS))

struct sec_eng_sha_reg {
    /* 0x0 : se_sha_ctrl */
    union {
        struct
        {
            uint32_t se_sha_busy       : 1;  /* [    0],          r,        0x0 */
            uint32_t se_sha_trig_1t    : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_sha_mode       : 3;  /* [ 4: 2],        r/w,        0x0 */
            uint32_t se_sha_en         : 1;  /* [    5],        r/w,        0x0 */
            uint32_t se_sha_hash_sel   : 1;  /* [    6],        r/w,        0x0 */
            uint32_t reserved_7        : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t se_sha_int        : 1;  /* [    8],          r,        0x0 */
            uint32_t se_sha_int_clr_1t : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_sha_int_set_1t : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_sha_int_mask   : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_14    : 3;  /* [14:12],       rsvd,        0x0 */
            uint32_t se_sha_link_mode  : 1;  /* [   15],        r/w,        0x0 */
            uint32_t se_sha_msg_len    : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_ctrl;

    /* 0x4 : se_sha_msa */
    union {
        struct
        {
            uint32_t se_sha_msa : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_msa;

    /* 0x8 : se_sha_status */
    union {
        struct
        {
            uint32_t se_sha_status : 32; /* [31: 0],          r,       0x41 */
        } BF;
        uint32_t WORD;
    } se_sha_status;

    /* 0xc : se_sha_endian */
    union {
        struct
        {
            uint32_t se_sha_dout_endian : 1;  /* [    0],        r/w,        0x1 */
            uint32_t reserved_1_31      : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_endian;

    /* 0x10 : se_sha_hash_l_0 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_0;

    /* 0x14 : se_sha_hash_l_1 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_1;

    /* 0x18 : se_sha_hash_l_2 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_2;

    /* 0x1c : se_sha_hash_l_3 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_3;

    /* 0x20 : se_sha_hash_l_4 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_4;

    /* 0x24 : se_sha_hash_l_5 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_5;

    /* 0x28 : se_sha_hash_l_6 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_6;

    /* 0x2c : se_sha_hash_l_7 */
    union {
        struct
        {
            uint32_t se_sha_hash_l_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_l_7;

    /* 0x30 : se_sha_hash_h_0 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_0;

    /* 0x34 : se_sha_hash_h_1 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_1;

    /* 0x38 : se_sha_hash_h_2 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_2;

    /* 0x3c : se_sha_hash_h_3 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_3;

    /* 0x40 : se_sha_hash_h_4 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_4;

    /* 0x44 : se_sha_hash_h_5 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_5;

    /* 0x48 : se_sha_hash_h_6 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_6;

    /* 0x4c : se_sha_hash_h_7 */
    union {
        struct
        {
            uint32_t se_sha_hash_h_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_hash_h_7;

    /* 0x50 : se_sha_link */
    union {
        struct
        {
            uint32_t se_sha_lca : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_link;

    /* 0x54  reserved */
    uint8_t RESERVED0x54[168];

    /* 0xfc : se_sha_ctrl_prot */
    union {
        struct
        {
            uint32_t se_sha_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_sha_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_sha_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_sha_ctrl_prot;
};

typedef volatile struct sec_eng_sha_reg sec_eng_sha_reg_t;

#define SEC_ENG_SHA_OFFSET 0x000

/*Following is reg patch*/

/* 0x0 : se_aes_ctrl */
#define SEC_ENG_SE_AES_CTRL_OFFSET      (0x0)
#define SEC_ENG_SE_AES_BUSY             SEC_ENG_SE_AES_BUSY
#define SEC_ENG_SE_AES_BUSY_POS         (0U)
#define SEC_ENG_SE_AES_BUSY_LEN         (1U)
#define SEC_ENG_SE_AES_BUSY_MSK         (((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS)
#define SEC_ENG_SE_AES_BUSY_UMSK        (~(((1U << SEC_ENG_SE_AES_BUSY_LEN) - 1) << SEC_ENG_SE_AES_BUSY_POS))
#define SEC_ENG_SE_AES_TRIG_1T          SEC_ENG_SE_AES_TRIG_1T
#define SEC_ENG_SE_AES_TRIG_1T_POS      (1U)
#define SEC_ENG_SE_AES_TRIG_1T_LEN      (1U)
#define SEC_ENG_SE_AES_TRIG_1T_MSK      (((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS)
#define SEC_ENG_SE_AES_TRIG_1T_UMSK     (~(((1U << SEC_ENG_SE_AES_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_TRIG_1T_POS))
#define SEC_ENG_SE_AES_EN               SEC_ENG_SE_AES_EN
#define SEC_ENG_SE_AES_EN_POS           (2U)
#define SEC_ENG_SE_AES_EN_LEN           (1U)
#define SEC_ENG_SE_AES_EN_MSK           (((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS)
#define SEC_ENG_SE_AES_EN_UMSK          (~(((1U << SEC_ENG_SE_AES_EN_LEN) - 1) << SEC_ENG_SE_AES_EN_POS))
#define SEC_ENG_SE_AES_MODE             SEC_ENG_SE_AES_MODE
#define SEC_ENG_SE_AES_MODE_POS         (3U)
#define SEC_ENG_SE_AES_MODE_LEN         (2U)
#define SEC_ENG_SE_AES_MODE_MSK         (((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS)
#define SEC_ENG_SE_AES_MODE_UMSK        (~(((1U << SEC_ENG_SE_AES_MODE_LEN) - 1) << SEC_ENG_SE_AES_MODE_POS))
#define SEC_ENG_SE_AES_DEC_EN           SEC_ENG_SE_AES_DEC_EN
#define SEC_ENG_SE_AES_DEC_EN_POS       (5U)
#define SEC_ENG_SE_AES_DEC_EN_LEN       (1U)
#define SEC_ENG_SE_AES_DEC_EN_MSK       (((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS)
#define SEC_ENG_SE_AES_DEC_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_DEC_EN_POS))
#define SEC_ENG_SE_AES_DEC_KEY_SEL      SEC_ENG_SE_AES_DEC_KEY_SEL
#define SEC_ENG_SE_AES_DEC_KEY_SEL_POS  (6U)
#define SEC_ENG_SE_AES_DEC_KEY_SEL_LEN  (1U)
#define SEC_ENG_SE_AES_DEC_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS)
#define SEC_ENG_SE_AES_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_DEC_KEY_SEL_POS))
#define SEC_ENG_SE_AES_HW_KEY_EN        SEC_ENG_SE_AES_HW_KEY_EN
#define SEC_ENG_SE_AES_HW_KEY_EN_POS    (7U)
#define SEC_ENG_SE_AES_HW_KEY_EN_LEN    (1U)
#define SEC_ENG_SE_AES_HW_KEY_EN_MSK    (((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS)
#define SEC_ENG_SE_AES_HW_KEY_EN_UMSK   (~(((1U << SEC_ENG_SE_AES_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_HW_KEY_EN_POS))
#define SEC_ENG_SE_AES_INT              SEC_ENG_SE_AES_INT
#define SEC_ENG_SE_AES_INT_POS          (8U)
#define SEC_ENG_SE_AES_INT_LEN          (1U)
#define SEC_ENG_SE_AES_INT_MSK          (((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS)
#define SEC_ENG_SE_AES_INT_UMSK         (~(((1U << SEC_ENG_SE_AES_INT_LEN) - 1) << SEC_ENG_SE_AES_INT_POS))
#define SEC_ENG_SE_AES_INT_CLR_1T       SEC_ENG_SE_AES_INT_CLR_1T
#define SEC_ENG_SE_AES_INT_CLR_1T_POS   (9U)
#define SEC_ENG_SE_AES_INT_CLR_1T_LEN   (1U)
#define SEC_ENG_SE_AES_INT_CLR_1T_MSK   (((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS)
#define SEC_ENG_SE_AES_INT_CLR_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_CLR_1T_POS))
#define SEC_ENG_SE_AES_INT_SET_1T       SEC_ENG_SE_AES_INT_SET_1T
#define SEC_ENG_SE_AES_INT_SET_1T_POS   (10U)
#define SEC_ENG_SE_AES_INT_SET_1T_LEN   (1U)
#define SEC_ENG_SE_AES_INT_SET_1T_MSK   (((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS)
#define SEC_ENG_SE_AES_INT_SET_1T_UMSK  (~(((1U << SEC_ENG_SE_AES_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_INT_SET_1T_POS))
#define SEC_ENG_SE_AES_INT_MASK         SEC_ENG_SE_AES_INT_MASK
#define SEC_ENG_SE_AES_INT_MASK_POS     (11U)
#define SEC_ENG_SE_AES_INT_MASK_LEN     (1U)
#define SEC_ENG_SE_AES_INT_MASK_MSK     (((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS)
#define SEC_ENG_SE_AES_INT_MASK_UMSK    (~(((1U << SEC_ENG_SE_AES_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_INT_MASK_POS))
#define SEC_ENG_SE_AES_BLOCK_MODE       SEC_ENG_SE_AES_BLOCK_MODE
#define SEC_ENG_SE_AES_BLOCK_MODE_POS   (12U)
#define SEC_ENG_SE_AES_BLOCK_MODE_LEN   (2U)
#define SEC_ENG_SE_AES_BLOCK_MODE_MSK   (((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS)
#define SEC_ENG_SE_AES_BLOCK_MODE_UMSK  (~(((1U << SEC_ENG_SE_AES_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_BLOCK_MODE_POS))
#define SEC_ENG_SE_AES_IV_SEL           SEC_ENG_SE_AES_IV_SEL
#define SEC_ENG_SE_AES_IV_SEL_POS       (14U)
#define SEC_ENG_SE_AES_IV_SEL_LEN       (1U)
#define SEC_ENG_SE_AES_IV_SEL_MSK       (((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS)
#define SEC_ENG_SE_AES_IV_SEL_UMSK      (~(((1U << SEC_ENG_SE_AES_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_IV_SEL_POS))
#define SEC_ENG_SE_AES_LINK_MODE        SEC_ENG_SE_AES_LINK_MODE
#define SEC_ENG_SE_AES_LINK_MODE_POS    (15U)
#define SEC_ENG_SE_AES_LINK_MODE_LEN    (1U)
#define SEC_ENG_SE_AES_LINK_MODE_MSK    (((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS)
#define SEC_ENG_SE_AES_LINK_MODE_UMSK   (~(((1U << SEC_ENG_SE_AES_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_LINK_MODE_POS))
#define SEC_ENG_SE_AES_MSG_LEN          SEC_ENG_SE_AES_MSG_LEN
#define SEC_ENG_SE_AES_MSG_LEN_POS      (16U)
#define SEC_ENG_SE_AES_MSG_LEN_LEN      (16U)
#define SEC_ENG_SE_AES_MSG_LEN_MSK      (((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS)
#define SEC_ENG_SE_AES_MSG_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_MSG_LEN_POS))

/* 0x4 : se_aes_msa */
#define SEC_ENG_SE_AES_MSA_OFFSET (0x4)
#define SEC_ENG_SE_AES_MSA        SEC_ENG_SE_AES_MSA
#define SEC_ENG_SE_AES_MSA_POS    (0U)
#define SEC_ENG_SE_AES_MSA_LEN    (32U)
#define SEC_ENG_SE_AES_MSA_MSK    (((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS)
#define SEC_ENG_SE_AES_MSA_UMSK   (~(((1U << SEC_ENG_SE_AES_MSA_LEN) - 1) << SEC_ENG_SE_AES_MSA_POS))

/* 0x8 : se_aes_mda */
#define SEC_ENG_SE_AES_MDA_OFFSET (0x8)
#define SEC_ENG_SE_AES_MDA        SEC_ENG_SE_AES_MDA
#define SEC_ENG_SE_AES_MDA_POS    (0U)
#define SEC_ENG_SE_AES_MDA_LEN    (32U)
#define SEC_ENG_SE_AES_MDA_MSK    (((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS)
#define SEC_ENG_SE_AES_MDA_UMSK   (~(((1U << SEC_ENG_SE_AES_MDA_LEN) - 1) << SEC_ENG_SE_AES_MDA_POS))

/* 0xc : se_aes_status */
#define SEC_ENG_SE_AES_STATUS_OFFSET (0xc)
#define SEC_ENG_SE_AES_STATUS        SEC_ENG_SE_AES_STATUS
#define SEC_ENG_SE_AES_STATUS_POS    (0U)
#define SEC_ENG_SE_AES_STATUS_LEN    (32U)
#define SEC_ENG_SE_AES_STATUS_MSK    (((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS)
#define SEC_ENG_SE_AES_STATUS_UMSK   (~(((1U << SEC_ENG_SE_AES_STATUS_LEN) - 1) << SEC_ENG_SE_AES_STATUS_POS))

/* 0x10 : se_aes_iv_0 */
#define SEC_ENG_SE_AES_IV_0_OFFSET (0x10)
#define SEC_ENG_SE_AES_IV_0        SEC_ENG_SE_AES_IV_0
#define SEC_ENG_SE_AES_IV_0_POS    (0U)
#define SEC_ENG_SE_AES_IV_0_LEN    (32U)
#define SEC_ENG_SE_AES_IV_0_MSK    (((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS)
#define SEC_ENG_SE_AES_IV_0_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_0_LEN) - 1) << SEC_ENG_SE_AES_IV_0_POS))

/* 0x14 : se_aes_iv_1 */
#define SEC_ENG_SE_AES_IV_1_OFFSET (0x14)
#define SEC_ENG_SE_AES_IV_1        SEC_ENG_SE_AES_IV_1
#define SEC_ENG_SE_AES_IV_1_POS    (0U)
#define SEC_ENG_SE_AES_IV_1_LEN    (32U)
#define SEC_ENG_SE_AES_IV_1_MSK    (((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS)
#define SEC_ENG_SE_AES_IV_1_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_1_LEN) - 1) << SEC_ENG_SE_AES_IV_1_POS))

/* 0x18 : se_aes_iv_2 */
#define SEC_ENG_SE_AES_IV_2_OFFSET (0x18)
#define SEC_ENG_SE_AES_IV_2        SEC_ENG_SE_AES_IV_2
#define SEC_ENG_SE_AES_IV_2_POS    (0U)
#define SEC_ENG_SE_AES_IV_2_LEN    (32U)
#define SEC_ENG_SE_AES_IV_2_MSK    (((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS)
#define SEC_ENG_SE_AES_IV_2_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_2_LEN) - 1) << SEC_ENG_SE_AES_IV_2_POS))

/* 0x1c : se_aes_iv_3 */
#define SEC_ENG_SE_AES_IV_3_OFFSET (0x1c)
#define SEC_ENG_SE_AES_IV_3        SEC_ENG_SE_AES_IV_3
#define SEC_ENG_SE_AES_IV_3_POS    (0U)
#define SEC_ENG_SE_AES_IV_3_LEN    (32U)
#define SEC_ENG_SE_AES_IV_3_MSK    (((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS)
#define SEC_ENG_SE_AES_IV_3_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_3_LEN) - 1) << SEC_ENG_SE_AES_IV_3_POS))

/* 0x20 : se_aes_key_0 */
#define SEC_ENG_SE_AES_KEY_0_OFFSET (0x20)
#define SEC_ENG_SE_AES_KEY_0        SEC_ENG_SE_AES_KEY_0
#define SEC_ENG_SE_AES_KEY_0_POS    (0U)
#define SEC_ENG_SE_AES_KEY_0_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_0_MSK    (((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS)
#define SEC_ENG_SE_AES_KEY_0_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_0_POS))

/* 0x24 : se_aes_key_1 */
#define SEC_ENG_SE_AES_KEY_1_OFFSET (0x24)
#define SEC_ENG_SE_AES_KEY_1        SEC_ENG_SE_AES_KEY_1
#define SEC_ENG_SE_AES_KEY_1_POS    (0U)
#define SEC_ENG_SE_AES_KEY_1_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_1_MSK    (((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS)
#define SEC_ENG_SE_AES_KEY_1_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_1_POS))

/* 0x28 : se_aes_key_2 */
#define SEC_ENG_SE_AES_KEY_2_OFFSET (0x28)
#define SEC_ENG_SE_AES_KEY_2        SEC_ENG_SE_AES_KEY_2
#define SEC_ENG_SE_AES_KEY_2_POS    (0U)
#define SEC_ENG_SE_AES_KEY_2_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_2_MSK    (((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS)
#define SEC_ENG_SE_AES_KEY_2_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_KEY_2_POS))

/* 0x2c : se_aes_key_3 */
#define SEC_ENG_SE_AES_KEY_3_OFFSET (0x2c)
#define SEC_ENG_SE_AES_KEY_3        SEC_ENG_SE_AES_KEY_3
#define SEC_ENG_SE_AES_KEY_3_POS    (0U)
#define SEC_ENG_SE_AES_KEY_3_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_3_MSK    (((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS)
#define SEC_ENG_SE_AES_KEY_3_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_KEY_3_POS))

/* 0x30 : se_aes_key_4 */
#define SEC_ENG_SE_AES_KEY_4_OFFSET (0x30)
#define SEC_ENG_SE_AES_KEY_4        SEC_ENG_SE_AES_KEY_4
#define SEC_ENG_SE_AES_KEY_4_POS    (0U)
#define SEC_ENG_SE_AES_KEY_4_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_4_MSK    (((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS)
#define SEC_ENG_SE_AES_KEY_4_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_KEY_4_POS))

/* 0x34 : se_aes_key_5 */
#define SEC_ENG_SE_AES_KEY_5_OFFSET (0x34)
#define SEC_ENG_SE_AES_KEY_5        SEC_ENG_SE_AES_KEY_5
#define SEC_ENG_SE_AES_KEY_5_POS    (0U)
#define SEC_ENG_SE_AES_KEY_5_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_5_MSK    (((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS)
#define SEC_ENG_SE_AES_KEY_5_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_KEY_5_POS))

/* 0x38 : se_aes_key_6 */
#define SEC_ENG_SE_AES_KEY_6_OFFSET (0x38)
#define SEC_ENG_SE_AES_KEY_6        SEC_ENG_SE_AES_KEY_6
#define SEC_ENG_SE_AES_KEY_6_POS    (0U)
#define SEC_ENG_SE_AES_KEY_6_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_6_MSK    (((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS)
#define SEC_ENG_SE_AES_KEY_6_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_KEY_6_POS))

/* 0x3c : se_aes_key_7 */
#define SEC_ENG_SE_AES_KEY_7_OFFSET (0x3c)
#define SEC_ENG_SE_AES_KEY_7        SEC_ENG_SE_AES_KEY_7
#define SEC_ENG_SE_AES_KEY_7_POS    (0U)
#define SEC_ENG_SE_AES_KEY_7_LEN    (32U)
#define SEC_ENG_SE_AES_KEY_7_MSK    (((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS)
#define SEC_ENG_SE_AES_KEY_7_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_KEY_7_POS))

/* 0x40 : se_aes_key_sel_0 */
#define SEC_ENG_SE_AES_KEY_SEL_0_OFFSET (0x40)
#define SEC_ENG_SE_AES_KEY_SEL_0        SEC_ENG_SE_AES_KEY_SEL_0
#define SEC_ENG_SE_AES_KEY_SEL_0_POS    (0U)
#define SEC_ENG_SE_AES_KEY_SEL_0_LEN    (2U)
#define SEC_ENG_SE_AES_KEY_SEL_0_MSK    (((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS)
#define SEC_ENG_SE_AES_KEY_SEL_0_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_SEL_0_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_0_POS))

/* 0x44 : se_aes_key_sel_1 */
#define SEC_ENG_SE_AES_KEY_SEL_1_OFFSET (0x44)
#define SEC_ENG_SE_AES_KEY_SEL_1        SEC_ENG_SE_AES_KEY_SEL_1
#define SEC_ENG_SE_AES_KEY_SEL_1_POS    (0U)
#define SEC_ENG_SE_AES_KEY_SEL_1_LEN    (2U)
#define SEC_ENG_SE_AES_KEY_SEL_1_MSK    (((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS)
#define SEC_ENG_SE_AES_KEY_SEL_1_UMSK   (~(((1U << SEC_ENG_SE_AES_KEY_SEL_1_LEN) - 1) << SEC_ENG_SE_AES_KEY_SEL_1_POS))

/* 0x48 : se_aes_endian */
#define SEC_ENG_SE_AES_ENDIAN_OFFSET    (0x48)
#define SEC_ENG_SE_AES_DOUT_ENDIAN      SEC_ENG_SE_AES_DOUT_ENDIAN
#define SEC_ENG_SE_AES_DOUT_ENDIAN_POS  (0U)
#define SEC_ENG_SE_AES_DOUT_ENDIAN_LEN  (1U)
#define SEC_ENG_SE_AES_DOUT_ENDIAN_MSK  (((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS)
#define SEC_ENG_SE_AES_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DOUT_ENDIAN_POS))
#define SEC_ENG_SE_AES_DIN_ENDIAN       SEC_ENG_SE_AES_DIN_ENDIAN
#define SEC_ENG_SE_AES_DIN_ENDIAN_POS   (1U)
#define SEC_ENG_SE_AES_DIN_ENDIAN_LEN   (1U)
#define SEC_ENG_SE_AES_DIN_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS)
#define SEC_ENG_SE_AES_DIN_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_DIN_ENDIAN_POS))
#define SEC_ENG_SE_AES_KEY_ENDIAN       SEC_ENG_SE_AES_KEY_ENDIAN
#define SEC_ENG_SE_AES_KEY_ENDIAN_POS   (2U)
#define SEC_ENG_SE_AES_KEY_ENDIAN_LEN   (1U)
#define SEC_ENG_SE_AES_KEY_ENDIAN_MSK   (((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS)
#define SEC_ENG_SE_AES_KEY_ENDIAN_UMSK  (~(((1U << SEC_ENG_SE_AES_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_KEY_ENDIAN_POS))
#define SEC_ENG_SE_AES_IV_ENDIAN        SEC_ENG_SE_AES_IV_ENDIAN
#define SEC_ENG_SE_AES_IV_ENDIAN_POS    (3U)
#define SEC_ENG_SE_AES_IV_ENDIAN_LEN    (1U)
#define SEC_ENG_SE_AES_IV_ENDIAN_MSK    (((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS)
#define SEC_ENG_SE_AES_IV_ENDIAN_UMSK   (~(((1U << SEC_ENG_SE_AES_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_IV_ENDIAN_POS))
#define SEC_ENG_SE_AES_CTR_LEN          SEC_ENG_SE_AES_CTR_LEN
#define SEC_ENG_SE_AES_CTR_LEN_POS      (30U)
#define SEC_ENG_SE_AES_CTR_LEN_LEN      (2U)
#define SEC_ENG_SE_AES_CTR_LEN_MSK      (((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS)
#define SEC_ENG_SE_AES_CTR_LEN_UMSK     (~(((1U << SEC_ENG_SE_AES_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_CTR_LEN_POS))

/* 0x4c : se_aes_sboot */
#define SEC_ENG_SE_AES_SBOOT_OFFSET       (0x4c)
#define SEC_ENG_SE_AES_SBOOT_KEY_SEL      SEC_ENG_SE_AES_SBOOT_KEY_SEL
#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS  (0U)
#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN  (1U)
#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_MSK  (((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS)
#define SEC_ENG_SE_AES_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_SBOOT_KEY_SEL_POS))

/* 0x50 : se_aes_link */
#define SEC_ENG_SE_AES_LINK_OFFSET (0x50)
#define SEC_ENG_SE_AES_LCA         SEC_ENG_SE_AES_LCA
#define SEC_ENG_SE_AES_LCA_POS     (0U)
#define SEC_ENG_SE_AES_LCA_LEN     (32U)
#define SEC_ENG_SE_AES_LCA_MSK     (((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS)
#define SEC_ENG_SE_AES_LCA_UMSK    (~(((1U << SEC_ENG_SE_AES_LCA_LEN) - 1) << SEC_ENG_SE_AES_LCA_POS))

/* 0xfc : se_aes_ctrl_prot */
#define SEC_ENG_SE_AES_CTRL_PROT_OFFSET (0xfc)
#define SEC_ENG_SE_AES_PROT_EN          SEC_ENG_SE_AES_PROT_EN
#define SEC_ENG_SE_AES_PROT_EN_POS      (0U)
#define SEC_ENG_SE_AES_PROT_EN_LEN      (1U)
#define SEC_ENG_SE_AES_PROT_EN_MSK      (((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS)
#define SEC_ENG_SE_AES_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_AES_PROT_EN_LEN) - 1) << SEC_ENG_SE_AES_PROT_EN_POS))
#define SEC_ENG_SE_AES_ID0_EN           SEC_ENG_SE_AES_ID0_EN
#define SEC_ENG_SE_AES_ID0_EN_POS       (1U)
#define SEC_ENG_SE_AES_ID0_EN_LEN       (1U)
#define SEC_ENG_SE_AES_ID0_EN_MSK       (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)
#define SEC_ENG_SE_AES_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS))
#define SEC_ENG_SE_AES_ID1_EN           SEC_ENG_SE_AES_ID1_EN
#define SEC_ENG_SE_AES_ID1_EN_POS       (2U)
#define SEC_ENG_SE_AES_ID1_EN_LEN       (1U)
#define SEC_ENG_SE_AES_ID1_EN_MSK       (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)
#define SEC_ENG_SE_AES_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS))

struct sec_eng_aes_reg {
    /* 0x0 : se_aes_ctrl */
    union {
        struct
        {
            uint32_t se_aes_busy        : 1;  /* [    0],          r,        0x0 */
            uint32_t se_aes_trig_1t     : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_aes_en          : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_aes_mode        : 2;  /* [ 4: 3],        r/w,        0x0 */
            uint32_t se_aes_dec_en      : 1;  /* [    5],        r/w,        0x0 */
            uint32_t se_aes_dec_key_sel : 1;  /* [    6],        r/w,        0x0 */
            uint32_t se_aes_hw_key_en   : 1;  /* [    7],        r/w,        0x0 */
            uint32_t se_aes_int         : 1;  /* [    8],          r,        0x0 */
            uint32_t se_aes_int_clr_1t  : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_aes_int_set_1t  : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_aes_int_mask    : 1;  /* [   11],        r/w,        0x0 */
            uint32_t se_aes_block_mode  : 2;  /* [13:12],        r/w,        0x0 */
            uint32_t se_aes_iv_sel      : 1;  /* [   14],        r/w,        0x0 */
            uint32_t se_aes_link_mode   : 1;  /* [   15],        r/w,        0x0 */
            uint32_t se_aes_msg_len     : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_ctrl;

    /* 0x4 : se_aes_msa */
    union {
        struct
        {
            uint32_t se_aes_msa : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_msa;

    /* 0x8 : se_aes_mda */
    union {
        struct
        {
            uint32_t se_aes_mda : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_mda;

    /* 0xc : se_aes_status */
    union {
        struct
        {
            uint32_t se_aes_status : 32; /* [31: 0],          r,      0x100 */
        } BF;
        uint32_t WORD;
    } se_aes_status;

    /* 0x10 : se_aes_iv_0 */
    union {
        struct
        {
            uint32_t se_aes_iv_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_iv_0;

    /* 0x14 : se_aes_iv_1 */
    union {
        struct
        {
            uint32_t se_aes_iv_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_iv_1;

    /* 0x18 : se_aes_iv_2 */
    union {
        struct
        {
            uint32_t se_aes_iv_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_iv_2;

    /* 0x1c : se_aes_iv_3 */
    union {
        struct
        {
            uint32_t se_aes_iv_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_iv_3;

    /* 0x20 : se_aes_key_0 */
    union {
        struct
        {
            uint32_t se_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_0;

    /* 0x24 : se_aes_key_1 */
    union {
        struct
        {
            uint32_t se_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_1;

    /* 0x28 : se_aes_key_2 */
    union {
        struct
        {
            uint32_t se_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_2;

    /* 0x2c : se_aes_key_3 */
    union {
        struct
        {
            uint32_t se_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_3;

    /* 0x30 : se_aes_key_4 */
    union {
        struct
        {
            uint32_t se_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_4;

    /* 0x34 : se_aes_key_5 */
    union {
        struct
        {
            uint32_t se_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_5;

    /* 0x38 : se_aes_key_6 */
    union {
        struct
        {
            uint32_t se_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_6;

    /* 0x3c : se_aes_key_7 */
    union {
        struct
        {
            uint32_t se_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_7;

    /* 0x40 : se_aes_key_sel_0 */
    union {
        struct
        {
            uint32_t se_aes_key_sel_0 : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_sel_0;

    /* 0x44 : se_aes_key_sel_1 */
    union {
        struct
        {
            uint32_t se_aes_key_sel_1 : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_key_sel_1;

    /* 0x48 : se_aes_endian */
    union {
        struct
        {
            uint32_t se_aes_dout_endian : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_aes_din_endian  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_aes_key_endian  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t se_aes_iv_endian   : 1;  /* [    3],        r/w,        0x1 */
            uint32_t reserved_4_29      : 26; /* [29: 4],       rsvd,        0x0 */
            uint32_t se_aes_ctr_len     : 2;  /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_endian;

    /* 0x4c : se_aes_sboot */
    union {
        struct
        {
            uint32_t se_aes_sboot_key_sel : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_31        : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_sboot;

    /* 0x50 : se_aes_link */
    union {
        struct
        {
            uint32_t se_aes_lca : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_link;

    /* 0x54  reserved */
    uint8_t RESERVED0x54[168];

    /* 0xfc : se_aes_ctrl_prot */
    union {
        struct
        {
            uint32_t se_aes_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_aes_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_aes_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_aes_ctrl_prot;
};

typedef volatile struct sec_eng_aes_reg sec_eng_aes_reg_t;

#define SEC_ENG_AES_OFFSET 0x100

/*Following is reg patch*/

/* 0x0 : se_trng_ctrl_0 */
#define SEC_ENG_SE_TRNG_CTRL_0_OFFSET       (0x0)
#define SEC_ENG_SE_TRNG_BUSY                SEC_ENG_SE_TRNG_BUSY
#define SEC_ENG_SE_TRNG_BUSY_POS            (0U)
#define SEC_ENG_SE_TRNG_BUSY_LEN            (1U)
#define SEC_ENG_SE_TRNG_BUSY_MSK            (((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS)
#define SEC_ENG_SE_TRNG_BUSY_UMSK           (~(((1U << SEC_ENG_SE_TRNG_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_BUSY_POS))
#define SEC_ENG_SE_TRNG_TRIG_1T             SEC_ENG_SE_TRNG_TRIG_1T
#define SEC_ENG_SE_TRNG_TRIG_1T_POS         (1U)
#define SEC_ENG_SE_TRNG_TRIG_1T_LEN         (1U)
#define SEC_ENG_SE_TRNG_TRIG_1T_MSK         (((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS)
#define SEC_ENG_SE_TRNG_TRIG_1T_UMSK        (~(((1U << SEC_ENG_SE_TRNG_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_TRIG_1T_POS))
#define SEC_ENG_SE_TRNG_EN                  SEC_ENG_SE_TRNG_EN
#define SEC_ENG_SE_TRNG_EN_POS              (2U)
#define SEC_ENG_SE_TRNG_EN_LEN              (1U)
#define SEC_ENG_SE_TRNG_EN_MSK              (((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS)
#define SEC_ENG_SE_TRNG_EN_UMSK             (~(((1U << SEC_ENG_SE_TRNG_EN_LEN) - 1) << SEC_ENG_SE_TRNG_EN_POS))
#define SEC_ENG_SE_TRNG_DOUT_CLR_1T         SEC_ENG_SE_TRNG_DOUT_CLR_1T
#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS     (3U)
#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN     (1U)
#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_MSK     (((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS)
#define SEC_ENG_SE_TRNG_DOUT_CLR_1T_UMSK    (~(((1U << SEC_ENG_SE_TRNG_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_CLR_1T_POS))
#define SEC_ENG_SE_TRNG_HT_ERROR            SEC_ENG_SE_TRNG_HT_ERROR
#define SEC_ENG_SE_TRNG_HT_ERROR_POS        (4U)
#define SEC_ENG_SE_TRNG_HT_ERROR_LEN        (1U)
#define SEC_ENG_SE_TRNG_HT_ERROR_MSK        (((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS)
#define SEC_ENG_SE_TRNG_HT_ERROR_UMSK       (~(((1U << SEC_ENG_SE_TRNG_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ERROR_POS))
#define SEC_ENG_SE_TRNG_INT                 SEC_ENG_SE_TRNG_INT
#define SEC_ENG_SE_TRNG_INT_POS             (8U)
#define SEC_ENG_SE_TRNG_INT_LEN             (1U)
#define SEC_ENG_SE_TRNG_INT_MSK             (((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS)
#define SEC_ENG_SE_TRNG_INT_UMSK            (~(((1U << SEC_ENG_SE_TRNG_INT_LEN) - 1) << SEC_ENG_SE_TRNG_INT_POS))
#define SEC_ENG_SE_TRNG_INT_CLR_1T          SEC_ENG_SE_TRNG_INT_CLR_1T
#define SEC_ENG_SE_TRNG_INT_CLR_1T_POS      (9U)
#define SEC_ENG_SE_TRNG_INT_CLR_1T_LEN      (1U)
#define SEC_ENG_SE_TRNG_INT_CLR_1T_MSK      (((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS)
#define SEC_ENG_SE_TRNG_INT_CLR_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_CLR_1T_POS))
#define SEC_ENG_SE_TRNG_INT_SET_1T          SEC_ENG_SE_TRNG_INT_SET_1T
#define SEC_ENG_SE_TRNG_INT_SET_1T_POS      (10U)
#define SEC_ENG_SE_TRNG_INT_SET_1T_LEN      (1U)
#define SEC_ENG_SE_TRNG_INT_SET_1T_MSK      (((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS)
#define SEC_ENG_SE_TRNG_INT_SET_1T_UMSK     (~(((1U << SEC_ENG_SE_TRNG_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_INT_SET_1T_POS))
#define SEC_ENG_SE_TRNG_INT_MASK            SEC_ENG_SE_TRNG_INT_MASK
#define SEC_ENG_SE_TRNG_INT_MASK_POS        (11U)
#define SEC_ENG_SE_TRNG_INT_MASK_LEN        (1U)
#define SEC_ENG_SE_TRNG_INT_MASK_MSK        (((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS)
#define SEC_ENG_SE_TRNG_INT_MASK_UMSK       (~(((1U << SEC_ENG_SE_TRNG_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_INT_MASK_POS))
#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL      SEC_ENG_SE_TRNG_MANUAL_FUN_SEL
#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS  (13U)
#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN  (1U)
#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_MSK  (((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS)
#define SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_FUN_SEL_POS))
#define SEC_ENG_SE_TRNG_MANUAL_RESEED       SEC_ENG_SE_TRNG_MANUAL_RESEED
#define SEC_ENG_SE_TRNG_MANUAL_RESEED_POS   (14U)
#define SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN   (1U)
#define SEC_ENG_SE_TRNG_MANUAL_RESEED_MSK   (((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS)
#define SEC_ENG_SE_TRNG_MANUAL_RESEED_UMSK  (~(((1U << SEC_ENG_SE_TRNG_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_RESEED_POS))
#define SEC_ENG_SE_TRNG_MANUAL_EN           SEC_ENG_SE_TRNG_MANUAL_EN
#define SEC_ENG_SE_TRNG_MANUAL_EN_POS       (15U)
#define SEC_ENG_SE_TRNG_MANUAL_EN_LEN       (1U)
#define SEC_ENG_SE_TRNG_MANUAL_EN_MSK       (((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS)
#define SEC_ENG_SE_TRNG_MANUAL_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_MANUAL_EN_POS))

/* 0x4 : se_trng_status */
#define SEC_ENG_SE_TRNG_STATUS_OFFSET (0x4)
#define SEC_ENG_SE_TRNG_STATUS        SEC_ENG_SE_TRNG_STATUS
#define SEC_ENG_SE_TRNG_STATUS_POS    (0U)
#define SEC_ENG_SE_TRNG_STATUS_LEN    (32U)
#define SEC_ENG_SE_TRNG_STATUS_MSK    (((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS)
#define SEC_ENG_SE_TRNG_STATUS_UMSK   (~(((1U << SEC_ENG_SE_TRNG_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_STATUS_POS))

/* 0x8 : se_trng_dout_0 */
#define SEC_ENG_SE_TRNG_DOUT_0_OFFSET (0x8)
#define SEC_ENG_SE_TRNG_DOUT_0        SEC_ENG_SE_TRNG_DOUT_0
#define SEC_ENG_SE_TRNG_DOUT_0_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_0_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS)
#define SEC_ENG_SE_TRNG_DOUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_0_POS))

/* 0xc : se_trng_dout_1 */
#define SEC_ENG_SE_TRNG_DOUT_1_OFFSET (0xc)
#define SEC_ENG_SE_TRNG_DOUT_1        SEC_ENG_SE_TRNG_DOUT_1
#define SEC_ENG_SE_TRNG_DOUT_1_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_1_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS)
#define SEC_ENG_SE_TRNG_DOUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_1_POS))

/* 0x10 : se_trng_dout_2 */
#define SEC_ENG_SE_TRNG_DOUT_2_OFFSET (0x10)
#define SEC_ENG_SE_TRNG_DOUT_2        SEC_ENG_SE_TRNG_DOUT_2
#define SEC_ENG_SE_TRNG_DOUT_2_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_2_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS)
#define SEC_ENG_SE_TRNG_DOUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_2_POS))

/* 0x14 : se_trng_dout_3 */
#define SEC_ENG_SE_TRNG_DOUT_3_OFFSET (0x14)
#define SEC_ENG_SE_TRNG_DOUT_3        SEC_ENG_SE_TRNG_DOUT_3
#define SEC_ENG_SE_TRNG_DOUT_3_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_3_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS)
#define SEC_ENG_SE_TRNG_DOUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_3_POS))

/* 0x18 : se_trng_dout_4 */
#define SEC_ENG_SE_TRNG_DOUT_4_OFFSET (0x18)
#define SEC_ENG_SE_TRNG_DOUT_4        SEC_ENG_SE_TRNG_DOUT_4
#define SEC_ENG_SE_TRNG_DOUT_4_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_4_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_4_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS)
#define SEC_ENG_SE_TRNG_DOUT_4_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_4_POS))

/* 0x1c : se_trng_dout_5 */
#define SEC_ENG_SE_TRNG_DOUT_5_OFFSET (0x1c)
#define SEC_ENG_SE_TRNG_DOUT_5        SEC_ENG_SE_TRNG_DOUT_5
#define SEC_ENG_SE_TRNG_DOUT_5_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_5_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_5_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS)
#define SEC_ENG_SE_TRNG_DOUT_5_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_5_POS))

/* 0x20 : se_trng_dout_6 */
#define SEC_ENG_SE_TRNG_DOUT_6_OFFSET (0x20)
#define SEC_ENG_SE_TRNG_DOUT_6        SEC_ENG_SE_TRNG_DOUT_6
#define SEC_ENG_SE_TRNG_DOUT_6_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_6_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_6_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS)
#define SEC_ENG_SE_TRNG_DOUT_6_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_6_POS))

/* 0x24 : se_trng_dout_7 */
#define SEC_ENG_SE_TRNG_DOUT_7_OFFSET (0x24)
#define SEC_ENG_SE_TRNG_DOUT_7        SEC_ENG_SE_TRNG_DOUT_7
#define SEC_ENG_SE_TRNG_DOUT_7_POS    (0U)
#define SEC_ENG_SE_TRNG_DOUT_7_LEN    (32U)
#define SEC_ENG_SE_TRNG_DOUT_7_MSK    (((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS)
#define SEC_ENG_SE_TRNG_DOUT_7_UMSK   (~(((1U << SEC_ENG_SE_TRNG_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_DOUT_7_POS))

/* 0x28 : se_trng_test */
#define SEC_ENG_SE_TRNG_TEST_OFFSET     (0x28)
#define SEC_ENG_SE_TRNG_TEST_EN         SEC_ENG_SE_TRNG_TEST_EN
#define SEC_ENG_SE_TRNG_TEST_EN_POS     (0U)
#define SEC_ENG_SE_TRNG_TEST_EN_LEN     (1U)
#define SEC_ENG_SE_TRNG_TEST_EN_MSK     (((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS)
#define SEC_ENG_SE_TRNG_TEST_EN_UMSK    (~(((1U << SEC_ENG_SE_TRNG_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_EN_POS))
#define SEC_ENG_SE_TRNG_CP_TEST_EN      SEC_ENG_SE_TRNG_CP_TEST_EN
#define SEC_ENG_SE_TRNG_CP_TEST_EN_POS  (1U)
#define SEC_ENG_SE_TRNG_CP_TEST_EN_LEN  (1U)
#define SEC_ENG_SE_TRNG_CP_TEST_EN_MSK  (((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS)
#define SEC_ENG_SE_TRNG_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_CP_TEST_EN_POS))
#define SEC_ENG_SE_TRNG_CP_BYPASS       SEC_ENG_SE_TRNG_CP_BYPASS
#define SEC_ENG_SE_TRNG_CP_BYPASS_POS   (2U)
#define SEC_ENG_SE_TRNG_CP_BYPASS_LEN   (1U)
#define SEC_ENG_SE_TRNG_CP_BYPASS_MSK   (((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS)
#define SEC_ENG_SE_TRNG_CP_BYPASS_UMSK  (~(((1U << SEC_ENG_SE_TRNG_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_CP_BYPASS_POS))
#define SEC_ENG_SE_TRNG_HT_DIS          SEC_ENG_SE_TRNG_HT_DIS
#define SEC_ENG_SE_TRNG_HT_DIS_POS      (3U)
#define SEC_ENG_SE_TRNG_HT_DIS_LEN      (1U)
#define SEC_ENG_SE_TRNG_HT_DIS_MSK      (((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS)
#define SEC_ENG_SE_TRNG_HT_DIS_UMSK     (~(((1U << SEC_ENG_SE_TRNG_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_HT_DIS_POS))
#define SEC_ENG_SE_TRNG_HT_ALARM_N      SEC_ENG_SE_TRNG_HT_ALARM_N
#define SEC_ENG_SE_TRNG_HT_ALARM_N_POS  (4U)
#define SEC_ENG_SE_TRNG_HT_ALARM_N_LEN  (8U)
#define SEC_ENG_SE_TRNG_HT_ALARM_N_MSK  (((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS)
#define SEC_ENG_SE_TRNG_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_HT_ALARM_N_POS))

/* 0x2c : se_trng_ctrl_1 */
#define SEC_ENG_SE_TRNG_CTRL_1_OFFSET     (0x2c)
#define SEC_ENG_SE_TRNG_RESEED_N_LSB      SEC_ENG_SE_TRNG_RESEED_N_LSB
#define SEC_ENG_SE_TRNG_RESEED_N_LSB_POS  (0U)
#define SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN  (32U)
#define SEC_ENG_SE_TRNG_RESEED_N_LSB_MSK  (((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS)
#define SEC_ENG_SE_TRNG_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_LSB_POS))

/* 0x30 : se_trng_ctrl_2 */
#define SEC_ENG_SE_TRNG_CTRL_2_OFFSET     (0x30)
#define SEC_ENG_SE_TRNG_RESEED_N_MSB      SEC_ENG_SE_TRNG_RESEED_N_MSB
#define SEC_ENG_SE_TRNG_RESEED_N_MSB_POS  (0U)
#define SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN  (16U)
#define SEC_ENG_SE_TRNG_RESEED_N_MSB_MSK  (((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS)
#define SEC_ENG_SE_TRNG_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_RESEED_N_MSB_POS))

/* 0x34 : se_trng_ctrl_3 */
#define SEC_ENG_SE_TRNG_CTRL_3_OFFSET (0x34)
#define SEC_ENG_SE_TRNG_CP_RATIO      SEC_ENG_SE_TRNG_CP_RATIO
#define SEC_ENG_SE_TRNG_CP_RATIO_POS  (0U)
#define SEC_ENG_SE_TRNG_CP_RATIO_LEN  (8U)
#define SEC_ENG_SE_TRNG_CP_RATIO_MSK  (((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS)
#define SEC_ENG_SE_TRNG_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_CP_RATIO_POS))
#define SEC_ENG_SE_TRNG_HT_RCT_C      SEC_ENG_SE_TRNG_HT_RCT_C
#define SEC_ENG_SE_TRNG_HT_RCT_C_POS  (8U)
#define SEC_ENG_SE_TRNG_HT_RCT_C_LEN  (8U)
#define SEC_ENG_SE_TRNG_HT_RCT_C_MSK  (((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS)
#define SEC_ENG_SE_TRNG_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_RCT_C_POS))
#define SEC_ENG_SE_TRNG_HT_APT_C      SEC_ENG_SE_TRNG_HT_APT_C
#define SEC_ENG_SE_TRNG_HT_APT_C_POS  (16U)
#define SEC_ENG_SE_TRNG_HT_APT_C_LEN  (10U)
#define SEC_ENG_SE_TRNG_HT_APT_C_MSK  (((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS)
#define SEC_ENG_SE_TRNG_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_HT_APT_C_POS))
#define SEC_ENG_SE_TRNG_HT_OD_EN      SEC_ENG_SE_TRNG_HT_OD_EN
#define SEC_ENG_SE_TRNG_HT_OD_EN_POS  (26U)
#define SEC_ENG_SE_TRNG_HT_OD_EN_LEN  (1U)
#define SEC_ENG_SE_TRNG_HT_OD_EN_MSK  (((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS)
#define SEC_ENG_SE_TRNG_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_HT_OD_EN_POS))
#define SEC_ENG_SE_TRNG_ROSC_EN       SEC_ENG_SE_TRNG_ROSC_EN
#define SEC_ENG_SE_TRNG_ROSC_EN_POS   (31U)
#define SEC_ENG_SE_TRNG_ROSC_EN_LEN   (1U)
#define SEC_ENG_SE_TRNG_ROSC_EN_MSK   (((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS)
#define SEC_ENG_SE_TRNG_ROSC_EN_UMSK  (~(((1U << SEC_ENG_SE_TRNG_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ROSC_EN_POS))

/* 0x40 : se_trng_test_out_0 */
#define SEC_ENG_SE_TRNG_TEST_OUT_0_OFFSET (0x40)
#define SEC_ENG_SE_TRNG_TEST_OUT_0        SEC_ENG_SE_TRNG_TEST_OUT_0
#define SEC_ENG_SE_TRNG_TEST_OUT_0_POS    (0U)
#define SEC_ENG_SE_TRNG_TEST_OUT_0_LEN    (32U)
#define SEC_ENG_SE_TRNG_TEST_OUT_0_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS)
#define SEC_ENG_SE_TRNG_TEST_OUT_0_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_0_POS))

/* 0x44 : se_trng_test_out_1 */
#define SEC_ENG_SE_TRNG_TEST_OUT_1_OFFSET (0x44)
#define SEC_ENG_SE_TRNG_TEST_OUT_1        SEC_ENG_SE_TRNG_TEST_OUT_1
#define SEC_ENG_SE_TRNG_TEST_OUT_1_POS    (0U)
#define SEC_ENG_SE_TRNG_TEST_OUT_1_LEN    (32U)
#define SEC_ENG_SE_TRNG_TEST_OUT_1_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS)
#define SEC_ENG_SE_TRNG_TEST_OUT_1_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_1_POS))

/* 0x48 : se_trng_test_out_2 */
#define SEC_ENG_SE_TRNG_TEST_OUT_2_OFFSET (0x48)
#define SEC_ENG_SE_TRNG_TEST_OUT_2        SEC_ENG_SE_TRNG_TEST_OUT_2
#define SEC_ENG_SE_TRNG_TEST_OUT_2_POS    (0U)
#define SEC_ENG_SE_TRNG_TEST_OUT_2_LEN    (32U)
#define SEC_ENG_SE_TRNG_TEST_OUT_2_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS)
#define SEC_ENG_SE_TRNG_TEST_OUT_2_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_2_POS))

/* 0x4c : se_trng_test_out_3 */
#define SEC_ENG_SE_TRNG_TEST_OUT_3_OFFSET (0x4c)
#define SEC_ENG_SE_TRNG_TEST_OUT_3        SEC_ENG_SE_TRNG_TEST_OUT_3
#define SEC_ENG_SE_TRNG_TEST_OUT_3_POS    (0U)
#define SEC_ENG_SE_TRNG_TEST_OUT_3_LEN    (32U)
#define SEC_ENG_SE_TRNG_TEST_OUT_3_MSK    (((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS)
#define SEC_ENG_SE_TRNG_TEST_OUT_3_UMSK   (~(((1U << SEC_ENG_SE_TRNG_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_TEST_OUT_3_POS))

/* 0xfc : se_trng_ctrl_prot */
#define SEC_ENG_SE_TRNG_CTRL_PROT_OFFSET (0xfc)
#define SEC_ENG_SE_TRNG_PROT_EN          SEC_ENG_SE_TRNG_PROT_EN
#define SEC_ENG_SE_TRNG_PROT_EN_POS      (0U)
#define SEC_ENG_SE_TRNG_PROT_EN_LEN      (1U)
#define SEC_ENG_SE_TRNG_PROT_EN_MSK      (((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS)
#define SEC_ENG_SE_TRNG_PROT_EN_UMSK     (~(((1U << SEC_ENG_SE_TRNG_PROT_EN_LEN) - 1) << SEC_ENG_SE_TRNG_PROT_EN_POS))
#define SEC_ENG_SE_TRNG_ID0_EN           SEC_ENG_SE_TRNG_ID0_EN
#define SEC_ENG_SE_TRNG_ID0_EN_POS       (1U)
#define SEC_ENG_SE_TRNG_ID0_EN_LEN       (1U)
#define SEC_ENG_SE_TRNG_ID0_EN_MSK       (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)
#define SEC_ENG_SE_TRNG_ID0_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS))
#define SEC_ENG_SE_TRNG_ID1_EN           SEC_ENG_SE_TRNG_ID1_EN
#define SEC_ENG_SE_TRNG_ID1_EN_POS       (2U)
#define SEC_ENG_SE_TRNG_ID1_EN_LEN       (1U)
#define SEC_ENG_SE_TRNG_ID1_EN_MSK       (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)
#define SEC_ENG_SE_TRNG_ID1_EN_UMSK      (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS))

struct sec_eng_trng_reg {
    /* 0x0 : se_trng_ctrl_0 */
    union {
        struct
        {
            uint32_t se_trng_busy           : 1;  /* [    0],          r,        0x0 */
            uint32_t se_trng_trig_1t        : 1;  /* [    1],        w1p,        0x0 */
            uint32_t se_trng_en             : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_trng_dout_clr_1t    : 1;  /* [    3],        w1p,        0x0 */
            uint32_t se_trng_ht_error       : 1;  /* [    4],          r,        0x0 */
            uint32_t reserved_5_7           : 3;  /* [ 7: 5],       rsvd,        0x0 */
            uint32_t se_trng_int            : 1;  /* [    8],          r,        0x0 */
            uint32_t se_trng_int_clr_1t     : 1;  /* [    9],        w1p,        0x0 */
            uint32_t se_trng_int_set_1t     : 1;  /* [   10],        w1p,        0x0 */
            uint32_t se_trng_int_mask       : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12            : 1;  /* [   12],       rsvd,        0x0 */
            uint32_t se_trng_manual_fun_sel : 1;  /* [   13],        r/w,        0x0 */
            uint32_t se_trng_manual_reseed  : 1;  /* [   14],        r/w,        0x0 */
            uint32_t se_trng_manual_en      : 1;  /* [   15],        r/w,        0x0 */
            uint32_t reserved_16_31         : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_ctrl_0;

    /* 0x4 : se_trng_status */
    union {
        struct
        {
            uint32_t se_trng_status : 32; /* [31: 0],          r,   0x100020 */
        } BF;
        uint32_t WORD;
    } se_trng_status;

    /* 0x8 : se_trng_dout_0 */
    union {
        struct
        {
            uint32_t se_trng_dout_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_0;

    /* 0xc : se_trng_dout_1 */
    union {
        struct
        {
            uint32_t se_trng_dout_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_1;

    /* 0x10 : se_trng_dout_2 */
    union {
        struct
        {
            uint32_t se_trng_dout_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_2;

    /* 0x14 : se_trng_dout_3 */
    union {
        struct
        {
            uint32_t se_trng_dout_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_3;

    /* 0x18 : se_trng_dout_4 */
    union {
        struct
        {
            uint32_t se_trng_dout_4 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_4;

    /* 0x1c : se_trng_dout_5 */
    union {
        struct
        {
            uint32_t se_trng_dout_5 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_5;

    /* 0x20 : se_trng_dout_6 */
    union {
        struct
        {
            uint32_t se_trng_dout_6 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_6;

    /* 0x24 : se_trng_dout_7 */
    union {
        struct
        {
            uint32_t se_trng_dout_7 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_dout_7;

    /* 0x28 : se_trng_test */
    union {
        struct
        {
            uint32_t se_trng_test_en    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t se_trng_cp_test_en : 1;  /* [    1],        r/w,        0x0 */
            uint32_t se_trng_cp_bypass  : 1;  /* [    2],        r/w,        0x0 */
            uint32_t se_trng_ht_dis     : 1;  /* [    3],        r/w,        0x0 */
            uint32_t se_trng_ht_alarm_n : 8;  /* [11: 4],        r/w,        0x0 */
            uint32_t reserved_12_31     : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_test;

    /* 0x2c : se_trng_ctrl_1 */
    union {
        struct
        {
            uint32_t se_trng_reseed_n_lsb : 32; /* [31: 0],        r/w,     0xffff */
        } BF;
        uint32_t WORD;
    } se_trng_ctrl_1;

    /* 0x30 : se_trng_ctrl_2 */
    union {
        struct
        {
            uint32_t se_trng_reseed_n_msb : 16; /* [15: 0],        r/w,       0xff */
            uint32_t reserved_16_31       : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_ctrl_2;

    /* 0x34 : se_trng_ctrl_3 */
    union {
        struct
        {
            uint32_t se_trng_cp_ratio : 8;  /* [ 7: 0],        r/w,        0x3 */
            uint32_t se_trng_ht_rct_c : 8;  /* [15: 8],        r/w,       0x42 */
            uint32_t se_trng_ht_apt_c : 10; /* [25:16],        r/w,      0x37a */
            uint32_t se_trng_ht_od_en : 1;  /* [   26],        r/w,        0x0 */
            uint32_t reserved_27_30   : 4;  /* [30:27],       rsvd,        0x0 */
            uint32_t se_trng_rosc_en  : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_ctrl_3;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[8];

    /* 0x40 : se_trng_test_out_0 */
    union {
        struct
        {
            uint32_t se_trng_test_out_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_test_out_0;

    /* 0x44 : se_trng_test_out_1 */
    union {
        struct
        {
            uint32_t se_trng_test_out_1 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_test_out_1;

    /* 0x48 : se_trng_test_out_2 */
    union {
        struct
        {
            uint32_t se_trng_test_out_2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_test_out_2;

    /* 0x4c : se_trng_test_out_3 */
    union {
        struct
        {
            uint32_t se_trng_test_out_3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_test_out_3;

    /* 0x50  reserved */
    uint8_t RESERVED0x50[172];

    /* 0xfc : se_trng_ctrl_prot */
    union {
        struct
        {
            uint32_t se_trng_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t se_trng_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t se_trng_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } se_trng_ctrl_prot;
};

typedef volatile struct sec_eng_trng_reg sec_eng_trng_reg_t;

#define SEC_ENG_TRNG_OFFSET 0x200

#endif /* __SEC_ENG_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/sf_ctrl_reg.h
================================================
/**
  ******************************************************************************
  * @file    sf_ctrl_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __SF_CTRL_REG_H__
#define __SF_CTRL_REG_H__

#include "bl702.h"

/* 0x0 : sf_ctrl_0 */
#define SF_CTRL_0_OFFSET                  (0x0)
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL      SF_CTRL_SF_CLK_SF_RX_INV_SEL
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS  (2U)
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN  (1U)
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
#define SF_CTRL_SF_CLK_OUT_GATE_EN        SF_CTRL_SF_CLK_OUT_GATE_EN
#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS    (3U)
#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN    (1U)
#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK    (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
#define SF_CTRL_SF_CLK_OUT_INV_SEL        SF_CTRL_SF_CLK_OUT_INV_SEL
#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS    (4U)
#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN    (1U)
#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL      SF_CTRL_SF_CLK_SAHB_SRAM_SEL
#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS  (5U)
#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN  (1U)
#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)
#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS))
#define SF_CTRL_SF_IF_READ_DLY_N          SF_CTRL_SF_IF_READ_DLY_N
#define SF_CTRL_SF_IF_READ_DLY_N_POS      (8U)
#define SF_CTRL_SF_IF_READ_DLY_N_LEN      (3U)
#define SF_CTRL_SF_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
#define SF_CTRL_SF_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
#define SF_CTRL_SF_IF_READ_DLY_EN         SF_CTRL_SF_IF_READ_DLY_EN
#define SF_CTRL_SF_IF_READ_DLY_EN_POS     (11U)
#define SF_CTRL_SF_IF_READ_DLY_EN_LEN     (1U)
#define SF_CTRL_SF_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
#define SF_CTRL_SF_IF_INT                 SF_CTRL_SF_IF_INT
#define SF_CTRL_SF_IF_INT_POS             (16U)
#define SF_CTRL_SF_IF_INT_LEN             (1U)
#define SF_CTRL_SF_IF_INT_MSK             (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
#define SF_CTRL_SF_IF_INT_UMSK            (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
#define SF_CTRL_SF_IF_INT_CLR             SF_CTRL_SF_IF_INT_CLR
#define SF_CTRL_SF_IF_INT_CLR_POS         (17U)
#define SF_CTRL_SF_IF_INT_CLR_LEN         (1U)
#define SF_CTRL_SF_IF_INT_CLR_MSK         (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
#define SF_CTRL_SF_IF_INT_CLR_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
#define SF_CTRL_SF_IF_INT_SET             SF_CTRL_SF_IF_INT_SET
#define SF_CTRL_SF_IF_INT_SET_POS         (18U)
#define SF_CTRL_SF_IF_INT_SET_LEN         (1U)
#define SF_CTRL_SF_IF_INT_SET_MSK         (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
#define SF_CTRL_SF_IF_INT_SET_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
#define SF_CTRL_SF_AES_DLY_MODE           SF_CTRL_SF_AES_DLY_MODE
#define SF_CTRL_SF_AES_DLY_MODE_POS       (19U)
#define SF_CTRL_SF_AES_DLY_MODE_LEN       (1U)
#define SF_CTRL_SF_AES_DLY_MODE_MSK       (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)
#define SF_CTRL_SF_AES_DLY_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS))
#define SF_CTRL_SF_AES_DOUT_ENDIAN        SF_CTRL_SF_AES_DOUT_ENDIAN
#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS    (20U)
#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN    (1U)
#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK    (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK   (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
#define SF_CTRL_SF_AES_CTR_PLUS_EN        SF_CTRL_SF_AES_CTR_PLUS_EN
#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS    (21U)
#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN    (1U)
#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK    (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)
#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK   (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS))
#define SF_CTRL_SF_AES_KEY_ENDIAN         SF_CTRL_SF_AES_KEY_ENDIAN
#define SF_CTRL_SF_AES_KEY_ENDIAN_POS     (22U)
#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN     (1U)
#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK     (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK    (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
#define SF_CTRL_SF_AES_IV_ENDIAN          SF_CTRL_SF_AES_IV_ENDIAN
#define SF_CTRL_SF_AES_IV_ENDIAN_POS      (23U)
#define SF_CTRL_SF_AES_IV_ENDIAN_LEN      (1U)
#define SF_CTRL_SF_AES_IV_ENDIAN_MSK      (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK     (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
#define SF_CTRL_SF_ID                     SF_CTRL_SF_ID
#define SF_CTRL_SF_ID_POS                 (24U)
#define SF_CTRL_SF_ID_LEN                 (8U)
#define SF_CTRL_SF_ID_MSK                 (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
#define SF_CTRL_SF_ID_UMSK                (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))

/* 0x4 : sf_ctrl_1 */
#define SF_CTRL_1_OFFSET                (0x4)
#define SF_CTRL_SF_IF_SR_PAT_MASK       SF_CTRL_SF_IF_SR_PAT_MASK
#define SF_CTRL_SF_IF_SR_PAT_MASK_POS   (0U)
#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN   (8U)
#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK   (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK  (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
#define SF_CTRL_SF_IF_SR_PAT            SF_CTRL_SF_IF_SR_PAT
#define SF_CTRL_SF_IF_SR_PAT_POS        (8U)
#define SF_CTRL_SF_IF_SR_PAT_LEN        (8U)
#define SF_CTRL_SF_IF_SR_PAT_MSK        (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
#define SF_CTRL_SF_IF_SR_PAT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
#define SF_CTRL_SF_IF_SR_INT            SF_CTRL_SF_IF_SR_INT
#define SF_CTRL_SF_IF_SR_INT_POS        (16U)
#define SF_CTRL_SF_IF_SR_INT_LEN        (1U)
#define SF_CTRL_SF_IF_SR_INT_MSK        (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
#define SF_CTRL_SF_IF_SR_INT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
#define SF_CTRL_SF_IF_SR_INT_EN         SF_CTRL_SF_IF_SR_INT_EN
#define SF_CTRL_SF_IF_SR_INT_EN_POS     (17U)
#define SF_CTRL_SF_IF_SR_INT_EN_LEN     (1U)
#define SF_CTRL_SF_IF_SR_INT_EN_MSK     (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
#define SF_CTRL_SF_IF_SR_INT_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
#define SF_CTRL_SF_IF_SR_INT_SET        SF_CTRL_SF_IF_SR_INT_SET
#define SF_CTRL_SF_IF_SR_INT_SET_POS    (18U)
#define SF_CTRL_SF_IF_SR_INT_SET_LEN    (1U)
#define SF_CTRL_SF_IF_SR_INT_SET_MSK    (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
#define SF_CTRL_SF_IF_SR_INT_SET_UMSK   (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
#define SF_CTRL_SF_IF_0_ACK_LAT         SF_CTRL_SF_IF_0_ACK_LAT
#define SF_CTRL_SF_IF_0_ACK_LAT_POS     (20U)
#define SF_CTRL_SF_IF_0_ACK_LAT_LEN     (3U)
#define SF_CTRL_SF_IF_0_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
#define SF_CTRL_SF_IF_REG_HOLD          SF_CTRL_SF_IF_REG_HOLD
#define SF_CTRL_SF_IF_REG_HOLD_POS      (24U)
#define SF_CTRL_SF_IF_REG_HOLD_LEN      (1U)
#define SF_CTRL_SF_IF_REG_HOLD_MSK      (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
#define SF_CTRL_SF_IF_REG_HOLD_UMSK     (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
#define SF_CTRL_SF_IF_REG_WP            SF_CTRL_SF_IF_REG_WP
#define SF_CTRL_SF_IF_REG_WP_POS        (25U)
#define SF_CTRL_SF_IF_REG_WP_LEN        (1U)
#define SF_CTRL_SF_IF_REG_WP_MSK        (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
#define SF_CTRL_SF_IF_REG_WP_UMSK       (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
#define SF_CTRL_SF_AHB2SIF_STOPPED      SF_CTRL_SF_AHB2SIF_STOPPED
#define SF_CTRL_SF_AHB2SIF_STOPPED_POS  (26U)
#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN  (1U)
#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK  (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
#define SF_CTRL_SF_AHB2SIF_STOP         SF_CTRL_SF_AHB2SIF_STOP
#define SF_CTRL_SF_AHB2SIF_STOP_POS     (27U)
#define SF_CTRL_SF_AHB2SIF_STOP_LEN     (1U)
#define SF_CTRL_SF_AHB2SIF_STOP_MSK     (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
#define SF_CTRL_SF_AHB2SIF_STOP_UMSK    (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
#define SF_CTRL_SF_IF_FN_SEL            SF_CTRL_SF_IF_FN_SEL
#define SF_CTRL_SF_IF_FN_SEL_POS        (28U)
#define SF_CTRL_SF_IF_FN_SEL_LEN        (1U)
#define SF_CTRL_SF_IF_FN_SEL_MSK        (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
#define SF_CTRL_SF_IF_FN_SEL_UMSK       (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
#define SF_CTRL_SF_IF_EN                SF_CTRL_SF_IF_EN
#define SF_CTRL_SF_IF_EN_POS            (29U)
#define SF_CTRL_SF_IF_EN_LEN            (1U)
#define SF_CTRL_SF_IF_EN_MSK            (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
#define SF_CTRL_SF_IF_EN_UMSK           (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
#define SF_CTRL_SF_AHB2SIF_EN           SF_CTRL_SF_AHB2SIF_EN
#define SF_CTRL_SF_AHB2SIF_EN_POS       (30U)
#define SF_CTRL_SF_AHB2SIF_EN_LEN       (1U)
#define SF_CTRL_SF_AHB2SIF_EN_MSK       (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
#define SF_CTRL_SF_AHB2SIF_EN_UMSK      (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
#define SF_CTRL_SF_AHB2SRAM_EN          SF_CTRL_SF_AHB2SRAM_EN
#define SF_CTRL_SF_AHB2SRAM_EN_POS      (31U)
#define SF_CTRL_SF_AHB2SRAM_EN_LEN      (1U)
#define SF_CTRL_SF_AHB2SRAM_EN_MSK      (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
#define SF_CTRL_SF_AHB2SRAM_EN_UMSK     (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))

/* 0x8 : sf_if_sahb_0 */
#define SF_CTRL_SF_IF_SAHB_0_OFFSET      (0x8)
#define SF_CTRL_SF_IF_BUSY               SF_CTRL_SF_IF_BUSY
#define SF_CTRL_SF_IF_BUSY_POS           (0U)
#define SF_CTRL_SF_IF_BUSY_LEN           (1U)
#define SF_CTRL_SF_IF_BUSY_MSK           (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
#define SF_CTRL_SF_IF_BUSY_UMSK          (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
#define SF_CTRL_SF_IF_0_TRIG             SF_CTRL_SF_IF_0_TRIG
#define SF_CTRL_SF_IF_0_TRIG_POS         (1U)
#define SF_CTRL_SF_IF_0_TRIG_LEN         (1U)
#define SF_CTRL_SF_IF_0_TRIG_MSK         (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
#define SF_CTRL_SF_IF_0_TRIG_UMSK        (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
#define SF_CTRL_SF_IF_0_DAT_BYTE         SF_CTRL_SF_IF_0_DAT_BYTE
#define SF_CTRL_SF_IF_0_DAT_BYTE_POS     (2U)
#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN     (10U)
#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
#define SF_CTRL_SF_IF_0_DMY_BYTE         SF_CTRL_SF_IF_0_DMY_BYTE
#define SF_CTRL_SF_IF_0_DMY_BYTE_POS     (12U)
#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN     (5U)
#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
#define SF_CTRL_SF_IF_0_ADR_BYTE         SF_CTRL_SF_IF_0_ADR_BYTE
#define SF_CTRL_SF_IF_0_ADR_BYTE_POS     (17U)
#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
#define SF_CTRL_SF_IF_0_CMD_BYTE         SF_CTRL_SF_IF_0_CMD_BYTE
#define SF_CTRL_SF_IF_0_CMD_BYTE_POS     (20U)
#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
#define SF_CTRL_SF_IF_0_DAT_RW           SF_CTRL_SF_IF_0_DAT_RW
#define SF_CTRL_SF_IF_0_DAT_RW_POS       (23U)
#define SF_CTRL_SF_IF_0_DAT_RW_LEN       (1U)
#define SF_CTRL_SF_IF_0_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
#define SF_CTRL_SF_IF_0_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
#define SF_CTRL_SF_IF_0_DAT_EN           SF_CTRL_SF_IF_0_DAT_EN
#define SF_CTRL_SF_IF_0_DAT_EN_POS       (24U)
#define SF_CTRL_SF_IF_0_DAT_EN_LEN       (1U)
#define SF_CTRL_SF_IF_0_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
#define SF_CTRL_SF_IF_0_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
#define SF_CTRL_SF_IF_0_DMY_EN           SF_CTRL_SF_IF_0_DMY_EN
#define SF_CTRL_SF_IF_0_DMY_EN_POS       (25U)
#define SF_CTRL_SF_IF_0_DMY_EN_LEN       (1U)
#define SF_CTRL_SF_IF_0_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
#define SF_CTRL_SF_IF_0_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
#define SF_CTRL_SF_IF_0_ADR_EN           SF_CTRL_SF_IF_0_ADR_EN
#define SF_CTRL_SF_IF_0_ADR_EN_POS       (26U)
#define SF_CTRL_SF_IF_0_ADR_EN_LEN       (1U)
#define SF_CTRL_SF_IF_0_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
#define SF_CTRL_SF_IF_0_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
#define SF_CTRL_SF_IF_0_CMD_EN           SF_CTRL_SF_IF_0_CMD_EN
#define SF_CTRL_SF_IF_0_CMD_EN_POS       (27U)
#define SF_CTRL_SF_IF_0_CMD_EN_LEN       (1U)
#define SF_CTRL_SF_IF_0_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
#define SF_CTRL_SF_IF_0_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
#define SF_CTRL_SF_IF_0_SPI_MODE         SF_CTRL_SF_IF_0_SPI_MODE
#define SF_CTRL_SF_IF_0_SPI_MODE_POS     (28U)
#define SF_CTRL_SF_IF_0_SPI_MODE_LEN     (3U)
#define SF_CTRL_SF_IF_0_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
#define SF_CTRL_SF_IF_0_QPI_MODE_EN      SF_CTRL_SF_IF_0_QPI_MODE_EN
#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS  (31U)
#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN  (1U)
#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))

/* 0xC : sf_if_sahb_1 */
#define SF_CTRL_SF_IF_SAHB_1_OFFSET    (0xC)
#define SF_CTRL_SF_IF_0_CMD_BUF_0      SF_CTRL_SF_IF_0_CMD_BUF_0
#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS  (0U)
#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN  (32U)
#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))

/* 0x10 : sf_if_sahb_2 */
#define SF_CTRL_SF_IF_SAHB_2_OFFSET    (0x10)
#define SF_CTRL_SF_IF_0_CMD_BUF_1      SF_CTRL_SF_IF_0_CMD_BUF_1
#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS  (0U)
#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN  (32U)
#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))

/* 0x14 : sf_if_iahb_0 */
#define SF_CTRL_SF_IF_IAHB_0_OFFSET      (0x14)
#define SF_CTRL_SF_IF_1_DMY_BYTE         SF_CTRL_SF_IF_1_DMY_BYTE
#define SF_CTRL_SF_IF_1_DMY_BYTE_POS     (12U)
#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN     (5U)
#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
#define SF_CTRL_SF_IF_1_ADR_BYTE         SF_CTRL_SF_IF_1_ADR_BYTE
#define SF_CTRL_SF_IF_1_ADR_BYTE_POS     (17U)
#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
#define SF_CTRL_SF_IF_1_CMD_BYTE         SF_CTRL_SF_IF_1_CMD_BYTE
#define SF_CTRL_SF_IF_1_CMD_BYTE_POS     (20U)
#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
#define SF_CTRL_SF_IF_1_DAT_RW           SF_CTRL_SF_IF_1_DAT_RW
#define SF_CTRL_SF_IF_1_DAT_RW_POS       (23U)
#define SF_CTRL_SF_IF_1_DAT_RW_LEN       (1U)
#define SF_CTRL_SF_IF_1_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
#define SF_CTRL_SF_IF_1_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
#define SF_CTRL_SF_IF_1_DAT_EN           SF_CTRL_SF_IF_1_DAT_EN
#define SF_CTRL_SF_IF_1_DAT_EN_POS       (24U)
#define SF_CTRL_SF_IF_1_DAT_EN_LEN       (1U)
#define SF_CTRL_SF_IF_1_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
#define SF_CTRL_SF_IF_1_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
#define SF_CTRL_SF_IF_1_DMY_EN           SF_CTRL_SF_IF_1_DMY_EN
#define SF_CTRL_SF_IF_1_DMY_EN_POS       (25U)
#define SF_CTRL_SF_IF_1_DMY_EN_LEN       (1U)
#define SF_CTRL_SF_IF_1_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
#define SF_CTRL_SF_IF_1_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
#define SF_CTRL_SF_IF_1_ADR_EN           SF_CTRL_SF_IF_1_ADR_EN
#define SF_CTRL_SF_IF_1_ADR_EN_POS       (26U)
#define SF_CTRL_SF_IF_1_ADR_EN_LEN       (1U)
#define SF_CTRL_SF_IF_1_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
#define SF_CTRL_SF_IF_1_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
#define SF_CTRL_SF_IF_1_CMD_EN           SF_CTRL_SF_IF_1_CMD_EN
#define SF_CTRL_SF_IF_1_CMD_EN_POS       (27U)
#define SF_CTRL_SF_IF_1_CMD_EN_LEN       (1U)
#define SF_CTRL_SF_IF_1_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
#define SF_CTRL_SF_IF_1_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
#define SF_CTRL_SF_IF_1_SPI_MODE         SF_CTRL_SF_IF_1_SPI_MODE
#define SF_CTRL_SF_IF_1_SPI_MODE_POS     (28U)
#define SF_CTRL_SF_IF_1_SPI_MODE_LEN     (3U)
#define SF_CTRL_SF_IF_1_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
#define SF_CTRL_SF_IF_1_QPI_MODE_EN      SF_CTRL_SF_IF_1_QPI_MODE_EN
#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS  (31U)
#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN  (1U)
#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))

/* 0x18 : sf_if_iahb_1 */
#define SF_CTRL_SF_IF_IAHB_1_OFFSET    (0x18)
#define SF_CTRL_SF_IF_1_CMD_BUF_0      SF_CTRL_SF_IF_1_CMD_BUF_0
#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS  (0U)
#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN  (32U)
#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))

/* 0x1C : sf_if_iahb_2 */
#define SF_CTRL_SF_IF_IAHB_2_OFFSET    (0x1C)
#define SF_CTRL_SF_IF_1_CMD_BUF_1      SF_CTRL_SF_IF_1_CMD_BUF_1
#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS  (0U)
#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN  (32U)
#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))

/* 0x20 : sf_if_status_0 */
#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
#define SF_CTRL_SF_IF_STATUS_0        SF_CTRL_SF_IF_STATUS_0
#define SF_CTRL_SF_IF_STATUS_0_POS    (0U)
#define SF_CTRL_SF_IF_STATUS_0_LEN    (32U)
#define SF_CTRL_SF_IF_STATUS_0_MSK    (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
#define SF_CTRL_SF_IF_STATUS_0_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))

/* 0x24 : sf_if_status_1 */
#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
#define SF_CTRL_SF_IF_STATUS_1        SF_CTRL_SF_IF_STATUS_1
#define SF_CTRL_SF_IF_STATUS_1_POS    (0U)
#define SF_CTRL_SF_IF_STATUS_1_LEN    (32U)
#define SF_CTRL_SF_IF_STATUS_1_MSK    (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
#define SF_CTRL_SF_IF_STATUS_1_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))

/* 0x28 : sf_aes */
#define SF_CTRL_SF_AES_OFFSET         (0x28)
#define SF_CTRL_SF_AES_EN             SF_CTRL_SF_AES_EN
#define SF_CTRL_SF_AES_EN_POS         (0U)
#define SF_CTRL_SF_AES_EN_LEN         (1U)
#define SF_CTRL_SF_AES_EN_MSK         (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
#define SF_CTRL_SF_AES_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
#define SF_CTRL_SF_AES_MODE           SF_CTRL_SF_AES_MODE
#define SF_CTRL_SF_AES_MODE_POS       (1U)
#define SF_CTRL_SF_AES_MODE_LEN       (2U)
#define SF_CTRL_SF_AES_MODE_MSK       (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
#define SF_CTRL_SF_AES_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
#define SF_CTRL_SF_AES_PREF_TRIG      SF_CTRL_SF_AES_PREF_TRIG
#define SF_CTRL_SF_AES_PREF_TRIG_POS  (3U)
#define SF_CTRL_SF_AES_PREF_TRIG_LEN  (1U)
#define SF_CTRL_SF_AES_PREF_TRIG_MSK  (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)
#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS))
#define SF_CTRL_SF_AES_PREF_BUSY      SF_CTRL_SF_AES_PREF_BUSY
#define SF_CTRL_SF_AES_PREF_BUSY_POS  (4U)
#define SF_CTRL_SF_AES_PREF_BUSY_LEN  (1U)
#define SF_CTRL_SF_AES_PREF_BUSY_MSK  (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)
#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS))
#define SF_CTRL_SF_AES_STATUS         SF_CTRL_SF_AES_STATUS
#define SF_CTRL_SF_AES_STATUS_POS     (5U)
#define SF_CTRL_SF_AES_STATUS_LEN     (27U)
#define SF_CTRL_SF_AES_STATUS_MSK     (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
#define SF_CTRL_SF_AES_STATUS_UMSK    (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))

/* 0x2C : sf_ahb2sif_status */
#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
#define SF_CTRL_SF_AHB2SIF_STATUS        SF_CTRL_SF_AHB2SIF_STATUS
#define SF_CTRL_SF_AHB2SIF_STATUS_POS    (0U)
#define SF_CTRL_SF_AHB2SIF_STATUS_LEN    (32U)
#define SF_CTRL_SF_AHB2SIF_STATUS_MSK    (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK   (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))

/* 0x30 : sf_if_io_dly_0 */
#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET   (0x30)
#define SF_CTRL_SF_CS_DLY_SEL           SF_CTRL_SF_CS_DLY_SEL
#define SF_CTRL_SF_CS_DLY_SEL_POS       (0U)
#define SF_CTRL_SF_CS_DLY_SEL_LEN       (2U)
#define SF_CTRL_SF_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
#define SF_CTRL_SF_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
#define SF_CTRL_SF_CS2_DLY_SEL          SF_CTRL_SF_CS2_DLY_SEL
#define SF_CTRL_SF_CS2_DLY_SEL_POS      (2U)
#define SF_CTRL_SF_CS2_DLY_SEL_LEN      (2U)
#define SF_CTRL_SF_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)
#define SF_CTRL_SF_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS))
#define SF_CTRL_SF_CLK_OUT_DLY_SEL      SF_CTRL_SF_CLK_OUT_DLY_SEL
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS  (8U)
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
#define SF_CTRL_SF_DQS_OE_DLY_SEL       SF_CTRL_SF_DQS_OE_DLY_SEL
#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS   (26U)
#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
#define SF_CTRL_SF_DQS_DI_DLY_SEL       SF_CTRL_SF_DQS_DI_DLY_SEL
#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS   (28U)
#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
#define SF_CTRL_SF_DQS_DO_DLY_SEL       SF_CTRL_SF_DQS_DO_DLY_SEL
#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS   (30U)
#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))

/* 0x34 : sf_if_io_dly_1 */
#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET   (0x34)
#define SF_CTRL_SF_IO_0_OE_DLY_SEL      SF_CTRL_SF_IO_0_OE_DLY_SEL
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
#define SF_CTRL_SF_IO_0_DI_DLY_SEL      SF_CTRL_SF_IO_0_DI_DLY_SEL
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
#define SF_CTRL_SF_IO_0_DO_DLY_SEL      SF_CTRL_SF_IO_0_DO_DLY_SEL
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))

/* 0x38 : sf_if_io_dly_2 */
#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET   (0x38)
#define SF_CTRL_SF_IO_1_OE_DLY_SEL      SF_CTRL_SF_IO_1_OE_DLY_SEL
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
#define SF_CTRL_SF_IO_1_DI_DLY_SEL      SF_CTRL_SF_IO_1_DI_DLY_SEL
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
#define SF_CTRL_SF_IO_1_DO_DLY_SEL      SF_CTRL_SF_IO_1_DO_DLY_SEL
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))

/* 0x3C : sf_if_io_dly_3 */
#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET   (0x3C)
#define SF_CTRL_SF_IO_2_OE_DLY_SEL      SF_CTRL_SF_IO_2_OE_DLY_SEL
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
#define SF_CTRL_SF_IO_2_DI_DLY_SEL      SF_CTRL_SF_IO_2_DI_DLY_SEL
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
#define SF_CTRL_SF_IO_2_DO_DLY_SEL      SF_CTRL_SF_IO_2_DO_DLY_SEL
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))

/* 0x40 : sf_if_io_dly_4 */
#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET   (0x40)
#define SF_CTRL_SF_IO_3_OE_DLY_SEL      SF_CTRL_SF_IO_3_OE_DLY_SEL
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
#define SF_CTRL_SF_IO_3_DI_DLY_SEL      SF_CTRL_SF_IO_3_DI_DLY_SEL
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
#define SF_CTRL_SF_IO_3_DO_DLY_SEL      SF_CTRL_SF_IO_3_DO_DLY_SEL
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))

/* 0x44 : sf_reserved */
#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
#define SF_CTRL_SF_RESERVED        SF_CTRL_SF_RESERVED
#define SF_CTRL_SF_RESERVED_POS    (0U)
#define SF_CTRL_SF_RESERVED_LEN    (32U)
#define SF_CTRL_SF_RESERVED_MSK    (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
#define SF_CTRL_SF_RESERVED_UMSK   (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))

/* 0x48 : sf2_if_io_dly_0 */
#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET   (0x48)
#define SF_CTRL_SF2_CS_DLY_SEL           SF_CTRL_SF2_CS_DLY_SEL
#define SF_CTRL_SF2_CS_DLY_SEL_POS       (0U)
#define SF_CTRL_SF2_CS_DLY_SEL_LEN       (2U)
#define SF_CTRL_SF2_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
#define SF_CTRL_SF2_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
#define SF_CTRL_SF2_CS2_DLY_SEL          SF_CTRL_SF2_CS2_DLY_SEL
#define SF_CTRL_SF2_CS2_DLY_SEL_POS      (2U)
#define SF_CTRL_SF2_CS2_DLY_SEL_LEN      (2U)
#define SF_CTRL_SF2_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)
#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS))
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL      SF_CTRL_SF2_CLK_OUT_DLY_SEL
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS  (8U)
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
#define SF_CTRL_SF2_DQS_OE_DLY_SEL       SF_CTRL_SF2_DQS_OE_DLY_SEL
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS   (26U)
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
#define SF_CTRL_SF2_DQS_DI_DLY_SEL       SF_CTRL_SF2_DQS_DI_DLY_SEL
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS   (28U)
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
#define SF_CTRL_SF2_DQS_DO_DLY_SEL       SF_CTRL_SF2_DQS_DO_DLY_SEL
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS   (30U)
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))

/* 0x4C : sf2_if_io_dly_1 */
#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET   (0x4C)
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL      SF_CTRL_SF2_IO_0_OE_DLY_SEL
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL      SF_CTRL_SF2_IO_0_DI_DLY_SEL
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL      SF_CTRL_SF2_IO_0_DO_DLY_SEL
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))

/* 0x50 : sf2_if_io_dly_2 */
#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET   (0x50)
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL      SF_CTRL_SF2_IO_1_OE_DLY_SEL
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL      SF_CTRL_SF2_IO_1_DI_DLY_SEL
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL      SF_CTRL_SF2_IO_1_DO_DLY_SEL
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))

/* 0x54 : sf2_if_io_dly_3 */
#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET   (0x54)
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL      SF_CTRL_SF2_IO_2_OE_DLY_SEL
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL      SF_CTRL_SF2_IO_2_DI_DLY_SEL
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL      SF_CTRL_SF2_IO_2_DO_DLY_SEL
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))

/* 0x58 : sf2_if_io_dly_4 */
#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET   (0x58)
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL      SF_CTRL_SF2_IO_3_OE_DLY_SEL
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL      SF_CTRL_SF2_IO_3_DI_DLY_SEL
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL      SF_CTRL_SF2_IO_3_DO_DLY_SEL
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))

/* 0x5C : sf3_if_io_dly_0 */
#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET   (0x5C)
#define SF_CTRL_SF3_CS_DLY_SEL           SF_CTRL_SF3_CS_DLY_SEL
#define SF_CTRL_SF3_CS_DLY_SEL_POS       (0U)
#define SF_CTRL_SF3_CS_DLY_SEL_LEN       (2U)
#define SF_CTRL_SF3_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
#define SF_CTRL_SF3_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
#define SF_CTRL_SF3_CS2_DLY_SEL          SF_CTRL_SF3_CS2_DLY_SEL
#define SF_CTRL_SF3_CS2_DLY_SEL_POS      (2U)
#define SF_CTRL_SF3_CS2_DLY_SEL_LEN      (2U)
#define SF_CTRL_SF3_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)
#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS))
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL      SF_CTRL_SF3_CLK_OUT_DLY_SEL
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS  (8U)
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
#define SF_CTRL_SF3_DQS_OE_DLY_SEL       SF_CTRL_SF3_DQS_OE_DLY_SEL
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS   (26U)
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
#define SF_CTRL_SF3_DQS_DI_DLY_SEL       SF_CTRL_SF3_DQS_DI_DLY_SEL
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS   (28U)
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
#define SF_CTRL_SF3_DQS_DO_DLY_SEL       SF_CTRL_SF3_DQS_DO_DLY_SEL
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS   (30U)
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN   (2U)
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))

/* 0x60 : sf3_if_io_dly_1 */
#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET   (0x60)
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL      SF_CTRL_SF3_IO_0_OE_DLY_SEL
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL      SF_CTRL_SF3_IO_0_DI_DLY_SEL
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL      SF_CTRL_SF3_IO_0_DO_DLY_SEL
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))

/* 0x64 : sf3_if_io_dly_2 */
#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET   (0x64)
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL      SF_CTRL_SF3_IO_1_OE_DLY_SEL
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL      SF_CTRL_SF3_IO_1_DI_DLY_SEL
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL      SF_CTRL_SF3_IO_1_DO_DLY_SEL
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))

/* 0x68 : sf3_if_io_dly_3 */
#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET   (0x68)
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL      SF_CTRL_SF3_IO_2_OE_DLY_SEL
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL      SF_CTRL_SF3_IO_2_DI_DLY_SEL
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL      SF_CTRL_SF3_IO_2_DO_DLY_SEL
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))

/* 0x6C : sf3_if_io_dly_4 */
#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET   (0x6C)
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL      SF_CTRL_SF3_IO_3_OE_DLY_SEL
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS  (0U)
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL      SF_CTRL_SF3_IO_3_DI_DLY_SEL
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS  (8U)
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL      SF_CTRL_SF3_IO_3_DO_DLY_SEL
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS  (16U)
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN  (2U)
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))

/* 0x70 : sf_ctrl_2 */
#define SF_CTRL_2_OFFSET                (0x70)
#define SF_CTRL_SF_IF_PAD_SEL           SF_CTRL_SF_IF_PAD_SEL
#define SF_CTRL_SF_IF_PAD_SEL_POS       (0U)
#define SF_CTRL_SF_IF_PAD_SEL_LEN       (2U)
#define SF_CTRL_SF_IF_PAD_SEL_MSK       (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
#define SF_CTRL_SF_IF_PAD_SEL_UMSK      (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
#define SF_CTRL_SF_IF_PAD_SEL_LOCK      SF_CTRL_SF_IF_PAD_SEL_LOCK
#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS  (3U)
#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN  (1U)
#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK  (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
#define SF_CTRL_SF_IF_DTR_EN            SF_CTRL_SF_IF_DTR_EN
#define SF_CTRL_SF_IF_DTR_EN_POS        (4U)
#define SF_CTRL_SF_IF_DTR_EN_LEN        (1U)
#define SF_CTRL_SF_IF_DTR_EN_MSK        (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
#define SF_CTRL_SF_IF_DTR_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
#define SF_CTRL_SF_IF_DQS_EN            SF_CTRL_SF_IF_DQS_EN
#define SF_CTRL_SF_IF_DQS_EN_POS        (5U)
#define SF_CTRL_SF_IF_DQS_EN_LEN        (1U)
#define SF_CTRL_SF_IF_DQS_EN_MSK        (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
#define SF_CTRL_SF_IF_DQS_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
#define SF_CTRL_SF_IF_BK_SWAP           SF_CTRL_SF_IF_BK_SWAP
#define SF_CTRL_SF_IF_BK_SWAP_POS       (28U)
#define SF_CTRL_SF_IF_BK_SWAP_LEN       (1U)
#define SF_CTRL_SF_IF_BK_SWAP_MSK       (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)
#define SF_CTRL_SF_IF_BK_SWAP_UMSK      (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS))
#define SF_CTRL_SF_IF_BK2_MODE          SF_CTRL_SF_IF_BK2_MODE
#define SF_CTRL_SF_IF_BK2_MODE_POS      (29U)
#define SF_CTRL_SF_IF_BK2_MODE_LEN      (1U)
#define SF_CTRL_SF_IF_BK2_MODE_MSK      (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)
#define SF_CTRL_SF_IF_BK2_MODE_UMSK     (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS))
#define SF_CTRL_SF_IF_BK2_EN            SF_CTRL_SF_IF_BK2_EN
#define SF_CTRL_SF_IF_BK2_EN_POS        (30U)
#define SF_CTRL_SF_IF_BK2_EN_LEN        (1U)
#define SF_CTRL_SF_IF_BK2_EN_MSK        (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)
#define SF_CTRL_SF_IF_BK2_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS))
#define SF_CTRL_SF_IF_0_BK_SEL          SF_CTRL_SF_IF_0_BK_SEL
#define SF_CTRL_SF_IF_0_BK_SEL_POS      (31U)
#define SF_CTRL_SF_IF_0_BK_SEL_LEN      (1U)
#define SF_CTRL_SF_IF_0_BK_SEL_MSK      (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)
#define SF_CTRL_SF_IF_0_BK_SEL_UMSK     (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS))

/* 0x74 : sf_ctrl_3 */
#define SF_CTRL_3_OFFSET                (0x74)
#define SF_CTRL_SF_CMDS_WRAP_LEN        SF_CTRL_SF_CMDS_WRAP_LEN
#define SF_CTRL_SF_CMDS_WRAP_LEN_POS    (0U)
#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN    (4U)
#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK    (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)
#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK   (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS))
#define SF_CTRL_SF_CMDS_EN              SF_CTRL_SF_CMDS_EN
#define SF_CTRL_SF_CMDS_EN_POS          (4U)
#define SF_CTRL_SF_CMDS_EN_LEN          (1U)
#define SF_CTRL_SF_CMDS_EN_MSK          (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)
#define SF_CTRL_SF_CMDS_EN_UMSK         (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS))
#define SF_CTRL_SF_CMDS_BT_DLY          SF_CTRL_SF_CMDS_BT_DLY
#define SF_CTRL_SF_CMDS_BT_DLY_POS      (5U)
#define SF_CTRL_SF_CMDS_BT_DLY_LEN      (3U)
#define SF_CTRL_SF_CMDS_BT_DLY_MSK      (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)
#define SF_CTRL_SF_CMDS_BT_DLY_UMSK     (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS))
#define SF_CTRL_SF_CMDS_BT_EN           SF_CTRL_SF_CMDS_BT_EN
#define SF_CTRL_SF_CMDS_BT_EN_POS       (8U)
#define SF_CTRL_SF_CMDS_BT_EN_LEN       (1U)
#define SF_CTRL_SF_CMDS_BT_EN_MSK       (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)
#define SF_CTRL_SF_CMDS_BT_EN_UMSK      (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS))
#define SF_CTRL_SF_CMDS_WRAP_Q_INI      SF_CTRL_SF_CMDS_WRAP_Q_INI
#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS  (9U)
#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN  (1U)
#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK  (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)
#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS))
#define SF_CTRL_SF_CMDS_WRAP_MODE       SF_CTRL_SF_CMDS_WRAP_MODE
#define SF_CTRL_SF_CMDS_WRAP_MODE_POS   (10U)
#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN   (1U)
#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK   (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)
#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK  (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS))
#define SF_CTRL_SF_CMDS_WRAP_Q          SF_CTRL_SF_CMDS_WRAP_Q
#define SF_CTRL_SF_CMDS_WRAP_Q_POS      (11U)
#define SF_CTRL_SF_CMDS_WRAP_Q_LEN      (1U)
#define SF_CTRL_SF_CMDS_WRAP_Q_MSK      (((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS)
#define SF_CTRL_SF_CMDS_WRAP_Q_UMSK     (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS))
#define SF_CTRL_SF_IF_1_ACK_LAT         SF_CTRL_SF_IF_1_ACK_LAT
#define SF_CTRL_SF_IF_1_ACK_LAT_POS     (29U)
#define SF_CTRL_SF_IF_1_ACK_LAT_LEN     (3U)
#define SF_CTRL_SF_IF_1_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))

/* 0x78 : sf_if_iahb_3 */
#define SF_CTRL_SF_IF_IAHB_3_OFFSET      (0x78)
#define SF_CTRL_SF_IF_2_DMY_BYTE         SF_CTRL_SF_IF_2_DMY_BYTE
#define SF_CTRL_SF_IF_2_DMY_BYTE_POS     (12U)
#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN     (5U)
#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
#define SF_CTRL_SF_IF_2_ADR_BYTE         SF_CTRL_SF_IF_2_ADR_BYTE
#define SF_CTRL_SF_IF_2_ADR_BYTE_POS     (17U)
#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
#define SF_CTRL_SF_IF_2_CMD_BYTE         SF_CTRL_SF_IF_2_CMD_BYTE
#define SF_CTRL_SF_IF_2_CMD_BYTE_POS     (20U)
#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
#define SF_CTRL_SF_IF_2_DAT_RW           SF_CTRL_SF_IF_2_DAT_RW
#define SF_CTRL_SF_IF_2_DAT_RW_POS       (23U)
#define SF_CTRL_SF_IF_2_DAT_RW_LEN       (1U)
#define SF_CTRL_SF_IF_2_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
#define SF_CTRL_SF_IF_2_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
#define SF_CTRL_SF_IF_2_DAT_EN           SF_CTRL_SF_IF_2_DAT_EN
#define SF_CTRL_SF_IF_2_DAT_EN_POS       (24U)
#define SF_CTRL_SF_IF_2_DAT_EN_LEN       (1U)
#define SF_CTRL_SF_IF_2_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
#define SF_CTRL_SF_IF_2_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
#define SF_CTRL_SF_IF_2_DMY_EN           SF_CTRL_SF_IF_2_DMY_EN
#define SF_CTRL_SF_IF_2_DMY_EN_POS       (25U)
#define SF_CTRL_SF_IF_2_DMY_EN_LEN       (1U)
#define SF_CTRL_SF_IF_2_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
#define SF_CTRL_SF_IF_2_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
#define SF_CTRL_SF_IF_2_ADR_EN           SF_CTRL_SF_IF_2_ADR_EN
#define SF_CTRL_SF_IF_2_ADR_EN_POS       (26U)
#define SF_CTRL_SF_IF_2_ADR_EN_LEN       (1U)
#define SF_CTRL_SF_IF_2_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
#define SF_CTRL_SF_IF_2_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
#define SF_CTRL_SF_IF_2_CMD_EN           SF_CTRL_SF_IF_2_CMD_EN
#define SF_CTRL_SF_IF_2_CMD_EN_POS       (27U)
#define SF_CTRL_SF_IF_2_CMD_EN_LEN       (1U)
#define SF_CTRL_SF_IF_2_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
#define SF_CTRL_SF_IF_2_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
#define SF_CTRL_SF_IF_2_SPI_MODE         SF_CTRL_SF_IF_2_SPI_MODE
#define SF_CTRL_SF_IF_2_SPI_MODE_POS     (28U)
#define SF_CTRL_SF_IF_2_SPI_MODE_LEN     (3U)
#define SF_CTRL_SF_IF_2_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
#define SF_CTRL_SF_IF_2_QPI_MODE_EN      SF_CTRL_SF_IF_2_QPI_MODE_EN
#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS  (31U)
#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN  (1U)
#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))

/* 0x7C : sf_if_iahb_4 */
#define SF_CTRL_SF_IF_IAHB_4_OFFSET    (0x7C)
#define SF_CTRL_SF_IF_2_CMD_BUF_0      SF_CTRL_SF_IF_2_CMD_BUF_0
#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS  (0U)
#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN  (32U)
#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))

/* 0x80 : sf_if_iahb_5 */
#define SF_CTRL_SF_IF_IAHB_5_OFFSET    (0x80)
#define SF_CTRL_SF_IF_2_CMD_BUF_1      SF_CTRL_SF_IF_2_CMD_BUF_1
#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS  (0U)
#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN  (32U)
#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))

/* 0x84 : sf_if_iahb_6 */
#define SF_CTRL_SF_IF_IAHB_6_OFFSET      (0x84)
#define SF_CTRL_SF_IF_3_ADR_BYTE         SF_CTRL_SF_IF_3_ADR_BYTE
#define SF_CTRL_SF_IF_3_ADR_BYTE_POS     (17U)
#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)
#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS))
#define SF_CTRL_SF_IF_3_CMD_BYTE         SF_CTRL_SF_IF_3_CMD_BYTE
#define SF_CTRL_SF_IF_3_CMD_BYTE_POS     (20U)
#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
#define SF_CTRL_SF_IF_3_ADR_EN           SF_CTRL_SF_IF_3_ADR_EN
#define SF_CTRL_SF_IF_3_ADR_EN_POS       (26U)
#define SF_CTRL_SF_IF_3_ADR_EN_LEN       (1U)
#define SF_CTRL_SF_IF_3_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)
#define SF_CTRL_SF_IF_3_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS))
#define SF_CTRL_SF_IF_3_CMD_EN           SF_CTRL_SF_IF_3_CMD_EN
#define SF_CTRL_SF_IF_3_CMD_EN_POS       (27U)
#define SF_CTRL_SF_IF_3_CMD_EN_LEN       (1U)
#define SF_CTRL_SF_IF_3_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)
#define SF_CTRL_SF_IF_3_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS))
#define SF_CTRL_SF_IF_3_SPI_MODE         SF_CTRL_SF_IF_3_SPI_MODE
#define SF_CTRL_SF_IF_3_SPI_MODE_POS     (28U)
#define SF_CTRL_SF_IF_3_SPI_MODE_LEN     (3U)
#define SF_CTRL_SF_IF_3_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
#define SF_CTRL_SF_IF_3_QPI_MODE_EN      SF_CTRL_SF_IF_3_QPI_MODE_EN
#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS  (31U)
#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN  (1U)
#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))

/* 0x88 : sf_if_iahb_7 */
#define SF_CTRL_SF_IF_IAHB_7_OFFSET    (0x88)
#define SF_CTRL_SF_IF_3_CMD_BUF_0      SF_CTRL_SF_IF_3_CMD_BUF_0
#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS  (0U)
#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN  (32U)
#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))

/* 0x8C : sf_if_iahb_8 */
#define SF_CTRL_SF_IF_IAHB_8_OFFSET    (0x8C)
#define SF_CTRL_SF_IF_3_CMD_BUF_1      SF_CTRL_SF_IF_3_CMD_BUF_1
#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS  (0U)
#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN  (32U)
#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)
#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS))

/* 0x90 : sf_if_iahb_9 */
#define SF_CTRL_SF_IF_IAHB_9_OFFSET      (0x90)
#define SF_CTRL_SF_IF_4_DMY_BYTE         SF_CTRL_SF_IF_4_DMY_BYTE
#define SF_CTRL_SF_IF_4_DMY_BYTE_POS     (12U)
#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN     (5U)
#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)
#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS))
#define SF_CTRL_SF_IF_4_ADR_BYTE         SF_CTRL_SF_IF_4_ADR_BYTE
#define SF_CTRL_SF_IF_4_ADR_BYTE_POS     (17U)
#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)
#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS))
#define SF_CTRL_SF_IF_4_CMD_BYTE         SF_CTRL_SF_IF_4_CMD_BYTE
#define SF_CTRL_SF_IF_4_CMD_BYTE_POS     (20U)
#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN     (3U)
#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)
#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS))
#define SF_CTRL_SF_IF_4_DAT_RW           SF_CTRL_SF_IF_4_DAT_RW
#define SF_CTRL_SF_IF_4_DAT_RW_POS       (23U)
#define SF_CTRL_SF_IF_4_DAT_RW_LEN       (1U)
#define SF_CTRL_SF_IF_4_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)
#define SF_CTRL_SF_IF_4_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS))
#define SF_CTRL_SF_IF_4_DAT_EN           SF_CTRL_SF_IF_4_DAT_EN
#define SF_CTRL_SF_IF_4_DAT_EN_POS       (24U)
#define SF_CTRL_SF_IF_4_DAT_EN_LEN       (1U)
#define SF_CTRL_SF_IF_4_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)
#define SF_CTRL_SF_IF_4_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS))
#define SF_CTRL_SF_IF_4_DMY_EN           SF_CTRL_SF_IF_4_DMY_EN
#define SF_CTRL_SF_IF_4_DMY_EN_POS       (25U)
#define SF_CTRL_SF_IF_4_DMY_EN_LEN       (1U)
#define SF_CTRL_SF_IF_4_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)
#define SF_CTRL_SF_IF_4_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS))
#define SF_CTRL_SF_IF_4_ADR_EN           SF_CTRL_SF_IF_4_ADR_EN
#define SF_CTRL_SF_IF_4_ADR_EN_POS       (26U)
#define SF_CTRL_SF_IF_4_ADR_EN_LEN       (1U)
#define SF_CTRL_SF_IF_4_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)
#define SF_CTRL_SF_IF_4_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS))
#define SF_CTRL_SF_IF_4_CMD_EN           SF_CTRL_SF_IF_4_CMD_EN
#define SF_CTRL_SF_IF_4_CMD_EN_POS       (27U)
#define SF_CTRL_SF_IF_4_CMD_EN_LEN       (1U)
#define SF_CTRL_SF_IF_4_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)
#define SF_CTRL_SF_IF_4_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS))
#define SF_CTRL_SF_IF_4_SPI_MODE         SF_CTRL_SF_IF_4_SPI_MODE
#define SF_CTRL_SF_IF_4_SPI_MODE_POS     (28U)
#define SF_CTRL_SF_IF_4_SPI_MODE_LEN     (3U)
#define SF_CTRL_SF_IF_4_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)
#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS))
#define SF_CTRL_SF_IF_4_QPI_MODE_EN      SF_CTRL_SF_IF_4_QPI_MODE_EN
#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS  (31U)
#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN  (1U)
#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)
#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS))

/* 0x94 : sf_if_iahb_10 */
#define SF_CTRL_SF_IF_IAHB_10_OFFSET   (0x94)
#define SF_CTRL_SF_IF_4_CMD_BUF_0      SF_CTRL_SF_IF_4_CMD_BUF_0
#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS  (0U)
#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN  (32U)
#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)
#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS))

/* 0x98 : sf_if_iahb_11 */
#define SF_CTRL_SF_IF_IAHB_11_OFFSET   (0x98)
#define SF_CTRL_SF_IF_4_CMD_BUF_1      SF_CTRL_SF_IF_4_CMD_BUF_1
#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS  (0U)
#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN  (32U)
#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)
#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS))

/* 0x9C : sf_if_iahb_12 */
#define SF_CTRL_SF_IF_IAHB_12_OFFSET       (0x9C)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL      SF_CTRL_SF2_CLK_SF_RX_INV_SEL
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS  (2U)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN  (1U)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS))
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC      SF_CTRL_SF2_CLK_SF_RX_INV_SRC
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS  (3U)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN  (1U)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS))
#define SF_CTRL_SF2_CLK_OUT_INV_SEL        SF_CTRL_SF2_CLK_OUT_INV_SEL
#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS    (4U)
#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN    (1U)
#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)
#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS))
#define SF_CTRL_SF3_CLK_OUT_INV_SEL        SF_CTRL_SF3_CLK_OUT_INV_SEL
#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS    (5U)
#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN    (1U)
#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)
#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS))
#define SF_CTRL_SF2_IF_READ_DLY_N          SF_CTRL_SF2_IF_READ_DLY_N
#define SF_CTRL_SF2_IF_READ_DLY_N_POS      (8U)
#define SF_CTRL_SF2_IF_READ_DLY_N_LEN      (3U)
#define SF_CTRL_SF2_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)
#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS))
#define SF_CTRL_SF2_IF_READ_DLY_EN         SF_CTRL_SF2_IF_READ_DLY_EN
#define SF_CTRL_SF2_IF_READ_DLY_EN_POS     (11U)
#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN     (1U)
#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)
#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS))
#define SF_CTRL_SF2_IF_READ_DLY_SRC        SF_CTRL_SF2_IF_READ_DLY_SRC
#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS    (12U)
#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN    (1U)
#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK    (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)
#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK   (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS))

/* 0x100 : sf_ctrl_prot_en_rd */
#define SF_CTRL_PROT_EN_RD_OFFSET         (0x100)
#define SF_CTRL_PROT_EN_RD                SF_CTRL_PROT_EN_RD
#define SF_CTRL_PROT_EN_RD_POS            (0U)
#define SF_CTRL_PROT_EN_RD_LEN            (1U)
#define SF_CTRL_PROT_EN_RD_MSK            (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)
#define SF_CTRL_PROT_EN_RD_UMSK           (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS))
#define SF_CTRL_ID0_EN_RD                 SF_CTRL_ID0_EN_RD
#define SF_CTRL_ID0_EN_RD_POS             (1U)
#define SF_CTRL_ID0_EN_RD_LEN             (1U)
#define SF_CTRL_ID0_EN_RD_MSK             (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
#define SF_CTRL_ID0_EN_RD_UMSK            (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
#define SF_CTRL_ID1_EN_RD                 SF_CTRL_ID1_EN_RD
#define SF_CTRL_ID1_EN_RD_POS             (2U)
#define SF_CTRL_ID1_EN_RD_LEN             (1U)
#define SF_CTRL_ID1_EN_RD_MSK             (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
#define SF_CTRL_ID1_EN_RD_UMSK            (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK      SF_CTRL_SF_IF_0_TRIG_WR_LOCK
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS  (30U)
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN  (1U)
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK  (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
#define SF_CTRL_SF_DBG_DIS                SF_CTRL_SF_DBG_DIS
#define SF_CTRL_SF_DBG_DIS_POS            (31U)
#define SF_CTRL_SF_DBG_DIS_LEN            (1U)
#define SF_CTRL_SF_DBG_DIS_MSK            (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
#define SF_CTRL_SF_DBG_DIS_UMSK           (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))

/* 0x104 : sf_ctrl_prot_en */
#define SF_CTRL_PROT_EN_OFFSET (0x104)
#define SF_CTRL_PROT_EN        SF_CTRL_PROT_EN
#define SF_CTRL_PROT_EN_POS    (0U)
#define SF_CTRL_PROT_EN_LEN    (1U)
#define SF_CTRL_PROT_EN_MSK    (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)
#define SF_CTRL_PROT_EN_UMSK   (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS))
#define SF_CTRL_ID0_EN         SF_CTRL_ID0_EN
#define SF_CTRL_ID0_EN_POS     (1U)
#define SF_CTRL_ID0_EN_LEN     (1U)
#define SF_CTRL_ID0_EN_MSK     (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
#define SF_CTRL_ID0_EN_UMSK    (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
#define SF_CTRL_ID1_EN         SF_CTRL_ID1_EN
#define SF_CTRL_ID1_EN_POS     (2U)
#define SF_CTRL_ID1_EN_LEN     (1U)
#define SF_CTRL_ID1_EN_MSK     (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
#define SF_CTRL_ID1_EN_UMSK    (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))

/* 0x200 : sf_aes_key_r0_0 */
#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
#define SF_CTRL_SF_AES_KEY_R0_0        SF_CTRL_SF_AES_KEY_R0_0
#define SF_CTRL_SF_AES_KEY_R0_0_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_0_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
#define SF_CTRL_SF_AES_KEY_R0_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))

/* 0x204 : sf_aes_key_r0_1 */
#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
#define SF_CTRL_SF_AES_KEY_R0_1        SF_CTRL_SF_AES_KEY_R0_1
#define SF_CTRL_SF_AES_KEY_R0_1_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_1_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
#define SF_CTRL_SF_AES_KEY_R0_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))

/* 0x208 : sf_aes_key_r0_2 */
#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
#define SF_CTRL_SF_AES_KEY_R0_2        SF_CTRL_SF_AES_KEY_R0_2
#define SF_CTRL_SF_AES_KEY_R0_2_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_2_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
#define SF_CTRL_SF_AES_KEY_R0_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))

/* 0x20C : sf_aes_key_r0_3 */
#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
#define SF_CTRL_SF_AES_KEY_R0_3        SF_CTRL_SF_AES_KEY_R0_3
#define SF_CTRL_SF_AES_KEY_R0_3_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_3_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
#define SF_CTRL_SF_AES_KEY_R0_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))

/* 0x210 : sf_aes_key_r0_4 */
#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
#define SF_CTRL_SF_AES_KEY_R0_4        SF_CTRL_SF_AES_KEY_R0_4
#define SF_CTRL_SF_AES_KEY_R0_4_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_4_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
#define SF_CTRL_SF_AES_KEY_R0_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))

/* 0x214 : sf_aes_key_r0_5 */
#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
#define SF_CTRL_SF_AES_KEY_R0_5        SF_CTRL_SF_AES_KEY_R0_5
#define SF_CTRL_SF_AES_KEY_R0_5_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_5_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
#define SF_CTRL_SF_AES_KEY_R0_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))

/* 0x218 : sf_aes_key_r0_6 */
#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
#define SF_CTRL_SF_AES_KEY_R0_6        SF_CTRL_SF_AES_KEY_R0_6
#define SF_CTRL_SF_AES_KEY_R0_6_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_6_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
#define SF_CTRL_SF_AES_KEY_R0_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))

/* 0x21C : sf_aes_key_r0_7 */
#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
#define SF_CTRL_SF_AES_KEY_R0_7        SF_CTRL_SF_AES_KEY_R0_7
#define SF_CTRL_SF_AES_KEY_R0_7_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R0_7_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R0_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
#define SF_CTRL_SF_AES_KEY_R0_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))

/* 0x220 : sf_aes_iv_r0_w0 */
#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
#define SF_CTRL_SF_AES_IV_R0_W0        SF_CTRL_SF_AES_IV_R0_W0
#define SF_CTRL_SF_AES_IV_R0_W0_POS    (0U)
#define SF_CTRL_SF_AES_IV_R0_W0_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R0_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
#define SF_CTRL_SF_AES_IV_R0_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))

/* 0x224 : sf_aes_iv_r0_w1 */
#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
#define SF_CTRL_SF_AES_IV_R0_W1        SF_CTRL_SF_AES_IV_R0_W1
#define SF_CTRL_SF_AES_IV_R0_W1_POS    (0U)
#define SF_CTRL_SF_AES_IV_R0_W1_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R0_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
#define SF_CTRL_SF_AES_IV_R0_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))

/* 0x228 : sf_aes_iv_r0_w2 */
#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
#define SF_CTRL_SF_AES_IV_R0_W2        SF_CTRL_SF_AES_IV_R0_W2
#define SF_CTRL_SF_AES_IV_R0_W2_POS    (0U)
#define SF_CTRL_SF_AES_IV_R0_W2_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R0_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
#define SF_CTRL_SF_AES_IV_R0_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))

/* 0x22C : sf_aes_iv_r0_w3 */
#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
#define SF_CTRL_SF_AES_IV_R0_W3        SF_CTRL_SF_AES_IV_R0_W3
#define SF_CTRL_SF_AES_IV_R0_W3_POS    (0U)
#define SF_CTRL_SF_AES_IV_R0_W3_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R0_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
#define SF_CTRL_SF_AES_IV_R0_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))

/* 0x230 : sf_aes_cfg_r0 */
#define SF_CTRL_SF_AES_CFG_R0_OFFSET            (0x230)
#define SF_CTRL_SF_AES_REGION_R0_END            SF_CTRL_SF_AES_REGION_R0_END
#define SF_CTRL_SF_AES_REGION_R0_END_POS        (0U)
#define SF_CTRL_SF_AES_REGION_R0_END_LEN        (14U)
#define SF_CTRL_SF_AES_REGION_R0_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
#define SF_CTRL_SF_AES_REGION_R0_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
#define SF_CTRL_SF_AES_REGION_R0_START          SF_CTRL_SF_AES_REGION_R0_START
#define SF_CTRL_SF_AES_REGION_R0_START_POS      (14U)
#define SF_CTRL_SF_AES_REGION_R0_START_LEN      (14U)
#define SF_CTRL_SF_AES_REGION_R0_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
#define SF_CTRL_SF_AES_REGION_R0_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN      SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS  (29U)
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN  (1U)
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
#define SF_CTRL_SF_AES_REGION_R0_EN             SF_CTRL_SF_AES_REGION_R0_EN
#define SF_CTRL_SF_AES_REGION_R0_EN_POS         (30U)
#define SF_CTRL_SF_AES_REGION_R0_EN_LEN         (1U)
#define SF_CTRL_SF_AES_REGION_R0_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
#define SF_CTRL_SF_AES_REGION_R0_LOCK           SF_CTRL_SF_AES_REGION_R0_LOCK
#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS       (31U)
#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN       (1U)
#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))

/* 0x300 : sf_aes_key_r1_0 */
#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300)
#define SF_CTRL_SF_AES_KEY_R1_0        SF_CTRL_SF_AES_KEY_R1_0
#define SF_CTRL_SF_AES_KEY_R1_0_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_0_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
#define SF_CTRL_SF_AES_KEY_R1_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))

/* 0x304 : sf_aes_key_r1_1 */
#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304)
#define SF_CTRL_SF_AES_KEY_R1_1        SF_CTRL_SF_AES_KEY_R1_1
#define SF_CTRL_SF_AES_KEY_R1_1_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_1_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
#define SF_CTRL_SF_AES_KEY_R1_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))

/* 0x308 : sf_aes_key_r1_2 */
#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308)
#define SF_CTRL_SF_AES_KEY_R1_2        SF_CTRL_SF_AES_KEY_R1_2
#define SF_CTRL_SF_AES_KEY_R1_2_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_2_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
#define SF_CTRL_SF_AES_KEY_R1_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))

/* 0x30C : sf_aes_key_r1_3 */
#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C)
#define SF_CTRL_SF_AES_KEY_R1_3        SF_CTRL_SF_AES_KEY_R1_3
#define SF_CTRL_SF_AES_KEY_R1_3_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_3_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
#define SF_CTRL_SF_AES_KEY_R1_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))

/* 0x310 : sf_aes_key_r1_4 */
#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310)
#define SF_CTRL_SF_AES_KEY_R1_4        SF_CTRL_SF_AES_KEY_R1_4
#define SF_CTRL_SF_AES_KEY_R1_4_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_4_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
#define SF_CTRL_SF_AES_KEY_R1_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))

/* 0x314 : sf_aes_key_r1_5 */
#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314)
#define SF_CTRL_SF_AES_KEY_R1_5        SF_CTRL_SF_AES_KEY_R1_5
#define SF_CTRL_SF_AES_KEY_R1_5_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_5_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
#define SF_CTRL_SF_AES_KEY_R1_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))

/* 0x318 : sf_aes_key_r1_6 */
#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318)
#define SF_CTRL_SF_AES_KEY_R1_6        SF_CTRL_SF_AES_KEY_R1_6
#define SF_CTRL_SF_AES_KEY_R1_6_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_6_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
#define SF_CTRL_SF_AES_KEY_R1_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))

/* 0x31C : sf_aes_key_r1_7 */
#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C)
#define SF_CTRL_SF_AES_KEY_R1_7        SF_CTRL_SF_AES_KEY_R1_7
#define SF_CTRL_SF_AES_KEY_R1_7_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R1_7_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R1_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
#define SF_CTRL_SF_AES_KEY_R1_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))

/* 0x320 : sf_aes_iv_r1_w0 */
#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320)
#define SF_CTRL_SF_AES_IV_R1_W0        SF_CTRL_SF_AES_IV_R1_W0
#define SF_CTRL_SF_AES_IV_R1_W0_POS    (0U)
#define SF_CTRL_SF_AES_IV_R1_W0_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R1_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
#define SF_CTRL_SF_AES_IV_R1_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))

/* 0x324 : sf_aes_iv_r1_w1 */
#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324)
#define SF_CTRL_SF_AES_IV_R1_W1        SF_CTRL_SF_AES_IV_R1_W1
#define SF_CTRL_SF_AES_IV_R1_W1_POS    (0U)
#define SF_CTRL_SF_AES_IV_R1_W1_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R1_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
#define SF_CTRL_SF_AES_IV_R1_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))

/* 0x328 : sf_aes_iv_r1_w2 */
#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328)
#define SF_CTRL_SF_AES_IV_R1_W2        SF_CTRL_SF_AES_IV_R1_W2
#define SF_CTRL_SF_AES_IV_R1_W2_POS    (0U)
#define SF_CTRL_SF_AES_IV_R1_W2_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R1_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
#define SF_CTRL_SF_AES_IV_R1_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))

/* 0x32C : sf_aes_iv_r1_w3 */
#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C)
#define SF_CTRL_SF_AES_IV_R1_W3        SF_CTRL_SF_AES_IV_R1_W3
#define SF_CTRL_SF_AES_IV_R1_W3_POS    (0U)
#define SF_CTRL_SF_AES_IV_R1_W3_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R1_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
#define SF_CTRL_SF_AES_IV_R1_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))

/* 0x330 : sf_aes_r1 */
#define SF_CTRL_SF_AES_R1_OFFSET         (0x330)
#define SF_CTRL_SF_AES_R1_END            SF_CTRL_SF_AES_R1_END
#define SF_CTRL_SF_AES_R1_END_POS        (0U)
#define SF_CTRL_SF_AES_R1_END_LEN        (14U)
#define SF_CTRL_SF_AES_R1_END_MSK        (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
#define SF_CTRL_SF_AES_R1_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
#define SF_CTRL_SF_AES_R1_START          SF_CTRL_SF_AES_R1_START
#define SF_CTRL_SF_AES_R1_START_POS      (14U)
#define SF_CTRL_SF_AES_R1_START_LEN      (14U)
#define SF_CTRL_SF_AES_R1_START_MSK      (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
#define SF_CTRL_SF_AES_R1_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
#define SF_CTRL_SF_AES_R1_HW_KEY_EN      SF_CTRL_SF_AES_R1_HW_KEY_EN
#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS  (29U)
#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN  (1U)
#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
#define SF_CTRL_SF_AES_R1_EN             SF_CTRL_SF_AES_R1_EN
#define SF_CTRL_SF_AES_R1_EN_POS         (30U)
#define SF_CTRL_SF_AES_R1_EN_LEN         (1U)
#define SF_CTRL_SF_AES_R1_EN_MSK         (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
#define SF_CTRL_SF_AES_R1_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
#define SF_CTRL_SF_AES_R1_LOCK           SF_CTRL_SF_AES_R1_LOCK
#define SF_CTRL_SF_AES_R1_LOCK_POS       (31U)
#define SF_CTRL_SF_AES_R1_LOCK_LEN       (1U)
#define SF_CTRL_SF_AES_R1_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
#define SF_CTRL_SF_AES_R1_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))

/* 0x400 : sf_aes_key_r2_0 */
#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400)
#define SF_CTRL_SF_AES_KEY_R2_0        SF_CTRL_SF_AES_KEY_R2_0
#define SF_CTRL_SF_AES_KEY_R2_0_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_0_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
#define SF_CTRL_SF_AES_KEY_R2_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))

/* 0x404 : sf_aes_key_r2_1 */
#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404)
#define SF_CTRL_SF_AES_KEY_R2_1        SF_CTRL_SF_AES_KEY_R2_1
#define SF_CTRL_SF_AES_KEY_R2_1_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_1_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
#define SF_CTRL_SF_AES_KEY_R2_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))

/* 0x408 : sf_aes_key_r2_2 */
#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408)
#define SF_CTRL_SF_AES_KEY_R2_2        SF_CTRL_SF_AES_KEY_R2_2
#define SF_CTRL_SF_AES_KEY_R2_2_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_2_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
#define SF_CTRL_SF_AES_KEY_R2_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))

/* 0x40C : sf_aes_key_r2_3 */
#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C)
#define SF_CTRL_SF_AES_KEY_R2_3        SF_CTRL_SF_AES_KEY_R2_3
#define SF_CTRL_SF_AES_KEY_R2_3_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_3_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
#define SF_CTRL_SF_AES_KEY_R2_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))

/* 0x410 : sf_aes_key_r2_4 */
#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410)
#define SF_CTRL_SF_AES_KEY_R2_4        SF_CTRL_SF_AES_KEY_R2_4
#define SF_CTRL_SF_AES_KEY_R2_4_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_4_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
#define SF_CTRL_SF_AES_KEY_R2_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))

/* 0x414 : sf_aes_key_r2_5 */
#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414)
#define SF_CTRL_SF_AES_KEY_R2_5        SF_CTRL_SF_AES_KEY_R2_5
#define SF_CTRL_SF_AES_KEY_R2_5_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_5_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
#define SF_CTRL_SF_AES_KEY_R2_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))

/* 0x418 : sf_aes_key_r2_6 */
#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418)
#define SF_CTRL_SF_AES_KEY_R2_6        SF_CTRL_SF_AES_KEY_R2_6
#define SF_CTRL_SF_AES_KEY_R2_6_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_6_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
#define SF_CTRL_SF_AES_KEY_R2_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))

/* 0x41C : sf_aes_key_r2_7 */
#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C)
#define SF_CTRL_SF_AES_KEY_R2_7        SF_CTRL_SF_AES_KEY_R2_7
#define SF_CTRL_SF_AES_KEY_R2_7_POS    (0U)
#define SF_CTRL_SF_AES_KEY_R2_7_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_R2_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
#define SF_CTRL_SF_AES_KEY_R2_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))

/* 0x420 : sf_aes_iv_r2_w0 */
#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420)
#define SF_CTRL_SF_AES_IV_R2_W0        SF_CTRL_SF_AES_IV_R2_W0
#define SF_CTRL_SF_AES_IV_R2_W0_POS    (0U)
#define SF_CTRL_SF_AES_IV_R2_W0_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R2_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
#define SF_CTRL_SF_AES_IV_R2_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))

/* 0x424 : sf_aes_iv_r2_w1 */
#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424)
#define SF_CTRL_SF_AES_IV_R2_W1        SF_CTRL_SF_AES_IV_R2_W1
#define SF_CTRL_SF_AES_IV_R2_W1_POS    (0U)
#define SF_CTRL_SF_AES_IV_R2_W1_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R2_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
#define SF_CTRL_SF_AES_IV_R2_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))

/* 0x428 : sf_aes_iv_r2_w2 */
#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428)
#define SF_CTRL_SF_AES_IV_R2_W2        SF_CTRL_SF_AES_IV_R2_W2
#define SF_CTRL_SF_AES_IV_R2_W2_POS    (0U)
#define SF_CTRL_SF_AES_IV_R2_W2_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R2_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
#define SF_CTRL_SF_AES_IV_R2_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))

/* 0x42C : sf_aes_iv_r2_w3 */
#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C)
#define SF_CTRL_SF_AES_IV_R2_W3        SF_CTRL_SF_AES_IV_R2_W3
#define SF_CTRL_SF_AES_IV_R2_W3_POS    (0U)
#define SF_CTRL_SF_AES_IV_R2_W3_LEN    (32U)
#define SF_CTRL_SF_AES_IV_R2_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
#define SF_CTRL_SF_AES_IV_R2_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))

/* 0x430 : sf_aes_r2 */
#define SF_CTRL_SF_AES_R2_OFFSET         (0x430)
#define SF_CTRL_SF_AES_R2_END            SF_CTRL_SF_AES_R2_END
#define SF_CTRL_SF_AES_R2_END_POS        (0U)
#define SF_CTRL_SF_AES_R2_END_LEN        (14U)
#define SF_CTRL_SF_AES_R2_END_MSK        (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
#define SF_CTRL_SF_AES_R2_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
#define SF_CTRL_SF_AES_R2_START          SF_CTRL_SF_AES_R2_START
#define SF_CTRL_SF_AES_R2_START_POS      (14U)
#define SF_CTRL_SF_AES_R2_START_LEN      (14U)
#define SF_CTRL_SF_AES_R2_START_MSK      (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
#define SF_CTRL_SF_AES_R2_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
#define SF_CTRL_SF_AES_R2_HW_KEY_EN      SF_CTRL_SF_AES_R2_HW_KEY_EN
#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS  (29U)
#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN  (1U)
#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
#define SF_CTRL_SF_AES_R2_EN             SF_CTRL_SF_AES_R2_EN
#define SF_CTRL_SF_AES_R2_EN_POS         (30U)
#define SF_CTRL_SF_AES_R2_EN_LEN         (1U)
#define SF_CTRL_SF_AES_R2_EN_MSK         (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
#define SF_CTRL_SF_AES_R2_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
#define SF_CTRL_SF_AES_R2_LOCK           SF_CTRL_SF_AES_R2_LOCK
#define SF_CTRL_SF_AES_R2_LOCK_POS       (31U)
#define SF_CTRL_SF_AES_R2_LOCK_LEN       (1U)
#define SF_CTRL_SF_AES_R2_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
#define SF_CTRL_SF_AES_R2_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))

/* 0x434 : sf_id0_offset */
#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434)
#define SF_CTRL_SF_ID0_OFFSET        SF_CTRL_SF_ID0_OFFSET
#define SF_CTRL_SF_ID0_OFFSET_POS    (0U)
#define SF_CTRL_SF_ID0_OFFSET_LEN    (24U)
#define SF_CTRL_SF_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
#define SF_CTRL_SF_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))

/* 0x438 : sf_id1_offset */
#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438)
#define SF_CTRL_SF_ID1_OFFSET        SF_CTRL_SF_ID1_OFFSET
#define SF_CTRL_SF_ID1_OFFSET_POS    (0U)
#define SF_CTRL_SF_ID1_OFFSET_LEN    (24U)
#define SF_CTRL_SF_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
#define SF_CTRL_SF_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))

/* 0x43C : sf_bk2_id0_offset */
#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0x43C)
#define SF_CTRL_SF_BK2_ID0_OFFSET        SF_CTRL_SF_BK2_ID0_OFFSET
#define SF_CTRL_SF_BK2_ID0_OFFSET_POS    (0U)
#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN    (24U)
#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)
#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS))

/* 0x440 : sf_bk2_id1_offset */
#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0x440)
#define SF_CTRL_SF_BK2_ID1_OFFSET        SF_CTRL_SF_BK2_ID1_OFFSET
#define SF_CTRL_SF_BK2_ID1_OFFSET_POS    (0U)
#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN    (24U)
#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)
#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS))

struct sf_ctrl_reg {
    /* 0x0 : sf_ctrl_0 */
    union {
        struct
        {
            uint32_t reserved_0_1         : 2; /* [ 1: 0],       rsvd,        0x0 */
            uint32_t sf_clk_sf_rx_inv_sel : 1; /* [    2],        r/w,        0x1 */
            uint32_t sf_clk_out_gate_en   : 1; /* [    3],        r/w,        0x1 */
            uint32_t sf_clk_out_inv_sel   : 1; /* [    4],        r/w,        0x1 */
            uint32_t sf_clk_sahb_sram_sel : 1; /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t sf_if_read_dly_n     : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t sf_if_read_dly_en    : 1; /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
            uint32_t sf_if_int            : 1; /* [   16],          r,        0x0 */
            uint32_t sf_if_int_clr        : 1; /* [   17],        r/w,        0x1 */
            uint32_t sf_if_int_set        : 1; /* [   18],        r/w,        0x0 */
            uint32_t sf_aes_dly_mode      : 1; /* [   19],        r/w,        0x0 */
            uint32_t sf_aes_dout_endian   : 1; /* [   20],        r/w,        0x1 */
            uint32_t sf_aes_ctr_plus_en   : 1; /* [   21],        r/w,        0x0 */
            uint32_t sf_aes_key_endian    : 1; /* [   22],        r/w,        0x1 */
            uint32_t sf_aes_iv_endian     : 1; /* [   23],        r/w,        0x1 */
            uint32_t sf_id                : 8; /* [31:24],        r/w,       0x1a */
        } BF;
        uint32_t WORD;
    } sf_ctrl_0;

    /* 0x4 : sf_ctrl_1 */
    union {
        struct
        {
            uint32_t sf_if_sr_pat_mask  : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t sf_if_sr_pat       : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t sf_if_sr_int       : 1; /* [   16],          r,        0x0 */
            uint32_t sf_if_sr_int_en    : 1; /* [   17],        r/w,        0x0 */
            uint32_t sf_if_sr_int_set   : 1; /* [   18],        r/w,        0x0 */
            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
            uint32_t sf_if_0_ack_lat    : 3; /* [22:20],        r/w,        0x6 */
            uint32_t reserved_23        : 1; /* [   23],       rsvd,        0x0 */
            uint32_t sf_if_reg_hold     : 1; /* [   24],        r/w,        0x1 */
            uint32_t sf_if_reg_wp       : 1; /* [   25],        r/w,        0x1 */
            uint32_t sf_ahb2sif_stopped : 1; /* [   26],          r,        0x0 */
            uint32_t sf_ahb2sif_stop    : 1; /* [   27],        r/w,        0x0 */
            uint32_t sf_if_fn_sel       : 1; /* [   28],        r/w,        0x1 */
            uint32_t sf_if_en           : 1; /* [   29],        r/w,        0x1 */
            uint32_t sf_ahb2sif_en      : 1; /* [   30],        r/w,        0x1 */
            uint32_t sf_ahb2sram_en     : 1; /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } sf_ctrl_1;

    /* 0x8 : sf_if_sahb_0 */
    union {
        struct
        {
            uint32_t sf_if_busy          : 1;  /* [    0],          r,        0x0 */
            uint32_t sf_if_0_trig        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t sf_if_0_dat_byte    : 10; /* [11: 2],        r/w,        0x0 */
            uint32_t sf_if_0_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
            uint32_t sf_if_0_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
            uint32_t sf_if_0_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t sf_if_0_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
            uint32_t sf_if_0_dat_en      : 1;  /* [   24],        r/w,        0x0 */
            uint32_t sf_if_0_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
            uint32_t sf_if_0_adr_en      : 1;  /* [   26],        r/w,        0x0 */
            uint32_t sf_if_0_cmd_en      : 1;  /* [   27],        r/w,        0x0 */
            uint32_t sf_if_0_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t sf_if_0_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_sahb_0;

    /* 0xC : sf_if_sahb_1 */
    union {
        struct
        {
            uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_sahb_1;

    /* 0x10 : sf_if_sahb_2 */
    union {
        struct
        {
            uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_sahb_2;

    /* 0x14 : sf_if_iahb_0 */
    union {
        struct
        {
            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
            uint32_t sf_if_1_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
            uint32_t sf_if_1_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
            uint32_t sf_if_1_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t sf_if_1_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
            uint32_t sf_if_1_dat_en      : 1;  /* [   24],        r/w,        0x1 */
            uint32_t sf_if_1_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
            uint32_t sf_if_1_adr_en      : 1;  /* [   26],        r/w,        0x1 */
            uint32_t sf_if_1_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
            uint32_t sf_if_1_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t sf_if_1_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_0;

    /* 0x18 : sf_if_iahb_1 */
    union {
        struct
        {
            uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0],        r/w,  0x3000000 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_1;

    /* 0x1C : sf_if_iahb_2 */
    union {
        struct
        {
            uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_2;

    /* 0x20 : sf_if_status_0 */
    union {
        struct
        {
            uint32_t sf_if_status_0 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_status_0;

    /* 0x24 : sf_if_status_1 */
    union {
        struct
        {
            uint32_t sf_if_status_1 : 32; /* [31: 0],          r, 0x20000000 */
        } BF;
        uint32_t WORD;
    } sf_if_status_1;

    /* 0x28 : sf_aes */
    union {
        struct
        {
            uint32_t sf_aes_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t sf_aes_mode      : 2;  /* [ 2: 1],        r/w,        0x0 */
            uint32_t sf_aes_pref_trig : 1;  /* [    3],        r/w,        0x0 */
            uint32_t sf_aes_pref_busy : 1;  /* [    4],          r,        0x0 */
            uint32_t sf_aes_status    : 27; /* [31: 5],          r,        0x2 */
        } BF;
        uint32_t WORD;
    } sf_aes;

    /* 0x2C : sf_ahb2sif_status */
    union {
        struct
        {
            uint32_t sf_ahb2sif_status : 32; /* [31: 0],          r, 0x10000003 */
        } BF;
        uint32_t WORD;
    } sf_ahb2sif_status;

    /* 0x30 : sf_if_io_dly_0 */
    union {
        struct
        {
            uint32_t sf_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t sf_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reserved_4_7       : 4;  /* [ 7: 4],       rsvd,        0x0 */
            uint32_t sf_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_25     : 16; /* [25:10],       rsvd,        0x0 */
            uint32_t sf_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
            uint32_t sf_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
            uint32_t sf_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_io_dly_0;

    /* 0x34 : sf_if_io_dly_1 */
    union {
        struct
        {
            uint32_t sf_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_io_dly_1;

    /* 0x38 : sf_if_io_dly_2 */
    union {
        struct
        {
            uint32_t sf_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_io_dly_2;

    /* 0x3C : sf_if_io_dly_3 */
    union {
        struct
        {
            uint32_t sf_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_io_dly_3;

    /* 0x40 : sf_if_io_dly_4 */
    union {
        struct
        {
            uint32_t sf_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_io_dly_4;

    /* 0x44 : sf_reserved */
    union {
        struct
        {
            uint32_t sf_reserved : 32; /* [31: 0],        r/w,     0xffff */
        } BF;
        uint32_t WORD;
    } sf_reserved;

    /* 0x48 : sf2_if_io_dly_0 */
    union {
        struct
        {
            uint32_t sf2_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t sf2_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
            uint32_t sf2_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
            uint32_t sf2_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
            uint32_t sf2_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
            uint32_t sf2_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf2_if_io_dly_0;

    /* 0x4C : sf2_if_io_dly_1 */
    union {
        struct
        {
            uint32_t sf2_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf2_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf2_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf2_if_io_dly_1;

    /* 0x50 : sf2_if_io_dly_2 */
    union {
        struct
        {
            uint32_t sf2_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf2_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf2_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf2_if_io_dly_2;

    /* 0x54 : sf2_if_io_dly_3 */
    union {
        struct
        {
            uint32_t sf2_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf2_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf2_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf2_if_io_dly_3;

    /* 0x58 : sf2_if_io_dly_4 */
    union {
        struct
        {
            uint32_t sf2_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf2_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf2_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf2_if_io_dly_4;

    /* 0x5C : sf3_if_io_dly_0 */
    union {
        struct
        {
            uint32_t sf3_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t sf3_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
            uint32_t sf3_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
            uint32_t sf3_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
            uint32_t sf3_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
            uint32_t sf3_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf3_if_io_dly_0;

    /* 0x60 : sf3_if_io_dly_1 */
    union {
        struct
        {
            uint32_t sf3_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf3_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf3_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf3_if_io_dly_1;

    /* 0x64 : sf3_if_io_dly_2 */
    union {
        struct
        {
            uint32_t sf3_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf3_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf3_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf3_if_io_dly_2;

    /* 0x68 : sf3_if_io_dly_3 */
    union {
        struct
        {
            uint32_t sf3_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf3_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf3_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf3_if_io_dly_3;

    /* 0x6C : sf3_if_io_dly_4 */
    union {
        struct
        {
            uint32_t sf3_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
            uint32_t sf3_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
            uint32_t sf3_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf3_if_io_dly_4;

    /* 0x70 : sf_ctrl_2 */
    union {
        struct
        {
            uint32_t sf_if_pad_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
            uint32_t sf_if_pad_sel_lock : 1;  /* [    3],        r/w,        0x0 */
            uint32_t sf_if_dtr_en       : 1;  /* [    4],        r/w,        0x0 */
            uint32_t sf_if_dqs_en       : 1;  /* [    5],        r/w,        0x0 */
            uint32_t reserved_6_27      : 22; /* [27: 6],       rsvd,        0x0 */
            uint32_t sf_if_bk_swap      : 1;  /* [   28],        r/w,        0x0 */
            uint32_t sf_if_bk2_mode     : 1;  /* [   29],        r/w,        0x0 */
            uint32_t sf_if_bk2_en       : 1;  /* [   30],        r/w,        0x0 */
            uint32_t sf_if_0_bk_sel     : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_ctrl_2;

    /* 0x74 : sf_ctrl_3 */
    union {
        struct
        {
            uint32_t sf_cmds_wrap_len   : 4;  /* [ 3: 0],        r/w,        0x6 */
            uint32_t sf_cmds_en         : 1;  /* [    4],        r/w,        0x0 */
            uint32_t sf_cmds_bt_dly     : 3;  /* [ 7: 5],        r/w,        0x2 */
            uint32_t sf_cmds_bt_en      : 1;  /* [    8],        r/w,        0x0 */
            uint32_t sf_cmds_wrap_q_ini : 1;  /* [    9],        r/w,        0x0 */
            uint32_t sf_cmds_wrap_mode  : 1;  /* [   10],        r/w,        0x0 */
            uint32_t sf_cmds_wrap_q     : 1;  /* [   11],          r,        0x0 */
            uint32_t reserved_12_28     : 17; /* [28:12],       rsvd,        0x0 */
            uint32_t sf_if_1_ack_lat    : 3;  /* [31:29],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } sf_ctrl_3;

    /* 0x78 : sf_if_iahb_3 */
    union {
        struct
        {
            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
            uint32_t sf_if_2_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
            uint32_t sf_if_2_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
            uint32_t sf_if_2_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t sf_if_2_dat_rw      : 1;  /* [   23],        r/w,        0x1 */
            uint32_t sf_if_2_dat_en      : 1;  /* [   24],        r/w,        0x1 */
            uint32_t sf_if_2_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
            uint32_t sf_if_2_adr_en      : 1;  /* [   26],        r/w,        0x1 */
            uint32_t sf_if_2_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
            uint32_t sf_if_2_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t sf_if_2_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_3;

    /* 0x7C : sf_if_iahb_4 */
    union {
        struct
        {
            uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0],        r/w, 0x38000000 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_4;

    /* 0x80 : sf_if_iahb_5 */
    union {
        struct
        {
            uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_5;

    /* 0x84 : sf_if_iahb_6 */
    union {
        struct
        {
            uint32_t reserved_0_16       : 17; /* [16: 0],       rsvd,        0x0 */
            uint32_t sf_if_3_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
            uint32_t sf_if_3_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t reserved_23_25      : 3;  /* [25:23],       rsvd,        0x0 */
            uint32_t sf_if_3_adr_en      : 1;  /* [   26],        r/w,        0x0 */
            uint32_t sf_if_3_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
            uint32_t sf_if_3_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t sf_if_3_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_6;

    /* 0x88 : sf_if_iahb_7 */
    union {
        struct
        {
            uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xc0000000L */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_7;

    /* 0x8C : sf_if_iahb_8 */
    union {
        struct
        {
            uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_8;

    /* 0x90 : sf_if_iahb_9 */
    union {
        struct
        {
            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
            uint32_t sf_if_4_dmy_byte    : 5;  /* [16:12],        r/w,        0x2 */
            uint32_t sf_if_4_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
            uint32_t sf_if_4_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
            uint32_t sf_if_4_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
            uint32_t sf_if_4_dat_en      : 1;  /* [   24],        r/w,        0x1 */
            uint32_t sf_if_4_dmy_en      : 1;  /* [   25],        r/w,        0x1 */
            uint32_t sf_if_4_adr_en      : 1;  /* [   26],        r/w,        0x1 */
            uint32_t sf_if_4_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
            uint32_t sf_if_4_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
            uint32_t sf_if_4_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_9;

    /* 0x94 : sf_if_iahb_10 */
    union {
        struct
        {
            uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xeb000000L */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_10;

    /* 0x98 : sf_if_iahb_11 */
    union {
        struct
        {
            uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_11;

    /* 0x9C : sf_if_iahb_12 */
    union {
        struct
        {
            uint32_t reserved_0_1          : 2;  /* [ 1: 0],       rsvd,        0x0 */
            uint32_t sf2_clk_sf_rx_inv_sel : 1;  /* [    2],        r/w,        0x0 */
            uint32_t sf2_clk_sf_rx_inv_src : 1;  /* [    3],        r/w,        0x0 */
            uint32_t sf2_clk_out_inv_sel   : 1;  /* [    4],        r/w,        0x1 */
            uint32_t sf3_clk_out_inv_sel   : 1;  /* [    5],        r/w,        0x1 */
            uint32_t reserved_6_7          : 2;  /* [ 7: 6],       rsvd,        0x0 */
            uint32_t sf2_if_read_dly_n     : 3;  /* [10: 8],        r/w,        0x0 */
            uint32_t sf2_if_read_dly_en    : 1;  /* [   11],        r/w,        0x0 */
            uint32_t sf2_if_read_dly_src   : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_if_iahb_12;

    /* 0xa0  reserved */
    uint8_t RESERVED0xa0[96];

    /* 0x100 : sf_ctrl_prot_en_rd */
    union {
        struct
        {
            uint32_t sf_ctrl_prot_en_rd   : 1;  /* [    0],          r,        0x1 */
            uint32_t sf_ctrl_id0_en_rd    : 1;  /* [    1],          r,        0x1 */
            uint32_t sf_ctrl_id1_en_rd    : 1;  /* [    2],          r,        0x1 */
            uint32_t reserved_3_29        : 27; /* [29: 3],       rsvd,        0x0 */
            uint32_t sf_if_0_trig_wr_lock : 1;  /* [   30],          r,        0x0 */
            uint32_t sf_dbg_dis           : 1;  /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_ctrl_prot_en_rd;

    /* 0x104 : sf_ctrl_prot_en */
    union {
        struct
        {
            uint32_t sf_ctrl_prot_en : 1;  /* [    0],        r/w,        0x1 */
            uint32_t sf_ctrl_id0_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t sf_ctrl_id1_en  : 1;  /* [    2],        r/w,        0x1 */
            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_ctrl_prot_en;

    /* 0x108  reserved */
    uint8_t RESERVED0x108[248];

    /* 0x200 : sf_aes_key_r0_0 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_0;

    /* 0x204 : sf_aes_key_r0_1 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_1;

    /* 0x208 : sf_aes_key_r0_2 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_2;

    /* 0x20C : sf_aes_key_r0_3 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_3;

    /* 0x210 : sf_aes_key_r0_4 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_4;

    /* 0x214 : sf_aes_key_r0_5 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_5;

    /* 0x218 : sf_aes_key_r0_6 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_6;

    /* 0x21C : sf_aes_key_r0_7 */
    union {
        struct
        {
            uint32_t sf_aes_key_r0_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r0_7;

    /* 0x220 : sf_aes_iv_r0_w0 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r0_w0;

    /* 0x224 : sf_aes_iv_r0_w1 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r0_w1;

    /* 0x228 : sf_aes_iv_r0_w2 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r0_w2;

    /* 0x22C : sf_aes_iv_r0_w3 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r0_w3;

    /* 0x230 : sf_aes_cfg_r0 */
    union {
        struct
        {
            uint32_t sf_aes_region_r0_end       : 14; /* [13: 0],        r/w,     0x3fff */
            uint32_t sf_aes_region_r0_start     : 14; /* [27:14],        r/w,        0x0 */
            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
            uint32_t sf_aes_region_r0_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
            uint32_t sf_aes_region_r0_en        : 1;  /* [   30],        r/w,        0x0 */
            uint32_t sf_aes_region_r0_lock      : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_cfg_r0;

    /* 0x234  reserved */
    uint8_t RESERVED0x234[204];

    /* 0x300 : sf_aes_key_r1_0 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_0;

    /* 0x304 : sf_aes_key_r1_1 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_1;

    /* 0x308 : sf_aes_key_r1_2 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_2;

    /* 0x30C : sf_aes_key_r1_3 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_3;

    /* 0x310 : sf_aes_key_r1_4 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_4;

    /* 0x314 : sf_aes_key_r1_5 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_5;

    /* 0x318 : sf_aes_key_r1_6 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_6;

    /* 0x31C : sf_aes_key_r1_7 */
    union {
        struct
        {
            uint32_t sf_aes_key_r1_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r1_7;

    /* 0x320 : sf_aes_iv_r1_w0 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r1_w0;

    /* 0x324 : sf_aes_iv_r1_w1 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r1_w1;

    /* 0x328 : sf_aes_iv_r1_w2 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r1_w2;

    /* 0x32C : sf_aes_iv_r1_w3 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r1_w3;

    /* 0x330 : sf_aes_r1 */
    union {
        struct
        {
            uint32_t sf_aes_r1_end       : 14; /* [13: 0],        r/w,     0x3fff */
            uint32_t sf_aes_r1_start     : 14; /* [27:14],        r/w,        0x0 */
            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
            uint32_t sf_aes_r1_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
            uint32_t sf_aes_r1_en        : 1;  /* [   30],        r/w,        0x0 */
            uint32_t sf_aes_r1_lock      : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_r1;

    /* 0x334  reserved */
    uint8_t RESERVED0x334[204];

    /* 0x400 : sf_aes_key_r2_0 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_0;

    /* 0x404 : sf_aes_key_r2_1 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_1;

    /* 0x408 : sf_aes_key_r2_2 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_2;

    /* 0x40C : sf_aes_key_r2_3 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_3;

    /* 0x410 : sf_aes_key_r2_4 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_4;

    /* 0x414 : sf_aes_key_r2_5 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_5;

    /* 0x418 : sf_aes_key_r2_6 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_6;

    /* 0x41C : sf_aes_key_r2_7 */
    union {
        struct
        {
            uint32_t sf_aes_key_r2_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_r2_7;

    /* 0x420 : sf_aes_iv_r2_w0 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r2_w0;

    /* 0x424 : sf_aes_iv_r2_w1 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r2_w1;

    /* 0x428 : sf_aes_iv_r2_w2 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r2_w2;

    /* 0x42C : sf_aes_iv_r2_w3 */
    union {
        struct
        {
            uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_r2_w3;

    /* 0x430 : sf_aes_r2 */
    union {
        struct
        {
            uint32_t sf_aes_r2_end       : 14; /* [13: 0],        r/w,     0x3fff */
            uint32_t sf_aes_r2_start     : 14; /* [27:14],        r/w,        0x0 */
            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
            uint32_t sf_aes_r2_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
            uint32_t sf_aes_r2_en        : 1;  /* [   30],        r/w,        0x0 */
            uint32_t sf_aes_r2_lock      : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_r2;

    /* 0x434 : sf_id0_offset */
    union {
        struct
        {
            uint32_t sf_id0_offset  : 24; /* [23: 0],        r/w,        0x0 */
            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_id0_offset;

    /* 0x438 : sf_id1_offset */
    union {
        struct
        {
            uint32_t sf_id1_offset  : 24; /* [23: 0],        r/w,        0x0 */
            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_id1_offset;

    /* 0x43C : sf_bk2_id0_offset */
    union {
        struct
        {
            uint32_t sf_bk2_id0_offset : 24; /* [23: 0],        r/w,        0x0 */
            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_bk2_id0_offset;

    /* 0x440 : sf_bk2_id1_offset */
    union {
        struct
        {
            uint32_t sf_bk2_id1_offset : 24; /* [23: 0],        r/w,        0x0 */
            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_bk2_id1_offset;
};

typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;

/*Following is reg patch*/

/* 0x0 : sf_aes_key_0 */
#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
#define SF_CTRL_SF_AES_KEY_0        SF_CTRL_SF_AES_KEY_0
#define SF_CTRL_SF_AES_KEY_0_POS    (0U)
#define SF_CTRL_SF_AES_KEY_0_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
#define SF_CTRL_SF_AES_KEY_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))

/* 0x4 : sf_aes_key_1 */
#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
#define SF_CTRL_SF_AES_KEY_1        SF_CTRL_SF_AES_KEY_1
#define SF_CTRL_SF_AES_KEY_1_POS    (0U)
#define SF_CTRL_SF_AES_KEY_1_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
#define SF_CTRL_SF_AES_KEY_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))

/* 0x8 : sf_aes_key_2 */
#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
#define SF_CTRL_SF_AES_KEY_2        SF_CTRL_SF_AES_KEY_2
#define SF_CTRL_SF_AES_KEY_2_POS    (0U)
#define SF_CTRL_SF_AES_KEY_2_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
#define SF_CTRL_SF_AES_KEY_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))

/* 0xc : sf_aes_key_3 */
#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
#define SF_CTRL_SF_AES_KEY_3        SF_CTRL_SF_AES_KEY_3
#define SF_CTRL_SF_AES_KEY_3_POS    (0U)
#define SF_CTRL_SF_AES_KEY_3_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
#define SF_CTRL_SF_AES_KEY_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))

/* 0x10 : sf_aes_key_4 */
#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
#define SF_CTRL_SF_AES_KEY_4        SF_CTRL_SF_AES_KEY_4
#define SF_CTRL_SF_AES_KEY_4_POS    (0U)
#define SF_CTRL_SF_AES_KEY_4_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
#define SF_CTRL_SF_AES_KEY_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))

/* 0x14 : sf_aes_key_5 */
#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
#define SF_CTRL_SF_AES_KEY_5        SF_CTRL_SF_AES_KEY_5
#define SF_CTRL_SF_AES_KEY_5_POS    (0U)
#define SF_CTRL_SF_AES_KEY_5_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
#define SF_CTRL_SF_AES_KEY_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))

/* 0x18 : sf_aes_key_6 */
#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
#define SF_CTRL_SF_AES_KEY_6        SF_CTRL_SF_AES_KEY_6
#define SF_CTRL_SF_AES_KEY_6_POS    (0U)
#define SF_CTRL_SF_AES_KEY_6_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
#define SF_CTRL_SF_AES_KEY_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))

/* 0x1c : sf_aes_key_7 */
#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
#define SF_CTRL_SF_AES_KEY_7        SF_CTRL_SF_AES_KEY_7
#define SF_CTRL_SF_AES_KEY_7_POS    (0U)
#define SF_CTRL_SF_AES_KEY_7_LEN    (32U)
#define SF_CTRL_SF_AES_KEY_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
#define SF_CTRL_SF_AES_KEY_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))

/* 0x20 : sf_aes_iv_w0 */
#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
#define SF_CTRL_SF_AES_IV_W0        SF_CTRL_SF_AES_IV_W0
#define SF_CTRL_SF_AES_IV_W0_POS    (0U)
#define SF_CTRL_SF_AES_IV_W0_LEN    (32U)
#define SF_CTRL_SF_AES_IV_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
#define SF_CTRL_SF_AES_IV_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))

/* 0x24 : sf_aes_iv_w1 */
#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
#define SF_CTRL_SF_AES_IV_W1        SF_CTRL_SF_AES_IV_W1
#define SF_CTRL_SF_AES_IV_W1_POS    (0U)
#define SF_CTRL_SF_AES_IV_W1_LEN    (32U)
#define SF_CTRL_SF_AES_IV_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
#define SF_CTRL_SF_AES_IV_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))

/* 0x28 : sf_aes_iv_w2 */
#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
#define SF_CTRL_SF_AES_IV_W2        SF_CTRL_SF_AES_IV_W2
#define SF_CTRL_SF_AES_IV_W2_POS    (0U)
#define SF_CTRL_SF_AES_IV_W2_LEN    (32U)
#define SF_CTRL_SF_AES_IV_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
#define SF_CTRL_SF_AES_IV_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))

/* 0x2c : sf_aes_iv_w3 */
#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
#define SF_CTRL_SF_AES_IV_W3        SF_CTRL_SF_AES_IV_W3
#define SF_CTRL_SF_AES_IV_W3_POS    (0U)
#define SF_CTRL_SF_AES_IV_W3_LEN    (32U)
#define SF_CTRL_SF_AES_IV_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
#define SF_CTRL_SF_AES_IV_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))

/* 0x30 : sf_aes_cfg */
#define SF_CTRL_SF_AES_CFG_OFFSET            (0x30)
#define SF_CTRL_SF_AES_REGION_END            SF_CTRL_SF_AES_REGION_END
#define SF_CTRL_SF_AES_REGION_END_POS        (0U)
#define SF_CTRL_SF_AES_REGION_END_LEN        (14U)
#define SF_CTRL_SF_AES_REGION_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
#define SF_CTRL_SF_AES_REGION_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
#define SF_CTRL_SF_AES_REGION_START          SF_CTRL_SF_AES_REGION_START
#define SF_CTRL_SF_AES_REGION_START_POS      (14U)
#define SF_CTRL_SF_AES_REGION_START_LEN      (14U)
#define SF_CTRL_SF_AES_REGION_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
#define SF_CTRL_SF_AES_REGION_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN      SF_CTRL_SF_AES_REGION_HW_KEY_EN
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS  (29U)
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN  (1U)
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
#define SF_CTRL_SF_AES_REGION_EN             SF_CTRL_SF_AES_REGION_EN
#define SF_CTRL_SF_AES_REGION_EN_POS         (30U)
#define SF_CTRL_SF_AES_REGION_EN_LEN         (1U)
#define SF_CTRL_SF_AES_REGION_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
#define SF_CTRL_SF_AES_REGION_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
#define SF_CTRL_SF_AES_REGION_LOCK           SF_CTRL_SF_AES_REGION_LOCK
#define SF_CTRL_SF_AES_REGION_LOCK_POS       (31U)
#define SF_CTRL_SF_AES_REGION_LOCK_LEN       (1U)
#define SF_CTRL_SF_AES_REGION_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
#define SF_CTRL_SF_AES_REGION_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))

struct sf_ctrl_aes_region_reg {
    /* 0x0 : sf_aes_key_0 */
    union {
        struct
        {
            uint32_t sf_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_0;

    /* 0x4 : sf_aes_key_1 */
    union {
        struct
        {
            uint32_t sf_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_1;

    /* 0x8 : sf_aes_key_2 */
    union {
        struct
        {
            uint32_t sf_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_2;

    /* 0xc : sf_aes_key_3 */
    union {
        struct
        {
            uint32_t sf_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_3;

    /* 0x10 : sf_aes_key_4 */
    union {
        struct
        {
            uint32_t sf_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_4;

    /* 0x14 : sf_aes_key_5 */
    union {
        struct
        {
            uint32_t sf_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_5;

    /* 0x18 : sf_aes_key_6 */
    union {
        struct
        {
            uint32_t sf_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_6;

    /* 0x1c : sf_aes_key_7 */
    union {
        struct
        {
            uint32_t sf_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_key_7;

    /* 0x20 : sf_aes_iv_w0 */
    union {
        struct
        {
            uint32_t sf_aes_iv_w0 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_w0;

    /* 0x24 : sf_aes_iv_w1 */
    union {
        struct
        {
            uint32_t sf_aes_iv_w1 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_w1;

    /* 0x28 : sf_aes_iv_w2 */
    union {
        struct
        {
            uint32_t sf_aes_iv_w2 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_w2;

    /* 0x2c : sf_aes_iv_w3 */
    union {
        struct
        {
            uint32_t sf_aes_iv_w3 : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_iv_w3;

    /* 0x30 : sf_aes_cfg */
    union {
        struct
        {
            uint32_t sf_aes_region_end       : 14; /* [13: 0],        r/w,     0x3fff */
            uint32_t sf_aes_region_start     : 14; /* [27:14],        r/w,        0x0 */
            uint32_t reserved_28             : 1;  /* [   28],       rsvd,        0x0 */
            uint32_t sf_aes_region_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
            uint32_t sf_aes_region_en        : 1;  /* [   30],        r/w,        0x0 */
            uint32_t sf_aes_region_lock      : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } sf_aes_cfg;
};

typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;

#define SF_CTRL_AES_REGION_OFFSET 0x200

#endif /* __SF_CTRL_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/soc702_reg.svd
================================================

	
		bouffalolab
		bouffalolab
		702
		WiFi BT
		high-performance, 32-bit RV32IMAFC core
		8
		32
		32
		0x00000000
		0xFFFFFFFF
		
			702
			little
		
		
			
				glb
				glb.
				0x40000000
				glb
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						clk_cfg0
						clk_cfg0.
						0x0
						
							
								glb_id
								28
								31
							
							
								chip_rdy
								27
								27
							
							
								fclk_sw_state
								24
								26
							
							
								reg_bclk_div
								16
								23
							
							
								reg_hclk_div
								8
								15
							
							
								hbn_root_clk_sel
								6
								7
							
							
								reg_pll_sel
								4
								5
							
							
								reg_bclk_en
								3
								3
							
							
								reg_hclk_en
								2
								2
							
							
								reg_fclk_en
								1
								1
							
							
								reg_pll_en
								0
								0
							
						
					
					
						clk_cfg1
						clk_cfg1.
						0x4
						
							
								reg_cam_ref_clk_div
								30
								31
							
							
								reg_cam_ref_clk_src_sel
								29
								29
							
							
								reg_cam_ref_clk_en
								28
								28
							
							
								m154_zbEn
								25
								25
							
							
								ble_en
								24
								24
							
							
								ble_clk_sel
								16
								21
							
							
								reg_i2s_0_ref_clk_oe
								14
								14
							
							
								reg_i2s0_clk_en
								13
								13
							
							
								reg_i2s_clk_sel
								12
								12
							
							
								dll_48m_div_en
								9
								9
							
							
								usb_clk_en
								8
								8
							
							
								qdec_clk_sel
								7
								7
							
							
								qdec_clk_div
								0
								4
							
						
					
					
						clk_cfg2
						clk_cfg2.
						0x8
						
							
								dma_clk_en
								24
								31
							
							
								ir_clk_en
								23
								23
							
							
								ir_clk_div
								16
								21
							
							
								sf_clk_sel2
								14
								15
							
							
								sf_clk_sel
								12
								13
							
							
								sf_clk_en
								11
								11
							
							
								sf_clk_div
								8
								10
							
							
								hbn_uart_clk_sel
								7
								7
							
							
								uart_clk_en
								4
								4
							
							
								uart_clk_div
								0
								2
							
						
					
					
						clk_cfg3
						clk_cfg3.
						0xC
						
							
								chip_clk_out_1_sel
								30
								31
							
							
								chip_clk_out_0_sel
								28
								29
							
							
								i2c_clk_en
								24
								24
							
							
								i2c_clk_div
								16
								23
							
							
								cfg_inv_eth_rx_clk
								10
								10
							
							
								cfg_inv_rf_test_clk_o
								9
								9
							
							
								spi_clk_en
								8
								8
							
							
								cfg_inv_eth_tx_clk
								7
								7
							
							
								cfg_inv_eth_ref_clk_o
								6
								6
							
							
								cfg_sel_eth_ref_clk_o
								5
								5
							
							
								spi_clk_div
								0
								4
							
						
					
					
						swrst_cfg0
						swrst_cfg0.
						0x10
						
							
								swrst_s30
								8
								8
							
							
								swrst_s20
								4
								4
							
							
								swrst_s01
								1
								1
							
							
								swrst_s00
								0
								0
							
						
					
					
						swrst_cfg1
						swrst_cfg1.
						0x14
						
							
								swrst_s1ae
								30
								30
							
							
								swrst_s1ad
								29
								29
							
							
								swrst_s1ac
								28
								28
							
							
								swrst_s1ab
								27
								27
							
							
								swrst_s1aa
								26
								26
							
							
								swrst_s1a9
								25
								25
							
							
								swrst_s1a8
								24
								24
							
							
								swrst_s1a7
								23
								23
							
							
								swrst_s1a6
								22
								22
							
							
								swrst_s1a5
								21
								21
							
							
								swrst_s1a4
								20
								20
							
							
								swrst_s1a3
								19
								19
							
							
								swrst_s1a2
								18
								18
							
							
								swrst_s1a1
								17
								17
							
							
								swrst_s1a0
								16
								16
							
							
								swrst_s1f
								15
								15
							
							
								swrst_s1e
								14
								14
							
							
								swrst_s1d
								13
								13
							
							
								swrst_s1c
								12
								12
							
							
								swrst_s1b
								11
								11
							
							
								swrst_s1a
								10
								10
							
							
								swrst_s19
								9
								9
							
							
								swrst_s18
								8
								8
							
							
								swrst_s17
								7
								7
							
							
								swrst_s16
								6
								6
							
							
								swrst_s15
								5
								5
							
							
								swrst_s14
								4
								4
							
							
								swrst_s13
								3
								3
							
							
								swrst_s12
								2
								2
							
							
								swrst_s11
								1
								1
							
							
								swrst_s10
								0
								0
							
						
					
					
						swrst_cfg2
						swrst_cfg2.
						0x18
						
							
								pka_clk_sel
								24
								24
							
							
								reg_ctrl_reset_dummy
								4
								7
							
							
								reg_ctrl_sys_reset
								2
								2
							
							
								reg_ctrl_cpu_reset
								1
								1
							
							
								reg_ctrl_pwron_rst
								0
								0
							
						
					
					
						swrst_cfg3
						swrst_cfg3.
						0x1C
						
					
					
						cgen_cfg0
						cgen_cfg0.
						0x20
						
							
								cgen_m
								0
								7
							
						
					
					
						cgen_cfg1
						cgen_cfg1.
						0x24
						
							
								cgen_s1a
								16
								31
							
							
								cgen_s1
								0
								15
							
						
					
					
						cgen_cfg2
						cgen_cfg2.
						0x28
						
							
								cgen_s3
								4
								4
							
							
								cgen_s2
								0
								0
							
						
					
					
						cgen_cfg3
						cgen_cfg3.
						0x2C
						
					
					
						MBIST_CTL
						MBIST_CTL.
						0x30
						
							
								reg_mbist_rst_n
								31
								31
							
							
								em_ram_mbist_mode
								5
								5
							
							
								ocram_mbist_mode
								4
								4
							
							
								tag_mbist_mode
								3
								3
							
							
								hsram_cache_mbist_mode
								2
								2
							
							
								hsram_mem_mbist_mode
								1
								1
							
							
								irom_mbist_mode
								0
								0
							
						
					
					
						MBIST_STAT
						MBIST_STAT.
						0x34
						
							
								em_ram_mbist_fail
								21
								21
							
							
								ocram_mbist_fail
								20
								20
							
							
								tag_mbist_fail
								19
								19
							
							
								hsram_cache_mbist_fail
								18
								18
							
							
								hsram_mem_mbist_fail
								17
								17
							
							
								irom_mbist_fail
								16
								16
							
							
								em_ram_mbist_done
								5
								5
							
							
								ocram_mbist_done
								4
								4
							
							
								tag_mbist_done
								3
								3
							
							
								hsram_cache_mbist_done
								2
								2
							
							
								hsram_mem_mbist_done
								1
								1
							
							
								irom_mbist_done
								0
								0
							
						
					
					
						bmx_cfg1
						bmx_cfg1.
						0x50
						
							
								hbn_apb_cfg
								24
								31
							
							
								pds_apb_cfg
								16
								23
							
							
								hsel_option
								12
								15
							
							
								bmx_gating_dis
								10
								10
							
							
								bmx_busy_option_dis
								9
								9
							
							
								bmx_err_en
								8
								8
							
							
								bmx_arb_mode
								4
								5
							
							
								bmx_timeout_en
								0
								3
							
						
					
					
						bmx_cfg2
						bmx_cfg2.
						0x54
						
							
								bmx_dbg_sel
								28
								31
							
							
								reg_w_thre_l1c
								10
								11
							
							
								reg_w_thre_bmx
								8
								9
							
							
								bmx_err_tz
								5
								5
							
							
								bmx_err_dec
								4
								4
							
							
								bmx_err_addr_dis
								0
								0
							
						
					
					
						bmx_err_addr
						bmx_err_addr.
						0x58
						
							
								bmx_err_addr
								0
								31
							
						
					
					
						bmx_dbg_out
						bmx_dbg_out.
						0x5C
						
							
								bmx_dbg_out
								0
								31
							
						
					
					
						rsv0
						rsv0.
						0x60
						
							
								rsvd_31_0
								0
								31
							
						
					
					
						rsv1
						rsv1.
						0x64
						
							
								rsvd_31_0
								0
								31
							
						
					
					
						rsv2
						rsv2.
						0x68
						
							
								rsvd_31_0
								0
								31
							
						
					
					
						rsv3
						rsv3.
						0x6C
						
							
								rsvd_31_0
								0
								31
							
						
					
					
						sram_ret
						sram_ret.
						0x70
						
							
								reg_sram_ret
								0
								31
							
						
					
					
						sram_slp
						sram_slp.
						0x74
						
							
								reg_sram_slp
								0
								31
							
						
					
					
						sram_parm
						sram_parm.
						0x78
						
							
								reg_sram_parm
								0
								31
							
						
					
					
						seam_misc
						seam_misc.
						0x7C
						
							
								em_sel
								0
								3
							
						
					
					
						glb_parm
						glb_parm.
						0x80
						
							
								pin_sel_emac_cam
								31
								31
							
							
								reg_ext_rst_smt
								30
								30
							
							
								reg_kys_drv_val
								29
								29
							
							
								uart_swap_set
								24
								27
							
							
								p6_jtag_use_io_0_2_7
								23
								23
							
							
								p5_dac_test_with_jtag
								21
								21
							
							
								p4_adc_test_with_jtag
								20
								20
							
							
								p3_cci_use_io_0_2_7
								19
								19
							
							
								p2_dac_test_with_cci
								18
								18
							
							
								p1_adc_test_with_cci
								17
								17
							
							
								reg_cci_use_jtag_pin
								16
								16
							
							
								reg_spi_0_swap
								13
								13
							
							
								reg_spi_0_master_mode
								12
								12
							
							
								cfg_flash_scenario
								10
								11
							
							
								cfg_sflash2_swap_cs_io2
								9
								9
							
							
								cfg_sflash2_swap_io0_io3
								8
								8
							
							
								jtag_swap_set
								0
								7
							
						
					
					
						PDM_CLK_CTRL
						PDM_CLK_CTRL.
						0x84
						
							
								reg_pdm0_clk_en
								7
								7
							
							
								reg_pdm0_clk_div
								0
								5
							
						
					
					
						GPIO_USE_PSRAM__IO
						GPIO_USE_PSRAM__IO.
						0x88
						
							
								cfg_gpio_use_psram_io
								0
								5
							
						
					
					
						CPU_CLK_CFG
						CPU_CLK_CFG.
						0x90
						
							
								debug_ndreset_gate
								20
								20
							
							
								cpu_rtc_sel
								19
								19
							
							
								cpu_rtc_en
								18
								18
							
							
								cpu_rtc_div
								0
								16
							
						
					
					
						GPADC_32M_SRC_CTRL
						GPADC_32M_SRC_CTRL.
						0xA4
						
							
								gpadc_32m_div_en
								8
								8
							
							
								gpadc_32m_clk_sel
								7
								7
							
							
								gpadc_32m_clk_div
								0
								5
							
						
					
					
						DIG32K_WAKEUP_CTRL
						DIG32K_WAKEUP_CTRL.
						0xA8
						
							
								reg_en_platform_wakeup
								31
								31
							
							
								dig_clk_src_sel
								28
								29
							
							
								dig_512k_comp
								25
								25
							
							
								dig_512k_en
								24
								24
							
							
								dig_512k_div
								16
								22
							
							
								dig_32k_comp
								13
								13
							
							
								dig_32k_en
								12
								12
							
							
								dig_32k_div
								0
								10
							
						
					
					
						WIFI_BT_COEX_CTRL
						WIFI_BT_COEX_CTRL.
						0xAC
						
							
								en_gpio_bt_coex
								12
								12
							
							
								coex_bt_bw
								11
								11
							
							
								coex_bt_pti
								7
								10
							
							
								coex_bt_channel
								0
								6
							
						
					
					
						BZ_COEX_CTRL
						BZ_COEX_CTRL.
						0xB0
						
							
								coex_arb
								28
								31
							
							
								ble_tx_abort_dis
								27
								27
							
							
								ble_rx_abort_dis
								26
								26
							
							
								m154_tx_abort_dis
								25
								25
							
							
								m154_rx_abort_dis
								24
								24
							
							
								coex_force_ch
								16
								22
							
							
								coex_option
								15
								15
							
							
								force_ble_win
								14
								14
							
							
								force_m154_win
								13
								13
							
							
								coex_pri
								12
								12
							
							
								bz_abort_pol
								11
								11
							
							
								bz_active_pol
								10
								10
							
							
								bz_pri_pol
								9
								9
							
							
								bz_pri_en
								8
								8
							
							
								bz_pri_thr
								4
								7
							
							
								m154_rx_ignore
								3
								3
							
							
								ble_rx_ignore
								2
								2
							
							
								wlan_en
								1
								1
							
							
								coex_en
								0
								0
							
						
					
					
						UART_SIG_SEL_0
						UART_SIG_SEL_0.
						0xC0
						
							
								uart_sig_7_sel
								28
								31
							
							
								uart_sig_6_sel
								24
								27
							
							
								uart_sig_5_sel
								20
								23
							
							
								uart_sig_4_sel
								16
								19
							
							
								uart_sig_3_sel
								12
								15
							
							
								uart_sig_2_sel
								8
								11
							
							
								uart_sig_1_sel
								4
								7
							
							
								uart_sig_0_sel
								0
								3
							
						
					
					
						DBG_SEL_LL
						DBG_SEL_LL.
						0xD0
						
							
								reg_dbg_ll_ctrl
								0
								31
							
						
					
					
						DBG_SEL_LH
						DBG_SEL_LH.
						0xD4
						
							
								reg_dbg_lh_ctrl
								0
								31
							
						
					
					
						DBG_SEL_HL
						DBG_SEL_HL.
						0xD8
						
							
								reg_dbg_hl_ctrl
								0
								31
							
						
					
					
						DBG_SEL_HH
						DBG_SEL_HH.
						0xDC
						
							
								reg_dbg_hh_ctrl
								0
								31
							
						
					
					
						debug
						debug.
						0xE0
						
							
								debug_i
								1
								31
							
							
								debug_oe
								0
								0
							
						
					
					
						GPIO_CFGCTL0
						GPIO_CFGCTL0.
						0x100
						
							
								reg_gpio_1_func_sel
								24
								28
							
							
								reg_gpio_1_pd
								21
								21
							
							
								reg_gpio_1_pu
								20
								20
							
							
								reg_gpio_1_drv
								18
								19
							
							
								reg_gpio_1_smt
								17
								17
							
							
								reg_gpio_1_ie
								16
								16
							
							
								reg_gpio_0_func_sel
								8
								12
							
							
								reg_gpio_0_pd
								5
								5
							
							
								reg_gpio_0_pu
								4
								4
							
							
								reg_gpio_0_drv
								2
								3
							
							
								reg_gpio_0_smt
								1
								1
							
							
								reg_gpio_0_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL1
						GPIO_CFGCTL1.
						0x104
						
							
								reg_gpio_3_func_sel
								24
								28
							
							
								reg_gpio_3_pd
								21
								21
							
							
								reg_gpio_3_pu
								20
								20
							
							
								reg_gpio_3_drv
								18
								19
							
							
								reg_gpio_3_smt
								17
								17
							
							
								reg_gpio_3_ie
								16
								16
							
							
								reg_gpio_2_func_sel
								8
								12
							
							
								reg_gpio_2_pd
								5
								5
							
							
								reg_gpio_2_pu
								4
								4
							
							
								reg_gpio_2_drv
								2
								3
							
							
								reg_gpio_2_smt
								1
								1
							
							
								reg_gpio_2_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL2
						GPIO_CFGCTL2.
						0x108
						
							
								reg_gpio_5_func_sel
								24
								28
							
							
								reg_gpio_5_pd
								21
								21
							
							
								reg_gpio_5_pu
								20
								20
							
							
								reg_gpio_5_drv
								18
								19
							
							
								reg_gpio_5_smt
								17
								17
							
							
								reg_gpio_5_ie
								16
								16
							
							
								reg_gpio_4_func_sel
								8
								12
							
							
								reg_gpio_4_pd
								5
								5
							
							
								reg_gpio_4_pu
								4
								4
							
							
								reg_gpio_4_drv
								2
								3
							
							
								reg_gpio_4_smt
								1
								1
							
							
								reg_gpio_4_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL3
						GPIO_CFGCTL3.
						0x10C
						
							
								reg_gpio_7_func_sel
								24
								28
							
							
								reg_gpio_7_pd
								21
								21
							
							
								reg_gpio_7_pu
								20
								20
							
							
								reg_gpio_7_drv
								18
								19
							
							
								reg_gpio_7_smt
								17
								17
							
							
								reg_gpio_7_ie
								16
								16
							
							
								reg_gpio_6_func_sel
								8
								12
							
							
								reg_gpio_6_pd
								5
								5
							
							
								reg_gpio_6_pu
								4
								4
							
							
								reg_gpio_6_drv
								2
								3
							
							
								reg_gpio_6_smt
								1
								1
							
							
								reg_gpio_6_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL4
						GPIO_CFGCTL4.
						0x110
						
							
								reg_gpio_9_func_sel
								24
								28
							
							
								reg_gpio_9_pd
								21
								21
							
							
								reg_gpio_9_pu
								20
								20
							
							
								reg_gpio_9_drv
								18
								19
							
							
								reg_gpio_9_smt
								17
								17
							
							
								reg_gpio_9_ie
								16
								16
							
							
								reg_gpio_8_func_sel
								8
								12
							
							
								reg_gpio_8_pd
								5
								5
							
							
								reg_gpio_8_pu
								4
								4
							
							
								reg_gpio_8_drv
								2
								3
							
							
								reg_gpio_8_smt
								1
								1
							
							
								reg_gpio_8_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL5
						GPIO_CFGCTL5.
						0x114
						
							
								reg_gpio_11_func_sel
								24
								28
							
							
								reg_gpio_11_pd
								21
								21
							
							
								reg_gpio_11_pu
								20
								20
							
							
								reg_gpio_11_drv
								18
								19
							
							
								reg_gpio_11_smt
								17
								17
							
							
								reg_gpio_11_ie
								16
								16
							
							
								reg_gpio_10_func_sel
								8
								12
							
							
								reg_gpio_10_pd
								5
								5
							
							
								reg_gpio_10_pu
								4
								4
							
							
								reg_gpio_10_drv
								2
								3
							
							
								reg_gpio_10_smt
								1
								1
							
							
								reg_gpio_10_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL6
						GPIO_CFGCTL6.
						0x118
						
							
								reg_gpio_13_func_sel
								24
								28
							
							
								reg_gpio_13_pd
								21
								21
							
							
								reg_gpio_13_pu
								20
								20
							
							
								reg_gpio_13_drv
								18
								19
							
							
								reg_gpio_13_smt
								17
								17
							
							
								reg_gpio_13_ie
								16
								16
							
							
								reg_gpio_12_func_sel
								8
								12
							
							
								reg_gpio_12_pd
								5
								5
							
							
								reg_gpio_12_pu
								4
								4
							
							
								reg_gpio_12_drv
								2
								3
							
							
								reg_gpio_12_smt
								1
								1
							
							
								reg_gpio_12_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL7
						GPIO_CFGCTL7.
						0x11C
						
							
								reg_gpio_15_func_sel
								24
								28
							
							
								reg_gpio_15_pd
								21
								21
							
							
								reg_gpio_15_pu
								20
								20
							
							
								reg_gpio_15_drv
								18
								19
							
							
								reg_gpio_15_smt
								17
								17
							
							
								reg_gpio_15_ie
								16
								16
							
							
								reg_gpio_14_func_sel
								8
								12
							
							
								reg_gpio_14_pd
								5
								5
							
							
								reg_gpio_14_pu
								4
								4
							
							
								reg_gpio_14_drv
								2
								3
							
							
								reg_gpio_14_smt
								1
								1
							
							
								reg_gpio_14_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL8
						GPIO_CFGCTL8.
						0x120
						
							
								reg_gpio_17_func_sel
								24
								28
							
							
								reg_gpio_17_pd
								21
								21
							
							
								reg_gpio_17_pu
								20
								20
							
							
								reg_gpio_17_drv
								18
								19
							
							
								reg_gpio_17_smt
								17
								17
							
							
								reg_gpio_17_ie
								16
								16
							
							
								reg_gpio_16_func_sel
								8
								12
							
							
								reg_gpio_16_pd
								5
								5
							
							
								reg_gpio_16_pu
								4
								4
							
							
								reg_gpio_16_drv
								2
								3
							
							
								reg_gpio_16_smt
								1
								1
							
							
								reg_gpio_16_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL9
						GPIO_CFGCTL9.
						0x124
						
							
								reg_gpio_19_func_sel
								24
								28
							
							
								reg_gpio_19_pd
								21
								21
							
							
								reg_gpio_19_pu
								20
								20
							
							
								reg_gpio_19_drv
								18
								19
							
							
								reg_gpio_19_smt
								17
								17
							
							
								reg_gpio_19_ie
								16
								16
							
							
								reg_gpio_18_func_sel
								8
								12
							
							
								reg_gpio_18_pd
								5
								5
							
							
								reg_gpio_18_pu
								4
								4
							
							
								reg_gpio_18_drv
								2
								3
							
							
								reg_gpio_18_smt
								1
								1
							
							
								reg_gpio_18_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL10
						GPIO_CFGCTL10.
						0x128
						
							
								reg_gpio_21_func_sel
								24
								28
							
							
								reg_gpio_21_pd
								21
								21
							
							
								reg_gpio_21_pu
								20
								20
							
							
								reg_gpio_21_drv
								18
								19
							
							
								reg_gpio_21_smt
								17
								17
							
							
								reg_gpio_21_ie
								16
								16
							
							
								reg_gpio_20_func_sel
								8
								12
							
							
								reg_gpio_20_pd
								5
								5
							
							
								reg_gpio_20_pu
								4
								4
							
							
								reg_gpio_20_drv
								2
								3
							
							
								reg_gpio_20_smt
								1
								1
							
							
								reg_gpio_20_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL11
						GPIO_CFGCTL11.
						0x12C
						
							
								reg_gpio_23_func_sel
								24
								28
							
							
								reg_gpio_23_pd
								21
								21
							
							
								reg_gpio_23_pu
								20
								20
							
							
								reg_gpio_23_drv
								18
								19
							
							
								reg_gpio_23_smt
								17
								17
							
							
								reg_gpio_23_ie
								16
								16
							
							
								reg_gpio_22_func_sel
								8
								12
							
							
								reg_gpio_22_pd
								5
								5
							
							
								reg_gpio_22_pu
								4
								4
							
							
								reg_gpio_22_drv
								2
								3
							
							
								reg_gpio_22_smt
								1
								1
							
							
								reg_gpio_22_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL12
						GPIO_CFGCTL12.
						0x130
						
							
								reg_gpio_25_func_sel
								24
								28
							
							
								reg_gpio_25_pd
								21
								21
							
							
								reg_gpio_25_pu
								20
								20
							
							
								reg_gpio_25_drv
								18
								19
							
							
								reg_gpio_25_smt
								17
								17
							
							
								reg_gpio_25_ie
								16
								16
							
							
								reg_gpio_24_func_sel
								8
								12
							
							
								reg_gpio_24_pd
								5
								5
							
							
								reg_gpio_24_pu
								4
								4
							
							
								reg_gpio_24_drv
								2
								3
							
							
								reg_gpio_24_smt
								1
								1
							
							
								reg_gpio_24_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL13
						GPIO_CFGCTL13.
						0x134
						
							
								reg_gpio_27_func_sel
								24
								28
							
							
								reg_gpio_27_pd
								21
								21
							
							
								reg_gpio_27_pu
								20
								20
							
							
								reg_gpio_27_drv
								18
								19
							
							
								reg_gpio_27_smt
								17
								17
							
							
								reg_gpio_27_ie
								16
								16
							
							
								reg_gpio_26_func_sel
								8
								12
							
							
								reg_gpio_26_pd
								5
								5
							
							
								reg_gpio_26_pu
								4
								4
							
							
								reg_gpio_26_drv
								2
								3
							
							
								reg_gpio_26_smt
								1
								1
							
							
								reg_gpio_26_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL14
						GPIO_CFGCTL14.
						0x138
						
							
								reg_gpio_29_func_sel
								24
								28
							
							
								reg_gpio_29_pd
								21
								21
							
							
								reg_gpio_29_pu
								20
								20
							
							
								reg_gpio_29_drv
								18
								19
							
							
								reg_gpio_29_smt
								17
								17
							
							
								reg_gpio_29_ie
								16
								16
							
							
								reg_gpio_28_func_sel
								8
								12
							
							
								reg_gpio_28_pd
								5
								5
							
							
								reg_gpio_28_pu
								4
								4
							
							
								reg_gpio_28_drv
								2
								3
							
							
								reg_gpio_28_smt
								1
								1
							
							
								reg_gpio_28_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL15
						GPIO_CFGCTL15.
						0x13C
						
							
								reg_gpio_31_func_sel
								24
								28
							
							
								reg_gpio_31_pd
								21
								21
							
							
								reg_gpio_31_pu
								20
								20
							
							
								reg_gpio_31_drv
								18
								19
							
							
								reg_gpio_31_smt
								17
								17
							
							
								reg_gpio_31_ie
								16
								16
							
							
								reg_gpio_30_func_sel
								8
								12
							
							
								reg_gpio_30_pd
								5
								5
							
							
								reg_gpio_30_pu
								4
								4
							
							
								reg_gpio_30_drv
								2
								3
							
							
								reg_gpio_30_smt
								1
								1
							
							
								reg_gpio_30_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL16
						GPIO_CFGCTL16.
						0x140
						
							
								reg_gpio_33_pd
								21
								21
							
							
								reg_gpio_33_pu
								20
								20
							
							
								reg_gpio_33_drv
								18
								19
							
							
								reg_gpio_33_smt
								17
								17
							
							
								reg_gpio_33_ie
								16
								16
							
							
								reg_gpio_32_pd
								5
								5
							
							
								reg_gpio_32_pu
								4
								4
							
							
								reg_gpio_32_drv
								2
								3
							
							
								reg_gpio_32_smt
								1
								1
							
							
								reg_gpio_32_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL17
						GPIO_CFGCTL17.
						0x144
						
							
								reg_gpio_35_pd
								21
								21
							
							
								reg_gpio_35_pu
								20
								20
							
							
								reg_gpio_35_drv
								18
								19
							
							
								reg_gpio_35_smt
								17
								17
							
							
								reg_gpio_35_ie
								16
								16
							
							
								reg_gpio_34_pd
								5
								5
							
							
								reg_gpio_34_pu
								4
								4
							
							
								reg_gpio_34_drv
								2
								3
							
							
								reg_gpio_34_smt
								1
								1
							
							
								reg_gpio_34_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL18
						GPIO_CFGCTL18.
						0x148
						
							
								reg_gpio_37_pd
								21
								21
							
							
								reg_gpio_37_pu
								20
								20
							
							
								reg_gpio_37_drv
								18
								19
							
							
								reg_gpio_37_smt
								17
								17
							
							
								reg_gpio_37_ie
								16
								16
							
							
								reg_gpio_36_pd
								5
								5
							
							
								reg_gpio_36_pu
								4
								4
							
							
								reg_gpio_36_drv
								2
								3
							
							
								reg_gpio_36_smt
								1
								1
							
							
								reg_gpio_36_ie
								0
								0
							
						
					
					
						GPIO_CFGCTL30
						GPIO_CFGCTL30.
						0x180
						
							
								reg_gpio_31_i
								31
								31
							
							
								reg_gpio_30_i
								30
								30
							
							
								reg_gpio_29_i
								29
								29
							
							
								reg_gpio_28_i
								28
								28
							
							
								reg_gpio_27_i
								27
								27
							
							
								reg_gpio_26_i
								26
								26
							
							
								reg_gpio_25_i
								25
								25
							
							
								reg_gpio_24_i
								24
								24
							
							
								reg_gpio_23_i
								23
								23
							
							
								reg_gpio_22_i
								22
								22
							
							
								reg_gpio_21_i
								21
								21
							
							
								reg_gpio_20_i
								20
								20
							
							
								reg_gpio_19_i
								19
								19
							
							
								reg_gpio_18_i
								18
								18
							
							
								reg_gpio_17_i
								17
								17
							
							
								reg_gpio_16_i
								16
								16
							
							
								reg_gpio_15_i
								15
								15
							
							
								reg_gpio_14_i
								14
								14
							
							
								reg_gpio_13_i
								13
								13
							
							
								reg_gpio_12_i
								12
								12
							
							
								reg_gpio_11_i
								11
								11
							
							
								reg_gpio_10_i
								10
								10
							
							
								reg_gpio_9_i
								9
								9
							
							
								reg_gpio_8_i
								8
								8
							
							
								reg_gpio_7_i
								7
								7
							
							
								reg_gpio_6_i
								6
								6
							
							
								reg_gpio_5_i
								5
								5
							
							
								reg_gpio_4_i
								4
								4
							
							
								reg_gpio_3_i
								3
								3
							
							
								reg_gpio_2_i
								2
								2
							
							
								reg_gpio_1_i
								1
								1
							
							
								reg_gpio_0_i
								0
								0
							
						
					
					
						GPIO_CFGCTL31
						GPIO_CFGCTL31.
						0x184
						
					
					
						GPIO_CFGCTL32
						GPIO_CFGCTL32.
						0x188
						
							
								reg_gpio_31_o
								31
								31
							
							
								reg_gpio_30_o
								30
								30
							
							
								reg_gpio_29_o
								29
								29
							
							
								reg_gpio_28_o
								28
								28
							
							
								reg_gpio_27_o
								27
								27
							
							
								reg_gpio_26_o
								26
								26
							
							
								reg_gpio_25_o
								25
								25
							
							
								reg_gpio_24_o
								24
								24
							
							
								reg_gpio_23_o
								23
								23
							
							
								reg_gpio_22_o
								22
								22
							
							
								reg_gpio_21_o
								21
								21
							
							
								reg_gpio_20_o
								20
								20
							
							
								reg_gpio_19_o
								19
								19
							
							
								reg_gpio_18_o
								18
								18
							
							
								reg_gpio_17_o
								17
								17
							
							
								reg_gpio_16_o
								16
								16
							
							
								reg_gpio_15_o
								15
								15
							
							
								reg_gpio_14_o
								14
								14
							
							
								reg_gpio_13_o
								13
								13
							
							
								reg_gpio_12_o
								12
								12
							
							
								reg_gpio_11_o
								11
								11
							
							
								reg_gpio_10_o
								10
								10
							
							
								reg_gpio_9_o
								9
								9
							
							
								reg_gpio_8_o
								8
								8
							
							
								reg_gpio_7_o
								7
								7
							
							
								reg_gpio_6_o
								6
								6
							
							
								reg_gpio_5_o
								5
								5
							
							
								reg_gpio_4_o
								4
								4
							
							
								reg_gpio_3_o
								3
								3
							
							
								reg_gpio_2_o
								2
								2
							
							
								reg_gpio_1_o
								1
								1
							
							
								reg_gpio_0_o
								0
								0
							
						
					
					
						GPIO_CFGCTL33
						GPIO_CFGCTL33.
						0x18C
						
					
					
						GPIO_CFGCTL34
						GPIO_CFGCTL34.
						0x190
						
							
								reg_gpio_31_oe
								31
								31
							
							
								reg_gpio_30_oe
								30
								30
							
							
								reg_gpio_29_oe
								29
								29
							
							
								reg_gpio_28_oe
								28
								28
							
							
								reg_gpio_27_oe
								27
								27
							
							
								reg_gpio_26_oe
								26
								26
							
							
								reg_gpio_25_oe
								25
								25
							
							
								reg_gpio_24_oe
								24
								24
							
							
								reg_gpio_23_oe
								23
								23
							
							
								reg_gpio_22_oe
								22
								22
							
							
								reg_gpio_21_oe
								21
								21
							
							
								reg_gpio_20_oe
								20
								20
							
							
								reg_gpio_19_oe
								19
								19
							
							
								reg_gpio_18_oe
								18
								18
							
							
								reg_gpio_17_oe
								17
								17
							
							
								reg_gpio_16_oe
								16
								16
							
							
								reg_gpio_15_oe
								15
								15
							
							
								reg_gpio_14_oe
								14
								14
							
							
								reg_gpio_13_oe
								13
								13
							
							
								reg_gpio_12_oe
								12
								12
							
							
								reg_gpio_11_oe
								11
								11
							
							
								reg_gpio_10_oe
								10
								10
							
							
								reg_gpio_9_oe
								9
								9
							
							
								reg_gpio_8_oe
								8
								8
							
							
								reg_gpio_7_oe
								7
								7
							
							
								reg_gpio_6_oe
								6
								6
							
							
								reg_gpio_5_oe
								5
								5
							
							
								reg_gpio_4_oe
								4
								4
							
							
								reg_gpio_3_oe
								3
								3
							
							
								reg_gpio_2_oe
								2
								2
							
							
								reg_gpio_1_oe
								1
								1
							
							
								reg_gpio_0_oe
								0
								0
							
						
					
					
						GPIO_CFGCTL35
						GPIO_CFGCTL35.
						0x194
						
					
					
						GPIO_INT_MASK1
						GPIO_INT_MASK1.
						0x1A0
						
							
								reg_gpio_int_mask1
								0
								31
							
						
					
					
						GPIO_INT_STAT1
						GPIO_INT_STAT1.
						0x1A8
						
							
								gpio_int_stat1
								0
								31
							
						
					
					
						GPIO_INT_CLR1
						GPIO_INT_CLR1.
						0x1B0
						
							
								reg_gpio_int_clr1
								0
								31
							
						
					
					
						GPIO_INT_MODE_SET1
						GPIO_INT_MODE_SET1.
						0x1C0
						
							
								reg_gpio_int_mode_set1
								0
								29
							
						
					
					
						GPIO_INT_MODE_SET2
						GPIO_INT_MODE_SET2.
						0x1C4
						
							
								reg_gpio_int_mode_set2
								0
								29
							
						
					
					
						GPIO_INT_MODE_SET3
						GPIO_INT_MODE_SET3.
						0x1C8
						
							
								reg_gpio_int_mode_set3
								0
								29
							
						
					
					
						GPIO_INT_MODE_SET4
						GPIO_INT_MODE_SET4.
						0x1CC
						
							
								reg_gpio_int_mode_set4
								0
								5
							
						
					
					
						GPIO_INT2_MASK1
						GPIO_INT2_MASK1.
						0x1D0
						
							
								reg_gpio_int2_mask1
								0
								31
							
						
					
					
						GPIO_INT2_STAT1
						GPIO_INT2_STAT1.
						0x1D4
						
							
								gpio_int2_stat1
								0
								31
							
						
					
					
						GPIO_INT2_CLR1
						GPIO_INT2_CLR1.
						0x1D8
						
							
								reg_gpio_int2_clr1
								0
								31
							
						
					
					
						GPIO_INT2_MODE_SET1
						GPIO_INT2_MODE_SET1.
						0x1DC
						
							
								reg_gpio_int2_mode_set1
								0
								29
							
						
					
					
						GPIO_INT2_MODE_SET2
						GPIO_INT2_MODE_SET2.
						0x1E0
						
							
								reg_gpio_int2_mode_set2
								0
								29
							
						
					
					
						GPIO_INT2_MODE_SET3
						GPIO_INT2_MODE_SET3.
						0x1E4
						
							
								reg_gpio_int2_mode_set3
								0
								29
							
						
					
					
						GPIO_INT2_MODE_SET4
						GPIO_INT2_MODE_SET4.
						0x1E8
						
							
								reg_gpio_int2_mode_set4
								0
								5
							
						
					
					
						dll
						dll.
						0x200
						
							
								ppu_dll
								31
								31
							
							
								pu_dll
								30
								30
							
							
								dll_reset
								29
								29
							
							
								dll_refclk_sel
								28
								28
							
							
								dll_cp_hiz
								23
								23
							
							
								dll_cp_op_en
								22
								22
							
							
								dll_delay_sel
								20
								21
							
							
								dll_post_div
								16
								19
							
							
								dll_vctrl_force_en
								15
								15
							
							
								dll_prechg_en
								14
								14
							
							
								dll_prechg_reg
								13
								13
							
							
								dll_prechg_sel
								12
								12
							
							
								dll_vctrl_sel
								8
								10
							
							
								dll_clk_57p6M_en
								7
								7
							
							
								dll_clk_96M_en
								6
								6
							
							
								dll_clk_144M_en
								5
								5
							
							
								dll_clk_288M_en
								4
								4
							
							
								dll_clk_mmdiv_en
								3
								3
							
							
								ten_dll
								2
								2
							
							
								dtest_en_dll_outclk
								1
								1
							
							
								dtest_en_dll_refclk
								0
								0
							
						
					
					
						led_driver
						led_driver.
						0x224
						
							
								pu_leddrv
								31
								31
							
							
								leddrv_out_en
								28
								29
							
							
								ir_rx_gpio_sel
								8
								11
							
							
								leddrv_ibias
								4
								7
							
							
								led_din_polarity_sel
								2
								2
							
							
								led_din_sel
								1
								1
							
							
								led_din_reg
								0
								0
							
						
					
					
						usb_xcvr
						usb_xcvr.
						0x228
						
							
								usb_rcv
								27
								27
							
							
								usb_vip
								26
								26
							
							
								usb_vim
								25
								25
							
							
								usb_bd
								24
								24
							
							
								pu_usb
								23
								23
							
							
								usb_sus
								22
								22
							
							
								usb_spd
								21
								21
							
							
								usb_enum
								20
								20
							
							
								usb_data_convert
								16
								16
							
							
								usb_oeb
								14
								14
							
							
								usb_oeb_reg
								13
								13
							
							
								usb_oeb_sel
								12
								12
							
							
								usb_rout_pmos
								8
								10
							
							
								usb_rout_nmos
								4
								6
							
							
								pu_usb_ldo
								3
								3
							
							
								usb_ldo_vfb
								0
								2
							
						
					
					
						usb_xcvr_config
						usb_xcvr_config.
						0x22C
						
							
								usb_slewrate_p_rise
								28
								30
							
							
								usb_slewrate_p_fall
								24
								26
							
							
								usb_slewrate_m_rise
								20
								22
							
							
								usb_slewrate_m_fall
								16
								18
							
							
								usb_res_pullup_tune
								12
								14
							
							
								reg_usb_use_ctrl
								11
								11
							
							
								usb_str_drv
								8
								10
							
							
								reg_usb_use_xcvr
								7
								7
							
							
								usb_bd_vth
								4
								6
							
							
								usb_v_hys_p
								2
								3
							
							
								usb_v_hys_m
								0
								1
							
						
					
					
						gpdac_ctrl
						gpdac_ctrl.
						0x308
						
							
								gpdac_reserved
								24
								31
							
							
								gpdac_test_sel
								9
								11
							
							
								gpdac_ref_sel
								8
								8
							
							
								gpdac_test_en
								7
								7
							
							
								gpdacb_rstn_ana
								1
								1
							
							
								gpdaca_rstn_ana
								0
								0
							
						
					
					
						gpdac_actrl
						gpdac_actrl.
						0x30C
						
							
								gpdac_a_outmux
								20
								22
							
							
								gpdac_a_rng
								18
								19
							
							
								gpdac_ioa_en
								1
								1
							
							
								gpdac_a_en
								0
								0
							
						
					
					
						gpdac_bctrl
						gpdac_bctrl.
						0x310
						
							
								gpdac_b_outmux
								20
								22
							
							
								gpdac_b_rng
								18
								19
							
							
								gpdac_iob_en
								1
								1
							
							
								gpdac_b_en
								0
								0
							
						
					
					
						gpdac_data
						gpdac_data.
						0x314
						
							
								gpdac_a_data
								16
								25
							
							
								gpdac_b_data
								0
								9
							
						
					
					
						chip_revision
						chip_revision.
						0xE00
						
							
								chip_rev
								0
								3
							
						
					
					
						tzc_glb_ctrl_0
						tzc_glb_ctrl_0.
						0xF00
						
							
								tzc_glb_clk_lock
								31
								31
							
							
								tzc_glb_mbist_lock
								30
								30
							
							
								tzc_glb_dbg_lock
								29
								29
							
							
								tzc_glb_bmx_lock
								28
								28
							
							
								tzc_glb_l2c_lock
								27
								27
							
							
								tzc_glb_sram_lock
								26
								26
							
							
								tzc_glb_misc_lock
								25
								25
							
							
								tzc_glb_ctrl_ungated_ap_lock
								15
								15
							
							
								tzc_glb_ctrl_sys_reset_lock
								14
								14
							
							
								tzc_glb_ctrl_cpu_reset_lock
								13
								13
							
							
								tzc_glb_ctrl_pwron_rst_lock
								12
								12
							
							
								tzc_glb_swrst_s30_lock
								8
								8
							
							
								tzc_glb_swrst_s01_lock
								1
								1
							
							
								tzc_glb_swrst_s00_lock
								0
								0
							
						
					
					
						tzc_glb_ctrl_1
						tzc_glb_ctrl_1.
						0xF04
						
							
								tzc_glb_swrst_s1f_lock
								31
								31
							
							
								tzc_glb_swrst_s1e_lock
								30
								30
							
							
								tzc_glb_swrst_s1d_lock
								29
								29
							
							
								tzc_glb_swrst_s1c_lock
								28
								28
							
							
								tzc_glb_swrst_s1b_lock
								27
								27
							
							
								tzc_glb_swrst_s1a_lock
								26
								26
							
							
								tzc_glb_swrst_s19_lock
								25
								25
							
							
								tzc_glb_swrst_s18_lock
								24
								24
							
							
								tzc_glb_swrst_s17_lock
								23
								23
							
							
								tzc_glb_swrst_s16_lock
								22
								22
							
							
								tzc_glb_swrst_s15_lock
								21
								21
							
							
								tzc_glb_swrst_s14_lock
								20
								20
							
							
								tzc_glb_swrst_s13_lock
								19
								19
							
							
								tzc_glb_swrst_s12_lock
								18
								18
							
							
								tzc_glb_swrst_s11_lock
								17
								17
							
							
								tzc_glb_swrst_s10_lock
								16
								16
							
							
								tzc_glb_swrst_s2f_lock
								15
								15
							
							
								tzc_glb_swrst_s2e_lock
								14
								14
							
							
								tzc_glb_swrst_s2d_lock
								13
								13
							
							
								tzc_glb_swrst_s2c_lock
								12
								12
							
							
								tzc_glb_swrst_s2b_lock
								11
								11
							
							
								tzc_glb_swrst_s2a_lock
								10
								10
							
							
								tzc_glb_swrst_s29_lock
								9
								9
							
							
								tzc_glb_swrst_s28_lock
								8
								8
							
							
								tzc_glb_swrst_s27_lock
								7
								7
							
							
								tzc_glb_swrst_s26_lock
								6
								6
							
							
								tzc_glb_swrst_s25_lock
								5
								5
							
							
								tzc_glb_swrst_s24_lock
								4
								4
							
							
								tzc_glb_swrst_s23_lock
								3
								3
							
							
								tzc_glb_swrst_s22_lock
								2
								2
							
							
								tzc_glb_swrst_s21_lock
								1
								1
							
							
								tzc_glb_swrst_s20_lock
								0
								0
							
						
					
					
						tzc_glb_ctrl_2
						tzc_glb_ctrl_2.
						0xF08
						
							
								tzc_glb_gpio_31_lock
								31
								31
							
							
								tzc_glb_gpio_30_lock
								30
								30
							
							
								tzc_glb_gpio_29_lock
								29
								29
							
							
								tzc_glb_gpio_28_lock
								28
								28
							
							
								tzc_glb_gpio_27_lock
								27
								27
							
							
								tzc_glb_gpio_26_lock
								26
								26
							
							
								tzc_glb_gpio_25_lock
								25
								25
							
							
								tzc_glb_gpio_24_lock
								24
								24
							
							
								tzc_glb_gpio_23_lock
								23
								23
							
							
								tzc_glb_gpio_22_lock
								22
								22
							
							
								tzc_glb_gpio_21_lock
								21
								21
							
							
								tzc_glb_gpio_20_lock
								20
								20
							
							
								tzc_glb_gpio_19_lock
								19
								19
							
							
								tzc_glb_gpio_18_lock
								18
								18
							
							
								tzc_glb_gpio_17_lock
								17
								17
							
							
								tzc_glb_gpio_16_lock
								16
								16
							
							
								tzc_glb_gpio_15_lock
								15
								15
							
							
								tzc_glb_gpio_14_lock
								14
								14
							
							
								tzc_glb_gpio_13_lock
								13
								13
							
							
								tzc_glb_gpio_12_lock
								12
								12
							
							
								tzc_glb_gpio_11_lock
								11
								11
							
							
								tzc_glb_gpio_10_lock
								10
								10
							
							
								tzc_glb_gpio_9_lock
								9
								9
							
							
								tzc_glb_gpio_8_lock
								8
								8
							
							
								tzc_glb_gpio_7_lock
								7
								7
							
							
								tzc_glb_gpio_6_lock
								6
								6
							
							
								tzc_glb_gpio_5_lock
								5
								5
							
							
								tzc_glb_gpio_4_lock
								4
								4
							
							
								tzc_glb_gpio_3_lock
								3
								3
							
							
								tzc_glb_gpio_2_lock
								2
								2
							
							
								tzc_glb_gpio_1_lock
								1
								1
							
							
								tzc_glb_gpio_0_lock
								0
								0
							
						
					
					
						tzc_glb_ctrl_3
						tzc_glb_ctrl_3.
						0xF0C
						
							
								tzc_glb_gpio_37_lock
								5
								5
							
							
								tzc_glb_gpio_36_lock
								4
								4
							
							
								tzc_glb_gpio_35_lock
								3
								3
							
							
								tzc_glb_gpio_34_lock
								2
								2
							
							
								tzc_glb_gpio_33_lock
								1
								1
							
							
								tzc_glb_gpio_32_lock
								0
								0
							
						
					
				
			
			
				gpip
				gpip.
				0x40002000
				gpip
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						gpadc_config
						gpadc_config.
						0x0
						
							
								rsvd_31_24
								24
								31
							
							
								gpadc_fifo_thl
								22
								23
							
							
								gpadc_fifo_data_count
								16
								21
							
							
								gpadc_fifo_rdy_mask
								15
								15
							
							
								gpadc_fifo_underrun_mask
								14
								14
							
							
								gpadc_fifo_overrun_mask
								13
								13
							
							
								gpadc_rdy_mask
								12
								12
							
							
								gpadc_fifo_underrun_clr
								10
								10
							
							
								gpadc_fifo_overrun_clr
								9
								9
							
							
								gpadc_rdy_clr
								8
								8
							
							
								gpadc_fifo_rdy
								7
								7
							
							
								gpadc_fifo_underrun
								6
								6
							
							
								gpadc_fifo_overrun
								5
								5
							
							
								gpadc_rdy
								4
								4
							
							
								gpadc_fifo_full
								3
								3
							
							
								gpadc_fifo_ne
								2
								2
							
							
								gpadc_fifo_clr
								1
								1
							
							
								gpadc_dma_en
								0
								0
							
						
					
					
						gpadc_dma_rdata
						gpadc_dma_rdata.
						0x4
						
							
								rsvd_31_26
								26
								31
							
							
								gpadc_dma_rdata
								0
								25
							
						
					
					
						gpdac_config
						gpdac_config.
						0x40
						
							
								rsvd_31_24
								24
								31
							
							
								gpdac_ch_b_sel
								20
								23
							
							
								gpdac_ch_a_sel
								16
								19
							
							
								gpdac_mode
								8
								10
							
							
								dsm_mode
								4
								5
							
							
								gpdac_en2
								1
								1
							
							
								gpdac_en
								0
								0
							
						
					
					
						gpdac_dma_config
						gpdac_dma_config.
						0x44
						
							
								gpdac_dma_format
								4
								5
							
							
								gpdac_dma_tx_en
								0
								0
							
						
					
					
						gpdac_dma_wdata
						gpdac_dma_wdata.
						0x48
						
							
								gpdac_dma_wdata
								0
								31
							
						
					
					
						gpdac_tx_fifo_status
						gpdac_tx_fifo_status.
						0x4C
						
							
								TxFifoWrPtr
								8
								9
							
							
								TxFifoRdPtr
								4
								6
							
							
								tx_cs
								2
								3
							
							
								tx_fifo_full
								1
								1
							
							
								tx_fifo_empty
								0
								0
							
						
					
				
			
			
				sec_dbg
				sec_dbg.
				0x40003000
				sec_dbg
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						sd_chip_id_low
						sd_chip_id_low.
						0x0
						
							
								sd_chip_id_low
								0
								31
							
						
					
					
						sd_chip_id_high
						sd_chip_id_high.
						0x4
						
							
								sd_chip_id_high
								0
								31
							
						
					
					
						sd_wifi_mac_low
						sd_wifi_mac_low.
						0x8
						
							
								sd_wifi_mac_low
								0
								31
							
						
					
					
						sd_wifi_mac_high
						sd_wifi_mac_high.
						0xC
						
							
								sd_wifi_mac_high
								0
								31
							
						
					
					
						sd_dbg_pwd_low
						sd_dbg_pwd_low.
						0x10
						
							
								sd_dbg_pwd_low
								0
								31
							
						
					
					
						sd_dbg_pwd_high
						sd_dbg_pwd_high.
						0x14
						
							
								sd_dbg_pwd_high
								0
								31
							
						
					
					
						sd_status
						sd_status.
						0x18
						
							
								sd_dbg_ena
								28
								31
							
							
								sd_dbg_mode
								24
								27
							
							
								sd_dbg_pwd_cnt
								4
								23
							
							
								sd_dbg_cci_clk_sel
								3
								3
							
							
								sd_dbg_cci_read_en
								2
								2
							
							
								sd_dbg_pwd_trig
								1
								1
							
							
								sd_dbg_pwd_busy
								0
								0
							
						
					
					
						sd_dbg_reserved
						sd_dbg_reserved.
						0x1C
						
							
								sd_dbg_reserved
								0
								31
							
						
					
				
			
			
				sec_eng
				sec_eng.
				0x40004000
				sec_eng
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						se_sha_0_ctrl
						se_sha_0_ctrl.
						0x0
						
							
								se_sha_0_msg_len
								16
								31
							
							
								se_sha_0_link_mode
								15
								15
							
							
								se_sha_0_int_mask
								11
								11
							
							
								se_sha_0_int_set_1t
								10
								10
							
							
								se_sha_0_int_clr_1t
								9
								9
							
							
								se_sha_0_int
								8
								8
							
							
								se_sha_0_hash_sel
								6
								6
							
							
								se_sha_0_en
								5
								5
							
							
								se_sha_0_mode
								2
								4
							
							
								se_sha_0_trig_1t
								1
								1
							
							
								se_sha_0_busy
								0
								0
							
						
					
					
						se_sha_0_msa
						se_sha_0_msa.
						0x4
						
							
								se_sha_0_msa
								0
								31
							
						
					
					
						se_sha_0_status
						se_sha_0_status.
						0x8
						
							
								se_sha_0_status
								0
								31
							
						
					
					
						se_sha_0_endian
						se_sha_0_endian.
						0xC
						
							
								se_sha_0_dout_endian
								0
								0
							
						
					
					
						se_sha_0_hash_l_0
						se_sha_0_hash_l_0.
						0x10
						
							
								se_sha_0_hash_l_0
								0
								31
							
						
					
					
						se_sha_0_hash_l_1
						se_sha_0_hash_l_1.
						0x14
						
							
								se_sha_0_hash_l_1
								0
								31
							
						
					
					
						se_sha_0_hash_l_2
						se_sha_0_hash_l_2.
						0x18
						
							
								se_sha_0_hash_l_2
								0
								31
							
						
					
					
						se_sha_0_hash_l_3
						se_sha_0_hash_l_3.
						0x1C
						
							
								se_sha_0_hash_l_3
								0
								31
							
						
					
					
						se_sha_0_hash_l_4
						se_sha_0_hash_l_4.
						0x20
						
							
								se_sha_0_hash_l_4
								0
								31
							
						
					
					
						se_sha_0_hash_l_5
						se_sha_0_hash_l_5.
						0x24
						
							
								se_sha_0_hash_l_5
								0
								31
							
						
					
					
						se_sha_0_hash_l_6
						se_sha_0_hash_l_6.
						0x28
						
							
								se_sha_0_hash_l_6
								0
								31
							
						
					
					
						se_sha_0_hash_l_7
						se_sha_0_hash_l_7.
						0x2C
						
							
								se_sha_0_hash_l_7
								0
								31
							
						
					
					
						se_sha_0_hash_h_0
						se_sha_0_hash_h_0.
						0x30
						
							
								se_sha_0_hash_h_0
								0
								31
							
						
					
					
						se_sha_0_hash_h_1
						se_sha_0_hash_h_1.
						0x34
						
							
								se_sha_0_hash_h_1
								0
								31
							
						
					
					
						se_sha_0_hash_h_2
						se_sha_0_hash_h_2.
						0x38
						
							
								se_sha_0_hash_h_2
								0
								31
							
						
					
					
						se_sha_0_hash_h_3
						se_sha_0_hash_h_3.
						0x3C
						
							
								se_sha_0_hash_h_3
								0
								31
							
						
					
					
						se_sha_0_hash_h_4
						se_sha_0_hash_h_4.
						0x40
						
							
								se_sha_0_hash_h_4
								0
								31
							
						
					
					
						se_sha_0_hash_h_5
						se_sha_0_hash_h_5.
						0x44
						
							
								se_sha_0_hash_h_5
								0
								31
							
						
					
					
						se_sha_0_hash_h_6
						se_sha_0_hash_h_6.
						0x48
						
							
								se_sha_0_hash_h_6
								0
								31
							
						
					
					
						se_sha_0_hash_h_7
						se_sha_0_hash_h_7.
						0x4C
						
							
								se_sha_0_hash_h_7
								0
								31
							
						
					
					
						se_sha_0_link
						se_sha_0_link.
						0x50
						
							
								se_sha_0_lca
								0
								31
							
						
					
					
						se_sha_0_ctrl_prot
						se_sha_0_ctrl_prot.
						0xFC
						
							
								se_sha_id1_en
								2
								2
							
							
								se_sha_id0_en
								1
								1
							
							
								se_sha_prot_en
								0
								0
							
						
					
					
						se_aes_0_ctrl
						se_aes_0_ctrl.
						0x100
						
							
								se_aes_0_msg_len
								16
								31
							
							
								se_aes_0_link_mode
								15
								15
							
							
								se_aes_0_iv_sel
								14
								14
							
							
								se_aes_0_block_mode
								12
								13
							
							
								se_aes_0_int_mask
								11
								11
							
							
								se_aes_0_int_set_1t
								10
								10
							
							
								se_aes_0_int_clr_1t
								9
								9
							
							
								se_aes_0_int
								8
								8
							
							
								se_aes_0_hw_key_en
								7
								7
							
							
								se_aes_0_dec_key_sel
								6
								6
							
							
								se_aes_0_dec_en
								5
								5
							
							
								se_aes_0_mode
								3
								4
							
							
								se_aes_0_en
								2
								2
							
							
								se_aes_0_trig_1t
								1
								1
							
							
								se_aes_0_busy
								0
								0
							
						
					
					
						se_aes_0_msa
						se_aes_0_msa.
						0x104
						
							
								se_aes_0_msa
								0
								31
							
						
					
					
						se_aes_0_mda
						se_aes_0_mda.
						0x108
						
							
								se_aes_0_mda
								0
								31
							
						
					
					
						se_aes_0_status
						se_aes_0_status.
						0x10C
						
							
								se_aes_0_status
								0
								31
							
						
					
					
						se_aes_0_iv_0
						se_aes_0_iv_0.
						0x110
						
							
								se_aes_0_iv_0
								0
								31
							
						
					
					
						se_aes_0_iv_1
						se_aes_0_iv_1.
						0x114
						
							
								se_aes_0_iv_1
								0
								31
							
						
					
					
						se_aes_0_iv_2
						se_aes_0_iv_2.
						0x118
						
							
								se_aes_0_iv_2
								0
								31
							
						
					
					
						se_aes_0_iv_3
						se_aes_0_iv_3.
						0x11C
						
							
								se_aes_0_iv_3
								0
								31
							
						
					
					
						se_aes_0_key_0
						se_aes_0_key_0.
						0x120
						
							
								se_aes_0_key_0
								0
								31
							
						
					
					
						se_aes_0_key_1
						se_aes_0_key_1.
						0x124
						
							
								se_aes_0_key_1
								0
								31
							
						
					
					
						se_aes_0_key_2
						se_aes_0_key_2.
						0x128
						
							
								se_aes_0_key_2
								0
								31
							
						
					
					
						se_aes_0_key_3
						se_aes_0_key_3.
						0x12C
						
							
								se_aes_0_key_3
								0
								31
							
						
					
					
						se_aes_0_key_4
						se_aes_0_key_4.
						0x130
						
							
								se_aes_0_key_4
								0
								31
							
						
					
					
						se_aes_0_key_5
						se_aes_0_key_5.
						0x134
						
							
								se_aes_0_key_5
								0
								31
							
						
					
					
						se_aes_0_key_6
						se_aes_0_key_6.
						0x138
						
							
								se_aes_0_key_6
								0
								31
							
						
					
					
						se_aes_0_key_7
						se_aes_0_key_7.
						0x13C
						
							
								se_aes_0_key_7
								0
								31
							
						
					
					
						se_aes_0_key_sel_0
						se_aes_0_key_sel_0.
						0x140
						
							
								se_aes_0_key_sel_0
								0
								1
							
						
					
					
						se_aes_0_key_sel_1
						se_aes_0_key_sel_1.
						0x144
						
							
								se_aes_0_key_sel_1
								0
								1
							
						
					
					
						se_aes_0_endian
						se_aes_0_endian.
						0x148
						
							
								se_aes_0_ctr_len
								30
								31
							
							
								se_aes_0_iv_endian
								3
								3
							
							
								se_aes_0_key_endian
								2
								2
							
							
								se_aes_0_din_endian
								1
								1
							
							
								se_aes_0_dout_endian
								0
								0
							
						
					
					
						se_aes_0_sboot
						se_aes_0_sboot.
						0x14C
						
							
								se_aes_0_sboot_key_sel
								0
								0
							
						
					
					
						se_aes_0_link
						se_aes_0_link.
						0x150
						
							
								se_aes_0_lca
								0
								31
							
						
					
					
						se_aes_0_ctrl_prot
						se_aes_0_ctrl_prot.
						0x1FC
						
							
								se_aes_id1_en
								2
								2
							
							
								se_aes_id0_en
								1
								1
							
							
								se_aes_prot_en
								0
								0
							
						
					
					
						se_trng_0_ctrl_0
						se_trng_0_ctrl_0.
						0x200
						
							
								se_trng_0_manual_en
								15
								15
							
							
								se_trng_0_manual_reseed
								14
								14
							
							
								se_trng_0_manual_fun_sel
								13
								13
							
							
								se_trng_0_int_mask
								11
								11
							
							
								se_trng_0_int_set_1t
								10
								10
							
							
								se_trng_0_int_clr_1t
								9
								9
							
							
								se_trng_0_int
								8
								8
							
							
								se_trng_0_ht_error
								4
								4
							
							
								se_trng_0_dout_clr_1t
								3
								3
							
							
								se_trng_0_en
								2
								2
							
							
								se_trng_0_trig_1t
								1
								1
							
							
								se_trng_0_busy
								0
								0
							
						
					
					
						se_trng_0_status
						se_trng_0_status.
						0x204
						
							
								se_trng_0_status
								0
								31
							
						
					
					
						se_trng_0_dout_0
						se_trng_0_dout_0.
						0x208
						
							
								se_trng_0_dout_0
								0
								31
							
						
					
					
						se_trng_0_dout_1
						se_trng_0_dout_1.
						0x20C
						
							
								se_trng_0_dout_1
								0
								31
							
						
					
					
						se_trng_0_dout_2
						se_trng_0_dout_2.
						0x210
						
							
								se_trng_0_dout_2
								0
								31
							
						
					
					
						se_trng_0_dout_3
						se_trng_0_dout_3.
						0x214
						
							
								se_trng_0_dout_3
								0
								31
							
						
					
					
						se_trng_0_dout_4
						se_trng_0_dout_4.
						0x218
						
							
								se_trng_0_dout_4
								0
								31
							
						
					
					
						se_trng_0_dout_5
						se_trng_0_dout_5.
						0x21C
						
							
								se_trng_0_dout_5
								0
								31
							
						
					
					
						se_trng_0_dout_6
						se_trng_0_dout_6.
						0x220
						
							
								se_trng_0_dout_6
								0
								31
							
						
					
					
						se_trng_0_dout_7
						se_trng_0_dout_7.
						0x224
						
							
								se_trng_0_dout_7
								0
								31
							
						
					
					
						se_trng_0_test
						se_trng_0_test.
						0x228
						
							
								se_trng_0_ht_alarm_n
								4
								11
							
							
								se_trng_0_ht_dis
								3
								3
							
							
								se_trng_0_cp_bypass
								2
								2
							
							
								se_trng_0_cp_test_en
								1
								1
							
							
								se_trng_0_test_en
								0
								0
							
						
					
					
						se_trng_0_ctrl_1
						se_trng_0_ctrl_1.
						0x22C
						
							
								se_trng_0_reseed_n_lsb
								0
								31
							
						
					
					
						se_trng_0_ctrl_2
						se_trng_0_ctrl_2.
						0x230
						
							
								se_trng_0_reseed_n_msb
								0
								15
							
						
					
					
						se_trng_0_ctrl_3
						se_trng_0_ctrl_3.
						0x234
						
							
								se_trng_0_rosc_en
								31
								31
							
							
								se_trng_0_ht_od_en
								26
								26
							
							
								se_trng_0_ht_apt_c
								16
								25
							
							
								se_trng_0_ht_rct_c
								8
								15
							
							
								se_trng_0_cp_ratio
								0
								7
							
						
					
					
						se_trng_0_test_out_0
						se_trng_0_test_out_0.
						0x240
						
							
								se_trng_0_test_out_0
								0
								31
							
						
					
					
						se_trng_0_test_out_1
						se_trng_0_test_out_1.
						0x244
						
							
								se_trng_0_test_out_1
								0
								31
							
						
					
					
						se_trng_0_test_out_2
						se_trng_0_test_out_2.
						0x248
						
							
								se_trng_0_test_out_2
								0
								31
							
						
					
					
						se_trng_0_test_out_3
						se_trng_0_test_out_3.
						0x24C
						
							
								se_trng_0_test_out_3
								0
								31
							
						
					
					
						se_trng_0_ctrl_prot
						se_trng_0_ctrl_prot.
						0x2FC
						
							
								se_trng_id1_en
								2
								2
							
							
								se_trng_id0_en
								1
								1
							
							
								se_trng_prot_en
								0
								0
							
						
					
					
						se_pka_0_ctrl_0
						se_pka_0_ctrl_0.
						0x300
						
							
								se_pka_0_status
								16
								31
							
							
								se_pka_0_status_clr_1t
								15
								15
							
							
								se_pka_0_ram_clr_md
								13
								13
							
							
								se_pka_0_endian
								12
								12
							
							
								se_pka_0_int_mask
								11
								11
							
							
								se_pka_0_int_set
								10
								10
							
							
								se_pka_0_int_clr_1t
								9
								9
							
							
								se_pka_0_int
								8
								8
							
							
								se_pka_0_prot_md
								4
								7
							
							
								se_pka_0_en
								3
								3
							
							
								se_pka_0_busy
								2
								2
							
							
								se_pka_0_done_clr_1t
								1
								1
							
							
								se_pka_0_done
								0
								0
							
						
					
					
						se_pka_0_seed
						se_pka_0_seed.
						0x30C
						
							
								se_pka_0_seed
								0
								31
							
						
					
					
						se_pka_0_ctrl_1
						se_pka_0_ctrl_1.
						0x310
						
							
								se_pka_0_hbypass
								3
								3
							
							
								se_pka_0_hburst
								0
								2
							
						
					
					
						se_pka_0_rw
						se_pka_0_rw.
						0x340
						
					
					
						se_pka_0_rw_burst
						se_pka_0_rw_burst.
						0x360
						
					
					
						se_pka_0_ctrl_prot
						se_pka_0_ctrl_prot.
						0x3FC
						
							
								se_pka_id1_en
								2
								2
							
							
								se_pka_id0_en
								1
								1
							
							
								se_pka_prot_en
								0
								0
							
						
					
					
						se_cdet_0_ctrl_0
						se_cdet_0_ctrl_0.
						0x400
						
							
								se_cdet_0_g_loop_min
								24
								31
							
							
								se_cdet_0_g_loop_max
								16
								23
							
							
								se_cdet_0_status
								2
								15
							
							
								se_cdet_0_error
								1
								1
							
							
								se_cdet_0_en
								0
								0
							
						
					
					
						se_cdet_0_ctrl_1
						se_cdet_0_ctrl_1.
						0x404
						
							
								se_cdet_0_g_slp_n
								16
								23
							
							
								se_cdet_0_t_dly_n
								8
								15
							
							
								se_cdet_0_t_loop_n
								0
								7
							
						
					
					
						se_cdet_0_ctrl_prot
						se_cdet_0_ctrl_prot.
						0x4FC
						
							
								se_cdet_id1_en
								2
								2
							
							
								se_cdet_id0_en
								1
								1
							
							
								se_cdet_prot_en
								0
								0
							
						
					
					
						se_gmac_0_ctrl_0
						se_gmac_0_ctrl_0.
						0x500
						
							
								se_gmac_0_x_endian
								14
								14
							
							
								se_gmac_0_h_endian
								13
								13
							
							
								se_gmac_0_t_endian
								12
								12
							
							
								se_gmac_0_int_mask
								11
								11
							
							
								se_gmac_0_int_set_1t
								10
								10
							
							
								se_gmac_0_int_clr_1t
								9
								9
							
							
								se_gmac_0_int
								8
								8
							
							
								se_gmac_0_en
								2
								2
							
							
								se_gmac_0_trig_1t
								1
								1
							
							
								se_gmac_0_busy
								0
								0
							
						
					
					
						se_gmac_0_lca
						se_gmac_0_lca.
						0x504
						
							
								se_gmac_0_lca
								0
								31
							
						
					
					
						se_gmac_0_status
						se_gmac_0_status.
						0x508
						
							
								se_gmac_0_status
								0
								31
							
						
					
					
						se_gmac_0_ctrl_prot
						se_gmac_0_ctrl_prot.
						0x5FC
						
							
								se_gmac_id1_en
								2
								2
							
							
								se_gmac_id0_en
								1
								1
							
							
								se_gmac_prot_en
								0
								0
							
						
					
					
						se_ctrl_prot_rd
						se_ctrl_prot_rd.
						0xF00
						
							
								se_dbg_dis
								31
								31
							
							
								se_gmac_id1_en_rd
								22
								22
							
							
								se_gmac_id0_en_rd
								21
								21
							
							
								se_gmac_prot_en_rd
								20
								20
							
							
								se_cdet_id1_en_rd
								18
								18
							
							
								se_cdet_id0_en_rd
								17
								17
							
							
								se_cdet_prot_en_rd
								16
								16
							
							
								se_pka_id1_en_rd
								14
								14
							
							
								se_pka_id0_en_rd
								13
								13
							
							
								se_pka_prot_en_rd
								12
								12
							
							
								se_trng_id1_en_rd
								10
								10
							
							
								se_trng_id0_en_rd
								9
								9
							
							
								se_trng_prot_en_rd
								8
								8
							
							
								se_aes_id1_en_rd
								6
								6
							
							
								se_aes_id0_en_rd
								5
								5
							
							
								se_aes_prot_en_rd
								4
								4
							
							
								se_sha_id1_en_rd
								2
								2
							
							
								se_sha_id0_en_rd
								1
								1
							
							
								se_sha_prot_en_rd
								0
								0
							
						
					
					
						se_ctrl_reserved_0
						se_ctrl_reserved_0.
						0xF04
						
							
								se_ctrl_reserved_0
								0
								31
							
						
					
					
						se_ctrl_reserved_1
						se_ctrl_reserved_1.
						0xF08
						
							
								se_ctrl_reserved_1
								0
								31
							
						
					
					
						se_ctrl_reserved_2
						se_ctrl_reserved_2.
						0xF0C
						
							
								se_ctrl_reserved_2
								0
								31
							
						
					
				
			
			
				tzc_sec
				tzc_sec.
				0x40005000
				tzc_sec
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						tzc_rom_ctrl
						tzc_rom_ctrl.
						0x40
						
							
								tzc_sboot_done
								28
								31
							
							
								tzc_rom1_r1_lock
								27
								27
							
							
								tzc_rom1_r0_lock
								26
								26
							
							
								tzc_rom0_r1_lock
								25
								25
							
							
								tzc_rom0_r0_lock
								24
								24
							
							
								tzc_rom1_r1_en
								19
								19
							
							
								tzc_rom1_r0_en
								18
								18
							
							
								tzc_rom0_r1_en
								17
								17
							
							
								tzc_rom0_r0_en
								16
								16
							
							
								tzc_rom1_r1_id1_en
								11
								11
							
							
								tzc_rom1_r0_id1_en
								10
								10
							
							
								tzc_rom0_r1_id1_en
								9
								9
							
							
								tzc_rom0_r0_id1_en
								8
								8
							
							
								tzc_rom1_r1_id0_en
								3
								3
							
							
								tzc_rom1_r0_id0_en
								2
								2
							
							
								tzc_rom0_r1_id0_en
								1
								1
							
							
								tzc_rom0_r0_id0_en
								0
								0
							
						
					
					
						tzc_rom0_r0
						tzc_rom0_r0.
						0x44
						
							
								tzc_rom0_r0_start
								16
								31
							
							
								tzc_rom0_r0_end
								0
								15
							
						
					
					
						tzc_rom0_r1
						tzc_rom0_r1.
						0x48
						
							
								tzc_rom0_r1_start
								16
								31
							
							
								tzc_rom0_r1_end
								0
								15
							
						
					
					
						tzc_rom1_r0
						tzc_rom1_r0.
						0x4C
						
							
								tzc_rom1_r0_start
								16
								31
							
							
								tzc_rom1_r0_end
								0
								15
							
						
					
					
						tzc_rom1_r1
						tzc_rom1_r1.
						0x50
						
							
								tzc_rom1_r1_start
								16
								31
							
							
								tzc_rom1_r1_end
								0
								15
							
						
					
				
			
			
				tzc_nsec
				tzc_nsec.
				0x40006000
				tzc_nsec
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						tzc_rom_ctrl
						tzc_rom_ctrl.
						0x40
						
							
								tzc_sboot_done
								28
								31
							
							
								tzc_rom1_r1_lock
								27
								27
							
							
								tzc_rom1_r0_lock
								26
								26
							
							
								tzc_rom0_r1_lock
								25
								25
							
							
								tzc_rom0_r0_lock
								24
								24
							
							
								tzc_rom1_r1_en
								19
								19
							
							
								tzc_rom1_r0_en
								18
								18
							
							
								tzc_rom0_r1_en
								17
								17
							
							
								tzc_rom0_r0_en
								16
								16
							
							
								tzc_rom1_r1_id1_en
								11
								11
							
							
								tzc_rom1_r0_id1_en
								10
								10
							
							
								tzc_rom0_r1_id1_en
								9
								9
							
							
								tzc_rom0_r0_id1_en
								8
								8
							
							
								tzc_rom1_r1_id0_en
								3
								3
							
							
								tzc_rom1_r0_id0_en
								2
								2
							
							
								tzc_rom0_r1_id0_en
								1
								1
							
							
								tzc_rom0_r0_id0_en
								0
								0
							
						
					
					
						tzc_rom0_r0
						tzc_rom0_r0.
						0x44
						
							
								tzc_rom0_r0_start
								16
								31
							
							
								tzc_rom0_r0_end
								0
								15
							
						
					
					
						tzc_rom0_r1
						tzc_rom0_r1.
						0x48
						
							
								tzc_rom0_r1_start
								16
								31
							
							
								tzc_rom0_r1_end
								0
								15
							
						
					
					
						tzc_rom1_r0
						tzc_rom1_r0.
						0x4C
						
							
								tzc_rom1_r0_start
								16
								31
							
							
								tzc_rom1_r0_end
								0
								15
							
						
					
					
						tzc_rom1_r1
						tzc_rom1_r1.
						0x50
						
							
								tzc_rom1_r1_start
								16
								31
							
							
								tzc_rom1_r1_end
								0
								15
							
						
					
				
			
			
				ef_data_0
				ef_data_0.
				0x40007000
				ef_data_0
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						ef_cfg_0
						ef_cfg_0.
						0x0
						
							
								ef_dbg_mode
								28
								31
							
							
								ef_dbg_jtag_0_dis
								26
								27
							
							
								ef_dbg_jtag_1_dis
								24
								25
							
							
								ef_efuse_dbg_dis
								23
								23
							
							
								ef_se_dbg_dis
								22
								22
							
							
								ef_cpu_rst_dbg_dis
								21
								21
							
							
								ef_cpu1_dis
								20
								20
							
							
								ef_sf_dis
								19
								19
							
							
								ef_cam_dis
								18
								18
							
							
								ef_0_key_enc_en
								17
								17
							
							
								ef_wifi_dis
								16
								16
							
							
								ef_ble_dis
								15
								15
							
							
								ef_sdu_dis
								14
								14
							
							
								ef_sf_key_0_sel
								12
								13
							
							
								ef_boot_sel
								8
								11
							
							
								ef_cpu0_enc_en
								7
								7
							
							
								ef_cpu1_enc_en
								6
								6
							
							
								ef_sboot_en
								4
								5
							
							
								ef_sboot_sign_mode
								2
								3
							
							
								ef_sf_aes_mode
								0
								1
							
						
					
					
						ef_dbg_pwd_low
						ef_dbg_pwd_low.
						0x4
						
							
								ef_dbg_pwd_low
								0
								31
							
						
					
					
						ef_dbg_pwd_high
						ef_dbg_pwd_high.
						0x8
						
							
								ef_dbg_pwd_high
								0
								31
							
						
					
					
						ef_ana_trim_0
						ef_ana_trim_0.
						0xC
						
							
								ef_ana_trim_0
								0
								31
							
						
					
					
						ef_sw_usage_0
						ef_sw_usage_0.
						0x10
						
							
								ef_sw_usage_0
								0
								31
							
						
					
					
						ef_wifi_mac_low
						ef_wifi_mac_low.
						0x14
						
							
								ef_wifi_mac_low
								0
								31
							
						
					
					
						ef_wifi_mac_high
						ef_wifi_mac_high.
						0x18
						
							
								ef_wifi_mac_high
								0
								31
							
						
					
					
						ef_key_slot_0_w0
						ef_key_slot_0_w0.
						0x1C
						
							
								ef_key_slot_0_w0
								0
								31
							
						
					
					
						ef_key_slot_0_w1
						ef_key_slot_0_w1.
						0x20
						
							
								ef_key_slot_0_w1
								0
								31
							
						
					
					
						ef_key_slot_0_w2
						ef_key_slot_0_w2.
						0x24
						
							
								ef_key_slot_0_w2
								0
								31
							
						
					
					
						ef_key_slot_0_w3
						ef_key_slot_0_w3.
						0x28
						
							
								ef_key_slot_0_w3
								0
								31
							
						
					
					
						ef_key_slot_1_w0
						ef_key_slot_1_w0.
						0x2C
						
							
								ef_key_slot_1_w0
								0
								31
							
						
					
					
						ef_key_slot_1_w1
						ef_key_slot_1_w1.
						0x30
						
							
								ef_key_slot_1_w1
								0
								31
							
						
					
					
						ef_key_slot_1_w2
						ef_key_slot_1_w2.
						0x34
						
							
								ef_key_slot_1_w2
								0
								31
							
						
					
					
						ef_key_slot_1_w3
						ef_key_slot_1_w3.
						0x38
						
							
								ef_key_slot_1_w3
								0
								31
							
						
					
					
						ef_key_slot_2_w0
						ef_key_slot_2_w0.
						0x3C
						
							
								ef_key_slot_2_w0
								0
								31
							
						
					
					
						ef_key_slot_2_w1
						ef_key_slot_2_w1.
						0x40
						
							
								ef_key_slot_2_w1
								0
								31
							
						
					
					
						ef_key_slot_2_w2
						ef_key_slot_2_w2.
						0x44
						
							
								ef_key_slot_2_w2
								0
								31
							
						
					
					
						ef_key_slot_2_w3
						ef_key_slot_2_w3.
						0x48
						
							
								ef_key_slot_2_w3
								0
								31
							
						
					
					
						ef_key_slot_3_w0
						ef_key_slot_3_w0.
						0x4C
						
							
								ef_key_slot_3_w0
								0
								31
							
						
					
					
						ef_key_slot_3_w1
						ef_key_slot_3_w1.
						0x50
						
							
								ef_key_slot_3_w1
								0
								31
							
						
					
					
						ef_key_slot_3_w2
						ef_key_slot_3_w2.
						0x54
						
							
								ef_key_slot_3_w2
								0
								31
							
						
					
					
						ef_key_slot_3_w3
						ef_key_slot_3_w3.
						0x58
						
							
								ef_key_slot_3_w3
								0
								31
							
						
					
					
						ef_key_slot_4_w0
						ef_key_slot_4_w0.
						0x5C
						
							
								ef_key_slot_4_w0
								0
								31
							
						
					
					
						ef_key_slot_4_w1
						ef_key_slot_4_w1.
						0x60
						
							
								ef_key_slot_4_w1
								0
								31
							
						
					
					
						ef_key_slot_4_w2
						ef_key_slot_4_w2.
						0x64
						
							
								ef_key_slot_4_w2
								0
								31
							
						
					
					
						ef_key_slot_4_w3
						ef_key_slot_4_w3.
						0x68
						
							
								ef_key_slot_4_w3
								0
								31
							
						
					
					
						ef_key_slot_5_w0
						ef_key_slot_5_w0.
						0x6C
						
							
								ef_key_slot_5_w0
								0
								31
							
						
					
					
						ef_key_slot_5_w1
						ef_key_slot_5_w1.
						0x70
						
							
								ef_key_slot_5_w1
								0
								31
							
						
					
					
						ef_key_slot_5_w2
						ef_key_slot_5_w2.
						0x74
						
							
								ef_key_slot_5_w2
								0
								31
							
						
					
					
						ef_key_slot_5_w3
						ef_key_slot_5_w3.
						0x78
						
							
								ef_key_slot_5_w3
								0
								31
							
						
					
					
						ef_data_0_lock
						ef_data_0_lock.
						0x7C
						
							
								rd_lock_key_slot_5
								31
								31
							
							
								rd_lock_key_slot_4
								30
								30
							
							
								rd_lock_key_slot_3
								29
								29
							
							
								rd_lock_key_slot_2
								28
								28
							
							
								rd_lock_key_slot_1
								27
								27
							
							
								rd_lock_key_slot_0
								26
								26
							
							
								rd_lock_dbg_pwd
								25
								25
							
							
								wr_lock_key_slot_5_h
								24
								24
							
							
								wr_lock_key_slot_4_h
								23
								23
							
							
								wr_lock_key_slot_3
								22
								22
							
							
								wr_lock_key_slot_2
								21
								21
							
							
								wr_lock_key_slot_1
								20
								20
							
							
								wr_lock_key_slot_0
								19
								19
							
							
								wr_lock_wifi_mac
								18
								18
							
							
								wr_lock_sw_usage_0
								17
								17
							
							
								wr_lock_dbg_pwd
								16
								16
							
							
								wr_lock_boot_mode
								15
								15
							
							
								wr_lock_key_slot_5_l
								14
								14
							
							
								wr_lock_key_slot_4_l
								13
								13
							
							
								ef_ana_trim_1
								0
								12
							
						
					
				
			
			
				ef_data_1
				ef_data_1.
				0x40007000
				ef_data_1
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						reg_key_slot_6_w0
						reg_key_slot_6_w0.
						0x80
						
							
								reg_key_slot_6_w0
								0
								31
							
						
					
					
						reg_key_slot_6_w1
						reg_key_slot_6_w1.
						0x84
						
							
								reg_key_slot_6_w1
								0
								31
							
						
					
					
						reg_key_slot_6_w2
						reg_key_slot_6_w2.
						0x88
						
							
								reg_key_slot_6_w2
								0
								31
							
						
					
					
						reg_key_slot_6_w3
						reg_key_slot_6_w3.
						0x8C
						
							
								reg_key_slot_6_w3
								0
								31
							
						
					
					
						reg_key_slot_7_w0
						reg_key_slot_7_w0.
						0x90
						
							
								reg_key_slot_7_w0
								0
								31
							
						
					
					
						reg_key_slot_7_w1
						reg_key_slot_7_w1.
						0x94
						
							
								reg_key_slot_7_w1
								0
								31
							
						
					
					
						reg_key_slot_7_w2
						reg_key_slot_7_w2.
						0x98
						
							
								reg_key_slot_7_w2
								0
								31
							
						
					
					
						reg_key_slot_7_w3
						reg_key_slot_7_w3.
						0x9C
						
							
								reg_key_slot_7_w3
								0
								31
							
						
					
					
						reg_key_slot_8_w0
						reg_key_slot_8_w0.
						0xA0
						
							
								reg_key_slot_8_w0
								0
								31
							
						
					
					
						reg_key_slot_8_w1
						reg_key_slot_8_w1.
						0xA4
						
							
								reg_key_slot_8_w1
								0
								31
							
						
					
					
						reg_key_slot_8_w2
						reg_key_slot_8_w2.
						0xA8
						
							
								reg_key_slot_8_w2
								0
								31
							
						
					
					
						reg_key_slot_8_w3
						reg_key_slot_8_w3.
						0xAC
						
							
								reg_key_slot_8_w3
								0
								31
							
						
					
					
						reg_key_slot_9_w0
						reg_key_slot_9_w0.
						0xB0
						
							
								reg_key_slot_9_w0
								0
								31
							
						
					
					
						reg_key_slot_9_w1
						reg_key_slot_9_w1.
						0xB4
						
							
								reg_key_slot_9_w1
								0
								31
							
						
					
					
						reg_key_slot_9_w2
						reg_key_slot_9_w2.
						0xB8
						
							
								reg_key_slot_9_w2
								0
								31
							
						
					
					
						reg_key_slot_9_w3
						reg_key_slot_9_w3.
						0xBC
						
							
								reg_key_slot_9_w3
								0
								31
							
						
					
					
						reg_key_slot_10_w0
						reg_key_slot_10_w0.
						0xC0
						
					
					
						reg_key_slot_10_w1
						reg_key_slot_10_w1.
						0xC4
						
					
					
						reg_key_slot_10_w2
						reg_key_slot_10_w2.
						0xC8
						
					
					
						reg_key_slot_10_w3
						reg_key_slot_10_w3.
						0xCC
						
					
					
						reg_key_slot_11_w0
						reg_key_slot_11_w0.
						0xD0
						
					
					
						reg_key_slot_11_w1
						reg_key_slot_11_w1.
						0xD4
						
					
					
						reg_key_slot_11_w2
						reg_key_slot_11_w2.
						0xD8
						
					
					
						reg_key_slot_11_w3
						reg_key_slot_11_w3.
						0xDC
						
					
					
						reg_data_1_lock
						reg_data_1_lock.
						0xE0
						
							
								rd_lock_key_slot_9
								29
								29
							
							
								rd_lock_key_slot_8
								28
								28
							
							
								rd_lock_key_slot_7
								27
								27
							
							
								rd_lock_key_slot_6
								26
								26
							
							
								RESERVED_25_16
								16
								25
							
							
								wr_lock_key_slot_9
								13
								13
							
							
								wr_lock_key_slot_8
								12
								12
							
							
								wr_lock_key_slot_7
								11
								11
							
							
								wr_lock_key_slot_6
								10
								10
							
							
								RESERVED_9_0
								0
								9
							
						
					
				
			
			
				ef_ctrl
				ef_ctrl.
				0x40007000
				ef_ctrl
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						ef_if_ctrl_0
						ef_if_ctrl_0.
						0x800
						
							
								ef_if_prot_code_cyc
								24
								31
							
							
								ef_if_0_int_set
								22
								22
							
							
								ef_if_0_int_clr
								21
								21
							
							
								ef_if_0_int
								20
								20
							
							
								ef_if_cyc_modify_lock
								19
								19
							
							
								ef_if_auto_rd_en
								18
								18
							
							
								ef_clk_sahb_data_gate
								17
								17
							
							
								ef_if_por_dig
								16
								16
							
							
								ef_if_prot_code_ctrl
								8
								15
							
							
								ef_clk_sahb_data_sel
								7
								7
							
							
								ef_if_0_cyc_modify
								6
								6
							
							
								ef_if_0_manual_en
								5
								5
							
							
								ef_if_0_trig
								4
								4
							
							
								ef_if_0_rw
								3
								3
							
							
								ef_if_0_busy
								2
								2
							
							
								ef_if_0_autoload_done
								1
								1
							
							
								ef_if_0_autoload_p1_done
								0
								0
							
						
					
					
						ef_if_cyc_0
						ef_if_cyc_0.
						0x804
						
							
								ef_if_cyc_pd_cs_s
								24
								31
							
							
								ef_if_cyc_cs
								18
								23
							
							
								ef_if_cyc_rd_adr
								12
								17
							
							
								ef_if_cyc_rd_dat
								6
								11
							
							
								ef_if_cyc_rd_dmy
								0
								5
							
						
					
					
						ef_if_cyc_1
						ef_if_cyc_1.
						0x808
						
							
								ef_if_cyc_pd_cs_h
								26
								31
							
							
								ef_if_cyc_ps_cs
								20
								25
							
							
								ef_if_cyc_wr_adr
								14
								19
							
							
								ef_if_cyc_pp
								6
								13
							
							
								ef_if_cyc_pi
								0
								5
							
						
					
					
						ef_if_0_manual
						ef_if_0_manual.
						0x80C
						
							
								ef_if_prot_code_manual
								24
								31
							
							
								ef_if_0_q
								16
								23
							
							
								ef_if_csb
								15
								15
							
							
								ef_if_load
								14
								14
							
							
								ef_if_pgenb
								13
								13
							
							
								ef_if_strobe
								12
								12
							
							
								ef_if_ps
								11
								11
							
							
								ef_if_pd
								10
								10
							
							
								ef_if_a
								0
								9
							
						
					
					
						ef_if_0_status
						ef_if_0_status.
						0x810
						
							
								ef_if_0_status
								0
								31
							
						
					
					
						ef_if_cfg_0
						ef_if_cfg_0.
						0x814
						
							
								ef_if_dbg_mode
								28
								31
							
							
								ef_if_dbg_jtag_0_dis
								26
								27
							
							
								ef_if_dbg_jtag_1_dis
								24
								25
							
							
								ef_if_efuse_dbg_dis
								23
								23
							
							
								ef_if_se_dbg_dis
								22
								22
							
							
								ef_if_cpu_rst_dbg_dis
								21
								21
							
							
								ef_if_cpu1_dis
								20
								20
							
							
								ef_if_sf_dis
								19
								19
							
							
								ef_if_cam_dis
								18
								18
							
							
								ef_if_0_key_enc_en
								17
								17
							
							
								ef_if_wifi_dis
								16
								16
							
							
								ef_if_ble_dis
								15
								15
							
							
								ef_if_sdu_dis
								14
								14
							
							
								ef_if_sf_key_0_sel
								12
								13
							
							
								ef_if_boot_sel
								8
								11
							
							
								ef_if_cpu0_enc_en
								7
								7
							
							
								ef_if_cpu1_enc_en
								6
								6
							
							
								ef_if_sboot_en
								4
								5
							
							
								ef_if_sboot_sign_mode
								2
								3
							
							
								ef_if_sf_aes_mode
								0
								1
							
						
					
					
						ef_sw_cfg_0
						ef_sw_cfg_0.
						0x818
						
							
								ef_sw_dbg_mode
								28
								31
							
							
								ef_sw_dbg_jtag_0_dis
								26
								27
							
							
								ef_sw_dbg_jtag_1_dis
								24
								25
							
							
								ef_sw_efuse_dbg_dis
								23
								23
							
							
								ef_sw_se_dbg_dis
								22
								22
							
							
								ef_sw_cpu_rst_dbg_dis
								21
								21
							
							
								ef_sw_cpu1_dis
								20
								20
							
							
								ef_sw_sf_dis
								19
								19
							
							
								ef_sw_cam_dis
								18
								18
							
							
								ef_sw_0_key_enc_en
								17
								17
							
							
								ef_sw_wifi_dis
								16
								16
							
							
								ef_sw_ble_dis
								15
								15
							
							
								ef_sw_sdu_dis
								14
								14
							
							
								ef_sw_sf_key_0_sel
								12
								13
							
							
								ef_sw_cpu0_enc_en
								7
								7
							
							
								ef_sw_cpu1_enc_en
								6
								6
							
							
								ef_sw_sboot_en
								4
								5
							
							
								ef_sw_sboot_sign_mode
								2
								3
							
							
								ef_sw_sf_aes_mode
								0
								1
							
						
					
					
						ef_reserved
						ef_reserved.
						0x81C
						
							
								ef_reserved
								0
								31
							
						
					
					
						ef_if_ana_trim_0
						ef_if_ana_trim_0.
						0x820
						
							
								ef_if_ana_trim_0
								0
								31
							
						
					
					
						ef_if_sw_usage_0
						ef_if_sw_usage_0.
						0x824
						
							
								ef_if_sw_usage_0
								0
								31
							
						
					
					
						ef_crc_ctrl_0
						ef_crc_ctrl_0.
						0xA00
						
							
								ef_crc_slp_n
								16
								31
							
							
								ef_crc_lock
								11
								11
							
							
								ef_crc_int_set
								10
								10
							
							
								ef_crc_int_clr
								9
								9
							
							
								ef_crc_int
								8
								8
							
							
								ef_crc_din_endian
								7
								7
							
							
								ef_crc_dout_endian
								6
								6
							
							
								ef_crc_dout_inv_en
								5
								5
							
							
								ef_crc_error
								4
								4
							
							
								ef_crc_mode
								3
								3
							
							
								ef_crc_en
								2
								2
							
							
								ef_crc_trig
								1
								1
							
							
								ef_crc_busy
								0
								0
							
						
					
					
						ef_crc_ctrl_1
						ef_crc_ctrl_1.
						0xA04
						
							
								ef_crc_data_0_en
								0
								31
							
						
					
					
						ef_crc_ctrl_2
						ef_crc_ctrl_2.
						0xA08
						
							
								ef_crc_data_1_en
								0
								31
							
						
					
					
						ef_crc_ctrl_3
						ef_crc_ctrl_3.
						0xA0C
						
							
								ef_crc_iv
								0
								31
							
						
					
					
						ef_crc_ctrl_4
						ef_crc_ctrl_4.
						0xA10
						
							
								ef_crc_golden
								0
								31
							
						
					
					
						ef_crc_ctrl_5
						ef_crc_ctrl_5.
						0xA14
						
							
								ef_crc_dout
								0
								31
							
						
					
				
			
			
				cci
				cci.
				0x40008000
				cci
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						cci_cfg
						cci_cfg.
						0x0
						
							
								reg_mcci_clk_inv
								9
								9
							
							
								reg_scci_clk_inv
								8
								8
							
							
								cfg_cci1_pre_read
								7
								7
							
							
								reg_div_m_cci_sclk
								5
								6
							
							
								reg_m_cci_sclk_en
								4
								4
							
							
								cci_mas_hw_mode
								3
								3
							
							
								cci_mas_sel_cci2
								2
								2
							
							
								cci_slv_sel_cci2
								1
								1
							
							
								cci_en
								0
								0
							
						
					
					
						cci_addr
						cci_addr.
						0x4
						
							
								apb_cci_addr
								0
								31
							
						
					
					
						cci_wdata
						cci_wdata.
						0x8
						
							
								apb_cci_wdata
								0
								31
							
						
					
					
						cci_rdata
						cci_rdata.
						0xC
						
							
								apb_cci_rdata
								0
								31
							
						
					
					
						cci_ctl
						cci_ctl.
						0x10
						
							
								ahb_state
								2
								3
							
							
								cci_read_flag
								1
								1
							
							
								cci_write_flag
								0
								0
							
						
					
				
			
			
				l1c
				l1c.
				0x40009000
				l1c
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						l1c_config
						l1c_config.
						0x0
						
							
								reserved_31_30
								30
								31
							
							
								l1c_flush_done
								29
								29
							
							
								l1c_flush_en
								28
								28
							
							
								wrap_dis
								26
								26
							
							
								early_resp_dis
								25
								25
							
							
								l1c_bmx_busy_option_dis
								24
								24
							
							
								l1c_bmx_timeout_en
								20
								23
							
							
								l1c_bmx_arb_mode
								16
								17
							
							
								l1c_bmx_err_en
								15
								15
							
							
								l1c_bypass
								14
								14
							
							
								irom_2t_access
								12
								12
							
							
								l1c_way_dis
								8
								11
							
							
								l1c_wa_en
								6
								6
							
							
								l1c_wb_en
								5
								5
							
							
								l1c_wt_en
								4
								4
							
							
								l1c_invalid_done
								3
								3
							
							
								l1c_invalid_en
								2
								2
							
							
								l1c_cnt_en
								1
								1
							
							
								l1c_cacheable
								0
								0
							
						
					
					
						hit_cnt_lsb
						hit_cnt_lsb.
						0x4
						
							
								hit_cnt_lsb
								0
								31
							
						
					
					
						hit_cnt_msb
						hit_cnt_msb.
						0x8
						
							
								hit_cnt_msb
								0
								31
							
						
					
					
						miss_cnt
						miss_cnt.
						0xC
						
							
								miss_cnt
								0
								31
							
						
					
					
						l1c_misc
						l1c_misc.
						0x10
						
							
								l1c_fsm
								28
								30
							
						
					
					
						l1c_bmx_err_addr_en
						l1c_bmx_err_addr_en.
						0x200
						
							
								l1c_hsel_option
								16
								19
							
							
								l1c_bmx_err_tz
								5
								5
							
							
								l1c_bmx_err_dec
								4
								4
							
							
								l1c_bmx_err_addr_dis
								0
								0
							
						
					
					
						l1c_bmx_err_addr
						l1c_bmx_err_addr.
						0x204
						
							
								l1c_bmx_err_addr
								0
								31
							
						
					
					
						irom1_misr_dataout_0
						irom1_misr_dataout_0.
						0x208
						
							
								irom1_misr_dataout_0
								0
								31
							
						
					
					
						irom1_misr_dataout_1
						irom1_misr_dataout_1.
						0x20C
						
							
								irom1_misr_dataout_1
								0
								31
							
						
					
					
						cpu_clk_gate
						cpu_clk_gate.
						0x210
						
							
								force_e21_clock_on_2
								2
								2
							
							
								force_e21_clock_on_1
								1
								1
							
							
								force_e21_clock_on_0
								0
								0
							
						
					
				
			
			
				uart
				uart.
				0x4000A000
				uart
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						utx_config
						utx_config.
						0x0
						
							
								cr_utx_len
								16
								31
							
							
								cr_utx_bit_cnt_b
								13
								15
							
							
								cr_utx_bit_cnt_p
								11
								12
							
							
								cr_utx_bit_cnt_d
								8
								10
							
							
								cr_utx_ir_inv
								7
								7
							
							
								cr_utx_ir_en
								6
								6
							
							
								cr_utx_prt_sel
								5
								5
							
							
								cr_utx_prt_en
								4
								4
							
							
								cr_utx_lin_en
								3
								3
							
							
								cr_utx_frm_en
								2
								2
							
							
								cr_utx_cts_en
								1
								1
							
							
								cr_utx_en
								0
								0
							
						
					
					
						urx_config
						urx_config.
						0x4
						
							
								cr_urx_len
								16
								31
							
							
								cr_urx_deg_cnt
								12
								15
							
							
								cr_urx_deg_en
								11
								11
							
							
								cr_urx_bit_cnt_d
								8
								10
							
							
								cr_urx_ir_inv
								7
								7
							
							
								cr_urx_ir_en
								6
								6
							
							
								cr_urx_prt_sel
								5
								5
							
							
								cr_urx_prt_en
								4
								4
							
							
								cr_urx_lin_en
								3
								3
							
							
								cr_urx_abr_en
								1
								1
							
							
								cr_urx_en
								0
								0
							
						
					
					
						uart_bit_prd
						uart_bit_prd.
						0x8
						
							
								cr_urx_bit_prd
								16
								31
							
							
								cr_utx_bit_prd
								0
								15
							
						
					
					
						data_config
						data_config.
						0xC
						
							
								cr_uart_bit_inv
								0
								0
							
						
					
					
						utx_ir_position
						utx_ir_position.
						0x10
						
							
								cr_utx_ir_pos_p
								16
								31
							
							
								cr_utx_ir_pos_s
								0
								15
							
						
					
					
						urx_ir_position
						urx_ir_position.
						0x14
						
							
								cr_urx_ir_pos_s
								0
								15
							
						
					
					
						urx_rto_timer
						urx_rto_timer.
						0x18
						
							
								cr_urx_rto_value
								0
								7
							
						
					
					
						uart_sw_mode
						uart_sw_mode.
						0x1C
						
							
								cr_urx_rts_sw_val
								3
								3
							
							
								cr_urx_rts_sw_mode
								2
								2
							
							
								cr_utx_txd_sw_val
								1
								1
							
							
								cr_utx_txd_sw_mode
								0
								0
							
						
					
					
						uart_int_sts
						UART interrupt status
						0x20
						
							
								urx_lse_int
								8
								8
							
							
								urx_fer_int
								7
								7
							
							
								utx_fer_int
								6
								6
							
							
								urx_pce_int
								5
								5
							
							
								urx_rto_int
								4
								4
							
							
								urx_fifo_int
								3
								3
							
							
								utx_fifo_int
								2
								2
							
							
								urx_end_int
								1
								1
							
							
								utx_end_int
								0
								0
							
						
					
					
						uart_int_mask
						UART interrupt mask
						0x24
						
							
								cr_urx_lse_mask
								8
								8
							
							
								cr_urx_fer_mask
								7
								7
							
							
								cr_utx_fer_mask
								6
								6
							
							
								cr_urx_pce_mask
								5
								5
							
							
								cr_urx_rto_mask
								4
								4
							
							
								cr_urx_fifo_mask
								3
								3
							
							
								cr_utx_fifo_mask
								2
								2
							
							
								cr_urx_end_mask
								1
								1
							
							
								cr_utx_end_mask
								0
								0
							
						
					
					
						uart_int_clear
						UART interrupt clear
						0x28
						
							
								cr_urx_lse_clr
								8
								8
							
							
								rsvd_7
								7
								7
							
							
								rsvd_6
								6
								6
							
							
								cr_urx_pce_clr
								5
								5
							
							
								cr_urx_rto_clr
								4
								4
							
							
								rsvd_3
								3
								3
							
							
								rsvd_2
								2
								2
							
							
								cr_urx_end_clr
								1
								1
							
							
								cr_utx_end_clr
								0
								0
							
						
					
					
						uart_int_en
						UART interrupt enable
						0x2C
						
							
								cr_urx_lse_en
								8
								8
							
							
								cr_urx_fer_en
								7
								7
							
							
								cr_utx_fer_en
								6
								6
							
							
								cr_urx_pce_en
								5
								5
							
							
								cr_urx_rto_en
								4
								4
							
							
								cr_urx_fifo_en
								3
								3
							
							
								cr_utx_fifo_en
								2
								2
							
							
								cr_urx_end_en
								1
								1
							
							
								cr_utx_end_en
								0
								0
							
						
					
					
						uart_status
						uart_status.
						0x30
						
							
								sts_urx_bus_busy
								1
								1
							
							
								sts_utx_bus_busy
								0
								0
							
						
					
					
						sts_urx_abr_prd
						sts_urx_abr_prd.
						0x34
						
							
								sts_urx_abr_prd_0x55
								16
								31
							
							
								sts_urx_abr_prd_start
								0
								15
							
						
					
					
						uart_fifo_config_0
						uart_fifo_config_0.
						0x80
						
							
								rx_fifo_underflow
								7
								7
							
							
								rx_fifo_overflow
								6
								6
							
							
								tx_fifo_underflow
								5
								5
							
							
								tx_fifo_overflow
								4
								4
							
							
								rx_fifo_clr
								3
								3
							
							
								tx_fifo_clr
								2
								2
							
							
								uart_dma_rx_en
								1
								1
							
							
								uart_dma_tx_en
								0
								0
							
						
					
					
						uart_fifo_config_1
						uart_fifo_config_1.
						0x84
						
							
								rx_fifo_th
								24
								30
							
							
								tx_fifo_th
								16
								22
							
							
								rx_fifo_cnt
								8
								15
							
							
								tx_fifo_cnt
								0
								7
							
						
					
					
						uart_fifo_wdata
						uart_fifo_wdata.
						0x88
						
							
								uart_fifo_wdata
								0
								7
							
						
					
					
						uart_fifo_rdata
						uart_fifo_rdata.
						0x8C
						
							
								uart_fifo_rdata
								0
								7
							
						
					
				
			
			
				spi
				spi.
				0x4000A200
				spi
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						spi_config
						spi_config.
						0x0
						
							
								cr_spi_deg_cnt
								12
								15
							
							
								cr_spi_deg_en
								11
								11
							
							
								cr_spi_m_cont_en
								9
								9
							
							
								cr_spi_rxd_ignr_en
								8
								8
							
							
								cr_spi_byte_inv
								7
								7
							
							
								cr_spi_bit_inv
								6
								6
							
							
								cr_spi_sclk_ph
								5
								5
							
							
								cr_spi_sclk_pol
								4
								4
							
							
								cr_spi_frame_size
								2
								3
							
							
								cr_spi_s_en
								1
								1
							
							
								cr_spi_m_en
								0
								0
							
						
					
					
						spi_int_sts
						spi_int_sts.
						0x4
						
							
								cr_spi_fer_en
								29
								29
							
							
								cr_spi_txu_en
								28
								28
							
							
								cr_spi_sto_en
								27
								27
							
							
								cr_spi_rxf_en
								26
								26
							
							
								cr_spi_txf_en
								25
								25
							
							
								cr_spi_end_en
								24
								24
							
							
								rsvd_21
								21
								21
							
							
								cr_spi_txu_clr
								20
								20
							
							
								cr_spi_sto_clr
								19
								19
							
							
								rsvd_18
								18
								18
							
							
								rsvd_17
								17
								17
							
							
								cr_spi_end_clr
								16
								16
							
							
								cr_spi_fer_mask
								13
								13
							
							
								cr_spi_txu_mask
								12
								12
							
							
								cr_spi_sto_mask
								11
								11
							
							
								cr_spi_rxf_mask
								10
								10
							
							
								cr_spi_txf_mask
								9
								9
							
							
								cr_spi_end_mask
								8
								8
							
							
								spi_fer_int
								5
								5
							
							
								spi_txu_int
								4
								4
							
							
								spi_sto_int
								3
								3
							
							
								spi_rxf_int
								2
								2
							
							
								spi_txf_int
								1
								1
							
							
								spi_end_int
								0
								0
							
						
					
					
						spi_bus_busy
						spi_bus_busy.
						0x8
						
							
								sts_spi_bus_busy
								0
								0
							
						
					
					
						spi_prd_0
						spi_prd_0.
						0x10
						
							
								cr_spi_prd_d_ph_1
								24
								31
							
							
								cr_spi_prd_d_ph_0
								16
								23
							
							
								cr_spi_prd_p
								8
								15
							
							
								cr_spi_prd_s
								0
								7
							
						
					
					
						spi_prd_1
						spi_prd_1.
						0x14
						
							
								cr_spi_prd_i
								0
								7
							
						
					
					
						spi_rxd_ignr
						spi_rxd_ignr.
						0x18
						
							
								cr_spi_rxd_ignr_s
								16
								20
							
							
								cr_spi_rxd_ignr_p
								0
								4
							
						
					
					
						spi_sto_value
						spi_sto_value.
						0x1C
						
							
								cr_spi_sto_value
								0
								11
							
						
					
					
						spi_fifo_config_0
						spi_fifo_config_0.
						0x80
						
							
								rx_fifo_underflow
								7
								7
							
							
								rx_fifo_overflow
								6
								6
							
							
								tx_fifo_underflow
								5
								5
							
							
								tx_fifo_overflow
								4
								4
							
							
								rx_fifo_clr
								3
								3
							
							
								tx_fifo_clr
								2
								2
							
							
								spi_dma_rx_en
								1
								1
							
							
								spi_dma_tx_en
								0
								0
							
						
					
					
						spi_fifo_config_1
						spi_fifo_config_1.
						0x84
						
							
								rx_fifo_th
								24
								25
							
							
								tx_fifo_th
								16
								17
							
							
								rx_fifo_cnt
								8
								10
							
							
								tx_fifo_cnt
								0
								2
							
						
					
					
						spi_fifo_wdata
						spi_fifo_wdata.
						0x88
						
							
								spi_fifo_wdata
								0
								31
							
						
					
					
						spi_fifo_rdata
						spi_fifo_rdata.
						0x8C
						
							
								spi_fifo_rdata
								0
								31
							
						
					
				
			
			
				i2c
				i2c.
				0x4000A300
				i2c
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						i2c_config
						i2c_config.
						0x0
						
							
								cr_i2c_deg_cnt
								28
								31
							
							
								cr_i2c_pkt_len
								16
								23
							
							
								cr_i2c_slv_addr
								8
								14
							
							
								cr_i2c_sub_addr_bc
								5
								6
							
							
								cr_i2c_sub_addr_en
								4
								4
							
							
								cr_i2c_scl_sync_en
								3
								3
							
							
								cr_i2c_deg_en
								2
								2
							
							
								cr_i2c_pkt_dir
								1
								1
							
							
								cr_i2c_m_en
								0
								0
							
						
					
					
						i2c_int_sts
						i2c_int_sts.
						0x4
						
							
								cr_i2c_fer_en
								29
								29
							
							
								cr_i2c_arb_en
								28
								28
							
							
								cr_i2c_nak_en
								27
								27
							
							
								cr_i2c_rxf_en
								26
								26
							
							
								cr_i2c_txf_en
								25
								25
							
							
								cr_i2c_end_en
								24
								24
							
							
								rsvd_21
								21
								21
							
							
								cr_i2c_arb_clr
								20
								20
							
							
								cr_i2c_nak_clr
								19
								19
							
							
								rsvd_18
								18
								18
							
							
								rsvd_17
								17
								17
							
							
								cr_i2c_end_clr
								16
								16
							
							
								cr_i2c_fer_mask
								13
								13
							
							
								cr_i2c_arb_mask
								12
								12
							
							
								cr_i2c_nak_mask
								11
								11
							
							
								cr_i2c_rxf_mask
								10
								10
							
							
								cr_i2c_txf_mask
								9
								9
							
							
								cr_i2c_end_mask
								8
								8
							
							
								i2c_fer_int
								5
								5
							
							
								i2c_arb_int
								4
								4
							
							
								i2c_nak_int
								3
								3
							
							
								i2c_rxf_int
								2
								2
							
							
								i2c_txf_int
								1
								1
							
							
								i2c_end_int
								0
								0
							
						
					
					
						i2c_sub_addr
						i2c_sub_addr.
						0x8
						
							
								cr_i2c_sub_addr_b3
								24
								31
							
							
								cr_i2c_sub_addr_b2
								16
								23
							
							
								cr_i2c_sub_addr_b1
								8
								15
							
							
								cr_i2c_sub_addr_b0
								0
								7
							
						
					
					
						i2c_bus_busy
						i2c_bus_busy.
						0xC
						
							
								cr_i2c_bus_busy_clr
								1
								1
							
							
								sts_i2c_bus_busy
								0
								0
							
						
					
					
						i2c_prd_start
						i2c_prd_start.
						0x10
						
							
								cr_i2c_prd_s_ph_3
								24
								31
							
							
								cr_i2c_prd_s_ph_2
								16
								23
							
							
								cr_i2c_prd_s_ph_1
								8
								15
							
							
								cr_i2c_prd_s_ph_0
								0
								7
							
						
					
					
						i2c_prd_stop
						i2c_prd_stop.
						0x14
						
							
								cr_i2c_prd_p_ph_3
								24
								31
							
							
								cr_i2c_prd_p_ph_2
								16
								23
							
							
								cr_i2c_prd_p_ph_1
								8
								15
							
							
								cr_i2c_prd_p_ph_0
								0
								7
							
						
					
					
						i2c_prd_data
						i2c_prd_data.
						0x18
						
							
								cr_i2c_prd_d_ph_3
								24
								31
							
							
								cr_i2c_prd_d_ph_2
								16
								23
							
							
								cr_i2c_prd_d_ph_1
								8
								15
							
							
								cr_i2c_prd_d_ph_0
								0
								7
							
						
					
					
						i2c_fifo_config_0
						i2c_fifo_config_0.
						0x80
						
							
								rx_fifo_underflow
								7
								7
							
							
								rx_fifo_overflow
								6
								6
							
							
								tx_fifo_underflow
								5
								5
							
							
								tx_fifo_overflow
								4
								4
							
							
								rx_fifo_clr
								3
								3
							
							
								tx_fifo_clr
								2
								2
							
							
								i2c_dma_rx_en
								1
								1
							
							
								i2c_dma_tx_en
								0
								0
							
						
					
					
						i2c_fifo_config_1
						i2c_fifo_config_1.
						0x84
						
							
								rx_fifo_th
								24
								24
							
							
								tx_fifo_th
								16
								16
							
							
								rx_fifo_cnt
								8
								9
							
							
								tx_fifo_cnt
								0
								1
							
						
					
					
						i2c_fifo_wdata
						i2c_fifo_wdata.
						0x88
						
							
								i2c_fifo_wdata
								0
								31
							
						
					
					
						i2c_fifo_rdata
						i2c_fifo_rdata.
						0x8C
						
							
								i2c_fifo_rdata
								0
								31
							
						
					
				
			
			
				pwm
				pwm.
				0x4000A400
				pwm
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						pwm_int_config
						pwm_int_config.
						0x0
						
							
								pwm_int_clear
								8
								13
							
							
								pwm_interrupt_sts
								0
								5
							
						
					
					
						pwm0_clkdiv
						pwm0_clkdiv.
						0x20
						
							
								pwm_clk_div
								0
								15
							
						
					
					
						pwm0_thre1
						pwm0_thre1.
						0x24
						
							
								pwm_thre1
								0
								15
							
						
					
					
						pwm0_thre2
						pwm0_thre2.
						0x28
						
							
								pwm_thre2
								0
								15
							
						
					
					
						pwm0_period
						pwm0_period.
						0x2C
						
							
								pwm_period
								0
								15
							
						
					
					
						pwm0_config
						pwm0_config.
						0x30
						
							
								pwm_sts_top
								7
								7
							
							
								pwm_stop_en
								6
								6
							
							
								pwm_sw_mode
								5
								5
							
							
								pwm_sw_force_val
								4
								4
							
							
								pwm_stop_mode
								3
								3
							
							
								pwm_out_inv
								2
								2
							
							
								reg_clk_sel
								0
								1
							
						
					
					
						pwm0_interrupt
						pwm0_interrupt.
						0x34
						
							
								pwm_int_enable
								16
								16
							
							
								pwm_int_period_cnt
								0
								15
							
						
					
					
						pwm1_clkdiv
						pwm1_clkdiv.
						0x40
						
							
								pwm_clk_div
								0
								15
							
						
					
					
						pwm1_thre1
						pwm1_thre1.
						0x44
						
							
								pwm_thre1
								0
								15
							
						
					
					
						pwm1_thre2
						pwm1_thre2.
						0x48
						
							
								pwm_thre2
								0
								15
							
						
					
					
						pwm1_period
						pwm1_period.
						0x4C
						
							
								pwm_period
								0
								15
							
						
					
					
						pwm1_config
						pwm1_config.
						0x50
						
							
								pwm_sts_top
								7
								7
							
							
								pwm_stop_en
								6
								6
							
							
								pwm_sw_mode
								5
								5
							
							
								pwm_sw_force_val
								4
								4
							
							
								pwm_stop_mode
								3
								3
							
							
								pwm_out_inv
								2
								2
							
							
								reg_clk_sel
								0
								1
							
						
					
					
						pwm1_interrupt
						pwm1_interrupt.
						0x54
						
							
								pwm_int_enable
								16
								16
							
							
								pwm_int_period_cnt
								0
								15
							
						
					
					
						pwm2_clkdiv
						pwm2_clkdiv.
						0x60
						
							
								pwm_clk_div
								0
								15
							
						
					
					
						pwm2_thre1
						pwm2_thre1.
						0x64
						
							
								pwm_thre1
								0
								15
							
						
					
					
						pwm2_thre2
						pwm2_thre2.
						0x68
						
							
								pwm_thre2
								0
								15
							
						
					
					
						pwm2_period
						pwm2_period.
						0x6C
						
							
								pwm_period
								0
								15
							
						
					
					
						pwm2_config
						pwm2_config.
						0x70
						
							
								pwm_sts_top
								7
								7
							
							
								pwm_stop_en
								6
								6
							
							
								pwm_sw_mode
								5
								5
							
							
								pwm_sw_force_val
								4
								4
							
							
								pwm_stop_mode
								3
								3
							
							
								pwm_out_inv
								2
								2
							
							
								reg_clk_sel
								0
								1
							
						
					
					
						pwm2_interrupt
						pwm2_interrupt.
						0x74
						
							
								pwm_int_enable
								16
								16
							
							
								pwm_int_period_cnt
								0
								15
							
						
					
					
						pwm3_clkdiv
						pwm3_clkdiv.
						0x80
						
							
								pwm_clk_div
								0
								15
							
						
					
					
						pwm3_thre1
						pwm3_thre1.
						0x84
						
							
								pwm_thre1
								0
								15
							
						
					
					
						pwm3_thre2
						pwm3_thre2.
						0x88
						
							
								pwm_thre2
								0
								15
							
						
					
					
						pwm3_period
						pwm3_period.
						0x8C
						
							
								pwm_period
								0
								15
							
						
					
					
						pwm3_config
						pwm3_config.
						0x90
						
							
								pwm_sts_top
								7
								7
							
							
								pwm_stop_en
								6
								6
							
							
								pwm_sw_mode
								5
								5
							
							
								pwm_sw_force_val
								4
								4
							
							
								pwm_stop_mode
								3
								3
							
							
								pwm_out_inv
								2
								2
							
							
								reg_clk_sel
								0
								1
							
						
					
					
						pwm3_interrupt
						pwm3_interrupt.
						0x94
						
							
								pwm_int_enable
								16
								16
							
							
								pwm_int_period_cnt
								0
								15
							
						
					
					
						pwm4_clkdiv
						pwm4_clkdiv.
						0xA0
						
							
								pwm_clk_div
								0
								15
							
						
					
					
						pwm4_thre1
						pwm4_thre1.
						0xA4
						
							
								pwm_thre1
								0
								15
							
						
					
					
						pwm4_thre2
						pwm4_thre2.
						0xA8
						
							
								pwm_thre2
								0
								15
							
						
					
					
						pwm4_period
						pwm4_period.
						0xAC
						
							
								pwm_period
								0
								15
							
						
					
					
						pwm4_config
						pwm4_config.
						0xB0
						
							
								pwm_sts_top
								7
								7
							
							
								pwm_stop_en
								6
								6
							
							
								pwm_sw_mode
								5
								5
							
							
								pwm_sw_force_val
								4
								4
							
							
								pwm_stop_mode
								3
								3
							
							
								pwm_out_inv
								2
								2
							
							
								reg_clk_sel
								0
								1
							
						
					
					
						pwm4_interrupt
						pwm4_interrupt.
						0xB4
						
							
								pwm_int_enable
								16
								16
							
							
								pwm_int_period_cnt
								0
								15
							
						
					
				
			
			
				timer
				timer.
				0x4000A500
				timer
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						TCCR
						TCCR.
						0x0
						
							
								cs_wdt
								8
								9
							
							
								RESERVED_7
								7
								7
							
							
								cs_2
								5
								6
							
							
								RESERVED_4
								4
								4
							
							
								cs_1
								2
								3
							
						
					
					
						TMR2_0
						TMR2_0.
						0x10
						
							
								tmr
								0
								31
							
						
					
					
						TMR2_1
						TMR2_1.
						0x14
						
							
								tmr
								0
								31
							
						
					
					
						TMR2_2
						TMR2_2.
						0x18
						
							
								tmr
								0
								31
							
						
					
					
						TMR3_0
						TMR3_0.
						0x1C
						
							
								tmr
								0
								31
							
						
					
					
						TMR3_1
						TMR3_1.
						0x20
						
							
								tmr
								0
								31
							
						
					
					
						TMR3_2
						TMR3_2.
						0x24
						
							
								tmr
								0
								31
							
						
					
					
						TCR2
						TCR2.
						0x2C
						
							
								tcr
								0
								31
							
						
					
					
						TCR3
						TCR3.
						0x30
						
							
								tcr
								0
								31
							
						
					
					
						TMSR2
						TMSR2.
						0x38
						
							
								tmsr_2
								2
								2
							
							
								tmsr_1
								1
								1
							
							
								tmsr_0
								0
								0
							
						
					
					
						TMSR3
						TMSR3.
						0x3C
						
							
								tmsr_2
								2
								2
							
							
								tmsr_1
								1
								1
							
							
								tmsr_0
								0
								0
							
						
					
					
						TIER2
						TIER2.
						0x44
						
							
								tier_2
								2
								2
							
							
								tier_1
								1
								1
							
							
								tier_0
								0
								0
							
						
					
					
						TIER3
						TIER3.
						0x48
						
							
								tier_2
								2
								2
							
							
								tier_1
								1
								1
							
							
								tier_0
								0
								0
							
						
					
					
						TPLVR2
						TPLVR2.
						0x50
						
							
								tplvr
								0
								31
							
						
					
					
						TPLVR3
						TPLVR3.
						0x54
						
							
								tplvr
								0
								31
							
						
					
					
						TPLCR2
						TPLCR2.
						0x5C
						
							
								tplcr
								0
								1
							
						
					
					
						TPLCR3
						TPLCR3.
						0x60
						
							
								tplcr
								0
								1
							
						
					
					
						WMER
						WMER.
						0x64
						
							
								wrie
								1
								1
							
							
								we
								0
								0
							
						
					
					
						WMR
						WMR.
						0x68
						
							
								wmr
								0
								15
							
						
					
					
						WVR
						WVR.
						0x6C
						
							
								wvr
								0
								15
							
						
					
					
						WSR
						WSR.
						0x70
						
							
								wts
								0
								0
							
						
					
					
						TICR2
						TICR2.
						0x78
						
							
								tclr_2
								2
								2
							
							
								tclr_1
								1
								1
							
							
								tclr_0
								0
								0
							
						
					
					
						TICR3
						TICR3.
						0x7C
						
							
								tclr_2
								2
								2
							
							
								tclr_1
								1
								1
							
							
								tclr_0
								0
								0
							
						
					
					
						WICR
						WICR.
						0x80
						
							
								wiclr
								0
								0
							
						
					
					
						TCER
						TCER.
						0x84
						
							
								timer3_en
								2
								2
							
							
								timer2_en
								1
								1
							
						
					
					
						TCMR
						TCMR.
						0x88
						
							
								timer3_mode
								2
								2
							
							
								timer2_mode
								1
								1
							
						
					
					
						TILR2
						TILR2.
						0x90
						
							
								tilr_2
								2
								2
							
							
								tilr_1
								1
								1
							
							
								tilr_0
								0
								0
							
						
					
					
						TILR3
						TILR3.
						0x94
						
							
								tilr_2
								2
								2
							
							
								tilr_1
								1
								1
							
							
								tilr_0
								0
								0
							
						
					
					
						WCR
						WCR.
						0x98
						
							
								wcr
								0
								0
							
						
					
					
						WFAR
						WFAR.
						0x9C
						
							
								wfar
								0
								15
							
						
					
					
						WSAR
						WSAR.
						0xA0
						
							
								wsar
								0
								15
							
						
					
					
						TCVWR2
						TCVWR2.
						0xA8
						
							
								tcvwr
								0
								31
							
						
					
					
						TCVWR3
						TCVWR3.
						0xAC
						
							
								tcvwr
								0
								31
							
						
					
					
						TCVSYN2
						TCVSYN2.
						0xB4
						
							
								tcvsyn2
								0
								31
							
						
					
					
						TCVSYN3
						TCVSYN3.
						0xB8
						
							
								tcvsyn3
								0
								31
							
						
					
					
						TCDR
						TCDR.
						0xBC
						
							
								wcdr
								24
								31
							
							
								tcdr3
								16
								23
							
							
								tcdr2
								8
								15
							
						
					
				
			
			
				ir
				ir.
				0x4000A600
				ir
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						irtx_config
						irtx_config.
						0x0
						
							
								cr_irtx_data_num
								12
								17
							
							
								cr_irtx_tail_hl_inv
								11
								11
							
							
								cr_irtx_tail_en
								10
								10
							
							
								cr_irtx_head_hl_inv
								9
								9
							
							
								cr_irtx_head_en
								8
								8
							
							
								cr_irtx_logic1_hl_inv
								6
								6
							
							
								cr_irtx_logic0_hl_inv
								5
								5
							
							
								cr_irtx_data_en
								4
								4
							
							
								cr_irtx_swm_en
								3
								3
							
							
								cr_irtx_mod_en
								2
								2
							
							
								cr_irtx_out_inv
								1
								1
							
							
								cr_irtx_en
								0
								0
							
						
					
					
						irtx_int_sts
						irtx_int_sts.
						0x4
						
							
								cr_irtx_end_en
								24
								24
							
							
								cr_irtx_end_clr
								16
								16
							
							
								cr_irtx_end_mask
								8
								8
							
							
								irtx_end_int
								0
								0
							
						
					
					
						irtx_data_word0
						irtx_data_word0.
						0x8
						
							
								cr_irtx_data_word0
								0
								31
							
						
					
					
						irtx_data_word1
						irtx_data_word1.
						0xC
						
							
								cr_irtx_data_word1
								0
								31
							
						
					
					
						irtx_pulse_width
						irtx_pulse_width.
						0x10
						
							
								cr_irtx_mod_ph1_w
								24
								31
							
							
								cr_irtx_mod_ph0_w
								16
								23
							
							
								cr_irtx_pw_unit
								0
								11
							
						
					
					
						irtx_pw
						irtx_pw.
						0x14
						
							
								cr_irtx_tail_ph1_w
								28
								31
							
							
								cr_irtx_tail_ph0_w
								24
								27
							
							
								cr_irtx_head_ph1_w
								20
								23
							
							
								cr_irtx_head_ph0_w
								16
								19
							
							
								cr_irtx_logic1_ph1_w
								12
								15
							
							
								cr_irtx_logic1_ph0_w
								8
								11
							
							
								cr_irtx_logic0_ph1_w
								4
								7
							
							
								cr_irtx_logic0_ph0_w
								0
								3
							
						
					
					
						irtx_swm_pw_0
						irtx_swm_pw_0.
						0x40
						
							
								cr_irtx_swm_pw_0
								0
								31
							
						
					
					
						irtx_swm_pw_1
						irtx_swm_pw_1.
						0x44
						
							
								cr_irtx_swm_pw_1
								0
								31
							
						
					
					
						irtx_swm_pw_2
						irtx_swm_pw_2.
						0x48
						
							
								cr_irtx_swm_pw_2
								0
								31
							
						
					
					
						irtx_swm_pw_3
						irtx_swm_pw_3.
						0x4C
						
							
								cr_irtx_swm_pw_3
								0
								31
							
						
					
					
						irtx_swm_pw_4
						irtx_swm_pw_4.
						0x50
						
							
								cr_irtx_swm_pw_4
								0
								31
							
						
					
					
						irtx_swm_pw_5
						irtx_swm_pw_5.
						0x54
						
							
								cr_irtx_swm_pw_5
								0
								31
							
						
					
					
						irtx_swm_pw_6
						irtx_swm_pw_6.
						0x58
						
							
								cr_irtx_swm_pw_6
								0
								31
							
						
					
					
						irtx_swm_pw_7
						irtx_swm_pw_7.
						0x5C
						
							
								cr_irtx_swm_pw_7
								0
								31
							
						
					
					
						irrx_config
						irrx_config.
						0x80
						
							
								cr_irrx_deg_cnt
								8
								11
							
							
								cr_irrx_deg_en
								4
								4
							
							
								cr_irrx_mode
								2
								3
							
							
								cr_irrx_in_inv
								1
								1
							
							
								cr_irrx_en
								0
								0
							
						
					
					
						irrx_int_sts
						irrx_int_sts.
						0x84
						
							
								cr_irrx_end_en
								24
								24
							
							
								cr_irrx_end_clr
								16
								16
							
							
								cr_irrx_end_mask
								8
								8
							
							
								irrx_end_int
								0
								0
							
						
					
					
						irrx_pw_config
						irrx_pw_config.
						0x88
						
							
								cr_irrx_end_th
								16
								31
							
							
								cr_irrx_data_th
								0
								15
							
						
					
					
						irrx_data_count
						irrx_data_count.
						0x90
						
							
								sts_irrx_data_cnt
								0
								6
							
						
					
					
						irrx_data_word0
						irrx_data_word0.
						0x94
						
							
								sts_irrx_data_word0
								0
								31
							
						
					
					
						irrx_data_word1
						irrx_data_word1.
						0x98
						
							
								sts_irrx_data_word1
								0
								31
							
						
					
					
						irrx_swm_fifo_config_0
						irrx_swm_fifo_config_0.
						0xC0
						
							
								rx_fifo_cnt
								4
								10
							
							
								rx_fifo_underflow
								3
								3
							
							
								rx_fifo_overflow
								2
								2
							
							
								rx_fifo_clr
								0
								0
							
						
					
					
						irrx_swm_fifo_rdata
						irrx_swm_fifo_rdata.
						0xC4
						
							
								rx_fifo_rdata
								0
								15
							
						
					
				
			
			
				cks
				cks.
				0x4000A700
				cks
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						cks_config
						cks_config.
						0x0
						
							
								cr_cks_byte_swap
								1
								1
							
							
								cr_cks_clr
								0
								0
							
						
					
					
						data_in
						data_in.
						0x4
						
							
								data_in
								0
								7
							
						
					
					
						cks_out
						cks_out.
						0x8
						
							
								cks_out
								0
								15
							
						
					
				
			
			
				qdec
				qdec.
				0x4000A800
				qdec
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						qdec_ctrl
						qdec_ctrl.
						0x0
						
							
								input_swap
								31
								31
							
							
								rpt_mode
								30
								30
							
							
								spl_mode
								29
								29
							
							
								led_period
								20
								28
							
							
								rpt_period
								12
								19
							
							
								spl_period
								8
								11
							
							
								deg_cnt
								4
								7
							
							
								deg_en
								3
								3
							
							
								led_pol
								2
								2
							
							
								led_en
								1
								1
							
							
								qdec_en
								0
								0
							
						
					
					
						qdec_value
						qdec_value.
						0x4
						
							
								spl_val
								28
								29
							
							
								acc2_val
								16
								19
							
							
								acc1_val
								0
								10
							
						
					
					
						qdec_int_en
						qdec_int_en.
						0x10
						
							
								overflow_en
								3
								3
							
							
								dbl_rdy_en
								2
								2
							
							
								spl_rdy_en
								1
								1
							
							
								rpt_rdy_en
								0
								0
							
						
					
					
						qdec_int_sts
						qdec_int_sts.
						0x14
						
							
								overflow_sts
								3
								3
							
							
								dbl_rdy_sts
								2
								2
							
							
								spl_rdy_sts
								1
								1
							
							
								rpt_rdy_sts
								0
								0
							
						
					
					
						qdec_int_clr
						qdec_int_clr.
						0x18
						
							
								overflow_clr
								3
								3
							
							
								dbl_rdy_clr
								2
								2
							
							
								spl_rdy_clr
								1
								1
							
							
								rpt_rdy_clr
								0
								0
							
						
					
				
			
			
				kys
				kys.
				0x4000AB00
				kys
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						ks_ctrl
						ks_ctrl.
						0x0
						
							
								col_num
								20
								24
							
							
								row_num
								16
								18
							
							
								rc_ext
								8
								9
							
							
								deg_cnt
								4
								7
							
							
								deg_en
								3
								3
							
							
								ghost_en
								2
								2
							
							
								ks_en
								0
								0
							
						
					
					
						ks_int_en
						ks_int_en.
						0x10
						
							
								ks_int_en
								0
								0
							
						
					
					
						ks_int_sts
						ks_int_sts.
						0x14
						
							
								keycode_valid
								0
								3
							
						
					
					
						keycode_clr
						keycode_clr.
						0x18
						
							
								keycode_clr
								0
								3
							
						
					
					
						keycode_value
						keycode_value.
						0x1C
						
							
								keycode3
								24
								31
							
							
								keycode2
								16
								23
							
							
								keycode1
								8
								15
							
							
								keycode0
								0
								7
							
						
					
				
			
			
				i2s
				i2s.
				0x4000AA00
				i2s
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						i2s_config
						i2s_config.
						0x0
						
							
								cr_ofs_en
								25
								25
							
							
								cr_ofs_cnt
								20
								24
							
							
								cr_mono_rx_ch
								19
								19
							
							
								cr_endian
								18
								18
							
							
								cr_i2s_mode
								16
								17
							
							
								cr_data_size
								14
								15
							
							
								cr_frame_size
								12
								13
							
							
								cr_fs_3ch_mode
								8
								8
							
							
								cr_fs_4ch_mode
								7
								7
							
							
								cr_fs_1t_mode
								6
								6
							
							
								cr_mute_mode
								5
								5
							
							
								cr_mono_mode
								4
								4
							
							
								cr_i2s_rxd_en
								3
								3
							
							
								cr_i2s_txd_en
								2
								2
							
							
								cr_i2s_s_en
								1
								1
							
							
								cr_i2s_m_en
								0
								0
							
						
					
					
						i2s_int_sts
						i2s_int_sts.
						0x4
						
							
								cr_i2s_fer_en
								26
								26
							
							
								cr_i2s_rxf_en
								25
								25
							
							
								cr_i2s_txf_en
								24
								24
							
							
								cr_i2s_fer_mask
								10
								10
							
							
								cr_i2s_rxf_mask
								9
								9
							
							
								cr_i2s_txf_mask
								8
								8
							
							
								i2s_fer_int
								2
								2
							
							
								i2s_rxf_int
								1
								1
							
							
								i2s_txf_int
								0
								0
							
						
					
					
						i2s_bclk_config
						i2s_bclk_config.
						0x10
						
							
								cr_bclk_div_h
								16
								27
							
							
								cr_bclk_div_l
								0
								11
							
						
					
					
						i2s_fifo_config_0
						i2s_fifo_config_0.
						0x80
						
							
								cr_fifo_24b_lj
								10
								10
							
							
								cr_fifo_lr_exchg
								9
								9
							
							
								cr_fifo_lr_merge
								8
								8
							
							
								rx_fifo_underflow
								7
								7
							
							
								rx_fifo_overflow
								6
								6
							
							
								tx_fifo_underflow
								5
								5
							
							
								tx_fifo_overflow
								4
								4
							
							
								rx_fifo_clr
								3
								3
							
							
								tx_fifo_clr
								2
								2
							
							
								i2s_dma_rx_en
								1
								1
							
							
								i2s_dma_tx_en
								0
								0
							
						
					
					
						i2s_fifo_config_1
						i2s_fifo_config_1.
						0x84
						
							
								rx_fifo_th
								24
								27
							
							
								tx_fifo_th
								16
								19
							
							
								rx_fifo_cnt
								8
								12
							
							
								tx_fifo_cnt
								0
								4
							
						
					
					
						i2s_fifo_wdata
						i2s_fifo_wdata.
						0x88
						
							
								i2s_fifo_wdata
								0
								31
							
						
					
					
						i2s_fifo_rdata
						i2s_fifo_rdata.
						0x8C
						
							
								i2s_fifo_rdata
								0
								31
							
						
					
					
						i2s_io_config
						i2s_io_config.
						0xFC
						
							
								cr_deg_en
								7
								7
							
							
								cr_deg_cnt
								4
								6
							
							
								cr_i2s_bclk_inv
								3
								3
							
							
								cr_i2s_fs_inv
								2
								2
							
							
								cr_i2s_rxd_inv
								1
								1
							
							
								cr_i2s_txd_inv
								0
								0
							
						
					
				
			
			
				cam
				cam.
				0x4000AD00
				cam
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						dvp2axi_configue
						dvp2axi_configue.
						0x0
						
							
								reg_dvp_wait_cycle
								24
								31
							
							
								reg_dvp_pix_clk_cg
								20
								20
							
							
								reg_interlv_mode
								16
								16
							
							
								reg_subsample_even
								15
								15
							
							
								reg_subsample_en
								14
								14
							
							
								reg_drop_even
								13
								13
							
							
								reg_drop_en
								12
								12
							
							
								reg_hw_mode_fwrap
								11
								11
							
							
								reg_dvp_mode
								8
								10
							
							
								reg_hburst
								4
								5
							
							
								reg_line_vld_pol
								3
								3
							
							
								reg_fram_vld_pol
								2
								2
							
							
								reg_sw_mode
								1
								1
							
							
								reg_dvp_enable
								0
								0
							
						
					
					
						dvp2ahb_addr_start_0
						dvp2ahb_addr_start_0.
						0x4
						
							
								reg_addr_start_0
								0
								31
							
						
					
					
						dvp2ahb_mem_bcnt_0
						dvp2ahb_mem_bcnt_0.
						0x8
						
							
								reg_mem_burst_cnt_0
								0
								31
							
						
					
					
						dvp2ahb_frame_bcnt_0
						dvp2ahb_frame_bcnt_0.
						0xC
						
							
								reg_frame_burst_cnt_0
								0
								31
							
						
					
					
						dvp2ahb_addr_start_1
						dvp2ahb_addr_start_1.
						0x10
						
							
								reg_addr_start_1
								0
								31
							
						
					
					
						dvp2ahb_mem_bcnt_1
						dvp2ahb_mem_bcnt_1.
						0x14
						
							
								reg_mem_burst_cnt_1
								0
								31
							
						
					
					
						dvp2ahb_frame_bcnt_1
						dvp2ahb_frame_bcnt_1.
						0x18
						
							
								reg_frame_burst_cnt_1
								0
								31
							
						
					
					
						dvp_status_and_error
						dvp_status_and_error.
						0x1C
						
							
								st_bus_flsh
								31
								31
							
							
								st_bus_wait
								30
								30
							
							
								st_bus_func
								29
								29
							
							
								st_bus_idle
								28
								28
							
							
								frame_valid_cnt_1
								24
								27
							
							
								frame_valid_cnt_0
								20
								23
							
							
								st_dvp_idle
								19
								19
							
							
								ahb_idle_1
								17
								17
							
							
								ahb_idle_0
								16
								16
							
							
								sts_vcnt_int
								9
								9
							
							
								sts_hcnt_int
								8
								8
							
							
								sts_fifo_int_1
								7
								7
							
							
								sts_fifo_int_0
								6
								6
							
							
								sts_frame_int_1
								5
								5
							
							
								sts_frame_int_0
								4
								4
							
							
								sts_mem_int_1
								3
								3
							
							
								sts_mem_int_0
								2
								2
							
							
								sts_normal_int_1
								1
								1
							
							
								sts_normal_int_0
								0
								0
							
						
					
					
						dvp_frame_fifo_pop
						dvp_frame_fifo_pop.
						0x20
						
							
								reg_int_fifo_clr_1
								19
								19
							
							
								reg_int_frame_clr_1
								18
								18
							
							
								reg_int_mem_clr_1
								17
								17
							
							
								reg_int_normal_clr_1
								16
								16
							
							
								reg_int_vcnt_clr_0
								9
								9
							
							
								reg_int_hcnt_clr_0
								8
								8
							
							
								reg_int_fifo_clr_0
								7
								7
							
							
								reg_int_frame_clr_0
								6
								6
							
							
								reg_int_mem_clr_0
								5
								5
							
							
								reg_int_normal_clr_0
								4
								4
							
							
								rfifo_pop_1
								1
								1
							
							
								rfifo_pop_0
								0
								0
							
						
					
					
						snsr_control
						snsr_control.
						0x24
						
							
								reg_cam_pwdn
								1
								1
							
							
								reg_cam_rst
								0
								0
							
						
					
					
						int_control
						int_control.
						0x28
						
							
								reg_frame_cnt_trgr_int
								28
								31
							
							
								reg_int_vcnt_en
								6
								6
							
							
								reg_int_hcnt_en
								5
								5
							
							
								reg_int_fifo_en
								4
								4
							
							
								reg_int_frame_en
								3
								3
							
							
								reg_int_mem_en
								2
								2
							
							
								reg_int_normal_1_en
								1
								1
							
							
								reg_int_normal_0_en
								0
								0
							
						
					
					
						hsync_control
						hsync_control.
						0x30
						
							
								reg_hsync_act_start
								16
								31
							
							
								reg_hsync_act_end
								0
								15
							
						
					
					
						vsync_control
						vsync_control.
						0x34
						
							
								reg_vsync_act_start
								16
								31
							
							
								reg_vsync_act_end
								0
								15
							
						
					
					
						frame_size_control
						frame_size_control.
						0x38
						
							
								reg_total_vcnt
								16
								31
							
							
								reg_total_hcnt
								0
								15
							
						
					
					
						frame_start_addr0_0
						frame_start_addr0_0.
						0x40
						
							
								frame_start_addr_0_0
								0
								31
							
						
					
					
						frame_byte_cnt0_0
						frame_byte_cnt0_0.
						0x44
						
							
								frame_byte_cnt_0_0
								0
								31
							
						
					
					
						frame_start_addr0_1
						frame_start_addr0_1.
						0x48
						
							
								frame_start_addr_0_1
								0
								31
							
						
					
					
						frame_byte_cnt0_1
						frame_byte_cnt0_1.
						0x4C
						
							
								frame_byte_cnt_0_1
								0
								31
							
						
					
					
						frame_start_addr0_2
						frame_start_addr0_2.
						0x50
						
							
								frame_start_addr_0_2
								0
								31
							
						
					
					
						frame_byte_cnt0_2
						frame_byte_cnt0_2.
						0x54
						
							
								frame_byte_cnt_0_2
								0
								31
							
						
					
					
						frame_start_addr0_3
						frame_start_addr0_3.
						0x58
						
							
								frame_start_addr_0_3
								0
								31
							
						
					
					
						frame_byte_cnt0_3
						frame_byte_cnt0_3.
						0x5C
						
							
								frame_byte_cnt_0_3
								0
								31
							
						
					
					
						frame_start_addr0_4
						frame_start_addr0_4.
						0x60
						
							
								frame_start_addr_0_4
								0
								31
							
						
					
					
						frame_byte_cnt0_4
						frame_byte_cnt0_4.
						0x64
						
							
								frame_byte_cnt_0_4
								0
								31
							
						
					
					
						frame_start_addr0_5
						frame_start_addr0_5.
						0x68
						
							
								frame_start_addr_0_5
								0
								31
							
						
					
					
						frame_byte_cnt0_5
						frame_byte_cnt0_5.
						0x6C
						
							
								frame_byte_cnt_0_5
								0
								31
							
						
					
					
						frame_start_addr0_6
						frame_start_addr0_6.
						0x70
						
							
								frame_start_addr_0_6
								0
								31
							
						
					
					
						frame_byte_cnt0_6
						frame_byte_cnt0_6.
						0x74
						
							
								frame_byte_cnt_0_6
								0
								31
							
						
					
					
						frame_start_addr0_7
						frame_start_addr0_7.
						0x78
						
							
								frame_start_addr_0_7
								0
								31
							
						
					
					
						frame_byte_cnt0_7
						frame_byte_cnt0_7.
						0x7C
						
							
								frame_byte_cnt_0_7
								0
								31
							
						
					
					
						frame_start_addr1_0
						frame_start_addr1_0.
						0x80
						
							
								frame_start_addr_1_0
								0
								31
							
						
					
					
						frame_byte_cnt1_0
						frame_byte_cnt1_0.
						0x84
						
							
								frame_byte_cnt_1_0
								0
								31
							
						
					
					
						frame_start_addr1_1
						frame_start_addr1_1.
						0x88
						
							
								frame_start_addr_1_1
								0
								31
							
						
					
					
						frame_byte_cnt1_1
						frame_byte_cnt1_1.
						0x8C
						
							
								frame_byte_cnt_1_1
								0
								31
							
						
					
					
						frame_start_addr1_2
						frame_start_addr1_2.
						0x90
						
							
								frame_start_addr_1_2
								0
								31
							
						
					
					
						frame_byte_cnt1_2
						frame_byte_cnt1_2.
						0x94
						
							
								frame_byte_cnt_1_2
								0
								31
							
						
					
					
						frame_start_addr1_3
						frame_start_addr1_3.
						0x98
						
							
								frame_start_addr_1_3
								0
								31
							
						
					
					
						frame_byte_cnt1_3
						frame_byte_cnt1_3.
						0x9C
						
							
								frame_byte_cnt_1_3
								0
								31
							
						
					
					
						frame_start_addr1_4
						frame_start_addr1_4.
						0xA0
						
							
								frame_start_addr_1_4
								0
								31
							
						
					
					
						frame_byte_cnt1_4
						frame_byte_cnt1_4.
						0xA4
						
							
								frame_byte_cnt_1_4
								0
								31
							
						
					
					
						frame_start_addr1_5
						frame_start_addr1_5.
						0xA8
						
							
								frame_start_addr_1_5
								0
								31
							
						
					
					
						frame_byte_cnt1_5
						frame_byte_cnt1_5.
						0xAC
						
							
								frame_byte_cnt_1_5
								0
								31
							
						
					
					
						frame_start_addr1_6
						frame_start_addr1_6.
						0xB0
						
							
								frame_start_addr_1_6
								0
								31
							
						
					
					
						frame_byte_cnt1_6
						frame_byte_cnt1_6.
						0xB4
						
							
								frame_byte_cnt_1_6
								0
								31
							
						
					
					
						frame_start_addr1_7
						frame_start_addr1_7.
						0xB8
						
							
								frame_start_addr_1_7
								0
								31
							
						
					
					
						frame_byte_cnt1_7
						frame_byte_cnt1_7.
						0xBC
						
							
								frame_byte_cnt_1_7
								0
								31
							
						
					
					
						dvp_debug
						dvp_debug.
						0xFF0
						
							
								reg_dvp_dbg_sel
								1
								3
							
							
								reg_dvp_dbg_en
								0
								0
							
						
					
					
						dvp_dummy_reg
						dvp_dummy_reg.
						0xFFC
						
							
								RESERVED_31_0
								0
								31
							
						
					
				
			
			
				mjpeg
				mjpeg.
				0x4000AE00
				mjpeg
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						mjpeg_control_1
						mjpeg_control_1.
						0x0
						
							
								reg_v0_order
								30
								31
							
							
								reg_y1_order
								28
								29
							
							
								reg_u0_order
								26
								27
							
							
								reg_y0_order
								24
								25
							
							
								reg_q_mode
								16
								22
							
							
								reg_yuv_mode
								12
								13
							
							
								reg_h_bust
								8
								9
							
							
								reg_reflect_dmy
								6
								6
							
							
								reg_last_hf_hblk_dmy
								5
								5
							
							
								reg_last_hf_wblk_dmy
								4
								4
							
							
								reg_wr_over_stop
								3
								3
							
							
								reg_order_u_even
								2
								2
							
							
								reg_mjpeg_bit_order
								1
								1
							
							
								reg_mjpeg_enable
								0
								0
							
						
					
					
						mjpeg_control_2
						mjpeg_control_2.
						0x4
						
							
								reg_mjpeg_wait_cycle
								16
								31
							
							
								reg_uv_dvp2ahb_fsel
								15
								15
							
							
								reg_uv_dvp2ahb_lsel
								14
								14
							
							
								reg_yy_dvp2ahb_fsel
								13
								13
							
							
								reg_yy_dvp2ahb_lsel
								12
								12
							
							
								reg_mjpeg_sw_run
								9
								9
							
							
								reg_mjpeg_sw_mode
								8
								8
							
							
								reg_sw_frame
								0
								4
							
						
					
					
						mjpeg_yy_frame_addr
						mjpeg_yy_frame_addr.
						0x08
						
							
								reg_yy_addr_start
								0
								31
							
						
					
					
						mjpeg_uv_frame_addr
						mjpeg_uv_frame_addr.
						0x0C
						
							
								reg_uv_addr_start
								0
								31
							
						
					
					
						mjpeg_yuv_mem
						mjpeg_yuv_mem.
						0x10
						
							
								reg_uv_mem_hblk
								16
								28
							
							
								reg_yy_mem_hblk
								0
								12
							
						
					
					
						jpeg_frame_addr
						jpeg_frame_addr.
						0x14
						
							
								reg_w_addr_start
								0
								31
							
						
					
					
						jpeg_store_memory
						jpeg_store_memory.
						0x18
						
							
								reg_w_burst_cnt
								0
								31
							
						
					
					
						mjpeg_control_3
						mjpeg_control_3.
						0x1C
						
							
								sts_swap_int
								30
								30
							
							
								reg_int_swap_en
								29
								29
							
							
								frame_valid_cnt
								24
								28
							
							
								sts_idle_int
								22
								22
							
							
								reg_int_idle_en
								21
								21
							
							
								reg_frame_cnt_trgr_int
								16
								20
							
							
								ahb_idle
								14
								14
							
							
								mjpeg_manf
								13
								13
							
							
								mjpeg_mans
								12
								12
							
							
								mjpeg_flsh
								11
								11
							
							
								mjpeg_wait
								10
								10
							
							
								mjpeg_func
								9
								9
							
							
								mjpeg_idle
								8
								8
							
							
								sts_frame_int
								7
								7
							
							
								sts_mem_int
								6
								6
							
							
								sts_cam_int
								5
								5
							
							
								sts_normal_int
								4
								4
							
							
								reg_int_frame_en
								3
								3
							
							
								reg_int_mem_en
								2
								2
							
							
								reg_int_cam_en
								1
								1
							
							
								reg_int_normal_en
								0
								0
							
						
					
					
						mjpeg_frame_fifo_pop
						mjpeg_frame_fifo_pop.
						0x20
						
							
								reg_int_swap_clr
								13
								13
							
							
								reg_int_idle_clr
								12
								12
							
							
								reg_int_frame_clr
								11
								11
							
							
								reg_int_mem_clr
								10
								10
							
							
								reg_int_cam_clr
								9
								9
							
							
								reg_int_normal_clr
								8
								8
							
							
								reg_w_swap_clr
								1
								1
							
							
								rfifo_pop
								0
								0
							
						
					
					
						mjpeg_frame_size
						mjpeg_frame_size.
						0x24
						
							
								reg_frame_hblk
								16
								27
							
							
								reg_frame_wblk
								0
								11
							
						
					
					
						mjpeg_header_byte
						mjpeg_header_byte.
						0x28
						
							
								reg_tail_exp
								16
								16
							
							
								reg_head_byte
								0
								11
							
						
					
					
						mjpeg_swap_mode
						mjpeg_swap_mode.
						0x30
						
							
								sts_swap_fend
								12
								12
							
							
								sts_swap_fstart
								11
								11
							
							
								sts_read_swap_idx
								10
								10
							
							
								sts_swap1_full
								9
								9
							
							
								sts_swap0_full
								8
								8
							
							
								reg_w_swap_mode
								0
								0
							
						
					
					
						mjpeg_swap_bit_cnt
						mjpeg_swap_bit_cnt.
						0x34
						
							
								frame_swap_end_bit_cnt
								0
								31
							
						
					
					
						mjpeg_paket_ctrl
						mjpeg_paket_ctrl.
						0x38
						
							
								reg_pket_body_byte
								16
								31
							
							
								reg_jend_to_pend
								1
								1
							
							
								reg_pket_en
								0
								0
							
						
					
					
						mjpeg_paket_head_tail
						mjpeg_paket_head_tail.
						0x3C
						
							
								reg_pket_tail_byte
								16
								27
							
							
								reg_pket_head_byte
								0
								11
							
						
					
					
						mjpeg_Y_frame_read_status_1
						mjpeg_Y_frame_read_status_1.
						0x40
						
							
								yy_frm_hblk_r
								16
								28
							
							
								yy_mem_hblk_r
								0
								12
							
						
					
					
						mjpeg_Y_frame_read_status_2
						mjpeg_Y_frame_read_status_2.
						0x44
						
							
								yy_frm_cnt_r
								24
								31
							
							
								yy_mem_rnd_r
								16
								23
							
							
								yy_wblk_r
								0
								12
							
						
					
					
						mjpeg_Y_frame_write_status
						mjpeg_Y_frame_write_status.
						0x48
						
							
								yy_frm_cnt_w
								24
								31
							
							
								yy_mem_rnd_w
								16
								23
							
							
								yy_mem_hblk_w
								0
								12
							
						
					
					
						mjpeg_UV_frame_read_status_1
						mjpeg_UV_frame_read_status_1.
						0x4C
						
							
								uv_frm_hblk_r
								16
								28
							
							
								uv_mem_hblk_r
								0
								12
							
						
					
					
						mjpeg_UV_frame_read_status_2
						mjpeg_UV_frame_read_status_2.
						0x50
						
							
								uv_frm_cnt_r
								24
								31
							
							
								uv_mem_rnd_r
								16
								23
							
							
								uv_wblk_r
								0
								12
							
						
					
					
						mjpeg_UV_frame_write_status
						mjpeg_UV_frame_write_status.
						0x54
						
							
								uv_frm_cnt_w
								24
								31
							
							
								uv_mem_rnd_w
								16
								23
							
							
								uv_mem_hblk_w
								0
								12
							
						
					
					
						mjpeg_start_addr0
						mjpeg_start_addr0.
						0x80
						
							
								frame_start_addr_0
								0
								31
							
						
					
					
						mjpeg_bit_cnt0
						mjpeg_bit_cnt0.
						0x84
						
							
								frame_bit_cnt_0
								0
								31
							
						
					
					
						mjpeg_start_addr1
						mjpeg_start_addr1.
						0x88
						
							
								frame_start_addr_1
								0
								31
							
						
					
					
						mjpeg_bit_cnt1
						mjpeg_bit_cnt1.
						0x8C
						
							
								frame_bit_cnt_1
								0
								31
							
						
					
					
						mjpeg_start_addr2
						mjpeg_start_addr2.
						0x90
						
							
								frame_start_addr_2
								0
								31
							
						
					
					
						mjpeg_bit_cnt2
						mjpeg_bit_cnt2.
						0x94
						
							
								frame_bit_cnt_2
								0
								31
							
						
					
					
						mjpeg_start_addr3
						mjpeg_start_addr3.
						0x98
						
							
								frame_start_addr_3
								0
								31
							
						
					
					
						mjpeg_bit_cnt3
						mjpeg_bit_cnt3.
						0x9C
						
							
								frame_bit_cnt_3
								0
								31
							
						
					
					
						mjpeg_start_addr4
						mjpeg_start_addr4.
						0xA0
						
							
								frame_start_addr_4
								0
								31
							
						
					
					
						mjpeg_bit_cnt4
						mjpeg_bit_cnt4.
						0xA4
						
							
								frame_bit_cnt_4
								0
								31
							
						
					
					
						mjpeg_start_addr5
						mjpeg_start_addr5.
						0xA8
						
							
								frame_start_addr_5
								0
								31
							
						
					
					
						mjpeg_bit_cnt5
						mjpeg_bit_cnt5.
						0xAC
						
							
								frame_bit_cnt_5
								0
								31
							
						
					
					
						mjpeg_start_addr6
						mjpeg_start_addr6.
						0xB0
						
							
								frame_start_addr_6
								0
								31
							
						
					
					
						mjpeg_bit_cnt6
						mjpeg_bit_cnt6.
						0xB4
						
							
								frame_bit_cnt_6
								0
								31
							
						
					
					
						mjpeg_start_addr7
						mjpeg_start_addr7.
						0xB8
						
							
								frame_start_addr_7
								0
								31
							
						
					
					
						mjpeg_bit_cnt7
						mjpeg_bit_cnt7.
						0xBC
						
							
								frame_bit_cnt_7
								0
								31
							
						
					
					
						mjpeg_start_addr_8
						mjpeg_start_addr_8.
						0xC0
						
							
								frame_start_addr_8
								0
								31
							
						
					
					
						mjpeg_bit_cnt_8
						mjpeg_bit_cnt_8.
						0xC4
						
							
								frame_bit_cnt_8
								0
								31
							
						
					
					
						mjpeg_start_addr_9
						mjpeg_start_addr_9.
						0xC8
						
							
								frame_start_addr_9
								0
								31
							
						
					
					
						mjpeg_bit_cnt_9
						mjpeg_bit_cnt_9.
						0xCC
						
							
								frame_bit_cnt_9
								0
								31
							
						
					
					
						mjpeg_start_addr_a
						mjpeg_start_addr_a.
						0xD0
						
							
								frame_start_addr_a
								0
								31
							
						
					
					
						mjpeg_bit_cnt_a
						mjpeg_bit_cnt_a.
						0xD4
						
							
								frame_bit_cnt_a
								0
								31
							
						
					
					
						mjpeg_start_addr_b
						mjpeg_start_addr_b.
						0xD8
						
							
								frame_start_addr_b
								0
								31
							
						
					
					
						mjpeg_bit_cnt_b
						mjpeg_bit_cnt_b.
						0xDC
						
							
								frame_bit_cnt_b
								0
								31
							
						
					
					
						mjpeg_start_addr_c
						mjpeg_start_addr_c.
						0xE0
						
							
								frame_start_addr_c
								0
								31
							
						
					
					
						mjpeg_bit_cnt_c
						mjpeg_bit_cnt_c.
						0xE4
						
							
								frame_bit_cnt_c
								0
								31
							
						
					
					
						mjpeg_start_addr_d
						mjpeg_start_addr_d.
						0xE8
						
							
								frame_start_addr_d
								0
								31
							
						
					
					
						mjpeg_bit_cnt_d
						mjpeg_bit_cnt_d.
						0xEC
						
							
								frame_bit_cnt_d
								0
								31
							
						
					
					
						mjpeg_start_addr_e
						mjpeg_start_addr_e.
						0xF0
						
							
								frame_start_addr_e
								0
								31
							
						
					
					
						mjpeg_bit_cnt_e
						mjpeg_bit_cnt_e.
						0xF4
						
							
								frame_bit_cnt_e
								0
								31
							
						
					
					
						mjpeg_start_addr_f
						mjpeg_start_addr_f.
						0xF8
						
							
								frame_start_addr_f
								0
								31
							
						
					
					
						mjpeg_bit_cnt_f
						mjpeg_bit_cnt_f.
						0xFC
						
							
								frame_bit_cnt_f
								0
								31
							
						
					
					
						mjpeg_q_mode0
						mjpeg_q_mode0.
						0x100
						
							
								frame_q_mode_0
								0
								6
							
						
					
					
						mjpeg_q_mode1
						mjpeg_q_mode1.
						0x104
						
							
								frame_q_mode_1
								0
								6
							
						
					
					
						mjpeg_q_mode2
						mjpeg_q_mode2.
						0x108
						
							
								frame_q_mode_2
								0
								6
							
						
					
					
						mjpeg_q_mode3
						mjpeg_q_mode3.
						0x10C
						
							
								frame_q_mode_3
								0
								6
							
						
					
					
						mjpeg_q_mode4
						mjpeg_q_mode4.
						0x110
						
							
								frame_q_mode_4
								0
								6
							
						
					
					
						mjpeg_q_mode5
						mjpeg_q_mode5.
						0x114
						
							
								frame_q_mode_5
								0
								6
							
						
					
					
						mjpeg_q_mode6
						mjpeg_q_mode6.
						0x118
						
							
								frame_q_mode_6
								0
								6
							
						
					
					
						mjpeg_q_mode7
						mjpeg_q_mode7.
						0x11C
						
							
								frame_q_mode_7
								0
								6
							
						
					
					
						mjpeg_q_mode_8
						mjpeg_q_mode_8.
						0x120
						
							
								frame_q_mode_8
								0
								6
							
						
					
					
						mjpeg_q_mode_9
						mjpeg_q_mode_9.
						0x124
						
							
								frame_q_mode_9
								0
								6
							
						
					
					
						mjpeg_q_mode_a
						mjpeg_q_mode_a.
						0x128
						
							
								frame_q_mode_a
								0
								6
							
						
					
					
						mjpeg_q_mode_b
						mjpeg_q_mode_b.
						0x12C
						
							
								frame_q_mode_b
								0
								6
							
						
					
					
						mjpeg_q_mode_c
						mjpeg_q_mode_c.
						0x130
						
							
								frame_q_mode_c
								0
								6
							
						
					
					
						mjpeg_q_mode_d
						mjpeg_q_mode_d.
						0x134
						
							
								frame_q_mode_d
								0
								6
							
						
					
					
						mjpeg_q_mode_e
						mjpeg_q_mode_e.
						0x138
						
							
								frame_q_mode_e
								0
								6
							
						
					
					
						mjpeg_q_mode_f
						mjpeg_q_mode_f.
						0x13C
						
							
								frame_q_mode_f
								0
								6
							
						
					
					
						mjpeg_debug
						mjpeg_debug.
						0x1F0
						
							
								reg_mjpeg_dbg_sel
								4
								7
							
							
								reg_mjpeg_dbg_en
								0
								0
							
						
					
					
						mjpeg_dummy_reg
						mjpeg_dummy_reg.
						0x1FC
						
							
								mjpeg_dummy_reg
								0
								31
							
						
					
				
			
			
				sf_ctrl
				sf_ctrl.
				0x4000B000
				sf_ctrl
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						sf_ctrl_0
						sf_ctrl_0.
						0x0
						
							
								sf_id
								24
								31
							
							
								sf_aes_iv_endian
								23
								23
							
							
								sf_aes_key_endian
								22
								22
							
							
								sf_aes_ctr_plus_en
								21
								21
							
							
								sf_aes_dout_endian
								20
								20
							
							
								sf_aes_dly_mode
								19
								19
							
							
								sf_if_int_set
								18
								18
							
							
								sf_if_int_clr
								17
								17
							
							
								sf_if_int
								16
								16
							
							
								sf_if_read_dly_en
								11
								11
							
							
								sf_if_read_dly_n
								8
								10
							
							
								sf_clk_sahb_sram_sel
								5
								5
							
							
								sf_clk_out_inv_sel
								4
								4
							
							
								sf_clk_out_gate_en
								3
								3
							
							
								sf_clk_sf_rx_inv_sel
								2
								2
							
						
					
					
						sf_ctrl_1
						sf_ctrl_1.
						0x4
						
							
								sf_ahb2sram_en
								31
								31
							
							
								sf_ahb2sif_en
								30
								30
							
							
								sf_if_en
								29
								29
							
							
								sf_if_fn_sel
								28
								28
							
							
								sf_ahb2sif_stop
								27
								27
							
							
								sf_ahb2sif_stopped
								26
								26
							
							
								sf_if_reg_wp
								25
								25
							
							
								sf_if_reg_hold
								24
								24
							
							
								sf_if_0_ack_lat
								20
								22
							
							
								sf_if_sr_int_set
								18
								18
							
							
								sf_if_sr_int_en
								17
								17
							
							
								sf_if_sr_int
								16
								16
							
							
								sf_if_sr_pat
								8
								15
							
							
								sf_if_sr_pat_mask
								0
								7
							
						
					
					
						sf_if_sahb_0
						sf_if_sahb_0.
						0x8
						
							
								sf_if_0_qpi_mode_en
								31
								31
							
							
								sf_if_0_spi_mode
								28
								30
							
							
								sf_if_0_cmd_en
								27
								27
							
							
								sf_if_0_adr_en
								26
								26
							
							
								sf_if_0_dmy_en
								25
								25
							
							
								sf_if_0_dat_en
								24
								24
							
							
								sf_if_0_dat_rw  
								23
								23
							
							
								sf_if_0_cmd_byte
								20
								22
							
							
								sf_if_0_adr_byte
								17
								19
							
							
								sf_if_0_dmy_byte
								12
								16
							
							
								sf_if_0_dat_byte
								2
								11
							
							
								sf_if_0_trig
								1
								1
							
							
								sf_if_busy
								0
								0
							
						
					
					
						sf_if_sahb_1
						sf_if_sahb_1.
						0xC
						
							
								sf_if_0_cmd_buf_0
								0
								31
							
						
					
					
						sf_if_sahb_2
						sf_if_sahb_2.
						0x10
						
							
								sf_if_0_cmd_buf_1
								0
								31
							
						
					
					
						sf_if_iahb_0
						sf_if_iahb_0.
						0x14
						
							
								sf_if_1_qpi_mode_en
								31
								31
							
							
								sf_if_1_spi_mode
								28
								30
							
							
								sf_if_1_cmd_en
								27
								27
							
							
								sf_if_1_adr_en
								26
								26
							
							
								sf_if_1_dmy_en
								25
								25
							
							
								sf_if_1_dat_en
								24
								24
							
							
								sf_if_1_dat_rw  
								23
								23
							
							
								sf_if_1_cmd_byte
								20
								22
							
							
								sf_if_1_adr_byte
								17
								19
							
							
								sf_if_1_dmy_byte
								12
								16
							
						
					
					
						sf_if_iahb_1
						sf_if_iahb_1.
						0x18
						
							
								sf_if_1_cmd_buf_0
								0
								31
							
						
					
					
						sf_if_iahb_2
						sf_if_iahb_2.
						0x1C
						
							
								sf_if_1_cmd_buf_1
								0
								31
							
						
					
					
						sf_if_status_0
						sf_if_status_0.
						0x20
						
							
								sf_if_status_0
								0
								31
							
						
					
					
						sf_if_status_1
						sf_if_status_1.
						0x24
						
							
								sf_if_status_1
								0
								31
							
						
					
					
						sf_aes
						sf_aes.
						0x28
						
							
								sf_aes_status
								5
								31
							
							
								sf_aes_pref_busy
								4
								4
							
							
								sf_aes_pref_trig
								3
								3
							
							
								sf_aes_mode
								1
								2
							
							
								sf_aes_en
								0
								0
							
						
					
					
						sf_ahb2sif_status
						sf_ahb2sif_status.
						0x2C
						
							
								sf_ahb2sif_status
								0
								31
							
						
					
					
						sf_if_io_dly_0
						sf_if_io_dly_0.
						0x30
						
							
								sf_dqs_do_dly_sel
								30
								31
							
							
								sf_dqs_di_dly_sel
								28
								29
							
							
								sf_dqs_oe_dly_sel
								26
								27
							
							
								sf_clk_out_dly_sel
								8
								9
							
							
								sf_cs2_dly_sel
								2
								3
							
							
								sf_cs_dly_sel
								0
								1
							
						
					
					
						sf_if_io_dly_1
						sf_if_io_dly_1.
						0x34
						
							
								sf_io_0_do_dly_sel
								16
								17
							
							
								sf_io_0_di_dly_sel
								8
								9
							
							
								sf_io_0_oe_dly_sel
								0
								1
							
						
					
					
						sf_if_io_dly_2
						sf_if_io_dly_2.
						0x38
						
							
								sf_io_1_do_dly_sel
								16
								17
							
							
								sf_io_1_di_dly_sel
								8
								9
							
							
								sf_io_1_oe_dly_sel
								0
								1
							
						
					
					
						sf_if_io_dly_3
						sf_if_io_dly_3.
						0x3C
						
							
								sf_io_2_do_dly_sel
								16
								17
							
							
								sf_io_2_di_dly_sel
								8
								9
							
							
								sf_io_2_oe_dly_sel
								0
								1
							
						
					
					
						sf_if_io_dly_4
						sf_if_io_dly_4.
						0x40
						
							
								sf_io_3_do_dly_sel
								16
								17
							
							
								sf_io_3_di_dly_sel
								8
								9
							
							
								sf_io_3_oe_dly_sel
								0
								1
							
						
					
					
						sf_reserved
						sf_reserved.
						0x44
						
							
								sf_reserved
								0
								31
							
						
					
					
						sf2_if_io_dly_0
						sf2_if_io_dly_0.
						0x48
						
							
								sf2_dqs_do_dly_sel
								30
								31
							
							
								sf2_dqs_di_dly_sel
								28
								29
							
							
								sf2_dqs_oe_dly_sel
								26
								27
							
							
								sf2_clk_out_dly_sel
								8
								9
							
							
								sf2_cs2_dly_sel
								2
								3
							
							
								sf2_cs_dly_sel
								0
								1
							
						
					
					
						sf2_if_io_dly_1
						sf2_if_io_dly_1.
						0x4C
						
							
								sf2_io_0_do_dly_sel
								16
								17
							
							
								sf2_io_0_di_dly_sel
								8
								9
							
							
								sf2_io_0_oe_dly_sel
								0
								1
							
						
					
					
						sf2_if_io_dly_2
						sf2_if_io_dly_2.
						0x50
						
							
								sf2_io_1_do_dly_sel
								16
								17
							
							
								sf2_io_1_di_dly_sel
								8
								9
							
							
								sf2_io_1_oe_dly_sel
								0
								1
							
						
					
					
						sf2_if_io_dly_3
						sf2_if_io_dly_3.
						0x54
						
							
								sf2_io_2_do_dly_sel
								16
								17
							
							
								sf2_io_2_di_dly_sel
								8
								9
							
							
								sf2_io_2_oe_dly_sel
								0
								1
							
						
					
					
						sf2_if_io_dly_4
						sf2_if_io_dly_4.
						0x58
						
							
								sf2_io_3_do_dly_sel
								16
								17
							
							
								sf2_io_3_di_dly_sel
								8
								9
							
							
								sf2_io_3_oe_dly_sel
								0
								1
							
						
					
					
						sf3_if_io_dly_0
						sf3_if_io_dly_0.
						0x5C
						
							
								sf3_dqs_do_dly_sel
								30
								31
							
							
								sf3_dqs_di_dly_sel
								28
								29
							
							
								sf3_dqs_oe_dly_sel
								26
								27
							
							
								sf3_clk_out_dly_sel
								8
								9
							
							
								sf3_cs2_dly_sel
								2
								3
							
							
								sf3_cs_dly_sel
								0
								1
							
						
					
					
						sf3_if_io_dly_1
						sf3_if_io_dly_1.
						0x60
						
							
								sf3_io_0_do_dly_sel
								16
								17
							
							
								sf3_io_0_di_dly_sel
								8
								9
							
							
								sf3_io_0_oe_dly_sel
								0
								1
							
						
					
					
						sf3_if_io_dly_2
						sf3_if_io_dly_2.
						0x64
						
							
								sf3_io_1_do_dly_sel
								16
								17
							
							
								sf3_io_1_di_dly_sel
								8
								9
							
							
								sf3_io_1_oe_dly_sel
								0
								1
							
						
					
					
						sf3_if_io_dly_3
						sf3_if_io_dly_3.
						0x68
						
							
								sf3_io_2_do_dly_sel
								16
								17
							
							
								sf3_io_2_di_dly_sel
								8
								9
							
							
								sf3_io_2_oe_dly_sel
								0
								1
							
						
					
					
						sf3_if_io_dly_4
						sf3_if_io_dly_4.
						0x6C
						
							
								sf3_io_3_do_dly_sel
								16
								17
							
							
								sf3_io_3_di_dly_sel
								8
								9
							
							
								sf3_io_3_oe_dly_sel
								0
								1
							
						
					
					
						sf_ctrl_2
						sf_ctrl_2.
						0x70
						
							
								sf_if_0_bk_sel
								31
								31
							
							
								sf_if_bk2_en
								30
								30
							
							
								sf_if_bk2_mode
								29
								29
							
							
								sf_if_bk_swap
								28
								28
							
							
								sf_if_dqs_en
								5
								5
							
							
								sf_if_dtr_en
								4
								4
							
							
								sf_if_pad_sel_lock
								3
								3
							
							
								sf_if_pad_sel
								0
								1
							
						
					
					
						sf_ctrl_3
						sf_ctrl_3.
						0x74
						
							
								sf_if_1_ack_lat
								29
								31
							
							
								sf_cmds_wrap_q
								11
								11
							
							
								sf_cmds_wrap_mode
								10
								10
							
							
								sf_cmds_wrap_q_ini
								9
								9
							
							
								sf_cmds_bt_en
								8
								8
							
							
								sf_cmds_bt_dly
								5
								7
							
							
								sf_cmds_en
								4
								4
							
							
								sf_cmds_wrap_len
								0
								3
							
						
					
					
						sf_if_iahb_3
						sf_if_iahb_3.
						0x78
						
							
								sf_if_2_qpi_mode_en
								31
								31
							
							
								sf_if_2_spi_mode
								28
								30
							
							
								sf_if_2_cmd_en
								27
								27
							
							
								sf_if_2_adr_en
								26
								26
							
							
								sf_if_2_dmy_en
								25
								25
							
							
								sf_if_2_dat_en
								24
								24
							
							
								sf_if_2_dat_rw  
								23
								23
							
							
								sf_if_2_cmd_byte
								20
								22
							
							
								sf_if_2_adr_byte
								17
								19
							
							
								sf_if_2_dmy_byte
								12
								16
							
						
					
					
						sf_if_iahb_4
						sf_if_iahb_4.
						0x7C
						
							
								sf_if_2_cmd_buf_0
								0
								31
							
						
					
					
						sf_if_iahb_5
						sf_if_iahb_5.
						0x80
						
							
								sf_if_2_cmd_buf_1
								0
								31
							
						
					
					
						sf_if_iahb_6
						sf_if_iahb_6.
						0x84
						
							
								sf_if_3_qpi_mode_en
								31
								31
							
							
								sf_if_3_spi_mode
								28
								30
							
							
								sf_if_3_cmd_en
								27
								27
							
							
								sf_if_3_adr_en
								26
								26
							
							
								sf_if_3_cmd_byte
								20
								22
							
							
								sf_if_3_adr_byte
								17
								19
							
						
					
					
						sf_if_iahb_7
						sf_if_iahb_7.
						0x88
						
							
								sf_if_3_cmd_buf_0
								0
								31
							
						
					
					
						sf_if_iahb_8
						sf_if_iahb_8.
						0x8C
						
							
								sf_if_3_cmd_buf_1
								0
								31
							
						
					
					
						sf_if_iahb_9
						sf_if_iahb_9.
						0x90
						
							
								sf_if_4_qpi_mode_en
								31
								31
							
							
								sf_if_4_spi_mode
								28
								30
							
							
								sf_if_4_cmd_en
								27
								27
							
							
								sf_if_4_adr_en
								26
								26
							
							
								sf_if_4_dmy_en
								25
								25
							
							
								sf_if_4_dat_en
								24
								24
							
							
								sf_if_4_dat_rw  
								23
								23
							
							
								sf_if_4_cmd_byte
								20
								22
							
							
								sf_if_4_adr_byte
								17
								19
							
							
								sf_if_4_dmy_byte
								12
								16
							
						
					
					
						sf_if_iahb_10
						sf_if_iahb_10.
						0x94
						
							
								sf_if_4_cmd_buf_0
								0
								31
							
						
					
					
						sf_if_iahb_11
						sf_if_iahb_11.
						0x98
						
							
								sf_if_4_cmd_buf_1
								0
								31
							
						
					
					
						sf_if_iahb_12
						sf_if_iahb_12.
						0x9C
						
							
								sf2_if_read_dly_src
								12
								12
							
							
								sf2_if_read_dly_en
								11
								11
							
							
								sf2_if_read_dly_n
								8
								10
							
							
								sf3_clk_out_inv_sel
								5
								5
							
							
								sf2_clk_out_inv_sel
								4
								4
							
							
								sf2_clk_sf_rx_inv_src
								3
								3
							
							
								sf2_clk_sf_rx_inv_sel
								2
								2
							
						
					
					
						sf_ctrl_prot_en_rd
						sf_ctrl_prot_en_rd.
						0x100
						
							
								sf_dbg_dis
								31
								31
							
							
								sf_if_0_trig_wr_lock
								30
								30
							
							
								sf_ctrl_id1_en_rd
								2
								2
							
							
								sf_ctrl_id0_en_rd
								1
								1
							
							
								sf_ctrl_prot_en_rd
								0
								0
							
						
					
					
						sf_ctrl_prot_en
						sf_ctrl_prot_en.
						0x104
						
							
								sf_ctrl_id1_en
								2
								2
							
							
								sf_ctrl_id0_en
								1
								1
							
							
								sf_ctrl_prot_en
								0
								0
							
						
					
					
						sf_aes_key_r0_0
						sf_aes_key_r0_0.
						0x200
						
							
								sf_aes_key_r0_0
								0
								31
							
						
					
					
						sf_aes_key_r0_1
						sf_aes_key_r0_1.
						0x204
						
							
								sf_aes_key_r0_1
								0
								31
							
						
					
					
						sf_aes_key_r0_2
						sf_aes_key_r0_2.
						0x208
						
							
								sf_aes_key_r0_2
								0
								31
							
						
					
					
						sf_aes_key_r0_3
						sf_aes_key_r0_3.
						0x20C
						
							
								sf_aes_key_r0_3
								0
								31
							
						
					
					
						sf_aes_key_r0_4
						sf_aes_key_r0_4.
						0x210
						
							
								sf_aes_key_r0_4
								0
								31
							
						
					
					
						sf_aes_key_r0_5
						sf_aes_key_r0_5.
						0x214
						
							
								sf_aes_key_r0_5
								0
								31
							
						
					
					
						sf_aes_key_r0_6
						sf_aes_key_r0_6.
						0x218
						
							
								sf_aes_key_r0_6
								0
								31
							
						
					
					
						sf_aes_key_r0_7
						sf_aes_key_r0_7.
						0x21C
						
							
								sf_aes_key_r0_7
								0
								31
							
						
					
					
						sf_aes_iv_r0_w0
						sf_aes_iv_r0_w0.
						0x220
						
							
								sf_aes_iv_r0_w0
								0
								31
							
						
					
					
						sf_aes_iv_r0_w1
						sf_aes_iv_r0_w1.
						0x224
						
							
								sf_aes_iv_r0_w1
								0
								31
							
						
					
					
						sf_aes_iv_r0_w2
						sf_aes_iv_r0_w2.
						0x228
						
							
								sf_aes_iv_r0_w2
								0
								31
							
						
					
					
						sf_aes_iv_r0_w3
						sf_aes_iv_r0_w3.
						0x22C
						
							
								sf_aes_iv_r0_w3
								0
								31
							
						
					
					
						sf_aes_cfg_r0
						sf_aes_cfg_r0.
						0x230
						
							
								sf_aes_region_r0_lock
								31
								31
							
							
								sf_aes_region_r0_en
								30
								30
							
							
								sf_aes_region_r0_hw_key_en
								29
								29
							
							
								sf_aes_region_r0_start
								14
								27
							
							
								sf_aes_region_r0_end
								0
								13
							
						
					
					
						sf_aes_key_r1_0
						sf_aes_key_r1_0.
						0x300
						
							
								sf_aes_key_r1_0
								0
								31
							
						
					
					
						sf_aes_key_r1_1
						sf_aes_key_r1_1.
						0x304
						
							
								sf_aes_key_r1_1
								0
								31
							
						
					
					
						sf_aes_key_r1_2
						sf_aes_key_r1_2.
						0x308
						
							
								sf_aes_key_r1_2
								0
								31
							
						
					
					
						sf_aes_key_r1_3
						sf_aes_key_r1_3.
						0x30C
						
							
								sf_aes_key_r1_3
								0
								31
							
						
					
					
						sf_aes_key_r1_4
						sf_aes_key_r1_4.
						0x310
						
							
								sf_aes_key_r1_4
								0
								31
							
						
					
					
						sf_aes_key_r1_5
						sf_aes_key_r1_5.
						0x314
						
							
								sf_aes_key_r1_5
								0
								31
							
						
					
					
						sf_aes_key_r1_6
						sf_aes_key_r1_6.
						0x318
						
							
								sf_aes_key_r1_6
								0
								31
							
						
					
					
						sf_aes_key_r1_7
						sf_aes_key_r1_7.
						0x31C
						
							
								sf_aes_key_r1_7
								0
								31
							
						
					
					
						sf_aes_iv_r1_w0
						sf_aes_iv_r1_w0.
						0x320
						
							
								sf_aes_iv_r1_w0
								0
								31
							
						
					
					
						sf_aes_iv_r1_w1
						sf_aes_iv_r1_w1.
						0x324
						
							
								sf_aes_iv_r1_w1
								0
								31
							
						
					
					
						sf_aes_iv_r1_w2
						sf_aes_iv_r1_w2.
						0x328
						
							
								sf_aes_iv_r1_w2
								0
								31
							
						
					
					
						sf_aes_iv_r1_w3
						sf_aes_iv_r1_w3.
						0x32C
						
							
								sf_aes_iv_r1_w3
								0
								31
							
						
					
					
						sf_aes_r1
						sf_aes_r1.
						0x330
						
							
								sf_aes_r1_lock
								31
								31
							
							
								sf_aes_r1_en
								30
								30
							
							
								sf_aes_r1_hw_key_en
								29
								29
							
							
								sf_aes_r1_start
								14
								27
							
							
								sf_aes_r1_end
								0
								13
							
						
					
					
						sf_aes_key_r2_0
						sf_aes_key_r2_0.
						0x400
						
							
								sf_aes_key_r2_0
								0
								31
							
						
					
					
						sf_aes_key_r2_1
						sf_aes_key_r2_1.
						0x404
						
							
								sf_aes_key_r2_1
								0
								31
							
						
					
					
						sf_aes_key_r2_2
						sf_aes_key_r2_2.
						0x408
						
							
								sf_aes_key_r2_2
								0
								31
							
						
					
					
						sf_aes_key_r2_3
						sf_aes_key_r2_3.
						0x40C
						
							
								sf_aes_key_r2_3
								0
								31
							
						
					
					
						sf_aes_key_r2_4
						sf_aes_key_r2_4.
						0x410
						
							
								sf_aes_key_r2_4
								0
								31
							
						
					
					
						sf_aes_key_r2_5
						sf_aes_key_r2_5.
						0x414
						
							
								sf_aes_key_r2_5
								0
								31
							
						
					
					
						sf_aes_key_r2_6
						sf_aes_key_r2_6.
						0x418
						
							
								sf_aes_key_r2_6
								0
								31
							
						
					
					
						sf_aes_key_r2_7
						sf_aes_key_r2_7.
						0x41C
						
							
								sf_aes_key_r2_7
								0
								31
							
						
					
					
						sf_aes_iv_r2_w0
						sf_aes_iv_r2_w0.
						0x420
						
							
								sf_aes_iv_r2_w0
								0
								31
							
						
					
					
						sf_aes_iv_r2_w1
						sf_aes_iv_r2_w1.
						0x424
						
							
								sf_aes_iv_r2_w1
								0
								31
							
						
					
					
						sf_aes_iv_r2_w2
						sf_aes_iv_r2_w2.
						0x428
						
							
								sf_aes_iv_r2_w2
								0
								31
							
						
					
					
						sf_aes_iv_r2_w3
						sf_aes_iv_r2_w3.
						0x42C
						
							
								sf_aes_iv_r2_w3
								0
								31
							
						
					
					
						sf_aes_r2
						sf_aes_r2.
						0x430
						
							
								sf_aes_r2_lock
								31
								31
							
							
								sf_aes_r2_en
								30
								30
							
							
								sf_aes_r2_hw_key_en
								29
								29
							
							
								sf_aes_r2_start
								14
								27
							
							
								sf_aes_r2_end
								0
								13
							
						
					
					
						sf_id0_offset
						sf_id0_offset.
						0x434
						
							
								sf_id0_offset
								0
								23
							
						
					
					
						sf_id1_offset
						sf_id1_offset.
						0x438
						
							
								sf_id1_offset
								0
								23
							
						
					
					
						sf_bk2_id0_offset
						sf_bk2_id0_offset.
						0x43C
						
							
								sf_bk2_id0_offset
								0
								23
							
						
					
					
						sf_bk2_id1_offset
						sf_bk2_id1_offset.
						0x440
						
							
								sf_bk2_id1_offset
								0
								23
							
						
					
				
			
			
				dma
				dma.
				0x40007000
				dma
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						DMA_IntStatus
						DMA_IntStatus.
						0x0
						
							
								IntStatus
								0
								7
							
						
					
					
						DMA_IntTCStatus
						DMA_IntTCStatus.
						0x4
						
							
								IntTCStatus
								0
								7
							
						
					
					
						DMA_IntTCClear
						DMA_IntTCClear.
						0x8
						
							
								IntTCClear
								0
								7
							
						
					
					
						DMA_IntErrorStatus
						DMA_IntErrorStatus.
						0xC
						
							
								IntErrorStatus
								0
								7
							
						
					
					
						DMA_IntErrClr
						DMA_IntErrClr.
						0x10
						
							
								IntErrClr
								0
								7
							
						
					
					
						DMA_RawIntTCStatus
						DMA_RawIntTCStatus.
						0x14
						
							
								RawIntTCStatus
								0
								7
							
						
					
					
						DMA_RawIntErrorStatus
						DMA_RawIntErrorStatus.
						0x18
						
							
								RawIntErrorStatus
								0
								7
							
						
					
					
						DMA_EnbldChns
						DMA_EnbldChns.
						0x1C
						
							
								EnabledChannels
								0
								7
							
						
					
					
						DMA_SoftBReq
						DMA_SoftBReq.
						0x20
						
							
								SoftBReq
								0
								31
							
						
					
					
						DMA_SoftSReq
						DMA_SoftSReq.
						0x24
						
							
								SoftSReq
								0
								31
							
						
					
					
						DMA_SoftLBReq
						DMA_SoftLBReq.
						0x28
						
							
								SoftLBReq
								0
								31
							
						
					
					
						DMA_SoftLSReq
						DMA_SoftLSReq.
						0x2C
						
							
								SoftLSReq
								0
								31
							
						
					
					
						DMA_Top_Config
						DMA_Top_Config.
						0x30
						
							
								M
								1
								1
							
							
								E
								0
								0
							
						
					
					
						DMA_Sync
						DMA_Sync.
						0x34
						
							
								DMA_Sync
								0
								31
							
						
					
					
						DMA_C0SrcAddr
						DMA_C0SrcAddr.
						0x100
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C0DstAddr
						DMA_C0DstAddr.
						0x104
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C0LLI
						DMA_C0LLI.
						0x108
						
							
								LLI
								0
								31
							
						
					
					
						DMA_C0Control
						DMA_C0Control.
						0x10C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								SLargerD
								25
								25
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								22
							
							
								SWidth
								18
								19
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C0Config
						DMA_C0Config.
						0x110
						
							
								LLICounter
								20
								29
							
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C1SrcAddr
						DMA_C1SrcAddr.
						0x200
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C1DstAddr
						DMA_C1DstAddr.
						0x204
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C1LLI
						DMA_C1LLI.
						0x208
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C1Control
						DMA_C1Control.
						0x20C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C1Config
						DMA_C1Config.
						0x210
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C2SrcAddr
						DMA_C2SrcAddr.
						0x300
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C2DstAddr
						DMA_C2DstAddr.
						0x304
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C2LLI
						DMA_C2LLI.
						0x308
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C2Control
						DMA_C2Control.
						0x30C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C2Config
						DMA_C2Config.
						0x310
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C3SrcAddr
						DMA_C3SrcAddr.
						0x400
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C3DstAddr
						DMA_C3DstAddr.
						0x404
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C3LLI
						DMA_C3LLI.
						0x408
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C3Control
						DMA_C3Control.
						0x40C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C3Config
						DMA_C3Config.
						0x410
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C4SrcAddr
						DMA_C4SrcAddr.
						0x500
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C4DstAddr
						DMA_C4DstAddr.
						0x504
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C4LLI
						DMA_C4LLI.
						0x508
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C4Control
						DMA_C4Control.
						0x50C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C4Config
						DMA_C4Config.
						0x510
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C5SrcAddr
						DMA_C5SrcAddr.
						0x600
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C5DstAddr
						DMA_C5DstAddr.
						0x604
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C5LLI
						DMA_C5LLI.
						0x608
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C5Control
						DMA_C5Control.
						0x60C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C5Config
						DMA_C5Config.
						0x610
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C6SrcAddr
						DMA_C6SrcAddr.
						0x700
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C6DstAddr
						DMA_C6DstAddr.
						0x704
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C6LLI
						DMA_C6LLI.
						0x708
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C6Control
						DMA_C6Control.
						0x70C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C6Config
						DMA_C6Config.
						0x710
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
					
						DMA_C7SrcAddr
						DMA_C7SrcAddr.
						0x800
						
							
								SrcAddr
								0
								31
							
						
					
					
						DMA_C7DstAddr
						DMA_C7DstAddr.
						0x804
						
							
								DstAddr
								0
								31
							
						
					
					
						DMA_C7LLI
						DMA_C7LLI.
						0x808
						
							
								LLI
								2
								31
							
						
					
					
						DMA_C7Control
						DMA_C7Control.
						0x80C
						
							
								I
								31
								31
							
							
								Prot
								28
								30
							
							
								DI
								27
								27
							
							
								SI
								26
								26
							
							
								fix_cnt
								23
								24
							
							
								DWidth
								21
								23
							
							
								SWidth
								18
								20
							
							
								dst_add_mode
								17
								17
							
							
								DBSize
								15
								16
							
							
								dst_min_mode
								14
								14
							
							
								SBSize
								12
								13
							
							
								TransferSize
								0
								11
							
						
					
					
						DMA_C7Config
						DMA_C7Config.
						0x810
						
							
								H
								18
								18
							
							
								A
								17
								17
							
							
								L
								16
								16
							
							
								ITC
								15
								15
							
							
								IE
								14
								14
							
							
								FlowCntrl
								11
								13
							
							
								DstPeripheral
								6
								10
							
							
								SrcPeripheral
								1
								5
							
							
								E
								0
								0
							
						
					
				
			
			
				emac
				emac.
				0x4000D000
				emac
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						MODE
						MODE.
						0x0
						
							
								rsvd_23_18
								18
								23
							
							
								RMII_EN
								17
								17
							
							
								RECSMALL
								16
								16
							
							
								PAD
								15
								15
							
							
								HUGEN
								14
								14
							
							
								CRCEN
								13
								13
							
							
								rsvd_12_11
								11
								12
							
							
								FULLD
								10
								10
							
							
								rsvd_9_7
								7
								9
							
							
								IFG
								6
								6
							
							
								PRO
								5
								5
							
							
								rsvd_4
								4
								4
							
							
								BRO
								3
								3
							
							
								NOPRE
								2
								2
							
							
								TXEN
								1
								1
							
							
								RXEN
								0
								0
							
						
					
					
						INT_SOURCE
						INT_SOURCE.
						0x4
						
							
								RXC
								6
								6
							
							
								TXC
								5
								5
							
							
								BUSY
								4
								4
							
							
								RXE
								3
								3
							
							
								RXB
								2
								2
							
							
								TXE
								1
								1
							
							
								TXB
								0
								0
							
						
					
					
						INT_MASK
						INT_MASK.
						0x8
						
							
								RXC_M
								6
								6
							
							
								TXC_M
								5
								5
							
							
								BUSY_M
								4
								4
							
							
								RXE_M
								3
								3
							
							
								RXB_M
								2
								2
							
							
								TXE_M
								1
								1
							
							
								TXB_M
								0
								0
							
						
					
					
						IPGT
						IPGT.
						0xC
						
							
								IPGT
								0
								6
							
						
					
					
						PACKETLEN
						PACKETLEN.
						0x18
						
							
								MINFL
								16
								31
							
							
								MAXFL
								0
								15
							
						
					
					
						COLLCONFIG
						COLLCONFIG.
						0x1C
						
							
								MAXRET
								16
								19
							
							
								COLLVALID
								0
								5
							
						
					
					
						TX_BD_NUM
						TX_BD_NUM.
						0x20
						
							
								RXBDPTR
								24
								30
							
							
								TXBDPTR
								16
								22
							
							
								TXBDNUM
								0
								7
							
						
					
					
						MIIMODE
						MIIMODE.
						0x28
						
							
								MIINOPRE
								8
								8
							
							
								CLKDIV
								0
								7
							
						
					
					
						MIICOMMAND
						MIICOMMAND.
						0x2C
						
							
								WCTRLDATA
								2
								2
							
							
								RSTAT
								1
								1
							
							
								SCANSTAT
								0
								0
							
						
					
					
						MIIADDRESS
						MIIADDRESS.
						0x30
						
							
								RGAD
								8
								12
							
							
								FIAD
								0
								4
							
						
					
					
						MIITX_DATA
						MIITX_DATA.
						0x34
						
							
								CTRLDATA
								0
								15
							
						
					
					
						MIIRX_DATA
						MIIRX_DATA.
						0x38
						
							
								PRSD
								0
								15
							
						
					
					
						MIISTATUS
						MIISTATUS.
						0x3C
						
							
								MIIM_BUSY
								1
								1
							
							
								MIIM_LINKFAIL
								0
								0
							
						
					
					
						MAC_ADDR0
						MAC_ADDR0.
						0x40
						
							
								MAC_B2
								24
								31
							
							
								MAC_B3
								16
								23
							
							
								MAC_B4
								8
								15
							
							
								MAC_B5
								0
								7
							
						
					
					
						MAC_ADDR1
						MAC_ADDR1.
						0x44
						
							
								MAC_B0
								8
								15
							
							
								MAC_B1
								0
								7
							
						
					
					
						HASH0_ADDR
						HASH0_ADDR.
						0x48
						
							
								HASH0
								0
								31
							
						
					
					
						HASH1_ADDR
						HASH1_ADDR.
						0x4C
						
							
								HASH1
								0
								31
							
						
					
					
						TXCTRL
						TXCTRL.
						0x50
						
							
								TXPAUSERQ
								16
								16
							
							
								TXPAUSETV
								0
								15
							
						
					
				
			
			
				usb
				usb.
				0x4000D800
				usb
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						usb_config
						usb_config.
						0x0
						
							
								sts_usb_ep0_sw_rdy
								28
								28
							
							
								cr_usb_ep0_sw_rdy
								27
								27
							
							
								cr_usb_ep0_sw_nack_out
								26
								26
							
							
								cr_usb_ep0_sw_nack_in
								25
								25
							
							
								cr_usb_ep0_sw_stall
								24
								24
							
							
								cr_usb_ep0_sw_size
								16
								23
							
							
								cr_usb_ep0_sw_addr
								9
								15
							
							
								cr_usb_ep0_sw_ctrl
								8
								8
							
							
								cr_usb_rom_dct_en
								4
								4
							
							
								cr_usb_en
								0
								0
							
						
					
					
						usb_lpm_config
						usb_lpm_config.
						0x4
						
							
								sts_lpm
								31
								31
							
							
								sts_lpm_attr
								20
								30
							
							
								cr_lpm_resp
								2
								3
							
							
								cr_lpm_resp_upd
								1
								1
							
							
								cr_lpm_en
								0
								0
							
						
					
					
						usb_resume_config
						usb_resume_config.
						0x8
						
							
								cr_res_force
								31
								31
							
							
								cr_res_trig
								12
								12
							
							
								cr_res_width
								0
								10
							
						
					
					
						usb_setup_data_0
						usb_setup_data_0.
						0x10
						
							
								sts_setup_data_b3
								24
								31
							
							
								sts_setup_data_b2
								16
								23
							
							
								sts_setup_data_b1
								8
								15
							
							
								sts_setup_data_b0
								0
								7
							
						
					
					
						usb_setup_data_1
						usb_setup_data_1.
						0x14
						
							
								sts_setup_data_b7
								24
								31
							
							
								sts_setup_data_b6
								16
								23
							
							
								sts_setup_data_b5
								8
								15
							
							
								sts_setup_data_b4
								0
								7
							
						
					
					
						usb_frame_no
						usb_frame_no.
						0x18
						
							
								sts_ep_no
								16
								19
							
							
								sts_pid
								12
								15
							
							
								sts_frame_no
								0
								10
							
						
					
					
						usb_error
						usb_error.
						0x1C
						
							
								crc16_err
								6
								6
							
							
								crc5_err
								5
								5
							
							
								pid_cks_err
								4
								4
							
							
								pid_seq_err
								3
								3
							
							
								ivld_ep_err
								2
								2
							
							
								xfer_to_err
								1
								1
							
							
								utmi_rx_err
								0
								0
							
						
					
					
						usb_int_en
						USB interrupt enable
						0x20
						
							
								cr_usb_err_en
								31
								31
							
							
								cr_sof_3ms_en
								30
								30
							
							
								cr_lpm_pkt_en
								29
								29
							
							
								cr_lpm_wkup_en
								28
								28
							
							
								rsvd_27_24
								24
								27
							
							
								cr_ep7_done_en
								23
								23
							
							
								cr_ep7_cmd_en
								22
								22
							
							
								cr_ep6_done_en
								21
								21
							
							
								cr_ep6_cmd_en
								20
								20
							
							
								cr_ep5_done_en
								19
								19
							
							
								cr_ep5_cmd_en
								18
								18
							
							
								cr_ep4_done_en
								17
								17
							
							
								cr_ep4_cmd_en
								16
								16
							
							
								cr_ep3_done_en
								15
								15
							
							
								cr_ep3_cmd_en
								14
								14
							
							
								cr_ep2_done_en
								13
								13
							
							
								cr_ep2_cmd_en
								12
								12
							
							
								cr_ep1_done_en
								11
								11
							
							
								cr_ep1_cmd_en
								10
								10
							
							
								cr_ep0_out_done_en
								9
								9
							
							
								cr_ep0_out_cmd_en
								8
								8
							
							
								cr_ep0_in_done_en
								7
								7
							
							
								cr_ep0_in_cmd_en
								6
								6
							
							
								cr_ep0_setup_done_en
								5
								5
							
							
								cr_ep0_setup_cmd_en
								4
								4
							
							
								cr_get_dct_cmd_en
								3
								3
							
							
								cr_vbus_tgl_en
								2
								2
							
							
								cr_usb_reset_en
								1
								1
							
							
								cr_sof_en
								0
								0
							
						
					
					
						usb_int_sts
						USB interrupt status
						0x24
						
							
								usb_err_int
								31
								31
							
							
								sof_3ms_int
								30
								30
							
							
								lpm_pkt_int
								29
								29
							
							
								lpm_wkup_int
								28
								28
							
							
								rsvd_27_24
								24
								27
							
							
								ep7_done_int
								23
								23
							
							
								ep7_cmd_int
								22
								22
							
							
								ep6_done_int
								21
								21
							
							
								ep6_cmd_int
								20
								20
							
							
								ep5_done_int
								19
								19
							
							
								ep5_cmd_int
								18
								18
							
							
								ep4_done_int
								17
								17
							
							
								ep4_cmd_int
								16
								16
							
							
								ep3_done_int
								15
								15
							
							
								ep3_cmd_int
								14
								14
							
							
								ep2_done_int
								13
								13
							
							
								ep2_cmd_int
								12
								12
							
							
								ep1_done_int
								11
								11
							
							
								ep1_cmd_int
								10
								10
							
							
								ep0_out_done_int
								9
								9
							
							
								ep0_out_cmd_int
								8
								8
							
							
								ep0_in_done_int
								7
								7
							
							
								ep0_in_cmd_int
								6
								6
							
							
								ep0_setup_done_int
								5
								5
							
							
								ep0_setup_cmd_int
								4
								4
							
							
								get_dct_cmd_int
								3
								3
							
							
								vbus_tgl_int
								2
								2
							
							
								usb_reset_int
								1
								1
							
							
								sof_int
								0
								0
							
						
					
					
						usb_int_mask
						USB interrupt mask
						0x28
						
							
								cr_usb_err_mask
								31
								31
							
							
								cr_sof_3ms_mask
								30
								30
							
							
								cr_lpm_pkt_mask
								29
								29
							
							
								cr_lpm_wkup_mask
								28
								28
							
							
								rsvd_27_24
								24
								27
							
							
								cr_ep7_done_mask
								23
								23
							
							
								cr_ep7_cmd_mask
								22
								22
							
							
								cr_ep6_done_mask
								21
								21
							
							
								cr_ep6_cmd_mask
								20
								20
							
							
								cr_ep5_done_mask
								19
								19
							
							
								cr_ep5_cmd_mask
								18
								18
							
							
								cr_ep4_done_mask
								17
								17
							
							
								cr_ep4_cmd_mask
								16
								16
							
							
								cr_ep3_done_mask
								15
								15
							
							
								cr_ep3_cmd_mask
								14
								14
							
							
								cr_ep2_done_mask
								13
								13
							
							
								cr_ep2_cmd_mask
								12
								12
							
							
								cr_ep1_done_mask
								11
								11
							
							
								cr_ep1_cmd_mask
								10
								10
							
							
								cr_ep0_out_done_mask
								9
								9
							
							
								cr_ep0_out_cmd_mask
								8
								8
							
							
								cr_ep0_in_done_mask
								7
								7
							
							
								cr_ep0_in_cmd_mask
								6
								6
							
							
								cr_ep0_setup_done_mask
								5
								5
							
							
								cr_ep0_setup_cmd_mask
								4
								4
							
							
								cr_get_dct_cmd_mask
								3
								3
							
							
								cr_vbus_tgl_mask
								2
								2
							
							
								cr_usb_reset_mask
								1
								1
							
							
								cr_sof_mask
								0
								0
							
						
					
					
						usb_int_clear
						USB interrupt clear
						0x2C
						
							
								cr_usb_err_clr
								31
								31
							
							
								cr_sof_3ms_clr
								30
								30
							
							
								cr_lpm_pkt_clr
								29
								29
							
							
								cr_lpm_wkup_clr
								28
								28
							
							
								rsvd_27_24
								24
								27
							
							
								cr_ep7_done_clr
								23
								23
							
							
								cr_ep7_cmd_clr
								22
								22
							
							
								cr_ep6_done_clr
								21
								21
							
							
								cr_ep6_cmd_clr
								20
								20
							
							
								cr_ep5_done_clr
								19
								19
							
							
								cr_ep5_cmd_clr
								18
								18
							
							
								cr_ep4_done_clr
								17
								17
							
							
								cr_ep4_cmd_clr
								16
								16
							
							
								cr_ep3_done_clr
								15
								15
							
							
								cr_ep3_cmd_clr
								14
								14
							
							
								cr_ep2_done_clr
								13
								13
							
							
								cr_ep2_cmd_clr
								12
								12
							
							
								cr_ep1_done_clr
								11
								11
							
							
								cr_ep1_cmd_clr
								10
								10
							
							
								cr_ep0_out_done_clr
								9
								9
							
							
								cr_ep0_out_cmd_clr
								8
								8
							
							
								cr_ep0_in_done_clr
								7
								7
							
							
								cr_ep0_in_cmd_clr
								6
								6
							
							
								cr_ep0_setup_done_clr
								5
								5
							
							
								cr_ep0_setup_cmd_clr
								4
								4
							
							
								cr_get_dct_cmd_clr
								3
								3
							
							
								cr_vbus_tgl_clr
								2
								2
							
							
								cr_usb_reset_clr
								1
								1
							
							
								cr_sof_clr
								0
								0
							
						
					
					
						ep1_config
						ep1_config.
						0x40
						
							
								sts_ep1_rdy
								19
								19
							
							
								cr_ep1_rdy
								18
								18
							
							
								cr_ep1_nack
								17
								17
							
							
								cr_ep1_stall
								16
								16
							
							
								cr_ep1_type
								13
								15
							
							
								cr_ep1_dir
								11
								12
							
							
								cr_ep1_size
								0
								10
							
						
					
					
						ep2_config
						ep2_config.
						0x44
						
							
								sts_ep2_rdy
								19
								19
							
							
								cr_ep2_rdy
								18
								18
							
							
								cr_ep2_nack
								17
								17
							
							
								cr_ep2_stall
								16
								16
							
							
								cr_ep2_type
								13
								15
							
							
								cr_ep2_dir
								11
								12
							
							
								cr_ep2_size
								0
								10
							
						
					
					
						ep3_config
						ep3_config.
						0x48
						
							
								sts_ep3_rdy
								19
								19
							
							
								cr_ep3_rdy
								18
								18
							
							
								cr_ep3_nack
								17
								17
							
							
								cr_ep3_stall
								16
								16
							
							
								cr_ep3_type
								13
								15
							
							
								cr_ep3_dir
								11
								12
							
							
								cr_ep3_size
								0
								10
							
						
					
					
						ep4_config
						ep4_config.
						0x4C
						
							
								sts_ep4_rdy
								19
								19
							
							
								cr_ep4_rdy
								18
								18
							
							
								cr_ep4_nack
								17
								17
							
							
								cr_ep4_stall
								16
								16
							
							
								cr_ep4_type
								13
								15
							
							
								cr_ep4_dir
								11
								12
							
							
								cr_ep4_size
								0
								10
							
						
					
					
						ep5_config
						ep5_config.
						0x50
						
							
								sts_ep5_rdy
								19
								19
							
							
								cr_ep5_rdy
								18
								18
							
							
								cr_ep5_nack
								17
								17
							
							
								cr_ep5_stall
								16
								16
							
							
								cr_ep5_type
								13
								15
							
							
								cr_ep5_dir
								11
								12
							
							
								cr_ep5_size
								0
								10
							
						
					
					
						ep6_config
						ep6_config.
						0x54
						
							
								sts_ep6_rdy
								19
								19
							
							
								cr_ep6_rdy
								18
								18
							
							
								cr_ep6_nack
								17
								17
							
							
								cr_ep6_stall
								16
								16
							
							
								cr_ep6_type
								13
								15
							
							
								cr_ep6_dir
								11
								12
							
							
								cr_ep6_size
								0
								10
							
						
					
					
						ep7_config
						ep7_config.
						0x58
						
							
								sts_ep7_rdy
								19
								19
							
							
								cr_ep7_rdy
								18
								18
							
							
								cr_ep7_nack
								17
								17
							
							
								cr_ep7_stall
								16
								16
							
							
								cr_ep7_type
								13
								15
							
							
								cr_ep7_dir
								11
								12
							
							
								cr_ep7_size
								0
								10
							
						
					
					
						ep0_fifo_config
						ep0_fifo_config.
						0x100
						
							
								ep0_rx_fifo_underflow
								7
								7
							
							
								ep0_rx_fifo_overflow
								6
								6
							
							
								ep0_tx_fifo_underflow
								5
								5
							
							
								ep0_tx_fifo_overflow
								4
								4
							
							
								ep0_rx_fifo_clr
								3
								3
							
							
								ep0_tx_fifo_clr
								2
								2
							
							
								ep0_dma_rx_en
								1
								1
							
							
								ep0_dma_tx_en
								0
								0
							
						
					
					
						ep0_fifo_status
						ep0_fifo_status.
						0x104
						
							
								ep0_rx_fifo_full
								31
								31
							
							
								ep0_rx_fifo_empty
								30
								30
							
							
								ep0_rx_fifo_cnt
								16
								22
							
							
								ep0_tx_fifo_full
								15
								15
							
							
								ep0_tx_fifo_empty
								14
								14
							
							
								ep0_tx_fifo_cnt
								0
								6
							
						
					
					
						ep0_tx_fifo_wdata
						ep0_tx_fifo_wdata.
						0x108
						
							
								ep0_tx_fifo_wdata
								0
								7
							
						
					
					
						ep0_rx_fifo_rdata
						ep0_rx_fifo_rdata.
						0x10C
						
							
								ep0_rx_fifo_rdata
								0
								7
							
						
					
					
						ep1_fifo_config
						ep1_fifo_config.
						0x110
						
							
								ep1_rx_fifo_underflow
								7
								7
							
							
								ep1_rx_fifo_overflow
								6
								6
							
							
								ep1_tx_fifo_underflow
								5
								5
							
							
								ep1_tx_fifo_overflow
								4
								4
							
							
								ep1_rx_fifo_clr
								3
								3
							
							
								ep1_tx_fifo_clr
								2
								2
							
							
								ep1_dma_rx_en
								1
								1
							
							
								ep1_dma_tx_en
								0
								0
							
						
					
					
						ep1_fifo_status
						ep1_fifo_status.
						0x114
						
							
								ep1_rx_fifo_full
								31
								31
							
							
								ep1_rx_fifo_empty
								30
								30
							
							
								ep1_rx_fifo_cnt
								16
								22
							
							
								ep1_tx_fifo_full
								15
								15
							
							
								ep1_tx_fifo_empty
								14
								14
							
							
								ep1_tx_fifo_cnt
								0
								6
							
						
					
					
						ep1_tx_fifo_wdata
						ep1_tx_fifo_wdata.
						0x118
						
							
								ep1_tx_fifo_wdata
								0
								7
							
						
					
					
						ep1_rx_fifo_rdata
						ep1_rx_fifo_rdata.
						0x11C
						
							
								ep1_rx_fifo_rdata
								0
								7
							
						
					
					
						ep2_fifo_config
						ep2_fifo_config.
						0x120
						
							
								ep2_rx_fifo_underflow
								7
								7
							
							
								ep2_rx_fifo_overflow
								6
								6
							
							
								ep2_tx_fifo_underflow
								5
								5
							
							
								ep2_tx_fifo_overflow
								4
								4
							
							
								ep2_rx_fifo_clr
								3
								3
							
							
								ep2_tx_fifo_clr
								2
								2
							
							
								ep2_dma_rx_en
								1
								1
							
							
								ep2_dma_tx_en
								0
								0
							
						
					
					
						ep2_fifo_status
						ep2_fifo_status.
						0x124
						
							
								ep2_rx_fifo_full
								31
								31
							
							
								ep2_rx_fifo_empty
								30
								30
							
							
								ep2_rx_fifo_cnt
								16
								22
							
							
								ep2_tx_fifo_full
								15
								15
							
							
								ep2_tx_fifo_empty
								14
								14
							
							
								ep2_tx_fifo_cnt
								0
								6
							
						
					
					
						ep2_tx_fifo_wdata
						ep2_tx_fifo_wdata.
						0x128
						
							
								ep2_tx_fifo_wdata
								0
								7
							
						
					
					
						ep2_rx_fifo_rdata
						ep2_rx_fifo_rdata.
						0x12C
						
							
								ep2_rx_fifo_rdata
								0
								7
							
						
					
					
						ep3_fifo_config
						ep3_fifo_config.
						0x130
						
							
								ep3_rx_fifo_underflow
								7
								7
							
							
								ep3_rx_fifo_overflow
								6
								6
							
							
								ep3_tx_fifo_underflow
								5
								5
							
							
								ep3_tx_fifo_overflow
								4
								4
							
							
								ep3_rx_fifo_clr
								3
								3
							
							
								ep3_tx_fifo_clr
								2
								2
							
							
								ep3_dma_rx_en
								1
								1
							
							
								ep3_dma_tx_en
								0
								0
							
						
					
					
						ep3_fifo_status
						ep3_fifo_status.
						0x134
						
							
								ep3_rx_fifo_full
								31
								31
							
							
								ep3_rx_fifo_empty
								30
								30
							
							
								ep3_rx_fifo_cnt
								16
								22
							
							
								ep3_tx_fifo_full
								15
								15
							
							
								ep3_tx_fifo_empty
								14
								14
							
							
								ep3_tx_fifo_cnt
								0
								6
							
						
					
					
						ep3_tx_fifo_wdata
						ep3_tx_fifo_wdata.
						0x138
						
							
								ep3_tx_fifo_wdata
								0
								7
							
						
					
					
						ep3_rx_fifo_rdata
						ep3_rx_fifo_rdata.
						0x13C
						
							
								ep3_rx_fifo_rdata
								0
								7
							
						
					
					
						ep4_fifo_config
						ep4_fifo_config.
						0x140
						
							
								ep4_rx_fifo_underflow
								7
								7
							
							
								ep4_rx_fifo_overflow
								6
								6
							
							
								ep4_tx_fifo_underflow
								5
								5
							
							
								ep4_tx_fifo_overflow
								4
								4
							
							
								ep4_rx_fifo_clr
								3
								3
							
							
								ep4_tx_fifo_clr
								2
								2
							
							
								ep4_dma_rx_en
								1
								1
							
							
								ep4_dma_tx_en
								0
								0
							
						
					
					
						ep4_fifo_status
						ep4_fifo_status.
						0x144
						
							
								ep4_rx_fifo_full
								31
								31
							
							
								ep4_rx_fifo_empty
								30
								30
							
							
								ep4_rx_fifo_cnt
								16
								22
							
							
								ep4_tx_fifo_full
								15
								15
							
							
								ep4_tx_fifo_empty
								14
								14
							
							
								ep4_tx_fifo_cnt
								0
								6
							
						
					
					
						ep4_tx_fifo_wdata
						ep4_tx_fifo_wdata.
						0x148
						
							
								ep4_tx_fifo_wdata
								0
								7
							
						
					
					
						ep4_rx_fifo_rdata
						ep4_rx_fifo_rdata.
						0x14C
						
							
								ep4_rx_fifo_rdata
								0
								7
							
						
					
					
						ep5_fifo_config
						ep5_fifo_config.
						0x150
						
							
								ep5_rx_fifo_underflow
								7
								7
							
							
								ep5_rx_fifo_overflow
								6
								6
							
							
								ep5_tx_fifo_underflow
								5
								5
							
							
								ep5_tx_fifo_overflow
								4
								4
							
							
								ep5_rx_fifo_clr
								3
								3
							
							
								ep5_tx_fifo_clr
								2
								2
							
							
								ep5_dma_rx_en
								1
								1
							
							
								ep5_dma_tx_en
								0
								0
							
						
					
					
						ep5_fifo_status
						ep5_fifo_status.
						0x154
						
							
								ep5_rx_fifo_full
								31
								31
							
							
								ep5_rx_fifo_empty
								30
								30
							
							
								ep5_rx_fifo_cnt
								16
								22
							
							
								ep5_tx_fifo_full
								15
								15
							
							
								ep5_tx_fifo_empty
								14
								14
							
							
								ep5_tx_fifo_cnt
								0
								6
							
						
					
					
						ep5_tx_fifo_wdata
						ep5_tx_fifo_wdata.
						0x158
						
							
								ep5_tx_fifo_wdata
								0
								7
							
						
					
					
						ep5_rx_fifo_rdata
						ep5_rx_fifo_rdata.
						0x15C
						
							
								ep5_rx_fifo_rdata
								0
								7
							
						
					
					
						ep6_fifo_config
						ep6_fifo_config.
						0x160
						
							
								ep6_rx_fifo_underflow
								7
								7
							
							
								ep6_rx_fifo_overflow
								6
								6
							
							
								ep6_tx_fifo_underflow
								5
								5
							
							
								ep6_tx_fifo_overflow
								4
								4
							
							
								ep6_rx_fifo_clr
								3
								3
							
							
								ep6_tx_fifo_clr
								2
								2
							
							
								ep6_dma_rx_en
								1
								1
							
							
								ep6_dma_tx_en
								0
								0
							
						
					
					
						ep6_fifo_status
						ep6_fifo_status.
						0x164
						
							
								ep6_rx_fifo_full
								31
								31
							
							
								ep6_rx_fifo_empty
								30
								30
							
							
								ep6_rx_fifo_cnt
								16
								22
							
							
								ep6_tx_fifo_full
								15
								15
							
							
								ep6_tx_fifo_empty
								14
								14
							
							
								ep6_tx_fifo_cnt
								0
								6
							
						
					
					
						ep6_tx_fifo_wdata
						ep6_tx_fifo_wdata.
						0x168
						
							
								ep6_tx_fifo_wdata
								0
								7
							
						
					
					
						ep6_rx_fifo_rdata
						ep6_rx_fifo_rdata.
						0x16C
						
							
								ep6_rx_fifo_rdata
								0
								7
							
						
					
					
						ep7_fifo_config
						ep7_fifo_config.
						0x170
						
							
								ep7_rx_fifo_underflow
								7
								7
							
							
								ep7_rx_fifo_overflow
								6
								6
							
							
								ep7_tx_fifo_underflow
								5
								5
							
							
								ep7_tx_fifo_overflow
								4
								4
							
							
								ep7_rx_fifo_clr
								3
								3
							
							
								ep7_tx_fifo_clr
								2
								2
							
							
								ep7_dma_rx_en
								1
								1
							
							
								ep7_dma_tx_en
								0
								0
							
						
					
					
						ep7_fifo_status
						ep7_fifo_status.
						0x174
						
							
								ep7_rx_fifo_full
								31
								31
							
							
								ep7_rx_fifo_empty
								30
								30
							
							
								ep7_rx_fifo_cnt
								16
								22
							
							
								ep7_tx_fifo_full
								15
								15
							
							
								ep7_tx_fifo_empty
								14
								14
							
							
								ep7_tx_fifo_cnt
								0
								6
							
						
					
					
						ep7_tx_fifo_wdata
						ep7_tx_fifo_wdata.
						0x178
						
							
								ep7_tx_fifo_wdata
								0
								7
							
						
					
					
						ep7_rx_fifo_rdata
						ep7_rx_fifo_rdata.
						0x17C
						
							
								ep7_rx_fifo_rdata
								0
								7
							
						
					
					
						rsvd_0
						rsvd_0.
						0x1F0
						
							
								rsvd_0
								0
								31
							
						
					
					
						rsvd_1
						rsvd_1.
						0x1F4
						
							
								rsvd_1
								0
								31
							
						
					
					
						xcvr_if_config
						xcvr_if_config.
						0x1FC
						
							
								sts_vbus_det
								31
								31
							
							
								cr_xcvr_om_rx_dn
								11
								11
							
							
								cr_xcvr_om_rx_dp
								10
								10
							
							
								cr_xcvr_om_rx_d
								9
								9
							
							
								cr_xcvr_om_rx_sel
								8
								8
							
							
								cr_xcvr_force_rx_dn
								7
								7
							
							
								cr_xcvr_force_rx_dp
								6
								6
							
							
								cr_xcvr_force_rx_d
								5
								5
							
							
								cr_xcvr_force_rx_en
								4
								4
							
							
								cr_xcvr_force_tx_dn
								3
								3
							
							
								cr_xcvr_force_tx_dp
								2
								2
							
							
								cr_xcvr_force_tx_oe
								1
								1
							
							
								cr_xcvr_force_tx_en
								0
								0
							
						
					
				
			
			
				pds
				pds.
				0x4000E000
				pds
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						PDS_CTL
						PDS_CTL.
						0x0
						
							
								cr_pds_ctrl_pll
								30
								31
							
							
								cr_pds_ctrl_rf
								28
								29
							
							
								cr_pds_ldo_vol
								24
								27
							
							
								cr_pds_force_ram_clk_en
								23
								23
							
							
								cr_pds_pd_ldo11
								22
								22
							
							
								cr_np_wfi_mask
								21
								21
							
							
								cr_pds_ram_lp_with_clk_en
								19
								19
							
							
								cr_pds_ldo_vsel_en
								18
								18
							
							
								cr_pds_rc32m_off_dis
								17
								17
							
							
								cr_pds_rst_soc_en
								16
								16
							
							
								cr_pds_soc_enb_force_on
								15
								15
							
							
								cr_pds_pd_xtal
								14
								14
							
							
								cr_pds_pwr_off
								13
								13
							
							
								cr_pds_wait_xtal_rdy
								12
								12
							
							
								cr_pds_iso_en
								11
								11
							
							
								cr_sw_pu_flash
								10
								10
							
							
								cr_pds_mem_stby
								9
								9
							
							
								cr_pds_gate_clk
								8
								8
							
							
								cr_pds_ctrl_pu_flash
								7
								7
							
							
								cr_pds_ctrl_gpio_ie_pu_pd
								6
								6
							
							
								cr_pds_pd_bg_sys
								5
								5
							
							
								cr_pds_pd_dcdc18
								4
								4
							
							
								cr_wifi_pds_save_state
								3
								3
							
							
								cr_xtal_force_off
								2
								2
							
							
								cr_sleep_forever
								1
								1
							
							
								pds_start_ps
								0
								0
							
						
					
					
						PDS_TIME1
						PDS_TIME1.
						0x4
						
							
								cr_sleep_duration
								0
								31
							
						
					
					
						PDS_INT
						PDS_INT.
						0xC
						
							
								ro_pds_wakeup_event
								24
								31
							
							
								cr_pds_wakeup_src_en
								16
								23
							
							
								cr_pds_int_clr
								15
								15
							
							
								cr_pds_pll_done_int_mask
								11
								11
							
							
								cr_pds_rf_done_int_mask
								10
								10
							
							
								cr_pds_wake_int_mask
								8
								8
							
							
								pds_clr_reset_event
								7
								7
							
							
								pds_reset_event
								4
								6
							
							
								ro_pds_pll_done_int
								3
								3
							
							
								ro_pds_rf_done_int
								2
								2
							
							
								ro_pds_wake_int
								0
								0
							
						
					
					
						PDS_CTL2
						PDS_CTL2.
						0x10
						
							
								cr_pds_force_usb_gate_clk
								19
								19
							
							
								cr_pds_force_bz_gate_clk
								18
								18
							
							
								cr_pds_force_np_gate_clk
								16
								16
							
							
								cr_pds_force_usb_mem_stby
								15
								15
							
							
								cr_pds_force_bz_mem_stby
								14
								14
							
							
								cr_pds_force_np_mem_stby
								12
								12
							
							
								cr_pds_force_usb_pds_rst
								11
								11
							
							
								cr_pds_force_bz_pds_rst
								10
								10
							
							
								cr_pds_force_np_pds_rst
								8
								8
							
							
								cr_pds_force_usb_iso_en
								7
								7
							
							
								cr_pds_force_bz_iso_en
								6
								6
							
							
								cr_pds_force_np_iso_en
								4
								4
							
							
								cr_pds_force_usb_pwr_off
								3
								3
							
							
								cr_pds_force_bz_pwr_off
								2
								2
							
							
								cr_pds_force_np_pwr_off
								0
								0
							
						
					
					
						PDS_CTL3
						PDS_CTL3.
						0x14
						
							
								cr_pds_misc_iso_en
								30
								30
							
							
								cr_pds_usb_iso_en
								29
								29
							
							
								cr_pds_ble_iso_en
								28
								28
							
							
								cr_pds_bz_iso_en
								27
								27
							
							
								cr_pds_np_iso_en
								24
								24
							
							
								cr_pds_force_ble_gate_clk
								14
								14
							
							
								cr_pds_force_misc_gate_clk
								13
								13
							
							
								cr_pds_force_ble_mem_stby
								11
								11
							
							
								cr_pds_force_misc_mem_stby
								10
								10
							
							
								cr_pds_force_ble_pds_rst
								8
								8
							
							
								cr_pds_force_misc_pds_rst
								7
								7
							
							
								cr_pds_force_ble_iso_en
								5
								5
							
							
								cr_pds_force_ble_pwr_off
								2
								2
							
							
								cr_pds_force_misc_pwr_off
								1
								1
							
						
					
					
						PDS_CTL4
						PDS_CTL4.
						0x18
						
							
								cr_pds_misc_dig_pwr_off
								31
								31
							
							
								cr_pds_misc_ana_pwr_off
								30
								30
							
							
								cr_pds_misc_gate_clk
								27
								27
							
							
								cr_pds_misc_mem_stby
								26
								26
							
							
								cr_pds_misc_reset
								25
								25
							
							
								cr_pds_misc_pwr_off
								24
								24
							
							
								cr_pds_usb_gate_clk
								23
								23
							
							
								cr_pds_usb_mem_stby
								22
								22
							
							
								cr_pds_usb_reset
								21
								21
							
							
								cr_pds_usb_pwr_off
								20
								20
							
							
								cr_pds_ble_gate_clk
								19
								19
							
							
								cr_pds_ble_mem_stby
								18
								18
							
							
								cr_pds_ble_reset
								17
								17
							
							
								cr_pds_ble_pwr_off
								16
								16
							
							
								cr_pds_bz_gate_clk
								15
								15
							
							
								cr_pds_bz_mem_stby
								14
								14
							
							
								cr_pds_bz_reset
								13
								13
							
							
								cr_pds_bz_pwr_off
								12
								12
							
							
								cr_pds_np_gate_clk
								3
								3
							
							
								cr_pds_np_mem_stby
								2
								2
							
							
								cr_pds_np_reset
								1
								1
							
							
								cr_pds_np_pwr_off
								0
								0
							
						
					
					
						pds_stat
						pds_stat.
						0x1C
						
							
								ro_pds_pll_state
								16
								17
							
							
								ro_pds_rf_state
								8
								11
							
							
								ro_pds_state
								0
								3
							
						
					
					
						pds_ram1
						pds_ram1.
						0x20
						
							
								cr_pds_ram_pgen
								8
								11
							
							
								cr_pds_ram_ret2n
								4
								7
							
							
								cr_pds_ram_ret1n
								0
								3
							
						
					
					
						pds_gpio_set_pu_pd
						pds_gpio_set_pu_pd.
						0x30
						
							
								cr_pds_gpio_28_23_pu
								24
								29
							
							
								cr_pds_gpio_28_23_pd
								16
								21
							
							
								cr_pds_gpio_22_17_pu
								8
								13
							
							
								cr_pds_gpio_22_17_pd
								0
								5
							
						
					
					
						pds_gpio_int
						pds_gpio_int.
						0x40
						
							
								pds_gpio_int_select
								8
								10
							
							
								pds_gpio_int_mode
								4
								6
							
							
								pds_gpio_int_clr
								2
								2
							
							
								pds_gpio_int_stat
								1
								1
							
							
								pds_gpio_int_mask
								0
								0
							
						
					
					
						rc32m_ctrl0
						rc32m_ctrl0.
						0x300
						
							
								rc32m_code_fr_ext
								22
								29
							
							
								rc32m_pd
								21
								21
							
							
								rc32m_cal_en
								20
								20
							
							
								rc32m_ext_code_en
								19
								19
							
							
								rc32m_refclk_half
								18
								18
							
							
								rc32m_allow_cal
								17
								17
							
							
								rc32m_dig_code_fr_cal
								6
								13
							
							
								rc32m_cal_precharge
								5
								5
							
							
								rc32m_cal_div
								3
								4
							
							
								rc32m_cal_inprogress
								2
								2
							
							
								rc32m_rdy
								1
								1
							
							
								rc32m_cal_done
								0
								0
							
						
					
					
						rc32m_ctrl1
						rc32m_ctrl1.
						0x304
						
							
								rc32m_reserved
								24
								31
							
							
								rc32m_clk_force_on
								4
								4
							
							
								rc32m_clk_inv
								3
								3
							
							
								rc32m_clk_soft_rst
								2
								2
							
							
								rc32m_soft_rst
								1
								1
							
							
								rc32m_test_en
								0
								0
							
						
					
					
						pu_rst_clkpll
						pu_rst_clkpll.
						0x400
						
							
								pu_clkpll
								10
								10
							
							
								pu_clkpll_sfreg
								9
								9
							
							
								clkpll_pu_cp
								8
								8
							
							
								clkpll_pu_pfd
								7
								7
							
							
								clkpll_pu_clamp_op
								6
								6
							
							
								clkpll_pu_fbdv
								5
								5
							
							
								clkpll_pu_postdiv
								4
								4
							
							
								clkpll_reset_refdiv
								3
								3
							
							
								clkpll_reset_fbdv
								2
								2
							
							
								clkpll_reset_postdiv
								1
								1
							
							
								clkpll_sdm_reset
								0
								0
							
						
					
					
						clkpll_top_ctrl
						clkpll_top_ctrl.
						0x404
						
							
								clkpll_resv
								24
								25
							
							
								clkpll_vg11_sel
								20
								21
							
							
								clkpll_refclk_sel
								16
								16
							
							
								clkpll_xtal_rc32m_sel
								12
								12
							
							
								clkpll_refdiv_ratio
								8
								11
							
							
								clkpll_postdiv
								0
								6
							
						
					
					
						clkpll_cp
						clkpll_cp.
						0x408
						
							
								clkpll_cp_opamp_en
								10
								10
							
							
								clkpll_cp_startup_en
								9
								9
							
							
								clkpll_int_frac_sw
								8
								8
							
							
								clkpll_icp_1u
								6
								7
							
							
								clkpll_icp_5u
								4
								5
							
							
								clkpll_sel_cp_bias
								0
								0
							
						
					
					
						clkpll_rz
						clkpll_rz.
						0x40C
						
							
								clkpll_rz
								16
								18
							
							
								clkpll_cz
								14
								15
							
							
								clkpll_c3
								12
								13
							
							
								clkpll_r4_short
								8
								8
							
							
								clkpll_r4
								4
								5
							
							
								clkpll_c4_en
								0
								0
							
						
					
					
						clkpll_fbdv
						clkpll_fbdv.
						0x410
						
							
								clkpll_sel_fb_clk
								2
								3
							
							
								clkpll_sel_sample_clk
								0
								1
							
						
					
					
						clkpll_vco
						clkpll_vco.
						0x414
						
							
								clkpll_shrtr
								3
								3
							
							
								clkpll_vco_speed
								0
								2
							
						
					
					
						clkpll_sdm
						clkpll_sdm.
						0x418
						
							
								clkpll_sdm_bypass
								29
								29
							
							
								clkpll_sdm_flag
								28
								28
							
							
								clkpll_dither_sel
								24
								25
							
							
								clkpll_sdmin
								0
								23
							
						
					
					
						clkpll_output_en
						clkpll_output_en.
						0x41C
						
							
								clkpll_en_div2_480m
								9
								9
							
							
								clkpll_en_32m
								8
								8
							
							
								clkpll_en_48m
								7
								7
							
							
								clkpll_en_80m
								6
								6
							
							
								clkpll_en_96m
								5
								5
							
							
								clkpll_en_120m
								4
								4
							
							
								clkpll_en_160m
								3
								3
							
							
								clkpll_en_192m
								2
								2
							
							
								clkpll_en_240m
								1
								1
							
							
								clkpll_en_480m
								0
								0
							
						
					
					
						clkpll_test_enable
						clkpll_test_enable.
						0x420
						
							
								clkpll_dc_tp_out_en
								8
								8
							
							
								ten_clkpll
								7
								7
							
							
								ten_clkpll_sfreg
								6
								6
							
							
								dten_clkpll_fin
								5
								5
							
							
								dten_clkpll_fref
								4
								4
							
							
								dten_clkpll_fsdm
								3
								3
							
							
								dten_clk32M
								2
								2
							
							
								dten_clk96M
								1
								1
							
							
								dten_clkpll_postdiv_clk
								0
								0
							
						
					
				
			
			
				HBN
				HBN.
				0x4000F000
				HBN
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						HBN_CTL
						HBN_CTL.
						0x0
						
							
								hbn_state
								28
								31
							
							
								sram_slp
								27
								27
							
							
								sram_slp_option
								26
								26
							
							
								pwr_on_option
								25
								25
							
							
								rtc_dly_option
								24
								24
							
							
								pu_dcdc18_aon
								23
								23
							
							
								hbn_ldo11_aon_vout_sel
								19
								22
							
							
								hbn_ldo11_rt_vout_sel
								15
								18
							
							
								hbn_dis_pwr_off_ldo11_rt
								14
								14
							
							
								hbn_dis_pwr_off_ldo11
								13
								13
							
							
								sw_rst
								12
								12
							
							
								pwrdn_hbn_rtc
								11
								11
							
							
								pwrdn_hbn_core
								9
								9
							
							
								trap_mode
								8
								8
							
							
								hbn_mode
								7
								7
							
							
								rtc_ctl
								0
								6
							
						
					
					
						HBN_TIME_L
						HBN_TIME_L.
						0x4
						
							
								hbn_time_l
								0
								31
							
						
					
					
						HBN_TIME_H
						HBN_TIME_H.
						0x8
						
							
								hbn_time_h
								0
								7
							
						
					
					
						RTC_TIME_L
						RTC_TIME_L.
						0xC
						
							
								rtc_time_latch_l
								0
								31
							
						
					
					
						RTC_TIME_H
						RTC_TIME_H.
						0x10
						
							
								rtc_time_latch
								31
								31
							
							
								rtc_time_latch_h
								0
								7
							
						
					
					
						HBN_IRQ_MODE
						HBN_IRQ_MODE.
						0x14
						
							
								pin_wakeup_en
								27
								27
							
							
								pin_wakeup_sel
								24
								26
							
							
								irq_acomp1_en
								22
								23
							
							
								irq_acomp0_en
								20
								21
							
							
								irq_bor_en
								18
								18
							
							
								reg_en_hw_pu_pd
								16
								16
							
							
								reg_aon_pad_ie_smt
								8
								12
							
							
								hbn_pin_wakeup_mask
								3
								7
							
							
								hbn_pin_wakeup_mode
								0
								2
							
						
					
					
						HBN_IRQ_STAT
						HBN_IRQ_STAT.
						0x18
						
							
								irq_stat
								0
								31
							
						
					
					
						HBN_IRQ_CLR
						HBN_IRQ_CLR.
						0x1C
						
							
								irq_clr
								0
								31
							
						
					
					
						HBN_PIR_CFG
						HBN_PIR_CFG.
						0x20
						
							
								gpadc_nosync
								9
								9
							
							
								gpadc_cgen
								8
								8
							
							
								pir_en
								7
								7
							
							
								pir_dis
								4
								5
							
							
								pir_lpf_sel
								2
								2
							
							
								pir_hpf_sel
								0
								1
							
						
					
					
						HBN_PIR_VTH
						HBN_PIR_VTH.
						0x24
						
							
								pir_vth
								0
								13
							
						
					
					
						HBN_PIR_INTERVAL
						HBN_PIR_INTERVAL.
						0x28
						
							
								pir_interval
								0
								11
							
						
					
					
						HBN_MISC
						HBN_MISC.
						0x2C
						
							
								hbn_flash_pulldown_aon
								24
								29
							
							
								hbn_flash_pullup_aon
								16
								21
							
							
								r_bor_out
								3
								3
							
							
								pu_bor
								2
								2
							
							
								bor_vth
								1
								1
							
							
								bor_sel
								0
								0
							
						
					
					
						HBN_GLB
						HBN_GLB.
						0x30
						
							
								sw_ldo11_aon_vout_sel
								28
								31
							
							
								sw_ldo11_rt_vout_sel
								24
								27
							
							
								sw_ldo11soc_vout_sel_aon
								16
								19
							
							
								hbn_clear_reset_event
								13
								13
							
							
								hbn_reset_event
								8
								12
							
							
								ldo11_rt_iload_sel
								6
								7
							
							
								hbn_pu_rc32k
								5
								5
							
							
								hbn_f32k_sel
								3
								4
							
							
								hbn_uart_clk_sel
								2
								2
							
							
								hbn_root_clk_sel
								0
								1
							
						
					
					
						HBN_SRAM
						HBN_SRAM.
						0x34
						
							
								retram_slp
								7
								7
							
							
								retram_ret
								6
								6
							
							
								retram_emaw
								3
								4
							
							
								retram_ema
								0
								2
							
						
					
					
						HBN_RSV0
						HBN_RSV0.
						0x100
						
							
								HBN_RSV0
								0
								31
							
						
					
					
						HBN_RSV1
						HBN_RSV1.
						0x104
						
							
								HBN_RSV1
								0
								31
							
						
					
					
						HBN_RSV2
						HBN_RSV2.
						0x108
						
							
								HBN_RSV2
								0
								31
							
						
					
					
						HBN_RSV3
						HBN_RSV3.
						0x10C
						
							
								HBN_RSV3
								0
								31
							
						
					
					
						rc32k_ctrl0
						rc32k_ctrl0.
						0x200
						
							
								rc32k_code_fr_ext
								22
								31
							
							
								rc32k_cal_en
								20
								20
							
							
								rc32k_ext_code_en
								19
								19
							
							
								rc32k_allow_cal
								18
								18
							
							
								rc32k_vref_dly
								16
								17
							
							
								rc32k_dig_code_fr_cal
								6
								15
							
							
								rc32k_cal_precharge
								5
								5
							
							
								rc32k_cal_div
								3
								4
							
							
								rc32k_cal_inprogress
								2
								2
							
							
								rc32k_rdy
								1
								1
							
							
								rc32k_cal_done
								0
								0
							
						
					
					
						xtal32k
						xtal32k.
						0x204
						
							
								pu_xtal32k
								19
								19
							
							
								pu_xtal32k_buf
								18
								18
							
							
								xtal32k_ac_cap_short
								17
								17
							
							
								xtal32k_capbank
								11
								16
							
							
								xtal32k_inv_stre
								9
								10
							
							
								xtal32k_otf_short
								8
								8
							
							
								xtal32k_outbuf_stre
								7
								7
							
							
								xtal32k_reg
								5
								6
							
							
								xtal32k_amp_ctrl
								3
								4
							
							
								xtal32k_ext_sel
								2
								2
							
							
								xtal32k_lowv_en
								1
								1
							
							
								xtal32k_hiz_en
								0
								0
							
						
					
				
			
			
				AON
				AON.
				
				AON
				32
				read-write
				
					0
					0x1000
					registers
				
				
					
						aon
						aon.
						0x800
						
							
								sw_pu_ldo11_rt
								22
								22
							
							
								ldo11_rt_pulldown_sel
								21
								21
							
							
								ldo11_rt_pulldown
								20
								20
							
							
								pu_aon_dc_tbuf
								12
								12
							
							
								aon_resv
								0
								7
							
						
					
					
						aon_common
						aon_common.
						0x804
						
							
								ten_cip_misc_aon
								20
								20
							
							
								ten_mbg_aon
								19
								19
							
							
								dten_xtal_aon
								18
								18
							
							
								ten_xtal_aon
								17
								17
							
							
								ten_ldo15rf_aon
								16
								16
							
							
								ten_bg_sys_aon
								12
								12
							
							
								ten_dcdc18_1_aon
								11
								11
							
							
								ten_dcdc18_0_aon
								10
								10
							
							
								ten_ldo11soc_aon
								9
								9
							
							
								ten_vddcore_aon
								8
								8
							
							
								ten_xtal32k
								6
								6
							
							
								dten_xtal32k
								5
								5
							
							
								ten_aon
								4
								4
							
							
								tmux_aon
								0
								2
							
						
					
					
						aon_misc
						aon_misc.
						0x808
						
							
								sw_bz_en_aon
								1
								1
							
							
								sw_soc_en_aon
								0
								0
							
						
					
					
						bg_sys_top
						bg_sys_top.
						0x810
						
							
								bg_sys_start_ctrl_aon
								12
								12
							
							
								pu_bg_sys_aon
								8
								8
							
							
								pmip_resv
								0
								7
							
						
					
					
						dcdc18_top_0
						dcdc18_top_0.
						0x814
						
							
								dcdc18_rdy_aon
								31
								31
							
							
								dcdc18_sstart_time_aon
								28
								29
							
							
								dcdc18_osc_inhibit_t2_aon
								27
								27
							
							
								dcdc18_slow_osc_aon
								26
								26
							
							
								dcdc18_stop_osc_aon
								25
								25
							
							
								dcdc18_slope_curr_sel_aon
								20
								24
							
							
								dcdc18_osc_freq_trim_aon
								16
								19
							
							
								dcdc18_osc_2m_mode_aon
								12
								12
							
							
								dcdc18_vpfm_aon
								8
								11
							
							
								dcdc18_vout_sel_aon
								1
								5
							
						
					
					
						dcdc18_top_1
						dcdc18_top_1.
						0x818
						
							
								dcdc18_pulldown_aon
								29
								29
							
							
								dcdc18_en_antiring_aon
								28
								28
							
							
								dcdc18_cfb_sel_aon
								24
								27
							
							
								dcdc18_chf_sel_aon
								20
								23
							
							
								dcdc18_rc_sel_aon
								16
								19
							
							
								dcdc18_nonoverlap_td_aon
								8
								12
							
							
								dcdc18_zvs_td_opt_aon
								4
								6
							
							
								dcdc18_cs_delay_aon
								1
								3
							
							
								dcdc18_force_cs_zvs_aon
								0
								0
							
						
					
					
						ldo11soc_and_dctest
						ldo11soc_and_dctest.
						0x81C
						
							
								pmip_dc_tp_out_en_aon
								31
								31
							
							
								pu_vddcore_misc_aon
								30
								30
							
							
								ldo11soc_power_good_aon
								29
								29
							
							
								ldo11soc_rdy_aon
								28
								28
							
							
								ldo11soc_cc_aon
								24
								25
							
							
								ldo11soc_vth_sel_aon
								12
								13
							
							
								ldo11soc_pulldown_sel_aon
								11
								11
							
							
								ldo11soc_pulldown_aon
								10
								10
							
							
								ldo11soc_sstart_delay_aon
								8
								9
							
							
								ldo11soc_sstart_sel_aon
								4
								4
							
							
								pu_ldo11soc_aon
								0
								0
							
						
					
					
						psw_irrcv
						psw_irrcv.
						0x820
						
							
								pu_ir_psw_aon
								0
								0
							
						
					
					
						rf_top_aon
						rf_top_aon.
						0x880
						
							
								ldo15rf_bypass_aon
								28
								28
							
							
								ldo15rf_cc_aon
								24
								25
							
							
								ldo15rf_vout_sel_aon
								16
								18
							
							
								ldo15rf_pulldown_sel_aon
								13
								13
							
							
								ldo15rf_pulldown_aon
								12
								12
							
							
								ldo15rf_sstart_delay_aon
								9
								10
							
							
								ldo15rf_sstart_sel_aon
								8
								8
							
							
								pu_xtal_aon
								5
								5
							
							
								pu_xtal_buf_aon
								4
								4
							
							
								pu_sfreg_aon
								2
								2
							
							
								pu_ldo15rf_aon
								1
								1
							
							
								pu_mbg_aon
								0
								0
							
						
					
					
						xtal_cfg
						xtal_cfg.
						0x884
						
							
								xtal_rdy_sel_aon
								30
								31
							
							
								xtal_gm_boost_aon
								28
								29
							
							
								xtal_capcode_in_aon
								22
								27
							
							
								xtal_capcode_out_aon
								16
								21
							
							
								xtal_amp_ctrl_aon
								14
								15
							
							
								xtal_sleep_aon
								13
								13
							
							
								xtal_fast_startup_aon
								12
								12
							
							
								xtal_buf_hp_aon
								8
								11
							
							
								xtal_buf_en_aon
								4
								7
							
							
								xtal_ext_sel_aon
								3
								3
							
							
								xtal_capcode_extra_aon
								2
								2
							
							
								xtal_bk_aon
								0
								1
							
						
					
					
						tsen
						tsen.
						0x888
						
							
								xtal_rdy_int_sel_aon
								30
								31
							
							
								xtal_inn_cfg_en_aon
								29
								29
							
							
								xtal_rdy
								28
								28
							
							
								tsen_refcode_rfcal
								16
								27
							
							
								tsen_refcode_corner
								0
								11
							
						
					
					
						acomp0_ctrl
						acomp0_ctrl.
						0x900
						
							
								acomp0_muxen
								26
								26
							
							
								acomp0_pos_sel
								22
								25
							
							
								acomp0_neg_sel
								18
								21
							
							
								acomp0_level_sel
								12
								17
							
							
								acomp0_bias_prog
								10
								11
							
							
								acomp0_hyst_selp
								7
								9
							
							
								acomp0_hyst_seln
								4
								6
							
							
								acomp0_en
								0
								0
							
						
					
					
						acomp1_ctrl
						acomp1_ctrl.
						0x904
						
							
								acomp1_muxen
								26
								26
							
							
								acomp1_pos_sel
								22
								25
							
							
								acomp1_neg_sel
								18
								21
							
							
								acomp1_level_sel
								12
								17
							
							
								acomp1_bias_prog
								10
								11
							
							
								acomp1_hyst_selp
								7
								9
							
							
								acomp1_hyst_seln
								4
								6
							
							
								acomp1_en
								0
								0
							
						
					
					
						acomp_ctrl
						acomp_ctrl.
						0x908
						
							
								acomp_reserved
								24
								31
							
							
								acomp0_out_raw
								19
								19
							
							
								acomp1_out_raw
								17
								17
							
							
								acomp0_test_sel
								12
								13
							
							
								acomp1_test_sel
								10
								11
							
							
								acomp0_test_en
								9
								9
							
							
								acomp1_test_en
								8
								8
							
							
								acomp0_rstn_ana
								1
								1
							
							
								acomp1_rstn_ana
								0
								0
							
						
					
					
						gpadc_reg_cmd
						gpadc_reg_cmd.
						0x90C
						
							
								gpadc_sen_test_en
								30
								30
							
							
								gpadc_sen_sel
								28
								29
							
							
								gpadc_chip_sen_pu
								27
								27
							
							
								gpadc_micboost_32db_en
								23
								23
							
							
								gpadc_mic_pga2_gain
								21
								22
							
							
								gpadc_mic1_diff
								20
								20
							
							
								gpadc_mic2_diff
								19
								19
							
							
								gpadc_dwa_en
								18
								18
							
							
								gpadc_byp_micboost
								16
								16
							
							
								gpadc_micpga_en
								15
								15
							
							
								gpadc_micbias_en
								14
								14
							
							
								gpadc_neg_gnd
								13
								13
							
							
								gpadc_pos_sel
								8
								12
							
							
								gpadc_neg_sel
								3
								7
							
							
								gpadc_soft_rst
								2
								2
							
							
								gpadc_conv_start
								1
								1
							
							
								gpadc_global_en
								0
								0
							
						
					
					
						gpadc_reg_config1
						gpadc_reg_config1.
						0x910
						
							
								gpadc_v18_sel
								29
								30
							
							
								gpadc_v11_sel
								27
								28
							
							
								gpadc_dither_en
								26
								26
							
							
								gpadc_scan_en
								25
								25
							
							
								gpadc_scan_length
								21
								24
							
							
								gpadc_clk_div_ratio
								18
								20
							
							
								gpadc_clk_ana_inv
								17
								17
							
							
								gpadc_lowv_det_en
								10
								10
							
							
								gpadc_vcm_hyst_sel
								9
								9
							
							
								gpadc_vcm_sel_en
								8
								8
							
							
								gpadc_res_sel
								2
								4
							
							
								gpadc_cont_conv_en
								1
								1
							
							
								gpadc_cal_os_en
								0
								0
							
						
					
					
						gpadc_reg_config2
						gpadc_reg_config2.
						0x914
						
							
								gpadc_tsvbe_low
								31
								31
							
							
								gpadc_dly_sel
								28
								30
							
							
								gpadc_pga1_gain
								25
								27
							
							
								gpadc_pga2_gain
								22
								24
							
							
								gpadc_test_sel
								19
								21
							
							
								gpadc_test_en
								18
								18
							
							
								gpadc_bias_sel
								17
								17
							
							
								gpadc_chop_mode
								15
								16
							
							
								gpadc_pga_vcmi_en
								14
								14
							
							
								gpadc_pga_en
								13
								13
							
							
								gpadc_pga_os_cal
								9
								12
							
							
								gpadc_pga_vcm
								7
								8
							
							
								gpadc_ts_en
								6
								6
							
							
								gpadc_tsext_sel
								5
								5
							
							
								gpadc_vbat_en
								4
								4
							
							
								gpadc_vref_sel
								3
								3
							
							
								gpadc_diff_mode
								2
								2
							
						
					
					
						gpadc_reg_scn_pos1
						adc converation sequence 1
						0x918
						
							
								gpadc_scan_pos_5
								25
								29
							
							
								gpadc_scan_pos_4
								20
								24
							
							
								gpadc_scan_pos_3
								15
								19
							
							
								gpadc_scan_pos_2
								10
								14
							
							
								gpadc_scan_pos_1
								5
								9
							
							
								gpadc_scan_pos_0
								0
								4
							
						
					
					
						gpadc_reg_scn_pos2
						adc converation sequence 2
						0x91C
						
							
								gpadc_scan_pos_11
								25
								29
							
							
								gpadc_scan_pos_10
								20
								24
							
							
								gpadc_scan_pos_9
								15
								19
							
							
								gpadc_scan_pos_8
								10
								14
							
							
								gpadc_scan_pos_7
								5
								9
							
							
								gpadc_scan_pos_6
								0
								4
							
						
					
					
						gpadc_reg_scn_neg1
						adc converation sequence 3
						0x920
						
							
								gpadc_scan_neg_5
								25
								29
							
							
								gpadc_scan_neg_4
								20
								24
							
							
								gpadc_scan_neg_3
								15
								19
							
							
								gpadc_scan_neg_2
								10
								14
							
							
								gpadc_scan_neg_1
								5
								9
							
							
								gpadc_scan_neg_0
								0
								4
							
						
					
					
						gpadc_reg_scn_neg2
						adc converation sequence 4
						0x924
						
							
								gpadc_scan_neg_11
								25
								29
							
							
								gpadc_scan_neg_10
								20
								24
							
							
								gpadc_scan_neg_9
								15
								19
							
							
								gpadc_scan_neg_8
								10
								14
							
							
								gpadc_scan_neg_7
								5
								9
							
							
								gpadc_scan_neg_6
								0
								4
							
						
					
					
						gpadc_reg_status
						gpadc_reg_status.
						0x928
						
							
								gpadc_reserved
								16
								31
							
							
								gpadc_data_rdy
								0
								0
							
						
					
					
						gpadc_reg_isr
						gpadc_reg_isr.
						0x92C
						
							
								gpadc_pos_satur_mask
								9
								9
							
							
								gpadc_neg_satur_mask
								8
								8
							
							
								gpadc_pos_satur_clr
								5
								5
							
							
								gpadc_neg_satur_clr
								4
								4
							
							
								gpadc_pos_satur
								1
								1
							
							
								gpadc_neg_satur
								0
								0
							
						
					
					
						gpadc_reg_result
						gpadc_reg_result.
						0x930
						
							
								gpadc_data_out
								0
								25
							
						
					
					
						gpadc_reg_raw_result
						gpadc_reg_raw_result.
						0x934
						
							
								gpadc_raw_data
								0
								11
							
						
					
					
						gpadc_reg_define
						gpadc_reg_define.
						0x938
						
							
								gpadc_os_cal_data
								0
								15
							
						
					
					
						hbncore_resv0
						hbncore_resv0.
						0x93C
						
							
								hbncore_resv0_data
								0
								31
							
						
					
					
						hbncore_resv1
						hbncore_resv1.
						0x940
						
							
								hbncore_resv1_data
								0
								31
							
						
					
				
			
		
	


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/spi_reg.h
================================================
/**
  ******************************************************************************
  * @file    spi_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __SPI_REG_H__
#define __SPI_REG_H__

#include "bl702.h"

/* 0x0 : spi_config */
#define SPI_CONFIG_OFFSET           (0x0)
#define SPI_CR_SPI_M_EN             SPI_CR_SPI_M_EN
#define SPI_CR_SPI_M_EN_POS         (0U)
#define SPI_CR_SPI_M_EN_LEN         (1U)
#define SPI_CR_SPI_M_EN_MSK         (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)
#define SPI_CR_SPI_M_EN_UMSK        (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS))
#define SPI_CR_SPI_S_EN             SPI_CR_SPI_S_EN
#define SPI_CR_SPI_S_EN_POS         (1U)
#define SPI_CR_SPI_S_EN_LEN         (1U)
#define SPI_CR_SPI_S_EN_MSK         (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)
#define SPI_CR_SPI_S_EN_UMSK        (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS))
#define SPI_CR_SPI_FRAME_SIZE       SPI_CR_SPI_FRAME_SIZE
#define SPI_CR_SPI_FRAME_SIZE_POS   (2U)
#define SPI_CR_SPI_FRAME_SIZE_LEN   (2U)
#define SPI_CR_SPI_FRAME_SIZE_MSK   (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)
#define SPI_CR_SPI_FRAME_SIZE_UMSK  (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS))
#define SPI_CR_SPI_SCLK_POL         SPI_CR_SPI_SCLK_POL
#define SPI_CR_SPI_SCLK_POL_POS     (4U)
#define SPI_CR_SPI_SCLK_POL_LEN     (1U)
#define SPI_CR_SPI_SCLK_POL_MSK     (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)
#define SPI_CR_SPI_SCLK_POL_UMSK    (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS))
#define SPI_CR_SPI_SCLK_PH          SPI_CR_SPI_SCLK_PH
#define SPI_CR_SPI_SCLK_PH_POS      (5U)
#define SPI_CR_SPI_SCLK_PH_LEN      (1U)
#define SPI_CR_SPI_SCLK_PH_MSK      (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)
#define SPI_CR_SPI_SCLK_PH_UMSK     (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS))
#define SPI_CR_SPI_BIT_INV          SPI_CR_SPI_BIT_INV
#define SPI_CR_SPI_BIT_INV_POS      (6U)
#define SPI_CR_SPI_BIT_INV_LEN      (1U)
#define SPI_CR_SPI_BIT_INV_MSK      (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)
#define SPI_CR_SPI_BIT_INV_UMSK     (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS))
#define SPI_CR_SPI_BYTE_INV         SPI_CR_SPI_BYTE_INV
#define SPI_CR_SPI_BYTE_INV_POS     (7U)
#define SPI_CR_SPI_BYTE_INV_LEN     (1U)
#define SPI_CR_SPI_BYTE_INV_MSK     (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)
#define SPI_CR_SPI_BYTE_INV_UMSK    (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS))
#define SPI_CR_SPI_RXD_IGNR_EN      SPI_CR_SPI_RXD_IGNR_EN
#define SPI_CR_SPI_RXD_IGNR_EN_POS  (8U)
#define SPI_CR_SPI_RXD_IGNR_EN_LEN  (1U)
#define SPI_CR_SPI_RXD_IGNR_EN_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)
#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS))
#define SPI_CR_SPI_M_CONT_EN        SPI_CR_SPI_M_CONT_EN
#define SPI_CR_SPI_M_CONT_EN_POS    (9U)
#define SPI_CR_SPI_M_CONT_EN_LEN    (1U)
#define SPI_CR_SPI_M_CONT_EN_MSK    (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)
#define SPI_CR_SPI_M_CONT_EN_UMSK   (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS))
#define SPI_CR_SPI_DEG_EN           SPI_CR_SPI_DEG_EN
#define SPI_CR_SPI_DEG_EN_POS       (11U)
#define SPI_CR_SPI_DEG_EN_LEN       (1U)
#define SPI_CR_SPI_DEG_EN_MSK       (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)
#define SPI_CR_SPI_DEG_EN_UMSK      (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS))
#define SPI_CR_SPI_DEG_CNT          SPI_CR_SPI_DEG_CNT
#define SPI_CR_SPI_DEG_CNT_POS      (12U)
#define SPI_CR_SPI_DEG_CNT_LEN      (4U)
#define SPI_CR_SPI_DEG_CNT_MSK      (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)
#define SPI_CR_SPI_DEG_CNT_UMSK     (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS))

/* 0x4 : spi_int_sts */
#define SPI_INT_STS_OFFSET       (0x4)
#define SPI_END_INT              SPI_END_INT
#define SPI_END_INT_POS          (0U)
#define SPI_END_INT_LEN          (1U)
#define SPI_END_INT_MSK          (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)
#define SPI_END_INT_UMSK         (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS))
#define SPI_TXF_INT              SPI_TXF_INT
#define SPI_TXF_INT_POS          (1U)
#define SPI_TXF_INT_LEN          (1U)
#define SPI_TXF_INT_MSK          (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)
#define SPI_TXF_INT_UMSK         (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS))
#define SPI_RXF_INT              SPI_RXF_INT
#define SPI_RXF_INT_POS          (2U)
#define SPI_RXF_INT_LEN          (1U)
#define SPI_RXF_INT_MSK          (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)
#define SPI_RXF_INT_UMSK         (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS))
#define SPI_STO_INT              SPI_STO_INT
#define SPI_STO_INT_POS          (3U)
#define SPI_STO_INT_LEN          (1U)
#define SPI_STO_INT_MSK          (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)
#define SPI_STO_INT_UMSK         (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS))
#define SPI_TXU_INT              SPI_TXU_INT
#define SPI_TXU_INT_POS          (4U)
#define SPI_TXU_INT_LEN          (1U)
#define SPI_TXU_INT_MSK          (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)
#define SPI_TXU_INT_UMSK         (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS))
#define SPI_FER_INT              SPI_FER_INT
#define SPI_FER_INT_POS          (5U)
#define SPI_FER_INT_LEN          (1U)
#define SPI_FER_INT_MSK          (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)
#define SPI_FER_INT_UMSK         (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS))
#define SPI_CR_SPI_END_MASK      SPI_CR_SPI_END_MASK
#define SPI_CR_SPI_END_MASK_POS  (8U)
#define SPI_CR_SPI_END_MASK_LEN  (1U)
#define SPI_CR_SPI_END_MASK_MSK  (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)
#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS))
#define SPI_CR_SPI_TXF_MASK      SPI_CR_SPI_TXF_MASK
#define SPI_CR_SPI_TXF_MASK_POS  (9U)
#define SPI_CR_SPI_TXF_MASK_LEN  (1U)
#define SPI_CR_SPI_TXF_MASK_MSK  (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)
#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS))
#define SPI_CR_SPI_RXF_MASK      SPI_CR_SPI_RXF_MASK
#define SPI_CR_SPI_RXF_MASK_POS  (10U)
#define SPI_CR_SPI_RXF_MASK_LEN  (1U)
#define SPI_CR_SPI_RXF_MASK_MSK  (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)
#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS))
#define SPI_CR_SPI_STO_MASK      SPI_CR_SPI_STO_MASK
#define SPI_CR_SPI_STO_MASK_POS  (11U)
#define SPI_CR_SPI_STO_MASK_LEN  (1U)
#define SPI_CR_SPI_STO_MASK_MSK  (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)
#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS))
#define SPI_CR_SPI_TXU_MASK      SPI_CR_SPI_TXU_MASK
#define SPI_CR_SPI_TXU_MASK_POS  (12U)
#define SPI_CR_SPI_TXU_MASK_LEN  (1U)
#define SPI_CR_SPI_TXU_MASK_MSK  (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)
#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS))
#define SPI_CR_SPI_FER_MASK      SPI_CR_SPI_FER_MASK
#define SPI_CR_SPI_FER_MASK_POS  (13U)
#define SPI_CR_SPI_FER_MASK_LEN  (1U)
#define SPI_CR_SPI_FER_MASK_MSK  (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)
#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS))
#define SPI_CR_SPI_END_CLR       SPI_CR_SPI_END_CLR
#define SPI_CR_SPI_END_CLR_POS   (16U)
#define SPI_CR_SPI_END_CLR_LEN   (1U)
#define SPI_CR_SPI_END_CLR_MSK   (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)
#define SPI_CR_SPI_END_CLR_UMSK  (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS))
#define SPI_CR_SPI_STO_CLR       SPI_CR_SPI_STO_CLR
#define SPI_CR_SPI_STO_CLR_POS   (19U)
#define SPI_CR_SPI_STO_CLR_LEN   (1U)
#define SPI_CR_SPI_STO_CLR_MSK   (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)
#define SPI_CR_SPI_STO_CLR_UMSK  (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS))
#define SPI_CR_SPI_TXU_CLR       SPI_CR_SPI_TXU_CLR
#define SPI_CR_SPI_TXU_CLR_POS   (20U)
#define SPI_CR_SPI_TXU_CLR_LEN   (1U)
#define SPI_CR_SPI_TXU_CLR_MSK   (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)
#define SPI_CR_SPI_TXU_CLR_UMSK  (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS))
#define SPI_CR_SPI_END_EN        SPI_CR_SPI_END_EN
#define SPI_CR_SPI_END_EN_POS    (24U)
#define SPI_CR_SPI_END_EN_LEN    (1U)
#define SPI_CR_SPI_END_EN_MSK    (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)
#define SPI_CR_SPI_END_EN_UMSK   (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS))
#define SPI_CR_SPI_TXF_EN        SPI_CR_SPI_TXF_EN
#define SPI_CR_SPI_TXF_EN_POS    (25U)
#define SPI_CR_SPI_TXF_EN_LEN    (1U)
#define SPI_CR_SPI_TXF_EN_MSK    (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)
#define SPI_CR_SPI_TXF_EN_UMSK   (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS))
#define SPI_CR_SPI_RXF_EN        SPI_CR_SPI_RXF_EN
#define SPI_CR_SPI_RXF_EN_POS    (26U)
#define SPI_CR_SPI_RXF_EN_LEN    (1U)
#define SPI_CR_SPI_RXF_EN_MSK    (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)
#define SPI_CR_SPI_RXF_EN_UMSK   (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS))
#define SPI_CR_SPI_STO_EN        SPI_CR_SPI_STO_EN
#define SPI_CR_SPI_STO_EN_POS    (27U)
#define SPI_CR_SPI_STO_EN_LEN    (1U)
#define SPI_CR_SPI_STO_EN_MSK    (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)
#define SPI_CR_SPI_STO_EN_UMSK   (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS))
#define SPI_CR_SPI_TXU_EN        SPI_CR_SPI_TXU_EN
#define SPI_CR_SPI_TXU_EN_POS    (28U)
#define SPI_CR_SPI_TXU_EN_LEN    (1U)
#define SPI_CR_SPI_TXU_EN_MSK    (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)
#define SPI_CR_SPI_TXU_EN_UMSK   (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS))
#define SPI_CR_SPI_FER_EN        SPI_CR_SPI_FER_EN
#define SPI_CR_SPI_FER_EN_POS    (29U)
#define SPI_CR_SPI_FER_EN_LEN    (1U)
#define SPI_CR_SPI_FER_EN_MSK    (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)
#define SPI_CR_SPI_FER_EN_UMSK   (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS))

/* 0x8 : spi_bus_busy */
#define SPI_BUS_BUSY_OFFSET       (0x8)
#define SPI_STS_SPI_BUS_BUSY      SPI_STS_SPI_BUS_BUSY
#define SPI_STS_SPI_BUS_BUSY_POS  (0U)
#define SPI_STS_SPI_BUS_BUSY_LEN  (1U)
#define SPI_STS_SPI_BUS_BUSY_MSK  (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)
#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS))

/* 0x10 : spi_prd_0 */
#define SPI_PRD_0_OFFSET           (0x10)
#define SPI_CR_SPI_PRD_S           SPI_CR_SPI_PRD_S
#define SPI_CR_SPI_PRD_S_POS       (0U)
#define SPI_CR_SPI_PRD_S_LEN       (8U)
#define SPI_CR_SPI_PRD_S_MSK       (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)
#define SPI_CR_SPI_PRD_S_UMSK      (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS))
#define SPI_CR_SPI_PRD_P           SPI_CR_SPI_PRD_P
#define SPI_CR_SPI_PRD_P_POS       (8U)
#define SPI_CR_SPI_PRD_P_LEN       (8U)
#define SPI_CR_SPI_PRD_P_MSK       (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)
#define SPI_CR_SPI_PRD_P_UMSK      (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS))
#define SPI_CR_SPI_PRD_D_PH_0      SPI_CR_SPI_PRD_D_PH_0
#define SPI_CR_SPI_PRD_D_PH_0_POS  (16U)
#define SPI_CR_SPI_PRD_D_PH_0_LEN  (8U)
#define SPI_CR_SPI_PRD_D_PH_0_MSK  (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)
#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS))
#define SPI_CR_SPI_PRD_D_PH_1      SPI_CR_SPI_PRD_D_PH_1
#define SPI_CR_SPI_PRD_D_PH_1_POS  (24U)
#define SPI_CR_SPI_PRD_D_PH_1_LEN  (8U)
#define SPI_CR_SPI_PRD_D_PH_1_MSK  (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)
#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS))

/* 0x14 : spi_prd_1 */
#define SPI_PRD_1_OFFSET      (0x14)
#define SPI_CR_SPI_PRD_I      SPI_CR_SPI_PRD_I
#define SPI_CR_SPI_PRD_I_POS  (0U)
#define SPI_CR_SPI_PRD_I_LEN  (8U)
#define SPI_CR_SPI_PRD_I_MSK  (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)
#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS))

/* 0x18 : spi_rxd_ignr */
#define SPI_RXD_IGNR_OFFSET        (0x18)
#define SPI_CR_SPI_RXD_IGNR_P      SPI_CR_SPI_RXD_IGNR_P
#define SPI_CR_SPI_RXD_IGNR_P_POS  (0U)
#define SPI_CR_SPI_RXD_IGNR_P_LEN  (5U)
#define SPI_CR_SPI_RXD_IGNR_P_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)
#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS))
#define SPI_CR_SPI_RXD_IGNR_S      SPI_CR_SPI_RXD_IGNR_S
#define SPI_CR_SPI_RXD_IGNR_S_POS  (16U)
#define SPI_CR_SPI_RXD_IGNR_S_LEN  (5U)
#define SPI_CR_SPI_RXD_IGNR_S_MSK  (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)
#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS))

/* 0x1C : spi_sto_value */
#define SPI_STO_VALUE_OFFSET      (0x1C)
#define SPI_CR_SPI_STO_VALUE      SPI_CR_SPI_STO_VALUE
#define SPI_CR_SPI_STO_VALUE_POS  (0U)
#define SPI_CR_SPI_STO_VALUE_LEN  (12U)
#define SPI_CR_SPI_STO_VALUE_MSK  (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)
#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS))

/* 0x80 : spi_fifo_config_0 */
#define SPI_FIFO_CONFIG_0_OFFSET   (0x80)
#define SPI_DMA_TX_EN              SPI_DMA_TX_EN
#define SPI_DMA_TX_EN_POS          (0U)
#define SPI_DMA_TX_EN_LEN          (1U)
#define SPI_DMA_TX_EN_MSK          (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)
#define SPI_DMA_TX_EN_UMSK         (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS))
#define SPI_DMA_RX_EN              SPI_DMA_RX_EN
#define SPI_DMA_RX_EN_POS          (1U)
#define SPI_DMA_RX_EN_LEN          (1U)
#define SPI_DMA_RX_EN_MSK          (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)
#define SPI_DMA_RX_EN_UMSK         (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS))
#define SPI_TX_FIFO_CLR            SPI_TX_FIFO_CLR
#define SPI_TX_FIFO_CLR_POS        (2U)
#define SPI_TX_FIFO_CLR_LEN        (1U)
#define SPI_TX_FIFO_CLR_MSK        (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)
#define SPI_TX_FIFO_CLR_UMSK       (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS))
#define SPI_RX_FIFO_CLR            SPI_RX_FIFO_CLR
#define SPI_RX_FIFO_CLR_POS        (3U)
#define SPI_RX_FIFO_CLR_LEN        (1U)
#define SPI_RX_FIFO_CLR_MSK        (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)
#define SPI_RX_FIFO_CLR_UMSK       (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS))
#define SPI_TX_FIFO_OVERFLOW       SPI_TX_FIFO_OVERFLOW
#define SPI_TX_FIFO_OVERFLOW_POS   (4U)
#define SPI_TX_FIFO_OVERFLOW_LEN   (1U)
#define SPI_TX_FIFO_OVERFLOW_MSK   (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)
#define SPI_TX_FIFO_OVERFLOW_UMSK  (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS))
#define SPI_TX_FIFO_UNDERFLOW      SPI_TX_FIFO_UNDERFLOW
#define SPI_TX_FIFO_UNDERFLOW_POS  (5U)
#define SPI_TX_FIFO_UNDERFLOW_LEN  (1U)
#define SPI_TX_FIFO_UNDERFLOW_MSK  (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)
#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS))
#define SPI_RX_FIFO_OVERFLOW       SPI_RX_FIFO_OVERFLOW
#define SPI_RX_FIFO_OVERFLOW_POS   (6U)
#define SPI_RX_FIFO_OVERFLOW_LEN   (1U)
#define SPI_RX_FIFO_OVERFLOW_MSK   (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)
#define SPI_RX_FIFO_OVERFLOW_UMSK  (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS))
#define SPI_RX_FIFO_UNDERFLOW      SPI_RX_FIFO_UNDERFLOW
#define SPI_RX_FIFO_UNDERFLOW_POS  (7U)
#define SPI_RX_FIFO_UNDERFLOW_LEN  (1U)
#define SPI_RX_FIFO_UNDERFLOW_MSK  (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)
#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS))

/* 0x84 : spi_fifo_config_1 */
#define SPI_FIFO_CONFIG_1_OFFSET (0x84)
#define SPI_TX_FIFO_CNT          SPI_TX_FIFO_CNT
#define SPI_TX_FIFO_CNT_POS      (0U)
#define SPI_TX_FIFO_CNT_LEN      (3U)
#define SPI_TX_FIFO_CNT_MSK      (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)
#define SPI_TX_FIFO_CNT_UMSK     (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS))
#define SPI_RX_FIFO_CNT          SPI_RX_FIFO_CNT
#define SPI_RX_FIFO_CNT_POS      (8U)
#define SPI_RX_FIFO_CNT_LEN      (3U)
#define SPI_RX_FIFO_CNT_MSK      (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)
#define SPI_RX_FIFO_CNT_UMSK     (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS))
#define SPI_TX_FIFO_TH           SPI_TX_FIFO_TH
#define SPI_TX_FIFO_TH_POS       (16U)
#define SPI_TX_FIFO_TH_LEN       (2U)
#define SPI_TX_FIFO_TH_MSK       (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)
#define SPI_TX_FIFO_TH_UMSK      (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS))
#define SPI_RX_FIFO_TH           SPI_RX_FIFO_TH
#define SPI_RX_FIFO_TH_POS       (24U)
#define SPI_RX_FIFO_TH_LEN       (2U)
#define SPI_RX_FIFO_TH_MSK       (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)
#define SPI_RX_FIFO_TH_UMSK      (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS))

/* 0x88 : spi_fifo_wdata */
#define SPI_FIFO_WDATA_OFFSET (0x88)
#define SPI_FIFO_WDATA        SPI_FIFO_WDATA
#define SPI_FIFO_WDATA_POS    (0U)
#define SPI_FIFO_WDATA_LEN    (32U)
#define SPI_FIFO_WDATA_MSK    (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)
#define SPI_FIFO_WDATA_UMSK   (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS))

/* 0x8C : spi_fifo_rdata */
#define SPI_FIFO_RDATA_OFFSET (0x8C)
#define SPI_FIFO_RDATA        SPI_FIFO_RDATA
#define SPI_FIFO_RDATA_POS    (0U)
#define SPI_FIFO_RDATA_LEN    (32U)
#define SPI_FIFO_RDATA_MSK    (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)
#define SPI_FIFO_RDATA_UMSK   (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS))

struct spi_reg {
    /* 0x0 : spi_config */
    union {
        struct
        {
            uint32_t cr_spi_m_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_spi_s_en        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_spi_frame_size  : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t cr_spi_sclk_pol    : 1;  /* [    4],        r/w,        0x0 */
            uint32_t cr_spi_sclk_ph     : 1;  /* [    5],        r/w,        0x0 */
            uint32_t cr_spi_bit_inv     : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_spi_byte_inv    : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_spi_rxd_ignr_en : 1;  /* [    8],        r/w,        0x0 */
            uint32_t cr_spi_m_cont_en   : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reserved_10        : 1;  /* [   10],       rsvd,        0x0 */
            uint32_t cr_spi_deg_en      : 1;  /* [   11],        r/w,        0x0 */
            uint32_t cr_spi_deg_cnt     : 4;  /* [15:12],        r/w,        0x0 */
            uint32_t reserved_16_31     : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_config;

    /* 0x4 : spi_int_sts */
    union {
        struct
        {
            uint32_t spi_end_int     : 1; /* [    0],          r,        0x0 */
            uint32_t spi_txf_int     : 1; /* [    1],          r,        0x0 */
            uint32_t spi_rxf_int     : 1; /* [    2],          r,        0x0 */
            uint32_t spi_sto_int     : 1; /* [    3],          r,        0x0 */
            uint32_t spi_txu_int     : 1; /* [    4],          r,        0x0 */
            uint32_t spi_fer_int     : 1; /* [    5],          r,        0x0 */
            uint32_t reserved_6_7    : 2; /* [ 7: 6],       rsvd,        0x0 */
            uint32_t cr_spi_end_mask : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_spi_txf_mask : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_spi_rxf_mask : 1; /* [   10],        r/w,        0x1 */
            uint32_t cr_spi_sto_mask : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_spi_txu_mask : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_spi_fer_mask : 1; /* [   13],        r/w,        0x1 */
            uint32_t reserved_14_15  : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t cr_spi_end_clr  : 1; /* [   16],        w1c,        0x0 */
            uint32_t rsvd_17         : 1; /* [   17],       rsvd,        0x0 */
            uint32_t rsvd_18         : 1; /* [   18],       rsvd,        0x0 */
            uint32_t cr_spi_sto_clr  : 1; /* [   19],        w1c,        0x0 */
            uint32_t cr_spi_txu_clr  : 1; /* [   20],        w1c,        0x0 */
            uint32_t rsvd_21         : 1; /* [   21],       rsvd,        0x0 */
            uint32_t reserved_22_23  : 2; /* [23:22],       rsvd,        0x0 */
            uint32_t cr_spi_end_en   : 1; /* [   24],        r/w,        0x1 */
            uint32_t cr_spi_txf_en   : 1; /* [   25],        r/w,        0x1 */
            uint32_t cr_spi_rxf_en   : 1; /* [   26],        r/w,        0x1 */
            uint32_t cr_spi_sto_en   : 1; /* [   27],        r/w,        0x1 */
            uint32_t cr_spi_txu_en   : 1; /* [   28],        r/w,        0x1 */
            uint32_t cr_spi_fer_en   : 1; /* [   29],        r/w,        0x1 */
            uint32_t reserved_30_31  : 2; /* [31:30],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_int_sts;

    /* 0x8 : spi_bus_busy */
    union {
        struct
        {
            uint32_t sts_spi_bus_busy : 1;  /* [    0],          r,        0x0 */
            uint32_t reserved_1_31    : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_bus_busy;

    /* 0xc  reserved */
    uint8_t RESERVED0xc[4];

    /* 0x10 : spi_prd_0 */
    union {
        struct
        {
            uint32_t cr_spi_prd_s      : 8; /* [ 7: 0],        r/w,        0xf */
            uint32_t cr_spi_prd_p      : 8; /* [15: 8],        r/w,        0xf */
            uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16],        r/w,        0xf */
            uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24],        r/w,        0xf */
        } BF;
        uint32_t WORD;
    } spi_prd_0;

    /* 0x14 : spi_prd_1 */
    union {
        struct
        {
            uint32_t cr_spi_prd_i  : 8;  /* [ 7: 0],        r/w,        0xf */
            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_prd_1;

    /* 0x18 : spi_rxd_ignr */
    union {
        struct
        {
            uint32_t cr_spi_rxd_ignr_p : 5;  /* [ 4: 0],        r/w,        0x0 */
            uint32_t reserved_5_15     : 11; /* [15: 5],       rsvd,        0x0 */
            uint32_t cr_spi_rxd_ignr_s : 5;  /* [20:16],        r/w,        0x0 */
            uint32_t reserved_21_31    : 11; /* [31:21],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_rxd_ignr;

    /* 0x1C : spi_sto_value */
    union {
        struct
        {
            uint32_t cr_spi_sto_value : 12; /* [11: 0],        r/w,      0xfff */
            uint32_t reserved_12_31   : 20; /* [31:12],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_sto_value;

    /* 0x20  reserved */
    uint8_t RESERVED0x20[96];

    /* 0x80 : spi_fifo_config_0 */
    union {
        struct
        {
            uint32_t spi_dma_tx_en     : 1;  /* [    0],        r/w,        0x0 */
            uint32_t spi_dma_rx_en     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_fifo_config_0;

    /* 0x84 : spi_fifo_config_1 */
    union {
        struct
        {
            uint32_t tx_fifo_cnt    : 3; /* [ 2: 0],          r,        0x4 */
            uint32_t reserved_3_7   : 5; /* [ 7: 3],       rsvd,        0x0 */
            uint32_t rx_fifo_cnt    : 3; /* [10: 8],          r,        0x0 */
            uint32_t reserved_11_15 : 5; /* [15:11],       rsvd,        0x0 */
            uint32_t tx_fifo_th     : 2; /* [17:16],        r/w,        0x0 */
            uint32_t reserved_18_23 : 6; /* [23:18],       rsvd,        0x0 */
            uint32_t rx_fifo_th     : 2; /* [25:24],        r/w,        0x0 */
            uint32_t reserved_26_31 : 6; /* [31:26],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_fifo_config_1;

    /* 0x88 : spi_fifo_wdata */
    union {
        struct
        {
            uint32_t spi_fifo_wdata : 32; /* [31: 0],          w,          x */
        } BF;
        uint32_t WORD;
    } spi_fifo_wdata;

    /* 0x8C : spi_fifo_rdata */
    union {
        struct
        {
            uint32_t spi_fifo_rdata : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } spi_fifo_rdata;
};

typedef volatile struct spi_reg spi_reg_t;

#endif /* __SPI_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/timer_reg.h
================================================
/**
  ******************************************************************************
  * @file    timer_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __TIMER_REG_H__
#define __TIMER_REG_H__

#include "bl702.h"

/* 0x0 : TCCR */
#define TIMER_TCCR_OFFSET (0x0)
#define TIMER_CS_1        TIMER_CS_1
#define TIMER_CS_1_POS    (2U)
#define TIMER_CS_1_LEN    (2U)
#define TIMER_CS_1_MSK    (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)
#define TIMER_CS_1_UMSK   (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS))
#define TIMER_CS_2        TIMER_CS_2
#define TIMER_CS_2_POS    (5U)
#define TIMER_CS_2_LEN    (2U)
#define TIMER_CS_2_MSK    (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)
#define TIMER_CS_2_UMSK   (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS))
#define TIMER_CS_WDT      TIMER_CS_WDT
#define TIMER_CS_WDT_POS  (8U)
#define TIMER_CS_WDT_LEN  (2U)
#define TIMER_CS_WDT_MSK  (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)
#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS))

/* 0x10 : TMR2_0 */
#define TIMER_TMR2_0_OFFSET (0x10)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x14 : TMR2_1 */
#define TIMER_TMR2_1_OFFSET (0x14)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x18 : TMR2_2 */
#define TIMER_TMR2_2_OFFSET (0x18)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x1C : TMR3_0 */
#define TIMER_TMR3_0_OFFSET (0x1C)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x20 : TMR3_1 */
#define TIMER_TMR3_1_OFFSET (0x20)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x24 : TMR3_2 */
#define TIMER_TMR3_2_OFFSET (0x24)
#define TIMER_TMR           TIMER_TMR
#define TIMER_TMR_POS       (0U)
#define TIMER_TMR_LEN       (32U)
#define TIMER_TMR_MSK       (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
#define TIMER_TMR_UMSK      (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))

/* 0x2C : TCR2 */
#define TIMER_TCR2_OFFSET (0x2C)
#define TIMER_TCR         TIMER_TCR
#define TIMER_TCR_POS     (0U)
#define TIMER_TCR_LEN     (32U)
#define TIMER_TCR_MSK     (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
#define TIMER_TCR_UMSK    (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))

/* 0x30 : TCR3 */
#define TIMER_TCR3_OFFSET (0x30)
#define TIMER_TCR         TIMER_TCR
#define TIMER_TCR_POS     (0U)
#define TIMER_TCR_LEN     (32U)
#define TIMER_TCR_MSK     (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
#define TIMER_TCR_UMSK    (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))

/* 0x38 : TMSR2 */
#define TIMER_TMSR2_OFFSET (0x38)
#define TIMER_TMSR_0       TIMER_TMSR_0
#define TIMER_TMSR_0_POS   (0U)
#define TIMER_TMSR_0_LEN   (1U)
#define TIMER_TMSR_0_MSK   (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK  (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1       TIMER_TMSR_1
#define TIMER_TMSR_1_POS   (1U)
#define TIMER_TMSR_1_LEN   (1U)
#define TIMER_TMSR_1_MSK   (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK  (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2       TIMER_TMSR_2
#define TIMER_TMSR_2_POS   (2U)
#define TIMER_TMSR_2_LEN   (1U)
#define TIMER_TMSR_2_MSK   (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK  (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))

/* 0x3C : TMSR3 */
#define TIMER_TMSR3_OFFSET (0x3C)
#define TIMER_TMSR_0       TIMER_TMSR_0
#define TIMER_TMSR_0_POS   (0U)
#define TIMER_TMSR_0_LEN   (1U)
#define TIMER_TMSR_0_MSK   (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK  (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
#define TIMER_TMSR_1       TIMER_TMSR_1
#define TIMER_TMSR_1_POS   (1U)
#define TIMER_TMSR_1_LEN   (1U)
#define TIMER_TMSR_1_MSK   (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK  (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
#define TIMER_TMSR_2       TIMER_TMSR_2
#define TIMER_TMSR_2_POS   (2U)
#define TIMER_TMSR_2_LEN   (1U)
#define TIMER_TMSR_2_MSK   (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK  (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))

/* 0x44 : TIER2 */
#define TIMER_TIER2_OFFSET (0x44)
#define TIMER_TIER_0       TIMER_TIER_0
#define TIMER_TIER_0_POS   (0U)
#define TIMER_TIER_0_LEN   (1U)
#define TIMER_TIER_0_MSK   (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK  (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1       TIMER_TIER_1
#define TIMER_TIER_1_POS   (1U)
#define TIMER_TIER_1_LEN   (1U)
#define TIMER_TIER_1_MSK   (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK  (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2       TIMER_TIER_2
#define TIMER_TIER_2_POS   (2U)
#define TIMER_TIER_2_LEN   (1U)
#define TIMER_TIER_2_MSK   (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK  (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))

/* 0x48 : TIER3 */
#define TIMER_TIER3_OFFSET (0x48)
#define TIMER_TIER_0       TIMER_TIER_0
#define TIMER_TIER_0_POS   (0U)
#define TIMER_TIER_0_LEN   (1U)
#define TIMER_TIER_0_MSK   (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK  (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
#define TIMER_TIER_1       TIMER_TIER_1
#define TIMER_TIER_1_POS   (1U)
#define TIMER_TIER_1_LEN   (1U)
#define TIMER_TIER_1_MSK   (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK  (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
#define TIMER_TIER_2       TIMER_TIER_2
#define TIMER_TIER_2_POS   (2U)
#define TIMER_TIER_2_LEN   (1U)
#define TIMER_TIER_2_MSK   (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK  (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))

/* 0x50 : TPLVR2 */
#define TIMER_TPLVR2_OFFSET (0x50)
#define TIMER_TPLVR         TIMER_TPLVR
#define TIMER_TPLVR_POS     (0U)
#define TIMER_TPLVR_LEN     (32U)
#define TIMER_TPLVR_MSK     (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK    (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))

/* 0x54 : TPLVR3 */
#define TIMER_TPLVR3_OFFSET (0x54)
#define TIMER_TPLVR         TIMER_TPLVR
#define TIMER_TPLVR_POS     (0U)
#define TIMER_TPLVR_LEN     (32U)
#define TIMER_TPLVR_MSK     (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK    (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))

/* 0x5C : TPLCR2 */
#define TIMER_TPLCR2_OFFSET (0x5C)
#define TIMER_TPLCR         TIMER_TPLCR
#define TIMER_TPLCR_POS     (0U)
#define TIMER_TPLCR_LEN     (2U)
#define TIMER_TPLCR_MSK     (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK    (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))

/* 0x60 : TPLCR3 */
#define TIMER_TPLCR3_OFFSET (0x60)
#define TIMER_TPLCR         TIMER_TPLCR
#define TIMER_TPLCR_POS     (0U)
#define TIMER_TPLCR_LEN     (2U)
#define TIMER_TPLCR_MSK     (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK    (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))

/* 0x64 : WMER */
#define TIMER_WMER_OFFSET (0x64)
#define TIMER_WE          TIMER_WE
#define TIMER_WE_POS      (0U)
#define TIMER_WE_LEN      (1U)
#define TIMER_WE_MSK      (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)
#define TIMER_WE_UMSK     (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS))
#define TIMER_WRIE        TIMER_WRIE
#define TIMER_WRIE_POS    (1U)
#define TIMER_WRIE_LEN    (1U)
#define TIMER_WRIE_MSK    (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)
#define TIMER_WRIE_UMSK   (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS))

/* 0x68 : WMR */
#define TIMER_WMR_OFFSET (0x68)
#define TIMER_WMR        TIMER_WMR
#define TIMER_WMR_POS    (0U)
#define TIMER_WMR_LEN    (16U)
#define TIMER_WMR_MSK    (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)
#define TIMER_WMR_UMSK   (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS))

/* 0x6C : WVR */
#define TIMER_WVR_OFFSET (0x6C)
#define TIMER_WVR        TIMER_WVR
#define TIMER_WVR_POS    (0U)
#define TIMER_WVR_LEN    (16U)
#define TIMER_WVR_MSK    (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)
#define TIMER_WVR_UMSK   (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS))

/* 0x70 : WSR */
#define TIMER_WSR_OFFSET (0x70)
#define TIMER_WTS        TIMER_WTS
#define TIMER_WTS_POS    (0U)
#define TIMER_WTS_LEN    (1U)
#define TIMER_WTS_MSK    (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)
#define TIMER_WTS_UMSK   (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS))

/* 0x78 : TICR2 */
#define TIMER_TICR2_OFFSET (0x78)
#define TIMER_TCLR_0       TIMER_TCLR_0
#define TIMER_TCLR_0_POS   (0U)
#define TIMER_TCLR_0_LEN   (1U)
#define TIMER_TCLR_0_MSK   (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK  (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1       TIMER_TCLR_1
#define TIMER_TCLR_1_POS   (1U)
#define TIMER_TCLR_1_LEN   (1U)
#define TIMER_TCLR_1_MSK   (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK  (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2       TIMER_TCLR_2
#define TIMER_TCLR_2_POS   (2U)
#define TIMER_TCLR_2_LEN   (1U)
#define TIMER_TCLR_2_MSK   (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK  (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))

/* 0x7C : TICR3 */
#define TIMER_TICR3_OFFSET (0x7C)
#define TIMER_TCLR_0       TIMER_TCLR_0
#define TIMER_TCLR_0_POS   (0U)
#define TIMER_TCLR_0_LEN   (1U)
#define TIMER_TCLR_0_MSK   (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK  (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
#define TIMER_TCLR_1       TIMER_TCLR_1
#define TIMER_TCLR_1_POS   (1U)
#define TIMER_TCLR_1_LEN   (1U)
#define TIMER_TCLR_1_MSK   (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK  (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
#define TIMER_TCLR_2       TIMER_TCLR_2
#define TIMER_TCLR_2_POS   (2U)
#define TIMER_TCLR_2_LEN   (1U)
#define TIMER_TCLR_2_MSK   (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK  (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))

/* 0x80 : WICR */
#define TIMER_WICR_OFFSET (0x80)
#define TIMER_WICLR       TIMER_WICLR
#define TIMER_WICLR_POS   (0U)
#define TIMER_WICLR_LEN   (1U)
#define TIMER_WICLR_MSK   (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)
#define TIMER_WICLR_UMSK  (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS))

/* 0x84 : TCER */
#define TIMER_TCER_OFFSET (0x84)
#define TIMER2_EN         TIMER2_EN
#define TIMER2_EN_POS     (1U)
#define TIMER2_EN_LEN     (1U)
#define TIMER2_EN_MSK     (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)
#define TIMER2_EN_UMSK    (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS))
#define TIMER3_EN         TIMER3_EN
#define TIMER3_EN_POS     (2U)
#define TIMER3_EN_LEN     (1U)
#define TIMER3_EN_MSK     (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)
#define TIMER3_EN_UMSK    (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS))

/* 0x88 : TCMR */
#define TIMER_TCMR_OFFSET (0x88)
#define TIMER2_MODE       TIMER2_MODE
#define TIMER2_MODE_POS   (1U)
#define TIMER2_MODE_LEN   (1U)
#define TIMER2_MODE_MSK   (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)
#define TIMER2_MODE_UMSK  (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS))
#define TIMER3_MODE       TIMER3_MODE
#define TIMER3_MODE_POS   (2U)
#define TIMER3_MODE_LEN   (1U)
#define TIMER3_MODE_MSK   (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)
#define TIMER3_MODE_UMSK  (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS))

/* 0x90 : TILR2 */
#define TIMER_TILR2_OFFSET (0x90)
#define TIMER_TILR_0       TIMER_TILR_0
#define TIMER_TILR_0_POS   (0U)
#define TIMER_TILR_0_LEN   (1U)
#define TIMER_TILR_0_MSK   (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK  (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1       TIMER_TILR_1
#define TIMER_TILR_1_POS   (1U)
#define TIMER_TILR_1_LEN   (1U)
#define TIMER_TILR_1_MSK   (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK  (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2       TIMER_TILR_2
#define TIMER_TILR_2_POS   (2U)
#define TIMER_TILR_2_LEN   (1U)
#define TIMER_TILR_2_MSK   (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK  (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))

/* 0x94 : TILR3 */
#define TIMER_TILR3_OFFSET (0x94)
#define TIMER_TILR_0       TIMER_TILR_0
#define TIMER_TILR_0_POS   (0U)
#define TIMER_TILR_0_LEN   (1U)
#define TIMER_TILR_0_MSK   (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK  (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
#define TIMER_TILR_1       TIMER_TILR_1
#define TIMER_TILR_1_POS   (1U)
#define TIMER_TILR_1_LEN   (1U)
#define TIMER_TILR_1_MSK   (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK  (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
#define TIMER_TILR_2       TIMER_TILR_2
#define TIMER_TILR_2_POS   (2U)
#define TIMER_TILR_2_LEN   (1U)
#define TIMER_TILR_2_MSK   (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK  (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))

/* 0x98 : WCR */
#define TIMER_WCR_OFFSET (0x98)
#define TIMER_WCR        TIMER_WCR
#define TIMER_WCR_POS    (0U)
#define TIMER_WCR_LEN    (1U)
#define TIMER_WCR_MSK    (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)
#define TIMER_WCR_UMSK   (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS))

/* 0x9C : WFAR */
#define TIMER_WFAR_OFFSET (0x9C)
#define TIMER_WFAR        TIMER_WFAR
#define TIMER_WFAR_POS    (0U)
#define TIMER_WFAR_LEN    (16U)
#define TIMER_WFAR_MSK    (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)
#define TIMER_WFAR_UMSK   (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS))

/* 0xA0 : WSAR */
#define TIMER_WSAR_OFFSET (0xA0)
#define TIMER_WSAR        TIMER_WSAR
#define TIMER_WSAR_POS    (0U)
#define TIMER_WSAR_LEN    (16U)
#define TIMER_WSAR_MSK    (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)
#define TIMER_WSAR_UMSK   (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS))

/* 0xA8 : TCVWR2 */
#define TIMER_TCVWR2_OFFSET (0xA8)
#define TIMER_TCVWR         TIMER_TCVWR
#define TIMER_TCVWR_POS     (0U)
#define TIMER_TCVWR_LEN     (32U)
#define TIMER_TCVWR_MSK     (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK    (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))

/* 0xAC : TCVWR3 */
#define TIMER_TCVWR3_OFFSET (0xAC)
#define TIMER_TCVWR         TIMER_TCVWR
#define TIMER_TCVWR_POS     (0U)
#define TIMER_TCVWR_LEN     (32U)
#define TIMER_TCVWR_MSK     (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK    (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))

/* 0xB4 : TCVSYN2 */
#define TIMER_TCVSYN2_OFFSET (0xB4)
#define TIMER_TCVSYN2        TIMER_TCVSYN2
#define TIMER_TCVSYN2_POS    (0U)
#define TIMER_TCVSYN2_LEN    (32U)
#define TIMER_TCVSYN2_MSK    (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)
#define TIMER_TCVSYN2_UMSK   (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS))

/* 0xB8 : TCVSYN3 */
#define TIMER_TCVSYN3_OFFSET (0xB8)
#define TIMER_TCVSYN3        TIMER_TCVSYN3
#define TIMER_TCVSYN3_POS    (0U)
#define TIMER_TCVSYN3_LEN    (32U)
#define TIMER_TCVSYN3_MSK    (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)
#define TIMER_TCVSYN3_UMSK   (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS))

/* 0xBC : TCDR */
#define TIMER_TCDR_OFFSET (0xBC)
#define TIMER_TCDR2       TIMER_TCDR2
#define TIMER_TCDR2_POS   (8U)
#define TIMER_TCDR2_LEN   (8U)
#define TIMER_TCDR2_MSK   (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)
#define TIMER_TCDR2_UMSK  (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS))
#define TIMER_TCDR3       TIMER_TCDR3
#define TIMER_TCDR3_POS   (16U)
#define TIMER_TCDR3_LEN   (8U)
#define TIMER_TCDR3_MSK   (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)
#define TIMER_TCDR3_UMSK  (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS))
#define TIMER_WCDR        TIMER_WCDR
#define TIMER_WCDR_POS    (24U)
#define TIMER_WCDR_LEN    (8U)
#define TIMER_WCDR_MSK    (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
#define TIMER_WCDR_UMSK   (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))

struct timer_reg {
    /* 0x0 : TCCR */
    union {
        struct
        {
            uint32_t reserved_0_1   : 2;  /* [ 1: 0],       rsvd,        0x0 */
            uint32_t cs_1           : 2;  /* [ 3: 2],        r/w,        0x0 */
            uint32_t RESERVED_4     : 1;  /* [    4],       rsvd,        0x0 */
            uint32_t cs_2           : 2;  /* [ 6: 5],        r/w,        0x0 */
            uint32_t RESERVED_7     : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t cs_wdt         : 2;  /* [ 9: 8],        r/w,        0x0 */
            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TCCR;

    /* 0x4  reserved */
    uint8_t RESERVED0x4[12];

    /* 0x10 : TMR2_0 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR2_0;

    /* 0x14 : TMR2_1 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR2_1;

    /* 0x18 : TMR2_2 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR2_2;

    /* 0x1C : TMR3_0 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR3_0;

    /* 0x20 : TMR3_1 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR3_1;

    /* 0x24 : TMR3_2 */
    union {
        struct
        {
            uint32_t tmr : 32; /* [31: 0],        r/w, 0xffffffffL */
        } BF;
        uint32_t WORD;
    } TMR3_2;

    /* 0x28  reserved */
    uint8_t RESERVED0x28[4];

    /* 0x2C : TCR2 */
    union {
        struct
        {
            uint32_t tcr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCR2;

    /* 0x30 : TCR3 */
    union {
        struct
        {
            uint32_t tcr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCR3;

    /* 0x34  reserved */
    uint8_t RESERVED0x34[4];

    /* 0x38 : TMSR2 */
    union {
        struct
        {
            uint32_t tmsr_0        : 1;  /* [    0],          r,        0x0 */
            uint32_t tmsr_1        : 1;  /* [    1],          r,        0x0 */
            uint32_t tmsr_2        : 1;  /* [    2],          r,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TMSR2;

    /* 0x3C : TMSR3 */
    union {
        struct
        {
            uint32_t tmsr_0        : 1;  /* [    0],          r,        0x0 */
            uint32_t tmsr_1        : 1;  /* [    1],          r,        0x0 */
            uint32_t tmsr_2        : 1;  /* [    2],          r,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TMSR3;

    /* 0x40  reserved */
    uint8_t RESERVED0x40[4];

    /* 0x44 : TIER2 */
    union {
        struct
        {
            uint32_t tier_0        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t tier_1        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tier_2        : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TIER2;

    /* 0x48 : TIER3 */
    union {
        struct
        {
            uint32_t tier_0        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t tier_1        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tier_2        : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TIER3;

    /* 0x4c  reserved */
    uint8_t RESERVED0x4c[4];

    /* 0x50 : TPLVR2 */
    union {
        struct
        {
            uint32_t tplvr : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } TPLVR2;

    /* 0x54 : TPLVR3 */
    union {
        struct
        {
            uint32_t tplvr : 32; /* [31: 0],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } TPLVR3;

    /* 0x58  reserved */
    uint8_t RESERVED0x58[4];

    /* 0x5C : TPLCR2 */
    union {
        struct
        {
            uint32_t tplcr         : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TPLCR2;

    /* 0x60 : TPLCR3 */
    union {
        struct
        {
            uint32_t tplcr         : 2;  /* [ 1: 0],        r/w,        0x0 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TPLCR3;

    /* 0x64 : WMER */
    union {
        struct
        {
            uint32_t we            : 1;  /* [    0],        r/w,        0x0 */
            uint32_t wrie          : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WMER;

    /* 0x68 : WMR */
    union {
        struct
        {
            uint32_t wmr            : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WMR;

    /* 0x6C : WVR */
    union {
        struct
        {
            uint32_t wvr            : 16; /* [15: 0],          r,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WVR;

    /* 0x70 : WSR */
    union {
        struct
        {
            uint32_t wts           : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WSR;

    /* 0x74  reserved */
    uint8_t RESERVED0x74[4];

    /* 0x78 : TICR2 */
    union {
        struct
        {
            uint32_t tclr_0        : 1;  /* [    0],          w,        0x0 */
            uint32_t tclr_1        : 1;  /* [    1],          w,        0x0 */
            uint32_t tclr_2        : 1;  /* [    2],          w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TICR2;

    /* 0x7C : TICR3 */
    union {
        struct
        {
            uint32_t tclr_0        : 1;  /* [    0],          w,        0x0 */
            uint32_t tclr_1        : 1;  /* [    1],          w,        0x0 */
            uint32_t tclr_2        : 1;  /* [    2],          w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TICR3;

    /* 0x80 : WICR */
    union {
        struct
        {
            uint32_t wiclr         : 1;  /* [    0],          w,        0x0 */
            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WICR;

    /* 0x84 : TCER */
    union {
        struct
        {
            uint32_t reserved_0    : 1;  /* [    0],       rsvd,        0x0 */
            uint32_t timer2_en     : 1;  /* [    1],        r/w,        0x0 */
            uint32_t timer3_en     : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TCER;

    /* 0x88 : TCMR */
    union {
        struct
        {
            uint32_t reserved_0    : 1;  /* [    0],       rsvd,        0x0 */
            uint32_t timer2_mode   : 1;  /* [    1],        r/w,        0x0 */
            uint32_t timer3_mode   : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TCMR;

    /* 0x8c  reserved */
    uint8_t RESERVED0x8c[4];

    /* 0x90 : TILR2 */
    union {
        struct
        {
            uint32_t tilr_0        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t tilr_1        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tilr_2        : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TILR2;

    /* 0x94 : TILR3 */
    union {
        struct
        {
            uint32_t tilr_0        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t tilr_1        : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tilr_2        : 1;  /* [    2],        r/w,        0x0 */
            uint32_t reserved_3_31 : 29; /* [31: 3],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } TILR3;

    /* 0x98 : WCR */
    union {
        struct
        {
            uint32_t wcr           : 1;  /* [    0],          w,        0x0 */
            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WCR;

    /* 0x9C : WFAR */
    union {
        struct
        {
            uint32_t wfar           : 16; /* [15: 0],          w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WFAR;

    /* 0xA0 : WSAR */
    union {
        struct
        {
            uint32_t wsar           : 16; /* [15: 0],          w,        0x0 */
            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } WSAR;

    /* 0xa4  reserved */
    uint8_t RESERVED0xa4[4];

    /* 0xA8 : TCVWR2 */
    union {
        struct
        {
            uint32_t tcvwr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCVWR2;

    /* 0xAC : TCVWR3 */
    union {
        struct
        {
            uint32_t tcvwr : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCVWR3;

    /* 0xb0  reserved */
    uint8_t RESERVED0xb0[4];

    /* 0xB4 : TCVSYN2 */
    union {
        struct
        {
            uint32_t tcvsyn2 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCVSYN2;

    /* 0xB8 : TCVSYN3 */
    union {
        struct
        {
            uint32_t tcvsyn3 : 32; /* [31: 0],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } TCVSYN3;

    /* 0xBC : TCDR */
    union {
        struct
        {
            uint32_t reserved_0_7 : 8; /* [ 7: 0],       rsvd,        0x0 */
            uint32_t tcdr2        : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t tcdr3        : 8; /* [23:16],        r/w,        0x0 */
            uint32_t wcdr         : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } TCDR;
};

typedef volatile struct timer_reg timer_reg_t;

#endif /* __TIMER_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/tzc_sec_reg.h
================================================
/**
  ******************************************************************************
  * @file    tzc_sec_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __TZC_SEC_REG_H__
#define __TZC_SEC_REG_H__

#include "bl702.h"

/* 0x40 : tzc_rom_ctrl */
#define TZC_SEC_TZC_ROM_CTRL_OFFSET     (0x40)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN      TZC_SEC_TZC_ROM0_R0_ID0_EN
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS  (0U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID0_EN      TZC_SEC_TZC_ROM0_R1_ID0_EN
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS  (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID0_EN      TZC_SEC_TZC_ROM1_R0_ID0_EN
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS  (2U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID0_EN      TZC_SEC_TZC_ROM1_R1_ID0_EN
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS  (3U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_ID1_EN      TZC_SEC_TZC_ROM0_R0_ID1_EN
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS  (8U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID1_EN      TZC_SEC_TZC_ROM0_R1_ID1_EN
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS  (9U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID1_EN      TZC_SEC_TZC_ROM1_R0_ID1_EN
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS  (10U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID1_EN      TZC_SEC_TZC_ROM1_R1_ID1_EN
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS  (11U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN  (1U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_EN          TZC_SEC_TZC_ROM0_R0_EN
#define TZC_SEC_TZC_ROM0_R0_EN_POS      (16U)
#define TZC_SEC_TZC_ROM0_R0_EN_LEN      (1U)
#define TZC_SEC_TZC_ROM0_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_EN          TZC_SEC_TZC_ROM0_R1_EN
#define TZC_SEC_TZC_ROM0_R1_EN_POS      (17U)
#define TZC_SEC_TZC_ROM0_R1_EN_LEN      (1U)
#define TZC_SEC_TZC_ROM0_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_EN          TZC_SEC_TZC_ROM1_R0_EN
#define TZC_SEC_TZC_ROM1_R0_EN_POS      (18U)
#define TZC_SEC_TZC_ROM1_R0_EN_LEN      (1U)
#define TZC_SEC_TZC_ROM1_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_EN          TZC_SEC_TZC_ROM1_R1_EN
#define TZC_SEC_TZC_ROM1_R1_EN_POS      (19U)
#define TZC_SEC_TZC_ROM1_R1_EN_LEN      (1U)
#define TZC_SEC_TZC_ROM1_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_LOCK        TZC_SEC_TZC_ROM0_R0_LOCK
#define TZC_SEC_TZC_ROM0_R0_LOCK_POS    (24U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN    (1U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM0_R1_LOCK        TZC_SEC_TZC_ROM0_R1_LOCK
#define TZC_SEC_TZC_ROM0_R1_LOCK_POS    (25U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN    (1U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R0_LOCK        TZC_SEC_TZC_ROM1_R0_LOCK
#define TZC_SEC_TZC_ROM1_R0_LOCK_POS    (26U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN    (1U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R1_LOCK        TZC_SEC_TZC_ROM1_R1_LOCK
#define TZC_SEC_TZC_ROM1_R1_LOCK_POS    (27U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN    (1U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
#define TZC_SEC_TZC_SBOOT_DONE          TZC_SEC_TZC_SBOOT_DONE
#define TZC_SEC_TZC_SBOOT_DONE_POS      (28U)
#define TZC_SEC_TZC_SBOOT_DONE_LEN      (4U)
#define TZC_SEC_TZC_SBOOT_DONE_MSK      (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
#define TZC_SEC_TZC_SBOOT_DONE_UMSK     (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))

/* 0x44 : tzc_rom0_r0 */
#define TZC_SEC_TZC_ROM0_R0_OFFSET     (0x44)
#define TZC_SEC_TZC_ROM0_R0_END        TZC_SEC_TZC_ROM0_R0_END
#define TZC_SEC_TZC_ROM0_R0_END_POS    (0U)
#define TZC_SEC_TZC_ROM0_R0_END_LEN    (16U)
#define TZC_SEC_TZC_ROM0_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
#define TZC_SEC_TZC_ROM0_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
#define TZC_SEC_TZC_ROM0_R0_START      TZC_SEC_TZC_ROM0_R0_START
#define TZC_SEC_TZC_ROM0_R0_START_POS  (16U)
#define TZC_SEC_TZC_ROM0_R0_START_LEN  (16U)
#define TZC_SEC_TZC_ROM0_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))

/* 0x48 : tzc_rom0_r1 */
#define TZC_SEC_TZC_ROM0_R1_OFFSET     (0x48)
#define TZC_SEC_TZC_ROM0_R1_END        TZC_SEC_TZC_ROM0_R1_END
#define TZC_SEC_TZC_ROM0_R1_END_POS    (0U)
#define TZC_SEC_TZC_ROM0_R1_END_LEN    (16U)
#define TZC_SEC_TZC_ROM0_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
#define TZC_SEC_TZC_ROM0_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
#define TZC_SEC_TZC_ROM0_R1_START      TZC_SEC_TZC_ROM0_R1_START
#define TZC_SEC_TZC_ROM0_R1_START_POS  (16U)
#define TZC_SEC_TZC_ROM0_R1_START_LEN  (16U)
#define TZC_SEC_TZC_ROM0_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))

/* 0x4C : tzc_rom1_r0 */
#define TZC_SEC_TZC_ROM1_R0_OFFSET     (0x4C)
#define TZC_SEC_TZC_ROM1_R0_END        TZC_SEC_TZC_ROM1_R0_END
#define TZC_SEC_TZC_ROM1_R0_END_POS    (0U)
#define TZC_SEC_TZC_ROM1_R0_END_LEN    (16U)
#define TZC_SEC_TZC_ROM1_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
#define TZC_SEC_TZC_ROM1_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
#define TZC_SEC_TZC_ROM1_R0_START      TZC_SEC_TZC_ROM1_R0_START
#define TZC_SEC_TZC_ROM1_R0_START_POS  (16U)
#define TZC_SEC_TZC_ROM1_R0_START_LEN  (16U)
#define TZC_SEC_TZC_ROM1_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))

/* 0x50 : tzc_rom1_r1 */
#define TZC_SEC_TZC_ROM1_R1_OFFSET     (0x50)
#define TZC_SEC_TZC_ROM1_R1_END        TZC_SEC_TZC_ROM1_R1_END
#define TZC_SEC_TZC_ROM1_R1_END_POS    (0U)
#define TZC_SEC_TZC_ROM1_R1_END_LEN    (16U)
#define TZC_SEC_TZC_ROM1_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
#define TZC_SEC_TZC_ROM1_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
#define TZC_SEC_TZC_ROM1_R1_START      TZC_SEC_TZC_ROM1_R1_START
#define TZC_SEC_TZC_ROM1_R1_START_POS  (16U)
#define TZC_SEC_TZC_ROM1_R1_START_LEN  (16U)
#define TZC_SEC_TZC_ROM1_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))

struct tzc_sec_reg {
    /* 0x0  reserved */
    uint8_t RESERVED0x0[64];

    /* 0x40 : tzc_rom_ctrl */
    union {
        struct
        {
            uint32_t tzc_rom0_r0_id0_en : 1; /* [    0],        r/w,        0x1 */
            uint32_t tzc_rom0_r1_id0_en : 1; /* [    1],        r/w,        0x1 */
            uint32_t tzc_rom1_r0_id0_en : 1; /* [    2],        r/w,        0x1 */
            uint32_t tzc_rom1_r1_id0_en : 1; /* [    3],        r/w,        0x1 */
            uint32_t reserved_4_7       : 4; /* [ 7: 4],       rsvd,        0x0 */
            uint32_t tzc_rom0_r0_id1_en : 1; /* [    8],        r/w,        0x1 */
            uint32_t tzc_rom0_r1_id1_en : 1; /* [    9],        r/w,        0x1 */
            uint32_t tzc_rom1_r0_id1_en : 1; /* [   10],        r/w,        0x1 */
            uint32_t tzc_rom1_r1_id1_en : 1; /* [   11],        r/w,        0x1 */
            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
            uint32_t tzc_rom0_r0_en     : 1; /* [   16],        r/w,        0x0 */
            uint32_t tzc_rom0_r1_en     : 1; /* [   17],        r/w,        0x0 */
            uint32_t tzc_rom1_r0_en     : 1; /* [   18],        r/w,        0x0 */
            uint32_t tzc_rom1_r1_en     : 1; /* [   19],        r/w,        0x0 */
            uint32_t reserved_20_23     : 4; /* [23:20],       rsvd,        0x0 */
            uint32_t tzc_rom0_r0_lock   : 1; /* [   24],        r/w,        0x0 */
            uint32_t tzc_rom0_r1_lock   : 1; /* [   25],        r/w,        0x0 */
            uint32_t tzc_rom1_r0_lock   : 1; /* [   26],        r/w,        0x0 */
            uint32_t tzc_rom1_r1_lock   : 1; /* [   27],        r/w,        0x0 */
            uint32_t tzc_sboot_done     : 4; /* [31:28],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_rom_ctrl;

    /* 0x44 : tzc_rom0_r0 */
    union {
        struct
        {
            uint32_t tzc_rom0_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t tzc_rom0_r0_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_rom0_r0;

    /* 0x48 : tzc_rom0_r1 */
    union {
        struct
        {
            uint32_t tzc_rom0_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t tzc_rom0_r1_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_rom0_r1;

    /* 0x4C : tzc_rom1_r0 */
    union {
        struct
        {
            uint32_t tzc_rom1_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t tzc_rom1_r0_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_rom1_r0;

    /* 0x50 : tzc_rom1_r1 */
    union {
        struct
        {
            uint32_t tzc_rom1_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
            uint32_t tzc_rom1_r1_start : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } tzc_rom1_r1;
};

typedef volatile struct tzc_sec_reg tzc_sec_reg_t;

#endif /* __TZC_SEC_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/uart_reg.h
================================================
/**
  ******************************************************************************
  * @file    uart_reg.h
  * @version V1.2
  * @date    2020-03-30
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __UART_REG_H__
#define __UART_REG_H__

#include "bl702.h"

/* 0x0 : utx_config */
#define UART_UTX_CONFIG_OFFSET     (0x0)
#define UART_CR_UTX_EN             UART_CR_UTX_EN
#define UART_CR_UTX_EN_POS         (0U)
#define UART_CR_UTX_EN_LEN         (1U)
#define UART_CR_UTX_EN_MSK         (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)
#define UART_CR_UTX_EN_UMSK        (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS))
#define UART_CR_UTX_CTS_EN         UART_CR_UTX_CTS_EN
#define UART_CR_UTX_CTS_EN_POS     (1U)
#define UART_CR_UTX_CTS_EN_LEN     (1U)
#define UART_CR_UTX_CTS_EN_MSK     (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)
#define UART_CR_UTX_CTS_EN_UMSK    (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS))
#define UART_CR_UTX_FRM_EN         UART_CR_UTX_FRM_EN
#define UART_CR_UTX_FRM_EN_POS     (2U)
#define UART_CR_UTX_FRM_EN_LEN     (1U)
#define UART_CR_UTX_FRM_EN_MSK     (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)
#define UART_CR_UTX_FRM_EN_UMSK    (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS))
#define UART_CR_UTX_LIN_EN         UART_CR_UTX_LIN_EN
#define UART_CR_UTX_LIN_EN_POS     (3U)
#define UART_CR_UTX_LIN_EN_LEN     (1U)
#define UART_CR_UTX_LIN_EN_MSK     (((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS)
#define UART_CR_UTX_LIN_EN_UMSK    (~(((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS))
#define UART_CR_UTX_PRT_EN         UART_CR_UTX_PRT_EN
#define UART_CR_UTX_PRT_EN_POS     (4U)
#define UART_CR_UTX_PRT_EN_LEN     (1U)
#define UART_CR_UTX_PRT_EN_MSK     (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)
#define UART_CR_UTX_PRT_EN_UMSK    (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS))
#define UART_CR_UTX_PRT_SEL        UART_CR_UTX_PRT_SEL
#define UART_CR_UTX_PRT_SEL_POS    (5U)
#define UART_CR_UTX_PRT_SEL_LEN    (1U)
#define UART_CR_UTX_PRT_SEL_MSK    (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)
#define UART_CR_UTX_PRT_SEL_UMSK   (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS))
#define UART_CR_UTX_IR_EN          UART_CR_UTX_IR_EN
#define UART_CR_UTX_IR_EN_POS      (6U)
#define UART_CR_UTX_IR_EN_LEN      (1U)
#define UART_CR_UTX_IR_EN_MSK      (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)
#define UART_CR_UTX_IR_EN_UMSK     (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS))
#define UART_CR_UTX_IR_INV         UART_CR_UTX_IR_INV
#define UART_CR_UTX_IR_INV_POS     (7U)
#define UART_CR_UTX_IR_INV_LEN     (1U)
#define UART_CR_UTX_IR_INV_MSK     (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)
#define UART_CR_UTX_IR_INV_UMSK    (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS))
#define UART_CR_UTX_BIT_CNT_D      UART_CR_UTX_BIT_CNT_D
#define UART_CR_UTX_BIT_CNT_D_POS  (8U)
#define UART_CR_UTX_BIT_CNT_D_LEN  (3U)
#define UART_CR_UTX_BIT_CNT_D_MSK  (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)
#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS))
#define UART_CR_UTX_BIT_CNT_P      UART_CR_UTX_BIT_CNT_P
#define UART_CR_UTX_BIT_CNT_P_POS  (11U)
#define UART_CR_UTX_BIT_CNT_P_LEN  (2U)
#define UART_CR_UTX_BIT_CNT_P_MSK  (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)
#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS))
#define UART_CR_UTX_BIT_CNT_B      UART_CR_UTX_BIT_CNT_B
#define UART_CR_UTX_BIT_CNT_B_POS  (13U)
#define UART_CR_UTX_BIT_CNT_B_LEN  (3U)
#define UART_CR_UTX_BIT_CNT_B_MSK  (((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS)
#define UART_CR_UTX_BIT_CNT_B_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS))
#define UART_CR_UTX_LEN            UART_CR_UTX_LEN
#define UART_CR_UTX_LEN_POS        (16U)
#define UART_CR_UTX_LEN_LEN        (16U)
#define UART_CR_UTX_LEN_MSK        (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)
#define UART_CR_UTX_LEN_UMSK       (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS))

/* 0x4 : urx_config */
#define UART_URX_CONFIG_OFFSET     (0x4)
#define UART_CR_URX_EN             UART_CR_URX_EN
#define UART_CR_URX_EN_POS         (0U)
#define UART_CR_URX_EN_LEN         (1U)
#define UART_CR_URX_EN_MSK         (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)
#define UART_CR_URX_EN_UMSK        (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS))
#define UART_CR_URX_ABR_EN         UART_CR_URX_ABR_EN
#define UART_CR_URX_ABR_EN_POS     (1U)
#define UART_CR_URX_ABR_EN_LEN     (1U)
#define UART_CR_URX_ABR_EN_MSK     (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)
#define UART_CR_URX_ABR_EN_UMSK    (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS))
#define UART_CR_URX_LIN_EN         UART_CR_URX_LIN_EN
#define UART_CR_URX_LIN_EN_POS     (3U)
#define UART_CR_URX_LIN_EN_LEN     (1U)
#define UART_CR_URX_LIN_EN_MSK     (((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS)
#define UART_CR_URX_LIN_EN_UMSK    (~(((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS))
#define UART_CR_URX_PRT_EN         UART_CR_URX_PRT_EN
#define UART_CR_URX_PRT_EN_POS     (4U)
#define UART_CR_URX_PRT_EN_LEN     (1U)
#define UART_CR_URX_PRT_EN_MSK     (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)
#define UART_CR_URX_PRT_EN_UMSK    (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS))
#define UART_CR_URX_PRT_SEL        UART_CR_URX_PRT_SEL
#define UART_CR_URX_PRT_SEL_POS    (5U)
#define UART_CR_URX_PRT_SEL_LEN    (1U)
#define UART_CR_URX_PRT_SEL_MSK    (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)
#define UART_CR_URX_PRT_SEL_UMSK   (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS))
#define UART_CR_URX_IR_EN          UART_CR_URX_IR_EN
#define UART_CR_URX_IR_EN_POS      (6U)
#define UART_CR_URX_IR_EN_LEN      (1U)
#define UART_CR_URX_IR_EN_MSK      (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)
#define UART_CR_URX_IR_EN_UMSK     (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS))
#define UART_CR_URX_IR_INV         UART_CR_URX_IR_INV
#define UART_CR_URX_IR_INV_POS     (7U)
#define UART_CR_URX_IR_INV_LEN     (1U)
#define UART_CR_URX_IR_INV_MSK     (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)
#define UART_CR_URX_IR_INV_UMSK    (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS))
#define UART_CR_URX_BIT_CNT_D      UART_CR_URX_BIT_CNT_D
#define UART_CR_URX_BIT_CNT_D_POS  (8U)
#define UART_CR_URX_BIT_CNT_D_LEN  (3U)
#define UART_CR_URX_BIT_CNT_D_MSK  (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)
#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS))
#define UART_CR_URX_DEG_EN         UART_CR_URX_DEG_EN
#define UART_CR_URX_DEG_EN_POS     (11U)
#define UART_CR_URX_DEG_EN_LEN     (1U)
#define UART_CR_URX_DEG_EN_MSK     (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)
#define UART_CR_URX_DEG_EN_UMSK    (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS))
#define UART_CR_URX_DEG_CNT        UART_CR_URX_DEG_CNT
#define UART_CR_URX_DEG_CNT_POS    (12U)
#define UART_CR_URX_DEG_CNT_LEN    (4U)
#define UART_CR_URX_DEG_CNT_MSK    (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)
#define UART_CR_URX_DEG_CNT_UMSK   (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS))
#define UART_CR_URX_LEN            UART_CR_URX_LEN
#define UART_CR_URX_LEN_POS        (16U)
#define UART_CR_URX_LEN_LEN        (16U)
#define UART_CR_URX_LEN_MSK        (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)
#define UART_CR_URX_LEN_UMSK       (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS))

/* 0x8 : uart_bit_prd */
#define UART_BIT_PRD_OFFSET      (0x8)
#define UART_CR_UTX_BIT_PRD      UART_CR_UTX_BIT_PRD
#define UART_CR_UTX_BIT_PRD_POS  (0U)
#define UART_CR_UTX_BIT_PRD_LEN  (16U)
#define UART_CR_UTX_BIT_PRD_MSK  (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)
#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS))
#define UART_CR_URX_BIT_PRD      UART_CR_URX_BIT_PRD
#define UART_CR_URX_BIT_PRD_POS  (16U)
#define UART_CR_URX_BIT_PRD_LEN  (16U)
#define UART_CR_URX_BIT_PRD_MSK  (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)
#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS))

/* 0xC : data_config */
#define UART_DATA_CONFIG_OFFSET   (0xC)
#define UART_CR_UART_BIT_INV      UART_CR_UART_BIT_INV
#define UART_CR_UART_BIT_INV_POS  (0U)
#define UART_CR_UART_BIT_INV_LEN  (1U)
#define UART_CR_UART_BIT_INV_MSK  (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)
#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS))

/* 0x10 : utx_ir_position */
#define UART_UTX_IR_POSITION_OFFSET (0x10)
#define UART_CR_UTX_IR_POS_S        UART_CR_UTX_IR_POS_S
#define UART_CR_UTX_IR_POS_S_POS    (0U)
#define UART_CR_UTX_IR_POS_S_LEN    (16U)
#define UART_CR_UTX_IR_POS_S_MSK    (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)
#define UART_CR_UTX_IR_POS_S_UMSK   (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS))
#define UART_CR_UTX_IR_POS_P        UART_CR_UTX_IR_POS_P
#define UART_CR_UTX_IR_POS_P_POS    (16U)
#define UART_CR_UTX_IR_POS_P_LEN    (16U)
#define UART_CR_UTX_IR_POS_P_MSK    (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)
#define UART_CR_UTX_IR_POS_P_UMSK   (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS))

/* 0x14 : urx_ir_position */
#define UART_URX_IR_POSITION_OFFSET (0x14)
#define UART_CR_URX_IR_POS_S        UART_CR_URX_IR_POS_S
#define UART_CR_URX_IR_POS_S_POS    (0U)
#define UART_CR_URX_IR_POS_S_LEN    (16U)
#define UART_CR_URX_IR_POS_S_MSK    (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)
#define UART_CR_URX_IR_POS_S_UMSK   (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS))

/* 0x18 : urx_rto_timer */
#define UART_URX_RTO_TIMER_OFFSET  (0x18)
#define UART_CR_URX_RTO_VALUE      UART_CR_URX_RTO_VALUE
#define UART_CR_URX_RTO_VALUE_POS  (0U)
#define UART_CR_URX_RTO_VALUE_LEN  (8U)
#define UART_CR_URX_RTO_VALUE_MSK  (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)
#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS))

/* 0x1C : uart_sw_mode */
#define UART_SW_MODE_OFFSET          (0x1C)
#define UART_CR_UTX_TXD_SW_MODE      UART_CR_UTX_TXD_SW_MODE
#define UART_CR_UTX_TXD_SW_MODE_POS  (0U)
#define UART_CR_UTX_TXD_SW_MODE_LEN  (1U)
#define UART_CR_UTX_TXD_SW_MODE_MSK  (((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS)
#define UART_CR_UTX_TXD_SW_MODE_UMSK (~(((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS))
#define UART_CR_UTX_TXD_SW_VAL       UART_CR_UTX_TXD_SW_VAL
#define UART_CR_UTX_TXD_SW_VAL_POS   (1U)
#define UART_CR_UTX_TXD_SW_VAL_LEN   (1U)
#define UART_CR_UTX_TXD_SW_VAL_MSK   (((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS)
#define UART_CR_UTX_TXD_SW_VAL_UMSK  (~(((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS))
#define UART_CR_URX_RTS_SW_MODE      UART_CR_URX_RTS_SW_MODE
#define UART_CR_URX_RTS_SW_MODE_POS  (2U)
#define UART_CR_URX_RTS_SW_MODE_LEN  (1U)
#define UART_CR_URX_RTS_SW_MODE_MSK  (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)
#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS))
#define UART_CR_URX_RTS_SW_VAL       UART_CR_URX_RTS_SW_VAL
#define UART_CR_URX_RTS_SW_VAL_POS   (3U)
#define UART_CR_URX_RTS_SW_VAL_LEN   (1U)
#define UART_CR_URX_RTS_SW_VAL_MSK   (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)
#define UART_CR_URX_RTS_SW_VAL_UMSK  (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS))

/* 0x20 : UART interrupt status */
#define UART_INT_STS_OFFSET    (0x20)
#define UART_UTX_END_INT       UART_UTX_END_INT
#define UART_UTX_END_INT_POS   (0U)
#define UART_UTX_END_INT_LEN   (1U)
#define UART_UTX_END_INT_MSK   (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)
#define UART_UTX_END_INT_UMSK  (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS))
#define UART_URX_END_INT       UART_URX_END_INT
#define UART_URX_END_INT_POS   (1U)
#define UART_URX_END_INT_LEN   (1U)
#define UART_URX_END_INT_MSK   (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)
#define UART_URX_END_INT_UMSK  (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS))
#define UART_UTX_FIFO_INT      UART_UTX_FIFO_INT
#define UART_UTX_FIFO_INT_POS  (2U)
#define UART_UTX_FIFO_INT_LEN  (1U)
#define UART_UTX_FIFO_INT_MSK  (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)
#define UART_UTX_FIFO_INT_UMSK (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS))
#define UART_URX_FIFO_INT      UART_URX_FIFO_INT
#define UART_URX_FIFO_INT_POS  (3U)
#define UART_URX_FIFO_INT_LEN  (1U)
#define UART_URX_FIFO_INT_MSK  (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)
#define UART_URX_FIFO_INT_UMSK (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS))
#define UART_URX_RTO_INT       UART_URX_RTO_INT
#define UART_URX_RTO_INT_POS   (4U)
#define UART_URX_RTO_INT_LEN   (1U)
#define UART_URX_RTO_INT_MSK   (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)
#define UART_URX_RTO_INT_UMSK  (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS))
#define UART_URX_PCE_INT       UART_URX_PCE_INT
#define UART_URX_PCE_INT_POS   (5U)
#define UART_URX_PCE_INT_LEN   (1U)
#define UART_URX_PCE_INT_MSK   (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)
#define UART_URX_PCE_INT_UMSK  (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS))
#define UART_UTX_FER_INT       UART_UTX_FER_INT
#define UART_UTX_FER_INT_POS   (6U)
#define UART_UTX_FER_INT_LEN   (1U)
#define UART_UTX_FER_INT_MSK   (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)
#define UART_UTX_FER_INT_UMSK  (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS))
#define UART_URX_FER_INT       UART_URX_FER_INT
#define UART_URX_FER_INT_POS   (7U)
#define UART_URX_FER_INT_LEN   (1U)
#define UART_URX_FER_INT_MSK   (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)
#define UART_URX_FER_INT_UMSK  (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS))
#define UART_URX_LSE_INT       UART_URX_LSE_INT
#define UART_URX_LSE_INT_POS   (8U)
#define UART_URX_LSE_INT_LEN   (1U)
#define UART_URX_LSE_INT_MSK   (((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS)
#define UART_URX_LSE_INT_UMSK  (~(((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS))

/* 0x24 : UART interrupt mask */
#define UART_INT_MASK_OFFSET       (0x24)
#define UART_CR_UTX_END_MASK       UART_CR_UTX_END_MASK
#define UART_CR_UTX_END_MASK_POS   (0U)
#define UART_CR_UTX_END_MASK_LEN   (1U)
#define UART_CR_UTX_END_MASK_MSK   (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)
#define UART_CR_UTX_END_MASK_UMSK  (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS))
#define UART_CR_URX_END_MASK       UART_CR_URX_END_MASK
#define UART_CR_URX_END_MASK_POS   (1U)
#define UART_CR_URX_END_MASK_LEN   (1U)
#define UART_CR_URX_END_MASK_MSK   (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)
#define UART_CR_URX_END_MASK_UMSK  (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS))
#define UART_CR_UTX_FIFO_MASK      UART_CR_UTX_FIFO_MASK
#define UART_CR_UTX_FIFO_MASK_POS  (2U)
#define UART_CR_UTX_FIFO_MASK_LEN  (1U)
#define UART_CR_UTX_FIFO_MASK_MSK  (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)
#define UART_CR_UTX_FIFO_MASK_UMSK (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS))
#define UART_CR_URX_FIFO_MASK      UART_CR_URX_FIFO_MASK
#define UART_CR_URX_FIFO_MASK_POS  (3U)
#define UART_CR_URX_FIFO_MASK_LEN  (1U)
#define UART_CR_URX_FIFO_MASK_MSK  (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)
#define UART_CR_URX_FIFO_MASK_UMSK (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS))
#define UART_CR_URX_RTO_MASK       UART_CR_URX_RTO_MASK
#define UART_CR_URX_RTO_MASK_POS   (4U)
#define UART_CR_URX_RTO_MASK_LEN   (1U)
#define UART_CR_URX_RTO_MASK_MSK   (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)
#define UART_CR_URX_RTO_MASK_UMSK  (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS))
#define UART_CR_URX_PCE_MASK       UART_CR_URX_PCE_MASK
#define UART_CR_URX_PCE_MASK_POS   (5U)
#define UART_CR_URX_PCE_MASK_LEN   (1U)
#define UART_CR_URX_PCE_MASK_MSK   (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)
#define UART_CR_URX_PCE_MASK_UMSK  (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS))
#define UART_CR_UTX_FER_MASK       UART_CR_UTX_FER_MASK
#define UART_CR_UTX_FER_MASK_POS   (6U)
#define UART_CR_UTX_FER_MASK_LEN   (1U)
#define UART_CR_UTX_FER_MASK_MSK   (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)
#define UART_CR_UTX_FER_MASK_UMSK  (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS))
#define UART_CR_URX_FER_MASK       UART_CR_URX_FER_MASK
#define UART_CR_URX_FER_MASK_POS   (7U)
#define UART_CR_URX_FER_MASK_LEN   (1U)
#define UART_CR_URX_FER_MASK_MSK   (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)
#define UART_CR_URX_FER_MASK_UMSK  (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS))
#define UART_CR_URX_LSE_MASK       UART_CR_URX_LSE_MASK
#define UART_CR_URX_LSE_MASK_POS   (8U)
#define UART_CR_URX_LSE_MASK_LEN   (1U)
#define UART_CR_URX_LSE_MASK_MSK   (((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS)
#define UART_CR_URX_LSE_MASK_UMSK  (~(((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS))

/* 0x28 : UART interrupt clear */
#define UART_INT_CLEAR_OFFSET    (0x28)
#define UART_CR_UTX_END_CLR      UART_CR_UTX_END_CLR
#define UART_CR_UTX_END_CLR_POS  (0U)
#define UART_CR_UTX_END_CLR_LEN  (1U)
#define UART_CR_UTX_END_CLR_MSK  (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)
#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS))
#define UART_CR_URX_END_CLR      UART_CR_URX_END_CLR
#define UART_CR_URX_END_CLR_POS  (1U)
#define UART_CR_URX_END_CLR_LEN  (1U)
#define UART_CR_URX_END_CLR_MSK  (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)
#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS))
#define UART_CR_URX_RTO_CLR      UART_CR_URX_RTO_CLR
#define UART_CR_URX_RTO_CLR_POS  (4U)
#define UART_CR_URX_RTO_CLR_LEN  (1U)
#define UART_CR_URX_RTO_CLR_MSK  (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)
#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS))
#define UART_CR_URX_PCE_CLR      UART_CR_URX_PCE_CLR
#define UART_CR_URX_PCE_CLR_POS  (5U)
#define UART_CR_URX_PCE_CLR_LEN  (1U)
#define UART_CR_URX_PCE_CLR_MSK  (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)
#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS))
#define UART_CR_URX_LSE_CLR      UART_CR_URX_LSE_CLR
#define UART_CR_URX_LSE_CLR_POS  (8U)
#define UART_CR_URX_LSE_CLR_LEN  (1U)
#define UART_CR_URX_LSE_CLR_MSK  (((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS)
#define UART_CR_URX_LSE_CLR_UMSK (~(((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS))

/* 0x2C : UART interrupt enable */
#define UART_INT_EN_OFFSET       (0x2C)
#define UART_CR_UTX_END_EN       UART_CR_UTX_END_EN
#define UART_CR_UTX_END_EN_POS   (0U)
#define UART_CR_UTX_END_EN_LEN   (1U)
#define UART_CR_UTX_END_EN_MSK   (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)
#define UART_CR_UTX_END_EN_UMSK  (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS))
#define UART_CR_URX_END_EN       UART_CR_URX_END_EN
#define UART_CR_URX_END_EN_POS   (1U)
#define UART_CR_URX_END_EN_LEN   (1U)
#define UART_CR_URX_END_EN_MSK   (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)
#define UART_CR_URX_END_EN_UMSK  (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS))
#define UART_CR_UTX_FIFO_EN      UART_CR_UTX_FIFO_EN
#define UART_CR_UTX_FIFO_EN_POS  (2U)
#define UART_CR_UTX_FIFO_EN_LEN  (1U)
#define UART_CR_UTX_FIFO_EN_MSK  (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)
#define UART_CR_UTX_FIFO_EN_UMSK (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS))
#define UART_CR_URX_FIFO_EN      UART_CR_URX_FIFO_EN
#define UART_CR_URX_FIFO_EN_POS  (3U)
#define UART_CR_URX_FIFO_EN_LEN  (1U)
#define UART_CR_URX_FIFO_EN_MSK  (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)
#define UART_CR_URX_FIFO_EN_UMSK (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS))
#define UART_CR_URX_RTO_EN       UART_CR_URX_RTO_EN
#define UART_CR_URX_RTO_EN_POS   (4U)
#define UART_CR_URX_RTO_EN_LEN   (1U)
#define UART_CR_URX_RTO_EN_MSK   (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)
#define UART_CR_URX_RTO_EN_UMSK  (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS))
#define UART_CR_URX_PCE_EN       UART_CR_URX_PCE_EN
#define UART_CR_URX_PCE_EN_POS   (5U)
#define UART_CR_URX_PCE_EN_LEN   (1U)
#define UART_CR_URX_PCE_EN_MSK   (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)
#define UART_CR_URX_PCE_EN_UMSK  (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS))
#define UART_CR_UTX_FER_EN       UART_CR_UTX_FER_EN
#define UART_CR_UTX_FER_EN_POS   (6U)
#define UART_CR_UTX_FER_EN_LEN   (1U)
#define UART_CR_UTX_FER_EN_MSK   (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)
#define UART_CR_UTX_FER_EN_UMSK  (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS))
#define UART_CR_URX_FER_EN       UART_CR_URX_FER_EN
#define UART_CR_URX_FER_EN_POS   (7U)
#define UART_CR_URX_FER_EN_LEN   (1U)
#define UART_CR_URX_FER_EN_MSK   (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)
#define UART_CR_URX_FER_EN_UMSK  (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS))
#define UART_CR_URX_LSE_EN       UART_CR_URX_LSE_EN
#define UART_CR_URX_LSE_EN_POS   (8U)
#define UART_CR_URX_LSE_EN_LEN   (1U)
#define UART_CR_URX_LSE_EN_MSK   (((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS)
#define UART_CR_URX_LSE_EN_UMSK  (~(((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS))

/* 0x30 : uart_status */
#define UART_STATUS_OFFSET         (0x30)
#define UART_STS_UTX_BUS_BUSY      UART_STS_UTX_BUS_BUSY
#define UART_STS_UTX_BUS_BUSY_POS  (0U)
#define UART_STS_UTX_BUS_BUSY_LEN  (1U)
#define UART_STS_UTX_BUS_BUSY_MSK  (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)
#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS))
#define UART_STS_URX_BUS_BUSY      UART_STS_URX_BUS_BUSY
#define UART_STS_URX_BUS_BUSY_POS  (1U)
#define UART_STS_URX_BUS_BUSY_LEN  (1U)
#define UART_STS_URX_BUS_BUSY_MSK  (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)
#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS))

/* 0x34 : sts_urx_abr_prd */
#define UART_STS_URX_ABR_PRD_OFFSET     (0x34)
#define UART_STS_URX_ABR_PRD_START      UART_STS_URX_ABR_PRD_START
#define UART_STS_URX_ABR_PRD_START_POS  (0U)
#define UART_STS_URX_ABR_PRD_START_LEN  (16U)
#define UART_STS_URX_ABR_PRD_START_MSK  (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)
#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS))
#define UART_STS_URX_ABR_PRD_0X55       UART_STS_URX_ABR_PRD_0X55
#define UART_STS_URX_ABR_PRD_0X55_POS   (16U)
#define UART_STS_URX_ABR_PRD_0X55_LEN   (16U)
#define UART_STS_URX_ABR_PRD_0X55_MSK   (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)
#define UART_STS_URX_ABR_PRD_0X55_UMSK  (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS))

/* 0x80 : uart_fifo_config_0 */
#define UART_FIFO_CONFIG_0_OFFSET   (0x80)
#define UART_DMA_TX_EN              UART_DMA_TX_EN
#define UART_DMA_TX_EN_POS          (0U)
#define UART_DMA_TX_EN_LEN          (1U)
#define UART_DMA_TX_EN_MSK          (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)
#define UART_DMA_TX_EN_UMSK         (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS))
#define UART_DMA_RX_EN              UART_DMA_RX_EN
#define UART_DMA_RX_EN_POS          (1U)
#define UART_DMA_RX_EN_LEN          (1U)
#define UART_DMA_RX_EN_MSK          (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)
#define UART_DMA_RX_EN_UMSK         (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS))
#define UART_TX_FIFO_CLR            UART_TX_FIFO_CLR
#define UART_TX_FIFO_CLR_POS        (2U)
#define UART_TX_FIFO_CLR_LEN        (1U)
#define UART_TX_FIFO_CLR_MSK        (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)
#define UART_TX_FIFO_CLR_UMSK       (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS))
#define UART_RX_FIFO_CLR            UART_RX_FIFO_CLR
#define UART_RX_FIFO_CLR_POS        (3U)
#define UART_RX_FIFO_CLR_LEN        (1U)
#define UART_RX_FIFO_CLR_MSK        (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)
#define UART_RX_FIFO_CLR_UMSK       (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS))
#define UART_TX_FIFO_OVERFLOW       UART_TX_FIFO_OVERFLOW
#define UART_TX_FIFO_OVERFLOW_POS   (4U)
#define UART_TX_FIFO_OVERFLOW_LEN   (1U)
#define UART_TX_FIFO_OVERFLOW_MSK   (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)
#define UART_TX_FIFO_OVERFLOW_UMSK  (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS))
#define UART_TX_FIFO_UNDERFLOW      UART_TX_FIFO_UNDERFLOW
#define UART_TX_FIFO_UNDERFLOW_POS  (5U)
#define UART_TX_FIFO_UNDERFLOW_LEN  (1U)
#define UART_TX_FIFO_UNDERFLOW_MSK  (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)
#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS))
#define UART_RX_FIFO_OVERFLOW       UART_RX_FIFO_OVERFLOW
#define UART_RX_FIFO_OVERFLOW_POS   (6U)
#define UART_RX_FIFO_OVERFLOW_LEN   (1U)
#define UART_RX_FIFO_OVERFLOW_MSK   (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)
#define UART_RX_FIFO_OVERFLOW_UMSK  (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS))
#define UART_RX_FIFO_UNDERFLOW      UART_RX_FIFO_UNDERFLOW
#define UART_RX_FIFO_UNDERFLOW_POS  (7U)
#define UART_RX_FIFO_UNDERFLOW_LEN  (1U)
#define UART_RX_FIFO_UNDERFLOW_MSK  (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)
#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS))

/* 0x84 : uart_fifo_config_1 */
#define UART_FIFO_CONFIG_1_OFFSET (0x84)
#define UART_TX_FIFO_CNT          UART_TX_FIFO_CNT
#define UART_TX_FIFO_CNT_POS      (0U)
#define UART_TX_FIFO_CNT_LEN      (8U)
#define UART_TX_FIFO_CNT_MSK      (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)
#define UART_TX_FIFO_CNT_UMSK     (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS))
#define UART_RX_FIFO_CNT          UART_RX_FIFO_CNT
#define UART_RX_FIFO_CNT_POS      (8U)
#define UART_RX_FIFO_CNT_LEN      (8U)
#define UART_RX_FIFO_CNT_MSK      (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)
#define UART_RX_FIFO_CNT_UMSK     (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS))
#define UART_TX_FIFO_TH           UART_TX_FIFO_TH
#define UART_TX_FIFO_TH_POS       (16U)
#define UART_TX_FIFO_TH_LEN       (7U)
#define UART_TX_FIFO_TH_MSK       (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)
#define UART_TX_FIFO_TH_UMSK      (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS))
#define UART_RX_FIFO_TH           UART_RX_FIFO_TH
#define UART_RX_FIFO_TH_POS       (24U)
#define UART_RX_FIFO_TH_LEN       (7U)
#define UART_RX_FIFO_TH_MSK       (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)
#define UART_RX_FIFO_TH_UMSK      (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS))

/* 0x88 : uart_fifo_wdata */
#define UART_FIFO_WDATA_OFFSET (0x88)
#define UART_FIFO_WDATA        UART_FIFO_WDATA
#define UART_FIFO_WDATA_POS    (0U)
#define UART_FIFO_WDATA_LEN    (8U)
#define UART_FIFO_WDATA_MSK    (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)
#define UART_FIFO_WDATA_UMSK   (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS))

/* 0x8C : uart_fifo_rdata */
#define UART_FIFO_RDATA_OFFSET (0x8C)
#define UART_FIFO_RDATA        UART_FIFO_RDATA
#define UART_FIFO_RDATA_POS    (0U)
#define UART_FIFO_RDATA_LEN    (8U)
#define UART_FIFO_RDATA_MSK    (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)
#define UART_FIFO_RDATA_UMSK   (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS))

struct uart_reg {
    /* 0x0 : utx_config */
    union {
        struct
        {
            uint32_t cr_utx_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_utx_cts_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_utx_frm_en    : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_utx_lin_en    : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_utx_prt_en    : 1;  /* [    4],        r/w,        0x0 */
            uint32_t cr_utx_prt_sel   : 1;  /* [    5],        r/w,        0x0 */
            uint32_t cr_utx_ir_en     : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_utx_ir_inv    : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_utx_bit_cnt_d : 3;  /* [10: 8],        r/w,        0x7 */
            uint32_t cr_utx_bit_cnt_p : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_utx_bit_cnt_b : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_utx_len       : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } utx_config;

    /* 0x4 : urx_config */
    union {
        struct
        {
            uint32_t cr_urx_en        : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_urx_abr_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t reserved_2       : 1;  /* [    2],       rsvd,        0x0 */
            uint32_t cr_urx_lin_en    : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_urx_prt_en    : 1;  /* [    4],        r/w,        0x0 */
            uint32_t cr_urx_prt_sel   : 1;  /* [    5],        r/w,        0x0 */
            uint32_t cr_urx_ir_en     : 1;  /* [    6],        r/w,        0x0 */
            uint32_t cr_urx_ir_inv    : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_urx_bit_cnt_d : 3;  /* [10: 8],        r/w,        0x7 */
            uint32_t cr_urx_deg_en    : 1;  /* [   11],        r/w,        0x0 */
            uint32_t cr_urx_deg_cnt   : 4;  /* [15:12],        r/w,        0x0 */
            uint32_t cr_urx_len       : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } urx_config;

    /* 0x8 : uart_bit_prd */
    union {
        struct
        {
            uint32_t cr_utx_bit_prd : 16; /* [15: 0],        r/w,       0xff */
            uint32_t cr_urx_bit_prd : 16; /* [31:16],        r/w,       0xff */
        } BF;
        uint32_t WORD;
    } uart_bit_prd;

    /* 0xC : data_config */
    union {
        struct
        {
            uint32_t cr_uart_bit_inv : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_31   : 31; /* [31: 1],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } data_config;

    /* 0x10 : utx_ir_position */
    union {
        struct
        {
            uint32_t cr_utx_ir_pos_s : 16; /* [15: 0],        r/w,       0x70 */
            uint32_t cr_utx_ir_pos_p : 16; /* [31:16],        r/w,       0x9f */
        } BF;
        uint32_t WORD;
    } utx_ir_position;

    /* 0x14 : urx_ir_position */
    union {
        struct
        {
            uint32_t cr_urx_ir_pos_s : 16; /* [15: 0],        r/w,       0x6f */
            uint32_t reserved_16_31  : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } urx_ir_position;

    /* 0x18 : urx_rto_timer */
    union {
        struct
        {
            uint32_t cr_urx_rto_value : 8;  /* [ 7: 0],        r/w,        0xf */
            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } urx_rto_timer;

    /* 0x1C : uart_sw_mode */
    union {
        struct
        {
            uint32_t cr_utx_txd_sw_mode : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_utx_txd_sw_val  : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_urx_rts_sw_mode : 1;  /* [    2],        r/w,        0x0 */
            uint32_t cr_urx_rts_sw_val  : 1;  /* [    3],        r/w,        0x0 */
            uint32_t reserved_4_31      : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_sw_mode;

    /* 0x20 : UART interrupt status */
    union {
        struct
        {
            uint32_t utx_end_int   : 1;  /* [    0],          r,        0x0 */
            uint32_t urx_end_int   : 1;  /* [    1],          r,        0x0 */
            uint32_t utx_fifo_int  : 1;  /* [    2],          r,        0x0 */
            uint32_t urx_fifo_int  : 1;  /* [    3],          r,        0x0 */
            uint32_t urx_rto_int   : 1;  /* [    4],          r,        0x0 */
            uint32_t urx_pce_int   : 1;  /* [    5],          r,        0x0 */
            uint32_t utx_fer_int   : 1;  /* [    6],          r,        0x0 */
            uint32_t urx_fer_int   : 1;  /* [    7],          r,        0x0 */
            uint32_t urx_lse_int   : 1;  /* [    8],          r,        0x0 */
            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_int_sts;

    /* 0x24 : UART interrupt mask */
    union {
        struct
        {
            uint32_t cr_utx_end_mask  : 1;  /* [    0],        r/w,        0x1 */
            uint32_t cr_urx_end_mask  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t cr_utx_fifo_mask : 1;  /* [    2],        r/w,        0x1 */
            uint32_t cr_urx_fifo_mask : 1;  /* [    3],        r/w,        0x1 */
            uint32_t cr_urx_rto_mask  : 1;  /* [    4],        r/w,        0x1 */
            uint32_t cr_urx_pce_mask  : 1;  /* [    5],        r/w,        0x1 */
            uint32_t cr_utx_fer_mask  : 1;  /* [    6],        r/w,        0x1 */
            uint32_t cr_urx_fer_mask  : 1;  /* [    7],        r/w,        0x1 */
            uint32_t cr_urx_lse_mask  : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_31    : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_int_mask;

    /* 0x28 : UART interrupt clear */
    union {
        struct
        {
            uint32_t cr_utx_end_clr : 1;  /* [    0],        w1c,        0x0 */
            uint32_t cr_urx_end_clr : 1;  /* [    1],        w1c,        0x0 */
            uint32_t rsvd_2         : 1;  /* [    2],       rsvd,        0x0 */
            uint32_t rsvd_3         : 1;  /* [    3],       rsvd,        0x0 */
            uint32_t cr_urx_rto_clr : 1;  /* [    4],        w1c,        0x0 */
            uint32_t cr_urx_pce_clr : 1;  /* [    5],        w1c,        0x0 */
            uint32_t rsvd_6         : 1;  /* [    6],       rsvd,        0x0 */
            uint32_t rsvd_7         : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t cr_urx_lse_clr : 1;  /* [    8],        w1c,        0x0 */
            uint32_t reserved_9_31  : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_int_clear;

    /* 0x2C : UART interrupt enable */
    union {
        struct
        {
            uint32_t cr_utx_end_en  : 1;  /* [    0],        r/w,        0x1 */
            uint32_t cr_urx_end_en  : 1;  /* [    1],        r/w,        0x1 */
            uint32_t cr_utx_fifo_en : 1;  /* [    2],        r/w,        0x1 */
            uint32_t cr_urx_fifo_en : 1;  /* [    3],        r/w,        0x1 */
            uint32_t cr_urx_rto_en  : 1;  /* [    4],        r/w,        0x1 */
            uint32_t cr_urx_pce_en  : 1;  /* [    5],        r/w,        0x1 */
            uint32_t cr_utx_fer_en  : 1;  /* [    6],        r/w,        0x1 */
            uint32_t cr_urx_fer_en  : 1;  /* [    7],        r/w,        0x1 */
            uint32_t cr_urx_lse_en  : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_31  : 23; /* [31: 9],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_int_en;

    /* 0x30 : uart_status */
    union {
        struct
        {
            uint32_t sts_utx_bus_busy : 1;  /* [    0],          r,        0x0 */
            uint32_t sts_urx_bus_busy : 1;  /* [    1],          r,        0x0 */
            uint32_t reserved_2_31    : 30; /* [31: 2],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_status;

    /* 0x34 : sts_urx_abr_prd */
    union {
        struct
        {
            uint32_t sts_urx_abr_prd_start : 16; /* [15: 0],          r,        0x0 */
            uint32_t sts_urx_abr_prd_0x55  : 16; /* [31:16],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } sts_urx_abr_prd;

    /* 0x38  reserved */
    uint8_t RESERVED0x38[72];

    /* 0x80 : uart_fifo_config_0 */
    union {
        struct
        {
            uint32_t uart_dma_tx_en    : 1;  /* [    0],        r/w,        0x0 */
            uint32_t uart_dma_rx_en    : 1;  /* [    1],        r/w,        0x0 */
            uint32_t tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_fifo_config_0;

    /* 0x84 : uart_fifo_config_1 */
    union {
        struct
        {
            uint32_t tx_fifo_cnt : 8; /* [ 7: 0],          r,       0x80 */
            uint32_t rx_fifo_cnt : 8; /* [15: 8],          r,        0x0 */
            uint32_t tx_fifo_th  : 7; /* [22:16],        r/w,        0x0 */
            uint32_t reserved_23 : 1; /* [   23],       rsvd,        0x0 */
            uint32_t rx_fifo_th  : 7; /* [30:24],        r/w,        0x0 */
            uint32_t reserved_31 : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_fifo_config_1;

    /* 0x88 : uart_fifo_wdata */
    union {
        struct
        {
            uint32_t uart_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_fifo_wdata;

    /* 0x8C : uart_fifo_rdata */
    union {
        struct
        {
            uint32_t uart_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31   : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } uart_fifo_rdata;
};

typedef volatile struct uart_reg uart_reg_t;

#endif /* __UART_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/regs/usb_reg.h
================================================
/**
  ******************************************************************************
  * @file    usb_reg.h
  * @version V1.2
  * @date    2020-09-04
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __USB_REG_H__
#define __USB_REG_H__

#include "bl702.h"

/* 0x0 : usb_config */
#define USB_CONFIG_OFFSET               (0x0)
#define USB_CR_USB_EN                   USB_CR_USB_EN
#define USB_CR_USB_EN_POS               (0U)
#define USB_CR_USB_EN_LEN               (1U)
#define USB_CR_USB_EN_MSK               (((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS)
#define USB_CR_USB_EN_UMSK              (~(((1U << USB_CR_USB_EN_LEN) - 1) << USB_CR_USB_EN_POS))
#define USB_CR_USB_ROM_DCT_EN           USB_CR_USB_ROM_DCT_EN
#define USB_CR_USB_ROM_DCT_EN_POS       (4U)
#define USB_CR_USB_ROM_DCT_EN_LEN       (1U)
#define USB_CR_USB_ROM_DCT_EN_MSK       (((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS)
#define USB_CR_USB_ROM_DCT_EN_UMSK      (~(((1U << USB_CR_USB_ROM_DCT_EN_LEN) - 1) << USB_CR_USB_ROM_DCT_EN_POS))
#define USB_CR_USB_EP0_SW_CTRL          USB_CR_USB_EP0_SW_CTRL
#define USB_CR_USB_EP0_SW_CTRL_POS      (8U)
#define USB_CR_USB_EP0_SW_CTRL_LEN      (1U)
#define USB_CR_USB_EP0_SW_CTRL_MSK      (((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS)
#define USB_CR_USB_EP0_SW_CTRL_UMSK     (~(((1U << USB_CR_USB_EP0_SW_CTRL_LEN) - 1) << USB_CR_USB_EP0_SW_CTRL_POS))
#define USB_CR_USB_EP0_SW_ADDR          USB_CR_USB_EP0_SW_ADDR
#define USB_CR_USB_EP0_SW_ADDR_POS      (9U)
#define USB_CR_USB_EP0_SW_ADDR_LEN      (7U)
#define USB_CR_USB_EP0_SW_ADDR_MSK      (((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS)
#define USB_CR_USB_EP0_SW_ADDR_UMSK     (~(((1U << USB_CR_USB_EP0_SW_ADDR_LEN) - 1) << USB_CR_USB_EP0_SW_ADDR_POS))
#define USB_CR_USB_EP0_SW_SIZE          USB_CR_USB_EP0_SW_SIZE
#define USB_CR_USB_EP0_SW_SIZE_POS      (16U)
#define USB_CR_USB_EP0_SW_SIZE_LEN      (8U)
#define USB_CR_USB_EP0_SW_SIZE_MSK      (((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS)
#define USB_CR_USB_EP0_SW_SIZE_UMSK     (~(((1U << USB_CR_USB_EP0_SW_SIZE_LEN) - 1) << USB_CR_USB_EP0_SW_SIZE_POS))
#define USB_CR_USB_EP0_SW_STALL         USB_CR_USB_EP0_SW_STALL
#define USB_CR_USB_EP0_SW_STALL_POS     (24U)
#define USB_CR_USB_EP0_SW_STALL_LEN     (1U)
#define USB_CR_USB_EP0_SW_STALL_MSK     (((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS)
#define USB_CR_USB_EP0_SW_STALL_UMSK    (~(((1U << USB_CR_USB_EP0_SW_STALL_LEN) - 1) << USB_CR_USB_EP0_SW_STALL_POS))
#define USB_CR_USB_EP0_SW_NACK_IN       USB_CR_USB_EP0_SW_NACK_IN
#define USB_CR_USB_EP0_SW_NACK_IN_POS   (25U)
#define USB_CR_USB_EP0_SW_NACK_IN_LEN   (1U)
#define USB_CR_USB_EP0_SW_NACK_IN_MSK   (((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS)
#define USB_CR_USB_EP0_SW_NACK_IN_UMSK  (~(((1U << USB_CR_USB_EP0_SW_NACK_IN_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_IN_POS))
#define USB_CR_USB_EP0_SW_NACK_OUT      USB_CR_USB_EP0_SW_NACK_OUT
#define USB_CR_USB_EP0_SW_NACK_OUT_POS  (26U)
#define USB_CR_USB_EP0_SW_NACK_OUT_LEN  (1U)
#define USB_CR_USB_EP0_SW_NACK_OUT_MSK  (((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS)
#define USB_CR_USB_EP0_SW_NACK_OUT_UMSK (~(((1U << USB_CR_USB_EP0_SW_NACK_OUT_LEN) - 1) << USB_CR_USB_EP0_SW_NACK_OUT_POS))
#define USB_CR_USB_EP0_SW_RDY           USB_CR_USB_EP0_SW_RDY
#define USB_CR_USB_EP0_SW_RDY_POS       (27U)
#define USB_CR_USB_EP0_SW_RDY_LEN       (1U)
#define USB_CR_USB_EP0_SW_RDY_MSK       (((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS)
#define USB_CR_USB_EP0_SW_RDY_UMSK      (~(((1U << USB_CR_USB_EP0_SW_RDY_LEN) - 1) << USB_CR_USB_EP0_SW_RDY_POS))
#define USB_STS_USB_EP0_SW_RDY          USB_STS_USB_EP0_SW_RDY
#define USB_STS_USB_EP0_SW_RDY_POS      (28U)
#define USB_STS_USB_EP0_SW_RDY_LEN      (1U)
#define USB_STS_USB_EP0_SW_RDY_MSK      (((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS)
#define USB_STS_USB_EP0_SW_RDY_UMSK     (~(((1U << USB_STS_USB_EP0_SW_RDY_LEN) - 1) << USB_STS_USB_EP0_SW_RDY_POS))

/* 0x4 : usb_lpm_config */
#define USB_LPM_CONFIG_OFFSET    (0x4)
#define USB_CR_LPM_EN            USB_CR_LPM_EN
#define USB_CR_LPM_EN_POS        (0U)
#define USB_CR_LPM_EN_LEN        (1U)
#define USB_CR_LPM_EN_MSK        (((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS)
#define USB_CR_LPM_EN_UMSK       (~(((1U << USB_CR_LPM_EN_LEN) - 1) << USB_CR_LPM_EN_POS))
#define USB_CR_LPM_RESP_UPD      USB_CR_LPM_RESP_UPD
#define USB_CR_LPM_RESP_UPD_POS  (1U)
#define USB_CR_LPM_RESP_UPD_LEN  (1U)
#define USB_CR_LPM_RESP_UPD_MSK  (((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS)
#define USB_CR_LPM_RESP_UPD_UMSK (~(((1U << USB_CR_LPM_RESP_UPD_LEN) - 1) << USB_CR_LPM_RESP_UPD_POS))
#define USB_CR_LPM_RESP          USB_CR_LPM_RESP
#define USB_CR_LPM_RESP_POS      (2U)
#define USB_CR_LPM_RESP_LEN      (2U)
#define USB_CR_LPM_RESP_MSK      (((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS)
#define USB_CR_LPM_RESP_UMSK     (~(((1U << USB_CR_LPM_RESP_LEN) - 1) << USB_CR_LPM_RESP_POS))
#define USB_STS_LPM_ATTR         USB_STS_LPM_ATTR
#define USB_STS_LPM_ATTR_POS     (20U)
#define USB_STS_LPM_ATTR_LEN     (11U)
#define USB_STS_LPM_ATTR_MSK     (((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS)
#define USB_STS_LPM_ATTR_UMSK    (~(((1U << USB_STS_LPM_ATTR_LEN) - 1) << USB_STS_LPM_ATTR_POS))
#define USB_STS_LPM              USB_STS_LPM
#define USB_STS_LPM_POS          (31U)
#define USB_STS_LPM_LEN          (1U)
#define USB_STS_LPM_MSK          (((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS)
#define USB_STS_LPM_UMSK         (~(((1U << USB_STS_LPM_LEN) - 1) << USB_STS_LPM_POS))

/* 0x8 : usb_resume_config */
#define USB_RESUME_CONFIG_OFFSET (0x8)
#define USB_CR_RES_WIDTH         USB_CR_RES_WIDTH
#define USB_CR_RES_WIDTH_POS     (0U)
#define USB_CR_RES_WIDTH_LEN     (11U)
#define USB_CR_RES_WIDTH_MSK     (((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS)
#define USB_CR_RES_WIDTH_UMSK    (~(((1U << USB_CR_RES_WIDTH_LEN) - 1) << USB_CR_RES_WIDTH_POS))
#define USB_CR_RES_TRIG          USB_CR_RES_TRIG
#define USB_CR_RES_TRIG_POS      (12U)
#define USB_CR_RES_TRIG_LEN      (1U)
#define USB_CR_RES_TRIG_MSK      (((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS)
#define USB_CR_RES_TRIG_UMSK     (~(((1U << USB_CR_RES_TRIG_LEN) - 1) << USB_CR_RES_TRIG_POS))
#define USB_CR_RES_FORCE         USB_CR_RES_FORCE
#define USB_CR_RES_FORCE_POS     (31U)
#define USB_CR_RES_FORCE_LEN     (1U)
#define USB_CR_RES_FORCE_MSK     (((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS)
#define USB_CR_RES_FORCE_UMSK    (~(((1U << USB_CR_RES_FORCE_LEN) - 1) << USB_CR_RES_FORCE_POS))

/* 0x10 : usb_setup_data_0 */
#define USB_SETUP_DATA_0_OFFSET    (0x10)
#define USB_STS_SETUP_DATA_B0      USB_STS_SETUP_DATA_B0
#define USB_STS_SETUP_DATA_B0_POS  (0U)
#define USB_STS_SETUP_DATA_B0_LEN  (8U)
#define USB_STS_SETUP_DATA_B0_MSK  (((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS)
#define USB_STS_SETUP_DATA_B0_UMSK (~(((1U << USB_STS_SETUP_DATA_B0_LEN) - 1) << USB_STS_SETUP_DATA_B0_POS))
#define USB_STS_SETUP_DATA_B1      USB_STS_SETUP_DATA_B1
#define USB_STS_SETUP_DATA_B1_POS  (8U)
#define USB_STS_SETUP_DATA_B1_LEN  (8U)
#define USB_STS_SETUP_DATA_B1_MSK  (((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS)
#define USB_STS_SETUP_DATA_B1_UMSK (~(((1U << USB_STS_SETUP_DATA_B1_LEN) - 1) << USB_STS_SETUP_DATA_B1_POS))
#define USB_STS_SETUP_DATA_B2      USB_STS_SETUP_DATA_B2
#define USB_STS_SETUP_DATA_B2_POS  (16U)
#define USB_STS_SETUP_DATA_B2_LEN  (8U)
#define USB_STS_SETUP_DATA_B2_MSK  (((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS)
#define USB_STS_SETUP_DATA_B2_UMSK (~(((1U << USB_STS_SETUP_DATA_B2_LEN) - 1) << USB_STS_SETUP_DATA_B2_POS))
#define USB_STS_SETUP_DATA_B3      USB_STS_SETUP_DATA_B3
#define USB_STS_SETUP_DATA_B3_POS  (24U)
#define USB_STS_SETUP_DATA_B3_LEN  (8U)
#define USB_STS_SETUP_DATA_B3_MSK  (((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS)
#define USB_STS_SETUP_DATA_B3_UMSK (~(((1U << USB_STS_SETUP_DATA_B3_LEN) - 1) << USB_STS_SETUP_DATA_B3_POS))

/* 0x14 : usb_setup_data_1 */
#define USB_SETUP_DATA_1_OFFSET    (0x14)
#define USB_STS_SETUP_DATA_B4      USB_STS_SETUP_DATA_B4
#define USB_STS_SETUP_DATA_B4_POS  (0U)
#define USB_STS_SETUP_DATA_B4_LEN  (8U)
#define USB_STS_SETUP_DATA_B4_MSK  (((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS)
#define USB_STS_SETUP_DATA_B4_UMSK (~(((1U << USB_STS_SETUP_DATA_B4_LEN) - 1) << USB_STS_SETUP_DATA_B4_POS))
#define USB_STS_SETUP_DATA_B5      USB_STS_SETUP_DATA_B5
#define USB_STS_SETUP_DATA_B5_POS  (8U)
#define USB_STS_SETUP_DATA_B5_LEN  (8U)
#define USB_STS_SETUP_DATA_B5_MSK  (((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS)
#define USB_STS_SETUP_DATA_B5_UMSK (~(((1U << USB_STS_SETUP_DATA_B5_LEN) - 1) << USB_STS_SETUP_DATA_B5_POS))
#define USB_STS_SETUP_DATA_B6      USB_STS_SETUP_DATA_B6
#define USB_STS_SETUP_DATA_B6_POS  (16U)
#define USB_STS_SETUP_DATA_B6_LEN  (8U)
#define USB_STS_SETUP_DATA_B6_MSK  (((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS)
#define USB_STS_SETUP_DATA_B6_UMSK (~(((1U << USB_STS_SETUP_DATA_B6_LEN) - 1) << USB_STS_SETUP_DATA_B6_POS))
#define USB_STS_SETUP_DATA_B7      USB_STS_SETUP_DATA_B7
#define USB_STS_SETUP_DATA_B7_POS  (24U)
#define USB_STS_SETUP_DATA_B7_LEN  (8U)
#define USB_STS_SETUP_DATA_B7_MSK  (((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS)
#define USB_STS_SETUP_DATA_B7_UMSK (~(((1U << USB_STS_SETUP_DATA_B7_LEN) - 1) << USB_STS_SETUP_DATA_B7_POS))

/* 0x18 : usb_frame_no */
#define USB_FRAME_NO_OFFSET   (0x18)
#define USB_STS_FRAME_NO      USB_STS_FRAME_NO
#define USB_STS_FRAME_NO_POS  (0U)
#define USB_STS_FRAME_NO_LEN  (11U)
#define USB_STS_FRAME_NO_MSK  (((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS)
#define USB_STS_FRAME_NO_UMSK (~(((1U << USB_STS_FRAME_NO_LEN) - 1) << USB_STS_FRAME_NO_POS))
#define USB_STS_PID           USB_STS_PID
#define USB_STS_PID_POS       (12U)
#define USB_STS_PID_LEN       (4U)
#define USB_STS_PID_MSK       (((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS)
#define USB_STS_PID_UMSK      (~(((1U << USB_STS_PID_LEN) - 1) << USB_STS_PID_POS))
#define USB_STS_EP_NO         USB_STS_EP_NO
#define USB_STS_EP_NO_POS     (16U)
#define USB_STS_EP_NO_LEN     (4U)
#define USB_STS_EP_NO_MSK     (((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS)
#define USB_STS_EP_NO_UMSK    (~(((1U << USB_STS_EP_NO_LEN) - 1) << USB_STS_EP_NO_POS))

/* 0x1C : usb_error */
#define USB_ERROR_OFFSET     (0x1C)
#define USB_UTMI_RX_ERR      USB_UTMI_RX_ERR
#define USB_UTMI_RX_ERR_POS  (0U)
#define USB_UTMI_RX_ERR_LEN  (1U)
#define USB_UTMI_RX_ERR_MSK  (((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS)
#define USB_UTMI_RX_ERR_UMSK (~(((1U << USB_UTMI_RX_ERR_LEN) - 1) << USB_UTMI_RX_ERR_POS))
#define USB_XFER_TO_ERR      USB_XFER_TO_ERR
#define USB_XFER_TO_ERR_POS  (1U)
#define USB_XFER_TO_ERR_LEN  (1U)
#define USB_XFER_TO_ERR_MSK  (((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS)
#define USB_XFER_TO_ERR_UMSK (~(((1U << USB_XFER_TO_ERR_LEN) - 1) << USB_XFER_TO_ERR_POS))
#define USB_IVLD_EP_ERR      USB_IVLD_EP_ERR
#define USB_IVLD_EP_ERR_POS  (2U)
#define USB_IVLD_EP_ERR_LEN  (1U)
#define USB_IVLD_EP_ERR_MSK  (((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS)
#define USB_IVLD_EP_ERR_UMSK (~(((1U << USB_IVLD_EP_ERR_LEN) - 1) << USB_IVLD_EP_ERR_POS))
#define USB_PID_SEQ_ERR      USB_PID_SEQ_ERR
#define USB_PID_SEQ_ERR_POS  (3U)
#define USB_PID_SEQ_ERR_LEN  (1U)
#define USB_PID_SEQ_ERR_MSK  (((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS)
#define USB_PID_SEQ_ERR_UMSK (~(((1U << USB_PID_SEQ_ERR_LEN) - 1) << USB_PID_SEQ_ERR_POS))
#define USB_PID_CKS_ERR      USB_PID_CKS_ERR
#define USB_PID_CKS_ERR_POS  (4U)
#define USB_PID_CKS_ERR_LEN  (1U)
#define USB_PID_CKS_ERR_MSK  (((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS)
#define USB_PID_CKS_ERR_UMSK (~(((1U << USB_PID_CKS_ERR_LEN) - 1) << USB_PID_CKS_ERR_POS))
#define USB_CRC5_ERR         USB_CRC5_ERR
#define USB_CRC5_ERR_POS     (5U)
#define USB_CRC5_ERR_LEN     (1U)
#define USB_CRC5_ERR_MSK     (((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS)
#define USB_CRC5_ERR_UMSK    (~(((1U << USB_CRC5_ERR_LEN) - 1) << USB_CRC5_ERR_POS))
#define USB_CRC16_ERR        USB_CRC16_ERR
#define USB_CRC16_ERR_POS    (6U)
#define USB_CRC16_ERR_LEN    (1U)
#define USB_CRC16_ERR_MSK    (((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS)
#define USB_CRC16_ERR_UMSK   (~(((1U << USB_CRC16_ERR_LEN) - 1) << USB_CRC16_ERR_POS))

/* 0x20 : USB interrupt enable */
#define USB_INT_EN_OFFSET             (0x20)
#define USB_CR_SOF_EN                 USB_CR_SOF_EN
#define USB_CR_SOF_EN_POS             (0U)
#define USB_CR_SOF_EN_LEN             (1U)
#define USB_CR_SOF_EN_MSK             (((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS)
#define USB_CR_SOF_EN_UMSK            (~(((1U << USB_CR_SOF_EN_LEN) - 1) << USB_CR_SOF_EN_POS))
#define USB_CR_USB_RESET_EN           USB_CR_USB_RESET_EN
#define USB_CR_USB_RESET_EN_POS       (1U)
#define USB_CR_USB_RESET_EN_LEN       (1U)
#define USB_CR_USB_RESET_EN_MSK       (((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS)
#define USB_CR_USB_RESET_EN_UMSK      (~(((1U << USB_CR_USB_RESET_EN_LEN) - 1) << USB_CR_USB_RESET_EN_POS))
#define USB_CR_VBUS_TGL_EN            USB_CR_VBUS_TGL_EN
#define USB_CR_VBUS_TGL_EN_POS        (2U)
#define USB_CR_VBUS_TGL_EN_LEN        (1U)
#define USB_CR_VBUS_TGL_EN_MSK        (((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS)
#define USB_CR_VBUS_TGL_EN_UMSK       (~(((1U << USB_CR_VBUS_TGL_EN_LEN) - 1) << USB_CR_VBUS_TGL_EN_POS))
#define USB_CR_GET_DCT_CMD_EN         USB_CR_GET_DCT_CMD_EN
#define USB_CR_GET_DCT_CMD_EN_POS     (3U)
#define USB_CR_GET_DCT_CMD_EN_LEN     (1U)
#define USB_CR_GET_DCT_CMD_EN_MSK     (((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS)
#define USB_CR_GET_DCT_CMD_EN_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_EN_LEN) - 1) << USB_CR_GET_DCT_CMD_EN_POS))
#define USB_CR_EP0_SETUP_CMD_EN       USB_CR_EP0_SETUP_CMD_EN
#define USB_CR_EP0_SETUP_CMD_EN_POS   (4U)
#define USB_CR_EP0_SETUP_CMD_EN_LEN   (1U)
#define USB_CR_EP0_SETUP_CMD_EN_MSK   (((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS)
#define USB_CR_EP0_SETUP_CMD_EN_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_EN_LEN) - 1) << USB_CR_EP0_SETUP_CMD_EN_POS))
#define USB_CR_EP0_SETUP_DONE_EN      USB_CR_EP0_SETUP_DONE_EN
#define USB_CR_EP0_SETUP_DONE_EN_POS  (5U)
#define USB_CR_EP0_SETUP_DONE_EN_LEN  (1U)
#define USB_CR_EP0_SETUP_DONE_EN_MSK  (((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS)
#define USB_CR_EP0_SETUP_DONE_EN_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_EN_LEN) - 1) << USB_CR_EP0_SETUP_DONE_EN_POS))
#define USB_CR_EP0_IN_CMD_EN          USB_CR_EP0_IN_CMD_EN
#define USB_CR_EP0_IN_CMD_EN_POS      (6U)
#define USB_CR_EP0_IN_CMD_EN_LEN      (1U)
#define USB_CR_EP0_IN_CMD_EN_MSK      (((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS)
#define USB_CR_EP0_IN_CMD_EN_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_EN_LEN) - 1) << USB_CR_EP0_IN_CMD_EN_POS))
#define USB_CR_EP0_IN_DONE_EN         USB_CR_EP0_IN_DONE_EN
#define USB_CR_EP0_IN_DONE_EN_POS     (7U)
#define USB_CR_EP0_IN_DONE_EN_LEN     (1U)
#define USB_CR_EP0_IN_DONE_EN_MSK     (((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS)
#define USB_CR_EP0_IN_DONE_EN_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_EN_LEN) - 1) << USB_CR_EP0_IN_DONE_EN_POS))
#define USB_CR_EP0_OUT_CMD_EN         USB_CR_EP0_OUT_CMD_EN
#define USB_CR_EP0_OUT_CMD_EN_POS     (8U)
#define USB_CR_EP0_OUT_CMD_EN_LEN     (1U)
#define USB_CR_EP0_OUT_CMD_EN_MSK     (((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS)
#define USB_CR_EP0_OUT_CMD_EN_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_EN_LEN) - 1) << USB_CR_EP0_OUT_CMD_EN_POS))
#define USB_CR_EP0_OUT_DONE_EN        USB_CR_EP0_OUT_DONE_EN
#define USB_CR_EP0_OUT_DONE_EN_POS    (9U)
#define USB_CR_EP0_OUT_DONE_EN_LEN    (1U)
#define USB_CR_EP0_OUT_DONE_EN_MSK    (((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS)
#define USB_CR_EP0_OUT_DONE_EN_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_EN_LEN) - 1) << USB_CR_EP0_OUT_DONE_EN_POS))
#define USB_CR_EP1_CMD_EN             USB_CR_EP1_CMD_EN
#define USB_CR_EP1_CMD_EN_POS         (10U)
#define USB_CR_EP1_CMD_EN_LEN         (1U)
#define USB_CR_EP1_CMD_EN_MSK         (((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS)
#define USB_CR_EP1_CMD_EN_UMSK        (~(((1U << USB_CR_EP1_CMD_EN_LEN) - 1) << USB_CR_EP1_CMD_EN_POS))
#define USB_CR_EP1_DONE_EN            USB_CR_EP1_DONE_EN
#define USB_CR_EP1_DONE_EN_POS        (11U)
#define USB_CR_EP1_DONE_EN_LEN        (1U)
#define USB_CR_EP1_DONE_EN_MSK        (((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS)
#define USB_CR_EP1_DONE_EN_UMSK       (~(((1U << USB_CR_EP1_DONE_EN_LEN) - 1) << USB_CR_EP1_DONE_EN_POS))
#define USB_CR_EP2_CMD_EN             USB_CR_EP2_CMD_EN
#define USB_CR_EP2_CMD_EN_POS         (12U)
#define USB_CR_EP2_CMD_EN_LEN         (1U)
#define USB_CR_EP2_CMD_EN_MSK         (((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS)
#define USB_CR_EP2_CMD_EN_UMSK        (~(((1U << USB_CR_EP2_CMD_EN_LEN) - 1) << USB_CR_EP2_CMD_EN_POS))
#define USB_CR_EP2_DONE_EN            USB_CR_EP2_DONE_EN
#define USB_CR_EP2_DONE_EN_POS        (13U)
#define USB_CR_EP2_DONE_EN_LEN        (1U)
#define USB_CR_EP2_DONE_EN_MSK        (((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS)
#define USB_CR_EP2_DONE_EN_UMSK       (~(((1U << USB_CR_EP2_DONE_EN_LEN) - 1) << USB_CR_EP2_DONE_EN_POS))
#define USB_CR_EP3_CMD_EN             USB_CR_EP3_CMD_EN
#define USB_CR_EP3_CMD_EN_POS         (14U)
#define USB_CR_EP3_CMD_EN_LEN         (1U)
#define USB_CR_EP3_CMD_EN_MSK         (((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS)
#define USB_CR_EP3_CMD_EN_UMSK        (~(((1U << USB_CR_EP3_CMD_EN_LEN) - 1) << USB_CR_EP3_CMD_EN_POS))
#define USB_CR_EP3_DONE_EN            USB_CR_EP3_DONE_EN
#define USB_CR_EP3_DONE_EN_POS        (15U)
#define USB_CR_EP3_DONE_EN_LEN        (1U)
#define USB_CR_EP3_DONE_EN_MSK        (((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS)
#define USB_CR_EP3_DONE_EN_UMSK       (~(((1U << USB_CR_EP3_DONE_EN_LEN) - 1) << USB_CR_EP3_DONE_EN_POS))
#define USB_CR_EP4_CMD_EN             USB_CR_EP4_CMD_EN
#define USB_CR_EP4_CMD_EN_POS         (16U)
#define USB_CR_EP4_CMD_EN_LEN         (1U)
#define USB_CR_EP4_CMD_EN_MSK         (((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS)
#define USB_CR_EP4_CMD_EN_UMSK        (~(((1U << USB_CR_EP4_CMD_EN_LEN) - 1) << USB_CR_EP4_CMD_EN_POS))
#define USB_CR_EP4_DONE_EN            USB_CR_EP4_DONE_EN
#define USB_CR_EP4_DONE_EN_POS        (17U)
#define USB_CR_EP4_DONE_EN_LEN        (1U)
#define USB_CR_EP4_DONE_EN_MSK        (((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS)
#define USB_CR_EP4_DONE_EN_UMSK       (~(((1U << USB_CR_EP4_DONE_EN_LEN) - 1) << USB_CR_EP4_DONE_EN_POS))
#define USB_CR_EP5_CMD_EN             USB_CR_EP5_CMD_EN
#define USB_CR_EP5_CMD_EN_POS         (18U)
#define USB_CR_EP5_CMD_EN_LEN         (1U)
#define USB_CR_EP5_CMD_EN_MSK         (((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS)
#define USB_CR_EP5_CMD_EN_UMSK        (~(((1U << USB_CR_EP5_CMD_EN_LEN) - 1) << USB_CR_EP5_CMD_EN_POS))
#define USB_CR_EP5_DONE_EN            USB_CR_EP5_DONE_EN
#define USB_CR_EP5_DONE_EN_POS        (19U)
#define USB_CR_EP5_DONE_EN_LEN        (1U)
#define USB_CR_EP5_DONE_EN_MSK        (((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS)
#define USB_CR_EP5_DONE_EN_UMSK       (~(((1U << USB_CR_EP5_DONE_EN_LEN) - 1) << USB_CR_EP5_DONE_EN_POS))
#define USB_CR_EP6_CMD_EN             USB_CR_EP6_CMD_EN
#define USB_CR_EP6_CMD_EN_POS         (20U)
#define USB_CR_EP6_CMD_EN_LEN         (1U)
#define USB_CR_EP6_CMD_EN_MSK         (((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS)
#define USB_CR_EP6_CMD_EN_UMSK        (~(((1U << USB_CR_EP6_CMD_EN_LEN) - 1) << USB_CR_EP6_CMD_EN_POS))
#define USB_CR_EP6_DONE_EN            USB_CR_EP6_DONE_EN
#define USB_CR_EP6_DONE_EN_POS        (21U)
#define USB_CR_EP6_DONE_EN_LEN        (1U)
#define USB_CR_EP6_DONE_EN_MSK        (((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS)
#define USB_CR_EP6_DONE_EN_UMSK       (~(((1U << USB_CR_EP6_DONE_EN_LEN) - 1) << USB_CR_EP6_DONE_EN_POS))
#define USB_CR_EP7_CMD_EN             USB_CR_EP7_CMD_EN
#define USB_CR_EP7_CMD_EN_POS         (22U)
#define USB_CR_EP7_CMD_EN_LEN         (1U)
#define USB_CR_EP7_CMD_EN_MSK         (((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS)
#define USB_CR_EP7_CMD_EN_UMSK        (~(((1U << USB_CR_EP7_CMD_EN_LEN) - 1) << USB_CR_EP7_CMD_EN_POS))
#define USB_CR_EP7_DONE_EN            USB_CR_EP7_DONE_EN
#define USB_CR_EP7_DONE_EN_POS        (23U)
#define USB_CR_EP7_DONE_EN_LEN        (1U)
#define USB_CR_EP7_DONE_EN_MSK        (((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS)
#define USB_CR_EP7_DONE_EN_UMSK       (~(((1U << USB_CR_EP7_DONE_EN_LEN) - 1) << USB_CR_EP7_DONE_EN_POS))
#define USB_CR_USB_REND_EN            USB_CR_USB_REND_EN
#define USB_CR_USB_REND_EN_POS        (27U)
#define USB_CR_USB_REND_EN_LEN        (1U)
#define USB_CR_USB_REND_EN_MSK        (((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS)
#define USB_CR_USB_REND_EN_UMSK       (~(((1U << USB_CR_USB_REND_EN_LEN) - 1) << USB_CR_USB_REND_EN_POS))
#define USB_CR_LPM_WKUP_EN            USB_CR_LPM_WKUP_EN
#define USB_CR_LPM_WKUP_EN_POS        (28U)
#define USB_CR_LPM_WKUP_EN_LEN        (1U)
#define USB_CR_LPM_WKUP_EN_MSK        (((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS)
#define USB_CR_LPM_WKUP_EN_UMSK       (~(((1U << USB_CR_LPM_WKUP_EN_LEN) - 1) << USB_CR_LPM_WKUP_EN_POS))
#define USB_CR_LPM_PKT_EN             USB_CR_LPM_PKT_EN
#define USB_CR_LPM_PKT_EN_POS         (29U)
#define USB_CR_LPM_PKT_EN_LEN         (1U)
#define USB_CR_LPM_PKT_EN_MSK         (((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS)
#define USB_CR_LPM_PKT_EN_UMSK        (~(((1U << USB_CR_LPM_PKT_EN_LEN) - 1) << USB_CR_LPM_PKT_EN_POS))
#define USB_CR_SOF_3MS_EN             USB_CR_SOF_3MS_EN
#define USB_CR_SOF_3MS_EN_POS         (30U)
#define USB_CR_SOF_3MS_EN_LEN         (1U)
#define USB_CR_SOF_3MS_EN_MSK         (((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS)
#define USB_CR_SOF_3MS_EN_UMSK        (~(((1U << USB_CR_SOF_3MS_EN_LEN) - 1) << USB_CR_SOF_3MS_EN_POS))
#define USB_CR_USB_ERR_EN             USB_CR_USB_ERR_EN
#define USB_CR_USB_ERR_EN_POS         (31U)
#define USB_CR_USB_ERR_EN_LEN         (1U)
#define USB_CR_USB_ERR_EN_MSK         (((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS)
#define USB_CR_USB_ERR_EN_UMSK        (~(((1U << USB_CR_USB_ERR_EN_LEN) - 1) << USB_CR_USB_ERR_EN_POS))

/* 0x24 : USB interrupt status */
#define USB_INT_STS_OFFSET          (0x24)
#define USB_SOF_INT                 USB_SOF_INT
#define USB_SOF_INT_POS             (0U)
#define USB_SOF_INT_LEN             (1U)
#define USB_SOF_INT_MSK             (((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS)
#define USB_SOF_INT_UMSK            (~(((1U << USB_SOF_INT_LEN) - 1) << USB_SOF_INT_POS))
#define USB_RESET_INT               USB_RESET_INT
#define USB_RESET_INT_POS           (1U)
#define USB_RESET_INT_LEN           (1U)
#define USB_RESET_INT_MSK           (((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS)
#define USB_RESET_INT_UMSK          (~(((1U << USB_RESET_INT_LEN) - 1) << USB_RESET_INT_POS))
#define USB_VBUS_TGL_INT            USB_VBUS_TGL_INT
#define USB_VBUS_TGL_INT_POS        (2U)
#define USB_VBUS_TGL_INT_LEN        (1U)
#define USB_VBUS_TGL_INT_MSK        (((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS)
#define USB_VBUS_TGL_INT_UMSK       (~(((1U << USB_VBUS_TGL_INT_LEN) - 1) << USB_VBUS_TGL_INT_POS))
#define USB_GET_DCT_CMD_INT         USB_GET_DCT_CMD_INT
#define USB_GET_DCT_CMD_INT_POS     (3U)
#define USB_GET_DCT_CMD_INT_LEN     (1U)
#define USB_GET_DCT_CMD_INT_MSK     (((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS)
#define USB_GET_DCT_CMD_INT_UMSK    (~(((1U << USB_GET_DCT_CMD_INT_LEN) - 1) << USB_GET_DCT_CMD_INT_POS))
#define USB_EP0_SETUP_CMD_INT       USB_EP0_SETUP_CMD_INT
#define USB_EP0_SETUP_CMD_INT_POS   (4U)
#define USB_EP0_SETUP_CMD_INT_LEN   (1U)
#define USB_EP0_SETUP_CMD_INT_MSK   (((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS)
#define USB_EP0_SETUP_CMD_INT_UMSK  (~(((1U << USB_EP0_SETUP_CMD_INT_LEN) - 1) << USB_EP0_SETUP_CMD_INT_POS))
#define USB_EP0_SETUP_DONE_INT      USB_EP0_SETUP_DONE_INT
#define USB_EP0_SETUP_DONE_INT_POS  (5U)
#define USB_EP0_SETUP_DONE_INT_LEN  (1U)
#define USB_EP0_SETUP_DONE_INT_MSK  (((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS)
#define USB_EP0_SETUP_DONE_INT_UMSK (~(((1U << USB_EP0_SETUP_DONE_INT_LEN) - 1) << USB_EP0_SETUP_DONE_INT_POS))
#define USB_EP0_IN_CMD_INT          USB_EP0_IN_CMD_INT
#define USB_EP0_IN_CMD_INT_POS      (6U)
#define USB_EP0_IN_CMD_INT_LEN      (1U)
#define USB_EP0_IN_CMD_INT_MSK      (((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS)
#define USB_EP0_IN_CMD_INT_UMSK     (~(((1U << USB_EP0_IN_CMD_INT_LEN) - 1) << USB_EP0_IN_CMD_INT_POS))
#define USB_EP0_IN_DONE_INT         USB_EP0_IN_DONE_INT
#define USB_EP0_IN_DONE_INT_POS     (7U)
#define USB_EP0_IN_DONE_INT_LEN     (1U)
#define USB_EP0_IN_DONE_INT_MSK     (((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS)
#define USB_EP0_IN_DONE_INT_UMSK    (~(((1U << USB_EP0_IN_DONE_INT_LEN) - 1) << USB_EP0_IN_DONE_INT_POS))
#define USB_EP0_OUT_CMD_INT         USB_EP0_OUT_CMD_INT
#define USB_EP0_OUT_CMD_INT_POS     (8U)
#define USB_EP0_OUT_CMD_INT_LEN     (1U)
#define USB_EP0_OUT_CMD_INT_MSK     (((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS)
#define USB_EP0_OUT_CMD_INT_UMSK    (~(((1U << USB_EP0_OUT_CMD_INT_LEN) - 1) << USB_EP0_OUT_CMD_INT_POS))
#define USB_EP0_OUT_DONE_INT        USB_EP0_OUT_DONE_INT
#define USB_EP0_OUT_DONE_INT_POS    (9U)
#define USB_EP0_OUT_DONE_INT_LEN    (1U)
#define USB_EP0_OUT_DONE_INT_MSK    (((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS)
#define USB_EP0_OUT_DONE_INT_UMSK   (~(((1U << USB_EP0_OUT_DONE_INT_LEN) - 1) << USB_EP0_OUT_DONE_INT_POS))
#define USB_EP1_CMD_INT             USB_EP1_CMD_INT
#define USB_EP1_CMD_INT_POS         (10U)
#define USB_EP1_CMD_INT_LEN         (1U)
#define USB_EP1_CMD_INT_MSK         (((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS)
#define USB_EP1_CMD_INT_UMSK        (~(((1U << USB_EP1_CMD_INT_LEN) - 1) << USB_EP1_CMD_INT_POS))
#define USB_EP1_DONE_INT            USB_EP1_DONE_INT
#define USB_EP1_DONE_INT_POS        (11U)
#define USB_EP1_DONE_INT_LEN        (1U)
#define USB_EP1_DONE_INT_MSK        (((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS)
#define USB_EP1_DONE_INT_UMSK       (~(((1U << USB_EP1_DONE_INT_LEN) - 1) << USB_EP1_DONE_INT_POS))
#define USB_EP2_CMD_INT             USB_EP2_CMD_INT
#define USB_EP2_CMD_INT_POS         (12U)
#define USB_EP2_CMD_INT_LEN         (1U)
#define USB_EP2_CMD_INT_MSK         (((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS)
#define USB_EP2_CMD_INT_UMSK        (~(((1U << USB_EP2_CMD_INT_LEN) - 1) << USB_EP2_CMD_INT_POS))
#define USB_EP2_DONE_INT            USB_EP2_DONE_INT
#define USB_EP2_DONE_INT_POS        (13U)
#define USB_EP2_DONE_INT_LEN        (1U)
#define USB_EP2_DONE_INT_MSK        (((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS)
#define USB_EP2_DONE_INT_UMSK       (~(((1U << USB_EP2_DONE_INT_LEN) - 1) << USB_EP2_DONE_INT_POS))
#define USB_EP3_CMD_INT             USB_EP3_CMD_INT
#define USB_EP3_CMD_INT_POS         (14U)
#define USB_EP3_CMD_INT_LEN         (1U)
#define USB_EP3_CMD_INT_MSK         (((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS)
#define USB_EP3_CMD_INT_UMSK        (~(((1U << USB_EP3_CMD_INT_LEN) - 1) << USB_EP3_CMD_INT_POS))
#define USB_EP3_DONE_INT            USB_EP3_DONE_INT
#define USB_EP3_DONE_INT_POS        (15U)
#define USB_EP3_DONE_INT_LEN        (1U)
#define USB_EP3_DONE_INT_MSK        (((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS)
#define USB_EP3_DONE_INT_UMSK       (~(((1U << USB_EP3_DONE_INT_LEN) - 1) << USB_EP3_DONE_INT_POS))
#define USB_EP4_CMD_INT             USB_EP4_CMD_INT
#define USB_EP4_CMD_INT_POS         (16U)
#define USB_EP4_CMD_INT_LEN         (1U)
#define USB_EP4_CMD_INT_MSK         (((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS)
#define USB_EP4_CMD_INT_UMSK        (~(((1U << USB_EP4_CMD_INT_LEN) - 1) << USB_EP4_CMD_INT_POS))
#define USB_EP4_DONE_INT            USB_EP4_DONE_INT
#define USB_EP4_DONE_INT_POS        (17U)
#define USB_EP4_DONE_INT_LEN        (1U)
#define USB_EP4_DONE_INT_MSK        (((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS)
#define USB_EP4_DONE_INT_UMSK       (~(((1U << USB_EP4_DONE_INT_LEN) - 1) << USB_EP4_DONE_INT_POS))
#define USB_EP5_CMD_INT             USB_EP5_CMD_INT
#define USB_EP5_CMD_INT_POS         (18U)
#define USB_EP5_CMD_INT_LEN         (1U)
#define USB_EP5_CMD_INT_MSK         (((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS)
#define USB_EP5_CMD_INT_UMSK        (~(((1U << USB_EP5_CMD_INT_LEN) - 1) << USB_EP5_CMD_INT_POS))
#define USB_EP5_DONE_INT            USB_EP5_DONE_INT
#define USB_EP5_DONE_INT_POS        (19U)
#define USB_EP5_DONE_INT_LEN        (1U)
#define USB_EP5_DONE_INT_MSK        (((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS)
#define USB_EP5_DONE_INT_UMSK       (~(((1U << USB_EP5_DONE_INT_LEN) - 1) << USB_EP5_DONE_INT_POS))
#define USB_EP6_CMD_INT             USB_EP6_CMD_INT
#define USB_EP6_CMD_INT_POS         (20U)
#define USB_EP6_CMD_INT_LEN         (1U)
#define USB_EP6_CMD_INT_MSK         (((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS)
#define USB_EP6_CMD_INT_UMSK        (~(((1U << USB_EP6_CMD_INT_LEN) - 1) << USB_EP6_CMD_INT_POS))
#define USB_EP6_DONE_INT            USB_EP6_DONE_INT
#define USB_EP6_DONE_INT_POS        (21U)
#define USB_EP6_DONE_INT_LEN        (1U)
#define USB_EP6_DONE_INT_MSK        (((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS)
#define USB_EP6_DONE_INT_UMSK       (~(((1U << USB_EP6_DONE_INT_LEN) - 1) << USB_EP6_DONE_INT_POS))
#define USB_EP7_CMD_INT             USB_EP7_CMD_INT
#define USB_EP7_CMD_INT_POS         (22U)
#define USB_EP7_CMD_INT_LEN         (1U)
#define USB_EP7_CMD_INT_MSK         (((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS)
#define USB_EP7_CMD_INT_UMSK        (~(((1U << USB_EP7_CMD_INT_LEN) - 1) << USB_EP7_CMD_INT_POS))
#define USB_EP7_DONE_INT            USB_EP7_DONE_INT
#define USB_EP7_DONE_INT_POS        (23U)
#define USB_EP7_DONE_INT_LEN        (1U)
#define USB_EP7_DONE_INT_MSK        (((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS)
#define USB_EP7_DONE_INT_UMSK       (~(((1U << USB_EP7_DONE_INT_LEN) - 1) << USB_EP7_DONE_INT_POS))
#define USB_REND_INT                USB_REND_INT
#define USB_REND_INT_POS            (27U)
#define USB_REND_INT_LEN            (1U)
#define USB_REND_INT_MSK            (((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS)
#define USB_REND_INT_UMSK           (~(((1U << USB_REND_INT_LEN) - 1) << USB_REND_INT_POS))
#define USB_LPM_WKUP_INT            USB_LPM_WKUP_INT
#define USB_LPM_WKUP_INT_POS        (28U)
#define USB_LPM_WKUP_INT_LEN        (1U)
#define USB_LPM_WKUP_INT_MSK        (((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS)
#define USB_LPM_WKUP_INT_UMSK       (~(((1U << USB_LPM_WKUP_INT_LEN) - 1) << USB_LPM_WKUP_INT_POS))
#define USB_LPM_PKT_INT             USB_LPM_PKT_INT
#define USB_LPM_PKT_INT_POS         (29U)
#define USB_LPM_PKT_INT_LEN         (1U)
#define USB_LPM_PKT_INT_MSK         (((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS)
#define USB_LPM_PKT_INT_UMSK        (~(((1U << USB_LPM_PKT_INT_LEN) - 1) << USB_LPM_PKT_INT_POS))
#define USB_SOF_3MS_INT             USB_SOF_3MS_INT
#define USB_SOF_3MS_INT_POS         (30U)
#define USB_SOF_3MS_INT_LEN         (1U)
#define USB_SOF_3MS_INT_MSK         (((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS)
#define USB_SOF_3MS_INT_UMSK        (~(((1U << USB_SOF_3MS_INT_LEN) - 1) << USB_SOF_3MS_INT_POS))
#define USB_ERR_INT                 USB_ERR_INT
#define USB_ERR_INT_POS             (31U)
#define USB_ERR_INT_LEN             (1U)
#define USB_ERR_INT_MSK             (((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS)
#define USB_ERR_INT_UMSK            (~(((1U << USB_ERR_INT_LEN) - 1) << USB_ERR_INT_POS))

/* 0x28 : USB interrupt mask */
#define USB_INT_MASK_OFFSET             (0x28)
#define USB_CR_SOF_MASK                 USB_CR_SOF_MASK
#define USB_CR_SOF_MASK_POS             (0U)
#define USB_CR_SOF_MASK_LEN             (1U)
#define USB_CR_SOF_MASK_MSK             (((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS)
#define USB_CR_SOF_MASK_UMSK            (~(((1U << USB_CR_SOF_MASK_LEN) - 1) << USB_CR_SOF_MASK_POS))
#define USB_CR_USB_RESET_MASK           USB_CR_USB_RESET_MASK
#define USB_CR_USB_RESET_MASK_POS       (1U)
#define USB_CR_USB_RESET_MASK_LEN       (1U)
#define USB_CR_USB_RESET_MASK_MSK       (((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS)
#define USB_CR_USB_RESET_MASK_UMSK      (~(((1U << USB_CR_USB_RESET_MASK_LEN) - 1) << USB_CR_USB_RESET_MASK_POS))
#define USB_CR_VBUS_TGL_MASK            USB_CR_VBUS_TGL_MASK
#define USB_CR_VBUS_TGL_MASK_POS        (2U)
#define USB_CR_VBUS_TGL_MASK_LEN        (1U)
#define USB_CR_VBUS_TGL_MASK_MSK        (((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS)
#define USB_CR_VBUS_TGL_MASK_UMSK       (~(((1U << USB_CR_VBUS_TGL_MASK_LEN) - 1) << USB_CR_VBUS_TGL_MASK_POS))
#define USB_CR_GET_DCT_CMD_MASK         USB_CR_GET_DCT_CMD_MASK
#define USB_CR_GET_DCT_CMD_MASK_POS     (3U)
#define USB_CR_GET_DCT_CMD_MASK_LEN     (1U)
#define USB_CR_GET_DCT_CMD_MASK_MSK     (((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS)
#define USB_CR_GET_DCT_CMD_MASK_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_MASK_LEN) - 1) << USB_CR_GET_DCT_CMD_MASK_POS))
#define USB_CR_EP0_SETUP_CMD_MASK       USB_CR_EP0_SETUP_CMD_MASK
#define USB_CR_EP0_SETUP_CMD_MASK_POS   (4U)
#define USB_CR_EP0_SETUP_CMD_MASK_LEN   (1U)
#define USB_CR_EP0_SETUP_CMD_MASK_MSK   (((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS)
#define USB_CR_EP0_SETUP_CMD_MASK_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_MASK_LEN) - 1) << USB_CR_EP0_SETUP_CMD_MASK_POS))
#define USB_CR_EP0_SETUP_DONE_MASK      USB_CR_EP0_SETUP_DONE_MASK
#define USB_CR_EP0_SETUP_DONE_MASK_POS  (5U)
#define USB_CR_EP0_SETUP_DONE_MASK_LEN  (1U)
#define USB_CR_EP0_SETUP_DONE_MASK_MSK  (((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS)
#define USB_CR_EP0_SETUP_DONE_MASK_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_MASK_LEN) - 1) << USB_CR_EP0_SETUP_DONE_MASK_POS))
#define USB_CR_EP0_IN_CMD_MASK          USB_CR_EP0_IN_CMD_MASK
#define USB_CR_EP0_IN_CMD_MASK_POS      (6U)
#define USB_CR_EP0_IN_CMD_MASK_LEN      (1U)
#define USB_CR_EP0_IN_CMD_MASK_MSK      (((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS)
#define USB_CR_EP0_IN_CMD_MASK_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_MASK_LEN) - 1) << USB_CR_EP0_IN_CMD_MASK_POS))
#define USB_CR_EP0_IN_DONE_MASK         USB_CR_EP0_IN_DONE_MASK
#define USB_CR_EP0_IN_DONE_MASK_POS     (7U)
#define USB_CR_EP0_IN_DONE_MASK_LEN     (1U)
#define USB_CR_EP0_IN_DONE_MASK_MSK     (((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS)
#define USB_CR_EP0_IN_DONE_MASK_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_MASK_LEN) - 1) << USB_CR_EP0_IN_DONE_MASK_POS))
#define USB_CR_EP0_OUT_CMD_MASK         USB_CR_EP0_OUT_CMD_MASK
#define USB_CR_EP0_OUT_CMD_MASK_POS     (8U)
#define USB_CR_EP0_OUT_CMD_MASK_LEN     (1U)
#define USB_CR_EP0_OUT_CMD_MASK_MSK     (((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS)
#define USB_CR_EP0_OUT_CMD_MASK_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_MASK_LEN) - 1) << USB_CR_EP0_OUT_CMD_MASK_POS))
#define USB_CR_EP0_OUT_DONE_MASK        USB_CR_EP0_OUT_DONE_MASK
#define USB_CR_EP0_OUT_DONE_MASK_POS    (9U)
#define USB_CR_EP0_OUT_DONE_MASK_LEN    (1U)
#define USB_CR_EP0_OUT_DONE_MASK_MSK    (((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS)
#define USB_CR_EP0_OUT_DONE_MASK_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_MASK_LEN) - 1) << USB_CR_EP0_OUT_DONE_MASK_POS))
#define USB_CR_EP1_CMD_MASK             USB_CR_EP1_CMD_MASK
#define USB_CR_EP1_CMD_MASK_POS         (10U)
#define USB_CR_EP1_CMD_MASK_LEN         (1U)
#define USB_CR_EP1_CMD_MASK_MSK         (((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS)
#define USB_CR_EP1_CMD_MASK_UMSK        (~(((1U << USB_CR_EP1_CMD_MASK_LEN) - 1) << USB_CR_EP1_CMD_MASK_POS))
#define USB_CR_EP1_DONE_MASK            USB_CR_EP1_DONE_MASK
#define USB_CR_EP1_DONE_MASK_POS        (11U)
#define USB_CR_EP1_DONE_MASK_LEN        (1U)
#define USB_CR_EP1_DONE_MASK_MSK        (((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS)
#define USB_CR_EP1_DONE_MASK_UMSK       (~(((1U << USB_CR_EP1_DONE_MASK_LEN) - 1) << USB_CR_EP1_DONE_MASK_POS))
#define USB_CR_EP2_CMD_MASK             USB_CR_EP2_CMD_MASK
#define USB_CR_EP2_CMD_MASK_POS         (12U)
#define USB_CR_EP2_CMD_MASK_LEN         (1U)
#define USB_CR_EP2_CMD_MASK_MSK         (((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS)
#define USB_CR_EP2_CMD_MASK_UMSK        (~(((1U << USB_CR_EP2_CMD_MASK_LEN) - 1) << USB_CR_EP2_CMD_MASK_POS))
#define USB_CR_EP2_DONE_MASK            USB_CR_EP2_DONE_MASK
#define USB_CR_EP2_DONE_MASK_POS        (13U)
#define USB_CR_EP2_DONE_MASK_LEN        (1U)
#define USB_CR_EP2_DONE_MASK_MSK        (((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS)
#define USB_CR_EP2_DONE_MASK_UMSK       (~(((1U << USB_CR_EP2_DONE_MASK_LEN) - 1) << USB_CR_EP2_DONE_MASK_POS))
#define USB_CR_EP3_CMD_MASK             USB_CR_EP3_CMD_MASK
#define USB_CR_EP3_CMD_MASK_POS         (14U)
#define USB_CR_EP3_CMD_MASK_LEN         (1U)
#define USB_CR_EP3_CMD_MASK_MSK         (((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS)
#define USB_CR_EP3_CMD_MASK_UMSK        (~(((1U << USB_CR_EP3_CMD_MASK_LEN) - 1) << USB_CR_EP3_CMD_MASK_POS))
#define USB_CR_EP3_DONE_MASK            USB_CR_EP3_DONE_MASK
#define USB_CR_EP3_DONE_MASK_POS        (15U)
#define USB_CR_EP3_DONE_MASK_LEN        (1U)
#define USB_CR_EP3_DONE_MASK_MSK        (((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS)
#define USB_CR_EP3_DONE_MASK_UMSK       (~(((1U << USB_CR_EP3_DONE_MASK_LEN) - 1) << USB_CR_EP3_DONE_MASK_POS))
#define USB_CR_EP4_CMD_MASK             USB_CR_EP4_CMD_MASK
#define USB_CR_EP4_CMD_MASK_POS         (16U)
#define USB_CR_EP4_CMD_MASK_LEN         (1U)
#define USB_CR_EP4_CMD_MASK_MSK         (((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS)
#define USB_CR_EP4_CMD_MASK_UMSK        (~(((1U << USB_CR_EP4_CMD_MASK_LEN) - 1) << USB_CR_EP4_CMD_MASK_POS))
#define USB_CR_EP4_DONE_MASK            USB_CR_EP4_DONE_MASK
#define USB_CR_EP4_DONE_MASK_POS        (17U)
#define USB_CR_EP4_DONE_MASK_LEN        (1U)
#define USB_CR_EP4_DONE_MASK_MSK        (((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS)
#define USB_CR_EP4_DONE_MASK_UMSK       (~(((1U << USB_CR_EP4_DONE_MASK_LEN) - 1) << USB_CR_EP4_DONE_MASK_POS))
#define USB_CR_EP5_CMD_MASK             USB_CR_EP5_CMD_MASK
#define USB_CR_EP5_CMD_MASK_POS         (18U)
#define USB_CR_EP5_CMD_MASK_LEN         (1U)
#define USB_CR_EP5_CMD_MASK_MSK         (((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS)
#define USB_CR_EP5_CMD_MASK_UMSK        (~(((1U << USB_CR_EP5_CMD_MASK_LEN) - 1) << USB_CR_EP5_CMD_MASK_POS))
#define USB_CR_EP5_DONE_MASK            USB_CR_EP5_DONE_MASK
#define USB_CR_EP5_DONE_MASK_POS        (19U)
#define USB_CR_EP5_DONE_MASK_LEN        (1U)
#define USB_CR_EP5_DONE_MASK_MSK        (((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS)
#define USB_CR_EP5_DONE_MASK_UMSK       (~(((1U << USB_CR_EP5_DONE_MASK_LEN) - 1) << USB_CR_EP5_DONE_MASK_POS))
#define USB_CR_EP6_CMD_MASK             USB_CR_EP6_CMD_MASK
#define USB_CR_EP6_CMD_MASK_POS         (20U)
#define USB_CR_EP6_CMD_MASK_LEN         (1U)
#define USB_CR_EP6_CMD_MASK_MSK         (((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS)
#define USB_CR_EP6_CMD_MASK_UMSK        (~(((1U << USB_CR_EP6_CMD_MASK_LEN) - 1) << USB_CR_EP6_CMD_MASK_POS))
#define USB_CR_EP6_DONE_MASK            USB_CR_EP6_DONE_MASK
#define USB_CR_EP6_DONE_MASK_POS        (21U)
#define USB_CR_EP6_DONE_MASK_LEN        (1U)
#define USB_CR_EP6_DONE_MASK_MSK        (((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS)
#define USB_CR_EP6_DONE_MASK_UMSK       (~(((1U << USB_CR_EP6_DONE_MASK_LEN) - 1) << USB_CR_EP6_DONE_MASK_POS))
#define USB_CR_EP7_CMD_MASK             USB_CR_EP7_CMD_MASK
#define USB_CR_EP7_CMD_MASK_POS         (22U)
#define USB_CR_EP7_CMD_MASK_LEN         (1U)
#define USB_CR_EP7_CMD_MASK_MSK         (((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS)
#define USB_CR_EP7_CMD_MASK_UMSK        (~(((1U << USB_CR_EP7_CMD_MASK_LEN) - 1) << USB_CR_EP7_CMD_MASK_POS))
#define USB_CR_EP7_DONE_MASK            USB_CR_EP7_DONE_MASK
#define USB_CR_EP7_DONE_MASK_POS        (23U)
#define USB_CR_EP7_DONE_MASK_LEN        (1U)
#define USB_CR_EP7_DONE_MASK_MSK        (((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS)
#define USB_CR_EP7_DONE_MASK_UMSK       (~(((1U << USB_CR_EP7_DONE_MASK_LEN) - 1) << USB_CR_EP7_DONE_MASK_POS))
#define USB_CR_USB_REND_MASK            USB_CR_USB_REND_MASK
#define USB_CR_USB_REND_MASK_POS        (27U)
#define USB_CR_USB_REND_MASK_LEN        (1U)
#define USB_CR_USB_REND_MASK_MSK        (((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS)
#define USB_CR_USB_REND_MASK_UMSK       (~(((1U << USB_CR_USB_REND_MASK_LEN) - 1) << USB_CR_USB_REND_MASK_POS))
#define USB_CR_LPM_WKUP_MASK            USB_CR_LPM_WKUP_MASK
#define USB_CR_LPM_WKUP_MASK_POS        (28U)
#define USB_CR_LPM_WKUP_MASK_LEN        (1U)
#define USB_CR_LPM_WKUP_MASK_MSK        (((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS)
#define USB_CR_LPM_WKUP_MASK_UMSK       (~(((1U << USB_CR_LPM_WKUP_MASK_LEN) - 1) << USB_CR_LPM_WKUP_MASK_POS))
#define USB_CR_LPM_PKT_MASK             USB_CR_LPM_PKT_MASK
#define USB_CR_LPM_PKT_MASK_POS         (29U)
#define USB_CR_LPM_PKT_MASK_LEN         (1U)
#define USB_CR_LPM_PKT_MASK_MSK         (((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS)
#define USB_CR_LPM_PKT_MASK_UMSK        (~(((1U << USB_CR_LPM_PKT_MASK_LEN) - 1) << USB_CR_LPM_PKT_MASK_POS))
#define USB_CR_SOF_3MS_MASK             USB_CR_SOF_3MS_MASK
#define USB_CR_SOF_3MS_MASK_POS         (30U)
#define USB_CR_SOF_3MS_MASK_LEN         (1U)
#define USB_CR_SOF_3MS_MASK_MSK         (((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS)
#define USB_CR_SOF_3MS_MASK_UMSK        (~(((1U << USB_CR_SOF_3MS_MASK_LEN) - 1) << USB_CR_SOF_3MS_MASK_POS))
#define USB_CR_USB_ERR_MASK             USB_CR_USB_ERR_MASK
#define USB_CR_USB_ERR_MASK_POS         (31U)
#define USB_CR_USB_ERR_MASK_LEN         (1U)
#define USB_CR_USB_ERR_MASK_MSK         (((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS)
#define USB_CR_USB_ERR_MASK_UMSK        (~(((1U << USB_CR_USB_ERR_MASK_LEN) - 1) << USB_CR_USB_ERR_MASK_POS))

/* 0x2C : USB interrupt clear */
#define USB_INT_CLEAR_OFFSET           (0x2C)
#define USB_CR_SOF_CLR                 USB_CR_SOF_CLR
#define USB_CR_SOF_CLR_POS             (0U)
#define USB_CR_SOF_CLR_LEN             (1U)
#define USB_CR_SOF_CLR_MSK             (((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS)
#define USB_CR_SOF_CLR_UMSK            (~(((1U << USB_CR_SOF_CLR_LEN) - 1) << USB_CR_SOF_CLR_POS))
#define USB_CR_USB_RESET_CLR           USB_CR_USB_RESET_CLR
#define USB_CR_USB_RESET_CLR_POS       (1U)
#define USB_CR_USB_RESET_CLR_LEN       (1U)
#define USB_CR_USB_RESET_CLR_MSK       (((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS)
#define USB_CR_USB_RESET_CLR_UMSK      (~(((1U << USB_CR_USB_RESET_CLR_LEN) - 1) << USB_CR_USB_RESET_CLR_POS))
#define USB_CR_VBUS_TGL_CLR            USB_CR_VBUS_TGL_CLR
#define USB_CR_VBUS_TGL_CLR_POS        (2U)
#define USB_CR_VBUS_TGL_CLR_LEN        (1U)
#define USB_CR_VBUS_TGL_CLR_MSK        (((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS)
#define USB_CR_VBUS_TGL_CLR_UMSK       (~(((1U << USB_CR_VBUS_TGL_CLR_LEN) - 1) << USB_CR_VBUS_TGL_CLR_POS))
#define USB_CR_GET_DCT_CMD_CLR         USB_CR_GET_DCT_CMD_CLR
#define USB_CR_GET_DCT_CMD_CLR_POS     (3U)
#define USB_CR_GET_DCT_CMD_CLR_LEN     (1U)
#define USB_CR_GET_DCT_CMD_CLR_MSK     (((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS)
#define USB_CR_GET_DCT_CMD_CLR_UMSK    (~(((1U << USB_CR_GET_DCT_CMD_CLR_LEN) - 1) << USB_CR_GET_DCT_CMD_CLR_POS))
#define USB_CR_EP0_SETUP_CMD_CLR       USB_CR_EP0_SETUP_CMD_CLR
#define USB_CR_EP0_SETUP_CMD_CLR_POS   (4U)
#define USB_CR_EP0_SETUP_CMD_CLR_LEN   (1U)
#define USB_CR_EP0_SETUP_CMD_CLR_MSK   (((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS)
#define USB_CR_EP0_SETUP_CMD_CLR_UMSK  (~(((1U << USB_CR_EP0_SETUP_CMD_CLR_LEN) - 1) << USB_CR_EP0_SETUP_CMD_CLR_POS))
#define USB_CR_EP0_SETUP_DONE_CLR      USB_CR_EP0_SETUP_DONE_CLR
#define USB_CR_EP0_SETUP_DONE_CLR_POS  (5U)
#define USB_CR_EP0_SETUP_DONE_CLR_LEN  (1U)
#define USB_CR_EP0_SETUP_DONE_CLR_MSK  (((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS)
#define USB_CR_EP0_SETUP_DONE_CLR_UMSK (~(((1U << USB_CR_EP0_SETUP_DONE_CLR_LEN) - 1) << USB_CR_EP0_SETUP_DONE_CLR_POS))
#define USB_CR_EP0_IN_CMD_CLR          USB_CR_EP0_IN_CMD_CLR
#define USB_CR_EP0_IN_CMD_CLR_POS      (6U)
#define USB_CR_EP0_IN_CMD_CLR_LEN      (1U)
#define USB_CR_EP0_IN_CMD_CLR_MSK      (((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS)
#define USB_CR_EP0_IN_CMD_CLR_UMSK     (~(((1U << USB_CR_EP0_IN_CMD_CLR_LEN) - 1) << USB_CR_EP0_IN_CMD_CLR_POS))
#define USB_CR_EP0_IN_DONE_CLR         USB_CR_EP0_IN_DONE_CLR
#define USB_CR_EP0_IN_DONE_CLR_POS     (7U)
#define USB_CR_EP0_IN_DONE_CLR_LEN     (1U)
#define USB_CR_EP0_IN_DONE_CLR_MSK     (((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS)
#define USB_CR_EP0_IN_DONE_CLR_UMSK    (~(((1U << USB_CR_EP0_IN_DONE_CLR_LEN) - 1) << USB_CR_EP0_IN_DONE_CLR_POS))
#define USB_CR_EP0_OUT_CMD_CLR         USB_CR_EP0_OUT_CMD_CLR
#define USB_CR_EP0_OUT_CMD_CLR_POS     (8U)
#define USB_CR_EP0_OUT_CMD_CLR_LEN     (1U)
#define USB_CR_EP0_OUT_CMD_CLR_MSK     (((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS)
#define USB_CR_EP0_OUT_CMD_CLR_UMSK    (~(((1U << USB_CR_EP0_OUT_CMD_CLR_LEN) - 1) << USB_CR_EP0_OUT_CMD_CLR_POS))
#define USB_CR_EP0_OUT_DONE_CLR        USB_CR_EP0_OUT_DONE_CLR
#define USB_CR_EP0_OUT_DONE_CLR_POS    (9U)
#define USB_CR_EP0_OUT_DONE_CLR_LEN    (1U)
#define USB_CR_EP0_OUT_DONE_CLR_MSK    (((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS)
#define USB_CR_EP0_OUT_DONE_CLR_UMSK   (~(((1U << USB_CR_EP0_OUT_DONE_CLR_LEN) - 1) << USB_CR_EP0_OUT_DONE_CLR_POS))
#define USB_CR_EP1_CMD_CLR             USB_CR_EP1_CMD_CLR
#define USB_CR_EP1_CMD_CLR_POS         (10U)
#define USB_CR_EP1_CMD_CLR_LEN         (1U)
#define USB_CR_EP1_CMD_CLR_MSK         (((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS)
#define USB_CR_EP1_CMD_CLR_UMSK        (~(((1U << USB_CR_EP1_CMD_CLR_LEN) - 1) << USB_CR_EP1_CMD_CLR_POS))
#define USB_CR_EP1_DONE_CLR            USB_CR_EP1_DONE_CLR
#define USB_CR_EP1_DONE_CLR_POS        (11U)
#define USB_CR_EP1_DONE_CLR_LEN        (1U)
#define USB_CR_EP1_DONE_CLR_MSK        (((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS)
#define USB_CR_EP1_DONE_CLR_UMSK       (~(((1U << USB_CR_EP1_DONE_CLR_LEN) - 1) << USB_CR_EP1_DONE_CLR_POS))
#define USB_CR_EP2_CMD_CLR             USB_CR_EP2_CMD_CLR
#define USB_CR_EP2_CMD_CLR_POS         (12U)
#define USB_CR_EP2_CMD_CLR_LEN         (1U)
#define USB_CR_EP2_CMD_CLR_MSK         (((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS)
#define USB_CR_EP2_CMD_CLR_UMSK        (~(((1U << USB_CR_EP2_CMD_CLR_LEN) - 1) << USB_CR_EP2_CMD_CLR_POS))
#define USB_CR_EP2_DONE_CLR            USB_CR_EP2_DONE_CLR
#define USB_CR_EP2_DONE_CLR_POS        (13U)
#define USB_CR_EP2_DONE_CLR_LEN        (1U)
#define USB_CR_EP2_DONE_CLR_MSK        (((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS)
#define USB_CR_EP2_DONE_CLR_UMSK       (~(((1U << USB_CR_EP2_DONE_CLR_LEN) - 1) << USB_CR_EP2_DONE_CLR_POS))
#define USB_CR_EP3_CMD_CLR             USB_CR_EP3_CMD_CLR
#define USB_CR_EP3_CMD_CLR_POS         (14U)
#define USB_CR_EP3_CMD_CLR_LEN         (1U)
#define USB_CR_EP3_CMD_CLR_MSK         (((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS)
#define USB_CR_EP3_CMD_CLR_UMSK        (~(((1U << USB_CR_EP3_CMD_CLR_LEN) - 1) << USB_CR_EP3_CMD_CLR_POS))
#define USB_CR_EP3_DONE_CLR            USB_CR_EP3_DONE_CLR
#define USB_CR_EP3_DONE_CLR_POS        (15U)
#define USB_CR_EP3_DONE_CLR_LEN        (1U)
#define USB_CR_EP3_DONE_CLR_MSK        (((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS)
#define USB_CR_EP3_DONE_CLR_UMSK       (~(((1U << USB_CR_EP3_DONE_CLR_LEN) - 1) << USB_CR_EP3_DONE_CLR_POS))
#define USB_CR_EP4_CMD_CLR             USB_CR_EP4_CMD_CLR
#define USB_CR_EP4_CMD_CLR_POS         (16U)
#define USB_CR_EP4_CMD_CLR_LEN         (1U)
#define USB_CR_EP4_CMD_CLR_MSK         (((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS)
#define USB_CR_EP4_CMD_CLR_UMSK        (~(((1U << USB_CR_EP4_CMD_CLR_LEN) - 1) << USB_CR_EP4_CMD_CLR_POS))
#define USB_CR_EP4_DONE_CLR            USB_CR_EP4_DONE_CLR
#define USB_CR_EP4_DONE_CLR_POS        (17U)
#define USB_CR_EP4_DONE_CLR_LEN        (1U)
#define USB_CR_EP4_DONE_CLR_MSK        (((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS)
#define USB_CR_EP4_DONE_CLR_UMSK       (~(((1U << USB_CR_EP4_DONE_CLR_LEN) - 1) << USB_CR_EP4_DONE_CLR_POS))
#define USB_CR_EP5_CMD_CLR             USB_CR_EP5_CMD_CLR
#define USB_CR_EP5_CMD_CLR_POS         (18U)
#define USB_CR_EP5_CMD_CLR_LEN         (1U)
#define USB_CR_EP5_CMD_CLR_MSK         (((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS)
#define USB_CR_EP5_CMD_CLR_UMSK        (~(((1U << USB_CR_EP5_CMD_CLR_LEN) - 1) << USB_CR_EP5_CMD_CLR_POS))
#define USB_CR_EP5_DONE_CLR            USB_CR_EP5_DONE_CLR
#define USB_CR_EP5_DONE_CLR_POS        (19U)
#define USB_CR_EP5_DONE_CLR_LEN        (1U)
#define USB_CR_EP5_DONE_CLR_MSK        (((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS)
#define USB_CR_EP5_DONE_CLR_UMSK       (~(((1U << USB_CR_EP5_DONE_CLR_LEN) - 1) << USB_CR_EP5_DONE_CLR_POS))
#define USB_CR_EP6_CMD_CLR             USB_CR_EP6_CMD_CLR
#define USB_CR_EP6_CMD_CLR_POS         (20U)
#define USB_CR_EP6_CMD_CLR_LEN         (1U)
#define USB_CR_EP6_CMD_CLR_MSK         (((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS)
#define USB_CR_EP6_CMD_CLR_UMSK        (~(((1U << USB_CR_EP6_CMD_CLR_LEN) - 1) << USB_CR_EP6_CMD_CLR_POS))
#define USB_CR_EP6_DONE_CLR            USB_CR_EP6_DONE_CLR
#define USB_CR_EP6_DONE_CLR_POS        (21U)
#define USB_CR_EP6_DONE_CLR_LEN        (1U)
#define USB_CR_EP6_DONE_CLR_MSK        (((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS)
#define USB_CR_EP6_DONE_CLR_UMSK       (~(((1U << USB_CR_EP6_DONE_CLR_LEN) - 1) << USB_CR_EP6_DONE_CLR_POS))
#define USB_CR_EP7_CMD_CLR             USB_CR_EP7_CMD_CLR
#define USB_CR_EP7_CMD_CLR_POS         (22U)
#define USB_CR_EP7_CMD_CLR_LEN         (1U)
#define USB_CR_EP7_CMD_CLR_MSK         (((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS)
#define USB_CR_EP7_CMD_CLR_UMSK        (~(((1U << USB_CR_EP7_CMD_CLR_LEN) - 1) << USB_CR_EP7_CMD_CLR_POS))
#define USB_CR_EP7_DONE_CLR            USB_CR_EP7_DONE_CLR
#define USB_CR_EP7_DONE_CLR_POS        (23U)
#define USB_CR_EP7_DONE_CLR_LEN        (1U)
#define USB_CR_EP7_DONE_CLR_MSK        (((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS)
#define USB_CR_EP7_DONE_CLR_UMSK       (~(((1U << USB_CR_EP7_DONE_CLR_LEN) - 1) << USB_CR_EP7_DONE_CLR_POS))
#define USB_CR_USB_REND_CLR            USB_CR_USB_REND_CLR
#define USB_CR_USB_REND_CLR_POS        (27U)
#define USB_CR_USB_REND_CLR_LEN        (1U)
#define USB_CR_USB_REND_CLR_MSK        (((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS)
#define USB_CR_USB_REND_CLR_UMSK       (~(((1U << USB_CR_USB_REND_CLR_LEN) - 1) << USB_CR_USB_REND_CLR_POS))
#define USB_CR_LPM_WKUP_CLR            USB_CR_LPM_WKUP_CLR
#define USB_CR_LPM_WKUP_CLR_POS        (28U)
#define USB_CR_LPM_WKUP_CLR_LEN        (1U)
#define USB_CR_LPM_WKUP_CLR_MSK        (((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS)
#define USB_CR_LPM_WKUP_CLR_UMSK       (~(((1U << USB_CR_LPM_WKUP_CLR_LEN) - 1) << USB_CR_LPM_WKUP_CLR_POS))
#define USB_CR_LPM_PKT_CLR             USB_CR_LPM_PKT_CLR
#define USB_CR_LPM_PKT_CLR_POS         (29U)
#define USB_CR_LPM_PKT_CLR_LEN         (1U)
#define USB_CR_LPM_PKT_CLR_MSK         (((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS)
#define USB_CR_LPM_PKT_CLR_UMSK        (~(((1U << USB_CR_LPM_PKT_CLR_LEN) - 1) << USB_CR_LPM_PKT_CLR_POS))
#define USB_CR_SOF_3MS_CLR             USB_CR_SOF_3MS_CLR
#define USB_CR_SOF_3MS_CLR_POS         (30U)
#define USB_CR_SOF_3MS_CLR_LEN         (1U)
#define USB_CR_SOF_3MS_CLR_MSK         (((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS)
#define USB_CR_SOF_3MS_CLR_UMSK        (~(((1U << USB_CR_SOF_3MS_CLR_LEN) - 1) << USB_CR_SOF_3MS_CLR_POS))
#define USB_CR_USB_ERR_CLR             USB_CR_USB_ERR_CLR
#define USB_CR_USB_ERR_CLR_POS         (31U)
#define USB_CR_USB_ERR_CLR_LEN         (1U)
#define USB_CR_USB_ERR_CLR_MSK         (((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS)
#define USB_CR_USB_ERR_CLR_UMSK        (~(((1U << USB_CR_USB_ERR_CLR_LEN) - 1) << USB_CR_USB_ERR_CLR_POS))

/* 0x40 : ep1_config */
#define USB_EP1_CONFIG_OFFSET (0x40)
#define USB_CR_EP1_SIZE       USB_CR_EP1_SIZE
#define USB_CR_EP1_SIZE_POS   (0U)
#define USB_CR_EP1_SIZE_LEN   (11U)
#define USB_CR_EP1_SIZE_MSK   (((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS)
#define USB_CR_EP1_SIZE_UMSK  (~(((1U << USB_CR_EP1_SIZE_LEN) - 1) << USB_CR_EP1_SIZE_POS))
#define USB_CR_EP1_DIR        USB_CR_EP1_DIR
#define USB_CR_EP1_DIR_POS    (11U)
#define USB_CR_EP1_DIR_LEN    (2U)
#define USB_CR_EP1_DIR_MSK    (((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS)
#define USB_CR_EP1_DIR_UMSK   (~(((1U << USB_CR_EP1_DIR_LEN) - 1) << USB_CR_EP1_DIR_POS))
#define USB_CR_EP1_TYPE       USB_CR_EP1_TYPE
#define USB_CR_EP1_TYPE_POS   (13U)
#define USB_CR_EP1_TYPE_LEN   (3U)
#define USB_CR_EP1_TYPE_MSK   (((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS)
#define USB_CR_EP1_TYPE_UMSK  (~(((1U << USB_CR_EP1_TYPE_LEN) - 1) << USB_CR_EP1_TYPE_POS))
#define USB_CR_EP1_STALL      USB_CR_EP1_STALL
#define USB_CR_EP1_STALL_POS  (16U)
#define USB_CR_EP1_STALL_LEN  (1U)
#define USB_CR_EP1_STALL_MSK  (((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS)
#define USB_CR_EP1_STALL_UMSK (~(((1U << USB_CR_EP1_STALL_LEN) - 1) << USB_CR_EP1_STALL_POS))
#define USB_CR_EP1_NACK       USB_CR_EP1_NACK
#define USB_CR_EP1_NACK_POS   (17U)
#define USB_CR_EP1_NACK_LEN   (1U)
#define USB_CR_EP1_NACK_MSK   (((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS)
#define USB_CR_EP1_NACK_UMSK  (~(((1U << USB_CR_EP1_NACK_LEN) - 1) << USB_CR_EP1_NACK_POS))
#define USB_CR_EP1_RDY        USB_CR_EP1_RDY
#define USB_CR_EP1_RDY_POS    (18U)
#define USB_CR_EP1_RDY_LEN    (1U)
#define USB_CR_EP1_RDY_MSK    (((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS)
#define USB_CR_EP1_RDY_UMSK   (~(((1U << USB_CR_EP1_RDY_LEN) - 1) << USB_CR_EP1_RDY_POS))
#define USB_STS_EP1_RDY       USB_STS_EP1_RDY
#define USB_STS_EP1_RDY_POS   (19U)
#define USB_STS_EP1_RDY_LEN   (1U)
#define USB_STS_EP1_RDY_MSK   (((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS)
#define USB_STS_EP1_RDY_UMSK  (~(((1U << USB_STS_EP1_RDY_LEN) - 1) << USB_STS_EP1_RDY_POS))

/* 0x44 : ep2_config */
#define USB_EP2_CONFIG_OFFSET (0x44)
#define USB_CR_EP2_SIZE       USB_CR_EP2_SIZE
#define USB_CR_EP2_SIZE_POS   (0U)
#define USB_CR_EP2_SIZE_LEN   (11U)
#define USB_CR_EP2_SIZE_MSK   (((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS)
#define USB_CR_EP2_SIZE_UMSK  (~(((1U << USB_CR_EP2_SIZE_LEN) - 1) << USB_CR_EP2_SIZE_POS))
#define USB_CR_EP2_DIR        USB_CR_EP2_DIR
#define USB_CR_EP2_DIR_POS    (11U)
#define USB_CR_EP2_DIR_LEN    (2U)
#define USB_CR_EP2_DIR_MSK    (((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS)
#define USB_CR_EP2_DIR_UMSK   (~(((1U << USB_CR_EP2_DIR_LEN) - 1) << USB_CR_EP2_DIR_POS))
#define USB_CR_EP2_TYPE       USB_CR_EP2_TYPE
#define USB_CR_EP2_TYPE_POS   (13U)
#define USB_CR_EP2_TYPE_LEN   (3U)
#define USB_CR_EP2_TYPE_MSK   (((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS)
#define USB_CR_EP2_TYPE_UMSK  (~(((1U << USB_CR_EP2_TYPE_LEN) - 1) << USB_CR_EP2_TYPE_POS))
#define USB_CR_EP2_STALL      USB_CR_EP2_STALL
#define USB_CR_EP2_STALL_POS  (16U)
#define USB_CR_EP2_STALL_LEN  (1U)
#define USB_CR_EP2_STALL_MSK  (((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS)
#define USB_CR_EP2_STALL_UMSK (~(((1U << USB_CR_EP2_STALL_LEN) - 1) << USB_CR_EP2_STALL_POS))
#define USB_CR_EP2_NACK       USB_CR_EP2_NACK
#define USB_CR_EP2_NACK_POS   (17U)
#define USB_CR_EP2_NACK_LEN   (1U)
#define USB_CR_EP2_NACK_MSK   (((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS)
#define USB_CR_EP2_NACK_UMSK  (~(((1U << USB_CR_EP2_NACK_LEN) - 1) << USB_CR_EP2_NACK_POS))
#define USB_CR_EP2_RDY        USB_CR_EP2_RDY
#define USB_CR_EP2_RDY_POS    (18U)
#define USB_CR_EP2_RDY_LEN    (1U)
#define USB_CR_EP2_RDY_MSK    (((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS)
#define USB_CR_EP2_RDY_UMSK   (~(((1U << USB_CR_EP2_RDY_LEN) - 1) << USB_CR_EP2_RDY_POS))
#define USB_STS_EP2_RDY       USB_STS_EP2_RDY
#define USB_STS_EP2_RDY_POS   (19U)
#define USB_STS_EP2_RDY_LEN   (1U)
#define USB_STS_EP2_RDY_MSK   (((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS)
#define USB_STS_EP2_RDY_UMSK  (~(((1U << USB_STS_EP2_RDY_LEN) - 1) << USB_STS_EP2_RDY_POS))

/* 0x48 : ep3_config */
#define USB_EP3_CONFIG_OFFSET (0x48)
#define USB_CR_EP3_SIZE       USB_CR_EP3_SIZE
#define USB_CR_EP3_SIZE_POS   (0U)
#define USB_CR_EP3_SIZE_LEN   (11U)
#define USB_CR_EP3_SIZE_MSK   (((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS)
#define USB_CR_EP3_SIZE_UMSK  (~(((1U << USB_CR_EP3_SIZE_LEN) - 1) << USB_CR_EP3_SIZE_POS))
#define USB_CR_EP3_DIR        USB_CR_EP3_DIR
#define USB_CR_EP3_DIR_POS    (11U)
#define USB_CR_EP3_DIR_LEN    (2U)
#define USB_CR_EP3_DIR_MSK    (((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS)
#define USB_CR_EP3_DIR_UMSK   (~(((1U << USB_CR_EP3_DIR_LEN) - 1) << USB_CR_EP3_DIR_POS))
#define USB_CR_EP3_TYPE       USB_CR_EP3_TYPE
#define USB_CR_EP3_TYPE_POS   (13U)
#define USB_CR_EP3_TYPE_LEN   (3U)
#define USB_CR_EP3_TYPE_MSK   (((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS)
#define USB_CR_EP3_TYPE_UMSK  (~(((1U << USB_CR_EP3_TYPE_LEN) - 1) << USB_CR_EP3_TYPE_POS))
#define USB_CR_EP3_STALL      USB_CR_EP3_STALL
#define USB_CR_EP3_STALL_POS  (16U)
#define USB_CR_EP3_STALL_LEN  (1U)
#define USB_CR_EP3_STALL_MSK  (((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS)
#define USB_CR_EP3_STALL_UMSK (~(((1U << USB_CR_EP3_STALL_LEN) - 1) << USB_CR_EP3_STALL_POS))
#define USB_CR_EP3_NACK       USB_CR_EP3_NACK
#define USB_CR_EP3_NACK_POS   (17U)
#define USB_CR_EP3_NACK_LEN   (1U)
#define USB_CR_EP3_NACK_MSK   (((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS)
#define USB_CR_EP3_NACK_UMSK  (~(((1U << USB_CR_EP3_NACK_LEN) - 1) << USB_CR_EP3_NACK_POS))
#define USB_CR_EP3_RDY        USB_CR_EP3_RDY
#define USB_CR_EP3_RDY_POS    (18U)
#define USB_CR_EP3_RDY_LEN    (1U)
#define USB_CR_EP3_RDY_MSK    (((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS)
#define USB_CR_EP3_RDY_UMSK   (~(((1U << USB_CR_EP3_RDY_LEN) - 1) << USB_CR_EP3_RDY_POS))
#define USB_STS_EP3_RDY       USB_STS_EP3_RDY
#define USB_STS_EP3_RDY_POS   (19U)
#define USB_STS_EP3_RDY_LEN   (1U)
#define USB_STS_EP3_RDY_MSK   (((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS)
#define USB_STS_EP3_RDY_UMSK  (~(((1U << USB_STS_EP3_RDY_LEN) - 1) << USB_STS_EP3_RDY_POS))

/* 0x4C : ep4_config */
#define USB_EP4_CONFIG_OFFSET (0x4C)
#define USB_CR_EP4_SIZE       USB_CR_EP4_SIZE
#define USB_CR_EP4_SIZE_POS   (0U)
#define USB_CR_EP4_SIZE_LEN   (11U)
#define USB_CR_EP4_SIZE_MSK   (((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS)
#define USB_CR_EP4_SIZE_UMSK  (~(((1U << USB_CR_EP4_SIZE_LEN) - 1) << USB_CR_EP4_SIZE_POS))
#define USB_CR_EP4_DIR        USB_CR_EP4_DIR
#define USB_CR_EP4_DIR_POS    (11U)
#define USB_CR_EP4_DIR_LEN    (2U)
#define USB_CR_EP4_DIR_MSK    (((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS)
#define USB_CR_EP4_DIR_UMSK   (~(((1U << USB_CR_EP4_DIR_LEN) - 1) << USB_CR_EP4_DIR_POS))
#define USB_CR_EP4_TYPE       USB_CR_EP4_TYPE
#define USB_CR_EP4_TYPE_POS   (13U)
#define USB_CR_EP4_TYPE_LEN   (3U)
#define USB_CR_EP4_TYPE_MSK   (((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS)
#define USB_CR_EP4_TYPE_UMSK  (~(((1U << USB_CR_EP4_TYPE_LEN) - 1) << USB_CR_EP4_TYPE_POS))
#define USB_CR_EP4_STALL      USB_CR_EP4_STALL
#define USB_CR_EP4_STALL_POS  (16U)
#define USB_CR_EP4_STALL_LEN  (1U)
#define USB_CR_EP4_STALL_MSK  (((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS)
#define USB_CR_EP4_STALL_UMSK (~(((1U << USB_CR_EP4_STALL_LEN) - 1) << USB_CR_EP4_STALL_POS))
#define USB_CR_EP4_NACK       USB_CR_EP4_NACK
#define USB_CR_EP4_NACK_POS   (17U)
#define USB_CR_EP4_NACK_LEN   (1U)
#define USB_CR_EP4_NACK_MSK   (((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS)
#define USB_CR_EP4_NACK_UMSK  (~(((1U << USB_CR_EP4_NACK_LEN) - 1) << USB_CR_EP4_NACK_POS))
#define USB_CR_EP4_RDY        USB_CR_EP4_RDY
#define USB_CR_EP4_RDY_POS    (18U)
#define USB_CR_EP4_RDY_LEN    (1U)
#define USB_CR_EP4_RDY_MSK    (((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS)
#define USB_CR_EP4_RDY_UMSK   (~(((1U << USB_CR_EP4_RDY_LEN) - 1) << USB_CR_EP4_RDY_POS))
#define USB_STS_EP4_RDY       USB_STS_EP4_RDY
#define USB_STS_EP4_RDY_POS   (19U)
#define USB_STS_EP4_RDY_LEN   (1U)
#define USB_STS_EP4_RDY_MSK   (((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS)
#define USB_STS_EP4_RDY_UMSK  (~(((1U << USB_STS_EP4_RDY_LEN) - 1) << USB_STS_EP4_RDY_POS))

/* 0x50 : ep5_config */
#define USB_EP5_CONFIG_OFFSET (0x50)
#define USB_CR_EP5_SIZE       USB_CR_EP5_SIZE
#define USB_CR_EP5_SIZE_POS   (0U)
#define USB_CR_EP5_SIZE_LEN   (11U)
#define USB_CR_EP5_SIZE_MSK   (((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS)
#define USB_CR_EP5_SIZE_UMSK  (~(((1U << USB_CR_EP5_SIZE_LEN) - 1) << USB_CR_EP5_SIZE_POS))
#define USB_CR_EP5_DIR        USB_CR_EP5_DIR
#define USB_CR_EP5_DIR_POS    (11U)
#define USB_CR_EP5_DIR_LEN    (2U)
#define USB_CR_EP5_DIR_MSK    (((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS)
#define USB_CR_EP5_DIR_UMSK   (~(((1U << USB_CR_EP5_DIR_LEN) - 1) << USB_CR_EP5_DIR_POS))
#define USB_CR_EP5_TYPE       USB_CR_EP5_TYPE
#define USB_CR_EP5_TYPE_POS   (13U)
#define USB_CR_EP5_TYPE_LEN   (3U)
#define USB_CR_EP5_TYPE_MSK   (((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS)
#define USB_CR_EP5_TYPE_UMSK  (~(((1U << USB_CR_EP5_TYPE_LEN) - 1) << USB_CR_EP5_TYPE_POS))
#define USB_CR_EP5_STALL      USB_CR_EP5_STALL
#define USB_CR_EP5_STALL_POS  (16U)
#define USB_CR_EP5_STALL_LEN  (1U)
#define USB_CR_EP5_STALL_MSK  (((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS)
#define USB_CR_EP5_STALL_UMSK (~(((1U << USB_CR_EP5_STALL_LEN) - 1) << USB_CR_EP5_STALL_POS))
#define USB_CR_EP5_NACK       USB_CR_EP5_NACK
#define USB_CR_EP5_NACK_POS   (17U)
#define USB_CR_EP5_NACK_LEN   (1U)
#define USB_CR_EP5_NACK_MSK   (((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS)
#define USB_CR_EP5_NACK_UMSK  (~(((1U << USB_CR_EP5_NACK_LEN) - 1) << USB_CR_EP5_NACK_POS))
#define USB_CR_EP5_RDY        USB_CR_EP5_RDY
#define USB_CR_EP5_RDY_POS    (18U)
#define USB_CR_EP5_RDY_LEN    (1U)
#define USB_CR_EP5_RDY_MSK    (((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS)
#define USB_CR_EP5_RDY_UMSK   (~(((1U << USB_CR_EP5_RDY_LEN) - 1) << USB_CR_EP5_RDY_POS))
#define USB_STS_EP5_RDY       USB_STS_EP5_RDY
#define USB_STS_EP5_RDY_POS   (19U)
#define USB_STS_EP5_RDY_LEN   (1U)
#define USB_STS_EP5_RDY_MSK   (((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS)
#define USB_STS_EP5_RDY_UMSK  (~(((1U << USB_STS_EP5_RDY_LEN) - 1) << USB_STS_EP5_RDY_POS))

/* 0x54 : ep6_config */
#define USB_EP6_CONFIG_OFFSET (0x54)
#define USB_CR_EP6_SIZE       USB_CR_EP6_SIZE
#define USB_CR_EP6_SIZE_POS   (0U)
#define USB_CR_EP6_SIZE_LEN   (11U)
#define USB_CR_EP6_SIZE_MSK   (((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS)
#define USB_CR_EP6_SIZE_UMSK  (~(((1U << USB_CR_EP6_SIZE_LEN) - 1) << USB_CR_EP6_SIZE_POS))
#define USB_CR_EP6_DIR        USB_CR_EP6_DIR
#define USB_CR_EP6_DIR_POS    (11U)
#define USB_CR_EP6_DIR_LEN    (2U)
#define USB_CR_EP6_DIR_MSK    (((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS)
#define USB_CR_EP6_DIR_UMSK   (~(((1U << USB_CR_EP6_DIR_LEN) - 1) << USB_CR_EP6_DIR_POS))
#define USB_CR_EP6_TYPE       USB_CR_EP6_TYPE
#define USB_CR_EP6_TYPE_POS   (13U)
#define USB_CR_EP6_TYPE_LEN   (3U)
#define USB_CR_EP6_TYPE_MSK   (((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS)
#define USB_CR_EP6_TYPE_UMSK  (~(((1U << USB_CR_EP6_TYPE_LEN) - 1) << USB_CR_EP6_TYPE_POS))
#define USB_CR_EP6_STALL      USB_CR_EP6_STALL
#define USB_CR_EP6_STALL_POS  (16U)
#define USB_CR_EP6_STALL_LEN  (1U)
#define USB_CR_EP6_STALL_MSK  (((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS)
#define USB_CR_EP6_STALL_UMSK (~(((1U << USB_CR_EP6_STALL_LEN) - 1) << USB_CR_EP6_STALL_POS))
#define USB_CR_EP6_NACK       USB_CR_EP6_NACK
#define USB_CR_EP6_NACK_POS   (17U)
#define USB_CR_EP6_NACK_LEN   (1U)
#define USB_CR_EP6_NACK_MSK   (((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS)
#define USB_CR_EP6_NACK_UMSK  (~(((1U << USB_CR_EP6_NACK_LEN) - 1) << USB_CR_EP6_NACK_POS))
#define USB_CR_EP6_RDY        USB_CR_EP6_RDY
#define USB_CR_EP6_RDY_POS    (18U)
#define USB_CR_EP6_RDY_LEN    (1U)
#define USB_CR_EP6_RDY_MSK    (((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS)
#define USB_CR_EP6_RDY_UMSK   (~(((1U << USB_CR_EP6_RDY_LEN) - 1) << USB_CR_EP6_RDY_POS))
#define USB_STS_EP6_RDY       USB_STS_EP6_RDY
#define USB_STS_EP6_RDY_POS   (19U)
#define USB_STS_EP6_RDY_LEN   (1U)
#define USB_STS_EP6_RDY_MSK   (((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS)
#define USB_STS_EP6_RDY_UMSK  (~(((1U << USB_STS_EP6_RDY_LEN) - 1) << USB_STS_EP6_RDY_POS))

/* 0x58 : ep7_config */
#define USB_EP7_CONFIG_OFFSET (0x58)
#define USB_CR_EP7_SIZE       USB_CR_EP7_SIZE
#define USB_CR_EP7_SIZE_POS   (0U)
#define USB_CR_EP7_SIZE_LEN   (11U)
#define USB_CR_EP7_SIZE_MSK   (((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS)
#define USB_CR_EP7_SIZE_UMSK  (~(((1U << USB_CR_EP7_SIZE_LEN) - 1) << USB_CR_EP7_SIZE_POS))
#define USB_CR_EP7_DIR        USB_CR_EP7_DIR
#define USB_CR_EP7_DIR_POS    (11U)
#define USB_CR_EP7_DIR_LEN    (2U)
#define USB_CR_EP7_DIR_MSK    (((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS)
#define USB_CR_EP7_DIR_UMSK   (~(((1U << USB_CR_EP7_DIR_LEN) - 1) << USB_CR_EP7_DIR_POS))
#define USB_CR_EP7_TYPE       USB_CR_EP7_TYPE
#define USB_CR_EP7_TYPE_POS   (13U)
#define USB_CR_EP7_TYPE_LEN   (3U)
#define USB_CR_EP7_TYPE_MSK   (((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS)
#define USB_CR_EP7_TYPE_UMSK  (~(((1U << USB_CR_EP7_TYPE_LEN) - 1) << USB_CR_EP7_TYPE_POS))
#define USB_CR_EP7_STALL      USB_CR_EP7_STALL
#define USB_CR_EP7_STALL_POS  (16U)
#define USB_CR_EP7_STALL_LEN  (1U)
#define USB_CR_EP7_STALL_MSK  (((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS)
#define USB_CR_EP7_STALL_UMSK (~(((1U << USB_CR_EP7_STALL_LEN) - 1) << USB_CR_EP7_STALL_POS))
#define USB_CR_EP7_NACK       USB_CR_EP7_NACK
#define USB_CR_EP7_NACK_POS   (17U)
#define USB_CR_EP7_NACK_LEN   (1U)
#define USB_CR_EP7_NACK_MSK   (((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS)
#define USB_CR_EP7_NACK_UMSK  (~(((1U << USB_CR_EP7_NACK_LEN) - 1) << USB_CR_EP7_NACK_POS))
#define USB_CR_EP7_RDY        USB_CR_EP7_RDY
#define USB_CR_EP7_RDY_POS    (18U)
#define USB_CR_EP7_RDY_LEN    (1U)
#define USB_CR_EP7_RDY_MSK    (((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS)
#define USB_CR_EP7_RDY_UMSK   (~(((1U << USB_CR_EP7_RDY_LEN) - 1) << USB_CR_EP7_RDY_POS))
#define USB_STS_EP7_RDY       USB_STS_EP7_RDY
#define USB_STS_EP7_RDY_POS   (19U)
#define USB_STS_EP7_RDY_LEN   (1U)
#define USB_STS_EP7_RDY_MSK   (((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS)
#define USB_STS_EP7_RDY_UMSK  (~(((1U << USB_STS_EP7_RDY_LEN) - 1) << USB_STS_EP7_RDY_POS))

/* 0x100 : ep0_fifo_config */
#define USB_EP0_FIFO_CONFIG_OFFSET     (0x100)
#define USB_EP0_DMA_TX_EN              USB_EP0_DMA_TX_EN
#define USB_EP0_DMA_TX_EN_POS          (0U)
#define USB_EP0_DMA_TX_EN_LEN          (1U)
#define USB_EP0_DMA_TX_EN_MSK          (((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS)
#define USB_EP0_DMA_TX_EN_UMSK         (~(((1U << USB_EP0_DMA_TX_EN_LEN) - 1) << USB_EP0_DMA_TX_EN_POS))
#define USB_EP0_DMA_RX_EN              USB_EP0_DMA_RX_EN
#define USB_EP0_DMA_RX_EN_POS          (1U)
#define USB_EP0_DMA_RX_EN_LEN          (1U)
#define USB_EP0_DMA_RX_EN_MSK          (((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS)
#define USB_EP0_DMA_RX_EN_UMSK         (~(((1U << USB_EP0_DMA_RX_EN_LEN) - 1) << USB_EP0_DMA_RX_EN_POS))
#define USB_EP0_TX_FIFO_CLR            USB_EP0_TX_FIFO_CLR
#define USB_EP0_TX_FIFO_CLR_POS        (2U)
#define USB_EP0_TX_FIFO_CLR_LEN        (1U)
#define USB_EP0_TX_FIFO_CLR_MSK        (((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS)
#define USB_EP0_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP0_TX_FIFO_CLR_LEN) - 1) << USB_EP0_TX_FIFO_CLR_POS))
#define USB_EP0_RX_FIFO_CLR            USB_EP0_RX_FIFO_CLR
#define USB_EP0_RX_FIFO_CLR_POS        (3U)
#define USB_EP0_RX_FIFO_CLR_LEN        (1U)
#define USB_EP0_RX_FIFO_CLR_MSK        (((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS)
#define USB_EP0_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP0_RX_FIFO_CLR_LEN) - 1) << USB_EP0_RX_FIFO_CLR_POS))
#define USB_EP0_TX_FIFO_OVERFLOW       USB_EP0_TX_FIFO_OVERFLOW
#define USB_EP0_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP0_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP0_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS)
#define USB_EP0_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP0_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_OVERFLOW_POS))
#define USB_EP0_TX_FIFO_UNDERFLOW      USB_EP0_TX_FIFO_UNDERFLOW
#define USB_EP0_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP0_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP0_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS)
#define USB_EP0_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_TX_FIFO_UNDERFLOW_POS))
#define USB_EP0_RX_FIFO_OVERFLOW       USB_EP0_RX_FIFO_OVERFLOW
#define USB_EP0_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP0_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP0_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS)
#define USB_EP0_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP0_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_OVERFLOW_POS))
#define USB_EP0_RX_FIFO_UNDERFLOW      USB_EP0_RX_FIFO_UNDERFLOW
#define USB_EP0_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP0_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP0_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS)
#define USB_EP0_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP0_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP0_RX_FIFO_UNDERFLOW_POS))

/* 0x104 : ep0_fifo_status */
#define USB_EP0_FIFO_STATUS_OFFSET (0x104)
#define USB_EP0_TX_FIFO_CNT        USB_EP0_TX_FIFO_CNT
#define USB_EP0_TX_FIFO_CNT_POS    (0U)
#define USB_EP0_TX_FIFO_CNT_LEN    (7U)
#define USB_EP0_TX_FIFO_CNT_MSK    (((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS)
#define USB_EP0_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP0_TX_FIFO_CNT_LEN) - 1) << USB_EP0_TX_FIFO_CNT_POS))
#define USB_EP0_TX_FIFO_EMPTY      USB_EP0_TX_FIFO_EMPTY
#define USB_EP0_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP0_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP0_TX_FIFO_EMPTY_MSK  (((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS)
#define USB_EP0_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_TX_FIFO_EMPTY_LEN) - 1) << USB_EP0_TX_FIFO_EMPTY_POS))
#define USB_EP0_TX_FIFO_FULL       USB_EP0_TX_FIFO_FULL
#define USB_EP0_TX_FIFO_FULL_POS   (15U)
#define USB_EP0_TX_FIFO_FULL_LEN   (1U)
#define USB_EP0_TX_FIFO_FULL_MSK   (((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS)
#define USB_EP0_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP0_TX_FIFO_FULL_LEN) - 1) << USB_EP0_TX_FIFO_FULL_POS))
#define USB_EP0_RX_FIFO_CNT        USB_EP0_RX_FIFO_CNT
#define USB_EP0_RX_FIFO_CNT_POS    (16U)
#define USB_EP0_RX_FIFO_CNT_LEN    (7U)
#define USB_EP0_RX_FIFO_CNT_MSK    (((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS)
#define USB_EP0_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP0_RX_FIFO_CNT_LEN) - 1) << USB_EP0_RX_FIFO_CNT_POS))
#define USB_EP0_RX_FIFO_EMPTY      USB_EP0_RX_FIFO_EMPTY
#define USB_EP0_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP0_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP0_RX_FIFO_EMPTY_MSK  (((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS)
#define USB_EP0_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP0_RX_FIFO_EMPTY_LEN) - 1) << USB_EP0_RX_FIFO_EMPTY_POS))
#define USB_EP0_RX_FIFO_FULL       USB_EP0_RX_FIFO_FULL
#define USB_EP0_RX_FIFO_FULL_POS   (31U)
#define USB_EP0_RX_FIFO_FULL_LEN   (1U)
#define USB_EP0_RX_FIFO_FULL_MSK   (((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS)
#define USB_EP0_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP0_RX_FIFO_FULL_LEN) - 1) << USB_EP0_RX_FIFO_FULL_POS))

/* 0x108 : ep0_tx_fifo_wdata */
#define USB_EP0_TX_FIFO_WDATA_OFFSET (0x108)
#define USB_EP0_TX_FIFO_WDATA        USB_EP0_TX_FIFO_WDATA
#define USB_EP0_TX_FIFO_WDATA_POS    (0U)
#define USB_EP0_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP0_TX_FIFO_WDATA_MSK    (((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS)
#define USB_EP0_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP0_TX_FIFO_WDATA_LEN) - 1) << USB_EP0_TX_FIFO_WDATA_POS))

/* 0x10C : ep0_rx_fifo_rdata */
#define USB_EP0_RX_FIFO_RDATA_OFFSET (0x10C)
#define USB_EP0_RX_FIFO_RDATA        USB_EP0_RX_FIFO_RDATA
#define USB_EP0_RX_FIFO_RDATA_POS    (0U)
#define USB_EP0_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP0_RX_FIFO_RDATA_MSK    (((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS)
#define USB_EP0_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP0_RX_FIFO_RDATA_LEN) - 1) << USB_EP0_RX_FIFO_RDATA_POS))

/* 0x110 : ep1_fifo_config */
#define USB_EP1_FIFO_CONFIG_OFFSET     (0x110)
#define USB_EP1_DMA_TX_EN              USB_EP1_DMA_TX_EN
#define USB_EP1_DMA_TX_EN_POS          (0U)
#define USB_EP1_DMA_TX_EN_LEN          (1U)
#define USB_EP1_DMA_TX_EN_MSK          (((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS)
#define USB_EP1_DMA_TX_EN_UMSK         (~(((1U << USB_EP1_DMA_TX_EN_LEN) - 1) << USB_EP1_DMA_TX_EN_POS))
#define USB_EP1_DMA_RX_EN              USB_EP1_DMA_RX_EN
#define USB_EP1_DMA_RX_EN_POS          (1U)
#define USB_EP1_DMA_RX_EN_LEN          (1U)
#define USB_EP1_DMA_RX_EN_MSK          (((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS)
#define USB_EP1_DMA_RX_EN_UMSK         (~(((1U << USB_EP1_DMA_RX_EN_LEN) - 1) << USB_EP1_DMA_RX_EN_POS))
#define USB_EP1_TX_FIFO_CLR            USB_EP1_TX_FIFO_CLR
#define USB_EP1_TX_FIFO_CLR_POS        (2U)
#define USB_EP1_TX_FIFO_CLR_LEN        (1U)
#define USB_EP1_TX_FIFO_CLR_MSK        (((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS)
#define USB_EP1_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP1_TX_FIFO_CLR_LEN) - 1) << USB_EP1_TX_FIFO_CLR_POS))
#define USB_EP1_RX_FIFO_CLR            USB_EP1_RX_FIFO_CLR
#define USB_EP1_RX_FIFO_CLR_POS        (3U)
#define USB_EP1_RX_FIFO_CLR_LEN        (1U)
#define USB_EP1_RX_FIFO_CLR_MSK        (((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS)
#define USB_EP1_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP1_RX_FIFO_CLR_LEN) - 1) << USB_EP1_RX_FIFO_CLR_POS))
#define USB_EP1_TX_FIFO_OVERFLOW       USB_EP1_TX_FIFO_OVERFLOW
#define USB_EP1_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP1_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP1_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS)
#define USB_EP1_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP1_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_OVERFLOW_POS))
#define USB_EP1_TX_FIFO_UNDERFLOW      USB_EP1_TX_FIFO_UNDERFLOW
#define USB_EP1_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP1_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP1_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS)
#define USB_EP1_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_TX_FIFO_UNDERFLOW_POS))
#define USB_EP1_RX_FIFO_OVERFLOW       USB_EP1_RX_FIFO_OVERFLOW
#define USB_EP1_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP1_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP1_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS)
#define USB_EP1_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP1_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_OVERFLOW_POS))
#define USB_EP1_RX_FIFO_UNDERFLOW      USB_EP1_RX_FIFO_UNDERFLOW
#define USB_EP1_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP1_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP1_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS)
#define USB_EP1_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP1_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP1_RX_FIFO_UNDERFLOW_POS))

/* 0x114 : ep1_fifo_status */
#define USB_EP1_FIFO_STATUS_OFFSET (0x114)
#define USB_EP1_TX_FIFO_CNT        USB_EP1_TX_FIFO_CNT
#define USB_EP1_TX_FIFO_CNT_POS    (0U)
#define USB_EP1_TX_FIFO_CNT_LEN    (7U)
#define USB_EP1_TX_FIFO_CNT_MSK    (((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS)
#define USB_EP1_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP1_TX_FIFO_CNT_LEN) - 1) << USB_EP1_TX_FIFO_CNT_POS))
#define USB_EP1_TX_FIFO_EMPTY      USB_EP1_TX_FIFO_EMPTY
#define USB_EP1_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP1_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP1_TX_FIFO_EMPTY_MSK  (((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS)
#define USB_EP1_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_TX_FIFO_EMPTY_LEN) - 1) << USB_EP1_TX_FIFO_EMPTY_POS))
#define USB_EP1_TX_FIFO_FULL       USB_EP1_TX_FIFO_FULL
#define USB_EP1_TX_FIFO_FULL_POS   (15U)
#define USB_EP1_TX_FIFO_FULL_LEN   (1U)
#define USB_EP1_TX_FIFO_FULL_MSK   (((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS)
#define USB_EP1_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP1_TX_FIFO_FULL_LEN) - 1) << USB_EP1_TX_FIFO_FULL_POS))
#define USB_EP1_RX_FIFO_CNT        USB_EP1_RX_FIFO_CNT
#define USB_EP1_RX_FIFO_CNT_POS    (16U)
#define USB_EP1_RX_FIFO_CNT_LEN    (7U)
#define USB_EP1_RX_FIFO_CNT_MSK    (((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS)
#define USB_EP1_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP1_RX_FIFO_CNT_LEN) - 1) << USB_EP1_RX_FIFO_CNT_POS))
#define USB_EP1_RX_FIFO_EMPTY      USB_EP1_RX_FIFO_EMPTY
#define USB_EP1_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP1_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP1_RX_FIFO_EMPTY_MSK  (((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS)
#define USB_EP1_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP1_RX_FIFO_EMPTY_LEN) - 1) << USB_EP1_RX_FIFO_EMPTY_POS))
#define USB_EP1_RX_FIFO_FULL       USB_EP1_RX_FIFO_FULL
#define USB_EP1_RX_FIFO_FULL_POS   (31U)
#define USB_EP1_RX_FIFO_FULL_LEN   (1U)
#define USB_EP1_RX_FIFO_FULL_MSK   (((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS)
#define USB_EP1_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP1_RX_FIFO_FULL_LEN) - 1) << USB_EP1_RX_FIFO_FULL_POS))

/* 0x118 : ep1_tx_fifo_wdata */
#define USB_EP1_TX_FIFO_WDATA_OFFSET (0x118)
#define USB_EP1_TX_FIFO_WDATA        USB_EP1_TX_FIFO_WDATA
#define USB_EP1_TX_FIFO_WDATA_POS    (0U)
#define USB_EP1_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP1_TX_FIFO_WDATA_MSK    (((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS)
#define USB_EP1_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP1_TX_FIFO_WDATA_LEN) - 1) << USB_EP1_TX_FIFO_WDATA_POS))

/* 0x11C : ep1_rx_fifo_rdata */
#define USB_EP1_RX_FIFO_RDATA_OFFSET (0x11C)
#define USB_EP1_RX_FIFO_RDATA        USB_EP1_RX_FIFO_RDATA
#define USB_EP1_RX_FIFO_RDATA_POS    (0U)
#define USB_EP1_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP1_RX_FIFO_RDATA_MSK    (((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS)
#define USB_EP1_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP1_RX_FIFO_RDATA_LEN) - 1) << USB_EP1_RX_FIFO_RDATA_POS))

/* 0x120 : ep2_fifo_config */
#define USB_EP2_FIFO_CONFIG_OFFSET     (0x120)
#define USB_EP2_DMA_TX_EN              USB_EP2_DMA_TX_EN
#define USB_EP2_DMA_TX_EN_POS          (0U)
#define USB_EP2_DMA_TX_EN_LEN          (1U)
#define USB_EP2_DMA_TX_EN_MSK          (((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS)
#define USB_EP2_DMA_TX_EN_UMSK         (~(((1U << USB_EP2_DMA_TX_EN_LEN) - 1) << USB_EP2_DMA_TX_EN_POS))
#define USB_EP2_DMA_RX_EN              USB_EP2_DMA_RX_EN
#define USB_EP2_DMA_RX_EN_POS          (1U)
#define USB_EP2_DMA_RX_EN_LEN          (1U)
#define USB_EP2_DMA_RX_EN_MSK          (((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS)
#define USB_EP2_DMA_RX_EN_UMSK         (~(((1U << USB_EP2_DMA_RX_EN_LEN) - 1) << USB_EP2_DMA_RX_EN_POS))
#define USB_EP2_TX_FIFO_CLR            USB_EP2_TX_FIFO_CLR
#define USB_EP2_TX_FIFO_CLR_POS        (2U)
#define USB_EP2_TX_FIFO_CLR_LEN        (1U)
#define USB_EP2_TX_FIFO_CLR_MSK        (((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS)
#define USB_EP2_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP2_TX_FIFO_CLR_LEN) - 1) << USB_EP2_TX_FIFO_CLR_POS))
#define USB_EP2_RX_FIFO_CLR            USB_EP2_RX_FIFO_CLR
#define USB_EP2_RX_FIFO_CLR_POS        (3U)
#define USB_EP2_RX_FIFO_CLR_LEN        (1U)
#define USB_EP2_RX_FIFO_CLR_MSK        (((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS)
#define USB_EP2_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP2_RX_FIFO_CLR_LEN) - 1) << USB_EP2_RX_FIFO_CLR_POS))
#define USB_EP2_TX_FIFO_OVERFLOW       USB_EP2_TX_FIFO_OVERFLOW
#define USB_EP2_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP2_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP2_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS)
#define USB_EP2_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP2_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_OVERFLOW_POS))
#define USB_EP2_TX_FIFO_UNDERFLOW      USB_EP2_TX_FIFO_UNDERFLOW
#define USB_EP2_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP2_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP2_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS)
#define USB_EP2_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_TX_FIFO_UNDERFLOW_POS))
#define USB_EP2_RX_FIFO_OVERFLOW       USB_EP2_RX_FIFO_OVERFLOW
#define USB_EP2_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP2_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP2_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS)
#define USB_EP2_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP2_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_OVERFLOW_POS))
#define USB_EP2_RX_FIFO_UNDERFLOW      USB_EP2_RX_FIFO_UNDERFLOW
#define USB_EP2_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP2_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP2_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS)
#define USB_EP2_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP2_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP2_RX_FIFO_UNDERFLOW_POS))

/* 0x124 : ep2_fifo_status */
#define USB_EP2_FIFO_STATUS_OFFSET (0x124)
#define USB_EP2_TX_FIFO_CNT        USB_EP2_TX_FIFO_CNT
#define USB_EP2_TX_FIFO_CNT_POS    (0U)
#define USB_EP2_TX_FIFO_CNT_LEN    (7U)
#define USB_EP2_TX_FIFO_CNT_MSK    (((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS)
#define USB_EP2_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP2_TX_FIFO_CNT_LEN) - 1) << USB_EP2_TX_FIFO_CNT_POS))
#define USB_EP2_TX_FIFO_EMPTY      USB_EP2_TX_FIFO_EMPTY
#define USB_EP2_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP2_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP2_TX_FIFO_EMPTY_MSK  (((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS)
#define USB_EP2_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_TX_FIFO_EMPTY_LEN) - 1) << USB_EP2_TX_FIFO_EMPTY_POS))
#define USB_EP2_TX_FIFO_FULL       USB_EP2_TX_FIFO_FULL
#define USB_EP2_TX_FIFO_FULL_POS   (15U)
#define USB_EP2_TX_FIFO_FULL_LEN   (1U)
#define USB_EP2_TX_FIFO_FULL_MSK   (((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS)
#define USB_EP2_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP2_TX_FIFO_FULL_LEN) - 1) << USB_EP2_TX_FIFO_FULL_POS))
#define USB_EP2_RX_FIFO_CNT        USB_EP2_RX_FIFO_CNT
#define USB_EP2_RX_FIFO_CNT_POS    (16U)
#define USB_EP2_RX_FIFO_CNT_LEN    (7U)
#define USB_EP2_RX_FIFO_CNT_MSK    (((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS)
#define USB_EP2_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP2_RX_FIFO_CNT_LEN) - 1) << USB_EP2_RX_FIFO_CNT_POS))
#define USB_EP2_RX_FIFO_EMPTY      USB_EP2_RX_FIFO_EMPTY
#define USB_EP2_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP2_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP2_RX_FIFO_EMPTY_MSK  (((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS)
#define USB_EP2_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP2_RX_FIFO_EMPTY_LEN) - 1) << USB_EP2_RX_FIFO_EMPTY_POS))
#define USB_EP2_RX_FIFO_FULL       USB_EP2_RX_FIFO_FULL
#define USB_EP2_RX_FIFO_FULL_POS   (31U)
#define USB_EP2_RX_FIFO_FULL_LEN   (1U)
#define USB_EP2_RX_FIFO_FULL_MSK   (((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS)
#define USB_EP2_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP2_RX_FIFO_FULL_LEN) - 1) << USB_EP2_RX_FIFO_FULL_POS))

/* 0x128 : ep2_tx_fifo_wdata */
#define USB_EP2_TX_FIFO_WDATA_OFFSET (0x128)
#define USB_EP2_TX_FIFO_WDATA        USB_EP2_TX_FIFO_WDATA
#define USB_EP2_TX_FIFO_WDATA_POS    (0U)
#define USB_EP2_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP2_TX_FIFO_WDATA_MSK    (((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS)
#define USB_EP2_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP2_TX_FIFO_WDATA_LEN) - 1) << USB_EP2_TX_FIFO_WDATA_POS))

/* 0x12C : ep2_rx_fifo_rdata */
#define USB_EP2_RX_FIFO_RDATA_OFFSET (0x12C)
#define USB_EP2_RX_FIFO_RDATA        USB_EP2_RX_FIFO_RDATA
#define USB_EP2_RX_FIFO_RDATA_POS    (0U)
#define USB_EP2_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP2_RX_FIFO_RDATA_MSK    (((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS)
#define USB_EP2_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP2_RX_FIFO_RDATA_LEN) - 1) << USB_EP2_RX_FIFO_RDATA_POS))

/* 0x130 : ep3_fifo_config */
#define USB_EP3_FIFO_CONFIG_OFFSET     (0x130)
#define USB_EP3_DMA_TX_EN              USB_EP3_DMA_TX_EN
#define USB_EP3_DMA_TX_EN_POS          (0U)
#define USB_EP3_DMA_TX_EN_LEN          (1U)
#define USB_EP3_DMA_TX_EN_MSK          (((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS)
#define USB_EP3_DMA_TX_EN_UMSK         (~(((1U << USB_EP3_DMA_TX_EN_LEN) - 1) << USB_EP3_DMA_TX_EN_POS))
#define USB_EP3_DMA_RX_EN              USB_EP3_DMA_RX_EN
#define USB_EP3_DMA_RX_EN_POS          (1U)
#define USB_EP3_DMA_RX_EN_LEN          (1U)
#define USB_EP3_DMA_RX_EN_MSK          (((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS)
#define USB_EP3_DMA_RX_EN_UMSK         (~(((1U << USB_EP3_DMA_RX_EN_LEN) - 1) << USB_EP3_DMA_RX_EN_POS))
#define USB_EP3_TX_FIFO_CLR            USB_EP3_TX_FIFO_CLR
#define USB_EP3_TX_FIFO_CLR_POS        (2U)
#define USB_EP3_TX_FIFO_CLR_LEN        (1U)
#define USB_EP3_TX_FIFO_CLR_MSK        (((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS)
#define USB_EP3_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP3_TX_FIFO_CLR_LEN) - 1) << USB_EP3_TX_FIFO_CLR_POS))
#define USB_EP3_RX_FIFO_CLR            USB_EP3_RX_FIFO_CLR
#define USB_EP3_RX_FIFO_CLR_POS        (3U)
#define USB_EP3_RX_FIFO_CLR_LEN        (1U)
#define USB_EP3_RX_FIFO_CLR_MSK        (((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS)
#define USB_EP3_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP3_RX_FIFO_CLR_LEN) - 1) << USB_EP3_RX_FIFO_CLR_POS))
#define USB_EP3_TX_FIFO_OVERFLOW       USB_EP3_TX_FIFO_OVERFLOW
#define USB_EP3_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP3_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP3_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS)
#define USB_EP3_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP3_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_OVERFLOW_POS))
#define USB_EP3_TX_FIFO_UNDERFLOW      USB_EP3_TX_FIFO_UNDERFLOW
#define USB_EP3_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP3_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP3_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS)
#define USB_EP3_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_TX_FIFO_UNDERFLOW_POS))
#define USB_EP3_RX_FIFO_OVERFLOW       USB_EP3_RX_FIFO_OVERFLOW
#define USB_EP3_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP3_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP3_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS)
#define USB_EP3_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP3_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_OVERFLOW_POS))
#define USB_EP3_RX_FIFO_UNDERFLOW      USB_EP3_RX_FIFO_UNDERFLOW
#define USB_EP3_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP3_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP3_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS)
#define USB_EP3_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP3_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP3_RX_FIFO_UNDERFLOW_POS))

/* 0x134 : ep3_fifo_status */
#define USB_EP3_FIFO_STATUS_OFFSET (0x134)
#define USB_EP3_TX_FIFO_CNT        USB_EP3_TX_FIFO_CNT
#define USB_EP3_TX_FIFO_CNT_POS    (0U)
#define USB_EP3_TX_FIFO_CNT_LEN    (7U)
#define USB_EP3_TX_FIFO_CNT_MSK    (((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS)
#define USB_EP3_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP3_TX_FIFO_CNT_LEN) - 1) << USB_EP3_TX_FIFO_CNT_POS))
#define USB_EP3_TX_FIFO_EMPTY      USB_EP3_TX_FIFO_EMPTY
#define USB_EP3_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP3_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP3_TX_FIFO_EMPTY_MSK  (((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS)
#define USB_EP3_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_TX_FIFO_EMPTY_LEN) - 1) << USB_EP3_TX_FIFO_EMPTY_POS))
#define USB_EP3_TX_FIFO_FULL       USB_EP3_TX_FIFO_FULL
#define USB_EP3_TX_FIFO_FULL_POS   (15U)
#define USB_EP3_TX_FIFO_FULL_LEN   (1U)
#define USB_EP3_TX_FIFO_FULL_MSK   (((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS)
#define USB_EP3_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP3_TX_FIFO_FULL_LEN) - 1) << USB_EP3_TX_FIFO_FULL_POS))
#define USB_EP3_RX_FIFO_CNT        USB_EP3_RX_FIFO_CNT
#define USB_EP3_RX_FIFO_CNT_POS    (16U)
#define USB_EP3_RX_FIFO_CNT_LEN    (7U)
#define USB_EP3_RX_FIFO_CNT_MSK    (((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS)
#define USB_EP3_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP3_RX_FIFO_CNT_LEN) - 1) << USB_EP3_RX_FIFO_CNT_POS))
#define USB_EP3_RX_FIFO_EMPTY      USB_EP3_RX_FIFO_EMPTY
#define USB_EP3_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP3_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP3_RX_FIFO_EMPTY_MSK  (((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS)
#define USB_EP3_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP3_RX_FIFO_EMPTY_LEN) - 1) << USB_EP3_RX_FIFO_EMPTY_POS))
#define USB_EP3_RX_FIFO_FULL       USB_EP3_RX_FIFO_FULL
#define USB_EP3_RX_FIFO_FULL_POS   (31U)
#define USB_EP3_RX_FIFO_FULL_LEN   (1U)
#define USB_EP3_RX_FIFO_FULL_MSK   (((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS)
#define USB_EP3_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP3_RX_FIFO_FULL_LEN) - 1) << USB_EP3_RX_FIFO_FULL_POS))

/* 0x138 : ep3_tx_fifo_wdata */
#define USB_EP3_TX_FIFO_WDATA_OFFSET (0x138)
#define USB_EP3_TX_FIFO_WDATA        USB_EP3_TX_FIFO_WDATA
#define USB_EP3_TX_FIFO_WDATA_POS    (0U)
#define USB_EP3_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP3_TX_FIFO_WDATA_MSK    (((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS)
#define USB_EP3_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP3_TX_FIFO_WDATA_LEN) - 1) << USB_EP3_TX_FIFO_WDATA_POS))

/* 0x13C : ep3_rx_fifo_rdata */
#define USB_EP3_RX_FIFO_RDATA_OFFSET (0x13C)
#define USB_EP3_RX_FIFO_RDATA        USB_EP3_RX_FIFO_RDATA
#define USB_EP3_RX_FIFO_RDATA_POS    (0U)
#define USB_EP3_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP3_RX_FIFO_RDATA_MSK    (((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS)
#define USB_EP3_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP3_RX_FIFO_RDATA_LEN) - 1) << USB_EP3_RX_FIFO_RDATA_POS))

/* 0x140 : ep4_fifo_config */
#define USB_EP4_FIFO_CONFIG_OFFSET     (0x140)
#define USB_EP4_DMA_TX_EN              USB_EP4_DMA_TX_EN
#define USB_EP4_DMA_TX_EN_POS          (0U)
#define USB_EP4_DMA_TX_EN_LEN          (1U)
#define USB_EP4_DMA_TX_EN_MSK          (((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS)
#define USB_EP4_DMA_TX_EN_UMSK         (~(((1U << USB_EP4_DMA_TX_EN_LEN) - 1) << USB_EP4_DMA_TX_EN_POS))
#define USB_EP4_DMA_RX_EN              USB_EP4_DMA_RX_EN
#define USB_EP4_DMA_RX_EN_POS          (1U)
#define USB_EP4_DMA_RX_EN_LEN          (1U)
#define USB_EP4_DMA_RX_EN_MSK          (((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS)
#define USB_EP4_DMA_RX_EN_UMSK         (~(((1U << USB_EP4_DMA_RX_EN_LEN) - 1) << USB_EP4_DMA_RX_EN_POS))
#define USB_EP4_TX_FIFO_CLR            USB_EP4_TX_FIFO_CLR
#define USB_EP4_TX_FIFO_CLR_POS        (2U)
#define USB_EP4_TX_FIFO_CLR_LEN        (1U)
#define USB_EP4_TX_FIFO_CLR_MSK        (((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS)
#define USB_EP4_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP4_TX_FIFO_CLR_LEN) - 1) << USB_EP4_TX_FIFO_CLR_POS))
#define USB_EP4_RX_FIFO_CLR            USB_EP4_RX_FIFO_CLR
#define USB_EP4_RX_FIFO_CLR_POS        (3U)
#define USB_EP4_RX_FIFO_CLR_LEN        (1U)
#define USB_EP4_RX_FIFO_CLR_MSK        (((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS)
#define USB_EP4_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP4_RX_FIFO_CLR_LEN) - 1) << USB_EP4_RX_FIFO_CLR_POS))
#define USB_EP4_TX_FIFO_OVERFLOW       USB_EP4_TX_FIFO_OVERFLOW
#define USB_EP4_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP4_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP4_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS)
#define USB_EP4_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP4_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_OVERFLOW_POS))
#define USB_EP4_TX_FIFO_UNDERFLOW      USB_EP4_TX_FIFO_UNDERFLOW
#define USB_EP4_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP4_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP4_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS)
#define USB_EP4_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_TX_FIFO_UNDERFLOW_POS))
#define USB_EP4_RX_FIFO_OVERFLOW       USB_EP4_RX_FIFO_OVERFLOW
#define USB_EP4_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP4_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP4_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS)
#define USB_EP4_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP4_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_OVERFLOW_POS))
#define USB_EP4_RX_FIFO_UNDERFLOW      USB_EP4_RX_FIFO_UNDERFLOW
#define USB_EP4_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP4_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP4_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS)
#define USB_EP4_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP4_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP4_RX_FIFO_UNDERFLOW_POS))

/* 0x144 : ep4_fifo_status */
#define USB_EP4_FIFO_STATUS_OFFSET (0x144)
#define USB_EP4_TX_FIFO_CNT        USB_EP4_TX_FIFO_CNT
#define USB_EP4_TX_FIFO_CNT_POS    (0U)
#define USB_EP4_TX_FIFO_CNT_LEN    (7U)
#define USB_EP4_TX_FIFO_CNT_MSK    (((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS)
#define USB_EP4_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP4_TX_FIFO_CNT_LEN) - 1) << USB_EP4_TX_FIFO_CNT_POS))
#define USB_EP4_TX_FIFO_EMPTY      USB_EP4_TX_FIFO_EMPTY
#define USB_EP4_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP4_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP4_TX_FIFO_EMPTY_MSK  (((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS)
#define USB_EP4_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_TX_FIFO_EMPTY_LEN) - 1) << USB_EP4_TX_FIFO_EMPTY_POS))
#define USB_EP4_TX_FIFO_FULL       USB_EP4_TX_FIFO_FULL
#define USB_EP4_TX_FIFO_FULL_POS   (15U)
#define USB_EP4_TX_FIFO_FULL_LEN   (1U)
#define USB_EP4_TX_FIFO_FULL_MSK   (((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS)
#define USB_EP4_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP4_TX_FIFO_FULL_LEN) - 1) << USB_EP4_TX_FIFO_FULL_POS))
#define USB_EP4_RX_FIFO_CNT        USB_EP4_RX_FIFO_CNT
#define USB_EP4_RX_FIFO_CNT_POS    (16U)
#define USB_EP4_RX_FIFO_CNT_LEN    (7U)
#define USB_EP4_RX_FIFO_CNT_MSK    (((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS)
#define USB_EP4_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP4_RX_FIFO_CNT_LEN) - 1) << USB_EP4_RX_FIFO_CNT_POS))
#define USB_EP4_RX_FIFO_EMPTY      USB_EP4_RX_FIFO_EMPTY
#define USB_EP4_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP4_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP4_RX_FIFO_EMPTY_MSK  (((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS)
#define USB_EP4_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP4_RX_FIFO_EMPTY_LEN) - 1) << USB_EP4_RX_FIFO_EMPTY_POS))
#define USB_EP4_RX_FIFO_FULL       USB_EP4_RX_FIFO_FULL
#define USB_EP4_RX_FIFO_FULL_POS   (31U)
#define USB_EP4_RX_FIFO_FULL_LEN   (1U)
#define USB_EP4_RX_FIFO_FULL_MSK   (((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS)
#define USB_EP4_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP4_RX_FIFO_FULL_LEN) - 1) << USB_EP4_RX_FIFO_FULL_POS))

/* 0x148 : ep4_tx_fifo_wdata */
#define USB_EP4_TX_FIFO_WDATA_OFFSET (0x148)
#define USB_EP4_TX_FIFO_WDATA        USB_EP4_TX_FIFO_WDATA
#define USB_EP4_TX_FIFO_WDATA_POS    (0U)
#define USB_EP4_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP4_TX_FIFO_WDATA_MSK    (((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS)
#define USB_EP4_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP4_TX_FIFO_WDATA_LEN) - 1) << USB_EP4_TX_FIFO_WDATA_POS))

/* 0x14C : ep4_rx_fifo_rdata */
#define USB_EP4_RX_FIFO_RDATA_OFFSET (0x14C)
#define USB_EP4_RX_FIFO_RDATA        USB_EP4_RX_FIFO_RDATA
#define USB_EP4_RX_FIFO_RDATA_POS    (0U)
#define USB_EP4_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP4_RX_FIFO_RDATA_MSK    (((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS)
#define USB_EP4_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP4_RX_FIFO_RDATA_LEN) - 1) << USB_EP4_RX_FIFO_RDATA_POS))

/* 0x150 : ep5_fifo_config */
#define USB_EP5_FIFO_CONFIG_OFFSET     (0x150)
#define USB_EP5_DMA_TX_EN              USB_EP5_DMA_TX_EN
#define USB_EP5_DMA_TX_EN_POS          (0U)
#define USB_EP5_DMA_TX_EN_LEN          (1U)
#define USB_EP5_DMA_TX_EN_MSK          (((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS)
#define USB_EP5_DMA_TX_EN_UMSK         (~(((1U << USB_EP5_DMA_TX_EN_LEN) - 1) << USB_EP5_DMA_TX_EN_POS))
#define USB_EP5_DMA_RX_EN              USB_EP5_DMA_RX_EN
#define USB_EP5_DMA_RX_EN_POS          (1U)
#define USB_EP5_DMA_RX_EN_LEN          (1U)
#define USB_EP5_DMA_RX_EN_MSK          (((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS)
#define USB_EP5_DMA_RX_EN_UMSK         (~(((1U << USB_EP5_DMA_RX_EN_LEN) - 1) << USB_EP5_DMA_RX_EN_POS))
#define USB_EP5_TX_FIFO_CLR            USB_EP5_TX_FIFO_CLR
#define USB_EP5_TX_FIFO_CLR_POS        (2U)
#define USB_EP5_TX_FIFO_CLR_LEN        (1U)
#define USB_EP5_TX_FIFO_CLR_MSK        (((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS)
#define USB_EP5_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP5_TX_FIFO_CLR_LEN) - 1) << USB_EP5_TX_FIFO_CLR_POS))
#define USB_EP5_RX_FIFO_CLR            USB_EP5_RX_FIFO_CLR
#define USB_EP5_RX_FIFO_CLR_POS        (3U)
#define USB_EP5_RX_FIFO_CLR_LEN        (1U)
#define USB_EP5_RX_FIFO_CLR_MSK        (((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS)
#define USB_EP5_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP5_RX_FIFO_CLR_LEN) - 1) << USB_EP5_RX_FIFO_CLR_POS))
#define USB_EP5_TX_FIFO_OVERFLOW       USB_EP5_TX_FIFO_OVERFLOW
#define USB_EP5_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP5_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP5_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS)
#define USB_EP5_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP5_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_OVERFLOW_POS))
#define USB_EP5_TX_FIFO_UNDERFLOW      USB_EP5_TX_FIFO_UNDERFLOW
#define USB_EP5_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP5_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP5_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS)
#define USB_EP5_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_TX_FIFO_UNDERFLOW_POS))
#define USB_EP5_RX_FIFO_OVERFLOW       USB_EP5_RX_FIFO_OVERFLOW
#define USB_EP5_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP5_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP5_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS)
#define USB_EP5_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP5_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_OVERFLOW_POS))
#define USB_EP5_RX_FIFO_UNDERFLOW      USB_EP5_RX_FIFO_UNDERFLOW
#define USB_EP5_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP5_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP5_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS)
#define USB_EP5_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP5_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP5_RX_FIFO_UNDERFLOW_POS))

/* 0x154 : ep5_fifo_status */
#define USB_EP5_FIFO_STATUS_OFFSET (0x154)
#define USB_EP5_TX_FIFO_CNT        USB_EP5_TX_FIFO_CNT
#define USB_EP5_TX_FIFO_CNT_POS    (0U)
#define USB_EP5_TX_FIFO_CNT_LEN    (7U)
#define USB_EP5_TX_FIFO_CNT_MSK    (((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS)
#define USB_EP5_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP5_TX_FIFO_CNT_LEN) - 1) << USB_EP5_TX_FIFO_CNT_POS))
#define USB_EP5_TX_FIFO_EMPTY      USB_EP5_TX_FIFO_EMPTY
#define USB_EP5_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP5_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP5_TX_FIFO_EMPTY_MSK  (((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS)
#define USB_EP5_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_TX_FIFO_EMPTY_LEN) - 1) << USB_EP5_TX_FIFO_EMPTY_POS))
#define USB_EP5_TX_FIFO_FULL       USB_EP5_TX_FIFO_FULL
#define USB_EP5_TX_FIFO_FULL_POS   (15U)
#define USB_EP5_TX_FIFO_FULL_LEN   (1U)
#define USB_EP5_TX_FIFO_FULL_MSK   (((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS)
#define USB_EP5_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP5_TX_FIFO_FULL_LEN) - 1) << USB_EP5_TX_FIFO_FULL_POS))
#define USB_EP5_RX_FIFO_CNT        USB_EP5_RX_FIFO_CNT
#define USB_EP5_RX_FIFO_CNT_POS    (16U)
#define USB_EP5_RX_FIFO_CNT_LEN    (7U)
#define USB_EP5_RX_FIFO_CNT_MSK    (((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS)
#define USB_EP5_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP5_RX_FIFO_CNT_LEN) - 1) << USB_EP5_RX_FIFO_CNT_POS))
#define USB_EP5_RX_FIFO_EMPTY      USB_EP5_RX_FIFO_EMPTY
#define USB_EP5_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP5_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP5_RX_FIFO_EMPTY_MSK  (((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS)
#define USB_EP5_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP5_RX_FIFO_EMPTY_LEN) - 1) << USB_EP5_RX_FIFO_EMPTY_POS))
#define USB_EP5_RX_FIFO_FULL       USB_EP5_RX_FIFO_FULL
#define USB_EP5_RX_FIFO_FULL_POS   (31U)
#define USB_EP5_RX_FIFO_FULL_LEN   (1U)
#define USB_EP5_RX_FIFO_FULL_MSK   (((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS)
#define USB_EP5_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP5_RX_FIFO_FULL_LEN) - 1) << USB_EP5_RX_FIFO_FULL_POS))

/* 0x158 : ep5_tx_fifo_wdata */
#define USB_EP5_TX_FIFO_WDATA_OFFSET (0x158)
#define USB_EP5_TX_FIFO_WDATA        USB_EP5_TX_FIFO_WDATA
#define USB_EP5_TX_FIFO_WDATA_POS    (0U)
#define USB_EP5_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP5_TX_FIFO_WDATA_MSK    (((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS)
#define USB_EP5_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP5_TX_FIFO_WDATA_LEN) - 1) << USB_EP5_TX_FIFO_WDATA_POS))

/* 0x15C : ep5_rx_fifo_rdata */
#define USB_EP5_RX_FIFO_RDATA_OFFSET (0x15C)
#define USB_EP5_RX_FIFO_RDATA        USB_EP5_RX_FIFO_RDATA
#define USB_EP5_RX_FIFO_RDATA_POS    (0U)
#define USB_EP5_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP5_RX_FIFO_RDATA_MSK    (((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS)
#define USB_EP5_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP5_RX_FIFO_RDATA_LEN) - 1) << USB_EP5_RX_FIFO_RDATA_POS))

/* 0x160 : ep6_fifo_config */
#define USB_EP6_FIFO_CONFIG_OFFSET     (0x160)
#define USB_EP6_DMA_TX_EN              USB_EP6_DMA_TX_EN
#define USB_EP6_DMA_TX_EN_POS          (0U)
#define USB_EP6_DMA_TX_EN_LEN          (1U)
#define USB_EP6_DMA_TX_EN_MSK          (((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS)
#define USB_EP6_DMA_TX_EN_UMSK         (~(((1U << USB_EP6_DMA_TX_EN_LEN) - 1) << USB_EP6_DMA_TX_EN_POS))
#define USB_EP6_DMA_RX_EN              USB_EP6_DMA_RX_EN
#define USB_EP6_DMA_RX_EN_POS          (1U)
#define USB_EP6_DMA_RX_EN_LEN          (1U)
#define USB_EP6_DMA_RX_EN_MSK          (((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS)
#define USB_EP6_DMA_RX_EN_UMSK         (~(((1U << USB_EP6_DMA_RX_EN_LEN) - 1) << USB_EP6_DMA_RX_EN_POS))
#define USB_EP6_TX_FIFO_CLR            USB_EP6_TX_FIFO_CLR
#define USB_EP6_TX_FIFO_CLR_POS        (2U)
#define USB_EP6_TX_FIFO_CLR_LEN        (1U)
#define USB_EP6_TX_FIFO_CLR_MSK        (((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS)
#define USB_EP6_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP6_TX_FIFO_CLR_LEN) - 1) << USB_EP6_TX_FIFO_CLR_POS))
#define USB_EP6_RX_FIFO_CLR            USB_EP6_RX_FIFO_CLR
#define USB_EP6_RX_FIFO_CLR_POS        (3U)
#define USB_EP6_RX_FIFO_CLR_LEN        (1U)
#define USB_EP6_RX_FIFO_CLR_MSK        (((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS)
#define USB_EP6_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP6_RX_FIFO_CLR_LEN) - 1) << USB_EP6_RX_FIFO_CLR_POS))
#define USB_EP6_TX_FIFO_OVERFLOW       USB_EP6_TX_FIFO_OVERFLOW
#define USB_EP6_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP6_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP6_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS)
#define USB_EP6_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP6_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_OVERFLOW_POS))
#define USB_EP6_TX_FIFO_UNDERFLOW      USB_EP6_TX_FIFO_UNDERFLOW
#define USB_EP6_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP6_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP6_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS)
#define USB_EP6_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_TX_FIFO_UNDERFLOW_POS))
#define USB_EP6_RX_FIFO_OVERFLOW       USB_EP6_RX_FIFO_OVERFLOW
#define USB_EP6_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP6_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP6_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS)
#define USB_EP6_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP6_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_OVERFLOW_POS))
#define USB_EP6_RX_FIFO_UNDERFLOW      USB_EP6_RX_FIFO_UNDERFLOW
#define USB_EP6_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP6_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP6_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS)
#define USB_EP6_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP6_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP6_RX_FIFO_UNDERFLOW_POS))

/* 0x164 : ep6_fifo_status */
#define USB_EP6_FIFO_STATUS_OFFSET (0x164)
#define USB_EP6_TX_FIFO_CNT        USB_EP6_TX_FIFO_CNT
#define USB_EP6_TX_FIFO_CNT_POS    (0U)
#define USB_EP6_TX_FIFO_CNT_LEN    (7U)
#define USB_EP6_TX_FIFO_CNT_MSK    (((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS)
#define USB_EP6_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP6_TX_FIFO_CNT_LEN) - 1) << USB_EP6_TX_FIFO_CNT_POS))
#define USB_EP6_TX_FIFO_EMPTY      USB_EP6_TX_FIFO_EMPTY
#define USB_EP6_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP6_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP6_TX_FIFO_EMPTY_MSK  (((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS)
#define USB_EP6_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_TX_FIFO_EMPTY_LEN) - 1) << USB_EP6_TX_FIFO_EMPTY_POS))
#define USB_EP6_TX_FIFO_FULL       USB_EP6_TX_FIFO_FULL
#define USB_EP6_TX_FIFO_FULL_POS   (15U)
#define USB_EP6_TX_FIFO_FULL_LEN   (1U)
#define USB_EP6_TX_FIFO_FULL_MSK   (((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS)
#define USB_EP6_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP6_TX_FIFO_FULL_LEN) - 1) << USB_EP6_TX_FIFO_FULL_POS))
#define USB_EP6_RX_FIFO_CNT        USB_EP6_RX_FIFO_CNT
#define USB_EP6_RX_FIFO_CNT_POS    (16U)
#define USB_EP6_RX_FIFO_CNT_LEN    (7U)
#define USB_EP6_RX_FIFO_CNT_MSK    (((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS)
#define USB_EP6_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP6_RX_FIFO_CNT_LEN) - 1) << USB_EP6_RX_FIFO_CNT_POS))
#define USB_EP6_RX_FIFO_EMPTY      USB_EP6_RX_FIFO_EMPTY
#define USB_EP6_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP6_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP6_RX_FIFO_EMPTY_MSK  (((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS)
#define USB_EP6_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP6_RX_FIFO_EMPTY_LEN) - 1) << USB_EP6_RX_FIFO_EMPTY_POS))
#define USB_EP6_RX_FIFO_FULL       USB_EP6_RX_FIFO_FULL
#define USB_EP6_RX_FIFO_FULL_POS   (31U)
#define USB_EP6_RX_FIFO_FULL_LEN   (1U)
#define USB_EP6_RX_FIFO_FULL_MSK   (((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS)
#define USB_EP6_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP6_RX_FIFO_FULL_LEN) - 1) << USB_EP6_RX_FIFO_FULL_POS))

/* 0x168 : ep6_tx_fifo_wdata */
#define USB_EP6_TX_FIFO_WDATA_OFFSET (0x168)
#define USB_EP6_TX_FIFO_WDATA        USB_EP6_TX_FIFO_WDATA
#define USB_EP6_TX_FIFO_WDATA_POS    (0U)
#define USB_EP6_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP6_TX_FIFO_WDATA_MSK    (((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS)
#define USB_EP6_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP6_TX_FIFO_WDATA_LEN) - 1) << USB_EP6_TX_FIFO_WDATA_POS))

/* 0x16C : ep6_rx_fifo_rdata */
#define USB_EP6_RX_FIFO_RDATA_OFFSET (0x16C)
#define USB_EP6_RX_FIFO_RDATA        USB_EP6_RX_FIFO_RDATA
#define USB_EP6_RX_FIFO_RDATA_POS    (0U)
#define USB_EP6_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP6_RX_FIFO_RDATA_MSK    (((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS)
#define USB_EP6_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP6_RX_FIFO_RDATA_LEN) - 1) << USB_EP6_RX_FIFO_RDATA_POS))

/* 0x170 : ep7_fifo_config */
#define USB_EP7_FIFO_CONFIG_OFFSET     (0x170)
#define USB_EP7_DMA_TX_EN              USB_EP7_DMA_TX_EN
#define USB_EP7_DMA_TX_EN_POS          (0U)
#define USB_EP7_DMA_TX_EN_LEN          (1U)
#define USB_EP7_DMA_TX_EN_MSK          (((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS)
#define USB_EP7_DMA_TX_EN_UMSK         (~(((1U << USB_EP7_DMA_TX_EN_LEN) - 1) << USB_EP7_DMA_TX_EN_POS))
#define USB_EP7_DMA_RX_EN              USB_EP7_DMA_RX_EN
#define USB_EP7_DMA_RX_EN_POS          (1U)
#define USB_EP7_DMA_RX_EN_LEN          (1U)
#define USB_EP7_DMA_RX_EN_MSK          (((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS)
#define USB_EP7_DMA_RX_EN_UMSK         (~(((1U << USB_EP7_DMA_RX_EN_LEN) - 1) << USB_EP7_DMA_RX_EN_POS))
#define USB_EP7_TX_FIFO_CLR            USB_EP7_TX_FIFO_CLR
#define USB_EP7_TX_FIFO_CLR_POS        (2U)
#define USB_EP7_TX_FIFO_CLR_LEN        (1U)
#define USB_EP7_TX_FIFO_CLR_MSK        (((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS)
#define USB_EP7_TX_FIFO_CLR_UMSK       (~(((1U << USB_EP7_TX_FIFO_CLR_LEN) - 1) << USB_EP7_TX_FIFO_CLR_POS))
#define USB_EP7_RX_FIFO_CLR            USB_EP7_RX_FIFO_CLR
#define USB_EP7_RX_FIFO_CLR_POS        (3U)
#define USB_EP7_RX_FIFO_CLR_LEN        (1U)
#define USB_EP7_RX_FIFO_CLR_MSK        (((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS)
#define USB_EP7_RX_FIFO_CLR_UMSK       (~(((1U << USB_EP7_RX_FIFO_CLR_LEN) - 1) << USB_EP7_RX_FIFO_CLR_POS))
#define USB_EP7_TX_FIFO_OVERFLOW       USB_EP7_TX_FIFO_OVERFLOW
#define USB_EP7_TX_FIFO_OVERFLOW_POS   (4U)
#define USB_EP7_TX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP7_TX_FIFO_OVERFLOW_MSK   (((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS)
#define USB_EP7_TX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP7_TX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_OVERFLOW_POS))
#define USB_EP7_TX_FIFO_UNDERFLOW      USB_EP7_TX_FIFO_UNDERFLOW
#define USB_EP7_TX_FIFO_UNDERFLOW_POS  (5U)
#define USB_EP7_TX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP7_TX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS)
#define USB_EP7_TX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_TX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_TX_FIFO_UNDERFLOW_POS))
#define USB_EP7_RX_FIFO_OVERFLOW       USB_EP7_RX_FIFO_OVERFLOW
#define USB_EP7_RX_FIFO_OVERFLOW_POS   (6U)
#define USB_EP7_RX_FIFO_OVERFLOW_LEN   (1U)
#define USB_EP7_RX_FIFO_OVERFLOW_MSK   (((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS)
#define USB_EP7_RX_FIFO_OVERFLOW_UMSK  (~(((1U << USB_EP7_RX_FIFO_OVERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_OVERFLOW_POS))
#define USB_EP7_RX_FIFO_UNDERFLOW      USB_EP7_RX_FIFO_UNDERFLOW
#define USB_EP7_RX_FIFO_UNDERFLOW_POS  (7U)
#define USB_EP7_RX_FIFO_UNDERFLOW_LEN  (1U)
#define USB_EP7_RX_FIFO_UNDERFLOW_MSK  (((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS)
#define USB_EP7_RX_FIFO_UNDERFLOW_UMSK (~(((1U << USB_EP7_RX_FIFO_UNDERFLOW_LEN) - 1) << USB_EP7_RX_FIFO_UNDERFLOW_POS))

/* 0x174 : ep7_fifo_status */
#define USB_EP7_FIFO_STATUS_OFFSET (0x174)
#define USB_EP7_TX_FIFO_CNT        USB_EP7_TX_FIFO_CNT
#define USB_EP7_TX_FIFO_CNT_POS    (0U)
#define USB_EP7_TX_FIFO_CNT_LEN    (7U)
#define USB_EP7_TX_FIFO_CNT_MSK    (((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS)
#define USB_EP7_TX_FIFO_CNT_UMSK   (~(((1U << USB_EP7_TX_FIFO_CNT_LEN) - 1) << USB_EP7_TX_FIFO_CNT_POS))
#define USB_EP7_TX_FIFO_EMPTY      USB_EP7_TX_FIFO_EMPTY
#define USB_EP7_TX_FIFO_EMPTY_POS  (14U)
#define USB_EP7_TX_FIFO_EMPTY_LEN  (1U)
#define USB_EP7_TX_FIFO_EMPTY_MSK  (((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS)
#define USB_EP7_TX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_TX_FIFO_EMPTY_LEN) - 1) << USB_EP7_TX_FIFO_EMPTY_POS))
#define USB_EP7_TX_FIFO_FULL       USB_EP7_TX_FIFO_FULL
#define USB_EP7_TX_FIFO_FULL_POS   (15U)
#define USB_EP7_TX_FIFO_FULL_LEN   (1U)
#define USB_EP7_TX_FIFO_FULL_MSK   (((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS)
#define USB_EP7_TX_FIFO_FULL_UMSK  (~(((1U << USB_EP7_TX_FIFO_FULL_LEN) - 1) << USB_EP7_TX_FIFO_FULL_POS))
#define USB_EP7_RX_FIFO_CNT        USB_EP7_RX_FIFO_CNT
#define USB_EP7_RX_FIFO_CNT_POS    (16U)
#define USB_EP7_RX_FIFO_CNT_LEN    (7U)
#define USB_EP7_RX_FIFO_CNT_MSK    (((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS)
#define USB_EP7_RX_FIFO_CNT_UMSK   (~(((1U << USB_EP7_RX_FIFO_CNT_LEN) - 1) << USB_EP7_RX_FIFO_CNT_POS))
#define USB_EP7_RX_FIFO_EMPTY      USB_EP7_RX_FIFO_EMPTY
#define USB_EP7_RX_FIFO_EMPTY_POS  (30U)
#define USB_EP7_RX_FIFO_EMPTY_LEN  (1U)
#define USB_EP7_RX_FIFO_EMPTY_MSK  (((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS)
#define USB_EP7_RX_FIFO_EMPTY_UMSK (~(((1U << USB_EP7_RX_FIFO_EMPTY_LEN) - 1) << USB_EP7_RX_FIFO_EMPTY_POS))
#define USB_EP7_RX_FIFO_FULL       USB_EP7_RX_FIFO_FULL
#define USB_EP7_RX_FIFO_FULL_POS   (31U)
#define USB_EP7_RX_FIFO_FULL_LEN   (1U)
#define USB_EP7_RX_FIFO_FULL_MSK   (((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS)
#define USB_EP7_RX_FIFO_FULL_UMSK  (~(((1U << USB_EP7_RX_FIFO_FULL_LEN) - 1) << USB_EP7_RX_FIFO_FULL_POS))

/* 0x178 : ep7_tx_fifo_wdata */
#define USB_EP7_TX_FIFO_WDATA_OFFSET (0x178)
#define USB_EP7_TX_FIFO_WDATA        USB_EP7_TX_FIFO_WDATA
#define USB_EP7_TX_FIFO_WDATA_POS    (0U)
#define USB_EP7_TX_FIFO_WDATA_LEN    (8U)
#define USB_EP7_TX_FIFO_WDATA_MSK    (((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS)
#define USB_EP7_TX_FIFO_WDATA_UMSK   (~(((1U << USB_EP7_TX_FIFO_WDATA_LEN) - 1) << USB_EP7_TX_FIFO_WDATA_POS))

/* 0x17C : ep7_rx_fifo_rdata */
#define USB_EP7_RX_FIFO_RDATA_OFFSET (0x17C)
#define USB_EP7_RX_FIFO_RDATA        USB_EP7_RX_FIFO_RDATA
#define USB_EP7_RX_FIFO_RDATA_POS    (0U)
#define USB_EP7_RX_FIFO_RDATA_LEN    (8U)
#define USB_EP7_RX_FIFO_RDATA_MSK    (((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS)
#define USB_EP7_RX_FIFO_RDATA_UMSK   (~(((1U << USB_EP7_RX_FIFO_RDATA_LEN) - 1) << USB_EP7_RX_FIFO_RDATA_POS))

/* 0x1F0 : rsvd_0 */
#define USB_RSVD_0_OFFSET (0x1F0)

/* 0x1F4 : rsvd_1 */
#define USB_RSVD_1_OFFSET (0x1F4)

/* 0x1FC : xcvr_if_config */
#define USB_XCVR_IF_CONFIG_OFFSET    (0x1FC)
#define USB_CR_XCVR_FORCE_TX_EN      USB_CR_XCVR_FORCE_TX_EN
#define USB_CR_XCVR_FORCE_TX_EN_POS  (0U)
#define USB_CR_XCVR_FORCE_TX_EN_LEN  (1U)
#define USB_CR_XCVR_FORCE_TX_EN_MSK  (((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS)
#define USB_CR_XCVR_FORCE_TX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_EN_POS))
#define USB_CR_XCVR_FORCE_TX_OE      USB_CR_XCVR_FORCE_TX_OE
#define USB_CR_XCVR_FORCE_TX_OE_POS  (1U)
#define USB_CR_XCVR_FORCE_TX_OE_LEN  (1U)
#define USB_CR_XCVR_FORCE_TX_OE_MSK  (((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS)
#define USB_CR_XCVR_FORCE_TX_OE_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_OE_LEN) - 1) << USB_CR_XCVR_FORCE_TX_OE_POS))
#define USB_CR_XCVR_FORCE_TX_DP      USB_CR_XCVR_FORCE_TX_DP
#define USB_CR_XCVR_FORCE_TX_DP_POS  (2U)
#define USB_CR_XCVR_FORCE_TX_DP_LEN  (1U)
#define USB_CR_XCVR_FORCE_TX_DP_MSK  (((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS)
#define USB_CR_XCVR_FORCE_TX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DP_POS))
#define USB_CR_XCVR_FORCE_TX_DN      USB_CR_XCVR_FORCE_TX_DN
#define USB_CR_XCVR_FORCE_TX_DN_POS  (3U)
#define USB_CR_XCVR_FORCE_TX_DN_LEN  (1U)
#define USB_CR_XCVR_FORCE_TX_DN_MSK  (((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS)
#define USB_CR_XCVR_FORCE_TX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_TX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_TX_DN_POS))
#define USB_CR_XCVR_FORCE_RX_EN      USB_CR_XCVR_FORCE_RX_EN
#define USB_CR_XCVR_FORCE_RX_EN_POS  (4U)
#define USB_CR_XCVR_FORCE_RX_EN_LEN  (1U)
#define USB_CR_XCVR_FORCE_RX_EN_MSK  (((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS)
#define USB_CR_XCVR_FORCE_RX_EN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_EN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_EN_POS))
#define USB_CR_XCVR_FORCE_RX_D       USB_CR_XCVR_FORCE_RX_D
#define USB_CR_XCVR_FORCE_RX_D_POS   (5U)
#define USB_CR_XCVR_FORCE_RX_D_LEN   (1U)
#define USB_CR_XCVR_FORCE_RX_D_MSK   (((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS)
#define USB_CR_XCVR_FORCE_RX_D_UMSK  (~(((1U << USB_CR_XCVR_FORCE_RX_D_LEN) - 1) << USB_CR_XCVR_FORCE_RX_D_POS))
#define USB_CR_XCVR_FORCE_RX_DP      USB_CR_XCVR_FORCE_RX_DP
#define USB_CR_XCVR_FORCE_RX_DP_POS  (6U)
#define USB_CR_XCVR_FORCE_RX_DP_LEN  (1U)
#define USB_CR_XCVR_FORCE_RX_DP_MSK  (((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS)
#define USB_CR_XCVR_FORCE_RX_DP_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DP_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DP_POS))
#define USB_CR_XCVR_FORCE_RX_DN      USB_CR_XCVR_FORCE_RX_DN
#define USB_CR_XCVR_FORCE_RX_DN_POS  (7U)
#define USB_CR_XCVR_FORCE_RX_DN_LEN  (1U)
#define USB_CR_XCVR_FORCE_RX_DN_MSK  (((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS)
#define USB_CR_XCVR_FORCE_RX_DN_UMSK (~(((1U << USB_CR_XCVR_FORCE_RX_DN_LEN) - 1) << USB_CR_XCVR_FORCE_RX_DN_POS))
#define USB_CR_XCVR_OM_RX_SEL        USB_CR_XCVR_OM_RX_SEL
#define USB_CR_XCVR_OM_RX_SEL_POS    (8U)
#define USB_CR_XCVR_OM_RX_SEL_LEN    (1U)
#define USB_CR_XCVR_OM_RX_SEL_MSK    (((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS)
#define USB_CR_XCVR_OM_RX_SEL_UMSK   (~(((1U << USB_CR_XCVR_OM_RX_SEL_LEN) - 1) << USB_CR_XCVR_OM_RX_SEL_POS))
#define USB_CR_XCVR_OM_RX_D          USB_CR_XCVR_OM_RX_D
#define USB_CR_XCVR_OM_RX_D_POS      (9U)
#define USB_CR_XCVR_OM_RX_D_LEN      (1U)
#define USB_CR_XCVR_OM_RX_D_MSK      (((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS)
#define USB_CR_XCVR_OM_RX_D_UMSK     (~(((1U << USB_CR_XCVR_OM_RX_D_LEN) - 1) << USB_CR_XCVR_OM_RX_D_POS))
#define USB_CR_XCVR_OM_RX_DP         USB_CR_XCVR_OM_RX_DP
#define USB_CR_XCVR_OM_RX_DP_POS     (10U)
#define USB_CR_XCVR_OM_RX_DP_LEN     (1U)
#define USB_CR_XCVR_OM_RX_DP_MSK     (((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS)
#define USB_CR_XCVR_OM_RX_DP_UMSK    (~(((1U << USB_CR_XCVR_OM_RX_DP_LEN) - 1) << USB_CR_XCVR_OM_RX_DP_POS))
#define USB_CR_XCVR_OM_RX_DN         USB_CR_XCVR_OM_RX_DN
#define USB_CR_XCVR_OM_RX_DN_POS     (11U)
#define USB_CR_XCVR_OM_RX_DN_LEN     (1U)
#define USB_CR_XCVR_OM_RX_DN_MSK     (((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS)
#define USB_CR_XCVR_OM_RX_DN_UMSK    (~(((1U << USB_CR_XCVR_OM_RX_DN_LEN) - 1) << USB_CR_XCVR_OM_RX_DN_POS))
#define USB_STS_VBUS_DET             USB_STS_VBUS_DET
#define USB_STS_VBUS_DET_POS         (31U)
#define USB_STS_VBUS_DET_LEN         (1U)
#define USB_STS_VBUS_DET_MSK         (((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS)
#define USB_STS_VBUS_DET_UMSK        (~(((1U << USB_STS_VBUS_DET_LEN) - 1) << USB_STS_VBUS_DET_POS))

struct usb_reg {
    /* 0x0 : usb_config */
    union {
        struct
        {
            uint32_t cr_usb_en              : 1; /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3           : 3; /* [ 3: 1],       rsvd,        0x0 */
            uint32_t cr_usb_rom_dct_en      : 1; /* [    4],        r/w,        0x1 */
            uint32_t reserved_5_7           : 3; /* [ 7: 5],       rsvd,        0x0 */
            uint32_t cr_usb_ep0_sw_ctrl     : 1; /* [    8],        r/w,        0x0 */
            uint32_t cr_usb_ep0_sw_addr     : 7; /* [15: 9],        r/w,        0x0 */
            uint32_t cr_usb_ep0_sw_size     : 8; /* [23:16],        r/w,        0x0 */
            uint32_t cr_usb_ep0_sw_stall    : 1; /* [   24],        w1c,        0x0 */
            uint32_t cr_usb_ep0_sw_nack_in  : 1; /* [   25],        r/w,        0x1 */
            uint32_t cr_usb_ep0_sw_nack_out : 1; /* [   26],        r/w,        0x0 */
            uint32_t cr_usb_ep0_sw_rdy      : 1; /* [   27],        w1c,        0x0 */
            uint32_t sts_usb_ep0_sw_rdy     : 1; /* [   28],          r,        0x0 */
            uint32_t reserved_29_31         : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_config;

    /* 0x4 : usb_lpm_config */
    union {
        struct
        {
            uint32_t cr_lpm_en       : 1;  /* [    0],        w1c,        0x0 */
            uint32_t cr_lpm_resp_upd : 1;  /* [    1],        w1c,        0x0 */
            uint32_t cr_lpm_resp     : 2;  /* [ 3: 2],        r/w,        0x2 */
            uint32_t reserved_4_19   : 16; /* [19: 4],       rsvd,        0x0 */
            uint32_t sts_lpm_attr    : 11; /* [30:20],          r,        0x0 */
            uint32_t sts_lpm         : 1;  /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_lpm_config;

    /* 0x8 : usb_resume_config */
    union {
        struct
        {
            uint32_t cr_res_width   : 11; /* [10: 0],        r/w,       0x1a */
            uint32_t reserved_11    : 1;  /* [   11],       rsvd,        0x0 */
            uint32_t cr_res_trig    : 1;  /* [   12],        w1c,        0x0 */
            uint32_t reserved_13_30 : 18; /* [30:13],       rsvd,        0x0 */
            uint32_t cr_res_force   : 1;  /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_resume_config;

    /* 0xc  reserved */
    uint8_t RESERVED0xc[4];

    /* 0x10 : usb_setup_data_0 */
    union {
        struct
        {
            uint32_t sts_setup_data_b0 : 8; /* [ 7: 0],          r,        0x0 */
            uint32_t sts_setup_data_b1 : 8; /* [15: 8],          r,        0x0 */
            uint32_t sts_setup_data_b2 : 8; /* [23:16],          r,        0x0 */
            uint32_t sts_setup_data_b3 : 8; /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_setup_data_0;

    /* 0x14 : usb_setup_data_1 */
    union {
        struct
        {
            uint32_t sts_setup_data_b4 : 8; /* [ 7: 0],          r,        0x0 */
            uint32_t sts_setup_data_b5 : 8; /* [15: 8],          r,        0x0 */
            uint32_t sts_setup_data_b6 : 8; /* [23:16],          r,        0x0 */
            uint32_t sts_setup_data_b7 : 8; /* [31:24],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_setup_data_1;

    /* 0x18 : usb_frame_no */
    union {
        struct
        {
            uint32_t sts_frame_no   : 11; /* [10: 0],          r,        0x0 */
            uint32_t reserved_11    : 1;  /* [   11],       rsvd,        0x0 */
            uint32_t sts_pid        : 4;  /* [15:12],          r,        0x0 */
            uint32_t sts_ep_no      : 4;  /* [19:16],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_frame_no;

    /* 0x1C : usb_error */
    union {
        struct
        {
            uint32_t utmi_rx_err   : 1;  /* [    0],          r,        0x0 */
            uint32_t xfer_to_err   : 1;  /* [    1],          r,        0x0 */
            uint32_t ivld_ep_err   : 1;  /* [    2],          r,        0x0 */
            uint32_t pid_seq_err   : 1;  /* [    3],          r,        0x0 */
            uint32_t pid_cks_err   : 1;  /* [    4],          r,        0x0 */
            uint32_t crc5_err      : 1;  /* [    5],          r,        0x0 */
            uint32_t crc16_err     : 1;  /* [    6],          r,        0x0 */
            uint32_t reserved_7_31 : 25; /* [31: 7],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_error;

    /* 0x20 : USB interrupt enable */
    union {
        struct
        {
            uint32_t cr_sof_en            : 1; /* [    0],        r/w,        0x1 */
            uint32_t cr_usb_reset_en      : 1; /* [    1],        r/w,        0x1 */
            uint32_t cr_vbus_tgl_en       : 1; /* [    2],        r/w,        0x1 */
            uint32_t cr_get_dct_cmd_en    : 1; /* [    3],        r/w,        0x1 */
            uint32_t cr_ep0_setup_cmd_en  : 1; /* [    4],        r/w,        0x1 */
            uint32_t cr_ep0_setup_done_en : 1; /* [    5],        r/w,        0x1 */
            uint32_t cr_ep0_in_cmd_en     : 1; /* [    6],        r/w,        0x1 */
            uint32_t cr_ep0_in_done_en    : 1; /* [    7],        r/w,        0x1 */
            uint32_t cr_ep0_out_cmd_en    : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_ep0_out_done_en   : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_ep1_cmd_en        : 1; /* [   10],        r/w,        0x1 */
            uint32_t cr_ep1_done_en       : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_ep2_cmd_en        : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_ep2_done_en       : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_ep3_cmd_en        : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_ep3_done_en       : 1; /* [   15],        r/w,        0x1 */
            uint32_t cr_ep4_cmd_en        : 1; /* [   16],        r/w,        0x1 */
            uint32_t cr_ep4_done_en       : 1; /* [   17],        r/w,        0x1 */
            uint32_t cr_ep5_cmd_en        : 1; /* [   18],        r/w,        0x1 */
            uint32_t cr_ep5_done_en       : 1; /* [   19],        r/w,        0x1 */
            uint32_t cr_ep6_cmd_en        : 1; /* [   20],        r/w,        0x1 */
            uint32_t cr_ep6_done_en       : 1; /* [   21],        r/w,        0x1 */
            uint32_t cr_ep7_cmd_en        : 1; /* [   22],        r/w,        0x1 */
            uint32_t cr_ep7_done_en       : 1; /* [   23],        r/w,        0x1 */
            uint32_t rsvd_26_24           : 3; /* [26:24],       rsvd,        0x0 */
            uint32_t cr_usb_rend_en       : 1; /* [   27],        r/w,        0x0 */
            uint32_t cr_lpm_wkup_en       : 1; /* [   28],        r/w,        0x0 */
            uint32_t cr_lpm_pkt_en        : 1; /* [   29],        r/w,        0x0 */
            uint32_t cr_sof_3ms_en        : 1; /* [   30],        r/w,        0x0 */
            uint32_t cr_usb_err_en        : 1; /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } usb_int_en;

    /* 0x24 : USB interrupt status */
    union {
        struct
        {
            uint32_t sof_int            : 1; /* [    0],          r,        0x0 */
            uint32_t usb_reset_int      : 1; /* [    1],          r,        0x0 */
            uint32_t vbus_tgl_int       : 1; /* [    2],          r,        0x0 */
            uint32_t get_dct_cmd_int    : 1; /* [    3],          r,        0x0 */
            uint32_t ep0_setup_cmd_int  : 1; /* [    4],          r,        0x0 */
            uint32_t ep0_setup_done_int : 1; /* [    5],          r,        0x0 */
            uint32_t ep0_in_cmd_int     : 1; /* [    6],          r,        0x0 */
            uint32_t ep0_in_done_int    : 1; /* [    7],          r,        0x0 */
            uint32_t ep0_out_cmd_int    : 1; /* [    8],          r,        0x0 */
            uint32_t ep0_out_done_int   : 1; /* [    9],          r,        0x0 */
            uint32_t ep1_cmd_int        : 1; /* [   10],          r,        0x0 */
            uint32_t ep1_done_int       : 1; /* [   11],          r,        0x0 */
            uint32_t ep2_cmd_int        : 1; /* [   12],          r,        0x0 */
            uint32_t ep2_done_int       : 1; /* [   13],          r,        0x0 */
            uint32_t ep3_cmd_int        : 1; /* [   14],          r,        0x0 */
            uint32_t ep3_done_int       : 1; /* [   15],          r,        0x0 */
            uint32_t ep4_cmd_int        : 1; /* [   16],          r,        0x0 */
            uint32_t ep4_done_int       : 1; /* [   17],          r,        0x0 */
            uint32_t ep5_cmd_int        : 1; /* [   18],          r,        0x0 */
            uint32_t ep5_done_int       : 1; /* [   19],          r,        0x0 */
            uint32_t ep6_cmd_int        : 1; /* [   20],          r,        0x0 */
            uint32_t ep6_done_int       : 1; /* [   21],          r,        0x0 */
            uint32_t ep7_cmd_int        : 1; /* [   22],          r,        0x0 */
            uint32_t ep7_done_int       : 1; /* [   23],          r,        0x0 */
            uint32_t rsvd_26_24         : 3; /* [26:24],       rsvd,        0x0 */
            uint32_t usb_rend_int       : 1; /* [   27],          r,        0x0 */
            uint32_t lpm_wkup_int       : 1; /* [   28],          r,        0x0 */
            uint32_t lpm_pkt_int        : 1; /* [   29],          r,        0x0 */
            uint32_t sof_3ms_int        : 1; /* [   30],          r,        0x0 */
            uint32_t usb_err_int        : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_int_sts;

    /* 0x28 : USB interrupt mask */
    union {
        struct
        {
            uint32_t cr_sof_mask            : 1; /* [    0],        r/w,        0x1 */
            uint32_t cr_usb_reset_mask      : 1; /* [    1],        r/w,        0x1 */
            uint32_t cr_vbus_tgl_mask       : 1; /* [    2],        r/w,        0x1 */
            uint32_t cr_get_dct_cmd_mask    : 1; /* [    3],        r/w,        0x1 */
            uint32_t cr_ep0_setup_cmd_mask  : 1; /* [    4],        r/w,        0x1 */
            uint32_t cr_ep0_setup_done_mask : 1; /* [    5],        r/w,        0x1 */
            uint32_t cr_ep0_in_cmd_mask     : 1; /* [    6],        r/w,        0x1 */
            uint32_t cr_ep0_in_done_mask    : 1; /* [    7],        r/w,        0x1 */
            uint32_t cr_ep0_out_cmd_mask    : 1; /* [    8],        r/w,        0x1 */
            uint32_t cr_ep0_out_done_mask   : 1; /* [    9],        r/w,        0x1 */
            uint32_t cr_ep1_cmd_mask        : 1; /* [   10],        r/w,        0x1 */
            uint32_t cr_ep1_done_mask       : 1; /* [   11],        r/w,        0x1 */
            uint32_t cr_ep2_cmd_mask        : 1; /* [   12],        r/w,        0x1 */
            uint32_t cr_ep2_done_mask       : 1; /* [   13],        r/w,        0x1 */
            uint32_t cr_ep3_cmd_mask        : 1; /* [   14],        r/w,        0x1 */
            uint32_t cr_ep3_done_mask       : 1; /* [   15],        r/w,        0x1 */
            uint32_t cr_ep4_cmd_mask        : 1; /* [   16],        r/w,        0x1 */
            uint32_t cr_ep4_done_mask       : 1; /* [   17],        r/w,        0x1 */
            uint32_t cr_ep5_cmd_mask        : 1; /* [   18],        r/w,        0x1 */
            uint32_t cr_ep5_done_mask       : 1; /* [   19],        r/w,        0x1 */
            uint32_t cr_ep6_cmd_mask        : 1; /* [   20],        r/w,        0x1 */
            uint32_t cr_ep6_done_mask       : 1; /* [   21],        r/w,        0x1 */
            uint32_t cr_ep7_cmd_mask        : 1; /* [   22],        r/w,        0x1 */
            uint32_t cr_ep7_done_mask       : 1; /* [   23],        r/w,        0x1 */
            uint32_t rsvd_26_24             : 3; /* [26:24],       rsvd,        0x0 */
            uint32_t cr_usb_rend_mask       : 1; /* [   27],        r/w,        0x1 */
            uint32_t cr_lpm_wkup_mask       : 1; /* [   28],        r/w,        0x1 */
            uint32_t cr_lpm_pkt_mask        : 1; /* [   29],        r/w,        0x1 */
            uint32_t cr_sof_3ms_mask        : 1; /* [   30],        r/w,        0x1 */
            uint32_t cr_usb_err_mask        : 1; /* [   31],        r/w,        0x1 */
        } BF;
        uint32_t WORD;
    } usb_int_mask;

    /* 0x2C : USB interrupt clear */
    union {
        struct
        {
            uint32_t cr_sof_clr            : 1; /* [    0],        w1c,        0x0 */
            uint32_t cr_usb_reset_clr      : 1; /* [    1],        w1c,        0x0 */
            uint32_t cr_vbus_tgl_clr       : 1; /* [    2],        w1c,        0x0 */
            uint32_t cr_get_dct_cmd_clr    : 1; /* [    3],        w1c,        0x0 */
            uint32_t cr_ep0_setup_cmd_clr  : 1; /* [    4],        w1c,        0x0 */
            uint32_t cr_ep0_setup_done_clr : 1; /* [    5],        w1c,        0x0 */
            uint32_t cr_ep0_in_cmd_clr     : 1; /* [    6],        w1c,        0x0 */
            uint32_t cr_ep0_in_done_clr    : 1; /* [    7],        w1c,        0x0 */
            uint32_t cr_ep0_out_cmd_clr    : 1; /* [    8],        w1c,        0x0 */
            uint32_t cr_ep0_out_done_clr   : 1; /* [    9],        w1c,        0x0 */
            uint32_t cr_ep1_cmd_clr        : 1; /* [   10],        w1c,        0x0 */
            uint32_t cr_ep1_done_clr       : 1; /* [   11],        w1c,        0x0 */
            uint32_t cr_ep2_cmd_clr        : 1; /* [   12],        w1c,        0x0 */
            uint32_t cr_ep2_done_clr       : 1; /* [   13],        w1c,        0x0 */
            uint32_t cr_ep3_cmd_clr        : 1; /* [   14],        w1c,        0x0 */
            uint32_t cr_ep3_done_clr       : 1; /* [   15],        w1c,        0x0 */
            uint32_t cr_ep4_cmd_clr        : 1; /* [   16],        w1c,        0x0 */
            uint32_t cr_ep4_done_clr       : 1; /* [   17],        w1c,        0x0 */
            uint32_t cr_ep5_cmd_clr        : 1; /* [   18],        w1c,        0x0 */
            uint32_t cr_ep5_done_clr       : 1; /* [   19],        w1c,        0x0 */
            uint32_t cr_ep6_cmd_clr        : 1; /* [   20],        w1c,        0x0 */
            uint32_t cr_ep6_done_clr       : 1; /* [   21],        w1c,        0x0 */
            uint32_t cr_ep7_cmd_clr        : 1; /* [   22],        w1c,        0x0 */
            uint32_t cr_ep7_done_clr       : 1; /* [   23],        w1c,        0x0 */
            uint32_t rsvd_26_24            : 3; /* [26:24],       rsvd,        0x0 */
            uint32_t cr_usb_rend_clr       : 1; /* [   27],        w1c,        0x0 */
            uint32_t cr_lpm_wkup_clr       : 1; /* [   28],        w1c,        0x0 */
            uint32_t cr_lpm_pkt_clr        : 1; /* [   29],        w1c,        0x0 */
            uint32_t cr_sof_3ms_clr        : 1; /* [   30],        w1c,        0x0 */
            uint32_t cr_usb_err_clr        : 1; /* [   31],        w1c,        0x0 */
        } BF;
        uint32_t WORD;
    } usb_int_clear;

    /* 0x30  reserved */
    uint8_t RESERVED0x30[16];

    /* 0x40 : ep1_config */
    union {
        struct
        {
            uint32_t cr_ep1_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep1_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep1_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep1_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep1_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep1_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep1_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep1_config;

    /* 0x44 : ep2_config */
    union {
        struct
        {
            uint32_t cr_ep2_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep2_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep2_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep2_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep2_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep2_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep2_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep2_config;

    /* 0x48 : ep3_config */
    union {
        struct
        {
            uint32_t cr_ep3_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep3_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep3_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep3_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep3_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep3_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep3_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep3_config;

    /* 0x4C : ep4_config */
    union {
        struct
        {
            uint32_t cr_ep4_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep4_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep4_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep4_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep4_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep4_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep4_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep4_config;

    /* 0x50 : ep5_config */
    union {
        struct
        {
            uint32_t cr_ep5_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep5_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep5_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep5_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep5_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep5_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep5_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep5_config;

    /* 0x54 : ep6_config */
    union {
        struct
        {
            uint32_t cr_ep6_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep6_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep6_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep6_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep6_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep6_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep6_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep6_config;

    /* 0x58 : ep7_config */
    union {
        struct
        {
            uint32_t cr_ep7_size    : 11; /* [10: 0],        r/w,       0x40 */
            uint32_t cr_ep7_dir     : 2;  /* [12:11],        r/w,        0x1 */
            uint32_t cr_ep7_type    : 3;  /* [15:13],        r/w,        0x4 */
            uint32_t cr_ep7_stall   : 1;  /* [   16],        r/w,        0x0 */
            uint32_t cr_ep7_nack    : 1;  /* [   17],        r/w,        0x1 */
            uint32_t cr_ep7_rdy     : 1;  /* [   18],        w1c,        0x0 */
            uint32_t sts_ep7_rdy    : 1;  /* [   19],          r,        0x0 */
            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep7_config;

    /* 0x5c  reserved */
    uint8_t RESERVED0x5c[164];

    /* 0x100 : ep0_fifo_config */
    union {
        struct
        {
            uint32_t ep0_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep0_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep0_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep0_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep0_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep0_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep0_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep0_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep0_fifo_config;

    /* 0x104 : ep0_fifo_status */
    union {
        struct
        {
            uint32_t ep0_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep0_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep0_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep0_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep0_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep0_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep0_fifo_status;

    /* 0x108 : ep0_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep0_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep0_tx_fifo_wdata;

    /* 0x10C : ep0_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep0_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep0_rx_fifo_rdata;

    /* 0x110 : ep1_fifo_config */
    union {
        struct
        {
            uint32_t ep1_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep1_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep1_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep1_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep1_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep1_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep1_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep1_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep1_fifo_config;

    /* 0x114 : ep1_fifo_status */
    union {
        struct
        {
            uint32_t ep1_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep1_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep1_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep1_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep1_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep1_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep1_fifo_status;

    /* 0x118 : ep1_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep1_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep1_tx_fifo_wdata;

    /* 0x11C : ep1_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep1_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep1_rx_fifo_rdata;

    /* 0x120 : ep2_fifo_config */
    union {
        struct
        {
            uint32_t ep2_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep2_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep2_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep2_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep2_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep2_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep2_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep2_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep2_fifo_config;

    /* 0x124 : ep2_fifo_status */
    union {
        struct
        {
            uint32_t ep2_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep2_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep2_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep2_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep2_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep2_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep2_fifo_status;

    /* 0x128 : ep2_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep2_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep2_tx_fifo_wdata;

    /* 0x12C : ep2_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep2_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep2_rx_fifo_rdata;

    /* 0x130 : ep3_fifo_config */
    union {
        struct
        {
            uint32_t ep3_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep3_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep3_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep3_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep3_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep3_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep3_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep3_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep3_fifo_config;

    /* 0x134 : ep3_fifo_status */
    union {
        struct
        {
            uint32_t ep3_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep3_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep3_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep3_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep3_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep3_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep3_fifo_status;

    /* 0x138 : ep3_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep3_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep3_tx_fifo_wdata;

    /* 0x13C : ep3_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep3_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep3_rx_fifo_rdata;

    /* 0x140 : ep4_fifo_config */
    union {
        struct
        {
            uint32_t ep4_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep4_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep4_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep4_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep4_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep4_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep4_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep4_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep4_fifo_config;

    /* 0x144 : ep4_fifo_status */
    union {
        struct
        {
            uint32_t ep4_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep4_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep4_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep4_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep4_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep4_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep4_fifo_status;

    /* 0x148 : ep4_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep4_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep4_tx_fifo_wdata;

    /* 0x14C : ep4_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep4_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep4_rx_fifo_rdata;

    /* 0x150 : ep5_fifo_config */
    union {
        struct
        {
            uint32_t ep5_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep5_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep5_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep5_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep5_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep5_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep5_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep5_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep5_fifo_config;

    /* 0x154 : ep5_fifo_status */
    union {
        struct
        {
            uint32_t ep5_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep5_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep5_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep5_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep5_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep5_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep5_fifo_status;

    /* 0x158 : ep5_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep5_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep5_tx_fifo_wdata;

    /* 0x15C : ep5_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep5_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep5_rx_fifo_rdata;

    /* 0x160 : ep6_fifo_config */
    union {
        struct
        {
            uint32_t ep6_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep6_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep6_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep6_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep6_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep6_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep6_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep6_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep6_fifo_config;

    /* 0x164 : ep6_fifo_status */
    union {
        struct
        {
            uint32_t ep6_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep6_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep6_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep6_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep6_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep6_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep6_fifo_status;

    /* 0x168 : ep6_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep6_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep6_tx_fifo_wdata;

    /* 0x16C : ep6_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep6_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep6_rx_fifo_rdata;

    /* 0x170 : ep7_fifo_config */
    union {
        struct
        {
            uint32_t ep7_dma_tx_en         : 1;  /* [    0],        r/w,        0x0 */
            uint32_t ep7_dma_rx_en         : 1;  /* [    1],        r/w,        0x0 */
            uint32_t ep7_tx_fifo_clr       : 1;  /* [    2],        w1c,        0x0 */
            uint32_t ep7_rx_fifo_clr       : 1;  /* [    3],        w1c,        0x0 */
            uint32_t ep7_tx_fifo_overflow  : 1;  /* [    4],          r,        0x0 */
            uint32_t ep7_tx_fifo_underflow : 1;  /* [    5],          r,        0x0 */
            uint32_t ep7_rx_fifo_overflow  : 1;  /* [    6],          r,        0x0 */
            uint32_t ep7_rx_fifo_underflow : 1;  /* [    7],          r,        0x0 */
            uint32_t reserved_8_31         : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep7_fifo_config;

    /* 0x174 : ep7_fifo_status */
    union {
        struct
        {
            uint32_t ep7_tx_fifo_cnt   : 7; /* [ 6: 0],          r,       0x40 */
            uint32_t reserved_7_13     : 7; /* [13: 7],       rsvd,        0x0 */
            uint32_t ep7_tx_fifo_empty : 1; /* [   14],          r,        0x1 */
            uint32_t ep7_tx_fifo_full  : 1; /* [   15],          r,        0x0 */
            uint32_t ep7_rx_fifo_cnt   : 7; /* [22:16],          r,        0x0 */
            uint32_t reserved_23_29    : 7; /* [29:23],       rsvd,        0x0 */
            uint32_t ep7_rx_fifo_empty : 1; /* [   30],          r,        0x1 */
            uint32_t ep7_rx_fifo_full  : 1; /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } ep7_fifo_status;

    /* 0x178 : ep7_tx_fifo_wdata */
    union {
        struct
        {
            uint32_t ep7_tx_fifo_wdata : 8;  /* [ 7: 0],          w,          x */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep7_tx_fifo_wdata;

    /* 0x17C : ep7_rx_fifo_rdata */
    union {
        struct
        {
            uint32_t ep7_rx_fifo_rdata : 8;  /* [ 7: 0],          r,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } ep7_rx_fifo_rdata;

    /* 0x180  reserved */
    uint8_t RESERVED0x180[112];

    /* 0x1F0 : rsvd_0 */
    union {
        struct
        {
            uint32_t rsvd_0 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rsvd_0;

    /* 0x1F4 : rsvd_1 */
    union {
        struct
        {
            uint32_t rsvd_1 : 32; /* [31: 0],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } rsvd_1;

    /* 0x1f8  reserved */
    uint8_t RESERVED0x1f8[4];

    /* 0x1FC : xcvr_if_config */
    union {
        struct
        {
            uint32_t cr_xcvr_force_tx_en : 1;  /* [    0],        r/w,        0x0 */
            uint32_t cr_xcvr_force_tx_oe : 1;  /* [    1],        r/w,        0x0 */
            uint32_t cr_xcvr_force_tx_dp : 1;  /* [    2],        r/w,        0x1 */
            uint32_t cr_xcvr_force_tx_dn : 1;  /* [    3],        r/w,        0x0 */
            uint32_t cr_xcvr_force_rx_en : 1;  /* [    4],        r/w,        0x0 */
            uint32_t cr_xcvr_force_rx_d  : 1;  /* [    5],        r/w,        0x1 */
            uint32_t cr_xcvr_force_rx_dp : 1;  /* [    6],        r/w,        0x1 */
            uint32_t cr_xcvr_force_rx_dn : 1;  /* [    7],        r/w,        0x0 */
            uint32_t cr_xcvr_om_rx_sel   : 1;  /* [    8],        r/w,        0x0 */
            uint32_t cr_xcvr_om_rx_d     : 1;  /* [    9],        r/w,        0x1 */
            uint32_t cr_xcvr_om_rx_dp    : 1;  /* [   10],        r/w,        0x1 */
            uint32_t cr_xcvr_om_rx_dn    : 1;  /* [   11],        r/w,        0x0 */
            uint32_t reserved_12_30      : 19; /* [30:12],       rsvd,        0x0 */
            uint32_t sts_vbus_det        : 1;  /* [   31],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } xcvr_if_config;
};

typedef volatile struct usb_reg usb_reg_t;

#endif /* __USB_REG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/clic.h
================================================
// See LICENSE for license details.

#ifndef _SIFIVE_CLIC_H
#define _SIFIVE_CLIC_H

#define CLIC_CTRL_ADDR  0x02000000UL
#define CLIC_HART0_ADDR 0x02800000UL

#define CLIC_MSIP          0x0000
#define CLIC_MSIP_size     0x4
#define CLIC_MTIMECMP      0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME         0xBFF8
#define CLIC_MTIME_size    0x8

#define CLIC_INTIP  0x000
#define CLIC_INTIE  0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG    0xc00

#endif /* _SIFIVE_CLIC_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_bits.h
================================================
// See LICENSE for license details.
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H

#define likely(x)   __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)

#define ROUNDUP(a, b)   ((((a)-1) / (b) + 1) * (b))
#define ROUNDDOWN(a, b) ((a) / (b) * (b))

#define MAX(a, b)        ((a) > (b) ? (a) : (b))
#define MIN(a, b)        ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)

#define EXTRACT_FIELD(val, which)          (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))

#define STR(x)  XSTR(x)
#define XSTR(x) #x

#if __riscv_xlen == 64
#define SLL32        sllw
#define STORE        sd
#define LOAD         ld
#define LWU          lwu
#define LOG_REGBYTES 3
#else
#define SLL32        sll
#define STORE        sw
#define LOAD         lw
#define LWU          lw
#define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_const.h
================================================
// See LICENSE for license details.
/* Derived from  */

#ifndef _RISCV_CONST_H
#define _RISCV_CONST_H

#ifdef __ASSEMBLER__
#define _AC(X, Y) X
#define _AT(T, X) X
#else
#define _AC(X, Y) (X##Y)
#define _AT(T, X) ((T)(X))
#endif /* !__ASSEMBLER__*/

#define _BITUL(x)  (_AC(1, UL) << (x))
#define _BITULL(x) (_AC(1, ULL) << (x))

#endif /* _NUCLEI_CONST_H */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h
================================================
// See LICENSE for license details.

#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H

#define MSTATUS_UIE  0x00000001
#define MSTATUS_SIE  0x00000002
#define MSTATUS_HIE  0x00000004
#define MSTATUS_MIE  0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP  0x00000100
#define MSTATUS_MPP  0x00001800
#define MSTATUS_FS   0x00006000
#define MSTATUS_XS   0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_PUM  0x00040000
#define MSTATUS_MXR  0x00080000
#define MSTATUS_VM   0x1F000000
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000

#define SSTATUS_UIE  0x00000001
#define SSTATUS_SIE  0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP  0x00000100
#define SSTATUS_FS   0x00006000
#define SSTATUS_XS   0x00018000
#define SSTATUS_PUM  0x00040000
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000

#define DCSR_XDEBUGVER (3U << 30)
#define DCSR_NDRESET   (1 << 29)
#define DCSR_FULLRESET (1 << 28)
#define DCSR_EBREAKM   (1 << 15)
#define DCSR_EBREAKH   (1 << 14)
#define DCSR_EBREAKS   (1 << 13)
#define DCSR_EBREAKU   (1 << 12)
#define DCSR_STOPCYCLE (1 << 10)
#define DCSR_STOPTIME  (1 << 9)
#define DCSR_CAUSE     (7 << 6)
#define DCSR_DEBUGINT  (1 << 5)
#define DCSR_HALT      (1 << 3)
#define DCSR_STEP      (1 << 2)
#define DCSR_PRV       (3 << 0)

#define DCSR_CAUSE_NONE     0
#define DCSR_CAUSE_SWBP     1
#define DCSR_CAUSE_HWBP     2
#define DCSR_CAUSE_DEBUGINT 3
#define DCSR_CAUSE_STEP     4
#define DCSR_CAUSE_HALT     5

#define MCONTROL_TYPE(xlen)    (0xfULL << ((xlen)-4))
#define MCONTROL_DMODE(xlen)   (1ULL << ((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))

#define MCONTROL_SELECT  (1 << 19)
#define MCONTROL_TIMING  (1 << 18)
#define MCONTROL_ACTION  (0x3f << 12)
#define MCONTROL_CHAIN   (1 << 11)
#define MCONTROL_MATCH   (0xf << 7)
#define MCONTROL_M       (1 << 6)
#define MCONTROL_H       (1 << 5)
#define MCONTROL_S       (1 << 4)
#define MCONTROL_U       (1 << 3)
#define MCONTROL_EXECUTE (1 << 2)
#define MCONTROL_STORE   (1 << 1)
#define MCONTROL_LOAD    (1 << 0)

#define MCONTROL_TYPE_NONE  0
#define MCONTROL_TYPE_MATCH 2

#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
#define MCONTROL_ACTION_DEBUG_MODE      1
#define MCONTROL_ACTION_TRACE_START     2
#define MCONTROL_ACTION_TRACE_STOP      3
#define MCONTROL_ACTION_TRACE_EMIT      4

#define MCONTROL_MATCH_EQUAL     0
#define MCONTROL_MATCH_NAPOT     1
#define MCONTROL_MATCH_GE        2
#define MCONTROL_MATCH_LT        3
#define MCONTROL_MATCH_MASK_LOW  4
#define MCONTROL_MATCH_MASK_HIGH 5

#define MIP_SSIP (1 << IRQ_S_SOFT)
#define MIP_HSIP (1 << IRQ_H_SOFT)
#define MIP_MSIP (1 << IRQ_M_SOFT)
#define MIP_STIP (1 << IRQ_S_TIMER)
#define MIP_HTIP (1 << IRQ_H_TIMER)
#define MIP_MTIP (1 << IRQ_M_TIMER)
#define MIP_SEIP (1 << IRQ_S_EXT)
#define MIP_HEIP (1 << IRQ_H_EXT)
#define MIP_MEIP (1 << IRQ_M_EXT)

#define MIE_SSIE MIP_SSIP
#define MIE_HSIE MIP_HSIP
#define MIE_MSIE MIP_MSIP
#define MIE_STIE MIP_STIP
#define MIE_HTIE MIP_HTIP
#define MIE_MTIE MIP_MTIP
#define MIE_SEIE MIP_SEIP
#define MIE_HEIE MIP_HEIP
#define MIE_MEIE MIP_MEIP

#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP

#define PRV_U 0
#define PRV_S 1
#define PRV_H 2
#define PRV_M 3

#define VM_MBARE 0
#define VM_MBB   1
#define VM_MBBID 2
#define VM_SV32  8
#define VM_SV39  9
#define VM_SV48  10

#define IRQ_S_SOFT  1
#define IRQ_H_SOFT  2
#define IRQ_M_SOFT  3
#define IRQ_S_TIMER 5
#define IRQ_H_TIMER 6
#define IRQ_M_TIMER 7
#define IRQ_S_EXT   9
#define IRQ_H_EXT   10
#define IRQ_M_EXT   11
#define IRQ_COP     12
#define IRQ_HOST    13

#define DEFAULT_RSTVEC     0x00001000
#define DEFAULT_NMIVEC     0x00001004
#define DEFAULT_MTVEC      0x00001010
#define CONFIG_STRING_ADDR 0x0000100C
#define EXT_IO_BASE        0x40000000
#define DRAM_BASE          0x80000000

// page table entry (PTE) fields
#define PTE_V    0x001 // Valid
#define PTE_R    0x002 // Read
#define PTE_W    0x004 // Write
#define PTE_X    0x008 // Execute
#define PTE_U    0x010 // User
#define PTE_G    0x020 // Global
#define PTE_A    0x040 // Accessed
#define PTE_D    0x080 // Dirty
#define PTE_SOFT 0x300 // Reserved for Software

#define PTE_PPN_SHIFT 10

#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

#ifdef __riscv

#ifdef __riscv64
#define MSTATUS_SD         MSTATUS64_SD
#define SSTATUS_SD         SSTATUS64_SD
#define RISCV_PGLEVEL_BITS 9
#else
#define MSTATUS_SD         MSTATUS32_SD
#define SSTATUS_SD         SSTATUS32_SD
#define RISCV_PGLEVEL_BITS 10
#endif
#define RISCV_PGSHIFT 12
#define RISCV_PGSIZE  (1 << RISCV_PGSHIFT)

#ifndef __ASSEMBLER__

#ifdef __GNUC__

#define asm __asm

#define read_fpu(reg) ({ unsigned long __tmp; \
        asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
        __tmp; })

#define write_fpu(reg, val) ({ \
        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
            asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \
        else \
            asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })

#define read_csr(reg) ({ unsigned long __tmp; \
        asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
        __tmp; })

#define write_csr(reg, val) ({ \
        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
            asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
        else \
            asm volatile ("csrw " #reg ", %0" :: "r"(val)); })

#define swap_csr(reg, val) ({ unsigned long __tmp; \
        if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
            asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
        else \
            asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
        __tmp; })

#define set_csr(reg, bit) ({ unsigned long __tmp; \
        if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
            asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
        else \
            asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
        __tmp; })

#define clear_csr(reg, bit) ({ unsigned long __tmp; \
        if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
            asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
        else \
            asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
        __tmp; })

#define rdtime()    read_csr(time)
#define rdcycle()   read_csr(cycle)
#define rdinstret() read_csr(instret)
#define get_pc() read_csr(mepc)

#endif

#endif

#endif

#endif
/* Automatically generated by parse-opcodes */
#ifndef RISCV_ENCODING_H
#define RISCV_ENCODING_H
#define MATCH_BEQ                0x63
#define MASK_BEQ                 0x707f
#define MATCH_BNE                0x1063
#define MASK_BNE                 0x707f
#define MATCH_BLT                0x4063
#define MASK_BLT                 0x707f
#define MATCH_BGE                0x5063
#define MASK_BGE                 0x707f
#define MATCH_BLTU               0x6063
#define MASK_BLTU                0x707f
#define MATCH_BGEU               0x7063
#define MASK_BGEU                0x707f
#define MATCH_JALR               0x67
#define MASK_JALR                0x707f
#define MATCH_JAL                0x6f
#define MASK_JAL                 0x7f
#define MATCH_LUI                0x37
#define MASK_LUI                 0x7f
#define MATCH_AUIPC              0x17
#define MASK_AUIPC               0x7f
#define MATCH_ADDI               0x13
#define MASK_ADDI                0x707f
#define MATCH_SLLI               0x1013
#define MASK_SLLI                0xfc00707f
#define MATCH_SLTI               0x2013
#define MASK_SLTI                0x707f
#define MATCH_SLTIU              0x3013
#define MASK_SLTIU               0x707f
#define MATCH_XORI               0x4013
#define MASK_XORI                0x707f
#define MATCH_SRLI               0x5013
#define MASK_SRLI                0xfc00707f
#define MATCH_SRAI               0x40005013
#define MASK_SRAI                0xfc00707f
#define MATCH_ORI                0x6013
#define MASK_ORI                 0x707f
#define MATCH_ANDI               0x7013
#define MASK_ANDI                0x707f
#define MATCH_ADD                0x33
#define MASK_ADD                 0xfe00707f
#define MATCH_SUB                0x40000033
#define MASK_SUB                 0xfe00707f
#define MATCH_SLL                0x1033
#define MASK_SLL                 0xfe00707f
#define MATCH_SLT                0x2033
#define MASK_SLT                 0xfe00707f
#define MATCH_SLTU               0x3033
#define MASK_SLTU                0xfe00707f
#define MATCH_XOR                0x4033
#define MASK_XOR                 0xfe00707f
#define MATCH_SRL                0x5033
#define MASK_SRL                 0xfe00707f
#define MATCH_SRA                0x40005033
#define MASK_SRA                 0xfe00707f
#define MATCH_OR                 0x6033
#define MASK_OR                  0xfe00707f
#define MATCH_AND                0x7033
#define MASK_AND                 0xfe00707f
#define MATCH_ADDIW              0x1b
#define MASK_ADDIW               0x707f
#define MATCH_SLLIW              0x101b
#define MASK_SLLIW               0xfe00707f
#define MATCH_SRLIW              0x501b
#define MASK_SRLIW               0xfe00707f
#define MATCH_SRAIW              0x4000501b
#define MASK_SRAIW               0xfe00707f
#define MATCH_ADDW               0x3b
#define MASK_ADDW                0xfe00707f
#define MATCH_SUBW               0x4000003b
#define MASK_SUBW                0xfe00707f
#define MATCH_SLLW               0x103b
#define MASK_SLLW                0xfe00707f
#define MATCH_SRLW               0x503b
#define MASK_SRLW                0xfe00707f
#define MATCH_SRAW               0x4000503b
#define MASK_SRAW                0xfe00707f
#define MATCH_LB                 0x3
#define MASK_LB                  0x707f
#define MATCH_LH                 0x1003
#define MASK_LH                  0x707f
#define MATCH_LW                 0x2003
#define MASK_LW                  0x707f
#define MATCH_LD                 0x3003
#define MASK_LD                  0x707f
#define MATCH_LBU                0x4003
#define MASK_LBU                 0x707f
#define MATCH_LHU                0x5003
#define MASK_LHU                 0x707f
#define MATCH_LWU                0x6003
#define MASK_LWU                 0x707f
#define MATCH_SB                 0x23
#define MASK_SB                  0x707f
#define MATCH_SH                 0x1023
#define MASK_SH                  0x707f
#define MATCH_SW                 0x2023
#define MASK_SW                  0x707f
#define MATCH_SD                 0x3023
#define MASK_SD                  0x707f
#define MATCH_FENCE              0xf
#define MASK_FENCE               0x707f
#define MATCH_FENCE_I            0x100f
#define MASK_FENCE_I             0x707f
#define MATCH_MUL                0x2000033
#define MASK_MUL                 0xfe00707f
#define MATCH_MULH               0x2001033
#define MASK_MULH                0xfe00707f
#define MATCH_MULHSU             0x2002033
#define MASK_MULHSU              0xfe00707f
#define MATCH_MULHU              0x2003033
#define MASK_MULHU               0xfe00707f
#define MATCH_DIV                0x2004033
#define MASK_DIV                 0xfe00707f
#define MATCH_DIVU               0x2005033
#define MASK_DIVU                0xfe00707f
#define MATCH_REM                0x2006033
#define MASK_REM                 0xfe00707f
#define MATCH_REMU               0x2007033
#define MASK_REMU                0xfe00707f
#define MATCH_MULW               0x200003b
#define MASK_MULW                0xfe00707f
#define MATCH_DIVW               0x200403b
#define MASK_DIVW                0xfe00707f
#define MATCH_DIVUW              0x200503b
#define MASK_DIVUW               0xfe00707f
#define MATCH_REMW               0x200603b
#define MASK_REMW                0xfe00707f
#define MATCH_REMUW              0x200703b
#define MASK_REMUW               0xfe00707f
#define MATCH_AMOADD_W           0x202f
#define MASK_AMOADD_W            0xf800707f
#define MATCH_AMOXOR_W           0x2000202f
#define MASK_AMOXOR_W            0xf800707f
#define MATCH_AMOOR_W            0x4000202f
#define MASK_AMOOR_W             0xf800707f
#define MATCH_AMOAND_W           0x6000202f
#define MASK_AMOAND_W            0xf800707f
#define MATCH_AMOMIN_W           0x8000202f
#define MASK_AMOMIN_W            0xf800707f
#define MATCH_AMOMAX_W           0xa000202f
#define MASK_AMOMAX_W            0xf800707f
#define MATCH_AMOMINU_W          0xc000202f
#define MASK_AMOMINU_W           0xf800707f
#define MATCH_AMOMAXU_W          0xe000202f
#define MASK_AMOMAXU_W           0xf800707f
#define MATCH_AMOSWAP_W          0x800202f
#define MASK_AMOSWAP_W           0xf800707f
#define MATCH_LR_W               0x1000202f
#define MASK_LR_W                0xf9f0707f
#define MATCH_SC_W               0x1800202f
#define MASK_SC_W                0xf800707f
#define MATCH_AMOADD_D           0x302f
#define MASK_AMOADD_D            0xf800707f
#define MATCH_AMOXOR_D           0x2000302f
#define MASK_AMOXOR_D            0xf800707f
#define MATCH_AMOOR_D            0x4000302f
#define MASK_AMOOR_D             0xf800707f
#define MATCH_AMOAND_D           0x6000302f
#define MASK_AMOAND_D            0xf800707f
#define MATCH_AMOMIN_D           0x8000302f
#define MASK_AMOMIN_D            0xf800707f
#define MATCH_AMOMAX_D           0xa000302f
#define MASK_AMOMAX_D            0xf800707f
#define MATCH_AMOMINU_D          0xc000302f
#define MASK_AMOMINU_D           0xf800707f
#define MATCH_AMOMAXU_D          0xe000302f
#define MASK_AMOMAXU_D           0xf800707f
#define MATCH_AMOSWAP_D          0x800302f
#define MASK_AMOSWAP_D           0xf800707f
#define MATCH_LR_D               0x1000302f
#define MASK_LR_D                0xf9f0707f
#define MATCH_SC_D               0x1800302f
#define MASK_SC_D                0xf800707f
#define MATCH_ECALL              0x73
#define MASK_ECALL               0xffffffff
#define MATCH_EBREAK             0x100073
#define MASK_EBREAK              0xffffffff
#define MATCH_URET               0x200073
#define MASK_URET                0xffffffff
#define MATCH_SRET               0x10200073
#define MASK_SRET                0xffffffff
#define MATCH_HRET               0x20200073
#define MASK_HRET                0xffffffff
#define MATCH_MRET               0x30200073
#define MASK_MRET                0xffffffff
#define MATCH_DRET               0x7b200073
#define MASK_DRET                0xffffffff
#define MATCH_SFENCE_VM          0x10400073
#define MASK_SFENCE_VM           0xfff07fff
#define MATCH_WFI                0x10500073
#define MASK_WFI                 0xffffffff
#define MATCH_CSRRW              0x1073
#define MASK_CSRRW               0x707f
#define MATCH_CSRRS              0x2073
#define MASK_CSRRS               0x707f
#define MATCH_CSRRC              0x3073
#define MASK_CSRRC               0x707f
#define MATCH_CSRRWI             0x5073
#define MASK_CSRRWI              0x707f
#define MATCH_CSRRSI             0x6073
#define MASK_CSRRSI              0x707f
#define MATCH_CSRRCI             0x7073
#define MASK_CSRRCI              0x707f
#define MATCH_FADD_S             0x53
#define MASK_FADD_S              0xfe00007f
#define MATCH_FSUB_S             0x8000053
#define MASK_FSUB_S              0xfe00007f
#define MATCH_FMUL_S             0x10000053
#define MASK_FMUL_S              0xfe00007f
#define MATCH_FDIV_S             0x18000053
#define MASK_FDIV_S              0xfe00007f
#define MATCH_FSGNJ_S            0x20000053
#define MASK_FSGNJ_S             0xfe00707f
#define MATCH_FSGNJN_S           0x20001053
#define MASK_FSGNJN_S            0xfe00707f
#define MATCH_FSGNJX_S           0x20002053
#define MASK_FSGNJX_S            0xfe00707f
#define MATCH_FMIN_S             0x28000053
#define MASK_FMIN_S              0xfe00707f
#define MATCH_FMAX_S             0x28001053
#define MASK_FMAX_S              0xfe00707f
#define MATCH_FSQRT_S            0x58000053
#define MASK_FSQRT_S             0xfff0007f
#define MATCH_FADD_D             0x2000053
#define MASK_FADD_D              0xfe00007f
#define MATCH_FSUB_D             0xa000053
#define MASK_FSUB_D              0xfe00007f
#define MATCH_FMUL_D             0x12000053
#define MASK_FMUL_D              0xfe00007f
#define MATCH_FDIV_D             0x1a000053
#define MASK_FDIV_D              0xfe00007f
#define MATCH_FSGNJ_D            0x22000053
#define MASK_FSGNJ_D             0xfe00707f
#define MATCH_FSGNJN_D           0x22001053
#define MASK_FSGNJN_D            0xfe00707f
#define MATCH_FSGNJX_D           0x22002053
#define MASK_FSGNJX_D            0xfe00707f
#define MATCH_FMIN_D             0x2a000053
#define MASK_FMIN_D              0xfe00707f
#define MATCH_FMAX_D             0x2a001053
#define MASK_FMAX_D              0xfe00707f
#define MATCH_FCVT_S_D           0x40100053
#define MASK_FCVT_S_D            0xfff0007f
#define MATCH_FCVT_D_S           0x42000053
#define MASK_FCVT_D_S            0xfff0007f
#define MATCH_FSQRT_D            0x5a000053
#define MASK_FSQRT_D             0xfff0007f
#define MATCH_FLE_S              0xa0000053
#define MASK_FLE_S               0xfe00707f
#define MATCH_FLT_S              0xa0001053
#define MASK_FLT_S               0xfe00707f
#define MATCH_FEQ_S              0xa0002053
#define MASK_FEQ_S               0xfe00707f
#define MATCH_FLE_D              0xa2000053
#define MASK_FLE_D               0xfe00707f
#define MATCH_FLT_D              0xa2001053
#define MASK_FLT_D               0xfe00707f
#define MATCH_FEQ_D              0xa2002053
#define MASK_FEQ_D               0xfe00707f
#define MATCH_FCVT_W_S           0xc0000053
#define MASK_FCVT_W_S            0xfff0007f
#define MATCH_FCVT_WU_S          0xc0100053
#define MASK_FCVT_WU_S           0xfff0007f
#define MATCH_FCVT_L_S           0xc0200053
#define MASK_FCVT_L_S            0xfff0007f
#define MATCH_FCVT_LU_S          0xc0300053
#define MASK_FCVT_LU_S           0xfff0007f
#define MATCH_FMV_X_S            0xe0000053
#define MASK_FMV_X_S             0xfff0707f
#define MATCH_FCLASS_S           0xe0001053
#define MASK_FCLASS_S            0xfff0707f
#define MATCH_FCVT_W_D           0xc2000053
#define MASK_FCVT_W_D            0xfff0007f
#define MATCH_FCVT_WU_D          0xc2100053
#define MASK_FCVT_WU_D           0xfff0007f
#define MATCH_FCVT_L_D           0xc2200053
#define MASK_FCVT_L_D            0xfff0007f
#define MATCH_FCVT_LU_D          0xc2300053
#define MASK_FCVT_LU_D           0xfff0007f
#define MATCH_FMV_X_D            0xe2000053
#define MASK_FMV_X_D             0xfff0707f
#define MATCH_FCLASS_D           0xe2001053
#define MASK_FCLASS_D            0xfff0707f
#define MATCH_FCVT_S_W           0xd0000053
#define MASK_FCVT_S_W            0xfff0007f
#define MATCH_FCVT_S_WU          0xd0100053
#define MASK_FCVT_S_WU           0xfff0007f
#define MATCH_FCVT_S_L           0xd0200053
#define MASK_FCVT_S_L            0xfff0007f
#define MATCH_FCVT_S_LU          0xd0300053
#define MASK_FCVT_S_LU           0xfff0007f
#define MATCH_FMV_S_X            0xf0000053
#define MASK_FMV_S_X             0xfff0707f
#define MATCH_FCVT_D_W           0xd2000053
#define MASK_FCVT_D_W            0xfff0007f
#define MATCH_FCVT_D_WU          0xd2100053
#define MASK_FCVT_D_WU           0xfff0007f
#define MATCH_FCVT_D_L           0xd2200053
#define MASK_FCVT_D_L            0xfff0007f
#define MATCH_FCVT_D_LU          0xd2300053
#define MASK_FCVT_D_LU           0xfff0007f
#define MATCH_FMV_D_X            0xf2000053
#define MASK_FMV_D_X             0xfff0707f
#define MATCH_FLW                0x2007
#define MASK_FLW                 0x707f
#define MATCH_FLD                0x3007
#define MASK_FLD                 0x707f
#define MATCH_FSW                0x2027
#define MASK_FSW                 0x707f
#define MATCH_FSD                0x3027
#define MASK_FSD                 0x707f
#define MATCH_FMADD_S            0x43
#define MASK_FMADD_S             0x600007f
#define MATCH_FMSUB_S            0x47
#define MASK_FMSUB_S             0x600007f
#define MATCH_FNMSUB_S           0x4b
#define MASK_FNMSUB_S            0x600007f
#define MATCH_FNMADD_S           0x4f
#define MASK_FNMADD_S            0x600007f
#define MATCH_FMADD_D            0x2000043
#define MASK_FMADD_D             0x600007f
#define MATCH_FMSUB_D            0x2000047
#define MASK_FMSUB_D             0x600007f
#define MATCH_FNMSUB_D           0x200004b
#define MASK_FNMSUB_D            0x600007f
#define MATCH_FNMADD_D           0x200004f
#define MASK_FNMADD_D            0x600007f
#define MATCH_C_NOP              0x1
#define MASK_C_NOP               0xffff
#define MATCH_C_ADDI16SP         0x6101
#define MASK_C_ADDI16SP          0xef83
#define MATCH_C_JR               0x8002
#define MASK_C_JR                0xf07f
#define MATCH_C_JALR             0x9002
#define MASK_C_JALR              0xf07f
#define MATCH_C_EBREAK           0x9002
#define MASK_C_EBREAK            0xffff
#define MATCH_C_LD               0x6000
#define MASK_C_LD                0xe003
#define MATCH_C_SD               0xe000
#define MASK_C_SD                0xe003
#define MATCH_C_ADDIW            0x2001
#define MASK_C_ADDIW             0xe003
#define MATCH_C_LDSP             0x6002
#define MASK_C_LDSP              0xe003
#define MATCH_C_SDSP             0xe002
#define MASK_C_SDSP              0xe003
#define MATCH_C_ADDI4SPN         0x0
#define MASK_C_ADDI4SPN          0xe003
#define MATCH_C_FLD              0x2000
#define MASK_C_FLD               0xe003
#define MATCH_C_LW               0x4000
#define MASK_C_LW                0xe003
#define MATCH_C_FLW              0x6000
#define MASK_C_FLW               0xe003
#define MATCH_C_FSD              0xa000
#define MASK_C_FSD               0xe003
#define MATCH_C_SW               0xc000
#define MASK_C_SW                0xe003
#define MATCH_C_FSW              0xe000
#define MASK_C_FSW               0xe003
#define MATCH_C_ADDI             0x1
#define MASK_C_ADDI              0xe003
#define MATCH_C_JAL              0x2001
#define MASK_C_JAL               0xe003
#define MATCH_C_LI               0x4001
#define MASK_C_LI                0xe003
#define MATCH_C_LUI              0x6001
#define MASK_C_LUI               0xe003
#define MATCH_C_SRLI             0x8001
#define MASK_C_SRLI              0xec03
#define MATCH_C_SRAI             0x8401
#define MASK_C_SRAI              0xec03
#define MATCH_C_ANDI             0x8801
#define MASK_C_ANDI              0xec03
#define MATCH_C_SUB              0x8c01
#define MASK_C_SUB               0xfc63
#define MATCH_C_XOR              0x8c21
#define MASK_C_XOR               0xfc63
#define MATCH_C_OR               0x8c41
#define MASK_C_OR                0xfc63
#define MATCH_C_AND              0x8c61
#define MASK_C_AND               0xfc63
#define MATCH_C_SUBW             0x9c01
#define MASK_C_SUBW              0xfc63
#define MATCH_C_ADDW             0x9c21
#define MASK_C_ADDW              0xfc63
#define MATCH_C_J                0xa001
#define MASK_C_J                 0xe003
#define MATCH_C_BEQZ             0xc001
#define MASK_C_BEQZ              0xe003
#define MATCH_C_BNEZ             0xe001
#define MASK_C_BNEZ              0xe003
#define MATCH_C_SLLI             0x2
#define MASK_C_SLLI              0xe003
#define MATCH_C_FLDSP            0x2002
#define MASK_C_FLDSP             0xe003
#define MATCH_C_LWSP             0x4002
#define MASK_C_LWSP              0xe003
#define MATCH_C_FLWSP            0x6002
#define MASK_C_FLWSP             0xe003
#define MATCH_C_MV               0x8002
#define MASK_C_MV                0xf003
#define MATCH_C_ADD              0x9002
#define MASK_C_ADD               0xf003
#define MATCH_C_FSDSP            0xa002
#define MASK_C_FSDSP             0xe003
#define MATCH_C_SWSP             0xc002
#define MASK_C_SWSP              0xe003
#define MATCH_C_FSWSP            0xe002
#define MASK_C_FSWSP             0xe003
#define MATCH_CUSTOM0            0xb
#define MASK_CUSTOM0             0x707f
#define MATCH_CUSTOM0_RS1        0x200b
#define MASK_CUSTOM0_RS1         0x707f
#define MATCH_CUSTOM0_RS1_RS2    0x300b
#define MASK_CUSTOM0_RS1_RS2     0x707f
#define MATCH_CUSTOM0_RD         0x400b
#define MASK_CUSTOM0_RD          0x707f
#define MATCH_CUSTOM0_RD_RS1     0x600b
#define MASK_CUSTOM0_RD_RS1      0x707f
#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
#define MATCH_CUSTOM1            0x2b
#define MASK_CUSTOM1             0x707f
#define MATCH_CUSTOM1_RS1        0x202b
#define MASK_CUSTOM1_RS1         0x707f
#define MATCH_CUSTOM1_RS1_RS2    0x302b
#define MASK_CUSTOM1_RS1_RS2     0x707f
#define MATCH_CUSTOM1_RD         0x402b
#define MASK_CUSTOM1_RD          0x707f
#define MATCH_CUSTOM1_RD_RS1     0x602b
#define MASK_CUSTOM1_RD_RS1      0x707f
#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
#define MATCH_CUSTOM2            0x5b
#define MASK_CUSTOM2             0x707f
#define MATCH_CUSTOM2_RS1        0x205b
#define MASK_CUSTOM2_RS1         0x707f
#define MATCH_CUSTOM2_RS1_RS2    0x305b
#define MASK_CUSTOM2_RS1_RS2     0x707f
#define MATCH_CUSTOM2_RD         0x405b
#define MASK_CUSTOM2_RD          0x707f
#define MATCH_CUSTOM2_RD_RS1     0x605b
#define MASK_CUSTOM2_RD_RS1      0x707f
#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
#define MATCH_CUSTOM3            0x7b
#define MASK_CUSTOM3             0x707f
#define MATCH_CUSTOM3_RS1        0x207b
#define MASK_CUSTOM3_RS1         0x707f
#define MATCH_CUSTOM3_RS1_RS2    0x307b
#define MASK_CUSTOM3_RS1_RS2     0x707f
#define MATCH_CUSTOM3_RD         0x407b
#define MASK_CUSTOM3_RD          0x707f
#define MATCH_CUSTOM3_RD_RS1     0x607b
#define MASK_CUSTOM3_RD_RS1      0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
#define CSR_FFLAGS               0x1
#define CSR_FRM                  0x2
#define CSR_FCSR                 0x3
#define CSR_CYCLE                0xc00
#define CSR_TIME                 0xc01
#define CSR_INSTRET              0xc02
#define CSR_HPMCOUNTER3          0xc03
#define CSR_HPMCOUNTER4          0xc04
#define CSR_HPMCOUNTER5          0xc05
#define CSR_HPMCOUNTER6          0xc06
#define CSR_HPMCOUNTER7          0xc07
#define CSR_HPMCOUNTER8          0xc08
#define CSR_HPMCOUNTER9          0xc09
#define CSR_HPMCOUNTER10         0xc0a
#define CSR_HPMCOUNTER11         0xc0b
#define CSR_HPMCOUNTER12         0xc0c
#define CSR_HPMCOUNTER13         0xc0d
#define CSR_HPMCOUNTER14         0xc0e
#define CSR_HPMCOUNTER15         0xc0f
#define CSR_HPMCOUNTER16         0xc10
#define CSR_HPMCOUNTER17         0xc11
#define CSR_HPMCOUNTER18         0xc12
#define CSR_HPMCOUNTER19         0xc13
#define CSR_HPMCOUNTER20         0xc14
#define CSR_HPMCOUNTER21         0xc15
#define CSR_HPMCOUNTER22         0xc16
#define CSR_HPMCOUNTER23         0xc17
#define CSR_HPMCOUNTER24         0xc18
#define CSR_HPMCOUNTER25         0xc19
#define CSR_HPMCOUNTER26         0xc1a
#define CSR_HPMCOUNTER27         0xc1b
#define CSR_HPMCOUNTER28         0xc1c
#define CSR_HPMCOUNTER29         0xc1d
#define CSR_HPMCOUNTER30         0xc1e
#define CSR_HPMCOUNTER31         0xc1f
#define CSR_SSTATUS              0x100
#define CSR_SIE                  0x104
#define CSR_STVEC                0x105
#define CSR_SSCRATCH             0x140
#define CSR_SEPC                 0x141
#define CSR_SCAUSE               0x142
#define CSR_SBADADDR             0x143
#define CSR_SIP                  0x144
#define CSR_SPTBR                0x180
#define CSR_MSTATUS              0x300
#define CSR_MISA                 0x301
#define CSR_MEDELEG              0x302
#define CSR_MIDELEG              0x303
#define CSR_MIE                  0x304
#define CSR_MTVEC                0x305
#define CSR_MCOUNTEREN           0x306
#define CSR_MSCRATCH             0x340
#define CSR_MEPC                 0x341
#define CSR_MCAUSE               0x342
#define CSR_MBADADDR             0x343
#define CSR_MIP                  0x344
#define CSR_TSELECT              0x7a0
#define CSR_TDATA1               0x7a1
#define CSR_TDATA2               0x7a2
#define CSR_TDATA3               0x7a3
#define CSR_DCSR                 0x7b0
#define CSR_DPC                  0x7b1
#define CSR_DSCRATCH             0x7b2
#define CSR_MCYCLE               0xb00
#define CSR_MINSTRET             0xb02
#define CSR_MHPMCOUNTER3         0xb03
#define CSR_MHPMCOUNTER4         0xb04
#define CSR_MHPMCOUNTER5         0xb05
#define CSR_MHPMCOUNTER6         0xb06
#define CSR_MHPMCOUNTER7         0xb07
#define CSR_MHPMCOUNTER8         0xb08
#define CSR_MHPMCOUNTER9         0xb09
#define CSR_MHPMCOUNTER10        0xb0a
#define CSR_MHPMCOUNTER11        0xb0b
#define CSR_MHPMCOUNTER12        0xb0c
#define CSR_MHPMCOUNTER13        0xb0d
#define CSR_MHPMCOUNTER14        0xb0e
#define CSR_MHPMCOUNTER15        0xb0f
#define CSR_MHPMCOUNTER16        0xb10
#define CSR_MHPMCOUNTER17        0xb11
#define CSR_MHPMCOUNTER18        0xb12
#define CSR_MHPMCOUNTER19        0xb13
#define CSR_MHPMCOUNTER20        0xb14
#define CSR_MHPMCOUNTER21        0xb15
#define CSR_MHPMCOUNTER22        0xb16
#define CSR_MHPMCOUNTER23        0xb17
#define CSR_MHPMCOUNTER24        0xb18
#define CSR_MHPMCOUNTER25        0xb19
#define CSR_MHPMCOUNTER26        0xb1a
#define CSR_MHPMCOUNTER27        0xb1b
#define CSR_MHPMCOUNTER28        0xb1c
#define CSR_MHPMCOUNTER29        0xb1d
#define CSR_MHPMCOUNTER30        0xb1e
#define CSR_MHPMCOUNTER31        0xb1f
#define CSR_MUCOUNTEREN          0x320
#define CSR_MSCOUNTEREN          0x321
#define CSR_MHPMEVENT3           0x323
#define CSR_MHPMEVENT4           0x324
#define CSR_MHPMEVENT5           0x325
#define CSR_MHPMEVENT6           0x326
#define CSR_MHPMEVENT7           0x327
#define CSR_MHPMEVENT8           0x328
#define CSR_MHPMEVENT9           0x329
#define CSR_MHPMEVENT10          0x32a
#define CSR_MHPMEVENT11          0x32b
#define CSR_MHPMEVENT12          0x32c
#define CSR_MHPMEVENT13          0x32d
#define CSR_MHPMEVENT14          0x32e
#define CSR_MHPMEVENT15          0x32f
#define CSR_MHPMEVENT16          0x330
#define CSR_MHPMEVENT17          0x331
#define CSR_MHPMEVENT18          0x332
#define CSR_MHPMEVENT19          0x333
#define CSR_MHPMEVENT20          0x334
#define CSR_MHPMEVENT21          0x335
#define CSR_MHPMEVENT22          0x336
#define CSR_MHPMEVENT23          0x337
#define CSR_MHPMEVENT24          0x338
#define CSR_MHPMEVENT25          0x339
#define CSR_MHPMEVENT26          0x33a
#define CSR_MHPMEVENT27          0x33b
#define CSR_MHPMEVENT28          0x33c
#define CSR_MHPMEVENT29          0x33d
#define CSR_MHPMEVENT30          0x33e
#define CSR_MHPMEVENT31          0x33f
#define CSR_MVENDORID            0xf11
#define CSR_MARCHID              0xf12
#define CSR_MIMPID               0xf13
#define CSR_MHARTID              0xf14
#define CSR_CYCLEH               0xc80
#define CSR_TIMEH                0xc81
#define CSR_INSTRETH             0xc82
#define CSR_HPMCOUNTER3H         0xc83
#define CSR_HPMCOUNTER4H         0xc84
#define CSR_HPMCOUNTER5H         0xc85
#define CSR_HPMCOUNTER6H         0xc86
#define CSR_HPMCOUNTER7H         0xc87
#define CSR_HPMCOUNTER8H         0xc88
#define CSR_HPMCOUNTER9H         0xc89
#define CSR_HPMCOUNTER10H        0xc8a
#define CSR_HPMCOUNTER11H        0xc8b
#define CSR_HPMCOUNTER12H        0xc8c
#define CSR_HPMCOUNTER13H        0xc8d
#define CSR_HPMCOUNTER14H        0xc8e
#define CSR_HPMCOUNTER15H        0xc8f
#define CSR_HPMCOUNTER16H        0xc90
#define CSR_HPMCOUNTER17H        0xc91
#define CSR_HPMCOUNTER18H        0xc92
#define CSR_HPMCOUNTER19H        0xc93
#define CSR_HPMCOUNTER20H        0xc94
#define CSR_HPMCOUNTER21H        0xc95
#define CSR_HPMCOUNTER22H        0xc96
#define CSR_HPMCOUNTER23H        0xc97
#define CSR_HPMCOUNTER24H        0xc98
#define CSR_HPMCOUNTER25H        0xc99
#define CSR_HPMCOUNTER26H        0xc9a
#define CSR_HPMCOUNTER27H        0xc9b
#define CSR_HPMCOUNTER28H        0xc9c
#define CSR_HPMCOUNTER29H        0xc9d
#define CSR_HPMCOUNTER30H        0xc9e
#define CSR_HPMCOUNTER31H        0xc9f
#define CSR_MCYCLEH              0xb80
#define CSR_MINSTRETH            0xb82
#define CSR_MHPMCOUNTER3H        0xb83
#define CSR_MHPMCOUNTER4H        0xb84
#define CSR_MHPMCOUNTER5H        0xb85
#define CSR_MHPMCOUNTER6H        0xb86
#define CSR_MHPMCOUNTER7H        0xb87
#define CSR_MHPMCOUNTER8H        0xb88
#define CSR_MHPMCOUNTER9H        0xb89
#define CSR_MHPMCOUNTER10H       0xb8a
#define CSR_MHPMCOUNTER11H       0xb8b
#define CSR_MHPMCOUNTER12H       0xb8c
#define CSR_MHPMCOUNTER13H       0xb8d
#define CSR_MHPMCOUNTER14H       0xb8e
#define CSR_MHPMCOUNTER15H       0xb8f
#define CSR_MHPMCOUNTER16H       0xb90
#define CSR_MHPMCOUNTER17H       0xb91
#define CSR_MHPMCOUNTER18H       0xb92
#define CSR_MHPMCOUNTER19H       0xb93
#define CSR_MHPMCOUNTER20H       0xb94
#define CSR_MHPMCOUNTER21H       0xb95
#define CSR_MHPMCOUNTER22H       0xb96
#define CSR_MHPMCOUNTER23H       0xb97
#define CSR_MHPMCOUNTER24H       0xb98
#define CSR_MHPMCOUNTER25H       0xb99
#define CSR_MHPMCOUNTER26H       0xb9a
#define CSR_MHPMCOUNTER27H       0xb9b
#define CSR_MHPMCOUNTER28H       0xb9c
#define CSR_MHPMCOUNTER29H       0xb9d
#define CSR_MHPMCOUNTER30H       0xb9e
#define CSR_MHPMCOUNTER31H       0xb9f

#define CSR_MTVT  0x307
#define CSR_MNXTI 0x345

#define CSR_MCOUNTINHIBIT 0x320

#define CSR_MNVEC 0x7C3

#define CSR_MTVT2      0x7EC
#define CSR_JALMNXTI   0x7ED
#define CSR_PUSHMCAUSE 0x7EE
#define CSR_PUSHMEPC   0x7EF
#define CSR_PUSHMSUBM  0x7EB

#define CSR_WFE        0x810
#define CSR_SLEEPVALUE 0x811
#define CSR_TXEVT      0x812

#define CSR_MMISC_CTL 0x7d0
#define CSR_MSUBM     0x7c4

#define CAUSE_MISALIGNED_FETCH    0x0
#define CAUSE_FAULT_FETCH         0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_BREAKPOINT          0x3
#define CAUSE_MISALIGNED_LOAD     0x4
#define CAUSE_FAULT_LOAD          0x5
#define CAUSE_MISALIGNED_STORE    0x6
#define CAUSE_FAULT_STORE         0x7
#define CAUSE_USER_ECALL          0x8
#define CAUSE_SUPERVISOR_ECALL    0x9
#define CAUSE_HYPERVISOR_ECALL    0xa
#define CAUSE_MACHINE_ECALL       0xb
#endif
#ifdef DECLARE_INSN
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
DECLARE_INSN(or, MATCH_OR, MASK_OR)
DECLARE_INSN(and, MATCH_AND, MASK_AND)
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
DECLARE_INSN(lw, MATCH_LW, MASK_LW)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
DECLARE_INSN(sb, MATCH_SB, MASK_SB)
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
DECLARE_INSN(rem, MATCH_REM, MASK_REM)
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
DECLARE_INSN(uret, MATCH_URET, MASK_URET)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
             MASK_CUSTOM0_RD_RS1_RS2)
DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
             MASK_CUSTOM1_RD_RS1_RS2)
DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
             MASK_CUSTOM2_RD_RS1_RS2)
DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
             MASK_CUSTOM3_RD_RS1_RS2)
#endif
#ifdef DECLARE_CSR
DECLARE_CSR(fflags, CSR_FFLAGS)
DECLARE_CSR(frm, CSR_FRM)
DECLARE_CSR(fcsr, CSR_FCSR)
DECLARE_CSR(cycle, CSR_CYCLE)
DECLARE_CSR(time, CSR_TIME)
DECLARE_CSR(instret, CSR_INSTRET)
DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
DECLARE_CSR(sstatus, CSR_SSTATUS)
DECLARE_CSR(sie, CSR_SIE)
DECLARE_CSR(stvec, CSR_STVEC)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE)
DECLARE_CSR(sbadaddr, CSR_SBADADDR)
DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(sptbr, CSR_SPTBR)
DECLARE_CSR(mstatus, CSR_MSTATUS)
DECLARE_CSR(misa, CSR_MISA)
DECLARE_CSR(medeleg, CSR_MEDELEG)
DECLARE_CSR(mideleg, CSR_MIDELEG)
DECLARE_CSR(mie, CSR_MIE)
DECLARE_CSR(mtvec, CSR_MTVEC)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
DECLARE_CSR(mip, CSR_MIP)
DECLARE_CSR(tselect, CSR_TSELECT)
DECLARE_CSR(tdata1, CSR_TDATA1)
DECLARE_CSR(tdata2, CSR_TDATA2)
DECLARE_CSR(tdata3, CSR_TDATA3)
DECLARE_CSR(dcsr, CSR_DCSR)
DECLARE_CSR(dpc, CSR_DPC)
DECLARE_CSR(dscratch, CSR_DSCRATCH)
DECLARE_CSR(mcycle, CSR_MCYCLE)
DECLARE_CSR(minstret, CSR_MINSTRET)
DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
DECLARE_CSR(mvendorid, CSR_MVENDORID)
DECLARE_CSR(marchid, CSR_MARCHID)
DECLARE_CSR(mimpid, CSR_MIMPID)
DECLARE_CSR(mhartid, CSR_MHARTID)
DECLARE_CSR(cycleh, CSR_CYCLEH)
DECLARE_CSR(timeh, CSR_TIMEH)
DECLARE_CSR(instreth, CSR_INSTRETH)
DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
DECLARE_CSR(mcycleh, CSR_MCYCLEH)
DECLARE_CSR(minstreth, CSR_MINSTRETH)
DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/entry.S
================================================
/* Copyright 2018 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include "risc-v/Core/Include/riscv_encoding.h"

/* This code executes before _start, which is contained inside the C library.
 * In embedded systems we want to ensure that _enter, which contains the first
 * code to be executed, can be loaded at a specific address.  To enable this
 * feature we provide the '.text.metal.init.enter' section, which is
 * defined to have the first address being where execution should start. */
.section .text.metal.init.enter
.global _enter
_enter:
    .cfi_startproc

    /* Inform the debugger that there is nowhere to backtrace past _enter. */
    .cfi_undefined ra

    /* The absolute first thing that must happen is configuring the global
     * pointer register, which must be done with relaxation disabled because
     * it's not valid to obtain the address of any symbol without GP
     * configured.  The C environment might go ahead and do this again, but
     * that's safe as it's a fixed register. */
.option push
.option norelax
    la gp, __global_pointer$
.option pop

    /* Disable global interrupt */
    /*clear_csr(mstatus, MSTATUS_MIE);*/
    csrci mstatus,8

    /* Set up a simple trap vector to catch anything that goes wrong early in
     * the boot process. */
    la t0, Trap_Handler_Stub
    /* enable CLIC Vectored mode */
    ori	t0,t0,3
    csrw mtvec, t0
    /* enable chicken bit if core is bullet series*/
    la t0, __metal_chicken_bit
    beqz t0, 1f
    csrwi 0x7C1, 0
1:

    /* There may be pre-initialization routines inside the MBI code that run in
     * C, so here we set up a C environment.  First we set up a stack pointer,
     * which is left as a weak reference in order to allow initialization
     * routines that do not need a stack to be set up to transparently be
     * called. */
    .weak __StackTop
    la sp, __StackTop

    /* Intial the mtvt, MUST BE 64 bytes aligned*/
    .weak __Vectors
    la t0, __Vectors
    // From drivers/bl702_driver/risc-v/Core/Include/riscv_encoding.h
    csrw CSR_MTVT, t0

#ifdef __riscv_float_abi_single
    /* deal with FP */
    /* Is F extension present? */
    csrr t0, misa
    andi t0, t0, (1 << ('F' - 'A'))
    beqz t0, 1f
    /* If so, enable it */
    li t0, MSTATUS_FS
    csrs mstatus, t0
    fssr x0
1:
#endif

    /* Check for an initialization routine and call it if one exists, otherwise
     * just skip over the call entirely.   Note that __metal_initialize isn't
     * actually a full C function, as it doesn't end up with the .bss or .data
     * segments having been initialized.  This is done to avoid putting a
     * burden on systems that can be initialized without having a C environment
     * set up. */
    call SystemInit

    /* start load code to itcm like. */
    call start_load
    // Register at exit cleanup (not required for embedded)
    // la a0, __libc_fini_array
    // call atexit
    /* Call C/C++ constructor start up code */
    call __libc_init_array


    jal System_Post_Init

    /* At this point we can enter the C runtime's startup file.  The arguments
     * to this function are designed to match those provided to the SEE, just
     * so we don't have to write another ABI. */
    
    //Sets argv,argc to 0/null
    csrr a0, mhartid
    li a1, 0
    li a2, 0
    call main

    csrci mstatus, (1 << 3)

__exit:
    j __exit

    .cfi_endproc

/* For sanity's sake we set up an early trap vector that just does nothing.  If
 * you end up here then there's a bug in the early boot code somewhere. */
.weak Trap_Handler_Stub
.section .text.metal.init.trapvec
.align 2
Trap_Handler_Stub:
    .cfi_startproc
    csrr t0, mcause
    csrr t1, mepc
    csrr t2, mtval
    j Trap_Handler_Stub
    .cfi_endproc

/* The GCC port might not emit a __register_frame_info symbol, which eventually
 * results in a weak undefined reference that eventually causes crash when it
 * is dereference early in boot.  We really shouldn't need to put this here,
 * but to deal with what I think is probably a bug in the linker script I'm
 * going to leave this in for now.  At least it's fairly cheap :) */
.weak __register_frame_info
.global __register_frame_info
.section .text.metal.init.__register_frame_info
__register_frame_info:
    .cfi_startproc
    ret
    .cfi_endproc


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/GCC/start_load.c
================================================
/**
 * @file start_load.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#include "bl702.h"
#include 

#define __STARTUP_CLEAR_BSS 1

/*----------------------------------------------------------------------------
  Linker generated Symbols
 *----------------------------------------------------------------------------*/
extern uint32_t __itcm_load_addr;
extern uint32_t __dtcm_load_addr;
extern uint32_t __system_ram_load_addr;
extern uint32_t __ram_load_addr;

extern uint32_t __text_code_start__;
extern uint32_t __text_code_end__;
extern uint32_t __tcm_code_start__;
extern uint32_t __tcm_code_end__;
extern uint32_t __tcm_data_start__;
extern uint32_t __tcm_data_end__;
extern uint32_t __system_ram_data_start__;
extern uint32_t __system_ram_data_end__;
extern uint32_t __ram_data_start__;
extern uint32_t __ram_data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __noinit_data_start__;
extern uint32_t __noinit_data_end__;

extern uint32_t __StackTop;
extern uint32_t __StackLimit;
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;

// extern uint32_t __copy_table_start__;
// extern uint32_t __copy_table_end__;
// extern uint32_t __zero_table_start__;
// extern uint32_t __zero_table_end__;

void start_load(void) {
  uint32_t *pSrc, *pDest;
  uint32_t *pTable __attribute__((unused));

  /* Copy ITCM code */
  pSrc  = &__itcm_load_addr;
  pDest = &__tcm_code_start__;

  for (; pDest < &__tcm_code_end__;) {
    *pDest++ = *pSrc++;
  }

  /* Copy DTCM code */
  pSrc  = &__dtcm_load_addr;
  pDest = &__tcm_data_start__;

  for (; pDest < &__tcm_data_end__;) {
    *pDest++ = *pSrc++;
  }

  /* BF Add system RAM data copy */
  pSrc  = &__system_ram_load_addr;
  pDest = &__system_ram_data_start__;

  for (; pDest < &__system_ram_data_end__;) {
    *pDest++ = *pSrc++;
  }

  /* BF Add OCARAM data copy */
  pSrc  = &__ram_load_addr;
  pDest = &__ram_data_start__;

  for (; pDest < &__ram_data_end__;) {
    *pDest++ = *pSrc++;
  }

  // #ifdef __STARTUP_CLEAR_BSS
  /*  Single BSS section scheme.
   *
   *  The BSS section is specified by following symbols
   *    __bss_start__: start of the BSS section.
   *    __bss_end__: end of the BSS section.
   *
   *  Both addresses must be aligned to 4 bytes boundary.
   */
  pDest = &__bss_start__;

  for (; pDest < &__bss_end__;) {
    *pDest++ = 0ul;
  }

  // #endif
}

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/drv_mmheap.c
================================================
/**
 * @file drv_mmheap.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#include "drv_mmheap.h"

#define MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT 8
#define MEM_MANAGE_BITS_PER_BYTE          8
#define MEM_MANAGE_MEM_STRUCT_SIZE        mmheap_align_up(sizeof(struct heap_node), MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT)
#define MEM_MANAGE_MINUM_MEM_SIZE         (MEM_MANAGE_MEM_STRUCT_SIZE << 1)
#define MEM_MANAGE_ALLOCA_LABAL           ((size_t)((size_t)1 << (sizeof(size_t) * MEM_MANAGE_BITS_PER_BYTE - 1)))

static inline size_t mmheap_align_down(size_t data, size_t align_byte) { return data & ~(align_byte - 1); }

static inline size_t mmheap_align_up(size_t data, size_t align_byte) { return (data + align_byte - 1) & ~(align_byte - 1); }

static inline struct heap_node *mmheap_addr_sub(const void *addr) { return (struct heap_node *)((const uint8_t *)addr - MEM_MANAGE_MEM_STRUCT_SIZE); }

static inline void *mmheap_addr_add(const struct heap_node *mem_node) { return (void *)((const uint8_t *)mem_node + MEM_MANAGE_MEM_STRUCT_SIZE); }

/**
 * @brief mmheap_insert_node_to_freelist
 *
 * @param pRoot
 * @param pNode
 */
static inline void mmheap_insert_node_to_freelist(struct heap_info *pRoot, struct heap_node *pNode) {
  struct heap_node *pPriv_Node;
  struct heap_node *pNext_Node;
  /*Find the node with an address similar to pNode*/
  for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pNode; pPriv_Node = pPriv_Node->next_node) {
  }

  pNext_Node = pPriv_Node->next_node;
  /*Try to merge the pNode with the previous block*/
  if ((uint8_t *)mmheap_addr_add(pPriv_Node) + pPriv_Node->mem_size == (uint8_t *)pNode) {
    if (pPriv_Node != pRoot->pStart) { /*can merge if not start block*/
      pPriv_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNode->mem_size;
      pNode = pPriv_Node;
    } else {
      /*The latter is not merged if it is a Start block to avoid wasting memory*/
      pRoot->pStart->next_node = pNode;
    }
  } else {
    /*Insert directly into the free single-chain table when merging is not possible*/
    pPriv_Node->next_node = pNode;
  }
  /*Try to merge the pNode with the next block*/
  if ((uint8_t *)mmheap_addr_add(pNode) + pNode->mem_size == (uint8_t *)pNext_Node) {
    if (pNext_Node != pRoot->pEnd) {
      pNode->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size;
      pNode->next_node = pNext_Node->next_node;
    } else {
      pNode->next_node = pRoot->pEnd;
    }
  } else {
    /*Insert directly into the free single-chain table when merging is not possible*/
    pNode->next_node = pNext_Node;
  }
}

/**
 * @brief mmheap_get_state
 *
 * @param pRoot
 * @param pState
 */
void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState) {
  MMHEAP_ASSERT(pRoot->pStart != NULL);
  MMHEAP_ASSERT(pRoot->pEnd != NULL);
  pState->max_node_size = pRoot->pStart->next_node->mem_size;
  pState->min_node_size = pRoot->pStart->next_node->mem_size;
  pState->remain_size   = 0;
  pState->free_node_num = 0;
  MMHEAP_LOCK();
  for (struct heap_node *pNode = pRoot->pStart->next_node; pNode->next_node != NULL; pNode = pNode->next_node) {
    pState->remain_size += pNode->mem_size;
    pState->free_node_num++;
    if (pNode->mem_size > pState->max_node_size) {
      pState->max_node_size = pNode->mem_size;
    }
    if (pNode->mem_size < pState->min_node_size) {
      pState->min_node_size = pNode->mem_size;
    }
  }
  MMHEAP_UNLOCK();
}
/**
 * @brief mmheap_align_alloc
 *
 * @param pRoot
 * @param align_size
 * @param want_size
 * @return void*
 */
void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size) {
  void             *pReturn = NULL;
  struct heap_node *pPriv_Node, *pNow_Node;

  MMHEAP_ASSERT(pRoot->pStart != NULL);
  MMHEAP_ASSERT(pRoot->pEnd != NULL);

  if (want_size == 0) {
    return NULL;
  }

  if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) {
    MMHEAP_MALLOC_FAIL();
    return NULL;
  }

  if (align_size & (align_size - 1)) {
    MMHEAP_MALLOC_FAIL();
    return NULL;
  }

  MMHEAP_LOCK();
  if (want_size < MEM_MANAGE_MINUM_MEM_SIZE) {
    want_size = MEM_MANAGE_MINUM_MEM_SIZE;
  }
  if (align_size < MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT) {
    align_size = MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT;
  }

  want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);

  pPriv_Node = pRoot->pStart;
  pNow_Node  = pRoot->pStart->next_node;

  while (pNow_Node->next_node != NULL) {
    if (pNow_Node->mem_size >= want_size + MEM_MANAGE_MEM_STRUCT_SIZE) {
      size_t use_align_size;
      size_t new_size;
      pReturn        = (void *)mmheap_align_up((size_t)mmheap_addr_add(pNow_Node), align_size); /*Calculate the aligned address*/
      use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node);              /*Calculate the memory consumed by the alignment*/
      if (use_align_size != 0) {                                                                /*if Memory misalignment*/
        if (use_align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) {          /*The unaligned value is too small*/
          pReturn        = (void *)mmheap_align_up((size_t)mmheap_addr_add(pNow_Node) + MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE, align_size);
          use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node);
        }
        if (use_align_size <= pNow_Node->mem_size) {
          new_size = pNow_Node->mem_size - use_align_size; /*Calculate the remaining memory size by removing the memory consumed by alignment*/
          if (new_size >= want_size) {                     /*Meet the conditions for distribution*/
            struct heap_node *pNew_Node = mmheap_addr_sub(pReturn);
            pNow_Node->mem_size -= new_size + MEM_MANAGE_MEM_STRUCT_SIZE; /*Split Node*/
            pNew_Node->mem_size  = new_size;                              /*The new node is also not in the free chain and does not need to be discharged from the free chain*/
            pNew_Node->next_node = NULL;
            pNow_Node            = pNew_Node;
            break;
          }
        }
      } else { /*Memory is directly aligned*/
        pPriv_Node->next_node = pNow_Node->next_node;
        pNow_Node->next_node  = NULL;
        break;
      }
    }
    pPriv_Node = pNow_Node;
    pNow_Node  = pNow_Node->next_node;
  }

  if (pNow_Node == pRoot->pEnd) {
    MMHEAP_UNLOCK();
    MMHEAP_MALLOC_FAIL();
    return NULL;
  }

  if (pNow_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) {         /*Node memory is still available*/
    struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pNow_Node) + want_size); /*Calculate the address of the node that will be moved into the free chain table*/
    pNew_Node->mem_size         = pNow_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE;
    pNew_Node->next_node        = NULL;
    pNow_Node->mem_size         = want_size;
    mmheap_insert_node_to_freelist(pRoot, pNew_Node);
  }
  pNow_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;
  MMHEAP_UNLOCK();
  return pReturn;
}
/**
 * @brief mmheap_alloc
 *
 * @param pRoot
 * @param want_size
 * @return void*
 */
void *mmheap_alloc(struct heap_info *pRoot, size_t want_size) { return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); }
/**
 * @brief mmheap_realloc
 *
 * @param pRoot
 * @param src_addr
 * @param want_size
 * @return void*
 */
void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size) {
  void             *pReturn = NULL;
  struct heap_node *pNext_Node, *pPriv_Node;
  struct heap_node *pSrc_Node;
  MMHEAP_ASSERT(pRoot->pStart != NULL);
  MMHEAP_ASSERT(pRoot->pEnd != NULL);
  if (src_addr == NULL) {
    return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size);
  }
  if (want_size == 0) {
    mmheap_free(pRoot, src_addr);
    return NULL;
  }

  MMHEAP_LOCK();
  if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) {
    MMHEAP_UNLOCK();
    MMHEAP_MALLOC_FAIL();
    return NULL;
  }

  pSrc_Node = mmheap_addr_sub(src_addr);

  if ((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) {
    MMHEAP_UNLOCK();
    MMHEAP_ASSERT((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0);
    MMHEAP_MALLOC_FAIL();
    return NULL;
  }

  pSrc_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL;
  if (pSrc_Node->mem_size >= want_size) {
    pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;
    pReturn = src_addr;
    MMHEAP_UNLOCK();
    return pReturn;
  }
  /*Start looking in the free list for blocks similar to this block*/
  for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pSrc_Node; pPriv_Node = pPriv_Node->next_node) {
  }
  pNext_Node = pPriv_Node->next_node;

  if (pNext_Node != pRoot->pEnd && ((uint8_t *)src_addr + pSrc_Node->mem_size == (uint8_t *)pNext_Node) && (pSrc_Node->mem_size + pNext_Node->mem_size + MEM_MANAGE_MEM_STRUCT_SIZE >= want_size)) {
    /*Meet next node non-end, memory contiguous, enough memory left*/
    pReturn               = src_addr;
    pPriv_Node->next_node = pNext_Node->next_node;
    pSrc_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size;
    want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);
    if (pSrc_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Removing the remaining space allocated is enough to open new blocks*/
      struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pSrc_Node) + want_size);
      pNew_Node->next_node        = NULL;
      pNew_Node->mem_size         = pSrc_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE;
      pSrc_Node->mem_size         = want_size;
      mmheap_insert_node_to_freelist(pRoot, pNew_Node);
    }
    pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;
    MMHEAP_UNLOCK();
  } else {
    MMHEAP_UNLOCK();
    pReturn = mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size);
    if (pReturn == NULL) {
      pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;
      MMHEAP_MALLOC_FAIL();
      return NULL;
    }
    MMHEAP_LOCK();
    memcpy(pReturn, src_addr, pSrc_Node->mem_size);
    pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL;
    MMHEAP_UNLOCK();
    mmheap_free(pRoot, src_addr);
  }
  return pReturn;
}
/**
 * @brief
 *
 * @param pRoot
 * @param num
 * @param size
 * @return void*
 */
void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size) {
  void *pReturn = NULL;

  pReturn = (void *)mmheap_alloc(pRoot, size * num);

  if (pReturn) {
    memset(pReturn, 0, num * size);
  }

  return pReturn;
}
/**
 * @brief mmheap_free
 *
 * @param pRoot
 * @param addr
 */
void mmheap_free(struct heap_info *pRoot, void *addr) {
  struct heap_node *pFree_Node;
  MMHEAP_ASSERT(pRoot->pStart != NULL);
  MMHEAP_ASSERT(pRoot->pEnd != NULL);
  MMHEAP_LOCK();
  if (addr == NULL) {
    MMHEAP_UNLOCK();
    return;
  }
  pFree_Node = mmheap_addr_sub(addr);

  if ((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) {
    MMHEAP_UNLOCK();
    MMHEAP_ASSERT((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0);
    return;
  }

  if (pFree_Node->next_node != NULL) {
    MMHEAP_UNLOCK();
    MMHEAP_ASSERT(pFree_Node->next_node == NULL);
    return;
  }
  pFree_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL;
  mmheap_insert_node_to_freelist(pRoot, pFree_Node);
  MMHEAP_UNLOCK();
}
/**
 * @brief mmheap_init
 *
 * @param pRoot
 * @param pRegion
 */
void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRegion) {
  struct heap_node *align_addr;
  size_t            align_size;
  struct heap_node *pPriv_node = NULL;

  pRoot->total_size = 0;
  pRoot->pEnd       = NULL;
  pRoot->pStart     = NULL;

  for (; pRegion->addr != NULL; pRegion++) {
    align_addr = (struct heap_node *)mmheap_align_up((size_t)pRegion->addr, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); /*Calculate the aligned address*/
    if ((uint8_t *)align_addr > pRegion->mem_size + (uint8_t *)pRegion->addr) {                                 /*Alignment consumes more memory than the memory area*/
      continue;
    }
    align_size = pRegion->mem_size - ((uint8_t *)align_addr - (uint8_t *)pRegion->addr); /*Calculate the size of memory left after alignment*/
    if (align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) {           /*if Aligning the remaining memory is too small*/
      continue;
    }
    align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Find the size of the memory block after removing the table header*/
    align_addr->mem_size  = align_size;
    align_addr->next_node = NULL;
    if (pRoot->pStart == NULL) {
      pRoot->pStart = align_addr;                                                                               /*set current addr for start*/
      if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) {                               /*If the remaining blocks are large enough*/
        align_size -= MEM_MANAGE_MEM_STRUCT_SIZE;                                                               /*Remove the next block of table headers remaining memory size*/
        align_addr               = (struct heap_node *)((uint8_t *)pRoot->pStart + MEM_MANAGE_MEM_STRUCT_SIZE); // the next block addr
        align_addr->mem_size     = align_size;
        align_addr->next_node    = NULL;
        pRoot->pStart->mem_size  = 0;
        pRoot->pStart->next_node = align_addr;
        pRoot->total_size        = align_addr->mem_size;
      } else { /*The memory is too small, and the address of the current memory block is recorded as start*/
        pRoot->total_size       = 0;
        pRoot->pStart->mem_size = 0;
      }
    } else {
      pPriv_node->next_node = align_addr;
      pRoot->total_size += align_size;
    }
    pPriv_node = align_addr;
  }
  // At this point, pPriv_node is the last block, then place the end of the table at the end of the block, find the address to place the end block, end block is only convenient for traversal, so as
  // small as possible, assigned to MEM_MANAGE_MEM_STRUCT_SIZE
  align_addr = (struct heap_node *)mmheap_align_down((size_t)mmheap_addr_add(pPriv_node) + pPriv_node->mem_size - MEM_MANAGE_MEM_STRUCT_SIZE, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT);
  align_size = (uint8_t *)align_addr - (uint8_t *)mmheap_addr_add(pPriv_node); /*Find the remaining size of the previous block after the end block is allocated*/
  if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE) {
    pRoot->total_size -= pPriv_node->mem_size - align_size; /*Removing memory consumed by allocating end blocks*/
    pRoot->pEnd           = align_addr;                     /*Update the address at the end of the list*/
    pPriv_node->next_node = align_addr;
    pPriv_node->mem_size  = align_size;
    align_addr->next_node = NULL;
    align_addr->mem_size  = 0; /*The end block is not involved in memory allocation, so a direct 0 is sufficient*/
  } else {                     /*The last block is too small, directly as the end block*/
    pRoot->pEnd = pPriv_node;
    pRoot->total_size -= pPriv_node->mem_size;
  }
  MMHEAP_ASSERT(pRoot->pStart != NULL);
  MMHEAP_ASSERT(pRoot->pEnd != NULL);
}


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/drv_mmheap.h
================================================
/**
 * @file drv_mmheap.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef __DRV_MMHEAP_H
#define __DRV_MMHEAP_H

#include 
#include 
#include 

#ifndef MMHEAP_LOCK
#define MMHEAP_LOCK()
#endif

#ifndef MMHEAP_UNLOCK
#define MMHEAP_UNLOCK()
#endif

#ifndef MMHEAP_ASSERT
#define MMHEAP_ASSERT(A) \
    if (!(A))            \
    printf("mmheap malloc error:drv_mmheap,%d\r\n", __LINE__)

#endif

#ifndef MMHEAP_MALLOC_FAIL
#define MMHEAP_MALLOC_FAIL() printf("mmheap malloc fail:drv_mmheap,%d\r\n", __LINE__)
#endif

#ifdef __cplusplus
extern "C" {
#endif

struct heap_region {
    void *addr;
    size_t mem_size;
};

struct heap_node {
    struct heap_node *next_node;
    size_t mem_size;
};

struct heap_info {
    struct heap_node *pStart;
    struct heap_node *pEnd;
    size_t total_size;
};

struct heap_state {
    size_t remain_size;
    size_t free_node_num;
    size_t max_node_size;
    size_t min_node_size;
};

void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRigon);
/**
 * @brief Alloc start address aligned memory from the heap.
 * Alloc aligned address and specified size memory from the heap.
 *
 * @attention
 *
 * @param[in]   pRoot    heap info.
 * @param[in]   align_size   address align mask of the memory.
 * @param[in]   want_size    size of the memory.
 *
 * @return  the pointer to the allocated memory.
 */
void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size);
/**
 * @brief Alloc memory.
 * Allocate size bytes and returns a pointer to the allocated memory.
 *
 * @attention size should no bigger than MMHEAP_BLK_SIZE_MAX.
 *
 * @param[in]   pRoot    heap info.
 * @param[in]   want_size    size of the memory.
 *
 * @return  the pointer to the allocated memory.
 */
void *mmheap_alloc(struct heap_info *pRoot, size_t want_size);
/**
 * @brief Realloc memory from the heap.
 * Change the size of the memory block pointed to by ptr to size bytes.
 *
 * @attention
 * 
    
 * 
  •  if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size.
 * 
  •  if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr).
 * 

 *
 * @param[in]   pRoot    heap info.
 * @param[in]   src_addr     old pointer to the memory space.
 * @param[in]   want_size    new size of the memory space.
 *
 * @return  the new pointer to the allocated memory.
 */
void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size);
/**
 * @brief Cealloc memory from the heap.
 * Change the size of the memory block pointed to by ptr to size bytes.
 *
 * @attention
 * 
    
 * 
  •  if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size.
 * 
  •  if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr).
 * 

 *
 * @param[in]   pRoot    heap info.
 * @param[in]   num     size number.
 * @param[in]   size    new size of the memory space.
 *
 * @return  the new pointer to the allocated memory.
 */
void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size);
/**
 * @brief Free the memory.
 * Free the memory space pointed to by ptr, which must have been returned by a previous call to mmheap_alloc(), mmheap_aligned_alloc(), or mmheap_realloc().
 *
 * @attention
 *
 * @param[in]   pRoot    heap info.
 * @param[in]   addr     pointer to the memory.
 *
 * @return  None.
 */
void mmheap_free(struct heap_info *pRoot, void *addr);
/**
 * @brief get mmheap state
 *
 * @param pRoot heap info.
 * @param pState heap state
 */
void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState);
#ifdef __cplusplus
}
#endif

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/interrupt.c
================================================
/**
 * @file interrupt.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "bflb_platform.h"
#include "bl702_common.h"
#include "risc-v/Core/Include/clic.h"
#include "risc-v/Core/Include/riscv_encoding.h"

pFunc __Interrupt_Handlers[IRQn_LAST] = {0};

void Interrupt_Handler_Stub(void);

void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MJPEG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void CAM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void I2S_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void USB_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void EMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void KYS_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void QDEC0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void QDEC1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void QDEC2_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void TOUCH_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void M154_REQ_ENH_ACK_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void M154_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void M154_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));

const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
    0,                           /*         */
    0,                           /*         */
    0,                           /*         */
    clic_msip_handler_Wrapper,   /* 3       */
    0,                           /*         */
    0,                           /*         */
    0,                           /*         */
    clic_mtimer_handler_Wrapper, /* 7       */
    (pFunc)0x00000001,           /*         */
    0,                           /*         */
    (pFunc)0x00000102,
    /*         */                        // disable log as default
    clic_mext_handler_Wrapper,           /* 11      */
    clic_csoft_handler_Wrapper,          /* 12      */
    0,                                   /*         */
    0,                                   /*         */
    0,                                   /*         */
    BMX_ERR_IRQHandler_Wrapper,          /* 16 +  0 */
    BMX_TO_IRQHandler_Wrapper,           /* 16 +  1 */
    L1C_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  2 */
    L1C_BMX_TO_IRQHandler_Wrapper,       /* 16 +  3 */
    SEC_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  4 */
    RF_TOP_INT0_IRQHandler_Wrapper,      /* 16 +  5 */
    RF_TOP_INT1_IRQHandler_Wrapper,      /* 16 +  6 */
    0,                                   /* 16 +  7 */
    DMA_BMX_ERR_IRQHandler_Wrapper,      /* 16 +  8 */
    SEC_GMAC_IRQHandler_Wrapper,         /* 16 +  9 */
    SEC_CDET_IRQHandler_Wrapper,         /* 16 + 10 */
    SEC_PKA_IRQHandler_Wrapper,          /* 16 + 11 */
    SEC_TRNG_IRQHandler_Wrapper,         /* 16 + 12 */
    SEC_AES_IRQHandler_Wrapper,          /* 16 + 13 */
    SEC_SHA_IRQHandler_Wrapper,          /* 16 + 14 */
    DMA_ALL_IRQHandler_Wrapper,          /* 16 + 15 */
    MJPEG_IRQHandler_Wrapper,            /* 16 + 16 */
    CAM_IRQHandler_Wrapper,              /* 16 + 17 */
    I2S_IRQHandler_Wrapper,              /* 16 + 18 */
    IRTX_IRQHandler_Wrapper,             /* 16 + 19 */
    IRRX_IRQHandler_Wrapper,             /* 16 + 20 */
    USB_IRQHandler_Wrapper,              /* 16 + 21 */
    EMAC_IRQHandler_Wrapper,             /* 16 + 22 */
    SF_CTRL_IRQHandler_Wrapper,          /* 16 + 23 */
    0,                                   /* 16 + 24 */
    GPADC_DMA_IRQHandler_Wrapper,        /* 16 + 25 */
    EFUSE_IRQHandler_Wrapper,            /* 16 + 26 */
    SPI_IRQHandler_Wrapper,              /* 16 + 27 */
    0,                                   /* 16 + 28 */
    UART0_IRQHandler_Wrapper,            /* 16 + 29 */
    UART1_IRQHandler_Wrapper,            /* 16 + 30 */
    0,                                   /* 16 + 31 */
    I2C_IRQHandler_Wrapper,              /* 16 + 32 */
    0,                                   /* 16 + 33 */
    PWM_IRQHandler_Wrapper,              /* 16 + 34 */
    0,                                   /* 16 + 35 */
    TIMER_CH0_IRQHandler_Wrapper,        /* 16 + 36 */
    TIMER_CH1_IRQHandler_Wrapper,        /* 16 + 37 */
    TIMER_WDT_IRQHandler_Wrapper,        /* 16 + 38 */
    KYS_IRQHandler_Wrapper,              /* 16 + 39 */
    QDEC0_IRQHandler_Wrapper,            /* 16 + 40 */
    QDEC1_IRQHandler_Wrapper,            /* 16 + 41 */
    QDEC2_IRQHandler_Wrapper,            /* 16 + 42 */
    0,                                   /* 16 + 43 */
    GPIO_INT0_IRQHandler_Wrapper,        /* 16 + 44 */
    TOUCH_IRQHandler_Wrapper,            /* 16 + 45 */
    0,                                   /* 16 + 46 */
    M154_REQ_ENH_ACK_IRQHandler_Wrapper, /* 16 + 47 */
    M154_IRQHandler_Wrapper,             /* 16 + 48 */
    M154_AES_IRQHandler_Wrapper,         /* 16 + 49 */
    PDS_WAKEUP_IRQHandler_Wrapper,       /* 16 + 50 */
    HBN_OUT0_IRQHandler_Wrapper,         /* 16 + 51 */
    HBN_OUT1_IRQHandler_Wrapper,         /* 16 + 52 */
    BOR_IRQHandler_Wrapper,              /* 16 + 53 */
    WIFI_IRQHandler_Wrapper,             /* 16 + 54 */
    BZ_PHY_IRQHandler_Wrapper,           /* 16 + 55 */
    BLE_IRQHandler_Wrapper,              /* 16 + 56 */
    MAC_TXRX_TIMER_IRQHandler_Wrapper,   /* 16 + 57 */
    MAC_TXRX_MISC_IRQHandler_Wrapper,    /* 16 + 58 */
    MAC_RX_TRG_IRQHandler_Wrapper,       /* 16 + 59 */
    MAC_TX_TRG_IRQHandler_Wrapper,       /* 16 + 60 */
    MAC_GEN_IRQHandler_Wrapper,          /* 16 + 61 */
    MAC_PORT_TRG_IRQHandler_Wrapper,     /* 16 + 62 */
    WIFI_IPC_PUBLIC_IRQHandler_Wrapper,  /* 16 + 63 */
};

#include "riscv_encoding.h"
void vAssertCalled(void) {
  MSG((char *)"vAssertCalled\r\n");
  unsigned long epc;
  epc = get_pc();
  MSG("mepc:0x%08x\r\n", (uint32_t)epc);

  //   PWM_Channel_Disable(PWM_Channel);
  //   gpio_set_mode(PWM_Out_Pin, GPIO_INPUT_PD_MODE);

  while (1) {
  }
}

void Trap_Handler(void) {
  unsigned long cause;
  unsigned long epc;
  unsigned long tval;
  uint8_t       isecall = 0;

  MSG("Trap_Handler\r\n");

  cause = read_csr(mcause);
  MSG("mcause=%08x\r\n", (uint32_t)cause);
  epc = get_pc();
  MSG("mepc:%08x\r\n", (uint32_t)epc);
  tval = read_csr(mtval);
  MSG("mtval:%08x\r\n", (uint32_t)tval);

  cause = (cause & 0x3ff);

  switch (cause) {
  case 1:
    MSG("Instruction access fault\r\n");
    break;

  case 2:
    MSG("Illegal instruction\r\n");
    break;

  case 3:
    MSG("Breakpoint\r\n");
    break;

  case 4:
    MSG("Load address misaligned\r\n");
    break;

  case 5:
    MSG("Load access fault\r\n");
    break;

  case 6:
    MSG("Store/AMO address misaligned\r\n");
    break;

  case 7:
    MSG("Store/AMO access fault\r\n");
    break;

  case 8:
    MSG("Environment call from U-mode\r\n");
    epc += 4;
    write_csr(mepc, epc);
    break;

  case 11:
    MSG("Environment call from M-mode\r\n");
    epc += 4;
    write_csr(mepc, epc);
    isecall = 1;
    break;

  default:
    MSG("Cause num=%d\r\n", (uint32_t)cause);
    epc += 4;
    write_csr(mepc, epc);
    break;
  }

  if (!isecall) {
    while (1) {
    }
  }
}

void Interrupt_Handler(void) {
  pFunc             interruptFun;
  uint32_t          num    = 0;
  volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL;

  /* Store a few register values that might be useful when determining why this
  function was called. */
  __asm volatile("csrr %0, mepc" : "=r"(ulMEPC));
  __asm volatile("csrr %0, mcause" : "=r"(ulMCAUSE));

  if ((ulMCAUSE & 0x80000000) == 0) {
    /*Exception*/
    MSG("Exception should not be here\r\n");
  } else {
    num = ulMCAUSE & 0x3FF;

    if (num < IRQn_LAST) {
      interruptFun = __Interrupt_Handlers[num];

      if (NULL != interruptFun) {
        interruptFun();
      } else {
        MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num);

        if (num >= IRQ_NUM_BASE) {
          MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE);
        }

        while (1) {
        }
      }
    } else {
      MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num);
    }
  }
}

void handle_trap(void) {
#define MCAUSE_INT_MASK  0x80000000 // [31]=1 interrupt, else exception
#define MCAUSE_CODE_MASK 0x7FFFFFFF // low bits show code

  unsigned long mcause_value = read_csr(mcause);
  if (mcause_value & MCAUSE_INT_MASK) {
    // Branch to interrupt handler here
    Interrupt_Handler();
  } else {
    // Branch to exception handle
    Trap_Handler();
  }
}

void __IRQ_ALIGN64 Trap_Handler_Stub(void) { Trap_Handler(); }

void __IRQ Interrupt_Handler_Stub(void) { Interrupt_Handler(); }

void FreeRTOS_Interrupt_Handler(void) { Interrupt_Handler(); }

void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) {
  if (irq < IRQn_LAST) {
    __Interrupt_Handlers[irq] = interruptFun;
  }
}

void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) {}

void clic_enable_interrupt(uint32_t source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; }

void clic_disable_interrupt(uint32_t source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; }

void clic_clear_pending(uint32_t source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; }

void clic_set_pending(uint32_t source) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; }

void clic_set_intcfg(uint32_t source, uint32_t intcfg) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source) = intcfg; }

uint8_t clic_get_intcfg(uint32_t source) { return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source); }

void clic_set_cliccfg(uint32_t cfg) { *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG) = cfg; }

uint8_t clic_get_cliccfg(void) { return *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_CFG); }

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.c
================================================
/**
 * @file system_bl702.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#include "bl702.h"
#include "bl702_glb.h"
#include "bl702_hbn.h"
#include "risc-v/Core/Include/clic.h"

#ifdef BFLB_EFLASH_LOADER
#include "bl702_usb.h"
void USB_DoNothing_IRQHandler(void) {
  /* clear all USB int sts */
  USB_Clr_IntStatus(32);
}
#endif

/*----------------------------------------------------------------------------
  Define clocks
 *----------------------------------------------------------------------------*/
#define SYSTEM_CLOCK (32000000UL)

/*----------------------------------------------------------------------------
  Vector Table
 *----------------------------------------------------------------------------*/
#define VECT_TAB_OFFSET                                                                                                                                                                                \
  0x00 /*!< Vector Table base offset field.                                                                                                                                                            \
             This value must be a multiple of 0x200. */

/*----------------------------------------------------------------------------
  System initialization function
 *----------------------------------------------------------------------------*/

void system_bor_init(void) {
  HBN_BOR_CFG_Type borCfg = {0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */};
  HBN_Set_BOR_Cfg(&borCfg);
}

void SystemInit(void) {
  uint32_t *p;
  uint32_t  i               = 0;
  uint32_t  tmpVal          = 0;
  uint8_t   flashCfg        = 0;
  uint8_t   psramCfg        = 0;
  uint8_t   isInternalFlash = 0;
  uint8_t   isInternalPsram = 0;

  /* global IRQ disable */
  __disable_irq();

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal |= (1 << 8);      /*mask pds wakeup*/
  tmpVal |= (1 << 10);     /*mask rf done*/
  tmpVal |= (1 << 11);     /*mask pll done*/
  tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  /* GLB_Set_EM_Sel(GLB_EM_0KB); */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
  BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);

  /* Restore default setting*/
  /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  /* fix 57.6M */
  if (SystemCoreClockGet() == 57 * 6000 * 1000) {
    SystemCoreClockSet(57.6 * 1000 * 1000)
  }

  /* CLear all interrupt */
  p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);

  for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
    p[i] = 0;
  }

  p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);

  for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
    p[i] = 0;
  }

  /* SF io select from efuse value */
  tmpVal   = BL_RD_WORD(0x40007074);
  flashCfg = ((tmpVal >> 26) & 7);
  psramCfg = ((tmpVal >> 24) & 3);
  if (flashCfg == 1 || flashCfg == 2) {
    isInternalFlash = 1;
  } else {
    isInternalFlash = 0;
  }
  if (psramCfg == 1) {
    isInternalPsram = 1;
  } else {
    isInternalPsram = 0;
  }
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
  if (isInternalFlash == 1 && isInternalPsram == 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
  }
  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);

#ifdef BFLB_EFLASH_LOADER
  Interrupt_Handler_Register(USB_IRQn, USB_DoNothing_IRQHandler);
#endif
  /* init bor for all platform */
  system_bor_init();
  /* global IRQ enable */
  __enable_irq();
}

void System_Post_Init(void) {
  PDS_Trim_RC32M();
  HBN_Trim_RC32K();
}

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/startup/system_bl702.h
================================================
/**
 * @file system_bl702.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#ifndef __SYSTEM_BL702_H__
#define __SYSTEM_BL702_H__

/**
 *  @brief PLL Clock type definition
 */

extern uint32_t SystemCoreClock;
typedef void (*pFunc)(void);

#define CPU_Interrupt_Enable        clic_enable_interrupt
#define CPU_Interrupt_Disable       clic_disable_interrupt
#define CPU_Interrupt_Pending_Clear clic_clear_pending

extern void SystemCoreClockUpdate(void);
extern void SystemInit(void);
void clic_enable_interrupt(uint32_t source);
void clic_disable_interrupt(uint32_t source);
void clic_clear_pending(uint32_t source);
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_acomp.h
================================================
/**
  ******************************************************************************
  * @file    bl702_acomp.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_ACOMP_H__
#define __BL702_ACOMP_H__

#include "aon_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  ACOMP
 *  @{
 */

/** @defgroup  ACOMP_Public_Types
 *  @{
 */

/**
 *  @brief Analog compare id type definition
 */
typedef enum {
    AON_ACOMP0_ID, /*!< Analog compare 0 */
    AON_ACOMP1_ID, /*!< Analog compare 1 */
} AON_ACOMP_ID_Type;

/**
 *  @brief Analog compare level type definition
 */
typedef enum {
    AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */
    AON_ACOMP_LEVEL_FACTOR_0P5,  /*!< Analog compare level scaling factor 0.5 */
    AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */
    AON_ACOMP_LEVEL_FACTOR_1,    /*!< Analog compare level scaling factor 1 */
} AON_ACOMP_Level_Factor_Type;

/**
 *  @brief Analog compare channel type definition
 */
typedef enum {
    AON_ACOMP_CHAN_ADC0,              /*!< Analog compare channel,ADC input channel 0 */
    AON_ACOMP_CHAN_ADC1,              /*!< Analog compare channel,ADC input channel 1 */
    AON_ACOMP_CHAN_ADC2,              /*!< Analog compare channel,ADC input channel 2 */
    AON_ACOMP_CHAN_ADC3,              /*!< Analog compare channel,ADC input channel 3 */
    AON_ACOMP_CHAN_ADC4,              /*!< Analog compare channel,ADC input channel 4 */
    AON_ACOMP_CHAN_ADC5,              /*!< Analog compare channel,ADC input channel 5 */
    AON_ACOMP_CHAN_ADC6,              /*!< Analog compare channel,ADC input channel 6 */
    AON_ACOMP_CHAN_ADC7,              /*!< Analog compare channel,ADC input channel 7 */
    AON_ACOMP_CHAN_DACA,              /*!< Analog compare channel,DAC output channel A */
    AON_ACOMP_CHAN_DACB,              /*!< Analog compare channel,DAC output channel B */
    AON_ACOMP_CHAN_VREF_1P2V,         /*!< Analog compare channel,1.2V ref voltage */
    AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */
    AON_ACOMP_CHAN_0P25VBAT,          /*!< Analog compare channel,4/16Vbat */
    AON_ACOMP_CHAN_0P1875VBAT,        /*!< Analog compare channel,3/16Vbat */
    AON_ACOMP_CHAN_0P3125VBAT,        /*!< Analog compare channel,5/16Vbat */
    AON_ACOMP_CHAN_VSS,               /*!< Analog compare channel,vss */
} AON_ACOMP_Chan_Type;

/**
 *  @brief Analog compare bias current control type definition
 */
typedef enum {
    AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */
    AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */
    AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */
    AON_ACOMP_BIAS_POWER_NONE,  /*!< Analog compare power mode none */
} AON_ACOMP_Bias_Prog_Type;

/**
 *  @brief Analog compare hysteresis voltage type definition
 */
typedef enum {
    AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */
    AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */
    AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */
    AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */
    AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */
    AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */
    AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */
    AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */
} AON_ACOMP_Hysteresis_Volt_Type;

/**
 *  @brief AON ACOMP configuration type definition
 */
typedef struct
{
    BL_Fun_Type muxEn;                                /*!< ACOMP mux enable */
    uint8_t posChanSel;                               /*!< ACOMP positive channel select */
    uint8_t negChanSel;                               /*!< ACOMP negtive channel select */
    AON_ACOMP_Level_Factor_Type levelFactor;          /*!< ACOMP level select factor */
    AON_ACOMP_Bias_Prog_Type biasProg;                /*!< ACOMP bias current control */
    AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */
    AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */
} AON_ACOMP_CFG_Type;

/*@} end of group ACOMP_Public_Types */

/** @defgroup  ACOMP_Public_Constants
 *  @{
 */

/** @defgroup  AON_ACOMP_ID_TYPE
 *  @{
 */
#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \
                                    ((type) == AON_ACOMP1_ID))

/** @defgroup  AON_ACOMP_LEVEL_FACTOR_TYPE
 *  @{
 */
#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \
                                              ((type) == AON_ACOMP_LEVEL_FACTOR_0P5) ||  \
                                              ((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \
                                              ((type) == AON_ACOMP_LEVEL_FACTOR_1))

/** @defgroup  AON_ACOMP_CHAN_TYPE
 *  @{
 */
#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC1) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC2) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC3) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC4) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC5) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC6) ||              \
                                      ((type) == AON_ACOMP_CHAN_ADC7) ||              \
                                      ((type) == AON_ACOMP_CHAN_DACA) ||              \
                                      ((type) == AON_ACOMP_CHAN_DACB) ||              \
                                      ((type) == AON_ACOMP_CHAN_VREF_1P2V) ||         \
                                      ((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \
                                      ((type) == AON_ACOMP_CHAN_0P25VBAT) ||          \
                                      ((type) == AON_ACOMP_CHAN_0P1875VBAT) ||        \
                                      ((type) == AON_ACOMP_CHAN_0P3125VBAT) ||        \
                                      ((type) == AON_ACOMP_CHAN_VSS))

/** @defgroup  AON_ACOMP_BIAS_PROG_TYPE
 *  @{
 */
#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \
                                           ((type) == AON_ACOMP_BIAS_POWER_MODE2) || \
                                           ((type) == AON_ACOMP_BIAS_POWER_MODE3) || \
                                           ((type) == AON_ACOMP_BIAS_POWER_NONE))

/** @defgroup  AON_ACOMP_HYSTERESIS_VOLT_TYPE
 *  @{
 */
#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \
                                                 ((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV))

/*@} end of group ACOMP_Public_Constants */

/** @defgroup  ACOMP_Public_Macros
 *  @{
 */

/*@} end of group ACOMP_Public_Macros */

/** @defgroup  ACOMP_Public_Functions
 *  @{
 */
void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg);
void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo);
BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo);

/*@} end of group ACOMP_Public_Functions */

/*@} end of group ACOMP */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_ACOMP_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_adc.h
================================================
/**
 ******************************************************************************
 * @file    bl702_adc.h
 * @version V1.0
 * @date
 * @brief   This file is the standard driver header file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#ifndef __BL702_ADC_H__
#define __BL702_ADC_H__

#include "aon_reg.h"
#include "bl702_common.h"
#include "gpip_reg.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  ADC
 *  @{
 */

/** @defgroup  ADC_Public_Types
 *  @{
 */

/**
 *  @brief ADC channel type definition
 */
typedef enum {
  ADC_CHAN0,          /*!< ADC channel 0 */
  ADC_CHAN1,          /*!< ADC channel 1 */
  ADC_CHAN2,          /*!< ADC channel 2 */
  ADC_CHAN3,          /*!< ADC channel 3 */
  ADC_CHAN4,          /*!< ADC channel 4 */
  ADC_CHAN5,          /*!< ADC channel 5 */
  ADC_CHAN6,          /*!< ADC channel 6 */
  ADC_CHAN7,          /*!< ADC channel 7 */
  ADC_CHAN8,          /*!< ADC channel 8 */
  ADC_CHAN9,          /*!< ADC channel 9 */
  ADC_CHAN10,         /*!< ADC channel 10 */
  ADC_CHAN11,         /*!< ADC channel 11 */
  ADC_CHAN_DAC_OUTA,  /*!< DACA, ADC channel 12 */
  ADC_CHAN_DAC_OUTB,  /*!< DACB, ADC channel 13 */
  ADC_CHAN_TSEN_P,    /*!< TSenp, ADC channel 14 */
  ADC_CHAN_TSEN_N,    /*!< TSenn, ADC channel 15 */
  ADC_CHAN_VREF,      /*!< Vref, ADC channel 16 */
  ADC_CHAN_DCTEST,    /*!< DCTest, ADC channel 17 */
  ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */
  ADC_CHAN_SENP3,     /*!< SenVP3, ADC channel 19 */
  ADC_CHAN_SENP2,     /*!< SenVP2, ADC channel 20 */
  ADC_CHAN_SENP1,     /*!< SenVP1, ADC channel 21 */
  ADC_CHAN_SENP0,     /*!< SenVP0, ADC channel 22 */
  ADC_CHAN_GND,       /*!< GND, ADC channel 23 */
} ADC_Chan_Type;

/**
 *  @brief ADC V18 selection type definition
 */
typedef enum {
  ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */
  ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */
  ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */
  ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */
} ADC_V18_SEL_Type;

/**
 *  @brief ADC V11 selection type definition
 */
typedef enum {
  ADC_V11_SEL_1P0V,  /*!< V11 select 1.0V */
  ADC_V11_SEL_1P1V,  /*!< V11 select 1.1V */
  ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */
  ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */
} ADC_V11_SEL_Type;

/**
 *  @brief ADC clock type definition
 */
typedef enum {
  ADC_CLK_DIV_1,  /*!< ADC clock:on 32M clock is 32M */
  ADC_CLK_DIV_4,  /*!< ADC clock:on 32M clock is 8M */
  ADC_CLK_DIV_8,  /*!< ADC clock:on 32M clock is 4M */
  ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
  ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
  ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
  ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
  ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
} ADC_CLK_Type;

/**
 *  @brief ADC conversion speed type definition
 */
typedef enum {
  ADC_DELAY_SEL_0, /*!< Select delay 0 */
  ADC_DELAY_SEL_1, /*!< Select delay 1 */
  ADC_DELAY_SEL_2, /*!< Select delay 2 */
  ADC_DELAY_SEL_3, /*!< Select delay 3 */
  ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */
  ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */
  ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */
  ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */
} ADC_DELAY_SEL_Type;

/**
 *  @brief ADC PGA gain type definition
 */
typedef enum {
  ADC_PGA_GAIN_NONE, /*!< No PGA gain */
  ADC_PGA_GAIN_1,    /*!< PGA gain 1 */
  ADC_PGA_GAIN_2,    /*!< PGA gain 2 */
  ADC_PGA_GAIN_4,    /*!< PGA gain 4 */
  ADC_PGA_GAIN_8,    /*!< PGA gain 8 */
  ADC_PGA_GAIN_16,   /*!< PGA gain 16 */
  ADC_PGA_GAIN_32,   /*!< PGA gain 32 */
} ADC_PGA_GAIN_Type;

/**
 *  @brief ADC analog portion low power mode selection type definition
 */
typedef enum {
  ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */
  ADC_BIAS_SEL_AON_BANDGAP,  /*!< ADC current from aon bandgap for HBN mode */
} ADC_BIAS_SEL_Type;

/**
 *  @brief ADC chop mode type definition
 */
typedef enum {
  ADC_CHOP_MOD_ALL_OFF,       /*!< all off */
  ADC_CHOP_MOD_AZ_ON,         /*!< Vref AZ on */
  ADC_CHOP_MOD_AZ_PGA_ON,     /*!< Vref AZ and PGA chop on */
  ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */
} ADC_CHOP_MOD_Type;

/**
 *  @brief ADC audio PGA output common mode control type definition
 */
typedef enum {
  ADC_PGA_VCM_1V,   /*!< ADC VCM=1V */
  ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */
  ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */
  ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */
} ADC_PGA_VCM_Type;

/**
 *  @brief ADC tsen diode mode type definition
 */
typedef enum {
  ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */
  ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */
} ADC_TSEN_MOD_Type;

/**
 *  @brief ADC voltage reference type definition
 */
typedef enum {
  ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */
  ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */
} ADC_VREF_Type;

/**
 *  @brief ADC signal input type definition
 */
typedef enum {
  ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */
  ADC_INPUT_DIFF,       /*!< ADC signal is differential */
} ADC_SIG_INPUT_Type;

/**
 *  @brief ADC data width type definition
 */
typedef enum {
  ADC_DATA_WIDTH_12,                  /*!< ADC 12 bits */
  ADC_DATA_WIDTH_14_WITH_16_AVERAGE,  /*!< ADC 14 bits,and the value is average of 16 converts */
  ADC_DATA_WIDTH_14_WITH_64_AVERAGE,  /*!< ADC 14 bits,and the value is average of 64 converts */
  ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
  ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
} ADC_Data_Width_Type;

/**
 *  @brief ADC micboost 32db type definition
 */
typedef enum {
  ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */
  ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */
} ADC_MICBOOST_DB_Type;

/**
 *  @brief ADC pga2 gain type definition
 */
typedef enum {
  ADC_PGA2_GAIN_0DB,  /*!< MIC pga2 gain 0db */
  ADC_PGA2_GAIN_6DB,  /*!< MIC pga2 gain 6db */
  ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */
  ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */
} ADC_PGA2_GAIN_Type;

/**
 *  @brief ADC mic mode type definition
 */
typedef enum {
  ADC_MIC_MODE_SINGLE, /*!< MIC single mode */
  ADC_MIC_MODE_DIFF,   /*!< MIC diff mode */
} ADC_MIC_MODE_Type;

/**
 *  @brief ADC mic type definition
 */
typedef struct {
  ADC_MICBOOST_DB_Type micboostDb;       /*!< MIC boost db */
  ADC_PGA2_GAIN_Type   micPga2Gain;      /*!< MIC pga2 gain */
  ADC_MIC_MODE_Type    mic1Mode;         /*!< MIC1 single or diff */
  ADC_MIC_MODE_Type    mic2Mode;         /*!< MIC2 single or diff */
  BL_Fun_Type          dwaEn;            /*!< Improve dynamic performance */
  BL_Fun_Type          micboostBypassEn; /*!< MIC boost amp bypass enable or disable */
  BL_Fun_Type          micPgaEn;         /*!< MIC pga enable or disable */
  BL_Fun_Type          micBiasEn;        /*!< MIC bias enable or disable */
} ADC_MIC_Type;

/**
 *  @brief ADC configuration type definition
 */
typedef struct {
  ADC_V18_SEL_Type    v18Sel;         /*!< ADC 1.8V select */
  ADC_V11_SEL_Type    v11Sel;         /*!< ADC 1.1V select */
  ADC_CLK_Type        clkDiv;         /*!< Clock divider */
  ADC_PGA_GAIN_Type   gain1;          /*!< PGA gain 1 */
  ADC_PGA_GAIN_Type   gain2;          /*!< PGA gain 2 */
  ADC_CHOP_MOD_Type   chopMode;       /*!< ADC chop mode select */
  ADC_BIAS_SEL_Type   biasSel;        /*!< ADC current form main bandgap or aon bandgap */
  ADC_PGA_VCM_Type    vcm;            /*!< ADC VCM value */
  ADC_VREF_Type       vref;           /*!< ADC voltage reference */
  ADC_SIG_INPUT_Type  inputMode;      /*!< ADC input signal type */
  ADC_Data_Width_Type resWidth;       /*!< ADC resolution and oversample rate */
  BL_Fun_Type         offsetCalibEn;  /*!< Offset calibration enable */
  int16_t             offsetCalibVal; /*!< Offset calibration value */
} ADC_CFG_Type;

/**
 *  @brief ADC configuration type definition
 */
typedef struct {
  int8_t   posChan; /*!< Positive channel */
  int8_t   negChan; /*!< Negative channel */
  uint32_t value;   /*!< ADC value */
  // float    volt;    /*!< ADC voltage result */
} ADC_Result_Type;

/**
 *  @brief ADC FIFO threshold type definition
 */
typedef enum {
  ADC_FIFO_THRESHOLD_1,  /*!< ADC FIFO threshold is 1 */
  ADC_FIFO_THRESHOLD_4,  /*!< ADC FIFO threshold is 4 */
  ADC_FIFO_THRESHOLD_8,  /*!< ADC FIFO threshold is 8 */
  ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */
} ADC_FIFO_Threshold_Type;

/**
 *  @brief ADC interrupt type definition
 */
typedef enum {
  ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */
  ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */
  ADC_INT_FIFO_UNDERRUN,  /*!< ADC FIFO underrun interrupt */
  ADC_INT_FIFO_OVERRUN,   /*!< ADC FIFO overrun interrupt */
  ADC_INT_ADC_READY,      /*!< ADC data ready interrupt */
  ADC_INT_FIFO_READY,     /*!< ADC FIFO count upper to threhold interrupt */
  ADC_INT_ALL,            /*!< ADC all the interrupt */
} ADC_INT_Type;

/**
 *  @brief ADC FIFO configuration structure type definition
 */
typedef struct {
  ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */
  BL_Fun_Type             dmaEn;         /*!< ADC DMA enable */
} ADC_FIFO_Cfg_Type;

/**
 *  @brief ADC REG GAIN CAL
 */
typedef struct {
  BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */
  uint16_t    adcgainCoeffVal;    /*!< ADC_Gain_Coeff value */
  float       coe;                /*!< ADC_Gain_Coeff result */
} ADC_Gain_Coeff_Type;

/*@} end of group ADC_Public_Types */

/** @defgroup  ADC_Public_Constants
 *  @{
 */

/** @defgroup  ADC_CHAN_TYPE
 *  @{
 */
#define IS_ADC_CHAN_TYPE(type)                                                                                                                                                                         \
  (((type) == ADC_CHAN0) || ((type) == ADC_CHAN1) || ((type) == ADC_CHAN2) || ((type) == ADC_CHAN3) || ((type) == ADC_CHAN4) || ((type) == ADC_CHAN5) || ((type) == ADC_CHAN6) ||                      \
   ((type) == ADC_CHAN7) || ((type) == ADC_CHAN8) || ((type) == ADC_CHAN9) || ((type) == ADC_CHAN10) || ((type) == ADC_CHAN11) || ((type) == ADC_CHAN_DAC_OUTA) || ((type) == ADC_CHAN_DAC_OUTB) ||    \
   ((type) == ADC_CHAN_TSEN_P) || ((type) == ADC_CHAN_TSEN_N) || ((type) == ADC_CHAN_VREF) || ((type) == ADC_CHAN_DCTEST) || ((type) == ADC_CHAN_VABT_HALF) || ((type) == ADC_CHAN_SENP3) ||           \
   ((type) == ADC_CHAN_SENP2) || ((type) == ADC_CHAN_SENP1) || ((type) == ADC_CHAN_SENP0) || ((type) == ADC_CHAN_GND))

/** @defgroup  ADC_V18_SEL_TYPE
 *  @{
 */
#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || ((type) == ADC_V18_SEL_1P72V) || ((type) == ADC_V18_SEL_1P82V) || ((type) == ADC_V18_SEL_1P92V))

/** @defgroup  ADC_V11_SEL_TYPE
 *  @{
 */
#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || ((type) == ADC_V11_SEL_1P1V) || ((type) == ADC_V11_SEL_1P18V) || ((type) == ADC_V11_SEL_1P26V))

/** @defgroup  ADC_CLK_TYPE
 *  @{
 */
#define IS_ADC_CLK_TYPE(type)                                                                                                                                                                          \
  (((type) == ADC_CLK_DIV_1) || ((type) == ADC_CLK_DIV_4) || ((type) == ADC_CLK_DIV_8) || ((type) == ADC_CLK_DIV_12) || ((type) == ADC_CLK_DIV_16) || ((type) == ADC_CLK_DIV_20) ||                    \
   ((type) == ADC_CLK_DIV_24) || ((type) == ADC_CLK_DIV_32))

/** @defgroup  ADC_DELAY_SEL_TYPE
 *  @{
 */
#define IS_ADC_DELAY_SEL_TYPE(type)                                                                                                                                                                    \
  (((type) == ADC_DELAY_SEL_0) || ((type) == ADC_DELAY_SEL_1) || ((type) == ADC_DELAY_SEL_2) || ((type) == ADC_DELAY_SEL_3) || ((type) == ADC_DELAY_SEL_4) || ((type) == ADC_DELAY_SEL_5) ||           \
   ((type) == ADC_DELAY_SEL_6) || ((type) == ADC_DELAY_SEL_7))

/** @defgroup  ADC_PGA_GAIN_TYPE
 *  @{
 */
#define IS_ADC_PGA_GAIN_TYPE(type)                                                                                                                                                                     \
  (((type) == ADC_PGA_GAIN_NONE) || ((type) == ADC_PGA_GAIN_1) || ((type) == ADC_PGA_GAIN_2) || ((type) == ADC_PGA_GAIN_4) || ((type) == ADC_PGA_GAIN_8) || ((type) == ADC_PGA_GAIN_16) ||             \
   ((type) == ADC_PGA_GAIN_32))

/** @defgroup  ADC_BIAS_SEL_TYPE
 *  @{
 */
#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || ((type) == ADC_BIAS_SEL_AON_BANDGAP))

/** @defgroup  ADC_CHOP_MOD_TYPE
 *  @{
 */
#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || ((type) == ADC_CHOP_MOD_AZ_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON))

/** @defgroup  ADC_PGA_VCM_TYPE
 *  @{
 */
#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || ((type) == ADC_PGA_VCM_1P2V) || ((type) == ADC_PGA_VCM_1P4V) || ((type) == ADC_PGA_VCM_1P6V))

/** @defgroup  ADC_TSEN_MOD_TYPE
 *  @{
 */
#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE))

/** @defgroup  ADC_VREF_TYPE
 *  @{
 */
#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || ((type) == ADC_VREF_2V))

/** @defgroup  ADC_SIG_INPUT_TYPE
 *  @{
 */
#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || ((type) == ADC_INPUT_DIFF))

/** @defgroup  ADC_DATA_WIDTH_TYPE
 *  @{
 */
#define IS_ADC_DATA_WIDTH_TYPE(type)                                                                                                                                                                   \
  (((type) == ADC_DATA_WIDTH_12) || ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) ||                \
   ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE))

/** @defgroup  ADC_MICBOOST_DB_TYPE
 *  @{
 */
#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || ((type) == ADC_MICBOOST_DB_32DB))

/** @defgroup  ADC_PGA2_GAIN_TYPE
 *  @{
 */
#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || ((type) == ADC_PGA2_GAIN_6DB) || ((type) == ADC_PGA2_GAIN_N6DB) || ((type) == ADC_PGA2_GAIN_12DB))

/** @defgroup  ADC_MIC_MODE_TYPE
 *  @{
 */
#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || ((type) == ADC_MIC_MODE_DIFF))

/** @defgroup  ADC_FIFO_THRESHOLD_TYPE
 *  @{
 */
#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || ((type) == ADC_FIFO_THRESHOLD_4) || ((type) == ADC_FIFO_THRESHOLD_8) || ((type) == ADC_FIFO_THRESHOLD_16))

/** @defgroup  ADC_INT_TYPE
 *  @{
 */
#define IS_ADC_INT_TYPE(type)                                                                                                                                                                          \
  (((type) == ADC_INT_POS_SATURATION) || ((type) == ADC_INT_NEG_SATURATION) || ((type) == ADC_INT_FIFO_UNDERRUN) || ((type) == ADC_INT_FIFO_OVERRUN) || ((type) == ADC_INT_ADC_READY) ||               \
   ((type) == ADC_INT_FIFO_READY) || ((type) == ADC_INT_ALL))

/*@} end of group ADC_Public_Constants */

/** @defgroup  ADC_Public_Macros
 *  @{
 */

/*@} end of group ADC_Public_Macros */

/** @defgroup  ADC_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void GPADC_DMA_IRQHandler(void);
#endif
void         ADC_Vbat_Enable(void);
void         ADC_Vbat_Disable(void);
void         ADC_Reset(void);
void         ADC_Enable(void);
void         ADC_Disable(void);
void         ADC_Init(ADC_CFG_Type *cfg);
void         ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn);
void         ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn);
void         ADC_Start(void);
void         ADC_Stop(void);
void         ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg);
uint8_t      ADC_Get_FIFO_Count(void);
BL_Sts_Type  ADC_FIFO_Is_Empty(void);
BL_Sts_Type  ADC_FIFO_Is_Full(void);
void         ADC_FIFO_Clear(void);
uint32_t     ADC_Read_FIFO(void);
void         ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result);
void         ADC_IntClr(ADC_INT_Type intType);
BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType);
BL_Sts_Type  ADC_GetIntStatus(ADC_INT_Type intType);
void         ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun);
void         ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);
void         ADC_SET_TSVBE_LOW(void);
void         ADC_SET_TSVBE_HIGH(void);
void         ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod);
void         ADC_Tsen_Enable(void);
void         ADC_Tsen_Disable(void);
void         ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal);
BL_Err_Type  ADC_Mic_Init(ADC_MIC_Type *adc_mic_config);
void         ADC_MIC_Bias_Disable(void);
void         ADC_MIC_Bias_Enable(void);
BL_Err_Type  ADC_Trim_TSEN(uint16_t *tsen_offset);
BL_Err_Type  ADC_Gain_Trim(void);
uint32_t     ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg);
float        TSEN_Get_Temp(uint32_t tsen_offset);

/*@} end of group ADC_Public_Functions */

/*@} end of group ADC */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_ADC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_aon.h
================================================
/**
  ******************************************************************************
  * @file    bl702_aon.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_AON_H__
#define __BL702_AON_H__

#include "aon_reg.h"
#include "glb_reg.h"
#include "hbn_reg.h"
#include "pds_reg.h"
#include "bl702_ef_ctrl.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  AON
 *  @{
 */

/** @defgroup  AON_Public_Types
 *  @{
 */

/*@} end of group AON_Public_Types */

/** @defgroup  AON_Public_Constants
 *  @{
 */

/*@} end of group AON_Public_Constants */

/** @defgroup  AON_Public_Macros
 *  @{
 */

/*@} end of group AON_Public_Macros */

/** @defgroup  AON_Public_Functions
 *  @{
 */
/*----------*/
BL_Err_Type AON_Power_On_MBG(void);
BL_Err_Type AON_Power_Off_MBG(void);
/*----------*/
BL_Err_Type AON_Power_On_XTAL(void);
BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
uint8_t AON_Get_Xtal_CapCode(void);
BL_Err_Type AON_Set_Xtal_CapCode_Extra(uint8_t extra);
BL_Err_Type AON_Power_Off_XTAL(void);
/*----------*/
BL_Err_Type AON_Power_On_BG(void);
BL_Err_Type AON_Power_Off_BG(void);
/*----------*/
BL_Err_Type AON_Power_On_LDO11_SOC(void);
BL_Err_Type AON_Power_Off_LDO11_SOC(void);
/*----------*/
BL_Err_Type AON_Power_On_LDO15_RF(void);
BL_Err_Type AON_Power_Off_LDO15_RF(void);
/*----------*/
BL_Err_Type AON_Power_On_SFReg(void);
BL_Err_Type AON_Power_Off_SFReg(void);
/*----------*/
BL_Err_Type AON_LowPower_Enter_PDS0(void);
BL_Err_Type AON_LowPower_Exit_PDS0(void);
/*----------*/
BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay);
/*----------*/
BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm);
BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup);
/*----------*/

/*@} end of group AON_Public_Functions */

/*@} end of group AON */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_AON_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_cam.h
================================================
/**
  ******************************************************************************
  * @file    bl702_cam.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_CAM_H__
#define __BL702_CAM_H__

#include "cam_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  CAM
 *  @{
 */

/** @defgroup  CAM_Public_Types
 *  @{
 */

/**
 *  @brief CAM AHB burst type definition
 */
typedef enum {
    CAM_BURST_TYPE_SINGLE, /*!< Camera AHB burst type:single */
    CAM_BURST_TYPE_INCR4,  /*!< Camera AHB burst type:incrementing 4 */
    CAM_BURST_TYPE_INCR8,  /*!< Camera AHB burst type:incrementing 8 */
    CAM_BURST_TYPE_INCR16, /*!< Camera AHB burst type:incrementing 16 */
} CAM_Burst_Type;

/**
 *  @brief CAM software mode type definition
 */
typedef enum {
    CAM_SW_MODE_AUTO,   /*!< CAM auto mode with mjpeg */
    CAM_SW_MODE_MANUAL, /*!< CAM manual mode(software mode) */
} CAM_SW_Mode_Type;

/**
 *  @brief CAM frame mode type definition
 */
typedef enum {
    CAM_PLANAR_MODE,     /*!< CAM planar mode(YYYY.../UVUV...) */
    CAM_INTERLEAVE_MODE, /*!< CAM interleave mode(YUYVYUYV...) */
} CAM_Frame_Mode_Type;

/**
 *  @brief CAM YUV mode type definition
 */
typedef enum {
    CAM_YUV422,      /*!< CAM YUV422 mode */
    CAM_YUV420_EVEN, /*!< CAM YUV420 mode(raw data:YUYV YUYV..., processed data:YUYV YY...) which dropped odd pix data in
                                                 odd rows */
    CAM_YUV420_ODD,  /*!< CAM YUV420 mode(raw data:UYVY UYVY..., processed data:UYVY YY...) which dropped even pix data
                                                 in odd rows */
    CAM_YUV400_EVEN, /*!< CAM YUV400 mode(raw data:YUYV YUYV..., processed data:YY YY...) which dropped odd pix data */
    CAM_YUV400_ODD,  /*!< CAM YUV400 mode(raw data:UYVY UYVY..., processed data:YY YY...) which dropped even pix data */
} CAM_YUV_Mode_Type;

/**
 *  @brief CAM line active polarity type definition
 */
typedef enum {
    CAM_LINE_ACTIVE_POLARITY_LOW,  /*!< CAM line active polarity low */
    CAM_LINE_ACTIVE_POLARITY_HIGH, /*!< CAM line active polarity high */
} CAM_Line_Active_Pol;

/**
 *  @brief CAM frame active polarity type definition
 */
typedef enum {
    CAM_FRAME_ACTIVE_POLARITY_LOW,  /*!< CAM frame active polarity low */
    CAM_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAM frame active polarity high */
} CAM_Frame_Active_Pol;

/**
 *  @brief CAM sensor mode type definition
 */
typedef enum {
    CAM_SENSOR_MODE_V_AND_H, /*!< CAM sensor type v and h */
    CAM_SENSOR_MODE_V_OR_H,  /*!< CAM sensor type v  or h */
    CAM_SENSOR_MODE_V,       /*!< CAM sensor type v */
    CAM_SENSOR_MODE_H,       /*!< CAM sensor type h */
} CAM_Sensor_Mode_Type;

/**
 *  @brief CAM interrupt type definition
 */
typedef enum {
    CAM_INT_NORMAL_0,           /*!< Interleave mode: normal write interrupt,     planar mode:even byte normal write interrupt */
    CAM_INT_NORMAL_1,           /*!< Interleave mode: no use,                     planar mode:odd byte normal write interrupt */
    CAM_INT_MEMORY_OVERWRITE_0, /*!< Interleave mode: memory overwrite interrupt, planar mode:even byte memory overwrite interrupt */
    CAM_INT_MEMORY_OVERWRITE_1, /*!< Interleave mode: no use,                     planar mode:odd byte memory overwrite interrupt */
    CAM_INT_FRAME_OVERWRITE_0,  /*!< Interleave mode: frame overwrite interrupt,  planar mode:even byte frame overwrite interrupt */
    CAM_INT_FRAME_OVERWRITE_1,  /*!< Interleave mode: no use,                     planar mode:odd byte frame overwrite interrupt */
    CAM_INT_FIFO_OVERWRITE_0,   /*!< Interleave mode: fifo overwrite interrupt,   planar mode:even byte fifo overwrite interrupt */
    CAM_INT_FIFO_OVERWRITE_1,   /*!< Interleave mode: no use,                     planar mode:odd byte fifo overwrite interrupt */
    CAM_INT_VSYNC_CNT_ERROR,    /*!< Vsync valid line count non-match interrupt */
    CAM_INT_HSYNC_CNT_ERROR,    /*!< Hsync valid pixel count non-match interrupt */
    CAM_INT_ALL,                /*!< All of interrupt */
} CAM_INT_Type;

/**
 *  @brief CAM configuration strcut definition
 */
typedef struct
{
    CAM_SW_Mode_Type swMode;            /*!< Software mode */
    uint8_t swIntCnt;                   /*!< Set frame count to issue interrupt at software mode */
    CAM_Frame_Mode_Type frameMode;      /*!< Frame mode */
    CAM_YUV_Mode_Type yuvMode;          /*!< YUV mode */
    CAM_Frame_Active_Pol framePol;      /*!< Frame polarity */
    CAM_Line_Active_Pol linePol;        /*!< Line polarity */
    CAM_Burst_Type burstType;           /*!< AHB burst type */
    CAM_Sensor_Mode_Type camSensorMode; /*!< CAM sensor mode */
    uint8_t waitCount;                  /*!< cycles in FSM wait mode, default value:0x40 */
    uint32_t memStart0;                 /*!< Interleave mode:data start address,   planar mode:even byte start address */
    uint32_t memSize0;                  /*!< Interleave mode:memory size in burst, planar mode:even byte memory size in burst */
    uint32_t frameSize0;                /*!< Interleave mode:frame size in burst,  planar mode:even byte frame size in burst */
    uint32_t memStart1;                 /*!< Interleave mode:no use,               planar mode:odd byte start address */
    uint32_t memSize1;                  /*!< Interleave mode:no use,               planar mode:odd byte memory size in burst */
    uint32_t frameSize1;                /*!< Interleave mode:no use,               planar mode:odd byte frame size in burst */
} CAM_CFG_Type;

/**
 *  @brief CAM interleave mode frame information strcut definition
 */
typedef struct
{
    uint8_t validFrames;    /*!< Valid frames */
    uint32_t curFrameAddr;  /*!< Current frame address */
    uint32_t curFrameBytes; /*!< Current frame bytes */
    uint32_t status;        /*!< CAM module status */
} CAM_Interleave_Frame_Info;

/**
 *  @brief CAM planar mode frame information strcut definition
 */
typedef struct
{
    uint8_t validFrames0;    /*!< Even byte frame counts in memory */
    uint8_t validFrames1;    /*!< Odd byte frame counts in memory */
    uint32_t curFrameAddr0;  /*!< Current even frame address */
    uint32_t curFrameAddr1;  /*!< Current odd frame address */
    uint32_t curFrameBytes0; /*!< Current even frame bytes */
    uint32_t curFrameBytes1; /*!< Current odd frame bytes */
    uint32_t status;         /*!< CAM module status */
} CAM_Planar_Frame_Info;

/*@} end of group CAM_Public_Types */

/** @defgroup  CAM_Public_Constants
 *  @{
 */

/** @defgroup  CAM_BURST_TYPE
 *  @{
 */
#define IS_CAM_BURST_TYPE(type) (((type) == CAM_BURST_TYPE_SINGLE) || \
                                 ((type) == CAM_BURST_TYPE_INCR4) ||  \
                                 ((type) == CAM_BURST_TYPE_INCR8) ||  \
                                 ((type) == CAM_BURST_TYPE_INCR16))

/** @defgroup  CAM_SW_MODE_TYPE
 *  @{
 */
#define IS_CAM_SW_MODE_TYPE(type) (((type) == CAM_SW_MODE_AUTO) || \
                                   ((type) == CAM_SW_MODE_MANUAL))

/** @defgroup  CAM_FRAME_MODE_TYPE
 *  @{
 */
#define IS_CAM_FRAME_MODE_TYPE(type) (((type) == CAM_PLANAR_MODE) || \
                                      ((type) == CAM_INTERLEAVE_MODE))

/** @defgroup  CAM_YUV_MODE_TYPE
 *  @{
 */
#define IS_CAM_YUV_MODE_TYPE(type) (((type) == CAM_YUV422) ||      \
                                    ((type) == CAM_YUV420_EVEN) || \
                                    ((type) == CAM_YUV420_ODD) ||  \
                                    ((type) == CAM_YUV400_EVEN) || \
                                    ((type) == CAM_YUV400_ODD))

/** @defgroup  CAM_LINE_ACTIVE_POL
 *  @{
 */
#define IS_CAM_LINE_ACTIVE_POL(type) (((type) == CAM_LINE_ACTIVE_POLARITY_LOW) || \
                                      ((type) == CAM_LINE_ACTIVE_POLARITY_HIGH))

/** @defgroup  CAM_FRAME_ACTIVE_POL
 *  @{
 */
#define IS_CAM_FRAME_ACTIVE_POL(type) (((type) == CAM_FRAME_ACTIVE_POLARITY_LOW) || \
                                       ((type) == CAM_FRAME_ACTIVE_POLARITY_HIGH))

/** @defgroup  CAM_SENSOR_MODE_TYPE
 *  @{
 */
#define IS_CAM_SENSOR_MODE_TYPE(type) (((type) == CAM_SENSOR_MODE_V_AND_H) || \
                                       ((type) == CAM_SENSOR_MODE_V_OR_H) ||  \
                                       ((type) == CAM_SENSOR_MODE_V) ||       \
                                       ((type) == CAM_SENSOR_MODE_H))

/** @defgroup  CAM_INT_TYPE
 *  @{
 */
#define IS_CAM_INT_TYPE(type) (((type) == CAM_INT_NORMAL_0) ||           \
                               ((type) == CAM_INT_NORMAL_1) ||           \
                               ((type) == CAM_INT_MEMORY_OVERWRITE_0) || \
                               ((type) == CAM_INT_MEMORY_OVERWRITE_1) || \
                               ((type) == CAM_INT_FRAME_OVERWRITE_0) ||  \
                               ((type) == CAM_INT_FRAME_OVERWRITE_1) ||  \
                               ((type) == CAM_INT_FIFO_OVERWRITE_0) ||   \
                               ((type) == CAM_INT_FIFO_OVERWRITE_1) ||   \
                               ((type) == CAM_INT_VSYNC_CNT_ERROR) ||    \
                               ((type) == CAM_INT_HSYNC_CNT_ERROR) ||    \
                               ((type) == CAM_INT_ALL))

/*@} end of group CAM_Public_Constants */

/** @defgroup  CAM_Public_Macros
 *  @{
 */

/*@} end of group CAM_Public_Macros */

/** @defgroup  CAM_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void CAM_IRQHandler(void);
#endif
void CAM_Init(CAM_CFG_Type *cfg);
void CAM_Deinit(void);
void CAM_Enable(void);
void CAM_Disable(void);
void CAM_Clock_Gate(BL_Fun_Type enable);
void CAM_Hsync_Crop(uint16_t start, uint16_t end);
void CAM_Vsync_Crop(uint16_t start, uint16_t end);
void CAM_Set_Hsync_Total_Count(uint16_t count);
void CAM_Set_Vsync_Total_Count(uint16_t count);
void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info);
void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info);
uint8_t CAM_Get_Frame_Count_0(void);
uint8_t CAM_Get_Frame_Count_1(void);
void CAM_Interleave_Pop_Frame(void);
void CAM_Planar_Pop_Frame(void);
void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask);
void CAM_IntClr(CAM_INT_Type intType);
void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun);
void CAM_HW_Mode_Wrap(BL_Fun_Type enable);

/*@} end of group CAM_Public_Functions */

/*@} end of group CAM */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_CAM_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_clock.h
================================================
/**
  ******************************************************************************
  * @file    bl702_clock.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_CLOCK_H__
#define __BL702_CLOCK_H__

#include "glb_reg.h"
#include "bl702_hbn.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  CLOCK
 *  @{
 */

/** @defgroup  CLOCK_Public_Types
 *  @{
 */

/**
 *  @brief System clock type definition
 */
typedef enum {
    BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */
    BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */
    BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */
    BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */
    BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */
    BL_SYSTEM_CLOCK_MAX,  /*!< MAX type of system clock */
} BL_System_Clock_Type;

/**
 *  @brief SOC clock config type
 */
typedef struct
{
    uint16_t systemClock[BL_SYSTEM_CLOCK_MAX];   /*!< System lock value */
    uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
    uint32_t i2sClock;                           /*!< I2S clock */
} Clock_Cfg_Type;

/*@} end of group CLOCK_Public_Types */

/** @defgroup  CLOCK_Public_Constants
 *  @{
 */

/** @defgroup  BL_SYSTEM_CLOCK_TYPE
 *  @{
 */
#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_FCLK) || \
                                       ((type) == BL_SYSTEM_CLOCK_BCLK) || \
                                       ((type) == BL_SYSTEM_CLOCK_F32K) || \
                                       ((type) == BL_SYSTEM_CLOCK_XCLK) || \
                                       ((type) == BL_SYSTEM_CLOCK_XTAL) || \
                                       ((type) == BL_SYSTEM_CLOCK_MAX))

/*@} end of group CLOCK_Public_Constants */

/** @defgroup  CLOCK_Public_Macros
 *  @{
 */

/*@} end of group CLOCK_Public_Macros */

/** @defgroup  CLOCK_Public_Functions
 *  @{
 */
void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock);
void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock);
uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type);

/*@} end of group CLOCK_Public_Functions */

/*@} end of group CLOCK */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_CLOCK_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_common.h
================================================
#ifndef __BL702_COMMON_H__
#define __BL702_COMMON_H__

#include "bl702.h"
#include "misc.h"

#ifndef __NOP
#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
#endif
#ifndef __WFI
#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
#endif
#ifndef __WFE
#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
#endif
#ifndef __SEV
#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
#endif
#ifndef __set_MSP
#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
#endif

__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) {
  // return __builtin_bswap32(value);
  uint32_t res = 0;

  res = (value << 24) | (value >> 24);
  res &= 0xFF0000FF; /* only for sure */
  res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);

  return res;
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { return __builtin_bswap16(value); }

/**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by setting the IE-bit in the PSR.
           Can only be executed in Privileged modes.
 */
__ALWAYS_STATIC_INLINE void __enable_irq(void) { __ASM volatile("csrs mstatus, 8"); }

/**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
  Can only be executed in Privileged modes.
 */
__ALWAYS_STATIC_INLINE void __disable_irq(void) { __ASM volatile("csrc mstatus, 8"); }

/** @defgroup  COMMON_Public_Constants
 *  @{
 */

/** @defgroup DRIVER_INT_PERIPH
 *  @{
 */
#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)

/*@} end of group DRIVER_INT_PERIPH */

/** @defgroup DRIVER_INT_MASK
 *  @{
 */
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))

/*@} end of group COMMON_Public_Constants */

/*@} end of group DRIVER_Public_Macro */
#define BL702_MemCpy      arch_memcpy
#define BL702_MemSet      arch_memset
#define BL702_MemCmp      arch_memcmp
#define BL702_MemCpy4     arch_memcpy4
#define BL702_MemCpy_Fast arch_memcpy_fast
#define BL702_MemSet4     arch_memset4

#define arch_delay_us BL702_Delay_US
#define arch_delay_ms BL702_Delay_MS

void BL702_Delay_US(uint32_t cnt);
void BL702_Delay_MS(uint32_t cnt);
void ASM_Delay_Us(uint32_t core, uint32_t cnt);
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dac.h
================================================
/**
  ******************************************************************************
  * @file    bl702_dac.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_DAC_H__
#define __BL702_DAC_H__

#include "aon_reg.h"
#include "glb_reg.h"
#include "gpip_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  DAC
 *  @{
 */

/** @defgroup  DAC_Public_Types
 *  @{
 */

/**
 *  @brief DAC reference voltage definition
 */
typedef enum {
    GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */
    GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */
} GLB_DAC_Ref_Sel_Type;

/**
 *  @brief DAC reference voltage definition
 */
typedef enum {
    GLB_DAC_Output_Volt_0P2_1,       /*!< DAC output voltage is 0.2-1V */
    GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */
    GLB_DAC_Output_Volt_RESEVED,     /*!< DAC output voltage is 0.225-1.425V */
    GLB_DAC_Output_Volt_0P2_1P8,     /*!< DAC output voltage is 0.2-1.8V */
} GLB_DAC_Output_Volt_Range_Type;

/**
 *  @brief DAC channel type definition
 */
typedef enum {
    GLB_DAC_CHAN0,    /*!< DAC channel 0 */
    GLB_DAC_CHAN1,    /*!< DAC channel 1 */
    GLB_DAC_CHAN2,    /*!< DAC channel 2 */
    GLB_DAC_CHAN3,    /*!< DAC channel 3 */
    GLB_DAC_CHAN4,    /*!< DAC channel 4 */
    GLB_DAC_CHAN5,    /*!< DAC channel 5 */
    GLB_DAC_CHAN6,    /*!< DAC channel 6 */
    GLB_DAC_CHAN7,    /*!< DAC channel 7 */
    GLB_DAC_CHAN_ALL, /*!< DAC channel all */
} GLB_DAC_Chan_Type;

/**
 *  @brief DAC channel configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type chanEn;                      /*!< Enable this channel or not */
    BL_Fun_Type outputEn;                    /*!< Output this channel result to PAD */
    GLB_DAC_Chan_Type outMux;                /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */
    GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */
} GLB_DAC_Chan_Cfg_Type;

/**
 *  @brief DAC configuration structure type definition
 */
typedef struct
{
    GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */
    BL_Fun_Type resetChanA;      /*!< Reset DAC channel A */
    BL_Fun_Type resetChanB;      /*!< Reset DAC channel B */
} GLB_DAC_Cfg_Type;

/**
 *  @brief DAC channel B source selection type definition
 */
typedef enum {
    GPIP_DAC_ChanB_SRC_REG,             /*!< select Reg as source of DAC channel B */
    GPIP_DAC_ChanB_SRC_DMA,             /*!< select DMA as source of DAC channel B */
    GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */
    GPIP_DAC_ChanB_SRC_SIN_GEN,         /*!< select Sin Gen as source of DAC channel B */
    GPIP_DAC_ChanB_SRC_A,               /*!< select channel A as source of DAC channel B */
    GPIP_DAC_ChanB_SRC_INVERSE_A,       /*!< select inverse of channel A as source of DAC channel B */
} GPIP_DAC_ChanB_SRC_Type;

/**
 *  @brief DAC channel A source selection type definition
 */
typedef enum {
    GPIP_DAC_ChanA_SRC_REG,             /*!< select Reg as source of DAC channel A */
    GPIP_DAC_ChanA_SRC_DMA,             /*!< select DMA as source of DAC channel A */
    GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */
    GPIP_DAC_ChanA_SRC_SIN_GEN,         /*!< select Sin Gen as source of DAC channel A */
} GPIP_DAC_ChanA_SRC_Type;

/**
 *  @brief DAC clock divider type definition
 */
typedef enum {
    DAC_CLK_DIV_16,      /*!< ADC clock:on 32M clock is 2M */
    DAC_CLK_DIV_32,      /*!< ADC clock:on 32M clock is 1M */
    DAC_CLK_DIV_RESERVE, /*!< reserved */
    DAC_CLK_DIV_64,      /*!< ADC clock:on 32M clock is 0.5M */
    DAC_CLK_DIV_1,       /*!< ADC clock:on 32M clock is 32M */
} DAC_CLK_Type;

/**
 *  @brief DAC DMA TX format selection type definition
 */
typedef enum {
    GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */
    GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */
    GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */
} GPIP_DAC_DMA_TX_FORMAT_Type;

/**
 *  @brief AON and GPIP DAC configuration structure type definition
 */
typedef struct
{
    GLB_DAC_Ref_Sel_Type refSel;        /*!< DAC reference voltage select */
    BL_Fun_Type resetChanA;             /*!< Reset DAC channel A */
    BL_Fun_Type resetChanB;             /*!< Reset DAC channel B */
    DAC_CLK_Type div;                   /*!< DAC clock div */
    BL_Fun_Type dmaEn;                  /*!< DAC DMA transfer enable */
    GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */
} GLB_GPIP_DAC_Cfg_Type;

/**
 *  @brief AON and GPIP DAC channel A configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type chanCovtEn;      /*!< Enable this channel conversion or not */
    BL_Fun_Type outputEn;        /*!< Output this channel result to PAD */
    BL_Fun_Type chanEn;          /*!< Enable this channel or not */
    GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */
} GLB_GPIP_DAC_ChanA_Cfg_Type;

/**
 *  @brief AON and GPIP DAC channel B configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type chanCovtEn;      /*!< Enable this channel conversion or not */
    BL_Fun_Type outputEn;        /*!< Output this channel result to PAD */
    BL_Fun_Type chanEn;          /*!< Enable this channel or not */
    GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */
} GLB_GPIP_DAC_ChanB_Cfg_Type;

/*@} end of group DAC_Public_Types */

/** @defgroup  DAC_Public_Constants
 *  @{
 */

/** @defgroup  GLB_DAC_REF_SEL_TYPE
 *  @{
 */
#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \
                                       ((type) == GLB_DAC_REF_SEL_EXTERNAL))

/** @defgroup  GLB_DAC_OUTPUT_VOLT_RANGE_TYPE
 *  @{
 */
#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) ||       \
                                                 ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \
                                                 ((type) == GLB_DAC_Output_Volt_RESEVED) ||     \
                                                 ((type) == GLB_DAC_Output_Volt_0P2_1P8))

/** @defgroup  GLB_DAC_CHAN_TYPE
 *  @{
 */
#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \
                                    ((type) == GLB_DAC_CHAN1) || \
                                    ((type) == GLB_DAC_CHAN2) || \
                                    ((type) == GLB_DAC_CHAN3) || \
                                    ((type) == GLB_DAC_CHAN4) || \
                                    ((type) == GLB_DAC_CHAN5) || \
                                    ((type) == GLB_DAC_CHAN6) || \
                                    ((type) == GLB_DAC_CHAN7) || \
                                    ((type) == GLB_DAC_CHAN_ALL))

/** @defgroup  GPIP_DAC_CHANB_SRC_TYPE
 *  @{
 */
#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) ||             \
                                          ((type) == GPIP_DAC_ChanB_SRC_DMA) ||             \
                                          ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \
                                          ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) ||         \
                                          ((type) == GPIP_DAC_ChanB_SRC_A) ||               \
                                          ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A))

/** @defgroup  GPIP_DAC_CHANA_SRC_TYPE
 *  @{
 */
#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) ||             \
                                          ((type) == GPIP_DAC_ChanA_SRC_DMA) ||             \
                                          ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \
                                          ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN))

/** @defgroup  DAC_CLK_TYPE
 *  @{
 */
#define IS_DAC_CLK_TYPE(type) (((type) == DAC_CLK_DIV_16) ||      \
                               ((type) == DAC_CLK_DIV_32) ||      \
                               ((type) == DAC_CLK_DIV_RESERVE) || \
                               ((type) == DAC_CLK_DIV_64) ||      \
                               ((type) == DAC_CLK_DIV_1))

/** @defgroup  GPIP_DAC_DMA_TX_FORMAT_TYPE
 *  @{
 */
#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \
                                              ((type) == GPIP_DAC_DMA_FORMAT_1) || \
                                              ((type) == GPIP_DAC_DMA_FORMAT_2))

/*@} end of group DAC_Public_Constants */

/** @defgroup  DAC_Public_Macros
 *  @{
 */

/*@} end of group DAC_Public_Macros */

/** @defgroup  DAC_Public_Functions
 *  @{
 */
void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg);
void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg);
void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg);
void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src);
void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src);
void GPIP_DAC_ChanB_Enable(void);
void GPIP_DAC_ChanB_Disable(void);
void GPIP_DAC_ChanA_Enable(void);
void GPIP_DAC_ChanA_Disable(void);
void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt);
void GPIP_Set_DAC_DMA_TX_Enable(void);
void GPIP_Set_DAC_DMA_TX_Disable(void);
void GPIP_DAC_DMA_WriteData(uint32_t data);
BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg);
void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg);
void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg);
void GLB_DAC_Set_ChanA_Value(uint16_t val);
void GLB_DAC_Set_ChanB_Value(uint16_t val);

/*@} end of group DAC_Public_Functions */

/*@} end of group DAC */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_DAC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_dma.h
================================================
/**
  ******************************************************************************
  * @file    bl702_dma.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_DMA_H__
#define __BL702_DMA_H__

#include "dma_reg.h"
#include "bl702_common.h"

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  DMA
 *  @{
 */

/** @defgroup  DMA_Public_Types
 *  @{
 */

/**
 *  @brief DMA endian type definition
 */
typedef enum {
    DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */
    DMA_BIG_ENDIAN,        /*!< DMA use big endian */
} DMA_Endian_Type;

/**
 *  @brief DMA synchronization logic  type definition
 */
typedef enum {
    DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */
    DMA_SYNC_LOGIC_DISABLE,    /*!< DMA synchronization logic disable */
} DMA_Sync_Logic_Type;

/**
 *  @brief DMA transfer width type definition
 */
typedef enum {
    DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */
    DMA_TRNS_WIDTH_16BITS,    /*!< DMA transfer width:16 bits */
    DMA_TRNS_WIDTH_32BITS,    /*!< DMA transfer width:32 bits */
} DMA_Trans_Width_Type;

/**
 *  @brief DMA transfer direction type definition
 */
typedef enum {
    DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */
    DMA_TRNS_M2P,     /*!< DMA transfer tyep:memory to peripheral */
    DMA_TRNS_P2M,     /*!< DMA transfer tyep:peripheral to memory */
    DMA_TRNS_P2P,     /*!< DMA transfer tyep:peripheral to peripheral */
} DMA_Trans_Dir_Type;

/**
 *  @brief DMA burst size type definition
 */
typedef enum {
    DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */
    DMA_BURST_SIZE_4,     /*!< DMA transfer width:16 bits */
    DMA_BURST_SIZE_8,     /*!< DMA transfer width:32 bits */
    DMA_BURST_SIZE_16,    /*!< DMA transfer width:64 bits */
} DMA_Burst_Size_Type;

/**
 *  @brief DMA destination peripheral type definition
 */
typedef enum {
    DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */
    DMA_REQ_UART0_TX,     /*!< DMA request peripheral:UART0 TX */
    DMA_REQ_UART1_RX,     /*!< DMA request peripheral:UART1 RX */
    DMA_REQ_UART1_TX,     /*!< DMA request peripheral:UART1 TX */
    DMA_REQ_I2C_RX = 6,   /*!< DMA request peripheral:I2C RX */
    DMA_REQ_I2C_TX,       /*!< DMA request peripheral:I2C TX */
    DMA_REQ_SPI_RX = 10,  /*!< DMA request peripheral:SPI RX */
    DMA_REQ_SPI_TX,       /*!< DMA request peripheral:SPI TX */
    DMA_REQ_I2S_RX = 20,  /*!< DMA request peripheral:SPI RX */
    DMA_REQ_I2S_TX,       /*!< DMA request peripheral:SPI TX */
    DMA_REQ_GPADC0 = 22,  /*!< DMA request peripheral:GPADC0 */
    DMA_REQ_GPADC1,       /*!< DMA request peripheral:GPADC1 */
    DMA_REQ_NONE = 0,     /*!< DMA request peripheral:None */
} DMA_Periph_Req_Type;

/**
 *  @brief DMA channel type definition
 */
typedef enum {
    DMA_CH0 = 0, /*!< DMA channel 0 */
    DMA_CH1,     /*!< DMA channel 1 */
    DMA_CH2,     /*!< DMA channel 2 */
    DMA_CH3,     /*!< DMA channel 3 */
    DMA_CH4,     /*!< DMA channel 4 */
    DMA_CH5,     /*!< DMA channel 5 */
    DMA_CH6,     /*!< DMA channel 6 */
    DMA_CH7,     /*!< DMA channel 7 */
    DMA_CH_MAX,  /*!<  */
} DMA_Chan_Type;

/**
 *  @brief DMA LLI Structure PING-PONG
 */
typedef enum {
    PING_INDEX = 0, /*!< PING INDEX */
    PONG_INDEX,     /*!< PONG INDEX */
} DMA_LLI_PP_Index_Type;

/**
 *  @brief DMA interrupt type definition
 */
typedef enum {
    DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */
    DMA_INT_ERR,            /*!< DMA error interrupt */
    DMA_INT_ALL,            /*!< All the interrupt */
} DMA_INT_Type;

/**
 *  @brief DMA Configuration Structure type definition
 */
typedef struct
{
    DMA_Endian_Type endian;        /*!< DMA endian type */
    DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */
} DMA_Cfg_Type;

/**
 *  @brief DMA channel Configuration Structure type definition
 */
typedef struct
{
    uint32_t srcDmaAddr;                 /*!< Source address of DMA transfer */
    uint32_t destDmaAddr;                /*!< Destination address of DMA transfer */
    uint32_t transfLength;               /*!< Transfer length, 0~4095, this is burst count */
    DMA_Trans_Dir_Type dir;              /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
    DMA_Chan_Type ch;                    /*!< Channel select 0-7 */
    DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8  bits, 1: 16  bits, 2: 32  bits */
    DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8  bits, 1: 16  bits, 2: 32  bits */
    DMA_Burst_Size_Type srcBurstSize;    /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
                                                 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
    DMA_Burst_Size_Type dstBurstSize;    /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
                                                 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
    BL_Fun_Type dstAddMode;              /*!<  */
    BL_Fun_Type dstMinMode;              /*!<  */
    uint8_t fixCnt;                      /*!<  */
    uint8_t srcAddrInc;                  /*!< Source address increment. 0: No change, 1: Increment */
    uint8_t destAddrInc;                 /*!< Destination address increment. 0: No change, 1: Increment */
    DMA_Periph_Req_Type srcPeriph;       /*!< Source peripheral select */
    DMA_Periph_Req_Type dstPeriph;       /*!< Destination peripheral select */
} DMA_Channel_Cfg_Type;


/**
 *  @brief DMA LLI configuration structure type definition
 */
typedef struct
{
    DMA_Trans_Dir_Type dir;        /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
    DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */
    DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */
} DMA_LLI_Cfg_Type;


/*@} end of group DMA_Public_Types */

/** @defgroup  DMA_Public_Constants
 *  @{
 */

/** @defgroup  DMA_ENDIAN_TYPE
 *  @{
 */
#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \
                                  ((type) == DMA_BIG_ENDIAN))

/** @defgroup  DMA_SYNC_LOGIC_TYPE
 *  @{
 */
#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \
                                      ((type) == DMA_SYNC_LOGIC_DISABLE))

/** @defgroup  DMA_TRANS_WIDTH_TYPE
 *  @{
 */
#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) ||  \
                                       ((type) == DMA_TRNS_WIDTH_16BITS) || \
                                       ((type) == DMA_TRNS_WIDTH_32BITS))

/** @defgroup  DMA_TRANS_DIR_TYPE
 *  @{
 */
#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \
                                     ((type) == DMA_TRNS_M2P) || \
                                     ((type) == DMA_TRNS_P2M) || \
                                     ((type) == DMA_TRNS_P2P))

/** @defgroup  DMA_BURST_SIZE_TYPE
 *  @{
 */
#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \
                                      ((type) == DMA_BURST_SIZE_4) || \
                                      ((type) == DMA_BURST_SIZE_8) || \
                                      ((type) == DMA_BURST_SIZE_16))

/** @defgroup  DMA_PERIPH_REQ_TYPE
 *  @{
 */
#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \
                                      ((type) == DMA_REQ_UART0_TX) || \
                                      ((type) == DMA_REQ_UART1_RX) || \
                                      ((type) == DMA_REQ_UART1_TX) || \
                                      ((type) == DMA_REQ_I2C_RX) ||   \
                                      ((type) == DMA_REQ_I2C_TX) ||   \
                                      ((type) == DMA_REQ_SPI_RX) ||   \
                                      ((type) == DMA_REQ_SPI_TX) ||   \
                                      ((type) == DMA_REQ_I2S_RX) ||   \
                                      ((type) == DMA_REQ_I2S_TX) ||   \
                                      ((type) == DMA_REQ_GPADC0) ||   \
                                      ((type) == DMA_REQ_GPADC1) ||   \
                                      ((type) == DMA_REQ_NONE))

/** @defgroup  DMA_CHAN_TYPE
 *  @{
 */
#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \
                                ((type) == DMA_CH1) || \
                                ((type) == DMA_CH2) || \
                                ((type) == DMA_CH3) || \
                                ((type) == DMA_CH4) || \
                                ((type) == DMA_CH5) || \
                                ((type) == DMA_CH6) || \
                                ((type) == DMA_CH7) || \
                                ((type) == DMA_CH_MAX))

/** @defgroup  DMA_LLI_PP_INDEX_TYPE
 *  @{
 */
#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \
                                        ((type) == PONG_INDEX))

/** @defgroup  DMA_INT_TYPE
 *  @{
 */
#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \
                               ((type) == DMA_INT_ERR) ||        \
                               ((type) == DMA_INT_ALL))

/*@} end of group DMA_Public_Constants */

/** @defgroup  DMA_Public_Macros
 *  @{
 */
#define DMA_PINC_ENABLE  1
#define DMA_PINC_DISABLE 0
#define DMA_MINC_ENABLE  1
#define DMA_MINC_DISABLE 0

/*@} end of group DMA_Public_Macros */

/** @defgroup  DMA_Public_Functions
 *  @{
 */

/**
 *  @brief DMA Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void DMA_ALL_IRQHandler(void);
#endif
void DMA_Enable(void);
void DMA_Disable(void);
void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg);
void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
uint32_t DMA_Channel_TranferSize(uint8_t ch);
BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch);
void DMA_Channel_Enable(uint8_t ch);
void DMA_Channel_Disable(uint8_t ch);
void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg);
void DMA_LLI_Update(uint8_t ch, uint32_t LLI);
void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask);
void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun);

/*@} end of group DMA_Public_Functions */

/*@} end of group DMA */

/*@} end of group BL702_Peripheral_Driver */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __BL702_DMA_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ef_ctrl.h
================================================
/**
 ******************************************************************************
 * @file    bl702_ef_ctrl.h
 * @version V1.0
 * @date
 * @brief   This file is the standard driver header file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#ifndef __BL702_EF_CTRL_H__
#define __BL702_EF_CTRL_H__

#include "bl702_common.h"
#include "ef_ctrl_reg.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  EF_CTRL
 *  @{
 */

/** @defgroup  EF_CTRL_Public_Types
 *  @{
 */

/**
 *  @brief Efuse Ctrl key slot type definition
 */
typedef enum {
  EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
  EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
  EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
  EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
  EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
  EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
  EF_CTRL_KEY_MAX,   /*!<  */
} EF_Ctrl_Key_Type;

/**
 *  @brief Efuse Ctrl sign type definition
 */
typedef enum {
  EF_CTRL_SIGN_NONE, /*!< no sign */
  EF_CTRL_SIGN_RSA,  /*!< use RSA to sign */
  EF_CTRL_SIGN_ECC,  /*!< use ECC to sign */
} EF_Ctrl_Sign_Type;

/**
 *  @brief Efuse Ctrl flash AES type definition
 */
typedef enum {
  EF_CTRL_SF_AES_NONE, /*!< No AES */
  EF_CTRL_SF_AES_128,  /*!< AES 128 */
  EF_CTRL_SF_AES_192,  /*!< AES 192 */
  EF_CTRL_SF_AES_256,  /*!< AES 256 */
} EF_Ctrl_SF_AES_Type;

/**
 *  @brief Efuse Ctrl Dbg type definition
 */
typedef enum {
  EF_CTRL_DBG_OPEN = 0,  /*!< Open debug */
  EF_CTRL_DBG_PASSWORD,  /*!< Open debug with password */
  EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
} EF_Ctrl_Dbg_Mode_Type;

/**
 *  @brief Efuse Ctrl clock type definition
 */
typedef enum {
  EF_CTRL_EF_CLK,   /*!< Select efuse clock */
  EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
} EF_Ctrl_CLK_Type;

/**
 *  @brief Efuse Ctrl clock type definition
 */
typedef enum {
  EF_CTRL_PARA_DFT,    /*!< Select default cyc parameter */
  EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
} EF_Ctrl_CYC_PARA_Type;

/**
 *  @brief Efuse Ctrl clock type definition
 */
typedef enum {
  EF_CTRL_OP_MODE_AUTO,   /*!< Select efuse program auto mode */
  EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
} EF_Ctrl_OP_MODE_Type;

/**
 *  @brief Efuse Ctrl secure configuration structure type definition
 */
typedef struct {
  EF_Ctrl_Dbg_Mode_Type ef_dbg_mode;       /*!< Efuse debug mode */
  uint8_t               ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */
  uint8_t               ef_sboot_en;       /*!< Secure boot enable config value */
} EF_Ctrl_Sec_Param_Type;

/**
 *  @brief Efuse analog RC32M trim type definition
 */
typedef struct {
  uint32_t trimRc32mCodeFrExt : 8;       /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
  uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
  uint32_t trimRc32mExtCodeEn : 1;       /*!< Efuse analog trim:trim_rc32m_ext_code_en */
  uint32_t reserved : 22;                /*!< Efuse analog trim:reserved */
} Efuse_Ana_RC32M_Trim_Type;

/**
 *  @brief Efuse analog RC32K trim type definition
 */
typedef struct {
  uint32_t trimRc32kCodeFrExt : 10;      /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
  uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
  uint32_t trimRc32kExtCodeEn : 1;       /*!< Efuse analog trim:trim_rc32k_ext_code_en */
  uint32_t reserved : 20;                /*!< Efuse analog trim:reserved */
} Efuse_Ana_RC32K_Trim_Type;

/**
 *  @brief Efuse analog TSEN trim type definition
 */
typedef struct {
  uint32_t tsenRefcodeCorner : 12;       /*!< TSEN refcode */
  uint32_t tsenRefcodeCornerParity : 1;  /*!< TSEN refcode parity */
  uint32_t tsenRefcodeCornerEn : 1;      /*!< TSEN refcode enable */
  uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN ATE Version */
  uint32_t reserved : 18;                /*!< TSEN analog trim:reserved */
} Efuse_TSEN_Refcode_Corner_Type;

/**
 *  @brief Efuse analog ADC Gain trim type definition
 */
typedef struct {
  uint32_t adcGainCoeff : 12;      /*!< ADC gain coeff */
  uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */
  uint32_t adcGainCoeffEn : 1;     /*!< ADC gain coeff enable */
  uint32_t reserved : 18;          /*!< ADC gain coeff:reserved */
} Efuse_ADC_Gain_Coeff_Type;

/**
 *  @brief Efuse analog device info type definition
 */
typedef struct {
  uint32_t rsvd_21_0 : 22;  /*!< Reserved */
  uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */
  uint32_t psram_cfg : 2;   /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */
  uint32_t flash_cfg : 3;   /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1 */
  uint32_t rsvd_29 : 1;     /*!< Reserved */
  uint32_t pkg_info : 2;    /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */
} Efuse_Device_Info_Type;

/**
 *  @brief Efuse Capcode type definition
 */
typedef struct {
  uint32_t capCode : 6; /*!< Cap code value */
  uint32_t parity : 1;  /*!< Parity of capcode */
  uint32_t en : 1;      /*!< Enable status */
  uint32_t rsvd : 24;   /*!< Reserved */
} Efuse_Capcode_Info_Type;

/*@} end of group EF_CTRL_Public_Types */

/** @defgroup  EF_CTRL_Public_Constants
 *  @{
 */

/** @defgroup  EF_CTRL_KEY_TYPE
 *  @{
 */
#define IS_EF_CTRL_KEY_TYPE(type)                                                                                                                                                                     \
  (((type) == EF_CTRL_KEY_SLOT0) || ((type) == EF_CTRL_KEY_SLOT1) || ((type) == EF_CTRL_KEY_SLOT2) || ((type) == EF_CTRL_KEY_SLOT3) || ((type) == EF_CTRL_KEY_SLOT4) || ((type) == EF_CTRL_KEY_SLOT5) \
   || ((type) == EF_CTRL_KEY_MAX))

/** @defgroup  EF_CTRL_SIGN_TYPE
 *  @{
 */
#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || ((type) == EF_CTRL_SIGN_RSA) || ((type) == EF_CTRL_SIGN_ECC))

/** @defgroup  EF_CTRL_SF_AES_TYPE
 *  @{
 */
#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || ((type) == EF_CTRL_SF_AES_128) || ((type) == EF_CTRL_SF_AES_192) || ((type) == EF_CTRL_SF_AES_256))

/** @defgroup  EF_CTRL_DBG_MODE_TYPE
 *  @{
 */
#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || ((type) == EF_CTRL_DBG_PASSWORD) || ((type) == EF_CTRL_DBG_CLOSE))

/** @defgroup  EF_CTRL_CLK_TYPE
 *  @{
 */
#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || ((type) == EF_CTRL_SAHB_CLK))

/** @defgroup  EF_CTRL_CYC_PARA_TYPE
 *  @{
 */
#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || ((type) == EF_CTRL_PARA_MANUAL))

/** @defgroup  EF_CTRL_OP_MODE_TYPE
 *  @{
 */
#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || ((type) == EF_CTRL_OP_MODE_MANUAL))

/*@} end of group EF_CTRL_Public_Constants */

/** @defgroup  EF_CTRL_Public_Macros
 *  @{
 */
#define EF_CTRL_EFUSE_R0_SIZE 128

/*@} end of group EF_CTRL_Public_Macros */

/** @defgroup  EF_CTRL_Public_Functions
 *  @{
 */
void        EF_Ctrl_Load_Efuse_R0(void);
BL_Sts_Type EF_Ctrl_Busy(void);
BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
void        EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
void        EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh);
void        EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
void        EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
void        EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
void        EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
void        EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
void        EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]);
void        EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType);
uint8_t     EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
void        EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program);
void        EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim);
void        EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
void        EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
void        EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
void        EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
void        EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
void        EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
void        EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
void        EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
void        EF_Ctrl_Writelock_MAC_Address(uint8_t program);
uint8_t     EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload);
BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
/*----------*/
BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]);
uint32_t    EF_Ctrl_Get_Key_Slot_w0();
uint32_t    EF_Ctrl_Get_Key_Slot_w1();
BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
/*----------*/
void        EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
uint8_t     EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program);
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload);
uint8_t     EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload);
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program);
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload);
void        EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
void        EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
void        EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
void        EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
void        EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
void        EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
void        EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len);
void        EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len);
void        EF_Ctrl_Clear(uint32_t index, uint32_t len);
void        EF_Ctrl_Crc_Enable(void);
BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
void        EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
BL_Err_Type EF_Ctrl_Crc_Result(void);
void        EF_Ctrl_Sw_AHB_Clk_0(void);

/*@} end of group EF_CTRL_Public_Functions */

/*@} end of group EF_CTRL */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_EF_CTRL_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_emac.h
================================================
/**
  ******************************************************************************
  * @file    bl702_emac.h
  * @version V1.2
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2018 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_EMAC_H__
#define __BL702_EMAC_H__

#include "emac_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  EMAC
 *  @{
 */

/** @defgroup  EMAC_Public_Types
 *  @{
 */

/**
 *  @brief EMAC half/full-duplex type definition
 */
typedef enum {
    EMAC_MODE_HALFDUPLEX, /*!< ETH half-duplex */
    EMAC_MODE_FULLDUPLEX, /*!< ETH full-duplex */
} EMAC_Duplex_Type;

/**
 *  @brief EMAC speed type definition
 */
typedef enum {
    EMAC_SPEED_10M,  /*!< ETH speed 10M */
    EMAC_SPEED_100M, /*!< ETH speed 100M */
} EMAC_Speed_Type;

/**
 *  @brief EMAC interrupt type definition
 */
typedef enum {
    EMAC_INT_TX_DONE = 0x01,  /*!< Transmit one frame done */
    EMAC_INT_TX_ERROR = 0x02, /*!< Transmit error occur */
    EMAC_INT_RX_DONE = 0x04,  /*!< Receive one frame done */
    EMAC_INT_RX_ERROR = 0x08, /*!< Receive error occur */
    EMAC_INT_RX_BUSY = 0x10,  /*!< Receive busy due to no free RX buffer Descripter */
    EMAC_INT_TX_CTRL = 0x20,  /*!< Transmit control frame */
    EMAC_INT_RX_CTRL = 0x40,  /*!< Receive control frame */
    EMAC_INT_ALL = 0x7F,      /*!<  */
} EMAC_INT_Type;

/**
 *  @brief EMAC interrupt Index
 */
typedef enum {
    EMAC_INT_TX_DONE_IDX = 0x0,  /*!< Transmit one frame done */
    EMAC_INT_TX_ERROR_IDX = 0x1, /*!< Transmit error occur */
    EMAC_INT_RX_DONE_IDX = 0x2,  /*!< Receive one frame done */
    EMAC_INT_RX_ERROR_IDX = 0x3, /*!< Receive error occur */
    EMAC_INT_RX_BUSY_IDX = 0x4,  /*!< Receive busy due to no free RX buffer Descripter */
    EMAC_INT_TX_CTRL_IDX = 0x5,  /*!< Transmit control frame */
    EMAC_INT_RX_CTRL_IDX = 0x6,  /*!< Receive control frame */
    EMAC_INT_CNT,                /*!< EMAC INT source count */
} EMAC_INT_Index;

/**
 *  @brief EMAC configuration type definition
 */
typedef struct
{
    BL_Fun_Type recvSmallFrame;     /*!< Receive small frmae or not */
    BL_Fun_Type recvHugeFrame;      /*!< Receive huge frmae(>64K bytes) or not */
    BL_Fun_Type padEnable;          /*!< Enable padding for frame which is less than MINFL or not */
    BL_Fun_Type crcEnable;          /*!< Enable hardware CRC or not */
    BL_Fun_Type noPreamble;         /*!< Enable preamble or not */
    BL_Fun_Type recvBroadCast;      /*!< Receive broadcast frame or not */
    BL_Fun_Type interFrameGapCheck; /*!< Check inter frame gap or not */
    BL_Fun_Type miiNoPreamble;      /*!< Enable MII interface preamble or not */
    uint8_t miiClkDiv;              /*!< MII interface clock divider from bus clock */
    uint8_t maxTxRetry;             /*!< Maximum tx retry count */
    uint16_t interFrameGapValue;    /*!< Inter frame gap vaule in clock cycles(default 24),which equals 9.6 us for 10 Mbps and 0.96 us
                                                 for 100 Mbps mode */
    uint16_t minFrameLen;           /*!< Minimum frame length */
    uint16_t maxFrameLen;           /*!< Maximum frame length */
    uint16_t collisionValid;        /*!< Collision valid value */
    uint8_t macAddr[6];             /*!< MAC Address */
} EMAC_CFG_Type;

/**
 *  @brief EMAC TX DMA description type definition
 */
/**
 * Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
 */
typedef struct
{
    uint32_t C_S_L;  /*!< Buffer Descriptors(BD) control,status,length */
    uint32_t Buffer; /*!< BD buffer address */
} EMAC_BD_Desc_Type;

/**
 *  @brief EMAC Handle type definition
 */
typedef struct
{
    EMAC_BD_Desc_Type *bd; /*!< Tx descriptor header pointer */
    uint8_t txIndexEMAC;   /*!< TX index: EMAC */
    uint8_t txIndexCPU;    /*!< TX index: CPU/SW */
    uint8_t txBuffLimit;   /*!< TX index max */
    uint8_t rsv0;
    uint8_t rxIndexEMAC; /*!< RX index: EMAC */
    uint8_t rxIndexCPU;  /*!< RX index: CPU/SW */
    uint8_t rxBuffLimit; /*!< RX index max */
    uint8_t rsv1;
} EMAC_Handle_Type;

/*@} end of group EMAC_Public_Types */

/** @defgroup  EMAC_Public_Constants
 *  @{
 */

/** @defgroup  EMAC_DUPLEX_TYPE
 *  @{
 */
#define IS_EMAC_DUPLEX_TYPE(type) (((type) == EMAC_MODE_HALFDUPLEX) || \
                                   ((type) == EMAC_MODE_FULLDUPLEX))

/** @defgroup  EMAC_SPEED_TYPE
 *  @{
 */
#define IS_EMAC_SPEED_TYPE(type) (((type) == EMAC_SPEED_10M) || \
                                  ((type) == EMAC_SPEED_100M))

/** @defgroup  EMAC_INT_TYPE
 *  @{
 */
#define IS_EMAC_INT_TYPE(type) (((type) == EMAC_INT_TX_DONE) ||  \
                                ((type) == EMAC_INT_TX_ERROR) || \
                                ((type) == EMAC_INT_RX_DONE) ||  \
                                ((type) == EMAC_INT_RX_ERROR) || \
                                ((type) == EMAC_INT_RX_BUSY) ||  \
                                ((type) == EMAC_INT_TX_CTRL) ||  \
                                ((type) == EMAC_INT_RX_CTRL) ||  \
                                ((type) == EMAC_INT_ALL))

/** @defgroup  EMAC_INT_INDEX
 *  @{
 */
#define IS_EMAC_INT_INDEX(type) (((type) == EMAC_INT_TX_DONE_IDX) ||  \
                                 ((type) == EMAC_INT_TX_ERROR_IDX) || \
                                 ((type) == EMAC_INT_RX_DONE_IDX) ||  \
                                 ((type) == EMAC_INT_RX_ERROR_IDX) || \
                                 ((type) == EMAC_INT_RX_BUSY_IDX) ||  \
                                 ((type) == EMAC_INT_TX_CTRL_IDX) ||  \
                                 ((type) == EMAC_INT_RX_CTRL_IDX) ||  \
                                 ((type) == EMAC_INT_CNT))

/*@} end of group EMAC_Public_Constants */

/** @defgroup  EMAC_Public_Macros
 *  @{
 */
#define BD_TX_CS_POS   (0) /*!< Carrier Sense Lost */
#define BD_TX_CS_LEN   (1)
#define BD_TX_DF_POS   (1) /*!< Defer Indication */
#define BD_TX_DF_LEN   (1)
#define BD_TX_LC_POS   (2) /*!< Late Collision */
#define BD_TX_LC_LEN   (1)
#define BD_TX_RL_POS   (3) /*!< Retransmission Limit */
#define BD_TX_RL_LEN   (1)
#define BD_TX_RTRY_POS (4) /*!< Retry Count */
#define BD_TX_RTRY_LEN (4)
#define BD_TX_UR_POS   (8) /*!< Underrun */
#define BD_TX_UR_LEN   (1)
#define BD_TX_EOF_POS  (10) /*!< EOF */
#define BD_TX_EOF_LEN  (1)
#define BD_TX_CRC_POS  (11) /*!< CRC Enable */
#define BD_TX_CRC_LEN  (1)
#define BD_TX_PAD_POS  (12) /*!< PAD enable */
#define BD_TX_PAD_LEN  (1)
#define BD_TX_WR_POS   (13) /*!< Wrap */
#define BD_TX_WR_LEN   (1)
#define BD_TX_IRQ_POS  (14) /*!< Interrupt Request Enable */
#define BD_TX_IRQ_LEN  (1)
#define BD_TX_RD_POS   (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
#define BD_TX_RD_LEN   (1)
#define BD_TX_LEN_POS  (16) /*!< TX Data buffer length */
#define BD_TX_LEN_LEN  (16)

#define BD_RX_LC_POS  (0) /*!< Late Collision */
#define BD_RX_LC_LEN  (1)
#define BD_RX_CRC_POS (1) /*!< RX CRC Error */
#define BD_RX_CRC_LEN (1)
#define BD_RX_SF_POS  (2) /*!< Short Frame */
#define BD_RX_SF_LEN  (1)
#define BD_RX_TL_POS  (3) /*!< Too Long */
#define BD_RX_TL_LEN  (1)
#define BD_RX_DN_POS  (4) /*!< Dribble Nibble */
#define BD_RX_DN_LEN  (1)
#define BD_RX_RE_POS  (5) /*!< Receive Error */
#define BD_RX_RE_LEN  (1)
#define BD_RX_OR_POS  (6) /*!< Overrun */
#define BD_RX_OR_LEN  (1)
#define BD_RX_M_POS   (7) /*!< Miss */
#define BD_RX_M_LEN   (1)
#define BD_RX_CF_POS  (8) /*!< Control Frame Received */
#define BD_RX_CF_LEN  (1)
#define BD_RX_WR_POS  (13) /*!< Wrap */
#define BD_RX_WR_LEN  (1)
#define BD_RX_IRQ_POS (14) /*!< Interrupt Request Enable */
#define BD_RX_IRQ_LEN (1)
#define BD_RX_E_POS   (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
#define BD_RX_E_LEN   (1)
#define BD_RX_LEN_POS (16) /*!< RX Data buffer length */
#define BD_RX_LEN_LEN (16)

#define EMAC_BD_FIELD_MSK(field)  (((1U << BD_##field##_LEN) - 1) << BD_##field##_POS)
#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS))
/* DMA Descriptor offset */
#define EMAC_DMA_DESC_OFFSET 0x400

/* ETH packet size */
// ETH     | Header | Extra | VLAN tag | Payload   | CRC |
// Size    | 14     | 2     | 4        | 46 ~ 1500 | 4   |
#define ETH_MAX_PACKET_SIZE          ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER_SZIE              ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC_SIZE                 ((uint32_t)4U) /*!< Ethernet CRC */
#define ETH_EXTRA_SIZE               ((uint32_t)2U) /*!< Extra bytes in some cases */
#define ETH_VLAN_TAG_SIZE            ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
#define ETH_MIN_ETH_PAYLOAD_SIZE     ((uint32_t)46U) /*!< Minimum Ethernet payload size */
#define ETH_MAX_ETH_PAYLOAD_SIZE     ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */

/*@} end of group EMAC_Public_Macros */

/** @defgroup  EMAC_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void EMAC_IRQHandler(void);
#endif
BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg);
BL_Err_Type EMAC_DeInit(void);
BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount,
                                 uint8_t *rxBuff, uint32_t rxBuffCount);
BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc);
BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len);
BL_Err_Type EMAC_Enable(void);
BL_Err_Type EMAC_Disable(void);
BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask);
BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType);
BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType);
BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun);
BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount);
BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1);
BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue);
BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue);

BL_Err_Type EMAC_Enable_TX(void);
BL_Err_Type EMAC_Disable_TX(void);
BL_Err_Type EMAC_Enable_RX(void);
BL_Err_Type EMAC_Disable_RX(void);

void EMAC_Phy_SetAddress(uint16_t phyAddress);
void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex);

/*@} end of group EMAC_Public_Functions */

/*@} end of group EMAC */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_EMAC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_glb.h
================================================
/**
  ******************************************************************************
  * @file    bl702_glb.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_GLB_H__
#define __BL702_GLB_H__

#include "glb_reg.h"
#include "pds_reg.h"
#include "bl702_gpio.h"
#include "bl702_l1c.h"
#include "bl702_hbn.h"
#include "bl702_sf_ctrl.h"
#include "bl702_sf_cfg.h"
#include "bl702_aon.h"
#include "bl702_ef_ctrl.h"
#include "bl702_pds.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  GLB
 *  @{
 */

/** @defgroup  GLB_Public_Types
 *  @{
 */

/**
 *  @brief GLB root clock type definition
 */
typedef enum {
    GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */
    GLB_ROOT_CLK_XTAL,  /*!< root clock select XTAL */
    GLB_ROOT_CLK_DLL,   /*!< root clock select DLL others, PLL120M not recommend */
} GLB_ROOT_CLK_Type;

/**
 *  @brief GLB system clock type definition
 */
typedef enum {
    GLB_SYS_CLK_RC32M,    /*!< use RC32M as system clock frequency */
    GLB_SYS_CLK_XTAL,     /*!< use XTAL as system clock */
    GLB_SYS_CLK_DLL57P6M, /*!< use DLL output 57.6M as system clock */
    GLB_SYS_CLK_DLL96M,   /*!< use DLL output 96M as system clock */
    GLB_SYS_CLK_DLL144M,  /*!< use DLL output 144M as system clock, PLL120M not recommend */
} GLB_SYS_CLK_Type;

/**
 *  @brief GLB CAM clock type definition
 */
typedef enum {
    GLB_CAM_CLK_XCLK,   /*!< Select XCLK as CAM clock */
    GLB_CAM_CLK_DLL96M, /*!< Select DLL96M as CAM clock */
} GLB_CAM_CLK_Type;

/**
 *  @brief GLB I2S output ref clock type definition
 */
typedef enum {
    GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */
    GLB_I2S_OUT_REF_CLK_SRC,  /*!< output reference clock on I2S_0 ref_clock port */
} GLB_I2S_OUT_REF_CLK_Type;

/**
 *  @brief GLB qdec clock type definition
 */
typedef enum {
    GLB_QDEC_CLK_XCLK, /*!< Select XCLK as QDEC clock */
    GLB_QDEC_CLK_F32K, /*!< Select f32k as QDEC clock (PDS mode) */
} GLB_QDEC_CLK_Type;

/**
 *  @brief GLB DMA clock ID type definition
 */
typedef enum {
    GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */
    GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */
    GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */
    GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */
    GLB_DMA_CLK_DMA0_CH4, /*!< DMA clock ID:channel 4 */
    GLB_DMA_CLK_DMA0_CH5, /*!< DMA clock ID:channel 5 */
    GLB_DMA_CLK_DMA0_CH6, /*!< DMA clock ID:channel 6 */
    GLB_DMA_CLK_DMA0_CH7, /*!< DMA clock ID:channel 7 */
} GLB_DMA_CLK_ID_Type;

/**
 *  @brief GLB clock source type definition
 */
typedef enum {
    GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
} GLB_IR_CLK_SRC_Type;

/**
 *  @brief GLB flash clock type definition
 */
typedef enum {
    GLB_SFLASH_CLK_144M,  /*!< Select 144M as flash clock */
    GLB_SFLASH_CLK_XCLK,  /*!< Select XCLK as flash clock */
    GLB_SFLASH_CLK_57P6M, /*!< Select 57.6M as flash clock */
    GLB_SFLASH_CLK_72M,   /*!< Select 72M as flash clock */
    GLB_SFLASH_CLK_BCLK,  /*!< Select BCLK as flash clock */
    GLB_SFLASH_CLK_96M,   /*!< Select 96M as flash clock */
} GLB_SFLASH_CLK_Type;

/**
 *  @brief GLB chip clock out type definition
 */
typedef enum {
    GLB_CHIP_CLK_OUT_NONE,          /*!< no chip clock out */
    GLB_CHIP_CLK_OUT_I2S_REF_CLK,   /*!< i2s_ref_clk out */
    GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK, /*!< audio_pll_clk out */
    GLB_CHIP_CLK_OUT_XTAL_SOC_32M,  /*!< clk_xtal_soc_32M */
} GLB_CHIP_CLK_OUT_Type;

/**
 *  @brief GLB eth ref clock out type definition
 */
typedef enum {
    GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */
    GLB_ETH_REF_CLK_OUT_INSIDE_50M,  /*!< select inside 50MHz RMII ref clock */
} GLB_ETH_REF_CLK_OUT_Type;

/**
 *  @brief GLB SPI pad action type definition
 */
typedef enum {
    GLB_SPI_PAD_ACT_AS_SLAVE,  /*!< SPI pad act as slave */
    GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
} GLB_SPI_PAD_ACT_AS_Type;

/**
 *  @brief GLB PKA clock type definition
 */
typedef enum {
    GLB_PKA_CLK_HCLK,   /*!< Select HCLK as PKA clock */
    GLB_PKA_CLK_DLL96M, /*!< Select DLL 96M as PKA clock */
} GLB_PKA_CLK_Type;

/**
 *  @brief BMX arb mode type definition
 */
typedef enum {
    BMX_ARB_FIX,         /*!< 0->fix */
    BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
    BMX_ARB_RANDOM,      /*!< 3->random */
} BMX_ARB_Type;

/**
 *  @brief BMX configuration structure type definition
 */
typedef struct {
    uint8_t timeoutEn;   /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
    BL_Fun_Type errEn;   /*!< Bus error response enable */
    BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
} BMX_Cfg_Type;

/**
 *  @brief BMX bus err type definition
 */
typedef enum {
    BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
    BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
} BMX_BUS_ERR_Type;

/**
 *  @brief BMX bus err interrupt type definition
 */
typedef enum {
    BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
    BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
} BMX_ERR_INT_Type;

/**
 *  @brief BMX time out interrupt type definition
 */
typedef enum {
    BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
    BMX_TO_INT_ALL,     /*!< BMX timeout interrupt max num */
} BMX_TO_INT_Type;

/**
 *  @brief GLB EM type definition
 */
typedef enum {
    GLB_EM_0KB = 0x0,  /*!< 0x0 --> 0KB */
    GLB_EM_8KB = 0x3,  /*!< 0x3 --> 8KB */
    GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */
} GLB_EM_Type;

/**
 *  @brief GLB EMAC and CAM pin type definition
 */
typedef enum {
    GLB_EMAC_CAM_PIN_EMAC, /*!< select pin as emac */
    GLB_EMAC_CAM_PIN_CAM,  /*!< select pin as cam */
} GLB_EMAC_CAM_PIN_Type;

/**
 *  @brief GLB RTC clock type definition
 */
typedef enum {
    GLB_MTIMER_CLK_BCLK, /*!< BUS clock */
    GLB_MTIMER_CLK_32K,  /*!< 32KHz */
} GLB_MTIMER_CLK_Type;

/**
 *  @brief GLB ADC clock type definition
 */
typedef enum {
    GLB_ADC_CLK_AUDIO_PLL, /*!< use Audio PLL as ADC clock */
    GLB_ADC_CLK_XCLK,      /*!< use XCLK as ADC clock */
} GLB_ADC_CLK_Type;

/**
 *  @brief GLB DAC clock type definition
 */
typedef enum {
    GLB_DAC_CLK_PLL_32M,   /*!< select PLL 32M as DAC clock source */
    GLB_DAC_CLK_XCLK,      /*!< select XCLK as DAC clock source */
    GLB_DAC_CLK_AUDIO_PLL, /*!< select Audio PLL as DAC clock source */
} GLB_DAC_CLK_Type;

/**
 *  @brief GLB DIG clock source select type definition
 */
typedef enum {
    GLB_DIG_CLK_PLL_32M,   /*!< select PLL 32M as DIG clock source */
    GLB_DIG_CLK_XCLK,      /*!< select XCLK as DIG clock source */
    GLB_DIG_CLK_AUDIO_PLL, /*!< select Audio PLL as DIG clock source */
} GLB_DIG_CLK_Type;

/**
 *  @brief GLB BT bandwidth type definition
 */
typedef enum {
    GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
    GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
} GLB_BT_BANDWIDTH_Type;

/**
 *  @brief GLB UART signal type definition
 */
typedef enum {
    GLB_UART_SIG_0, /*!< UART signal 0 */
    GLB_UART_SIG_1, /*!< UART signal 1 */
    GLB_UART_SIG_2, /*!< UART signal 2 */
    GLB_UART_SIG_3, /*!< UART signal 3 */
    GLB_UART_SIG_4, /*!< UART signal 4 */
    GLB_UART_SIG_5, /*!< UART signal 5 */
    GLB_UART_SIG_6, /*!< UART signal 6 */
    GLB_UART_SIG_7, /*!< UART signal 7 */
} GLB_UART_SIG_Type;

/**
 *  @brief GLB UART signal  function type definition
 */
typedef enum {
    GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
    GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
    GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
    GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
    GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
    GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
    GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
    GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
} GLB_UART_SIG_FUN_Type;

/**
 *  @brief GLB DLL output clock type definition
 */
typedef enum {
    GLB_DLL_CLK_57P6M, /*!< DLL output 57P6M clock */
    GLB_DLL_CLK_96M,   /*!< DLL output 96M clock */
    GLB_DLL_CLK_144M,  /*!< DLL output 144M clock */
    GLB_DLL_CLK_288M,  /*!< DLL output 288M clock */
    GLB_DLL_CLK_MMDIV, /*!< DLL output mmdiv clock */
} GLB_DLL_CLK_Type;

/**
 *  @brief GLB GPIO interrupt trigger mode type definition
 */
typedef enum {
    GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */
    GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */
    GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */
    GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */
} GLB_GPIO_INT_TRIG_Type;

/**
 *  @brief GLB GPIO interrupt control mode type definition
 */
typedef enum {
    GLB_GPIO_INT_CONTROL_SYNC,  /*!< GPIO interrupt sync mode */
    GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */
} GLB_GPIO_INT_CONTROL_Type;

/**
 *  @brief PLL XTAL type definition
 */
typedef enum {
    GLB_DLL_XTAL_NONE,  /*!< XTAL is none */
    GLB_DLL_XTAL_32M,   /*!< XTAL is 32M */
    GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */
} GLB_DLL_XTAL_Type;

typedef enum {
    GLB_AHB_CLOCK_IP_CPU,
    GLB_AHB_CLOCK_IP_SDU,
    GLB_AHB_CLOCK_IP_SEC,
    GLB_AHB_CLOCK_IP_DMA_0,
    GLB_AHB_CLOCK_IP_DMA_1,
    GLB_AHB_CLOCK_IP_DMA_2,
    GLB_AHB_CLOCK_IP_CCI,
    GLB_AHB_CLOCK_IP_RF_TOP,
    GLB_AHB_CLOCK_IP_GPIP,
    GLB_AHB_CLOCK_IP_TZC,
    GLB_AHB_CLOCK_IP_EF_CTRL,
    GLB_AHB_CLOCK_IP_SF_CTRL,
    GLB_AHB_CLOCK_IP_EMAC,
    GLB_AHB_CLOCK_IP_UART0,
    GLB_AHB_CLOCK_IP_UART1,
    GLB_AHB_CLOCK_IP_UART2,
    GLB_AHB_CLOCK_IP_UART3,
    GLB_AHB_CLOCK_IP_UART4,
    GLB_AHB_CLOCK_IP_SPI,
    GLB_AHB_CLOCK_IP_I2C,
    GLB_AHB_CLOCK_IP_PWM,
    GLB_AHB_CLOCK_IP_TIMER,
    GLB_AHB_CLOCK_IP_IR,
    GLB_AHB_CLOCK_IP_CHECKSUM,
    GLB_AHB_CLOCK_IP_QDEC,
    GLB_AHB_CLOCK_IP_KYS,
    GLB_AHB_CLOCK_IP_I2S,
    GLB_AHB_CLOCK_IP_USB11,
    GLB_AHB_CLOCK_IP_CAM,
    GLB_AHB_CLOCK_IP_MJPEG,
    GLB_AHB_CLOCK_IP_BT_BLE_NORMAL,
    GLB_AHB_CLOCK_IP_BT_BLE_LP,
    GLB_AHB_CLOCK_IP_ZB_NORMAL,
    GLB_AHB_CLOCK_IP_ZB_LP,
    GLB_AHB_CLOCK_IP_WIFI_NORMAL,
    GLB_AHB_CLOCK_IP_WIFI_LP,
    GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL,
    GLB_AHB_CLOCK_IP_BT_BLE_2_LP,
    GLB_AHB_CLOCK_IP_EMI_MISC,
    GLB_AHB_CLOCK_IP_PSRAM0_CTRL,
    GLB_AHB_CLOCK_IP_PSRAM1_CTRL,
    GLB_AHB_CLOCK_IP_USB20,
    GLB_AHB_CLOCK_IP_MIX2,
    GLB_AHB_CLOCK_IP_AUDIO,
    GLB_AHB_CLOCK_IP_SDH,
} GLB_AHB_CLOCK_IP_Type;

/*@} end of group GLB_Public_Types */

/** @defgroup  GLB_Public_Constants
 *  @{
 */

/** @defgroup  GLB_ROOT_CLK_TYPE
 *  @{
 */
#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \
                                    ((type) == GLB_ROOT_CLK_XTAL) ||  \
                                    ((type) == GLB_ROOT_CLK_DLL))

/** @defgroup  GLB_SYS_CLK_TYPE
 *  @{
 */
#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) ||    \
                                   ((type) == GLB_SYS_CLK_XTAL) ||     \
                                   ((type) == GLB_SYS_CLK_DLL57P6M) || \
                                   ((type) == GLB_SYS_CLK_DLL96M) ||   \
                                   ((type) == GLB_SYS_CLK_DLL144M))

/** @defgroup  GLB_CAM_CLK_TYPE
 *  @{
 */
#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \
                                   ((type) == GLB_CAM_CLK_DLL96M))

/** @defgroup  GLB_I2S_OUT_REF_CLK_TYPE
 *  @{
 */
#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \
                                           ((type) == GLB_I2S_OUT_REF_CLK_SRC))

/** @defgroup  GLB_QDEC_CLK_TYPE
 *  @{
 */
#define IS_GLB_QDEC_CLK_TYPE(type) (((type) == GLB_QDEC_CLK_XCLK) || \
                                    ((type) == GLB_QDEC_CLK_F32K))

/** @defgroup  GLB_DMA_CLK_ID_TYPE
 *  @{
 */
#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH1) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH2) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH3) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH4) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH5) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH6) || \
                                      ((type) == GLB_DMA_CLK_DMA0_CH7))

/** @defgroup  GLB_IR_CLK_SRC_TYPE
 *  @{
 */
#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))

/** @defgroup  GLB_SFLASH_CLK_TYPE
 *  @{
 */
#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_144M) ||  \
                                      ((type) == GLB_SFLASH_CLK_XCLK) ||  \
                                      ((type) == GLB_SFLASH_CLK_57P6M) || \
                                      ((type) == GLB_SFLASH_CLK_72M) ||   \
                                      ((type) == GLB_SFLASH_CLK_BCLK) ||  \
                                      ((type) == GLB_SFLASH_CLK_96M))

/** @defgroup  GLB_CHIP_CLK_OUT_TYPE
 *  @{
 */
#define IS_GLB_CHIP_CLK_OUT_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_NONE) ||          \
                                        ((type) == GLB_CHIP_CLK_OUT_I2S_REF_CLK) ||   \
                                        ((type) == GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK) || \
                                        ((type) == GLB_CHIP_CLK_OUT_XTAL_SOC_32M))

/** @defgroup  GLB_ETH_REF_CLK_OUT_TYPE
 *  @{
 */
#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \
                                           ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M))

/** @defgroup  GLB_SPI_PAD_ACT_AS_TYPE
 *  @{
 */
#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
                                          ((type) == GLB_SPI_PAD_ACT_AS_MASTER))

/** @defgroup  GLB_PKA_CLK_TYPE
 *  @{
 */
#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \
                                   ((type) == GLB_PKA_CLK_DLL96M))

/** @defgroup  BMX_ARB_TYPE
 *  @{
 */
#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) ||         \
                               ((type) == BMX_ARB_ROUND_ROBIN) || \
                               ((type) == BMX_ARB_RANDOM))

/** @defgroup  BMX_BUS_ERR_TYPE
 *  @{
 */
#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
                                   ((type) == BMX_BUS_ERR_ADDR_DECODE))

/** @defgroup  BMX_ERR_INT_TYPE
 *  @{
 */
#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
                                   ((type) == BMX_ERR_INT_ALL))

/** @defgroup  BMX_TO_INT_TYPE
 *  @{
 */
#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
                                  ((type) == BMX_TO_INT_ALL))

/** @defgroup  GLB_EM_TYPE
 *  @{
 */
#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \
                              ((type) == GLB_EM_8KB) || \
                              ((type) == GLB_EM_16KB))

/** @defgroup  GLB_EMAC_CAM_PIN_TYPE
 *  @{
 */
#define IS_GLB_EMAC_CAM_PIN_TYPE(type) (((type) == GLB_EMAC_CAM_PIN_EMAC) || \
                                        ((type) == GLB_EMAC_CAM_PIN_CAM))

/** @defgroup  GLB_MTIMER_CLK_TYPE
 *  @{
 */
#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \
                                      ((type) == GLB_MTIMER_CLK_32K))

/** @defgroup  GLB_ADC_CLK_TYPE
 *  @{
 */
#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUDIO_PLL) || \
                                   ((type) == GLB_ADC_CLK_XCLK))

/** @defgroup  GLB_DAC_CLK_TYPE
 *  @{
 */
#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_PLL_32M) || \
                                   ((type) == GLB_DAC_CLK_XCLK) ||    \
                                   ((type) == GLB_DAC_CLK_AUDIO_PLL))

/** @defgroup  GLB_DIG_CLK_TYPE
 *  @{
 */
#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \
                                   ((type) == GLB_DIG_CLK_XCLK) ||    \
                                   ((type) == GLB_DIG_CLK_AUDIO_PLL))

/** @defgroup  GLB_BT_BANDWIDTH_TYPE
 *  @{
 */
#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
                                        ((type) == GLB_BT_BANDWIDTH_2M))

/** @defgroup  GLB_UART_SIG_TYPE
 *  @{
 */
#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
                                    ((type) == GLB_UART_SIG_1) || \
                                    ((type) == GLB_UART_SIG_2) || \
                                    ((type) == GLB_UART_SIG_3) || \
                                    ((type) == GLB_UART_SIG_4) || \
                                    ((type) == GLB_UART_SIG_5) || \
                                    ((type) == GLB_UART_SIG_6) || \
                                    ((type) == GLB_UART_SIG_7))

/** @defgroup  GLB_UART_SIG_FUN_TYPE
 *  @{
 */
#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
                                        ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
                                        ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
                                        ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
                                        ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
                                        ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
                                        ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
                                        ((type) == GLB_UART_SIG_FUN_UART1_RXD))

/** @defgroup  GLB_DLL_CLK_TYPE
 *  @{
 */
#define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_57P6M) || \
                                   ((type) == GLB_DLL_CLK_96M) ||   \
                                   ((type) == GLB_DLL_CLK_144M) ||  \
                                   ((type) == GLB_DLL_CLK_288M) ||  \
                                   ((type) == GLB_DLL_CLK_MMDIV))

/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
 *  @{
 */
#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \
                                         ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \
                                         ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \
                                         ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL))

/** @defgroup  GLB_GPIO_INT_CONTROL_TYPE
 *  @{
 */
#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \
                                            ((type) == GLB_GPIO_INT_CONTROL_ASYNC))

/** @defgroup  GLB_DLL_XTAL_TYPE
 *  @{
 */
#define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \
                                    ((type) == GLB_DLL_XTAL_32M) ||  \
                                    ((type) == GLB_DLL_XTAL_RC32M))

/*@} end of group GLB_Public_Constants */

/** @defgroup  GLB_Public_Macros
 *  @{
 */
#define UART_SIG_SWAP_GPIO0_GPIO7   0x01 /* GPIO0-7   uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_GPIO8_GPIO15  0x02 /* GPIO8-15  uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_NONE          0x00 /* GPIO0-22  uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */
#define JTAG_SIG_SWAP_GPIO0_GPIO3   0x01 /* GPIO0-3   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO4_GPIO7   0x02 /* GPIO4-7   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO8_GPIO11  0x04 /* GPIO8-11  E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_NONE          0x00 /* GPIO0-22  E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */

#define GLB_AHB_CLOCK_CPU             (0x0000000000000001UL)
#define GLB_AHB_CLOCK_SDU             (0x0000000000000002UL)
#define GLB_AHB_CLOCK_SEC             (0x0000000000000004UL)
#define GLB_AHB_CLOCK_DMA_0           (0x0000000000000008UL)
#define GLB_AHB_CLOCK_DMA_1           (0x0000000000000010UL)
#define GLB_AHB_CLOCK_DMA_2           (0x0000000000000020UL)
#define GLB_AHB_CLOCK_CCI             (0x0000000000000040UL)
#define GLB_AHB_CLOCK_RF_TOP          (0x0000000000000080UL)
#define GLB_AHB_CLOCK_GPIP            (0x0000000000000100UL)
#define GLB_AHB_CLOCK_TZC             (0x0000000000000200UL)
#define GLB_AHB_CLOCK_EF_CTRL         (0x0000000000000400UL)
#define GLB_AHB_CLOCK_SF_CTRL         (0x0000000000000800UL)
#define GLB_AHB_CLOCK_EMAC            (0x0000000000001000UL)
#define GLB_AHB_CLOCK_UART0           (0x0000000000002000UL)
#define GLB_AHB_CLOCK_UART1           (0x0000000000004000UL)
#define GLB_AHB_CLOCK_UART2           (0x0000000000008000UL)
#define GLB_AHB_CLOCK_UART3           (0x0000000000010000UL)
#define GLB_AHB_CLOCK_UART4           (0x0000000000020000UL)
#define GLB_AHB_CLOCK_SPI             (0x0000000000040000UL)
#define GLB_AHB_CLOCK_I2C             (0x0000000000080000UL)
#define GLB_AHB_CLOCK_PWM             (0x0000000000100000UL)
#define GLB_AHB_CLOCK_TIMER           (0x0000000000200000UL)
#define GLB_AHB_CLOCK_IR              (0x0000000000400000UL)
#define GLB_AHB_CLOCK_CHECKSUM        (0x0000000000800000UL)
#define GLB_AHB_CLOCK_QDEC            (0x0000000001000000UL)
#define GLB_AHB_CLOCK_KYS             (0x0000000002000000UL)
#define GLB_AHB_CLOCK_I2S             (0x0000000004000000UL)
#define GLB_AHB_CLOCK_USB11           (0x0000000008000000UL)
#define GLB_AHB_CLOCK_CAM             (0x0000000010000000UL)
#define GLB_AHB_CLOCK_MJPEG           (0x0000000020000000UL)
#define GLB_AHB_CLOCK_BT_BLE_NORMAL   (0x0000000040000000UL)
#define GLB_AHB_CLOCK_BT_BLE_LP       (0x0000000080000000UL)
#define GLB_AHB_CLOCK_ZB_NORMAL       (0x0000000100000000UL)
#define GLB_AHB_CLOCK_ZB_LP           (0x0000000200000000UL)
#define GLB_AHB_CLOCK_WIFI_NORMAL     (0x0000000400000000UL)
#define GLB_AHB_CLOCK_WIFI_LP         (0x0000000800000000UL)
#define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (0x0000001000000000UL)
#define GLB_AHB_CLOCK_BT_BLE_2_LP     (0x0000002000000000UL)
#define GLB_AHB_CLOCK_EMI_MISC        (0x0000004000000000UL)
#define GLB_AHB_CLOCK_PSRAM0_CTRL     (0x0000008000000000UL)
#define GLB_AHB_CLOCK_PSRAM1_CTRL     (0x0000010000000000UL)
#define GLB_AHB_CLOCK_USB20           (0x0000020000000000UL)
#define GLB_AHB_CLOCK_MIX2            (0x0000040000000000UL)
#define GLB_AHB_CLOCK_AUDIO           (0x0000080000000000UL)
#define GLB_AHB_CLOCK_SDH             (0x0000100000000000UL)

/*@} end of group GLB_Public_Macros */

/** @defgroup  GLB_Public_Functions
 *  @{
 */
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void BMX_ERR_IRQHandler(void);
void BMX_TO_IRQHandler(void);
void GPIO_INT0_IRQHandler(void);
#endif
/*----------*/
GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void);
BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv);
uint8_t GLB_Get_BCLK_Div(void);
uint8_t GLB_Get_HCLK_Div(void);
BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType);
BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq);
BL_Err_Type System_Core_Clock_Update_From_RC32M(void);
/*----------*/
BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div);
BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable);
BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable);
BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef);
BL_Err_Type GLB_Set_USB_CLK(uint8_t enable);
BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk);
BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div);
BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div);
BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div);
BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable);
BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable);
BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div);
BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable);
BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable);
BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel);
/*----------*/
BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
BL_Err_Type GLB_SW_System_Reset(void);
BL_Err_Type GLB_SW_CPU_Reset(void);
BL_Err_Type GLB_SW_POR_Reset(void);
BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1);
BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1);
uint64_t GLB_PER_Clock_Gate_Status_Get(void);
BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips);
BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips);
/*----------*/
BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg);
BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void);
BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void);
BL_Err_Type GLB_BMX_BusErrResponse_Enable(void);
BL_Err_Type GLB_BMX_BusErrResponse_Disable(void);
BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType);
uint32_t GLB_BMX_Get_Err_Addr(void);
BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun);
/*----------*/
BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
uint32_t GLB_Get_SRAM_RET(void);
BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value);
uint32_t GLB_Get_SRAM_SLP(void);
BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value);
uint32_t GLB_Get_SRAM_PARM(void);
/*----------*/
BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType);
/*----------*/
BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType);
BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable);
BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable);
BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel);
BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel);
BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable);
BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable);
BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
BL_Err_Type GLB_Select_Internal_Flash(void);
BL_Err_Type GLB_Select_External_Flash(void);
BL_Err_Type GLB_Deswap_Flash_Pin(void);
BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin();
BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin();
BL_Err_Type GLB_Swap_Flash_Pin(void);
BL_Err_Type GLB_Select_Internal_PSram(void);
/*----------*/
BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div);
/*----------*/
BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div);
BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel);
BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth,
                                   uint8_t pti, uint8_t channel);
/*----------*/
BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun);
/*----------*/
BL_Err_Type GLB_Power_Off_DLL(void);
BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType);
BL_Err_Type GLB_Enable_DLL_All_Clks(void);
BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
BL_Err_Type GLB_Disable_DLL_All_Clks(void);
BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
/*----------*/
BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio);
BL_Err_Type GLB_IR_LED_Driver_Enable(void);
BL_Err_Type GLB_IR_LED_Driver_Disable(void);
BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio);
BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio);
BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias);
/*----------*/
BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Set_Flash_Pad_HZ(void);
BL_Err_Type GLB_Set_Psram_Pad_HZ(void);
uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
                                GLB_GPIO_INT_TRIG_Type intTrgMod);
GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
                                 GLB_GPIO_INT_TRIG_Type intTrgMod);
GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
/*----------*/;

/*@} end of group GLB_Public_Functions */

/*@} end of group GLB */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_GLB_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_gpio.h
================================================
/**

  ******************************************************************************

  * @file    bl702_gpio.h

  * @version V1.2

  * @date    2020-09-04

  * @brief   This file is the description of.IP register

  ******************************************************************************

  * @attention

  *

  * 
© COPYRIGHT(c) 2020 Bouffalo Lab


  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of Bouffalo Lab nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

#ifndef __BL702_GPIO_H__
#define __BL702_GPIO_H__

typedef enum {
  GLB_GPIO_PIN_0 = 0,
  GLB_GPIO_PIN_1,
  GLB_GPIO_PIN_2,
  GLB_GPIO_PIN_3,
  GLB_GPIO_PIN_4,
  GLB_GPIO_PIN_5,
  GLB_GPIO_PIN_6,
  GLB_GPIO_PIN_7,
  GLB_GPIO_PIN_8,
  GLB_GPIO_PIN_9,
  GLB_GPIO_PIN_10,
  GLB_GPIO_PIN_11,
  GLB_GPIO_PIN_12,
  GLB_GPIO_PIN_13,
  GLB_GPIO_PIN_14,
  GLB_GPIO_PIN_15,
  GLB_GPIO_PIN_16,
  GLB_GPIO_PIN_17,
  GLB_GPIO_PIN_18,
  GLB_GPIO_PIN_19,
  GLB_GPIO_PIN_20,
  GLB_GPIO_PIN_21,
  GLB_GPIO_PIN_22,
  GLB_GPIO_PIN_23,
  GLB_GPIO_PIN_24,
  GLB_GPIO_PIN_25,
  GLB_GPIO_PIN_26,
  GLB_GPIO_PIN_27,
  GLB_GPIO_PIN_28,
  GLB_GPIO_PIN_29,
  GLB_GPIO_PIN_30,
  GLB_GPIO_PIN_31,
  GLB_GPIO_PIN_MAX,
} GLB_GPIO_Type;

#define GPIO_MODE_INPUT  ((uint32_t)0x00000000U) /*!< Input Floating Mode                   */
#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode                 */
#define GPIO_MODE_AF     ((uint32_t)0x00000002U) /*!< Alternate function                    */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function                       */
#define GPIO_PULL_UP     ((uint32_t)0x00000000U) /*!< GPIO pull up                          */
#define GPIO_PULL_DOWN   ((uint32_t)0x00000001U) /*!< GPIO pull down                        */
#define GPIO_PULL_NONE   ((uint32_t)0x00000002U) /*!< GPIO no pull up or down               */

typedef enum {
  GPIO_FUN_CLK_OUT                = 0,
  GPIO_FUN_BT_COEXIST             = 1,
  GPIO_FUN_FLASH_PSRAM            = 2,
  GPIO_FUN_QSPI                   = 2,
  GPIO_FUN_I2S                    = 3,
  GPIO_FUN_SPI                    = 4,
  GPIO_FUN_I2C                    = 6,
  GPIO_FUN_UART                   = 7,
  GPIO_FUN_PWM                    = 8,
  GPIO_FUN_CAM                    = 9,
  GPIO_FUN_ANALOG                 = 10,
  GPIO_FUN_GPIO                   = 11,
  GPIO_FUN_RF_TEST                = 12,
  GPIO_FUN_SCAN                   = 13,
  GPIO_FUN_E21_JTAG               = 14,
  GPIO_FUN_DEBUG                  = 15,
  GPIO_FUN_EXTERNAL_PA            = 16,
  GPIO_FUN_USB_TRANCEIVER         = 17,
  GPIO_FUN_USB_CONTROLLER         = 18,
  GPIO_FUN_ETHER_MAC              = 19,
  GPIO_FUN_EMAC                   = 19,
  GPIO_FUN_QDEC                   = 20,
  GPIO_FUN_KEY_SCAN_IN            = 21,
  GPIO_FUN_KEY_SCAN_ROW           = 21,
  GPIO_FUN_KEY_SCAN_DRIVE         = 22,
  GPIO_FUN_KEY_SCAN_COL           = 22,
  GPIO_FUN_CAM_MISC               = 23,
  GPIO_FUN_USB                    = 0xD0,
  GPIO_FUN_DAC                    = 0xD1,
  GPIO_FUN_ADC                    = 0xD2,
  GPIO_FUN_QDEC_LED               = 0xD3,
  GPIO_FUN_GPIO_OUTPUT_UP         = 0xE0,
  GPIO_FUN_GPIO_OUTPUT_DOWN       = 0xE1,
  GPIO_FUN_GPIO_OUTPUT_NONE       = 0xE2,
  GPIO_FUN_GPIO_INPUT_UP          = 0xE3,
  GPIO_FUN_GPIO_INPUT_DOWN        = 0xE4,
  GPIO_FUN_GPIO_INPUT_NONE        = 0xE5,
  GPIO_FUN_GPIO_EXTI_RISING_EDGE  = 0xE6,
  GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xE7,
  GPIO_FUN_GPIO_EXTI_HIGH_LEVEL   = 0xE8,
  GPIO_FUN_GPIO_EXTI_LOW_LEVEL    = 0xE9,
  GPIO_FUN_UART0_RTS              = 0xF0,
  GPIO_FUN_UART0_CTS              = 0xF1,
  GPIO_FUN_UART0_TX               = 0xF2,
  GPIO_FUN_UART0_RX               = 0xF3,
  GPIO_FUN_UART1_RTS              = 0xF4,
  GPIO_FUN_UART1_CTS              = 0xF5,
  GPIO_FUN_UART1_TX               = 0xF6,
  GPIO_FUN_UART1_RX               = 0xF7,
  GPIO_FUN_WAKEUP                 = 0xFE,
  GPIO_FUN_UNUSED                 = 0xFF
} GLB_GPIO_FUNC_Type;

typedef struct {
  uint8_t gpioPin;
  uint8_t gpioFun;
  uint8_t gpioMode;
  uint8_t pullType;
  uint8_t drive;
  uint8_t smtCtrl; // Schmitt trigger
} GLB_GPIO_Cfg_Type;

/* GPIO0 function definition */
#define GPIO0_FUN_CLK_OUT_0             0
#define GPIO0_FUN_BT_ABORT              1
#define GPIO0_FUN_UNUSED2               2
#define GPIO0_FUN_I2S0_BCLK             3
#define GPIO0_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO0_FUN_I2C0_SCL              6
#define GPIO0_FUN_UART_SIG0_UART_SIG4   7
#define GPIO0_FUN_PWM_CH0               8
#define GPIO0_FUN_PIX_CLK               9
#define GPIO0_FUN_UNUSED10              10
#define GPIO0_FUN_REG_GPIO_0            11
#define GPIO0_FUN_UNUSED12              12
#define GPIO0_FUN_SCAN_IN_0             13
#define GPIO0_FUN_E21_TMS_E21_TCK       14
#define GPIO0_FUN_S_CCI_CLK             15
#define GPIO0_FUN_FEM_GPIO_0            16
#define GPIO0_FUN_USB_TX_DN_USB_RX_DN   17
#define GPIO0_FUN_USB_SUS               18
#define GPIO0_FUN_MII_REF_CLK           19
#define GPIO0_FUN_QDEC0_A               20
#define GPIO0_FUN_ROW_I_0               21
#define GPIO0_FUN_COL_O_0               22
#define GPIO0_FUN_CAM_PWRDN             23
/* GPIO1 function definition */
#define GPIO1_FUN_CLK_OUT_1             0
#define GPIO1_FUN_BT_ACTIVE             1
#define GPIO1_FUN_UNUSED2               2
#define GPIO1_FUN_I2S0_FS               3
#define GPIO1_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO1_FUN_I2C0_SDA              6
#define GPIO1_FUN_UART_SIG1_UART_SIG5   7
#define GPIO1_FUN_PWM_CH1               8
#define GPIO1_FUN_FRAME_VLD             9
#define GPIO1_FUN_UNUSED10              10
#define GPIO1_FUN_REG_GPIO_1            11
#define GPIO1_FUN_UNUSED12              12
#define GPIO1_FUN_SCAN_IN_1             13
#define GPIO1_FUN_E21_TDI_E21_TDO       14
#define GPIO1_FUN_S_CCI_CS              15
#define GPIO1_FUN_FEM_GPIO_1            16
#define GPIO1_FUN_USB_TX_OE             17
#define GPIO1_FUN_USB_ENUM              18
#define GPIO1_FUN_MII_TXD_0             19
#define GPIO1_FUN_QDEC0_B               20
#define GPIO1_FUN_ROW_I_1               21
#define GPIO1_FUN_COL_O_1               22
#define GPIO1_FUN_CAM_REF_CLK           23
/* GPIO2 function definition */
#define GPIO2_FUN_CLK_OUT_0           0
#define GPIO2_FUN_BT_PRI              1
#define GPIO2_FUN_UNUSED2             2
#define GPIO2_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO2_FUN_SPI_0_SS            4
#define GPIO2_FUN_I2C0_SCL            6
#define GPIO2_FUN_UART_SIG2_UART_SIG6 7
#define GPIO2_FUN_PWM_CH2             8
#define GPIO2_FUN_LINE_VLD            9
#define GPIO2_FUN_UNUSED10            10
#define GPIO2_FUN_REG_GPIO_2          11
#define GPIO2_FUN_UNUSED12            12
#define GPIO2_FUN_SCAN_IN_2           13
#define GPIO2_FUN_E21_TCK_E21_TMS     14
#define GPIO2_FUN_S_CCI_DATA_0        15
#define GPIO2_FUN_FEM_GPIO_2          16
#define GPIO2_FUN_USB_TX_DP_USB_RX_DP 17
#define GPIO2_FUN_USB_OEB             18
#define GPIO2_FUN_MII_TXD_1           19
#define GPIO2_FUN_QDEC0_LED           20
#define GPIO2_FUN_ROW_I_2             21
#define GPIO2_FUN_COL_O_2             22
#define GPIO2_FUN_CAM_RESET           23
/* GPIO3 function definition */
#define GPIO3_FUN_CLK_OUT_1           0
#define GPIO3_FUN_BT_ABORT            1
#define GPIO3_FUN_UNUSED2             2
#define GPIO3_FUN_I2S0_RCLK_O_I2S0_DI 3
#define GPIO3_FUN_SPI_0_SCLK          4
#define GPIO3_FUN_I2C0_SDA            6
#define GPIO3_FUN_UART_SIG3_UART_SIG7 7
#define GPIO3_FUN_PWM_CH3             8
#define GPIO3_FUN_PIX_DAT0            9
#define GPIO3_FUN_UNUSED10            10
#define GPIO3_FUN_REG_GPIO_3          11
#define GPIO3_FUN_RF_TEST_0           12
#define GPIO3_FUN_UNUSED13            13
#define GPIO3_FUN_E21_TDO_E21_TDI     14
#define GPIO3_FUN_DEBUG_0             15
#define GPIO3_FUN_FEM_GPIO_3          16
#define GPIO3_FUN_USB_SUS_EXT         17
#define GPIO3_FUN_VOP                 18
#define GPIO3_FUN_UNUSED19            19
#define GPIO3_FUN_QDEC1_A             20
#define GPIO3_FUN_ROW_I_3             21
#define GPIO3_FUN_COL_O_3             22
#define GPIO3_FUN_CAM_PWRDN           23
/* GPIO4 function definition */
#define GPIO4_FUN_CLK_OUT_0             0
#define GPIO4_FUN_BT_ACTIVE             1
#define GPIO4_FUN_UNUSED2               2
#define GPIO4_FUN_I2S0_BCLK             3
#define GPIO4_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO4_FUN_I2C0_SCL              6
#define GPIO4_FUN_UART_SIG4_UART_SIG0   7
#define GPIO4_FUN_PWM_CH4               8
#define GPIO4_FUN_PIX_DAT1              9
#define GPIO4_FUN_UNUSED10              10
#define GPIO4_FUN_REG_GPIO_4            11
#define GPIO4_FUN_RF_TEST_1             12
#define GPIO4_FUN_UNUSED13              13
#define GPIO4_FUN_E21_TMS_E21_TCK       14
#define GPIO4_FUN_DEBUG_1               15
#define GPIO4_FUN_FEM_GPIO_4            16
#define GPIO4_FUN_USB_ENUM_EXT          17
#define GPIO4_FUN_VOM                   18
#define GPIO4_FUN_UNUSED19              19
#define GPIO4_FUN_QDEC1_B               20
#define GPIO4_FUN_ROW_I_4               21
#define GPIO4_FUN_COL_O_4               22
#define GPIO4_FUN_CAM_REF_CLK           23
/* GPIO5 function definition */
#define GPIO5_FUN_CLK_OUT_1             0
#define GPIO5_FUN_BT_PRI                1
#define GPIO5_FUN_UNUSED2               2
#define GPIO5_FUN_I2S0_FS               3
#define GPIO5_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO5_FUN_I2C0_SDA              6
#define GPIO5_FUN_UART_SIG5_UART_SIG1   7
#define GPIO5_FUN_PWM_CH0               8
#define GPIO5_FUN_PIX_DAT2              9
#define GPIO5_FUN_UNUSED10              10
#define GPIO5_FUN_REG_GPIO_5            11
#define GPIO5_FUN_RF_TEST_2             12
#define GPIO5_FUN_UNUSED13              13
#define GPIO5_FUN_E21_TDI_E21_TDO       14
#define GPIO5_FUN_DEBUG_2               15
#define GPIO5_FUN_FEM_GPIO_0            16
#define GPIO5_FUN_USB_TX_DN_USB_RX_DN   17
#define GPIO5_FUN_BD                    18
#define GPIO5_FUN_UNUSED19              19
#define GPIO5_FUN_QDEC1_LED             20
#define GPIO5_FUN_ROW_I_5               21
#define GPIO5_FUN_COL_O_5               22
#define GPIO5_FUN_CAM_RESET             23
/* GPIO6 function definition */
#define GPIO6_FUN_CLK_OUT_0           0
#define GPIO6_FUN_BT_ABORT            1
#define GPIO6_FUN_UNUSED2             2
#define GPIO6_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO6_FUN_SPI_0_SS            4
#define GPIO6_FUN_I2C0_SCL            6
#define GPIO6_FUN_UART_SIG6_UART_SIG2 7
#define GPIO6_FUN_PWM_CH1             8
#define GPIO6_FUN_PIX_DAT3            9
#define GPIO6_FUN_UNUSED10            10
#define GPIO6_FUN_REG_GPIO_6          11
#define GPIO6_FUN_RF_TEST_3           12
#define GPIO6_FUN_UNUSED13            13
#define GPIO6_FUN_E21_TCK_E21_TMS     14
#define GPIO6_FUN_DEBUG_3             15
#define GPIO6_FUN_FEM_GPIO_1          16
#define GPIO6_FUN_USB_TX_OE           17
#define GPIO6_FUN_VIP                 18
#define GPIO6_FUN_UNUSED19            19
#define GPIO6_FUN_QDEC2_A             20
#define GPIO6_FUN_ROW_I_6             21
#define GPIO6_FUN_COL_O_6             22
#define GPIO6_FUN_CAM_PWRDN           23
/* GPIO7 function definition */
#define GPIO7_FUN_CLK_OUT_1                       0
#define GPIO7_FUN_BT_ACTIVE                       1
#define GPIO7_FUN_UNUSED2                         2
#define GPIO7_FUN_I2S0_RCLK_O_I2S0_DI             3
#define GPIO7_FUN_SPI_0_SCLK                      4
#define GPIO7_FUN_I2C0_SDA                        6
#define GPIO7_FUN_UART_SIG7_UART_SIG3             7
#define GPIO7_FUN_PWM_CH2                         8
#define GPIO7_FUN_UNUSED9                         9
#define GPIO7_FUN_USB_DP_GPIP_CH_6_GPDAC_VREF_EXT 10
#define GPIO7_FUN_REG_GPIO_7                      11
#define GPIO7_FUN_UNUSED12                        12
#define GPIO7_FUN_SCAN_RSTB                       13
#define GPIO7_FUN_E21_TDO_E21_TDI                 14
#define GPIO7_FUN_S_CCI_DATA_1                    15
#define GPIO7_FUN_FEM_GPIO_2                      16
#define GPIO7_FUN_USB_TX_DP_USB_RX_DP             17
#define GPIO7_FUN_VIM                             18
#define GPIO7_FUN_MII_RXD_0                       19
#define GPIO7_FUN_QDEC2_B                         20
#define GPIO7_FUN_ROW_I_7                         21
#define GPIO7_FUN_COL_O_7                         22
#define GPIO7_FUN_CAM_REF_CLK                     23
/* GPIO8 function definition */
#define GPIO8_FUN_CLK_OUT_0             0
#define GPIO8_FUN_BT_PRI                1
#define GPIO8_FUN_UNUSED2               2
#define GPIO8_FUN_I2S0_BCLK             3
#define GPIO8_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO8_FUN_I2C0_SCL              6
#define GPIO8_FUN_UART_SIG0_UART_SIG4   7
#define GPIO8_FUN_PWM_CH3               8
#define GPIO8_FUN_UNUSED9               9
#define GPIO8_FUN_USB_DM_GPIP_CH_0      10
#define GPIO8_FUN_REG_GPIO_8            11
#define GPIO8_FUN_RF_TEST_4             12
#define GPIO8_FUN_SCAN_CLK              13
#define GPIO8_FUN_E21_TMS_E21_TCK       14
#define GPIO8_FUN_DEBUG_4               15
#define GPIO8_FUN_FEM_GPIO_3            16
#define GPIO8_FUN_USB_SUS_EXT           17
#define GPIO8_FUN_RCV                   18
#define GPIO8_FUN_MII_RXD_1             19
#define GPIO8_FUN_QDEC2_LED             20
#define GPIO8_FUN_ROW_I_0               21
#define GPIO8_FUN_COL_O_8               22
#define GPIO8_FUN_CAM_RESET             23
/* GPIO9 function definition */
#define GPIO9_FUN_CLK_OUT_1                         0
#define GPIO9_FUN_BT_ABORT                          1
#define GPIO9_FUN_UNUSED2                           2
#define GPIO9_FUN_I2S0_FS                           3
#define GPIO9_FUN_SPI_0_MISO_SPI_0_MOSI             4
#define GPIO9_FUN_I2C0_SDA                          6
#define GPIO9_FUN_UART_SIG1_UART_SIG5               7
#define GPIO9_FUN_PWM_CH4                           8
#define GPIO9_FUN_UNUSED9                           9
#define GPIO9_FUN_PMIP_DC_TP_CLKPLL_DC_TP_GPIP_CH_7 10
#define GPIO9_FUN_REG_GPIO_9                        11
#define GPIO9_FUN_RF_TEST_5                         12
#define GPIO9_FUN_SCAN_EN                           13
#define GPIO9_FUN_E21_TDI_E21_TDO                   14
#define GPIO9_FUN_DEBUG_5                           15
#define GPIO9_FUN_FEM_GPIO_4                        16
#define GPIO9_FUN_USB_ENUM_EXT                      17
#define GPIO9_FUN_USB_SUS                           18
#define GPIO9_FUN_UNUSED19                          19
#define GPIO9_FUN_QDEC0_A                           20
#define GPIO9_FUN_ROW_I_1                           21
#define GPIO9_FUN_COL_O_9                           22
#define GPIO9_FUN_CAM_PWRDN                         23
/* GPIO10 function definition */
#define GPIO10_FUN_CLK_OUT_0           0
#define GPIO10_FUN_BT_ACTIVE           1
#define GPIO10_FUN_UNUSED2             2
#define GPIO10_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO10_FUN_SPI_0_SS            4
#define GPIO10_FUN_I2C0_SCL            6
#define GPIO10_FUN_UART_SIG2_UART_SIG6 7
#define GPIO10_FUN_PWM_CH0             8
#define GPIO10_FUN_UNUSED9             9
#define GPIO10_FUN_MICBIAS             10
#define GPIO10_FUN_REG_GPIO_10         11
#define GPIO10_FUN_RF_TEST_6           12
#define GPIO10_FUN_UNUSED13            13
#define GPIO10_FUN_E21_TCK_E21_TMS     14
#define GPIO10_FUN_DEBUG_6             15
#define GPIO10_FUN_FEM_GPIO_0          16
#define GPIO10_FUN_USB_TX_DN_USB_RX_DN 17
#define GPIO10_FUN_USB_ENUM            18
#define GPIO10_FUN_UNUSED19            19
#define GPIO10_FUN_QDEC0_B             20
#define GPIO10_FUN_ROW_I_2             21
#define GPIO10_FUN_COL_O_10            22
#define GPIO10_FUN_CAM_REF_CLK         23
/* GPIO11 function definition */
#define GPIO11_FUN_CLK_OUT_1           0
#define GPIO11_FUN_BT_PRI              1
#define GPIO11_FUN_UNUSED2             2
#define GPIO11_FUN_I2S0_RCLK_O_I2S0_DI 3
#define GPIO11_FUN_SPI_0_SCLK          4
#define GPIO11_FUN_I2C0_SDA            6
#define GPIO11_FUN_UART_SIG3_UART_SIG7 7
#define GPIO11_FUN_PWM_CH1             8
#define GPIO11_FUN_UNUSED9             9
#define GPIO11_FUN_GPIP_CH_3           10
#define GPIO11_FUN_REG_GPIO_11         11
#define GPIO11_FUN_RF_TEST_7           12
#define GPIO11_FUN_UNUSED13            13
#define GPIO11_FUN_E21_TDO_E21_TDI     14
#define GPIO11_FUN_DEBUG_7             15
#define GPIO11_FUN_FEM_GPIO_1          16
#define GPIO11_FUN_USB_TX_OE           17
#define GPIO11_FUN_USB_OEB             18
#define GPIO11_FUN_UNUSED19            19
#define GPIO11_FUN_QDEC0_LED           20
#define GPIO11_FUN_ROW_I_3             21
#define GPIO11_FUN_COL_O_11            22
#define GPIO11_FUN_CAM_RESET           23
/* GPIO12 function definition */
#define GPIO12_FUN_CLK_OUT_0             0
#define GPIO12_FUN_BT_ABORT              1
#define GPIO12_FUN_UNUSED2               2
#define GPIO12_FUN_I2S0_BCLK             3
#define GPIO12_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO12_FUN_I2C0_SCL              6
#define GPIO12_FUN_UART_SIG4_UART_SIG0   7
#define GPIO12_FUN_PWM_CH2               8
#define GPIO12_FUN_PIX_DAT4              9
#define GPIO12_FUN_GPIP_CH_4             10
#define GPIO12_FUN_REG_GPIO_12           11
#define GPIO12_FUN_RF_TEST_8             12
#define GPIO12_FUN_UNUSED13              13
#define GPIO12_FUN_E21_TMS_E21_TCK       14
#define GPIO12_FUN_DEBUG_8               15
#define GPIO12_FUN_FEM_GPIO_2            16
#define GPIO12_FUN_USB_TX_DP_USB_RX_DP   17
#define GPIO12_FUN_VOP                   18
#define GPIO12_FUN_UNUSED19              19
#define GPIO12_FUN_QDEC1_A               20
#define GPIO12_FUN_ROW_I_4               21
#define GPIO12_FUN_COL_O_12              22
#define GPIO12_FUN_CAM_PWRDN             23
/* GPIO13 function definition */
#define GPIO13_FUN_CLK_OUT_1             0
#define GPIO13_FUN_BT_ACTIVE             1
#define GPIO13_FUN_UNUSED2               2
#define GPIO13_FUN_I2S0_FS               3
#define GPIO13_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO13_FUN_I2C0_SDA              6
#define GPIO13_FUN_UART_SIG5_UART_SIG1   7
#define GPIO13_FUN_PWM_CH3               8
#define GPIO13_FUN_UNUSED9               9
#define GPIO13_FUN_UNUSED10              10
#define GPIO13_FUN_REG_GPIO_13           11
#define GPIO13_FUN_UNUSED12              12
#define GPIO13_FUN_UNUSED13              13
#define GPIO13_FUN_E21_TDI_E21_TDO       14
#define GPIO13_FUN_DEBUG_9               15
#define GPIO13_FUN_FEM_GPIO_3            16
#define GPIO13_FUN_USB_SUS_EXT           17
#define GPIO13_FUN_VOM                   18
#define GPIO13_FUN_UNUSED19              19
#define GPIO13_FUN_QDEC1_B               20
#define GPIO13_FUN_ROW_I_5               21
#define GPIO13_FUN_COL_O_13              22
#define GPIO13_FUN_CAM_REF_CLK           23
/* GPIO14 function definition */
#define GPIO14_FUN_CLK_OUT_0             0
#define GPIO14_FUN_BT_PRI                1
#define GPIO14_FUN_UNUSED2               2
#define GPIO14_FUN_I2S0_DIO_I2S0_DO      3
#define GPIO14_FUN_SPI_0_SS              4
#define GPIO14_FUN_I2C0_SCL              6
#define GPIO14_FUN_UART_SIG6_UART_SIG2   7
#define GPIO14_FUN_PWM_CH4               8
#define GPIO14_FUN_UNUSED9               9
#define GPIO14_FUN_GPIP_CH_5_ATEST_OUT_0 10
#define GPIO14_FUN_REG_GPIO_14           11
#define GPIO14_FUN_RF_TEST_9             12
#define GPIO14_FUN_SCAN_OUT_0            13
#define GPIO14_FUN_E21_TCK_E21_TMS       14
#define GPIO14_FUN_DEBUG_10              15
#define GPIO14_FUN_FEM_GPIO_4            16
#define GPIO14_FUN_USB_ENUM_EXT          17
#define GPIO14_FUN_BD                    18
#define GPIO14_FUN_UNUSED19              19
#define GPIO14_FUN_QDEC1_LED             20
#define GPIO14_FUN_ROW_I_6               21
#define GPIO14_FUN_COL_O_14              22
#define GPIO14_FUN_CAM_RESET             23
/* GPIO15 function definition */
#define GPIO15_FUN_CLK_OUT_1             0
#define GPIO15_FUN_BT_ABORT              1
#define GPIO15_FUN_UNUSED2               2
#define GPIO15_FUN_I2S0_RCLK_O_I2S0_DI   3
#define GPIO15_FUN_SPI_0_SCLK            4
#define GPIO15_FUN_I2C0_SDA              6
#define GPIO15_FUN_UART_SIG7_UART_SIG3   7
#define GPIO15_FUN_PWM_CH0               8
#define GPIO15_FUN_UNUSED9               9
#define GPIO15_FUN_GPIP_CH_1_ATEST_OUT_1 10
#define GPIO15_FUN_REG_GPIO_15           11
#define GPIO15_FUN_RF_TEST_10            12
#define GPIO15_FUN_SCAN_OUT_1            13
#define GPIO15_FUN_E21_TDO_E21_TDI       14
#define GPIO15_FUN_DEBUG_11              15
#define GPIO15_FUN_FEM_GPIO_0            16
#define GPIO15_FUN_USB_TX_DN_USB_RX_DN   17
#define GPIO15_FUN_VIP                   18
#define GPIO15_FUN_UNUSED19              19
#define GPIO15_FUN_QDEC2_A               20
#define GPIO15_FUN_ROW_I_7               21
#define GPIO15_FUN_COL_O_15              22
#define GPIO15_FUN_CAM_PWRDN             23
/* GPIO16 function definition */
#define GPIO16_FUN_CLK_OUT_0             0
#define GPIO16_FUN_BT_ACTIVE             1
#define GPIO16_FUN_UNUSED2               2
#define GPIO16_FUN_I2S0_BCLK             3
#define GPIO16_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO16_FUN_I2C0_SCL              6
#define GPIO16_FUN_UART_SIG0_UART_SIG4   7
#define GPIO16_FUN_PWM_CH1               8
#define GPIO16_FUN_UNUSED9               9
#define GPIO16_FUN_UNUSED10              10
#define GPIO16_FUN_REG_GPIO_16           11
#define GPIO16_FUN_RF_TEST_11            12
#define GPIO16_FUN_UNUSED13              13
#define GPIO16_FUN_E21_TMS_E21_TCK       14
#define GPIO16_FUN_DEBUG_12              15
#define GPIO16_FUN_FEM_GPIO_1            16
#define GPIO16_FUN_USB_TX_OE             17
#define GPIO16_FUN_VIM                   18
#define GPIO16_FUN_UNUSED19              19
#define GPIO16_FUN_QDEC2_B               20
#define GPIO16_FUN_ROW_I_0               21
#define GPIO16_FUN_COL_O_16              22
#define GPIO16_FUN_CAM_REF_CLK           23
/* GPIO17 function definition */
#define GPIO17_FUN_CLK_OUT_1             0
#define GPIO17_FUN_BT_PRI                1
#define GPIO17_FUN_SF_IO_0_SF2_CS2       2
#define GPIO17_FUN_I2S0_FS               3
#define GPIO17_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO17_FUN_I2C0_SDA              6
#define GPIO17_FUN_UART_SIG1_UART_SIG5   7
#define GPIO17_FUN_PWM_CH2               8
#define GPIO17_FUN_PIX_DAT4              9
#define GPIO17_FUN_GPIP_CH_2_PSW_IRRCV   10
#define GPIO17_FUN_REG_GPIO_17           11
#define GPIO17_FUN_RF_TEST_12            12
#define GPIO17_FUN_SCAN_OUT_2            13
#define GPIO17_FUN_E21_TDI_E21_TDO       14
#define GPIO17_FUN_DEBUG_13              15
#define GPIO17_FUN_FEM_GPIO_2            16
#define GPIO17_FUN_USB_TX_DP_USB_RX_DP   17
#define GPIO17_FUN_RCV                   18
#define GPIO17_FUN_UNUSED19              19
#define GPIO17_FUN_QDEC2_LED             20
#define GPIO17_FUN_ROW_I_1               21
#define GPIO17_FUN_COL_O_17              22
#define GPIO17_FUN_CAM_RESET             23
/* GPIO18 function definition */
#define GPIO18_FUN_CLK_OUT_0           0
#define GPIO18_FUN_BT_ABORT            1
#define GPIO18_FUN_SF_IO_1             2
#define GPIO18_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO18_FUN_SPI_0_SS            4
#define GPIO18_FUN_I2C0_SCL            6
#define GPIO18_FUN_UART_SIG2_UART_SIG6 7
#define GPIO18_FUN_PWM_CH3             8
#define GPIO18_FUN_PIX_DAT5            9
#define GPIO18_FUN_GPIP_CH_8           10
#define GPIO18_FUN_REG_GPIO_18         11
#define GPIO18_FUN_RF_TEST_13          12
#define GPIO18_FUN_UNUSED13            13
#define GPIO18_FUN_E21_TCK_E21_TMS     14
#define GPIO18_FUN_M_CCI_CLK_DEBUG_14  15
#define GPIO18_FUN_FEM_GPIO_3          16
#define GPIO18_FUN_USB_SUS_EXT         17
#define GPIO18_FUN_USB_SUS             18
#define GPIO18_FUN_RMII_MDC            19
#define GPIO18_FUN_QDEC0_A             20
#define GPIO18_FUN_ROW_I_2             21
#define GPIO18_FUN_COL_O_18            22
#define GPIO18_FUN_CAM_PWRDN           23
/* GPIO19 function definition */
#define GPIO19_FUN_CLK_OUT_1           0
#define GPIO19_FUN_BT_ACTIVE           1
#define GPIO19_FUN_SF_CS               2
#define GPIO19_FUN_I2S0_RCLK_O_I2S0_DI 3
#define GPIO19_FUN_SPI_0_SCLK          4
#define GPIO19_FUN_I2C0_SDA            6
#define GPIO19_FUN_UART_SIG3_UART_SIG7 7
#define GPIO19_FUN_PWM_CH4             8
#define GPIO19_FUN_PIX_DAT6            9
#define GPIO19_FUN_GPIP_CH_9           10
#define GPIO19_FUN_REG_GPIO_19         11
#define GPIO19_FUN_RF_TEST_14          12
#define GPIO19_FUN_UNUSED13            13
#define GPIO19_FUN_E21_TDO_E21_TDI     14
#define GPIO19_FUN_M_CCI_CS_DEBUG_15   15
#define GPIO19_FUN_FEM_GPIO_4          16
#define GPIO19_FUN_USB_ENUM_EXT        17
#define GPIO19_FUN_USB_ENUM            18
#define GPIO19_FUN_RMII_MDIO           19
#define GPIO19_FUN_QDEC0_B             20
#define GPIO19_FUN_ROW_I_3             21
#define GPIO19_FUN_COL_O_19            22
#define GPIO19_FUN_CAM_REF_CLK         23
/* GPIO20 function definition */
#define GPIO20_FUN_CLK_OUT_0             0
#define GPIO20_FUN_BT_PRI                1
#define GPIO20_FUN_SF_IO_3               2
#define GPIO20_FUN_I2S0_BCLK             3
#define GPIO20_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO20_FUN_I2C0_SCL              6
#define GPIO20_FUN_UART_SIG4_UART_SIG0   7
#define GPIO20_FUN_PWM_CH0               8
#define GPIO20_FUN_PIX_DAT7              9
#define GPIO20_FUN_GPIP_CH_10            10
#define GPIO20_FUN_REG_GPIO_20           11
#define GPIO20_FUN_RF_TEST_15            12
#define GPIO20_FUN_UNUSED13              13
#define GPIO20_FUN_E21_TMS_E21_TCK       14
#define GPIO20_FUN_M_CCI_DI_DEBUG_16     15
#define GPIO20_FUN_FEM_GPIO_0            16
#define GPIO20_FUN_USB_TX_DN_USB_RX_DN   17
#define GPIO20_FUN_USB_OEB               18
#define GPIO20_FUN_RMII_RXERR            19
#define GPIO20_FUN_QDEC0_LED             20
#define GPIO20_FUN_ROW_I_4               21
#define GPIO20_FUN_COL_O_0               22
#define GPIO20_FUN_CAM_RESET             23
/* GPIO21 function definition */
#define GPIO21_FUN_CLK_OUT_1             0
#define GPIO21_FUN_BT_ABORT              1
#define GPIO21_FUN_SF_CLK                2
#define GPIO21_FUN_I2S0_FS               3
#define GPIO21_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO21_FUN_I2C0_SDA              6
#define GPIO21_FUN_UART_SIG5_UART_SIG1   7
#define GPIO21_FUN_PWM_CH1               8
#define GPIO21_FUN_UNUSED9               9
#define GPIO21_FUN_GPIP_CH_11            10
#define GPIO21_FUN_REG_GPIO_21           11
#define GPIO21_FUN_RF_TEST_16            12
#define GPIO21_FUN_UNUSED13              13
#define GPIO21_FUN_E21_TDI_E21_TDO       14
#define GPIO21_FUN_M_CCI_DO_DEBUG_17     15
#define GPIO21_FUN_FEM_GPIO_1            16
#define GPIO21_FUN_USB_TX_OE             17
#define GPIO21_FUN_VOP                   18
#define GPIO21_FUN_RMII_TX_EN            19
#define GPIO21_FUN_QDEC1_A               20
#define GPIO21_FUN_ROW_I_5               21
#define GPIO21_FUN_COL_O_1               22
#define GPIO21_FUN_CAM_PWRDN             23
/* GPIO22 function definition */
#define GPIO22_FUN_CLK_OUT_0           0
#define GPIO22_FUN_BT_ACTIVE           1
#define GPIO22_FUN_SF_IO_2             2
#define GPIO22_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO22_FUN_SPI_0_SS            4
#define GPIO22_FUN_I2C0_SCL            6
#define GPIO22_FUN_UART_SIG6_UART_SIG2 7
#define GPIO22_FUN_PWM_CH2             8
#define GPIO22_FUN_UNUSED9             9
#define GPIO22_FUN_LEDDRV_0            10
#define GPIO22_FUN_REG_GPIO_22         11
#define GPIO22_FUN_RF_TEST_17          12
#define GPIO22_FUN_UNUSED13            13
#define GPIO22_FUN_E21_TCK_E21_TMS     14
#define GPIO22_FUN_DEBUG_18            15
#define GPIO22_FUN_FEM_GPIO_2          16
#define GPIO22_FUN_USB_TX_DP_USB_RX_DP 17
#define GPIO22_FUN_VOM                 18
#define GPIO22_FUN_RMII_RX_DV          19
#define GPIO22_FUN_QDEC1_B             20
#define GPIO22_FUN_ROW_I_6             21
#define GPIO22_FUN_COL_O_2             22
#define GPIO22_FUN_CAM_REF_CLK         23
/* GPIO23 function definition */
#define GPIO23_FUN_CLK_OUT_1                 0
#define GPIO23_FUN_BT_PRI                    1
#define GPIO23_FUN_SF2_IO_2_SF3_CS2          2
#define GPIO23_FUN_I2S0_RCLK_O_I2S0_DI       3
#define GPIO23_FUN_SPI_0_SCLK                4
#define GPIO23_FUN_I2C0_SDA                  6
#define GPIO23_FUN_UART_SIG7_UART_SIG3       7
#define GPIO23_FUN_PWM_CH3                   8
#define GPIO23_FUN_PIX_DAT4                  9
#define GPIO23_FUN_LEDDRV_1_FLASH_PULL_OUT_0 10
#define GPIO23_FUN_REG_GPIO_23               11
#define GPIO23_FUN_RF_TEST_18                12
#define GPIO23_FUN_UNUSED13                  13
#define GPIO23_FUN_E21_TDO_E21_TDI           14
#define GPIO23_FUN_DEBUG_19                  15
#define GPIO23_FUN_FEM_GPIO_3                16
#define GPIO23_FUN_USB_SUS_EXT               17
#define GPIO23_FUN_BD                        18
#define GPIO23_FUN_UNUSED19                  19
#define GPIO23_FUN_QDEC1_LED                 20
#define GPIO23_FUN_ROW_I_7                   21
#define GPIO23_FUN_COL_O_3                   22
#define GPIO23_FUN_CAM_RESET                 23
/* GPIO24 function definition */
#define GPIO24_FUN_CLK_OUT_0             0
#define GPIO24_FUN_BT_ABORT              1
#define GPIO24_FUN_SF2_IO_1              2
#define GPIO24_FUN_I2S0_BCLK             3
#define GPIO24_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO24_FUN_I2C0_SCL              6
#define GPIO24_FUN_UART_SIG0_UART_SIG4   7
#define GPIO24_FUN_PWM_CH4               8
#define GPIO24_FUN_PIX_DAT5              9
#define GPIO24_FUN_FLASH_PULL_OUT_1      10
#define GPIO24_FUN_REG_GPIO_24           11
#define GPIO24_FUN_RF_TEST_19            12
#define GPIO24_FUN_UNUSED13              13
#define GPIO24_FUN_E21_TMS_E21_TCK       14
#define GPIO24_FUN_DEBUG_20              15
#define GPIO24_FUN_FEM_GPIO_4            16
#define GPIO24_FUN_USB_ENUM_EXT          17
#define GPIO24_FUN_VIP                   18
#define GPIO24_FUN_RMII_MDC              19
#define GPIO24_FUN_QDEC2_A               20
#define GPIO24_FUN_ROW_I_0               21
#define GPIO24_FUN_COL_O_4               22
#define GPIO24_FUN_CAM_PWRDN             23
/* GPIO25 function definition */
#define GPIO25_FUN_CLK_OUT_1             0
#define GPIO25_FUN_BT_ACTIVE             1
#define GPIO25_FUN_SF2_CS                2
#define GPIO25_FUN_I2S0_FS               3
#define GPIO25_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO25_FUN_I2C0_SDA              6
#define GPIO25_FUN_UART_SIG1_UART_SIG5   7
#define GPIO25_FUN_PWM_CH0               8
#define GPIO25_FUN_PIX_DAT6              9
#define GPIO25_FUN_FLASH_PULL_OUT_2      10
#define GPIO25_FUN_REG_GPIO_25           11
#define GPIO25_FUN_RF_TEST_20            12
#define GPIO25_FUN_UNUSED13              13
#define GPIO25_FUN_E21_TDI_E21_TDO       14
#define GPIO25_FUN_DEBUG_21              15
#define GPIO25_FUN_FEM_GPIO_0            16
#define GPIO25_FUN_USB_TX_DN_USB_RX_DN   17
#define GPIO25_FUN_VIM                   18
#define GPIO25_FUN_RMII_MDIO             19
#define GPIO25_FUN_QDEC2_B               20
#define GPIO25_FUN_ROW_I_1               21
#define GPIO25_FUN_COL_O_5               22
#define GPIO25_FUN_CAM_REF_CLK           23
/* GPIO26 function definition */
#define GPIO26_FUN_CLK_OUT_0           0
#define GPIO26_FUN_BT_PRI              1
#define GPIO26_FUN_SF2_IO_3            2
#define GPIO26_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO26_FUN_SPI_0_SS            4
#define GPIO26_FUN_I2C0_SCL            6
#define GPIO26_FUN_UART_SIG2_UART_SIG6 7
#define GPIO26_FUN_PWM_CH1             8
#define GPIO26_FUN_PIX_DAT7            9
#define GPIO26_FUN_FLASH_PULL_OUT_3    10
#define GPIO26_FUN_REG_GPIO_26         11
#define GPIO26_FUN_RF_TEST_21          12
#define GPIO26_FUN_UNUSED13            13
#define GPIO26_FUN_E21_TCK_E21_TMS     14
#define GPIO26_FUN_DEBUG_22            15
#define GPIO26_FUN_FEM_GPIO_1          16
#define GPIO26_FUN_USB_TX_OE           17
#define GPIO26_FUN_RCV                 18
#define GPIO26_FUN_RMII_RXERR          19
#define GPIO26_FUN_QDEC2_LED           20
#define GPIO26_FUN_ROW_I_2             21
#define GPIO26_FUN_COL_O_6             22
#define GPIO26_FUN_CAM_RESET           23
/* GPIO27 function definition */
#define GPIO27_FUN_CLK_OUT_1           0
#define GPIO27_FUN_BT_ABORT            1
#define GPIO27_FUN_SF2_CLK             2
#define GPIO27_FUN_I2S0_RCLK_O_I2S0_DI 3
#define GPIO27_FUN_SPI_0_SCLK          4
#define GPIO27_FUN_I2C0_SDA            6
#define GPIO27_FUN_UART_SIG3_UART_SIG7 7
#define GPIO27_FUN_PWM_CH2             8
#define GPIO27_FUN_UNUSED9             9
#define GPIO27_FUN_FLASH_PULL_OUT_4    10
#define GPIO27_FUN_REG_GPIO_27         11
#define GPIO27_FUN_RF_TEST_22          12
#define GPIO27_FUN_UNUSED13            13
#define GPIO27_FUN_E21_TDO_E21_TDI     14
#define GPIO27_FUN_DEBUG_23            15
#define GPIO27_FUN_FEM_GPIO_2          16
#define GPIO27_FUN_USB_TX_DP_USB_RX_DP 17
#define GPIO27_FUN_USB_SUS             18
#define GPIO27_FUN_RMII_TX_EN          19
#define GPIO27_FUN_QDEC0_A             20
#define GPIO27_FUN_ROW_I_3             21
#define GPIO27_FUN_COL_O_7             22
#define GPIO27_FUN_CAM_PWRDN           23
/* GPIO28 function definition */
#define GPIO28_FUN_CLK_OUT_0             0
#define GPIO28_FUN_BT_ACTIVE             1
#define GPIO28_FUN_SF2_IO_0              2
#define GPIO28_FUN_I2S0_BCLK             3
#define GPIO28_FUN_SPI_0_MOSI_SPI_0_MISO 4
#define GPIO28_FUN_I2C0_SCL              6
#define GPIO28_FUN_UART_SIG4_UART_SIG0   7
#define GPIO28_FUN_PWM_CH3               8
#define GPIO28_FUN_PIX_DAT4              9
#define GPIO28_FUN_FLASH_PULL_OUT_5      10
#define GPIO28_FUN_REG_GPIO_28           11
#define GPIO28_FUN_RF_TEST_23            12
#define GPIO28_FUN_UNUSED13              13
#define GPIO28_FUN_E21_TMS_E21_TCK       14
#define GPIO28_FUN_DEBUG_24              15
#define GPIO28_FUN_FEM_GPIO_3            16
#define GPIO28_FUN_USB_SUS_EXT           17
#define GPIO28_FUN_USB_ENUM              18
#define GPIO28_FUN_RMII_RX_DV            19
#define GPIO28_FUN_QDEC0_B               20
#define GPIO28_FUN_ROW_I_4               21
#define GPIO28_FUN_COL_O_8               22
#define GPIO28_FUN_CAM_REF_CLK           23
/* GPIO29 function definition */
#define GPIO29_FUN_CLK_OUT_1             0
#define GPIO29_FUN_BT_PRI                1
#define GPIO29_FUN_UNUSED2               2
#define GPIO29_FUN_I2S0_FS               3
#define GPIO29_FUN_SPI_0_MISO_SPI_0_MOSI 4
#define GPIO29_FUN_I2C0_SDA              6
#define GPIO29_FUN_UART_SIG5_UART_SIG1   7
#define GPIO29_FUN_PWM_CH4               8
#define GPIO29_FUN_PIX_DAT5              9
#define GPIO29_FUN_UNUSED10              10
#define GPIO29_FUN_REG_GPIO_29           11
#define GPIO29_FUN_RF_TEST_24            12
#define GPIO29_FUN_UNUSED13              13
#define GPIO29_FUN_E21_TDI_E21_TDO       14
#define GPIO29_FUN_DEBUG_25              15
#define GPIO29_FUN_FEM_GPIO_4            16
#define GPIO29_FUN_USB_ENUM_EXT          17
#define GPIO29_FUN_USB_OEB               18
#define GPIO29_FUN_UNUSED19              19
#define GPIO29_FUN_QDEC0_LED             20
#define GPIO29_FUN_ROW_I_5               21
#define GPIO29_FUN_COL_O_9               22
#define GPIO29_FUN_CAM_RESET             23
/* GPIO30 function definition */
#define GPIO30_FUN_CLK_OUT_0           0
#define GPIO30_FUN_BT_ABORT            1
#define GPIO30_FUN_UNUSED2             2
#define GPIO30_FUN_I2S0_DIO_I2S0_DO    3
#define GPIO30_FUN_SPI_0_SS            4
#define GPIO30_FUN_I2C0_SCL            6
#define GPIO30_FUN_UART_SIG6_UART_SIG2 7
#define GPIO30_FUN_PWM_CH0             8
#define GPIO30_FUN_PIX_DAT6            9
#define GPIO30_FUN_UNUSED10            10
#define GPIO30_FUN_REG_GPIO_30         11
#define GPIO30_FUN_RF_TEST_25          12
#define GPIO30_FUN_UNUSED13            13
#define GPIO30_FUN_E21_TCK_E21_TMS     14
#define GPIO30_FUN_DEBUG_26            15
#define GPIO30_FUN_FEM_GPIO_0          16
#define GPIO30_FUN_USB_TX_DN_USB_RX_DN 17
#define GPIO30_FUN_VOP                 18
#define GPIO30_FUN_UNUSED19            19
#define GPIO30_FUN_QDEC1_A             20
#define GPIO30_FUN_ROW_I_6             21
#define GPIO30_FUN_COL_O_10            22
#define GPIO30_FUN_CAM_PWRDN           23
/* GPIO31 function definition */
#define GPIO31_FUN_CLK_OUT_1           0
#define GPIO31_FUN_BT_ACTIVE           1
#define GPIO31_FUN_UNUSED2             2
#define GPIO31_FUN_I2S0_RCLK_O_I2S0_DI 3
#define GPIO31_FUN_SPI_0_SCLK          4
#define GPIO31_FUN_I2C0_SDA            6
#define GPIO31_FUN_UART_SIG7_UART_SIG3 7
#define GPIO31_FUN_PWM_CH1             8
#define GPIO31_FUN_PIX_DAT7            9
#define GPIO31_FUN_UNUSED10            10
#define GPIO31_FUN_REG_GPIO_31         11
#define GPIO31_FUN_RF_TEST_26          12
#define GPIO31_FUN_UNUSED13            13
#define GPIO31_FUN_E21_TDO_E21_TDI     14
#define GPIO31_FUN_DEBUG_27            15
#define GPIO31_FUN_FEM_GPIO_1          16
#define GPIO31_FUN_USB_TX_OE           17
#define GPIO31_FUN_VOM                 18
#define GPIO31_FUN_UNUSED19            19
#define GPIO31_FUN_QDEC1_B             20
#define GPIO31_FUN_ROW_I_7             21
#define GPIO31_FUN_COL_O_11            22
#define GPIO31_FUN_CAM_REF_CLK         23

#endif /*__BL702_GPIO_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_hbn.h
================================================
/**
  ******************************************************************************
  * @file    bl702_hbn.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_HBN_H__
#define __BL702_HBN_H__

#include "hbn_reg.h"
#include "bl702_aon.h"
#include "bl702_sflash.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  HBN
 *  @{
 */

/** @defgroup  HBN_Public_Types
 *  @{
 */

/**
 *  @brief HBN PIR interrupt configuration type definition
 */
typedef struct
{
    BL_Fun_Type lowIntEn;  /*!< Low will trigger interrupt */
    BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
} HBN_PIR_INT_CFG_Type;

/**
 *  @brief HBN PIR low pass filter type definition
 */
typedef enum {
    HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
    HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
} HBN_PIR_LPF_Type;

/**
 *  @brief HBN PIR high pass filter type definition
 */
typedef enum {
    HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
    HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
    HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
} HBN_PIR_HPF_Type;

/**
 *  @brief HBN BOR threshold type definition
 */
typedef enum {
    HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */
    HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */
} HBN_BOR_THRES_Type;

/**
 *  @brief HBN BOR mode type definition
 */
typedef enum {
    HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */
    HBN_BOR_MODE_POR_RELEVANT,    /*!< POR is relevant to BOR */
} HBN_BOR_MODE_Type;

/**
 *  @brief HBN 32K clock type definition
 */
typedef enum {
    HBN_32K_RC = 0,  /*!< HBN use rc 32k */
    HBN_32K_XTAL,    /*!< HBN use xtal 32k */
    HBN_32K_DIG = 3, /*!< HBN use dig 32k */
} HBN_32K_CLK_Type;

/**
 *  @brief HBN xclk clock type definition
 */
typedef enum {
    HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */
    HBN_XCLK_CLK_XTAL,  /*!< use XTAL as xclk clock */
} HBN_XCLK_CLK_Type;

/**
 *  @brief HBN root clock type definition
 */
typedef enum {
    HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */
    HBN_ROOT_CLK_XTAL,  /*!< use XTAL as root clock */
    HBN_ROOT_CLK_DLL,   /*!< use DLL as root clock */
} HBN_ROOT_CLK_Type;

/**
 *  @brief HBN UART clock type definition
 */
typedef enum {
    HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */
    HBN_UART_CLK_96M,      /*!< Select 96M as UART clock */
} HBN_UART_CLK_Type;

/**
 *  @brief HBN RTC interrupt delay type definition
 */
typedef enum {
    HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
    HBN_RTC_INT_DELAY_0T = 1,  /*!< HBN RTC interrupt delay 0T */
} HBN_RTC_INT_Delay_Type;

/**
 *  @brief HBN interrupt type definition
 */
typedef enum {
    HBN_INT_GPIO9 = 0,   /*!< HBN interrupt type: GPIO9 */
    HBN_INT_GPIO10 = 1,  /*!< HBN interrupt type: GPIO10 */
    HBN_INT_GPIO11 = 2,  /*!< HBN interrupt type: GPIO11 */
    HBN_INT_GPIO12 = 3,  /*!< HBN interrupt type: GPIO12 */
    HBN_INT_GPIO13 = 4,  /*!< HBN interrupt type: GPIO13 */
    HBN_INT_RTC = 16,    /*!< HBN interrupt type: RTC */
    HBN_INT_PIR,         /*!< HBN interrupt type: PIR */
    HBN_INT_BOR,         /*!< HBN interrupt type: BOR */
    HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
    HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
} HBN_INT_Type;

/**
 *  @brief HBN acomp interrupt type definition
 */
typedef enum {
    HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */
    HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */
} HBN_ACOMP_INT_EDGE_Type;

/**
 *  @brief HBN reset event type definition
 */
typedef enum {
    HBN_RST_EVENT_POR_OUT,   /*!< por_out event */
    HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */
    HBN_RST_EVENT_SW_RST,    /*!< sw_rst event */
    HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */
    HBN_RST_EVENT_BOR_OUT,   /*!< bor_out_ event */
} HBN_RST_EVENT_Type;

/**
 *  @brief HBN GPIO interrupt trigger type definition
 */
typedef enum {
    HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< HBN GPIO INT trigger type: sync falling edge trigger */
    HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< HBN GPIO INT trigger type: sync rising edge trigger */
    HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< HBN GPIO INT trigger type: sync low level trigger */
    HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< HBN GPIO INT trigger type: sync high level trigger */
    HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */
    HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< HBN GPIO INT trigger type: async rising edge trigger */
    HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< HBN GPIO INT trigger type: async low level trigger */
    HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< HBN GPIO INT trigger type: async high level trigger */
} HBN_GPIO_INT_Trigger_Type;

/**
 *  @brief HBN OUT0 interrupt type definition
 */
typedef enum {
    HBN_OUT0_INT_GPIO9 = 0,  /*!< HBN out 0 interrupt type: GPIO9 */
    HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */
    HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */
    HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */
    HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */
    HBN_OUT0_INT_RTC,        /*!< HBN out 0 interrupt type: RTC */
    HBN_OUT0_MAX,            /*!< HBN out 0 max num */
} HBN_OUT0_INT_Type;

/**
 *  @brief HBN OUT0 interrupt type definition
 */
typedef enum {
    HBN_OUT1_INT_PIR,    /*!< HBN out 1 interrupt type: PIR */
    HBN_OUT1_INT_BOR,    /*!< HBN out 1 interrupt type: BOR */
    HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
    HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
    HBN_OUT1_MAX,        /*!< HBN out 1 max num */
} HBN_OUT1_INT_Type;

/**
 *  @brief HBN LDO level type definition
 */
typedef enum {
    HBN_LDO_LEVEL_0P60V = 0,  /*!< HBN LDO voltage 0.60V */
    HBN_LDO_LEVEL_0P65V = 1,  /*!< HBN LDO voltage 0.65V */
    HBN_LDO_LEVEL_0P70V = 2,  /*!< HBN LDO voltage 0.70V */
    HBN_LDO_LEVEL_0P75V = 3,  /*!< HBN LDO voltage 0.75V */
    HBN_LDO_LEVEL_0P80V = 4,  /*!< HBN LDO voltage 0.80V */
    HBN_LDO_LEVEL_0P85V = 5,  /*!< HBN LDO voltage 0.85V */
    HBN_LDO_LEVEL_0P90V = 6,  /*!< HBN LDO voltage 0.90V */
    HBN_LDO_LEVEL_0P95V = 7,  /*!< HBN LDO voltage 0.95V */
    HBN_LDO_LEVEL_1P00V = 8,  /*!< HBN LDO voltage 1.00V */
    HBN_LDO_LEVEL_1P05V = 9,  /*!< HBN LDO voltage 1.05V */
    HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
    HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
    HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
    HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
    HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
    HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
} HBN_LDO_LEVEL_Type;

/**
 *  @brief HBN LDO11RT drive strength type definition
 */
typedef enum {
    HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0,   /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */
    HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */
    HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */
    HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */
} HBN_LDO11RT_DRIVE_STRENGTH_Type;

/**
 *  @brief HBN level type definition
 */
typedef enum {
    HBN_LEVEL_0, /*!< HBN pd_core */
    HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
    HBN_LEVEL_2, /*!< HBN pd_aon_hbncore + pd_core */
    HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
} HBN_LEVEL_Type;

/**
 *  @brief HBN BOR configuration type definition
 */
typedef struct
{
    uint8_t enableBor;      /*!< Enable BOR or not */
    uint8_t enableBorInt;   /*!< Enable BOR interrupt or not */
    uint8_t borThreshold;   /*!< BOR threshold */
    uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */
} HBN_BOR_CFG_Type;

/**
 *  @brief HBN APP configuration type definition
 */
typedef struct
{
    uint8_t useXtal32k;                     /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
    uint32_t sleepTime;                     /*!< HBN sleep time */
    uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
    HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
    SPI_Flash_Cfg_Type *flashCfg;           /*!< Flash config pointer, used when power down flash */
    uint8_t flashPinCfg;                    /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
    HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
    HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
} HBN_APP_CFG_Type;

/*@} end of group HBN_Public_Types */

/** @defgroup  HBN_Public_Constants
 *  @{
 */

/** @defgroup  HBN_PIR_LPF_TYPE
 *  @{
 */
#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
                                   ((type) == HBN_PIR_LPF_DIV2))

/** @defgroup  HBN_PIR_HPF_TYPE
 *  @{
 */
#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
                                   ((type) == HBN_PIR_HPF_METHOD1) || \
                                   ((type) == HBN_PIR_HPF_METHOD2))

/** @defgroup  HBN_BOR_THRES_TYPE
 *  @{
 */
#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \
                                     ((type) == HBN_BOR_THRES_2P4V))

/** @defgroup  HBN_BOR_MODE_TYPE
 *  @{
 */
#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \
                                    ((type) == HBN_BOR_MODE_POR_RELEVANT))

/** @defgroup  HBN_32K_CLK_TYPE
 *  @{
 */
#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) ||   \
                                   ((type) == HBN_32K_XTAL) || \
                                   ((type) == HBN_32K_DIG))

/** @defgroup  HBN_XCLK_CLK_TYPE
 *  @{
 */
#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \
                                    ((type) == HBN_XCLK_CLK_XTAL))

/** @defgroup  HBN_ROOT_CLK_TYPE
 *  @{
 */
#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \
                                    ((type) == HBN_ROOT_CLK_XTAL) ||  \
                                    ((type) == HBN_ROOT_CLK_DLL))

/** @defgroup  HBN_UART_CLK_TYPE
 *  @{
 */
#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \
                                    ((type) == HBN_UART_CLK_96M))

/** @defgroup  HBN_RTC_INT_DELAY_TYPE
 *  @{
 */
#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
                                         ((type) == HBN_RTC_INT_DELAY_0T))

/** @defgroup  HBN_INT_TYPE
 *  @{
 */
#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) ||  \
                               ((type) == HBN_INT_GPIO10) || \
                               ((type) == HBN_INT_GPIO11) || \
                               ((type) == HBN_INT_GPIO12) || \
                               ((type) == HBN_INT_GPIO13) || \
                               ((type) == HBN_INT_RTC) ||    \
                               ((type) == HBN_INT_PIR) ||    \
                               ((type) == HBN_INT_BOR) ||    \
                               ((type) == HBN_INT_ACOMP0) || \
                               ((type) == HBN_INT_ACOMP1))

/** @defgroup  HBN_ACOMP_INT_EDGE_TYPE
 *  @{
 */
#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
                                          ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))

/** @defgroup  HBN_RST_EVENT_TYPE
 *  @{
 */
#define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) ||   \
                                     ((type) == HBN_RST_EVENT_EXT_RST_N) || \
                                     ((type) == HBN_RST_EVENT_SW_RST) ||    \
                                     ((type) == HBN_RST_EVENT_PWR_RST_N) || \
                                     ((type) == HBN_RST_EVENT_BOR_OUT))

/** @defgroup  HBN_GPIO_INT_TRIGGER_TYPE
 *  @{
 */
#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))

/** @defgroup  HBN_OUT0_INT_TYPE
 *  @{
 */
#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) ||  \
                                    ((type) == HBN_OUT0_INT_GPIO10) || \
                                    ((type) == HBN_OUT0_INT_GPIO11) || \
                                    ((type) == HBN_OUT0_INT_GPIO12) || \
                                    ((type) == HBN_OUT0_INT_GPIO13) || \
                                    ((type) == HBN_OUT0_INT_RTC) ||    \
                                    ((type) == HBN_OUT0_MAX))

/** @defgroup  HBN_OUT1_INT_TYPE
 *  @{
 */
#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) ||    \
                                    ((type) == HBN_OUT1_INT_BOR) ||    \
                                    ((type) == HBN_OUT1_INT_ACOMP0) || \
                                    ((type) == HBN_OUT1_INT_ACOMP1) || \
                                    ((type) == HBN_OUT1_MAX))

/** @defgroup  HBN_LDO_LEVEL_TYPE
 *  @{
 */
#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \
                                     ((type) == HBN_LDO_LEVEL_0P65V) || \
                                     ((type) == HBN_LDO_LEVEL_0P70V) || \
                                     ((type) == HBN_LDO_LEVEL_0P75V) || \
                                     ((type) == HBN_LDO_LEVEL_0P80V) || \
                                     ((type) == HBN_LDO_LEVEL_0P85V) || \
                                     ((type) == HBN_LDO_LEVEL_0P90V) || \
                                     ((type) == HBN_LDO_LEVEL_0P95V) || \
                                     ((type) == HBN_LDO_LEVEL_1P00V) || \
                                     ((type) == HBN_LDO_LEVEL_1P05V) || \
                                     ((type) == HBN_LDO_LEVEL_1P10V) || \
                                     ((type) == HBN_LDO_LEVEL_1P15V) || \
                                     ((type) == HBN_LDO_LEVEL_1P20V) || \
                                     ((type) == HBN_LDO_LEVEL_1P25V) || \
                                     ((type) == HBN_LDO_LEVEL_1P30V) || \
                                     ((type) == HBN_LDO_LEVEL_1P35V))

/** @defgroup  HBN_LDO11RT_DRIVE_STRENGTH_TYPE
 *  @{
 */
#define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) ||   \
                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \
                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \
                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA))

/** @defgroup  HBN_LEVEL_TYPE
 *  @{
 */
#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
                                 ((type) == HBN_LEVEL_1) || \
                                 ((type) == HBN_LEVEL_2) || \
                                 ((type) == HBN_LEVEL_3))

/*@} end of group HBN_Public_Constants */

/** @defgroup  HBN_Public_Macros
 *  @{
 */
#define HBN_RAM_SIZE           (4 * 1024)
#define HBN_RTC_COMP_BIT0_39   0x01
#define HBN_RTC_COMP_BIT0_23   0x02
#define HBN_RTC_COMP_BIT13_39  0x04
#define HBN_STATUS_ENTER_FLAG  0x4e424845
#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
#define HBN_WAKEUP_GPIO_NONE   0x00
#define HBN_WAKEUP_GPIO_9      0x01
#define HBN_WAKEUP_GPIO_10     0x02
#define HBN_WAKEUP_GPIO_11     0x04
#define HBN_WAKEUP_GPIO_12     0x08
#define HBN_WAKEUP_GPIO_13     0x10
#define HBN_WAKEUP_GPIO_ALL    0x1E

/*@} end of group HBN_Public_Macros */

/** @defgroup  HBN_Public_Functions
 *  @{
 */
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void HBN_OUT0_IRQHandler(void);
void HBN_OUT1_IRQHandler(void);
#endif
/*----------*/
void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
BL_Err_Type HBN_Reset(void);
BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv);
BL_Err_Type HBN_Disable(void);
/*----------*/
BL_Err_Type HBN_PIR_Enable(void);
BL_Err_Type HBN_PIR_Disable(void);
BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
uint16_t HBN_Get_PIR_Threshold(void);
BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
uint16_t HBN_Get_PIR_Interval(void);
/*----------*/
BL_Sts_Type HBN_Get_BOR_OUT_State(void);
BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode);
/*----------*/
BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength);
/*----------*/
BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
/*----------*/
BL_Err_Type HBN_Set_HRAM_slp(void);
BL_Err_Type HBN_Set_HRAM_Ret(void);
/*----------*/
uint32_t HBN_Get_Status_Flag(void);
BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
uint32_t HBN_Get_Wakeup_Addr(void);
BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
/*----------*/
BL_Err_Type HBN_Clear_RTC_Counter(void);
BL_Err_Type HBN_Enable_RTC_Counter(void);
BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
BL_Err_Type HBN_Clear_RTC_INT(void);
/*----------*/
BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
BL_Err_Type HBN_GPIO_INT_Disable(void);
BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
uint8_t HBN_Get_Pin_Wakeup_Mode(void);
BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg);
BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
/*----------*/
BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
/*----------*/
BL_Err_Type HBN_Enable_BOR_IRQ(void);
BL_Err_Type HBN_Disable_BOR_IRQ(void);
/*----------*/
BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event);
BL_Err_Type HBN_Clear_Reset_Event(void);
/*----------*/
BL_Err_Type HBN_Out0_IRQHandler_Install(void);
BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
BL_Err_Type HBN_Out1_IRQHandler_Install(void);
BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
/*----------*/
BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn,
                                  uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask);
/*----------*/
BL_Err_Type HBN_Power_On_Xtal_32K(void);
BL_Err_Type HBN_Power_Off_Xtal_32K(void);
BL_Err_Type HBN_Power_On_RC32K(void);
BL_Err_Type HBN_Power_Off_RC32K(void);
BL_Err_Type HBN_Trim_RC32K(void);
BL_Err_Type HBN_Set_Pad_23_28_Pullnone(void);
BL_Err_Type HBN_Set_Pad_23_28_Pullup(void);
BL_Err_Type HBN_Set_Pad_23_28_Pulldown(void);
BL_Err_Type HBN_Set_Pad_23_28_ActiveIE(void);
BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg);
/*----------*/
void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
/*----------*/;

/*@} end of group HBN_Public_Functions */

/*@} end of group HBN */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_HBN_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c.h
================================================
/**
 ******************************************************************************
 * @file    bl702_i2c.h
 * @version V1.0
 * @date
 * @brief   This file is the standard driver header file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#ifndef __BL702_I2C_H__
#define __BL702_I2C_H__

#include "bl702_common.h"
#include "i2c_reg.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2C
 *  @{
 */

/** @defgroup  I2C_Public_Types
 *  @{
 */

/**
 *  @brief I2C No. type definition
 */
typedef enum {
  I2C0_ID = 0, /*!< I2C0 define */
  I2C_ID_MAX,  /*!< I2C max define */
} I2C_ID_Type;

/**
 *  @brief I2C read/write type definition
 */
typedef enum {
  I2C_WRITE = 0, /*!< I2C write direction */
  I2C_READ,      /*!< I2C read direction */
} I2C_Direction_Type;

/**
 *  @brief I2C interrupt type definition
 */
typedef enum {
  I2C_TRANS_END_INT,     /*!< I2C transfer end interrupt */
  I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */
  I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */
  I2C_NACK_RECV_INT,     /*!< I2C nack received interrupt */
  I2C_ARB_LOST_INT,      /*!< I2C arbitration lost interrupt */
  I2C_FIFO_ERR_INT,      /*!< I2C TX/RX FIFO error interrupt */
  I2C_INT_ALL,           /*!< I2C interrupt all type */
} I2C_INT_Type;

/**
 *  @brief I2S start condition phase structure type definition
 */
typedef struct {
  uint8_t len0; /*!< Length of START condition phase 0 */
  uint8_t len1; /*!< Length of START condition phase 1 */
  uint8_t len2; /*!< Length of START condition phase 2 */
  uint8_t len3; /*!< Length of START condition phase 3 */
} I2C_Start_Condition_Phase_Type;

/**
 *  @brief I2S stop condition phase structure type definition
 */
typedef struct {
  uint8_t len0; /*!< Length of STOP condition phase 0 */
  uint8_t len1; /*!< Length of STOP condition phase 1 */
  uint8_t len2; /*!< Length of STOP condition phase 2 */
  uint8_t len3; /*!< Length of STOP condition phase 3 */
} I2C_Stop_Condition_Phase_Type;

/**
 *  @brief I2S data phase structure type definition
 */
typedef struct {
  uint8_t len0; /*!< Length of DATA phase 0 */
  uint8_t len1; /*!< Length of DATA phase 1 */
  uint8_t len2; /*!< Length of DATA phase 2 */
  uint8_t len3; /*!< Length of DATA phase 3 */
} I2C_Data_Phase_Type;

/**
 *  @brief I2S transfer structure type definition
 */
typedef struct {
  uint8_t     slaveAddr;     /*!< I2C slave address */
  BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */
  uint8_t     subAddrSize;   /*!< Specifies the size of I2C sub address section */
  uint32_t    subAddr;       /*!< I2C sub address */
  uint16_t    dataSize;      /*!< Specifies the size of I2C data section */
  uint8_t    *data;          /*!< Specifies the pointer of I2C R/W data */
} I2C_Transfer_Cfg;

/*@} end of group I2C_Public_Types */

/** @defgroup  I2C_Public_Constants
 *  @{
 */

/** @defgroup  I2C_ID_TYPE
 *  @{
 */
#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || ((type) == I2C_ID_MAX))

/** @defgroup  I2C_DIRECTION_TYPE
 *  @{
 */
#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || ((type) == I2C_READ))

/** @defgroup  I2C_INT_TYPE
 *  @{
 */
#define IS_I2C_INT_TYPE(type)                                                                                                                                                                          \
  (((type) == I2C_TRANS_END_INT) || ((type) == I2C_TX_FIFO_READY_INT) || ((type) == I2C_RX_FIFO_READY_INT) || ((type) == I2C_NACK_RECV_INT) || ((type) == I2C_ARB_LOST_INT) ||                         \
   ((type) == I2C_FIFO_ERR_INT) || ((type) == I2C_INT_ALL))

/*@} end of group I2C_Public_Constants */

/** @defgroup  I2C_Public_Macros
 *  @{
 */

/*@} end of group I2C_Public_Macros */

/** @defgroup  I2C_Public_Functions
 *  @{
 */

/**
 *  @brief I2C Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void I2C_IRQHandler(void);
#endif
void        I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data);
uint32_t    I2C_RecieveWord(I2C_ID_Type i2cNo);
void        I2C_Enable(I2C_ID_Type i2cNo);
void        I2C_Disable(I2C_ID_Type i2cNo);
BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt);
BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo);
uint8_t     I2C_GetTXFIFOAvailable();
uint8_t     I2C_GetRXFIFOAvailable();
void        I2C_DMATxEnable();
void        I2C_DMATxDisable();
void        I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase);
void        I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk);
void        I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable);
void        I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg);
BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo);
BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo);
BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
void        I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask);
void        I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun);

/*@} end of group I2C_Public_Functions */

/*@} end of group I2C */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_I2C_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2c_gpio_sim.h
================================================
/**
  ******************************************************************************
  * @file    bl702_i2c_gpio_sim.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_I2C_GPIO_SIM_H__
#define __BL702_I2C_GPIO_SIM_H__

#include "bl702_glb.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2C_GPIO_SIM
 *  @{
 */

/** @defgroup  I2C_GPIO_SIM_Public_Types
 *  @{
 */

/*@} end of group I2C_GPIO_SIM_Public_Types */

/** @defgroup  I2C_GPIO_SIM_Public_Functions
 *  @{
 */

/**
 *  @brief I2C Functions
 */
void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin);
int I2C_Start(void);
void I2C_Stop(void);
uint8_t I2C_GetAck(void);
void I2C_SendByte(uint8_t Data);
uint8_t I2C_ReadByte(uint8_t ack);
int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin);
int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize);
int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize);

/*@} end of group I2C_GPIO_SIM_Public_Functions */

/*@} end of group I2C_GPIO_SIM */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_I2C_GPIO_SIM_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_i2s.h
================================================
/**
  ******************************************************************************
  * @file    bl702_i2s.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_I2S_H__
#define __BL702_I2S_H__

#include "i2s_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2S
 *  @{
 */

/** @defgroup  I2S_Public_Types
 *  @{
 */

/**
 *  @brief I2S mode type definition
 */
typedef enum {
    I2S_MODE_I2S_LEFT,  /*!< Left-Justified Mode */
    I2S_MODE_I2S_RIGHT, /*!< Right-Justified Mode */
    I2S_MODE_I2S_DSP,   /*!< DSP Mode */
} I2S_Mode_Type;

/**
 *  @brief I2S role type definition
 */
typedef enum {
    I2S_ROLE_MASTER = 0, /*!< I2S as master */
    I2S_ROLE_SLAVE = 1,  /*!< I2S as slave */
} I2S_Role_Type;

/**
 *  @brief I2S data size type definition
 */
typedef enum {
    I2S_SIZE_DATA_8 = 0, /*!< I2S data size 8 bits */
    I2S_SIZE_DATA_16,    /*!< I2S data size 16 bits */
    I2S_SIZE_DATA_24,    /*!< I2S data size 24 bits */
    I2S_SIZE_DATA_32,    /*!< I2S data size 32 bits */
} I2S_Data_Size_Type;

/**
 *  @brief I2S frame size type definition
 */
typedef enum {
    I2S_SIZE_FRAME_8 = 0, /*!< I2S frame size 8 bits */
    I2S_SIZE_FRAME_16,    /*!< I2S frame size 16 bits */
    I2S_SIZE_FRAME_24,    /*!< I2S frame size 24 bits */
    I2S_SIZE_FRAME_32,    /*!< I2S frame size 32 bits */
} I2S_Frame_Size_Type;

/**
 *  @brief I2S endian data type definition
 */
typedef enum {
    I2S_DATA_ENDIAN_MSB = 0, /*!< I2S use MSB first */
    I2S_DATA_ENDIAN_LSB,     /*!< I2S use LSB first */
} I2S_Endian_Type;

/**
 *  @brief I2S frame select mode type definition
 */
typedef enum {
    I2S_FS_MODE_EVEN = 0, /*!< I2S frame is even */
    I2S_FS_MODE_1T,       /*!< I2S frame is only 1T high */
} I2S_Fs_Mode_Type;

/**
 *  @brief I2S rx mono mode channel select type definition
 */
typedef enum {
    I2S_RX_MONO_MODE_LEFT_CHANNEL,  /*!< I2S rx mono mode left channel */
    I2S_RX_MONO_MODE_RIGHT_CHANNEL, /*!< I2S rx mono mode right channel */
} I2S_Mono_Mode_Channel;

/**
 *  @brief I2S frame channel mode type definition
 */
typedef enum {
    I2S_FS_CHANNELS_2 = 0, /*!< I2S frame is for 2 channels */
    I2S_FS_CHANNELS_3,     /*!< I2S frame is for 3 channels */
    I2S_FS_CHANNELS_4,     /*!< I2S frame is for 4 channels */
} I2S_Fs_Channel_Type;

/**
 *  @brief I2S mono control definition
 */
typedef enum {
    I2S_MONO_CONTROL_STEREO = 0, /*!< I2S output stereo */
    I2S_MONO_CONTROL_MONO,       /*!< I2S output mono */
} I2S_MonoControl_Type;

/**
 *  @brief I2S fifo 24-bit data align type definition
 */
typedef enum {
    I2S_FIFO_24_RIGHT_JUSTIFIED = 0, /*!< I2S fifo:[31:24]0x00,[23:0]24bit_data */
    I2S_FIFO_24_LEFT_JUSTIFIED,      /*!< I2S fifo:[31:8]24bit_data,[7:0]0x00 */
} I2S_FIFO_24_Justified_Type;

/**
 *  @brief I2S configuration structure type definition
 */
typedef struct
{
    I2S_Endian_Type endianType;            /*!< I2S endian configuration */
    I2S_Mode_Type modeType;                /*!< I2S mode configuration */
    uint32_t audioFreqHz;                  /*!< I2S audio pll output frequency in Hz */
    uint32_t sampleFreqHz;                 /*!< I2S sample data frequency in Hz */
    BL_Fun_Type bclkInvert;                /*!< I2S bclk invert configuration */
    I2S_Frame_Size_Type frameSize;         /*!< I2S frame size configuration */
    BL_Fun_Type fsInvert;                  /*!< I2S frame select invert configuration */
    I2S_Fs_Mode_Type fsMode;               /*!< I2S frame mode configuration */
    I2S_Fs_Channel_Type fsChannel;         /*!< I2S frame channels configuration */
    uint32_t dataOffset;                   /*!< I2S data output offset configuration */
    I2S_Data_Size_Type dataSize;           /*!< I2S data size configuration */
    BL_Fun_Type monoMode;                  /*!< I2S enable mono mode,when this mode enable,lRMerge must be disabled */
    I2S_Mono_Mode_Channel monoModeChannel; /*!< I2S mono mode channel configuration */
} I2S_CFG_Type;

/**
 *  @brief I2S FIFO configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type lRMerge;           /*!< I2S FIFO contains both left and right channel data in one entry */
    BL_Fun_Type frameDataExchange; /*!< I2S exchange left and right channel data in one entry */
    BL_Fun_Type txfifoDmaEnable;   /*!< Enable or disable I2S tx fifo dma function. */
    BL_Fun_Type rxfifoDmaEnable;   /*!< Enable or disable I2S rx fifo dma function. */
    uint8_t rxFifoLevel;           /*!< I2S receive fifo interrupt trigger level. only valid when fifo mode enabled. */
    uint8_t txFifoLevel;           /*!< I2S transmit fifo interrupt trigger level. only valid when fifo mode enabled. */
} I2S_FifoCfg_Type;

/**
 *  @brief I2S IO configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type deglitchEn;  /*!< Enable or disable deglitch(for all the input pins) */
    uint8_t deglitchCnt;     /*!< Deglitch cycle count(unit:cycle of I2S kernel clock) */
    BL_Fun_Type inverseBCLK; /*!< Enable or disable inverse BCLK signal */
    BL_Fun_Type inverseFS;   /*!< Enable or disable inverse FS signal */
    BL_Fun_Type inverseRX;   /*!< Enable or disable inverse RX signal */
    BL_Fun_Type inverseTX;   /*!< Enable or disable inverse TX signal */
} I2S_IOCfg_Type;

/*@} end of group I2S_Public_Types */

/** @defgroup  I2S_Public_Constants
 *  @{
 */

/** @defgroup  I2S_MODE_TYPE
 *  @{
 */
#define IS_I2S_MODE_TYPE(type) (((type) == I2S_MODE_I2S_LEFT) ||  \
                                ((type) == I2S_MODE_I2S_RIGHT) || \
                                ((type) == I2S_MODE_I2S_DSP))

/** @defgroup  I2S_ROLE_TYPE
 *  @{
 */
#define IS_I2S_ROLE_TYPE(type) (((type) == I2S_ROLE_MASTER) || \
                                ((type) == I2S_ROLE_SLAVE))

/** @defgroup  I2S_DATA_SIZE_TYPE
 *  @{
 */
#define IS_I2S_DATA_SIZE_TYPE(type) (((type) == I2S_SIZE_DATA_8) ||  \
                                     ((type) == I2S_SIZE_DATA_16) || \
                                     ((type) == I2S_SIZE_DATA_24) || \
                                     ((type) == I2S_SIZE_DATA_32))

/** @defgroup  I2S_FRAME_SIZE_TYPE
 *  @{
 */
#define IS_I2S_FRAME_SIZE_TYPE(type) (((type) == I2S_SIZE_FRAME_8) ||  \
                                      ((type) == I2S_SIZE_FRAME_16) || \
                                      ((type) == I2S_SIZE_FRAME_24) || \
                                      ((type) == I2S_SIZE_FRAME_32))

/** @defgroup  I2S_ENDIAN_TYPE
 *  @{
 */
#define IS_I2S_ENDIAN_TYPE(type) (((type) == I2S_DATA_ENDIAN_MSB) || \
                                  ((type) == I2S_DATA_ENDIAN_LSB))

/** @defgroup  I2S_FS_MODE_TYPE
 *  @{
 */
#define IS_I2S_FS_MODE_TYPE(type) (((type) == I2S_FS_MODE_EVEN) || \
                                   ((type) == I2S_FS_MODE_1T))

/** @defgroup  I2S_MONO_MODE_CHANNEL
 *  @{
 */
#define IS_I2S_MONO_MODE_CHANNEL(type) (((type) == I2S_RX_MONO_MODE_LEFT_CHANNEL) || \
                                        ((type) == I2S_RX_MONO_MODE_RIGHT_CHANNEL))

/** @defgroup  I2S_FS_CHANNEL_TYPE
 *  @{
 */
#define IS_I2S_FS_CHANNEL_TYPE(type) (((type) == I2S_FS_CHANNELS_2) || \
                                      ((type) == I2S_FS_CHANNELS_3) || \
                                      ((type) == I2S_FS_CHANNELS_4))

/** @defgroup  I2S_MONOCONTROL_TYPE
 *  @{
 */
#define IS_I2S_MONOCONTROL_TYPE(type) (((type) == I2S_MONO_CONTROL_STEREO) || \
                                       ((type) == I2S_MONO_CONTROL_MONO))

/** @defgroup  I2S_FIFO_24_JUSTIFIED_TYPE
 *  @{
 */
#define IS_I2S_FIFO_24_JUSTIFIED_TYPE(type) (((type) == I2S_FIFO_24_RIGHT_JUSTIFIED) || \
                                             ((type) == I2S_FIFO_24_LEFT_JUSTIFIED))

/*@} end of group I2S_Public_Constants */

/** @defgroup  I2S_Public_Macros
 *  @{
 */
#define I2S_TX_FIFO_SIZE 16
#define I2S_RX_FIFO_SIZE 16

/*@} end of group I2S_Public_Macros */

/** @defgroup  I2S_Public_Functions
 *  @{
 */

/**
 *  @brief I2S Functions
 */
void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg);
void I2S_Init(I2S_CFG_Type *i2sCfg);
void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg);
void I2S_IOConfig(I2S_IOCfg_Type *ioCfg);
void I2S_Enable(I2S_Role_Type roleType);
void I2S_Disable(void);
uint32_t I2S_Read(void);
void I2S_Write(uint32_t data);
void I2S_Mute(BL_Fun_Type enabled);
void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType);
uint32_t I2S_GetTxFIFO_AvlCnt(void);
uint32_t I2S_GetRxFIFO_AvlCnt(void);
void I2S_Flush(void);

/*@} end of group I2S_Public_Functions */

/*@} end of group I2S */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_I2S_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_ir.h
================================================
/**
  ******************************************************************************
  * @file    bl702_ir.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_IR_H__
#define __BL702_IR_H__

#include "ir_reg.h"
#include "bl702_common.h"
#include "bl702_hbn.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  IR
 *  @{
 */

/** @defgroup  IR_Public_Types
 *  @{
 */

/**
 *  @brief IR direction type definition
 */
typedef enum {
    IR_TX,   /*!< IR TX direction */
    IR_RX,   /*!< IR RX direction */
    IR_TXRX, /*!< IR TX and RX direction */
} IR_Direction_Type;

/**
 *  @brief IR word type definition
 */
typedef enum {
    IR_WORD_0, /*!< IR data word 0 */
    IR_WORD_1, /*!< IR data word 1 */
} IR_Word_Type;

/**
 *  @brief IR RX mode type definition
 */
typedef enum {
    IR_RX_NEC, /*!< IR RX NEC mode */
    IR_RX_RC5, /*!< IR RX RC5 mode */
    IR_RX_SWM, /*!< IR RX software pulse-width detection mode */
} IR_RxMode_Type;

/**
 *  @brief IR interrupt type definition
 */
typedef enum {
    IR_INT_TX,  /*!< IR TX transfer end interrupt */
    IR_INT_RX,  /*!< IR RX transfer end interrupt */
    IR_INT_ALL, /*!< IR all interrupt */
} IR_INT_Type;

/**
 *  @brief IR fifo underflow or overflow type definition
 */
typedef enum {
    IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */
    IR_RX_FIFO_OVERFLOW,  /*!< Overflow flag of rx fifo */
} IR_FifoStatus_Type;

/**
 *  @brief IR TX configuration structure type definition
 */
typedef struct
{
    uint8_t dataBits;               /*!< Bit count of data phase */
    BL_Fun_Type tailPulseInverse;   /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */
    BL_Fun_Type tailPulse;          /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */
    BL_Fun_Type headPulseInverse;   /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */
    BL_Fun_Type headPulse;          /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */
    BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */
    BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */
    BL_Fun_Type dataPulse;          /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */
    BL_Fun_Type outputModulation;   /*!< Enable or disable signal of output modulation */
    BL_Fun_Type outputInverse;      /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */
} IR_TxCfg_Type;

/**
 *  @brief IR TX pulse width configuration structure type definition
 */
typedef struct
{
    uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */
    uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */
    uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */
    uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */
    uint8_t headPulseWidth_1;   /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */
    uint8_t headPulseWidth_0;   /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */
    uint8_t tailPulseWidth_1;   /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */
    uint8_t tailPulseWidth_0;   /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */
    uint8_t moduWidth_1;        /*!< Modulation phase 1 width */
    uint8_t moduWidth_0;        /*!< Modulation phase 0 width */
    uint16_t pulseWidthUnit;    /*!< Pulse width unit */
} IR_TxPulseWidthCfg_Type;

/**
 *  @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition
 */
typedef struct
{
    uint32_t swmData0; /*!< SWM pulse width data   0~7,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData1; /*!< SWM pulse width data  8~15,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */
    uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */
} IR_TxSWMPulseWidthCfg_Type;

/**
 *  @brief IR RX configuration structure type definition
 */
typedef struct
{
    IR_RxMode_Type rxMode;    /*!< Set ir rx mode */
    BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */
    uint16_t endThreshold;    /*!< Pulse width threshold to trigger end condition */
    uint16_t dataThreshold;   /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */
    BL_Fun_Type rxDeglitch;   /*!< Enable or disable signal of rx input de-glitch function */
    uint8_t DeglitchCnt;      /*!< De-glitch function cycle count */
} IR_RxCfg_Type;

/*@} end of group IR_Public_Types */

/** @defgroup  IR_Public_Constants
 *  @{
 */

/** @defgroup  IR_DIRECTION_TYPE
 *  @{
 */
#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \
                                    ((type) == IR_RX) || \
                                    ((type) == IR_TXRX))

/** @defgroup  IR_WORD_TYPE
 *  @{
 */
#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \
                               ((type) == IR_WORD_1))

/** @defgroup  IR_RXMODE_TYPE
 *  @{
 */
#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \
                                 ((type) == IR_RX_RC5) || \
                                 ((type) == IR_RX_SWM))

/** @defgroup  IR_INT_TYPE
 *  @{
 */
#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \
                              ((type) == IR_INT_RX) || \
                              ((type) == IR_INT_ALL))

/** @defgroup  IR_FIFOSTATUS_TYPE
 *  @{
 */
#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \
                                     ((type) == IR_RX_FIFO_OVERFLOW))

/*@} end of group IR_Public_Constants */

/** @defgroup  IR_Public_Macros
 *  @{
 */
#define IR_RX_FIFO_SIZE 64

/*@} end of group IR_Public_Macros */

/** @defgroup  IR_Public_Functions
 *  @{
 */

/**
 *  @brief IR Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void IRRX_IRQHandler(void);
void IRTX_IRQHandler(void);
#endif
BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg);
BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg);
BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg);
BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg);
BL_Err_Type IR_DeInit(void);
BL_Err_Type IR_Enable(IR_Direction_Type direct);
BL_Err_Type IR_Disable(IR_Direction_Type direct);
BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM);
BL_Err_Type IR_RxFIFOClear(void);
BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data);
BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length);
BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0);
BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length);
BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command);
BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask);
BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType);
BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun);
BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType);
BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts);
uint32_t IR_ReceiveData(IR_Word_Type irWord);
uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length);
BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command);
uint8_t IR_GetRxDataBitCount(void);
uint8_t IR_GetRxFIFOCount(void);
IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length);
BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length);
uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data);
BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H,
                       uint8_t code1L);
BL_Err_Type IR_LEDSend(uint32_t data);

/*@} end of group IR_Public_Functions */

/*@} end of group IR */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_IR_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_kys.h
================================================
/**
  ******************************************************************************
  * @file    bl702_kys.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_KYS_H__
#define __BL702_KYS_H__

#include "kys_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  KYS
 *  @{
 */

/** @defgroup  KYS_Public_Types
 *  @{
 */

/**
 *  @brief KYS keycode type definition
 */
typedef enum {
    KYS_KEYCODE_0, /*!< KYS keycode 0 */
    KYS_KEYCODE_1, /*!< KYS keycode 1 */
    KYS_KEYCODE_2, /*!< KYS keycode 2 */
    KYS_KEYCODE_3, /*!< KYS keycode 3 */
} KYS_Keycode_Type;

/**
 *  @brief KYS configuration structure type definition
 */
typedef struct
{
    uint8_t col;            /*!< Col of keyboard,max:20 */
    uint8_t row;            /*!< Row of keyboard,max:8 */
    uint8_t idleDuration;   /*!< Idle duration between column scans */
    BL_Fun_Type ghostEn;    /*!< Enable or disable ghost key event detection */
    BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch function */
    uint8_t deglitchCnt;    /*!< Deglitch count */
} KYS_CFG_Type;

/*@} end of group KYS_Public_Types */

/** @defgroup  KYS_Public_Constants
 *  @{
 */

/** @defgroup  KYS_KEYCODE_TYPE
 *  @{
 */
#define IS_KYS_KEYCODE_TYPE(type) (((type) == KYS_KEYCODE_0) || \
                                   ((type) == KYS_KEYCODE_1) || \
                                   ((type) == KYS_KEYCODE_2) || \
                                   ((type) == KYS_KEYCODE_3))

/*@} end of group KYS_Public_Constants */

/** @defgroup  KYS_Public_Macros
 *  @{
 */

/*@} end of group KYS_Public_Macros */

/** @defgroup  KYS_Public_Functions
 *  @{
 */

/**
 *  @brief UART Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void KYS_IRQHandler(void);
#endif
BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg);
BL_Err_Type KYS_Enable(void);
BL_Err_Type KYS_Disable(void);
BL_Err_Type KYS_IntMask(BL_Mask_Type intMask);
BL_Err_Type KYS_IntClear(void);
BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun);
uint8_t KYS_GetIntStatus(void);
uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row);

/*@} end of group KYS_Public_Functions */

/*@} end of group KYS */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_KYS_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_l1c.h
================================================
/**
  ******************************************************************************
  * @file    bl702_l1c.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_L1C_H__
#define __BL702_L1C_H__

#include "l1c_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  L1C
 *  @{
 */

/** @defgroup  L1C_Public_Types
 *  @{
 */

/**
 *  @brief L1C configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type wrapDis;  /*!< wrap disable */
    BL_Fun_Type bypassEn; /*!< bypass cache enable */
    uint8_t wayDis;       /*!< Disable part of cache ways & used as ITCM */
    BL_Fun_Type cntEn;    /*!< l1c count enable */
} L1C_CACHE_Cfg_Type;

/**
 *  @brief L1C BMX arb mode type definition
 */
typedef enum {
    L1C_BMX_ARB_FIX,         /*!< 0->fix */
    L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
    L1C_BMX_ARB_RANDOM,      /*!< 3->random */
} L1C_BMX_ARB_Type;

/**
 *  @brief L1C BMX configuration structure type definition
 */
typedef struct
{
    uint8_t timeoutEn;       /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
    BL_Fun_Type errEn;       /*!< Bus error response enable */
    L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
} L1C_BMX_Cfg_Type;

/**
 *  @brief L1C BMX bus err type definition
 */
typedef enum {
    L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
    L1C_BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
} L1C_BMX_BUS_ERR_Type;

/**
 *  @brief L1C BMX bus err interrupt type definition
 */
typedef enum {
    L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
    L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
} L1C_BMX_ERR_INT_Type;

/**
 *  @brief L1C BMX time out interrupt type definition
 */
typedef enum {
    L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
    L1C_BMX_TO_INT_ALL,     /*!< L1C_BMX timeout interrupt max num */
} L1C_BMX_TO_INT_Type;

/*@} end of group L1C_Public_Types */

/** @defgroup  L1C_Public_Constants
 *  @{
 */

/** @defgroup  L1C_BMX_ARB_TYPE
 *  @{
 */
#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) ||         \
                                   ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
                                   ((type) == L1C_BMX_ARB_RANDOM))

/** @defgroup  L1C_BMX_BUS_ERR_TYPE
 *  @{
 */
#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
                                       ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))

/** @defgroup  L1C_BMX_ERR_INT_TYPE
 *  @{
 */
#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
                                       ((type) == L1C_BMX_ERR_INT_ALL))

/** @defgroup  L1C_BMX_TO_INT_TYPE
 *  @{
 */
#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
                                      ((type) == L1C_BMX_TO_INT_ALL))

/*@} end of group L1C_Public_Constants */

/** @defgroup  L1C_Public_Macros
 *  @{
 */
#define L1C_WAY_DISABLE_NONE  0x00
#define L1C_WAY_DISABLE_ONE   0x01
#define L1C_WAY_DISABLE_TWO   0x03
#define L1C_WAY_DISABLE_THREE 0x07
#define L1C_WAY_DISABLE_ALL   0x0F
#define L1C_WAY_DISABLE_USER  0xFF
#if 1
/*NP config address */
#define L1C_CONF_REG        (L1C_BASE + 0x00)
#define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04)
#define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08)
#define L1C_MISS_CNT_REG    (L1C_BASE + 0x0C)
/* Get miss and hit count */
#define L1C_Get_Miss_Cnt()    BL702_REG_RD(L1C_MISS_CNT_REG)
#define L1C_Get_Hit_Cnt_LSB() BL702_REG_RD(L1C_HIT_CNT_LSB_REG)
#define L1C_Get_Hit_Cnt_MSB() BL702_REG_RD(L1C_HIT_CNT_MSB_REG)
#endif

/*@} end of group L1C_Public_Macros */

/** @defgroup  L1C_Public_Functions
 *  @{
 */
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void L1C_BMX_ERR_IRQHandler(void);
void L1C_BMX_TO_IRQHandler(void);
#endif
/*----------*/
BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable);
void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
BL_Err_Type L1C_Cache_Flush(uint8_t wayDisable);
BL_Err_Type L1C_Cache_Flush_Ext(void);
void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh);
uint32_t L1C_Cache_Miss_Count_Get(void);
void L1C_Cache_Read_Disable(void);
/*----------*/
BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
/*----------*/
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
uint32_t L1C_BMX_Get_Err_Addr(void);
BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
                                                 intCallback_Type *cbFun);
/*----------*/;

/*@} end of group L1C_Public_Functions */

/*@} end of group L1C */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_L1C_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_mjpeg.h
================================================
/**
  ******************************************************************************
  * @file    bl702_mjpeg.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_MJPEG_H__
#define __BL702_MJPEG_H__

#include "mjpeg_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  MJPEG
 *  @{
 */

/** @defgroup  MJPEG_Public_Types
 *  @{
 */

/**
 *  @brief MJPEG YUV format definition
 */
typedef enum {
    MJPEG_YUV420,            /*!< MJPEG YUV420 planar mode */
    MJPEG_YUV400,            /*!< MJPEG YUV400 grey scale mode */
    MJPEG_YUV422_PLANAR,     /*!< MJPEG YUV422 planar mode */
    MJPEG_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */
} MJPEG_YUV_Mode_Type;

/**
 *  @brief MJPEG burst type definition
 */
typedef enum {
    MJPEG_BURST_SINGLE, /*!< MJPEG burst single */
    MJPEG_BURST_INCR4,  /*!< MJPEG burst incr4 */
    MJPEG_BURST_INCR8,  /*!< MJPEG burst incr8 */
    MJPEG_BURST_INCR16, /*!< MJPEG burst incr16 */
} MJPEG_Burst_Type;

/**
 *  @brief MJPEG swap mode block definition
 */
typedef enum {
    MJPEG_BLOCK_0, /*!< Memory block 0 */
    MJPEG_BLOCK_1, /*!< Memory block 1 */
} MJPEG_Swap_Block_Type;

/**
 *  @brief MJPEG interrupt type definition
 */
typedef enum {
    MJPEG_INT_NORMAL,          /*!< MJPEG normal write interrupt */
    MJPEG_INT_CAM_OVERWRITE,   /*!< MJPEG camera overwrite interrupt */
    MJPEG_INT_MEM_OVERWRITE,   /*!< MJPEG memory overwrite interrupt */
    MJPEG_INT_FRAME_OVERWRITE, /*!< MJPEG frame overwrite interrupt */
    MJPEG_INT_BACK_IDLE,       /*!< MJPEG back idle interrupt */
    MJPEG_INT_SWAP,            /*!< MJPEG swap memory block interrupt */
    MJPEG_INT_ALL,             /*!< MJPEG all interrupt type */
} MJPEG_INT_Type;

/**
 *  @brief MJPEG configuration strcut definition
 */
typedef struct
{
    MJPEG_Burst_Type burst;      /*!< MJPEG burst type */
    uint8_t quality;             /*!< MJPEG quantization selection, 1-75:Q table selection, others:Q100(lossless) */
    MJPEG_YUV_Mode_Type yuv;     /*!< MJPEG control YUV mode */
    uint16_t waitCount;          /*!< Cycle count in wait state, default value:0x400 */
    uint32_t bufferMjpeg;        /*!< MJPEG buffer addr */
    uint32_t sizeMjpeg;          /*!< MJPEG buffer size */
    uint32_t bufferCamYY;        /*!< CAM buffer address of Y frame */
    uint32_t sizeCamYY;          /*!< CAM buffer size of Y frame */
    uint32_t bufferCamUV;        /*!< CAM buffer address of UV frame */
    uint32_t sizeCamUV;          /*!< CAM buffer size of UV frame */
    uint16_t resolutionX;        /*!< CAM RESOLUTION X */
    uint16_t resolutionY;        /*!< CAM RESOLUTION Y */
    BL_Fun_Type bitOrderEnable;  /*!< MJPEG bitstream order adjustment */
    BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */
    BL_Fun_Type swapModeEnable;  /*!< Enable or disable write swap mode */
    BL_Fun_Type overStopEnable;  /*!< Enable:if camera overwrite error occur,mjpeg will stop fetch data */
    BL_Fun_Type reflectDmy;      /*!< UV dummy with relect */
    BL_Fun_Type verticalDmy;     /*!< MJPEG last half vertical block with dummy data 0x80 */
    BL_Fun_Type horizationalDmy; /*!< MJPEG last half horizational block with dummy data 0x80 */
} MJPEG_CFG_Type;

/**
 *  @brief MJPEG packet configuration strcut definition
 */
typedef struct
{
    BL_Fun_Type packetEnable; /*!< Enable or disable packet mode */
    BL_Fun_Type endToTail;    /*!< Enable or disable jpeg end jump to packet tail */
    uint16_t frameHead;       /*!< Preserve head memory space for each frame */
    BL_Fun_Type frameTail;    /*!< Enable:auto fill tail 0xFF and 0xD9 */
    uint16_t packetHead;      /*!< Packet head byte count */
    uint16_t packetBody;      /*!< Packet body byte count */
    uint16_t packetTail;      /*!< Packet tail byte count */
} MJPEG_Packet_Type;

/**
 *  @brief MJPEG frame information strcut definition
 */
typedef struct
{
    uint8_t validFrames;    /*!< Valid frames */
    uint32_t curFrameAddr;  /*!< Current frame address */
    uint32_t curFrameBytes; /*!< Current frame bytes */
    uint8_t curFrameQ;      /*!< Current frame Q mode */
    uint32_t status;        /*!< MJPEG module status */
} MJPEG_Frame_Info;

/*@} end of group MJPEG_Public_Types */

/** @defgroup  MJPEG_Public_Constants
 *  @{
 */

/** @defgroup  MJPEG_YUV_MODE_TYPE
 *  @{
 */
#define IS_MJPEG_YUV_MODE_TYPE(type) (((type) == MJPEG_YUV420) ||        \
                                      ((type) == MJPEG_YUV400) ||        \
                                      ((type) == MJPEG_YUV422_PLANAR) || \
                                      ((type) == MJPEG_YUV422_INTERLEAVE))

/** @defgroup  MJPEG_BURST_TYPE
 *  @{
 */
#define IS_MJPEG_BURST_TYPE(type) (((type) == MJPEG_BURST_SINGLE) || \
                                   ((type) == MJPEG_BURST_INCR4) ||  \
                                   ((type) == MJPEG_BURST_INCR8) ||  \
                                   ((type) == MJPEG_BURST_INCR16))

/** @defgroup  MJPEG_SWAP_BLOCK_TYPE
 *  @{
 */
#define IS_MJPEG_SWAP_BLOCK_TYPE(type) (((type) == MJPEG_BLOCK_0) || \
                                        ((type) == MJPEG_BLOCK_1))

/** @defgroup  MJPEG_INT_TYPE
 *  @{
 */
#define IS_MJPEG_INT_TYPE(type) (((type) == MJPEG_INT_NORMAL) ||          \
                                 ((type) == MJPEG_INT_CAM_OVERWRITE) ||   \
                                 ((type) == MJPEG_INT_MEM_OVERWRITE) ||   \
                                 ((type) == MJPEG_INT_FRAME_OVERWRITE) || \
                                 ((type) == MJPEG_INT_BACK_IDLE) ||       \
                                 ((type) == MJPEG_INT_SWAP) ||            \
                                 ((type) == MJPEG_INT_ALL))

/*@} end of group MJPEG_Public_Constants */

/** @defgroup  MJPEG_Public_Macros
 *  @{
 */

/*@} end of group MJPEG_Public_Macros */

/** @defgroup  MJPEG_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void MJPEG_IRQHandler(void);
#endif
void MJPEG_Init(MJPEG_CFG_Type *cfg);
void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg);
void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0);
void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv);
void MJPEG_Deinit(void);
void MJPEG_Enable(void);
void MJPEG_Disable(void);
void MJPEG_SW_Enable(uint8_t count);
void MJPEG_SW_Run(void);
void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info);
uint8_t MJPEG_Get_Frame_Count(void);
void MJPEG_Pop_Frame(void);
void MJPEG_Current_Block_Clear(void);
MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void);
BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block);
BL_Sts_Type MJPEG_Current_Block_Is_Start(void);
BL_Sts_Type MJPEG_Current_Block_Is_End(void);
uint32_t MJPEG_Get_Remain_Bit(void);
void MJPEG_Set_Frame_Threshold(uint8_t count);
void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask);
void MJPEG_IntClr(MJPEG_INT_Type intType);
void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun);

/*@} end of group MJPEG_Public_Functions */

/*@} end of group MJPEG */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_MJPEG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nf_cfg.h
================================================
/**
  ******************************************************************************
  * @file    bl702_nf_cfg.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_NF_CFG_H__
#define __BL702_NF_CFG_H__

#include "string.h"
#include "bl702_nflash.h"
#include "bl702_sf_ctrl.h"

/** @defgroup  NF_CFG_Public_Functions
 *  @{
 */
uint32_t NF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, Nand_Flash_Cfg_Type *pFlashCfg);

#endif /* __BL702_NF_CFG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_nflash.h
================================================
/**
  ******************************************************************************
  * @file    bl702_nflah.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_NFLAH_H__
#define __BL702_NFLAH_H__

#include "bl702_common.h"
#include "bl702_sf_ctrl.h"

/** @addtogroup  BL602_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SFLAH
 *  @{
 */

/** @defgroup  SFLAH_Public_Types
 *  @{
 */

/**
 *  @brief Serial flash configuration structure type definition
 */
/*@} end of group SFLAH_Public_Types */

/** @defgroup  SFLAH_Public_Constants
 *  @{
 */

/*@} end of group SFLAH_Public_Constants */

/** @defgroup  SFLAH_Public_Macros
 *  @{
 */
#define BFLB_NAND_FLASH_BLK_DATA_SIZE   (128 * 1024)
#define BFLB_NAND_FLASH_BLK_TOTAL_SIZE  ((128 + 4) * 1024)
#define BFLB_NAND_FLASH_PAGE_SIZE       (2048)
#define BFLB_NAND_FLASH_PAGE_TOTAL_SIZE (2048 + 64)
#define BFLB_NAND_FLASH_PAGES_PER_BLOCK (64)
#define BFLB_NAND_FLASH_CMD_INVALID     (0xff)
#define DISK_SECTOR_SIZE                (512)
typedef unsigned char BYTE;
typedef unsigned long DWORD;
typedef unsigned int UINT;
typedef BYTE DSTATUS;
typedef enum {
    RES_OK = 0, /* 0: Successful */
    RES_ERROR,  /* 1: R/W Error */
    RES_WRPRT,  /* 2: Write Protected */
    RES_NOTRDY, /* 3: Not Ready */
    RES_PARERR  /* 4: Invalid Parameter */
} DRESULT;

typedef enum {
    READ_DATA_FROM_CACHE = 0,       //date:2048 bytes in each page
    READ_SPARE_DATA_FROM_CACHE = 1, //spare date:64 bytes in each page
} BL_Nand_Flash_READ_DATE_TYPE;

typedef struct
{
    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
    uint8_t resetEnCmd;           /*!< Flash enable reset command */
    uint8_t resetCmd;             /*!< Flash reset command */
    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
    uint8_t qpiJedecIdCmd;        /*!< QPI JEDEC ID comamnd */
    uint8_t qpiJedecIdCmdDmyClk;  /*!< QPI JEDEC ID command dummy clock */
    uint8_t sectorSize;           /*!< *1024bytes */
    uint8_t mid;                  /*!< Manufacturer ID */
    uint16_t pageSize;            /*!< Page size */
    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
    uint8_t sectorEraseCmd;       /*!< Sector erase command */
    uint8_t blk128EraseCmd;       /*!< Block 128K erase command */
    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
    uint8_t programLoadCmd;       /*!< Program Load cmd */
    uint8_t qprogramLoadCmd;      /*!< Program Load cmd x4*/
    uint8_t pageProgramCmd;       /*!< Page program cmd */
    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
    uint8_t qppAddrMode;          /*!< QIO page program address mode */
    uint8_t pageReadToCacheCmd;   /*!< Page read comamnd */
    uint8_t getFeaturesCmd;       /*!< GET FEATURES command to read the status */
    uint8_t setFeaturesCmd;       /*!< SET FEATURES command to read the status */
    uint8_t readFromCacheCmd;     /*!< Read from cache command */
    uint8_t fastReadCmd;          /*!< Fast read command */
    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
    uint8_t wrEnableIndex;        /*!< Write enable register index */
    uint8_t qeIndex;              /*!< Quad mode enable register index */
    uint8_t busyIndex;            /*!< Busy status register index */
    uint8_t wrEnableBit;          /*!< Write enable bit pos */
    uint8_t qeBit;                /*!< Quad enable bit pos */
    uint8_t busyBit;              /*!< Busy status bit pos */
    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
    uint8_t releasePowerDown;     /*!< Release power down command */
    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
    uint8_t readRegCmd[4];        /*!< Read register command buffer */
    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
    uint8_t enterQpi;             /*!< Enter qpi command */
    uint8_t exitQpi;              /*!< Exit qpi command */
    uint8_t cReadMode;            /*!< Config data for continuous read mode */
    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
    uint16_t timeEsector;         /*!< 4K erase time */
    uint16_t timeE132k;           /*!< 132K erase time */
    uint16_t timePagePgm;         /*!< Page program time */
    uint16_t timeCe;              /*!< Chip erase time in ms */
    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
    uint8_t qeData;               /*!< QE set data */
} __attribute__((packed)) Nand_Flash_Cfg_Type;

//BL_Nand_Flash_Program_Bit_Err_Type ATTR_TCM_SECTION NFlash_Pass(uint8_t errorCode, BL_Nand_Flash_OP_Type opType);
BL_Err_Type NFlash_GetJedecId(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data);
BL_Err_Type ATTR_TCM_SECTION NFlash_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t startAddr, uint32_t endAddr);
BL_Err_Type ATTR_TCM_SECTION NFlash_Blk128_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum);
BL_Err_Type ATTR_TCM_SECTION NFlash_Write_Enable(Nand_Flash_Cfg_Type *flashCfg);
BL_Err_Type ATTR_TCM_SECTION NFlash_Read(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type ATTR_TCM_SECTION NFlash_Program(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
BL_Err_Type ATTR_TCM_SECTION NFlash_Page_Read_To_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t absolutePageNum);
BL_Err_Type ATTR_TCM_SECTION NFlash_Get_Feature(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data, uint8_t cmdType);
BL_Err_Type ATTR_TCM_SECTION NFlash_Read_From_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t readType);
BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Execute(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr);
BL_Err_Type ATTR_TCM_SECTION NFlash_Set_Feature(Nand_Flash_Cfg_Type *flashCfg);
BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Load(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
BL_Err_Type ATTR_TCM_SECTION NFlash_Check_Bad_Block(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum, uint8_t *data, uint32_t len);
DRESULT ff_disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
DRESULT ff_disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
DSTATUS ff_disk_initialize(BYTE pdrv);

/*@} end of group SFLAH_Public_Functions */

/*@} end of group SFLAH */

/*@} end of group BL602_Peripheral_Driver */

#endif /* __BL602_SFLAH_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pds.h
================================================
/**
  ******************************************************************************
  * @file    bl702_pds.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_PDS_H__
#define __BL702_PDS_H__

#include "pds_reg.h"
#include "bl702_ef_ctrl.h"
#include "bl702_aon.h"
#include "bl702_hbn.h"
#include "bl702_sflash.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PDS
 *  @{
 */

/** @defgroup  PDS_Public_Types
 *  @{
 */

/**
 *  @brief PDS LDO level type definition
 */
typedef enum {
    PDS_LDO_LEVEL_0P60V = 0,  /*!< PDS LDO voltage 0.60V */
    PDS_LDO_LEVEL_0P65V = 1,  /*!< PDS LDO voltage 0.65V */
    PDS_LDO_LEVEL_0P70V = 2,  /*!< PDS LDO voltage 0.70V */
    PDS_LDO_LEVEL_0P75V = 3,  /*!< PDS LDO voltage 0.75V */
    PDS_LDO_LEVEL_0P80V = 4,  /*!< PDS LDO voltage 0.80V */
    PDS_LDO_LEVEL_0P85V = 5,  /*!< PDS LDO voltage 0.85V */
    PDS_LDO_LEVEL_0P90V = 6,  /*!< PDS LDO voltage 0.90V */
    PDS_LDO_LEVEL_0P95V = 7,  /*!< PDS LDO voltage 0.95V */
    PDS_LDO_LEVEL_1P00V = 8,  /*!< PDS LDO voltage 1.00V */
    PDS_LDO_LEVEL_1P05V = 9,  /*!< PDS LDO voltage 1.05V */
    PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
    PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
    PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
    PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
    PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
    PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
} PDS_LDO_LEVEL_Type;

/**
 *  @brief PDS RAM configuration type definition
 */
typedef struct
{
    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N  : 1;  /*!< [0] 0~16KB cpu_ram RET1N */
    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1;  /*!< [1] 16~32KB cpu_ram RET1N */
    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1;  /*!< [2] 32~48KB cpu_ram RET1N */
    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1;  /*!< [3] 48~64KB cpu_ram RET1N */
    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N  : 1;  /*!< [4] 0~16KB cpu_ram RET2N */
    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1;  /*!< [5] 16~32KB cpu_ram RET2N */
    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1;  /*!< [6] 32~48KB cpu_ram RET2N */
    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1;  /*!< [7] 48~64KB cpu_ram RET2N */
    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN   : 1;  /*!< [8] 0~16KB cpu_ram PGEN */
    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN  : 1;  /*!< [9] 16~32KB cpu_ram PGEN */
    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN  : 1;  /*!< [10] 32~48KB cpu_ram PGEN */
    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN  : 1;  /*!< [11] 48~64KB cpu_ram PGEN */
    uint32_t PDS_RAM_CFG_RSV                     : 20; /*!< [31:12]reserve */
} PDS_RAM_CFG_Type;

/**
 *  @brief PDS PAD pin configuration type definition
 */
typedef enum {
    PDS_PAD_PIN_GPIO_17, /*!< PAD GPIO 17 */
    PDS_PAD_PIN_GPIO_18, /*!< PAD GPIO 18 */
    PDS_PAD_PIN_GPIO_19, /*!< PAD GPIO 19 */
    PDS_PAD_PIN_GPIO_20, /*!< PAD GPIO 20 */
    PDS_PAD_PIN_GPIO_21, /*!< PAD GPIO 21 */
    PDS_PAD_PIN_GPIO_22, /*!< PAD GPIO 22 */
    PDS_PAD_PIN_GPIO_23, /*!< PAD GPIO 23 */
    PDS_PAD_PIN_GPIO_24, /*!< PAD GPIO 24 */
    PDS_PAD_PIN_GPIO_25, /*!< PAD GPIO 25 */
    PDS_PAD_PIN_GPIO_26, /*!< PAD GPIO 26 */
    PDS_PAD_PIN_GPIO_27, /*!< PAD GPIO 27 */
    PDS_PAD_PIN_GPIO_28, /*!< PAD GPIO 28 */
} PDS_PAD_PIN_Type;

/**
 *  @brief PDS PAD configuration type definition
 */
typedef enum {
    PDS_PAD_CFG_PULL_NONE, /*!< no PD/PU/IE on PAD */
    PDS_PAD_CFG_PULL_DOWN, /*!< Pulldown PAD */
    PDS_PAD_CFG_PULL_UP,   /*!< Pullup PAD */
    PDS_PAD_CFG_ACTIVE_IE, /*!< Active IE */
} PDS_PAD_CFG_Type;

/**
 *  @brief PDS configuration type definition
 */
typedef struct
{
    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
    uint32_t reserved20              : 1; /*!< [20]Reserved */
    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
} PDS_CFG_Type;

/**
 *  @brief PDS configuration type definition
 */
typedef struct
{
    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
    uint32_t reserved20              : 1; /*!< [20]Reserved */
    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
} PDS_CTL_Type;

/**
 *  @brief PDS force configuration type definition
 */
typedef struct
{
    uint32_t forceCpuPwrOff  : 1;  /*!< [0]manual force NP power off */
    uint32_t rsv1            : 1;  /*!< [1]reserve */
    uint32_t forceBzPwrOff   : 1;  /*!< [2]manual force BZ power off */
    uint32_t forceUsbPwrOff  : 1;  /*!< [3]manual force USB power off */
    uint32_t forceCpuIsoEn   : 1;  /*!< [4]manual force NP isolation */
    uint32_t rsv5            : 1;  /*!< [5]reserve */
    uint32_t forceBzIsoEn    : 1;  /*!< [6]manual force BZ isolation */
    uint32_t forceUsbIsoEn   : 1;  /*!< [7]manual force USB isolation */
    uint32_t forceCpuPdsRst  : 1;  /*!< [8]manual force NP pds reset */
    uint32_t rsv9            : 1;  /*!< [9]reserve */
    uint32_t forceBzPdsRst   : 1;  /*!< [10]manual force BZ pds reset */
    uint32_t forceUsbPdsRst  : 1;  /*!< [11]manual force USB pds reset */
    uint32_t forceCpuMemStby : 1;  /*!< [12]manual force NP memory sleep */
    uint32_t rsv13           : 1;  /*!< [13]reserve */
    uint32_t forceBzMemStby  : 1;  /*!< [14]manual force BZ memory sleep */
    uint32_t forceUsbMemStby : 1;  /*!< [15]manual force USB memory sleep */
    uint32_t forceCpuGateClk : 1;  /*!< [16]manual force NP clock gated */
    uint32_t rsv17           : 1;  /*!< [17]reserve */
    uint32_t forceBzGateClk  : 1;  /*!< [18]manual force BZ clock gated */
    uint32_t forceUsbGateClk : 1;  /*!< [19]manual force USB clock gated */
    uint32_t rsv20_31        : 12; /*!< [31:20]reserve */
} PDS_CTL2_Type;

/**
 *  @brief PDS force configuration type definition
 */
typedef struct
{
    uint32_t rsv0             : 1; /*!< [0]reserve */
    uint32_t forceMiscPwrOff  : 1; /*!< [1]manual force MISC pwr_off */
    uint32_t forceBlePwrOff   : 1; /*!< [2]manual force BZ_BLE pwr_off */
    uint32_t rsv3_4           : 2; /*!< [4:3]reserve */
    uint32_t forceBleIsoEn    : 1; /*!< [5]manual force BZ_BLE iso_en */
    uint32_t rsv6             : 1; /*!< [6]reserve */
    uint32_t forceMiscPdsRst  : 1; /*!< [7]manual force MISC pds_rst */
    uint32_t forceBlePdsRst   : 1; /*!< [8]manual force BZ_BLE pds_rst */
    uint32_t rsv9             : 1; /*!< [9]reserve */
    uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */
    uint32_t forceBleMemStby  : 1; /*!< [11]manual force BZ_BLE mem_stby */
    uint32_t rsv12            : 1; /*!< [12]reserve */
    uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */
    uint32_t forceBleGateClk  : 1; /*!< [14]manual force BZ_BLE gate_clk */
    uint32_t rsv15_23         : 9; /*!< [23:15]reserve */
    uint32_t CpuIsoEn         : 1; /*!< [24]make NP isolated at PDS Sleep state */
    uint32_t rsv25_26         : 2; /*!< [26:25]reserve */
    uint32_t BzIsoEn          : 1; /*!< [27]make BZ isolated at PDS Sleep state */
    uint32_t BleIsoEn         : 1; /*!< [28]make Ble isolated at PDS Sleep state */
    uint32_t UsbIsoEn         : 1; /*!< [29]make USB isolated at PDS Sleep state */
    uint32_t MiscIsoEn        : 1; /*!< [30]make misc isolated at PDS Sleep state */
    uint32_t rsv31            : 1; /*!< [31]reserve */
} PDS_CTL3_Type;

/**
 *  @brief PDS force configuration type definition
 */
typedef struct
{
    uint32_t cpuPwrOff     : 1; /*!< [0] */
    uint32_t cpuRst        : 1; /*!< [1] */
    uint32_t cpuMemStby    : 1; /*!< [2] */
    uint32_t cpuGateClk    : 1; /*!< [3] */
    uint32_t rsv4_11       : 8; /*!< [11:4]reserve */
    uint32_t BzPwrOff      : 1; /*!< [12] */
    uint32_t BzRst         : 1; /*!< [13] */
    uint32_t BzMemStby     : 1; /*!< [14] */
    uint32_t BzGateClk     : 1; /*!< [15] */
    uint32_t BlePwrOff     : 1; /*!< [16] */
    uint32_t BleRst        : 1; /*!< [17] */
    uint32_t BleMemStby    : 1; /*!< [18] */
    uint32_t BleGateClk    : 1; /*!< [19] */
    uint32_t UsbPwrOff     : 1; /*!< [20] */
    uint32_t UsbRst        : 1; /*!< [21] */
    uint32_t UsbMemStby    : 1; /*!< [22] */
    uint32_t UsbGateClk    : 1; /*!< [23] */
    uint32_t MiscPwrOff    : 1; /*!< [24] */
    uint32_t MiscRst       : 1; /*!< [25] */
    uint32_t MiscMemStby   : 1; /*!< [26] */
    uint32_t MiscGateClk   : 1; /*!< [27] */
    uint32_t rsv28_29      : 2; /*!< [29:28]reserve */
    uint32_t MiscAnaPwrOff : 1; /*!< [30] */
    uint32_t MiscDigPwrOff : 1; /*!< [31] */
} PDS_CTL4_Type;

/**
 *  @brief PDS default level configuration type definition
 */
typedef struct
{
    PDS_CTL_Type pdsCtl;   /*!< PDS_CTL configuration */
    PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
    PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
    PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
} PDS_DEFAULT_LV_CFG_Type;

/**
 *  @brief PDS interrupt type definition
 */
typedef enum {
    PDS_INT_WAKEUP = 0,    /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
    PDS_INT_RF_DONE,       /*!< PDS RF done interrupt */
    PDS_INT_PLL_DONE,      /*!< PDS PLL done interrupt */
    PDS_INT_PDS_SLEEP_CNT, /*!< wakeup trigger by pds_sleep_cnt=0 */
    PDS_INT_HBN_IRQ_OUT0,  /*!< wakeup trigger by hbn_irq_out[0] */
    PDS_INT_HBN_IRQ_OUT1,  /*!< wakeup trigger by hbn_irq_out[1] */
    PDS_INT_GPIO_IRQ,      /*!< wakeup trigger by gpio_irq */
    PDS_INT_IRRX,          /*!< wakeup trigger by irrx_int */
    PDS_INT_BLE_SLP_IRQ,   /*!< wakeup trigger by ble_slp_irq */
    PDS_INT_USB_WKUP,      /*!< wakeup trigger by usb_wkup */
    PDS_INT_KYS_QDEC,      /*!< wakeup trigger by kys_int or qdec */
    PDS_INT_MAX,           /*!< PDS int max number */
} PDS_INT_Type;

/**
 *  @brief PDS vddcore GPIO interrupt type definition
 */
typedef enum {
    PDS_VDDCORE_GPIO_SRC_GPIO_0, /*!< PDS VDDCORE GPIO0 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_1, /*!< PDS VDDCORE GPIO1 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_2, /*!< PDS VDDCORE GPIO2 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_3, /*!< PDS VDDCORE GPIO3 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_4, /*!< PDS VDDCORE GPIO4 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_5, /*!< PDS VDDCORE GPIO5 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_6, /*!< PDS VDDCORE GPIO6 as PDS interrupt source */
    PDS_VDDCORE_GPIO_SRC_GPIO_7, /*!< PDS VDDCORE GPIO7 as PDS interrupt source */
} PDS_VDDCORE_GPIO_SRC_Type;

/**
 *  @brief PDS reset event type definition
 */
typedef enum {
    PDS_RST_EVENT_BUS_RST,        /*!< hreset_n (Bus Reset) */
    PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */
    PDS_RST_EVENT_PDS_RST,        /*!< pds_rst_n (pds reset) */
    PDS_RST_EVENT_MAX,            /*!< PDS rst event max number */
} PDS_RST_EVENT_Type;

/**
 *  @brief PDS PLL status type definition
 */
typedef enum {
    PDS_PLL_STS_OFF = 0,   /*!< 2'b00 */
    PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */
    PDS_PLL_STS_PU = 2,    /*!< 2'b10 */
    PDS_PLL_STS_RDY = 3,   /*!< 2'b11 */
} PDS_PLL_STS_Type;

/**
 *  @brief PDS RF status type definition
 */
typedef enum {
    PDS_RF_STS_OFF = 0,        /*!< 4'b0000 */
    PDS_RF_STS_PU_MBG = 1,     /*!< 4'b0001 */
    PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */
    PDS_RF_STS_PU_SFREG = 7,   /*!< 4'b0111 */
    PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */
} PDS_RF_STS_Type;

/**
 *  @brief PDS status type definition
 */
typedef enum {
    PDS_STS_IDLE = 0,            /*!< 4'b0000 */
    PDS_STS_ECG = 8,             /*!< 4'b1000 */
    PDS_STS_ERST = 12,           /*!< 4'b1100 */
    PDS_STS_EISO = 15,           /*!< 4'b1111 */
    PDS_STS_POFF = 7,            /*!< 4'b0111 */
    PDS_STS_PRE_BGON = 3,        /*!< 4'b0011 */
    PDS_STS_PRE_BGON1 = 1,       /*!< 4'b0001 */
    PDS_STS_BGON = 5,            /*!< 4'b0101 */
    PDS_STS_CLK_SW_32M = 4,      /*!< 4'b0100 */
    PDS_STS_PON_DCDC = 6,        /*!< 4'b0110 */
    PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */
    PDS_STS_PON = 10,            /*!< 4'b1010 */
    PDS_STS_DISO = 2,            /*!< 4'b0010 */
    PDS_STS_DCG = 13,            /*!< 4'b1101 */
    PDS_STS_DRST = 11,           /*!< 4'b1011 */
    PDS_STS_WAIT_EFUSE = 9,      /*!< 4'b1001 */
} PDS_STS_Type;

/**
 *  @brief PLL XTAL type definition
 */
typedef enum {
    PDS_PLL_XTAL_NONE,  /*!< XTAL is none */
    PDS_PLL_XTAL_32M,   /*!< XTAL is 32M */
    PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
} PDS_PLL_XTAL_Type;

/**
 *  @brief PLL output clock type definition
 */
typedef enum {
    PDS_PLL_CLK_480M, /*!< PLL output clock:480M */
    PDS_PLL_CLK_240M, /*!< PLL output clock:240M */
    PDS_PLL_CLK_192M, /*!< PLL output clock:192M */
    PDS_PLL_CLK_160M, /*!< PLL output clock:160M */
    PDS_PLL_CLK_120M, /*!< PLL output clock:120M */
    PDS_PLL_CLK_96M,  /*!< PLL output clock:96M */
    PDS_PLL_CLK_80M,  /*!< PLL output clock:80M */
    PDS_PLL_CLK_48M,  /*!< PLL output clock:48M */
    PDS_PLL_CLK_32M,  /*!< PLL output clock:32M */
} PDS_PLL_CLK_Type;

/**
 *  @brief PDS level 0-7 mode HBN GPIO interrupt trigger type definition
 */
typedef enum {
    PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync falling edge trigger */
    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync rising edge trigger */
    PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync low level trigger */
    PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync high level trigger */
    PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async falling edge trigger */
    PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async rising edge trigger */
    PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async low level trigger */
    PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async high level trigger */
} PDS_AON_GPIO_INT_Trigger_Type;

/**
 *  @brief PDS APP configuration type definition
 */
typedef struct
{
    uint8_t pdsLevel;                                 /*!< PDS level */
    uint8_t turnOffXtal32m;                           /*!< Wheather turn off XTAL32M */
    uint8_t turnOffDll;                               /*!< Wheather turn off DLL */
    uint8_t turnOffRF;                                /*!< Wheather turn off RF */
    uint8_t useXtal32k;                               /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
    uint8_t pdsAonGpioWakeupSrc;                      /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */
    PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */
    uint8_t powerDownFlash;                           /*!< Whether power down flash */
    uint8_t pdsHoldGpio;                              /*!< Whether pds hold gpio level */
    uint8_t turnOffFlashPad;                          /*!< Whether turn off flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */
    uint8_t flashPinCfg;                              /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
    uint8_t turnoffPLL;                               /*!< Whether trun off PLL */
    uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
    uint8_t flashContRead;                            /*!< Whether enable flash continue read */
    uint32_t sleepTime;                               /*!< PDS sleep time */
    SPI_Flash_Cfg_Type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
    HBN_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
    void (*preCbFun)(void);                           /*!< Pre callback function */
    void (*postCbFun)(void);                          /*!< Post callback function */
} PDS_APP_CFG_Type;

/**
 *  @brief PDS LDO voltage type definition
 */
typedef enum {
    PDS_LDO_VOLTAGE_0P60V, /*!< PDS LDO voltage 0.60V */
    PDS_LDO_VOLTAGE_0P65V, /*!< PDS LDO voltage 0.65V */
    PDS_LDO_VOLTAGE_0P70V, /*!< PDS LDO voltage 0.70V */
    PDS_LDO_VOLTAGE_0P75V, /*!< PDS LDO voltage 0.75V */
    PDS_LDO_VOLTAGE_0P80V, /*!< PDS LDO voltage 0.80V */
    PDS_LDO_VOLTAGE_0P85V, /*!< PDS LDO voltage 0.85V */
    PDS_LDO_VOLTAGE_0P90V, /*!< PDS LDO voltage 0.9V */
    PDS_LDO_VOLTAGE_0P95V, /*!< PDS LDO voltage 0.95V */
    PDS_LDO_VOLTAGE_1P00V, /*!< PDS LDO voltage 1.0V */
    PDS_LDO_VOLTAGE_1P05V, /*!< PDS LDO voltage 1.05V */
    PDS_LDO_VOLTAGE_1P10V, /*!< PDS LDO voltage 1.1V */
    PDS_LDO_VOLTAGE_1P15V, /*!< PDS LDO voltage 1.15V */
    PDS_LDO_VOLTAGE_1P20V, /*!< PDS LDO voltage 1.2V */
    PDS_LDO_VOLTAGE_1P25V, /*!< PDS LDO voltage 1.25V */
    PDS_LDO_VOLTAGE_1P30V, /*!< PDS LDO voltage 1.3V */
    PDS_LDO_VOLTAGE_1P35V, /*!< PDS LDO voltage 1.35V */
} PDS_LDO_VOLTAGE_Type;

/**
 *  @brief PDS auto power down configuration type definition
 */
typedef struct
{
    BL_Fun_Type mbgPower;      /*!< PDS auto [31] MBG power */
    BL_Fun_Type ldo18rfPower;  /*!< PDS auto [30] LDO18RF power */
    BL_Fun_Type sfregPower;    /*!< PDS auto [29] SF_REG power */
    BL_Fun_Type pllPower;      /*!< PDS auto [28] PLL power */
    BL_Fun_Type cpu0Power;     /*!< PDS auto [19] NP power */
    BL_Fun_Type rc32mPower;    /*!< PDS auto [17] RC32M power */
    BL_Fun_Type xtalPower;     /*!< PDS auto [14] XTAL power */
    BL_Fun_Type allPower;      /*!< PDS auto [13] all power */
    BL_Fun_Type isoPower;      /*!< PDS auto [11] ISO power */
    BL_Fun_Type bzPower;       /*!< PDS auto [10] BZ power */
    BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */
    BL_Fun_Type cgPower;       /*!< PDS auto [8] CG power */
    BL_Fun_Type cpu1Power;     /*!< PDS auto [7] AP power */
    BL_Fun_Type usbPower;      /*!< PDS auto [3] USB power */
} PDS_AUTO_POWER_DOWN_CFG_Type;

/**
 *  @brief PDS auto configuration type definition
 */
typedef struct
{
    PDS_LDO_VOLTAGE_Type vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */
    BL_Fun_Type vddcoreVolEn;        /*!< PDS auto [18] VDDCORE voltage enable bit */
    BL_Fun_Type cpu0NotNeedWFI;      /*!< PDS auto [21] NP not need WFI to get in PDS mode */
    BL_Fun_Type cpu1NotNeedWFI;      /*!< PDS auto [20] AP not need WFI to get in PDS mode */
    BL_Fun_Type busReset;            /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */
    BL_Fun_Type disIrqWakeUp;        /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */
    BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */
    BL_Fun_Type sleepForever;        /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */
} PDS_AUTO_NORMAL_CFG_Type;

/**
 *  @brief PDS force type definition
 */
typedef enum {
    PDS_FORCE_NP,  /*!< PDS force NP */
    PDS_FORCE_RSV, /*!< rsv */
    PDS_FORCE_BZ,  /*!< PDS force BZ */
    PDS_FORCE_USB, /*!< PDS force USB */
} PDS_FORCE_Type;

/**
 *  @brief PDS force type definition
 */
typedef enum {
    AUDIO_PLL_12288000_HZ, /*!< PDS AUDIO PLL SET AS 12.288MHZ */
    AUDIO_PLL_11289600_HZ, /*!< PDS AUDIO PLL SET AS 11.2896HZ */
    AUDIO_PLL_5644800_HZ,  /*!< PDS AUDIO PLL SET AS 2.822400HZ */
    AUDIO_PLL_24576000_HZ, /*!< PDS AUDIO PLL SET AS 24.576000MHZ */
    AUDIO_PLL_24000000_HZ, /*!< PDS AUDIO PLL SET AS 24.000000MHZ */
} PDS_AUDIO_PLL_Type;

/*@} end of group PDS_Public_Types */

/** @defgroup  PDS_Public_Constants
 *  @{
 */

/** @defgroup  PDS_LDO_LEVEL_TYPE
 *  @{
 */
#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \
                                     ((type) == PDS_LDO_LEVEL_0P65V) || \
                                     ((type) == PDS_LDO_LEVEL_0P70V) || \
                                     ((type) == PDS_LDO_LEVEL_0P75V) || \
                                     ((type) == PDS_LDO_LEVEL_0P80V) || \
                                     ((type) == PDS_LDO_LEVEL_0P85V) || \
                                     ((type) == PDS_LDO_LEVEL_0P90V) || \
                                     ((type) == PDS_LDO_LEVEL_0P95V) || \
                                     ((type) == PDS_LDO_LEVEL_1P00V) || \
                                     ((type) == PDS_LDO_LEVEL_1P05V) || \
                                     ((type) == PDS_LDO_LEVEL_1P10V) || \
                                     ((type) == PDS_LDO_LEVEL_1P15V) || \
                                     ((type) == PDS_LDO_LEVEL_1P20V) || \
                                     ((type) == PDS_LDO_LEVEL_1P25V) || \
                                     ((type) == PDS_LDO_LEVEL_1P30V) || \
                                     ((type) == PDS_LDO_LEVEL_1P35V))

/** @defgroup  PDS_PAD_PIN_TYPE
 *  @{
 */
#define IS_PDS_PAD_PIN_TYPE(type) (((type) == PDS_PAD_PIN_GPIO_17) || \
                                   ((type) == PDS_PAD_PIN_GPIO_18) || \
                                   ((type) == PDS_PAD_PIN_GPIO_19) || \
                                   ((type) == PDS_PAD_PIN_GPIO_20) || \
                                   ((type) == PDS_PAD_PIN_GPIO_21) || \
                                   ((type) == PDS_PAD_PIN_GPIO_22) || \
                                   ((type) == PDS_PAD_PIN_GPIO_23) || \
                                   ((type) == PDS_PAD_PIN_GPIO_24) || \
                                   ((type) == PDS_PAD_PIN_GPIO_25) || \
                                   ((type) == PDS_PAD_PIN_GPIO_26) || \
                                   ((type) == PDS_PAD_PIN_GPIO_27) || \
                                   ((type) == PDS_PAD_PIN_GPIO_28))

/** @defgroup  PDS_PAD_CFG_TYPE
 *  @{
 */
#define IS_PDS_PAD_CFG_TYPE(type) (((type) == PDS_PAD_CFG_PULL_NONE) || \
                                   ((type) == PDS_PAD_CFG_PULL_DOWN) || \
                                   ((type) == PDS_PAD_CFG_PULL_UP) ||   \
                                   ((type) == PDS_PAD_CFG_ACTIVE_IE))

/** @defgroup  PDS_INT_TYPE
 *  @{
 */
#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) ||        \
                               ((type) == PDS_INT_RF_DONE) ||       \
                               ((type) == PDS_INT_PLL_DONE) ||      \
                               ((type) == PDS_INT_PDS_SLEEP_CNT) || \
                               ((type) == PDS_INT_HBN_IRQ_OUT0) ||  \
                               ((type) == PDS_INT_HBN_IRQ_OUT1) ||  \
                               ((type) == PDS_INT_GPIO_IRQ) ||      \
                               ((type) == PDS_INT_IRRX) ||          \
                               ((type) == PDS_INT_BLE_SLP_IRQ) ||   \
                               ((type) == PDS_INT_USB_WKUP) ||      \
                               ((type) == PDS_INT_KYS_QDEC) ||      \
                               ((type) == PDS_INT_MAX))

/** @defgroup  PDS_VDDCORE_GPIO_SRC_TYPE
 *  @{
 */
#define IS_PDS_VDDCORE_GPIO_SRC_TYPE(type) (((type) == PDS_VDDCORE_GPIO_SRC_GPIO_0) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_1) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_2) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_3) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_4) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_5) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_6) || \
                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_7))

/** @defgroup  PDS_RST_EVENT_TYPE
 *  @{
 */
#define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) ||        \
                                     ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \
                                     ((type) == PDS_RST_EVENT_PDS_RST) ||        \
                                     ((type) == PDS_RST_EVENT_MAX))

/** @defgroup  PDS_PLL_STS_TYPE
 *  @{
 */
#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) ||   \
                                   ((type) == PDS_PLL_STS_SFREG) || \
                                   ((type) == PDS_PLL_STS_PU) ||    \
                                   ((type) == PDS_PLL_STS_RDY))

/** @defgroup  PDS_RF_STS_TYPE
 *  @{
 */
#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) ||        \
                                  ((type) == PDS_RF_STS_PU_MBG) ||     \
                                  ((type) == PDS_RF_STS_PU_LDO15RF) || \
                                  ((type) == PDS_RF_STS_PU_SFREG) ||   \
                                  ((type) == PDS_RF_STS_BZ_EN_AON))

/** @defgroup  PDS_STS_TYPE
 *  @{
 */
#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) ||           \
                               ((type) == PDS_STS_ECG) ||            \
                               ((type) == PDS_STS_ERST) ||           \
                               ((type) == PDS_STS_EISO) ||           \
                               ((type) == PDS_STS_POFF) ||           \
                               ((type) == PDS_STS_PRE_BGON) ||       \
                               ((type) == PDS_STS_PRE_BGON1) ||      \
                               ((type) == PDS_STS_BGON) ||           \
                               ((type) == PDS_STS_CLK_SW_32M) ||     \
                               ((type) == PDS_STS_PON_DCDC) ||       \
                               ((type) == PDS_STS_PON_LDO11_MISC) || \
                               ((type) == PDS_STS_PON) ||            \
                               ((type) == PDS_STS_DISO) ||           \
                               ((type) == PDS_STS_DCG) ||            \
                               ((type) == PDS_STS_DRST) ||           \
                               ((type) == PDS_STS_WAIT_EFUSE))

/** @defgroup  PDS_PLL_XTAL_TYPE
 *  @{
 */
#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \
                                    ((type) == PDS_PLL_XTAL_32M) ||  \
                                    ((type) == PDS_PLL_XTAL_RC32M))

/** @defgroup  PDS_PLL_CLK_TYPE
 *  @{
 */
#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \
                                   ((type) == PDS_PLL_CLK_240M) || \
                                   ((type) == PDS_PLL_CLK_192M) || \
                                   ((type) == PDS_PLL_CLK_160M) || \
                                   ((type) == PDS_PLL_CLK_120M) || \
                                   ((type) == PDS_PLL_CLK_96M) ||  \
                                   ((type) == PDS_PLL_CLK_80M) ||  \
                                   ((type) == PDS_PLL_CLK_48M) ||  \
                                   ((type) == PDS_PLL_CLK_32M))

/** @defgroup  PDS_AON_GPIO_INT_TRIGGER_TYPE
 *  @{
 */
#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))

/** @defgroup  PDS_LDO_VOLTAGE_TYPE
 *  @{
 */
#define IS_PDS_LDO_VOLTAGE_TYPE(type) (((type) == PDS_LDO_VOLTAGE_0P60V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P65V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P70V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P75V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P80V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P85V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P90V) || \
                                       ((type) == PDS_LDO_VOLTAGE_0P95V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P00V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P05V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P10V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P15V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P20V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P25V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P30V) || \
                                       ((type) == PDS_LDO_VOLTAGE_1P35V))

/** @defgroup  PDS_FORCE_TYPE
 *  @{
 */
#define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) ||  \
                                 ((type) == PDS_FORCE_RSV) || \
                                 ((type) == PDS_FORCE_BZ) ||  \
                                 ((type) == PDS_FORCE_USB))

/** @defgroup  PDS_AUDIO_PLL_TYPE
 *  @{
 */
#define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \
                                     ((type) == AUDIO_PLL_11289600_HZ) || \
                                     ((type) == AUDIO_PLL_5644800_HZ))

/*@} end of group PDS_Public_Constants */

/** @defgroup  PDS_Public_Macros
 *  @{
 */
#define PDS_LDO_MIN_PU_CNT        (25) /* LDO need 25 cycles to power up */
#define PDS_WARMUP_CNT            (38) /* LDO hw warmup compensation latency cycles */
#define PDS_WARMUP_LATENCY_CNT    (38) /* LDO hw warmup compensation latency cycles */
#define PDS_FORCE_PWR_OFF_OFFSET  (0)
#define PDS_FORCE_ISO_EN_OFFSET   (4)
#define PDS_FORCE_PDS_RST_OFFSET  (8)
#define PDS_FORCE_MEM_STBY_OFFSET (12)
#define PDS_FORCE_GATE_CLK_OFFSET (16)
#define PDS_INT_MASK_BIT_OFFSET   (8)
#define PDS_AON_WAKEUP_GPIO_NONE  (0x00)
#define PDS_AON_WAKEUP_GPIO_9     (0x01)
#define PDS_AON_WAKEUP_GPIO_10    (0x02)
#define PDS_AON_WAKEUP_GPIO_11    (0x04)
#define PDS_AON_WAKEUP_GPIO_12    (0x08)
#define PDS_AON_WAKEUP_GPIO_13    (0x10)
#define PDS_AON_WAKEUP_GPIO_ALL   (0x1E)

/*@} end of group PDS_Public_Macros */

/** @defgroup  PDS_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void PDS_WAKEUP_IRQHandler(void);
#endif
/*----------*/
BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg);
BL_Err_Type PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg);
/*----------*/
BL_Err_Type PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3);
BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt);
/*----------*/
BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable);
BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
BL_Err_Type PDS_IntClear(void);
PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void);
PDS_RF_STS_Type PDS_Get_PdsRfStstus(void);
PDS_STS_Type PDS_Get_PdsStstus(void);
/*----------*/
BL_Err_Type PDS_Clear_Reset_Event(void);
BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event);
/*----------*/
BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src,
                                        PDS_AON_GPIO_INT_Trigger_Type mode);
BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask);
BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void);
BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void);
/*----------*/
BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
/*----------*/
BL_Err_Type PDS_Trim_RC32M(void);
BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void);
BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void);
BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType);
BL_Err_Type PDS_Enable_PLL_All_Clks(void);
BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
BL_Err_Type PDS_Disable_PLL_All_Clks(void);
BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
BL_Err_Type PDS_Power_Off_PLL(void);
BL_Err_Type PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq);
/*----------*/
void PDS_Reset(void);
void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt);
void PDS_Auto_Time_Config(uint32_t sleepDuration);
void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable);
void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain);
void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain);
/*----------*/
BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel);
/*----------*/

/*@} end of group PDS_Public_Functions */

/*@} end of group PDS */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_PDS_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_psram.h
================================================
/**
  ******************************************************************************
  * @file    bl702_psram.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_PSRAM_H__
#define __BL702_PSRAM_H__

#include "sf_ctrl_reg.h"
#include "bl702_common.h"
#include "bl702_sf_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PSRAM
 *  @{
 */

/** @defgroup  PSRAM_Public_Types
 *  @{
 */

/**
 *  @brief Psram drive strength type definition
 */
typedef enum {
    PSRAM_DRIVE_STRENGTH_50_OHMS,  /*!< Drive strength 50 ohms(default) */
    PSRAM_DRIVE_STRENGTH_100_OHMS, /*!< Drive strength 100 ohms */
    PSRAM_DRIVE_STRENGTH_200_OHMS, /*!< Drive strength 200 ohms */
} PSRAM_Drive_Strength;

/**
 *  @brief Psram burst length size type definition
 */
typedef enum {
    PSRAM_BURST_LENGTH_16_BYTES,  /*!< Burst Length 16 bytes */
    PSRAM_BURST_LENGTH_32_BYTES,  /*!< Burst Length 32 bytes */
    PSRAM_BURST_LENGTH_64_BYTES,  /*!< Burst Length 64 bytes */
    PSRAM_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 bytes(default) */
} PSRAM_Burst_Length;

/**
 *  @brief Psram ctrl mode type definition
 */
typedef enum {
    PSRAM_SPI_CTRL_MODE, /*!< Psram SPI ctrl mode */
    PSRAM_QPI_CTRL_MODE, /*!< Psram QPI ctrl mode */
} PSRAM_Ctrl_Mode;

/**
 *  @brief Psram ctrl configuration structure type definition
 */
typedef struct
{
    uint8_t readIdCmd;                  /*!< Read ID command */
    uint8_t readIdDmyClk;               /*!< Read ID command dummy clock */
    uint8_t burstToggleCmd;             /*!< Burst toggle length command */
    uint8_t resetEnableCmd;             /*!< Psram reset enable command */
    uint8_t resetCmd;                   /*!< Psram reset command */
    uint8_t enterQuadModeCmd;           /*!< Psram enter quad mode command */
    uint8_t exitQuadModeCmd;            /*!< Psram exit quad mode command */
    uint8_t readRegCmd;                 /*!< Read register command */
    uint8_t readRegDmyClk;              /*!< Read register command dummy clock */
    uint8_t writeRegCmd;                /*!< Write register command */
    uint8_t readCmd;                    /*!< Psram read command */
    uint8_t readDmyClk;                 /*!< Psram read command dummy clock */
    uint8_t fReadCmd;                   /*!< Psram fast read command */
    uint8_t fReadDmyClk;                /*!< Psram fast read command dummy clock */
    uint8_t fReadQuadCmd;               /*!< Psram fast read quad command */
    uint8_t fReadQuadDmyClk;            /*!< Psram fast read quad command dummy clock */
    uint8_t writeCmd;                   /*!< Psram write command */
    uint8_t quadWriteCmd;               /*!< Psram quad write command */
    uint16_t pageSize;                  /*!< Psram page size */
    PSRAM_Ctrl_Mode ctrlMode;           /*!< Psram ctrl mode */
    PSRAM_Drive_Strength driveStrength; /*!< Psram drive strength */
    PSRAM_Burst_Length burstLength;     /*!< Psram burst length size */
} SPI_Psram_Cfg_Type;

/*@} end of group PSRAM_Public_Types */

/** @defgroup  PSRAM_Public_Constants
 *  @{
 */

/** @defgroup  PSRAM_DRIVE_STRENGTH
 *  @{
 */
#define IS_PSRAM_DRIVE_STRENGTH(type) (((type) == PSRAM_DRIVE_STRENGTH_50_OHMS) ||  \
                                       ((type) == PSRAM_DRIVE_STRENGTH_100_OHMS) || \
                                       ((type) == PSRAM_DRIVE_STRENGTH_200_OHMS))

/** @defgroup  PSRAM_BURST_LENGTH
 *  @{
 */
#define IS_PSRAM_BURST_LENGTH(type) (((type) == PSRAM_BURST_LENGTH_16_BYTES) || \
                                     ((type) == PSRAM_BURST_LENGTH_32_BYTES) || \
                                     ((type) == PSRAM_BURST_LENGTH_64_BYTES) || \
                                     ((type) == PSRAM_BURST_LENGTH_512_BYTES))

/** @defgroup  PSRAM_CTRL_MODE
 *  @{
 */
#define IS_PSRAM_CTRL_MODE(type) (((type) == PSRAM_SPI_CTRL_MODE) || \
                                  ((type) == PSRAM_QPI_CTRL_MODE))

/*@} end of group PSRAM_Public_Constants */

/** @defgroup  PSRAM_Public_Macros
 *  @{
 */

/*@} end of group PSRAM_Public_Macros */

/** @defgroup  PSRAM_Public_Functions
 *  @{
 */

/**
 *  @brief PSRAM Functions
 */
void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg);
void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue);
void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue);
BL_Err_Type Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg);
BL_Err_Type Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg);
void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data);
BL_Err_Type Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg);
BL_Err_Type Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg);
BL_Err_Type Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode);
BL_Err_Type Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode);
BL_Err_Type Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len);
BL_Err_Type Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn,
                                  BL_Fun_Type wbEn, BL_Fun_Type waEn);
BL_Err_Type Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);

/*@} end of group PSRAM_Public_Functions */

/*@} end of group PSRAM */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_PSRAM_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_pwm.h
================================================
/**
 ******************************************************************************
 * @file    bl702_pwm.h
 * @version V1.0
 * @date
 * @brief   This file is the standard driver header file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#ifndef __BL702_PWM_H__
#define __BL702_PWM_H__

#include "bl702_common.h"
#include "pwm_reg.h"


/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PWM
 *  @{
 */

/** @defgroup  PWM_Public_Types
 *  @{
 */

/**
 *  @brief PWM No. type definition
 */
typedef enum {
  PWM_CH0 = 0, /*!< PWM Channel 0 define */
  PWM_CH1,     /*!< PWM Channel 1 define */
  PWM_CH2,     /*!< PWM Channel 2 define */
  PWM_CH3,     /*!< PWM Channel 3 define */
  PWM_CH4,     /*!< PWM Channel 4 define */
  PWM_CH_MAX,  /*!<  */
} PWM_CH_ID_Type;

/**
 *  @brief PWM Clock definition
 */
typedef enum {
  PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */
  PWM_CLK_BCLK,     /*!< PWM Clock source :Bus CLK */
  PWM_CLK_32K,      /*!< PWM Clock source :32K CLK */
} PWM_Clk_Type;

/**
 *  @brief PWM Stop Mode definition
 */
typedef enum {
  PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */
  PWM_STOP_GRACEFUL,   /*!< PWM stop graceful select define */
} PWM_Stop_Mode_Type;

/**
 *  @brief PWM mode type def
 */
typedef enum {
  PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */
  PWM_POL_INVERT,     /*!< PWM invert polarity mode define */
} PWM_Polarity_Type;

/**
 *  @brief PWM interrupt type def
 */
typedef enum {
  PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */
  PWM_INT_ALL,           /*!<  */
} PWM_INT_Type;

/**
 *  @brief PWM configuration structure type definition
 */
typedef struct {
  PWM_CH_ID_Type     ch;          /*!< PWM channel */
  PWM_Clk_Type       clk;         /*!< PWM Clock */
  PWM_Stop_Mode_Type stopMode;    /*!< PWM Stop Mode */
  PWM_Polarity_Type  pol;         /*!< PWM mode type */
  uint16_t           clkDiv;      /*!< PWM clkDiv num */
  uint16_t           period;      /*!< PWM period set */
  uint16_t           threshold1;  /*!< PWM threshold1 num */
  uint16_t           threshold2;  /*!< PWM threshold2 num */
  uint16_t           intPulseCnt; /*!< PWM interrupt pulse count */
} PWM_CH_CFG_Type;

/*@} end of group PWM_Public_Types */

/** @defgroup  PWM_Public_Constants
 *  @{
 */

/** @defgroup  PWM_CH_ID_TYPE
 *  @{
 */
#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0) || ((type) == PWM_CH1) || ((type) == PWM_CH2) || ((type) == PWM_CH3) || ((type) == PWM_CH4) || ((type) == PWM_CH_MAX))

/** @defgroup  PWM_CLK_TYPE
 *  @{
 */
#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || ((type) == PWM_CLK_BCLK) || ((type) == PWM_CLK_32K))

/** @defgroup  PWM_STOP_MODE_TYPE
 *  @{
 */
#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || ((type) == PWM_STOP_GRACEFUL))

/** @defgroup  PWM_POLARITY_TYPE
 *  @{
 */
#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL) || ((type) == PWM_POL_INVERT))

/** @defgroup  PWM_INT_TYPE
 *  @{
 */
#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT) || ((type) == PWM_INT_ALL))

/*@} end of group PWM_Public_Constants */

/** @defgroup  PWM_Public_Macros
 *  @{
 */
#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX)

/*@} end of group PWM_Public_Macros */

/** @defgroup  PWM_Public_Functions
 *  @{
 */

/**
 *  @brief PWM Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void PWM_IRQHandler(void);
#endif
BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg);
void        PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2);
void        PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div);
void        PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1);
void        PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2);
void        PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period);
void        PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2);
void        PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask);
void        PWM_Channel_Enable(PWM_CH_ID_Type ch);
uint8_t     PWM_Channel_Is_Enabled(PWM_CH_ID_Type ch);
void        PWM_Channel_Disable(PWM_CH_ID_Type ch);
void        PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable);
void        PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value);
void        PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun);
BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle);

/*@} end of group PWM_Public_Functions */

/*@} end of group PWM */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_PWM_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_qdec.h
================================================
/**
  ******************************************************************************
  * @file    bl702_qdec.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_QDEC_H__
#define __BL702_QDEC_H__

#include "qdec_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  QDEC
 *  @{
 */

/** @defgroup  QDEC_Public_Types
 *  @{
 */

/**
 *  @brief QDEC port type definition
 */
typedef enum {
    QDEC0_ID,    /*!< QDEC0 port define */
    QDEC1_ID,    /*!< QDEC1 port define */
    QDEC2_ID,    /*!< QDEC2 port define */
    QDEC_ID_MAX, /*!< QDEC MAX ID define */
} QDEC_ID_Type;

/**
 *  @brief QDEC sample work mode type definition
 */
typedef enum {
    QDEC_SAMPLE_SINGLE_MOD,   /*!< Stop sample if rpt_rdy */
    QDEC_SAMPLE_CONTINUE_MOD, /*!< Continue sample */
} QDEC_SAMPLE_MODE_Type;

/**
 *  @brief QDEC sample period type definition
 */
typedef enum {
    QDEC_SAMPLE_PERIOD_32US,  /*!< 32  us at clock 1MHz */
    QDEC_SAMPLE_PERIOD_64US,  /*!< 64  us at clock 1MHz */
    QDEC_SAMPLE_PERIOD_128US, /*!< 128 us at clock 1MHz */
    QDEC_SAMPLE_PERIOD_256US, /*!< 256 us at clock 1MHz */
    QDEC_SAMPLE_PERIOD_512US, /*!< 512 us at clock 1MHz */
    QDEC_SAMPLE_PERIOD_1MS,   /*!< 1   ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_2MS,   /*!< 2   ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_4MS,   /*!< 4   ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_8MS,   /*!< 8   ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_16MS,  /*!< 16  ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_32MS,  /*!< 32  ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_65MS,  /*!< 65  ms at clock 1MHz */
    QDEC_SAMPLE_PERIOD_131MS, /*!< 131 ms at clock 1MHz */
} QDEC_SAMPLE_PERIOD_Type;

/**
 *  @brief QDEC report work mode type definition
 */
typedef enum {
    QDEC_REPORT_SAMPLE_CHANGE_MOD, /*!< Count time only if sample change */
    QDEC_REPORT_TIME_MOD,          /*!< Continue time */
} QDEC_REPORT_MODE_Type;

/**
 *  @brief QDEC sample config structure type definition
 */
typedef struct
{
    QDEC_SAMPLE_MODE_Type sampleMod;      /*!< Sample work mode */
    QDEC_SAMPLE_PERIOD_Type samplePeriod; /*!< Sample period time */
} QDEC_SAMPLE_Type;

/**
 *  @brief QDEC report config structure type definition
 */
typedef struct
{
    QDEC_REPORT_MODE_Type reportMod; /*!< Report work mode */
    uint16_t reportPeriod;           /*!< RPT_US report period in [us/report] = SP * RP */
} QDEC_REPORT_Type;

/**
 *  @brief QDEC acc work mode type definition
 */
typedef enum {
    QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW, /*!< Stop accumulate if overflow */
    QDEC_ACC_CONTINUE_ACCUMULATE,     /*!< Continue accumulate */
} QDEC_ACC_MODE_Type;

/**
 *  @brief QDEC led config structure type definition
 */
typedef struct
{
    BL_Fun_Type ledEn;   /*!< LED enable */
    BL_Fun_Type ledSwap; /*!< LED on/off polarity swap */
    uint16_t ledPeriod;  /*!< Period in us the LED is switched on prior to sampling */
} QDEC_LED_Type;

/**
 *  @brief QDEC deglitch config structure type definition
 */
typedef struct
{
    BL_Fun_Type deglitchEn;   /*!< deglitch enable */
    uint8_t deglitchStrength; /*!< deglitch strength */
} QDEC_DEGLITCH_Type;

/**
 *  @brief QDEC config structure type definition
 */
typedef struct
{
    QDEC_SAMPLE_Type sampleCfg;     /*!< QDEC sample config structure */
    QDEC_REPORT_Type reportCfg;     /*!< QDEC report config structure */
    QDEC_ACC_MODE_Type accMod;      /*!< QDEC acc mode config */
    QDEC_LED_Type ledCfg;           /*!< QDEC led config structure */
    QDEC_DEGLITCH_Type deglitchCfg; /*!< QDEC deglitch config structure */
} QDEC_CFG_Type;

/**
 *  @brief QDEC direction type definition
 */
typedef enum {
    QDEC_DIRECTION_NO_CHANGE,         /*!< Direction of last change no change */
    QDEC_DIRECTION_CLOCKWISE,         /*!< Direction of last change clockwise */
    QDEC_DIRECTION_COUNTER_CLOCKWISE, /*!< Direction of last change counter-clockwise */
    QDEC_DIRECTION_ERROR,             /*!< Direction of last change error */
} QDEC_DIRECTION_Type;

/**
 *  @brief QDEC interrupt type definition
 */
typedef enum {
    QDEC_INT_REPORT,   /*!< report interrupt */
    QDEC_INT_SAMPLE,   /*!< sample interrupt */
    QDEC_INT_ERROR,    /*!< error interrupt */
    QDEC_INT_OVERFLOW, /*!< ACC1 and ACC2 overflow interrupt */
    QDEC_INT_ALL,      /*!< interrupt max num */
} QDEC_INT_Type;

/*@} end of group QDEC_Public_Types */

/** @defgroup  QDEC_Public_Constants
 *  @{
 */

/** @defgroup  QDEC_ID_TYPE
 *  @{
 */
#define IS_QDEC_ID_TYPE(type) (((type) == QDEC0_ID) || \
                               ((type) == QDEC1_ID) || \
                               ((type) == QDEC2_ID) || \
                               ((type) == QDEC_ID_MAX))

/** @defgroup  QDEC_SAMPLE_MODE_TYPE
 *  @{
 */
#define IS_QDEC_SAMPLE_MODE_TYPE(type) (((type) == QDEC_SAMPLE_SINGLE_MOD) || \
                                        ((type) == QDEC_SAMPLE_CONTINUE_MOD))

/** @defgroup  QDEC_SAMPLE_PERIOD_TYPE
 *  @{
 */
#define IS_QDEC_SAMPLE_PERIOD_TYPE(type) (((type) == QDEC_SAMPLE_PERIOD_32US) ||  \
                                          ((type) == QDEC_SAMPLE_PERIOD_64US) ||  \
                                          ((type) == QDEC_SAMPLE_PERIOD_128US) || \
                                          ((type) == QDEC_SAMPLE_PERIOD_256US) || \
                                          ((type) == QDEC_SAMPLE_PERIOD_512US) || \
                                          ((type) == QDEC_SAMPLE_PERIOD_1MS) ||   \
                                          ((type) == QDEC_SAMPLE_PERIOD_2MS) ||   \
                                          ((type) == QDEC_SAMPLE_PERIOD_4MS) ||   \
                                          ((type) == QDEC_SAMPLE_PERIOD_8MS) ||   \
                                          ((type) == QDEC_SAMPLE_PERIOD_16MS) ||  \
                                          ((type) == QDEC_SAMPLE_PERIOD_32MS) ||  \
                                          ((type) == QDEC_SAMPLE_PERIOD_65MS) ||  \
                                          ((type) == QDEC_SAMPLE_PERIOD_131MS))

/** @defgroup  QDEC_REPORT_MODE_TYPE
 *  @{
 */
#define IS_QDEC_REPORT_MODE_TYPE(type) (((type) == QDEC_REPORT_SAMPLE_CHANGE_MOD) || \
                                        ((type) == QDEC_REPORT_TIME_MOD))

/** @defgroup  QDEC_ACC_MODE_TYPE
 *  @{
 */
#define IS_QDEC_ACC_MODE_TYPE(type) (((type) == QDEC_ACC_STOP_SAMPLE_IF_OVERFLOW) || \
                                     ((type) == QDEC_ACC_CONTINUE_ACCUMULATE))

/** @defgroup  QDEC_DIRECTION_TYPE
 *  @{
 */
#define IS_QDEC_DIRECTION_TYPE(type) (((type) == QDEC_DIRECTION_NO_CHANGE) ||         \
                                      ((type) == QDEC_DIRECTION_CLOCKWISE) ||         \
                                      ((type) == QDEC_DIRECTION_COUNTER_CLOCKWISE) || \
                                      ((type) == QDEC_DIRECTION_ERROR))

/** @defgroup  QDEC_INT_TYPE
 *  @{
 */
#define IS_QDEC_INT_TYPE(type) (((type) == QDEC_INT_REPORT) ||   \
                                ((type) == QDEC_INT_SAMPLE) ||   \
                                ((type) == QDEC_INT_ERROR) ||    \
                                ((type) == QDEC_INT_OVERFLOW) || \
                                ((type) == QDEC_INT_ALL))

/*@} end of group QDEC_Public_Constants */

/** @defgroup  QDEC_Public_Macros
 *  @{
 */

/*@} end of group QDEC_Public_Macros */

/** @defgroup  QDEC_Public_Functions
 *  @{
 */

/**
 *  @brief QDEC Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void QDEC0_IRQHandler(void);
void QDEC1_IRQHandler(void);
void QDEC2_IRQHandler(void);
#endif
void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg);
void QDEC_DeInit(QDEC_ID_Type qdecId);
void QDEC_Enable(QDEC_ID_Type qdecId);
void QDEC_Disable(QDEC_ID_Type qdecId);
void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask);
BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun);
BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType);
QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId);
uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId);
uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId);
void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType);

/*@} end of group QDEC_Public_Functions */

/*@} end of group QDEC */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_QDEC_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_romdriver.h
================================================
/**
  ******************************************************************************
  * @file    bl702_romdriver.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_ROMDRIVER_H__
#define __BL702_ROMDRIVER_H__

#include "bl702_common.h"
#include "bl702_aon.h"
#include "bl702_glb.h"
#include "bl702_hbn.h"
#include "bl702_xip_sflash.h"
#include "bl702_sflash.h"
#include "bl702_sf_ctrl.h"
#include "bl702_psram.h"
#include "softcrc.h"

#define ROMAPI_INDEX_SECT_SIZE (0x800)
#define ROMAPI_INDEX_MAX       (ROMAPI_INDEX_SECT_SIZE / 4 - 1)

typedef enum {
    ROM_API_INDEX_REV = 0,

    ROM_API_INDEX_FUNC_START = 4,

    ROM_API_INDEX_AON_Power_On_MBG = ROM_API_INDEX_FUNC_START,
    ROM_API_INDEX_AON_Power_Off_MBG,
    ROM_API_INDEX_AON_Power_On_XTAL,
    ROM_API_INDEX_AON_Set_Xtal_CapCode,
    ROM_API_INDEX_AON_Power_Off_XTAL,

    ROM_API_INDEX_ASM_Delay_Us,
    ROM_API_INDEX_BL702_Delay_US,
    ROM_API_INDEX_BL702_Delay_MS,
    ROM_API_INDEX_BL702_MemCpy,
    ROM_API_INDEX_BL702_MemCpy4,
    ROM_API_INDEX_BL702_MemCpy_Fast,
    ROM_API_INDEX_ARCH_MemCpy_Fast,
    ROM_API_INDEX_BL702_MemSet,
    ROM_API_INDEX_BL702_MemSet4,
    ROM_API_INDEX_BL702_MemCmp,
    ROM_API_INDEX_BFLB_Soft_CRC32,

    ROM_API_INDEX_GLB_Get_Root_CLK_Sel,
    ROM_API_INDEX_GLB_Set_System_CLK_Div,
    ROM_API_INDEX_GLB_Get_BCLK_Div,
    ROM_API_INDEX_GLB_Get_HCLK_Div,
    ROM_API_INDEX_Update_SystemCoreClockWith_XTAL,
    ROM_API_INDEX_GLB_Set_System_CLK,
    ROM_API_INDEX_System_Core_Clock_Update_From_RC32M,
    ROM_API_INDEX_GLB_Set_SF_CLK,
    ROM_API_INDEX_GLB_Power_Off_DLL,
    ROM_API_INDEX_GLB_Power_On_DLL,
    ROM_API_INDEX_GLB_Enable_DLL_All_Clks,
    ROM_API_INDEX_GLB_Enable_DLL_Clk,
    ROM_API_INDEX_GLB_Disable_DLL_All_Clks,
    ROM_API_INDEX_GLB_Disable_DLL_Clk,
    ROM_API_INDEX_GLB_SW_System_Reset,
    ROM_API_INDEX_GLB_SW_CPU_Reset,
    ROM_API_INDEX_GLB_SW_POR_Reset,
    ROM_API_INDEX_GLB_Select_Internal_Flash,
    ROM_API_INDEX_GLB_Swap_Flash_Pin,
    ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin,
    ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin,
    ROM_API_INDEX_GLB_Select_Internal_PSram,
    ROM_API_INDEX_GLB_GPIO_Init,
    ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable,
    ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable,
    ROM_API_INDEX_GLB_GPIO_Set_HZ,
    ROM_API_INDEX_GLB_Deswap_Flash_Pin,
    ROM_API_INDEX_GLB_Select_External_Flash,
    ROM_API_INDEX_GLB_GPIO_Get_Fun,

    ROM_API_INDEX_EF_Ctrl_Busy,
    ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
    ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
    ROM_API_INDEX_EF_Ctrl_Clear,
    ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
    ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
    ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,

    ROM_API_INDEX_PDS_Trim_RC32M,
    ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref,
    ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref,
    ROM_API_INDEX_PDS_Power_On_PLL,
    ROM_API_INDEX_PDS_Enable_PLL_All_Clks,
    ROM_API_INDEX_PDS_Disable_PLL_All_Clks,
    ROM_API_INDEX_PDS_Enable_PLL_Clk,
    ROM_API_INDEX_PDS_Disable_PLL_Clk,
    ROM_API_INDEX_PDS_Power_Off_PLL,
    ROM_API_INDEX_PDS_Reset,
    ROM_API_INDEX_PDS_Enable,
    ROM_API_INDEX_PDS_Auto_Time_Config,
    ROM_API_INDEX_PDS_Auto_Enable,
    ROM_API_INDEX_PDS_Manual_Force_Turn_Off,
    ROM_API_INDEX_PDS_Manual_Force_Turn_On,

    ROM_API_INDEX_HBN_Enable,
    ROM_API_INDEX_HBN_Reset,
    ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg,
    ROM_API_INDEX_HBN_Trim_RC32K,
    ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel,

    ROM_API_INDEX_XIP_SFlash_State_Save,
    ROM_API_INDEX_XIP_SFlash_State_Restore,
    ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,
    ROM_API_INDEX_XIP_SFlash_Read_With_Lock,
    ROM_API_INDEX_XIP_SFlash_Write_With_Lock,
    ROM_API_INDEX_XIP_SFlash_Erase_With_Lock,

    ROM_API_INDEX_SFlash_Init,
    ROM_API_INDEX_SFlash_SetSPIMode,
    ROM_API_INDEX_SFlash_Read_Reg,
    ROM_API_INDEX_SFlash_Write_Reg,
    ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,
    ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,
    ROM_API_INDEX_SFlash_Busy,
    ROM_API_INDEX_SFlash_Write_Enable,
    ROM_API_INDEX_SFlash_Qspi_Enable,
    ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
    ROM_API_INDEX_SFlash_Chip_Erase,
    ROM_API_INDEX_SFlash_Sector_Erase,
    ROM_API_INDEX_SFlash_Blk32_Erase,
    ROM_API_INDEX_SFlash_Blk64_Erase,
    ROM_API_INDEX_SFlash_Erase,
    ROM_API_INDEX_SFlash_Program,
    ROM_API_INDEX_SFlash_GetUniqueId,
    ROM_API_INDEX_SFlash_GetJedecId,
    ROM_API_INDEX_SFlash_GetDeviceId,
    ROM_API_INDEX_SFlash_Powerdown,
    ROM_API_INDEX_SFlash_Releae_Powerdown,
    ROM_API_INDEX_SFlash_Restore_From_Powerdown,
    ROM_API_INDEX_SFlash_SetBurstWrap,
    ROM_API_INDEX_SFlash_DisableBurstWrap,
    ROM_API_INDEX_SFlash_Software_Reset,
    ROM_API_INDEX_SFlash_Reset_Continue_Read,
    ROM_API_INDEX_SFlash_Set_IDbus_Cfg,
    ROM_API_INDEX_SFlash_IDbus_Read_Enable,
    ROM_API_INDEX_SFlash_Cache_Read_Enable,
    ROM_API_INDEX_SFlash_Cache_Read_Disable,
    ROM_API_INDEX_SFlash_Read,

    ROM_API_INDEX_L1C_Cache_Enable_Set,
    ROM_API_INDEX_L1C_Cache_Write_Set,
    ROM_API_INDEX_L1C_Cache_Flush,
    ROM_API_INDEX_L1C_Cache_Hit_Count_Get,
    ROM_API_INDEX_L1C_Cache_Miss_Count_Get,
    ROM_API_INDEX_L1C_Cache_Read_Disable,
    ROM_API_INDEX_L1C_Set_Wrap,
    ROM_API_INDEX_L1C_Set_Way_Disable,
    ROM_API_INDEX_L1C_IROM_2T_Access_Set,

    ROM_API_INDEX_SF_Ctrl_Enable,
    ROM_API_INDEX_SF_Ctrl_Psram_Init,
    ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,
    ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,
    ROM_API_INDEX_SF_Ctrl_Cmds_Set,
    ROM_API_INDEX_SF_Ctrl_Set_Owner,
    ROM_API_INDEX_SF_Ctrl_Disable,
    ROM_API_INDEX_SF_Ctrl_Select_Pad,
    ROM_API_INDEX_SF_Ctrl_Select_Bank,
    ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,
    ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,
    ROM_API_INDEX_SF_Ctrl_AES_Set_Region,
    ROM_API_INDEX_SF_Ctrl_AES_Set_Key,
    ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,
    ROM_API_INDEX_SF_Ctrl_AES_Set_IV,
    ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,
    ROM_API_INDEX_SF_Ctrl_AES_Enable,
    ROM_API_INDEX_SF_Ctrl_AES_Disable,
    ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
    ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,
    ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,
    ROM_API_INDEX_SF_Ctrl_Select_Clock,
    ROM_API_INDEX_SF_Ctrl_SendCmd,
    ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set,
    ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set,
    ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set,
    ROM_API_INDEX_SF_Ctrl_GetBusyState,
    ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
    ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
    ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
    ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
    ROM_API_INDEX_SF_Cfg_Flash_Identify,

    ROM_API_INDEX_Psram_Init,
    ROM_API_INDEX_Psram_ReadReg,
    ROM_API_INDEX_Psram_WriteReg,
    ROM_API_INDEX_Psram_SetDriveStrength,
    ROM_API_INDEX_Psram_SetBurstWrap,
    ROM_API_INDEX_Psram_ReadId,
    ROM_API_INDEX_Psram_EnterQuadMode,
    ROM_API_INDEX_Psram_ExitQuadMode,
    ROM_API_INDEX_Psram_ToggleBurstLength,
    ROM_API_INDEX_Psram_SoftwareReset,
    ROM_API_INDEX_Psram_Set_IDbus_Cfg,
    ROM_API_INDEX_Psram_Cache_Write_Set,
    ROM_API_INDEX_Psram_Write,
    ROM_API_INDEX_Psram_Read,

    ROM_API_INDEX_FUNC_LAST = ROM_API_INDEX_Psram_Read,

    ROM_API_INDEX_FUNC_INVALID_START,

    ROM_API_INDEX_FUNC_LAST_ENTRY = ROMAPI_INDEX_MAX
} ROM_API_INDEX_e;

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  ROMDRIVER
 *  @{
 */

/** @defgroup  ROMDRIVER_Public_Types
 *  @{
 */
#define ROM_APITABLE ((uint32_t *)0x21018800)

#define RomDriver_AON_Power_On_MBG \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])
#define RomDriver_AON_Power_Off_MBG \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])
#define RomDriver_AON_Power_On_XTAL \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
#define RomDriver_AON_Set_Xtal_CapCode \
    ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
#define RomDriver_AON_Power_Off_XTAL \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])

#define RomDriver_ASM_Delay_Us \
    ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
#define RomDriver_BL702_Delay_US \
    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_US])
#define RomDriver_BL702_Delay_MS \
    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_MS])
#define RomDriver_BL702_MemCpy \
    ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy])
#define RomDriver_BL702_MemCpy4 \
    ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy4])
#define RomDriver_BL702_MemCpy_Fast \
    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy_Fast])
#define RomDriver_ARCH_MemCpy_Fast \
    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_ARCH_MemCpy_Fast])
#define RomDriver_BL702_MemSet \
    ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemSet])
#define RomDriver_BL702_MemSet4 \
    ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemSet4])
#define RomDriver_BL702_MemCmp \
    ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCmp])
#define RomDriver_BFLB_Soft_CRC32 \
    ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32])

#define RomDriver_GLB_Get_Root_CLK_Sel \
    ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel])
#define RomDriver_GLB_Set_System_CLK_Div \
    ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div])
#define RomDriver_GLB_Get_BCLK_Div \
    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div])
#define RomDriver_GLB_Get_HCLK_Div \
    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div])
#define RomDriver_Update_SystemCoreClockWith_XTAL \
    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL])
#define RomDriver_GLB_Set_System_CLK \
    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK])
#define RomDriver_System_Core_Clock_Update_From_RC32M \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M])
#define RomDriver_GLB_Set_SF_CLK \
    ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
#define RomDriver_GLB_Power_Off_DLL \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_DLL])
#define RomDriver_GLB_Power_On_DLL \
    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_DLL])
#define RomDriver_GLB_Enable_DLL_All_Clks \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_All_Clks])
#define RomDriver_GLB_Enable_DLL_Clk \
    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_Clk])
#define RomDriver_GLB_Disable_DLL_All_Clks \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_All_Clks])
#define RomDriver_GLB_Disable_DLL_Clk \
    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_Clk])
#define RomDriver_GLB_SW_System_Reset \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
#define RomDriver_GLB_SW_CPU_Reset \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
#define RomDriver_GLB_SW_POR_Reset \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])
#define RomDriver_GLB_Select_Internal_Flash \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash])
#define RomDriver_GLB_Swap_Flash_Pin \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin])
#define RomDriver_GLB_Swap_Flash_CS_IO2_Pin \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin])
#define RomDriver_GLB_Swap_Flash_IO0_IO3_Pin \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin])
#define RomDriver_GLB_Select_Internal_PSram \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_PSram])
#define RomDriver_GLB_GPIO_Init \
    ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])
#define RomDriver_GLB_GPIO_OUTPUT_Enable \
    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable])
#define RomDriver_GLB_GPIO_OUTPUT_Disable \
    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable])
#define RomDriver_GLB_GPIO_Set_HZ \
    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])
#define RomDriver_GLB_Deswap_Flash_Pin \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin])
#define RomDriver_GLB_Select_External_Flash \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash])
#define RomDriver_GLB_GPIO_Get_Fun \
    ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])

#define RomDriver_EF_Ctrl_Busy \
    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])
#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
#define RomDriver_EF_Ctrl_Load_Efuse_R0 \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
#define RomDriver_EF_Ctrl_Clear \
    ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
#define RomDriver_EF_Ctrl_Get_Trim_Parity \
    ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])
#define RomDriver_EF_Ctrl_Read_RC32K_Trim \
    ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
#define RomDriver_EF_Ctrl_Read_RC32M_Trim \
    ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])

#define RomDriver_PDS_Trim_RC32M \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])
#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref])
#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref])
#define RomDriver_PDS_Power_On_PLL \
    ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL])
#define RomDriver_PDS_Enable_PLL_All_Clks \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks])
#define RomDriver_PDS_Disable_PLL_All_Clks \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks])
#define RomDriver_PDS_Enable_PLL_Clk \
    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk])
#define RomDriver_PDS_Disable_PLL_Clk \
    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk])
#define RomDriver_PDS_Power_Off_PLL \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL])
#define RomDriver_PDS_Reset \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset])
#define RomDriver_PDS_Enable \
    ((void (*)(PDS_CFG_Type * cfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
#define RomDriver_PDS_Auto_Time_Config \
    ((void (*)(uint32_t sleepDuration))ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Time_Config])
#define RomDriver_PDS_Auto_Enable \
    ((void (*)(PDS_AUTO_POWER_DOWN_CFG_Type * powerCfg, PDS_AUTO_NORMAL_CFG_Type * normalCfg, BL_Fun_Type enable)) ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Enable])
#define RomDriver_PDS_Manual_Force_Turn_Off \
    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_Off])
#define RomDriver_PDS_Manual_Force_Turn_On \
    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_On])

#define RomDriver_HBN_Enable \
    ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
#define RomDriver_HBN_Reset \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])
#define RomDriver_HBN_GPIO_Dbg_Pull_Cfg \
    ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg])
#define RomDriver_HBN_Trim_RC32K \
    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
#define RomDriver_HBN_Set_ROOT_CLK_Sel \
    ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel])

#define RomDriver_XIP_SFlash_State_Save \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
#define RomDriver_XIP_SFlash_State_Restore \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
#define RomDriver_XIP_SFlash_Erase_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
#define RomDriver_XIP_SFlash_Write_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
    ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
#define RomDriver_XIP_SFlash_Read_With_Lock \
    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock])
#define RomDriver_XIP_SFlash_Write_With_Lock \
    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock])
#define RomDriver_XIP_SFlash_Erase_With_Lock \
    ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock])

#define RomDriver_SFlash_Init \
    ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
#define RomDriver_SFlash_SetSPIMode \
    ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
#define RomDriver_SFlash_Read_Reg \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
#define RomDriver_SFlash_Write_Reg \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
#define RomDriver_SFlash_Read_Reg_With_Cmd \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
#define RomDriver_SFlash_Write_Reg_With_Cmd \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
#define RomDriver_SFlash_Busy \
    ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
#define RomDriver_SFlash_Write_Enable \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
#define RomDriver_SFlash_Qspi_Enable \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
#define RomDriver_SFlash_Chip_Erase \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
#define RomDriver_SFlash_Sector_Erase \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
#define RomDriver_SFlash_Blk32_Erase \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
#define RomDriver_SFlash_Blk64_Erase \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
#define RomDriver_SFlash_Erase \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
#define RomDriver_SFlash_Program \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
#define RomDriver_SFlash_GetUniqueId \
    ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
#define RomDriver_SFlash_GetJedecId \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
#define RomDriver_SFlash_GetDeviceId \
    ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
#define RomDriver_SFlash_Powerdown \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
#define RomDriver_SFlash_Releae_Powerdown \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
#define RomDriver_SFlash_Restore_From_Powerdown \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
#define RomDriver_SFlash_SetBurstWrap \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
#define RomDriver_SFlash_DisableBurstWrap \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
#define RomDriver_SFlash_Software_Reset \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
#define RomDriver_SFlash_Reset_Continue_Read \
    ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
#define RomDriver_SFlash_Set_IDbus_Cfg \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
#define RomDriver_SFlash_IDbus_Read_Enable \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
#define RomDriver_SFlash_Cache_Read_Enable \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
#define RomDriver_SFlash_Cache_Read_Disable \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
#define RomDriver_SFlash_Read \
    ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])

#define RomDriver_L1C_Cache_Enable_Set \
    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set])
#define RomDriver_L1C_Cache_Write_Set \
    ((void (*)(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Write_Set])
#define RomDriver_L1C_Cache_Flush \
    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Flush])
#define RomDriver_L1C_Cache_Hit_Count_Get \
    ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Hit_Count_Get])
#define RomDriver_L1C_Cache_Miss_Count_Get \
    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Miss_Count_Get])
#define RomDriver_L1C_Cache_Read_Disable \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Read_Disable])
#define RomDriver_L1C_Set_Wrap \
    ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
#define RomDriver_L1C_Set_Way_Disable \
    ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable])
#define RomDriver_L1C_IROM_2T_Access_Set \
    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set])

#define RomDriver_SF_Ctrl_Enable \
    ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
#define RomDriver_SF_Ctrl_Psram_Init \
    ((void (*)(SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init])
#define RomDriver_SF_Ctrl_Get_Clock_Delay \
    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
#define RomDriver_SF_Ctrl_Set_Clock_Delay \
    ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
#define RomDriver_SF_Ctrl_Cmds_Set \
    ((void (*)(SF_Ctrl_Cmds_Cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
#define RomDriver_SF_Ctrl_Set_Owner \
    ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
#define RomDriver_SF_Ctrl_Disable \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
#define RomDriver_SF_Ctrl_Select_Pad \
    ((void (*)(SF_Ctrl_Pad_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
#define RomDriver_SF_Ctrl_Select_Bank \
    ((void (*)(SF_Ctrl_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank])
#define RomDriver_SF_Ctrl_AES_Enable_BE \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])
#define RomDriver_SF_Ctrl_AES_Enable_LE \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])
#define RomDriver_SF_Ctrl_AES_Set_Region \
    ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
#define RomDriver_SF_Ctrl_AES_Set_Key \
    ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
    ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
#define RomDriver_SF_Ctrl_AES_Set_IV \
    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
#define RomDriver_SF_Ctrl_AES_Set_IV_BE \
    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
#define RomDriver_SF_Ctrl_AES_Enable \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])
#define RomDriver_SF_Ctrl_AES_Disable \
    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])
#define RomDriver_SF_Ctrl_Is_AES_Enable \
    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
    ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Select_Clock \
    ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
#define RomDriver_SF_Ctrl_SendCmd \
    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \
    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
#define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \
    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set])
#define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \
    ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set])
#define RomDriver_SF_Ctrl_GetBusyState \
    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
    ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
    ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
    ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
#define RomDriver_SF_Cfg_Init_Flash_Gpio \
    ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
#define RomDriver_SF_Cfg_Flash_Identify \
    ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])

#define RomDriver_Psram_Init \
    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_Cmds_Cfg * cmdsCfg, SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init])
#define RomDriver_Psram_ReadReg \
    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg])
#define RomDriver_Psram_WriteReg \
    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg])
#define RomDriver_Psram_SetDriveStrength \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength])
#define RomDriver_Psram_SetBurstWrap \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap])
#define RomDriver_Psram_ReadId \
    ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId])
#define RomDriver_Psram_EnterQuadMode \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode])
#define RomDriver_Psram_ExitQuadMode \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode])
#define RomDriver_Psram_ToggleBurstLength \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength])
#define RomDriver_Psram_SoftwareReset \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset])
#define RomDriver_Psram_Set_IDbus_Cfg \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg])
#define RomDriver_Psram_Cache_Write_Set \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set])
#define RomDriver_Psram_Write \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write])
#define RomDriver_Psram_Read \
    ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read])
/*@} end of group ROMDRIVER_Public_Types */

/** @defgroup  ROMDRIVER_Public_Constants
 *  @{
 */

/*@} end of group ROMDRIVER_Public_Constants */

/** @defgroup  ROMDRIVER_Public_Macros
 *  @{
 */

/*@} end of group ROMDRIVER_Public_Macros */

/** @defgroup  ROMDRIVER_Public_Functions
 *  @{
 */

/*@} end of group ROMDRIVER_Public_Functions */

/*@} end of group ROMDRIVER */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_ROMDRIVER_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_dbg.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sec_dbg.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SEC_DBG_H__
#define __BL702_SEC_DBG_H__

#include "sec_dbg_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SEC_DBG
 *  @{
 */

/** @defgroup  SEC_DBG_Public_Types
 *  @{
 */

/*@} end of group SEC_DBG_Public_Types */

/** @defgroup  SEC_DBG_Public_Constants
 *  @{
 */

/*@} end of group SEC_DBG_Public_Constants */

/** @defgroup  SEC_DBG_Public_Macros
 *  @{
 */

/*@} end of group SEC_DBG_Public_Macros */

/** @defgroup  SEC_DBG_Public_Functions
 *  @{
 */
void Sec_Dbg_Read_Chip_ID(uint8_t id[8]);
void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]);
uint32_t Sec_Dbg_Read_Dbg_Mode(void);
uint32_t Sec_Dbg_Read_Dbg_Enable(void);

/*@} end of group SEC_DBG_Public_Functions */

/*@} end of group SEC_DBG */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SEC_DBG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h
================================================
/**
 ******************************************************************************
 * @file    bl702_sec_eng.h
 * @version V1.0
 * @date
 * @brief   This file is the standard driver header file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#ifndef __BL702_SEC_ENG_H__
#define __BL702_SEC_ENG_H__

#include "bl702_common.h"
#include "sec_eng_reg.h"

#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SEC_ENG
 *  @{
 */

/** @defgroup  SEC_ENG_Public_Types
 *  @{
 */

/**
 *  @brief AES port type definition
 */
typedef enum {
  SEC_ENG_AES_ID0, /*!< AES0 port define */
} SEC_ENG_AES_ID_Type;

/**
 *  @brief SHA port type definition
 */
typedef enum {
  SEC_ENG_SHA_ID0, /*!< SHA0 port define */
} SEC_ENG_SHA_ID_Type;

/**
 *  @brief SHA type definition
 */
typedef enum {
  SEC_ENG_SHA256,    /*!< SHA type:SHA256 */
  SEC_ENG_SHA224,    /*!< SHA type:SHA224 */
  SEC_ENG_SHA1,      /*!< SHA type:SHA1 */
  SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */
} SEC_ENG_SHA_Type;

/**
 *  @brief AES type definition
 */
typedef enum {
  SEC_ENG_AES_ECB, /*!< AES mode type:ECB */
  SEC_ENG_AES_CTR, /*!< AES mode type:CTR */
  SEC_ENG_AES_CBC, /*!< AES mode type:CBC */
} SEC_ENG_AES_Type;

/**
 *  @brief AES KEY type definition
 */
typedef enum {
  SEC_ENG_AES_KEY_128BITS,        /*!< AES KEY type:128 bits */
  SEC_ENG_AES_KEY_256BITS,        /*!< AES KEY type:256 bits */
  SEC_ENG_AES_KEY_192BITS,        /*!< AES KEY type:192 bits */
  SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */
} SEC_ENG_AES_Key_Type;

/**
 *  @brief AES CTR mode counter type definition
 */
typedef enum {
  SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */
  SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */
  SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */
  SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */
} SEC_ENG_AES_Counter_Type;

/**
 *  @brief AES use new or old value type definition
 */
typedef enum {
  SEC_ENG_AES_USE_NEW, /*!< Use new value */
  SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */
} SEC_ENG_AES_ValueUsed_Type;

/**
 *  @brief AES KEY source type definition
 */
typedef enum {
  SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */
  SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */
} SEC_ENG_AES_Key_Src_Type;

/**
 *  @brief AES KEY source type definition
 */
typedef enum {
  SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */
  SEC_ENG_AES_DECRYPTION, /*!< AES decryption */
} SEC_ENG_AES_EnDec_Type;

/**
 *  @brief AES PKA register size type definition
 */
typedef enum {
  SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is  8 Bytes */
  SEC_ENG_PKA_REG_SIZE_16,    /*!< Register size is  16 Bytes */
  SEC_ENG_PKA_REG_SIZE_32,    /*!< Register size is  32 Bytes */
  SEC_ENG_PKA_REG_SIZE_64,    /*!< Register size is  64 Bytes */
  SEC_ENG_PKA_REG_SIZE_96,    /*!< Register size is  96 Bytes */
  SEC_ENG_PKA_REG_SIZE_128,   /*!< Register size is  128 Bytes */
  SEC_ENG_PKA_REG_SIZE_192,   /*!< Register size is  192 Bytes */
  SEC_ENG_PKA_REG_SIZE_256,   /*!< Register size is  256 Bytes */
  SEC_ENG_PKA_REG_SIZE_384,   /*!< Register size is  384 Bytes */
  SEC_ENG_PKA_REG_SIZE_512,   /*!< Register size is  512 Bytes */
} SEC_ENG_PKA_REG_SIZE_Type;

/**
 *  @brief AES PKA register size type definition
 */
typedef enum {
  SEC_ENG_PKA_OP_PPSEL,                /*!< PKA operation type */
  SEC_ENG_PKA_OP_MOD2N         = 0x11, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LDIV2N        = 0x12, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LMUL2N        = 0x13, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LDIV          = 0x14, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LSQR          = 0x15, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LMUL          = 0x16, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LSUB          = 0x17, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LADD          = 0x18, /*!< PKA operation type */
  SEC_ENG_PKA_OP_LCMP          = 0x19, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MDIV2         = 0x21, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MINV          = 0x22, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MEXP          = 0x23, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MSQR          = 0x24, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MMUL          = 0x25, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MREM          = 0x26, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MSUB          = 0x27, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MADD          = 0x28, /*!< PKA operation type */
  SEC_ENG_PKA_OP_RESIZE        = 0x31, /*!< PKA operation type */
  SEC_ENG_PKA_OP_MOVDAT        = 0x32, /*!< PKA operation type */
  SEC_ENG_PKA_OP_NLIR          = 0x33, /*!< PKA operation type */
  SEC_ENG_PKA_OP_SLIR          = 0x34, /*!< PKA operation type */
  SEC_ENG_PKA_OP_CLIR          = 0x35, /*!< PKA operation type */
  SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */
  SEC_ENG_PKA_OP_CTLIRI_PLD    = 0x37, /*!< PKA operation type */
  SEC_ENG_PKA_OP_CFLIR_BUFFER  = 0x38, /*!< PKA operation type */
  SEC_ENG_PKA_OP_CTLIR_PLD     = 0x39, /*!< PKA operation type */
} SEC_ENG_PKA_OP_Type;

/**
 *  @brief Sec Eng Interrupt Type Def
 */
typedef enum {
  SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */
  SEC_ENG_INT_AES,  /*!< Sec Eng Aes Interrupt Type */
  SEC_ENG_INT_SHA,  /*!< Sec Eng Sha Interrupt Type */
  SEC_ENG_INT_PKA,  /*!< Sec Eng Pka Interrupt Type */
  SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */
  SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */
  SEC_ENG_INT_ALL,  /*!< Sec Eng All Interrupt Types */
} SEC_ENG_INT_Type;

/**
 *  @brief SEC_ENG SHA context
 */
typedef struct {
  uint32_t  total[2];   /*!< Number of bytes processed */
  uint32_t *shaBuf;     /*!< Data not processed but in this temp buffer */
  uint32_t *shaPadding; /*!< Padding data */
  uint8_t   shaFeed;    /*!< Sha has feed data */
} SEC_Eng_SHA256_Ctx;

/**
 *  @brief SEC_ENG SHA link mode context
 */
typedef struct {
  uint32_t  total[2];   /*!< Number of bytes processed */
  uint32_t *shaBuf;     /*!< Data not processed but in this temp buffer */
  uint32_t *shaPadding; /*!< Padding data */
  uint32_t  linkAddr;   /*!< Link configure address */
} SEC_Eng_SHA256_Link_Ctx;

/**
 *  @brief SEC_ENG AES context
 */
typedef struct {
  uint8_t          aesFeed; /*!< AES has feed data */
  SEC_ENG_AES_Type mode;    /*!< AES mode */
} SEC_Eng_AES_Ctx;

/**
 *  @brief SEC_ENG SHA link config structure type definition
 */
typedef struct {
  uint32_t : 2;            /*!< [1:0]reserved */
  uint32_t shaMode : 3;    /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */
  uint32_t : 1;            /*!< [5]reserved */
  uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */
  uint32_t : 2;            /*!< [8:7]reserved */
  uint32_t shaIntClr : 1;  /*!< [9]Clear interrupt */
  uint32_t shaIntSet : 1;  /*!< [10]Set interrupt */
  uint32_t : 5;            /*!< [15:11]reserved */
  uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */
  uint32_t shaSrcAddr;     /*!< Message source address */
  uint32_t result[8];      /*!< Result of SHA */
} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type;

/**
 *  @brief SEC_ENG AES link config structure type definition
 */
typedef struct {
  uint32_t : 3;              /*!< [2:0]Reserved */
  uint32_t aesMode : 2;      /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
  uint32_t aesDecEn : 1;     /*!< [5]Encode or decode */
  uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */
  uint32_t aesHwKeyEn : 1;   /*!< [7]Enable or disable using hardware hey */
  uint32_t : 1;              /*!< [8]Reserved */
  uint32_t aesIntClr : 1;    /*!< [9]Clear interrupt */
  uint32_t aesIntSet : 1;    /*!< [10]Set interrupt */
  uint32_t : 1;              /*!< [11]Reserved */
  uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */
  uint32_t aesIVSel : 1;     /*!< [14]Use new iv or use same iv as last one */
  uint32_t : 1;              /*!< [15]Reserved */
  uint32_t aesMsgLen : 16;   /*!< [31:16]Number of 128-bit block */
  uint32_t aesSrcAddr;       /*!< Message source address */
  uint32_t aesDstAddr;       /*!< Message destination address */
  uint32_t aesIV0;           /*!< Big endian initial vector(MSB) */
  uint32_t aesIV1;           /*!< Big endian initial vector */
  uint32_t aesIV2;           /*!< Big endian initial vector */
  uint32_t aesIV3;           /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
  uint32_t aesKey0;          /*!< Big endian aes key(aes-128/256 key MSB) */
  uint32_t aesKey1;          /*!< Big endian aes key */
  uint32_t aesKey2;          /*!< Big endian aes key */
  uint32_t aesKey3;          /*!< Big endian aes key(aes-128 key LSB) */
  uint32_t aesKey4;          /*!< Big endian aes key */
  uint32_t aesKey5;          /*!< Big endian aes key */
  uint32_t aesKey6;          /*!< Big endian aes key */
  uint32_t aesKey7;          /*!< Big endian aes key(aes-256 key LSB) */
} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type;

/**
 *  @brief SEC_ENG GMAC link config structure type definition
 */
typedef struct {
  uint32_t : 9;             /*!< [8:0]reserved */
  uint32_t gmacIntClr : 1;  /*!< [9]Clear interrupt */
  uint32_t gmacIntSet : 1;  /*!< [10]Set interrupt */
  uint32_t : 5;             /*!< [15:11]reserved */
  uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */
  uint32_t gmacSrcAddr;     /*!< Message source address */
  uint32_t gmacKey0;        /*!< GMAC key */
  uint32_t gmacKey1;        /*!< GMAC key */
  uint32_t gmacKey2;        /*!< GMAC key */
  uint32_t gmacKey3;        /*!< GMAC key */
  uint32_t result[4];       /*!< Result of GMAC */
  uint32_t dummy;           /*!< Not use,trigger GMAC will clear this value */
} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type;

/**
 *  @brief SEC_ENG PKA status type definition
 */
typedef struct {
  uint16_t primeFail : 1;   /*!< [0]Prime fail */
  uint16_t errUnknown : 1;  /*!< [1]Err unknown opc */
  uint16_t errOverflow : 1; /*!< [2]Err opq overflow */
  uint16_t errSrc2 : 1;     /*!< [3]Err invalid src2 */
  uint16_t errSrc1 : 1;     /*!< [4]Err invalid src1 */
  uint16_t errSrc0 : 1;     /*!< [5]Err invalid src0 */
  uint16_t errDiv0 : 1;     /*!< [6]Err div by 0 */
  uint16_t errFull : 1;     /*!< [7]Err cam full */
  uint16_t lastOpc : 1;     /*!< [8]Last opc */
  uint16_t opqFull : 1;     /*!< [9]Opq full */
  uint16_t cmdIndex : 5;    /*!< [14:10]Cmd err index */
  uint16_t errCmd : 1;      /*!< [15]Err cmd */
} SEC_Eng_PKA_Status_Type;

/*@} end of group SEC_ENG_Public_Types */

/** @defgroup  SEC_ENG_Public_Constants
 *  @{
 */

/** @defgroup  SEC_ENG_AES_ID_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0))

/** @defgroup  SEC_ENG_SHA_ID_TYPE
 *  @{
 */
#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0))

/** @defgroup  SEC_ENG_SHA_TYPE
 *  @{
 */
#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || ((type) == SEC_ENG_SHA224) || ((type) == SEC_ENG_SHA1) || ((type) == SEC_ENG_SHA1_RSVD))

/** @defgroup  SEC_ENG_AES_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || ((type) == SEC_ENG_AES_CTR) || ((type) == SEC_ENG_AES_CBC))

/** @defgroup  SEC_ENG_AES_KEY_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || ((type) == SEC_ENG_AES_KEY_256BITS) || ((type) == SEC_ENG_AES_KEY_192BITS) || ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS))

/** @defgroup  SEC_ENG_AES_COUNTER_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_COUNTER_TYPE(type) \
  (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || ((type) == SEC_ENG_AES_COUNTER_BYTE_3))

/** @defgroup  SEC_ENG_AES_VALUEUSED_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || ((type) == SEC_ENG_AES_USE_OLD))

/** @defgroup  SEC_ENG_AES_KEY_SRC_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || ((type) == SEC_ENG_AES_KEY_HW))

/** @defgroup  SEC_ENG_AES_ENDEC_TYPE
 *  @{
 */
#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || ((type) == SEC_ENG_AES_DECRYPTION))

/** @defgroup  SEC_ENG_PKA_REG_SIZE_TYPE
 *  @{
 */
#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type)                                                                                                                                                        \
  (((type) == SEC_ENG_PKA_REG_SIZE_8) || ((type) == SEC_ENG_PKA_REG_SIZE_16) || ((type) == SEC_ENG_PKA_REG_SIZE_32) || ((type) == SEC_ENG_PKA_REG_SIZE_64) || ((type) == SEC_ENG_PKA_REG_SIZE_96) \
   || ((type) == SEC_ENG_PKA_REG_SIZE_128) || ((type) == SEC_ENG_PKA_REG_SIZE_192) || ((type) == SEC_ENG_PKA_REG_SIZE_256) || ((type) == SEC_ENG_PKA_REG_SIZE_384)                                \
   || ((type) == SEC_ENG_PKA_REG_SIZE_512))

/** @defgroup  SEC_ENG_PKA_OP_TYPE
 *  @{
 */
#define IS_SEC_ENG_PKA_OP_TYPE(type)                                                                                                                                                             \
  (((type) == SEC_ENG_PKA_OP_PPSEL) || ((type) == SEC_ENG_PKA_OP_MOD2N) || ((type) == SEC_ENG_PKA_OP_LDIV2N) || ((type) == SEC_ENG_PKA_OP_LMUL2N) || ((type) == SEC_ENG_PKA_OP_LDIV)             \
   || ((type) == SEC_ENG_PKA_OP_LSQR) || ((type) == SEC_ENG_PKA_OP_LMUL) || ((type) == SEC_ENG_PKA_OP_LSUB) || ((type) == SEC_ENG_PKA_OP_LADD) || ((type) == SEC_ENG_PKA_OP_LCMP)                \
   || ((type) == SEC_ENG_PKA_OP_MDIV2) || ((type) == SEC_ENG_PKA_OP_MINV) || ((type) == SEC_ENG_PKA_OP_MEXP) || ((type) == SEC_ENG_PKA_OP_MSQR) || ((type) == SEC_ENG_PKA_OP_MMUL)               \
   || ((type) == SEC_ENG_PKA_OP_MREM) || ((type) == SEC_ENG_PKA_OP_MSUB) || ((type) == SEC_ENG_PKA_OP_MADD) || ((type) == SEC_ENG_PKA_OP_RESIZE) || ((type) == SEC_ENG_PKA_OP_MOVDAT)            \
   || ((type) == SEC_ENG_PKA_OP_NLIR) || ((type) == SEC_ENG_PKA_OP_SLIR) || ((type) == SEC_ENG_PKA_OP_CLIR) || ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) \
   || ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || ((type) == SEC_ENG_PKA_OP_CTLIR_PLD))

/** @defgroup  SEC_ENG_INT_TYPE
 *  @{
 */
#define IS_SEC_ENG_INT_TYPE(type)                                                                                                                                                            \
  (((type) == SEC_ENG_INT_TRNG) || ((type) == SEC_ENG_INT_AES) || ((type) == SEC_ENG_INT_SHA) || ((type) == SEC_ENG_INT_PKA) || ((type) == SEC_ENG_INT_CDET) || ((type) == SEC_ENG_INT_GMAC) \
   || ((type) == SEC_ENG_INT_ALL))

/*@} end of group SEC_ENG_Public_Constants */

/** @defgroup  SEC_ENG_Public_Macros
 *  @{
 */
#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24
#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK   0x01000000

/*@} end of group SEC_ENG_Public_Macros */

/** @defgroup  SEC_ENG_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void SEC_GMAC_IRQHandler(void);
void SEC_CDET_IRQHandler(void);
void SEC_TRNG_IRQHandler(void);
void SEC_PKA_IRQHandler(void);
void SEC_AES_IRQHandler(void);
void SEC_SHA_IRQHandler(void);
#endif
void        Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type type, uint32_t shaTmpBuf[16], uint32_t padding[16]);
void        Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo);
BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len);
BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);
void        Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo);
void        Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo);
void        Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]);
BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len);
BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash);
BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType);
void        Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo);
void        Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo);
void        Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo);
void        Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo);
BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out);
void        Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src);
void        Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv);
void        Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv);
void        Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType);
BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out);
BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo);
BL_Err_Type Sec_Eng_Trng_Enable(void);
void        Sec_Eng_Trng_Int_Enable(void);
void        Sec_Eng_Trng_Int_Disable(void);
BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]);
BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len);
void        Sec_Eng_Trng_Int_Read_Trigger(void);
void        Sec_Eng_Trng_Int_Read(uint8_t data[32]);
void        Sec_Eng_Trng_Disable(void);
void        Sec_Eng_PKA_Reset(void);
void        Sec_Eng_PKA_BigEndian_Enable(void);
void        Sec_Eng_PKA_LittleEndian_Enable(void);
void        Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status);
void        Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp);
void        Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize);
void        Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp);
void        Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp);
void        Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx);
void        Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp);
void        Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp);
void        Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp);
void        Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp);
void        Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size, uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx);
void        Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, uint8_t invrRegIdx, uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType,
                                uint8_t pRegIdx);
void        Sec_Eng_GMAC_Enable_LE(void);
void        Sec_Eng_GMAC_Enable_BE(void);
void        Sec_Eng_GMAC_Enable_Link(void);
void        Sec_Eng_GMAC_Disable_Link(void);
BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out);
void        SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask);
void        SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType);
void        SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun);
BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType);
/*----------*/
void SEC_Eng_Turn_On_Sec_Ring(void);
void SEC_Eng_Turn_Off_Sec_Ring(void);
/*----------*/;

/*@} end of group SEC_ENG_Public_Functions */

/*@} end of group SEC_ENG */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SEC_ENG_H__ */
#ifdef __cplusplus
}
#endif

================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sf_cfg.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SF_CFG_H__
#define __BL702_SF_CFG_H__

#include "string.h"
#include "bl702_sflash.h"
#include "bl702_sf_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CFG
 *  @{
 */

/** @defgroup  SF_CFG_Public_Types
 *  @{
 */

/*@} end of group SF_CFG_Public_Types */

/** @defgroup  SF_CFG_Public_Constants
 *  @{
 */

/*@} end of group SF_CFG_Public_Constants */

/** @defgroup  SF_CFG_Public_Macros
 *  @{
 */
/* Flash option 0 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_21
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_19
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_17
#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_18
#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_22
#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_20
/* Flash option 1 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_27
/* FLASH CS */
#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_25
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_28
#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_24
#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_23
#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_26
/* Flash option 2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK2_GPIO 38
/* FLASH CS */
#define BFLB_EXTFLASH_CS2_GPIO 38
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA02_GPIO 38
#define BFLB_EXTFLASH_DATA12_GPIO 38
#define BFLB_EXTFLASH_DATA22_GPIO 38
#define BFLB_EXTFLASH_DATA32_GPIO 38
#define BFLB_FLASH_CFG_SF2_EXT_23_28 0
#define BFLB_FLASH_CFG_SF2_INT_512K  1
#define BFLB_FLASH_CFG_SF2_INT_1M    2
#define BFLB_FLASH_CFG_SF1_EXT_17_22 3
#define BFLB_SF2_SWAP_NONE           0
#define BFLB_SF2_SWAP_CS_IO2         1
#define BFLB_SF2_SWAP_IO0_IO3        2
#define BFLB_SF2_SWAP_BOTH           3
#define BFLB_FLASH_ID_VALID_FLAG     0x80000000
#define BFLB_FLASH_ID_VALID_MASK     0x7FFFFFFF

/*@} end of group SF_CFG_Public_Macros */

/** @defgroup  SF_CFG_Public_Functions
 *  @{
 */
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault);
uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault,
                               SPI_Flash_Cfg_Type *pFlashCfg);
void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);
void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);

/*@} end of group SF_CFG_Public_Functions */

/*@} end of group SF_CFG */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SF_CFG_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_cfg_ext.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sf_cfg_ext.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SF_CFG_EXT_H__
#define __BL702_SF_CFG_EXT_H__

#include "string.h"
#include "bl702_sflash.h"
#include "bl702_sf_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CFG_EXT
 *  @{
 */

/** @defgroup  SF_CFG_EXT_Public_Types
 *  @{
 */

/*@} end of group SF_CFG_EXT_Public_Types */

/** @defgroup  SF_CFG_EXT_Public_Constants
 *  @{
 */

/*@} end of group SF_CFG_EXT_Public_Constants */

/** @defgroup  SF_CFG_EXT_Public_Macros
 *  @{
 */

/*@} end of group SF_CFG_EXT_Public_Macros */

/** @defgroup  SF_CFG_EXT_Public_Functions
 *  @{
 */
void SF_Cfg_Init_Internal_Flash_Gpio(void);
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg,
                                   uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg);

/*@} end of group SF_CFG_EXT_Public_Functions */

/*@} end of group SF_CFG_EXT */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SF_CFG_EXT_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sf_ctrl.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sf_ctrl.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SF_CTRL_H__
#define __BL702_SF_CTRL_H__

#include "sf_ctrl_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CTRL
 *  @{
 */

/** @defgroup  SF_CTRL_Public_Types
 *  @{
 */

/**
 *  @brief Serial flash pad select type definition
 */
typedef enum {
    SF_CTRL_PAD_SEL_SF1,               /*!< SF Ctrl pad select sf1, flash use GPIO 17-22, no psram */
    SF_CTRL_PAD_SEL_SF2,               /*!< SF Ctrl pad select sf2, flash use GPIO 23-28, no psram, embedded flash */
    SF_CTRL_PAD_SEL_SF3,               /*!< SF Ctrl pad select sf3, flash use GPIO 32-37, no psram */
    SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2, /*!< SF Ctrl pad select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */
    SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3, /*!< SF Ctrl pad select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */
    SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1, /*!< SF Ctrl pad select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */
    SF_CTRL_PAD_SEL_DUAL_CS_SF2,       /*!< SF Ctrl pad select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */
    SF_CTRL_PAD_SEL_DUAL_CS_SF3,       /*!< SF Ctrl pad select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */
} SF_Ctrl_Pad_Select;

/**
 *  @brief Serial flash system bus control type definition
 */
typedef enum {
    SF_CTRL_SEL_FLASH, /*!< SF Ctrl system bus control flash */
    SF_CTRL_SEL_PSRAM, /*!< SF Ctrl system bus control psram */
} SF_Ctrl_Select;

/**
 *  @brief Serail flash controller wrap mode len type definition
 */
typedef enum {
    SF_CTRL_WRAP_LEN_8,    /*!< SF Ctrl wrap length: 8 */
    SF_CTRL_WRAP_LEN_16,   /*!< SF Ctrl wrap length: 16 */
    SF_CTRL_WRAP_LEN_32,   /*!< SF Ctrl wrap length: 32 */
    SF_CTRL_WRAP_LEN_64,   /*!< SF Ctrl wrap length: 64 */
    SF_CTRL_WRAP_LEN_128,  /*!< SF Ctrl wrap length: 128 */
    SF_CTRL_WRAP_LEN_256,  /*!< SF Ctrl wrap length: 256 */
    SF_CTRL_WRAP_LEN_512,  /*!< SF Ctrl wrap length: 512 */
    SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */
    SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */
    SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */
} SF_Ctrl_Wrap_Len_Type;

/**
 *  @brief Serial flash controller owner type definition
 */
typedef enum {
    SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */
    SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */
} SF_Ctrl_Owner_Type;

/**
 *  @brief Serial flash controller select clock type definition
 */
typedef enum {
    SF_CTRL_SAHB_CLOCK,  /*!< Serial flash controller select default sahb clock */
    SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */
} SF_Ctrl_Sahb_Type;

/**
 *  @brief Serial flash controller owner type definition
 */
typedef enum {
    HIGH_SPEED_MODE_CLOCK,  /*!< Serial flash controller high speed mode clk_ahb>clk_sf */
    REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */
} SF_Ctrl_Ahb2sif_Type;

/**
 *  @brief Read and write type definition
 */
typedef enum {
    SF_CTRL_READ,  /*!< Serail flash read command flag */
    SF_CTRL_WRITE, /*!< Serail flash write command flag */
} SF_Ctrl_RW_Type;

/**
 *  @brief Serail flash interface IO type definition
 */
typedef enum {
    SF_CTRL_NIO_MODE, /*!< Normal IO mode define */
    SF_CTRL_DO_MODE,  /*!< Dual Output mode define */
    SF_CTRL_QO_MODE,  /*!< Quad Output mode define */
    SF_CTRL_DIO_MODE, /*!< Dual IO mode define */
    SF_CTRL_QIO_MODE, /*!< Quad IO mode define */
} SF_Ctrl_IO_Type;

/**
 *  @brief Serail flash controller interface mode type definition
 */
typedef enum {
    SF_CTRL_SPI_MODE, /*!< SPI mode define */
    SF_CTRL_QPI_MODE, /*!< QPI mode define */
} SF_Ctrl_Mode_Type;

/**
 *  @brief Serail flash controller command mode type definition
 */
typedef enum {
    SF_CTRL_CMD_1_LINE,  /*!< Command in one line mode */
    SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */
} SF_Ctrl_Cmd_Mode_Type;

/**
 *  @brief Serail flash controller address mode type definition
 */
typedef enum {
    SF_CTRL_ADDR_1_LINE,  /*!< Address in one line mode */
    SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */
    SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */
} SF_Ctrl_Addr_Mode_Type;

/**
 *  @brief Serail flash controller dummy mode type definition
 */
typedef enum {
    SF_CTRL_DUMMY_1_LINE,  /*!< Dummy in one line mode */
    SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */
    SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */
} SF_Ctrl_Dmy_Mode_Type;

/**
 *  @brief Serail flash controller data mode type definition
 */
typedef enum {
    SF_CTRL_DATA_1_LINE,  /*!< Data in one line mode */
    SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */
    SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */
} SF_Ctrl_Data_Mode_Type;

/**
 *  @brief Serail flash controller AES type definition
 */
typedef enum {
    SF_CTRL_AES_128BITS,            /*!< Serail flash AES key 128 bits length */
    SF_CTRL_AES_256BITS,            /*!< Serail flash AES key 256 bits length */
    SF_CTRL_AES_192BITS,            /*!< Serail flash AES key 192 bits length */
    SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */
} SF_Ctrl_AES_Key_Type;

/**
 *  @brief Serail flash controller configuration structure type definition
 */
typedef struct
{
    SF_Ctrl_Owner_Type owner;         /*!< Sflash interface bus owner */
    SF_Ctrl_Sahb_Type sahbClock;      /*!< Sflash clock sahb sram select */
    SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */
    uint8_t clkDelay;                 /*!< Clock count for read due to pad delay */
    uint8_t clkInvert;                /*!< Clock invert */
    uint8_t rxClkInvert;              /*!< RX clock invert */
    uint8_t doDelay;                  /*!< Data out delay */
    uint8_t diDelay;                  /*!< Data in delay */
    uint8_t oeDelay;                  /*!< Output enable delay */
} SF_Ctrl_Cfg_Type;

/**
 *  @brief SF Ctrl psram controller configuration structure type definition
 */
typedef struct
{
    SF_Ctrl_Owner_Type owner;        /*!< Psram interface bus owner */
    SF_Ctrl_Pad_Select padSel;       /*!< SF Ctrl pad select */
    SF_Ctrl_Select bankSel;          /*!< SF Ctrl bank select */
    BL_Fun_Type psramRxClkInvertSrc; /*!< Select psram rx clock invert source */
    BL_Fun_Type psramRxClkInvertSel; /*!< Select inveted psram rx clock */
    BL_Fun_Type psramDelaySrc;       /*!< Select psram read delay source */
    uint8_t psramClkDelay;           /*!< Psram read delay cycle = n + 1 */
} SF_Ctrl_Psram_Cfg;

/**
 *  @brief SF Ctrl cmds configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type cmdsEn;            /*!< SF Ctrl cmds enable */
    BL_Fun_Type burstToggleEn;     /*!< SF Ctrl burst toggle mode enable */
    BL_Fun_Type wrapModeEn;        /*!< SF Ctrl wrap mode cmd enable */
    SF_Ctrl_Wrap_Len_Type wrapLen; /*!< SF Ctrl wrap length */
} SF_Ctrl_Cmds_Cfg;

/**
 *  @brief Serail flash command configuration structure type definition
 */
typedef struct
{
    uint8_t rwFlag;                  /*!< Read write flag */
    SF_Ctrl_Cmd_Mode_Type cmdMode;   /*!< Command mode */
    SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */
    uint8_t addrSize;                /*!< Address size */
    uint8_t dummyClks;               /*!< Dummy clocks */
    SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */
    SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */
    uint8_t rsv[1];                  /*!<  */
    uint32_t nbData;                 /*!< Transfer number of bytes */
    uint32_t cmdBuf[2];              /*!< Command buffer */
} SF_Ctrl_Cmd_Cfg_Type;

/*@} end of group SF_CTRL_Public_Types */

/** @defgroup  SF_CTRL_Public_Constants
 *  @{
 */

/** @defgroup  SF_CTRL_PAD_SELECT
 *  @{
 */
#define IS_SF_CTRL_PAD_SELECT(type) (((type) == SF_CTRL_PAD_SEL_SF1) ||               \
                                     ((type) == SF_CTRL_PAD_SEL_SF2) ||               \
                                     ((type) == SF_CTRL_PAD_SEL_SF3) ||               \
                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2) || \
                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3) || \
                                     ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) || \
                                     ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF2) ||       \
                                     ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF3))

/** @defgroup  SF_CTRL_SELECT
 *  @{
 */
#define IS_SF_CTRL_SELECT(type) (((type) == SF_CTRL_SEL_FLASH) || \
                                 ((type) == SF_CTRL_SEL_PSRAM))

/** @defgroup  SF_CTRL_WRAP_LEN_TYPE
 *  @{
 */
#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) ||    \
                                        ((type) == SF_CTRL_WRAP_LEN_16) ||   \
                                        ((type) == SF_CTRL_WRAP_LEN_32) ||   \
                                        ((type) == SF_CTRL_WRAP_LEN_64) ||   \
                                        ((type) == SF_CTRL_WRAP_LEN_128) ||  \
                                        ((type) == SF_CTRL_WRAP_LEN_256) ||  \
                                        ((type) == SF_CTRL_WRAP_LEN_512) ||  \
                                        ((type) == SF_CTRL_WRAP_LEN_1024) || \
                                        ((type) == SF_CTRL_WRAP_LEN_2048) || \
                                        ((type) == SF_CTRL_WRAP_LEN_4096))

/** @defgroup  SF_CTRL_OWNER_TYPE
 *  @{
 */
#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \
                                     ((type) == SF_CTRL_OWNER_IAHB))

/** @defgroup  SF_CTRL_SAHB_TYPE
 *  @{
 */
#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \
                                    ((type) == SF_CTRL_FLASH_CLOCK))

/** @defgroup  SF_CTRL_AHB2SIF_TYPE
 *  @{
 */
#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \
                                       ((type) == REMOVE_CLOCK_CONSTRAIN))

/** @defgroup  SF_CTRL_RW_TYPE
 *  @{
 */
#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \
                                  ((type) == SF_CTRL_WRITE))

/** @defgroup  SF_CTRL_IO_TYPE
 *  @{
 */
#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \
                                  ((type) == SF_CTRL_DO_MODE) ||  \
                                  ((type) == SF_CTRL_QO_MODE) ||  \
                                  ((type) == SF_CTRL_DIO_MODE) || \
                                  ((type) == SF_CTRL_QIO_MODE))

/** @defgroup  SF_CTRL_MODE_TYPE
 *  @{
 */
#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \
                                    ((type) == SF_CTRL_QPI_MODE))

/** @defgroup  SF_CTRL_CMD_MODE_TYPE
 *  @{
 */
#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \
                                        ((type) == SF_CTRL_CMD_4_LINES))

/** @defgroup  SF_CTRL_ADDR_MODE_TYPE
 *  @{
 */
#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) ||  \
                                         ((type) == SF_CTRL_ADDR_2_LINES) || \
                                         ((type) == SF_CTRL_ADDR_4_LINES))

/** @defgroup  SF_CTRL_DMY_MODE_TYPE
 *  @{
 */
#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) ||  \
                                        ((type) == SF_CTRL_DUMMY_2_LINES) || \
                                        ((type) == SF_CTRL_DUMMY_4_LINES))

/** @defgroup  SF_CTRL_DATA_MODE_TYPE
 *  @{
 */
#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) ||  \
                                         ((type) == SF_CTRL_DATA_2_LINES) || \
                                         ((type) == SF_CTRL_DATA_4_LINES))

/** @defgroup  SF_CTRL_AES_KEY_TYPE
 *  @{
 */
#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \
                                       ((type) == SF_CTRL_AES_256BITS) || \
                                       ((type) == SF_CTRL_AES_192BITS) || \
                                       ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))

/*@} end of group SF_CTRL_Public_Constants */

/** @defgroup  SF_CTRL_Public_Macros
 *  @{
 */
#define SF_CTRL_NO_ADDRESS  0xFFFFFFFF
#define FLASH_CTRL_BUF_SIZE 256

/*@} end of group SF_CTRL_Public_Macros */

/** @defgroup  SF_CTRL_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void);
#endif
void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);
void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *psramCfg);
uint8_t SF_Ctrl_Get_Clock_Delay(void);
void SF_Ctrl_Set_Clock_Delay(uint8_t delay);
void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg);
void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel);
void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel);
void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);
void SF_Ctrl_Disable(void);
void SF_Ctrl_AES_Enable_BE(void);
void SF_Ctrl_AES_Enable_LE(void);
void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr,
                            uint32_t endAddr,
                            uint8_t locked);
void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Enable(void);
void SF_Ctrl_AES_Disable(void);
uint8_t SF_Ctrl_Is_AES_Enable(void);
void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset);
uint32_t SF_Ctrl_Get_Flash_Image_Offset(void);
void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType);
void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);
void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
BL_Sts_Type SF_Ctrl_GetBusyState(void);

/*@} end of group SF_CTRL_Public_Functions */

/*@} end of group SF_CTRL */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SF_CTRL_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sflah.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SFLAH_H__
#define __BL702_SFLAH_H__

#include "bl702_common.h"
#include "bl702_sf_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SFLAH
 *  @{
 */

/** @defgroup  SFLAH_Public_Types
 *  @{
 */

/**
 *  @brief Serial flash configuration structure type definition
 */
typedef struct
{
    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
    uint8_t resetEnCmd;           /*!< Flash enable reset command */
    uint8_t resetCmd;             /*!< Flash reset command */
    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
    uint8_t qpiJedecIdCmd;        /*!< QPI JEDEC ID comamnd */
    uint8_t qpiJedecIdCmdDmyClk;  /*!< QPI JEDEC ID command dummy clock */
    uint8_t sectorSize;           /*!< *1024bytes */
    uint8_t mid;                  /*!< Manufacturer ID */
    uint16_t pageSize;            /*!< Page size */
    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
    uint8_t sectorEraseCmd;       /*!< Sector erase command */
    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
    uint8_t pageProgramCmd;       /*!< Page program cmd */
    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
    uint8_t qppAddrMode;          /*!< QIO page program address mode */
    uint8_t fastReadCmd;          /*!< Fast read command */
    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
    uint8_t wrEnableIndex;        /*!< Write enable register index */
    uint8_t qeIndex;              /*!< Quad mode enable register index */
    uint8_t busyIndex;            /*!< Busy status register index */
    uint8_t wrEnableBit;          /*!< Write enable bit pos */
    uint8_t qeBit;                /*!< Quad enable bit pos */
    uint8_t busyBit;              /*!< Busy status bit pos */
    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
    uint8_t releasePowerDown;     /*!< Release power down command */
    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
    uint8_t readRegCmd[4];        /*!< Read register command buffer */
    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
    uint8_t enterQpi;             /*!< Enter qpi command */
    uint8_t exitQpi;              /*!< Exit qpi command */
    uint8_t cReadMode;            /*!< Config data for continuous read mode */
    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
    uint16_t timeEsector;         /*!< 4K erase time */
    uint16_t timeE32k;            /*!< 32K erase time */
    uint16_t timeE64k;            /*!< 64K erase time */
    uint16_t timePagePgm;         /*!< Page program time */
    uint16_t timeCe;              /*!< Chip erase time in ms */
    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
    uint8_t qeData;               /*!< QE set data */
} __attribute__((packed)) SPI_Flash_Cfg_Type;

/*@} end of group SFLAH_Public_Types */

/** @defgroup  SFLAH_Public_Constants
 *  @{
 */

/*@} end of group SFLAH_Public_Constants */

/** @defgroup  SFLAH_Public_Macros
 *  @{
 */
#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
#define BFLB_SPIFLASH_CMD_INVALID 0xff

/*@} end of group SFLAH_Public_Macros */

/** @defgroup  SFLAH_Public_Functions
 *  @{
 */
void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg);
BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
                                     uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
                                      uint8_t regLen);
BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);
BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);
BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);
void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);
void SFlash_GetDeviceId(uint8_t *data);
void SFlash_Powerdown(void);
void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead);
void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,
                                 uint32_t len);
BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead);
BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,
                                     uint8_t wayDisable);
void SFlash_Cache_Read_Disable(void);
BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead);
BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,
                        uint32_t len);

/*@} end of group SFLAH_Public_Functions */

/*@} end of group SFLAH */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SFLAH_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h
================================================
/**
  ******************************************************************************
  * @file    bl702_sflah_ext.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SFLAH_EXT_H__
#define __BL702_SFLAH_EXT_H__

#include "bl702_sflash.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SFLAH_EXT
 *  @{
 */

/** @defgroup  SFLAH_EXT_Public_Types
 *  @{
 */

/**
 *  @brief Serail flash protect KH25V40 type definition
 */
typedef enum {
    SFLASH_KH25V40_PROTECT_NONE,          /*!< SFlash no protect KH25V40 */
    SFLASH_KH25V40_PROTECT_448KTO512K,    /*!< SFlash protect KH25V40 448K to 512K */
    SFLASH_KH25V40_PROTECT_384KTO512K,    /*!< SFlash protect KH25V40 384K to 512K */
    SFLASH_KH25V40_PROTECT_256KTO512K,    /*!< SFlash protect KH25V40 256K to 512K */
    SFLASH_KH25V40_PROTECT_ALL,           /*!< SFlash protect KH25V40 0K to 512K */
} SFlash_Protect_Kh25v40_Type;

/*@} end of group SFLAH_EXT_Public_Types */

/** @defgroup  SFLAH_EXT_Public_Constants
 *  @{
 */

/** @defgroup  SFLASH_PROTECT_KH25V40_TYPE
 *  @{
 */
#define IS_SFLASH_PROTECT_KH25V40_TYPE(type) (((type) == SFLASH_KH25V40_PROTECT_NONE) || \
                                              ((type) == SFLASH_KH25V40_PROTECT_448KTO512K) ||  \
                                              ((type) == SFLASH_KH25V40_PROTECT_384KTO512K) ||  \
                                              ((type) == SFLASH_KH25V40_PROTECT_256KTO512K) || \
                                              ((type) == SFLASH_KH25V40_PROTECT_ALL))

/*@} end of group SFLAH_EXT_Public_Constants */

/** @defgroup  SFLAH_EXT_Public_Macros
 *  @{
 */

/*@} end of group SFLAH_EXT_Public_Macros */

/** @defgroup  SFLAH_EXT_Public_Functions
 *  @{
 */
BL_Err_Type SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
                                     uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
                                      uint8_t regLen);
BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg);

/*@} end of group SFLAH_EXT_Public_Functions */

/*@} end of group SFLAH_EXT */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SFLAH_EXT_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_spi.h
================================================
/**
  ******************************************************************************
  * @file    bl702_spi.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_SPI_H__
#define __BL702_SPI_H__

#include "spi_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SPI
 *  @{
 */

/** @defgroup  SPI_Public_Types
 *  @{
 */

/**
 *  @brief SPI No. type definition
 */
typedef enum {
    SPI_ID_0,   /*!< SPI0 port define */
    SPI_ID_MAX, /*!< SPI MAX ID define */
} SPI_ID_Type;

/**
 *  @brief SPI byte inverse type definition
 */
typedef enum {
    SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */
    SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */
} SPI_BYTE_INVERSE_Type;

/**
 *  @brief SPI bit inverse type definition
 */
typedef enum {
    SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */
    SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */
} SPI_BIT_INVERSE_Type;

/**
 *  @brief SPI clock phase inverse type definition
 */
typedef enum {
    SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */
    SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */
} SPI_CLK_PHASE_INVERSE_Type;

/**
 *  @brief SPI clock polarity type definition
 */
typedef enum {
    SPI_CLK_POLARITY_LOW,  /*!< SPI clock output low at IDLE state */
    SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */
} SPI_CLK_POLARITY_Type;

/**
 *  @brief SPI frame size(also the valid width for each fifo entry) type definition
 */
typedef enum {
    SPI_FRAME_SIZE_8,  /*!< SPI frame size 8 bit */
    SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */
    SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */
    SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */
} SPI_FrameSize_Type;

/**
 *  @brief SPI work mode select type definition
 */
typedef enum {
    SPI_WORK_MODE_SLAVE,  /*!< SPI work at slave mode */
    SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */
} SPI_WORK_MODE_Type;

/**
 *  @brief SPI enable or disable timeout judgment definition
 */
typedef enum {
    SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */
    SPI_TIMEOUT_ENABLE,  /*!< SPI enable timeout judgment */
} SPI_Timeout_Type;

/**
 *  @brief SPI fifo overflow/underflow flag type definition
 */
typedef enum {
    SPI_FIFO_TX_OVERFLOW,  /*!< SPI tx fifo overflow flag */
    SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */
    SPI_FIFO_RX_OVERFLOW,  /*!< SPI rx fifo overflow flag */
    SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */
} SPI_FifoStatus_Type;

/**
 *  @brief SPI interrupt type definition
 */
typedef enum {
    SPI_INT_END,            /*!< SPI transfer end interrupt,shared by both master and slave mode */
    SPI_INT_TX_FIFO_REQ,    /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */
    SPI_INT_RX_FIFO_REQ,    /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */
    SPI_INT_SLAVE_TIMEOUT,  /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */
    SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */
    SPI_INT_FIFO_ERROR,     /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */
    SPI_INT_ALL,            /*!< All the interrupt */
} SPI_INT_Type;

/**
 *  @brief SPI configuration type definition
 */
typedef struct
{
    BL_Fun_Type deglitchEnable;             /*!< Enable or disable de-glitch function */
    BL_Fun_Type continuousEnable;           /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */
    SPI_BYTE_INVERSE_Type byteSequence;     /*!< The byte is sent first in SPI transfer */
    SPI_BIT_INVERSE_Type bitSequence;       /*!< The bit is sent first in SPI transfer */
    SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */
    SPI_CLK_POLARITY_Type clkPolarity;      /*!< SPI clock plarity */
    SPI_FrameSize_Type frameSize;           /*!< SPI frame size(also the valid width for each fifo entry) */
} SPI_CFG_Type;

/**
 *  @brief SPI configuration type definition
 */
typedef struct
{
    uint8_t startLen;      /*!< Length of start condition */
    uint8_t stopLen;       /*!< Length of stop condition */
    uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */
    uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */
    uint8_t intervalLen;   /*!< Length of interval between frame */
} SPI_ClockCfg_Type;

/**
 *  @brief SPI DMA configuration type definition
 */
typedef struct
{
    uint8_t txFifoThreshold;     /*!< SPI tx FIFO threshold */
    uint8_t rxFifoThreshold;     /*!< SPI rx FIFO threshold */
    BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
    BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
} SPI_FifoCfg_Type;

/*@} end of group SPI_Public_Types */

/** @defgroup  SPI_Public_Constants
 *  @{
 */

/** @defgroup  SPI_ID_TYPE
 *  @{
 */
#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \
                              ((type) == SPI_ID_MAX))

/** @defgroup  SPI_BYTE_INVERSE_TYPE
 *  @{
 */
#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \
                                        ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST))

/** @defgroup  SPI_BIT_INVERSE_TYPE
 *  @{
 */
#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \
                                       ((type) == SPI_BIT_INVERSE_LSB_FIRST))

/** @defgroup  SPI_CLK_PHASE_INVERSE_TYPE
 *  @{
 */
#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \
                                             ((type) == SPI_CLK_PHASE_INVERSE_1))

/** @defgroup  SPI_CLK_POLARITY_TYPE
 *  @{
 */
#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \
                                        ((type) == SPI_CLK_POLARITY_HIGH))

/** @defgroup  SPI_FRAMESIZE_TYPE
 *  @{
 */
#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) ||  \
                                     ((type) == SPI_FRAME_SIZE_16) || \
                                     ((type) == SPI_FRAME_SIZE_24) || \
                                     ((type) == SPI_FRAME_SIZE_32))

/** @defgroup  SPI_WORK_MODE_TYPE
 *  @{
 */
#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \
                                     ((type) == SPI_WORK_MODE_MASTER))

/** @defgroup  SPI_TIMEOUT_TYPE
 *  @{
 */
#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \
                                   ((type) == SPI_TIMEOUT_ENABLE))

/** @defgroup  SPI_FIFOSTATUS_TYPE
 *  @{
 */
#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) ||  \
                                      ((type) == SPI_FIFO_TX_UNDERFLOW) || \
                                      ((type) == SPI_FIFO_RX_OVERFLOW) ||  \
                                      ((type) == SPI_FIFO_RX_UNDERFLOW))

/** @defgroup  SPI_INT_TYPE
 *  @{
 */
#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) ||            \
                               ((type) == SPI_INT_TX_FIFO_REQ) ||    \
                               ((type) == SPI_INT_RX_FIFO_REQ) ||    \
                               ((type) == SPI_INT_SLAVE_TIMEOUT) ||  \
                               ((type) == SPI_INT_SLAVE_UNDERRUN) || \
                               ((type) == SPI_INT_FIFO_ERROR) ||     \
                               ((type) == SPI_INT_ALL))

/*@} end of group SPI_Public_Constants */

/** @defgroup  SPI_Public_Macros
 *  @{
 */
#define SPI_RX_FIFO_SIZE 4
#define SPI_TX_FIFO_SIZE 4

/*@} end of group SPI_Public_Macros */

/** @defgroup  SPI_Public_Functions
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
void SPI_IRQHandler(void);
#endif
BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg);
BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo);
BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk);
BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg);
BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg);
BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);
BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType);
BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value);
BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt);
BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint);
BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);
BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask);
BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun);
BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data);
BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length,
                               SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length,
                                SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length,
                                SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length,
                                SPI_Timeout_Type timeoutType);
uint32_t SPI_ReceiveData(SPI_ID_Type spiNo);
uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo);
uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo);
BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType);
BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts);
BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo);

/*@} end of group SPI_Public_Functions */

/*@} end of group SPI */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_SPI_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_timer.h
================================================
/**
  ******************************************************************************
  * @file    bl702_timer.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_TIMER_H__
#define __BL702_TIMER_H__

#include "timer_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  TIMER
 *  @{
 */

/** @defgroup  TIMER_Public_Types
 *  @{
 */

/**
 *  @brief TIMER channel type definition
 */
typedef enum {
    TIMER_CH0,    /*!< TIMER channel 0 port define */
    TIMER_CH1,    /*!< TIMER channel 1 port define */
    TIMER_CH_MAX, /*!<  */
} TIMER_Chan_Type;

/**
 *  @brief TIMER clock source type definition
 */
typedef enum {
    TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */
    TIMER_CLKSRC_32K,  /*!< TIMER clock source :32K CLK */
    TIMER_CLKSRC_1K,   /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */
    TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */
} TIMER_ClkSrc_Type;

/**
 *  @brief TIMER match compare ID type definition
 */
typedef enum {
    TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */
    TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */
    TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */
} TIMER_Comp_ID_Type;

/**
 *  @brief TIMER preload source type definition
 */
typedef enum {
    TIMER_PRELOAD_TRIG_NONE,  /*!< TIMER no preload source, just free run */
    TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */
    TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */
    TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */
} TIMER_PreLoad_Trig_Type;

/**
 *  @brief TIMER count register run mode type definition
 */
typedef enum {
    TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */
    TIMER_COUNT_FREERUN, /*!< TIMER count register free run */
} TIMER_CountMode_Type;

/**
 *  @brief TIMER interrupt type definition
 */
typedef enum {
    TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */
    TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */
    TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */
    TIMER_INT_ALL,    /*!<  */
} TIMER_INT_Type;

/**
 *  @brief Watchdog timer interrupt type definition
 */
typedef enum {
    WDT_INT,     /*!< Comparator 0 match cause interrupt */
    WDT_INT_ALL, /*!<  */
} WDT_INT_Type;

/**
 *  @brief TIMER configuration structure type definition
 */
typedef struct
{
    TIMER_Chan_Type timerCh;           /*!< Timer channel */
    TIMER_ClkSrc_Type clkSrc;          /*!< Timer clock source */
    TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */
    TIMER_CountMode_Type countMode;    /*!< Timer count mode */
    uint8_t clockDivision;             /*!< Timer clock divison value */
    uint32_t matchVal0;                /*!< Timer match 0 value 0 */
    uint32_t matchVal1;                /*!< Timer match 1 value 0 */
    uint32_t matchVal2;                /*!< Timer match 2 value 0 */
    uint32_t preLoadVal;               /*!< Timer preload value */
} TIMER_CFG_Type;

/*@} end of group TIMER_Public_Types */

/** @defgroup  TIMER_Public_Constants
 *  @{
 */

/** @defgroup  TIMER_CHAN_TYPE
 *  @{
 */
#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \
                                  ((type) == TIMER_CH1) || \
                                  ((type) == TIMER_CH_MAX))

/** @defgroup  TIMER_CLKSRC_TYPE
 *  @{
 */
#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \
                                    ((type) == TIMER_CLKSRC_32K) ||  \
                                    ((type) == TIMER_CLKSRC_1K) ||   \
                                    ((type) == TIMER_CLKSRC_XTAL))

/** @defgroup  TIMER_COMP_ID_TYPE
 *  @{
 */
#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \
                                     ((type) == TIMER_COMP_ID_1) || \
                                     ((type) == TIMER_COMP_ID_2))

/** @defgroup  TIMER_PRELOAD_TRIG_TYPE
 *  @{
 */
#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) ||  \
                                          ((type) == TIMER_PRELOAD_TRIG_COMP0) || \
                                          ((type) == TIMER_PRELOAD_TRIG_COMP1) || \
                                          ((type) == TIMER_PRELOAD_TRIG_COMP2))

/** @defgroup  TIMER_COUNTMODE_TYPE
 *  @{
 */
#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \
                                       ((type) == TIMER_COUNT_FREERUN))

/** @defgroup  TIMER_INT_TYPE
 *  @{
 */
#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \
                                 ((type) == TIMER_INT_COMP_1) || \
                                 ((type) == TIMER_INT_COMP_2) || \
                                 ((type) == TIMER_INT_ALL))

/** @defgroup  WDT_INT_TYPE
 *  @{
 */
#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \
                               ((type) == WDT_INT_ALL))

/*@} end of group TIMER_Public_Constants */

/** @defgroup  TIMER_Public_Macros
 *  @{
 */
#define WDT_ENABLE_ACCESS()                                                                                            \
    {                                                                                                                  \
        BL_WR_REG(TIMER_BASE, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \
        BL_WR_REG(TIMER_BASE, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \
    }

/*@} end of group TIMER_Public_Macros */

/** @defgroup  TIMER_Public_Functions
 *  @{
 */

/**
 *  @brief UART Functions
 */
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_CH0_IRQHandler(void);
void TIMER_CH1_IRQHandler(void);
void TIMER_WDT_IRQHandler(void);
#endif
BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg);
uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val);
uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh);
BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh);
void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val);
void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc);
void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode);
void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
void TIMER_Enable(TIMER_Chan_Type timerCh);
void TIMER_Disable(TIMER_Chan_Type timerCh);
void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask);
void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div);
uint16_t WDT_GetMatchValue(void);
void WDT_SetCompValue(uint16_t val);
uint16_t WDT_GetCounterValue(void);
void WDT_ResetCounterValue(void);
BL_Sts_Type WDT_GetResetStatus(void);
void WDT_ClearResetStatus(void);
void WDT_Enable(void);
void WDT_Disable(void);
void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask);
void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun);
void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun);

/*@} end of group TIMER_Public_Functions */

/*@} end of group TIMER */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_TIMER_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_uart.h
================================================
/**
  ******************************************************************************
  * @file    bl702_uart.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_UART_H__
#define __BL702_UART_H__

#include "uart_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  UART
 *  @{
 */

/** @defgroup  UART_Public_Types
 *  @{
 */

/**
 *  @brief UART port type definition
 */
typedef enum {
    UART0_ID,    /*!< UART0 port define */
    UART1_ID,    /*!< UART1 port define */
    UART_ID_MAX, /*!< UART MAX ID define */
} UART_ID_Type;

/**
 *  @brief UART direction type definition
 */
typedef enum {
    UART_TX,   /*!< UART TX Direction */
    UART_RX,   /*!< UART RX Direction */
    UART_TXRX, /*!< UART TX and RX Direction */
} UART_Direction_Type;

/**
 *  @brief UART parity type definition
 */
typedef enum {
    UART_PARITY_NONE, /*!< UART parity none define */
    UART_PARITY_ODD,  /*!< UART parity odd define */
    UART_PARITY_EVEN, /*!< UART parity even define */
} UART_Parity_Type;

/**
 *  @brief UART data bits type definiton
 */
typedef enum {
    UART_DATABITS_5, /*!< UART data bits length:5 bits */
    UART_DATABITS_6, /*!< UART data bits length:6 bits */
    UART_DATABITS_7, /*!< UART data bits length:7 bits */
    UART_DATABITS_8, /*!< UART data bits length:8 bits */
} UART_DataBits_Type;

/**
 *  @brief UART stop bits type definiton
 */
typedef enum {
    UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */
    UART_STOPBITS_1,   /*!< UART data stop bits length:1 bits */
    UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */
    UART_STOPBITS_2,   /*!< UART data stop bits length:2 bits */
} UART_StopBits_Type;

/**
 *  @brief UART each data byte is send out LSB-first or MSB-first type definiton
 */
typedef enum {
    UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */
    UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */
} UART_ByteBitInverse_Type;

/**
 *  @brief UART auto baudrate detection using codeword 0x55 or start bit definiton
 */
typedef enum {
    UART_AUTOBAUD_0X55,     /*!< UART auto baudrate detection using codeword 0x55 */
    UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */
} UART_AutoBaudDetection_Type;

/**
 *  @brief UART interrupt type definition
 */
typedef enum {
    UART_INT_TX_END,      /*!< UART tx transfer end interrupt */
    UART_INT_RX_END,      /*!< UART rx transfer end interrupt */
    UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */
    UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */
    UART_INT_RTO,         /*!< UART rx time-out interrupt */
    UART_INT_PCE,         /*!< UART rx parity check error interrupt */
    UART_INT_TX_FER,      /*!< UART tx fifo overflow/underflow error interrupt */
    UART_INT_RX_FER,      /*!< UART rx fifo overflow/underflow error interrupt */
    UART_INT_LSE,         /*!< UART rx lin mode sync field error interrupt */
    UART_INT_ALL,         /*!< All the interrupt */
} UART_INT_Type;

/**
 *  @brief UART overflow or underflow type definition
 */
typedef enum {
    UART_TX_OVERFLOW,  /*!< UART tx fifo overflow */
    UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */
    UART_RX_OVERFLOW,  /*!< UART rx fifo overflow */
    UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */
} UART_Overflow_Type;

/**
 *  @brief UART configuration structure type definition
 */
typedef struct
{
    uint32_t uartClk;                        /*!< Uart module clock */
    uint32_t baudRate;                       /*!< Uart baudrate */
    UART_DataBits_Type dataBits;             /*!< Uart frame length of data bit */
    UART_StopBits_Type stopBits;             /*!< Uart frame length of stop bit */
    UART_Parity_Type parity;                 /*!< Uart parity check type */
    BL_Fun_Type ctsFlowControl;              /*!< Enable or disable tx CTS flow control */
    BL_Fun_Type rxDeglitch;                  /*!< Enable or disable rx input de-glitch function */
    BL_Fun_Type rtsSoftwareControl;          /*!< Enable or disable rx RTS output SW control mode */
    BL_Fun_Type txSoftwareControl;           /*!< Enable or disable tx output SW control mode */
    BL_Fun_Type txLinMode;                   /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */
    BL_Fun_Type rxLinMode;                   /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */
    uint8_t txBreakBitCnt;                   /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at
                                                 least 13 bit times */
    UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */
} UART_CFG_Type;

/**
 *  @brief UART FIFO configuration structure type definition
 */
typedef struct
{
    uint8_t txFifoDmaThreshold;  /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */
    uint8_t rxFifoDmaThreshold;  /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */
    BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
    BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
} UART_FifoCfg_Type;

/**
 *  @brief UART infrared configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type txIrEnable;  /*!< Enable or disable uart tx ir mode */
    BL_Fun_Type rxIrEnable;  /*!< Enable or disable uart rx ir mode */
    BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */
    BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */
    uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */
    uint16_t txIrPulseStop;  /*!< Set stop position of uart tx ir pulse */
    uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */
} UART_IrCfg_Type;

/*@} end of group UART_Public_Types */

/** @defgroup  UART_Public_Constants
 *  @{
 */

/** @defgroup  UART_ID_TYPE
 *  @{
 */
#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \
                               ((type) == UART1_ID) || \
                               ((type) == UART_ID_MAX))

/** @defgroup  UART_DIRECTION_TYPE
 *  @{
 */
#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \
                                      ((type) == UART_RX) || \
                                      ((type) == UART_TXRX))

/** @defgroup  UART_PARITY_TYPE
 *  @{
 */
#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \
                                   ((type) == UART_PARITY_ODD) ||  \
                                   ((type) == UART_PARITY_EVEN))

/** @defgroup  UART_DATABITS_TYPE
 *  @{
 */
#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \
                                     ((type) == UART_DATABITS_6) || \
                                     ((type) == UART_DATABITS_7) || \
                                     ((type) == UART_DATABITS_8))

/** @defgroup  UART_STOPBITS_TYPE
 *  @{
 */
#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) ||   \
                                     ((type) == UART_STOPBITS_1_5) || \
                                     ((type) == UART_STOPBITS_2))

/** @defgroup  UART_BYTEBITINVERSE_TYPE
 *  @{
 */
#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \
                                           ((type) == UART_MSB_FIRST))

/** @defgroup  UART_AUTOBAUDDETECTION_TYPE
 *  @{
 */
#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \
                                              ((type) == UART_AUTOBAUD_STARTBIT))

/** @defgroup  UART_INT_TYPE
 *  @{
 */
#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) ||      \
                                ((type) == UART_INT_RX_END) ||      \
                                ((type) == UART_INT_TX_FIFO_REQ) || \
                                ((type) == UART_INT_RX_FIFO_REQ) || \
                                ((type) == UART_INT_RTO) ||         \
                                ((type) == UART_INT_PCE) ||         \
                                ((type) == UART_INT_TX_FER) ||      \
                                ((type) == UART_INT_RX_FER) ||      \
                                ((type) == UART_INT_LSE) ||         \
                                ((type) == UART_INT_ALL))

/** @defgroup  UART_OVERFLOW_TYPE
 *  @{
 */
#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) ||  \
                                     ((type) == UART_TX_UNDERFLOW) || \
                                     ((type) == UART_RX_OVERFLOW) ||  \
                                     ((type) == UART_RX_UNDERFLOW))

/*@} end of group UART_Public_Constants */

/** @defgroup  UART_Public_Macros
 *  @{
 */
#define UART_RX_FIFO_SIZE         128
#define UART_TX_FIFO_SIZE         128
#define UART_DEFAULT_RECV_TIMEOUT 80

/*@} end of group UART_Public_Macros */

/** @defgroup  UART_Public_Functions
 *  @{
 */

/**
 *  @brief UART Functions
 */
#if (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER)
void UART0_IRQHandler(void);
void UART1_IRQHandler(void);
#endif
BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg);
BL_Err_Type UART_DeInit(UART_ID_Type uartId);
BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg);
BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg);
BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct);
BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct);
BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time);
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt);
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_SetTxValue(UART_ID_Type uartId);
BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId);
BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun);
BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud);
BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId);
BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId);
BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask);
BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType);
BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun);
BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len);
BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len);
uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen);
uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
uint8_t UART_GetTxFifoCount(UART_ID_Type uartId);
uint8_t UART_GetRxFifoCount(UART_ID_Type uartId);
BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType);
BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId);
BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId);
BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow);

/*@} end of group UART_Public_Functions */

/*@} end of group UART */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_UART_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_usb.h
================================================
/**
  ******************************************************************************
  * @file    bl702_usb.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_USB_H__
#define __BL702_USB_H__

#include "usb_reg.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  USB
 *  @{
 */

/** @defgroup  USB_Public_Types
 *  @{
 */

/**
 *  @brief USB end point ID
 */
typedef enum {
    EP_ID0 = 0, /*!< USB end point 0 */
    EP_ID1,     /*!< USB end point 1 */
    EP_ID2,     /*!< USB end point 2 */
    EP_ID3,     /*!< USB end point 3 */
    EP_ID4,     /*!< USB end point 4 */
    EP_ID5,     /*!< USB end point 5 */
    EP_ID6,     /*!< USB end point 6 */
    EP_ID7,     /*!< USB end point 7 */
} USB_EP_ID;

/**
 *  @brief USB end point type
 */
typedef enum {
    EP_INT = 0,  /*!< interrupt transfer ep */
    EP_ISO = 2,  /*!< isochronous transfer ep */
    EP_BULK = 4, /*!< bulk transfer ep */
    EP_CTRL = 5, /*!< control transfer ep */
} EP_XFER_Type;

/**
 *  @brief USB end point transfer directions
 */
typedef enum {
    EP_DISABLED = 0, /*!< end point disabled */
    EP_IN = 1,       /*!< IN end point,device to host */
    EP_OUT = 2,      /*!< OUT end point ,host to device */
} EP_XFER_DIR;

typedef enum {
    USB_INT_SOF = 0,
    USB_INT_RESET,
    USB_INT_VBUS_TGL,
    USB_INT_GET_DCT_CMD,
    USB_INT_EP0_SETUP_CMD,
    USB_INT_EP0_SETUP_DONE,
    USB_INT_EP0_IN_CMD,
    USB_INT_EP0_IN_DONE,
    USB_INT_EP0_OUT_CMD,
    USB_INT_EP0_OUT_DONE,
    USB_INT_EP1_CMD,
    USB_INT_EP1_DONE,
    USB_INT_EP2_CMD,
    USB_INT_EP2_DONE,
    USB_INT_EP3_CMD,
    USB_INT_EP3_DONE,
    USB_INT_EP4_CMD,
    USB_INT_EP4_DONE,
    USB_INT_EP5_CMD,
    USB_INT_EP5_DONE,
    USB_INT_EP6_CMD,
    USB_INT_EP6_DONE,
    USB_INT_EP7_CMD,
    USB_INT_EP7_DONE,
    USB_INT_RESET_END = 27,
    USB_INT_LPM_WAKEUP = 28,
    USB_INT_LPM_PACKET = 29,
    USB_INT_LOST_SOF_3_TIMES = 30,
    USB_INT_ERROR = 31,
    USB_INT_ALL = 32, /* special */
} USB_INT_Type;

typedef enum {
    USB_FIFO_EMPTY = 0,
    USB_FIFO_FULL,
} USB_FIFO_STATUS_Type;

typedef enum {
    USB_FIFO_ERROR_OVERFLOW = 0,
    USB_FIFO_ERROR_UNDERFLOW,
} USB_FIFO_ERROR_FLAG_Type;

typedef enum {
    USB_EP_STATUS_ACK = 0,
    USB_EP_STATUS_NACK,
    USB_EP_STATUS_STALL,
    USB_EP_STATUS_NSTALL,
} USB_EP_STATUS_Type;

typedef enum {
    USB_LPM_DEFAULT_RESP_ACK = 0,
    USB_LPM_DEFAULT_RESP_NACK,
    USB_LPM_DEFAULT_RESP_STALL,
    USB_LPM_DEFAULT_RESP_NYET,
} USB_LPM_DEFAULT_RESP_Type;

typedef enum {
    USB_ERROR_UTMI_RX = 0,
    USB_ERROR_XFER_TO,
    USB_ERROR_IVLD_EP,
    USB_ERROR_PID_SEQ,
    USB_ERROR_PID_CKS,
    USB_ERROR_CRC5,
    USB_ERROR_CRC16,
} USB_ERROR_Type;

/**
 *  @brief USB configuration structure type definition
 */
typedef struct
{
    BL_Fun_Type EnumOutEn;             /*!< EP0 IN direction enable or disable */
    BL_Fun_Type EnumInEn;              /*!< EP0 OUT direction enable or disable */
    uint8_t EnumMaxPacketSize;         /*!< EP0 max packet size, only valid when SoftwareCtrl is set */
    uint8_t DeviceAddress;             /*!< Device(EP0) address, only valid when SoftwareCtrl is set */
    BL_Fun_Type SoftwareCtrl;          /*!< EP0 software control enable */
    BL_Fun_Type RomBaseDescriptorUsed; /*!< Enable signal of ROM-based descriptors (don't care if SoftwareCtrl is set) */
} USB_Config_Type;

/**
 *  @brief end point configuration structure type definition
 */
typedef struct
{
    uint16_t EPMaxPacketSize; /*!< Endpoint max packet size */
    EP_XFER_DIR dir;          /*!< Endpoint direction */
    EP_XFER_Type type;        /*!< Endpoint type */
} EP_Config_Type;

typedef struct
{
    uint32_t cr_ep_size     : 9;
    uint32_t cr_ep_dir      : 2;
    uint32_t cr_ep_type     : 3;
    uint32_t cr_ep_stall    : 1;
    uint32_t cr_ep_nack     : 1;
    uint32_t cr_ep_rdy      : 1;
    uint32_t reserved_17_31 : 15;
} usb_reg_epx_config_t;

typedef struct
{
    uint32_t ep_dma_tx_en         : 1;
    uint32_t ep_dma_rx_en         : 1;
    uint32_t ep_tx_fifo_clr       : 1;
    uint32_t ep_rx_fifo_clr       : 1;
    uint32_t ep_tx_fifo_overflow  : 1;
    uint32_t ep_tx_fifo_underflow : 1;
    uint32_t ep_rx_fifo_overflow  : 1;
    uint32_t ep_rx_fifo_underflow : 1;
    uint32_t reserved_8_31        : 24;
} usb_reg_epx_fifo_config_t;

typedef struct
{
    uint32_t ep_tx_fifo_cnt   : 7;
    uint32_t reserved_7_13    : 7;
    uint32_t ep_tx_fifo_empty : 1;
    uint32_t ep_tx_fifo_full  : 1;
    uint32_t ep_rx_fifo_cnt   : 7;
    uint32_t reserved_23_29   : 7;
    uint32_t ep_rx_fifo_empty : 1;
    uint32_t ep_rx_fifo_full  : 1;
} usb_reg_epx_fifo_status_t;

typedef struct
{
    uint32_t fifo          : 8;
    uint32_t reserved_8_31 : 24;
} usb_reg_epx_fifo_t;

/*@} end of group USB_Public_Types */

/** @defgroup  USB_Public_Constants
 *  @{
 */

/** @defgroup  USB_EP_ID
 *  @{
 */
#define IS_USB_EP_ID(type) (((type) == EP_ID0) || \
                            ((type) == EP_ID1) || \
                            ((type) == EP_ID2) || \
                            ((type) == EP_ID3) || \
                            ((type) == EP_ID4) || \
                            ((type) == EP_ID5) || \
                            ((type) == EP_ID6) || \
                            ((type) == EP_ID7))

/** @defgroup  EP_XFER_TYPE
 *  @{
 */
#define IS_EP_XFER_TYPE(type) (((type) == EP_INT) ||  \
                               ((type) == EP_ISO) ||  \
                               ((type) == EP_CTRL) || \
                               ((type) == EP_BULK))

/** @defgroup  EP_XFER_DIR
 *  @{
 */
#define IS_EP_XFER_DIR(type) (((type) == EP_DISABLED) || \
                              ((type) == EP_IN) ||       \
                              ((type) == EP_OUT))

/*@} end of group USB_Public_Constants */

/** @defgroup  USB_Public_Macros
 *  @{
 */
#define USB_INT_TYPE_SOF              0x00000001
#define USB_INT_TYPE_RESET            0x00000002
#define USB_INT_TYPE_GET_DCT_CMD      0x00000008
#define USB_INT_TYPE_EP0_SETUP_CMD    0x00000010
#define USB_INT_TYPE_EP0_SETUP_DONE   0x00000020
#define USB_INT_TYPE_EP0_IN_CMD       0x00000040
#define USB_INT_TYPE_EP0_IN_DONE      0x00000080
#define USB_INT_TYPE_EP0_OUT_CMD      0x00000100
#define USB_INT_TYPE_EP0_OUT_DONE     0x00000200
#define USB_INT_TYPE_EP1_CMD          0x00000400
#define USB_INT_TYPE_EP1_DONE         0x00000800
#define USB_INT_TYPE_EP2_CMD          0x00001000
#define USB_INT_TYPE_EP2_DONE         0x00002000
#define USB_INT_TYPE_EP3_CMD          0x00004000
#define USB_INT_TYPE_EP3_DONE         0x00008000
#define USB_INT_TYPE_EP4_CMD          0x00010000
#define USB_INT_TYPE_EP4_DONE         0x00020000
#define USB_INT_TYPE_EP5_CMD          0x00040000
#define USB_INT_TYPE_EP5_DONE         0x00080000
#define USB_INT_TYPE_EP6_CMD          0x00100000
#define USB_INT_TYPE_EP6_DONE         0x00200000
#define USB_INT_TYPE_EP7_CMD          0x00400000
#define USB_INT_TYPE_EP7_DONE         0x00800000
#define USB_INT_TYPE_RESET_END        0x08000000
#define USB_INT_TYPE_LPM_WAKEUP       0x10000000
#define USB_INT_TYPE_LPM_PACKET       0x20000000
#define USB_INT_TYPE_LOST_SOF_3_TIMES 0x40000000
#define USB_INT_TYPE_ERROR            0x80000000
#define USB_INT_TYPE_ALL              (USB_INT_TYPE_SOF | \
                          USB_INT_TYPE_RESET |            \
                          USB_INT_TYPE_GET_DCT_CMD |      \
                          USB_INT_TYPE_EP0_SETUP_CMD |    \
                          USB_INT_TYPE_EP0_SETUP_DONE |   \
                          USB_INT_TYPE_EP0_IN_CMD |       \
                          USB_INT_TYPE_EP0_IN_DONE |      \
                          USB_INT_TYPE_EP0_OUT_CMD |      \
                          USB_INT_TYPE_EP0_OUT_DONE |     \
                          USB_INT_TYPE_EP1_CMD |          \
                          USB_INT_TYPE_EP1_DONE |         \
                          USB_INT_TYPE_EP2_CMD |          \
                          USB_INT_TYPE_EP2_DONE |         \
                          USB_INT_TYPE_EP3_CMD |          \
                          USB_INT_TYPE_EP3_DONE |         \
                          USB_INT_TYPE_EP4_CMD |          \
                          USB_INT_TYPE_EP4_DONE |         \
                          USB_INT_TYPE_EP5_CMD |          \
                          USB_INT_TYPE_EP5_DONE |         \
                          USB_INT_TYPE_EP6_CMD |          \
                          USB_INT_TYPE_EP6_DONE |         \
                          USB_INT_TYPE_EP7_CMD |          \
                          USB_INT_TYPE_EP7_DONE |         \
                          USB_INT_TYPE_RESET_END |        \
                          USB_INT_TYPE_LPM_WAKEUP |       \
                          USB_INT_TYPE_LPM_PACKET |       \
                          USB_INT_TYPE_LOST_SOF_3_TIMES | \
                          USB_INT_TYPE_ERROR)

#define USB_EP_TX_FIFO_EMPTY    0x00004000
#define USB_EP_TX_FIFO_FULL     0x00008000
#define USB_EP_RX_FIFO_EMPTY    0x40000000
#define USB_EP_RX_FIFO_FULL     0x80000000
#define USB_EP_FIFO_STATUS_MASK (USB_EP_TX_FIFO_EMPTY | \
                                 USB_EP_TX_FIFO_FULL |  \
                                 USB_EP_RX_FIFO_EMPTY | \
                                 USB_EP_RX_FIFO_FULL)
#define USB_EP_TX_FIFO_OVERFLOW  0x00000010
#define USB_EP_TX_FIFO_UNDERFLOW 0x00000020
#define USB_EP_RX_FIFO_OVERFLOW  0x00000040
#define USB_EP_RX_FIFO_UNDERLOW  0x00000080
#define USB_EP_FIFO_ERROR_MASK   (USB_EP_TX_FIFO_OVERFLOW | \
                                USB_EP_TX_FIFO_UNDERFLOW |  \
                                USB_EP_RX_FIFO_OVERFLOW |   \
                                USB_EP_RX_FIFO_UNDERLOW)

#define EP_ID_MAX 8

/*@} end of group USB_Public_Macros */

/** @defgroup  USB_Public_Functions
 *  @{
 */

/**
 *  @brief USB Functions
 */

/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void USB_IRQHandler(void);
#endif
/*----------*/
BL_Err_Type USB_Enable(void);
BL_Err_Type USB_Disable(void);
BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg);
BL_Err_Type USB_Set_Device_Addr(uint8_t addr);
uint8_t USB_Get_Device_Addr(void);
/*----------*/
BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size);
BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId);
BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId);
BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts);
USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId);
/*----------*/
BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable);
BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask);
BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType);
BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType);
BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId);
/*----------*/
uint16_t USB_Get_Frame_Num(void);
/*----------*/
BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg);
BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type);
EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir);
EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId);
BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size);
/*----------*/
BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag);
BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag);
BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId);
BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId);
/*----------*/
BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len);
BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len);
/*----------*/
BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState);
BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState);
BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len);
BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len);
/*----------*/
uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId);
uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId);
BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts);
BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts);
/*----------*/
BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState);
/*----------*/
BL_Sts_Type USB_Get_LPM_Status(void);
uint16_t USB_Get_LPM_Packet_Attr(void);
BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp);
BL_Err_Type USB_LPM_Enable(void);
BL_Err_Type USB_LPM_Disable(void);
/*----------*/
BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth);
/*----------*/
uint8_t USB_Get_Current_Packet_PID(void);
uint8_t USB_Get_Current_Packet_EP(void);
/*----------*/
BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err);
BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err);
/*----------*/

/*@} end of group USB_Public_Functions */

/*@} end of group USB */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_USB_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h
================================================
/**
  ******************************************************************************
  * @file    bl702_xip_sflash.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_XIP_SFLASH_H__
#define __BL702_XIP_SFLASH_H__

#include "bl702_common.h"
#include "bl702_sflash.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  XIP_SFLASH
 *  @{
 */

/** @defgroup  XIP_SFLASH_Public_Types
 *  @{
 */

/*@} end of group XIP_SFLASH_Public_Types */

/** @defgroup  XIP_SFLASH_Public_Constants
 *  @{
 */

/*@} end of group XIP_SFLASH_Public_Constants */

/** @defgroup  XIP_SFLASH_Public_Macros
 *  @{
 */

/*@} end of group XIP_SFLASH_Public_Macros */

/** @defgroup  XIP_SFLASH_Public_Functions
 *  @{
 */
void XIP_SFlash_Opt_Enter(void);
void XIP_SFlash_Opt_Exit(void);
BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset);
BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset);
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
                                       uint32_t startaddr, uint32_t endaddr);
BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
                                       uint8_t *data, uint32_t len);
BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
                                      uint8_t *data, uint32_t len);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
                                            uint8_t *data);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
                                             uint8_t *data);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
                                             uint8_t *data, uint8_t idLen);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);

/*@} end of group XIP_SFLASH_Public_Functions */

/*@} end of group XIP_SFLASH */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_XIP_SFLASH_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h
================================================
/**
  ******************************************************************************
  * @file    bl702_xip_sflash_ext.h
  * @version V1.0
  * @date
  * @brief   This file is the standard driver header file
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __BL702_XIP_SFLASH_EXT_H__
#define __BL702_XIP_SFLASH_EXT_H__

#include "bl702_common.h"
#include "bl702_sflash.h"
#include "bl702_xip_sflash.h"
#include "bl702_sflash.h"
#include "bl702_sflash_ext.h"
#include "bl702_sf_cfg.h"
#include "bl702_sf_cfg_ext.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  XIP_SFLASH
 *  @{
 */

/** @defgroup  XIP_SFLASH_EXT_Public_Types
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Public_Types */

/** @defgroup  XIP_SFLASH_EXT_Public_Constants
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Public_Constants */

/** @defgroup  XIP_SFLASH_EXT_Public_Macros
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Public_Macros */

/** @defgroup  XIP_SFLASH_EXT_Public_Functions
 *  @{
 */

BL_Err_Type XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect);
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg);

/*@} end of group XIP_SFLASH_EXT_Public_Functions */

/*@} end of group XIP_SFLASH */

/*@} end of group BL702_Peripheral_Driver */

#endif /* __BL702_XIP_SFLASH_EXT_H__ */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_acomp.c
================================================
/**
 ******************************************************************************
 * @file    bl702_acomp.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_acomp.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  ACOMP
 *  @{
 */

/** @defgroup  ACOMP_Private_Macros
 *  @{
 */

/*@} end of group ACOMP_Private_Macros */

/** @defgroup  ACOMP_Private_Types
 *  @{
 */

/*@} end of group ACOMP_Private_Types */

/** @defgroup  ACOMP_Private_Variables
 *  @{
 */

/*@} end of group ACOMP_Private_Variables */

/** @defgroup  ACOMP_Global_Variables
 *  @{
 */

/*@} end of group ACOMP_Global_Variables */

/** @defgroup  ACOMP_Private_Fun_Declaration
 *  @{
 */

/*@} end of group ACOMP_Private_Fun_Declaration */

/** @defgroup  ACOMP_Private_Functions
 *  @{
 */

/*@} end of group ACOMP_Private_Functions */

/** @defgroup  ACOMP_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Analog compare init
                                                                                *
                                                                                * @param  acompNo: Compare ID
                                                                                * @param  cfg: Compare consideration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg) {
  uint32_t tmpVal = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));

  if (acompNo == AON_ACOMP0_ID) {
    /* Disable ACOMP first */
    tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);
    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);

    /* Set ACOMP config */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->levelFactor);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt);

    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);

  } else {
    /* Disable ACOMP first */
    tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);
    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);

    /* Set ACOMP config */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->levelFactor);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt);

    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Analog compare enable
                                                                                *
                                                                                * @param  acompNo: Compare ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) {
  uint32_t tmpVal = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));

  if (acompNo == AON_ACOMP0_ID) {
    tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);
    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
  } else {
    tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);
    tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Analog compare enable
                                                                                *
                                                                                * @param  acompNo: Compare ID
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) {
  uint32_t tmpVal = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));

  tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);

  /* Disable ACOMP first */
  if (acompNo == AON_ACOMP0_ID) {
    if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) {
      return SET;
    } else {
      return RESET;
    }
  } else {
    if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) {
      return SET;
    } else {
      return RESET;
    }
  }
}

/*@} end of group ACOMP_Public_Functions */

/*@} end of group ACOMP */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_adc.c
================================================
/**
 ******************************************************************************
 * @file    bl702_adc.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_adc.h"
#include "bl702_ef_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  ADC
 *  @{
 */

/** @defgroup  ADC_Private_Macros
 *  @{
 */
#undef MSG
#define MSG(...)
#define AON_CLK_SET_DUMMY_WAIT                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
  }
#define ADC_RESTART_DUMMY_WAIT BL702_Delay_US(100)

/*@} end of group ADC_Private_Macros */

/** @defgroup  ADC_Private_Types
 *  @{
 */

/*@} end of group ADC_Private_Types */

/** @defgroup  ADC_Private_Variables
 *  @{
 */
static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = {NULL};
ADC_Gain_Coeff_Type      adcGainCoeffCal            = {
                    .adcGainCoeffEnable = DISABLE,
                    .adcgainCoeffVal    = 0,
                    .coe                = 1,
};

/*@} end of group ADC_Private_Variables */

/** @defgroup  ADC_Global_Variables
 *  @{
 */

/*@} end of group ADC_Global_Variables */

/** @defgroup  ADC_Private_Fun_Declaration
 *  @{
 */

/*@} end of group ADC_Private_Fun_Declaration */

/** @defgroup  ADC_Private_Functions
 *  @{
 */

/*@} end of group ADC_Private_Functions */

/** @defgroup  ADC_Public_Functions
 *  @{
 */

/****************************************************************************/
/**
 * @brief  Software reset the whole ADC
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Reset(void) {
  uint32_t regCmd;

  /* reset ADC */
  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST));
  AON_CLK_SET_DUMMY_WAIT;
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST));
}

/****************************************************************************/
/**
 * @brief  ADC glable enable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC glable disable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC normal mode init
 *
 * @param  cfg: ADC normal mode configuration
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Init(ADC_CFG_Type *cfg) {
  uint32_t regCfg1;
  uint32_t regCfg2;
  uint32_t regCalib;

  CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel));
  CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel));
  CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv));
  CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1));
  CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2));
  CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode));
  CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel));
  CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm));
  CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref));
  CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode));
  CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth));

  /* config 1 */
  regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel);
  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN);
  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv);
  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);
  AON_CLK_SET_DUMMY_WAIT;

  /* config 2 */
  regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode);
  /* pga_vcmi_en is for mic */
  regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN);

  if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) {
    regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN);
  } else {
    regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN);
  }

  /* pga_os_cal is for mic */
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref);
  regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode);

  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2);

  /* calibration offset */
  regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE);
  regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler);
#endif

  ADC_Gain_Trim();
}

/****************************************************************************/
/**
 * @brief  ADC normal mode channel config
 *
 * @param  posCh: ADC pos channel type
 * @param  negCh: ADC neg channel type
 * @param  contEn: ENABLE or DISABLE continuous mode
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) {
  uint32_t regCmd;
  uint32_t regCfg1;

  CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh));
  CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh));

  /* set channel */
  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh);
  regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);

  /* set continuous mode */
  regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
  regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn);
  regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1);
}

/****************************************************************************/
/**
 * @brief  ADC scan mode channel config
 *
 * @param  posChList[]: ADC pos channel list type
 * @param  negChList[]: ADC neg channel list type
 * @param  scanLength: ADC scan length
 * @param  contEn: ENABLE or DISABLE continuous mode
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Scan_Channel_Config(const ADC_Chan_Type posChList[], const ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) {
  uint32_t tmpVal, i;
  uint32_t dealLen;

  CHECK_PARAM((scanLength < 13));

  /* Deal with the first 6 */
  dealLen = 6;

  if (scanLength < dealLen) {
    dealLen = scanLength;
  }

  /* Set first 6 scan channels */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1);

  for (i = 0; i < dealLen; i++) {
    tmpVal = tmpVal & (~(0x1F << (i * 5)));
    tmpVal |= (posChList[i] << (i * 5));
  }

  BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1);

  for (i = 0; i < dealLen; i++) {
    tmpVal = tmpVal & (~(0x1F << (i * 5)));
    tmpVal |= (negChList[i] << (i * 5));
  }

  BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal);

  /* Set the left channels */
  if (scanLength > dealLen) {
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2);

    for (i = 0; i < scanLength - dealLen; i++) {
      tmpVal = tmpVal & (~(0x1F << (i * 5)));
      tmpVal |= (posChList[i + dealLen] << (i * 5));
    }

    BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal);

    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2);

    for (i = 0; i < scanLength - dealLen; i++) {
      tmpVal = tmpVal & (~(0x1F << (i * 5)));
      tmpVal |= (negChList[i + dealLen] << (i * 5));
    }

    BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal);
  }

  /* Scan mode */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC normal mode convert start
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Start(void) {
  uint32_t regCmd;

  /* disable convert start */
  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);

  ADC_RESTART_DUMMY_WAIT;

  /* enable convert start */
  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
}

/****************************************************************************/
/**
 * @brief  ADC normal mode convert stop
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Stop(void) {
  uint32_t regCmd;

  /* disable convert start */
  regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
}

/****************************************************************************/
/**
 * @brief  ADC FIFO configuration
 *
 * @param  fifoCfg: ADC FIFO confifuration pointer
 *
 * @return None
 *
 *******************************************************************************/
void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold));

  /*
   *  DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur
   *  DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt
   */

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold);

  /* Enable DMA */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn);

  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC get DMA FIFO data count
 *
 * @param  None
 *
 * @return data count in FIFO
 *
 *******************************************************************************/
uint8_t ADC_Get_FIFO_Count(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

  return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT);
}

/****************************************************************************/
/**
 * @brief  ADC get DMA FIFO full status
 *
 * @param  None
 *
 * @return SET or RESET
 *
 *******************************************************************************/
BL_Sts_Type ADC_FIFO_Is_Full(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

  if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/
/**
 * @brief  ADC get DMA FIFO empty status
 *
 * @param  None
 *
 * @return SET or RESET
 *
 *******************************************************************************/
BL_Sts_Type ADC_FIFO_Is_Empty(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

  if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) {
    return RESET;
  } else {
    return SET;
  }
}

/****************************************************************************/
/**
 * @brief  ADC read DMA FIFO data
 *
 * @param  None
 *
 * @return ADC result if return 0 that means this is error data,user should ignore this data.
 *
 *******************************************************************************/
uint32_t ADC_Read_FIFO(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA);

  return (tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC parse result
 *
 * @param  orgVal: Original A to D value
 * @param  len: Original AD vaule count
 * @param  result: Final Result array pointer
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) {
  uint8_t             neg     = 0;
  uint32_t            tmpVal1 = 0, tmpVal2 = 0;
  ADC_Data_Width_Type dataType;
  ADC_SIG_INPUT_Type  sigType;
  uint32_t            i = 0;

  float coe = 1.0;

  if (adcGainCoeffCal.adcGainCoeffEnable) {
    coe = adcGainCoeffCal.coe;
  }

  tmpVal1  = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
  tmpVal2  = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL);
  sigType  = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE);

  if (sigType == ADC_INPUT_SINGLE_END) {
    for (i = 0; i < len; i++) {
      result[i].posChan = orgVal[i] >> 21;
      result[i].negChan = -1;
      uint32_t sample   = 0;
      if (dataType == ADC_DATA_WIDTH_12) {
        sample = ((orgVal[i] & 0xffff) >> 4);
      } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
        sample = ((orgVal[i] & 0xffff) >> 2);
      } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
        sample = (orgVal[i] & 0xffff);
      }

      result[i].value = (unsigned int)(sample / coe);

      // Saturate at 16 bits
      if (result[i].value > 0xFFFF) {
        result[i].value = 0xFFFF;
      }
    }
  }
  // else {
  //   for (i = 0; i < len; i++) {
  //     neg               = 0;
  //     result[i].posChan = orgVal[i] >> 21;
  //     result[i].negChan = (orgVal[i] >> 16) & 0x1F;

  //     if (orgVal[i] & 0x8000) {
  //       orgVal[i] = ~orgVal[i];
  //       orgVal[i] += 1;
  //       neg = 1;
  //     }

  //     if (dataType == ADC_DATA_WIDTH_12) {
  //       result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);
  //     } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
  //       result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);
  //     } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
  //       result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);
  //     }
  //     // Saturate at 16 bits
  //     if (result[i].value > 0xFFFF) {
  //       result[i].value = 0xFFFF;
  //     }
  //   }
  // }
}

/****************************************************************************/
/**
 * @brief  ADC mask or unmask certain or all interrupt
 *
 * @param  intType: interrupt type
 * @param  intMask: mask or unmask
 *
 * @return None
 *
 *******************************************************************************/
BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  switch (intType) {
  case ADC_INT_POS_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK);
    break;

  case ADC_INT_NEG_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK);
    break;

  case ADC_INT_FIFO_UNDERRUN:
    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
    break;

  case ADC_INT_FIFO_OVERRUN:
    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
    break;

  case ADC_INT_ADC_READY:
    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK);
    break;

  case ADC_INT_FIFO_READY:
    tmpVal = BL_RD_REG(AON_BASE, GPIP_GPADC_CONFIG);
    return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
    break;
  default:
    break;
  }
  return 0;
}

/****************************************************************************/
/**
 * @brief  ADC mask or unmask certain or all interrupt
 *
 * @param  intType: interrupt type
 * @param  intMask: mask or unmask
 *
 * @return None
 *
 *******************************************************************************/
void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  switch (intType) {
  case ADC_INT_POS_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
    }

    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
    break;

  case ADC_INT_NEG_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
    }

    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);
    break;

  case ADC_INT_FIFO_UNDERRUN:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
    }

    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    break;

  case ADC_INT_FIFO_OVERRUN:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
    }

    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    break;

  case ADC_INT_ADC_READY:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
    }

    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    break;

  case ADC_INT_FIFO_READY:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);

    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY_MASK);
    }

    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    break;

  case ADC_INT_ALL:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR);
      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
      BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

      tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
      BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_RD_REG(GPIP_BASE, AON_GPADC_REG_ISR);
      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK);
      BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

      tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK);
      BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
    }

    break;

  default:
    break;
  }
}

/****************************************************************************/
/**
 * @brief  ADC clear certain or all interrupt
 *
 * @param  intType: interrupt type
 *
 * @return None
 *
 *******************************************************************************/
void ADC_IntClr(ADC_INT_Type intType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));

  switch (intType) {
  case ADC_INT_POS_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    break;

  case ADC_INT_NEG_SATURATION:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    break;

  case ADC_INT_FIFO_UNDERRUN:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    break;

  case ADC_INT_FIFO_OVERRUN:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    break;

  case ADC_INT_ADC_READY:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    break;

  case ADC_INT_FIFO_READY:
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_RDY);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    break;

  case ADC_INT_ALL:
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR);
    BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal);

    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    /*Manual reset*/
    tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR);
    BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

    break;

  default:
    break;
  }
}

/****************************************************************************/
/**
 * @brief  ADC get interrupt status
 *
 * @param  intType: interrupt type
 *
 * @return SET or RESET
 *
 *******************************************************************************/
BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) {
  uint32_t    tmpVal;
  BL_Sts_Type bitStatus = RESET;

  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));

  switch (intType) {
  case ADC_INT_POS_SATURATION:
    tmpVal    = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET;
    break;

  case ADC_INT_NEG_SATURATION:
    tmpVal    = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET;
    break;

  case ADC_INT_FIFO_UNDERRUN:
    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET;
    break;

  case ADC_INT_FIFO_OVERRUN:
    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET;
    break;

  case ADC_INT_ADC_READY:
    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET;
    break;

  case ADC_INT_FIFO_READY:
    tmpVal    = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
    bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_RDY)) ? SET : RESET;
    break;

  case ADC_INT_ALL:
    break;

  default:
    break;
  }

  return bitStatus;
}

/****************************************************************************/
/**
 * @brief  ADC install interrupt callback
 *
 * @param  intType: ADC interrupt type
 * @param  cbFun: ADC interrupt callback
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType));

  adcIntCbfArra[intType] = cbFun;
}

/****************************************************************************/
/**
 * @brief  ADC DMA interrupt handler
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void GPADC_DMA_IRQHandler(void) {
  if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) {
    ADC_IntClr(ADC_INT_POS_SATURATION);

    if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) {
      adcIntCbfArra[ADC_INT_POS_SATURATION]();
    }
  }

  if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) {
    ADC_IntClr(ADC_INT_NEG_SATURATION);

    if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) {
      adcIntCbfArra[ADC_INT_NEG_SATURATION]();
    }
  }

  if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) {
    ADC_IntClr(ADC_INT_FIFO_UNDERRUN);

    if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) {
      adcIntCbfArra[ADC_INT_FIFO_UNDERRUN]();
    }
  }

  if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) {
    ADC_IntClr(ADC_INT_FIFO_OVERRUN);

    if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) {
      adcIntCbfArra[ADC_INT_FIFO_OVERRUN]();
    }
  }

  if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) {
    ADC_IntClr(ADC_INT_FIFO_READY);

    if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) {
      adcIntCbfArra[ADC_INT_FIFO_READY]();
    }
  }

  if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET) {
    ADC_IntClr(ADC_INT_FIFO_READY);

    if (adcIntCbfArra[ADC_INT_FIFO_READY] != NULL) {
      adcIntCbfArra[ADC_INT_FIFO_READY]();
    }
  }
}
#endif

/****************************************************************************/
/**
 * @brief  ADC VBAT enable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Vbat_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC VBAT disable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Vbat_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC TSEN Config
 *
 * @param  tsenMod: None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type));

  /* config gpadc_reg_cmd */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  /* enable sensor dc test mux*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN);
  /*selected sen output current channel*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0);
  /* enable chip sensor*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU);
  /*dwa_en */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);

  /* config 2 */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  /*tsvbe low=0*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
  /*dly_sel=2*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2);
  /*test_sel=0*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0);
  /*test_en=0*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN);
  /*ts_en*/
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);
  /*select tsen ext or inner*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2);
  /*pga vcmi enable*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
  /*0:512uS;1:16mS;2:32mS;3:64mS*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0);

  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);

  /* config 3 */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1);
  /* set gpadc_dither_en */
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal);

  /* set 4000F90C[19](gpadc_mic2_diff) = 1
   * debug advise form Ran
   * 2020.08.26
   */
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC TSEN Enable
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Tsen_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC TSEN Disable
 *
 * @return None
 *
 *******************************************************************************/
void ADC_Tsen_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC Clear fifo
 *
 * @return None
 *
 *******************************************************************************/
void ADC_FIFO_Clear(void) {
  uint32_t tmpVal;

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
}

/****************************************************************************/
/**
 * @brief  config pga
 *
 * @param  pga_vcmi_enable: enable or not vcmi
 * @param  pga_os_cal: pga os cal value
 * @return None
 *
 *******************************************************************************/
void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);

  if (pga_vcmi_enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN);
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal);

  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}
/****************************************************************************/
/**
 * @brief  TSEN_Get_V_Error
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
uint32_t TSEN_Get_V_Error(void) {
  uint32_t        v0 = 0, v1 = 0;
  uint32_t        v_error = 0;
  uint32_t        regVal  = 0;
  ADC_Result_Type result;
  uint32_t        tmpVal;
  uint8_t         gainCalEnabled = 0;

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

  ADC_SET_TSVBE_LOW();

  ADC_Start();

  while (ADC_Get_FIFO_Count() == 0)
    ;

  regVal                             = ADC_Read_FIFO();
  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
  adcGainCoeffCal.adcGainCoeffEnable = 0;
  ADC_Parse_Result(®Val, 1, &result);
  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
  v0                                 = result.value;

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

  ADC_SET_TSVBE_HIGH();

  ADC_Start();

  while (ADC_Get_FIFO_Count() == 0)
    ;

  regVal                             = ADC_Read_FIFO();
  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
  adcGainCoeffCal.adcGainCoeffEnable = 0;
  ADC_Parse_Result(®Val, 1, &result);
  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
  v1                                 = result.value;

  v_error = v0 - v1;

  return v_error;
}

/****************************************************************************/
/**
 * @brief  Trim TSEN
 *
 * @param  tsen_offset: None
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) {
  Efuse_TSEN_Refcode_Corner_Type trim;

  EF_Ctrl_Read_TSEN_Trim(&trim);
  if (trim.tsenRefcodeCornerEn) {
    if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {
      *tsen_offset = trim.tsenRefcodeCorner;

      return SUCCESS;
    }
  }

  return ERROR;
}

/****************************************************************************/
/**
 * @brief  SET ADC TSEN TSVBE LOW/HIGH
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_SET_TSVBE_LOW(void) {
  uint32_t tmpVal;
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  SET ADC TSEN TSVBE LOW/HIGH
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_SET_TSVBE_HIGH(void) {
  uint32_t tmpVal;
  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
}

/****************************************************************************/
/**
 * @brief  SET ADC TSEN TSVBE LOW/HIGH
 *
 * @param  tsen_offset: tsen_offset form efuse trim data
 *
 * @return tempture
 *
 *******************************************************************************/
float TSEN_Get_Temp(uint32_t tsen_offset) {
  uint32_t        v0 = 0, v1 = 0;
  float           temp   = 0;
  uint32_t        regVal = 0;
  ADC_Result_Type result;
  uint32_t        tmpVal;
  uint8_t         gainCalEnabled = 0;

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

  ADC_SET_TSVBE_LOW();

  ADC_Start();

  while (ADC_Get_FIFO_Count() == 0)
    ;

  regVal = ADC_Read_FIFO();

  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
  adcGainCoeffCal.adcGainCoeffEnable = 0;
  ADC_Parse_Result(®Val, 1, &result);
  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
  v0                                 = result.value;

  /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
  BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);

  ADC_SET_TSVBE_HIGH();

  ADC_Start();

  while (ADC_Get_FIFO_Count() == 0)
    ;

  regVal                             = ADC_Read_FIFO();
  gainCalEnabled                     = adcGainCoeffCal.adcGainCoeffEnable;
  adcGainCoeffCal.adcGainCoeffEnable = 0;
  ADC_Parse_Result(®Val, 1, &result);
  adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled;
  v1                                 = result.value;

  if (v0 > v1) {
    temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;
  } else {
    temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753;
  }

  return temp;
}

/****************************************************************************/
/**
 * @brief  ADC MIC Config
 *
 * @param  adc_mic_config: adc_mic_config
 *
 * @return success or not
 *
 *******************************************************************************/
BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) {
  uint32_t tmpVal1 = 0, tmpVal2 = 0;

  CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb));
  CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain));
  CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode));
  CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode));
  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn));
  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn));
  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn));
  CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn));

  tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);

  tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn);
  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn);

  if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) {
    /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/
    return ERROR;
  } else {
    tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn);
  }

  tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn);

  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1);

  return SUCCESS;
}

/****************************************************************************/
/**
 * @brief  ADC MIC bias control
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_MIC_Bias_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}

/****************************************************************************/
/**
 * @brief  ADC MIC bias control
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void ADC_MIC_Bias_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
  BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
}

/****************************************************************************/
/**
 * @brief  Trim ADC Gain
 *
 * @param  None
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) {
  Efuse_ADC_Gain_Coeff_Type trim;
  uint32_t                  tmp;

  EF_Ctrl_Read_ADC_Gain_Trim(&trim);

  if (trim.adcGainCoeffEn) {
    if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) {
      adcGainCoeffCal.adcGainCoeffEnable = ENABLE;
      adcGainCoeffCal.adcgainCoeffVal    = trim.adcGainCoeff;
      tmp                                = adcGainCoeffCal.adcgainCoeffVal;

      if (tmp & 0x800) {
        tmp = ~tmp;
        tmp += 1;
        tmp = tmp & 0xfff;
        // printf("val==%08x\r\n",(unsigned int)tmp);
        adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0));
        // printf("coe==%0f\r\n",adcGainCoeffCal.coe);
      } else {
        adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0));
        // printf("coe==%0f\r\n",adcGainCoeffCal.coe);
      }

      return SUCCESS;
    }
  }

  return ERROR;
}

/*@} end of group ADC_Public_Functions */

/*@} end of group ADC */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_aon.c
================================================
/**
 ******************************************************************************
 * @file    bl702_aon.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_aon.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  AON
 *  @{
 */

/** @defgroup  AON_Private_Macros
 *  @{
 */
#define AON_CLK_SET_DUMMY_WAIT                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
  }

/*@} end of group AON_Private_Macros */

/** @defgroup  AON_Private_Types
 *  @{
 */

/*@} end of group AON_Private_Types */

/** @defgroup  AON_Private_Variables
 *  @{
 */

/*@} end of group AON_Private_Variables */

/** @defgroup  AON_Global_Variables
 *  @{
 */

/*@} end of group AON_Global_Variables */

/** @defgroup  AON_Private_Fun_Declaration
 *  @{
 */

/*@} end of group AON_Private_Fun_Declaration */

/** @defgroup  AON_Private_Functions
 *  @{
 */

/*@} end of group AON_Private_Functions */

/** @defgroup  AON_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Power on MXX band gap
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) {
  uint32_t tmpVal = 0;

  /* Power up RF for PLL to work */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(55);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power off MXX band gap
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) {
  uint32_t tmpVal = 0;

  /* Power OFF */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power on XTAL
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  /* Polling for ready */
  do {
    BL702_Delay_US(10);
    timeOut++;
    tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
  } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);

  if (timeOut >= 120) {
    return TIMEOUT;
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set XTAL cap code
                                                                                *
                                                                                * @param  capIn: Cap code in
                                                                                * @param  capOut: Cap code out
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  BL702_Delay_US(100);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get XTAL cap code
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Cap code
                                                                                *
                                                                                *******************************************************************************/
uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);

  return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
}

/****************************************************************************/ /**
                                                                                * @brief  Set XTAL cap code
                                                                                *
                                                                                * @param  extra: cap cpde extra aon
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode_Extra(uint8_t extra) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  if (extra) {
    tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
  }
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off XTAL
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power on bandgap system
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) {
  uint32_t tmpVal = 0;

  /* power up RF for PLL to work */
  tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
  BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);

  BL702_Delay_US(55);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off bandgap system
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) {
  uint32_t tmpVal = 0;

  /* power up RF for PLL to work */
  tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
  BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);

  BL702_Delay_US(55);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on LDO11
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
  BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);

  BL702_Delay_US(55);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off LDO11
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
  BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);

  BL702_Delay_US(55);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on LDO15_RF
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void) {
  uint32_t tmpVal = 0;

  /* ldo15rf power on */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(90);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off LDO15_RF
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void) {
  uint32_t tmpVal = 0;

  /* ldo15rf power off */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power on source follow regular
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) {
  uint32_t tmpVal = 0;

  /* power on sfreg */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(10);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power off source follow regular
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) {
  uint32_t tmpVal = 0;

  /* power off sfreg */
  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off the power can be shut down in PDS0
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) {
  uint32_t tmpVal = 0;

  /* power off bz */
  tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
  BL_WR_REG(AON_BASE, AON_MISC, tmpVal);

  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
  tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  /* gating Clock, no more use */
  // tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
  // tmpVal=tmpVal&(~(1<<6));
  // tmpVal=tmpVal&(~(1<<7));
  // BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on the power powered down in PDS0
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);

  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(20);

  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(60);

  tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
  BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);

  BL702_Delay_US(20);

  /* power on bz */
  tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
  tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
  BL_WR_REG(AON_BASE, AON_MISC, tmpVal);

  /* ungating Clock, no more use */
  // tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
  // tmpVal=tmpVal|((1<<6));
  // tmpVal=tmpVal|((1<<7));
  // BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on the power powered down in PDS0
                                                                                *
                                                                                * @param  delay: None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((delay <= 0x3));

  /* config ldo11soc_sstart_delay_aon */
  tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
  BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief
                                                                                *
                                                                                * @param
                                                                                *
                                                                                * @return
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
  // dcdc18_vout_sel_aon, 1.425V*1.05=1.5V
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, voutSel);
  // dcdc18_vpfm_aon
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, vpfm);
  BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief
                                                                                *
                                                                                * @param
                                                                                *
                                                                                * @return
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
  // xtal_gm_boost
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_GM_BOOST_AON, gmBoost);
  // xtal_amp_ctrl
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_AMP_CTRL_AON, ampCtrl);
  // xtal_fast_startup
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_FAST_STARTUP_AON, fastStartup);
  BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);

  return SUCCESS;
}

/*@} end of group AON_Public_Functions */

/*@} end of group AON */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_cam.c
================================================
/**
 ******************************************************************************
 * @file    bl702_cam.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_cam.h"
#include "bl702.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  CAM
 *  @{
 */

/** @defgroup  CAM_Private_Macros
 *  @{
 */

/*@} end of group CAM_Private_Macros */

/** @defgroup  CAM_Private_Types
 *  @{
 */

/*@} end of group CAM_Private_Types */

/** @defgroup  CAM_Private_Variables
 *  @{
 */
static intCallback_Type *camIntCbfArra[CAM_INT_ALL] = {NULL};

/*@} end of group CAM_Private_Variables */

/** @defgroup  CAM_Global_Variables
 *  @{
 */

/*@} end of group CAM_Global_Variables */

/** @defgroup  CAM_Private_Fun_Declaration
 *  @{
 */

/*@} end of group CAM_Private_Fun_Declaration */

/** @defgroup  CAM_Private_Functions
 *  @{
 */

/*@} end of group CAM_Private_Functions */

/** @defgroup  CAM_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Camera module init
                                                                                *
                                                                                * @param  cfg: Camera configuration structure pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Init(CAM_CFG_Type *cfg) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode));
  CHECK_PARAM(IS_CAM_FRAME_MODE_TYPE(cfg->frameMode));
  CHECK_PARAM(IS_CAM_YUV_MODE_TYPE(cfg->yuvMode));
  CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol));
  CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol));
  CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType));
  CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);

  /* Set camera configuration */
  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_INTERLV_MODE, cfg->frameMode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HBURST, cfg->burstType);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount);

  switch (cfg->yuvMode) {
  case CAM_YUV422:
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
    break;

  case CAM_YUV420_EVEN:
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN);
    break;

  case CAM_YUV420_ODD:
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EVEN);
    break;

  case CAM_YUV400_EVEN:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
    break;

  case CAM_YUV400_ODD:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_SUBSAMPLE_EN);
    break;

  default:
    break;
  }

  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);

  /* Set frame count to issue interrupt at sw mode */
  tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt);
  BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal);

  /* Set camera memory start address, memory size and frame size in burst */
  BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_0, cfg->memStart0 & 0xFFFFFFF0);

  if (cfg->burstType == CAM_BURST_TYPE_SINGLE) {
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 4);
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 4);
  } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) {
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 16);
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 16);
  } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) {
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 32);
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 32);
  } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) {
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_0, cfg->memSize0 / 64);
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_0, cfg->frameSize0 / 64);
  }

  if (!cfg->frameMode) {
    BL_WR_REG(CAM_BASE, CAM_DVP2AHB_ADDR_START_1, cfg->memStart1 & 0xFFFFFFF0);

    if (cfg->burstType == CAM_BURST_TYPE_SINGLE) {
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 4);
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 4);
    } else if (cfg->burstType == CAM_BURST_TYPE_INCR4) {
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 16);
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 16);
    } else if (cfg->burstType == CAM_BURST_TYPE_INCR8) {
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 32);
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 32);
    } else if (cfg->burstType == CAM_BURST_TYPE_INCR16) {
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_MEM_BCNT_1, cfg->memSize1 / 64);
      BL_WR_REG(CAM_BASE, CAM_DVP2AHB_FRAME_BCNT_1, cfg->frameSize1 / 64);
    }
  }

  /* Clear interrupt */
  BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(CAM_IRQn, CAM_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  Deinit camera module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Deinit(void) {
  // GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_CAM);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable camera module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Enable(void) {
  uint32_t tmpVal;

  /* Enable camera module */
  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
  tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable camera module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Disable(void) {
  uint32_t tmpVal;

  /* Disable camera module */
  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE);
  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Camera clock gate function
                                                                                *
                                                                                * @param  enable: Enable or disable
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Clock_Gate(BL_Fun_Type enable) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable);
  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Camera hsync crop function
                                                                                *
                                                                                * @param  start: Valid hsync start count
                                                                                * @param  end: Valid hsync end count
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Hsync_Crop(uint16_t start, uint16_t end) { BL_WR_REG(CAM_BASE, CAM_HSYNC_CONTROL, (start << 16) + end); }

/****************************************************************************/ /**
                                                                                * @brief  Camera vsync crop function
                                                                                *
                                                                                * @param  start: Valid vsync start count
                                                                                * @param  end: Valid vsync end count
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Vsync_Crop(uint16_t start, uint16_t end) { BL_WR_REG(CAM_BASE, CAM_VSYNC_CONTROL, (start << 16) + end); }

/****************************************************************************/ /**
                                                                                * @brief  Camera set total valid pix count in a line function
                                                                                *
                                                                                * @param  count: Count value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Set_Hsync_Total_Count(uint16_t count) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count);
  BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Camera set total valid line count in a frame function
                                                                                *
                                                                                * @param  count: Count value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Set_Vsync_Total_Count(uint16_t count) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count);
  BL_WR_REG(CAM_BASE, CAM_FRAME_SIZE_CONTROL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Get one camera frame in interleave mode
                                                                                *
                                                                                * @param  info: Interleave mode camera frame infomation pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Interleave_Get_Frame_Info(CAM_Interleave_Frame_Info *info) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);

  info->validFrames   = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0);
  info->curFrameAddr  = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
  info->curFrameBytes = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
  info->status        = tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  Get one camera frame in planar mode
                                                                                *
                                                                                * @param  info: Planar mode camera frame infomation pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Planar_Get_Frame_Info(CAM_Planar_Frame_Info *info) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);

  info->validFrames0   = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_0);
  info->validFrames1   = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT_1);
  info->curFrameAddr0  = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR0_0);
  info->curFrameAddr1  = BL_RD_REG(CAM_BASE, CAM_FRAME_START_ADDR1_0);
  info->curFrameBytes0 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT0_0);
  info->curFrameBytes1 = BL_RD_REG(CAM_BASE, CAM_FRAME_BYTE_CNT1_0);
  info->status         = tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  Get available count 0 of frames
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Frames count
                                                                                *
                                                                                *******************************************************************************/
uint8_t CAM_Get_Frame_Count_0(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_0); }

/****************************************************************************/ /**
                                                                                * @brief  Get available count 1 of frames
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Frames count
                                                                                *
                                                                                *******************************************************************************/
uint8_t CAM_Get_Frame_Count_1(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT_1); }

/****************************************************************************/ /**
                                                                                * @brief  Pop one camera frame in interleave mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Interleave_Pop_Frame(void) {
  /* Pop one frame */
  BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 1);
}

/****************************************************************************/ /**
                                                                                * @brief  Pop one camera frame in planar mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Planar_Pop_Frame(void) {
  /* Pop one frame */
  BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3);
}

/****************************************************************************/ /**
                                                                                * @brief  CAMERA Enable Disable Interrupt
                                                                                *
                                                                                * @param  intType: CAMERA Interrupt Type
                                                                                * @param  intMask: Enable or Disable
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_IntMask(CAM_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_CAM_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(CAM_BASE, CAM_INT_CONTROL);

  switch (intType) {
  case CAM_INT_NORMAL_0:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_0_EN);
    }

    break;

  case CAM_INT_NORMAL_1:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_1_EN);
    }

    break;

  case CAM_INT_MEMORY_OVERWRITE_0:
  case CAM_INT_MEMORY_OVERWRITE_1:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN);
    }

    break;

  case CAM_INT_FRAME_OVERWRITE_0:
  case CAM_INT_FRAME_OVERWRITE_1:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN);
    }

    break;

  case CAM_INT_FIFO_OVERWRITE_0:
  case CAM_INT_FIFO_OVERWRITE_1:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN);
    }

    break;

  case CAM_INT_VSYNC_CNT_ERROR:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN);
    }

    break;

  case CAM_INT_HSYNC_CNT_ERROR:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN);
    }

    break;

  case CAM_INT_ALL:
    if (intMask == UNMASK) {
      /* Enable all interrupt */
      tmpVal |= 0x7F;
    } else {
      /* Disable all interrupt */
      tmpVal &= 0xFFFFFF80;
    }

    break;

  default:
    break;
  }

  BL_WR_REG(CAM_BASE, CAM_INT_CONTROL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  CAMERA Interrupt Clear
                                                                                *
                                                                                * @param  intType: CAMERA Interrupt Type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_IntClr(CAM_INT_Type intType) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP);

  switch (intType) {
  case CAM_INT_NORMAL_0:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_0);
    break;

  case CAM_INT_NORMAL_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR_1);
    break;

  case CAM_INT_MEMORY_OVERWRITE_0:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_0);
    break;

  case CAM_INT_MEMORY_OVERWRITE_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR_1);
    break;

  case CAM_INT_FRAME_OVERWRITE_0:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_0);
    break;

  case CAM_INT_FRAME_OVERWRITE_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR_1);
    break;

  case CAM_INT_FIFO_OVERWRITE_0:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_0);
    break;

  case CAM_INT_FIFO_OVERWRITE_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR_1);
    break;

  case CAM_INT_VSYNC_CNT_ERROR:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR_0);
    break;

  case CAM_INT_HSYNC_CNT_ERROR:
    tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR_0);
    break;

  case CAM_INT_ALL:
    tmpVal = 0xFFFF0;

  default:
    break;
  }

  BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Install camera interrupt callback function
                                                                                *
                                                                                * @param  intType: CAMERA interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_Int_Callback_Install(CAM_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_CAM_INT_TYPE(intType));

  camIntCbfArra[intType] = cbFun;
}

/****************************************************************************/ /**
                                                                                * @brief  CAM hardware mode with frame start address wrap to memory address start function enable or disable
                                                                                *
                                                                                * @param  enable: Enable or disable
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void CAM_HW_Mode_Wrap(BL_Fun_Type enable) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable);
  BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Camera interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void CAM_IRQHandler(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP_STATUS_AND_ERROR);

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_0)) {
    CAM_IntClr(CAM_INT_NORMAL_0);

    if (camIntCbfArra[CAM_INT_NORMAL_0] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_NORMAL_0]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT_1)) {
    CAM_IntClr(CAM_INT_NORMAL_1);

    if (camIntCbfArra[CAM_INT_NORMAL_1] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_NORMAL_1]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_0)) {
    CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_0);

    if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_0]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT_1)) {
    CAM_IntClr(CAM_INT_MEMORY_OVERWRITE_1);

    if (camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_MEMORY_OVERWRITE_1]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_0)) {
    CAM_IntClr(CAM_INT_FRAME_OVERWRITE_0);

    if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_FRAME_OVERWRITE_0]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT_1)) {
    CAM_IntClr(CAM_INT_FRAME_OVERWRITE_1);

    if (camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_FRAME_OVERWRITE_1]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_0)) {
    CAM_IntClr(CAM_INT_FIFO_OVERWRITE_0);

    if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_FIFO_OVERWRITE_0]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT_1)) {
    CAM_IntClr(CAM_INT_FIFO_OVERWRITE_1);

    if (camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_FIFO_OVERWRITE_1]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) {
    CAM_IntClr(CAM_INT_HSYNC_CNT_ERROR);

    if (camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_HSYNC_CNT_ERROR]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) {
    CAM_IntClr(CAM_INT_VSYNC_CNT_ERROR);

    if (camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR] != NULL) {
      /* call the callback function */
      camIntCbfArra[CAM_INT_VSYNC_CNT_ERROR]();
    }
  }
}
#endif

/*@} end of group CAM_Public_Functions */

/*@} end of group CAM */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_clock.c
================================================
/**
 ******************************************************************************
 * @file    bl702_clock.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_clock.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  CLOCK
 *  @{
 */

/** @defgroup  CLOCK_Private_Macros
 *  @{
 */

/*@} end of group CLOCK_Private_Macros */

/** @defgroup  CLOCK_Private_Types
 *  @{
 */

/*@} end of group CLOCK_Private_Types */

/** @defgroup  CLOCK_Private_Variables
 *  @{
 */
static Clock_Cfg_Type clkCfg;

/*@} end of group CLOCK_Private_Variables */

/** @defgroup  CLOCK_Global_Variables
 *  @{
 */

/*@} end of group CLOCK_Global_Variables */

/** @defgroup  CLOCK_Private_Fun_Declaration
 *  @{
 */

/*@} end of group CLOCK_Private_Fun_Declaration */

/** @defgroup  CLOCK_Private_Functions
 *  @{
 */

/*@} end of group CLOCK_Private_Functions */

/** @defgroup  CLOCK_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Set System Clock
                                                                                *
                                                                                * @param  type: System clock type
                                                                                * @param  clock: System clock value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock) {
  if (type < BL_SYSTEM_CLOCK_MAX) {
    clkCfg.systemClock[type] = clock / 1000000;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Set Peripheral Clock
                                                                                *
                                                                                * @param  type: Peripheral clock type
                                                                                * @param  clock: Peripheral clock value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock) {
  if (type < BL_AHB_SLAVE1_MAX) {
    if (type == BL_AHB_SLAVE1_I2S) {
      clkCfg.i2sClock = clock;
    } else {
      clkCfg.peripheralClock[type] = clock / 1000000;
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get System Clock
                                                                                *
                                                                                * @param  type: System clock type
                                                                                *
                                                                                * @return System clock value
                                                                                *
                                                                                *******************************************************************************/
uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) {
  if (type < BL_SYSTEM_CLOCK_MAX) {
    return clkCfg.systemClock[type] * 1000000;
  }

  return 0;
}

/****************************************************************************/ /**
                                                                                * @brief  Get Peripheral Clock
                                                                                *
                                                                                * @param  type: Peripheral clock type
                                                                                *
                                                                                * @return Peripheral clock value
                                                                                *
                                                                                *******************************************************************************/
uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type) {
  if (type < BL_AHB_SLAVE1_MAX) {
    if (type == BL_AHB_SLAVE1_I2S) {
      return clkCfg.i2sClock;
    } else {
      return clkCfg.peripheralClock[type] * 1000000;
    }
  }

  return 0;
}

/*@} end of group CLOCK_Public_Functions */

/*@} end of group CLOCK */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_common.c
================================================
/**
 ******************************************************************************
 * @file    bl702_common.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */
#include "bl702_common.h"
#include "l1c_reg.h"

/** @addtogroup  BL702_Periph_Driver
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief      delay us
                                                                                *
                                                                                * @param[in]  core:  systemcoreclock
                                                                                *
                                                                                * @param[in]  cnt:  delay cnt us
                                                                                *
                                                                                * @return none
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
#ifdef ARCH_ARM
#ifndef __GNUC__
__WEAK
__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt){
    lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2,
# 0x01 cmp r2, #0x00 bne loop end bx lr
}
#else
__WEAK
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) {
  __asm__ __volatile__("lsr r0,#0x10\n\t"
                       "mul r0,r1,r0\n\t"
                       "mov r2,r0\n\t"
                       "lsr r2,#0x04\n\t"
                       "lsr r2,#0x03\n\t"
                       "cmp r2,#0x01\n\t"
                       "beq end\n\t"
                       "cmp r2,#0x00\n\t"
                       "beq end\n"
                       "loop :"
                       "mov r0,r0\n\t"
                       "mov r0,r0\n\t"
                       "mov r0,r0\n\t"
                       "mov r0,r0\n\t"
                       "mov r0,r0\n\t"
                       "sub r2,r2,#0x01\n\t"
                       "cmp r2,#0x00\n\t"
                       "bne loop\n"
                       "end :"
                       "mov r0,r0\n\t");
}
#endif
#endif
#ifdef ARCH_RISCV
__WEAK void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) {
  uint32_t codeAddress = 0;
  uint32_t divVal      = 40;

  codeAddress = (uint32_t)&ASM_Delay_Us;

  /* 1M=100K*10, so multiple is 10 */
  /* loop function take 4 instructions, so instructionNum is 4 */
  /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
  /* divVal = multiple*instructionNum*irom2TAccess */
  if (((codeAddress & (0xF << 24)) >> 24) == 0x01) {
    /* IROM space */
    if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) {
      /* instruction 2T */
      divVal = 80;
    }
  }

  __asm__ __volatile__(".align 4\n\t"
                       "lw       a4,%1\n\t"
                       "lui   a5,0x18\n\t"
                       "addi  a5,a5,1696\n\t"
                       "divu  a5,a4,a5\n\t"
                       "sw       a5,%1\n\t"
                       "lw       a4,%1\n\t"
                       "lw       a5,%0\n\t"
                       "mul   a5,a4,a5\n\t"
                       "sw       a5,%1\n\t"
                       "lw       a4,%1\n\t"
                       "lw       a5,%2\n\t"
                       "divu  a5,a4,a5\n\t"
                       "sw    a5,%1\n\t"
                       "lw    a5,%1\n\t"
                       "li    a4,0x1\n\t"
                       "beq   a5,zero,end\n\t"
                       "beq   a5,a4,end\n\t"
                       "nop\n\t"
                       "nop\n\t"
                       ".align 4\n\t"
                       "loop  :\n"
                       "addi  a4,a5,-1\n\t"
                       "mv    a5,a4\n\t"
                       "bnez  a5,loop\n\t"
                       "nop\n\t"
                       "end   :\n\t"
                       "nop\n"
                       :                                  /* output */
                       : "m"(cnt), "m"(core), "m"(divVal) /* input */
                       : "t1", "a4", "a5"                 /* destruct description */
  );
}
#endif
#endif

/****************************************************************************/ /**
                                                                                * @brief      delay us
                                                                                *
                                                                                * @param[in]  cnt:  delay cnt us
                                                                                *
                                                                                * @return none
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION BL702_Delay_US(uint32_t cnt) { ASM_Delay_Us(SystemCoreClockGet(), cnt); }
#endif
/****************************************************************************/ /**
                                                                                * @brief      delay ms
                                                                                *
                                                                                * @param[in]  cnt:  delay cnt ms
                                                                                *
                                                                                * @return none
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION BL702_Delay_MS(uint32_t cnt) {
  uint32_t i     = 0;
  uint32_t count = 0;

  if (cnt >= 1024) {
    /* delay (n*1024) ms */
    count = 1024;

    for (i = 0; i < (cnt / 1024); i++) {
      BL702_Delay_US(1024 * 1000);
    }
  }

  if (cnt & 0x3FF) {
    /* delay (1-1023)ms */
    count = cnt & 0x3FF;
    BL702_Delay_US(count * 1000);
  }

  // BL702_Delay_US(((cnt<<10)-(cnt<<4)-(cnt<<3)));
}
#endif

/*
char *_sbrk(int incr)
{}
*/
/*@} end of group DRIVER_Public_Functions */

/*@} end of group DRIVER_COMMON */

/*@} end of group BL702_Periph_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dac.c
================================================
/**
 ******************************************************************************
 * @file    bl702_dac.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_dac.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  DAC
 *  @{
 */

/** @defgroup  DAC_Private_Macros
 *  @{
 */
#define GPIP_CLK_SET_DUMMY_WAIT                                                                                                                                                                        \
  {                                                                                                                                                                                                    \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
  }

/*@} end of group DAC_Private_Macros */

/** @defgroup  DAC_Private_Types
 *  @{
 */

/*@} end of group DAC_Private_Types */

/** @defgroup  DAC_Private_Variables
 *  @{
 */

/*@} end of group DAC_Private_Variables */

/** @defgroup  DAC_Global_Variables
 *  @{
 */

/*@} end of group DAC_Global_Variables */

/** @defgroup  DAC_Private_Fun_Declaration
 *  @{
 */

/*@} end of group DAC_Private_Fun_Declaration */

/** @defgroup  DAC_Private_Functions
 *  @{
 */

/*@} end of group DAC_Private_Functions */

/** @defgroup  DAC_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  DAC initialization
                                                                                *
                                                                                * @param  cfg: DAC configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));

  /* Set DAC config */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);

  if (ENABLE == cfg->resetChanA) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
    __NOP();
    __NOP();
    __NOP();
    __NOP();
  }

  if (ENABLE == cfg->resetChanB) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
    __NOP();
    __NOP();
    __NOP();
    __NOP();
  }

  /* Clear reset */
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  DAC channel A initialization
                                                                                *
                                                                                * @param  cfg: DAC channel configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));

  /* Set channel A config */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn);

  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  DAC channel B initialization
                                                                                *
                                                                                * @param  cfg: DAC channel configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));

  /* Set channel A config */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn);

  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Select DAC channel B source
                                                                                *
                                                                                * @param  src: DAC channel B source selection type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src));

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Select DAC channel A source
                                                                                *
                                                                                * @param  src: DAC channel A source selection type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src));

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable DAC channel B
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_DAC_ChanB_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable DAC channel B
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_DAC_ChanB_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN2);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable DAC channel A
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_DAC_ChanA_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable DAC channel A
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_DAC_ChanA_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Select DAC DMA TX format
                                                                                *
                                                                                * @param  fmt: DAC DMA TX format selection type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt));

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable DAC DMA TX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_Set_DAC_DMA_TX_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable DAC DMA TX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_Set_DAC_DMA_TX_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable DAC DMA TX
                                                                                *
                                                                                * @param  data: The data to be send
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GPIP_DAC_DMA_WriteData(uint32_t data) { BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data); }

/****************************************************************************/ /**
                                                                                * @brief  AON and GPIP DAC config
                                                                                *
                                                                                * @param  cfg: AON and GPIP DAC configuration
                                                                                *
                                                                                * @return config success or not
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
  CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div));
  CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt));

  /* AON Set DAC config */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel);

  if (ENABLE == cfg->resetChanA) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
    __NOP();
    __NOP();
    __NOP();
    __NOP();
  }

  if (ENABLE == cfg->resetChanB) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
    tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);
    __NOP();
    __NOP();
    __NOP();
    __NOP();
  }

  /* AON Clear reset */
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal);

  /* GPIP Set DAC config */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);

  /* GPIP Set DMA config */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  AON and GPIP DAC channel A config
                                                                                *
                                                                                * @param  cfg: AON and GPIP DAC channel A configuration
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src));

  /* GPIP select source */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);

  /* GPIP enable or disable channel */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);

  /* AON enable or disable channel */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  AON and GPIP DAC channel B config
                                                                                *
                                                                                * @param  cfg: AON and GPIP DAC channel B configuration
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src));

  /* GPIP select source */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);

  /* GPIP enable or disable channel */
  tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN2, cfg->chanEn);
  BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal);

  /* AON enable or disable channel */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  DAC channel A set value
                                                                                *
                                                                                * @param  val: DAC value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_DAC_Set_ChanA_Value(uint16_t val) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  DAC channel B set value
                                                                                *
                                                                                * @param  val: DAC value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void GLB_DAC_Set_ChanB_Value(uint16_t val) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_DATA);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val);
  tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_DATA, tmpVal);
}

/*@} end of group DAC_Public_Functions */

/*@} end of group DAC */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_dma.c
================================================
/**
 ******************************************************************************
 * @file    bl702_dma.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_dma.h"
#include "bl702.h"
#include "bl702_glb.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  DMA
 *  @{
 */

/** @defgroup  DMA_Private_Macros
 *  @{
 */
#define DMA_CHANNEL_OFFSET  0x100
#define DMA_Get_Channel(ch) (DMA_BASE + DMA_CHANNEL_OFFSET + (ch) * 0x100)
static intCallback_Type *dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL] = {
    {NULL, NULL},
    {NULL, NULL},
    {NULL, NULL},
    {NULL, NULL}
};
// static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2];

/*@} end of group DMA_Private_Macros */

/** @defgroup  DMA_Private_Types
 *  @{
 */

/*@} end of group DMA_Private_Types */

/** @defgroup  DMA_Private_Variables
 *  @{
 */

/*@} end of group DMA_Private_Variables */

/** @defgroup  DMA_Global_Variables
 *  @{
 */

/*@} end of group DMA_Global_Variables */

/** @defgroup  DMA_Private_Fun_Declaration
 *  @{
 */

/*@} end of group DMA_Private_Fun_Declaration */

/** @defgroup  DMA_Private_Functions
 *  @{
 */

/**
 * @brief  DMA interrupt handler
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void DMA_ALL_IRQHandler(void) {
  uint32_t tmpVal;
  uint32_t intClr;
  uint8_t  ch;
  /* Get DMA register */
  uint32_t DMAChs = DMA_BASE;

  for (ch = 0; ch < DMA_CH_MAX; ch++) {
    tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);

    if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) {
      /* Clear interrupt */
      tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
      intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
      intClr |= (1 << ch);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
      BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);

      if (dmaIntCbfArra[ch][DMA_INT_TCOMPLETED] != NULL) {
        /* Call the callback function */
        dmaIntCbfArra[ch][DMA_INT_TCOMPLETED]();
      }
    }
  }

  for (ch = 0; ch < DMA_CH_MAX; ch++) {
    tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);

    if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) {
      /*Clear interrupt */
      tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
      intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
      intClr |= (1 << ch);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
      BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);

      if (dmaIntCbfArra[ch][DMA_INT_ERR] != NULL) {
        /* Call the callback function */
        dmaIntCbfArra[ch][DMA_INT_ERR]();
      }
    }
  }
}
#endif

/*@} end of group DMA_Private_Functions */

/** @defgroup  DMA_Public_Functions
 *  @{
 */

/**
 * @brief  DMA enable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Enable(void) {
  uint32_t tmpVal;
  /* Get DMA register */
  uint32_t DMAChs = DMA_BASE;

  tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
  BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(DMA_ALL_IRQn, DMA_ALL_IRQHandler);
#endif
}

/**
 * @brief  DMA disable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Disable(void) {
  uint32_t tmpVal;
  /* Get DMA register */
  uint32_t DMAChs = DMA_BASE;

  tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
  BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
}

/**
 * @brief  DMA channel init
 *
 * @param  chCfg: DMA configuration
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(chCfg->ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch));
  CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth));
  CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth));
  CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSize));
  CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSize));
  CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir));
  CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph));
  CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph));

  /* Disable clock gate */
  // Turns on clock
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA);

  /* Config channel config */
  BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr);
  BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr);

  tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSize);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSize);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt);

  /* FIXME: how to deal with SLargerD */
  tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD); // Reserved bit 25
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc);
  BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);

  tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph);
  BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
  // Clear interrupts
  *((uint32_t *)0x4000c008) = 1 << (chCfg->ch); // Clear transfer complete
  *((uint32_t *)0x4000c010) = 1 << (chCfg->ch); // Clear Error
}

/**
 * @brief  DMA channel update source memory address and len
 *
 * @param  ch: DMA channel
 * @param  memAddr: source memoty address
 * @param  len: source memory data length
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  /* config channel config*/
  BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr);
  tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
  BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}

/**
 * @brief  DMA channel update destination memory address and len
 *
 * @param  ch: DMA channel
 * @param  memAddr: destination memoty address
 * @param  len: destination memory data length
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  /* config channel config*/
  BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr);
  tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
  BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}

/**
 * @brief  Get DMA channel tranfersize
 *
 * @param  ch: DMA channel
 *
 * @return tranfersize size
 *
 *******************************************************************************/
uint32_t DMA_Channel_TranferSize(uint8_t ch) {
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE);
}

/**
 * @brief  Get DMA channel busy status
 *
 * @param  ch: DMA channel
 *
 * @return SET or RESET
 *
 *******************************************************************************/
BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch) {
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET;
}

/**
 * @brief  DMA enable
 *
 * @param  ch: DMA channel number
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Channel_Enable(uint8_t ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
  BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}

/**
 * @brief  DMA disable
 *
 * @param  ch: DMA channel number
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Channel_Disable(uint8_t ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
  BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}

/**
 * @brief  DMA init LLI transfer
 *
 * @param  ch: DMA channel number
 * @param  lliCfg: LLI configuration
 *
 * @return None
 *
 *******************************************************************************/
void DMA_LLI_Init(uint8_t ch, DMA_LLI_Cfg_Type *lliCfg) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
  CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir));
  CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph));
  CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_DMA);

  tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph);
  BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}

/**
 * @brief  DMA channel update LLI
 *
 * @param  ch: DMA channel number
 * @param  LLI: LLI addr
 *
 * @return None
 *
 *******************************************************************************/
void DMA_LLI_Update(uint8_t ch, uint32_t LLI) {
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));

  /* Config channel config */
  // BL_WR_REG(DMAChs, DMA_LLI, LLI);
  BL702_MemCpy4((uint32_t *)DMAChs, (uint32_t *)LLI, 4);
}

/**
 * @brief  Mask/Unmask the DMA interrupt
 *
 * @param  ch: DMA channel number
 * @param  intType: Specifies the interrupt type
 * @param  intMask: Enable/Disable Specified interrupt type
 *
 * @return None
 *
 *******************************************************************************/
void DMA_IntMask(uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t DMAChs = DMA_Get_Channel(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
  CHECK_PARAM(IS_DMA_INT_TYPE(intType));

  switch (intType) {
  case DMA_INT_TCOMPLETED:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
      tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
      BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
      tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
      BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
    }

    break;

  case DMA_INT_ERR:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
    }

    break;

  case DMA_INT_ALL:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC);
      tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
      tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
      tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I);
      BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC);
      tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE);
      BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
      tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
      tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I);
      BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
    }

    break;

  default:
    break;
  }
}

/**
 * @brief  Install DMA interrupt callback function
 *
 * @param  dmaChan: DMA Channel type
 * @param  intType: DMA interrupt type
 * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
 *
 * @return None
 *
 *******************************************************************************/
void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan));
  CHECK_PARAM(IS_DMA_INT_TYPE(intType));

  dmaIntCbfArra[dmaChan][intType] = cbFun;
}

/*@} end of group DMA_Public_Functions */

/*@} end of group DMA */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ef_ctrl.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sec_ef_ctrl.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_ef_ctrl.h"
#include "ef_data_0_reg.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SEC_EF_CTRL
 *  @{
 */

/** @defgroup  SEC_EF_CTRL_Private_Macros
 *  @{
 */
#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)
#define EF_CTRL_EFUSE_CTRL_PROTECT  (0xbf << 8)
#define EF_CTRL_DFT_TIMEOUT_VAL     (160 * 1000)
#ifndef BOOTROM
#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0()
#else
#define EF_CTRL_LOAD_BEFORE_READ_R0
#endif
#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4)

/*@} end of group SEC_EF_CTRL_Private_Macros */

/** @defgroup  SEC_EF_CTRL_Private_Types
 *  @{
 */

/*@} end of group SEC_EF_CTRL_Private_Types */

/** @defgroup  SEC_EF_CTRL_Private_Variables
 *  @{
 */

/*@} end of group SEC_EF_CTRL_Private_Variables */

/** @defgroup  SEC_EF_CTRL_Global_Variables
 *  @{
 */

/*@} end of group SEC_EF_CTRL_Global_Variables */

/** @defgroup  SEC_EF_CTRL_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */

/** @defgroup  SEC_EF_CTRL_Private_Functions
 *  @{
 */

/****************************************************************************
 * @brief  Switch efuse region 0 control to AHB clock
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
/* static */ void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) {
  uint32_t tmpVal;
  uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;

  while (EF_Ctrl_Busy() == SET) {
    timeout--;

    if (timeout == 0) {
      break;
    }
  }

  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);

  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************
 * @brief  Program efuse region 0
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
static void EF_Ctrl_Program_Efuse_0(void) {
  uint32_t tmpVal;

  /* Select auto mode and select ef clock */
  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);

  /* Program */
  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (1 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (1 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);

  /* Add delay for POR to be stable */
  BL702_Delay_US(4);

  /* Trigger */
  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (1 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (1 << EF_CTRL_EF_IF_0_RW_POS) | (1 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
}

/*@} end of group SEC_EF_CTRL_Private_Functions */

/** @defgroup  SEC_EF_CTRL_Public_Functions
 *  @{
 */

/****************************************************************************
 * @brief  Load efuse region 0
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) {
  uint32_t tmpVal;
  uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;

  EF_CTRL_DATA0_CLEAR;

  /* Trigger read */
  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);

  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (0 << EF_CTRL_EF_IF_0_RW_POS) | (1 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);

  BL702_Delay_US(10);

  /* Wait for efuse control idle*/
  do {
    tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);
    timeout--;

    if (timeout == 0) {
      break;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) ||

           (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)));

  /* Switch to AHB clock */
  tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
           (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | (0 << EF_CTRL_EF_IF_POR_DIG_POS) | (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
           (0 << EF_CTRL_EF_IF_0_RW_POS) | (0 << EF_CTRL_EF_IF_0_TRIG_POS);
  BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************
 * @brief  Check efuse busy status
 *
 * @param  None
 *
 * @return SET or RESET
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);

  if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) {
    return SET;
  }

  return RESET;
}
#endif

/****************************************************************************
 * @brief  Check efuse whether finish loading
 *
 * @param  None
 *
 * @return SET or RESET
 *
 *******************************************************************************/
BL_Sts_Type EF_Ctrl_AutoLoad_Done(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0);

  if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************
 * @brief  Efuse write debug password
 *
 * @param  passWdLow: password low 32 bits
 * @param  passWdHigh: password high 32 bits
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) {
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read debug password
 *
 * @param  passWdLow: password low 32 bits pointer to store value
 * @param  passWdHigh: password high 32 bits pointer to store value
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) {
  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  *passWdLow  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
  *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
}

/****************************************************************************
 * @brief  Efuse lock reading for passwd
 *
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) {
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse lock writing for passwd
 *
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) {
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read security configuration
 *
 * @param  cfg: security configuration pointer
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read security configuration
 *
 * @param  cfg: security configuration pointer
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) {
  uint32_t tmpVal;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);

  cfg->ef_dbg_mode       = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE);
  cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS);
  cfg->ef_sboot_en       = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN);
}

/****************************************************************************
 * @brief  Efuse write security boot configuration
 *
 * @param  sign[1]: Sign configuration pointer
 * @param  aes[1]: AES configuration pointer
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) {
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]);

  if (aes[0] != EF_CTRL_SF_AES_NONE) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1);
  }

  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse write security boot configuration
 *
 * @param  sign[1]: Sign configuration pointer
 * @param  aes[1]: AES configuration pointer
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);

  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE);
  sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01);

  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN);

  if (tmpVal2) {
    aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE);
  } else {
    aes[0] = EF_CTRL_SF_AES_NONE;
  }
}

/****************************************************************************
 * @brief  Analog Trim parity calculate
 *
 * @param  val: Value of efuse trim data
 * @param  len: Length of bit to calculate
 *
 * @return Parity bit value
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) {
  uint8_t cnt = 0;
  uint8_t i   = 0;

  for (i = 0; i < len; i++) {
    if (val & (1 << i)) {
      cnt++;
    }
  }

  return cnt & 0x01;
}
#endif

/****************************************************************************
 * @brief  Efuse write analog trim
 *
 * @param  index: index of analog trim
 * @param  trim: trim value
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) {
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (index == 0) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim);
  }

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read analog trim
 *
 * @param  index: index of analog trim
 * @param  trim: trim value
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) {
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  if (index == 0) {
    *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
  }
}

/****************************************************************************
 * @brief  Efuse read RC32M trim
 *
 * @param  trim: Trim data pointer
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) {
  uint32_t tmpVal = 0;
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal                         = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
  trim->trimRc32mCodeFrExt       = (tmpVal >> 10) & 0xff;
  trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01;
  trim->trimRc32mExtCodeEn       = (tmpVal >> 19) & 0x01;
}
#endif

/****************************************************************************
 * @brief  Efuse read RC32K trim
 *
 * @param  trim: Trim data pointer
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) {
  uint32_t tmpVal = 0;
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal                         = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0);
  trim->trimRc32kCodeFrExt       = (tmpVal >> 20) & 0x3ff;
  trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01;
  trim->trimRc32kExtCodeEn       = (tmpVal >> 31) & 0x01;
}
#endif

/****************************************************************************
 * @brief  Efuse read TSEN trim
 *
 * @param  trim: Trim data pointer
 *
 * @return None
 *
 *******************************************************************************/
void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) {
  uint32_t tmpVal = 0;
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal                    = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
  trim->tsenRefcodeCornerEn = tmpVal & 0x01;

  tmpVal                        = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
  trim->tsenRefcodeCorner       = tmpVal & 0xfff;
  trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01;

  trim->tsenRefcodeCornerVersion = 0;
}

/****************************************************************************
 * @brief  Efuse read ADC Gain trim
 *
 * @param  trim: Trim data pointer
 *
 * @return None
 *
 *******************************************************************************/
void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) {
  uint32_t tmpVal = 0;
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal                   = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
  trim->adcGainCoeff       = (tmpVal >> 1) & 0xfff;
  trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01;
  trim->adcGainCoeffEn     = (tmpVal >> 14) & 0x01;
}

/****************************************************************************
 * @brief  Efuse write software usage
 *
 * @param  index: index of software usage
 * @param  usage: usage value
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) {
  /* switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (index == 0) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage);
  }

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read software usage
 *
 * @param  index: index of software usage
 * @param  usage: usage value
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) {
  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  EF_CTRL_LOAD_BEFORE_READ_R0;

  if (index == 0) {
    *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0);
  }
}

/****************************************************************************
 * @brief  Efuse read software usage
 *
 * @param  index: index of software usage
 * @param  program: usage value
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) {
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);

  if (index == 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0);
  }

  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse write MAC address
 *
 * @param  mac[6]: MAC address buffer
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) {
  uint8_t *maclow  = (uint8_t *)mac;
  uint8_t *machigh = (uint8_t *)(mac + 4);
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  /* The low 32 bits */
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));
  /* The high 16 bits */
  tmpVal = machigh[0] + (machigh[1] << 8);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse Ctrl get zero bit count
 *
 * @param  val: Value to count
 *
 * @return Zero bit count
 *
 *******************************************************************************/
static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) {
  uint32_t cnt = 0;
  uint32_t i   = 0;

  for (i = 0; i < 8; i++) {
    if ((val & (1 << i)) == 0) {
      cnt += 1;
    }
  }

  return cnt;
}

/****************************************************************************
 * @brief  Efuse read MAC address
 *
 * @param  mac[8]: MAC address buffer
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]) {
  uint8_t *maclow  = (uint8_t *)mac;
  uint8_t *machigh = (uint8_t *)(mac + 4);
  uint32_t tmpVal;
  uint32_t i   = 0;
  uint32_t cnt = 0;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
  BL_WRWD_TO_BYTEP(maclow, tmpVal);

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
  BL_WRWD_TO_BYTEP(machigh, tmpVal);

  /* Get original parity */
  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);

  /* Check parity */
  for (i = 0; i < 8; i++) {
    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
  }

  if ((cnt & 0x3f) == (tmpVal & 0x3f)) {
    return SUCCESS;
  } else {
    return ERROR;
  }
}

/****************************************************************************
 * @brief  Efuse read MAC address
 *
 * @param  mac[7]: MAC address buffer
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) {
  uint8_t *maclow  = (uint8_t *)mac;
  uint8_t *machigh = (uint8_t *)(mac + 4);
  uint32_t tmpVal;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
  BL_WRWD_TO_BYTEP(maclow, tmpVal);

  tmpVal     = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
  machigh[0] = tmpVal & 0xff;
  machigh[1] = (tmpVal >> 8) & 0xff;
  machigh[2] = (tmpVal >> 16) & 0xff;

  return SUCCESS;
}

/****************************************************************************
 * @brief  Efuse lock writing for MAC address
 *
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Writelock_MAC_Address(uint8_t program) {
  uint32_t tmpVal;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC);
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Whether a value bits is all zero
 *
 * @param  val: value to check
 * @param  start: start bit
 * @param  len: total length of bits to check
 *
 * @return 1 for all bits zero 0 for others
 *
 *******************************************************************************/
uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) {
  uint32_t mask = 0;

  val = (val >> start);

  if (len >= 32) {
    mask = 0xffffffff;
  } else {
    mask = (1 << len) - 1;
  }

  if ((val & mask) == 0) {
    return 1;
  } else {
    return 0;
  }
}

/****************************************************************************
 * @brief  Whether MAC address slot is empty
 *
 * @param  slot: MAC address slot
 * @param  reload: whether  reload to check
 *
 * @return 0 for all slots full,1 for others
 *
 *******************************************************************************/
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) {
  uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
  uint32_t part1Empty = 0, part2Empty = 0;

  if (slot == 0) {
    /* Switch to AHB clock */
    EF_Ctrl_Sw_AHB_Clk_0();

    if (reload) {
      EF_CTRL_LOAD_BEFORE_READ_R0;
    }

    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
  } else if (slot == 1) {
    /* Switch to AHB clock */
    EF_Ctrl_Sw_AHB_Clk_0();

    if (reload) {
      EF_CTRL_LOAD_BEFORE_READ_R0;
    }

    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0);
    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1);
  } else if (slot == 2) {
    /* Switch to AHB clock */
    EF_Ctrl_Sw_AHB_Clk_0();

    if (reload) {
      EF_CTRL_LOAD_BEFORE_READ_R0;
    }

    tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
    tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
  }

  part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32));
  part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22));

  return (part1Empty && part2Empty);
}

/****************************************************************************
 * @brief  Efuse write optional MAC address
 *
 * @param  slot: MAC address slot
 * @param  mac[8]: MAC address buffer
 * @param  program: Whether program
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program) {
  uint8_t *maclow  = (uint8_t *)mac;
  uint8_t *machigh = (uint8_t *)(mac + 4);
  uint32_t tmpVal  = 0;
  uint32_t i       = 0;
  uint32_t cnt     = 0;

  if (slot >= 3) {
    return ERROR;
  }

  if (slot == 2) {
    /* Switch to AHB clock */
    EF_Ctrl_Sw_AHB_Clk_0();
  } else {
    /* Switch to AHB clock */
    EF_Ctrl_Sw_AHB_Clk_0();
  }

  /* The low 32 bits */
  if (slot == 0) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));
  } else if (slot == 1) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow));
  } else if (slot == 2) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow));
  }

  /* The high 32 bits */
  if (slot == 0) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, BL_RDWD_FRM_BYTEP(machigh));
  } else if (slot == 1) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, BL_RDWD_FRM_BYTEP(machigh));
  } else if (slot == 2) {
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, BL_RDWD_FRM_BYTEP(machigh));
  }

  cnt = 0;
  for (i = 0; i < 8; i++) {
    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
  }
  cnt &= 0x3f;
  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
  if (slot == 0) {
    tmpVal |= (cnt << 0);
  } else if (slot == 1) {
    tmpVal |= (cnt << 6);
  } else if (slot == 2) {
    tmpVal |= (cnt << 12);
  }
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmpVal);

  if (program) {
    if (slot == 2) {
      EF_Ctrl_Program_Efuse_0();
    } else {
      EF_Ctrl_Program_Efuse_0();
    }
  }
  return SUCCESS;
}

/****************************************************************************
 * @brief  Efuse read optional MAC address
 *
 * @param  slot: MAC address slot
 * @param  mac[8]: MAC address buffer
 * @param  reload: Whether reload
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload) {
  uint8_t *maclow  = (uint8_t *)mac;
  uint8_t *machigh = (uint8_t *)(mac + 4);
  uint32_t tmpVal  = 0;
  uint32_t i       = 0;
  uint32_t cnt     = 0;
  uint32_t crc     = 0;

  if (slot >= 3) {
    return ERROR;
  }

  /* Trigger read data from efuse */
  if (reload) {
    if (slot == 2) {
      EF_CTRL_LOAD_BEFORE_READ_R0;
    } else {
      EF_CTRL_LOAD_BEFORE_READ_R0;
    }
  }

  if (slot == 0) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
  } else if (slot == 1) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0);
  } else if (slot == 2) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW);
  }
  BL_WRWD_TO_BYTEP(maclow, tmpVal);

  if (slot == 0) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
  } else if (slot == 1) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1);
  } else if (slot == 2) {
    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH);
  }
  BL_WRWD_TO_BYTEP(machigh, tmpVal);

  /* Get original parity */
  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
  if (slot == 0) {
    crc = ((tmpVal >> 0) & 0x3f);
  } else if (slot == 1) {
    crc = ((tmpVal >> 6) & 0x3f);
  } else if (slot == 2) {
    crc = ((tmpVal >> 12) & 0x3f);
  }

  /* Check parity */
  for (i = 0; i < 8; i++) {
    cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]);
  }
  if ((cnt & 0x3f) == crc) {
    return SUCCESS;
  } else {
    return ERROR;
  }
}

/****************************************************************************
 * @brief  Efuse read chip ID
 *
 * @param  chipID[8]: Chip ID buffer
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) { return EF_Ctrl_Read_MAC_Address(chipID); }

/****************************************************************************
 * @brief  Efuse get chip PID&&VID
 *
 * @param  pid[1]: Chip PID
 * @param  vid[1]: Chip VID
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]) {
  uint32_t tmpVal;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3);
  pid[0] = (uint16_t)(tmpVal & 0xFFFF);
  vid[0] = (uint16_t)(tmpVal >> 16);

  return SUCCESS;
}

uint32_t EF_Ctrl_Get_Key_Slot_w0() {

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  return BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W0);
}
uint32_t EF_Ctrl_Get_Key_Slot_w1() {

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  return BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W1);
}

/****************************************************************************
 * @brief  Efuse get customer PID&&VID
 *
 * @param  pid[1]: Customer PID
 * @param  vid[1]: Customer VID
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) {
  uint32_t tmpVal;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W2);
  pid[0] = (uint16_t)(tmpVal & 0xFFFF);
  vid[0] = (uint16_t)(tmpVal >> 16);

  return SUCCESS;
}

/****************************************************************************
 * @brief  Efuse read device info
 *
 * @param  deviceInfo: Device info pointer
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) {
  uint32_t  tmpVal;
  uint32_t *p = (uint32_t *)deviceInfo;

  /* Trigger read data from efuse */
  EF_CTRL_LOAD_BEFORE_READ_R0;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2);
  *p     = tmpVal;
}

/****************************************************************************
 * @brief  Whether Capcode is empty
 *
 * @param  slot: Cap code slot
 * @param  reload: Whether reload
 *
 * @return 0 for all slots full,1 for others
 *
 *******************************************************************************/
uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload) {
  uint32_t tmp = 0xffffffff;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (reload) {
    EF_CTRL_LOAD_BEFORE_READ_R0;
  }

  if (slot == 0) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
  } else if (slot == 1) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 9, 7));
  } else if (slot == 2) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7));
  } else {
    return 0;
  }
}

/****************************************************************************
 * @brief  Efuse write Cap code
 *
 * @param  slot: Cap code slot
 * @param  code: Cap code value
 * @param  program: Whether program
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program) {
  uint32_t tmp;
  uint8_t  trim;

  if (slot >= 3) {
    return ERROR;
  }

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();
  EF_CTRL_LOAD_BEFORE_READ_R0;

  trim = (code << 1);
  trim |= (1 << 0);

  if (slot == 0) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp | (trim << 25));
  } else if (slot == 1) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 9));
  } else if (slot == 2) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 25));
  }

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
  while (SET == EF_Ctrl_Busy())
    ;

  return SUCCESS;
}

/****************************************************************************
 * @brief  Efuse read Cap code
 *
 * @param  slot: Cap code slot
 * @param  code: Cap code pointer
 * @param  reload: Whether reload
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload) {
  uint32_t tmp;
  uint8_t  trim = 0;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (reload) {
    EF_CTRL_LOAD_BEFORE_READ_R0;
  }

  if (slot == 0) {
    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    trim = (tmp >> 25) & 0x7f;
  } else if (slot == 1) {
    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    trim = (tmp >> 9) & 0x7f;
  } else if (slot == 2) {
    tmp  = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    trim = (tmp >> 25) & 0x7f;
  }

  if (trim & 0x01) {
    *code = trim >> 1;
    return SUCCESS;
  }
  return ERROR;
}

/****************************************************************************
 * @brief  Whether power offset slot is empty
 *
 * @param  slot: Power offset code slot
 * @param  reload: Whether reload
 *
 * @return 0 for all slots full,1 for others
 *
 *******************************************************************************/
uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) {
  uint32_t tmp1       = 0xffffffff;
  uint32_t part1Empty = 0, part2Empty = 0;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (reload) {
    EF_CTRL_LOAD_BEFORE_READ_R0;
  }

  if (slot == 0) {
    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
    part2Empty = 1;
  } else if (slot == 1) {
    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 9));
    part2Empty = 1;
  } else if (slot == 2) {
    tmp1       = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9));
    part2Empty = 1;
  }

  return (part1Empty && part2Empty);
}

/****************************************************************************
 * @brief  Efuse write power offset
 *
 * @param  slot: Power offset slot
 * @param  pwrOffset[2]: Power offset value array
 * @param  program: Whether program
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program) {
  uint32_t tmp   = 0;
  uint32_t k     = 0;
  uint32_t Value = 0;

  if (slot >= 3) {
    return ERROR;
  }

  for (k = 0; k < 2; k++) {
    /* Use 4 bits as signed value */
    if (pwrOffset[k] > 7) {
      pwrOffset[k] = 7;
    }
    if (pwrOffset[k] < -8) {
      pwrOffset[k] = -8;
    }
    Value += (uint32_t)(pwrOffset[k] & 0x0f) << (k * 4);
  }

  if (slot == 0) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    tmp |= (Value << 17);
    tmp |= (1 << 16);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp);
  } else if (slot == 1) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    tmp |= (Value << 1);
    tmp |= (1 << 0);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
  } else if (slot == 2) {
    tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    tmp |= (Value << 17);
    tmp |= (1 << 16);
    BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp);
  }

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }

  while (SET == EF_Ctrl_Busy())
    ;

  return SUCCESS;
}

/****************************************************************************
 * @brief  Efuse read poweroffset value
 *
 * @param  slot: Power offset slot
 * @param  pwrOffset[2]: Power offset array
 * @param  reload: Whether reload
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload) {
  uint32_t pwrOffsetValue = 0;
  uint32_t tmp            = 0, k;
  uint8_t  en             = 0;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  if (reload) {
    EF_CTRL_LOAD_BEFORE_READ_R0;
  }

  if (slot == 0) {
    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3);
    en             = (tmp >> 16) & 0x01;
    pwrOffsetValue = (tmp >> 17) & 0xff;
  } else if (slot == 1) {
    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    en             = (tmp >> 0) & 0x01;
    pwrOffsetValue = (tmp >> 1) & 0xff;
  } else if (slot == 2) {
    tmp            = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3);
    en             = (tmp >> 16) & 0x01;
    pwrOffsetValue = (tmp >> 17) & 0xff;
  }

  if (en) {
    for (k = 0; k < 2; k++) {
      tmp = (pwrOffsetValue >> (k * 4)) & 0x0f;
      if (tmp >= 8) {
        pwrOffset[k] = tmp - 16;
      } else {
        pwrOffset[k] = tmp;
      }
    }
    return SUCCESS;
  }
  return ERROR;
}

/****************************************************************************
 * @brief  Efuse write AES key
 *
 * @param  index: index of key slot
 * @param  keyData: key data buffer
 * @param  len: key data length in words
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) {
  uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);

  if (index > 5) {
    return;
  }

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  /* Every key is 4 words len*/
  BL702_MemCpy4(pAESKeyStart0 + index * 4, keyData, len);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse read AES key from specified region and index
 *
 * @param  index: index of key slot
 * @param  keyData: key data buffer
 * @param  len: key data length in words
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) {
  uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C);

  if (index > 5) {
    return;
  }

  /* Trigger read data from efuse*/
  EF_CTRL_LOAD_BEFORE_READ_R0;

  /* Every key is 4 words len*/
  BL702_MemCpy4(keyData, pAESKeyStart0 + index * 4, len);
}

/****************************************************************************
 * @brief  Efuse lock writing for aes key
 *
 * @param  index: index of key slot
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) {
  uint32_t tmpVal;

  if (index > 5) {
    return;
  }

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);

  if (index <= 3) {
    tmpVal |= (1 << (index + 19));
  } else {
    tmpVal |= (1 << (index + 19));
    tmpVal |= (1 << (index - 4 + 13));
  }

  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Efuse lock reading for aes key
 *
 * @param  index: index of key slot
 * @param  program: program to efuse entity or not
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) {
  uint32_t tmpVal;

  if (index > 5) {
    return;
  }

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK);
  tmpVal |= (1 << (index + 26));
  BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal);

  if (program) {
    EF_Ctrl_Program_Efuse_0();
  }
}

/****************************************************************************
 * @brief  Program data to efuse region 0
 *
 * @param  index: index of efuse in word
 * @param  data: data buffer
 * @param  len: data length
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) {
  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  /* Add delay for CLK to be stable */
  BL702_Delay_US(4);

  BL702_MemCpy4(pEfuseStart0 + index, data, len);

  EF_Ctrl_Program_Efuse_0();
}

/****************************************************************************
 * @brief  Read data from efuse region 0
 *
 * @param  index: index of efuse in word
 * @param  data: data buffer
 * @param  len: data length
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) {
  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);

  EF_CTRL_LOAD_BEFORE_READ_R0;

  BL702_MemCpy4(data, pEfuseStart0 + index, len);
}

/****************************************************************************
 * @brief  Clear efuse data register
 *
 * @param  index: index of efuse in word
 * @param  len: data length
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) {
  uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00);
  uint32_t  i            = 0;

  /* Switch to AHB clock */
  EF_Ctrl_Sw_AHB_Clk_0();

  /* Clear data */
  for (i = 0; i < len; i++) {
    pEfuseStart0[index + i] = 0;
  }
}
#endif

/****************************************************************************
 * @brief  efuse ctrl crc enable
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Crc_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET);
  BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN);
  BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal);
}

/****************************************************************************
 * @brief  efuse ctrl get crc busy status
 *
 * @param  None
 *
 * @return DISABLE or ENABLE
 *
 *******************************************************************************/
BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
  return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY);
}

/****************************************************************************
 * @brief  efuse ctrl set golden value
 *
 * @param  goldenValue: Crc golden value
 *
 * @return None
 *
 *******************************************************************************/
void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) { BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); }

/****************************************************************************
 * @brief  efuse ctrl get crc result
 *
 * @param  None
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type EF_Ctrl_Crc_Result(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0);
  return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR);
}

/*@} end of group SEC_EF_CTRL_Public_Functions */

/*@} end of group SEC_EF_CTRL */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_emac.c
================================================
/**
 ******************************************************************************
 * @file    bl702_emac.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_emac.h"
#include "bl702.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  EMAC
 *  @{
 */

/** @defgroup  EMAC_Private_Macros
 *  @{
 */
#define PHY_MAX_RETRY (0x3F0)

/*@} end of group EMAC_Private_Macros */

/** @defgroup  EMAC_Private_Types
 *  @{
 */

/*@} end of group EMAC_Private_Types */

/** @defgroup  EMAC_Private_Variables
 *  @{
 */
static intCallback_Type *emacIntCbfArra[EMAC_INT_CNT] = {NULL};

/*@} end of group EMAC_Private_Variables */

/** @defgroup  EMAC_Global_Variables
 *  @{
 */

/*@} end of group EMAC_Global_Variables */

/** @defgroup  EMAC_Private_Fun_Declaration
 *  @{
 */

/*@} end of group EMAC_Private_Fun_Declaration */

/** @defgroup  EMAC_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Set MAC Address
                                                                                *
                                                                                * @param  macAddr[6]: MAC address buffer array
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void EMAC_SetMACAddress(uint8_t macAddr[6]) {
  BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]);
  BL_WR_REG(EMAC_BASE, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0));
}

/****************************************************************************/ /**
                                                                                * @brief  Set PHY Address
                                                                                *
                                                                                * @param  phyAddress: Phy address
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void EMAC_Phy_SetAddress(uint16_t phyAddress) {
  uint32_t tmpVal;

  /* Set Phy Address */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress);
  BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Set PHY Address
                                                                                *
                                                                                * @param  phyAddress: Phy address
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex) {
  uint32_t tmpVal;

  /* Set MAC duplex config */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Read PHY register
                                                                                *
                                                                                * @param  phyReg: PHY register
                                                                                * @param  regValue: PHY register value pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Phy_Read(uint16_t phyReg, uint16_t *regValue) {
  uint32_t tmpVal;

  /* Set Register Address */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);
  BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);

  /* Trigger read */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND);
  tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT);
  BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal);

  BL_DRV_DUMMY;

  do {
    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS);
    BL702_Delay_US(16);
  } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));

  *regValue = BL_RD_REG(EMAC_BASE, EMAC_MIIRX_DATA);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Write PHY register
                                                                                *
                                                                                * @param  phyReg: PHY register
                                                                                * @param  regValue: PHY register value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue) {
  uint32_t tmpVal;

  /* Set Register Address */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIADDRESS);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg);
  BL_WR_REG(EMAC_BASE, EMAC_MIIADDRESS, tmpVal);

  /* Set Write data */
  BL_WR_REG(EMAC_BASE, EMAC_MIITX_DATA, regValue);

  /* Trigger write */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIICOMMAND);
  tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA);
  BL_WR_REG(EMAC_BASE, EMAC_MIICOMMAND, tmpVal);

  BL_DRV_DUMMY;

  do {
    tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIISTATUS);
  } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY));

  return SUCCESS;
}

/*@} end of group EMAC_Private_Functions */

/** @defgroup  EMAC_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Initialize EMAC module
                                                                                *
                                                                                * @param  cfg: EMAC configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Init(EMAC_CFG_Type *cfg) {
  uint32_t tmpVal;

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC);

  /* Set MAC config */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE);
  // tmpVal |= (1 << 7); /* local loopback in emac */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);

  /* Set inter frame gap value */
  BL_WR_REG(EMAC_BASE, EMAC_IPGT, cfg->interFrameGapValue);

  /* Set MII interface */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MIIMODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv);
  BL_WR_REG(EMAC_BASE, EMAC_MIIMODE, tmpVal);

  /* Set collision */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_COLLCONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid);
  BL_WR_REG(EMAC_BASE, EMAC_COLLCONFIG, tmpVal);

  /* Set frame length */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_PACKETLEN);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen);
  BL_WR_REG(EMAC_BASE, EMAC_PACKETLEN, tmpVal);

  EMAC_SetMACAddress(cfg->macAddr);

  void EMAC_IRQHandler(void);
  Interrupt_Handler_Register(EMAC_IRQn, EMAC_IRQHandler);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  DeInitialize EMAC module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_DeInit(void) {
  EMAC_Disable();

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Initialize EMAC TX RX MDA buffer
                                                                                *
                                                                                * @param  handle: EMAC handle pointer
                                                                                * @param  txBuff: TX buffer
                                                                                * @param  txBuffCount: TX buffer count
                                                                                * @param  rxBuff: RX buffer
                                                                                * @param  rxBuffCount: RX buffer count
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_DMADescListInit(EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount) {
  uint32_t i = 0;

  /* Set the Ethernet handler env */
  handle->bd          = (EMAC_BD_Desc_Type *)(EMAC_BASE + EMAC_DMA_DESC_OFFSET);
  handle->txIndexEMAC = 0;
  handle->txIndexCPU  = 0;
  handle->txBuffLimit = txBuffCount - 1;
  /* The receive descriptors' address starts right after the last transmit BD. */
  handle->rxIndexEMAC = txBuffCount;
  handle->rxIndexCPU  = txBuffCount;
  handle->rxBuffLimit = txBuffCount + rxBuffCount - 1;

  /* Fill each DMARxDesc descriptor with the right values */
  for (i = 0; i < txBuffCount; i++) {
    /* Get the pointer on the ith member of the Tx Desc list */
    handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(txBuff + (ETH_MAX_PACKET_SIZE * i));
    handle->bd[i].C_S_L  = 0;
  }

  /* For the last TX DMA Descriptor, it should be wrap back */
  handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR);

  for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) {
    /* Get the pointer on the ith member of the Rx Desc list */
    handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount)));
    handle->bd[i].C_S_L  = (ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_FIELD_MSK(RX_IRQ) | EMAC_BD_FIELD_MSK(RX_E);
  }

  /* For the last RX DMA Descriptor, it should be wrap back */
  handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR);

  /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/
  BL_WR_REG(EMAC_BASE, EMAC_TX_BD_NUM, txBuffCount);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get TX MDA buffer descripter for data to send
                                                                                *
                                                                                * @param  handle: EMAC handle pointer
                                                                                * @param  txDMADesc: TX DMA descriptor pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc) { return SUCCESS; }

/****************************************************************************/ /**
                                                                                * @brief  Start TX
                                                                                *
                                                                                * @param  handle: EMAC handle pointer
                                                                                * @param  txDMADesc: TX DMA descriptor pointer
                                                                                * @param  len: len
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len) { return SUCCESS; }

/****************************************************************************/ /**
                                                                                * @brief  Enable EMAC module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Enable(void) {
  uint32_t tmpVal;

  /* Enable EMAC */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);
  tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_Enable_TX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Enable_TX(void) {
  uint32_t tmpVal;

  /* Enable EMAC */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_Disable_TX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Disable_TX(void) {
  uint32_t tmpVal;

  /* Enable EMAC */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_Enable_RX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Enable_RX(void) {
  uint32_t tmpval;

  /* Enable EMAC TX*/
  tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_Disable_RX
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Disable_RX(void) {
  uint32_t tmpval;

  /* Disable EMAC RX*/
  tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable EMAC module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Disable(void) {
  uint32_t tmpVal;

  /* Enable EMAC */
  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_MODE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN);
  BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC mask or unmask certain or all interrupt
                                                                                *
                                                                                * @param  intType: EMAC interrupt type
                                                                                * @param  intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_IntMask(EMAC_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK);

  /* Mask or unmask certain or all interrupt */
  if (MASK == intMask) {
    tmpVal |= intType;
  } else {
    tmpVal &= (~intType);
  }

  /* Write back */
  BL_WR_REG(EMAC_BASE, EMAC_INT_MASK, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get EMAC interrupt status
                                                                                *
                                                                                * @param  intType: EMAC interrupt type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type EMAC_GetIntStatus(EMAC_INT_Type intType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_EMAC_INT_TYPE(intType));

  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE);

  return (tmpVal & intType) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear EMAC interrupt
                                                                                *
                                                                                * @param  intType: EMAC interrupt type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_ClrIntStatus(EMAC_INT_Type intType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_EMAC_INT_TYPE(intType));

  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_SOURCE);

  BL_WR_REG(EMAC_BASE, EMAC_INT_SOURCE, tmpVal | intType);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_Int_Callback_Install
                                                                                *
                                                                                * @param  intIdx: EMAC_INT_Index
                                                                                * @param  cbFun: call back
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_Int_Callback_Install(EMAC_INT_Index intIdx, intCallback_Type *cbFun) {
  /* Check the parameters */

  emacIntCbfArra[intIdx] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EMAC_IRQHandler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void EMAC_IRQHandler(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(EMAC_BASE, EMAC_INT_MASK);

  if (SET == EMAC_GetIntStatus(EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) {
    EMAC_ClrIntStatus(EMAC_INT_TX_DONE);

    if (emacIntCbfArra[EMAC_INT_TX_DONE_IDX]) {
      emacIntCbfArra[EMAC_INT_TX_DONE_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) {
    EMAC_ClrIntStatus(EMAC_INT_TX_ERROR);

    if (emacIntCbfArra[EMAC_INT_TX_ERROR_IDX]) {
      emacIntCbfArra[EMAC_INT_TX_ERROR_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) {
    EMAC_ClrIntStatus(EMAC_INT_RX_DONE);

    if (emacIntCbfArra[EMAC_INT_RX_DONE_IDX]) {
      emacIntCbfArra[EMAC_INT_RX_DONE_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) {
    EMAC_ClrIntStatus(EMAC_INT_RX_ERROR);

    if (emacIntCbfArra[EMAC_INT_RX_ERROR_IDX]) {
      emacIntCbfArra[EMAC_INT_RX_ERROR_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) {
    EMAC_ClrIntStatus(EMAC_INT_RX_BUSY);

    if (emacIntCbfArra[EMAC_INT_RX_BUSY_IDX]) {
      emacIntCbfArra[EMAC_INT_RX_BUSY_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) {
    EMAC_ClrIntStatus(EMAC_INT_TX_CTRL);

    if (emacIntCbfArra[EMAC_INT_TX_CTRL_IDX]) {
      emacIntCbfArra[EMAC_INT_TX_CTRL_IDX]();
    }
  }

  if (SET == EMAC_GetIntStatus(EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) {
    EMAC_ClrIntStatus(EMAC_INT_RX_CTRL);

    if (emacIntCbfArra[EMAC_INT_RX_CTRL_IDX]) {
      emacIntCbfArra[EMAC_INT_RX_CTRL_IDX]();
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Request to pause TX
                                                                                *
                                                                                * @param  timeCount: Pause time count
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_TxPauseReq(uint16_t timeCount) {
  BL_WR_REG(EMAC_BASE, EMAC_TXCTRL, (1 << 16) | timeCount);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set hash value
                                                                                *
                                                                                * @param  hash0: Hash value one
                                                                                * @param  hash1: Hash value two
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type EMAC_SetHash(uint32_t hash0, uint32_t hash1) {
  BL_WR_REG(EMAC_BASE, EMAC_HASH0_ADDR, hash0);

  BL_WR_REG(EMAC_BASE, EMAC_HASH1_ADDR, hash1);

  return SUCCESS;
}

/*@} end of group EMAC_Public_Functions */

/*@} end of group EMAC */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_glb.c
================================================
/**
 ******************************************************************************
 * @file    bl702_glb.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_glb.h"
#include "bl702_hbn.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  GLB
 *  @{
 */

/** @defgroup  GLB_Private_Macros
 *  @{
 */
#define GLB_CLK_SET_DUMMY_WAIT                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
  }
#define GLB_GPIO_Get_Reg(pin)       (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4)
#define GLB_GPIO_INT0_NUM           (32)
#define GLB_REG_BCLK_DIS_TRUE       (*(volatile uint32_t *)(0x40000FFC) = (0x00000001))
#define GLB_REG_BCLK_DIS_FALSE      (*(volatile uint32_t *)(0x40000FFC) = (0x00000000))
#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)

/*@} end of group GLB_Private_Macros */

/** @defgroup  GLB_Private_Types
 *  @{
 */

/*@} end of group GLB_Private_Types */

/** @defgroup  GLB_Private_Variables
 *  @{
 */
static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL]   = {NULL};
static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL]     = {NULL};
static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM]  = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};
static intCallback_Type *glbGpioInt0CbfArra2[GLB_GPIO_INT0_NUM] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};

/*@} end of group GLB_Private_Variables */

/** @defgroup  GLB_Global_Variables
 *  @{
 */

/*@} end of group GLB_Global_Variables */

/** @defgroup  GLB_Private_Fun_Declaration
 *  @{
 */

/*@} end of group GLB_Private_Fun_Declaration */

/** @defgroup  GLB_Private_Functions
 *  @{
 */

/*@} end of group GLB_Private_Functions */

/** @defgroup  GLB_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  get root clock selection
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return root clock selection
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);

  switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) {
  case 0:
    return GLB_ROOT_CLK_RC32M;
  case 1:
    return GLB_ROOT_CLK_XTAL;
  case 2:
  case 3:
    return GLB_ROOT_CLK_DLL;
  default:
    return GLB_ROOT_CLK_RC32M;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set System clock divider
                                                                                *
                                                                                * @param  hclkDiv: HCLK divider
                                                                                * @param  bclkDiv: BCLK divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) {
  /***********************************************************************************/
  /*                                 NOTE                                            */
  /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
  /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
  /***********************************************************************************/
  uint32_t tmpVal;

  /* recommend: fclk<=160MHz, bclk<=80MHz */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  GLB_REG_BCLK_DIS_TRUE;
  GLB_REG_BCLK_DIS_FALSE;
  // SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1));
  GLB_CLK_SET_DUMMY_WAIT;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  GLB_CLK_SET_DUMMY_WAIT;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get Bus clock divider
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Clock Divider
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);

  return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get CPU clock divider
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Clock Divider
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);

  return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  update SystemCoreClock value
                                                                                *
                                                                                * @param  xtalType: XTAL frequency type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType) {
  CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));

  switch (xtalType) {
  case GLB_DLL_XTAL_NONE:
    break;
  case GLB_DLL_XTAL_32M:
    SystemCoreClockSet(32000000);
    break;
  case GLB_DLL_XTAL_RC32M:
    SystemCoreClockSet(32000000);
    break;
  default:
    break;
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set System clock
                                                                                *
                                                                                * @param  xtalType: XTAL frequency type
                                                                                * @param  clkFreq: clock frequency selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
  CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq));

  /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);

  /* Before config XTAL and DLL ,make sure root clk is from RC32M */
  HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
  GLB_Set_System_CLK_Div(0, 0);
  SystemCoreClockSet(32 * 1000 * 1000);

  if (xtalType == GLB_DLL_XTAL_NONE) {
    if (clkFreq == GLB_SYS_CLK_RC32M) {
      return SUCCESS;
    } else {
      return ERROR;
    }
  }

  if (xtalType != GLB_DLL_XTAL_RC32M) {
    /* power on xtal first */
    AON_Power_On_XTAL();
  }

  /* Bl702 make PLL Setting out of RF, so following setting can be removed*/
  // AON_Power_On_MBG();
  // AON_Power_On_LDO15_RF();

  /* always power up PLL and enable all PLL clock output */
  // PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType);
  // BL702_Delay_US(55);
  // PDS_Enable_PLL_All_Clks();

  /* always power up DLL and enable all DLL clock output */
  GLB_Power_Off_DLL();
  GLB_Power_On_DLL(xtalType);
  GLB_Enable_DLL_All_Clks();

  /* reg_pll_en = 1, cannot be zero */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);

  /* select pll output clock before select root clock */
  if (clkFreq >= GLB_SYS_CLK_DLL57P6M) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_DLL57P6M);
    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  }
  /* select root clock */
  switch (clkFreq) {
  case GLB_SYS_CLK_RC32M:
    break;
  case GLB_SYS_CLK_XTAL:
    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL);
    Update_SystemCoreClockWith_XTAL(xtalType);
    break;
  case GLB_SYS_CLK_DLL57P6M:
    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
    SystemCoreClockSet(57 * 6000 * 1000);
    break;
  case GLB_SYS_CLK_DLL96M:
    L1C_IROM_2T_Access_Set(ENABLE);
    GLB_Set_System_CLK_Div(0, 1);
    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
    SystemCoreClockSet(96 * 1000 * 1000);
    break;
  case GLB_SYS_CLK_DLL144M:
    L1C_IROM_2T_Access_Set(ENABLE);
    GLB_Set_System_CLK_Div(0, 1);
    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
    SystemCoreClockSet(144 * 1000 * 1000);
    break;
  default:
    break;
  }

  GLB_CLK_SET_DUMMY_WAIT;

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  This is demo for user that use RC32M as default bootup clock instead of DLL,when APP is
                                                                                *         started, this function can be called to set DLL to 160M
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) {
  SF_Ctrl_Cfg_Type sfCtrlCfg = {
      .owner       = SF_CTRL_OWNER_IAHB,
      .clkDelay    = 1,
      .clkInvert   = 1,
      .rxClkInvert = 1,
      .doDelay     = 0,
      .diDelay     = 0,
      .oeDelay     = 0,
  };
  /* Use RC32M as DLL ref source to set up DLL to 144M */
  GLB_Set_System_CLK(GLB_DLL_XTAL_RC32M, GLB_SYS_CLK_DLL144M);
  /* Flash controller also need changes since system (bus) clock changed */
  SF_Ctrl_Enable(&sfCtrlCfg);
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  set CAM clock
                                                                                *
                                                                                * @param  enable: Enable or disable CAM clock
                                                                                * @param  clkSel: CAM clock type
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set mac154 and zigbee clock
                                                                                *
                                                                                * @param  enable: Enable or disable mac154 and zigbee clock
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_M154_ZBEN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_M154_ZBEN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set BLE clock
                                                                                *
                                                                                * @param  enable: Enable or disable BLE clock
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set I2S clock
                                                                                *
                                                                                * @param  enable: Enable or disable I2S clock
                                                                                * @param  outRef: I2S output ref clock type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_I2S_OUT_REF_CLK_TYPE(outRef));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_0_REF_CLK_OE, outRef);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set USB clock
                                                                                *
                                                                                * @param  enable: Enable or disable USB clock
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_USB_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_48M_DIV_EN, 1);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USB_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USB_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set QDEC clock
                                                                                *
                                                                                * @param  clkSel: QDEC clock type
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_QDEC_CLK_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL, clkSel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set DMA clock
                                                                                *
                                                                                * @param  enable: Enable or disable DMA clock
                                                                                * @param  clk: DMA ID type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  tmpVal  = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
  if (enable) {
    tmpVal2 |= (1 << clk);
  } else {
    tmpVal2 &= (~(1 << clk));
  }
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set IR clock divider
                                                                                *
                                                                                * @param  enable: enable or disable IR clock
                                                                                * @param  clkSel: IR clock type
                                                                                * @param  div: divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
  CHECK_PARAM((div <= 0x3F));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set sflash clock
                                                                                *
                                                                                * @param  enable: Enable or disable sflash clock
                                                                                * @param  clkSel: sflash clock type
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) {
  uint32_t         tmpVal = 0;
  GLB_DLL_CLK_Type clk;

  CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
  CHECK_PARAM((div <= 0x7));

  /* disable SFLASH clock first */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  /* Select flash clock, all Flash CLKs are divied by DLL_288M */
  clk = GLB_DLL_CLK_288M;
  GLB_Enable_DLL_Clk(clk);
  /* clock divider */
  /* Select flash clock, all Flash CLKs are divied by DLL_288M */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
  switch (clkSel) {
  case GLB_SFLASH_CLK_144M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
    break;
  case GLB_SFLASH_CLK_XCLK:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
    break;
  case GLB_SFLASH_CLK_57P6M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
    break;
  case GLB_SFLASH_CLK_72M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
    break;
  case GLB_SFLASH_CLK_BCLK:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
    break;
  case GLB_SFLASH_CLK_96M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
    break;
  default:
    break;
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  /* enable or disable flash clock */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  set UART clock
                                                                                *
                                                                                * @param  enable: Enable or disable UART clock
                                                                                * @param  clkSel: UART clock type
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((div <= 0x7));
  CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));

  /* disable UART clock first */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  /* Set div */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  /* Select clock source for uart */
  HBN_Set_UART_CLK_Sel(clkSel);

  /* Set enable or disable */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select chip clock out 0 type
                                                                                *
                                                                                * @param  clkSel: chip clock out type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkSel);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select chip clock out 1 type
                                                                                *
                                                                                * @param  clkSel: chip clock out type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkSel);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set I2C clock
                                                                                *
                                                                                * @param  enable: Enable or disable I2C clock
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  invert eth rx clock
                                                                                *
                                                                                * @param  enable: invert or not invert
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  invert rf test clock out
                                                                                *
                                                                                * @param  enable: invert or not invert
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set SPI clock
                                                                                *
                                                                                * @param  enable: Enable or disable SPI clock
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((div <= 0x1F));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  invert eth tx clock
                                                                                *
                                                                                * @param  enable: invert or not invert
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  invert eth ref clock out
                                                                                *
                                                                                * @param  enable: invert or not invert
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
  }
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select eth ref clock out
                                                                                *
                                                                                * @param  clkSel: eth ref clock type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select PKA clock source
                                                                                *
                                                                                * @param  clkSel: PKA clock selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Software system reset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) {
  /***********************************************************************************/
  /*                                 NOTE                                            */
  /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
  /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
  /***********************************************************************************/
  uint32_t tmpVal;

  /* Swicth clock to 32M as default */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  GLB_CLK_SET_DUMMY_WAIT;

  /* HCLK is RC32M , so BCLK/HCLK no need divider */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  GLB_REG_BCLK_DIS_TRUE;
  GLB_REG_BCLK_DIS_FALSE;
  GLB_CLK_SET_DUMMY_WAIT;

  /* Do reset */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  /* waiting for reset */
  while (1) {
    BL702_Delay_US(10);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Software CPU reset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) {
  /***********************************************************************************/
  /*                                 NOTE                                            */
  /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
  /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
  /***********************************************************************************/
  uint32_t tmpVal;

  /* Swicth clock to 32M as default */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  GLB_CLK_SET_DUMMY_WAIT;

  /* HCLK is RC32M , so BCLK/HCLK no need divider */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  GLB_REG_BCLK_DIS_TRUE;
  GLB_REG_BCLK_DIS_FALSE;
  GLB_CLK_SET_DUMMY_WAIT;

  /* Do reset */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  /* waiting for reset */
  while (1) {
    BL702_Delay_US(10);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Software power on reset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) {
  /***********************************************************************************/
  /*                                 NOTE                                            */
  /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
  /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
  /***********************************************************************************/
  uint32_t tmpVal;

  /* Swicth clock to 32M as default */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  GLB_CLK_SET_DUMMY_WAIT;

  /* HCLK is RC32M , so BCLK/HCLK no need divider */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
  BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
  GLB_REG_BCLK_DIS_TRUE;
  GLB_REG_BCLK_DIS_FALSE;
  GLB_CLK_SET_DUMMY_WAIT;

  /* Do reset */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);

  /* waiting for reset */
  while (1) {
    BL702_Delay_US(10);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Reset slave 1
                                                                                *
                                                                                * @param  slave1: slave num
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
  tmpVal &= (~(1 << slave1));
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
  BL_DRV_DUMMY;
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
  tmpVal |= (1 << slave1);
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
  BL_DRV_DUMMY;
  tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
  tmpVal &= (~(1 << slave1));
  BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  clock gate
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                * @param  slave1: AHB slaveClk type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1) {
  /* gate QDEC <=> gate QDEC0 + QDEC1 +QDEC2 + I2S */
  /* gate I2S  <=> gate I2S + QDEC2                */

  uint32_t tmpVal = 0;

  if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) || (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) || (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) {
    /* not support */
    return ERROR;
  }

  /* gate QDEC and I2S */
  if (BL_AHB_SLAVE1_QDEC == slave1) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
    if (enable) {
      /* clear bit means clock gate */
      tmpVal &= (~(1 << 0x18));
      tmpVal &= (~(1 << 0x19));
      tmpVal &= (~(1 << 0x1A));
    } else {
      /* set bit means clock pass */
      tmpVal |= (1 << 0x18);
      tmpVal |= (1 << 0x19);
      tmpVal |= (1 << 0x1A);
    }
    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
    return SUCCESS;
  }

  /* gate KYS */
  if (BL_AHB_SLAVE1_KYS == slave1) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
    if (enable) {
      /* clear bit means clock gate */
      tmpVal &= (~(1 << 0x1B));
    } else {
      /* set bit means clock pass */
      tmpVal |= (1 << 0x1B);
    }
    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
    return SUCCESS;
  }

  /* gate I2S and QDEC2 */
  if (BL_AHB_SLAVE1_I2S == slave1) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
    if (enable) {
      /* clear bit means clock gate */
      tmpVal &= (~(1 << 0x1A));
    } else {
      /* set bit means clock pass */
      tmpVal |= (1 << 0x1A);
    }
    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
    return SUCCESS;
  }

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  if (enable) {
    /* clear bit means clock gate */
    tmpVal &= (~(1 << slave1));
  } else {
    /* set bit means clock pass */
    tmpVal |= (1 << slave1);
  }
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get IPs clock gate value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return clock gate value
                                                                                *
                                                                                *******************************************************************************/
uint64_t GLB_PER_Clock_Gate_Status_Get(void) {
  /* api request from cjy */

  uint32_t tmpValCfg0 = 0;
  uint32_t tmpValCfg1 = 0;
  uint32_t tmpValCfg2 = 0;
  uint32_t targetBit  = 0;
  uint64_t targetVal  = 0;

  tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
  tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
  for (uint8_t i = 0; i < 64; i++) {
    targetBit = 0;
    switch (i) {
    case GLB_AHB_CLOCK_IP_CPU:
      targetBit = tmpValCfg0 & (1 << 0);
      break;
    case GLB_AHB_CLOCK_IP_SDU:
      targetBit = tmpValCfg0 & (1 << 1);
      break;
    case GLB_AHB_CLOCK_IP_SEC:
      targetBit = (tmpValCfg0 & (1 << 2)) && (tmpValCfg1 & (1 << 3)) && (tmpValCfg1 & (1 << 4));
      break;
    case GLB_AHB_CLOCK_IP_DMA_0:
      targetBit = (tmpValCfg0 & (1 << 3)) && (tmpValCfg1 & (1 << 12));
      break;
    case GLB_AHB_CLOCK_IP_DMA_1:
      break;
    case GLB_AHB_CLOCK_IP_DMA_2:
      break;
    case GLB_AHB_CLOCK_IP_CCI:
      targetBit = tmpValCfg0 & (1 << 4);
      break;
    case GLB_AHB_CLOCK_IP_RF_TOP:
      break;
    case GLB_AHB_CLOCK_IP_GPIP:
      targetBit = tmpValCfg1 & (1 << 2);
      break;
    case GLB_AHB_CLOCK_IP_TZC:
      targetBit = tmpValCfg1 & (1 << 5);
      break;
    case GLB_AHB_CLOCK_IP_EF_CTRL:
      targetBit = tmpValCfg1 & (1 << 7);
      break;
    case GLB_AHB_CLOCK_IP_SF_CTRL:
      targetBit = tmpValCfg1 & (1 << 11);
      break;
    case GLB_AHB_CLOCK_IP_EMAC:
      targetBit = tmpValCfg1 & (1 << 13);
      break;
    case GLB_AHB_CLOCK_IP_UART0:
      targetBit = tmpValCfg1 & (1 << 16);
      break;
    case GLB_AHB_CLOCK_IP_UART1:
      targetBit = tmpValCfg1 & (1 << 17);
      break;
    case GLB_AHB_CLOCK_IP_UART2:
      break;
    case GLB_AHB_CLOCK_IP_UART3:
      break;
    case GLB_AHB_CLOCK_IP_UART4:
      break;
    case GLB_AHB_CLOCK_IP_SPI:
      targetBit = tmpValCfg1 & (1 << 18);
      break;
    case GLB_AHB_CLOCK_IP_I2C:
      targetBit = tmpValCfg1 & (1 << 19);
      break;
    case GLB_AHB_CLOCK_IP_PWM:
      targetBit = tmpValCfg1 & (1 << 20);
      break;
    case GLB_AHB_CLOCK_IP_TIMER:
      targetBit = tmpValCfg1 & (1 << 21);
      break;
    case GLB_AHB_CLOCK_IP_IR:
      targetBit = tmpValCfg1 & (1 << 22);
      break;
    case GLB_AHB_CLOCK_IP_CHECKSUM:
      targetBit = tmpValCfg1 & (1 << 23);
      break;
    case GLB_AHB_CLOCK_IP_QDEC:
      targetBit = (tmpValCfg1 & (1 << 24)) && (tmpValCfg1 & (1 << 25)) && (tmpValCfg1 & (1 << 26));
      break;
    case GLB_AHB_CLOCK_IP_KYS:
      targetBit = tmpValCfg1 & (1 << 27);
      break;
    case GLB_AHB_CLOCK_IP_I2S:
      targetBit = tmpValCfg1 & (1 << 26);
      break;
    case GLB_AHB_CLOCK_IP_USB11:
      targetBit = tmpValCfg1 & (1 << 28);
      break;
    case GLB_AHB_CLOCK_IP_CAM:
      targetBit = tmpValCfg1 & (1 << 29);
      break;
    case GLB_AHB_CLOCK_IP_MJPEG:
      targetBit = tmpValCfg1 & (1 << 30);
      break;
    case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
      targetBit = (tmpValCfg2 & (1 << 0)) && (tmpValCfg2 & (1 << 4));
      break;
    case GLB_AHB_CLOCK_IP_BT_BLE_LP:
      break;
    case GLB_AHB_CLOCK_IP_ZB_NORMAL:
      targetBit = tmpValCfg2 & (1 << 0);
      break;
    case GLB_AHB_CLOCK_IP_ZB_LP:
      break;
    case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
      break;
    case GLB_AHB_CLOCK_IP_WIFI_LP:
      break;
    case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
      break;
    case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
      break;
    case GLB_AHB_CLOCK_IP_EMI_MISC:
      break;
    case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
      break;
    case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
      break;
    case GLB_AHB_CLOCK_IP_USB20:
      break;
    case GLB_AHB_CLOCK_IP_MIX2:
      break;
    case GLB_AHB_CLOCK_IP_AUDIO:
      break;
    case GLB_AHB_CLOCK_IP_SDH:
      break;
    default:
      break;
    }
    if (!targetBit) {
      targetVal |= ((uint64_t)1 << i);
    }
  }

  return targetVal;
}

/****************************************************************************/ /**
                                                                                * @brief  get first 1 from u64, then clear it
                                                                                *
                                                                                * @param  val: target value
                                                                                * @param  bit: first 1 in bit
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit) {
  if (!*val) {
    return ERROR;
  }

  for (uint8_t i = 0; i < 64; i++) {
    if ((*val) & ((uint64_t)1 << i)) {
      *bit = i;
      (*val) &= ~((uint64_t)1 << i);
      break;
    }
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  hold IPs clock
                                                                                *
                                                                                * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) {
  /* api request from cjy */

  uint32_t tmpValCfg0 = 0;
  uint32_t tmpValCfg1 = 0;
  uint32_t tmpValCfg2 = 0;
  uint32_t bitfield   = 0;

  tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
  tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
  while (ips) {
    if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
      switch (bitfield) {
      case GLB_AHB_CLOCK_IP_CPU:
        tmpValCfg0 &= ~(1 << 0);
        break;
      case GLB_AHB_CLOCK_IP_SDU:
        tmpValCfg0 &= ~(1 << 1);
        break;
      case GLB_AHB_CLOCK_IP_SEC:
        tmpValCfg0 &= ~(1 << 2);
        tmpValCfg1 &= ~(1 << 3);
        tmpValCfg1 &= ~(1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_DMA_0:
        tmpValCfg0 &= ~(1 << 3);
        tmpValCfg1 &= ~(1 << 12);
        break;
      case GLB_AHB_CLOCK_IP_DMA_1:
        break;
      case GLB_AHB_CLOCK_IP_DMA_2:
        break;
      case GLB_AHB_CLOCK_IP_CCI:
        tmpValCfg0 &= ~(1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_RF_TOP:
        break;
      case GLB_AHB_CLOCK_IP_GPIP:
        tmpValCfg1 &= ~(1 << 2);
        break;
      case GLB_AHB_CLOCK_IP_TZC:
        tmpValCfg1 &= ~(1 << 5);
        break;
      case GLB_AHB_CLOCK_IP_EF_CTRL:
        tmpValCfg1 &= ~(1 << 7);
        break;
      case GLB_AHB_CLOCK_IP_SF_CTRL:
        tmpValCfg1 &= ~(1 << 11);
        break;
      case GLB_AHB_CLOCK_IP_EMAC:
        tmpValCfg1 &= ~(1 << 13);
        break;
      case GLB_AHB_CLOCK_IP_UART0:
        tmpValCfg1 &= ~(1 << 16);
        break;
      case GLB_AHB_CLOCK_IP_UART1:
        tmpValCfg1 &= ~(1 << 17);
        break;
      case GLB_AHB_CLOCK_IP_UART2:
        break;
      case GLB_AHB_CLOCK_IP_UART3:
        break;
      case GLB_AHB_CLOCK_IP_UART4:
        break;
      case GLB_AHB_CLOCK_IP_SPI:
        tmpValCfg1 &= ~(1 << 18);
        break;
      case GLB_AHB_CLOCK_IP_I2C:
        tmpValCfg1 &= ~(1 << 19);
        break;
      case GLB_AHB_CLOCK_IP_PWM:
        tmpValCfg1 &= ~(1 << 20);
        break;
      case GLB_AHB_CLOCK_IP_TIMER:
        tmpValCfg1 &= ~(1 << 21);
        break;
      case GLB_AHB_CLOCK_IP_IR:
        tmpValCfg1 &= ~(1 << 22);
        break;
      case GLB_AHB_CLOCK_IP_CHECKSUM:
        tmpValCfg1 &= ~(1 << 23);
        break;
      case GLB_AHB_CLOCK_IP_QDEC:
        tmpValCfg1 &= ~(1 << 24);
        tmpValCfg1 &= ~(1 << 25);
        tmpValCfg1 &= ~(1 << 26);
        break;
      case GLB_AHB_CLOCK_IP_KYS:
        tmpValCfg1 &= ~(1 << 27);
        break;
      case GLB_AHB_CLOCK_IP_I2S:
        tmpValCfg1 &= ~(1 << 26);
        break;
      case GLB_AHB_CLOCK_IP_USB11:
        tmpValCfg1 &= ~(1 << 28);
        break;
      case GLB_AHB_CLOCK_IP_CAM:
        tmpValCfg1 &= ~(1 << 29);
        break;
      case GLB_AHB_CLOCK_IP_MJPEG:
        tmpValCfg1 &= ~(1 << 30);
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
        tmpValCfg2 &= ~(1 << 0);
        tmpValCfg2 &= ~(1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_LP:
        break;
      case GLB_AHB_CLOCK_IP_ZB_NORMAL:
        tmpValCfg2 &= ~(1 << 0);
        break;
      case GLB_AHB_CLOCK_IP_ZB_LP:
        break;
      case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
        break;
      case GLB_AHB_CLOCK_IP_WIFI_LP:
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
        break;
      case GLB_AHB_CLOCK_IP_EMI_MISC:
        break;
      case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
        break;
      case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
        break;
      case GLB_AHB_CLOCK_IP_USB20:
        break;
      case GLB_AHB_CLOCK_IP_MIX2:
        break;
      case GLB_AHB_CLOCK_IP_AUDIO:
        break;
      case GLB_AHB_CLOCK_IP_SDH:
        break;
      default:
        break;
      }
    }
  }
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  release IPs clock
                                                                                *
                                                                                * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) {
  /* api request from cjy */

  uint32_t tmpValCfg0 = 0;
  uint32_t tmpValCfg1 = 0;
  uint32_t tmpValCfg2 = 0;
  uint32_t bitfield   = 0;

  tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
  tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
  tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
  while (ips) {
    if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
      switch (bitfield) {
      case GLB_AHB_CLOCK_IP_CPU:
        tmpValCfg0 |= (1 << 0);
        break;
      case GLB_AHB_CLOCK_IP_SDU:
        tmpValCfg0 |= (1 << 1);
        break;
      case GLB_AHB_CLOCK_IP_SEC:
        tmpValCfg0 |= (1 << 2);
        tmpValCfg1 |= (1 << 3);
        tmpValCfg1 |= (1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_DMA_0:
        tmpValCfg0 |= (1 << 3);
        tmpValCfg1 |= (1 << 12);
        break;
      case GLB_AHB_CLOCK_IP_DMA_1:
        break;
      case GLB_AHB_CLOCK_IP_DMA_2:
        break;
      case GLB_AHB_CLOCK_IP_CCI:
        tmpValCfg0 |= (1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_RF_TOP:
        break;
      case GLB_AHB_CLOCK_IP_GPIP:
        tmpValCfg1 |= (1 << 2);
        break;
      case GLB_AHB_CLOCK_IP_TZC:
        tmpValCfg1 |= (1 << 5);
        break;
      case GLB_AHB_CLOCK_IP_EF_CTRL:
        tmpValCfg1 |= (1 << 7);
        break;
      case GLB_AHB_CLOCK_IP_SF_CTRL:
        tmpValCfg1 |= (1 << 11);
        break;
      case GLB_AHB_CLOCK_IP_EMAC:
        tmpValCfg1 |= (1 << 13);
        break;
      case GLB_AHB_CLOCK_IP_UART0:
        tmpValCfg1 |= (1 << 16);
        break;
      case GLB_AHB_CLOCK_IP_UART1:
        tmpValCfg1 |= (1 << 17);
        break;
      case GLB_AHB_CLOCK_IP_UART2:
        break;
      case GLB_AHB_CLOCK_IP_UART3:
        break;
      case GLB_AHB_CLOCK_IP_UART4:
        break;
      case GLB_AHB_CLOCK_IP_SPI:
        tmpValCfg1 |= (1 << 18);
        break;
      case GLB_AHB_CLOCK_IP_I2C:
        tmpValCfg1 |= (1 << 19);
        break;
      case GLB_AHB_CLOCK_IP_PWM:
        tmpValCfg1 |= (1 << 20);
        break;
      case GLB_AHB_CLOCK_IP_TIMER:
        tmpValCfg1 |= (1 << 21);
        break;
      case GLB_AHB_CLOCK_IP_IR:
        tmpValCfg1 |= (1 << 22);
        break;
      case GLB_AHB_CLOCK_IP_CHECKSUM:
        tmpValCfg1 |= (1 << 23);
        break;
      case GLB_AHB_CLOCK_IP_QDEC:
        tmpValCfg1 |= (1 << 24);
        tmpValCfg1 |= (1 << 25);
        tmpValCfg1 |= (1 << 26);
        break;
      case GLB_AHB_CLOCK_IP_KYS:
        tmpValCfg1 |= (1 << 27);
        break;
      case GLB_AHB_CLOCK_IP_I2S:
        tmpValCfg1 |= (1 << 26);
        break;
      case GLB_AHB_CLOCK_IP_USB11:
        tmpValCfg1 |= (1 << 28);
        break;
      case GLB_AHB_CLOCK_IP_CAM:
        tmpValCfg1 |= (1 << 29);
        break;
      case GLB_AHB_CLOCK_IP_MJPEG:
        tmpValCfg1 |= (1 << 30);
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
        tmpValCfg2 |= (1 << 0);
        tmpValCfg2 |= (1 << 4);
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_LP:
        break;
      case GLB_AHB_CLOCK_IP_ZB_NORMAL:
        tmpValCfg2 |= (1 << 0);
        break;
      case GLB_AHB_CLOCK_IP_ZB_LP:
        break;
      case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
        break;
      case GLB_AHB_CLOCK_IP_WIFI_LP:
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
        break;
      case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
        break;
      case GLB_AHB_CLOCK_IP_EMI_MISC:
        break;
      case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
        break;
      case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
        break;
      case GLB_AHB_CLOCK_IP_USB20:
        break;
      case GLB_AHB_CLOCK_IP_MIX2:
        break;
      case GLB_AHB_CLOCK_IP_AUDIO:
        break;
      case GLB_AHB_CLOCK_IP_SDH:
        break;
      default:
        break;
      }
    }
  }
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
  BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX init
                                                                                *
                                                                                * @param  BmxCfg: BMX config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod);
  BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler);
  Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX address monitor enable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
  BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX address monitor disable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
  BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX bus error response enable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
  BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX bus error response disable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
  BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get BMX error status
                                                                                *
                                                                                * @param  errType: BMX error status type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
  if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) {
    return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET;
  } else {
    return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get BMX error address
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return NP BMX error address
                                                                                *
                                                                                *******************************************************************************/
uint32_t GLB_BMX_Get_Err_Addr(void) { return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR); }

/****************************************************************************/ /**
                                                                                * @brief  BMX error interrupt callback install
                                                                                *
                                                                                * @param  intType: BMX error interrupt type
                                                                                * @param  cbFun: callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun) {
  CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType));

  glbBmxErrIntCbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX ERR interrupt IRQ handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void BMX_ERR_IRQHandler(void) {
  BMX_ERR_INT_Type intType;

  for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) {
    if (glbBmxErrIntCbfArra[intType] != NULL) {
      glbBmxErrIntCbfArra[intType]();
    }
  }

  while (1) {
    // MSG("BMX_ERR_IRQHandler\r\n");
    BL702_Delay_MS(1000);
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  BMX timeout interrupt callback install
                                                                                *
                                                                                * @param  intType: BMX timeout interrupt type
                                                                                * @param  cbFun: callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) {
  CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));

  glbBmxToIntCbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  BMX Time Out interrupt IRQ handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void BMX_TO_IRQHandler(void) {
  BMX_TO_INT_Type intType;

  for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) {
    if (glbBmxToIntCbfArra[intType] != NULL) {
      glbBmxToIntCbfArra[intType]();
    }
  }

  while (1) {
    // MSG("BMX_TO_IRQHandler\r\n");
    BL702_Delay_MS(1000);
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  set sram_ret value
                                                                                *
                                                                                * @param  value: value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) {
  BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get sram_ret value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return value
                                                                                *
                                                                                *******************************************************************************/
uint32_t GLB_Get_SRAM_RET(void) { return BL_RD_REG(GLB_BASE, GLB_SRAM_RET); }

/****************************************************************************/ /**
                                                                                * @brief  set sram_slp value
                                                                                *
                                                                                * @param  value: value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) {
  BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get sram_slp value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return value
                                                                                *
                                                                                *******************************************************************************/
uint32_t GLB_Get_SRAM_SLP(void) { return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP); }

/****************************************************************************/ /**
                                                                                * @brief  set sram_param value
                                                                                *
                                                                                * @param  value: value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) {
  BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get sram_parm value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return value
                                                                                *
                                                                                *******************************************************************************/
uint32_t GLB_Get_SRAM_PARM(void) { return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); }

/****************************************************************************/ /**
                                                                                * @brief  select EM type
                                                                                *
                                                                                * @param  emType: EM type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_EM_TYPE(emType));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType);
  BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select pin as EMAC or CAM
                                                                                *
                                                                                * @param  pinType: pin type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_EMAC_CAM_PIN_TYPE(pinType));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PIN_SEL_EMAC_CAM, pinType);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  EXT_RST PAD SMT
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
  }
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Key Scan Column Drive
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
  }
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  swap UART gpio pins sig function
                                                                                *
                                                                                * @param  swapSel: UART swap set gpio pins selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((swapSel <= 0xF));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  swap JTAG gpio pins function
                                                                                *
                                                                                * @param  swapSel: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((swapSel <= 0xFF));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  CCI use GPIO 0 1 2 7
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
  }
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  CCI use JTAG pin
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
  }
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  swap SPI0 MOSI with MISO
                                                                                *
                                                                                * @param  newState: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select SPI_0 act mode
                                                                                *
                                                                                * @param  mod: SPI work mode
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  use internal flash
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  use external flash
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Deswap internal flash pin
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Swap internal flash CS and IO2 pin
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_CS_IO2_Pin(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Swap internal flash IO3 and IO0 pin
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_IO0_IO3_Pin(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
  BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Swap internal flash IO3 and IO0 pin
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void) {
  /*To be removed*/

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Select internal psram
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_PSram(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
  BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  set PDM clock
                                                                                *
                                                                                * @param  enable: Enable or disable PDM clock
                                                                                * @param  div: clock divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
  BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM0_CLK_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set MTimer clock
                                                                                *
                                                                                * @param  enable: enable or disable MTimer clock
                                                                                * @param  clkSel: clock selection
                                                                                * @param  div: divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel));
  CHECK_PARAM((div <= 0x1FFFF));

  /* disable MTimer clock first */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
  BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set ADC clock
                                                                                *
                                                                                * @param  enable: enable or disable ADC clock
                                                                                * @param  clkSel: ADC clock selection
                                                                                * @param  div: divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));

  /* disable ADC clock first */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
  BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
  BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set DAC clock
                                                                                *
                                                                                * @param  enable: enable frequency divider or not
                                                                                * @param  clkSel: ADC clock selection
                                                                                * @param  div: src divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);

  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  }

  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  select DIG clock source
                                                                                *
                                                                                * @param  clkSel: DIG clock selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) {
  uint32_t tmpVal;
  uint32_t dig512kEn;
  uint32_t dig32kEn;

  /* disable DIG512K and DIG32K clock first */
  tmpVal    = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
  dig32kEn  = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
  tmpVal    = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  tmpVal    = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  /* repristinate DIG512K and DIG32K clock */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set DIG 512K clock
                                                                                *
                                                                                * @param  enable: enable or disable DIG 512K clock
                                                                                * @param  compensation: enable or disable DIG 512K clock compensation
                                                                                * @param  div: divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  if (compensation) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
  }
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set DIG 32K clock
                                                                                *
                                                                                * @param  enable: enable or disable DIG 32K clock
                                                                                * @param  compensation: enable or disable DIG 32K clock compensation
                                                                                * @param  div: divider
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint8_t div) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  if (compensation) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
  }
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
  }
  BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set BT coex signal
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal
                                                                                * @param  bandWidth: BT Bandwidth
                                                                                * @param  pti: BT Packet Traffic Information
                                                                                * @param  channel: BT Channel
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth));
  CHECK_PARAM((pti <= 0xF));
  CHECK_PARAM((channel <= 78));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel);
  BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);

  tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
  if (enable) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0);
  }
  BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select UART signal function
                                                                                *
                                                                                * @param  sig: UART signal
                                                                                * @param  fun: UART function
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) {
  uint32_t sig_pos = 0;
  uint32_t tmpVal  = 0;

  CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
  CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));

  tmpVal  = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
  sig_pos = (sig * 4);
  /* Clear original val */
  tmpVal &= (~(0xf << sig_pos));
  /* Set new value */
  tmpVal |= (fun << sig_pos);
  BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power off DLL
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_DLL(void) {
  uint32_t tmpVal = 0;

  /* GLB->dll.BF.ppu_dll = 0;   */
  /* GLB->dll.BF.pu_dll = 0;    */
  /* GLB->dll.BF.dll_reset = 1; */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 1);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  power on DLL
                                                                                *
                                                                                * @param  xtalType: DLL xtal type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));

  /* GLB->dll.BF.dll_refclk_sel = XXX; */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  switch (xtalType) {
  case GLB_DLL_XTAL_NONE:
    return ERROR;
  case GLB_DLL_XTAL_32M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 0);
    break;
  case GLB_DLL_XTAL_RC32M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 1);
    break;
  default:
    break;
  }
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  /* GLB->dll.BF.dll_prechg_sel = 1;   */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_PRECHG_SEL, 1);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  /* GLB->dll.BF.ppu_dll = 1;   */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 1);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  BL702_Delay_US(2);

  /* GLB->dll.BF.pu_dll = 1; */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 1);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  BL702_Delay_US(2);

  /* GLB->dll.BF.dll_reset = 0; */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 0);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  /* delay for settling */
  BL702_Delay_US(5);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  enable all DLL output clock
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_All_Clks(void) {
  uint32_t tmpVal = 0;

  /* GLB->dll.WORD = GLB->dll.WORD | 0x000000f8; include 288m and mmdiv */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  enable one of DLL output clock
                                                                                *
                                                                                * @param  dllClk: None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  switch (dllClk) {
  case GLB_DLL_CLK_57P6M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
    break;
  case GLB_DLL_CLK_96M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
    break;
  case GLB_DLL_CLK_144M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
    break;
  case GLB_DLL_CLK_288M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
    break;
  case GLB_DLL_CLK_MMDIV:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
    break;
  default:
    break;
  }
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  disable all DLL output clock
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_All_Clks(void) {
  uint32_t tmpVal = 0;

  /* GLB->dll.WORD = GLB->dll.WORD & ~0x000000f8; */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  disable one of DLL output clock
                                                                                *
                                                                                * @param  dllClk: None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));

  tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
  switch (dllClk) {
  case GLB_DLL_CLK_57P6M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
    break;
  case GLB_DLL_CLK_96M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
    break;
  case GLB_DLL_CLK_144M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
    break;
  case GLB_DLL_CLK_288M:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
    break;
  case GLB_DLL_CLK_MMDIV:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
    break;
  default:
    break;
  }
  BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Select ir rx gpio (gpio17~gpio31)
                                                                                *
                                                                                * @param  gpio: IR gpio selected
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) {
  uint32_t tmpVal = 0;

  /* Select gpio between gpio17 and gpio31 */
  if (gpio > 16 && gpio < 32) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 16);
    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable ir led driver
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_LED_Driver_Enable(void) {
  uint32_t tmpVal = 0;

  /* Enable led driver */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
  tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
  BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable ir led driver
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_LED_Driver_Disable(void) {
  uint32_t tmpVal = 0;

  /* Disable led driver */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
  tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
  BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable ir led driver gpio output(gpio 22 or 23)
                                                                                *
                                                                                * @param  gpio: IR gpio selected
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio) {
  uint32_t tmpVal = 0;

  if (gpio == GLB_GPIO_PIN_22) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 1);
    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
  } else if (gpio == GLB_GPIO_PIN_23) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 2);
    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable ir led driver gpio output(gpio 22 or 23)
                                                                                *
                                                                                * @param  gpio: IR gpio selected
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio) {
  uint32_t tmpVal = 0;

  if (gpio == GLB_GPIO_PIN_22) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~1);
    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
  } else if (gpio == GLB_GPIO_PIN_23) {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~2);
    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set ir led driver ibias
                                                                                *
                                                                                * @param  ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) {
  uint32_t tmpVal = 0;

  /* Set driver ibias */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF);
  BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO initialization
                                                                                *
                                                                                * @param  cfg: GPIO configuration
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) {
  uint8_t   gpioPin = cfg->gpioPin;
  uint8_t   realPin;
  uint32_t *pOut;
  uint32_t  pos;
  uint32_t  tmpOut;
  uint32_t  tmpVal;

  /* drive strength(drive) = 0  <=>  8.0mA  @ 3.3V */
  /* drive strength(drive) = 1  <=>  9.6mA  @ 3.3V */
  /* drive strength(drive) = 2  <=>  11.2mA @ 3.3V */
  /* drive strength(drive) = 3  <=>  12.8mA @ 3.3V */

  pOut   = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
  pos    = gpioPin % 32;
  tmpOut = *pOut;

  /* Disable output anyway*/
  tmpOut &= (~(1 << pos));
  *pOut = tmpOut;

  realPin = gpioPin;
  /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
  if (gpioPin >= 23 && gpioPin <= 28) {
    if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
      realPin += 9;
    }
  }
  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
  if (realPin % 2 == 0) {
    if (cfg->gpioMode != GPIO_MODE_ANALOG) {
      /* not analog mode */

      /* Set input or output */
      if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
        tmpOut |= (1 << pos);
      } else {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
      }

      /* Set pull up or down */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
      if (cfg->pullType == GPIO_PULL_UP) {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
      } else if (cfg->pullType == GPIO_PULL_DOWN) {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
      }
    } else {
      /* analog mode */

      /* clear ie && oe */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
      tmpOut &= ~(1 << pos);

      /* clear pu && pd */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
    }

    /* set drive && smt && func */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
  } else {
    if (cfg->gpioMode != GPIO_MODE_ANALOG) {
      /* not analog mode */

      /* Set input or output */
      if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
        tmpOut |= (1 << pos);
      } else {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
      }

      /* Set pull up or down */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
      if (cfg->pullType == GPIO_PULL_UP) {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
      } else if (cfg->pullType == GPIO_PULL_DOWN) {
        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
      }
    } else {
      /* analog mode */

      /* clear ie && oe */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
      tmpOut &= ~(1 << pos);

      /* clear pu && pd */
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
    }

    /* set drive && smt && func */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
  }
  BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);

  *pOut = tmpOut;

  /* always on pads IE control (in HBN) */
  if (gpioPin >= 9 && gpioPin <= 13) {
    tmpVal               = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
    uint32_t aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);

    if (cfg->gpioMode != GPIO_MODE_ANALOG) {
      /* not analog mode */

      if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
        aonPadIeSmt &= ~(1 << (gpioPin - 9));
      } else {
        aonPadIeSmt |= (1 << (gpioPin - 9));
      }
    } else {
      /* analog mode */

      /* clear aon pad ie */
      aonPadIeSmt &= ~(1 << (gpioPin - 9));
    }
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
  }

  if (gpioPin >= 23 && gpioPin <= 28) {
    if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
      tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
      if (gpioPin % 2 == 0) {
        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
      } else {
        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
      }
      BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);

      /* sf pad use GPIO23-GPIO28 pinmux&&outputEn */
      pOut   = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
      pos    = gpioPin % 32;
      tmpOut = *pOut;
      /* Disable output anyway*/
      tmpOut &= (~(1 << pos));
      *pOut = tmpOut;
      if (cfg->gpioMode != GPIO_MODE_ANALOG) {
        /* not analog mode */

        if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
          tmpOut |= (1 << pos);
        }
      }
      *pOut = tmpOut;
    }
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  init GPIO function in pin list
                                                                                *
                                                                                * @param  gpioFun: GPIO pin function
                                                                                * @param  pinList: GPIO pin list
                                                                                * @param  cnt: GPIO pin count
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt) {
  GLB_GPIO_Cfg_Type gpioCfg = {.gpioPin = GLB_GPIO_PIN_0, .gpioFun = (uint8_t)gpioFun, .gpioMode = GPIO_MODE_AF, .pullType = GPIO_PULL_UP, .drive = 3, .smtCtrl = 1};

  if (gpioFun == GPIO_FUN_ANALOG) {
    gpioCfg.gpioMode = GPIO_MODE_ANALOG;
  }

  for (uint8_t i = 0; i < cnt; i++) {
    gpioCfg.gpioPin = pinList[i];
    GLB_GPIO_Init(&gpioCfg);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO set input function enable
                                                                                *
                                                                                * @param  gpioPin: GPIO pin
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;
  uint32_t pinOffset;
  uint32_t aonPadIeSmt;

  pinOffset = (gpioPin >> 1) << 2;
  tmpVal    = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
  if (gpioPin % 2 == 0) {
    /* [0] is ie */
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
  } else {
    /* [16] is ie */
    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
  }
  *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;

  /* always on pads IE control (in HBN) */
  if (gpioPin >= 9 && gpioPin <= 13) {
    tmpVal      = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
    aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
    aonPadIeSmt |= (1 << (gpioPin - 9));
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO set input function disable
                                                                                *
                                                                                * @param  gpioPin: GPIO pin
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;
  uint32_t pinOffset;
  uint32_t aonPadIeSmt;

  pinOffset = (gpioPin >> 1) << 2;
  tmpVal    = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
  if (gpioPin % 2 == 0) {
    /* [0] is ie */
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
  } else {
    /* [16] is ie */
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
  }
  *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;

  /* always on pads IE control (in HBN) */
  if (gpioPin >= 9 && gpioPin <= 13) {
    tmpVal      = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
    aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
    aonPadIeSmt &= ~(1 << (gpioPin - 9));
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO set output function enable
                                                                                *
                                                                                * @param  gpioPin: GPIO pin
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
  tmpVal = tmpVal | (1 << gpioPin);
  BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO set output function disable
                                                                                *
                                                                                * @param  gpioPin: GPIO pin
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
  tmpVal = tmpVal & ~(1 << gpioPin);
  BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO set High-Z
                                                                                *
                                                                                * @param  gpioPin: GPIO pin
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) {
  uint32_t *pOut;
  uint32_t  pos;
  uint32_t  tmpOut;
  uint32_t  tmpVal;
  uint32_t  aonPadIeSmt;
  uint8_t   realPin;

  /* always on pads IE control (in HBN) */
  if (gpioPin >= 9 && gpioPin <= 13) {
    tmpVal      = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
    aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
    aonPadIeSmt &= ~(1 << (gpioPin - 9));
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
  }

  realPin = gpioPin;
  /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
  if (gpioPin >= 23 && gpioPin <= 28) {
    if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
      realPin += 9;
    }
  }
  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);

  /* pu=0, pd=0, ie=0 */
  if (realPin % 2 == 0) {
    tmpVal = (tmpVal & 0xffffff00);
  } else {
    tmpVal = (tmpVal & 0xff00ffff);
  }

  BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);

  pOut   = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
  pos    = gpioPin % 32;
  tmpOut = *pOut;

  /* Disable output anyway*/
  tmpOut &= (~(1 << pos));
  *pOut = tmpOut;

  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);

  /* func_sel=swgpio */
  if (gpioPin % 2 == 0) {
    tmpVal = (tmpVal & 0xffff00ff);
    tmpVal |= 0x0B00;
  } else {
    tmpVal = (tmpVal & 0x00ffffff);
    tmpVal |= (0x0B00 << 16);
  }

  BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);

  /* Disable output anyway*/
  *pOut = tmpOut;

  return SUCCESS;
}

BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void) {
  uint32_t tmpVal;
  uint32_t offset;

  if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x00) {
    return ERROR;
  }

  for (offset = 23; offset <= 28; offset++) {
    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
    /* pu=0, pd=0, ie=0 */
    if (offset % 2 == 0) {
      tmpVal = (tmpVal & 0xffffff00);
    } else {
      tmpVal = (tmpVal & 0xff00ffff);
    }
    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);

    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
    /* func_sel=swgpio */
    if (offset % 2 == 0) {
      tmpVal = (tmpVal & 0xffff00ff);
      tmpVal |= 0x0B00;
    } else {
      tmpVal = (tmpVal & 0x00ffffff);
      tmpVal |= (0x0B00 << 16);
    }
    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
  }

  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
  tmpVal &= 0xE07FFFFF;
  BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);

  return SUCCESS;
}

BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void) {
  uint32_t tmpVal;
  uint32_t offset;

  if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x3F) {
    return ERROR;
  }

  for (offset = 32; offset <= 37; offset++) {
    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
    /* pu=0, pd=0, ie=0 */
    if (offset % 2 == 0) {
      tmpVal = (tmpVal & 0xffffff00);
    } else {
      tmpVal = (tmpVal & 0xff00ffff);
    }
    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);

    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4);
    /* func_sel=swgpio */
    if ((offset - 9) % 2 == 0) {
      tmpVal = (tmpVal & 0xffff00ff);
      tmpVal |= 0x0B00;
    } else {
      tmpVal = (tmpVal & 0x00ffffff);
      tmpVal |= (0x0B00 << 16);
    }
    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal);
  }

  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
  tmpVal &= 0xE07FFFFF;
  BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get GPIO function
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                *
                                                                                * @return GPIO function
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;

  tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);

  if (gpioPin % 2 == 0) {
    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
  } else {
    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL);
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Write GPIO
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  val: GPIO value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val) {
  uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
  uint32_t  pos  = gpioPin % 32;
  uint32_t  tmpOut;

  tmpOut = *pOut;
  if (val > 0) {
    tmpOut |= (1 << pos);
  } else {
    tmpOut &= (~(1 << pos));
  }
  *pOut = tmpOut;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Read GPIO
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                *
                                                                                * @return GPIO value
                                                                                *
                                                                                *******************************************************************************/
uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin) {
  uint32_t *p   = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
  uint32_t  pos = gpioPin % 32;

  if ((*p) & (1 << pos)) {
    return 1;
  } else {
    return 0;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mask
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intMask: GPIO interrupt MASK or UNMASK
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1);
    if (intMask == MASK) {
      tmpVal = tmpVal | (1 << gpioPin);
    } else {
      tmpVal = tmpVal & ~(1 << gpioPin);
    }
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mask
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intClear: GPIO interrupt clear or unclear
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) {
  uint32_t tmpVal;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
    if (intClear == SET) {
      tmpVal = tmpVal | (1 << gpioPin);
    } else {
      tmpVal = tmpVal & ~(1 << gpioPin);
    }
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get GLB GPIO interrrupt status
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal = 0;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1);
  }

  return (tmpVal & (1 << gpioPin)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mode
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intCtlMod: GPIO interrupt control mode
                                                                                * @param  intTrgMod: GPIO interrupt trigger mode
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) {
  uint32_t tmpVal;
  uint32_t tmpGpioPin;

  CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
  CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));

  if (gpioPin < GLB_GPIO_PIN_10) {
    /* GPIO0 ~ GPIO9 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
    tmpGpioPin = gpioPin;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal);
  } else if (gpioPin < GLB_GPIO_PIN_20) {
    /* GPIO10 ~ GPIO19 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal);
  } else if (gpioPin < GLB_GPIO_PIN_30) {
    /* GPIO20 ~ GPIO29 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
  } else {
    /* GPIO30 ~ GPIO31 not recommend */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get GPIO interrupt control mode
                                                                                *
                                                                                * @param  gpioPin: GPIO pin type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;
  uint32_t bitVal;

  if (gpioPin < GLB_GPIO_PIN_10) {
    /* GPIO0 - GPIO9 */
    bitVal = gpioPin - 0;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
    /* GPIO10 - GPIO19 */
    bitVal = gpioPin - 10;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
    /* GPIO20 - GPIO29 */
    bitVal = gpioPin - 20;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else {
    /* GPIO30 ~ GPIO31 not recommend */
    bitVal = gpioPin - 30;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mask 2
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intMask: GPIO interrupt MASK or UNMASK
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MASK1);
    if (intMask == MASK) {
      tmpVal = tmpVal | (1 << gpioPin);
    } else {
      tmpVal = tmpVal & ~(1 << gpioPin);
    }
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MASK1, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mask 2
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intClear: GPIO interrupt clear or unclear
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear) {
  uint32_t tmpVal;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_CLR1);
    if (intClear == SET) {
      tmpVal = tmpVal | (1 << gpioPin);
    } else {
      tmpVal = tmpVal & ~(1 << gpioPin);
    }
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_CLR1, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get GLB GPIO interrrupt status 2
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal = 0;

  if (gpioPin < 32) {
    /* GPIO0 ~ GPIO31 */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_STAT1);
  }

  return (tmpVal & (1 << gpioPin)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  Set GLB GPIO interrupt mode 2
                                                                                *
                                                                                * @param  gpioPin: GPIO type
                                                                                * @param  intCtlMod: GPIO interrupt control mode
                                                                                * @param  intTrgMod: GPIO interrupt trigger mode
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod) {
  uint32_t tmpVal;
  uint32_t tmpGpioPin;

  CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
  CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));

  if (gpioPin < GLB_GPIO_PIN_10) {
    /* GPIO0 ~ GPIO9 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
    tmpGpioPin = gpioPin;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1, tmpVal);
  } else if (gpioPin < GLB_GPIO_PIN_20) {
    /* GPIO10 ~ GPIO19 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2, tmpVal);
  } else if (gpioPin < GLB_GPIO_PIN_30) {
    /* GPIO20 ~ GPIO29 */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3, tmpVal);
  } else {
    /* GPIO30 ~ GPIO31 not recommend */
    tmpVal     = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
    tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
    tmpVal     = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
    BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get GPIO interrupt control mode 2
                                                                                *
                                                                                * @param  gpioPin: GPIO pin type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin) {
  uint32_t tmpVal;
  uint32_t bitVal;

  if (gpioPin < GLB_GPIO_PIN_10) {
    /* GPIO0 - GPIO9 */
    bitVal = gpioPin - 0;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
    /* GPIO10 - GPIO19 */
    bitVal = gpioPin - 10;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
    /* GPIO20 - GPIO29 */
    bitVal = gpioPin - 20;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  } else {
    /* GPIO30 ~ GPIO31 not recommend */
    bitVal = gpioPin - 30;
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
    tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
    return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO INT0 IRQHandler install
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) {
#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO interrupt IRQ handler callback install
                                                                                *
                                                                                * @param  gpioPin: GPIO pin type
                                                                                * @param  cbFun: callback function
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) {
  if (gpioPin < 32) {
    glbGpioInt0CbfArra[gpioPin] = cbFun;
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO interrupt IRQ handler callback install2
                                                                                *
                                                                                * @param  gpioPin: GPIO pin type
                                                                                * @param  cbFun: callback function
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) {
  if (gpioPin < 32) {
    glbGpioInt0CbfArra2[gpioPin] = cbFun;
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  GPIO interrupt IRQ handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void GPIO_INT0_IRQHandler(void) {
  GLB_GPIO_Type gpioPin;
  uint32_t      timeOut = 0;

  for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_31; gpioPin++) {
    if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
      GLB_GPIO_IntClear(gpioPin, SET);

      /* timeout check */
      timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
      do {
        timeOut--;
      } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
      if (!timeOut) {
        // MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
      }

      /* if timeOut==0, GPIO interrupt status not cleared */
      GLB_GPIO_IntClear(gpioPin, RESET);

      if (glbGpioInt0CbfArra[gpioPin] != NULL) {
        /* Call the callback function */
        glbGpioInt0CbfArra[gpioPin]();
      }
    }
    if (SET == GLB_Get_GPIO_Int2Status(gpioPin)) {
      GLB_GPIO_Int2Clear(gpioPin, SET);

      /* timeout check */
      timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
      do {
        timeOut--;
      } while ((SET == GLB_Get_GPIO_Int2Status(gpioPin)) && timeOut);
      if (!timeOut) {
        // MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
      }

      /* if timeOut==0, GPIO interrupt status not cleared */
      GLB_GPIO_Int2Clear(gpioPin, RESET);

      if (glbGpioInt0CbfArra2[gpioPin] != NULL) {
        /* Call the callback function */
        glbGpioInt0CbfArra2[gpioPin]();
      }
    }
  }
}
#endif

/*@} end of group GLB_Public_Functions */

/*@} end of group GLB */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_hbn.c
================================================
/**
 ******************************************************************************
 * @file    bl702_hbn.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_hbn.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  HBN
 *  @{
 */

/** @defgroup  HBN_Private_Macros
 *  @{
 */
#define HBN_CLK_SET_DUMMY_WAIT                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
    __NOP();                                                                                                                                                                                           \
  }

/*@} end of group HBN_Private_Macros */

/** @defgroup  HBN_Private_Types
 *  @{
 */

/*@} end of group HBN_Private_Types */

/** @defgroup  HBN_Private_Variables
 *  @{
 */
static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_MAX] = {NULL, NULL, NULL, NULL, NULL, NULL};
static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_MAX] = {NULL, NULL, NULL, NULL};

/*@} end of group HBN_Private_Variables */

/** @defgroup  HBN_Global_Variables
 *  @{
 */

/*@} end of group HBN_Global_Variables */

/** @defgroup  HBN_Private_Fun_Declaration
 *  @{
 */

/*@} end of group HBN_Private_Fun_Declaration */

/** @defgroup  HBN_Private_Functions
 *  @{
 */

/*@} end of group HBN_Private_Functions */

/** @defgroup  HBN_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Enter HBN
                                                                                *
                                                                                * @param  cfg: HBN APP Config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) {
  uint32_t valLow = 0, valHigh = 0;
  uint64_t val;

  /* work clock select */
  if (cfg->useXtal32k) {
    HBN_32K_Sel(HBN_32K_XTAL);
  } else {
    HBN_32K_Sel(HBN_32K_RC);
    HBN_Power_Off_Xtal_32K();
  }

  /* turn off RC32K during HBN */
  if ((cfg->hbnLevel) >= HBN_LEVEL_2) {
    HBN_Power_Off_RC32K();
  } else {
    HBN_Power_On_RC32K();
  }

  /* clear aon pad interrupt before config them */
  HBN_Clear_IRQ(HBN_INT_GPIO9);
  HBN_Clear_IRQ(HBN_INT_GPIO10);
  HBN_Clear_IRQ(HBN_INT_GPIO11);
  HBN_Clear_IRQ(HBN_INT_GPIO12);
  HBN_Clear_IRQ(HBN_INT_GPIO13);

  /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
  HBN_Hw_Pu_Pd_Cfg(DISABLE);

  HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));

  if (cfg->gpioWakeupSrc != 0) {
    HBN_Aon_Pad_IeSmt_Cfg(cfg->gpioWakeupSrc);
    HBN_GPIO_INT_Enable(cfg->gpioTrigType);
  } else {
    HBN_Aon_Pad_IeSmt_Cfg(0);
  }

  /* HBN RTC config and enable */
  if (cfg->sleepTime != 0) {
    // set rtc enable flag
    BL_WR_WORD(0x40010FFC, 0x1);

    HBN_Clear_RTC_Counter();
    HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
    val = valLow + ((uint64_t)valHigh << 32);
    val += cfg->sleepTime;
    HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
    HBN_Enable_RTC_Counter();
  }

  HBN_Power_Down_Flash(cfg->flashCfg);

  switch (cfg->flashPinCfg) {
  case 0:
    HBN_Set_Pad_23_28_Pullup();
    break;

  case 1:
    /* need do nothing */
    break;

  case 2:
    /* need do nothing */
    break;

  case 3:
    /* can do nothing */
    break;

  default:
    break;
  }

  GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);

  /* power off xtal */
  AON_Power_Off_XTAL();

  HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel);
}

/****************************************************************************/ /**
                                                                                * @brief  power down and switch clock
                                                                                *
                                                                                * @param  flashCfg: None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) {
  SPI_Flash_Cfg_Type bhFlashCfg;

  if (flashCfg == NULL) {
    /* fix this some time */
    /* SFlash_Cache_Flush(); */
    XIP_SFlash_Read_Via_Cache_Need_Lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type));
    /* fix this some time */
    /* SFlash_Cache_Flush(); */

    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
    SFlash_Reset_Continue_Read(&bhFlashCfg);
  } else {
    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
    SFlash_Reset_Continue_Read(flashCfg);
  }

  SFlash_Powerdown();
}

/****************************************************************************/ /**
                                                                                * @brief  Enable HBN mode
                                                                                *
                                                                                * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
                                                                                *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                * @param  hbnLevel: HBN work level
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
  CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));

  /* Setting from guide */
  /* RAM Retion, no longer use */
  /* BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); */

  /* AON GPIO IE */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  /* HBN mode LDO level */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  /* Select RC32M */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  /* Set HBN flag */
  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);

  /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
  switch (hbnLevel) {
  case HBN_LEVEL_0:
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_2:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_3:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  default:
    break;
  }

  /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  /* Enable HBN mode */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  while (1) {
    BL702_Delay_MS(1000);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Reset HBN mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Reset HBN mode */
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  reset HBN by software
                                                                                *
                                                                                * @param  npXtalType: NP clock type
                                                                                * @param  bclkDiv: NP clock div
                                                                                * @param  apXtalType: AP clock type
                                                                                * @param  fclkDiv: AP clock div
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv) {
  uint32_t tmp[12];

  tmp[0]  = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmp[1]  = BL_RD_REG(HBN_BASE, HBN_TIME_L);
  tmp[2]  = BL_RD_REG(HBN_BASE, HBN_TIME_H);
  tmp[3]  = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmp[4]  = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
  tmp[5]  = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
  tmp[6]  = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
  tmp[7]  = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
  tmp[8]  = BL_RD_REG(HBN_BASE, HBN_SRAM);
  tmp[9]  = BL_RD_REG(HBN_BASE, HBN_RSV0);
  tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1);
  tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2);
  /* DO HBN reset */
  HBN_Reset();
  /* HBN need 3 32k cyclce to recovery */
  BL702_Delay_US(100);
  /* Recover HBN value */
  BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]);
  BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]);

  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]);
  BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]);
  BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]);
  BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]);
  BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]);
  BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]);
  BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable HBN mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Disable HBN mode */
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable HBN PIR
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_PIR_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable HBN PIR
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_PIR_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Config HBN PIR interrupt
                                                                                *
                                                                                * @param  pirIntCfg: HBN PIR interrupt configuration
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg) {
  uint32_t tmpVal;
  uint32_t bit4   = 0;
  uint32_t bit5   = 0;
  uint32_t bitVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);

  /* low trigger interrupt */
  if (pirIntCfg->lowIntEn == ENABLE) {
    bit5 = 0;
  } else {
    bit5 = 1;
  }

  /* high trigger interrupt */
  if (pirIntCfg->highIntEn == ENABLE) {
    bit4 = 0;
  } else {
    bit4 = 1;
  }

  bitVal = bit4 | (bit5 << 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select HBN PIR low pass filter
                                                                                *
                                                                                * @param  lpf: HBN PIR low pass filter selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select HBN PIR high pass filter
                                                                                *
                                                                                * @param  hpf: HBN PIR high pass filter selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
  BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set HBN PIR threshold value
                                                                                *
                                                                                * @param  threshold: HBN PIR threshold value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold) {
  uint32_t tmpVal;

  CHECK_PARAM((threshold <= 0x3FFF));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
  BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get HBN PIR threshold value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return HBN PIR threshold value
                                                                                *
                                                                                *******************************************************************************/
uint16_t HBN_Get_PIR_Threshold(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);

  return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
}

/****************************************************************************/ /**
                                                                                * @brief  Set HBN PIR interval value
                                                                                *
                                                                                * @param  interval: HBN PIR interval value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval) {
  uint32_t tmpVal;

  CHECK_PARAM((interval <= 0xFFF));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
  BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get HBN PIR interval value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return HBN PIR interval value
                                                                                *
                                                                                *******************************************************************************/
uint16_t HBN_Get_PIR_Interval(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);

  return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
}

/****************************************************************************/ /**
                                                                                * @brief  get HBN bor out state
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type HBN_Get_BOR_OUT_State(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOR_OUT) ? SET : RESET; }

/****************************************************************************/ /**
                                                                                * @brief  set HBN bor config
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
                                                                                * @param  threshold: bor threshold
                                                                                * @param  mode: bor work mode with por
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold));
  CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);

  if (enable) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0);
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set ldo11aon voltage out
                                                                                *
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set ldo11rt voltage out
                                                                                *
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set ldo11soc voltage out
                                                                                *
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set ldo11 all voltage out
                                                                                *
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set ldo11rt drive strength
                                                                                *
                                                                                * @param  strength: ldo11rt drive strength
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(strength));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_ILOAD_SEL, strength);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN select 32K
                                                                                *
                                                                                * @param  clkType: HBN 32k clock type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));

  HBN_Trim_RC32K();

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select uart clock source
                                                                                *
                                                                                * @param  clkSel: uart clock type selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select xclk clock source
                                                                                *
                                                                                * @param  xClk: xclk clock type selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);

  switch (xClk) {
  case HBN_XCLK_CLK_RC32M:
    tmpVal2 &= (~(1 << 0));
    break;

  case HBN_XCLK_CLK_XTAL:
    tmpVal2 |= (1 << 0);
    break;

  default:
    break;
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  HBN_CLK_SET_DUMMY_WAIT;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Select root clk source
                                                                                *
                                                                                * @param  rootClk: root clock type selection
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);

  switch (rootClk) {
  case HBN_ROOT_CLK_RC32M:
    tmpVal2 = 0x0;
    break;

  case HBN_ROOT_CLK_XTAL:
    tmpVal2 = 0x1;
    break;

  case HBN_ROOT_CLK_DLL:
    tmpVal2 |= (1 << 1);
    break;

  default:
    break;
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  HBN_CLK_SET_DUMMY_WAIT;

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  set HBN_RAM sleep mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_HRAM_slp(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
  BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set HBN_RAM retension mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_HRAM_Ret(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
  BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on XTAL 32K
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
  BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);

  /* Delay >1s */
  BL702_Delay_US(1100);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off XTAL 32K
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
  BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power on RC32K
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  /* Delay >800us */
  BL702_Delay_US(880);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Power off RC3K
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Trim RC32K
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) {
  Efuse_Ana_RC32K_Trim_Type trim;
  int32_t                   tmpVal = 0;

  EF_Ctrl_Read_RC32K_Trim(&trim);

  if (trim.trimRc32kExtCodeEn) {
    if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {
      tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);
      tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
      BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
      BL702_Delay_US(2);
      return SUCCESS;
    }
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get HBN status flag
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return HBN status flag value
                                                                                *
                                                                                *******************************************************************************/
uint32_t HBN_Get_Status_Flag(void) { return BL_RD_REG(HBN_BASE, HBN_RSV0); }

/****************************************************************************/ /**
                                                                                * @brief  Set HBN status flag
                                                                                *
                                                                                * @param  flag: Status Flag
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) {
  BL_WR_REG(HBN_BASE, HBN_RSV0, flag);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get HBN wakeup address
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return HBN wakeup address
                                                                                *
                                                                                *******************************************************************************/
uint32_t HBN_Get_Wakeup_Addr(void) { return BL_RD_REG(HBN_BASE, HBN_RSV1); }

/****************************************************************************/ /**
                                                                                * @brief  Set HBN wakeup address
                                                                                *
                                                                                * @param  addr: HBN wakeup address
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) {
  BL_WR_REG(HBN_BASE, HBN_RSV1, addr);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN clear RTC timer counter
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Clear_RTC_Counter(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Clear RTC control bit0 */
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN clear RTC timer counter
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Enable_RTC_Counter(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Set RTC control bit0 */
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN set RTC timer configuration
                                                                                *
                                                                                * @param  delay: RTC interrupt delay 32 clocks
                                                                                * @param  compValLow: RTC interrupt commpare value low 32 bits
                                                                                * @param  compValHigh: RTC interrupt commpare value high 32 bits
                                                                                * @param  compMode: RTC interrupt commpare
                                                                                *                   mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));

  BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
  BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Set interrupt delay option */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
  /* Set RTC compare mode */
  tmpVal |= (compMode << 1);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN get RTC async timer count value
                                                                                *
                                                                                * @param  valLow: RTC count value pointer for low 32 bits
                                                                                * @param  valHigh: RTC count value pointer for high 8 bits
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh) {
  uint32_t tmpVal;

  /* Tigger RTC val read */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
  BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);

  /* Read RTC val */
  *valLow  = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
  *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN get RTC timer count value
                                                                                *
                                                                                * @param  valLow: RTC count value pointer for low 32 bits
                                                                                * @param  valHigh: RTC count value pointer for high 8 bits
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh) {
  uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
  uint64_t val, val1;

  do {
    HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
    val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
    HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
    val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
  } while (val1 < val);

  *valLow  = tmpValLow1;
  *valHigh = tmpValHigh1;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Clear_RTC_INT(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN enable GPIO interrupt
                                                                                *
                                                                                * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN disable GPIO interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_GPIO_INT_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN get interrupt status
                                                                                *
                                                                                * @param  irqType: HBN interrupt type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) {
  uint32_t tmpVal;

  /* Check the parameters */

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);

  if (tmpVal & (1 << irqType)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  HBN get pin wakeup mode value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return HBN pin wakeup mode value
                                                                                *
                                                                                *******************************************************************************/
uint8_t HBN_Get_Pin_Wakeup_Mode(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); }

/****************************************************************************/ /**
                                                                                * @brief  HBN clear interrupt status
                                                                                *
                                                                                * @param  irqType: HBN interrupt type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_INT_TYPE(irqType));

  /* set clear bit */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
  tmpVal |= (1 << irqType);
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);

  /* unset clear bit */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
  tmpVal &= (~(1 << irqType));
  BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN hardware pullup or pulldown configuration
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);

  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
  }

  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN Config AON pad input and SMT
                                                                                *
                                                                                * @param  padCfg: AON pad config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN wakeup pin mask configuration
                                                                                *
                                                                                * @param  maskVal: mask value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN enable ACOMP0 interrupt
                                                                                *
                                                                                * @param  edge: HBN acomp interrupt edge type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
  tmpVal2 = tmpVal2 | (1 << edge);
  tmpVal  = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN disable ACOMP0 interrupt
                                                                                *
                                                                                * @param  edge: HBN acomp interrupt edge type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
  tmpVal2 = tmpVal2 & (~(1 << edge));
  tmpVal  = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN enable ACOMP1 interrupt
                                                                                *
                                                                                * @param  edge: HBN acomp interrupt edge type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
  tmpVal2 = tmpVal2 | (1 << edge);
  tmpVal  = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN disable ACOMP1 interrupt
                                                                                *
                                                                                * @param  edge: HBN acomp interrupt edge type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) {
  uint32_t tmpVal;
  uint32_t tmpVal2;

  CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));

  tmpVal  = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
  tmpVal2 = tmpVal2 & (~(1 << edge));
  tmpVal  = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN enable BOR interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Enable_BOR_IRQ(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN disable BOR interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Disable_BOR_IRQ(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get HBN reset event status
                                                                                *
                                                                                * @param  event: HBN reset event type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT);

  return (tmpVal & (1 << event)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  clear HBN reset event status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Clear_Reset_Event(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN out0 install interrupt callback
                                                                                *
                                                                                * @param  intType: HBN out0 interrupt type
                                                                                * @param  cbFun: HBN out0 interrupt callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));

  hbnInt0CbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN out1 install interrupt callback
                                                                                *
                                                                                * @param  intType: HBN out1 interrupt type
                                                                                * @param  cbFun: HBN out1 interrupt callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));

  hbnInt1CbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN GPIO debug pull config
                                                                                *
                                                                                * @param  pupdEn: Enable or disable GPIO pull down and pull up
                                                                                * @param  dlyEn: Enable or disable GPIO wakeup delay function
                                                                                * @param  dlySec: GPIO wakeup delay sec 1 to 7
                                                                                * @param  gpioIrq: HBN GPIO num
                                                                                * @param  gpioMask: HBN GPIO MASK or UNMASK
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask) {
  uint32_t tmpVal;

  CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
  CHECK_PARAM((gpioIrq >= HBN_INT_GPIO9) && (gpioIrq <= HBN_INT_GPIO13));

  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn);

  if (gpioMask != UNMASK) {
    tmpVal = tmpVal | (1 << (gpioIrq + 8));
  } else {
    tmpVal = tmpVal & ~(1 << (gpioIrq + 8));
  }

  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set pad 23-28 pull none
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullnone(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set pad 23-28 pull up
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullup(void) {
  uint32_t tmpVal = 0;

  /********************************************/
  /* GPIO28 is bootpin, so leave it pull none */
  /********************************************/

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set pad 23-28 pull down
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pulldown(void) {
  uint32_t tmpVal = 0;

  /********************************************/
  /* GPIO28 is bootpin, so leave it pull none */
  /********************************************/

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set pad 23-28 active ie
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_ActiveIE(void) {
  uint32_t tmpVal = 0;

  /********************************************/
  /* GPIO28 is bootpin, so leave it pull none */
  /********************************************/

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set BOR config
                                                                                *
                                                                                * @param  cfg: Enable or disable
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) {
  uint32_t tmpVal = 0;

  if (cfg->enableBorInt) {
    HBN_Enable_BOR_IRQ();
  } else {
    HBN_Disable_BOR_IRQ();
  }

  tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold);

  if (cfg->enablePorInBor) {
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL);
  }

  if (cfg->enableBor) {
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
  }

  BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN OUT0 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void HBN_OUT0_IRQHandler(void) {
  if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
    HBN_Clear_IRQ(HBN_INT_GPIO9);

    if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO9] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_GPIO9]();
    }
  }

  if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
    HBN_Clear_IRQ(HBN_INT_GPIO10);

    if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO10] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_GPIO10]();
    }
  }

  if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
    HBN_Clear_IRQ(HBN_INT_GPIO11);

    if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO11] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_GPIO11]();
    }
  }

  if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
    HBN_Clear_IRQ(HBN_INT_GPIO12);

    if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO12] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_GPIO12]();
    }
  }

  if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) {
    HBN_Clear_IRQ(HBN_INT_GPIO13);

    if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO13] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_GPIO13]();
    }
  }

  if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
    HBN_Clear_IRQ(HBN_INT_RTC);
    HBN_Clear_RTC_INT();

    if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
      hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  HBN OUT1 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void HBN_OUT1_IRQHandler(void) {
  /* PIR */
  if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
    HBN_Clear_IRQ(HBN_INT_PIR);

    if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
      hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
    }
  }

  /* BOR */
  if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
    HBN_Clear_IRQ(HBN_INT_BOR);

    if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) {
      hbnInt1CbfArra[HBN_OUT1_INT_BOR]();
    }
  }

  /* ACOMP0 */
  if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
    HBN_Clear_IRQ(HBN_INT_ACOMP0);

    if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
      hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
    }
  }

  /* ACOMP1 */
  if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
    HBN_Clear_IRQ(HBN_INT_ACOMP1);

    if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
      hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Enable HBN mode
                                                                                *
                                                                                * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
                                                                                *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
                                                                                * @param  ldoLevel: LDO volatge level
                                                                                * @param  hbnLevel: HBN work level
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
  CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));

  /* Setting from guide */
  /* RAM Retion */
  BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24);
  /* AON GPIO IE */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
  ///* Power off 1.8V */
  // tmpVal=BL_RD_REG(AON_BASE,AON_PMIP);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO);
  ///* SOC11 enum is not the same as VDD11*/
  // tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1);
  // BL_WR_REG(AON_BASE,AON_PMIP,tmpVal);
  //
  ///* Set RT voltage */
  // tmpVal=BL_RD_REG(AON_BASE,AON);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON);
  ///* RT11 enum is not the same as VDD11*/
  // tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1);
  // tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel);
  // BL_WR_REG(AON_BASE,AON,tmpVal);

  /* Select RC32M */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
  BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  /* Set HBN flag */
  BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);

  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);

  /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
  switch (hbnLevel) {
  case HBN_LEVEL_0:
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_1:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_2:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  case HBN_LEVEL_3:
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
    break;

  default:
    break;
  }

  /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  /* Enable HBN mode */
  tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
  tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
  BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);

  while (1) {
    BL702_Delay_MS(1000);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  HBN out0 IRQHandler install
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Out0_IRQHandler_Install(void) {
  Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  HBN out1 IRQHandler install
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type HBN_Out1_IRQHandler_Install(void) {
  Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
  return SUCCESS;
}

/*@} end of group HBN_Public_Functions */

/*@} end of group HBN */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c.c
================================================
/**
 ******************************************************************************
 * @file    bl702_i2c.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_i2c.h"
#include "bflb_platform.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2C
 *  @{
 */

/** @defgroup  I2C_Private_Macros
 *  @{
 */
#define I2C_FIFO_STATUS_TIMEOUT (160 * 1000 * 2)
#define PUT_UINT32_LE(n, b, i)                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    (b)[(i)]     = (uint8_t)((n));                                                                                                                                                                     \
    (b)[(i) + 1] = (uint8_t)((n) >> 8);                                                                                                                                                                \
    (b)[(i) + 2] = (uint8_t)((n) >> 16);                                                                                                                                                               \
    (b)[(i) + 3] = (uint8_t)((n) >> 24);                                                                                                                                                               \
  }

/*@} end of group I2C_Private_Macros */

/** @defgroup  I2C_Private_Types
 *  @{
 */

/*@} end of group I2C_Private_Types */

/** @defgroup  I2C_Private_Variables
 *  @{
 */
intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = {{NULL}};

/*@} end of group I2C_Private_Variables */

/** @defgroup  I2C_Global_Variables
 *  @{
 */

/*@} end of group I2C_Global_Variables */

/** @defgroup  I2C_Private_Fun_Declaration
 *  @{
 */

/*@} end of group I2C_Private_Fun_Declaration */

/** @defgroup  I2C_Private_Functions
 *  @{
 */

/**
 * @brief  I2C interrupt handler
 *
 * @param  i2cNo: I2C ID type
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
static void I2C_IntHandler(I2C_ID_Type i2cNo) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) {
    if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) {
      /* Call the callback function */
      i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT]();
    }
  }
}
#endif

/*@} end of group I2C_Private_Functions */

/** @defgroup  I2C_Public_Functions
 *  @{
 */

/**
 * @brief  I2C write word data
 *
 * @param  i2cNo: I2C ID type
 * @param  data: Data word
 *
 * @return None
 *
 *******************************************************************************/
void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) {
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
  BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data);
}

/**
 * @brief  I2C read word data
 *
 * @param  i2cNo: I2C ID type
 *
 * @return word data
 *
 *******************************************************************************/
uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo) {
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
  return BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
}

/**
 * @brief  I2C enable
 *
 * @param  i2cNo: I2C ID type
 *
 * @return None
 *
 *******************************************************************************/
void I2C_Enable(I2C_ID_Type i2cNo) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  // Set the M_EN bit

  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
}

uint8_t I2C_GetTXFIFOAvailable() {

  volatile uint32_t tmpVal;
  uint32_t          I2Cx = I2C_BASE;

  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1);
  return tmpVal & 0b11; // Lowest two bits
}

uint8_t I2C_GetRXFIFOAvailable() {

  volatile uint32_t tmpVal;
  uint32_t          I2Cx = I2C_BASE;

  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1);
  return (tmpVal >> 8) & 0b11; // Lowest two bits of byte 2
}

void I2C_DMATxEnable() {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_DMA_TX_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);

  // tmpVal = BL_SET_REG_BIT(tmpVal, I2C_DMA_RX_EN);

  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);

  // Ensure fifo setpoint is as we expect
  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1);
  tmpVal &= I2C_TX_FIFO_CNT_UMSK;
  tmpVal |= 1;

  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_1, tmpVal);
}
void I2C_DMATxDisable() {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_DMA_TX_EN);
  // tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_DMA_RX_EN);
  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);

  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1);
  tmpVal &= I2C_TX_FIFO_CNT_UMSK;
  tmpVal |= 1;

  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_1, tmpVal);
}

/**
 * @brief  I2C disable
 *
 * @param  i2cNo: I2C ID type
 *
 * @return None
 *
 *******************************************************************************/
void I2C_Disable(I2C_ID_Type i2cNo) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);

  /* Clear I2C fifo */
  tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);
  BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);

  /* Clear I2C interrupt status */
  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR);
  BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
}

/**
 * @brief  I2C set global reset function
 *
 * @param  i2cNo: I2C ID type
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo) {
  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C);
  return SUCCESS;
}

/**
 * @brief  I2C init function
 *
 * @param  i2cNo: I2C ID type
 * @param  direct: I2C read or write direct
 * @param  cfg: I2C transfer config struct
 *
 * @return None
 *
 *******************************************************************************/
void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2C);

  /* I2C write config */
  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);

  if (direct == I2C_WRITE) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
  } else {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr);

  if (cfg->subAddrSize > 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
  }

  // Packet length <=256 bytes per transaction

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1);
  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);

  /* Set sub address */
  BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr);

  Interrupt_Handler_Register(I2C_IRQn, I2C_IRQHandler);
}

/**
 * @brief  Set de-glitch function cycle count value
 *
 * @param  i2cNo: I2C ID type
 * @param  cnt: De-glitch function cycle count
 *
 * @return SUCCESS
 *
 *******************************************************************************/
BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);

  if (cnt > 0) {
    /* enable de-glitch function */
    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
  } else if (cnt == 0) {
    /* disable de-glitch function */
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN);
  } else {
    return ERROR;
  }

  /* Set count value */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt);
  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);

  return SUCCESS;
}

/**
 * @brief  Set i2c prd
 *
 * @param  i2cNo: I2C ID type
 * @param  phase: I2C phase value
 *
 * @return None
 *
 *******************************************************************************/
void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  // phase_cycles = (32000000 / phase / 4) - 1;
  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase);
  BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal);
  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase);
  BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal);
  tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase);
  BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal);
}

/**
 * @brief  I2C set scl output clock
 *
 * @param  i2cNo: I2C ID type
 * @param  clk: Clock set
 *
 * @return None
 *
 *******************************************************************************/
void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) {
  uint8_t bclkDiv = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  bclkDiv = GLB_Get_BCLK_Div();

  if (clk >= 100000) {
    GLB_Set_I2C_CLK(1, 0);
    I2C_SetPrd(i2cNo, (SystemCoreClockGet() / (bclkDiv + 1)) / (clk * 4) - 1);
  } else if (clk >= 8000) {
    GLB_Set_I2C_CLK(1, 9);
    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 10) / (clk * 4) - 1);
  } else if (clk >= 800) {
    GLB_Set_I2C_CLK(1, 99);
    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 100) / (clk * 4) - 1);
  } else {
    GLB_Set_I2C_CLK(1, 255);
    I2C_SetPrd(i2cNo, ((SystemCoreClockGet() / (bclkDiv + 1)) / 256) / (clk * 4) - 1);
  }
}

/**
 * @brief  I2C set scl sync
 *
 * @param  i2cNo: I2C ID type
 * @param  enable: Enable or disable I2C scl sync
 *
 * @return None
 *
 *******************************************************************************/
void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);

  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
  }

  BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
}

/**
 * @brief  Get i2c busy state
 *
 * @param  i2cNo: I2C ID type
 *
 * @return RESET or SET
 *
 *******************************************************************************/
BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY);
  return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET);
}

/**
 * @brief  Get i2c transfer end state
 *
 * @param  i2cNo: I2C ID type
 *
 * @return RESET or SET
 *
 *******************************************************************************/
BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
  return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET);
}

/**
 * @brief  I2C master write block data
 *
 * @param  i2cNo: I2C ID type
 * @param  cfg: I2C transfer config struct
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) {
  uint8_t  i;
  uint32_t timeOut = 0;
  uint32_t temp    = 0;
  uint32_t I2Cx    = I2C_BASE;
  I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK); // This function needs to be able to use the irq status bits
  I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK); // This function needs to be able to use the irq status bits

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  I2C_Disable(i2cNo);
  I2C_Init(i2cNo, I2C_WRITE, cfg);
  I2C_Enable(i2cNo);

  /* Set I2C write data */
  for (i = 0; i < cfg->dataSize; i++) {
    temp += (cfg->data[i] << ((i % 4) * 8));

    if ((i + 1) % 4 == 0) {
      timeOut = I2C_FIFO_STATUS_TIMEOUT;

      while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {
        timeOut--;

        if (timeOut == 0) {
          I2C_Disable(i2cNo);
          return TIMEOUT;
        }
      }

      BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
      temp = 0;
    }
  }

  if ((cfg->dataSize % 4) != 0) {
    timeOut = I2C_FIFO_STATUS_TIMEOUT;

    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) {
      timeOut--;

      if (timeOut == 0) {
        I2C_Disable(i2cNo);
        return TIMEOUT;
      }
    }

    BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
  }

  timeOut = I2C_FIFO_STATUS_TIMEOUT;

  while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {
    timeOut--;

    if (timeOut == 0) {
      I2C_Disable(i2cNo);
      return TIMEOUT;
    }
  }

  I2C_Disable(i2cNo);
  return SUCCESS;
}

/**
 * @brief  I2C master read block data
 *
 * @param  i2cNo: I2C ID type
 * @param  cfg: I2C transfer config struct
 *
 * @return SUCCESS or ERROR
 *
 *******************************************************************************/
BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) {
  uint8_t  i       = 0;
  uint32_t timeOut = 0;
  uint32_t temp    = 0;
  uint32_t I2Cx    = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));

  I2C_Disable(i2cNo);
  I2C_Init(i2cNo, I2C_READ, cfg);
  I2C_Enable(i2cNo);
  I2C_IntMask(I2C0_ID, I2C_TRANS_END_INT, UNMASK); // This function needs to be able to use the irq status bits
  I2C_IntMask(I2C0_ID, I2C_NACK_RECV_INT, UNMASK); // This function needs to be able to use the irq status bits

  timeOut = I2C_FIFO_STATUS_TIMEOUT;
  if (cfg->dataSize == 0 && cfg->subAddrSize == 0) {
    while (BL_RD_REG(I2C_BASE, I2C_BUS_BUSY)) {
      timeOut--;

      if (timeOut == 0) {
        I2C_Disable(i2cNo);
        return TIMEOUT;
      }
    }

    temp = BL_RD_REG(I2C_BASE, I2C_INT_STS); // TODO this sucks as a workaround
    if (BL_IS_REG_BIT_SET(temp, I2C_NAK_INT)) {
      temp = BL_RD_REG(I2C_BASE, I2C_BUS_BUSY);
      I2C_Disable(i2cNo);
      return TIMEOUT;
    }
  }

  /* Read I2C data */
  while (cfg->dataSize - i >= 4) {
    timeOut = I2C_FIFO_STATUS_TIMEOUT;

    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {
      timeOut--;

      if (timeOut == 0) {
        I2C_Disable(i2cNo);
        return TIMEOUT;
      }
    }

    temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
    PUT_UINT32_LE(temp, cfg->data, i);
    i += 4;
  }

  if (i < cfg->dataSize) {
    timeOut = I2C_FIFO_STATUS_TIMEOUT;

    while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) {
      timeOut--;

      if (timeOut == 0) {
        I2C_Disable(i2cNo);
        return TIMEOUT;
      }
    }

    temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);

    while (i < cfg->dataSize) {
      cfg->data[i] = (temp & 0xff);
      temp         = (temp >> 8);
      i++;
    }
  }

  timeOut = I2C_FIFO_STATUS_TIMEOUT;

  while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) {
    timeOut--;

    if (timeOut == 0) {
      I2C_Disable(i2cNo);
      return TIMEOUT;
    }
  }

  I2C_Disable(i2cNo);
  return SUCCESS;
}

/**
 * @brief  Mask/Unmask the I2C interrupt
 *
 * @param  i2cNo: I2C ID type
 * @param  intType: Specifies the interrupt type
 * @param  intMask: Enable/Disable Specified interrupt type
 *
 * @return None
 *
 *******************************************************************************/
void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;
  uint32_t I2Cx = I2C_BASE;

  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
  CHECK_PARAM(IS_I2C_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);

  switch (intType) {
  case I2C_TRANS_END_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
    }

    break;

  case I2C_TX_FIFO_READY_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
    }

    break;

  case I2C_RX_FIFO_READY_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
    }

    break;

  case I2C_NACK_RECV_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
    }

    break;

  case I2C_ARB_LOST_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
    }

    break;

  case I2C_FIFO_ERR_INT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
    }

    break;

  case I2C_INT_ALL:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
    } else {
      /* MASK(Disable) this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
      tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
    }

    break;

  default:
    break;
  }

  BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
}

/**
 * @brief  Install I2C interrupt callback function
 *
 * @param  i2cNo: I2C ID type
 * @param  intType: Specifies the interrupt type
 * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
  CHECK_PARAM(IS_I2C_INT_TYPE(intType));

  i2cIntCbfArra[i2cNo][intType] = cbFun;
}
#endif

/**
 * @brief  I2C IRQ handler
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void I2C_IRQHandler(void) { I2C_IntHandler(I2C0_ID); }
#endif

/*@} end of group I2C_Public_Functions */

/*@} end of group I2C */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2c_gpio_sim.c
================================================
/**
 ******************************************************************************
 * @file    bl702_i2c_gpio_sim.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_glb.h"
#include "bl702_gpio.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2C_GPIO_SIM
 *  @{
 */

/** @defgroup  I2C_GPIO_SIM_Private_Macros
 *  @{
 */
#define SCL_H           GLB_GPIO_Write(sclPin, 1)
#define SCL_L           GLB_GPIO_Write(sclPin, 0)
#define SDA_H           GLB_GPIO_Write(sdaPin, 1)
#define SDA_L           GLB_GPIO_Write(sdaPin, 0)
#define SDA_read        GLB_GPIO_Read(sdaPin)
#define I2C_Delay_US(a) BL702_Delay_US(a)
#define I2C_Delay_Const I2C_Delay_US(2)

/*@} end of group I2C_GPIO_SIM_Private_Macros */

/** @defgroup  I2C_GPIO_SIM_Private_Types
 *  @{
 */

/*@} end of group I2C_GPIO_SIM_Private_Types */

/** @defgroup  I2C_GPIO_SIM_Private_Variables
 *  @{
 */
static GLB_GPIO_Type sclPin;
static GLB_GPIO_Type sdaPin;
static uint8_t       sda_out = 0;

/*@} end of group I2C_GPIO_SIM_Private_Variables */

/** @defgroup  I2C_GPIO_SIM_Global_Variables
 *  @{
 */

/*@} end of group I2C_GPIO_SIM_Global_Variables */

/** @defgroup  I2C_GPIO_SIM_Private_Fun_Declaration
 *  @{
 */

/*@} end of group I2C_GPIO_SIM_Private_Fun_Declaration */

/** @defgroup  I2C_GPIO_SIM_Private_Functions
 *  @{
 */

/*@} end of group I2C_GPIO_SIM_Private_Functions */

/** @defgroup  I2C_GPIO_SIM_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  I2C GPIO init function
                                                                                *
                                                                                * @param  sclGPIOPin: I2C SCL GPIO pin
                                                                                * @param  sdaGPIOPin: I2C SDA GPIO pin
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2C_GPIO_Sim_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) {
  GLB_GPIO_Cfg_Type cfg;
  uint8_t           gpiopins[2];
  uint8_t           gpiofuns[2];
  size_t            i;

  sclPin = sclGPIOPin;
  sdaPin = sdaGPIOPin;

  cfg.pullType = GPIO_PULL_UP;
  cfg.drive    = 1;
  cfg.smtCtrl  = 1;
  cfg.gpioMode = GPIO_MODE_OUTPUT;

  gpiopins[0] = sclPin;
  gpiopins[1] = sdaPin;
  gpiofuns[0] = 11;
  gpiofuns[1] = 11;

  for (i = 0; i < sizeof(gpiopins) / sizeof(gpiopins[0]); i++) {
    cfg.gpioPin = gpiopins[i];
    cfg.gpioFun = gpiofuns[i];
    GLB_GPIO_Init(&cfg);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  I2C SDA out function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void I2C_SDA_OUT(void) {
  GLB_GPIO_Cfg_Type cfg;

  if (sda_out == 1) {
    return;
  }

  cfg.pullType = GPIO_PULL_UP;
  cfg.drive    = 1;
  cfg.smtCtrl  = 1;
  cfg.gpioMode = GPIO_MODE_OUTPUT;
  cfg.gpioPin  = sdaPin;
  cfg.gpioFun  = 11;

  GLB_GPIO_Init(&cfg);

  sda_out = 1;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C SDA in function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void I2C_SDA_IN(void) {
  GLB_GPIO_Cfg_Type cfg;

  if (sda_out == 0) {
    return;
  }

  cfg.pullType = GPIO_PULL_UP;
  cfg.drive    = 1;
  cfg.smtCtrl  = 1;
  cfg.gpioMode = GPIO_MODE_INPUT;
  cfg.gpioPin  = sdaPin;
  cfg.gpioFun  = 11;

  GLB_GPIO_Init(&cfg);

  sda_out = 0;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C start function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2C_Start(void) {
  I2C_SDA_OUT();
  SDA_H;
  I2C_Delay_Const;
  SCL_H;
  I2C_Delay_Const;
  SDA_L;
  I2C_Delay_Const;
  SCL_L;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C stop function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2C_Stop(void) {
  I2C_SDA_OUT();
  SCL_L;
  I2C_Delay_Const;
  SDA_L;
  I2C_Delay_Const;
  SCL_H;
  I2C_Delay_Const;
  SDA_H;
  I2C_Delay_Const;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C ack function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void I2C_Ack(void) {
  SCL_L;
  I2C_Delay_Const;
  I2C_SDA_OUT();
  SDA_L;
  I2C_Delay_Const;
  SCL_H;
  I2C_Delay_Const;
  SCL_L;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C no ack function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void I2C_NoAck(void) {
  SCL_L;
  I2C_Delay_Const;
  I2C_SDA_OUT();
  SDA_H;
  I2C_Delay_Const;
  SCL_H;
  I2C_Delay_Const;
  SCL_L;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C get ack function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
uint8_t I2C_GetAck(void) {
  uint8_t time = 0;

  I2C_Delay_Const;
  I2C_SDA_IN();

  I2C_Delay_Const;
  SCL_H;
  I2C_Delay_Const;

  while (SDA_read) {
    time++;

    if (time > 25) {
      SCL_L;
      return 0;
    }
  }

  SCL_L;

  return 1;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C send byte function
                                                                                *
                                                                                * @param  Data: send data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2C_SendByte(uint8_t Data) {
  uint8_t cnt;

  I2C_SDA_OUT();

  for (cnt = 0; cnt < 8; cnt++) {
    SCL_L;
    I2C_Delay_Const;

    if (Data & 0x80) {
      SDA_H;
    } else {
      SDA_L;
    }

    Data <<= 1;
    I2C_Delay_Const;
    SCL_H;
    I2C_Delay_Const;
  }

  SCL_L;

  I2C_Delay_Const;
}

/****************************************************************************/ /**
                                                                                * @brief  I2C read byte function
                                                                                *
                                                                                * @param  ack: i2c ack byte
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
uint8_t I2C_ReadByte(uint8_t ack) {
  uint8_t cnt;
  uint8_t data = 0;

  I2C_SDA_IN();

  for (cnt = 0; cnt < 8; cnt++) {
    SCL_L;
    I2C_Delay_Const;

    SCL_H;
    I2C_Delay_Const;
    data <<= 1;

    if (SDA_read) {
      data |= 0x01;
    }
  }

  if (ack == 1) {
    I2C_Ack();
  } else {
    I2C_NoAck();
  }

  return data;
}

/****************************************************************************/ /**
                                                                                * @brief  SCCB init function
                                                                                *
                                                                                * @param  sclGPIOPin: I2C SCL GPIO pin
                                                                                * @param  sdaGPIOPin: I2C SDA GPIO pin
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
int SCCB_Init(GLB_GPIO_Type sclGPIOPin, GLB_GPIO_Type sdaGPIOPin) {
  I2C_GPIO_Sim_Init(sclGPIOPin, sdaGPIOPin);
  return 0;
}

/****************************************************************************/ /**
                                                                                * @brief  SCCB write function
                                                                                *
                                                                                * @param  slave_addr: salve addr
                                                                                * @param  data: write data
                                                                                * @param  wrsize: write data len
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
int SCCB_Write(uint8_t slave_addr, uint8_t *data, uint32_t wrsize) {
  uint32_t i = 0;

  I2C_Start();

  I2C_SendByte((slave_addr << 1) | 0);

  if (!I2C_GetAck()) {
    I2C_Stop();
    return -1;
  }

  for (i = 0; i < wrsize; i++) {
    I2C_SendByte(data[i]);

    if (!I2C_GetAck()) {
      I2C_Stop();
      return -1;
    }
  }

  I2C_Stop();

  return 0;
}

/****************************************************************************/ /**
                                                                                * @brief  SCCB read function
                                                                                *
                                                                                * @param  slave_addr: salve addr
                                                                                * @param  data: read data
                                                                                * @param  rdsize: read data len
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
int SCCB_Read(uint8_t slave_addr, uint8_t *data, uint32_t rdsize) {
  uint32_t i = 0;

  if (0 == rdsize) {
    return -1;
  }

  I2C_Start();

  I2C_SendByte((slave_addr << 1) | 1);

  if (!I2C_GetAck()) {
    I2C_Stop();
    return -1;
  }

  for (i = 0; i < rdsize - 1; i++) {
    data[i] = I2C_ReadByte(1);
  }

  data[i] = I2C_ReadByte(0);

  I2C_Stop();

  return 0;
}

/*@} end of group I2C_GPIO_SIM_Public_Functions */

/*@} end of group I2C_GPIO_SIM */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_i2s.c
================================================
/**
 ******************************************************************************
 * @file    bl702_i2s.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_i2s.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  I2S
 *  @{
 */

/** @defgroup  I2S_Private_Macros
 *  @{
 */

/*@} end of group I2S_Private_Macros */

/** @defgroup  I2S_Private_Types
 *  @{
 */

/*@} end of group I2S_Private_Types */

/** @defgroup  I2S_Private_Variables
 *  @{
 */

/*@} end of group I2S_Private_Variables */

/** @defgroup  I2S_Global_Variables
 *  @{
 */

/*@} end of group I2S_Global_Variables */

/** @defgroup  I2S_Private_Fun_Declaration
 *  @{
 */

/*@} end of group I2S_Private_Fun_Declaration */

/** @defgroup  I2S_Private_Functions
 *  @{
 */

/*@} end of group I2S_Private_Functions */

/** @defgroup  I2S_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  I2S BCLK config
                                                                                *
                                                                                * @param  i2sCfg: I2S configuration pointer
                                                                                *
                                                                                * @return NONE
                                                                                *
                                                                                *******************************************************************************/
void I2S_SetBclkPeriod(I2S_CFG_Type *i2sCfg) {
  uint32_t overSampleRate;
  uint32_t bclkDivCnt;
  uint32_t tmpVal;

  CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));

  overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz;

  switch (i2sCfg->frameSize) {
  case I2S_SIZE_FRAME_8:
    bclkDivCnt = overSampleRate / 16;
    break;

  case I2S_SIZE_FRAME_16:
    bclkDivCnt = overSampleRate / 32;
    break;

  case I2S_SIZE_FRAME_24:
    bclkDivCnt = overSampleRate / 48;
    break;

  case I2S_SIZE_FRAME_32:
    bclkDivCnt = overSampleRate / 64;
    break;

  default:
    bclkDivCnt = overSampleRate / 16;
    break;
  }

  bclkDivCnt = (bclkDivCnt / 2) - 1;

  tmpVal = (bclkDivCnt << 16) | bclkDivCnt;
  BL_WR_REG(I2S_BASE, I2S_BCLK_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S configuration
                                                                                *
                                                                                * @param  i2sCfg: I2S configuration pointer
                                                                                *
                                                                                * @return NONE
                                                                                *
                                                                                *******************************************************************************/
void I2S_Init(I2S_CFG_Type *i2sCfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType));
  CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType));
  CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize));
  CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode));
  CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel));
  CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize));
  CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_I2S);

  tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);

  /* Set data endian*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType);

  /* Set I2S mode */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType);

  /* Set BCLK invert */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert);

  /* Set FS size */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize);

  /* Set FS invert */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert);

  /* Set FS mode */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode);

  /* Set FS channel mode */

  switch (i2sCfg->fsChannel) {
  case I2S_FS_CHANNELS_2:
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
    break;

  case I2S_FS_CHANNELS_3:
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
    break;

  case I2S_FS_CHANNELS_4:
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_FS_3CH_MODE);
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_FS_4CH_MODE);
    break;

  default:
    break;
  }

  /* Set Data size */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize);

  /* Set Data offset */
  if (i2sCfg->dataOffset != 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN);
  }

  /* Set mono mode */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode);

  /* Set rx mono mode channel left or right */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel);

  /* Clear mute mode */
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);

  BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);

  I2S_SetBclkPeriod(i2sCfg);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S configure FIFO function
                                                                                *
                                                                                * @param  fifoCfg: FIFO configuration structure pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_FifoConfig(I2S_FifoCfg_Type *fifoCfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0);
  /* Set packed mode */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange);
  /* Clear tx and rx FIFO signal */
  tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);

  /* Set DMA config */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable);

  BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);

  /* Set CLR signal to 0*/
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR);
  BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);

  tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1);
  /* Set TX and RX FIFO threshold */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel);

  BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_1, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S configure IO function
                                                                                *
                                                                                * @param  ioCfg: IO configuration structure pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_IOConfig(I2S_IOCfg_Type *ioCfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(I2S_BASE, I2S_IO_CONFIG);
  /* Enable or disable deglitch */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn);

  /* Set deglitch cycle count */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt);

  /* Enable or disable inverse BCLK signal */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK);

  /* Enable or disable inverse FS signal */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS);

  /* Enable or disable inverse RX signal */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX);

  /* Enable or disable inverse TX signal */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX);

  BL_WR_REG(I2S_BASE, I2S_IO_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable I2S
                                                                                *
                                                                                * @param  roleType: I2S master or slave
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_Enable(I2S_Role_Type roleType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType));

  tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);

  /* Set role type */
  if (I2S_ROLE_MASTER == roleType) {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
  } else if (I2S_ROLE_SLAVE == roleType) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
  }

  BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable I2S
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN);

  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN);
  BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S read data
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Data read
                                                                                *
                                                                                *******************************************************************************/
uint32_t I2S_Read(void) {
  while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) {
  };

  return BL_RD_REG(I2S_BASE, I2S_FIFO_RDATA);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S write data
                                                                                *
                                                                                * @param  data: write data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_Write(uint32_t data) {
  while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) {
  };

  BL_WR_REG(I2S_BASE, I2S_FIFO_WDATA, data);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S set mute
                                                                                *
                                                                                * @param  enabled: mute enabled or not
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_Mute(BL_Fun_Type enabled) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(I2S_BASE, I2S_CONFIG);

  if (enabled ? 1 : 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE);
  }

  BL_WR_REG(I2S_BASE, I2S_CONFIG, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S set 24-bit data align mode in fifo
                                                                                *
                                                                                * @param  justType: Align mode
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_SetFifoJustified(I2S_FIFO_24_Justified_Type justType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType));

  tmpVal = BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType);
  BL_WR_REG(I2S_BASE, I2S_FIFO_CONFIG_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  I2S flush
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return data count in TX FIFO
                                                                                *
                                                                                *******************************************************************************/
uint32_t I2S_GetTxFIFO_AvlCnt(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT); }

/****************************************************************************/ /**
                                                                                * @brief  I2S flush
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return data count in RX FIFO
                                                                                *
                                                                                *******************************************************************************/
uint32_t I2S_GetRxFIFO_AvlCnt(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(I2S_BASE, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT); }

/****************************************************************************/ /**
                                                                                * @brief  I2S flush
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void I2S_Flush(void) {
  while (I2S_TX_FIFO_SIZE != I2S_GetTxFIFO_AvlCnt())
    ;
}

/*@} end of group I2S_Public_Functions */

/*@} end of group I2S */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_ir.c
================================================
/**
 ******************************************************************************
 * @file    bl702_ir.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_ir.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  IR
 *  @{
 */

/** @defgroup  IR_Private_Macros
 *  @{
 */
#define NEC_HEAD_H_MIN          17000
#define NEC_HEAD_H_MAX          19000
#define NEC_HEAD_L_MIN          8400
#define NEC_HEAD_L_MAX          9600
#define NEC_BIT0_H_MIN          525
#define NEC_BIT0_H_MAX          1725
#define RC5_ONE_PLUSE_MIN       1175
#define RC5_ONE_PLUSE_MAX       2375
#define RC5_TWO_PLUSE_MIN       2955
#define RC5_TWO_PLUSE_MAX       4155
#define IR_TX_INT_TIMEOUT_COUNT (100 * 160 * 1000)
#define IR_RX_INT_TIMEOUT_COUNT (100 * 160 * 1000)

/*@} end of group IR_Private_Macros */

/** @defgroup  IR_Private_Types
 *  @{
 */

/*@} end of group IR_Private_Types */

/** @defgroup  IR_Private_Variables
 *  @{
 */
static intCallback_Type *irIntCbfArra[IR_INT_ALL] = {NULL, NULL};

/*@} end of group IR_Private_Variables */

/** @defgroup  IR_Global_Variables
 *  @{
 */

/*@} end of group IR_Global_Variables */

/** @defgroup  IR_Private_Fun_Declaration
 *  @{
 */

/*@} end of group IR_Private_Fun_Declaration */

/** @defgroup  IR_Private_Functions
 *  @{
 */

/*@} end of group IR_Private_Functions */

/** @defgroup  IR_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  IR RX IRQ handler function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void IRRX_IRQHandler(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);

  if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) {
    BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));

    if (irIntCbfArra[IR_INT_RX] != NULL) {
      irIntCbfArra[IR_INT_RX]();
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  IR TX IRQ handler function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void IRTX_IRQHandler(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);

  if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) {
    BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));

    if (irIntCbfArra[IR_INT_TX] != NULL) {
      irIntCbfArra[IR_INT_TX]();
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  IR tx initialization function
                                                                                *
                                                                                * @param  irTxCfg: IR tx configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) {
  uint32_t tmpVal;

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);

  tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
  /* Set data bit */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1);
  /* Set tail pulse */
  ENABLE == irTxCfg->tailPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_HL_INV));
  ENABLE == irTxCfg->tailPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_TAIL_EN));
  /* Set head pulse */
  ENABLE == irTxCfg->headPulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_HL_INV));
  ENABLE == irTxCfg->headPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_HEAD_EN));
  /* Enable or disable logic 1 and 0 pulse inverse */
  ENABLE == irTxCfg->logic1PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV));
  ENABLE == irTxCfg->logic0PulseInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV));
  /* Enable or disable data pulse */
  ENABLE == irTxCfg->dataPulse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_DATA_EN));
  /* Enable or disable output modulation */
  ENABLE == irTxCfg->outputModulation ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_MOD_EN));
  /* Enable or disable output inverse */
  ENABLE == irTxCfg->outputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_OUT_INV));

  /* Write back */
  BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler);
#endif
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR tx pulse width configure function
                                                                                *
                                                                                * @param  irTxPulseWidthCfg: IR tx pulse width configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(IR_BASE, IRTX_PW);
  /* Set logic 0 pulse phase 0 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1);
  /* Set logic 0 pulse phase 1 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1);
  /* Set logic 1 pulse phase 0 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1);
  /* Set logic 1 pulse phase 1 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1);
  /* Set head pulse phase 0 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1);
  /* Set head pulse phase 1 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1);
  /* Set tail pulse phase 0 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1);
  /* Set tail pulse phase 1 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1);
  BL_WR_REG(IR_BASE, IRTX_PW, tmpVal);

  tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);
  /* Set modulation phase 0 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1);
  /* Set modulation phase 1 width */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1);
  /* Set pulse width unit */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1);
  BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR tx software mode pulse width(multiples of pulse width unit) configure function
                                                                                *
                                                                                * @param  irTxSWMPulseWidthCfg: IR tx software mode pulse width configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg) {
  /* Set swm pulse width,multiples of pulse width unit */
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_0, irTxSWMPulseWidthCfg->swmData0);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_1, irTxSWMPulseWidthCfg->swmData1);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_2, irTxSWMPulseWidthCfg->swmData2);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_3, irTxSWMPulseWidthCfg->swmData3);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_4, irTxSWMPulseWidthCfg->swmData4);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_5, irTxSWMPulseWidthCfg->swmData5);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_6, irTxSWMPulseWidthCfg->swmData6);
  BL_WR_REG(IR_BASE, IRTX_SWM_PW_7, irTxSWMPulseWidthCfg->swmData7);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR rx initialization function
                                                                                *
                                                                                * @param  irRxCfg: IR rx configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);

  tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);

  /* Set rx mode */
  switch (irRxCfg->rxMode) {
  case IR_RX_NEC:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0);
    break;

  case IR_RX_RC5:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1);
    break;

  case IR_RX_SWM:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);
    break;

  default:
    break;
  }

  /* Enable or disable input inverse */
  ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV));
  /* Enable or disable rx input de-glitch function */
  ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN));
  /* Set de-glitch function cycle count */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt);
  /* Write back */
  BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);

  tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);
  /* Set pulse width threshold to trigger end condition */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1);
  /* Set pulse width threshold for logic0/1 detection */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1);
  /* Write back */
  BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR set default value of all registers function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_DeInit(void) {
  GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_IRR);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR enable function
                                                                                *
                                                                                * @param  direct: IR direction type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_Enable(IR_Direction_Type direct) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));

  if (direct == IR_TX || direct == IR_TXRX) {
    /* Enable ir tx unit */
    tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
    BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN));
  }

  if (direct == IR_RX || direct == IR_TXRX) {
    /* Enable ir rx unit */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR disable function
                                                                                *
                                                                                * @param  direct: IR direction type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_Disable(IR_Direction_Type direct) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct));

  if (direct == IR_TX || direct == IR_TXRX) {
    /* Disable ir tx unit */
    tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
    BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN));
  }

  if (direct == IR_RX || direct == IR_TXRX) {
    /* Disable ir rx unit */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR tx software mode enable or disable function
                                                                                *
                                                                                * @param  txSWM: Enable or disable
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) {
  uint32_t tmpVal;

  /* Enable or disable tx swm */
  tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);

  if (ENABLE == txSWM) {
    BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));
  } else {
    BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR clear rx fifo function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_RxFIFOClear(void) {
  uint32_t tmpVal;

  /* Clear rx fifo */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);
  BL_WR_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send data function
                                                                                *
                                                                                * @param  irWord: IR tx data word 0 or 1
                                                                                * @param  data: data to send
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_SendData(IR_Word_Type irWord, uint32_t data) {
  /* Check the parameters */
  CHECK_PARAM(IS_IR_WORD_TYPE(irWord));

  /* Write word 0 or word 1 */
  if (IR_WORD_0 == irWord) {
    BL_WR_REG(IR_BASE, IRTX_DATA_WORD0, data);
  } else {
    BL_WR_REG(IR_BASE, IRTX_DATA_WORD1, data);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR software mode send pulse width data function
                                                                                *
                                                                                * @param  data: data to send
                                                                                * @param  length: Length of send buffer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length) {
  uint8_t  i = 0, j = 0;
  uint16_t minData = data[0];
  uint32_t tmpVal;
  uint32_t pwVal = 0;
  uint32_t count = (length + 7) / 8;

  /* Search for min value */
  for (i = 1; i < length; i++) {
    if (minData > data[i] && data[i] != 0) {
      minData = data[i];
    }
  }

  /* Set pulse width unit */
  tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH);
  BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData));

  /* Set tx SWM pulse width data as multiples of pulse width unit */
  for (i = 0; i < count; i++) {
    pwVal = 0;

    if (i < count - 1) {
      for (j = 0; j < 8; j++) {
        tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf;
        pwVal |= tmpVal << (4 * j);
      }

      *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal;
    } else {
      for (j = 0; j < length % 8; j++) {
        tmpVal = ((2 * data[j + i * 8] + minData) / (2 * minData) - 1) & 0xf;
        pwVal |= tmpVal << (4 * j);
      }

      *(volatile uint32_t *)(IR_BASE + IRTX_SWM_PW_0_OFFSET + i * 4) = pwVal;
    }
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send command function
                                                                                *
                                                                                * @param  word1: IR send data word 1
                                                                                * @param  word0: IR send data word 0
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_SendCommand(uint32_t word1, uint32_t word0) {
  uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;

  /* Write data */
  IR_SendData(IR_WORD_1, word1);
  IR_SendData(IR_WORD_0, word0);

  /* Mask tx interrupt */
  IR_IntMask(IR_INT_TX, MASK);

  /* Clear tx interrupt */
  IR_ClrIntStatus(IR_INT_TX);

  /* Enable ir tx */
  IR_Enable(IR_TX);

  /* Wait for tx interrupt */
  while (SET != IR_GetIntStatus(IR_INT_TX)) {
    timeoutCnt--;

    if (timeoutCnt == 0) {
      IR_Disable(IR_TX);

      return TIMEOUT;
    }
  }

  /* Disable ir tx */
  IR_Disable(IR_TX);

  /* Clear tx interrupt */
  IR_ClrIntStatus(IR_INT_TX);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send command in software mode function
                                                                                *
                                                                                * @param  data: IR fifo data to send
                                                                                * @param  length: Length of data
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length) {
  uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT;

  /* Write fifo */
  IR_SWMSendData(data, length);

  /* Mask tx interrupt */
  IR_IntMask(IR_INT_TX, MASK);

  /* Clear tx interrupt */
  IR_ClrIntStatus(IR_INT_TX);

  /* Enable ir tx */
  IR_Enable(IR_TX);

  /* Wait for tx interrupt */
  while (SET != IR_GetIntStatus(IR_INT_TX)) {
    timeoutCnt--;

    if (timeoutCnt == 0) {
      IR_Disable(IR_TX);

      return TIMEOUT;
    }
  }

  /* Disable ir tx */
  IR_Disable(IR_TX);

  /* Clear tx interrupt */
  IR_ClrIntStatus(IR_INT_TX);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send in NEC protocol
                                                                                *
                                                                                * @param  address: Address
                                                                                * @param  command: Command
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command) {
  uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address;

  IR_SendCommand(0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR interrupt mask or unmask function
                                                                                *
                                                                                * @param  intType: IR interrupt type
                                                                                * @param  intMask: Mask or unmask
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_INT_TYPE(intType));

  if (intType == IR_INT_TX || intType == IR_INT_ALL) {
    /* Mask or unmask tx interrupt */
    tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
    BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_END_MASK, intMask));
  }

  if (intType == IR_INT_RX || intType == IR_INT_ALL) {
    /* Mask or unmask rx interrupt */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
    BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_MASK, intMask));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear ir interrupt function
                                                                                *
                                                                                * @param  intType: IR interrupt type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_INT_TYPE(intType));

  if (intType == IR_INT_TX || intType == IR_INT_ALL) {
    /* Clear tx interrupt */
    tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
    BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR));
  }

  if (intType == IR_INT_RX || intType == IR_INT_ALL) {
    /* Clear rx interrupt */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
    BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR install interrupt callback function
                                                                                *
                                                                                * @param  intType: IR interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_IR_INT_TYPE(intType));

  irIntCbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR get interrupt status function
                                                                                *
                                                                                * @param  intType: IR int type
                                                                                *
                                                                                * @return IR tx or rx interrupt status
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType) {
  uint32_t tmpVal = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_INT_TYPE(intType));

  /* Read tx or rx interrupt status */
  if (IR_INT_TX == intType) {
    tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRTX_END_INT);
  } else if (IR_INT_RX == intType) {
    tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IRRX_END_INT);
  }

  if (tmpVal) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  IR get rx fifo underflow or overflow status function
                                                                                *
                                                                                * @param  fifoSts: IR fifo status type
                                                                                *
                                                                                * @return IR rx fifo status
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts));

  /* Read rx fifo status */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);

  if (fifoSts == IR_RX_FIFO_UNDERFLOW) {
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_UNDERFLOW);
  } else {
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_OVERFLOW);
  }

  if (tmpVal) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  IR receive data function
                                                                                *
                                                                                * @param  irWord: IR rx data word 0 or 1
                                                                                *
                                                                                * @return Data received
                                                                                *
                                                                                *******************************************************************************/
uint32_t IR_ReceiveData(IR_Word_Type irWord) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_WORD_TYPE(irWord));

  /* Read word 0 or word 1 */
  if (IR_WORD_0 == irWord) {
    tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0);
  } else {
    tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1);
  }

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  IR software mode receive pulse width data function
                                                                                *
                                                                                * @param  data: Data received
                                                                                * @param  length: Max length of receive buffer
                                                                                *
                                                                                * @return Length of datas received
                                                                                *
                                                                                *******************************************************************************/
uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length) {
  uint8_t rxLen = 0;

  while (rxLen < length && IR_GetRxFIFOCount() > 0) {
    /* Read data */
    data[rxLen++] = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_RDATA) & 0xffff;
  }

  return rxLen;
}

/****************************************************************************/ /**
                                                                                * @brief  IR receive in NEC protocol
                                                                                *
                                                                                * @param  address: Address
                                                                                * @param  command: Command
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command) {
  uint32_t tmpVal = IR_ReceiveData(IR_WORD_0);

  *address = tmpVal & 0xff;
  *command = (tmpVal >> 16) & 0xff;

  if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) {
    return ERROR;
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR get rx data bit count function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return IR rx data bit count
                                                                                *
                                                                                *******************************************************************************/
uint8_t IR_GetRxDataBitCount(void) {
  uint32_t tmpVal;

  /* Read rx data bit count */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT);
  tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT);

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  IR get rx fifo count function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return IR rx fifo available count
                                                                                *
                                                                                *******************************************************************************/
uint8_t IR_GetRxFIFOCount(void) {
  uint32_t tmpVal;

  /* Read rx fifo count */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_SWM_FIFO_CONFIG_0);
  tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT);

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  IR learning to set rx and tx mode function
                                                                                *
                                                                                * @param  data: Buffer to save data
                                                                                * @param  length: Length of data
                                                                                *
                                                                                * @return Protocol type
                                                                                *
                                                                                *******************************************************************************/
IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length) {
  uint32_t tmpVal;
  uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_IRR);

  /* Disable rx,set rx in software mode and enable rx input inverse */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2);
  tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV);
  BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal);
  /* Set pulse width threshold to trigger end condition */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG);
  BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999));

  /* Clear and mask rx interrupt */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
  tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK);
  BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));

  /* Enable rx */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
  BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN));

  /* Wait for rx interrupt */
  while (SET != IR_GetIntStatus(IR_INT_RX)) {
    timeoutCnt--;

    if (timeoutCnt == 0) {
      IR_Disable(IR_RX);

      return IR_RX_SWM;
    }
  }

  /* Disable rx */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
  BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN));

  /* Clear rx interrupt */
  tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS);
  BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR));

  /*Receive data */
  *length = IR_GetRxFIFOCount();
  *length = IR_SWMReceiveData((uint16_t *)data, *length);

  /* Judge protocol type */
  if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) &&
      (data[1] & 0xffff) < NEC_BIT0_H_MAX) {
    /* Set rx in NEC mode */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0));
    /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */
    BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47);
    /* Set tx in NEC mode */
    /* Tx configure */
    BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1f514);
    /* Set logic 0,logic 1,head and tail pulse width */
    BL_WR_REG(IR_BASE, IRTX_PW, 0x7f2000);
    /* Set modulation phase width and pulse width unit */
    BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464);

    return IR_RX_NEC;
  } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX &&
             ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) &&
             ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) {
    /* Set rx in RC-5 mode */
    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
    BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1));
    /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */
    BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a);
    /* Set tx in RC-5 mode */
    /* Tx configure */
    BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xc134);
    /* Set logic 0,logic 1,head and tail pulse width */
    BL_WR_REG(IR_BASE, IRTX_PW, 0);
    /* Set modulation phase width and pulse width unit */
    BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1);

    return IR_RX_RC5;
  } else if ((data[0] >> 16) != 0) {
    /* Set tx in software mode */
    /* Tx configure */
    BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 12 | 0xc);
    /* Set modulation phase width */
    BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000);

    return IR_RX_SWM;
  } else {
    tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE);

    if (tmpVal == 0) {
      return IR_RX_NEC;
    } else if (tmpVal == 1) {
      return IR_RX_RC5;
    } else {
      return IR_RX_SWM;
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  IR receive data according to mode which is learned function
                                                                                *
                                                                                * @param  mode: Protocol type
                                                                                * @param  data: Buffer to save data
                                                                                *
                                                                                * @return Length of data
                                                                                *
                                                                                *******************************************************************************/
uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data) {
  uint8_t  length     = 0;
  uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));

  /* Disable ir rx */
  IR_Disable(IR_RX);

  /* Clear and mask rx interrupt */
  IR_ClrIntStatus(IR_INT_RX);
  IR_IntMask(IR_INT_RX, MASK);

  /* Enable ir rx */
  IR_Enable(IR_RX);

  /* Wait for rx interrupt */
  while (SET != IR_GetIntStatus(IR_INT_RX)) {
    timeoutCnt--;

    if (timeoutCnt == 0) {
      IR_Disable(IR_RX);

      return TIMEOUT;
    }
  }

  /* Disable ir rx */
  IR_Disable(IR_RX);

  /* Clear rx interrupt */
  IR_ClrIntStatus(IR_INT_RX);

  /* Receive data according to mode */
  if (mode == IR_RX_NEC || mode == IR_RX_RC5) {
    /* Get data bit count */
    length  = IR_GetRxDataBitCount();
    data[0] = IR_ReceiveData(IR_WORD_0);
  } else {
    /* Get fifo count */
    length = IR_GetRxFIFOCount();
    length = IR_SWMReceiveData((uint16_t *)data, length);
  }

  return length;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send data according to mode which is learned function
                                                                                *
                                                                                * @param  mode: Protocol type
                                                                                * @param  data: Buffer of data to send
                                                                                * @param  length: Length of data
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_IR_RXMODE_TYPE(mode));

  /* Set send length */
  tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1);
  BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal);

  if (mode == IR_RX_NEC || mode == IR_RX_RC5) {
    IR_SendCommand(0, data[0]);
  } else {
    IR_SWMSendCommand((uint16_t *)data, length);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR init to control led function
                                                                                *
                                                                                * @param  clk: Clock source
                                                                                * @param  div: Clock division(1~64)
                                                                                * @param  unit: Pulse width unit(multiples of clock pulse width, 1~4096)
                                                                                * @param  code0H: code 0 high level time(multiples of pulse width unit, 1~16)
                                                                                * @param  code0L: code 0 low level time(multiples of pulse width unit, 1~16)
                                                                                * @param  code1H: code 1 high level time(multiples of pulse width unit, 1~16)
                                                                                * @param  code1L: code 1 low level time(multiples of pulse width unit, 1~16)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_LEDInit(HBN_XCLK_CLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L) {
  IR_TxCfg_Type txCfg = {
      24,      /* 24-bit data */
      DISABLE, /* Disable signal of tail pulse inverse */
      DISABLE, /* Disable signal of tail pulse */
      DISABLE, /* Disable signal of head pulse inverse */
      DISABLE, /* Disable signal of head pulse */
      DISABLE, /* Disable signal of logic 1 pulse inverse */
      DISABLE, /* Disable signal of logic 0 pulse inverse */
      ENABLE,  /* Enable signal of data pulse */
      DISABLE, /* Disable signal of output modulation */
      ENABLE   /* Enable signal of output inverse */
  };

  IR_TxPulseWidthCfg_Type txPWCfg = {
      code0L, /* Pulse width of logic 0 pulse phase 1 */
      code0H, /* Pulse width of logic 0 pulse phase 0 */
      code1L, /* Pulse width of logic 1 pulse phase 1 */
      code1H, /* Pulse width of logic 1 pulse phase 0 */
      1,      /* Pulse width of head pulse phase 1 */
      1,      /* Pulse width of head pulse phase 0 */
      1,      /* Pulse width of tail pulse phase 1 */
      1,      /* Pulse width of tail pulse phase 0 */
      1,      /* Modulation phase 1 width */
      1,      /* Modulation phase 0 width */
      unit    /* Pulse width unit */
  };

  HBN_Set_XCLK_CLK_Sel(clk);
  GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1);

  /* Disable ir before config */
  IR_Disable(IR_TXRX);

  /* IR tx init */
  IR_TxInit(&txCfg);
  IR_TxPulseWidthConfig(&txPWCfg);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  IR send 24-bit data to control led function
                                                                                *
                                                                                * @param  data: Data to send(24-bit)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type IR_LEDSend(uint32_t data) {
  /* Change MSB_first to LSB_first */
  data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa);
  data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc);
  data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0);
  data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000);
  IR_SendCommand(0, data);

  return SUCCESS;
}

/*@} end of group IR_Public_Functions */

/*@} end of group IR */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_kys.c
================================================
/**
 ******************************************************************************
 * @file    bl702_kys.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_kys.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  KYS
 *  @{
 */

/** @defgroup  KYS_Private_Macros
 *  @{
 */

/*@} end of group KYS_Private_Macros */

/** @defgroup  KYS_Private_Types
 *  @{
 */

/*@} end of group KYS_Private_Types */

/** @defgroup  KYS_Private_Variables
 *  @{
 */
static intCallback_Type *KYSIntCbfArra[1] = {NULL};

/*@} end of group KYS_Private_Variables */

/** @defgroup  KYS_Global_Variables
 *  @{
 */

/*@} end of group KYS_Global_Variables */

/** @defgroup  KYS_Private_Fun_Declaration
 *  @{
 */

/*@} end of group KYS_Private_Fun_Declaration */

/** @defgroup  KYS_Private_Functions
 *  @{
 */

/*@} end of group KYS_Private_Functions */

/** @defgroup  KYS_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  KYS interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void KYS_IRQHandler(void) {
  if (KYSIntCbfArra[0] != NULL) {
    KYSIntCbfArra[0]();
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  KYS initialization function
                                                                                *
                                                                                * @param  kysCfg: KYS configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
  /* Set col and row */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, kysCfg->col - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, kysCfg->row - 1);

  /* Set idle duration between column scans */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, kysCfg->idleDuration);

  /* Enable or disable ghost key event detection */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, kysCfg->ghostEn);

  /* Enable or disable deglitch function */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, kysCfg->deglitchEn);

  /* Set deglitch count */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, kysCfg->deglitchCnt);

  /* Write back */
  BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(KYS_IRQn, KYS_IRQHandler);
#endif
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable KYS
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
  BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable KYS
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
  BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  KYS mask or unmask interrupt
                                                                                *
                                                                                * @param  intMask: KYS interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_IntMask(BL_Mask_Type intMask) {
  if (MASK == intMask) {
    BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 0);
  } else {
    BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, 1);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  KYS clear interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_IntClear(void) {
  BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, 0xf);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Install KYS interrupt callback function
                                                                                *
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type KYS_Int_Callback_Install(intCallback_Type *cbFun) {
  KYSIntCbfArra[0] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  KYS get interrupt status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Status of interrupt
                                                                                *
                                                                                *******************************************************************************/
uint8_t KYS_GetIntStatus(void) { return BL_RD_REG(KYS_BASE, KYS_KS_INT_STS) & 0xf; }

/****************************************************************************/ /**
                                                                                * @brief  KYS get keycode value
                                                                                *
                                                                                * @param  keycode: KYS keycode type
                                                                                * @param  col: Col of key
                                                                                * @param  row: Row of key
                                                                                *
                                                                                * @return Keycode value
                                                                                *
                                                                                *******************************************************************************/
uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row) {
  uint32_t tmpVal;
  uint8_t  keyValue;

  /* Get keycode value */
  keyValue = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE) >> (8 * keycode) & 0xff;

  /* Get total row number of keyboard */
  tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL);
  tmpVal = BL_GET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM);

  /* Calculate col and row of the key */
  *col = keyValue / (tmpVal + 1);
  *row = keyValue % (tmpVal + 1);

  return keyValue;
}

/*@} end of group KYS_Public_Functions */

/*@} end of group KYS */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_l1c.c
================================================
/**
 ******************************************************************************
 * @file    bl702_l1c.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_l1c.h"
#include "bl702_common.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  L1C
 *  @{
 */

/** @defgroup  L1C_Private_Macros
 *  @{
 */

/*@} end of group L1C_Private_Macros */

/** @defgroup  L1C_Private_Types
 *  @{
 */

/*@} end of group L1C_Private_Types */

/** @defgroup  L1C_Private_Variables
 *  @{
 */
static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = {NULL};
static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL]   = {NULL};

/*@} end of group L1C_Private_Variables */

/** @defgroup  L1C_Global_Variables
 *  @{
 */

/*@} end of group L1C_Global_Variables */

/** @defgroup  L1C_Private_Fun_Declaration
 *  @{
 */

/*@} end of group L1C_Private_Fun_Declaration */

/** @defgroup  L1C_Private_Functions
 *  @{
 */

/*@} end of group L1C_Private_Functions */

/** @defgroup  L1C_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Enable cache
                                                                                *
                                                                                * @param  wayDisable: cache way disable config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable) {
  L1C_Cache_Flush(wayDisable);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  L1C cache write set
                                                                                *
                                                                                * @param  wtEn: L1C write through enable
                                                                                * @param  wbEn: L1C write back enable
                                                                                * @param  waEn: L1C write allocate enable
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);

  if (wtEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
  }

  if (wbEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
  }

  if (waEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
  }

  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Flush cache
                                                                                *
                                                                                * @param  wayDisable: cache way disable config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable) {
  uint32_t tmpVal;
  uint32_t cnt           = 0;
  uint8_t  finWayDisable = 0;

  tmpVal        = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal        = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
  tmpVal        = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
  tmpVal        = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
  tmpVal        = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN);
  finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  /*Set Tag RAM to zero */
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  /* Left space for hardware change status*/
  __NOP();
  __NOP();
  __NOP();
  __NOP();
  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  /* Left space for hardware change status*/
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  /* Polling for invalid done */
  do {
    BL702_Delay_US(1);
    cnt++;
    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100);

  /* data flush */
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  /* Left space for hardware change status*/
  __NOP();
  __NOP();
  __NOP();
  __NOP();
  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  /* Left space for hardware change status*/
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  /* Polling for flush done */
  do {
    BL702_Delay_US(1);
    cnt++;
    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100);

  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS);
  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  if (wayDisable != 0xff) {
    finWayDisable = wayDisable;
  }

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  tmpVal |= (finWayDisable << L1C_WAY_DIS_POS);

  /* If way disable is 0x0f, cacheable can't be set */
  if (finWayDisable != 0x0f) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
  }

  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Flush cache external api
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush_Ext(void) {
  uint32_t tmpVal;

  /* Disable early respone */
  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  L1C_Cache_Flush((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
  __NOP();
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get cache hit count
                                                                                *
                                                                                * @param  hitCountLow: hit count low 32 bits pointer
                                                                                * @param  hitCountHigh: hit count high 32 bits pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) {
  *hitCountLow  = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB);
  *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get cache miss count
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Cache miss count
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void) { return BL_RD_REG(L1C_BASE, L1C_MISS_CNT); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable read from flash or psram with cache
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  wrap set
                                                                                *
                                                                                * @param  wrap: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) {
  uint32_t tmpVal  = 0;
  uint8_t  cacheEn = 0;

  tmpVal  = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);

  if (cacheEn != 0) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  }

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);

  if (wrap == ENABLE) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
  } else {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
  }

  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  if (cacheEn != 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  cache way disable set
                                                                                *
                                                                                * @param  disableVal: cache way disable value
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  if (disableVal != 0x0f) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
  }

  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set for ROM 2T access if CPU freq >120MHz
                                                                                *
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);

  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
  }

  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX init
                                                                                *
                                                                                * @param  l1cBmxCfg: L1C BMX config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
  Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX address monitor enable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
  BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX address monitor disable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
  BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX bus error response enable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX bus error response disable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
  BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Get L1C BMX error status
                                                                                *
                                                                                * @param  errType: L1C BMX error status type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));

  tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);

  if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
    return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
  } else {
    return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get L1C BMX error address
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return NP L1C BMX error address
                                                                                *
                                                                                *******************************************************************************/
uint32_t L1C_BMX_Get_Err_Addr(void) { return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR); }

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX error interrupt callback install
                                                                                *
                                                                                * @param  intType: L1C BMX error interrupt type
                                                                                * @param  cbFun: callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun) {
  CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));

  l1cBmxErrIntCbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX ERR interrupt IRQ handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void L1C_BMX_ERR_IRQHandler(void) {
  L1C_BMX_ERR_INT_Type intType;

  for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
    if (l1cBmxErrIntCbfArra[intType] != NULL) {
      l1cBmxErrIntCbfArra[intType]();
    }
  }

  while (1) {
    // MSG("L1C_BMX_ERR_IRQHandler\r\n");
    BL702_Delay_MS(1000);
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX timeout interrupt callback install
                                                                                *
                                                                                * @param  intType: L1C BMX timeout interrupt type
                                                                                * @param  cbFun: callback
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun) {
  CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));

  l1cBmxToIntCbfArra[intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  L1C BMX Time Out interrupt IRQ handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void L1C_BMX_TO_IRQHandler(void) {
  L1C_BMX_TO_INT_Type intType;

  for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
    if (l1cBmxToIntCbfArra[intType] != NULL) {
      l1cBmxToIntCbfArra[intType]();
    }
  }

  while (1) {
    // MSG("L1C_BMX_TO_IRQHandler\r\n");
    BL702_Delay_MS(1000);
  }
}
#endif

/*@} end of group L1C_Public_Functions */

/*@} end of group L1C */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_mjpeg.c
================================================
/**
 ******************************************************************************
 * @file    bl702_mjpeg.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_mjpeg.h"
#include "bl702.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  MJPEG
 *  @{
 */

/** @defgroup  MJPEG_Private_Macros
 *  @{
 */

/*@} end of group MJPEG_Private_Macros */

/** @defgroup  MJPEG_Private_Types
 *  @{
 */

/*@} end of group MJPEG_Private_Types */

/** @defgroup  MJPEG_Private_Variables
 *  @{
 */
static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = {NULL};

/*@} end of group MJPEG_Private_Variables */

/** @defgroup  MJPEG_Global_Variables
 *  @{
 */

/*@} end of group MJPEG_Global_Variables */

/** @defgroup  MJPEG_Private_Fun_Declaration
 *  @{
 */

/*@} end of group MJPEG_Private_Fun_Declaration */

/** @defgroup  MJPEG_Private_Functions
 *  @{
 */

/*@} end of group MJPEG_Private_Functions */

/** @defgroup  MJPEG_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Mjpeg module init
                                                                                *
                                                                                * @param  cfg: Mjpeg configuration structure pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Init(MJPEG_CFG_Type *cfg) {
  uint32_t tmpVal;

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG);

  /* disable mjpeg */
  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
  tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);

  /* basic stuff */
  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Q_MODE, cfg->quality);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_H_BUST, cfg->burst);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_WR_OVER_STOP, cfg->overStopEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE);

  switch (cfg->yuv) {
  case MJPEG_YUV422_INTERLEAVE:
  case MJPEG_YUV422_PLANAR:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);
    break;

  case MJPEG_YUV420:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4);
    break;

  case MJPEG_YUV400:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3);
    break;

  default:
    break;
  }

  BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal);

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable);
  BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal);

  /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/
  BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0));
  BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0));
  BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY);

  /*align buffer to 16 bytes boundary*/
  BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0));
  /*align buffer size in unit of 64 bytes */
  BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg >> 6);

  /* Clear interrupt */
  BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  Mjpeg packet mode configure
                                                                                *
                                                                                * @param  cfg: Packet configuration
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Packet_Config(MJPEG_Packet_Type *cfg) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_PAKET_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_EN, cfg->packetEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_JEND_TO_PEND, cfg->endToTail);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_PKET_BODY_BYTE, cfg->packetBody);
  BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_CTRL, tmpVal);

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, cfg->frameHead);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, cfg->frameTail);
  BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal);

  BL_WR_REG(MJPEG_BASE, MJPEG_PAKET_HEAD_TAIL, (cfg->packetTail << 16) + cfg->packetHead);
}

/****************************************************************************/ /**
                                                                                * @brief  Mjpeg set YUYV order, only work in interleave mode
                                                                                *
                                                                                * @param  y0: Y0 order
                                                                                * @param  u0: U0 order
                                                                                * @param  y1: Y1 order
                                                                                * @param  v0: V0 order
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);

  MJPEG_Set_YUYV_Order_Planar(0, 1);
}

/****************************************************************************/ /**
                                                                                * @brief  Mjpeg set YY/UV order, only work in planar mode
                                                                                *
                                                                                * @param  yy: YY order
                                                                                * @param  uv: UV order
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Set_YUYV_Order_Planar(uint8_t yy, uint8_t uv) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_LSEL, yy);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AHB_FSEL, yy);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_LSEL, uv);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AHB_FSEL, uv);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Deinit mjpeg module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Deinit(void) {
  // GLB_AHB_Slave2_Reset(BL_AHB_SLAVE2_MJPEG);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable mjpeg module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Enable(void) {
  uint32_t tmpVal;

  /* Enable mjpeg module */
  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
  tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable mjpeg module
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Disable(void) {
  uint32_t tmpVal;

  /* Disable mjpeg module */
  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
  tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Enable&disable mjpeg software mode and set frame count
                                                                                *
                                                                                * @param  count: Frame count
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_SW_Enable(uint8_t count) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count);
  tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
  tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  MJPEG software mode run, software mode enable first
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_SW_Run(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2);
  tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
  tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Get one mjpeg frame
                                                                                *
                                                                                * @param  info: Mjpeg frame infomation pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);

  info->validFrames   = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT);
  info->curFrameAddr  = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0);
  info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3;
  info->curFrameQ     = BL_RD_REG(MJPEG_BASE, MJPEG_Q_MODE0) & 0x3f;
  info->status        = tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  Get available count of frames
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Frames count
                                                                                *
                                                                                *******************************************************************************/
uint8_t MJPEG_Get_Frame_Count(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT); }

/****************************************************************************/ /**
                                                                                * @brief  Pop one mjpeg frame
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Pop_Frame(void) { BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1); }

/****************************************************************************/ /**
                                                                                * @brief  Free current read memory block
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Current_Block_Clear(void) { BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2); }

/****************************************************************************/ /**
                                                                                * @brief  Current read memory block index
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Block number
                                                                                *
                                                                                *******************************************************************************/
MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX); }

/****************************************************************************/ /**
                                                                                * @brief  Get block status, full or not full
                                                                                *
                                                                                * @param  block: Block number
                                                                                *
                                                                                * @return Block status
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block) {
  CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block));

  if (MJPEG_BLOCK_0 == block) {
    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL);
  } else {
    return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Current read memory block is frame start
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Set or reset
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type MJPEG_Current_Block_Is_Start(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART); }

/****************************************************************************/ /**
                                                                                * @brief  Current read memory block is frame end
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Set or reset
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type MJPEG_Current_Block_Is_End(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND); }

/****************************************************************************/ /**
                                                                                * @brief  Get frame remain bit count in last block, only valid when current read memory block is
                                                                                *         frame end
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Bit count
                                                                                *
                                                                                *******************************************************************************/
uint32_t MJPEG_Get_Remain_Bit(void) { return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT); }

/****************************************************************************/ /**
                                                                                * @brief  Set frame threshold to issue normal interrupt
                                                                                *
                                                                                * @param  count: Frame threshold
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Set_Frame_Threshold(uint8_t count) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count);
  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  MJPEG Enable Disable Interrupt
                                                                                *
                                                                                * @param  intType: MJPEG Interrupt Type
                                                                                * @param  intMask: Enable or Disable
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);

  switch (intType) {
  case MJPEG_INT_NORMAL:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
    }

    break;

  case MJPEG_INT_CAM_OVERWRITE:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
    }

    break;

  case MJPEG_INT_MEM_OVERWRITE:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
    }

    break;

  case MJPEG_INT_FRAME_OVERWRITE:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
    }

    break;

  case MJPEG_INT_BACK_IDLE:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
    }

    break;

  case MJPEG_INT_SWAP:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
    } else {
      /* Disable this interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
    }

    break;

  case MJPEG_INT_ALL:
    if (intMask == UNMASK) {
      /* Enable all interrupt */
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
      tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
    } else {
      /* Disable all interrupt */
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN);
      tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN);
    }

    break;

  default:
    break;
  }

  BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  MJPEG Interrupt Clear
                                                                                *
                                                                                * @param  intType: MJPEG Interrupt Type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_IntClr(MJPEG_INT_Type intType) {
  uint32_t tmpVal;

  CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP);

  switch (intType) {
  case MJPEG_INT_NORMAL:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR);
    break;

  case MJPEG_INT_CAM_OVERWRITE:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR);
    break;

  case MJPEG_INT_MEM_OVERWRITE:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR);
    break;

  case MJPEG_INT_FRAME_OVERWRITE:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR);
    break;

  case MJPEG_INT_BACK_IDLE:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR);
    break;

  case MJPEG_INT_SWAP:
    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR);
    break;

  case MJPEG_INT_ALL:
    tmpVal = 0x3F00;

  default:
    break;
  }

  BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Install mjpeg interrupt callback function
                                                                                *
                                                                                * @param  intType: MJPEG interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_MJPEG_INT_TYPE(intType));

  mjpegIntCbfArra[intType] = cbFun;
}

/****************************************************************************/ /**
                                                                                * @brief  Mjpeg interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void MJPEG_IRQHandler(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3);

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100);

    if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_NORMAL]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200);

    if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400);

    if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800);

    if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000);

    if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_BACK_IDLE]();
    }
  }

  if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) {
    BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000);

    if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) {
      /* call the callback function */
      mjpegIntCbfArra[MJPEG_INT_SWAP]();
    }
  }
}
#endif

/*@} end of group MJPEG_Public_Functions */

/*@} end of group MJPEG */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pds.c
================================================
/**
 ******************************************************************************
 * @file    bl702_pds.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_pds.h"
#include "bl702.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PDS
 *  @{
 */

/** @defgroup  PDS_Private_Macros
 *  @{
 */

/*@} end of group PDS_Private_Macros */

/** @defgroup  PDS_Private_Types
 *  @{
 */

/*@} end of group PDS_Private_Types */

/** @defgroup  PDS_Private_Variables
 *  @{
 */
static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX][1] = {{NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}, {NULL}};

/*@} end of group PDS_Private_Variables */

/** @defgroup  PDS_Global_Variables
 *  @{
 */

/*@} end of group PDS_Global_Variables */

/** @defgroup  PDS_Private_Fun_Declaration
 *  @{
 */

/*@} end of group PDS_Private_Fun_Declaration */

/** @defgroup  PDS_Private_Functions
 *  @{
 */

/*@} end of group PDS_Private_Functions */

/** @defgroup  PDS_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  power down sleep ram configure
                                                                                *
                                                                                * @param  ramCfg: power down sleep force ram configuration
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) {
  if (NULL == ramCfg) {
    return ERROR;
  }

  /* PDS_RAM1 config */
  BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power down sleep set pad configure
                                                                                *
                                                                                * @param  pin: power down sleep pad num
                                                                                * @param  cfg: power down sleep pad type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg) {
  uint32_t tmpVal = 0;
  uint32_t tmpPu  = 0;
  uint32_t tmpPd  = 0;

  if (pin < PDS_PAD_PIN_GPIO_23) {
    /* GPIO17 - GPIO22 */
    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);

    switch (cfg) {
    case PDS_PAD_CFG_PULL_NONE:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
      break;

    case PDS_PAD_CFG_PULL_DOWN:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
      break;

    case PDS_PAD_CFG_PULL_UP:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
      break;

    case PDS_PAD_CFG_ACTIVE_IE:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
      break;

    default:
      break;
    }

    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD, tmpPd);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU, tmpPu);
    BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
  } else {
    /* GPIO23 - GPIO28 */
    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);

    switch (cfg) {
    case PDS_PAD_CFG_PULL_NONE:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
      break;

    case PDS_PAD_CFG_PULL_DOWN:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
      break;

    case PDS_PAD_CFG_PULL_UP:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
      break;

    case PDS_PAD_CFG_ACTIVE_IE:
      tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
      tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
      break;

    default:
      break;
    }

    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD, tmpPd);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU, tmpPu);
    BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable power down sleep
                                                                                *
                                                                                * @param  cfg: power down sleep configuration 1
                                                                                * @param  cfg4: power down sleep configuration 2
                                                                                * @param  pdsSleepCnt: power down sleep count cycle
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) {
  /* PDS sleep time 0 <=> sleep forever */
  /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
  /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
  if (!pdsSleepCnt) {
    cfg->sleepForever = 0;
  } else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
    return ERROR;
  } else {
    BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
  }

  /* PDS_CTL4 config */
  BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);

  /* PDS_CTL config */
  if (cfg->pdsStart) {
    BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
    BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
  } else {
    BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power down sleep force configure
                                                                                *
                                                                                * @param  cfg2: power down sleep force configuration 1
                                                                                * @param  cfg3: power down sleep force configuration 2
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) {
  /* PDS_CTL2 config */
  BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);

  /* PDS_CTL3 config */
  BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power down sleep force configure
                                                                                *
                                                                                * @param  defaultLvCfg: power down sleep default level configuration
                                                                                * @param  pdsSleepCnt: power down sleep time count
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt) {
  PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
  PDS_App_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power down sleep int enable
                                                                                *
                                                                                * @param  intType: PDS int type
                                                                                * @param  enable: ENABLE or DISABLE
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable) {
  uint32_t offset = 0;
  uint32_t tmpVal = 0;

  if ((intType < PDS_INT_PDS_SLEEP_CNT) || (intType > PDS_INT_KYS_QDEC)) {
    return ERROR;
  }

  switch (intType) {
  case PDS_INT_WAKEUP:
  case PDS_INT_RF_DONE:
  case PDS_INT_PLL_DONE:
    return ERROR;

  case PDS_INT_PDS_SLEEP_CNT:
    offset = 16;
    break;

  case PDS_INT_HBN_IRQ_OUT0:
    offset = 17;
    break;

  case PDS_INT_HBN_IRQ_OUT1:
    offset = 18;
    break;

  case PDS_INT_GPIO_IRQ:
    offset = 19;
    break;

  case PDS_INT_IRRX:
    offset = 20;
    break;

  case PDS_INT_BLE_SLP_IRQ:
    offset = 21;
    break;

  case PDS_INT_USB_WKUP:
    offset = 22;
    break;

  case PDS_INT_KYS_QDEC:
    offset = 23;
    break;

  case PDS_INT_MAX:
    break;

  default:
    break;
  }

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);

  if (enable) {
    tmpVal = tmpVal | (1 << offset);
  } else {
    tmpVal = tmpVal & ~(1 << offset);
  }

  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  power down sleep int mask
                                                                                *
                                                                                * @param  intType: PDS int type
                                                                                * @param  intMask: MASK or UNMASK
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t offset = 0;
  uint32_t tmpVal = 0;

  if (intType > PDS_INT_PLL_DONE) {
    return ERROR;
  }

  switch (intType) {
  case PDS_INT_WAKEUP:
    offset = 8;
    break;

  case PDS_INT_RF_DONE:
    offset = 10;
    break;

  case PDS_INT_PLL_DONE:
    offset = 11;
    break;

  case PDS_INT_PDS_SLEEP_CNT:
  case PDS_INT_HBN_IRQ_OUT0:
  case PDS_INT_HBN_IRQ_OUT1:
  case PDS_INT_GPIO_IRQ:
  case PDS_INT_IRRX:
  case PDS_INT_BLE_SLP_IRQ:
  case PDS_INT_USB_WKUP:
  case PDS_INT_KYS_QDEC:
  case PDS_INT_MAX:
  default:
    return ERROR;
  }

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);

  if (intMask != UNMASK) {
    tmpVal = tmpVal | (1 << offset);
  } else {
    tmpVal = tmpVal & ~(1 << offset);
  }

  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get power down sleep int status
                                                                                *
                                                                                * @param  intType: PDS int type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType) {
  uint32_t offset = 0;

  switch (intType) {
  case PDS_INT_WAKEUP:
    offset = 0;
    break;

  case PDS_INT_RF_DONE:
    offset = 2;
    break;

  case PDS_INT_PLL_DONE:
    offset = 3;
    break;

  case PDS_INT_PDS_SLEEP_CNT:
    offset = 24;
    break;

  case PDS_INT_HBN_IRQ_OUT0:
    offset = 25;
    break;

  case PDS_INT_HBN_IRQ_OUT1:
    offset = 26;
    break;

  case PDS_INT_GPIO_IRQ:
    offset = 27;
    break;

  case PDS_INT_IRRX:
    offset = 28;
    break;

  case PDS_INT_BLE_SLP_IRQ:
    offset = 29;
    break;

  case PDS_INT_USB_WKUP:
    offset = 30;
    break;

  case PDS_INT_KYS_QDEC:
    offset = 31;
    break;

  case PDS_INT_MAX:
    break;

  default:
    break;
  }

  return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  clear power down sleep int status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_IntClear(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get power down sleep PLL status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return PDS PLL status
                                                                                *
                                                                                *******************************************************************************/
PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void) { return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE); }

/****************************************************************************/ /**
                                                                                * @brief  get power down sleep RF status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return PDS RF status
                                                                                *
                                                                                *******************************************************************************/
PDS_RF_STS_Type PDS_Get_PdsRfStstus(void) { return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE); }

/****************************************************************************/ /**
                                                                                * @brief  get power down sleep status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return PDS status
                                                                                *
                                                                                *******************************************************************************/
PDS_STS_Type PDS_Get_PdsStstus(void) { return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); }

/****************************************************************************/ /**
                                                                                * @brief  power down sleep clear reset event
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Clear_Reset_Event(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
  BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  get power down sleep reset event
                                                                                *
                                                                                * @param  event: power down sleep reset event
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
  tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT);

  return (tmpVal & (1 << event)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  set power down sleep VDDCORE gpio interrupt config
                                                                                *
                                                                                * @param  src: PDS VDDCORE src pin num
                                                                                * @param  mode: PDS VDDCORE src pin interrupt type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, PDS_AON_GPIO_INT_Trigger_Type mode) {
  uint32_t tmpVal = 0;

  CHECK_PARAM(IS_PDS_VDDCORE_GPIO_SRC_TYPE(src));
  CHECK_PARAM(IS_PDS_AON_GPIO_INT_Trigger_TYPE(mode));

  tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, src);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, mode);
  BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set power down sleep VDDCORE gpio interrupt mask
                                                                                *
                                                                                * @param  intMask: None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);

  if (intMask != UNMASK) {
    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
  }

  BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  set power down sleep VDDCORE gpio interrupt mask
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET; }

/****************************************************************************/ /**
                                                                                * @brief  set power down sleep VDDCORE gpio interrupt mask
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);

  tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
  BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Install PDS interrupt callback function
                                                                                *
                                                                                * @param  intType: PDS int type
                                                                                * @param  cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun) {
  pdsIntCbfArra[intType][0] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Trim RC32M
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void) {
  Efuse_Ana_RC32M_Trim_Type trim;
  int32_t                   tmpVal = 0;

  EF_Ctrl_Read_RC32M_Trim(&trim);

  if (trim.trimRc32mExtCodeEn) {
    if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
      tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
      tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
      BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
      BL702_Delay_US(2);
      return SUCCESS;
    }
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Select RC32M as PLL ref source
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Select XTAL as PLL ref source
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power on PLL
                                                                                *
                                                                                * @param  xtalType: xtal type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) {
  uint32_t tmpVal = 0;

  /* Check parameter*/
  CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));

  /**************************/
  /* select PLL XTAL source */
  /**************************/

  if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
    PDS_Trim_RC32M();
    PDS_Select_RC32M_As_PLL_Ref();
  } else {
    PDS_Select_XTAL_As_PLL_Ref();
  }

  /*******************************************/
  /* PLL power down first, not indispensable */
  /*******************************************/
  /* power off PLL first, this step is not indispensable */
  PDS_Power_Off_PLL();

  /********************/
  /* PLL param config */
  /********************/

  /* clkpll_icp_1u */
  /* clkpll_icp_5u */
  /* clkpll_int_frac_sw */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);

  /* clkpll_c3 */
  /* clkpll_cz */
  /* clkpll_rz */
  /* clkpll_r4 */
  /* clkpll_r4_short */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);

  /* clkpll_refdiv_ratio */
  /* clkpll_postdiv */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  /* clkpll_sdmin */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);

  /* clkpll_sel_fb_clk */
  /* clkpll_sel_sample_clk can be 0/1, default is 1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);

  /*************************/
  /* PLL power up sequence */
  /*************************/

  /* pu_clkpll_sfreg=1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  BL702_Delay_US(5);

  /* pu_clkpll=1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  /* clkpll_pu_cp=1 */
  /* clkpll_pu_pfd=1 */
  /* clkpll_pu_fbdv=1 */
  /* clkpll_pu_postdiv=1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  BL702_Delay_US(5);

  /* clkpll_sdm_reset=1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
  BL702_Delay_US(1);
  /* clkpll_reset_fbdv=1 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
  BL702_Delay_US(2);
  /* clkpll_reset_fbdv=0 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
  BL702_Delay_US(1);
  /* clkpll_sdm_reset=0 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  return SUCCESS;
}
#endif
/** PLL output config **/
/*
[8]    1'h0    r/w    clkpll_en_32m
[7]    1'h0    r/w    clkpll_en_48m
[6]    1'h0    r/w    clkpll_en_80m
[5]    1'h0    r/w    clkpll_en_96m
[4]    1'h0    r/w    clkpll_en_120m
[3]    1'h0    r/w    clkpll_en_160m
[2]    1'h0    r/w    clkpll_en_192m
[1]    1'h0    r/w    clkpll_en_240m
[0]    1'h0    r/w    clkpll_en_480m
*/

/****************************************************************************/ /**
                                                                                * @brief  Enable all PLL clock
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
  tmpVal |= 0x1FF;
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable all PLL clock
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
  tmpVal &= (~0x1FF);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable PLL clock
                                                                                *
                                                                                * @param  pllClk: PLL clock type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) {
  uint32_t tmpVal = 0;

  /* Check parameter*/
  CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
  tmpVal |= (1 << pllClk);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable PLL clock
                                                                                *
                                                                                * @param  pllClk: PLL clock type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) {
  uint32_t tmpVal = 0;

  /* Check parameter*/
  CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
  tmpVal &= (~(1 << pllClk));
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power off PLL
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void) {
  uint32_t tmpVal = 0;

  /* pu_clkpll_sfreg=0 */
  /* pu_clkpll=0 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  /* clkpll_pu_cp=0 */
  /* clkpll_pu_pfd=0 */
  /* clkpll_pu_fbdv=0 */
  /* clkpll_pu_postdiv=0 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
  tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set Audio PLL clock
                                                                                *
                                                                                * @param  audioPLLFreq: Audio PLL sel frequency , have two vaild input 12.288 or 11.289 MHZ
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq) {
  uint32_t sdmin_table[] = {0x374BC6, 0x32CCED, 0x32CCED, 0x6E978D, 0x6C0000};
  uint32_t tmpVal        = 0;

  CHECK_PARAM(IS_PDS_AUDIO_PLL_TYPE(audioPLLFreq));

  /*set PDS_CLKPLL_REFDIV_RATIO as 0x2 */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 0x2);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  /*set clkpll_sdmin as sdmin*/
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, (uint32_t)sdmin_table[audioPLLFreq % (sizeof(sdmin_table) / sizeof(sdmin_table[0]))]);

  BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);

  /*reset pll */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL_SFREG, 1);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  BL702_Delay_MS(10);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL, 1);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 1);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  BL702_Delay_MS(10);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 0);
  BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);

  /*set div for audio pll */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);

  if (audioPLLFreq != AUDIO_PLL_5644800_HZ) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 36);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 72);
  }

  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  PDS software reset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Reset(void) {
  uint32_t tmpVal = 0;

  tmpVal                  = *(uint32_t *)0x40000010;
  tmpVal                  = tmpVal | (1 << 14);
  *(uint32_t *)0x40000010 = tmpVal;

  tmpVal                  = *(uint32_t *)0x40000010;
  tmpVal                  = tmpVal & ~(1 << 14);
  *(uint32_t *)0x40000010 = tmpVal;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable power down sleep
                                                                                *
                                                                                * @param  cfg: power down sleep configuration 1
                                                                                * @param  pdsSleepCnt: power down sleep count cycle
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt) {
  uint32_t *p = (uint32_t *)cfg;

  if (pdsSleepCnt - PDS_WARMUP_CNT <= 0) {
    return;
  }

  BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_CNT);

  /* Set PDS control register  */
  BL_WR_REG(PDS_BASE, PDS_CTL, *p);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PDS Auto mode wake up counter config
                                                                                *
                                                                                * @param  sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles),
                                                                                *                        recommend maxWarmCnt*N+2
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration) {
  /* PDS_TIME1 */
  BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PDS Auto mode config and enable
                                                                                *
                                                                                * @param  powerCfg: PDS Auto mode power domain config
                                                                                * @param  normalCfg: PDS Auto mode power normal config
                                                                                * @param  enable: PDS Auto mode Enable or Disable
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable) {
  uint32_t pdsCtl = 0;

  CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol));

  /* power config */
  pdsCtl |= (powerCfg->mbgPower << 31) | (powerCfg->ldo18rfPower << 30) | (powerCfg->sfregPower << 29) | (powerCfg->pllPower << 28) | (powerCfg->cpu0Power << 19) | (powerCfg->rc32mPower << 17) |
            (powerCfg->xtalPower << 14) | (powerCfg->allPower << 13) | (powerCfg->isoPower << 11) | (powerCfg->bzPower << 10) | (powerCfg->sramDisStanby << 9) | (powerCfg->cgPower << 8) |
            (powerCfg->cpu1Power << 7) | (powerCfg->usbPower << 3);
  pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol);
  pdsCtl |= (normalCfg->vddcoreVolEn << 18) | (normalCfg->cpu0NotNeedWFI << 21) | (normalCfg->cpu1NotNeedWFI << 20) | (normalCfg->busReset << 16) | (normalCfg->disIrqWakeUp << 15) |
            (normalCfg->powerOffXtalForever << 2) | (normalCfg->sleepForever << 1);
  BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);

  pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL);

  if (enable) {
    pdsCtl |= (1 << 0);
  } else {
    pdsCtl &= ~(1 << 0);
  }

  BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PDS force turn off XXX domain
                                                                                *
                                                                                * @param  domain: PDS domain
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain) {
  uint32_t tmpVal = 0;

  /* memory sleep */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET);
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* gate clock */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET);
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* pds reset */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET);
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* isolation on */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET);
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* power off */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET);
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PDS force turn on XXX domain
                                                                                *
                                                                                * @param  domain: PDS domain
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain) {
  uint32_t tmpVal = 0;

  /* power on */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET));
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* isolation off */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET));
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* pds de_reset */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET));
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* memory active */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET));
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);

  /* clock on */
  tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
  tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET));
  BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Power down sleep wake up interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void PDS_WAKEUP_IRQHandler(void) {
  for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
    if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
      pdsIntCbfArra[intType][0]();
    }
  }
  PDS_Set_Vddcore_GPIO_IntClear();
  PDS_IntClear();
}

/****************************************************************************/ /**
                                                                                * @brief  PDS wakeup IRQHandler install
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void) {
  Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief
                                                                                *
                                                                                * @param
                                                                                *
                                                                                * @return
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
  // clkpll_vg11_sel
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_VG11_SEL, vg11Sel);
  BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);

  return SUCCESS;
}

/*@} end of group PDS_Public_Functions */

/*@} end of group PDS */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_psram.c
================================================
/**
 ******************************************************************************
 * @file    bl702_psram.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_psram.h"
#include "bl702_l1c.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PSRAM
 *  @{
 */

/** @defgroup  PSRAM_Private_Macros
 *  @{
 */

/*@} end of group PSRAM_Private_Macros */

/** @defgroup  PSRAM_Private_Types
 *  @{
 */

/*@} end of group PSRAM_Private_Types */

/** @defgroup  PSRAM_Private_Variables
 *  @{
 */

/*@} end of group PSRAM_Private_Variables */

/** @defgroup  PSRAM_Global_Variables
 *  @{
 */

/*@} end of group PSRAM_Global_Variables */

/** @defgroup  PSRAM_Private_Fun_Declaration
 *  @{
 */

/*@} end of group PSRAM_Private_Fun_Declaration */

/** @defgroup  PSRAM_Private_Functions
 *  @{
 */

/*@} end of group PSRAM_Private_Functions */

/** @defgroup  PSRAM_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Init serial psram control interface
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  cmdsCfg: Serial Serial Flash controller configuration pointer
                                                                                * @param  sfCtrlPsramCfg: Serial psram controller configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
// #ifndef BFLB_USE_ROM_DRIVER
//__WEAK
void ATTR_TCM_SECTION Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) {
  SF_Ctrl_Psram_Init(sfCtrlPsramCfg);
  SF_Ctrl_Cmds_Set(cmdsCfg);

  Psram_SetDriveStrength(psramCfg);
  Psram_SetBurstWrap(psramCfg);
}
// #endif

/****************************************************************************/ /**
                                                                                * @brief  Read psram register
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  regValue: Register value pointer to store data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) {
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode));

  uint8_t *const       psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) {
    psramCmd.cmdMode  = SF_CTRL_CMD_4_LINES;
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
  }

  psramCmd.cmdBuf[0] = (psramCfg->readRegCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_READ;
  psramCmd.addrSize  = 3;
  psramCmd.dummyClks = psramCfg->readRegDmyClk;
  psramCmd.nbData    = 1;

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  BL702_MemCpy(regValue, psramCtrlBuf, 1);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Write psram register
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  regValue: Register value pointer storing data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) {
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode));

  uint8_t *const       psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  BL702_MemCpy(psramCtrlBuf, regValue, 1);

  if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) {
    psramCmd.cmdMode  = SF_CTRL_CMD_4_LINES;
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
  }

  psramCmd.cmdBuf[0] = (psramCfg->writeRegCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_WRITE;
  psramCmd.addrSize  = 3;
  psramCmd.nbData    = 1;

  SF_Ctrl_SendCmd(&psramCmd);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set psram driver strength
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) {
  uint32_t stat = 0;
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_DRIVE_STRENGTH(psramCfg->driveStrength));

  Psram_ReadReg(psramCfg, (uint8_t *)&stat);

  if ((stat & 0x3) == psramCfg->driveStrength) {
    return SUCCESS;
  }

  stat &= (~0x3);
  stat |= psramCfg->driveStrength;

  Psram_WriteReg(psramCfg, (uint8_t *)&stat);
  /* Wait for write done */

  Psram_ReadReg(psramCfg, (uint8_t *)&stat);

  if ((stat & 0x3) == psramCfg->driveStrength) {
    return SUCCESS;
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set psram burst wrap size
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) {
  uint32_t stat = 0;
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_BURST_LENGTH(psramCfg->burstLength));

  Psram_ReadReg(psramCfg, (uint8_t *)&stat);

  if (((stat >> 5) & 0x3) == psramCfg->burstLength) {
    return SUCCESS;
  }

  stat &= (~(0x3 << 5));
  stat |= (psramCfg->burstLength << 5);

  Psram_WriteReg(psramCfg, (uint8_t *)&stat);
  /* Wait for write done */

  Psram_ReadReg(psramCfg, (uint8_t *)&stat);

  if (((stat >> 5) & 0x3) == psramCfg->burstLength) {
    return SUCCESS;
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get psram ID
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  data: Data pointer to store read data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) {
  uint8_t *const       psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  psramCmd.cmdBuf[0] = (psramCfg->readIdCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_READ;
  psramCmd.addrSize  = 3;
  psramCmd.dummyClks = psramCfg->readIdDmyClk;
  psramCmd.nbData    = 8;

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  BL702_MemCpy(data, psramCtrlBuf, 8);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Psram enter quad mode
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) {
  SF_Ctrl_Cmd_Cfg_Type psramCmd;

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  psramCmd.cmdBuf[0] = (psramCfg->enterQuadModeCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_READ;

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Psram exit quad mode
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) {
  SF_Ctrl_Cmd_Cfg_Type psramCmd;

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  psramCmd.cmdMode  = SF_CTRL_CMD_4_LINES;
  psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
  psramCmd.dataMode = SF_CTRL_DATA_4_LINES;

  psramCmd.cmdBuf[0] = (psramCfg->exitQuadModeCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_READ;

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Psram toggle burst length
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ctrlMode: Psram ctrl mode type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) {
  SF_Ctrl_Cmd_Cfg_Type psramCmd;
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode));

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (ctrlMode == PSRAM_QPI_CTRL_MODE) {
    psramCmd.cmdMode  = SF_CTRL_CMD_4_LINES;
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
  }

  psramCmd.cmdBuf[0] = (psramCfg->burstToggleCmd) << 24;
  psramCmd.rwFlag    = SF_CTRL_READ;

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Psram software reset
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ctrlMode: Psram ctrl mode type
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) {
  SF_Ctrl_Cmd_Cfg_Type psramCmd;
  /* Check the parameters */
  CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode));

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (ctrlMode == PSRAM_QPI_CTRL_MODE) {
    psramCmd.cmdMode  = SF_CTRL_CMD_4_LINES;
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
  }

  /* Reset enable */
  psramCmd.cmdBuf[0] = (psramCfg->resetEnableCmd) << 24;
  /* rwFlag don't care */
  psramCmd.rwFlag = SF_CTRL_READ;
  /* Wait for write done */

  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  /* Reset */
  psramCmd.cmdBuf[0] = (psramCfg->resetCmd) << 24;
  /* rwFlag don't care */
  psramCmd.rwFlag = SF_CTRL_READ;
  SF_Ctrl_SendCmd(&psramCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
  }

  BL702_Delay_US(50);
  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Psram set IDbus config
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ioMode: Psram ctrl mode type
                                                                                * @param  addr: Address to read/write
                                                                                * @param  len: Data length to read/write
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) {
  uint8_t              cmd, dummyClks;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;
  uint8_t              cmdValid = 1;
  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));

  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);

  /* read mode cache set */
  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd       = psramCfg->fReadCmd;
    dummyClks = psramCfg->fReadDmyClk;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = psramCfg->fReadQuadCmd;
    dummyClks         = psramCfg->fReadQuadDmyClk;
  } else {
    return ERROR;
  }

  /* prepare command */
  psramCmd.rwFlag    = SF_CTRL_READ;
  psramCmd.addrSize  = 3;
  psramCmd.cmdBuf[0] = (cmd << 24) | addr;
  psramCmd.dummyClks = dummyClks;
  psramCmd.nbData    = len;
  SF_Ctrl_Psram_Read_Icache_Set(&psramCmd, cmdValid);

  /* write mode cache set */
  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd = psramCfg->writeCmd;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = psramCfg->quadWriteCmd;
  } else {
    return ERROR;
  }

  dummyClks = 0;

  /* prepare command */
  psramCmd.rwFlag    = SF_CTRL_WRITE;
  psramCmd.addrSize  = 3;
  psramCmd.cmdBuf[0] = (cmd << 24) | addr;
  psramCmd.dummyClks = dummyClks;
  psramCmd.nbData    = len;
  SF_Ctrl_Psram_Write_Icache_Set(&psramCmd, cmdValid);
  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set cache write to psram with cache
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ioMode: Psram controller interface mode
                                                                                * @param  wtEn: Psram cache write through enable
                                                                                * @param  wbEn: Psram cache write back enable
                                                                                * @param  waEn: Psram cache write allocate enable
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) {
  BL_Err_Type stat;

  /* Cache now only support 32 bytes read */
  stat = Psram_Set_IDbus_Cfg(psramCfg, ioMode, 0, 32);

  if (SUCCESS != stat) {
    return stat;
  }

  L1C_Cache_Write_Set(wtEn, wbEn, waEn);
  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Write psram one region
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ioMode: Write mode: SPI mode or QPI mode
                                                                                * @param  addr: Start address to be write
                                                                                * @param  data: Data pointer to be write
                                                                                * @param  len: Data length to be write
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  uint8_t *const       psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             i = 0, curLen = 0;
  uint32_t             burstLen = 512;
  uint8_t              cmd;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;
  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd = psramCfg->writeCmd;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = psramCfg->quadWriteCmd;
  } else {
    return ERROR;
  }

  /* Prepare command */
  psramCmd.rwFlag   = SF_CTRL_WRITE;
  psramCmd.addrSize = 3;

  if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) {
    burstLen = 16;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) {
    burstLen = 32;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) {
    burstLen = 64;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) {
    burstLen = 512;
  }

  for (i = 0; i < len;) {
    /* Get current programmed length within page size */
    curLen = burstLen - addr % burstLen;

    if (curLen > len - i) {
      curLen = len - i;
    }

    /* Prepare command */
    BL702_MemCpy_Fast(psramCtrlBuf, data, curLen);
    psramCmd.cmdBuf[0] = (cmd << 24) | (addr);
    psramCmd.nbData    = curLen;

    SF_Ctrl_SendCmd(&psramCmd);

    /* Adjust address and programmed length */
    addr += curLen;
    i += curLen;
    data += curLen;

    /* Wait for write done */
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read data from psram
                                                                                *
                                                                                * @param  psramCfg: Serial psram parameter configuration pointer
                                                                                * @param  ioMode: IoMode: psram controller interface mode
                                                                                * @param  addr: Psram read start address
                                                                                * @param  data: Data pointer to store data read from psram
                                                                                * @param  len: Data length to read
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  uint8_t *const       psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             curLen, i;
  uint32_t             burstLen = 512;
  uint8_t              cmd, dummyClks;
  SF_Ctrl_Cmd_Cfg_Type psramCmd;
  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode));

  if (((uint32_t)&psramCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4);
  } else {
    BL702_MemSet(&psramCmd, 0, sizeof(psramCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd       = psramCfg->fReadCmd;
    dummyClks = psramCfg->fReadDmyClk;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    psramCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    psramCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = psramCfg->fReadQuadCmd;
    dummyClks         = psramCfg->fReadQuadDmyClk;
  } else {
    return ERROR;
  }

  /* Prepare command */
  psramCmd.rwFlag    = SF_CTRL_READ;
  psramCmd.addrSize  = 3;
  psramCmd.dummyClks = dummyClks;

  if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) {
    burstLen = 16;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) {
    burstLen = 32;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) {
    burstLen = 64;
  } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) {
    burstLen = 512;
  }

  /* Read data */
  for (i = 0; i < len;) {
    /* Prepare command */
    psramCmd.cmdBuf[0] = (cmd << 24) | (addr);
    curLen             = burstLen - addr % burstLen;

    if (curLen > len - i) {
      curLen = len - i;
    }

    if (curLen >= FLASH_CTRL_BUF_SIZE) {
      curLen          = FLASH_CTRL_BUF_SIZE;
      psramCmd.nbData = curLen;
    } else {
      /* Make sf_ctrl word read */
      psramCmd.nbData = ((curLen + 3) >> 2) << 2;
    }

    SF_Ctrl_SendCmd(&psramCmd);

    while (SET == SF_Ctrl_GetBusyState()) {
    }

    BL702_MemCpy_Fast(data, psramCtrlBuf, curLen);

    addr += curLen;
    i += curLen;
    data += curLen;
  }

  return SUCCESS;
}
#endif

/*@} end of group PSRAM_Public_Functions */

/*@} end of group PSRAM */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_pwm.c
================================================
/**
 ******************************************************************************
 * @file    bl702_pwm.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_pwm.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  PWM
 *  @{
 */

/** @defgroup  PWM_Private_Macros
 *  @{
 */
#define PWM_Get_Channel_Reg(ch) (PWM_BASE + PWM_CHANNEL_OFFSET + (ch) * 0x20)
#define PWM_INT_TIMEOUT_COUNT   (160 * 1000)
#define PWM_STOP_TIMEOUT_COUNT  (160 * 1000)

/*@} end of group PWM_Private_Macros */

/** @defgroup  PWM_Private_Types
 *  @{
 */

/*@} end of group PWM_Private_Types */

/** @defgroup  PWM_Private_Variables
 *  @{
 */

/**
 *  @brief PWM interrupt callback function address array
 */
static intCallback_Type *PWMIntCbfArra[PWM_CH_MAX][PWM_INT_ALL] = {{NULL}};

/*@} end of group PWM_Private_Variables */

/** @defgroup  PWM_Global_Variables
 *  @{
 */

/*@} end of group PWM_Global_Variables */

/** @defgroup  PWM_Private_Fun_Declaration
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph);
#endif

/*@} end of group PWM_Private_Fun_Declaration */

/** @defgroup  PWM_Private_Functions
 *  @{
 */

/****************************************************************************
 * @brief  PWM interrupt handle
 *
 * @param  intPeriph: Select the peripheral, such as PWM0_IRQn
 *
 * @return SUCCESS
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) {
  uint32_t i;
  uint32_t tmpVal;
  uint32_t timeoutCnt = PWM_INT_TIMEOUT_COUNT;
  /* Get channel register */
  uint32_t PWMx = PWM_BASE;

  for (i = 0; i < PWM_CH_MAX; i++) {
    tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);

    if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i)) != 0) {
      /* Clear interrupt */
      tmpVal |= (1 << (i + PWM_INT_CLEAR_POS));
      BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);

      /* FIXME: we need set pwm_int_clear to 0 by software and
         before this,we must make sure pwm_interrupt_sts is 0*/
      do {
        tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
        timeoutCnt--;

        if (timeoutCnt == 0) {
          break;
        }
      } while (BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << i));

      tmpVal &= (~(1 << (i + PWM_INT_CLEAR_POS)));
      BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);

      if (PWMIntCbfArra[i][PWM_INT_PULSE_CNT] != NULL) {
        /* Call the callback function */
        PWMIntCbfArra[i][PWM_INT_PULSE_CNT]();
      }
    }
  }

  return SUCCESS;
}
#endif

/*@} end of group PWM_Private_Functions */

/** @defgroup  PWM_Public_Functions
 *  @{
 */

/****************************************************************************
 * @brief  PWM channel init
 *
 * @param  chCfg: PWM configuration
 *
 * @return SUCCESS
 *
 *******************************************************************************/
BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg) {
  uint32_t tmpVal;
  uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(chCfg->ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(chCfg->ch));
  CHECK_PARAM(IS_PWM_CLK_TYPE(chCfg->clk));
  CHECK_PARAM(IS_PWM_POLARITY_TYPE(chCfg->pol));
  CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(chCfg->stopMode));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_PWM);

  /* Config pwm clock and polarity */
  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));

  while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  }

  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, chCfg->clk);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, chCfg->pol);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, chCfg->stopMode);
  BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);

  /* Config pwm division */
  BL_WR_REG(PWMx, PWM_CLKDIV, chCfg->clkDiv);

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_THRE1, chCfg->threshold1);
  BL_WR_REG(PWMx, PWM_THRE2, chCfg->threshold2);
  BL_WR_REG(PWMx, PWM_PERIOD, chCfg->period);

  /* Config interrupt pulse count */
  tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);
  BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, chCfg->intPulseCnt));
  // PWM_IntMask(chCfg->ch, PWM_INT_PULSE_CNT, chCfg->intPulseCnt != 0 ? UNMASK : MASK);
  CPU_Interrupt_Disable(PWM_IRQn);

  return SUCCESS;
}

/****************************************************************************
 * @brief  PWM channel update source memory address and len
 *
 * @param  ch: PWM channel
 * @param  period: period
 * @param  threshold1: threshold1
 * @param  threshold2: threshold2
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Update(PWM_CH_ID_Type ch, uint16_t period, uint16_t threshold1, uint16_t threshold2) {
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_THRE1, threshold1);
  BL_WR_REG(PWMx, PWM_THRE2, threshold2);
  BL_WR_REG(PWMx, PWM_PERIOD, period);
}

/****************************************************************************
 * @brief  PWM channel update clock divider
 *
 * @param  ch: PWM channel
 * @param  div: Clock divider
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Set_Div(PWM_CH_ID_Type ch, uint16_t div) {
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  BL_WR_REG(PWMx, PWM_CLKDIV, div);
}

/****************************************************************************
 * @brief  PWM channel update threshold1
 *
 * @param  ch: PWM channel
 * @param  threshold1: threshold1
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch, uint16_t threshold1) {
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_THRE1, threshold1);
}

/****************************************************************************
 * @brief  PWM channel update threshold2
 *
 * @param  ch: PWM channel
 * @param  threshold2: threshold2
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch, uint16_t threshold2) {
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_THRE2, threshold2);
}

/****************************************************************************
 * @brief  PWM channel update period
 *
 * @param  ch: PWM channel
 * @param  period: period
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Set_Period(PWM_CH_ID_Type ch, uint16_t period) {
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_PERIOD, period);
}

/****************************************************************************
 * @brief  PWM get configuration
 *
 * @param  ch: PWM channel
 * @param  period: period pointer
 * @param  threshold1: threshold1 pointer
 * @param  threshold2: threshold2 pointer
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Get(PWM_CH_ID_Type ch, uint16_t *period, uint16_t *threshold1, uint16_t *threshold2) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* get pwm period and duty */
  tmpVal      = BL_RD_REG(PWMx, PWM_THRE1);
  *threshold1 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE1);
  tmpVal      = BL_RD_REG(PWMx, PWM_THRE2);
  *threshold2 = BL_GET_REG_BITS_VAL(tmpVal, PWM_THRE2);
  tmpVal      = BL_RD_REG(PWMx, PWM_PERIOD);
  *period     = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD);
}

/****************************************************************************
 * @brief  PWM enable
 *
 * @param  ch: PWM channel number
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Enable(PWM_CH_ID_Type ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm clock to enable pwm */
  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN));
}
uint8_t PWM_Channel_Is_Enabled(PWM_CH_ID_Type ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm clock to enable pwm */
  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  return BL_GET_REG_BITS_VAL(tmpVal, PWM_STOP_EN) == 0;
}
/****************************************************************************
 * @brief  PWM disable
 *
 * @param  ch: PWM channel number
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Disable(PWM_CH_ID_Type ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  /* Config pwm clock to disable pwm */
  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
  PWM_IntMask(ch, PWM_INT_PULSE_CNT, MASK);
}

/****************************************************************************
 * @brief  PWM channel software mode enable or disable
 *
 * @param  ch: PWM channel number
 * @param  enable: Enable or disable
 *
 * @return None
 *
 *******************************************************************************/
void PWM_SW_Mode(PWM_CH_ID_Type ch, BL_Fun_Type enable) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_MODE, enable));
}

/****************************************************************************
 * @brief  PWM channel force output high or low
 *
 * @param  ch: PWM channel number
 * @param  value: Output value
 *
 * @return None
 *
 *******************************************************************************/
void PWM_SW_Force_Value(PWM_CH_ID_Type ch, uint8_t value) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, PWM_SW_FORCE_VAL, value));
}

/****************************************************************************
 * @brief  PWM channel force output high
 *
 * @param  ch: PWM channel number
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Channel_Fource_Output(PWM_CH_ID_Type ch) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));

  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_SW_MODE));
}

/****************************************************************************
 * @brief  Mask/Unmask the PWM interrupt
 *
 * @param  ch: PWM channel number
 * @param  intType: Specifies the interrupt type
 * @param  intMask: Enable/Disable Specified interrupt type
 *
 * @return None
 *
 *******************************************************************************/
void PWM_IntMask(PWM_CH_ID_Type ch, PWM_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  /* Check the parameters */
  CHECK_PARAM(IS_PWM_CH_ID_TYPE(ch));
  CHECK_PARAM(IS_PWM_INT_TYPE(intType));

  tmpVal = BL_RD_REG(PWMx, PWM_INTERRUPT);

  switch (intType) {
  case PWM_INT_PULSE_CNT:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE));
    } else {
      /* MASK(Disable) this interrupt */
      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE));
    }

    break;

  case PWM_INT_ALL:
    if (intMask == UNMASK) {
      /* UNMASK(Enable) this interrupt */
      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_SET_REG_BIT(tmpVal, PWM_INT_ENABLE));
    } else {
      /* MASK(Disable) this interrupt */
      BL_WR_REG(PWMx, PWM_INTERRUPT, BL_CLR_REG_BIT(tmpVal, PWM_INT_ENABLE));
    }

    break;

  default:
    break;
  }
}

/****************************************************************************
 * @brief  Install PWM interrupt callback function
 *
 * @param  ch: PWM channel number
 * @param  intType: PWM interrupt type
 * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
 *
 * @return None
 *
 *******************************************************************************/
void PWM_Int_Callback_Install(PWM_CH_ID_Type ch, uint32_t intType, intCallback_Type *cbFun) { PWMIntCbfArra[ch][intType] = cbFun; }

/****************************************************************************
 * @brief  PWM smart configure according to frequency and duty cycle function
 *
 * @param  ch: PWM channel number
 * @param  frequency: PWM frequency
 * @param  dutyCycle: PWM duty cycle
 *
 * @return SUCCESS or TIMEOUT
 *
 *******************************************************************************/
BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch, uint32_t frequency, uint8_t dutyCycle) {
  uint32_t tmpVal;
  uint16_t clkDiv, period, threshold2;
  uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT;
  /* Get channel register */
  uint32_t PWMx = PWM_Get_Channel_Reg(ch);

  if (frequency <= 32) {
    clkDiv     = 500;
    period     = 64000 / frequency;
    threshold2 = 640 * dutyCycle / frequency;
  } else if (frequency <= 62) {
    clkDiv     = 16;
    period     = 2000000 / frequency;
    threshold2 = 20000 * dutyCycle / frequency;
  } else if (frequency <= 124) {
    clkDiv     = 8;
    period     = 4000000 / frequency;
    threshold2 = 40000 * dutyCycle / frequency;
  } else if (frequency <= 246) {
    clkDiv     = 4;
    period     = 8000000 / frequency;
    threshold2 = 80000 * dutyCycle / frequency;
  } else if (frequency <= 490) {
    clkDiv     = 2;
    period     = 16000000 / frequency;
    threshold2 = 160000 * dutyCycle / frequency;
  } else {
    clkDiv     = 1;
    period     = 32000000 / frequency;
    threshold2 = 320000 * dutyCycle / frequency;
  }

  tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
  if (BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL) != PWM_CLK_XCLK) {
    BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
    while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
      timeoutCnt--;
      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    }
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
  }
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, PWM_POL_NORMAL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL);
  BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);

  /* Config pwm division */
  BL_WR_REG(PWMx, PWM_CLKDIV, clkDiv);

  /* Config pwm period and duty */
  BL_WR_REG(PWMx, PWM_PERIOD, period);
  BL_WR_REG(PWMx, PWM_THRE1, 0);
  BL_WR_REG(PWMx, PWM_THRE2, threshold2);

  return SUCCESS;
}

/****************************************************************************
 * @brief  PWM interrupt function
 *
 * @param  None
 *
 * @return None
 *
 *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void PWM_IRQHandler(void) { PWM_IntHandler(PWM_IRQn); }
#endif

/*@} end of group PWM_Public_Functions */

/*@} end of group PWM */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_qdec.c
================================================
/**
 ******************************************************************************
 * @file    bl702_qdec.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_qdec.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  QDEC
 *  @{
 */

/** @defgroup  QDEC_Private_Macros
 *  @{
 */

/*@} end of group QDEC_Private_Macros */

/** @defgroup  QDEC_Private_Types
 *  @{
 */

/*@} end of group QDEC_Private_Types */

/** @defgroup  QDEC_Private_Variables
 *  @{
 */
static const uint32_t    qdecAddr[QDEC_ID_MAX]                     = {QDEC0_BASE, QDEC1_BASE, QDEC2_BASE};
static intCallback_Type *qdecIntCbfArra[QDEC_ID_MAX][QDEC_INT_ALL] = {
    {NULL, NULL, NULL, NULL},
    {NULL, NULL, NULL, NULL},
    {NULL, NULL, NULL, NULL}
};

/*@} end of group QDEC_Private_Variables */

/** @defgroup  QDEC_Global_Variables
 *  @{
 */

/*@} end of group QDEC_Global_Variables */

/** @defgroup  QDEC_Private_Fun_Declaration
 *  @{
 */

/*@} end of group QDEC_Private_Fun_Declaration */

/** @defgroup  QDEC_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  QDEC init
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  qdecCfg: QDEC config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_Init(QDEC_ID_Type qdecId, QDEC_CFG_Type *qdecCfg) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  CHECK_PARAM(IS_QDEC_SAMPLE_MODE_TYPE(qdecCfg->sampleCfg.sampleMod));
  CHECK_PARAM(IS_QDEC_SAMPLE_PERIOD_TYPE(qdecCfg->sampleCfg.samplePeriod));
  CHECK_PARAM(IS_QDEC_REPORT_MODE_TYPE(qdecCfg->reportCfg.reportMod));
  CHECK_PARAM((qdecCfg->ledCfg.ledPeriod) <= 0x1FF);
  CHECK_PARAM((qdecCfg->deglitchCfg.deglitchStrength) <= 0xF);

  /* qdec_ctrl */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, qdecCfg->sampleCfg.samplePeriod);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, qdecCfg->reportCfg.reportPeriod);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, qdecCfg->ledCfg.ledEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, qdecCfg->ledCfg.ledSwap);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, qdecCfg->deglitchCfg.deglitchEn);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, qdecCfg->deglitchCfg.deglitchStrength);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);

  /* qdec_ctrl1 */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, qdecCfg->sampleCfg.sampleMod);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, qdecCfg->reportCfg.reportMod);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, qdecCfg->ledCfg.ledPeriod);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, qdecCfg->accMod);
  BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(QDEC0_IRQn, QDEC0_IRQHandler);
  Interrupt_Handler_Register(QDEC1_IRQn, QDEC1_IRQHandler);
  Interrupt_Handler_Register(QDEC2_IRQn, QDEC2_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC deinit
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_DeInit(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* deconfig qdec */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_PERIOD, 10);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_PERIOD, 2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_CNT, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DEG_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_POL, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_EN, 0);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_LED_PERIOD, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_INPUT_SWAP, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_MODE, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_MODE, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_ACC_MODE, 1);
  BL_WR_REG(QDECx, QDEC0_CTRL1, tmpVal);

  /* enable qdec */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 1);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);

  /* deconfig interrupt */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, 0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, 1);
  BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal);

  /* clear status */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_CLR, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_CLR, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_CLR, 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_CLR, 1);
  BL_WR_REG(QDECx, QDEC0_INT_STS, tmpVal);

  /* clear value */
  tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);

  /* disable qdec */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_EN, 0);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC enable
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_Enable(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* qdec_ctrl */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_EN);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC disable
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_Disable(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* qdec_ctrl */
  tmpVal = BL_RD_REG(QDECx, QDEC0_CTRL0);
  tmpVal = BL_CLR_REG_BIT(tmpVal, QDEC_EN);
  BL_WR_REG(QDECx, QDEC0_CTRL0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  set QDEC interrupt mask
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                * @param  intMask: MASK or UNMASK
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_SetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  CHECK_PARAM(IS_QDEC_INT_TYPE(intType));

  /* qdec_int_en */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);

  switch (intType) {
  case QDEC_INT_REPORT:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN, (intMask ? 0 : 1));
    break;

  case QDEC_INT_SAMPLE:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN, (intMask ? 0 : 1));
    break;

  case QDEC_INT_ERROR:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN, (intMask ? 0 : 1));
    break;

  case QDEC_INT_OVERFLOW:
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN, (intMask ? 0 : 1));
    break;

  default:
    break;
  }

  BL_WR_REG(QDECx, QDEC0_INT_EN, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  get QDEC interrupt mask
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                *
                                                                                * @return MASK or UNMASK
                                                                                *
                                                                                *******************************************************************************/
BL_Mask_Type QDEC_GetIntMask(QDEC_ID_Type qdecId, QDEC_INT_Type intType) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  CHECK_PARAM(IS_QDEC_INT_TYPE(intType));

  /* qdec_int_en */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_EN);

  switch (intType) {
  case QDEC_INT_REPORT:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_EN) ? UNMASK : MASK;

  case QDEC_INT_SAMPLE:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_EN) ? UNMASK : MASK;

  case QDEC_INT_ERROR:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_EN) ? UNMASK : MASK;

  case QDEC_INT_OVERFLOW:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_EN) ? UNMASK : MASK;

  default:
    return UNMASK;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC interrupt callback install
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                * @param  cbFun: interrupt callback
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_Int_Callback_Install(QDEC_ID_Type qdecId, QDEC_INT_Type intType, intCallback_Type *cbFun) { qdecIntCbfArra[qdecId][intType] = cbFun; }

/****************************************************************************/ /**
                                                                                * @brief  QDEC get interrupt status
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type QDEC_Get_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  CHECK_PARAM(IS_QDEC_INT_TYPE(intType));

  /* qdec_int_sts */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_STS);

  switch (intType) {
  case QDEC_INT_REPORT:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_RPT_RDY_STS) ? SET : RESET;

  case QDEC_INT_SAMPLE:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_RDY_STS) ? SET : RESET;

  case QDEC_INT_ERROR:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_DBL_RDY_STS) ? SET : RESET;

  case QDEC_INT_OVERFLOW:
    return BL_GET_REG_BITS_VAL(tmpVal, QDEC_OVERFLOW_STS) ? SET : RESET;

  default:
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC clear interrupt status
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_Clr_Int_Status(QDEC_ID_Type qdecId, QDEC_INT_Type intType) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  CHECK_PARAM(IS_QDEC_INT_TYPE(intType));

  /* qdec_int_clr */
  tmpVal = BL_RD_REG(QDECx, QDEC0_INT_CLR);

  switch (intType) {
  case QDEC_INT_REPORT:
    tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_RPT_RDY_CLR);
    break;

  case QDEC_INT_SAMPLE:
    tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_SPL_RDY_CLR);
    break;

  case QDEC_INT_ERROR:
    tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_DBL_RDY_CLR);
    break;

  case QDEC_INT_OVERFLOW:
    tmpVal = BL_SET_REG_BIT(tmpVal, QDEC_OVERFLOW_CLR);
    break;

  default:
    break;
  }

  BL_WR_REG(QDECx, QDEC0_INT_CLR, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC get sample direction
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
QDEC_DIRECTION_Type QDEC_Get_Sample_Direction(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* qdec_value */
  tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);

  return (QDEC_DIRECTION_Type)BL_GET_REG_BITS_VAL(tmpVal, QDEC_SPL_VAL);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC get error count
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
uint8_t QDEC_Get_Err_Cnt(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* qdec_value */
  tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);

  return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC2_VAL);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC get sample value
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
uint16_t QDEC_Get_Sample_Val(QDEC_ID_Type qdecId) {
  uint32_t tmpVal = 0;
  uint32_t QDECx  = qdecAddr[qdecId];

  /* qdec_value */
  tmpVal = BL_RD_REG(QDECx, QDEC0_VALUE);

  return BL_GET_REG_BITS_VAL(tmpVal, QDEC_ACC1_VAL);
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC interrupt handler
                                                                                *
                                                                                * @param  qdecId: QDEC ID
                                                                                * @param  intType: QDEC interrupt type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void QDEC_IntHandler(QDEC_ID_Type qdecId, QDEC_INT_Type intType) {
  if (SET == QDEC_Get_Int_Status(qdecId, intType)) {
    QDEC_Clr_Int_Status(qdecId, intType);

    if (qdecIntCbfArra[qdecId][intType] != NULL) {
      qdecIntCbfArra[qdecId][intType]();
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  QDEC0 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void QDEC0_IRQHandler(void) {
  QDEC_INT_Type intType;

  for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
    if (UNMASK == QDEC_GetIntMask(QDEC0_ID, intType)) {
      QDEC_IntHandler(QDEC0_ID, intType);
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  QDEC1 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void QDEC1_IRQHandler(void) {
  QDEC_INT_Type intType;

  for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
    if (UNMASK == QDEC_GetIntMask(QDEC1_ID, intType)) {
      QDEC_IntHandler(QDEC1_ID, intType);
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  QDEC2 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void QDEC2_IRQHandler(void) {
  QDEC_INT_Type intType;

  for (intType = QDEC_INT_REPORT; intType < QDEC_INT_ALL; intType++) {
    if (UNMASK == QDEC_GetIntMask(QDEC2_ID, intType)) {
      QDEC_IntHandler(QDEC2_ID, intType);
    }
  }
}
#endif

/*@} end of group QDEC_Private_Functions */

/*@} end of group QDEC */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romapi.c
================================================
#include "bl702_romdriver.h"

/******************************************************************************/
__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type AON_Power_On_MBG(void) { return RomDriver_AON_Power_On_MBG(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type AON_Power_Off_MBG(void) { return RomDriver_AON_Power_Off_MBG(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type AON_Power_On_XTAL(void) { return RomDriver_AON_Power_On_XTAL(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) { return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type AON_Power_Off_XTAL(void) { return RomDriver_AON_Power_Off_XTAL(); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION void ASM_Delay_Us(uint32_t core, uint32_t cnt) { RomDriver_ASM_Delay_Us(core, cnt); }

__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_US(uint32_t cnt) { RomDriver_BL702_Delay_US(cnt); }

__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_MS(uint32_t cnt) { RomDriver_BL702_Delay_MS(cnt); }

__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n) { return RomDriver_BL702_MemCpy(dst, src, n); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t *BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n) { return RomDriver_BL702_MemCpy4(dst, src, n); }

// __ALWAYS_INLINE ATTR_TCM_SECTION
// void* BL702_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) {
//     return RomDriver_BL702_MemCpy_Fast(pdst, psrc, n);
// }

__ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) { return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n); }

__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n) { return RomDriver_BL702_MemSet(s, c, n); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t *BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n) { return RomDriver_BL702_MemSet4(dst, val, n); }

__ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n) { return RomDriver_BL702_MemCmp(s1, s2, n); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len) { return RomDriver_BFLB_Soft_CRC32(dataIn, len); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_CLOCK_SECTION GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void) { return RomDriver_GLB_Get_Root_CLK_Sel(); }
#if 0
__ALWAYS_INLINE ATTR_CLOCK_SECTION
    BL_Err_Type
    GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
{
    return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv);
}
#endif
__ALWAYS_INLINE ATTR_CLOCK_SECTION uint8_t GLB_Get_BCLK_Div(void) { return RomDriver_GLB_Get_BCLK_Div(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION uint8_t GLB_Get_HCLK_Div(void) { return RomDriver_GLB_Get_HCLK_Div(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType) { return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) { return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type System_Core_Clock_Update_From_RC32M(void) { return RomDriver_System_Core_Clock_Update_From_RC32M(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) { return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Power_Off_DLL(void) { return RomDriver_GLB_Power_Off_DLL(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType) { return RomDriver_GLB_Power_On_DLL(xtalType); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Enable_DLL_All_Clks(void) { return RomDriver_GLB_Enable_DLL_All_Clks(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk) { return RomDriver_GLB_Enable_DLL_Clk(dllClk); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Disable_DLL_All_Clks(void) { return RomDriver_GLB_Disable_DLL_All_Clks(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk) { return RomDriver_GLB_Disable_DLL_Clk(dllClk); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_SW_System_Reset(void) { return RomDriver_GLB_SW_System_Reset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_SW_CPU_Reset(void) { return RomDriver_GLB_SW_CPU_Reset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_SW_POR_Reset(void) { return RomDriver_GLB_SW_POR_Reset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Select_Internal_Flash(void) { return RomDriver_GLB_Select_Internal_Flash(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Swap_Flash_Pin(void) { return RomDriver_GLB_Swap_Flash_Pin(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin(void) { return RomDriver_GLB_Swap_Flash_CS_IO2_Pin(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin(void) { return RomDriver_GLB_Swap_Flash_IO0_IO3_Pin(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Select_Internal_PSram(void) { return RomDriver_GLB_Select_Internal_PSram(); }

/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
{
    return RomDriver_GLB_GPIO_Init(cfg);
}
#endif

#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
{
    return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin);
}
#endif

#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
{
    return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin);
}
#endif

/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
{
    return RomDriver_GLB_GPIO_Set_HZ(gpioPin);
}
#endif

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Deswap_Flash_Pin(void) { return RomDriver_GLB_Deswap_Flash_Pin(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type GLB_Select_External_Flash(void) { return RomDriver_GLB_Select_External_Flash(); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) { return RomDriver_GLB_GPIO_Get_Fun(gpioPin); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION BL_Sts_Type EF_Ctrl_Busy(void) { return RomDriver_EF_Ctrl_Busy(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Sw_AHB_Clk_0(void) { RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Load_Efuse_R0(void) { RomDriver_EF_Ctrl_Load_Efuse_R0(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Clear(uint32_t index, uint32_t len) { RomDriver_EF_Ctrl_Clear(index, len); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) { return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) { RomDriver_EF_Ctrl_Read_RC32K_Trim(trim); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) { RomDriver_EF_Ctrl_Read_RC32M_Trim(trim); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Trim_RC32M(void) { return RomDriver_PDS_Trim_RC32M(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void) { return RomDriver_PDS_Select_RC32M_As_PLL_Ref(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void) { return RomDriver_PDS_Select_XTAL_As_PLL_Ref(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType) { return RomDriver_PDS_Power_On_PLL(xtalType); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Enable_PLL_All_Clks(void) { return RomDriver_PDS_Enable_PLL_All_Clks(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Disable_PLL_All_Clks(void) { return RomDriver_PDS_Disable_PLL_All_Clks(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk) { return RomDriver_PDS_Enable_PLL_Clk(pllClk); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk) { return RomDriver_PDS_Disable_PLL_Clk(pllClk); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type PDS_Power_Off_PLL(void) { return RomDriver_PDS_Power_Off_PLL(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Reset(void) { RomDriver_PDS_Reset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt) { RomDriver_PDS_Enable(cfg, pdsSleepCnt); }

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Time_Config(uint32_t sleepDuration) { RomDriver_PDS_Auto_Time_Config(sleepDuration); }

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable) {
  RomDriver_PDS_Auto_Enable(powerCfg, normalCfg, enable);
}

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain) { RomDriver_PDS_Manual_Force_Turn_Off(domain); }

__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain) { RomDriver_PDS_Manual_Force_Turn_On(domain); }
/******************************************************************************/

/******************************************************************************/
#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
{
    RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel);
}
#endif

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type HBN_Reset(void) { return RomDriver_HBN_Reset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask) {
  return RomDriver_HBN_GPIO_Dbg_Pull_Cfg(pupdEn, dlyEn, dlySec, gpioIrq, gpioMask);
}

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type HBN_Trim_RC32K(void) { return RomDriver_HBN_Trim_RC32K(); }

__ALWAYS_INLINE ATTR_CLOCK_SECTION BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) { return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) { return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) {
  return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) {
  return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, startaddr, endaddr);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, data, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, data, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) {
  return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, ioMode, data);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) {
  return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, ioMode, data);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) {
  return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, ioMode, data, idLen);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) { return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); }

__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len) {
  return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg, ioMode, addr, dst, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len) {
  return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg, ioMode, addr, src, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len) {
  return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg, ioMode, addr, len);
}
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) { RomDriver_SFlash_Init(pSfCtrlCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) { return RomDriver_SFlash_SetSPIMode(mode); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
  return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
  return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) {
  return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) {
  return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Busy(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Write_Enable(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Qspi_Enable(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) { RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Chip_Erase(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) { return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) { return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) { return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) { return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) { RomDriver_SFlash_GetUniqueId(data, idLen); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) { RomDriver_SFlash_GetJedecId(flashCfg, data); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetDeviceId(uint8_t *data) { RomDriver_SFlash_GetDeviceId(data); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Powerdown(void) { RomDriver_SFlash_Powerdown(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) { RomDriver_SFlash_Releae_Powerdown(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) {
  return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead);
}

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) { RomDriver_SFlash_SetBurstWrap(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) { RomDriver_SFlash_DisableBurstWrap(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Software_Reset(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) { return RomDriver_SFlash_Reset_Continue_Read(flashCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) {
  return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) {
  return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) {
  return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable);
}

__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Cache_Read_Disable(void) { RomDriver_SFlash_Cache_Read_Disable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len);
}
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable) { return RomDriver_L1C_Cache_Enable_Set(wayDisable); }

__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) { RomDriver_L1C_Cache_Write_Set(wtEn, wbEn, waEn); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type L1C_Cache_Flush(uint8_t wayDisable) { return RomDriver_L1C_Cache_Flush(wayDisable); }

__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) { RomDriver_L1C_Cache_Hit_Count_Get(hitCountLow, hitCountHigh); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t L1C_Cache_Miss_Count_Get(void) { return RomDriver_L1C_Cache_Miss_Count_Get(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Read_Disable(void) { RomDriver_L1C_Cache_Read_Disable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap) { return RomDriver_L1C_Set_Wrap(wrap); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal) { return RomDriver_L1C_Set_Way_Disable(disableVal); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable) { return RomDriver_L1C_IROM_2T_Access_Set(enable); }
/******************************************************************************/

/******************************************************************************/
__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) { RomDriver_SF_Ctrl_Enable(cfg); }

#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
{
    RomDriver_SF_Ctrl_Psram_Init(sfCtrlPsramCfg);
}
#endif

__ALWAYS_INLINE ATTR_TCM_SECTION uint8_t SF_Ctrl_Get_Clock_Delay(void) { return RomDriver_SF_Ctrl_Get_Clock_Delay(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Clock_Delay(uint8_t delay) { RomDriver_SF_Ctrl_Set_Clock_Delay(delay); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) { RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) { RomDriver_SF_Ctrl_Set_Owner(owner); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Disable(void) { RomDriver_SF_Ctrl_Disable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) { RomDriver_SF_Ctrl_Select_Pad(sel); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) { RomDriver_SF_Ctrl_Select_Bank(sel); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_BE(void) { RomDriver_SF_Ctrl_AES_Enable_BE(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_LE(void) { RomDriver_SF_Ctrl_AES_Enable_LE(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) {
  RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked);
}

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) { RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) { RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) { RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) { RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable(void) { RomDriver_SF_Ctrl_AES_Enable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Disable(void) { RomDriver_SF_Ctrl_AES_Disable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint8_t SF_Ctrl_Is_AES_Enable(void) { return RomDriver_SF_Ctrl_Is_AES_Enable(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) { RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); }

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t SF_Ctrl_Get_Flash_Image_Offset(void) { return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) { RomDriver_SF_Ctrl_Select_Clock(sahbType); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) { RomDriver_SF_Ctrl_SendCmd(cfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) { RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmdValid); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) { RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmdValid); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) { RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmdValid); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Sts_Type SF_Ctrl_GetBusyState(void) { return RomDriver_SF_Ctrl_GetBusyState(); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) { RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); }

__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) { RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) { return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); }

#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault)
{
    RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
}
#endif

__ALWAYS_INLINE ATTR_TCM_SECTION uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) {
  return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg);
}
/******************************************************************************/

/******************************************************************************/
#if 0
__ALWAYS_INLINE ATTR_TCM_SECTION
void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg)
{
    RomDriver_Psram_Init(psramCfg, cmdsCfg, sfCtrlPsramCfg);
}
#endif

__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) { RomDriver_Psram_ReadReg(psramCfg, regValue); }

__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) { RomDriver_Psram_WriteReg(psramCfg, regValue); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) { return RomDriver_Psram_SetDriveStrength(psramCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) { return RomDriver_Psram_SetBurstWrap(psramCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) { RomDriver_Psram_ReadId(psramCfg, data); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) { return RomDriver_Psram_EnterQuadMode(psramCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) { return RomDriver_Psram_ExitQuadMode(psramCfg); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) { return RomDriver_Psram_ToggleBurstLength(psramCfg, ctrlMode); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) { return RomDriver_Psram_SoftwareReset(psramCfg, ctrlMode); }

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) {
  return RomDriver_Psram_Set_IDbus_Cfg(psramCfg, ioMode, addr, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) {
  return RomDriver_Psram_Cache_Write_Set(psramCfg, ioMode, wtEn, wbEn, waEn);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_Psram_Write(psramCfg, ioMode, addr, data, len);
}

__ALWAYS_INLINE ATTR_TCM_SECTION BL_Err_Type Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  return RomDriver_Psram_Read(psramCfg, ioMode, addr, data, len);
}
/******************************************************************************/


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_romdriver.c
================================================
#include "bl702_romdriver.h"
#include 

/** @addtogroup  BL702_Periph_Driver
 *  @{
 */

/** @defgroup ROMDRIVER
 *  @brief ROMDRIVER common functions
 *  @{
 */

/** @defgroup ROMDRIVER_Private_Type
 *  @{
 */
uint32_t const romDriverTable[] = {
    0x07020001,
    0x00000000,
    0x00000000,
    0x00000000,

    [ROM_API_INDEX_AON_Power_On_MBG]     = (uint32_t)AON_Power_On_MBG,
    [ROM_API_INDEX_AON_Power_Off_MBG]    = (uint32_t)AON_Power_Off_MBG,
    [ROM_API_INDEX_AON_Power_On_XTAL]    = (uint32_t)AON_Power_On_XTAL,
    [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,
    [ROM_API_INDEX_AON_Power_Off_XTAL]   = (uint32_t)AON_Power_Off_XTAL,

    [ROM_API_INDEX_ASM_Delay_Us]      = (uint32_t)ASM_Delay_Us,
    [ROM_API_INDEX_BL702_Delay_US]    = (uint32_t)BL702_Delay_US,
    [ROM_API_INDEX_BL702_Delay_MS]    = (uint32_t)BL702_Delay_MS,
    [ROM_API_INDEX_BL702_MemCpy]      = (uint32_t)BL702_MemCpy,
    [ROM_API_INDEX_BL702_MemCpy4]     = (uint32_t)BL702_MemCpy4,
    [ROM_API_INDEX_BL702_MemCpy_Fast] = (uint32_t)BL702_MemCpy_Fast,
    [ROM_API_INDEX_ARCH_MemCpy_Fast]  = (uint32_t)ARCH_MemCpy_Fast,
    [ROM_API_INDEX_BL702_MemSet]      = (uint32_t)BL702_MemSet,
    [ROM_API_INDEX_BL702_MemSet4]     = (uint32_t)BL702_MemSet4,
    [ROM_API_INDEX_BL702_MemCmp]      = (uint32_t)BL702_MemCmp,
    [ROM_API_INDEX_BFLB_Soft_CRC32]   = (uint32_t)BFLB_Soft_CRC32,

    [ROM_API_INDEX_GLB_Get_Root_CLK_Sel]                = (uint32_t)GLB_Get_Root_CLK_Sel,
    [ROM_API_INDEX_GLB_Set_System_CLK_Div]              = (uint32_t)GLB_Set_System_CLK_Div,
    [ROM_API_INDEX_GLB_Get_BCLK_Div]                    = (uint32_t)GLB_Get_BCLK_Div,
    [ROM_API_INDEX_GLB_Get_HCLK_Div]                    = (uint32_t)GLB_Get_HCLK_Div,
    [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL]     = (uint32_t)Update_SystemCoreClockWith_XTAL,
    [ROM_API_INDEX_GLB_Set_System_CLK]                  = (uint32_t)GLB_Set_System_CLK,
    [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M,
    [ROM_API_INDEX_GLB_Set_SF_CLK]                      = (uint32_t)GLB_Set_SF_CLK,
    [ROM_API_INDEX_GLB_Power_Off_DLL]                   = (uint32_t)GLB_Power_Off_DLL,
    [ROM_API_INDEX_GLB_Power_On_DLL]                    = (uint32_t)GLB_Power_On_DLL,
    [ROM_API_INDEX_GLB_Enable_DLL_All_Clks]             = (uint32_t)GLB_Enable_DLL_All_Clks,
    [ROM_API_INDEX_GLB_Enable_DLL_Clk]                  = (uint32_t)GLB_Enable_DLL_Clk,
    [ROM_API_INDEX_GLB_Disable_DLL_All_Clks]            = (uint32_t)GLB_Disable_DLL_All_Clks,
    [ROM_API_INDEX_GLB_Disable_DLL_Clk]                 = (uint32_t)GLB_Disable_DLL_Clk,
    [ROM_API_INDEX_GLB_SW_System_Reset]                 = (uint32_t)GLB_SW_System_Reset,
    [ROM_API_INDEX_GLB_SW_CPU_Reset]                    = (uint32_t)GLB_SW_CPU_Reset,
    [ROM_API_INDEX_GLB_SW_POR_Reset]                    = (uint32_t)GLB_SW_POR_Reset,
    [ROM_API_INDEX_GLB_Select_Internal_Flash]           = (uint32_t)GLB_Select_Internal_Flash,
    [ROM_API_INDEX_GLB_Swap_Flash_Pin]                  = (uint32_t)GLB_Swap_Flash_Pin,
    [ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin]           = (uint32_t)GLB_Swap_Flash_CS_IO2_Pin,
    [ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin]          = (uint32_t)GLB_Swap_Flash_IO0_IO3_Pin,
    [ROM_API_INDEX_GLB_Select_Internal_PSram]           = (uint32_t)GLB_Select_Internal_PSram,
    [ROM_API_INDEX_GLB_GPIO_Init]                       = (uint32_t)GLB_GPIO_Init,
    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]              = (uint32_t)GLB_GPIO_OUTPUT_Enable,
    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]             = (uint32_t)GLB_GPIO_OUTPUT_Disable,
    [ROM_API_INDEX_GLB_GPIO_Set_HZ]                     = (uint32_t)GLB_GPIO_Set_HZ,
    [ROM_API_INDEX_GLB_Deswap_Flash_Pin]                = (uint32_t)GLB_Deswap_Flash_Pin,
    [ROM_API_INDEX_GLB_Select_External_Flash]           = (uint32_t)GLB_Select_External_Flash,
    [ROM_API_INDEX_GLB_GPIO_Get_Fun]                    = (uint32_t)GLB_GPIO_Get_Fun,

    [ROM_API_INDEX_EF_Ctrl_Busy]            = (uint32_t)EF_Ctrl_Busy,
    [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]    = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
    [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]   = (uint32_t)EF_Ctrl_Load_Efuse_R0,
    [ROM_API_INDEX_EF_Ctrl_Clear]           = (uint32_t)EF_Ctrl_Clear,
    [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,
    [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
    [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,

    [ROM_API_INDEX_PDS_Trim_RC32M]              = (uint32_t)PDS_Trim_RC32M,
    [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref,
    [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref]  = (uint32_t)PDS_Select_XTAL_As_PLL_Ref,
    [ROM_API_INDEX_PDS_Power_On_PLL]            = (uint32_t)PDS_Power_On_PLL,
    [ROM_API_INDEX_PDS_Enable_PLL_All_Clks]     = (uint32_t)PDS_Enable_PLL_All_Clks,
    [ROM_API_INDEX_PDS_Disable_PLL_All_Clks]    = (uint32_t)PDS_Disable_PLL_All_Clks,
    [ROM_API_INDEX_PDS_Enable_PLL_Clk]          = (uint32_t)PDS_Enable_PLL_Clk,
    [ROM_API_INDEX_PDS_Disable_PLL_Clk]         = (uint32_t)PDS_Disable_PLL_Clk,
    [ROM_API_INDEX_PDS_Power_Off_PLL]           = (uint32_t)PDS_Power_Off_PLL,
    [ROM_API_INDEX_PDS_Reset]                   = (uint32_t)PDS_Reset,
    [ROM_API_INDEX_PDS_Enable]                  = (uint32_t)PDS_Enable,
    [ROM_API_INDEX_PDS_Auto_Time_Config]        = (uint32_t)PDS_Auto_Time_Config,
    [ROM_API_INDEX_PDS_Auto_Enable]             = (uint32_t)PDS_Auto_Enable,
    [ROM_API_INDEX_PDS_Manual_Force_Turn_Off]   = (uint32_t)PDS_Manual_Force_Turn_Off,
    [ROM_API_INDEX_PDS_Manual_Force_Turn_On]    = (uint32_t)PDS_Manual_Force_Turn_On,

    [ROM_API_INDEX_HBN_Enable]            = (uint32_t)HBN_Enable,
    [ROM_API_INDEX_HBN_Reset]             = (uint32_t)HBN_Reset,
    [ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO_Dbg_Pull_Cfg,
    [ROM_API_INDEX_HBN_Trim_RC32K]        = (uint32_t)HBN_Trim_RC32K,
    [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]  = (uint32_t)HBN_Set_ROOT_CLK_Sel,

    [ROM_API_INDEX_XIP_SFlash_State_Save]               = (uint32_t)XIP_SFlash_State_Save,
    [ROM_API_INDEX_XIP_SFlash_State_Restore]            = (uint32_t)XIP_SFlash_State_Restore,
    [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]          = (uint32_t)XIP_SFlash_Erase_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]          = (uint32_t)XIP_SFlash_Write_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]           = (uint32_t)XIP_SFlash_Read_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]     = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]    = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]    = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,
    [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,
    // [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock,
    // [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock,
    // [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock,

    [ROM_API_INDEX_SFlash_Init]                      = (uint32_t)SFlash_Init,
    [ROM_API_INDEX_SFlash_SetSPIMode]                = (uint32_t)SFlash_SetSPIMode,
    [ROM_API_INDEX_SFlash_Read_Reg]                  = (uint32_t)SFlash_Read_Reg,
    [ROM_API_INDEX_SFlash_Write_Reg]                 = (uint32_t)SFlash_Write_Reg,
    [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]         = (uint32_t)SFlash_Read_Reg_With_Cmd,
    [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]        = (uint32_t)SFlash_Write_Reg_With_Cmd,
    [ROM_API_INDEX_SFlash_Busy]                      = (uint32_t)SFlash_Busy,
    [ROM_API_INDEX_SFlash_Write_Enable]              = (uint32_t)SFlash_Write_Enable,
    [ROM_API_INDEX_SFlash_Qspi_Enable]               = (uint32_t)SFlash_Qspi_Enable,
    [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
    [ROM_API_INDEX_SFlash_Chip_Erase]                = (uint32_t)SFlash_Chip_Erase,
    [ROM_API_INDEX_SFlash_Sector_Erase]              = (uint32_t)SFlash_Sector_Erase,
    [ROM_API_INDEX_SFlash_Blk32_Erase]               = (uint32_t)SFlash_Blk32_Erase,
    [ROM_API_INDEX_SFlash_Blk64_Erase]               = (uint32_t)SFlash_Blk64_Erase,
    [ROM_API_INDEX_SFlash_Erase]                     = (uint32_t)SFlash_Erase,
    [ROM_API_INDEX_SFlash_Program]                   = (uint32_t)SFlash_Program,
    [ROM_API_INDEX_SFlash_GetUniqueId]               = (uint32_t)SFlash_GetUniqueId,
    [ROM_API_INDEX_SFlash_GetJedecId]                = (uint32_t)SFlash_GetJedecId,
    [ROM_API_INDEX_SFlash_GetDeviceId]               = (uint32_t)SFlash_GetDeviceId,
    [ROM_API_INDEX_SFlash_Powerdown]                 = (uint32_t)SFlash_Powerdown,
    [ROM_API_INDEX_SFlash_Releae_Powerdown]          = (uint32_t)SFlash_Releae_Powerdown,
    [ROM_API_INDEX_SFlash_Restore_From_Powerdown]    = (uint32_t)SFlash_Restore_From_Powerdown,
    [ROM_API_INDEX_SFlash_SetBurstWrap]              = (uint32_t)SFlash_SetBurstWrap,
    [ROM_API_INDEX_SFlash_DisableBurstWrap]          = (uint32_t)SFlash_DisableBurstWrap,
    [ROM_API_INDEX_SFlash_Software_Reset]            = (uint32_t)SFlash_Software_Reset,
    [ROM_API_INDEX_SFlash_Reset_Continue_Read]       = (uint32_t)SFlash_Reset_Continue_Read,
    [ROM_API_INDEX_SFlash_Set_IDbus_Cfg]             = (uint32_t)SFlash_Set_IDbus_Cfg,
    [ROM_API_INDEX_SFlash_IDbus_Read_Enable]         = (uint32_t)SFlash_IDbus_Read_Enable,
    [ROM_API_INDEX_SFlash_Cache_Read_Enable]         = (uint32_t)SFlash_Cache_Read_Enable,
    [ROM_API_INDEX_SFlash_Cache_Read_Disable]        = (uint32_t)SFlash_Cache_Read_Disable,
    [ROM_API_INDEX_SFlash_Read]                      = (uint32_t)SFlash_Read,

    [ROM_API_INDEX_L1C_Cache_Enable_Set]     = (uint32_t)L1C_Cache_Enable_Set,
    [ROM_API_INDEX_L1C_Cache_Write_Set]      = (uint32_t)L1C_Cache_Write_Set,
    [ROM_API_INDEX_L1C_Cache_Flush]          = (uint32_t)L1C_Cache_Flush,
    [ROM_API_INDEX_L1C_Cache_Hit_Count_Get]  = (uint32_t)L1C_Cache_Hit_Count_Get,
    [ROM_API_INDEX_L1C_Cache_Miss_Count_Get] = (uint32_t)L1C_Cache_Miss_Count_Get,
    [ROM_API_INDEX_L1C_Cache_Read_Disable]   = (uint32_t)L1C_Cache_Read_Disable,
    [ROM_API_INDEX_L1C_Set_Wrap]             = (uint32_t)L1C_Set_Wrap,
    [ROM_API_INDEX_L1C_Set_Way_Disable]      = (uint32_t)L1C_Set_Way_Disable,
    [ROM_API_INDEX_L1C_IROM_2T_Access_Set]   = (uint32_t)L1C_IROM_2T_Access_Set,

    [ROM_API_INDEX_SF_Ctrl_Enable]                 = (uint32_t)SF_Ctrl_Enable,
    [ROM_API_INDEX_SF_Ctrl_Psram_Init]             = (uint32_t)SF_Ctrl_Psram_Init,
    [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]        = (uint32_t)SF_Ctrl_Get_Clock_Delay,
    [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]        = (uint32_t)SF_Ctrl_Set_Clock_Delay,
    [ROM_API_INDEX_SF_Ctrl_Cmds_Set]               = (uint32_t)SF_Ctrl_Cmds_Set,
    [ROM_API_INDEX_SF_Ctrl_Set_Owner]              = (uint32_t)SF_Ctrl_Set_Owner,
    [ROM_API_INDEX_SF_Ctrl_Disable]                = (uint32_t)SF_Ctrl_Disable,
    [ROM_API_INDEX_SF_Ctrl_Select_Pad]             = (uint32_t)SF_Ctrl_Select_Pad,
    [ROM_API_INDEX_SF_Ctrl_Select_Bank]            = (uint32_t)SF_Ctrl_Select_Bank,
    [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]          = (uint32_t)SF_Ctrl_AES_Enable_BE,
    [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]          = (uint32_t)SF_Ctrl_AES_Enable_LE,
    [ROM_API_INDEX_SF_Ctrl_AES_Set_Region]         = (uint32_t)SF_Ctrl_AES_Set_Region,
    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key]            = (uint32_t)SF_Ctrl_AES_Set_Key,
    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]         = (uint32_t)SF_Ctrl_AES_Set_Key_BE,
    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV]             = (uint32_t)SF_Ctrl_AES_Set_IV,
    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]          = (uint32_t)SF_Ctrl_AES_Set_IV_BE,
    [ROM_API_INDEX_SF_Ctrl_AES_Enable]             = (uint32_t)SF_Ctrl_AES_Enable,
    [ROM_API_INDEX_SF_Ctrl_AES_Disable]            = (uint32_t)SF_Ctrl_AES_Disable,
    [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]          = (uint32_t)SF_Ctrl_Is_AES_Enable,
    [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,
    [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,
    [ROM_API_INDEX_SF_Ctrl_Select_Clock]           = (uint32_t)SF_Ctrl_Select_Clock,
    [ROM_API_INDEX_SF_Ctrl_SendCmd]                = (uint32_t)SF_Ctrl_SendCmd,
    [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]  = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set,
    [ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Write_Icache_Set,
    [ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]  = (uint32_t)SF_Ctrl_Psram_Read_Icache_Set,
    [ROM_API_INDEX_SF_Ctrl_GetBusyState]           = (uint32_t)SF_Ctrl_GetBusyState,
    [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]   = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
    [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]     = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
    [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
    [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]         = (uint32_t)SF_Cfg_Init_Flash_Gpio,
    [ROM_API_INDEX_SF_Cfg_Flash_Identify]          = (uint32_t)SF_Cfg_Flash_Identify,

    [ROM_API_INDEX_Psram_Init]              = (uint32_t)Psram_Init,
    [ROM_API_INDEX_Psram_ReadReg]           = (uint32_t)Psram_ReadReg,
    [ROM_API_INDEX_Psram_WriteReg]          = (uint32_t)Psram_WriteReg,
    [ROM_API_INDEX_Psram_SetDriveStrength]  = (uint32_t)Psram_SetDriveStrength,
    [ROM_API_INDEX_Psram_SetBurstWrap]      = (uint32_t)Psram_SetBurstWrap,
    [ROM_API_INDEX_Psram_ReadId]            = (uint32_t)Psram_ReadId,
    [ROM_API_INDEX_Psram_EnterQuadMode]     = (uint32_t)Psram_EnterQuadMode,
    [ROM_API_INDEX_Psram_ExitQuadMode]      = (uint32_t)Psram_ExitQuadMode,
    [ROM_API_INDEX_Psram_ToggleBurstLength] = (uint32_t)Psram_ToggleBurstLength,
    [ROM_API_INDEX_Psram_SoftwareReset]     = (uint32_t)Psram_SoftwareReset,
    [ROM_API_INDEX_Psram_Set_IDbus_Cfg]     = (uint32_t)Psram_Set_IDbus_Cfg,
    [ROM_API_INDEX_Psram_Cache_Write_Set]   = (uint32_t)Psram_Cache_Write_Set,
    [ROM_API_INDEX_Psram_Write]             = (uint32_t)Psram_Write,
    [ROM_API_INDEX_Psram_Read]              = (uint32_t)Psram_Read,

    [ROM_API_INDEX_FUNC_INVALID_START... ROM_API_INDEX_FUNC_LAST_ENTRY] = 0xdeedbeef,
};

/*@} end of group ROMDRIVER_Private_Type*/

/** @defgroup ROMDRIVER_Private_Defines
 *  @{
 */

/*@} end of group ROMDRIVER_Private_Defines */

/** @defgroup ROMDRIVER_Private_Variables
 *  @{
 */

/*@} end of group ROMDRIVER_Private_Variables */

/** @defgroup ROMDRIVER_Global_Variables
 *  @{
 */

/*@} end of group ROMDRIVER_Global_Variables */

/** @defgroup ROMDRIVER_Private_FunctionDeclaration
 *  @{
 */

/*@} end of group ROMDRIVER_Private_FunctionDeclaration */

/** @defgroup ROMDRIVER_Private_Functions
 *  @{
 */

/*@} end of group ROMDRIVER_Private_Functions */

/** @defgroup ROMDRIVER_Public_Functions
 *  @{
 */

/*@} end of group ROMDRIVER_Public_Functions */

/*@} end of group ROMDRIVER_COMMON */

/*@} end of group BL702_Periph_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_dbg.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sec_dbg.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sec_dbg.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SEC_DBG
 *  @{
 */

/** @defgroup  SEC_DBG_Private_Macros
 *  @{
 */

/*@} end of group SEC_DBG_Private_Macros */

/** @defgroup  SEC_DBG_Private_Types
 *  @{
 */

/*@} end of group SEC_DBG_Private_Types */

/** @defgroup  SEC_DBG_Private_Variables
 *  @{
 */

/*@} end of group SEC_DBG_Private_Variables */

/** @defgroup  SEC_DBG_Global_Variables
 *  @{
 */

/*@} end of group SEC_DBG_Global_Variables */

/** @defgroup  SEC_DBG_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SEC_DBG_Private_Fun_Declaration */

/** @defgroup  SEC_DBG_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Sec Dbg read chip ID
                                                                                *
                                                                                * @param  id[8]: chip ID buffer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) {
  uint32_t idLow, idHigh;

  idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW);
  BL_WRWD_TO_BYTEP(id, idLow);

  idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH);
  BL_WRWD_TO_BYTEP((id + 4), idHigh);
}

/****************************************************************************/ /**
                                                                                * @brief  Sec Dbg read MAC address
                                                                                *
                                                                                * @param  macAddr[6]: MAC address buffer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]) {
  uint32_t macLow, macHigh;

  macLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_LOW);
  BL_WRWD_TO_BYTEP(macAddr, macLow);

  macHigh    = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_WIFI_MAC_HIGH);
  macAddr[4] = (macHigh >> 0) & 0xff;
  macAddr[5] = (macHigh >> 8) & 0xff;
}

/****************************************************************************/ /**
                                                                                * @brief  Sec Dbg read debug mode
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return debug mode status
                                                                                *
                                                                                *******************************************************************************/
uint32_t Sec_Dbg_Read_Dbg_Mode(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE); }

/****************************************************************************/ /**
                                                                                * @brief  Sec Dbg read debug enable status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return enable status
                                                                                *
                                                                                *******************************************************************************/
uint32_t Sec_Dbg_Read_Dbg_Enable(void) { return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA); }

/*@} end of group SEC_DBG_Public_Functions */

/*@} end of group SEC_DBG */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sec_eng.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sec_eng.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sec_eng.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SEC_ENG
 *  @{
 */

/** @defgroup  SEC_ENG_Private_Macros
 *  @{
 */
#define PUT_UINT32_BE(n, b, i)                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    (b)[(i)]     = (uint8_t)((n) >> 24);                                                                                                                                                               \
    (b)[(i) + 1] = (uint8_t)((n) >> 16);                                                                                                                                                               \
    (b)[(i) + 2] = (uint8_t)((n) >> 8);                                                                                                                                                                \
    (b)[(i) + 3] = (uint8_t)((n));                                                                                                                                                                     \
  }
#define PUT_UINT64_BE(n, b, i)                                                                                                                                                                         \
  {                                                                                                                                                                                                    \
    (b)[(i)]     = (uint8_t)((n) >> 56);                                                                                                                                                               \
    (b)[(i) + 1] = (uint8_t)((n) >> 48);                                                                                                                                                               \
    (b)[(i) + 2] = (uint8_t)((n) >> 40);                                                                                                                                                               \
    (b)[(i) + 3] = (uint8_t)((n) >> 32);                                                                                                                                                               \
    (b)[(i) + 4] = (uint8_t)((n) >> 24);                                                                                                                                                               \
    (b)[(i) + 5] = (uint8_t)((n) >> 16);                                                                                                                                                               \
    (b)[(i) + 6] = (uint8_t)((n) >> 8);                                                                                                                                                                \
    (b)[(i) + 7] = (uint8_t)((n));                                                                                                                                                                     \
  }
#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT  (100 * 160 * 1000)
#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT  (100 * 160 * 1000)
#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 160 * 1000)
#define SEC_ENG_PKA_INT_TIMEOUT_COUNT   (100 * 160 * 1000)
#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 160 * 1000)

/*@} end of group SEC_ENG_Private_Macros */

/** @defgroup  SEC_ENG_Private_Types
 *  @{
 */
struct pka0_pld_cfg {
  union {
    struct {
      uint32_t size        : 12; /*[11: 0],       r/w,        0x0 */
      uint32_t d_reg_index : 8;  /*[19:12],        r/w,        0x0 */
      uint32_t d_reg_type  : 4;  /*[23:20],        r/w,        0x0 */
      uint32_t op          : 7;  /*[30:24],        r/w,        0x0 */
      uint32_t last_op     : 1;  /*[31:31],        r/w,        0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_pldi_cfg {
  union {
    struct {
      uint32_t rsvd        : 12; /*[11: 0],       r/w,        0x0 */
      uint32_t d_reg_index : 8;  /*[19:12],        r/w,        0x0 */
      uint32_t d_reg_type  : 4;  /*[23:20],        r/w,        0x0 */
      uint32_t op          : 7;  /*[30:24],        r/w,        0x0 */
      uint32_t last_op     : 1;  /*[31:31],        r/w,        0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_common_op_first_cfg {
  union {
    struct {
      uint32_t s0_reg_idx  : 8; /*[7: 0],       r/w,        0x0 */
      uint32_t s0_reg_type : 4; /*[11:8],       r/w,        0x0 */
      uint32_t d_reg_idx   : 8; /*[19:12],      r/w,        0x0 */
      uint32_t d_reg_type  : 4; /*[23:20],      r/w,        0x0 */
      uint32_t op          : 7; /*[30:24],      r/w,        0x0 */
      uint32_t last_op     : 1; /*[31:31],      r/w,        0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_common_op_snd_cfg_S1_only {
  union {
    struct {
      uint32_t reserved_0_11  : 12; /*[11: 0],       rsvd,       0x0 */
      uint32_t s1_reg_idx     : 8;  /*[19:12],       r/w,        0x0 */
      uint32_t s1_reg_type    : 4;  /*[23:20],       r/w,        0x0 */
      uint32_t reserved_24_31 : 8;  /*[31:24],       rsvd,       0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_common_op_snd_cfg_S2_only {
  union {
    struct {
      uint32_t s2_reg_idx     : 8;  /*[7 : 0],       r/w,        0x0 */
      uint32_t s2_reg_type    : 4;  /*[11: 8],       r/w,        0x0 */
      uint32_t reserved_12_31 : 20; /*[31:12],       rsvd,       0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_common_op_snd_cfg_S1_S2 {
  union {
    struct {
      uint32_t s2_reg_idx     : 8; /*[7 : 0],       r/w,        0x0 */
      uint32_t s2_reg_type    : 4; /*[11: 8],       r/w,        0x0 */
      uint32_t s1_reg_idx     : 8; /*[19:12],       r/w,        0x0 */
      uint32_t s1_reg_type    : 4; /*[23:20],       r/w,        0x0 */
      uint32_t reserved_24_31 : 8; /*[31:24],       rsvd,       0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

struct pka0_bit_shift_op_cfg {
  union {
    struct {
      uint32_t bit_shift      : 15; /*[14: 0],       r/w,        0x0 */
      uint32_t reserved_24_31 : 17; /*[31:15],       rsvd,        0x0 */
    } BF;
    uint32_t WORD;
  } value;
};

/*@} end of group SEC_ENG_Private_Types */

/** @defgroup  SEC_ENG_Private_Variables
 *  @{
 */
static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = {NULL};

/*@} end of group SEC_ENG_Private_Variables */

/** @defgroup  SEC_ENG_Global_Variables
 *  @{
 */

/*@} end of group SEC_ENG_Global_Variables */

/** @defgroup  SEC_ENG_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SEC_ENG_Private_Fun_Declaration */

/** @defgroup  SEC_ENG_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  SHA256 initialization function
                                                                                *
                                                                                * @param  shaCtx: SHA256 context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  shaType: SHA type
                                                                                * @param  shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes
                                                                                * @param  padding[16]: SHA padding buffer for store padding data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16]) {
  uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));
  CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType));

  /* Deal SHA control register to set SHA mode */
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE, shaType);
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);

  /* Clear context */
  memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx));

  /* Init temp buffer and padding buffer */
  shaCtx->shaBuf     = shaTmpBuf;
  shaCtx->shaPadding = padding;
  BL702_MemSet(shaCtx->shaPadding, 0, 64);
  BL702_MemSet(shaCtx->shaPadding, 0x80, 1);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  SHA start function
                                                                                *
                                                                                * @param  shaNo: SHA ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) {
  uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Set SHA enable */
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);

  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN);
  /* Hash sel 0 for new start */
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL);

  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  SHA256 update input data function
                                                                                *
                                                                                * @param  shaCtx: SHA256 context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  input: SHA input data pointer, and the address should be word align
                                                                                * @param  len: SHA input data length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) {
  uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
  uint32_t tmpVal;
  uint32_t fill;
  uint32_t left;
  uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  if (len == 0) {
    return SUCCESS;
  }

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

  /* SHA need set se_sha_sel to 1 to keep the last SHA state */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed);

  left = shaCtx->total[0] & 0x3F;
  fill = 64 - left;

  shaCtx->total[0] += (uint32_t)len;
  shaCtx->total[0] &= 0xFFFFFFFF;

  if (shaCtx->total[0] < (uint32_t)len) {
    shaCtx->total[1]++;
  }

  if (left && len >= fill) {
    BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);
    /* Set data source address */
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)shaCtx->shaBuf);

    /* Set data length */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, 1);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);
    /* Trigger */
    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);

    shaCtx->shaFeed = 1;
    input += fill;
    len -= fill;
    left = 0;
  }

  fill = len / 64;
  len  = len % 64;

  if (fill > 0) {
    /* Wait finished */
    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

    do {
      tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

    /* SHA need set se_sha_sel to 1 to keep the last sha state */
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_HASH_SEL, shaCtx->shaFeed);

    /* Fill data */
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_MSA, (uint32_t)input);

    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MSG_LEN, fill);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);

    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_TRIG_1T);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);

    input += (fill * 64);
    shaCtx->shaFeed = 1;
  }

  if (len > 0) {
    /* Wait finished */
    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

    do {
      tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

    /* Copy left data into temp buffer */
    BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);
  }

  /* Wait finished */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SHA256 finish to get output function
                                                                                *
                                                                                * @param  shaCtx: SHA256 context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  hash: SHA output data of SHA result
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) {
  uint32_t last, padn;
  uint32_t high, low;
  uint8_t  shaMode;
  uint8_t  msgLen[8];
  uint8_t *p    = (uint8_t *)hash;
  uint32_t SHAx = SEC_ENG_BASE + SEC_ENG_SHA_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

  high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);
  low  = (shaCtx->total[0] << 3);

  PUT_UINT32_BE(high, msgLen, 0);
  PUT_UINT32_BE(low, msgLen, 4);

  last = shaCtx->total[0] & 0x3F;
  padn = (last < 56) ? (56 - last) : (120 - last);

  Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);

  /* Wait for  shaPadding idle */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

  BL702_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8);
  Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8);

  /* Wait finished */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_BUSY));

  tmpVal  = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
  shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_MODE);
  /* Copy SHA value */
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_0);
  *p++   = (tmpVal & 0xff);
  *p++   = ((tmpVal >> 8) & 0xff);
  *p++   = ((tmpVal >> 16) & 0xff);
  *p++   = ((tmpVal >> 24) & 0xff);
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_1);
  *p++   = (tmpVal & 0xff);
  *p++   = ((tmpVal >> 8) & 0xff);
  *p++   = ((tmpVal >> 16) & 0xff);
  *p++   = ((tmpVal >> 24) & 0xff);
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_2);
  *p++   = (tmpVal & 0xff);
  *p++   = ((tmpVal >> 8) & 0xff);
  *p++   = ((tmpVal >> 16) & 0xff);
  *p++   = ((tmpVal >> 24) & 0xff);
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_3);
  *p++   = (tmpVal & 0xff);
  *p++   = ((tmpVal >> 8) & 0xff);
  *p++   = ((tmpVal >> 16) & 0xff);
  *p++   = ((tmpVal >> 24) & 0xff);
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_4);
  *p++   = (tmpVal & 0xff);
  *p++   = ((tmpVal >> 8) & 0xff);
  *p++   = ((tmpVal >> 16) & 0xff);
  *p++   = ((tmpVal >> 24) & 0xff);

  if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_5);
    *p++   = (tmpVal & 0xff);
    *p++   = ((tmpVal >> 8) & 0xff);
    *p++   = ((tmpVal >> 16) & 0xff);
    *p++   = ((tmpVal >> 24) & 0xff);
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_6);
    *p++   = (tmpVal & 0xff);
    *p++   = ((tmpVal >> 8) & 0xff);
    *p++   = ((tmpVal >> 16) & 0xff);
    *p++   = ((tmpVal >> 24) & 0xff);

    if (shaMode == SEC_ENG_SHA256) {
      tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_HASH_L_7);
      *p++   = (tmpVal & 0xff);
      *p++   = ((tmpVal >> 8) & 0xff);
      *p++   = ((tmpVal >> 16) & 0xff);
      *p++   = ((tmpVal >> 24) & 0xff);
    }
  }

  /* Disable SHA engine*/
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_HASH_SEL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_EN);
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SHA enable link mode and set link config address
                                                                                *
                                                                                * @param  shaNo: SHA ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) {
  uint32_t SHAx = SEC_ENG_BASE;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Enable sha and enable link mode */
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  SHA disable link mode
                                                                                *
                                                                                * @param  shaNo: SHA ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) {
  uint32_t SHAx = SEC_ENG_BASE;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Disable sha and disable link mode */
  tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN);
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  SHA256 link mode initialization function
                                                                                *
                                                                                * @param  shaCtx: SHA256 link mode context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  linkAddr: SHA link configure address
                                                                                * @param  shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes
                                                                                * @param  padding[16]: SHA padding buffer for store padding data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]) {
  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Clear context */
  memset(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx));

  /* Init temp buffer,padding buffer and link address */
  shaCtx->shaBuf     = shaTmpBuf;
  shaCtx->shaPadding = padding;
  BL702_MemSet(shaCtx->shaPadding, 0, 64);
  BL702_MemSet(shaCtx->shaPadding, 0x80, 1);
  shaCtx->linkAddr = linkAddr;

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_SHA_IRQn, SEC_SHA_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  SHA256 link mode update input data function
                                                                                *
                                                                                * @param  shaCtx: SHA256 link mode context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  input: SHA input data pointer, and the address should be word align
                                                                                * @param  len: SHA input data length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) {
  uint32_t SHAx = SEC_ENG_BASE;
  uint32_t tmpVal;
  uint32_t fill;
  uint32_t left;
  uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  if (len == 0) {
    return SUCCESS;
  }

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

  /* Set link address */
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);

  left = shaCtx->total[0] & 0x3F;
  fill = 64 - left;

  shaCtx->total[0] += (uint32_t)len;
  shaCtx->total[0] &= 0xFFFFFFFF;

  if (shaCtx->total[0] < (uint32_t)len) {
    shaCtx->total[1]++;
  }

  if (left && len >= fill) {
    BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill);
    /* Set data source address */
    *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)shaCtx->shaBuf;

    /* Set data length */
    *((uint16_t *)shaCtx->linkAddr + 1) = 1;
    /* Trigger */
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));

    /* Choose accumulating last hash in the next time */
    *((uint32_t *)shaCtx->linkAddr) |= 0x40;
    input += fill;
    len -= fill;
    left = 0;
  }

  fill = len / 64;
  len  = len % 64;

  if (fill > 0) {
    /* Wait finished */
    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

    do {
      tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

    /* Fill data */
    *(uint32_t *)(shaCtx->linkAddr + 4) = (uint32_t)input;
    *((uint16_t *)shaCtx->linkAddr + 1) = fill;

    /* Trigger */
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T));

    input += (fill * 64);
    /* Choose accumulating last hash in the next time */
    *((uint32_t *)shaCtx->linkAddr) |= 0x40;
  }

  if (len > 0) {
    /* Wait finished */
    timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

    do {
      tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

    /* Copy left data into temp buffer */
    BL702_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len);
  }

  /* Wait finished */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SHA256 link mode finish to get output function
                                                                                *
                                                                                * @param  shaCtx: SHA256 link mode context pointer
                                                                                * @param  shaNo: SHA ID type
                                                                                * @param  hash: SHA output data of SHA result
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) {
  uint32_t last, padn;
  uint32_t high, low;
  uint8_t  msgLen[8];
  uint32_t SHAx = SEC_ENG_BASE;
  uint32_t tmpVal;
  uint32_t shaMode    = (*(uint32_t *)shaCtx->linkAddr) >> 2 & 0x7;
  uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo));

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

  /* Set link address */
  BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr);

  high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3);
  low  = (shaCtx->total[0] << 3);

  PUT_UINT32_BE(high, msgLen, 0);
  PUT_UINT32_BE(low, msgLen, 4);

  last = shaCtx->total[0] & 0x3F;
  padn = (last < 56) ? (56 - last) : (120 - last);

  Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn);

  /* Wait for shaPadding idle */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

  Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8);

  /* Wait finished */
  timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY));

  /* Get result according to SHA mode,result is placed in (link address + offset:8) */
  switch (shaMode) {
  case 0:
    BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 32);
    break;

  case 1:
    BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 28);
    break;

  case 2:
    BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20);
    break;

  case 3:
    BL702_MemCpy_Fast(hash, (uint8_t *)(shaCtx->linkAddr + 8), 20);
    break;

  default:
    break;
  }

  /* Choose new hash in the next time */
  *((uint32_t *)shaCtx->linkAddr) &= ~0x40;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  AES initialization function
                                                                                *
                                                                                * @param  aesCtx: AES context pointer
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  aesType: AES type:ECB,CTR,CBC
                                                                                * @param  keyType: AES key type:128,256,192
                                                                                * @param  enDecType: AES encryption or decryption
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
  CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType));
  CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType));
  CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType));

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));

  /* Set AES mode type*/
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_BLOCK_MODE, aesType);

  /* Set AES key type */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE, keyType);

  /* Set AES encryption or decryption */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_DEC_EN, enDecType);

  /* Clear dec_key_sel to select new key */
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);

  /* Clear aes iv sel to select new iv */
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL);

  /* Clear AES interrupt */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_INT_CLR_1T);

  /* Enable AES */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN);

  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

  /* Clear AES context */
  memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx));

  /* Enable ID0 Access for HW Key */
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  AES enable function,set AES bigendian
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x0f);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  AES enable function,set AES littleendian
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  BL_WR_REG(AESx, SEC_ENG_SE_AES_ENDIAN, 0x00);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_AES_IRQn, SEC_AES_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  AES enable link mode
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) {
  uint32_t AESx = SEC_ENG_BASE;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  /* Enable aes link mode */
  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));

  /* Enable ID0 Access for HW Key */
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x03);
}

/****************************************************************************/ /**
                                                                                * @brief  AES disable link mode
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) {
  uint32_t AESx = SEC_ENG_BASE;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  /* Disable aes link mode */
  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE));
}

/****************************************************************************/ /**
                                                                                * @brief  AES work in link mode
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  linkAddr: Address of config structure in link mode
                                                                                * @param  in: AES input data buffer to deal with
                                                                                * @param  len: AES input data length
                                                                                * @param  out: AES output data buffer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) {
  uint32_t AESx = SEC_ENG_BASE;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  /* Link address should word align */
  if ((linkAddr & 0x03) != 0 || len % 16 != 0) {
    return ERROR;
  }

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));

  /* Set link address */
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr);

  /* Change source buffer address and destination buffer address */
  *(uint32_t *)(linkAddr + 4) = (uint32_t)in;
  *(uint32_t *)(linkAddr + 8) = (uint32_t)out;

  /* Set data length */
  *((uint16_t *)linkAddr + 1) = len / 16;

  /* Enable aes */
  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));

  /* Start aes engine and wait finishing */
  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T));
  __NOP();
  __NOP();
  timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY));

  /* Disable aes */
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  AES set hardware key source:efuse region for CPU0  or region efuse for CPU1
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  src: AES key source type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));

  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_SBOOT);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_SBOOT_KEY_SEL, src);

  BL_WR_REG(AESx, SEC_ENG_SE_AES_SBOOT, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  AES set KEY and IV
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW
                                                                                * @param  key: AES KEY pointer
                                                                                * @param  iv: AES IV pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;
  uint32_t keyType;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
  CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));

  /* Set IV */
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv)));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv)));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv)));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv)));
  iv += 4;

  /* Select hardware key */
  if (keySrc == SEC_ENG_AES_KEY_HW) {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal);

    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal);

    return;
  }

  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key)));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key)));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key)));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key)));
  key += 4;

  tmpVal  = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
  keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE);

  if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
  } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) {
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key)));
    key += 4;
  }

  /* Select software key */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW);

  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  AES set KEY and IV with bigendian
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW
                                                                                * @param  key: AES KEY pointer
                                                                                * @param  iv: AES IV pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;
  uint32_t keyType;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
  CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc));

  /* Set IV */
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_0, BL_RDWD_FRM_BYTEP(iv));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_1, BL_RDWD_FRM_BYTEP(iv));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_2, BL_RDWD_FRM_BYTEP(iv));
  iv += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_IV_3, BL_RDWD_FRM_BYTEP(iv));
  iv += 4;

  /* Select hardware key */
  if (keySrc == SEC_ENG_AES_KEY_HW) {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_HW);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_0, *key);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_0, tmpVal);

    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_KEY_SEL_1, *key);
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_SEL_1, tmpVal);

    return;
  }

  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_0, BL_RDWD_FRM_BYTEP(key));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_1, BL_RDWD_FRM_BYTEP(key));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_2, BL_RDWD_FRM_BYTEP(key));
  key += 4;
  BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_3, BL_RDWD_FRM_BYTEP(key));
  key += 4;

  tmpVal  = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
  keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MODE);

  if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) {
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key));
    key += 4;
  } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS) {
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_4, BL_RDWD_FRM_BYTEP(key));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_5, BL_RDWD_FRM_BYTEP(key));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_6, BL_RDWD_FRM_BYTEP(key));
    key += 4;
    BL_WR_REG(AESx, SEC_ENG_SE_AES_KEY_7, BL_RDWD_FRM_BYTEP(key));
    key += 4;
  }

  /* Select software key */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_HW_KEY_EN, SEC_ENG_AES_KEY_SW);

  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  AES set counter byte type in CTR mode
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  counterType: AES counter type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType) {
  uint32_t AESx = SEC_ENG_BASE;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo));
  CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType));

  /* Set counter type */
  tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType));
}

/****************************************************************************/ /**
                                                                                * @brief  AES encrypt or decrypt input data
                                                                                *
                                                                                * @param  aesCtx: AES context pointer
                                                                                * @param  aesNo: AES ID type
                                                                                * @param  in: AES input data buffer to deal with
                                                                                * @param  len: AES input data length
                                                                                * @param  out: AES output data buffer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  if (len % 16 != 0) {
    return ERROR;
  }

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));

  /* Clear trigger */
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

  /* Set input and output address */
  BL_WR_REG(AESx, SEC_ENG_SE_AES_MSA, (uint32_t)in);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_MDA, (uint32_t)out);

  /* Set message length */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_MSG_LEN, len / 16);

  if (aesCtx->mode == SEC_ENG_AES_CTR) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);
  }

  /* Set IV sel:0 for new, 1 for last */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_IV_SEL, aesCtx->aesFeed);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

  /* Trigger AES Engine */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_TRIG_1T);
  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

  /* Wait finished */
  timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));

  aesCtx->aesFeed = 1;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  AES finish function, clean register
                                                                                *
                                                                                * @param  aesNo: AES ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) {
  uint32_t AESx = SEC_ENG_BASE + SEC_ENG_AES_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT;

  /* Wait finished */
  do {
    tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_CTRL);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_BUSY));

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_EN);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_DEC_KEY_SEL);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_IV_SEL);

  BL_WR_REG(AESx, SEC_ENG_SE_AES_CTRL, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG enable TRNG interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_Trng_Enable(void) {
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */
  // tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_RESEED_N,0x1ff);

  /* No interrupt as default */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
  /* busy will be set to 1 after trigger, the gap is 1T */
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  do {
    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY));

  /* Clear trng interrupt */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_TRNG_IRQn, SEC_TRNG_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG enable TRNG interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_Trng_Int_Enable(void) {
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK);

  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG disable TRNG interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_Trng_Int_Disable(void) {
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_MASK);

  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG get random data out
                                                                                *
                                                                                * @param  data[32]: TRNG output data
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) {
  uint8_t *p     = (uint8_t *)data;
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;
  uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  /* Trigger */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  /* busy will be set to 1 after trigger, the gap is 1T */
  __NOP();
  __NOP();
  __NOP();
  __NOP();

  do {
    tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_BUSY));

  /* copy trng value */
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7));
  p += 4;

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  /* Clear data */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG get random data out
                                                                                *
                                                                                * @param  data: TRNG output data buffer
                                                                                *
                                                                                * @param  len: total length to get in bytes
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len) {
  uint8_t  tmpBuf[32];
  uint32_t readLen = 0;
  uint32_t i = 0, cnt = 0;

  while (readLen < len) {
    if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) {
      return -1;
    }

    cnt = len - readLen;

    if (cnt > sizeof(tmpBuf)) {
      cnt = sizeof(tmpBuf);
    }

    for (i = 0; i < cnt; i++) {
      data[readLen + i] = tmpBuf[i];
    }

    readLen += cnt;
  }

  return 0;
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG Interrupt Read Trigger
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_Trng_Int_Read_Trigger(void) {
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;

  Sec_Eng_Trng_Int_Enable();

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);
  /* Trigger */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TRNG get random data out with Interrupt
                                                                                *
                                                                                * @param  data[32]: TRNG output data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_Trng_Int_Read(uint8_t data[32]) {
  uint8_t *p     = (uint8_t *)data;
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  /* copy trng value */
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_0));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_1));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_2));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_3));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_4));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_5));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_6));
  p += 4;
  BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_DOUT_7));
  p += 4;

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_TRIG_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  /* Clear data */
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_DOUT_CLR_1T);
  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  Disable TRNG
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_Trng_Disable(void) {
  uint32_t TRNGx = SEC_ENG_BASE + SEC_ENG_TRNG_OFFSET;
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_EN);
  // tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_RESEED_N);
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_INT_CLR_1T);

  BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_CTRL_0, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA Reset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Reset(void) {
  uint8_t val;

  // Disable sec engine
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0);

  // Enable sec engine
  val = 1 << 3;
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA Enable big endian
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_BigEndian_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  PKA Enable little endian
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LittleEndian_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SEC_PKA_IRQn, SEC_PKA_IRQHandler);
#endif
}

/****************************************************************************/ /**
                                                                                * @brief  PKA get status function
                                                                                *
                                                                                * @param  status: Structure pointer of PKA status type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status) {
  uint32_t tmpVal;

  tmpVal              = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
  *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA clear interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Clear_Int(void) {
  uint32_t ctrl;

  ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
  ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);

  ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
  ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA get Register size according to Register type
                                                                                *
                                                                                * @param  reg_type: PKA Register type
                                                                                *
                                                                                * @return Register size
                                                                                *
                                                                                *******************************************************************************/
static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) {
  switch (reg_type) {
  case SEC_ENG_PKA_REG_SIZE_8:
    return 8;

  case SEC_ENG_PKA_REG_SIZE_16:
    return 16;

  case SEC_ENG_PKA_REG_SIZE_32:
    return 32;

  case SEC_ENG_PKA_REG_SIZE_64:
    return 64;

  case SEC_ENG_PKA_REG_SIZE_96:
    return 96;

  case SEC_ENG_PKA_REG_SIZE_128:
    return 128;

  case SEC_ENG_PKA_REG_SIZE_192:
    return 192;

  case SEC_ENG_PKA_REG_SIZE_256:
    return 256;

  case SEC_ENG_PKA_REG_SIZE_384:
    return 384;

  case SEC_ENG_PKA_REG_SIZE_512:
    return 512;

  default:
    return 0;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA set pre-load register configuration
                                                                                *
                                                                                * @param  size: Data size in word to write
                                                                                * @param  regIndex: Register index
                                                                                * @param  regType: Register type
                                                                                * @param  op: PKA operation
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) {
  struct pka0_pld_cfg cfg;

  cfg.value.BF.size        = size;
  cfg.value.BF.d_reg_index = regIndex;
  cfg.value.BF.d_reg_type  = regType;
  cfg.value.BF.op          = op;
  cfg.value.BF.last_op     = lastOp;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA write common operation first configuration
                                                                                *
                                                                                * @param  s0RegIndex: Register index
                                                                                * @param  s0RegType: Register type
                                                                                * @param  dRegIndex: Result Register index
                                                                                * @param  dRegType: Result Register type
                                                                                * @param  op: PKA operation
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, uint8_t op, uint8_t lastOp) {
  struct pka0_common_op_first_cfg cfg;

  cfg.value.BF.s0_reg_idx  = s0RegIndex;
  cfg.value.BF.s0_reg_type = s0RegType;

  if (op != SEC_ENG_PKA_OP_LCMP) {
    cfg.value.BF.d_reg_idx  = dRegIndex;
    cfg.value.BF.d_reg_type = dRegType;
  }

  cfg.value.BF.op      = op;
  cfg.value.BF.last_op = lastOp;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA write common operation second configuration1
                                                                                *
                                                                                * @param  s1RegIndex: Register index
                                                                                * @param  s1RegType: Register type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) {
  struct pka0_common_op_snd_cfg_S1_only cfg;

  cfg.value.BF.s1_reg_idx  = s1RegIndex;
  cfg.value.BF.s1_reg_type = s1RegType;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA write common operation second configuration2
                                                                                *
                                                                                * @param  s2RegIndex: Register index
                                                                                * @param  s2RegType: Register type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) {
  struct pka0_common_op_snd_cfg_S2_only cfg;

  cfg.value.BF.s2_reg_idx  = s2RegIndex;
  cfg.value.BF.s2_reg_type = s2RegType;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA write common operation second configuration1 and configuration 2
                                                                                *
                                                                                * @param  s1RegIndex: Configuration 1 Register index
                                                                                * @param  s1RegType: Configuration 1 Register type
                                                                                * @param  s2RegIndex: Configuration 2 Register index
                                                                                * @param  s2RegType: Configuration 3 Register type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) {
  struct pka0_common_op_snd_cfg_S1_S2 cfg;

  cfg.value.BF.s1_reg_idx  = s1RegIndex;
  cfg.value.BF.s1_reg_type = s1RegType;
  cfg.value.BF.s2_reg_idx  = s2RegIndex;
  cfg.value.BF.s2_reg_type = s2RegType;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA wait for complete interrupt
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) {
  uint32_t pka0_ctrl;
  uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT;

  do {
    pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);
    timeoutCnt--;

    if (timeoutCnt == 0) {
      return TIMEOUT;
    }
  } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  PKA read block data from register
                                                                                *
                                                                                * @param  dest: Pointer to buffer address
                                                                                * @param  src: Pointer to register address
                                                                                * @param  len: Data len in word
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifdef ARCH_ARM
#ifndef __GNUC__
__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  PUSH{R3 - R6, LR} Start0 CMP R2, #4 BLT Finish0 LDR R3, [R1] LDR R4, [R1] LDR R5, [R1] LDR R6, [R1] STMIA R0 !, {R3 - R6} SUBS R2, R2, #4 B Start0 Finish0 POP { R3 - R6, PC }
}
#else
void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  __asm__ __volatile__("push {r3-r6,lr}\n\t"
                       "Start0 :"
                       "cmp   r2,#4\n\t"
                       "blt   Finish0\n\t"
                       "ldr   r3,[r1]\n\t"
                       "ldr   r4,[r1]\n\t"
                       "ldr   r5,[r1]\n\t"
                       "ldr   r6,[r1]\n\t"
                       "stmia r0!,{r3-r6}\n\t"
                       "sub   r2,r2,#4\n\t"
                       "b     Start0\n\t"
                       "Finish0 :"
                       "pop   {r3-r6,pc}\n\t");
}
#endif
#endif
#ifdef ARCH_RISCV
void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  uint32_t wrLen = len - len % 4;
  uint32_t i;

  for (i = 0; i < wrLen; i++) {
    dest[i] = *src;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PKA Write block data to register
                                                                                *
                                                                                * @param  dest: Pointer to register address
                                                                                * @param  src: Pointer to buffer address
                                                                                * @param  len: Data len in word
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifdef ARCH_ARM
#ifndef __GNUC__
__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  PUSH{R3 - R6, LR} Start1 CMP R2, #4 BLT Finish1 LDMIA R1 !, {R3 - R6} STR R3, [R0] STR R4, [R0] STR R5, [R0] STR R6, [R0] SUBS R2, R2, #4 B Start1 Finish1 POP { R3 - R6, PC }
}
#else
void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  __asm__ __volatile__("push {r3-r6,lr}\n\t"
                       "Start1 :"
                       "cmp   r2,#4\n\t"
                       "blt   Finish1\n\t"
                       "ldmia r1!,{r3-r6}\n\t"
                       "str   r3,[r0]\n\t"
                       "str   r4,[r0]\n\t"
                       "str   r5,[r0]\n\t"
                       "str   r6,[r0]\n\t"
                       "sub   r2,r2,#4\n\t"
                       "b     Start1\n\t"
                       "Finish1 :"
                       "pop   {r3-r6,pc}\n\t");
}
#endif
#endif
#ifdef ARCH_RISCV
void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) {
  uint32_t wrLen = len - len % 4;
  uint32_t i;

  for (i = 0; i < wrLen; i++) {
    *dest = src[i];
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  PKA get result
                                                                                *
                                                                                * @param  result: Pointer to store result
                                                                                * @param  retSize: Result length in word
                                                                                * @param  regLen: register length in byte
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen) {
  uint32_t ret_data = 0x00;
  int      index    = 0x00;

  /* Wait for the result */
  Sec_Eng_PKA_Wait_ISR();
  Sec_Eng_PKA_Clear_Int();
  Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize);
  index = retSize - (retSize % 4);

  while (index < retSize) {
    ret_data      = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW);
    result[index] = ret_data;
    index++;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA load data to register
                                                                                *
                                                                                * @param  regType: Register type
                                                                                * @param  regIndex: Register index
                                                                                * @param  data: Data buffer
                                                                                * @param  size: Data length in word
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp) {
  int      index  = 0x00;
  uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType);

  Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp);

  if (size > regLen / 4) {
    size = regLen / 4;
  }

  Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size);
  index = size - (size % 4);

  while (index < size) {
    BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]);
    index++;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA read data from register
                                                                                *
                                                                                * @param  regType: Register type
                                                                                * @param  regIdx: Register index
                                                                                * @param  result: Data buffer
                                                                                * @param  retSize: Data length in word
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) {
  uint16_t regSize;
  uint32_t dummyData = 0;

  regSize = Sec_Eng_PKA_Get_Reg_Size(regType);

  if (retSize > regSize / 4) {
    result = NULL;
    return;
  }

  Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1);

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  Sec_Eng_PKA_Get_Result(result, retSize, regSize);
}

/****************************************************************************/ /**
                                                                                * @brief  PKA clear register
                                                                                *
                                                                                * @param  dRegType: Register type
                                                                                * @param  dRegIdx: Register index
                                                                                * @param  size: Data length in word
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp) {
  uint32_t dummyData = 0;

  Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA load data to register
                                                                                *
                                                                                * @param  regType: regType: Register type
                                                                                * @param  regIndex: regIndex: Register index
                                                                                * @param  data: data: Data buffer
                                                                                * @param  lastOp: size: Data length in word
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp) {
  struct pka0_pldi_cfg cfg;

  cfg.value.BF.rsvd        = 0;
  cfg.value.BF.d_reg_index = regIndex;
  cfg.value.BF.d_reg_type  = regType;
  cfg.value.BF.op          = SEC_ENG_PKA_OP_SLIR;
  cfg.value.BF.last_op     = lastOp;

  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA negative source data:D = (1 << SIZE{S0})-S0
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source Register type
                                                                                * @param  s0RegIdx: Source Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) {
  uint32_t dummyData = 0;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA move data:D = S0
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source Register type
                                                                                * @param  s0RegIdx: Source Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) {
  uint32_t dummyData = 0;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA resize data:D = S0, D.Size = S0.Size
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source Register type
                                                                                * @param  s0RegIdx: Source Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) {
  uint32_t dummyData = 0;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod add:D = (S0 + S1) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod sub:D = (S0 - S1) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod :D = S0 mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod mul:D = (S0 * S1) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod sqr:D = (S0 ^ 2) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod exp:D = (S0 ^ S1) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod exp:D = (S0 ^ (S2-2) ) mod S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA Report COUT to 1 when S0 < S1
                                                                                *
                                                                                * @param  cout: Compare result
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) {
  uint32_t pka0_ctrl = 0x00;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);

  Sec_Eng_PKA_Wait_ISR();
  Sec_Eng_PKA_Clear_Int();
  pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0);

  *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET;
}

/****************************************************************************/ /**
                                                                                * @brief  PKA add:D = S0 + S1
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA sub:D = S0 - S1
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mul:D = S0 * S1
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s1RegType: Source 1 Register type
                                                                                * @param  s1RegIdx: Source 1 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA sqr:D = S0^2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) {
  uint32_t dummyData = 0;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp);
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA div:D = S0 / S2
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  s2RegType: Source 2 Register type
                                                                                * @param  s2RegIdx: Source 2 Register index
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) {
  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp);
  Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA shift:D = S0 << BIT SHIFT
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  bit_shift: Bits to shift
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp) {
  struct pka0_bit_shift_op_cfg cfg;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0);

  cfg.value.BF.bit_shift = bit_shift;
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA shift:D = S0 >> BIT SHIFT
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  bit_shift: Bits to shift
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp) {
  struct pka0_bit_shift_op_cfg cfg;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0);

  cfg.value.BF.bit_shift = bit_shift;
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1)
                                                                                *
                                                                                * @param  dRegType: Destination Register type
                                                                                * @param  dRegIdx: Destination Register index
                                                                                * @param  s0RegType: Source 0 Register type
                                                                                * @param  s0RegIdx: Source 0 Register index
                                                                                * @param  bit_shift: Bits to shift
                                                                                * @param  lastOp: Last operation
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint16_t bit_shift, uint8_t lastOp) {
  struct pka0_bit_shift_op_cfg cfg;

  Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp);

  cfg.value.BF.bit_shift = bit_shift;
  BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD);

  if (lastOp) {
    Sec_Eng_PKA_Wait_ISR();
    Sec_Eng_PKA_Clear_Int();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  PKA GF to Mont  filed 2N:d = (a<
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sf_cfg.h"
#include "bl702_glb.h"
#include "bl702_xip_sflash.h"
#include "softcrc.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CFG
 *  @{
 */

/** @defgroup  SF_CFG_Private_Macros
 *  @{
 */
#define BFLB_FLASH_CFG_MAGIC "FCFG"

/*@} end of group SF_CFG_Private_Macros */

/** @defgroup  SF_CFG_Private_Types
 *  @{
 */
#ifndef BFLB_USE_ROM_DRIVER
typedef struct {
  uint32_t                  jedecID;
  char                     *name;
  const SPI_Flash_Cfg_Type *cfg;
} Flash_Info_t;
#endif

/*@} end of group SF_CFG_Private_Types */

/** @defgroup  SF_CFG_Private_Variables
 *  @{
 */
#ifndef BFLB_USE_ROM_DRIVER
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xef,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 0,
    .cReadMode      = 0xFF,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3d,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 3,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16DV = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xef,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3d,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 3,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16FW_32JW_32FW_32FV = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xef,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 400,
    .timeE32k    = 1600,
    .timeE64k    = 2000,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 3,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x9d,

    .deBurstWrapCmd       = 0xC0,
    .deBurstWrapCmdDmyClk = 0x00,
    .deBurstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .deBurstWrapData      = 0x00,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0,
    .qeBit         = 0x06,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0xC0,
    .burstWrapCmdDmyClk = 0x00,
    .burstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .burstWrapData      = 0x06,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 5,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x51,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 0,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_DO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc8,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc8,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc8,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 32 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 8 / 8,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0x12,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc8,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xC2,

    .deBurstWrapCmd       = 0xC0,
    .deBurstWrapCmdDmyClk = 0x00,
    .deBurstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .deBurstWrapData      = 0x10,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0,
    .qeBit         = 0x06,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA5,

    .burstWrapCmd       = 0xC0,
    .burstWrapCmdDmyClk = 0x00,
    .burstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .burstWrapData      = 0x02,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x38,
    .qppAddrMode     = SF_CTRL_ADDR_4_LINES,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 45,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xC2,

    .deBurstWrapCmd       = 0xC0,
    .deBurstWrapCmdDmyClk = 0x00,
    .deBurstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .deBurstWrapData      = 0x10,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0,
    .qeBit         = 0x06,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA5,

    .burstWrapCmd       = 0xC0,
    .burstWrapCmdDmyClk = 0x00,
    .burstWrapDataMode  = SF_CTRL_DATA_1_LINE,
    .burstWrapData      = 0x02,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x38,
    .qppAddrMode     = SF_CTRL_ADDR_4_LINES,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 45,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx40 = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x0B,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0x01,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_DIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,
    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 6000,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x0B,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0x01,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,
    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 6000,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x85,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0x01,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3d,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,
    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 8,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x85,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0x01,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,
    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 8,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya40 = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x68,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 0,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_DO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x68,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 0x01,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,
    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xef,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 8,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {
    {
     .jedecID = 0x1440ef,
     .name    = "Winb_80DV_08_33",
     .cfg     = &flashCfg_Winb_80DV,
     },
    {
     .jedecID = 0x1540ef,
     .name    = "Winb_16DV_16_33",
     .cfg     = &flashCfg_Winb_16DV,
     },
    {
     .jedecID = 0x1640ef,
     .name    = "Winb_32FV_32_33",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x1460ef,
     .name    = "Winb_80EW_08_18",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x1560ef,
     .name    = "Winb_16FW_16_18",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x1660ef,
     .name    = "Winb_32FW_32_18",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x1860ef,
     .name    = "Winb_128FW_128_18",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x1680ef,
     .name    = "Winb_32JW_32_18",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x13605e,
     .name    = "Zbit_04_33",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x14605e,
     .name    = "Zbit_08_33",
     .cfg     = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV,
     },
    {
     .jedecID = 0x14609d,
     .name    = "ISSI_08_33",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x15609d,
     .name    = "ISSI_16_33",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x16609d,
     .name    = "ISSI_32_33",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x14709d,
     .name    = "ISSI_08_18",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x15709d,
     .name    = "ISSI_16_18",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x16709d,
     .name    = "ISSI_32_18",
     .cfg     = &flashCfg_Issi,
     },
    {
     .jedecID = 0x134051,
     .name    = "GD_MD04D_04_33",
     .cfg     = &flashCfg_Gd_Md_40D,
     },
    {
     .jedecID = 0x1440C8,
     .name    = "GD_Q08E_08_33",
     .cfg     = &flashCfg_Gd_Q80E_Q16E,
     },
    {
     .jedecID = 0x1540C8,
     .name    = "GD_Q16E_16_33",
     .cfg     = &flashCfg_Gd_Q80E_Q16E,
     },
    {
     .jedecID = 0x1640C8,
     .name    = "GD_Q32C_32_33",
     .cfg     = &flashCfg_Gd_Q32C,
     },
    {
     .jedecID = 0x1460C8,
     .name    = "GD_LQ08C_08_18",
     .cfg     = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
     },
    {
     .jedecID = 0x1560C8,
     .name    = "GD_LE16C_16_18",
     .cfg     = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
     },
    {
     .jedecID = 0x1660C8,
     .name    = "GD_LQ32D_32_18",
     .cfg     = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
     },
    {
     .jedecID = 0x1465C8,
     .name    = "GD_WQ80E_80_33",
     .cfg     = &flashCfg_Gd_WQ80E_WQ16E,
     },
    {
     .jedecID = 0x1565C8,
     .name    = "GD_WQ16E_16_33",
     .cfg     = &flashCfg_Gd_WQ80E_WQ16E,
     },
    {
     .jedecID = 0x1665C8,
     .name    = "GD_WQ32E_32_33",
     .cfg     = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E,
     },
    {
     .jedecID = 0x3425C2,
     .name    = "MX_25V80_08_18",
     .cfg     = &flashCfg_Mxic,
     },
    {
     .jedecID = 0x3525C2,
     .name    = "MX_25U16_35_18",
     .cfg     = &flashCfg_Mxic_1635F,
     },
    {
     .jedecID = 0x3625C2,
     .name    = "MX_25V32_32_18",
     .cfg     = &flashCfg_Mxic,
     },
    {
     .jedecID = 0x13400B,
     .name    = "XT_25F04D_04_33",
     .cfg     = &flashCfg_Xtx40,
     },
    {
     .jedecID = 0x15400B,
     .name    = "XT_25F16B_16_33",
     .cfg     = &flashCfg_Xtx,
     },
    {
     .jedecID = 0x16400B,
     .name    = "XT_25F32B_32_33",
     .cfg     = &flashCfg_Xtx,
     },
    {
     .jedecID = 0x14600B,
     .name    = "XT_25Q80B_08_18",
     .cfg     = &flashCfg_Xtx,
     },
    {
     .jedecID = 0x16600B,
     .name    = "XT_25Q32B_32_18",
     .cfg     = &flashCfg_Xtx,
     },
    {
     .jedecID = 0x146085,
     .name    = "Puya_Q80L/H_08_18/33",
     .cfg     = &flashCfg_Puya_Q80L_Q80H_Q16H,
     },
    {
     .jedecID = 0x156085,
     .name    = "Puya_Q16H_16_33",
     .cfg     = &flashCfg_Puya_Q80L_Q80H_Q16H,
     },
    {
     .jedecID = 0x166085,
     .name    = "Puya_Q32H_32_33",
     .cfg     = &flashCfg_Puya_Q32H,
     },
    {
     .jedecID = 0x134068,
     .name    = "Boya_Q04B_04_33",
     .cfg     = &flashCfg_Boya40,
     },
    {
     .jedecID = 0x144068,
     .name    = "Boya_Q08B_08_33",
     .cfg     = &flashCfg_Boya,
     },
    {
     .jedecID = 0x154068,
     .name    = "Boya_Q16B_16_33",
     .cfg     = &flashCfg_Boya,
     },
    {
     .jedecID = 0x164068,
     .name    = "Boya_Q32B_32_33",
     .cfg     = &flashCfg_Boya,
     },
    {
     .jedecID = 0x174068,
     .name    = "Boya_Q64A_64_33",
     .cfg     = &flashCfg_Boya,
     },
    {
     .jedecID = 0x184068,
     .name    = "Boya_Q128A_128_33",
     .cfg     = &flashCfg_Boya,
     },
    {
     .jedecID = 0x14605E,
     .name    = "FT_VQ80",
     .cfg     = &flashCfg_FT_VQ80,
     }
};
#endif

/*@} end of group SF_CFG_Private_Variables */

/** @defgroup  SF_CFG_Global_Variables
 *  @{
 */

/*@} end of group SF_CFG_Global_Variables */

/** @defgroup  SF_CFG_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SF_CFG_Private_Fun_Declaration */

/** @defgroup  SF_CFG_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Init external flash GPIO according to flash GPIO config
                                                                                *
                                                                                * @param  extFlashPin: Flash GPIO config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
/* static */ void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) {
  GLB_GPIO_Cfg_Type cfg;
  uint8_t           gpiopins[6];
  uint8_t           i = 0;

  cfg.gpioMode = GPIO_MODE_AF;
  cfg.pullType = GPIO_PULL_UP;
  cfg.drive    = 1;
  cfg.smtCtrl  = 1;
  cfg.gpioFun  = GPIO_FUN_FLASH_PSRAM;

  if (extFlashPin == 0) {
    gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;
  } else if (extFlashPin == 1) {
    gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO;
  } else {
    gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO;
  }

  for (i = 0; i < sizeof(gpiopins); i++) {
    cfg.gpioPin = gpiopins[i];

    if (i == 0 || i == 1) {
      /*flash clk and cs is output*/
      cfg.gpioMode = GPIO_MODE_OUTPUT;
    } else {
      /*data are bidir*/
      cfg.gpioMode = GPIO_MODE_AF;
    }

    GLB_GPIO_Init(&cfg);
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Deinit external flash GPIO according to flash GPIO config
                                                                                *
                                                                                * @param  extFlashPin: Flash GPIO config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
/* static */ void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) {
  GLB_GPIO_Cfg_Type cfg;
  uint8_t           gpiopins[6];
  uint8_t           i = 0;

  cfg.gpioMode = GPIO_MODE_INPUT;
  cfg.pullType = GPIO_PULL_UP;
  cfg.drive    = 1;
  cfg.smtCtrl  = 1;
  cfg.gpioFun  = GPIO_FUN_GPIO;

  if (extFlashPin == 0) {
    gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO;

  } else if (extFlashPin == 1) {
    gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO;
  } else {
    gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO;
    gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO;
    gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO;
    gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO;
    gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO;
    gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO;
  }

  for (i = 0; i < sizeof(gpiopins); i++) {
    cfg.gpioPin = gpiopins[i];
    GLB_GPIO_Init(&cfg);
  }
}
#endif

/*@} end of group SF_CFG_Private_Functions */

/** @defgroup  SF_CFG_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Get flash config according to flash ID
                                                                                *
                                                                                * @param  flashID: Flash ID
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) {
  uint32_t i;
  uint8_t  buf[sizeof(SPI_Flash_Cfg_Type) + 8];
  uint32_t crc, *pCrc;
  uint32_t xipOffset;

  if (flashID == 0) {
    xipOffset = SF_Ctrl_Get_Flash_Image_Offset();
    SF_Ctrl_Set_Flash_Image_Offset(0);
    XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);
    SF_Ctrl_Set_Flash_Image_Offset(xipOffset);

    if (BL702_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) {
      crc  = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
      pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));

      if (*pCrc == crc) {
        BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
        return SUCCESS;
      }
    }
  } else {
    for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
      if (flashInfos[i].jedecID == flashID) {
        BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
        return SUCCESS;
      }
    }
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Init flash GPIO according to flash Pin config
                                                                                *
                                                                                * @param  flashPinCfg: Specify flash Pin config
                                                                                * @param  restoreDefault: Wether to restore default setting
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
__WEAK
void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) {
  uint8_t  flashCfg;
  uint8_t  swapCfg;
  uint32_t tmpVal;

  flashCfg = (flashPinCfg >> 2) & 0x03;
  swapCfg  = flashPinCfg & 0x03;

  if (restoreDefault) {
    /* Set Default first */
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);

    if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) {
      SF_Cfg_Init_Ext_Flash_Gpio(1);
    }

    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

    SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2);

    /* Default is set, so return */
    if (flashCfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swapCfg == BFLB_SF2_SWAP_NONE) {
      return;
    }
  }

  if (flashCfg == BFLB_FLASH_CFG_SF1_EXT_17_22) {
    SF_Cfg_Init_Ext_Flash_Gpio(0);
    SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF1);
  } else {
    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);

    if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) {
      SF_Cfg_Init_Ext_Flash_Gpio(1);
    }

    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);

    if (swapCfg == BFLB_SF2_SWAP_NONE) {
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
    } else if (swapCfg == BFLB_SF2_SWAP_CS_IO2) {
      tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
    } else if (swapCfg == BFLB_SF2_SWAP_IO0_IO3) {
      tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
      tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
    } else {
      tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
      tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
    }

    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);

    SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Identify one flash
                                                                                *
                                                                                * @param  callFromFlash: code run at flash or ram
                                                                                * @param  autoScan: Auto scan all GPIO pin
                                                                                * @param  flashPinCfg: Specify flash GPIO config, not auto scan
                                                                                * @param  restoreDefault: Wether restore default flash GPIO config
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                *
                                                                                * @return Flash ID
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) {
  uint32_t    jdecId = 0;
  uint32_t    i      = 0;
  uint32_t    offset;
  BL_Err_Type stat;

  BL702_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type));

  if (callFromFlash == 1) {
    stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

    if (stat != SUCCESS) {
      SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
      return 0;
    }
  }

  if (autoScan) {
    flashPinCfg = 0;

    do {
      if (flashPinCfg > 0x0f) {
        jdecId = 0;
        break;
      }

      SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
      SFlash_Releae_Powerdown(pFlashCfg);
      SFlash_Reset_Continue_Read(pFlashCfg);
      SFlash_DisableBurstWrap(pFlashCfg);
      jdecId = 0;
      SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
      SFlash_DisableBurstWrap(pFlashCfg);
      jdecId = jdecId & 0xffffff;
      flashPinCfg++;
    } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00);
  } else {
    /* select media gpio */
    SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
    SFlash_Releae_Powerdown(pFlashCfg);
    SFlash_Reset_Continue_Read(pFlashCfg);
    SFlash_DisableBurstWrap(pFlashCfg);
    SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
    SFlash_DisableBurstWrap(pFlashCfg);
    jdecId = jdecId & 0xffffff;
  }

  for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
    if (flashInfos[i].jedecID == jdecId) {
      BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
      break;
    }
  }

  if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) {
    if (callFromFlash == 1) {
      XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset);
    }

    return jdecId;
  } else {
    if (callFromFlash == 1) {
      XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset);
    }

    return (jdecId | BFLB_FLASH_ID_VALID_FLAG);
  }
}
#endif

/*@} end of group SF_CFG_Public_Functions */

/*@} end of group SF_CFG */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_cfg_ext.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sf_cfg_ext.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sf_cfg_ext.h"
#include "bl702_glb.h"
#include "bl702_romdriver.h"
#include "bl702_sf_cfg.h"
#include "bl702_xip_sflash.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CFG_EXT
 *  @{
 */

/** @defgroup  SF_CFG_EXT_Private_Macros
 *  @{
 */
#define BFLB_FLASH_CFG_MAGIC "FCFG"

/*@} end of group SF_CFG_EXT_Private_Macros */

/** @defgroup  SF_CFG_EXT_Private_Types
 *  @{
 */
typedef struct {
  uint32_t                  jedecID;
  char                     *name;
  const SPI_Flash_Cfg_Type *cfg;
} Flash_Info_t;

/*@} end of group SF_CFG_EXT_Private_Types */

/** @defgroup  SF_CFG_EXT_Private_Variables
 *  @{
 */

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0x51,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 0,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = 0x11,
    .clkDelay  = 1,
    .clkInvert = 0x3f,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 20 * 1000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25 = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc2,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x00,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x00,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 0,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = 0x11,
    .clkDelay  = 1,
    .clkInvert = 0x01,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 33000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_Q80 = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xc8,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x02,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x01,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0xA0,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x01,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 300,
    .timeE32k    = 1200,
    .timeE64k    = 1200,
    .timePagePgm = 5,
    .timeCe      = 33000,
    .pdDelay     = 20,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = {
    .resetCreadCmd     = 0xff,
    .resetCreadCmdSize = 3,
    .mid               = 0xef,

    .deBurstWrapCmd       = 0x77,
    .deBurstWrapCmdDmyClk = 0x3,
    .deBurstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .deBurstWrapData      = 0xF0,

    /*reg*/
    .writeEnableCmd     = 0x06,
    .wrEnableIndex      = 0x00,
    .wrEnableBit        = 0x01,
    .wrEnableReadRegLen = 0x01,

    .qeIndex       = 1,
    .qeBit         = 0x01,
    .qeWriteRegLen = 0x01,
    .qeReadRegLen  = 0x1,

    .busyIndex        = 0,
    .busyBit          = 0x00,
    .busyReadRegLen   = 0x1,
    .releasePowerDown = 0xab,

    .readRegCmd[0]  = 0x05,
    .readRegCmd[1]  = 0x35,
    .writeRegCmd[0] = 0x01,
    .writeRegCmd[1] = 0x31,

    .fastReadQioCmd = 0xeb,
    .frQioDmyClk    = 16 / 8,
    .cReadSupport   = 1,
    .cReadMode      = 0x20,

    .burstWrapCmd       = 0x77,
    .burstWrapCmdDmyClk = 0x3,
    .burstWrapDataMode  = SF_CTRL_DATA_4_LINES,
    .burstWrapData      = 0x40,
    /*erase*/
    .chipEraseCmd   = 0xc7,
    .sectorEraseCmd = 0x20,
    .blk32EraseCmd  = 0x52,
    .blk64EraseCmd  = 0xd8,
    /*write*/
    .pageProgramCmd  = 0x02,
    .qpageProgramCmd = 0x32,
    .qppAddrMode     = SF_CTRL_ADDR_1_LINE,

    .ioMode    = SF_CTRL_QIO_MODE,
    .clkDelay  = 1,
    .clkInvert = 0x01,

    .resetEnCmd          = 0x66,
    .resetCmd            = 0x99,
    .cRExit              = 0xff,
    .wrEnableWriteRegLen = 0x00,

    /*id*/
    .jedecIdCmd          = 0x9f,
    .jedecIdCmdDmyClk    = 0,
    .qpiJedecIdCmd       = 0x9f,
    .qpiJedecIdCmdDmyClk = 0x00,
    .sectorSize          = 4,
    .pageSize            = 256,

    /*read*/
    .fastReadCmd    = 0x0b,
    .frDmyClk       = 8 / 8,
    .qpiFastReadCmd = 0x0b,
    .qpiFrDmyClk    = 8 / 8,
    .fastReadDoCmd  = 0x3b,
    .frDoDmyClk     = 8 / 8,
    .fastReadDioCmd = 0xbb,
    .frDioDmyClk    = 0,
    .fastReadQoCmd  = 0x6b,
    .frQoDmyClk     = 8 / 8,

    .qpiFastReadQioCmd  = 0xeb,
    .qpiFrQioDmyClk     = 16 / 8,
    .qpiPageProgramCmd  = 0x02,
    .writeVregEnableCmd = 0x50,

    /* qpi mode */
    .enterQpi = 0x38,
    .exitQpi  = 0xff,

    /*AC*/
    .timeEsector = 400,
    .timeE32k    = 1600,
    .timeE64k    = 2000,
    .timePagePgm = 5,
    .timeCe      = 33000,
    .pdDelay     = 3,
    .qeData      = 0,
};

static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {
    {
     .jedecID = 0x134051,
     .name    = "GD_MD04D_04_33",
     .cfg     = &flashCfg_Gd_Md_40D,
     },
    {
     .jedecID = 0x1320c2,
     .name    = "MX_KH40_04_33",
     .cfg     = &flashCfg_MX_KH25,
     },
    {
     .jedecID = 0x1420c2,
     .name    = "MX_KH80_08_33",
     .cfg     = &flashCfg_MX_KH25,
     },
    {
     .jedecID = 0x1520c2,
     .name    = "MX_KH16_16_33",
     .cfg     = &flashCfg_MX_KH25,
     },
    {
     .jedecID = 0x1440A1,
     .name    = "FM_25Q80_80_33",
     .cfg     = &flashCfg_FM_Q80,
     },
    {
     .jedecID = 0x1570EF,
     .name    = "Winb_16JV_16_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x1870EF,
     .name    = "Winb_128JV_128_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x15605E,
     .name    = "ZB_VQ16_16_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x144020,
     .name    = "XM_25QH80_80_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x154020,
     .name    = "XM_25QH16_16_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x164020,
     .name    = "XM_25QH32_32_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x174020,
     .name    = "XM_25QH64_64_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x13325E,
     .name    = "ZB_D40B_80_33",
     .cfg     = &flashCfg_MX_KH25,
     },
    {
     .jedecID = 0x14325E,
     .name    = "ZB_D80B_80_33",
     .cfg     = &flashCfg_MX_KH25,
     },
    {
     .jedecID = 0x15405E,
     .name    = "ZB_25Q16B_15_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x16405E,
     .name    = "ZB_25Q32B_16_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
    {
     .jedecID = 0x1560EB,
     .name    = "TH_25Q16HB_16_33",
     .cfg     = &flashCfg_FM_Q80,
     },
    {
     .jedecID = 0x15345E,
     .name    = "ZB_25Q16A_15_33",
     .cfg     = &flashCfg_Winb_16JV,
     },
};

/*@} end of group SF_CFG_EXT_Private_Variables */

/** @defgroup  SF_CFG_EXT_Global_Variables
 *  @{
 */

/*@} end of group SF_CFG_EXT_Global_Variables */

/** @defgroup  SF_CFG_EXT_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */

/** @defgroup  SF_CFG_EXT_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Init internal flash GPIO
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) {
  GLB_GPIO_Cfg_Type gpioCfg = {
      .gpioPin  = GLB_GPIO_PIN_0,
      .gpioFun  = GPIO_FUN_GPIO,
      .gpioMode = GPIO_MODE_INPUT,
      .pullType = GPIO_PULL_NONE,
      .drive    = 0,
      .smtCtrl  = 1,
  };

  /* Turn on Flash pad, GPIO23 - GPIO28 */
  for (uint32_t pin = 23; pin < 29; pin++) {
    gpioCfg.gpioPin = pin;

    if (pin == 25) {
      gpioCfg.pullType = GPIO_PULL_DOWN;
    } else {
      gpioCfg.pullType = GPIO_PULL_NONE;
    }

    GLB_GPIO_Init(&gpioCfg);
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get flash config according to flash ID
                                                                                *
                                                                                * @param  flashID: Flash ID
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) {
  uint32_t i;
  uint8_t  buf[sizeof(SPI_Flash_Cfg_Type) + 8];
  uint32_t crc, *pCrc;
  char     flashCfgMagic[] = "FCFG";

  if (flashID == 0) {
    XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);

    if (BL702_MemCmp(buf, flashCfgMagic, 4) == 0) {
      crc  = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
      pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));

      if (*pCrc == crc) {
        BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
        return SUCCESS;
      }
    }
  } else {
    if (SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) {
      /* 0x134051 flash cfg is wrong in rom, find again */
      if ((flashID & 0xFFFFFF) != 0x134051) {
        return SUCCESS;
      }
    }

    for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
      if (flashInfos[i].jedecID == flashID) {
        BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
        return SUCCESS;
      }
    }
  }

  return ERROR;
}

/****************************************************************************/ /**
                                                                                * @brief  Identify one flash
                                                                                *
                                                                                * @param  callFromFlash: code run at flash or ram
                                                                                * @param  autoScan: Auto scan all GPIO pin
                                                                                * @param  flashPinCfg: Specify flash GPIO config, not auto scan
                                                                                * @param  restoreDefault: Wether restore default flash GPIO config
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                *
                                                                                * @return Flash ID
                                                                                *
                                                                                *******************************************************************************/
uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) {
  uint32_t jdecId = 0;
  uint32_t i      = 0;
  uint32_t ret    = 0;

  ret = SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg);

  if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) {
    /* 0x134051 flash cfg is wrong in rom, find again */
    if ((ret & 0xFFFFFF) != 0x134051) {
      return ret;
    }
  }

  jdecId = (ret & 0xffffff);

  for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
    if (flashInfos[i].jedecID == jdecId) {
      BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
      break;
    }
  }

  if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) {
    return jdecId;
  } else {
    return (jdecId | BFLB_FLASH_ID_VALID_FLAG);
  }
}

/*@} end of group SF_CFG_EXT_Public_Functions */

/*@} end of group SF_CFG_EXT */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sf_ctrl.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sf_ctrl.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sf_ctrl.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SF_CTRL
 *  @{
 */

/** @defgroup  SF_CTRL_Private_Macros
 *  @{
 */

/*@} end of group SF_CTRL_Private_Macros */

/** @defgroup  SF_CTRL_Private_Types
 *  @{
 */

/*@} end of group SF_CTRL_Private_Types */

/** @defgroup  SF_CTRL_Private_Variables
 *  @{
 */
#define SF_CTRL_BUSY_STATE_TIMEOUT      (5 * 160 * 1000)
#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r) * 0x100)

/*@} end of group SF_CTRL_Private_Variables */

/** @defgroup  SF_CTRL_Global_Variables
 *  @{
 */

/*@} end of group SF_CTRL_Global_Variables */

/** @defgroup  SF_CTRL_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SF_CTRL_Private_Fun_Declaration */

/** @defgroup  SF_CTRL_Private_Functions
 *  @{
 */

/*@} end of group SF_CTRL_Private_Functions */

/** @defgroup  SF_CTRL_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Enable serail flash controller
                                                                                *
                                                                                * @param  cfg: serial flash controller config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  if (cfg == NULL) {
    return;
  }

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  if (cfg->clkDelay > 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
  }

  /* Serail out inverted, so sf ctrl send on negative edge */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);

  /* Set do di and oe delay */
  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal);

  /* Enable AHB access sram buffer and enable sf interface */
  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);

  SF_Ctrl_Set_Owner(cfg->owner);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable serail psram controller
                                                                                *
                                                                                * @param  sfCtrlPsramCfg: serial psram controller config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
// #ifndef BFLB_USE_ROM_DRIVER
//__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) {
  uint32_t tmpVal = 0;

  SF_Ctrl_Select_Pad(sfCtrlPsramCfg->padSel);
  SF_Ctrl_Select_Bank(sfCtrlPsramCfg->bankSel);

  /* Select psram clock delay */
  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12);

  if (sfCtrlPsramCfg->psramRxClkInvertSrc) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);

    if (sfCtrlPsramCfg->psramRxClkInvertSel) {
      tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);
    } else {
      tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL);
    }
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC);
  }

  if (sfCtrlPsramCfg->psramDelaySrc) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);

    if (sfCtrlPsramCfg->psramClkDelay > 0) {
      tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, sfCtrlPsramCfg->psramClkDelay - 1);
    } else {
      tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN);
    }
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal);

  /* Enable AHB access sram buffer and enable sf interface */
  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);

  SF_Ctrl_Set_Owner(sfCtrlPsramCfg->owner);
}
// #endif

/****************************************************************************/ /**
                                                                                * @brief  Get flash controller clock delay value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Clock delay value
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) {
    return 0;
  } else {
    return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set flash controller clock delay value
                                                                                *
                                                                                * @param  delay: Clock delay value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  if (delay > 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF Ctrl set cmds config
                                                                                *
                                                                                * @param  cmdsCfg: SF Ctrl cmds config
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->wrapLen));

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3);

  if (cmdsCfg->cmdsEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN);
  }

  if (cmdsCfg->burstToggleEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN);
  }

  if (cmdsCfg->wrapModeEn) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE);
  }

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_WRAP_LEN, cmdsCfg->wrapLen);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF Ctrl pad select
                                                                                *
                                                                                * @param  sel: pad select type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) {
  /* TODO: sf_if_bk_swap */
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_PAD_SELECT(sel));

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);

  if (sel <= SF_CTRL_PAD_SEL_SF3) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel);
  } else if (sel >= SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel - SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2);
  } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF2) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 1);
  } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF3) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 2);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF Ctrl bank select
                                                                                *
                                                                                * @param  sel: bank select type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) {
  /* TODO: sf_if_bk_swap */
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_SELECT(sel));

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2);

  if (sel == SF_CTRL_SEL_FLASH) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);
  } else {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set flash controller owner:I/D AHB or system AHB
                                                                                *
                                                                                * @param  owner: owner type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  /* Set owner */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner);

  /* Set iahb to flash interface */
  if (owner == SF_CTRL_OWNER_IAHB) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable flash controller
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable flash controller AES with big indian
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable flash controller AES with little indian
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Serial flash controller set AES region
                                                                                *
                                                                                * @param  region: region number
                                                                                * @param  enable: enable or not
                                                                                * @param  hwKey: hardware key or software key
                                                                                * @param  startAddr: region start address
                                                                                * @param  endAddr: region end address
                                                                                * @param  locked: lock this region or not
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) {
  /* Do flash key eco*/
  uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  uint32_t tmpVal;

  if (!hwKey) {
    regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  }

  tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG);

  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024);
  /* sf_aes_end =1 means 1,11,1111,1111 */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked);

  BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Serial flash controller set AES key
                                                                                *
                                                                                * @param  region: region number
                                                                                * @param  key: key data pointer
                                                                                * @param  keyType: flash controller AES key type:128 bits,192 bits or 256 bits
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) {
  /* Do flash key eco*/
  uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  uint32_t tmpVal, i = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);

  if (NULL != key) {
    if (keyType == SF_CTRL_AES_128BITS) {
      i = 4;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      */
    } else if (keyType == SF_CTRL_AES_256BITS) {
      i = 8;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      */
    } else if (keyType == SF_CTRL_AES_192BITS) {
      i = 6;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key)));
      key+=4;
      */
    }

    tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET;

    while (i--) {
      BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key)));
      key += 4;
      tmpVal -= 4;
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Serial flash controller set AES key with big endian
                                                                                *
                                                                                * @param  region: region number
                                                                                * @param  key: key data pointer
                                                                                * @param  keyType: flash controller AES key type:128 bits,192 bits or 256 bits
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) {
  /* Do flash key eco*/
  uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  uint32_t tmpVal, i = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType));

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);

  if (NULL != key) {
    if (keyType == SF_CTRL_AES_128BITS) {
      i = 4;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      */
    } else if (keyType == SF_CTRL_AES_256BITS) {
      i = 8;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      */
    } else if (keyType == SF_CTRL_AES_192BITS) {
      i = 6;
      /*
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key));
      key+=4;
      BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key));
      */
    }

    tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET;

    while (i--) {
      BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key));
      key += 4;
      tmpVal += 4;
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Serial flash controller set AES iv
                                                                                *
                                                                                * @param  region: region number
                                                                                * @param  iv: iv data pointer
                                                                                * @param  addrOffset: flash address offset
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) {
  /* Do flash key eco*/
  uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  uint32_t tmpVal, i = 3;

  if (iv != NULL) {
    tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET;

    while (i--) {
      BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv)));
      iv += 4;
      tmpVal -= 4;
    }

    /*
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv)));
    iv+=4;
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv)));
    iv+=4;
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv)));
    iv+=4;
    */
    BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset);
    iv += 4;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Serial flash controller set AES iv with big endian
                                                                                *
                                                                                * @param  region: region number
                                                                                * @param  iv: iv data pointer
                                                                                * @param  addrOffset: flash address offset
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) {
  /* Do flash key eco*/
  uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region);
  uint32_t tmpVal, i = 3;

  if (iv != NULL) {
    tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET;

    while (i--) {
      BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv));
      iv += 4;
      tmpVal += 4;
    }

    /*
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv));
    iv+=4;
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv));
    iv+=4;
    BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv));
    iv+=4;
    */
    BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset));
    iv += 4;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable serial flash controller AES
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable serial flash controller AES
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Check is serial flash controller AES enable
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Wether AES is enable
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES);
  return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set flash image offset
                                                                                *
                                                                                * @param  addrOffset: Address offset value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) { BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get flash image offset
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return :Address offset value
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) { return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF controller send one command
                                                                                *
                                                                                * @param  sahbType: Serial flash controller clock sahb sram select
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);

  if (sahbType == SF_CTRL_SAHB_CLOCK) {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL);
  } else if (sahbType == SF_CTRL_FLASH_CLOCK) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL);
  }

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF controller send one command
                                                                                *
                                                                                * @param  cfg: Serial flash controller command configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
  CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
  CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
  CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) {
    return;
  }

  /* Clear trigger */
  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);

  /* Copy command buffer */
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]);

  /* Configure SPI and IO mode*/
  if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE);
  }

  if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
    if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE);
    } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE);
    } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE);
    }
  } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE);
  } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE);
  }

  /* Configure cmd */
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0);

  /* Configure address */
  if (cfg->addrSize != 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0);
  }

  /* Configure dummy */
  if (cfg->dummyClks != 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0);
  }

  /* Configure data */
  if (cfg->nbData != 0) {
    tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0);
  }

  /* Set read write flag */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);

  // switch sf_clk_sahb_sram_sel = 1
  SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK);
  /* Trigger */
  tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal);

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK);
      return;
    }
  }

  // switch sf_clk_sahb_sram_sel = 0
  SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Config SF controller for flash I/D cache read
                                                                                *
                                                                                * @param  cfg: Serial flash controller command configuration pointer
                                                                                * @param  cmdValid: command valid or not, for continous read, cache may need no command
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
  CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
  CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
  CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
    return;
  }

  /* Copy command buffer */
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0);

  /* Configure SPI and IO mode*/
  if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);
  }

  if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
    if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);
    } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);
    } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);
    }
  } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);
  } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);
  }

  if (cmdValid) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
  }

  /* Configure address */
  if (cfg->addrSize != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);
  }

  /* configure dummy */
  if (cfg->dummyClks != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);
  }

  /* Configure data */
  if (cfg->nbData != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);
  }

  /* Set read write flag */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Config psram controller for psram I/D cache write
                                                                                *
                                                                                * @param  cfg: Serial flash controller command configuration pointer
                                                                                * @param  cmdValid: command valid or not, cache may need no command
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
  CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
  CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
  CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
    return;
  }

  /* Copy command buffer */
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3);

  /* Configure SPI and IO mode*/
  if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE);
  }

  if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
    if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE);
    } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE);
    } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE);
    }
  } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE);
  } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE);
  }

  if (cmdValid) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0);
  }

  /* Configure address */
  if (cfg->addrSize != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0);
  }

  /* configure dummy */
  if (cfg->dummyClks != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0);
  }

  /* Configure data */
  if (cfg->nbData != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0);
  }

  /* Set read write flag */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Config psram controller for psram I/D cache read
                                                                                *
                                                                                * @param  cfg: Serial flash controller command configuration pointer
                                                                                * @param  cmdValid: command valid or not, for continous read, cache may need no command
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) {
  uint32_t tmpVal  = 0;
  uint32_t timeOut = 0;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode));
  CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode));
  CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode));
  CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode));

  timeOut = SF_CTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1);

  if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) {
    return;
  }

  /* Copy command buffer */
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]);
  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]);

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9);

  /* Configure SPI and IO mode*/
  if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE);
  }

  if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) {
    if (SF_CTRL_DATA_1_LINE == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE);
    } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE);
    } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) {
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE);
    }
  } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE);
  } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE);
  }

  if (cmdValid) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0);
  }

  /* Configure address */
  if (cfg->addrSize != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0);
  }

  /* configure dummy */
  if (cfg->dummyClks != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0);
  }

  /* Configure data */
  if (cfg->nbData != 0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0);
  }

  /* Set read write flag */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag);

  BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get SF Ctrl busy state
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SET  for SF ctrl busy or RESET for SF ctrl not busy
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) {
  uint32_t tmpVal;

  tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0);

  if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) {
    return SET;
  } else {
    return RESET;
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  SF Controller interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void) { /* TODO: Not implemented */ }
#endif

/*@} end of group SF_CTRL_Public_Functions */

/*@} end of group SF_CTRL */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sflash.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sflash.h"
#include "bl702_l1c.h"
#include "bl702_sf_ctrl.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SFLASH
 *  @{
 */

/** @defgroup  SFLASH_Private_Macros
 *  @{
 */

/*@} end of group SFLASH_Private_Macros */

/** @defgroup  SFLASH_Private_Types
 *  @{
 */

/*@} end of group SFLASH_Private_Types */

/** @defgroup  SFLASH_Private_Variables
 *  @{
 */
#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)

/*@} end of group SFLASH_Private_Variables */

/** @defgroup  SFLASH_Global_Variables
 *  @{
 */

/*@} end of group SFLASH_Global_Variables */

/** @defgroup  SFLASH_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SFLASH_Private_Fun_Declaration */

/** @defgroup  SFLASH_Private_Functions
 *  @{
 */

/*@} end of group SFLASH_Private_Functions */

/** @defgroup  SFLASH_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Init serial flash control interface
                                                                                *
                                                                                * @param  pSfCtrlCfg: Serial flash controller configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) { SF_Ctrl_Enable(pSfCtrlCfg); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set serial flash control interface SPI or QPI mode
                                                                                *
                                                                                * @param  mode: Serial flash interface mode
                                                                                *
                                                                                * @return BFLB_RET:SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) {
  BL_Err_Type stat = SUCCESS;

  /* Check the parameters */
  CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode));

  return stat;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read flash register
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  regIndex: register index
                                                                                * @param  regValue: register value pointer to store data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             cnt = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24;
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
    BL702_Delay_US(1);
    cnt++;

    if (cnt > 1000) {
      return ERROR;
    }
  }

  BL702_MemCpy(regValue, flashCtrlBuf, regLen);
  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Write flash register
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  regIndex: register index
                                                                                * @param  regValue: register value pointer storing data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             cnt          = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  BL702_MemCpy(flashCtrlBuf, regValue, regLen);

  flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24;
  flashCmd.rwFlag    = SF_CTRL_WRITE;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  /* take 40ms for tw(write status register) as default */
  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(100);
    cnt++;

    if (cnt > 400) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read flash register with read command
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  readRegCmd: read command
                                                                                * @param  regValue: register value pointer to store data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             cnt = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = readRegCmd << 24;
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
    BL702_Delay_US(1);
    cnt++;

    if (cnt > 1000) {
      return ERROR;
    }
  }

  BL702_MemCpy(regValue, flashCtrlBuf, regLen);
  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Write flash register with write command
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  writeRegCmd: write command
                                                                                * @param  regValue: register value pointer storing data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             cnt          = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  BL702_MemCpy(flashCtrlBuf, regValue, regLen);

  flashCmd.cmdBuf[0] = writeRegCmd << 24;
  flashCmd.rwFlag    = SF_CTRL_WRITE;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  /* take 40ms for tw(write status register) as default */
  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(100);
    cnt++;

    if (cnt > 400) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Check flash busy status
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return SET for busy or RESET for not busy
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) {
  uint32_t stat = 0;
  SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen);

  if ((stat & (1 << flashCfg->busyBit)) == 0) {
    return RESET;
  }

  return SET;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable flash write function
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) {
  uint32_t             stat = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  /* Write enable*/
  flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24;
  /* rwFlag don't care */
  flashCmd.rwFlag = SF_CTRL_READ;
  SF_Ctrl_SendCmd(&flashCmd);

  SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen);

  if ((stat & (1 << flashCfg->wrEnableBit)) != 0) {
    return SUCCESS;
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable flash flash controller QSPI interface
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) {
  uint32_t stat = 0, ret;

  if (flashCfg->qeReadRegLen == 0) {
    ret = SFlash_Write_Enable(flashCfg);

    if (SUCCESS != ret) {
      return ERROR;
    }

    SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);
    return SUCCESS;
  }

  SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);

  if (flashCfg->qeData == 0) {
    if ((stat & (1 << flashCfg->qeBit)) != 0) {
      return SUCCESS;
    }
  } else {
    if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {
      return SUCCESS;
    }
  }

  if (flashCfg->qeWriteRegLen != 1) {
    /* This is  read r0,read r1 write r0,r1 case*/
    SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
    SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1);

    if (flashCfg->qeData == 0) {
      stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex));
    } else {
      stat = stat & (~(0xff << (8 * flashCfg->qeIndex)));
      stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex));
    }
  } else {
    if (flashCfg->qeData == 0) {
      stat |= (1 << (flashCfg->qeBit % 8));
    } else {
      stat = flashCfg->qeData;
    }
  }

  ret = SFlash_Write_Enable(flashCfg);

  if (SUCCESS != ret) {
    return ERROR;
  }

  SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen);
  SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen);

  if (flashCfg->qeData == 0) {
    if ((stat & (1 << flashCfg->qeBit)) != 0) {
      return SUCCESS;
    }
  } else {
    if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) {
      return SUCCESS;
    }
  }

  return ERROR;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable flash volatile register write enable
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) {
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24;
  flashCmd.rwFlag    = SF_CTRL_WRITE;

  SF_Ctrl_SendCmd(&flashCmd);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Erase flash whole chip
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) {
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             cnt  = 0;
  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);

  if (stat != SUCCESS) {
    return stat;
  }

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24;
  /* rwFlag don't care */
  flashCmd.rwFlag = SF_CTRL_READ;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(500);
    cnt++;

    if (cnt > flashCfg->timeCe * 3) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Erase flash one sector
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  secNum: flash sector number
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) {
  uint32_t             cnt = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  BL_Err_Type stat = SFlash_Write_Enable(flashCfg);

  if (stat != SUCCESS) {
    return stat;
  }

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum);
  /* rwFlag don't care */
  flashCmd.rwFlag   = SF_CTRL_READ;
  flashCmd.addrSize = 3;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(500);
    cnt++;

    if (cnt > flashCfg->timeEsector * 3) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Erase flash one 32K block
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  blkNum: flash 32K block number
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) {
  uint32_t             cnt = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);

  if (stat != SUCCESS) {
    return stat;
  }

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum);
  /* rwFlag don't care */
  flashCmd.rwFlag   = SF_CTRL_READ;
  flashCmd.addrSize = 3;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(500);
    cnt++;

    if (cnt > flashCfg->timeE32k * 3) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Erase flash one 64K block
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  blkNum: flash 64K block number
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) {
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             cnt  = 0;
  BL_Err_Type          stat = SFlash_Write_Enable(flashCfg);

  if (stat != SUCCESS) {
    return stat;
  }

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum);
  /* rwFlag don't care */
  flashCmd.rwFlag   = SF_CTRL_READ;
  flashCmd.addrSize = 3;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(500);
    cnt++;

    if (cnt > flashCfg->timeE64k * 3) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Erase flash one region
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  startaddr: start address to erase
                                                                                * @param  endaddr: end address(include this address) to erase
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) {
  uint32_t    len      = 0;
  uint32_t    eraseLen = 0;
  BL_Err_Type ret      = SUCCESS;

  while (startaddr <= endaddr) {
    len = endaddr - startaddr + 1;

    if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && len > (uint32_t)(BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) {
      /* 64K margin address,and length > 64K-sector size, erase one first */
      ret      = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE);
      eraseLen = BFLB_SPIFLASH_BLK64K_SIZE;
    } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&
               len > (uint32_t)(BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) {
      /* 32K margin address,and length > 32K-sector size, erase one first */
      ret      = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE);
      eraseLen = BFLB_SPIFLASH_BLK32K_SIZE;
    } else {
      /* Sector erase */
      startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1)));
      ret       = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024);
      eraseLen  = flashCfg->sectorSize * 1024;
    }

    startaddr += eraseLen;

    if (ret != SUCCESS) {
      return ERROR;
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Program flash one region
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  ioMode: progran mode:SPI mode or QPI mode
                                                                                * @param  addr: start address to be programed
                                                                                * @param  data: data pointer to be programed
                                                                                * @param  len: data length to be programed
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             i = 0, curLen = 0;
  uint32_t             cnt = 0;
  BL_Err_Type          stat;
  uint8_t              cmd;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
    cmd = flashCfg->pageProgramCmd;
  } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) {
    flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode;
    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = flashCfg->qpageProgramCmd;
  } else {
    return ERROR;
  }

  /* Prepare command */
  flashCmd.rwFlag   = SF_CTRL_WRITE;
  flashCmd.addrSize = 3;

  for (i = 0; i < len;) {
    /* Write enable is needed for every program */
    stat = SFlash_Write_Enable(flashCfg);

    if (stat != SUCCESS) {
      return stat;
    }

    /* Get current programmed length within page size */
    curLen = flashCfg->pageSize - addr % flashCfg->pageSize;

    if (curLen > len - i) {
      curLen = len - i;
    }

    /* Prepare command */
    BL702_MemCpy_Fast(flashCtrlBuf, data, curLen);
    flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
    flashCmd.nbData    = curLen;

    SF_Ctrl_SendCmd(&flashCmd);

    /* Adjust address and programmed length */
    addr += curLen;
    i += curLen;
    data += curLen;

    /* Wait for write done */
    cnt = 0;

    while (SET == SFlash_Busy(flashCfg)) {
      BL702_Delay_US(100);
      cnt++;

      if (cnt > flashCfg->timePagePgm * 20) {
        return ERROR;
      }
    }
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get flash unique ID
                                                                                *
                                                                                * @param  data: data pointer to store read data
                                                                                * @param  idLen: unique ID len
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint8_t              cmd, dummyClks;
  uint32_t             timeOut = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  dummyClks          = 4;
  cmd                = 0x4B;
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = idLen;

  SF_Ctrl_SendCmd(&flashCmd);

  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  BL702_MemCpy(data, flashCtrlBuf, idLen);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get flash jedec ID
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  data: data pointer to store read data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint8_t              cmd, dummyClks;
  uint32_t             timeOut = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  dummyClks          = flashCfg->jedecIdCmdDmyClk;
  cmd                = flashCfg->jedecIdCmd;
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = 3;

  SF_Ctrl_SendCmd(&flashCmd);

  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  BL702_MemCpy(data, flashCtrlBuf, 3);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get flash device ID
                                                                                *
                                                                                * @param  data: data pointer to store read data
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint8_t              cmd, dummyClks;
  uint32_t             timeOut = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             addr     = 0x00000001;
  uint8_t              readMode = 0xFF;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.addrMode  = SF_CTRL_ADDR_4_LINES;
  flashCmd.dataMode  = SF_CTRL_DATA_4_LINES;
  dummyClks          = 2;
  cmd                = 0x94;
  flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
  flashCmd.cmdBuf[1] = (readMode << 24);
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.addrSize  = 4;
  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = 2;

  SF_Ctrl_SendCmd(&flashCmd);

  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }

  BL702_MemCpy(data, flashCtrlBuf, 2);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set flash power down
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Powerdown(void) {
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint8_t              cmd     = 0;
  uint32_t             timeOut = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  cmd                = 0xB9;
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_WRITE;

  SF_Ctrl_SendCmd(&flashCmd);

  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Release flash power down for wake up
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) {
  uint8_t  cmd;
  uint32_t timeOut = 0;

  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  cmd                = flashCfg->releasePowerDown;
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_WRITE;

  SF_Ctrl_SendCmd(&flashCmd);

  timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

  while (SET == SF_Ctrl_GetBusyState()) {
    timeOut--;

    if (timeOut == 0) {
      return;
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Sflash restore from power down
                                                                                *
                                                                                * @param  pFlashCfg: Flash configuration pointer
                                                                                * @param  flashContRead: Whether enable continuous read
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) {
  BL_Err_Type stat   = SUCCESS;
  uint32_t    jdecId = 0;
  uint8_t     tmp[8];
  uint8_t     ioMode = pFlashCfg->ioMode & 0xf;

  /* Wake flash up from power down */
  SFlash_Releae_Powerdown(pFlashCfg);
  BL702_Delay_US(120);

  SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);

  if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) {
    SFlash_Qspi_Enable(pFlashCfg);
  }

  if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) {
    /* unwrap */
    L1C_Set_Wrap(DISABLE);
  } else {
    /* burst wrap */
    L1C_Set_Wrap(ENABLE);
    /* For command that is setting register instead of send command, we need write enable */
    SFlash_Write_Enable(pFlashCfg);
    SFlash_SetBurstWrap(pFlashCfg);
  }

  if (flashContRead) {
    stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);
  } else {
    stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32);
  }

  return stat;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set flash burst wrap config
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint8_t              cmd, dummyClks;
  uint32_t             wrapData;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((flashCfg->ioMode >> 4) & 0x01) == 1) {
    /* Disable burst wrap ,just return */
    return;
  }

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode;
  flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode;
  dummyClks         = flashCfg->burstWrapCmdDmyClk;
  cmd               = flashCfg->burstWrapCmd;
  wrapData          = flashCfg->burstWrapData;
  BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_WRITE;
  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = 1;

  SF_Ctrl_SendCmd(&flashCmd);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable flash burst wrap config
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint8_t              cmd, dummyClks;
  uint32_t             wrapData;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode;
  flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode;
  dummyClks         = flashCfg->deBurstWrapCmdDmyClk;
  cmd               = flashCfg->deBurstWrapCmd;
  wrapData          = flashCfg->deBurstWrapData;
  BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4);
  flashCmd.cmdBuf[0] = (cmd << 24);
  flashCmd.rwFlag    = SF_CTRL_WRITE;
  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = 1;

  SF_Ctrl_SendCmd(&flashCmd);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Software reset flash
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) {
  uint16_t             cnt = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  /* Reset enable */
  flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24;
  /* rwFlag don't care */
  flashCmd.rwFlag = SF_CTRL_READ;

  /* Wait for write done */
  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(100);
    cnt++;

    if (cnt > 20) {
      return ERROR;
    }
  }

  SF_Ctrl_SendCmd(&flashCmd);

  /* Reset */
  flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24;
  /* rwFlag don't care */
  flashCmd.rwFlag = SF_CTRL_READ;
  SF_Ctrl_SendCmd(&flashCmd);

  BL702_Delay_US(50);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Reset flash continous read mode
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) {
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  /* Reset continous read */
  BL702_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4);
  /* rwFlag don't care */
  flashCmd.rwFlag   = SF_CTRL_READ;
  flashCmd.addrSize = flashCfg->resetCreadCmdSize;
  SF_Ctrl_SendCmd(&flashCmd);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Set I/D bus read flash configuration in flash controller
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  contRead: Wether enable cont read mode
                                                                                * @param  addr: address to read/write
                                                                                * @param  len: data length to read/write
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) {
  uint8_t              cmd, dummyClks;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint8_t              cmdValid      = 1;
  uint8_t              noReadModeCfg = 0;
  uint8_t              cReadSupport  = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB);

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd       = flashCfg->fastReadCmd;
    dummyClks = flashCfg->frDmyClk;
  } else if (SF_CTRL_DO_MODE == ioMode) {
    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
    cmd               = flashCfg->fastReadDoCmd;
    dummyClks         = flashCfg->frDoDmyClk;
  } else if (SF_CTRL_DIO_MODE == ioMode) {
    flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;
    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
    cmd               = flashCfg->fastReadDioCmd;
    dummyClks         = flashCfg->frDioDmyClk;
  } else if (SF_CTRL_QO_MODE == ioMode) {
    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = flashCfg->fastReadQoCmd;
    dummyClks         = flashCfg->frQoDmyClk;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = flashCfg->fastReadQioCmd;
    dummyClks         = flashCfg->frQioDmyClk;
  } else {
    return ERROR;
  }

  /*prepare command**/
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.addrSize  = 3;
  flashCmd.cmdBuf[0] = (cmd << 24) | addr;

  if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
    noReadModeCfg = flashCfg->cReadSupport & 0x02;
    cReadSupport  = flashCfg->cReadSupport & 0x01;

    if (noReadModeCfg == 0) {
      /* Read mode must be set*/
      if (cReadSupport == 0) {
        /* Not support cont read,but we still need set read mode(winbond 80dv)*/
        flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
      } else {
        /* Flash support cont read, setting depend on user parameter */
        if (contRead) {
          flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode;
          cmdValid           = 0;
        } else {
          flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);
        }
      }

      flashCmd.addrSize++;
    }
  }

  flashCmd.dummyClks = dummyClks;
  flashCmd.nbData    = len;
  SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable I/D bus read from flash
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  contRead: Wether enable cont read mode
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) {
  BL_Err_Type stat;

  stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4);

  if (SUCCESS != stat) {
    return stat;
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Enable cache read from flash with cache
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  contRead: Wether enable cont read mode
                                                                                * @param  wayDisable: cache way disable config
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) {
  BL_Err_Type stat;

  /* Cache now only support 32 bytes read */
  stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32);

  if (SUCCESS != stat) {
    return stat;
  }

  return L1C_Cache_Enable_Set(wayDisable);
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Disable read from flash with cache
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) { L1C_Cache_Read_Disable(); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read data from flash
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  contRead: Wether enable cont read mode
                                                                                * @param  addr: flash read start address
                                                                                * @param  data: data pointer to store data read from flash
                                                                                * @param  len: data length to read
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             curLen, i;
  uint8_t              cmd, dummyClks;
  uint32_t             timeOut = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint8_t              noReadModeCfg = 0;
  uint8_t              cReadSupport  = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  if (SF_CTRL_NIO_MODE == ioMode) {
    cmd       = flashCfg->fastReadCmd;
    dummyClks = flashCfg->frDmyClk;
  } else if (SF_CTRL_DO_MODE == ioMode) {
    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
    cmd               = flashCfg->fastReadDoCmd;
    dummyClks         = flashCfg->frDoDmyClk;
  } else if (SF_CTRL_DIO_MODE == ioMode) {
    flashCmd.addrMode = SF_CTRL_ADDR_2_LINES;
    flashCmd.dataMode = SF_CTRL_DATA_2_LINES;
    cmd               = flashCfg->fastReadDioCmd;
    dummyClks         = flashCfg->frDioDmyClk;
  } else if (SF_CTRL_QO_MODE == ioMode) {
    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = flashCfg->fastReadQoCmd;
    dummyClks         = flashCfg->frQoDmyClk;
  } else if (SF_CTRL_QIO_MODE == ioMode) {
    flashCmd.addrMode = SF_CTRL_ADDR_4_LINES;
    flashCmd.dataMode = SF_CTRL_DATA_4_LINES;
    cmd               = flashCfg->fastReadQioCmd;
    dummyClks         = flashCfg->frQioDmyClk;
  } else {
    return ERROR;
  }

  /* Prepare command */
  flashCmd.rwFlag   = SF_CTRL_READ;
  flashCmd.addrSize = 3;

  if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) {
    noReadModeCfg = flashCfg->cReadSupport & 0x02;
    cReadSupport  = flashCfg->cReadSupport & 0x01;

    if (noReadModeCfg == 0) {
      /* Read mode must be set*/
      if (cReadSupport == 0) {
        /* Not support cont read,but we still need set read mode(winbond 80dv)*/
        flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
      } else {
        /* Flash support cont read, setting depend on user parameter */
        if (contRead) {
          flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24);
        } else {
          flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24);
        }
      }

      flashCmd.addrSize++;
    }
  }

  flashCmd.dummyClks = dummyClks;

  /* Read data */
  for (i = 0; i < len;) {
    /* Prepare command */
    flashCmd.cmdBuf[0] = (cmd << 24) | (addr);
    curLen             = len - i;

    if (curLen >= FLASH_CTRL_BUF_SIZE) {
      curLen          = FLASH_CTRL_BUF_SIZE;
      flashCmd.nbData = curLen;
    } else {
      /* Make sf_ctrl word read */
      flashCmd.nbData = ((curLen + 3) >> 2) << 2;
    }

    SF_Ctrl_SendCmd(&flashCmd);

    timeOut = SFCTRL_BUSY_STATE_TIMEOUT;

    while (SET == SF_Ctrl_GetBusyState()) {
      timeOut--;

      if (timeOut == 0) {
        return TIMEOUT;
      }
    }

    BL702_MemCpy_Fast(data, flashCtrlBuf, curLen);

    addr += curLen;
    i += curLen;
    data += curLen;
  }

  return SUCCESS;
}
#endif

/*@} end of group SFLASH_Public_Functions */

/*@} end of group SFLASH */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c
================================================
/**
 ******************************************************************************
 * @file    bl702_sflash_ext.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2019 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_sflash_ext.h"
#include "bl702_sf_ctrl.h"
#include "l1c_reg.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SFLASH_EXT
 *  @{
 */

/** @defgroup  SFLASH_EXT_Private_Macros
 *  @{
 */

/*@} end of group SFLASH_EXT_Private_Macros */

/** @defgroup  SFLASH_EXT_Private_Types
 *  @{
 */

/*@} end of group SFLASH_EXT_Private_Types */

/** @defgroup  SFLASH_EXT_Private_Variables
 *  @{
 */

/*@} end of group SFLASH_EXT_Private_Variables */

/** @defgroup  SFLASH_EXT_Global_Variables
 *  @{
 */

/*@} end of group SFLASH_EXT_Global_Variables */

/** @defgroup  SFLASH_EXT_Private_Fun_Declaration
 *  @{
 */

/*@} end of group SFLASH_EXT_Private_Fun_Declaration */

/** @defgroup  SFLASH_EXT_Private_Functions
 *  @{
 */

/*@} end of group SFLASH_EXT_Private_Functions */

/** @defgroup  SFLASH_EXT_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  KH25V40 flash write protect set
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  protect: protect area
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect) {
  uint32_t stat = 0, ret;

  SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
  if (((stat >> 2) & 0xf) == protect) {
    return SUCCESS;
  }

  stat |= ((protect << 2) & 0xff);

  ret = SFlash_Write_Enable(flashCfg);
  if (SUCCESS != ret) {
    return ERROR;
  }

  SFlash_Write_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
  SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1);
  if (((stat >> 2) & 0xf) == protect) {
    return SUCCESS;
  }

  return ERROR;
}

/****************************************************************************/ /**
                                                                                * @brief  Read flash register with read command
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  readRegCmd: read command
                                                                                * @param  regValue: register value pointer to store data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;
  uint32_t             cnt = 0;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  flashCmd.cmdBuf[0] = readRegCmd << 24;
  flashCmd.rwFlag    = SF_CTRL_READ;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  while (SET == SF_Ctrl_GetBusyState()) {
    BL702_Delay_US(1);
    cnt++;

    if (cnt > 1000) {
      return ERROR;
    }
  }

  BL702_MemCpy(regValue, flashCtrlBuf, regLen);
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Write flash register with write command
                                                                                *
                                                                                * @param  flashCfg: Serial flash parameter configuration pointer
                                                                                * @param  writeRegCmd: write command
                                                                                * @param  regValue: register value pointer storing data
                                                                                * @param  regLen: register value length
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) {
  uint8_t *const       flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
  uint32_t             cnt          = 0;
  SF_Ctrl_Cmd_Cfg_Type flashCmd;

  if (((uint32_t)&flashCmd) % 4 == 0) {
    BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
  } else {
    BL702_MemSet(&flashCmd, 0, sizeof(flashCmd));
  }

  BL702_MemCpy(flashCtrlBuf, regValue, regLen);

  flashCmd.cmdBuf[0] = writeRegCmd << 24;
  flashCmd.rwFlag    = SF_CTRL_WRITE;
  flashCmd.nbData    = regLen;

  SF_Ctrl_SendCmd(&flashCmd);

  /* take 40ms for tw(write status register) as default */
  while (SET == SFlash_Busy(flashCfg)) {
    BL702_Delay_US(100);
    cnt++;

    if (cnt > 400) {
      return ERROR;
    }
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear flash status register
                                                                                *
                                                                                * @param  pFlashCfg: Flash configuration pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg) {
  uint32_t ret           = 0;
  uint32_t qeValue       = 0;
  uint32_t regValue      = 0;
  uint32_t readValue     = 0;
  uint8_t  readRegValue0 = 0;
  uint8_t  readRegValue1 = 0;

  if ((pFlashCfg->ioMode & 0xf) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0xf) == SF_CTRL_QIO_MODE) {
    qeValue = 1;
  }

  SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1);
  SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1);
  readValue = (readRegValue0 | (readRegValue1 << 8));
  if ((readValue & (~((1 << (pFlashCfg->qeIndex * 8 + pFlashCfg->qeBit)) | (1 << (pFlashCfg->busyIndex * 8 + pFlashCfg->busyBit)) | (1 << (pFlashCfg->wrEnableIndex * 8 + pFlashCfg->wrEnableBit))))) ==
      0) {
    return SUCCESS;
  }

  ret = SFlash_Write_Enable(pFlashCfg);
  if (SUCCESS != ret) {
    return ERROR;
  }
  if (pFlashCfg->qeWriteRegLen == 2) {
    regValue = (qeValue << (pFlashCfg->qeIndex * 8 + pFlashCfg->qeBit));
    SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 2);
  } else {
    if (pFlashCfg->qeIndex == 0) {
      regValue = (qeValue << pFlashCfg->qeBit);
    } else {
      regValue = 0;
    }
    SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 1);
    ret = SFlash_Write_Enable(pFlashCfg);
    if (SUCCESS != ret) {
      return ERROR;
    }
    if (pFlashCfg->qeIndex == 1) {
      regValue = (qeValue << pFlashCfg->qeBit);
    } else {
      regValue = 0;
    }
    SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)®Value, 1);
  }
  return SUCCESS;
}

/*@} end of group SFLASH_EXT_Public_Functions */

/*@} end of group SFLASH_EXT */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_spi.c
================================================
/**
 ******************************************************************************
 * @file    bl702_spi.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_spi.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  SPI
 *  @{
 */

/** @defgroup  SPI_Private_Macros
 *  @{
 */
#define SPI_TX_TIMEOUT_COUNT (160 * 1000)
#define SPI_RX_TIMEOUT_COUNT (160 * 1000)

/*@} end of group SPI_Private_Macros */

/** @defgroup  SPI_Private_Types
 *  @{
 */

/*@} end of group SPI_Private_Types */

/** @defgroup  SPI_Private_Variables
 *  @{
 */
static const uint32_t    spiAddr[SPI_ID_MAX]                    = {SPI_BASE};
static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = {{NULL}};

/*@} end of group SPI_Private_Variables */

/** @defgroup  SPI_Global_Variables
 *  @{
 */

/*@} end of group SPI_Global_Variables */

/** @defgroup  SPI_Private_Fun_Declaration
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
static void SPI_IntHandler(SPI_ID_Type spiNo);
#endif

/*@} end of group SPI_Private_Fun_Declaration */

/** @defgroup  SPI_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  SPI interrupt common handler function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
static void SPI_IntHandler(SPI_ID_Type spiNo) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);

  /* Transfer end interrupt,shared by both master and slave mode */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) {
    BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR));

    if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_END]();
    }
  }

  /* TX fifo ready interrupt(fifo count > fifo threshold) */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) {
    if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ]();
    }
  }

  /*  RX fifo ready interrupt(fifo count > fifo threshold) */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) {
    if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ]();
    }
  }

  /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) {
    BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR));

    if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT]();
    }
  }

  /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) {
    BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR));

    if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN]();
    }
  }

  /* TX/RX fifo overflow/underflow interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) {
    if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) {
      spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR]();
    }
  }
}
#endif

/*@} end of group SPI_Private_Functions */

/** @defgroup  SPI_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  SPI initialization function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  spiCfg: SPI configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod));
  CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence));
  CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence));
  CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv));
  CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity));

  /* Disable clock gate */
  GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_SPI);

  /* spi config */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize);
  BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(SPI_IRQn, SPI_IRQHandler);
#endif
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI set default value of all registers function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) {
  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  if (SPI_ID_0 == spiNo) {
    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Length of data phase1/0,start/stop condition and interval between frame initialization
                                                                                *         function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  clockCfg: Clock configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Configure length of data phase1/0 and start/stop condition */
  tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1);
  BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);

  /* Configure length of interval between frame */
  tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);
  BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI configure fifo function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  fifoCfg: FIFO configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Set fifo threshold value */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal);

  /* Enable or disable dma function */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set SPI SCK Clcok
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  clk: Clk
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk) {
  uint32_t glb_div = 1, spi_div = 1;
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  if (clk > 36000000) {
    clk     = 36000000;
    glb_div = 1;
    spi_div = 1;
  } else if (clk > 140625) {
    glb_div = 1;
    spi_div = 36000000 / clk;
  } else if (clk > 70312) {
    glb_div = 2;
    spi_div = 18000000 / clk;
  } else if (clk > 35156) {
    glb_div = 4;
    spi_div = 9000000 / clk;
  } else if (clk > 4394) {
    glb_div = 32;
    spi_div = 1125000 / clk;
  } else {
    glb_div = 32;
    spi_div = 256;
  }

  /* Configure length of data phase1/0 and start/stop condition */
  tmpVal = BL_RD_REG(SPIx, SPI_PRD_0);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div - 1);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div - 1);
  BL_WR_REG(SPIx, SPI_PRD_0, tmpVal);

  tmpVal = BL_RD_REG(SPIx, SPI_PRD_1);
  BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div - 1));

  GLB_Set_SPI_CLK(ENABLE, glb_div - 1);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable spi transfer
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  modeType: Master or slave mode select
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));

  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);

  if (modeType != SPI_WORK_MODE_SLAVE) {
    /* master mode */
    tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
  } else {
    /* slave mode */
    tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
    tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
  }

  BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable spi transfer
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  modeType: Master or slave mode select
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType));

  /* close master and slave */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN);
  tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN);
  BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set time-out value to trigger interrupt when spi bus is idle for the given value
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  value: Time value
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Set time-out value */
  tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE);
  BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Set de-glitch function cycle count value
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  cnt: De-glitch function cycle count
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Set count value */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt);
  BL_WR_REG(SPIx, SPI_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable rx data ignore function and set start/stop point
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  startPoint: Start point
                                                                                * @param  stopPoint: Stop point
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Enable rx ignore function */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Set start and stop point */
  tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint;
  BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable rx data ignore function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Disable rx ignore function */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear tx fifo and tx fifo overflow/underflow status
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Clear tx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear rx fifo and rx fifo overflow/underflow status
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Clear rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear spi interrupt status
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  intType: SPI interrupt type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Clear certain or all interrupt */
  tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);

  if (SPI_INT_ALL == intType) {
    tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS;
  } else {
    tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS);
  }

  BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI mask or unmask certain or all interrupt
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  intType: SPI interrupt type
                                                                                * @param  intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);

  /* Mask or unmask certain or all interrupt */
  if (SPI_INT_ALL == intType) {
    if (MASK == intMask) {
      tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS;
    } else {
      tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS);
    }
  } else {
    if (MASK == intMask) {
      tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS);
    } else {
      tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS));
    }
  }

  /* Write back */
  BL_WR_REG(SPIx, SPI_INT_STS, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Install spi interrupt callback function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  intType: SPI interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_INT_TYPE(intType));

  spiIntCbfArra[spiNo][intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI write data to tx fifo
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  data: Data to write
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, uint32_t data) {
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Write tx fifo */
  BL_WR_REG(SPIx, SPI_FIFO_WDATA, data);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send 8-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen = 0;
  uint32_t rData;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send 16-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen = 0;
  uint32_t rData;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)buff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send 24-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen = 0;
  uint32_t rData;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send 32-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen = 0;
  uint32_t rData;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, buff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI receive 8-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo, uint8_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t rxLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo with 0 */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (rxLen = 0; rxLen < tmpVal; rxLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive data and send the rest of the data 0 */
  for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive the rest of the data */
  for (; rxLen < length; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI receive 16-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo, uint16_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t rxLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo with 0 */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (rxLen = 0; rxLen < tmpVal; rxLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive data and send the rest of the data 0 */
  for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive the rest of the data */
  for (; rxLen < length; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI receive 24-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t rxLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo with 0 */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (rxLen = 0; rxLen < tmpVal; rxLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive data and send the rest of the data 0 */
  for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive the rest of the data */
  for (; rxLen < length; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI receive 32-bit datas
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  buff: Buffer of datas
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo, uint32_t *buff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t rxLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo with 0 */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (rxLen = 0; rxLen < tmpVal; rxLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive data and send the rest of the data 0 */
  for (rxLen = 0; rxLen < length - tmpVal; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0);
  }

  /* Wait receive the rest of the data */
  for (; rxLen < length; rxLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    buff[rxLen++] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send and receive 8-bit datas at the same time
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  sendBuff: Buffer of datas to send
                                                                                * @param  recvBuff: Buffer of datas received
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[txLen - tmpVal] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[length - tmpVal + txLen] = (uint8_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xff);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send and receive 16-bit datas at the same time
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  sendBuff: Buffer of datas to send
                                                                                * @param  recvBuff: Buffer of datas received
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo, uint16_t *sendBuff, uint16_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[txLen - tmpVal] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, (uint32_t)sendBuff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[length - tmpVal + txLen] = (uint16_t)(BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffff);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send and receive 24-bit datas at the same time
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  sendBuff: Buffer of datas to send
                                                                                * @param  recvBuff: Buffer of datas received
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 2));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA) & 0xffffff;
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI send and receive 32-bit datas at the same time
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  sendBuff: Buffer of datas to send
                                                                                * @param  recvBuff: Buffer of datas received
                                                                                * @param  length: Length of buffer
                                                                                * @param  timeoutType: Enable or disable timeout judgment
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo, uint32_t *sendBuff, uint32_t *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) {
  uint32_t tmpVal;
  uint32_t txLen      = 0;
  uint32_t SPIx       = spiAddr[spiNo];
  uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT;

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType));

  /* Set valid width for each fifo entry */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3));

  /* Disable rx ignore */
  tmpVal = BL_RD_REG(SPIx, SPI_CONFIG);
  BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN));

  /* Clear tx and rx fifo */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR);
  tmpVal = BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR);
  BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal);

  /* Fill tx fifo */
  tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE;

  for (txLen = 0; txLen < tmpVal; txLen++) {
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
  }

  /* Wait receive data and send the rest of the data */
  for (; txLen < length; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
    BL_WR_REG(SPIx, SPI_FIFO_WDATA, sendBuff[txLen]);
  }

  /* Wait receive the rest of the data */
  for (txLen = 0; txLen < tmpVal; txLen++) {
    timeoutCnt = SPI_RX_TIMEOUT_COUNT;

    while (SPI_GetRxFifoCount(spiNo) == 0) {
      if (timeoutType) {
        timeoutCnt--;

        if (timeoutCnt == 0) {
          return TIMEOUT;
        }
      }
    }

    recvBuff[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  SPI read data from rx fifo
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return Data readed
                                                                                *
                                                                                *******************************************************************************/
uint32_t SPI_ReceiveData(SPI_ID_Type spiNo) {
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  return BL_RD_REG(SPIx, SPI_FIFO_RDATA);
}

/****************************************************************************/ /**
                                                                                * @brief  Get tx fifo available count value function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return Count value
                                                                                *
                                                                                *******************************************************************************/
uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo) {
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Get count value */
  return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT);
}

/****************************************************************************/ /**
                                                                                * @brief  Get rx fifo available count value function
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return Count value
                                                                                *
                                                                                *******************************************************************************/
uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo) {
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Get count value */
  return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT);
}

/****************************************************************************/ /**
                                                                                * @brief  Get spi interrupt status
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  intType: SPI interrupt type
                                                                                *
                                                                                * @return Status of interrupt
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_INT_TYPE(intType));

  /* Get certain or all interrupt status */
  tmpVal = BL_RD_REG(SPIx, SPI_INT_STS);

  if (SPI_INT_ALL == intType) {
    if ((tmpVal & 0x3f) != 0) {
      return SET;
    } else {
      return RESET;
    }
  } else {
    if ((tmpVal & (1U << intType)) != 0) {
      return SET;
    } else {
      return RESET;
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get indicator of spi bus busy
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                *
                                                                                * @return Status of spi bus
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));

  /* Get bus busy status */
  tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY);

  if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get tx/rx fifo overflow or underflow status
                                                                                *
                                                                                * @param  spiNo: SPI ID type
                                                                                * @param  fifoSts: Select tx/rx overflow or underflow
                                                                                *
                                                                                * @return Status of tx/rx fifo
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts) {
  uint32_t tmpVal;
  uint32_t SPIx = spiAddr[spiNo];

  /* Check the parameters */
  CHECK_PARAM(IS_SPI_ID_TYPE(spiNo));
  CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts));

  /* Get tx/rx fifo overflow or underflow status */
  tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0);

  if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  SPI interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void SPI_IRQHandler(void) { SPI_IntHandler(SPI_ID_0); }
#endif

/*@} end of group SPI_Public_Functions */

/*@} end of group SPI */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_timer.c
================================================
/**
 ******************************************************************************
 * @file    bl702_timer.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_timer.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  TIMER
 *  @{
 */

/** @defgroup  TIMER_Private_Macros
 *  @{
 */
#define TIMER_MAX_MATCH 3

/*@} end of group TIMER_Private_Macros */

/** @defgroup  TIMER_Private_Types
 *  @{
 */

/*@} end of group TIMER_Private_Types */

/** @defgroup  TIMER_Private_Variables
 *  @{
 */
intCallback_Type *timerIntCbfArra[3][TIMER_INT_ALL] = {
    {NULL, NULL, NULL},
    {NULL, NULL, NULL},
    {NULL, NULL, NULL}
};

/*@} end of group TIMER_Private_Variables */

/** @defgroup  TIMER_Global_Variables
 *  @{
 */

/*@} end of group TIMER_Global_Variables */

/** @defgroup  TIMER_Private_Fun_Declaration
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
static void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh);
#endif

/*@} end of group TIMER_Private_Fun_Declaration */

/** @defgroup  TIMER_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  TIMER interrupt common handler function
                                                                                *
                                                                                * @param  irqNo: Interrupt ID type
                                                                                * @param  timerCh: TIMER channel type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_IntHandler(IRQn_Type irqNo, TIMER_Chan_Type timerCh) {
  uint32_t intId;
  uint32_t tmpVal;
  uint32_t tmpAddr;

  intId   = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh);
  tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh;
  tmpVal  = BL_RD_WORD(tmpAddr);

  /* Comparator 0 match interrupt */
  if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0)) {
    BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0));

    if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0] != NULL) {
      /* Call the callback function */
      timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_0]();
    }
  }

  /* Comparator 1 match interrupt */
  if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_1)) {
    BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_1));

    if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1] != NULL) {
      /* Call the callback function */
      timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_1]();
    }
  }

  /* Comparator 2 match interrupt */
  if (BL_IS_REG_BIT_SET(intId, TIMER_TMSR_2)) {
    BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_2));

    if (timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2] != NULL) {
      /* Call the callback function */
      timerIntCbfArra[irqNo - TIMER_CH0_IRQn][TIMER_INT_COMP_2]();
    }
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get the specified channel and match comparator value
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  cmpNo: TIMER comparator ID type
                                                                                *
                                                                                * @return Match comapre register value
                                                                                *
                                                                                *******************************************************************************/
uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));

  tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo));
  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set specified channel and comparator compare value
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  cmpNo: TIMER comparator ID type
                                                                                * @param  val: TIMER match comapre register value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) {
  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));

  BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get the specified channel count value
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                *
                                                                                * @return TIMER count register value
                                                                                *
                                                                                *******************************************************************************/
uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh) {
  uint32_t tmpVal;
  uint32_t tmpAddr;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));

  /* TO avoid risk of reading, don't read TCVWR directly*/
  /* request for read*/
  tmpAddr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timerCh;
  BL_WR_WORD(tmpAddr, 1);

  /* Need wait */
  tmpVal = BL_RD_WORD(tmpAddr);
  tmpVal = BL_RD_WORD(tmpAddr);
  tmpVal = BL_RD_WORD(tmpAddr);

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get specified channel and comparator match status
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  cmpNo: TIMER comparator ID type
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) {
  uint32_t    tmpVal;
  BL_Sts_Type bitStatus = RESET;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));

  tmpVal = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timerCh);

  switch (cmpNo) {
  case TIMER_COMP_ID_0:
    bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_0) ? SET : RESET;
    break;

  case TIMER_COMP_ID_1:
    bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_1) ? SET : RESET;
    break;

  case TIMER_COMP_ID_2:
    bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TMSR_2) ? SET : RESET;
    break;

  default:
    break;
  }

  return bitStatus;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get specified channel preload value
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                *
                                                                                * @return Preload register value
                                                                                *
                                                                                *******************************************************************************/
uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh) {
  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));

  return BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set preload register low 32bits value
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  val: Preload register low 32bits value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh, uint32_t val) {
  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));

  BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timerCh, val);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  plSrc: TIMER preload source type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_SetPreloadTrigSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) {
  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc));

  BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set count mode:preload or free run
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) {
  uint32_t tmpval;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode));

  tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
  tmpval &= (~(1 << (timerCh + 1)));
  tmpval |= (countMode << (timerCh + 1));

  BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER clear interrupt status
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  cmpNo: TIMER macth comparator ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) {
  uint32_t tmpAddr;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo));

  tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timerCh;

  tmpVal = BL_RD_WORD(tmpAddr);
  tmpVal |= (1 << cmpNo);

  BL_WR_WORD(tmpAddr, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER initialization function
                                                                                *
                                                                                * @param  timerCfg: TIMER configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type TIMER_Init(TIMER_CFG_Type *timerCfg) {
  TIMER_Chan_Type timerCh = timerCfg->timerCh;
  uint32_t        tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc));
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh));
  CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc));
  CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode));

  /* Configure timer clock source */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);

  if (timerCh == TIMER_CH0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_1, timerCfg->clkSrc);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc);
  }

  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal);

  /* Configure timer clock division */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);

  if (timerCh == TIMER_CH0) {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision);
  } else {
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision);
  }

  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal);

  /* Configure timer count mode: preload or free run */
  TIMER_SetCountMode(timerCh, timerCfg->countMode);

  /* Configure timer preload trigger src */
  TIMER_SetPreloadTrigSrc(timerCh, timerCfg->plTrigSrc);

  if (timerCfg->countMode == TIMER_COUNT_PRELOAD) {
    /* Configure timer preload value */
    TIMER_SetPreloadValue(timerCh, timerCfg->preLoadVal);

    /* Configure match compare values */
    if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);
    }

    if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);
    }

    if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);
    }
  } else {
    /* Configure match compare values */
    if (timerCfg->matchVal0 > 1) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0);
    }

    if (timerCfg->matchVal1 > 1) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1);
    }

    if (timerCfg->matchVal2 > 1) {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2);
    } else {
      TIMER_SetCompValue(timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2);
    }
  }

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQHandler);
  Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQHandler);
#endif

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER enable one channel function
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_Enable(TIMER_Chan_Type timerCh) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER);
  tmpVal |= (1 << (timerCh + 1));

  BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER disable one channel function
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_Disable(TIMER_Chan_Type timerCh) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCER);
  tmpVal &= (~(1 << (timerCh + 1)));

  BL_WR_REG(TIMER_BASE, TIMER_TCER, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER mask or unmask certain or all interrupt
                                                                                *
                                                                                * @param  timerCh: TIMER channel type
                                                                                * @param  intType: TIMER interrupt type
                                                                                * @param  intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void TIMER_IntMask(TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpAddr;
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh));
  CHECK_PARAM(IS_TIMER_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpAddr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timerCh;
  tmpVal  = BL_RD_WORD(tmpAddr);

  switch (intType) {
  case TIMER_INT_COMP_0:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0));
    } else {
      /* Disable this interrupt */
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0));
    }

    break;

  case TIMER_INT_COMP_1:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1));
    } else {
      /* Disable this interrupt */
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1));
    }

    break;

  case TIMER_INT_COMP_2:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2));
    } else {
      /* Disable this interrupt */
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2));
    }

    break;

  case TIMER_INT_ALL:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_0));
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_1));
      BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER_2));
    } else {
      /* Disable this interrupt */
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_0));
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_1));
      BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER_2));
    }

    break;

  default:
    break;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set watchdog clock source and clock division
                                                                                *
                                                                                * @param  clkSrc: Watchdog timer clock source type
                                                                                * @param  div: Watchdog timer clock division value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc, uint8_t div) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc));

  /* Configure watchdog timer clock source */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc);
  BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpVal);

  /* Configure watchdog timer clock divison */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div);
  BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpVal);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get watchdog match compare value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Watchdog match comapre register value
                                                                                *
                                                                                *******************************************************************************/
uint16_t WDT_GetMatchValue(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  /* Get watchdog timer match register value */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMR);

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER set watchdog match compare value
                                                                                *
                                                                                * @param  val: Watchdog match compare value
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_SetCompValue(uint16_t val) {
  WDT_ENABLE_ACCESS();

  /* Set watchdog timer match register value */
  BL_WR_REG(TIMER_BASE, TIMER_WMR, val);
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get watchdog count register value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return Watchdog count register value
                                                                                *
                                                                                *******************************************************************************/
uint16_t WDT_GetCounterValue(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  /* Get watchdog timer count register value */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WVR);

  return tmpVal;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER reset watchdog count register value
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_ResetCounterValue(void) {
  uint32_t tmpVal;

  /* Reset watchdog timer count register value */
  WDT_ENABLE_ACCESS();

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WCR);

  /* Set watchdog counter reset register bit0 to 1 */
  BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR));
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER get watchdog reset status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return SET or RESET
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type WDT_GetResetStatus(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  /* Get watchdog status register */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR);

  return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET;
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER clear watchdog reset status
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_ClearResetStatus(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WSR);

  /* Set watchdog status register */
  BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS));
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER enable watchdog function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_Enable(void) {
  uint32_t tmpVal;

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(TIMER_WDT_IRQn, TIMER_WDT_IRQHandler);
#endif

  WDT_ENABLE_ACCESS();

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);

  BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE));
}

/****************************************************************************/ /**
                                                                                * @brief  Watchdog timer disable function
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_Disable(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);

  BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE));
}

/****************************************************************************/ /**
                                                                                * @brief  Watchdog timer mask or unmask certain or all interrupt
                                                                                *
                                                                                * @param  intType: Watchdog interrupt type
                                                                                * @param  intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_WDT_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  WDT_ENABLE_ACCESS();

  /* Deal with watchdog match/interrupt enable register,
    WRIE:watchdog reset/interrupt enable */
  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WMER);

  switch (intType) {
  case WDT_INT:
    if (intMask == UNMASK) {
      /* Enable this interrupt */
      /* 0 means generates a watchdog interrupt,
         a watchdog timer reset is not generated*/
      BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE));
    } else {
      /* Disable this interrupt */
      /* 1 means generates a watchdog timer reset,
         a watchdog  interrupt is not generated*/
      BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE));
    }

    break;

  default:
    break;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  TIMER channel 0 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_CH0_IRQHandler(void) { TIMER_IntHandler(TIMER_CH0_IRQn, TIMER_CH0); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  TIMER channel 1 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_CH1_IRQHandler(void) { TIMER_IntHandler(TIMER_CH1_IRQn, TIMER_CH1); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  TIMER watchdog interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_WDT_IRQHandler(void) {
  uint32_t tmpVal;

  WDT_ENABLE_ACCESS();

  tmpVal = BL_RD_REG(TIMER_BASE, TIMER_WICR);
  BL_WR_REG(TIMER_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR));

  if (timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT] != NULL) {
    /* Call the callback function */
    timerIntCbfArra[TIMER_WDT_IRQn - TIMER_CH0_IRQn][WDT_INT]();
  }
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  TIMER install interrupt callback
                                                                                *
                                                                                * @param  timerChan: TIMER channel type
                                                                                * @param  intType: TIMER interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan));
  CHECK_PARAM(IS_TIMER_INT_TYPE(intType));

  timerIntCbfArra[timerChan][intType] = cbFun;
}

/****************************************************************************/ /**
                                                                                * @brief  Watchdog install interrupt callback
                                                                                *
                                                                                * @param  wdtInt: Watchdog interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void WDT_Int_Callback_Install(WDT_INT_Type wdtInt, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt));

  timerIntCbfArra[2][wdtInt] = cbFun;
}

/*@} end of group TIMER_Private_Functions */

/*@} end of group TIMER */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_uart.c
================================================
/**
 ******************************************************************************
 * @file    bl702_uart.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_uart.h"
#include "bl702_glb.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  UART
 *  @{
 */

/** @defgroup  UART_Private_Macros
 *  @{
 */
#define UART_TX_TIMEOUT_COUNT (160 * 1000)

/*@} end of group UART_Private_Macros */

/** @defgroup  UART_Private_Types
 *  @{
 */

/*@} end of group UART_Private_Types */

/** @defgroup  UART_Private_Variables
 *  @{
 */
static const uint32_t    uartAddr[2]                     = {UART0_BASE, UART1_BASE};
static intCallback_Type *uartIntCbfArra[2][UART_INT_ALL] = {{NULL}, {NULL}};

/*@} end of group UART_Private_Variables */

/** @defgroup  UART_Global_Variables
 *  @{
 */

/*@} end of group UART_Global_Variables */

/** @defgroup  UART_Private_Fun_Declaration
 *  @{
 */
#ifndef BFLB_USE_HAL_DRIVER
static void UART_IntHandler(UART_ID_Type uartId);
#endif

/*@} end of group UART_Private_Fun_Declaration */

/** @defgroup  UART_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  UART interrupt common handler function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
static void UART_IntHandler(UART_ID_Type uartId) {
  uint32_t tmpVal  = 0;
  uint32_t maskVal = 0;
  uint32_t UARTx   = uartAddr[uartId];

  tmpVal  = BL_RD_REG(UARTx, UART_INT_STS);
  maskVal = BL_RD_REG(UARTx, UART_INT_MASK);

  /* Length of uart tx data transfer arrived interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);

    if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) {
      uartIntCbfArra[uartId][UART_INT_TX_END]();
    }
  }

  /* Length of uart rx data transfer arrived interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);

    if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) {
      uartIntCbfArra[uartId][UART_INT_RX_END]();
    }
  }

  /* Tx fifo ready interrupt,auto-cleared when data is pushed */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK)) {
    if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) {
      uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();
    }
  }

  /* Rx fifo ready interrupt,auto-cleared when data is popped */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK)) {
    if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) {
      uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();
    }
  }

  /* Rx time-out interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);

    if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) {
      uartIntCbfArra[uartId][UART_INT_RTO]();
    }
  }

  /* Rx parity check error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);

    if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) {
      uartIntCbfArra[uartId][UART_INT_PCE]();
    }
  }

  /* Tx fifo overflow/underflow error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
    if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) {
      uartIntCbfArra[uartId][UART_INT_TX_FER]();
    }
  }

  /* Rx fifo overflow/underflow error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
    if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) {
      uartIntCbfArra[uartId][UART_INT_RX_FER]();
    }
  }

  /* Rx lin mode sync field error interrupt */
  if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) {
    BL_WR_REG(UARTx, UART_INT_CLEAR, 0x100);

    if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) {
      uartIntCbfArra[uartId][UART_INT_LSE]();
    }
  }
}
#endif

/*@} end of group UART_Private_Functions */

/** @defgroup  UART_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  UART initialization function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  uartCfg: UART configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg) {
  uint32_t tmpValTxCfg     = 0;
  uint32_t tmpValRxCfg     = 0;
  uint32_t fraction        = 0;
  uint32_t baudRateDivisor = 0;
  uint32_t UARTx           = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity));
  CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits));
  CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits));
  CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse));

  /* Cal the baud rate divisor */
  fraction        = uartCfg->uartClk * 10 / uartCfg->baudRate % 10;
  baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate;

  if (fraction >= 5) {
    ++baudRateDivisor;
  }

  /* Set the baud rate register value */
  BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF));

  /* Configure parity type */
  tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG);
  tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG);

  switch (uartCfg->parity) {
  case UART_PARITY_NONE:
    tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
    tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
    break;

  case UART_PARITY_ODD:
    tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
    tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);
    tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
    tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);
    break;

  case UART_PARITY_EVEN:
    tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN);
    tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL);
    tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN);
    tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL);
    break;

  default:
    break;
  }

  /* Configure data bits */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4));
  tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4));

  /* Configure tx stop bits */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits);

  /* Configure tx cts flow control function */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl);

  /* Configure rx input de-glitch function */
  tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch);

  /* Configure tx lin mode function */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode);

  /* Configure rx lin mode function */
  tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode);

  /* Set tx break bit count for lin protocol */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt);

  /* Write back */
  BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg);
  BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg);

  /* Configure LSB-first or MSB-first */
  tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG);

  if (UART_MSB_FIRST == uartCfg->byteBitInverse) {
    tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);
  } else {
    tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV);
  }

  BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg);

  tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE);
  /* Configure rx rts output SW control mode */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl);
  /* Configure tx output SW control mode */
  tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl);
  BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg);

#ifndef BFLB_USE_HAL_DRIVER
  Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler);
  Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler);
#endif
  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set default value of all registers function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_DeInit(UART_ID_Type uartId) {
  if (UART0_ID == uartId) {
    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
  } else if (UART1_ID == uartId) {
    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART configure fifo function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  fifoCfg: FIFO configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Deal with uart fifo configure register */
  tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1);
  /* Configure dma tx fifo threshold */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold);
  /* Configure dma rx fifo threshold */
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold);
  /* Write back */
  BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal);

  /* Enable or disable uart fifo dma function */
  tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);

  if (ENABLE == fifoCfg->txFifoDmaEnable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN);
  }

  if (ENABLE == fifoCfg->rxFifoDmaEnable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN);
  }

  BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART configure infra function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  irCfg: IR configuration structure pointer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Configure tx ir mode */
  tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);

  if (ENABLE == irCfg->txIrEnable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN);
  }

  if (ENABLE == irCfg->txIrInverse) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV);
  }

  BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal);

  /* Configure rx ir mode */
  tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);

  if (ENABLE == irCfg->rxIrEnable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN);
  }

  if (ENABLE == irCfg->rxIrInverse) {
    tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV);
  }

  BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);

  /* Configure tx ir pulse start and stop position */
  BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart);

  /* Configure rx ir pulse start position */
  BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Enable UART
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  direct: UART direction type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));

  if (direct == UART_TX || direct == UART_TXRX) {
    /* Enable UART tx unit */
    tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
    BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN));
  }

  if (direct == UART_RX || direct == UART_TXRX) {
    /* Enable UART rx unit */
    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
    BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Disable UART
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  direct: UART direction type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct));

  if (direct == UART_TX || direct == UART_TXRX) {
    /* Disable UART tx unit */
    tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
    BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN));
  }

  if (direct == UART_RX || direct == UART_TXRX) {
    /* Disable UART rx unit */
    tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
    BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set length of tx data transfer,tx end interrupt will assert when this length is
                                                                                *         reached
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  length: Length of data (unit:character/byte)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Set length */
  tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);
  BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set length of rx data transfer,rx end interrupt will assert when this length is
                                                                                *         reached
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  length: Length of data (unit:character/byte)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Set length */
  tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
  BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set rx time-out value for triggering RTO interrupt
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  time: Time-out value (unit:bit time)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Set time-out value */
  tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1);
  BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set de-glitch function cycle count value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  deglitchCnt: De-glitch function cycle count
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Set count value */
  tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt);
  BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set tx and rx baudrate according to auto baudrate detection value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  autoBaudDet: Choose detection value using codeword 0x55 or start bit
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) {
  uint32_t UARTx = uartAddr[uartId];
  uint16_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Get detection value */
  tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet);

  /* Set tx baudrate */
  BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set rx rts output software control value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Rts set 1*/
  tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
  BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART clear rx rts output software control value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Rts clear 0 */
  tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
  BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART set tx output software control value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SetTxValue(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Tx set 1*/
  tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
  BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART clear tx output software control value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];
  uint32_t tmpVal;

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Rts clear 0 */
  tmpVal = BL_RD_REG(UARTx, UART_SW_MODE);
  BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART configure tx free run mode function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  txFreeRun: Enable or disable tx free run mode
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Enable or disable tx free run mode */
  tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG);

  if (ENABLE == txFreeRun) {
    BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));
  } else {
    BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART configure auto baud rate detection function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  autoBaud: Enable or disable auto function
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Enable or disable auto baud rate detection function */
  tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG);

  if (ENABLE == autoBaud) {
    BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));
  } else {
    BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN));
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART tx fifo clear
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Clear tx fifo */
  tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
  BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART rx fifo clear
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) {
  uint32_t tmpVal = 0;
  uint32_t UARTx  = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Clear rx fifo */
  tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);
  BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR));

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART mask or unmask certain or all interrupt
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  intType: UART interrupt type
                                                                                * @param  intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt )
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_INT_TYPE(intType));
  CHECK_PARAM(IS_BL_MASK_TYPE(intMask));

  tmpVal = BL_RD_REG(UARTx, UART_INT_MASK);

  /* Mask or unmask certain or all interrupt */
  if (UART_INT_ALL == intType) {
    if (MASK == intMask) {
      tmpVal |= 0x1ff;
    } else {
      tmpVal &= 0;
    }
  } else {
    if (MASK == intMask) {
      tmpVal |= 1 << intType;
    } else {
      tmpVal &= ~(1 << intType);
    }
  }

  /* Write back */
  BL_WR_REG(UARTx, UART_INT_MASK, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART clear certain or all interrupt
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  intType: UART interrupt type
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_INT_TYPE(intType));

  tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR);

  /* Clear certain or all interrupt */
  if (UART_INT_ALL == intType) {
    tmpVal |= 0x1ff;
  } else {
    tmpVal |= 1 << intType;
  }

  /* Write back */
  BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal);

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  Install uart interrupt callback function
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  intType: UART interrupt type
                                                                                * @param  cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) {
  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_INT_TYPE(intType));

  uartIntCbfArra[uartId][intType] = cbFun;

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART send data to tx fifo
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  data: The data to be send
                                                                                * @param  len: The length of the send buffer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len) {
  uint32_t txLen      = 0;
  uint32_t UARTx      = uartAddr[uartId];
  uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Send data */
  while (txLen < len) {
    if (UART_GetTxFifoCount(uartId) > 0) {
      BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);
      timeoutCnt = UART_TX_TIMEOUT_COUNT;
    } else {
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    }
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART send data to tx fifo in block mode
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  data: The data to be send
                                                                                * @param  len: The length of the send buffer
                                                                                *
                                                                                * @return SUCCESS
                                                                                *
                                                                                *******************************************************************************/
BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len) {
  uint32_t txLen      = 0;
  uint32_t UARTx      = uartAddr[uartId];
  uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT;

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Send data */
  while (txLen < len) {
    if (UART_GetTxFifoCount(uartId) > 0) {
      BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]);
      timeoutCnt = UART_TX_TIMEOUT_COUNT;
    } else {
      timeoutCnt--;

      if (timeoutCnt == 0) {
        return TIMEOUT;
      }
    }
  }

  while (UART_GetTxBusBusyStatus(uartId) == SET) {
  }

  return SUCCESS;
}

/****************************************************************************/ /**
                                                                                * @brief  UART receive data from rx fifo
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  data: The receive data buffer
                                                                                * @param  maxLen: The max length of the buffer
                                                                                *
                                                                                * @return The length of the received buffer
                                                                                *
                                                                                *******************************************************************************/
uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen) {
  uint32_t rxLen = 0;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Receive data */
  while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) {
    data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET);
  }

  return rxLen;
}

/****************************************************************************/ /**
                                                                                * @brief  UART get auto baud count value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  autoBaudDet: Detection using codeword 0x55 or start bit
                                                                                *
                                                                                * @return Bit period of auto baudrate detection
                                                                                *
                                                                                *******************************************************************************/
uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) {
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet));

  /* Select 0x55 or start bit detection value */
  if (UART_AUTOBAUD_0X55 == autoBaudDet) {
    return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff;
  } else {
    return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  UART get tx fifo unoccupied count value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return Tx fifo unoccupied count value
                                                                                *
                                                                                *******************************************************************************/
uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
}

/****************************************************************************/ /**
                                                                                * @brief  UART get rx fifo occupied count value
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return Rx fifo occupied count value
                                                                                *
                                                                                *******************************************************************************/
uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) {
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameter */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
}

/****************************************************************************/ /**
                                                                                * @brief  Get uart interrupt status
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  intType: UART interrupt type
                                                                                *
                                                                                * @return Status of interrupt
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_INT_TYPE(intType));

  /* Get certain or all interrupt status */
  tmpVal = BL_RD_REG(UARTx, UART_INT_STS);

  if (UART_INT_ALL == intType) {
    if ((tmpVal & 0x1ff) != 0) {
      return SET;
    } else {
      return RESET;
    }
  } else {
    if ((tmpVal & (1U << intType)) != 0) {
      return SET;
    } else {
      return RESET;
    }
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get indicator of uart tx bus busy
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return Status of tx bus
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Get tx bus busy status */
  tmpVal = BL_RD_REG(UARTx, UART_STATUS);

  if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get indicator of uart rx bus busy
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                *
                                                                                * @return Status of rx bus
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));

  /* Get rx bus busy status */
  tmpVal = BL_RD_REG(UARTx, UART_STATUS);

  if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Get tx/rx fifo overflow or underflow status
                                                                                *
                                                                                * @param  uartId: UART ID type
                                                                                * @param  overflow: Select tx/rx overflow or underflow
                                                                                *
                                                                                * @return Status of tx/rx fifo
                                                                                *
                                                                                *******************************************************************************/
BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow) {
  uint32_t tmpVal;
  uint32_t UARTx = uartAddr[uartId];

  /* Check the parameters */
  CHECK_PARAM(IS_UART_ID_TYPE(uartId));
  CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow));

  /* Get tx/rx fifo overflow or underflow status */
  tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0);

  if ((tmpVal & (1U << (overflow + 4))) != 0) {
    return SET;
  } else {
    return RESET;
  }
}

/****************************************************************************/ /**
                                                                                * @brief  UART0 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void UART0_IRQHandler(void) { UART_IntHandler(UART0_ID); }
#endif

/****************************************************************************/ /**
                                                                                * @brief  UART1 interrupt handler
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void UART1_IRQHandler(void) { UART_IntHandler(UART1_ID); }
#endif

/*@} end of group UART_Public_Functions */

/*@} end of group UART */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_usb.c
================================================
/**
 ******************************************************************************
 * @file    bl70x_usb.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2019 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_usb.h"
#include "bl702_common.h"
#include "bl702_glb.h"

/** @addtogroup  BL70X_Peripheral_Driver
 *  @{
 */

/** @addtogroup  USB
 *  @{
 */

/** @defgroup  USB_Private_Macros
 *  @{
 */

/*@} end of group USB_Private_Macros */

/** @defgroup  USB_Private_Types
 *  @{
 */

/*@} end of group USB_Private_Types */

/** @defgroup  USB_Private_Variables
 *  @{
 */

/*@} end of group USB_Private_Variables */

/** @defgroup  USB_Global_Variables
 *  @{
 */

/*@} end of group USB_Global_Variables */

/** @defgroup  USB_Private_Fun_Declaration
 *  @{
 */

/*@} end of group USB_Private_Fun_Declaration */

/** @defgroup  USB_Private_Functions
 *  @{
 */

/*@} end of group USB_Private_Functions */

/** @defgroup  USB_Public_Functions
 *  @{
 */

BL_Err_Type USB_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN);
  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN);
  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Set_Config(BL_Fun_Type enable, USB_Config_Type *usbCfg) {
  uint32_t tmpVal = 0;

  /* disable USB first */
  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EN);
  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  /* USB config */
  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);

  if (usbCfg->SoftwareCtrl == ENABLE) {
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, usbCfg->DeviceAddress);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, usbCfg->EnumMaxPacketSize);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_IN, usbCfg->EnumInEn);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT, usbCfg->EnumOutEn);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed);
  } else {
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_CTRL);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_ROM_DCT_EN, usbCfg->RomBaseDescriptorUsed);
  }

  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  /* enable/disable USB */
  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);

  if (enable) {
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EN);
  }

  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Set_Device_Addr(uint8_t addr) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR, addr);
  BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);

  return SUCCESS;
}

uint8_t USB_Get_Device_Addr(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);

  return BL_GET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_ADDR);
}

BL_Err_Type USB_Set_EPx_Xfer_Size(USB_EP_ID epId, uint8_t size) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_IN_Busy(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_IN_Stall(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_OUT_Busy(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_OUT_Stall(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_Rdy(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_RDY);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
    tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Sts_Type USB_Is_EPx_RDY_Free(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_USB_EP0_SW_RDY);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP1_RDY);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP2_RDY);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP3_RDY);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP4_RDY);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP5_RDY);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP6_RDY);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP7_RDY);
      break;

    default:
      break;
    }
  }

  return tmpVal ? RESET : SET;
}

BL_Err_Type USB_Set_EPx_STALL(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Clr_EPx_STALL(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return SUCCESS;
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_Busy(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP1_STALL);
      BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP2_STALL);
      BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP3_STALL);
      BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP4_STALL);
      BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP5_STALL);
      BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP6_STALL);
      BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_EP7_STALL);
      BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_Status(USB_EP_ID epId, USB_EP_STATUS_Type sts) {
  switch (sts) {
  case USB_EP_STATUS_ACK:
    USB_Set_EPx_Rdy(epId);
    break;

  case USB_EP_STATUS_NACK:
    USB_Set_EPx_Busy(epId);
    break;

  case USB_EP_STATUS_STALL:
    USB_Set_EPx_STALL(epId);
    break;

  case USB_EP_STATUS_NSTALL:
    USB_Clr_EPx_STALL(epId);
    break;

  default:
    break;
  }

  return SUCCESS;
}

USB_EP_STATUS_Type USB_Get_EPx_Status(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);

    switch ((tmpVal >> 24) & 0x7) {
    case 0:
      return USB_EP_STATUS_ACK;

    case 1:
      return USB_EP_STATUS_STALL;

    case 2:
    case 4:
    case 6:
      return USB_EP_STATUS_NACK;

    default:
      break;
    }
  } else {
    switch (epId) {
    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
      break;

    default:
      tmpVal = 0;
      break;
    }

    switch ((tmpVal >> 14) & 0x3) {
    case 0:
      return USB_EP_STATUS_ACK;

    case 1:
      return USB_EP_STATUS_STALL;

    case 2:
      return USB_EP_STATUS_NACK;

    case 3:
    default:
      break;
    }
  }

  return USB_EP_STATUS_NSTALL;
}

BL_Err_Type USB_IntEn(USB_INT_Type intType, uint8_t enable) {
  uint32_t tmpVal = 0;

  if (USB_INT_ALL == intType) {
    if (enable) {
      BL_WR_REG(USB_BASE, USB_INT_EN, USB_INT_TYPE_ALL);
    } else {
      BL_WR_REG(USB_BASE, USB_INT_EN, ~USB_INT_TYPE_ALL);
    }

    return SUCCESS;
  }

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_EN);

  if (enable) {
    tmpVal |= (1 << intType);
  } else {
    tmpVal &= ~(1 << intType);
  }

  BL_WR_REG(USB_BASE, USB_INT_EN, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_IntMask(USB_INT_Type intType, BL_Mask_Type intMask) {
  uint32_t tmpVal = 0;

  if (USB_INT_ALL == intType) {
    if (intMask != UNMASK) {
      BL_WR_REG(USB_BASE, USB_INT_MASK, USB_INT_TYPE_ALL);
    } else {
      BL_WR_REG(USB_BASE, USB_INT_MASK, ~USB_INT_TYPE_ALL);
    }

    return SUCCESS;
  }

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_MASK);

  if (intMask != UNMASK) {
    tmpVal |= (1 << intType);
  } else {
    tmpVal &= ~(1 << intType);
  }

  BL_WR_REG(USB_BASE, USB_INT_MASK, tmpVal);

  return SUCCESS;
}

BL_Sts_Type USB_Get_IntStatus(USB_INT_Type intType) {
  if (USB_INT_ALL == intType) {
    return BL_RD_REG(USB_BASE, USB_INT_STS) ? SET : RESET;
  }

  return ((BL_RD_REG(USB_BASE, USB_INT_STS) & (1 << intType))) ? SET : RESET;
}

BL_Err_Type USB_Clr_IntStatus(USB_INT_Type intType) {
  uint32_t tmpVal = 0;

  if (USB_INT_ALL == intType) {
    BL_WR_REG(USB_BASE, USB_INT_CLEAR, USB_INT_TYPE_ALL);

    return SUCCESS;
  }

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
  tmpVal |= (1 << intType);
  BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Clr_EPx_IntStatus(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);

  if (epId == EP_ID0) {
    tmpVal |= (0x3F << 4);
  } else {
    tmpVal |= (0x3 << (epId * 2 + 8));
  }

  BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);

  return SUCCESS;
}

uint16_t USB_Get_Frame_Num(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);

  return tmpVal & 0x7ff;
}

BL_Err_Type USB_Set_EPx_Config(USB_EP_ID epId, EP_Config_Type *epCfg) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return ERROR;
  }

  switch (epId) {
  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, epCfg->type);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, epCfg->dir);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, epCfg->EPMaxPacketSize);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_Type(USB_EP_ID epId, EP_XFER_Type type) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return ERROR;
  }

  switch (epId) {
  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE, type);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

EP_XFER_Type USB_Get_EPx_Type(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return EP_CTRL;
  }

  switch (epId) {
  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_TYPE);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_TYPE);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_TYPE);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_TYPE);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_TYPE);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_TYPE);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_TYPE);
    break;

  default:
    break;
  }

  return (EP_XFER_Type)tmpVal;
}

BL_Err_Type USB_Set_EPx_Dir(USB_EP_ID epId, EP_XFER_DIR dir) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return ERROR;
  }

  switch (epId) {
  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR, dir);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

EP_XFER_DIR USB_Get_EPx_Dir(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  if (epId == EP_ID0) {
    return EP_DISABLED;
  }

  switch (epId) {
  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP1_DIR);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP2_DIR);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP3_DIR);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP4_DIR);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP5_DIR);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP6_DIR);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_CR_EP7_DIR);
    break;

  default:
    break;
  }

  return (EP_XFER_DIR)tmpVal;
}

BL_Err_Type USB_Set_EPx_Size(USB_EP_ID epId, uint32_t size) {
  uint32_t tmpVal = 0;

  switch (epId) {
  case EP_ID0:
    tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_USB_EP0_SW_SIZE, size);
    BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
    break;

  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP1_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP2_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP3_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP4_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP5_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP6_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_EP7_SIZE, size);
    BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

BL_Sts_Type USB_Get_EPx_TX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag) {
  uint32_t tmpVal = 0;

  if (errFlag == USB_FIFO_ERROR_OVERFLOW) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_OVERFLOW);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_OVERFLOW);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_OVERFLOW);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_OVERFLOW);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_OVERFLOW);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_OVERFLOW);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_OVERFLOW);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_OVERFLOW);
      break;

    default:
      tmpVal = 0;
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_UNDERFLOW);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_UNDERFLOW);
      break;

    default:
      tmpVal = 0;
      break;
    }
  }

  return tmpVal ? SET : RESET;
}

BL_Sts_Type USB_Get_EPx_RX_FIFO_Errors(USB_EP_ID epId, USB_FIFO_ERROR_FLAG_Type errFlag) {
  uint32_t tmpVal = 0;

  if (errFlag == USB_FIFO_ERROR_OVERFLOW) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_OVERFLOW);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_OVERFLOW);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_OVERFLOW);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_OVERFLOW);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_OVERFLOW);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_OVERFLOW);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_OVERFLOW);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_OVERFLOW);
      break;

    default:
      tmpVal = 0;
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_UNDERFLOW);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_UNDERFLOW);
      break;

    default:
      tmpVal = 0;
      break;
    }
  }

  return tmpVal ? SET : RESET;
}

BL_Err_Type USB_Clr_EPx_TX_FIFO_Errors(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  switch (epId) {
  case EP_ID0:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_TX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

BL_Err_Type USB_Clr_EPx_RX_FIFO_Errors(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  switch (epId) {
  case EP_ID0:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
    tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_RX_FIFO_CLR);
    BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
    break;

  default:
    break;
  }

  return SUCCESS;
}

BL_Err_Type USB_EPx_Write_Data_To_FIFO(USB_EP_ID epId, uint8_t *pData, uint16_t len) {
  uint32_t timeout = 0x00FFFFFF;

  while ((!USB_Is_EPx_RDY_Free(epId)) && timeout) {
    timeout--;
  }

  if (!timeout) {
    return ERROR;
  }

  if (len == 1) {
    USB_Set_EPx_Xfer_Size(EP_ID0, 1);
  } else {
    USB_Set_EPx_Xfer_Size(EP_ID0, 64);
  }

  for (uint16_t i = 0; i < len; i++) {
    switch (epId) {
    case EP_ID0:
      BL_WR_REG(USB_BASE, USB_EP0_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID1:
      BL_WR_REG(USB_BASE, USB_EP1_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID2:
      BL_WR_REG(USB_BASE, USB_EP2_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID3:
      BL_WR_REG(USB_BASE, USB_EP3_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID4:
      BL_WR_REG(USB_BASE, USB_EP4_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID5:
      BL_WR_REG(USB_BASE, USB_EP5_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID6:
      BL_WR_REG(USB_BASE, USB_EP6_TX_FIFO_WDATA, pData[i]);
      break;

    case EP_ID7:
      BL_WR_REG(USB_BASE, USB_EP7_TX_FIFO_WDATA, pData[i]);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_EPx_Read_Data_From_FIFO(USB_EP_ID epId, uint8_t *pBuff, uint16_t len) {
  for (uint16_t i = 0; i < len; i++) {
    switch (epId) {
    case EP_ID0:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP0_RX_FIFO_RDATA);
      break;

    case EP_ID1:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP1_RX_FIFO_RDATA);
      break;

    case EP_ID2:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP2_RX_FIFO_RDATA);
      break;

    case EP_ID3:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP3_RX_FIFO_RDATA);
      break;

    case EP_ID4:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP4_RX_FIFO_RDATA);
      break;

    case EP_ID5:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP5_RX_FIFO_RDATA);
      break;

    case EP_ID6:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP6_RX_FIFO_RDATA);
      break;

    case EP_ID7:
      pBuff[i] = (uint8_t)BL_RD_REG(USB_BASE, USB_EP7_RX_FIFO_RDATA);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_TX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState) {
  uint32_t tmpVal = 0;

  if (newState == ENABLE) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_TX_EN);
      BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_Set_EPx_RX_DMA_Interface_Config(USB_EP_ID epId, BL_Fun_Type newState) {
  uint32_t tmpVal = 0;

  if (newState == ENABLE) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_SET_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP0_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP0_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP1_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP1_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP2_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP2_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP3_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP3_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP4_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP4_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP5_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP5_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP6_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP6_FIFO_CONFIG, tmpVal);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_CONFIG);
      tmpVal = BL_CLR_REG_BIT(tmpVal, USB_EP7_DMA_RX_EN);
      BL_WR_REG(USB_BASE, USB_EP7_FIFO_CONFIG, tmpVal);
      break;

    default:
      break;
    }
  }

  return SUCCESS;
}

BL_Err_Type USB_EPx_Write_Data_To_FIFO_DMA(USB_EP_ID epId, uint8_t *pData, uint16_t len) {
  /* not yet implemented */

  return SUCCESS;
}

BL_Err_Type USB_EPx_Read_Data_From_FIFO_DMA(USB_EP_ID epId, uint8_t *pBuff, uint16_t len) {
  /* not yet implemented */

  return SUCCESS;
}

uint16_t USB_Get_EPx_TX_FIFO_CNT(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  switch (epId) {
  case EP_ID0:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_CNT);
    break;

  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_CNT);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_CNT);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_CNT);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_CNT);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_CNT);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_CNT);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_CNT);
    break;

  default:
    tmpVal = 0;
    break;
  }

  return tmpVal;
}

uint16_t USB_Get_EPx_RX_FIFO_CNT(USB_EP_ID epId) {
  uint32_t tmpVal = 0;

  switch (epId) {
  case EP_ID0:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_CNT);
    break;

  case EP_ID1:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_CNT);
    break;

  case EP_ID2:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_CNT);
    break;

  case EP_ID3:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_CNT);
    break;

  case EP_ID4:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_CNT);
    break;

  case EP_ID5:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_CNT);
    break;

  case EP_ID6:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_CNT);
    break;

  case EP_ID7:
    tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_CNT);
    break;

  default:
    tmpVal = 0;
    break;
  }

  return tmpVal;
}

BL_Sts_Type USB_Get_EPx_TX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts) {
  uint32_t tmpVal = 0;

  if (sts == USB_FIFO_EMPTY) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_EMPTY);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_EMPTY);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_EMPTY);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_EMPTY);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_EMPTY);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_EMPTY);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_EMPTY);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_EMPTY);
      break;

    default:
      tmpVal = 0;
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_TX_FIFO_FULL);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_TX_FIFO_FULL);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_TX_FIFO_FULL);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_TX_FIFO_FULL);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_TX_FIFO_FULL);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_TX_FIFO_FULL);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_TX_FIFO_FULL);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_TX_FIFO_FULL);
      break;

    default:
      tmpVal = 0;
      break;
    }
  }

  return tmpVal ? SET : RESET;
}

BL_Sts_Type USB_Get_EPx_RX_FIFO_Status(USB_EP_ID epId, USB_FIFO_STATUS_Type sts) {
  uint32_t tmpVal = 0;

  if (sts == USB_FIFO_EMPTY) {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_EMPTY);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_EMPTY);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_EMPTY);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_EMPTY);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_EMPTY);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_EMPTY);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_EMPTY);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_EMPTY);
      break;

    default:
      tmpVal = 0;
      break;
    }
  } else {
    switch (epId) {
    case EP_ID0:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP0_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP0_RX_FIFO_FULL);
      break;

    case EP_ID1:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP1_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP1_RX_FIFO_FULL);
      break;

    case EP_ID2:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP2_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP2_RX_FIFO_FULL);
      break;

    case EP_ID3:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP3_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP3_RX_FIFO_FULL);
      break;

    case EP_ID4:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP4_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP4_RX_FIFO_FULL);
      break;

    case EP_ID5:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP5_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP5_RX_FIFO_FULL);
      break;

    case EP_ID6:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP6_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP6_RX_FIFO_FULL);
      break;

    case EP_ID7:
      tmpVal = BL_RD_REG(USB_BASE, USB_EP7_FIFO_STATUS);
      tmpVal = BL_GET_REG_BITS_VAL(tmpVal, USB_EP7_RX_FIFO_FULL);
      break;

    default:
      tmpVal = 0;
      break;
    }
  }

  return tmpVal ? SET : RESET;
}

BL_Err_Type USB_Set_Internal_PullUp_Config(BL_Fun_Type newState) {
  uint32_t tmpVal = 0;

  /* recommended: fclk<=160MHz, bclk<=80MHz */
  tmpVal = BL_RD_REG(GLB_BASE, GLB_USB_XCVR);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USB_ENUM, newState);
  BL_WR_REG(GLB_BASE, GLB_USB_XCVR, tmpVal);

  return SUCCESS;
}

BL_Sts_Type USB_Get_LPM_Status(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);

  return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM) ? SET : RESET;
}

uint16_t USB_Get_LPM_Packet_Attr(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);

  return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_LPM_ATTR);
}

BL_Err_Type USB_Set_LPM_Default_Response(USB_LPM_DEFAULT_RESP_Type defaultResp) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_LPM_RESP, defaultResp);
  BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_RESP_UPD);
  BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_LPM_Enable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_LPM_EN);
  BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_LPM_Disable(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CONFIG);
  tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CR_LPM_EN);
  BL_WR_REG(USB_BASE, USB_LPM_CONFIG, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Device_Output_K_State(uint16_t stateWidth) {
  uint32_t tmpVal = 0;

  CHECK_PARAM((stateWidth <= 0x7FF));

  tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_CR_RES_WIDTH, stateWidth);
  BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal);

  tmpVal = BL_RD_REG(USB_BASE, USB_RESUME_CONFIG);
  tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_RES_TRIG);
  BL_WR_REG(USB_BASE, USB_RESUME_CONFIG, tmpVal);

  return SUCCESS;
}

uint8_t USB_Get_Current_Packet_PID(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);

  return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_PID);
}

uint8_t USB_Get_Current_Packet_EP(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_FRAME_NO);

  return BL_GET_REG_BITS_VAL(tmpVal, USB_STS_EP_NO);
}

BL_Sts_Type USB_Get_Error_Status(USB_ERROR_Type err) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_ERROR);

  return tmpVal & (1 << err) ? SET : RESET;
}

BL_Err_Type USB_Clr_Error_Status(USB_ERROR_Type err) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
  tmpVal |= (1 << USB_INT_ERROR);
  BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);

  return SUCCESS;
}

BL_Err_Type USB_Clr_RstEndIntStatus(void) {
  uint32_t tmpVal = 0;

  tmpVal = BL_RD_REG(USB_BASE, USB_INT_CLEAR);
  tmpVal |= (1 << 27);
  BL_WR_REG(USB_BASE, USB_INT_CLEAR, tmpVal);

  return SUCCESS;
}

/*@} end of group USB_Public_Functions */

/*@} end of group USB */

/*@} end of group BL70X_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c
================================================
/**
 ******************************************************************************
 * @file    bl702_xip_sflash.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_xip_sflash.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  XIP_SFLASH
 *  @{
 */

/** @defgroup  XIP_SFLASH_Private_Macros
 *  @{
 */

/*@} end of group XIP_SFLASH_Private_Macros */

/** @defgroup  XIP_SFLASH_Private_Types
 *  @{
 */

/*@} end of group XIP_SFLASH_Private_Types */

/** @defgroup  XIP_SFLASH_Private_Variables
 *  @{
 */
static uint8_t aesEnable;

/*@} end of group XIP_SFLASH_Private_Variables */

/** @defgroup  XIP_SFLASH_Global_Variables
 *  @{
 */

/*@} end of group XIP_SFLASH_Global_Variables */

/** @defgroup  XIP_SFLASH_Private_Fun_Declaration
 *  @{
 */

/*@} end of group XIP_SFLASH_Private_Fun_Declaration */

/** @defgroup  XIP_SFLASH_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  XIP SFlash option save
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(void) {
  aesEnable = SF_Ctrl_Is_AES_Enable();

  if (aesEnable) {
    SF_Ctrl_AES_Disable();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  XIP SFlash option restore
                                                                                *
                                                                                * @param  None
                                                                                *
                                                                                * @return None
                                                                                *
                                                                                *******************************************************************************/
void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(void) {
  if (aesEnable) {
    SF_Ctrl_AES_Enable();
  }
}

/****************************************************************************/ /**
                                                                                * @brief  Save flash controller state
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  offset: CPU XIP flash offset pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) {
  /* XIP_SFlash_Delay */
  volatile uint32_t i = 32 * 2;

  while (i--)
    ;

  SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
  /* Exit form continous read for accepting command */
  SFlash_Reset_Continue_Read(pFlashCfg);
  /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
  SFlash_Software_Reset(pFlashCfg);
  /* For disable command that is setting register instaed of send command, we need write enable */
  SFlash_DisableBurstWrap(pFlashCfg);
  /* Enable QE again in case reset command make it reset */
  SFlash_Qspi_Enable(pFlashCfg);
  /* Deburst again to make sure */
  SFlash_DisableBurstWrap(pFlashCfg);

  /* Clear offset setting*/
  *offset = SF_Ctrl_Get_Flash_Image_Offset();
  SF_Ctrl_Set_Flash_Image_Offset(0);

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Restore flash controller state
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  offset: CPU XIP flash offset
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) {
  uint32_t tmp[1];

  SF_Ctrl_Set_Flash_Image_Offset(offset);

  SFlash_SetBurstWrap(pFlashCfg);
  SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
  SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);

  return SUCCESS;
}
#endif

/*@} end of group XIP_SFLASH_Private_Functions */

/** @defgroup  XIP_SFLASH_Public_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  Erase flash one region
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  startaddr: start address to erase
                                                                                * @param  endaddr: end address(include this address) to erase
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    stat = SFlash_Erase(pFlashCfg, startaddr, endaddr);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return stat;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Program flash one region
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  addr: start address to be programed
                                                                                * @param  data: data pointer to be programed
                                                                                * @param  len: data length to be programed
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return stat;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read data from flash
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  addr: flash read start address
                                                                                * @param  data: data pointer to store data read from flash
                                                                                * @param  len: data length to read
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return stat;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get Flash Jedec ID
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  data: data pointer to store Jedec ID Read from flash
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    SFlash_GetJedecId(pFlashCfg, data);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get Flash Device ID
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  data: data pointer to store Device ID Read from flash
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    SFlash_GetDeviceId(data);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Get Flash Unique ID
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  ioMode: flash controller interface mode
                                                                                * @param  data: data pointer to store Device ID Read from flash
                                                                                * @param  idLen: Unique id len
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) {
  BL_Err_Type stat;
  uint32_t    offset;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);

  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    SFlash_GetUniqueId(data, idLen);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return SUCCESS;
}
#endif

/****************************************************************************/ /**
                                                                                * @brief  Read data from flash via XIP
                                                                                *
                                                                                * @param  addr: flash read start address
                                                                                * @param  data: data pointer to store data read from flash
                                                                                * @param  len: data length to read
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) {
  uint32_t offset;

  if (addr >= BL702_FLASH_XIP_BASE && addr < BL702_FLASH_XIP_END) {
    offset = SF_Ctrl_Get_Flash_Image_Offset();
    SF_Ctrl_Set_Flash_Image_Offset(0);
    /* Flash read */
    BL702_MemCpy_Fast(data, (void *)(addr - SF_Ctrl_Get_Flash_Image_Offset()), len);
    SF_Ctrl_Set_Flash_Image_Offset(offset);
  }

  return SUCCESS;
}
#endif

/*@} end of group XIP_SFLASH_Public_Functions */

/*@} end of group XIP_SFLASH */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c
================================================
/**
 ******************************************************************************
 * @file    bl702_xip_sflash_ext.c
 * @version V1.0
 * @date
 * @brief   This file is the standard driver c file
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2020 Bouffalo Lab

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of Bouffalo Lab nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "bl702_xip_sflash_ext.h"
#include "string.h"

/** @addtogroup  BL702_Peripheral_Driver
 *  @{
 */

/** @addtogroup  XIP_SFLASH
 *  @{
 */

/** @defgroup  XIP_SFLASH_EXT_Private_Macros
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Private_Macros */

/** @defgroup  XIP_SFLASH_EXT_Private_Types
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Private_Types */

/** @defgroup  XIP_SFLASH_EXT_Private_Variables
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Private_Variables */

/** @defgroup  XIP_SFLASH_EXT_Global_Variables
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Global_Variables */

/** @defgroup  XIP_SFLASH_EXT_Private_Fun_Declaration
 *  @{
 */

/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */

/** @defgroup  XIP_SFLASH_EXT_Private_Functions
 *  @{
 */

/****************************************************************************/ /**
                                                                                * @brief  XIP KH25V40 flash write protect set
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                * @param  protect: protect area
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Protect_Kh25v40_Type protect) {
  BL_Err_Type     stat;
  uint32_t        offset;
  SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    stat = SFlash_KH25V40_Write_Protect(pFlashCfg, protect);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return stat;
}

/****************************************************************************/ /**
                                                                                * @brief  Clear flash status register need lock
                                                                                *
                                                                                * @param  pFlashCfg: Flash config pointer
                                                                                *
                                                                                * @return SUCCESS or ERROR
                                                                                *
                                                                                *******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg) {
  BL_Err_Type     stat;
  uint32_t        offset;
  SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;

  stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
  if (stat != SUCCESS) {
    SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
  } else {
    stat = SFlash_Clear_Status_Register(pFlashCfg);
    XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
  }

  return stat;
}

/*@} end of group XIP_SFLASH_EXT_Public_Functions */

/*@} end of group XIP_SFLASH_EXT */

/*@} end of group BL702_Peripheral_Driver */


================================================
FILE: source/Core/BSP/Pinecilv2/ble.c
================================================
#include "ble.h"
#include "BSP.h"
#include "bflb_platform.h"
#include "bl702_glb.h"
#include "ble_characteristics.h"
#include "ble_peripheral.h"
#include "bluetooth.h"
#include "conn.h"
#include "gatt.h"
#include "hal_clock.h"
#include "hci_core.h"
#include "log.h"
#include "uuid.h"
#include 
#include 
#include 
#include 
#include 

void ble_stack_start(void) {
  MSG("BLE Starting\n");
  GLB_Set_EM_Sel(GLB_EM_8KB);
  ble_controller_init(configMAX_PRIORITIES - 1);

  // Initialize BLE Host stack
  hci_driver_init();

  bt_enable(bt_enable_cb);
  MSG("BLE Starting...Done\n");
}

/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
application must provide an implementation of vApplicationGetTimerTaskMemory()
to provide the memory that is used by the Timer service task. */
void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
  /* If the buffers to be provided to the Timer task are declared inside this
  function then they must be declared static - otherwise they will be allocated on
  the stack and so not exists after this function exits. */
  static StaticTask_t xTimerTaskTCB;
  static StackType_t  uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];

  /* Pass out a pointer to the StaticTask_t structure in which the Timer
  task's state will be stored. */
  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;

  /* Pass out the array that will be used as the Timer task's stack. */
  *ppxTimerTaskStackBuffer = uxTimerTaskStack;

  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
  Note that, as the array is necessarily of type StackType_t,
  configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}

void vApplicationMallocFailedHook(void) {
  MSG("vApplicationMallocFailedHook\r\n");

  while (1) {
    ;
  }
}

void user_vAssertCalled(void) {

  MSG("user_vAssertCalled\r\n");

  while (1) {
    ;
  }
}


================================================
FILE: source/Core/BSP/Pinecilv2/ble.h
================================================
#ifndef PINECILV2_BLE_H_
#define PINECILV2_BLE_H_

/*
 * BLE Interface for the Pinecil V2
 *
 * Exposes:
 * - Live Measurements
 * - Device Settings Names
 * - Device Settings Values
 */
#ifdef __cplusplus
extern "C" {
#endif

// Spawns the BLE stack tasks and makes the device available to be connected to via BLE.
void ble_stack_start(void);

#ifdef __cplusplus
};
#endif

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/ble_characteristics.h
================================================
#ifndef BLE_CHARACTERISTICS_H_
#define BLE_CHARACTERISTICS_H_

#include "ble_config.h"

/*

 Pinecil exposes two main services; Status and settings

 Status:
 - Current setpoint temperature
 - Current live tip temperature
 - Current DC Input
 - Current Handle cold junction temperature
 - Current power level (aka pwm level)

 Settings:
 - One entry for every setting in the unit
*/

// d85efab4-168e-4a71-affd-33e27f9bc533
#define BT_UUID_SVC_LIVE_DATA BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef000, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
// f6d75f91-5a10-4eba-a233-47d3f26a907f
#define BT_UUID_SVC_SETTINGS_DATA BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d80000, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
// 9eae1adb-9d0d-48c5-a6e7-ae93f0ea37b0
#define BT_UUID_SVC_BULK_DATA BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1000, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))

#define BT_UUID_CHAR_BLE_LIVE_LIVE_TEMP     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef001, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_SETPOINT_TEMP BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef002, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_DC_INPUT      BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef003, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_HANDLE_TEMP   BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef004, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_POWER_LEVEL   BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef005, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_POWER_SRC     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef006, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_TIP_RES       BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef007, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_UPTIME        BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef008, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_MOVEMENT      BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef009, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_MAX_TEMP      BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef00A, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_RAW_TIP       BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef00B, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_HALL_SENSOR   BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef00C, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_OP_MODE       BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef00D, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_EST_WATTS     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xd85ef00E, 0x168e, 0x4a71, 0xAA55, 0x33e27f9bc533))

// Bulk data that returns non-fixed sized objects
#define BT_UUID_CHAR_BLE_LIVE_BULK_LIVE_DATA BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1001, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_ACCEL_NAME     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1002, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_BUILD          BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1003, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_DEV_SN         BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1004, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_LIVE_DEV_ID         BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0x9eae1005, 0x9d0d, 0x48c5, 0xAA55, 0x33e27f9bc533))

// Settings

#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_SAVE  BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7FFFF, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_RESET BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7FFFE, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_0     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70000, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_1     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70001, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_2     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70002, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_3     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70003, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_4     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70004, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_5     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70005, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_6     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70006, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_7     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70007, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_8     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70008, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_9     BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70009, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_10    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000a, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_11    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000b, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_12    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000c, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_13    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000d, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_14    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000e, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_15    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7000f, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_16    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70010, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_17    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70011, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_18    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70012, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_19    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70013, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_20    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70014, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_21    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70015, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_22    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70016, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_23    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70017, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_24    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70018, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_25    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70019, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_26    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001a, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_27    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001b, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_28    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001c, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_29    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001d, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_30    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001e, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_31    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d7001f, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_32    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70020, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_33    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70021, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_34    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70022, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_35    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70023, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_36    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70024, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_37    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70025, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_38    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70026, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_53    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70035, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#define BT_UUID_CHAR_BLE_SETTINGS_VALUE_54    BT_UUID_DECLARE_128(BT_UUID_128_ENCODE(0xf6d70036, 0x5a10, 0x4eba, 0xAA55, 0x33e27f9bc533))
#endif


================================================
FILE: source/Core/BSP/Pinecilv2/ble_handlers.cpp
================================================


#include 
#include 
#include 
#include 
#include 

#include "types.h"

#include "BSP.h"
#include "TipThermoModel.h"
#include "ble_peripheral.h"
#include "bluetooth.h"
#include "configuration.h"
#include "conn.h"
#include "gatt.h"
#include "hal_clock.h"
#include "hci_core.h"
#include "log.h"
#include "uuid.h"

#include "../../version.h"
#include "OLED.hpp"
#include "OperatingModes.h"
#include "USBPD.h"
#include "ble_characteristics.h"
#include "ble_handlers.h"
#include "pd.h"
#include "power.hpp"
#ifdef POW_PD
#include "USBPD.h"
#include "pd.h"
#endif

extern TickType_t    lastMovementTime;
extern OperatingMode currentOperatingMode;

int ble_char_read_status_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  if (attr == NULL || attr->uuid == NULL) {
    return 0;
  }
  // Decode the uuid
  // Byte 12 has the lowest part of the first UUID chunk
  uint16_t uuid_value = ((struct bt_uuid_128 *)attr->uuid)->val[12];
  uint32_t temp       = 0;
  switch (uuid_value) {
  case 1: // Live temp
  {
    temp = TipThermoModel::getTipInC();
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
  } break;
  case 2: // Setpoint temp
    temp = getSettingValue(SettingsOptions::SolderingTemp);
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 3: // DC Input
    temp = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 4: // Handle temp
    temp = getHandleTemperature(0);
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 5: // power level
    // return current PWM level
    temp = X10WattsToPWM(x10WattHistory.average());
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 6: // power src
    // Todo return enum for current power source
    temp = getPowerSrc();
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 7:
    // Tip resistance
    temp = getTipResistanceX10();
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 8:
    // uptime
    temp = xTaskGetTickCount() / TICKS_100MS;
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 9:
    // movement
    temp = lastMovementTime / TICKS_100MS;
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);

    break;
  case 10:
    // max temp
    temp = TipThermoModel::getTipMaxInC();
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 11:
    // raw tip
    temp = TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true);
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 12:
    // hall sensor
    {
      int16_t hallEffectStrength = getRawHallEffect();
      if (hallEffectStrength < 0) {
        hallEffectStrength = -hallEffectStrength;
      }
      temp = hallEffectStrength;
      memcpy(buf, &temp, sizeof(temp));
      return sizeof(temp);
    }
    break;
  case 13:
    // Operating mode
    temp = (uint32_t)currentOperatingMode;
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  case 14:
    // Estimated watts
    temp = x10WattHistory.average();
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
    break;
  default:
    break;
  }
  MSG((char *)"Unhandled attr read %d | %d\n", (uint32_t)attr->uuid, uuid_value);
  return 0;
}

int ble_char_read_bulk_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  if (attr == NULL || attr->uuid == NULL) {
    return 0;
  }
  // Byte 12 has the lowest part of the first UUID chunk
  uint16_t uuid_value = ((struct bt_uuid_128 *)attr->uuid)->val[12];
  // Bulk is the non-const size service
  switch (uuid_value) {
  case 1:
    // Bulk data
    {
      uint32_t bulkData[] = {
          (uint32_t)TipThermoModel::getTipInC(),                               // 0  - Current temp
          getSettingValue(SettingsOptions::SolderingTemp),                     // 1  - Setpoint
          getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0), // 2  - Input voltage
          getHandleTemperature(0),                                             // 3  - Handle X10 Temp in C
          X10WattsToPWM(x10WattHistory.average()),                             // 4  - Power as PWM level
          getPowerSrc(),                                                       // 5  - power src
          getTipResistanceX10(),                                               // 6  - Tip resistance
          xTaskGetTickCount() / TICKS_100MS,                                   // 7  - uptime in deciseconds
          lastMovementTime / TICKS_100MS,                                      // 8  - last movement time (deciseconds)
          (uint32_t)TipThermoModel::getTipMaxInC(),                            // 9  - max temp
          TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true),        // 10 - Raw tip in μV
          (uint32_t)abs(getRawHallEffect()),                                   // 11 - hall sensor
          (uint32_t)currentOperatingMode,                                      // 12 - Operating mode
          x10WattHistory.average(),                                            // 13 - Estimated Wattage *10
      };
      int lenToCopy = sizeof(bulkData) - offset;
      if (lenToCopy > len) {
        lenToCopy = len;
      }
      if (lenToCopy < 0) {
        lenToCopy = 0;
      }
      memcpy(buf, ((uint8_t *)bulkData) + offset, lenToCopy);
      return lenToCopy;
    }

    break;
  case 2:
    // Accelerometer name
    // TODO: Need to store non-encoded version
    break;
  case 3:
    // FW Version
    memcpy(buf, &BUILD_VERSION, sizeof(BUILD_VERSION) - 1);
    return sizeof(BUILD_VERSION) - 1;
  case 4:
    // Device serial number.
    // Serial number is the ID burned by manufacturer.
    // In case of Pinecil V2, device SN = device MAC.
    {
      uint64_t sn = getDeviceID();
      memcpy(buf, &sn, sizeof(sn));
      return sizeof(sn);
    }
    break;
  case 5:
    // Device ID [https://github.com/Ralim/IronOS/issues/1609].
    // ID is a unique key Pine burns at the factory and records in their db.
    {
      uint32_t id = getDeviceValidation();
      memcpy(buf, &id, sizeof(id));
      return sizeof(id);
    }
  default:
    break;
  }
  return 0;
}
int ble_char_read_setting_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset) {
  if (attr == NULL || attr->uuid == NULL) {
    return 0;
  }
  // Byte 12 has the lowest part of the first UUID chunk
  uint16_t uuid_value = ((struct bt_uuid_128 *)attr->uuid)->val[12];
  uint16_t temp       = 0xFFFF;
  if (uuid_value <= SettingsOptions::SettingsOptionsLength) {
    temp = getSettingValue((SettingsOptions)(uuid_value));
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
  } else {
    memcpy(buf, &temp, sizeof(temp));
    return sizeof(temp);
  }

  MSG((char *)"Unhandled attr read %d | %d\n", (uint32_t)attr->uuid, uuid_value);
  return 0;
}

int ble_char_write_setting_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags) {

  if (flags & BT_GATT_WRITE_FLAG_PREPARE) {
    // Don't use prepare write data, execute write will upload data again.
    BT_WARN((char *)"recv prepare write request\n");
    return 0;
  }
  if (attr == NULL || attr->uuid == NULL) {
    return 0;
  }

  if (flags & BT_GATT_WRITE_FLAG_CMD) {
    // Use write command data.
    BT_WARN((char *)"recv write command\n");
  } else {
    // Use write request / execute write data.
    BT_WARN((char *)"recv write request / exce write\n");
  }
  uint8_t uuid_value = ((struct bt_uuid_128 *)attr->uuid)->val[12];
  if (len == 2) {
    uint16_t new_value = 0;
    memcpy(&new_value, buf, sizeof(new_value));
    if (uuid_value == 0xFF) {
      if (new_value == 1) {
        saveSettings();
        return len;
      }
    } else if (uuid_value == 0xFE) {
      if (new_value == 1) {
        resetSettings();
        return len;
      }
    } else if (uuid_value < SettingsOptions::SettingsOptionsLength) {
      setSettingValue((SettingsOptions)(uuid_value), new_value);
      switch (uuid_value) {
      case SettingsOptions::OLEDInversion:
        OLED::setInverseDisplay(getSettingValue(SettingsOptions::OLEDInversion));
        break;
      case SettingsOptions::OLEDBrightness:
        OLED::setBrightness(getSettingValue(SettingsOptions::OLEDBrightness));
        break;
      case SettingsOptions::OrientationMode:
        OLED::setRotation(getSettingValue(SettingsOptions::OrientationMode) & 1);
        break;
      default:
        break;
      }
      return len;
    }
  }
  MSG((char *)"Unhandled attr write %d | %d\n", (uint32_t)attr->uuid, uuid_value);
  return 0;
}

uint32_t getPowerSrc() {
  int sourceNumber = 0;
  if (getIsPoweredByDCIN()) {
    sourceNumber = 0;
  } else {
    // We are not powered via DC, so want to display the appropriate state for PD or QC
    bool poweredbyPD        = false;
    bool pdHasVBUSConnected = false;
#ifdef POW_PD
    if (USBPowerDelivery::fusbPresent()) {
      // We are PD capable
      if (USBPowerDelivery::negotiationComplete()) {
        // We are powered via PD
        poweredbyPD = true;
#ifdef VBUS_MOD_TEST
        pdHasVBUSConnected = USBPowerDelivery::isVBUSConnected();
#endif
      }
    }
#endif
    if (poweredbyPD) {

      if (pdHasVBUSConnected) {
        sourceNumber = 2;
      } else {
        sourceNumber = 3;
      }
    } else {
      sourceNumber = 1;
    }
  }
  return sourceNumber;
}


================================================
FILE: source/Core/BSP/Pinecilv2/ble_handlers.h
================================================
#ifndef BLE_HANDLERS_H_
#define BLE_HANDLERS_H_

#include "conn_internal.h"
#include "types.h"
#ifdef __cplusplus
extern "C" {
#endif

int ble_char_read_status_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset);
int ble_char_read_setting_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset);
int ble_char_read_bulk_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, u16_t len, u16_t offset);

int ble_char_write_setting_value_callback(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, u16_t len, u16_t offset, u8_t flags);

uint32_t getPowerSrc();

#ifdef __cplusplus
};
#endif

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/ble_peripheral.c
================================================
/****************************************************************************
FILE NAME
    ble_peripheral_tp_server.c

DESCRIPTION
    test profile demo

NOTES
*/
/****************************************************************************/

#include 
#include 
#include 
#include 
#include 

#include "types.h"

#include "ble_peripheral.h"
#include "bluetooth.h"
#include "conn.h"
#include "gatt.h"
#include "hal_clock.h"
#include "hci_core.h"
#include "log.h"
#include "uuid.h"

#include "BSP.h"
#include "ble_characteristics.h"
#include "ble_handlers.h"
bool pds_start;

static void          ble_device_connected(struct bt_conn *conn, u8_t err);
static void          ble_device_disconnected(struct bt_conn *conn, u8_t reason);
static void          ble_connection_param_changed(struct bt_conn *conn, u16_t interval, u16_t latency, u16_t timeout);
struct bt_gatt_attr *get_attr(u8_t index);

static struct bt_conn                *ble_tp_conn;
static struct bt_gatt_exchange_params exchg_mtu;
static TaskHandle_t                   ble_tp_task_h;
static int                            tx_mtu_size     = 20;
static u8_t                           created_tp_task = 0;

static struct bt_conn_cb ble_tp_conn_callbacks = {
    .connected        = ble_device_connected,
    .disconnected     = ble_device_disconnected,
    .le_param_updated = ble_connection_param_changed,
};

/*************************************************************************
NAME
    ble_tx_mtu_change_callback
*/
static void ble_tx_mtu_change_callback(struct bt_conn *conn, u8_t err, struct bt_gatt_exchange_params *params) {
  if (!err) {
    tx_mtu_size = bt_gatt_get_mtu(ble_tp_conn);
    BT_WARN("ble tp echange mtu size success, mtu size: %d\n", tx_mtu_size);
  } else {
    BT_WARN("ble tp echange mtu size failure, err: %d\n", err);
  }
}
/*************************************************************************
NAME
    ble_device_connected
*/
static void ble_device_connected(struct bt_conn *conn, u8_t err) {
  int tx_octets = 0x00fb;
  int tx_time   = 0x0848;
  int ret       = -1;

  if (err) {
    return;
  }

  BT_INFO("BLE connected");
  ble_tp_conn = conn;
  pds_start   = false;

  // set data length after connected.
  ret = bt_le_set_data_len(ble_tp_conn, tx_octets, tx_time);

  if (!ret) {
    BT_INFO("ble tp set data length success\n");
  } else {
    BT_WARN("ble tp set data length failure, err: %d\n", ret);
  }

  // exchange mtu size after connected.
  exchg_mtu.func = ble_tx_mtu_change_callback;
  ret            = bt_gatt_exchange_mtu(ble_tp_conn, &exchg_mtu);

  if (!ret) {
    BT_INFO("ble tp exchange mtu size pending\n");
  } else {
    BT_WARN("ble tp exchange mtu size failure, err: %d\n", ret);
  }
}

/*************************************************************************
NAME
    ble_device_disconnected
*/
static void ble_device_disconnected(struct bt_conn *conn, u8_t reason) {
  BT_WARN("Tp disconnected");

  if (created_tp_task) {
    BT_WARN("Delete throughput tx task\n");
    vTaskDelete(ble_tp_task_h);
    created_tp_task = 0;
  }

  ble_tp_conn = NULL;
  extern int ble_start_adv(void);
  ble_start_adv();
  pds_start = true;
}

/*************************************************************************
NAME
    ble_connection_param_changed
*/

static void ble_connection_param_changed(struct bt_conn *conn, u16_t interval, u16_t latency, u16_t timeout) {
  BT_INFO("LE conn param updated: int 0x%04x lat %d to %d \r\n", interval, latency, timeout);
}

/*************************************************************************
NAME
    ble_tp_ind_ccc_changed
*/
static void ble_tp_ind_ccc_changed(const struct bt_gatt_attr *attr, u16_t value) {
  int  err     = -1;
  char data[9] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09};

  if (value == BT_GATT_CCC_INDICATE) {
    err = bl_tp_send_indicate(ble_tp_conn, get_attr(BT_CHAR_BLE_TP_IND_ATTR_VAL_INDEX), data, 9);
    BT_WARN("ble tp send indicate: %d\n", err);
  }
}

/*************************************************************************
 *  DEFINE : attrs
 */
static struct bt_gatt_attr ble_attrs_declaration[] = {
    BT_GATT_PRIMARY_SERVICE(BT_UUID_SVC_LIVE_DATA),

    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_LIVE_TEMP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_SETPOINT_TEMP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_DC_INPUT, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_HANDLE_TEMP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_POWER_LEVEL, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_POWER_SRC, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_TIP_RES, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_UPTIME, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_MOVEMENT, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_MAX_TEMP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_RAW_TIP, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_HALL_SENSOR, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_OP_MODE, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_EST_WATTS, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_status_callback, NULL, NULL),

    BT_GATT_PRIMARY_SERVICE(BT_UUID_SVC_BULK_DATA),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_BULK_LIVE_DATA, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_bulk_value_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_ACCEL_NAME, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_bulk_value_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_BUILD, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_bulk_value_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_DEV_SN, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_bulk_value_callback, NULL, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_LIVE_DEV_ID, BT_GATT_CHRC_READ, BT_GATT_PERM_READ, ble_char_read_bulk_value_callback, NULL, NULL),

    BT_GATT_PRIMARY_SERVICE(BT_UUID_SVC_SETTINGS_DATA),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_0, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_1, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_2, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_3, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_4, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_5, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_6, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_7, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_8, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_9, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_10, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_11, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_12, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_13, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_14, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_15, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_16, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_17, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_18, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_19, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_20, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_21, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_22, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_23, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_24, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_25, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_26, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_27, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_28, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_29, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_30, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_31, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_32, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_33, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_34, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_35, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_36, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_37, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_38, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_53, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_54, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),

    /* Save & reset */
    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_SAVE, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),

    BT_GATT_CHARACTERISTIC(BT_UUID_CHAR_BLE_SETTINGS_VALUE_RESET, BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE,
                           ble_char_read_setting_value_callback, ble_char_write_setting_value_callback, NULL),

};

/*************************************************************************
NAME
    get_attr
*/
struct bt_gatt_attr *get_attr(u8_t index) { return &ble_attrs_declaration[index]; }

static struct bt_gatt_service ble_tp_server = BT_GATT_SERVICE(ble_attrs_declaration);

// Start advertising with expected default values
int ble_start_adv(void) {
  MSG("BLE Starting advertising\n");
  struct bt_le_adv_param adv_param = {
      // options:3, connectable undirected, adv one time
      .options      = 3,
      .interval_min = BT_GAP_ADV_FAST_INT_MIN_3,
      .interval_max = BT_GAP_ADV_FAST_INT_MAX_3,
  };
  char     nameBuffer[16];
  uint32_t scratch = getDeviceID() & 0xFFFFFFFF;
  scratch ^= (getDeviceID() >> 32) & 0xFFFFFFFF;
  int nameLen = snprintf(nameBuffer, 16, "Pinecil-%08X", (int)scratch);

  // scan and response data must each stay < 31 bytes
  struct bt_data adv_data[2] = {BT_DATA_BYTES(BT_DATA_FLAGS, (BT_LE_AD_NO_BREDR | BT_LE_AD_GENERAL)), BT_DATA(BT_DATA_NAME_COMPLETE, nameBuffer, nameLen)};

  struct bt_data scan_response_data[1] = {BT_DATA(BT_DATA_UUID128_SOME, ((struct bt_uuid_128 *)BT_UUID_SVC_BULK_DATA)->val, 16)};

  return bt_le_adv_start(&adv_param, adv_data, ARRAY_SIZE(adv_data), scan_response_data, ARRAY_SIZE(scan_response_data));
}

// Callback that the ble stack will call once it has been kicked off running
// We use this to register the handlers (as we know its now ready for them) + start advertising to the world
void bt_enable_cb(int err) {
  bt_conn_cb_register(&ble_tp_conn_callbacks);
  bt_gatt_service_register(&ble_tp_server);

  ble_start_adv();
}


================================================
FILE: source/Core/BSP/Pinecilv2/ble_peripheral.h
================================================
/****************************************************************************
FILE NAME
    ble_peripheral_tp_server.h

DESCRIPTION
NOTES
*/
/****************************************************************************/

#ifndef _BLE_TP_SVC_H_
#define _BLE_TP_SVC_H_

#include 
#include "ble_config.h"

// read value handle offset 2
#define BT_CHAR_BLE_TP_RD_ATTR_VAL_INDEX (2)
// write value handle offset 4
#define BT_CHAR_BLE_TP_WR_ATTR_VAL_INDEX (4)
// indicate value handle offset 6
#define BT_CHAR_BLE_TP_IND_ATTR_VAL_INDEX (6)
// notity value handle offset 9
#define BT_CHAR_BLE_TP_NOT_ATTR_VAL_INDEX (9)
#ifdef __cplusplus
extern "C" {
#endif

void                 ble_tp_init();
void                 bt_enable_cb(int err);
struct bt_gatt_attr *get_attr(u8_t index);

#ifdef __cplusplus
};
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/board.c
================================================
/**
 * @file board.c
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#include "bflb_platform.h"
#include "bl702_config.h"
#include "bl702_glb.h"
#include "hal_gpio.h"

struct pin_mux_cfg {
  uint8_t  pin;
  uint16_t func;
};

static const struct pin_mux_cfg af_pin_table[] = {
#ifdef CONFIG_GPIO0_FUNC
    { .pin = GPIO_PIN_0,  .func = CONFIG_GPIO0_FUNC},
#endif
#ifdef CONFIG_GPIO1_FUNC
    { .pin = GPIO_PIN_1,  .func = CONFIG_GPIO1_FUNC},
#endif
#ifdef CONFIG_GPIO2_FUNC
    { .pin = GPIO_PIN_2,  .func = CONFIG_GPIO2_FUNC},
#endif
#ifdef CONFIG_GPIO3_FUNC
    { .pin = GPIO_PIN_3,  .func = CONFIG_GPIO3_FUNC},
#endif
#ifdef CONFIG_GPIO4_FUNC
    { .pin = GPIO_PIN_4,  .func = CONFIG_GPIO4_FUNC},
#endif
#ifdef CONFIG_GPIO5_FUNC
    { .pin = GPIO_PIN_5,  .func = CONFIG_GPIO5_FUNC},
#endif
#ifdef CONFIG_GPIO6_FUNC
    { .pin = GPIO_PIN_6,  .func = CONFIG_GPIO6_FUNC},
#endif
#ifdef CONFIG_GPIO7_FUNC
    { .pin = GPIO_PIN_7,  .func = CONFIG_GPIO7_FUNC},
#endif
#ifdef CONFIG_GPIO8_FUNC
    { .pin = GPIO_PIN_8,  .func = CONFIG_GPIO8_FUNC},
#endif
#ifdef CONFIG_GPIO9_FUNC
    { .pin = GPIO_PIN_9,  .func = CONFIG_GPIO9_FUNC},
#endif
#ifdef CONFIG_GPIO10_FUNC
    {.pin = GPIO_PIN_10, .func = CONFIG_GPIO10_FUNC},
#endif
#ifdef CONFIG_GPIO11_FUNC
    {.pin = GPIO_PIN_11, .func = CONFIG_GPIO11_FUNC},
#endif
#ifdef CONFIG_GPIO12_FUNC
    {.pin = GPIO_PIN_12, .func = CONFIG_GPIO12_FUNC},
#endif
#ifdef CONFIG_GPIO13_FUNC
    {.pin = GPIO_PIN_13, .func = CONFIG_GPIO13_FUNC},
#endif
#ifdef CONFIG_GPIO14_FUNC
    {.pin = GPIO_PIN_14, .func = CONFIG_GPIO14_FUNC},
#endif
#ifdef CONFIG_GPIO15_FUNC
    {.pin = GPIO_PIN_15, .func = CONFIG_GPIO15_FUNC},
#endif
#ifdef CONFIG_GPIO16_FUNC
    {.pin = GPIO_PIN_16, .func = CONFIG_GPIO16_FUNC},
#endif
#ifdef CONFIG_GPIO17_FUNC
    {.pin = GPIO_PIN_17, .func = CONFIG_GPIO17_FUNC},
#endif
#ifdef CONFIG_GPIO18_FUNC
    {.pin = GPIO_PIN_18, .func = CONFIG_GPIO18_FUNC},
#endif
#ifdef CONFIG_GPIO19_FUNC
    {.pin = GPIO_PIN_19, .func = CONFIG_GPIO19_FUNC},
#endif
#ifdef CONFIG_GPIO20_FUNC
    {.pin = GPIO_PIN_20, .func = CONFIG_GPIO20_FUNC},
#endif
#ifdef CONFIG_GPIO21_FUNC
    {.pin = GPIO_PIN_21, .func = CONFIG_GPIO21_FUNC},
#endif
#ifdef CONFIG_GPIO22_FUNC
    {.pin = GPIO_PIN_22, .func = CONFIG_GPIO22_FUNC},
#endif
#ifdef CONFIG_GPIO23_FUNC
    {.pin = GPIO_PIN_23, .func = CONFIG_GPIO23_FUNC},
#endif
#ifdef CONFIG_GPIO24_FUNC
    {.pin = GPIO_PIN_24, .func = CONFIG_GPIO24_FUNC},
#endif
#ifdef CONFIG_GPIO25_FUNC
    {.pin = GPIO_PIN_25, .func = CONFIG_GPIO25_FUNC},
#endif
#ifdef CONFIG_GPIO26_FUNC
    {.pin = GPIO_PIN_26, .func = CONFIG_GPIO26_FUNC},
#endif
#ifdef CONFIG_GPIO27_FUNC
    {.pin = GPIO_PIN_27, .func = CONFIG_GPIO27_FUNC},
#endif
#ifdef CONFIG_GPIO28_FUNC
    {.pin = GPIO_PIN_28, .func = CONFIG_GPIO28_FUNC},
#endif
#ifdef CONFIG_GPIO29_FUNC
    {.pin = GPIO_PIN_29, .func = CONFIG_GPIO29_FUNC},
#endif
#ifdef CONFIG_GPIO30_FUNC
    {.pin = GPIO_PIN_30, .func = CONFIG_GPIO30_FUNC},
#endif
#ifdef CONFIG_GPIO31_FUNC
    {.pin = GPIO_PIN_31, .func = CONFIG_GPIO31_FUNC},
#endif
};

static void board_pin_mux_init(void) {
  GLB_GPIO_Cfg_Type gpio_cfg;
  uint32_t          tmpVal;
  gpio_cfg.drive        = 2;
  gpio_cfg.smtCtrl      = 1;
  uint8_t hbn_gpio_mask = 0x1f;
  uint8_t hbn_aon_ie    = 0;

  for (uint32_t i = 0; i < sizeof(af_pin_table) / sizeof(af_pin_table[0]); i++) {
    gpio_cfg.gpioMode = GPIO_MODE_AF;
    gpio_cfg.pullType = GPIO_PULL_UP;
    gpio_cfg.gpioPin  = af_pin_table[i].pin;
    gpio_cfg.gpioFun  = af_pin_table[i].func;

    /*if using gpio9-gpio12 and func is not analog and output ,should set reg_aon_pad_ie_smt corresponding bit = 1*/
    if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
      if ((af_pin_table[i].func != 10) && ((af_pin_table[i].func < GPIO_FUN_GPIO_OUTPUT_UP) || (af_pin_table[i].func > GPIO_FUN_GPIO_OUTPUT_NONE))) {
        hbn_aon_ie |= (1 << (af_pin_table[i].pin - 9));
      }
    }

    /*if reset state*/
    if (af_pin_table[i].func == GPIO_FUN_UNUSED) {
      continue;
    } else if (af_pin_table[i].func == GPIO_FUN_WAKEUP) {
      /*if hbn or pds gpio wakeup func*/
      if (af_pin_table[i].pin < GPIO_PIN_8) {
        /*enable pds gpio wakeup and irq unmask*/
        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, af_pin_table[i].pin);
        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
        BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
      } else if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
        hbn_gpio_mask &= ~(1 << (af_pin_table[i].pin - 9));
      }
      continue;
    } else if ((af_pin_table[i].func == GPIO_FUN_USB) || (af_pin_table[i].func == GPIO_FUN_DAC) || (af_pin_table[i].func == GPIO_FUN_ADC)) {
      /*if analog func , for usb、adc、dac*/
      gpio_cfg.gpioFun  = GPIO_FUN_ANALOG;
      gpio_cfg.gpioMode = GPIO_MODE_ANALOG;
      gpio_cfg.pullType = GPIO_PULL_NONE;
    } else if ((af_pin_table[i].func & 0xF0) == 0xF0) {
      /*if uart func*/
      gpio_cfg.gpioFun  = GPIO_FUN_UART;
      uint8_t uart_func = af_pin_table[i].func & 0x07;
      uint8_t uart_sig  = gpio_cfg.gpioPin % 8;
      /*link to one uart sig*/
      GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func);
      GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig);
    } else if (af_pin_table[i].func == GPIO_FUN_PWM) {
      /*if pwm func*/
      gpio_cfg.pullType = GPIO_PULL_DOWN;
    } else if (af_pin_table[i].func == GPIO_FUN_QDEC) {
      /* if qdec a/b */
      gpio_cfg.pullType = GPIO_PULL_NONE;
      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
      gpio_cfg.gpioFun  = GPIO_FUN_QDEC;
    } else if (af_pin_table[i].func == GPIO_FUN_QDEC_LED) {
      /* if qdec led */
      gpio_cfg.pullType = GPIO_PULL_NONE;
      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
      gpio_cfg.gpioFun  = GPIO_FUN_QDEC;
    } else if (af_pin_table[i].func == GPIO_FUN_CLK_OUT) {
      if (af_pin_table[i].pin % 2) {
        /*odd gpio output clock*/
        GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
      } else {
        /*even gpio output clock*/
        GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
      }
    } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_UP) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL)) {
      /*if common gpio func,include input、output and exti*/
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
      gpio_cfg.pullType = GPIO_PULL_UP;

      if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) {
        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
      } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL) {
        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
      }
    } else if ((af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_DOWN) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) || (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL)) {
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
      gpio_cfg.pullType = GPIO_PULL_DOWN;

      if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) {
        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
      } else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL) {
        GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
      }
    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_INPUT_NONE) {
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_INPUT;
      gpio_cfg.pullType = GPIO_PULL_NONE;
    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_UP) {
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
      gpio_cfg.pullType = GPIO_PULL_UP;
    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_DOWN) {
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
      gpio_cfg.pullType = GPIO_PULL_DOWN;
    } else if (af_pin_table[i].func == GPIO_FUN_GPIO_OUTPUT_NONE) {
      gpio_cfg.gpioFun  = GPIO_FUN_GPIO;
      gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
      gpio_cfg.pullType = GPIO_PULL_NONE;
    }
    GLB_GPIO_Init(&gpio_cfg);
  }

  /*disable unused reg_aon_pad_ie_smt bits and hbn_pin_wakeup_mask bits*/
  tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, hbn_gpio_mask);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, hbn_aon_ie);
  tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
  BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}

static void board_clock_init(void) {
  system_clock_init();
  peripheral_clock_init();
}

void board_init(void) {
  board_clock_init();
  board_pin_mux_init();
}

================================================
FILE: source/Core/BSP/Pinecilv2/clock_config.h
================================================
/**
 * @file clock_config.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#ifndef _CLOCK_CONFIG_H
#define _CLOCK_CONFIG_H

#define XTAL_TYPE                  EXTERNAL_XTAL_32M
#define XTAL_32K_TYPE              INTERNAL_RC_32K
#define BSP_ROOT_CLOCK_SOURCE      ROOT_CLOCK_SOURCE_PLL_144M
#define BSP_AUDIO_PLL_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ

#define BSP_FCLK_DIV 0
#define BSP_BCLK_DIV 1

#define BSP_UART_CLOCK_SOURCE   ROOT_CLOCK_SOURCE_PLL_96M
#define BSP_UART_CLOCK_DIV      0
#define BSP_I2C_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_BCLK
#define BSP_I2C_CLOCK_DIV       0
#define BSP_SPI_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_BCLK
#define BSP_SPI_CLOCK_DIV       0
#define BSP_TIMER0_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
#define BSP_TIMER0_CLOCK_DIV    22
#define BSP_TIMER1_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK
#define BSP_TIMER1_CLOCK_DIV    31
#define BSP_WDT_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_32K_CLK
#define BSP_WDT_CLOCK_DIV       32
#define BSP_PWM_CLOCK_SOURCE    ROOT_CLOCK_SOURCE_XCLK
#define BSP_PWM_CLOCK_DIV       22
#define BSP_IR_CLOCK_SOURCE     ROOT_CLOCK_SOURCE_XCLK
#define BSP_IR_CLOCK_DIV        0

#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
#define BSP_ADC_CLOCK_DIV    16

#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ
#define BSP_DAC_CLOCK_DIV    2

#define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M
#define BSP_CAM_CLOCK_DIV    3

#define BSP_QDEC_KEYSCAN_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
#define BSP_QDEC_KEYSCAN_CLOCK_DIV    31

#endif

================================================
FILE: source/Core/BSP/Pinecilv2/configuration.h
================================================
#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
#include 
/**
 * Configuration.h
 * Define here your default pre settings for Pinecilv2
 *
 */

//===========================================================================
//============================= Default Settings ============================
//===========================================================================
/**
 * Default soldering temp is 320.0 C
 * Temperature the iron sleeps at - default 150.0 C
 */

#define SLEEP_TEMP         150 // Default sleep temperature
#define BOOST_TEMP         420 // Default boost temp.
#define BOOST_MODE_ENABLED 1   // 0: Disable 1: Enable

/**
 * Blink the temperature on the cooling screen when its > 50C
 */
#define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable

/**
 * How many seconds/minutes we wait until going to sleep/shutdown.
 * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds!
 */
#define SLEEP_TIME    5  // x10 Seconds
#define SHUTDOWN_TIME 10 // Minutes

/**
 * Auto start off for safety.
 * Pissible values are:
 *  0 - none
 *  1 - Soldering Temperature
 *  2 - Sleep Temperature
 *  3 - Sleep Off Temperature
 */
#define AUTO_START_MODE 0 // Default to none

/**
 * Locking Mode
 * When in soldering mode a long press on both keys toggle the lock of the buttons
 * Possible values are:
 *  0 - Desactivated
 *  1 - Lock except boost
 *  2 - Full lock
 */
#define LOCKING_MODE 0 // Default to desactivated for safety

/**
 * OLED Orientation
 *
 */
#define ORIENTATION_MODE           2 // 0: Right 1:Left 2:Automatic - Default Automatic
#define MAX_ORIENTATION_MODE       2 // Up to auto
#define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change

/**
 * OLED Brightness
 *
 */
#define MIN_BRIGHTNESS     1   // Min OLED brightness selectable
#define MAX_BRIGHTNESS     101 // Max OLED brightness selectable
#define BRIGHTNESS_STEP    25  // OLED brightness increment
#define DEFAULT_BRIGHTNESS 26  // default OLED brightness

/**
 * Temp change settings
 */
#define TEMP_CHANGE_SHORT_STEP     1  // Default temp change short step +1
#define TEMP_CHANGE_LONG_STEP      10 // Default temp change long step +10
#define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value
#define TEMP_CHANGE_LONG_STEP_MAX  90 // Temp change long step MAX value

/* Power pulse for keeping power banks awake*/

#define POWER_PULSE_INCREMENT    1
#define POWER_PULSE_MAX          100 // x10 max watts
#define POWER_PULSE_WAIT_MAX     9   // 9*2.5s = 22.5 seconds
#define POWER_PULSE_DURATION_MAX 9   // 9*250ms = 2.25 seconds

#ifdef MODEL_Pinecilv2
#define POWER_PULSE_DEFAULT 0
#else
#define POWER_PULSE_DEFAULT 5
#endif                                 /* Pinecil */
#define POWER_PULSE_WAIT_DEFAULT     4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s
#define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms

/**
 * OLED Orientation Sensitivity on Automatic mode!
 * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive>
 */
#define SENSITIVITY 7 // Default 7

/**
 * Detailed soldering screen
 * Detailed idle screen (off for first time users)
 */
#define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0
#define DETAILED_IDLE      0 // 0: Disable 1: Enable - Default 0

#define THERMAL_RUNAWAY_TIME_SEC 20
#define THERMAL_RUNAWAY_TEMP_C   3

#define CUT_OUT_SETTING          0  // default to no cut-off voltage
#define RECOM_VOL_CELL           33 // Minimum voltage per cell (Recommended 3.3V (33))
#define TEMPERATURE_INF          0  // default to 0
#define DESCRIPTION_SCROLL_SPEED 0  // 0: Slow 1: Fast - default to slow
#define ANIMATION_LOOP           1  // 0: off 1: on
#define ANIMATION_SPEED          settingOffSpeed_t::MEDIUM

#define OP_AMP_Rf_Pinecil  680 * 1000 // 680  Kilo-ohms -> From schematic, R1
#define OP_AMP_Rin_Pinecil 2370       // 2.37 Kilo-ohms -> From schematic, R2

#define OP_AMP_GAIN_STAGE_PINECIL (1 + (OP_AMP_Rf_Pinecil / OP_AMP_Rin_Pinecil))

#if defined(MODEL_Pinecilv2) == 0
#error "No model defined!"
#endif

#ifdef MODEL_Pinecilv2
#define ADC_VDD_MV                 3200                      // ADC max reading millivolts
#define ADC_MAX_READING            ((1 << 16) >> 1)          // Maximum reading of the adc
#define SOLDERING_TEMP             320                       // Default soldering temp is 320.0 °C
#define VOLTAGE_DIV                630                       // 600 - Default divider from schematic
#define CALIBRATION_OFFSET         900                       // 900 - Default adc offset in uV
#define MIN_CALIBRATION_OFFSET     100                       // Min value for calibration
#define PID_POWER_LIMIT            120                       // Sets the max pwm power limit
#define POWER_LIMIT                0                         // 0 watts default limit
#define MAX_POWER_LIMIT            120                       // Sets the max power limit
#define POWER_LIMIT_STEPS          5                         //
#define OP_AMP_GAIN_STAGE          OP_AMP_GAIN_STAGE_PINECIL // Uses TS100 resistors
#define TEMP_uV_LOOKUP_HAKKO                                 // Use Hakko lookup table
#define USB_PD_VMAX                28                        // Maximum voltage for PD to negotiate
#define PID_TIM_HZ                 (10)                      // Tick rate of the PID loop
#define MAX_TEMP_C                 450                       // Max soldering temp selectable °C
#define MAX_TEMP_F                 850                       // Max soldering temp selectable °F
#define MIN_TEMP_C                 10                        // Min soldering temp selectable °C
#define MIN_TEMP_F                 50                        // Min soldering temp selectable °F
#define MIN_BOOST_TEMP_C           250                       // The min settable temp for boost mode °C
#define MIN_BOOST_TEMP_F           480                       // The min settable temp for boost mode °F
#define DEVICE_HAS_VALIDATION_CODE                           // We have 2 digit validations
#define POW_PD                     1                         // Supported features
#define USB_PD_EPR_WATTAGE         140                       // USB PD EPR Wattage
#define POW_PD_EXT                 0                         // Future-proof macro for other models with other PD modes
#define POW_QC                     1                         // Supported features
#define POW_DC                     1                         // Supported features
#define POW_QC_20V                 1                         // Supported features
#define POW_EPR                    1
#define ENABLE_QC2                 1
#define MAG_SLEEP_SUPPORT          1
#define TIP_TYPE_SUPPORT           1 // Support for tips of different types, i.e. resistance
#define AUTO_TIP_SELECTION         1 // Can auto-select the tip
#define TIPTYPE_T12                1 // Can manually pick a T12 tip
#define DEVICE_HAS_VALIDATION_SUPPORT
#define OLED_96x16 1
#define TEMP_NTC
#define ACCEL_BMA
#define ACCEL_SC7
#define HALL_SENSOR
#define HALL_SI7210
#define DEBUG_UART_OUTPUT
#define HAS_POWER_DEBUG_MENU
#define HARDWARE_MAX_WATTAGE_X10  750
#define BLE_ENABLED                   // We have a BLE stack
#define NEEDS_VBUS_PROBE          0   // No vbus probe, its not connected in pcb
#define CANT_DIRECT_READ_SETTINGS     // We cant memcpy settings due to flash cache
#define TIP_CONTROL_PID               // We use PID rather than integrator
#define TIP_PID_KP                40  // Reasonable compromise for most tips so far
#define TIP_PID_KI                6   // About as high for stability across tips
#define TIP_PID_KD                200 // Helps dampen smaller tips; ~= nothing for larger tips
#define FILTER_DISPLAYED_TIP_TEMP 8   // Filtering for GUI display

#endif /* Pinecilv2 */

#define FLASH_PAGE_SIZE (1024) // Read pages
// Erase is 4 or 8 k size, so we pad these apart for now
// If we ever get low on flash, will need better solution
#define FLASH_LOGOADDR      (0x23000000 + (1016 * FLASH_PAGE_SIZE))
#define SETTINGS_START_PAGE (1023 * FLASH_PAGE_SIZE) // Hal auto offsets base addr

#endif /* CONFIGURATION_H_ */


================================================
FILE: source/Core/BSP/Pinecilv2/crc32.h
================================================
#pragma once

#include 

#define DEFAULT_POLY 0x973afb51

template  struct CRC32Table {
  constexpr CRC32Table() : table() {
    for (uint32_t i = 0; i < 256; i++) {
      uint32_t c = i;
      for (auto j = 0; j < 8; j++) {
        if (c & 1) {
          c = polynomial ^ (c >> 1);
        } else {
          c >>= 1;
        }
      }
      table[i] = c;
    }
  }
  uint32_t table[256];
  uint32_t computeCRC32(uint32_t initial, const uint8_t *buf, int len) {
    uint32_t c = initial ^ 0xFFFFFFFF;
    for (auto i = 0; i < len; ++i) {
      c = table[(c ^ buf[i]) & 0xFF] ^ (c >> 8);
    }
    return c ^ 0xFFFFFFFF;
  }
};


================================================
FILE: source/Core/BSP/Pinecilv2/flash.c
================================================
/*
 * flash.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BSP.h"
#include "BSP_Flash.h"
#include "hal_flash.h"
#include "string.h"

void flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
  BL_Err_Type err = flash_erase(SETTINGS_START_PAGE, FLASH_PAGE_SIZE);
  err             = flash_write(SETTINGS_START_PAGE, buffer, length);
}

void flash_read_buffer(uint8_t *buffer, const uint16_t length) { flash_read(SETTINGS_START_PAGE, buffer, length); }


================================================
FILE: source/Core/BSP/Pinecilv2/fusb_user.cpp
================================================
#include "configuration.h"
#ifdef POW_PD
#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "Setup.h"

/*
 * Read multiple bytes from the FUSB302B
 *
 * cfg: The FUSB302B to communicate with
 * addr: The memory address from which to read
 * size: The number of bytes to read
 * buf: The buffer into which data will be read
 */
bool fusb_read_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Read(deviceAddr, registerAdd, buf, size); }

/*
 * Write multiple bytes to the FUSB302B
 *
 * cfg: The FUSB302B to communicate with
 * addr: The memory address to which we will write
 * size: The number of bytes to write
 * buf: The buffer to write
 */
bool fusb_write_buf(const uint8_t deviceAddr, const uint8_t registerAdd, const uint8_t size, uint8_t *buf) { return FRToSI2C::Mem_Write(deviceAddr, registerAdd, (uint8_t *)buf, size); }

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/peripheral_config.h
================================================
/**
 * @file peripheral_config.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */

#ifndef _PERIPHERAL_CONFIG_H_
#define _PERIPHERAL_CONFIG_H_

/* PERIPHERAL USING LIST */
#define BSP_USING_ADC0
// #define BSP_USING_DAC0
#define BSP_USING_UART0
// #define BSP_USING_UART1
// #define BSP_USING_SPI0
#define BSP_USING_I2C0
// #define BSP_USING_I2S0
// #define BSP_USING_PWM_CH0
#define BSP_USING_PWM_CH1
// #define BSP_USING_PWM_CH2
// #define BSP_USING_PWM_CH3
// #define BSP_USING_PWM_CH4
#define BSP_USING_TIMER0
#define BSP_USING_TIMER1
#define BSP_USING_WDT
// #define BSP_USING_KEYSCAN
// #define BSP_USING_QDEC0
// #define BSP_USING_QDEC1
// #define BSP_USING_QDEC2
// #define BSP_USING_USB
/* ----------------------*/

/* PERIPHERAL With DMA LIST */

#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
#define BSP_USING_DMA0_CH3
#define BSP_USING_DMA0_CH4
#define BSP_USING_DMA0_CH5
#define BSP_USING_DMA0_CH6
#define BSP_USING_DMA0_CH7

/* PERIPHERAL CONFIG */
#if defined(BSP_USING_ADC0)
#ifndef ADC0_CONFIG
#define ADC0_CONFIG                                                                                                                                                      \
  {                                                                                                                                                                      \
    .clk_div = ADC_CLOCK_DIV_32, .vref = ADC_VREF_3V2, .continuous_conv_mode = DISABLE, .differential_mode = DISABLE, .data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
    .fifo_threshold = ADC_FIFO_THRESHOLD_8BYTE, .gain = ADC_GAIN_1                                                                                                       \
  }
#endif
#endif

#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
  { .channels = DAC_CHANNEL_0, .sample_freq = DAC_SAMPLE_FREQ_500KHZ, .vref = DAC_VREF_INTERNAL, }
#endif
#endif

#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
  { .id = 0, .baudrate = 2000000, .databits = UART_DATA_LEN_8, .stopbits = UART_STOP_ONE, .parity = UART_PAR_NONE, .fifo_threshold = 0, }
#endif
#endif

#if defined(BSP_USING_PWM_CH0)
#ifndef PWM_CH0_CONFIG
#define PWM_CH0_CONFIG \
  { .ch = 0, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
#endif
#endif

#if defined(BSP_USING_PWM_CH1)
#ifndef PWM_CH1_CONFIG
#define PWM_CH1_CONFIG \
  { .ch = 1, .polarity_invert_mode = DISABLE, .period = 100, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
#endif
#endif

#if defined(BSP_USING_PWM_CH2)
#ifndef PWM_CH2_CONFIG
#define PWM_CH2_CONFIG \
  { .ch = 2, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
#endif
#endif

#if defined(BSP_USING_PWM_CH3)
#ifndef PWM_CH3_CONFIG
#define PWM_CH3_CONFIG \
  { .ch = 3, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
#endif
#endif

#if defined(BSP_USING_PWM_CH4)
#ifndef PWM_CH4_CONFIG
#define PWM_CH4_CONFIG \
  { .ch = 4, .polarity_invert_mode = DISABLE, .period = 0, .threshold_low = 0, .threshold_high = 0, .it_pulse_count = 0, }
#endif
#endif

#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG                                                                                                                                                                            \
  {                                                                                                                                                                                                \
    .id = 0, .ch = 0, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG                                                                                                                                                                            \
  {                                                                                                                                                                                                \
    .id = 0, .ch = 1, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_4, .dst_burst_size = DMA_BURST_SIZE_4, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT, \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG                                                                                                                                                                               \
  {                                                                                                                                                                                                   \
    .id = 0, .ch = 2, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_UART1_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,     \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG                                                                                                                                                                              \
  {                                                                                                                                                                                                  \
    .id = 0, .ch = 3, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_SPI0_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,    \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG                                                                                                                                                                               \
  {                                                                                                                                                                                                   \
    .id = 0, .ch = 4, .direction = DMA_PERIPH_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_SPI0_RX, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_8BIT, .dst_width = DMA_TRANSFER_WIDTH_8BIT,      \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG                                                                                                                                                                              \
  {                                                                                                                                                                                                  \
    .id = 0, .ch = 5, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT,  \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG                                                                                                                                                                              \
  {                                                                                                                                                                                                  \
    .id = 0, .ch = 6, .direction = DMA_MEMORY_TO_PERIPH, .transfer_mode = DMA_LLI_CYCLE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_I2S_TX, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
    .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_16BIT, .dst_width = DMA_TRANSFER_WIDTH_16BIT,  \
  }
#endif
#endif

#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG                                                                                                                                                                            \
  {                                                                                                                                                                                                \
    .id = 0, .ch = 7, .direction = DMA_MEMORY_TO_MEMORY, .transfer_mode = DMA_LLI_ONCE_MODE, .src_req = DMA_REQUEST_NONE, .dst_req = DMA_REQUEST_NONE, .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,  \
    .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, .src_burst_size = DMA_BURST_SIZE_1, .dst_burst_size = DMA_BURST_SIZE_1, .src_width = DMA_TRANSFER_WIDTH_32BIT, .dst_width = DMA_TRANSFER_WIDTH_32BIT, \
  }
#endif
#endif

#if defined(BSP_USING_I2C0)
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \
  { .id = 0, .mode = I2C_HW_MODE, .phase = 15, }
#endif
#endif

#if defined(BSP_USING_TIMER0)
#ifndef TIMER0_CONFIG
#define TIMER0_CONFIG \
  { .id = 0, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP2, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
#endif
#endif

#if defined(BSP_USING_TIMER1)
#ifndef TIMER1_CONFIG
#define TIMER1_CONFIG \
  { .id = 1, .cnt_mode = TIMER_CNT_PRELOAD, .trigger = TIMER_PRELOAD_TRIGGER_COMP0, .reload = 0, .timeout1 = 1000000, .timeout2 = 2000000, .timeout3 = 3000000, }
#endif
#endif

#if defined(BSP_USING_WDT)
#ifndef WDT_CONFIG
#define WDT_CONFIG \
  { .id = 0, .wdt_timeout = 6000, }
#endif
#endif

#if defined(BSP_USING_KEYSCAN)
#ifndef KEYSCAN_CONFIG
#define KEYSCAN_CONFIG \
  { .col_num = COL_NUM_4, .row_num = ROW_NUM_4, .deglitch_count = 0, }
#endif
#endif

#if defined(BSP_USING_QDEC0)
#ifndef QDEC0_CONFIG
#define QDEC0_CONFIG                                                                                                                                                                                 \
  {                                                                                                                                                                                                  \
    .id = 0, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
  }
#endif
#endif

#if defined(BSP_USING_QDEC1)
#ifndef QDEC1_CONFIG
#define QDEC1_CONFIG                                                                                                                                                                                 \
  {                                                                                                                                                                                                  \
    .id = 1, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
  }
#endif
#endif

#if defined(BSP_USING_QDEC2)
#ifndef QDEC2_CONFIG
#define QDEC2_CONFIG                                                                                                                                                                                 \
  {                                                                                                                                                                                                  \
    .id = 2, .acc_mode = QDEC_ACC_CONTINUE_ACCUMULATE, .sample_mode = QDEC_SAMPLE_SINGLE_MOD, .sample_period = QDEC_SAMPLE_PERIOD_256US, .report_mode = QDEC_REPORT_TIME_MOD, .report_period = 2000, \
    .led_en = ENABLE, .led_swap = DISABLE, .led_period = 7, .deglitch_en = DISABLE, .deglitch_strength = 0x0,                                                                                        \
  }
#endif
#endif

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/pinmux_config.h
================================================
/**
 * @file pinmux_config.h
 * @brief
 *
 * Copyright (c) 2021 Bouffalolab team
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 */
#ifndef _PINMUX_CONFIG_H
#define _PINMUX_CONFIG_H

//  GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio0 function
#define CONFIG_GPIO0_FUNC GPIO_FUN_E21_JTAG

//  GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio1 function
#define CONFIG_GPIO1_FUNC GPIO_FUN_E21_JTAG

//  GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio2 function
#define CONFIG_GPIO2_FUNC GPIO_FUN_E21_JTAG

//  GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio3 function
#define CONFIG_GPIO3_FUNC GPIO_FUN_GPIO_OUTPUT_NONE

//  GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio4 function
#define CONFIG_GPIO4_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio5 function
#define CONFIG_GPIO5_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio6 function
#define CONFIG_GPIO6_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio7 function
#define CONFIG_GPIO7_FUNC GPIO_FUN_USB

//  GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio8 function
#define CONFIG_GPIO8_FUNC GPIO_FUN_USB

//  GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio9 function
#define CONFIG_GPIO9_FUNC GPIO_FUN_E21_JTAG

//  GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio10 function
#define CONFIG_GPIO10_FUNC GPIO_FUN_I2C

//  GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio11 function
#define CONFIG_GPIO11_FUNC GPIO_FUN_I2C

//  GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio12 function
#define CONFIG_GPIO12_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio13 function
#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED

//  GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio14 function
#define CONFIG_GPIO14_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio15 function
#define CONFIG_GPIO15_FUNC GPIO_FUN_SPI

//  GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio16 function
#define CONFIG_GPIO16_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL

//  GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio17 function
#define CONFIG_GPIO17_FUNC GPIO_FUN_ADC

//  GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio18 function
#define CONFIG_GPIO18_FUNC GPIO_FUN_ADC

//  GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio19 function
#define CONFIG_GPIO19_FUNC GPIO_FUN_ADC

//  GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio20 function
#define CONFIG_GPIO20_FUNC GPIO_FUN_ADC

//  GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio21 function
#define CONFIG_GPIO21_FUNC GPIO21_FUN_PWM_CH1

//  GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio22 function
#define CONFIG_GPIO22_FUNC GPIO_FUN_UART0_TX

//  GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio23 function
#define CONFIG_GPIO23_FUNC GPIO_FUN_UART0_RX

//  GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio24 function
#define CONFIG_GPIO24_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio25 function
#define CONFIG_GPIO25_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio26 function
#define CONFIG_GPIO26_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio27 function
#define CONFIG_GPIO27_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio28 function
#define CONFIG_GPIO28_FUNC GPIO_FUN_GPIO_INPUT_NONE

//  GPIO29 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio29 function
#define CONFIG_GPIO29_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL

//  GPIO30 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio30 function
#define CONFIG_GPIO30_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL

//  GPIO31 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio31 function
#define CONFIG_GPIO31_FUNC GPIO_FUN_GPIO_EXTI_LOW_LEVEL

//  GPIO32 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio32 function
#define CONFIG_GPIO32_FUNC GPIO_FUN_UNUSED

//  GPIO33 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio33 function
#define CONFIG_GPIO33_FUNC GPIO_FUN_UNUSED

//  GPIO34 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio34 function
#define CONFIG_GPIO34_FUNC GPIO_FUN_UNUSED

//  GPIO35 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio35 function
#define CONFIG_GPIO35_FUNC GPIO_FUN_UNUSED

//  GPIO36 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio36 function
#define CONFIG_GPIO36_FUNC GPIO_FUN_UNUSED

//  GPIO37 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_USB//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
//  config gpio37 function
#define CONFIG_GPIO37_FUNC GPIO_FUN_UNUSED

#endif


================================================
FILE: source/Core/BSP/Pinecilv2/postRTOS.cpp
================================================
#include "BSP.h"
#include "FreeRTOS.h"
#include "I2C_Wrapper.hpp"
#include "QC3.h"
#include "Settings.h"
#include "Si7210.h"
#include "ble.h"
#include "cmsis_os.h"
#include "main.hpp"
#include "power.hpp"
#include "stdlib.h"
#include "task.h"
bool hall_effect_present = false;

void postRToSInit() {
  // Any after RTos setup
#ifdef HALL_SI7210
  if (Si7210::detect()) {
    hall_effect_present = Si7210::init();
  }
#endif

  if (getSettingValue(SettingsOptions::BluetoothLE)) {
    ble_stack_start();
  }
}
int16_t getRawHallEffect() {
  if (hall_effect_present) {
    return Si7210::read();
  }
  return 0;
}

bool getHallSensorFitted() { return hall_effect_present; }


================================================
FILE: source/Core/BSP/Pinecilv2/preRTOS.cpp
================================================
/*
 * preRTOS.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BSP.h"
#include "Pins.h"
#include "Setup.h"
#include "bflb_platform.h"
#include "hal_gpio.h"
#include 

void preRToSInit() {
  // Normal system bringup -- GPIO etc
  bflb_platform_init(0);

  hardware_init();
  gpio_write(OLED_RESET_Pin, 0);
  delay_ms(10);
  gpio_write(OLED_RESET_Pin, 1);
  BSPInit();
  FRToSI2C::FRToSInit();
}


================================================
FILE: source/Core/BSP/Sequre/BSP.cpp
================================================
// BSP mapping functions

#include "BSP.h"
#include "BootLogo.h"
#include "FS2711.hpp"
#include "HUB238.hpp"
#include "I2C_Wrapper.hpp"
#include "Pins.h"
#include "Settings.h"
#include "Setup.h"
#include "TipThermoModel.h"
#include "configuration.h"
#include "history.hpp"
#include "main.hpp"
#include 

volatile uint16_t    PWMSafetyTimer   = 0;
volatile uint8_t     pendingPWM       = 0;
const uint16_t       powerPWM         = 255;
static const uint8_t holdoffTicks     = 15; // delay of 8 ish ms
static const uint8_t tempMeasureTicks = 15;

uint16_t totalPWM = powerPWM + tempMeasureTicks + holdoffTicks; // htim2.Init.Period, the full PWM cycle

void resetWatchdog() { HAL_IWDG_Refresh(&hiwdg); }
// Lookup table for the NTC
// We dont know exact specs, but it loooks to be roughly a 10K B=4000 NTC
// Stored as ADCReading,Temp in degC
static const uint16_t NTCHandleLookup[] = {
    // ADC Reading , Temp in C
    23931, 0,  //
    23210, 2,  //
    22466, 4,  //
    21703, 6,  //
    20924, 8,  //
    20135, 10, //
    19338, 12, //
    18538, 14, //
    17738, 16, //
    16943, 18, //
    16156, 20, //
    15381, 22, //
    14621, 24, //
    13878, 26, //
    13155, 28, //
    12455, 30, //
    11778, 32, //
    11126, 34, //
    10501, 36, //
    9902,  38, //
    9330,  40, //
    8786,  42, //
    8269,  44, //
};

uint16_t getHandleTemperature(uint8_t sample) {
#ifdef TMP36_ADC1_CHANNEL
  int32_t result = getADCHandleTemp(sample);
  // S60 uses 10k NTC resistor
  // For now not doing interpolation
  for (uint32_t i = 0; i < (sizeof(NTCHandleLookup) / (2 * sizeof(uint16_t))); i++) {
    if (result > NTCHandleLookup[(i * 2) + 0]) {
      return NTCHandleLookup[(i * 2) + 1] * 10;
    }
  }
  return 45 * 10;
#else
  return 0; // Not implemented
#endif
}

uint16_t getInputVoltageX10(uint16_t divisor, uint8_t sample) {
  // ADC maximum is 32767 == 3.3V at input == 28.05V at VIN
  // Therefore we can divide down from there
  // Multiplying ADC max by 4 for additional calibration options,
  // ideal term is 467
  uint32_t res = getADCVin(sample);
  res *= 4;
  res /= divisor;
  return res;
}

static void switchToFastPWM(void) {
  // 20Hz
  totalPWM             = powerPWM + tempMeasureTicks + holdoffTicks;
  htim2.Instance->ARR  = totalPWM;
  htim2.Instance->CCR1 = powerPWM + holdoffTicks;
  htim2.Instance->CCR4 = powerPWM;
  htim2.Instance->PSC  = 1500;
}

void setTipPWM(const uint8_t pulse, const bool shouldUseFastModePWM) {
  PWMSafetyTimer = 20; // This is decremented in the handler for PWM so that the tip pwm is
                       // disabled if the PID task is not scheduled often enough.
  pendingPWM = pulse;
}
// These are called by the HAL after the corresponding events from the system
// timers.

void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
  // Period has elapsed
  if (htim->Instance == TIM2) {
    // we want to turn on the output again
    PWMSafetyTimer--;
    // We decrement this safety value so that lockups in the
    // scheduler will not cause the PWM to become locked in an
    // active driving state.
    // While we could assume this could never happen, its a small price for
    // increased safety
    if (PWMSafetyTimer == 0) {
      htim4.Instance->CCR3 = 0;
    } else {
      htim4.Instance->CCR3 = pendingPWM / 4;
    }
  } else if (htim->Instance == TIM1) {
    // STM uses this for internal functions as a counter for timeouts
    HAL_IncTick();
  }
}

void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
  // This was a when the PWM for the output has timed out
  if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) {
    // HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3);
    htim4.Instance->CCR3 = 0;
  }
}

void unstick_I2C() {
#ifdef SCL_Pin
  GPIO_InitTypeDef GPIO_InitStruct;
  int              timeout     = 100;
  int              timeout_cnt = 0;

  // 1. Clear PE bit.
  hi2c1.Instance->CR1 &= ~(0x0001);
  /**I2C1 GPIO Configuration
   PB6     ------> I2C1_SCL
   PB7     ------> I2C1_SDA
   */
  //  2. Configure the SCL and SDA I/Os as General Purpose Output Open-Drain, High level (Write 1 to GPIOx_ODR).
  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;

  GPIO_InitStruct.Pin = SCL_Pin;
  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);

  GPIO_InitStruct.Pin = SDA_Pin;
  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);

  while (GPIO_PIN_SET != HAL_GPIO_ReadPin(SDA_GPIO_Port, SDA_Pin)) {
    // Move clock to release I2C
    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET);
    asm("nop");
    asm("nop");
    asm("nop");
    asm("nop");
    HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);

    timeout_cnt++;
    if (timeout_cnt > timeout) {
      return;
    }
  }

  // 12. Configure the SCL and SDA I/Os as Alternate function Open-Drain.
  GPIO_InitStruct.Mode  = GPIO_MODE_AF_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;

  GPIO_InitStruct.Pin = SCL_Pin;
  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);

  GPIO_InitStruct.Pin = SDA_Pin;
  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);

  HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
  HAL_GPIO_WritePin(SDA_GPIO_Port, SDA_Pin, GPIO_PIN_SET);

  // 13. Set SWRST bit in I2Cx_CR1 register.
  hi2c1.Instance->CR1 |= 0x8000;

  asm("nop");

  // 14. Clear SWRST bit in I2Cx_CR1 register.
  hi2c1.Instance->CR1 &= ~0x8000;

  asm("nop");

  // 15. Enable the I2C peripheral by setting the PE bit in I2Cx_CR1 register
  hi2c1.Instance->CR1 |= 0x0001;

  // Call initialization function.
  HAL_I2C_Init(&hi2c1);
#endif
}

uint8_t getButtonA() { return HAL_GPIO_ReadPin(KEY_A_GPIO_Port, KEY_A_Pin) == GPIO_PIN_RESET ? 1 : 0; }
uint8_t getButtonB() { return HAL_GPIO_ReadPin(KEY_B_GPIO_Port, KEY_B_Pin) == GPIO_PIN_RESET ? 1 : 0; }

void BSPInit(void) { switchToFastPWM(); }

void reboot() { NVIC_SystemReset(); }

void delay_ms(uint16_t count) { HAL_Delay(count); }

bool isTipDisconnected() {

  uint16_t tipDisconnectedThres = TipThermoModel::getTipMaxInC() - 5;
  uint32_t tipTemp              = TipThermoModel::getTipInC();
  return tipTemp > tipDisconnectedThres;
}

void    setStatusLED(const enum StatusLED state) {}
uint8_t preStartChecks() {
#if POW_PD_EXT == 1
  if (!hub238_has_run_selection() && (xTaskGetTickCount() < TICKS_SECOND * 5)) {
    return 0;
  }
  // We check if we are in a "Limited" mode; where we have to run the PWM really fast
  // Where as if we are on 9V for example, the tip resistance is enough
  uint16_t voltage     = hub238_source_voltage();
  uint16_t currentx100 = hub238_source_currentX100();
#endif
#if POW_PD_EXT == 2
  if (!FS2711::has_run_selection() && (xTaskGetTickCount() < TICKS_SECOND * 5)) {
    return 0;
  }
  uint16_t voltage     = FS2711::source_voltage();
  uint16_t currentx100 = FS2711::source_currentx100();
#endif

  uint16_t thresholdResistancex10 = ((voltage * 1000) / currentx100) + 5;

  if (getTipResistanceX10() <= thresholdResistancex10) {
    // We are limited by resistance, not our current limiting, we can slow down PWM to avoid audible noise
    htim4.Instance->PSC = 50; // 10 -> 500 removes audible noise
  }

  return 1; // We are done now
}
uint64_t getDeviceID() {
  //
  return HAL_GetUIDw0() | ((uint64_t)HAL_GetUIDw1() << 32);
}

uint8_t getTipResistanceX10() {
#ifdef COPPER_HEATER_COIL

  // TODO
  //! Warning, must never return 0.
  TemperatureType_t measuredTemperature = TipThermoModel::getTipInC(false);
  if (measuredTemperature < 25) {
    return 50; // Start assuming under spec to soft-start
  }

  // Assuming a temperature rise of 0.00393 per deg c over 20C

  uint32_t scaler = 393 * (measuredTemperature - 20);

  return TIP_RESISTANCE + ((TIP_RESISTANCE * scaler) / 100000);
#else
  uint8_t user_selected_tip = getUserSelectedTipResistance();
  if (user_selected_tip == 0) {
    return TIP_RESISTANCE; // Auto mode
  }
  return user_selected_tip;
#endif
}
bool    isTipShorted() { return false; }
uint8_t preStartChecksDone() { return 1; }

uint16_t getTipThermalMass() { return TIP_THERMAL_MASS; }
uint16_t getTipInertia() { return TIP_THERMAL_INERTIA; }

void setBuzzer(bool on) {}

void showBootLogo(void) { BootLogo::handleShowingLogo((uint8_t *)FLASH_LOGOADDR); }

#ifdef CUSTOM_MAX_TEMP_C
TemperatureType_t getCustomTipMaxInC() { return MAX_TEMP_C; }
#endif


================================================
FILE: source/Core/BSP/Sequre/FreeRTOSConfig.h
================================================
/*
 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
 All rights reserved

 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

 This file is part of the FreeRTOS distribution.

 FreeRTOS is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License (version 2) as published by the
 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.

 ***************************************************************************
 >>!   NOTE: The modification to the GPL is included to allow you to     !<<
 >>!   distribute a combined work that includes FreeRTOS without being   !<<
 >>!   obliged to provide the source code for proprietary components     !<<
 >>!   outside of the FreeRTOS kernel.                                   !<<
 ***************************************************************************

 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
 FOR A PARTICULAR PURPOSE.  Full license text is available on the following
 link: http://www.freertos.org/a00114.html

 ***************************************************************************
 *                                                                       *
 *    FreeRTOS provides completely free yet professionally developed,    *
 *    robust, strictly quality controlled, supported, and cross          *
 *    platform software that is more than just the market leader, it     *
 *    is the industry's de facto standard.                               *
 *                                                                       *
 *    Help yourself get started quickly while simultaneously helping     *
 *    to support the FreeRTOS project by purchasing a FreeRTOS           *
 *    tutorial book, reference manual, or both:                          *
 *    http://www.FreeRTOS.org/Documentation                              *
 *                                                                       *
 ***************************************************************************

 http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
 the FAQ page "My application does not run, what could be wrong?".  Have you
 defined configASSERT()?

 http://www.FreeRTOS.org/support - In return for receiving this top quality
 embedded software for free we request you assist our global community by
 participating in the support forum.

 http://www.FreeRTOS.org/training - Investing in training allows your team to
 be as productive as possible as early as possible.  Now you can receive
 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
 Ltd, and the world's leading authority on the world's leading RTOS.

 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
 compatible FAT file system, and our tiny thread aware UDP/IP stack.

 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.

 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
 Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
 licenses offer ticketed support, indemnification and commercial middleware.

 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
 engineered and independently SIL3 certified version for use in safety and
 mission critical applications that require provable dependability.

 1 tab == 4 spaces!
 */

#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H

/*-----------------------------------------------------------
 * Application specific definitions.
 *
 * These definitions should be adjusted for your particular hardware and
 * application requirements.
 *
 * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
 * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
 *
 * See http://www.freertos.org/a00110.html.
 *----------------------------------------------------------*/

/* USER CODE BEGIN Includes */
#ifdef __cplusplus
extern "C" {
#endif
/* USER CODE END Includes */

/* Ensure stdint is only used by the compiler, and not the assembler. */
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include 
extern uint32_t SystemCoreClock;
#endif

#define configUSE_PREEMPTION                    1
#define configSUPPORT_STATIC_ALLOCATION         1
#define configSUPPORT_DYNAMIC_ALLOCATION        0
#define configUSE_IDLE_HOOK                     1
#define configUSE_TICK_HOOK                     0
#define configCPU_CLOCK_HZ                      (SystemCoreClock)
#define configTICK_RATE_HZ                      (1000)
#define configMAX_PRIORITIES                    (7)
#define configMINIMAL_STACK_SIZE                ((uint16_t)256)
#define configTOTAL_HEAP_SIZE                   ((size_t)1024 * 14) /*Currently use about 9000*/
#define configMAX_TASK_NAME_LEN                 (32)
#define configUSE_MUTEXES                       1
#define configQUEUE_REGISTRY_SIZE               8
#define configUSE_TIMERS                        0
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configCHECK_FOR_STACK_OVERFLOW          2 /*Bump this to 2 during development and bug hunting*/
#define configTICK_TYPE_WIDTH_IN_BITS           TICK_TYPE_WIDTH_32_BITS

/* Co-routine definitions. */
#define configUSE_CO_ROUTINES           0
#define configMAX_CO_ROUTINE_PRIORITIES (2)

/* Set the following definitions to 1 to include the API function, or zero
 to exclude the API function. */
#define INCLUDE_vTaskPrioritySet            1
#define INCLUDE_uxTaskPriorityGet           0
#define INCLUDE_vTaskDelete                 0
#define INCLUDE_vTaskCleanUpResources       0
#define INCLUDE_vTaskSuspend                0
#define INCLUDE_vTaskDelayUntil             1
#define INCLUDE_vTaskDelay                  1
#define INCLUDE_xTaskGetSchedulerState      1
#define INCLUDE_uxTaskGetStackHighWaterMark 1

/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4
#endif

/* The lowest interrupt priority that can be used in a call to a "set priority"
 function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15

/* The highest interrupt priority that can be used by any interrupt service
 routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
 INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
 PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5

/* Interrupt priorities used by the kernel port layer itself.  These are generic
 to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))

/* Normal assert() semantics without relying on the provision of an assert.h
 header file. */
/* USER CODE BEGIN 1 */
#define configASSERT(x)                                                                                                                                                                                \
  if ((x) == 0) {                                                                                                                                                                                      \
    taskDISABLE_INTERRUPTS();                                                                                                                                                                          \
    for (;;)                                                                                                                                                                                           \
      ;                                                                                                                                                                                                \
  }
/* USER CODE END 1 */

/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
 standard names. */
#define vPortSVCHandler    SVC_Handler
#define xPortPendSVHandler PendSV_Handler

#if configUSE_TIMERS
#define configTIMER_TASK_PRIORITY    2
#define configTIMER_QUEUE_LENGTH     8
#define configTIMER_TASK_STACK_DEPTH (512 / 4)
#endif
#ifdef __cplusplus
}
#endif
#endif /* FREERTOS_CONFIG_H */


================================================
FILE: source/Core/BSP/Sequre/IRQ.cpp
================================================
/*
 * IRQ.c
 *
 *  Created on: 30 May 2020
 *      Author: Ralim
 */

#include "IRQ.h"
#include "Pins.h"
#include "configuration.h"

/*
 * Catch the IRQ that says that the conversion is done on the temperature
 * readings coming in Once these have come in we can unblock the PID so that it
 * runs again
 */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
  if (hadc == &hadc1) {
    if (pidTaskNotification) {
      vTaskNotifyGiveFromISR(pidTaskNotification, &xHigherPriorityTaskWoken);
      portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
    }
  }
}

extern osThreadId POWTaskHandle;

void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
  (void)GPIO_Pin;
  // Notify POW thread that an irq occured
  if (POWTaskHandle != nullptr) {
    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
    xTaskNotifyFromISR(POWTaskHandle, 1, eSetBits, &xHigherPriorityTaskWoken);
    /* Force a context switch if xHigherPriorityTaskWoken is now set to pdTRUE.
    The macro used to do this is dependent on the port and may be called
    portEND_SWITCHING_ISR. */
    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
  }
}

// No FUSB302 support
bool getFUS302IRQLow() { return false; }

================================================
FILE: source/Core/BSP/Sequre/IRQ.h
================================================
/*
 * Irqs.h
 *
 *  Created on: 30 May 2020
 *      Author: Ralim
 */

#ifndef BSP_MINIWARE_IRQ_H_
#define BSP_MINIWARE_IRQ_H_

#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "Setup.h"
#include "main.hpp"
#include "stm32f1xx_hal.h"

#ifdef __cplusplus
extern "C" {
#endif
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_GPIO_EXTI_Callback(uint16_t);

#ifdef __cplusplus
}
#endif
#endif /* BSP_MINIWARE_IRQ_H_ */


================================================
FILE: source/Core/BSP/Sequre/Pins.h
================================================
/*
 * Pins.h
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#ifndef BSP_MINIWARE_PINS_H_
#define BSP_MINIWARE_PINS_H_
#include "configuration.h"

#ifdef MODEL_S60

#define KEY_B_Pin             GPIO_PIN_1
#define KEY_B_GPIO_Port       GPIOB
#define TMP36_INPUT_Pin       GPIO_PIN_5
#define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC1_CHANNEL    ADC_CHANNEL_5
#define TMP36_ADC2_CHANNEL    ADC_CHANNEL_5
#define TIP_TEMP_Pin          GPIO_PIN_0
#define TIP_TEMP_GPIO_Port    GPIOA
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_0
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_0
#define VIN_Pin               GPIO_PIN_4
#define VIN_GPIO_Port         GPIOA
#define VIN_ADC1_CHANNEL      ADC_CHANNEL_4
#define VIN_ADC2_CHANNEL      ADC_CHANNEL_4
#define KEY_A_Pin             GPIO_PIN_0
#define KEY_A_GPIO_Port       GPIOB
#define PWM_Out_Pin           GPIO_PIN_8
#define PWM_Out_GPIO_Port     GPIOB
#define PWM_Out_CHANNEL       TIM_CHANNEL_3 // Timer 4; channel 3
#define SCL2_Pin              GPIO_PIN_6
#define SCL2_GPIO_Port        GPIOB
#define SDA2_Pin              GPIO_PIN_7
#define SDA2_GPIO_Port        GPIOB
// Pin gets pulled high on movement
#define MOVEMENT_Pin       GPIO_PIN_3
#define MOVEMENT_GPIO_Port GPIOA

#endif

#ifdef MODEL_S60P

#define KEY_B_Pin             GPIO_PIN_1
#define KEY_B_GPIO_Port       GPIOB
#define TMP36_INPUT_Pin       GPIO_PIN_5
#define TMP36_INPUT_GPIO_Port GPIOA
#define TMP36_ADC1_CHANNEL    ADC_CHANNEL_5
#define TMP36_ADC2_CHANNEL    ADC_CHANNEL_5
#define TIP_TEMP_Pin          GPIO_PIN_0
#define TIP_TEMP_GPIO_Port    GPIOA
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_0
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_0
#define VIN_Pin               GPIO_PIN_4
#define VIN_GPIO_Port         GPIOA
#define VIN_ADC1_CHANNEL      ADC_CHANNEL_4
#define VIN_ADC2_CHANNEL      ADC_CHANNEL_4
#define KEY_A_Pin             GPIO_PIN_0
#define KEY_A_GPIO_Port       GPIOB
#define PWM_Out_Pin           GPIO_PIN_8
#define PWM_Out_GPIO_Port     GPIOB
#define PWM_Out_CHANNEL       TIM_CHANNEL_3 // Timer 4; channel 3
#define SCL2_Pin              GPIO_PIN_6
#define SCL2_GPIO_Port        GPIOB
#define SDA2_Pin              GPIO_PIN_7
#define SDA2_GPIO_Port        GPIOB
// Pin gets pulled high on movement
#define MOVEMENT_Pin       GPIO_PIN_3
#define MOVEMENT_GPIO_Port GPIOA

#endif // MODEL_S60P

#ifdef MODEL_T55

#define KEY_A_Pin       GPIO_PIN_1
#define KEY_A_GPIO_Port GPIOB
// No cold junction compensation as its a PT1000
#define TIP_TEMP_Pin          GPIO_PIN_5
#define TIP_TEMP_GPIO_Port    GPIOA
#define TIP_TEMP_ADC1_CHANNEL ADC_CHANNEL_5
#define TIP_TEMP_ADC2_CHANNEL ADC_CHANNEL_5

#define VIN_Pin          GPIO_PIN_4
#define VIN_GPIO_Port    GPIOA
#define VIN_ADC1_CHANNEL ADC_CHANNEL_4
#define VIN_ADC2_CHANNEL ADC_CHANNEL_4
#define KEY_B_Pin        GPIO_PIN_0
#define KEY_B_GPIO_Port  GPIOB

#define PWM_Out_Pin       GPIO_PIN_8
#define PWM_Out_GPIO_Port GPIOB
#define PWM_Out_CHANNEL   TIM_CHANNEL_3 // Timer 4; channel 3
#define SCL2_Pin          GPIO_PIN_6
#define SCL2_GPIO_Port    GPIOB
#define SDA2_Pin          GPIO_PIN_7
#define SDA2_GPIO_Port    GPIOB

#endif // MODEL_T55

#endif /* BSP_MINIWARE_PINS_H_ */


================================================
FILE: source/Core/BSP/Sequre/Power.cpp
================================================
#include "BSP.h"
#include "BSP_Power.h"
#include "Pins.h"
#include "QC3.h"
#include "Settings.h"
#include "USBPD.h"
#include "configuration.h"

void power_check() {
#ifdef POW_PD
  // Cant start QC until either PD works or fails
  if (!USBPowerDelivery::negotiationComplete()) {
    return;
  }
  if (USBPowerDelivery::negotiationHasWorked()) {
    return; // We are using PD
  }
#endif
#ifdef POW_QC
  QC_resync();
#endif
}

bool getIsPoweredByDCIN() { return false; }


================================================
FILE: source/Core/BSP/Sequre/README.md
================================================
# BSP section for STM32F103 based Miniware products

This folder contains the hardware abstractions required for the TS100, TS80 and probably TS80P soldering irons.

## Main abstractions

* Hardware Init
* -> Should contain all bootstrap to bring the hardware up to an operating point
* -> Two functions are required, a pre and post FreeRToS call
* I2C read/write
* Set PWM for the tip
* Links between IRQ's on the system and the calls in the rest of the firmware


================================================
FILE: source/Core/BSP/Sequre/Setup.cpp
================================================
/*
 * Setup.c
 *
 *  Created on: 29Aug.,2017
 *      Author: Ben V. Brown
 */
#include "Setup.h"
#include "BSP.h"
#include "Pins.h"
#include "history.hpp"
#include 
#include 
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
DMA_HandleTypeDef hdma_adc1;

IWDG_HandleTypeDef hiwdg;
TIM_HandleTypeDef  htim4; // Tip control
TIM_HandleTypeDef  htim2; // ADC Scheduling
#define ADC_FILTER_LEN 4
#define ADC_SAMPLES    16
uint16_t ADCReadings[ADC_SAMPLES]; // Used to store the adc readings for the handle cold junction temp

// Functions
static void SystemClock_Config(void);
static void MX_ADC1_Init(void);
static void MX_IWDG_Init(void);
static void MX_TIM4_Init(void); // Tip control
static void MX_TIM2_Init(void); // ADC Scheduling
static void MX_DMA_Init(void);
static void MX_GPIO_Init(void);
static void MX_ADC2_Init(void);
void        Setup_HAL() {
  __HAL_RCC_I2C1_CLK_DISABLE();
  __HAL_RCC_GPIOD_CLK_DISABLE();
  __HAL_RCC_GPIOA_CLK_DISABLE();
  __HAL_RCC_GPIOB_CLK_DISABLE();
  SystemClock_Config();

  // These are not shared so no harm enabling
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
  MX_GPIO_Init();
  MX_DMA_Init();
  MX_ADC1_Init();
  MX_ADC2_Init();

  MX_TIM4_Init();
  MX_TIM2_Init();
  MX_IWDG_Init();
  HAL_ADC_Start_DMA(&hadc1, (uint32_t *)ADCReadings, (ADC_SAMPLES)); // start DMA of normal readings
  HAL_ADCEx_InjectedStart(&hadc1);                                   // enable injected readings
  HAL_ADCEx_InjectedStart(&hadc2);                                   // enable injected readings

// Setup movement pin
#ifdef MOVEMENT_Pin
  {
    GPIO_InitTypeDef GPIO_InitStruct;
    GPIO_InitStruct.Pin   = MOVEMENT_Pin;
    GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
    GPIO_InitStruct.Pull  = GPIO_PULLDOWN;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
    HAL_GPIO_Init(MOVEMENT_GPIO_Port, &GPIO_InitStruct);
  }
#endif
}

uint16_t getADCHandleTemp(uint8_t sample) {
#ifdef TMP36_ADC1_CHANNEL
  static history filter = {{0}, 0, 0};
  if (sample) {
    uint32_t sum = 0;
    for (uint8_t i = 0; i < ADC_SAMPLES; i++) {
      sum += ADCReadings[i];
    }
    filter.update(sum);
  }
  return filter.average() >> 1;
#else
  return 0;
#endif
}

uint16_t getADCVin(uint8_t sample) {
  static history filter = {{0}, 0, 0};
  if (sample) {
    uint16_t latestADC = 0;

    latestADC += hadc2.Instance->JDR1;
    latestADC += hadc2.Instance->JDR2;
    latestADC += hadc2.Instance->JDR3;
    latestADC += hadc2.Instance->JDR4;
    latestADC <<= 3;
    filter.update(latestADC);
  }
  return filter.average();
}
// Returns either average or instant value. When sample is set the samples from the injected ADC are copied to the filter and then the raw reading is returned
uint16_t getTipRawTemp(uint8_t sample) {
  static history filter = {{0}, 0, 0};
  if (sample) {
    uint16_t latestADC = 0;

    latestADC += hadc1.Instance->JDR1;
    latestADC += hadc1.Instance->JDR2;
    latestADC += hadc1.Instance->JDR3;
    latestADC += hadc1.Instance->JDR4;
    latestADC <<= 1;
    filter.update(latestADC);
    return latestADC;
  }
  return filter.average();
}
/** System Clock Configuration
 */
void SystemClock_Config(void) {
  RCC_OscInitTypeDef       RCC_OscInitStruct;
  RCC_ClkInitTypeDef       RCC_ClkInitStruct;
  RCC_PeriphCLKInitTypeDef PeriphClkInit;

  /**Initializes the CPU, AHB and APB busses clocks
   */
  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI;
  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
  RCC_OscInitStruct.HSICalibrationValue = 16;
  RCC_OscInitStruct.LSIState            = RCC_LSI_ON;
  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64MHz
  HAL_RCC_OscConfig(&RCC_OscInitStruct);

  /**Initializes the CPU, AHB and APB busses clocks
   */
  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16; // TIM
                                                     // 2,3,4,5,6,7,12,13,14
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  // 64 mhz to some peripherals and adc

  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);

  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection    = RCC_ADCPCLK2_DIV6; // 6 or 8 are the only non overclocked options
  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

  /**Configure the Systick interrupt time
   */
  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);

  /**Configure the Systick
   */
  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);

  /* SysTick_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}

/* ADC1 init function */
static void MX_ADC1_Init(void) {

  ADC_ChannelConfTypeDef   sConfig;
  ADC_InjectionConfTypeDef sConfigInjected;
  /**Common config
   */
  hadc1.Instance                   = ADC1;
  hadc1.Init.ScanConvMode          = ADC_SCAN_ENABLE;
  hadc1.Init.ContinuousConvMode    = ENABLE;
  hadc1.Init.DiscontinuousConvMode = DISABLE;
  hadc1.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
  hadc1.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
  hadc1.Init.NbrOfConversion       = 1;
  HAL_ADC_Init(&hadc1);

/**Configure Regular Channel
 */
#ifdef TMP36_ADC1_CHANNEL
  sConfig.Channel      = TMP36_ADC1_CHANNEL;
  sConfig.Rank         = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
#else
  sConfig.Channel      = VIN_ADC1_CHANNEL; // Filler
  sConfig.Rank         = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
  HAL_ADC_ConfigChannel(&hadc1, &sConfig);
#endif
  /**Configure Injected Channel
   */
  // F in = 10.66 MHz
  /*
   * Injected time is 1 delay clock + (12 adc cycles*4)+4*sampletime =~217
   * clocks = 0.2ms Charge time is 0.016 uS ideally So Sampling time must be >=
   * 0.016uS 1/10.66MHz is 0.09uS, so 1 CLK is *should* be enough
   * */
  sConfigInjected.InjectedChannel               = TIP_TEMP_ADC1_CHANNEL;
  sConfigInjected.InjectedRank                  = 1;
  sConfigInjected.InjectedNbrOfConversion       = 4;
  sConfigInjected.InjectedSamplingTime          = ADC_SAMPLETIME_28CYCLES_5;
  sConfigInjected.ExternalTrigInjecConv         = ADC_EXTERNALTRIGINJECCONV_T2_TRGO;
  sConfigInjected.AutoInjectedConv              = DISABLE;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.InjectedOffset                = 0;

  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
  sConfigInjected.InjectedRank = 2;
  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
  sConfigInjected.InjectedRank = 3;
  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
  sConfigInjected.InjectedRank = 4;
  HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected);
  SET_BIT(hadc1.Instance->CR1, (ADC_CR1_JEOCIE)); // Enable end of injected conv irq
  // Run ADC internal calibration
  while (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) {
    ;
  }
}

/* ADC2 init function */
static void MX_ADC2_Init(void) {
  ADC_InjectionConfTypeDef sConfigInjected;

  /**Common config
   */
  hadc2.Instance                   = ADC2;
  hadc2.Init.ScanConvMode          = ADC_SCAN_DISABLE;
  hadc2.Init.ContinuousConvMode    = ENABLE;
  hadc2.Init.DiscontinuousConvMode = DISABLE;
  hadc2.Init.ExternalTrigConv      = ADC_SOFTWARE_START;
  hadc2.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
  hadc2.Init.NbrOfConversion       = 0;
  HAL_ADC_Init(&hadc2);

  /**Configure Injected Channel
   */
  sConfigInjected.InjectedChannel               = VIN_ADC2_CHANNEL;
  sConfigInjected.InjectedRank                  = ADC_INJECTED_RANK_1;
  sConfigInjected.InjectedNbrOfConversion       = 4;
  sConfigInjected.InjectedSamplingTime          = ADC_SAMPLETIME_28CYCLES_5;
  sConfigInjected.ExternalTrigInjecConv         = ADC_EXTERNALTRIGINJECCONV_T2_TRGO;
  sConfigInjected.AutoInjectedConv              = DISABLE;
  sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
  sConfigInjected.InjectedOffset                = 0;
  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_2;
  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_3;
  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);
  sConfigInjected.InjectedRank = ADC_INJECTED_RANK_4;
  HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected);

  // Run ADC internal calibration
  while (HAL_ADCEx_Calibration_Start(&hadc2) != HAL_OK) {
    ;
  }
}

/* IWDG init function */
static void MX_IWDG_Init(void) {
  hiwdg.Instance       = IWDG;
  hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
  hiwdg.Init.Reload    = 2048;
#ifndef SWD_ENABLE
  HAL_IWDG_Init(&hiwdg);
#endif
}

static void MX_TIM4_Init(void) {
  /*
   * On Sequre devies we run the output PWM as fast as possible due to the low tip resistance + no inductor for filtering.
   * So we run it as fast as we can and hope that the caps filter out the current spikes.
   * */
  TIM_ClockConfigTypeDef  sClockSourceConfig;
  TIM_MasterConfigTypeDef sMasterConfig;
  TIM_OC_InitTypeDef      sConfigOC;
  memset(&sConfigOC, 0, sizeof(sConfigOC));

  htim4.Instance = TIM4;
  // dummy value, will be reconfigured by BSPInit()
  htim4.Init.Prescaler = 10; // 2 MHz timer clock/10 = 200 kHz tick rate

  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim4.Init.Period      = 64;

  htim4.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1; // 8 MHz (x2 APB1) before divide
  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  htim4.Init.RepetitionCounter = 0;
  HAL_TIM_Base_Init(&htim4);

  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig);
  HAL_TIM_PWM_Init(&htim4);
  HAL_TIM_OC_Init(&htim4);

  sConfigOC.OCMode = TIM_OCMODE_PWM1;

  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
  sConfigOC.Pulse      = 0; // default to entirely off
  HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, PWM_Out_CHANNEL);

  GPIO_InitTypeDef GPIO_InitStruct;
  GPIO_InitStruct.Pin   = PWM_Out_Pin;
  GPIO_InitStruct.Mode  = GPIO_MODE_AF_PP;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // We would like sharp rising edges
  HAL_GPIO_Init(PWM_Out_GPIO_Port, &GPIO_InitStruct);

  // HAL_NVIC_SetPriority(TIM4_IRQn, 15, 0);
  // HAL_NVIC_EnableIRQ(TIM4_IRQn);

  HAL_TIM_Base_Start(&htim4);
  HAL_TIM_PWM_Start(&htim4, PWM_Out_CHANNEL);
}
///////////////////
static void MX_TIM2_Init(void) {
  /*
   * We use the channel 1 to trigger the ADC at end of PWM period
   * And we use the channel 4 as the PWM modulation source using Interrupts
   * */
  TIM_ClockConfigTypeDef  sClockSourceConfig;
  TIM_MasterConfigTypeDef sMasterConfig;
  TIM_OC_InitTypeDef      sConfigOC;
  memset(&sConfigOC, 0, sizeof(sConfigOC));
  memset(&sClockSourceConfig, 0, sizeof(sClockSourceConfig));
  memset(&sMasterConfig, 0, sizeof(sMasterConfig));

  // Timer 2 is fairly slow as its being used to run the PWM and trigger the ADC
  // in the PWM off time.
  htim2.Instance = TIM2;
  // dummy value, will be reconfigured by BSPInit()
  htim2.Init.Prescaler = 2000; // 2 MHz timer clock/2000 = 1 kHz tick rate

  // pwm out is 10k from tim3, we want to run our PWM at around 10hz or slower on the output stage
  // These values give a rate of around 3.5 Hz for "fast" mode and 1.84 Hz for "slow"
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
  // dummy value, will be reconfigured by BSPInit()
  htim2.Init.Period = powerPWM + 14 * 2;

  htim2.Init.ClockDivision     = TIM_CLOCKDIVISION_DIV4; // 8 MHz (x2 APB1) before divide
  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  htim2.Init.RepetitionCounter = 0;
  HAL_TIM_Base_Init(&htim2);

  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig);

  HAL_TIM_PWM_Init(&htim2);
  HAL_TIM_OC_Init(&htim2);

  sMasterConfig.MasterOutputTrigger = TIM_TRGO_OC1;
  sMasterConfig.MasterSlaveMode     = TIM_MASTERSLAVEMODE_DISABLE;
  HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);

  sConfigOC.OCMode = TIM_OCMODE_PWM1;
  // dummy value, will be reconfigured by BSPInit() in the BSP.cpp
  sConfigOC.Pulse = powerPWM + 14; // 13 -> Delay of 7 ms
  // 255 is the largest time period of the drive signal, and then offset ADC sample to be a bit delayed after this
  /*
   * It takes 4 milliseconds for output to be stable after PWM turns off.
   * Assume ADC samples in 0.5ms
   * We need to set this to 100% + 4.5ms
   * */
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
  HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1); // ADC Triggers

  sConfigOC.Pulse = powerPWM; // Power PWM cycle time

  HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4); // Output triggers

  HAL_TIM_Base_Start_IT(&htim2);
  HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
  HAL_TIM_PWM_Start_IT(&htim2, TIM_CHANNEL_4);

  HAL_NVIC_SetPriority(TIM2_IRQn, 15, 0);
  HAL_NVIC_EnableIRQ(TIM2_IRQn);
}
/**
 * Enable DMA controller clock
 */
static void MX_DMA_Init(void) {
  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();

  /* DMA interrupt init */
  /* DMA1_Channel1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
  /* DMA1_Channel6_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
  /* DMA1_Channel7_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
}

/** Configure pins as
 * Analog
 * Input
 * Output
 * EVENT_OUT
 * EXTI
 * Free pins are configured automatically as Analog
 PB0   ------> ADCx_IN8
 PB1   ------> ADCx_IN9
 */
static void MX_GPIO_Init(void) {
  GPIO_InitTypeDef GPIO_InitStruct;

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();

  /*Configure peripheral I/O remapping */
  __HAL_AFIO_REMAP_PD01_ENABLE();
  //^ remap XTAL so that pins can be analog (all input buffers off).
  // reduces power consumption

  /*
   * Configure All pins as analog by default
   */
  GPIO_InitStruct.Pin  = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_15;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
                        GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

  /*Configure GPIO pins : KEY_B_Pin KEY_A_Pin */
  GPIO_InitStruct.Pin  = KEY_B_Pin | KEY_A_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_PULLUP;
  HAL_GPIO_Init(KEY_B_GPIO_Port, &GPIO_InitStruct);
}
#ifdef USE_FULL_ASSERT
void assert_failed(uint8_t *file, uint32_t line) { asm("bkpt"); }
#endif


================================================
FILE: source/Core/BSP/Sequre/Setup.h
================================================
/*
 * Setup.h
 *
 *  Created on: 29Aug.,2017
 *      Author: Ben V. Brown
 */

#ifndef SETUP_H_
#define SETUP_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "stm32f1xx_hal.h"

extern ADC_HandleTypeDef hadc1;
extern ADC_HandleTypeDef hadc2;
extern DMA_HandleTypeDef hdma_adc1;

extern IWDG_HandleTypeDef hiwdg;

extern TIM_HandleTypeDef htim4;
extern TIM_HandleTypeDef htim2;
void                     Setup_HAL();
uint16_t                 getADCHandleTemp(uint8_t sample);
uint16_t                 getADCVin(uint8_t sample);
void                     HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); // Since the hal header file does not define this one

#ifdef __cplusplus
}
#endif

#endif /* SETUP_H_ */


================================================
FILE: source/Core/BSP/Sequre/Software_I2C.h
================================================
/*
 * Software_I2C.h
 *
 *  Created on: 25 Jul 2020
 *      Author: Ralim
 */

#ifndef BSP_MINIWARE_SOFTWARE_I2C_H_
#define BSP_MINIWARE_SOFTWARE_I2C_H_
#include "BSP.h"
#include "configuration.h"
#include "stm32f1xx_hal.h"
#ifdef I2C_SOFT_BUS_2

#define SOFT_SCL2_HIGH() HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_SET)
#define SOFT_SCL2_LOW()  HAL_GPIO_WritePin(SCL2_GPIO_Port, SCL2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA2_HIGH() HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_SET)
#define SOFT_SDA2_LOW()  HAL_GPIO_WritePin(SDA2_GPIO_Port, SDA2_Pin, GPIO_PIN_RESET)
#define SOFT_SDA2_READ() (HAL_GPIO_ReadPin(SDA2_GPIO_Port, SDA2_Pin) == GPIO_PIN_SET ? 1 : 0)
#define SOFT_SCL2_READ() (HAL_GPIO_ReadPin(SCL2_GPIO_Port, SCL2_Pin) == GPIO_PIN_SET ? 1 : 0)
// clang-format off
#define SOFT_I2C_DELAY()              \
  {                                   \
    for (int xx = 0; xx < 12; xx++) { \
      asm("nop");                     \
    }                                 \
  }
// clang-format on

#endif
// 40 ~= 100kHz; 15 gives around 250kHz or so which is fast _and_ stable

#endif /* BSP_MINIWARE_SOFTWARE_I2C_H_ */


================================================
FILE: source/Core/BSP/Sequre/Startup/startup_stm32f103t8ux.S
================================================
/**
  ******************************************************************************
  * @file      startup_stm32.s
  * @author    Ac6
  * @version   V1.0.0
  * @date      12-June-2014
  ******************************************************************************
  */

  .syntax unified
  .cpu cortex-m3
  .thumb

.global	g_pfnVectors
.global	Default_Handler

/* start address for the initialization values of the .data section.
defined in linker script */
.word	_sidata
/* start address for the .data section. defined in linker script */
.word	_sdata
/* end address for the .data section. defined in linker script */
.word	_edata
/* start address for the .bss section. defined in linker script */
.word	_sbss
/* end address for the .bss section. defined in linker script */
.word	_ebss

.equ  BootRAM,        0xF1E0F85F
/**
 * @brief  This is the code that gets called when the processor first
 *          starts execution following a reset event. Only the absolutely
 *          necessary set is performed, after which the application
 *          supplied main() routine is called.
 * @param  None
 * @retval : None
*/

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs	r1, #0
  b	LoopCopyDataInit

CopyDataInit:
	ldr	r3, =_sidata
	ldr	r3, [r3, r1]
	str	r3, [r0, r1]
	adds	r1, r1, #4

LoopCopyDataInit:
	ldr	r0, =_sdata
	ldr	r3, =_edata
	adds	r2, r0, r1
	cmp	r2, r3
	bcc	CopyDataInit
	ldr	r2, =_sbss
	b	LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
	movs r3, #0
 	str  r3, [r2]
	adds r2, r2, #4

LoopFillZerobss:
	ldr	r3, = _ebss
	cmp	r2, r3
	bcc	FillZerobss

/* Call the clock system intitialization function.*/
    bl  SystemInit
/* Call static constructors */
    bl __libc_init_array
/* Call the application's entry point.*/
	bl	main

LoopForever:
    b LoopForever

.size	Reset_Handler, .-Reset_Handler

/**
 * @brief  This is the code that gets called when the processor receives an
 *         unexpected interrupt.  This simply enters an infinite loop, preserving
 *         the system state for examination by a debugger.
 *
 * @param  None
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
	.size	Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M.  Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
 	.section	.isr_vector,"a",%progbits
	.type	g_pfnVectors, %object
	.size	g_pfnVectors, .-g_pfnVectors

g_pfnVectors:
	.word _estack
  .word Reset_Handler
  .word NMI_Handler
  .word HardFault_Handler
  .word MemManage_Handler
  .word BusFault_Handler
  .word UsageFault_Handler
  .word 0
  .word 0
  .word 0
  .word 0
  .word SVC_Handler
  .word DebugMon_Handler
  .word 0
  .word PendSV_Handler
  .word SysTick_Handler
  .word WWDG_IRQHandler
  .word PVD_IRQHandler
  .word TAMPER_IRQHandler
  .word RTC_IRQHandler
  .word FLASH_IRQHandler
  .word RCC_IRQHandler
  .word EXTI0_IRQHandler
  .word EXTI1_IRQHandler
  .word EXTI2_IRQHandler
  .word EXTI3_IRQHandler
  .word EXTI4_IRQHandler
  .word DMA1_Channel1_IRQHandler
  .word DMA1_Channel2_IRQHandler
  .word DMA1_Channel3_IRQHandler
  .word DMA1_Channel4_IRQHandler
  .word DMA1_Channel5_IRQHandler
  .word DMA1_Channel6_IRQHandler
  .word DMA1_Channel7_IRQHandler
  .word ADC1_2_IRQHandler
  .word USB_HP_CAN1_TX_IRQHandler
  .word USB_LP_CAN1_RX0_IRQHandler
  .word CAN1_RX1_IRQHandler
  .word CAN1_SCE_IRQHandler
  .word EXTI9_5_IRQHandler
  .word TIM1_BRK_IRQHandler
  .word TIM1_UP_IRQHandler
  .word TIM1_TRG_COM_IRQHandler
  .word TIM1_CC_IRQHandler
  .word TIM2_IRQHandler
  .word TIM3_IRQHandler
  .word TIM4_IRQHandler
  .word I2C1_EV_IRQHandler
  .word I2C1_ER_IRQHandler
  .word I2C2_EV_IRQHandler
  .word I2C2_ER_IRQHandler
  .word SPI1_IRQHandler
  .word SPI2_IRQHandler
  .word USART1_IRQHandler
  .word USART2_IRQHandler
  .word USART3_IRQHandler
  .word EXTI15_10_IRQHandler
  .word RTC_Alarm_IRQHandler
  .word USBWakeUp_IRQHandler
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word 0
  .word BootRAM          /* @0x108. This is for boot in RAM mode for
                            STM32F10x Medium Density devices. */

/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/

  	.weak NMI_Handler
  .thumb_set NMI_Handler,Default_Handler

  .weak HardFault_Handler
  .thumb_set HardFault_Handler,Default_Handler

  .weak MemManage_Handler
  .thumb_set MemManage_Handler,Default_Handler

  .weak BusFault_Handler
  .thumb_set BusFault_Handler,Default_Handler

  .weak UsageFault_Handler
  .thumb_set UsageFault_Handler,Default_Handler

  .weak SVC_Handler
  .thumb_set SVC_Handler,Default_Handler

  .weak DebugMon_Handler
  .thumb_set DebugMon_Handler,Default_Handler

  .weak PendSV_Handler
  .thumb_set PendSV_Handler,Default_Handler

  .weak SysTick_Handler
  .thumb_set SysTick_Handler,Default_Handler

  .weak WWDG_IRQHandler
  .thumb_set WWDG_IRQHandler,Default_Handler

  .weak PVD_IRQHandler
  .thumb_set PVD_IRQHandler,Default_Handler

  .weak TAMPER_IRQHandler
  .thumb_set TAMPER_IRQHandler,Default_Handler

  .weak RTC_IRQHandler
  .thumb_set RTC_IRQHandler,Default_Handler

  .weak FLASH_IRQHandler
  .thumb_set FLASH_IRQHandler,Default_Handler

  .weak RCC_IRQHandler
  .thumb_set RCC_IRQHandler,Default_Handler

  .weak EXTI0_IRQHandler
  .thumb_set EXTI0_IRQHandler,Default_Handler

  .weak EXTI1_IRQHandler
  .thumb_set EXTI1_IRQHandler,Default_Handler

  .weak EXTI2_IRQHandler
  .thumb_set EXTI2_IRQHandler,Default_Handler

  .weak EXTI3_IRQHandler
  .thumb_set EXTI3_IRQHandler,Default_Handler

  .weak EXTI4_IRQHandler
  .thumb_set EXTI4_IRQHandler,Default_Handler

  .weak DMA1_Channel1_IRQHandler
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler

  .weak DMA1_Channel2_IRQHandler
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler

  .weak DMA1_Channel3_IRQHandler
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler

  .weak DMA1_Channel4_IRQHandler
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler

  .weak DMA1_Channel5_IRQHandler
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler

  .weak DMA1_Channel6_IRQHandler
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler

  .weak DMA1_Channel7_IRQHandler
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler

  .weak ADC1_2_IRQHandler
  .thumb_set ADC1_2_IRQHandler,Default_Handler

  .weak USB_HP_CAN1_TX_IRQHandler
  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler

  .weak USB_LP_CAN1_RX0_IRQHandler
  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler

  .weak CAN1_RX1_IRQHandler
  .thumb_set CAN1_RX1_IRQHandler,Default_Handler

  .weak CAN1_SCE_IRQHandler
  .thumb_set CAN1_SCE_IRQHandler,Default_Handler

  .weak EXTI9_5_IRQHandler
  .thumb_set EXTI9_5_IRQHandler,Default_Handler

  .weak TIM1_BRK_IRQHandler
  .thumb_set TIM1_BRK_IRQHandler,Default_Handler

  .weak TIM1_UP_IRQHandler
  .thumb_set TIM1_UP_IRQHandler,Default_Handler

  .weak TIM1_TRG_COM_IRQHandler
  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler

  .weak TIM1_CC_IRQHandler
  .thumb_set TIM1_CC_IRQHandler,Default_Handler

  .weak TIM2_IRQHandler
  .thumb_set TIM2_IRQHandler,Default_Handler

  .weak TIM3_IRQHandler
  .thumb_set TIM3_IRQHandler,Default_Handler

  .weak TIM4_IRQHandler
  .thumb_set TIM4_IRQHandler,Default_Handler

  .weak I2C1_EV_IRQHandler
  .thumb_set I2C1_EV_IRQHandler,Default_Handler

  .weak I2C1_ER_IRQHandler
  .thumb_set I2C1_ER_IRQHandler,Default_Handler

  .weak I2C2_EV_IRQHandler
  .thumb_set I2C2_EV_IRQHandler,Default_Handler

  .weak I2C2_ER_IRQHandler
  .thumb_set I2C2_ER_IRQHandler,Default_Handler

  .weak SPI1_IRQHandler
  .thumb_set SPI1_IRQHandler,Default_Handler

  .weak SPI2_IRQHandler
  .thumb_set SPI2_IRQHandler,Default_Handler

  .weak USART1_IRQHandler
  .thumb_set USART1_IRQHandler,Default_Handler

  .weak USART2_IRQHandler
  .thumb_set USART2_IRQHandler,Default_Handler

  .weak USART3_IRQHandler
  .thumb_set USART3_IRQHandler,Default_Handler

  .weak EXTI15_10_IRQHandler
  .thumb_set EXTI15_10_IRQHandler,Default_Handler

  .weak RTC_Alarm_IRQHandler
  .thumb_set RTC_Alarm_IRQHandler,Default_Handler

  .weak USBWakeUp_IRQHandler
  .thumb_set USBWakeUp_IRQHandler,Default_Handler


/************************ (C) COPYRIGHT Ac6 *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/ThermoModel.cpp
================================================
/*
 * ThermoModel.cpp
 *
 *  Created on: 1 May 2021
 *      Author: Ralim
 */
#include "TipThermoModel.h"
#include "Utils.hpp"
#include "configuration.h"

#ifdef TEMP_uV_LOOKUP_PT1000
// Use https://br.flukecal.com/pt100-table-generator to make table for resistance to temp
const int32_t ohmsToDegC[] = {
    //
    //  Resistance (ohms x10)	Temperature (Celsius)

    10000, 0,   //
    10390, 10,  //
    10779, 20,  //
    11167, 30,  //
    11554, 40,  //
    11940, 50,  //
    12324, 60,  //
    12708, 70,  //
    13090, 80,  //
    13471, 90,  //
    13851, 100, //
    14229, 110, //
    14607, 120, //
    14983, 130, //
    15358, 140, //
    15733, 150, //
    16105, 160, //
    16477, 170, //
    16848, 180, //
    17217, 190, //
    17586, 200, //
    17953, 210, //
    18319, 220, //
    18684, 230, //
    19047, 240, //
    19410, 250, //
    19771, 260, //
    20131, 270, //
    20490, 280, //
    20848, 290, //
    21205, 300, //
    21561, 310, //
    21915, 320, //
    22268, 330, //
    22621, 340, //
    22972, 350, //
    23321, 360, //
    23670, 370, //
    24018, 380, //
    24364, 390, //
    24709, 400, //
    25053, 410, //
    25396, 420, //
    25738, 430, //
    26078, 440, //
    26418, 450, //
    26756, 460, //
    27093, 470, //
    27429, 480, //
    27764, 490, //
    28098, 500, //

};

TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) {

  // 3.3V -> 1K ->(ADC) <- PT1000 <- GND
  // PT100 = (adc*r1)/(3.3V-adc)
  uint32_t reading_mv     = tipuVDelta / 1000;
  uint32_t resistance_x10 = (reading_mv * 10000) / (3300 - reading_mv);

  return Utils::InterpolateLookupTable(ohmsToDegC, sizeof(ohmsToDegC) / (2 * sizeof(int32_t)), resistance_x10);
}

#endif // TEMP_uV_LOOKUP_PT1000

#ifdef TEMP_uV_LOOKUP_S60
TemperatureType_t TipThermoModel::convertuVToDegC(uint32_t tipuVDelta) { return (tipuVDelta * 50) / 485; }
#endif // TEMP_uV_LOOKUP_S60


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
================================================
/**
 ******************************************************************************
 * @file    stm32f103xb.h
 * @author  MCD Application Team
 * @version V4.2.0
 * @date    31-March-2017
 * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
 *          This file contains all the peripheral register's definitions, bits
 *          definitions and memory mapping for STM32F1xx devices.
 *
 *          This file contains:
 *           - Data structures and the address mapping for all peripherals
 *           - Peripheral's registers declarations and bits definition
 *           - Macros to access peripherals registers hardware
 *
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/** @addtogroup CMSIS
 * @{
 */

/** @addtogroup stm32f103xb
 * @{
 */

#ifndef __STM32F103xB_H
#define __STM32F103xB_H

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup Configuration_section_for_CMSIS
 * @{
 */
/**
 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
 */
#define __CM3_REV              0x0200U /*!< Core Revision r2p0                           */
#define __MPU_PRESENT          0U      /*!< Other STM32 devices does not provide an MPU  */
#define __NVIC_PRIO_BITS       4U      /*!< STM32 uses 4 Bits for the Priority Levels    */
#define __Vendor_SysTickConfig 0U      /*!< Set to 1 if different SysTick Config is used */

/**
 * @}
 */

/** @addtogroup Peripheral_interrupt_number_definition
 * @{
 */

/**
 * @brief STM32F10x Interrupt Number Definition, according to the selected device
 *        in @ref Library_configuration_section
 */

/*!< Interrupt Number Definition */
typedef enum {
  /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
  NonMaskableInt_IRQn   = -14, /*!< 2 Non Maskable Interrupt                             */
  HardFault_IRQn        = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt              */
  BusFault_IRQn         = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
  UsageFault_IRQn       = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
  SVCall_IRQn           = -5,  /*!< 11 Cortex-M3 SV Call Interrupt                       */
  DebugMonitor_IRQn     = -4,  /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
  PendSV_IRQn           = -2,  /*!< 14 Cortex-M3 Pend SV Interrupt                       */
  SysTick_IRQn          = -1,  /*!< 15 Cortex-M3 System Tick Interrupt                   */

  /******  STM32 specific Interrupt Numbers *********************************************************/
  WWDG_IRQn            = 0,  /*!< Window WatchDog Interrupt                            */
  PVD_IRQn             = 1,  /*!< PVD through EXTI Line detection Interrupt            */
  TAMPER_IRQn          = 2,  /*!< Tamper Interrupt                                     */
  RTC_IRQn             = 3,  /*!< RTC global Interrupt                                 */
  FLASH_IRQn           = 4,  /*!< FLASH global Interrupt                               */
  RCC_IRQn             = 5,  /*!< RCC global Interrupt                                 */
  EXTI0_IRQn           = 6,  /*!< EXTI Line0 Interrupt                                 */
  EXTI1_IRQn           = 7,  /*!< EXTI Line1 Interrupt                                 */
  EXTI2_IRQn           = 8,  /*!< EXTI Line2 Interrupt                                 */
  EXTI3_IRQn           = 9,  /*!< EXTI Line3 Interrupt                                 */
  EXTI4_IRQn           = 10, /*!< EXTI Line4 Interrupt                                 */
  DMA1_Channel1_IRQn   = 11, /*!< DMA1 Channel 1 global Interrupt                      */
  DMA1_Channel2_IRQn   = 12, /*!< DMA1 Channel 2 global Interrupt                      */
  DMA1_Channel3_IRQn   = 13, /*!< DMA1 Channel 3 global Interrupt                      */
  DMA1_Channel4_IRQn   = 14, /*!< DMA1 Channel 4 global Interrupt                      */
  DMA1_Channel5_IRQn   = 15, /*!< DMA1 Channel 5 global Interrupt                      */
  DMA1_Channel6_IRQn   = 16, /*!< DMA1 Channel 6 global Interrupt                      */
  DMA1_Channel7_IRQn   = 17, /*!< DMA1 Channel 7 global Interrupt                      */
  ADC1_2_IRQn          = 18, /*!< ADC1 and ADC2 global Interrupt                       */
  USB_HP_CAN1_TX_IRQn  = 19, /*!< USB Device High Priority or CAN1 TX Interrupts       */
  USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
  CAN1_RX1_IRQn        = 21, /*!< CAN1 RX1 Interrupt                                   */
  CAN1_SCE_IRQn        = 22, /*!< CAN1 SCE Interrupt                                   */
  EXTI9_5_IRQn         = 23, /*!< External Line[9:5] Interrupts                        */
  TIM1_BRK_IRQn        = 24, /*!< TIM1 Break Interrupt                                 */
  TIM1_UP_IRQn         = 25, /*!< TIM1 Update Interrupt                                */
  TIM1_TRG_COM_IRQn    = 26, /*!< TIM1 Trigger and Commutation Interrupt               */
  TIM1_CC_IRQn         = 27, /*!< TIM1 Capture Compare Interrupt                       */
  TIM2_IRQn            = 28, /*!< TIM2 global Interrupt                                */
  TIM3_IRQn            = 29, /*!< TIM3 global Interrupt                                */
  TIM4_IRQn            = 30, /*!< TIM4 global Interrupt                                */
  I2C1_EV_IRQn         = 31, /*!< I2C1 Event Interrupt                                 */
  I2C1_ER_IRQn         = 32, /*!< I2C1 Error Interrupt                                 */
  I2C2_EV_IRQn         = 33, /*!< I2C2 Event Interrupt                                 */
  I2C2_ER_IRQn         = 34, /*!< I2C2 Error Interrupt                                 */
  SPI1_IRQn            = 35, /*!< SPI1 global Interrupt                                */
  SPI2_IRQn            = 36, /*!< SPI2 global Interrupt                                */
  USART1_IRQn          = 37, /*!< USART1 global Interrupt                              */
  USART2_IRQn          = 38, /*!< USART2 global Interrupt                              */
  USART3_IRQn          = 39, /*!< USART3 global Interrupt                              */
  EXTI15_10_IRQn       = 40, /*!< External Line[15:10] Interrupts                      */
  RTC_Alarm_IRQn       = 41, /*!< RTC Alarm through EXTI Line Interrupt                */
  USBWakeUp_IRQn       = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
} IRQn_Type;

/**
 * @}
 */

#include "core_cm3.h"
#include "system_stm32f1xx.h"
#include 

/** @addtogroup Peripheral_registers_structures
 * @{
 */

/**
 * @brief Analog to Digital Converter
 */

typedef struct {
  __IO uint32_t SR;
  __IO uint32_t CR1;
  __IO uint32_t CR2;
  __IO uint32_t SMPR1;
  __IO uint32_t SMPR2;
  __IO uint32_t JOFR1;
  __IO uint32_t JOFR2;
  __IO uint32_t JOFR3;
  __IO uint32_t JOFR4;
  __IO uint32_t HTR;
  __IO uint32_t LTR;
  __IO uint32_t SQR1;
  __IO uint32_t SQR2;
  __IO uint32_t SQR3;
  __IO uint32_t JSQR;
  __IO uint32_t JDR1;
  __IO uint32_t JDR2;
  __IO uint32_t JDR3;
  __IO uint32_t JDR4;
  __IO uint32_t DR;
} ADC_TypeDef;

typedef struct {
  __IO uint32_t SR;  /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
  __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
  __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
  uint32_t      RESERVED[16];
  __IO uint32_t DR; /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */
} ADC_Common_TypeDef;

/**
 * @brief Backup Registers
 */

typedef struct {
  uint32_t      RESERVED0;
  __IO uint32_t DR1;
  __IO uint32_t DR2;
  __IO uint32_t DR3;
  __IO uint32_t DR4;
  __IO uint32_t DR5;
  __IO uint32_t DR6;
  __IO uint32_t DR7;
  __IO uint32_t DR8;
  __IO uint32_t DR9;
  __IO uint32_t DR10;
  __IO uint32_t RTCCR;
  __IO uint32_t CR;
  __IO uint32_t CSR;
} BKP_TypeDef;

/**
 * @brief Controller Area Network TxMailBox
 */

typedef struct {
  __IO uint32_t TIR;
  __IO uint32_t TDTR;
  __IO uint32_t TDLR;
  __IO uint32_t TDHR;
} CAN_TxMailBox_TypeDef;

/**
 * @brief Controller Area Network FIFOMailBox
 */

typedef struct {
  __IO uint32_t RIR;
  __IO uint32_t RDTR;
  __IO uint32_t RDLR;
  __IO uint32_t RDHR;
} CAN_FIFOMailBox_TypeDef;

/**
 * @brief Controller Area Network FilterRegister
 */

typedef struct {
  __IO uint32_t FR1;
  __IO uint32_t FR2;
} CAN_FilterRegister_TypeDef;

/**
 * @brief Controller Area Network
 */

typedef struct {
  __IO uint32_t              MCR;
  __IO uint32_t              MSR;
  __IO uint32_t              TSR;
  __IO uint32_t              RF0R;
  __IO uint32_t              RF1R;
  __IO uint32_t              IER;
  __IO uint32_t              ESR;
  __IO uint32_t              BTR;
  uint32_t                   RESERVED0[88];
  CAN_TxMailBox_TypeDef      sTxMailBox[3];
  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];
  uint32_t                   RESERVED1[12];
  __IO uint32_t              FMR;
  __IO uint32_t              FM1R;
  uint32_t                   RESERVED2;
  __IO uint32_t              FS1R;
  uint32_t                   RESERVED3;
  __IO uint32_t              FFA1R;
  uint32_t                   RESERVED4;
  __IO uint32_t              FA1R;
  uint32_t                   RESERVED5[8];
  CAN_FilterRegister_TypeDef sFilterRegister[14];
} CAN_TypeDef;

/**
 * @brief CRC calculation unit
 */

typedef struct {
  __IO uint32_t DR;        /*!< CRC Data register,                           Address offset: 0x00 */
  __IO uint8_t  IDR;       /*!< CRC Independent data register,               Address offset: 0x04 */
  uint8_t       RESERVED0; /*!< Reserved,                                    Address offset: 0x05 */
  uint16_t      RESERVED1; /*!< Reserved,                                    Address offset: 0x06 */
  __IO uint32_t CR;        /*!< CRC Control register,                        Address offset: 0x08 */
} CRC_TypeDef;

/**
 * @brief Debug MCU
 */

typedef struct {
  __IO uint32_t IDCODE;
  __IO uint32_t CR;
} DBGMCU_TypeDef;

/**
 * @brief DMA Controller
 */

typedef struct {
  __IO uint32_t CCR;
  __IO uint32_t CNDTR;
  __IO uint32_t CPAR;
  __IO uint32_t CMAR;
} DMA_Channel_TypeDef;

typedef struct {
  __IO uint32_t ISR;
  __IO uint32_t IFCR;
} DMA_TypeDef;

/**
 * @brief External Interrupt/Event Controller
 */

typedef struct {
  __IO uint32_t IMR;
  __IO uint32_t EMR;
  __IO uint32_t RTSR;
  __IO uint32_t FTSR;
  __IO uint32_t SWIER;
  __IO uint32_t PR;
} EXTI_TypeDef;

/**
 * @brief FLASH Registers
 */

typedef struct {
  __IO uint32_t ACR;
  __IO uint32_t KEYR;
  __IO uint32_t OPTKEYR;
  __IO uint32_t SR;
  __IO uint32_t CR;
  __IO uint32_t AR;
  __IO uint32_t RESERVED;
  __IO uint32_t OBR;
  __IO uint32_t WRPR;
} FLASH_TypeDef;

/**
 * @brief Option Bytes Registers
 */

typedef struct {
  __IO uint16_t RDP;
  __IO uint16_t USER;
  __IO uint16_t Data0;
  __IO uint16_t Data1;
  __IO uint16_t WRP0;
  __IO uint16_t WRP1;
  __IO uint16_t WRP2;
  __IO uint16_t WRP3;
} OB_TypeDef;

/**
 * @brief General Purpose I/O
 */

typedef struct {
  __IO uint32_t CRL;
  __IO uint32_t CRH;
  __IO uint32_t IDR;
  __IO uint32_t ODR;
  __IO uint32_t BSRR;
  __IO uint32_t BRR;
  __IO uint32_t LCKR;
} GPIO_TypeDef;

/**
 * @brief Alternate Function I/O
 */

typedef struct {
  __IO uint32_t EVCR;
  __IO uint32_t MAPR;
  __IO uint32_t EXTICR[4];
  uint32_t      RESERVED0;
  __IO uint32_t MAPR2;
} AFIO_TypeDef;
/**
 * @brief Inter Integrated Circuit Interface
 */

typedef struct {
  __IO uint32_t CR1;
  __IO uint32_t CR2;
  __IO uint32_t OAR1;
  __IO uint32_t OAR2;
  __IO uint32_t DR;
  __IO uint32_t SR1;
  __IO uint32_t SR2;
  __IO uint32_t CCR;
  __IO uint32_t TRISE;
} I2C_TypeDef;

/**
 * @brief Independent WATCHDOG
 */

typedef struct {
  __IO uint32_t KR;  /*!< Key register,                                Address offset: 0x00 */
  __IO uint32_t PR;  /*!< Prescaler register,                          Address offset: 0x04 */
  __IO uint32_t RLR; /*!< Reload register,                             Address offset: 0x08 */
  __IO uint32_t SR;  /*!< Status register,                             Address offset: 0x0C */
} IWDG_TypeDef;

/**
 * @brief Power Control
 */

typedef struct {
  __IO uint32_t CR;
  __IO uint32_t CSR;
} PWR_TypeDef;

/**
 * @brief Reset and Clock Control
 */

typedef struct {
  __IO uint32_t CR;
  __IO uint32_t CFGR;
  __IO uint32_t CIR;
  __IO uint32_t APB2RSTR;
  __IO uint32_t APB1RSTR;
  __IO uint32_t AHBENR;
  __IO uint32_t APB2ENR;
  __IO uint32_t APB1ENR;
  __IO uint32_t BDCR;
  __IO uint32_t CSR;

} RCC_TypeDef;

/**
 * @brief Real-Time Clock
 */

typedef struct {
  __IO uint32_t CRH;
  __IO uint32_t CRL;
  __IO uint32_t PRLH;
  __IO uint32_t PRLL;
  __IO uint32_t DIVH;
  __IO uint32_t DIVL;
  __IO uint32_t CNTH;
  __IO uint32_t CNTL;
  __IO uint32_t ALRH;
  __IO uint32_t ALRL;
} RTC_TypeDef;

/**
 * @brief SD host Interface
 */

typedef struct {
  __IO uint32_t POWER;
  __IO uint32_t CLKCR;
  __IO uint32_t ARG;
  __IO uint32_t CMD;
  __I uint32_t  RESPCMD;
  __I uint32_t  RESP1;
  __I uint32_t  RESP2;
  __I uint32_t  RESP3;
  __I uint32_t  RESP4;
  __IO uint32_t DTIMER;
  __IO uint32_t DLEN;
  __IO uint32_t DCTRL;
  __I uint32_t  DCOUNT;
  __I uint32_t  STA;
  __IO uint32_t ICR;
  __IO uint32_t MASK;
  uint32_t      RESERVED0[2];
  __I uint32_t  FIFOCNT;
  uint32_t      RESERVED1[13];
  __IO uint32_t FIFO;
} SDIO_TypeDef;

/**
 * @brief Serial Peripheral Interface
 */

typedef struct {
  __IO uint32_t CR1;
  __IO uint32_t CR2;
  __IO uint32_t SR;
  __IO uint32_t DR;
  __IO uint32_t CRCPR;
  __IO uint32_t RXCRCR;
  __IO uint32_t TXCRCR;
  __IO uint32_t I2SCFGR;
} SPI_TypeDef;

/**
 * @brief TIM Timers
 */
typedef struct {
  __IO uint32_t CR1;   /*!< TIM control register 1,                      Address offset: 0x00 */
  __IO uint32_t CR2;   /*!< TIM control register 2,                      Address offset: 0x04 */
  __IO uint32_t SMCR;  /*!< TIM slave Mode Control register,             Address offset: 0x08 */
  __IO uint32_t DIER;  /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
  __IO uint32_t SR;    /*!< TIM status register,                         Address offset: 0x10 */
  __IO uint32_t EGR;   /*!< TIM event generation register,               Address offset: 0x14 */
  __IO uint32_t CCMR1; /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
  __IO uint32_t CCMR2; /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
  __IO uint32_t CCER;  /*!< TIM capture/compare enable register,         Address offset: 0x20 */
  __IO uint32_t CNT;   /*!< TIM counter register,                        Address offset: 0x24 */
  __IO uint32_t PSC;   /*!< TIM prescaler register,                      Address offset: 0x28 */
  __IO uint32_t ARR;   /*!< TIM auto-reload register,                    Address offset: 0x2C */
  __IO uint32_t RCR;   /*!< TIM  repetition counter register,            Address offset: 0x30 */
  __IO uint32_t CCR1;  /*!< TIM capture/compare register 1,              Address offset: 0x34 */
  __IO uint32_t CCR2;  /*!< TIM capture/compare register 2,              Address offset: 0x38 */
  __IO uint32_t CCR3;  /*!< TIM capture/compare register 3,              Address offset: 0x3C */
  __IO uint32_t CCR4;  /*!< TIM capture/compare register 4,              Address offset: 0x40 */
  __IO uint32_t BDTR;  /*!< TIM break and dead-time register,            Address offset: 0x44 */
  __IO uint32_t DCR;   /*!< TIM DMA control register,                    Address offset: 0x48 */
  __IO uint32_t DMAR;  /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
  __IO uint32_t OR;    /*!< TIM option register,                         Address offset: 0x50 */
} TIM_TypeDef;

/**
 * @brief Universal Synchronous Asynchronous Receiver Transmitter
 */

typedef struct {
  __IO uint32_t SR;   /*!< USART Status register,                   Address offset: 0x00 */
  __IO uint32_t DR;   /*!< USART Data register,                     Address offset: 0x04 */
  __IO uint32_t BRR;  /*!< USART Baud rate register,                Address offset: 0x08 */
  __IO uint32_t CR1;  /*!< USART Control register 1,                Address offset: 0x0C */
  __IO uint32_t CR2;  /*!< USART Control register 2,                Address offset: 0x10 */
  __IO uint32_t CR3;  /*!< USART Control register 3,                Address offset: 0x14 */
  __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;

/**
 * @brief Universal Serial Bus Full Speed Device
 */

typedef struct {
  __IO uint16_t EP0R;          /*!< USB Endpoint 0 register,                   Address offset: 0x00 */
  __IO uint16_t RESERVED0;     /*!< Reserved */
  __IO uint16_t EP1R;          /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
  __IO uint16_t RESERVED1;     /*!< Reserved */
  __IO uint16_t EP2R;          /*!< USB Endpoint 2 register,                   Address offset: 0x08 */
  __IO uint16_t RESERVED2;     /*!< Reserved */
  __IO uint16_t EP3R;          /*!< USB Endpoint 3 register,                   Address offset: 0x0C */
  __IO uint16_t RESERVED3;     /*!< Reserved */
  __IO uint16_t EP4R;          /*!< USB Endpoint 4 register,                   Address offset: 0x10 */
  __IO uint16_t RESERVED4;     /*!< Reserved */
  __IO uint16_t EP5R;          /*!< USB Endpoint 5 register,                   Address offset: 0x14 */
  __IO uint16_t RESERVED5;     /*!< Reserved */
  __IO uint16_t EP6R;          /*!< USB Endpoint 6 register,                   Address offset: 0x18 */
  __IO uint16_t RESERVED6;     /*!< Reserved */
  __IO uint16_t EP7R;          /*!< USB Endpoint 7 register,                   Address offset: 0x1C */
  __IO uint16_t RESERVED7[17]; /*!< Reserved */
  __IO uint16_t CNTR;          /*!< Control register,                          Address offset: 0x40 */
  __IO uint16_t RESERVED8;     /*!< Reserved */
  __IO uint16_t ISTR;          /*!< Interrupt status register,                 Address offset: 0x44 */
  __IO uint16_t RESERVED9;     /*!< Reserved */
  __IO uint16_t FNR;           /*!< Frame number register,                     Address offset: 0x48 */
  __IO uint16_t RESERVEDA;     /*!< Reserved */
  __IO uint16_t DADDR;         /*!< Device address register,                   Address offset: 0x4C */
  __IO uint16_t RESERVEDB;     /*!< Reserved */
  __IO uint16_t BTABLE;        /*!< Buffer Table address register,             Address offset: 0x50 */
  __IO uint16_t RESERVEDC;     /*!< Reserved */
} USB_TypeDef;

/**
 * @brief Window WATCHDOG
 */

typedef struct {
  __IO uint32_t CR;  /*!< WWDG Control register,       Address offset: 0x00 */
  __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  __IO uint32_t SR;  /*!< WWDG Status register,        Address offset: 0x08 */
} WWDG_TypeDef;

/**
 * @}
 */

/** @addtogroup Peripheral_memory_map
 * @{
 */

#define FLASH_BASE      0x08000000U /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
#define SRAM_BASE       0x20000000U /*!< SRAM base address in the alias region */
#define PERIPH_BASE     0x40000000U /*!< Peripheral base address in the alias region */

#define SRAM_BB_BASE   0x22000000U /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */

/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
#define AHBPERIPH_BASE  (PERIPH_BASE + 0x00020000U)

#define TIM2_BASE   (APB1PERIPH_BASE + 0x00000000U)
#define TIM3_BASE   (APB1PERIPH_BASE + 0x00000400U)
#define TIM4_BASE   (APB1PERIPH_BASE + 0x00000800U)
#define RTC_BASE    (APB1PERIPH_BASE + 0x00002800U)
#define WWDG_BASE   (APB1PERIPH_BASE + 0x00002C00U)
#define IWDG_BASE   (APB1PERIPH_BASE + 0x00003000U)
#define SPI2_BASE   (APB1PERIPH_BASE + 0x00003800U)
#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
#define I2C1_BASE   (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE   (APB1PERIPH_BASE + 0x00006400U)
#define BKP_BASE    (APB1PERIPH_BASE + 0x00006C00U)
#define PWR_BASE    (APB1PERIPH_BASE + 0x00007000U)
#define AFIO_BASE   (APB2PERIPH_BASE + 0x00000000U)
#define EXTI_BASE   (APB2PERIPH_BASE + 0x00000400U)
#define GPIOA_BASE  (APB2PERIPH_BASE + 0x00000800U)
#define GPIOB_BASE  (APB2PERIPH_BASE + 0x00000C00U)
#define GPIOC_BASE  (APB2PERIPH_BASE + 0x00001000U)
#define GPIOD_BASE  (APB2PERIPH_BASE + 0x00001400U)
#define GPIOE_BASE  (APB2PERIPH_BASE + 0x00001800U)
#define ADC1_BASE   (APB2PERIPH_BASE + 0x00002400U)
#define ADC2_BASE   (APB2PERIPH_BASE + 0x00002800U)
#define TIM1_BASE   (APB2PERIPH_BASE + 0x00002C00U)
#define SPI1_BASE   (APB2PERIPH_BASE + 0x00003000U)
#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)

#define SDIO_BASE (PERIPH_BASE + 0x00018000U)

#define DMA1_BASE          (AHBPERIPH_BASE + 0x00000000U)
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
#define RCC_BASE           (AHBPERIPH_BASE + 0x00001000U)
#define CRC_BASE           (AHBPERIPH_BASE + 0x00003000U)

#define FLASH_R_BASE   (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U                    /*!< FLASH Size register base address */
#define UID_BASE       0x1FFFF7E8U                    /*!< Unique device ID register base address */
#define OB_BASE        0x1FFFF800U                    /*!< Flash Option Bytes base address */

#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */

/* USB device FS */
#define USB_BASE    (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */

/**
 * @}
 */

/** @addtogroup Peripheral_declaration
 * @{
 */

#define TIM2          ((TIM_TypeDef *)TIM2_BASE)
#define TIM3          ((TIM_TypeDef *)TIM3_BASE)
#define TIM4          ((TIM_TypeDef *)TIM4_BASE)
#define RTC           ((RTC_TypeDef *)RTC_BASE)
#define WWDG          ((WWDG_TypeDef *)WWDG_BASE)
#define IWDG          ((IWDG_TypeDef *)IWDG_BASE)
#define SPI2          ((SPI_TypeDef *)SPI2_BASE)
#define USART2        ((USART_TypeDef *)USART2_BASE)
#define USART3        ((USART_TypeDef *)USART3_BASE)
#define I2C1          ((I2C_TypeDef *)I2C1_BASE)
#define I2C2          ((I2C_TypeDef *)I2C2_BASE)
#define USB           ((USB_TypeDef *)USB_BASE)
#define CAN1          ((CAN_TypeDef *)CAN1_BASE)
#define BKP           ((BKP_TypeDef *)BKP_BASE)
#define PWR           ((PWR_TypeDef *)PWR_BASE)
#define AFIO          ((AFIO_TypeDef *)AFIO_BASE)
#define EXTI          ((EXTI_TypeDef *)EXTI_BASE)
#define GPIOA         ((GPIO_TypeDef *)GPIOA_BASE)
#define GPIOB         ((GPIO_TypeDef *)GPIOB_BASE)
#define GPIOC         ((GPIO_TypeDef *)GPIOC_BASE)
#define GPIOD         ((GPIO_TypeDef *)GPIOD_BASE)
#define GPIOE         ((GPIO_TypeDef *)GPIOE_BASE)
#define ADC1          ((ADC_TypeDef *)ADC1_BASE)
#define ADC2          ((ADC_TypeDef *)ADC2_BASE)
#define ADC12_COMMON  ((ADC_Common_TypeDef *)ADC1_BASE)
#define TIM1          ((TIM_TypeDef *)TIM1_BASE)
#define SPI1          ((SPI_TypeDef *)SPI1_BASE)
#define USART1        ((USART_TypeDef *)USART1_BASE)
#define SDIO          ((SDIO_TypeDef *)SDIO_BASE)
#define DMA1          ((DMA_TypeDef *)DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
#define RCC           ((RCC_TypeDef *)RCC_BASE)
#define CRC           ((CRC_TypeDef *)CRC_BASE)
#define FLASH         ((FLASH_TypeDef *)FLASH_R_BASE)
#define OB            ((OB_TypeDef *)OB_BASE)
#define DBGMCU        ((DBGMCU_TypeDef *)DBGMCU_BASE)

/**
 * @}
 */

/** @addtogroup Exported_constants
 * @{
 */

/** @addtogroup Peripheral_Registers_Bits_Definition
 * @{
 */

/******************************************************************************/
/*                         Peripheral Registers_Bits_Definition               */
/******************************************************************************/

/******************************************************************************/
/*                                                                            */
/*                       CRC calculation unit (CRC)                           */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for CRC_DR register  *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR     CRC_DR_DR_Msk                  /*!< Data register bits */

/*******************  Bit definition for CRC_IDR register  ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR     CRC_IDR_IDR_Msk            /*!< General-purpose 8-bit data register bits */

/********************  Bit definition for CRC_CR register  ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET     CRC_CR_RESET_Msk           /*!< RESET bit */

/******************************************************************************/
/*                                                                            */
/*                             Power Control                                  */
/*                                                                            */
/******************************************************************************/

/********************  Bit definition for PWR_CR register  ********************/
#define PWR_CR_LPDS_Pos (0U)
#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
#define PWR_CR_LPDS     PWR_CR_LPDS_Msk           /*!< Low-Power Deepsleep */
#define PWR_CR_PDDS_Pos (1U)
#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
#define PWR_CR_PDDS     PWR_CR_PDDS_Msk           /*!< Power Down Deepsleep */
#define PWR_CR_CWUF_Pos (2U)
#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
#define PWR_CR_CWUF     PWR_CR_CWUF_Msk           /*!< Clear Wakeup Flag */
#define PWR_CR_CSBF_Pos (3U)
#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
#define PWR_CR_CSBF     PWR_CR_CSBF_Msk           /*!< Clear Standby Flag */
#define PWR_CR_PVDE_Pos (4U)
#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
#define PWR_CR_PVDE     PWR_CR_PVDE_Msk           /*!< Power Voltage Detector Enable */

#define PWR_CR_PLS_Pos (5U)
#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
#define PWR_CR_PLS     PWR_CR_PLS_Msk           /*!< PLS[2:0] bits (PVD Level Selection) */
#define PWR_CR_PLS_0   (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
#define PWR_CR_PLS_1   (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
#define PWR_CR_PLS_2   (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */

/*!< PVD level configuration */
#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */

/* Legacy defines */
#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7

#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR_DBP     PWR_CR_DBP_Msk           /*!< Disable Backup Domain write protection */

/*******************  Bit definition for PWR_CSR register  ********************/
#define PWR_CSR_WUF_Pos  (0U)
#define PWR_CSR_WUF_Msk  (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
#define PWR_CSR_WUF      PWR_CSR_WUF_Msk           /*!< Wakeup Flag */
#define PWR_CSR_SBF_Pos  (1U)
#define PWR_CSR_SBF_Msk  (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
#define PWR_CSR_SBF      PWR_CSR_SBF_Msk           /*!< Standby Flag */
#define PWR_CSR_PVDO_Pos (2U)
#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
#define PWR_CSR_PVDO     PWR_CSR_PVDO_Msk           /*!< PVD Output */
#define PWR_CSR_EWUP_Pos (8U)
#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
#define PWR_CSR_EWUP     PWR_CSR_EWUP_Msk           /*!< Enable WKUP pin */

/******************************************************************************/
/*                                                                            */
/*                            Backup registers                                */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for BKP_DR1 register  ********************/
#define BKP_DR1_D_Pos (0U)
#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR1_D     BKP_DR1_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR2 register  ********************/
#define BKP_DR2_D_Pos (0U)
#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR2_D     BKP_DR2_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR3 register  ********************/
#define BKP_DR3_D_Pos (0U)
#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR3_D     BKP_DR3_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR4 register  ********************/
#define BKP_DR4_D_Pos (0U)
#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR4_D     BKP_DR4_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR5 register  ********************/
#define BKP_DR5_D_Pos (0U)
#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR5_D     BKP_DR5_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR6 register  ********************/
#define BKP_DR6_D_Pos (0U)
#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR6_D     BKP_DR6_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR7 register  ********************/
#define BKP_DR7_D_Pos (0U)
#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR7_D     BKP_DR7_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR8 register  ********************/
#define BKP_DR8_D_Pos (0U)
#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR8_D     BKP_DR8_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR9 register  ********************/
#define BKP_DR9_D_Pos (0U)
#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR9_D     BKP_DR9_D_Msk              /*!< Backup data */

/*******************  Bit definition for BKP_DR10 register  *******************/
#define BKP_DR10_D_Pos (0U)
#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
#define BKP_DR10_D     BKP_DR10_D_Msk              /*!< Backup data */

#define RTC_BKP_NUMBER 10

/******************  Bit definition for BKP_RTCCR register  *******************/
#define BKP_RTCCR_CAL_Pos  (0U)
#define BKP_RTCCR_CAL_Msk  (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
#define BKP_RTCCR_CAL      BKP_RTCCR_CAL_Msk            /*!< Calibration value */
#define BKP_RTCCR_CCO_Pos  (7U)
#define BKP_RTCCR_CCO_Msk  (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
#define BKP_RTCCR_CCO      BKP_RTCCR_CCO_Msk           /*!< Calibration Clock Output */
#define BKP_RTCCR_ASOE_Pos (8U)
#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
#define BKP_RTCCR_ASOE     BKP_RTCCR_ASOE_Msk           /*!< Alarm or Second Output Enable */
#define BKP_RTCCR_ASOS_Pos (9U)
#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
#define BKP_RTCCR_ASOS     BKP_RTCCR_ASOS_Msk           /*!< Alarm or Second Output Selection */

/********************  Bit definition for BKP_CR register  ********************/
#define BKP_CR_TPE_Pos  (0U)
#define BKP_CR_TPE_Msk  (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
#define BKP_CR_TPE      BKP_CR_TPE_Msk           /*!< TAMPER pin enable */
#define BKP_CR_TPAL_Pos (1U)
#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
#define BKP_CR_TPAL     BKP_CR_TPAL_Msk           /*!< TAMPER pin active level */

/*******************  Bit definition for BKP_CSR register  ********************/
#define BKP_CSR_CTE_Pos  (0U)
#define BKP_CSR_CTE_Msk  (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
#define BKP_CSR_CTE      BKP_CSR_CTE_Msk           /*!< Clear Tamper event */
#define BKP_CSR_CTI_Pos  (1U)
#define BKP_CSR_CTI_Msk  (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
#define BKP_CSR_CTI      BKP_CSR_CTI_Msk           /*!< Clear Tamper Interrupt */
#define BKP_CSR_TPIE_Pos (2U)
#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
#define BKP_CSR_TPIE     BKP_CSR_TPIE_Msk           /*!< TAMPER Pin interrupt enable */
#define BKP_CSR_TEF_Pos  (8U)
#define BKP_CSR_TEF_Msk  (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
#define BKP_CSR_TEF      BKP_CSR_TEF_Msk           /*!< Tamper Event Flag */
#define BKP_CSR_TIF_Pos  (9U)
#define BKP_CSR_TIF_Msk  (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
#define BKP_CSR_TIF      BKP_CSR_TIF_Msk           /*!< Tamper Interrupt Flag */

/******************************************************************************/
/*                                                                            */
/*                         Reset and Clock Control                            */
/*                                                                            */
/******************************************************************************/

/********************  Bit definition for RCC_CR register  ********************/
#define RCC_CR_HSION_Pos   (0U)
#define RCC_CR_HSION_Msk   (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
#define RCC_CR_HSION       RCC_CR_HSION_Msk           /*!< Internal High Speed clock enable */
#define RCC_CR_HSIRDY_Pos  (1U)
#define RCC_CR_HSIRDY_Msk  (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CR_HSIRDY      RCC_CR_HSIRDY_Msk           /*!< Internal High Speed clock ready flag */
#define RCC_CR_HSITRIM_Pos (3U)
#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
#define RCC_CR_HSITRIM     RCC_CR_HSITRIM_Msk            /*!< Internal High Speed clock trimming */
#define RCC_CR_HSICAL_Pos  (8U)
#define RCC_CR_HSICAL_Msk  (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
#define RCC_CR_HSICAL      RCC_CR_HSICAL_Msk            /*!< Internal High Speed clock Calibration */
#define RCC_CR_HSEON_Pos   (16U)
#define RCC_CR_HSEON_Msk   (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON       RCC_CR_HSEON_Msk           /*!< External High Speed clock enable */
#define RCC_CR_HSERDY_Pos  (17U)
#define RCC_CR_HSERDY_Msk  (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY      RCC_CR_HSERDY_Msk           /*!< External High Speed clock ready flag */
#define RCC_CR_HSEBYP_Pos  (18U)
#define RCC_CR_HSEBYP_Msk  (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP      RCC_CR_HSEBYP_Msk           /*!< External High Speed clock Bypass */
#define RCC_CR_CSSON_Pos   (19U)
#define RCC_CR_CSSON_Msk   (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON       RCC_CR_CSSON_Msk           /*!< Clock Security System enable */
#define RCC_CR_PLLON_Pos   (24U)
#define RCC_CR_PLLON_Msk   (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON       RCC_CR_PLLON_Msk           /*!< PLL enable */
#define RCC_CR_PLLRDY_Pos  (25U)
#define RCC_CR_PLLRDY_Msk  (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY      RCC_CR_PLLRDY_Msk           /*!< PLL clock ready flag */

/*******************  Bit definition for RCC_CFGR register  *******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW     RCC_CFGR_SW_Msk           /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0   (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1   (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */

#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */

/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS     RCC_CFGR_SWS_Msk           /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0   (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1   (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */

#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */

/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE     RCC_CFGR_HPRE_Msk           /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0   (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1   (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2   (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3   (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */

#define RCC_CFGR_HPRE_DIV1   0x00000000U /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2   0x00000080U /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4   0x00000090U /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8   0x000000A0U /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16  0x000000B0U /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64  0x000000C0U /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */

/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1     RCC_CFGR_PPRE1_Msk           /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0   (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1   (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2   (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */

#define RCC_CFGR_PPRE1_DIV1  0x00000000U /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2  0x00000400U /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4  0x00000500U /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8  0x00000600U /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */

/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2     RCC_CFGR_PPRE2_Msk           /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0   (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1   (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2   (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */

#define RCC_CFGR_PPRE2_DIV1  0x00000000U /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2  0x00002000U /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4  0x00002800U /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8  0x00003000U /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */

/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
#define RCC_CFGR_ADCPRE     RCC_CFGR_ADCPRE_Msk           /*!< ADCPRE[1:0] bits (ADC prescaler) */
#define RCC_CFGR_ADCPRE_0   (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1   (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */

#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */

#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
#define RCC_CFGR_PLLSRC     RCC_CFGR_PLLSRC_Msk           /*!< PLL entry clock source */

#define RCC_CFGR_PLLXTPRE_Pos (17U)
#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
#define RCC_CFGR_PLLXTPRE     RCC_CFGR_PLLXTPRE_Msk           /*!< HSE divider for PLL entry */

/*!< PLLMUL configuration */
#define RCC_CFGR_PLLMULL_Pos (18U)
#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
#define RCC_CFGR_PLLMULL     RCC_CFGR_PLLMULL_Msk           /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
#define RCC_CFGR_PLLMULL_0   (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL_1   (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
#define RCC_CFGR_PLLMULL_2   (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3   (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */

#define RCC_CFGR_PLLXTPRE_HSE      0x00000000U /*!< HSE clock not divided for PLL entry */
#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */

#define RCC_CFGR_PLLMULL2      0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos  (18U)
#define RCC_CFGR_PLLMULL3_Msk  (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3      RCC_CFGR_PLLMULL3_Msk           /*!< PLL input clock*3 */
#define RCC_CFGR_PLLMULL4_Pos  (19U)
#define RCC_CFGR_PLLMULL4_Msk  (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
#define RCC_CFGR_PLLMULL4      RCC_CFGR_PLLMULL4_Msk           /*!< PLL input clock*4 */
#define RCC_CFGR_PLLMULL5_Pos  (18U)
#define RCC_CFGR_PLLMULL5_Msk  (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
#define RCC_CFGR_PLLMULL5      RCC_CFGR_PLLMULL5_Msk           /*!< PLL input clock*5 */
#define RCC_CFGR_PLLMULL6_Pos  (20U)
#define RCC_CFGR_PLLMULL6_Msk  (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL6      RCC_CFGR_PLLMULL6_Msk           /*!< PLL input clock*6 */
#define RCC_CFGR_PLLMULL7_Pos  (18U)
#define RCC_CFGR_PLLMULL7_Msk  (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
#define RCC_CFGR_PLLMULL7      RCC_CFGR_PLLMULL7_Msk           /*!< PLL input clock*7 */
#define RCC_CFGR_PLLMULL8_Pos  (19U)
#define RCC_CFGR_PLLMULL8_Msk  (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
#define RCC_CFGR_PLLMULL8      RCC_CFGR_PLLMULL8_Msk           /*!< PLL input clock*8 */
#define RCC_CFGR_PLLMULL9_Pos  (18U)
#define RCC_CFGR_PLLMULL9_Msk  (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
#define RCC_CFGR_PLLMULL9      RCC_CFGR_PLLMULL9_Msk           /*!< PLL input clock*9 */
#define RCC_CFGR_PLLMULL10_Pos (21U)
#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
#define RCC_CFGR_PLLMULL10     RCC_CFGR_PLLMULL10_Msk           /*!< PLL input clock10 */
#define RCC_CFGR_PLLMULL11_Pos (18U)
#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
#define RCC_CFGR_PLLMULL11     RCC_CFGR_PLLMULL11_Msk           /*!< PLL input clock*11 */
#define RCC_CFGR_PLLMULL12_Pos (19U)
#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
#define RCC_CFGR_PLLMULL12     RCC_CFGR_PLLMULL12_Msk           /*!< PLL input clock*12 */
#define RCC_CFGR_PLLMULL13_Pos (18U)
#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
#define RCC_CFGR_PLLMULL13     RCC_CFGR_PLLMULL13_Msk           /*!< PLL input clock*13 */
#define RCC_CFGR_PLLMULL14_Pos (20U)
#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
#define RCC_CFGR_PLLMULL14     RCC_CFGR_PLLMULL14_Msk           /*!< PLL input clock*14 */
#define RCC_CFGR_PLLMULL15_Pos (18U)
#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
#define RCC_CFGR_PLLMULL15     RCC_CFGR_PLLMULL15_Msk           /*!< PLL input clock*15 */
#define RCC_CFGR_PLLMULL16_Pos (19U)
#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
#define RCC_CFGR_PLLMULL16     RCC_CFGR_PLLMULL16_Msk           /*!< PLL input clock*16 */
#define RCC_CFGR_USBPRE_Pos    (22U)
#define RCC_CFGR_USBPRE_Msk    (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
#define RCC_CFGR_USBPRE        RCC_CFGR_USBPRE_Msk           /*!< USB Device prescaler */

/*!< MCO configuration */
#define RCC_CFGR_MCO_Pos (24U)
#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
#define RCC_CFGR_MCO     RCC_CFGR_MCO_Msk           /*!< MCO[2:0] bits (Microcontroller Clock Output) */
#define RCC_CFGR_MCO_0   (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCO_1   (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2   (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */

#define RCC_CFGR_MCO_NOCLOCK     0x00000000U /*!< No clock */
#define RCC_CFGR_MCO_SYSCLK      0x04000000U /*!< System clock selected as MCO source */
#define RCC_CFGR_MCO_HSI         0x05000000U /*!< HSI clock selected as MCO source */
#define RCC_CFGR_MCO_HSE         0x06000000U /*!< HSE clock selected as MCO source  */
#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */

/* Reference defines */
#define RCC_CFGR_MCOSEL          RCC_CFGR_MCO
#define RCC_CFGR_MCOSEL_0        RCC_CFGR_MCO_0
#define RCC_CFGR_MCOSEL_1        RCC_CFGR_MCO_1
#define RCC_CFGR_MCOSEL_2        RCC_CFGR_MCO_2
#define RCC_CFGR_MCOSEL_NOCLOCK  RCC_CFGR_MCO_NOCLOCK
#define RCC_CFGR_MCOSEL_SYSCLK   RCC_CFGR_MCO_SYSCLK
#define RCC_CFGR_MCOSEL_HSI      RCC_CFGR_MCO_HSI
#define RCC_CFGR_MCOSEL_HSE      RCC_CFGR_MCO_HSE
#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2

/*!<******************  Bit definition for RCC_CIR register  ********************/
#define RCC_CIR_LSIRDYF_Pos  (0U)
#define RCC_CIR_LSIRDYF_Msk  (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIR_LSIRDYF      RCC_CIR_LSIRDYF_Msk           /*!< LSI Ready Interrupt flag */
#define RCC_CIR_LSERDYF_Pos  (1U)
#define RCC_CIR_LSERDYF_Msk  (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIR_LSERDYF      RCC_CIR_LSERDYF_Msk           /*!< LSE Ready Interrupt flag */
#define RCC_CIR_HSIRDYF_Pos  (2U)
#define RCC_CIR_HSIRDYF_Msk  (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
#define RCC_CIR_HSIRDYF      RCC_CIR_HSIRDYF_Msk           /*!< HSI Ready Interrupt flag */
#define RCC_CIR_HSERDYF_Pos  (3U)
#define RCC_CIR_HSERDYF_Msk  (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
#define RCC_CIR_HSERDYF      RCC_CIR_HSERDYF_Msk           /*!< HSE Ready Interrupt flag */
#define RCC_CIR_PLLRDYF_Pos  (4U)
#define RCC_CIR_PLLRDYF_Msk  (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
#define RCC_CIR_PLLRDYF      RCC_CIR_PLLRDYF_Msk           /*!< PLL Ready Interrupt flag */
#define RCC_CIR_CSSF_Pos     (7U)
#define RCC_CIR_CSSF_Msk     (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
#define RCC_CIR_CSSF         RCC_CIR_CSSF_Msk           /*!< Clock Security System Interrupt flag */
#define RCC_CIR_LSIRDYIE_Pos (8U)
#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
#define RCC_CIR_LSIRDYIE     RCC_CIR_LSIRDYIE_Msk           /*!< LSI Ready Interrupt Enable */
#define RCC_CIR_LSERDYIE_Pos (9U)
#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
#define RCC_CIR_LSERDYIE     RCC_CIR_LSERDYIE_Msk           /*!< LSE Ready Interrupt Enable */
#define RCC_CIR_HSIRDYIE_Pos (10U)
#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
#define RCC_CIR_HSIRDYIE     RCC_CIR_HSIRDYIE_Msk           /*!< HSI Ready Interrupt Enable */
#define RCC_CIR_HSERDYIE_Pos (11U)
#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
#define RCC_CIR_HSERDYIE     RCC_CIR_HSERDYIE_Msk           /*!< HSE Ready Interrupt Enable */
#define RCC_CIR_PLLRDYIE_Pos (12U)
#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
#define RCC_CIR_PLLRDYIE     RCC_CIR_PLLRDYIE_Msk           /*!< PLL Ready Interrupt Enable */
#define RCC_CIR_LSIRDYC_Pos  (16U)
#define RCC_CIR_LSIRDYC_Msk  (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
#define RCC_CIR_LSIRDYC      RCC_CIR_LSIRDYC_Msk           /*!< LSI Ready Interrupt Clear */
#define RCC_CIR_LSERDYC_Pos  (17U)
#define RCC_CIR_LSERDYC_Msk  (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
#define RCC_CIR_LSERDYC      RCC_CIR_LSERDYC_Msk           /*!< LSE Ready Interrupt Clear */
#define RCC_CIR_HSIRDYC_Pos  (18U)
#define RCC_CIR_HSIRDYC_Msk  (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
#define RCC_CIR_HSIRDYC      RCC_CIR_HSIRDYC_Msk           /*!< HSI Ready Interrupt Clear */
#define RCC_CIR_HSERDYC_Pos  (19U)
#define RCC_CIR_HSERDYC_Msk  (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
#define RCC_CIR_HSERDYC      RCC_CIR_HSERDYC_Msk           /*!< HSE Ready Interrupt Clear */
#define RCC_CIR_PLLRDYC_Pos  (20U)
#define RCC_CIR_PLLRDYC_Msk  (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
#define RCC_CIR_PLLRDYC      RCC_CIR_PLLRDYC_Msk           /*!< PLL Ready Interrupt Clear */
#define RCC_CIR_CSSC_Pos     (23U)
#define RCC_CIR_CSSC_Msk     (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
#define RCC_CIR_CSSC         RCC_CIR_CSSC_Msk           /*!< Clock Security System Interrupt Clear */

/*****************  Bit definition for RCC_APB2RSTR register  *****************/
#define RCC_APB2RSTR_AFIORST_Pos (0U)
#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_AFIORST     RCC_APB2RSTR_AFIORST_Msk           /*!< Alternate Function I/O reset */
#define RCC_APB2RSTR_IOPARST_Pos (2U)
#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
#define RCC_APB2RSTR_IOPARST     RCC_APB2RSTR_IOPARST_Msk           /*!< I/O port A reset */
#define RCC_APB2RSTR_IOPBRST_Pos (3U)
#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
#define RCC_APB2RSTR_IOPBRST     RCC_APB2RSTR_IOPBRST_Msk           /*!< I/O port B reset */
#define RCC_APB2RSTR_IOPCRST_Pos (4U)
#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
#define RCC_APB2RSTR_IOPCRST     RCC_APB2RSTR_IOPCRST_Msk           /*!< I/O port C reset */
#define RCC_APB2RSTR_IOPDRST_Pos (5U)
#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTR_IOPDRST     RCC_APB2RSTR_IOPDRST_Msk           /*!< I/O port D reset */
#define RCC_APB2RSTR_ADC1RST_Pos (9U)
#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADC1RST     RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC 1 interface reset */

#define RCC_APB2RSTR_ADC2RST_Pos (10U)
#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
#define RCC_APB2RSTR_ADC2RST     RCC_APB2RSTR_ADC2RST_Msk           /*!< ADC 2 interface reset */

#define RCC_APB2RSTR_TIM1RST_Pos   (11U)
#define RCC_APB2RSTR_TIM1RST_Msk   (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST       RCC_APB2RSTR_TIM1RST_Msk           /*!< TIM1 Timer reset */
#define RCC_APB2RSTR_SPI1RST_Pos   (12U)
#define RCC_APB2RSTR_SPI1RST_Msk   (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST       RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI 1 reset */
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST     RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */

#define RCC_APB2RSTR_IOPERST_Pos (6U)
#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_IOPERST     RCC_APB2RSTR_IOPERST_Msk           /*!< I/O port E reset */

/*****************  Bit definition for RCC_APB1RSTR register  *****************/
#define RCC_APB1RSTR_TIM2RST_Pos   (0U)
#define RCC_APB1RSTR_TIM2RST_Msk   (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR_TIM2RST       RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
#define RCC_APB1RSTR_TIM3RST_Pos   (1U)
#define RCC_APB1RSTR_TIM3RST_Msk   (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR_TIM3RST       RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
#define RCC_APB1RSTR_WWDGRST_Pos   (11U)
#define RCC_APB1RSTR_WWDGRST_Msk   (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR_WWDGRST       RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
#define RCC_APB1RSTR_USART2RST_Pos (17U)
#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTR_USART2RST     RCC_APB1RSTR_USART2RST_Msk           /*!< USART 2 reset */
#define RCC_APB1RSTR_I2C1RST_Pos   (21U)
#define RCC_APB1RSTR_I2C1RST_Msk   (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR_I2C1RST       RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */

#define RCC_APB1RSTR_CAN1RST_Pos (25U)
#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
#define RCC_APB1RSTR_CAN1RST     RCC_APB1RSTR_CAN1RST_Msk           /*!< CAN1 reset */

#define RCC_APB1RSTR_BKPRST_Pos (27U)
#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
#define RCC_APB1RSTR_BKPRST     RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */
#define RCC_APB1RSTR_PWRRST_Pos (28U)
#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
#define RCC_APB1RSTR_PWRRST     RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */

#define RCC_APB1RSTR_TIM4RST_Pos   (2U)
#define RCC_APB1RSTR_TIM4RST_Msk   (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
#define RCC_APB1RSTR_TIM4RST       RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
#define RCC_APB1RSTR_SPI2RST_Pos   (14U)
#define RCC_APB1RSTR_SPI2RST_Msk   (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR_SPI2RST       RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
#define RCC_APB1RSTR_USART3RST_Pos (18U)
#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR_USART3RST     RCC_APB1RSTR_USART3RST_Msk           /*!< USART 3 reset */
#define RCC_APB1RSTR_I2C2RST_Pos   (22U)
#define RCC_APB1RSTR_I2C2RST_Msk   (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR_I2C2RST       RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */

#define RCC_APB1RSTR_USBRST_Pos (23U)
#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR_USBRST     RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */

/******************  Bit definition for RCC_AHBENR register  ******************/
#define RCC_AHBENR_DMA1EN_Pos  (0U)
#define RCC_AHBENR_DMA1EN_Msk  (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHBENR_DMA1EN      RCC_AHBENR_DMA1EN_Msk           /*!< DMA1 clock enable */
#define RCC_AHBENR_SRAMEN_Pos  (2U)
#define RCC_AHBENR_SRAMEN_Msk  (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
#define RCC_AHBENR_SRAMEN      RCC_AHBENR_SRAMEN_Msk           /*!< SRAM interface clock enable */
#define RCC_AHBENR_FLITFEN_Pos (4U)
#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
#define RCC_AHBENR_FLITFEN     RCC_AHBENR_FLITFEN_Msk           /*!< FLITF clock enable */
#define RCC_AHBENR_CRCEN_Pos   (6U)
#define RCC_AHBENR_CRCEN_Msk   (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
#define RCC_AHBENR_CRCEN       RCC_AHBENR_CRCEN_Msk           /*!< CRC clock enable */

/******************  Bit definition for RCC_APB2ENR register  *****************/
#define RCC_APB2ENR_AFIOEN_Pos (0U)
#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
#define RCC_APB2ENR_AFIOEN     RCC_APB2ENR_AFIOEN_Msk           /*!< Alternate Function I/O clock enable */
#define RCC_APB2ENR_IOPAEN_Pos (2U)
#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
#define RCC_APB2ENR_IOPAEN     RCC_APB2ENR_IOPAEN_Msk           /*!< I/O port A clock enable */
#define RCC_APB2ENR_IOPBEN_Pos (3U)
#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
#define RCC_APB2ENR_IOPBEN     RCC_APB2ENR_IOPBEN_Msk           /*!< I/O port B clock enable */
#define RCC_APB2ENR_IOPCEN_Pos (4U)
#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
#define RCC_APB2ENR_IOPCEN     RCC_APB2ENR_IOPCEN_Msk           /*!< I/O port C clock enable */
#define RCC_APB2ENR_IOPDEN_Pos (5U)
#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
#define RCC_APB2ENR_IOPDEN     RCC_APB2ENR_IOPDEN_Msk           /*!< I/O port D clock enable */
#define RCC_APB2ENR_ADC1EN_Pos (9U)
#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
#define RCC_APB2ENR_ADC1EN     RCC_APB2ENR_ADC1EN_Msk           /*!< ADC 1 interface clock enable */

#define RCC_APB2ENR_ADC2EN_Pos (10U)
#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
#define RCC_APB2ENR_ADC2EN     RCC_APB2ENR_ADC2EN_Msk           /*!< ADC 2 interface clock enable */

#define RCC_APB2ENR_TIM1EN_Pos   (11U)
#define RCC_APB2ENR_TIM1EN_Msk   (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN       RCC_APB2ENR_TIM1EN_Msk           /*!< TIM1 Timer clock enable */
#define RCC_APB2ENR_SPI1EN_Pos   (12U)
#define RCC_APB2ENR_SPI1EN_Msk   (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN       RCC_APB2ENR_SPI1EN_Msk           /*!< SPI 1 clock enable */
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN     RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */

#define RCC_APB2ENR_IOPEEN_Pos (6U)
#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
#define RCC_APB2ENR_IOPEEN     RCC_APB2ENR_IOPEEN_Msk           /*!< I/O port E clock enable */

/*****************  Bit definition for RCC_APB1ENR register  ******************/
#define RCC_APB1ENR_TIM2EN_Pos   (0U)
#define RCC_APB1ENR_TIM2EN_Msk   (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
#define RCC_APB1ENR_TIM2EN       RCC_APB1ENR_TIM2EN_Msk           /*!< Timer 2 clock enabled*/
#define RCC_APB1ENR_TIM3EN_Pos   (1U)
#define RCC_APB1ENR_TIM3EN_Msk   (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
#define RCC_APB1ENR_TIM3EN       RCC_APB1ENR_TIM3EN_Msk           /*!< Timer 3 clock enable */
#define RCC_APB1ENR_WWDGEN_Pos   (11U)
#define RCC_APB1ENR_WWDGEN_Msk   (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
#define RCC_APB1ENR_WWDGEN       RCC_APB1ENR_WWDGEN_Msk           /*!< Window Watchdog clock enable */
#define RCC_APB1ENR_USART2EN_Pos (17U)
#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
#define RCC_APB1ENR_USART2EN     RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
#define RCC_APB1ENR_I2C1EN_Pos   (21U)
#define RCC_APB1ENR_I2C1EN_Msk   (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
#define RCC_APB1ENR_I2C1EN       RCC_APB1ENR_I2C1EN_Msk           /*!< I2C 1 clock enable */

#define RCC_APB1ENR_CAN1EN_Pos (25U)
#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
#define RCC_APB1ENR_CAN1EN     RCC_APB1ENR_CAN1EN_Msk           /*!< CAN1 clock enable */

#define RCC_APB1ENR_BKPEN_Pos (27U)
#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
#define RCC_APB1ENR_BKPEN     RCC_APB1ENR_BKPEN_Msk           /*!< Backup interface clock enable */
#define RCC_APB1ENR_PWREN_Pos (28U)
#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR_PWREN     RCC_APB1ENR_PWREN_Msk           /*!< Power interface clock enable */

#define RCC_APB1ENR_TIM4EN_Pos   (2U)
#define RCC_APB1ENR_TIM4EN_Msk   (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
#define RCC_APB1ENR_TIM4EN       RCC_APB1ENR_TIM4EN_Msk           /*!< Timer 4 clock enable */
#define RCC_APB1ENR_SPI2EN_Pos   (14U)
#define RCC_APB1ENR_SPI2EN_Msk   (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
#define RCC_APB1ENR_SPI2EN       RCC_APB1ENR_SPI2EN_Msk           /*!< SPI 2 clock enable */
#define RCC_APB1ENR_USART3EN_Pos (18U)
#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
#define RCC_APB1ENR_USART3EN     RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
#define RCC_APB1ENR_I2C2EN_Pos   (22U)
#define RCC_APB1ENR_I2C2EN_Msk   (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
#define RCC_APB1ENR_I2C2EN       RCC_APB1ENR_I2C2EN_Msk           /*!< I2C 2 clock enable */

#define RCC_APB1ENR_USBEN_Pos (23U)
#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
#define RCC_APB1ENR_USBEN     RCC_APB1ENR_USBEN_Msk           /*!< USB Device clock enable */

/*******************  Bit definition for RCC_BDCR register  *******************/
#define RCC_BDCR_LSEON_Pos  (0U)
#define RCC_BDCR_LSEON_Msk  (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON      RCC_BDCR_LSEON_Msk           /*!< External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY     RCC_BDCR_LSERDY_Msk           /*!< External Low Speed oscillator Ready */
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP     RCC_BDCR_LSEBYP_Msk           /*!< External Low Speed oscillator Bypass */

#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL     RCC_BDCR_RTCSEL_Msk           /*!< RTCSEL[1:0] bits (RTC clock source selection) */
#define RCC_BDCR_RTCSEL_0   (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1   (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */

/*!< RTC congiguration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE     0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI     0x00000200U /*!< LSI oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_HSE     0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */

#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN     RCC_BDCR_RTCEN_Msk           /*!< RTC clock enable */
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST     RCC_BDCR_BDRST_Msk           /*!< Backup domain software reset  */

/*******************  Bit definition for RCC_CSR register  ********************/
#define RCC_CSR_LSION_Pos    (0U)
#define RCC_CSR_LSION_Msk    (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION        RCC_CSR_LSION_Msk           /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY_Pos   (1U)
#define RCC_CSR_LSIRDY_Msk   (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY       RCC_CSR_LSIRDY_Msk           /*!< Internal Low Speed oscillator Ready */
#define RCC_CSR_RMVF_Pos     (24U)
#define RCC_CSR_RMVF_Msk     (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
#define RCC_CSR_RMVF         RCC_CSR_RMVF_Msk           /*!< Remove reset flag */
#define RCC_CSR_PINRSTF_Pos  (26U)
#define RCC_CSR_PINRSTF_Msk  (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF      RCC_CSR_PINRSTF_Msk           /*!< PIN reset flag */
#define RCC_CSR_PORRSTF_Pos  (27U)
#define RCC_CSR_PORRSTF_Msk  (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_PORRSTF      RCC_CSR_PORRSTF_Msk           /*!< POR/PDR reset flag */
#define RCC_CSR_SFTRSTF_Pos  (28U)
#define RCC_CSR_SFTRSTF_Msk  (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF      RCC_CSR_SFTRSTF_Msk           /*!< Software Reset flag */
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF     RCC_CSR_IWDGRSTF_Msk           /*!< Independent Watchdog reset flag */
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF     RCC_CSR_WWDGRSTF_Msk           /*!< Window watchdog reset flag */
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF     RCC_CSR_LPWRRSTF_Msk           /*!< Low-Power reset flag */

/******************************************************************************/
/*                                                                            */
/*                General Purpose and Alternate Function I/O                  */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for GPIO_CRL register  *******************/
#define GPIO_CRL_MODE_Pos (0U)
#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
#define GPIO_CRL_MODE     GPIO_CRL_MODE_Msk                  /*!< Port x mode bits */

#define GPIO_CRL_MODE0_Pos (0U)
#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_CRL_MODE0     GPIO_CRL_MODE0_Msk           /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
#define GPIO_CRL_MODE0_0   (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_CRL_MODE0_1   (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */

#define GPIO_CRL_MODE1_Pos (4U)
#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
#define GPIO_CRL_MODE1     GPIO_CRL_MODE1_Msk           /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
#define GPIO_CRL_MODE1_0   (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
#define GPIO_CRL_MODE1_1   (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */

#define GPIO_CRL_MODE2_Pos (8U)
#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
#define GPIO_CRL_MODE2     GPIO_CRL_MODE2_Msk           /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
#define GPIO_CRL_MODE2_0   (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
#define GPIO_CRL_MODE2_1   (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */

#define GPIO_CRL_MODE3_Pos (12U)
#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
#define GPIO_CRL_MODE3     GPIO_CRL_MODE3_Msk           /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
#define GPIO_CRL_MODE3_0   (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
#define GPIO_CRL_MODE3_1   (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */

#define GPIO_CRL_MODE4_Pos (16U)
#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
#define GPIO_CRL_MODE4     GPIO_CRL_MODE4_Msk           /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
#define GPIO_CRL_MODE4_0   (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
#define GPIO_CRL_MODE4_1   (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */

#define GPIO_CRL_MODE5_Pos (20U)
#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
#define GPIO_CRL_MODE5     GPIO_CRL_MODE5_Msk           /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
#define GPIO_CRL_MODE5_0   (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
#define GPIO_CRL_MODE5_1   (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */

#define GPIO_CRL_MODE6_Pos (24U)
#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
#define GPIO_CRL_MODE6     GPIO_CRL_MODE6_Msk           /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
#define GPIO_CRL_MODE6_0   (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
#define GPIO_CRL_MODE6_1   (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */

#define GPIO_CRL_MODE7_Pos (28U)
#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
#define GPIO_CRL_MODE7     GPIO_CRL_MODE7_Msk           /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
#define GPIO_CRL_MODE7_0   (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
#define GPIO_CRL_MODE7_1   (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */

#define GPIO_CRL_CNF_Pos (2U)
#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
#define GPIO_CRL_CNF     GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */

#define GPIO_CRL_CNF0_Pos (2U)
#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
#define GPIO_CRL_CNF0     GPIO_CRL_CNF0_Msk           /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
#define GPIO_CRL_CNF0_0   (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
#define GPIO_CRL_CNF0_1   (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */

#define GPIO_CRL_CNF1_Pos (6U)
#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
#define GPIO_CRL_CNF1     GPIO_CRL_CNF1_Msk           /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
#define GPIO_CRL_CNF1_0   (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
#define GPIO_CRL_CNF1_1   (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */

#define GPIO_CRL_CNF2_Pos (10U)
#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
#define GPIO_CRL_CNF2     GPIO_CRL_CNF2_Msk           /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
#define GPIO_CRL_CNF2_0   (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
#define GPIO_CRL_CNF2_1   (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */

#define GPIO_CRL_CNF3_Pos (14U)
#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
#define GPIO_CRL_CNF3     GPIO_CRL_CNF3_Msk           /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
#define GPIO_CRL_CNF3_0   (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
#define GPIO_CRL_CNF3_1   (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */

#define GPIO_CRL_CNF4_Pos (18U)
#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
#define GPIO_CRL_CNF4     GPIO_CRL_CNF4_Msk           /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
#define GPIO_CRL_CNF4_0   (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
#define GPIO_CRL_CNF4_1   (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */

#define GPIO_CRL_CNF5_Pos (22U)
#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
#define GPIO_CRL_CNF5     GPIO_CRL_CNF5_Msk           /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
#define GPIO_CRL_CNF5_0   (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
#define GPIO_CRL_CNF5_1   (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */

#define GPIO_CRL_CNF6_Pos (26U)
#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
#define GPIO_CRL_CNF6     GPIO_CRL_CNF6_Msk           /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
#define GPIO_CRL_CNF6_0   (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
#define GPIO_CRL_CNF6_1   (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */

#define GPIO_CRL_CNF7_Pos (30U)
#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
#define GPIO_CRL_CNF7     GPIO_CRL_CNF7_Msk           /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
#define GPIO_CRL_CNF7_0   (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
#define GPIO_CRL_CNF7_1   (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */

/*******************  Bit definition for GPIO_CRH register  *******************/
#define GPIO_CRH_MODE_Pos (0U)
#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
#define GPIO_CRH_MODE     GPIO_CRH_MODE_Msk                  /*!< Port x mode bits */

#define GPIO_CRH_MODE8_Pos (0U)
#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
#define GPIO_CRH_MODE8     GPIO_CRH_MODE8_Msk           /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
#define GPIO_CRH_MODE8_0   (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
#define GPIO_CRH_MODE8_1   (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */

#define GPIO_CRH_MODE9_Pos (4U)
#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
#define GPIO_CRH_MODE9     GPIO_CRH_MODE9_Msk           /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
#define GPIO_CRH_MODE9_0   (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
#define GPIO_CRH_MODE9_1   (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */

#define GPIO_CRH_MODE10_Pos (8U)
#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
#define GPIO_CRH_MODE10     GPIO_CRH_MODE10_Msk           /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
#define GPIO_CRH_MODE10_0   (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
#define GPIO_CRH_MODE10_1   (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */

#define GPIO_CRH_MODE11_Pos (12U)
#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
#define GPIO_CRH_MODE11     GPIO_CRH_MODE11_Msk           /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
#define GPIO_CRH_MODE11_0   (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
#define GPIO_CRH_MODE11_1   (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */

#define GPIO_CRH_MODE12_Pos (16U)
#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
#define GPIO_CRH_MODE12     GPIO_CRH_MODE12_Msk           /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
#define GPIO_CRH_MODE12_0   (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
#define GPIO_CRH_MODE12_1   (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */

#define GPIO_CRH_MODE13_Pos (20U)
#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
#define GPIO_CRH_MODE13     GPIO_CRH_MODE13_Msk           /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
#define GPIO_CRH_MODE13_0   (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
#define GPIO_CRH_MODE13_1   (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */

#define GPIO_CRH_MODE14_Pos (24U)
#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
#define GPIO_CRH_MODE14     GPIO_CRH_MODE14_Msk           /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
#define GPIO_CRH_MODE14_0   (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
#define GPIO_CRH_MODE14_1   (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */

#define GPIO_CRH_MODE15_Pos (28U)
#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
#define GPIO_CRH_MODE15     GPIO_CRH_MODE15_Msk           /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
#define GPIO_CRH_MODE15_0   (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
#define GPIO_CRH_MODE15_1   (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */

#define GPIO_CRH_CNF_Pos (2U)
#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
#define GPIO_CRH_CNF     GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */

#define GPIO_CRH_CNF8_Pos (2U)
#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
#define GPIO_CRH_CNF8     GPIO_CRH_CNF8_Msk           /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
#define GPIO_CRH_CNF8_0   (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
#define GPIO_CRH_CNF8_1   (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */

#define GPIO_CRH_CNF9_Pos (6U)
#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
#define GPIO_CRH_CNF9     GPIO_CRH_CNF9_Msk           /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
#define GPIO_CRH_CNF9_0   (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
#define GPIO_CRH_CNF9_1   (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */

#define GPIO_CRH_CNF10_Pos (10U)
#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
#define GPIO_CRH_CNF10     GPIO_CRH_CNF10_Msk           /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
#define GPIO_CRH_CNF10_0   (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
#define GPIO_CRH_CNF10_1   (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */

#define GPIO_CRH_CNF11_Pos (14U)
#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
#define GPIO_CRH_CNF11     GPIO_CRH_CNF11_Msk           /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
#define GPIO_CRH_CNF11_0   (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
#define GPIO_CRH_CNF11_1   (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */

#define GPIO_CRH_CNF12_Pos (18U)
#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
#define GPIO_CRH_CNF12     GPIO_CRH_CNF12_Msk           /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
#define GPIO_CRH_CNF12_0   (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
#define GPIO_CRH_CNF12_1   (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */

#define GPIO_CRH_CNF13_Pos (22U)
#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
#define GPIO_CRH_CNF13     GPIO_CRH_CNF13_Msk           /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
#define GPIO_CRH_CNF13_0   (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
#define GPIO_CRH_CNF13_1   (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */

#define GPIO_CRH_CNF14_Pos (26U)
#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
#define GPIO_CRH_CNF14     GPIO_CRH_CNF14_Msk           /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
#define GPIO_CRH_CNF14_0   (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
#define GPIO_CRH_CNF14_1   (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */

#define GPIO_CRH_CNF15_Pos (30U)
#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
#define GPIO_CRH_CNF15     GPIO_CRH_CNF15_Msk           /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
#define GPIO_CRH_CNF15_0   (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
#define GPIO_CRH_CNF15_1   (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */

/*!<******************  Bit definition for GPIO_IDR register  *******************/
#define GPIO_IDR_IDR0_Pos  (0U)
#define GPIO_IDR_IDR0_Msk  (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_IDR0      GPIO_IDR_IDR0_Msk           /*!< Port input data, bit 0 */
#define GPIO_IDR_IDR1_Pos  (1U)
#define GPIO_IDR_IDR1_Msk  (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_IDR1      GPIO_IDR_IDR1_Msk           /*!< Port input data, bit 1 */
#define GPIO_IDR_IDR2_Pos  (2U)
#define GPIO_IDR_IDR2_Msk  (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_IDR2      GPIO_IDR_IDR2_Msk           /*!< Port input data, bit 2 */
#define GPIO_IDR_IDR3_Pos  (3U)
#define GPIO_IDR_IDR3_Msk  (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_IDR3      GPIO_IDR_IDR3_Msk           /*!< Port input data, bit 3 */
#define GPIO_IDR_IDR4_Pos  (4U)
#define GPIO_IDR_IDR4_Msk  (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_IDR4      GPIO_IDR_IDR4_Msk           /*!< Port input data, bit 4 */
#define GPIO_IDR_IDR5_Pos  (5U)
#define GPIO_IDR_IDR5_Msk  (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_IDR5      GPIO_IDR_IDR5_Msk           /*!< Port input data, bit 5 */
#define GPIO_IDR_IDR6_Pos  (6U)
#define GPIO_IDR_IDR6_Msk  (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_IDR6      GPIO_IDR_IDR6_Msk           /*!< Port input data, bit 6 */
#define GPIO_IDR_IDR7_Pos  (7U)
#define GPIO_IDR_IDR7_Msk  (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_IDR7      GPIO_IDR_IDR7_Msk           /*!< Port input data, bit 7 */
#define GPIO_IDR_IDR8_Pos  (8U)
#define GPIO_IDR_IDR8_Msk  (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_IDR8      GPIO_IDR_IDR8_Msk           /*!< Port input data, bit 8 */
#define GPIO_IDR_IDR9_Pos  (9U)
#define GPIO_IDR_IDR9_Msk  (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_IDR9      GPIO_IDR_IDR9_Msk           /*!< Port input data, bit 9 */
#define GPIO_IDR_IDR10_Pos (10U)
#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_IDR10     GPIO_IDR_IDR10_Msk           /*!< Port input data, bit 10 */
#define GPIO_IDR_IDR11_Pos (11U)
#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_IDR11     GPIO_IDR_IDR11_Msk           /*!< Port input data, bit 11 */
#define GPIO_IDR_IDR12_Pos (12U)
#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_IDR12     GPIO_IDR_IDR12_Msk           /*!< Port input data, bit 12 */
#define GPIO_IDR_IDR13_Pos (13U)
#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_IDR13     GPIO_IDR_IDR13_Msk           /*!< Port input data, bit 13 */
#define GPIO_IDR_IDR14_Pos (14U)
#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_IDR14     GPIO_IDR_IDR14_Msk           /*!< Port input data, bit 14 */
#define GPIO_IDR_IDR15_Pos (15U)
#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_IDR15     GPIO_IDR_IDR15_Msk           /*!< Port input data, bit 15 */

/*******************  Bit definition for GPIO_ODR register  *******************/
#define GPIO_ODR_ODR0_Pos  (0U)
#define GPIO_ODR_ODR0_Msk  (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_ODR0      GPIO_ODR_ODR0_Msk           /*!< Port output data, bit 0 */
#define GPIO_ODR_ODR1_Pos  (1U)
#define GPIO_ODR_ODR1_Msk  (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_ODR1      GPIO_ODR_ODR1_Msk           /*!< Port output data, bit 1 */
#define GPIO_ODR_ODR2_Pos  (2U)
#define GPIO_ODR_ODR2_Msk  (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_ODR2      GPIO_ODR_ODR2_Msk           /*!< Port output data, bit 2 */
#define GPIO_ODR_ODR3_Pos  (3U)
#define GPIO_ODR_ODR3_Msk  (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_ODR3      GPIO_ODR_ODR3_Msk           /*!< Port output data, bit 3 */
#define GPIO_ODR_ODR4_Pos  (4U)
#define GPIO_ODR_ODR4_Msk  (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_ODR4      GPIO_ODR_ODR4_Msk           /*!< Port output data, bit 4 */
#define GPIO_ODR_ODR5_Pos  (5U)
#define GPIO_ODR_ODR5_Msk  (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_ODR5      GPIO_ODR_ODR5_Msk           /*!< Port output data, bit 5 */
#define GPIO_ODR_ODR6_Pos  (6U)
#define GPIO_ODR_ODR6_Msk  (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_ODR6      GPIO_ODR_ODR6_Msk           /*!< Port output data, bit 6 */
#define GPIO_ODR_ODR7_Pos  (7U)
#define GPIO_ODR_ODR7_Msk  (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_ODR7      GPIO_ODR_ODR7_Msk           /*!< Port output data, bit 7 */
#define GPIO_ODR_ODR8_Pos  (8U)
#define GPIO_ODR_ODR8_Msk  (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_ODR8      GPIO_ODR_ODR8_Msk           /*!< Port output data, bit 8 */
#define GPIO_ODR_ODR9_Pos  (9U)
#define GPIO_ODR_ODR9_Msk  (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_ODR9      GPIO_ODR_ODR9_Msk           /*!< Port output data, bit 9 */
#define GPIO_ODR_ODR10_Pos (10U)
#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_ODR10     GPIO_ODR_ODR10_Msk           /*!< Port output data, bit 10 */
#define GPIO_ODR_ODR11_Pos (11U)
#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_ODR11     GPIO_ODR_ODR11_Msk           /*!< Port output data, bit 11 */
#define GPIO_ODR_ODR12_Pos (12U)
#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_ODR12     GPIO_ODR_ODR12_Msk           /*!< Port output data, bit 12 */
#define GPIO_ODR_ODR13_Pos (13U)
#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_ODR13     GPIO_ODR_ODR13_Msk           /*!< Port output data, bit 13 */
#define GPIO_ODR_ODR14_Pos (14U)
#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_ODR14     GPIO_ODR_ODR14_Msk           /*!< Port output data, bit 14 */
#define GPIO_ODR_ODR15_Pos (15U)
#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_ODR15     GPIO_ODR_ODR15_Msk           /*!< Port output data, bit 15 */

/******************  Bit definition for GPIO_BSRR register  *******************/
#define GPIO_BSRR_BS0_Pos  (0U)
#define GPIO_BSRR_BS0_Msk  (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0      GPIO_BSRR_BS0_Msk           /*!< Port x Set bit 0 */
#define GPIO_BSRR_BS1_Pos  (1U)
#define GPIO_BSRR_BS1_Msk  (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1      GPIO_BSRR_BS1_Msk           /*!< Port x Set bit 1 */
#define GPIO_BSRR_BS2_Pos  (2U)
#define GPIO_BSRR_BS2_Msk  (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2      GPIO_BSRR_BS2_Msk           /*!< Port x Set bit 2 */
#define GPIO_BSRR_BS3_Pos  (3U)
#define GPIO_BSRR_BS3_Msk  (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3      GPIO_BSRR_BS3_Msk           /*!< Port x Set bit 3 */
#define GPIO_BSRR_BS4_Pos  (4U)
#define GPIO_BSRR_BS4_Msk  (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4      GPIO_BSRR_BS4_Msk           /*!< Port x Set bit 4 */
#define GPIO_BSRR_BS5_Pos  (5U)
#define GPIO_BSRR_BS5_Msk  (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5      GPIO_BSRR_BS5_Msk           /*!< Port x Set bit 5 */
#define GPIO_BSRR_BS6_Pos  (6U)
#define GPIO_BSRR_BS6_Msk  (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6      GPIO_BSRR_BS6_Msk           /*!< Port x Set bit 6 */
#define GPIO_BSRR_BS7_Pos  (7U)
#define GPIO_BSRR_BS7_Msk  (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7      GPIO_BSRR_BS7_Msk           /*!< Port x Set bit 7 */
#define GPIO_BSRR_BS8_Pos  (8U)
#define GPIO_BSRR_BS8_Msk  (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8      GPIO_BSRR_BS8_Msk           /*!< Port x Set bit 8 */
#define GPIO_BSRR_BS9_Pos  (9U)
#define GPIO_BSRR_BS9_Msk  (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9      GPIO_BSRR_BS9_Msk           /*!< Port x Set bit 9 */
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10     GPIO_BSRR_BS10_Msk           /*!< Port x Set bit 10 */
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11     GPIO_BSRR_BS11_Msk           /*!< Port x Set bit 11 */
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12     GPIO_BSRR_BS12_Msk           /*!< Port x Set bit 12 */
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13     GPIO_BSRR_BS13_Msk           /*!< Port x Set bit 13 */
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14     GPIO_BSRR_BS14_Msk           /*!< Port x Set bit 14 */
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15     GPIO_BSRR_BS15_Msk           /*!< Port x Set bit 15 */

#define GPIO_BSRR_BR0_Pos  (16U)
#define GPIO_BSRR_BR0_Msk  (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0      GPIO_BSRR_BR0_Msk           /*!< Port x Reset bit 0 */
#define GPIO_BSRR_BR1_Pos  (17U)
#define GPIO_BSRR_BR1_Msk  (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1      GPIO_BSRR_BR1_Msk           /*!< Port x Reset bit 1 */
#define GPIO_BSRR_BR2_Pos  (18U)
#define GPIO_BSRR_BR2_Msk  (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2      GPIO_BSRR_BR2_Msk           /*!< Port x Reset bit 2 */
#define GPIO_BSRR_BR3_Pos  (19U)
#define GPIO_BSRR_BR3_Msk  (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3      GPIO_BSRR_BR3_Msk           /*!< Port x Reset bit 3 */
#define GPIO_BSRR_BR4_Pos  (20U)
#define GPIO_BSRR_BR4_Msk  (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4      GPIO_BSRR_BR4_Msk           /*!< Port x Reset bit 4 */
#define GPIO_BSRR_BR5_Pos  (21U)
#define GPIO_BSRR_BR5_Msk  (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5      GPIO_BSRR_BR5_Msk           /*!< Port x Reset bit 5 */
#define GPIO_BSRR_BR6_Pos  (22U)
#define GPIO_BSRR_BR6_Msk  (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6      GPIO_BSRR_BR6_Msk           /*!< Port x Reset bit 6 */
#define GPIO_BSRR_BR7_Pos  (23U)
#define GPIO_BSRR_BR7_Msk  (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7      GPIO_BSRR_BR7_Msk           /*!< Port x Reset bit 7 */
#define GPIO_BSRR_BR8_Pos  (24U)
#define GPIO_BSRR_BR8_Msk  (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8      GPIO_BSRR_BR8_Msk           /*!< Port x Reset bit 8 */
#define GPIO_BSRR_BR9_Pos  (25U)
#define GPIO_BSRR_BR9_Msk  (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9      GPIO_BSRR_BR9_Msk           /*!< Port x Reset bit 9 */
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10     GPIO_BSRR_BR10_Msk           /*!< Port x Reset bit 10 */
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11     GPIO_BSRR_BR11_Msk           /*!< Port x Reset bit 11 */
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12     GPIO_BSRR_BR12_Msk           /*!< Port x Reset bit 12 */
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13     GPIO_BSRR_BR13_Msk           /*!< Port x Reset bit 13 */
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14     GPIO_BSRR_BR14_Msk           /*!< Port x Reset bit 14 */
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15     GPIO_BSRR_BR15_Msk           /*!< Port x Reset bit 15 */

/*******************  Bit definition for GPIO_BRR register  *******************/
#define GPIO_BRR_BR0_Pos  (0U)
#define GPIO_BRR_BR0_Msk  (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0      GPIO_BRR_BR0_Msk           /*!< Port x Reset bit 0 */
#define GPIO_BRR_BR1_Pos  (1U)
#define GPIO_BRR_BR1_Msk  (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1      GPIO_BRR_BR1_Msk           /*!< Port x Reset bit 1 */
#define GPIO_BRR_BR2_Pos  (2U)
#define GPIO_BRR_BR2_Msk  (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2      GPIO_BRR_BR2_Msk           /*!< Port x Reset bit 2 */
#define GPIO_BRR_BR3_Pos  (3U)
#define GPIO_BRR_BR3_Msk  (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3      GPIO_BRR_BR3_Msk           /*!< Port x Reset bit 3 */
#define GPIO_BRR_BR4_Pos  (4U)
#define GPIO_BRR_BR4_Msk  (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4      GPIO_BRR_BR4_Msk           /*!< Port x Reset bit 4 */
#define GPIO_BRR_BR5_Pos  (5U)
#define GPIO_BRR_BR5_Msk  (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5      GPIO_BRR_BR5_Msk           /*!< Port x Reset bit 5 */
#define GPIO_BRR_BR6_Pos  (6U)
#define GPIO_BRR_BR6_Msk  (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6      GPIO_BRR_BR6_Msk           /*!< Port x Reset bit 6 */
#define GPIO_BRR_BR7_Pos  (7U)
#define GPIO_BRR_BR7_Msk  (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7      GPIO_BRR_BR7_Msk           /*!< Port x Reset bit 7 */
#define GPIO_BRR_BR8_Pos  (8U)
#define GPIO_BRR_BR8_Msk  (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8      GPIO_BRR_BR8_Msk           /*!< Port x Reset bit 8 */
#define GPIO_BRR_BR9_Pos  (9U)
#define GPIO_BRR_BR9_Msk  (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9      GPIO_BRR_BR9_Msk           /*!< Port x Reset bit 9 */
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10     GPIO_BRR_BR10_Msk           /*!< Port x Reset bit 10 */
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11     GPIO_BRR_BR11_Msk           /*!< Port x Reset bit 11 */
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12     GPIO_BRR_BR12_Msk           /*!< Port x Reset bit 12 */
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13     GPIO_BRR_BR13_Msk           /*!< Port x Reset bit 13 */
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14     GPIO_BRR_BR14_Msk           /*!< Port x Reset bit 14 */
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15     GPIO_BRR_BR15_Msk           /*!< Port x Reset bit 15 */

/******************  Bit definition for GPIO_LCKR register  *******************/
#define GPIO_LCKR_LCK0_Pos  (0U)
#define GPIO_LCKR_LCK0_Msk  (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0      GPIO_LCKR_LCK0_Msk           /*!< Port x Lock bit 0 */
#define GPIO_LCKR_LCK1_Pos  (1U)
#define GPIO_LCKR_LCK1_Msk  (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1      GPIO_LCKR_LCK1_Msk           /*!< Port x Lock bit 1 */
#define GPIO_LCKR_LCK2_Pos  (2U)
#define GPIO_LCKR_LCK2_Msk  (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2      GPIO_LCKR_LCK2_Msk           /*!< Port x Lock bit 2 */
#define GPIO_LCKR_LCK3_Pos  (3U)
#define GPIO_LCKR_LCK3_Msk  (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3      GPIO_LCKR_LCK3_Msk           /*!< Port x Lock bit 3 */
#define GPIO_LCKR_LCK4_Pos  (4U)
#define GPIO_LCKR_LCK4_Msk  (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4      GPIO_LCKR_LCK4_Msk           /*!< Port x Lock bit 4 */
#define GPIO_LCKR_LCK5_Pos  (5U)
#define GPIO_LCKR_LCK5_Msk  (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5      GPIO_LCKR_LCK5_Msk           /*!< Port x Lock bit 5 */
#define GPIO_LCKR_LCK6_Pos  (6U)
#define GPIO_LCKR_LCK6_Msk  (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6      GPIO_LCKR_LCK6_Msk           /*!< Port x Lock bit 6 */
#define GPIO_LCKR_LCK7_Pos  (7U)
#define GPIO_LCKR_LCK7_Msk  (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7      GPIO_LCKR_LCK7_Msk           /*!< Port x Lock bit 7 */
#define GPIO_LCKR_LCK8_Pos  (8U)
#define GPIO_LCKR_LCK8_Msk  (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8      GPIO_LCKR_LCK8_Msk           /*!< Port x Lock bit 8 */
#define GPIO_LCKR_LCK9_Pos  (9U)
#define GPIO_LCKR_LCK9_Msk  (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9      GPIO_LCKR_LCK9_Msk           /*!< Port x Lock bit 9 */
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10     GPIO_LCKR_LCK10_Msk           /*!< Port x Lock bit 10 */
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11     GPIO_LCKR_LCK11_Msk           /*!< Port x Lock bit 11 */
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12     GPIO_LCKR_LCK12_Msk           /*!< Port x Lock bit 12 */
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13     GPIO_LCKR_LCK13_Msk           /*!< Port x Lock bit 13 */
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14     GPIO_LCKR_LCK14_Msk           /*!< Port x Lock bit 14 */
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15     GPIO_LCKR_LCK15_Msk           /*!< Port x Lock bit 15 */
#define GPIO_LCKR_LCKK_Pos  (16U)
#define GPIO_LCKR_LCKK_Msk  (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK      GPIO_LCKR_LCKK_Msk           /*!< Lock key */

/*----------------------------------------------------------------------------*/

/******************  Bit definition for AFIO_EVCR register  *******************/
#define AFIO_EVCR_PIN_Pos (0U)
#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
#define AFIO_EVCR_PIN     AFIO_EVCR_PIN_Msk           /*!< PIN[3:0] bits (Pin selection) */
#define AFIO_EVCR_PIN_0   (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_1   (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
#define AFIO_EVCR_PIN_2   (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
#define AFIO_EVCR_PIN_3   (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */

/*!< PIN configuration */
#define AFIO_EVCR_PIN_PX0      0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos  (0U)
#define AFIO_EVCR_PIN_PX1_Msk  (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1      AFIO_EVCR_PIN_PX1_Msk           /*!< Pin 1 selected */
#define AFIO_EVCR_PIN_PX2_Pos  (1U)
#define AFIO_EVCR_PIN_PX2_Msk  (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
#define AFIO_EVCR_PIN_PX2      AFIO_EVCR_PIN_PX2_Msk           /*!< Pin 2 selected */
#define AFIO_EVCR_PIN_PX3_Pos  (0U)
#define AFIO_EVCR_PIN_PX3_Msk  (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
#define AFIO_EVCR_PIN_PX3      AFIO_EVCR_PIN_PX3_Msk           /*!< Pin 3 selected */
#define AFIO_EVCR_PIN_PX4_Pos  (2U)
#define AFIO_EVCR_PIN_PX4_Msk  (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
#define AFIO_EVCR_PIN_PX4      AFIO_EVCR_PIN_PX4_Msk           /*!< Pin 4 selected */
#define AFIO_EVCR_PIN_PX5_Pos  (0U)
#define AFIO_EVCR_PIN_PX5_Msk  (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
#define AFIO_EVCR_PIN_PX5      AFIO_EVCR_PIN_PX5_Msk           /*!< Pin 5 selected */
#define AFIO_EVCR_PIN_PX6_Pos  (1U)
#define AFIO_EVCR_PIN_PX6_Msk  (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
#define AFIO_EVCR_PIN_PX6      AFIO_EVCR_PIN_PX6_Msk           /*!< Pin 6 selected */
#define AFIO_EVCR_PIN_PX7_Pos  (0U)
#define AFIO_EVCR_PIN_PX7_Msk  (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
#define AFIO_EVCR_PIN_PX7      AFIO_EVCR_PIN_PX7_Msk           /*!< Pin 7 selected */
#define AFIO_EVCR_PIN_PX8_Pos  (3U)
#define AFIO_EVCR_PIN_PX8_Msk  (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
#define AFIO_EVCR_PIN_PX8      AFIO_EVCR_PIN_PX8_Msk           /*!< Pin 8 selected */
#define AFIO_EVCR_PIN_PX9_Pos  (0U)
#define AFIO_EVCR_PIN_PX9_Msk  (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
#define AFIO_EVCR_PIN_PX9      AFIO_EVCR_PIN_PX9_Msk           /*!< Pin 9 selected */
#define AFIO_EVCR_PIN_PX10_Pos (1U)
#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
#define AFIO_EVCR_PIN_PX10     AFIO_EVCR_PIN_PX10_Msk           /*!< Pin 10 selected */
#define AFIO_EVCR_PIN_PX11_Pos (0U)
#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
#define AFIO_EVCR_PIN_PX11     AFIO_EVCR_PIN_PX11_Msk           /*!< Pin 11 selected */
#define AFIO_EVCR_PIN_PX12_Pos (2U)
#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
#define AFIO_EVCR_PIN_PX12     AFIO_EVCR_PIN_PX12_Msk           /*!< Pin 12 selected */
#define AFIO_EVCR_PIN_PX13_Pos (0U)
#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
#define AFIO_EVCR_PIN_PX13     AFIO_EVCR_PIN_PX13_Msk           /*!< Pin 13 selected */
#define AFIO_EVCR_PIN_PX14_Pos (1U)
#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
#define AFIO_EVCR_PIN_PX14     AFIO_EVCR_PIN_PX14_Msk           /*!< Pin 14 selected */
#define AFIO_EVCR_PIN_PX15_Pos (0U)
#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
#define AFIO_EVCR_PIN_PX15     AFIO_EVCR_PIN_PX15_Msk           /*!< Pin 15 selected */

#define AFIO_EVCR_PORT_Pos (4U)
#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
#define AFIO_EVCR_PORT     AFIO_EVCR_PORT_Msk           /*!< PORT[2:0] bits (Port selection) */
#define AFIO_EVCR_PORT_0   (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_1   (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
#define AFIO_EVCR_PORT_2   (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */

/*!< PORT configuration */
#define AFIO_EVCR_PORT_PA     0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB     AFIO_EVCR_PORT_PB_Msk           /*!< Port B selected */
#define AFIO_EVCR_PORT_PC_Pos (5U)
#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
#define AFIO_EVCR_PORT_PC     AFIO_EVCR_PORT_PC_Msk           /*!< Port C selected */
#define AFIO_EVCR_PORT_PD_Pos (4U)
#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
#define AFIO_EVCR_PORT_PD     AFIO_EVCR_PORT_PD_Msk           /*!< Port D selected */
#define AFIO_EVCR_PORT_PE_Pos (6U)
#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
#define AFIO_EVCR_PORT_PE     AFIO_EVCR_PORT_PE_Msk           /*!< Port E selected */

#define AFIO_EVCR_EVOE_Pos (7U)
#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
#define AFIO_EVCR_EVOE     AFIO_EVCR_EVOE_Msk           /*!< Event Output Enable */

/******************  Bit definition for AFIO_MAPR register  *******************/
#define AFIO_MAPR_SPI1_REMAP_Pos   (0U)
#define AFIO_MAPR_SPI1_REMAP_Msk   (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
#define AFIO_MAPR_SPI1_REMAP       AFIO_MAPR_SPI1_REMAP_Msk           /*!< SPI1 remapping */
#define AFIO_MAPR_I2C1_REMAP_Pos   (1U)
#define AFIO_MAPR_I2C1_REMAP_Msk   (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
#define AFIO_MAPR_I2C1_REMAP       AFIO_MAPR_I2C1_REMAP_Msk           /*!< I2C1 remapping */
#define AFIO_MAPR_USART1_REMAP_Pos (2U)
#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
#define AFIO_MAPR_USART1_REMAP     AFIO_MAPR_USART1_REMAP_Msk           /*!< USART1 remapping */
#define AFIO_MAPR_USART2_REMAP_Pos (3U)
#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
#define AFIO_MAPR_USART2_REMAP     AFIO_MAPR_USART2_REMAP_Msk           /*!< USART2 remapping */

#define AFIO_MAPR_USART3_REMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
#define AFIO_MAPR_USART3_REMAP     AFIO_MAPR_USART3_REMAP_Msk           /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
#define AFIO_MAPR_USART3_REMAP_0   (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_1   (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */

/* USART3_REMAP configuration */
#define AFIO_MAPR_USART3_REMAP_NOREMAP          0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP     AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk           /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos    (4U)
#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk    (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
#define AFIO_MAPR_USART3_REMAP_FULLREMAP        AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk           /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */

#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
#define AFIO_MAPR_TIM1_REMAP     AFIO_MAPR_TIM1_REMAP_Msk           /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
#define AFIO_MAPR_TIM1_REMAP_0   (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_1   (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */

/*!< TIM1_REMAP configuration */
#define AFIO_MAPR_TIM1_REMAP_NOREMAP          0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP     AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos    (6U)
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk    (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP        AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */

#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
#define AFIO_MAPR_TIM2_REMAP     AFIO_MAPR_TIM2_REMAP_Msk           /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
#define AFIO_MAPR_TIM2_REMAP_0   (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_1   (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */

/*!< TIM2_REMAP configuration */
#define AFIO_MAPR_TIM2_REMAP_NOREMAP           0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1     AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk           /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2     AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk           /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos     (8U)
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk     (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP         AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk           /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */

#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
#define AFIO_MAPR_TIM3_REMAP     AFIO_MAPR_TIM3_REMAP_Msk           /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
#define AFIO_MAPR_TIM3_REMAP_0   (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
#define AFIO_MAPR_TIM3_REMAP_1   (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */

/*!< TIM3_REMAP configuration */
#define AFIO_MAPR_TIM3_REMAP_NOREMAP          0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP     AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk           /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos    (10U)
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk    (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP        AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk           /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */

#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
#define AFIO_MAPR_TIM4_REMAP     AFIO_MAPR_TIM4_REMAP_Msk           /*!< TIM4_REMAP bit (TIM4 remapping) */

#define AFIO_MAPR_CAN_REMAP_Pos (13U)
#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
#define AFIO_MAPR_CAN_REMAP     AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
#define AFIO_MAPR_CAN_REMAP_0   (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
#define AFIO_MAPR_CAN_REMAP_1   (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */

/*!< CAN_REMAP configuration */
#define AFIO_MAPR_CAN_REMAP_REMAP1     0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2     AFIO_MAPR_CAN_REMAP_REMAP2_Msk           /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
#define AFIO_MAPR_CAN_REMAP_REMAP3     AFIO_MAPR_CAN_REMAP_REMAP3_Msk           /*!< CANRX mapped to PD0, CANTX mapped to PD1 */

#define AFIO_MAPR_PD01_REMAP_Pos (15U)
#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
#define AFIO_MAPR_PD01_REMAP     AFIO_MAPR_PD01_REMAP_Msk           /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */

/*!< SWJ_CFG configuration */
#define AFIO_MAPR_SWJ_CFG_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
#define AFIO_MAPR_SWJ_CFG     AFIO_MAPR_SWJ_CFG_Msk           /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
#define AFIO_MAPR_SWJ_CFG_0   (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_1   (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2   (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */

#define AFIO_MAPR_SWJ_CFG_RESET           0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos    (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST        AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk           /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE     AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk           /*!< JTAG-DP Disabled and SW-DP Enabled */
#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos     (26U)
#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk     (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
#define AFIO_MAPR_SWJ_CFG_DISABLE         AFIO_MAPR_SWJ_CFG_DISABLE_Msk           /*!< JTAG-DP Disabled and SW-DP Disabled */

/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
#define AFIO_EXTICR1_EXTI0_Pos (0U)
#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define AFIO_EXTICR1_EXTI0     AFIO_EXTICR1_EXTI0_Msk           /*!< EXTI 0 configuration */
#define AFIO_EXTICR1_EXTI1_Pos (4U)
#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define AFIO_EXTICR1_EXTI1     AFIO_EXTICR1_EXTI1_Msk           /*!< EXTI 1 configuration */
#define AFIO_EXTICR1_EXTI2_Pos (8U)
#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define AFIO_EXTICR1_EXTI2     AFIO_EXTICR1_EXTI2_Msk           /*!< EXTI 2 configuration */
#define AFIO_EXTICR1_EXTI3_Pos (12U)
#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define AFIO_EXTICR1_EXTI3     AFIO_EXTICR1_EXTI3_Msk           /*!< EXTI 3 configuration */

/*!< EXTI0 configuration */
#define AFIO_EXTICR1_EXTI0_PA     0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB     AFIO_EXTICR1_EXTI0_PB_Msk           /*!< PB[0] pin */
#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
#define AFIO_EXTICR1_EXTI0_PC     AFIO_EXTICR1_EXTI0_PC_Msk           /*!< PC[0] pin */
#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
#define AFIO_EXTICR1_EXTI0_PD     AFIO_EXTICR1_EXTI0_PD_Msk           /*!< PD[0] pin */
#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
#define AFIO_EXTICR1_EXTI0_PE     AFIO_EXTICR1_EXTI0_PE_Msk           /*!< PE[0] pin */
#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
#define AFIO_EXTICR1_EXTI0_PF     AFIO_EXTICR1_EXTI0_PF_Msk           /*!< PF[0] pin */
#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
#define AFIO_EXTICR1_EXTI0_PG     AFIO_EXTICR1_EXTI0_PG_Msk           /*!< PG[0] pin */

/*!< EXTI1 configuration */
#define AFIO_EXTICR1_EXTI1_PA     0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB     AFIO_EXTICR1_EXTI1_PB_Msk           /*!< PB[1] pin */
#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
#define AFIO_EXTICR1_EXTI1_PC     AFIO_EXTICR1_EXTI1_PC_Msk           /*!< PC[1] pin */
#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
#define AFIO_EXTICR1_EXTI1_PD     AFIO_EXTICR1_EXTI1_PD_Msk           /*!< PD[1] pin */
#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
#define AFIO_EXTICR1_EXTI1_PE     AFIO_EXTICR1_EXTI1_PE_Msk           /*!< PE[1] pin */
#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
#define AFIO_EXTICR1_EXTI1_PF     AFIO_EXTICR1_EXTI1_PF_Msk           /*!< PF[1] pin */
#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
#define AFIO_EXTICR1_EXTI1_PG     AFIO_EXTICR1_EXTI1_PG_Msk           /*!< PG[1] pin */

/*!< EXTI2 configuration */
#define AFIO_EXTICR1_EXTI2_PA     0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB     AFIO_EXTICR1_EXTI2_PB_Msk           /*!< PB[2] pin */
#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
#define AFIO_EXTICR1_EXTI2_PC     AFIO_EXTICR1_EXTI2_PC_Msk           /*!< PC[2] pin */
#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
#define AFIO_EXTICR1_EXTI2_PD     AFIO_EXTICR1_EXTI2_PD_Msk           /*!< PD[2] pin */
#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
#define AFIO_EXTICR1_EXTI2_PE     AFIO_EXTICR1_EXTI2_PE_Msk           /*!< PE[2] pin */
#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
#define AFIO_EXTICR1_EXTI2_PF     AFIO_EXTICR1_EXTI2_PF_Msk           /*!< PF[2] pin */
#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
#define AFIO_EXTICR1_EXTI2_PG     AFIO_EXTICR1_EXTI2_PG_Msk           /*!< PG[2] pin */

/*!< EXTI3 configuration */
#define AFIO_EXTICR1_EXTI3_PA     0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB     AFIO_EXTICR1_EXTI3_PB_Msk           /*!< PB[3] pin */
#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
#define AFIO_EXTICR1_EXTI3_PC     AFIO_EXTICR1_EXTI3_PC_Msk           /*!< PC[3] pin */
#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
#define AFIO_EXTICR1_EXTI3_PD     AFIO_EXTICR1_EXTI3_PD_Msk           /*!< PD[3] pin */
#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
#define AFIO_EXTICR1_EXTI3_PE     AFIO_EXTICR1_EXTI3_PE_Msk           /*!< PE[3] pin */
#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
#define AFIO_EXTICR1_EXTI3_PF     AFIO_EXTICR1_EXTI3_PF_Msk           /*!< PF[3] pin */
#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
#define AFIO_EXTICR1_EXTI3_PG     AFIO_EXTICR1_EXTI3_PG_Msk           /*!< PG[3] pin */

/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
#define AFIO_EXTICR2_EXTI4_Pos (0U)
#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define AFIO_EXTICR2_EXTI4     AFIO_EXTICR2_EXTI4_Msk           /*!< EXTI 4 configuration */
#define AFIO_EXTICR2_EXTI5_Pos (4U)
#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define AFIO_EXTICR2_EXTI5     AFIO_EXTICR2_EXTI5_Msk           /*!< EXTI 5 configuration */
#define AFIO_EXTICR2_EXTI6_Pos (8U)
#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define AFIO_EXTICR2_EXTI6     AFIO_EXTICR2_EXTI6_Msk           /*!< EXTI 6 configuration */
#define AFIO_EXTICR2_EXTI7_Pos (12U)
#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define AFIO_EXTICR2_EXTI7     AFIO_EXTICR2_EXTI7_Msk           /*!< EXTI 7 configuration */

/*!< EXTI4 configuration */
#define AFIO_EXTICR2_EXTI4_PA     0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB     AFIO_EXTICR2_EXTI4_PB_Msk           /*!< PB[4] pin */
#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
#define AFIO_EXTICR2_EXTI4_PC     AFIO_EXTICR2_EXTI4_PC_Msk           /*!< PC[4] pin */
#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
#define AFIO_EXTICR2_EXTI4_PD     AFIO_EXTICR2_EXTI4_PD_Msk           /*!< PD[4] pin */
#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
#define AFIO_EXTICR2_EXTI4_PE     AFIO_EXTICR2_EXTI4_PE_Msk           /*!< PE[4] pin */
#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
#define AFIO_EXTICR2_EXTI4_PF     AFIO_EXTICR2_EXTI4_PF_Msk           /*!< PF[4] pin */
#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
#define AFIO_EXTICR2_EXTI4_PG     AFIO_EXTICR2_EXTI4_PG_Msk           /*!< PG[4] pin */

/* EXTI5 configuration */
#define AFIO_EXTICR2_EXTI5_PA     0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB     AFIO_EXTICR2_EXTI5_PB_Msk           /*!< PB[5] pin */
#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
#define AFIO_EXTICR2_EXTI5_PC     AFIO_EXTICR2_EXTI5_PC_Msk           /*!< PC[5] pin */
#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
#define AFIO_EXTICR2_EXTI5_PD     AFIO_EXTICR2_EXTI5_PD_Msk           /*!< PD[5] pin */
#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
#define AFIO_EXTICR2_EXTI5_PE     AFIO_EXTICR2_EXTI5_PE_Msk           /*!< PE[5] pin */
#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
#define AFIO_EXTICR2_EXTI5_PF     AFIO_EXTICR2_EXTI5_PF_Msk           /*!< PF[5] pin */
#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
#define AFIO_EXTICR2_EXTI5_PG     AFIO_EXTICR2_EXTI5_PG_Msk           /*!< PG[5] pin */

/*!< EXTI6 configuration */
#define AFIO_EXTICR2_EXTI6_PA     0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB     AFIO_EXTICR2_EXTI6_PB_Msk           /*!< PB[6] pin */
#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
#define AFIO_EXTICR2_EXTI6_PC     AFIO_EXTICR2_EXTI6_PC_Msk           /*!< PC[6] pin */
#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
#define AFIO_EXTICR2_EXTI6_PD     AFIO_EXTICR2_EXTI6_PD_Msk           /*!< PD[6] pin */
#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
#define AFIO_EXTICR2_EXTI6_PE     AFIO_EXTICR2_EXTI6_PE_Msk           /*!< PE[6] pin */
#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
#define AFIO_EXTICR2_EXTI6_PF     AFIO_EXTICR2_EXTI6_PF_Msk           /*!< PF[6] pin */
#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
#define AFIO_EXTICR2_EXTI6_PG     AFIO_EXTICR2_EXTI6_PG_Msk           /*!< PG[6] pin */

/*!< EXTI7 configuration */
#define AFIO_EXTICR2_EXTI7_PA     0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB     AFIO_EXTICR2_EXTI7_PB_Msk           /*!< PB[7] pin */
#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
#define AFIO_EXTICR2_EXTI7_PC     AFIO_EXTICR2_EXTI7_PC_Msk           /*!< PC[7] pin */
#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
#define AFIO_EXTICR2_EXTI7_PD     AFIO_EXTICR2_EXTI7_PD_Msk           /*!< PD[7] pin */
#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
#define AFIO_EXTICR2_EXTI7_PE     AFIO_EXTICR2_EXTI7_PE_Msk           /*!< PE[7] pin */
#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
#define AFIO_EXTICR2_EXTI7_PF     AFIO_EXTICR2_EXTI7_PF_Msk           /*!< PF[7] pin */
#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
#define AFIO_EXTICR2_EXTI7_PG     AFIO_EXTICR2_EXTI7_PG_Msk           /*!< PG[7] pin */

/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
#define AFIO_EXTICR3_EXTI8_Pos  (0U)
#define AFIO_EXTICR3_EXTI8_Msk  (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define AFIO_EXTICR3_EXTI8      AFIO_EXTICR3_EXTI8_Msk           /*!< EXTI 8 configuration */
#define AFIO_EXTICR3_EXTI9_Pos  (4U)
#define AFIO_EXTICR3_EXTI9_Msk  (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define AFIO_EXTICR3_EXTI9      AFIO_EXTICR3_EXTI9_Msk           /*!< EXTI 9 configuration */
#define AFIO_EXTICR3_EXTI10_Pos (8U)
#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define AFIO_EXTICR3_EXTI10     AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */
#define AFIO_EXTICR3_EXTI11_Pos (12U)
#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define AFIO_EXTICR3_EXTI11     AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */

/*!< EXTI8 configuration */
#define AFIO_EXTICR3_EXTI8_PA     0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB     AFIO_EXTICR3_EXTI8_PB_Msk           /*!< PB[8] pin */
#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
#define AFIO_EXTICR3_EXTI8_PC     AFIO_EXTICR3_EXTI8_PC_Msk           /*!< PC[8] pin */
#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
#define AFIO_EXTICR3_EXTI8_PD     AFIO_EXTICR3_EXTI8_PD_Msk           /*!< PD[8] pin */
#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
#define AFIO_EXTICR3_EXTI8_PE     AFIO_EXTICR3_EXTI8_PE_Msk           /*!< PE[8] pin */
#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
#define AFIO_EXTICR3_EXTI8_PF     AFIO_EXTICR3_EXTI8_PF_Msk           /*!< PF[8] pin */
#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
#define AFIO_EXTICR3_EXTI8_PG     AFIO_EXTICR3_EXTI8_PG_Msk           /*!< PG[8] pin */

/*!< EXTI9 configuration */
#define AFIO_EXTICR3_EXTI9_PA     0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB     AFIO_EXTICR3_EXTI9_PB_Msk           /*!< PB[9] pin */
#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
#define AFIO_EXTICR3_EXTI9_PC     AFIO_EXTICR3_EXTI9_PC_Msk           /*!< PC[9] pin */
#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
#define AFIO_EXTICR3_EXTI9_PD     AFIO_EXTICR3_EXTI9_PD_Msk           /*!< PD[9] pin */
#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
#define AFIO_EXTICR3_EXTI9_PE     AFIO_EXTICR3_EXTI9_PE_Msk           /*!< PE[9] pin */
#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
#define AFIO_EXTICR3_EXTI9_PF     AFIO_EXTICR3_EXTI9_PF_Msk           /*!< PF[9] pin */
#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
#define AFIO_EXTICR3_EXTI9_PG     AFIO_EXTICR3_EXTI9_PG_Msk           /*!< PG[9] pin */

/*!< EXTI10 configuration */
#define AFIO_EXTICR3_EXTI10_PA     0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB     AFIO_EXTICR3_EXTI10_PB_Msk           /*!< PB[10] pin */
#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
#define AFIO_EXTICR3_EXTI10_PC     AFIO_EXTICR3_EXTI10_PC_Msk           /*!< PC[10] pin */
#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
#define AFIO_EXTICR3_EXTI10_PD     AFIO_EXTICR3_EXTI10_PD_Msk           /*!< PD[10] pin */
#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
#define AFIO_EXTICR3_EXTI10_PE     AFIO_EXTICR3_EXTI10_PE_Msk           /*!< PE[10] pin */
#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
#define AFIO_EXTICR3_EXTI10_PF     AFIO_EXTICR3_EXTI10_PF_Msk           /*!< PF[10] pin */
#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
#define AFIO_EXTICR3_EXTI10_PG     AFIO_EXTICR3_EXTI10_PG_Msk           /*!< PG[10] pin */

/*!< EXTI11 configuration */
#define AFIO_EXTICR3_EXTI11_PA     0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB     AFIO_EXTICR3_EXTI11_PB_Msk           /*!< PB[11] pin */
#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
#define AFIO_EXTICR3_EXTI11_PC     AFIO_EXTICR3_EXTI11_PC_Msk           /*!< PC[11] pin */
#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
#define AFIO_EXTICR3_EXTI11_PD     AFIO_EXTICR3_EXTI11_PD_Msk           /*!< PD[11] pin */
#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
#define AFIO_EXTICR3_EXTI11_PE     AFIO_EXTICR3_EXTI11_PE_Msk           /*!< PE[11] pin */
#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
#define AFIO_EXTICR3_EXTI11_PF     AFIO_EXTICR3_EXTI11_PF_Msk           /*!< PF[11] pin */
#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
#define AFIO_EXTICR3_EXTI11_PG     AFIO_EXTICR3_EXTI11_PG_Msk           /*!< PG[11] pin */

/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
#define AFIO_EXTICR4_EXTI12_Pos (0U)
#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
#define AFIO_EXTICR4_EXTI12     AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */
#define AFIO_EXTICR4_EXTI13_Pos (4U)
#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
#define AFIO_EXTICR4_EXTI13     AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */
#define AFIO_EXTICR4_EXTI14_Pos (8U)
#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
#define AFIO_EXTICR4_EXTI14     AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */
#define AFIO_EXTICR4_EXTI15_Pos (12U)
#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
#define AFIO_EXTICR4_EXTI15     AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */

/* EXTI12 configuration */
#define AFIO_EXTICR4_EXTI12_PA     0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB     AFIO_EXTICR4_EXTI12_PB_Msk           /*!< PB[12] pin */
#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
#define AFIO_EXTICR4_EXTI12_PC     AFIO_EXTICR4_EXTI12_PC_Msk           /*!< PC[12] pin */
#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
#define AFIO_EXTICR4_EXTI12_PD     AFIO_EXTICR4_EXTI12_PD_Msk           /*!< PD[12] pin */
#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
#define AFIO_EXTICR4_EXTI12_PE     AFIO_EXTICR4_EXTI12_PE_Msk           /*!< PE[12] pin */
#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
#define AFIO_EXTICR4_EXTI12_PF     AFIO_EXTICR4_EXTI12_PF_Msk           /*!< PF[12] pin */
#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
#define AFIO_EXTICR4_EXTI12_PG     AFIO_EXTICR4_EXTI12_PG_Msk           /*!< PG[12] pin */

/* EXTI13 configuration */
#define AFIO_EXTICR4_EXTI13_PA     0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB     AFIO_EXTICR4_EXTI13_PB_Msk           /*!< PB[13] pin */
#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
#define AFIO_EXTICR4_EXTI13_PC     AFIO_EXTICR4_EXTI13_PC_Msk           /*!< PC[13] pin */
#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
#define AFIO_EXTICR4_EXTI13_PD     AFIO_EXTICR4_EXTI13_PD_Msk           /*!< PD[13] pin */
#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
#define AFIO_EXTICR4_EXTI13_PE     AFIO_EXTICR4_EXTI13_PE_Msk           /*!< PE[13] pin */
#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
#define AFIO_EXTICR4_EXTI13_PF     AFIO_EXTICR4_EXTI13_PF_Msk           /*!< PF[13] pin */
#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
#define AFIO_EXTICR4_EXTI13_PG     AFIO_EXTICR4_EXTI13_PG_Msk           /*!< PG[13] pin */

/*!< EXTI14 configuration */
#define AFIO_EXTICR4_EXTI14_PA     0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB     AFIO_EXTICR4_EXTI14_PB_Msk           /*!< PB[14] pin */
#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
#define AFIO_EXTICR4_EXTI14_PC     AFIO_EXTICR4_EXTI14_PC_Msk           /*!< PC[14] pin */
#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
#define AFIO_EXTICR4_EXTI14_PD     AFIO_EXTICR4_EXTI14_PD_Msk           /*!< PD[14] pin */
#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
#define AFIO_EXTICR4_EXTI14_PE     AFIO_EXTICR4_EXTI14_PE_Msk           /*!< PE[14] pin */
#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
#define AFIO_EXTICR4_EXTI14_PF     AFIO_EXTICR4_EXTI14_PF_Msk           /*!< PF[14] pin */
#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
#define AFIO_EXTICR4_EXTI14_PG     AFIO_EXTICR4_EXTI14_PG_Msk           /*!< PG[14] pin */

/*!< EXTI15 configuration */
#define AFIO_EXTICR4_EXTI15_PA     0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB     AFIO_EXTICR4_EXTI15_PB_Msk           /*!< PB[15] pin */
#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
#define AFIO_EXTICR4_EXTI15_PC     AFIO_EXTICR4_EXTI15_PC_Msk           /*!< PC[15] pin */
#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
#define AFIO_EXTICR4_EXTI15_PD     AFIO_EXTICR4_EXTI15_PD_Msk           /*!< PD[15] pin */
#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
#define AFIO_EXTICR4_EXTI15_PE     AFIO_EXTICR4_EXTI15_PE_Msk           /*!< PE[15] pin */
#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
#define AFIO_EXTICR4_EXTI15_PF     AFIO_EXTICR4_EXTI15_PF_Msk           /*!< PF[15] pin */
#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
#define AFIO_EXTICR4_EXTI15_PG     AFIO_EXTICR4_EXTI15_PG_Msk           /*!< PG[15] pin */

/******************  Bit definition for AFIO_MAPR2 register  ******************/

/******************************************************************************/
/*                                                                            */
/*                    External Interrupt/Event Controller                     */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for EXTI_IMR register  *******************/
#define EXTI_IMR_MR0_Pos  (0U)
#define EXTI_IMR_MR0_Msk  (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
#define EXTI_IMR_MR0      EXTI_IMR_MR0_Msk           /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1_Pos  (1U)
#define EXTI_IMR_MR1_Msk  (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
#define EXTI_IMR_MR1      EXTI_IMR_MR1_Msk           /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2_Pos  (2U)
#define EXTI_IMR_MR2_Msk  (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
#define EXTI_IMR_MR2      EXTI_IMR_MR2_Msk           /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3_Pos  (3U)
#define EXTI_IMR_MR3_Msk  (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
#define EXTI_IMR_MR3      EXTI_IMR_MR3_Msk           /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4_Pos  (4U)
#define EXTI_IMR_MR4_Msk  (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
#define EXTI_IMR_MR4      EXTI_IMR_MR4_Msk           /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5_Pos  (5U)
#define EXTI_IMR_MR5_Msk  (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
#define EXTI_IMR_MR5      EXTI_IMR_MR5_Msk           /*!< Interrupt Mask on line 5 */
#define EXTI_IMR_MR6_Pos  (6U)
#define EXTI_IMR_MR6_Msk  (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
#define EXTI_IMR_MR6      EXTI_IMR_MR6_Msk           /*!< Interrupt Mask on line 6 */
#define EXTI_IMR_MR7_Pos  (7U)
#define EXTI_IMR_MR7_Msk  (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
#define EXTI_IMR_MR7      EXTI_IMR_MR7_Msk           /*!< Interrupt Mask on line 7 */
#define EXTI_IMR_MR8_Pos  (8U)
#define EXTI_IMR_MR8_Msk  (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
#define EXTI_IMR_MR8      EXTI_IMR_MR8_Msk           /*!< Interrupt Mask on line 8 */
#define EXTI_IMR_MR9_Pos  (9U)
#define EXTI_IMR_MR9_Msk  (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
#define EXTI_IMR_MR9      EXTI_IMR_MR9_Msk           /*!< Interrupt Mask on line 9 */
#define EXTI_IMR_MR10_Pos (10U)
#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
#define EXTI_IMR_MR10     EXTI_IMR_MR10_Msk           /*!< Interrupt Mask on line 10 */
#define EXTI_IMR_MR11_Pos (11U)
#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
#define EXTI_IMR_MR11     EXTI_IMR_MR11_Msk           /*!< Interrupt Mask on line 11 */
#define EXTI_IMR_MR12_Pos (12U)
#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
#define EXTI_IMR_MR12     EXTI_IMR_MR12_Msk           /*!< Interrupt Mask on line 12 */
#define EXTI_IMR_MR13_Pos (13U)
#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
#define EXTI_IMR_MR13     EXTI_IMR_MR13_Msk           /*!< Interrupt Mask on line 13 */
#define EXTI_IMR_MR14_Pos (14U)
#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
#define EXTI_IMR_MR14     EXTI_IMR_MR14_Msk           /*!< Interrupt Mask on line 14 */
#define EXTI_IMR_MR15_Pos (15U)
#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
#define EXTI_IMR_MR15     EXTI_IMR_MR15_Msk           /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16_Pos (16U)
#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
#define EXTI_IMR_MR16     EXTI_IMR_MR16_Msk           /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17     EXTI_IMR_MR17_Msk           /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18     EXTI_IMR_MR18_Msk           /*!< Interrupt Mask on line 18 */

/* References Defines */
#define EXTI_IMR_IM0  EXTI_IMR_MR0
#define EXTI_IMR_IM1  EXTI_IMR_MR1
#define EXTI_IMR_IM2  EXTI_IMR_MR2
#define EXTI_IMR_IM3  EXTI_IMR_MR3
#define EXTI_IMR_IM4  EXTI_IMR_MR4
#define EXTI_IMR_IM5  EXTI_IMR_MR5
#define EXTI_IMR_IM6  EXTI_IMR_MR6
#define EXTI_IMR_IM7  EXTI_IMR_MR7
#define EXTI_IMR_IM8  EXTI_IMR_MR8
#define EXTI_IMR_IM9  EXTI_IMR_MR9
#define EXTI_IMR_IM10 EXTI_IMR_MR10
#define EXTI_IMR_IM11 EXTI_IMR_MR11
#define EXTI_IMR_IM12 EXTI_IMR_MR12
#define EXTI_IMR_IM13 EXTI_IMR_MR13
#define EXTI_IMR_IM14 EXTI_IMR_MR14
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM   0x0007FFFFU /*!< Interrupt Mask All */

/*******************  Bit definition for EXTI_EMR register  *******************/
#define EXTI_EMR_MR0_Pos  (0U)
#define EXTI_EMR_MR0_Msk  (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
#define EXTI_EMR_MR0      EXTI_EMR_MR0_Msk           /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1_Pos  (1U)
#define EXTI_EMR_MR1_Msk  (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
#define EXTI_EMR_MR1      EXTI_EMR_MR1_Msk           /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2_Pos  (2U)
#define EXTI_EMR_MR2_Msk  (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
#define EXTI_EMR_MR2      EXTI_EMR_MR2_Msk           /*!< Event Mask on line 2 */
#define EXTI_EMR_MR3_Pos  (3U)
#define EXTI_EMR_MR3_Msk  (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
#define EXTI_EMR_MR3      EXTI_EMR_MR3_Msk           /*!< Event Mask on line 3 */
#define EXTI_EMR_MR4_Pos  (4U)
#define EXTI_EMR_MR4_Msk  (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
#define EXTI_EMR_MR4      EXTI_EMR_MR4_Msk           /*!< Event Mask on line 4 */
#define EXTI_EMR_MR5_Pos  (5U)
#define EXTI_EMR_MR5_Msk  (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
#define EXTI_EMR_MR5      EXTI_EMR_MR5_Msk           /*!< Event Mask on line 5 */
#define EXTI_EMR_MR6_Pos  (6U)
#define EXTI_EMR_MR6_Msk  (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
#define EXTI_EMR_MR6      EXTI_EMR_MR6_Msk           /*!< Event Mask on line 6 */
#define EXTI_EMR_MR7_Pos  (7U)
#define EXTI_EMR_MR7_Msk  (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
#define EXTI_EMR_MR7      EXTI_EMR_MR7_Msk           /*!< Event Mask on line 7 */
#define EXTI_EMR_MR8_Pos  (8U)
#define EXTI_EMR_MR8_Msk  (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
#define EXTI_EMR_MR8      EXTI_EMR_MR8_Msk           /*!< Event Mask on line 8 */
#define EXTI_EMR_MR9_Pos  (9U)
#define EXTI_EMR_MR9_Msk  (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
#define EXTI_EMR_MR9      EXTI_EMR_MR9_Msk           /*!< Event Mask on line 9 */
#define EXTI_EMR_MR10_Pos (10U)
#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
#define EXTI_EMR_MR10     EXTI_EMR_MR10_Msk           /*!< Event Mask on line 10 */
#define EXTI_EMR_MR11_Pos (11U)
#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
#define EXTI_EMR_MR11     EXTI_EMR_MR11_Msk           /*!< Event Mask on line 11 */
#define EXTI_EMR_MR12_Pos (12U)
#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
#define EXTI_EMR_MR12     EXTI_EMR_MR12_Msk           /*!< Event Mask on line 12 */
#define EXTI_EMR_MR13_Pos (13U)
#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
#define EXTI_EMR_MR13     EXTI_EMR_MR13_Msk           /*!< Event Mask on line 13 */
#define EXTI_EMR_MR14_Pos (14U)
#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
#define EXTI_EMR_MR14     EXTI_EMR_MR14_Msk           /*!< Event Mask on line 14 */
#define EXTI_EMR_MR15_Pos (15U)
#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
#define EXTI_EMR_MR15     EXTI_EMR_MR15_Msk           /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16_Pos (16U)
#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
#define EXTI_EMR_MR16     EXTI_EMR_MR16_Msk           /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17     EXTI_EMR_MR17_Msk           /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18     EXTI_EMR_MR18_Msk           /*!< Event Mask on line 18 */

/* References Defines */
#define EXTI_EMR_EM0  EXTI_EMR_MR0
#define EXTI_EMR_EM1  EXTI_EMR_MR1
#define EXTI_EMR_EM2  EXTI_EMR_MR2
#define EXTI_EMR_EM3  EXTI_EMR_MR3
#define EXTI_EMR_EM4  EXTI_EMR_MR4
#define EXTI_EMR_EM5  EXTI_EMR_MR5
#define EXTI_EMR_EM6  EXTI_EMR_MR6
#define EXTI_EMR_EM7  EXTI_EMR_MR7
#define EXTI_EMR_EM8  EXTI_EMR_MR8
#define EXTI_EMR_EM9  EXTI_EMR_MR9
#define EXTI_EMR_EM10 EXTI_EMR_MR10
#define EXTI_EMR_EM11 EXTI_EMR_MR11
#define EXTI_EMR_EM12 EXTI_EMR_MR12
#define EXTI_EMR_EM13 EXTI_EMR_MR13
#define EXTI_EMR_EM14 EXTI_EMR_MR14
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18

/******************  Bit definition for EXTI_RTSR register  *******************/
#define EXTI_RTSR_TR0_Pos  (0U)
#define EXTI_RTSR_TR0_Msk  (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR_TR0      EXTI_RTSR_TR0_Msk           /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1_Pos  (1U)
#define EXTI_RTSR_TR1_Msk  (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR_TR1      EXTI_RTSR_TR1_Msk           /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2_Pos  (2U)
#define EXTI_RTSR_TR2_Msk  (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR_TR2      EXTI_RTSR_TR2_Msk           /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR_TR3_Pos  (3U)
#define EXTI_RTSR_TR3_Msk  (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR_TR3      EXTI_RTSR_TR3_Msk           /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR_TR4_Pos  (4U)
#define EXTI_RTSR_TR4_Msk  (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR_TR4      EXTI_RTSR_TR4_Msk           /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR_TR5_Pos  (5U)
#define EXTI_RTSR_TR5_Msk  (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR_TR5      EXTI_RTSR_TR5_Msk           /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR_TR6_Pos  (6U)
#define EXTI_RTSR_TR6_Msk  (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR_TR6      EXTI_RTSR_TR6_Msk           /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR_TR7_Pos  (7U)
#define EXTI_RTSR_TR7_Msk  (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR_TR7      EXTI_RTSR_TR7_Msk           /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR_TR8_Pos  (8U)
#define EXTI_RTSR_TR8_Msk  (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR_TR8      EXTI_RTSR_TR8_Msk           /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR_TR9_Pos  (9U)
#define EXTI_RTSR_TR9_Msk  (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR_TR9      EXTI_RTSR_TR9_Msk           /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR_TR10_Pos (10U)
#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR_TR10     EXTI_RTSR_TR10_Msk           /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR_TR11_Pos (11U)
#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR_TR11     EXTI_RTSR_TR11_Msk           /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR_TR12_Pos (12U)
#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR_TR12     EXTI_RTSR_TR12_Msk           /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR_TR13_Pos (13U)
#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR_TR13     EXTI_RTSR_TR13_Msk           /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR_TR14_Pos (14U)
#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR_TR14     EXTI_RTSR_TR14_Msk           /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR_TR15_Pos (15U)
#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR_TR15     EXTI_RTSR_TR15_Msk           /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16_Pos (16U)
#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR_TR16     EXTI_RTSR_TR16_Msk           /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17     EXTI_RTSR_TR17_Msk           /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18     EXTI_RTSR_TR18_Msk           /*!< Rising trigger event configuration bit of line 18 */

/* References Defines */
#define EXTI_RTSR_RT0  EXTI_RTSR_TR0
#define EXTI_RTSR_RT1  EXTI_RTSR_TR1
#define EXTI_RTSR_RT2  EXTI_RTSR_TR2
#define EXTI_RTSR_RT3  EXTI_RTSR_TR3
#define EXTI_RTSR_RT4  EXTI_RTSR_TR4
#define EXTI_RTSR_RT5  EXTI_RTSR_TR5
#define EXTI_RTSR_RT6  EXTI_RTSR_TR6
#define EXTI_RTSR_RT7  EXTI_RTSR_TR7
#define EXTI_RTSR_RT8  EXTI_RTSR_TR8
#define EXTI_RTSR_RT9  EXTI_RTSR_TR9
#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18

/******************  Bit definition for EXTI_FTSR register  *******************/
#define EXTI_FTSR_TR0_Pos  (0U)
#define EXTI_FTSR_TR0_Msk  (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR_TR0      EXTI_FTSR_TR0_Msk           /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1_Pos  (1U)
#define EXTI_FTSR_TR1_Msk  (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR_TR1      EXTI_FTSR_TR1_Msk           /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2_Pos  (2U)
#define EXTI_FTSR_TR2_Msk  (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR_TR2      EXTI_FTSR_TR2_Msk           /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR_TR3_Pos  (3U)
#define EXTI_FTSR_TR3_Msk  (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR_TR3      EXTI_FTSR_TR3_Msk           /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR_TR4_Pos  (4U)
#define EXTI_FTSR_TR4_Msk  (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR_TR4      EXTI_FTSR_TR4_Msk           /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR_TR5_Pos  (5U)
#define EXTI_FTSR_TR5_Msk  (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR_TR5      EXTI_FTSR_TR5_Msk           /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR_TR6_Pos  (6U)
#define EXTI_FTSR_TR6_Msk  (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR_TR6      EXTI_FTSR_TR6_Msk           /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR_TR7_Pos  (7U)
#define EXTI_FTSR_TR7_Msk  (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR_TR7      EXTI_FTSR_TR7_Msk           /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR_TR8_Pos  (8U)
#define EXTI_FTSR_TR8_Msk  (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR_TR8      EXTI_FTSR_TR8_Msk           /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR_TR9_Pos  (9U)
#define EXTI_FTSR_TR9_Msk  (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR_TR9      EXTI_FTSR_TR9_Msk           /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR_TR10_Pos (10U)
#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR_TR10     EXTI_FTSR_TR10_Msk           /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR_TR11_Pos (11U)
#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR_TR11     EXTI_FTSR_TR11_Msk           /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR_TR12_Pos (12U)
#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR_TR12     EXTI_FTSR_TR12_Msk           /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR_TR13_Pos (13U)
#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR_TR13     EXTI_FTSR_TR13_Msk           /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR_TR14_Pos (14U)
#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR_TR14     EXTI_FTSR_TR14_Msk           /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR_TR15_Pos (15U)
#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR_TR15     EXTI_FTSR_TR15_Msk           /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16_Pos (16U)
#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR_TR16     EXTI_FTSR_TR16_Msk           /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17     EXTI_FTSR_TR17_Msk           /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18     EXTI_FTSR_TR18_Msk           /*!< Falling trigger event configuration bit of line 18 */

/* References Defines */
#define EXTI_FTSR_FT0  EXTI_FTSR_TR0
#define EXTI_FTSR_FT1  EXTI_FTSR_TR1
#define EXTI_FTSR_FT2  EXTI_FTSR_TR2
#define EXTI_FTSR_FT3  EXTI_FTSR_TR3
#define EXTI_FTSR_FT4  EXTI_FTSR_TR4
#define EXTI_FTSR_FT5  EXTI_FTSR_TR5
#define EXTI_FTSR_FT6  EXTI_FTSR_TR6
#define EXTI_FTSR_FT7  EXTI_FTSR_TR7
#define EXTI_FTSR_FT8  EXTI_FTSR_TR8
#define EXTI_FTSR_FT9  EXTI_FTSR_TR9
#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18

/******************  Bit definition for EXTI_SWIER register  ******************/
#define EXTI_SWIER_SWIER0_Pos  (0U)
#define EXTI_SWIER_SWIER0_Msk  (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER_SWIER0      EXTI_SWIER_SWIER0_Msk           /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1_Pos  (1U)
#define EXTI_SWIER_SWIER1_Msk  (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER_SWIER1      EXTI_SWIER_SWIER1_Msk           /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2_Pos  (2U)
#define EXTI_SWIER_SWIER2_Msk  (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER_SWIER2      EXTI_SWIER_SWIER2_Msk           /*!< Software Interrupt on line 2 */
#define EXTI_SWIER_SWIER3_Pos  (3U)
#define EXTI_SWIER_SWIER3_Msk  (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER_SWIER3      EXTI_SWIER_SWIER3_Msk           /*!< Software Interrupt on line 3 */
#define EXTI_SWIER_SWIER4_Pos  (4U)
#define EXTI_SWIER_SWIER4_Msk  (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER_SWIER4      EXTI_SWIER_SWIER4_Msk           /*!< Software Interrupt on line 4 */
#define EXTI_SWIER_SWIER5_Pos  (5U)
#define EXTI_SWIER_SWIER5_Msk  (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER_SWIER5      EXTI_SWIER_SWIER5_Msk           /*!< Software Interrupt on line 5 */
#define EXTI_SWIER_SWIER6_Pos  (6U)
#define EXTI_SWIER_SWIER6_Msk  (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER_SWIER6      EXTI_SWIER_SWIER6_Msk           /*!< Software Interrupt on line 6 */
#define EXTI_SWIER_SWIER7_Pos  (7U)
#define EXTI_SWIER_SWIER7_Msk  (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER_SWIER7      EXTI_SWIER_SWIER7_Msk           /*!< Software Interrupt on line 7 */
#define EXTI_SWIER_SWIER8_Pos  (8U)
#define EXTI_SWIER_SWIER8_Msk  (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER_SWIER8      EXTI_SWIER_SWIER8_Msk           /*!< Software Interrupt on line 8 */
#define EXTI_SWIER_SWIER9_Pos  (9U)
#define EXTI_SWIER_SWIER9_Msk  (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER_SWIER9      EXTI_SWIER_SWIER9_Msk           /*!< Software Interrupt on line 9 */
#define EXTI_SWIER_SWIER10_Pos (10U)
#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER_SWIER10     EXTI_SWIER_SWIER10_Msk           /*!< Software Interrupt on line 10 */
#define EXTI_SWIER_SWIER11_Pos (11U)
#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER_SWIER11     EXTI_SWIER_SWIER11_Msk           /*!< Software Interrupt on line 11 */
#define EXTI_SWIER_SWIER12_Pos (12U)
#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER_SWIER12     EXTI_SWIER_SWIER12_Msk           /*!< Software Interrupt on line 12 */
#define EXTI_SWIER_SWIER13_Pos (13U)
#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER_SWIER13     EXTI_SWIER_SWIER13_Msk           /*!< Software Interrupt on line 13 */
#define EXTI_SWIER_SWIER14_Pos (14U)
#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER_SWIER14     EXTI_SWIER_SWIER14_Msk           /*!< Software Interrupt on line 14 */
#define EXTI_SWIER_SWIER15_Pos (15U)
#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER_SWIER15     EXTI_SWIER_SWIER15_Msk           /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16_Pos (16U)
#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER_SWIER16     EXTI_SWIER_SWIER16_Msk           /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17     EXTI_SWIER_SWIER17_Msk           /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18     EXTI_SWIER_SWIER18_Msk           /*!< Software Interrupt on line 18 */

/* References Defines */
#define EXTI_SWIER_SWI0  EXTI_SWIER_SWIER0
#define EXTI_SWIER_SWI1  EXTI_SWIER_SWIER1
#define EXTI_SWIER_SWI2  EXTI_SWIER_SWIER2
#define EXTI_SWIER_SWI3  EXTI_SWIER_SWIER3
#define EXTI_SWIER_SWI4  EXTI_SWIER_SWIER4
#define EXTI_SWIER_SWI5  EXTI_SWIER_SWIER5
#define EXTI_SWIER_SWI6  EXTI_SWIER_SWIER6
#define EXTI_SWIER_SWI7  EXTI_SWIER_SWIER7
#define EXTI_SWIER_SWI8  EXTI_SWIER_SWIER8
#define EXTI_SWIER_SWI9  EXTI_SWIER_SWIER9
#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

/*******************  Bit definition for EXTI_PR register  ********************/
#define EXTI_PR_PR0_Pos  (0U)
#define EXTI_PR_PR0_Msk  (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
#define EXTI_PR_PR0      EXTI_PR_PR0_Msk           /*!< Pending bit for line 0 */
#define EXTI_PR_PR1_Pos  (1U)
#define EXTI_PR_PR1_Msk  (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
#define EXTI_PR_PR1      EXTI_PR_PR1_Msk           /*!< Pending bit for line 1 */
#define EXTI_PR_PR2_Pos  (2U)
#define EXTI_PR_PR2_Msk  (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
#define EXTI_PR_PR2      EXTI_PR_PR2_Msk           /*!< Pending bit for line 2 */
#define EXTI_PR_PR3_Pos  (3U)
#define EXTI_PR_PR3_Msk  (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
#define EXTI_PR_PR3      EXTI_PR_PR3_Msk           /*!< Pending bit for line 3 */
#define EXTI_PR_PR4_Pos  (4U)
#define EXTI_PR_PR4_Msk  (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
#define EXTI_PR_PR4      EXTI_PR_PR4_Msk           /*!< Pending bit for line 4 */
#define EXTI_PR_PR5_Pos  (5U)
#define EXTI_PR_PR5_Msk  (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
#define EXTI_PR_PR5      EXTI_PR_PR5_Msk           /*!< Pending bit for line 5 */
#define EXTI_PR_PR6_Pos  (6U)
#define EXTI_PR_PR6_Msk  (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
#define EXTI_PR_PR6      EXTI_PR_PR6_Msk           /*!< Pending bit for line 6 */
#define EXTI_PR_PR7_Pos  (7U)
#define EXTI_PR_PR7_Msk  (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
#define EXTI_PR_PR7      EXTI_PR_PR7_Msk           /*!< Pending bit for line 7 */
#define EXTI_PR_PR8_Pos  (8U)
#define EXTI_PR_PR8_Msk  (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
#define EXTI_PR_PR8      EXTI_PR_PR8_Msk           /*!< Pending bit for line 8 */
#define EXTI_PR_PR9_Pos  (9U)
#define EXTI_PR_PR9_Msk  (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
#define EXTI_PR_PR9      EXTI_PR_PR9_Msk           /*!< Pending bit for line 9 */
#define EXTI_PR_PR10_Pos (10U)
#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
#define EXTI_PR_PR10     EXTI_PR_PR10_Msk           /*!< Pending bit for line 10 */
#define EXTI_PR_PR11_Pos (11U)
#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
#define EXTI_PR_PR11     EXTI_PR_PR11_Msk           /*!< Pending bit for line 11 */
#define EXTI_PR_PR12_Pos (12U)
#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
#define EXTI_PR_PR12     EXTI_PR_PR12_Msk           /*!< Pending bit for line 12 */
#define EXTI_PR_PR13_Pos (13U)
#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
#define EXTI_PR_PR13     EXTI_PR_PR13_Msk           /*!< Pending bit for line 13 */
#define EXTI_PR_PR14_Pos (14U)
#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
#define EXTI_PR_PR14     EXTI_PR_PR14_Msk           /*!< Pending bit for line 14 */
#define EXTI_PR_PR15_Pos (15U)
#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
#define EXTI_PR_PR15     EXTI_PR_PR15_Msk           /*!< Pending bit for line 15 */
#define EXTI_PR_PR16_Pos (16U)
#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
#define EXTI_PR_PR16     EXTI_PR_PR16_Msk           /*!< Pending bit for line 16 */
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17     EXTI_PR_PR17_Msk           /*!< Pending bit for line 17 */
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18     EXTI_PR_PR18_Msk           /*!< Pending bit for line 18 */

/* References Defines */
#define EXTI_PR_PIF0  EXTI_PR_PR0
#define EXTI_PR_PIF1  EXTI_PR_PR1
#define EXTI_PR_PIF2  EXTI_PR_PR2
#define EXTI_PR_PIF3  EXTI_PR_PR3
#define EXTI_PR_PIF4  EXTI_PR_PR4
#define EXTI_PR_PIF5  EXTI_PR_PR5
#define EXTI_PR_PIF6  EXTI_PR_PR6
#define EXTI_PR_PIF7  EXTI_PR_PR7
#define EXTI_PR_PIF8  EXTI_PR_PR8
#define EXTI_PR_PIF9  EXTI_PR_PR9
#define EXTI_PR_PIF10 EXTI_PR_PR10
#define EXTI_PR_PIF11 EXTI_PR_PR11
#define EXTI_PR_PIF12 EXTI_PR_PR12
#define EXTI_PR_PIF13 EXTI_PR_PR13
#define EXTI_PR_PIF14 EXTI_PR_PR14
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18

/******************************************************************************/
/*                                                                            */
/*                             DMA Controller                                 */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for DMA_ISR register  ********************/
#define DMA_ISR_GIF1_Pos  (0U)
#define DMA_ISR_GIF1_Msk  (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1      DMA_ISR_GIF1_Msk           /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1     DMA_ISR_TCIF1_Msk           /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1     DMA_ISR_HTIF1_Msk           /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1     DMA_ISR_TEIF1_Msk           /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos  (4U)
#define DMA_ISR_GIF2_Msk  (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2      DMA_ISR_GIF2_Msk           /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2     DMA_ISR_TCIF2_Msk           /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2     DMA_ISR_HTIF2_Msk           /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2     DMA_ISR_TEIF2_Msk           /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos  (8U)
#define DMA_ISR_GIF3_Msk  (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3      DMA_ISR_GIF3_Msk           /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3     DMA_ISR_TCIF3_Msk           /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3     DMA_ISR_HTIF3_Msk           /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3     DMA_ISR_TEIF3_Msk           /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos  (12U)
#define DMA_ISR_GIF4_Msk  (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4      DMA_ISR_GIF4_Msk           /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4     DMA_ISR_TCIF4_Msk           /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4     DMA_ISR_HTIF4_Msk           /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4     DMA_ISR_TEIF4_Msk           /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos  (16U)
#define DMA_ISR_GIF5_Msk  (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5      DMA_ISR_GIF5_Msk           /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5     DMA_ISR_TCIF5_Msk           /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5     DMA_ISR_HTIF5_Msk           /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5     DMA_ISR_TEIF5_Msk           /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos  (20U)
#define DMA_ISR_GIF6_Msk  (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6      DMA_ISR_GIF6_Msk           /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6     DMA_ISR_TCIF6_Msk           /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6     DMA_ISR_HTIF6_Msk           /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6     DMA_ISR_TEIF6_Msk           /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos  (24U)
#define DMA_ISR_GIF7_Msk  (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7      DMA_ISR_GIF7_Msk           /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7     DMA_ISR_TCIF7_Msk           /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7     DMA_ISR_HTIF7_Msk           /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7     DMA_ISR_TEIF7_Msk           /*!< Channel 7 Transfer Error flag */

/*******************  Bit definition for DMA_IFCR register  *******************/
#define DMA_IFCR_CGIF1_Pos  (0U)
#define DMA_IFCR_CGIF1_Msk  (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1      DMA_IFCR_CGIF1_Msk           /*!< Channel 1 Global interrupt clear */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1     DMA_IFCR_CTCIF1_Msk           /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1     DMA_IFCR_CHTIF1_Msk           /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1     DMA_IFCR_CTEIF1_Msk           /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos  (4U)
#define DMA_IFCR_CGIF2_Msk  (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2      DMA_IFCR_CGIF2_Msk           /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2     DMA_IFCR_CTCIF2_Msk           /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2     DMA_IFCR_CHTIF2_Msk           /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2     DMA_IFCR_CTEIF2_Msk           /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos  (8U)
#define DMA_IFCR_CGIF3_Msk  (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3      DMA_IFCR_CGIF3_Msk           /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3     DMA_IFCR_CTCIF3_Msk           /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3     DMA_IFCR_CHTIF3_Msk           /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3     DMA_IFCR_CTEIF3_Msk           /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos  (12U)
#define DMA_IFCR_CGIF4_Msk  (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4      DMA_IFCR_CGIF4_Msk           /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4     DMA_IFCR_CTCIF4_Msk           /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4     DMA_IFCR_CHTIF4_Msk           /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4     DMA_IFCR_CTEIF4_Msk           /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos  (16U)
#define DMA_IFCR_CGIF5_Msk  (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5      DMA_IFCR_CGIF5_Msk           /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5     DMA_IFCR_CTCIF5_Msk           /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5     DMA_IFCR_CHTIF5_Msk           /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5     DMA_IFCR_CTEIF5_Msk           /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos  (20U)
#define DMA_IFCR_CGIF6_Msk  (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6      DMA_IFCR_CGIF6_Msk           /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6     DMA_IFCR_CTCIF6_Msk           /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6     DMA_IFCR_CHTIF6_Msk           /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6     DMA_IFCR_CTEIF6_Msk           /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos  (24U)
#define DMA_IFCR_CGIF7_Msk  (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7      DMA_IFCR_CGIF7_Msk           /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7     DMA_IFCR_CTCIF7_Msk           /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7     DMA_IFCR_CHTIF7_Msk           /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7     DMA_IFCR_CTEIF7_Msk           /*!< Channel 7 Transfer Error clear */

/*******************  Bit definition for DMA_CCR register   *******************/
#define DMA_CCR_EN_Pos   (0U)
#define DMA_CCR_EN_Msk   (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN       DMA_CCR_EN_Msk           /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE     DMA_CCR_TCIE_Msk           /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE     DMA_CCR_HTIE_Msk           /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE     DMA_CCR_TEIE_Msk           /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos  (4U)
#define DMA_CCR_DIR_Msk  (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR      DMA_CCR_DIR_Msk           /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC     DMA_CCR_CIRC_Msk           /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC     DMA_CCR_PINC_Msk           /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC     DMA_CCR_MINC_Msk           /*!< Memory increment mode */

#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE     DMA_CCR_PSIZE_Msk           /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0   (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1   (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */

#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE     DMA_CCR_MSIZE_Msk           /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0   (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1   (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */

#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL     DMA_CCR_PL_Msk           /*!< PL[1:0] bits(Channel Priority level) */
#define DMA_CCR_PL_0   (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1   (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */

#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM     DMA_CCR_MEM2MEM_Msk           /*!< Memory to memory mode */

/******************  Bit definition for DMA_CNDTR  register  ******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT     DMA_CNDTR_NDT_Msk              /*!< Number of data to Transfer */

/******************  Bit definition for DMA_CPAR  register  *******************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA     DMA_CPAR_PA_Msk                  /*!< Peripheral Address */

/******************  Bit definition for DMA_CMAR  register  *******************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA     DMA_CMAR_MA_Msk                  /*!< Memory Address */

/******************************************************************************/
/*                                                                            */
/*                      Analog to Digital Converter (ADC)                     */
/*                                                                            */
/******************************************************************************/

/*
 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
 */
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */

/********************  Bit definition for ADC_SR register  ********************/
#define ADC_SR_AWD_Pos   (0U)
#define ADC_SR_AWD_Msk   (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
#define ADC_SR_AWD       ADC_SR_AWD_Msk           /*!< ADC analog watchdog 1 flag */
#define ADC_SR_EOS_Pos   (1U)
#define ADC_SR_EOS_Msk   (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
#define ADC_SR_EOS       ADC_SR_EOS_Msk           /*!< ADC group regular end of sequence conversions flag */
#define ADC_SR_JEOS_Pos  (2U)
#define ADC_SR_JEOS_Msk  (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
#define ADC_SR_JEOS      ADC_SR_JEOS_Msk           /*!< ADC group injected end of sequence conversions flag */
#define ADC_SR_JSTRT_Pos (3U)
#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
#define ADC_SR_JSTRT     ADC_SR_JSTRT_Msk           /*!< ADC group injected conversion start flag */
#define ADC_SR_STRT_Pos  (4U)
#define ADC_SR_STRT_Msk  (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
#define ADC_SR_STRT      ADC_SR_STRT_Msk           /*!< ADC group regular conversion start flag */

/* Legacy defines */
#define ADC_SR_EOC  (ADC_SR_EOS)
#define ADC_SR_JEOC (ADC_SR_JEOS)

/*******************  Bit definition for ADC_CR1 register  ********************/
#define ADC_CR1_AWDCH_Pos (0U)
#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
#define ADC_CR1_AWDCH     ADC_CR1_AWDCH_Msk            /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CR1_AWDCH_0   (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
#define ADC_CR1_AWDCH_1   (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
#define ADC_CR1_AWDCH_2   (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
#define ADC_CR1_AWDCH_3   (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
#define ADC_CR1_AWDCH_4   (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */

#define ADC_CR1_EOSIE_Pos   (5U)
#define ADC_CR1_EOSIE_Msk   (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
#define ADC_CR1_EOSIE       ADC_CR1_EOSIE_Msk           /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_CR1_AWDIE_Pos   (6U)
#define ADC_CR1_AWDIE_Msk   (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
#define ADC_CR1_AWDIE       ADC_CR1_AWDIE_Msk           /*!< ADC analog watchdog 1 interrupt */
#define ADC_CR1_JEOSIE_Pos  (7U)
#define ADC_CR1_JEOSIE_Msk  (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
#define ADC_CR1_JEOSIE      ADC_CR1_JEOSIE_Msk           /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_CR1_SCAN_Pos    (8U)
#define ADC_CR1_SCAN_Msk    (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
#define ADC_CR1_SCAN        ADC_CR1_SCAN_Msk           /*!< ADC scan mode */
#define ADC_CR1_AWDSGL_Pos  (9U)
#define ADC_CR1_AWDSGL_Msk  (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
#define ADC_CR1_AWDSGL      ADC_CR1_AWDSGL_Msk           /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CR1_JAUTO_Pos   (10U)
#define ADC_CR1_JAUTO_Msk   (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
#define ADC_CR1_JAUTO       ADC_CR1_JAUTO_Msk           /*!< ADC group injected automatic trigger mode */
#define ADC_CR1_DISCEN_Pos  (11U)
#define ADC_CR1_DISCEN_Msk  (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
#define ADC_CR1_DISCEN      ADC_CR1_DISCEN_Msk           /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CR1_JDISCEN_Pos (12U)
#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
#define ADC_CR1_JDISCEN     ADC_CR1_JDISCEN_Msk           /*!< ADC group injected sequencer discontinuous mode */

#define ADC_CR1_DISCNUM_Pos (13U)
#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
#define ADC_CR1_DISCNUM     ADC_CR1_DISCNUM_Msk           /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CR1_DISCNUM_0   (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
#define ADC_CR1_DISCNUM_1   (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
#define ADC_CR1_DISCNUM_2   (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */

#define ADC_CR1_DUALMOD_Pos (16U)
#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
#define ADC_CR1_DUALMOD     ADC_CR1_DUALMOD_Msk           /*!< ADC multimode mode selection */
#define ADC_CR1_DUALMOD_0   (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
#define ADC_CR1_DUALMOD_1   (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
#define ADC_CR1_DUALMOD_2   (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
#define ADC_CR1_DUALMOD_3   (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */

#define ADC_CR1_JAWDEN_Pos (22U)
#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
#define ADC_CR1_JAWDEN     ADC_CR1_JAWDEN_Msk           /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CR1_AWDEN_Pos  (23U)
#define ADC_CR1_AWDEN_Msk  (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
#define ADC_CR1_AWDEN      ADC_CR1_AWDEN_Msk           /*!< ADC analog watchdog 1 enable on scope ADC group regular */

/* Legacy defines */
#define ADC_CR1_EOCIE  (ADC_CR1_EOSIE)
#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)

/*******************  Bit definition for ADC_CR2 register  ********************/
#define ADC_CR2_ADON_Pos   (0U)
#define ADC_CR2_ADON_Msk   (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
#define ADC_CR2_ADON       ADC_CR2_ADON_Msk           /*!< ADC enable */
#define ADC_CR2_CONT_Pos   (1U)
#define ADC_CR2_CONT_Msk   (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
#define ADC_CR2_CONT       ADC_CR2_CONT_Msk           /*!< ADC group regular continuous conversion mode */
#define ADC_CR2_CAL_Pos    (2U)
#define ADC_CR2_CAL_Msk    (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
#define ADC_CR2_CAL        ADC_CR2_CAL_Msk           /*!< ADC calibration start */
#define ADC_CR2_RSTCAL_Pos (3U)
#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
#define ADC_CR2_RSTCAL     ADC_CR2_RSTCAL_Msk           /*!< ADC calibration reset */
#define ADC_CR2_DMA_Pos    (8U)
#define ADC_CR2_DMA_Msk    (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
#define ADC_CR2_DMA        ADC_CR2_DMA_Msk           /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos  (11U)
#define ADC_CR2_ALIGN_Msk  (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN      ADC_CR2_ALIGN_Msk           /*!< ADC data alignement */

#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
#define ADC_CR2_JEXTSEL     ADC_CR2_JEXTSEL_Msk           /*!< ADC group injected external trigger source */
#define ADC_CR2_JEXTSEL_0   (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
#define ADC_CR2_JEXTSEL_1   (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
#define ADC_CR2_JEXTSEL_2   (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */

#define ADC_CR2_JEXTTRIG_Pos (15U)
#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
#define ADC_CR2_JEXTTRIG     ADC_CR2_JEXTTRIG_Msk           /*!< ADC group injected external trigger enable */

#define ADC_CR2_EXTSEL_Pos (17U)
#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
#define ADC_CR2_EXTSEL     ADC_CR2_EXTSEL_Msk           /*!< ADC group regular external trigger source */
#define ADC_CR2_EXTSEL_0   (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
#define ADC_CR2_EXTSEL_1   (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
#define ADC_CR2_EXTSEL_2   (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */

#define ADC_CR2_EXTTRIG_Pos  (20U)
#define ADC_CR2_EXTTRIG_Msk  (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
#define ADC_CR2_EXTTRIG      ADC_CR2_EXTTRIG_Msk           /*!< ADC group regular external trigger enable */
#define ADC_CR2_JSWSTART_Pos (21U)
#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
#define ADC_CR2_JSWSTART     ADC_CR2_JSWSTART_Msk           /*!< ADC group injected conversion start */
#define ADC_CR2_SWSTART_Pos  (22U)
#define ADC_CR2_SWSTART_Msk  (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
#define ADC_CR2_SWSTART      ADC_CR2_SWSTART_Msk           /*!< ADC group regular conversion start */
#define ADC_CR2_TSVREFE_Pos  (23U)
#define ADC_CR2_TSVREFE_Msk  (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
#define ADC_CR2_TSVREFE      ADC_CR2_TSVREFE_Msk           /*!< ADC internal path to VrefInt and temperature sensor enable */

/******************  Bit definition for ADC_SMPR1 register  *******************/
#define ADC_SMPR1_SMP10_Pos (0U)
#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP10     ADC_SMPR1_SMP10_Msk           /*!< ADC channel 10 sampling time selection  */
#define ADC_SMPR1_SMP10_0   (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP10_1   (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP10_2   (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */

#define ADC_SMPR1_SMP11_Pos (3U)
#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP11     ADC_SMPR1_SMP11_Msk           /*!< ADC channel 11 sampling time selection  */
#define ADC_SMPR1_SMP11_0   (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP11_1   (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP11_2   (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */

#define ADC_SMPR1_SMP12_Pos (6U)
#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP12     ADC_SMPR1_SMP12_Msk           /*!< ADC channel 12 sampling time selection  */
#define ADC_SMPR1_SMP12_0   (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP12_1   (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP12_2   (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */

#define ADC_SMPR1_SMP13_Pos (9U)
#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP13     ADC_SMPR1_SMP13_Msk           /*!< ADC channel 13 sampling time selection  */
#define ADC_SMPR1_SMP13_0   (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP13_1   (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP13_2   (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */

#define ADC_SMPR1_SMP14_Pos (12U)
#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP14     ADC_SMPR1_SMP14_Msk           /*!< ADC channel 14 sampling time selection  */
#define ADC_SMPR1_SMP14_0   (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP14_1   (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP14_2   (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */

#define ADC_SMPR1_SMP15_Pos (15U)
#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP15     ADC_SMPR1_SMP15_Msk           /*!< ADC channel 15 sampling time selection  */
#define ADC_SMPR1_SMP15_0   (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP15_1   (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP15_2   (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */

#define ADC_SMPR1_SMP16_Pos (18U)
#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP16     ADC_SMPR1_SMP16_Msk           /*!< ADC channel 16 sampling time selection  */
#define ADC_SMPR1_SMP16_0   (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP16_1   (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP16_2   (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */

#define ADC_SMPR1_SMP17_Pos (21U)
#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP17     ADC_SMPR1_SMP17_Msk           /*!< ADC channel 17 sampling time selection  */
#define ADC_SMPR1_SMP17_0   (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP17_1   (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP17_2   (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */

/******************  Bit definition for ADC_SMPR2 register  *******************/
#define ADC_SMPR2_SMP0_Pos (0U)
#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP0     ADC_SMPR2_SMP0_Msk           /*!< ADC channel 0 sampling time selection  */
#define ADC_SMPR2_SMP0_0   (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP0_1   (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP0_2   (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */

#define ADC_SMPR2_SMP1_Pos (3U)
#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP1     ADC_SMPR2_SMP1_Msk           /*!< ADC channel 1 sampling time selection  */
#define ADC_SMPR2_SMP1_0   (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP1_1   (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP1_2   (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */

#define ADC_SMPR2_SMP2_Pos (6U)
#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP2     ADC_SMPR2_SMP2_Msk           /*!< ADC channel 2 sampling time selection  */
#define ADC_SMPR2_SMP2_0   (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP2_1   (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP2_2   (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */

#define ADC_SMPR2_SMP3_Pos (9U)
#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP3     ADC_SMPR2_SMP3_Msk           /*!< ADC channel 3 sampling time selection  */
#define ADC_SMPR2_SMP3_0   (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP3_1   (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP3_2   (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */

#define ADC_SMPR2_SMP4_Pos (12U)
#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP4     ADC_SMPR2_SMP4_Msk           /*!< ADC channel 4 sampling time selection  */
#define ADC_SMPR2_SMP4_0   (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP4_1   (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP4_2   (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */

#define ADC_SMPR2_SMP5_Pos (15U)
#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP5     ADC_SMPR2_SMP5_Msk           /*!< ADC channel 5 sampling time selection  */
#define ADC_SMPR2_SMP5_0   (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP5_1   (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP5_2   (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */

#define ADC_SMPR2_SMP6_Pos (18U)
#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP6     ADC_SMPR2_SMP6_Msk           /*!< ADC channel 6 sampling time selection  */
#define ADC_SMPR2_SMP6_0   (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP6_1   (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP6_2   (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */

#define ADC_SMPR2_SMP7_Pos (21U)
#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP7     ADC_SMPR2_SMP7_Msk           /*!< ADC channel 7 sampling time selection  */
#define ADC_SMPR2_SMP7_0   (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP7_1   (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP7_2   (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */

#define ADC_SMPR2_SMP8_Pos (24U)
#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP8     ADC_SMPR2_SMP8_Msk           /*!< ADC channel 8 sampling time selection  */
#define ADC_SMPR2_SMP8_0   (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP8_1   (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP8_2   (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */

#define ADC_SMPR2_SMP9_Pos (27U)
#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP9     ADC_SMPR2_SMP9_Msk           /*!< ADC channel 9 sampling time selection  */
#define ADC_SMPR2_SMP9_0   (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP9_1   (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP9_2   (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */

/******************  Bit definition for ADC_JOFR1 register  *******************/
#define ADC_JOFR1_JOFFSET1_Pos (0U)
#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_JOFR1_JOFFSET1     ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */

/******************  Bit definition for ADC_JOFR2 register  *******************/
#define ADC_JOFR2_JOFFSET2_Pos (0U)
#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_JOFR2_JOFFSET2     ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */

/******************  Bit definition for ADC_JOFR3 register  *******************/
#define ADC_JOFR3_JOFFSET3_Pos (0U)
#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_JOFR3_JOFFSET3     ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */

/******************  Bit definition for ADC_JOFR4 register  *******************/
#define ADC_JOFR4_JOFFSET4_Pos (0U)
#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_JOFR4_JOFFSET4     ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */

/*******************  Bit definition for ADC_HTR register  ********************/
#define ADC_HTR_HT_Pos (0U)
#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
#define ADC_HTR_HT     ADC_HTR_HT_Msk             /*!< ADC analog watchdog 1 threshold high */

/*******************  Bit definition for ADC_LTR register  ********************/
#define ADC_LTR_LT_Pos (0U)
#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
#define ADC_LTR_LT     ADC_LTR_LT_Msk             /*!< ADC analog watchdog 1 threshold low */

/*******************  Bit definition for ADC_SQR1 register  *******************/
#define ADC_SQR1_SQ13_Pos (0U)
#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
#define ADC_SQR1_SQ13     ADC_SQR1_SQ13_Msk            /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR1_SQ13_0   (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
#define ADC_SQR1_SQ13_1   (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
#define ADC_SQR1_SQ13_2   (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
#define ADC_SQR1_SQ13_3   (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ13_4   (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */

#define ADC_SQR1_SQ14_Pos (5U)
#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
#define ADC_SQR1_SQ14     ADC_SQR1_SQ14_Msk            /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR1_SQ14_0   (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
#define ADC_SQR1_SQ14_1   (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ14_2   (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ14_3   (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ14_4   (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */

#define ADC_SQR1_SQ15_Pos (10U)
#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
#define ADC_SQR1_SQ15     ADC_SQR1_SQ15_Msk            /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR1_SQ15_0   (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ15_1   (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
#define ADC_SQR1_SQ15_2   (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ15_3   (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ15_4   (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */

#define ADC_SQR1_SQ16_Pos (15U)
#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
#define ADC_SQR1_SQ16     ADC_SQR1_SQ16_Msk            /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR1_SQ16_0   (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ16_1   (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ16_2   (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
#define ADC_SQR1_SQ16_3   (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ16_4   (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */

#define ADC_SQR1_L_Pos (20U)
#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
#define ADC_SQR1_L     ADC_SQR1_L_Msk           /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0   (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
#define ADC_SQR1_L_1   (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
#define ADC_SQR1_L_2   (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
#define ADC_SQR1_L_3   (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */

/*******************  Bit definition for ADC_SQR2 register  *******************/
#define ADC_SQR2_SQ7_Pos (0U)
#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ7     ADC_SQR2_SQ7_Msk            /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0   (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ7_1   (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ7_2   (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ7_3   (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ7_4   (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */

#define ADC_SQR2_SQ8_Pos (5U)
#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
#define ADC_SQR2_SQ8     ADC_SQR2_SQ8_Msk            /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0   (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
#define ADC_SQR2_SQ8_1   (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ8_2   (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ8_3   (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ8_4   (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */

#define ADC_SQR2_SQ9_Pos (10U)
#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
#define ADC_SQR2_SQ9     ADC_SQR2_SQ9_Msk            /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0   (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ9_1   (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
#define ADC_SQR2_SQ9_2   (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ9_3   (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ9_4   (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */

#define ADC_SQR2_SQ10_Pos (15U)
#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
#define ADC_SQR2_SQ10     ADC_SQR2_SQ10_Msk            /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR2_SQ10_0   (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ10_1   (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ10_2   (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
#define ADC_SQR2_SQ10_3   (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ10_4   (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */

#define ADC_SQR2_SQ11_Pos (20U)
#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
#define ADC_SQR2_SQ11     ADC_SQR2_SQ11_Msk            /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR2_SQ11_0   (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ11_1   (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ11_2   (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ11_3   (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
#define ADC_SQR2_SQ11_4   (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */

#define ADC_SQR2_SQ12_Pos (25U)
#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
#define ADC_SQR2_SQ12     ADC_SQR2_SQ12_Msk            /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR2_SQ12_0   (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ12_1   (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ12_2   (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ12_3   (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
#define ADC_SQR2_SQ12_4   (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */

/*******************  Bit definition for ADC_SQR3 register  *******************/
#define ADC_SQR3_SQ1_Pos (0U)
#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ1     ADC_SQR3_SQ1_Msk            /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR3_SQ1_0   (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ1_1   (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ1_2   (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ1_3   (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ1_4   (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */

#define ADC_SQR3_SQ2_Pos (5U)
#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
#define ADC_SQR3_SQ2     ADC_SQR3_SQ2_Msk            /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR3_SQ2_0   (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
#define ADC_SQR3_SQ2_1   (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ2_2   (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ2_3   (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ2_4   (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */

#define ADC_SQR3_SQ3_Pos (10U)
#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
#define ADC_SQR3_SQ3     ADC_SQR3_SQ3_Msk            /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR3_SQ3_0   (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ3_1   (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
#define ADC_SQR3_SQ3_2   (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ3_3   (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ3_4   (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */

#define ADC_SQR3_SQ4_Pos (15U)
#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
#define ADC_SQR3_SQ4     ADC_SQR3_SQ4_Msk            /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR3_SQ4_0   (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ4_1   (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ4_2   (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
#define ADC_SQR3_SQ4_3   (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ4_4   (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */

#define ADC_SQR3_SQ5_Pos (20U)
#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
#define ADC_SQR3_SQ5     ADC_SQR3_SQ5_Msk            /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR3_SQ5_0   (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ5_1   (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ5_2   (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ5_3   (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
#define ADC_SQR3_SQ5_4   (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */

#define ADC_SQR3_SQ6_Pos (25U)
#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
#define ADC_SQR3_SQ6     ADC_SQR3_SQ6_Msk            /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR3_SQ6_0   (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ6_1   (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ6_2   (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ6_3   (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
#define ADC_SQR3_SQ6_4   (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */

/*******************  Bit definition for ADC_JSQR register  *******************/
#define ADC_JSQR_JSQ1_Pos (0U)
#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
#define ADC_JSQR_JSQ1     ADC_JSQR_JSQ1_Msk            /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0   (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JSQ1_1   (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JSQ1_2   (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JSQ1_3   (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JSQ1_4   (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */

#define ADC_JSQR_JSQ2_Pos (5U)
#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
#define ADC_JSQR_JSQ2     ADC_JSQR_JSQ2_Msk            /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0   (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JSQ2_1   (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JSQ2_2   (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JSQ2_3   (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ2_4   (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */

#define ADC_JSQR_JSQ3_Pos (10U)
#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
#define ADC_JSQR_JSQ3     ADC_JSQR_JSQ3_Msk            /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0   (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ3_1   (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ3_2   (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ3_3   (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ3_4   (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */

#define ADC_JSQR_JSQ4_Pos (15U)
#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ4     ADC_JSQR_JSQ4_Msk            /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0   (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ4_1   (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ4_2   (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ4_3   (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ4_4   (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */

#define ADC_JSQR_JL_Pos (20U)
#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
#define ADC_JSQR_JL     ADC_JSQR_JL_Msk           /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0   (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JL_1   (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */

/*******************  Bit definition for ADC_JDR1 register  *******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA     ADC_JDR1_JDATA_Msk              /*!< ADC group injected sequencer rank 1 conversion data */

/*******************  Bit definition for ADC_JDR2 register  *******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA     ADC_JDR2_JDATA_Msk              /*!< ADC group injected sequencer rank 2 conversion data */

/*******************  Bit definition for ADC_JDR3 register  *******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA     ADC_JDR3_JDATA_Msk              /*!< ADC group injected sequencer rank 3 conversion data */

/*******************  Bit definition for ADC_JDR4 register  *******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA     ADC_JDR4_JDATA_Msk              /*!< ADC group injected sequencer rank 4 conversion data */

/********************  Bit definition for ADC_DR register  ********************/
#define ADC_DR_DATA_Pos     (0U)
#define ADC_DR_DATA_Msk     (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_DATA         ADC_DR_DATA_Msk              /*!< ADC group regular conversion data */
#define ADC_DR_ADC2DATA_Pos (16U)
#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
#define ADC_DR_ADC2DATA     ADC_DR_ADC2DATA_Msk              /*!< ADC group regular conversion data for ADC slave, in multimode */

/*****************************************************************************/
/*                                                                           */
/*                               Timers (TIM)                                */
/*                                                                           */
/*****************************************************************************/
/*******************  Bit definition for TIM_CR1 register  *******************/
#define TIM_CR1_CEN_Pos  (0U)
#define TIM_CR1_CEN_Msk  (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN      TIM_CR1_CEN_Msk           /*!
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/** @addtogroup CMSIS
 * @{
 */

/** @addtogroup stm32f1xx
 * @{
 */

#ifndef __STM32F1XX_H
#define __STM32F1XX_H

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/** @addtogroup Library_configuration_section
 * @{
 */

/**
 * @brief STM32 Family
 */
#if !defined(STM32F1)
#define STM32F1
#endif /* STM32F1 */

/* Uncomment the line below according to the target STM32L device used in your
   application
  */

#if !defined(STM32F100xB) && !defined(STM32F100xE) && !defined(STM32F101x6) && !defined(STM32F101xB) && !defined(STM32F101xE) && !defined(STM32F101xG) && !defined(STM32F102x6) \
    && !defined(STM32F102xB) && !defined(STM32F103x6) && !defined(STM32F103xB) && !defined(STM32F103xE) && !defined(STM32F103xG) && !defined(STM32F105xC) && !defined(STM32F107xC)
/* #define STM32F100xB  */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */  /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6  */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB  */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */  /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG  */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */  /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB  */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6  */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB  */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */  /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG  */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */  /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC  */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif

/*  Tip: To avoid modifying this file each time you need to switch between these
        devices, you can define the device in your toolchain compiler preprocessor.
  */

#if !defined(USE_HAL_DRIVER)
/**
 * @brief Comment the line below if you will not use the peripherals drivers.
   In this case, these drivers will not be included and the application code will
   be based on direct access to peripherals registers
   */
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */

/**
 * @brief CMSIS Device version number V4.2.0
 */
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8]  sub2 version */
#define __STM32F1_CMSIS_VERSION_RC   (0x00) /*!< [7:0]  release candidate */
#define __STM32F1_CMSIS_VERSION      ((__STM32F1_CMSIS_VERSION_MAIN << 24) | (__STM32F1_CMSIS_VERSION_SUB1 << 16) | (__STM32F1_CMSIS_VERSION_SUB2 << 8) | (__STM32F1_CMSIS_VERSION_RC))

/**
 * @}
 */

/** @addtogroup Device_Included
 * @{
 */

#if defined(STM32F100xB)
#include "stm32f100xb.h"
#elif defined(STM32F100xE)
#include "stm32f100xe.h"
#elif defined(STM32F101x6)
#include "stm32f101x6.h"
#elif defined(STM32F101xB)
#include "stm32f101xb.h"
#elif defined(STM32F101xE)
#include "stm32f101xe.h"
#elif defined(STM32F101xG)
#include "stm32f101xg.h"
#elif defined(STM32F102x6)
#include "stm32f102x6.h"
#elif defined(STM32F102xB)
#include "stm32f102xb.h"
#elif defined(STM32F103x6)
#include "stm32f103x6.h"
#elif defined(STM32F103xB)
#include "stm32f103xb.h"
#elif defined(STM32F103xE)
#include "stm32f103xe.h"
#elif defined(STM32F103xG)
#include "stm32f103xg.h"
#elif defined(STM32F105xC)
#include "stm32f105xc.h"
#elif defined(STM32F107xC)
#include "stm32f107xc.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif

/**
 * @}
 */

/** @addtogroup Exported_types
 * @{
 */
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;

typedef enum { DISABLE = 0, ENABLE = !DISABLE } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum { ERROR = 0, SUCCESS = !ERROR } ErrorStatus;

/**
 * @}
 */

/** @addtogroup Exported_macros
 * @{
 */
#define SET_BIT(REG, BIT) ((REG) |= (BIT))

#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))

#define READ_BIT(REG, BIT) ((REG) & (BIT))

#define CLEAR_REG(REG) ((REG) = (0x0))

#define WRITE_REG(REG, VAL) ((REG) = (VAL))

#define READ_REG(REG) ((REG))

#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))

/**
 * @}
 */

#if defined(USE_HAL_DRIVER)
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __STM32F1xx_H */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
================================================
/**
 ******************************************************************************
 * @file    system_stm32f10x.h
 * @author  MCD Application Team
 * @version V4.2.0
 * @date    31-March-2017
 * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/** @addtogroup CMSIS
 * @{
 */

/** @addtogroup stm32f10x_system
 * @{
 */

/**
 * @brief Define to prevent recursive inclusion
 */
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H

#ifdef __cplusplus
extern "C" {
#endif

/** @addtogroup STM32F10x_System_Includes
 * @{
 */

/**
 * @}
 */

/** @addtogroup STM32F10x_System_Exported_types
 * @{
 */

extern uint32_t      SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U];  /*!< APB prescalers table values */

/**
 * @}
 */

/** @addtogroup STM32F10x_System_Exported_Constants
 * @{
 */

/**
 * @}
 */

/** @addtogroup STM32F10x_System_Exported_Macros
 * @{
 */

/**
 * @}
 */

/** @addtogroup STM32F10x_System_Exported_Functions
 * @{
 */

extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /*__SYSTEM_STM32F10X_H */

/**
 * @}
 */

/**
 * @}
 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/arm_common_tables.h
================================================
/* ----------------------------------------------------------------------
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. October 2015
 * $Revision: 	V.1.4.5 a
 *
 * Project: 	    CMSIS DSP Library
 * Title:	    arm_common_tables.h
 *
 * Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
 *
 * Target Processor: Cortex-M4/Cortex-M3
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 * -------------------------------------------------------------------- */

#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H

#include "arm_math.h"

extern const uint16_t armBitRevTable[1024];
extern const q15_t    armRecipTableQ15[64];
extern const q31_t    armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t     twiddleCoef_16_q31[24];
extern const q31_t     twiddleCoef_32_q31[48];
extern const q31_t     twiddleCoef_64_q31[96];
extern const q31_t     twiddleCoef_128_q31[192];
extern const q31_t     twiddleCoef_256_q31[384];
extern const q31_t     twiddleCoef_512_q31[768];
extern const q31_t     twiddleCoef_1024_q31[1536];
extern const q31_t     twiddleCoef_2048_q31[3072];
extern const q31_t     twiddleCoef_4096_q31[6144];
extern const q15_t     twiddleCoef_16_q15[24];
extern const q15_t     twiddleCoef_32_q15[48];
extern const q15_t     twiddleCoef_64_q15[96];
extern const q15_t     twiddleCoef_128_q15[192];
extern const q15_t     twiddleCoef_256_q15[384];
extern const q15_t     twiddleCoef_512_q15[768];
extern const q15_t     twiddleCoef_1024_q15[1536];
extern const q15_t     twiddleCoef_2048_q15[3072];
extern const q15_t     twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];

/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)

extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];

/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];

/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t     sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t     sinTable_q15[FAST_MATH_TABLE_SIZE + 1];

#endif /*  ARM_COMMON_TABLES_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/arm_const_structs.h
================================================
/* ----------------------------------------------------------------------
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. March 2015
 * $Revision: 	V.1.4.5
 *
 * Project: 	    CMSIS DSP Library
 * Title:	    arm_const_structs.h
 *
 * Description:	This file has constant structs that are initialized for
 *              user convenience.  For example, some can be given as
 *              arguments to the arm_cfft_f32() function.
 *
 * Target Processor: Cortex-M4/Cortex-M3
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 * -------------------------------------------------------------------- */

#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H

#include "arm_common_tables.h"
#include "arm_math.h"

extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;

extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;

extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;

#endif


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/arm_math.h
================================================
/* ----------------------------------------------------------------------
 * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
 *
 * $Date:        20. October 2015
 * $Revision:    V1.4.5 b
 *
 * Project:      CMSIS DSP Library
 * Title:        arm_math.h
 *
 * Description:  Public header file for CMSIS DSP Library
 *
 * Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *   - Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *   - Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *   - Neither the name of ARM LIMITED nor the names of its contributors
 *     may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 * -------------------------------------------------------------------- */

/**
   \mainpage CMSIS DSP Software Library
   *
   * Introduction
   * ------------
   *
   * This user manual describes the CMSIS DSP software library,
   * a suite of common signal processing functions for use on Cortex-M processor based devices.
   *
   * The library is divided into a number of functions each covering a specific category:
   * - Basic math functions
   * - Fast math functions
   * - Complex math functions
   * - Filters
   * - Matrix functions
   * - Transforms
   * - Motor control functions
   * - Statistical functions
   * - Support functions
   * - Interpolation functions
   *
   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
   * 32-bit integer and 32-bit floating-point values.
   *
   * Using the Library
   * ------------
   *
   * The library installer contains prebuilt versions of the libraries in the Lib folder.
   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
   *
   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
   * public header file  arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
   *
   * Examples
   * --------
   *
   * The library ships with a number of examples which demonstrate how to use the library functions.
   *
   * Toolchain Support
   * ------------
   *
   * The library has been developed and tested with MDK-ARM version 5.14.0.0
   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
   *
   * Building the Library
   * ------------
   *
   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
   * - arm_cortexM_math.uvprojx
   *
   *
   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
   *
   * Pre-processor Macros
   * ------------
   *
   * Each library project have differant pre-processor macros.
   *
   * - UNALIGNED_SUPPORT_DISABLE:
   *
   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
   *
   * - ARM_MATH_BIG_ENDIAN:
   *
   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
   *
   * - ARM_MATH_MATRIX_CHECK:
   *
   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
   *
   * - ARM_MATH_ROUNDING:
   *
   * Define macro ARM_MATH_ROUNDING for rounding on support functions
   *
   * - ARM_MATH_CMx:
   *
   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
   * ARM_MATH_CM7 for building the library on cortex-M7.
   *
   * - __FPU_PRESENT:
   *
   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
   *
   * 

   * CMSIS-DSP in ARM::CMSIS Pack
   * -----------------------------
   *
   * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
   * |File/Folder                   |Content                                                                 |
   * |------------------------------|------------------------------------------------------------------------|
   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
   *
   * 

   * Revision History of CMSIS-DSP
   * ------------
   * Please refer to \ref ChangeLog_pg.
   *
   * Copyright Notice
   * ------------
   *
   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
   */

/**
 * @defgroup groupMath Basic Math Functions
 */

/**
 * @defgroup groupFastMath Fast Math Functions
 * This set of functions provides a fast approximation to sine, cosine, and square root.
 * As compared to most of the other functions in the CMSIS math library, the fast math functions
 * operate on individual values and not arrays.
 * There are separate functions for Q15, Q31, and floating-point data.
 *
 */

/**
 * @defgroup groupCmplxMath Complex Math Functions
 * This set of functions operates on complex data vectors.
 * The data in the complex arrays is stored in an interleaved fashion
 * (real, imag, real, imag, ...).
 * In the API functions, the number of samples in a complex array refers
 * to the number of complex values; the array contains twice this number of
 * real values.
 */

/**
 * @defgroup groupFilters Filtering Functions
 */

/**
 * @defgroup groupMatrix Matrix Functions
 *
 * This set of functions provides basic matrix math operations.
 * The functions operate on matrix data structures.  For example,
 * the type
 * definition for the floating-point matrix structure is shown
 * below:
 * 
 *     typedef struct
 *     {
 *       uint16_t numRows;     // number of rows of the matrix.
 *       uint16_t numCols;     // number of columns of the matrix.
 *       float32_t *pData;     // points to the data of the matrix.
 *     } arm_matrix_instance_f32;
 * 

 * There are similar definitions for Q15 and Q31 data types.
 *
 * The structure specifies the size of the matrix and then points to
 * an array of data.  The array is of size numRows X numCols
 * and the values are arranged in row order.  That is, the
 * matrix element (i, j) is stored at:
 * 
 *     pData[i*numCols + j]
 * 

 *
 * \par Init Functions
 * There is an associated initialization function for each type of matrix
 * data structure.
 * The initialization function sets the values of the internal structure fields.
 * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
 * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
 *
 * \par
 * Use of the initialization function is optional. However, if initialization function is used
 * then the instance structure cannot be placed into a const data section.
 * To place the instance structure in a const data
 * section, manually initialize the data structure.  For example:
 * 
 * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
 * 

 * where nRows specifies the number of rows, nColumns
 * specifies the number of columns, and pData points to the
 * data array.
 *
 * \par Size Checking
 * By default all of the matrix functions perform size checking on the input and
 * output matrices.  For example, the matrix addition function verifies that the
 * two input matrices and the output matrix all have the same number of rows and
 * columns.  If the size check fails the functions return:
 * 
 *     ARM_MATH_SIZE_MISMATCH
 * 

 * Otherwise the functions return
 * 
 *     ARM_MATH_SUCCESS
 * 

 * There is some overhead associated with this matrix size checking.
 * The matrix size checking is enabled via the \#define
 * 
 *     ARM_MATH_MATRIX_CHECK
 * 

 * within the library project settings.  By default this macro is defined
 * and size checking is enabled.  By changing the project settings and
 * undefining this macro size checking is eliminated and the functions
 * run a bit faster.  With size checking disabled the functions always
 * return ARM_MATH_SUCCESS.
 */

/**
 * @defgroup groupTransforms Transform Functions
 */

/**
 * @defgroup groupController Controller Functions
 */

/**
 * @defgroup groupStats Statistics Functions
 */
/**
 * @defgroup groupSupport Support Functions
 */

/**
 * @defgroup groupInterpolation Interpolation Functions
 * These functions perform 1- and 2-dimensional interpolation of data.
 * Linear interpolation is used for 1-dimensional data and
 * bilinear interpolation is used for 2-dimensional data.
 */

/**
 * @defgroup groupExamples Examples
 */
#ifndef _ARM_MATH_H
#define _ARM_MATH_H

/* ignore some GCC warnings */
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif

#define __CMSIS_GENERIC /* disable NVIC and Systick functions */

#if defined(ARM_MATH_CM7)
#include "core_cm7.h"
#elif defined(ARM_MATH_CM4)
#include "core_cm4.h"
#elif defined(ARM_MATH_CM3)
#include "core_cm3.h"
#elif defined(ARM_MATH_CM0)
#include "core_cm0.h"
#define ARM_MATH_CM0_FAMILY
#elif defined(ARM_MATH_CM0PLUS)
#include "core_cm0plus.h"
#define ARM_MATH_CM0_FAMILY
#else
#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
#endif

#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
#include "math.h"
#include "string.h"
#ifdef __cplusplus
extern "C" {
#endif

/**
 * @brief Macros required for reciprocal calculation in Normalized LMS
 */

#define DELTA_Q31  (0x100)
#define DELTA_Q15  0x5
#define INDEX_MASK 0x0000003F
#ifndef PI
#define PI 3.14159265358979f
#endif

/**
 * @brief Macros required for SINE and COSINE Fast math approximations
 */

#define FAST_MATH_TABLE_SIZE 512
#define FAST_MATH_Q31_SHIFT  (32 - 10)
#define FAST_MATH_Q15_SHIFT  (16 - 10)
#define CONTROLLER_Q31_SHIFT (32 - 9)
#define TABLE_SIZE           256
#define TABLE_SPACING_Q31    0x400000
#define TABLE_SPACING_Q15    0x80

/**
 * @brief Macros required for SINE and COSINE Controller functions
 */
/* 1.31(q31) Fixed value of 2/360 */
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
#define INPUT_SPACING 0xB60B61

/**
 * @brief Macro for Unaligned Support
 */
#ifndef UNALIGNED_SUPPORT_DISABLE
#define ALIGN4
#else
#if defined(__GNUC__)
#define ALIGN4 __attribute__((aligned(4)))
#else
#define ALIGN4 __align(4)
#endif
#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */

/**
 * @brief Error status returned by some functions in the library.
 */

typedef enum {
  ARM_MATH_SUCCESS        = 0,  /**< No error */
  ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
  ARM_MATH_LENGTH_ERROR   = -2, /**< Length of data buffer is incorrect */
  ARM_MATH_SIZE_MISMATCH  = -3, /**< Size of matrices is not compatible with the operation. */
  ARM_MATH_NANINF         = -4, /**< Not-a-number (NaN) or infinity is generated */
  ARM_MATH_SINGULAR       = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
  ARM_MATH_TEST_FAILURE   = -6  /**< Test Failed  */
} arm_status;

/**
 * @brief 8-bit fractional data type in 1.7 format.
 */
typedef int8_t q7_t;

/**
 * @brief 16-bit fractional data type in 1.15 format.
 */
typedef int16_t q15_t;

/**
 * @brief 32-bit fractional data type in 1.31 format.
 */
typedef int32_t q31_t;

/**
 * @brief 64-bit fractional data type in 1.63 format.
 */
typedef int64_t q63_t;

/**
 * @brief 32-bit floating-point type definition.
 */
typedef float float32_t;

/**
 * @brief 64-bit floating-point type definition.
 */
typedef double float64_t;

/**
 * @brief definition to read/write two 16 bit values.
 */
#if defined __CC_ARM
#define __SIMD32_TYPE int32_t __packed
#define CMSIS_UNUSED  __attribute__((unused))

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED  __attribute__((unused))

#elif defined __GNUC__
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED  __attribute__((unused))

#elif defined __ICCARM__
#define __SIMD32_TYPE int32_t __packed
#define CMSIS_UNUSED

#elif defined __CSMC__
#define __SIMD32_TYPE int32_t
#define CMSIS_UNUSED

#elif defined __TASKING__
#define __SIMD32_TYPE __unaligned int32_t
#define CMSIS_UNUSED

#else
#error Unknown compiler
#endif

#define __SIMD32(addr)       (*(__SIMD32_TYPE **)&(addr))
#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr))
#define __SIMD64(addr)       (*(int64_t **)&(addr))

#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY)
/**
 * @brief definition to pack two 16 bit values.
 */
#define __PKHBT(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000))
#define __PKHTB(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF))

#endif

/**
 * @brief definition to pack four 8 bit values.
 */
#ifndef ARM_MATH_BIG_ENDIAN

#define __PACKq7(v0, v1, v2, v3) \
  ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v3) << 24) & (int32_t)0xFF000000))
#else

#define __PACKq7(v0, v1, v2, v3) \
  ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v0) << 24) & (int32_t)0xFF000000))

#endif

/**
 * @brief Clips Q63 to Q31 values.
 */
static __INLINE q31_t clip_q63_to_q31(q63_t x) { return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; }

/**
 * @brief Clips Q63 to Q15 values.
 */
static __INLINE q15_t clip_q63_to_q15(q63_t x) { return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : (q15_t)(x >> 15); }

/**
 * @brief Clips Q31 to Q7 values.
 */
static __INLINE q7_t clip_q31_to_q7(q31_t x) { return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; }

/**
 * @brief Clips Q31 to Q15 values.
 */
static __INLINE q15_t clip_q31_to_q15(q31_t x) { return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; }

/**
 * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
 */

static __INLINE q63_t mult32x64(q63_t x, q31_t y) { return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t)(x >> 32) * y))); }

/*
  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
  #define __CLZ __clz
  #endif
 */
/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
#if defined(ARM_MATH_CM0_FAMILY) && ((defined(__ICCARM__)))
static __INLINE uint32_t __CLZ(q31_t data);

static __INLINE uint32_t __CLZ(q31_t data) {
  uint32_t count = 0;
  uint32_t mask  = 0x80000000;

  while ((data & mask) == 0) {
    count += 1u;
    mask = mask >> 1u;
  }

  return (count);
}
#endif

/**
 * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
 */

static __INLINE uint32_t arm_recip_q31(q31_t in, q31_t *dst, q31_t *pRecipTable) {
  q31_t    out;
  uint32_t tempVal;
  uint32_t index, i;
  uint32_t signBits;

  if (in > 0) {
    signBits = ((uint32_t)(__CLZ(in) - 1));
  } else {
    signBits = ((uint32_t)(__CLZ(-in) - 1));
  }

  /* Convert input sample to 1.31 format */
  in = (in << signBits);

  /* calculation of index for initial approximated Val */
  index = (uint32_t)(in >> 24);
  index = (index & INDEX_MASK);

  /* 1.31 with exp 1 */
  out = pRecipTable[index];

  /* calculation of reciprocal value */
  /* running approximation for two iterations */
  for (i = 0u; i < 2u; i++) {
    tempVal = (uint32_t)(((q63_t)in * out) >> 31);
    tempVal = 0x7FFFFFFFu - tempVal;
    /*      1.31 with exp 1 */
    /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
    out = clip_q63_to_q31(((q63_t)out * tempVal) >> 30);
  }

  /* write output */
  *dst = out;

  /* return num of signbits of out = 1/in value */
  return (signBits + 1u);
}

/**
 * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
 */
static __INLINE uint32_t arm_recip_q15(q15_t in, q15_t *dst, q15_t *pRecipTable) {
  q15_t    out     = 0;
  uint32_t tempVal = 0;
  uint32_t index = 0, i = 0;
  uint32_t signBits = 0;

  if (in > 0) {
    signBits = ((uint32_t)(__CLZ(in) - 17));
  } else {
    signBits = ((uint32_t)(__CLZ(-in) - 17));
  }

  /* Convert input sample to 1.15 format */
  in = (in << signBits);

  /* calculation of index for initial approximated Val */
  index = (uint32_t)(in >> 8);
  index = (index & INDEX_MASK);

  /*      1.15 with exp 1  */
  out = pRecipTable[index];

  /* calculation of reciprocal value */
  /* running approximation for two iterations */
  for (i = 0u; i < 2u; i++) {
    tempVal = (uint32_t)(((q31_t)in * out) >> 15);
    tempVal = 0x7FFFu - tempVal;
    /*      1.15 with exp 1 */
    out = (q15_t)(((q31_t)out * tempVal) >> 14);
    /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
  }

  /* write output */
  *dst = out;

  /* return num of signbits of out = 1/in value */
  return (signBits + 1);
}

/*
 * @brief C custom defined intrinisic function for only M0 processors
 */
#if defined(ARM_MATH_CM0_FAMILY)
static __INLINE q31_t __SSAT(q31_t x, uint32_t y) {
  int32_t  posMax, negMin;
  uint32_t i;

  posMax = 1;
  for (i = 0; i < (y - 1); i++) {
    posMax = posMax * 2;
  }

  if (x > 0) {
    posMax = (posMax - 1);

    if (x > posMax) {
      x = posMax;
    }
  } else {
    negMin = -posMax;

    if (x < negMin) {
      x = negMin;
    }
  }
  return (x);
}
#endif /* end of ARM_MATH_CM0_FAMILY */

/*
 * @brief C custom defined intrinsic function for M3 and M0 processors
 */
#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY)

/*
 * @brief C custom defined QADD8 for M3 and M0 processors
 */
static __INLINE uint32_t __QADD8(uint32_t x, uint32_t y) {
  q31_t r, s, t, u;

  r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
  s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
  t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
  u = __SSAT(((((q31_t)x) >> 24) + (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF;

  return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}

/*
 * @brief C custom defined QSUB8 for M3 and M0 processors
 */
static __INLINE uint32_t __QSUB8(uint32_t x, uint32_t y) {
  q31_t r, s, t, u;

  r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
  s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
  t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
  u = __SSAT(((((q31_t)x) >> 24) - (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF;

  return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r)));
}

/*
 * @brief C custom defined QADD16 for M3 and M0 processors
 */
static __INLINE uint32_t __QADD16(uint32_t x, uint32_t y) {
  /*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
  q31_t r = 0, s = 0;

  r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
  s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined SHADD16 for M3 and M0 processors
 */
static __INLINE uint32_t __SHADD16(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
  s = (((((q31_t)x) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined QSUB16 for M3 and M0 processors
 */
static __INLINE uint32_t __QSUB16(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
  s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined SHSUB16 for M3 and M0 processors
 */
static __INLINE uint32_t __SHSUB16(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
  s = (((((q31_t)x) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined QASX for M3 and M0 processors
 */
static __INLINE uint32_t __QASX(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
  s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined SHASX for M3 and M0 processors
 */
static __INLINE uint32_t __SHASX(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = (((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
  s = (((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined QSAX for M3 and M0 processors
 */
static __INLINE uint32_t __QSAX(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF;
  s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined SHSAX for M3 and M0 processors
 */
static __INLINE uint32_t __SHSAX(uint32_t x, uint32_t y) {
  q31_t r, s;

  r = (((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF;
  s = (((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;

  return ((uint32_t)((s << 16) | (r)));
}

/*
 * @brief C custom defined SMUSDX for M3 and M0 processors
 */
static __INLINE uint32_t __SMUSDX(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); }

/*
 * @brief C custom defined SMUADX for M3 and M0 processors
 */
static __INLINE uint32_t __SMUADX(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); }

/*
 * @brief C custom defined QADD for M3 and M0 processors
 */
static __INLINE int32_t __QADD(int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); }

/*
 * @brief C custom defined QSUB for M3 and M0 processors
 */
static __INLINE int32_t __QSUB(int32_t x, int32_t y) { return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); }

/*
 * @brief C custom defined SMLAD for M3 and M0 processors
 */
static __INLINE uint32_t __SMLAD(uint32_t x, uint32_t y, uint32_t sum) {
  return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q31_t)sum))));
}

/*
 * @brief C custom defined SMLADX for M3 and M0 processors
 */
static __INLINE uint32_t __SMLADX(uint32_t x, uint32_t y, uint32_t sum) {
  return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum))));
}

/*
 * @brief C custom defined SMLSDX for M3 and M0 processors
 */
static __INLINE uint32_t __SMLSDX(uint32_t x, uint32_t y, uint32_t sum) {
  return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q31_t)sum))));
}

/*
 * @brief C custom defined SMLALD for M3 and M0 processors
 */
static __INLINE uint64_t __SMLALD(uint32_t x, uint32_t y, uint64_t sum) {
  /*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
  return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + (((q63_t)sum))));
}

/*
 * @brief C custom defined SMLALDX for M3 and M0 processors
 */
static __INLINE uint64_t __SMLALDX(uint32_t x, uint32_t y, uint64_t sum) {
  /*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
  return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + (((q63_t)sum))));
}

/*
 * @brief C custom defined SMUAD for M3 and M0 processors
 */
static __INLINE uint32_t __SMUAD(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); }

/*
 * @brief C custom defined SMUSD for M3 and M0 processors
 */
static __INLINE uint32_t __SMUSD(uint32_t x, uint32_t y) { return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); }

/*
 * @brief C custom defined SXTB16 for M3 and M0 processors
 */
static __INLINE uint32_t __SXTB16(uint32_t x) { return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000))); }

#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */

/**
 * @brief Instance structure for the Q7 FIR filter.
 */
typedef struct {
  uint16_t numTaps; /**< number of filter coefficients in the filter. */
  q7_t *   pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q7_t *   pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} arm_fir_instance_q7;

/**
 * @brief Instance structure for the Q15 FIR filter.
 */
typedef struct {
  uint16_t numTaps; /**< number of filter coefficients in the filter. */
  q15_t *  pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q15_t *  pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
} arm_fir_instance_q15;

/**
 * @brief Instance structure for the Q31 FIR filter.
 */
typedef struct {
  uint16_t numTaps; /**< number of filter coefficients in the filter. */
  q31_t *  pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q31_t *  pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} arm_fir_instance_q31;

/**
 * @brief Instance structure for the floating-point FIR filter.
 */
typedef struct {
  uint16_t   numTaps; /**< number of filter coefficients in the filter. */
  float32_t *pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
} arm_fir_instance_f32;

/**
 * @brief Processing function for the Q7 FIR filter.
 * @param[in]  S          points to an instance of the Q7 FIR filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_q7(const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q7 FIR filter.
 * @param[in,out] S          points to an instance of the Q7 FIR structure.
 * @param[in]     numTaps    Number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of samples that are processed.
 */
void arm_fir_init_q7(arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q15 FIR filter.
 * @param[in]  S          points to an instance of the Q15 FIR structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q15 FIR filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_fast_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q15 FIR filter.
 * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
 * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of samples that are processed at a time.
 * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
 * numTaps is not a supported value.
 */
arm_status arm_fir_init_q15(arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 FIR filter.
 * @param[in]  S          points to an instance of the Q31 FIR filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q31 FIR structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_fast_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q31 FIR filter.
 * @param[in,out] S          points to an instance of the Q31 FIR structure.
 * @param[in]     numTaps    Number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of samples that are processed at a time.
 */
void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the floating-point FIR filter.
 * @param[in]  S          points to an instance of the floating-point FIR structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_f32(const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point FIR filter.
 * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
 * @param[in]     numTaps    Number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of samples that are processed at a time.
 */
void arm_fir_init_f32(arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize);

/**
 * @brief Instance structure for the Q15 Biquad cascade filter.
 */
typedef struct {
  int8_t numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  q15_t *pState;    /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
  q15_t *pCoeffs;   /**< Points to the array of coefficients.  The array is of length 5*numStages. */
  int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
} arm_biquad_casd_df1_inst_q15;

/**
 * @brief Instance structure for the Q31 Biquad cascade filter.
 */
typedef struct {
  uint32_t numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  q31_t *  pState;    /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
  q31_t *  pCoeffs;   /**< Points to the array of coefficients.  The array is of length 5*numStages. */
  uint8_t  postShift; /**< Additional shift, in bits, applied to each output sample. */
} arm_biquad_casd_df1_inst_q31;

/**
 * @brief Instance structure for the floating-point Biquad cascade filter.
 */
typedef struct {
  uint32_t   numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  float32_t *pState;    /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
  float32_t *pCoeffs;   /**< Points to the array of coefficients.  The array is of length 5*numStages. */
} arm_biquad_casd_df1_inst_f32;

/**
 * @brief Processing function for the Q15 Biquad cascade filter.
 * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df1_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q15 Biquad cascade filter.
 * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
 */
void arm_biquad_cascade_df1_init_q15(arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift);

/**
 * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df1_fast_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 Biquad cascade filter
 * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df1_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df1_fast_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q31 Biquad cascade filter.
 * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
 */
void arm_biquad_cascade_df1_init_q31(arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift);

/**
 * @brief Processing function for the floating-point Biquad cascade filter.
 * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df1_f32(const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point Biquad cascade filter.
 * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 */
void arm_biquad_cascade_df1_init_f32(arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState);

/**
 * @brief Instance structure for the floating-point matrix structure.
 */
typedef struct {
  uint16_t   numRows; /**< number of rows of the matrix.     */
  uint16_t   numCols; /**< number of columns of the matrix.  */
  float32_t *pData;   /**< points to the data of the matrix. */
} arm_matrix_instance_f32;

/**
 * @brief Instance structure for the floating-point matrix structure.
 */
typedef struct {
  uint16_t   numRows; /**< number of rows of the matrix.     */
  uint16_t   numCols; /**< number of columns of the matrix.  */
  float64_t *pData;   /**< points to the data of the matrix. */
} arm_matrix_instance_f64;

/**
 * @brief Instance structure for the Q15 matrix structure.
 */
typedef struct {
  uint16_t numRows; /**< number of rows of the matrix.     */
  uint16_t numCols; /**< number of columns of the matrix.  */
  q15_t *  pData;   /**< points to the data of the matrix. */
} arm_matrix_instance_q15;

/**
 * @brief Instance structure for the Q31 matrix structure.
 */
typedef struct {
  uint16_t numRows; /**< number of rows of the matrix.     */
  uint16_t numCols; /**< number of columns of the matrix.  */
  q31_t *  pData;   /**< points to the data of the matrix. */
} arm_matrix_instance_q31;

/**
 * @brief Floating-point matrix addition.
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15 matrix addition.
 * @param[in]   pSrcA  points to the first input matrix structure
 * @param[in]   pSrcB  points to the second input matrix structure
 * @param[out]  pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst);

/**
 * @brief Q31 matrix addition.
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst);

/**
 * @brief Floating-point, complex, matrix multiplication.
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_cmplx_mult_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15, complex,  matrix multiplication.
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_cmplx_mult_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pScratch);

/**
 * @brief Q31, complex, matrix multiplication.
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_cmplx_mult_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst);

/**
 * @brief Floating-point matrix transpose.
 * @param[in]  pSrc  points to the input matrix
 * @param[out] pDst  points to the output matrix
 * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
 * or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15 matrix transpose.
 * @param[in]  pSrc  points to the input matrix
 * @param[out] pDst  points to the output matrix
 * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
 * or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst);

/**
 * @brief Q31 matrix transpose.
 * @param[in]  pSrc  points to the input matrix
 * @param[out] pDst  points to the output matrix
 * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
 * or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst);

/**
 * @brief Floating-point matrix multiplication
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15 matrix multiplication
 * @param[in]  pSrcA   points to the first input matrix structure
 * @param[in]  pSrcB   points to the second input matrix structure
 * @param[out] pDst    points to output matrix structure
 * @param[in]  pState  points to the array for storing intermediate results
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState);

/**
 * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA   points to the first input matrix structure
 * @param[in]  pSrcB   points to the second input matrix structure
 * @param[out] pDst    points to output matrix structure
 * @param[in]  pState  points to the array for storing intermediate results
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_mult_fast_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState);

/**
 * @brief Q31 matrix multiplication
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst);

/**
 * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_mult_fast_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst);

/**
 * @brief Floating-point matrix subtraction
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15 matrix subtraction
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst);

/**
 * @brief Q31 matrix subtraction
 * @param[in]  pSrcA  points to the first input matrix structure
 * @param[in]  pSrcB  points to the second input matrix structure
 * @param[out] pDst   points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst);

/**
 * @brief Floating-point matrix scaling.
 * @param[in]  pSrc   points to the input matrix
 * @param[in]  scale  scale factor
 * @param[out] pDst   points to the output matrix
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst);

/**
 * @brief Q15 matrix scaling.
 * @param[in]  pSrc        points to input matrix
 * @param[in]  scaleFract  fractional portion of the scale factor
 * @param[in]  shift       number of bits to shift the result by
 * @param[out] pDst        points to output matrix
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst);

/**
 * @brief Q31 matrix scaling.
 * @param[in]  pSrc        points to input matrix
 * @param[in]  scaleFract  fractional portion of the scale factor
 * @param[in]  shift       number of bits to shift the result by
 * @param[out] pDst        points to output matrix structure
 * @return     The function returns either
 * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
 */
arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst);

/**
 * @brief  Q31 matrix initialization.
 * @param[in,out] S         points to an instance of the floating-point matrix structure.
 * @param[in]     nRows     number of rows in the matrix.
 * @param[in]     nColumns  number of columns in the matrix.
 * @param[in]     pData     points to the matrix data array.
 */
void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData);

/**
 * @brief  Q15 matrix initialization.
 * @param[in,out] S         points to an instance of the floating-point matrix structure.
 * @param[in]     nRows     number of rows in the matrix.
 * @param[in]     nColumns  number of columns in the matrix.
 * @param[in]     pData     points to the matrix data array.
 */
void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData);

/**
 * @brief  Floating-point matrix initialization.
 * @param[in,out] S         points to an instance of the floating-point matrix structure.
 * @param[in]     nRows     number of rows in the matrix.
 * @param[in]     nColumns  number of columns in the matrix.
 * @param[in]     pData     points to the matrix data array.
 */
void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData);

/**
 * @brief Instance structure for the Q15 PID Control.
 */
typedef struct {
  q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
#ifdef ARM_MATH_CM0_FAMILY
  q15_t A1;
  q15_t A2;
#else
  q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
#endif
  q15_t state[3]; /**< The state array of length 3. */
  q15_t Kp;       /**< The proportional gain. */
  q15_t Ki;       /**< The integral gain. */
  q15_t Kd;       /**< The derivative gain. */
} arm_pid_instance_q15;

/**
 * @brief Instance structure for the Q31 PID Control.
 */
typedef struct {
  q31_t A0;       /**< The derived gain, A0 = Kp + Ki + Kd . */
  q31_t A1;       /**< The derived gain, A1 = -Kp - 2Kd. */
  q31_t A2;       /**< The derived gain, A2 = Kd . */
  q31_t state[3]; /**< The state array of length 3. */
  q31_t Kp;       /**< The proportional gain. */
  q31_t Ki;       /**< The integral gain. */
  q31_t Kd;       /**< The derivative gain. */
} arm_pid_instance_q31;

/**
 * @brief Instance structure for the floating-point PID Control.
 */
typedef struct {
  float32_t A0;       /**< The derived gain, A0 = Kp + Ki + Kd . */
  float32_t A1;       /**< The derived gain, A1 = -Kp - 2Kd. */
  float32_t A2;       /**< The derived gain, A2 = Kd . */
  float32_t state[3]; /**< The state array of length 3. */
  float32_t Kp;       /**< The proportional gain. */
  float32_t Ki;       /**< The integral gain. */
  float32_t Kd;       /**< The derivative gain. */
} arm_pid_instance_f32;

/**
 * @brief  Initialization function for the floating-point PID Control.
 * @param[in,out] S               points to an instance of the PID structure.
 * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
 */
void arm_pid_init_f32(arm_pid_instance_f32 *S, int32_t resetStateFlag);

/**
 * @brief  Reset function for the floating-point PID Control.
 * @param[in,out] S  is an instance of the floating-point PID Control structure
 */
void arm_pid_reset_f32(arm_pid_instance_f32 *S);

/**
 * @brief  Initialization function for the Q31 PID Control.
 * @param[in,out] S               points to an instance of the Q15 PID structure.
 * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
 */
void arm_pid_init_q31(arm_pid_instance_q31 *S, int32_t resetStateFlag);

/**
 * @brief  Reset function for the Q31 PID Control.
 * @param[in,out] S   points to an instance of the Q31 PID Control structure
 */

void arm_pid_reset_q31(arm_pid_instance_q31 *S);

/**
 * @brief  Initialization function for the Q15 PID Control.
 * @param[in,out] S               points to an instance of the Q15 PID structure.
 * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
 */
void arm_pid_init_q15(arm_pid_instance_q15 *S, int32_t resetStateFlag);

/**
 * @brief  Reset function for the Q15 PID Control.
 * @param[in,out] S  points to an instance of the q15 PID Control structure
 */
void arm_pid_reset_q15(arm_pid_instance_q15 *S);

/**
 * @brief Instance structure for the floating-point Linear Interpolate function.
 */
typedef struct {
  uint32_t   nValues;  /**< nValues */
  float32_t  x1;       /**< x1 */
  float32_t  xSpacing; /**< xSpacing */
  float32_t *pYData;   /**< pointer to the table of Y values */
} arm_linear_interp_instance_f32;

/**
 * @brief Instance structure for the floating-point bilinear interpolation function.
 */
typedef struct {
  uint16_t   numRows; /**< number of rows in the data table. */
  uint16_t   numCols; /**< number of columns in the data table. */
  float32_t *pData;   /**< points to the data table. */
} arm_bilinear_interp_instance_f32;

/**
 * @brief Instance structure for the Q31 bilinear interpolation function.
 */
typedef struct {
  uint16_t numRows; /**< number of rows in the data table. */
  uint16_t numCols; /**< number of columns in the data table. */
  q31_t *  pData;   /**< points to the data table. */
} arm_bilinear_interp_instance_q31;

/**
 * @brief Instance structure for the Q15 bilinear interpolation function.
 */
typedef struct {
  uint16_t numRows; /**< number of rows in the data table. */
  uint16_t numCols; /**< number of columns in the data table. */
  q15_t *  pData;   /**< points to the data table. */
} arm_bilinear_interp_instance_q15;

/**
 * @brief Instance structure for the Q15 bilinear interpolation function.
 */
typedef struct {
  uint16_t numRows; /**< number of rows in the data table. */
  uint16_t numCols; /**< number of columns in the data table. */
  q7_t *   pData;   /**< points to the data table. */
} arm_bilinear_interp_instance_q7;

/**
 * @brief Q7 vector multiplication.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize);

/**
 * @brief Q15 vector multiplication.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Q31 vector multiplication.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_mult_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Floating-point vector multiplication.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_mult_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Instance structure for the Q15 CFFT/CIFFT function.
 */
typedef struct {
  uint16_t  fftLen;           /**< length of the FFT. */
  uint8_t   ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t   bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  q15_t *   pTwiddle;         /**< points to the Sin twiddle factor table. */
  uint16_t *pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t  twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t  bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q15;

/* Deprecated */
arm_status arm_cfft_radix2_init_q15(arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/* Deprecated */
void arm_cfft_radix2_q15(const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc);

/**
 * @brief Instance structure for the Q15 CFFT/CIFFT function.
 */
typedef struct {
  uint16_t  fftLen;           /**< length of the FFT. */
  uint8_t   ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t   bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  q15_t *   pTwiddle;         /**< points to the twiddle factor table. */
  uint16_t *pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t  twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t  bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q15;

/* Deprecated */
arm_status arm_cfft_radix4_init_q15(arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/* Deprecated */
void arm_cfft_radix4_q15(const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc);

/**
 * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
 */
typedef struct {
  uint16_t  fftLen;           /**< length of the FFT. */
  uint8_t   ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t   bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  q31_t *   pTwiddle;         /**< points to the Twiddle factor table. */
  uint16_t *pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t  twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t  bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q31;

/* Deprecated */
arm_status arm_cfft_radix2_init_q31(arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/* Deprecated */
void arm_cfft_radix2_q31(const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc);

/**
 * @brief Instance structure for the Q31 CFFT/CIFFT function.
 */
typedef struct {
  uint16_t  fftLen;           /**< length of the FFT. */
  uint8_t   ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t   bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  q31_t *   pTwiddle;         /**< points to the twiddle factor table. */
  uint16_t *pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t  twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t  bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q31;

/* Deprecated */
void arm_cfft_radix4_q31(const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc);

/* Deprecated */
arm_status arm_cfft_radix4_init_q31(arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/**
 * @brief Instance structure for the floating-point CFFT/CIFFT function.
 */
typedef struct {
  uint16_t   fftLen;           /**< length of the FFT. */
  uint8_t    ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t    bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
  uint16_t * pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t   twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t   bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
  float32_t  onebyfftLen;      /**< value of 1/fftLen. */
} arm_cfft_radix2_instance_f32;

/* Deprecated */
arm_status arm_cfft_radix2_init_f32(arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/* Deprecated */
void arm_cfft_radix2_f32(const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc);

/**
 * @brief Instance structure for the floating-point CFFT/CIFFT function.
 */
typedef struct {
  uint16_t   fftLen;           /**< length of the FFT. */
  uint8_t    ifftFlag;         /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
  uint8_t    bitReverseFlag;   /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
  float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
  uint16_t * pBitRevTable;     /**< points to the bit reversal table. */
  uint16_t   twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  uint16_t   bitRevFactor;     /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
  float32_t  onebyfftLen;      /**< value of 1/fftLen. */
} arm_cfft_radix4_instance_f32;

/* Deprecated */
arm_status arm_cfft_radix4_init_f32(arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag);

/* Deprecated */
void arm_cfft_radix4_f32(const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc);

/**
 * @brief Instance structure for the fixed-point CFFT/CIFFT function.
 */
typedef struct {
  uint16_t        fftLen;       /**< length of the FFT. */
  const q15_t *   pTwiddle;     /**< points to the Twiddle factor table. */
  const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
  uint16_t        bitRevLength; /**< bit reversal table length. */
} arm_cfft_instance_q15;

void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag);

/**
 * @brief Instance structure for the fixed-point CFFT/CIFFT function.
 */
typedef struct {
  uint16_t        fftLen;       /**< length of the FFT. */
  const q31_t *   pTwiddle;     /**< points to the Twiddle factor table. */
  const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
  uint16_t        bitRevLength; /**< bit reversal table length. */
} arm_cfft_instance_q31;

void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag);

/**
 * @brief Instance structure for the floating-point CFFT/CIFFT function.
 */
typedef struct {
  uint16_t         fftLen;       /**< length of the FFT. */
  const float32_t *pTwiddle;     /**< points to the Twiddle factor table. */
  const uint16_t * pBitRevTable; /**< points to the bit reversal table. */
  uint16_t         bitRevLength; /**< bit reversal table length. */
} arm_cfft_instance_f32;

void arm_cfft_f32(const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag);

/**
 * @brief Instance structure for the Q15 RFFT/RIFFT function.
 */
typedef struct {
  uint32_t                     fftLenReal;        /**< length of the real FFT. */
  uint8_t                      ifftFlagR;         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
  uint8_t                      bitReverseFlagR;   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
  uint32_t                     twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  q15_t *                      pTwiddleAReal;     /**< points to the real twiddle factor table. */
  q15_t *                      pTwiddleBReal;     /**< points to the imag twiddle factor table. */
  const arm_cfft_instance_q15 *pCfft;             /**< points to the complex FFT instance. */
} arm_rfft_instance_q15;

arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag);

void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst);

/**
 * @brief Instance structure for the Q31 RFFT/RIFFT function.
 */
typedef struct {
  uint32_t                     fftLenReal;        /**< length of the real FFT. */
  uint8_t                      ifftFlagR;         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
  uint8_t                      bitReverseFlagR;   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
  uint32_t                     twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  q31_t *                      pTwiddleAReal;     /**< points to the real twiddle factor table. */
  q31_t *                      pTwiddleBReal;     /**< points to the imag twiddle factor table. */
  const arm_cfft_instance_q31 *pCfft;             /**< points to the complex FFT instance. */
} arm_rfft_instance_q31;

arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag);

void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst);

/**
 * @brief Instance structure for the floating-point RFFT/RIFFT function.
 */
typedef struct {
  uint32_t                      fftLenReal;        /**< length of the real FFT. */
  uint16_t                      fftLenBy2;         /**< length of the complex FFT. */
  uint8_t                       ifftFlagR;         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
  uint8_t                       bitReverseFlagR;   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
  uint32_t                      twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
  float32_t *                   pTwiddleAReal;     /**< points to the real twiddle factor table. */
  float32_t *                   pTwiddleBReal;     /**< points to the imag twiddle factor table. */
  arm_cfft_radix4_instance_f32 *pCfft;             /**< points to the complex FFT instance. */
} arm_rfft_instance_f32;

arm_status arm_rfft_init_f32(arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag);

void arm_rfft_f32(const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst);

/**
 * @brief Instance structure for the floating-point RFFT/RIFFT function.
 */
typedef struct {
  arm_cfft_instance_f32 Sint;         /**< Internal CFFT structure. */
  uint16_t              fftLenRFFT;   /**< length of the real sequence */
  float32_t *           pTwiddleRFFT; /**< Twiddle factors real stage  */
} arm_rfft_fast_instance_f32;

arm_status arm_rfft_fast_init_f32(arm_rfft_fast_instance_f32 *S, uint16_t fftLen);

void arm_rfft_fast_f32(arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, uint8_t ifftFlag);

/**
 * @brief Instance structure for the floating-point DCT4/IDCT4 function.
 */
typedef struct {
  uint16_t                      N;          /**< length of the DCT4. */
  uint16_t                      Nby2;       /**< half of the length of the DCT4. */
  float32_t                     normalize;  /**< normalizing factor. */
  float32_t *                   pTwiddle;   /**< points to the twiddle factor table. */
  float32_t *                   pCosFactor; /**< points to the cosFactor table. */
  arm_rfft_instance_f32 *       pRfft;      /**< points to the real FFT instance. */
  arm_cfft_radix4_instance_f32 *pCfft;      /**< points to the complex FFT instance. */
} arm_dct4_instance_f32;

/**
 * @brief  Initialization function for the floating-point DCT4/IDCT4.
 * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
 * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
 * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
 * @param[in]     N          length of the DCT4.
 * @param[in]     Nby2       half of the length of the DCT4.
 * @param[in]     normalize  normalizing factor.
 * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
 */
arm_status arm_dct4_init_f32(arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize);

/**
 * @brief Processing function for the floating-point DCT4/IDCT4.
 * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
 * @param[in]     pState         points to state buffer.
 * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
 */
void arm_dct4_f32(const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer);

/**
 * @brief Instance structure for the Q31 DCT4/IDCT4 function.
 */
typedef struct {
  uint16_t                      N;          /**< length of the DCT4. */
  uint16_t                      Nby2;       /**< half of the length of the DCT4. */
  q31_t                         normalize;  /**< normalizing factor. */
  q31_t *                       pTwiddle;   /**< points to the twiddle factor table. */
  q31_t *                       pCosFactor; /**< points to the cosFactor table. */
  arm_rfft_instance_q31 *       pRfft;      /**< points to the real FFT instance. */
  arm_cfft_radix4_instance_q31 *pCfft;      /**< points to the complex FFT instance. */
} arm_dct4_instance_q31;

/**
 * @brief  Initialization function for the Q31 DCT4/IDCT4.
 * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
 * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
 * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
 * @param[in]     N          length of the DCT4.
 * @param[in]     Nby2       half of the length of the DCT4.
 * @param[in]     normalize  normalizing factor.
 * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
 */
arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize);

/**
 * @brief Processing function for the Q31 DCT4/IDCT4.
 * @param[in]     S              points to an instance of the Q31 DCT4 structure.
 * @param[in]     pState         points to state buffer.
 * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
 */
void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer);

/**
 * @brief Instance structure for the Q15 DCT4/IDCT4 function.
 */
typedef struct {
  uint16_t                      N;          /**< length of the DCT4. */
  uint16_t                      Nby2;       /**< half of the length of the DCT4. */
  q15_t                         normalize;  /**< normalizing factor. */
  q15_t *                       pTwiddle;   /**< points to the twiddle factor table. */
  q15_t *                       pCosFactor; /**< points to the cosFactor table. */
  arm_rfft_instance_q15 *       pRfft;      /**< points to the real FFT instance. */
  arm_cfft_radix4_instance_q15 *pCfft;      /**< points to the complex FFT instance. */
} arm_dct4_instance_q15;

/**
 * @brief  Initialization function for the Q15 DCT4/IDCT4.
 * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
 * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
 * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
 * @param[in]     N          length of the DCT4.
 * @param[in]     Nby2       half of the length of the DCT4.
 * @param[in]     normalize  normalizing factor.
 * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
 */
arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize);

/**
 * @brief Processing function for the Q15 DCT4/IDCT4.
 * @param[in]     S              points to an instance of the Q15 DCT4 structure.
 * @param[in]     pState         points to state buffer.
 * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
 */
void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer);

/**
 * @brief Floating-point vector addition.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_add_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Q7 vector addition.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_add_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize);

/**
 * @brief Q15 vector addition.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_add_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Q31 vector addition.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_add_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Floating-point vector subtraction.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_sub_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Q7 vector subtraction.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_sub_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize);

/**
 * @brief Q15 vector subtraction.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_sub_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Q31 vector subtraction.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_sub_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Multiplies a floating-point vector by a scalar.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  scale      scale factor to be applied
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_scale_f32(float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Multiplies a Q7 vector by a scalar.
 * @param[in]  pSrc        points to the input vector
 * @param[in]  scaleFract  fractional portion of the scale value
 * @param[in]  shift       number of bits to shift the result by
 * @param[out] pDst        points to the output vector
 * @param[in]  blockSize   number of samples in the vector
 */
void arm_scale_q7(q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize);

/**
 * @brief Multiplies a Q15 vector by a scalar.
 * @param[in]  pSrc        points to the input vector
 * @param[in]  scaleFract  fractional portion of the scale value
 * @param[in]  shift       number of bits to shift the result by
 * @param[out] pDst        points to the output vector
 * @param[in]  blockSize   number of samples in the vector
 */
void arm_scale_q15(q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Multiplies a Q31 vector by a scalar.
 * @param[in]  pSrc        points to the input vector
 * @param[in]  scaleFract  fractional portion of the scale value
 * @param[in]  shift       number of bits to shift the result by
 * @param[out] pDst        points to the output vector
 * @param[in]  blockSize   number of samples in the vector
 */
void arm_scale_q31(q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Q7 vector absolute value.
 * @param[in]  pSrc       points to the input buffer
 * @param[out] pDst       points to the output buffer
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_abs_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief Floating-point vector absolute value.
 * @param[in]  pSrc       points to the input buffer
 * @param[out] pDst       points to the output buffer
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_abs_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Q15 vector absolute value.
 * @param[in]  pSrc       points to the input buffer
 * @param[out] pDst       points to the output buffer
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_abs_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Q31 vector absolute value.
 * @param[in]  pSrc       points to the input buffer
 * @param[out] pDst       points to the output buffer
 * @param[in]  blockSize  number of samples in each vector
 */
void arm_abs_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Dot product of floating-point vectors.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[in]  blockSize  number of samples in each vector
 * @param[out] result     output result returned here
 */
void arm_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result);

/**
 * @brief Dot product of Q7 vectors.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[in]  blockSize  number of samples in each vector
 * @param[out] result     output result returned here
 */
void arm_dot_prod_q7(q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result);

/**
 * @brief Dot product of Q15 vectors.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[in]  blockSize  number of samples in each vector
 * @param[out] result     output result returned here
 */
void arm_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result);

/**
 * @brief Dot product of Q31 vectors.
 * @param[in]  pSrcA      points to the first input vector
 * @param[in]  pSrcB      points to the second input vector
 * @param[in]  blockSize  number of samples in each vector
 * @param[out] result     output result returned here
 */
void arm_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result);

/**
 * @brief  Shifts the elements of a Q7 vector a specified number of bits.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_shift_q7(q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Shifts the elements of a Q15 vector a specified number of bits.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_shift_q15(q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Shifts the elements of a Q31 vector a specified number of bits.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_shift_q31(q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Adds a constant offset to a floating-point vector.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  offset     is the offset to be added
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_offset_f32(float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Adds a constant offset to a Q7 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  offset     is the offset to be added
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_offset_q7(q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Adds a constant offset to a Q15 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  offset     is the offset to be added
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_offset_q15(q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Adds a constant offset to a Q31 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[in]  offset     is the offset to be added
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_offset_q31(q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Negates the elements of a floating-point vector.
 * @param[in]  pSrc       points to the input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_negate_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Negates the elements of a Q7 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_negate_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Negates the elements of a Q15 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_negate_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Negates the elements of a Q31 vector.
 * @param[in]  pSrc       points to the input vector
 * @param[out] pDst       points to the output vector
 * @param[in]  blockSize  number of samples in the vector
 */
void arm_negate_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Copies the elements of a floating-point vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_copy_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Copies the elements of a Q7 vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_copy_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Copies the elements of a Q15 vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_copy_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Copies the elements of a Q31 vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_copy_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Fills a constant value into a floating-point vector.
 * @param[in]  value      input value to be filled
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Fills a constant value into a Q7 vector.
 * @param[in]  value      input value to be filled
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Fills a constant value into a Q15 vector.
 * @param[in]  value      input value to be filled
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Fills a constant value into a Q31 vector.
 * @param[in]  value      input value to be filled
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Convolution of floating-point sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
 */
void arm_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst);

/**
 * @brief Convolution of Q15 sequences.
 * @param[in]  pSrcA      points to the first input sequence.
 * @param[in]  srcALen    length of the first input sequence.
 * @param[in]  pSrcB      points to the second input sequence.
 * @param[in]  srcBLen    length of the second input sequence.
 * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
 * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
 */
void arm_conv_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Convolution of Q15 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
 */
void arm_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst);

/**
 * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
 */
void arm_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst);

/**
 * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA      points to the first input sequence.
 * @param[in]  srcALen    length of the first input sequence.
 * @param[in]  pSrcB      points to the second input sequence.
 * @param[in]  srcBLen    length of the second input sequence.
 * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
 * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
 */
void arm_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Convolution of Q31 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
 */
void arm_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst);

/**
 * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
 */
void arm_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst);

/**
 * @brief Convolution of Q7 sequences.
 * @param[in]  pSrcA      points to the first input sequence.
 * @param[in]  srcALen    length of the first input sequence.
 * @param[in]  pSrcB      points to the second input sequence.
 * @param[in]  srcBLen    length of the second input sequence.
 * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
 * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
 */
void arm_conv_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Convolution of Q7 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
 */
void arm_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst);

/**
 * @brief Partial convolution of floating-point sequences.
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Partial convolution of Q15 sequences.
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Partial convolution of Q15 sequences.
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Partial convolution of Q31 sequences.
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Partial convolution of Q7 sequences
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Partial convolution of Q7 sequences.
 * @param[in]  pSrcA       points to the first input sequence.
 * @param[in]  srcALen     length of the first input sequence.
 * @param[in]  pSrcB       points to the second input sequence.
 * @param[in]  srcBLen     length of the second input sequence.
 * @param[out] pDst        points to the block of output data
 * @param[in]  firstIndex  is the first output sample to start with.
 * @param[in]  numPoints   is the number of output points to be computed.
 * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
 */
arm_status arm_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints);

/**
 * @brief Instance structure for the Q15 FIR decimator.
 */
typedef struct {
  uint8_t  M;       /**< decimation factor. */
  uint16_t numTaps; /**< number of coefficients in the filter. */
  q15_t *  pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
  q15_t *  pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_q15;

/**
 * @brief Instance structure for the Q31 FIR decimator.
 */
typedef struct {
  uint8_t  M;       /**< decimation factor. */
  uint16_t numTaps; /**< number of coefficients in the filter. */
  q31_t *  pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
  q31_t *  pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_q31;

/**
 * @brief Instance structure for the floating-point FIR decimator.
 */
typedef struct {
  uint8_t    M;       /**< decimation factor. */
  uint16_t   numTaps; /**< number of coefficients in the filter. */
  float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
  float32_t *pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
} arm_fir_decimate_instance_f32;

/**
 * @brief Processing function for the floating-point FIR decimator.
 * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_decimate_f32(const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point FIR decimator.
 * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
 * @param[in]     numTaps    number of coefficients in the filter.
 * @param[in]     M          decimation factor.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * blockSize is not a multiple of M.
 */
arm_status arm_fir_decimate_init_f32(arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q15 FIR decimator.
 * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_decimate_fast_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q15 FIR decimator.
 * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
 * @param[in]     numTaps    number of coefficients in the filter.
 * @param[in]     M          decimation factor.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * blockSize is not a multiple of M.
 */
arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 FIR decimator.
 * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
 * @param[in]  pSrc  points to the block of input data.
 * @param[out] pDst  points to the block of output data
 * @param[in] blockSize number of input samples to process per call.
 */
void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
 * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_decimate_fast_q31(arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q31 FIR decimator.
 * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
 * @param[in]     numTaps    number of coefficients in the filter.
 * @param[in]     M          decimation factor.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * blockSize is not a multiple of M.
 */
arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize);

/**
 * @brief Instance structure for the Q15 FIR interpolator.
 */
typedef struct {
  uint8_t  L;           /**< upsample factor. */
  uint16_t phaseLength; /**< length of each polyphase filter component. */
  q15_t *  pCoeffs;     /**< points to the coefficient array. The array is of length L*phaseLength. */
  q15_t *  pState;      /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} arm_fir_interpolate_instance_q15;

/**
 * @brief Instance structure for the Q31 FIR interpolator.
 */
typedef struct {
  uint8_t  L;           /**< upsample factor. */
  uint16_t phaseLength; /**< length of each polyphase filter component. */
  q31_t *  pCoeffs;     /**< points to the coefficient array. The array is of length L*phaseLength. */
  q31_t *  pState;      /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
} arm_fir_interpolate_instance_q31;

/**
 * @brief Instance structure for the floating-point FIR interpolator.
 */
typedef struct {
  uint8_t    L;           /**< upsample factor. */
  uint16_t   phaseLength; /**< length of each polyphase filter component. */
  float32_t *pCoeffs;     /**< points to the coefficient array. The array is of length L*phaseLength. */
  float32_t *pState;      /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
} arm_fir_interpolate_instance_f32;

/**
 * @brief Processing function for the Q15 FIR interpolator.
 * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_interpolate_q15(const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q15 FIR interpolator.
 * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
 * @param[in]     L          upsample factor.
 * @param[in]     numTaps    number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficient buffer.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * the filter length numTaps is not a multiple of the interpolation factor L.
 */
arm_status arm_fir_interpolate_init_q15(arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 FIR interpolator.
 * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_interpolate_q31(const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q31 FIR interpolator.
 * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
 * @param[in]     L          upsample factor.
 * @param[in]     numTaps    number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficient buffer.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * the filter length numTaps is not a multiple of the interpolation factor L.
 */
arm_status arm_fir_interpolate_init_q31(arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the floating-point FIR interpolator.
 * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of input samples to process per call.
 */
void arm_fir_interpolate_f32(const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point FIR interpolator.
 * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
 * @param[in]     L          upsample factor.
 * @param[in]     numTaps    number of filter coefficients in the filter.
 * @param[in]     pCoeffs    points to the filter coefficient buffer.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     blockSize  number of input samples to process per call.
 * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
 * the filter length numTaps is not a multiple of the interpolation factor L.
 */
arm_status arm_fir_interpolate_init_f32(arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize);

/**
 * @brief Instance structure for the high precision Q31 Biquad cascade filter.
 */
typedef struct {
  uint8_t numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  q63_t * pState;    /**< points to the array of state coefficients.  The array is of length 4*numStages. */
  q31_t * pCoeffs;   /**< points to the array of coefficients.  The array is of length 5*numStages. */
  uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
} arm_biquad_cas_df1_32x64_ins_q31;

/**
 * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cas_df1_32x64_q31(const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
 */
void arm_biquad_cas_df1_32x64_init_q31(arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift);

/**
 * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
 */
typedef struct {
  uint8_t    numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  float32_t *pState;    /**< points to the array of state coefficients.  The array is of length 2*numStages. */
  float32_t *pCoeffs;   /**< points to the array of coefficients.  The array is of length 5*numStages. */
} arm_biquad_cascade_df2T_instance_f32;

/**
 * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
 */
typedef struct {
  uint8_t    numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  float32_t *pState;    /**< points to the array of state coefficients.  The array is of length 4*numStages. */
  float32_t *pCoeffs;   /**< points to the array of coefficients.  The array is of length 5*numStages. */
} arm_biquad_cascade_stereo_df2T_instance_f32;

/**
 * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
 */
typedef struct {
  uint8_t    numStages; /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
  float64_t *pState;    /**< points to the array of state coefficients.  The array is of length 2*numStages. */
  float64_t *pCoeffs;   /**< points to the array of coefficients.  The array is of length 5*numStages. */
} arm_biquad_cascade_df2T_instance_f64;

/**
 * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
 * @param[in]  S          points to an instance of the filter data structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df2T_f32(const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
 * @param[in]  S          points to an instance of the filter data structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_stereo_df2T_f32(const arm_biquad_cascade_stereo_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
 * @param[in]  S          points to an instance of the filter data structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_biquad_cascade_df2T_f64(const arm_biquad_cascade_df2T_instance_f64 *S, float64_t *pSrc, float64_t *pDst, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
 * @param[in,out] S          points to an instance of the filter data structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 */
void arm_biquad_cascade_df2T_init_f32(arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState);

/**
 * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
 * @param[in,out] S          points to an instance of the filter data structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 */
void arm_biquad_cascade_stereo_df2T_init_f32(arm_biquad_cascade_stereo_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState);

/**
 * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
 * @param[in,out] S          points to an instance of the filter data structure.
 * @param[in]     numStages  number of 2nd order stages in the filter.
 * @param[in]     pCoeffs    points to the filter coefficients.
 * @param[in]     pState     points to the state buffer.
 */
void arm_biquad_cascade_df2T_init_f64(arm_biquad_cascade_df2T_instance_f64 *S, uint8_t numStages, float64_t *pCoeffs, float64_t *pState);

/**
 * @brief Instance structure for the Q15 FIR lattice filter.
 */
typedef struct {
  uint16_t numStages; /**< number of filter stages. */
  q15_t *  pState;    /**< points to the state variable array. The array is of length numStages. */
  q15_t *  pCoeffs;   /**< points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_q15;

/**
 * @brief Instance structure for the Q31 FIR lattice filter.
 */
typedef struct {
  uint16_t numStages; /**< number of filter stages. */
  q31_t *  pState;    /**< points to the state variable array. The array is of length numStages. */
  q31_t *  pCoeffs;   /**< points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_q31;

/**
 * @brief Instance structure for the floating-point FIR lattice filter.
 */
typedef struct {
  uint16_t   numStages; /**< number of filter stages. */
  float32_t *pState;    /**< points to the state variable array. The array is of length numStages. */
  float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numStages. */
} arm_fir_lattice_instance_f32;

/**
 * @brief Initialization function for the Q15 FIR lattice filter.
 * @param[in] S          points to an instance of the Q15 FIR lattice structure.
 * @param[in] numStages  number of filter stages.
 * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
 * @param[in] pState     points to the state buffer.  The array is of length numStages.
 */
void arm_fir_lattice_init_q15(arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState);

/**
 * @brief Processing function for the Q15 FIR lattice filter.
 * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_lattice_q15(const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Initialization function for the Q31 FIR lattice filter.
 * @param[in] S          points to an instance of the Q31 FIR lattice structure.
 * @param[in] numStages  number of filter stages.
 * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
 * @param[in] pState     points to the state buffer.   The array is of length numStages.
 */
void arm_fir_lattice_init_q31(arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState);

/**
 * @brief Processing function for the Q31 FIR lattice filter.
 * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_lattice_q31(const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Initialization function for the floating-point FIR lattice filter.
 * @param[in] S          points to an instance of the floating-point FIR lattice structure.
 * @param[in] numStages  number of filter stages.
 * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
 * @param[in] pState     points to the state buffer.  The array is of length numStages.
 */
void arm_fir_lattice_init_f32(arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState);

/**
 * @brief Processing function for the floating-point FIR lattice filter.
 * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data
 * @param[in]  blockSize  number of samples to process.
 */
void arm_fir_lattice_f32(const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Instance structure for the Q15 IIR lattice filter.
 */
typedef struct {
  uint16_t numStages; /**< number of stages in the filter. */
  q15_t *  pState;    /**< points to the state variable array. The array is of length numStages+blockSize. */
  q15_t *  pkCoeffs;  /**< points to the reflection coefficient array. The array is of length numStages. */
  q15_t *  pvCoeffs;  /**< points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_q15;

/**
 * @brief Instance structure for the Q31 IIR lattice filter.
 */
typedef struct {
  uint16_t numStages; /**< number of stages in the filter. */
  q31_t *  pState;    /**< points to the state variable array. The array is of length numStages+blockSize. */
  q31_t *  pkCoeffs;  /**< points to the reflection coefficient array. The array is of length numStages. */
  q31_t *  pvCoeffs;  /**< points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_q31;

/**
 * @brief Instance structure for the floating-point IIR lattice filter.
 */
typedef struct {
  uint16_t   numStages; /**< number of stages in the filter. */
  float32_t *pState;    /**< points to the state variable array. The array is of length numStages+blockSize. */
  float32_t *pkCoeffs;  /**< points to the reflection coefficient array. The array is of length numStages. */
  float32_t *pvCoeffs;  /**< points to the ladder coefficient array. The array is of length numStages+1. */
} arm_iir_lattice_instance_f32;

/**
 * @brief Processing function for the floating-point IIR lattice filter.
 * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_iir_lattice_f32(const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief Initialization function for the floating-point IIR lattice filter.
 * @param[in] S          points to an instance of the floating-point IIR lattice structure.
 * @param[in] numStages  number of stages in the filter.
 * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
 * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
 * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
 * @param[in] blockSize  number of samples to process.
 */
void arm_iir_lattice_init_f32(arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 IIR lattice filter.
 * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_iir_lattice_q31(const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Initialization function for the Q31 IIR lattice filter.
 * @param[in] S          points to an instance of the Q31 IIR lattice structure.
 * @param[in] numStages  number of stages in the filter.
 * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
 * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
 * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
 * @param[in] blockSize  number of samples to process.
 */
void arm_iir_lattice_init_q31(arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize);

/**
 * @brief Processing function for the Q15 IIR lattice filter.
 * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[out] pDst       points to the block of output data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_iir_lattice_q15(const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Initialization function for the Q15 IIR lattice filter.
 * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
 * @param[in] numStages  number of stages in the filter.
 * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
 * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
 * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
 * @param[in] blockSize  number of samples to process per call.
 */
void arm_iir_lattice_init_q15(arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize);

/**
 * @brief Instance structure for the floating-point LMS filter.
 */
typedef struct {
  uint16_t   numTaps; /**< number of coefficients in the filter. */
  float32_t *pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
  float32_t  mu;      /**< step size that controls filter coefficient updates. */
} arm_lms_instance_f32;

/**
 * @brief Processing function for floating-point LMS filter.
 * @param[in]  S          points to an instance of the floating-point LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_f32(const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize);

/**
 * @brief Initialization function for floating-point LMS filter.
 * @param[in] S          points to an instance of the floating-point LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to the coefficient buffer.
 * @param[in] pState     points to state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 */
void arm_lms_init_f32(arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize);

/**
 * @brief Instance structure for the Q15 LMS filter.
 */
typedef struct {
  uint16_t numTaps;   /**< number of coefficients in the filter. */
  q15_t *  pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q15_t *  pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
  q15_t    mu;        /**< step size that controls filter coefficient updates. */
  uint32_t postShift; /**< bit shift applied to coefficients. */
} arm_lms_instance_q15;

/**
 * @brief Initialization function for the Q15 LMS filter.
 * @param[in] S          points to an instance of the Q15 LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to the coefficient buffer.
 * @param[in] pState     points to the state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 * @param[in] postShift  bit shift applied to coefficients.
 */
void arm_lms_init_q15(arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift);

/**
 * @brief Processing function for Q15 LMS filter.
 * @param[in]  S          points to an instance of the Q15 LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_q15(const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize);

/**
 * @brief Instance structure for the Q31 LMS filter.
 */
typedef struct {
  uint16_t numTaps;   /**< number of coefficients in the filter. */
  q31_t *  pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q31_t *  pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
  q31_t    mu;        /**< step size that controls filter coefficient updates. */
  uint32_t postShift; /**< bit shift applied to coefficients. */
} arm_lms_instance_q31;

/**
 * @brief Processing function for Q31 LMS filter.
 * @param[in]  S          points to an instance of the Q15 LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_q31(const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize);

/**
 * @brief Initialization function for Q31 LMS filter.
 * @param[in] S          points to an instance of the Q31 LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to coefficient buffer.
 * @param[in] pState     points to state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 * @param[in] postShift  bit shift applied to coefficients.
 */
void arm_lms_init_q31(arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift);

/**
 * @brief Instance structure for the floating-point normalized LMS filter.
 */
typedef struct {
  uint16_t   numTaps; /**< number of coefficients in the filter. */
  float32_t *pState;  /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
  float32_t  mu;      /**< step size that control filter coefficient updates. */
  float32_t  energy;  /**< saves previous frame energy. */
  float32_t  x0;      /**< saves previous input sample. */
} arm_lms_norm_instance_f32;

/**
 * @brief Processing function for floating-point normalized LMS filter.
 * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_norm_f32(arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize);

/**
 * @brief Initialization function for floating-point normalized LMS filter.
 * @param[in] S          points to an instance of the floating-point LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to coefficient buffer.
 * @param[in] pState     points to state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 */
void arm_lms_norm_init_f32(arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize);

/**
 * @brief Instance structure for the Q31 normalized LMS filter.
 */
typedef struct {
  uint16_t numTaps;    /**< number of coefficients in the filter. */
  q31_t *  pState;     /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q31_t *  pCoeffs;    /**< points to the coefficient array. The array is of length numTaps. */
  q31_t    mu;         /**< step size that controls filter coefficient updates. */
  uint8_t  postShift;  /**< bit shift applied to coefficients. */
  q31_t *  recipTable; /**< points to the reciprocal initial value table. */
  q31_t    energy;     /**< saves previous frame energy. */
  q31_t    x0;         /**< saves previous input sample. */
} arm_lms_norm_instance_q31;

/**
 * @brief Processing function for Q31 normalized LMS filter.
 * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_norm_q31(arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize);

/**
 * @brief Initialization function for Q31 normalized LMS filter.
 * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to coefficient buffer.
 * @param[in] pState     points to state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 * @param[in] postShift  bit shift applied to coefficients.
 */
void arm_lms_norm_init_q31(arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift);

/**
 * @brief Instance structure for the Q15 normalized LMS filter.
 */
typedef struct {
  uint16_t numTaps;    /**< Number of coefficients in the filter. */
  q15_t *  pState;     /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
  q15_t *  pCoeffs;    /**< points to the coefficient array. The array is of length numTaps. */
  q15_t    mu;         /**< step size that controls filter coefficient updates. */
  uint8_t  postShift;  /**< bit shift applied to coefficients. */
  q15_t *  recipTable; /**< Points to the reciprocal initial value table. */
  q15_t    energy;     /**< saves previous frame energy. */
  q15_t    x0;         /**< saves previous input sample. */
} arm_lms_norm_instance_q15;

/**
 * @brief Processing function for Q15 normalized LMS filter.
 * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
 * @param[in]  pSrc       points to the block of input data.
 * @param[in]  pRef       points to the block of reference data.
 * @param[out] pOut       points to the block of output data.
 * @param[out] pErr       points to the block of error data.
 * @param[in]  blockSize  number of samples to process.
 */
void arm_lms_norm_q15(arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize);

/**
 * @brief Initialization function for Q15 normalized LMS filter.
 * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
 * @param[in] numTaps    number of filter coefficients.
 * @param[in] pCoeffs    points to coefficient buffer.
 * @param[in] pState     points to state buffer.
 * @param[in] mu         step size that controls filter coefficient updates.
 * @param[in] blockSize  number of samples to process.
 * @param[in] postShift  bit shift applied to coefficients.
 */
void arm_lms_norm_init_q15(arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift);

/**
 * @brief Correlation of floating-point sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */
void arm_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst);

/**
 * @brief Correlation of Q15 sequences
 * @param[in]  pSrcA     points to the first input sequence.
 * @param[in]  srcALen   length of the first input sequence.
 * @param[in]  pSrcB     points to the second input sequence.
 * @param[in]  srcBLen   length of the second input sequence.
 * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 */
void arm_correlate_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch);

/**
 * @brief Correlation of Q15 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */

void arm_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst);

/**
 * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */

void arm_correlate_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst);

/**
 * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
 * @param[in]  pSrcA     points to the first input sequence.
 * @param[in]  srcALen   length of the first input sequence.
 * @param[in]  pSrcB     points to the second input sequence.
 * @param[in]  srcBLen   length of the second input sequence.
 * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 */
void arm_correlate_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch);

/**
 * @brief Correlation of Q31 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */
void arm_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst);

/**
 * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */
void arm_correlate_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst);

/**
 * @brief Correlation of Q7 sequences.
 * @param[in]  pSrcA      points to the first input sequence.
 * @param[in]  srcALen    length of the first input sequence.
 * @param[in]  pSrcB      points to the second input sequence.
 * @param[in]  srcBLen    length of the second input sequence.
 * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
 * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
 */
void arm_correlate_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2);

/**
 * @brief Correlation of Q7 sequences.
 * @param[in]  pSrcA    points to the first input sequence.
 * @param[in]  srcALen  length of the first input sequence.
 * @param[in]  pSrcB    points to the second input sequence.
 * @param[in]  srcBLen  length of the second input sequence.
 * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
 */
void arm_correlate_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst);

/**
 * @brief Instance structure for the floating-point sparse FIR filter.
 */
typedef struct {
  uint16_t   numTaps;    /**< number of coefficients in the filter. */
  uint16_t   stateIndex; /**< state buffer index.  Points to the oldest sample in the state buffer. */
  float32_t *pState;     /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
  float32_t *pCoeffs;    /**< points to the coefficient array. The array is of length numTaps.*/
  uint16_t   maxDelay;   /**< maximum offset specified by the pTapDelay array. */
  int32_t *  pTapDelay;  /**< points to the array of delay values.  The array is of length numTaps. */
} arm_fir_sparse_instance_f32;

/**
 * @brief Instance structure for the Q31 sparse FIR filter.
 */
typedef struct {
  uint16_t numTaps;    /**< number of coefficients in the filter. */
  uint16_t stateIndex; /**< state buffer index.  Points to the oldest sample in the state buffer. */
  q31_t *  pState;     /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
  q31_t *  pCoeffs;    /**< points to the coefficient array. The array is of length numTaps.*/
  uint16_t maxDelay;   /**< maximum offset specified by the pTapDelay array. */
  int32_t *pTapDelay;  /**< points to the array of delay values.  The array is of length numTaps. */
} arm_fir_sparse_instance_q31;

/**
 * @brief Instance structure for the Q15 sparse FIR filter.
 */
typedef struct {
  uint16_t numTaps;    /**< number of coefficients in the filter. */
  uint16_t stateIndex; /**< state buffer index.  Points to the oldest sample in the state buffer. */
  q15_t *  pState;     /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
  q15_t *  pCoeffs;    /**< points to the coefficient array. The array is of length numTaps.*/
  uint16_t maxDelay;   /**< maximum offset specified by the pTapDelay array. */
  int32_t *pTapDelay;  /**< points to the array of delay values.  The array is of length numTaps. */
} arm_fir_sparse_instance_q15;

/**
 * @brief Instance structure for the Q7 sparse FIR filter.
 */
typedef struct {
  uint16_t numTaps;    /**< number of coefficients in the filter. */
  uint16_t stateIndex; /**< state buffer index.  Points to the oldest sample in the state buffer. */
  q7_t *   pState;     /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
  q7_t *   pCoeffs;    /**< points to the coefficient array. The array is of length numTaps.*/
  uint16_t maxDelay;   /**< maximum offset specified by the pTapDelay array. */
  int32_t *pTapDelay;  /**< points to the array of delay values.  The array is of length numTaps. */
} arm_fir_sparse_instance_q7;

/**
 * @brief Processing function for the floating-point sparse FIR filter.
 * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
 * @param[in]  pSrc        points to the block of input data.
 * @param[out] pDst        points to the block of output data
 * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
 * @param[in]  blockSize   number of input samples to process per call.
 */
void arm_fir_sparse_f32(arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize);

/**
 * @brief  Initialization function for the floating-point sparse FIR filter.
 * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
 * @param[in]     numTaps    number of nonzero coefficients in the filter.
 * @param[in]     pCoeffs    points to the array of filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     pTapDelay  points to the array of offset times.
 * @param[in]     maxDelay   maximum offset time supported.
 * @param[in]     blockSize  number of samples that will be processed per block.
 */
void arm_fir_sparse_init_f32(arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize);

/**
 * @brief Processing function for the Q31 sparse FIR filter.
 * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
 * @param[in]  pSrc        points to the block of input data.
 * @param[out] pDst        points to the block of output data
 * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
 * @param[in]  blockSize   number of input samples to process per call.
 */
void arm_fir_sparse_q31(arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q31 sparse FIR filter.
 * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
 * @param[in]     numTaps    number of nonzero coefficients in the filter.
 * @param[in]     pCoeffs    points to the array of filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     pTapDelay  points to the array of offset times.
 * @param[in]     maxDelay   maximum offset time supported.
 * @param[in]     blockSize  number of samples that will be processed per block.
 */
void arm_fir_sparse_init_q31(arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize);

/**
 * @brief Processing function for the Q15 sparse FIR filter.
 * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
 * @param[in]  pSrc         points to the block of input data.
 * @param[out] pDst         points to the block of output data
 * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
 * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
 * @param[in]  blockSize    number of input samples to process per call.
 */
void arm_fir_sparse_q15(arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q15 sparse FIR filter.
 * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
 * @param[in]     numTaps    number of nonzero coefficients in the filter.
 * @param[in]     pCoeffs    points to the array of filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     pTapDelay  points to the array of offset times.
 * @param[in]     maxDelay   maximum offset time supported.
 * @param[in]     blockSize  number of samples that will be processed per block.
 */
void arm_fir_sparse_init_q15(arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize);

/**
 * @brief Processing function for the Q7 sparse FIR filter.
 * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
 * @param[in]  pSrc         points to the block of input data.
 * @param[out] pDst         points to the block of output data
 * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
 * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
 * @param[in]  blockSize    number of input samples to process per call.
 */
void arm_fir_sparse_q7(arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize);

/**
 * @brief  Initialization function for the Q7 sparse FIR filter.
 * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
 * @param[in]     numTaps    number of nonzero coefficients in the filter.
 * @param[in]     pCoeffs    points to the array of filter coefficients.
 * @param[in]     pState     points to the state buffer.
 * @param[in]     pTapDelay  points to the array of offset times.
 * @param[in]     maxDelay   maximum offset time supported.
 * @param[in]     blockSize  number of samples that will be processed per block.
 */
void arm_fir_sparse_init_q7(arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize);

/**
 * @brief  Floating-point sin_cos function.
 * @param[in]  theta   input value in degrees
 * @param[out] pSinVal  points to the processed sine output.
 * @param[out] pCosVal  points to the processed cos output.
 */
void arm_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCosVal);

/**
 * @brief  Q31 sin_cos function.
 * @param[in]  theta    scaled input value in degrees
 * @param[out] pSinVal  points to the processed sine output.
 * @param[out] pCosVal  points to the processed cosine output.
 */
void arm_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal);

/**
 * @brief  Floating-point complex conjugate.
 * @param[in]  pSrc        points to the input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_conj_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples);

/**
 * @brief  Q31 complex conjugate.
 * @param[in]  pSrc        points to the input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_conj_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples);

/**
 * @brief  Q15 complex conjugate.
 * @param[in]  pSrc        points to the input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_conj_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples);

/**
 * @brief  Floating-point complex magnitude squared
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_squared_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples);

/**
 * @brief  Q31 complex magnitude squared
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_squared_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples);

/**
 * @brief  Q15 complex magnitude squared
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_squared_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples);

/**
 * @ingroup groupController
 */

/**
 * @defgroup PID PID Motor Control
 *
 * A Proportional Integral Derivative (PID) controller is a generic feedback control
 * loop mechanism widely used in industrial control systems.
 * A PID controller is the most commonly used type of feedback controller.
 *
 * This set of functions implements (PID) controllers
 * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
 * of data and each call to the function returns a single processed value.
 * S points to an instance of the PID control data structure.  in
 * is the input sample value. The functions return the output value.
 *
 * \par Algorithm:
 * 
 *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
 *    A0 = Kp + Ki + Kd
 *    A1 = (-Kp ) - (2 * Kd )
 *    A2 = Kd  

 *
 * \par
 * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
 *
 * \par
 * \image html PID.gif "Proportional Integral Derivative Controller"
 *
 * \par
 * The PID controller calculates an "error" value as the difference between
 * the measured output and the reference input.
 * The controller attempts to minimize the error by adjusting the process control inputs.
 * The proportional value determines the reaction to the current error,
 * the integral value determines the reaction based on the sum of recent errors,
 * and the derivative value determines the reaction based on the rate at which the error has been changing.
 *
 * \par Instance Structure
 * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
 * A separate instance structure must be defined for each PID Controller.
 * There are separate instance structure declarations for each of the 3 supported data types.
 *
 * \par Reset Functions
 * There is also an associated reset function for each data type which clears the state array.
 *
 * \par Initialization Functions
 * There is also an associated initialization function for each data type.
 * The initialization function performs the following operations:
 * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
 * - Zeros out the values in the state buffer.
 *
 * \par
 * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
 *
 * \par Fixed-Point Behavior
 * Care must be taken when using the fixed-point versions of the PID Controller functions.
 * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
 * Refer to the function specific documentation below for usage guidelines.
 */

/**
 * @addtogroup PID
 * @{
 */

/**
 * @brief  Process function for the floating-point PID Control.
 * @param[in,out] S   is an instance of the floating-point PID Control structure
 * @param[in]     in  input sample to process
 * @return out processed output sample.
 */
static __INLINE float32_t arm_pid_f32(arm_pid_instance_f32 *S, float32_t in) {
  float32_t out;

  /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
  out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);

  /* Update state */
  S->state[1] = S->state[0];
  S->state[0] = in;
  S->state[2] = out;

  /* return to application */
  return (out);
}

/**
 * @brief  Process function for the Q31 PID Control.
 * @param[in,out] S  points to an instance of the Q31 PID Control structure
 * @param[in]     in  input sample to process
 * @return out processed output sample.
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using an internal 64-bit accumulator.
 * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
 * Thus, if the accumulator result overflows it wraps around rather than clip.
 * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
 * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
 */
static __INLINE q31_t arm_pid_q31(arm_pid_instance_q31 *S, q31_t in) {
  q63_t acc;
  q31_t out;

  /* acc = A0 * x[n]  */
  acc = (q63_t)S->A0 * in;

  /* acc += A1 * x[n-1] */
  acc += (q63_t)S->A1 * S->state[0];

  /* acc += A2 * x[n-2]  */
  acc += (q63_t)S->A2 * S->state[1];

  /* convert output to 1.31 format to add y[n-1] */
  out = (q31_t)(acc >> 31u);

  /* out += y[n-1] */
  out += S->state[2];

  /* Update state */
  S->state[1] = S->state[0];
  S->state[0] = in;
  S->state[2] = out;

  /* return to application */
  return (out);
}

/**
 * @brief  Process function for the Q15 PID Control.
 * @param[in,out] S   points to an instance of the Q15 PID Control structure
 * @param[in]     in  input sample to process
 * @return out processed output sample.
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using a 64-bit internal accumulator.
 * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
 * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
 * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
 * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
 * Lastly, the accumulator is saturated to yield a result in 1.15 format.
 */
static __INLINE q15_t arm_pid_q15(arm_pid_instance_q15 *S, q15_t in) {
  q63_t acc;
  q15_t out;

#ifndef ARM_MATH_CM0_FAMILY
  __SIMD32_TYPE *vstate;

  /* Implementation of PID controller */

  /* acc = A0 * x[n]  */
  acc = (q31_t)__SMUAD((uint32_t)S->A0, (uint32_t)in);

  /* acc += A1 * x[n-1] + A2 * x[n-2]  */
  vstate = __SIMD32_CONST(S->state);
  acc    = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
#else
  /* acc = A0 * x[n]  */
  acc = ((q31_t)S->A0) * in;

  /* acc += A1 * x[n-1] + A2 * x[n-2]  */
  acc += (q31_t)S->A1 * S->state[0];
  acc += (q31_t)S->A2 * S->state[1];
#endif

  /* acc += y[n-1] */
  acc += (q31_t)S->state[2] << 15;

  /* saturate the output */
  out = (q15_t)(__SSAT((acc >> 15), 16));

  /* Update state */
  S->state[1] = S->state[0];
  S->state[0] = in;
  S->state[2] = out;

  /* return to application */
  return (out);
}

/**
 * @} end of PID group
 */

/**
 * @brief Floating-point matrix inverse.
 * @param[in]  src   points to the instance of the input floating-point matrix structure.
 * @param[out] dst   points to the instance of the output floating-point matrix structure.
 * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
 * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
 */
arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst);

/**
 * @brief Floating-point matrix inverse.
 * @param[in]  src   points to the instance of the input floating-point matrix structure.
 * @param[out] dst   points to the instance of the output floating-point matrix structure.
 * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
 * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
 */
arm_status arm_mat_inverse_f64(const arm_matrix_instance_f64 *src, arm_matrix_instance_f64 *dst);

/**
 * @ingroup groupController
 */

/**
 * @defgroup clarke Vector Clarke Transform
 * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
 * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
 * in the two-phase orthogonal stator axis Ialpha and Ibeta.
 * When Ialpha is superposed with Ia as shown in the figure below
 * \image html clarke.gif Stator current space vector and its components in (a,b).
 * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
 * can be calculated using only Ia and Ib.
 *
 * The function operates on a single sample of data and each call to the function returns the processed output.
 * The library provides separate functions for Q31 and floating-point data types.
 * \par Algorithm
 * \image html clarkeFormula.gif
 * where Ia and Ib are the instantaneous stator phases and
 * pIalpha and pIbeta are the two coordinates of time invariant vector.
 * \par Fixed-Point Behavior
 * Care must be taken when using the Q31 version of the Clarke transform.
 * In particular, the overflow and saturation behavior of the accumulator used must be considered.
 * Refer to the function specific documentation below for usage guidelines.
 */

/**
 * @addtogroup clarke
 * @{
 */

/**
 *
 * @brief  Floating-point Clarke transform
 * @param[in]  Ia       input three-phase coordinate a
 * @param[in]  Ib       input three-phase coordinate b
 * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
 * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
 */
static __INLINE void arm_clarke_f32(float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta) {
  /* Calculate pIalpha using the equation, pIalpha = Ia */
  *pIalpha = Ia;

  /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
  *pIbeta = ((float32_t)0.57735026919 * Ia + (float32_t)1.15470053838 * Ib);
}

/**
 * @brief  Clarke transform for Q31 version
 * @param[in]  Ia       input three-phase coordinate a
 * @param[in]  Ib       input three-phase coordinate b
 * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
 * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using an internal 32-bit accumulator.
 * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
 * There is saturation on the addition, hence there is no risk of overflow.
 */
static __INLINE void arm_clarke_q31(q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta) {
  q31_t product1, product2; /* Temporary variables used to store intermediate results */

  /* Calculating pIalpha from Ia by equation pIalpha = Ia */
  *pIalpha = Ia;

  /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
  product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30);

  /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
  product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30);

  /* pIbeta is calculated by adding the intermediate products */
  *pIbeta = __QADD(product1, product2);
}

/**
 * @} end of clarke group
 */

/**
 * @brief  Converts the elements of the Q7 vector to Q31 vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_q7_to_q31(q7_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @ingroup groupController
 */

/**
 * @defgroup inv_clarke Vector Inverse Clarke Transform
 * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
 *
 * The function operates on a single sample of data and each call to the function returns the processed output.
 * The library provides separate functions for Q31 and floating-point data types.
 * \par Algorithm
 * \image html clarkeInvFormula.gif
 * where pIa and pIb are the instantaneous stator phases and
 * Ialpha and Ibeta are the two coordinates of time invariant vector.
 * \par Fixed-Point Behavior
 * Care must be taken when using the Q31 version of the Clarke transform.
 * In particular, the overflow and saturation behavior of the accumulator used must be considered.
 * Refer to the function specific documentation below for usage guidelines.
 */

/**
 * @addtogroup inv_clarke
 * @{
 */

/**
 * @brief  Floating-point Inverse Clarke transform
 * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
 * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
 * @param[out] pIa     points to output three-phase coordinate a
 * @param[out] pIb     points to output three-phase coordinate b
 */
static __INLINE void arm_inv_clarke_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb) {
  /* Calculating pIa from Ialpha by equation pIa = Ialpha */
  *pIa = Ialpha;

  /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
  *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
}

/**
 * @brief  Inverse Clarke transform for Q31 version
 * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
 * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
 * @param[out] pIa     points to output three-phase coordinate a
 * @param[out] pIb     points to output three-phase coordinate b
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using an internal 32-bit accumulator.
 * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
 * There is saturation on the subtraction, hence there is no risk of overflow.
 */
static __INLINE void arm_inv_clarke_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb) {
  q31_t product1, product2; /* Temporary variables used to store intermediate results */

  /* Calculating pIa from Ialpha by equation pIa = Ialpha */
  *pIa = Ialpha;

  /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
  product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31);

  /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
  product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31);

  /* pIb is calculated by subtracting the products */
  *pIb = __QSUB(product2, product1);
}

/**
 * @} end of inv_clarke group
 */

/**
 * @brief  Converts the elements of the Q7 vector to Q15 vector.
 * @param[in]  pSrc       input pointer
 * @param[out] pDst       output pointer
 * @param[in]  blockSize  number of samples to process
 */
void arm_q7_to_q15(q7_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @ingroup groupController
 */

/**
 * @defgroup park Vector Park Transform
 *
 * Forward Park transform converts the input two-coordinate vector to flux and torque components.
 * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
 * from the stationary to the moving reference frame and control the spatial relationship between
 * the stator vector current and rotor flux vector.
 * If we consider the d axis aligned with the rotor flux, the diagram below shows the
 * current vector and the relationship from the two reference frames:
 * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
 *
 * The function operates on a single sample of data and each call to the function returns the processed output.
 * The library provides separate functions for Q31 and floating-point data types.
 * \par Algorithm
 * \image html parkFormula.gif
 * where Ialpha and Ibeta are the stator vector components,
 * pId and pIq are rotor vector components and cosVal and sinVal are the
 * cosine and sine values of theta (rotor flux position).
 * \par Fixed-Point Behavior
 * Care must be taken when using the Q31 version of the Park transform.
 * In particular, the overflow and saturation behavior of the accumulator used must be considered.
 * Refer to the function specific documentation below for usage guidelines.
 */

/**
 * @addtogroup park
 * @{
 */

/**
 * @brief Floating-point Park transform
 * @param[in]  Ialpha  input two-phase vector coordinate alpha
 * @param[in]  Ibeta   input two-phase vector coordinate beta
 * @param[out] pId     points to output   rotor reference frame d
 * @param[out] pIq     points to output   rotor reference frame q
 * @param[in]  sinVal  sine value of rotation angle theta
 * @param[in]  cosVal  cosine value of rotation angle theta
 *
 * The function implements the forward Park transform.
 *
 */
static __INLINE void arm_park_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal) {
  /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
  *pId = Ialpha * cosVal + Ibeta * sinVal;

  /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
  *pIq = -Ialpha * sinVal + Ibeta * cosVal;
}

/**
 * @brief  Park transform for Q31 version
 * @param[in]  Ialpha  input two-phase vector coordinate alpha
 * @param[in]  Ibeta   input two-phase vector coordinate beta
 * @param[out] pId     points to output rotor reference frame d
 * @param[out] pIq     points to output rotor reference frame q
 * @param[in]  sinVal  sine value of rotation angle theta
 * @param[in]  cosVal  cosine value of rotation angle theta
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using an internal 32-bit accumulator.
 * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
 * There is saturation on the addition and subtraction, hence there is no risk of overflow.
 */
static __INLINE void arm_park_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal) {
  q31_t product1, product2; /* Temporary variables used to store intermediate results */
  q31_t product3, product4; /* Temporary variables used to store intermediate results */

  /* Intermediate product is calculated by (Ialpha * cosVal) */
  product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31);

  /* Intermediate product is calculated by (Ibeta * sinVal) */
  product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31);

  /* Intermediate product is calculated by (Ialpha * sinVal) */
  product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31);

  /* Intermediate product is calculated by (Ibeta * cosVal) */
  product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31);

  /* Calculate pId by adding the two intermediate products 1 and 2 */
  *pId = __QADD(product1, product2);

  /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
  *pIq = __QSUB(product4, product3);
}

/**
 * @} end of park group
 */

/**
 * @brief  Converts the elements of the Q7 vector to floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q7_to_float(q7_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @ingroup groupController
 */

/**
 * @defgroup inv_park Vector Inverse Park transform
 * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
 *
 * The function operates on a single sample of data and each call to the function returns the processed output.
 * The library provides separate functions for Q31 and floating-point data types.
 * \par Algorithm
 * \image html parkInvFormula.gif
 * where pIalpha and pIbeta are the stator vector components,
 * Id and Iq are rotor vector components and cosVal and sinVal are the
 * cosine and sine values of theta (rotor flux position).
 * \par Fixed-Point Behavior
 * Care must be taken when using the Q31 version of the Park transform.
 * In particular, the overflow and saturation behavior of the accumulator used must be considered.
 * Refer to the function specific documentation below for usage guidelines.
 */

/**
 * @addtogroup inv_park
 * @{
 */

/**
 * @brief  Floating-point Inverse Park transform
 * @param[in]  Id       input coordinate of rotor reference frame d
 * @param[in]  Iq       input coordinate of rotor reference frame q
 * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
 * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
 * @param[in]  sinVal   sine value of rotation angle theta
 * @param[in]  cosVal   cosine value of rotation angle theta
 */
static __INLINE void arm_inv_park_f32(float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal) {
  /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
  *pIalpha = Id * cosVal - Iq * sinVal;

  /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
  *pIbeta = Id * sinVal + Iq * cosVal;
}

/**
 * @brief  Inverse Park transform for   Q31 version
 * @param[in]  Id       input coordinate of rotor reference frame d
 * @param[in]  Iq       input coordinate of rotor reference frame q
 * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
 * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
 * @param[in]  sinVal   sine value of rotation angle theta
 * @param[in]  cosVal   cosine value of rotation angle theta
 *
 * Scaling and Overflow Behavior:
 * \par
 * The function is implemented using an internal 32-bit accumulator.
 * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
 * There is saturation on the addition, hence there is no risk of overflow.
 */
static __INLINE void arm_inv_park_q31(q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal) {
  q31_t product1, product2; /* Temporary variables used to store intermediate results */
  q31_t product3, product4; /* Temporary variables used to store intermediate results */

  /* Intermediate product is calculated by (Id * cosVal) */
  product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31);

  /* Intermediate product is calculated by (Iq * sinVal) */
  product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31);

  /* Intermediate product is calculated by (Id * sinVal) */
  product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31);

  /* Intermediate product is calculated by (Iq * cosVal) */
  product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31);

  /* Calculate pIalpha by using the two intermediate products 1 and 2 */
  *pIalpha = __QSUB(product1, product2);

  /* Calculate pIbeta by using the two intermediate products 3 and 4 */
  *pIbeta = __QADD(product4, product3);
}

/**
 * @} end of Inverse park group
 */

/**
 * @brief  Converts the elements of the Q31 vector to floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q31_to_float(q31_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @ingroup groupInterpolation
 */

/**
 * @defgroup LinearInterpolate Linear Interpolation
 *
 * Linear interpolation is a method of curve fitting using linear polynomials.
 * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
 *
 * \par
 * \image html LinearInterp.gif "Linear interpolation"
 *
 * \par
 * A  Linear Interpolate function calculates an output value(y), for the input(x)
 * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
 *
 * \par Algorithm:
 * 
 *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
 *       where x0, x1 are nearest values of input x
 *             y0, y1 are nearest values to output y
 * 

 *
 * \par
 * This set of functions implements Linear interpolation process
 * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
 * sample of data and each call to the function returns a single processed value.
 * S points to an instance of the Linear Interpolate function data structure.
 * x is the input sample value. The functions returns the output value.
 *
 * \par
 * if x is outside of the table boundary, Linear interpolation returns first value of the table
 * if x is below input range and returns last value of table if x is above range.
 */

/**
 * @addtogroup LinearInterpolate
 * @{
 */

/**
 * @brief  Process function for the floating-point Linear Interpolation Function.
 * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
 * @param[in]     x  input sample to process
 * @return y processed output sample.
 *
 */
static __INLINE float32_t arm_linear_interp_f32(arm_linear_interp_instance_f32 *S, float32_t x) {
  float32_t  y;
  float32_t  x0, x1;                 /* Nearest input values */
  float32_t  y0, y1;                 /* Nearest output values */
  float32_t  xSpacing = S->xSpacing; /* spacing between input values */
  int32_t    i;                      /* Index variable */
  float32_t *pYData = S->pYData;     /* pointer to output table */

  /* Calculation of index */
  i = (int32_t)((x - S->x1) / xSpacing);

  if (i < 0) {
    /* Iniatilize output for below specified range as least output value of table */
    y = pYData[0];
  } else if ((uint32_t)i >= S->nValues) {
    /* Iniatilize output for above specified range as last output value of table */
    y = pYData[S->nValues - 1];
  } else {
    /* Calculation of nearest input values */
    x0 = S->x1 + i * xSpacing;
    x1 = S->x1 + (i + 1) * xSpacing;

    /* Read of nearest output values */
    y0 = pYData[i];
    y1 = pYData[i + 1];

    /* Calculation of output */
    y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
  }

  /* returns output value */
  return (y);
}

/**
 *
 * @brief  Process function for the Q31 Linear Interpolation Function.
 * @param[in] pYData   pointer to Q31 Linear Interpolation table
 * @param[in] x        input sample to process
 * @param[in] nValues  number of table values
 * @return y processed output sample.
 *
 * \par
 * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
 * This function can support maximum of table size 2^12.
 *
 */
static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, q31_t x, uint32_t nValues) {
  q31_t   y;      /* output */
  q31_t   y0, y1; /* Nearest output values */
  q31_t   fract;  /* fractional part */
  int32_t index;  /* Index to read nearest output values */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  index = ((x & (q31_t)0xFFF00000) >> 20);

  if (index >= (int32_t)(nValues - 1)) {
    return (pYData[nValues - 1]);
  } else if (index < 0) {
    return (pYData[0]);
  } else {
    /* 20 bits for the fractional part */
    /* shift left by 11 to keep fract in 1.31 format */
    fract = (x & 0x000FFFFF) << 11;

    /* Read two nearest output values from the index in 1.31(q31) format */
    y0 = pYData[index];
    y1 = pYData[index + 1];

    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
    y = ((q31_t)((q63_t)y0 * (0x7FFFFFFF - fract) >> 32));

    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
    y += ((q31_t)(((q63_t)y1 * fract) >> 32));

    /* Convert y to 1.31 format */
    return (y << 1u);
  }
}

/**
 *
 * @brief  Process function for the Q15 Linear Interpolation Function.
 * @param[in] pYData   pointer to Q15 Linear Interpolation table
 * @param[in] x        input sample to process
 * @param[in] nValues  number of table values
 * @return y processed output sample.
 *
 * \par
 * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
 * This function can support maximum of table size 2^12.
 *
 */
static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) {
  q63_t   y;      /* output */
  q15_t   y0, y1; /* Nearest output values */
  q31_t   fract;  /* fractional part */
  int32_t index;  /* Index to read nearest output values */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  index = ((x & (int32_t)0xFFF00000) >> 20);

  if (index >= (int32_t)(nValues - 1)) {
    return (pYData[nValues - 1]);
  } else if (index < 0) {
    return (pYData[0]);
  } else {
    /* 20 bits for the fractional part */
    /* fract is in 12.20 format */
    fract = (x & 0x000FFFFF);

    /* Read two nearest output values from the index */
    y0 = pYData[index];
    y1 = pYData[index + 1];

    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
    y = ((q63_t)y0 * (0xFFFFF - fract));

    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
    y += ((q63_t)y1 * (fract));

    /* convert y to 1.15 format */
    return (q15_t)(y >> 20);
  }
}

/**
 *
 * @brief  Process function for the Q7 Linear Interpolation Function.
 * @param[in] pYData   pointer to Q7 Linear Interpolation table
 * @param[in] x        input sample to process
 * @param[in] nValues  number of table values
 * @return y processed output sample.
 *
 * \par
 * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
 * This function can support maximum of table size 2^12.
 */
static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) {
  q31_t    y;      /* output */
  q7_t     y0, y1; /* Nearest output values */
  q31_t    fract;  /* fractional part */
  uint32_t index;  /* Index to read nearest output values */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  if (x < 0) {
    return (pYData[0]);
  }
  index = (x >> 20) & 0xfff;

  if (index >= (nValues - 1)) {
    return (pYData[nValues - 1]);
  } else {
    /* 20 bits for the fractional part */
    /* fract is in 12.20 format */
    fract = (x & 0x000FFFFF);

    /* Read two nearest output values from the index and are in 1.7(q7) format */
    y0 = pYData[index];
    y1 = pYData[index + 1];

    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
    y = ((y0 * (0xFFFFF - fract)));

    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
    y += (y1 * fract);

    /* convert y to 1.7(q7) format */
    return (q7_t)(y >> 20);
  }
}

/**
 * @} end of LinearInterpolate group
 */

/**
 * @brief  Fast approximation to the trigonometric sine function for floating-point data.
 * @param[in] x  input value in radians.
 * @return  sin(x).
 */
float32_t arm_sin_f32(float32_t x);

/**
 * @brief  Fast approximation to the trigonometric sine function for Q31 data.
 * @param[in] x  Scaled input value in radians.
 * @return  sin(x).
 */
q31_t arm_sin_q31(q31_t x);

/**
 * @brief  Fast approximation to the trigonometric sine function for Q15 data.
 * @param[in] x  Scaled input value in radians.
 * @return  sin(x).
 */
q15_t arm_sin_q15(q15_t x);

/**
 * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
 * @param[in] x  input value in radians.
 * @return  cos(x).
 */
float32_t arm_cos_f32(float32_t x);

/**
 * @brief Fast approximation to the trigonometric cosine function for Q31 data.
 * @param[in] x  Scaled input value in radians.
 * @return  cos(x).
 */
q31_t arm_cos_q31(q31_t x);

/**
 * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
 * @param[in] x  Scaled input value in radians.
 * @return  cos(x).
 */
q15_t arm_cos_q15(q15_t x);

/**
 * @ingroup groupFastMath
 */

/**
 * @defgroup SQRT Square Root
 *
 * Computes the square root of a number.
 * There are separate functions for Q15, Q31, and floating-point data types.
 * The square root function is computed using the Newton-Raphson algorithm.
 * This is an iterative algorithm of the form:
 * 
 *      x1 = x0 - f(x0)/f'(x0)
 * 

 * where x1 is the current estimate,
 * x0 is the previous estimate, and
 * f'(x0) is the derivative of f() evaluated at x0.
 * For the square root function, the algorithm reduces to:
 * 
 *     x0 = in/2                         [initial guess]
 *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
 * 

 */

/**
 * @addtogroup SQRT
 * @{
 */

/**
 * @brief  Floating-point square root function.
 * @param[in]  in    input value.
 * @param[out] pOut  square root of input value.
 * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
 * in is negative value and returns zero output for negative values.
 */
static __INLINE arm_status arm_sqrt_f32(float32_t in, float32_t *pOut) {
  if (in >= 0.0f) {

#if (__FPU_USED == 1) && defined(__CC_ARM)
    *pOut = __sqrtf(in);
#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
    *pOut = __builtin_sqrtf(in);
#elif (__FPU_USED == 1) && defined(__GNUC__)
    *pOut = __builtin_sqrtf(in);
#elif (__FPU_USED == 1) && defined(__ICCARM__) && (__VER__ >= 6040000)
    __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
#else
    *pOut = sqrtf(in);
#endif

    return (ARM_MATH_SUCCESS);
  } else {
    *pOut = 0.0f;
    return (ARM_MATH_ARGUMENT_ERROR);
  }
}

/**
 * @brief Q31 square root function.
 * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
 * @param[out] pOut  square root of input value.
 * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
 * in is negative value and returns zero output for negative values.
 */
arm_status arm_sqrt_q31(q31_t in, q31_t *pOut);

/**
 * @brief  Q15 square root function.
 * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
 * @param[out] pOut  square root of input value.
 * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
 * in is negative value and returns zero output for negative values.
 */
arm_status arm_sqrt_q15(q15_t in, q15_t *pOut);

/**
 * @} end of SQRT group
 */

/**
 * @brief floating-point Circular write function.
 */
static __INLINE void arm_circularWrite_f32(int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize) {
  uint32_t i = 0u;
  int32_t  wOffset;

  /* Copy the value of Index pointer that points
   * to the current location where the input samples to be copied */
  wOffset = *writeOffset;

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the input sample to the circular buffer */
    circBuffer[wOffset] = *src;

    /* Update the input pointer */
    src += srcInc;

    /* Circularly update wOffset.  Watch out for positive and negative value */
    wOffset += bufferInc;
    if (wOffset >= L)
      wOffset -= L;

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *writeOffset = (uint16_t)wOffset;
}

/**
 * @brief floating-point Circular Read function.
 */
static __INLINE void arm_circularRead_f32(int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc,
                                          uint32_t blockSize) {
  uint32_t i = 0u;
  int32_t  rOffset, dst_end;

  /* Copy the value of Index pointer that points
   * to the current location from where the input samples to be read */
  rOffset = *readOffset;
  dst_end = (int32_t)(dst_base + dst_length);

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the sample from the circular buffer to the destination buffer */
    *dst = circBuffer[rOffset];

    /* Update the input pointer */
    dst += dstInc;

    if (dst == (int32_t *)dst_end) {
      dst = dst_base;
    }

    /* Circularly update rOffset.  Watch out for positive and negative value  */
    rOffset += bufferInc;

    if (rOffset >= L) {
      rOffset -= L;
    }

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *readOffset = rOffset;
}

/**
 * @brief Q15 Circular write function.
 */
static __INLINE void arm_circularWrite_q15(q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize) {
  uint32_t i = 0u;
  int32_t  wOffset;

  /* Copy the value of Index pointer that points
   * to the current location where the input samples to be copied */
  wOffset = *writeOffset;

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the input sample to the circular buffer */
    circBuffer[wOffset] = *src;

    /* Update the input pointer */
    src += srcInc;

    /* Circularly update wOffset.  Watch out for positive and negative value */
    wOffset += bufferInc;
    if (wOffset >= L)
      wOffset -= L;

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *writeOffset = (uint16_t)wOffset;
}

/**
 * @brief Q15 Circular Read function.
 */
static __INLINE void arm_circularRead_q15(q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) {
  uint32_t i = 0;
  int32_t  rOffset, dst_end;

  /* Copy the value of Index pointer that points
   * to the current location from where the input samples to be read */
  rOffset = *readOffset;

  dst_end = (int32_t)(dst_base + dst_length);

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the sample from the circular buffer to the destination buffer */
    *dst = circBuffer[rOffset];

    /* Update the input pointer */
    dst += dstInc;

    if (dst == (q15_t *)dst_end) {
      dst = dst_base;
    }

    /* Circularly update wOffset.  Watch out for positive and negative value */
    rOffset += bufferInc;

    if (rOffset >= L) {
      rOffset -= L;
    }

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *readOffset = rOffset;
}

/**
 * @brief Q7 Circular write function.
 */
static __INLINE void arm_circularWrite_q7(q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize) {
  uint32_t i = 0u;
  int32_t  wOffset;

  /* Copy the value of Index pointer that points
   * to the current location where the input samples to be copied */
  wOffset = *writeOffset;

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the input sample to the circular buffer */
    circBuffer[wOffset] = *src;

    /* Update the input pointer */
    src += srcInc;

    /* Circularly update wOffset.  Watch out for positive and negative value */
    wOffset += bufferInc;
    if (wOffset >= L)
      wOffset -= L;

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *writeOffset = (uint16_t)wOffset;
}

/**
 * @brief Q7 Circular Read function.
 */
static __INLINE void arm_circularRead_q7(q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) {
  uint32_t i = 0;
  int32_t  rOffset, dst_end;

  /* Copy the value of Index pointer that points
   * to the current location from where the input samples to be read */
  rOffset = *readOffset;

  dst_end = (int32_t)(dst_base + dst_length);

  /* Loop over the blockSize */
  i = blockSize;

  while (i > 0u) {
    /* copy the sample from the circular buffer to the destination buffer */
    *dst = circBuffer[rOffset];

    /* Update the input pointer */
    dst += dstInc;

    if (dst == (q7_t *)dst_end) {
      dst = dst_base;
    }

    /* Circularly update rOffset.  Watch out for positive and negative value */
    rOffset += bufferInc;

    if (rOffset >= L) {
      rOffset -= L;
    }

    /* Decrement the loop counter */
    i--;
  }

  /* Update the index pointer */
  *readOffset = rOffset;
}

/**
 * @brief  Sum of the squares of the elements of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_power_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult);

/**
 * @brief  Sum of the squares of the elements of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_power_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult);

/**
 * @brief  Sum of the squares of the elements of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_power_q15(q15_t *pSrc, uint32_t blockSize, q63_t *pResult);

/**
 * @brief  Sum of the squares of the elements of a Q7 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_power_q7(q7_t *pSrc, uint32_t blockSize, q31_t *pResult);

/**
 * @brief  Mean value of a Q7 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_mean_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult);

/**
 * @brief  Mean value of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_mean_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult);

/**
 * @brief  Mean value of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_mean_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult);

/**
 * @brief  Mean value of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_mean_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult);

/**
 * @brief  Variance of the elements of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_var_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult);

/**
 * @brief  Variance of the elements of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_var_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult);

/**
 * @brief  Variance of the elements of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_var_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult);

/**
 * @brief  Root Mean Square of the elements of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_rms_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult);

/**
 * @brief  Root Mean Square of the elements of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_rms_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult);

/**
 * @brief  Root Mean Square of the elements of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_rms_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult);

/**
 * @brief  Standard deviation of the elements of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_std_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult);

/**
 * @brief  Standard deviation of the elements of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_std_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult);

/**
 * @brief  Standard deviation of the elements of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output value.
 */
void arm_std_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult);

/**
 * @brief  Floating-point complex magnitude
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples);

/**
 * @brief  Q31 complex magnitude
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples);

/**
 * @brief  Q15 complex magnitude
 * @param[in]  pSrc        points to the complex input vector
 * @param[out] pDst        points to the real output vector
 * @param[in]  numSamples  number of complex samples in the input vector
 */
void arm_cmplx_mag_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples);

/**
 * @brief  Q15 complex dot product
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[in]  numSamples  number of complex samples in each vector
 * @param[out] realResult  real part of the result returned here
 * @param[out] imagResult  imaginary part of the result returned here
 */
void arm_cmplx_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult);

/**
 * @brief  Q31 complex dot product
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[in]  numSamples  number of complex samples in each vector
 * @param[out] realResult  real part of the result returned here
 * @param[out] imagResult  imaginary part of the result returned here
 */
void arm_cmplx_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult);

/**
 * @brief  Floating-point complex dot product
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[in]  numSamples  number of complex samples in each vector
 * @param[out] realResult  real part of the result returned here
 * @param[out] imagResult  imaginary part of the result returned here
 */
void arm_cmplx_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult);

/**
 * @brief  Q15 complex-by-real multiplication
 * @param[in]  pSrcCmplx   points to the complex input vector
 * @param[in]  pSrcReal    points to the real input vector
 * @param[out] pCmplxDst   points to the complex output vector
 * @param[in]  numSamples  number of samples in each vector
 */
void arm_cmplx_mult_real_q15(q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples);

/**
 * @brief  Q31 complex-by-real multiplication
 * @param[in]  pSrcCmplx   points to the complex input vector
 * @param[in]  pSrcReal    points to the real input vector
 * @param[out] pCmplxDst   points to the complex output vector
 * @param[in]  numSamples  number of samples in each vector
 */
void arm_cmplx_mult_real_q31(q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples);

/**
 * @brief  Floating-point complex-by-real multiplication
 * @param[in]  pSrcCmplx   points to the complex input vector
 * @param[in]  pSrcReal    points to the real input vector
 * @param[out] pCmplxDst   points to the complex output vector
 * @param[in]  numSamples  number of samples in each vector
 */
void arm_cmplx_mult_real_f32(float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples);

/**
 * @brief  Minimum value of a Q7 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] result     is output pointer
 * @param[in]  index      is the array index of the minimum value in the input buffer.
 */
void arm_min_q7(q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index);

/**
 * @brief  Minimum value of a Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output pointer
 * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
 */
void arm_min_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex);

/**
 * @brief  Minimum value of a Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output pointer
 * @param[out] pIndex     is the array index of the minimum value in the input buffer.
 */
void arm_min_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex);

/**
 * @brief  Minimum value of a floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[in]  blockSize  is the number of samples to process
 * @param[out] pResult    is output pointer
 * @param[out] pIndex     is the array index of the minimum value in the input buffer.
 */
void arm_min_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex);

/**
 * @brief Maximum value of a Q7 vector.
 * @param[in]  pSrc       points to the input buffer
 * @param[in]  blockSize  length of the input vector
 * @param[out] pResult    maximum value returned here
 * @param[out] pIndex     index of maximum value returned here
 */
void arm_max_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex);

/**
 * @brief Maximum value of a Q15 vector.
 * @param[in]  pSrc       points to the input buffer
 * @param[in]  blockSize  length of the input vector
 * @param[out] pResult    maximum value returned here
 * @param[out] pIndex     index of maximum value returned here
 */
void arm_max_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex);

/**
 * @brief Maximum value of a Q31 vector.
 * @param[in]  pSrc       points to the input buffer
 * @param[in]  blockSize  length of the input vector
 * @param[out] pResult    maximum value returned here
 * @param[out] pIndex     index of maximum value returned here
 */
void arm_max_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex);

/**
 * @brief Maximum value of a floating-point vector.
 * @param[in]  pSrc       points to the input buffer
 * @param[in]  blockSize  length of the input vector
 * @param[out] pResult    maximum value returned here
 * @param[out] pIndex     index of maximum value returned here
 */
void arm_max_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex);

/**
 * @brief  Q15 complex-by-complex multiplication
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_mult_cmplx_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples);

/**
 * @brief  Q31 complex-by-complex multiplication
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_mult_cmplx_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples);

/**
 * @brief  Floating-point complex-by-complex multiplication
 * @param[in]  pSrcA       points to the first input vector
 * @param[in]  pSrcB       points to the second input vector
 * @param[out] pDst        points to the output vector
 * @param[in]  numSamples  number of complex samples in each vector
 */
void arm_cmplx_mult_cmplx_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples);

/**
 * @brief Converts the elements of the floating-point vector to Q31 vector.
 * @param[in]  pSrc       points to the floating-point input vector
 * @param[out] pDst       points to the Q31 output vector
 * @param[in]  blockSize  length of the input vector
 */
void arm_float_to_q31(float32_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief Converts the elements of the floating-point vector to Q15 vector.
 * @param[in]  pSrc       points to the floating-point input vector
 * @param[out] pDst       points to the Q15 output vector
 * @param[in]  blockSize  length of the input vector
 */
void arm_float_to_q15(float32_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief Converts the elements of the floating-point vector to Q7 vector.
 * @param[in]  pSrc       points to the floating-point input vector
 * @param[out] pDst       points to the Q7 output vector
 * @param[in]  blockSize  length of the input vector
 */
void arm_float_to_q7(float32_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Converts the elements of the Q31 vector to Q15 vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q31_to_q15(q31_t *pSrc, q15_t *pDst, uint32_t blockSize);

/**
 * @brief  Converts the elements of the Q31 vector to Q7 vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q31_to_q7(q31_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @brief  Converts the elements of the Q15 vector to floating-point vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q15_to_float(q15_t *pSrc, float32_t *pDst, uint32_t blockSize);

/**
 * @brief  Converts the elements of the Q15 vector to Q31 vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q15_to_q31(q15_t *pSrc, q31_t *pDst, uint32_t blockSize);

/**
 * @brief  Converts the elements of the Q15 vector to Q7 vector.
 * @param[in]  pSrc       is input pointer
 * @param[out] pDst       is output pointer
 * @param[in]  blockSize  is the number of samples to process
 */
void arm_q15_to_q7(q15_t *pSrc, q7_t *pDst, uint32_t blockSize);

/**
 * @ingroup groupInterpolation
 */

/**
 * @defgroup BilinearInterpolate Bilinear Interpolation
 *
 * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
 * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
 * determines values between the grid points.
 * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
 * Bilinear interpolation is often used in image processing to rescale images.
 * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
 *
 * Algorithm
 * \par
 * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
 * For floating-point, the instance structure is defined as:
 * 
 *   typedef struct
 *   {
 *     uint16_t numRows;
 *     uint16_t numCols;
 *     float32_t *pData;
 * } arm_bilinear_interp_instance_f32;
 * 

 *
 * \par
 * where numRows specifies the number of rows in the table;
 * numCols specifies the number of columns in the table;
 * and pData points to an array of size numRows*numCols values.
 * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
 * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
 *
 * \par
 * Let (x, y) specify the desired interpolation point.  Then define:
 * 
 *     XF = floor(x)
 *     YF = floor(y)
 * 

 * \par
 * The interpolated output point is computed as:
 * 
 *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
 *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
 *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
 *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
 * 

 * Note that the coordinates (x, y) contain integer and fractional components.
 * The integer components specify which portion of the table to use while the
 * fractional components control the interpolation processor.
 *
 * \par
 * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
 */

/**
 * @addtogroup BilinearInterpolate
 * @{
 */

/**
 *
 * @brief  Floating-point bilinear interpolation.
 * @param[in,out] S  points to an instance of the interpolation structure.
 * @param[in]     X  interpolation coordinate.
 * @param[in]     Y  interpolation coordinate.
 * @return out interpolated value.
 */
static __INLINE float32_t arm_bilinear_interp_f32(const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y) {
  float32_t  out;
  float32_t  f00, f01, f10, f11;
  float32_t *pData = S->pData;
  int32_t    xIndex, yIndex, index;
  float32_t  xdiff, ydiff;
  float32_t  b1, b2, b3, b4;

  xIndex = (int32_t)X;
  yIndex = (int32_t)Y;

  /* Care taken for table outside boundary */
  /* Returns zero output when values are outside table boundary */
  if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
    return (0);
  }

  /* Calculation of index for two nearest points in X-direction */
  index = (xIndex - 1) + (yIndex - 1) * S->numCols;

  /* Read two nearest points in X-direction */
  f00 = pData[index];
  f01 = pData[index + 1];

  /* Calculation of index for two nearest points in Y-direction */
  index = (xIndex - 1) + (yIndex)*S->numCols;

  /* Read two nearest points in Y-direction */
  f10 = pData[index];
  f11 = pData[index + 1];

  /* Calculation of intermediate values */
  b1 = f00;
  b2 = f01 - f00;
  b3 = f10 - f00;
  b4 = f00 - f01 - f10 + f11;

  /* Calculation of fractional part in X */
  xdiff = X - xIndex;

  /* Calculation of fractional part in Y */
  ydiff = Y - yIndex;

  /* Calculation of bi-linear interpolated output */
  out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;

  /* return to application */
  return (out);
}

/**
 *
 * @brief  Q31 bilinear interpolation.
 * @param[in,out] S  points to an instance of the interpolation structure.
 * @param[in]     X  interpolation coordinate in 12.20 format.
 * @param[in]     Y  interpolation coordinate in 12.20 format.
 * @return out interpolated value.
 */
static __INLINE q31_t arm_bilinear_interp_q31(arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y) {
  q31_t    out;                 /* Temporary output */
  q31_t    acc = 0;             /* output */
  q31_t    xfract, yfract;      /* X, Y fractional parts */
  q31_t    x1, x2, y1, y2;      /* Nearest output values */
  int32_t  rI, cI;              /* Row and column indices */
  q31_t *  pYData = S->pData;   /* pointer to output table values */
  uint32_t nCols  = S->numCols; /* num of rows */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  rI = ((X & (q31_t)0xFFF00000) >> 20);

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  cI = ((Y & (q31_t)0xFFF00000) >> 20);

  /* Care taken for table outside boundary */
  /* Returns zero output when values are outside table boundary */
  if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
    return (0);
  }

  /* 20 bits for the fractional part */
  /* shift left xfract by 11 to keep 1.31 format */
  xfract = (X & 0x000FFFFF) << 11u;

  /* Read two nearest output values from the index */
  x1 = pYData[(rI) + (int32_t)nCols * (cI)];
  x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];

  /* 20 bits for the fractional part */
  /* shift left yfract by 11 to keep 1.31 format */
  yfract = (Y & 0x000FFFFF) << 11u;

  /* Read two nearest output values from the index */
  y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)];
  y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];

  /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
  out = ((q31_t)(((q63_t)x1 * (0x7FFFFFFF - xfract)) >> 32));
  acc = ((q31_t)(((q63_t)out * (0x7FFFFFFF - yfract)) >> 32));

  /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
  out = ((q31_t)((q63_t)x2 * (0x7FFFFFFF - yfract) >> 32));
  acc += ((q31_t)((q63_t)out * (xfract) >> 32));

  /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
  out = ((q31_t)((q63_t)y1 * (0x7FFFFFFF - xfract) >> 32));
  acc += ((q31_t)((q63_t)out * (yfract) >> 32));

  /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
  out = ((q31_t)((q63_t)y2 * (xfract) >> 32));
  acc += ((q31_t)((q63_t)out * (yfract) >> 32));

  /* Convert acc to 1.31(q31) format */
  return ((q31_t)(acc << 2));
}

/**
 * @brief  Q15 bilinear interpolation.
 * @param[in,out] S  points to an instance of the interpolation structure.
 * @param[in]     X  interpolation coordinate in 12.20 format.
 * @param[in]     Y  interpolation coordinate in 12.20 format.
 * @return out interpolated value.
 */
static __INLINE q15_t arm_bilinear_interp_q15(arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y) {
  q63_t    acc = 0;             /* output */
  q31_t    out;                 /* Temporary output */
  q15_t    x1, x2, y1, y2;      /* Nearest output values */
  q31_t    xfract, yfract;      /* X, Y fractional parts */
  int32_t  rI, cI;              /* Row and column indices */
  q15_t *  pYData = S->pData;   /* pointer to output table values */
  uint32_t nCols  = S->numCols; /* num of rows */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  rI = ((X & (q31_t)0xFFF00000) >> 20);

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  cI = ((Y & (q31_t)0xFFF00000) >> 20);

  /* Care taken for table outside boundary */
  /* Returns zero output when values are outside table boundary */
  if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
    return (0);
  }

  /* 20 bits for the fractional part */
  /* xfract should be in 12.20 format */
  xfract = (X & 0x000FFFFF);

  /* Read two nearest output values from the index */
  x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)];
  x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];

  /* 20 bits for the fractional part */
  /* yfract should be in 12.20 format */
  yfract = (Y & 0x000FFFFF);

  /* Read two nearest output values from the index */
  y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)];
  y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];

  /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */

  /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
  /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
  out = (q31_t)(((q63_t)x1 * (0xFFFFF - xfract)) >> 4u);
  acc = ((q63_t)out * (0xFFFFF - yfract));

  /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
  out = (q31_t)(((q63_t)x2 * (0xFFFFF - yfract)) >> 4u);
  acc += ((q63_t)out * (xfract));

  /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
  out = (q31_t)(((q63_t)y1 * (0xFFFFF - xfract)) >> 4u);
  acc += ((q63_t)out * (yfract));

  /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
  out = (q31_t)(((q63_t)y2 * (xfract)) >> 4u);
  acc += ((q63_t)out * (yfract));

  /* acc is in 13.51 format and down shift acc by 36 times */
  /* Convert out to 1.15 format */
  return ((q15_t)(acc >> 36));
}

/**
 * @brief  Q7 bilinear interpolation.
 * @param[in,out] S  points to an instance of the interpolation structure.
 * @param[in]     X  interpolation coordinate in 12.20 format.
 * @param[in]     Y  interpolation coordinate in 12.20 format.
 * @return out interpolated value.
 */
static __INLINE q7_t arm_bilinear_interp_q7(arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y) {
  q63_t    acc = 0;             /* output */
  q31_t    out;                 /* Temporary output */
  q31_t    xfract, yfract;      /* X, Y fractional parts */
  q7_t     x1, x2, y1, y2;      /* Nearest output values */
  int32_t  rI, cI;              /* Row and column indices */
  q7_t *   pYData = S->pData;   /* pointer to output table values */
  uint32_t nCols  = S->numCols; /* num of rows */

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  rI = ((X & (q31_t)0xFFF00000) >> 20);

  /* Input is in 12.20 format */
  /* 12 bits for the table index */
  /* Index value calculation */
  cI = ((Y & (q31_t)0xFFF00000) >> 20);

  /* Care taken for table outside boundary */
  /* Returns zero output when values are outside table boundary */
  if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
    return (0);
  }

  /* 20 bits for the fractional part */
  /* xfract should be in 12.20 format */
  xfract = (X & (q31_t)0x000FFFFF);

  /* Read two nearest output values from the index */
  x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)];
  x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];

  /* 20 bits for the fractional part */
  /* yfract should be in 12.20 format */
  yfract = (Y & (q31_t)0x000FFFFF);

  /* Read two nearest output values from the index */
  y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)];
  y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];

  /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
  out = ((x1 * (0xFFFFF - xfract)));
  acc = (((q63_t)out * (0xFFFFF - yfract)));

  /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
  out = ((x2 * (0xFFFFF - yfract)));
  acc += (((q63_t)out * (xfract)));

  /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
  out = ((y1 * (0xFFFFF - xfract)));
  acc += (((q63_t)out * (yfract)));

  /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
  out = ((y2 * (yfract)));
  acc += (((q63_t)out * (xfract)));

  /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
  return ((q7_t)(acc >> 40));
}

/**
 * @} end of BilinearInterpolate group
 */

/* SMMLAR */
#define multAcc_32x32_keep32_R(a, x, y) a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32)

/* SMMLSR */
#define multSub_32x32_keep32_R(a, x, y) a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32)

/* SMMULR */
#define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32)

/* SMMLA */
#define multAcc_32x32_keep32(a, x, y) a += (q31_t)(((q63_t)x * y) >> 32)

/* SMMLS */
#define multSub_32x32_keep32(a, x, y) a -= (q31_t)(((q63_t)x * y) >> 32)

/* SMMUL */
#define mult_32x32_keep32(a, x, y) a = (q31_t)(((q63_t)x * y) >> 32)

#if defined(__CC_ARM)
/* Enter low optimization region - place directly above function definition */
#if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7)
#define LOW_OPTIMIZATION_ENTER _Pragma("push") _Pragma("O1")
#else
#define LOW_OPTIMIZATION_ENTER
#endif

/* Exit low optimization region - place directly after end of function definition */
#if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7)
#define LOW_OPTIMIZATION_EXIT _Pragma("pop")
#else
#define LOW_OPTIMIZATION_EXIT
#endif

/* Enter low optimization region - place directly above function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER

/* Exit low optimization region - place directly after end of function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#elif defined(__GNUC__)
#define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1")))
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#elif defined(__ICCARM__)
/* Enter low optimization region - place directly above function definition */
#if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7)
#define LOW_OPTIMIZATION_ENTER _Pragma("optimize=low")
#else
#define LOW_OPTIMIZATION_ENTER
#endif

/* Exit low optimization region - place directly after end of function definition */
#define LOW_OPTIMIZATION_EXIT

/* Enter low optimization region - place directly above function definition */
#if defined(ARM_MATH_CM4) || defined(ARM_MATH_CM7)
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER _Pragma("optimize=low")
#else
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#endif

/* Exit low optimization region - place directly after end of function definition */
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#elif defined(__CSMC__)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#elif defined(__TASKING__)
#define LOW_OPTIMIZATION_ENTER
#define LOW_OPTIMIZATION_EXIT
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT

#endif

#ifdef __cplusplus
}
#endif

#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif

#endif /* _ARM_MATH_H */

/**
 *
 * End of file.
 */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/cmsis_armcc.h
================================================
/**************************************************************************/ /**
                                                                              * @file     cmsis_armcc.h
                                                                              * @brief    CMSIS Cortex-M Core Function/Instruction Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H

#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif

/* ###########################  Core Function Access  ########################### */
/** \ingroup  CMSIS_Core_FunctionInterface
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  @{
 */

/* intrinsic void __enable_irq();     */
/* intrinsic void __disable_irq();    */

/**
  \brief   Get Control Register
  \details Returns the content of the Control Register.
  \return               Control Register value
 */
__STATIC_INLINE uint32_t __get_CONTROL(void) {
  register uint32_t __regControl __ASM("control");
  return (__regControl);
}

/**
  \brief   Set Control Register
  \details Writes the given value to the Control Register.
  \param [in]    control  Control Register value to set
 */
__STATIC_INLINE void __set_CONTROL(uint32_t control) {
  register uint32_t __regControl __ASM("control");
  __regControl = control;
}

/**
  \brief   Get IPSR Register
  \details Returns the content of the IPSR Register.
  \return               IPSR Register value
 */
__STATIC_INLINE uint32_t __get_IPSR(void) {
  register uint32_t __regIPSR __ASM("ipsr");
  return (__regIPSR);
}

/**
  \brief   Get APSR Register
  \details Returns the content of the APSR Register.
  \return               APSR Register value
 */
__STATIC_INLINE uint32_t __get_APSR(void) {
  register uint32_t __regAPSR __ASM("apsr");
  return (__regAPSR);
}

/**
  \brief   Get xPSR Register
  \details Returns the content of the xPSR Register.
  \return               xPSR Register value
 */
__STATIC_INLINE uint32_t __get_xPSR(void) {
  register uint32_t __regXPSR __ASM("xpsr");
  return (__regXPSR);
}

/**
  \brief   Get Process Stack Pointer
  \details Returns the current value of the Process Stack Pointer (PSP).
  \return               PSP Register value
 */
__STATIC_INLINE uint32_t __get_PSP(void) {
  register uint32_t __regProcessStackPointer __ASM("psp");
  return (__regProcessStackPointer);
}

/**
  \brief   Set Process Stack Pointer
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
  register uint32_t __regProcessStackPointer __ASM("psp");
  __regProcessStackPointer = topOfProcStack;
}

/**
  \brief   Get Main Stack Pointer
  \details Returns the current value of the Main Stack Pointer (MSP).
  \return               MSP Register value
 */
__STATIC_INLINE uint32_t __get_MSP(void) {
  register uint32_t __regMainStackPointer __ASM("msp");
  return (__regMainStackPointer);
}

/**
  \brief   Set Main Stack Pointer
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
  register uint32_t __regMainStackPointer __ASM("msp");
  __regMainStackPointer = topOfMainStack;
}

/**
  \brief   Get Priority Mask
  \details Returns the current state of the priority mask bit from the Priority Mask Register.
  \return               Priority Mask value
 */
__STATIC_INLINE uint32_t __get_PRIMASK(void) {
  register uint32_t __regPriMask __ASM("primask");
  return (__regPriMask);
}

/**
  \brief   Set Priority Mask
  \details Assigns the given value to the Priority Mask Register.
  \param [in]    priMask  Priority Mask
 */
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
  register uint32_t __regPriMask __ASM("primask");
  __regPriMask = (priMask);
}

#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

/**
  \brief   Enable FIQ
  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
#define __enable_fault_irq __enable_fiq

/**
  \brief   Disable FIQ
  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
#define __disable_fault_irq __disable_fiq

/**
  \brief   Get Base Priority
  \details Returns the current value of the Base Priority register.
  \return               Base Priority register value
 */
__STATIC_INLINE uint32_t __get_BASEPRI(void) {
  register uint32_t __regBasePri __ASM("basepri");
  return (__regBasePri);
}

/**
  \brief   Set Base Priority
  \details Assigns the given value to the Base Priority register.
  \param [in]    basePri  Base Priority value to set
 */
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
  register uint32_t __regBasePri __ASM("basepri");
  __regBasePri = (basePri & 0xFFU);
}

/**
  \brief   Set Base Priority with condition
  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
           or the new value increases the BASEPRI priority level.
  \param [in]    basePri  Base Priority value to set
 */
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
  register uint32_t __regBasePriMax __ASM("basepri_max");
  __regBasePriMax = (basePri & 0xFFU);
}

/**
  \brief   Get Fault Mask
  \details Returns the current value of the Fault Mask register.
  \return               Fault Mask register value
 */
__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
  register uint32_t __regFaultMask __ASM("faultmask");
  return (__regFaultMask);
}

/**
  \brief   Set Fault Mask
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
  register uint32_t __regFaultMask __ASM("faultmask");
  __regFaultMask = (faultMask & (uint32_t)1);
}

#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)

/**
  \brief   Get FPSCR
  \details Returns the current value of the Floating Point Status/Control register.
  \return               Floating Point Status/Control register value
 */
__STATIC_INLINE uint32_t __get_FPSCR(void) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  register uint32_t __regfpscr __ASM("fpscr");
  return (__regfpscr);
#else
  return (0U);
#endif
}

/**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  register uint32_t __regfpscr __ASM("fpscr");
  __regfpscr = (fpscr);
#endif
}

#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */

/*@} end of CMSIS_Core_RegAccFunctions */

/* ##########################  Core Instruction Access  ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  Access to dedicated instructions
  @{
*/

/**
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
#define __NOP __nop

/**
  \brief   Wait For Interrupt
  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
 */
#define __WFI __wfi

/**
  \brief   Wait For Event
  \details Wait For Event is a hint instruction that permits the processor to enter
           a low-power state until one of a number of events occurs.
 */
#define __WFE __wfe

/**
  \brief   Send Event
  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
#define __SEV __sev

/**
  \brief   Instruction Synchronization Barrier
  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
           so that all instructions following the ISB are fetched from cache or memory,
           after the instruction has been completed.
 */
#define __ISB()           \
  do {                    \
    __schedule_barrier(); \
    __isb(0xF);           \
    __schedule_barrier(); \
  } while (0U)

/**
  \brief   Data Synchronization Barrier
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
#define __DSB()           \
  do {                    \
    __schedule_barrier(); \
    __dsb(0xF);           \
    __schedule_barrier(); \
  } while (0U)

/**
  \brief   Data Memory Barrier
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
#define __DMB()           \
  do {                    \
    __schedule_barrier(); \
    __dmb(0xF);           \
    __schedule_barrier(); \
  } while (0U)

/**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in integer value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#define __REV __rev

/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in two unsigned short values.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr }
#endif

/**
  \brief   Reverse byte order in signed short value
  \details Reverses the byte order in a signed short value with sign extension to integer.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr }
#endif

/**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    value  Value to rotate
  \param [in]    value  Number of Bits to rotate
  \return               Rotated value
 */
#define __ROR __ror

/**
  \brief   Breakpoint
  \details Causes the processor to enter Debug state.
           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
#define __BKPT(value) __breakpoint(value)

/**
  \brief   Reverse bit order of value
  \details Reverses the bit order of the given value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
  uint32_t result;
  int32_t  s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

  result = value; /* r will be reversed bits of v; first get LSB of v */
  for (value >>= 1U; value; value >>= 1U) {
    result <<= 1U;
    result |= value & 1U;
    s--;
  }
  result <<= s; /* shift when v's highest bits are zero */
  return (result);
}
#endif

/**
  \brief   Count leading zeros
  \details Counts the number of leading zeros of a data value.
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
#define __CLZ __clz

#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

/**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint8_t)__ldrex(ptr)) _Pragma("pop")
#endif

/**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint16_t)__ldrex(ptr)) _Pragma("pop")
#endif

/**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731")((uint32_t)__ldrex(ptr)) _Pragma("pop")
#endif

/**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif

/**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif

/**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif

/**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
#define __CLREX __clrex

/**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
#define __SSAT __ssat

/**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
#define __USAT __usat

/**
  \brief   Rotate Right with Extend (32 bit)
  \details Moves each bit of a bitstring right by one bit.
           The carry input is shifted in at the left end of the bitstring.
  \param [in]    value  Value to rotate
  \return               Rotated value
 */
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr }
#endif

/**
  \brief   LDRT Unprivileged (8 bit)
  \details Executes a Unprivileged LDRT instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))

/**
  \brief   LDRT Unprivileged (16 bit)
  \details Executes a Unprivileged LDRT instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))

/**
  \brief   LDRT Unprivileged (32 bit)
  \details Executes a Unprivileged LDRT instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))

/**
  \brief   STRT Unprivileged (8 bit)
  \details Executes a Unprivileged STRT instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
#define __STRBT(value, ptr) __strt(value, ptr)

/**
  \brief   STRT Unprivileged (16 bit)
  \details Executes a Unprivileged STRT instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
#define __STRHT(value, ptr) __strt(value, ptr)

/**
  \brief   STRT Unprivileged (32 bit)
  \details Executes a Unprivileged STRT instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
#define __STRT(value, ptr) __strt(value, ptr)

#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

/* ###################  Compiler specific Intrinsics  ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  Access to dedicated SIMD instructions
  @{
*/

#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */

#define __SADD8   __sadd8
#define __QADD8   __qadd8
#define __SHADD8  __shadd8
#define __UADD8   __uadd8
#define __UQADD8  __uqadd8
#define __UHADD8  __uhadd8
#define __SSUB8   __ssub8
#define __QSUB8   __qsub8
#define __SHSUB8  __shsub8
#define __USUB8   __usub8
#define __UQSUB8  __uqsub8
#define __UHSUB8  __uhsub8
#define __SADD16  __sadd16
#define __QADD16  __qadd16
#define __SHADD16 __shadd16
#define __UADD16  __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16  __ssub16
#define __QSUB16  __qsub16
#define __SHSUB16 __shsub16
#define __USUB16  __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX    __sasx
#define __QASX    __qasx
#define __SHASX   __shasx
#define __UASX    __uasx
#define __UQASX   __uqasx
#define __UHASX   __uhasx
#define __SSAX    __ssax
#define __QSAX    __qsax
#define __SHSAX   __shsax
#define __USAX    __usax
#define __UQSAX   __uqsax
#define __UHSAX   __uhsax
#define __USAD8   __usad8
#define __USADA8  __usada8
#define __SSAT16  __ssat16
#define __USAT16  __usat16
#define __UXTB16  __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16  __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD   __smuad
#define __SMUADX  __smuadx
#define __SMLAD   __smlad
#define __SMLADX  __smladx
#define __SMLALD  __smlald
#define __SMLALDX __smlaldx
#define __SMUSD   __smusd
#define __SMUSDX  __smusdx
#define __SMLSD   __smlsd
#define __SMLSDX  __smlsdx
#define __SMLSLD  __smlsld
#define __SMLSLDX __smlsldx
#define __SEL     __sel
#define __QADD    __qadd
#define __QSUB    __qsub

#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))

#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))

#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U)) >> 32U))

#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */

#endif /* __CMSIS_ARMCC_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/cmsis_armcc_V6.h
================================================
/**************************************************************************/ /**
                                                                              * @file     cmsis_armcc_V6.h
                                                                              * @brief    CMSIS Cortex-M Core Function/Instruction Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#ifndef __CMSIS_ARMCC_V6_H
#define __CMSIS_ARMCC_V6_H

/* ###########################  Core Function Access  ########################### */
/** \ingroup  CMSIS_Core_FunctionInterface
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  @{
 */

/**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { __ASM volatile("cpsie i" : : : "memory"); }

/**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { __ASM volatile("cpsid i" : : : "memory"); }

/**
  \brief   Get Control Register
  \details Returns the content of the Control Register.
  \return               Control Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) {
  uint32_t result;

  __ASM volatile("MRS %0, control" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Control Register (non-secure)
  \details Returns the content of the non-secure Control Register when in secure mode.
  \return               non-secure Control Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, control_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Control Register
  \details Writes the given value to the Control Register.
  \param [in]    control  Control Register value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Control Register (non-secure)
  \details Writes the given value to the non-secure Control Register when in secure state.
  \param [in]    control  Control Register value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); }
#endif

/**
  \brief   Get IPSR Register
  \details Returns the content of the IPSR Register.
  \return               IPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, ipsr" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get IPSR Register (non-secure)
  \details Returns the content of the non-secure IPSR Register when in secure state.
  \return               IPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, ipsr_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Get APSR Register
  \details Returns the content of the APSR Register.
  \return               APSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, apsr" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get APSR Register (non-secure)
  \details Returns the content of the non-secure APSR Register when in secure state.
  \return               APSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, apsr_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Get xPSR Register
  \details Returns the content of the xPSR Register.
  \return               xPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, xpsr" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get xPSR Register (non-secure)
  \details Returns the content of the non-secure xPSR Register when in secure state.
  \return               xPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, xpsr_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Get Process Stack Pointer
  \details Returns the current value of the Process Stack Pointer (PSP).
  \return               PSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, psp" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Process Stack Pointer (non-secure)
  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
  \return               PSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, psp_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Process Stack Pointer
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) : "sp"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Process Stack Pointer (non-secure)
  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) : "sp"); }
#endif

/**
  \brief   Get Main Stack Pointer
  \details Returns the current value of the Main Stack Pointer (MSP).
  \return               MSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, msp" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Main Stack Pointer (non-secure)
  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
  \return               MSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, msp_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Main Stack Pointer
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) : "sp"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Main Stack Pointer (non-secure)
  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) : "sp"); }
#endif

/**
  \brief   Get Priority Mask
  \details Returns the current state of the priority mask bit from the Priority Mask Register.
  \return               Priority Mask value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) {
  uint32_t result;

  __ASM volatile("MRS %0, primask" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Priority Mask (non-secure)
  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
  \return               Priority Mask value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, primask_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Priority Mask
  \details Assigns the given value to the Priority Mask Register.
  \param [in]    priMask  Priority Mask
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Priority Mask (non-secure)
  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
  \param [in]    priMask  Priority Mask
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); }
#endif

#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */

/**
  \brief   Enable FIQ
  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile("cpsie f" : : : "memory"); }

/**
  \brief   Disable FIQ
  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile("cpsid f" : : : "memory"); }

/**
  \brief   Get Base Priority
  \details Returns the current value of the Base Priority register.
  \return               Base Priority register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) {
  uint32_t result;

  __ASM volatile("MRS %0, basepri" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Base Priority (non-secure)
  \details Returns the current value of the non-secure Base Priority register when in secure state.
  \return               Base Priority register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, basepri_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Base Priority
  \details Assigns the given value to the Base Priority register.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Base Priority (non-secure)
  \details Assigns the given value to the non-secure Base Priority register when in secure state.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) { __ASM volatile("MSR basepri_ns, %0" : : "r"(value) : "memory"); }
#endif

/**
  \brief   Set Base Priority with condition
  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
           or the new value increases the BASEPRI priority level.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) { __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Base Priority with condition (non_secure)
  \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
               or the new value increases the BASEPRI priority level.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) { __ASM volatile("MSR basepri_max_ns, %0" : : "r"(value) : "memory"); }
#endif

/**
  \brief   Get Fault Mask
  \details Returns the current value of the Fault Mask register.
  \return               Fault Mask register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) {
  uint32_t result;

  __ASM volatile("MRS %0, faultmask" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get Fault Mask (non-secure)
  \details Returns the current value of the non-secure Fault Mask register when in secure state.
  \return               Fault Mask register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) {
  uint32_t result;

  __ASM volatile("MRS %0, faultmask_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Fault Mask
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); }

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set Fault Mask (non-secure)
  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
  \param [in]    faultMask  Fault Mask value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); }
#endif

#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

#if (__ARM_ARCH_8M__ == 1U)

/**
  \brief   Get Process Stack Pointer Limit
  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
  \return               PSPLIM Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, psplim" : "=r"(result));
  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo:  ARMCC_V6: check predefined macro for mainline */
/**
  \brief   Get Process Stack Pointer Limit (non-secure)
  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  \return               PSPLIM Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, psplim_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Process Stack Pointer Limit
  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); }

#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo:  ARMCC_V6: check predefined macro for mainline */
/**
  \brief   Set Process Stack Pointer (non-secure)
  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); }
#endif

/**
  \brief   Get Main Stack Pointer Limit
  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
  \return               MSPLIM Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, msplim" : "=r"(result));

  return (result);
}

#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo:  ARMCC_V6: check predefined macro for mainline */
/**
  \brief   Get Main Stack Pointer Limit (non-secure)
  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
  \return               MSPLIM Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) {
  register uint32_t result;

  __ASM volatile("MRS %0, msplim_ns" : "=r"(result));
  return (result);
}
#endif

/**
  \brief   Set Main Stack Pointer Limit
  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); }

#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo:  ARMCC_V6: check predefined macro for mainline */
/**
  \brief   Set Main Stack Pointer Limit (non-secure)
  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); }
#endif

#endif /* (__ARM_ARCH_8M__ == 1U) */

#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */

/**
  \brief   Get FPSCR
  \details eturns the current value of the Floating Point Status/Control register.
  \return               Floating Point Status/Control register value
 */
#define __get_FPSCR __builtin_arm_get_fpscr
#if 0
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  uint32_t result;

  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  __ASM volatile ("");
  return(result);
#else
   return(0);
#endif
}
#endif

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Get FPSCR (non-secure)
  \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
  \return               Floating Point Status/Control register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  uint32_t result;

  __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */
  __ASM volatile("VMRS %0, fpscr_ns" : "=r"(result));
  __ASM volatile("");
  return (result);
#else
  return (0);
#endif
}
#endif

/**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
#define __set_FPSCR __builtin_arm_set_fpscr
#if 0
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  __ASM volatile ("");                                 /* Empty asm statement works as a scheduling barrier */
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
  __ASM volatile ("");
#endif
}
#endif

#if (__ARM_FEATURE_CMSE == 3U)
/**
  \brief   Set FPSCR (non-secure)
  \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */
  __ASM volatile("VMSR fpscr_ns, %0" : : "r"(fpscr) : "vfpcc");
  __ASM volatile("");
#endif
}
#endif

#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

/*@} end of CMSIS_Core_RegAccFunctions */

/* ##########################  Core Instruction Access  ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  Access to dedicated instructions
  @{
*/

/* Define macros for porting to both thumb1 and thumb2.
 * For thumb1, use low register (r0-r7), specified by constraint "l"
 * Otherwise, use general registers, specified by constraint "r" */
#if defined(__thumb__) && !defined(__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
#define __CMSIS_GCC_USE_REG(r) "l"(r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
#define __CMSIS_GCC_USE_REG(r) "r"(r)
#endif

/**
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
#define __NOP __builtin_arm_nop

/**
  \brief   Wait For Interrupt
  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
 */
#define __WFI __builtin_arm_wfi

/**
  \brief   Wait For Event
  \details Wait For Event is a hint instruction that permits the processor to enter
           a low-power state until one of a number of events occurs.
 */
#define __WFE __builtin_arm_wfe

/**
  \brief   Send Event
  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
#define __SEV __builtin_arm_sev

/**
  \brief   Instruction Synchronization Barrier
  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
           so that all instructions following the ISB are fetched from cache or memory,
           after the instruction has been completed.
 */
#define __ISB() __builtin_arm_isb(0xF);

/**
  \brief   Data Synchronization Barrier
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
#define __DSB() __builtin_arm_dsb(0xF);

/**
  \brief   Data Memory Barrier
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
#define __DMB() __builtin_arm_dmb(0xF);

/**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in integer value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#define __REV __builtin_bswap32

/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in two unsigned short values.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
#define __REV16 __builtin_bswap16 /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */
#if 0
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
  uint32_t result;

  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  return(result);
}
#endif

/**
  \brief   Reverse byte order in signed short value
  \details Reverses the byte order in a signed short value with sign extension to integer.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
/* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) {
  int32_t result;

  __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
}

/**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    op1  Value to rotate
  \param [in]    op2  Number of Bits to rotate
  \return               Rotated value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); }

/**
  \brief   Breakpoint
  \details Causes the processor to enter Debug state.
            Debug tools can use this to investigate system state when the instruction at a particular address is reached.
    \param [in]    value  is ignored by the processor.
                   If required, a debugger can use it to store additional information about the breakpoint.
 */
#define __BKPT(value) __ASM volatile("bkpt " #value)

/**
  \brief   Reverse bit order of value
  \details Reverses the bit order of the given value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
/* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
  uint32_t result;

#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */
  __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
#else
  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

  result = value; /* r will be reversed bits of v; first get LSB of v */
  for (value >>= 1U; value; value >>= 1U) {
    result <<= 1U;
    result |= value & 1U;
    s--;
  }
  result <<= s; /* shift when v's highest bits are zero */
#endif
  return (result);
}

/**
  \brief   Count leading zeros
  \details Counts the number of leading zeros of a data value.
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
#define __CLZ __builtin_clz

#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */

/**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
#define __LDREXB (uint8_t) __builtin_arm_ldrex

/**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
#define __LDREXH (uint16_t) __builtin_arm_ldrex

/**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
#define __LDREXW (uint32_t) __builtin_arm_ldrex

/**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STREXB (uint32_t) __builtin_arm_strex

/**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STREXH (uint32_t) __builtin_arm_strex

/**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STREXW (uint32_t) __builtin_arm_strex

/**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
#define __CLREX __builtin_arm_clrex

/**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
/*#define __SSAT             __builtin_arm_ssat*/
#define __SSAT(ARG1, ARG2)                                           \
  ({                                                                 \
    int32_t __RES, __ARG1 = (ARG1);                                  \
    __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                           \
  })

/**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
#define __USAT __builtin_arm_usat
#if 0
#define __USAT(ARG1, ARG2)                                           \
  ({                                                                 \
    uint32_t __RES, __ARG1 = (ARG1);                                 \
    __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                           \
  })
#endif

/**
  \brief   Rotate Right with Extend (32 bit)
  \details Moves each bit of a bitstring right by one bit.
           The carry input is shifted in at the left end of the bitstring.
  \param [in]    value  Value to rotate
  \return               Rotated value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) {
  uint32_t result;

  __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
}

/**
  \brief   LDRT Unprivileged (8 bit)
  \details Executes a Unprivileged LDRT instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) {
  uint32_t result;

  __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr));
  return ((uint8_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDRT Unprivileged (16 bit)
  \details Executes a Unprivileged LDRT instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) {
  uint32_t result;

  __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr));
  return ((uint16_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDRT Unprivileged (32 bit)
  \details Executes a Unprivileged LDRT instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) {
  uint32_t result;

  __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr));
  return (result);
}

/**
  \brief   STRT Unprivileged (8 bit)
  \details Executes a Unprivileged STRT instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); }

/**
  \brief   STRT Unprivileged (16 bit)
  \details Executes a Unprivileged STRT instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); }

/**
  \brief   STRT Unprivileged (32 bit)
  \details Executes a Unprivileged STRT instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); }

#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */

#if (__ARM_ARCH_8M__ == 1U)

/**
  \brief   Load-Acquire (8 bit)
  \details Executes a LDAB instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) {
  uint32_t result;

  __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr));
  return ((uint8_t)result);
}

/**
  \brief   Load-Acquire (16 bit)
  \details Executes a LDAH instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) {
  uint32_t result;

  __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr));
  return ((uint16_t)result);
}

/**
  \brief   Load-Acquire (32 bit)
  \details Executes a LDA instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) {
  uint32_t result;

  __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr));
  return (result);
}

/**
  \brief   Store-Release (8 bit)
  \details Executes a STLB instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); }

/**
  \brief   Store-Release (16 bit)
  \details Executes a STLH instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); }

/**
  \brief   Store-Release (32 bit)
  \details Executes a STL instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); }

/**
  \brief   Load-Acquire Exclusive (8 bit)
  \details Executes a LDAB exclusive instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
#define __LDAEXB (uint8_t) __builtin_arm_ldaex

/**
  \brief   Load-Acquire Exclusive (16 bit)
  \details Executes a LDAH exclusive instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
#define __LDAEXH (uint16_t) __builtin_arm_ldaex

/**
  \brief   Load-Acquire Exclusive (32 bit)
  \details Executes a LDA exclusive instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
#define __LDAEX (uint32_t) __builtin_arm_ldaex

/**
  \brief   Store-Release Exclusive (8 bit)
  \details Executes a STLB exclusive instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STLEXB (uint32_t) __builtin_arm_stlex

/**
  \brief   Store-Release Exclusive (16 bit)
  \details Executes a STLH exclusive instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STLEXH (uint32_t) __builtin_arm_stlex

/**
  \brief   Store-Release Exclusive (32 bit)
  \details Executes a STL exclusive instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
#define __STLEX (uint32_t) __builtin_arm_stlex

#endif /* (__ARM_ARCH_8M__ == 1U) */

/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

/* ###################  Compiler specific Intrinsics  ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  Access to dedicated SIMD instructions
  @{
*/

#if (__ARM_FEATURE_DSP == 1U) /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

#define __SSAT16(ARG1, ARG2)                                           \
  ({                                                                   \
    uint32_t __RES, __ARG1 = (ARG1);                                   \
    __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                             \
  })

#define __USAT16(ARG1, ARG2)                                           \
  ({                                                                   \
    uint32_t __RES, __ARG1 = (ARG1);                                   \
    __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                             \
  })

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) {
  uint32_t result;

  __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) {
  uint32_t result;

  __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) {
  int32_t result;

  __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) {
  int32_t result;

  __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

#define __PKHBT(ARG1, ARG2, ARG3)                                                          \
  ({                                                                                       \
    uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);                                      \
    __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
    __RES;                                                                                 \
  })

#define __PKHTB(ARG1, ARG2, ARG3)                                                            \
  ({                                                                                         \
    uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);                                        \
    if (ARG3 == 0)                                                                           \
      __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2));                    \
    else                                                                                     \
      __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
    __RES;                                                                                   \
  })

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) {
  int32_t result;

  __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

#endif /* (__ARM_FEATURE_DSP == 1U) */
/*@} end of group CMSIS_SIMD_intrinsics */

#endif /* __CMSIS_ARMCC_V6_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/cmsis_gcc.h
================================================
/**************************************************************************/ /**
                                                                              * @file     cmsis_gcc.h
                                                                              * @brief    CMSIS Cortex-M Core Function/Instruction Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H

/* ignore some GCC warnings */
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif

/* ###########################  Core Function Access  ########################### */
/** \ingroup  CMSIS_Core_FunctionInterface
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  @{
 */

/**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { __ASM volatile("cpsie i" : : : "memory"); }

/**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { __ASM volatile("cpsid i" : : : "memory"); }

/**
  \brief   Get Control Register
  \details Returns the content of the Control Register.
  \return               Control Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) {
  uint32_t result;

  __ASM volatile("MRS %0, control" : "=r"(result));
  return (result);
}

/**
  \brief   Set Control Register
  \details Writes the given value to the Control Register.
  \param [in]    control  Control Register value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); }

/**
  \brief   Get IPSR Register
  \details Returns the content of the IPSR Register.
  \return               IPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, ipsr" : "=r"(result));
  return (result);
}

/**
  \brief   Get APSR Register
  \details Returns the content of the APSR Register.
  \return               APSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, apsr" : "=r"(result));
  return (result);
}

/**
  \brief   Get xPSR Register
  \details Returns the content of the xPSR Register.

    \return               xPSR Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) {
  uint32_t result;

  __ASM volatile("MRS %0, xpsr" : "=r"(result));
  return (result);
}

/**
  \brief   Get Process Stack Pointer
  \details Returns the current value of the Process Stack Pointer (PSP).
  \return               PSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) {
  uint32_t result;

  __ASM volatile("MRS %0, psp\n" : "=r"(result));
  return (result);
}

/**
  \brief   Set Process Stack Pointer
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack) : "sp"); }

/**
  \brief   Get Main Stack Pointer
  \details Returns the current value of the Main Stack Pointer (MSP).
  \return               MSP Register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) {
  uint32_t result;

  __ASM volatile("MRS %0, msp\n" : "=r"(result));
  return (result);
}

/**
  \brief   Set Main Stack Pointer
  \details Assigns the given value to the Main Stack Pointer (MSP).

    \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack) : "sp"); }

/**
  \brief   Get Priority Mask
  \details Returns the current state of the priority mask bit from the Priority Mask Register.
  \return               Priority Mask value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) {
  uint32_t result;

  __ASM volatile("MRS %0, primask" : "=r"(result));
  return (result);
}

/**
  \brief   Set Priority Mask
  \details Assigns the given value to the Priority Mask Register.
  \param [in]    priMask  Priority Mask
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); }

#if (__CORTEX_M >= 0x03U)

/**
  \brief   Enable FIQ
  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile("cpsie f" : : : "memory"); }

/**
  \brief   Disable FIQ
  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile("cpsid f" : : : "memory"); }

/**
  \brief   Get Base Priority
  \details Returns the current value of the Base Priority register.
  \return               Base Priority register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) {
  uint32_t result;

  __ASM volatile("MRS %0, basepri" : "=r"(result));
  return (result);
}

/**
  \brief   Set Base Priority
  \details Assigns the given value to the Base Priority register.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); }

/**
  \brief   Set Base Priority with condition
  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
           or the new value increases the BASEPRI priority level.
  \param [in]    basePri  Base Priority value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) { __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); }

/**
  \brief   Get Fault Mask
  \details Returns the current value of the Fault Mask register.
  \return               Fault Mask register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) {
  uint32_t result;

  __ASM volatile("MRS %0, faultmask" : "=r"(result));
  return (result);
}

/**
  \brief   Set Fault Mask
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); }

#endif /* (__CORTEX_M >= 0x03U) */

#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)

/**
  \brief   Get FPSCR
  \details Returns the current value of the Floating Point Status/Control register.
  \return               Floating Point Status/Control register value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  uint32_t result;

  /* Empty asm statement works as a scheduling barrier */
  __ASM volatile("");
  __ASM volatile("VMRS %0, fpscr" : "=r"(result));
  __ASM volatile("");
  return (result);
#else
  return (0);
#endif
}

/**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
  /* Empty asm statement works as a scheduling barrier */
  __ASM volatile("");
  __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc");
  __ASM volatile("");
#endif
}

#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */

/*@} end of CMSIS_Core_RegAccFunctions */

/* ##########################  Core Instruction Access  ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  Access to dedicated instructions
  @{
*/

/* Define macros for porting to both thumb1 and thumb2.
 * For thumb1, use low register (r0-r7), specified by constraint "l"
 * Otherwise, use general registers, specified by constraint "r" */
#if defined(__thumb__) && !defined(__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
#define __CMSIS_GCC_USE_REG(r) "l"(r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
#define __CMSIS_GCC_USE_REG(r) "r"(r)
#endif

/**
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile("nop"); }

/**
  \brief   Wait For Interrupt
  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
 */
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { __ASM volatile("wfi"); }

/**
  \brief   Wait For Event
  \details Wait For Event is a hint instruction that permits the processor to enter
    a low-power state until one of a number of events occurs.
 */
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { __ASM volatile("wfe"); }

/**
  \brief   Send Event
  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { __ASM volatile("sev"); }

/**
  \brief   Instruction Synchronization Barrier
  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
           so that all instructions following the ISB are fetched from cache or memory,
           after the instruction has been completed.
 */
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { __ASM volatile("isb 0xF" ::: "memory"); }

/**
  \brief   Data Synchronization Barrier
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { __ASM volatile("dsb 0xF" ::: "memory"); }

/**
  \brief   Data Memory Barrier
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { __ASM volatile("dmb 0xF" ::: "memory"); }

/**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in integer value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) {
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
  return __builtin_bswap32(value);
#else
  uint32_t result;

  __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
#endif
}

/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in two unsigned short values.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) {
  uint32_t result;

  __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
}

/**
  \brief   Reverse byte order in signed short value
  \details Reverses the byte order in a signed short value with sign extension to integer.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) {
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  return (short)__builtin_bswap16(value);
#else
  int32_t result;

  __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
#endif
}

/**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    value  Value to rotate
  \param [in]    value  Number of Bits to rotate
  \return               Rotated value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32U - op2)); }

/**
  \brief   Breakpoint
  \details Causes the processor to enter Debug state.
           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
#define __BKPT(value) __ASM volatile("bkpt " #value)

/**
  \brief   Reverse bit order of value
  \details Reverses the bit order of the given value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
  uint32_t result;

#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
  __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
#else
  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */

  result = value; /* r will be reversed bits of v; first get LSB of v */
  for (value >>= 1U; value; value >>= 1U) {
    result <<= 1U;
    result |= value & 1U;
    s--;
  }
  result <<= s; /* shift when v's highest bits are zero */
#endif
  return (result);
}

/**
  \brief   Count leading zeros
  \details Counts the number of leading zeros of a data value.
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
#define __CLZ __builtin_clz

#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)

/**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) {
  uint32_t result;

#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr));
#else
  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
     accepted by assembler. So has to use following less efficient pattern.
  */
  __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
#endif
  return ((uint8_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) {
  uint32_t result;

#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr));
#else
  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
     accepted by assembler. So has to use following less efficient pattern.
  */
  __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
#endif
  return ((uint16_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) {
  uint32_t result;

  __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr));
  return (result);
}

/**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) {
  uint32_t result;

  __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value));
  return (result);
}

/**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) {
  uint32_t result;

  __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value));
  return (result);
}

/**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) {
  uint32_t result;

  __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value));
  return (result);
}

/**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile("clrex" ::: "memory"); }

/**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
#define __SSAT(ARG1, ARG2)                                           \
  ({                                                                 \
    uint32_t __RES, __ARG1 = (ARG1);                                 \
    __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                           \
  })

/**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
#define __USAT(ARG1, ARG2)                                           \
  ({                                                                 \
    uint32_t __RES, __ARG1 = (ARG1);                                 \
    __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                           \
  })

/**
  \brief   Rotate Right with Extend (32 bit)
  \details Moves each bit of a bitstring right by one bit.
           The carry input is shifted in at the left end of the bitstring.
  \param [in]    value  Value to rotate
  \return               Rotated value
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) {
  uint32_t result;

  __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  return (result);
}

/**
  \brief   LDRT Unprivileged (8 bit)
  \details Executes a Unprivileged LDRT instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) {
  uint32_t result;

#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*addr));
#else
  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
     accepted by assembler. So has to use following less efficient pattern.
  */
  __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
#endif
  return ((uint8_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDRT Unprivileged (16 bit)
  \details Executes a Unprivileged LDRT instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) {
  uint32_t result;

#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*addr));
#else
  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
     accepted by assembler. So has to use following less efficient pattern.
  */
  __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(addr) : "memory");
#endif
  return ((uint16_t)result); /* Add explicit type cast here */
}

/**
  \brief   LDRT Unprivileged (32 bit)
  \details Executes a Unprivileged LDRT instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) {
  uint32_t result;

  __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*addr));
  return (result);
}

/**
  \brief   STRT Unprivileged (8 bit)
  \details Executes a Unprivileged STRT instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM volatile("strbt %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); }

/**
  \brief   STRT Unprivileged (16 bit)
  \details Executes a Unprivileged STRT instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM volatile("strht %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); }

/**
  \brief   STRT Unprivileged (32 bit)
  \details Executes a Unprivileged STRT instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM volatile("strt %1, %0" : "=Q"(*addr) : "r"(value)); }

#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */

/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

/* ###################  Compiler specific Intrinsics  ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  Access to dedicated SIMD instructions
  @{
*/

#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

#define __SSAT16(ARG1, ARG2)                                           \
  ({                                                                   \
    int32_t __RES, __ARG1 = (ARG1);                                    \
    __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                             \
  })

#define __USAT16(ARG1, ARG2)                                           \
  ({                                                                   \
    uint32_t __RES, __ARG1 = (ARG1);                                   \
    __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \
    __RES;                                                             \
  })

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) {
  uint32_t result;

  __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) {
  uint32_t result;

  __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) {
  uint32_t result;

  __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) {
  union llreg_u {
    uint32_t w32[2];
    uint64_t w64;
  } llr;
  llr.w64 = acc;

#ifndef __ARMEB__ /* Little endian */
  __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]) : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
#else /* Big endian */
  __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]) : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
#endif

  return (llr.w64);
}

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) {
  uint32_t result;

  __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) {
  int32_t result;

  __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) {
  int32_t result;

  __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  return (result);
}

#define __PKHBT(ARG1, ARG2, ARG3)                                                          \
  ({                                                                                       \
    uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);                                      \
    __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
    __RES;                                                                                 \
  })

#define __PKHTB(ARG1, ARG2, ARG3)                                                            \
  ({                                                                                         \
    uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2);                                        \
    if (ARG3 == 0)                                                                           \
      __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2));                    \
    else                                                                                     \
      __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
    __RES;                                                                                   \
  })

__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) {
  int32_t result;

  __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  return (result);
}

#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */

#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif

#endif /* __CMSIS_GCC_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cm0.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cm0.h
                                                                              * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup Cortex_M0
  @{
 */

/*  CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION      ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_M (0x00U) /*!< Cortex-M Core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
*/
#define __FPU_USED 0U

#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM0_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group Cortex_M0 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[31U];
  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[31U];
  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[31U];
  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[31U];
  uint32_t       RESERVED4[64U];
  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
} NVIC_Type;

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  uint32_t       RESERVED0;
  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  uint32_t       RESERVED1;
  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
            Therefore they are not covered by the Cortex-M0 header file.
  @{
 */
/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  } else {
    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB(); /* Ensure all outstanding memory accesses included
              buffered write are completed before reset */
  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
  __DSB(); /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM0_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cm0plus.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cm0plus.h
                                                                              * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup Cortex-M0+
  @{
 */

/*  CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                                               /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                                               /*!< [15:0]  CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_M (0x00U) /*!< Cortex-M Core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
*/
#define __FPU_USED 0U

#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM0PLUS_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group Cortex-M0+ */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core MPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[31U];
  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[31U];
  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[31U];
  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[31U];
  uint32_t       RESERVED4[64U];
  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
} NVIC_Type;

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
  __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
#else
  uint32_t RESERVED0;
#endif
  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  uint32_t       RESERVED1;
  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U                                  /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U                                /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
            Therefore they are not covered by the Cortex-M0+ header file.
  @{
 */
/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  } else {
    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB(); /* Ensure all outstanding memory accesses included
              buffered write are completed before reset */
  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
  __DSB(); /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM0PLUS_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cm3.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cm3.h
                                                                              * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup Cortex_M3
  @{
 */

/*  CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION      ((__CM3_CMSIS_VERSION_MAIN << 16U) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_M (0x03U) /*!< Cortex-M Core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
*/
#define __FPU_USED 0U

#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM3_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
#define __CM3_REV 0x0200U
#warning "__CM3_REV not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group Cortex_M3 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core Debug Register
  - Core MPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

#define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t IT : 2;          /*!< bit: 25..26  saved IT state   (read 0) */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_Q_Pos 27U                 /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */

#define xPSR_IT_Pos 25U                  /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[24U];
  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[24U];
  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[24U];
  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[24U];
  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
  uint32_t       RESERVED4[56U];
  __IOM uint8_t  IP[240U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
  uint32_t       RESERVED5[644U];
  __OM uint32_t  STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
} NVIC_Type;

/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U                                   /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
  __IOM uint32_t AIRCR;    /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;      /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;      /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  __IOM uint8_t  SHP[12U]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  __IOM uint32_t SHCSR;    /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
  __IOM uint32_t CFSR;     /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
  __IOM uint32_t HFSR;     /*!< Offset: 0x02C (R/W)  HardFault Status Register */
  __IOM uint32_t DFSR;     /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
  __IOM uint32_t MMFAR;    /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
  __IOM uint32_t BFAR;     /*!< Offset: 0x038 (R/W)  BusFault Address Register */
  __IOM uint32_t AFSR;     /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
  __IM uint32_t  PFR[2U];  /*!< Offset: 0x040 (R/ )  Processor Feature Register */
  __IM uint32_t  DFR;      /*!< Offset: 0x048 (R/ )  Debug Feature Register */
  __IM uint32_t  ADR;      /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
  __IM uint32_t  MMFR[4U]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
  __IM uint32_t  ISAR[5U]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
  uint32_t       RESERVED0[5U];
  __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_RETTOBASE_Pos 11U                             /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201U)                                  /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U                           /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */

#define SCB_VTOR_TBLOFF_Pos 7U                                  /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#else
#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U                              /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

#define SCB_AIRCR_VECTRESET_Pos 0U                                   /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_BFHFNMIGN_Pos 8U                             /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */

#define SCB_CCR_DIV_0_TRP_Pos 4U                             /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

#define SCB_CCR_USERSETMPEND_Pos 1U                                /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */

#define SCB_CCR_NONBASETHRDENA_Pos 0U                                      /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U                                /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */

#define SCB_SHCSR_BUSFAULTENA_Pos 17U                                /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */

#define SCB_SHCSR_MEMFAULTENA_Pos 16U                                /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */

#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U                                   /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U                                   /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U                                   /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */

#define SCB_SHCSR_SYSTICKACT_Pos 11U                               /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */

#define SCB_SHCSR_PENDSVACT_Pos 10U                              /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */

#define SCB_SHCSR_MONITORACT_Pos 8U                                /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */

#define SCB_SHCSR_SVCALLACT_Pos 7U                               /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */

#define SCB_SHCSR_USGFAULTACT_Pos 3U                                 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */

#define SCB_SHCSR_BUSFAULTACT_Pos 1U                                 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */

#define SCB_SHCSR_MEMFAULTACT_Pos 0U                                     /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */

/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U                                   /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */

#define SCB_CFSR_BUSFAULTSR_Pos 8U                                  /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */

#define SCB_CFSR_MEMFAULTSR_Pos 0U                                      /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U                            /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */

#define SCB_HFSR_FORCED_Pos 30U                          /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */

#define SCB_HFSR_VECTTBL_Pos 1U                            /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */

/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U                             /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */

#define SCB_DFSR_VCATCH_Pos 3U                           /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */

#define SCB_DFSR_DWTTRAP_Pos 2U                            /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */

#define SCB_DFSR_BKPT_Pos 1U                         /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */

#define SCB_DFSR_HALTED_Pos 0U                               /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */

/**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct {
  uint32_t      RESERVED0[1U];
  __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
#else
  uint32_t RESERVED1[1U];
#endif
} SCnSCB_Type;

/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U                                         /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */

/* Auxiliary Control Register Definitions */

#define SCnSCB_ACTLR_DISFOLD_Pos 2U                                /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U                                   /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */

/*@} end of group CMSIS_SCnotSCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
  @{
 */

/**
  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 */
typedef struct {
  __OM union {
    __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
    __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
    __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
  } PORT[32U];         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
  uint32_t       RESERVED0[864U];
  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
  uint32_t       RESERVED1[15U];
  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
  uint32_t       RESERVED2[15U];
  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
  uint32_t       RESERVED3[29U];
  __OM uint32_t  IWR;  /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
  __IM uint32_t  IRR;  /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
  uint32_t       RESERVED4[43U];
  __OM uint32_t  LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
  __IM uint32_t  LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
  uint32_t       RESERVED5[6U];
  __IM uint32_t  PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
  __IM uint32_t  PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
  __IM uint32_t  PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
  __IM uint32_t  PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
  __IM uint32_t  PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
  __IM uint32_t  PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
  __IM uint32_t  PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
  __IM uint32_t  PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
  __IM uint32_t  CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
  __IM uint32_t  CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
  __IM uint32_t  CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
  __IM uint32_t  CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
} ITM_Type;

/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U                                  /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */

/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U                       /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */

#define ITM_TCR_TraceBusID_Pos 16U                                /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */

#define ITM_TCR_GTSFREQ_Pos 10U                          /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */

#define ITM_TCR_TSPrescale_Pos 8U                              /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */

#define ITM_TCR_SWOENA_Pos 4U                          /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */

#define ITM_TCR_DWTENA_Pos 3U                          /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */

#define ITM_TCR_SYNCENA_Pos 2U                           /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */

#define ITM_TCR_TSENA_Pos 1U                         /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */

#define ITM_TCR_ITMENA_Pos 0U                              /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */

/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U                                /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */

/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U                                /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */

/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U                                    /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */

/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U                           /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */

#define ITM_LSR_Access_Pos 1U                          /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */

#define ITM_LSR_Present_Pos 0U                               /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */

/*@}*/ /* end of group CMSIS_ITM */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
  @{
 */

/**
  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct {
  __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
  __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
  __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
  __IOM uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
  __IOM uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register */
  __IOM uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register */
  __IOM uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
  __IM uint32_t  PCSR;      /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
  __IOM uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
  __IOM uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0 */
  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0 */
  uint32_t       RESERVED0[1U];
  __IOM uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
  __IOM uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1 */
  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1 */
  uint32_t       RESERVED1[1U];
  __IOM uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
  __IOM uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2 */
  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2 */
  uint32_t       RESERVED2[1U];
  __IOM uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
  __IOM uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3 */
  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3 */
} DWT_Type;

/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U                             /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */

#define DWT_CTRL_NOTRCPKT_Pos 27U                              /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */

#define DWT_CTRL_NOEXTTRIG_Pos 26U                               /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */

#define DWT_CTRL_NOCYCCNT_Pos 25U                              /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */

#define DWT_CTRL_NOPRFCNT_Pos 24U                              /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */

#define DWT_CTRL_CYCEVTENA_Pos 22U                               /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */

#define DWT_CTRL_FOLDEVTENA_Pos 21U                                /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */

#define DWT_CTRL_LSUEVTENA_Pos 20U                               /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */

#define DWT_CTRL_SLEEPEVTENA_Pos 19U                                 /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */

#define DWT_CTRL_EXCEVTENA_Pos 18U                               /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */

#define DWT_CTRL_CPIEVTENA_Pos 17U                               /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */

#define DWT_CTRL_EXCTRCENA_Pos 16U                               /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */

#define DWT_CTRL_PCSAMPLENA_Pos 12U                                /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */

#define DWT_CTRL_SYNCTAP_Pos 10U                             /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */

#define DWT_CTRL_CYCTAP_Pos 9U                             /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */

#define DWT_CTRL_POSTINIT_Pos 5U                               /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */

#define DWT_CTRL_POSTPRESET_Pos 1U                                 /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */

#define DWT_CTRL_CYCCNTENA_Pos 0U                                    /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */

/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U                                    /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */

/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U                                    /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */

/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U                                        /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */

/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U                                    /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */

/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U                                      /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */

/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U                                /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */

/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U                                 /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */

#define DWT_FUNCTION_DATAVADDR1_Pos 16U                                    /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */

#define DWT_FUNCTION_DATAVADDR0_Pos 12U                                    /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */

#define DWT_FUNCTION_DATAVSIZE_Pos 10U                                   /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */

#define DWT_FUNCTION_LNK1ENA_Pos 9U                                  /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */

#define DWT_FUNCTION_DATAVMATCH_Pos 8U                                     /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */

#define DWT_FUNCTION_CYCMATCH_Pos 7U                                   /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */

#define DWT_FUNCTION_EMITRANGE_Pos 5U                                    /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */

#define DWT_FUNCTION_FUNCTION_Pos 0U                                       /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */

/*@}*/ /* end of group CMSIS_DWT */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
  \brief    Type definitions for the Trace Port Interface (TPI)
  @{
 */

/**
  \brief  Structure type to access the Trace Port Interface Register (TPI).
 */
typedef struct {
  __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
  uint32_t       RESERVED0[2U];
  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
  uint32_t       RESERVED1[55U];
  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
  uint32_t       RESERVED2[131U];
  __IM uint32_t  FFSR; /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
  __IM uint32_t  FSCR; /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
  uint32_t       RESERVED3[759U];
  __IM uint32_t  TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
  __IM uint32_t  FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
  __IM uint32_t  ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
  uint32_t       RESERVED4[1U];
  __IM uint32_t  ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
  __IM uint32_t  FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
  __IOM uint32_t ITCTRL;    /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
  uint32_t       RESERVED5[39U];
  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
  uint32_t       RESERVED7[8U];
  __IM uint32_t  DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
  __IM uint32_t  DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
} TPI_Type;

/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U                                       /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */

/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U                                 /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */

/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U                                /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */

#define TPI_FFSR_TCPresent_Pos 2U                                /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */

#define TPI_FFSR_FtStopped_Pos 1U                                /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */

#define TPI_FFSR_FlInProg_Pos 0U                                   /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */

/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U                             /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */

#define TPI_FFCR_EnFCont_Pos 1U                              /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */

/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U                                     /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */

/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */

#define TPI_FIFO0_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */

#define TPI_FIFO0_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */

#define TPI_FIFO0_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */

#define TPI_FIFO0_ETM2_Pos 16U                            /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */

#define TPI_FIFO0_ETM1_Pos 8U                             /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */

#define TPI_FIFO0_ETM0_Pos 0U                                 /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */

/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */

/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */

#define TPI_FIFO1_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */

#define TPI_FIFO1_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */

#define TPI_FIFO1_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */

#define TPI_FIFO1_ITM2_Pos 16U                            /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */

#define TPI_FIFO1_ITM1_Pos 8U                             /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */

#define TPI_FIFO1_ITM0_Pos 0U                                 /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */

/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */

/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U                                 /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */

/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U                               /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */

#define TPI_DEVID_MANCVALID_Pos 10U                                /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */

#define TPI_DEVID_PTINVALID_Pos 9U                                 /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */

#define TPI_DEVID_MinBufSz_Pos 6U                                /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */

#define TPI_DEVID_AsynClkIn_Pos 5U                                 /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */

#define TPI_DEVID_NrTraceInput_Pos 0U                                         /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */

/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U                                   /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */

#define TPI_DEVTYPE_SubType_Pos 0U                                     /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */

/*@}*/ /* end of group CMSIS_TPI */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U                                 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Type definitions for the Core Debug Registers
  @{
 */

/**
  \brief  Structure type to access the Core Debug Register (CoreDebug).
 */
typedef struct {
  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
  __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
} CoreDebug_Type;

/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U                                      /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U                                     /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U                                      /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U                                   /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U                                  /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */

#define CoreDebug_DHCSR_S_HALT_Pos 17U                                 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U                                   /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U                                       /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U                                      /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */

#define CoreDebug_DHCSR_C_STEP_Pos 2U                                  /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */

#define CoreDebug_DHCSR_C_HALT_Pos 1U                                  /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U                                         /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U                                 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */

#define CoreDebug_DCRSR_REGSEL_Pos 0U                                         /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */

/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U                                 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */

#define CoreDebug_DEMCR_MON_REQ_Pos 19U                                  /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */

#define CoreDebug_DEMCR_MON_STEP_Pos 18U                                   /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */

#define CoreDebug_DEMCR_MON_PEND_Pos 17U                                   /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */

#define CoreDebug_DEMCR_MON_EN_Pos 16U                                 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U                                     /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U                                     /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U                                     /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U                                      /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U                                     /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U                                      /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U                                    /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */

/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE       (0xE000E000UL)        /*!< System Control Space Base Address */
#define ITM_BASE       (0xE0000000UL)        /*!< ITM Base Address */
#define DWT_BASE       (0xE0001000UL)        /*!< DWT Base Address */
#define TPI_BASE       (0xE0040000UL)        /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL)        /*!< Core Debug Base Address */
#define SysTick_BASE   (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE      (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE       (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCnSCB    ((SCnSCB_Type *)SCS_BASE)          /*!< System control Register not in SCB */
#define SCB       ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct */
#define SysTick   ((SysTick_Type *)SysTick_BASE)     /*!< SysTick configuration struct */
#define NVIC      ((NVIC_Type *)NVIC_BASE)           /*!< NVIC configuration struct */
#define ITM       ((ITM_Type *)ITM_BASE)             /*!< ITM configuration struct */
#define DWT       ((DWT_Type *)DWT_BASE)             /*!< DWT configuration struct */
#define TPI       ((TPI_Type *)TPI_BASE)             /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Debug Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/**
  \brief   Set Priority Grouping
  \details Sets the priority grouping field using the required unlock sequence.
           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
           Only values from 0..7 are used.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */

  reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
  SCB->AIRCR = reg_value;
}

/**
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
  return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Active Interrupt
  \details Reads the active register in NVIC and returns the active bit.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not active.
  \return             1  Interrupt status is active.
 */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  } else {
    NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}

/**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                      buffered write are completed before reset */
  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
  __DSB();                                                                                                                         /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

/* ##################################### Debug In/Output function ########################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_core_DebugFunctions ITM Functions
  \brief    Functions that access the ITM debug interface.
  @{
 */

extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

/**
  \brief   ITM Send Character
  \details Transmits a character via the ITM channel 0, and
           \li Just returns when no debugger is connected that has booked the output.
           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  \param [in]     ch  Character to transmit.
  \returns            Character to transmit.
 */
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
      ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
  {
    while (ITM->PORT[0U].u32 == 0UL) {
      __NOP();
    }
    ITM->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}

/**
  \brief   ITM Receive Character
  \details Inputs a character via the external variable \ref ITM_RxBuffer.
  \return             Received character.
  \return         -1  No character pending.
 */
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
  int32_t ch = -1; /* no character available */

  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
    ch           = ITM_RxBuffer;
    ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
  }

  return (ch);
}

/**
  \brief   ITM Check Character
  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
  \return          0  No character available.
  \return          1  Character available.
 */
__STATIC_INLINE int32_t ITM_CheckChar(void) {

  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
    return (0); /* no character available */
  } else {
    return (1); /*    character available */
  }
}

/*@} end of CMSIS_core_DebugFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM3_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cm4.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cm4.h
                                                                              * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CM4_H_GENERIC
#define __CORE_CM4_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup Cortex_M4
  @{
 */

/*  CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION      ((__CM4_CMSIS_VERSION_MAIN << 16U) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_M (0x04U) /*!< Cortex-M Core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmSimd.h"  /* Compiler specific SIMD Intrinsics */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM4_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_CM4_H_DEPENDANT
#define __CORE_CM4_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM4_REV
#define __CM4_REV 0x0000U
#warning "__CM4_REV not defined in device header file; using default!"
#endif

#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group Cortex_M4 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core Debug Register
  - Core MPU Register
  - Core FPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved */
    uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags */
    uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

#define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */

#define APSR_GE_Pos 16U                    /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;        /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 7; /*!< bit:  9..15  Reserved */
    uint32_t GE : 4;         /*!< bit: 16..19  Greater than or Equal flags */
    uint32_t _reserved1 : 4; /*!< bit: 20..23  Reserved */
    uint32_t T : 1;          /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t IT : 2;         /*!< bit: 25..26  saved IT state   (read 0) */
    uint32_t Q : 1;          /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;          /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;          /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;          /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;          /*!< bit:     31  Negative condition code flag */
  } b;                       /*!< Structure used for bit  access */
  uint32_t w;                /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_Q_Pos 27U                 /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */

#define xPSR_IT_Pos 25U                  /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_GE_Pos 16U                    /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag */
    uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_FPCA_Pos 2U                        /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */

#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[24U];
  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[24U];
  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[24U];
  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[24U];
  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
  uint32_t       RESERVED4[56U];
  __IOM uint8_t  IP[240U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
  uint32_t       RESERVED5[644U];
  __OM uint32_t  STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
} NVIC_Type;

/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U                                   /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
  __IOM uint32_t AIRCR;    /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;      /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;      /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  __IOM uint8_t  SHP[12U]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  __IOM uint32_t SHCSR;    /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
  __IOM uint32_t CFSR;     /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
  __IOM uint32_t HFSR;     /*!< Offset: 0x02C (R/W)  HardFault Status Register */
  __IOM uint32_t DFSR;     /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
  __IOM uint32_t MMFAR;    /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
  __IOM uint32_t BFAR;     /*!< Offset: 0x038 (R/W)  BusFault Address Register */
  __IOM uint32_t AFSR;     /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
  __IM uint32_t  PFR[2U];  /*!< Offset: 0x040 (R/ )  Processor Feature Register */
  __IM uint32_t  DFR;      /*!< Offset: 0x048 (R/ )  Debug Feature Register */
  __IM uint32_t  ADR;      /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
  __IM uint32_t  MMFR[4U]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
  __IM uint32_t  ISAR[5U]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
  uint32_t       RESERVED0[5U];
  __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_RETTOBASE_Pos 11U                             /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U                              /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

#define SCB_AIRCR_VECTRESET_Pos 0U                                   /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_BFHFNMIGN_Pos 8U                             /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */

#define SCB_CCR_DIV_0_TRP_Pos 4U                             /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

#define SCB_CCR_USERSETMPEND_Pos 1U                                /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */

#define SCB_CCR_NONBASETHRDENA_Pos 0U                                      /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U                                /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */

#define SCB_SHCSR_BUSFAULTENA_Pos 17U                                /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */

#define SCB_SHCSR_MEMFAULTENA_Pos 16U                                /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */

#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U                                   /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U                                   /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U                                   /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */

#define SCB_SHCSR_SYSTICKACT_Pos 11U                               /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */

#define SCB_SHCSR_PENDSVACT_Pos 10U                              /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */

#define SCB_SHCSR_MONITORACT_Pos 8U                                /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */

#define SCB_SHCSR_SVCALLACT_Pos 7U                               /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */

#define SCB_SHCSR_USGFAULTACT_Pos 3U                                 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */

#define SCB_SHCSR_BUSFAULTACT_Pos 1U                                 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */

#define SCB_SHCSR_MEMFAULTACT_Pos 0U                                     /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */

/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U                                   /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */

#define SCB_CFSR_BUSFAULTSR_Pos 8U                                  /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */

#define SCB_CFSR_MEMFAULTSR_Pos 0U                                      /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U                            /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */

#define SCB_HFSR_FORCED_Pos 30U                          /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */

#define SCB_HFSR_VECTTBL_Pos 1U                            /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */

/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U                             /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */

#define SCB_DFSR_VCATCH_Pos 3U                           /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */

#define SCB_DFSR_DWTTRAP_Pos 2U                            /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */

#define SCB_DFSR_BKPT_Pos 1U                         /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */

#define SCB_DFSR_HALTED_Pos 0U                               /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */

/**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct {
  uint32_t       RESERVED0[1U];
  __IM uint32_t  ICTR;  /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
} SCnSCB_Type;

/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U                                         /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */

/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISOOFP_Pos 9U                                /*!< ACTLR: DISOOFP Position */
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */

#define SCnSCB_ACTLR_DISFPCA_Pos 8U                                /*!< ACTLR: DISFPCA Position */
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */

#define SCnSCB_ACTLR_DISFOLD_Pos 2U                                /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U                                   /*!< ACTLR: DISDEFWBUF Position */
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */

/*@} end of group CMSIS_SCnotSCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
  @{
 */

/**
  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 */
typedef struct {
  __OM union {
    __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
    __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
    __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
  } PORT[32U];         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
  uint32_t       RESERVED0[864U];
  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
  uint32_t       RESERVED1[15U];
  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
  uint32_t       RESERVED2[15U];
  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
  uint32_t       RESERVED3[29U];
  __OM uint32_t  IWR;  /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
  __IM uint32_t  IRR;  /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
  uint32_t       RESERVED4[43U];
  __OM uint32_t  LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
  __IM uint32_t  LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
  uint32_t       RESERVED5[6U];
  __IM uint32_t  PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
  __IM uint32_t  PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
  __IM uint32_t  PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
  __IM uint32_t  PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
  __IM uint32_t  PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
  __IM uint32_t  PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
  __IM uint32_t  PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
  __IM uint32_t  PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
  __IM uint32_t  CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
  __IM uint32_t  CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
  __IM uint32_t  CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
  __IM uint32_t  CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
} ITM_Type;

/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U                                  /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */

/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U                       /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */

#define ITM_TCR_TraceBusID_Pos 16U                                /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */

#define ITM_TCR_GTSFREQ_Pos 10U                          /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */

#define ITM_TCR_TSPrescale_Pos 8U                              /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */

#define ITM_TCR_SWOENA_Pos 4U                          /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */

#define ITM_TCR_DWTENA_Pos 3U                          /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */

#define ITM_TCR_SYNCENA_Pos 2U                           /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */

#define ITM_TCR_TSENA_Pos 1U                         /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */

#define ITM_TCR_ITMENA_Pos 0U                              /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */

/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U                                /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */

/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U                                /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */

/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U                                    /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */

/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U                           /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */

#define ITM_LSR_Access_Pos 1U                          /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */

#define ITM_LSR_Present_Pos 0U                               /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */

/*@}*/ /* end of group CMSIS_ITM */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
  @{
 */

/**
  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct {
  __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
  __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
  __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
  __IOM uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
  __IOM uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register */
  __IOM uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register */
  __IOM uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
  __IM uint32_t  PCSR;      /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
  __IOM uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
  __IOM uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0 */
  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0 */
  uint32_t       RESERVED0[1U];
  __IOM uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
  __IOM uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1 */
  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1 */
  uint32_t       RESERVED1[1U];
  __IOM uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
  __IOM uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2 */
  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2 */
  uint32_t       RESERVED2[1U];
  __IOM uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
  __IOM uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3 */
  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3 */
} DWT_Type;

/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U                             /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */

#define DWT_CTRL_NOTRCPKT_Pos 27U                              /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */

#define DWT_CTRL_NOEXTTRIG_Pos 26U                               /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */

#define DWT_CTRL_NOCYCCNT_Pos 25U                              /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */

#define DWT_CTRL_NOPRFCNT_Pos 24U                              /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */

#define DWT_CTRL_CYCEVTENA_Pos 22U                               /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */

#define DWT_CTRL_FOLDEVTENA_Pos 21U                                /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */

#define DWT_CTRL_LSUEVTENA_Pos 20U                               /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */

#define DWT_CTRL_SLEEPEVTENA_Pos 19U                                 /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */

#define DWT_CTRL_EXCEVTENA_Pos 18U                               /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */

#define DWT_CTRL_CPIEVTENA_Pos 17U                               /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */

#define DWT_CTRL_EXCTRCENA_Pos 16U                               /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */

#define DWT_CTRL_PCSAMPLENA_Pos 12U                                /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */

#define DWT_CTRL_SYNCTAP_Pos 10U                             /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */

#define DWT_CTRL_CYCTAP_Pos 9U                             /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */

#define DWT_CTRL_POSTINIT_Pos 5U                               /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */

#define DWT_CTRL_POSTPRESET_Pos 1U                                 /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */

#define DWT_CTRL_CYCCNTENA_Pos 0U                                    /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */

/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U                                    /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */

/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U                                    /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */

/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U                                        /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */

/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U                                    /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */

/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U                                      /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */

/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U                                /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */

/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U                                 /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */

#define DWT_FUNCTION_DATAVADDR1_Pos 16U                                    /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */

#define DWT_FUNCTION_DATAVADDR0_Pos 12U                                    /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */

#define DWT_FUNCTION_DATAVSIZE_Pos 10U                                   /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */

#define DWT_FUNCTION_LNK1ENA_Pos 9U                                  /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */

#define DWT_FUNCTION_DATAVMATCH_Pos 8U                                     /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */

#define DWT_FUNCTION_CYCMATCH_Pos 7U                                   /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */

#define DWT_FUNCTION_EMITRANGE_Pos 5U                                    /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */

#define DWT_FUNCTION_FUNCTION_Pos 0U                                       /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */

/*@}*/ /* end of group CMSIS_DWT */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
  \brief    Type definitions for the Trace Port Interface (TPI)
  @{
 */

/**
  \brief  Structure type to access the Trace Port Interface Register (TPI).
 */
typedef struct {
  __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
  uint32_t       RESERVED0[2U];
  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
  uint32_t       RESERVED1[55U];
  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
  uint32_t       RESERVED2[131U];
  __IM uint32_t  FFSR; /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
  __IM uint32_t  FSCR; /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
  uint32_t       RESERVED3[759U];
  __IM uint32_t  TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
  __IM uint32_t  FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
  __IM uint32_t  ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
  uint32_t       RESERVED4[1U];
  __IM uint32_t  ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
  __IM uint32_t  FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
  __IOM uint32_t ITCTRL;    /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
  uint32_t       RESERVED5[39U];
  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
  uint32_t       RESERVED7[8U];
  __IM uint32_t  DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
  __IM uint32_t  DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
} TPI_Type;

/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U                                       /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */

/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U                                 /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */

/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U                                /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */

#define TPI_FFSR_TCPresent_Pos 2U                                /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */

#define TPI_FFSR_FtStopped_Pos 1U                                /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */

#define TPI_FFSR_FlInProg_Pos 0U                                   /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */

/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U                             /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */

#define TPI_FFCR_EnFCont_Pos 1U                              /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */

/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U                                     /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */

/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */

#define TPI_FIFO0_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */

#define TPI_FIFO0_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */

#define TPI_FIFO0_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */

#define TPI_FIFO0_ETM2_Pos 16U                            /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */

#define TPI_FIFO0_ETM1_Pos 8U                             /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */

#define TPI_FIFO0_ETM0_Pos 0U                                 /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */

/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */

/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */

#define TPI_FIFO1_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */

#define TPI_FIFO1_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */

#define TPI_FIFO1_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */

#define TPI_FIFO1_ITM2_Pos 16U                            /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */

#define TPI_FIFO1_ITM1_Pos 8U                             /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */

#define TPI_FIFO1_ITM0_Pos 0U                                 /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */

/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */

/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U                                 /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */

/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U                               /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */

#define TPI_DEVID_MANCVALID_Pos 10U                                /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */

#define TPI_DEVID_PTINVALID_Pos 9U                                 /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */

#define TPI_DEVID_MinBufSz_Pos 6U                                /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */

#define TPI_DEVID_AsynClkIn_Pos 5U                                 /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */

#define TPI_DEVID_NrTraceInput_Pos 0U                                         /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */

/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U                                   /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */

#define TPI_DEVTYPE_SubType_Pos 0U                                     /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */

/*@}*/ /* end of group CMSIS_TPI */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U                                 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

#if (__FPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
  \brief    Type definitions for the Floating Point Unit (FPU)
  @{
 */

/**
  \brief  Structure type to access the Floating Point Unit (FPU).
 */
typedef struct {
  uint32_t       RESERVED0[1U];
  __IOM uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
  __IOM uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
  __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
  __IM uint32_t  MVFR0;  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
  __IM uint32_t  MVFR1;  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
} FPU_Type;

/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U                          /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */

#define FPU_FPCCR_LSPEN_Pos 30U                          /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */

#define FPU_FPCCR_MONRDY_Pos 8U                            /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */

#define FPU_FPCCR_BFRDY_Pos 6U                           /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */

#define FPU_FPCCR_MMRDY_Pos 5U                           /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */

#define FPU_FPCCR_HFRDY_Pos 4U                           /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */

#define FPU_FPCCR_THREAD_Pos 3U                            /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */

#define FPU_FPCCR_USER_Pos 1U                          /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */

#define FPU_FPCCR_LSPACT_Pos 0U                                /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */

/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U                                      /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */

/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U                         /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */

#define FPU_FPDSCR_DN_Pos 25U                        /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */

#define FPU_FPDSCR_FZ_Pos 24U                        /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */

#define FPU_FPDSCR_RMode_Pos 22U                           /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */

/* Media and FP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U                                        /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */

#define FPU_MVFR0_Short_vectors_Pos 24U                                    /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */

#define FPU_MVFR0_Square_root_Pos 20U                                  /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */

#define FPU_MVFR0_Divide_Pos 16U                             /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */

#define FPU_MVFR0_FP_excep_trapping_Pos 12U                                        /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */

#define FPU_MVFR0_Double_precision_Pos 8U                                        /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */

#define FPU_MVFR0_Single_precision_Pos 4U                                        /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */

#define FPU_MVFR0_A_SIMD_registers_Pos 0U                                            /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */

/* Media and FP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U                                   /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */

#define FPU_MVFR1_FP_HPFP_Pos 24U                              /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */

#define FPU_MVFR1_D_NaN_mode_Pos 4U                                  /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */

#define FPU_MVFR1_FtZ_mode_Pos 0U                                    /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */

/*@} end of group CMSIS_FPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Type definitions for the Core Debug Registers
  @{
 */

/**
  \brief  Structure type to access the Core Debug Register (CoreDebug).
 */
typedef struct {
  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
  __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
} CoreDebug_Type;

/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U                                      /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U                                     /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U                                      /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U                                   /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U                                  /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */

#define CoreDebug_DHCSR_S_HALT_Pos 17U                                 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U                                   /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U                                       /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U                                      /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */

#define CoreDebug_DHCSR_C_STEP_Pos 2U                                  /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */

#define CoreDebug_DHCSR_C_HALT_Pos 1U                                  /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U                                         /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U                                 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */

#define CoreDebug_DCRSR_REGSEL_Pos 0U                                         /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */

/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U                                 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */

#define CoreDebug_DEMCR_MON_REQ_Pos 19U                                  /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */

#define CoreDebug_DEMCR_MON_STEP_Pos 18U                                   /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */

#define CoreDebug_DEMCR_MON_PEND_Pos 17U                                   /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */

#define CoreDebug_DEMCR_MON_EN_Pos 16U                                 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U                                     /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U                                     /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U                                     /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U                                      /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U                                     /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U                                      /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U                                    /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */

/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE       (0xE000E000UL)        /*!< System Control Space Base Address */
#define ITM_BASE       (0xE0000000UL)        /*!< ITM Base Address */
#define DWT_BASE       (0xE0001000UL)        /*!< DWT Base Address */
#define TPI_BASE       (0xE0040000UL)        /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL)        /*!< Core Debug Base Address */
#define SysTick_BASE   (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE      (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE       (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCnSCB    ((SCnSCB_Type *)SCS_BASE)          /*!< System control Register not in SCB */
#define SCB       ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct */
#define SysTick   ((SysTick_Type *)SysTick_BASE)     /*!< SysTick configuration struct */
#define NVIC      ((NVIC_Type *)NVIC_BASE)           /*!< NVIC configuration struct */
#define ITM       ((ITM_Type *)ITM_BASE)             /*!< ITM configuration struct */
#define DWT       ((DWT_Type *)DWT_BASE)             /*!< DWT configuration struct */
#define TPI       ((TPI_Type *)TPI_BASE)             /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

#if (__FPU_PRESENT == 1U)
#define FPU_BASE (SCS_BASE + 0x0F30UL)  /*!< Floating Point Unit */
#define FPU      ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Debug Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/**
  \brief   Set Priority Grouping
  \details Sets the priority grouping field using the required unlock sequence.
           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
           Only values from 0..7 are used.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */

  reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
  SCB->AIRCR = reg_value;
}

/**
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
  return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Active Interrupt
  \details Reads the active register in NVIC and returns the active bit.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not active.
  \return             1  Interrupt status is active.
 */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  } else {
    NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}

/**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                      buffered write are completed before reset */
  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
  __DSB();                                                                                                                         /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

/* ##################################### Debug In/Output function ########################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_core_DebugFunctions ITM Functions
  \brief    Functions that access the ITM debug interface.
  @{
 */

extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

/**
  \brief   ITM Send Character
  \details Transmits a character via the ITM channel 0, and
           \li Just returns when no debugger is connected that has booked the output.
           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  \param [in]     ch  Character to transmit.
  \returns            Character to transmit.
 */
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
      ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
  {
    while (ITM->PORT[0U].u32 == 0UL) {
      __NOP();
    }
    ITM->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}

/**
  \brief   ITM Receive Character
  \details Inputs a character via the external variable \ref ITM_RxBuffer.
  \return             Received character.
  \return         -1  No character pending.
 */
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
  int32_t ch = -1; /* no character available */

  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
    ch           = ITM_RxBuffer;
    ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
  }

  return (ch);
}

/**
  \brief   ITM Check Character
  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
  \return          0  No character available.
  \return          1  Character available.
 */
__STATIC_INLINE int32_t ITM_CheckChar(void) {

  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
    return (0); /* no character available */
  } else {
    return (1); /*    character available */
  }
}

/*@} end of CMSIS_core_DebugFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM4_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cm7.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cm7.h
                                                                              * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CM7_H_GENERIC
#define __CORE_CM7_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup Cortex_M7
  @{
 */

/*  CMSIS CM7 definitions */
#define __CM7_CMSIS_VERSION_MAIN (0x04U)                                                       /*!< [31:16] CMSIS HAL main version */
#define __CM7_CMSIS_VERSION_SUB  (0x1EU)                                                       /*!< [15:0]  CMSIS HAL sub version */
#define __CM7_CMSIS_VERSION      ((__CM7_CMSIS_VERSION_MAIN << 16U) | __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_M (0x07U) /*!< Cortex-M Core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1U
#else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#if (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmSimd.h"  /* Compiler specific SIMD Intrinsics */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM7_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_CM7_H_DEPENDANT
#define __CORE_CM7_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM7_REV
#define __CM7_REV 0x0000U
#warning "__CM7_REV not defined in device header file; using default!"
#endif

#ifndef __FPU_PRESENT
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __ICACHE_PRESENT
#define __ICACHE_PRESENT 0U
#warning "__ICACHE_PRESENT not defined in device header file; using default!"
#endif

#ifndef __DCACHE_PRESENT
#define __DCACHE_PRESENT 0U
#warning "__DCACHE_PRESENT not defined in device header file; using default!"
#endif

#ifndef __DTCM_PRESENT
#define __DTCM_PRESENT 0U
#warning "__DTCM_PRESENT        not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group Cortex_M7 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core Debug Register
  - Core MPU Register
  - Core FPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved */
    uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags */
    uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

#define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */

#define APSR_GE_Pos 16U                    /*!< APSR: GE Position */
#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;        /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 7; /*!< bit:  9..15  Reserved */
    uint32_t GE : 4;         /*!< bit: 16..19  Greater than or Equal flags */
    uint32_t _reserved1 : 4; /*!< bit: 20..23  Reserved */
    uint32_t T : 1;          /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t IT : 2;         /*!< bit: 25..26  saved IT state   (read 0) */
    uint32_t Q : 1;          /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;          /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;          /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;          /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;          /*!< bit:     31  Negative condition code flag */
  } b;                       /*!< Structure used for bit  access */
  uint32_t w;                /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_Q_Pos 27U                 /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */

#define xPSR_IT_Pos 25U                  /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_GE_Pos 16U                    /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag */
    uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_FPCA_Pos 2U                        /*!< CONTROL: FPCA Position */
#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */

#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[24U];
  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[24U];
  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[24U];
  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[24U];
  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
  uint32_t       RESERVED4[56U];
  __IOM uint8_t  IP[240U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
  uint32_t       RESERVED5[644U];
  __OM uint32_t  STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
} NVIC_Type;

/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U                                   /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID;       /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;        /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  __IOM uint32_t VTOR;        /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
  __IOM uint32_t AIRCR;       /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;         /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;         /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  __IOM uint8_t  SHPR[12U];   /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  __IOM uint32_t SHCSR;       /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
  __IOM uint32_t CFSR;        /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
  __IOM uint32_t HFSR;        /*!< Offset: 0x02C (R/W)  HardFault Status Register */
  __IOM uint32_t DFSR;        /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
  __IOM uint32_t MMFAR;       /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
  __IOM uint32_t BFAR;        /*!< Offset: 0x038 (R/W)  BusFault Address Register */
  __IOM uint32_t AFSR;        /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
  __IM uint32_t  ID_PFR[2U];  /*!< Offset: 0x040 (R/ )  Processor Feature Register */
  __IM uint32_t  ID_DFR;      /*!< Offset: 0x048 (R/ )  Debug Feature Register */
  __IM uint32_t  ID_AFR;      /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
  __IM uint32_t  ID_MFR[4U];  /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
  __IM uint32_t  ID_ISAR[5U]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
  uint32_t       RESERVED0[1U];
  __IM uint32_t  CLIDR;  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
  __IM uint32_t  CTR;    /*!< Offset: 0x07C (R/ )  Cache Type register */
  __IM uint32_t  CCSIDR; /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
  __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
  __IOM uint32_t CPACR;  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
  uint32_t       RESERVED3[93U];
  __OM uint32_t  STIR; /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
  uint32_t       RESERVED4[15U];
  __IM uint32_t  MVFR0; /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
  __IM uint32_t  MVFR1; /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
  __IM uint32_t  MVFR2; /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
  uint32_t       RESERVED5[1U];
  __OM uint32_t  ICIALLU; /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
  uint32_t       RESERVED6[1U];
  __OM uint32_t  ICIMVAU;  /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
  __OM uint32_t  DCIMVAC;  /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
  __OM uint32_t  DCISW;    /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
  __OM uint32_t  DCCMVAU;  /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
  __OM uint32_t  DCCMVAC;  /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
  __OM uint32_t  DCCSW;    /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
  __OM uint32_t  DCCIMVAC; /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
  __OM uint32_t  DCCISW;   /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
  uint32_t       RESERVED7[6U];
  __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
  __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
  __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W)  AHBP Control Register */
  __IOM uint32_t CACR;   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
  __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
  uint32_t       RESERVED8[1U];
  __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_RETTOBASE_Pos 11U                             /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U                              /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

#define SCB_AIRCR_VECTRESET_Pos 0U                                   /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_BP_Pos 18U                     /*!< SCB CCR: Branch prediction enable bit Position */
#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */

#define SCB_CCR_IC_Pos 17U                     /*!< SCB CCR: Instruction cache enable bit Position */
#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */

#define SCB_CCR_DC_Pos 16U                     /*!< SCB CCR: Cache enable bit Position */
#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */

#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_BFHFNMIGN_Pos 8U                             /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */

#define SCB_CCR_DIV_0_TRP_Pos 4U                             /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

#define SCB_CCR_USERSETMPEND_Pos 1U                                /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */

#define SCB_CCR_NONBASETHRDENA_Pos 0U                                      /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U                                /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */

#define SCB_SHCSR_BUSFAULTENA_Pos 17U                                /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */

#define SCB_SHCSR_MEMFAULTENA_Pos 16U                                /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */

#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U                                   /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U                                   /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U                                   /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */

#define SCB_SHCSR_SYSTICKACT_Pos 11U                               /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */

#define SCB_SHCSR_PENDSVACT_Pos 10U                              /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */

#define SCB_SHCSR_MONITORACT_Pos 8U                                /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */

#define SCB_SHCSR_SVCALLACT_Pos 7U                               /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */

#define SCB_SHCSR_USGFAULTACT_Pos 3U                                 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */

#define SCB_SHCSR_BUSFAULTACT_Pos 1U                                 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */

#define SCB_SHCSR_MEMFAULTACT_Pos 0U                                     /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */

/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U                                   /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */

#define SCB_CFSR_BUSFAULTSR_Pos 8U                                  /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */

#define SCB_CFSR_MEMFAULTSR_Pos 0U                                      /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U                            /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */

#define SCB_HFSR_FORCED_Pos 30U                          /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */

#define SCB_HFSR_VECTTBL_Pos 1U                            /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */

/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U                             /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */

#define SCB_DFSR_VCATCH_Pos 3U                           /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */

#define SCB_DFSR_DWTTRAP_Pos 2U                            /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */

#define SCB_DFSR_BKPT_Pos 1U                         /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */

#define SCB_DFSR_HALTED_Pos 0U                               /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */

/* SCB Cache Level ID Register Definitions */
#define SCB_CLIDR_LOUU_Pos 27U                         /*!< SCB CLIDR: LoUU Position */
#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */

#define SCB_CLIDR_LOC_Pos 24U                        /*!< SCB CLIDR: LoC Position */
#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */

/* SCB Cache Type Register Definitions */
#define SCB_CTR_FORMAT_Pos 29U                         /*!< SCB CTR: Format Position */
#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */

#define SCB_CTR_CWG_Pos 24U                        /*!< SCB CTR: CWG Position */
#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */

#define SCB_CTR_ERG_Pos 20U                        /*!< SCB CTR: ERG Position */
#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */

#define SCB_CTR_DMINLINE_Pos 16U                             /*!< SCB CTR: DminLine Position */
#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */

#define SCB_CTR_IMINLINE_Pos 0U                                  /*!< SCB CTR: ImInLine Position */
#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */

/* SCB Cache Size ID Register Definitions */
#define SCB_CCSIDR_WT_Pos 31U                        /*!< SCB CCSIDR: WT Position */
#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */

#define SCB_CCSIDR_WB_Pos 30U                        /*!< SCB CCSIDR: WB Position */
#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */

#define SCB_CCSIDR_RA_Pos 29U                        /*!< SCB CCSIDR: RA Position */
#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */

#define SCB_CCSIDR_WA_Pos 28U                        /*!< SCB CCSIDR: WA Position */
#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */

#define SCB_CCSIDR_NUMSETS_Pos 13U                                  /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U                                        /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */

#define SCB_CCSIDR_LINESIZE_Pos 0U                                   /*!< SCB CCSIDR: LineSize Position */
#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */

/* SCB Cache Size Selection Register Definitions */
#define SCB_CSSELR_LEVEL_Pos 1U                            /*!< SCB CSSELR: Level Position */
#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */

#define SCB_CSSELR_IND_Pos 0U                              /*!< SCB CSSELR: InD Position */
#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */

/* SCB Software Triggered Interrupt Register Definitions */
#define SCB_STIR_INTID_Pos 0U                                  /*!< SCB STIR: INTID Position */
#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */

/* SCB D-Cache Invalidate by Set-way Register Definitions */
#define SCB_DCISW_WAY_Pos 30U                        /*!< SCB DCISW: Way Position */
#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */

#define SCB_DCISW_SET_Pos 5U                             /*!< SCB DCISW: Set Position */
#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */

/* SCB D-Cache Clean by Set-way Register Definitions */
#define SCB_DCCSW_WAY_Pos 30U                        /*!< SCB DCCSW: Way Position */
#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */

#define SCB_DCCSW_SET_Pos 5U                             /*!< SCB DCCSW: Set Position */
#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */

/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
#define SCB_DCCISW_WAY_Pos 30U                         /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */

#define SCB_DCCISW_SET_Pos 5U                              /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */

/* Instruction Tightly-Coupled Memory Control Register Definitions */
#define SCB_ITCMCR_SZ_Pos 3U                           /*!< SCB ITCMCR: SZ Position */
#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */

#define SCB_ITCMCR_RETEN_Pos 2U                            /*!< SCB ITCMCR: RETEN Position */
#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */

#define SCB_ITCMCR_RMW_Pos 1U                          /*!< SCB ITCMCR: RMW Position */
#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */

#define SCB_ITCMCR_EN_Pos 0U                             /*!< SCB ITCMCR: EN Position */
#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */

/* Data Tightly-Coupled Memory Control Register Definitions */
#define SCB_DTCMCR_SZ_Pos 3U                           /*!< SCB DTCMCR: SZ Position */
#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */

#define SCB_DTCMCR_RETEN_Pos 2U                            /*!< SCB DTCMCR: RETEN Position */
#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */

#define SCB_DTCMCR_RMW_Pos 1U                          /*!< SCB DTCMCR: RMW Position */
#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */

#define SCB_DTCMCR_EN_Pos 0U                             /*!< SCB DTCMCR: EN Position */
#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */

/* AHBP Control Register Definitions */
#define SCB_AHBPCR_SZ_Pos 1U                         /*!< SCB AHBPCR: SZ Position */
#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */

#define SCB_AHBPCR_EN_Pos 0U                             /*!< SCB AHBPCR: EN Position */
#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */

/* L1 Cache Control Register Definitions */
#define SCB_CACR_FORCEWT_Pos 2U                            /*!< SCB CACR: FORCEWT Position */
#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */

#define SCB_CACR_ECCEN_Pos 1U                          /*!< SCB CACR: ECCEN Position */
#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */

#define SCB_CACR_SIWT_Pos 0U                             /*!< SCB CACR: SIWT Position */
#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */

/* AHBS Control Register Definitions */
#define SCB_AHBSCR_INITCOUNT_Pos 11U                                  /*!< SCB AHBSCR: INITCOUNT Position */
#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */

#define SCB_AHBSCR_TPRI_Pos 2U                               /*!< SCB AHBSCR: TPRI Position */
#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */

#define SCB_AHBSCR_CTL_Pos 0U                              /*!< SCB AHBSCR: CTL Position*/
#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */

/* Auxiliary Bus Fault Status Register Definitions */
#define SCB_ABFSR_AXIMTYPE_Pos 8U                              /*!< SCB ABFSR: AXIMTYPE Position*/
#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */

#define SCB_ABFSR_EPPB_Pos 4U                          /*!< SCB ABFSR: EPPB Position*/
#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */

#define SCB_ABFSR_AXIM_Pos 3U                          /*!< SCB ABFSR: AXIM Position*/
#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */

#define SCB_ABFSR_AHBP_Pos 2U                          /*!< SCB ABFSR: AHBP Position*/
#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */

#define SCB_ABFSR_DTCM_Pos 1U                          /*!< SCB ABFSR: DTCM Position*/
#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */

#define SCB_ABFSR_ITCM_Pos 0U                              /*!< SCB ABFSR: ITCM Position*/
#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */

/**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct {
  uint32_t       RESERVED0[1U];
  __IM uint32_t  ICTR;  /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
} SCnSCB_Type;

/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U                                         /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */

/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U                                      /*!< ACTLR: DISITMATBFLUSH Position */
#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */

#define SCnSCB_ACTLR_DISRAMODE_Pos 11U                                 /*!< ACTLR: DISRAMODE Position */
#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */

#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U                                 /*!< ACTLR: FPEXCODIS Position */
#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */

#define SCnSCB_ACTLR_DISFOLD_Pos 2U                                /*!< ACTLR: DISFOLD Position */
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */

/*@} end of group CMSIS_SCnotSCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
  @{
 */

/**
  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 */
typedef struct {
  __OM union {
    __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
    __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
    __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
  } PORT[32U];         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
  uint32_t       RESERVED0[864U];
  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
  uint32_t       RESERVED1[15U];
  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
  uint32_t       RESERVED2[15U];
  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
  uint32_t       RESERVED3[29U];
  __OM uint32_t  IWR;  /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
  __IM uint32_t  IRR;  /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
  uint32_t       RESERVED4[43U];
  __OM uint32_t  LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
  __IM uint32_t  LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
  uint32_t       RESERVED5[6U];
  __IM uint32_t  PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
  __IM uint32_t  PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
  __IM uint32_t  PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
  __IM uint32_t  PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
  __IM uint32_t  PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
  __IM uint32_t  PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
  __IM uint32_t  PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
  __IM uint32_t  PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
  __IM uint32_t  CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
  __IM uint32_t  CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
  __IM uint32_t  CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
  __IM uint32_t  CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
} ITM_Type;

/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U                                  /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */

/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U                       /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */

#define ITM_TCR_TraceBusID_Pos 16U                                /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */

#define ITM_TCR_GTSFREQ_Pos 10U                          /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */

#define ITM_TCR_TSPrescale_Pos 8U                              /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */

#define ITM_TCR_SWOENA_Pos 4U                          /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */

#define ITM_TCR_DWTENA_Pos 3U                          /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */

#define ITM_TCR_SYNCENA_Pos 2U                           /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */

#define ITM_TCR_TSENA_Pos 1U                         /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */

#define ITM_TCR_ITMENA_Pos 0U                              /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */

/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U                                /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */

/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U                                /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */

/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U                                    /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */

/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U                           /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */

#define ITM_LSR_Access_Pos 1U                          /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */

#define ITM_LSR_Present_Pos 0U                               /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */

/*@}*/ /* end of group CMSIS_ITM */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
  @{
 */

/**
  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct {
  __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
  __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
  __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
  __IOM uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
  __IOM uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register */
  __IOM uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register */
  __IOM uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
  __IM uint32_t  PCSR;      /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
  __IOM uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
  __IOM uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0 */
  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0 */
  uint32_t       RESERVED0[1U];
  __IOM uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
  __IOM uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1 */
  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1 */
  uint32_t       RESERVED1[1U];
  __IOM uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
  __IOM uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2 */
  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2 */
  uint32_t       RESERVED2[1U];
  __IOM uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
  __IOM uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3 */
  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3 */
  uint32_t       RESERVED3[981U];
  __OM uint32_t  LAR; /*!< Offset: 0xFB0 (  W)  Lock Access Register */
  __IM uint32_t  LSR; /*!< Offset: 0xFB4 (R  )  Lock Status Register */
} DWT_Type;

/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U                             /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */

#define DWT_CTRL_NOTRCPKT_Pos 27U                              /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */

#define DWT_CTRL_NOEXTTRIG_Pos 26U                               /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */

#define DWT_CTRL_NOCYCCNT_Pos 25U                              /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */

#define DWT_CTRL_NOPRFCNT_Pos 24U                              /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */

#define DWT_CTRL_CYCEVTENA_Pos 22U                               /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */

#define DWT_CTRL_FOLDEVTENA_Pos 21U                                /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */

#define DWT_CTRL_LSUEVTENA_Pos 20U                               /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */

#define DWT_CTRL_SLEEPEVTENA_Pos 19U                                 /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */

#define DWT_CTRL_EXCEVTENA_Pos 18U                               /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */

#define DWT_CTRL_CPIEVTENA_Pos 17U                               /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */

#define DWT_CTRL_EXCTRCENA_Pos 16U                               /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */

#define DWT_CTRL_PCSAMPLENA_Pos 12U                                /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */

#define DWT_CTRL_SYNCTAP_Pos 10U                             /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */

#define DWT_CTRL_CYCTAP_Pos 9U                             /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */

#define DWT_CTRL_POSTINIT_Pos 5U                               /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */

#define DWT_CTRL_POSTPRESET_Pos 1U                                 /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */

#define DWT_CTRL_CYCCNTENA_Pos 0U                                    /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */

/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U                                    /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */

/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U                                    /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */

/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U                                        /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */

/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U                                    /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */

/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U                                      /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */

/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U                                /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */

/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U                                 /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */

#define DWT_FUNCTION_DATAVADDR1_Pos 16U                                    /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */

#define DWT_FUNCTION_DATAVADDR0_Pos 12U                                    /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */

#define DWT_FUNCTION_DATAVSIZE_Pos 10U                                   /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */

#define DWT_FUNCTION_LNK1ENA_Pos 9U                                  /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */

#define DWT_FUNCTION_DATAVMATCH_Pos 8U                                     /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */

#define DWT_FUNCTION_CYCMATCH_Pos 7U                                   /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */

#define DWT_FUNCTION_EMITRANGE_Pos 5U                                    /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */

#define DWT_FUNCTION_FUNCTION_Pos 0U                                       /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */

/*@}*/ /* end of group CMSIS_DWT */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
  \brief    Type definitions for the Trace Port Interface (TPI)
  @{
 */

/**
  \brief  Structure type to access the Trace Port Interface Register (TPI).
 */
typedef struct {
  __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
  uint32_t       RESERVED0[2U];
  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
  uint32_t       RESERVED1[55U];
  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
  uint32_t       RESERVED2[131U];
  __IM uint32_t  FFSR; /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
  __IM uint32_t  FSCR; /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
  uint32_t       RESERVED3[759U];
  __IM uint32_t  TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
  __IM uint32_t  FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
  __IM uint32_t  ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
  uint32_t       RESERVED4[1U];
  __IM uint32_t  ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
  __IM uint32_t  FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
  __IOM uint32_t ITCTRL;    /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
  uint32_t       RESERVED5[39U];
  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
  uint32_t       RESERVED7[8U];
  __IM uint32_t  DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
  __IM uint32_t  DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
} TPI_Type;

/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U                                       /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */

/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U                                 /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */

/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U                                /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */

#define TPI_FFSR_TCPresent_Pos 2U                                /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */

#define TPI_FFSR_FtStopped_Pos 1U                                /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */

#define TPI_FFSR_FlInProg_Pos 0U                                   /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */

/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U                             /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */

#define TPI_FFCR_EnFCont_Pos 1U                              /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */

/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U                                     /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */

/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */

#define TPI_FIFO0_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */

#define TPI_FIFO0_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */

#define TPI_FIFO0_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */

#define TPI_FIFO0_ETM2_Pos 16U                            /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */

#define TPI_FIFO0_ETM1_Pos 8U                             /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */

#define TPI_FIFO0_ETM0_Pos 0U                                 /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */

/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */

/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */

#define TPI_FIFO1_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */

#define TPI_FIFO1_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */

#define TPI_FIFO1_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */

#define TPI_FIFO1_ITM2_Pos 16U                            /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */

#define TPI_FIFO1_ITM1_Pos 8U                             /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */

#define TPI_FIFO1_ITM0_Pos 0U                                 /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */

/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */

/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U                                 /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */

/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U                               /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */

#define TPI_DEVID_MANCVALID_Pos 10U                                /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */

#define TPI_DEVID_PTINVALID_Pos 9U                                 /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */

#define TPI_DEVID_MinBufSz_Pos 6U                                /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */

#define TPI_DEVID_AsynClkIn_Pos 5U                                 /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */

#define TPI_DEVID_NrTraceInput_Pos 0U                                         /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */

/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U                                   /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */

#define TPI_DEVTYPE_SubType_Pos 0U                                     /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */

/*@}*/ /* end of group CMSIS_TPI */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U                                 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

#if (__FPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
  \brief    Type definitions for the Floating Point Unit (FPU)
  @{
 */

/**
  \brief  Structure type to access the Floating Point Unit (FPU).
 */
typedef struct {
  uint32_t       RESERVED0[1U];
  __IOM uint32_t FPCCR;  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
  __IOM uint32_t FPCAR;  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
  __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
  __IM uint32_t  MVFR0;  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
  __IM uint32_t  MVFR1;  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
  __IM uint32_t  MVFR2;  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
} FPU_Type;

/* Floating-Point Context Control Register Definitions */
#define FPU_FPCCR_ASPEN_Pos 31U                          /*!< FPCCR: ASPEN bit Position */
#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */

#define FPU_FPCCR_LSPEN_Pos 30U                          /*!< FPCCR: LSPEN Position */
#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */

#define FPU_FPCCR_MONRDY_Pos 8U                            /*!< FPCCR: MONRDY Position */
#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */

#define FPU_FPCCR_BFRDY_Pos 6U                           /*!< FPCCR: BFRDY Position */
#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */

#define FPU_FPCCR_MMRDY_Pos 5U                           /*!< FPCCR: MMRDY Position */
#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */

#define FPU_FPCCR_HFRDY_Pos 4U                           /*!< FPCCR: HFRDY Position */
#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */

#define FPU_FPCCR_THREAD_Pos 3U                            /*!< FPCCR: processor mode bit Position */
#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */

#define FPU_FPCCR_USER_Pos 1U                          /*!< FPCCR: privilege level bit Position */
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */

#define FPU_FPCCR_LSPACT_Pos 0U                                /*!< FPCCR: Lazy state preservation active bit Position */
#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */

/* Floating-Point Context Address Register Definitions */
#define FPU_FPCAR_ADDRESS_Pos 3U                                      /*!< FPCAR: ADDRESS bit Position */
#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */

/* Floating-Point Default Status Control Register Definitions */
#define FPU_FPDSCR_AHP_Pos 26U                         /*!< FPDSCR: AHP bit Position */
#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */

#define FPU_FPDSCR_DN_Pos 25U                        /*!< FPDSCR: DN bit Position */
#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */

#define FPU_FPDSCR_FZ_Pos 24U                        /*!< FPDSCR: FZ bit Position */
#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */

#define FPU_FPDSCR_RMode_Pos 22U                           /*!< FPDSCR: RMode bit Position */
#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */

/* Media and FP Feature Register 0 Definitions */
#define FPU_MVFR0_FP_rounding_modes_Pos 28U                                        /*!< MVFR0: FP rounding modes bits Position */
#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */

#define FPU_MVFR0_Short_vectors_Pos 24U                                    /*!< MVFR0: Short vectors bits Position */
#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */

#define FPU_MVFR0_Square_root_Pos 20U                                  /*!< MVFR0: Square root bits Position */
#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */

#define FPU_MVFR0_Divide_Pos 16U                             /*!< MVFR0: Divide bits Position */
#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */

#define FPU_MVFR0_FP_excep_trapping_Pos 12U                                        /*!< MVFR0: FP exception trapping bits Position */
#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */

#define FPU_MVFR0_Double_precision_Pos 8U                                        /*!< MVFR0: Double-precision bits Position */
#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */

#define FPU_MVFR0_Single_precision_Pos 4U                                        /*!< MVFR0: Single-precision bits Position */
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */

#define FPU_MVFR0_A_SIMD_registers_Pos 0U                                            /*!< MVFR0: A_SIMD registers bits Position */
#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */

/* Media and FP Feature Register 1 Definitions */
#define FPU_MVFR1_FP_fused_MAC_Pos 28U                                   /*!< MVFR1: FP fused MAC bits Position */
#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */

#define FPU_MVFR1_FP_HPFP_Pos 24U                              /*!< MVFR1: FP HPFP bits Position */
#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */

#define FPU_MVFR1_D_NaN_mode_Pos 4U                                  /*!< MVFR1: D_NaN mode bits Position */
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */

#define FPU_MVFR1_FtZ_mode_Pos 0U                                    /*!< MVFR1: FtZ mode bits Position */
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */

/* Media and FP Feature Register 2 Definitions */

/*@} end of group CMSIS_FPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Type definitions for the Core Debug Registers
  @{
 */

/**
  \brief  Structure type to access the Core Debug Register (CoreDebug).
 */
typedef struct {
  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
  __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
} CoreDebug_Type;

/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U                                      /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U                                     /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U                                      /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U                                   /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U                                  /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */

#define CoreDebug_DHCSR_S_HALT_Pos 17U                                 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U                                   /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U                                       /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U                                      /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */

#define CoreDebug_DHCSR_C_STEP_Pos 2U                                  /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */

#define CoreDebug_DHCSR_C_HALT_Pos 1U                                  /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U                                         /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U                                 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */

#define CoreDebug_DCRSR_REGSEL_Pos 0U                                         /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */

/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U                                 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */

#define CoreDebug_DEMCR_MON_REQ_Pos 19U                                  /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */

#define CoreDebug_DEMCR_MON_STEP_Pos 18U                                   /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */

#define CoreDebug_DEMCR_MON_PEND_Pos 17U                                   /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */

#define CoreDebug_DEMCR_MON_EN_Pos 16U                                 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U                                     /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U                                     /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U                                     /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U                                      /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U                                     /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U                                      /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U                                    /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */

/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE       (0xE000E000UL)        /*!< System Control Space Base Address */
#define ITM_BASE       (0xE0000000UL)        /*!< ITM Base Address */
#define DWT_BASE       (0xE0001000UL)        /*!< DWT Base Address */
#define TPI_BASE       (0xE0040000UL)        /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL)        /*!< Core Debug Base Address */
#define SysTick_BASE   (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE      (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE       (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCnSCB    ((SCnSCB_Type *)SCS_BASE)          /*!< System control Register not in SCB */
#define SCB       ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct */
#define SysTick   ((SysTick_Type *)SysTick_BASE)     /*!< SysTick configuration struct */
#define NVIC      ((NVIC_Type *)NVIC_BASE)           /*!< NVIC configuration struct */
#define ITM       ((ITM_Type *)ITM_BASE)             /*!< ITM configuration struct */
#define DWT       ((DWT_Type *)DWT_BASE)             /*!< DWT configuration struct */
#define TPI       ((TPI_Type *)TPI_BASE)             /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

#if (__FPU_PRESENT == 1U)
#define FPU_BASE (SCS_BASE + 0x0F30UL)  /*!< Floating Point Unit */
#define FPU      ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Debug Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/**
  \brief   Set Priority Grouping
  \details Sets the priority grouping field using the required unlock sequence.
           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
           Only values from 0..7 are used.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */

  reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
  SCB->AIRCR = reg_value;
}

/**
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
  return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Active Interrupt
  \details Reads the active register in NVIC and returns the active bit.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not active.
  \return             1  Interrupt status is active.
 */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  } else {
    NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}

/**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                      buffered write are completed before reset */
  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
  __DSB();                                                                                                                         /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##########################  FPU functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_FpuFunctions FPU Functions
  \brief    Function that provides FPU type.
  @{
 */

/**
  \brief   get FPU type
  \details returns the FPU type
  \returns
   - \b  0: No FPU
   - \b  1: Single precision FPU
   - \b  2: Double + Single precision FPU
 */
__STATIC_INLINE uint32_t SCB_GetFPUType(void) {
  uint32_t mvfr0;

  mvfr0 = SCB->MVFR0;
  if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
    return 2UL; /* Double + Single precision FPU */
  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
    return 1UL; /* Single precision FPU */
  } else {
    return 0UL; /* No FPU */
  }
}

/*@} end of CMSIS_Core_FpuFunctions */

/* ##########################  Cache functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_CacheFunctions Cache Functions
  \brief    Functions that configure Instruction and Data cache.
  @{
 */

/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)

/**
  \brief   Enable I-Cache
  \details Turns on I-Cache
  */
__STATIC_INLINE void SCB_EnableICache(void) {
#if (__ICACHE_PRESENT == 1U)
  __DSB();
  __ISB();
  SCB->ICIALLU = 0UL;                   /* invalidate I-Cache */
  SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
  __DSB();
  __ISB();
#endif
}

/**
  \brief   Disable I-Cache
  \details Turns off I-Cache
  */
__STATIC_INLINE void SCB_DisableICache(void) {
#if (__ICACHE_PRESENT == 1U)
  __DSB();
  __ISB();
  SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
  SCB->ICIALLU = 0UL;                    /* invalidate I-Cache */
  __DSB();
  __ISB();
#endif
}

/**
  \brief   Invalidate I-Cache
  \details Invalidates I-Cache
  */
__STATIC_INLINE void SCB_InvalidateICache(void) {
#if (__ICACHE_PRESENT == 1U)
  __DSB();
  __ISB();
  SCB->ICIALLU = 0UL;
  __DSB();
  __ISB();
#endif
}

/**
  \brief   Enable D-Cache
  \details Turns on D-Cache
  */
__STATIC_INLINE void SCB_EnableDCache(void) {
#if (__DCACHE_PRESENT == 1U)
  uint32_t ccsidr;
  uint32_t sets;
  uint32_t ways;

  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
  __DSB();

  ccsidr = SCB->CCSIDR;

  /* invalidate D-Cache */
  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  do {
    ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
    do {
      SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
#if defined(__CC_ARM)
      __schedule_barrier();
#endif
    } while (ways--);
  } while (sets--);
  __DSB();

  SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */

  __DSB();
  __ISB();
#endif
}

/**
  \brief   Disable D-Cache
  \details Turns off D-Cache
  */
__STATIC_INLINE void SCB_DisableDCache(void) {
#if (__DCACHE_PRESENT == 1U)
  uint32_t ccsidr;
  uint32_t sets;
  uint32_t ways;

  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
  __DSB();

  ccsidr = SCB->CCSIDR;

  SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */

  /* clean & invalidate D-Cache */
  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  do {
    ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
    do {
      SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
#if defined(__CC_ARM)
      __schedule_barrier();
#endif
    } while (ways--);
  } while (sets--);

  __DSB();
  __ISB();
#endif
}

/**
  \brief   Invalidate D-Cache
  \details Invalidates D-Cache
  */
__STATIC_INLINE void SCB_InvalidateDCache(void) {
#if (__DCACHE_PRESENT == 1U)
  uint32_t ccsidr;
  uint32_t sets;
  uint32_t ways;

  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
  __DSB();

  ccsidr = SCB->CCSIDR;

  /* invalidate D-Cache */
  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  do {
    ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
    do {
      SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk));
#if defined(__CC_ARM)
      __schedule_barrier();
#endif
    } while (ways--);
  } while (sets--);

  __DSB();
  __ISB();
#endif
}

/**
  \brief   Clean D-Cache
  \details Cleans D-Cache
  */
__STATIC_INLINE void SCB_CleanDCache(void) {
#if (__DCACHE_PRESENT == 1U)
  uint32_t ccsidr;
  uint32_t sets;
  uint32_t ways;

  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
  __DSB();

  ccsidr = SCB->CCSIDR;

  /* clean D-Cache */
  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  do {
    ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
    do {
      SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk));
#if defined(__CC_ARM)
      __schedule_barrier();
#endif
    } while (ways--);
  } while (sets--);

  __DSB();
  __ISB();
#endif
}

/**
  \brief   Clean & Invalidate D-Cache
  \details Cleans and Invalidates D-Cache
  */
__STATIC_INLINE void SCB_CleanInvalidateDCache(void) {
#if (__DCACHE_PRESENT == 1U)
  uint32_t ccsidr;
  uint32_t sets;
  uint32_t ways;

  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
  __DSB();

  ccsidr = SCB->CCSIDR;

  /* clean & invalidate D-Cache */
  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
  do {
    ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
    do {
      SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk));
#if defined(__CC_ARM)
      __schedule_barrier();
#endif
    } while (ways--);
  } while (sets--);

  __DSB();
  __ISB();
#endif
}

/**
  \brief   D-Cache Invalidate by address
  \details Invalidates D-Cache for the given address
  \param[in]   addr    address (aligned to 32-byte boundary)
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
#if (__DCACHE_PRESENT == 1U)
  int32_t  op_size  = dsize;
  uint32_t op_addr  = (uint32_t)addr;
  int32_t  linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

  __DSB();

  while (op_size > 0) {
    SCB->DCIMVAC = op_addr;
    op_addr += linesize;
    op_size -= linesize;
  }

  __DSB();
  __ISB();
#endif
}

/**
  \brief   D-Cache Clean by address
  \details Cleans D-Cache for the given address
  \param[in]   addr    address (aligned to 32-byte boundary)
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) {
#if (__DCACHE_PRESENT == 1)
  int32_t  op_size  = dsize;
  uint32_t op_addr  = (uint32_t)addr;
  int32_t  linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

  __DSB();

  while (op_size > 0) {
    SCB->DCCMVAC = op_addr;
    op_addr += linesize;
    op_size -= linesize;
  }

  __DSB();
  __ISB();
#endif
}

/**
  \brief   D-Cache Clean and Invalidate by address
  \details Cleans and invalidates D_Cache for the given address
  \param[in]   addr    address (aligned to 32-byte boundary)
  \param[in]   dsize   size of memory block (in number of bytes)
*/
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) {
#if (__DCACHE_PRESENT == 1U)
  int32_t  op_size  = dsize;
  uint32_t op_addr  = (uint32_t)addr;
  int32_t  linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */

  __DSB();

  while (op_size > 0) {
    SCB->DCCIMVAC = op_addr;
    op_addr += linesize;
    op_size -= linesize;
  }

  __DSB();
  __ISB();
#endif
}

/*@} end of CMSIS_Core_CacheFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

/* ##################################### Debug In/Output function ########################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_core_DebugFunctions ITM Functions
  \brief    Functions that access the ITM debug interface.
  @{
 */

extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

/**
  \brief   ITM Send Character
  \details Transmits a character via the ITM channel 0, and
           \li Just returns when no debugger is connected that has booked the output.
           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  \param [in]     ch  Character to transmit.
  \returns            Character to transmit.
 */
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
      ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
  {
    while (ITM->PORT[0U].u32 == 0UL) {
      __NOP();
    }
    ITM->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}

/**
  \brief   ITM Receive Character
  \details Inputs a character via the external variable \ref ITM_RxBuffer.
  \return             Received character.
  \return         -1  No character pending.
 */
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
  int32_t ch = -1; /* no character available */

  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
    ch           = ITM_RxBuffer;
    ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
  }

  return (ch);
}

/**
  \brief   ITM Check Character
  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
  \return          0  No character available.
  \return          1  Character available.
 */
__STATIC_INLINE int32_t ITM_CheckChar(void) {

  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
    return (0); /* no character available */
  } else {
    return (1); /*    character available */
  }
}

/*@} end of CMSIS_core_DebugFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CM7_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cmFunc.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cmFunc.h
                                                                              * @brief    CMSIS Cortex-M Core Function Access Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H

/* ###########################  Core Function Access  ########################### */
/** \ingroup  CMSIS_Core_FunctionInterface
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  @{
*/

/*------------------ RealView Compiler -----------------*/
#if defined(__CC_ARM)
#include "cmsis_armcc.h"

/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"

/*------------------ GNU Compiler ----------------------*/
#elif defined(__GNUC__)
#include "cmsis_gcc.h"

/*------------------ ICC Compiler ----------------------*/
#elif defined(__ICCARM__)
#include 

/*------------------ TI CCS Compiler -------------------*/
#elif defined(__TMS470__)
#include 

/*------------------ TASKING Compiler ------------------*/
#elif defined(__TASKING__)
/*
 * The CMSIS functions have been implemented as intrinsics in the compiler.
 * Please use "carm -?i" to get an up to date list of all intrinsics,
 * Including the CMSIS ones.
 */

/*------------------ COSMIC Compiler -------------------*/
#elif defined(__CSMC__)
#include 

#endif

/*@} end of CMSIS_Core_RegAccFunctions */

#endif /* __CORE_CMFUNC_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cmInstr.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cmInstr.h
                                                                              * @brief    CMSIS Cortex-M Core Instruction Access Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H

/* ##########################  Core Instruction Access  ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  Access to dedicated instructions
  @{
*/

/*------------------ RealView Compiler -----------------*/
#if defined(__CC_ARM)
#include "cmsis_armcc.h"

/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"

/*------------------ GNU Compiler ----------------------*/
#elif defined(__GNUC__)
#include "cmsis_gcc.h"

/*------------------ ICC Compiler ----------------------*/
#elif defined(__ICCARM__)
#include 

/*------------------ TI CCS Compiler -------------------*/
#elif defined(__TMS470__)
#include 

/*------------------ TASKING Compiler ------------------*/
#elif defined(__TASKING__)
/*
 * The CMSIS functions have been implemented as intrinsics in the compiler.
 * Please use "carm -?i" to get an up to date list of all intrinsics,
 * Including the CMSIS ones.
 */

/*------------------ COSMIC Compiler -------------------*/
#elif defined(__CSMC__)
#include 

#endif

/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

#endif /* __CORE_CMINSTR_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_cmSimd.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_cmSimd.h
                                                                              * @brief    CMSIS Cortex-M SIMD Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H

#ifdef __cplusplus
extern "C" {
#endif

/* ###################  Compiler specific Intrinsics  ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  Access to dedicated SIMD instructions
  @{
*/

/*------------------ RealView Compiler -----------------*/
#if defined(__CC_ARM)
#include "cmsis_armcc.h"

/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"

/*------------------ GNU Compiler ----------------------*/
#elif defined(__GNUC__)
#include "cmsis_gcc.h"

/*------------------ ICC Compiler ----------------------*/
#elif defined(__ICCARM__)
#include 

/*------------------ TI CCS Compiler -------------------*/
#elif defined(__TMS470__)
#include 

/*------------------ TASKING Compiler ------------------*/
#elif defined(__TASKING__)
/*
 * The CMSIS functions have been implemented as intrinsics in the compiler.
 * Please use "carm -?i" to get an up to date list of all intrinsics,
 * Including the CMSIS ones.
 */

/*------------------ COSMIC Compiler -------------------*/
#elif defined(__CSMC__)
#include 

#endif

/*@} end of group CMSIS_SIMD_intrinsics */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_CMSIMD_H */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_sc000.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_sc000.h
                                                                              * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup SC000
  @{
 */

/*  CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U)                                                           /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB  (0x1EU)                                                           /*!< [15:0]  CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION      ((__SC000_CMSIS_VERSION_MAIN << 16U) | __SC000_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_SC (000U) /*!< Cortex secure core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
*/
#define __FPU_USED 0U

#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_SC000_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group SC000 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core MPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 28; /*!< bit:  0..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t _reserved1 : 3;  /*!< bit: 25..27  Reserved */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 1;  /*!< bit:      0  Reserved */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[31U];
  __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[31U];
  __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[31U];
  __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[31U];
  uint32_t       RESERVED4[64U];
  __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
} NVIC_Type;

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;  /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  __IOM uint32_t VTOR;  /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  uint32_t       RESERVED0[1U];
  __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
  __IOM uint32_t SHCSR;   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
  uint32_t       RESERVED1[154U];
  __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W)  Security Features Control Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U                                   /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */

/**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct {
  uint32_t       RESERVED0[2U];
  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
} SCnSCB_Type;

/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U                                       /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */

/*@} end of group CMSIS_SCnotSCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE; /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;  /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U                                /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
            Therefore they are not covered by the SC000 header file.
  @{
 */
/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of SC000 Hardware */
#define SCS_BASE     (0xE000E000UL)        /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE    (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE     (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCnSCB  ((SCnSCB_Type *)SCS_BASE)      /*!< System control Register not in SCB */
#define SCB     ((SCB_Type *)SCB_BASE)         /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC    ((NVIC_Type *)NVIC_BASE)       /*!< NVIC configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn)   ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
#define _IP_IDX(IRQn)    ((((uint32_t)(int32_t)(IRQn)) >> 2UL))

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  } else {
    NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB(); /* Ensure all outstanding memory accesses included
              buffered write are completed before reset */
  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
  __DSB(); /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_SC000_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/CMSIS/Include/core_sc300.h
================================================
/**************************************************************************/ /**
                                                                              * @file     core_sc300.h
                                                                              * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
                                                                              * @version  V4.30
                                                                              * @date     20. October 2015
                                                                              ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef __CORE_SC300_H_GENERIC
#define __CORE_SC300_H_GENERIC

#include 

#ifdef __cplusplus
extern "C" {
#endif

/**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:

   \li Required Rule 8.5, object/function definition in header file.

     Function definitions in header files are used to allow 'inlining'.

   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

     Unions are used for effective representation of core registers.

   \li Advisory Rule 19.7, Function-like macro defined.

     Function-like macros are used to allow more efficient code.
 */

/*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
/**
  \ingroup SC3000
  @{
 */

/*  CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x04U)                                                           /*!< [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB  (0x1EU)                                                           /*!< [15:0]  CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION      ((__SC300_CMSIS_VERSION_MAIN << 16U) | __SC300_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */

#define __CORTEX_SC (300U) /*!< Cortex secure core */

#if defined(__CC_ARM)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM           __asm    /*!< asm keyword for ARM Compiler */
#define __INLINE        __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline

#elif defined(__GNUC__)
#define __ASM           __asm  /*!< asm keyword for GNU Compiler */
#define __INLINE        inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline

#elif defined(__ICCARM__)
#define __ASM           __asm  /*!< asm keyword for IAR Compiler */
#define __INLINE        inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline

#elif defined(__TMS470__)
#define __ASM           __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline

#elif defined(__TASKING__)
#define __ASM           __asm  /*!< asm keyword for TASKING Compiler */
#define __INLINE        inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline

#elif defined(__CSMC__)
#define __packed
#define __ASM           _asm   /*!< asm keyword for COSMIC Compiler */
#define __INLINE        inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline

#else
#error Unknown compiler
#endif

/** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
*/
#define __FPU_USED 0U

#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__ICCARM__)
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TMS470__)
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#elif defined(__CSMC__)
#if (__CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif

#endif

#include "core_cmFunc.h"  /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_SC300_H_GENERIC */

#ifndef __CMSIS_GENERIC

#ifndef __CORE_SC300_H_DEPENDANT
#define __CORE_SC300_H_DEPENDANT

#ifdef __cplusplus
extern "C" {
#endif

/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC300_REV
#define __SC300_REV 0x0000U
#warning "__SC300_REV not defined in device header file; using default!"
#endif

#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif

#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif

#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif

/* IO definitions (access restrictions to peripheral registers) */
/**
    \defgroup CMSIS_glob_defs CMSIS Global Defines

    IO Type Qualifiers are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O  volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */

/* following defines should be used for structure members */
#define __IM  volatile const /*! Defines 'read only' structure member permissions */
#define __OM  volatile       /*! Defines 'write only' structure member permissions */
#define __IOM volatile       /*! Defines 'read / write' structure member permissions */

/*@} end of group SC300 */

/*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
  - Core Debug Register
  - Core MPU Register
 ******************************************************************************/
/**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
*/

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */

/**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union {
  struct {
    uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} APSR_Type;

/* APSR Register Definitions */
#define APSR_N_Pos 31U                 /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */

#define APSR_Z_Pos 30U                 /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */

#define APSR_C_Pos 29U                 /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */

#define APSR_V_Pos 28U                 /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */

#define APSR_Q_Pos 27U                 /*!< APSR: Q Position */
#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */

/**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} IPSR_Type;

/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U                            /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */

/**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union {
  struct {
    uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved */
    uint32_t T : 1;           /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t IT : 2;          /*!< bit: 25..26  saved IT state   (read 0) */
    uint32_t Q : 1;           /*!< bit:     27  Saturation condition flag */
    uint32_t V : 1;           /*!< bit:     28  Overflow condition code flag */
    uint32_t C : 1;           /*!< bit:     29  Carry condition code flag */
    uint32_t Z : 1;           /*!< bit:     30  Zero condition code flag */
    uint32_t N : 1;           /*!< bit:     31  Negative condition code flag */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} xPSR_Type;

/* xPSR Register Definitions */
#define xPSR_N_Pos 31U                 /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */

#define xPSR_Z_Pos 30U                 /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */

#define xPSR_C_Pos 29U                 /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */

#define xPSR_V_Pos 28U                 /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */

#define xPSR_Q_Pos 27U                 /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */

#define xPSR_IT_Pos 25U                  /*!< xPSR: IT Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */

#define xPSR_T_Pos 24U                 /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */

#define xPSR_ISR_Pos 0U                            /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */

/**
  \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union {
  struct {
    uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
    uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used */
    uint32_t _reserved1 : 30; /*!< bit:  2..31  Reserved */
  } b;                        /*!< Structure used for bit  access */
  uint32_t w;                 /*!< Type      used for word access */
} CONTROL_Type;

/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U                         /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */

#define CONTROL_nPRIV_Pos 0U                             /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

/*@} end of group CMSIS_CORE */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */

/**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct {
  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
  uint32_t       RESERVED0[24U];
  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
  uint32_t       RSERVED1[24U];
  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
  uint32_t       RESERVED2[24U];
  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
  uint32_t       RESERVED3[24U];
  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
  uint32_t       RESERVED4[56U];
  __IOM uint8_t  IP[240U]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
  uint32_t       RESERVED5[644U];
  __OM uint32_t  STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
} NVIC_Type;

/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0U                                   /*!< STIR: INTLINESNUM Position */
#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */

/*@} end of group CMSIS_NVIC */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */

/**
  \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct {
  __IM uint32_t  CPUID;    /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;     /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
  __IOM uint32_t VTOR;     /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
  __IOM uint32_t AIRCR;    /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;      /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;      /*!< Offset: 0x014 (R/W)  Configuration Control Register */
  __IOM uint8_t  SHP[12U]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  __IOM uint32_t SHCSR;    /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
  __IOM uint32_t CFSR;     /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
  __IOM uint32_t HFSR;     /*!< Offset: 0x02C (R/W)  HardFault Status Register */
  __IOM uint32_t DFSR;     /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
  __IOM uint32_t MMFAR;    /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
  __IOM uint32_t BFAR;     /*!< Offset: 0x038 (R/W)  BusFault Address Register */
  __IOM uint32_t AFSR;     /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
  __IM uint32_t  PFR[2U];  /*!< Offset: 0x040 (R/ )  Processor Feature Register */
  __IM uint32_t  DFR;      /*!< Offset: 0x048 (R/ )  Debug Feature Register */
  __IM uint32_t  ADR;      /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
  __IM uint32_t  MMFR[4U]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
  __IM uint32_t  ISAR[5U]; /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
  uint32_t       RESERVED0[5U];
  __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
  uint32_t       RESERVED1[129U];
  __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W)  Security Features Control Register */
} SCB_Type;

/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U                                   /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */

#define SCB_CPUID_VARIANT_Pos 20U                              /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */

#define SCB_CPUID_ARCHITECTURE_Pos 16U                                   /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */

#define SCB_CPUID_PARTNO_Pos 4U                                /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */

#define SCB_CPUID_REVISION_Pos 0U                                    /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */

/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U                              /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */

#define SCB_ICSR_PENDSVSET_Pos 28U                             /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */

#define SCB_ICSR_PENDSVCLR_Pos 27U                             /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */

#define SCB_ICSR_PENDSTSET_Pos 26U                             /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */

#define SCB_ICSR_PENDSTCLR_Pos 25U                             /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */

#define SCB_ICSR_ISRPREEMPT_Pos 23U                              /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */

#define SCB_ICSR_ISRPENDING_Pos 22U                              /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */

#define SCB_ICSR_VECTPENDING_Pos 12U                                   /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */

#define SCB_ICSR_RETTOBASE_Pos 11U                             /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */

#define SCB_ICSR_VECTACTIVE_Pos 0U                                       /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */

/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29U                           /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */

#define SCB_VTOR_TBLOFF_Pos 7U                                  /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */

/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U                                 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U                                     /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */

#define SCB_AIRCR_ENDIANESS_Pos 15U                              /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */

#define SCB_AIRCR_PRIGROUP_Pos 8U                              /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */

#define SCB_AIRCR_SYSRESETREQ_Pos 2U                                 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U                                   /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */

#define SCB_AIRCR_VECTRESET_Pos 0U                                   /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */

/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U                             /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */

#define SCB_SCR_SLEEPDEEP_Pos 2U                             /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */

#define SCB_SCR_SLEEPONEXIT_Pos 1U                               /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */

/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U                            /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */

#define SCB_CCR_BFHFNMIGN_Pos 8U                             /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */

#define SCB_CCR_DIV_0_TRP_Pos 4U                             /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */

#define SCB_CCR_UNALIGN_TRP_Pos 3U                               /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */

#define SCB_CCR_USERSETMPEND_Pos 1U                                /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */

#define SCB_CCR_NONBASETHRDENA_Pos 0U                                      /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */

/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18U                                /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */

#define SCB_SHCSR_BUSFAULTENA_Pos 17U                                /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */

#define SCB_SHCSR_MEMFAULTENA_Pos 16U                                /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */

#define SCB_SHCSR_SVCALLPENDED_Pos 15U                                 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U                                   /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U                                   /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U                                   /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */

#define SCB_SHCSR_SYSTICKACT_Pos 11U                               /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */

#define SCB_SHCSR_PENDSVACT_Pos 10U                              /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */

#define SCB_SHCSR_MONITORACT_Pos 8U                                /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */

#define SCB_SHCSR_SVCALLACT_Pos 7U                               /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */

#define SCB_SHCSR_USGFAULTACT_Pos 3U                                 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */

#define SCB_SHCSR_BUSFAULTACT_Pos 1U                                 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */

#define SCB_SHCSR_MEMFAULTACT_Pos 0U                                     /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */

/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U                                   /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */

#define SCB_CFSR_BUSFAULTSR_Pos 8U                                  /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */

#define SCB_CFSR_MEMFAULTSR_Pos 0U                                      /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

/* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U                            /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */

#define SCB_HFSR_FORCED_Pos 30U                          /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */

#define SCB_HFSR_VECTTBL_Pos 1U                            /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */

/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4U                             /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */

#define SCB_DFSR_VCATCH_Pos 3U                           /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */

#define SCB_DFSR_DWTTRAP_Pos 2U                            /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */

#define SCB_DFSR_BKPT_Pos 1U                         /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */

#define SCB_DFSR_HALTED_Pos 0U                               /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */

/*@} end of group CMSIS_SCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */

/**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct {
  uint32_t      RESERVED0[1U];
  __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
  uint32_t      RESERVED1[1U];
} SCnSCB_Type;

/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U                                         /*!< ICTR: INTLINESNUM Position */
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */

/*@} end of group CMSIS_SCnotSCB */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */

/**
  \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct {
  __IOM uint32_t CTRL;  /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;  /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;   /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM uint32_t  CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U                                 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */

#define SysTick_CTRL_CLKSOURCE_Pos 2U                                  /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */

#define SysTick_CTRL_TICKINT_Pos 1U                                /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */

#define SysTick_CTRL_ENABLE_Pos 0U                                   /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */

/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U                                          /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */

/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U                                          /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */

/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U                              /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */

#define SysTick_CALIB_SKEW_Pos 30U                             /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */

#define SysTick_CALIB_TENMS_Pos 0U                                          /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */

/*@} end of group CMSIS_SysTick */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
  @{
 */

/**
  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 */
typedef struct {
  __OM union {
    __OM uint8_t  u8;  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
    __OM uint16_t u16; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
    __OM uint32_t u32; /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
  } PORT[32U];         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
  uint32_t       RESERVED0[864U];
  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
  uint32_t       RESERVED1[15U];
  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
  uint32_t       RESERVED2[15U];
  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
  uint32_t       RESERVED3[29U];
  __OM uint32_t  IWR;  /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
  __IM uint32_t  IRR;  /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
  uint32_t       RESERVED4[43U];
  __OM uint32_t  LAR; /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
  __IM uint32_t  LSR; /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
  uint32_t       RESERVED5[6U];
  __IM uint32_t  PID4; /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
  __IM uint32_t  PID5; /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
  __IM uint32_t  PID6; /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
  __IM uint32_t  PID7; /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
  __IM uint32_t  PID0; /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
  __IM uint32_t  PID1; /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
  __IM uint32_t  PID2; /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
  __IM uint32_t  PID3; /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
  __IM uint32_t  CID0; /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
  __IM uint32_t  CID1; /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
  __IM uint32_t  CID2; /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
  __IM uint32_t  CID3; /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
} ITM_Type;

/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U                                  /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */

/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U                       /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */

#define ITM_TCR_TraceBusID_Pos 16U                                /*!< ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */

#define ITM_TCR_GTSFREQ_Pos 10U                          /*!< ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */

#define ITM_TCR_TSPrescale_Pos 8U                              /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */

#define ITM_TCR_SWOENA_Pos 4U                          /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */

#define ITM_TCR_DWTENA_Pos 3U                          /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */

#define ITM_TCR_SYNCENA_Pos 2U                           /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */

#define ITM_TCR_TSENA_Pos 1U                         /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */

#define ITM_TCR_ITMENA_Pos 0U                              /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */

/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0U                                /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */

/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0U                                /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */

/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0U                                    /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */

/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2U                           /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */

#define ITM_LSR_Access_Pos 1U                          /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */

#define ITM_LSR_Present_Pos 0U                               /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */

/*@}*/ /* end of group CMSIS_ITM */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
  @{
 */

/**
  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct {
  __IOM uint32_t CTRL;      /*!< Offset: 0x000 (R/W)  Control Register */
  __IOM uint32_t CYCCNT;    /*!< Offset: 0x004 (R/W)  Cycle Count Register */
  __IOM uint32_t CPICNT;    /*!< Offset: 0x008 (R/W)  CPI Count Register */
  __IOM uint32_t EXCCNT;    /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
  __IOM uint32_t SLEEPCNT;  /*!< Offset: 0x010 (R/W)  Sleep Count Register */
  __IOM uint32_t LSUCNT;    /*!< Offset: 0x014 (R/W)  LSU Count Register */
  __IOM uint32_t FOLDCNT;   /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
  __IM uint32_t  PCSR;      /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
  __IOM uint32_t COMP0;     /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
  __IOM uint32_t MASK0;     /*!< Offset: 0x024 (R/W)  Mask Register 0 */
  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W)  Function Register 0 */
  uint32_t       RESERVED0[1U];
  __IOM uint32_t COMP1;     /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
  __IOM uint32_t MASK1;     /*!< Offset: 0x034 (R/W)  Mask Register 1 */
  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W)  Function Register 1 */
  uint32_t       RESERVED1[1U];
  __IOM uint32_t COMP2;     /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
  __IOM uint32_t MASK2;     /*!< Offset: 0x044 (R/W)  Mask Register 2 */
  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W)  Function Register 2 */
  uint32_t       RESERVED2[1U];
  __IOM uint32_t COMP3;     /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
  __IOM uint32_t MASK3;     /*!< Offset: 0x054 (R/W)  Mask Register 3 */
  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W)  Function Register 3 */
} DWT_Type;

/* DWT Control Register Definitions */
#define DWT_CTRL_NUMCOMP_Pos 28U                             /*!< DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */

#define DWT_CTRL_NOTRCPKT_Pos 27U                              /*!< DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */

#define DWT_CTRL_NOEXTTRIG_Pos 26U                               /*!< DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */

#define DWT_CTRL_NOCYCCNT_Pos 25U                              /*!< DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */

#define DWT_CTRL_NOPRFCNT_Pos 24U                              /*!< DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */

#define DWT_CTRL_CYCEVTENA_Pos 22U                               /*!< DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */

#define DWT_CTRL_FOLDEVTENA_Pos 21U                                /*!< DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */

#define DWT_CTRL_LSUEVTENA_Pos 20U                               /*!< DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */

#define DWT_CTRL_SLEEPEVTENA_Pos 19U                                 /*!< DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */

#define DWT_CTRL_EXCEVTENA_Pos 18U                               /*!< DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */

#define DWT_CTRL_CPIEVTENA_Pos 17U                               /*!< DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */

#define DWT_CTRL_EXCTRCENA_Pos 16U                               /*!< DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */

#define DWT_CTRL_PCSAMPLENA_Pos 12U                                /*!< DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */

#define DWT_CTRL_SYNCTAP_Pos 10U                             /*!< DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */

#define DWT_CTRL_CYCTAP_Pos 9U                             /*!< DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */

#define DWT_CTRL_POSTINIT_Pos 5U                               /*!< DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */

#define DWT_CTRL_POSTPRESET_Pos 1U                                 /*!< DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */

#define DWT_CTRL_CYCCNTENA_Pos 0U                                    /*!< DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */

/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0U                                    /*!< DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */

/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0U                                    /*!< DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */

/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U                                        /*!< DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */

/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0U                                    /*!< DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */

/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0U                                      /*!< DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */

/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0U                                /*!< DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */

/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24U                                 /*!< DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */

#define DWT_FUNCTION_DATAVADDR1_Pos 16U                                    /*!< DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */

#define DWT_FUNCTION_DATAVADDR0_Pos 12U                                    /*!< DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */

#define DWT_FUNCTION_DATAVSIZE_Pos 10U                                   /*!< DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */

#define DWT_FUNCTION_LNK1ENA_Pos 9U                                  /*!< DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */

#define DWT_FUNCTION_DATAVMATCH_Pos 8U                                     /*!< DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */

#define DWT_FUNCTION_CYCMATCH_Pos 7U                                   /*!< DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */

#define DWT_FUNCTION_EMITRANGE_Pos 5U                                    /*!< DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */

#define DWT_FUNCTION_FUNCTION_Pos 0U                                       /*!< DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */

/*@}*/ /* end of group CMSIS_DWT */

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
  \brief    Type definitions for the Trace Port Interface (TPI)
  @{
 */

/**
  \brief  Structure type to access the Trace Port Interface Register (TPI).
 */
typedef struct {
  __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
  uint32_t       RESERVED0[2U];
  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
  uint32_t       RESERVED1[55U];
  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
  uint32_t       RESERVED2[131U];
  __IM uint32_t  FFSR; /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
  __IM uint32_t  FSCR; /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
  uint32_t       RESERVED3[759U];
  __IM uint32_t  TRIGGER;   /*!< Offset: 0xEE8 (R/ )  TRIGGER */
  __IM uint32_t  FIFO0;     /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
  __IM uint32_t  ITATBCTR2; /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
  uint32_t       RESERVED4[1U];
  __IM uint32_t  ITATBCTR0; /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
  __IM uint32_t  FIFO1;     /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
  __IOM uint32_t ITCTRL;    /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
  uint32_t       RESERVED5[39U];
  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W)  Claim tag set */
  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
  uint32_t       RESERVED7[8U];
  __IM uint32_t  DEVID;   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
  __IM uint32_t  DEVTYPE; /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
} TPI_Type;

/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0U                                       /*!< TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */

/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0U                                 /*!< TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */

/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3U                                /*!< TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */

#define TPI_FFSR_TCPresent_Pos 2U                                /*!< TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */

#define TPI_FFSR_FtStopped_Pos 1U                                /*!< TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */

#define TPI_FFSR_FlInProg_Pos 0U                                   /*!< TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */

/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8U                             /*!< TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */

#define TPI_FFCR_EnFCont_Pos 1U                              /*!< TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */

/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0U                                     /*!< TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */

/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */

#define TPI_FIFO0_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */

#define TPI_FIFO0_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */

#define TPI_FIFO0_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */

#define TPI_FIFO0_ETM2_Pos 16U                            /*!< TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */

#define TPI_FIFO0_ETM1_Pos 8U                             /*!< TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */

#define TPI_FIFO0_ETM0_Pos 0U                                 /*!< TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */

/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */

/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U                                  /*!< TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */

#define TPI_FIFO1_ITM_bytecount_Pos 27U                                    /*!< TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */

#define TPI_FIFO1_ETM_ATVALID_Pos 26U                                  /*!< TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */

#define TPI_FIFO1_ETM_bytecount_Pos 24U                                    /*!< TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */

#define TPI_FIFO1_ITM2_Pos 16U                            /*!< TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */

#define TPI_FIFO1_ITM1_Pos 8U                             /*!< TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */

#define TPI_FIFO1_ITM0_Pos 0U                                 /*!< TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */

/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U                                       /*!< TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */

/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U                                 /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */

/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U                               /*!< TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */

#define TPI_DEVID_MANCVALID_Pos 10U                                /*!< TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */

#define TPI_DEVID_PTINVALID_Pos 9U                                 /*!< TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */

#define TPI_DEVID_MinBufSz_Pos 6U                                /*!< TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */

#define TPI_DEVID_AsynClkIn_Pos 5U                                 /*!< TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */

#define TPI_DEVID_NrTraceInput_Pos 0U                                         /*!< TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */

/* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U                                   /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */

#define TPI_DEVTYPE_SubType_Pos 0U                                     /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */

/*@}*/ /* end of group CMSIS_TPI */

#if (__MPU_PRESENT == 1U)
/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
  \brief    Type definitions for the Memory Protection Unit (MPU)
  @{
 */

/**
  \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct {
  __IM uint32_t  TYPE;    /*!< Offset: 0x000 (R/ )  MPU Type Register */
  __IOM uint32_t CTRL;    /*!< Offset: 0x004 (R/W)  MPU Control Register */
  __IOM uint32_t RNR;     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
  __IOM uint32_t RBAR;    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
  __IOM uint32_t RASR;    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;

/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U                              /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */

#define MPU_TYPE_DREGION_Pos 8U                               /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */

#define MPU_TYPE_SEPARATE_Pos 0U                                 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */

/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U                               /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */

#define MPU_CTRL_HFNMIENA_Pos 1U                             /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */

#define MPU_CTRL_ENABLE_Pos 0U                               /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */

/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U                                 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 5U                                 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */

#define MPU_RBAR_VALID_Pos 4U                          /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */

#define MPU_RBAR_REGION_Pos 0U                                 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U                              /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */

#define MPU_RASR_XN_Pos 28U                      /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */

#define MPU_RASR_AP_Pos 24U                        /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */

#define MPU_RASR_TEX_Pos 19U                         /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */

#define MPU_RASR_S_Pos 18U                     /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */

#define MPU_RASR_C_Pos 17U                     /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */

#define MPU_RASR_B_Pos 16U                     /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */

#define MPU_RASR_SRD_Pos 8U                           /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

#define MPU_RASR_SIZE_Pos 1U                            /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

#define MPU_RASR_ENABLE_Pos 0U                               /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

/*@} end of group CMSIS_MPU */
#endif

/**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Type definitions for the Core Debug Registers
  @{
 */

/**
  \brief  Structure type to access the Core Debug Register (CoreDebug).
 */
typedef struct {
  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
  __OM uint32_t  DCRSR; /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
} CoreDebug_Type;

/* Debug Halting Control and Status Register Definitions */
#define CoreDebug_DHCSR_DBGKEY_Pos 16U                                      /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U                                     /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U                                      /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U                                   /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U                                  /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */

#define CoreDebug_DHCSR_S_HALT_Pos 17U                                 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U                                   /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U                                       /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U                                      /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */

#define CoreDebug_DHCSR_C_STEP_Pos 2U                                  /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */

#define CoreDebug_DHCSR_C_HALT_Pos 1U                                  /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U                                         /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U                                 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */

#define CoreDebug_DCRSR_REGSEL_Pos 0U                                         /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */

/* Debug Exception and Monitor Control Register Definitions */
#define CoreDebug_DEMCR_TRCENA_Pos 24U                                 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */

#define CoreDebug_DEMCR_MON_REQ_Pos 19U                                  /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */

#define CoreDebug_DEMCR_MON_STEP_Pos 18U                                   /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */

#define CoreDebug_DEMCR_MON_PEND_Pos 17U                                   /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */

#define CoreDebug_DEMCR_MON_EN_Pos 16U                                 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U                                     /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U                                     /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U                                     /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U                                      /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U                                     /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U                                      /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U                                    /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */

/*@} end of group CMSIS_CoreDebug */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */

/**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field.
  \return           Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)

/**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register.
  \return           Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)

/*@} end of group CMSIS_core_bitfield */

/**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */

/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE       (0xE000E000UL)        /*!< System Control Space Base Address */
#define ITM_BASE       (0xE0000000UL)        /*!< ITM Base Address */
#define DWT_BASE       (0xE0001000UL)        /*!< DWT Base Address */
#define TPI_BASE       (0xE0040000UL)        /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL)        /*!< Core Debug Base Address */
#define SysTick_BASE   (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE      (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE       (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */

#define SCnSCB    ((SCnSCB_Type *)SCS_BASE)          /*!< System control Register not in SCB */
#define SCB       ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct */
#define SysTick   ((SysTick_Type *)SysTick_BASE)     /*!< SysTick configuration struct */
#define NVIC      ((NVIC_Type *)NVIC_BASE)           /*!< NVIC configuration struct */
#define ITM       ((ITM_Type *)ITM_BASE)             /*!< ITM configuration struct */
#define DWT       ((DWT_Type *)DWT_BASE)             /*!< DWT configuration struct */
#define TPI       ((TPI_Type *)TPI_BASE)             /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */

#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL)  /*!< Memory Protection Unit */
#define MPU      ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
#endif

/*@} */

/*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Debug Functions
  - Core Register Access Functions
 ******************************************************************************/
/**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/

/* ##########################   NVIC functions  #################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */

/**
  \brief   Set Priority Grouping
  \details Sets the priority grouping field using the required unlock sequence.
           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
           Only values from 0..7 are used.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */

  reg_value = SCB->AIRCR;                                                                             /* read old register configuration    */
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));                         /* clear bits to change               */
  reg_value  = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */
  SCB->AIRCR = reg_value;
}

/**
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); }

/**
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Disable External Interrupt
  \details Disables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Pending Interrupt
  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
 */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
  return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}

/**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of an external interrupt.
  \param [in]      IRQn  Interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of an external interrupt.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); }

/**
  \brief   Get Active Interrupt
  \details Reads the active register in NVIC and returns the active bit.
  \param [in]      IRQn  Interrupt number.
  \return             0  Interrupt status is not active.
  \return             1  Interrupt status is active.
 */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); }

/**
  \brief   Set Interrupt Priority
  \details Sets the priority of an interrupt.
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
  if ((int32_t)(IRQn) < 0) {
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  } else {
    NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}

/**
  \brief   Get Interrupt Priority
  \details Reads the priority of an interrupt.
           The interrupt number can be positive to specify an external (device specific) interrupt,
           or negative to specify an internal (core) interrupt.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {

  if ((int32_t)(IRQn) < 0) {
    return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
  } else {
    return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
  }
}

/**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
}

/**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
}

/**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
__STATIC_INLINE void NVIC_SystemReset(void) {
  __DSB();                                                                                                                         /* Ensure all outstanding memory accesses included
                                                                                                                                      buffered write are completed before reset */
  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
  __DSB();                                                                                                                         /* Ensure completion of memory access */

  for (;;) /* wait until reset */
  {
    __NOP();
  }
}

/*@} end of CMSIS_Core_NVICFunctions */

/* ##################################    SysTick function  ############################################ */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */

#if (__Vendor_SysTickConfig == 0U)

/**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
           function SysTick_Config is not included. In this case, the file device.h
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
    return (1UL); /* Reload value impossible */
  }

  SysTick->LOAD = (uint32_t)(ticks - 1UL);                                                         /* set reload register */
  NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL);                                 /* set Priority for Systick Interrupt */
  SysTick->VAL  = 0UL;                                                                             /* Load the SysTick Counter Value */
  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                                                    /* Function successful */
}

#endif

/*@} end of CMSIS_Core_SysTickFunctions */

/* ##################################### Debug In/Output function ########################################### */
/**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_core_DebugFunctions ITM Functions
  \brief    Functions that access the ITM debug interface.
  @{
 */

extern volatile int32_t ITM_RxBuffer;  /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

/**
  \brief   ITM Send Character
  \details Transmits a character via the ITM channel 0, and
           \li Just returns when no debugger is connected that has booked the output.
           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  \param [in]     ch  Character to transmit.
  \returns            Character to transmit.
 */
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
      ((ITM->TER & 1UL) != 0UL))                  /* ITM Port #0 enabled */
  {
    while (ITM->PORT[0U].u32 == 0UL) {
      __NOP();
    }
    ITM->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}

/**
  \brief   ITM Receive Character
  \details Inputs a character via the external variable \ref ITM_RxBuffer.
  \return             Received character.
  \return         -1  No character pending.
 */
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
  int32_t ch = -1; /* no character available */

  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
    ch           = ITM_RxBuffer;
    ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
  }

  return (ch);
}

/**
  \brief   ITM Check Character
  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
  \return          0  No character available.
  \return          1  Character available.
 */
__STATIC_INLINE int32_t ITM_CheckChar(void) {

  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
    return (0); /* no character available */
  } else {
    return (1); /*    character available */
  }
}

/*@} end of CMSIS_core_DebugFunctions */

#ifdef __cplusplus
}
#endif

#endif /* __CORE_SC300_H_DEPENDANT */

#endif /* __CMSIS_GENERIC */


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
================================================
/**
 ******************************************************************************
 * @file    stm32_hal_legacy.h
 * @author  MCD Application Team
 * @version V1.1.1
 * @date    12-May-2017
 * @brief   This file contains aliases definition for the STM32Cube HAL constants
 *          macros and functions maintained for legacy purpose.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_HAL_LEGACY
#define __STM32_HAL_LEGACY

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
 * @{
 */
#define AES_FLAG_RDERR      CRYP_FLAG_RDERR
#define AES_FLAG_WRERR      CRYP_FLAG_WRERR
#define AES_CLEARFLAG_CCF   CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR

/**
 * @}
 */

/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
 * @{
 */
#define ADC_RESOLUTION12b                   ADC_RESOLUTION_12B
#define ADC_RESOLUTION10b                   ADC_RESOLUTION_10B
#define ADC_RESOLUTION8b                    ADC_RESOLUTION_8B
#define ADC_RESOLUTION6b                    ADC_RESOLUTION_6B
#define OVR_DATA_OVERWRITTEN                ADC_OVR_DATA_OVERWRITTEN
#define OVR_DATA_PRESERVED                  ADC_OVR_DATA_PRESERVED
#define EOC_SINGLE_CONV                     ADC_EOC_SINGLE_CONV
#define EOC_SEQ_CONV                        ADC_EOC_SEQ_CONV
#define EOC_SINGLE_SEQ_CONV                 ADC_EOC_SINGLE_SEQ_CONV
#define REGULAR_GROUP                       ADC_REGULAR_GROUP
#define INJECTED_GROUP                      ADC_INJECTED_GROUP
#define REGULAR_INJECTED_GROUP              ADC_REGULAR_INJECTED_GROUP
#define AWD_EVENT                           ADC_AWD_EVENT
#define AWD1_EVENT                          ADC_AWD1_EVENT
#define AWD2_EVENT                          ADC_AWD2_EVENT
#define AWD3_EVENT                          ADC_AWD3_EVENT
#define OVR_EVENT                           ADC_OVR_EVENT
#define JQOVF_EVENT                         ADC_JQOVF_EVENT
#define ALL_CHANNELS                        ADC_ALL_CHANNELS
#define REGULAR_CHANNELS                    ADC_REGULAR_CHANNELS
#define INJECTED_CHANNELS                   ADC_INJECTED_CHANNELS
#define SYSCFG_FLAG_SENSOR_ADC              ADC_FLAG_SENSOR
#define SYSCFG_FLAG_VREF_ADC                ADC_FLAG_VREFINT
#define ADC_CLOCKPRESCALER_PCLK_DIV1        ADC_CLOCK_SYNC_PCLK_DIV1
#define ADC_CLOCKPRESCALER_PCLK_DIV2        ADC_CLOCK_SYNC_PCLK_DIV2
#define ADC_CLOCKPRESCALER_PCLK_DIV4        ADC_CLOCK_SYNC_PCLK_DIV4
#define ADC_CLOCKPRESCALER_PCLK_DIV6        ADC_CLOCK_SYNC_PCLK_DIV6
#define ADC_CLOCKPRESCALER_PCLK_DIV8        ADC_CLOCK_SYNC_PCLK_DIV8
#define ADC_EXTERNALTRIG0_T6_TRGO           ADC_EXTERNALTRIGCONV_T6_TRGO
#define ADC_EXTERNALTRIG1_T21_CC2           ADC_EXTERNALTRIGCONV_T21_CC2
#define ADC_EXTERNALTRIG2_T2_TRGO           ADC_EXTERNALTRIGCONV_T2_TRGO
#define ADC_EXTERNALTRIG3_T2_CC4            ADC_EXTERNALTRIGCONV_T2_CC4
#define ADC_EXTERNALTRIG4_T22_TRGO          ADC_EXTERNALTRIGCONV_T22_TRGO
#define ADC_EXTERNALTRIG7_EXT_IT11          ADC_EXTERNALTRIGCONV_EXT_IT11
#define ADC_CLOCK_ASYNC                     ADC_CLOCK_ASYNC_DIV1
#define ADC_EXTERNALTRIG_EDGE_NONE          ADC_EXTERNALTRIGCONVEDGE_NONE
#define ADC_EXTERNALTRIG_EDGE_RISING        ADC_EXTERNALTRIGCONVEDGE_RISING
#define ADC_EXTERNALTRIG_EDGE_FALLING       ADC_EXTERNALTRIGCONVEDGE_FALLING
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
#define ADC_SAMPLETIME_2CYCLE_5             ADC_SAMPLETIME_2CYCLES_5

#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
#define HAL_ADC_STATE_EOC_REG  HAL_ADC_STATE_REG_EOC
#define HAL_ADC_STATE_EOC_INJ  HAL_ADC_STATE_INJ_EOC
#define HAL_ADC_STATE_ERROR    HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY     HAL_ADC_STATE_BUSY_INTERNAL
#define HAL_ADC_STATE_AWD      HAL_ADC_STATE_AWD1
/**
 * @}
 */

/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
 * @{
 */

#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG

/**
 * @}
 */

/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
 * @{
 */
#define COMP_WINDOWMODE_DISABLED      COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED       COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT    COMP_EXTI_LINE_COMP1
#define COMP_EXTI_LINE_COMP2_EVENT    COMP_EXTI_LINE_COMP2
#define COMP_EXTI_LINE_COMP3_EVENT    COMP_EXTI_LINE_COMP3
#define COMP_EXTI_LINE_COMP4_EVENT    COMP_EXTI_LINE_COMP4
#define COMP_EXTI_LINE_COMP5_EVENT    COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT    COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT    COMP_EXTI_LINE_COMP7
#define COMP_LPTIMCONNECTION_ENABLED  COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1      COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */

#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6

#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT    COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1   COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2   COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1       COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2       COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1        COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
/* to the second dedicated IO (only for COMP2).                               */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5

#define COMP_OUTPUTLEVEL_LOW  COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH

/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif

#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5  COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3  COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3  COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4  COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5  COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE     COMP_BLANKINGSRC_NONE
#endif

#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED  COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED     COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED   COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER      COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif

#endif
/**
 * @}
 */

/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
 * @{
 */
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
/**
 * @}
 */

/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
 * @{
 */

#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
#define CRC_OUTPUTDATA_INVERSION_ENABLED  CRC_OUTPUTDATA_INVERSION_ENABLE

/**
 * @}
 */

/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
 * @{
 */

#define DAC1_CHANNEL_1              DAC_CHANNEL_1
#define DAC1_CHANNEL_2              DAC_CHANNEL_2
#define DAC2_CHANNEL_1              DAC_CHANNEL_1
#define DAC_WAVE_NONE               0x00000000U
#define DAC_WAVE_NOISE              DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE           DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE     DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE    DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE

/**
 * @}
 */

/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
 * @{
 */
#define HAL_REMAPDMA_ADC_DMA_CH2       DMA_REMAP_ADC_DMA_CH2
#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
#define HAL_REMAPDMA_TIM16_DMA_CH4     DMA_REMAP_TIM16_DMA_CH4
#define HAL_REMAPDMA_TIM17_DMA_CH2     DMA_REMAP_TIM17_DMA_CH2
#define HAL_REMAPDMA_USART3_DMA_CH32   DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_TIM16_DMA_CH6     DMA_REMAP_TIM16_DMA_CH6
#define HAL_REMAPDMA_TIM17_DMA_CH7     DMA_REMAP_TIM17_DMA_CH7
#define HAL_REMAPDMA_SPI2_DMA_CH67     DMA_REMAP_SPI2_DMA_CH67
#define HAL_REMAPDMA_USART2_DMA_CH67   DMA_REMAP_USART2_DMA_CH67
#define HAL_REMAPDMA_USART3_DMA_CH32   DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_I2C1_DMA_CH76     DMA_REMAP_I2C1_DMA_CH76
#define HAL_REMAPDMA_TIM1_DMA_CH6      DMA_REMAP_TIM1_DMA_CH6
#define HAL_REMAPDMA_TIM2_DMA_CH7      DMA_REMAP_TIM2_DMA_CH7
#define HAL_REMAPDMA_TIM3_DMA_CH6      DMA_REMAP_TIM3_DMA_CH6

#define IS_HAL_REMAPDMA                IS_DMA_REMAP
#define __HAL_REMAPDMA_CHANNEL_ENABLE  __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE

/**
 * @}
 */

/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
 * @{
 */

#define TYPEPROGRAM_BYTE             FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_HALFWORD         FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_WORD             FLASH_TYPEPROGRAM_WORD
#define TYPEPROGRAM_DOUBLEWORD       FLASH_TYPEPROGRAM_DOUBLEWORD
#define TYPEERASE_SECTORS            FLASH_TYPEERASE_SECTORS
#define TYPEERASE_PAGES              FLASH_TYPEERASE_PAGES
#define TYPEERASE_PAGEERASE          FLASH_TYPEERASE_PAGES
#define TYPEERASE_MASSERASE          FLASH_TYPEERASE_MASSERASE
#define WRPSTATE_DISABLE             OB_WRPSTATE_DISABLE
#define WRPSTATE_ENABLE              OB_WRPSTATE_ENABLE
#define HAL_FLASH_TIMEOUT_VALUE      FLASH_TIMEOUT_VALUE
#define OBEX_PCROP                   OPTIONBYTE_PCROP
#define OBEX_BOOTCONFIG              OPTIONBYTE_BOOTCONFIG
#define PCROPSTATE_DISABLE           OB_PCROP_STATE_DISABLE
#define PCROPSTATE_ENABLE            OB_PCROP_STATE_ENABLE
#define TYPEERASEDATA_BYTE           FLASH_TYPEERASEDATA_BYTE
#define TYPEERASEDATA_HALFWORD       FLASH_TYPEERASEDATA_HALFWORD
#define TYPEERASEDATA_WORD           FLASH_TYPEERASEDATA_WORD
#define TYPEPROGRAMDATA_BYTE         FLASH_TYPEPROGRAMDATA_BYTE
#define TYPEPROGRAMDATA_HALFWORD     FLASH_TYPEPROGRAMDATA_HALFWORD
#define TYPEPROGRAMDATA_WORD         FLASH_TYPEPROGRAMDATA_WORD
#define TYPEPROGRAMDATA_FASTBYTE     FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD     FLASH_TYPEPROGRAMDATA_FASTWORD
#define PAGESIZE                     FLASH_PAGE_SIZE
#define TYPEPROGRAM_FASTBYTE         FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD     FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD         FLASH_TYPEPROGRAM_WORD
#define VOLTAGE_RANGE_1              FLASH_VOLTAGE_RANGE_1
#define VOLTAGE_RANGE_2              FLASH_VOLTAGE_RANGE_2
#define VOLTAGE_RANGE_3              FLASH_VOLTAGE_RANGE_3
#define VOLTAGE_RANGE_4              FLASH_VOLTAGE_RANGE_4
#define TYPEPROGRAM_FAST             FLASH_TYPEPROGRAM_FAST
#define TYPEPROGRAM_FAST_AND_LAST    FLASH_TYPEPROGRAM_FAST_AND_LAST
#define WRPAREA_BANK1_AREAA          OB_WRPAREA_BANK1_AREAA
#define WRPAREA_BANK1_AREAB          OB_WRPAREA_BANK1_AREAB
#define WRPAREA_BANK2_AREAA          OB_WRPAREA_BANK2_AREAA
#define WRPAREA_BANK2_AREAB          OB_WRPAREA_BANK2_AREAB
#define IWDG_STDBY_FREEZE            OB_IWDG_STDBY_FREEZE
#define IWDG_STDBY_ACTIVE            OB_IWDG_STDBY_RUN
#define IWDG_STOP_FREEZE             OB_IWDG_STOP_FREEZE
#define IWDG_STOP_ACTIVE             OB_IWDG_STOP_RUN
#define FLASH_ERROR_NONE             HAL_FLASH_ERROR_NONE
#define FLASH_ERROR_RD               HAL_FLASH_ERROR_RD
#define FLASH_ERROR_PG               HAL_FLASH_ERROR_PROG
#define FLASH_ERROR_PGP              HAL_FLASH_ERROR_PGS
#define FLASH_ERROR_WRP              HAL_FLASH_ERROR_WRP
#define FLASH_ERROR_OPTV             HAL_FLASH_ERROR_OPTV
#define FLASH_ERROR_OPTVUSR          HAL_FLASH_ERROR_OPTVUSR
#define FLASH_ERROR_PROG             HAL_FLASH_ERROR_PROG
#define FLASH_ERROR_OP               HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_PGA              HAL_FLASH_ERROR_PGA
#define FLASH_ERROR_SIZE             HAL_FLASH_ERROR_SIZE
#define FLASH_ERROR_SIZ              HAL_FLASH_ERROR_SIZE
#define FLASH_ERROR_PGS              HAL_FLASH_ERROR_PGS
#define FLASH_ERROR_MIS              HAL_FLASH_ERROR_MIS
#define FLASH_ERROR_FAST             HAL_FLASH_ERROR_FAST
#define FLASH_ERROR_FWWERR           HAL_FLASH_ERROR_FWWERR
#define FLASH_ERROR_NOTZERO          HAL_FLASH_ERROR_NOTZERO
#define FLASH_ERROR_OPERATION        HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_ERS              HAL_FLASH_ERROR_ERS
#define OB_WDG_SW                    OB_IWDG_SW
#define OB_WDG_HW                    OB_IWDG_HW
#define OB_SDADC12_VDD_MONITOR_SET   OB_SDACD_VDD_MONITOR_SET
#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
#define OB_RAM_PARITY_CHECK_SET      OB_SRAM_PARITY_SET
#define OB_RAM_PARITY_CHECK_RESET    OB_SRAM_PARITY_RESET
#define IS_OB_SDADC12_VDD_MONITOR    IS_OB_SDACD_VDD_MONITOR
#define OB_RDP_LEVEL0                OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1                OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2                OB_RDP_LEVEL_2

/**
 * @}
 */

/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
 * @{
 */

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9  I2C_FASTMODEPLUS_PA9
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6  I2C_FASTMODEPLUS_PB6
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7  I2C_FASTMODEPLUS_PB7
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8  I2C_FASTMODEPLUS_PB8
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9  I2C_FASTMODEPLUS_PB9
#define HAL_SYSCFG_FASTMODEPLUS_I2C1     I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2     I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3     I2C_FASTMODEPLUS_I2C3
/**
 * @}
 */

/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
 * @{
 */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE  FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8      FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16     FMC_NAND_MEM_BUS_WIDTH_16
#else
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE  FMC_NAND_PCC_WAIT_FEATURE_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8      FMC_NAND_PCC_MEM_BUS_WIDTH_8
#define FMC_NAND_MEM_BUS_WIDTH_16     FMC_NAND_PCC_MEM_BUS_WIDTH_16
#endif
/**
 * @}
 */

/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
 * @{
 */

#define FSMC_NORSRAM_TYPEDEF          FSMC_NORSRAM_TypeDef
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
/**
 * @}
 */

/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
 * @{
 */
#define GET_GPIO_SOURCE GPIO_GET_INDEX
#define GET_GPIO_INDEX  GPIO_GET_INDEX

#if defined(STM32F4)
#define GPIO_AF12_SDMMC  GPIO_AF12_SDIO
#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
#endif

#if defined(STM32F7)
#define GPIO_AF12_SDIO  GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif

#if defined(STM32L4)
#define GPIO_AF12_SDIO  GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif

#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1

#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
#define GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST   GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */

#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW      GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM   GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH     GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */

#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */

#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
 * @}
 */

/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
 * @{
 */

#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE        __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE       __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET       __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET     __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE  __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7  */

/**
 * @}
 */

/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
 * @{
 */
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7

#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
/**
 * @}
 */

/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
 * @{
 */
#define I2C_DUALADDRESS_DISABLED  I2C_DUALADDRESS_DISABLE
#define I2C_DUALADDRESS_ENABLED   I2C_DUALADDRESS_ENABLE
#define I2C_GENERALCALL_DISABLED  I2C_GENERALCALL_DISABLE
#define I2C_GENERALCALL_ENABLED   I2C_GENERALCALL_ENABLE
#define I2C_NOSTRETCH_DISABLED    I2C_NOSTRETCH_DISABLE
#define I2C_NOSTRETCH_ENABLED     I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED  I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX    HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX    HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_SLAVE_BUSY_TX  HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_SLAVE_BUSY_RX  HAL_I2C_STATE_BUSY_RX
#endif
/**
 * @}
 */

/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
 * @{
 */
#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
#define IRDA_ONE_BIT_SAMPLE_ENABLED  IRDA_ONE_BIT_SAMPLE_ENABLE

/**
 * @}
 */

/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
 * @{
 */
#define KR_KEY_RELOAD IWDG_KEY_RELOAD
#define KR_KEY_ENABLE IWDG_KEY_ENABLE
#define KR_KEY_EWA    IWDG_KEY_WRITE_ACCESS_ENABLE
#define KR_KEY_DWA    IWDG_KEY_WRITE_ACCESS_DISABLE
/**
 * @}
 */

/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
 * @{
 */

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS

#define LPTIM_CLOCKPOLARITY_RISINGEDGE  LPTIM_CLOCKPOLARITY_RISING
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
#define LPTIM_CLOCKPOLARITY_BOTHEDGES   LPTIM_CLOCKPOLARITY_RISING_FALLING

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS     LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS     LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS     LPTIM_TRIGSAMPLETIME_8TRANSITIONS

/* The following 3 definition have also been present in a temporary version of lptim.h */
/* They need to be renamed also to the right name, just in case */
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS

/**
 * @}
 */

/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
 * @{
 */
#define HAL_NAND_Read_Page       HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page      HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea  HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b

#define NAND_AddressTypedef NAND_AddressTypeDef

#define __ARRAY_ADDRESS  ARRAY_ADDRESS
#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
/**
 * @}
 */

/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
 * @{
 */
#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
#define NOR_SUCCESS       HAL_NOR_STATUS_SUCCESS
#define NOR_ONGOING       HAL_NOR_STATUS_ONGOING
#define NOR_ERROR         HAL_NOR_STATUS_ERROR
#define NOR_TIMEOUT       HAL_NOR_STATUS_TIMEOUT

#define __NOR_WRITE      NOR_WRITE
#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
/**
 * @}
 */

/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
 * @{
 */

#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3

#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3

#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1

#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1

#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1

#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1

#define OPAMP_PGACONNECT_NO  OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1

/**
 * @}
 */

/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
 * @{
 */
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
 * @}
 */

/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
 * @{
 */

/* Compact Flash-ATA registers description */
#define CF_DATA                 ATA_DATA
#define CF_SECTOR_COUNT         ATA_SECTOR_COUNT
#define CF_SECTOR_NUMBER        ATA_SECTOR_NUMBER
#define CF_CYLINDER_LOW         ATA_CYLINDER_LOW
#define CF_CYLINDER_HIGH        ATA_CYLINDER_HIGH
#define CF_CARD_HEAD            ATA_CARD_HEAD
#define CF_STATUS_CMD           ATA_STATUS_CMD
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
#define CF_COMMON_DATA_AREA     ATA_COMMON_DATA_AREA

/* Compact Flash-ATA commands */
#define CF_READ_SECTOR_CMD  ATA_READ_SECTOR_CMD
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
#define CF_IDENTIFY_CMD     ATA_IDENTIFY_CMD

#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
#define PCCARD_SUCCESS       HAL_PCCARD_STATUS_SUCCESS
#define PCCARD_ONGOING       HAL_PCCARD_STATUS_ONGOING
#define PCCARD_ERROR         HAL_PCCARD_STATUS_ERROR
#define PCCARD_TIMEOUT       HAL_PCCARD_STATUS_TIMEOUT
/**
 * @}
 */

/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
 * @{
 */

#define FORMAT_BIN RTC_FORMAT_BIN
#define FORMAT_BCD RTC_FORMAT_BCD

#define RTC_ALARMSUBSECONDMASK_None    RTC_ALARMSUBSECONDMASK_NONE
#define RTC_TAMPERERASEBACKUP_ENABLED  RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED   RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED    RTC_TAMPERMASK_FLAG_ENABLE

#define RTC_MASKTAMPERFLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED  RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_MASKTAMPERFLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPER1_2_INTERRUPT        RTC_ALL_TAMPER_INTERRUPT
#define RTC_TAMPER1_2_3_INTERRUPT      RTC_ALL_TAMPER_INTERRUPT

#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
#define RTC_TIMESTAMPPIN_PA0  RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8  RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1  RTC_TIMESTAMPPIN_POS2

#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
#define RTC_OUTPUT_REMAP_PB2  RTC_OUTPUT_REMAP_POS1

#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1

/**
 * @}
 */

/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
 * @{
 */
#define SMARTCARD_NACK_ENABLED  SMARTCARD_NACK_ENABLE
#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE

#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED  SMARTCARD_ONE_BIT_SAMPLE_ENABLE
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE  SMARTCARD_ONE_BIT_SAMPLE_DISABLE
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE   SMARTCARD_ONE_BIT_SAMPLE_ENABLE

#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
#define SMARTCARD_TIMEOUT_ENABLED  SMARTCARD_TIMEOUT_ENABLE

#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
#define SMARTCARD_LASTBIT_ENABLED  SMARTCARD_LASTBIT_ENABLE
/**
 * @}
 */

/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
 * @{
 */
#define SMBUS_DUALADDRESS_DISABLED   SMBUS_DUALADDRESS_DISABLE
#define SMBUS_DUALADDRESS_ENABLED    SMBUS_DUALADDRESS_ENABLE
#define SMBUS_GENERALCALL_DISABLED   SMBUS_GENERALCALL_DISABLE
#define SMBUS_GENERALCALL_ENABLED    SMBUS_GENERALCALL_ENABLE
#define SMBUS_NOSTRETCH_DISABLED     SMBUS_NOSTRETCH_DISABLE
#define SMBUS_NOSTRETCH_ENABLED      SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED   SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED  SMBUS_ANALOGFILTER_DISABLE
#define SMBUS_PEC_DISABLED           SMBUS_PEC_DISABLE
#define SMBUS_PEC_ENABLED            SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**
 * @}
 */

/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
 * @{
 */
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
#define SPI_TIMODE_ENABLED  SPI_TIMODE_ENABLE

#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
#define SPI_CRCCALCULATION_ENABLED  SPI_CRCCALCULATION_ENABLE

#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLED  SPI_NSS_PULSE_ENABLE

/**
 * @}
 */

/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
 * @{
 */
#define CCER_CCxE_MASK  TIM_CCER_CCxE_MASK
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK

#define TIM_DMABase_CR1   TIM_DMABASE_CR1
#define TIM_DMABase_CR2   TIM_DMABASE_CR2
#define TIM_DMABase_SMCR  TIM_DMABASE_SMCR
#define TIM_DMABase_DIER  TIM_DMABASE_DIER
#define TIM_DMABase_SR    TIM_DMABASE_SR
#define TIM_DMABase_EGR   TIM_DMABASE_EGR
#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
#define TIM_DMABase_CCER  TIM_DMABASE_CCER
#define TIM_DMABase_CNT   TIM_DMABASE_CNT
#define TIM_DMABase_PSC   TIM_DMABASE_PSC
#define TIM_DMABase_ARR   TIM_DMABASE_ARR
#define TIM_DMABase_RCR   TIM_DMABASE_RCR
#define TIM_DMABase_CCR1  TIM_DMABASE_CCR1
#define TIM_DMABase_CCR2  TIM_DMABASE_CCR2
#define TIM_DMABase_CCR3  TIM_DMABASE_CCR3
#define TIM_DMABase_CCR4  TIM_DMABASE_CCR4
#define TIM_DMABase_BDTR  TIM_DMABASE_BDTR
#define TIM_DMABase_DCR   TIM_DMABASE_DCR
#define TIM_DMABase_DMAR  TIM_DMABASE_DMAR
#define TIM_DMABase_OR1   TIM_DMABASE_OR1
#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
#define TIM_DMABase_CCR5  TIM_DMABASE_CCR5
#define TIM_DMABase_CCR6  TIM_DMABASE_CCR6
#define TIM_DMABase_OR2   TIM_DMABASE_OR2
#define TIM_DMABase_OR3   TIM_DMABASE_OR3
#define TIM_DMABase_OR    TIM_DMABASE_OR

#define TIM_EventSource_Update  TIM_EVENTSOURCE_UPDATE
#define TIM_EventSource_CC1     TIM_EVENTSOURCE_CC1
#define TIM_EventSource_CC2     TIM_EVENTSOURCE_CC2
#define TIM_EventSource_CC3     TIM_EVENTSOURCE_CC3
#define TIM_EventSource_CC4     TIM_EVENTSOURCE_CC4
#define TIM_EventSource_COM     TIM_EVENTSOURCE_COM
#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
#define TIM_EventSource_Break   TIM_EVENTSOURCE_BREAK
#define TIM_EventSource_Break2  TIM_EVENTSOURCE_BREAK2

#define TIM_DMABurstLength_1Transfer   TIM_DMABURSTLENGTH_1TRANSFER
#define TIM_DMABurstLength_2Transfers  TIM_DMABURSTLENGTH_2TRANSFERS
#define TIM_DMABurstLength_3Transfers  TIM_DMABURSTLENGTH_3TRANSFERS
#define TIM_DMABurstLength_4Transfers  TIM_DMABURSTLENGTH_4TRANSFERS
#define TIM_DMABurstLength_5Transfers  TIM_DMABURSTLENGTH_5TRANSFERS
#define TIM_DMABurstLength_6Transfers  TIM_DMABURSTLENGTH_6TRANSFERS
#define TIM_DMABurstLength_7Transfers  TIM_DMABURSTLENGTH_7TRANSFERS
#define TIM_DMABurstLength_8Transfers  TIM_DMABURSTLENGTH_8TRANSFERS
#define TIM_DMABurstLength_9Transfers  TIM_DMABURSTLENGTH_9TRANSFERS
#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS

/**
 * @}
 */

/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
 * @{
 */
#define TSC_SYNC_POL_FALL      TSC_SYNC_POLARITY_FALLING
#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
/**
 * @}
 */

/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
 * @{
 */
#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
#define UART_ONEBIT_SAMPLING_ENABLED  UART_ONE_BIT_SAMPLE_ENABLE
#define UART_ONE_BIT_SAMPLE_DISABLED  UART_ONE_BIT_SAMPLE_DISABLE
#define UART_ONE_BIT_SAMPLE_ENABLED   UART_ONE_BIT_SAMPLE_ENABLE

#define __HAL_UART_ONEBIT_ENABLE  __HAL_UART_ONE_BIT_SAMPLE_ENABLE
#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE

#define __DIV_SAMPLING16      UART_DIV_SAMPLING16
#define __DIVMANT_SAMPLING16  UART_DIVMANT_SAMPLING16
#define __DIVFRAQ_SAMPLING16  UART_DIVFRAQ_SAMPLING16
#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16

#define __DIV_SAMPLING8      UART_DIV_SAMPLING8
#define __DIVMANT_SAMPLING8  UART_DIVMANT_SAMPLING8
#define __DIVFRAQ_SAMPLING8  UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8

#define __DIV_LPUART UART_DIV_LPUART

#define UART_WAKEUPMETHODE_IDLELINE    UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK

/**
 * @}
 */

/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
 * @{
 */

#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
#define USART_CLOCK_ENABLED  USART_CLOCK_ENABLE

#define USARTNACK_ENABLED  USART_NACK_ENABLE
#define USARTNACK_DISABLED USART_NACK_DISABLE
/**
 * @}
 */

/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
 * @{
 */
#define CFR_BASE WWDG_CFR_BASE

/**
 * @}
 */

/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
 * @{
 */
#define CAN_FilterFIFO0      CAN_FILTER_FIFO0
#define CAN_FilterFIFO1      CAN_FILTER_FIFO1
#define CAN_IT_RQCP0         CAN_IT_TME
#define CAN_IT_RQCP1         CAN_IT_TME
#define CAN_IT_RQCP2         CAN_IT_TME
#define INAK_TIMEOUT         CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT         CAN_TIMEOUT_VALUE
#define CAN_TXSTATUS_FAILED  ((uint8_t)0x00)
#define CAN_TXSTATUS_OK      ((uint8_t)0x01)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)

/**
 * @}
 */

/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
 * @{
 */

#define VLAN_TAG            ETH_VLAN_TAG
#define MIN_ETH_PAYLOAD     ETH_MIN_ETH_PAYLOAD
#define MAX_ETH_PAYLOAD     ETH_MAX_ETH_PAYLOAD
#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
#define MACMIIAR_CR_MASK    ETH_MACMIIAR_CR_MASK
#define MACCR_CLEAR_MASK    ETH_MACCR_CLEAR_MASK
#define MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK

#define ETH_MMCCR       0x00000100U
#define ETH_MMCRIR      0x00000104U
#define ETH_MMCTIR      0x00000108U
#define ETH_MMCRIMR     0x0000010CU
#define ETH_MMCTIMR     0x00000110U
#define ETH_MMCTGFSCCR  0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR    0x00000168U
#define ETH_MMCRFCECR   0x00000194U
#define ETH_MMCRFAECR   0x00000198U
#define ETH_MMCRGUFCR   0x000001C4U

#define ETH_MAC_TXFIFO_FULL                           0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE                           0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ                           0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING                        0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING                        0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE                   0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY                          0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD                0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD                0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL                           0x00000300U /* Rx FIFO fill level: full */
#define ETH_MAC_READCONTROLLER_IDLE                   0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA           0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS         0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define ETH_MAC_READCONTROLLER_FLUSHING               0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE                   0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE                  0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE                0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE               0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE                  0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE           0x00000001U /* MAC MII receive protocol engine active */

/**
 * @}
 */

/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
 * @{
 */
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF        DCMI_IT_OVR
#define DCMI_FLAG_OVFRI    DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI    DCMI_FLAG_OVRMI

#define HAL_DCMI_ConfigCROP  HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP  HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop

/**
 * @}
 */

#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
 * @{
 */
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888   DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565   DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444

#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888   DMA2D_INPUT_RGB888
#define CM_RGB565   DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8       DMA2D_INPUT_L8
#define CM_AL44     DMA2D_INPUT_AL44
#define CM_AL88     DMA2D_INPUT_AL88
#define CM_L4       DMA2D_INPUT_L4
#define CM_A8       DMA2D_INPUT_A8
#define CM_A4       DMA2D_INPUT_A4
/**
 * @}
 */
#endif /* STM32L4 ||  STM32F7*/

/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
 * @{
 */

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/

/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
/**
 * @}
 */

/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_HASH_STATETypeDef  HAL_HASH_StateTypeDef
#define HAL_HASHPhaseTypeDef   HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish    HAL_HASH_MD5_Finish
#define HAL_HMAC_SHA1_Finish   HAL_HASH_SHA1_Finish
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish

/*HASH Algorithm Selection*/

#define HASH_AlgoSelection_SHA1   HASH_ALGOSELECTION_SHA1
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
#define HASH_AlgoSelection_MD5    HASH_ALGOSELECTION_MD5

#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC

#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey  HASH_HMAC_KEYTYPE_LONGKEY
/**
 * @}
 */

/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_EnableDBGSleepMode              HAL_DBGMCU_EnableDBGSleepMode
#define HAL_DisableDBGSleepMode             HAL_DBGMCU_DisableDBGSleepMode
#define HAL_EnableDBGStopMode               HAL_DBGMCU_EnableDBGStopMode
#define HAL_DisableDBGStopMode              HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode            HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode           HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd) == ENABLE) ? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect            HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd)                   (((cmd) == ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd) == ENABLE) ? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd)       (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd) == ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
 * @}
 */

/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
 * @{
 */
#define FLASH_HalfPageProgram     HAL_FLASHEx_HalfPageProgram
#define FLASH_EnableRunPowerDown  HAL_FLASHEx_EnableRunPowerDown
#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
#define HAL_DATA_EEPROMEx_Unlock  HAL_FLASHEx_DATAEEPROM_Unlock
#define HAL_DATA_EEPROMEx_Lock    HAL_FLASHEx_DATAEEPROM_Lock
#define HAL_DATA_EEPROMEx_Erase   HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program

/**
 * @}
 */

/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_I2CEx_AnalogFilter_Config     HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config    HAL_I2CEx_ConfigDigitalFilter
#define HAL_FMPI2CEx_AnalogFilter_Config  HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter

#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE) ? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus) : HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/**
 * @}
 */

/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
 * @{
 */
#define HAL_PWR_PVDConfig                HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg           HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown    HAL_PWREx_DisableFlashPowerDown
#define HAL_PWR_DisableVddio2Monitor     HAL_PWREx_DisableVddio2Monitor
#define HAL_PWR_EnableBkUpReg            HAL_PWREx_EnableBkUpReg
#define HAL_PWR_EnableFlashPowerDown     HAL_PWREx_EnableFlashPowerDown
#define HAL_PWR_EnableVddio2Monitor      HAL_PWREx_EnableVddio2Monitor
#define HAL_PWR_PVD_PVM_IRQHandler       HAL_PWREx_PVD_PVM_IRQHandler
#define HAL_PWR_PVDLevelConfig           HAL_PWR_ConfigPVD
#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
#define HAL_PWR_Vddio2MonitorCallback    HAL_PWREx_Vddio2MonitorCallback
#define HAL_PWREx_ActivateOverDrive      HAL_PWREx_EnableOverDrive
#define HAL_PWREx_DeactivateOverDrive    HAL_PWREx_DisableOverDrive
#define HAL_PWREx_DisableSDADCAnalog     HAL_PWREx_DisableSDADC
#define HAL_PWREx_EnableSDADCAnalog      HAL_PWREx_EnableSDADC
#define HAL_PWREx_PVMConfig              HAL_PWREx_ConfigPVM

#define PWR_MODE_NORMAL               PWR_PVD_MODE_NORMAL
#define PWR_MODE_IT_RISING            PWR_PVD_MODE_IT_RISING
#define PWR_MODE_IT_FALLING           PWR_PVD_MODE_IT_FALLING
#define PWR_MODE_IT_RISING_FALLING    PWR_PVD_MODE_IT_RISING_FALLING
#define PWR_MODE_EVENT_RISING         PWR_PVD_MODE_EVENT_RISING
#define PWR_MODE_EVENT_FALLING        PWR_PVD_MODE_EVENT_FALLING
#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING

#define CR_OFFSET_BB  PWR_CR_OFFSET_BB
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB

#define DBP_BitNumber    DBP_BIT_NUMBER
#define PVDE_BitNumber   PVDE_BIT_NUMBER
#define PMODE_BitNumber  PMODE_BIT_NUMBER
#define EWUP_BitNumber   EWUP_BIT_NUMBER
#define FPDS_BitNumber   FPDS_BIT_NUMBER
#define ODEN_BitNumber   ODEN_BIT_NUMBER
#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
#define BRE_BitNumber    BRE_BIT_NUMBER

#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL

/**
 * @}
 */

/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_SMBUS_Slave_Listen_IT         HAL_SMBUS_EnableListen_IT
#define HAL_SMBUS_SlaveAddrCallback       HAL_SMBUS_AddrCallback
#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
/**
 * @}
 */

/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
/**
 * @}
 */

/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_TIM_DMADelayPulseCplt    TIM_DMADelayPulseCplt
#define HAL_TIM_DMAError             TIM_DMAError
#define HAL_TIM_DMACaptureCplt       TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
/**
 * @}
 */

/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
/**
 * @}
 */

/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_LTDC_LineEvenCallback                   HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod                             HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig          HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
 * @}
 */

/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
 * @{
 */

/**
 * @}
 */

/* Exported macros ------------------------------------------------------------*/

/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
 * @{
 */
#define AES_IT_CC    CRYP_IT_CC
#define AES_IT_ERR   CRYP_IT_ERR
#define AES_FLAG_CCF CRYP_FLAG_CCF
/**
 * @}
 */

/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_GET_BOOT_MODE           __HAL_SYSCFG_GET_BOOT_MODE
#define __HAL_REMAPMEMORY_FLASH       __HAL_SYSCFG_REMAPMEMORY_FLASH
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
#define __HAL_REMAPMEMORY_SRAM        __HAL_SYSCFG_REMAPMEMORY_SRAM
#define __HAL_REMAPMEMORY_FMC         __HAL_SYSCFG_REMAPMEMORY_FMC
#define __HAL_REMAPMEMORY_FMC_SDRAM   __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
#define __HAL_REMAPMEMORY_FSMC        __HAL_SYSCFG_REMAPMEMORY_FSMC
#define __HAL_REMAPMEMORY_QUADSPI     __HAL_SYSCFG_REMAPMEMORY_QUADSPI
#define __HAL_FMC_BANK                __HAL_SYSCFG_FMC_BANK
#define __HAL_GET_FLAG                __HAL_SYSCFG_GET_FLAG
#define __HAL_CLEAR_FLAG              __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE      __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE     __HAL_SYSCFG_VREFINT_OUT_DISABLE
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

#define SYSCFG_FLAG_VREF_READY        SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48              RCC_FLAG_HSI48
#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
#define UFB_MODE_BitNumber            UFB_MODE_BIT_NUMBER
#define CMP_PD_BitNumber              CMP_PD_BIT_NUMBER

/**
 * @}
 */

/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
 * @{
 */
#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE

#define __HAL_ADC_GET_RESOLUTION              ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR_RK                     ADC_JSQR_RK
#define __HAL_ADC_CFGR_AWD1CH                 ADC_CFGR_AWD1CH_SHIFT
#define __HAL_ADC_CFGR_AWD23CR                ADC_CFGR_AWD23CR
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE   ADC_CFGR_INJECT_CONTEXT_QUEUE
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS  ADC_CFGR_INJECT_DISCCONTINUOUS
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS     ADC_CFGR_REG_DISCCONTINUOUS
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM      ADC_CFGR_DISCONTINUOUS_NUM
#define __HAL_ADC_CFGR_AUTOWAIT               ADC_CFGR_AUTOWAIT
#define __HAL_ADC_CFGR_CONTINUOUS             ADC_CFGR_CONTINUOUS
#define __HAL_ADC_CFGR_OVERRUN                ADC_CFGR_OVERRUN
#define __HAL_ADC_CFGR_DMACONTREQ             ADC_CFGR_DMACONTREQ
#define __HAL_ADC_CFGR_EXTSEL                 ADC_CFGR_EXTSEL_SET
#define __HAL_ADC_JSQR_JEXTSEL                ADC_JSQR_JEXTSEL_SET
#define __HAL_ADC_OFR_CHANNEL                 ADC_OFR_CHANNEL
#define __HAL_ADC_DIFSEL_CHANNEL              ADC_DIFSEL_CHANNEL
#define __HAL_ADC_CALFACT_DIFF_SET            ADC_CALFACT_DIFF_SET
#define __HAL_ADC_CALFACT_DIFF_GET            ADC_CALFACT_DIFF_GET
#define __HAL_ADC_TRX_HIGHTHRESHOLD           ADC_TRX_HIGHTHRESHOLD

#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION         ADC_OFFSET_SHIFT_RESOLUTION
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION  ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
#define __HAL_ADC_COMMON_REGISTER                 ADC_COMMON_REGISTER
#define __HAL_ADC_COMMON_CCR_MULTI                ADC_COMMON_CCR_MULTI
#define __HAL_ADC_MULTIMODE_IS_ENABLED            ADC_MULTIMODE_IS_ENABLE
#define __ADC_MULTIMODE_IS_ENABLED                ADC_MULTIMODE_IS_ENABLE
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
#define __HAL_ADC_COMMON_ADC_OTHER                ADC_COMMON_ADC_OTHER
#define __HAL_ADC_MULTI_SLAVE                     ADC_MULTI_SLAVE

#define __HAL_ADC_SQR1_L                ADC_SQR1_L_SHIFT
#define __HAL_ADC_JSQR_JL               ADC_JSQR_JL_SHIFT
#define __HAL_ADC_JSQR_RK_JL            ADC_JSQR_RK_JL
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
#define __HAL_ADC_CR1_SCAN              ADC_CR1_SCAN_SET
#define __HAL_ADC_CONVCYCLES_MAX_RANGE  ADC_CONVCYCLES_MAX_RANGE
#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
#define __HAL_ADC_GET_CLOCK_PRESCALER   ADC_GET_CLOCK_PRESCALER

#define __HAL_ADC_SQR1              ADC_SQR1
#define __HAL_ADC_SMPR1             ADC_SMPR1
#define __HAL_ADC_SMPR2             ADC_SMPR2
#define __HAL_ADC_SQR3_RK           ADC_SQR3_RK
#define __HAL_ADC_SQR2_RK           ADC_SQR2_RK
#define __HAL_ADC_SQR1_RK           ADC_SQR1_RK
#define __HAL_ADC_CR2_CONTINUOUS    ADC_CR2_CONTINUOUS
#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
#define __HAL_ADC_CR1_SCANCONV      ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection  ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq    ADC_CR2_DMAContReq
#define __HAL_ADC_GET_RESOLUTION    ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR              ADC_JSQR

#define __HAL_ADC_CHSELR_CHANNEL           ADC_CHSELR_CHANNEL
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
#define __HAL_ADC_CFGR1_AUTOOFF            ADC_CFGR1_AUTOOFF
#define __HAL_ADC_CFGR1_AUTOWAIT           ADC_CFGR1_AUTOWAIT
#define __HAL_ADC_CFGR1_CONTINUOUS         ADC_CFGR1_CONTINUOUS
#define __HAL_ADC_CFGR1_OVERRUN            ADC_CFGR1_OVERRUN
#define __HAL_ADC_CFGR1_SCANDIR            ADC_CFGR1_SCANDIR
#define __HAL_ADC_CFGR1_DMACONTREQ         ADC_CFGR1_DMACONTREQ

/**
 * @}
 */

/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
#define IS_DAC_GENERATE_WAVE     IS_DAC_WAVE

/**
 * @}
 */

/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_FREEZE_TIM1_DBGMCU   __HAL_DBGMCU_FREEZE_TIM1
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
#define __HAL_FREEZE_TIM2_DBGMCU   __HAL_DBGMCU_FREEZE_TIM2
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
#define __HAL_FREEZE_TIM3_DBGMCU   __HAL_DBGMCU_FREEZE_TIM3
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
#define __HAL_FREEZE_TIM4_DBGMCU   __HAL_DBGMCU_FREEZE_TIM4
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
#define __HAL_FREEZE_TIM5_DBGMCU   __HAL_DBGMCU_FREEZE_TIM5
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
#define __HAL_FREEZE_TIM6_DBGMCU   __HAL_DBGMCU_FREEZE_TIM6
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
#define __HAL_FREEZE_TIM7_DBGMCU   __HAL_DBGMCU_FREEZE_TIM7
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
#define __HAL_FREEZE_TIM8_DBGMCU   __HAL_DBGMCU_FREEZE_TIM8
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8

#define __HAL_FREEZE_TIM9_DBGMCU    __HAL_DBGMCU_FREEZE_TIM9
#define __HAL_UNFREEZE_TIM9_DBGMCU  __HAL_DBGMCU_UNFREEZE_TIM9
#define __HAL_FREEZE_TIM10_DBGMCU   __HAL_DBGMCU_FREEZE_TIM10
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
#define __HAL_FREEZE_TIM11_DBGMCU   __HAL_DBGMCU_FREEZE_TIM11
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
#define __HAL_FREEZE_TIM12_DBGMCU   __HAL_DBGMCU_FREEZE_TIM12
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
#define __HAL_FREEZE_TIM13_DBGMCU   __HAL_DBGMCU_FREEZE_TIM13
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
#define __HAL_FREEZE_TIM14_DBGMCU   __HAL_DBGMCU_FREEZE_TIM14
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
#define __HAL_FREEZE_CAN2_DBGMCU    __HAL_DBGMCU_FREEZE_CAN2
#define __HAL_UNFREEZE_CAN2_DBGMCU  __HAL_DBGMCU_UNFREEZE_CAN2

#define __HAL_FREEZE_TIM15_DBGMCU          __HAL_DBGMCU_FREEZE_TIM15
#define __HAL_UNFREEZE_TIM15_DBGMCU        __HAL_DBGMCU_UNFREEZE_TIM15
#define __HAL_FREEZE_TIM16_DBGMCU          __HAL_DBGMCU_FREEZE_TIM16
#define __HAL_UNFREEZE_TIM16_DBGMCU        __HAL_DBGMCU_UNFREEZE_TIM16
#define __HAL_FREEZE_TIM17_DBGMCU          __HAL_DBGMCU_FREEZE_TIM17
#define __HAL_UNFREEZE_TIM17_DBGMCU        __HAL_DBGMCU_UNFREEZE_TIM17
#define __HAL_FREEZE_RTC_DBGMCU            __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU          __HAL_DBGMCU_UNFREEZE_RTC
#define __HAL_FREEZE_WWDG_DBGMCU           __HAL_DBGMCU_FREEZE_WWDG
#define __HAL_UNFREEZE_WWDG_DBGMCU         __HAL_DBGMCU_UNFREEZE_WWDG
#define __HAL_FREEZE_IWDG_DBGMCU           __HAL_DBGMCU_FREEZE_IWDG
#define __HAL_UNFREEZE_IWDG_DBGMCU         __HAL_DBGMCU_UNFREEZE_IWDG
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU   __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU   __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU   __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
#define __HAL_FREEZE_CAN1_DBGMCU           __HAL_DBGMCU_FREEZE_CAN1
#define __HAL_UNFREEZE_CAN1_DBGMCU         __HAL_DBGMCU_UNFREEZE_CAN1
#define __HAL_FREEZE_LPTIM1_DBGMCU         __HAL_DBGMCU_FREEZE_LPTIM1
#define __HAL_UNFREEZE_LPTIM1_DBGMCU       __HAL_DBGMCU_UNFREEZE_LPTIM1
#define __HAL_FREEZE_LPTIM2_DBGMCU         __HAL_DBGMCU_FREEZE_LPTIM2
#define __HAL_UNFREEZE_LPTIM2_DBGMCU       __HAL_DBGMCU_UNFREEZE_LPTIM2

/**
 * @}
 */

/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
 * @{
 */
#if defined(STM32F3)
#define COMP_START __HAL_COMP_ENABLE
#define COMP_STOP  __HAL_COMP_DISABLE
#define COMP_LOCK  __HAL_COMP_LOCK

#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2)   ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2)   ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2)   ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2)   ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) \
  (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) \
  (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)                                   \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
                                              : __HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)                                   \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
                                              : __HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)                                   \
  (((__FLAG__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
                                          : __HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)                                   \
  (((__FLAG__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
                                          : __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() \
                                              : __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)                                     \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() \
                                              : __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)                                   \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() \
                                              : __HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)                                   \
  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() \
   : ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() \
                                              : __HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)                                   \
  (((__FLAG__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() \
                                          : __HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)                                   \
  (((__FLAG__) == COMP_EXTI_LINE_COMP1)   ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() \
   : ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() \
                                          : __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
#endif
#if defined(STM32F373xC) || defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : __HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : __HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : __HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif

#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE

#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro             */
/*       is COMP_FLAG_LOCK.                                                   */
/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
/*       argument.                                                            */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
 * @}
 */

#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
 * @{
 */
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT  HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
 * @}
 */
#endif

/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 * @{
 */

#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || ((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))

/**
 * @}
 */

/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
 * @{
 */

#define IS_WRPAREA          IS_OB_WRPAREA
#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
#define IS_TYPEERASE        IS_FLASH_TYPEERASE
#define IS_NBSECTORS        IS_FLASH_NBSECTORS
#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE

/**
 * @}
 */

/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_I2C_RESET_CR2      I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME          I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD     I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST         I2C_SPEED_FAST
#define __HAL_I2C_SPEED              I2C_SPEED
#define __HAL_I2C_7BIT_ADD_WRITE     I2C_7BIT_ADD_WRITE
#define __HAL_I2C_7BIT_ADD_READ      I2C_7BIT_ADD_READ
#define __HAL_I2C_10BIT_ADDRESS      I2C_10BIT_ADDRESS
#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
#define __HAL_I2C_10BIT_HEADER_READ  I2C_10BIT_HEADER_READ
#define __HAL_I2C_MEM_ADD_MSB        I2C_MEM_ADD_MSB
#define __HAL_I2C_MEM_ADD_LSB        I2C_MEM_ADD_LSB
#define __HAL_I2C_FREQRANGE          I2C_FREQRANGE
/**
 * @}
 */

/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
 * @{
 */

#define IS_I2S_INSTANCE     IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT

/**
 * @}
 */

/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
 * @{
 */

#define __IRDA_DISABLE __HAL_IRDA_DISABLE
#define __IRDA_ENABLE  __HAL_IRDA_ENABLE

#define __HAL_IRDA_GETCLOCKSOURCE   IRDA_GETCLOCKSOURCE
#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
#define __IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
#define __IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION

#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE

/**
 * @}
 */

/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
/**
 * @}
 */

/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_LPTIM_ENABLE_INTERRUPT  __HAL_LPTIM_ENABLE_IT
#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
#define __HAL_LPTIM_GET_ITSTATUS      __HAL_LPTIM_GET_IT_SOURCE

/**
 * @}
 */

/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
 * @{
 */
#define __OPAMP_CSR_OPAXPD               OPAMP_CSR_OPAXPD
#define __OPAMP_CSR_S3SELX               OPAMP_CSR_S3SELX
#define __OPAMP_CSR_S4SELX               OPAMP_CSR_S4SELX
#define __OPAMP_CSR_S5SELX               OPAMP_CSR_S5SELX
#define __OPAMP_CSR_S6SELX               OPAMP_CSR_S6SELX
#define __OPAMP_CSR_OPAXCAL_L            OPAMP_CSR_OPAXCAL_L
#define __OPAMP_CSR_OPAXCAL_H            OPAMP_CSR_OPAXCAL_H
#define __OPAMP_CSR_OPAXLPM              OPAMP_CSR_OPAXLPM
#define __OPAMP_CSR_ALL_SWITCHES         OPAMP_CSR_ALL_SWITCHES
#define __OPAMP_CSR_ANAWSELX             OPAMP_CSR_ANAWSELX
#define __OPAMP_CSR_OPAXCALOUT           OPAMP_CSR_OPAXCALOUT
#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
#define __OPAMP_OFFSET_TRIM_SET          OPAMP_OFFSET_TRIM_SET

/**
 * @}
 */

/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_PVD_EVENT_DISABLE               __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PVD_EVENT_ENABLE                __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PVM_EVENT_DISABLE               __HAL_PWR_PVM_EVENT_DISABLE
#define __HAL_PVM_EVENT_ENABLE                __HAL_PWR_PVM_EVENT_ENABLE
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE  __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE  __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE   __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
#define __HAL_PWR_INTERNALWAKEUP_DISABLE      HAL_PWREx_DisableInternalWakeUpLine
#define __HAL_PWR_INTERNALWAKEUP_ENABLE       HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE  HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() \
  do {                                          \
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();   \
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();  \
  } while (0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE            __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE             __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() \
  do {                          \
    HAL_PWREx_DisablePVM1();    \
    HAL_PWREx_DisablePVM2();    \
    HAL_PWREx_DisablePVM3();    \
    HAL_PWREx_DisablePVM4();    \
  } while (0)
#define __HAL_PWR_PVM_ENABLE() \
  do {                         \
    HAL_PWREx_EnablePVM1();    \
    HAL_PWREx_EnablePVM2();    \
    HAL_PWREx_EnablePVM3();    \
    HAL_PWREx_EnablePVM4();    \
  } while (0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE        HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE         HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE                       HAL_PWREx_DisableVddIO2
#define __HAL_PWR_VDDIO2_ENABLE                        HAL_PWREx_EnableVddIO2
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER       __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_VDDUSB_DISABLE                       HAL_PWREx_DisableVddUSB
#define __HAL_PWR_VDDUSB_ENABLE                        HAL_PWREx_EnableVddUSB

#if defined(STM32F4)
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_ENABLE_IT()
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)    __HAL_PWR_PVD_EXTI_DISABLE_IT()
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)      __HAL_PWR_PVD_EXTI_GET_FLAG()
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)    __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
#else
#define __HAL_PVD_EXTI_CLEAR_FLAG    __HAL_PWR_PVD_EXTI_CLEAR_FLAG
#define __HAL_PVD_EXTI_DISABLE_IT    __HAL_PWR_PVD_EXTI_DISABLE_IT
#define __HAL_PVD_EXTI_ENABLE_IT     __HAL_PWR_PVD_EXTI_ENABLE_IT
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
#define __HAL_PVD_EXTI_GET_FLAG      __HAL_PWR_PVD_EXTI_GET_FLAG
#endif /* STM32F4 */
/**
 * @}
 */

/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
 * @{
 */

#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI

#define HAL_RCC_CCSCallback            HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd) == ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

#define __ADC_CLK_DISABLE           __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE            __HAL_RCC_ADC_CLK_ENABLE
#define __ADC_CLK_SLEEP_DISABLE     __HAL_RCC_ADC_CLK_SLEEP_DISABLE
#define __ADC_CLK_SLEEP_ENABLE      __HAL_RCC_ADC_CLK_SLEEP_ENABLE
#define __ADC_FORCE_RESET           __HAL_RCC_ADC_FORCE_RESET
#define __ADC_RELEASE_RESET         __HAL_RCC_ADC_RELEASE_RESET
#define __ADC1_CLK_DISABLE          __HAL_RCC_ADC1_CLK_DISABLE
#define __ADC1_CLK_ENABLE           __HAL_RCC_ADC1_CLK_ENABLE
#define __ADC1_FORCE_RESET          __HAL_RCC_ADC1_FORCE_RESET
#define __ADC1_RELEASE_RESET        __HAL_RCC_ADC1_RELEASE_RESET
#define __ADC1_CLK_SLEEP_ENABLE     __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
#define __ADC1_CLK_SLEEP_DISABLE    __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
#define __ADC2_CLK_DISABLE          __HAL_RCC_ADC2_CLK_DISABLE
#define __ADC2_CLK_ENABLE           __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET          __HAL_RCC_ADC2_FORCE_RESET
#define __ADC2_RELEASE_RESET        __HAL_RCC_ADC2_RELEASE_RESET
#define __ADC3_CLK_DISABLE          __HAL_RCC_ADC3_CLK_DISABLE
#define __ADC3_CLK_ENABLE           __HAL_RCC_ADC3_CLK_ENABLE
#define __ADC3_FORCE_RESET          __HAL_RCC_ADC3_FORCE_RESET
#define __ADC3_RELEASE_RESET        __HAL_RCC_ADC3_RELEASE_RESET
#define __AES_CLK_DISABLE           __HAL_RCC_AES_CLK_DISABLE
#define __AES_CLK_ENABLE            __HAL_RCC_AES_CLK_ENABLE
#define __AES_CLK_SLEEP_DISABLE     __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __AES_CLK_SLEEP_ENABLE      __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __AES_FORCE_RESET           __HAL_RCC_AES_FORCE_RESET
#define __AES_RELEASE_RESET         __HAL_RCC_AES_RELEASE_RESET
#define __CRYP_CLK_SLEEP_ENABLE     __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
#define __CRYP_CLK_SLEEP_DISABLE    __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
#define __CRYP_CLK_ENABLE           __HAL_RCC_CRYP_CLK_ENABLE
#define __CRYP_CLK_DISABLE          __HAL_RCC_CRYP_CLK_DISABLE
#define __CRYP_FORCE_RESET          __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_RELEASE_RESET        __HAL_RCC_CRYP_RELEASE_RESET
#define __AFIO_CLK_DISABLE          __HAL_RCC_AFIO_CLK_DISABLE
#define __AFIO_CLK_ENABLE           __HAL_RCC_AFIO_CLK_ENABLE
#define __AFIO_FORCE_RESET          __HAL_RCC_AFIO_FORCE_RESET
#define __AFIO_RELEASE_RESET        __HAL_RCC_AFIO_RELEASE_RESET
#define __AHB_FORCE_RESET           __HAL_RCC_AHB_FORCE_RESET
#define __AHB_RELEASE_RESET         __HAL_RCC_AHB_RELEASE_RESET
#define __AHB1_FORCE_RESET          __HAL_RCC_AHB1_FORCE_RESET
#define __AHB1_RELEASE_RESET        __HAL_RCC_AHB1_RELEASE_RESET
#define __AHB2_FORCE_RESET          __HAL_RCC_AHB2_FORCE_RESET
#define __AHB2_RELEASE_RESET        __HAL_RCC_AHB2_RELEASE_RESET
#define __AHB3_FORCE_RESET          __HAL_RCC_AHB3_FORCE_RESET
#define __AHB3_RELEASE_RESET        __HAL_RCC_AHB3_RELEASE_RESET
#define __APB1_FORCE_RESET          __HAL_RCC_APB1_FORCE_RESET
#define __APB1_RELEASE_RESET        __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET          __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET        __HAL_RCC_APB2_RELEASE_RESET
#define __BKP_CLK_DISABLE           __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE            __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET           __HAL_RCC_BKP_FORCE_RESET
#define __BKP_RELEASE_RESET         __HAL_RCC_BKP_RELEASE_RESET
#define __CAN1_CLK_DISABLE          __HAL_RCC_CAN1_CLK_DISABLE
#define __CAN1_CLK_ENABLE           __HAL_RCC_CAN1_CLK_ENABLE
#define __CAN1_CLK_SLEEP_DISABLE    __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
#define __CAN1_CLK_SLEEP_ENABLE     __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
#define __CAN1_FORCE_RESET          __HAL_RCC_CAN1_FORCE_RESET
#define __CAN1_RELEASE_RESET        __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN_CLK_DISABLE           __HAL_RCC_CAN1_CLK_DISABLE
#define __CAN_CLK_ENABLE            __HAL_RCC_CAN1_CLK_ENABLE
#define __CAN_FORCE_RESET           __HAL_RCC_CAN1_FORCE_RESET
#define __CAN_RELEASE_RESET         __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN2_CLK_DISABLE          __HAL_RCC_CAN2_CLK_DISABLE
#define __CAN2_CLK_ENABLE           __HAL_RCC_CAN2_CLK_ENABLE
#define __CAN2_FORCE_RESET          __HAL_RCC_CAN2_FORCE_RESET
#define __CAN2_RELEASE_RESET        __HAL_RCC_CAN2_RELEASE_RESET
#define __CEC_CLK_DISABLE           __HAL_RCC_CEC_CLK_DISABLE
#define __CEC_CLK_ENABLE            __HAL_RCC_CEC_CLK_ENABLE
#define __COMP_CLK_DISABLE          __HAL_RCC_COMP_CLK_DISABLE
#define __COMP_CLK_ENABLE           __HAL_RCC_COMP_CLK_ENABLE
#define __COMP_FORCE_RESET          __HAL_RCC_COMP_FORCE_RESET
#define __COMP_RELEASE_RESET        __HAL_RCC_COMP_RELEASE_RESET
#define __COMP_CLK_SLEEP_ENABLE     __HAL_RCC_COMP_CLK_SLEEP_ENABLE
#define __COMP_CLK_SLEEP_DISABLE    __HAL_RCC_COMP_CLK_SLEEP_DISABLE
#define __CEC_FORCE_RESET           __HAL_RCC_CEC_FORCE_RESET
#define __CEC_RELEASE_RESET         __HAL_RCC_CEC_RELEASE_RESET
#define __CRC_CLK_DISABLE           __HAL_RCC_CRC_CLK_DISABLE
#define __CRC_CLK_ENABLE            __HAL_RCC_CRC_CLK_ENABLE
#define __CRC_CLK_SLEEP_DISABLE     __HAL_RCC_CRC_CLK_SLEEP_DISABLE
#define __CRC_CLK_SLEEP_ENABLE      __HAL_RCC_CRC_CLK_SLEEP_ENABLE
#define __CRC_FORCE_RESET           __HAL_RCC_CRC_FORCE_RESET
#define __CRC_RELEASE_RESET         __HAL_RCC_CRC_RELEASE_RESET
#define __DAC_CLK_DISABLE           __HAL_RCC_DAC_CLK_DISABLE
#define __DAC_CLK_ENABLE            __HAL_RCC_DAC_CLK_ENABLE
#define __DAC_FORCE_RESET           __HAL_RCC_DAC_FORCE_RESET
#define __DAC_RELEASE_RESET         __HAL_RCC_DAC_RELEASE_RESET
#define __DAC1_CLK_DISABLE          __HAL_RCC_DAC1_CLK_DISABLE
#define __DAC1_CLK_ENABLE           __HAL_RCC_DAC1_CLK_ENABLE
#define __DAC1_CLK_SLEEP_DISABLE    __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
#define __DAC1_CLK_SLEEP_ENABLE     __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
#define __DAC1_FORCE_RESET          __HAL_RCC_DAC1_FORCE_RESET
#define __DAC1_RELEASE_RESET        __HAL_RCC_DAC1_RELEASE_RESET
#define __DBGMCU_CLK_ENABLE         __HAL_RCC_DBGMCU_CLK_ENABLE
#define __DBGMCU_CLK_DISABLE        __HAL_RCC_DBGMCU_CLK_DISABLE
#define __DBGMCU_FORCE_RESET        __HAL_RCC_DBGMCU_FORCE_RESET
#define __DBGMCU_RELEASE_RESET      __HAL_RCC_DBGMCU_RELEASE_RESET
#define __DFSDM_CLK_DISABLE         __HAL_RCC_DFSDM_CLK_DISABLE
#define __DFSDM_CLK_ENABLE          __HAL_RCC_DFSDM_CLK_ENABLE
#define __DFSDM_CLK_SLEEP_DISABLE   __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
#define __DFSDM_CLK_SLEEP_ENABLE    __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
#define __DFSDM_FORCE_RESET         __HAL_RCC_DFSDM_FORCE_RESET
#define __DFSDM_RELEASE_RESET       __HAL_RCC_DFSDM_RELEASE_RESET
#define __DMA1_CLK_DISABLE          __HAL_RCC_DMA1_CLK_DISABLE
#define __DMA1_CLK_ENABLE           __HAL_RCC_DMA1_CLK_ENABLE
#define __DMA1_CLK_SLEEP_DISABLE    __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
#define __DMA1_CLK_SLEEP_ENABLE     __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
#define __DMA1_FORCE_RESET          __HAL_RCC_DMA1_FORCE_RESET
#define __DMA1_RELEASE_RESET        __HAL_RCC_DMA1_RELEASE_RESET
#define __DMA2_CLK_DISABLE          __HAL_RCC_DMA2_CLK_DISABLE
#define __DMA2_CLK_ENABLE           __HAL_RCC_DMA2_CLK_ENABLE
#define __DMA2_CLK_SLEEP_DISABLE    __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
#define __DMA2_CLK_SLEEP_ENABLE     __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
#define __DMA2_FORCE_RESET          __HAL_RCC_DMA2_FORCE_RESET
#define __DMA2_RELEASE_RESET        __HAL_RCC_DMA2_RELEASE_RESET
#define __ETHMAC_CLK_DISABLE        __HAL_RCC_ETHMAC_CLK_DISABLE
#define __ETHMAC_CLK_ENABLE         __HAL_RCC_ETHMAC_CLK_ENABLE
#define __ETHMAC_FORCE_RESET        __HAL_RCC_ETHMAC_FORCE_RESET
#define __ETHMAC_RELEASE_RESET      __HAL_RCC_ETHMAC_RELEASE_RESET
#define __ETHMACRX_CLK_DISABLE      __HAL_RCC_ETHMACRX_CLK_DISABLE
#define __ETHMACRX_CLK_ENABLE       __HAL_RCC_ETHMACRX_CLK_ENABLE
#define __ETHMACTX_CLK_DISABLE      __HAL_RCC_ETHMACTX_CLK_DISABLE
#define __ETHMACTX_CLK_ENABLE       __HAL_RCC_ETHMACTX_CLK_ENABLE
#define __FIREWALL_CLK_DISABLE      __HAL_RCC_FIREWALL_CLK_DISABLE
#define __FIREWALL_CLK_ENABLE       __HAL_RCC_FIREWALL_CLK_ENABLE
#define __FLASH_CLK_DISABLE         __HAL_RCC_FLASH_CLK_DISABLE
#define __FLASH_CLK_ENABLE          __HAL_RCC_FLASH_CLK_ENABLE
#define __FLASH_CLK_SLEEP_DISABLE   __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
#define __FLASH_CLK_SLEEP_ENABLE    __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
#define __FLASH_FORCE_RESET         __HAL_RCC_FLASH_FORCE_RESET
#define __FLASH_RELEASE_RESET       __HAL_RCC_FLASH_RELEASE_RESET
#define __FLITF_CLK_DISABLE         __HAL_RCC_FLITF_CLK_DISABLE
#define __FLITF_CLK_ENABLE          __HAL_RCC_FLITF_CLK_ENABLE
#define __FLITF_FORCE_RESET         __HAL_RCC_FLITF_FORCE_RESET
#define __FLITF_RELEASE_RESET       __HAL_RCC_FLITF_RELEASE_RESET
#define __FLITF_CLK_SLEEP_ENABLE    __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
#define __FLITF_CLK_SLEEP_DISABLE   __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
#define __FMC_CLK_DISABLE           __HAL_RCC_FMC_CLK_DISABLE
#define __FMC_CLK_ENABLE            __HAL_RCC_FMC_CLK_ENABLE
#define __FMC_CLK_SLEEP_DISABLE     __HAL_RCC_FMC_CLK_SLEEP_DISABLE
#define __FMC_CLK_SLEEP_ENABLE      __HAL_RCC_FMC_CLK_SLEEP_ENABLE
#define __FMC_FORCE_RESET           __HAL_RCC_FMC_FORCE_RESET
#define __FMC_RELEASE_RESET         __HAL_RCC_FMC_RELEASE_RESET
#define __FSMC_CLK_DISABLE          __HAL_RCC_FSMC_CLK_DISABLE
#define __FSMC_CLK_ENABLE           __HAL_RCC_FSMC_CLK_ENABLE
#define __GPIOA_CLK_DISABLE         __HAL_RCC_GPIOA_CLK_DISABLE
#define __GPIOA_CLK_ENABLE          __HAL_RCC_GPIOA_CLK_ENABLE
#define __GPIOA_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
#define __GPIOA_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
#define __GPIOA_FORCE_RESET         __HAL_RCC_GPIOA_FORCE_RESET
#define __GPIOA_RELEASE_RESET       __HAL_RCC_GPIOA_RELEASE_RESET
#define __GPIOB_CLK_DISABLE         __HAL_RCC_GPIOB_CLK_DISABLE
#define __GPIOB_CLK_ENABLE          __HAL_RCC_GPIOB_CLK_ENABLE
#define __GPIOB_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
#define __GPIOB_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
#define __GPIOB_FORCE_RESET         __HAL_RCC_GPIOB_FORCE_RESET
#define __GPIOB_RELEASE_RESET       __HAL_RCC_GPIOB_RELEASE_RESET
#define __GPIOC_CLK_DISABLE         __HAL_RCC_GPIOC_CLK_DISABLE
#define __GPIOC_CLK_ENABLE          __HAL_RCC_GPIOC_CLK_ENABLE
#define __GPIOC_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
#define __GPIOC_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
#define __GPIOC_FORCE_RESET         __HAL_RCC_GPIOC_FORCE_RESET
#define __GPIOC_RELEASE_RESET       __HAL_RCC_GPIOC_RELEASE_RESET
#define __GPIOD_CLK_DISABLE         __HAL_RCC_GPIOD_CLK_DISABLE
#define __GPIOD_CLK_ENABLE          __HAL_RCC_GPIOD_CLK_ENABLE
#define __GPIOD_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
#define __GPIOD_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
#define __GPIOD_FORCE_RESET         __HAL_RCC_GPIOD_FORCE_RESET
#define __GPIOD_RELEASE_RESET       __HAL_RCC_GPIOD_RELEASE_RESET
#define __GPIOE_CLK_DISABLE         __HAL_RCC_GPIOE_CLK_DISABLE
#define __GPIOE_CLK_ENABLE          __HAL_RCC_GPIOE_CLK_ENABLE
#define __GPIOE_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
#define __GPIOE_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
#define __GPIOE_FORCE_RESET         __HAL_RCC_GPIOE_FORCE_RESET
#define __GPIOE_RELEASE_RESET       __HAL_RCC_GPIOE_RELEASE_RESET
#define __GPIOF_CLK_DISABLE         __HAL_RCC_GPIOF_CLK_DISABLE
#define __GPIOF_CLK_ENABLE          __HAL_RCC_GPIOF_CLK_ENABLE
#define __GPIOF_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
#define __GPIOF_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
#define __GPIOF_FORCE_RESET         __HAL_RCC_GPIOF_FORCE_RESET
#define __GPIOF_RELEASE_RESET       __HAL_RCC_GPIOF_RELEASE_RESET
#define __GPIOG_CLK_DISABLE         __HAL_RCC_GPIOG_CLK_DISABLE
#define __GPIOG_CLK_ENABLE          __HAL_RCC_GPIOG_CLK_ENABLE
#define __GPIOG_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
#define __GPIOG_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
#define __GPIOG_FORCE_RESET         __HAL_RCC_GPIOG_FORCE_RESET
#define __GPIOG_RELEASE_RESET       __HAL_RCC_GPIOG_RELEASE_RESET
#define __GPIOH_CLK_DISABLE         __HAL_RCC_GPIOH_CLK_DISABLE
#define __GPIOH_CLK_ENABLE          __HAL_RCC_GPIOH_CLK_ENABLE
#define __GPIOH_CLK_SLEEP_DISABLE   __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
#define __GPIOH_CLK_SLEEP_ENABLE    __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
#define __GPIOH_FORCE_RESET         __HAL_RCC_GPIOH_FORCE_RESET
#define __GPIOH_RELEASE_RESET       __HAL_RCC_GPIOH_RELEASE_RESET
#define __I2C1_CLK_DISABLE          __HAL_RCC_I2C1_CLK_DISABLE
#define __I2C1_CLK_ENABLE           __HAL_RCC_I2C1_CLK_ENABLE
#define __I2C1_CLK_SLEEP_DISABLE    __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
#define __I2C1_CLK_SLEEP_ENABLE     __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
#define __I2C1_FORCE_RESET          __HAL_RCC_I2C1_FORCE_RESET
#define __I2C1_RELEASE_RESET        __HAL_RCC_I2C1_RELEASE_RESET
#define __I2C2_CLK_DISABLE          __HAL_RCC_I2C2_CLK_DISABLE
#define __I2C2_CLK_ENABLE           __HAL_RCC_I2C2_CLK_ENABLE
#define __I2C2_CLK_SLEEP_DISABLE    __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
#define __I2C2_CLK_SLEEP_ENABLE     __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
#define __I2C2_FORCE_RESET          __HAL_RCC_I2C2_FORCE_RESET
#define __I2C2_RELEASE_RESET        __HAL_RCC_I2C2_RELEASE_RESET
#define __I2C3_CLK_DISABLE          __HAL_RCC_I2C3_CLK_DISABLE
#define __I2C3_CLK_ENABLE           __HAL_RCC_I2C3_CLK_ENABLE
#define __I2C3_CLK_SLEEP_DISABLE    __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
#define __I2C3_CLK_SLEEP_ENABLE     __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
#define __I2C3_FORCE_RESET          __HAL_RCC_I2C3_FORCE_RESET
#define __I2C3_RELEASE_RESET        __HAL_RCC_I2C3_RELEASE_RESET
#define __LCD_CLK_DISABLE           __HAL_RCC_LCD_CLK_DISABLE
#define __LCD_CLK_ENABLE            __HAL_RCC_LCD_CLK_ENABLE
#define __LCD_CLK_SLEEP_DISABLE     __HAL_RCC_LCD_CLK_SLEEP_DISABLE
#define __LCD_CLK_SLEEP_ENABLE      __HAL_RCC_LCD_CLK_SLEEP_ENABLE
#define __LCD_FORCE_RESET           __HAL_RCC_LCD_FORCE_RESET
#define __LCD_RELEASE_RESET         __HAL_RCC_LCD_RELEASE_RESET
#define __LPTIM1_CLK_DISABLE        __HAL_RCC_LPTIM1_CLK_DISABLE
#define __LPTIM1_CLK_ENABLE         __HAL_RCC_LPTIM1_CLK_ENABLE
#define __LPTIM1_CLK_SLEEP_DISABLE  __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
#define __LPTIM1_CLK_SLEEP_ENABLE   __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
#define __LPTIM1_FORCE_RESET        __HAL_RCC_LPTIM1_FORCE_RESET
#define __LPTIM1_RELEASE_RESET      __HAL_RCC_LPTIM1_RELEASE_RESET
#define __LPTIM2_CLK_DISABLE        __HAL_RCC_LPTIM2_CLK_DISABLE
#define __LPTIM2_CLK_ENABLE         __HAL_RCC_LPTIM2_CLK_ENABLE
#define __LPTIM2_CLK_SLEEP_DISABLE  __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
#define __LPTIM2_CLK_SLEEP_ENABLE   __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
#define __LPTIM2_FORCE_RESET        __HAL_RCC_LPTIM2_FORCE_RESET
#define __LPTIM2_RELEASE_RESET      __HAL_RCC_LPTIM2_RELEASE_RESET
#define __LPUART1_CLK_DISABLE       __HAL_RCC_LPUART1_CLK_DISABLE
#define __LPUART1_CLK_ENABLE        __HAL_RCC_LPUART1_CLK_ENABLE
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
#define __LPUART1_CLK_SLEEP_ENABLE  __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
#define __LPUART1_FORCE_RESET       __HAL_RCC_LPUART1_FORCE_RESET
#define __LPUART1_RELEASE_RESET     __HAL_RCC_LPUART1_RELEASE_RESET
#define __OPAMP_CLK_DISABLE         __HAL_RCC_OPAMP_CLK_DISABLE
#define __OPAMP_CLK_ENABLE          __HAL_RCC_OPAMP_CLK_ENABLE
#define __OPAMP_CLK_SLEEP_DISABLE   __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
#define __OPAMP_CLK_SLEEP_ENABLE    __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
#define __OPAMP_FORCE_RESET         __HAL_RCC_OPAMP_FORCE_RESET
#define __OPAMP_RELEASE_RESET       __HAL_RCC_OPAMP_RELEASE_RESET
#define __OTGFS_CLK_DISABLE         __HAL_RCC_OTGFS_CLK_DISABLE
#define __OTGFS_CLK_ENABLE          __HAL_RCC_OTGFS_CLK_ENABLE
#define __OTGFS_CLK_SLEEP_DISABLE   __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
#define __OTGFS_CLK_SLEEP_ENABLE    __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
#define __OTGFS_FORCE_RESET         __HAL_RCC_OTGFS_FORCE_RESET
#define __OTGFS_RELEASE_RESET       __HAL_RCC_OTGFS_RELEASE_RESET
#define __PWR_CLK_DISABLE           __HAL_RCC_PWR_CLK_DISABLE
#define __PWR_CLK_ENABLE            __HAL_RCC_PWR_CLK_ENABLE
#define __PWR_CLK_SLEEP_DISABLE     __HAL_RCC_PWR_CLK_SLEEP_DISABLE
#define __PWR_CLK_SLEEP_ENABLE      __HAL_RCC_PWR_CLK_SLEEP_ENABLE
#define __PWR_FORCE_RESET           __HAL_RCC_PWR_FORCE_RESET
#define __PWR_RELEASE_RESET         __HAL_RCC_PWR_RELEASE_RESET
#define __QSPI_CLK_DISABLE          __HAL_RCC_QSPI_CLK_DISABLE
#define __QSPI_CLK_ENABLE           __HAL_RCC_QSPI_CLK_ENABLE
#define __QSPI_CLK_SLEEP_DISABLE    __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
#define __QSPI_CLK_SLEEP_ENABLE     __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
#define __QSPI_FORCE_RESET          __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET        __HAL_RCC_QSPI_RELEASE_RESET
#define __RNG_CLK_DISABLE           __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE            __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE     __HAL_RCC_RNG_CLK_SLEEP_DISABLE
#define __RNG_CLK_SLEEP_ENABLE      __HAL_RCC_RNG_CLK_SLEEP_ENABLE
#define __RNG_FORCE_RESET           __HAL_RCC_RNG_FORCE_RESET
#define __RNG_RELEASE_RESET         __HAL_RCC_RNG_RELEASE_RESET
#define __SAI1_CLK_DISABLE          __HAL_RCC_SAI1_CLK_DISABLE
#define __SAI1_CLK_ENABLE           __HAL_RCC_SAI1_CLK_ENABLE
#define __SAI1_CLK_SLEEP_DISABLE    __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
#define __SAI1_CLK_SLEEP_ENABLE     __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
#define __SAI1_FORCE_RESET          __HAL_RCC_SAI1_FORCE_RESET
#define __SAI1_RELEASE_RESET        __HAL_RCC_SAI1_RELEASE_RESET
#define __SAI2_CLK_DISABLE          __HAL_RCC_SAI2_CLK_DISABLE
#define __SAI2_CLK_ENABLE           __HAL_RCC_SAI2_CLK_ENABLE
#define __SAI2_CLK_SLEEP_DISABLE    __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
#define __SAI2_CLK_SLEEP_ENABLE     __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
#define __SAI2_FORCE_RESET          __HAL_RCC_SAI2_FORCE_RESET
#define __SAI2_RELEASE_RESET        __HAL_RCC_SAI2_RELEASE_RESET
#define __SDIO_CLK_DISABLE          __HAL_RCC_SDIO_CLK_DISABLE
#define __SDIO_CLK_ENABLE           __HAL_RCC_SDIO_CLK_ENABLE
#define __SDMMC_CLK_DISABLE         __HAL_RCC_SDMMC_CLK_DISABLE
#define __SDMMC_CLK_ENABLE          __HAL_RCC_SDMMC_CLK_ENABLE
#define __SDMMC_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
#define __SDMMC_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
#define __SDMMC_FORCE_RESET         __HAL_RCC_SDMMC_FORCE_RESET
#define __SDMMC_RELEASE_RESET       __HAL_RCC_SDMMC_RELEASE_RESET
#define __SPI1_CLK_DISABLE          __HAL_RCC_SPI1_CLK_DISABLE
#define __SPI1_CLK_ENABLE           __HAL_RCC_SPI1_CLK_ENABLE
#define __SPI1_CLK_SLEEP_DISABLE    __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
#define __SPI1_CLK_SLEEP_ENABLE     __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
#define __SPI1_FORCE_RESET          __HAL_RCC_SPI1_FORCE_RESET
#define __SPI1_RELEASE_RESET        __HAL_RCC_SPI1_RELEASE_RESET
#define __SPI2_CLK_DISABLE          __HAL_RCC_SPI2_CLK_DISABLE
#define __SPI2_CLK_ENABLE           __HAL_RCC_SPI2_CLK_ENABLE
#define __SPI2_CLK_SLEEP_DISABLE    __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
#define __SPI2_CLK_SLEEP_ENABLE     __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
#define __SPI2_FORCE_RESET          __HAL_RCC_SPI2_FORCE_RESET
#define __SPI2_RELEASE_RESET        __HAL_RCC_SPI2_RELEASE_RESET
#define __SPI3_CLK_DISABLE          __HAL_RCC_SPI3_CLK_DISABLE
#define __SPI3_CLK_ENABLE           __HAL_RCC_SPI3_CLK_ENABLE
#define __SPI3_CLK_SLEEP_DISABLE    __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
#define __SPI3_CLK_SLEEP_ENABLE     __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
#define __SPI3_FORCE_RESET          __HAL_RCC_SPI3_FORCE_RESET
#define __SPI3_RELEASE_RESET        __HAL_RCC_SPI3_RELEASE_RESET
#define __SRAM_CLK_DISABLE          __HAL_RCC_SRAM_CLK_DISABLE
#define __SRAM_CLK_ENABLE           __HAL_RCC_SRAM_CLK_ENABLE
#define __SRAM1_CLK_SLEEP_DISABLE   __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
#define __SRAM1_CLK_SLEEP_ENABLE    __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
#define __SRAM2_CLK_SLEEP_DISABLE   __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
#define __SRAM2_CLK_SLEEP_ENABLE    __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
#define __SWPMI1_CLK_DISABLE        __HAL_RCC_SWPMI1_CLK_DISABLE
#define __SWPMI1_CLK_ENABLE         __HAL_RCC_SWPMI1_CLK_ENABLE
#define __SWPMI1_CLK_SLEEP_DISABLE  __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
#define __SWPMI1_CLK_SLEEP_ENABLE   __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
#define __SWPMI1_FORCE_RESET        __HAL_RCC_SWPMI1_FORCE_RESET
#define __SWPMI1_RELEASE_RESET      __HAL_RCC_SWPMI1_RELEASE_RESET
#define __SYSCFG_CLK_DISABLE        __HAL_RCC_SYSCFG_CLK_DISABLE
#define __SYSCFG_CLK_ENABLE         __HAL_RCC_SYSCFG_CLK_ENABLE
#define __SYSCFG_CLK_SLEEP_DISABLE  __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
#define __SYSCFG_CLK_SLEEP_ENABLE   __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
#define __SYSCFG_FORCE_RESET        __HAL_RCC_SYSCFG_FORCE_RESET
#define __SYSCFG_RELEASE_RESET      __HAL_RCC_SYSCFG_RELEASE_RESET
#define __TIM1_CLK_DISABLE          __HAL_RCC_TIM1_CLK_DISABLE
#define __TIM1_CLK_ENABLE           __HAL_RCC_TIM1_CLK_ENABLE
#define __TIM1_CLK_SLEEP_DISABLE    __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
#define __TIM1_CLK_SLEEP_ENABLE     __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
#define __TIM1_FORCE_RESET          __HAL_RCC_TIM1_FORCE_RESET
#define __TIM1_RELEASE_RESET        __HAL_RCC_TIM1_RELEASE_RESET
#define __TIM10_CLK_DISABLE         __HAL_RCC_TIM10_CLK_DISABLE
#define __TIM10_CLK_ENABLE          __HAL_RCC_TIM10_CLK_ENABLE
#define __TIM10_FORCE_RESET         __HAL_RCC_TIM10_FORCE_RESET
#define __TIM10_RELEASE_RESET       __HAL_RCC_TIM10_RELEASE_RESET
#define __TIM11_CLK_DISABLE         __HAL_RCC_TIM11_CLK_DISABLE
#define __TIM11_CLK_ENABLE          __HAL_RCC_TIM11_CLK_ENABLE
#define __TIM11_FORCE_RESET         __HAL_RCC_TIM11_FORCE_RESET
#define __TIM11_RELEASE_RESET       __HAL_RCC_TIM11_RELEASE_RESET
#define __TIM12_CLK_DISABLE         __HAL_RCC_TIM12_CLK_DISABLE
#define __TIM12_CLK_ENABLE          __HAL_RCC_TIM12_CLK_ENABLE
#define __TIM12_FORCE_RESET         __HAL_RCC_TIM12_FORCE_RESET
#define __TIM12_RELEASE_RESET       __HAL_RCC_TIM12_RELEASE_RESET
#define __TIM13_CLK_DISABLE         __HAL_RCC_TIM13_CLK_DISABLE
#define __TIM13_CLK_ENABLE          __HAL_RCC_TIM13_CLK_ENABLE
#define __TIM13_FORCE_RESET         __HAL_RCC_TIM13_FORCE_RESET
#define __TIM13_RELEASE_RESET       __HAL_RCC_TIM13_RELEASE_RESET
#define __TIM14_CLK_DISABLE         __HAL_RCC_TIM14_CLK_DISABLE
#define __TIM14_CLK_ENABLE          __HAL_RCC_TIM14_CLK_ENABLE
#define __TIM14_FORCE_RESET         __HAL_RCC_TIM14_FORCE_RESET
#define __TIM14_RELEASE_RESET       __HAL_RCC_TIM14_RELEASE_RESET
#define __TIM15_CLK_DISABLE         __HAL_RCC_TIM15_CLK_DISABLE
#define __TIM15_CLK_ENABLE          __HAL_RCC_TIM15_CLK_ENABLE
#define __TIM15_CLK_SLEEP_DISABLE   __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
#define __TIM15_CLK_SLEEP_ENABLE    __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
#define __TIM15_FORCE_RESET         __HAL_RCC_TIM15_FORCE_RESET
#define __TIM15_RELEASE_RESET       __HAL_RCC_TIM15_RELEASE_RESET
#define __TIM16_CLK_DISABLE         __HAL_RCC_TIM16_CLK_DISABLE
#define __TIM16_CLK_ENABLE          __HAL_RCC_TIM16_CLK_ENABLE
#define __TIM16_CLK_SLEEP_DISABLE   __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
#define __TIM16_CLK_SLEEP_ENABLE    __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
#define __TIM16_FORCE_RESET         __HAL_RCC_TIM16_FORCE_RESET
#define __TIM16_RELEASE_RESET       __HAL_RCC_TIM16_RELEASE_RESET
#define __TIM17_CLK_DISABLE         __HAL_RCC_TIM17_CLK_DISABLE
#define __TIM17_CLK_ENABLE          __HAL_RCC_TIM17_CLK_ENABLE
#define __TIM17_CLK_SLEEP_DISABLE   __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
#define __TIM17_CLK_SLEEP_ENABLE    __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
#define __TIM17_FORCE_RESET         __HAL_RCC_TIM17_FORCE_RESET
#define __TIM17_RELEASE_RESET       __HAL_RCC_TIM17_RELEASE_RESET
#define __TIM2_CLK_DISABLE          __HAL_RCC_TIM2_CLK_DISABLE
#define __TIM2_CLK_ENABLE           __HAL_RCC_TIM2_CLK_ENABLE
#define __TIM2_CLK_SLEEP_DISABLE    __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
#define __TIM2_CLK_SLEEP_ENABLE     __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
#define __TIM2_FORCE_RESET          __HAL_RCC_TIM2_FORCE_RESET
#define __TIM2_RELEASE_RESET        __HAL_RCC_TIM2_RELEASE_RESET
#define __TIM3_CLK_DISABLE          __HAL_RCC_TIM3_CLK_DISABLE
#define __TIM3_CLK_ENABLE           __HAL_RCC_TIM3_CLK_ENABLE
#define __TIM3_CLK_SLEEP_DISABLE    __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
#define __TIM3_CLK_SLEEP_ENABLE     __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
#define __TIM3_FORCE_RESET          __HAL_RCC_TIM3_FORCE_RESET
#define __TIM3_RELEASE_RESET        __HAL_RCC_TIM3_RELEASE_RESET
#define __TIM4_CLK_DISABLE          __HAL_RCC_TIM4_CLK_DISABLE
#define __TIM4_CLK_ENABLE           __HAL_RCC_TIM4_CLK_ENABLE
#define __TIM4_CLK_SLEEP_DISABLE    __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
#define __TIM4_CLK_SLEEP_ENABLE     __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
#define __TIM4_FORCE_RESET          __HAL_RCC_TIM4_FORCE_RESET
#define __TIM4_RELEASE_RESET        __HAL_RCC_TIM4_RELEASE_RESET
#define __TIM5_CLK_DISABLE          __HAL_RCC_TIM5_CLK_DISABLE
#define __TIM5_CLK_ENABLE           __HAL_RCC_TIM5_CLK_ENABLE
#define __TIM5_CLK_SLEEP_DISABLE    __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
#define __TIM5_CLK_SLEEP_ENABLE     __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
#define __TIM5_FORCE_RESET          __HAL_RCC_TIM5_FORCE_RESET
#define __TIM5_RELEASE_RESET        __HAL_RCC_TIM5_RELEASE_RESET
#define __TIM6_CLK_DISABLE          __HAL_RCC_TIM6_CLK_DISABLE
#define __TIM6_CLK_ENABLE           __HAL_RCC_TIM6_CLK_ENABLE
#define __TIM6_CLK_SLEEP_DISABLE    __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
#define __TIM6_CLK_SLEEP_ENABLE     __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
#define __TIM6_FORCE_RESET          __HAL_RCC_TIM6_FORCE_RESET
#define __TIM6_RELEASE_RESET        __HAL_RCC_TIM6_RELEASE_RESET
#define __TIM7_CLK_DISABLE          __HAL_RCC_TIM7_CLK_DISABLE
#define __TIM7_CLK_ENABLE           __HAL_RCC_TIM7_CLK_ENABLE
#define __TIM7_CLK_SLEEP_DISABLE    __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
#define __TIM7_CLK_SLEEP_ENABLE     __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
#define __TIM7_FORCE_RESET          __HAL_RCC_TIM7_FORCE_RESET
#define __TIM7_RELEASE_RESET        __HAL_RCC_TIM7_RELEASE_RESET
#define __TIM8_CLK_DISABLE          __HAL_RCC_TIM8_CLK_DISABLE
#define __TIM8_CLK_ENABLE           __HAL_RCC_TIM8_CLK_ENABLE
#define __TIM8_CLK_SLEEP_DISABLE    __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
#define __TIM8_CLK_SLEEP_ENABLE     __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
#define __TIM8_FORCE_RESET          __HAL_RCC_TIM8_FORCE_RESET
#define __TIM8_RELEASE_RESET        __HAL_RCC_TIM8_RELEASE_RESET
#define __TIM9_CLK_DISABLE          __HAL_RCC_TIM9_CLK_DISABLE
#define __TIM9_CLK_ENABLE           __HAL_RCC_TIM9_CLK_ENABLE
#define __TIM9_FORCE_RESET          __HAL_RCC_TIM9_FORCE_RESET
#define __TIM9_RELEASE_RESET        __HAL_RCC_TIM9_RELEASE_RESET
#define __TSC_CLK_DISABLE           __HAL_RCC_TSC_CLK_DISABLE
#define __TSC_CLK_ENABLE            __HAL_RCC_TSC_CLK_ENABLE
#define __TSC_CLK_SLEEP_DISABLE     __HAL_RCC_TSC_CLK_SLEEP_DISABLE
#define __TSC_CLK_SLEEP_ENABLE      __HAL_RCC_TSC_CLK_SLEEP_ENABLE
#define __TSC_FORCE_RESET           __HAL_RCC_TSC_FORCE_RESET
#define __TSC_RELEASE_RESET         __HAL_RCC_TSC_RELEASE_RESET
#define __UART4_CLK_DISABLE         __HAL_RCC_UART4_CLK_DISABLE
#define __UART4_CLK_ENABLE          __HAL_RCC_UART4_CLK_ENABLE
#define __UART4_CLK_SLEEP_DISABLE   __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __UART4_CLK_SLEEP_ENABLE    __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __UART4_FORCE_RESET         __HAL_RCC_UART4_FORCE_RESET
#define __UART4_RELEASE_RESET       __HAL_RCC_UART4_RELEASE_RESET
#define __UART5_CLK_DISABLE         __HAL_RCC_UART5_CLK_DISABLE
#define __UART5_CLK_ENABLE          __HAL_RCC_UART5_CLK_ENABLE
#define __UART5_CLK_SLEEP_DISABLE   __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __UART5_CLK_SLEEP_ENABLE    __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __UART5_FORCE_RESET         __HAL_RCC_UART5_FORCE_RESET
#define __UART5_RELEASE_RESET       __HAL_RCC_UART5_RELEASE_RESET
#define __USART1_CLK_DISABLE        __HAL_RCC_USART1_CLK_DISABLE
#define __USART1_CLK_ENABLE         __HAL_RCC_USART1_CLK_ENABLE
#define __USART1_CLK_SLEEP_DISABLE  __HAL_RCC_USART1_CLK_SLEEP_DISABLE
#define __USART1_CLK_SLEEP_ENABLE   __HAL_RCC_USART1_CLK_SLEEP_ENABLE
#define __USART1_FORCE_RESET        __HAL_RCC_USART1_FORCE_RESET
#define __USART1_RELEASE_RESET      __HAL_RCC_USART1_RELEASE_RESET
#define __USART2_CLK_DISABLE        __HAL_RCC_USART2_CLK_DISABLE
#define __USART2_CLK_ENABLE         __HAL_RCC_USART2_CLK_ENABLE
#define __USART2_CLK_SLEEP_DISABLE  __HAL_RCC_USART2_CLK_SLEEP_DISABLE
#define __USART2_CLK_SLEEP_ENABLE   __HAL_RCC_USART2_CLK_SLEEP_ENABLE
#define __USART2_FORCE_RESET        __HAL_RCC_USART2_FORCE_RESET
#define __USART2_RELEASE_RESET      __HAL_RCC_USART2_RELEASE_RESET
#define __USART3_CLK_DISABLE        __HAL_RCC_USART3_CLK_DISABLE
#define __USART3_CLK_ENABLE         __HAL_RCC_USART3_CLK_ENABLE
#define __USART3_CLK_SLEEP_DISABLE  __HAL_RCC_USART3_CLK_SLEEP_DISABLE
#define __USART3_CLK_SLEEP_ENABLE   __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET        __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET      __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE           __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE            __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET           __HAL_RCC_USB_FORCE_RESET
#define __USB_CLK_SLEEP_ENABLE      __HAL_RCC_USB_CLK_SLEEP_ENABLE
#define __USB_CLK_SLEEP_DISABLE     __HAL_RCC_USB_CLK_SLEEP_DISABLE
#define __USB_OTG_FS_CLK_DISABLE    __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE     __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET         __HAL_RCC_USB_RELEASE_RESET
#define __WWDG_CLK_DISABLE          __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE           __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE    __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE     __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET          __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET        __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE          __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE         __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET         __HAL_RCC_TIM21_FORCE_RESET
#define __TIM21_RELEASE_RESET       __HAL_RCC_TIM21_RELEASE_RESET
#define __TIM21_CLK_SLEEP_ENABLE    __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
#define __TIM22_CLK_ENABLE          __HAL_RCC_TIM22_CLK_ENABLE
#define __TIM22_CLK_DISABLE         __HAL_RCC_TIM22_CLK_DISABLE
#define __TIM22_FORCE_RESET         __HAL_RCC_TIM22_FORCE_RESET
#define __TIM22_RELEASE_RESET       __HAL_RCC_TIM22_RELEASE_RESET
#define __TIM22_CLK_SLEEP_ENABLE    __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
#define __CRS_CLK_DISABLE           __HAL_RCC_CRS_CLK_DISABLE
#define __CRS_CLK_ENABLE            __HAL_RCC_CRS_CLK_ENABLE
#define __CRS_CLK_SLEEP_DISABLE     __HAL_RCC_CRS_CLK_SLEEP_DISABLE
#define __CRS_CLK_SLEEP_ENABLE      __HAL_RCC_CRS_CLK_SLEEP_ENABLE
#define __CRS_FORCE_RESET           __HAL_RCC_CRS_FORCE_RESET
#define __CRS_RELEASE_RESET         __HAL_RCC_CRS_RELEASE_RESET
#define __RCC_BACKUPRESET_FORCE     __HAL_RCC_BACKUPRESET_FORCE
#define __RCC_BACKUPRESET_RELEASE   __HAL_RCC_BACKUPRESET_RELEASE

#define __USB_OTG_FS_FORCE_RESET                  __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __USB_OTG_FS_RELEASE_RESET                __HAL_RCC_USB_OTG_FS_RELEASE_RESET
#define __USB_OTG_FS_CLK_SLEEP_ENABLE             __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
#define __USB_OTG_FS_CLK_SLEEP_DISABLE            __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
#define __USB_OTG_HS_CLK_DISABLE                  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
#define __USB_OTG_HS_CLK_ENABLE                   __HAL_RCC_USB_OTG_HS_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_ENABLE              __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_DISABLE             __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
#define __TIM9_CLK_SLEEP_ENABLE                   __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
#define __TIM9_CLK_SLEEP_DISABLE                  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
#define __TIM10_CLK_SLEEP_ENABLE                  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
#define __TIM10_CLK_SLEEP_DISABLE                 __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
#define __TIM11_CLK_SLEEP_ENABLE                  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
#define __TIM11_CLK_SLEEP_DISABLE                 __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_SLEEP_ENABLE              __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
#define __ETHMACPTP_CLK_SLEEP_DISABLE             __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_ENABLE                    __HAL_RCC_ETHMACPTP_CLK_ENABLE
#define __ETHMACPTP_CLK_DISABLE                   __HAL_RCC_ETHMACPTP_CLK_DISABLE
#define __HASH_CLK_ENABLE                         __HAL_RCC_HASH_CLK_ENABLE
#define __HASH_FORCE_RESET                        __HAL_RCC_HASH_FORCE_RESET
#define __HASH_RELEASE_RESET                      __HAL_RCC_HASH_RELEASE_RESET
#define __HASH_CLK_SLEEP_ENABLE                   __HAL_RCC_HASH_CLK_SLEEP_ENABLE
#define __HASH_CLK_SLEEP_DISABLE                  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
#define __HASH_CLK_DISABLE                        __HAL_RCC_HASH_CLK_DISABLE
#define __SPI5_CLK_ENABLE                         __HAL_RCC_SPI5_CLK_ENABLE
#define __SPI5_CLK_DISABLE                        __HAL_RCC_SPI5_CLK_DISABLE
#define __SPI5_FORCE_RESET                        __HAL_RCC_SPI5_FORCE_RESET
#define __SPI5_RELEASE_RESET                      __HAL_RCC_SPI5_RELEASE_RESET
#define __SPI5_CLK_SLEEP_ENABLE                   __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
#define __SPI5_CLK_SLEEP_DISABLE                  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
#define __SPI6_CLK_ENABLE                         __HAL_RCC_SPI6_CLK_ENABLE
#define __SPI6_CLK_DISABLE                        __HAL_RCC_SPI6_CLK_DISABLE
#define __SPI6_FORCE_RESET                        __HAL_RCC_SPI6_FORCE_RESET
#define __SPI6_RELEASE_RESET                      __HAL_RCC_SPI6_RELEASE_RESET
#define __SPI6_CLK_SLEEP_ENABLE                   __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
#define __SPI6_CLK_SLEEP_DISABLE                  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
#define __LTDC_CLK_ENABLE                         __HAL_RCC_LTDC_CLK_ENABLE
#define __LTDC_CLK_DISABLE                        __HAL_RCC_LTDC_CLK_DISABLE
#define __LTDC_FORCE_RESET                        __HAL_RCC_LTDC_FORCE_RESET
#define __LTDC_RELEASE_RESET                      __HAL_RCC_LTDC_RELEASE_RESET
#define __LTDC_CLK_SLEEP_ENABLE                   __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_ENABLE                 __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_DISABLE                __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
#define __ETHMACTX_CLK_SLEEP_ENABLE               __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
#define __ETHMACTX_CLK_SLEEP_DISABLE              __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
#define __ETHMACRX_CLK_SLEEP_ENABLE               __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
#define __ETHMACRX_CLK_SLEEP_DISABLE              __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
#define __TIM12_CLK_SLEEP_ENABLE                  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
#define __TIM12_CLK_SLEEP_DISABLE                 __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
#define __TIM13_CLK_SLEEP_ENABLE                  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
#define __TIM13_CLK_SLEEP_DISABLE                 __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
#define __TIM14_CLK_SLEEP_ENABLE                  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
#define __TIM14_CLK_SLEEP_DISABLE                 __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
#define __BKPSRAM_CLK_ENABLE                      __HAL_RCC_BKPSRAM_CLK_ENABLE
#define __BKPSRAM_CLK_DISABLE                     __HAL_RCC_BKPSRAM_CLK_DISABLE
#define __BKPSRAM_CLK_SLEEP_ENABLE                __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
#define __BKPSRAM_CLK_SLEEP_DISABLE               __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
#define __CCMDATARAMEN_CLK_ENABLE                 __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
#define __CCMDATARAMEN_CLK_DISABLE                __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
#define __USART6_CLK_ENABLE                       __HAL_RCC_USART6_CLK_ENABLE
#define __USART6_CLK_DISABLE                      __HAL_RCC_USART6_CLK_DISABLE
#define __USART6_FORCE_RESET                      __HAL_RCC_USART6_FORCE_RESET
#define __USART6_RELEASE_RESET                    __HAL_RCC_USART6_RELEASE_RESET
#define __USART6_CLK_SLEEP_ENABLE                 __HAL_RCC_USART6_CLK_SLEEP_ENABLE
#define __USART6_CLK_SLEEP_DISABLE                __HAL_RCC_USART6_CLK_SLEEP_DISABLE
#define __SPI4_CLK_ENABLE                         __HAL_RCC_SPI4_CLK_ENABLE
#define __SPI4_CLK_DISABLE                        __HAL_RCC_SPI4_CLK_DISABLE
#define __SPI4_FORCE_RESET                        __HAL_RCC_SPI4_FORCE_RESET
#define __SPI4_RELEASE_RESET                      __HAL_RCC_SPI4_RELEASE_RESET
#define __SPI4_CLK_SLEEP_ENABLE                   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
#define __SPI4_CLK_SLEEP_DISABLE                  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
#define __GPIOI_CLK_ENABLE                        __HAL_RCC_GPIOI_CLK_ENABLE
#define __GPIOI_CLK_DISABLE                       __HAL_RCC_GPIOI_CLK_DISABLE
#define __GPIOI_FORCE_RESET                       __HAL_RCC_GPIOI_FORCE_RESET
#define __GPIOI_RELEASE_RESET                     __HAL_RCC_GPIOI_RELEASE_RESET
#define __GPIOI_CLK_SLEEP_ENABLE                  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
#define __GPIOI_CLK_SLEEP_DISABLE                 __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
#define __GPIOJ_CLK_ENABLE                        __HAL_RCC_GPIOJ_CLK_ENABLE
#define __GPIOJ_CLK_DISABLE                       __HAL_RCC_GPIOJ_CLK_DISABLE
#define __GPIOJ_FORCE_RESET                       __HAL_RCC_GPIOJ_FORCE_RESET
#define __GPIOJ_RELEASE_RESET                     __HAL_RCC_GPIOJ_RELEASE_RESET
#define __GPIOJ_CLK_SLEEP_ENABLE                  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
#define __GPIOJ_CLK_SLEEP_DISABLE                 __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
#define __GPIOK_CLK_ENABLE                        __HAL_RCC_GPIOK_CLK_ENABLE
#define __GPIOK_CLK_DISABLE                       __HAL_RCC_GPIOK_CLK_DISABLE
#define __GPIOK_RELEASE_RESET                     __HAL_RCC_GPIOK_RELEASE_RESET
#define __GPIOK_CLK_SLEEP_ENABLE                  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
#define __GPIOK_CLK_SLEEP_DISABLE                 __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
#define __ETH_CLK_ENABLE                          __HAL_RCC_ETH_CLK_ENABLE
#define __ETH_CLK_DISABLE                         __HAL_RCC_ETH_CLK_DISABLE
#define __DCMI_CLK_ENABLE                         __HAL_RCC_DCMI_CLK_ENABLE
#define __DCMI_CLK_DISABLE                        __HAL_RCC_DCMI_CLK_DISABLE
#define __DCMI_FORCE_RESET                        __HAL_RCC_DCMI_FORCE_RESET
#define __DCMI_RELEASE_RESET                      __HAL_RCC_DCMI_RELEASE_RESET
#define __DCMI_CLK_SLEEP_ENABLE                   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
#define __DCMI_CLK_SLEEP_DISABLE                  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
#define __UART7_CLK_ENABLE                        __HAL_RCC_UART7_CLK_ENABLE
#define __UART7_CLK_DISABLE                       __HAL_RCC_UART7_CLK_DISABLE
#define __UART7_RELEASE_RESET                     __HAL_RCC_UART7_RELEASE_RESET
#define __UART7_FORCE_RESET                       __HAL_RCC_UART7_FORCE_RESET
#define __UART7_CLK_SLEEP_ENABLE                  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
#define __UART7_CLK_SLEEP_DISABLE                 __HAL_RCC_UART7_CLK_SLEEP_DISABLE
#define __UART8_CLK_ENABLE                        __HAL_RCC_UART8_CLK_ENABLE
#define __UART8_CLK_DISABLE                       __HAL_RCC_UART8_CLK_DISABLE
#define __UART8_FORCE_RESET                       __HAL_RCC_UART8_FORCE_RESET
#define __UART8_RELEASE_RESET                     __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE                  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
#define __UART8_CLK_SLEEP_DISABLE                 __HAL_RCC_UART8_CLK_SLEEP_DISABLE
#define __OTGHS_CLK_SLEEP_ENABLE                  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __OTGHS_CLK_SLEEP_DISABLE                 __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __OTGHS_FORCE_RESET                       __HAL_RCC_USB_OTG_HS_FORCE_RESET
#define __OTGHS_RELEASE_RESET                     __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __OTGHSULPI_CLK_SLEEP_ENABLE              __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __OTGHSULPI_CLK_SLEEP_DISABLE             __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE         __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED      __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED     __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
#define __HAL_RCC_OTGHS_FORCE_RESET               __HAL_RCC_USB_OTG_HS_FORCE_RESET
#define __HAL_RCC_OTGHS_RELEASE_RESET             __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __CRYP_FORCE_RESET                        __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE                  __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE                   __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE                  __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE                    __HAL_RCC_DAC_CLK_SLEEP_ENABLE
#define __DAC_CLK_SLEEP_DISABLE                   __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE                   __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
#define __ADC2_CLK_SLEEP_DISABLE                  __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE                   __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
#define __ADC3_CLK_SLEEP_DISABLE                  __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET                        __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET                      __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE                   __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
#define __FSMC_CLK_SLEEP_DISABLE                  __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET                        __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET                      __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE                  __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __SDIO_CLK_SLEEP_ENABLE                   __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE                        __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE                       __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET                       __HAL_RCC_DMA2D_FORCE_RESET
#define __DMA2D_RELEASE_RESET                     __HAL_RCC_DMA2D_RELEASE_RESET
#define __DMA2D_CLK_SLEEP_ENABLE                  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_SLEEP_DISABLE                 __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE

/* alias define maintained for legacy */
#define __HAL_RCC_OTGFS_FORCE_RESET   __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET

#define __ADC12_CLK_ENABLE   __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE  __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE   __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE  __HAL_RCC_ADC34_CLK_DISABLE
#define __ADC12_CLK_ENABLE   __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE  __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE    __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE   __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE   __HAL_RCC_TIM18_CLK_ENABLE
#define __TIM18_CLK_DISABLE  __HAL_RCC_TIM18_CLK_DISABLE
#define __TIM19_CLK_ENABLE   __HAL_RCC_TIM19_CLK_ENABLE
#define __TIM19_CLK_DISABLE  __HAL_RCC_TIM19_CLK_DISABLE
#define __TIM20_CLK_ENABLE   __HAL_RCC_TIM20_CLK_ENABLE
#define __TIM20_CLK_DISABLE  __HAL_RCC_TIM20_CLK_DISABLE
#define __HRTIM1_CLK_ENABLE  __HAL_RCC_HRTIM1_CLK_ENABLE
#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
#define __SDADC1_CLK_ENABLE  __HAL_RCC_SDADC1_CLK_ENABLE
#define __SDADC2_CLK_ENABLE  __HAL_RCC_SDADC2_CLK_ENABLE
#define __SDADC3_CLK_ENABLE  __HAL_RCC_SDADC3_CLK_ENABLE
#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE

#define __ADC12_FORCE_RESET    __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET  __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET    __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET  __HAL_RCC_ADC34_RELEASE_RESET
#define __ADC12_FORCE_RESET    __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET  __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET     __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET   __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET    __HAL_RCC_TIM18_FORCE_RESET
#define __TIM18_RELEASE_RESET  __HAL_RCC_TIM18_RELEASE_RESET
#define __TIM19_FORCE_RESET    __HAL_RCC_TIM19_FORCE_RESET
#define __TIM19_RELEASE_RESET  __HAL_RCC_TIM19_RELEASE_RESET
#define __TIM20_FORCE_RESET    __HAL_RCC_TIM20_FORCE_RESET
#define __TIM20_RELEASE_RESET  __HAL_RCC_TIM20_RELEASE_RESET
#define __HRTIM1_FORCE_RESET   __HAL_RCC_HRTIM1_FORCE_RESET
#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
#define __SDADC1_FORCE_RESET   __HAL_RCC_SDADC1_FORCE_RESET
#define __SDADC2_FORCE_RESET   __HAL_RCC_SDADC2_FORCE_RESET
#define __SDADC3_FORCE_RESET   __HAL_RCC_SDADC3_FORCE_RESET
#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET

#define __ADC1_IS_CLK_ENABLED    __HAL_RCC_ADC1_IS_CLK_ENABLED
#define __ADC1_IS_CLK_DISABLED   __HAL_RCC_ADC1_IS_CLK_DISABLED
#define __ADC12_IS_CLK_ENABLED   __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __ADC12_IS_CLK_DISABLED  __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __ADC34_IS_CLK_ENABLED   __HAL_RCC_ADC34_IS_CLK_ENABLED
#define __ADC34_IS_CLK_DISABLED  __HAL_RCC_ADC34_IS_CLK_DISABLED
#define __CEC_IS_CLK_ENABLED     __HAL_RCC_CEC_IS_CLK_ENABLED
#define __CEC_IS_CLK_DISABLED    __HAL_RCC_CEC_IS_CLK_DISABLED
#define __CRC_IS_CLK_ENABLED     __HAL_RCC_CRC_IS_CLK_ENABLED
#define __CRC_IS_CLK_DISABLED    __HAL_RCC_CRC_IS_CLK_DISABLED
#define __DAC1_IS_CLK_ENABLED    __HAL_RCC_DAC1_IS_CLK_ENABLED
#define __DAC1_IS_CLK_DISABLED   __HAL_RCC_DAC1_IS_CLK_DISABLED
#define __DAC2_IS_CLK_ENABLED    __HAL_RCC_DAC2_IS_CLK_ENABLED
#define __DAC2_IS_CLK_DISABLED   __HAL_RCC_DAC2_IS_CLK_DISABLED
#define __DMA1_IS_CLK_ENABLED    __HAL_RCC_DMA1_IS_CLK_ENABLED
#define __DMA1_IS_CLK_DISABLED   __HAL_RCC_DMA1_IS_CLK_DISABLED
#define __DMA2_IS_CLK_ENABLED    __HAL_RCC_DMA2_IS_CLK_ENABLED
#define __DMA2_IS_CLK_DISABLED   __HAL_RCC_DMA2_IS_CLK_DISABLED
#define __FLITF_IS_CLK_ENABLED   __HAL_RCC_FLITF_IS_CLK_ENABLED
#define __FLITF_IS_CLK_DISABLED  __HAL_RCC_FLITF_IS_CLK_DISABLED
#define __FMC_IS_CLK_ENABLED     __HAL_RCC_FMC_IS_CLK_ENABLED
#define __FMC_IS_CLK_DISABLED    __HAL_RCC_FMC_IS_CLK_DISABLED
#define __GPIOA_IS_CLK_ENABLED   __HAL_RCC_GPIOA_IS_CLK_ENABLED
#define __GPIOA_IS_CLK_DISABLED  __HAL_RCC_GPIOA_IS_CLK_DISABLED
#define __GPIOB_IS_CLK_ENABLED   __HAL_RCC_GPIOB_IS_CLK_ENABLED
#define __GPIOB_IS_CLK_DISABLED  __HAL_RCC_GPIOB_IS_CLK_DISABLED
#define __GPIOC_IS_CLK_ENABLED   __HAL_RCC_GPIOC_IS_CLK_ENABLED
#define __GPIOC_IS_CLK_DISABLED  __HAL_RCC_GPIOC_IS_CLK_DISABLED
#define __GPIOD_IS_CLK_ENABLED   __HAL_RCC_GPIOD_IS_CLK_ENABLED
#define __GPIOD_IS_CLK_DISABLED  __HAL_RCC_GPIOD_IS_CLK_DISABLED
#define __GPIOE_IS_CLK_ENABLED   __HAL_RCC_GPIOE_IS_CLK_ENABLED
#define __GPIOE_IS_CLK_DISABLED  __HAL_RCC_GPIOE_IS_CLK_DISABLED
#define __GPIOF_IS_CLK_ENABLED   __HAL_RCC_GPIOF_IS_CLK_ENABLED
#define __GPIOF_IS_CLK_DISABLED  __HAL_RCC_GPIOF_IS_CLK_DISABLED
#define __GPIOG_IS_CLK_ENABLED   __HAL_RCC_GPIOG_IS_CLK_ENABLED
#define __GPIOG_IS_CLK_DISABLED  __HAL_RCC_GPIOG_IS_CLK_DISABLED
#define __GPIOH_IS_CLK_ENABLED   __HAL_RCC_GPIOH_IS_CLK_ENABLED
#define __GPIOH_IS_CLK_DISABLED  __HAL_RCC_GPIOH_IS_CLK_DISABLED
#define __HRTIM1_IS_CLK_ENABLED  __HAL_RCC_HRTIM1_IS_CLK_ENABLED
#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
#define __I2C1_IS_CLK_ENABLED    __HAL_RCC_I2C1_IS_CLK_ENABLED
#define __I2C1_IS_CLK_DISABLED   __HAL_RCC_I2C1_IS_CLK_DISABLED
#define __I2C2_IS_CLK_ENABLED    __HAL_RCC_I2C2_IS_CLK_ENABLED
#define __I2C2_IS_CLK_DISABLED   __HAL_RCC_I2C2_IS_CLK_DISABLED
#define __I2C3_IS_CLK_ENABLED    __HAL_RCC_I2C3_IS_CLK_ENABLED
#define __I2C3_IS_CLK_DISABLED   __HAL_RCC_I2C3_IS_CLK_DISABLED
#define __PWR_IS_CLK_ENABLED     __HAL_RCC_PWR_IS_CLK_ENABLED
#define __PWR_IS_CLK_DISABLED    __HAL_RCC_PWR_IS_CLK_DISABLED
#define __SYSCFG_IS_CLK_ENABLED  __HAL_RCC_SYSCFG_IS_CLK_ENABLED
#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
#define __SPI1_IS_CLK_ENABLED    __HAL_RCC_SPI1_IS_CLK_ENABLED
#define __SPI1_IS_CLK_DISABLED   __HAL_RCC_SPI1_IS_CLK_DISABLED
#define __SPI2_IS_CLK_ENABLED    __HAL_RCC_SPI2_IS_CLK_ENABLED
#define __SPI2_IS_CLK_DISABLED   __HAL_RCC_SPI2_IS_CLK_DISABLED
#define __SPI3_IS_CLK_ENABLED    __HAL_RCC_SPI3_IS_CLK_ENABLED
#define __SPI3_IS_CLK_DISABLED   __HAL_RCC_SPI3_IS_CLK_DISABLED
#define __SPI4_IS_CLK_ENABLED    __HAL_RCC_SPI4_IS_CLK_ENABLED
#define __SPI4_IS_CLK_DISABLED   __HAL_RCC_SPI4_IS_CLK_DISABLED
#define __SDADC1_IS_CLK_ENABLED  __HAL_RCC_SDADC1_IS_CLK_ENABLED
#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
#define __SDADC2_IS_CLK_ENABLED  __HAL_RCC_SDADC2_IS_CLK_ENABLED
#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
#define __SDADC3_IS_CLK_ENABLED  __HAL_RCC_SDADC3_IS_CLK_ENABLED
#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
#define __SRAM_IS_CLK_ENABLED    __HAL_RCC_SRAM_IS_CLK_ENABLED
#define __SRAM_IS_CLK_DISABLED   __HAL_RCC_SRAM_IS_CLK_DISABLED
#define __TIM1_IS_CLK_ENABLED    __HAL_RCC_TIM1_IS_CLK_ENABLED
#define __TIM1_IS_CLK_DISABLED   __HAL_RCC_TIM1_IS_CLK_DISABLED
#define __TIM2_IS_CLK_ENABLED    __HAL_RCC_TIM2_IS_CLK_ENABLED
#define __TIM2_IS_CLK_DISABLED   __HAL_RCC_TIM2_IS_CLK_DISABLED
#define __TIM3_IS_CLK_ENABLED    __HAL_RCC_TIM3_IS_CLK_ENABLED
#define __TIM3_IS_CLK_DISABLED   __HAL_RCC_TIM3_IS_CLK_DISABLED
#define __TIM4_IS_CLK_ENABLED    __HAL_RCC_TIM4_IS_CLK_ENABLED
#define __TIM4_IS_CLK_DISABLED   __HAL_RCC_TIM4_IS_CLK_DISABLED
#define __TIM5_IS_CLK_ENABLED    __HAL_RCC_TIM5_IS_CLK_ENABLED
#define __TIM5_IS_CLK_DISABLED   __HAL_RCC_TIM5_IS_CLK_DISABLED
#define __TIM6_IS_CLK_ENABLED    __HAL_RCC_TIM6_IS_CLK_ENABLED
#define __TIM6_IS_CLK_DISABLED   __HAL_RCC_TIM6_IS_CLK_DISABLED
#define __TIM7_IS_CLK_ENABLED    __HAL_RCC_TIM7_IS_CLK_ENABLED
#define __TIM7_IS_CLK_DISABLED   __HAL_RCC_TIM7_IS_CLK_DISABLED
#define __TIM8_IS_CLK_ENABLED    __HAL_RCC_TIM8_IS_CLK_ENABLED
#define __TIM8_IS_CLK_DISABLED   __HAL_RCC_TIM8_IS_CLK_DISABLED
#define __TIM12_IS_CLK_ENABLED   __HAL_RCC_TIM12_IS_CLK_ENABLED
#define __TIM12_IS_CLK_DISABLED  __HAL_RCC_TIM12_IS_CLK_DISABLED
#define __TIM13_IS_CLK_ENABLED   __HAL_RCC_TIM13_IS_CLK_ENABLED
#define __TIM13_IS_CLK_DISABLED  __HAL_RCC_TIM13_IS_CLK_DISABLED
#define __TIM14_IS_CLK_ENABLED   __HAL_RCC_TIM14_IS_CLK_ENABLED
#define __TIM14_IS_CLK_DISABLED  __HAL_RCC_TIM14_IS_CLK_DISABLED
#define __TIM15_IS_CLK_ENABLED   __HAL_RCC_TIM15_IS_CLK_ENABLED
#define __TIM15_IS_CLK_DISABLED  __HAL_RCC_TIM15_IS_CLK_DISABLED
#define __TIM16_IS_CLK_ENABLED   __HAL_RCC_TIM16_IS_CLK_ENABLED
#define __TIM16_IS_CLK_DISABLED  __HAL_RCC_TIM16_IS_CLK_DISABLED
#define __TIM17_IS_CLK_ENABLED   __HAL_RCC_TIM17_IS_CLK_ENABLED
#define __TIM17_IS_CLK_DISABLED  __HAL_RCC_TIM17_IS_CLK_DISABLED
#define __TIM18_IS_CLK_ENABLED   __HAL_RCC_TIM18_IS_CLK_ENABLED
#define __TIM18_IS_CLK_DISABLED  __HAL_RCC_TIM18_IS_CLK_DISABLED
#define __TIM19_IS_CLK_ENABLED   __HAL_RCC_TIM19_IS_CLK_ENABLED
#define __TIM19_IS_CLK_DISABLED  __HAL_RCC_TIM19_IS_CLK_DISABLED
#define __TIM20_IS_CLK_ENABLED   __HAL_RCC_TIM20_IS_CLK_ENABLED
#define __TIM20_IS_CLK_DISABLED  __HAL_RCC_TIM20_IS_CLK_DISABLED
#define __TSC_IS_CLK_ENABLED     __HAL_RCC_TSC_IS_CLK_ENABLED
#define __TSC_IS_CLK_DISABLED    __HAL_RCC_TSC_IS_CLK_DISABLED
#define __UART4_IS_CLK_ENABLED   __HAL_RCC_UART4_IS_CLK_ENABLED
#define __UART4_IS_CLK_DISABLED  __HAL_RCC_UART4_IS_CLK_DISABLED
#define __UART5_IS_CLK_ENABLED   __HAL_RCC_UART5_IS_CLK_ENABLED
#define __UART5_IS_CLK_DISABLED  __HAL_RCC_UART5_IS_CLK_DISABLED
#define __USART1_IS_CLK_ENABLED  __HAL_RCC_USART1_IS_CLK_ENABLED
#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
#define __USART2_IS_CLK_ENABLED  __HAL_RCC_USART2_IS_CLK_ENABLED
#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
#define __USART3_IS_CLK_ENABLED  __HAL_RCC_USART3_IS_CLK_ENABLED
#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
#define __USB_IS_CLK_ENABLED     __HAL_RCC_USB_IS_CLK_ENABLED
#define __USB_IS_CLK_DISABLED    __HAL_RCC_USB_IS_CLK_DISABLED
#define __WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED   __HAL_RCC_WWDG_IS_CLK_DISABLED

#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
#define Sdmmc1ClockSelection               SdioClockSelection
#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
#endif

#if defined(STM32F7) || defined(STM32L4)
#define __HAL_RCC_SDIO_FORCE_RESET       __HAL_RCC_SDMMC1_FORCE_RESET
#define __HAL_RCC_SDIO_RELEASE_RESET     __HAL_RCC_SDMMC1_RELEASE_RESET
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDIO_CLK_ENABLE        __HAL_RCC_SDMMC1_CLK_ENABLE
#define __HAL_RCC_SDIO_CLK_DISABLE       __HAL_RCC_SDMMC1_CLK_DISABLE
#define __HAL_RCC_SDIO_IS_CLK_ENABLED    __HAL_RCC_SDMMC1_IS_CLK_ENABLED
#define __HAL_RCC_SDIO_IS_CLK_DISABLED   __HAL_RCC_SDMMC1_IS_CLK_DISABLED
#define SdioClockSelection               Sdmmc1ClockSelection
#define RCC_PERIPHCLK_SDIO               RCC_PERIPHCLK_SDMMC1
#define __HAL_RCC_SDIO_CONFIG            __HAL_RCC_SDMMC1_CONFIG
#define __HAL_RCC_GET_SDIO_SOURCE        __HAL_RCC_GET_SDMMC1_SOURCE
#endif

#if defined(STM32H7)
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()             __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()            __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()       __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()            __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()          __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()

#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
#endif

#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CLK48  RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif

#define __HAL_RCC_I2SCLK        __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG

#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE

#define IS_RCC_MSIRANGE      IS_RCC_MSI_CLOCK_RANGE
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
#define IS_RCC_SYSCLK_DIV    IS_RCC_HCLK
#define IS_RCC_HCLK_DIV      IS_RCC_PCLK
#define IS_RCC_PERIPHCLK     IS_RCC_PERIPHCLOCK

#define RCC_IT_HSI14 RCC_IT_HSI14RDY

#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS

#define RCC_PLLMUL_3  RCC_PLL_MUL3
#define RCC_PLLMUL_4  RCC_PLL_MUL4
#define RCC_PLLMUL_6  RCC_PLL_MUL6
#define RCC_PLLMUL_8  RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48

#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4

#define IS_RCC_MCOSOURCE           IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG       __HAL_RCC_MCO1_CONFIG
#define RCC_MCO_NODIV              RCC_MCODIV_1
#define RCC_MCO_DIV1               RCC_MCODIV_1
#define RCC_MCO_DIV2               RCC_MCODIV_2
#define RCC_MCO_DIV4               RCC_MCODIV_4
#define RCC_MCO_DIV8               RCC_MCODIV_8
#define RCC_MCO_DIV16              RCC_MCODIV_16
#define RCC_MCO_DIV32              RCC_MCODIV_32
#define RCC_MCO_DIV64              RCC_MCODIV_64
#define RCC_MCO_DIV128             RCC_MCODIV_128
#define RCC_MCOSOURCE_NONE         RCC_MCO1SOURCE_NOCLOCK
#define RCC_MCOSOURCE_LSI          RCC_MCO1SOURCE_LSI
#define RCC_MCOSOURCE_LSE          RCC_MCO1SOURCE_LSE
#define RCC_MCOSOURCE_SYSCLK       RCC_MCO1SOURCE_SYSCLK
#define RCC_MCOSOURCE_HSI          RCC_MCO1SOURCE_HSI
#define RCC_MCOSOURCE_HSI14        RCC_MCO1SOURCE_HSI14
#define RCC_MCOSOURCE_HSI48        RCC_MCO1SOURCE_HSI48
#define RCC_MCOSOURCE_HSE          RCC_MCO1SOURCE_HSE
#define RCC_MCOSOURCE_PLLCLK_DIV1  RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2  RCC_MCO1SOURCE_PLLCLK_DIV2

#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK

#define RCC_USBCLK_PLLSAI1      RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL          RCC_USBCLKSOURCE_PLL
#define RCC_USBCLK_MSI          RCC_USBCLKSOURCE_MSI
#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1      RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1_5    RCC_USBCLKSOURCE_PLL_DIV1_5
#define RCC_USBPLLCLK_DIV2      RCC_USBCLKSOURCE_PLL_DIV2
#define RCC_USBPLLCLK_DIV3      RCC_USBCLKSOURCE_PLL_DIV3

#define HSION_BitNumber             RCC_HSION_BIT_NUMBER
#define HSION_BITNUMBER             RCC_HSION_BIT_NUMBER
#define HSEON_BitNumber             RCC_HSEON_BIT_NUMBER
#define HSEON_BITNUMBER             RCC_HSEON_BIT_NUMBER
#define MSION_BITNUMBER             RCC_MSION_BIT_NUMBER
#define CSSON_BitNumber             RCC_CSSON_BIT_NUMBER
#define CSSON_BITNUMBER             RCC_CSSON_BIT_NUMBER
#define PLLON_BitNumber             RCC_PLLON_BIT_NUMBER
#define PLLON_BITNUMBER             RCC_PLLON_BIT_NUMBER
#define PLLI2SON_BitNumber          RCC_PLLI2SON_BIT_NUMBER
#define I2SSRC_BitNumber            RCC_I2SSRC_BIT_NUMBER
#define RTCEN_BitNumber             RCC_RTCEN_BIT_NUMBER
#define RTCEN_BITNUMBER             RCC_RTCEN_BIT_NUMBER
#define BDRST_BitNumber             RCC_BDRST_BIT_NUMBER
#define BDRST_BITNUMBER             RCC_BDRST_BIT_NUMBER
#define RTCRST_BITNUMBER            RCC_RTCRST_BIT_NUMBER
#define LSION_BitNumber             RCC_LSION_BIT_NUMBER
#define LSION_BITNUMBER             RCC_LSION_BIT_NUMBER
#define LSEON_BitNumber             RCC_LSEON_BIT_NUMBER
#define LSEON_BITNUMBER             RCC_LSEON_BIT_NUMBER
#define LSEBYP_BITNUMBER            RCC_LSEBYP_BIT_NUMBER
#define PLLSAION_BitNumber          RCC_PLLSAION_BIT_NUMBER
#define TIMPRE_BitNumber            RCC_TIMPRE_BIT_NUMBER
#define RMVF_BitNumber              RCC_RMVF_BIT_NUMBER
#define RMVF_BITNUMBER              RCC_RMVF_BIT_NUMBER
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
#define CR_BYTE2_ADDRESS            RCC_CR_BYTE2_ADDRESS
#define CIR_BYTE1_ADDRESS           RCC_CIR_BYTE1_ADDRESS
#define CIR_BYTE2_ADDRESS           RCC_CIR_BYTE2_ADDRESS
#define BDCR_BYTE0_ADDRESS          RCC_BDCR_BYTE0_ADDRESS
#define DBP_TIMEOUT_VALUE           RCC_DBP_TIMEOUT_VALUE
#define LSE_TIMEOUT_VALUE           RCC_LSE_TIMEOUT_VALUE

#define CR_HSION_BB       RCC_CR_HSION_BB
#define CR_CSSON_BB       RCC_CR_CSSON_BB
#define CR_PLLON_BB       RCC_CR_PLLON_BB
#define CR_PLLI2SON_BB    RCC_CR_PLLI2SON_BB
#define CR_MSION_BB       RCC_CR_MSION_BB
#define CSR_LSION_BB      RCC_CSR_LSION_BB
#define CSR_LSEON_BB      RCC_CSR_LSEON_BB
#define CSR_LSEBYP_BB     RCC_CSR_LSEBYP_BB
#define CSR_RTCEN_BB      RCC_CSR_RTCEN_BB
#define CSR_RTCRST_BB     RCC_CSR_RTCRST_BB
#define CFGR_I2SSRC_BB    RCC_CFGR_I2SSRC_BB
#define BDCR_RTCEN_BB     RCC_BDCR_RTCEN_BB
#define BDCR_BDRST_BB     RCC_BDCR_BDRST_BB
#define CR_HSEON_BB       RCC_CR_HSEON_BB
#define CSR_RMVF_BB       RCC_CSR_RMVF_BB
#define CR_PLLSAION_BB    RCC_CR_PLLSAION_BB
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB

#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER  __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB     __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB    __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE      __HAL_RCC_CRS_RELOADVALUE_CALCULATE

#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT

#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV   RCC_CRS_TRIMOVF

#define RCC_PERIPHCLK_CK48        RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ    RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE      IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48    RCC_SDIOCLKSOURCE_CLK48

#define __HAL_RCC_DFSDM_CLK_ENABLE            __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE           __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED        __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED       __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET           __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET         __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE     __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection                   Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM                   RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK               RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK             RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG                __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE            __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK              RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK              RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK              RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK              RCC_LPTIM2CLKSOURCE_PCLK1

#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM1CLKSOURCE_APB2         RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2         RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB         RCC_FMPI2C1CLKSOURCE_PCLK1

/**
 * @}
 */

/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
 * @{
 */
#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)

/**
 * @}
 */

/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT  __HAL_RTC_EXTI_ENABLE_IT

#if defined(STM32F1)
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()

#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()

#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()

#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()

#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)                                      \
  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() \
                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)                                      \
  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() \
                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)                                      \
  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() \
                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)                                      \
  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() \
                                                  : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) \
  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT)   \
       ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()       \
       : (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */

#define IS_ALARM                              IS_RTC_ALARM
#define IS_ALARM_MASK                         IS_RTC_ALARM_MASK
#define IS_TAMPER                             IS_RTC_TAMPER
#define IS_TAMPER_ERASE_MODE                  IS_RTC_TAMPER_ERASE_MODE
#define IS_TAMPER_FILTER                      IS_RTC_TAMPER_FILTER
#define IS_TAMPER_INTERRUPT                   IS_RTC_TAMPER_INTERRUPT
#define IS_TAMPER_MASKFLAG_STATE              IS_RTC_TAMPER_MASKFLAG_STATE
#define IS_TAMPER_PRECHARGE_DURATION          IS_RTC_TAMPER_PRECHARGE_DURATION
#define IS_TAMPER_PULLUP_STATE                IS_RTC_TAMPER_PULLUP_STATE
#define IS_TAMPER_SAMPLING_FREQ               IS_RTC_TAMPER_SAMPLING_FREQ
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
#define IS_TAMPER_TRIGGER                     IS_RTC_TAMPER_TRIGGER
#define IS_WAKEUP_CLOCK                       IS_RTC_WAKEUP_CLOCK
#define IS_WAKEUP_COUNTER                     IS_RTC_WAKEUP_COUNTER

#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE

/**
 * @}
 */

/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
 * @{
 */

#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS       SD_CMD_SD_APP_STATUS

#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED          SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
#define SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
#define SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
#define SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
#define SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
#define SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
#define __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
#define __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
#define __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
#define __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
#define __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
#define __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
#define __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
#define __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
#define __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
#define SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
#define SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
#define SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
/* alias CMSIS */
#define SDMMC1_IRQn       SDIO_IRQn
#define SDMMC1_IRQHandler SDIO_IRQHandler
#endif

#if defined(STM32F7) || defined(STM32L4)
#define SD_SDIO_DISABLED         SD_SDMMC_DISABLED
#define SD_SDIO_FUNCTION_BUSY    SD_SDMMC_FUNCTION_BUSY
#define SD_SDIO_FUNCTION_FAILED  SD_SDMMC_FUNCTION_FAILED
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
#define SD_CMD_SDIO_SEN_OP_COND  SD_CMD_SDMMC_SEN_OP_COND
#define SD_CMD_SDIO_RW_DIRECT    SD_CMD_SDMMC_RW_DIRECT
#define SD_CMD_SDIO_RW_EXTENDED  SD_CMD_SDMMC_RW_EXTENDED
#define __HAL_SD_SDIO_ENABLE     __HAL_SD_SDMMC_ENABLE
#define __HAL_SD_SDIO_DISABLE    __HAL_SD_SDMMC_DISABLE
#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
#define __HAL_SD_SDIO_ENABLE_IT  __HAL_SD_SDMMC_ENABLE_IT
#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
#define __HAL_SD_SDIO_GET_FLAG   __HAL_SD_SDMMC_GET_FLAG
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT     __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT   __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS        SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT         SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND     SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn       SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif

#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#define HAL_SD_CardCIDTypedef    HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef    HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef  HAL_SD_CardStateTypeDef
#endif

/**
 * @}
 */

/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
 * @{
 */

#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE

#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
#define __SMARTCARD_GETCLOCKSOURCE     SMARTCARD_GETCLOCKSOURCE

#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE

/**
 * @}
 */

/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_SMBUS_RESET_CR1         SMBUS_RESET_CR1
#define __HAL_SMBUS_RESET_CR2         SMBUS_RESET_CR2
#define __HAL_SMBUS_GENERATE_START    SMBUS_GENERATE_START
#define __HAL_SMBUS_GET_ADDR_MATCH    SMBUS_GET_ADDR_MATCH
#define __HAL_SMBUS_GET_DIR           SMBUS_GET_DIR
#define __HAL_SMBUS_GET_STOP_MODE     SMBUS_GET_STOP_MODE
#define __HAL_SMBUS_GET_PEC_MODE      SMBUS_GET_PEC_MODE
#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
/**
 * @}
 */

/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_SPI_1LINE_TX  SPI_1LINE_TX
#define __HAL_SPI_1LINE_RX  SPI_1LINE_RX
#define __HAL_SPI_RESET_CRC SPI_RESET_CRC

/**
 * @}
 */

/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_UART_GETCLOCKSOURCE   UART_GETCLOCKSOURCE
#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
#define __UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
#define __UART_MASK_COMPUTATION     UART_MASK_COMPUTATION

#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD

#define IS_UART_ONEBIT_SAMPLE   IS_UART_ONE_BIT_SAMPLE
#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE

/**
 * @}
 */

/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
 * @{
 */

#define __USART_ENABLE_IT  __HAL_USART_ENABLE_IT
#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
#define __USART_ENABLE     __HAL_USART_ENABLE
#define __USART_DISABLE    __HAL_USART_DISABLE

#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE     USART_GETCLOCKSOURCE

/**
 * @}
 */

/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
 * @{
 */
#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE

#define USB_FS_EXTI_TRIGGER_RISING_EDGE  USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE    USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
#define USB_FS_EXTI_LINE_WAKEUP          USB_OTG_FS_WAKEUP_EXTI_LINE

#define USB_HS_EXTI_TRIGGER_RISING_EDGE  USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE    USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
#define USB_HS_EXTI_LINE_WAKEUP          USB_OTG_HS_WAKEUP_EXTI_LINE

#define __HAL_USB_EXTI_ENABLE_IT                 __HAL_USB_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_EXTI_DISABLE_IT                __HAL_USB_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_EXTI_GET_FLAG                  __HAL_USB_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_EXTI_CLEAR_FLAG                __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER   __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER  __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE

#define __HAL_USB_FS_EXTI_ENABLE_IT                 __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_FS_EXTI_DISABLE_IT                __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_FS_EXTI_GET_FLAG                  __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_FS_EXTI_CLEAR_FLAG                __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER   __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER  __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
#define __HAL_USB_FS_EXTI_GENERATE_SWIT             __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT

#define __HAL_USB_HS_EXTI_ENABLE_IT                 __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_HS_EXTI_DISABLE_IT                __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_HS_EXTI_GET_FLAG                  __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_HS_EXTI_CLEAR_FLAG                __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER   __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER  __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
#define __HAL_USB_HS_EXTI_GENERATE_SWIT             __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT

#define HAL_PCD_ActiveRemoteWakeup   HAL_PCD_ActivateRemoteWakeup
#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup

#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
/**
 * @}
 */

/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE

#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT

#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE

#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
#define __HAL_TIM_PRESCALER        __HAL_TIM_SET_PRESCALER
#define __HAL_TIM_SetCounter       __HAL_TIM_SET_COUNTER
#define __HAL_TIM_GetCounter       __HAL_TIM_GET_COUNTER
#define __HAL_TIM_SetAutoreload    __HAL_TIM_SET_AUTORELOAD
#define __HAL_TIM_GetAutoreload    __HAL_TIM_GET_AUTORELOAD
#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
#define __HAL_TIM_SetICPrescaler   __HAL_TIM_SET_ICPRESCALER
#define __HAL_TIM_GetICPrescaler   __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare       __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare       __HAL_TIM_GET_COMPARE

#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
 * @}
 */

/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
 * @{
 */

#define __HAL_ETH_EXTI_ENABLE_IT                 __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
#define __HAL_ETH_EXTI_DISABLE_IT                __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
#define __HAL_ETH_EXTI_GET_FLAG                  __HAL_ETH_WAKEUP_EXTI_GET_FLAG
#define __HAL_ETH_EXTI_CLEAR_FLAG                __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER  __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER

#define ETH_PROMISCIOUSMODE_ENABLE  ETH_PROMISCUOUS_MODE_ENABLE
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
#define IS_ETH_PROMISCIOUS_MODE     IS_ETH_PROMISCUOUS_MODE
/**
 * @}
 */

/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
 * @{
 */
#define __HAL_LTDC_LAYER         LTDC_LAYER
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
 * @}
 */

/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
 * @{
 */
#define SAI_OUTPUTDRIVE_DISABLED        SAI_OUTPUTDRIVE_DISABLE
#define SAI_OUTPUTDRIVE_ENABLED         SAI_OUTPUTDRIVE_ENABLE
#define SAI_MASTERDIVIDER_ENABLED       SAI_MASTERDIVIDER_ENABLE
#define SAI_MASTERDIVIDER_DISABLED      SAI_MASTERDIVIDER_DISABLE
#define SAI_STREOMODE                   SAI_STEREOMODE
#define SAI_FIFOStatus_Empty            SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull     SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull         SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull    SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full             SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE    IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_SYNCHRONOUS_EXT             SAI_SYNCHRONOUS_EXT_SAI1
#define SAI_SYNCEXT_IN_ENABLE           SAI_SYNCEXT_OUTBLOCKA_ENABLE
/**
 * @}
 */

/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
 * @{
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* ___STM32_HAL_LEGACY */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal.h
 * @author  MCD Application Team
 * @brief   This file contains all the functions prototypes for the HAL
 *          module driver.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_H
#define __STM32F1xx_HAL_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_conf.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup HAL
 * @{
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup HAL_Exported_Constants HAL Exported Constants
 * @{
 */

/** @defgroup HAL_TICK_FREQ Tick Frequency
 * @{
 */
typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef;
/**
 * @}
 */
/* Exported types ------------------------------------------------------------*/
extern uint32_t            uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;

/**
 * @}
 */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
 * @{
 */

/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
 * @brief   Freeze/Unfreeze Peripherals in Debug mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @{
 */

/* Peripherals on APB1 */
/**
 * @brief  TIM2 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)

/**
 * @brief  TIM3 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM3()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)

#if defined(DBGMCU_CR_DBG_TIM4_STOP)
/**
 * @brief  TIM4 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM4()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM5_STOP)
/**
 * @brief  TIM5 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM5()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM6_STOP)
/**
 * @brief  TIM6 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM6()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM7_STOP)
/**
 * @brief  TIM7 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM7()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM12_STOP)
/**
 * @brief  TIM12 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM12()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM13_STOP)
/**
 * @brief  TIM13 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM13()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM14_STOP)
/**
 * @brief  TIM14 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM14()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#endif

/**
 * @brief  WWDG Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_WWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)

/**
 * @brief  IWDG Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_IWDG()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)

/**
 * @brief  I2C1 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)

#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
/**
 * @brief  I2C2 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#endif

#if defined(DBGMCU_CR_DBG_CAN1_STOP)
/**
 * @brief  CAN1 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_CAN1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#endif

#if defined(DBGMCU_CR_DBG_CAN2_STOP)
/**
 * @brief  CAN2 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_CAN2()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#endif

/* Peripherals on APB2 */
#if defined(DBGMCU_CR_DBG_TIM1_STOP)
/**
 * @brief  TIM1 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM1()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM8_STOP)
/**
 * @brief  TIM8 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM8()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM9_STOP)
/**
 * @brief  TIM9 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM9()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM10_STOP)
/**
 * @brief  TIM10 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM10()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM11_STOP)
/**
 * @brief  TIM11 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM11()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM15_STOP)
/**
 * @brief  TIM15 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM15()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM16_STOP)
/**
 * @brief  TIM16 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM16()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#endif

#if defined(DBGMCU_CR_DBG_TIM17_STOP)
/**
 * @brief  TIM17 Peripherals Debug mode
 */
#define __HAL_DBGMCU_FREEZE_TIM17()   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#endif

/**
 * @}
 */

/** @defgroup HAL_Private_Macros HAL Private Macros
 * @{
 */
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || ((FREQ) == HAL_TICK_FREQ_100HZ) || ((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
 * @{
 */
/** @addtogroup HAL_Exported_Functions_Group1
 * @{
 */
/* Initialization and de-initialization functions  ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void              HAL_MspInit(void);
void              HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
 * @}
 */

/** @addtogroup HAL_Exported_Functions_Group2
 * @{
 */
/* Peripheral Control functions  ************************************************/
void                HAL_IncTick(void);
void                HAL_Delay(uint32_t Delay);
uint32_t            HAL_GetTick(void);
uint32_t            HAL_GetTickPrio(void);
HAL_StatusTypeDef   HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void                HAL_SuspendTick(void);
void                HAL_ResumeTick(void);
uint32_t            HAL_GetHalVersion(void);
uint32_t            HAL_GetREVID(void);
uint32_t            HAL_GetDEVID(void);
uint32_t            HAL_GetUIDw0(void);
uint32_t            HAL_GetUIDw1(void);
uint32_t            HAL_GetUIDw2(void);
void                HAL_DBGMCU_EnableDBGSleepMode(void);
void                HAL_DBGMCU_DisableDBGSleepMode(void);
void                HAL_DBGMCU_EnableDBGStopMode(void);
void                HAL_DBGMCU_DisableDBGStopMode(void);
void                HAL_DBGMCU_EnableDBGStandbyMode(void);
void                HAL_DBGMCU_DisableDBGStandbyMode(void);
void                HAL_GetUID(uint32_t *UID);
/**
 * @}
 */

/**
 * @}
 */
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables
 * @{
 */
/**
 * @}
 */
/* Private constants ---------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants
 * @{
 */
/**
 * @}
 */
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_adc.h
 * @author  MCD Application Team
 * @brief   Header file containing functions prototypes of ADC HAL library.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_ADC_H
#define __STM32F1xx_HAL_ADC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup ADC
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
 * @{
 */

/**
 * @brief  Structure definition of ADC and regular group initialization
 * @note   Parameters of this structure are shared within 2 scopes:
 *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
 *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
 * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
 *         ADC can be either disabled or enabled without conversion on going on regular group.
 */
typedef struct {
  uint32_t DataAlign;          /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
                                    or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset
                                  application): MSB on register bit 14 and LSB on register bit 3).          This parameter can be a value of @ref ADC_Data_align */
  uint32_t ScanConvMode;       /*!< Configures the sequencer of regular and injected groups.
                                    This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
                                    If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
                                                 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
                                    If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
                                                 Scan direction is upward: from rank1 to rank 'n'.
                                    This parameter can be a value of @ref ADC_Scan_mode
                                    Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
                                          or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
                                          the last conversion of the sequence. All previous conversions would be overwritten by the last one.
                                          Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
  uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
                                    after the selected trigger occurred (software start or external trigger).
                                    This parameter can be set to ENABLE or DISABLE. */
  uint32_t NbrOfConversion;    /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
                                    To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                    This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
  uint32_t
      DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
                                  Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
                                  Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
                                  This parameter can be set to ENABLE or DISABLE. */
  uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
                                     If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
                                     This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
  uint32_t ExternalTrigConv;    /*!< Selects the external event used to trigger the conversion start of regular group.
                                     If set to ADC_SOFTWARE_START, external triggers are disabled.
                                     If set to external trigger source, triggering is on event rising edge.
                                     This parameter can be a value of @ref ADC_External_trigger_source_Regular */
} ADC_InitTypeDef;

/**
 * @brief  Structure definition of ADC channel for regular group
 * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
 *         ADC can be either disabled or enabled without conversion on going on regular group.
 */
typedef struct {
  uint32_t
      Channel;           /*!< Specifies the channel to configure into ADC regular group.
                              This parameter can be a value of @ref ADC_channels
                              Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
                              Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
                              Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection
                            trigger.      It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.      Refer to errata sheet of these devices for more details. */
  uint32_t Rank;         /*!< Specifies the rank in the regular group sequencer
                              This parameter can be a value of @ref ADC_regular_rank
                              Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or
                            parameter number of conversions can be adjusted) */
  uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
                              Unit: ADC clock cycles
                              Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
                              This parameter can be a value of @ref ADC_sampling_times
                              Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
                                       If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
                              Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
                                    sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
                                    Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
} ADC_ChannelConfTypeDef;

/**
 * @brief  ADC Configuration analog watchdog definition
 * @note   The setting of these parameters with function is conditioned to ADC state.
 *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
 */
typedef struct {
  uint32_t WatchdogMode;   /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
                                This parameter can be a value of @ref ADC_analog_watchdog_mode. */
  uint32_t Channel;        /*!< Selects which ADC channel to monitor by analog watchdog.
                                This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
                                This parameter can be a value of @ref ADC_channels. */
  uint32_t ITMode;         /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
                                This parameter can be set to ENABLE or DISABLE */
  uint32_t HighThreshold;  /*!< Configures the ADC analog watchdog High threshold value.
                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
  uint32_t LowThreshold;   /*!< Configures the ADC analog watchdog High threshold value.
                                This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
  uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
} ADC_AnalogWDGConfTypeDef;

/**
 * @brief  HAL ADC state machine: ADC states definition (bitfields)
 */
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET         0x00000000U /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY         0x00000001U /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT       0x00000004U /*!< TimeOut occurrence */

/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG   0x00000020U /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA      0x00000040U /*!< DMA error occurrence */

/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY                                                                                                     \
  0x00000100U                               /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, \
                                                external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC   0x00000200U /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR   0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised  */

/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY                                                                                                          \
  0x00001000U                               /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, \
                                                external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC   0x00002000U /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */

/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */

/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */

/**
 * @brief  ADC handle Structure definition
 */
typedef struct {
  ADC_TypeDef *Instance; /*!< Register base address */

  ADC_InitTypeDef Init; /*!< ADC required parameters */

  DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */

  HAL_LockTypeDef Lock; /*!< ADC locking object */

  __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */

  __IO uint32_t ErrorCode; /*!< ADC Error code */
} ADC_HandleTypeDef;
/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup ADC_Exported_Constants ADC Exported Constants
 * @{
 */

/** @defgroup ADC_Error_Code ADC Error Code
 * @{
 */
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error                                              */
#define HAL_ADC_ERROR_INTERNAL                                                      \
  0x01U                         /*!< ADC IP internal error: if problem of clocking, \
                                     enable/disable, erroneous state                       */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error                                         */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error                                    */

/**
 * @}
 */

/** @defgroup ADC_Data_align ADC data alignment
 * @{
 */
#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT  ((uint32_t)ADC_CR2_ALIGN)
/**
 * @}
 */

/** @defgroup ADC_Scan_mode ADC scan mode
 * @{
 */
/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for     */
/*       compatibility with other STM32 devices having a sequencer with       */
/*       additional options.                                                  */
#define ADC_SCAN_DISABLE 0x00000000U
#define ADC_SCAN_ENABLE  ((uint32_t)ADC_CR1_SCAN)
/**
 * @}
 */

/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
 * @{
 */
#define ADC_EXTERNALTRIGCONVEDGE_NONE   0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
/**
 * @}
 */

/** @defgroup ADC_channels ADC channels
 * @{
 */
/* Note: Depending on devices, some channels may not be available on package  */
/*       pins. Refer to device datasheet for channels availability.           */
#define ADC_CHANNEL_0  0x00000000U
#define ADC_CHANNEL_1  ((uint32_t)(ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_2  ((uint32_t)(ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_3  ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_4  ((uint32_t)(ADC_SQR3_SQ1_2))
#define ADC_CHANNEL_5  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_6  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_7  ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_8  ((uint32_t)(ADC_SQR3_SQ1_3))
#define ADC_CHANNEL_9  ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))

// #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
// #define ADC_CHANNEL_VREFINT    ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
/**
 * @}
 */

/** @defgroup ADC_sampling_times ADC sampling times
 * @{
 */
#define ADC_SAMPLETIME_1CYCLE_5    0x00000000U                                                          /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_7CYCLES_5   ((uint32_t)(ADC_SMPR2_SMP0_0))                                       /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_13CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1))                                       /*!< Sampling time 13.5 ADC clock cycles */
#define ADC_SAMPLETIME_28CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 28.5 ADC clock cycles */
#define ADC_SAMPLETIME_41CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2))                                       /*!< Sampling time 41.5 ADC clock cycles */
#define ADC_SAMPLETIME_55CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))                    /*!< Sampling time 55.5 ADC clock cycles */
#define ADC_SAMPLETIME_71CYCLES_5  ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1))                    /*!< Sampling time 71.5 ADC clock cycles */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
/**
 * @}
 */

/** @defgroup ADC_regular_rank ADC rank into regular group
 * @{
 */
#define ADC_REGULAR_RANK_1  0x00000001U
#define ADC_REGULAR_RANK_2  0x00000002U
#define ADC_REGULAR_RANK_3  0x00000003U
#define ADC_REGULAR_RANK_4  0x00000004U
#define ADC_REGULAR_RANK_5  0x00000005U
#define ADC_REGULAR_RANK_6  0x00000006U
#define ADC_REGULAR_RANK_7  0x00000007U
#define ADC_REGULAR_RANK_8  0x00000008U
#define ADC_REGULAR_RANK_9  0x00000009U
#define ADC_REGULAR_RANK_10 0x0000000AU
#define ADC_REGULAR_RANK_11 0x0000000BU
#define ADC_REGULAR_RANK_12 0x0000000CU
#define ADC_REGULAR_RANK_13 0x0000000DU
#define ADC_REGULAR_RANK_14 0x0000000EU
#define ADC_REGULAR_RANK_15 0x0000000FU
#define ADC_REGULAR_RANK_16 0x00000010U
/**
 * @}
 */

/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
 * @{
 */
#define ADC_ANALOGWATCHDOG_NONE            0x00000000U
#define ADC_ANALOGWATCHDOG_SINGLE_REG      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG         ((uint32_t)ADC_CR1_AWDEN)
#define ADC_ANALOGWATCHDOG_ALL_INJEC       ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC    ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
/**
 * @}
 */

/** @defgroup ADC_conversion_group ADC conversion group
 * @{
 */
#define ADC_REGULAR_GROUP          ((uint32_t)(ADC_FLAG_EOC))
#define ADC_INJECTED_GROUP         ((uint32_t)(ADC_FLAG_JEOC))
#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
/**
 * @}
 */

/** @defgroup ADC_Event_type ADC Event type
 * @{
 */
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */

#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
/**
 * @}
 */

/** @defgroup ADC_interrupts_definition ADC interrupts definition
 * @{
 */
#define ADC_IT_EOC  ADC_CR1_EOCIE  /*!< ADC End of Regular Conversion interrupt source */
#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
#define ADC_IT_AWD  ADC_CR1_AWDIE  /*!< ADC Analog watchdog interrupt source */
/**
 * @}
 */

/** @defgroup ADC_flags_definition ADC flags definition
 * @{
 */
#define ADC_FLAG_STRT  ADC_SR_STRT  /*!< ADC Regular group start flag */
#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
#define ADC_FLAG_EOC   ADC_SR_EOC   /*!< ADC End of Regular conversion flag */
#define ADC_FLAG_JEOC  ADC_SR_JEOC  /*!< ADC End of Injected conversion flag */
#define ADC_FLAG_AWD   ADC_SR_AWD   /*!< ADC Analog watchdog flag */
/**
 * @}
 */

/**
 * @}
 */

/* Private constants ---------------------------------------------------------*/

/** @addtogroup ADC_Private_Constants ADC Private Constants
 * @{
 */

/** @defgroup ADC_conversion_cycles ADC conversion cycles
 * @{
 */
/* ADC conversion cycles (unit: ADC clock cycles)                           */
/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
/* resolution 12 bits)                                                      */
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5    14U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5   20U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5  26U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5  41U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5  54U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5  68U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5  84U
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
/**
 * @}
 */

/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
 * @{
 */
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
  (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
  (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2)

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
  (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
  (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1)

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
  (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
  (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0)

#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
/**
 * @}
 */

/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD)

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/

/** @defgroup ADC_Exported_Macros ADC Exported Macros
 * @{
 */
/* Macro for internal HAL driver usage, and possibly can be used into code of */
/* final user.                                                                */

/**
 * @brief Enable the ADC peripheral
 * @note ADC enable requires a delay for ADC stabilization time
 *       (refer to device datasheet, parameter tSTAB)
 * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
 *       SW start on regular group.
 * @param __HANDLE__: ADC handle
 * @retval None
 */
#define __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

/**
 * @brief Disable the ADC peripheral
 * @param __HANDLE__: ADC handle
 * @retval None
 */
#define __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

/** @brief Enable the ADC end of conversion interrupt.
 * @param __HANDLE__: ADC handle
 * @param __INTERRUPT__: ADC Interrupt
 *          This parameter can be any combination of the following values:
 *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
 *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
 *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
 * @retval None
 */
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

/** @brief Disable the ADC end of conversion interrupt.
 * @param __HANDLE__: ADC handle
 * @param __INTERRUPT__: ADC Interrupt
 *          This parameter can be any combination of the following values:
 *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
 *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
 *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
 * @retval None
 */
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
 * @param __HANDLE__: ADC handle
 * @param __INTERRUPT__: ADC interrupt source to check
 *          This parameter can be any combination of the following values:
 *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
 *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
 *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
 * @retval None
 */
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

/** @brief Get the selected ADC's flag status.
 * @param __HANDLE__: ADC handle
 * @param __FLAG__: ADC flag
 *          This parameter can be any combination of the following values:
 *            @arg ADC_FLAG_STRT: ADC Regular group start flag
 *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
 *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
 *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
 *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
 * @retval None
 */
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

/** @brief Clear the ADC's pending flags
 * @param __HANDLE__: ADC handle
 * @param __FLAG__: ADC flag
 *          This parameter can be any combination of the following values:
 *            @arg ADC_FLAG_STRT: ADC Regular group start flag
 *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
 *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
 *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
 *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
 * @retval None
 */
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))

/** @brief  Reset ADC handle state
 * @param  __HANDLE__: ADC handle
 * @retval None
 */
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

/**
 * @}
 */

/* Private macro ------------------------------------------------------------*/

/** @defgroup ADC_Private_Macros ADC Private Macros
 * @{
 */
/* Macro reserved for internal HAL driver usage, not intended to be used in   */
/* code of final user.                                                        */

/**
 * @brief Verification of ADC state: enabled or disabled
 * @param __HANDLE__: ADC handle
 * @retval SET (ADC enabled) or RESET (ADC disabled)
 */
#define ADC_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON)) ? SET : RESET)

/**
 * @brief Test if conversion trigger of regular group is software start
 *        or external trigger.
 * @param __HANDLE__: ADC handle
 * @retval SET (software start) or RESET (external trigger)
 */
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)

/**
 * @brief Test if conversion trigger of injected group is software start
 *        or external trigger.
 * @param __HANDLE__: ADC handle
 * @retval SET (software start) or RESET (external trigger)
 */
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)

/**
 * @brief Simultaneously clears and sets specific bits of the handle State
 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
 *        the first parameter is the ADC handle State, the second parameter is the
 *        bit field to clear, the third and last parameter is the bit field to set.
 * @retval None
 */
#define ADC_STATE_CLR_SET MODIFY_REG

/**
 * @brief Clear ADC error code (set it to error code: "no error")
 * @param __HANDLE__: ADC handle
 * @retval None
 */
#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

/**
 * @brief Set ADC number of conversions into regular channel sequence length.
 * @param _NbrOfConversion_: Regular channel sequence length
 * @retval None
 */
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)

/**
 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
 * @param _SAMPLETIME_: Sample time parameter.
 * @param _CHANNELNB_: Channel number.
 * @retval None
 */
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_)-10)))

/**
 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
 * @param _SAMPLETIME_: Sample time parameter.
 * @param _CHANNELNB_: Channel number.
 * @retval None
 */
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))

/**
 * @brief Set the selected regular channel rank for rank between 1 and 6.
 * @param _CHANNELNB_: Channel number.
 * @param _RANKNB_: Rank number.
 * @retval None
 */
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_)-1)))

/**
 * @brief Set the selected regular channel rank for rank between 7 and 12.
 * @param _CHANNELNB_: Channel number.
 * @param _RANKNB_: Rank number.
 * @retval None
 */
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_)-7)))

/**
 * @brief Set the selected regular channel rank for rank between 13 and 16.
 * @param _CHANNELNB_: Channel number.
 * @param _RANKNB_: Rank number.
 * @retval None
 */
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_)-13)))

/**
 * @brief Set the injected sequence length.
 * @param _JSQR_JL_: Sequence length.
 * @retval None
 */
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_)-1) << ADC_JSQR_JL_Pos)

/**
 * @brief Set the selected injected channel rank
 *        Note: on STM32F1 devices, channel rank position in JSQR register
 *              is depending on total number of ranks selected into
 *              injected sequencer (ranks sequence starting from 4-JL)
 * @param _CHANNELNB_: Channel number.
 * @param _RANKNB_: Rank number.
 * @param _JSQR_JL_: Sequence length.
 * @retval None
 */
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))

/**
 * @brief Enable ADC continuous conversion mode.
 * @param _CONTINUOUS_MODE_: Continuous mode.
 * @retval None
 */
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)

/**
 * @brief Configures the number of discontinuous conversions for the regular group channels.
 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
 * @retval None
 */
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_)-1) << ADC_CR1_DISCNUM_Pos)

/**
 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
 * @param _SCAN_MODE_: Scan conversion mode.
 * @retval None
 */
/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
/*       is equivalent to ADC_SCAN_ENABLE.                                    */
#define ADC_CR1_SCAN_SET(_SCAN_MODE_) ((((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)) ? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE))

/**
 * @brief Get the maximum ADC conversion cycles on all channels.
 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
 * Approximation of sampling time within 4 ranges, returns the highest value:
 *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
 *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
 *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
 *   equal to 239.5 cycles
 * Unit: ADC clock cycles
 * @param __HANDLE__: ADC handle
 * @retval ADC conversion cycles on all channels
 */
#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                                                                                            \
  (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET))             \
       ?                                                                                                                                                                                \
                                                                                                                                                                                        \
       (((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))        \
            ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5                                                                                                                             \
            : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)                                                                                                                           \
       : ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET))     \
           || ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) \
              ? ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5                                                                                                                          \
              : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5))

#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT))

#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || ((SCAN_MODE) == ADC_SCAN_ENABLE))

#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING))

#define IS_ADC_CHANNEL(CHANNEL)                                                                                                                                                                      \
  (((CHANNEL) == ADC_CHANNEL_0) || ((CHANNEL) == ADC_CHANNEL_1) || ((CHANNEL) == ADC_CHANNEL_2) || ((CHANNEL) == ADC_CHANNEL_3) || ((CHANNEL) == ADC_CHANNEL_4) || ((CHANNEL) == ADC_CHANNEL_5)      \
   || ((CHANNEL) == ADC_CHANNEL_6) || ((CHANNEL) == ADC_CHANNEL_7) || ((CHANNEL) == ADC_CHANNEL_8) || ((CHANNEL) == ADC_CHANNEL_9) || ((CHANNEL) == ADC_CHANNEL_10) || ((CHANNEL) == ADC_CHANNEL_11) \
   || ((CHANNEL) == ADC_CHANNEL_12) || ((CHANNEL) == ADC_CHANNEL_13) || ((CHANNEL) == ADC_CHANNEL_14) || ((CHANNEL) == ADC_CHANNEL_15) || ((CHANNEL) == ADC_CHANNEL_16)                              \
   || ((CHANNEL) == ADC_CHANNEL_17))

#define IS_ADC_SAMPLE_TIME(TIME)                                                                                                                                 \
  (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || ((TIME) == ADC_SAMPLETIME_28CYCLES_5) \
   || ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || ((TIME) == ADC_SAMPLETIME_239CYCLES_5))

#define IS_ADC_REGULAR_RANK(CHANNEL)                                                                                                                                                             \
  (((CHANNEL) == ADC_REGULAR_RANK_1) || ((CHANNEL) == ADC_REGULAR_RANK_2) || ((CHANNEL) == ADC_REGULAR_RANK_3) || ((CHANNEL) == ADC_REGULAR_RANK_4) || ((CHANNEL) == ADC_REGULAR_RANK_5)         \
   || ((CHANNEL) == ADC_REGULAR_RANK_6) || ((CHANNEL) == ADC_REGULAR_RANK_7) || ((CHANNEL) == ADC_REGULAR_RANK_8) || ((CHANNEL) == ADC_REGULAR_RANK_9) || ((CHANNEL) == ADC_REGULAR_RANK_10)     \
   || ((CHANNEL) == ADC_REGULAR_RANK_11) || ((CHANNEL) == ADC_REGULAR_RANK_12) || ((CHANNEL) == ADC_REGULAR_RANK_13) || ((CHANNEL) == ADC_REGULAR_RANK_14) || ((CHANNEL) == ADC_REGULAR_RANK_15) \
   || ((CHANNEL) == ADC_REGULAR_RANK_16))

#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)                                                                                                                                                        \
  (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \
   || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC))

#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || ((CONVERSION) == ADC_INJECTED_GROUP) || ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP))

#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)

/** @defgroup ADC_range_verification ADC range verification
 * For a unique ADC resolution: 12 bits
 * @{
 */
#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
/**
 * @}
 */

/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
 * @{
 */
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
/**
 * @}
 */

/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
 * @{
 */
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
/**
 * @}
 */

/**
 * @}
 */

/* Include ADC HAL Extension module */
#include "stm32f1xx_hal_adc_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions
 * @{
 */

/** @addtogroup ADC_Exported_Functions_Group1
 * @{
 */

/* Initialization and de-initialization functions  **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void              HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void              HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
/**
 * @}
 */

/* IO operation functions  *****************************************************/

/** @addtogroup ADC_Exported_Functions_Group2
 * @{
 */

/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);

/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);

/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);

/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);

/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
/**
 * @}
 */

/* Peripheral Control functions ***********************************************/
/** @addtogroup ADC_Exported_Functions_Group3
 * @{
 */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/**
 * @}
 */

/* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4
 * @{
 */
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
 * @}
 */

/**
 * @}
 */

/* Internal HAL driver functions **********************************************/
/** @addtogroup ADC_Private_Functions
 * @{
 */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc);
void              ADC_StabilizationTime(uint32_t DelayUs);
void              ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_ADC_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_adc_ex.h
 * @author  MCD Application Team
 * @brief   Header file of ADC HAL extension module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_ADC_EX_H
#define __STM32F1xx_HAL_ADC_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup ADCEx
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
 * @{
 */

/**
 * @brief  ADC Configuration injected Channel structure definition
 * @note   Parameters of this structure are shared within 2 scopes:
 *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
 *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
 *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
 * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
 *         ADC state can be either:
 *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
 *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
 */
typedef struct {
  uint32_t InjectedChannel;         /*!< Selection of ADC channel to configure
                                         This parameter can be a value of @ref ADC_channels
                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
                                         Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
                                         Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with
                                       injection         trigger.              It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.              Refer to
                                       errata         sheet of these devices for more details. */
  uint32_t InjectedRank;            /*!< Rank in the injected group sequencer
                                         This parameter must be a value of @ref ADCEx_injected_rank
                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel
                                       setting (or parameter number of conversions can be adjusted) */
  uint32_t InjectedSamplingTime;    /*!< Sampling time value to be set for the selected channel.
                                         Unit: ADC clock cycles
                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
                                         This parameter can be a value of @ref ADC_sampling_times
                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
                                         Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
  uint32_t InjectedOffset;          /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
                                         Offset value must be a positive number.
                                         Depending of ADC resolution selected (12, 10, 8 or 6 bits),
                                         this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
  uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
                                         To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                         This parameter must be a number between Min_Data = 1 and Max_Data = 4.
                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                  configure a channel on injected group can impact the configuration of other channels previously set. */
  uint32_t
      InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive
                                        parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous
                                        mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE
                                        or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group.
                                        Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */
  uint32_t AutoInjectedConv;         /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
                                          This parameter can be set to ENABLE or DISABLE.
                                          Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
                                          Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
                                          Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
                                                To maintain JAUTO always enabled, DMA must be configured in circular mode.
                                          Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
  uint32_t ExternalTrigInjecConv;    /*!< Selects the external event used to trigger the conversion start of injected group.
                                          If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
                                          If set to external trigger source, triggering is on event rising edge.
                                          This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
                                          Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
                                                If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on
                                        the fly)    Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
} ADC_InjectionConfTypeDef;

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief  Structure definition of ADC multimode
 * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
 *         State of ADCs of the common group must be: disabled.
 */
typedef struct {
  uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
                      This parameter can be a value of @ref ADCEx_Common_mode
                      Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any
                    configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1
                    and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC
                    clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration
                    structure can have additional parameters). The equivalences are:
                              - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several
                    ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
                              - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32
                    devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */

} ADC_MultiModeTypeDef;
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
 * @{
 */

/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
 * @{
 */
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
#define ADC_INJECTED_RANK_4 0x00000004U
/**
 * @}
 */

/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
 * @{
 */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE   0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
/**
 * @}
 */

/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
 * @{
 */
/*!< List of external triggers with generic trigger name, independently of    */
/* ADC target, sorted by trigger name:                                        */

/*!< External triggers of regular group for ADC1&ADC2 only */
#define ADC_EXTERNALTRIGCONV_T1_CC1   ADC1_2_EXTERNALTRIG_T1_CC1
#define ADC_EXTERNALTRIGCONV_T1_CC2   ADC1_2_EXTERNALTRIG_T1_CC2
#define ADC_EXTERNALTRIGCONV_T2_CC2   ADC1_2_EXTERNALTRIG_T2_CC2
#define ADC_EXTERNALTRIGCONV_T3_TRGO  ADC1_2_EXTERNALTRIG_T3_TRGO
#define ADC_EXTERNALTRIGCONV_T4_CC4   ADC1_2_EXTERNALTRIG_T4_CC4
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11

#if defined(STM32F103xE) || defined(STM32F103xG)
/*!< External triggers of regular group for ADC3 only */
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
#endif /* STM32F103xE || defined STM32F103xG */

/*!< External triggers of regular group for all ADC instances */
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and   */
/*         XL-density devices.                                                */
/*         To use it on ADC or ADC2, a remap of trigger must be done from     */
/*         EXTI line 11 to TIM8_TRGO with macro:                              */
/*           __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()                           */
/*           __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()                           */

/* Note for internal constant value management: If TIM8_TRGO is available,    */
/* its definition is set to value for ADC1&ADC2 by default and changed to     */
/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
/**
 * @}
 */

/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
 * @{
 */
/*!< List of external triggers with generic trigger name, independently of    */
/* ADC target, sorted by trigger name:                                        */

/*!< External triggers of injected group for ADC1&ADC2 only */
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1   ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4   ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO  ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15

#if defined(STM32F103xE) || defined(STM32F103xG)
/*!< External triggers of injected group for ADC3 only */
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3  ADC3_EXTERNALTRIGINJEC_T4_CC3
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2  ADC3_EXTERNALTRIGINJEC_T8_CC2
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4  ADC3_EXTERNALTRIGINJEC_T5_CC4
#endif /* STM32F103xE || defined STM32F103xG */

/*!< External triggers of injected group for all ADC instances */
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4  ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and    */
/*         XL-density devices.                                                */
/*         To use it on ADC1 or ADC2, a remap of trigger must be done from    */
/*         EXTI line 11 to TIM8_CC4 with macro:                               */
/*           __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()                           */
/*           __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()                           */

/* Note for internal constant value management: If TIM8_CC4 is available,     */
/* its definition is set to value for ADC1&ADC2 by default and changed to     */
/* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
/**
 * @}
 */

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
 * @{
 */
#define ADC_MODE_INDEPENDENT               0x00000000U                     /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   ((uint32_t)(ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST                                                                                                                                                          \
  ((uint32_t)(ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling \
                                                         phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW                                                                                                                                                           \
  ((uint32_t)(ADC_CR1_DUALMOD_2)) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock \
                                     cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
#define ADC_DUALMODE_REGSIMULT   ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1)) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
#define ADC_DUALMODE_INTERLFAST                                                                                                                                                                      \
  ((uint32_t)(ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles \
                                                                             (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INTERLSLOW                                                                                                                                                        \
  ((uint32_t)(ADC_CR1_DUALMOD_3)) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter \
                                     "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
/**
 * @}
 */
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @}
 */

/* Private constants ---------------------------------------------------------*/

/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
 * @{
 */

/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
 * @{
 */
/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC    */
/* instance is available on the selected device).                             */
/* (used internally by HAL driver. To not use into HAL structure parameters)  */

/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIG_T1_CC1   0x00000000U
#define ADC1_2_EXTERNALTRIG_T1_CC2   ((uint32_t)(ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T2_CC2   ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T3_TRGO  ((uint32_t)(ADC_CR2_EXTSEL_2))
#define ADC1_2_EXTERNALTRIG_T4_CC4   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
/* XL-density devices.                                                        */
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
#endif

#if defined(STM32F103xE) || defined(STM32F103xG)
/* External triggers of regular group for ADC3 */
#define ADC3_EXTERNALTRIG_T3_CC1  ADC1_2_EXTERNALTRIG_T1_CC1
#define ADC3_EXTERNALTRIG_T2_CC3  ADC1_2_EXTERNALTRIG_T1_CC2
#define ADC3_EXTERNALTRIG_T8_CC1  ADC1_2_EXTERNALTRIG_T2_CC2
#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
#define ADC3_EXTERNALTRIG_T5_CC1  ADC1_2_EXTERNALTRIG_T4_CC4
#define ADC3_EXTERNALTRIG_T5_CC3  ADC1_2_EXTERNALTRIG_EXT_IT11
#endif

/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)(ADC_CR2_EXTSEL_1))
#define ADC1_2_3_SWSTART             ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
/**
 * @}
 */

/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
 * @{
 */
/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC    */
/* instance is available on the selected device).                             */
/* (used internally by HAL driver. To not use into HAL structure parameters)  */

/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_1))
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1   ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4   ((uint32_t)(ADC_CR2_JEXTSEL_2))
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F103xG)
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and      */
/* XL-density devices.                                                        */
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#endif

#if defined(STM32F103xE) || defined(STM32F103xG)
/* External triggers of injected group for ADC3 */
#define ADC3_EXTERNALTRIGINJEC_T4_CC3  ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define ADC3_EXTERNALTRIGINJEC_T8_CC2  ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define ADC3_EXTERNALTRIGINJEC_T8_CC4  ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define ADC3_EXTERNALTRIGINJEC_T5_CC4  ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#endif /* STM32F103xE || defined STM32F103xG */

/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4  ((uint32_t)(ADC_CR2_JEXTSEL_0))
#define ADC1_2_3_JSWSTART                  ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/

/* Private macro -------------------------------------------------------------*/

/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
 * @{
 */
/* Macro reserved for internal HAL driver usage, not intended to be used in   */
/* code of final user.                                                        */

/**
 * @brief For devices with 3 ADCs: Defines the external trigger source
 *        for regular group according to ADC into common group ADC1&ADC2 or
 *        ADC3 (some triggers with same source have different value to
 *        be programmed into ADC EXTSEL bits of CR2 register).
 *        For devices with 2 ADCs or less: this macro makes no change.
 * @param __HANDLE__: ADC handle
 * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
 * @retval External trigger to be programmed into EXTSEL bits of CR2 register
 */
#if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO) ? (ADC3_EXTERNALTRIG_T8_TRGO) : (__EXT_TRIG_CONV__)) : (__EXT_TRIG_CONV__))
#else
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
#endif /* STM32F103xE || STM32F103xG */

/**
 * @brief For devices with 3 ADCs: Defines the external trigger source
 *        for injected group according to ADC into common group ADC1&ADC2 or
 *        ADC3 (some triggers with same source have different value to
 *        be programmed into ADC JEXTSEL bits of CR2 register).
 *        For devices with 2 ADCs or less: this macro makes no change.
 * @param __HANDLE__: ADC handle
 * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
 * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
 */
#if defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
  (((((__HANDLE__)->Instance) == ADC3)) ? (((__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) ? (ADC3_EXTERNALTRIGINJEC_T8_CC4) : (__EXT_TRIG_INJECTCONV__)) : (__EXT_TRIG_INJECTCONV__))
#else
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
#endif /* STM32F103xE || STM32F103xG */

/**
 * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
 * @param __HANDLE__: ADC handle
 * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
 */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_DUALMOD) : (RESET))
#else
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) (RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
 * @param __HANDLE__: ADC handle
 * @retval None
 */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (((((__HANDLE__)->Instance) == ADC2)) ? ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) : (!RESET))
#else
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (!RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
 * @param __HANDLE__: ADC handle
 * @retval None
 */
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) ? (ADC1->CR1 & ADC_CR1_JAUTO) : (RESET))
#else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) (RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief Set handle of the other ADC sharing the common multimode settings
 * @param __HANDLE__: ADC handle
 * @param __HANDLE_OTHER_ADC__: other ADC handle
 * @retval None
 */
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)

/**
 * @brief Set handle of the ADC slave associated to the ADC master
 * On STM32F1 devices, ADC slave is always ADC2 (this can be different
 * on other STM32 devices)
 * @param __HANDLE_MASTER__: ADC master handle
 * @param __HANDLE_SLAVE__: ADC slave handle
 * @retval None
 */
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)

#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || ((CHANNEL) == ADC_INJECTED_RANK_2) || ((CHANNEL) == ADC_INJECTED_RANK_3) || ((CHANNEL) == ADC_INJECTED_RANK_4))

#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))

/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
 * @{
 */
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
/**
 * @}
 */

#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
    || defined(STM32F105xC) || defined(STM32F107xC)
#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined(STM32F101xE)
#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined(STM32F101xG)
#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                          \
  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIG(REGTRIG)                                                                                                                                                              \
  (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)     \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)   \
   || ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || ((REGTRIG) == ADC_SOFTWARE_START))
#endif

#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) \
    || defined(STM32F105xC) || defined(STM32F107xC)
#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined(STM32F101xE)
#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined(STM32F101xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG)                                                                                                                           \
  (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)      \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)   \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)   \
   || ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define IS_ADC_MODE(MODE)                                                                                                                                                                \
  (((MODE) == ADC_MODE_INDEPENDENT) || ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) \
   || ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || ((MODE) == ADC_DUALMODE_INJECSIMULT) || ((MODE) == ADC_DUALMODE_REGSIMULT) || ((MODE) == ADC_DUALMODE_INTERLFAST)               \
   || ((MODE) == ADC_DUALMODE_INTERLSLOW) || ((MODE) == ADC_DUALMODE_ALTERTRIG))
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
 * @{
 */

/* IO operation functions  *****************************************************/
/** @addtogroup ADCEx_Exported_Functions_Group1
 * @{
 */

/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);

/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);

/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
/**
 * @}
 */

/* Peripheral Control functions ***********************************************/
/** @addtogroup ADCEx_Exported_Functions_Group2
 * @{
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected);
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_ADC_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_cortex.h
 * @author  MCD Application Team
 * @brief   Header file of CORTEX HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CORTEX_H
#define __STM32F1xx_HAL_CORTEX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup CORTEX
 * @{
 */
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
 * @{
 */

#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
 * @brief  MPU Region initialization structure
 * @{
 */
typedef struct {
  uint8_t Enable;           /*!< Specifies the status of the region.
                                 This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
  uint8_t Number;           /*!< Specifies the number of the region to protect.
                                 This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
  uint32_t BaseAddress;     /*!< Specifies the base address of the region to protect.                           */
  uint8_t  Size;            /*!< Specifies the size of the region to protect.
                                 This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
  uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
  uint8_t TypeExtField;     /*!< Specifies the TEX field level.
                                 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
  uint8_t AccessPermission; /*!< Specifies the region access permission type.
                                 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
  uint8_t DisableExec;      /*!< Specifies the instruction access status.
                                 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
  uint8_t IsShareable;      /*!< Specifies the shareability status of the protected region.
                                 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
  uint8_t IsCacheable;      /*!< Specifies the cacheable status of the region protected.
                                 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
  uint8_t IsBufferable;     /*!< Specifies the bufferable status of the protected region.
                                 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
} MPU_Region_InitTypeDef;
/**
 * @}
 */
#endif /* __MPU_PRESENT */

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
 * @{
 */

/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
 * @{
 */
#define NVIC_PRIORITYGROUP_0                       \
  0x00000007U /*!< 0 bits for pre-emption priority \
                   4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1                       \
  0x00000006U /*!< 1 bits for pre-emption priority \
                   3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2                       \
  0x00000005U /*!< 2 bits for pre-emption priority \
                   2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3                       \
  0x00000004U /*!< 3 bits for pre-emption priority \
                   1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4                       \
  0x00000003U /*!< 4 bits for pre-emption priority \
                   0 bits for subpriority */
/**
 * @}
 */

/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
 * @{
 */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK      0x00000004U

/**
 * @}
 */

#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
 * @{
 */
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI      MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF      (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)

/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
 * @{
 */
#define MPU_REGION_ENABLE  ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
 * @{
 */
#define MPU_INSTRUCTION_ACCESS_ENABLE  ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
 * @{
 */
#define MPU_ACCESS_SHAREABLE     ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
 * @{
 */
#define MPU_ACCESS_CACHEABLE     ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
 * @{
 */
#define MPU_ACCESS_BUFFERABLE     ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
 * @{
 */
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
 * @{
 */
#define MPU_REGION_SIZE_32B   ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B   ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B  ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B  ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B  ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB   ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB   ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB   ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB   ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB  ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB  ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB  ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB   ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB   ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB   ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB   ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB  ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB  ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB  ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB   ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB   ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB   ((uint8_t)0x1F)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
 * @{
 */
#define MPU_REGION_NO_ACCESS   ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW     ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO     ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
 * @}
 */

/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
 * @{
 */
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
 * @}
 */
#endif /* __MPU_PRESENT */

/**
 * @}
 */

/* Exported Macros -----------------------------------------------------------*/

/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
 * @{
 */

/** @addtogroup CORTEX_Exported_Functions_Group1
 * @{
 */
/* Initialization and de-initialization functions *****************************/
void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void     HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
 * @}
 */

/** @addtogroup CORTEX_Exported_Functions_Group2
 * @{
 */
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void     HAL_SYSTICK_IRQHandler(void);
void     HAL_SYSTICK_Callback(void);

#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
 * @}
 */

/**
 * @}
 */

/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
 * @{
 */
#define IS_NVIC_PRIORITY_GROUP(GROUP) \
  (((GROUP) == NVIC_PRIORITYGROUP_0) || ((GROUP) == NVIC_PRIORITYGROUP_1) || ((GROUP) == NVIC_PRIORITYGROUP_2) || ((GROUP) == NVIC_PRIORITYGROUP_3) || ((GROUP) == NVIC_PRIORITYGROUP_4))

#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)

#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)

#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)

#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

#if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || ((STATE) == MPU_REGION_DISABLE))

#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || ((TYPE) == MPU_TEX_LEVEL1) || ((TYPE) == MPU_TEX_LEVEL2))

#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)                                                                                                                                    \
  (((TYPE) == MPU_REGION_NO_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RW) || ((TYPE) == MPU_REGION_PRIV_RW_URO) || ((TYPE) == MPU_REGION_FULL_ACCESS) || ((TYPE) == MPU_REGION_PRIV_RO) \
   || ((TYPE) == MPU_REGION_PRIV_RO_URO))

#define IS_MPU_REGION_NUMBER(NUMBER)                                                                                                                                                \
  (((NUMBER) == MPU_REGION_NUMBER0) || ((NUMBER) == MPU_REGION_NUMBER1) || ((NUMBER) == MPU_REGION_NUMBER2) || ((NUMBER) == MPU_REGION_NUMBER3) || ((NUMBER) == MPU_REGION_NUMBER4) \
   || ((NUMBER) == MPU_REGION_NUMBER5) || ((NUMBER) == MPU_REGION_NUMBER6) || ((NUMBER) == MPU_REGION_NUMBER7))

#define IS_MPU_REGION_SIZE(SIZE)                                                                                                                                                          \
  (((SIZE) == MPU_REGION_SIZE_32B) || ((SIZE) == MPU_REGION_SIZE_64B) || ((SIZE) == MPU_REGION_SIZE_128B) || ((SIZE) == MPU_REGION_SIZE_256B) || ((SIZE) == MPU_REGION_SIZE_512B)         \
   || ((SIZE) == MPU_REGION_SIZE_1KB) || ((SIZE) == MPU_REGION_SIZE_2KB) || ((SIZE) == MPU_REGION_SIZE_4KB) || ((SIZE) == MPU_REGION_SIZE_8KB) || ((SIZE) == MPU_REGION_SIZE_16KB)        \
   || ((SIZE) == MPU_REGION_SIZE_32KB) || ((SIZE) == MPU_REGION_SIZE_64KB) || ((SIZE) == MPU_REGION_SIZE_128KB) || ((SIZE) == MPU_REGION_SIZE_256KB) || ((SIZE) == MPU_REGION_SIZE_512KB) \
   || ((SIZE) == MPU_REGION_SIZE_1MB) || ((SIZE) == MPU_REGION_SIZE_2MB) || ((SIZE) == MPU_REGION_SIZE_4MB) || ((SIZE) == MPU_REGION_SIZE_8MB) || ((SIZE) == MPU_REGION_SIZE_16MB)        \
   || ((SIZE) == MPU_REGION_SIZE_32MB) || ((SIZE) == MPU_REGION_SIZE_64MB) || ((SIZE) == MPU_REGION_SIZE_128MB) || ((SIZE) == MPU_REGION_SIZE_256MB) || ((SIZE) == MPU_REGION_SIZE_512MB) \
   || ((SIZE) == MPU_REGION_SIZE_1GB) || ((SIZE) == MPU_REGION_SIZE_2GB) || ((SIZE) == MPU_REGION_SIZE_4GB))

#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */

/**
 * @}
 */

/* Private functions ---------------------------------------------------------*/

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_CORTEX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_def.h
 * @author  MCD Application Team
 * @brief   This file contains HAL common defines, enumeration, macros and
 *          structures definitions.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DEF
#define __STM32F1xx_HAL_DEF

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
#endif
#include 

/* Exported types ------------------------------------------------------------*/

/**
 * @brief  HAL Status structures definition
 */
typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef;

/**
 * @brief  HAL Lock structures definition
 */
typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef;

/* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU

#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)

#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
  do {                                                               \
    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__);             \
    (__DMA_HANDLE__).Parent         = (__HANDLE__);                  \
  } while (0U)

#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */

/** @brief Reset the Handle's State field.
 * @param __HANDLE__: specifies the Peripheral Handle.
 * @note  This macro can be used for the following purpose:
 *          - When the Handle is declared as local variable; before passing it as parameter
 *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
 *            to set to 0 the Handle's "State" field.
 *            Otherwise, "State" field may have any random value and the first time the function
 *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
 *            (i.e. HAL_PPP_MspInit() will not be executed).
 *          - When there is a need to reconfigure the low level hardware: instead of calling
 *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
 *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
 *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
 * @retval None
 */
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)

#if (USE_RTOS == 1U)
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
#else
#define __HAL_LOCK(__HANDLE__)              \
  do {                                      \
    if ((__HANDLE__)->Lock == HAL_LOCKED) { \
      return HAL_BUSY;                      \
    } else {                                \
      (__HANDLE__)->Lock = HAL_LOCKED;      \
    }                                       \
  } while (0U)

#define __HAL_UNLOCK(__HANDLE__)       \
  do {                                 \
    (__HANDLE__)->Lock = HAL_UNLOCKED; \
  } while (0U)
#endif /* USE_RTOS */

#if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */

/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined(__GNUC__) && !defined(__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__((aligned(4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined(__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined(__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */

/**
 * @brief  __RAM_FUNC definition
 */
#if defined(__CC_ARM)
/* ARM Compiler
   ------------
   RAM functions are defined using the toolchain options.
   Functions that are executed in RAM should reside in a separate source module.
   Using the 'Options for File' dialog you can simply change the 'Code / Const'
   area of a module to a memory space in physical RAM.
   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
   dialog.
*/
#define __RAM_FUNC

#elif defined(__ICCARM__)
/* ICCARM Compiler
   ---------------
   RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc

#elif defined(__GNUC__)
/* GNU Compiler
   ------------
  RAM functions are defined using a specific toolchain attribute
   "__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))

#endif

/**
 * @brief  __NOINLINE definition
 */
#if defined(__CC_ARM) || defined(__GNUC__)
/* ARM & GNUCompiler
   ----------------
*/
#define __NOINLINE __attribute__((noinline))

#elif defined(__ICCARM__)
/* ICCARM Compiler
   ---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")

#endif

#ifdef __cplusplus
}
#endif

#endif /* ___STM32F1xx_HAL_DEF */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_dma.h
 * @author  MCD Application Team
 * @brief   Header file of DMA HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_H
#define __STM32F1xx_HAL_DMA_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup DMA
 * @{
 */

/* Exported types ------------------------------------------------------------*/

/** @defgroup DMA_Exported_Types DMA Exported Types
 * @{
 */

/**
 * @brief  DMA Configuration Structure definition
 */
typedef struct {
  uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
                           from memory to memory or from peripheral to memory.
                           This parameter can be a value of @ref DMA_Data_transfer_direction */

  uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */

  uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
                        This parameter can be a value of @ref DMA_Memory_incremented_mode */

  uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
                                     This parameter can be a value of @ref DMA_Peripheral_data_size */

  uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
                                  This parameter can be a value of @ref DMA_Memory_data_size */

  uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
                      This parameter can be a value of @ref DMA_mode
                      @note The circular buffer mode cannot be used if the memory-to-memory
                            data transfer is configured on the selected Channel */

  uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
                          This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;

/**
 * @brief  HAL DMA State structures definition
 */
typedef enum {
  HAL_DMA_STATE_RESET   = 0x00U, /*!< DMA not yet initialized or disabled    */
  HAL_DMA_STATE_READY   = 0x01U, /*!< DMA initialized and ready for use      */
  HAL_DMA_STATE_BUSY    = 0x02U, /*!< DMA process is ongoing                 */
  HAL_DMA_STATE_TIMEOUT = 0x03U  /*!< DMA timeout state                      */
} HAL_DMA_StateTypeDef;

/**
 * @brief  HAL DMA Error Code structure definition
 */
typedef enum {
  HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer     */
  HAL_DMA_HALF_TRANSFER = 0x01U  /*!< Half Transfer     */
} HAL_DMA_LevelCompleteTypeDef;

/**
 * @brief  HAL DMA Callback ID structure definition
 */
typedef enum {
  HAL_DMA_XFER_CPLT_CB_ID     = 0x00U, /*!< Full transfer     */
  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer     */
  HAL_DMA_XFER_ERROR_CB_ID    = 0x02U, /*!< Error             */
  HAL_DMA_XFER_ABORT_CB_ID    = 0x03U, /*!< Abort             */
  HAL_DMA_XFER_ALL_CB_ID      = 0x04U  /*!< All               */

} HAL_DMA_CallbackIDTypeDef;

/**
 * @brief  DMA handle Structure definition
 */
typedef struct __DMA_HandleTypeDef {
  DMA_Channel_TypeDef *Instance; /*!< Register base address                  */

  DMA_InitTypeDef Init; /*!< DMA communication parameters           */

  HAL_LockTypeDef Lock; /*!< DMA locking object                     */

  HAL_DMA_StateTypeDef State; /*!< DMA transfer state                     */

  void *Parent; /*!< Parent object state                    */

  void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback         */

  void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback    */

  void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback            */

  void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback            */

  __IO uint32_t ErrorCode; /*!< DMA Error code                         */

  DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address               */

  uint32_t ChannelIndex; /*!< DMA Channel Index                      */

} DMA_HandleTypeDef;
/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup DMA_Exported_Constants DMA Exported Constants
 * @{
 */

/** @defgroup DMA_Error_Code DMA Error Code
 * @{
 */
#define HAL_DMA_ERROR_NONE          0x00000000U /*!< No error             */
#define HAL_DMA_ERROR_TE            0x00000001U /*!< Transfer error       */
#define HAL_DMA_ERROR_NO_XFER       0x00000004U /*!< no ongoing transfer  */
#define HAL_DMA_ERROR_TIMEOUT       0x00000020U /*!< Timeout error        */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode                    */
/**
 * @}
 */

/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 * @{
 */
#define DMA_PERIPH_TO_MEMORY 0x00000000U                 /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */

/**
 * @}
 */

/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 * @{
 */
#define DMA_PINC_ENABLE  ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U              /*!< Peripheral increment mode Disable */
/**
 * @}
 */

/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 * @{
 */
#define DMA_MINC_ENABLE  ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable  */
#define DMA_MINC_DISABLE 0x00000000U              /*!< Memory increment mode Disable */
/**
 * @}
 */

/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 * @{
 */
#define DMA_PDATAALIGN_BYTE     0x00000000U                 /*!< Peripheral data alignment: Byte     */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD     ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
/**
 * @}
 */

/** @defgroup DMA_Memory_data_size DMA Memory data size
 * @{
 */
#define DMA_MDATAALIGN_BYTE     0x00000000U                 /*!< Memory data alignment: Byte     */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD     ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word     */
/**
 * @}
 */

/** @defgroup DMA_mode DMA mode
 * @{
 */
#define DMA_NORMAL   0x00000000U              /*!< Normal mode                  */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode                */
/**
 * @}
 */

/** @defgroup DMA_Priority_level DMA Priority level
 * @{
 */
#define DMA_PRIORITY_LOW       0x00000000U              /*!< Priority level : Low       */
#define DMA_PRIORITY_MEDIUM    ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium    */
#define DMA_PRIORITY_HIGH      ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High      */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)   /*!< Priority level : Very_High */
/**
 * @}
 */

/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 * @{
 */
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/**
 * @}
 */

/** @defgroup DMA_flag_definitions DMA flag definitions
 * @{
 */
#define DMA_FLAG_GL1 0x00000001U
#define DMA_FLAG_TC1 0x00000002U
#define DMA_FLAG_HT1 0x00000004U
#define DMA_FLAG_TE1 0x00000008U
#define DMA_FLAG_GL2 0x00000010U
#define DMA_FLAG_TC2 0x00000020U
#define DMA_FLAG_HT2 0x00000040U
#define DMA_FLAG_TE2 0x00000080U
#define DMA_FLAG_GL3 0x00000100U
#define DMA_FLAG_TC3 0x00000200U
#define DMA_FLAG_HT3 0x00000400U
#define DMA_FLAG_TE3 0x00000800U
#define DMA_FLAG_GL4 0x00001000U
#define DMA_FLAG_TC4 0x00002000U
#define DMA_FLAG_HT4 0x00004000U
#define DMA_FLAG_TE4 0x00008000U
#define DMA_FLAG_GL5 0x00010000U
#define DMA_FLAG_TC5 0x00020000U
#define DMA_FLAG_HT5 0x00040000U
#define DMA_FLAG_TE5 0x00080000U
#define DMA_FLAG_GL6 0x00100000U
#define DMA_FLAG_TC6 0x00200000U
#define DMA_FLAG_HT6 0x00400000U
#define DMA_FLAG_TE6 0x00800000U
#define DMA_FLAG_GL7 0x01000000U
#define DMA_FLAG_TC7 0x02000000U
#define DMA_FLAG_HT7 0x04000000U
#define DMA_FLAG_TE7 0x08000000U
/**
 * @}
 */

/**
 * @}
 */

/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
 * @{
 */

/** @brief  Reset DMA handle state.
 * @param  __HANDLE__: DMA handle
 * @retval None
 */
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

/**
 * @brief  Enable the specified DMA Channel.
 * @param  __HANDLE__: DMA handle
 * @retval None
 */
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))

/**
 * @brief  Disable the specified DMA Channel.
 * @param  __HANDLE__: DMA handle
 * @retval None
 */
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))

/* Interrupt & Flag management */

/**
 * @brief  Enables the specified DMA Channel interrupts.
 * @param  __HANDLE__: DMA handle
 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 *            @arg DMA_IT_TE:  Transfer error interrupt mask
 * @retval None
 */
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))

/**
 * @brief  Disable the specified DMA Channel interrupts.
 * @param  __HANDLE__: DMA handle
 * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 *            @arg DMA_IT_TE:  Transfer error interrupt mask
 * @retval None
 */
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))

/**
 * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
 * @param  __HANDLE__: DMA handle
 * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 *          This parameter can be one of the following values:
 *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 *            @arg DMA_IT_TE:  Transfer error interrupt mask
 * @retval The state of DMA_IT (SET or RESET).
 */
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

/**
 * @brief  Return the number of remaining data units in the current DMA Channel transfer.
 * @param  __HANDLE__: DMA handle
 * @retval The number of remaining data units in the current DMA Channel transfer.
 */
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)

/**
 * @}
 */

/* Include DMA HAL Extension module */
#include "stm32f1xx_hal_dma_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
 * @{
 */

/** @addtogroup DMA_Exported_Functions_Group1
 * @{
 */
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
 * @}
 */

/** @addtogroup DMA_Exported_Functions_Group2
 * @{
 */
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);

/**
 * @}
 */

/** @addtogroup DMA_Exported_Functions_Group3
 * @{
 */
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
 * @}
 */

/**
 * @}
 */

/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
 * @{
 */

#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))

#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || ((STATE) == DMA_PINC_DISABLE))

#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || ((STATE) == DMA_MINC_DISABLE))

#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || ((SIZE) == DMA_PDATAALIGN_HALFWORD) || ((SIZE) == DMA_PDATAALIGN_WORD))

#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || ((SIZE) == DMA_MDATAALIGN_HALFWORD) || ((SIZE) == DMA_MDATAALIGN_WORD))

#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL) || ((MODE) == DMA_CIRCULAR))

#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW) || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_HIGH) || ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

/**
 * @}
 */

/* Private functions ---------------------------------------------------------*/

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_DMA_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_dma_ex.h
 * @author  MCD Application Team
 * @brief   Header file of DMA HAL extension module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_EX_H
#define __STM32F1xx_HAL_DMA_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup DMAEx DMAEx
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
 * @{
 */
/* Interrupt & Flag management */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
 * @{
 */

/**
 * @brief  Returns the current DMA Channel transfer complete flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer complete flag index.
 */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_TC1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TC7 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TC1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TC2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TC3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TC4 \
                                                                       : DMA_FLAG_TC5)

/**
 * @brief  Returns the current DMA Channel half transfer complete flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified half transfer complete flag index.
 */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_HT1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_HT7 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_HT1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_HT2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_HT3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_HT4 \
                                                                       : DMA_FLAG_HT5)

/**
 * @brief  Returns the current DMA Channel transfer error flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer error flag index.
 */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_TE1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_TE7 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_TE1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_TE2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_TE3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_TE4 \
                                                                       : DMA_FLAG_TE5)

/**
 * @brief  Return the current DMA Channel Global interrupt flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer error flag index.
 */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_GL1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7)) ? DMA_FLAG_GL7 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1)) ? DMA_FLAG_GL1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2)) ? DMA_FLAG_GL2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3)) ? DMA_FLAG_GL3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4)) ? DMA_FLAG_GL4 \
                                                                       : DMA_FLAG_GL5)

/**
 * @brief  Get the DMA Channel pending flags.
 * @param  __HANDLE__: DMA handle
 * @param  __FLAG__: Get the specified flag.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_FLAG_TCx:  Transfer complete flag
 *            @arg DMA_FLAG_HTx:  Half transfer complete flag
 *            @arg DMA_FLAG_TEx:  Transfer error flag
 *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
 * @retval The state of FLAG (SET or RESET).
 */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

/**
 * @brief  Clears the DMA Channel pending flags.
 * @param  __HANDLE__: DMA handle
 * @param  __FLAG__: specifies the flag to clear.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_FLAG_TCx:  Transfer complete flag
 *            @arg DMA_FLAG_HTx:  Half transfer complete flag
 *            @arg DMA_FLAG_TEx:  Transfer error flag
 *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
 * @retval None
 */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7) ? (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))

/**
 * @}
 */

#else
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
 * @{
 */

/**
 * @brief  Returns the current DMA Channel transfer complete flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer complete flag index.
 */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_TC1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TC2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TC3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TC4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TC5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TC6 \
                                                                       : DMA_FLAG_TC7)

/**
 * @brief  Return the current DMA Channel half transfer complete flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified half transfer complete flag index.
 */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_HT1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_HT2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_HT3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_HT4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_HT5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_HT6 \
                                                                       : DMA_FLAG_HT7)

/**
 * @brief  Return the current DMA Channel transfer error flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer error flag index.
 */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_TE1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_TE2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_TE3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_TE4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_TE5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_TE6 \
                                                                       : DMA_FLAG_TE7)

/**
 * @brief  Return the current DMA Channel Global interrupt flag.
 * @param  __HANDLE__: DMA handle
 * @retval The specified transfer error flag index.
 */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)                                       \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))   ? DMA_FLAG_GL1 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2)) ? DMA_FLAG_GL2 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3)) ? DMA_FLAG_GL3 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4)) ? DMA_FLAG_GL4 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5)) ? DMA_FLAG_GL5 \
   : ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6)) ? DMA_FLAG_GL6 \
                                                                       : DMA_FLAG_GL7)

/**
 * @brief  Get the DMA Channel pending flags.
 * @param  __HANDLE__: DMA handle
 * @param  __FLAG__: Get the specified flag.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_FLAG_TCx:  Transfer complete flag
 *            @arg DMA_FLAG_HTx:  Half transfer complete flag
 *            @arg DMA_FLAG_TEx:  Transfer error flag
 *            @arg DMA_FLAG_GLx:  Global interrupt flag
 *         Where x can be 1_7 to select the DMA Channel flag.
 * @retval The state of FLAG (SET or RESET).
 */

#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))

/**
 * @brief  Clear the DMA Channel pending flags.
 * @param  __HANDLE__: DMA handle
 * @param  __FLAG__: specifies the flag to clear.
 *          This parameter can be any combination of the following values:
 *            @arg DMA_FLAG_TCx:  Transfer complete flag
 *            @arg DMA_FLAG_HTx:  Half transfer complete flag
 *            @arg DMA_FLAG_TEx:  Transfer error flag
 *            @arg DMA_FLAG_GLx:  Global interrupt flag
 *         Where x can be 1_7 to select the DMA Channel flag.
 * @retval None
 */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))

/**
 * @}
 */

#endif

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
       /* STM32F103xG || STM32F105xC || STM32F107xC */

#endif /* __STM32F1xx_HAL_DMA_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_flash.h
 * @author  MCD Application Team
 * @brief   Header file of Flash HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_FLASH_H
#define __STM32F1xx_HAL_FLASH_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup FLASH
 * @{
 */

/** @addtogroup FLASH_Private_Constants
 * @{
 */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
 * @}
 */

/** @addtogroup FLASH_Private_Macros
 * @{
 */

#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || ((VALUE) == FLASH_TYPEPROGRAM_WORD) || ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))

#if defined(FLASH_ACR_LATENCY)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || ((__LATENCY__) == FLASH_LATENCY_1) || ((__LATENCY__) == FLASH_LATENCY_2))

#else
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
#endif /* FLASH_ACR_LATENCY */
/**
 * @}
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
 * @{
 */

/**
 * @brief  FLASH Procedure structure definition
 */
typedef enum {
  FLASH_PROC_NONE              = 0U,
  FLASH_PROC_PAGEERASE         = 1U,
  FLASH_PROC_MASSERASE         = 2U,
  FLASH_PROC_PROGRAMHALFWORD   = 3U,
  FLASH_PROC_PROGRAMWORD       = 4U,
  FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef;

/**
 * @brief  FLASH handle Structure definition
 */
typedef struct {
  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */

  __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */

  __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */

  __IO uint64_t Data; /*!< Internal variable to save data to be programmed */

  HAL_LockTypeDef Lock; /*!< FLASH locking object                */

  __IO uint32_t ErrorCode; /*!< FLASH error code
                                This parameter can be a value of @ref FLASH_Error_Codes  */
} FLASH_ProcessTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
 * @{
 */

/** @defgroup FLASH_Error_Codes FLASH Error Codes
 * @{
 */

#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP  0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */

/**
 * @}
 */

/** @defgroup FLASH_Type_Program FLASH Type Program
 * @{
 */
#define FLASH_TYPEPROGRAM_HALFWORD   0x01U /*!ACR |= FLASH_ACR_HLFCYA)

/**
  * @brief  Disable the FLASH half cycle access.
  * @note   half cycle access can only be used with a low-frequency clock of less than
            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
  * @retval None
  */
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))

/**
 * @}
 */

#if defined(FLASH_ACR_LATENCY)
/** @defgroup FLASH_EM_Latency FLASH Latency
 *  @brief macros to handle FLASH Latency
 * @{
 */

/**
 * @brief  Set the FLASH Latency.
 * @param  __LATENCY__ FLASH Latency
 *         The value of this parameter depend on device used within the same series
 * @retval None
 */
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__))

/**
 * @brief  Get the FLASH Latency.
 * @retval FLASH Latency
 *         The value of this parameter depend on device used within the same series
 */
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

/**
 * @}
 */

#endif /* FLASH_ACR_LATENCY */
/** @defgroup FLASH_Prefetch FLASH Prefetch
 *  @brief macros to handle FLASH Prefetch buffer
 * @{
 */
/**
 * @brief  Enable the FLASH prefetch buffer.
 * @retval None
 */
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)

/**
 * @brief  Disable the FLASH prefetch buffer.
 * @retval None
 */
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))

/**
 * @}
 */

/**
 * @}
 */

/* Include FLASH HAL Extended module */
#include "stm32f1xx_hal_flash_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
 * @{
 */

/** @addtogroup FLASH_Exported_Functions_Group1
 * @{
 */
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);

/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);

/**
 * @}
 */

/** @addtogroup FLASH_Exported_Functions_Group2
 * @{
 */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
void              HAL_FLASH_OB_Launch(void);

/**
 * @}
 */

/** @addtogroup FLASH_Exported_Functions_Group3
 * @{
 */
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);

/**
 * @}
 */

/**
 * @}
 */

/* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
 * @{
 */
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#if defined(FLASH_BANK2_END)
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* FLASH_BANK2_END */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_FLASH_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_flash_ex.h
 * @author  MCD Application Team
 * @brief   Header file of Flash HAL Extended module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_FLASH_EX_H
#define __STM32F1xx_HAL_FLASH_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup FLASHEx
 * @{
 */

/** @addtogroup FLASHEx_Private_Constants
 * @{
 */

#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
#define OBR_REG_INDEX            1U
#define SR_FLAG_MASK             ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))

/**
 * @}
 */

/** @addtogroup FLASHEx_Private_Macros
 * @{
 */

#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))

#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))

#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))

#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))

#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))

#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

#if defined(FLASH_BANK2_END)
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
#endif /* FLASH_BANK2_END */

/* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */

/* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                                  \
  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                      \
       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU)        \
       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U)               \
              ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU) \
              : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08007FFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x08003FFFU))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/

/* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U)              \
       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0807FFFFU) \
       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0805FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU)))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */

/* XL Density */
#if defined(FLASH_BANK2_END)
#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES) \
  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080FFFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x080BFFFFU))
#endif /* FLASH_BANK2_END */

/* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)                           \
  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U)              \
       ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0803FFFFU) \
       : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0801FFFFU) : ((ADDRESS) + ((NBPAGES)*FLASH_PAGE_SIZE) - 1 <= 0x0800FFFFU)))
#endif /* STM32F105xC || STM32F107xC */

#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))

#if defined(FLASH_BANK2_END)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || ((BANK) == FLASH_BANK_2) || ((BANK) == FLASH_BANK_BOTH))
#else
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#endif /* FLASH_BANK2_END */

/* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))

#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */

/* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                      \
  (((ADDRESS) >= FLASH_BASE)                                                                   \
   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U)                                    \
           ? ((ADDRESS) <= FLASH_BANK1_END)                                                    \
           : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS) <= 0x0800FFFF) \
                                                                   : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))

#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/

/* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
  (((ADDRESS) >= FLASH_BASE)                                                                  \
   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS) <= FLASH_BANK1_END) \
                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))

#endif /* STM32F100xE || STM32F101xE || STM32F103xE */

/* XL Density */
#if defined(FLASH_BANK2_END)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))

#endif /* FLASH_BANK2_END */

/* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)                                                     \
  (((ADDRESS) >= FLASH_BASE)                                                                  \
   && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS) <= FLASH_BANK1_END) \
                                                             : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))

#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
 * @{
 */

/**
 * @brief  FLASH Erase structure definition
 */
typedef struct {
  uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
                           This parameter can be a value of @ref FLASHEx_Type_Erase */

  uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
                       This parameter must be a value of @ref FLASHEx_Banks */

  uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
                             This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
                             (x = 1 or 2 depending on devices)*/

  uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
                         This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/

} FLASH_EraseInitTypeDef;

/**
 * @brief  FLASH Options bytes program structure definition
 */
typedef struct {
  uint32_t OptionType; /*!< OptionType: Option byte to be configured.
                            This parameter can be a value of @ref FLASHEx_OB_Type */

  uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
                          This parameter can be a value of @ref FLASHEx_OB_WRP_State */

  uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
                         This parameter can be a value of @ref FLASHEx_OB_Write_Protection */

  uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
                       This parameter must be a value of @ref FLASHEx_Banks */

  uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
                         This parameter can be a value of @ref FLASHEx_OB_Read_Protection */

#if defined(FLASH_BANK2_END)
  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
                           IWDG / STOP / STDBY / BOOT1
                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
                           @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
#else
  uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
                           IWDG / STOP / STDBY
                           This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
                           @ref FLASHEx_OB_nRST_STDBY */
#endif /* FLASH_BANK2_END */

  uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
                             This parameter can be a value of @ref FLASHEx_OB_Data_Address */

  uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
} FLASH_OBProgramInitTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
 * @{
 */

/** @defgroup FLASHEx_Constants FLASH Constants
 * @{
 */

/** @defgroup FLASHEx_Page_Size Page Size
 * @{
 */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
#define FLASH_PAGE_SIZE 0x400U
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */

#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
#define FLASH_PAGE_SIZE 0x800U
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
       /* STM32F101xG || STM32F103xG */
       /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/** @defgroup FLASHEx_Type_Erase Type Erase
 * @{
 */
#define FLASH_TYPEERASE_PAGES     0x00U /*!CR, ((__INTERRUPT__)&0x0000FFFFU)); \
    /* Enable Bank2 IT */                              \
    SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
  } while (0U)

/**
 * @brief  Disable the specified FLASH interrupt.
 * @param  __INTERRUPT__  FLASH interrupt
 *     This parameter can be any combination of the following values:
 *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
 *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
 *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
 *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
 * @retval none
 */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)            \
  do {                                                   \
    /* Disable Bank1 IT */                               \
    CLEAR_BIT(FLASH->CR, ((__INTERRUPT__)&0x0000FFFFU)); \
    /* Disable Bank2 IT */                               \
    CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U));     \
  } while (0U)

/**
 * @brief  Get the specified FLASH flag status.
 * @param  __FLAG__ specifies the FLASH flag to check.
 *          This parameter can be one of the following values:
 *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
 *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
 *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
 *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
 *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
 *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
 *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
 *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
 *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
 * @retval The new state of __FLAG__ (SET or RESET).
 */
#define __HAL_FLASH_GET_FLAG(__FLAG__) \
  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : ((((__FLAG__)&SR_FLAG_MASK) != RESET) ? (FLASH->SR & ((__FLAG__)&SR_FLAG_MASK)) : (FLASH->SR2 & ((__FLAG__) >> 16U))))

/**
 * @brief  Clear the specified FLASH flag.
 * @param  __FLAG__ specifies the FLASH flags to clear.
 *          This parameter can be any combination of the following values:
 *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
 *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
 *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
 *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
 *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
 *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
 *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
 *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
 *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
 * @retval none
 */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        \
  do {                                          \
    /* Clear FLASH_FLAG_OPTVERR flag */         \
    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {     \
      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR);  \
    } else {                                    \
      /* Clear Flag in Bank1 */                 \
      if (((__FLAG__)&SR_FLAG_MASK) != RESET) { \
        FLASH->SR = ((__FLAG__)&SR_FLAG_MASK);  \
      }                                         \
      /* Clear Flag in Bank2 */                 \
      if (((__FLAG__) >> 16U) != RESET) {       \
        FLASH->SR2 = ((__FLAG__) >> 16U);       \
      }                                         \
    }                                           \
  } while (0U)
#else
                      /**
                       * @brief  Enable the specified FLASH interrupt.
                       * @param  __INTERRUPT__  FLASH interrupt
                       *         This parameter can be any combination of the following values:
                       *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
                       *     @arg @ref FLASH_IT_ERR Error Interrupt
                       * @retval none
                       */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))

/**
 * @brief  Disable the specified FLASH interrupt.
 * @param  __INTERRUPT__  FLASH interrupt
 *         This parameter can be any combination of the following values:
 *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
 *     @arg @ref FLASH_IT_ERR Error Interrupt
 * @retval none
 */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))

/**
 * @brief  Get the specified FLASH flag status.
 * @param  __FLAG__ specifies the FLASH flag to check.
 *          This parameter can be one of the following values:
 *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
 *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
 *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
 *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
 *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
 * @retval The new state of __FLAG__ (SET or RESET).
 */
#define __HAL_FLASH_GET_FLAG(__FLAG__)        (((__FLAG__) == FLASH_FLAG_OPTVERR) ? (FLASH->OBR & FLASH_OBR_OPTERR) : (FLASH->SR & (__FLAG__)))
/**
 * @brief  Clear the specified FLASH flag.
 * @param  __FLAG__ specifies the FLASH flags to clear.
 *          This parameter can be any combination of the following values:
 *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
 *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
 *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
 *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
 * @retval none
 */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)       \
  do {                                         \
    /* Clear FLASH_FLAG_OPTVERR flag */        \
    if ((__FLAG__) == FLASH_FLAG_OPTVERR) {    \
      CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
    } else {                                   \
      /* Clear Flag in Bank1 */                \
      FLASH->SR = (__FLAG__);                  \
    }                                          \
  } while (0U)

#endif

/**
 * @}
 */

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
 * @{
 */

/** @addtogroup FLASHEx_Exported_Functions_Group1
 * @{
 */
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);

/**
 * @}
 */

/** @addtogroup FLASHEx_Exported_Functions_Group2
 * @{
 */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
uint32_t          HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */
#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_FLASH_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_gpio.h
 * @author  MCD Application Team
 * @brief   Header file of GPIO HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_GPIO_H
#define __STM32F1xx_HAL_GPIO_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup GPIO
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
 * @{
 */

/**
 * @brief GPIO Init structure definition
 */
typedef struct {
  uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
                     This parameter can be any value of @ref GPIO_pins_define */

  uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
                      This parameter can be a value of @ref GPIO_mode_define */

  uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
                      This parameter can be a value of @ref GPIO_pull_define */

  uint32_t Speed; /*!< Specifies the speed for the selected pins.
                       This parameter can be a value of @ref GPIO_speed_define */
} GPIO_InitTypeDef;

/**
 * @brief  GPIO Bit SET and Bit RESET enumeration
 */
typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState;
/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
 * @{
 */

/** @defgroup GPIO_pins_define GPIO pins define
 * @{
 */
#define GPIO_PIN_0   ((uint16_t)0x0001) /* Pin 0 selected    */
#define GPIO_PIN_1   ((uint16_t)0x0002) /* Pin 1 selected    */
#define GPIO_PIN_2   ((uint16_t)0x0004) /* Pin 2 selected    */
#define GPIO_PIN_3   ((uint16_t)0x0008) /* Pin 3 selected    */
#define GPIO_PIN_4   ((uint16_t)0x0010) /* Pin 4 selected    */
#define GPIO_PIN_5   ((uint16_t)0x0020) /* Pin 5 selected    */
#define GPIO_PIN_6   ((uint16_t)0x0040) /* Pin 6 selected    */
#define GPIO_PIN_7   ((uint16_t)0x0080) /* Pin 7 selected    */
#define GPIO_PIN_8   ((uint16_t)0x0100) /* Pin 8 selected    */
#define GPIO_PIN_9   ((uint16_t)0x0200) /* Pin 9 selected    */
#define GPIO_PIN_10  ((uint16_t)0x0400) /* Pin 10 selected   */
#define GPIO_PIN_11  ((uint16_t)0x0800) /* Pin 11 selected   */
#define GPIO_PIN_12  ((uint16_t)0x1000) /* Pin 12 selected   */
#define GPIO_PIN_13  ((uint16_t)0x2000) /* Pin 13 selected   */
#define GPIO_PIN_14  ((uint16_t)0x4000) /* Pin 14 selected   */
#define GPIO_PIN_15  ((uint16_t)0x8000) /* Pin 15 selected   */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
/**
 * @}
 */

/** @defgroup GPIO_mode_define GPIO mode define
 * @brief GPIO Configuration Mode
 *        Elements values convention: 0xX0yz00YZ
 *           - X  : GPIO mode or EXTI Mode
 *           - y  : External IT or Event trigger detection
 *           - z  : IO configuration on External IT or Event
 *           - Y  : Output type (Push Pull or Open Drain)
 *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
 * @{
 */
#define GPIO_MODE_INPUT     0x00000000U     /*!< Input Floating Mode                   */
#define GPIO_MODE_OUTPUT_PP 0x00000001U     /*!< Output Push Pull Mode                 */
#define GPIO_MODE_OUTPUT_OD 0x00000011U     /*!< Output Open Drain Mode                */
#define GPIO_MODE_AF_PP     0x00000002U     /*!< Alternate Function Push Pull Mode     */
#define GPIO_MODE_AF_OD     0x00000012U     /*!< Alternate Function Open Drain Mode    */
#define GPIO_MODE_AF_INPUT  GPIO_MODE_INPUT /*!< Alternate Function Input Mode         */

#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode  */

#define GPIO_MODE_IT_RISING         0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection          */
#define GPIO_MODE_IT_FALLING        0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection         */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */

#define GPIO_MODE_EVT_RISING         0x10120000U /*!< External Event Mode with Rising edge trigger detection               */
#define GPIO_MODE_EVT_FALLING        0x10220000U /*!< External Event Mode with Falling edge trigger detection              */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection       */

/**
 * @}
 */

/** @defgroup GPIO_speed_define  GPIO speed define
 * @brief GPIO Output Maximum frequency
 * @{
 */
#define GPIO_SPEED_FREQ_LOW    (GPIO_CRL_MODE0_1) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH   (GPIO_CRL_MODE0)   /*!< High speed */

/**
 * @}
 */

/** @defgroup GPIO_pull_define GPIO pull define
 * @brief GPIO Pull-Up or Pull-Down Activation
 * @{
 */
#define GPIO_NOPULL   0x00000000U /*!< No Pull-up or Pull-down activation  */
#define GPIO_PULLUP   0x00000001U /*!< Pull-up activation                  */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation                */
/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
 * @{
 */

/**
 * @brief  Checks whether the specified EXTI line flag is set or not.
 * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
 *         This parameter can be GPIO_PIN_x where x can be(0..15)
 * @retval The new state of __EXTI_LINE__ (SET or RESET).
 */
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))

/**
 * @brief  Clears the EXTI's line pending flags.
 * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
 *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
 * @retval None
 */
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))

/**
 * @brief  Checks whether the specified EXTI line is asserted or not.
 * @param  __EXTI_LINE__: specifies the EXTI line to check.
 *          This parameter can be GPIO_PIN_x where x can be(0..15)
 * @retval The new state of __EXTI_LINE__ (SET or RESET).
 */
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))

/**
 * @brief  Clears the EXTI's line pending bits.
 * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
 *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
 * @retval None
 */
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))

/**
 * @brief  Generates a Software interrupt on selected EXTI line.
 * @param  __EXTI_LINE__: specifies the EXTI line to check.
 *          This parameter can be GPIO_PIN_x where x can be(0..15)
 * @retval None
 */
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/**
 * @}
 */

/* Include GPIO HAL Extension module */
#include "stm32f1xx_hal_gpio_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
 * @{
 */

/** @addtogroup GPIO_Exported_Functions_Group1
 * @{
 */
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
 * @}
 */

/** @addtogroup GPIO_Exported_Functions_Group2
 * @{
 */
/* IO operation functions *****************************************************/
GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);

/**
 * @}
 */

/**
 * @}
 */
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
 * @{
 */

/**
 * @}
 */

/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
 * @{
 */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN)           ((((PIN)&GPIO_PIN_MASK) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE)                                                                                                                                                                             \
  (((MODE) == GPIO_MODE_INPUT) || ((MODE) == GPIO_MODE_OUTPUT_PP) || ((MODE) == GPIO_MODE_OUTPUT_OD) || ((MODE) == GPIO_MODE_AF_PP) || ((MODE) == GPIO_MODE_AF_OD) || ((MODE) == GPIO_MODE_IT_RISING)  \
   || ((MODE) == GPIO_MODE_IT_FALLING) || ((MODE) == GPIO_MODE_IT_RISING_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING) || ((MODE) == GPIO_MODE_EVT_FALLING) || ((MODE) == GPIO_MODE_EVT_RISING_FALLING) \
   || ((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(PULL)   (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || ((PULL) == GPIO_PULLDOWN))
/**
 * @}
 */

/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions GPIO Private Functions
 * @{
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_GPIO_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_gpio_ex.h
 * @author  MCD Application Team
 * @brief   Header file of GPIO HAL Extension module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_GPIO_EX_H
#define __STM32F1xx_HAL_GPIO_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup GPIOEx GPIOEx
 * @{
 */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
 * @{
 */

/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
 * @brief This section propose definition to use the Cortex EVENTOUT signal.
 * @{
 */

/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
 * @{
 */

#define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0  /*!< EVENTOUT on pin 0 */
#define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1  /*!< EVENTOUT on pin 1 */
#define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2  /*!< EVENTOUT on pin 2 */
#define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3  /*!< EVENTOUT on pin 3 */
#define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4  /*!< EVENTOUT on pin 4 */
#define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5  /*!< EVENTOUT on pin 5 */
#define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6  /*!< EVENTOUT on pin 6 */
#define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7  /*!< EVENTOUT on pin 7 */
#define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8  /*!< EVENTOUT on pin 8 */
#define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9  /*!< EVENTOUT on pin 9 */
#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */

#define IS_AFIO_EVENTOUT_PIN(__PIN__)                                                                                                                                                                 \
  (((__PIN__) == AFIO_EVENTOUT_PIN_0) || ((__PIN__) == AFIO_EVENTOUT_PIN_1) || ((__PIN__) == AFIO_EVENTOUT_PIN_2) || ((__PIN__) == AFIO_EVENTOUT_PIN_3) || ((__PIN__) == AFIO_EVENTOUT_PIN_4)         \
   || ((__PIN__) == AFIO_EVENTOUT_PIN_5) || ((__PIN__) == AFIO_EVENTOUT_PIN_6) || ((__PIN__) == AFIO_EVENTOUT_PIN_7) || ((__PIN__) == AFIO_EVENTOUT_PIN_8) || ((__PIN__) == AFIO_EVENTOUT_PIN_9)      \
   || ((__PIN__) == AFIO_EVENTOUT_PIN_10) || ((__PIN__) == AFIO_EVENTOUT_PIN_11) || ((__PIN__) == AFIO_EVENTOUT_PIN_12) || ((__PIN__) == AFIO_EVENTOUT_PIN_13) || ((__PIN__) == AFIO_EVENTOUT_PIN_14) \
   || ((__PIN__) == AFIO_EVENTOUT_PIN_15))
/**
 * @}
 */

/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
 * @{
 */

#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */

#define IS_AFIO_EVENTOUT_PORT(__PORT__) \
  (((__PORT__) == AFIO_EVENTOUT_PORT_A) || ((__PORT__) == AFIO_EVENTOUT_PORT_B) || ((__PORT__) == AFIO_EVENTOUT_PORT_C) || ((__PORT__) == AFIO_EVENTOUT_PORT_D) || ((__PORT__) == AFIO_EVENTOUT_PORT_E))
/**
 * @}
 */

/**
 * @}
 */

/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
 * @brief This section propose definition to remap the alternate function to some other port/pins.
 * @{
 */

/**
 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
 * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
 * @retval None
 */
#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)

/**
 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
 * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
 * @retval None
 */
#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)

/**
 * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
 * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
 * @retval None
 */
#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)

/**
 * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
 * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
 * @retval None
 */
#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)

/**
 * @brief Enable the remapping of USART1 alternate function TX and RX.
 * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)

/**
 * @brief Disable the remapping of USART1 alternate function TX and RX.
 * @note  DISABLE: No remap (TX/PA9, RX/PA10)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)

/**
 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
 * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)

/**
 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
 * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)

/**
 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
 * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
 * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)

/**
 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
 * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
 * @retval None
 */
#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)

/**
 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)

/**
 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
 * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
 * @note  TIM3_ETR on PE0 is not re-mapped.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
 * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
 * @note  TIM3_ETR on PE0 is not re-mapped.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)

/**
 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
 * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
 * @note  TIM3_ETR on PE0 is not re-mapped.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)

/**
 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
 * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
 * @note  TIM4_ETR on PE0 is not re-mapped.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)

/**
 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
 * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
 * @note  TIM4_ETR on PE0 is not re-mapped.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)

#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)

/**
 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
 * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
 * @retval None
 */
#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)

/**
 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
 * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
 * @retval None
 */
#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)

/**
 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
 * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
 * @retval None
 */
#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)

#endif

/**
 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
 *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
 *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
 *        on 100-pin and 144-pin packages, no need for remapping).
 * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
 * @retval None
 */
#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)

/**
 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
 *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
 *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
 *        on 100-pin and 144-pin packages, no need for remapping).
 * @note  DISABLE: No remapping of PD0 and PD1
 * @retval None
 */
#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)

#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
/**
 * @brief Enable the remapping of TIM5CH4.
 * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
 * @note  This function is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)

/**
 * @brief Disable the remapping of TIM5CH4.
 * @note  DISABLE: TIM5_CH4 is connected to PA3
 * @note  This function is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
#endif

#if defined(AFIO_MAPR_ETH_REMAP)
/**
 * @brief Enable the remapping of Ethernet MAC connections with the PHY.
 * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)

/**
 * @brief Disable the remapping of Ethernet MAC connections with the PHY.
 * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
#endif

#if defined(AFIO_MAPR_CAN2_REMAP)

/**
 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
 * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)

/**
 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
 * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
#endif

#if defined(AFIO_MAPR_MII_RMII_SEL)
/**
 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
 * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)

/**
 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
 * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
#endif

/**
 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
 * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)

/**
 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
 * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)

/**
 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
 * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)

/**
 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
 * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)

#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)

/**
 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
 * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)

/**
 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
 * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
#endif

#if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP)

/**
 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)

/**
 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
 * @retval None
 */
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
#endif

/**
 * @brief Enable the Serial wire JTAG configuration
 * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
 * @retval None
 */
#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)

/**
 * @brief Enable the Serial wire JTAG configuration
 * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
 * @retval None
 */
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)

/**
 * @brief Enable the Serial wire JTAG configuration
 * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
 * @retval None
 */

#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)

/**
 * @brief Disable the Serial wire JTAG configuration
 * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
 * @retval None
 */
#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)

#if defined(AFIO_MAPR_SPI3_REMAP)

/**
 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
 * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)

/**
 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
 * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
#endif

#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)

/**
 * @brief Control of TIM2_ITR1 internal mapping.
 * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)

/**
 * @brief Control of TIM2_ITR1 internal mapping.
 * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
#endif

#if defined(AFIO_MAPR_PTP_PPS_REMAP)

/**
 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 * @note  ENABLE: PTP_PPS is output on PB5 pin.
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)

/**
 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 * @note  DISABLE: PTP_PPS not output on PB5 pin.
 * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 * @retval None
 */
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM9_REMAP)

/**
 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
 * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)

/**
 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
 * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM10_REMAP)

/**
 * @brief Enable the remapping of TIM10_CH1.
 * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)

/**
 * @brief Disable the remapping of TIM10_CH1.
 * @note  DISABLE: No remap (TIM10_CH1 on PB8).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM11_REMAP)
/**
 * @brief Enable the remapping of TIM11_CH1.
 * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)

/**
 * @brief Disable the remapping of TIM11_CH1.
 * @note  DISABLE: No remap (TIM11_CH1 on PB9).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM13_REMAP)

/**
 * @brief Enable the remapping of TIM13_CH1.
 * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)

/**
 * @brief Disable the remapping of TIM13_CH1.
 * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM14_REMAP)

/**
 * @brief Enable the remapping of TIM14_CH1.
 * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)

/**
 * @brief Disable the remapping of TIM14_CH1.
 * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
#endif

#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)

/**
 * @brief Controls the use of the optional FSMC_NADV signal.
 * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
 * @retval None
 */
#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)

/**
 * @brief Controls the use of the optional FSMC_NADV signal.
 * @note  CONNECTED: The NADV signal is connected to the output (default).
 * @retval None
 */
#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM15_REMAP)

/**
 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
 * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)

/**
 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
 * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM16_REMAP)

/**
 * @brief Enable the remapping of TIM16_CH1.
 * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)

/**
 * @brief Disable the remapping of TIM16_CH1.
 * @note  DISABLE: No remap (TIM16_CH1 on PB8).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM17_REMAP)

/**
 * @brief Enable the remapping of TIM17_CH1.
 * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)

/**
 * @brief Disable the remapping of TIM17_CH1.
 * @note  DISABLE: No remap (TIM17_CH1 on PB9).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
#endif

#if defined(AFIO_MAPR2_CEC_REMAP)

/**
 * @brief Enable the remapping of CEC.
 * @note  ENABLE: Remap     (CEC on PB10).
 * @retval None
 */
#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)

/**
 * @brief Disable the remapping of CEC.
 * @note  DISABLE: No remap (CEC on PB8).
 * @retval None
 */
#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)

/**
 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
 * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)

/**
 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
 * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)

/**
 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
 * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)

/**
 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
 * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
#endif

#if defined(AFIO_MAPR2_TIM12_REMAP)

/**
 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
 * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
 * @note  This bit is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)

/**
 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
 * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
 * @note  This bit is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
#endif

#if defined(AFIO_MAPR2_MISC_REMAP)

/**
 * @brief Miscellaneous features remapping.
 *        This bit is set and cleared by software. It controls miscellaneous features.
 *        The DMA2 channel 5 interrupt position in the vector table.
 *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
 * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
 *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
 * @note  This bit is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)

/**
 * @brief Miscellaneous features remapping.
 *        This bit is set and cleared by software. It controls miscellaneous features.
 *        The DMA2 channel 5 interrupt position in the vector table.
 *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
 * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
 *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
 * @note  This bit is available only in high density value line devices.
 * @retval None
 */
#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
#endif

/**
 * @}
 */

/**
 * @}
 */

/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
 * @{
 */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : 3U)
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : 4U)
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#define GPIO_GET_INDEX(__GPIOx__) \
  (((__GPIOx__) == (GPIOA)) ? 0U : ((__GPIOx__) == (GPIOB)) ? 1U : ((__GPIOx__) == (GPIOC)) ? 2U : ((__GPIOx__) == (GPIOD)) ? 3U : ((__GPIOx__) == (GPIOE)) ? 4U : ((__GPIOx__) == (GPIOF)) ? 5U : 6U)
#endif

#define AFIO_REMAP_ENABLE(REMAP_PIN) \
  do {                               \
    uint32_t tmpreg = AFIO->MAPR;    \
    tmpreg |= AFIO_MAPR_SWJ_CFG;     \
    tmpreg |= REMAP_PIN;             \
    AFIO->MAPR = tmpreg;             \
  } while (0U)

#define AFIO_REMAP_DISABLE(REMAP_PIN) \
  do {                                \
    uint32_t tmpreg = AFIO->MAPR;     \
    tmpreg |= AFIO_MAPR_SWJ_CFG;      \
    tmpreg &= ~REMAP_PIN;             \
    AFIO->MAPR = tmpreg;              \
  } while (0U)

#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) \
  do {                                                \
    uint32_t tmpreg = AFIO->MAPR;                     \
    tmpreg &= ~REMAP_PIN_MASK;                        \
    tmpreg |= AFIO_MAPR_SWJ_CFG;                      \
    tmpreg |= REMAP_PIN;                              \
    AFIO->MAPR = tmpreg;                              \
  } while (0U)

#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) \
  do {                                    \
    uint32_t tmpreg = AFIO->MAPR;         \
    tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk;     \
    tmpreg |= DBGAFR_SWJCFG;              \
    AFIO->MAPR = tmpreg;                  \
  } while (0U)

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @addtogroup GPIOEx_Exported_Functions
 * @{
 */

/** @addtogroup GPIOEx_Exported_Functions_Group1
 * @{
 */
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
void HAL_GPIOEx_EnableEventout(void);
void HAL_GPIOEx_DisableEventout(void);

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_GPIO_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_i2c.h
 * @author  MCD Application Team
 * @brief   Header file of I2C HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_I2C_H
#define __STM32F1xx_HAL_I2C_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup I2C
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
 * @{
 */

/**
 * @brief  I2C Configuration Structure definition
 */
typedef struct {
  uint32_t ClockSpeed; /*!< Specifies the clock frequency.
                            This parameter must be set to a value lower than 400kHz */

  uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
                           This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */

  uint32_t OwnAddress1; /*!< Specifies the first device own address.
                             This parameter can be a 7-bit or 10-bit address. */

  uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
                                This parameter can be a value of @ref I2C_addressing_mode */

  uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
                                 This parameter can be a value of @ref I2C_dual_addressing_mode */

  uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
                             This parameter can be a 7-bit address. */

  uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
                                 This parameter can be a value of @ref I2C_general_call_addressing_mode */

  uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
                               This parameter can be a value of @ref I2C_nostretch_mode */

} I2C_InitTypeDef;

/**
 * @brief  HAL State structure definition
 * @note  HAL I2C State value coding follow below described bitmap :
 *          b7-b6  Error information
 *             00 : No Error
 *             01 : Abort (Abort user request on going)
 *             10 : Timeout
 *             11 : Error
 *          b5     IP initilisation status
 *             0  : Reset (IP not initialized)
 *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
 *          b4     (not used)
 *             x  : Should be set to 0
 *          b3
 *             0  : Ready or Busy (No Listen mode ongoing)
 *             1  : Listen (IP in Address Listen Mode)
 *          b2     Intrinsic process state
 *             0  : Ready
 *             1  : Busy (IP busy with some configuration or internal operations)
 *          b1     Rx state
 *             0  : Ready (no Rx operation ongoing)
 *             1  : Busy (Rx operation ongoing)
 *          b0     Tx state
 *             0  : Ready (no Tx operation ongoing)
 *             1  : Busy (Tx operation ongoing)
 */
typedef enum {
  HAL_I2C_STATE_RESET          = 0x00U, /*!< Peripheral is not yet Initialized         */
  HAL_I2C_STATE_READY          = 0x20U, /*!< Peripheral Initialized and ready for use  */
  HAL_I2C_STATE_BUSY           = 0x24U, /*!< An internal process is ongoing            */
  HAL_I2C_STATE_BUSY_TX        = 0x21U, /*!< Data Transmission process is ongoing      */
  HAL_I2C_STATE_BUSY_RX        = 0x22U, /*!< Data Reception process is ongoing         */
  HAL_I2C_STATE_LISTEN         = 0x28U, /*!< Address Listen Mode is ongoing            */
  HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
                                            process is ongoing                         */
  HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
                                            process is ongoing                         */
  HAL_I2C_STATE_ABORT   = 0x60U,        /*!< Abort user request ongoing                */
  HAL_I2C_STATE_TIMEOUT = 0xA0U,        /*!< Timeout state                             */
  HAL_I2C_STATE_ERROR   = 0xE0U         /*!< Error                                     */

} HAL_I2C_StateTypeDef;

/**
 * @brief  HAL Mode structure definition
 * @note  HAL I2C Mode value coding follow below described bitmap :
 *          b7     (not used)
 *             x  : Should be set to 0
 *          b6
 *             0  : None
 *             1  : Memory (HAL I2C communication is in Memory Mode)
 *          b5
 *             0  : None
 *             1  : Slave (HAL I2C communication is in Slave Mode)
 *          b4
 *             0  : None
 *             1  : Master (HAL I2C communication is in Master Mode)
 *          b3-b2-b1-b0  (not used)
 *             xxxx : Should be set to 0000
 */
typedef enum {
  HAL_I2C_MODE_NONE   = 0x00U, /*!< No I2C communication on going             */
  HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode       */
  HAL_I2C_MODE_SLAVE  = 0x20U, /*!< I2C communication is in Slave Mode        */
  HAL_I2C_MODE_MEM    = 0x40U  /*!< I2C communication is in Memory Mode       */

} HAL_I2C_ModeTypeDef;

/**
 * @brief  I2C handle Structure definition
 */
typedef struct {
  I2C_TypeDef *Instance; /*!< I2C registers base address               */

  I2C_InitTypeDef Init; /*!< I2C communication parameters             */

  uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer           */

  uint16_t XferSize; /*!< I2C transfer size                        */

  __IO uint16_t XferCount; /*!< I2C transfer counter                     */

  __IO uint32_t XferOptions; /*!< I2C transfer options                     */

  __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
                                    context for internal usage               */

  DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters             */

  DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters             */

  HAL_LockTypeDef Lock; /*!< I2C locking object                       */

  __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state                  */

  __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode                   */

  __IO uint32_t ErrorCode; /*!< I2C Error code                           */

  __IO uint32_t Devaddress; /*!< I2C Target device address                */

  __IO uint32_t Memaddress; /*!< I2C Target memory address                */

  __IO uint32_t MemaddSize; /*!< I2C Target memory address  size          */

  __IO uint32_t EventCount; /*!< I2C Event counter                        */

} I2C_HandleTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
 * @{
 */

/** @defgroup I2C_Error_Code I2C Error Code
 * @brief    I2C Error Code
 * @{
 */
#define HAL_I2C_ERROR_NONE    0x00000000U /*!< No error           */
#define HAL_I2C_ERROR_BERR    0x00000001U /*!< BERR error         */
#define HAL_I2C_ERROR_ARLO    0x00000002U /*!< ARLO error         */
#define HAL_I2C_ERROR_AF      0x00000004U /*!< AF error           */
#define HAL_I2C_ERROR_OVR     0x00000008U /*!< OVR error          */
#define HAL_I2C_ERROR_DMA     0x00000010U /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error      */
/**
 * @}
 */

/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
 * @{
 */
#define I2C_DUTYCYCLE_2    0x00000000U
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
 * @}
 */

/** @defgroup I2C_addressing_mode I2C addressing mode
 * @{
 */
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
// #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
/**
 * @}
 */

/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
 * @{
 */
#define I2C_DUALADDRESS_DISABLE 0x00000000U
#define I2C_DUALADDRESS_ENABLE  I2C_OAR2_ENDUAL
/**
 * @}
 */

/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
 * @{
 */
#define I2C_GENERALCALL_DISABLE 0x00000000U
#define I2C_GENERALCALL_ENABLE  I2C_CR1_ENGC
/**
 * @}
 */

/** @defgroup I2C_nostretch_mode I2C nostretch mode
 * @{
 */
#define I2C_NOSTRETCH_DISABLE 0x00000000U
#define I2C_NOSTRETCH_ENABLE  I2C_CR1_NOSTRETCH
/**
 * @}
 */

/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
 * @{
 */
#define I2C_MEMADD_SIZE_8BIT  0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
/**
 * @}
 */

/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
 * @{
 */
#define I2C_DIRECTION_RECEIVE  0x00000000U
#define I2C_DIRECTION_TRANSMIT 0x00000001U
/**
 * @}
 */

/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
 * @{
 */
#define I2C_FIRST_FRAME          0x00000001U
#define I2C_NEXT_FRAME           0x00000002U
#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
#define I2C_LAST_FRAME           0x00000008U
/**
 * @}
 */

/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
 * @{
 */
#define I2C_IT_BUF I2C_CR2_ITBUFEN
#define I2C_IT_EVT I2C_CR2_ITEVTEN
#define I2C_IT_ERR I2C_CR2_ITERREN
/**
 * @}
 */

/** @defgroup I2C_Flag_definition I2C Flag definition
 * @{
 */
#define I2C_FLAG_SMBALERT 0x00018000U
#define I2C_FLAG_TIMEOUT  0x00014000U
#define I2C_FLAG_PECERR   0x00011000U
#define I2C_FLAG_OVR      0x00010800U
#define I2C_FLAG_AF       0x00010400U
#define I2C_FLAG_ARLO     0x00010200U
#define I2C_FLAG_BERR     0x00010100U
#define I2C_FLAG_TXE      0x00010080U
#define I2C_FLAG_RXNE     0x00010040U
#define I2C_FLAG_STOPF    0x00010010U
// #define I2C_FLAG_ADD10      0x00010008U
#define I2C_FLAG_BTF        0x00010004U
#define I2C_FLAG_ADDR       0x00010002U
#define I2C_FLAG_SB         0x00010001U
#define I2C_FLAG_DUALF      0x00100080U
#define I2C_FLAG_SMBHOST    0x00100040U
#define I2C_FLAG_SMBDEFAULT 0x00100020U
#define I2C_FLAG_GENCALL    0x00100010U
#define I2C_FLAG_TRA        0x00100004U
#define I2C_FLAG_BUSY       0x00100002U
#define I2C_FLAG_MSL        0x00100001U
/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
 * @{
 */

/** @brief Reset I2C handle state
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @retval None
 */
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

/** @brief  Enable or disable the specified I2C interrupts.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 *         This parameter can be one of the following values:
 *            @arg I2C_IT_BUF: Buffer interrupt enable
 *            @arg I2C_IT_EVT: Event interrupt enable
 *            @arg I2C_IT_ERR: Error interrupt enable
 * @retval None
 */
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
 *          This parameter can be one of the following values:
 *            @arg I2C_IT_BUF: Buffer interrupt enable
 *            @arg I2C_IT_EVT: Event interrupt enable
 *            @arg I2C_IT_ERR: Error interrupt enable
 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
 */
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

/** @brief  Checks whether the specified I2C flag is set or not.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @param  __FLAG__: specifies the flag to check.
 *         This parameter can be one of the following values:
 *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
 *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
 *            @arg I2C_FLAG_PECERR: PEC error in reception flag
 *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
 *            @arg I2C_FLAG_AF: Acknowledge failure flag
 *            @arg I2C_FLAG_ARLO: Arbitration lost flag
 *            @arg I2C_FLAG_BERR: Bus error flag
 *            @arg I2C_FLAG_TXE: Data register empty flag
 *            @arg I2C_FLAG_RXNE: Data register not empty flag
 *            @arg I2C_FLAG_STOPF: Stop detection flag
 *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
 *            @arg I2C_FLAG_BTF: Byte transfer finished flag
 *            @arg I2C_FLAG_ADDR: Address sent flag
 *                                Address matched flag
 *            @arg I2C_FLAG_SB: Start bit flag
 *            @arg I2C_FLAG_DUALF: Dual flag
 *            @arg I2C_FLAG_SMBHOST: SMBus host header
 *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
 *            @arg I2C_FLAG_GENCALL: General call header flag
 *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
 *            @arg I2C_FLAG_BUSY: Bus busy flag
 *            @arg I2C_FLAG_MSL: Master/Slave flag
 * @retval The new state of __FLAG__ (TRUE or FALSE).
 */
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)                                                                                            \
  ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? ((((__HANDLE__)->Instance->SR1) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)) \
                                             : ((((__HANDLE__)->Instance->SR2) & ((__FLAG__)&I2C_FLAG_MASK)) == ((__FLAG__)&I2C_FLAG_MASK)))

/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @param  __FLAG__: specifies the flag to clear.
 *         This parameter can be any combination of the following values:
 *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
 *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
 *            @arg I2C_FLAG_PECERR: PEC error in reception flag
 *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
 *            @arg I2C_FLAG_AF: Acknowledge failure flag
 *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
 *            @arg I2C_FLAG_BERR: Bus error flag
 * @retval None
 */
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__)&I2C_FLAG_MASK))

/** @brief  Clears the I2C ADDR pending flag.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @retval None
 */
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)            \
  do {                                                  \
    __IO uint32_t tmpreg = 0x00U;                       \
    tmpreg               = (__HANDLE__)->Instance->SR1; \
    tmpreg               = (__HANDLE__)->Instance->SR2; \
    UNUSED(tmpreg);                                     \
  } while (0U)

/** @brief  Clears the I2C STOPF pending flag.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
 * @retval None
 */
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)            \
  do {                                                  \
    __IO uint32_t tmpreg = 0x00U;                       \
    tmpreg               = (__HANDLE__)->Instance->SR1; \
    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;          \
    UNUSED(tmpreg);                                     \
  } while (0U)

/** @brief  Enable the I2C peripheral.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
 * @retval None
 */
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)

/** @brief  Disable the I2C peripheral.
 * @param  __HANDLE__: specifies the I2C Handle.
 *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
 * @retval None
 */
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
 * @{
 */

/** @addtogroup I2C_Exported_Functions_Group1
 * @{
 */
/* Initialization/de-initialization functions  **********************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void              HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void              HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
 * @}
 */

/** @addtogroup I2C_Exported_Functions_Group2
 * @{
 */
/* I/O operation functions  *****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);

/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);

/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
 * @}
 */

/** @addtogroup I2C_Exported_Functions_Group3
 * @{
 */
/* Peripheral State, Mode and Errors functions  *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);

/**
 * @}
 */

/**
 * @}
 */
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
 * @{
 */
#define I2C_FLAG_MASK              0x0000FFFFU
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz                     */
#define I2C_MIN_PCLK_FREQ_FAST     4000000U /*!< 4 MHz                     */
/**
 * @}
 */

/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macros I2C Private Macros
 * @{
 */

#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)              (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__)-1U) / ((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
#define I2C_FREQRANGE(__PCLK__)                             ((__PCLK__) / 1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__)*300U) / 1000U) + 1U))
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)             ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U) ? 4U : I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) \
  (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2) ? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)                                                                                 \
  (((__SPEED__) <= 100000U)                                                           ? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) \
   : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U) ? 1U                                            \
                                                                                      : ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))

#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__)  ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))

#define I2C_10BIT_ADDRESS(__ADDRESS__)      ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
#define I2C_10BIT_HEADER_READ(__ADDRESS__)  ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))

#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
 * @{
 */
#define IS_I2C_DUTY_CYCLE(CYCLE)                 (((CYCLE) == I2C_DUTYCYCLE_2) || ((CYCLE) == I2C_DUTYCYCLE_16_9))
#define IS_I2C_ADDRESSING_MODE(ADDRESS)          (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS)             (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_GENERAL_CALL(CALL)                (((CALL) == I2C_GENERALCALL_DISABLE) || ((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH)               (((STRETCH) == I2C_NOSTRETCH_DISABLE) || ((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE)                 (((SIZE) == I2C_MEMADD_SIZE_8BIT) || ((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_I2C_CLOCK_SPEED(SPEED)                (((SPEED) > 0) && ((SPEED) <= 400000U))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1)            (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2)            (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || ((REQUEST) == I2C_NEXT_FRAME) || ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || ((REQUEST) == I2C_LAST_FRAME))
/**
 * @}
 */

/**
 * @}
 */

/* Private functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
 * @{
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_I2C_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_iwdg.h
 * @author  MCD Application Team
 * @brief   Header file of IWDG HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_IWDG_H
#define __STM32F1xx_HAL_IWDG_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup IWDG
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
 * @{
 */

/**
 * @brief  IWDG Init structure definition
 */
typedef struct {
  uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
                           This parameter can be a value of @ref IWDG_Prescaler */

  uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
                        This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */

} IWDG_InitTypeDef;

/**
 * @brief  IWDG Handle Structure definition
 */
typedef struct {
  IWDG_TypeDef *Instance; /*!< Register base address    */

  IWDG_InitTypeDef Init; /*!< IWDG required parameters */

} IWDG_HandleTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
 * @{
 */

/** @defgroup IWDG_Prescaler IWDG Prescaler
 * @{
 */
#define IWDG_PRESCALER_4   0x00000000U                   /*!< IWDG prescaler set to 4   */
#define IWDG_PRESCALER_8   IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
#define IWDG_PRESCALER_16  IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
#define IWDG_PRESCALER_32  (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
#define IWDG_PRESCALER_64  IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
 * @}
 */

/**
 * @}
 */

/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
 * @{
 */

/**
 * @brief  Enable the IWDG peripheral.
 * @param  __HANDLE__  IWDG handle
 * @retval None
 */
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

/**
 * @brief  Reload IWDG counter with value defined in the reload register
 *         (write access to IWDG_PR & IWDG_RLR registers disabled).
 * @param  __HANDLE__  IWDG handle
 * @retval None
 */
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
 * @{
 */

/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
 * @{
 */
/* Initialization/Start functions  ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
 * @}
 */

/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
 * @{
 */
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
 * @}
 */

/**
 * @}
 */

/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
 * @{
 */

/**
 * @brief  IWDG Key Register BitMask
 */
#define IWDG_KEY_RELOAD               0x0000AAAAU /*!< IWDG Reload Counter Enable   */
#define IWDG_KEY_ENABLE               0x0000CCCCU /*!< IWDG Peripheral Enable       */
#define IWDG_KEY_WRITE_ACCESS_ENABLE  0x00005555U /*!< IWDG KR Write Access Enable  */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */

/**
 * @}
 */

/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
 * @{
 */

/**
 * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
 * @param  __HANDLE__  IWDG handle
 * @retval None
 */
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

/**
 * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
 * @param  __HANDLE__  IWDG handle
 * @retval None
 */
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

/**
 * @brief  Check IWDG prescaler value.
 * @param  __PRESCALER__  IWDG prescaler value
 * @retval None
 */
#define IS_IWDG_PRESCALER(__PRESCALER__)                                                                                                                              \
  (((__PRESCALER__) == IWDG_PRESCALER_4) || ((__PRESCALER__) == IWDG_PRESCALER_8) || ((__PRESCALER__) == IWDG_PRESCALER_16) || ((__PRESCALER__) == IWDG_PRESCALER_32) \
   || ((__PRESCALER__) == IWDG_PRESCALER_64) || ((__PRESCALER__) == IWDG_PRESCALER_128) || ((__PRESCALER__) == IWDG_PRESCALER_256))

/**
 * @brief  Check IWDG reload value.
 * @param  __RELOAD__  IWDG reload value
 * @retval None
 */
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_IWDG_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_pwr.h
 * @author  MCD Application Team
 * @brief   Header file of PWR HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_PWR_H
#define __STM32F1xx_HAL_PWR_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup PWR
 * @{
 */

/* Exported types ------------------------------------------------------------*/

/** @defgroup PWR_Exported_Types PWR Exported Types
 * @{
 */

/**
 * @brief  PWR PVD configuration structure definition
 */
typedef struct {
  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
                          This parameter can be a value of @ref PWR_PVD_detection_level */

  uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
                      This parameter can be a value of @ref PWR_PVD_Mode */
} PWR_PVDTypeDef;

/**
 * @}
 */

/* Internal constants --------------------------------------------------------*/

/** @addtogroup PWR_Private_Constants
 * @{
 */

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup PWR_Exported_Constants PWR Exported Constants
 * @{
 */

/** @defgroup PWR_PVD_detection_level PWR PVD detection level
 * @{
 */
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9

/**
 * @}
 */

/** @defgroup PWR_PVD_Mode PWR PVD Mode
 * @{
 */
#define PWR_PVD_MODE_NORMAL               0x00000000U /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING            0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING           0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING    0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING         0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING        0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */

/**
 * @}
 */

/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
 * @{
 */

#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP

/**
 * @}
 */

/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
 * @{
 */
#define PWR_MAINREGULATOR_ON     0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

/**
 * @}
 */

/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
 * @{
 */
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

/**
 * @}
 */

/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
 * @{
 */
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

/**
 * @}
 */

/** @defgroup PWR_Flag PWR Flag
 * @{
 */
#define PWR_FLAG_WU   PWR_CSR_WUF
#define PWR_FLAG_SB   PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO

/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
 * @{
 */

/** @brief  Check PWR flag is set or not.
 * @param  __FLAG__: specifies the flag to check.
 *           This parameter can be one of the following values:
 *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
 *                  was received from the WKUP pin or from the RTC alarm
 *                  An additional wakeup event is detected if the WKUP pin is enabled
 *                  (by setting the EWUP bit) when the WKUP pin level is already high.
 *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
 *                  resumed from StandBy mode.
 *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
 *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
 *                  For this reason, this bit is equal to 0 after Standby or reset
 *                  until the PVDE bit is set.
 * @retval The new state of __FLAG__ (TRUE or FALSE).
 */
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))

/** @brief  Clear the PWR's pending flags.
 * @param  __FLAG__: specifies the flag to clear.
 *          This parameter can be one of the following values:
 *            @arg PWR_FLAG_WU: Wake Up flag
 *            @arg PWR_FLAG_SB: StandBy flag
 */
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))

/**
 * @brief Enable interrupt on PVD Exti Line 16.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)

/**
 * @brief Disable interrupt on PVD Exti Line 16.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)

/**
 * @brief Enable event on PVD Exti Line 16.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)

/**
 * @brief Disable event on PVD Exti Line 16.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)

/**
 * @brief  PVD EXTI line configuration: set falling edge trigger.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

/**
 * @brief Disable the PVD Extended Interrupt Falling Trigger.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

/**
 * @brief  PVD EXTI line configuration: set rising edge trigger.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

/**
 * @brief Disable the PVD Extended Interrupt Rising Trigger.
 * This parameter can be:
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

/**
 * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();              \
  __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();

/**
 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
 * This parameter can be:
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();              \
  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();

/**
 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
 * @retval EXTI PVD Line Status.
 */
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))

/**
 * @brief Clear the PVD EXTI flag.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))

/**
 * @brief Generate a Software interrupt on selected EXTI line.
 * @retval None.
 */
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
 * @{
 */
#define IS_PWR_PVD_LEVEL(LEVEL)                                                                                                                                                           \
  (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) \
   || ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

#define IS_PWR_PVD_MODE(MODE)                                                                                                                                       \
  (((MODE) == PWR_PVD_MODE_IT_RISING) || ((MODE) == PWR_PVD_MODE_IT_FALLING) || ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) \
   || ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_NORMAL))

#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))

#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/

/** @addtogroup PWR_Exported_Functions PWR Exported Functions
 * @{
 */

/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
 * @{
 */

/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);

/**
 * @}
 */

/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
 * @{
 */

/* Peripheral Control functions  ************************************************/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
/* #define HAL_PWR_ConfigPVD 12*/
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);

/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);

/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);

void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);

void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_PWR_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_rcc.h
 * @author  MCD Application Team
 * @brief   Header file of RCC HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_RCC_H
#define __STM32F1xx_HAL_RCC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup RCC
 * @{
 */

/* Exported types ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Types RCC Exported Types
 * @{
 */

/**
 * @brief  RCC PLL configuration structure definition
 */
typedef struct {
  uint32_t PLLState; /*!< PLLState: The new state of the PLL.
                         This parameter can be a value of @ref RCC_PLL_Config */

  uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
                          This parameter must be a value of @ref RCC_PLL_Clock_Source */

  uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
                       This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
} RCC_PLLInitTypeDef;

/**
 * @brief  RCC System, AHB and APB busses clock configuration structure definition
 */
typedef struct {
  uint32_t ClockType; /*!< The clock to be configured.
                           This parameter can be a value of @ref RCC_System_Clock_Type */

  uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
                              This parameter can be a value of @ref RCC_System_Clock_Source */

  uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
                               This parameter can be a value of @ref RCC_AHB_Clock_Source */

  uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
                                This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */

  uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
                                This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
} RCC_ClkInitTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
 * @{
 */

/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
 * @{
 */

#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U     /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSE      RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */

/**
 * @}
 */

/** @defgroup RCC_Oscillator_Type Oscillator Type
 * @{
 */
#define RCC_OSCILLATORTYPE_NONE 0x00000000U
#define RCC_OSCILLATORTYPE_HSE  0x00000001U
#define RCC_OSCILLATORTYPE_HSI  0x00000002U
#define RCC_OSCILLATORTYPE_LSE  0x00000004U
#define RCC_OSCILLATORTYPE_LSI  0x00000008U
/**
 * @}
 */

/** @defgroup RCC_HSE_Config HSE Config
 * @{
 */
#define RCC_HSE_OFF    0x00000000U                                /*!< HSE clock deactivation */
#define RCC_HSE_ON     RCC_CR_HSEON                               /*!< HSE clock activation */
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
/**
 * @}
 */

/** @defgroup RCC_LSE_Config LSE Config
 * @{
 */
#define RCC_LSE_OFF    0x00000000U                                    /*!< LSE clock deactivation */
#define RCC_LSE_ON     RCC_BDCR_LSEON                                 /*!< LSE clock activation */
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */

/**
 * @}
 */

/** @defgroup RCC_HSI_Config HSI Config
 * @{
 */
#define RCC_HSI_OFF 0x00000000U  /*!< HSI clock deactivation */
#define RCC_HSI_ON  RCC_CR_HSION /*!< HSI clock activation */

#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */

/**
 * @}
 */

/** @defgroup RCC_LSI_Config LSI Config
 * @{
 */
#define RCC_LSI_OFF 0x00000000U   /*!< LSI clock deactivation */
#define RCC_LSI_ON  RCC_CSR_LSION /*!< LSI clock activation */

/**
 * @}
 */

/** @defgroup RCC_PLL_Config PLL Config
 * @{
 */
#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
#define RCC_PLL_OFF  0x00000001U /*!< PLL deactivation */
#define RCC_PLL_ON   0x00000002U /*!< PLL activation */

/**
 * @}
 */

/** @defgroup RCC_System_Clock_Type System Clock Type
 * @{
 */
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK   0x00000002U /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1  0x00000004U /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2  0x00000008U /*!< PCLK2 to configure */

/**
 * @}
 */

/** @defgroup RCC_System_Clock_Source System Clock Source
 * @{
 */
#define RCC_SYSCLKSOURCE_HSI    RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
#define RCC_SYSCLKSOURCE_HSE    RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */

/**
 * @}
 */

/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
 * @{
 */
#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */

/**
 * @}
 */

/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
 * @{
 */
#define RCC_SYSCLK_DIV1   RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
#define RCC_SYSCLK_DIV2   RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
#define RCC_SYSCLK_DIV4   RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
#define RCC_SYSCLK_DIV8   RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
#define RCC_SYSCLK_DIV16  RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
#define RCC_SYSCLK_DIV64  RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */

/**
 * @}
 */

/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
 * @{
 */
#define RCC_HCLK_DIV1  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
#define RCC_HCLK_DIV2  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
#define RCC_HCLK_DIV4  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
#define RCC_HCLK_DIV8  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */

/**
 * @}
 */

/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
 * @{
 */
#define RCC_RTCCLKSOURCE_NO_CLK     0x00000000U         /*!< No clock */
#define RCC_RTCCLKSOURCE_LSE        RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI        RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
/**
 * @}
 */

/** @defgroup RCC_MCO_Index MCO Index
 * @{
 */
#define RCC_MCO1 0x00000000U
#define RCC_MCO  RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/

/**
 * @}
 */

/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
 * @{
 */
#define RCC_MCODIV_1 0x00000000U

/**
 * @}
 */

/** @defgroup RCC_Interrupt Interrupts
 * @{
 */
#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
#define RCC_IT_CSS    ((uint8_t)RCC_CIR_CSSF)    /*!< Clock Security System Interrupt flag */
/**
 * @}
 */

/** @defgroup RCC_Flag Flags
 *        Elements values convention: XXXYYYYYb
 *           - YYYYY  : Flag position in the register
 *           - X XX  : Register index
 *                 - 001: CR register
 *                 - 010: BDCR register
 *                 - 011: CSR register
 * @{
 */
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */

/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
#define RCC_FLAG_PINRST  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
#define RCC_FLAG_PORRST  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
#define RCC_FLAG_SFTRST  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */

/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */

/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Macros RCC Exported Macros
 * @{
 */

/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
 * @brief  Enable or disable the AHB1 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */
#define __HAL_RCC_DMA1_CLK_ENABLE()                    \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);           \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_SRAM_CLK_ENABLE()                    \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);           \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_FLITF_CLK_ENABLE()                    \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_CRC_CLK_ENABLE()                     \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);            \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);  \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_DMA1_CLK_DISABLE()  (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define __HAL_RCC_SRAM_CLK_DISABLE()  (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
#define __HAL_RCC_CRC_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))

/**
 * @}
 */

/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the AHB peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#define __HAL_RCC_DMA1_IS_CLK_ENABLED()   ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define __HAL_RCC_DMA1_IS_CLK_DISABLED()  ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define __HAL_RCC_SRAM_IS_CLK_ENABLED()   ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define __HAL_RCC_SRAM_IS_CLK_DISABLED()  ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define __HAL_RCC_FLITF_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
#define __HAL_RCC_CRC_IS_CLK_ENABLED()    ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define __HAL_RCC_CRC_IS_CLK_DISABLED()   ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)

/**
 * @}
 */

/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
 * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */
#define __HAL_RCC_TIM2_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM3_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_WWDG_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_USART2_CLK_ENABLE()                      \
  do {                                                     \
    __IO uint32_t tmpreg;                                  \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);           \
    /* Delay after an RCC peripheral clock enabling */     \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN); \
    UNUSED(tmpreg);                                        \
  } while (0U)

#define __HAL_RCC_I2C1_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_BKP_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_PWR_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

/**
 * @}
 */

/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the APB1 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define __HAL_RCC_WWDG_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define __HAL_RCC_BKP_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
#define __HAL_RCC_BKP_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
#define __HAL_RCC_PWR_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

/**
 * @}
 */

/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
 * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */
#define __HAL_RCC_AFIO_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOA_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOB_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOC_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOD_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_ADC1_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM1_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_SPI1_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_USART1_CLK_ENABLE()                      \
  do {                                                     \
    __IO uint32_t tmpreg;                                  \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);           \
    /* Delay after an RCC peripheral clock enabling */     \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
    UNUSED(tmpreg);                                        \
  } while (0U)

#define __HAL_RCC_AFIO_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
#define __HAL_RCC_ADC1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

/**
 * @}
 */

/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the APB2 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#define __HAL_RCC_AFIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
#define __HAL_RCC_AFIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

/**
 * @}
 */

/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
 * @brief  Force or release APB1 peripheral reset.
 * @{
 */
#define __HAL_RCC_APB1_FORCE_RESET()   (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define __HAL_RCC_TIM3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_WWDG_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define __HAL_RCC_I2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00)
#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

/**
 * @}
 */

/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
 * @brief  Force or release APB2 peripheral reset.
 * @{
 */
#define __HAL_RCC_APB2_FORCE_RESET()  (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_AFIO_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
#define __HAL_RCC_ADC1_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))

#define __HAL_RCC_TIM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_SPI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

#define __HAL_RCC_APB2_RELEASE_RESET()  (RCC->APB2RSTR = 0x00)
#define __HAL_RCC_AFIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
#define __HAL_RCC_ADC1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))

#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

/**
 * @}
 */

/** @defgroup RCC_HSI_Configuration HSI Configuration
 * @{
 */

/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
 * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
 * @note   HSI can not be stopped if it is used as system clock source. In this case,
 *         you have to select another source of the system clock then stop the HSI.
 * @note   After enabling the HSI, the application software should wait on HSIRDY
 *         flag to be set indicating that HSI clock is stable and can be used as
 *         system clock source.
 * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 *         clock cycles.
 */
#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *)RCC_CR_HSION_BB = ENABLE)
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)RCC_CR_HSION_BB = DISABLE)

/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
 * @note   The calibration is used to compensate for the variations in voltage
 *         and temperature that influence the frequency of the internal HSI RC.
 * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
 *         (default is RCC_HSICALIBRATION_DEFAULT).
 *         This parameter must be a number between 0 and 0x1F.
 */
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))

/**
 * @}
 */

/** @defgroup RCC_LSI_Configuration  LSI Configuration
 * @{
 */

/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
 * @note   After enabling the LSI, the application software should wait on
 *         LSIRDY flag to be set indicating that LSI clock is stable and can
 *         be used to clock the IWDG and/or the RTC.
 */
#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = ENABLE)

/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
 * @note   LSI can not be disabled if the IWDG is running.
 * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
 *         clock cycles.
 */
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)RCC_CSR_LSION_BB = DISABLE)

/**
 * @}
 */

/** @defgroup RCC_HSE_Configuration HSE Configuration
 * @{
 */

/**
 * @brief  Macro to configure the External High Speed oscillator (HSE).
 * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
 *         supported by this macro. User should request a transition to HSE Off
 *         first and then HSE On or HSE Bypass.
 * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
 *         software should wait on HSERDY flag to be set indicating that HSE clock
 *         is stable and can be used to clock the PLL and/or system clock.
 * @note   HSE state can not be changed if it is used directly or through the
 *         PLL as system clock. In this case, you have to select another source
 *         of the system clock then change the HSE state (ex. disable it).
 * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
 * @note   This function reset the CSSON bit, so if the clock security system(CSS)
 *         was previously enabled you have to enable it again after calling this
 *         function.
 * @param  __STATE__ specifies the new state of the HSE.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
 *                              6 HSE oscillator clock cycles.
 *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
 *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
 */
#define __HAL_RCC_HSE_CONFIG(__STATE__)         \
  do {                                          \
    if ((__STATE__) == RCC_HSE_ON) {            \
      SET_BIT(RCC->CR, RCC_CR_HSEON);           \
    } else if ((__STATE__) == RCC_HSE_OFF) {    \
      CLEAR_BIT(RCC->CR, RCC_CR_HSEON);         \
      CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);        \
    } else if ((__STATE__) == RCC_HSE_BYPASS) { \
      SET_BIT(RCC->CR, RCC_CR_HSEBYP);          \
      SET_BIT(RCC->CR, RCC_CR_HSEON);           \
    } else {                                    \
      CLEAR_BIT(RCC->CR, RCC_CR_HSEON);         \
      CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);        \
    }                                           \
  } while (0U)

/**
 * @}
 */

/** @defgroup RCC_LSE_Configuration LSE Configuration
 * @{
 */

/**
 * @brief  Macro to configure the External Low Speed oscillator (LSE).
 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
 * @note   As the LSE is in the Backup domain and write access is denied to
 *         this domain after reset, you have to enable write access using
 *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
 *         (to be done once after reset).
 * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
 *         software should wait on LSERDY flag to be set indicating that LSE clock
 *         is stable and can be used to clock the RTC.
 * @param  __STATE__ specifies the new state of the LSE.
 *         This parameter can be one of the following values:
 *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
 *                              6 LSE oscillator clock cycles.
 *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
 *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
 */
#define __HAL_RCC_LSE_CONFIG(__STATE__)         \
  do {                                          \
    if ((__STATE__) == RCC_LSE_ON) {            \
      SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);       \
    } else if ((__STATE__) == RCC_LSE_OFF) {    \
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);     \
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);    \
    } else if ((__STATE__) == RCC_LSE_BYPASS) { \
      SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);      \
      SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);       \
    } else {                                    \
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);     \
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);    \
    }                                           \
  } while (0U)

/**
 * @}
 */

/** @defgroup RCC_PLL_Configuration PLL Configuration
 * @{
 */

/** @brief Macro to enable the main PLL.
 * @note   After enabling the main PLL, the application software should wait on
 *         PLLRDY flag to be set indicating that PLL clock is stable and can
 *         be used as system clock source.
 * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
 */
#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = ENABLE)

/** @brief Macro to disable the main PLL.
 * @note   The main PLL can not be disabled if it is used as system clock source
 */
#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLON_BB = DISABLE)

/** @brief Macro to configure the main PLL clock source and multiplication factors.
  * @note   This function must be used only when the main PLL is disabled.
  *
  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
  *          This parameter can be one of the following values:
  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
  @if STM32F105xC
  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
  @elseif STM32F107xC
  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
  @else
  *             @arg @ref RCC_PLL_MUL2   PLLVCO = PLL clock entry x 2
  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
  *             @arg @ref RCC_PLL_MUL10  PLLVCO = PLL clock entry x 10
  *             @arg @ref RCC_PLL_MUL11  PLLVCO = PLL clock entry x 11
  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
  *             @arg @ref RCC_PLL_MUL13  PLLVCO = PLL clock entry x 13
  *             @arg @ref RCC_PLL_MUL14  PLLVCO = PLL clock entry x 14
  *             @arg @ref RCC_PLL_MUL15  PLLVCO = PLL clock entry x 15
  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
  @endif
  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
  *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
  *
  */
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL), ((__RCC_PLLSOURCE__) | (__PLLMUL__)))

/** @brief  Get oscillator clock selected as PLL input clock
 * @retval The clock source used for PLL entry. The returned value can be one
 *         of the following:
 *             @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
 *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
 */
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

/**
 * @}
 */

/** @defgroup RCC_Get_Clock_source Get Clock source
 * @{
 */

/**
 * @brief  Macro to configure the system clock source.
 * @param  __SYSCLKSOURCE__ specifies the system clock source.
 *          This parameter can be one of the following values:
 *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
 *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
 *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
 */
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

/** @brief  Macro to get the clock source used as system clock.
 * @retval The clock source used as system clock. The returned value can be one
 *         of the following:
 *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
 *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
 *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
 */
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))

/**
 * @}
 */

/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
 * @{
 */

#if defined(RCC_CFGR_MCO_3)
/** @brief  Macro to configure the MCO clock.
 * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
 *         This parameter can be one of the following values:
 *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System clock (SYSCLK) selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_HSI          HSI selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected by 2 selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected (for Ethernet) as MCO clock
 * @param  __MCODIV__ specifies the MCO clock prescaler.
 *         This parameter can be one of the following values:
 *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
 */
#else
/** @brief  Macro to configure the MCO clock.
 * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
 *         This parameter can be one of the following values:
 *            @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System clock (SYSCLK) selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
 *            @arg @ref RCC_MCO1SOURCE_PLLCLK  PLL clock divided by 2 selected as MCO clock
 * @param  __MCODIV__ specifies the MCO clock prescaler.
 *         This parameter can be one of the following values:
 *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
 */
#endif

#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))

/**
 * @}
 */

/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
 * @{
 */

/** @brief Macro to configure the RTC clock (RTCCLK).
 * @note   As the RTC clock configuration bits are in the Backup domain and write
 *         access is denied to this domain after reset, you have to enable write
 *         access using the Power Backup Access macro before to configure
 *         the RTC clock source (to be done once after reset).
 * @note   Once the RTC clock is configured it can't be changed unless the
 *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
 *         a Power On Reset (POR).
 *
 * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
 *          This parameter can be one of the following values:
 *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
 *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
 *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
 *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
 * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
 *         work in STOP and STANDBY modes, and can be used as wakeup source.
 *         However, when the HSE clock is used as RTC clock source, the RTC
 *         cannot be used in STOP and STANDBY modes.
 * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
 *         RTC clock source).
 */
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

/** @brief Macro to get the RTC clock source.
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
 *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
 *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
 *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
 */
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

/** @brief Macro to enable the the RTC clock.
 * @note   These macros must be used only after the RTC clock source was selected.
 */
#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = ENABLE)

/** @brief Macro to disable the the RTC clock.
 * @note  These macros must be used only after the RTC clock source was selected.
 */
#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)RCC_BDCR_RTCEN_BB = DISABLE)

/** @brief  Macro to force the Backup domain reset.
 * @note   This function resets the RTC peripheral (including the backup registers)
 *         and the RTC clock source selection in RCC_BDCR register.
 */
#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = ENABLE)

/** @brief  Macros to release the Backup domain reset.
 */
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)RCC_BDCR_BDRST_BB = DISABLE)

/**
 * @}
 */

/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
 * @brief macros to manage the specified RCC Flags and interrupts.
 * @{
 */

/** @brief Enable RCC interrupt.
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  @if STM32F105xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @elsif STM32F107xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @endif
  */
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

/** @brief Disable RCC interrupt.
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
  @if STM32F105xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @elsif STM32F107xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @endif
  */
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))

/** @brief Clear the RCC's interrupt pending bits.
  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
  *          This parameter can be any combination of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
  @if STM32F105xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @elsif STM32F107xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @endif
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  */
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

/** @brief Check the RCC's interrupt has occurred or not.
  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
  @if STM32F105xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @elsif STM32F107xx
  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
  @endif
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
  */
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

/** @brief Set RMVF bit to clear the reset flags.
 *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
 *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
 */
#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)

/** @brief  Check RCC flag is set or not.
  * @param  __FLAG__ specifies the flag to check.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
  @if STM32F105xx
  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
  @elsif STM32F107xx
  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
  @endif
  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
  * @retval The new state of __FLAG__ (TRUE or FALSE).
  */
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & (1U << ((__FLAG__)&RCC_FLAG_MASK)))

/**
 * @}
 */

/**
 * @}
 */

/* Include RCC HAL Extension module */
#include "stm32f1xx_hal_rcc_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
 * @{
 */

/** @addtogroup RCC_Exported_Functions_Group1
 * @{
 */

/* Initialization and de-initialization functions  ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

/**
 * @}
 */

/** @addtogroup RCC_Exported_Functions_Group2
 * @{
 */

/* Peripheral Control functions  ************************************************/
void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void     HAL_RCC_EnableCSS(void);
void     HAL_RCC_DisableCSS(void);
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
uint32_t HAL_RCC_GetPCLK1Freq(void);
uint32_t HAL_RCC_GetPCLK2Freq(void);
void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);

/* CSS NMI IRQ handler */
void HAL_RCC_NMI_IRQHandler(void);

/* User Callbacks in non blocking mode (IT mode) */
void HAL_RCC_CSSCallback(void);

/**
 * @}
 */

/**
 * @}
 */

/** @addtogroup RCC_Private_Constants
 * @{
 */

/** @defgroup RCC_Timeout RCC Timeout
 * @{
 */

/* Disable Backup domain write protection state change timeout */
#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
/* LSE state change timeout */
#define RCC_LSE_TIMEOUT_VALUE     LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s    */
#define HSE_TIMEOUT_VALUE         HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE         2U /* 2 ms (minimum Tick + 1) */
#define LSI_TIMEOUT_VALUE         2U /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE         2U /* 2 ms (minimum Tick + 1) */

/**
 * @}
 */

/** @defgroup RCC_Register_Offset Register offsets
 * @{
 */
#define RCC_OFFSET      (RCC_BASE - PERIPH_BASE)
#define RCC_CR_OFFSET   0x00U
#define RCC_CFGR_OFFSET 0x04U
#define RCC_CIR_OFFSET  0x08U
#define RCC_BDCR_OFFSET 0x20U
#define RCC_CSR_OFFSET  0x24U

/**
 * @}
 */

/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
 * @brief RCC registers bit address in the alias region
 * @{
 */
#define RCC_CR_OFFSET_BB   (RCC_OFFSET + RCC_CR_OFFSET)
#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
#define RCC_CIR_OFFSET_BB  (RCC_OFFSET + RCC_CIR_OFFSET)
#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
#define RCC_CSR_OFFSET_BB  (RCC_OFFSET + RCC_CSR_OFFSET)

/* --- CR Register ---*/
/* Alias word address of HSION bit */
#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
#define RCC_CR_HSION_BB      ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
/* Alias word address of HSEON bit */
#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
#define RCC_CR_HSEON_BB      ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
/* Alias word address of CSSON bit */
#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
#define RCC_CR_CSSON_BB      ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
/* Alias word address of PLLON bit */
#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
#define RCC_CR_PLLON_BB      ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))

/* --- CSR Register ---*/
/* Alias word address of LSION bit */
#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
#define RCC_CSR_LSION_BB     ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))

/* Alias word address of RMVF bit */
#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
#define RCC_CSR_RMVF_BB     ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))

/* --- BDCR Registers ---*/
/* Alias word address of LSEON bit */
#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
#define RCC_BDCR_LSEON_BB    ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))

/* Alias word address of LSEON bit */
#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
#define RCC_BDCR_LSEBYP_BB    ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))

/* Alias word address of RTCEN bit */
#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
#define RCC_BDCR_RTCEN_BB    ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))

/* Alias word address of BDRST bit */
#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
#define RCC_BDCR_BDRST_BB    ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

/**
 * @}
 */

/* CR register byte 2 (Bits[23:16]) base address */
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))

/* CIR register byte 1 (Bits[15:8]) base address */
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))

/* CIR register byte 2 (Bits[23:16]) base address */
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))

/* Defines used for Flags */
#define CR_REG_INDEX   ((uint8_t)1)
#define BDCR_REG_INDEX ((uint8_t)2)
#define CSR_REG_INDEX  ((uint8_t)3)

#define RCC_FLAG_MASK ((uint8_t)0x1F)

/**
 * @}
 */

/** @addtogroup RCC_Private_Macros
 * @{
 */
/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
 * @{
 */
#define __HAL_RCC_SYSCFG_CLK_DISABLE   __HAL_RCC_AFIO_CLK_DISABLE
#define __HAL_RCC_SYSCFG_CLK_ENABLE    __HAL_RCC_AFIO_CLK_ENABLE
#define __HAL_RCC_SYSCFG_FORCE_RESET   __HAL_RCC_AFIO_FORCE_RESET
#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
/**
 * @}
 */

#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || ((__SOURCE__) == RCC_PLLSOURCE_HSE))
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)                                                                                                                                                      \
  (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \
   || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || (((__OSCILLATOR__)&RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#define IS_RCC_HSE(__HSE__)                 (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || ((__HSE__) == RCC_HSE_BYPASS))
#define IS_RCC_LSE(__LSE__)                 (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__)                 (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define IS_RCC_LSI(__LSI__)                 (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_PLL(__PLL__)                 (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))

#define IS_RCC_CLOCKTYPE(CLK)                                                                                                                                           \
  ((((CLK)&RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || (((CLK)&RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || (((CLK)&RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \
   || (((CLK)&RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
#define IS_RCC_SYSCLKSOURCE(__SOURCE__)        (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
#define IS_RCC_HCLK(__HCLK__)                                                                                                                                                   \
  (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV16) \
   || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
#define IS_RCC_PCLK(__PCLK__)  (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || ((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_MCO(__MCO__)    ((__MCO__) == RCC_MCO)
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) \
  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_RCC_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_rcc_ex.h
 * @author  MCD Application Team
 * @brief   Header file of RCC HAL Extension module.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_RCC_EX_H
#define __STM32F1xx_HAL_RCC_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup RCCEx
 * @{
 */

/** @addtogroup RCCEx_Private_Constants
 * @{
 */

#if defined(STM32F105xC) || defined(STM32F107xC)

/* Alias word address of PLLI2SON bit */
#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
/* Alias word address of PLL2ON bit */
#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))

#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
#define PLL2_TIMEOUT_VALUE   100U /* 100 ms */

#endif /* STM32F105xC || STM32F107xC */

#define CR_REG_INDEX ((uint8_t)1)

/**
 * @}
 */

/** @addtogroup RCCEx_Private_Macros
 * @{
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
#define IS_RCC_HSE_PREDIV(__DIV__)                                                                                                                                                                    \
  (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || ((__DIV__) == RCC_HSE_PREDIV_DIV5)         \
   || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10)     \
   || ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || ((__DIV__) == RCC_HSE_PREDIV_DIV15) \
   || ((__DIV__) == RCC_HSE_PREDIV_DIV16))

#else
#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */

#if defined(STM32F105xC) || defined(STM32F107xC)
#define IS_RCC_PLL_MUL(__MUL__)                                                                                                                                                           \
  (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) \
   || ((__MUL__) == RCC_PLL_MUL6_5))

#define IS_RCC_MCO1SOURCE(__SOURCE__)                                                                                                                                                   \
  (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK)                   \
   || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
   || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))

#else
#define IS_RCC_PLL_MUL(__MUL__)                                                                                                                                                                  \
  (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7)        \
   || ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) \
   || ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || ((__MUL__) == RCC_PLL_MUL16))

#define IS_RCC_MCO1SOURCE(__SOURCE__)                                                                                                                                 \
  (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
   || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))

#endif /* STM32F105xC || STM32F107xC*/

#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))

#if defined(STM32F105xC) || defined(STM32F107xC)
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))

#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))

#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))

#define IS_RCC_PLLI2S_MUL(__MUL__)                                                                                                                                           \
  (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || ((__MUL__) == RCC_PLLI2S_MUL12) \
   || ((__MUL__) == RCC_PLLI2S_MUL13) || ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || ((__MUL__) == RCC_PLLI2S_MUL20))

#define IS_RCC_HSE_PREDIV2(__DIV__)                                                                                                                                                                    \
  (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || ((__DIV__) == RCC_HSE_PREDIV2_DIV5)     \
   || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \
   || ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14)                                     \
   || ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))

#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || ((__PLL__) == RCC_PLL2_ON))

#define IS_RCC_PLL2_MUL(__MUL__)                                                                                                                                                                    \
  (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) \
   || ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || ((__MUL__) == RCC_PLL2_MUL20))

#define IS_RCC_PERIPHCLOCK(__SELECTION__)                                                                                                                                                   \
  ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \
   || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))

#elif defined(STM32F103xE) || defined(STM32F103xG)

#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)

#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)

#define IS_RCC_PERIPHCLOCK(__SELECTION__)                                                                                                                                                   \
  ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \
   || (((__SELECTION__)&RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))

#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB)

#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
  ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || (((__SELECTION__)&RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))

#else

#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__)&RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || (((__SELECTION__)&RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))

#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)

#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))

#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */

/**
 * @}
 */

/* Exported types ------------------------------------------------------------*/

/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
 * @{
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/**
 * @brief  RCC PLL2 configuration structure definition
 */
typedef struct {
  uint32_t PLL2State; /*!< The new state of the PLL2.
                          This parameter can be a value of @ref RCCEx_PLL2_Config */

  uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
                      This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/

#if defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t HSEPrediv2Value; /*!<  The Prediv2 factor value.
                                 This parameter can be a value of @ref RCCEx_Prediv2_Factor */

#endif /* STM32F105xC || STM32F107xC */
} RCC_PLL2InitTypeDef;

#endif /* STM32F105xC || STM32F107xC */

/**
 * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
 */
typedef struct {
  uint32_t OscillatorType; /*!< The oscillators to be configured.
                                 This parameter can be a value of @ref RCC_Oscillator_Type */

#if defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t Prediv1Source; /*!<  The Prediv1 source value.
                                 This parameter can be a value of @ref RCCEx_Prediv1_Source */
#endif                    /* STM32F105xC || STM32F107xC */

  uint32_t HSEState; /*!< The new state of the HSE.
                          This parameter can be a value of @ref RCC_HSE_Config */

  uint32_t HSEPredivValue; /*!<  The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
                                 This parameter can be a value of @ref RCCEx_Prediv1_Factor */

  uint32_t LSEState; /*!<  The new state of the LSE.
                           This parameter can be a value of @ref RCC_LSE_Config */

  uint32_t HSIState; /*!< The new state of the HSI.
                          This parameter can be a value of @ref RCC_HSI_Config */

  uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */

  uint32_t LSIState; /*!<  The new state of the LSI.
                           This parameter can be a value of @ref RCC_LSI_Config */

  RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */

#if defined(STM32F105xC) || defined(STM32F107xC)
  RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
#endif                      /* STM32F105xC || STM32F107xC */
} RCC_OscInitTypeDef;

#if defined(STM32F105xC) || defined(STM32F107xC)
/**
 * @brief  RCC PLLI2S configuration structure definition
 */
typedef struct {
  uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
                      This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/

#if defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t HSEPrediv2Value; /*!<  The Prediv2 factor value.
                                 This parameter can be a value of @ref RCCEx_Prediv2_Factor */

#endif /* STM32F105xC || STM32F107xC */
} RCC_PLLI2SInitTypeDef;
#endif /* STM32F105xC || STM32F107xC */

/**
 * @brief  RCC extended clocks structure definition
 */
typedef struct {
  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                  This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */

  uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
                               This parameter can be a value of @ref RCC_RTC_Clock_Source */

  uint32_t AdcClockSelection; /*!< ADC clock source
                               This parameter can be a value of @ref RCCEx_ADC_Prescaler */

#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t I2s2ClockSelection; /*!< I2S2 clock source
                               This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */

  uint32_t I2s3ClockSelection; /*!< I2S3 clock source
                               This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */

#if defined(STM32F105xC) || defined(STM32F107xC)
  RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
                                     This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */

#endif /* STM32F105xC || STM32F107xC */
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t UsbClockSelection; /*!< USB clock source
                               This parameter can be a value of @ref RCCEx_USB_Prescaler */

#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
} RCC_PeriphCLKInitTypeDef;

/**
 * @}
 */

/* Exported constants --------------------------------------------------------*/

/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
 * @{
 */

/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
 * @{
 */
#define RCC_PERIPHCLK_RTC 0x00000001U
#define RCC_PERIPHCLK_ADC 0x00000002U
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PERIPHCLK_I2S2 0x00000004U
#define RCC_PERIPHCLK_I2S3 0x00000008U
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PERIPHCLK_USB 0x00000010U
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

/**
 * @}
 */

/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
 * @{
 */
#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8

/**
 * @}
 */

#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
 * @{
 */
#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
#if defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
 * @{
 */
#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
#if defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)

/** @defgroup RCCEx_USB_Prescaler USB Prescaler
 * @{
 */
#define RCC_USBCLKSOURCE_PLL        RCC_CFGR_USBPRE
#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U

/**
 * @}
 */

#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_USB_Prescaler USB Prescaler
 * @{
 */
#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U

/**
 * @}
 */

/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
 * @{
 */

#define RCC_PLLI2S_MUL8  RCC_CFGR2_PLL3MUL8  /*!< PLLI2S input clock * 8 */
#define RCC_PLLI2S_MUL9  RCC_CFGR2_PLL3MUL9  /*!< PLLI2S input clock * 9 */
#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */

/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
 * @{
 */

#define RCC_PREDIV1_SOURCE_HSE  RCC_CFGR2_PREDIV1SRC_HSE
#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2

/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC */

/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
 * @{
 */

#define RCC_HSE_PREDIV_DIV1 0x00000000U

#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
#define RCC_HSE_PREDIV_DIV2  RCC_CFGR2_PREDIV1_DIV2
#define RCC_HSE_PREDIV_DIV3  RCC_CFGR2_PREDIV1_DIV3
#define RCC_HSE_PREDIV_DIV4  RCC_CFGR2_PREDIV1_DIV4
#define RCC_HSE_PREDIV_DIV5  RCC_CFGR2_PREDIV1_DIV5
#define RCC_HSE_PREDIV_DIV6  RCC_CFGR2_PREDIV1_DIV6
#define RCC_HSE_PREDIV_DIV7  RCC_CFGR2_PREDIV1_DIV7
#define RCC_HSE_PREDIV_DIV8  RCC_CFGR2_PREDIV1_DIV8
#define RCC_HSE_PREDIV_DIV9  RCC_CFGR2_PREDIV1_DIV9
#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
#else
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
 * @{
 */

#define RCC_HSE_PREDIV2_DIV1  RCC_CFGR2_PREDIV2_DIV1  /*!< PREDIV2 input clock not divided */
#define RCC_HSE_PREDIV2_DIV2  RCC_CFGR2_PREDIV2_DIV2  /*!< PREDIV2 input clock divided by 2 */
#define RCC_HSE_PREDIV2_DIV3  RCC_CFGR2_PREDIV2_DIV3  /*!< PREDIV2 input clock divided by 3 */
#define RCC_HSE_PREDIV2_DIV4  RCC_CFGR2_PREDIV2_DIV4  /*!< PREDIV2 input clock divided by 4 */
#define RCC_HSE_PREDIV2_DIV5  RCC_CFGR2_PREDIV2_DIV5  /*!< PREDIV2 input clock divided by 5 */
#define RCC_HSE_PREDIV2_DIV6  RCC_CFGR2_PREDIV2_DIV6  /*!< PREDIV2 input clock divided by 6 */
#define RCC_HSE_PREDIV2_DIV7  RCC_CFGR2_PREDIV2_DIV7  /*!< PREDIV2 input clock divided by 7 */
#define RCC_HSE_PREDIV2_DIV8  RCC_CFGR2_PREDIV2_DIV8  /*!< PREDIV2 input clock divided by 8 */
#define RCC_HSE_PREDIV2_DIV9  RCC_CFGR2_PREDIV2_DIV9  /*!< PREDIV2 input clock divided by 9 */
#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */

/**
 * @}
 */

/** @defgroup RCCEx_PLL2_Config PLL Config
 * @{
 */
#define RCC_PLL2_NONE 0x00000000U
#define RCC_PLL2_OFF  0x00000001U
#define RCC_PLL2_ON   0x00000002U

/**
 * @}
 */

/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
 * @{
 */

#define RCC_PLL2_MUL8  RCC_CFGR2_PLL2MUL8  /*!< PLL2 input clock * 8 */
#define RCC_PLL2_MUL9  RCC_CFGR2_PLL2MUL9  /*!< PLL2 input clock * 9 */
#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */

/**
 * @}
 */

#endif /* STM32F105xC || STM32F107xC */

/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
 * @{
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
#else
#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
#endif /* STM32F105xC || STM32F107xC */
#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
#if defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
#else
#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
 * @{
 */
#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
#define RCC_MCO1SOURCE_SYSCLK  ((uint32_t)RCC_CFGR_MCO_SYSCLK)
#define RCC_MCO1SOURCE_HSI     ((uint32_t)RCC_CFGR_MCO_HSI)
#define RCC_MCO1SOURCE_HSE     ((uint32_t)RCC_CFGR_MCO_HSE)
#define RCC_MCO1SOURCE_PLLCLK  ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
#if defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_MCO1SOURCE_PLL2CLK      ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
#define RCC_MCO1SOURCE_EXT_HSE      ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
#define RCC_MCO1SOURCE_PLL3CLK      ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
#endif /* STM32F105xC || STM32F107xC*/
/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Interrupt RCCEx Interrupt
 * @{
 */
#define RCC_IT_PLL2RDY   ((uint8_t)RCC_CIR_PLL2RDYF)
#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
/**
 * @}
 */

/** @defgroup RCCEx_Flag RCCEx Flag
 *        Elements values convention: 0XXYYYYYb
 *           - YYYYY  : Flag position in the register
 *           - XX  : Register index
 *                 - 01: CR register
 * @{
 */
/* Flags in the CR register */
#define RCC_FLAG_PLL2RDY   ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC*/

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
 * @{
 */

/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
 * @brief  Enable or disable the AHB1 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE)
#define __HAL_RCC_DMA2_CLK_ENABLE()                    \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);           \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
#define __HAL_RCC_FSMC_CLK_ENABLE()                    \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);           \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */

#if defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_SDIO_CLK_ENABLE()                    \
  do {                                                 \
    __IO uint32_t tmpreg;                              \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);           \
    /* Delay after an RCC peripheral clock enabling */ \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN); \
    UNUSED(tmpreg);                                    \
  } while (0U)

#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
#endif /* STM32F103xE || STM32F103xG */

#if defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()               \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
#endif /* STM32F105xC || STM32F107xC*/

#if defined(STM32F107xC)
#define __HAL_RCC_ETHMAC_CLK_ENABLE()                    \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_ETHMACTX_CLK_ENABLE()                    \
  do {                                                     \
    __IO uint32_t tmpreg;                                  \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);           \
    /* Delay after an RCC peripheral clock enabling */     \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN); \
    UNUSED(tmpreg);                                        \
  } while (0U)

#define __HAL_RCC_ETHMACRX_CLK_ENABLE()                    \
  do {                                                     \
    __IO uint32_t tmpreg;                                  \
    SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);           \
    /* Delay after an RCC peripheral clock enabling */     \
    tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN); \
    UNUSED(tmpreg);                                        \
  } while (0U)

#define __HAL_RCC_ETHMAC_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))

/**
 * @brief  Enable ETHERNET clock.
 */
#define __HAL_RCC_ETH_CLK_ENABLE()   \
  do {                               \
    __HAL_RCC_ETHMAC_CLK_ENABLE();   \
    __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
    __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
  } while (0U)
/**
 * @brief  Disable ETHERNET clock.
 */
#define __HAL_RCC_ETH_CLK_DISABLE()   \
  do {                                \
    __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
    __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
    __HAL_RCC_ETHMAC_CLK_DISABLE();   \
  } while (0U)

#endif /* STM32F107xC*/

/**
 * @}
 */

/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the AHB1 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xE)
#define __HAL_RCC_DMA2_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
#if defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_SDIO_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
#endif /* STM32F103xE || STM32F103xG */
#if defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
#endif /* STM32F105xC || STM32F107xC*/
#if defined(STM32F107xC)
#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()    ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()   ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()  ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
#endif /* STM32F107xC*/

/**
 * @}
 */

/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
 * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_CAN1_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \
    || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM4_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_SPI2_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_USART3_CLK_ENABLE()                      \
  do {                                                     \
    __IO uint32_t tmpreg;                                  \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);           \
    /* Delay after an RCC peripheral clock enabling */     \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN); \
    UNUSED(tmpreg);                                        \
  } while (0U)

#define __HAL_RCC_I2C2_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_USB_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM5_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM6_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM7_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_SPI3_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_UART4_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_UART5_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_DAC_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_TIM5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_TIM6_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define __HAL_RCC_SPI3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#define __HAL_RCC_DAC_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM6_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM7_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_DAC_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_CEC_CLK_ENABLE()                      \
  do {                                                  \
    __IO uint32_t tmpreg;                               \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);           \
    /* Delay after an RCC peripheral clock enabling */  \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN); \
    UNUSED(tmpreg);                                     \
  } while (0U)

#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#define __HAL_RCC_DAC_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define __HAL_RCC_CEC_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#endif /* STM32F100xB || STM32F100xE */

#ifdef STM32F100xE
#define __HAL_RCC_TIM5_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM12_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM13_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM14_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_SPI3_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_UART4_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_UART5_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#define __HAL_RCC_SPI3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#endif /* STM32F100xE */

#if defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_CAN2_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM12_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM13_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM14_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
#endif /* STM32F101xG || STM32F103xG*/

/**
 * @}
 */

/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the APB1 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_CAN1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \
    || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_USB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define __HAL_RCC_TIM5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define __HAL_RCC_TIM6_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define __HAL_RCC_TIM7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define __HAL_RCC_SPI3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define __HAL_RCC_DAC_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM6_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define __HAL_RCC_TIM7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
#define __HAL_RCC_DAC_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
#define __HAL_RCC_DAC_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
#define __HAL_RCC_CEC_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
#define __HAL_RCC_CEC_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
#endif /* STM32F100xB || STM32F100xE */
#ifdef STM32F100xE
#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
#define __HAL_RCC_TIM5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#define __HAL_RCC_SPI3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
#define __HAL_RCC_CAN2_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
#endif /* STM32F100xE */
#if defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#endif /* STM32F101xG || STM32F103xG*/

/**
 * @}
 */

/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
 * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_ADC2_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */

#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM15_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM16_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM17_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
#endif /* STM32F100xB || STM32F100xE */

#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \
    || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_GPIOE_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_GPIOF_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOG_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/

#if defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_TIM8_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_ADC3_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
#endif /* STM32F103xE || STM32F103xG */

#if defined(STM32F100xE)
#define __HAL_RCC_GPIOF_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOG_CLK_ENABLE()                     \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
#endif /* STM32F100xE */

#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM9_CLK_ENABLE()                      \
  do {                                                   \
    __IO uint32_t tmpreg;                                \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);           \
    /* Delay after an RCC peripheral clock enabling */   \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN); \
    UNUSED(tmpreg);                                      \
  } while (0U)

#define __HAL_RCC_TIM10_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM11_CLK_ENABLE()                      \
  do {                                                    \
    __IO uint32_t tmpreg;                                 \
    SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);           \
    /* Delay after an RCC peripheral clock enabling */    \
    tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN); \
    UNUSED(tmpreg);                                       \
  } while (0U)

#define __HAL_RCC_TIM9_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
#endif /* STM32F101xG || STM32F103xG */

/**
 * @}
 */

/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
 * @brief  Get the enable or disable status of the APB2 peripheral clock.
 * @note   After reset, the peripheral clock (used for registers read/write access)
 *         is disabled and the application software has to enable this clock before
 *         using it.
 * @{
 */

#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_ADC2_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM15_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
#define __HAL_RCC_TIM16_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
#define __HAL_RCC_TIM17_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
#endif /* STM32F100xB || STM32F100xE */
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \
    || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
#if defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_TIM8_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
#define __HAL_RCC_ADC3_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
#endif /* STM32F103xE || STM32F103xG */
#if defined(STM32F100xE)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
#endif /* STM32F100xE */
#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
#define __HAL_RCC_TIM9_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
#endif /* STM32F101xG || STM32F103xG */

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
 * @brief  Force or release AHB peripheral reset.
 * @{
 */
#define __HAL_RCC_AHB_FORCE_RESET()        (RCC->AHBRSTR = 0xFFFFFFFFU)
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
#if defined(STM32F107xC)
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
#endif /* STM32F107xC */

#define __HAL_RCC_AHB_RELEASE_RESET()        (RCC->AHBRSTR = 0x00)
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
#if defined(STM32F107xC)
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
#endif /* STM32F107xC */

/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC */

/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
 * @brief  Force or release APB1 peripheral reset.
 * @{
 */

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))

#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) \
    || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define __HAL_RCC_SPI2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define __HAL_RCC_I2C2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_USB_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_TIM5_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_TIM6_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_SPI3_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
#define __HAL_RCC_DAC_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))

#define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_TIM6_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
#define __HAL_RCC_DAC_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_DAC_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define __HAL_RCC_CEC_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))

#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
#define __HAL_RCC_DAC_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#define __HAL_RCC_CEC_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#endif /* STM32F100xB || STM32F100xE */

#if defined(STM32F100xE)
#define __HAL_RCC_TIM5_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define __HAL_RCC_SPI3_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))

#define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
#endif /* STM32F100xE */

#if defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))

#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))

#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
#endif /* STM32F101xG || STM32F103xG */

/**
 * @}
 */

/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
 * @brief  Force or release APB2 peripheral reset.
 * @{
 */

#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))

#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */

#if defined(STM32F100xB) || defined(STM32F100xE)
#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))

#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
#endif /* STM32F100xB || STM32F100xE */

#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) \
    || defined(STM32F105xC) || defined(STM32F107xC)
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))

#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */

#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))

#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/

#if defined(STM32F103xE) || defined(STM32F103xG)
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))

#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
#endif /* STM32F103xE || STM32F103xG */

#if defined(STM32F100xE)
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))

#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
#endif /* STM32F100xE */

#if defined(STM32F101xG) || defined(STM32F103xG)
#define __HAL_RCC_TIM9_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))

#define __HAL_RCC_TIM9_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
#endif /* STM32F101xG || STM32F103xG*/

/**
 * @}
 */

/** @defgroup RCCEx_HSE_Configuration HSE Configuration
 * @{
 */

#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
/**
 * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
 * @note   Predivision factor can not be changed if PLL is used as system clock
 *         In this case, you have to select another source of the system clock, disable the PLL and
 *         then change the HSE predivision factor.
 * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
 *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
 */
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
#else
/**
 * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
 * @note   Predivision factor can not be changed if PLL is used as system clock
 *         In this case, you have to select another source of the system clock, disable the PLL and
 *         then change the HSE predivision factor.
 * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
 *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
 */
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))

#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
/**
 * @brief  Macro to get prediv1 factor for PLL.
 */
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)

#else
/**
 * @brief  Macro to get prediv1 factor for PLL.
 */
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)

#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
 * @{
 */

/** @brief Macros to enable the main PLLI2S.
 * @note   After enabling the main PLLI2S, the application software should wait on
 *         PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
 *         be used as system clock source.
 * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
 */
#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = ENABLE)

/** @brief Macros to disable the main PLLI2S.
 * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
 */
#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *)RCC_CR_PLLI2SON_BB = DISABLE)

/** @brief macros to configure the main PLLI2S multiplication factor.
 * @note   This function must be used only when the main PLLI2S is disabled.
 *
 * @param  __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
 *          This parameter can be one of the following values:
 *             @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
 *             @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
 *             @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
 *             @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
 *             @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
 *             @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
 *             @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
 *             @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
 *             @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
 *
 */
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL, (__PLLI2SMUL__))

/**
 * @}
 */

#endif /* STM32F105xC || STM32F107xC */

/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
 * @brief  Macros to configure clock source of different peripherals.
 * @{
 */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
/** @brief  Macro to configure the USB clock.
 * @param  __USBCLKSOURCE__ specifies the USB clock source.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
 */
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))

/** @brief  Macro to get the USB clock (USBCLK).
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
 */
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))

#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */

#if defined(STM32F105xC) || defined(STM32F107xC)

/** @brief  Macro to configure the USB OTSclock.
 * @param  __USBCLKSOURCE__ specifies the USB clock source.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
 */
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))

/** @brief  Macro to get the USB clock (USBCLK).
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
 *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
 */
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))

#endif /* STM32F105xC || STM32F107xC */

/** @brief  Macro to configure the ADCx clock (x=1 to 3 depending on devices).
 * @param  __ADCCLKSOURCE__ specifies the ADC clock source.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
 */
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))

/** @brief  Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
 *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
 */
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)

/** @addtogroup RCCEx_HSE_Configuration
 * @{
 */

/**
 * @brief  Macro to configure the PLL2 & PLLI2S Predivision factor.
 * @note   Predivision factor can not be changed if PLL2 is used indirectly as system clock
 *         In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
 *         then change the PREDIV2 factor.
 * @param  __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
 *         This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
 */
#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))

/**
 * @brief  Macro to get prediv2 factor for PLL2 & PLL3.
 */
#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)

/**
 * @}
 */

/** @addtogroup RCCEx_PLLI2S_Configuration
 * @{
 */

/** @brief Macros to enable the main PLL2.
 * @note   After enabling the main PLL2, the application software should wait on
 *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
 *         be used as system clock source.
 * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
 */
#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = ENABLE)

/** @brief Macros to disable the main PLL2.
 * @note   The main PLL2 can not be disabled if it is used indirectly as system clock source
 * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
 */
#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *)RCC_CR_PLL2ON_BB = DISABLE)

/** @brief macros to configure the main PLL2 multiplication factor.
 * @note   This function must be used only when the main PLL2 is disabled.
 *
 * @param  __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
 *          This parameter can be one of the following values:
 *             @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
 *             @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
 *             @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
 *             @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
 *             @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
 *             @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
 *             @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
 *             @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
 *             @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
 *
 */
#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL, (__PLL2MUL__))

/**
 * @}
 */

/** @defgroup RCCEx_I2S_Configuration I2S Configuration
 * @brief  Macros to configure clock source of I2S peripherals.
 * @{
 */

/** @brief  Macro to configure the I2S2 clock.
 * @param  __I2S2CLKSOURCE__ specifies the I2S2 clock source.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
 *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
 */
#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))

/** @brief  Macro to get the I2S2 clock (I2S2CLK).
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
 *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
 */
#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))

/** @brief  Macro to configure the I2S3 clock.
 * @param  __I2S2CLKSOURCE__ specifies the I2S3 clock source.
 *          This parameter can be one of the following values:
 *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
 *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
 */
#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))

/** @brief  Macro to get the I2S3 clock (I2S3CLK).
 * @retval The clock source can be one of the following values:
 *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
 *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
 */
#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))

/**
 * @}
 */

#endif /* STM32F105xC || STM32F107xC */
/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCCEx_Exported_Functions
 * @{
 */

/** @addtogroup RCCEx_Exported_Functions_Group1
 * @{
 */

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @addtogroup RCCEx_Exported_Functions_Group2
 * @{
 */
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);

/**
 * @}
 */

/** @addtogroup RCCEx_Exported_Functions_Group3
 * @{
 */
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);

/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_RCC_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_tim.h
 * @author  MCD Application Team
 * @brief   Header file of TIM HAL module.
 ******************************************************************************
 * @attention
 *
 * 
© Copyright (c) 2016 STMicroelectronics.
 * All rights reserved.

 *
 * This software component is licensed by ST under BSD 3-Clause license,
 * the "License"; You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                        opensource.org/licenses/BSD-3-Clause
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_TIM_H
#define STM32F1xx_HAL_TIM_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#ifndef USE_HAL_TIM_REGISTER_CALLBACKS
#define USE_HAL_TIM_REGISTER_CALLBACKS 0
#endif
/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup TIM
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
 * @{
 */

/**
 * @brief  TIM Time base Configuration Structure definition
 */
typedef struct {
  uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
                           This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

  uint32_t CounterMode; /*!< Specifies the counter mode.
                             This parameter can be a value of @ref TIM_Counter_Mode */

  uint32_t Period; /*!< Specifies the period value to be loaded into the active
                        Auto-Reload Register at the next update event.
                        This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */

  uint32_t ClockDivision; /*!< Specifies the clock division.
                               This parameter can be a value of @ref TIM_ClockDivision */

  uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
                                   reaches zero, an update event is generated and counting restarts
                                   from the RCR value (N).
                                   This means in PWM mode that (N+1) corresponds to:
                                       - the number of PWM periods in edge-aligned mode
                                       - the number of half PWM period in center-aligned mode
                                    GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
                                    Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */

  uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
                                  This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;

/**
 * @brief  TIM Output Compare Configuration Structure definition
 */
typedef struct {
  uint32_t OCMode; /*!< Specifies the TIM mode.
                        This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

  uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
                       This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

  uint32_t OCPolarity; /*!< Specifies the output polarity.
                            This parameter can be a value of @ref TIM_Output_Compare_Polarity */

  uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
                             This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
                             @note This parameter is valid only for timer instances supporting break feature. */

  uint32_t OCFastMode; /*!< Specifies the Fast mode state.
                            This parameter can be a value of @ref TIM_Output_Fast_State
                            @note This parameter is valid only in PWM1 and PWM2 mode. */

  uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
                             This parameter can be a value of @ref TIM_Output_Compare_Idle_State
                             @note This parameter is valid only for timer instances supporting break feature. */

  uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
                              This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
                              @note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;

/**
 * @brief  TIM One Pulse Mode Configuration Structure definition
 */
typedef struct {
  uint32_t OCMode; /*!< Specifies the TIM mode.
                        This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

  uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
                       This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

  uint32_t OCPolarity; /*!< Specifies the output polarity.
                            This parameter can be a value of @ref TIM_Output_Compare_Polarity */

  uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
                             This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
                             @note This parameter is valid only for timer instances supporting break feature. */

  uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
                             This parameter can be a value of @ref TIM_Output_Compare_Idle_State
                             @note This parameter is valid only for timer instances supporting break feature. */

  uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
                              This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
                              @note This parameter is valid only for timer instances supporting break feature. */

  uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
                            This parameter can be a value of @ref TIM_Input_Capture_Polarity */

  uint32_t ICSelection; /*!< Specifies the input.
                            This parameter can be a value of @ref TIM_Input_Capture_Selection */

  uint32_t ICFilter; /*!< Specifies the input capture filter.
                         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;

/**
 * @brief  TIM Input Capture Configuration Structure definition
 */
typedef struct {
  uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
                            This parameter can be a value of @ref TIM_Input_Capture_Polarity */

  uint32_t ICSelection; /*!< Specifies the input.
                             This parameter can be a value of @ref TIM_Input_Capture_Selection */

  uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
                             This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

  uint32_t ICFilter; /*!< Specifies the input capture filter.
                          This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_IC_InitTypeDef;

/**
 * @brief  TIM Encoder Configuration Structure definition
 */
typedef struct {
  uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
                             This parameter can be a value of @ref TIM_Encoder_Mode */

  uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
                             This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

  uint32_t IC1Selection; /*!< Specifies the input.
                              This parameter can be a value of @ref TIM_Input_Capture_Selection */

  uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

  uint32_t IC1Filter; /*!< Specifies the input capture filter.
                           This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

  uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
                             This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

  uint32_t IC2Selection; /*!< Specifies the input.
                             This parameter can be a value of @ref TIM_Input_Capture_Selection */

  uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

  uint32_t IC2Filter; /*!< Specifies the input capture filter.
                           This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;

/**
 * @brief  Clock Configuration Handle Structure definition
 */
typedef struct {
  uint32_t ClockSource;    /*!< TIM clock sources
                                This parameter can be a value of @ref TIM_Clock_Source */
  uint32_t ClockPolarity;  /*!< TIM clock polarity
                                This parameter can be a value of @ref TIM_Clock_Polarity */
  uint32_t ClockPrescaler; /*!< TIM clock prescaler
                                This parameter can be a value of @ref TIM_Clock_Prescaler */
  uint32_t ClockFilter;    /*!< TIM clock filter
                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClockConfigTypeDef;

/**
 * @brief  TIM Clear Input Configuration Handle Structure definition
 */
typedef struct {
  uint32_t ClearInputState;     /*!< TIM clear Input state
                                     This parameter can be ENABLE or DISABLE */
  uint32_t ClearInputSource;    /*!< TIM clear Input sources
                                     This parameter can be a value of @ref TIM_ClearInput_Source */
  uint32_t ClearInputPolarity;  /*!< TIM Clear Input polarity
                                     This parameter can be a value of @ref TIM_ClearInput_Polarity */
  uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
                                     This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;

/**
 * @brief  TIM Master configuration Structure definition
 */
typedef struct {
  uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
                                     This parameter can be a value of @ref TIM_Master_Mode_Selection */
  uint32_t MasterSlaveMode;     /*!< Master/slave mode selection
                                     This parameter can be a value of @ref TIM_Master_Slave_Mode
                                     @note When the Master/slave mode is enabled, the effect of
                                     an event on the trigger input (TRGI) is delayed to allow a
                                     perfect synchronization between the current timer and its
                                     slaves (through TRGO). It is not mandatory in case of timer
                                     synchronization mode. */
} TIM_MasterConfigTypeDef;

/**
 * @brief  TIM Slave configuration Structure definition
 */
typedef struct {
  uint32_t SlaveMode;        /*!< Slave mode selection
                                  This parameter can be a value of @ref TIM_Slave_Mode */
  uint32_t InputTrigger;     /*!< Input Trigger source
                                  This parameter can be a value of @ref TIM_Trigger_Selection */
  uint32_t TriggerPolarity;  /*!< Input Trigger polarity
                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
  uint32_t TriggerPrescaler; /*!< Input trigger prescaler
                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
  uint32_t TriggerFilter;    /*!< Input trigger filter
                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */

} TIM_SlaveConfigTypeDef;

/**
 * @brief  TIM Break input(s) and Dead time configuration Structure definition
 * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
 *        filter and polarity.
 */
typedef struct {
  uint32_t OffStateRunMode;  /*!< TIM off state in run mode
                                  This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
  uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
                                  This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
  uint32_t LockLevel;        /*!< TIM Lock level
                                  This parameter can be a value of @ref TIM_Lock_level */
  uint32_t DeadTime;         /*!< TIM dead Time
                                  This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
  uint32_t BreakState;       /*!< TIM Break State
                                  This parameter can be a value of @ref TIM_Break_Input_enable_disable */
  uint32_t BreakPolarity;    /*!< TIM Break input polarity
                                  This parameter can be a value of @ref TIM_Break_Polarity */
  uint32_t BreakFilter;      /*!< Specifies the break input filter.
                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  uint32_t AutomaticOutput;  /*!< TIM Automatic Output Enable state
                                  This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;

/**
 * @brief  HAL State structures definition
 */
typedef enum {
  HAL_TIM_STATE_RESET   = 0x00U, /*!< Peripheral not yet initialized or disabled  */
  HAL_TIM_STATE_READY   = 0x01U, /*!< Peripheral Initialized and ready for use    */
  HAL_TIM_STATE_BUSY    = 0x02U, /*!< An internal process is ongoing              */
  HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state                               */
  HAL_TIM_STATE_ERROR   = 0x04U  /*!< Reception process is ongoing                */
} HAL_TIM_StateTypeDef;

/**
 * @brief  TIM Channel States definition
 */
typedef enum {
  HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state                         */
  HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use                         */
  HAL_TIM_CHANNEL_STATE_BUSY  = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;

/**
 * @brief  DMA Burst States definition
 */
typedef enum {
  HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
  HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
  HAL_DMA_BURST_STATE_BUSY  = 0x02U, /*!< Ongoing DMA Burst       */
} HAL_TIM_DMABurstStateTypeDef;

/**
 * @brief  HAL Active channel structures definition
 */
typedef enum {
  HAL_TIM_ACTIVE_CHANNEL_1       = 0x01U, /*!< The active channel is 1     */
  HAL_TIM_ACTIVE_CHANNEL_2       = 0x02U, /*!< The active channel is 2     */
  HAL_TIM_ACTIVE_CHANNEL_3       = 0x04U, /*!< The active channel is 3     */
  HAL_TIM_ACTIVE_CHANNEL_4       = 0x08U, /*!< The active channel is 4     */
  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U  /*!< All active channels cleared */
} HAL_TIM_ActiveChannel;

/**
 * @brief  TIM Time Base Handle Structure definition
 */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
typedef struct __TIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
  TIM_TypeDef *         Instance;                     /*!< Register base address                             */
  TIM_Base_InitTypeDef  Init;                         /*!< TIM Time Base required parameters                 */
  HAL_TIM_ActiveChannel Channel;                      /*!< Active channel                                    */
  DMA_HandleTypeDef *   hdma[7];                      /*!< DMA Handlers array
                                                           This array is accessed by a @ref DMA_Handle_index */
  HAL_LockTypeDef                   Lock;             /*!< Locking object                                    */
  __IO HAL_TIM_StateTypeDef         State;            /*!< TIM operation state                               */
  __IO HAL_TIM_ChannelStateTypeDef  ChannelState[4];  /*!< TIM channel operation state                       */
  __IO HAL_TIM_ChannelStateTypeDef  ChannelNState[4]; /*!< TIM complementary channel operation state         */
  __IO HAL_TIM_DMABurstStateTypeDef DMABurstState;    /*!< DMA burst operation state                         */

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  void (*Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
  void (*Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
  void (*IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
  void (*IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
  void (*OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
  void (*OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
  void (*PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
  void (*PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
  void (*OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
  void (*OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
  void (*Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
  void (*Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
  void (*HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
  void (*HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
  void (*PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
  void (*PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
  void (*TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
  void (*TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
  void (*IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
  void (*IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
  void (*OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
  void (*PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
  void (*PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
  void (*ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
  void (*CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
  void (*CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
  void (*BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
#endif                                                                         /* USE_HAL_TIM_REGISTER_CALLBACKS */
} TIM_HandleTypeDef;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
 * @brief  HAL TIM Callback ID enumeration definition
 */
typedef enum {
  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID                              */
  ,
  HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID                            */
  ,
  HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID                                */
  ,
  HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID                              */
  ,
  HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID                                */
  ,
  HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID                              */
  ,
  HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID                               */
  ,
  HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID                             */
  ,
  HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID                         */
  ,
  HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID                       */
  ,
  HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID                           */
  ,
  HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID                         */
  ,
  HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID                     */
  ,
  HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID                     */
  ,
  HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID                             */
  ,
  HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID               */
  ,
  HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID                                    */
  ,
  HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID                      */

  ,
  HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID                              */
  ,
  HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID                */
  ,
  HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID               */
  ,
  HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID           */
  ,
  HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID           */
  ,
  HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID                                      */
  ,
  HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID                                */
  ,
  HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID                  */
  ,
  HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID                                      */
} HAL_TIM_CallbackIDTypeDef;

/**
 * @brief  HAL TIM Callback pointer definition
 */
typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */

#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @}
 */
/* End of exported types -----------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_Constants TIM Exported Constants
 * @{
 */

/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
 * @{
 */
#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
#define TIM_CLEARINPUTSOURCE_ETR  0x00000001U /*!< OCREF_CLR is connected to ETRF input */
/**
 * @}
 */

/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
 * @{
 */
#define TIM_DMABASE_CR1   0x00000000U
#define TIM_DMABASE_CR2   0x00000001U
#define TIM_DMABASE_SMCR  0x00000002U
#define TIM_DMABASE_DIER  0x00000003U
#define TIM_DMABASE_SR    0x00000004U
#define TIM_DMABASE_EGR   0x00000005U
#define TIM_DMABASE_CCMR1 0x00000006U
#define TIM_DMABASE_CCMR2 0x00000007U
#define TIM_DMABASE_CCER  0x00000008U
#define TIM_DMABASE_CNT   0x00000009U
#define TIM_DMABASE_PSC   0x0000000AU
#define TIM_DMABASE_ARR   0x0000000BU
#define TIM_DMABASE_RCR   0x0000000CU
#define TIM_DMABASE_CCR1  0x0000000DU
#define TIM_DMABASE_CCR2  0x0000000EU
#define TIM_DMABASE_CCR3  0x0000000FU
#define TIM_DMABASE_CCR4  0x00000010U
#define TIM_DMABASE_BDTR  0x00000011U
#define TIM_DMABASE_DCR   0x00000012U
#define TIM_DMABASE_DMAR  0x00000013U
/**
 * @}
 */

/** @defgroup TIM_Event_Source TIM Event Source
 * @{
 */
#define TIM_EVENTSOURCE_UPDATE  TIM_EGR_UG   /*!< Reinitialize the counter and generates an update of the registers */
#define TIM_EVENTSOURCE_CC1     TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
#define TIM_EVENTSOURCE_CC2     TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
#define TIM_EVENTSOURCE_CC3     TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
#define TIM_EVENTSOURCE_CC4     TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
#define TIM_EVENTSOURCE_COM     TIM_EGR_COMG /*!< A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG   /*!< A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK   TIM_EGR_BG   /*!< A break event is generated */
/**
 * @}
 */

/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
 * @{
 */
#define TIM_INPUTCHANNELPOLARITY_RISING   0x00000000U                      /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING  TIM_CCER_CC1P                    /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
 * @}
 */

/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
 * @{
 */
#define TIM_ETRPOLARITY_INVERTED    TIM_SMCR_ETP /*!< Polarity for ETR source */
#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U  /*!< Polarity for ETR source */
/**
 * @}
 */

/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
 * @{
 */
#define TIM_ETRPRESCALER_DIV1 0x00000000U     /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS   /*!< ETR input source is divided by 8 */
/**
 * @}
 */

/** @defgroup TIM_Counter_Mode TIM Counter Mode
 * @{
 */
#define TIM_COUNTERMODE_UP             0x00000000U   /*!< Counter used as up-counter   */
#define TIM_COUNTERMODE_DOWN           TIM_CR1_DIR   /*!< Counter used as down-counter */
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1        */
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2        */
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS   /*!< Center-aligned mode 3        */
/**
 * @}
 */

/** @defgroup TIM_ClockDivision TIM Clock Division
 * @{
 */
#define TIM_CLOCKDIVISION_DIV1 0x00000000U   /*!< Clock division: tDTS=tCK_INT   */
#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_State TIM Output Compare State
 * @{
 */
#define TIM_OUTPUTSTATE_DISABLE 0x00000000U   /*!< Capture/Compare 1 output disabled */
#define TIM_OUTPUTSTATE_ENABLE  TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
/**
 * @}
 */

/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
 * @{
 */
#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U  /*!< TIMx_ARR register is not buffered */
#define TIM_AUTORELOAD_PRELOAD_ENABLE  TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */

/**
 * @}
 */

/** @defgroup TIM_Output_Fast_State TIM Output Fast State
 * @{
 */
#define TIM_OCFAST_DISABLE 0x00000000U     /*!< Output Compare fast disable */
#define TIM_OCFAST_ENABLE  TIM_CCMR1_OC1FE /*!< Output Compare fast enable  */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
 * @{
 */
#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U    /*!< OCxN is disabled  */
#define TIM_OUTPUTNSTATE_ENABLE  TIM_CCER_CC1NE /*!< OCxN is enabled   */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
 * @{
 */
#define TIM_OCPOLARITY_HIGH 0x00000000U   /*!< Capture/Compare output polarity  */
#define TIM_OCPOLARITY_LOW  TIM_CCER_CC1P /*!< Capture/Compare output polarity  */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
 * @{
 */
#define TIM_OCNPOLARITY_HIGH 0x00000000U    /*!< Capture/Compare complementary output polarity */
#define TIM_OCNPOLARITY_LOW  TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
 * @{
 */
#define TIM_OCIDLESTATE_SET   TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
#define TIM_OCIDLESTATE_RESET 0x00000000U  /*!< Output Idle state: OCx=0 when MOE=0 */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
 * @{
 */
#define TIM_OCNIDLESTATE_SET   TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
#define TIM_OCNIDLESTATE_RESET 0x00000000U   /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
/**
 * @}
 */

/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
 * @{
 */
#define TIM_ICPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING   /*!< Capture triggered by rising edge on timer input                  */
#define TIM_ICPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING  /*!< Capture triggered by falling edge on timer input                 */
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
/**
 * @}
 */

/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
 * @{
 */
#define TIM_ENCODERINPUTPOLARITY_RISING  TIM_INPUTCHANNELPOLARITY_RISING  /*!< Encoder input with rising edge polarity  */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
 * @}
 */

/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
 * @{
 */
#define TIM_ICSELECTION_DIRECTTI                                 \
  TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be \
                        connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI                                                       \
  TIM_CCMR1_CC1S_1                         /*!< TIM Input 1, 2, 3 or 4 is selected to be \
                                                connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
 * @}
 */

/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
 * @{
 */
#define TIM_ICPSC_DIV1 0x00000000U        /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events                                */
#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events                                */
#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC   /*!< Capture performed once every 8 events                                */
/**
 * @}
 */

/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
 * @{
 */
#define TIM_OPMODE_SINGLE     TIM_CR1_OPM /*!< Counter stops counting at the next update event */
#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event          */
/**
 * @}
 */

/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
 * @{
 */
#define TIM_ENCODERMODE_TI1  TIM_SMCR_SMS_0                    /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
#define TIM_ENCODERMODE_TI2  TIM_SMCR_SMS_1                    /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
/**
 * @}
 */

/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
 * @{
 */
#define TIM_IT_UPDATE  TIM_DIER_UIE   /*!< Update interrupt            */
#define TIM_IT_CC1     TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
#define TIM_IT_CC2     TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
#define TIM_IT_CC3     TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
#define TIM_IT_CC4     TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
#define TIM_IT_COM     TIM_DIER_COMIE /*!< Commutation interrupt       */
#define TIM_IT_TRIGGER TIM_DIER_TIE   /*!< Trigger interrupt           */
#define TIM_IT_BREAK   TIM_DIER_BIE   /*!< Break interrupt             */
/**
 * @}
 */

/** @defgroup TIM_Commutation_Source  TIM Commutation Source
 * @{
 */
#define TIM_COMMUTATION_TRGI     TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
#define TIM_COMMUTATION_SOFTWARE 0x00000000U  /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
/**
 * @}
 */

/** @defgroup TIM_DMA_sources TIM DMA Sources
 * @{
 */
#define TIM_DMA_UPDATE  TIM_DIER_UDE   /*!< DMA request is triggered by the update event */
#define TIM_DMA_CC1     TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
#define TIM_DMA_CC2     TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
#define TIM_DMA_CC3     TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
#define TIM_DMA_CC4     TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
#define TIM_DMA_COM     TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
#define TIM_DMA_TRIGGER TIM_DIER_TDE   /*!< DMA request is triggered by the trigger event */
/**
 * @}
 */

/** @defgroup TIM_Flag_definition TIM Flag Definition
 * @{
 */
#define TIM_FLAG_UPDATE  TIM_SR_UIF   /*!< Update interrupt flag         */
#define TIM_FLAG_CC1     TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
#define TIM_FLAG_CC2     TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
#define TIM_FLAG_CC3     TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
#define TIM_FLAG_CC4     TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
#define TIM_FLAG_COM     TIM_SR_COMIF /*!< Commutation interrupt flag    */
#define TIM_FLAG_TRIGGER TIM_SR_TIF   /*!< Trigger interrupt flag        */
#define TIM_FLAG_BREAK   TIM_SR_BIF   /*!< Break interrupt flag          */
#define TIM_FLAG_CC1OF   TIM_SR_CC1OF /*!< Capture 1 overcapture flag    */
#define TIM_FLAG_CC2OF   TIM_SR_CC2OF /*!< Capture 2 overcapture flag    */
#define TIM_FLAG_CC3OF   TIM_SR_CC3OF /*!< Capture 3 overcapture flag    */
#define TIM_FLAG_CC4OF   TIM_SR_CC4OF /*!< Capture 4 overcapture flag    */
/**
 * @}
 */

/** @defgroup TIM_Channel TIM Channel
 * @{
 */
#define TIM_CHANNEL_1   0x00000000U /*!< Capture/compare channel 1 identifier      */
#define TIM_CHANNEL_2   0x00000004U /*!< Capture/compare channel 2 identifier      */
#define TIM_CHANNEL_3   0x00000008U /*!< Capture/compare channel 3 identifier      */
#define TIM_CHANNEL_4   0x0000000CU /*!< Capture/compare channel 4 identifier      */
#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier  */
/**
 * @}
 */

/** @defgroup TIM_Clock_Source TIM Clock Source
 * @{
 */
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2                          */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source                                 */
#define TIM_CLOCKSOURCE_ITR0     TIM_TS_ITR0     /*!< External clock source mode 1 (ITR0)                   */
#define TIM_CLOCKSOURCE_ITR1     TIM_TS_ITR1     /*!< External clock source mode 1 (ITR1)                   */
#define TIM_CLOCKSOURCE_ITR2     TIM_TS_ITR2     /*!< External clock source mode 1 (ITR2)                   */
#define TIM_CLOCKSOURCE_ITR3     TIM_TS_ITR3     /*!< External clock source mode 1 (ITR3)                   */
#define TIM_CLOCKSOURCE_TI1ED    TIM_TS_TI1F_ED  /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
#define TIM_CLOCKSOURCE_TI1      TIM_TS_TI1FP1   /*!< External clock source mode 1 (TTI1FP1)                */
#define TIM_CLOCKSOURCE_TI2      TIM_TS_TI2FP2   /*!< External clock source mode 1 (TTI2FP2)                */
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF     /*!< External clock source mode 1 (ETRF)                   */
/**
 * @}
 */

/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
 * @{
 */
#define TIM_CLOCKPOLARITY_INVERTED    TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_RISING      TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING     TIM_INPUTCHANNELPOLARITY_FALLING  /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE    TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
 * @}
 */

/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
 * @{
 */
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used                                                     */
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
 * @}
 */

/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
 * @{
 */
#define TIM_CLEARINPUTPOLARITY_INVERTED    TIM_ETRPOLARITY_INVERTED    /*!< Polarity for ETRx pin */
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
 * @}
 */

/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
 * @{
 */
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used                                                   */
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
 * @}
 */

/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
 * @{
 */
#define TIM_OSSR_ENABLE  TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
#define TIM_OSSR_DISABLE 0x00000000U   /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
 * @}
 */

/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
 * @{
 */
#define TIM_OSSI_ENABLE  TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
#define TIM_OSSI_DISABLE 0x00000000U   /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
 * @}
 */
/** @defgroup TIM_Lock_level  TIM Lock level
 * @{
 */
#define TIM_LOCKLEVEL_OFF 0x00000000U     /*!< LOCK OFF     */
#define TIM_LOCKLEVEL_1   TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
#define TIM_LOCKLEVEL_2   TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
#define TIM_LOCKLEVEL_3   TIM_BDTR_LOCK   /*!< LOCK Level 3 */
/**
 * @}
 */

/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
 * @{
 */
#define TIM_BREAK_ENABLE  TIM_BDTR_BKE /*!< Break input BRK is enabled  */
#define TIM_BREAK_DISABLE 0x00000000U  /*!< Break input BRK is disabled */
/**
 * @}
 */

/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
 * @{
 */
#define TIM_BREAKPOLARITY_LOW  0x00000000U  /*!< Break input BRK is active low  */
#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
 * @}
 */

/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
 * @{
 */
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE                                                       \
  TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event \
                   (if none of the break inputs BRK and BRK2 is active) */
/**
 * @}
 */

/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
 * @{
 */
#define TIM_TRGO_RESET  0x00000000U                                     /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
#define TIM_TRGO_ENABLE TIM_CR2_MMS_0                                   /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
#define TIM_TRGO_UPDATE TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output (TRGO)                 */
#define TIM_TRGO_OC1    (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
#define TIM_TRGO_OC1REF TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output (TRGO)                */
#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output(TRGO)                 */
#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output(TRGO)                 */
#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO)                 */
/**
 * @}
 */

/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
 * @{
 */
#define TIM_MASTERSLAVEMODE_ENABLE  TIM_SMCR_MSM /*!< No action */
#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U  /*!< Master/slave mode is selected */
/**
 * @}
 */

/** @defgroup TIM_Slave_Mode TIM Slave mode
 * @{
 */
#define TIM_SLAVEMODE_DISABLE   0x00000000U                                        /*!< Slave mode disabled           */
#define TIM_SLAVEMODE_RESET     TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
#define TIM_SLAVEMODE_GATED     (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
#define TIM_SLAVEMODE_TRIGGER   (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
/**
 * @}
 */

/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
 * @{
 */
#define TIM_OCMODE_TIMING          0x00000000U                                              /*!< Frozen                                 */
#define TIM_OCMODE_ACTIVE          TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
#define TIM_OCMODE_INACTIVE        TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
#define TIM_OCMODE_TOGGLE          (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
#define TIM_OCMODE_PWM1            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
#define TIM_OCMODE_PWM2            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
#define TIM_OCMODE_FORCED_ACTIVE   (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
/**
 * @}
 */

/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
 * @{
 */
#define TIM_TS_ITR0    0x00000000U                                     /*!< Internal Trigger 0 (ITR0)              */
#define TIM_TS_ITR1    TIM_SMCR_TS_0                                   /*!< Internal Trigger 1 (ITR1)              */
#define TIM_TS_ITR2    TIM_SMCR_TS_1                                   /*!< Internal Trigger 2 (ITR2)              */
#define TIM_TS_ITR3    (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                 /*!< Internal Trigger 3 (ITR3)              */
#define TIM_TS_TI1F_ED TIM_SMCR_TS_2                                   /*!< TI1 Edge Detector (TI1F_ED)            */
#define TIM_TS_TI1FP1  (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                 /*!< Filtered Timer Input 1 (TI1FP1)        */
#define TIM_TS_TI2FP2  (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                 /*!< Filtered Timer Input 2 (TI2FP2)        */
#define TIM_TS_ETRF    (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
#define TIM_TS_NONE    0x0000FFFFU                                     /*!< No trigger selected                    */
/**
 * @}
 */

/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
 * @{
 */
#define TIM_TRIGGERPOLARITY_INVERTED    TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx trigger sources             */
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx trigger sources             */
#define TIM_TRIGGERPOLARITY_RISING      TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING     TIM_INPUTCHANNELPOLARITY_FALLING  /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE    TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
/**
 * @}
 */

/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
 * @{
 */
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used                                                       */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
 * @}
 */

/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
 * @{
 */
#define TIM_TI1SELECTION_CH1            0x00000000U  /*!< The TIMx_CH1 pin is connected to TI1 input */
#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
 * @}
 */

/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
 * @{
 */
#define TIM_DMABURSTLENGTH_1TRANSFER   0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
#define TIM_DMABURSTLENGTH_2TRANSFERS  0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_3TRANSFERS  0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_4TRANSFERS  0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_5TRANSFERS  0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_6TRANSFERS  0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_7TRANSFERS  0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_8TRANSFERS  0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_9TRANSFERS  0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
/**
 * @}
 */

/** @defgroup DMA_Handle_index TIM DMA Handle Index
 * @{
 */
#define TIM_DMA_ID_UPDATE      ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
#define TIM_DMA_ID_CC1         ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
#define TIM_DMA_ID_CC2         ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
#define TIM_DMA_ID_CC3         ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
#define TIM_DMA_ID_CC4         ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
#define TIM_DMA_ID_TRIGGER     ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
 * @}
 */

/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
 * @{
 */
#define TIM_CCx_ENABLE   0x00000001U /*!< Input or output channel is enabled */
#define TIM_CCx_DISABLE  0x00000000U /*!< Input or output channel is disabled */
#define TIM_CCxN_ENABLE  0x00000004U /*!< Complementary output channel is enabled */
#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
/**
 * @}
 */

/**
 * @}
 */
/* End of exported constants -------------------------------------------------*/

/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
 * @{
 */

/** @brief  Reset TIM handle state.
 * @param  __HANDLE__ TIM handle.
 * @retval None
 */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)                              \
  do {                                                                        \
    (__HANDLE__)->State                        = HAL_TIM_STATE_RESET;         \
    (__HANDLE__)->ChannelState[0]              = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[1]              = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[2]              = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[3]              = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[0]             = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[1]             = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[2]             = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[3]             = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->DMABurstState                = HAL_DMA_BURST_STATE_RESET;   \
    (__HANDLE__)->Base_MspInitCallback         = NULL;                        \
    (__HANDLE__)->Base_MspDeInitCallback       = NULL;                        \
    (__HANDLE__)->IC_MspInitCallback           = NULL;                        \
    (__HANDLE__)->IC_MspDeInitCallback         = NULL;                        \
    (__HANDLE__)->OC_MspInitCallback           = NULL;                        \
    (__HANDLE__)->OC_MspDeInitCallback         = NULL;                        \
    (__HANDLE__)->PWM_MspInitCallback          = NULL;                        \
    (__HANDLE__)->PWM_MspDeInitCallback        = NULL;                        \
    (__HANDLE__)->OnePulse_MspInitCallback     = NULL;                        \
    (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;                        \
    (__HANDLE__)->Encoder_MspInitCallback      = NULL;                        \
    (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;                        \
    (__HANDLE__)->HallSensor_MspInitCallback   = NULL;                        \
    (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;                        \
  } while (0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)                  \
  do {                                                            \
    (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
    (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
    (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
  } while (0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @brief  Enable the TIM peripheral.
 * @param  __HANDLE__ TIM handle
 * @retval None
 */
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= (TIM_CR1_CEN))

/**
 * @brief  Enable the TIM main Output.
 * @param  __HANDLE__ TIM handle
 * @retval None
 */
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR |= (TIM_BDTR_MOE))

/**
 * @brief  Disable the TIM peripheral.
 * @param  __HANDLE__ TIM handle
 * @retval None
 */
#define __HAL_TIM_DISABLE(__HANDLE__)                                    \
  do {                                                                   \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) {    \
      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN);                   \
      }                                                                  \
    }                                                                    \
  } while (0)

/**
 * @brief  Disable the TIM main Output.
 * @param  __HANDLE__ TIM handle
 * @retval None
 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
 */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__)                                \
  do {                                                                   \
    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) {    \
      if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) { \
        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE);                 \
      }                                                                  \
    }                                                                    \
  } while (0)

/**
 * @brief  Disable the TIM main Output.
 * @param  __HANDLE__ TIM handle
 * @retval None
 * @note The Main Output Enable of a timer instance is disabled unconditionally
 */
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

/** @brief  Enable the specified TIM interrupt.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
 *          This parameter can be one of the following values:
 *            @arg TIM_IT_UPDATE: Update interrupt
 *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
 *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
 *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
 *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
 *            @arg TIM_IT_COM:   Commutation interrupt
 *            @arg TIM_IT_TRIGGER: Trigger interrupt
 *            @arg TIM_IT_BREAK: Break interrupt
 * @retval None
 */
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

/** @brief  Disable the specified TIM interrupt.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
 *          This parameter can be one of the following values:
 *            @arg TIM_IT_UPDATE: Update interrupt
 *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
 *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
 *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
 *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
 *            @arg TIM_IT_COM:   Commutation interrupt
 *            @arg TIM_IT_TRIGGER: Trigger interrupt
 *            @arg TIM_IT_BREAK: Break interrupt
 * @retval None
 */
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

/** @brief  Enable the specified DMA request.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __DMA__ specifies the TIM DMA request to enable.
 *          This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: Update DMA request
 *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
 *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
 *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
 *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
 *            @arg TIM_DMA_COM:   Commutation DMA request
 *            @arg TIM_DMA_TRIGGER: Trigger DMA request
 * @retval None
 */
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))

/** @brief  Disable the specified DMA request.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __DMA__ specifies the TIM DMA request to disable.
 *          This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: Update DMA request
 *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
 *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
 *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
 *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
 *            @arg TIM_DMA_COM:   Commutation DMA request
 *            @arg TIM_DMA_TRIGGER: Trigger DMA request
 * @retval None
 */
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

/** @brief  Check whether the specified TIM interrupt flag is set or not.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __FLAG__ specifies the TIM interrupt flag to check.
 *        This parameter can be one of the following values:
 *            @arg TIM_FLAG_UPDATE: Update interrupt flag
 *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
 *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
 *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
 *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
 *            @arg TIM_FLAG_COM:  Commutation interrupt flag
 *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
 *            @arg TIM_FLAG_BREAK: Break interrupt flag
 *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
 *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
 *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
 *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
 * @retval The new state of __FLAG__ (TRUE or FALSE).
 */
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

/** @brief  Clear the specified TIM interrupt flag.
 * @param  __HANDLE__ specifies the TIM Handle.
 * @param  __FLAG__ specifies the TIM interrupt flag to clear.
 *        This parameter can be one of the following values:
 *            @arg TIM_FLAG_UPDATE: Update interrupt flag
 *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
 *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
 *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
 *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
 *            @arg TIM_FLAG_COM:  Commutation interrupt flag
 *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
 *            @arg TIM_FLAG_BREAK: Break interrupt flag
 *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
 *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
 *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
 *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
 * @retval The new state of __FLAG__ (TRUE or FALSE).
 */
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))

/**
 * @brief  Check whether the specified TIM interrupt source is enabled or not.
 * @param  __HANDLE__ TIM handle
 * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
 *          This parameter can be one of the following values:
 *            @arg TIM_IT_UPDATE: Update interrupt
 *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
 *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
 *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
 *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
 *            @arg TIM_IT_COM:   Commutation interrupt
 *            @arg TIM_IT_TRIGGER: Trigger interrupt
 *            @arg TIM_IT_BREAK: Break interrupt
 * @retval The state of TIM_IT (SET or RESET).
 */
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

/** @brief Clear the TIM interrupt pending bits.
 * @param  __HANDLE__ TIM handle
 * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
 *          This parameter can be one of the following values:
 *            @arg TIM_IT_UPDATE: Update interrupt
 *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
 *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
 *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
 *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
 *            @arg TIM_IT_COM:   Commutation interrupt
 *            @arg TIM_IT_TRIGGER: Trigger interrupt
 *            @arg TIM_IT_BREAK: Break interrupt
 * @retval None
 */
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

/**
  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
  * @param  __HANDLE__ TIM handle.
  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
  */
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))

/**
 * @brief  Set the TIM Prescaler on runtime.
 * @param  __HANDLE__ TIM handle.
 * @param  __PRESC__ specifies the Prescaler new value.
 * @retval None
 */
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))

/**
 * @brief  Set the TIM Counter Register value on runtime.
 * @param  __HANDLE__ TIM handle.
 * @param  __COUNTER__ specifies the Counter register new value.
 * @retval None
 */
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))

/**
 * @brief  Get the TIM Counter Register value on runtime.
 * @param  __HANDLE__ TIM handle.
 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
 */
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)

/**
 * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
 * @param  __HANDLE__ TIM handle.
 * @param  __AUTORELOAD__ specifies the Counter register new value.
 * @retval None
 */
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
  do {                                                       \
    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);          \
    (__HANDLE__)->Init.Period   = (__AUTORELOAD__);          \
  } while (0)

/**
 * @brief  Get the TIM Autoreload Register value on runtime.
 * @param  __HANDLE__ TIM handle.
 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
 */
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)

/**
 * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
 * @param  __HANDLE__ TIM handle.
 * @param  __CKD__ specifies the clock division value.
 *          This parameter can be one of the following value:
 *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
 *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
 *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
 * @retval None
 */
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
  do {                                                   \
    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);       \
    (__HANDLE__)->Instance->CR1 |= (__CKD__);            \
    (__HANDLE__)->Init.ClockDivision = (__CKD__);        \
  } while (0)

/**
 * @brief  Get the TIM Clock Division value on runtime.
 * @param  __HANDLE__ TIM handle.
 * @retval The clock division can be one of the following values:
 *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
 *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
 *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
 */
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

/**
 * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPSC_DIV1: no prescaler
 *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 * @retval None
 */
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)   \
  do {                                                                  \
    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));            \
    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  } while (0)

/**
 * @brief  Get the TIM Input Capture prescaler on runtime.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
 *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
 *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
 *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
 * @retval The input capture prescaler can be one of the following values:
 *            @arg TIM_ICPSC_DIV1: no prescaler
 *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 */
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)                                         \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC)         \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC)         \
                                      : (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

/**
 * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  __COMPARE__ specifies the Capture Compare register new value.
 * @retval None
 */
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)                    \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) \
                                      : ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))

/**
 * @brief  Get the TIM Capture Compare Register value on runtime.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channel associated with the capture compare register
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
 *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
 *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
 *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
 */
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)                 \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCR1) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) \
                                      : ((__HANDLE__)->Instance->CCR4))

/**
 * @brief  Set the TIM Output compare preload.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval None
 */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)                               \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) \
                                      : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))

/**
 * @brief  Reset the TIM Output compare preload.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval None
 */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)                               \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) \
                                      : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))

/**
 * @brief  Enable fast mode for a given channel.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @note  When fast mode is enabled an active edge on the trigger input acts
 *        like a compare match on CCx output. Delay to sample the trigger
 *        input and to activate CCx output is reduced to 3 clock cycles.
 * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
 * @retval None
 */
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)                                  \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) \
                                      : ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))

/**
 * @brief  Disable fast mode for a given channel.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @note  When fast mode is disabled CCx output behaves normally depending
 *        on counter and CCRx values even when the trigger is ON. The minimum
 *        delay to activate CCx output when an active edge occurs on the
 *        trigger input is 5 clock cycles.
 * @retval None
 */
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)                                  \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) \
                                      : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))

/**
 * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
 * @param  __HANDLE__ TIM handle.
 * @note  When the URS bit of the TIMx_CR1 register is set, only counter
 *        overflow/underflow generates an update interrupt or DMA request (if
 *        enabled)
 * @retval None
 */
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= TIM_CR1_URS)

/**
 * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
 * @param  __HANDLE__ TIM handle.
 * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
 *        following events generate an update interrupt or DMA request (if
 *        enabled):
 *           _ Counter overflow underflow
 *           _ Setting the UG bit
 *           _ Update generation through the slave mode controller
 * @retval None
 */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_URS)

/**
 * @brief  Set the TIM Capture x input polarity on runtime.
 * @param  __HANDLE__ TIM handle.
 * @param  __CHANNEL__ TIM Channels to be configured.
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  __POLARITY__ Polarity for TIx source
 *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
 *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
 *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
 * @retval None
 */
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  do {                                                                       \
    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));                  \
    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__));    \
  } while (0)

/**
 * @}
 */
/* End of exported macros ----------------------------------------------------*/

/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_Private_Constants TIM Private Constants
 * @{
 */
/* The counter of a timer instance is disabled only if all the CCx and CCxN
   channels have been disabled */
#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
/**
 * @}
 */
/* End of private constants --------------------------------------------------*/

/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_Private_Macros TIM Private Macros
 * @{
 */
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))

#define IS_TIM_DMA_BASE(__BASE__)                                                                                                                                                      \
  (((__BASE__) == TIM_DMABASE_CR1) || ((__BASE__) == TIM_DMABASE_CR2) || ((__BASE__) == TIM_DMABASE_SMCR) || ((__BASE__) == TIM_DMABASE_DIER) || ((__BASE__) == TIM_DMABASE_SR)        \
   || ((__BASE__) == TIM_DMABASE_EGR) || ((__BASE__) == TIM_DMABASE_CCMR1) || ((__BASE__) == TIM_DMABASE_CCMR2) || ((__BASE__) == TIM_DMABASE_CCER) || ((__BASE__) == TIM_DMABASE_CNT) \
   || ((__BASE__) == TIM_DMABASE_PSC) || ((__BASE__) == TIM_DMABASE_ARR) || ((__BASE__) == TIM_DMABASE_RCR) || ((__BASE__) == TIM_DMABASE_CCR1) || ((__BASE__) == TIM_DMABASE_CCR2)    \
   || ((__BASE__) == TIM_DMABASE_CCR3) || ((__BASE__) == TIM_DMABASE_CCR4) || ((__BASE__) == TIM_DMABASE_BDTR))

#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

#define IS_TIM_COUNTER_MODE(__MODE__)                                                                                                                                             \
  (((__MODE__) == TIM_COUNTERMODE_UP) || ((__MODE__) == TIM_COUNTERMODE_DOWN) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \
   || ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || ((__STATE__) == TIM_OCFAST_ENABLE))

#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCPOLARITY_LOW))

#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || ((__STATE__) == TIM_OCIDLESTATE_RESET))

#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || ((__STATE__) == TIM_OCNIDLESTATE_RESET))

#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || ((__SELECTION__) == TIM_ICSELECTION_TRC))

#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || ((__PRESCALER__) == TIM_ICPSC_DIV2) || ((__PRESCALER__) == TIM_ICPSC_DIV4) || ((__PRESCALER__) == TIM_ICPSC_DIV8))

#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || ((__MODE__) == TIM_OPMODE_REPETITIVE))

#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || ((__MODE__) == TIM_ENCODERMODE_TI2) || ((__MODE__) == TIM_ENCODERMODE_TI12))

#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__)&0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

#define IS_TIM_CHANNELS(__CHANNEL__) \
  (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4) || ((__CHANNEL__) == TIM_CHANNEL_ALL))

#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2))

#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || ((__CHANNEL__) == TIM_CHANNEL_2) || ((__CHANNEL__) == TIM_CHANNEL_3))

#define IS_TIM_CLOCKSOURCE(__CLOCK__)                                                                                                                                       \
  (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \
   || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      \
   || ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

#define IS_TIM_CLOCKPOLARITY(__POLARITY__)                                                                                                             \
  (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \
   || ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) \
  (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)                                                                                                             \
  (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \
   || ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || ((__STATE__) == TIM_OSSR_DISABLE))

#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || ((__STATE__) == TIM_OSSI_DISABLE))

#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || ((__LEVEL__) == TIM_LOCKLEVEL_1) || ((__LEVEL__) == TIM_LOCKLEVEL_2) || ((__LEVEL__) == TIM_LOCKLEVEL_3))

#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)

#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || ((__STATE__) == TIM_BREAK_DISABLE))

#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

#define IS_TIM_TRGO_SOURCE(__SOURCE__)                                                                                                                                               \
  (((__SOURCE__) == TIM_TRGO_RESET) || ((__SOURCE__) == TIM_TRGO_ENABLE) || ((__SOURCE__) == TIM_TRGO_UPDATE) || ((__SOURCE__) == TIM_TRGO_OC1) || ((__SOURCE__) == TIM_TRGO_OC1REF) \
   || ((__SOURCE__) == TIM_TRGO_OC2REF) || ((__SOURCE__) == TIM_TRGO_OC3REF) || ((__SOURCE__) == TIM_TRGO_OC4REF))

#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

#define IS_TIM_SLAVE_MODE(__MODE__)                                                                                                                             \
  (((__MODE__) == TIM_SLAVEMODE_DISABLE) || ((__MODE__) == TIM_SLAVEMODE_RESET) || ((__MODE__) == TIM_SLAVEMODE_GATED) || ((__MODE__) == TIM_SLAVEMODE_TRIGGER) \
   || ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))

#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || ((__MODE__) == TIM_OCMODE_PWM2))

#define IS_TIM_OC_MODE(__MODE__)                                                                                                                                                                  \
  (((__MODE__) == TIM_OCMODE_TIMING) || ((__MODE__) == TIM_OCMODE_ACTIVE) || ((__MODE__) == TIM_OCMODE_INACTIVE) || ((__MODE__) == TIM_OCMODE_TOGGLE) || ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \
   || ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))

#define IS_TIM_TRIGGER_SELECTION(__SELECTION__)                                                                                                                                        \
  (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_TI1F_ED) \
   || ((__SELECTION__) == TIM_TS_TI1FP1) || ((__SELECTION__) == TIM_TS_TI2FP2) || ((__SELECTION__) == TIM_TS_ETRF))

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) \
  (((__SELECTION__) == TIM_TS_ITR0) || ((__SELECTION__) == TIM_TS_ITR1) || ((__SELECTION__) == TIM_TS_ITR2) || ((__SELECTION__) == TIM_TS_ITR3) || ((__SELECTION__) == TIM_TS_NONE))

#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)                                                                                                                 \
  (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING) \
   || ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING) || ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE))

#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) \
  (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

#define IS_TIM_DMA_LENGTH(__LENGTH__)                                                                                                                          \
  (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)        \
   || ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)    \
   || ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)    \
   || ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \
   || ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \
   || ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)

#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)                           \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__))         \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__))         \
                                      : ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)                                  \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) \
                                      : ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                           \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__))         \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) \
                                      : ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)                                                  \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P))                  \
                                      : ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))

#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)                \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? (__HANDLE__)->ChannelState[0] \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] \
                                      : (__HANDLE__)->ChannelState[3])

#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)                     \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) \
                                      : ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))

#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
  do {                                                           \
    (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);         \
    (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);         \
    (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);         \
    (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);         \
  } while (0)

#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)               \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? (__HANDLE__)->ChannelNState[0] \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] \
                                      : (__HANDLE__)->ChannelNState[3])

#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)                    \
  (((__CHANNEL__) == TIM_CHANNEL_1)   ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) \
   : ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) \
                                      : ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))

#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \
  do {                                                             \
    (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__);          \
    (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__);          \
    (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__);          \
    (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__);          \
  } while (0)

/**
 * @}
 */
/* End of private macros -----------------------------------------------------*/

/* Include TIM HAL Extended module */
#include "stm32f1xx_hal_tim_ex.h"

/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIM_Exported_Functions TIM Exported Functions
 * @{
 */

/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
 *  @brief   Time Base functions
 * @{
 */
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
 *  @brief   TIM Output Compare functions
 * @{
 */
/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
 *  @brief   TIM PWM functions
 * @{
 */
/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
 *  @brief   TIM Input Capture functions
 * @{
 */
/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
 *  @brief   TIM One Pulse functions
 * @{
 */
/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
 *  @brief   TIM Encoder functions
 * @{
 */
/* Timer Encoder functions ****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void              HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
 *  @brief   IRQ handler management
 * @{
 */
/* Interrupt Handler functions  ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
 *  @brief   Peripheral Control functions
 * @{
 */
/* Control functions  *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t          HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
 *  @brief   TIM Callbacks functions
 * @{
 */
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);

/* Callbacks Register/UnRegister functions  ***********************************/

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
 *  @brief  Peripheral State functions
 * @{
 */
/* Peripheral State functions  ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);

/* Peripheral Channel state functions  ************************************************/
HAL_TIM_ActiveChannel        HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef  HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
 * @}
 */

/**
 * @}
 */
/* End of exported functions -------------------------------------------------*/

/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
 * @{
 */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);

void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @}
 */
/* End of private functions --------------------------------------------------*/

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* STM32F1xx_HAL_TIM_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_tim_ex.h
 * @author  MCD Application Team
 * @brief   Header file of TIM HAL Extended module.
 ******************************************************************************
 * @attention
 *
 * 
© Copyright (c) 2016 STMicroelectronics.
 * All rights reserved.

 *
 * This software component is licensed by ST under BSD 3-Clause license,
 * the "License"; You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                        opensource.org/licenses/BSD-3-Clause
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_TIM_EX_H
#define STM32F1xx_HAL_TIM_EX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @addtogroup TIMEx
 * @{
 */

/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
 * @{
 */

/**
 * @brief  TIM Hall sensor Configuration Structure definition
 */

typedef struct {
  uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
                             This parameter can be a value of @ref TIM_Input_Capture_Polarity */

  uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

  uint32_t IC1Filter; /*!< Specifies the input capture filter.
                           This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

  uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
 * @}
 */
/* End of exported types -----------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
 * @{
 */

/** @defgroup TIMEx_Remap TIM Extended Remapping
 * @{
 */
/**
 * @}
 */

/**
 * @}
 */
/* End of exported constants -------------------------------------------------*/

/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
 * @{
 */

/**
 * @}
 */
/* End of exported macro -----------------------------------------------------*/

/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
 * @{
 */

/**
 * @}
 */
/* End of private macro ------------------------------------------------------*/

/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
 * @{
 */

/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
 *  @brief    Timer Hall Sensor functions
 * @{
 */
/*  Timer Hall Sensor functions  **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);

void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);

/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
 *  @brief   Timer Complementary Output Compare functions
 * @{
 */
/*  Timer Complementary Output Compare functions  *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
 *  @brief    Timer Complementary PWM functions
 * @{
 */
/*  Timer Complementary PWM functions  ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
 *  @brief    Timer Complementary One Pulse functions
 * @{
 */
/*  Timer Complementary One Pulse functions  **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
 *  @brief    Peripheral Control functions
 * @{
 */
/* Extended Control functions  ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
 * @brief    Extended Callbacks functions
 * @{
 */
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/**
 * @}
 */

/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
 * @brief    Extended Peripheral State functions
 * @{
 */
/* Extended Peripheral State functions  ***************************************/
HAL_TIM_StateTypeDef        HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
 * @}
 */

/**
 * @}
 */
/* End of exported functions -------------------------------------------------*/

/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
 * @{
 */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
 * @}
 */
/* End of private functions --------------------------------------------------*/

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* STM32F1xx_HAL_TIM_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal.c
  * @author  MCD Application Team
  * @brief   HAL module driver.
  *          This is the common part of the HAL initialization
  *
  @verbatim
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup HAL HAL
 * @brief HAL module driver.
 * @{
 */

#ifdef HAL_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/

/** @defgroup HAL_Private_Constants HAL Private Constants
 * @{
 */
/**
 * @brief STM32F1xx HAL Driver version number V1.1.3
 */
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8]  sub2 version */
#define __STM32F1xx_HAL_VERSION_RC   (0x00U) /*!< [7:0]  release candidate */
#define __STM32F1xx_HAL_VERSION      ((__STM32F1xx_HAL_VERSION_MAIN << 24) | (__STM32F1xx_HAL_VERSION_SUB1 << 16) | (__STM32F1xx_HAL_VERSION_SUB2 << 8) | (__STM32F1xx_HAL_VERSION_RC))

#define IDCODE_DEVID_MASK 0x00000FFFU

/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/

/** @defgroup HAL_Private_Variables HAL Private Variables
 * @{
 */
__IO uint32_t       uwTick;
uint32_t            uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;     /* 1KHz */
/**
 * @}
 */
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/

/** @defgroup HAL_Exported_Functions HAL Exported Functions
 * @{
 */

/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
 *  @brief    Initialization and de-initialization functions
 *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface, the NVIC allocation and initial clock
          configuration. It initializes the systick also when timeout is needed
          and the backup domain when enabled.
      (+) de-Initializes common part of the HAL.
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) SysTick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.
@endverbatim
  * @{
  */

/**
 * @brief  This function is used to initialize the HAL Library; it must be the first
 *         instruction to be executed in the main program (before to call any other
 *         HAL function), it performs the following:
 *           Configure the Flash prefetch.
 *           Configures the SysTick to generate an interrupt each 1 millisecond,
 *           which is clocked by the HSI (at this stage, the clock is not yet
 *           configured and thus the system is running from the internal HSI at 16 MHz).
 *           Set NVIC Group Priority to 4.
 *           Calls the HAL_MspInit() callback function defined in user file
 *           "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
 *
 * @note   SysTick is used as time base for the HAL_Delay() function, the application
 *         need to ensure that the SysTick time base is always set to 1 millisecond
 *         to have correct HAL operation.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_Init(void) {
  /* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) ||    \
    defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)

  /* Prefetch buffer is not available on value line devices */
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);

  /* Init the low level hardware */
  HAL_MspInit();

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief This function de-Initializes common part of the HAL and stops the systick.
 *        of time base.
 * @note This function is optional.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DeInit(void) {
  /* Reset of all peripherals */
  __HAL_RCC_APB1_FORCE_RESET();
  __HAL_RCC_APB1_RELEASE_RESET();

  __HAL_RCC_APB2_FORCE_RESET();
  __HAL_RCC_APB2_RELEASE_RESET();

#if defined(STM32F105xC) || defined(STM32F107xC)
  __HAL_RCC_AHB_FORCE_RESET();
  __HAL_RCC_AHB_RELEASE_RESET();
#endif

  /* De-Init the low level hardware */
  HAL_MspDeInit();

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Initialize the MSP.
 * @retval None
 */
__weak void HAL_MspInit(void) {
  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes the MSP.
 * @retval None
 */
__weak void HAL_MspDeInit(void) {
  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief This function configures the source of the time base.
 *        The time source is configured  to have 1ms time base with a dedicated
 *        Tick interrupt priority.
 * @note This function is called  automatically at the beginning of program after
 *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
 * @note In the default implementation, SysTick timer is the source of time base.
 *       It is used to generate interrupts at regular time intervals.
 *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
 *       The SysTick interrupt must have higher priority (numerically lower)
 *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
 *       The function is declared as __weak  to be overwritten  in case of other
 *       implementation  in user file.
 * @param TickPriority Tick interrupt priority.
 * @retval HAL status
 */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS)) {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
    uwTickPrio = TickPriority;
  } else {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
  *  @brief    HAL Control functions
  *
@verbatim
 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

@endverbatim
  * @{
  */

/**
 * @brief This function is called to increment  a global variable "uwTick"
 *        used as application time base.
 * @note In the default implementation, this variable is incremented each 1ms
 *       in SysTick ISR.
 * @note This function is declared as __weak to be overwritten in case of other
 *      implementations in user file.
 * @retval None
 */
__weak void HAL_IncTick(void) { uwTick += uwTickFreq; }

/**
 * @brief Provides a tick value in millisecond.
 * @note  This function is declared as __weak to be overwritten in case of other
 *       implementations in user file.
 * @retval tick value
 */
__weak uint32_t HAL_GetTick(void) { return uwTick; }

/**
 * @brief This function returns a tick priority.
 * @retval tick priority
 */
uint32_t HAL_GetTickPrio(void) { return uwTickPrio; }

/**
 * @brief Set new tick Freq.
 * @retval Status
 */
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) {
  HAL_StatusTypeDef status = HAL_OK;
  assert_param(IS_TICKFREQ(Freq));

  if (uwTickFreq != Freq) {
    uwTickFreq = Freq;

    /* Apply the new tick Freq  */
    status = HAL_InitTick(uwTickPrio);
  }

  return status;
}

/**
 * @brief Return tick frequency.
 * @retval tick period in Hz
 */
HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; }

/**
 * @brief This function provides minimum delay (in milliseconds) based
 *        on variable incremented.
 * @note In the default implementation , SysTick timer is the source of time base.
 *       It is used to generate interrupts at regular time intervals where uwTick
 *       is incremented.
 * @note This function is declared as __weak to be overwritten in case of other
 *       implementations in user file.
 * @param Delay specifies the delay time length, in milliseconds.
 * @retval None
 */
__weak void HAL_Delay(uint32_t Delay) {
  uint32_t tickstart = HAL_GetTick();
  uint32_t wait      = Delay;

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY) {
    wait += (uint32_t)(uwTickFreq);
  }

  while ((HAL_GetTick() - tickstart) < wait) {
  }
}

/**
 * @brief Suspend Tick increment.
 * @note In the default implementation , SysTick timer is the source of time base. It is
 *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
 *       is called, the SysTick interrupt will be disabled and so Tick increment
 *       is suspended.
 * @note This function is declared as __weak to be overwritten in case of other
 *       implementations in user file.
 * @retval None
 */
__weak void HAL_SuspendTick(void) {
  /* Disable SysTick Interrupt */
  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}

/**
 * @brief Resume Tick increment.
 * @note In the default implementation , SysTick timer is the source of time base. It is
 *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
 *       is called, the SysTick interrupt will be enabled and so Tick increment
 *       is resumed.
 * @note This function is declared as __weak to be overwritten in case of other
 *       implementations in user file.
 * @retval None
 */
__weak void HAL_ResumeTick(void) {
  /* Enable SysTick Interrupt */
  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}

/**
 * @brief  Returns the HAL revision
 * @retval version 0xXYZR (8bits for each decimal, R for RC)
 */
uint32_t HAL_GetHalVersion(void) { return __STM32F1xx_HAL_VERSION; }

/**
 * @brief Returns the device revision identifier.
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval Device revision identifier
 */
uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); }

/**
 * @brief  Returns the device identifier.
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval Device identifier
 */
uint32_t HAL_GetDEVID(void) { return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); }

/**
 * @brief  Enable the Debug Module during SLEEP mode
 * @retval None
 */
void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }

/**
 * @brief  Disable the Debug Module during SLEEP mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval None
 */
void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); }

/**
 * @brief  Enable the Debug Module during STOP mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * Note: On all STM32F1 devices:
 *       If the system tick timer interrupt is enabled during the Stop mode
 *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
 *       the system from Stop mode.
 *       Workaround: To debug the Stop mode, disable the system tick timer
 *       interrupt.
 *       Refer to errata sheet of these devices for more details.
 * Note: On all STM32F1 devices:
 *       If the system tick timer interrupt is enabled during the Stop mode
 *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
 *       the system from Stop mode.
 *       Workaround: To debug the Stop mode, disable the system tick timer
 *       interrupt.
 *       Refer to errata sheet of these devices for more details.
 * @retval None
 */
void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }

/**
 * @brief  Disable the Debug Module during STOP mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval None
 */
void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); }

/**
 * @brief  Enable the Debug Module during STANDBY mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval None
 */
void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }

/**
 * @brief  Disable the Debug Module during STANDBY mode
 * Note: On devices STM32F10xx8 and STM32F10xxB,
 *                  STM32F101xC/D/E and STM32F103xC/D/E,
 *                  STM32F101xF/G and STM32F103xF/G
 *                  STM32F10xx4 and STM32F10xx6
 *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
 *       debug mode (not accessible by the user software in normal mode).
 *       Refer to errata sheet of these devices for more details.
 * @retval None
 */
void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); }

/**
 * @brief Return the unique device identifier (UID based on 96 bits)
 * @param UID pointer to 3 words array.
 * @retval Device identifier
 */
void HAL_GetUID(uint32_t *UID) {
  UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
  UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
  UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}

/**
 * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
 * @retval Device identifier
 */
uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); }

/**
 * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
 * @retval Device identifier
 */
uint32_t HAL_GetUIDw1(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); }

/**
 * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
 * @retval Device identifier
 */
uint32_t HAL_GetUIDw2(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); }

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_adc.c
  * @author  MCD Application Team
  * @brief   This file provides firmware functions to manage the following
  *          functionalities of the Analog to Digital Convertor (ADC)
  *          peripheral:
  *           + Initialization and de-initialization functions
  *             ++ Initialization and Configuration of ADC
  *           + Operation functions
  *             ++ Start, stop, get result of conversions of regular
  *                group, using 3 possible modes: polling, interruption or DMA.
  *           + Control functions
  *             ++ Channels configuration on regular group
  *             ++ Channels configuration on injected group
  *             ++ Analog Watchdog configuration
  *           + State functions
  *             ++ ADC state machine management
  *             ++ Interrupts and flags management
  *          Other functions (extended functions) are available in file
  *          "stm32f1xx_hal_adc_ex.c".
  *
  @verbatim
  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit resolution

  (+) Interrupt generation at the end of regular conversion, end of injected
      conversion, and in case of analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) ADC conversion of regular group and injected group.

  (+) External trigger (timer or EXTI)
      for both regular and injected groups.

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Multimode Dual mode (available on devices with 2 ADCs or more).

  (+) Configurable DMA data storage in Multimode Dual mode (available on devices
      with 2 DCs or more).

  (+) Configurable delay between conversions in Dual interleaved mode (available
      on devices with 2 DCs or more).

  (+) ADC calibration

  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
      slower speed.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).


                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
      (++) As prerequisite, ADC clock must be configured at RCC top level.
           Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
                    to device datasheet).
                    Therefore, ADC clock prescaler must be configured in
                    function of ADC clock source frequency to remain below
                    this maximum frequency.
        (++) One clock setting is mandatory:
             ADC clock (core clock, also possibly conversion clock).
             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) RCC_PeriphCLKInitTypeDef  PeriphClkInit;
               (+++) __ADC1_CLK_ENABLE();
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, groups regular/injected, channels parameters ***
     ==========================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the injected group parameters (conversion trigger,
        sequencer, ..., of injected group)
        and the channels for injected group parameters (channel number,
        channel rank into sequencer, ..., into injected group)
        using function HAL_ADCEx_InjectedConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

    (#) Optionally, for devices with several ADC instances: configure the
        multimode parameters
        using function HAL_ADCEx_MultiModeConfigChannel().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
                (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
                (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

        (++) For devices with several ADCs: ADC multimode conversion
             with transfer by DMA:
          (+++) Activate the ADC peripheral (slave) and start conversions
                using function HAL_ADC_Start()
          (+++) Activate the ADC peripheral (master) and start conversions
                using function HAL_ADCEx_MultiModeStart_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral (master)
                using function HAL_ADCEx_MultiModeStop_DMA()
          (+++) Stop conversion and disable the ADC peripheral (slave)
                using function HAL_ADC_Stop_IT()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback
      (+@) HAL_ADCEx_InjectedConvCpltCallback()

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]

    @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup ADC ADC
 * @brief ADC HAL module driver
 * @{
 */

#ifdef HAL_ADC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
 * @{
 */

/* Timeout values for ADC enable and disable settling time.                 */
/* Values defined to be higher than worst cases: low clocks freq,           */
/* maximum prescaler.                                                       */
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
/* Unit: ms                                                                 */
#define ADC_ENABLE_TIMEOUT  2U
#define ADC_DISABLE_TIMEOUT 2U

/* Delay for ADC stabilization time.                                        */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
/* Unit: us                                                                 */
#define ADC_STAB_DELAY_US 1U

/* Delay for temperature sensor stabilization time.                         */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
/* Unit: us                                                                 */
#define ADC_TEMPSENSOR_DELAY_US 10U

/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup ADC_Private_Functions ADC Private Functions
 * @{
 */
/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/

/** @defgroup ADC_Exported_Functions ADC Exported Functions
 * @{
 */

/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
  * @brief    Initialization and Configuration functions
  *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

@endverbatim
  * @{
  */

/**
 * @brief  Initializes the ADC peripheral and regular group according to
 *         parameters specified in structure "ADC_InitTypeDef".
 * @note   As prerequisite, ADC clock must be configured at RCC top level
 *         (clock source APB2).
 *         See commented example code below that can be copied and uncommented
 *         into HAL_ADC_MspInit().
 * @note   Possibility to update parameters on the fly:
 *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
 *         coming from ADC state reset. Following calls to this function can
 *         be used to reconfigure some parameters of ADC_InitTypeDef
 *         structure on the fly, without modifying MSP configuration. If ADC
 *         MSP has to be modified again, HAL_ADC_DeInit() must be called
 *         before HAL_ADC_Init().
 *         The setting of these parameters is conditioned to ADC state.
 *         For parameters constraints, see comments of structure
 *         "ADC_InitTypeDef".
 * @note   This function configures the ADC within 2 scopes: scope of entire
 *         ADC and scope of regular group. For parameters details, see comments
 *         of structure "ADC_InitTypeDef".
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  uint32_t          tmp_cr1        = 0U;
  uint32_t          tmp_cr2        = 0U;
  uint32_t          tmp_sqr1       = 0U;

  /* Check ADC handle */
  if (hadc == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));

  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
    if (hadc->Init.DiscontinuousConvMode != DISABLE) {
      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
    }
  }

  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
  /* at RCC top level.                                                        */
  /* Refer to header of this file for more details on clock enabling          */
  /* procedure.                                                               */

  /* Actions performed only if ADC is coming from state reset:                */
  /* - Initialization of ADC MSP                                              */
  if (hadc->State == HAL_ADC_STATE_RESET) {
    /* Initialize ADC error code */
    ADC_CLEAR_ERRORCODE(hadc);

    /* Allocate lock resource and initialize it */
    hadc->Lock = HAL_UNLOCKED;

    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
  }

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  /* Note: In case of ADC already enabled, precaution to not launch an        */
  /*       unwanted conversion while modifying register CR2 by writing 1 to   */
  /*       bit ADON.                                                          */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Configuration of ADC parameters if previous preliminary actions are      */
  /* correctly completed.                                                     */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK)) {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);

    /* Set ADC parameters */

    /* Configuration of ADC:                                                  */
    /*  - data alignment                                                      */
    /*  - external trigger to start conversion                                */
    /*  - external trigger polarity (always set to 1, because needed for all  */
    /*    triggers: external trigger of SW start)                             */
    /*  - continuous conversion mode                                          */
    /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
    /*       HAL_ADC_Start_xxx functions because if set in this function,     */
    /*       a conversion on injected group would start a conversion also on  */
    /*       regular group after ADC enabling.                                */
    tmp_cr2 |= (hadc->Init.DataAlign | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode));

    /* Configuration of ADC:                                                  */
    /*  - scan mode                                                           */
    /*  - discontinuous mode disable/enable                                   */
    /*  - discontinuous mode number of conversions                            */
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));

    /* Enable discontinuous mode only if continuous mode is disabled */
    /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
    /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
    if (hadc->Init.DiscontinuousConvMode == ENABLE) {
      if (hadc->Init.ContinuousConvMode == DISABLE) {
        /* Enable the selected ADC regular discontinuous mode */
        /* Set the number of channels to be converted in discontinuous mode */
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion));
      } else {
        /* ADC regular group settings continuous and sequencer discontinuous*/
        /* cannot be enabled simultaneously.                                */

        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
      }
    }

    /* Update ADC configuration register CR1 with previous settings */
    MODIFY_REG(hadc->Instance->CR1, ADC_CR1_SCAN | ADC_CR1_DISCEN | ADC_CR1_DISCNUM, tmp_cr1);

    /* Update ADC configuration register CR2 with previous settings */
    MODIFY_REG(hadc->Instance->CR2, ADC_CR2_ALIGN | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG | ADC_CR2_CONT, tmp_cr2);

    /* Configuration of regular group sequencer:                              */
    /* - if scan mode is disabled, regular channels sequence length is set to */
    /*   0x00: 1 channel converted (channel on regular rank 1)                */
    /*   Parameter "NbrOfConversion" is discarded.                            */
    /*   Note: Scan mode is present by hardware on this device and, if        */
    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
    /* - if scan mode is enabled, regular channels sequence length is set to  */
    /*   parameter "NbrOfConversion"                                          */
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) {
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
    }

    MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, tmp_sqr1);

    /* Check back that ADC registers have effectively been configured to      */
    /* ensure of no potential problem of ADC core IP clocking.                */
    /* Check through register CR2 (excluding bits set in other functions:     */
    /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
    /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
    /* measurement path bit (TSVREFE).                                        */
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE)) == tmp_cr2) {
      /* Set ADC error code to none */
      ADC_CLEAR_ERRORCODE(hadc);

      /* Set the ADC state */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
    } else {
      /* Update ADC state machine to error */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);

      /* Set ADC error code to ADC IP internal error */
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);

      tmp_hal_status = HAL_ERROR;
    }

  } else {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);

    tmp_hal_status = HAL_ERROR;
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Deinitialize the ADC peripheral registers to their default reset
 *         values, with deinitialization of the ADC MSP.
 *         If needed, the example code can be copied and uncommented into
 *         function HAL_ADC_MspDeInit().
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check ADC handle */
  if (hadc == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Configuration of ADC parameters if previous preliminary actions are      */
  /* correctly completed.                                                     */
  if (tmp_hal_status == HAL_OK) {
    /* ========== Reset ADC registers ========== */

    /* Reset register SR */
    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | ADC_FLAG_JSTRT | ADC_FLAG_STRT));

    /* Reset register CR1 */
    CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
                                    ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH));

    /* Reset register CR2 */
    CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
                                    ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | ADC_CR2_ADON));

    /* Reset register SMPR1 */
    CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10));

    /* Reset register SMPR2 */
    CLEAR_BIT(hadc->Instance->SMPR2,
              (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0));

    /* Reset register JOFR1 */
    CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
    /* Reset register JOFR2 */
    CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
    /* Reset register JOFR3 */
    CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
    /* Reset register JOFR4 */
    CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);

    /* Reset register HTR */
    CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
    /* Reset register LTR */
    CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);

    /* Reset register SQR1 */
    CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13);

    /* Reset register SQR1 */
    CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13);

    /* Reset register SQR2 */
    CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7);

    /* Reset register SQR3 */
    CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1);

    /* Reset register JSQR */
    CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1);

    /* Reset register JSQR */
    CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1);

    /* Reset register DR */
    /* bits in access mode read only, no direct reset applicable*/

    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
    /* bits in access mode read only, no direct reset applicable*/

    /* ========== Hard reset ADC peripheral ========== */
    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
    /* forced to a similar state after device power-on.                       */
    /* If needed, copy-paste and uncomment the following reset code into      */
    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
    /*                                                                        */
    /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */

    /* DeInit the low level hardware */
    HAL_ADC_MspDeInit(hadc);

    /* Set ADC error code to none */
    ADC_CLEAR_ERRORCODE(hadc);

    /* Set ADC state */
    hadc->State = HAL_ADC_STATE_RESET;
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Initializes the ADC MSP.
 * @param  hadc: ADC handle
 * @retval None
 */
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_MspInit must be implemented in the user file.
   */
}

/**
 * @brief  DeInitializes the ADC MSP.
 * @param  hadc: ADC handle
 * @retval None
 */
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_MspDeInit must be implemented in the user file.
   */
}

/**
 * @}
 */

/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
 *  @brief    Input and Output operation functions
 *
@verbatim
 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.
@endverbatim
  * @{
  */

/**
 * @brief  Enables ADC, starts conversion of regular group.
 *         Interruptions enabled in this function: None.
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Enable the ADC peripheral */
  tmp_hal_status = ADC_Enable(hadc);

  /* Start conversion if ADC is effectively enabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to regular group conversion results     */
    /* - Set state bitfield related to regular operation                      */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY);

    /* Set group injected state (from auto-injection) and multimode state     */
    /* for all cases of multimode: independent mode, multimode ADC master     */
    /* or multimode ADC slave (for devices with several ADCs):                */
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      /* Set ADC state (ADC independent or master) */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

      /* If conversions on group regular are also triggering group injected,  */
      /* update ADC state.                                                    */
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) {
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
      }
    } else {
      /* Set ADC state (ADC slave) */
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

      /* If conversions on group regular are also triggering group injected,  */
      /* update ADC state.                                                    */
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) {
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
      }
    }

    /* State machine update: Check if an injected conversion is ongoing */
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
      /* Reset ADC error code fields related to conversions on group regular */
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
    } else {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);

    /* Clear regular group conversion flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);

    /* Enable conversion of regular group.                                    */
    /* If software start has been selected, conversion starts immediately.    */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* Case of multimode enabled:                                             */
    /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
    /*  - if ADC is master, ADC is enabled and conversion is started.         */
    /* If ADC is master, ADC is enabled and conversion is started.            */
    /* Note: Alternate trigger for single conversion could be to force an     */
    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      /* Start ADC conversion on regular group with SW start */
      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
    } else {
      /* Start ADC conversion on regular group with external trigger */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
    }
  } else {
    /* Process unlocked */
    __HAL_UNLOCK(hadc);
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop ADC conversion of regular group (and injected channels in
 *         case of auto_injection mode), disable ADC peripheral.
 * @note:  ADC peripheral disable is forcing stop of potential
 *         conversion on injected group. If injected group is under use, it
 *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
 * @param  hadc: ADC handle
 * @retval HAL status.
 */
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Wait for regular group conversion to be completed.
 * @note   This function cannot be used in a particular setup: ADC configured
 *         in DMA mode.
 *         In this case, DMA resets the flag EOC and polling cannot be
 *         performed on each conversion.
 * @note   On STM32F1 devices, limitation in case of sequencer enabled
 *         (several ranks selected): polling cannot be done on each
 *         conversion inside the sequence. In this case, polling is replaced by
 *         wait for maximum conversion time.
 * @param  hadc: ADC handle
 * @param  Timeout: Timeout value in millisecond.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) {
  uint32_t tickstart = 0U;

  /* Variables for polling in case of scan mode enabled and polling for each  */
  /* conversion.                                                              */
  __IO uint32_t Conversion_Timeout_CPU_cycles     = 0U;
  uint32_t      Conversion_Timeout_CPU_cycles_max = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Get tick count */
  tickstart = HAL_GetTick();

  /* Verification that ADC configuration is compliant with polling for        */
  /* each conversion:                                                         */
  /* Particular case is ADC configured in DMA mode                            */
  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

    /* Process unlocked */
    __HAL_UNLOCK(hadc);

    return HAL_ERROR;
  }

  /* Polling for end of conversion: differentiation if single/sequence        */
  /* conversion.                                                              */
  /*  - If single conversion for regular group (Scan mode disabled or enabled */
  /*    with NbrOfConversion =1), flag EOC is used to determine the           */
  /*    conversion completion.                                                */
  /*  - If sequence conversion for regular group (scan mode enabled and       */
  /*    NbrOfConversion >=2), flag EOC is set only at the end of the          */
  /*    sequence.                                                             */
  /*    To poll for each conversion, the maximum conversion time is computed  */
  /*    from ADC conversion time (selected sampling time + conversion time of */
  /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
  /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
  /*    As flag EOC is not set after each conversion, no timeout status can   */
  /*    be set.                                                               */
  if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)) {
    /* Wait until End of Conversion flag is raised */
    while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) {
      /* Check if timeout is disabled (set to infinite wait) */
      if (Timeout != HAL_MAX_DELAY) {
        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
          /* Update ADC state machine to timeout */
          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);

          /* Process unlocked */
          __HAL_UNLOCK(hadc);

          return HAL_TIMEOUT;
        }
      }
    }
  } else {
    /* Replace polling by wait for maximum conversion time */
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
    /*    and ADC maximum conversion cycles on all channels.                  */
    /*  - Wait for the expected ADC clock cycles delay                        */
    Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc));

    while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) {
      /* Check if timeout is disabled (set to infinite wait) */
      if (Timeout != HAL_MAX_DELAY) {
        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
          /* Update ADC state machine to timeout */
          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);

          /* Process unlocked */
          __HAL_UNLOCK(hadc);

          return HAL_TIMEOUT;
        }
      }
      Conversion_Timeout_CPU_cycles++;
    }
  }

  /* Clear regular group conversion flag */
  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);

  /* Update ADC state machine */
  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);

  /* Determine whether any further conversion upcoming on group regular       */
  /* by external trigger, continuous mode or scan sequence on going.          */
  /* Note: On STM32F1 devices, in case of sequencer enabled                   */
  /*       (several ranks selected), end of conversion flag is raised         */
  /*       at the end of the sequence.                                        */
  if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) {
    /* Set ADC state */
    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);

    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
    }
  }

  /* Return ADC state */
  return HAL_OK;
}

/**
 * @brief  Poll for conversion event.
 * @param  hadc: ADC handle
 * @param  EventType: the ADC event type.
 *          This parameter can be one of the following values:
 *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
 * @param  Timeout: Timeout value in millisecond.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) {
  uint32_t tickstart = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_EVENT_TYPE(EventType));

  /* Get tick count */
  tickstart = HAL_GetTick();

  /* Check selected event flag */
  while (__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) {
    /* Check if timeout is disabled (set to infinite wait) */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
        /* Update ADC state machine to timeout */
        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);

        return HAL_TIMEOUT;
      }
    }
  }

  /* Analog watchdog (level out of window) event */
  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);

  /* Clear ADC analog watchdog flag */
  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);

  /* Return ADC state */
  return HAL_OK;
}

/**
 * @brief  Enables ADC, starts conversion of regular group with interruption.
 *         Interruptions enabled in this function:
 *          - EOC (end of conversion of regular group)
 *         Each of these interruptions has its dedicated callback function.
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Enable the ADC peripheral */
  tmp_hal_status = ADC_Enable(hadc);

  /* Start conversion if ADC is effectively enabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to regular group conversion results     */
    /* - Set state bitfield related to regular operation                      */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY);

    /* Set group injected state (from auto-injection) and multimode state     */
    /* for all cases of multimode: independent mode, multimode ADC master     */
    /* or multimode ADC slave (for devices with several ADCs):                */
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      /* Set ADC state (ADC independent or master) */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

      /* If conversions on group regular are also triggering group injected,  */
      /* update ADC state.                                                    */
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) {
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
      }
    } else {
      /* Set ADC state (ADC slave) */
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

      /* If conversions on group regular are also triggering group injected,  */
      /* update ADC state.                                                    */
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) {
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
      }
    }

    /* State machine update: Check if an injected conversion is ongoing */
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
      /* Reset ADC error code fields related to conversions on group regular */
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
    } else {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);

    /* Clear regular group conversion flag and overrun flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);

    /* Enable end of conversion interrupt for regular group */
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);

    /* Enable conversion of regular group.                                    */
    /* If software start has been selected, conversion starts immediately.    */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* Case of multimode enabled:                                             */
    /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
    /*  - if ADC is master, ADC is enabled and conversion is started.         */
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      /* Start ADC conversion on regular group with SW start */
      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
    } else {
      /* Start ADC conversion on regular group with external trigger */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
    }
  } else {
    /* Process unlocked */
    __HAL_UNLOCK(hadc);
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop ADC conversion of regular group (and injected group in
 *         case of auto_injection mode), disable interrution of
 *         end-of-conversion, disable ADC peripheral.
 * @param  hadc: ADC handle
 * @retval None
 */
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK) {
    /* Disable ADC end of conversion interrupt for regular group */
    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);

    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Enables ADC, starts conversion of regular group and transfers result
 *         through DMA.
 *         Interruptions enabled in this function:
 *          - DMA transfer complete
 *          - DMA half transfer
 *         Each of these interruptions has its dedicated callback function.
 * @note   For devices with several ADCs: This function is for single-ADC mode
 *         only. For multimode, use the dedicated MultimodeStart function.
 * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
 *         on devices) have DMA capability.
 *         ADC2 converted data can be transferred in dual ADC mode using DMA
 *         of ADC1 (ADC master in multimode).
 *         In case of using ADC1 with DMA on a device featuring 2 ADC
 *         instances: ADC1 conversion register DR contains ADC1 conversion
 *         result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
 *         conversion result (ADC1 register DR bits 16 to 27). Therefore, to
 *         have DMA transferring the conversion results of ADC1 only, DMA must
 *         be configured to transfer size: half word.
 * @param  hadc: ADC handle
 * @param  pData: The destination Buffer address.
 * @param  Length: The length of data to be transferred from ADC peripheral to memory.
 * @retval None
 */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));

  /* Verification if multimode is disabled (for devices with several ADC)     */
  /* If multimode is enabled, dedicated function multimode conversion         */
  /* start DMA must be used.                                                  */
  if (ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) {
    /* Process locked */
    __HAL_LOCK(hadc);

    /* Enable the ADC peripheral */
    tmp_hal_status = ADC_Enable(hadc);

    /* Start conversion if ADC is effectively enabled */
    if (tmp_hal_status == HAL_OK) {
      /* Set ADC state                                                        */
      /* - Clear state bitfield related to regular group conversion results   */
      /* - Set state bitfield related to regular operation                    */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY);

      /* Set group injected state (from auto-injection) and multimode state     */
      /* for all cases of multimode: independent mode, multimode ADC master     */
      /* or multimode ADC slave (for devices with several ADCs):                */
      if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
        /* Set ADC state (ADC independent or master) */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

        /* If conversions on group regular are also triggering group injected,  */
        /* update ADC state.                                                    */
        if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) {
          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
        }
      } else {
        /* Set ADC state (ADC slave) */
        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);

        /* If conversions on group regular are also triggering group injected,  */
        /* update ADC state.                                                    */
        if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) {
          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
        }
      }

      /* State machine update: Check if an injected conversion is ongoing */
      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
        /* Reset ADC error code fields related to conversions on group regular */
        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
      } else {
        /* Reset ADC all error code fields */
        ADC_CLEAR_ERRORCODE(hadc);
      }

      /* Process unlocked */
      /* Unlock before starting ADC conversions: in case of potential         */
      /* interruption, to let the process to ADC IRQ Handler.                 */
      __HAL_UNLOCK(hadc);

      /* Set the DMA transfer complete callback */
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;

      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
      /* start (in case of SW start):                                         */

      /* Clear regular group conversion flag and overrun flag */
      /* (To ensure of no unknown state from potential previous ADC           */
      /* operations)                                                          */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);

      /* Enable ADC DMA mode */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);

      /* Start the DMA channel */
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);

      /* Enable conversion of regular group.                                  */
      /* If software start has been selected, conversion starts immediately.  */
      /* If external trigger has been selected, conversion will start at next */
      /* trigger event.                                                       */
      if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) {
        /* Start ADC conversion on regular group with SW start */
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
      } else {
        /* Start ADC conversion on regular group with external trigger */
        SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
      }
    } else {
      /* Process unlocked */
      __HAL_UNLOCK(hadc);
    }
  } else {
    tmp_hal_status = HAL_ERROR;
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop ADC conversion of regular group (and injected group in
 *         case of auto_injection mode), disable ADC DMA transfer, disable
 *         ADC peripheral.
 * @note:  ADC peripheral disable is forcing stop of potential
 *         conversion on injected group. If injected group is under use, it
 *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
 * @note   For devices with several ADCs: This function is for single-ADC mode
 *         only. For multimode, use the dedicated MultimodeStop function.
 * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
 *         on devices) have DMA capability.
 * @param  hadc: ADC handle
 * @retval HAL status.
 */
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK) {
    /* Disable ADC DMA mode */
    CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);

    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
    /* DMA transfer is on going)                                              */
    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);

    /* Check if DMA channel effectively disabled */
    if (tmp_hal_status == HAL_OK) {
      /* Set ADC state */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
    } else {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
    }
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Get ADC regular group conversion result.
 * @note   Reading register DR automatically clears ADC flag EOC
 *         (ADC group regular end of unitary conversion).
 * @note   This function does not clear ADC flag EOS
 *         (ADC group regular end of sequence conversion).
 *         Occurrence of flag EOS rising:
 *          - If sequencer is composed of 1 rank, flag EOS is equivalent
 *            to flag EOC.
 *          - If sequencer is composed of several ranks, during the scan
 *            sequence flag EOC only is raised, at the end of the scan sequence
 *            both flags EOC and EOS are raised.
 *         To clear this flag, either use function:
 *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
 *         model polling: @ref HAL_ADC_PollForConversion()
 *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
 * @param  hadc: ADC handle
 * @retval ADC group regular conversion data
 */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) {
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Note: EOC flag is not cleared here by software because automatically     */
  /*       cleared by hardware when reading register DR.                      */

  /* Return ADC converted value */
  return hadc->Instance->DR;
}

/**
 * @brief  Handles ADC interrupt request
 * @param  hadc: ADC handle
 * @retval None
 */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) {
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));

  /* ========== Check End of Conversion flag for regular group ========== */
  if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) {
    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)) {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
      }

      /* Determine whether any further conversion upcoming on group regular   */
      /* by external trigger, continuous mode or scan sequence on going.      */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) {
        /* Disable ADC end of conversion interrupt on group regular */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);

        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);

        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
        }
      }

      /* Clear regular group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
    }
  }

  /* ========== Check End of Conversion flag for injected group ========== */
  if (__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) {
    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
      }

      /* Determine whether any further conversion upcoming on group injected  */
      /* by external trigger, scan sequence on going or by automatic injected */
      /* conversion from group regular (same conditions as group regular      */
      /* interruption disabling above).                                       */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) {
        /* Disable ADC end of conversion interrupt on group injected */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);

        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);

        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
        }
      }

      /* Conversion complete callback */
      HAL_ADCEx_InjectedConvCpltCallback(hadc);

      /* Clear injected group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
    }
  }
}

/**
 * @}
 */

/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
 *  @brief    Peripheral Control functions
 *
@verbatim
 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

@endverbatim
  * @{
  */

/**
 * @brief  Configures the the selected channel to be linked to the regular
 *         group.
 * @note   In case of usage of internal measurement channels:
 *         Vbat/VrefInt/TempSensor.
 *         These internal paths can be be disabled using function
 *         HAL_ADC_DeInit().
 * @note   Possibility to update parameters on the fly:
 *         This function initializes channel into regular group, following
 *         calls to this function can be used to reconfigure some parameters
 *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
 *         the ADC.
 *         The setting of these parameters is conditioned to ADC state.
 *         For parameters constraints, see comments of structure
 *         "ADC_ChannelConfTypeDef".
 * @param  hadc: ADC handle
 * @param  sConfig: Structure of ADC channel for regular group.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U) {
    MODIFY_REG(hadc->Instance->SQR3, ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank), ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));
  }
  /* For Rank 7 to 12 */
  else if (sConfig->Rank < 13U) {
    MODIFY_REG(hadc->Instance->SQR2, ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank), ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));
  }
  /* For Rank 13 to 16 */
  else {
    MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank), ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));
  }

  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10) {
    MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel), ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel));
  } else /* For channels 0 to 9 */
  {
    MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel), ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel));
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Configures the analog watchdog.
 * @note   Analog watchdog thresholds can be modified while ADC conversion
 *         is on going.
 *         In this case, some constraints must be taken into account:
 *         the programmed threshold values are effective from the next
 *         ADC EOC (end of unitary conversion).
 *         Considering that registers write delay may happen due to
 *         bus activity, this might cause an uncertainty on the
 *         effective timing of the new programmed threshold values.
 * @param  hadc: ADC handle
 * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) {
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
  assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
  assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));

  if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) {
    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
  }

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Analog watchdog configuration */

  /* Configure ADC Analog watchdog interrupt */
  if (AnalogWDGConfig->ITMode == ENABLE) {
    /* Enable the ADC Analog watchdog interrupt */
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
  } else {
    /* Disable the ADC Analog watchdog interrupt */
    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
  }

  /* Configuration of analog watchdog:                                        */
  /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
  /*    one or all channels.                                                  */
  /*  - Set the Analog watchdog channel (is not used if watchdog              */
  /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                             */
  MODIFY_REG(hadc->Instance->CR1, ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDCH, AnalogWDGConfig->WatchdogMode | AnalogWDGConfig->Channel);

  /* Set the high threshold */
  WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);

  /* Set the low threshold */
  WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
 *  @brief    Peripheral State functions
 *
@verbatim
 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

@endverbatim
  * @{
  */

/**
 * @brief  return the ADC state
 * @param  hadc: ADC handle
 * @retval HAL state
 */
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) {
  /* Return ADC state */
  return hadc->State;
}

/**
 * @brief  Return the ADC error code
 * @param  hadc: ADC handle
 * @retval ADC Error Code
 */
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { return hadc->ErrorCode; }

/**
 * @}
 */

/**
 * @}
 */

/** @defgroup ADC_Private_Functions ADC Private Functions
 * @{
 */

/**
 * @brief  Enable the selected ADC.
 * @note   Prerequisite condition to use this function: ADC must be disabled
 *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
 * @param  hadc: ADC handle
 * @retval HAL status.
 */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) {
  uint32_t      tickstart       = 0U;
  __IO uint32_t wait_loop_index = 0U;

  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
  /* causes: ADC clock not running, ...).                                     */
  if (ADC_IS_ENABLE(hadc) == RESET) {
    /* Enable the Peripheral */
    __HAL_ADC_ENABLE(hadc);

    /* Delay for ADC stabilization time */
    /* Compute number of CPU cycles to wait for */
    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
    while (wait_loop_index != 0U) {
      wait_loop_index--;
    }

    /* Get tick count */
    tickstart = HAL_GetTick();

    /* Wait for ADC effectively enabled */
    while (ADC_IS_ENABLE(hadc) == RESET) {
      if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) {
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);

        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);

        return HAL_ERROR;
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
}

/**
 * @brief  Stop ADC conversion and disable the selected ADC
 * @note   Prerequisite condition to use this function: ADC conversions must be
 *         stopped to disable the ADC.
 * @param  hadc: ADC handle
 * @retval HAL status.
 */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef *hadc) {
  uint32_t tickstart = 0U;

  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET) {
    /* Disable the ADC peripheral */
    __HAL_ADC_DISABLE(hadc);

    /* Get tick count */
    tickstart = HAL_GetTick();

    /* Wait for ADC effectively disabled */
    while (ADC_IS_ENABLE(hadc) != RESET) {
      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) {
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);

        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);

        return HAL_ERROR;
      }
    }
  }

  /* Return HAL status */
  return HAL_OK;
}

/**
 * @brief  DMA transfer complete callback.
 * @param  hdma: pointer to DMA handle.
 * @retval None
 */
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) {
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Update state machine on conversion status if not in error state */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) {
    /* Update ADC state machine */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);

    /* Determine whether any further conversion upcoming on group regular     */
    /* by external trigger, continuous mode or scan sequence on going.        */
    /* Note: On STM32F1 devices, in case of sequencer enabled                 */
    /*       (several ranks selected), end of conversion flag is raised       */
    /*       at the end of the sequence.                                      */
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)) {
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);

      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) {
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
      }
    }

  } else {
    /* Call DMA error callback */
    hadc->DMA_Handle->XferErrorCallback(hdma);
  }
}

/**
 * @}
 */

#endif /* HAL_ADC_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_adc_ex.c
  * @author  MCD Application Team
  * @brief   This file provides firmware functions to manage the following
  *          functionalities of the Analog to Digital Convertor (ADC)
  *          peripheral:
  *           + Operation functions
  *             ++ Start, stop, get result of conversions of injected
  *                group, using 2 possible modes: polling, interruption.
  *             ++ Multimode feature (available on devices with 2 ADCs or more)
  *             ++ Calibration (ADC automatic self-calibration)
  *           + Control functions
  *             ++ Channels configuration on injected group
  *          Other functions (generic functions) are available in file
  *          "stm32f1xx_hal_adc.c".
  *
  @verbatim
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32f1xx_hal_adc.c".
  [..]
  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup ADCEx ADCEx
 * @brief ADC Extension HAL module driver
 * @{
 */

#ifdef HAL_ADC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
 * @{
 */

/* Delay for ADC calibration:                                               */
/* Hardware prerequisite before starting a calibration: the ADC must have   */
/* been in power-on state for at least two ADC clock cycles.                */
/* Unit: ADC clock cycles                                                   */
#define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U

/* Timeout value for ADC calibration                                        */
/* Value defined to be higher than worst cases: low clocks freq,            */
/* maximum prescaler.                                                       */
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
/* Unit: ms                                                                 */
#define ADC_CALIBRATION_TIMEOUT 10U

/* Delay for temperature sensor stabilization time.                         */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
/* Unit: us                                                                 */
#define ADC_TEMPSENSOR_DELAY_US 10U

/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
 * @{
 */

/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
 *  @brief    Extended Extended Input and Output operation functions
 *
@verbatim
 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of injected group.
      (+) Stop conversion of injected group.
      (+) Poll for conversion complete on injected group.
      (+) Get result of injected channel conversion.
      (+) Start conversion of injected group and enable interruptions.
      (+) Stop conversion of injected group and disable interruptions.

      (+) Start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

@endverbatim
  * @{
  */

/**
 * @brief  Perform an ADC automatic self-calibration
 *         Calibration prerequisite: ADC must be disabled (execute this
 *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
 *         During calibration process, ADC is enabled. ADC is let enabled at
 *         the completion of this function.
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  uint32_t          tickstart;
  __IO uint32_t     wait_loop_index = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* 1. Calibration prerequisite:                                             */
  /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
  /*      mode before ADC enable                                              */
  /* Stop potential conversion on going, on regular and injected groups       */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);

    /* Hardware prerequisite: delay before starting the calibration.          */
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
    /*  - Wait for the expected ADC clock cycles delay */
    wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES);

    while (wait_loop_index != 0U) {
      wait_loop_index--;
    }

    /* 2. Enable the ADC peripheral */
    ADC_Enable(hadc);

    /* 3. Resets ADC calibration registers */
    SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);

    tickstart = HAL_GetTick();

    /* Wait for calibration reset completion */
    while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) {
      if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);

        return HAL_ERROR;
      }
    }

    /* 4. Start ADC calibration */
    SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);

    tickstart = HAL_GetTick();

    /* Wait for calibration completion */
    while (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) {
      if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);

        /* Process unlocked */
        __HAL_UNLOCK(hadc);

        return HAL_ERROR;
      }
    }

    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Enables ADC, starts conversion of injected group.
 *         Interruptions enabled in this function: None.
 * @param  hadc: ADC handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Enable the ADC peripheral */
  tmp_hal_status = ADC_Enable(hadc);

  /* Start conversion if ADC is effectively enabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to injected group conversion results    */
    /* - Set state bitfield related to injected operation                     */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);

    /* Case of independent mode or multimode (for devices with several ADCs): */
    /* Set multimode state.                                                   */
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
    } else {
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
    }

    /* Check if a regular conversion is ongoing */
    /* Note: On this device, there is no ADC error code fields related to     */
    /*       conversions on group injected only. In case of conversion on     */
    /*       going on group regular, no error code is reset.                  */
    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);

    /* Clear injected group conversion flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);

    /* Enable conversion of injected group.                                   */
    /* If software start has been selected, conversion starts immediately.    */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* If automatic injected conversion is enabled, conversion will start     */
    /* after next regular group conversion.                                   */
    /* Case of multimode enabled (for devices with several ADCs): if ADC is   */
    /* slave, ADC is enabled only (conversion is not started). If ADC is      */
    /* master, ADC is enabled and conversion is started.                      */
    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
      if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
        /* Start ADC conversion on injected group with SW start */
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
      } else {
        /* Start ADC conversion on injected group with external trigger */
        SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
      }
    }
  } else {
    /* Process unlocked */
    __HAL_UNLOCK(hadc);
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop conversion of injected channels. Disable ADC peripheral if
 *         no regular conversion is on going.
 * @note   If ADC must be disabled and if conversion is on going on
 *         regular group, function HAL_ADC_Stop must be used to stop both
 *         injected and regular groups, and disable the ADC.
 * @note   If injected group mode auto-injection is enabled,
 *         function HAL_ADC_Stop must be used.
 * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
 * @param  hadc: ADC handle
 * @retval None
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion and disable ADC peripheral                     */
  /* Conditioned to:                                                          */
  /* - No conversion on the other group (regular group) is intended to        */
  /*   continue (injected and regular groups stop conversion and ADC disable  */
  /*   are common)                                                            */
  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
    /* Stop potential conversion on going, on regular and injected groups */
    /* Disable ADC peripheral */
    tmp_hal_status = ADC_ConversionStop_Disable(hadc);

    /* Check if ADC is effectively disabled */
    if (tmp_hal_status == HAL_OK) {
      /* Set ADC state */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
    }
  } else {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

    tmp_hal_status = HAL_ERROR;
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Wait for injected group conversion to be completed.
 * @param  hadc: ADC handle
 * @param  Timeout: Timeout value in millisecond.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) {
  uint32_t tickstart;

  /* Variables for polling in case of scan mode enabled and polling for each  */
  /* conversion.                                                              */
  __IO uint32_t Conversion_Timeout_CPU_cycles     = 0U;
  uint32_t      Conversion_Timeout_CPU_cycles_max = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Get timeout */
  tickstart = HAL_GetTick();

  /* Polling for end of conversion: differentiation if single/sequence        */
  /* conversion.                                                              */
  /* For injected group, flag JEOC is set only at the end of the sequence,    */
  /* not for each conversion within the sequence.                             */
  /*  - If single conversion for injected group (scan mode disabled or        */
  /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
  /*    conversion completion.                                                */
  /*  - If sequence conversion for injected group (scan mode enabled and      */
  /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
  /*    sequence.                                                             */
  /*    To poll for each conversion, the maximum conversion time is computed  */
  /*    from ADC conversion time (selected sampling time + conversion time of */
  /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
  /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
  /*    As flag JEOC is not set after each conversion, no timeout status can  */
  /*    be set.                                                               */
  if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) {
    /* Wait until End of Conversion flag is raised */
    while (HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) {
      /* Check if timeout is disabled (set to infinite wait) */
      if (Timeout != HAL_MAX_DELAY) {
        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
          /* Update ADC state machine to timeout */
          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);

          /* Process unlocked */
          __HAL_UNLOCK(hadc);

          return HAL_TIMEOUT;
        }
      }
    }
  } else {
    /* Replace polling by wait for maximum conversion time */
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
    /*    and ADC maximum conversion cycles on all channels.                  */
    /*  - Wait for the expected ADC clock cycles delay                        */
    Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc));

    while (Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) {
      /* Check if timeout is disabled (set to infinite wait) */
      if (Timeout != HAL_MAX_DELAY) {
        if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) {
          /* Update ADC state machine to timeout */
          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);

          /* Process unlocked */
          __HAL_UNLOCK(hadc);

          return HAL_TIMEOUT;
        }
      }
      Conversion_Timeout_CPU_cycles++;
    }
  }

  /* Clear injected group conversion flag */
  /* Note: On STM32F1 ADC, clear regular conversion flag raised               */
  /* simultaneously.                                                          */
  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);

  /* Update ADC state machine */
  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);

  /* Determine whether any further conversion upcoming on group injected      */
  /* by external trigger or by automatic injected conversion                  */
  /* from group regular.                                                      */
  if (ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE)))) {
    /* Set ADC state */
    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);

    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
    }
  }

  /* Return ADC state */
  return HAL_OK;
}

/**
 * @brief  Enables ADC, starts conversion of injected group with interruption.
 *          - JEOC (end of conversion of injected group)
 *         Each of these interruptions has its dedicated callback function.
 * @param  hadc: ADC handle
 * @retval HAL status.
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Enable the ADC peripheral */
  tmp_hal_status = ADC_Enable(hadc);

  /* Start conversion if ADC is effectively enabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to injected group conversion results    */
    /* - Set state bitfield related to injected operation                     */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);

    /* Case of independent mode or multimode (for devices with several ADCs): */
    /* Set multimode state.                                                   */
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
    } else {
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
    }

    /* Check if a regular conversion is ongoing */
    /* Note: On this device, there is no ADC error code fields related to     */
    /*       conversions on group injected only. In case of conversion on     */
    /*       going on group regular, no error code is reset.                  */
    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);

    /* Clear injected group conversion flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);

    /* Enable end of conversion interrupt for injected channels */
    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);

    /* Start conversion of injected group if software start has been selected */
    /* and if automatic injected conversion is disabled.                      */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* If automatic injected conversion is enabled, conversion will start     */
    /* after next regular group conversion.                                   */
    if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
      if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) {
        /* Start ADC conversion on injected group with SW start */
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
      } else {
        /* Start ADC conversion on injected group with external trigger */
        SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
      }
    }
  } else {
    /* Process unlocked */
    __HAL_UNLOCK(hadc);
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop conversion of injected channels, disable interruption of
 *         end-of-conversion. Disable ADC peripheral if no regular conversion
 *         is on going.
 * @note   If ADC must be disabled and if conversion is on going on
 *         regular group, function HAL_ADC_Stop must be used to stop both
 *         injected and regular groups, and disable the ADC.
 * @note   If injected group mode auto-injection is enabled,
 *         function HAL_ADC_Stop must be used.
 * @param  hadc: ADC handle
 * @retval None
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion and disable ADC peripheral                     */
  /* Conditioned to:                                                          */
  /* - No conversion on the other group (regular group) is intended to        */
  /*   continue (injected and regular groups stop conversion and ADC disable  */
  /*   are common)                                                            */
  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
  if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) {
    /* Stop potential conversion on going, on regular and injected groups */
    /* Disable ADC peripheral */
    tmp_hal_status = ADC_ConversionStop_Disable(hadc);

    /* Check if ADC is effectively disabled */
    if (tmp_hal_status == HAL_OK) {
      /* Disable ADC end of conversion interrupt for injected channels */
      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);

      /* Set ADC state */
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
    }
  } else {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

    tmp_hal_status = HAL_ERROR;
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief  Enables ADC, starts conversion of regular group and transfers result
 *         through DMA.
 *         Multimode must have been previously configured using
 *         HAL_ADCEx_MultiModeConfigChannel() function.
 *         Interruptions enabled in this function:
 *          - DMA transfer complete
 *          - DMA half transfer
 *         Each of these interruptions has its dedicated callback function.
 * @note:  On STM32F1 devices, ADC slave regular group must be configured
 *         with conversion trigger ADC_SOFTWARE_START.
 * @note:  ADC slave can be enabled preliminarily using single-mode
 *         HAL_ADC_Start() function.
 * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
 * @param  pData: The destination Buffer address.
 * @param  Length: The length of data to be transferred from ADC peripheral to memory.
 * @retval None
 */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  ADC_HandleTypeDef tmphadcSlave;

  /* Check the parameters */
  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Set a temporary handle of the ADC slave associated to the ADC master     */
  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);

  /* On STM32F1 devices, ADC slave regular group must be configured with      */
  /* conversion trigger ADC_SOFTWARE_START.                                   */
  /* Note: External trigger of ADC slave must be enabled, it is already done  */
  /*       into function "HAL_ADC_Init()".                                    */
  if (!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

    /* Process unlocked */
    __HAL_UNLOCK(hadc);

    return HAL_ERROR;
  }

  /* Enable the ADC peripherals: master and slave (in case if not already     */
  /* enabled previously)                                                      */
  tmp_hal_status = ADC_Enable(hadc);
  if (tmp_hal_status == HAL_OK) {
    tmp_hal_status = ADC_Enable(&tmphadcSlave);
  }

  /* Start conversion if all ADCs of multimode are effectively enabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set ADC state (ADC master)                                             */
    /* - Clear state bitfield related to regular group conversion results     */
    /* - Set state bitfield related to regular operation                      */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY);

    /* If conversions on group regular are also triggering group injected,    */
    /* update ADC state.                                                      */
    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) {
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);

    /* Set ADC error code to none */
    ADC_CLEAR_ERRORCODE(hadc);

    /* Set the DMA transfer complete callback */
    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;

    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
    /* start (in case of SW start):                                           */

    /* Clear regular group conversion flag and overrun flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);

    /* Enable ADC DMA mode of ADC master */
    SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);

    /* Start the DMA channel */
    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);

    /* Start conversion of regular group if software start has been selected. */
    /* If external trigger has been selected, conversion will start at next   */
    /* trigger event.                                                         */
    /* Note: Alternate trigger for single conversion could be to force an     */
    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
    if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) {
      /* Start ADC conversion on regular group with SW start */
      SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
    } else {
      /* Start ADC conversion on regular group with external trigger */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
    }
  } else {
    /* Process unlocked */
    __HAL_UNLOCK(hadc);
  }

  /* Return function status */
  return tmp_hal_status;
}

/**
 * @brief  Stop ADC conversion of regular group (and injected channels in
 *         case of auto_injection mode), disable ADC DMA transfer, disable
 *         ADC peripheral.
 * @note   Multimode is kept enabled after this function. To disable multimode
 *         (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
 *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
 * @note   In case of DMA configured in circular mode, function
 *         HAL_ADC_Stop_DMA must be called after this function with handle of
 *         ADC slave, to properly disable the DMA channel.
 * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
 * @retval None
 */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  ADC_HandleTypeDef tmphadcSlave;

  /* Check the parameters */
  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC master peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);

  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK) {
    /* Set a temporary handle of the ADC slave associated to the ADC master   */
    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);

    /* Disable ADC slave peripheral */
    tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);

    /* Check if ADC is effectively disabled */
    if (tmp_hal_status != HAL_OK) {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);

      /* Process unlocked */
      __HAL_UNLOCK(hadc);

      return HAL_ERROR;
    }

    /* Disable ADC DMA mode */
    CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);

    /* Reset configuration of ADC DMA continuous request for dual mode */
    CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);

    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
    /* while DMA transfer is on going)                                        */
    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);

    /* Change ADC state (ADC master) */
    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @brief  Get ADC injected group conversion result.
 * @note   Reading register JDRx automatically clears ADC flag JEOC
 *         (ADC group injected end of unitary conversion).
 * @note   This function does not clear ADC flag JEOS
 *         (ADC group injected end of sequence conversion)
 *         Occurrence of flag JEOS rising:
 *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
 *            to flag JEOC.
 *          - If sequencer is composed of several ranks, during the scan
 *            sequence flag JEOC only is raised, at the end of the scan sequence
 *            both flags JEOC and EOS are raised.
 *         Flag JEOS must not be cleared by this function because
 *         it would not be compliant with low power features
 *         (feature low power auto-wait, not available on all STM32 families).
 *         To clear this flag, either use function:
 *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
 *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
 *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
 * @param  hadc: ADC handle
 * @param  InjectedRank: the converted ADC injected rank.
 *          This parameter can be one of the following values:
 *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
 *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
 *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
 *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
 * @retval ADC group injected conversion data
 */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) {
  uint32_t tmp_jdr = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));

  /* Get ADC converted value */
  switch (InjectedRank) {
  case ADC_INJECTED_RANK_4:
    tmp_jdr = hadc->Instance->JDR4;
    break;
  case ADC_INJECTED_RANK_3:
    tmp_jdr = hadc->Instance->JDR3;
    break;
  case ADC_INJECTED_RANK_2:
    tmp_jdr = hadc->Instance->JDR2;
    break;
  case ADC_INJECTED_RANK_1:
  default:
    tmp_jdr = hadc->Instance->JDR1;
    break;
  }

  /* Return ADC converted value */
  return tmp_jdr;
}

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief  Returns the last ADC Master&Slave regular conversions results data
 *         in the selected multi mode.
 * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
 * @retval The converted data value.
 */
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) {
  uint32_t tmpDR = 0U;

  /* Check the parameters */
  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Note: EOC flag is not cleared here by software because automatically     */
  /*       cleared by hardware when reading register DR.                      */

  /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions      */
  /* only if ADC1 DMA mode is enabled.                                        */
  tmpDR = hadc->Instance->DR;

  if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) {
    tmpDR |= (ADC2->DR << 16U);
  }

  /* Return ADC converted value */
  return tmpDR;
}
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */

/**
 * @brief  Injected conversion complete callback in non blocking mode
 * @param  hadc: ADC handle
 * @retval None
 */
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
  */
}

/**
 * @}
 */

/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
  * @brief    Extended Peripheral Control functions
  *
@verbatim
 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode

@endverbatim
  * @{
  */

/**
 * @brief  Configures the ADC injected group and the selected channel to be
 *         linked to the injected group.
 * @note   Possibility to update parameters on the fly:
 *         This function initializes injected group, following calls to this
 *         function can be used to reconfigure some parameters of structure
 *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
 *         The setting of these parameters is conditioned to ADC state:
 *         this function must be called when ADC is not under conversion.
 * @param  hadc: ADC handle
 * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
 *         injected group.
 * @retval None
 */
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
  assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
  assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));

  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) {
    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
  }

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Configuration of injected group sequencer:                               */
  /* - if scan mode is disabled, injected channels sequence length is set to  */
  /*   0x00: 1 channel converted (channel on regular rank 1)                  */
  /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
  /*   Note: Scan mode is present by hardware on this device and, if          */
  /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
  /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
  /* - if scan mode is enabled, injected channels sequence length is set to   */
  /*   parameter "InjectedNbrOfConversion".                                   */
  //  if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
  //  {
  //    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
  //    {
  //      /* Clear the old SQx bits for all injected ranks */
  //      MODIFY_REG(hadc->Instance->JSQR                             ,
  //                 ADC_JSQR_JL   |
  //                 ADC_JSQR_JSQ4 |
  //                 ADC_JSQR_JSQ3 |
  //                 ADC_JSQR_JSQ2 |
  //                 ADC_JSQR_JSQ1                                    ,
  //                 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
  //                                  ADC_INJECTED_RANK_1,
  //                                  0x01U));
  //    }
  //    /* If another injected rank than rank1 was intended to be set, and could  */
  //    /* not due to ScanConvMode disabled, error is reported.                   */
  //    else
  //    {
  //      /* Update ADC state machine to error */
  //      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  //
  //      tmp_hal_status = HAL_ERROR;
  //    }
  //  }
  //  else
  {
    /* Since injected channels rank conv. order depends on total number of   */
    /* injected conversions, selected rank must be below or equal to total   */
    /* number of injected conversions to be updated.                         */
    if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) {
      /* Clear the old SQx bits for the selected rank */
      /* Set the SQx bits for the selected rank */
      MODIFY_REG(hadc->Instance->JSQR,

                 ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion),

                 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
                     ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion));
    } else {
      /* Clear the old SQx bits for the selected rank */
      MODIFY_REG(hadc->Instance->JSQR,

                 ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion),

                 0x00000000U);
    }
  }

  /* Configuration of injected group                                          */
  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated only when ADC is disabled:                */
  /*  - external trigger to start conversion                                  */
  /* Parameters update not conditioned to ADC state:                          */
  /*  - Automatic injected conversion                                         */
  /*  - Injected discontinuous mode                                           */
  /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
  /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
  if (ADC_IS_ENABLE(hadc) == RESET) {
    MODIFY_REG(hadc->Instance->CR2, ADC_CR2_JEXTSEL | ADC_CR2_ADON, ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv));
  }

  /* Configuration of injected group                                          */
  /*  - Automatic injected conversion                                         */
  /*  - Injected discontinuous mode                                           */

  /* Automatic injected conversion can be enabled if injected group         */
  /* external triggers are disabled.                                        */
  if (sConfigInjected->AutoInjectedConv == ENABLE) {
    if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) {
      SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
    } else {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

      tmp_hal_status = HAL_ERROR;
    }
  }

  /* Injected discontinuous can be enabled only if auto-injected mode is    */
  /* disabled.                                                              */
  if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) {
    if (sConfigInjected->AutoInjectedConv == DISABLE) {
      SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
    } else {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

      tmp_hal_status = HAL_ERROR;
    }
  }

  /* InjectedChannel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) {
    MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
  } else /* For channels 0 to 9 */
  {
    MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel));
  }

  /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
  switch (sConfigInjected->InjectedRank) {
  case 1:
    /* Set injected channel 1 offset */
    MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset);
    break;
  case 2:
    /* Set injected channel 2 offset */
    MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset);
    break;
  case 3:
    /* Set injected channel 3 offset */
    MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset);
    break;
  case 4:
  default:
    MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset);
    break;
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}

#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief  Enable ADC multimode and configure multimode parameters
 * @note   Possibility to update parameters on the fly:
 *         This function initializes multimode parameters, following
 *         calls to this function can be used to reconfigure some parameters
 *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
 *         the ADCs (both ADCs of the common group).
 *         The setting of these parameters is conditioned to ADC state.
 *         For parameters constraints, see comments of structure
 *         "ADC_MultiModeTypeDef".
 * @note   To change back configuration from multimode to single mode, ADC must
 *         be reset (using function HAL_ADC_Init() ).
 * @param  hadc: ADC handle
 * @param  multimode: Structure of ADC multimode configuration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) {
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  ADC_HandleTypeDef tmphadcSlave;

  /* Check the parameters */
  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
  assert_param(IS_ADC_MODE(multimode->Mode));

  /* Process locked */
  __HAL_LOCK(hadc);

  /* Set a temporary handle of the ADC slave associated to the ADC master     */
  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);

  /* Parameters update conditioned to ADC state:                              */
  /* Parameters that can be updated when ADC is disabled or enabled without   */
  /* conversion on going on regular group:                                    */
  /*  - ADC master and ADC slave DMA configuration                            */
  /* Parameters that can be updated only when ADC is disabled:                */
  /*  - Multimode mode selection                                              */
  /* To optimize code, all multimode settings can be set when both ADCs of    */
  /* the common group are in state: disabled.                                 */
  if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))) {
    MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DUALMOD, multimode->Mode);
  }
  /* If one of the ADC sharing the same common group is enabled, no update    */
  /* could be done on neither of the multimode structure parameters.          */
  else {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);

    tmp_hal_status = HAL_ERROR;
  }

  /* Process unlocked */
  __HAL_UNLOCK(hadc);

  /* Return function status */
  return tmp_hal_status;
}
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_ADC_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_cortex.c
  * @author  MCD Application Team
  * @brief   CORTEX HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the CORTEX:
  *           + Initialization and de-initialization functions
  *           + Peripheral Control functions
  *
  @verbatim
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M3 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programming manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32f1xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2017 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup CORTEX CORTEX
 * @brief CORTEX HAL module driver
 * @{
 */

#ifdef HAL_CORTEX_MODULE_ENABLED

/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
 * @{
 */

/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief    Initialization and Configuration functions
  *
@verbatim
  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

@endverbatim
  * @{
  */

/**
 * @brief  Sets the priority grouping field (preemption priority and subpriority)
 *         using the required unlock sequence.
 * @param  PriorityGroup: The priority grouping bits length.
 *         This parameter can be one of the following values:
 *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 *                                    4 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 *                                    3 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 *                                    2 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 *                                    1 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 *                                    0 bits for subpriority
 * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
 *         The pending IRQ priority will be managed only by the subpriority.
 * @retval None
 */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
}

/**
 * @brief  Sets the priority of an interrupt.
 * @param  IRQn: External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
 * @param  PreemptPriority: The preemption priority for the IRQn channel.
 *         This parameter can be a value between 0 and 15
 *         A lower priority value indicates a higher priority
 * @param  SubPriority: the subpriority level for the IRQ channel.
 *         This parameter can be a value between 0 and 15
 *         A lower priority value indicates a higher priority.
 * @retval None
 */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) {
  uint32_t prioritygroup = 0x00U;

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}

/**
 * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
 * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
 *         function should be called before.
 * @param  IRQn External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval None
 */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
}

/**
 * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
 * @param  IRQn External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval None
 */
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Disable interrupt */
  NVIC_DisableIRQ(IRQn);
}

/**
 * @brief  Initiates a system reset request to reset the MCU.
 * @retval None
 */
void HAL_NVIC_SystemReset(void) {
  /* System Reset */
  NVIC_SystemReset();
}

/**
 * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
 *         Counter is in free running mode to generate periodic interrupts.
 * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
 * @retval status:  - 0  Function succeeded.
 *                  - 1  Function failed.
 */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); }
/**
 * @}
 */

/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
  *  @brief   Cortex control functions
  *
@verbatim
  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.


@endverbatim
  * @{
  */

#if (__MPU_PRESENT == 1U)
/**
 * @brief  Disables the MPU
 * @retval None
 */
void HAL_MPU_Disable(void) {
  /* Make sure outstanding transfers are done */
  __DMB();

  /* Disable fault exceptions */
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;

  /* Disable the MPU and clear the control register*/
  MPU->CTRL = 0U;
}

/**
 * @brief  Enable the MPU.
 * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
 *          NMI, FAULTMASK and privileged access to the default memory
 *          This parameter can be one of the following values:
 *            @arg MPU_HFNMI_PRIVDEF_NONE
 *            @arg MPU_HARDFAULT_NMI
 *            @arg MPU_PRIVILEGED_DEFAULT
 *            @arg MPU_HFNMI_PRIVDEF
 * @retval None
 */
void HAL_MPU_Enable(uint32_t MPU_Control) {
  /* Enable the MPU */
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;

  /* Enable fault exceptions */
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;

  /* Ensure MPU setting take effects */
  __DSB();
  __ISB();
}

/**
 * @brief  Initializes and configures the Region and the memory to be protected.
 * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
 *                the initialization and configuration information.
 * @retval None
 */
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) {
  /* Check the parameters */
  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));

  /* Set the Region number */
  MPU->RNR = MPU_Init->Number;

  if ((MPU_Init->Enable) != RESET) {
    /* Check the parameters */
    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));

    MPU->RBAR = MPU_Init->BaseAddress;
    MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
                ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
                ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
  } else {
    MPU->RBAR = 0x00U;
    MPU->RASR = 0x00U;
  }
}
#endif /* __MPU_PRESENT */

/**
 * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
 */
uint32_t HAL_NVIC_GetPriorityGrouping(void) {
  /* Get the PRIGROUP[10:8] field value */
  return NVIC_GetPriorityGrouping();
}

/**
 * @brief  Gets the priority of an interrupt.
 * @param  IRQn: External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @param   PriorityGroup: the priority grouping bits length.
 *         This parameter can be one of the following values:
 *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 *                                      4 bits for subpriority
 *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 *                                      3 bits for subpriority
 *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 *                                      2 bits for subpriority
 *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 *                                      1 bits for subpriority
 *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 *                                      0 bits for subpriority
 * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
 * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
 * @retval None
 */
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) {
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  /* Get priority for Cortex-M system or device specific interrupts */
  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}

/**
 * @brief  Sets Pending bit of an external interrupt.
 * @param  IRQn External interrupt number
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval None
 */
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Set interrupt pending */
  NVIC_SetPendingIRQ(IRQn);
}

/**
 * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
 *         and returns the pending bit for the specified interrupt).
 * @param  IRQn External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval status: - 0  Interrupt status is not pending.
 *                 - 1  Interrupt status is pending.
 */
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Return 1 if pending else 0 */
  return NVIC_GetPendingIRQ(IRQn);
}

/**
 * @brief  Clears the pending bit of an external interrupt.
 * @param  IRQn External interrupt number.
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval None
 */
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Clear pending interrupt */
  NVIC_ClearPendingIRQ(IRQn);
}

/**
 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
 * @param IRQn External interrupt number
 *         This parameter can be an enumerator of IRQn_Type enumeration
 *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
 * @retval status: - 0  Interrupt status is not pending.
 *                 - 1  Interrupt status is pending.
 */
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) {
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Return 1 if active else 0 */
  return NVIC_GetActive(IRQn);
}

/**
 * @brief  Configures the SysTick clock source.
 * @param  CLKSource: specifies the SysTick clock source.
 *         This parameter can be one of the following values:
 *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
 *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
 * @retval None
 */
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) {
  /* Check the parameters */
  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
  if (CLKSource == SYSTICK_CLKSOURCE_HCLK) {
    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
  } else {
    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
  }
}

/**
 * @brief  This function handles SYSTICK interrupt request.
 * @retval None
 */
void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); }

/**
 * @brief  SYSTICK callback.
 * @retval None
 */
__weak void HAL_SYSTICK_Callback(void) {
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_SYSTICK_Callback could be implemented in the user file
   */
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_dma.c
  * @author  MCD Application Team
  * @brief   DMA HAL module driver.
  *         This file provides firmware functions to manage the following
  *         functionalities of the Direct Memory Access (DMA) peripheral:
  *           + Initialization and de-initialization functions
  *           + IO operation functions
  *           + Peripheral State and errors functions
  @verbatim
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred.
              In this case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e. a member of DMA handle structure).

     *** DMA HAL driver macros list ***
     =============================================
      [..]
       Below the list of most used macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2017 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup DMA DMA
 * @brief DMA HAL module driver
 * @{
 */

#ifdef HAL_DMA_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
 * @{
 */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
 * @}
 */

/* Exported functions ---------------------------------------------------------*/

/** @defgroup DMA_Exported_Functions DMA Exported Functions
 * @{
 */

/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief   Initialization and de-initialization functions
  *
@verbatim
 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

@endverbatim
  * @{
  */

/**
 * @brief  Initialize the DMA according to the specified
 *         parameters in the DMA_InitTypeDef and initialize the associated handle.
 * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) {
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if (hdma == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
    /* DMA1 */
    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
    hdma->DmaBaseAddress = DMA1;
  } else {
    /* DMA2 */
    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
    hdma->DmaBaseAddress = DMA2;
  }
#else
  /* DMA1 */
  hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  hdma->DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */

  /* Change DMA peripheral state */
  hdma->State = HAL_DMA_STATE_BUSY;

  /* Get the CR register value */
  tmp = hdma->Instance->CCR;

  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
  tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority;

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;

  return HAL_OK;
}

/**
 * @brief  DeInitialize the DMA peripheral.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) {
  /* Check the DMA handle allocation */
  if (hdma == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));

  /* Disable the selected DMA Channelx */
  __HAL_DMA_DISABLE(hdma);

  /* Reset DMA Channel control register */
  hdma->Instance->CCR = 0U;

  /* Reset DMA Channel Number of Data to Transfer register */
  hdma->Instance->CNDTR = 0U;

  /* Reset DMA Channel peripheral address register */
  hdma->Instance->CPAR = 0U;

  /* Reset DMA Channel memory address register */
  hdma->Instance->CMAR = 0U;

#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F100xE) || defined(STM32F105xC) || defined(STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) {
    /* DMA1 */
    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
    hdma->DmaBaseAddress = DMA1;
  } else {
    /* DMA2 */
    hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
    hdma->DmaBaseAddress = DMA2;
  }
#else
  /* DMA1 */
  hdma->ChannelIndex   = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  hdma->DmaBaseAddress = DMA1;
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */

  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));

  /* Clean all callbacks */
  hdma->XferCpltCallback     = NULL;
  hdma->XferHalfCpltCallback = NULL;
  hdma->XferErrorCallback    = NULL;
  hdma->XferAbortCallback    = NULL;

  /* Reset the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Reset the DMA state */
  hdma->State = HAL_DMA_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(hdma);

  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
  *  @brief   Input and Output operation functions
  *
@verbatim
 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

@endverbatim
  * @{
  */

/**
 * @brief  Start the DMA Transfer.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @param  SrcAddress: The source memory Buffer address
 * @param  DstAddress: The destination memory Buffer address
 * @param  DataLength: The length of data to be transferred from source to destination
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);

  if (HAL_DMA_STATE_READY == hdma->State) {
    /* Change DMA peripheral state */
    hdma->State     = HAL_DMA_STATE_BUSY;
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);

    /* Configure the source, destination address and the data length & clear flags*/
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);

    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
  } else {
    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
    status = HAL_BUSY;
  }
  return status;
}

/**
 * @brief  Start the DMA Transfer with interrupt enabled.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @param  SrcAddress: The source memory Buffer address
 * @param  DstAddress: The destination memory Buffer address
 * @param  DataLength: The length of data to be transferred from source to destination
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);

  if (HAL_DMA_STATE_READY == hdma->State) {
    /* Change DMA peripheral state */
    hdma->State     = HAL_DMA_STATE_BUSY;
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;

    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);

    /* Configure the source, destination address and the data length & clear flags*/
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);

    /* Enable the transfer complete interrupt */
    /* Enable the transfer Error interrupt */
    if (NULL != hdma->XferHalfCpltCallback) {
      /* Enable the Half transfer complete interrupt as well */
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
    } else {
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
    }
    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
  } else {
    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    /* Remain BUSY */
    status = HAL_BUSY;
  }
  return status;
}

/**
 * @brief  Abort the DMA Transfer.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Disable DMA IT */
  __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));

  /* Disable the channel */
  __HAL_DMA_DISABLE(hdma);

  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);

  /* Change the DMA state */
  hdma->State = HAL_DMA_STATE_READY;

  /* Process Unlocked */
  __HAL_UNLOCK(hdma);

  return status;
}

/**
 * @brief  Aborts the DMA Transfer in Interrupt mode.
 * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
 *                 the configuration information for the specified DMA Channel.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) {
  HAL_StatusTypeDef status = HAL_OK;

  if (HAL_DMA_STATE_BUSY != hdma->State) {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;

    status = HAL_ERROR;
  } else {
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);

    /* Clear all flags */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    /* Call User Abort callback */
    if (hdma->XferAbortCallback != NULL) {
      hdma->XferAbortCallback(hdma);
    }
  }
  return status;
}

/**
 * @brief  Polling for transfer complete.
 * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
 *                  the configuration information for the specified DMA Channel.
 * @param  CompleteLevel: Specifies the DMA level complete.
 * @param  Timeout:       Timeout duration.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) {
  uint32_t temp;
  uint32_t tickstart = 0U;

  if (HAL_DMA_STATE_BUSY != hdma->State) {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
    __HAL_UNLOCK(hdma);
    return HAL_ERROR;
  }

  /* Polling mode not supported in circular mode */
  if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) {
    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
    return HAL_ERROR;
  }

  /* Get the level transfer complete flag */
  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
    /* Transfer Complete flag */
    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
  } else {
    /* Half Transfer Complete flag */
    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
  }

  /* Get tick */
  tickstart = HAL_GetTick();

  while (__HAL_DMA_GET_FLAG(hdma, temp) == RESET) {
    if ((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) {
      /* When a DMA transfer error occurs */
      /* A hardware clear of its EN bits is performed */
      /* Clear all flags */
      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);

      /* Update error code */
      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hdma);

      return HAL_ERROR;
    }
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
        /* Update error code */
        SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);

        /* Change the DMA state */
        hdma->State = HAL_DMA_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hdma);

        return HAL_ERROR;
      }
    }
  }

  if (CompleteLevel == HAL_DMA_FULL_TRANSFER) {
    /* Clear the transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));

    /* The selected Channelx EN bit is cleared (DMA is disabled and
    all transfers are complete) */
    hdma->State = HAL_DMA_STATE_READY;
  } else {
    /* Clear the half transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
  }

  /* Process unlocked */
  __HAL_UNLOCK(hdma);

  return HAL_OK;
}

/**
 * @brief  Handles DMA interrupt request.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @retval None
 */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) {
  uint32_t flag_it   = hdma->DmaBaseAddress->ISR;
  uint32_t source_it = hdma->Instance->CCR;

  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) {

    /* Clear the half transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));

  }

  /* Transfer Complete Interrupt management ***********************************/
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) {
    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) {
      /* Disable the transfer complete and error interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
    }
    /* Clear the transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    if (hdma->XferCpltCallback != NULL) {
      /* Transfer complete callback */
      hdma->XferCpltCallback(hdma);
    }
  }

  /* Transfer Error Interrupt management **************************************/
  else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) {
    /* When a DMA transfer error occurs */
    /* A hardware clear of its EN bits is performed */
    /* Disable ALL DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);

    /* Update error code */
    hdma->ErrorCode = HAL_DMA_ERROR_TE;

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    if (hdma->XferErrorCallback != NULL) {
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
    }
  }
  return;
}

/**
 * @brief Register callbacks
 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
 *              the configuration information for the specified DMA Channel.
 * @param CallbackID: User Callback identifer
 *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 * @param pCallback: pointer to private callbacsk function which has pointer to
 *                   a DMA_HandleTypeDef structure as parameter.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (*pCallback)(DMA_HandleTypeDef *_hdma)) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Process locked */
  __HAL_LOCK(hdma);

  if (HAL_DMA_STATE_READY == hdma->State) {
    switch (CallbackID) {
    case HAL_DMA_XFER_CPLT_CB_ID:
      hdma->XferCpltCallback = pCallback;
      break;

    case HAL_DMA_XFER_HALFCPLT_CB_ID:
      hdma->XferHalfCpltCallback = pCallback;
      break;

    case HAL_DMA_XFER_ERROR_CB_ID:
      hdma->XferErrorCallback = pCallback;
      break;

    case HAL_DMA_XFER_ABORT_CB_ID:
      hdma->XferAbortCallback = pCallback;
      break;

    default:
      status = HAL_ERROR;
      break;
    }
  } else {
    status = HAL_ERROR;
  }

  /* Release Lock */
  __HAL_UNLOCK(hdma);

  return status;
}

/**
 * @brief UnRegister callbacks
 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
 *              the configuration information for the specified DMA Channel.
 * @param CallbackID: User Callback identifer
 *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Process locked */
  __HAL_LOCK(hdma);

  if (HAL_DMA_STATE_READY == hdma->State) {
    switch (CallbackID) {
    case HAL_DMA_XFER_CPLT_CB_ID:
      hdma->XferCpltCallback = NULL;
      break;

    case HAL_DMA_XFER_HALFCPLT_CB_ID:
      hdma->XferHalfCpltCallback = NULL;
      break;

    case HAL_DMA_XFER_ERROR_CB_ID:
      hdma->XferErrorCallback = NULL;
      break;

    case HAL_DMA_XFER_ABORT_CB_ID:
      hdma->XferAbortCallback = NULL;
      break;

    case HAL_DMA_XFER_ALL_CB_ID:
      hdma->XferCpltCallback     = NULL;
      hdma->XferHalfCpltCallback = NULL;
      hdma->XferErrorCallback    = NULL;
      hdma->XferAbortCallback    = NULL;
      break;

    default:
      status = HAL_ERROR;
      break;
    }
  } else {
    status = HAL_ERROR;
  }

  /* Release Lock */
  __HAL_UNLOCK(hdma);

  return status;
}

/**
 * @}
 */

/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
  *  @brief    Peripheral State and Errors functions
  *
@verbatim
 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

@endverbatim
  * @{
  */

/**
 * @brief  Return the DMA hande state.
 * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
 *               the configuration information for the specified DMA Channel.
 * @retval HAL state
 */
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) {
  /* Return DMA handle state */
  return hdma->State;
}

/**
 * @brief  Return the DMA error code.
 * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
 *              the configuration information for the specified DMA Channel.
 * @retval DMA Error Code
 */
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; }

/**
 * @}
 */

/**
 * @}
 */

/** @addtogroup DMA_Private_Functions
 * @{
 */

/**
 * @brief  Sets the DMA Transfer parameter.
 * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
 *                     the configuration information for the specified DMA Channel.
 * @param  SrcAddress: The source memory Buffer address
 * @param  DstAddress: The destination memory Buffer address
 * @param  DataLength: The length of data to be transferred from source to destination
 * @retval HAL status
 */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) {
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;

  /* Memory to Peripheral */
  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;

    /* Configure DMA Channel source address */
    hdma->Instance->CMAR = SrcAddress;
  }
  /* Peripheral to Memory */
  else {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
  }
}

/**
 * @}
 */

#endif /* HAL_DMA_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_flash.c
  * @author  MCD Application Team
  * @brief   FLASH HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the internal FLASH memory:
  *           + Program operations functions
  *           + Memory Control functions
  *           + Peripheral State functions
  *
  @verbatim
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================
  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
      prefetch.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Prefetch on I-Code
      (+) Option Bytes programming


                     ##### How to use this driver #####
  ==============================================================================
  [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32F1xx devices.

      (#) FLASH Memory I/O Programming functions: this group includes all needed
          functions to erase and program the main memory:
        (++) Lock and Unlock the FLASH interface
        (++) Erase function: Erase page, erase all pages
        (++) Program functions: half word, word and doubleword
      (#) FLASH Option Bytes Programming functions: this group includes all needed
          functions to manage the Option Bytes:
        (++) Lock and Unlock the Option Bytes
        (++) Set/Reset the write protection
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Launch the Option Bytes loader
        (++) Erase Option Bytes
        (++) Program the data Option Bytes
        (++) Get the Write protection.
        (++) Get the user option bytes.

      (#) Interrupts and flags management functions : this group
          includes all needed functions to:
        (++) Handle FLASH interrupts
        (++) Wait for last FLASH operation according to its status
        (++) Get error flag status

  [..] In addition to these function, this driver includes a set of macros allowing
       to handle the following operations:

      (+) Set/Get the latency
      (+) Enable/Disable the prefetch buffer
      (+) Enable/Disable the half cycle access
      (+) Enable/Disable the FLASH interrupts
      (+) Monitor the FLASH flags status

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

#ifdef HAL_FLASH_MODULE_ENABLED

/** @defgroup FLASH FLASH
 * @brief FLASH HAL module driver
 * @{
 */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
 * @{
 */
/**
 * @}
 */

/* Private macro ---------------------------- ---------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
 * @{
 */

/**
 * @}
 */

/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
 * @{
 */
/* Variables used for Erase pages under interruption*/
FLASH_ProcessTypeDef pFlash;
/**
 * @}
 */

/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
 * @{
 */
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_SetErrorCode(void);
extern void FLASH_PageErase(uint32_t PageAddress);
/**
 * @}
 */

/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
 * @{
 */

/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
  *  @brief   Programming operation functions
  *
@verbatim
@endverbatim
  * @{
  */

/**
 * @brief  Program halfword, word or double word at a specified address
 * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
 *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
 *
 * @note   If an erase and a program operations are requested simultaneously,
 *         the erase operation is performed before the program one.
 *
 * @note   FLASH should be previously erased before new programmation (only exception to this
 *         is when 0x0000 is programmed)
 *
 * @param  TypeProgram:  Indicate the way to program at a specified address.
 *                       This parameter can be a value of @ref FLASH_Type_Program
 * @param  Address:      Specifies the address to be programmed.
 * @param  Data:         Specifies the data to be programmed
 *
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
  HAL_StatusTypeDef status       = HAL_ERROR;
  uint8_t           index        = 0;
  uint8_t           nbiterations = 0;

  /* Process Locked */
  __HAL_LOCK(&pFlash);

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));

#if defined(FLASH_BANK2_END)
  if (Address <= FLASH_BANK1_END) {
#endif /* FLASH_BANK2_END */
    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
#if defined(FLASH_BANK2_END)
  } else {
    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
  }
#endif /* FLASH_BANK2_END */

  if (status == HAL_OK) {
    if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
      /* Program halfword (16-bit) at a specified address. */
      nbiterations = 1U;
    } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
      /* Program word (32-bit = 2*16-bit) at a specified address. */
      nbiterations = 2U;
    } else {
      /* Program double word (64-bit = 4*16-bit) at a specified address. */
      nbiterations = 4U;
    }

    for (index = 0U; index < nbiterations; index++) {
      FLASH_Program_HalfWord((Address + (2U * index)), (uint16_t)(Data >> (16U * index)));

#if defined(FLASH_BANK2_END)
      if (Address <= FLASH_BANK1_END) {
#endif /* FLASH_BANK2_END */
        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);

        /* If the program operation is completed, disable the PG Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
#if defined(FLASH_BANK2_END)
      } else {
        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);

        /* If the program operation is completed, disable the PG Bit */
        CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
      }
#endif /* FLASH_BANK2_END */
      /* In case of error, stop programation procedure */
      if (status != HAL_OK) {
        break;
      }
    }
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);

  return status;
}

/**
 * @brief  Program halfword, word or double word at a specified address  with interrupt enabled.
 * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
 *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
 *
 * @note   If an erase and a program operations are requested simultaneously,
 *         the erase operation is performed before the program one.
 *
 * @param  TypeProgram: Indicate the way to program at a specified address.
 *                      This parameter can be a value of @ref FLASH_Type_Program
 * @param  Address:     Specifies the address to be programmed.
 * @param  Data:        Specifies the data to be programmed
 *
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Process Locked */
  __HAL_LOCK(&pFlash);

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));

#if defined(FLASH_BANK2_END)
  /* If procedure already ongoing, reject the next one */
  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
    return HAL_ERROR;
  }

  if (Address <= FLASH_BANK1_END) {
    /* Enable End of FLASH Operation and Error source interrupts */
    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);

  } else {
    /* Enable End of FLASH Operation and Error source interrupts */
    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
  }
#else
  /* Enable End of FLASH Operation and Error source interrupts */
  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#endif /* FLASH_BANK2_END */

  pFlash.Address = Address;
  pFlash.Data    = Data;

  if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) {
    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
    /* Program halfword (16-bit) at a specified address. */
    pFlash.DataRemaining = 1U;
  } else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) {
    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
    /* Program word (32-bit : 2*16-bit) at a specified address. */
    pFlash.DataRemaining = 2U;
  } else {
    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
    /* Program double word (64-bit : 4*16-bit) at a specified address. */
    pFlash.DataRemaining = 4U;
  }

  /* Program halfword (16-bit) at a specified address. */
  FLASH_Program_HalfWord(Address, (uint16_t)Data);

  return status;
}

/**
 * @brief This function handles FLASH interrupt request.
 * @retval None
 */
void HAL_FLASH_IRQHandler(void) {
  uint32_t addresstmp = 0U;

  /* Check FLASH operation error flags */
#if defined(FLASH_BANK2_END)
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
#else
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
  {
    /* Return the faulty address */
    addresstmp = pFlash.Address;
    /* Reset address */
    pFlash.Address = 0xFFFFFFFFU;

    /* Save the Error code */
    FLASH_SetErrorCode();

    /* FLASH error interrupt user callback */
    HAL_FLASH_OperationErrorCallback(addresstmp);

    /* Stop the procedure ongoing */
    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
  }

  /* Check FLASH End of Operation flag  */
#if defined(FLASH_BANK2_END)
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
#else
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
#endif /* FLASH_BANK2_END */

    /* Process can continue only if no error detected */
    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
        /* Nb of pages to erased can be decreased */
        pFlash.DataRemaining--;

        /* Check if there are still pages to erase */
        if (pFlash.DataRemaining != 0U) {
          addresstmp = pFlash.Address;
          /*Indicate user which sector has been erased */
          HAL_FLASH_EndOfOperationCallback(addresstmp);

          /*Increment sector number*/
          addresstmp     = pFlash.Address + FLASH_PAGE_SIZE;
          pFlash.Address = addresstmp;

          /* If the erase operation is completed, disable the PER Bit */
          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);

          FLASH_PageErase(addresstmp);
        } else {
          /* No more pages to Erase, user callback can be called. */
          /* Reset Sector and stop Erase pages procedure */
          pFlash.Address = addresstmp = 0xFFFFFFFFU;
          pFlash.ProcedureOnGoing     = FLASH_PROC_NONE;
          /* FLASH EOP interrupt user callback */
          HAL_FLASH_EndOfOperationCallback(addresstmp);
        }
      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
        /* Operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);

#if defined(FLASH_BANK2_END)
        /* Stop Mass Erase procedure if no pending mass erase on other bank */
        if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) {
#endif /* FLASH_BANK2_END */
          /* MassErase ended. Return the selected bank */
          /* FLASH EOP interrupt user callback */
          HAL_FLASH_EndOfOperationCallback(0U);

          /* Stop Mass Erase procedure*/
          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
        }
#if defined(FLASH_BANK2_END)
      }
#endif /* FLASH_BANK2_END */
      else {
        /* Nb of 16-bit data to program can be decreased */
        pFlash.DataRemaining--;

        /* Check if there are still 16-bit data to program */
        if (pFlash.DataRemaining != 0U) {
          /* Increment address to 16-bit */
          pFlash.Address += 2U;
          addresstmp = pFlash.Address;

          /* Shift to have next 16-bit data */
          pFlash.Data = (pFlash.Data >> 16U);

          /* Operation is completed, disable the PG Bit */
          CLEAR_BIT(FLASH->CR, FLASH_CR_PG);

          /*Program halfword (16-bit) at a specified address.*/
          FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
        } else {
          /* Program ended. Return the selected address */
          /* FLASH EOP interrupt user callback */
          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address);
          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
          } else {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
          }

          /* Reset Address and stop Program procedure */
          pFlash.Address          = 0xFFFFFFFFU;
          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
        }
      }
    }
  }

#if defined(FLASH_BANK2_END)
  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);

    /* Process can continue only if no error detected */
    if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
      if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) {
        /* Nb of pages to erased can be decreased */
        pFlash.DataRemaining--;

        /* Check if there are still pages to erase*/
        if (pFlash.DataRemaining != 0U) {
          /* Indicate user which page address has been erased*/
          HAL_FLASH_EndOfOperationCallback(pFlash.Address);

          /* Increment page address to next page */
          pFlash.Address += FLASH_PAGE_SIZE;
          addresstmp = pFlash.Address;

          /* Operation is completed, disable the PER Bit */
          CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);

          FLASH_PageErase(addresstmp);
        } else {
          /*No more pages to Erase*/

          /*Reset Address and stop Erase pages procedure*/
          pFlash.Address          = 0xFFFFFFFFU;
          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;

          /* FLASH EOP interrupt user callback */
          HAL_FLASH_EndOfOperationCallback(pFlash.Address);
        }
      } else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) {
        /* Operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);

        if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) {
          /* MassErase ended. Return the selected bank*/
          /* FLASH EOP interrupt user callback */
          HAL_FLASH_EndOfOperationCallback(0U);

          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
        }
      } else {
        /* Nb of 16-bit data to program can be decreased */
        pFlash.DataRemaining--;

        /* Check if there are still 16-bit data to program */
        if (pFlash.DataRemaining != 0U) {
          /* Increment address to 16-bit */
          pFlash.Address += 2U;
          addresstmp = pFlash.Address;

          /* Shift to have next 16-bit data */
          pFlash.Data = (pFlash.Data >> 16U);

          /* Operation is completed, disable the PG Bit */
          CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);

          /*Program halfword (16-bit) at a specified address.*/
          FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
        } else {
          /*Program ended. Return the selected address*/
          /* FLASH EOP interrupt user callback */
          if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address);
          } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
          } else {
            HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
          }

          /* Reset Address and stop Program procedure*/
          pFlash.Address          = 0xFFFFFFFFU;
          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
        }
      }
    }
  }
#endif

  if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) {
#if defined(FLASH_BANK2_END)
    /* Operation is completed, disable the PG, PER and MER Bits for both bank */
    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
    CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));

    /* Disable End of FLASH Operation and Error source interrupts for both banks */
    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
#else
    /* Operation is completed, disable the PG, PER and MER Bits */
    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));

    /* Disable End of FLASH Operation and Error source interrupts */
    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
#endif /* FLASH_BANK2_END */

    /* Process Unlocked */
    __HAL_UNLOCK(&pFlash);
  }
}

/**
 * @brief  FLASH end of operation interrupt callback
 * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
 *                 - Mass Erase: No return value expected
 *                 - Pages Erase: Address of the page which has been erased
 *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
 *                 - Program: Address which was selected for data program
 * @retval none
 */
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(ReturnValue);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
   */
}

/**
 * @brief  FLASH operation error interrupt callback
 * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
 *                 - Mass Erase: No return value expected
 *                 - Pages Erase: Address of the page which returned an error
 *                 - Program: Address which was selected for data program
 * @retval none
 */
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(ReturnValue);

  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
   */
}

/**
 * @}
 */

/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
 *  @brief   management functions
 *
@verbatim
 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

@endverbatim
  * @{
  */

/**
 * @brief  Unlock the FLASH control register access
 * @retval HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_Unlock(void) {
  HAL_StatusTypeDef status = HAL_OK;

  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
    /* Authorize the FLASH Registers access */
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);

    /* Verify Flash is unlocked */
    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) {
      status = HAL_ERROR;
    }
  }
#if defined(FLASH_BANK2_END)
  if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
    /* Authorize the FLASH BANK2 Registers access */
    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);

    /* Verify Flash BANK2 is unlocked */
    if (READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) {
      status = HAL_ERROR;
    }
  }
#endif /* FLASH_BANK2_END */

  return status;
}

/**
 * @brief  Locks the FLASH control register access
 * @retval HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_Lock(void) {
  /* Set the LOCK Bit to lock the FLASH Registers access */
  SET_BIT(FLASH->CR, FLASH_CR_LOCK);

#if defined(FLASH_BANK2_END)
  /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
  SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);

#endif /* FLASH_BANK2_END */
  return HAL_OK;
}

/**
 * @brief  Unlock the FLASH Option Control Registers access.
 * @retval HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) {
  if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) {
    /* Authorizes the Option Byte register programming */
    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
  } else {
    return HAL_ERROR;
  }

  return HAL_OK;
}

/**
 * @brief  Lock the FLASH Option Control Registers access.
 * @retval HAL Status
 */
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) {
  /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
  CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);

  return HAL_OK;
}

/**
 * @brief  Launch the option byte loading.
 * @note   This function will reset automatically the MCU.
 * @retval None
 */
void HAL_FLASH_OB_Launch(void) {
  /* Initiates a system reset request to launch the option byte loading */
  HAL_NVIC_SystemReset();
}

/**
 * @}
 */

/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
 *  @brief    Peripheral errors functions
 *
@verbatim
 ===============================================================================
                      ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time errors of  the FLASH peripheral.

@endverbatim
  * @{
  */

/**
 * @brief  Get the specific FLASH error flag.
 * @retval FLASH_ErrorCode The returned value can be:
 *            @ref FLASH_Error_Codes
 */
uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; }

/**
 * @}
 */

/**
 * @}
 */

/** @addtogroup FLASH_Private_Functions
 * @{
 */

/**
 * @brief  Program a half-word (16-bit) at a specified address.
 * @param  Address specify the address to be programmed.
 * @param  Data    specify the data to be programmed.
 * @retval None
 */
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) {
  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

#if defined(FLASH_BANK2_END)
  if (Address <= FLASH_BANK1_END) {
#endif /* FLASH_BANK2_END */
    /* Proceed to program the new data */
    SET_BIT(FLASH->CR, FLASH_CR_PG);
#if defined(FLASH_BANK2_END)
  } else {
    /* Proceed to program the new data */
    SET_BIT(FLASH->CR2, FLASH_CR2_PG);
  }
#endif /* FLASH_BANK2_END */

  /* Write data in the address */
  *(__IO uint16_t *)Address = Data;
}

/**
 * @brief  Wait for a FLASH operation to complete.
 * @param  Timeout  maximum flash operation timeout
 * @retval HAL Status
 */
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) {
  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
     Even if the FLASH operation fails, the BUSY flag will be reset and an error
     flag will be set */

  uint32_t tickstart = HAL_GetTick();

  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
        return HAL_TIMEOUT;
      }
    }
  }

  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
  }

  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) {
    /*Save the error code*/
    FLASH_SetErrorCode();
    return HAL_ERROR;
  }

  /* There is no error flag set */
  return HAL_OK;
}

#if defined(FLASH_BANK2_END)
/**
 * @brief  Wait for a FLASH BANK2 operation to complete.
 * @param  Timeout maximum flash operation timeout
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) {
  /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
     Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
     flag will be set */

  uint32_t tickstart = HAL_GetTick();

  while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2)) {
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
        return HAL_TIMEOUT;
      }
    }
  }

  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
  }

  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) {
    /*Save the error code*/
    FLASH_SetErrorCode();
    return HAL_ERROR;
  }

  /* If there is an error flag set */
  return HAL_OK;
}
#endif /* FLASH_BANK2_END */

/**
 * @brief  Set the specific FLASH error flag.
 * @retval None
 */
static void FLASH_SetErrorCode(void) {
  uint32_t flags = 0U;

#if defined(FLASH_BANK2_END)
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
    flags |= FLASH_FLAG_WRPERR;
#endif /* FLASH_BANK2_END */
  }
#if defined(FLASH_BANK2_END)
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
    flags |= FLASH_FLAG_PGERR;
#endif /* FLASH_BANK2_END */
  }
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
  }

  /* Clear FLASH error pending bits */
  __HAL_FLASH_CLEAR_FLAG(flags);
}
/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_FLASH_MODULE_ENABLED */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_flash_ex.c
  * @author  MCD Application Team
  * @brief   Extended FLASH HAL module driver.
  *
  *          This file provides firmware functions to manage the following
  *          functionalities of the FLASH peripheral:
  *           + Extended Initialization/de-initialization functions
  *           + Extended I/O operation functions
  *           + Extended Peripheral Control functions
  *
  @verbatim
  ==============================================================================
               ##### Flash peripheral extended features  #####
  ==============================================================================

                      ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32F1xxx devices. It includes

        (++) Set/Reset the write protection
        (++) Program the user Option Bytes
        (++) Get the Read protection Level

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */
#ifdef HAL_FLASH_MODULE_ENABLED

/** @addtogroup FLASH
 * @{
 */
/** @addtogroup FLASH_Private_Variables
 * @{
 */
/* Variables used for Erase pages under interruption*/
extern FLASH_ProcessTypeDef pFlash;
/**
 * @}
 */

/**
 * @}
 */

/** @defgroup FLASHEx FLASHEx
 * @brief FLASH HAL Extension module driver
 * @{
 */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
 * @{
 */
#define FLASH_POSITION_IWDGSW_BIT       FLASH_OBR_IWDG_SW_Pos
#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
 * @{
 */
/**
 * @}
 */

/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
 * @{
 */
/* Erase operations */
static void FLASH_MassErase(uint32_t Banks);
void        FLASH_PageErase(uint32_t PageAddress);

/* Option bytes control */
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
static uint32_t          FLASH_OB_GetWRP(void);
static uint32_t          FLASH_OB_GetRDP(void);
static uint8_t           FLASH_OB_GetUser(void);

/**
 * @}
 */

/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
 * @{
 */

/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
 *  @brief   FLASH Memory Erasing functions
  *
@verbatim
  ==============================================================================
                ##### FLASH Erasing Programming functions #####
  ==============================================================================

    [..] The FLASH Memory Erasing functions, includes the following functions:
    (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
        is called with parameter 0xFFFFFFFF

    [..] Any operation of erase should follow these steps:
    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
        program memory access.
    (#) Call the desired function to erase page.
    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
       (recommended to protect the FLASH memory against possible unwanted operation).

@endverbatim
  * @{
  */

/**
 * @brief  Perform a mass erase or erase the specified FLASH memory pages
 * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
 *         must be called before.
 *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
 *         (recommended to protect the FLASH memory against possible unwanted operation)
 * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
 *         contains the configuration information for the erasing.
 *
 * @param[out]  PageError pointer to variable  that
 *         contains the configuration information on faulty page in case of error
 *         (0xFFFFFFFF means that all the pages have been correctly erased)
 *
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) {
  HAL_StatusTypeDef status  = HAL_ERROR;
  uint32_t          address = 0U;

  /* Process Locked */
  __HAL_LOCK(&pFlash);

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));

  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
#if defined(FLASH_BANK2_END)
    if (pEraseInit->Banks == FLASH_BANK_BOTH) {
      /* Mass Erase requested for Bank1 and Bank2 */
      /* Wait for last operation to be completed */
      if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) {
        /*Mass erase to be done*/
        FLASH_MassErase(FLASH_BANK_BOTH);

        /* Wait for last operation to be completed */
        if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)) {
          status = HAL_OK;
        }

        /* If the erase operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
        CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
      }
    } else if (pEraseInit->Banks == FLASH_BANK_2) {
      /* Mass Erase requested for Bank2 */
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
        /*Mass erase to be done*/
        FLASH_MassErase(FLASH_BANK_2);

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);

        /* If the erase operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
      }
    } else
#endif /* FLASH_BANK2_END */
    {
      /* Mass Erase requested for Bank1 */
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
        /*Mass erase to be done*/
        FLASH_MassErase(FLASH_BANK_1);

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

        /* If the erase operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
      }
    }
  } else {
    /* Page Erase is requested */
    /* Check the parameters */
    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
    assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));

#if defined(FLASH_BANK2_END)
    /* Page Erase requested on address located on bank2 */
    if (pEraseInit->PageAddress > FLASH_BANK1_END) {
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
        /*Initialization of PageError variable*/
        *PageError = 0xFFFFFFFFU;

        /* Erase by page by page to be done*/
        for (address = pEraseInit->PageAddress; address < (pEraseInit->PageAddress + (pEraseInit->NbPages) * FLASH_PAGE_SIZE); address += FLASH_PAGE_SIZE) {
          FLASH_PageErase(address);

          /* Wait for last operation to be completed */
          status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);

          /* If the erase operation is completed, disable the PER Bit */
          CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);

          if (status != HAL_OK) {
            /* In case of error, stop erase procedure and return the faulty address */
            *PageError = address;
            break;
          }
        }
      }
    } else
#endif /* FLASH_BANK2_END */
    {
      /* Page Erase requested on address located on bank1 */
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) {
        /*Initialization of PageError variable*/
        *PageError = 0xFFFFFFFFU;

        /* Erase page by page to be done*/
        for (address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) {
          FLASH_PageErase(address);

          /* Wait for last operation to be completed */
          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

          /* If the erase operation is completed, disable the PER Bit */
          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);

          if (status != HAL_OK) {
            /* In case of error, stop erase procedure and return the faulty address */
            *PageError = address;
            break;
          }
        }
      }
    }
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);

  return status;
}

/**
 * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
 * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
 *         must be called before.
 *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
 *         (recommended to protect the FLASH memory against possible unwanted operation)
 * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
 *         contains the configuration information for the erasing.
 *
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Process Locked */
  __HAL_LOCK(&pFlash);

  /* If procedure already ongoing, reject the next one */
  if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));

  /* Enable End of FLASH Operation and Error source interrupts */
  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);

#if defined(FLASH_BANK2_END)
  /* Enable End of FLASH Operation and Error source interrupts */
  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);

#endif
  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) {
    /*Mass erase to be done*/
    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
    FLASH_MassErase(pEraseInit->Banks);
  } else {
    /* Erase by page to be done*/

    /* Check the parameters */
    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
    assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));

    pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
    pFlash.DataRemaining    = pEraseInit->NbPages;
    pFlash.Address          = pEraseInit->PageAddress;

    /*Erase 1st page and wait for IT*/
    FLASH_PageErase(pEraseInit->PageAddress);
  }

  return status;
}

/**
 * @}
 */

/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
 *  @brief   Option Bytes Programming functions
  *
@verbatim
  ==============================================================================
                ##### Option Bytes Programming functions #####
  ==============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    option bytes operations.

@endverbatim
  * @{
  */

/**
 * @brief  Erases the FLASH option bytes.
 * @note   This functions erases all option bytes except the Read protection (RDP).
 *         The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
 *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
 *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
 *         (system reset will occur)
 * @retval HAL status
 */

HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) {
  uint8_t           rdptmp = OB_RDP_LEVEL_0;
  HAL_StatusTypeDef status = HAL_ERROR;

  /* Get the actual read protection Option Byte value */
  rdptmp = FLASH_OB_GetRDP();

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* If the previous operation is completed, proceed to erase the option bytes */
    SET_BIT(FLASH->CR, FLASH_CR_OPTER);
    SET_BIT(FLASH->CR, FLASH_CR_STRT);

    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

    /* If the erase operation is completed, disable the OPTER Bit */
    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);

    if (status == HAL_OK) {
      /* Restore the last read protection Option Byte value */
      status = FLASH_OB_RDP_LevelConfig(rdptmp);
    }
  }

  /* Return the erase status */
  return status;
}

/**
 * @brief  Program option bytes
 * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
 *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
 *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
 *         (system reset will occur)
 *
 * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
 *         contains the configuration information for the programming.
 *
 * @retval HAL_StatusTypeDef HAL Status
 */
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) {
  HAL_StatusTypeDef status = HAL_ERROR;

  /* Process Locked */
  __HAL_LOCK(&pFlash);

  /* Check the parameters */
  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));

  /* Write protection configuration */
  if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) {
    assert_param(IS_WRPSTATE(pOBInit->WRPState));
    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) {
      /* Enable of Write protection on the selected page */
      status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
    } else {
      /* Disable of Write protection on the selected page */
      status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
    }
    if (status != HAL_OK) {
      /* Process Unlocked */
      __HAL_UNLOCK(&pFlash);
      return status;
    }
  }

  /* Read protection configuration */
  if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) {
    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
    if (status != HAL_OK) {
      /* Process Unlocked */
      __HAL_UNLOCK(&pFlash);
      return status;
    }
  }

  /* USER configuration */
  if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) {
    status = FLASH_OB_UserConfig(pOBInit->USERConfig);
    if (status != HAL_OK) {
      /* Process Unlocked */
      __HAL_UNLOCK(&pFlash);
      return status;
    }
  }

  /* DATA configuration*/
  if ((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) {
    status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
    if (status != HAL_OK) {
      /* Process Unlocked */
      __HAL_UNLOCK(&pFlash);
      return status;
    }
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);

  return status;
}

/**
 * @brief  Get the Option byte configuration
 * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
 *         contains the configuration information for the programming.
 *
 * @retval None
 */
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) {
  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;

  /*Get WRP*/
  pOBInit->WRPPage = FLASH_OB_GetWRP();

  /*Get RDP Level*/
  pOBInit->RDPLevel = FLASH_OB_GetRDP();

  /*Get USER*/
  pOBInit->USERConfig = FLASH_OB_GetUser();
}

/**
 * @brief  Get the Option byte user data
 * @param  DATAAdress Address of the option byte DATA
 *          This parameter can be one of the following values:
 *            @arg @ref OB_DATA_ADDRESS_DATA0
 *            @arg @ref OB_DATA_ADDRESS_DATA1
 * @retval Value programmed in USER data
 */
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) {
  uint32_t value = 0;

  if (DATAAdress == OB_DATA_ADDRESS_DATA0) {
    /* Get value programmed in OB USER Data0 */
    value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
  } else {
    /* Get value programmed in OB USER Data1 */
    value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
  }

  return value;
}

/**
 * @}
 */

/**
 * @}
 */

/** @addtogroup FLASHEx_Private_Functions
 * @{
 */

/**
  * @brief  Full erase of FLASH memory Bank
  * @param  Banks Banks to be erased
  *          This parameter can be one of the following values:
  *            @arg @ref FLASH_BANK_1 Bank1 to be erased
  @if STM32F101xG
  *            @arg @ref FLASH_BANK_2 Bank2 to be erased
  *            @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
  @endif
  @if STM32F103xG
  *            @arg @ref FLASH_BANK_2 Bank2 to be erased
  *            @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
  @endif
  *
  * @retval None
  */
static void FLASH_MassErase(uint32_t Banks) {
  /* Check the parameters */
  assert_param(IS_FLASH_BANK(Banks));

  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

#if defined(FLASH_BANK2_END)
  if (Banks == FLASH_BANK_BOTH) {
    /* bank1 & bank2 will be erased*/
    SET_BIT(FLASH->CR, FLASH_CR_MER);
    SET_BIT(FLASH->CR2, FLASH_CR2_MER);
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
    SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
  } else if (Banks == FLASH_BANK_2) {
    /*Only bank2 will be erased*/
    SET_BIT(FLASH->CR2, FLASH_CR2_MER);
    SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
  } else {
#endif /* FLASH_BANK2_END */
#if !defined(FLASH_BANK2_END)
    /* Prevent unused argument(s) compilation warning */
    UNUSED(Banks);
#endif /* FLASH_BANK2_END */
    /* Only bank1 will be erased*/
    SET_BIT(FLASH->CR, FLASH_CR_MER);
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
#if defined(FLASH_BANK2_END)
  }
#endif /* FLASH_BANK2_END */
}

/**
 * @brief  Enable the write protection of the desired pages
 * @note   An option byte erase is done automatically in this function.
 * @note   When the memory read protection level is selected (RDP level = 1),
 *         it is not possible to program or erase the flash page i if
 *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
 *
 * @param  WriteProtectPage specifies the page(s) to be write protected.
 *         The value of this parameter depend on device used within the same series
 * @retval HAL status
 */
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) {
  HAL_StatusTypeDef status    = HAL_OK;
  uint16_t          WRP0_Data = 0xFFFF;
#if defined(FLASH_WRP1_WRP1)
  uint16_t WRP1_Data = 0xFFFF;
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
  uint16_t WRP2_Data = 0xFFFF;
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
  uint16_t WRP3_Data = 0xFFFF;
#endif /* FLASH_WRP3_WRP3 */

  /* Check the parameters */
  assert_param(IS_OB_WRP(WriteProtectPage));

  /* Get current write protected pages and the new pages to be protected ******/
  WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));

#if defined(OB_WRP_PAGES0TO15MASK)
  WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#elif defined(OB_WRP_PAGES0TO31MASK)
  WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#endif /* OB_WRP_PAGES0TO31MASK */

#if defined(OB_WRP_PAGES16TO31MASK)
  WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
  WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */

#if defined(OB_WRP_PAGES64TO95MASK)
  WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
  WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */

#if defined(OB_WRP_PAGES96TO127MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#endif /* OB_WRP_PAGES96TO127MASK */

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* To be able to write again option byte, need to perform a option byte erase */
    status = HAL_FLASHEx_OBErase();
    if (status == HAL_OK) {
      /* Enable write protection */
      SET_BIT(FLASH->CR, FLASH_CR_OPTPG);

#if defined(FLASH_WRP0_WRP0)
      if (WRP0_Data != 0xFFU) {
        OB->WRP0 &= WRP0_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP0_WRP0 */

#if defined(FLASH_WRP1_WRP1)
      if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) {
        OB->WRP1 &= WRP1_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP1_WRP1 */

#if defined(FLASH_WRP2_WRP2)
      if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) {
        OB->WRP2 &= WRP2_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP2_WRP2 */

#if defined(FLASH_WRP3_WRP3)
      if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) {
        OB->WRP3 &= WRP3_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP3_WRP3 */

      /* if the program operation is completed, disable the OPTPG Bit */
      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
    }
  }

  return status;
}

/**
 * @brief  Disable the write protection of the desired pages
 * @note   An option byte erase is done automatically in this function.
 * @note   When the memory read protection level is selected (RDP level = 1),
 *         it is not possible to program or erase the flash page i if
 *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
 *
 * @param  WriteProtectPage specifies the page(s) to be write unprotected.
 *         The value of this parameter depend on device used within the same series
 * @retval HAL status
 */
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) {
  HAL_StatusTypeDef status    = HAL_OK;
  uint16_t          WRP0_Data = 0xFFFF;
#if defined(FLASH_WRP1_WRP1)
  uint16_t WRP1_Data = 0xFFFF;
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
  uint16_t WRP2_Data = 0xFFFF;
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
  uint16_t WRP3_Data = 0xFFFF;
#endif /* FLASH_WRP3_WRP3 */

  /* Check the parameters */
  assert_param(IS_OB_WRP(WriteProtectPage));

  /* Get current write protected pages and the new pages to be unprotected ******/
  WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);

#if defined(OB_WRP_PAGES0TO15MASK)
  WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
#elif defined(OB_WRP_PAGES0TO31MASK)
  WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
#endif /* OB_WRP_PAGES0TO31MASK */

#if defined(OB_WRP_PAGES16TO31MASK)
  WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
  WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */

#if defined(OB_WRP_PAGES64TO95MASK)
  WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
  WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */

#if defined(OB_WRP_PAGES96TO127MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#endif /* OB_WRP_PAGES96TO127MASK */

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* To be able to write again option byte, need to perform a option byte erase */
    status = HAL_FLASHEx_OBErase();
    if (status == HAL_OK) {
      SET_BIT(FLASH->CR, FLASH_CR_OPTPG);

#if defined(FLASH_WRP0_WRP0)
      if (WRP0_Data != 0xFFU) {
        OB->WRP0 |= WRP0_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP0_WRP0 */

#if defined(FLASH_WRP1_WRP1)
      if ((status == HAL_OK) && (WRP1_Data != 0xFFU)) {
        OB->WRP1 |= WRP1_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP1_WRP1 */

#if defined(FLASH_WRP2_WRP2)
      if ((status == HAL_OK) && (WRP2_Data != 0xFFU)) {
        OB->WRP2 |= WRP2_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP2_WRP2 */

#if defined(FLASH_WRP3_WRP3)
      if ((status == HAL_OK) && (WRP3_Data != 0xFFU)) {
        OB->WRP3 |= WRP3_Data;

        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
      }
#endif /* FLASH_WRP3_WRP3 */

      /* if the program operation is completed, disable the OPTPG Bit */
      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
    }
  }
  return status;
}

/**
 * @brief  Set the read protection level.
 * @param  ReadProtectLevel specifies the read protection level.
 *         This parameter can be one of the following values:
 *            @arg @ref OB_RDP_LEVEL_0 No protection
 *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
 * @retval HAL status
 */
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* If the previous operation is completed, proceed to erase the option bytes */
    SET_BIT(FLASH->CR, FLASH_CR_OPTER);
    SET_BIT(FLASH->CR, FLASH_CR_STRT);

    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

    /* If the erase operation is completed, disable the OPTER Bit */
    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);

    if (status == HAL_OK) {
      /* Enable the Option Bytes Programming operation */
      SET_BIT(FLASH->CR, FLASH_CR_OPTPG);

      WRITE_REG(OB->RDP, ReadProtectLevel);

      /* Wait for last operation to be completed */
      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

      /* if the program operation is completed, disable the OPTPG Bit */
      CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
    }
  }

  return status;
}

/**
 * @brief  Program the FLASH User Option Byte.
 * @note   Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
 * @param  UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
 *         FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
 *         And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
 * @retval HAL status
 */
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Check the parameters */
  assert_param(IS_OB_IWDG_SOURCE((UserConfig & OB_IWDG_SW)));
  assert_param(IS_OB_STOP_SOURCE((UserConfig & OB_STOP_NO_RST)));
  assert_param(IS_OB_STDBY_SOURCE((UserConfig & OB_STDBY_NO_RST)));
#if defined(FLASH_BANK2_END)
  assert_param(IS_OB_BOOT1((UserConfig & OB_BOOT1_SET)));
#endif /* FLASH_BANK2_END */

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* Enable the Option Bytes Programming operation */
    SET_BIT(FLASH->CR, FLASH_CR_OPTPG);

#if defined(FLASH_BANK2_END)
    OB->USER = (UserConfig | 0xF0U);
#else
    OB->USER = (UserConfig | 0x88U);
#endif /* FLASH_BANK2_END */

    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

    /* if the program operation is completed, disable the OPTPG Bit */
    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
  }

  return status;
}

/**
 * @brief  Programs a half word at a specified Option Byte Data address.
 * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
 *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
 *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
 *         (system reset will occur)
 *         Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
 * @param  Address specifies the address to be programmed.
 *         This parameter can be 0x1FFFF804 or 0x1FFFF806.
 * @param  Data specifies the data to be programmed.
 * @retval HAL status
 */
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) {
  HAL_StatusTypeDef status = HAL_ERROR;

  /* Check the parameters */
  assert_param(IS_OB_DATA_ADDRESS(Address));

  /* Wait for last operation to be completed */
  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

  if (status == HAL_OK) {
    /* Clean the error context */
    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

    /* Enables the Option Bytes Programming operation */
    SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
    *(__IO uint16_t *)Address = Data;

    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);

    /* If the program operation is completed, disable the OPTPG Bit */
    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
  }
  /* Return the Option Byte Data Program Status */
  return status;
}

/**
 * @brief  Return the FLASH Write Protection Option Bytes value.
 * @retval The FLASH Write Protection Option Bytes value
 */
static uint32_t FLASH_OB_GetWRP(void) {
  /* Return the FLASH write protection Register value */
  return (uint32_t)(READ_REG(FLASH->WRPR));
}

/**
 * @brief  Returns the FLASH Read Protection level.
 * @retval FLASH RDP level
 *         This parameter can be one of the following values:
 *            @arg @ref OB_RDP_LEVEL_0 No protection
 *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
 */
static uint32_t FLASH_OB_GetRDP(void) {
  uint32_t readstatus = OB_RDP_LEVEL_0;
  uint32_t tmp_reg    = 0U;

  /* Read RDP level bits */
  tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);

  if (tmp_reg == FLASH_OBR_RDPRT) {
    readstatus = OB_RDP_LEVEL_1;
  } else {
    readstatus = OB_RDP_LEVEL_0;
  }

  return readstatus;
}

/**
 * @brief  Return the FLASH User Option Byte value.
 * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
 *         FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
 *         And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
 */
static uint8_t FLASH_OB_GetUser(void) {
  /* Return the User Option Byte */
  return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
}

/**
 * @}
 */

/**
 * @}
 */

/** @addtogroup FLASH
 * @{
 */

/** @addtogroup FLASH_Private_Functions
 * @{
 */

/**
 * @brief  Erase the specified FLASH memory page
 * @param  PageAddress FLASH page to erase
 *         The value of this parameter depend on device used within the same series
 *
 * @retval None
 */
void FLASH_PageErase(uint32_t PageAddress) {
  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;

#if defined(FLASH_BANK2_END)
  if (PageAddress > FLASH_BANK1_END) {
    /* Proceed to erase the page */
    SET_BIT(FLASH->CR2, FLASH_CR2_PER);
    WRITE_REG(FLASH->AR2, PageAddress);
    SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
  } else {
#endif /* FLASH_BANK2_END */
    /* Proceed to erase the page */
    SET_BIT(FLASH->CR, FLASH_CR_PER);
    WRITE_REG(FLASH->AR, PageAddress);
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
#if defined(FLASH_BANK2_END)
  }
#endif /* FLASH_BANK2_END */
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_FLASH_MODULE_ENABLED */
/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_gpio.c
  * @author  MCD Application Team
  * @brief   GPIO HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
  *           + Initialization and de-initialization functions
  *           + IO operation functions
  *
  @verbatim
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  in several modes:
  (+) Input mode
  (+) Analog mode
  (+) Output mode
  (+) Alternate function mode
  (+) External interrupt/event lines

  [..]
  During and just after reset, the alternate functions and external interrupt
  lines are not active and the I/O ports are configured in input floating mode.

  [..]
  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
  activated or not.

  [..]
  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
  type and the IO speed can be selected depending on the VDD value.

  [..]
  All ports have external interrupt/event capability. To use external interrupt
  lines, the port must be configured in input mode. All available GPIO pins are
  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  [..]
  The external interrupt/event controller consists of up to 20 edge detectors in connectivity
  line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
  Each input line can be independently configured to select the type (event or interrupt) and
  the corresponding trigger event (rising or falling or both). Each line can also masked
  independently. A pending register maintains the status line of the interrupt requests

                     ##### How to use this driver #####
  ==============================================================================
 [..]
   (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().

   (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
       (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
       (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
            structure.
       (++) In case of Output or alternate function mode selection: the speed is
            configured through "Speed" member from GPIO_InitTypeDef structure
       (++) Analog mode is required when a pin is to be used as ADC channel
            or DAC output.
       (++) In case of external interrupt/event selection the "Mode" member from
            GPIO_InitTypeDef structure select the type (interrupt or event) and
            the corresponding trigger event (rising or falling or both).

   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
       mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
       HAL_NVIC_EnableIRQ().

   (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

   (#) To set/reset the level of a pin configured in output mode use
       HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

   (#) During and just after reset, the alternate functions are not
       active and the GPIO pins are configured in input floating mode (except JTAG
       pins).

   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
       priority over the GPIO function.

   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
       general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
       The HSE has priority over the GPIO function.

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup GPIO GPIO
 * @brief GPIO HAL module driver
 * @{
 */

#ifdef HAL_GPIO_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
 * @{
 */
#define GPIO_MODE        0x00000003U
#define EXTI_MODE        0x10000000U
#define GPIO_MODE_IT     0x00010000U
#define GPIO_MODE_EVT    0x00020000U
#define RISING_EDGE      0x00100000U
#define FALLING_EDGE     0x00200000U
#define GPIO_OUTPUT_TYPE 0x00000010U

#define GPIO_NUMBER 16U

/* Definitions for bit manipulation of CRL and CRH register */
#define GPIO_CR_MODE_INPUT         0x00000000U /*!< 00: Input mode (reset state)  */
#define GPIO_CR_CNF_ANALOG         0x00000000U /*!< 00: Analog mode  */
#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state)  */
#define GPIO_CR_CNF_INPUT_PU_PD    0x00000008U /*!< 10: Input with pull-up / pull-down  */
#define GPIO_CR_CNF_GP_OUTPUT_PP   0x00000000U /*!< 00: General purpose output push-pull  */
#define GPIO_CR_CNF_GP_OUTPUT_OD   0x00000004U /*!< 01: General purpose output Open-drain  */
#define GPIO_CR_CNF_AF_OUTPUT_PP   0x00000008U /*!< 10: Alternate function output Push-pull  */
#define GPIO_CR_CNF_AF_OUTPUT_OD   0x0000000CU /*!< 11: Alternate function output Open-drain  */

/**
 * @}
 */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
 * @{
 */

/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
 *  @brief    Initialization and Configuration functions
 *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

@endverbatim
  * @{
  */

/**
 * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
 *         the configuration information for the specified GPIO peripheral.
 * @retval None
 */
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) {
  uint32_t       position;
  uint32_t       ioposition = 0x00U;
  uint32_t       iocurrent  = 0x00U;
  uint32_t       temp       = 0x00U;
  uint32_t       config     = 0x00U;
  __IO uint32_t *configregister;      /* Store the address of CRL or CRH register based on pin number */
  uint32_t       registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */

  /* Check the parameters */
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++) {
    /* Get the IO position */
    ioposition = (0x01U << position);

    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;

    if (iocurrent == ioposition) {
      /* Check the Alternate function parameters */
      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));

      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
      switch (GPIO_Init->Mode) {
      /* If we are configuring the pin in OUTPUT push-pull mode */
      case GPIO_MODE_OUTPUT_PP:
        /* Check the GPIO speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
        break;

      /* If we are configuring the pin in OUTPUT open-drain mode */
      case GPIO_MODE_OUTPUT_OD:
        /* Check the GPIO speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
        break;

      /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
      case GPIO_MODE_AF_PP:
        /* Check the GPIO speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
        break;

      /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
      case GPIO_MODE_AF_OD:
        /* Check the GPIO speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
        break;

      /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
      case GPIO_MODE_INPUT:
      case GPIO_MODE_IT_RISING:
      case GPIO_MODE_IT_FALLING:
      case GPIO_MODE_IT_RISING_FALLING:
      case GPIO_MODE_EVT_RISING:
      case GPIO_MODE_EVT_FALLING:
      case GPIO_MODE_EVT_RISING_FALLING:
        /* Check the GPIO pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
        if (GPIO_Init->Pull == GPIO_NOPULL) {
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
        } else if (GPIO_Init->Pull == GPIO_PULLUP) {
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;

          /* Set the corresponding ODR bit */
          GPIOx->BSRR = ioposition;
        } else /* GPIO_PULLDOWN */
        {
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;

          /* Reset the corresponding ODR bit */
          GPIOx->BRR = ioposition;
        }
        break;

      /* If we are configuring the pin in INPUT analog mode */
      case GPIO_MODE_ANALOG:
        config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
        break;

      /* Parameters are checked with assert_param */
      default:
        break;
      }

      /* Check if the current bit belongs to first half or last half of the pin count number
       in order to address CRH or CRL register*/
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);

      /* Apply the new configuration of the pin to the register */
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
        AFIO->EXTICR[position >> 2U] = temp;

        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) {
          SET_BIT(EXTI->IMR, iocurrent);
        } else {
          CLEAR_BIT(EXTI->IMR, iocurrent);
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) {
          SET_BIT(EXTI->EMR, iocurrent);
        } else {
          CLEAR_BIT(EXTI->EMR, iocurrent);
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) {
          SET_BIT(EXTI->RTSR, iocurrent);
        } else {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) {
          SET_BIT(EXTI->FTSR, iocurrent);
        } else {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
        }
      }
    }
  }
}

/**
 * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Pin: specifies the port bit to be written.
 *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
 * @retval None
 */
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) {
  uint32_t       position  = 0x00U;
  uint32_t       iocurrent = 0x00U;
  uint32_t       tmp       = 0x00U;
  __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
  uint32_t       registeroffset = 0U;

  /* Check the parameters */
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* Configure the port pins */
  while ((GPIO_Pin >> position) != 0U) {
    /* Get current io position */
    iocurrent = (GPIO_Pin) & (1U << position);

    if (iocurrent) {
      /*------------------------- GPIO Mode Configuration --------------------*/
      /* Check if the current bit belongs to first half or last half of the pin count number
       in order to address CRH or CRL register */
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);

      /* CRL/CRH default value is floating input(0x04) shifted to correct position */
      MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);

      /* ODR default value is 0 */
      CLEAR_BIT(GPIOx->ODR, iocurrent);

      /*------------------------- EXTI Mode Configuration --------------------*/
      /* Clear the External Interrupt or Event for the current IO */

      tmp = AFIO->EXTICR[position >> 2U];
      tmp &= 0x0FU << (4U * (position & 0x03U));
      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) {
        tmp = 0x0FU << (4U * (position & 0x03U));
        CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);

        /* Clear EXTI line configuration */
        CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
        CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);

        /* Clear Rising Falling edge configuration */
        CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
        CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
      }
    }

    position++;
  }
}

/**
 * @}
 */

/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
 *  @brief   GPIO Read and Write
 *
@verbatim
 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the GPIOs.

@endverbatim
  * @{
  */

/**
 * @brief  Reads the specified input port pin.
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Pin: specifies the port bit to read.
 *         This parameter can be GPIO_PIN_x where x can be (0..15).
 * @retval The input port pin value.
 */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
  GPIO_PinState bitstatus;

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) {
    bitstatus = GPIO_PIN_SET;
  } else {
    bitstatus = GPIO_PIN_RESET;
  }
  return bitstatus;
}

/**
 * @brief  Sets or clears the selected data port bit.
 *
 * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
 *         accesses. In this way, there is no risk of an IRQ occurring between
 *         the read and the modify access.
 *
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Pin: specifies the port bit to be written.
 *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
 * @param  PinState: specifies the value to be written to the selected bit.
 *          This parameter can be one of the GPIO_PinState enum values:
 *            @arg GPIO_PIN_RESET: to clear the port pin
 *            @arg GPIO_PIN_SET: to set the port pin
 * @retval None
 */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) {
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET) {
    GPIOx->BSRR = GPIO_Pin;
  } else {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
  }
}

/**
 * @brief  Toggles the specified GPIO pin
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Pin: Specifies the pins to be toggled.
 * @retval None
 */
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->ODR ^= GPIO_Pin;
}

/**
 * @brief  Locks GPIO Pins configuration registers.
 * @note   The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
 *         has been applied on a port bit, it is no longer possible to modify the value of the port bit until
 *         the next reset.
 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 * @param  GPIO_Pin: specifies the port bit to be locked.
 *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 * @retval None
 */
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) {
  __IO uint32_t tmp = GPIO_LCKR_LCKK;

  /* Check the parameters */
  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  /* Apply lock key write sequence */
  SET_BIT(tmp, GPIO_Pin);
  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
  GPIOx->LCKR = tmp;
  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
  GPIOx->LCKR = GPIO_Pin;
  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
  GPIOx->LCKR = tmp;
  /* Read LCKK bit*/
  tmp = GPIOx->LCKR;

  if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) {
    return HAL_OK;
  } else {
    return HAL_ERROR;
  }
}

/**
 * @brief  This function handles EXTI interrupt request.
 * @param  GPIO_Pin: Specifies the pins connected EXTI line
 * @retval None
 */
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) {
  /* EXTI line interrupt detected */
  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) {
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
  }
}

/**
 * @brief  EXTI line detection callbacks.
 * @param  GPIO_Pin: Specifies the pins connected EXTI line
 * @retval None
 */
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(GPIO_Pin);
  /* NOTE: This function Should not be modified, when the callback is needed,
           the HAL_GPIO_EXTI_Callback could be implemented in the user file
   */
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_GPIO_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_gpio_ex.c
  * @author  MCD Application Team
  * @brief   GPIO Extension HAL module driver.
  *         This file provides firmware functions to manage the following
  *          functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
  *           + Extended features functions
  *
  @verbatim
  ==============================================================================
                    ##### GPIO Peripheral extension features #####
  ==============================================================================
  [..] GPIO module on STM32F1 family, manage also the AFIO register:
       (+) Possibility to use the EVENTOUT Cortex feature

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to use EVENTOUT Cortex feature
    (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
    (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
    (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup GPIOEx GPIOEx
 * @brief GPIO HAL module driver
 * @{
 */

#ifdef HAL_GPIO_MODULE_ENABLED

/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
 * @{
 */

/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
 *  @brief    Extended features functions
 *
@verbatim
  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
    (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
    (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
    (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()

@endverbatim
  * @{
  */

/**
 * @brief  Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
 * @param  GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
 *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
 * @param  GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
 *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
 * @retval None
 */
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) {
  /* Verify the parameters */
  assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
  assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));

  /* Apply the new configuration */
  MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
}

/**
 * @brief  Enables the Event Output.
 * @retval None
 */
void HAL_GPIOEx_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }

/**
 * @brief  Disables the Event Output.
 * @retval None
 */
void HAL_GPIOEx_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); }

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_GPIO_MODULE_ENABLED */

/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_i2c.c
  * @author  MCD Application Team
  * @brief   I2C HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
  *           + Initialization and de-initialization functions
  *           + IO operation functions
  *           + Peripheral State, Mode and Error functions
  *
  @verbatim
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()


    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()

    *** Interrupt mode IO sequential operation ***
    ==============================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback


     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros

     *** I2C Workarounds linked to Silicon Limitation ***
     ====================================================
     [..]
       Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
       (@) See ErrataSheet to know full silicon limitation list of your product.

       (#) Workarounds Implemented inside I2C HAL Driver
          (##) Wrong data read into data register (Polling and Interrupt mode)
          (##) Start cannot be generated after a misplaced Stop
          (##) Some software events must be managed before the current byte is being transferred:
               Workaround: Use DMA in general, except when the Master is receiving a single byte.
               For Interupt mode, I2C should have the highest priority in the application.
          (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
               Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
               supported by the slave.
          (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
               Workaround: If the slave device allows it, use the clock stretching mechanism
               by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup I2C I2C
 * @brief I2C HAL module driver
 * @{
 */

#ifdef HAL_I2C_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup I2C_Private_Define
 * @{
 */
#define I2C_TIMEOUT_FLAG      35U         /*!< Timeout 35 ms             */
#define I2C_TIMEOUT_BUSY_FLAG 25U         /*!< Timeout 25 ms             */
#define I2C_NO_OPTION_FRAME   0xFFFF0000U /*!< XferOptions default value */

/* Private define for @ref PreviousState usage */
#define I2C_STATE_MSK            ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
#define I2C_STATE_NONE           ((uint32_t)(HAL_I2C_MODE_NONE))                                                                  /*!< Default Value                                          */
#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))                      /*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))                      /*!< Master Busy RX, combinaison of State LSB and Mode enum */
#define I2C_STATE_SLAVE_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))                       /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
#define I2C_STATE_SLAVE_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))                       /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */

/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup I2C_Private_Functions
 * @{
 */
/* Private functions to handle DMA transfer */
static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);

static void I2C_ITError(I2C_HandleTypeDef *hi2c);

static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);

/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);

/**
 * @}
 */

/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_Exported_Functions I2C Exported Functions
 * @{
 */

/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
 *  @brief    Initialization and Configuration functions
 *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Communication Speed
        (++) Duty cycle
        (++) Addressing mode
        (++) Own Address 1
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

@endverbatim
  * @{
  */

/**
 * @brief  Initializes the I2C according to the specified parameters
 *         in the I2C_InitTypeDef and create the associated handle.
 * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) {
  uint32_t freqrange = 0U;
  uint32_t pclk1     = 0U;

  /* Check the I2C handle allocation */
  if (hi2c == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_I2C_MspInit(hi2c);
  }

  hi2c->State = HAL_I2C_STATE_BUSY;

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);

  /* Get PCLK1 frequency */
  pclk1 = HAL_RCC_GetPCLK1Freq();

  /* Check the minimum allowed PCLK1 frequency */
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) {
    return HAL_ERROR;
  }

  /* Calculate frequency range */
  freqrange = I2C_FREQRANGE(pclk1);

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->CR2 = freqrange;

  /*---------------------------- I2Cx TRISE Configuration --------------------*/
  /* Configure I2Cx: Rise Time */
  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);

  /*---------------------------- I2Cx CCR Configuration ----------------------*/
  /* Configure I2Cx: Speed */
  hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Configure I2Cx: Own Address1 and addressing mode */
  hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Configure I2Cx: Dual mode and Own Address2 */
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);

  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
  hi2c->State         = HAL_I2C_STATE_READY;
  hi2c->PreviousState = I2C_STATE_NONE;
  hi2c->Mode          = HAL_I2C_MODE_NONE;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the I2C peripheral.
 * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) {
  /* Check the I2C handle allocation */
  if (hi2c == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));

  hi2c->State = HAL_I2C_STATE_BUSY;

  /* Disable the I2C Peripheral Clock */
  __HAL_I2C_DISABLE(hi2c);

  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_I2C_MspDeInit(hi2c);

  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
  hi2c->State         = HAL_I2C_STATE_RESET;
  hi2c->PreviousState = I2C_STATE_NONE;
  hi2c->Mode          = HAL_I2C_MODE_NONE;

  /* Release Lock */
  __HAL_UNLOCK(hi2c);

  return HAL_OK;
}

/**
 * @brief I2C MSP Init.
 * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval None
 */
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_I2C_MspInit could be implemented in the user file
   */
}

/**
 * @brief I2C MSP DeInit
 * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval None
 */
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_I2C_MspDeInit could be implemented in the user file
   */
}

/**
 * @}
 */

/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
 *  @brief   Data transfers functions
 *
@verbatim
 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Master_Sequential_Transmit_IT()
        (++) HAL_I2C_Master_Sequential_Receive_IT()
        (++) HAL_I2C_Slave_Sequential_Transmit_IT()
        (++) HAL_I2C_Slave_Sequential_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

@endverbatim
  * @{
  */

/**
 * @brief  Transmits in master mode an amount of data in blocking mode.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
      return HAL_BUSY;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Send Slave Address */
    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_ERROR;
      } else {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_TIMEOUT;
      }
    }

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

    while (hi2c->XferSize > 0U) {
      /* Wait until TXE flag is set */
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;
          return HAL_ERROR;
        } else {
          return HAL_TIMEOUT;
        }
      }

      /* Write data to DR */
      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
      hi2c->XferCount--;
      hi2c->XferSize--;

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) {
        /* Write data to DR */
        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
        hi2c->XferCount--;
        hi2c->XferSize--;
      }

      /* Wait until BTF flag is set */
      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;
          return HAL_ERROR;
        } else {
          return HAL_TIMEOUT;
        }
      }
    }

    /* Generate Stop */
    hi2c->Instance->CR1 |= I2C_CR1_STOP;

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receives in master mode an amount of data in blocking mode.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
      return HAL_BUSY;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Send Slave Address */
    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_ERROR;
      } else {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_TIMEOUT;
      }
    }

    if (hi2c->XferSize == 0U) {
      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
    } else if (hi2c->XferSize == 1U) {
      /* Disable Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
      software sequence must complete before the current byte end of transfer */
      __disable_irq();

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;

      /* Re-enable IRQs */
      __enable_irq();
    } else if (hi2c->XferSize == 2U) {
      /* Enable Pos */
      hi2c->Instance->CR1 |= I2C_CR1_POS;

      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
      software sequence must complete before the current byte end of transfer */
      __disable_irq();

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Disable Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

      /* Re-enable IRQs */
      __enable_irq();
    } else {
      /* Enable Acknowledge */
      hi2c->Instance->CR1 |= I2C_CR1_ACK;

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
    }

    while (hi2c->XferSize > 0U) {
      if (hi2c->XferSize <= 3U) {
        /* One byte */
        if (hi2c->XferSize == 1U) {
          /* Wait until RXNE flag is set */
          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
            if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) {
              return HAL_TIMEOUT;
            } else {
              return HAL_ERROR;
            }
          }

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
        /* Two bytes */
        else if (hi2c->XferSize == 2U) {
          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
             software sequence must complete before the current byte end of transfer */
          __disable_irq();

          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Re-enable IRQs */
          __enable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
        /* 3 Last bytes */
        else {
          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Disable Acknowledge */
          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
             software sequence must complete before the current byte end of transfer */
          __disable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Re-enable IRQs */
          __enable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
      } else {
        /* Wait until RXNE flag is set */
        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
          if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) {
            return HAL_TIMEOUT;
          } else {
            return HAL_ERROR;
          }
        }

        /* Read data from DR */
        (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
        hi2c->XferSize--;
        hi2c->XferCount--;

        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) {
          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
      }
    }

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Transmits in slave mode an amount of data in blocking mode.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Wait until ADDR flag is set */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) {
      return HAL_TIMEOUT;
    }

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

    while (hi2c->XferSize > 0U) {
      /* Wait until TXE flag is set */
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
        /* Disable Address Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          return HAL_ERROR;
        } else {
          return HAL_TIMEOUT;
        }
      }

      /* Write data to DR */
      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
      hi2c->XferCount--;
      hi2c->XferSize--;

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) {
        /* Write data to DR */
        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
        hi2c->XferCount--;
        hi2c->XferSize--;
      }
    }

    /* Wait until AF flag is set */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) {
      return HAL_TIMEOUT;
    }

    /* Clear AF flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);

    /* Disable Address Acknowledge */
    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receive in slave mode an amount of data in blocking mode
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Wait until ADDR flag is set */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) {
      return HAL_TIMEOUT;
    }

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

    while (hi2c->XferSize > 0U) {
      /* Wait until RXNE flag is set */
      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
        /* Disable Address Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

        if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) {
          return HAL_TIMEOUT;
        } else {
          return HAL_ERROR;
        }
      }

      /* Read data from DR */
      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
      hi2c->XferSize--;
      hi2c->XferCount--;

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) {
        /* Read data from DR */
        (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
        hi2c->XferSize--;
        hi2c->XferCount--;
      }
    }

    /* Wait until STOP flag is set */
    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
      /* Disable Address Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        return HAL_ERROR;
      } else {
        return HAL_TIMEOUT;
      }
    }

    /* Clear STOP flag */
    __HAL_I2C_CLEAR_STOPFLAG(hi2c);

    /* Disable Address Acknowledge */
    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */
    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    /* Enable Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
    to avoid the risk of I2C interrupt handle execution before current
    process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
 * @note   This interface allow to manage repeated start condition when a direction change during transfer
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) {
  __IO uint32_t Prev_State = 0x00U;
  __IO uint32_t count      = 0x00U;

  /* Check the parameters */
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Check Busy Flag only if FIRST call of Master interface */
    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) {
      /* Wait until BUSY flag is reset */
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
      do {
        if (count-- == 0U) {
          hi2c->PreviousState = I2C_STATE_NONE;
          hi2c->State         = HAL_I2C_STATE_READY;

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);

          return HAL_TIMEOUT;
        }
      } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = XferOptions;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    Prev_State = hi2c->PreviousState;

    /* Generate Start */
    if ((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) {
      /* Generate Start condition if first transfer */
      if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) {
        /* Generate Start */
        hi2c->Instance->CR1 |= I2C_CR1_START;
      } else {
        /* Generate ReStart */
        hi2c->Instance->CR1 |= I2C_CR1_START;
      }
    }

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
    to avoid the risk of I2C interrupt handle execution before current
    process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
 * @note   This interface allow to manage repeated start condition when a direction change during transfer
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) {
  __IO uint32_t count = 0U;

  /* Check the parameters */
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Check Busy Flag only if FIRST call of Master interface */
    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) {
      /* Wait until BUSY flag is reset */
      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
      do {
        if (count-- == 0U) {
          hi2c->PreviousState = I2C_STATE_NONE;
          hi2c->State         = HAL_I2C_STATE_READY;

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);

          return HAL_TIMEOUT;
        }
      } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = XferOptions;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) {
      /* Generate Start condition if first transfer */
      if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;

        /* Generate Start */
        hi2c->Instance->CR1 |= I2C_CR1_START;
      } else {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;

        /* Generate ReStart */
        hi2c->Instance->CR1 |= I2C_CR1_START;
      }
    }

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
    to avoid the risk of I2C interrupt handle execution before current
    process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferSize    = Size;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
 * @note   This interface allow to manage repeated start condition when a direction change during transfer
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) {
  /* Check the parameters */
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));

  if (hi2c->State == HAL_I2C_STATE_LISTEN) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = XferOptions;
    hi2c->XferSize    = hi2c->XferCount;

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
 * @note   This interface allow to manage repeated start condition when a direction change during transfer
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) {
  /* Check the parameters */
  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));

  if (hi2c->State == HAL_I2C_STATE_LISTEN) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = XferOptions;
    hi2c->XferSize    = hi2c->XferCount;

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Enable the Address listen mode with Interrupt.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) {
  if (hi2c->State == HAL_I2C_STATE_READY) {
    hi2c->State = HAL_I2C_STATE_LISTEN;

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Enable EVT and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Disable the Address listen mode with Interrupt.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) {
  /* Declaration of tmp to prevent undefined behavior of volatile usage */
  uint32_t tmp;

  /* Disable Address listen mode only if a transfer is not ongoing */
  if (hi2c->State == HAL_I2C_STATE_LISTEN) {
    tmp                 = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
    hi2c->State         = HAL_I2C_STATE_READY;
    hi2c->Mode          = HAL_I2C_MODE_NONE;

    /* Disable Address Acknowledge */
    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

    /* Disable EVT and ERR interrupt */
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    if (hi2c->XferSize > 0U) {
      /* Set the I2C DMA transfer complete callback */
      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;

      /* Set the DMA error callback */
      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;

      /* Set the unused DMA callbacks to NULL */
      hi2c->hdmatx->XferHalfCpltCallback = NULL;
      hi2c->hdmatx->XferAbortCallback    = NULL;

      /* Enable the DMA channel */
      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);

      /* Enable Acknowledge */
      hi2c->Instance->CR1 |= I2C_CR1_ACK;

      /* Generate Start */
      hi2c->Instance->CR1 |= I2C_CR1_START;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
      to avoid the risk of I2C interrupt handle execution before current
      process unlock */

      /* Enable EVT and ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

      /* Enable DMA Request */
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
    } else {
      /* Enable Acknowledge */
      hi2c->Instance->CR1 |= I2C_CR1_ACK;

      /* Generate Start */
      hi2c->Instance->CR1 |= I2C_CR1_START;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
      to avoid the risk of I2C interrupt handle execution before current
      process unlock */

      /* Enable EVT, BUF and ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
    }

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;
    hi2c->Devaddress  = DevAddress;

    if (hi2c->XferSize > 0U) {
      /* Set the I2C DMA transfer complete callback */
      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;

      /* Set the DMA error callback */
      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;

      /* Set the unused DMA callbacks to NULL */
      hi2c->hdmarx->XferHalfCpltCallback = NULL;
      hi2c->hdmarx->XferAbortCallback    = NULL;

      /* Enable the DMA channel */
      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);

      /* Enable Acknowledge */
      hi2c->Instance->CR1 |= I2C_CR1_ACK;

      /* Generate Start */
      hi2c->Instance->CR1 |= I2C_CR1_START;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
                to avoid the risk of I2C interrupt handle execution before current
                process unlock */

      /* Enable EVT and ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

      /* Enable DMA Request */
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
    } else {
      /* Enable Acknowledge */
      hi2c->Instance->CR1 |= I2C_CR1_ACK;

      /* Generate Start */
      hi2c->Instance->CR1 |= I2C_CR1_START;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
      to avoid the risk of I2C interrupt handle execution before current
      process unlock */

      /* Enable EVT, BUF and ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
    }

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Abort a master I2C process communication with Interrupt.
 * @note   This abort can be called only if state is ready
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(DevAddress);

  /* Abort Master transfer during Receive or Transmit process    */
  if (hi2c->Mode == HAL_I2C_MODE_MASTER) {
    /* Process Locked */
    __HAL_LOCK(hi2c);

    hi2c->PreviousState = I2C_STATE_NONE;
    hi2c->State         = HAL_I2C_STATE_ABORT;

    /* Disable Acknowledge */
    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

    /* Generate Stop */
    hi2c->Instance->CR1 |= I2C_CR1_STOP;

    hi2c->XferCount = 0U;

    /* Disable EVT, BUF and ERR interrupt */
    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Call the corresponding callback to inform upper layer of End of Transfer */
    I2C_ITError(hi2c);

    return HAL_OK;
  } else {
    /* Wrong usage of abort function */
    /* This function should be used only in case of abort monitored by master device */
    return HAL_ERROR;
  }
}

/**
 * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Set the I2C DMA transfer complete callback */
    hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;

    /* Set the DMA error callback */
    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;

    /* Set the unused DMA callbacks to NULL */
    hi2c->hdmatx->XferHalfCpltCallback = NULL;
    hi2c->hdmatx->XferAbortCallback    = NULL;

    /* Enable the DMA channel */
    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */
    /* Enable EVT and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

    /* Enable DMA Request */
    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  if (hi2c->State == HAL_I2C_STATE_READY) {
    if ((pData == NULL) || (Size == 0U)) {
      return HAL_ERROR;
    }

    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Set the I2C DMA transfer complete callback */
    hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;

    /* Set the DMA error callback */
    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;

    /* Set the unused DMA callbacks to NULL */
    hi2c->hdmarx->XferHalfCpltCallback = NULL;
    hi2c->hdmarx->XferAbortCallback    = NULL;

    /* Enable the DMA channel */
    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);

    /* Enable Address Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
              to avoid the risk of I2C interrupt handle execution before current
              process unlock */
    /* Enable EVT and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

    /* Enable DMA Request */
    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}
/**
 * @brief  Write an amount of data in blocking mode to a specific memory address
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
      return HAL_BUSY;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Send Slave Address and Memory Address */
    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_ERROR;
      } else {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_TIMEOUT;
      }
    }

    while (hi2c->XferSize > 0U) {
      /* Wait until TXE flag is set */
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;
          return HAL_ERROR;
        } else {
          return HAL_TIMEOUT;
        }
      }

      /* Write data to DR */
      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
      hi2c->XferSize--;
      hi2c->XferCount--;

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) {
        /* Write data to DR */
        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
        hi2c->XferSize--;
        hi2c->XferCount--;
      }
    }

    /* Wait until BTF flag is set */
    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;
        return HAL_ERROR;
      } else {
        return HAL_TIMEOUT;
      }
    }

    /* Generate Stop */
    hi2c->Instance->CR1 |= I2C_CR1_STOP;

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Read an amount of data in blocking mode from a specific memory address
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) {
  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
      return HAL_BUSY;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    /* Send Slave Address and Memory Address */
    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_ERROR;
      } else {
        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
        return HAL_TIMEOUT;
      }
    }

    if (hi2c->XferSize == 0U) {
      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
    } else if (hi2c->XferSize == 1U) {
      /* Disable Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
         software sequence must complete before the current byte end of transfer */
      __disable_irq();

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;

      /* Re-enable IRQs */
      __enable_irq();
    } else if (hi2c->XferSize == 2U) {
      /* Enable Pos */
      hi2c->Instance->CR1 |= I2C_CR1_POS;

      /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
         software sequence must complete before the current byte end of transfer */
      __disable_irq();

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Disable Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

      /* Re-enable IRQs */
      __enable_irq();
    } else {
      /* Enable Acknowledge */
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
    }

    while (hi2c->XferSize > 0U) {
      if (hi2c->XferSize <= 3U) {
        /* One byte */
        if (hi2c->XferSize == 1U) {
          /* Wait until RXNE flag is set */
          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
            if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) {
              return HAL_TIMEOUT;
            } else {
              return HAL_ERROR;
            }
          }

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
        /* Two bytes */
        else if (hi2c->XferSize == 2U) {
          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
             software sequence must complete before the current byte end of transfer */
          __disable_irq();

          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Re-enable IRQs */
          __enable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
        /* 3 Last bytes */
        else {
          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Disable Acknowledge */
          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

          /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
             software sequence must complete before the current byte end of transfer */
          __disable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Wait until BTF flag is set */
          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) {
            return HAL_TIMEOUT;
          }

          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;

          /* Re-enable IRQs */
          __enable_irq();

          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
      } else {
        /* Wait until RXNE flag is set */
        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) {
          if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) {
            return HAL_TIMEOUT;
          } else {
            return HAL_ERROR;
          }
        }

        /* Read data from DR */
        (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
        hi2c->XferSize--;
        hi2c->XferCount--;

        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) {
          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
          hi2c->XferSize--;
          hi2c->XferCount--;
        }
      }
    }

    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferSize    = Size;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->Devaddress  = DevAddress;
    hi2c->Memaddress  = MemAddress;
    hi2c->MemaddSize  = MemAddSize;
    hi2c->EventCount  = 0U;

    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    /* Note : The I2C interrupts must be enabled after unlocking current process
    to avoid the risk of I2C interrupt handle execution before current
    process unlock */

    /* Enable EVT, BUF and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferSize    = Size;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->Devaddress  = DevAddress;
    hi2c->Memaddress  = MemAddress;
    hi2c->MemaddSize  = MemAddSize;
    hi2c->EventCount  = 0U;

    /* Enable Acknowledge */
    hi2c->Instance->CR1 |= I2C_CR1_ACK;

    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    if (hi2c->XferSize > 0U) {
      /* Note : The I2C interrupts must be enabled after unlocking current process
      to avoid the risk of I2C interrupt handle execution before current
      process unlock */

      /* Enable EVT, BUF and ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
    }
    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be sent
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) {
  __IO uint32_t count = 0U;

  uint32_t tickstart = 0x00U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferSize    = Size;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;

    if (hi2c->XferSize > 0U) {
      /* Set the I2C DMA transfer complete callback */
      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;

      /* Set the DMA error callback */
      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;

      /* Set the unused DMA callbacks to NULL */
      hi2c->hdmatx->XferHalfCpltCallback = NULL;
      hi2c->hdmatx->XferAbortCallback    = NULL;

      /* Enable the DMA channel */
      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);

      /* Send Slave Address and Memory Address */
      if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_ERROR;
        } else {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_TIMEOUT;
        }
      }

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
      to avoid the risk of I2C interrupt handle execution before current
      process unlock */
      /* Enable ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);

      /* Enable DMA Request */
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
    }
    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  pData Pointer to data buffer
 * @param  Size Amount of data to be read
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) {
  uint32_t      tickstart = 0x00U;
  __IO uint32_t count     = 0U;

  /* Init tickstart for timeout management*/
  tickstart = HAL_GetTick();

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
    do {
      if (count-- == 0U) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
    hi2c->Mode      = HAL_I2C_MODE_MEM;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
    hi2c->XferCount   = Size;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
    hi2c->XferSize    = hi2c->XferCount;

    if (hi2c->XferSize > 0U) {
      /* Set the I2C DMA transfer complete callback */
      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;

      /* Set the DMA error callback */
      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;

      /* Set the unused DMA callbacks to NULL */
      hi2c->hdmarx->XferAbortCallback = NULL;

      /* Enable the DMA channel */
      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);

      /* Send Slave Address and Memory Address */
      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_ERROR;
        } else {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_TIMEOUT;
        }
      }

      if (Size == 1U) {
        /* Disable Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
      } else {
        /* Enable Last DMA bit */
        hi2c->Instance->CR2 |= I2C_CR2_LAST;
      }

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      /* Note : The I2C interrupts must be enabled after unlocking current process
                to avoid the risk of I2C interrupt handle execution before current
                process unlock */
      /* Enable ERR interrupt */
      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);

      /* Enable DMA Request */
      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
    } else {
      /* Send Slave Address and Memory Address */
      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_ERROR;
        } else {
          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
          return HAL_TIMEOUT;
        }
      }

      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;

      hi2c->State = HAL_I2C_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);
    }

    return HAL_OK;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  Checks if target device is ready for communication.
 * @note   This function is used with Memory devices
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  Trials Number of trials
 * @param  Timeout Timeout duration
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) {
  uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;

  /* Get tick */
  tickstart = HAL_GetTick();

  if (hi2c->State == HAL_I2C_STATE_READY) {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
      return HAL_BUSY;
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
    }

    /* Disable Pos */
    hi2c->Instance->CR1 &= ~I2C_CR1_POS;

    hi2c->State       = HAL_I2C_STATE_BUSY;
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;

    do {
      /* Generate Start */
      hi2c->Instance->CR1 |= I2C_CR1_START;

      /* Wait until SB flag is set */
      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) {
        return HAL_TIMEOUT;
      }

      /* Send slave address */
      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);

      /* Wait until ADDR or AF flag are set */
      /* Get tick */
      tickstart = HAL_GetTick();

      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
      tmp3 = hi2c->State;
      while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) {
        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) {
          hi2c->State = HAL_I2C_STATE_TIMEOUT;
        }
        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
        tmp3 = hi2c->State;
      }

      hi2c->State = HAL_I2C_STATE_READY;

      /* Check if the ADDR flag has been set */
      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) {
        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;

        /* Clear ADDR Flag */
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

        /* Wait until BUSY flag is reset */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
          return HAL_TIMEOUT;
        }

        hi2c->State = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_OK;
      } else {
        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;

        /* Clear AF Flag */
        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);

        /* Wait until BUSY flag is reset */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) {
          return HAL_TIMEOUT;
        }
      }
    } while (I2C_Trials++ < Trials);

    hi2c->State = HAL_I2C_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_ERROR;
  } else {
    return HAL_BUSY;
  }
}

/**
 * @brief  This function handles I2C event interrupt request.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) {
  uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);

  uint32_t CurrentMode = hi2c->Mode;

  /* Master or Memory mode selected */
  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) {
    /* SB Set ----------------------------------------------------------------*/
    if (((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) {
      I2C_Master_SB(hi2c);
    }
    /* ADDR Set --------------------------------------------------------------*/
    else if (((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) {
      I2C_Master_ADDR(hi2c);
    }

    /* I2C in mode Transmitter -----------------------------------------------*/
    if ((sr2itflags & I2C_FLAG_TRA) != RESET) {
      /* TXE set and BTF reset -----------------------------------------------*/
      if (((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) {
        I2C_MasterTransmit_TXE(hi2c);
      }
      /* BTF set -------------------------------------------------------------*/
      else if (((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) {
        I2C_MasterTransmit_BTF(hi2c);
      }
    }
    /* I2C in mode Receiver --------------------------------------------------*/
    else {
      /* RXNE set and BTF reset -----------------------------------------------*/
      if (((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) {
        I2C_MasterReceive_RXNE(hi2c);
      }
      /* BTF set -------------------------------------------------------------*/
      else if (((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) {
        I2C_MasterReceive_BTF(hi2c);
      }
    }
  }
  /* Slave mode selected */
#if 0
  else
  {
    /* ADDR set --------------------------------------------------------------*/
    if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
    {
      I2C_Slave_ADDR(hi2c);
    }
    /* STOPF set --------------------------------------------------------------*/
    else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
    {
      I2C_Slave_STOPF(hi2c);
    }
    /* I2C in mode Transmitter -----------------------------------------------*/
    else if((sr2itflags & I2C_FLAG_TRA) != RESET)
    {
      /* TXE set and BTF reset -----------------------------------------------*/
      if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
      {
        I2C_SlaveTransmit_TXE(hi2c);
      }
      /* BTF set -------------------------------------------------------------*/
      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
      {
        I2C_SlaveTransmit_BTF(hi2c);
      }
    }
    /* I2C in mode Receiver --------------------------------------------------*/
    else
    {
      /* RXNE set and BTF reset ----------------------------------------------*/
      if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
      {
        I2C_SlaveReceive_RXNE(hi2c);
      }
      /* BTF set -------------------------------------------------------------*/
      else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
      {
        I2C_SlaveReceive_BTF(hi2c);
      }
    }
  }
#endif
}

/**
 * @brief  This function handles I2C error interrupt request.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) {
  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);

  /* I2C Bus error interrupt occurred ----------------------------------------*/
  if (((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) {
    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;

    /* Clear BERR flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);

    /* Workaround: Start cannot be generated after a misplaced Stop */
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
  }

  /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
  if (((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) {
    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;

    /* Clear ARLO flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
  }

  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
  if (((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) {
    tmp1 = hi2c->Mode;
    tmp2 = hi2c->XferCount;
    tmp3 = hi2c->State;
    tmp4 = hi2c->PreviousState;
    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) &&
        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) {
    } else {
      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;

      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
      if (hi2c->Mode == HAL_I2C_MODE_MASTER) {
        /* Generate Stop */
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
      }

      /* Clear AF flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
    }
  }

  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
  if (((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) {
    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
    /* Clear OVR flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
  }

  /* Call the Error Callback in case of Error detected -----------------------*/
  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) {
    I2C_ITError(hi2c);
  }
}

/**
 * @brief  Master Tx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
   */
}

/**
 * @brief  Master Rx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
   */
}

/** @brief  Slave Tx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
   */
}

/**
 * @brief  Slave Rx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
   */
}

/**
 * @brief  Slave Address Match callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
 * @param  AddrMatchCode Address Match Code
 * @retval None
 */
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);
  UNUSED(TransferDirection);
  UNUSED(AddrMatchCode);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_AddrCallback can be implemented in the user file
   */
}

/**
 * @brief  Listen Complete callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
          the HAL_I2C_ListenCpltCallback can be implemented in the user file
 */
}

/**
 * @brief  Memory Tx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_MemTxCpltCallback can be implemented in the user file
   */
}

/**
 * @brief  Memory Rx Transfer completed callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_MemRxCpltCallback can be implemented in the user file
   */
}

/**
 * @brief  I2C error callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_ErrorCallback can be implemented in the user file
   */
}

/**
 * @brief  I2C abort callback.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval None
 */
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hi2c);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_I2C_AbortCpltCallback could be implemented in the user file
   */
}

/**
 * @}
 */

/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
  *  @brief   Peripheral State and Errors functions
  *
@verbatim
 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

@endverbatim
  * @{
  */

/**
 * @brief  Return the I2C handle state.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval HAL state
 */
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) {
  /* Return I2C handle state */
  return hi2c->State;
}

/**
 * @brief  Return the I2C Master, Slave, Memory or no mode.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL mode
 */
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) { return hi2c->Mode; }

/**
 * @brief  Return the I2C error code
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *              the configuration information for the specified I2C.
 * @retval I2C Error Code
 */
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; }

/**
 * @}
 */

/**
 * @brief  Handle TXE flag for Master
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) {
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
  uint32_t CurrentState       = hi2c->State;
  uint32_t CurrentMode        = hi2c->Mode;
  uint32_t CurrentXferOptions = hi2c->XferOptions;

  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) {
    /* Call TxCpltCallback() directly if no stop mode is set */
    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) {
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
      hi2c->Mode          = HAL_I2C_MODE_NONE;
      hi2c->State         = HAL_I2C_STATE_READY;

      HAL_I2C_MasterTxCpltCallback(hi2c);
    } else /* Generate Stop condition then Call TxCpltCallback() */
    {
      /* Disable EVT, BUF and ERR interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;

      hi2c->PreviousState = I2C_STATE_NONE;
      hi2c->State         = HAL_I2C_STATE_READY;

      if (hi2c->Mode == HAL_I2C_MODE_MEM) {
        hi2c->Mode = HAL_I2C_MODE_NONE;
        HAL_I2C_MemTxCpltCallback(hi2c);
      } else {
        hi2c->Mode = HAL_I2C_MODE_NONE;
        HAL_I2C_MasterTxCpltCallback(hi2c);
      }
    }
  } else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) {
    if (hi2c->XferCount == 0U) {
      /* Disable BUF interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
    } else {
      if (hi2c->Mode == HAL_I2C_MODE_MEM) {
        if (hi2c->EventCount == 0) {
          /* If Memory address size is 8Bit */
          if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) {
            /* Send Memory Address */
            hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);

            hi2c->EventCount += 2;
          }
          /* If Memory address size is 16Bit */
          else {
            /* Send MSB of Memory Address */
            hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);

            hi2c->EventCount++;
          }
        } else if (hi2c->EventCount == 1) {
          /* Send LSB of Memory Address */
          hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);

          hi2c->EventCount++;
        } else if (hi2c->EventCount == 2) {
          if (hi2c->State == HAL_I2C_STATE_BUSY_RX) {
            /* Generate Restart */
            hi2c->Instance->CR1 |= I2C_CR1_START;
          } else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) {
            /* Write data to DR */
            hi2c->Instance->DR = (*hi2c->pBuffPtr++);
            hi2c->XferCount--;
          }
        }
      } else {
        /* Write data to DR */
        hi2c->Instance->DR = (*hi2c->pBuffPtr++);
        hi2c->XferCount--;
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  Handle BTF flag for Master transmitter
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) {
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
  uint32_t CurrentXferOptions = hi2c->XferOptions;

  if (hi2c->State == HAL_I2C_STATE_BUSY_TX) {
    if (hi2c->XferCount != 0U) {
      /* Write data to DR */
      hi2c->Instance->DR = (*hi2c->pBuffPtr++);
      hi2c->XferCount--;
    } else {
      /* Call TxCpltCallback() directly if no stop mode is set */
      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) {
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
        hi2c->Mode          = HAL_I2C_MODE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        HAL_I2C_MasterTxCpltCallback(hi2c);
      } else /* Generate Stop condition then Call TxCpltCallback() */
      {
        /* Disable EVT, BUF and ERR interrupt */
        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;

        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        if (hi2c->Mode == HAL_I2C_MODE_MEM) {
          hi2c->Mode = HAL_I2C_MODE_NONE;

          HAL_I2C_MemTxCpltCallback(hi2c);
        } else {
          hi2c->Mode = HAL_I2C_MODE_NONE;

          HAL_I2C_MasterTxCpltCallback(hi2c);
        }
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  Handle RXNE flag for Master
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) {
  if (hi2c->State == HAL_I2C_STATE_BUSY_RX) {
    uint32_t tmp = 0U;

    tmp = hi2c->XferCount;
    if (tmp > 3U) {
      /* Read data from DR */
      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
      hi2c->XferCount--;
    } else if ((tmp == 2U) || (tmp == 3U)) {
      if (hi2c->XferOptions != I2C_NEXT_FRAME) {
        /* Disable Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

        /* Enable Pos */
        hi2c->Instance->CR1 |= I2C_CR1_POS;
      } else {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;
      }

      /* Disable BUF interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
    } else {
      if (hi2c->XferOptions != I2C_NEXT_FRAME) {
        /* Disable Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
      } else {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;
      }

      /* Disable EVT, BUF and ERR interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);

      /* Read data from DR */
      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
      hi2c->XferCount--;

      hi2c->State         = HAL_I2C_STATE_READY;
      hi2c->PreviousState = I2C_STATE_NONE;

      if (hi2c->Mode == HAL_I2C_MODE_MEM) {
        hi2c->Mode = HAL_I2C_MODE_NONE;
        HAL_I2C_MemRxCpltCallback(hi2c);
      } else {
        hi2c->Mode = HAL_I2C_MODE_NONE;
        HAL_I2C_MasterRxCpltCallback(hi2c);
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  Handle BTF flag for Master receiver
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) {
  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
  uint32_t CurrentXferOptions = hi2c->XferOptions;

  if (hi2c->XferCount == 3U) {
    if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) {
      /* Disable Acknowledge */
      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
    }

    /* Read data from DR */
    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    hi2c->XferCount--;
  } else if (hi2c->XferCount == 2U) {
    /* Prepare next transfer or stop current transfer */
    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) {
      if (CurrentXferOptions != I2C_NEXT_FRAME) {
        /* Disable Acknowledge */
        hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
      } else {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;
      }

      /* Disable EVT and ERR interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
    } else {
      /* Disable EVT and ERR interrupt */
      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);

      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
    }

    /* Read data from DR */
    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    hi2c->XferCount--;

    /* Read data from DR */
    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    hi2c->XferCount--;

    hi2c->State         = HAL_I2C_STATE_READY;
    hi2c->PreviousState = I2C_STATE_NONE;

    if (hi2c->Mode == HAL_I2C_MODE_MEM) {
      hi2c->Mode = HAL_I2C_MODE_NONE;

      HAL_I2C_MemRxCpltCallback(hi2c);
    } else {
      hi2c->Mode = HAL_I2C_MODE_NONE;

      HAL_I2C_MasterRxCpltCallback(hi2c);
    }
  } else {
    /* Read data from DR */
    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    hi2c->XferCount--;
  }
  return HAL_OK;
}

/**
 * @brief  Handle SB flag for Master
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) {
  if (hi2c->Mode == HAL_I2C_MODE_MEM) {
    if (hi2c->EventCount == 0U) {
      /* Send slave address */
      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
    } else {
      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
    }
  } else {
    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) {
      /* Send slave 7 Bits address */
      if (hi2c->State == HAL_I2C_STATE_BUSY_TX) {
        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
      } else {
        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
      }
    } else {
      if (hi2c->EventCount == 0U) {
        /* Send header of slave address */
        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
      } else if (hi2c->EventCount == 1U) {
        /* Send header of slave address */
        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
      }
    }
  }

  return HAL_OK;
}

/**
 * @brief  Handle ADDR flag for Master
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) {
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentMode        = hi2c->Mode;
  uint32_t CurrentXferOptions = hi2c->XferOptions;
  uint32_t Prev_State         = hi2c->PreviousState;

  if (hi2c->State == HAL_I2C_STATE_BUSY_RX) {
    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) {
      /* Clear ADDR flag */
      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
    } else {
      if (hi2c->XferCount == 0U) {
        /* Clear ADDR flag */
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;
      } else if (hi2c->XferCount == 1U) {
        if (CurrentXferOptions == I2C_NO_OPTION_FRAME) {
          /* Disable Acknowledge */
          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) {
            /* Disable Acknowledge */
            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

            /* Clear ADDR flag */
            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
          } else {
            /* Clear ADDR flag */
            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

            /* Generate Stop */
            hi2c->Instance->CR1 |= I2C_CR1_STOP;
          }
        }
        /* Prepare next transfer or stop current transfer */
        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) {
          if (hi2c->XferOptions != I2C_NEXT_FRAME) {
            /* Disable Acknowledge */
            hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
          } else {
            /* Enable Acknowledge */
            hi2c->Instance->CR1 |= I2C_CR1_ACK;
          }

          /* Clear ADDR flag */
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
        } else {
          /* Disable Acknowledge */
          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

          /* Clear ADDR flag */
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

          /* Generate Stop */
          hi2c->Instance->CR1 |= I2C_CR1_STOP;
        }
      } else if (hi2c->XferCount == 2U) {
        if (hi2c->XferOptions != I2C_NEXT_FRAME) {
          /* Enable Pos */
          hi2c->Instance->CR1 |= I2C_CR1_POS;

          /* Clear ADDR flag */
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

          /* Disable Acknowledge */
          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
        } else {
          /* Enable Acknowledge */
          hi2c->Instance->CR1 |= I2C_CR1_ACK;

          /* Clear ADDR flag */
          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
        }

        if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) {
          /* Enable Last DMA bit */
          hi2c->Instance->CR2 |= I2C_CR2_LAST;
        }
      } else {
        /* Enable Acknowledge */
        hi2c->Instance->CR1 |= I2C_CR1_ACK;

        if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) {
          /* Enable Last DMA bit */
          hi2c->Instance->CR2 |= I2C_CR2_LAST;
        }

        /* Clear ADDR flag */
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
      }

      /* Reset Event counter  */
      hi2c->EventCount = 0U;
    }
  } else {
    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
  }

  return HAL_OK;
}

/**
 * @brief  I2C interrupts error process
 * @param  hi2c I2C handle.
 * @retval None
 */
static void I2C_ITError(I2C_HandleTypeDef *hi2c) {
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentState = hi2c->State;

  if ((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) {
    /* keep HAL_I2C_STATE_LISTEN */
    hi2c->PreviousState = I2C_STATE_NONE;
    hi2c->State         = HAL_I2C_STATE_LISTEN;
  } else {
    /* If state is an abort treatment on going, don't change state */
    /* This change will be do later */
    if ((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) {
      hi2c->State = HAL_I2C_STATE_READY;
    }
    hi2c->PreviousState = I2C_STATE_NONE;
    hi2c->Mode          = HAL_I2C_MODE_NONE;
  }

  /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
  hi2c->Instance->CR1 &= ~I2C_CR1_POS;

  /* Abort DMA transfer */
  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) {
    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;

    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) {
      /* Set the DMA Abort callback :
      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;

      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) {
        /* Disable I2C peripheral to prevent dummy data in buffer */
        __HAL_I2C_DISABLE(hi2c);

        hi2c->State = HAL_I2C_STATE_READY;

        /* Call Directly XferAbortCallback function in case of error */
        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
      }
    } else {
      /* Set the DMA Abort callback :
      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;

      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) {
        /* Store Last receive data if any */
        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) {
          /* Read data from DR */
          (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
        }

        /* Disable I2C peripheral to prevent dummy data in buffer */
        __HAL_I2C_DISABLE(hi2c);

        hi2c->State = HAL_I2C_STATE_READY;

        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
      }
    }
  } else if (hi2c->State == HAL_I2C_STATE_ABORT) {
    hi2c->State     = HAL_I2C_STATE_READY;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Store Last receive data if any */
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) {
      /* Read data from DR */
      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    }

    /* Disable I2C peripheral to prevent dummy data in buffer */
    __HAL_I2C_DISABLE(hi2c);

    /* Call the corresponding callback to inform upper layer of End of Transfer */
    HAL_I2C_AbortCpltCallback(hi2c);
  } else {
    /* Store Last receive data if any */
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) {
      /* Read data from DR */
      (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
    }

    /* Call user error callback */
    HAL_I2C_ErrorCallback(hi2c);
  }
  /* STOP Flag is not set after a NACK reception */
  /* So may inform upper layer that listen phase is stopped */
  /* during NACK error treatment */
  if ((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) {
    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
    hi2c->PreviousState = I2C_STATE_NONE;
    hi2c->State         = HAL_I2C_STATE_READY;
    hi2c->Mode          = HAL_I2C_MODE_NONE;

    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
    HAL_I2C_ListenCpltCallback(hi2c);
  }
}

/**
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) {
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentXferOptions = hi2c->XferOptions;

  /* Generate Start condition if first transfer */
  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) {
    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;
  } else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) {
    /* Generate ReStart */
    hi2c->Instance->CR1 |= I2C_CR1_START;
  }

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) {
    return HAL_TIMEOUT;
  }

  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) {
    /* Send slave address */
    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
  }

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  return HAL_OK;
}

/**
 * @brief  Master sends target device address for read request.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) {
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentXferOptions = hi2c->XferOptions;

  /* Enable Acknowledge */
  hi2c->Instance->CR1 |= I2C_CR1_ACK;

  /* Generate Start condition if first transfer */
  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) {
    /* Generate Start */
    hi2c->Instance->CR1 |= I2C_CR1_START;
  } else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) {
    /* Generate ReStart */
    hi2c->Instance->CR1 |= I2C_CR1_START;
  }

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) {
    return HAL_TIMEOUT;
  }

  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) {
    /* Send slave address */
    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
  }

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  return HAL_OK;
}

/**
 * @brief  Master sends target device address followed by internal memory address for write request.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) {
  /* Generate Start */
  hi2c->Instance->CR1 |= I2C_CR1_START;

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) {
    return HAL_TIMEOUT;
  }

  /* Send slave address */
  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  /* Clear ADDR flag */
  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

  /* Wait until TXE flag is set */
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  /* If Memory address size is 8Bit */
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT) {
    /* Send Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
  }
  /* If Memory address size is 16Bit */
  else {
    /* Send MSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);

    /* Wait until TXE flag is set */
    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;
        return HAL_ERROR;
      } else {
        return HAL_TIMEOUT;
      }
    }

    /* Send LSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
  }

  return HAL_OK;
}

/**
 * @brief  Master sends target device address followed by internal memory address for read request.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  DevAddress Target device address: The device 7 bits address value
 *         in datasheet must be shifted to the left before calling the interface
 * @param  MemAddress Internal memory address
 * @param  MemAddSize Size of internal memory address
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) {
  /* Enable Acknowledge */
  hi2c->Instance->CR1 |= I2C_CR1_ACK;

  /* Generate Start */
  hi2c->Instance->CR1 |= I2C_CR1_START;

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) {
    return HAL_TIMEOUT;
  }

  /* Send slave address */
  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  /* Clear ADDR flag */
  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);

  /* Wait until TXE flag is set */
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  /* If Memory address size is 8Bit */
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT) {
    /* Send Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
  }
  /* If Memory address size is 16Bit */
  else {
    /* Send MSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);

    /* Wait until TXE flag is set */
    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) {
      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
        /* Generate Stop */
        hi2c->Instance->CR1 |= I2C_CR1_STOP;
        return HAL_ERROR;
      } else {
        return HAL_TIMEOUT;
      }
    }

    /* Send LSB of Memory Address */
    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
  }

  /* Wait until TXE flag is set */
  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  /* Generate Restart */
  hi2c->Instance->CR1 |= I2C_CR1_START;

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) {
    return HAL_TIMEOUT;
  }

  /* Send slave address */
  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) {
    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) {
      return HAL_ERROR;
    } else {
      return HAL_TIMEOUT;
    }
  }

  return HAL_OK;
}

/**
 * @brief  DMA I2C process complete callback.
 * @param  hdma DMA handle
 * @retval None
 */
static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) {
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentState = hi2c->State;
  uint32_t CurrentMode  = hi2c->Mode;

  if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) {
    /* Disable DMA Request */
    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;

    hi2c->XferCount = 0U;

    /* Enable EVT and ERR interrupt */
    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
  } else {
    /* Disable Acknowledge */
    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

    /* Generate Stop */
    hi2c->Instance->CR1 |= I2C_CR1_STOP;

    /* Disable Last DMA */
    hi2c->Instance->CR2 &= ~I2C_CR2_LAST;

    /* Disable DMA Request */
    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;

    hi2c->XferCount = 0U;

    /* Check if Errors has been detected during transfer */
    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) {
      HAL_I2C_ErrorCallback(hi2c);
    } else {
      hi2c->State = HAL_I2C_STATE_READY;

      if (hi2c->Mode == HAL_I2C_MODE_MEM) {
        hi2c->Mode = HAL_I2C_MODE_NONE;

        HAL_I2C_MemRxCpltCallback(hi2c);
      } else {
        hi2c->Mode = HAL_I2C_MODE_NONE;

        HAL_I2C_MasterRxCpltCallback(hi2c);
      }
    }
  }
}

/**
 * @brief  DMA I2C communication error callback.
 * @param  hdma DMA handle
 * @retval None
 */
static void I2C_DMAError(DMA_HandleTypeDef *hdma) {
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Disable Acknowledge */
  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

  hi2c->XferCount = 0U;

  hi2c->State = HAL_I2C_STATE_READY;
  hi2c->Mode  = HAL_I2C_MODE_NONE;

  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;

  HAL_I2C_ErrorCallback(hi2c);
}

/**
 * @brief DMA I2C communication abort callback
 *        (To be called at end of DMA Abort procedure).
 * @param hdma: DMA handle.
 * @retval None
 */
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) {
  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Disable Acknowledge */
  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;

  hi2c->XferCount = 0U;

  /* Reset XferAbortCallback */
  hi2c->hdmatx->XferAbortCallback = NULL;
  hi2c->hdmarx->XferAbortCallback = NULL;

  /* Check if come from abort from user */
  if (hi2c->State == HAL_I2C_STATE_ABORT) {
    hi2c->State     = HAL_I2C_STATE_READY;
    hi2c->Mode      = HAL_I2C_MODE_NONE;
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;

    /* Disable I2C peripheral to prevent dummy data in buffer */
    __HAL_I2C_DISABLE(hi2c);

    /* Call the corresponding callback to inform upper layer of End of Transfer */
    HAL_I2C_AbortCpltCallback(hi2c);
  } else {
    hi2c->State = HAL_I2C_STATE_READY;
    hi2c->Mode  = HAL_I2C_MODE_NONE;

    /* Disable I2C peripheral to prevent dummy data in buffer */
    __HAL_I2C_DISABLE(hi2c);

    /* Call the corresponding callback to inform upper layer of End of Transfer */
    HAL_I2C_ErrorCallback(hi2c);
  }
}

/**
 * @brief  This function handles I2C Communication Timeout.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  Flag specifies the I2C flag to check.
 * @param  Status The new Flag status (SET or RESET).
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) {
  /* Wait until flag is set */
  while ((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;
        hi2c->Mode          = HAL_I2C_MODE_NONE;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    }
  }

  return HAL_OK;
}

/**
 * @brief  This function handles I2C Communication Timeout for Master addressing phase.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *         the configuration information for I2C module
 * @param  Flag specifies the I2C flag to check.
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) {
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) {
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) {
      /* Generate Stop */
      hi2c->Instance->CR1 |= I2C_CR1_STOP;

      /* Clear AF Flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);

      hi2c->ErrorCode     = HAL_I2C_ERROR_AF;
      hi2c->PreviousState = I2C_STATE_NONE;
      hi2c->State         = HAL_I2C_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      return HAL_ERROR;
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) {
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) {
      return HAL_ERROR;
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) {
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) {
      return HAL_ERROR;
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY) {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
        hi2c->PreviousState = I2C_STATE_NONE;
        hi2c->State         = HAL_I2C_STATE_READY;

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);

        return HAL_TIMEOUT;
      }
    }
  }
  return HAL_OK;
}

/**
 * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) {
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) {
      return HAL_ERROR;
    }

    /* Check for the Timeout */
    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
      hi2c->PreviousState = I2C_STATE_NONE;
      hi2c->State         = HAL_I2C_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      return HAL_TIMEOUT;
    }
  }
  return HAL_OK;
}

/**
 * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @param  Timeout Timeout duration
 * @param  Tickstart Tick start value
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) {

  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) {
    /* Check if a STOPF is detected */
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) {
      /* Clear STOP Flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);

      hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
      hi2c->PreviousState = I2C_STATE_NONE;
      hi2c->State         = HAL_I2C_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      return HAL_ERROR;
    }

    /* Check for the Timeout */
    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) {
      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
      hi2c->State = HAL_I2C_STATE_READY;

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);

      return HAL_TIMEOUT;
    }
  }
  return HAL_OK;
}

/**
 * @brief  This function handles Acknowledge failed detection during an I2C Communication.
 * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
 *                the configuration information for the specified I2C.
 * @retval HAL status
 */
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) {
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) {
    /* Clear NACKF Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);

    hi2c->ErrorCode     = HAL_I2C_ERROR_AF;
    hi2c->PreviousState = I2C_STATE_NONE;
    hi2c->State         = HAL_I2C_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);

    return HAL_ERROR;
  }
  return HAL_OK;
}
/**
 * @}
 */

#endif /* HAL_I2C_MODULE_ENABLED */

/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_iwdg.c
  * @author  MCD Application Team
  * @brief   IWDG HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the Independent Watchdog (IWDG) peripheral:
  *           + Initialization and Start functions
  *           + IO operation functions
  *
  @verbatim
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM5 CH4 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts downcounting.
      (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) wait for status flags to be reset"

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

#ifdef HAL_IWDG_MODULE_ENABLED
/** @defgroup IWDG IWDG
 * @brief IWDG HAL module driver.
 * @{
 */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
 * @{
 */
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
   higher prescaler (256), and according to HSI variation, we need to wait at
   least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @addtogroup IWDG_Exported_Functions
 * @{
 */

/** @addtogroup IWDG_Exported_Functions_Group1
  *  @brief    Initialization and Start functions.
  *
@verbatim
 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

@endverbatim
  * @{
  */

/**
 * @brief  Initialize the IWDG according to the specified parameters in the
 *         IWDG_InitTypeDef and start watchdog. Before exiting function,
 *         watchdog is refreshed in order to have correct time base.
 * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
 *                the configuration information for the specified IWDG module.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) {
  uint32_t tickstart;

  /* Check the IWDG handle allocation */
  if (hiwdg == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));

  /* Enable IWDG. LSI is turned on automaticaly */
  __HAL_IWDG_START(hiwdg);

  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
  IWDG_ENABLE_WRITE_ACCESS(hiwdg);

  /* Write to IWDG registers the Prescaler & Reload values to work with */
  hiwdg->Instance->PR  = hiwdg->Init.Prescaler;
  hiwdg->Instance->RLR = hiwdg->Init.Reload;

  /* Check pending flag, if previous update not done, return timeout */
  tickstart = HAL_GetTick();

  /* Wait for register to be updated */
  while (hiwdg->Instance->SR != RESET) {
    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) {
      return HAL_TIMEOUT;
    }
  }

  /* Reload IWDG counter with value defined in the reload register */
  __HAL_IWDG_RELOAD_COUNTER(hiwdg);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @addtogroup IWDG_Exported_Functions_Group2
  *  @brief   IO operation functions
  *
@verbatim
 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

@endverbatim
  * @{
  */

/**
 * @brief  Refresh the IWDG.
 * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
 *                the configuration information for the specified IWDG module.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) {
  /* Reload IWDG counter with value defined in the reload register */
  __HAL_IWDG_RELOAD_COUNTER(hiwdg);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_IWDG_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_pwr.c
 * @author  MCD Application Team
 * @brief   PWR HAL module driver.
 *
 *          This file provides firmware functions to manage the following
 *          functionalities of the Power Controller (PWR) peripheral:
 *           + Initialization/de-initialization functions
 *           + Peripheral Control functions
 *
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup PWR PWR
 * @brief    PWR HAL module driver
 * @{
 */

#ifdef HAL_PWR_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/

/** @defgroup PWR_Private_Constants PWR Private Constants
 * @{
 */

/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
 * @{
 */
#define PVD_MODE_IT      0x00010000U
#define PVD_MODE_EVT     0x00020000U
#define PVD_RISING_EDGE  0x00000001U
#define PVD_FALLING_EDGE 0x00000002U
/**
 * @}
 */

/** @defgroup PWR_register_alias_address PWR Register alias address
 * @{
 */
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET        (PWR_BASE - PERIPH_BASE)
#define PWR_CR_OFFSET     0x00U
#define PWR_CSR_OFFSET    0x04U
#define PWR_CR_OFFSET_BB  (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/**
 * @}
 */

/** @defgroup PWR_CR_register_alias PWR CR Register alias address
 * @{
 */
/* --- CR Register ---*/
/* Alias word address of LPSDSR bit */
#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
#define CR_LPSDSR_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))

/* Alias word address of DBP bit */
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
#define CR_DBP_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))

/* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
#define CR_PVDE_BB      ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))

/**
 * @}
 */

/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
 * @{
 */

/* --- CSR Register ---*/
/* Alias word address of EWUP1 bit */
#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
/**
 * @}
 */

/**
 * @}
 */

/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup PWR_Private_Functions PWR Private Functions
 * brief   WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
 * @{
 */
static void PWR_OverloadWfe(void);

/* Private functions ---------------------------------------------------------*/
__NOINLINE
static void PWR_OverloadWfe(void) {
  __asm volatile("wfe");
  __asm volatile("nop");
}

/**
 * @}
 */

/** @defgroup PWR_Exported_Functions PWR Exported Functions
 * @{
 */

/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief   Initialization and de-initialization functions
  *
@verbatim
 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

@endverbatim
  * @{
  */

/**
 * @brief  Deinitializes the PWR peripheral registers to their default reset values.
 * @retval None
 */
void HAL_PWR_DeInit(void) {
  __HAL_RCC_PWR_FORCE_RESET();
  __HAL_RCC_PWR_RELEASE_RESET();
}

/**
 * @brief  Enables access to the backup domain (RTC registers, RTC
 *         backup data registers ).
 * @note   If the HSE divided by 128 is used as the RTC clock, the
 *         Backup Domain Access should be kept enabled.
 * @retval None
 */
void HAL_PWR_EnableBkUpAccess(void) {
  /* Enable access to RTC and backup registers */
  *(__IO uint32_t *)CR_DBP_BB = (uint32_t)ENABLE;
}

/**
 * @brief  Disables access to the backup domain (RTC registers, RTC
 *         backup data registers).
 * @note   If the HSE divided by 128 is used as the RTC clock, the
 *         Backup Domain Access should be kept enabled.
 * @retval None
 */
void HAL_PWR_DisableBkUpAccess(void) {
  /* Disable access to RTC and backup registers */
  *(__IO uint32_t *)CR_DBP_BB = (uint32_t)DISABLE;
}

/**
 * @}
 */

/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
  * @brief    Low Power modes configuration functions
  *
@verbatim
 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).

      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
          forced in input pull-down configuration and is active on rising edges.
      (+) There is one WakeUp pin:
          WakeUp Pin 1 on PA.00.

    [..]

    *** Low Power modes configuration ***
    =====================================
     [..]
      The device features 3 low-power modes:
      (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
                      NVIC, SysTick, etc. are kept running
      (+) Stop mode: All clocks are stopped
      (+) Standby mode: 1.8V domain powered off


   *** Sleep mode ***
   ==================
    [..]
      (+) Entry:
          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
              functions with
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) Exit:
        (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) can wake up the device from Sleep mode.
        (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
           (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
           (+++) Any EXTI Line (Internal or External) configured in Event mode

   *** Stop mode ***
   =================
    [..]
      The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
      clock gating. The voltage regulator can be configured either in normal or low-power mode.
      In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
      oscillators are disabled. SRAM and register contents are preserved.
      In Stop mode, all I/O pins keep the same state as in Run mode.

      (+) Entry:
           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
             function with:
          (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
          (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
      (+) Exit:
          (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
          (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.

   *** Standby mode ***
   ====================
     [..]
      The Standby mode allows to achieve the lowest power consumption. It is based on the
      Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
      consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
      switched off. SRAM and register contents are lost except for registers in the Backup domain
      and Standby circuitry

      (+) Entry:
        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (+) Exit:
        (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
             NRSTpin, IWDG Reset

   *** Auto-wakeup (AWU) from low-power mode ***
       =============================================
       [..]

       (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
           without depending on an external interrupt (Auto-wakeup mode).

       (+) RTC auto-wakeup (AWU) from the Stop and Standby modes

           (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
                configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

   *** PWR Workarounds linked to Silicon Limitation ***
       ====================================================
       [..]
       Below the list of all silicon limitations known on STM32F1xx prouct.

       (#)Workarounds Implemented inside PWR HAL Driver
          (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function

@endverbatim
  * @{
  */

/**
 * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
 * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
 *         information for the PVD.
 * @note   Refer to the electrical characteristics of your device datasheet for
 *         more details about the voltage threshold corresponding to each
 *         detection level.
 * @retval None
 */
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) {
  /* Check the parameters */
  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));

  /* Set PLS[7:5] bits according to PVDLevel value */
  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);

  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
  __HAL_PWR_PVD_EXTI_DISABLE_IT();
  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();

  /* Configure interrupt mode */
  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) {
    __HAL_PWR_PVD_EXTI_ENABLE_IT();
  }

  /* Configure event mode */
  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) {
    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
  }

  /* Configure the edge */
  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) {
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
  }

  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) {
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
  }
}

/**
 * @brief  Enables the Power Voltage Detector(PVD).
 * @retval None
 */
void HAL_PWR_EnablePVD(void) {
  /* Enable the power voltage detector */
  *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)ENABLE;
}

/**
 * @brief  Disables the Power Voltage Detector(PVD).
 * @retval None
 */
void HAL_PWR_DisablePVD(void) {
  /* Disable the power voltage detector */
  *(__IO uint32_t *)CR_PVDE_BB = (uint32_t)DISABLE;
}

/**
 * @brief Enables the WakeUp PINx functionality.
 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
 *        This parameter can be one of the following values:
 *           @arg PWR_WAKEUP_PIN1
 * @retval None
 */
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) {
  /* Check the parameter */
  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  /* Enable the EWUPx pin */
  *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
}

/**
 * @brief Disables the WakeUp PINx functionality.
 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
 *        This parameter can be one of the following values:
 *           @arg PWR_WAKEUP_PIN1
 * @retval None
 */
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) {
  /* Check the parameter */
  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  /* Disable the EWUPx pin */
  *(__IO uint32_t *)CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
}

/**
 * @brief Enters Sleep mode.
 * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
 * @param Regulator: Regulator state as no effect in SLEEP mode -  allows to support portability from legacy software
 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
 *           When WFI entry is used, tick interrupt have to be disabled if not desired as
 *           the interrupt wake up source.
 *           This parameter can be one of the following values:
 *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
 *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
 * @retval None
 */
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) {
  /* Check the parameters */
  /* No check on Regulator because parameter not used in SLEEP mode */
  /* Prevent unused argument(s) compilation warning */
  UNUSED(Regulator);

  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));

  /* Clear SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

  /* Select SLEEP mode entry -------------------------------------------------*/
  if (SLEEPEntry == PWR_SLEEPENTRY_WFI) {
    /* Request Wait For Interrupt */
    __WFI();
  } else {
    /* Request Wait For Event */
    __SEV();
    __WFE();
    __WFE();
  }
}

/**
 * @brief Enters Stop mode.
 * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
 * @note  When exiting Stop mode by using an interrupt or a wakeup event,
 *        HSI RC oscillator is selected as system clock.
 * @note  When the voltage regulator operates in low power mode, an additional
 *         startup delay is incurred when waking up from Stop mode.
 *         By keeping the internal regulator ON during Stop mode, the consumption
 *         is higher although the startup time is reduced.
 * @param Regulator: Specifies the regulator state in Stop mode.
 *          This parameter can be one of the following values:
 *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
 *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
 *          This parameter can be one of the following values:
 *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
 *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
 * @retval None
 */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) {
  /* Check the parameters */
  assert_param(IS_PWR_REGULATOR(Regulator));
  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));

  /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
  CLEAR_BIT(PWR->CR, PWR_CR_PDDS);

  /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
  MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);

  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

  /* Select Stop mode entry --------------------------------------------------*/
  if (STOPEntry == PWR_STOPENTRY_WFI) {
    /* Request Wait For Interrupt */
    __WFI();
  } else {
    /* Request Wait For Event */
    __SEV();
    PWR_OverloadWfe(); /* WFE redefine locally */
    PWR_OverloadWfe(); /* WFE redefine locally */
  }
  /* Reset SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}

/**
 * @brief Enters Standby mode.
 * @note  In Standby mode, all I/O pins are high impedance except for:
 *          - Reset pad (still available)
 *          - TAMPER pin if configured for tamper or calibration out.
 *          - WKUP pin (PA0) if enabled.
 * @retval None
 */
void HAL_PWR_EnterSTANDBYMode(void) {
  /* Select Standby mode */
  SET_BIT(PWR->CR, PWR_CR_PDDS);

  /* Set SLEEPDEEP bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));

  /* This option is used to ensure that store operations are completed */
#if defined(__CC_ARM)
  __force_stores();
#endif
  /* Request Wait For Interrupt */
  __WFI();
}

/**
 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
 *       re-enters SLEEP mode when an interruption handling is over.
 *       Setting this bit is useful when the processor is expected to run only on
 *       interruptions handling.
 * @retval None
 */
void HAL_PWR_EnableSleepOnExit(void) {
  /* Set SLEEPONEXIT bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}

/**
 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
 *       re-enters SLEEP mode when an interruption handling is over.
 * @retval None
 */
void HAL_PWR_DisableSleepOnExit(void) {
  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}

/**
 * @brief Enables CORTEX M3 SEVONPEND bit.
 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
 *       WFE to wake up when an interrupt moves from inactive to pended.
 * @retval None
 */
void HAL_PWR_EnableSEVOnPend(void) {
  /* Set SEVONPEND bit of Cortex System Control Register */
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}

/**
 * @brief Disables CORTEX M3 SEVONPEND bit.
 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
 *       WFE to wake up when an interrupt moves from inactive to pended.
 * @retval None
 */
void HAL_PWR_DisableSEVOnPend(void) {
  /* Clear SEVONPEND bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}

/**
 * @brief  This function handles the PWR PVD interrupt request.
 * @note   This API should be called under the PVD_IRQHandler().
 * @retval None
 */
void HAL_PWR_PVD_IRQHandler(void) {
  /* Check PWR exti flag */
  if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) {
    /* PWR PVD interrupt user callback */
    HAL_PWR_PVDCallback();

    /* Clear PWR Exti pending bit */
    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
  }
}

/**
 * @brief  PWR PVD interrupt callback
 * @retval None
 */
__weak void HAL_PWR_PVDCallback(void) {
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_PWR_PVDCallback could be implemented in the user file
   */
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_PWR_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_rcc.c
  * @author  MCD Application Team
  * @brief   RCC HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the Reset and Clock Control (RCC) peripheral:
  *           + Initialization and de-initialization functions
  *           + Peripheral Control functions
  *
  @verbatim
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
      and all peripherals are off except internal SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.
    [..] Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals whose clocks are not
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© COPYRIGHT(c) 2016 STMicroelectronics

  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
*/

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup RCC RCC
 * @brief RCC HAL module driver
 * @{
 */

#ifdef HAL_RCC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCC_Private_Constants RCC Private Constants
 * @{
 */
/**
 * @}
 */
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCC_Private_Macros RCC Private Macros
 * @{
 */

#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT    GPIOA
#define MCO1_PIN          GPIO_PIN_8

/**
 * @}
 */

/* Private variables ---------------------------------------------------------*/
/** @defgroup RCC_Private_Variables RCC Private Variables
 * @{
 */
/**
 * @}
 */

/* Private function prototypes -----------------------------------------------*/

/* Exported functions --------------------------------------------------------*/

/** @defgroup RCC_Exported_Functions RCC Exported Functions
 * @{
 */

/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
  *  @brief    Initialization and Configuration functions
  *
  @verbatim
  ===============================================================================
           ##### Initialization and de-initialization functions #####
  ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
      and APB2).

    [..] Internal/external clock and PLL configuration
      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
          the PLL as System clock source.
      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
          clock source.

      (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
          clock source), the System clocks automatically switched to HSI and an interrupt
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
          (Non-Maskable Interrupt) exception vector.

      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x

    [..] System, AHB and APB buses clocks configuration
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
          HSE and PLL.
          The AHB clock (HCLK) is derived from System clock through configurable
          prescaler and used to clock the CPU, memory and peripherals mapped
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
          from AHB clock through configurable prescalers and used to clock
          the peripherals mapped on these buses. You can use
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
              divided by 128.
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
          (+@) IWDG clock which is always the LSI clock.

      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
  @endverbatim
  * @{
  */

/*
  Additional consideration on the SYSCLK based on Latency settings:
        +-----------------------------------------------+
        | Latency       | SYSCLK clock frequency (MHz)  |
        |---------------|-------------------------------|
        |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
        |---------------|-------------------------------|
        |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
        |---------------|-------------------------------|
        |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
        +-----------------------------------------------+
  */

/**
 * @brief  Resets the RCC clock configuration to the default reset state.
 * @note   The default reset state of the clock configuration is given below:
 *            - HSI ON and used as system clock source
 *            - HSE, PLL, PLL2 and PLL3 are OFF
 *            - AHB, APB1 and APB2 prescaler set to 1.
 *            - CSS and MCO1 OFF
 *            - All interrupts disabled
 *            - All flags are cleared
 * @note   This function does not modify the configuration of the
 *            - Peripheral clocks
 *            - LSI, LSE and RTC clocks
 * @retval HAL_StatusTypeDef
 */
HAL_StatusTypeDef HAL_RCC_DeInit(void) {
  uint32_t tickstart;

  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Set HSION bit */
  SET_BIT(RCC->CR, RCC_CR_HSION);

  /* Wait till HSI is ready */
  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) {
    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }

  /* Set HSITRIM bits to the reset value */
  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));

  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Reset CFGR register */
  CLEAR_REG(RCC->CFGR);

  /* Wait till clock switch is ready */
  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) {
    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HSI_VALUE;

  /* Adapt Systick interrupt period */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
    return HAL_ERROR;
  }

  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Second step is to clear PLLON bit */
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);

  /* Wait till PLL is disabled */
  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) {
    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }

  /* Ensure to reset PLLSRC and PLLMUL bits */
  CLEAR_REG(RCC->CFGR);

  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Reset HSEON & CSSON bits */
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);

  /* Wait till HSE is disabled */
  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) {
    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }

  /* Reset HSEBYP bit */
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

#if defined(RCC_PLL2_SUPPORT)
  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Clear PLL2ON bit */
  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);

  /* Wait till PLL2 is disabled */
  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET) {
    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }
#endif /* RCC_PLL2_SUPPORT */

#if defined(RCC_PLLI2S_SUPPORT)
  /* Get Start Tick */
  tickstart = HAL_GetTick();

  /* Clear PLL3ON bit */
  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);

  /* Wait till PLL3 is disabled */
  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET) {
    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
      return HAL_TIMEOUT;
    }
  }
#endif /* RCC_PLLI2S_SUPPORT */

#if defined(RCC_CFGR2_PREDIV1)
  /* Reset CFGR2 register */
  CLEAR_REG(RCC->CFGR2);
#endif /* RCC_CFGR2_PREDIV1 */

  /* Reset all CSR flags */
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);

  /* Disable all interrupts */
  CLEAR_REG(RCC->CIR);

  return HAL_OK;
}

/**
 * @brief  Initializes the RCC Oscillators according to the specified parameters in the
 *         RCC_OscInitTypeDef.
 * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
 *         contains the configuration information for the RCC Oscillators.
 * @note   The PLL is not disabled when used as system clock.
 * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
 * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
 *         supported by this macro. User should request a transition to LSE Off
 *         first and then LSE On or LSE Bypass.
 * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
 *         supported by this macro. User should request a transition to HSE Off
 *         first and then HSE On or HSE Bypass.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
  uint32_t tickstart = 0U;

  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) {
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) ||
        ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) {
      /* When HSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) {
        return HAL_ERROR;
      }
      /* Otherwise, just the calibration is allowed */
      else {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
      }
    } else {
      /* Check the HSI State */
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
      } else {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till HSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/

  /*------------------------------ LSE Configuration -------------------------*/

#if defined(RCC_CR_PLL2ON)
  /*-------------------------------- PLL2 Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) {
    /* This bit can not be cleared if the PLL2 clock is used indirectly as system
      clock (i.e. it is used as PLL clock entry that is used as system clock). */
    if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) &&
        ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
      return HAL_ERROR;
    } else {
      if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON) {
        /* Check the parameters */
        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));

        /* Prediv2 can be written only when the PLLI2S is disabled. */
        /* Return an error only if new value is different from the programmed value */
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value)) {
          return HAL_ERROR;
        }

        /* Disable the main PLL2. */
        __HAL_RCC_PLL2_DISABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL2 is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }

        /* Configure the HSE prediv2 factor --------------------------------*/
        __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);

        /* Configure the main PLL2 multiplication factors. */
        __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);

        /* Enable the main PLL2. */
        __HAL_RCC_PLL2_ENABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL2 is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) {
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      } else {
        /* Set PREDIV1 source to HSE */
        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);

        /* Disable the main PLL2. */
        __HAL_RCC_PLL2_DISABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL2 is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      }
    }
  }

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) {
        /* Check the parameters */
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }

        /* Configure the HSE prediv factor --------------------------------*/
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) {
          /* Check the parameter */
          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
#if defined(RCC_CFGR2_PREDIV1SRC)
          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));

          /* Set PREDIV1 source */
          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */

          /* Set PREDIV1 Value */
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
        }

        /* Configure the main PLL clock source and multiplication factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      } else {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      }
    } else {
      return HAL_ERROR;
    }
  }

  return HAL_OK;
}

/**
 * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
 *         parameters in the RCC_ClkInitStruct.
 * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
 *         contains the configuration information for the RCC peripheral.
 * @param  FLatency FLASH Latency
 *          The value of this parameter depend on device used within the same series
 * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
 *
 * @note   The HSI is used (enabled by hardware) as system clock source after
 *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
 *         of failure of the HSE used directly or indirectly as system clock
 *         (if the Clock Security System CSS is enabled).
 *
 * @note   A switch from one clock source to another occurs only if the target
 *         clock source is ready (clock stable after start-up delay or PLL locked).
 *         If a clock source which is not yet ready is selected, the switch will
 *         occur when the clock source will be ready.
 *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
 *         currently used as system clock source.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) {
  uint32_t tickstart = 0U;

  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != NULL);
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
  assert_param(IS_FLASH_LATENCY(FLatency));

  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  must be correctly programmed according to the frequency of the CPU clock
    (HCLK) of the device. */

#if defined(FLASH_ACR_LATENCY)
  /* Increasing the number of wait states because of higher CPU frequency */
  if (FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) {
      return HAL_ERROR;
    }
  }

#endif /* FLASH_ACR_LATENCY */
  /*-------------------------- HCLK Configuration --------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) {
    /* Set the highest APBx dividers in order to ensure that we do not go through
    a non-spec phase whatever we decrease or increase HCLK. */
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
    }

    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
    }

    /* Set the new HCLK clock divider */
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) {
        return HAL_ERROR;
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) {
        return HAL_ERROR;
      }
    }
    /* HSI is selected as System Clock Source */
    else {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) {
        return HAL_ERROR;
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);

    /* Get Start Tick */
    tickstart = HAL_GetTick();

    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) {
        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
          return HAL_TIMEOUT;
        }
      }
    } else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
          return HAL_TIMEOUT;
        }
      }
    } else {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) {
        if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) {
          return HAL_TIMEOUT;
        }
      }
    }
  }
#if defined(FLASH_ACR_LATENCY)
  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) {
      return HAL_ERROR;
    }
  }
#endif /* FLASH_ACR_LATENCY */

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];

  /* Configure the source of time base considering new system clocks settings*/
  HAL_InitTick(TICK_INT_PRIORITY);

  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
  *  @brief   RCC clocks control functions
  *
  @verbatim
  ===============================================================================
                  ##### Peripheral Control functions #####
  ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

  @endverbatim
  * @{
  */

/**
  * @brief  Selects the clock source to output on MCO pin.
  * @note   MCO pin should be configured in alternate function mode.
  * @param  RCC_MCOx specifies the output direction for the clock source.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
  * @param  RCC_MCOSource specifies the clock source to output.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
  @if STM32F105xC
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE      XT1 external 3-25 MHz oscillator clock selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
  @endif
  @if STM32F107xC
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected as MCO source
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
  @endif
  * @param  RCC_MCODiv specifies the MCO DIV.
  *          This parameter can be one of the following values:
  *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
  * @retval None
  */
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) {
  GPIO_InitTypeDef gpio = {0U};

  /* Check the parameters */
  assert_param(IS_RCC_MCO(RCC_MCOx));
  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));

  /* Prevent unused argument(s) compilation warning */
  UNUSED(RCC_MCOx);
  UNUSED(RCC_MCODiv);

  /* Configure the MCO1 pin in alternate function mode */
  gpio.Mode  = GPIO_MODE_AF_PP;
  gpio.Speed = GPIO_SPEED_FREQ_HIGH;
  gpio.Pull  = GPIO_NOPULL;
  gpio.Pin   = MCO1_PIN;

  /* MCO1 Clock Enable */
  MCO1_CLK_ENABLE();

  HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);

  /* Configure the MCO clock source */
  __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
}

/**
 * @brief  Enables the Clock Security System.
 * @note   If a failure is detected on the HSE oscillator clock, this oscillator
 *         is automatically disabled and an interrupt is generated to inform the
 *         software about the failure (Clock Security System Interrupt, CSSI),
 *         allowing the MCU to perform rescue operations. The CSSI is linked to
 *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
 * @retval None
 */
void HAL_RCC_EnableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)ENABLE; }

/**
 * @brief  Disables the Clock Security System.
 * @retval None
 */
void HAL_RCC_DisableCSS(void) { *(__IO uint32_t *)RCC_CR_CSSON_BB = (uint32_t)DISABLE; }

/**
 * @brief  Returns the SYSCLK frequency
 * @note   The system frequency computed by this function is not the real
 *         frequency in the chip. It is calculated based on the predefined
 *         constant and the selected clock source:
 * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
 * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
 *           divided by PREDIV factor(**)
 * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
 *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
 * @note     (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
 *               8 MHz) but the real value may vary depending on the variations
 *               in voltage and temperature.
 * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
 *                8 MHz), user has to ensure that HSE_VALUE is same as the real
 *                frequency of the crystal used. Otherwise, this function may
 *                have wrong result.
 *
 * @note   The result of this function could be not correct when using fractional
 *         value for HSE crystal.
 *
 * @note   This function can be used by the user application to compute the
 *         baud-rate for the communication peripherals or configure other parameters.
 *
 * @note   Each time SYSCLK changes, this function must be called to update the
 *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
 *
 * @retval SYSCLK frequency
 */
uint32_t HAL_RCC_GetSysClockFreq(void) {
#if defined(RCC_CFGR2_PREDIV1SRC)
  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
#if defined(RCC_CFGR2_PREDIV1)
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
  const uint8_t aPredivFactorTable[2] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/

#endif
  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
  uint32_t sysclockfreq = 0U;
#if defined(RCC_CFGR2_PREDIV1SRC)
  uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/

  tmpreg = RCC->CFGR;

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS) {
  case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
  {
    sysclockfreq = HSE_VALUE;
    break;
  }
  case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
  {
    pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
    if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
#if defined(RCC_CFGR2_PREDIV1)
      prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
      prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
#endif /*RCC_CFGR2_PREDIV1*/
#if defined(RCC_CFGR2_PREDIV1SRC)

      if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) {
        /* PLL2 selected as Prediv1 source */
        /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
        prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
        pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
        pllclk  = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
      } else {
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
        pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
      }

      /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
      /* In this case need to divide pllclk by 2 */
      if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) {
        pllclk = pllclk / 2;
      }
#else
      /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
      pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
#endif /*RCC_CFGR2_PREDIV1SRC*/
    } else {
      /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
      pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
    }
    sysclockfreq = pllclk;
    break;
  }
  case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
  default:                          /* HSI used as system clock */
  {
    sysclockfreq = HSI_VALUE;
    break;
  }
  }
  return sysclockfreq;
}

/**
 * @brief  Returns the HCLK frequency
 * @note   Each time HCLK changes, this function must be called to update the
 *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
 *
 * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 *         and updated within this function
 * @retval HCLK frequency
 */
uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; }

/**
 * @brief  Returns the PCLK1 frequency
 * @note   Each time PCLK1 changes, this function must be called to update the
 *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
 * @retval PCLK1 frequency
 */
uint32_t HAL_RCC_GetPCLK1Freq(void) {
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}

/**
 * @brief  Returns the PCLK2 frequency
 * @note   Each time PCLK2 changes, this function must be called to update the
 *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
 * @retval PCLK2 frequency
 */
uint32_t HAL_RCC_GetPCLK2Freq(void) {
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}

/**
 * @brief  Configures the RCC_OscInitStruct according to the internal
 * RCC configuration registers.
 * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
 * will be configured.
 * @retval None
 */
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) {
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);

  /* Set all possible values for the Oscillator type parameter ---------------*/
  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;

#if defined(RCC_CFGR2_PREDIV1SRC)
  /* Get the Prediv1 source --------------------------------------------------*/
  RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
#endif /* RCC_CFGR2_PREDIV1SRC */

  /* Get the HSE configuration -----------------------------------------------*/
  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) {
    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
  } else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) {
    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
  } else {
    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
  }
  RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();

  /* Get the HSI configuration -----------------------------------------------*/
  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) {
    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
  } else {
    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
  }

  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);

  /* Get the LSE configuration -----------------------------------------------*/
  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) {
    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
  } else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
  } else {
    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
  }

  /* Get the LSI configuration -----------------------------------------------*/
  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) {
    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
  } else {
    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
  }

  /* Get the PLL configuration -----------------------------------------------*/
  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) {
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
  } else {
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
  }
  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
  RCC_OscInitStruct->PLL.PLLMUL    = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
#if defined(RCC_CR_PLL2ON)
  /* Get the PLL2 configuration -----------------------------------------------*/
  if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON) {
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
  } else {
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
  }
  RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
  RCC_OscInitStruct->PLL2.PLL2MUL         = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
#endif /* RCC_CR_PLL2ON */
}

/**
 * @brief  Get the RCC_ClkInitStruct according to the internal
 * RCC configuration registers.
 * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
 * contains the current clock configuration.
 * @param  pFLatency Pointer on the Flash Latency.
 * @retval None
 */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) {
  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != NULL);
  assert_param(pFLatency != NULL);

  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);

#if defined(FLASH_ACR_LATENCY)
  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
#else
  /* For VALUE lines devices, only LATENCY_0 can be set*/
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
#endif
}

/**
 * @brief This function handles the RCC CSS interrupt request.
 * @note This API should be called under the NMI_Handler().
 * @retval None
 */
void HAL_RCC_NMI_IRQHandler(void) {
  /* Check RCC CSSF flag  */
  if (__HAL_RCC_GET_IT(RCC_IT_CSS)) {
    /* RCC Clock Security System interrupt user callback */
    HAL_RCC_CSSCallback();

    /* Clear RCC CSS pending bit */
    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
  }
}

/**
 * @brief  RCC Clock Security System interrupt callback
 * @retval none
 */
__weak void HAL_RCC_CSSCallback(void) {
  /* NOTE : This function Should not be modified, when the callback is needed,
    the HAL_RCC_CSSCallback could be implemented in the user file
    */
}

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_RCC_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_rcc_ex.c
 * @author  MCD Application Team
 * @brief   Extended RCC HAL module driver.
 *          This file provides firmware functions to manage the following
 *          functionalities RCC extension peripheral:
 *           + Extended Peripheral Control functions
 *
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2016 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

#ifdef HAL_RCC_MODULE_ENABLED

/** @defgroup RCCEx RCCEx
 * @brief RCC Extension HAL module driver.
 * @{
 */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
 * @{
 */
/**
 * @}
 */

/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
 * @{
 */
/**
 * @}
 */

/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
 * @{
 */

/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
  *  @brief  Extended Peripheral Control functions
  *
@verbatim
 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

@endverbatim
  * @{
  */

/**
 * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
 *         RCC_PeriphCLKInitTypeDef.
 * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
 *         contains the configuration information for the Extended Peripherals clocks(RTC clock).
 *
 * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
 *         the RTC clock source; in this case the Backup domain will be reset in
 *         order to modify the RTC Clock source, as consequence RTC registers (including
 *         the backup registers) are set to their reset values.
 *
 * @note   In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
 *         one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
 *         manually disable it.
 *
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
  uint32_t tickstart = 0U, temp_reg = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t pllactive = 0U;
#endif /* STM32F105xC || STM32F107xC */

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) {
    /* check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    FlagStatus pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
      __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();

      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
          return HAL_TIMEOUT;
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) {
      /* Store the content of BDCR register before the reset of Backup Domain */
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
      __HAL_RCC_BACKUPRESET_RELEASE();
      /* Restore the Content of BDCR register */
      RCC->BDCR = temp_reg;

      /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) {
        /* Get Start Tick */
        tickstart = HAL_GetTick();

        /* Wait till LSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
            return HAL_TIMEOUT;
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET) {
      __HAL_RCC_PWR_CLK_DISABLE();
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
  }

#if defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ I2S2 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) {
    /* Check the parameters */
    assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));

    /* Configure the I2S2 clock source */
    __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
  }

  /*------------------------------ I2S3 Configuration ------------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) {
    /* Check the parameters */
    assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));

    /* Configure the I2S3 clock source */
    __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
  }

  /*------------------------------ PLL I2S Configuration ----------------------*/
  /* Check that PLLI2S need to be enabled */
  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
    /* Update flag to indicate that PLL I2S should be active */
    pllactive = 1;
  }

  /* Check if PLL I2S need to be enabled */
  if (pllactive == 1) {
    /* Enable PLL I2S only if not active */
    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) {
      /* Check the parameters */
      assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
      assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));

      /* Prediv2 can be written only when the PLL2 is disabled. */
      /* Return an error only if new value is different from the programmed value */
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) {
        return HAL_ERROR;
      }

      /* Configure the HSE prediv2 factor --------------------------------*/
      __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);

      /* Configure the main PLLI2S multiplication factors. */
      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);

      /* Enable the main PLLI2S. */
      __HAL_RCC_PLLI2S_ENABLE();

      /* Get Start Tick*/
      tickstart = HAL_GetTick();

      /* Wait till PLLI2S is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
        if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
          return HAL_TIMEOUT;
        }
      }
    } else {
      /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) {
        return HAL_ERROR;
      }
    }
  }
#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));

    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
}

/**
 * @brief  Get the PeriphClkInit according to the internal
 * RCC configuration registers.
 * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
 *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
 * @retval None
 */
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) {
  uint32_t srcclk = 0U;

  /* Set all possible values for the extended clock type parameter------------*/
  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;

  /* Get the RTC configuration -----------------------------------------------*/
  srcclk = __HAL_RCC_GET_RTC_SOURCE();
  /* Source clock is LSE or LSI*/
  PeriphClkInit->RTCClockSelection = srcclk;

  /* Get the ADC clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();

#if defined(STM32F105xC) || defined(STM32F107xC)
  /* Get the I2S2 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
  PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();

  /* Get the I2S3 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
  PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();

#endif /* STM32F105xC || STM32F107xC */

#if defined(STM32F103xE) || defined(STM32F103xG)
  /* Get the I2S2 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
  PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;

  /* Get the I2S3 clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
  PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;

#endif /* STM32F103xE || STM32F103xG */

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  /* Get the USB clock configuration -----------------------------------------*/
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
}

/**
  * @brief  Returns the peripheral clock frequency
  * @note   Returns 0 if peripheral clock is unknown
  * @param  PeriphClk Peripheral clock identifier
  *         This parameter can be one of the following values:
  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
  @if STM32F103xE
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  @endif
  @if STM32F103xG
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  @endif
  @if STM32F105xC
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  @if STM32F107xC
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  @if STM32F102xx
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  @if STM32F103xx
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) {
#if defined(STM32F105xC) || defined(STM32F107xC)
  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};

  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
  uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  const uint8_t aPredivFactorTable[2]  = {1, 2};

  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
  uint32_t temp_reg = 0U, frequency = 0U;

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));

  switch (PeriphClk) {
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  case RCC_PERIPHCLK_USB: {
    /* Get RCC configuration ------------------------------------------------------*/
    temp_reg = RCC->CFGR;

    /* Check if PLL is enabled */
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) {
      pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
      if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB) || defined(STM32F100xE)
        prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
        prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */

#if defined(STM32F105xC) || defined(STM32F107xC)
        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) {
          /* PLL2 selected as Prediv1 source */
          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
          pllclk  = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
        } else {
          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
          pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
        }

        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
        /* In this case need to divide pllclk by 2 */
        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) {
          pllclk = pllclk / 2;
        }
#else
        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) {
          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
          pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
        }
#endif /* STM32F105xC || STM32F107xC */
      } else {
        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
      }

      /* Calcul of the USB frequency*/
#if defined(STM32F105xC) || defined(STM32F107xC)
      /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) {
        /* Prescaler of 2 selected for USB */
        frequency = pllclk;
      } else {
        /* Prescaler of 3 selected for USB */
        frequency = (2 * pllclk) / 3;
      }
#else
      /* USBCLK = PLLCLK / USB prescaler */
      if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) {
        /* No prescaler selected for USB */
        frequency = pllclk;
      } else {
        /* Prescaler of 1.5 selected for USB */
        frequency = (pllclk * 2) / 3;
      }
#endif
    }
    break;
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
  case RCC_PERIPHCLK_I2S2: {
#if defined(STM32F103xE) || defined(STM32F103xG)
    /* SYSCLK used as source clock for I2S2 */
    frequency = HAL_RCC_GetSysClockFreq();
#else
    if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) {
      /* SYSCLK used as source clock for I2S2 */
      frequency = HAL_RCC_GetSysClockFreq();
    } else {
      /* Check if PLLI2S is enabled */
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
        /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
        prediv2   = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
        pll3mul   = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
        frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
      }
    }
#endif /* STM32F103xE || STM32F103xG */
    break;
  }
  case RCC_PERIPHCLK_I2S3: {
#if defined(STM32F103xE) || defined(STM32F103xG)
    /* SYSCLK used as source clock for I2S3 */
    frequency = HAL_RCC_GetSysClockFreq();
#else
    if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) {
      /* SYSCLK used as source clock for I2S3 */
      frequency = HAL_RCC_GetSysClockFreq();
    } else {
      /* Check if PLLI2S is enabled */
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) {
        /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
        prediv2   = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
        pll3mul   = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
        frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
      }
    }
#endif /* STM32F103xE || STM32F103xG */
    break;
  }
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
  case RCC_PERIPHCLK_RTC: {
    /* Get RCC BDCR configuration ------------------------------------------------------*/
    temp_reg = RCC->BDCR;

    /* Check if LSE is ready if RTC clock selection is LSE */
    if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) {
      frequency = LSE_VALUE;
    }
    /* Check if LSI is ready if RTC clock selection is LSI */
    else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) {
      frequency = LSI_VALUE;
    } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) {
      frequency = HSE_VALUE / 128U;
    }
    /* Clock not enabled for RTC*/
    else {
      frequency = 0U;
    }
    break;
  }
  case RCC_PERIPHCLK_ADC: {
    frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
    break;
  }
  default: {
    break;
  }
  }
  return (frequency);
}

/**
 * @}
 */

#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
  *  @brief  PLLI2S Management functions
  *
@verbatim
 ===============================================================================
                ##### Extended PLLI2S Management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PLLI2S
    activation or deactivation
@endverbatim
  * @{
  */

/**
 * @brief  Enable PLLI2S
 * @param  PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
 *         contains the configuration information for the PLLI2S
 * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) {
  uint32_t tickstart = 0U;

  /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
    /* Check the parameters */
    assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
    assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));

    /* Prediv2 can be written only when the PLL2 is disabled. */
    /* Return an error only if new value is different from the programmed value */
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) {
      return HAL_ERROR;
    }

    /* Disable the main PLLI2S. */
    __HAL_RCC_PLLI2S_DISABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLLI2S is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }

    /* Configure the HSE prediv2 factor --------------------------------*/
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);

    /* Configure the main PLLI2S multiplication factors. */
    __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);

    /* Enable the main PLLI2S. */
    __HAL_RCC_PLLI2S_ENABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLLI2S is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) {
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }
  } else {
    /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
    return HAL_ERROR;
  }

  return HAL_OK;
}

/**
 * @brief  Disable PLLI2S
 * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) {
  uint32_t tickstart = 0U;

  /* Disable PLL I2S as not requested by I2S2 or I2S3*/
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) {
    /* Disable the main PLLI2S. */
    __HAL_RCC_PLLI2S_DISABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLLI2S is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) {
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }
  } else {
    /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
    return HAL_ERROR;
  }

  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
  *  @brief  PLL2 Management functions
  *
@verbatim
 ===============================================================================
                ##### Extended PLL2 Management functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PLL2
    activation or deactivation
@endverbatim
  * @{
  */

/**
 * @brief  Enable PLL2
 * @param  PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
 *         contains the configuration information for the PLL2
 * @note   The PLL2 configuration not modified if used indirectly as system clock.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) {
  uint32_t tickstart = 0U;

  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) &&
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
    return HAL_ERROR;
  } else {
    /* Check the parameters */
    assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
    assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));

    /* Prediv2 can be written only when the PLLI2S is disabled. */
    /* Return an error only if new value is different from the programmed value */
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) {
      return HAL_ERROR;
    }

    /* Disable the main PLL2. */
    __HAL_RCC_PLL2_DISABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLL2 is disabled */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }

    /* Configure the HSE prediv2 factor --------------------------------*/
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);

    /* Configure the main PLL2 multiplication factors. */
    __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);

    /* Enable the main PLL2. */
    __HAL_RCC_PLL2_ENABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLL2 is ready */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }
  }

  return HAL_OK;
}

/**
 * @brief  Disable PLL2
 * @note   PLL2 is not disabled if used indirectly as system clock.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) {
  uint32_t tickstart = 0U;

  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) &&
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) {
    return HAL_ERROR;
  } else {
    /* Disable the main PLL2. */
    __HAL_RCC_PLL2_DISABLE();

    /* Get Start Tick*/
    tickstart = HAL_GetTick();

    /* Wait till PLL2 is disabled */
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) {
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }
  }

  return HAL_OK;
}

/**
 * @}
 */
#endif /* STM32F105xC || STM32F107xC */

/**
 * @}
 */

/**
 * @}
 */

#endif /* HAL_RCC_MODULE_ENABLED */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_tim.c
  * @author  MCD Application Team
  * @brief   TIM HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the Timer (TIM) peripheral:
  *           + TIM Time Base Initialization
  *           + TIM Time Base Start
  *           + TIM Time Base Start Interruption
  *           + TIM Time Base Start DMA
  *           + TIM Output Compare/PWM Initialization
  *           + TIM Output Compare/PWM Channel Configuration
  *           + TIM Output Compare/PWM  Start
  *           + TIM Output Compare/PWM  Start Interruption
  *           + TIM Output Compare/PWM Start DMA
  *           + TIM Input Capture Initialization
  *           + TIM Input Capture Channel Configuration
  *           + TIM Input Capture Start
  *           + TIM Input Capture Start Interruption
  *           + TIM Input Capture Start DMA
  *           + TIM One Pulse Initialization
  *           + TIM One Pulse Channel Configuration
  *           + TIM One Pulse Start
  *           + TIM Encoder Interface Initialization
  *           + TIM Encoder Interface Start
  *           + TIM Encoder Interface Start Interruption
  *           + TIM Encoder Interface Start DMA
  *           + Commutation Event configuration with Interruption and DMA
  *           + TIM OCRef clear configuration
  *           + TIM External Clock configuration
  @verbatim
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output
       (#) Synchronization circuit to control the timer with external signals and to interconnect
            several timers together.
       (#) Supports incremental encoder for positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
            in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()

    *** Callback registration ***
  =============================================

  [..]
  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  allows the user to configure dynamically the driver callbacks.

  [..]
  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  the Callback ID and a pointer to the user callback function.

  [..]
  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  weak function.
  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  and the Callback ID.

  [..]
  These functions allow to register/unregister following callbacks:
    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
    (+) TriggerCallback                   : TIM Trigger Callback.
    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
    (+) IC_CaptureCallback                : TIM Input Capture Callback.
    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
    (+) ErrorCallback                     : TIM Error Callback.
    (+) CommutationCallback               : TIM Commutation Callback.
    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
    (+) BreakCallback                     : TIM Break Callback.

  [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().

  [..]
  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  functionalities in the Init / DeInit only when these callbacks are null
  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)

  [..]
    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
    Exception done MspInit / MspDeInit that can be registered / unregistered
    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  In that case first register the MspInit/MspDeInit user callbacks
      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.

  [..]
      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.

  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup TIM TIM
 * @brief TIM HAL module driver
 * @{
 */

#ifdef HAL_TIM_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
 * @{
 */
static void              TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void              TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void              TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void              TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void              TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
static void              TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void              TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
static void              TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
static void              TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void              TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void              TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void              TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
static void              TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void              TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
 * @}
 */
/* Exported functions --------------------------------------------------------*/

/** @defgroup TIM_Exported_Functions TIM Exported Functions
 * @{
 */

/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  *  @brief    Time Base functions
  *
@verbatim
  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM Time base Unit according to the specified
 *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) {
  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->Base_MspInitCallback == NULL) {
      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM Base peripheral
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->Base_MspDeInitCallback == NULL) {
    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->Base_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_TIM_Base_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Change the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Base MSP.
 * @param  htim TIM Base handle
 * @retval None
 */
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM Base MSP.
 * @param  htim TIM Base handle
 * @retval None
 */
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM Base generation.
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Base generation.
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_READY;

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Base generation in interrupt mode.
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Base generation in interrupt mode.
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Disable the TIM Update interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_READY;

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Base generation in DMA mode.
 * @param  htim TIM Base handle
 * @param  pData The source Buffer address.
 * @param  Length The length of data to be transferred from memory to peripheral.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));

  /* Set the TIM state */
  if (htim->State == HAL_TIM_STATE_BUSY) {
    return HAL_BUSY;
  } else if (htim->State == HAL_TIM_STATE_READY) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      htim->State = HAL_TIM_STATE_BUSY;
    }
  } else {
    return HAL_ERROR;
  }

  /* Set the DMA Period elapsed callbacks */
  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback     = TIM_DMAPeriodElapsedCplt;
  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;

  /* Set the DMA error callback */
  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;

  /* Enable the DMA channel */
  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) {
    /* Return error status */
    return HAL_ERROR;
  }

  /* Enable the TIM Update DMA request */
  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Base generation in DMA mode.
 * @param  htim TIM Base handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));

  /* Disable the TIM Update DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);

  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_READY;

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  *  @brief    TIM Output Compare functions
  *
@verbatim
  ==============================================================================
                  ##### TIM Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the TIM Output Compare.
    (+) Stop the TIM Output Compare.
    (+) Start the TIM Output Compare and enable interrupt.
    (+) Stop the TIM Output Compare and disable interrupt.
    (+) Start the TIM Output Compare and enable DMA transfer.
    (+) Stop the TIM Output Compare and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM Output Compare according to the specified
 *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
 * @param  htim TIM Output Compare handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) {
  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->OC_MspInitCallback == NULL) {
      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->OC_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_OC_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Init the base time for the Output Compare */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM peripheral
 * @param  htim TIM Output Compare handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->OC_MspDeInitCallback == NULL) {
    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->OC_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  HAL_TIM_OC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Change the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Output Compare MSP.
 * @param  htim TIM Output Compare handle
 * @retval None
 */
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM Output Compare MSP.
 * @param  htim TIM Output Compare handle
 * @retval None
 */
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM Output Compare signal generation.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Disable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Enable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Enable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Enable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Enable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }

  /* Enable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }

  /* Disable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Output Compare signal generation in DMA mode.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  pData The source Buffer address.
 * @param  Length The length of data to be transferred from memory to TIM peripheral
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Set the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
    return HAL_BUSY;
  } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }

    /* Enable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }

    /* Enable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 3 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 4 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
    break;
  }

  default:
    break;
  }

  /* Enable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation in DMA mode.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
    break;
  }

  default:
    break;
  }

  /* Disable the Output compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  *  @brief    TIM PWM functions
  *
@verbatim
  ==============================================================================
                          ##### TIM PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the TIM PWM.
    (+) Stop the TIM PWM.
    (+) Start the TIM PWM and enable interrupt.
    (+) Stop the TIM PWM and disable interrupt.
    (+) Start the TIM PWM and enable DMA transfer.
    (+) Stop the TIM PWM and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM PWM Time Base according to the specified
 *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
 * @param  htim TIM PWM handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) {
  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->PWM_MspInitCallback == NULL) {
      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->PWM_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_PWM_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Init the base time for the PWM */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM peripheral
 * @param  htim TIM PWM handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->PWM_MspDeInitCallback == NULL) {
    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->PWM_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  HAL_TIM_PWM_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Change the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM PWM MSP.
 * @param  htim TIM PWM handle
 * @retval None
 */
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM PWM MSP.
 * @param  htim TIM PWM handle
 * @retval None
 */
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the PWM signal generation.
 * @param  htim TIM handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  // if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
  //   /* Enable the main output */
  //   __HAL_TIM_MOE_ENABLE(htim);
  // }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the PWM signal generation.
 * @param  htim TIM PWM handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Disable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the PWM signal generation in interrupt mode.
 * @param  htim TIM PWM handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Enable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Enable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Enable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Enable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }

  /* Enable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the PWM signal generation in interrupt mode.
 * @param  htim TIM PWM handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }

  /* Disable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM PWM signal generation in DMA mode.
 * @param  htim TIM PWM handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  pData The source Buffer address.
 * @param  Length The length of data to be transferred from memory to TIM peripheral
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Set the TIM channel state */
  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
    return HAL_BUSY;
  } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }

    /* Enable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Output Capture/Compare 3 request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 4 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
    break;
  }

  default:
    break;
  }

  /* Enable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM PWM signal generation in DMA mode.
 * @param  htim TIM PWM handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
    break;
  }

  default:
    break;
  }

  /* Disable the Capture compare channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  *  @brief    TIM Input Capture functions
  *
@verbatim
  ==============================================================================
              ##### TIM Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the TIM Input Capture.
   (+) Stop the TIM Input Capture.
   (+) Start the TIM Input Capture and enable interrupt.
   (+) Stop the TIM Input Capture and disable interrupt.
   (+) Start the TIM Input Capture and enable DMA transfer.
   (+) Stop the TIM Input Capture and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM Input Capture Time base according to the specified
 *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
 * @param  htim TIM Input Capture handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) {
  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->IC_MspInitCallback == NULL) {
      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->IC_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_IC_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Init the base time for the input capture */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM peripheral
 * @param  htim TIM Input Capture handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->IC_MspDeInitCallback == NULL) {
    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->IC_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  HAL_TIM_IC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Change the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Input Capture MSP.
 * @param  htim TIM Input Capture handle
 * @retval None
 */
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM Input Capture MSP.
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM Input Capture measurement.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_state               = TIM_CHANNEL_STATE_GET(htim, Channel);
  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Input Capture measurement.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Disable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Input Capture measurement in interrupt mode.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_state               = TIM_CHANNEL_STATE_GET(htim, Channel);
  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  /* Check the TIM channel state */
  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Enable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Enable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Enable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Enable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }
  /* Enable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Input Capture measurement in interrupt mode.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
    break;
  }

  default:
    break;
  }

  /* Disable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Input Capture measurement in DMA mode.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @param  pData The destination Buffer address.
 * @param  Length The length of data to be transferred from TIM peripheral to memory.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_state               = TIM_CHANNEL_STATE_GET(htim, Channel);
  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

  /* Set the TIM channel state */
  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
    return HAL_BUSY;
  } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 2  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 3  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 4  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
    break;
  }

  default:
    break;
  }

  /* Enable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Input Capture measurement in DMA mode.
 * @param  htim TIM Input Capture handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));

  /* Disable the Input Capture channel */
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3  DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Disable the TIM Capture/Compare 4  DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
    break;
  }

  default:
    break;
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}
/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  *  @brief    TIM One Pulse functions
  *
@verbatim
  ==============================================================================
                        ##### TIM One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the TIM One Pulse.
    (+) Stop the TIM One Pulse.
    (+) Start the TIM One Pulse and enable interrupt.
    (+) Stop the TIM One Pulse and disable interrupt.
    (+) Start the TIM One Pulse and enable DMA transfer.
    (+) Stop the TIM One Pulse and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM One Pulse Time Base according to the specified
 *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
 * @note   When the timer instance is initialized in One Pulse mode, timer
 *         channels 1 and channel 2 are reserved and cannot be used for other
 *         purpose.
 * @param  htim TIM One Pulse handle
 * @param  OnePulseMode Select the One pulse mode.
 *         This parameter can be one of the following values:
 *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
 *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) {
  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->OnePulse_MspInitCallback == NULL) {
      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->OnePulse_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_OnePulse_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Configure the Time base in the One Pulse Mode */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Reset the OPM Bit */
  htim->Instance->CR1 &= ~TIM_CR1_OPM;

  /* Configure the OPM Mode */
  htim->Instance->CR1 |= OnePulseMode;

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM One Pulse
 * @param  htim TIM One Pulse handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->OnePulse_MspDeInitCallback == NULL) {
    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->OnePulse_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_TIM_OnePulse_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM One Pulse MSP.
 * @param  htim TIM One Pulse handle
 * @retval None
 */
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM One Pulse MSP.
 * @param  htim TIM One Pulse handle
 * @retval None
 */
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM One Pulse signal generation.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Prevent unused argument(s) compilation warning */
  UNUSED(OutputChannel);

  /* Check the TIM channels state */
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
      (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Capture compare and the Input Capture channels
    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together

    No need to enable the counter, it's enabled automatically by hardware
    (the counter starts in response to a stimulus and generate a pulse */

  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM One Pulse signal generation.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channels to be disable
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(OutputChannel);

  /* Disable the Capture compare and the Input Capture channels
  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */

  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Prevent unused argument(s) compilation warning */
  UNUSED(OutputChannel);

  /* Check the TIM channels state */
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
      (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Capture compare and the Input Capture channels
    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together

    No need to enable the counter, it's enabled automatically by hardware
    (the counter starts in response to a stimulus and generate a pulse */

  /* Enable the TIM Capture/Compare 1 interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);

  /* Enable the TIM Capture/Compare 2 interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);

  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Enable the main output */
    __HAL_TIM_MOE_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(OutputChannel);

  /* Disable the TIM Capture/Compare 1 interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);

  /* Disable the TIM Capture/Compare 2 interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);

  /* Disable the Capture compare and the Input Capture channels
  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) {
    /* Disable the Main Output */
    __HAL_TIM_MOE_DISABLE(htim);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  *  @brief    TIM Encoder functions
  *
@verbatim
  ==============================================================================
                          ##### TIM Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the TIM Encoder.
    (+) Stop the TIM Encoder.
    (+) Start the TIM Encoder and enable interrupt.
    (+) Stop the TIM Encoder and disable interrupt.
    (+) Start the TIM Encoder and enable DMA transfer.
    (+) Stop the TIM Encoder and disable DMA transfer.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
 * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
 *         requires a timer reset to avoid unexpected direction
 *         due to DIR bit readonly in center aligned mode.
 *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
 * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
 *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
 *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
 * @note   When the timer instance is initialized in Encoder mode, timer
 *         channels 1 and channel 2 are reserved and cannot be used for other
 *         purpose.
 * @param  htim TIM Encoder Interface handle
 * @param  sConfig TIM Encoder Interface configuration structure
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) {
  uint32_t tmpsmcr;
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy weak callbacks */
    TIM_ResetCallback(htim);

    if (htim->Encoder_MspInitCallback == NULL) {
      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Encoder_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIM_Encoder_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Reset the SMS and ECE bits */
  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);

  /* Configure the Time base in the Encoder Mode */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;

  /* Get the TIMx CCMR1 register value */
  tmpccmr1 = htim->Instance->CCMR1;

  /* Get the TIMx CCER register value */
  tmpccer = htim->Instance->CCER;

  /* Set the encoder Mode */
  tmpsmcr |= sConfig->EncoderMode;

  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));

  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);

  /* Set the TI1 and the TI2 Polarities */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);

  /* Write to TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;

  /* Write to TIMx CCMR1 */
  htim->Instance->CCMR1 = tmpccmr1;

  /* Write to TIMx CCER */
  htim->Instance->CCER = tmpccer;

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM Encoder interface
 * @param  htim TIM Encoder Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->Encoder_MspDeInitCallback == NULL) {
    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->Encoder_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_TIM_Encoder_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Encoder Interface MSP.
 * @param  htim TIM Encoder Interface handle
 * @retval None
 */
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Encoder_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM Encoder Interface MSP.
 * @param  htim TIM Encoder Interface handle
 * @retval None
 */
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM Encoder Interface.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Set the TIM channel(s) state */
  if (Channel == TIM_CHANNEL_1) {
    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else if (Channel == TIM_CHANNEL_2) {
    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
        (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  }

  /* Enable the encoder interface channels */
  switch (Channel) {
  case TIM_CHANNEL_1: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    break;
  }

  case TIM_CHANNEL_2: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
    break;
  }

  default: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
    break;
  }
  }
  /* Enable the Peripheral */
  __HAL_TIM_ENABLE(htim);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Encoder Interface.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channels 1 and 2
    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  switch (Channel) {
  case TIM_CHANNEL_1: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
    break;
  }

  case TIM_CHANNEL_2: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
    break;
  }

  default: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
    break;
  }
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel(s) state */
  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  } else {
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Encoder Interface in interrupt mode.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Set the TIM channel(s) state */
  if (Channel == TIM_CHANNEL_1) {
    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else if (Channel == TIM_CHANNEL_2) {
    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
        (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  }

  /* Enable the encoder interface channels */
  /* Enable the capture compare Interrupts 1 and/or 2 */
  switch (Channel) {
  case TIM_CHANNEL_1: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  default: {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }
  }

  /* Enable the Peripheral */
  __HAL_TIM_ENABLE(htim);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Encoder Interface in interrupt mode.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channels 1 and 2
    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  if (Channel == TIM_CHANNEL_1) {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);

    /* Disable the capture compare Interrupts 1 */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  } else if (Channel == TIM_CHANNEL_2) {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

    /* Disable the capture compare Interrupts 2 */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  } else {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

    /* Disable the capture compare Interrupts 1 and 2 */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel(s) state */
  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  } else {
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Encoder Interface in DMA mode.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @param  pData1 The destination Buffer address for IC1.
 * @param  pData2 The destination Buffer address for IC2.
 * @param  Length The length of data to be transferred from TIM peripheral to memory.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) {
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Set the TIM channel(s) state */
  if (Channel == TIM_CHANNEL_1) {
    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
      return HAL_BUSY;
    } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
      if ((pData1 == NULL) && (Length > 0U)) {
        return HAL_ERROR;
      } else {
        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      }
    } else {
      return HAL_ERROR;
    }
  } else if (Channel == TIM_CHANNEL_2) {
    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
      return HAL_BUSY;
    } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
      if ((pData2 == NULL) && (Length > 0U)) {
        return HAL_ERROR;
      } else {
        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      }
    } else {
      return HAL_ERROR;
    }
  } else {
    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) ||
        (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
      return HAL_BUSY;
    } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) &&
               (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) {
      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) {
        return HAL_ERROR;
      } else {
        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
      }
    } else {
      return HAL_ERROR;
    }
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Input Capture DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);

    /* Enable the Peripheral */
    __HAL_TIM_ENABLE(htim);

    /* Enable the Capture compare channel */
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Input Capture  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);

    /* Enable the Peripheral */
    __HAL_TIM_ENABLE(htim);

    /* Enable the Capture compare channel */
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
    break;
  }

  case TIM_CHANNEL_ALL: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }

    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the Peripheral */
    __HAL_TIM_ENABLE(htim);

    /* Enable the Capture compare channel */
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);

    /* Enable the TIM Input Capture  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    /* Enable the TIM Input Capture  DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  default:
    break;
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Encoder Interface in DMA mode.
 * @param  htim TIM Encoder Interface handle
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channels 1 and 2
    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  if (Channel == TIM_CHANNEL_1) {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);

    /* Disable the capture compare DMA Request 1 */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  } else if (Channel == TIM_CHANNEL_2) {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

    /* Disable the capture compare DMA Request 2 */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  } else {
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);

    /* Disable the capture compare DMA Request 1 and 2 */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  }

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel(s) state */
  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) {
    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  } else {
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  *  @brief    TIM IRQ handler management
  *
@verbatim
  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

@endverbatim
  * @{
  */
/**
 * @brief  This function handles TIM interrupts requests.
 * @param  htim TIM  handle
 * @retval None
 */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) {
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        /* Output compare event */
        else {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      /* Output compare event */
      else {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      /* Output compare event */
      else {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      /* Output compare event */
      else {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  *  @brief    TIM Peripheral Control functions
  *
@verbatim
  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

@endverbatim
  * @{
  */

/**
 * @brief  Initializes the TIM Output Compare Channels according to the specified
 *         parameters in the TIM_OC_InitTypeDef.
 * @param  htim TIM Output Compare handle
 * @param  sConfig TIM Output Compare configuration structure
 * @param  Channel TIM Channels to configure
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CHANNELS(Channel));
  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));

  /* Process Locked */
  __HAL_LOCK(htim);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Check the parameters */
    assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

    /* Configure the TIM Channel 1 in Output Compare */
    TIM_OC1_SetConfig(htim->Instance, sConfig);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Check the parameters */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    /* Configure the TIM Channel 2 in Output Compare */
    TIM_OC2_SetConfig(htim->Instance, sConfig);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Check the parameters */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    /* Configure the TIM Channel 3 in Output Compare */
    TIM_OC3_SetConfig(htim->Instance, sConfig);
    break;
  }

  case TIM_CHANNEL_4: {
    /* Check the parameters */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    /* Configure the TIM Channel 4 in Output Compare */
    TIM_OC4_SetConfig(htim->Instance, sConfig);
    break;
  }

  default:
    break;
  }

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Input Capture Channels according to the specified
 *         parameters in the TIM_IC_InitTypeDef.
 * @param  htim TIM IC handle
 * @param  sConfig TIM Input Capture configuration structure
 * @param  Channel TIM Channel to configure
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));

  /* Process Locked */
  __HAL_LOCK(htim);

  if (Channel == TIM_CHANNEL_1) {
    /* TI1 Configuration */
    TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

    /* Reset the IC1PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;

    /* Set the IC1PSC value */
    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  } else if (Channel == TIM_CHANNEL_2) {
    /* TI2 Configuration */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

    /* Reset the IC2PSC Bits */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;

    /* Set the IC2PSC value */
    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  } else if (Channel == TIM_CHANNEL_3) {
    /* TI3 Configuration */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

    /* Reset the IC3PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;

    /* Set the IC3PSC value */
    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  } else {
    /* TI4 Configuration */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

    /* Reset the IC4PSC Bits */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;

    /* Set the IC4PSC value */
    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  }

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM PWM  channels according to the specified
 *         parameters in the TIM_OC_InitTypeDef.
 * @param  htim TIM PWM handle
 * @param  sConfig TIM PWM configuration structure
 * @param  Channel TIM Channels to be configured
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CHANNELS(Channel));
  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));

  /* Process Locked */
  __HAL_LOCK(htim);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Check the parameters */
    assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

    /* Configure the Channel 1 in PWM mode */
    TIM_OC1_SetConfig(htim->Instance, sConfig);

    /* Set the Preload enable bit for channel1 */
    htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;

    /* Configure the Output Fast mode */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
    htim->Instance->CCMR1 |= sConfig->OCFastMode;
    break;
  }

  case TIM_CHANNEL_2: {
    /* Check the parameters */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    /* Configure the Channel 2 in PWM mode */
    TIM_OC2_SetConfig(htim->Instance, sConfig);

    /* Set the Preload enable bit for channel2 */
    htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;

    /* Configure the Output Fast mode */
    htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
    htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
    break;
  }

  case TIM_CHANNEL_3: {
    /* Check the parameters */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    /* Configure the Channel 3 in PWM mode */
    TIM_OC3_SetConfig(htim->Instance, sConfig);

    /* Set the Preload enable bit for channel3 */
    htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;

    /* Configure the Output Fast mode */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
    htim->Instance->CCMR2 |= sConfig->OCFastMode;
    break;
  }

  case TIM_CHANNEL_4: {
    /* Check the parameters */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    /* Configure the Channel 4 in PWM mode */
    TIM_OC4_SetConfig(htim->Instance, sConfig);

    /* Set the Preload enable bit for channel4 */
    htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;

    /* Configure the Output Fast mode */
    htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
    htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
    break;
  }

  default:
    break;
  }

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM One Pulse Channels according to the specified
 *         parameters in the TIM_OnePulse_InitTypeDef.
 * @param  htim TIM One Pulse handle
 * @param  sConfig TIM One Pulse configuration structure
 * @param  OutputChannel TIM output channel to configure
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @param  InputChannel TIM input Channel to configure
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @note  To output a waveform with a minimum delay user can enable the fast
 *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
 *        output is forced in response to the edge detection on TIx input,
 *        without taking in account the comparison.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) {
  TIM_OC_InitTypeDef temp1;

  /* Check the parameters */
  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));

  if (OutputChannel != InputChannel) {
    /* Process Locked */
    __HAL_LOCK(htim);

    htim->State = HAL_TIM_STATE_BUSY;

    /* Extract the Output compare configuration from sConfig structure */
    temp1.OCMode       = sConfig->OCMode;
    temp1.Pulse        = sConfig->Pulse;
    temp1.OCPolarity   = sConfig->OCPolarity;
    temp1.OCNPolarity  = sConfig->OCNPolarity;
    temp1.OCIdleState  = sConfig->OCIdleState;
    temp1.OCNIdleState = sConfig->OCNIdleState;

    switch (OutputChannel) {
    case TIM_CHANNEL_1: {
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

      TIM_OC1_SetConfig(htim->Instance, &temp1);
      break;
    }
    case TIM_CHANNEL_2: {
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

      TIM_OC2_SetConfig(htim->Instance, &temp1);
      break;
    }
    default:
      break;
    }

    switch (InputChannel) {
    case TIM_CHANNEL_1: {
      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

      TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

      /* Reset the IC1PSC Bits */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;

      /* Select the Trigger source */
      htim->Instance->SMCR &= ~TIM_SMCR_TS;
      htim->Instance->SMCR |= TIM_TS_TI1FP1;

      /* Select the Slave Mode */
      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
      break;
    }
    case TIM_CHANNEL_2: {
      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

      TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter);

      /* Reset the IC2PSC Bits */
      htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;

      /* Select the Trigger source */
      htim->Instance->SMCR &= ~TIM_SMCR_TS;
      htim->Instance->SMCR |= TIM_TS_TI2FP2;

      /* Select the Slave Mode */
      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
      break;
    }

    default:
      break;
    }

    htim->State = HAL_TIM_STATE_READY;

    __HAL_UNLOCK(htim);

    return HAL_OK;
  } else {
    return HAL_ERROR;
  }
}

/**
 * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
 * @param  htim TIM handle
 * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
 *         This parameter can be one of the following values:
 *            @arg TIM_DMABASE_CR1
 *            @arg TIM_DMABASE_CR2
 *            @arg TIM_DMABASE_SMCR
 *            @arg TIM_DMABASE_DIER
 *            @arg TIM_DMABASE_SR
 *            @arg TIM_DMABASE_EGR
 *            @arg TIM_DMABASE_CCMR1
 *            @arg TIM_DMABASE_CCMR2
 *            @arg TIM_DMABASE_CCER
 *            @arg TIM_DMABASE_CNT
 *            @arg TIM_DMABASE_PSC
 *            @arg TIM_DMABASE_ARR
 *            @arg TIM_DMABASE_RCR
 *            @arg TIM_DMABASE_CCR1
 *            @arg TIM_DMABASE_CCR2
 *            @arg TIM_DMABASE_CCR3
 *            @arg TIM_DMABASE_CCR4
 *            @arg TIM_DMABASE_BDTR
 * @param  BurstRequestSrc TIM DMA Request sources
 *         This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
 *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
 *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
 *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
 *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
 *            @arg TIM_DMA_COM: TIM Commutation DMA source
 *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
 * @param  BurstBuffer The Buffer address.
 * @param  BurstLength DMA Burst length. This parameter can be one value
 *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
 * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) {
  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
}

/**
 * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
 * @param  htim TIM handle
 * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
 *         This parameter can be one of the following values:
 *            @arg TIM_DMABASE_CR1
 *            @arg TIM_DMABASE_CR2
 *            @arg TIM_DMABASE_SMCR
 *            @arg TIM_DMABASE_DIER
 *            @arg TIM_DMABASE_SR
 *            @arg TIM_DMABASE_EGR
 *            @arg TIM_DMABASE_CCMR1
 *            @arg TIM_DMABASE_CCMR2
 *            @arg TIM_DMABASE_CCER
 *            @arg TIM_DMABASE_CNT
 *            @arg TIM_DMABASE_PSC
 *            @arg TIM_DMABASE_ARR
 *            @arg TIM_DMABASE_RCR
 *            @arg TIM_DMABASE_CCR1
 *            @arg TIM_DMABASE_CCR2
 *            @arg TIM_DMABASE_CCR3
 *            @arg TIM_DMABASE_CCR4
 *            @arg TIM_DMABASE_BDTR
 * @param  BurstRequestSrc TIM DMA Request sources
 *         This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
 *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
 *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
 *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
 *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
 *            @arg TIM_DMA_COM: TIM Commutation DMA source
 *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
 * @param  BurstBuffer The Buffer address.
 * @param  BurstLength DMA Burst length. This parameter can be one value
 *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
 * @param  DataLength Data length. This parameter can be one value
 *         between 1 and 0xFFFF.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) {
  /* Check the parameters */
  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));

  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
    return HAL_BUSY;
  } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
    if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
      return HAL_ERROR;
    } else {
      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
    }
  } else {
    /* nothing to do */
  }
  switch (BurstRequestSrc) {
  case TIM_DMA_UPDATE: {
    /* Set the DMA Period elapsed callbacks */
    htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback     = TIM_DMAPeriodElapsedCplt;
    htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC1: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC2: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC3: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC4: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback     = TIM_DMADelayPulseCplt;
    htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_COM: {
    /* Set the DMA commutation callbacks */
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback     = TIMEx_DMACommutationCplt;
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_TRIGGER: {
    /* Set the DMA trigger callbacks */
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback     = TIM_DMATriggerCplt;
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  default:
    break;
  }

  /* Configure the DMA Burst Mode */
  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  /* Enable the TIM DMA Request */
  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM DMA Burst mode
 * @param  htim TIM handle
 * @param  BurstRequestSrc TIM DMA Request sources to disable
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) {
  /* Check the parameters */
  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

  /* Abort the DMA transfer (at least disable the DMA channel) */
  switch (BurstRequestSrc) {
  case TIM_DMA_UPDATE: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
    break;
  }
  case TIM_DMA_CC1: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }
  case TIM_DMA_CC2: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }
  case TIM_DMA_CC3: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }
  case TIM_DMA_CC4: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
    break;
  }
  case TIM_DMA_COM: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
    break;
  }
  case TIM_DMA_TRIGGER: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
    break;
  }
  default:
    break;
  }

  /* Disable the TIM Update DMA request */
  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
 * @param  htim TIM handle
 * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
 *         This parameter can be one of the following values:
 *            @arg TIM_DMABASE_CR1
 *            @arg TIM_DMABASE_CR2
 *            @arg TIM_DMABASE_SMCR
 *            @arg TIM_DMABASE_DIER
 *            @arg TIM_DMABASE_SR
 *            @arg TIM_DMABASE_EGR
 *            @arg TIM_DMABASE_CCMR1
 *            @arg TIM_DMABASE_CCMR2
 *            @arg TIM_DMABASE_CCER
 *            @arg TIM_DMABASE_CNT
 *            @arg TIM_DMABASE_PSC
 *            @arg TIM_DMABASE_ARR
 *            @arg TIM_DMABASE_RCR
 *            @arg TIM_DMABASE_CCR1
 *            @arg TIM_DMABASE_CCR2
 *            @arg TIM_DMABASE_CCR3
 *            @arg TIM_DMABASE_CCR4
 *            @arg TIM_DMABASE_BDTR
 * @param  BurstRequestSrc TIM DMA Request sources
 *         This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
 *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
 *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
 *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
 *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
 *            @arg TIM_DMA_COM: TIM Commutation DMA source
 *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
 * @param  BurstBuffer The Buffer address.
 * @param  BurstLength DMA Burst length. This parameter can be one value
 *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
 * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) {
  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
}

/**
 * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
 * @param  htim TIM handle
 * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
 *         This parameter can be one of the following values:
 *            @arg TIM_DMABASE_CR1
 *            @arg TIM_DMABASE_CR2
 *            @arg TIM_DMABASE_SMCR
 *            @arg TIM_DMABASE_DIER
 *            @arg TIM_DMABASE_SR
 *            @arg TIM_DMABASE_EGR
 *            @arg TIM_DMABASE_CCMR1
 *            @arg TIM_DMABASE_CCMR2
 *            @arg TIM_DMABASE_CCER
 *            @arg TIM_DMABASE_CNT
 *            @arg TIM_DMABASE_PSC
 *            @arg TIM_DMABASE_ARR
 *            @arg TIM_DMABASE_RCR
 *            @arg TIM_DMABASE_CCR1
 *            @arg TIM_DMABASE_CCR2
 *            @arg TIM_DMABASE_CCR3
 *            @arg TIM_DMABASE_CCR4
 *            @arg TIM_DMABASE_BDTR
 * @param  BurstRequestSrc TIM DMA Request sources
 *         This parameter can be one of the following values:
 *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
 *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
 *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
 *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
 *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
 *            @arg TIM_DMA_COM: TIM Commutation DMA source
 *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
 * @param  BurstBuffer The Buffer address.
 * @param  BurstLength DMA Burst length. This parameter can be one value
 *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
 * @param  DataLength Data length. This parameter can be one value
 *         between 1 and 0xFFFF.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) {
  /* Check the parameters */
  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));

  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) {
    return HAL_BUSY;
  } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) {
    if ((BurstBuffer == NULL) && (BurstLength > 0U)) {
      return HAL_ERROR;
    } else {
      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
    }
  } else {
    /* nothing to do */
  }
  switch (BurstRequestSrc) {
  case TIM_DMA_UPDATE: {
    /* Set the DMA Period elapsed callbacks */
    htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback     = TIM_DMAPeriodElapsedCplt;
    htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC1: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC2: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC3: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_CC4: {
    /* Set the DMA capture callbacks */
    htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback     = TIM_DMACaptureCplt;
    htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_COM: {
    /* Set the DMA commutation callbacks */
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback     = TIMEx_DMACommutationCplt;
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  case TIM_DMA_TRIGGER: {
    /* Set the DMA trigger callbacks */
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback     = TIM_DMATriggerCplt;
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    break;
  }
  default:
    break;
  }

  /* Configure the DMA Burst Mode */
  htim->Instance->DCR = (BurstBaseAddress | BurstLength);

  /* Enable the TIM DMA Request */
  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stop the DMA burst reading
 * @param  htim TIM handle
 * @param  BurstRequestSrc TIM DMA Request sources to disable.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) {
  /* Check the parameters */
  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));

  /* Abort the DMA transfer (at least disable the DMA channel) */
  switch (BurstRequestSrc) {
  case TIM_DMA_UPDATE: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
    break;
  }
  case TIM_DMA_CC1: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }
  case TIM_DMA_CC2: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }
  case TIM_DMA_CC3: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }
  case TIM_DMA_CC4: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
    break;
  }
  case TIM_DMA_COM: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
    break;
  }
  case TIM_DMA_TRIGGER: {
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
    break;
  }
  default:
    break;
  }

  /* Disable the TIM Update DMA request */
  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Generate a software event
 * @param  htim TIM handle
 * @param  EventSource specifies the event source.
 *          This parameter can be one of the following values:
 *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
 *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
 *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
 *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
 *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
 *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
 *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
 *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
 * @note   Basic timers can only generate an update event.
 * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
 * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
 *         supporting a break input.
 * @retval HAL status
 */

HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_EVENT_SOURCE(EventSource));

  /* Process Locked */
  __HAL_LOCK(htim);

  /* Change the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Set the event sources */
  htim->Instance->EGR = EventSource;

  /* Change the TIM state */
  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Configures the OCRef clear feature
 * @param  htim TIM handle
 * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
 *         contains the OCREF clear feature and parameters for the TIM peripheral.
 * @param  Channel specifies the TIM Channel
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1
 *            @arg TIM_CHANNEL_2: TIM Channel 2
 *            @arg TIM_CHANNEL_3: TIM Channel 3
 *            @arg TIM_CHANNEL_4: TIM Channel 4
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));

  /* Process Locked */
  __HAL_LOCK(htim);

  htim->State = HAL_TIM_STATE_BUSY;

  switch (sClearInputConfig->ClearInputSource) {
  case TIM_CLEARINPUTSOURCE_NONE: {
    /* Clear the OCREF clear selection bit and the the ETR Bits */
    CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
    break;
  }

  case TIM_CLEARINPUTSOURCE_ETR: {
    /* Check the parameters */
    assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
    assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
    assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));

    /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
    if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) {
      htim->State = HAL_TIM_STATE_READY;
      __HAL_UNLOCK(htim);
      return HAL_ERROR;
    }

    TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter);
    break;
  }

  default:
    break;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
      /* Enable the OCREF clear feature for Channel 1 */
      SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
    } else {
      /* Disable the OCREF clear feature for Channel 1 */
      CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
    }
    break;
  }
  case TIM_CHANNEL_2: {
    if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
      /* Enable the OCREF clear feature for Channel 2 */
      SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
    } else {
      /* Disable the OCREF clear feature for Channel 2 */
      CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
    }
    break;
  }
  case TIM_CHANNEL_3: {
    if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
      /* Enable the OCREF clear feature for Channel 3 */
      SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
    } else {
      /* Disable the OCREF clear feature for Channel 3 */
      CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
    }
    break;
  }
  case TIM_CHANNEL_4: {
    if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) {
      /* Enable the OCREF clear feature for Channel 4 */
      SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
    } else {
      /* Disable the OCREF clear feature for Channel 4 */
      CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
    }
    break;
  }
  default:
    break;
  }

  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief   Configures the clock source to be used
 * @param  htim TIM handle
 * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
 *         contains the clock source information for the TIM peripheral.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) {
  uint32_t tmpsmcr;

  /* Process Locked */
  __HAL_LOCK(htim);

  htim->State = HAL_TIM_STATE_BUSY;

  /* Check the parameters */
  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));

  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  tmpsmcr = htim->Instance->SMCR;
  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  htim->Instance->SMCR = tmpsmcr;

  switch (sClockSourceConfig->ClockSource) {
  case TIM_CLOCKSOURCE_INTERNAL: {
    assert_param(IS_TIM_INSTANCE(htim->Instance));
    break;
  }

  case TIM_CLOCKSOURCE_ETRMODE1: {
    /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
    assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));

    /* Check ETR input conditioning related parameters */
    assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
    assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
    assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

    /* Configure the ETR Clock source */
    TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter);

    /* Select the External clock mode1 and the ETRF trigger */
    tmpsmcr = htim->Instance->SMCR;
    tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
    /* Write to TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
    break;
  }

  case TIM_CLOCKSOURCE_ETRMODE2: {
    /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
    assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));

    /* Check ETR input conditioning related parameters */
    assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
    assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
    assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

    /* Configure the ETR Clock source */
    TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter);
    /* Enable the External clock mode2 */
    htim->Instance->SMCR |= TIM_SMCR_ECE;
    break;
  }

  case TIM_CLOCKSOURCE_TI1: {
    /* Check whether or not the timer instance supports external clock mode 1 */
    assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));

    /* Check TI1 input conditioning related parameters */
    assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
    assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

    TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter);
    TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
    break;
  }

  case TIM_CLOCKSOURCE_TI2: {
    /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
    assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));

    /* Check TI2 input conditioning related parameters */
    assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
    assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

    TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter);
    TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
    break;
  }

  case TIM_CLOCKSOURCE_TI1ED: {
    /* Check whether or not the timer instance supports external clock mode 1 */
    assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));

    /* Check TI1 input conditioning related parameters */
    assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
    assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));

    TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter);
    TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
    break;
  }

  case TIM_CLOCKSOURCE_ITR0:
  case TIM_CLOCKSOURCE_ITR1:
  case TIM_CLOCKSOURCE_ITR2:
  case TIM_CLOCKSOURCE_ITR3: {
    /* Check whether or not the timer instance supports internal trigger input */
    assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));

    TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
    break;
  }

  default:
    break;
  }
  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
 *         or a XOR combination between CH1_input, CH2_input & CH3_input
 * @param  htim TIM handle.
 * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
 *         output of a XOR gate.
 *          This parameter can be one of the following values:
 *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
 *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
 *            pins are connected to the TI1 input (XOR combination)
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) {
  uint32_t tmpcr2;

  /* Check the parameters */
  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;

  /* Reset the TI1 selection */
  tmpcr2 &= ~TIM_CR2_TI1S;

  /* Set the TI1 selection */
  tmpcr2 |= TI1_Selection;

  /* Write to TIMxCR2 */
  htim->Instance->CR2 = tmpcr2;

  return HAL_OK;
}

/**
 * @brief  Configures the TIM in Slave mode
 * @param  htim TIM handle.
 * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
 *         contains the selected trigger (internal trigger input, filtered
 *         timer input or external trigger input) and the Slave mode
 *         (Disable, Reset, Gated, Trigger, External clock mode 1).
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
  /* Check the parameters */
  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));

  __HAL_LOCK(htim);

  htim->State = HAL_TIM_STATE_BUSY;

  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
    htim->State = HAL_TIM_STATE_READY;
    __HAL_UNLOCK(htim);
    return HAL_ERROR;
  }

  /* Disable Trigger Interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);

  /* Disable Trigger DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);

  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configures the TIM in Slave mode in interrupt mode
 * @param  htim TIM handle.
 * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
 *         contains the selected trigger (internal trigger input, filtered
 *         timer input or external trigger input) and the Slave mode
 *         (Disable, Reset, Gated, Trigger, External clock mode 1).
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
  /* Check the parameters */
  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));

  __HAL_LOCK(htim);

  htim->State = HAL_TIM_STATE_BUSY;

  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) {
    htim->State = HAL_TIM_STATE_READY;
    __HAL_UNLOCK(htim);
    return HAL_ERROR;
  }

  /* Enable Trigger Interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);

  /* Disable Trigger DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);

  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Read the captured value from Capture Compare unit
 * @param  htim TIM handle.
 * @param  Channel TIM Channels to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
 * @retval Captured value
 */
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpreg = 0U;

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Check the parameters */
    assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));

    /* Return the capture 1 value */
    tmpreg = htim->Instance->CCR1;

    break;
  }
  case TIM_CHANNEL_2: {
    /* Check the parameters */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));

    /* Return the capture 2 value */
    tmpreg = htim->Instance->CCR2;

    break;
  }

  case TIM_CHANNEL_3: {
    /* Check the parameters */
    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));

    /* Return the capture 3 value */
    tmpreg = htim->Instance->CCR3;

    break;
  }

  case TIM_CHANNEL_4: {
    /* Check the parameters */
    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));

    /* Return the capture 4 value */
    tmpreg = htim->Instance->CCR4;

    break;
  }

  default:
    break;
  }

  return tmpreg;
}

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  *  @brief    TIM Callbacks functions
  *
@verbatim
  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) TIM Period elapsed callback
   (+) TIM Output Compare callback
   (+) TIM Input capture callback
   (+) TIM Trigger callback
   (+) TIM Error callback

@endverbatim
  * @{
  */

/**
 * @brief  Period elapsed half complete callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
   */
}

/**
 * @brief  Output Compare callback in non-blocking mode
 * @param  htim TIM OC handle
 * @retval None
 */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}

/**
 * @brief  Input Capture callback in non-blocking mode
 * @param  htim TIM IC handle
 * @retval None
 */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}

/**
 * @brief  Input Capture half complete callback in non-blocking mode
 * @param  htim TIM IC handle
 * @retval None
 */
__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
   */
}

/**
 * @brief  PWM Pulse finished callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}

/**
 * @brief  PWM Pulse finished half complete callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
   */
}

/**
 * @brief  Hall Trigger detection callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}

/**
 * @brief  Hall Trigger detection half complete callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
   */
}

/**
 * @brief  Timer error callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_ErrorCallback could be implemented in the user file
   */
}

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
 * @brief  Register a User TIM callback to be used instead of the weak predefined callback
 * @param htim tim handle
 * @param CallbackID ID of the callback to be registered
 *        This parameter can be one of the following values:
 *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
 *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
 *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
 *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
 *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
 *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
 *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
 *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
 *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
 *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
 *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
 *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
 *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
 *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
 *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
 *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
 *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
 *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
 *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
 *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
 *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
 *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
 *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
 *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
 *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
 *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
 *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
 *          @param pCallback pointer to the callback function
 *          @retval status
 */
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) {
  HAL_StatusTypeDef status = HAL_OK;

  if (pCallback == NULL) {
    return HAL_ERROR;
  }
  /* Process locked */
  __HAL_LOCK(htim);

  if (htim->State == HAL_TIM_STATE_READY) {
    switch (CallbackID) {
    case HAL_TIM_BASE_MSPINIT_CB_ID:
      htim->Base_MspInitCallback = pCallback;
      break;

    case HAL_TIM_BASE_MSPDEINIT_CB_ID:
      htim->Base_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_IC_MSPINIT_CB_ID:
      htim->IC_MspInitCallback = pCallback;
      break;

    case HAL_TIM_IC_MSPDEINIT_CB_ID:
      htim->IC_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_OC_MSPINIT_CB_ID:
      htim->OC_MspInitCallback = pCallback;
      break;

    case HAL_TIM_OC_MSPDEINIT_CB_ID:
      htim->OC_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_PWM_MSPINIT_CB_ID:
      htim->PWM_MspInitCallback = pCallback;
      break;

    case HAL_TIM_PWM_MSPDEINIT_CB_ID:
      htim->PWM_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
      htim->OnePulse_MspInitCallback = pCallback;
      break;

    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
      htim->OnePulse_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_ENCODER_MSPINIT_CB_ID:
      htim->Encoder_MspInitCallback = pCallback;
      break;

    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
      htim->Encoder_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
      htim->HallSensor_MspInitCallback = pCallback;
      break;

    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
      htim->HallSensor_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_PERIOD_ELAPSED_CB_ID:
      htim->PeriodElapsedCallback = pCallback;
      break;

    case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
      htim->PeriodElapsedHalfCpltCallback = pCallback;
      break;

    case HAL_TIM_TRIGGER_CB_ID:
      htim->TriggerCallback = pCallback;
      break;

    case HAL_TIM_TRIGGER_HALF_CB_ID:
      htim->TriggerHalfCpltCallback = pCallback;
      break;

    case HAL_TIM_IC_CAPTURE_CB_ID:
      htim->IC_CaptureCallback = pCallback;
      break;

    case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
      htim->IC_CaptureHalfCpltCallback = pCallback;
      break;

    case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
      htim->OC_DelayElapsedCallback = pCallback;
      break;

    case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
      htim->PWM_PulseFinishedCallback = pCallback;
      break;

    case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
      htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
      break;

    case HAL_TIM_ERROR_CB_ID:
      htim->ErrorCallback = pCallback;
      break;

    case HAL_TIM_COMMUTATION_CB_ID:
      htim->CommutationCallback = pCallback;
      break;

    case HAL_TIM_COMMUTATION_HALF_CB_ID:
      htim->CommutationHalfCpltCallback = pCallback;
      break;

    case HAL_TIM_BREAK_CB_ID:
      htim->BreakCallback = pCallback;
      break;

    default:
      /* Return error status */
      status = HAL_ERROR;
      break;
    }
  } else if (htim->State == HAL_TIM_STATE_RESET) {
    switch (CallbackID) {
    case HAL_TIM_BASE_MSPINIT_CB_ID:
      htim->Base_MspInitCallback = pCallback;
      break;

    case HAL_TIM_BASE_MSPDEINIT_CB_ID:
      htim->Base_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_IC_MSPINIT_CB_ID:
      htim->IC_MspInitCallback = pCallback;
      break;

    case HAL_TIM_IC_MSPDEINIT_CB_ID:
      htim->IC_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_OC_MSPINIT_CB_ID:
      htim->OC_MspInitCallback = pCallback;
      break;

    case HAL_TIM_OC_MSPDEINIT_CB_ID:
      htim->OC_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_PWM_MSPINIT_CB_ID:
      htim->PWM_MspInitCallback = pCallback;
      break;

    case HAL_TIM_PWM_MSPDEINIT_CB_ID:
      htim->PWM_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
      htim->OnePulse_MspInitCallback = pCallback;
      break;

    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
      htim->OnePulse_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_ENCODER_MSPINIT_CB_ID:
      htim->Encoder_MspInitCallback = pCallback;
      break;

    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
      htim->Encoder_MspDeInitCallback = pCallback;
      break;

    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
      htim->HallSensor_MspInitCallback = pCallback;
      break;

    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
      htim->HallSensor_MspDeInitCallback = pCallback;
      break;

    default:
      /* Return error status */
      status = HAL_ERROR;
      break;
    }
  } else {
    /* Return error status */
    status = HAL_ERROR;
  }

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return status;
}

/**
 * @brief  Unregister a TIM callback
 *         TIM callback is redirected to the weak predefined callback
 * @param htim tim handle
 * @param CallbackID ID of the callback to be unregistered
 *        This parameter can be one of the following values:
 *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
 *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
 *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
 *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
 *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
 *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
 *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
 *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
 *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
 *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
 *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
 *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
 *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
 *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
 *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
 *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
 *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
 *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
 *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
 *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
 *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
 *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
 *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
 *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
 *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
 *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
 *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
 *          @retval status
 */
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) {
  HAL_StatusTypeDef status = HAL_OK;

  /* Process locked */
  __HAL_LOCK(htim);

  if (htim->State == HAL_TIM_STATE_READY) {
    switch (CallbackID) {
    case HAL_TIM_BASE_MSPINIT_CB_ID:
      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
      break;

    case HAL_TIM_BASE_MSPDEINIT_CB_ID:
      htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
      break;

    case HAL_TIM_IC_MSPINIT_CB_ID:
      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
      break;

    case HAL_TIM_IC_MSPDEINIT_CB_ID:
      htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
      break;

    case HAL_TIM_OC_MSPINIT_CB_ID:
      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
      break;

    case HAL_TIM_OC_MSPDEINIT_CB_ID:
      htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
      break;

    case HAL_TIM_PWM_MSPINIT_CB_ID:
      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
      break;

    case HAL_TIM_PWM_MSPDEINIT_CB_ID:
      htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
      break;

    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
      break;

    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
      htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
      break;

    case HAL_TIM_ENCODER_MSPINIT_CB_ID:
      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
      break;

    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
      htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
      break;

    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
      break;

    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
      htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
      break;

    case HAL_TIM_PERIOD_ELAPSED_CB_ID:
      htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
      break;

    case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID:
      htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
      break;

    case HAL_TIM_TRIGGER_CB_ID:
      htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
      break;

    case HAL_TIM_TRIGGER_HALF_CB_ID:
      htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
      break;

    case HAL_TIM_IC_CAPTURE_CB_ID:
      htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
      break;

    case HAL_TIM_IC_CAPTURE_HALF_CB_ID:
      htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
      break;

    case HAL_TIM_OC_DELAY_ELAPSED_CB_ID:
      htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
      break;

    case HAL_TIM_PWM_PULSE_FINISHED_CB_ID:
      htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
      break;

    case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID:
      htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
      break;

    case HAL_TIM_ERROR_CB_ID:
      htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
      break;

    case HAL_TIM_COMMUTATION_CB_ID:
      htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
      break;

    case HAL_TIM_COMMUTATION_HALF_CB_ID:
      htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
      break;

    case HAL_TIM_BREAK_CB_ID:
      htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
      break;

    default:
      /* Return error status */
      status = HAL_ERROR;
      break;
    }
  } else if (htim->State == HAL_TIM_STATE_RESET) {
    switch (CallbackID) {
    case HAL_TIM_BASE_MSPINIT_CB_ID:
      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
      break;

    case HAL_TIM_BASE_MSPDEINIT_CB_ID:
      htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
      break;

    case HAL_TIM_IC_MSPINIT_CB_ID:
      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
      break;

    case HAL_TIM_IC_MSPDEINIT_CB_ID:
      htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
      break;

    case HAL_TIM_OC_MSPINIT_CB_ID:
      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
      break;

    case HAL_TIM_OC_MSPDEINIT_CB_ID:
      htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
      break;

    case HAL_TIM_PWM_MSPINIT_CB_ID:
      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
      break;

    case HAL_TIM_PWM_MSPDEINIT_CB_ID:
      htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
      break;

    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID:
      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
      break;

    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID:
      htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
      break;

    case HAL_TIM_ENCODER_MSPINIT_CB_ID:
      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
      break;

    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID:
      htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
      break;

    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID:
      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
      break;

    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID:
      htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
      break;

    default:
      /* Return error status */
      status = HAL_ERROR;
      break;
    }
  } else {
    /* Return error status */
    status = HAL_ERROR;
  }

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return status;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @}
 */

/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  *  @brief   TIM Peripheral State functions
  *
@verbatim
  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

@endverbatim
  * @{
  */

/**
 * @brief  Return the TIM Base handle state.
 * @param  htim TIM Base handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM OC handle state.
 * @param  htim TIM Output Compare handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM PWM handle state.
 * @param  htim TIM handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM Input Capture handle state.
 * @param  htim TIM IC handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM One Pulse Mode handle state.
 * @param  htim TIM OPM handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM Encoder Mode handle state.
 * @param  htim TIM Encoder Interface handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return the TIM Encoder Mode handle state.
 * @param  htim TIM handle
 * @retval Active channel
 */
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) { return htim->Channel; }

/**
 * @brief  Return actual state of the TIM channel.
 * @param  htim TIM handle
 * @param  Channel TIM Channel
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1
 *            @arg TIM_CHANNEL_2: TIM Channel 2
 *            @arg TIM_CHANNEL_3: TIM Channel 3
 *            @arg TIM_CHANNEL_4: TIM Channel 4
 *            @arg TIM_CHANNEL_5: TIM Channel 5
 *            @arg TIM_CHANNEL_6: TIM Channel 6
 * @retval TIM Channel state
 */
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) {
  HAL_TIM_ChannelStateTypeDef channel_state;

  /* Check the parameters */
  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));

  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);

  return channel_state;
}

/**
 * @brief  Return actual state of a DMA burst operation.
 * @param  htim TIM handle
 * @retval DMA burst state
 */
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));

  return htim->DMABurstState;
}

/**
 * @}
 */

/**
 * @}
 */

/** @defgroup TIM_Private_Functions TIM Private Functions
 * @{
 */

/**
 * @brief  TIM DMA error callback
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIM_DMAError(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  } else {
    htim->State = HAL_TIM_STATE_READY;
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->ErrorCallback(htim);
#else
  HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA Delay Pulse complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PWM_PulseFinishedCallback(htim);
#else
  HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA Delay Pulse half complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PWM_PulseFinishedHalfCpltCallback(htim);
#else
  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA Capture complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureCallback(htim);
#else
  HAL_TIM_IC_CaptureCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA Capture half complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->IC_CaptureHalfCpltCallback(htim);
#else
  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA Period Elapse complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) {
    htim->State = HAL_TIM_STATE_READY;
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PeriodElapsedCallback(htim);
#else
  HAL_TIM_PeriodElapsedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  TIM DMA Period Elapse half complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PeriodElapsedHalfCpltCallback(htim);
#else
  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  TIM DMA Trigger callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) {
    htim->State = HAL_TIM_STATE_READY;
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->TriggerCallback(htim);
#else
  HAL_TIM_TriggerCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  TIM DMA Trigger half complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->TriggerHalfCpltCallback(htim);
#else
  HAL_TIM_TriggerHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  Time Base configuration
 * @param  TIMx TIM peripheral
 * @param  Structure TIM Base configuration structure
 * @retval None
 */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) {
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);

  TIMx->CR1 = tmpcr1;

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period;

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
}

/**
 * @brief  Timer Output Compare 1 configuration
 * @param  TIMx to select the TIM peripheral
 * @param  OC_Config The output configuration structure
 * @retval None
 */
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) {
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 = TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~TIM_CCMR1_OC1M;
  tmpccmrx &= ~TIM_CCMR1_CC1S;
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC1P;
  /* Set the Output Compare Polarity */
  tmpccer |= OC_Config->OCPolarity;

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) {
    /* Check parameters */
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC1NP;
    /* Set the Output N Polarity */
    tmpccer |= OC_Config->OCNPolarity;
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC1NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx)) {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS1;
    tmpcr2 &= ~TIM_CR2_OIS1N;
    /* Set the Output Idle state */
    tmpcr2 |= OC_Config->OCIdleState;
    /* Set the Output N Idle state */
    tmpcr2 |= OC_Config->OCNIdleState;
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

/**
 * @brief  Timer Output Compare 2 configuration
 * @param  TIMx to select the TIM peripheral
 * @param  OC_Config The output configuration structure
 * @retval None
 */
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) {
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 = TIMx->CR2;

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR1_OC2M;
  tmpccmrx &= ~TIM_CCMR1_CC2S;

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC2P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 4U);

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC2NP;
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 4U);
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC2NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx)) {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS2;
    tmpcr2 &= ~TIM_CR2_OIS2N;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 2U);
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR2 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

/**
 * @brief  Timer Output Compare 3 configuration
 * @param  TIMx to select the TIM peripheral
 * @param  OC_Config The output configuration structure
 * @retval None
 */
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) {
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 3: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 = TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC3M;
  tmpccmrx &= ~TIM_CCMR2_CC3S;
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC3P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 8U);

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) {
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC3NP;
    /* Set the Output N Polarity */
    tmpccer |= (OC_Config->OCNPolarity << 8U);
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC3NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx)) {
    /* Check parameters */
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS3;
    tmpcr2 &= ~TIM_CR2_OIS3N;
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 4U);
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

/**
 * @brief  Timer Output Compare 4 configuration
 * @param  TIMx to select the TIM peripheral
 * @param  OC_Config The output configuration structure
 * @retval None
 */
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) {
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
  /* Get the TIMx CR2 register value */
  tmpcr2 = TIMx->CR2;

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC4M;
  tmpccmrx &= ~TIM_CCMR2_CC4S;

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC4P;
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 12U);

  if (IS_TIM_BREAK_INSTANCE(TIMx)) {
    /* Check parameters */
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS4;

    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 6U);
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = OC_Config->Pulse;

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
}

/**
 * @brief  Slave Timer configuration function
 * @param  htim TIM handle
 * @param  sSlaveConfig Slave timer configuration
 * @retval None
 */
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) {
  uint32_t tmpsmcr;
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;

  /* Reset the Trigger Selection Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
  /* Set the Input Trigger source */
  tmpsmcr |= sSlaveConfig->InputTrigger;

  /* Reset the slave mode Bits */
  tmpsmcr &= ~TIM_SMCR_SMS;
  /* Set the slave mode */
  tmpsmcr |= sSlaveConfig->SlaveMode;

  /* Write to TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;

  /* Configure the trigger prescaler, filter, and polarity */
  switch (sSlaveConfig->InputTrigger) {
  case TIM_TS_ETRF: {
    /* Check the parameters */
    assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
    assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
    assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
    assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
    /* Configure the ETR Trigger source */
    TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);
    break;
  }

  case TIM_TS_TI1F_ED: {
    /* Check the parameters */
    assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
    assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

    if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) {
      return HAL_ERROR;
    }

    /* Disable the Channel 1: Reset the CC1E Bit */
    tmpccer = htim->Instance->CCER;
    htim->Instance->CCER &= ~TIM_CCER_CC1E;
    tmpccmr1 = htim->Instance->CCMR1;

    /* Set the filter */
    tmpccmr1 &= ~TIM_CCMR1_IC1F;
    tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);

    /* Write to TIMx CCMR1 and CCER registers */
    htim->Instance->CCMR1 = tmpccmr1;
    htim->Instance->CCER  = tmpccer;
    break;
  }

  case TIM_TS_TI1FP1: {
    /* Check the parameters */
    assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
    assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
    assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

    /* Configure TI1 Filter and Polarity */
    TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);
    break;
  }

  case TIM_TS_TI2FP2: {
    /* Check the parameters */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
    assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
    assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));

    /* Configure TI2 Filter and Polarity */
    TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);
    break;
  }

  case TIM_TS_ITR0:
  case TIM_TS_ITR1:
  case TIM_TS_ITR2:
  case TIM_TS_ITR3: {
    /* Check the parameter */
    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
    break;
  }

  default:
    break;
  }
  return HAL_OK;
}

/**
 * @brief  Configure the TI1 as Input.
 * @param  TIMx to select the TIM peripheral.
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 *            @arg TIM_ICPOLARITY_BOTHEDGE
 * @param  TIM_ICSelection specifies the input to be used.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
 *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
 *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @retval None
 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
 *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
 *        protected against un-initialized filter and polarity values.
 */
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer  = TIMx->CCER;

  /* Select the Input */
  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) {
    tmpccmr1 &= ~TIM_CCMR1_CC1S;
    tmpccmr1 |= TIM_ICSelection;
  } else {
    tmpccmr1 |= TIM_CCMR1_CC1S_0;
  }

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Configure the Polarity and Filter for TI1.
 * @param  TIMx to select the TIM peripheral.
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 *            @arg TIM_ICPOLARITY_BOTHEDGE
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @retval None
 */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
  TIMx->CCER &= ~TIM_CCER_CC1E;
  tmpccmr1 = TIMx->CCMR1;

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
  tmpccmr1 |= (TIM_ICFilter << 4U);

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  tmpccer |= TIM_ICPolarity;

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Configure the TI2 as Input.
 * @param  TIMx to select the TIM peripheral
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 *            @arg TIM_ICPOLARITY_BOTHEDGE
 * @param  TIM_ICSelection specifies the input to be used.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
 *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
 *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @retval None
 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
 *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
 *        protected against un-initialized filter and polarity values.
 */
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer  = TIMx->CCER;

  /* Select the Input */
  tmpccmr1 &= ~TIM_CCMR1_CC2S;
  tmpccmr1 |= (TIM_ICSelection << 8U);

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Configure the Polarity and Filter for TI2.
 * @param  TIMx to select the TIM peripheral.
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 *            @arg TIM_ICPOLARITY_BOTHEDGE
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @retval None
 */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
  tmpccmr1 = TIMx->CCMR1;
  tmpccer  = TIMx->CCER;

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
  tmpccmr1 |= (TIM_ICFilter << 12U);

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  tmpccer |= (TIM_ICPolarity << 4U);

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Configure the TI3 as Input.
 * @param  TIMx to select the TIM peripheral
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 * @param  TIM_ICSelection specifies the input to be used.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
 *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
 *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @retval None
 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
 *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
 *        protected against un-initialized filter and polarity values.
 */
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 3: Reset the CC3E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;
  tmpccmr2 = TIMx->CCMR2;
  tmpccer  = TIMx->CCER;

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC3S;
  tmpccmr2 |= TIM_ICSelection;

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC3F;
  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);

  /* Select the Polarity and set the CC3E Bit */
  tmpccer &= ~(TIM_CCER_CC3P);
  tmpccer |= ((TIM_ICPolarity << 8U) & TIM_CCER_CC3P);

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Configure the TI4 as Input.
 * @param  TIMx to select the TIM peripheral
 * @param  TIM_ICPolarity The Input Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICPOLARITY_RISING
 *            @arg TIM_ICPOLARITY_FALLING
 * @param  TIM_ICSelection specifies the input to be used.
 *          This parameter can be one of the following values:
 *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
 *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
 *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
 * @param  TIM_ICFilter Specifies the Input Capture Filter.
 *          This parameter must be a value between 0x00 and 0x0F.
 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
 *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
 *        protected against un-initialized filter and polarity values.
 * @retval None
 */
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) {
  uint32_t tmpccmr2;
  uint32_t tmpccer;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;
  tmpccmr2 = TIMx->CCMR2;
  tmpccer  = TIMx->CCER;

  /* Select the Input */
  tmpccmr2 &= ~TIM_CCMR2_CC4S;
  tmpccmr2 |= (TIM_ICSelection << 8U);

  /* Set the filter */
  tmpccmr2 &= ~TIM_CCMR2_IC4F;
  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);

  /* Select the Polarity and set the CC4E Bit */
  tmpccer &= ~(TIM_CCER_CC4P);
  tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);

  /* Write to TIMx CCMR2 and CCER registers */
  TIMx->CCMR2 = tmpccmr2;
  TIMx->CCER  = tmpccer;
}

/**
 * @brief  Selects the Input Trigger source
 * @param  TIMx to select the TIM peripheral
 * @param  InputTriggerSource The Input Trigger source.
 *          This parameter can be one of the following values:
 *            @arg TIM_TS_ITR0: Internal Trigger 0
 *            @arg TIM_TS_ITR1: Internal Trigger 1
 *            @arg TIM_TS_ITR2: Internal Trigger 2
 *            @arg TIM_TS_ITR3: Internal Trigger 3
 *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
 *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
 *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
 *            @arg TIM_TS_ETRF: External Trigger input
 * @retval None
 */
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) {
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
}
/**
 * @brief  Configures the TIMx External Trigger (ETR).
 * @param  TIMx to select the TIM peripheral
 * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
 *          This parameter can be one of the following values:
 *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
 *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
 *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
 *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
 * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
 *          This parameter can be one of the following values:
 *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
 *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
 * @param  ExtTRGFilter External Trigger Filter.
 *          This parameter must be a value between 0x00 and 0x0F
 * @retval None
 */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) {
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
}

/**
 * @brief  Enables or disables the TIM Capture Compare Channel x.
 * @param  TIMx to select the TIM peripheral
 * @param  Channel specifies the TIM Channel
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1
 *            @arg TIM_CHANNEL_2: TIM Channel 2
 *            @arg TIM_CHANNEL_3: TIM Channel 3
 *            @arg TIM_CHANNEL_4: TIM Channel 4
 * @param  ChannelState specifies the TIM Channel CCxE bit new state.
 *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
 * @retval None
 */
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) {
  uint32_t tmp;

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
 * @brief  Reset interrupt callbacks to the legacy weak callbacks.
 * @param  htim pointer to a TIM_HandleTypeDef structure that contains
 *                the configuration information for TIM module.
 * @retval None
 */
void TIM_ResetCallback(TIM_HandleTypeDef *htim) {
  /* Reset the TIM callback to the legacy weak callbacks */
  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
 * @}
 */

#endif /* HAL_TIM_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/Vendor/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
================================================
/**
  ******************************************************************************
  * @file    stm32f1xx_hal_tim_ex.c
  * @author  MCD Application Team
  * @brief   TIM HAL module driver.
  *          This file provides firmware functions to manage the following
  *          functionalities of the Timer Extended peripheral:
  *           + Time Hall Sensor Interface Initialization
  *           + Time Hall Sensor Interface Start
  *           + Time Complementary signal break and dead time configuration
  *           + Time Master and Slave synchronization configuration
  *           + Timer remapping capabilities configuration
  @verbatim
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending on the selected feature:
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
               Timer Hall Sensor Interface and the commutation event with the corresponding
               Interrupt and DMA request if needed (Note that One Timer is used to interface
               with the Hall sensor Interface and another Timer should be used to use
               the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().

  @endverbatim
  ******************************************************************************
  * @attention
  *
  * 
© Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.

  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
  *                        opensource.org/licenses/BSD-3-Clause
  *
  ******************************************************************************
  */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

/** @addtogroup STM32F1xx_HAL_Driver
 * @{
 */

/** @defgroup TIMEx TIMEx
 * @brief TIM Extended HAL module driver
 * @{
 */

#ifdef HAL_TIM_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);

/* Exported functions --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
 * @{
 */

/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
  * @brief    Timer Hall Sensor functions
  *
@verbatim
  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

@endverbatim
  * @{
  */
/**
 * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
 * @note   When the timer instance is initialized in Hall Sensor Interface mode,
 *         timer channels 1 and channel 2 are reserved and cannot be used for
 *         other purpose.
 * @param  htim TIM Hall Sensor Interface handle
 * @param  sConfig TIM Hall Sensor configuration structure
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) {
  TIM_OC_InitTypeDef OC_Config;

  /* Check the TIM handle allocation */
  if (htim == NULL) {
    return HAL_ERROR;
  }

  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));

  if (htim->State == HAL_TIM_STATE_RESET) {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
    /* Reset interrupt callbacks to legacy week callbacks */
    TIM_ResetCallback(htim);

    if (htim->HallSensor_MspInitCallback == NULL) {
      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->HallSensor_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
    HAL_TIMEx_HallSensor_MspInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Configure the Time base in the Encoder Mode */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);

  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);

  /* Reset the IC1PSC Bits */
  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  /* Set the IC1PSC value */
  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;

  /* Enable the Hall sensor interface (XOR function of the three inputs) */
  htim->Instance->CR2 |= TIM_CR2_TI1S;

  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
  htim->Instance->SMCR &= ~TIM_SMCR_TS;
  htim->Instance->SMCR |= TIM_TS_TI1F_ED;

  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;

  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
  OC_Config.OCFastMode   = TIM_OCFAST_DISABLE;
  OC_Config.OCIdleState  = TIM_OCIDLESTATE_RESET;
  OC_Config.OCMode       = TIM_OCMODE_PWM2;
  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  OC_Config.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
  OC_Config.OCPolarity   = TIM_OCPOLARITY_HIGH;
  OC_Config.Pulse        = sConfig->Commutation_Delay;

  TIM_OC2_SetConfig(htim->Instance, &OC_Config);

  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
    register to 101 */
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
  htim->Instance->CR2 |= TIM_TRGO_OC2REF;

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;

  return HAL_OK;
}

/**
 * @brief  DeInitializes the TIM Hall Sensor interface
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  htim->State = HAL_TIM_STATE_BUSY;

  /* Disable the TIM Peripheral Clock */
  __HAL_TIM_DISABLE(htim);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  if (htim->HallSensor_MspDeInitCallback == NULL) {
    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
  }
  /* DeInit the low level hardware */
  htim->HallSensor_MspDeInitCallback(htim);
#else
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  /* Change the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;

  /* Change the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);

  /* Change TIM state */
  htim->State = HAL_TIM_STATE_RESET;

  /* Release Lock */
  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Initializes the TIM Hall Sensor MSP.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval None
 */
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
   */
}

/**
 * @brief  DeInitializes TIM Hall Sensor MSP.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval None
 */
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
   */
}

/**
 * @brief  Starts the TIM Hall Sensor Interface.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Check the TIM channels state */
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
      (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Input Capture channel 1
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Hall sensor Interface.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channels 1, 2 and 3
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef channel_2_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);

  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Check the TIM channels state */
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
      (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the capture compare Interrupts 1 event */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);

  /* Enable the Input Capture channel 1
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channel 1
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);

  /* Disable the capture compare Interrupts event */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channels state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
 * @param  htim TIM Hall Sensor Interface handle
 * @param  pData The destination Buffer address.
 * @param  Length The length of data to be transferred from TIM peripheral to memory.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) {
  uint32_t                    tmpsmcr;
  HAL_TIM_ChannelStateTypeDef channel_1_state               = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);

  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Set the TIM channel state */
  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) {
    return HAL_BUSY;
  } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  /* Enable the Input Capture channel 1
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);

  /* Set the DMA Input Capture 1 Callbacks */
  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMACaptureCplt;
  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  /* Set the DMA error callback */
  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError;

  /* Enable the DMA channel for Capture 1*/
  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) {
    /* Return error status */
    return HAL_ERROR;
  }
  /* Enable the capture compare 1 Interrupt */
  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
 * @param  htim TIM Hall Sensor Interface handle
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) {
  /* Check the parameters */
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));

  /* Disable the Input Capture channel 1
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);

  /* Disable the capture compare Interrupts 1 event */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);

  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM channel state */
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
  *  @brief   Timer Complementary Output Compare functions
  *
@verbatim
  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

@endverbatim
  * @{
  */

/**
 * @brief  Starts the TIM Output Compare signal generation on the complementary
 *         output.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Check the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation on the complementary
 *         output.
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Disable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Output Compare signal generation in interrupt mode
 *         on the complementary output.
 * @param  htim TIM OC handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Check the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Enable the TIM Output Compare interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Enable the TIM Output Compare interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Enable the TIM Output Compare interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  default:
    break;
  }

  /* Enable the TIM Break interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);

  /* Enable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation in interrupt mode
 *         on the complementary output.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpccer;
  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Output Compare interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Output Compare interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Output Compare interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  default:
    break;
  }

  /* Disable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the TIM Break interrupt (only if no more channel is active) */
  tmpccer = htim->Instance->CCER;
  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) {
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
  }

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM Output Compare signal generation in DMA mode
 *         on the complementary output.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @param  pData The source Buffer address.
 * @param  Length The length of data to be transferred from memory to TIM peripheral
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Set the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
    return HAL_BUSY;
  } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Output Compare DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Output Compare DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Output Compare DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
    break;
  }

  default:
    break;
  }

  /* Enable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM Output Compare signal generation in DMA mode
 *         on the complementary output.
 * @param  htim TIM Output Compare handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Output Compare DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Output Compare DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Output Compare DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }

  default:
    break;
  }

  /* Disable the Capture compare channel N */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
  * @brief    Timer Complementary PWM functions
  *
@verbatim
  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

@endverbatim
  * @{
  */

/**
 * @brief  Starts the PWM signal generation on the complementary output.
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Check the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the complementary PWM output  */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the PWM signal generation on the complementary output.
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Disable the complementary PWM output  */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the PWM signal generation in interrupt mode on the
 *         complementary output.
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Check the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) {
    return HAL_ERROR;
  }

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Enable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Enable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Enable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  default:
    break;
  }

  /* Enable the TIM Break interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);

  /* Enable the complementary PWM output  */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the PWM signal generation in interrupt mode on the
 *         complementary output.
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) {
  uint32_t tmpccer;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 interrupt */
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
    break;
  }

  default:
    break;
  }

  /* Disable the complementary PWM output  */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the TIM Break interrupt (only if no more channel is active) */
  tmpccer = htim->Instance->CCER;
  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) {
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
  }

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM PWM signal generation in DMA mode on the
 *         complementary output
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @param  pData The source Buffer address.
 * @param  Length The length of data to be transferred from memory to TIM peripheral
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) {
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  /* Set the TIM complementary channel state */
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) {
    return HAL_BUSY;
  } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) {
    if ((pData == NULL) && (Length > 0U)) {
      return HAL_ERROR;
    } else {
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
    }
  } else {
    return HAL_ERROR;
  }

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Set the DMA compare callbacks */
    htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback     = TIM_DMADelayPulseNCplt;
    htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;

    /* Set the DMA error callback */
    htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN;

    /* Enable the DMA channel */
    if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) {
      /* Return error status */
      return HAL_ERROR;
    }
    /* Enable the TIM Capture/Compare 3 DMA request */
    __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
    break;
  }

  default:
    break;
  }

  /* Enable the complementary PWM output  */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) {
      __HAL_TIM_ENABLE(htim);
    }
  } else {
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
 *         output
 * @param  htim TIM handle
 * @param  Channel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) {
  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));

  switch (Channel) {
  case TIM_CHANNEL_1: {
    /* Disable the TIM Capture/Compare 1 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
    break;
  }

  case TIM_CHANNEL_2: {
    /* Disable the TIM Capture/Compare 2 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
    break;
  }

  case TIM_CHANNEL_3: {
    /* Disable the TIM Capture/Compare 3 DMA request */
    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
    break;
  }

  default:
    break;
  }

  /* Disable the complementary PWM output */
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM complementary channel state */
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
  * @brief    Timer Complementary One Pulse functions
  *
@verbatim
  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

@endverbatim
  * @{
  */

/**
 * @brief  Starts the TIM One Pulse signal generation on the complementary
 *         output.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  uint32_t                    input_channel        = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  HAL_TIM_ChannelStateTypeDef input_channel_state  = TIM_CHANNEL_STATE_GET(htim, input_channel);
  HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

  /* Check the TIM channels state */
  if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the complementary One Pulse output channel and the Input Capture channel */
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM One Pulse signal generation on the complementary
 *         output.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

  /* Disable the complementary One Pulse output channel and the Input Capture channel */
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM  channels state */
  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
 *         complementary channel.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channel to be enabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  uint32_t                    input_channel        = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
  HAL_TIM_ChannelStateTypeDef input_channel_state  = TIM_CHANNEL_STATE_GET(htim, input_channel);
  HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

  /* Check the TIM channels state */
  if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) {
    return HAL_ERROR;
  }

  /* Set the TIM channels state */
  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);

  /* Enable the TIM Capture/Compare 1 interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);

  /* Enable the TIM Capture/Compare 2 interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);

  /* Enable the complementary One Pulse output channel and the Input Capture channel */
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);

  /* Enable the Main Output */
  __HAL_TIM_MOE_ENABLE(htim);

  /* Return function status */
  return HAL_OK;
}

/**
 * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
 *         complementary channel.
 * @param  htim TIM One Pulse handle
 * @param  OutputChannel TIM Channel to be disabled
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
 *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) {
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));

  /* Disable the TIM Capture/Compare 1 interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);

  /* Disable the TIM Capture/Compare 2 interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);

  /* Disable the complementary One Pulse output channel and the Input Capture channel */
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);

  /* Disable the Main Output */
  __HAL_TIM_MOE_DISABLE(htim);

  /* Disable the Peripheral */
  __HAL_TIM_DISABLE(htim);

  /* Set the TIM  channels state */
  TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
  TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);

  /* Return function status */
  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
  * @brief    Peripheral Control functions
  *
@verbatim
  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Output channels for OC and PWM mode.

      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.
      (+) Configure timer remapping capabilities.

@endverbatim
  * @{
  */

/**
 * @brief  Configure the TIM commutation event sequence.
 * @note  This function is mandatory to use the commutation event in order to
 *        update the configuration at each commutation detection on the TRGI input of the Timer,
 *        the typical use of this feature is with the use of another Timer(interface Timer)
 *        configured in Hall sensor interface, this interface Timer will generate the
 *        commutation at its TRGO output (connected to Timer used in this function) each time
 *        the TI1 of the Interface Timer detect a commutation at its input TI1.
 * @param  htim TIM handle
 * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
 *          This parameter can be one of the following values:
 *            @arg TIM_TS_ITR0: Internal trigger 0 selected
 *            @arg TIM_TS_ITR1: Internal trigger 1 selected
 *            @arg TIM_TS_ITR2: Internal trigger 2 selected
 *            @arg TIM_TS_ITR3: Internal trigger 3 selected
 *            @arg TIM_TS_NONE: No trigger is needed
 * @param  CommutationSource the Commutation Event source
 *          This parameter can be one of the following values:
 *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
 *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
  /* Check the parameters */
  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));

  __HAL_LOCK(htim);

  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
    /* Select the Input trigger */
    htim->Instance->SMCR &= ~TIM_SMCR_TS;
    htim->Instance->SMCR |= InputTrigger;
  }

  /* Select the Capture Compare preload feature */
  htim->Instance->CR2 |= TIM_CR2_CCPC;
  /* Select the Commutation event source */
  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  htim->Instance->CR2 |= CommutationSource;

  /* Disable Commutation Interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);

  /* Disable Commutation DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configure the TIM commutation event sequence with interrupt.
 * @note  This function is mandatory to use the commutation event in order to
 *        update the configuration at each commutation detection on the TRGI input of the Timer,
 *        the typical use of this feature is with the use of another Timer(interface Timer)
 *        configured in Hall sensor interface, this interface Timer will generate the
 *        commutation at its TRGO output (connected to Timer used in this function) each time
 *        the TI1 of the Interface Timer detect a commutation at its input TI1.
 * @param  htim TIM handle
 * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
 *          This parameter can be one of the following values:
 *            @arg TIM_TS_ITR0: Internal trigger 0 selected
 *            @arg TIM_TS_ITR1: Internal trigger 1 selected
 *            @arg TIM_TS_ITR2: Internal trigger 2 selected
 *            @arg TIM_TS_ITR3: Internal trigger 3 selected
 *            @arg TIM_TS_NONE: No trigger is needed
 * @param  CommutationSource the Commutation Event source
 *          This parameter can be one of the following values:
 *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
 *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
  /* Check the parameters */
  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));

  __HAL_LOCK(htim);

  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
    /* Select the Input trigger */
    htim->Instance->SMCR &= ~TIM_SMCR_TS;
    htim->Instance->SMCR |= InputTrigger;
  }

  /* Select the Capture Compare preload feature */
  htim->Instance->CR2 |= TIM_CR2_CCPC;
  /* Select the Commutation event source */
  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  htim->Instance->CR2 |= CommutationSource;

  /* Disable Commutation DMA request */
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);

  /* Enable the Commutation Interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configure the TIM commutation event sequence with DMA.
 * @note  This function is mandatory to use the commutation event in order to
 *        update the configuration at each commutation detection on the TRGI input of the Timer,
 *        the typical use of this feature is with the use of another Timer(interface Timer)
 *        configured in Hall sensor interface, this interface Timer will generate the
 *        commutation at its TRGO output (connected to Timer used in this function) each time
 *        the TI1 of the Interface Timer detect a commutation at its input TI1.
 * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
 * @param  htim TIM handle
 * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
 *          This parameter can be one of the following values:
 *            @arg TIM_TS_ITR0: Internal trigger 0 selected
 *            @arg TIM_TS_ITR1: Internal trigger 1 selected
 *            @arg TIM_TS_ITR2: Internal trigger 2 selected
 *            @arg TIM_TS_ITR3: Internal trigger 3 selected
 *            @arg TIM_TS_NONE: No trigger is needed
 * @param  CommutationSource the Commutation Event source
 *          This parameter can be one of the following values:
 *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
 *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) {
  /* Check the parameters */
  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));

  __HAL_LOCK(htim);

  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) {
    /* Select the Input trigger */
    htim->Instance->SMCR &= ~TIM_SMCR_TS;
    htim->Instance->SMCR |= InputTrigger;
  }

  /* Select the Capture Compare preload feature */
  htim->Instance->CR2 |= TIM_CR2_CCPC;
  /* Select the Commutation event source */
  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
  htim->Instance->CR2 |= CommutationSource;

  /* Enable the Commutation DMA Request */
  /* Set the DMA Commutation Callback */
  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback     = TIMEx_DMACommutationCplt;
  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
  /* Set the DMA error callback */
  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;

  /* Disable Commutation Interrupt */
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);

  /* Enable the Commutation DMA Request */
  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configures the TIM in master mode.
 * @param  htim TIM handle.
 * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
 *         contains the selected trigger output (TRGO) and the Master/Slave
 *         mode.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) {
  uint32_t tmpcr2;
  uint32_t tmpsmcr;

  /* Check the parameters */
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
  /* Select the TRGO source */
  tmpcr2 |= sMasterConfig->MasterOutputTrigger;

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
 *         and the AOE(automatic output enable).
 * @param  htim TIM handle
 * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
 *         contains the BDTR Register configuration  information for the TIM peripheral.
 * @note   Interrupts can be generated when an active level is detected on the
 *         break input, the break 2 input or the system break input. Break
 *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) {
  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
  uint32_t tmpbdtr = 0U;

  /* Check the parameters */
  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));

  /* Check input state */
  __HAL_LOCK(htim);

  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
     the OSSI State, the dead time value and the Automatic Output Enable Bit */

  /* Set the BDTR bits */
  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);

  /* Set TIMx_BDTR */
  htim->Instance->BDTR = tmpbdtr;

  __HAL_UNLOCK(htim);

  return HAL_OK;
}

/**
 * @brief  Configures the TIMx Remapping input capabilities.
 * @param  htim TIM handle.
 * @param  Remap specifies the TIM remapping source.
 *
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);
  UNUSED(Remap);

  return HAL_OK;
}

/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
  * @brief    Extended Callbacks functions
  *
@verbatim
  ==============================================================================
                    ##### Extended Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extended TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

@endverbatim
  * @{
  */

/**
 * @brief  Hall commutation changed callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
/**
 * @brief  Hall commutation changed half complete callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
   */
}

/**
 * @brief  Hall Break detection callback in non-blocking mode
 * @param  htim TIM handle
 * @retval None
 */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) {
  /* Prevent unused argument(s) compilation warning */
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
/**
 * @}
 */

/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
  * @brief    Extended Peripheral State functions
  *
@verbatim
  ==============================================================================
                ##### Extended Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

@endverbatim
  * @{
  */

/**
 * @brief  Return the TIM Hall Sensor interface handle state.
 * @param  htim TIM Hall Sensor handle
 * @retval HAL state
 */
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; }

/**
 * @brief  Return actual state of the TIM complementary channel.
 * @param  htim TIM handle
 * @param  ChannelN TIM Complementary channel
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1
 *            @arg TIM_CHANNEL_2: TIM Channel 2
 *            @arg TIM_CHANNEL_3: TIM Channel 3
 * @retval TIM Complementary channel state
 */
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) {
  HAL_TIM_ChannelStateTypeDef channel_state;

  /* Check the parameters */
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));

  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);

  return channel_state;
}
/**
 * @}
 */

/**
 * @}
 */

/* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
 * @{
 */

/**
 * @brief  TIM DMA Commutation callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->CommutationCallback(htim);
#else
  HAL_TIMEx_CommutCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  TIM DMA Commutation half complete callback.
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->CommutationHalfCpltCallback(htim);
#else
  HAL_TIMEx_CommutHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}

/**
 * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;

    if (hdma->Init.Mode == DMA_NORMAL) {
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
    }
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->PWM_PulseFinishedCallback(htim);
#else
  HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  TIM DMA error callback (complementary channel)
 * @param  hdma pointer to DMA handle.
 * @retval None
 */
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) {
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;

  if (hdma == htim->hdma[TIM_DMA_ID_CC1]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) {
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  } else {
    /* nothing to do */
  }

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  htim->ErrorCallback(htim);
#else
  HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

/**
 * @brief  Enables or disables the TIM Capture Compare Channel xN.
 * @param  TIMx to select the TIM peripheral
 * @param  Channel specifies the TIM Channel
 *          This parameter can be one of the following values:
 *            @arg TIM_CHANNEL_1: TIM Channel 1
 *            @arg TIM_CHANNEL_2: TIM Channel 2
 *            @arg TIM_CHANNEL_3: TIM Channel 3
 * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
 *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
 * @retval None
 */
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) {
  uint32_t tmp;

  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */

  /* Reset the CCxNE Bit */
  TIMx->CCER &= ~tmp;

  /* Set or reset the CCxNE Bit */
  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
/**
 * @}
 */

#endif /* HAL_TIM_MODULE_ENABLED */
/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/configuration.h
================================================
#ifndef CONFIGURATION_H_
#define CONFIGURATION_H_
#include 
/**
 * Configuration.h
 * Define here your default pre settings for S60
 *
 */

//===========================================================================
//============================= Default Settings ============================
//===========================================================================
/**
 * Default soldering temp is 320.0 C
 * Temperature the iron sleeps at - default 150.0 C
 */

#define SLEEP_TEMP         150 // Default sleep temperature
#define BOOST_TEMP         420 // Default boost temp.
#define BOOST_MODE_ENABLED 1   // 0: Disable 1: Enable

/**
 * OLED Brightness
 *
 */
#define MIN_BRIGHTNESS     1   // Min OLED brightness selectable
#define MAX_BRIGHTNESS     101 // Max OLED brightness selectable
#define BRIGHTNESS_STEP    25  // OLED brightness increment
#define DEFAULT_BRIGHTNESS 25  // default OLED brightness

/**
 * Blink the temperature on the cooling screen when its > 50C
 */
#define COOLING_TEMP_BLINK 0 // 0: Disable 1: Enable

/**
 * How many seconds/minutes we wait until going to sleep/shutdown.
 * Values -> SLEEP_TIME * 10; i.e. 5*10 = 50 Seconds!
 */
#define SLEEP_TIME    5  // x10 Seconds
#define SHUTDOWN_TIME 10 // Minutes

/**
 * Auto start off for safety.
 * Pissible values are:
 *  0 - none
 *  1 - Soldering Temperature
 *  2 - Sleep Temperature
 *  3 - Sleep Off Temperature
 */
#define AUTO_START_MODE 0 // Default to none

/**
 * Locking Mode
 * When in soldering mode a long press on both keys toggle the lock of the buttons
 * Possible values are:
 *  0 - Desactivated
 *  1 - Lock except boost
 *  2 - Full lock
 */
#define LOCKING_MODE 0 // Default to desactivated for safety

/**
 * OLED Orientation
 *
 */
#define ORIENTATION_MODE           0 // 0: Right 1:Left (2:Automatic N/A)
#define MAX_ORIENTATION_MODE       1 // Disable auto mode
#define REVERSE_BUTTON_TEMP_CHANGE 0 // 0:Default 1:Reverse - Reverse the plus and minus button assigment for temperature change

/**
 * Temp change settings
 */
#define TEMP_CHANGE_SHORT_STEP     1  // Default temp change short step +1
#define TEMP_CHANGE_LONG_STEP      10 // Default temp change long step +10
#define TEMP_CHANGE_SHORT_STEP_MAX 50 // Temp change short step MAX value
#define TEMP_CHANGE_LONG_STEP_MAX  90 // Temp change long step MAX value

/* Power pulse for keeping power banks awake*/
#define POWER_PULSE_INCREMENT    1
#define POWER_PULSE_MAX          100 // x10 max watts
#define POWER_PULSE_WAIT_MAX     9   // 9*2.5s = 22.5 seconds
#define POWER_PULSE_DURATION_MAX 9   // 9*250ms = 2.25 seconds

#define POWER_PULSE_DEFAULT          0
#define POWER_PULSE_WAIT_DEFAULT     4 // Default rate of the power pulse: 4*2500 = 10000 ms = 10 s
#define POWER_PULSE_DURATION_DEFAULT 1 // Default duration of the power pulse: 1*250 = 250 ms

/**
 * OLED Orientation Sensitivity on Automatic mode!
 * Motion Sensitivity <0=Off 1=Least Sensitive 9=Most Sensitive>
 */
#define SENSITIVITY 7 // Default 7

/**
 * Detailed soldering screen
 * Detailed idle screen (off for first time users)
 */
#define DETAILED_SOLDERING 0 // 0: Disable 1: Enable - Default 0
#define DETAILED_IDLE      0 // 0: Disable 1: Enable - Default 0

#define CUT_OUT_SETTING          0  // default to no cut-off voltage
#define RECOM_VOL_CELL           33 // Minimum voltage per cell (Recommended 3.3V (33))
#define TEMPERATURE_INF          0  // default to 0
#define DESCRIPTION_SCROLL_SPEED 0  // 0: Slow 1: Fast - default to slow
#define ANIMATION_LOOP           1  // 0: off 1: on
#define ANIMATION_SPEED          settingOffSpeed_t::MEDIUM

// Op-amp gain
// First stage has a gain of 10.31, followed by gain of 52; so total gain is 536

#define ADC_MAX_READING (4096 * 8) // Maximum reading of the adc
#define ADC_VDD_MV      3300       // ADC max reading millivolts

// Deriving the Voltage div:
// Vin_max = (3.3*(r1+r2))/(r2)
// vdiv = (32768*4)/(vin_max*10)

#if defined(MODEL_S60) + defined(MODEL_S60P) + defined(MODEL_T55) == 0
#error "No model defined!"
#endif

#define NEEDS_VBUS_PROBE 0

#ifdef MODEL_S60
#define VOLTAGE_DIV        460 // Default divider scaler
#define CALIBRATION_OFFSET 200 // Default adc offset in uV
#define PID_POWER_LIMIT    70  // Sets the max pwm power limit
#define POWER_LIMIT        0   // 0 watts default limit
#define MAX_POWER_LIMIT    70
#define POWER_LIMIT_STEPS  5
#define OP_AMP_GAIN_STAGE  536
#define TEMP_uV_LOOKUP_S60
#define USB_PD_VMAX              12 // Maximum voltage for PD to negotiate
#define THERMAL_RUNAWAY_TIME_SEC 20
#define THERMAL_RUNAWAY_TEMP_C   3

#define HARDWARE_MAX_WATTAGE_X10 600

#define TIP_THERMAL_MASS    10  // X10 watts to raise 1 deg C in 1 second
#define TIP_THERMAL_INERTIA 128 // We use a large inertia value to smooth out the drive to the tip since its stupidly sensitive

#define TIP_RESISTANCE 20 //(actually 2.5 ish but we need to be more conservative on pwm'ing watt limit) x10 ohms

#define OLED_128x32
#define GPIO_VIBRATION
#define POW_PD_EXT                1
#define USB_PD_EPR_WATTAGE        0 /*No EPR*/
#define DEBUG_POWER_MENU_BUTTON_B 1
#define HAS_POWER_DEBUG_MENU
#define TEMP_NTC
#define I2C_SOFT_BUS_2 // For now we are doing software I2C to get around hardware chip issues
#define OLED_I2CBB2
#define FILTER_DISPLAYED_TIP_TEMP 4 // Filtering for GUI display

#define MODEL_HAS_DCDC // We dont have DC/DC but have reallly fast PWM that gets us roughly the same place
#endif                 /* S60 */

#ifdef MODEL_S60P
#define VOLTAGE_DIV        460 // Default divider scaler
#define CALIBRATION_OFFSET 200 // Default adc offset in uV
#define PID_POWER_LIMIT    70  // Sets the max pwm power limit
#define POWER_LIMIT        0   // 0 watts default limit
#define MAX_POWER_LIMIT    70
#define POWER_LIMIT_STEPS  5
#define OP_AMP_GAIN_STAGE  536
#define TEMP_uV_LOOKUP_S60
#define USB_PD_VMAX              20 // Maximum voltage for PD to negotiate
#define THERMAL_RUNAWAY_TIME_SEC 20
#define THERMAL_RUNAWAY_TEMP_C   3

#define HARDWARE_MAX_WATTAGE_X10 600

#define TIP_THERMAL_MASS    10  // X10 watts to raise 1 deg C in 1 second
#define TIP_THERMAL_INERTIA 128 // We use a large inertia value to smooth out the drive to the tip since its stupidly sensitive

#define TIP_RESISTANCE 20 //(actually 2.5 ish but we need to be more conservative on pwm'ing watt limit) x10 ohms

#define OLED_128x32
#define GPIO_VIBRATION
#define POW_PD_EXT                2
#define USB_PD_EPR_WATTAGE        0 /*No EPR*/
#define DEBUG_POWER_MENU_BUTTON_B 1
#define HAS_POWER_DEBUG_MENU
#define TEMP_NTC
#define I2C_SOFT_BUS_2 // For now we are doing software I2C to get around hardware chip issues
#define OLED_I2CBB2
#define FILTER_DISPLAYED_TIP_TEMP 4 // Filtering for GUI display

#define MODEL_HAS_DCDC // We dont have DC/DC but have reallly fast PWM that gets us roughly the same place
#endif                 /* S60P */

#ifdef MODEL_T55
// T55 Hotplate is similar to Project-Argon, PCB heater + PT100 sensor but no current rolloff compensation
// Uses a HUB238 for PD negotiation like the S60, also has a buzzer. Feels like designed to share with S60
// Hold back left button for "DFU"

#define SOLDERING_TEMP         200 // Default soldering temp is 200.0 °C
#define VOLTAGE_DIV            460 // Default divider scaler
#define MIN_CALIBRATION_OFFSET 0   // Should be 0
#define CALIBRATION_OFFSET     0   // Default adc offset in uV
#define PID_POWER_LIMIT        70  // Sets the max pwm power limit
#define POWER_LIMIT            0   // 0 watts default limit
#define MAX_POWER_LIMIT        70
#define POWER_LIMIT_STEPS      5
#define OP_AMP_GAIN_STAGE      1
#define TEMP_uV_LOOKUP_PT1000
#define USB_PD_VMAX       20  // Maximum voltage for PD to negotiate
#define NO_DISPLAY_ROTATE     // Disable OLED rotation by accel
#define MAX_TEMP_C        350 // Max soldering temp selectable °C
#define MAX_TEMP_F        660 // Max soldering temp selectable °F
#define MIN_TEMP_C        10  // Min soldering temp selectable °C
#define MIN_TEMP_F        50  // Min soldering temp selectable °F
#define MIN_BOOST_TEMP_C  150 // The min settable temp for boost mode °C
#define MIN_BOOST_TEMP_F  300 // The min settable temp for boost mode °F
#define NO_SLEEP_MODE
#define HARDWARE_MAX_WATTAGE_X10 850

#define TIP_THERMAL_MASS         30 // X10 watts to raise 1 deg C in 1 second
#define TIP_THERMAL_INERTIA      10 // We use a large inertia value to smooth out the drive to the tip since its stupidly sensitive
#define THERMAL_RUNAWAY_TIME_SEC 30
#define THERMAL_RUNAWAY_TEMP_C   2

#define COPPER_HEATER_COIL 1  // Have a heater coil that changes resistance on us
#define TIP_RESISTANCE     52 // PCB heater, measured at ~19C. Will shift by temp a decent amount
#define CUSTOM_MAX_TEMP_C
#define PROFILE_SUPPORT           1 // Soldering Profiles
#define OLED_128x32               1 // Larger OLED
#define OLED_FLIP                 1 // Mounted upside down
#define POW_PD_EXT                1 // Older HUB238
#define USB_PD_EPR_WATTAGE        0 /*No EPR*/
#define DEBUG_POWER_MENU_BUTTON_B 1
#define HAS_POWER_DEBUG_MENU
#define NO_ACCEL       1
#define I2C_SOFT_BUS_2 // For now we are doing software I2C to get around hardware chip issues
#define OLED_I2CBB2
#define FILTER_DISPLAYED_TIP_TEMP 16 // Filtering for GUI display

#define MODEL_HAS_DCDC // We dont have DC/DC but have reallly fast PWM that gets us roughly the same place
#endif                 /* T55 */

#define FLASH_LOGOADDR      (0x08000000 + (62 * 1024))
#define SETTINGS_START_PAGE (0x08000000 + (63 * 1024))

// Defaults

#ifndef MIN_CALIBRATION_OFFSET
#define MIN_CALIBRATION_OFFSET 100 // Min value for calibration
#endif
#ifndef SOLDERING_TEMP
#define SOLDERING_TEMP 320 // Default soldering temp is 320.0 °C
#endif
#ifndef PID_TIM_HZ
#define PID_TIM_HZ (8) // Tick rate of the PID loop
#endif
#ifndef MAX_TEMP_C
#define MAX_TEMP_C 450 // Max soldering temp selectable °C
#endif
#ifndef MAX_TEMP_F
#define MAX_TEMP_F 850 // Max soldering temp selectable °F
#endif
#ifndef MIN_TEMP_C
#define MIN_TEMP_C 10 // Min soldering temp selectable °C
#endif
#ifndef MIN_TEMP_F
#define MIN_TEMP_F 60 // Min soldering temp selectable °F
#endif
#ifndef MIN_BOOST_TEMP_C
#define MIN_BOOST_TEMP_C 250 // The min settable temp for boost mode °C
#endif
#ifndef MIN_BOOST_TEMP_F
#define MIN_BOOST_TEMP_F 480 // The min settable temp for boost mode °F
#endif

#endif /* CONFIGURATION_H_ */


================================================
FILE: source/Core/BSP/Sequre/flash.c
================================================
/*
 * flash.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BSP.h"
#include "BSP_Flash.h"
#include "stm32f1xx_hal.h"
#include "string.h"

void flash_save_buffer(const uint8_t *buffer, const uint16_t length) {
  FLASH_EraseInitTypeDef pEraseInit;
  pEraseInit.TypeErase    = FLASH_TYPEERASE_PAGES;
  pEraseInit.Banks        = FLASH_BANK_1;
  pEraseInit.NbPages      = 1;
  pEraseInit.PageAddress  = (uint32_t)SETTINGS_START_PAGE;
  uint32_t failingAddress = 0;
  resetWatchdog();
  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR | FLASH_FLAG_BSY);
  HAL_FLASH_Unlock();
  HAL_Delay(1);
  resetWatchdog();
  HAL_FLASHEx_Erase(&pEraseInit, &failingAddress);
  //^ Erase the page of flash (1024 bytes on this stm32)
  // erased the chunk
  // now we program it
  uint16_t *data = (uint16_t *)buffer;
  HAL_FLASH_Unlock();
  for (uint16_t i = 0; i < (length / 2); i++) {
    resetWatchdog();
    HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, SETTINGS_START_PAGE + (i * sizeof(uint16_t)), data[i]);
  }
  HAL_FLASH_Lock();
}

void flash_read_buffer(uint8_t *buffer, const uint16_t length) { memcpy(buffer, (uint8_t *)SETTINGS_START_PAGE, length); }


================================================
FILE: source/Core/BSP/Sequre/port.c
================================================
/*
 * FreeRTOS Kernel V10.3.1
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

/*-----------------------------------------------------------
 * Implementation of functions defined in portable.h for the ARM CM3 port.
 *----------------------------------------------------------*/

/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"

/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
 defined.  The value should also ensure backward compatibility.
 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
#ifndef configKERNEL_INTERRUPT_PRIORITY
#define configKERNEL_INTERRUPT_PRIORITY 255
#endif

#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
/* Ensure the SysTick is clocked at the same frequency as the core. */
#define portNVIC_SYSTICK_CLK_BIT (1UL << 2UL)
#else
/* The way the SysTick is clocked is not modified in case it is not the same
as the core. */
#define portNVIC_SYSTICK_CLK_BIT (0)
#endif

/* Constants required to manipulate the core.  Registers first... */
#define portNVIC_SYSTICK_CTRL_REG          (*((volatile uint32_t *)0xe000e010))
#define portNVIC_SYSTICK_LOAD_REG          (*((volatile uint32_t *)0xe000e014))
#define portNVIC_SYSTICK_CURRENT_VALUE_REG (*((volatile uint32_t *)0xe000e018))
#define portNVIC_SYSPRI2_REG               (*((volatile uint32_t *)0xe000ed20))
/* ...then bits in the registers. */
#define portNVIC_SYSTICK_INT_BIT        (1UL << 1UL)
#define portNVIC_SYSTICK_ENABLE_BIT     (1UL << 0UL)
#define portNVIC_SYSTICK_COUNT_FLAG_BIT (1UL << 16UL)
#define portNVIC_PENDSVCLEAR_BIT        (1UL << 27UL)
#define portNVIC_PEND_SYSTICK_CLEAR_BIT (1UL << 25UL)

#define portNVIC_PENDSV_PRI  (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 16UL)
#define portNVIC_SYSTICK_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 24UL)

/* Constants required to check the validity of an interrupt priority. */
#define portFIRST_USER_INTERRUPT_NUMBER (16)
#define portNVIC_IP_REGISTERS_OFFSET_16 (0xE000E3F0)
#define portAIRCR_REG                   (*((volatile uint32_t *)0xE000ED0C))
#define portMAX_8_BIT_VALUE             ((uint8_t)0xff)
#define portTOP_BIT_OF_BYTE             ((uint8_t)0x80)
#define portMAX_PRIGROUP_BITS           ((uint8_t)7)
#define portPRIORITY_GROUP_MASK         (0x07UL << 8UL)
#define portPRIGROUP_SHIFT              (8UL)

/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
#define portVECTACTIVE_MASK (0xFFUL)

/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR (0x01000000UL)

/* The systick is a 24-bit counter. */
#define portMAX_24_BIT_NUMBER (0xffffffUL)

/* A fiddle factor to estimate the number of SysTick counts that would have
 occurred while the SysTick counter is stopped during tickless idle
 calculations. */
#define portMISSED_COUNTS_FACTOR (45UL)

/* For strict compliance with the Cortex-M spec the task start address should
 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ((StackType_t)0xfffffffeUL)

/* Let the user override the pre-loading of the initial LR with the address of
 prvTaskExitError() in case it messes up unwinding of the stack in the
 debugger. */
#ifdef configTASK_RETURN_ADDRESS
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
#define portTASK_RETURN_ADDRESS prvTaskExitError
#endif

/*
 * Setup the timer to generate the tick interrupts.  The implementation in this
 * file is weak to allow application writers to change the timer used to
 * generate the tick interrupt.
 */
void vPortSetupTimerInterrupt(void);

/*
 * Exception handlers.
 */
void xPortPendSVHandler(void) __attribute__((naked));
void xPortSysTickHandler(void);
void vPortSVCHandler(void) __attribute__((naked));

/*
 * Start first task is a separate function so it can be tested in isolation.
 */
static void prvPortStartFirstTask(void) __attribute__((naked));

/*
 * Used to catch tasks that attempt to return from their implementing function.
 */
static void prvTaskExitError(void);

/*-----------------------------------------------------------*/

/* Each task maintains its own interrupt status in the critical nesting
 variable. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;

/*
 * The number of SysTick increments that make up one tick period.
 */
#if (configUSE_TICKLESS_IDLE == 1)
static uint32_t ulTimerCountsForOneTick = 0;
#endif /* configUSE_TICKLESS_IDLE */

/*
 * The maximum number of tick periods that can be suppressed is limited by the
 * 24 bit resolution of the SysTick timer.
 */
#if (configUSE_TICKLESS_IDLE == 1)
static uint32_t xMaximumPossibleSuppressedTicks = 0;
#endif /* configUSE_TICKLESS_IDLE */

/*
 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
 * power functionality only.
 */
#if (configUSE_TICKLESS_IDLE == 1)
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */

/*
 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
 * FreeRTOS API functions are not called from interrupts that have been assigned
 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
 */
#if (configASSERT_DEFINED == 1)
static uint8_t                       ucMaxSysCallPriority         = 0;
static uint32_t                      ulMaxPRIGROUPValue           = 0;
static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const)portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */

/*-----------------------------------------------------------*/

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) {
  /* Simulate the stack frame as it would be created by a context switch
   interrupt. */
  pxTopOfStack--;                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
  *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
  pxTopOfStack--;
  *pxTopOfStack = ((StackType_t)pxCode) & portSTART_ADDRESS_MASK; /* PC */
  pxTopOfStack--;
  *pxTopOfStack = (StackType_t)portTASK_RETURN_ADDRESS; /* LR */
  pxTopOfStack -= 5;                                    /* R12, R3, R2 and R1. */
  *pxTopOfStack = (StackType_t)pvParameters;            /* R0 */
  pxTopOfStack -= 8;                                    /* R11, R10, R9, R8, R7, R6, R5 and R4. */

  return pxTopOfStack;
}
/*-----------------------------------------------------------*/

static void prvTaskExitError(void) {
  // volatile uint32_t ulDummy = 0UL;

  // /* A function that implements a task must not exit or attempt to return to
  //  its caller as there is nothing to return to.  If a task wants to exit it
  //  should instead call vTaskDelete( NULL ).

  //  Artificially force an assert() to be triggered if configASSERT() is
  //  defined, then stop here so application writers can catch the error. */
  // configASSERT(uxCriticalNesting == ~0UL);
  // portDISABLE_INTERRUPTS();
  // while (ulDummy == 0) {
  //   /* This file calls prvTaskExitError() after the scheduler has been
  //    started to remove a compiler warning about the function being defined
  //    but never called.  ulDummy is used purely to quieten other warnings
  //    about code appearing after this function is called - making ulDummy
  //    volatile makes the compiler think the function could return and
  //    therefore not output an 'unreachable code' warning for code that appears
  //    after it. */
  // }
  for (;;) {
  }
}
/*-----------------------------------------------------------*/

void vPortSVCHandler(void) {
  __asm volatile("    ldr    r3,      pxCurrentTCBConst2 \n" /* Restore the context. */
                 "    ldr    r1,      [r3]               \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
                 "    ldr    r0,      [r1]               \n" /* The first item in pxCurrentTCB is the task top of stack. */
                 "    ldmia  r0!,     {r4-r11}           \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
                 "    msr    psp,      r0                \n" /* Restore the task stack pointer. */
                 "    isb                                \n"
                 "    mov    r0,       #0                \n"
                 "    msr    basepri,  r0                \n"
                 "    orr    r14,      #0xd              \n"
                 "    bx     r14                         \n"
                 "                                       \n"
                 "                    .align 4           \n"
                 "pxCurrentTCBConst2: .word pxCurrentTCB \n");
}
/*-----------------------------------------------------------*/

static void prvPortStartFirstTask(void) {
  __asm volatile("  ldr   r0,   =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
                 "  ldr   r0,  [r0]         \n"
                 "  ldr   r0,  [r0]         \n"
                 "  msr  msp,   r0          \n" /* Set the msp back to the start of the stack. */
                 "  cpsie  i                \n" /* Globally enable interrupts. */
                 "  cpsie  f                \n"
                 "  dsb                     \n"
                 "  isb                     \n"
                 "  svc    0                \n" /* System call to start first task. */
                 "  nop                     \n");
}
/*-----------------------------------------------------------*/

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler(void) {
  /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
   See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
  configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY);

#if (configASSERT_DEFINED == 1)
  {
    volatile uint32_t       ulOriginalPriority;
    volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER);
    volatile uint8_t        ucMaxPriorityValue;

    /* Determine the maximum priority from which ISR safe FreeRTOS API
     functions can be called.  ISR safe functions are those that end in
     "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
     ensure interrupt entry is as fast and simple as possible.

     Save the interrupt priority value that is about to be clobbered. */
    ulOriginalPriority = *pucFirstUserPriorityRegister;

    /* Determine the number of priority bits available.  First write to all
     possible bits. */
    *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;

    /* Read the value back to see how many bits stuck. */
    ucMaxPriorityValue = *pucFirstUserPriorityRegister;

    /* Use the same mask on the maximum system call priority. */
    ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;

    /* Calculate the maximum acceptable priority group value for the number
     of bits read back. */
    ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
    while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) {
      ulMaxPRIGROUPValue--;
      ucMaxPriorityValue <<= (uint8_t)0x01;
    }

#ifdef __NVIC_PRIO_BITS
    {
      /* Check the CMSIS configuration that defines the number of
      priority bits matches the number of priority bits actually queried
      from the hardware. */
      configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS);
    }
#endif

#ifdef configPRIO_BITS
    {
      /* Check the FreeRTOS configuration that defines the number of
      priority bits matches the number of priority bits actually queried
      from the hardware. */
      configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS);
    }
#endif

    /* Shift the priority group value back to its position within the AIRCR
     register. */
    ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
    ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;

    /* Restore the clobbered interrupt priority register to its original
     value. */
    *pucFirstUserPriorityRegister = ulOriginalPriority;
  }
#endif /* conifgASSERT_DEFINED */

  /* Make PendSV and SysTick the lowest priority interrupts. */
  portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
  portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;

  /* Start the timer that generates the tick ISR.  Interrupts are disabled
   here already. */
  vPortSetupTimerInterrupt();

  /* Initialise the critical nesting count ready for the first task. */
  uxCriticalNesting = 0;

  /* Start the first task. */
  prvPortStartFirstTask();

  /* Should never get here as the tasks will now be executing!  Call the task
   exit error function to prevent compiler warnings about a static function
   not being called in the case that the application writer overrides this
   functionality by defining configTASK_RETURN_ADDRESS.  Call
   vTaskSwitchContext() so link time optimisation does not remove the
   symbol. */
  vTaskSwitchContext();
  prvTaskExitError();

  /* Should not get here! */
  return 0;
}
/*-----------------------------------------------------------*/

void vPortEndScheduler(void) {
  /* Not implemented in ports where there is nothing to return to.
   Artificially force an assert. */
  configASSERT(uxCriticalNesting == 1000UL);
}
/*-----------------------------------------------------------*/

void vPortEnterCritical(void) {
  portDISABLE_INTERRUPTS();
  uxCriticalNesting++;

  /* This is not the interrupt safe version of the enter critical function so
   assert() if it is being called from an interrupt context.  Only API
   functions that end in "FromISR" can be used in an interrupt.  Only assert if
   the critical nesting count is 1 to protect against recursive calls if the
   assert function also uses a critical section. */
  if (uxCriticalNesting == 1) {
    configASSERT((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0);
  }
}
/*-----------------------------------------------------------*/

void vPortExitCritical(void) {
  configASSERT(uxCriticalNesting);
  uxCriticalNesting--;
  if (uxCriticalNesting == 0) {
    portENABLE_INTERRUPTS();
  }
}
/*-----------------------------------------------------------*/

void xPortPendSVHandler(void) {
  /* This is a naked function. */

  __asm volatile("	mrs r0, psp							\n"
                 "	isb									\n"
                 "										\n"
                 "	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
                 "	ldr	r2, [r3]						\n"
                 "										\n"
                 "	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
                 "	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
                 "										\n"
                 "	stmdb sp!, {r3, r14}				\n"
                 "	mov r0, %0							\n"
                 "	msr basepri, r0						\n"
                 "	bl vTaskSwitchContext				\n"
                 "	mov r0, #0							\n"
                 "	msr basepri, r0						\n"
                 "	ldmia sp!, {r3, r14}				\n"
                 "										\n" /* Restore the context, including the critical nesting count. */
                 "	ldr r1, [r3]						\n"
                 "	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
                 "	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
                 "	msr psp, r0							\n"
                 "	isb									\n"
                 "	bx r14								\n"
                 "										\n"
                 "	.align 4							\n"
                 "pxCurrentTCBConst: .word pxCurrentTCB	\n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY));
}
/*-----------------------------------------------------------*/

void xPortSysTickHandler(void) {
  /* The SysTick runs at the lowest interrupt priority, so when this interrupt
   executes all interrupts must be unmasked.  There is therefore no need to
   save and then restore the interrupt mask value as its value is already
   known. */
  portDISABLE_INTERRUPTS();
  {
    /* Increment the RTOS tick. */
    if (xTaskIncrementTick() != pdFALSE) {
      /* A context switch is required.  Context switching is performed in
       the PendSV interrupt.  Pend the PendSV interrupt. */
      portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
    }
  }
  portENABLE_INTERRUPTS();
}
/*-----------------------------------------------------------*/

#if (configUSE_TICKLESS_IDLE == 1)

__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
  uint32_t   ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
  TickType_t xModifiableIdleTime;

  /* Make sure the SysTick reload value does not overflow the counter. */
  if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) {
    xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
  }

  /* Stop the SysTick momentarily.  The time the SysTick is stopped for
  is accounted for as best it can be, but using the tickless mode will
  inevitably result in some tiny drift of the time maintained by the
  kernel with respect to calendar time. */
  portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;

  /* Calculate the reload value required to wait xExpectedIdleTime
  tick periods.  -1 is used because this code will execute part way
  through one of the tick periods. */
  ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL));
  if (ulReloadValue > ulStoppedTimerCompensation) {
    ulReloadValue -= ulStoppedTimerCompensation;
  }

  /* Enter a critical section but don't use the taskENTER_CRITICAL()
  method as that will mask interrupts that should exit sleep mode. */
  __asm volatile("cpsid i" ::: "memory");
  __asm volatile("dsb");
  __asm volatile("isb");

  /* If a context switch is pending or a task is waiting for the scheduler
  to be unsuspended then abandon the low power entry. */
  if (eTaskConfirmSleepModeStatus() == eAbortSleep) {
    /* Restart from whatever is left in the count register to complete
    this tick period. */
    portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;

    /* Restart SysTick. */
    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;

    /* Reset the reload register to the value required for normal tick
    periods. */
    portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;

    /* Re-enable interrupts - see comments above the cpsid instruction()
    above. */
    __asm volatile("cpsie i" ::: "memory");
  } else {
    /* Set the new reload value. */
    portNVIC_SYSTICK_LOAD_REG = ulReloadValue;

    /* Clear the SysTick count flag and set the count value back to
    zero. */
    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;

    /* Restart SysTick. */
    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;

    /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
    set its parameter to 0 to indicate that its implementation contains
    its own wait for interrupt or wait for event instruction, and so wfi
    should not be executed again.  However, the original expected idle
    time variable must remain unmodified, so a copy is taken. */
    xModifiableIdleTime = xExpectedIdleTime;
    configPRE_SLEEP_PROCESSING(xModifiableIdleTime);
    if (xModifiableIdleTime > 0) {
      __asm volatile("dsb" ::: "memory");
      __asm volatile("wfi");
      __asm volatile("isb");
    }
    configPOST_SLEEP_PROCESSING(xExpectedIdleTime);

    /* Re-enable interrupts to allow the interrupt that brought the MCU
    out of sleep mode to execute immediately.  see comments above
    __disable_interrupt() call above. */
    __asm volatile("cpsie i" ::: "memory");
    __asm volatile("dsb");
    __asm volatile("isb");

    /* Disable interrupts again because the clock is about to be stopped
    and interrupts that execute while the clock is stopped will increase
    any slippage between the time maintained by the RTOS and calendar
    time. */
    __asm volatile("cpsid i" ::: "memory");
    __asm volatile("dsb");
    __asm volatile("isb");

    /* Disable the SysTick clock without reading the
    portNVIC_SYSTICK_CTRL_REG register to ensure the
    portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
    the time the SysTick is stopped for is accounted for as best it can
    be, but using the tickless mode will inevitably result in some tiny
    drift of the time maintained by the kernel with respect to calendar
    time*/
    portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT);

    /* Determine if the SysTick clock has already counted to zero and
    been set back to the current reload value (the reload back being
    correct for the entire expected idle time) or if the SysTick is yet
    to count to zero (in which case an interrupt other than the SysTick
    must have brought the system out of sleep mode). */
    if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) {
      uint32_t ulCalculatedLoadValue;

      /* The tick interrupt is already pending, and the SysTick count
      reloaded with ulReloadValue.  Reset the
      portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
      period. */
      ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL) - (ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG);

      /* Don't allow a tiny value, or values that have somehow
      underflowed because the post sleep hook did something
      that took too long. */
      if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) {
        ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL);
      }

      portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;

      /* As the pending tick will be processed as soon as this
      function exits, the tick value maintained by the tick is stepped
      forward by one less than the time spent waiting. */
      ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
    } else {
      /* Something other than the tick interrupt ended the sleep.
      Work out how long the sleep lasted rounded to complete tick
      periods (not the ulReload value which accounted for part
      ticks). */
      ulCompletedSysTickDecrements = (xExpectedIdleTime * ulTimerCountsForOneTick) - portNVIC_SYSTICK_CURRENT_VALUE_REG;

      /* How many complete tick periods passed while the processor
      was waiting? */
      ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;

      /* The reload value is set to whatever fraction of a single tick
      period remains. */
      portNVIC_SYSTICK_LOAD_REG = ((ulCompleteTickPeriods + 1UL) * ulTimerCountsForOneTick) - ulCompletedSysTickDecrements;
    }

    /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
    again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
    value. */
    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
    portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
    vTaskStepTick(ulCompleteTickPeriods);
    portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;

    /* Exit with interrupts enabled. */
    __asm volatile("cpsie i" ::: "memory");
  }
}

#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/

/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__((weak)) void vPortSetupTimerInterrupt(void) {
  /* Calculate the constants required to configure the tick interrupt. */
#if (configUSE_TICKLESS_IDLE == 1)
  {
    ulTimerCountsForOneTick         = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ);
    xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
    ulStoppedTimerCompensation      = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ);
  }
#endif /* configUSE_TICKLESS_IDLE */

  /* Stop and clear the SysTick. */
  portNVIC_SYSTICK_CTRL_REG          = 0UL;
  portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;

  /* Configure SysTick to interrupt at the requested rate. */
  portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL;
  portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT);
}
/*-----------------------------------------------------------*/

#if (configASSERT_DEFINED == 1)

void vPortValidateInterruptPriority(void) {
  uint32_t ulCurrentInterrupt;
  uint8_t  ucCurrentPriority;

  /* Obtain the number of the currently executing interrupt. */
  __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");

  /* Is the interrupt number a user defined interrupt? */
  if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) {
    /* Look up the interrupt's priority. */
    ucCurrentPriority = pcInterruptPriorityRegisters[ulCurrentInterrupt];

    /* The following assertion will fail if a service routine (ISR) for
     an interrupt that has been assigned a priority above
     configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
     function.  ISR safe FreeRTOS API functions must *only* be called
     from interrupts that have been assigned a priority at or below
     configMAX_SYSCALL_INTERRUPT_PRIORITY.

     Numerically low interrupt priority numbers represent logically high
     interrupt priorities, therefore the priority of the interrupt must
     be set to a value equal to or numerically *higher* than
     configMAX_SYSCALL_INTERRUPT_PRIORITY.

     Interrupts that	use the FreeRTOS API must not be left at their
     default priority of	zero as that is the highest possible priority,
     which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
     and	therefore also guaranteed to be invalid.

     FreeRTOS maintains separate thread and ISR API functions to ensure
     interrupt entry is as fast and simple as possible.

     The following links provide detailed information:
     http://www.freertos.org/RTOS-Cortex-M3-M4.html
     http://www.freertos.org/FAQHelp.html */
    configASSERT(ucCurrentPriority >= ucMaxSysCallPriority);
  }

  /* Priority grouping:  The interrupt controller (NVIC) allows the bits
   that define each interrupt's priority to be split between bits that
   define the interrupt's pre-emption priority bits and bits that define
   the interrupt's sub-priority.  For simplicity all bits must be defined
   to be pre-emption priority bits.  The following assertion will fail if
   this is not the case (if some bits represent a sub-priority).

   If the application only uses CMSIS libraries for interrupt
   configuration then the correct setting can be achieved on all Cortex-M
   devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
   scheduler.  Note however that some vendor specific peripheral libraries
   assume a non-zero priority group setting, in which cases using a value
   of zero will result in unpredictable behaviour. */
  configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue);
}

#endif /* configASSERT_DEFINED */


================================================
FILE: source/Core/BSP/Sequre/portmacro.h
================================================
/*
 * FreeRTOS Kernel V10.3.1
 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * http://www.FreeRTOS.org
 * http://aws.amazon.com/freertos
 *
 * 1 tab == 4 spaces!
 */

#ifndef PORTMACRO_H
#define PORTMACRO_H
#include "FreeRTOSConfig.h"
#include "projdefs.h"

#ifdef __cplusplus
extern "C" {
#endif

/*-----------------------------------------------------------
 * Port specific definitions.
 *
 * The settings in this file configure FreeRTOS correctly for the
 * given hardware and compiler.
 *
 * These settings should not be altered.
 *-----------------------------------------------------------
 */

/* Type definitions. */
#define portCHAR       char
#define portFLOAT      float
#define portDOUBLE     double
#define portLONG       long
#define portSHORT      short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE  long

typedef portSTACK_TYPE StackType_t;
typedef long           BaseType_t;
typedef unsigned long  UBaseType_t;

#if (configUSE_16_BIT_TICKS == 1)
typedef uint16_t TickType_t;
#define portMAX_DELAY (TickType_t)0xffff
#else
typedef uint32_t TickType_t;
#define portMAX_DELAY           (TickType_t)0xffffffffUL

/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
 not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
/*-----------------------------------------------------------*/

/* Architecture specifics. */
#define portSTACK_GROWTH   (-1)
#define portTICK_PERIOD_MS ((TickType_t)1000 / configTICK_RATE_HZ)
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/

/* Scheduler utilities. */
#define portYIELD()                                                            \
  {                                                                            \
    /* Set a PendSV to request a context switch. */                            \
    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                            \
                                                                               \
    /* Barriers are normally not required but do ensure the code is completely \
    within the specified behaviour for the architecture. */                    \
    __asm volatile("dsb" ::: "memory");                                        \
    __asm volatile("isb");                                                     \
  }

#define portNVIC_INT_CTRL_REG  (*((volatile uint32_t *)0xe000ed04))
#define portNVIC_PENDSVSET_BIT (1UL << 28UL)
#define portEND_SWITCHING_ISR(xSwitchRequired) \
  if (xSwitchRequired != pdFALSE)              \
  portYIELD()
#define portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR(x)
/*-----------------------------------------------------------*/

/* Critical section management. */
extern void vPortEnterCritical(void);
extern void vPortExitCritical(void);
#define portSET_INTERRUPT_MASK_FROM_ISR()    ulPortRaiseBASEPRI()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
#define portDISABLE_INTERRUPTS()             vPortRaiseBASEPRI()
#define portENABLE_INTERRUPTS()              vPortSetBASEPRI(0)
#define portENTER_CRITICAL()                 vPortEnterCritical()
#define portEXIT_CRITICAL()                  vPortExitCritical()

/*-----------------------------------------------------------*/

/* Task function macros as described on the FreeRTOS.org WEB site.  These are
 not necessary for to use this port.  They are defined so the common demo files
 (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
/*-----------------------------------------------------------*/

/* Tickless idle/low power functionality. */
#ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
#endif
/*-----------------------------------------------------------*/

/* Architecture specific optimisations. */
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif

#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1

/* Generic helper function. */
__attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) {
  uint8_t ucReturn;

  __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory");
  return ucReturn;
}

/* Check the configuration. */
#if (configMAX_PRIORITIES > 32)
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
#endif

/* Store/clear the ready priorities in a bit map. */
#define portRECORD_READY_PRIORITY(uxPriority, uxReadyPriorities) (uxReadyPriorities) |= (1UL << (uxPriority))
#define portRESET_READY_PRIORITY(uxPriority, uxReadyPriorities)  (uxReadyPriorities) &= ~(1UL << (uxPriority))

/*-----------------------------------------------------------*/

#define portGET_HIGHEST_PRIORITY(uxTopPriority, uxReadyPriorities) uxTopPriority = (31UL - (uint32_t)ucPortCountLeadingZeros((uxReadyPriorities)))

#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

/*-----------------------------------------------------------*/

#ifdef configASSERT
void vPortValidateInterruptPriority(void);
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif

/* portNOP() is not required by this port. */
#define portNOP()

#define portINLINE __inline

#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__((always_inline))
#endif

/*-----------------------------------------------------------*/

portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) {
  uint32_t   ulCurrentInterrupt;
  BaseType_t xReturn;

  /* Obtain the number of the currently executing interrupt. */
  __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory");

  if (ulCurrentInterrupt == 0) {
    xReturn = pdFALSE;
  } else {
    xReturn = pdTRUE;
  }

  return xReturn;
}

/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortRaiseBASEPRI(void) {
  uint32_t ulNewBASEPRI;

  __asm volatile("	mov %0, %1												\n"
                 "	msr basepri, %0											\n"
                 "	isb														\n"
                 "	dsb														\n"
                 : "=r"(ulNewBASEPRI)
                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
                 : "memory");
}

/*-----------------------------------------------------------*/

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) {
  uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

  __asm volatile("	mrs %0, basepri											\n"
                 "	mov %1, %2												\n"
                 "	msr basepri, %1											\n"
                 "	isb														\n"
                 "	dsb														\n"
                 : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI)
                 : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
                 : "memory");

  /* This return will not be reached but is necessary to prevent compiler
   warnings. */
  return ulOriginalBASEPRI;
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) { __asm volatile("	msr basepri, %0	" ::"r"(ulNewMaskValue) : "memory"); }
/*-----------------------------------------------------------*/

#define portMEMORY_BARRIER() __asm volatile("" ::: "memory")

#ifdef __cplusplus
}
#endif

#endif /* PORTMACRO_H */


================================================
FILE: source/Core/BSP/Sequre/postRTOS.cpp
================================================
#include "BSP.h"

// Initialisation to be performed with scheduler active
void postRToSInit() {}


================================================
FILE: source/Core/BSP/Sequre/preRTOS.cpp
================================================
/*
 * preRTOS.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BSP.h"
#include "I2CBB2.hpp"
#include "Pins.h"
#include "Setup.h"
#include 

void preRToSInit() {
  /* Reset of all peripherals, Initializes the Flash interface and the Systick.
   */
  HAL_Init();
  Setup_HAL(); // Setup all the HAL objects
  BSPInit();
#ifdef I2C_SOFT_BUS_2
  I2CBB2::init();
#endif
}


================================================
FILE: source/Core/BSP/Sequre/stm32f103.ld
================================================


/* Entry Point */
ENTRY(Reset_Handler)

/* Highest address of the user mode stack */
_estack = 0x20005000;    /* end of RAM */

_Min_Heap_Size = 0x300;      /* required amount of heap  */
_Min_Stack_Size = 1024; /* required amount of stack */

__APP_BASE_ADDRESS__ = 0x08000000 + __BOOTLDR_SIZE__;
__ROM_REGION_LENGTH__ = __FLASH_SIZE__ - __BOOTLDR_SIZE__;
__FLASH_END_ADDR__ = __APP_BASE_ADDRESS__ + __ROM_REGION_LENGTH__;

/* Memories definition */
MEMORY
{
  RAM (xrw)		: ORIGIN = 0x20000000, LENGTH = 20K
  ROM (rx)		: ORIGIN = __APP_BASE_ADDRESS__, LENGTH = __ROM_REGION_LENGTH__
}
/* ROM is normally 48K after the bootloader, however we allocate the last page for settings, and the second last one for display boot logo*/

/* Sections */
SECTIONS
{
  /* The startup code into ROM memory */
  .isr_vector :
  {
    . = ALIGN(4);
    KEEP(*(.isr_vector)) /* Startup code */
    . = ALIGN(4);
  } >ROM

  /* The program code and other data into ROM memory */
  .text :
  {
    . = ALIGN(4);
    *(.text)           /* .text sections (code) */
    *(.text*)          /* .text* sections (code) */
    *(.glue_7)         /* glue arm to thumb code */
    *(.glue_7t)        /* glue thumb to arm code */
    *(.eh_frame)

    KEEP (*(.init))
    KEEP (*(.fini))

    . = ALIGN(4);
    _etext = .;        /* define a global symbols at end of code */
  } >ROM

  /* Constant data into ROM memory*/
  .rodata :
  {
    . = ALIGN(4);
    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
    . = ALIGN(4);
  } >ROM

  .ARM.extab   : { 
  	. = ALIGN(4);
  	*(.ARM.extab* .gnu.linkonce.armextab.*)
  	. = ALIGN(4);
  } >ROM
  
  .ARM : {
    . = ALIGN(4);
    __exidx_start = .;
    *(.ARM.exidx*)
    __exidx_end = .;
    . = ALIGN(4);
  } >ROM

  .preinit_array     :
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP (*(.preinit_array*))
    PROVIDE_HIDDEN (__preinit_array_end = .);
    . = ALIGN(4);
  } >ROM
  
  .init_array :
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP (*(SORT(.init_array.*)))
    KEEP (*(.init_array*))
    PROVIDE_HIDDEN (__init_array_end = .);
    . = ALIGN(4);
  } >ROM
  
  .fini_array :
  {
    . = ALIGN(4);
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP (*(SORT(.fini_array.*)))
    KEEP (*(.fini_array*))
    PROVIDE_HIDDEN (__fini_array_end = .);
    . = ALIGN(4);
  } >ROM

  /* Used by the startup to initialize data */
  _sidata = LOADADDR(.data);

  /* Initialized data sections into RAM memory */
  .data : 
  {
    . = ALIGN(4);
    _sdata = .;        /* create a global symbol at data start */
    *(.data)           /* .data sections */
    *(.data*)          /* .data* sections */

    . = ALIGN(4);
    _edata = .;        /* define a global symbol at data end */
  } >RAM AT> ROM


  .bss :
  {
    /* Uninitialized data section into RAM memory */
    . = ALIGN(4);
    /* This is used by the startup in order to initialize the .bss secion */
    _sbss = .;         /* define a global symbol at bss start */
    __bss_start__ = _sbss;
    *(.bss)
    *(.bss*)
    *(COMMON)

    . = ALIGN(4);
    _ebss = .;         /* define a global symbol at bss end */
    __bss_end__ = _ebss;
  } >RAM

  /* User_heap_stack section, used to check that there is enough RAM left */
  ._user_heap_stack :
  {
    . = ALIGN(8);
    PROVIDE ( end = . );
    PROVIDE ( _end = . );
    . = . + _Min_Heap_Size;
    . = . + _Min_Stack_Size;
    . = ALIGN(8);
  } >RAM

  

  /* Remove information from the compiler libraries */
  /DISCARD/ :
  {
    libc.a ( * )
    libm.a ( * )
    libgcc.a ( * )
  }

  .ARM.attributes 0 : { *(.ARM.attributes) }
}


================================================
FILE: source/Core/BSP/Sequre/stm32f1xx_hal_msp.c
================================================
#include "Pins.h"
#include "Setup.h"
#include "stm32f1xx_hal.h"
/**
 * Initializes the Global MSP.
 */
void HAL_MspInit(void) {
  __HAL_RCC_AFIO_CLK_ENABLE();

  // HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);

  /* System interrupt init*/
  /* MemoryManagement_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
  /* BusFault_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
  /* UsageFault_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
  /* SVCall_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
  /* DebugMonitor_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
  /* SysTick_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}

void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {

  GPIO_InitTypeDef GPIO_InitStruct;
  if (hadc->Instance == ADC1) {
    __HAL_RCC_ADC1_CLK_ENABLE();

    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance                 = DMA1_Channel1;
    hdma_adc1.Init.Direction           = DMA_PERIPH_TO_MEMORY;
    hdma_adc1.Init.PeriphInc           = DMA_PINC_DISABLE;
    hdma_adc1.Init.MemInc              = DMA_MINC_ENABLE;
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
    hdma_adc1.Init.MemDataAlignment    = DMA_MDATAALIGN_HALFWORD;
    hdma_adc1.Init.Mode                = DMA_CIRCULAR;
    hdma_adc1.Init.Priority            = DMA_PRIORITY_MEDIUM;
    HAL_DMA_Init(&hdma_adc1);

    __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc1);

    /* ADC1 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  } else {
    __HAL_RCC_ADC2_CLK_ENABLE();

    /**ADC2 GPIO Configuration
     PB0     ------> ADC2_IN8
     PB1     ------> ADC2_IN9
     */

    GPIO_InitStruct.Pin  = TIP_TEMP_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(TIP_TEMP_GPIO_Port, &GPIO_InitStruct);
#ifdef TMP36_INPUT_Pin
    GPIO_InitStruct.Pin  = TMP36_INPUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(TMP36_INPUT_GPIO_Port, &GPIO_InitStruct);
#endif
    GPIO_InitStruct.Pin  = VIN_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(VIN_GPIO_Port, &GPIO_InitStruct);

    /* ADC2 interrupt Init */
    HAL_NVIC_SetPriority(ADC1_2_IRQn, 15, 0);
    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
  }
}

void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim_base) {
  if (htim_base->Instance == TIM4) {
    /* Peripheral clock enable */
    __HAL_RCC_TIM4_CLK_ENABLE();
  }
  if (htim_base->Instance == TIM2) {
    /* Peripheral clock enable */
    __HAL_RCC_TIM2_CLK_ENABLE();
  }
}


================================================
FILE: source/Core/BSP/Sequre/stm32f1xx_hal_timebase_TIM.c
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_timebase_TIM.c
 * @brief   HAL time base based on the hardware TIM.
 ******************************************************************************
 * This notice applies to any and all portions of this file
 * that are not between comment pairs USER CODE BEGIN and
 * USER CODE END. Other portions of this file, whether
 * inserted by the user or by software development tools
 * are owned by their respective copyright owners.
 *
 * Copyright (c) 2017 STMicroelectronics International N.V.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted, provided that the following conditions are met:
 *
 * 1. Redistribution of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. Neither the name of STMicroelectronics nor the names of other
 *    contributors to this software may be used to endorse or promote products
 *    derived from this software without specific written permission.
 * 4. This software, including modifications and/or derivative works of this
 *    software, must execute solely and exclusively on microcontroller or
 *    microprocessor devices manufactured by or for STMicroelectronics.
 * 5. Redistribution and use of this software other than as permitted under
 *    this license is void and will automatically terminate your rights under
 *    this license.
 *
 * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
 * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
 * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
 * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#include "stm32f1xx_hal_tim.h"
/** @addtogroup STM32F7xx_HAL_Examples
 * @{
 */

/** @addtogroup HAL_TimeBase
 * @{
 */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim1;
uint32_t          uwIncrementState = 0;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/**
 * @brief  This function configures the TIM1 as a time base source.
 *         The time source is configured  to have 1ms time base with a dedicated
 *         Tick interrupt priority.
 * @note   This function is called  automatically at the beginning of program after
 *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
 * @param  TickPriority: Tick interrupt priorty.
 * @retval HAL status
 */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
  RCC_ClkInitTypeDef clkconfig;
  uint32_t           uwTimclock       = 0;
  uint32_t           uwPrescalerValue = 0;
  uint32_t           pFLatency;

  /*Configure the TIM1 IRQ priority */
  HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority, 0);

  /* Enable the TIM1 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);

  /* Enable TIM1 clock */
  __HAL_RCC_TIM1_CLK_ENABLE();

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);

  /* Compute TIM1 clock */
  uwTimclock = HAL_RCC_GetPCLK2Freq();

  /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t)((uwTimclock / 1000000) - 1);

  /* Initialize TIM1 */
  htim1.Instance = TIM1;

  /* Initialize TIMx peripheral as follow:
   + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base.
   + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
   + ClockDivision = 0
   + Counter direction = Up
   */
  htim1.Init.Period        = (1000000 / 1000) - 1;
  htim1.Init.Prescaler     = uwPrescalerValue;
  htim1.Init.ClockDivision = 0;
  htim1.Init.CounterMode   = TIM_COUNTERMODE_UP;
  if (HAL_TIM_Base_Init(&htim1) == HAL_OK) {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim1);
  }

  /* Return function status */
  return HAL_ERROR;
}

/**
 * @brief  Suspend Tick increment.
 * @note   Disable the tick increment by disabling TIM1 update interrupt.
 * @param  None
 * @retval None
 */
void HAL_SuspendTick(void) {
  /* Disable TIM1 update Interrupt */
  __HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE);
}

/**
 * @brief  Resume Tick increment.
 * @note   Enable the tick increment by Enabling TIM1 update interrupt.
 * @param  None
 * @retval None
 */
void HAL_ResumeTick(void) {
  /* Enable TIM1 Update interrupt */
  __HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE);
}

/**
 * @}
 */

/**
 * @}
 */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/BSP/Sequre/stm32f1xx_it.c
================================================
// This is the stock standard STM interrupt file full of handlers
#include "stm32f1xx_it.h"
#include "Setup.h"
#include "cmsis_os.h"
#include "stm32f1xx.h"
#include "stm32f1xx_hal.h"

extern TIM_HandleTypeDef htim1; // used for the systick

/******************************************************************************/
/*            Cortex-M3 Processor Interruption and Exception Handlers         */
/******************************************************************************/

// Systick is used by FreeRTOS tick
void SysTick_Handler(void) { osSystickHandler(); }

/******************************************************************************/
/* STM32F1xx Peripheral Interrupt Handlers                                    */
/* Add here the Interrupt Handlers for the used peripherals.                  */
/* For the available peripheral interrupt handler names,                      */
/* please refer to the startup file.					                      */
/******************************************************************************/

// DMA used to move the ADC readings into system ram
void DMA1_Channel1_IRQHandler(void) { HAL_DMA_IRQHandler(&hdma_adc1); }
// ADC interrupt used for DMA
void ADC1_2_IRQHandler(void) { HAL_ADC_IRQHandler(&hadc1); }

// Timer 1 has overflowed, used for HAL ticks
void TIM1_UP_IRQHandler(void) { HAL_TIM_IRQHandler(&htim1); }

// Timer 2 is used for co-ordination of PWM & ADC
void TIM4_IRQHandler(void) { HAL_TIM_IRQHandler(&htim4); }
void TIM2_IRQHandler(void) { HAL_TIM_IRQHandler(&htim2); }

void EXTI9_5_IRQHandler(void) { HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); }


================================================
FILE: source/Core/BSP/Sequre/system_stm32f1xx.c
================================================
// This file was automatically generated by the STM Cube software
// And as such, is BSD licneced from STM
#include "stm32f1xx.h"

#if !defined(HSI_VALUE)
#define HSI_VALUE                                                                                                                                                                                      \
  8000000U /*!< Default value of the Internal oscillator in Hz.                                                                                                                                        \
                This value can be provided and adapted by the user application. */
#endif     /* HSI_VALUE */

/*!< Uncomment the following line if you need to use external SRAM  */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#ifndef VECT_TAB_OFFSET
#error VECT_TAB_OFFSET
#endif
/*******************************************************************************
 *  Clock Definitions
 *******************************************************************************/
#if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
#else                                 /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = 64000000U; /*!< System Clock Frequency (Core Clock) */
#endif

const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8U]  = {0, 0, 0, 0, 1, 2, 3, 4};

/**
 * @brief  Setup the microcontroller system
 *         Initialize the Embedded Flash Interface, the PLL and update the
 *         SystemCoreClock variable.
 * @note   This function should be used only after reset.
 * @param  None
 * @retval None
 */
void SystemInit(void) {
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */

  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;

#if defined(STM32F105xC) || defined(STM32F107xC)
  /* Reset PLL2ON and PLL3ON bits */
  RCC->CR &= 0xEBFFFFFFU;

  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x00FF0000U;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE)
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
#endif /* STM32F105xC */

#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
  SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}

/**
 * @brief  Update SystemCoreClock variable according to Clock Register Values.
 *         The SystemCoreClock variable contains the core clock (HCLK), it can
 *         be used by the user application to setup the SysTick timer or configure
 *         other parameters.
 *
 * @note   Each time the core clock (HCLK) changes, this function must be called
 *         to update SystemCoreClock variable value. Otherwise, any configuration
 *         based on this variable will be incorrect.
 *
 * @note   - The system frequency computed by this function is not the real
 *           frequency in the chip. It is calculated based on the predefined
 *           constant and the selected clock source:
 *
 *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 *
 *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 *
 *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 *             or HSI_VALUE(*) multiplied by the PLL factors.
 *
 *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
 *             8 MHz) but the real value may vary depending on the variations
 *             in voltage and temperature.
 *
 *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
 *              8 MHz or 25 MHz, depending on the product used), user has to ensure
 *              that HSE_VALUE is same as the real frequency of the crystal used.
 *              Otherwise, this function may have wrong result.
 *
 *         - The result of this function could be not correct when using fractional
 *           value for HSE crystal.
 * @param  None
 * @retval None
 */
void SystemCoreClockUpdate(void) {
  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;

#if defined(STM32F105xC) || defined(STM32F107xC)
  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
#endif /* STM32F105xC */

#if defined(STM32F100xB) || defined(STM32F100xE)
  uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */

  /* Get SYSCLK source -------------------------------------------------------*/
  tmp = RCC->CFGR & RCC_CFGR_SWS;

  switch (tmp) {
  case 0x00U: /* HSI used as system clock */
    SystemCoreClock = HSI_VALUE;
    break;
  case 0x04U: /* HSE used as system clock */
    SystemCoreClock = HSE_VALUE;
    break;
  case 0x08U: /* PLL used as system clock */

    /* Get PLL clock source and multiplication factor ----------------------*/
    pllmull   = RCC->CFGR & RCC_CFGR_PLLMULL;
    pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

#if !defined(STM32F105xC) && !defined(STM32F107xC)
    pllmull = (pllmull >> 18U) + 2U;

    if (pllsource == 0x00U) {
      /* HSI oscillator clock divided by 2 selected as PLL clock entry */
      SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
    } else {
#if defined(STM32F100xB) || defined(STM32F100xE)
      prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
      /* HSE oscillator clock selected as PREDIV1 clock entry */
      SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
      /* HSE selected as PLL clock entry */
      if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) { /* HSE oscillator clock divided by 2 */
        SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
      } else {
        SystemCoreClock = HSE_VALUE * pllmull;
      }
#endif
    }
#else
    pllmull = pllmull >> 18U;

    if (pllmull != 0x0DU) {
      pllmull += 2U;
    } else { /* PLL multiplication factor = PLL input clock * 6.5 */
      pllmull = 13U / 2U;
    }

    if (pllsource == 0x00U) {
      /* HSI oscillator clock divided by 2 selected as PLL clock entry */
      SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
    } else { /* PREDIV1 selected as PLL clock entry */

      /* Get PREDIV1 clock source and division factor */
      prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
      prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;

      if (prediv1source == 0U) {
        /* HSE oscillator clock selected as PREDIV1 clock entry */
        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
      } else { /* PLL2 clock selected as PREDIV1 clock entry */

        /* Get PREDIV2 division factor and PLL2 multiplication factor */
        prediv2factor   = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
        pll2mull        = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
        SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
      }
    }
#endif /* STM32F105xC */
    break;

  default:
    SystemCoreClock = HSI_VALUE;
    break;
  }

  /* Compute HCLK clock frequency ----------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
  /* HCLK clock frequency */
  SystemCoreClock >>= tmp;
}

#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/**
 * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s
 *          before jump to __main
 * @param  None
 * @retval None
 */
#ifdef DATA_IN_ExtSRAM
/**
 * @brief  Setup the external memory controller.
 *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
 *         This function configures the external SRAM mounted on STM3210E-EVAL
 *         board (STM32 High density devices). This SRAM will be used as program
 *         data memory (including heap and stack).
 * @param  None
 * @retval None
 */
void SystemInit_ExtMemCtl(void) {
  __IO uint32_t tmpreg;
  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
    required, then adjust the Register Addresses */

  /* Enable FSMC clock */
  RCC->AHBENR = 0x00000114U;

  /* Delay after an RCC peripheral clock enabling */
  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);

  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  RCC->APB2ENR = 0x000001E0U;

  /* Delay after an RCC peripheral clock enabling */
  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);

  (void)(tmpreg);

  /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
  /*----------------  SRAM Address lines configuration -------------------------*/
  /*----------------  NOE and NWE configuration --------------------------------*/
  /*----------------  NE3 configuration ----------------------------------------*/
  /*----------------  NBL0, NBL1 configuration ---------------------------------*/

  GPIOD->CRL = 0x44BB44BBU;
  GPIOD->CRH = 0xBBBBBBBBU;

  GPIOE->CRL = 0xB44444BBU;
  GPIOE->CRH = 0xBBBBBBBBU;

  GPIOF->CRL = 0x44BBBBBBU;
  GPIOF->CRH = 0xBBBB4444U;

  GPIOG->CRL = 0x44BBBBBBU;
  GPIOG->CRH = 0x444B4B44U;

  /*----------------  FSMC Configuration ---------------------------------------*/
  /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/

  FSMC_Bank1->BTCR[4U] = 0x00001091U;
  FSMC_Bank1->BTCR[5U] = 0x00110212U;
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */

/**
 * @}
 */

/**
 * @}
 */

/**
 * @}
 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/Drivers/BMA223.cpp
================================================
/*
 * BMA223.cpp
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#include "accelerometers_common.h"
#include 
#include 

bool BMA223::detect() {
  if (ACCEL_I2C_CLASS::probe(BMA223_ADDRESS)) {
    // Read chip id to ensure its not an address collision
    uint8_t id = 0;
    if (ACCEL_I2C_CLASS::Mem_Read(BMA223_ADDRESS, BMA223_BGW_CHIPID, &id, 1)) {
      return id == 0b11111000;
    }
  }

  return false;
}

static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
    //
    //
    {    BMA223_PMU_RANGE, 0b00000011, 0}, // 2G range
    {       BMA223_PMU_BW, 0b00001101, 0}, // 250Hz filter
    {      BMA223_PMU_LPW, 0b00000000, 0}, // Full power
    {     BMA223_ACCD_HBW, 0b00000000, 0}, // filtered data out
    { BMA223_INT_OUT_CTRL, 0b00001010, 0}, // interrupt active low and OD to get it hi-z
    {BMA223_INT_RST_LATCH, 0b10000000, 0}, // interrupt active low and OD to get it hi-z
    {     BMA223_INT_EN_0, 0b01000000, 0}, // Enable orientation
    {        BMA223_INT_A, 0b00100111, 0}, // Setup orientation detection

    //
};
bool BMA223::initalize() {
  // Setup acceleration readings
  // 2G range
  // bandwidth = 250Hz
  // High pass filter on (Slow compensation)
  // Turn off IRQ output pins
  // Orientation recognition in symmetrical mode
  // Hysteresis is set to ~ 16 counts
  // Theta blocking is set to 0b10

  return ACCEL_I2C_CLASS::writeRegistersBulk(BMA223_ADDRESS, i2c_registers, sizeof(i2c_registers) / sizeof(i2c_registers[0]));
}

void BMA223::getAxisReadings(int16_t &x, int16_t &y, int16_t &z) {
  // The BMA is odd in that its output data width is only 8 bits
  // And yet there are MSB and LSB registers _sigh_.
  uint8_t sensorData[6] = {0, 0, 0, 0, 0, 0};

  if (ACCEL_I2C_CLASS::Mem_Read(BMA223_ADDRESS, BMA223_ACCD_X_LSB, sensorData, 6) == false) {
    x = y = z = 0;
    return;
  }
  // Shift 6 to make its range ~= the other accelerometers
  x = sensorData[1] << 6;
  y = sensorData[3] << 6;
  z = sensorData[5] << 6;
}


================================================
FILE: source/Core/Drivers/BMA223.hpp
================================================
/*
 * BMA223.hpp
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_BMA223_HPP_
#define CORE_DRIVERS_BMA223_HPP_
#include "BMA223_defines.h"
#include "BSP.h"
#include "accelerometers_common.h"
#include "I2C_Wrapper.hpp"
#include "accelerometers_common.h"


class BMA223 {
public:
  static bool detect();
  static bool initalize();
  // 1 = rh, 2,=lh, 8=flat
  static Orientation getOrientation() {
    uint8_t val = ACCEL_I2C_CLASS::I2C_RegisterRead(BMA223_ADDRESS, BMA223_INT_STATUS_3);
    val >>= 4; // we dont need high values
    val &= 0b11;
    if (val & 0b10) {
      return ORIENTATION_FLAT;
    } else {
      return static_cast(!val);
    }
    // 0 = rhs
    // 1 =lhs
    // 2 & 3 == ignore
  }
  static void getAxisReadings(int16_t &x, int16_t &y, int16_t &z);

private:
};

#endif /* CORE_DRIVERS_BMA223_HPP_ */


================================================
FILE: source/Core/Drivers/BMA223_defines.h
================================================
/*
 * BMA223_defines.h
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_BMA223_DEFINES_H_
#define CORE_DRIVERS_BMA223_DEFINES_H_

#define BMA223_ADDRESS       0x18 << 1
#define BMA223_BGW_CHIPID    0x00
#define BMA223_ACCD_X_LSB    0x02
#define BMA223_ACCD_X_MSB    0x03
#define BMA223_ACCD_Y_LSB    0x04
#define BMA223_ACCD_Y_MSB    0x05
#define BMA223_ACCD_Z_LSB    0x06
#define BMA223_ACCD_Z_MSB    0x07
#define BMA223_ACCD_TEMP     0x08
#define BMA223_INT_STATUS_0  0x09
#define BMA223_INT_STATUS_1  0x0A
#define BMA223_INT_STATUS_2  0x0B
#define BMA223_INT_STATUS_3  0x0C
#define BMA223_FIFO_STATUS   0x0E
#define BMA223_PMU_RANGE     0x0F
#define BMA223_PMU_BW        0x10
#define BMA223_PMU_LPW       0x11
#define BMA223_PMU_LOW_POWER 0x012
#define BMA223_ACCD_HBW      0x13
#define BMA223_BGW_SOFTRESET 0x14
#define BMA223_INT_EN_0      0x16
#define BMA223_INT_EN_1      0x17
#define BMA223_INT_EN_2      0x18
#define BMA223_INT_MAP_0     0x19
#define BMA223_INT_MAP_1     0x1A
#define BMA223_INT_MAP_2     0x1B
#define BMA223_INT_SRC       0x1E
#define BMA223_INT_OUT_CTRL  0x20
#define BMA223_INT_RST_LATCH 0x21
#define BMA223_INT_0         0x22
#define BMA223_INT_1         0x23
#define BMA223_INT_2         0x24
#define BMA223_INT_3         0x25
#define BMA223_INT_4         0x26
#define BMA223_INT_5         0x27
#define BMA223_INT_6         0x28
#define BMA223_INT_7         0x29
#define BMA223_INT_8         0x2A
#define BMA223_INT_9         0x2B
#define BMA223_INT_A         0x2C
#define BMA223_INT_B         0x2D
#define BMA223_INT_C         0x2E
#define BMA223_INT_D         0x2F
#define BMA223_FIFO_CONFIG_0 0x30
#define BMA223_PMU_SELF_TEST 0x32
#define BMA223_TRIM_NVM_CTRL 0x33
#define BMA223_BGW_SPI3_WDT  0x34
#define BMA223_OFC_CTRL      0x36
#define BMA223_OFC_SETTING   0x37
#define BMA223_OFC_OFFSET_X  0x38
#define BMA223_OFC_OFFSET_Y  0x39
#define BMA223_OFC_OFFSET_Z  0x3A
#define BMA223_TRIM_GP0      0x3B
#define BMA223_TRIM_GP1      0x3C
#define BMA223_FIFO_CONFIG_1 0x3E
#define BMA223_FIFO_DATA     0x3F

#endif /* CORE_DRIVERS_BMA223_DEFINES_H_ */


================================================
FILE: source/Core/Drivers/BootLogo.cpp
================================================
#include "BootLogo.h"
#include "BSP.h"
#include "Buttons.hpp"
#include "OLED.hpp"
#include "Settings.h"
#include "cmsis_os.h"

#define LOGO_PAGE_LENGTH 1024

void delay() {
  if (getSettingValue(SettingsOptions::LOGOTime) >= logoMode_t::ONETIME) {
    waitForButtonPress();
  } else {
    waitForButtonPressOrTimeout(TICKS_SECOND * getSettingValue(SettingsOptions::LOGOTime));
  }
}

void BootLogo::handleShowingLogo(const uint8_t *ptrLogoArea) {
  OLED::clearScreen();
  // Read the first few bytes and figure out what format we are looking at
  if (OLD_LOGO_HEADER_VALUE == *(reinterpret_cast(ptrLogoArea))) {
    showOldFormat(ptrLogoArea);
  } else if (ptrLogoArea[0] == 0xAA) {
    showNewFormat(ptrLogoArea + 1);
  }

  OLED::clearScreen();
}

void BootLogo::showOldFormat(const uint8_t *ptrLogoArea) {
#ifdef OLED_128x32
  // Draw in middle
  OLED::drawAreaSwapped(16, 8, 96, 16, (uint8_t *)(ptrLogoArea + 4));

#else
  OLED::drawAreaSwapped(0, 0, 96, 16, (uint8_t *)(ptrLogoArea + 4));

#endif
  OLED::refresh();
  // Delay here with static logo until a button is pressed or its been the amount of seconds set by the user
  delay();
}

void BootLogo::showNewFormat(const uint8_t *ptrLogoArea) {
  if (getSettingValue(SettingsOptions::LOGOTime) == logoMode_t::SKIP) {
    return;
  }

  // New logo format (a) fixes long standing byte swap quirk and (b) supports animation
  uint8_t interFrameDelay = ptrLogoArea[0];
  OLED::clearScreen();

  // Now draw in the frames
  int position = 1;
  while (getButtonState() == BUTTON_NONE) {
    int len = (showNewFrame(ptrLogoArea + position));
    OLED::refresh();
    position += len;

    if (interFrameDelay) {
      osDelay(interFrameDelay * 4);
    }

    // 1024 less the header type byte and the inter-frame-delay
    if (getSettingValue(SettingsOptions::LOGOTime) && (position >= 1022 || len == 0)) {
      // Animated logo stops here ...
      if (getSettingValue(SettingsOptions::LOGOTime) == logoMode_t::INFINITY) {
        // ... but if it's infinite logo setting then keep it rolling over again until a button is pressed
        osDelay(4 * TICKS_100MS);
        OLED::clearScreen();
        position = 1;
        continue;
      }
    } else {
      // Animation in progress so jumping to the next frame
      continue;
    }

    // Static logo case ends up right here, so delay until a button is pressed or its been the amount of seconds set by the user
    delay();
    return;
  }
}

int BootLogo::showNewFrame(const uint8_t *ptrLogoArea) {
  uint8_t length = ptrLogoArea[0];
  switch (length) {
  case 0:
    // End
    return 0;
    break;
  case 0xFE:
    return 1;
    break;
  case 0xFF:
// Full frame update
#ifdef OLED_128x32
    OLED::drawArea(16, 8, 96, 16, ptrLogoArea + 1);
#else
    OLED::drawArea(0, 0, 96, 16, ptrLogoArea + 1);
#endif
    length = 96;
    break;
  default:
    length /= 2;
    // Draw length patches
    for (int p = 0; p < length; p++) {
      uint8_t index = ptrLogoArea[1 + (p * 2)];
      uint8_t value = ptrLogoArea[2 + (p * 2)];
#ifdef OLED_128x32
      OLED::drawArea(16 + (index % 96), index >= 96 ? 16 : 8, 1, 8, &value);
#else
      OLED::drawArea(index % 96, index >= 96 ? 8 : 0, 1, 8, &value);
#endif
    }
  }

  OLED::refresh();
  return (length * 2) + 1;
}


================================================
FILE: source/Core/Drivers/BootLogo.h
================================================
#ifndef DRIVERS_BOOTLOGO_H_
#define DRIVERS_BOOTLOGO_H_

// Wrapper for handling showing a bootlogo
#include 
#define OLD_LOGO_HEADER_VALUE 0xF00DAA55
class BootLogo {
public:
  static void handleShowingLogo(const uint8_t *ptrLogoArea);

private:
  static void showOldFormat(const uint8_t *ptrLogoArea);
  static void showNewFormat(const uint8_t *ptrLogoArea);
  static int  showNewFrame(const uint8_t *ptrLogoArea);
};

#endif // DRIVERS_BOOTLOGO_H_

================================================
FILE: source/Core/Drivers/Buttons.cpp
================================================
/*
 * Buttons.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */
#include "FreeRTOS.h"
#include "OperatingModeUtilities.h"
#include "settingsGUI.hpp"
#include "task.h"
#include 
TickType_t lastButtonTime = 0;

ButtonState getButtonState() {
  /*
   * Read in the buttons and then determine if a state change needs to occur
   */

  /*
   * If the previous state was  00 Then we want to latch the new state if
   * different & update time
   * If the previous state was !00 Then we want to search if we trigger long
   * press (buttons still down), or if release we trigger press
   * (downtime>filter)
   */
  static uint8_t    previousState       = 0;
  static bool       longPressed         = false;
  static TickType_t previousStateChange = 0;
  const TickType_t  timeout             = TICKS_100MS * 4;
  uint8_t           currentState;
  currentState = (getButtonA()) << 0;
  currentState |= (getButtonB()) << 1;

  if (currentState) {
    lastButtonTime = xTaskGetTickCount();
  }
  if (currentState == previousState) {
    if (currentState == 0) {
      return BUTTON_NONE;
    }
    if ((xTaskGetTickCount() - previousStateChange) >= timeout) {
      // User has been holding the button down
      // We want to send a button is held message
      longPressed = true;
      if (currentState == 0x01) {
        return BUTTON_F_LONG;
      } else if (currentState == 0x02) {
        return BUTTON_B_LONG;
      } else {
        return BUTTON_BOTH_LONG; // Both being held case
      }
    } else {
      return BUTTON_NONE;
    }
  } else {
    // A change in button state has occurred
    ButtonState retVal = BUTTON_NONE;
    if (currentState) {
      // User has pressed a button down (nothing done on down)
      // If there is a rising edge on one of the buttons from double press we
      // want to mask that out As users are having issues with not release
      // both at once
      previousState |= currentState;
    } else {
      // User has released buttons
      // If they previously had the buttons down we want to check if they were <
      // long hold and trigger a press
      if (!longPressed) {
        // The user didn't hold the button for long
        // So we send button press

        if (previousState == 0x01) {
          retVal = BUTTON_F_SHORT;
        } else if (previousState == 0x02) {
          retVal = BUTTON_B_SHORT;
        } else {
          retVal = BUTTON_BOTH; // Both being held case
        }
      }
      previousState = 0;
      longPressed   = false;
    }
    previousStateChange = xTaskGetTickCount();
    return retVal;
  }
  return BUTTON_NONE;
}

void waitForButtonPress() {
  // we are just lazy and sleep until user confirms button press
  // This also eats the button press event!
  ButtonState buttons = getButtonState();
  while (buttons) {
    buttons = getButtonState();
    GUIDelay();
  }
  while (!buttons) {
    buttons = getButtonState();
    GUIDelay();
  }
}

void waitForButtonPressOrTimeout(TickType_t timeout) {
  timeout += xTaskGetTickCount();
  // calculate the exit point

  ButtonState buttons = getButtonState();
  while (buttons) {
    buttons = getButtonState();
    GUIDelay();
    if (xTaskGetTickCount() > timeout) {
      return;
    }
  }
  while (!buttons) {
    buttons = getButtonState();
    GUIDelay();
    if (xTaskGetTickCount() > timeout) {
      return;
    }
  }
}


================================================
FILE: source/Core/Drivers/Buttons.hpp
================================================
/*
 * Buttons.h
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */
#include "BSP.h"
#ifndef INC_BUTTONS_H_
#define INC_BUTTONS_H_
#include "portmacro.h"
extern TickType_t lastButtonTime;

enum ButtonState {
  BUTTON_NONE      = 0,  /* No buttons pressed / < filter time*/
  BUTTON_F_SHORT   = 1,  /* User has pressed the front button*/
  BUTTON_B_SHORT   = 2,  /* User has pressed the back  button*/
  BUTTON_F_LONG    = 4,  /* User is  holding the front button*/
  BUTTON_B_LONG    = 8,  /* User is  holding the back button*/
  BUTTON_BOTH      = 16, /* User has pressed both buttons*/
  BUTTON_BOTH_LONG = 32, /* User is holding both buttons*/

  /*
   * Note:
   * Pressed means press + release, we trigger on a full \__/ pulse
   * holding means it has gone low, and been low for longer than filter time
   */
};

// Returns what buttons are pressed (if any)
ButtonState getButtonState();
// Helpers
void waitForButtonPressOrTimeout(TickType_t timeout);
void waitForButtonPress();

#endif /* INC_BUTTONS_H_ */


================================================
FILE: source/Core/Drivers/FS2711.cpp
================================================
#include "configuration.h"

#if POW_PD_EXT == 2
#include "BSP.h"
#include "FS2711.hpp"
#include "FS2711_defines.h"
#include "I2CBB2.hpp"
#include "Settings.h"
#include "cmsis_os.h"
#include 
#include 
#include 

#ifndef USB_PD_VMAX
#error Max PD Voltage must be defined
#endif

#define PROTOCOL_TIMEOUT 100 // ms

extern int32_t powerSupplyWattageLimit;

fs2711_state_t FS2711::state;

inline void i2c_write(uint8_t addr, uint8_t data) { I2CBB2::Mem_Write(FS2711_ADDR, addr, &data, 1); }

inline uint8_t i2c_read(uint8_t addr) {
  uint8_t data = 0;
  I2CBB2::Mem_Read(FS2711_ADDR, addr, &data, 1);
  return data;
}

inline bool i2c_probe(uint8_t addr) { return I2CBB2::probe(addr); }

void FS2711::start() {
  memset(&state, 0, sizeof(fs2711_state_t));
  state.req_pdo_num = 0xFF;

  enable_protocol(false);
  osDelay(PROTOCOL_TIMEOUT);
  select_protocol(FS2711_PROTOCOL_PD);
  enable_protocol(true);
  osDelay(PROTOCOL_TIMEOUT);
}

uint8_t FS2711::selected_protocol() { return i2c_read(FS2711_REG_SELECT_PROTOCOL); }

void FS2711::enable_protocol(bool enable) { i2c_write(FS2711_REG_ENABLE_PROTOCOL, enable ? FS2711_ENABLE : FS2711_DISABLE); }

void FS2711::select_protocol(uint8_t protocol) { i2c_write(FS2711_REG_SELECT_PROTOCOL, protocol); }

void FS2711::enable_voltage() { i2c_write(FS2711_REG_ENABLE_VOLTAGE, FS2711_ENABLE); }

bool FS2711::probe() { return i2c_probe(FS2711_ADDR); }

void FS2711::pdo_update() {
  uint8_t pdo_b0 = 0, pdo_b1 = 0, pdo_b2 = 0, pdo_b3 = 0;

  state.pdo_num = 0;
  memset(state.pdo_type, 0, 7);
  memset(state.pdo_min_volt, 0, 7);
  memset(state.pdo_max_volt, 0, 7);
  memset(state.pdo_max_curr, 0, 7);

  for (uint8_t i = 0; i < 7; i++) {
    pdo_b0 = i2c_read(FS2711_REG_PDO_B0 + i * 4);
    pdo_b1 = i2c_read(FS2711_REG_PDO_B1 + i * 4);
    pdo_b2 = i2c_read(FS2711_REG_PDO_B2 + i * 4);
    pdo_b3 = i2c_read(FS2711_REG_PDO_B3 + i * 4);

    if (pdo_b0) {
      if ((pdo_b3 & FS2711_REG_PDO_B0) == FS2711_REG_PDO_B0) {
        state.pdo_type[i]     = FS2711_PDO_PPS;
        state.pdo_min_volt[i] = pdo_b1 * 100;
        state.pdo_max_volt[i] = ((pdo_b2 >> 1) + ((pdo_b3 & 0x1) << 7)) * 100;
        state.pdo_max_curr[i] = (pdo_b0 & 0x7F) * 50;
      } else {
        state.pdo_type[i]     = FS2711_PDO_FIX;
        state.pdo_min_volt[i] = ((pdo_b1 >> 2) + ((pdo_b2 & 0xF) << 6)) * 50;
        state.pdo_max_volt[i] = state.pdo_min_volt[i];
        state.pdo_max_curr[i] = (pdo_b0 + ((pdo_b1 & 0x3) << 8)) * 10;
      }
      state.pdo_num++;
    }
  }
}

bool FS2711::open_pps(uint8_t pdoid, uint16_t volt, uint16_t max_curr) {
  uint16_t wr;

  if (pdoid > state.pdo_num)
    return false;
  if ((volt > state.pdo_max_volt[pdoid]) || (volt < state.pdo_min_volt[pdoid]))
    return false;
  if ((volt > state.pdo_max_volt[pdoid]) || (volt < state.pdo_min_volt[pdoid]))
    return false;
  if (max_curr > state.pdo_max_curr[pdoid])
    return false;
  if (state.pdo_type[pdoid] != FS2711_PDO_PPS)
    return false;

  if (FS2711::selected_protocol() == FS2711_PROTOCOL_PD) {
    select_protocol(FS2711_PROTOCOL_PPS);
    enable_protocol(true);
  }

  if (FS2711::selected_protocol() != FS2711_PROTOCOL_PPS) {
    return false;
  }

  i2c_write(FS2711_REG_PDO_IDX, pdoid + (pdoid << 4));
  wr = (volt - state.pdo_min_volt[pdoid]) / 20;
  i2c_write(FS2711_PROTOCOL_PPS_CURRENT, max_curr / 50);

  i2c_write(FS2711_REG_VOLT_CFG_B0, wr & 0xFF);
  i2c_write(FS2711_REG_VOLT_CFG_B1, (wr >> 8) & 0xFF);
  i2c_write(FS2711_REG_VOLT_CFG_B2, wr & 0xFF);
  i2c_write(FS2711_REG_VOLT_CFG_B3, (wr >> 8) & 0xFF);

  enable_voltage();

  state.source_voltage    = volt;
  state.source_current    = max_curr;
  state.req_pdo_num       = pdoid;
  powerSupplyWattageLimit = ((volt * max_curr) / 1000000) - 2;
  return true;
}

bool FS2711::open_pd(uint8_t pdoid) {
  if (pdoid >= state.pdo_num) {
    return false;
  }
  if (state.pdo_type[pdoid] != FS2711_PDO_FIX) {
    return false;
  }

  if (FS2711::selected_protocol() != FS2711_PROTOCOL_PD) {
    return false;
  }

  i2c_write(FS2711_REG_PDO_IDX, pdoid + (pdoid << 4));

  enable_voltage();

  state.source_voltage = state.pdo_max_volt[pdoid];
  state.source_current = state.pdo_max_curr[pdoid];
  state.req_pdo_num    = pdoid;

  powerSupplyWattageLimit = ((state.source_voltage * state.source_current) / 1000000) - 2;
  return true;
}

void FS2711::negotiate() {
  uint16_t best_voltage = 0;
  uint16_t best_current = 0;
  uint8_t  best_pdoid   = 0xFF;
  bool     pps          = false;

  int min_resistance_omhsx10 = 0;

  // FS2711 uses mV instead of V
  const uint16_t vmax           = USB_PD_VMAX * 1000;
  uint8_t        tip_resistance = getTipResistanceX10();
  if (getSettingValue(SettingsOptions::USBPDMode) == usbpdMode_t::DEFAULT) {
    tip_resistance += 5;
  }

  uint16_t pdo_min_mv = 0, pdo_max_mv = 0, pdo_max_curr = 0, pdo_type = 0;

  FS2711::pdo_update();

  for (int i = 0; state.pdo_num > i; i++) {
    pdo_min_mv   = state.pdo_min_volt[i];
    pdo_max_mv   = state.pdo_max_volt[i];
    pdo_max_curr = state.pdo_max_curr[i];
    pdo_type     = state.pdo_type[i];

    min_resistance_omhsx10 = (pdo_max_mv / pdo_max_curr) * 10;

    switch (pdo_type) {
    case FS2711_PDO_FIX:
      if (pdo_max_mv > 0 && vmax >= pdo_max_mv) {
        if (min_resistance_omhsx10 <= tip_resistance) {
          if (pdo_max_mv > best_voltage) {
            pps          = false;
            best_pdoid   = i;
            best_voltage = pdo_max_mv;
            best_current = pdo_max_curr;
          }
        }
      }
      break;

    case FS2711_PDO_PPS: {
      int ideal_mv = tip_resistance * (pdo_max_curr / 10);
      if (ideal_mv > pdo_max_mv) {
        ideal_mv = pdo_max_mv;
      }

      if (ideal_mv > vmax) {
        ideal_mv = vmax;
      }

      if (ideal_mv > best_voltage) {
        best_pdoid   = i;
        best_voltage = ideal_mv;
        best_current = pdo_max_curr;
        pps          = true;
      }
    }

    break;

    default:
      break;
    }
  }

  if (best_pdoid != 0xFF && best_pdoid != state.req_pdo_num) {
    if (pps) {
      FS2711::open_pps(best_pdoid, best_voltage, best_current);
    } else {
      FS2711::open_pd(best_pdoid);
    }
  }
}

bool FS2711::has_run_selection() { return state.req_pdo_num != 0xFF; }

uint16_t FS2711::source_voltage() { return state.source_voltage / 1000; }

// FS2711 does current in mV so it needs to be converted to x100 intead of x1000
uint16_t FS2711::source_currentx100() { return state.source_current / 10; }

uint16_t FS2711::debug_pdo_max_voltage(uint8_t pdoid) { return state.pdo_max_volt[pdoid]; }

uint16_t FS2711::debug_pdo_min_voltage(uint8_t pdoid) { return state.pdo_min_volt[pdoid]; }

uint16_t FS2711::debug_pdo_source_current(uint8_t pdoid) { return state.pdo_max_curr[pdoid]; }

uint16_t FS2711::debug_pdo_type(uint8_t pdoid) { return state.pdo_type[pdoid]; }

fs2711_state_t FS2711::debug_get_state() { return state; }

#endif


================================================
FILE: source/Core/Drivers/FS2711.hpp
================================================
#include "configuration.h"
#ifndef _DRIVERS_FS2711_HPP_
#define _DRIVERS_FS2711_HPP_
// #define POW_PD_EXT 2
#if POW_PD_EXT == 2
#include 
#include 

typedef struct {
  uint8_t  pdo_num; // Nums of USB-PD Objects max of 7
  uint16_t source_current;
  uint16_t source_voltage;
  uint16_t req_pdo_num;
  uint16_t pdo_type[7];
  uint16_t pdo_min_volt[7];
  uint16_t pdo_max_volt[7];
  uint16_t pdo_max_curr[7];
} fs2711_state_t;

class FS2711 {
public:
  static bool probe();

  static void start();

  static bool open_pps(uint8_t PDOID, uint16_t volt, uint16_t max_curr);

  static bool open_pd(uint8_t PDOID);

  static void negotiate();

  static bool has_run_selection();

  static uint16_t source_voltage();

  static uint16_t source_currentx100();

  static uint8_t selected_protocol();

  static void pdo_update();

  static uint8_t        debug_protocol();
  static uint16_t       debug_pdo_max_voltage(uint8_t pdoid);
  static uint16_t       debug_pdo_min_voltage(uint8_t pdoid);
  static uint16_t       debug_pdo_source_current(uint8_t pdoid);
  static uint16_t       debug_pdo_type(uint8_t pdoid);
  static fs2711_state_t debug_get_state();

private:
  // Internal state of IC
  static fs2711_state_t state;

  static void enable_protocol(bool enable);

  static void select_protocol(uint8_t protocol);

  static void enable_voltage();
};

#endif
#endif


================================================
FILE: source/Core/Drivers/FS2711_defines.h
================================================
#ifndef _FS2711_DEFINE_HPP_
#define _FS2711_DEFINE_HPP_

#define FS2711_WRITE_ADDR 0x5A
#define FS2711_READ_ADDR  0x5B

#define FS2711_ADDR 0x5A

#define FS2711_PDO_FIX 0
#define FS2711_PDO_PPS 1

#define FS2711_MAX_5V  1
#define FS2711_MAX_9V  3
#define FS2711_MAX_12V 7
#define FS2711_MAX_20V 15

#define FS2711_ENABLE  0x1
#define FS2711_DISABLE 0x2

// Protocol Selection
#define FS2711_PROTOCOL_QC2A 4
#define FS2711_PROTOCOL_QC2B 5
#define FS2711_PROTOCOL_QC3A 6
#define FS2711_PROTOCOL_QC3B 7
#define FS2711_PROTOCOL_PPS  20
#define FS2711_PROTOCOL_PD   21

#define FS2711_PROTOCOL_PPS_CURRENT 0xDE

#define FS2711_PROTOCOL_QC_MAX_VOLT 0xC0

#define FS2711_REG_SCAN_START      0x40 // Protocol Scan
#define FS2711_REG_ENABLE_PROTOCOL 0x41 // Enable Protocol
#define FS2711_REG_SELECT_PROTOCOL 0x42 // Select Protocol
#define FS2711_REG_ENABLE_VOLTAGE  0x43 // Enable Voltage
#define FS2711_REG_PDO_IDX         0x46 // Requests Protocol Index
#define FS2711_REG_SWEEP           0x47 // Requests a voltage sweep?
#define FS2711_REG_PORT_RESET      0x49 // Port Reset
#define FS2711_REG_SYSTEM_RESET    0x4A // System Reset
#define FS2711_REG_DPDM            0x51 // DPDM
#define FS2711_REG_MODE_SET        0xA0 // Mode set
#define FS2711_REG_STATE0          0xB1 // PD:A_SNK PD:A_SRC (PD:pe_ready POM:crc_success) (PD:soft_reset POM:crc_fail) (PD:hard_rest POM:resp_fail) PD:hardreset_found VIVO
#define FS2711_REG_STATE1          0xB2 // scan_done pdo_updated vooc_recv_cmd vivo_pom_tx_finish vivo_pom_rx_finish huawei_comm_fail huawei_op_finish

// Used to calculate PDO Objects
#define FS2711_REG_PDO_B0 0xC0
#define FS2711_REG_PDO_B1 0xC1
#define FS2711_REG_PDO_B2 0xC2
#define FS2711_REG_PDO_B3 0xC3

#define FS2711_REG_VOLT_CFG_B0 0xF4
#define FS2711_REG_VOLT_CFG_B1 0xF5
#define FS2711_REG_VOLT_CFG_B2 0xF6
#define FS2711_REG_VOLT_CFG_B3 0xF7

// 0xF0 ~ 0xF1 16 bits
#define FS2711_REG_MASK 0xF0
// 0xF4 ~ 0xF7 32 bits
#define FS2711_REG_PROTOCOL_VOLT 0xF4
// 0xF8 ~ 0xFB 24 bits
#define FS2711_REG_PROTOCOL_EXISTS 0xF8

#define FS2711_SWEEP_SAW  0
#define FS2711_SWEEP_TRI  1
#define FS2711_SWEEP_STEP 2

#define FS2711_STATE_SCAN_DONE   0x01
#define FS2711_STATE_PDO_UPDATE  0x02
#define FS2711_STATE_PD_SNK      0x40
#define FS2711_STATE_PD_SRC      0x80
#define FS2711_STATE_PD_PE_READY 0x100
#define FS2711_STATE_DISABLE     0x800
#endif


================================================
FILE: source/Core/Drivers/Font.h
================================================
/*
 * Font.h
 *
 *  Created on: 17 Sep 2016
 *      Author: Ralim
 *
 *      ... This file contains the font...
 */

#ifndef FONT_H_
#define FONT_H_
#include "Translation.h"

#define FONT_12_WIDTH 12
// THE MAIN FONTS ARE NO LONGER HERE, MOVED TO PYTHON AUTO GEN
// THESE ARE ONLY THE SYMBOL FONTS
// clang-format off
  const uint8_t ExtraFontChars[] = {
      // width = 12
      // height = 16
      0x00, 0x18, 0x24, 0x24, 0x18, 0xC0, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, // Degrees F
      0x00, 0x18, 0x24, 0x24, 0x18, 0x80, 0x40, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x08, 0x10, 0x10, 0x10, 0x00, 0x00, // Degrees C
      0x00, 0x00, 0x20, 0x30, 0x38, 0xFC, 0xFE, 0xFC, 0x38, 0x30, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x7F, 0x7F, 0x00, 0x00, 0x00, 0x00, // UP arrow
  
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x3F, 0x00, // Battery Empty
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x40, 0x3F, 0x00, // Battery 1*/
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x40, 0x3F, 0x00, // Battery 2*/
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x40, 0x3F, 0x00, // Battery 3*/
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x5E, 0x40, 0x3F, 0x00, // Battery 4*/
      0x00, 0xF0, 0x08, 0x0E, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 5*/
      0x00, 0xF0, 0x08, 0x8E, 0x82, 0x82, 0x82, 0x82, 0x8E, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 6*/
      0x00, 0xF0, 0x08, 0xCE, 0xC2, 0xC2, 0xC2, 0xC2, 0xCE, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 7*/
      0x00, 0xF0, 0x08, 0xEE, 0xE2, 0xE2, 0xE2, 0xE2, 0xEE, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 8*/
      0x00, 0xF0, 0x08, 0xEE, 0xE2, 0xF2, 0xF2, 0xE2, 0xEE, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 9*/
      0x00, 0xF0, 0x08, 0xEE, 0xE2, 0xFA, 0xFA, 0xE2, 0xEE, 0x08, 0xF0, 0x00, 0x00, 0x3F, 0x40, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x5F, 0x40, 0x3F, 0x00, // Battery 10*/
  
      0x00, 0x00, 0x38, 0xC4, 0x00, 0x38, 0xC4, 0x00, 0x38, 0xC4, 0x00, 0x00, 0x00, 0x38, 0x3A, 0x39, 0x38, 0x3A, 0x39, 0x38, 0x3A, 0x39, 0x10, 0x10, // heating
      0x00, 0x60, 0xE0, 0xFE, 0xE0, 0xE0, 0xE0, 0xE0, 0xFE, 0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0xFF, 0xFF, 0x03, 0x01, 0x00, 0x00, 0x00, // AC
  
      0xFC, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x82, 0x62, 0x1A, 0x02, 0xFC, 0x3F, 0x40, 0x42, 0x46, 0x4C, 0x58, 0x46, 0x41, 0x40, 0x40, 0x40, 0x3F, // ☑ (check box on, menu true)
      0xFC, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFC, 0x3F, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x3F, // ☐ (check box off, menu false)
  
      /*
       0x00,0x00,0x00,0x80,0x80,0xFE,0xFF,0x83,0x87,0x06,0x00,0x00,0x00,0x00,0x30,0x70,0x60,0x7F,0x3F,0x00,0x00,0x00,0x00,0x00, // Function?
       0x00,0x70,0xFA,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xFF,0xFE,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x00,0x00, // a_
       0x00,0x3C,0x7E,0xE7,0xC3,0xC3,0xC3,0xC3,0xE7,0x7E,0x3C,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x00,0x00, // 0_
       0x55,0x00,0xAA,0x00,0x55,0x00,0xAA,0x00,0x55,0x00,0xAA,0x00,0x55,0x00,0xAA,0x00,0x55,0x00,0xAA,0x00,0x55,0x00,0xAA,0x00, // 25%  block
       0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55,0xAA,0x55, // 50% pipe
       0xAA,0xFF,0x55,0xFF,0xAA,0xFF,0x55,0xFF,0xAA,0xFF,0x55,0xFF,0xAA,0xFF,0x55,0xFF,0xAA,0xFF,0x55,0xFF,0xAA,0xFF,0x55,0xFF, // 75% block
       0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, // | pipe
       0x80,0x80,0x80,0x80,0x80,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, // T pipe ,|
       0xC0,0xC0,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0xFE,0xFE,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, // ,| double pipe
       0x00,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, //  || double pipe
       0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0xFE,0xFE,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, // #NAME?//#NAME?
       0xC0,0xC0,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x07,0x07,0x00,0x00,0x00,0x00,0x00, // ,^ double pupe
       0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00, // #NAME?//#NAME?
       0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01, // ,> pipe
       0x80,0x80,0x80,0x80,0x80,0xFF,0xFF,0x80,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, // _|_ pipe
       0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x01,0x01,0x01, // ,|, pipe
       0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x01,0x01,0x01,0x01,0x01, // |, pipe
       0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, // #NAME?//#NAME?
       0x80,0x80,0x80,0x80,0x80,0xFF,0xFF,0x80,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x01,0xFF,0xFF,0x01,0x01,0x01,0x01,0x01, // #NAME?//#NAME?
       0x00,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x07,0x07,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06, // ,> double pipe
       0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xFF,0xFF,0x00,0xFE,0xFE,0x06,0x06,0x06,0x06,0x06, // ^, double pipe
       0xC0,0xC0,0xFF,0xFF,0x00,0xFF,0xFF,0xC0,0xC0,0xC0,0xC0,0xC0,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06, // _|_ double pipe
       0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x06,0x06,0xFE,0xFE,0x00,0xFE,0xFE,0x06,0x06,0x06,0x06,0x06, // ,|, double pipe
       0x00,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xFF,0xFF,0x00,0xFE,0xFE,0x06,0x06,0x06,0x06,0x06, // |, double pipe
       0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06, // == double pipe
       0xC0,0xC0,0xFF,0xFF,0x00,0xFF,0xFF,0xC0,0xC0,0xC0,0xC0,0xC0,0x06,0x06,0xFE,0xFE,0x00,0xFE,0xFE,0x06,0x06,0x06,0x06,0x06, // #NAME?//#NAME?
       0x00,0x00,0x00,0x78,0xFC,0xCC,0x8C,0x0C,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x3E,0x33,0x33,0x3F,0x1E,0x00,0x00,0x00, // Delta lowercase
       0x00,0x00,0x00,0x00,0x00,0x7E,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 27 (')
       0x80,0x80,0x80,0x80,0x80,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00, // ,^ pipe
       0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x01,0x01,0x01,0x01,0x01, // | , pipe
       0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // solid block
       0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // half block bottom
       0x00,0x00,0x00,0x00,0x00,0xBF,0xBF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x3F,0x00,0x00,0x00,0x00,0x00, // 7C (|)
       0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // top half solid block
       0x00,0x00,0x0C,0xFC,0xFC,0x6C,0x60,0x60,0xE0,0xC0,0x00,0x00,0x00,0x00,0x30,0x3F,0x3F,0x36,0x06,0x06,0x07,0x03,0x00,0x00, // DE small
       0x00,0x00,0x03,0xFF,0xFF,0x1B,0x18,0x18,0xF8,0xF0,0x00,0x00,0x00,0x00,0x30,0x3F,0x3F,0x36,0x06,0x06,0x07,0x03,0x00,0x00, // DE large
       0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ? (,)
       0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x00, // =
       0x00,0x00,0x00,0x40,0x80,0x80,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // sideways comma
       0x00,0x00,0x80,0xC0,0x80,0x00,0x00,0x80,0xC0,0x80,0x00,0x00,0x00,0x00,0x01,0x03,0x01,0x00,0x00,0x01,0x03,0x01,0x00,0x00, // ..
       0x00,0x00,0x00,0x00,0x00,0x80,0xC0,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x01,0x00,0x00,0x00,0x00, // .
       0x00,0x00,0x02,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // tiny 1
       0x00,0x00,0x00,0x00,0xF0,0xF0,0xF0,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x00,0x00,0x00, // small block
       */
  };
  
  const uint8_t WarningBlock24[] = {
      // width = 24
      // height = 16
      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x30, 0x0C, 0x02, 0xF1, 0xF1, 0xF1, 0x02, 0x0C, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
      0x00, 0x00, 0x00, 0xC0, 0xB0, 0x8C, 0x83, 0x80, 0x80, 0x80, 0x80, 0xB3, 0xB3, 0xB3, 0x80, 0x80, 0x80, 0x80, 0x83, 0x8C, 0xB0, 0xC0, 0x00, 0x00};
  
  #if defined(MODEL_S60) || defined(MODEL_S60P) || defined(MODEL_TS101) || defined(MODEL_T55)
    #if defined(MODEL_S60) || defined(MODEL_S60P) 
    const uint8_t buttonA[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x04, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x04, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0xf0, 0x0e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x10, 0xe0, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x0f, 0x70, 0x80, 0x00, 0x00, 0x00, 0x0e, 0x51, 0x40, 0x40, 0x47, 0x48, 0xa0, 0x60, 0xa7, 0x60, 0xa0, 0x60, 0xa0, 0x40, 0x00, 0x40, 0x40, 0x40,
        0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0xfc, 0x08, 0xbc, 0x08, 0xbc, 0x00, 0xfc, 0xfc, 0x3c, 0x84, 0x70, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x40, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
        0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x47, 0x40, 0x44, 0x21, 0x20, 0x18, 0x09, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
  
    const uint8_t disconnectedTip[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0x80, 0x00, 0x80, 0x80, 0x80, 0x80, 0x81, 0x83, 0x87, 0x8e, 0x9c, 0x38, 0x70, 0xe0, 0xc0,
        0x80, 0x20, 0x70, 0x38, 0x9c, 0x8e, 0x87, 0x83, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0x70, 0x38, 0x1c, 0x0e, 0x04, 0x01,
        0x03, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
    
    #elif defined(MODEL_TS101)
    const uint8_t buttonA[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x04, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x04, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0xf0, 0x0e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x10, 0xe0, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x0f, 0x70, 0x80, 0x00, 0x00, 0x40, 0x5e, 0x41, 0xa0, 0x60, 0xa7, 0x70, 0x00, 0xf0, 0x37, 0x70, 0x30, 0x70, 0x30, 0x70, 0x30, 0x70, 0x30, 0x50,
        0x30, 0x50, 0x30, 0x50, 0x30, 0x50, 0xe0, 0x00, 0xa0, 0x60, 0xa0, 0x60, 0xa0, 0x60, 0xa0, 0x60, 0xa0, 0x50, 0xb8, 0x38, 0x80, 0x70, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x41, 0x80, 0x81, 0x81, 0x80, 0x81, 0x80, 0x81, 0x80, 0x81, 0x80, 0x81, 0x80,
        0x81, 0x80, 0x81, 0x80, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0x40, 0x40, 0x20, 0x20, 0x18, 0x09, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
  
    const uint8_t disconnectedTip[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x40, 0xc0, 0x40, 0xe0, 0x00, 0xe0, 0x60, 0xe0, 0x61, 0xe3, 0x67, 0xce, 0x1c, 0x38, 0x70, 0xe0, 0xc0,
        0x80, 0x20, 0x70, 0x38, 0x9c, 0xce, 0x07, 0x43, 0xc1, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0xa0, 0x70, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x02, 0x00, 0x03, 0x02, 0x00, 0x82, 0xc0, 0xe2, 0x70, 0x38, 0x1c, 0x0e, 0x04, 0x01,
        0x03, 0x07, 0x0e, 0x1c, 0x38, 0x71, 0xe0, 0xc1, 0x80, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
    
  #elif defined(MODEL_T55)
    const uint8_t buttonA[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x04, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x04, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0xf0, 0x0e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x10, 0xe0, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x88, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x0f, 0x70, 0x80, 0x00, 0x00, 0x00, 0x0e, 0x51, 0x40, 0x40, 0x47, 0x48, 0xa0, 0x60, 0xa7, 0x60, 0xa0, 0x60, 0xa0, 0x40, 0x00, 0x40, 0x40, 0x40,
        0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0xfc, 0x08, 0xbc, 0x08, 0xbc, 0x00, 0xfc, 0xfc, 0x3c, 0x84, 0x70, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x40, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
        0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x47, 0x40, 0x44, 0x21, 0x20, 0x18, 0x09, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
  
    const uint8_t disconnectedTip[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0xc0, 0x40, 0x80, 0x00, 0x80, 0x80, 0x80, 0x80, 0x81, 0x83, 0x87, 0x8e, 0x9c, 0x38, 0x70, 0xe0, 0xc0,
        0x80, 0x20, 0x70, 0x38, 0x9c, 0x8e, 0x87, 0x83, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0x70, 0x38, 0x1c, 0x0e, 0x04, 0x01,
        0x03, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
    #endif
    
    const uint8_t buttonB[] = {
        // width = 56
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x04, 0x02, 0x02, 0x02, 0x01, 0x01, 0x71, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xf1,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xf1, 0x01, 0x01, 0x02, 0x02, 0x02, 0x04, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0xf0, 0x0e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x1f, 0xd7, 0x13, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xdf, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0e, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 
        0x00, 0x00, 0x00, 0x00, 0x0f, 0x70, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x7c, 0x5d,
        0x4c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x03, 0x07, 0xf5, 0x04, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x70, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x40, 0x80, 0x80, 0x8f, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x8f,
        0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x8f, 0x80, 0x80, 0x40, 0x40, 0x40, 0x20, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
    
    const uint8_t RepeatOnce[] = {
        // width = 32
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x70, 0x78, 0x38, 0x38, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x38, 0x38, 0x78, 0xf0, 0xf0, 0xe0, 0xf0,
        0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xfc, 0xff, 0x1f, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
        0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0xe0, 0xe0, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x20, 0x30, 0x38, 0xfc, 0xfc, 0x00, 0x00, 0x00, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xf8, 0xff, 0x3f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
        0x3f, 0x3f, 0x00, 0x00, 0x00, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x1c, 0x1c, 0x1e, 0x0e, 0x0f, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00};
    
    const uint8_t RepeatInf[] = {
        // width = 32
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x70, 0x78, 0x38, 0x38, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x38, 0x38, 0x78, 0xf0, 0xf0, 0xe0, 0xf0,
        0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xfc, 0xff, 0x1f, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
        0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0xe0, 0xe0, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x1f, 0x9f, 0x98, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80,
        0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xf8, 0xff, 0x3f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x11, 0x20, 0x20, 0x20, 0x11,
        0x0a, 0x04, 0x0a, 0x11, 0x20, 0x20, 0x20, 0x11, 0x0e, 0x00, 0x00, 0x1c, 0x1c, 0x1e, 0x0e, 0x0f, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00};

    const uint8_t UnavailableIcon[] = {
        // width = 32
        // height = 32
        0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x70, 0x78, 0x38, 0x38, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x38, 0x38, 0x78, 0x70, 0xf0, 0xe0, 0xc0,
        0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xfc, 0xff, 0x1f, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0x7c,
        0x3e, 0x1e, 0x0c, 0x00, 0x01, 0x07, 0x1f, 0xff, 0xfc, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3f, 0xff, 0xf8, 0xe0, 0x80, 0x00, 0x30, 0x78, 0x7c, 0x3e, 0x1f,
        0x0f, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xf8, 0xff, 0x3f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07,
        0x0f, 0x0e, 0x1e, 0x1c, 0x1c, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x1c, 0x1c, 0x1e, 0x0e, 0x0f, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00};
    
    #define SETTINGS_ICON_WIDTH 21
    #define SETTINGS_ICON_HEIGHT 32
    /*
     * 21x32 icons
     * 84 * 3 = Frame size * Frame count
     * */
    const uint8_t SettingsMenuIcons[][84 * 3] = {
      // Power
      // 3 frames
      {
          // Power 1st frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0xfc,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x10,  0xdc,  0x37,  0x13,  0x01,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x80,  0xc0,  0xdf,  0xc0,  0x80,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x03,  0x07,  0x35,  0x04,  0x03,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Power 2nd frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0xfc,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0xe0,  0xfc,  0x7f,  0x1f,  0x0f,  0x07,  0x01,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x7f,  0x00,  0x00,  0x00,  0x00,  0x00,  0x02,  0x03,  0x83,  0x73,  0x3f,  0x0f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x0e,  0x1f,  0xd7,  0x13,  0x0e,  0x00,  0x00,  0x00,  0x00,  0x02,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x00,  0x00,  0x3f,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Power final frame
          // width = 21
          // height = 32
          0x00,  0xc0,  0xe0,  0xec,  0x60,  0xc0,  0x00,  0x00,  0x00,  0x80,  0xf0,  0xfc,  0xff,  0xff,  0x7f,  0x3f,  0x1f,  0x07,  0x03,  0x01,  0x00,  
          0x00,  0x01,  0x03,  0xfa,  0x02,  0x01,  0x00,  0x08,  0x0e,  0x0f,  0x8f,  0xef,  0xff,  0x7f,  0x3f,  0x1f,  0x07,  0x03,  0x01,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x00,  0x08,  0x0e,  0x0f,  0xcf,  0xfd,  0x3c,  0x1c,  0x04,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x00,  0x00,  0x3f,  0x00,  0x00,  0x00,  0x00,  0x10,  0x0c,  0x03,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
      },
  
      // Soldering
      // 3 frames
      {
          // Soldering 1st frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xf8,  0xfc,  0xfc,  0x7c,  0x18,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xe8,  0xe2,  0xf8,  0x7e,  0x1f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x66,  0x15,  0x07,  0x0f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x00,  0x00,  0x20,  0x18,  0x06,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Soldering 2nd frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xf8,  0xfc,  0xfc,  0x7c,  0x18,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xe8,  0xe2,  0xf8,  0x7e,  0x1f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x66,  0x15,  0x07,  0x0f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x03,  0x0c,  0x20,  0x18,  0x06,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Soldering final frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xf8,  0xfc,  0xfc,  0x7c,  0x18,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,  0x60,  0xe8,  0xe2,  0xf8,  0x7e,  0x1f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x80,  0xc8,  0xf0,  0x00,  0x00,  0x80,  0x66,  0x15,  0x07,  0x0f,  0x07,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x03,  0x0d,  0x20,  0x18,  0x06,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
      },
  
      // Sleep
      // 3 frames
      {
          // Sleep 1st frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x60,  0x60,  0x60,  0xe0,  0xe0,  0xc0,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00, 
          0x00,  0x00,  0x00,  0x00,  0x00,  0x0c,  0x1e,  0x1f,  0x1b,  0x19,  0x18,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Sleep 2nd frame
          // width = 21
          // height = 32
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x08,  0x1c,  0x1c,  0x9c,  0xdc,  0xfc,  0xfc,  0x38,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x60,  0x60,  0x60,  0xe0,  0xe0,  0xc0,  0x00,  0x18,  0x3e,  0x3f,  0x3f,  0x3b,  0x39,  0x38,  0x10,  0x00, 
          0x00,  0x00,  0x00,  0x00,  0x00,  0x0c,  0x1e,  0x1f,  0x1b,  0x19,  0x18,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
  
          // Sleep final frame
          // width = 21
          // height = 32
          0x00,  0x18,  0x3c,  0x3c,  0x3c,  0x3c,  0xbc,  0xfc,  0xfc,  0xfc,  0x78,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  
          0x00,  0xe0,  0xf8,  0xfc,  0xfe,  0xdf,  0xcf,  0xc7,  0xc3,  0xc1,  0x80,  0x00,  0x08,  0x1c,  0x1c,  0x9c,  0xdc,  0xfc,  0xfc,  0x38,  0x00,  
          0x00,  0x01,  0x03,  0x03,  0x03,  0x63,  0x63,  0x63,  0xe3,  0xe3,  0xc1,  0x00,  0x18,  0x3e,  0x3f,  0x3f,  0x3b,  0x39,  0x38,  0x10,  0x00, 
          0x00,  0x00,  0x00,  0x00,  0x00,  0x0c,  0x1e,  0x1f,  0x1b,  0x19,  0x18,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
      },
  
      // UI
      // 3 frames
      {
          // UI 1st frame
          // width = 21
          // height = 32
          0x00,  0x18,  0x74,  0x08,  0x44,  0x7c,  0x10,  0x7c,  0x10,  0x78,  0x44,  0x08,  0x48,  0x3c,  0x68,  0x08,  0x74,  0x10,  0x7c,  0x08,  0x00,  
          0x00,  0x60,  0xc0,  0x60,  0x80,  0xe0,  0x40,  0xe0,  0x20,  0xe0,  0x00,  0x00,  0xf8,  0x04,  0x84,  0x04,  0x04,  0x04,  0x04,  0xf8,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0xc3,  0x24,  0x24,  0x24,  0x24,  0x24,  0x24,  0xc3,  0x00, 
          0x00,  0x04,  0x03,  0x04,  0x07,  0x05,  0x00,  0x07,  0x02,  0x04,  0x00,  0x00,  0x1f,  0x20,  0x20,  0x20,  0x20,  0x20,  0x20,  0x1f,  0x00,
  
          // UI 2nd frame
          // width = 21
          // height = 32
          0x00,  0x18,  0x74,  0x08,  0x44,  0x7c,  0x10,  0x7c,  0x10,  0x78,  0x44,  0x08,  0x48,  0x3c,  0x68,  0x08,  0x74,  0x10,  0x7c,  0x08,  0x00,  
          0x00,  0x60,  0xc0,  0x60,  0x80,  0xe0,  0x40,  0xe0,  0x20,  0xe0,  0x00,  0x00,  0xf8,  0x04,  0x84,  0x04,  0x04,  0x04,  0x04,  0xf8,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0xc3,  0x24,  0x24,  0x25,  0x24,  0x24,  0x24,  0xc3,  0x00, 
          0x00,  0x04,  0x03,  0x04,  0x07,  0x05,  0x00,  0x07,  0x02,  0x04,  0x00,  0x00,  0x1f,  0x20,  0x20,  0x20,  0x20,  0x20,  0x20,  0x1f,  0x00,
  
          // UI final frame
          // width = 21
          // height = 32
          0x00,  0x18,  0x74,  0x08,  0x44,  0x7c,  0x10,  0x7c,  0x10,  0x78,  0x44,  0x08,  0x48,  0x3c,  0x68,  0x08,  0x74,  0x10,  0x7c,  0x08,  0x00,  
          0x00,  0x60,  0xc0,  0x60,  0x80,  0xe0,  0x40,  0xe0,  0x20,  0xe0,  0x00,  0x00,  0xf8,  0x04,  0x84,  0x04,  0xc4,  0x34,  0x04,  0xf8,  0x00,  
          0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0xc3,  0x24,  0x24,  0x25,  0x24,  0x24,  0x24,  0xc3,  0x00, 
          0x00,  0x04,  0x03,  0x04,  0x07,  0x05,  0x00,  0x07,  0x02,  0x04,  0x00,  0x00,  0x1f,  0x20,  0x20,  0x20,  0x20,  0x20,  0x20,  0x1f,  0x00,
      },
  
      // Advanced
      // 3 frames
      {
          // Advanced 1st frame
          // width = 21
          // height = 32
          0x00,  0x00,  0xfc,  0x00,  0x00,  0x00,  0xe0,  0xf0,  0x74,  0x30,  0xe0,  0x00,  0x00,  0x10,  0x00,  0xf0,  0x00,  0x00,  0x00,  0xf0,  0x00,  
          0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x00,  0x01,  0xfd,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x03,  0x00,  0x03,  0x00,  
          0x00,  0x80,  0xbf,  0x80,  0x00,  0x00,  0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0xf0,  0x08,  0x04,  0x04,  0x44,  0x44,  0x44,  0x48,  0x50, 
          0x07,  0x0f,  0x2b,  0x09,  0x07,  0x00,  0x00,  0x00,  0x3f,  0x00,  0x00,  0x00,  0x01,  0x02,  0x04,  0x04,  0x04,  0x04,  0x04,  0x02,  0x01,
  
          // Advanced 2nd frame
          // width = 21
          // height = 32
          0xe0,  0xf0,  0x74,  0x30,  0xe0,  0x00,  0x00,  0x00,  0xfc,  0x00,  0x00,  0x00,  0x00,  0xf0,  0x00,  0x10,  0x00,  0xc0,  0x00,  0x30,  0x00,  
          0x00,  0x01,  0xfd,  0x01,  0x00,  0x00,  0x00,  0x00,  0x7f,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x03,  0x00,  0x03,  0x00,  0x02,  0x00,  
          0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x0e,  0x1f,  0xd7,  0x13,  0x0e,  0x00,  0xf0,  0x08,  0x04,  0x04,  0xc4,  0x04,  0x04,  0x08,  0xf0, 
          0x00,  0x00,  0x3f,  0x00,  0x00,  0x00,  0x00,  0x00,  0x3f,  0x00,  0x00,  0x00,  0x01,  0x02,  0x04,  0x00,  0x07,  0x00,  0x04,  0x02,  0x01,
  
          // Advanced final frame
          // width = 21
          // height = 32
          0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x10, 0x00, 0xf0, 0x00, 0xc0, 0x00, 
          0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x00,  0x00,  0xff,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x03,  0x00,  0x00,  0x00,  
          0x70,  0xf8,  0xbb,  0x98,  0x70,  0x00,  0x00,  0x80,  0xbf,  0x80,  0x00,  0x00,  0xf0,  0x08,  0x04,  0x04,  0x44,  0x24,  0x10,  0x08,  0xe0, 
          0x00,  0x00,  0x3e,  0x00,  0x00,  0x00,  0x07,  0x0f,  0x2b,  0x09,  0x07,  0x00,  0x01,  0x02,  0x04,  0x04,  0x04,  0x04,  0x04,  0x02,  0x01,
      }
    };
  #else
    #if defined(MODEL_TS100) || defined(MODEL_Pinecil) || defined(MODEL_Pinecilv2)
    const uint8_t buttonA[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x00, 0xe0, 0x18, 0x04, 0x02, 0x02, 0x01, 0x81, 0x49, 0x31, 0x01, 0xc1, 0x25, 0x19, 0x01, 0xc1, 0x25, 0x19, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x80, 0x89, 0x8a, 0x88, 0x94,
        0x8c, 0x94, 0xae, 0x80, 0xbe, 0x8e, 0xa6, 0x8e, 0xa6, 0x8e, 0xa6, 0x8e, 0xa6, 0x8a, 0xa6, 0x8a, 0xa6, 0x8a, 0xa6, 0x8a, 0x46, 0x4a, 0x22, 0x18, 0x07, 0x00, 0x00, 0x00};
    
    const uint8_t disconnectedTip[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0xc0, 0x00, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xcc, 0x9c, 0x38, 0x70, 0xe0, 0xc0, 0x80, 0x20, 0x70, 0x38, 0x1c, 0xcc, 0x40,
        0x80, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xc0, 0x60, 0xe0, 0x00, 0x01, 0x01, 0x01, 0x02, 0x01, 0x02, 0x05, 0x00, 0x07, 0x01, 0x04, 0x01, 0x04, 0x01,
        0x04, 0x31, 0x38, 0x1c, 0x0e, 0x04, 0x01, 0x03, 0x07, 0x0e, 0x1c, 0x39, 0x30, 0x01, 0x03, 0x00, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09, 0x0f, 0x00};
    
    #elif defined(MODEL_TS80) || defined(MODEL_TS80P)
    const uint8_t buttonA[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x00, 0xe0, 0x18, 0x04, 0x02, 0x02, 0x01, 0x81, 0x49, 0x31, 0x01, 0xc1, 0x25, 0x19, 0x01, 0xc1, 0x25, 0x19, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x80, 0x81, 0x8a, 0x88, 0x88,
        0x8c, 0x95, 0x80, 0x9c, 0xa6, 0x8e, 0xa6, 0x8c, 0x80, 0x94, 0x8c, 0x94, 0x8c, 0x94, 0x8c, 0x94, 0x80, 0x88, 0x88, 0x88, 0x48, 0x48, 0x20, 0x18, 0x07, 0x00, 0x00, 0x00};
    
    const uint8_t disconnectedTip[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x80, 0xc0, 0xc0, 0xc0, 0x80, 0x00, 0x80, 0x80, 0x80, 0x8c, 0x9c, 0x38, 0x70, 0xe0, 0xc0, 0x80, 0x20, 0x70, 0x38, 0x1c, 0x0c, 0x00,
        0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0xc0, 0xc0, 0xc0, 0xc0, 0xe0, 0xa0, 0xe0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x02, 0x00, 0x03, 0x04, 0x01, 0x04, 0x01, 0x00, 0x02, 0x01,
        0x02, 0x31, 0x38, 0x1c, 0x0e, 0x04, 0x01, 0x03, 0x07, 0x0e, 0x1c, 0x39, 0x31, 0x01, 0x01, 0x00, 0x02, 0x01, 0x02, 0x01, 0x04, 0x01, 0x04, 0x01, 0x0a, 0x01, 0x0f, 0x00};
    
    #elif defined(MODEL_MHP30)
    const uint8_t buttonA[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x00, 0xe0, 0x18, 0x04, 0x02, 0x02, 0x81, 0x81, 0x41, 0x41, 0x41, 0x41, 0x21, 0x01, 0xc1, 0x25, 0x19, 0x01, 0x81, 0x49, 0x31, 0x01, 0xc1, 0x25, 0x19,
        0x01, 0xa1, 0xa1, 0x41, 0x41, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x83, 0x87, 0x83, 0xab, 0x86,
        0x96, 0x8e, 0xa6, 0x9c, 0xad, 0x8c, 0xb8, 0x89, 0xa4, 0x84, 0x84, 0x92, 0x82, 0x81, 0xa9, 0x80, 0x84, 0x80, 0x81, 0x80, 0x40, 0x40, 0x20, 0x18, 0x07, 0x00, 0x00, 0x00};
    
    const uint8_t disconnectedTip[] = {
        // width = 42
        // height = 16
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x40, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x20, 0x10, 0x10, 0xd0, 0xc8, 0x08, 0x10, 0x10, 0x10, 0x10,
        0x20, 0x20, 0x20, 0x40, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x04, 0x04, 0x38, 0x00,
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x04, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
    #endif
    
    const uint8_t buttonB[] = {
      // width = 42
      // height = 16
      0x00, 0x00, 0x00, 0xe0, 0x18, 0x04, 0x02, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x71, 0x55, 0x71, 0x01, 0x01, 0xfd, 0x01, 0x01, 0x81, 0xbd, 0x81, 0x01, 0x01,
      0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x18, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x40, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
      0x80, 0x80, 0xbf, 0x80, 0x80, 0x8e, 0xaa, 0x8e, 0x80, 0x83, 0xba, 0x83, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0x40, 0x20, 0x18, 0x07, 0x00, 0x00, 0x00, 0x00};
    
    // const uint8_t brightnessIcon[] = {
    //     // width = 16
    //     // height = 16
    //     0x80, 0x86, 0x8E, 0x9C, 0x18, 0xC0, 0xE0, 0xEF, 0xEF, 0xE0, 0xC0, 0x18, 0x9C, 0x8E, 0x86, 0x80, 0x01, 0x61, 0x71, 0x39, 0x18, 0x03, 0x07, 0xF7, 0xF7, 0x07, 0x03, 0x18, 0x39, 0x71, 0x61, 0x01};
    
    // const uint8_t invertDisplayIcon[] = {
    //     // width = 24
    //     // height = 16
    //     0xFE, 0x01, 0x79, 0x25, 0x79, 0x01, 0xFE, 0x00, 0x20, 0x20, 0x20, 0x20, 0xDF, 0x07, 0x8F, 0xDF, 0xFF, 0x01, 0xFE, 0x86, 0xDA, 0x86, 0xFE, 0x01,
    //     0x7F, 0x80, 0xA4, 0xBE, 0xA0, 0x80, 0x7F, 0x00, 0x04, 0x0E, 0x1F, 0x04, 0xFB, 0xFB, 0xFB, 0xFB, 0xFF, 0x80, 0x7F, 0x5B, 0x41, 0x5F, 0x7F, 0x80};
    
    const uint8_t RepeatOnce[] = {
      // width = 16
      // height = 16
      0x00, 0xc0, 0xf0, 0x78, 0x1c, 0x0c, 0x0e, 0x06, 0x06, 0x0e, 0x2c, 0x3c, 0x38, 0x3c, 0x00, 0x00,
      0x00, 0x01, 0x08, 0x04, 0x7e, 0x00, 0x00, 0x60, 0x60, 0x70, 0x30, 0x38, 0x1e, 0x0f, 0x03, 0x00};
  
    const uint8_t RepeatInf[] = {
      // width = 16
      // height = 16
      0x00, 0xc0, 0xf0, 0x78, 0x1c, 0x0c, 0x0e, 0x06, 0x06, 0x0e, 0x2c, 0x3c, 0x38, 0x3c, 0x00, 0x00,
      0x00, 0x31, 0x49, 0x48, 0x30, 0x48, 0x48, 0x30, 0x00, 0x00, 0x30, 0x38, 0x1e, 0x0f, 0x03, 0x00};

    const uint8_t UnavailableIcon[] = {
        // width = 16
        // height = 16
        0x00, 0xc0, 0x30, 0x08, 0x04, 0x04, 0x02, 0x82, 0xc2, 0xe2, 0x74, 0x24, 0x08, 0x30, 0xc0, 0x00,
        0x00, 0x03, 0x0c, 0x10, 0x24, 0x2e, 0x47, 0x43, 0x41, 0x40, 0x20, 0x20, 0x10, 0x0c, 0x03, 0x00};

    #define SETTINGS_ICON_WIDTH 16
    #define SETTINGS_ICON_HEIGHT 16
    /*
     * 16x16 icons
     * 32 * 3 = Frame size * Frame count
     * */
    const uint8_t SettingsMenuIcons[][32 * 3] = {
      // Power
      // 3 frames
      {
          // Power 1st frame
          // width = 16
          // height = 16
          0x00, 0x00, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 0x0f, 0x05, 0x00, 0x00, 0x00, 0x00, //
          0x00, 0x1c, 0x55, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
  
          // Power 2nd frame
          // width = 16
          // height = 16
          0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x10, 0x1c, 0xdf, 0x77, 0x33, 0x11, 0x00, 0x00, 0x00, //
          0x00, 0x07, 0x75, 0x07, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
  
          // Power final frame
          // width = 16
          // height = 16
          0x00, 0x38, 0xaa, 0x38, 0x00, 0x20, 0x30, 0x3c, 0xff, 0xff, 0xff, 0x77, 0x33, 0x13, 0x01, 0x00, //
          0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x42, 0x33, 0x1f, 0x0f, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, //
      },
  
      // Soldering
      // 3 frames
      {
          // Soldering 1st frame
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0xE0, 0x50, 0x28, 0x14, 0x0A, 0x06, 0x00, //
          0x00, 0x40, 0x20, 0x10, 0x08, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
  
          // Soldering 2nd frame
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0xE0, 0x50, 0x28, 0x14, 0x0A, 0x06, 0x00, //
          0x00, 0x48, 0x26, 0x10, 0x08, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
  
          // Soldering final frame
          // width = 16
          // height = 16
          0x00, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x80, 0x40, 0xE0, 0x50, 0x28, 0x14, 0x0A, 0x06, 0x00, //
          0x00, 0x49, 0x26, 0x10, 0x08, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
      },
  
      // Sleep
      // 3 frames
      {
          // Sleep 1st frame
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
          0x00, 0x00, 0x00, 0x00, 0x44, 0x64, 0x74, 0x5C, 0x4C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //
  
          // Sleep 2nd frame
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0xC0, 0xC0, 0xC0, 0x00, //
          0x00, 0x00, 0x00, 0x00, 0x44, 0x64, 0x74, 0x5C, 0x4C, 0x00, 0x06, 0x07, 0x07, 0x05, 0x04, 0x00, //
  
          // Sleep final frame
          // width = 16
          // height = 16
          0x00, 0xC6, 0xE6, 0xF6, 0xBE, 0x9E, 0x8E, 0x86, 0x00, 0x00, 0x40, 0x40, 0xC0, 0xC0, 0xC0, 0x00, //
          0x00, 0x01, 0x01, 0x01, 0x45, 0x65, 0x75, 0x5D, 0x4C, 0x00, 0x06, 0x07, 0x07, 0x05, 0x04, 0x00, //
      },
  
      // UI
      // 3 frames
      {
          // UI 1st frame
          // width = 16
          // height = 16
          0x00, 0x80, 0x06, 0x06, 0x06, 0x06, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x00, //
          0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x00, //
  
          // UI 2nd frame
          // width = 16
          // height = 16
          0x00, 0x80, 0x06, 0x06, 0x06, 0x06, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x00, //
          0x00, 0x00, 0x61, 0x60, 0x00, 0x00, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x00, //
  
          // UI final frame
          // width = 16
          // height = 16
          0x00, 0x80, 0x06, 0x86, 0x46, 0x06, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x86, 0x00, //
          0x00, 0x00, 0x61, 0x60, 0x00, 0x00, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x61, 0x00, //
      },
  
      // Advanced
      // 3 frames
      {
          // Advanced 1st frame
          // width = 16
          // height = 16
          0x00, 0xfe, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x00, 0x0c, 0x00, 0x14, 0x00, 0x18, 0x00, 0x14, 0x00, //
          0x1c, 0x55, 0x1c, 0x00, 0x1c, 0x55, 0x1c, 0x00, 0x00, 0x1c, 0x22, 0x41, 0x49, 0x11, 0x22, 0x0c, //
  
          // Advanced 2nd frame
          // width = 16
          // height = 16
          0xe0, 0xae, 0xe0, 0x00, 0x80, 0xbe, 0x80, 0x00, 0x08, 0x00, 0x04, 0x00, 0x1c, 0x00, 0x08, 0x00, //
          0x00, 0x7e, 0x00, 0x00, 0x03, 0x7a, 0x03, 0x00, 0x00, 0x1c, 0x22, 0x01, 0x79, 0x01, 0x22, 0x1c, //
  
          // Advanced final frame
          // width = 16
          // height = 16
        0x00, 0x7e, 0x00, 0x00, 0x38, 0xaa, 0x38, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x10, 0x00, 0x1c, 0x00,//
        0x07, 0x75, 0x07, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x0c, 0x22, 0x11, 0x49, 0x41, 0x22, 0x1c,//
      },
    #ifdef NOTUSED
  
      // Calibration (Not used, kept for future menu layouts)
      // 3 frames
      {
          // Calibration 1st frame (Not used, kept for future menu layouts)
          // width = 16
          // height = 16
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0x70, 0x3A, 0x1E, 0x0E, 0x1C, 0x30, 0x00,//
        0x00, 0x10, 0x3A, 0x1C, 0x1E, 0x17, 0x23, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,//

          // Calibration 2nd frame (Not used, kept for future menu layouts)
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x80, 0xC0, 0xE0, 0x70, 0x3A, 0x1E, 0x0E, 0x1C, 0x30, 0x00, // 
          0x00, 0x10, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x03, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //

          // Calibration final frame (Not used, kept for future menu layouts)
          // width = 16
          // height = 16
          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE8, 0x70, 0x7A, 0x5E, 0x8E, 0x1C, 0x30, 0x00, //
          0x00, 0x10, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //

    #endif
    };
  #endif
// clang-format on
#endif /* FONT_H_ */

================================================
FILE: source/Core/Drivers/HUB238.cpp
================================================
#include "HUB238.hpp"
#include "I2CBB2.hpp"
#include "Utils.hpp"
#include "configuration.h"

#if POW_PD_EXT == 1
bool hub238_probe() { return I2CBB2::probe(HUB238_ADDR); }

extern int32_t powerSupplyWattageLimit;

uint16_t hub238_debug_state() {
  uint8_t status0 = 0;
  uint8_t status1 = 0;
  if (!I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_PD_STATUS0, &status0, 1)) {
    return 0xFFFF;
  }
  if (!I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_PD_STATUS1, &status1, 1)) {
    return 0xFFFF;
  }
  return status1 | (((uint16_t)status0) << 8);
}
uint16_t pdo_slot_to_currentx100(uint8_t temp) {
  temp = temp & 0b1111;
  switch (temp) {
  case 0b0000:
    return 50;
  case 0b0001:
    return 70;
  case 0b0010:
    return 100;
  case 0b0011:
    return 125;
  case 0b0100:
    return 150;
  case 0b0101:
    return 175;
  case 0b0110:
    return 200;
  case 0b0111:
    return 225;
  case 0b1000:
    return 250;
  case 0b1001:
    return 275;
  case 0b1010:
    return 300;
  case 0b1011:
    return 325;
  case 0b1100:
    return 350;
  case 0b1101:
    return 400;
  case 0b1110:
    return 450;
  case 0b1111:
    return 500;
  }
}
uint16_t hub238_getVoltagePDOCurrent(uint8_t voltage) {
  uint8_t reg = HUB238_REG_SRC_PDO_5V;
  switch (voltage) {
  case 5:
    reg = HUB238_REG_SRC_PDO_5V;
    break;
  case 9:
    reg = HUB238_REG_SRC_PDO_9V;
    break;
  case 12:
    reg = HUB238_REG_SRC_PDO_12V;
    break;
  case 15:
    reg = HUB238_REG_SRC_PDO_15V;
    break;
  case 18:
    reg = HUB238_REG_SRC_PDO_18V;
    break;
  case 20:
    reg = HUB238_REG_SRC_PDO_20V;
    break;
  default:
    return 0;
  }
  uint8_t temp = 0;
  if (I2CBB2::Mem_Read(HUB238_ADDR, reg, &temp, 1) == true) {
    if (temp & HUB238_PDO_DETECTED) {
      return pdo_slot_to_currentx100(temp);
    }
  }
  return 0;
}
uint8_t findBestPDO() {
  uint8_t  temp              = 0;
  uint16_t ilim              = 0;
  uint16_t minimumx10current = 0;
#if USB_PD_VMAX >= 20
  ilim              = hub238_getVoltagePDOCurrent(20);
  minimumx10current = Utils::RequiredCurrentForTipAtVoltage(200);
  if (ilim != 0 && ilim / 10 >= minimumx10current) {
    powerSupplyWattageLimit = ((20 * ilim) / 100) - 2; // We take off 2W for safety of overhead
    return 0b1010;
  }
#endif
#if USB_PD_VMAX >= 18
  ilim              = hub238_getVoltagePDOCurrent(18);
  minimumx10current = Utils::RequiredCurrentForTipAtVoltage(180);
  if (ilim != 0 && ilim / 10 >= minimumx10current) {
    powerSupplyWattageLimit = ((18 * ilim) / 100) - 2; // We take off 2W for safety of overhead
    return 0b1001;
  }
#endif
#if USB_PD_VMAX >= 15
  ilim              = hub238_getVoltagePDOCurrent(15);
  minimumx10current = Utils::RequiredCurrentForTipAtVoltage(150);
  if (ilim != 0 && ilim / 10 >= minimumx10current) {
    powerSupplyWattageLimit = ((15 * ilim) / 100) - 2; // We take off 2W for safety of overhead
    return 0b1000;
  }
#endif
#if USB_PD_VMAX >= 12
  ilim              = hub238_getVoltagePDOCurrent(12);
  minimumx10current = Utils::RequiredCurrentForTipAtVoltage(120);
  if (ilim != 0 && (ilim / 10) >= minimumx10current) {
    powerSupplyWattageLimit = ((12 * ilim) / 100) - 2; // We take off 2W for safety of overhead
    return 0b0011;
  }
#endif
#if USB_PD_VMAX >= 9
  ilim              = hub238_getVoltagePDOCurrent(9);
  minimumx10current = Utils::RequiredCurrentForTipAtVoltage(90);
  if (ilim != 0 && ilim / 10 >= minimumx10current) {
    powerSupplyWattageLimit = ((9 * ilim) / 100) - 2; // We take off 2W for safety of overhead
    return 0b0010;
  }
#endif

  powerSupplyWattageLimit = 10;
  return 0b0001; // 5V PDO
}
volatile uint8_t haveSelected = 0xFF;

void hub238_check_negotiation() {
  // Dont do anything for first 2 seconds as its internal state machine corrupts if we ask it to change too fast

  if (xTaskGetTickCount() < 2000) {
    return;
  }
  // Want to check if there is a better PDO to be using
  // First, exit early if we already have changed _or_ no PD
  // Even if it negotiates the same voltage as we want, we still re-run it as that makes it ignore the resistor
  // and instead ask for max amps
  if (haveSelected != 0xFF || !hub238_has_negotiated() || hub238_source_voltage() == 0) {
    return;
  }
  uint8_t currentPDO = 0;
  vTaskDelay(5);

  uint8_t bestPDO = findBestPDO();

  if (I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_SRC_PDO, ¤tPDO, 1) == true) {
    currentPDO >>= 4; // grab upper bits
    if (currentPDO == bestPDO) {
      haveSelected = bestPDO;
      return;
    }
    currentPDO = bestPDO << 4;
    if (I2CBB2::Mem_Write(HUB238_ADDR, HUB238_REG_SRC_PDO, ¤tPDO, 1) == true) {

      currentPDO = 0x01; // request for new PDO
      if (I2CBB2::Mem_Write(HUB238_ADDR, HUB238_REG_GO_COMMAND, ¤tPDO, 1) == true) {
        haveSelected = bestPDO;
        vTaskDelay(50);

        return;
      }
    }
  }
}
bool hub238_has_run_selection() { return haveSelected != 0xFF; }

bool hub238_has_negotiated() {
  uint8_t temp = 0;
  if (I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_PD_STATUS1, &temp, 1) == true) {
    temp >>= 3;
    return (temp & 0b111) == 0b001; // success
  }
  return false;
}

// Return selected source voltage in V
uint16_t hub238_source_voltage() {
  uint8_t temp = 0;
  if (I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_PD_STATUS0, &temp, 1) == true) {
    temp >>= 4;
    switch (temp) {
    case 0b0001:
      return 5;
    case 0b0010:
      return 9;
    case 0b0011:
      return 12;
    case 0b0100:
      return 15;
    case 0b0101:
      return 18;
    case 0b0110:
      return 20;
    }
  }
  return 0;
}
// Return selected source current in Amps * 100
uint8_t hub238_source_currentX100() {
  uint8_t temp = 0;
  if (I2CBB2::Mem_Read(HUB238_ADDR, HUB238_REG_PD_STATUS0, &temp, 1) == true) {
    temp &= 0b1111;
    return pdo_slot_to_currentx100(temp);
  }
  return 10; // Failsafe to 0.1 amp
}
#endif


================================================
FILE: source/Core/Drivers/HUB238.hpp
================================================
#pragma once

#ifndef _DRIVERS_HUB238_HPP_
#define _DRIVERS_HUB238_HPP_
#include "configuration.h"
#if POW_PD_EXT == 1
#include 
#include 

#define HUB238_ADDR 0x08 << 1

#define HUB238_REG_PD_STATUS0  0x00
#define HUB238_REG_PD_STATUS1  0x01
#define HUB238_REG_SRC_PDO_5V  0x02
#define HUB238_REG_SRC_PDO_9V  0x03
#define HUB238_REG_SRC_PDO_12V 0x04
#define HUB238_REG_SRC_PDO_15V 0x05
#define HUB238_REG_SRC_PDO_18V 0x06
#define HUB238_REG_SRC_PDO_20V 0x07
#define HUB238_REG_SRC_PDO     0x08
#define HUB238_REG_GO_COMMAND  0x09

#define HUB238_PDO_DETECTED (0x01 << 7)
// The HUB238 is fairly simple device to interact to, with fairly few registers all in all
//  It only appears to support fixed PDO's up to 20V
//  And they have just dedicated registers to each potential option
//  Given a tip resistance we try and pick the best possible PDO option to suit that resistance
//  (Using I2C overrides any hardware strapping).

// Probe if the hub238 exists on the I2C bus
bool hub238_probe();
// If we have not manually picked a PDO,
// but there is an active PD supply, try for our preference

void hub238_check_negotiation();

// Returns true when negotiation has finished
bool hub238_has_negotiated();
// Returns true when we have run selection and negotiated higher current
bool hub238_has_run_selection();
// Return an encoded state for debugging
uint16_t hub238_debug_state();
// Return selected source voltage in V
uint16_t hub238_source_voltage();
// Return selected source current in Amps * 100
uint8_t hub238_source_currentX100();

uint16_t hub238_getVoltagePDOCurrent(uint8_t voltage);

#endif
#endif


================================================
FILE: source/Core/Drivers/I2CBB1.cpp
================================================
/*
 * I2CBB1.cpp
 *
 *  Created on: 12 Jun 2020
 *      Author: Ralim
 */
#include "configuration.h"
#ifdef I2C_SOFT_BUS_1
#include "FreeRTOS.h"
#include 
SemaphoreHandle_t I2CBB1::I2CSemaphore = NULL;
StaticSemaphore_t I2CBB1::xSemaphoreBuffer;
void              I2CBB1::init() {
  // Set GPIO's to output open drain
  GPIO_InitTypeDef GPIO_InitStruct;
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  GPIO_InitStruct.Pin   = SDA_Pin;
  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  HAL_GPIO_Init(SDA_GPIO_Port, &GPIO_InitStruct);
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  GPIO_InitStruct.Pin   = SCL_Pin;
  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  HAL_GPIO_Init(SCL_GPIO_Port, &GPIO_InitStruct);
  SOFT_SDA1_HIGH();
  SOFT_SCL1_HIGH();
  // To ensure bus is unlocked; we toggle the Clock a bunch of times to make things error out
  for (int i = 0; i < 128; i++) {
    SOFT_SCL1_LOW();
    asm("nop");
    asm("nop");
    asm("nop");
    asm("nop");
    SOFT_SCL1_HIGH();
    asm("nop");
    asm("nop");
    asm("nop");
    asm("nop");
  }
  I2CSemaphore = xSemaphoreCreateMutexStatic(&xSemaphoreBuffer);
  unlock();
}

bool I2CBB1::probe(uint8_t address) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(address);
  stop();
  unlock();
  return ack;
}

bool I2CBB1::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  ack = send(MemAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  SOFT_SCL1_LOW();
  SOFT_I2C_DELAY();
  //	stop();
  start();
  ack = send(DevAddress | 1);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  while (Size) {
    pData[0] = read(Size > 1);
    pData++;
    Size--;
  }
  stop();
  unlock();
  return true;
}

bool I2CBB1::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, const uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  ack = send(MemAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  while (Size) {
    resetWatchdog();
    ack = send(pData[0]);
    if (!ack) {
      stop();
      unlock();
      return false;
    }
    pData++;
    Size--;
  }
  stop();
  unlock();
  return true;
}

void I2CBB1::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return;
  }
  while (Size) {
    ack = send(pData[0]);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    pData++;
    Size--;
  }
  stop();
  unlock();
}

void I2CBB1::Receive(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return;
  }
  start();
  bool ack = send(DevAddress | 1);
  if (!ack) {
    stop();
    unlock();
    return;
  }
  while (Size) {
    pData[0] = read(Size > 1);
    pData++;
    Size--;
  }
  stop();
  unlock();
}

void I2CBB1::TransmitReceive(uint16_t DevAddress, uint8_t *pData_tx, uint16_t Size_tx, uint8_t *pData_rx, uint16_t Size_rx) {
  if (Size_tx == 0 && Size_rx == 0) {
    return;
  }
  if (lock() == false) {
    return;
  }
  if (Size_tx) {
    start();
    bool ack = send(DevAddress);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    while (Size_tx) {
      ack = send(pData_tx[0]);
      if (!ack) {
        stop();
        unlock();
        return;
      }
      pData_tx++;
      Size_tx--;
    }
  }
  if (Size_rx) {
    start();
    bool ack = send(DevAddress | 1);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    while (Size_rx) {
      pData_rx[0] = read(Size_rx > 1);
      pData_rx++;
      Size_rx--;
    }
  }
  stop();
  unlock();
}

void I2CBB1::start() {
  /* I2C Start condition, data line goes low when clock is high */
  SOFT_SCL1_HIGH();
  SOFT_SDA1_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SDA1_LOW();
  SOFT_I2C_DELAY();
  SOFT_SCL1_LOW();
  SOFT_I2C_DELAY();
  SOFT_SDA1_HIGH();
}

void I2CBB1::stop() {
  /* I2C Stop condition, clock goes high when data is low */
  SOFT_SDA1_LOW();
  SOFT_I2C_DELAY();
  SOFT_SCL1_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SDA1_HIGH();
  SOFT_I2C_DELAY();
}

bool I2CBB1::send(uint8_t value) {

  for (uint8_t i = 0; i < 8; i++) {
    write_bit(value & 0x80); // write the most-significant bit
    value <<= 1;
  }

  SOFT_SDA1_HIGH();
  bool ack = (read_bit() == 0);
  return ack;
}

uint8_t I2CBB1::read(bool ack) {
  uint8_t B = 0;

  uint8_t i;
  for (i = 0; i < 8; i++) {
    B <<= 1;
    B |= read_bit();
  }

  SOFT_SDA1_HIGH();
  if (ack) {
    write_bit(0);
  } else {
    write_bit(1);
  }
  return B;
}

uint8_t I2CBB1::read_bit() {
  uint8_t b;

  SOFT_SDA1_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SCL1_HIGH();
  SOFT_I2C_DELAY();

  if (SOFT_SDA1_READ()) {
    b = 1;
  } else {
    b = 0;
  }

  SOFT_SCL1_LOW();
  return b;
}

void I2CBB1::unlock() { xSemaphoreGive(I2CSemaphore); }

bool I2CBB1::lock() {
  if (I2CSemaphore == NULL) {
  }
  bool a = xSemaphoreTake(I2CSemaphore, (TickType_t)100) == pdTRUE;
  return a;
}

bool I2CBB1::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }

uint8_t I2CBB1::I2C_RegisterRead(uint8_t address, uint8_t reg) {
  uint8_t temp = 0;
  Mem_Read(address, reg, &temp, 1);
  return temp;
}

void I2CBB1::write_bit(uint8_t val) {
  if (val) {
    SOFT_SDA1_HIGH();
  } else {
    SOFT_SDA1_LOW();
  }

  SOFT_I2C_DELAY();
  SOFT_SCL1_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SCL1_LOW();
}

bool I2CBB1::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
  for (int index = 0; index < registersLength; index++) {
    if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
      return false;
    }
    if (registers[index].pause_ms) {
      delay_ms(registers[index].pause_ms);
    }
  }
  return true;
}

bool I2CBB1::wakePart(uint16_t DevAddress) {
  // wakepart is a special case  where only the device address is sent
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  stop();
  unlock();
  return ack;
}
#endif


================================================
FILE: source/Core/Drivers/I2CBB1.hpp
================================================
/*
 * I2CBB1.hpp
 *
 *  Created on: 12 Jun 2020
 *      Author: Ralim
 */

#ifndef BSP_MINIWARE_I2CBB1_HPP_
#define BSP_MINIWARE_I2CBB1_HPP_
#include "configuration.h"
#ifdef I2C_SOFT_BUS_1
#include "BSP.h"
#include "FreeRTOS.h"
#include "Pins.h"
#include "Setup.h"
#include "Software_I2C.h"
#include "semphr.h"

class I2CBB1 {
public:
  static void init();
  // Probe if device ACK's address or not
  static bool probe(uint8_t address);
  // Issues a complete 8bit register read
  static bool Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size);
  // Implements a register write
  static bool    Mem_Write(uint16_t DevAddress, uint16_t MemAddress, const uint8_t *pData, uint16_t Size);
  static void    Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    Receive(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    TransmitReceive(uint16_t DevAddress, uint8_t *pData_tx, uint16_t Size_tx, uint8_t *pData_rx, uint16_t Size_rx);
  static bool    I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data);
  static uint8_t I2C_RegisterRead(uint8_t address, uint8_t reg);
  typedef struct {
    const uint8_t reg;      // The register to write to
    uint8_t       val;      // The value to write to this register
    const uint8_t pause_ms; // How many ms to pause _after_ writing this reg
  } I2C_REG;
  static bool writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength);
  static bool wakePart(uint16_t DevAddress);

private:
  static SemaphoreHandle_t I2CSemaphore;
  static StaticSemaphore_t xSemaphoreBuffer;
  static void              unlock();
  static bool              lock();
  static void              start();
  static void              stop();
  static bool              send(uint8_t value);
  static uint8_t           read(bool ack);
  static uint8_t           read_bit();
  static void              write_bit(uint8_t val);
};
#endif
#endif /* BSP_MINIWARE_I2CBB_HPP_ */


================================================
FILE: source/Core/Drivers/I2CBB2.cpp
================================================
/*
 * I2CBB2.cpp
 *
 *  Created on: 12 Jun 2020
 *      Author: Ralim
 */
#include "configuration.h"
#ifdef I2C_SOFT_BUS_2
#include "FreeRTOS.h"
#include 
SemaphoreHandle_t I2CBB2::I2CSemaphore = NULL;
StaticSemaphore_t I2CBB2::xSemaphoreBuffer;
void              I2CBB2::init() {
  // Set GPIO's to output open drain
  GPIO_InitTypeDef GPIO_InitStruct;
  __HAL_RCC_GPIOA_CLK_ENABLE();
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  GPIO_InitStruct.Pin   = SDA2_Pin;
  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  HAL_GPIO_Init(SDA2_GPIO_Port, &GPIO_InitStruct);
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  GPIO_InitStruct.Pin   = SCL2_Pin;
  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull  = GPIO_PULLUP;
  HAL_GPIO_Init(SCL2_GPIO_Port, &GPIO_InitStruct);
  SOFT_SDA2_HIGH();
  SOFT_SCL2_HIGH();
  // To ensure bus is unlocked; we toggle the Clock a bunch of times to make things error out
  for (int i = 0; i < 128; i++) {
    SOFT_SCL2_LOW();
    asm("nop");
    asm("nop");
    asm("nop");
    asm("nop");
    SOFT_SCL2_HIGH();
    asm("nop");
    asm("nop");
    asm("nop");
    asm("nop");
  }
  I2CSemaphore = xSemaphoreCreateMutexStatic(&xSemaphoreBuffer);
  unlock();
}

bool I2CBB2::probe(uint8_t address) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(address);
  stop();
  unlock();
  return ack;
}

bool I2CBB2::Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  ack = send(MemAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  SOFT_SCL2_LOW();
  SOFT_I2C_DELAY();
  //	stop();
  start();
  ack = send(DevAddress | 1);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  while (Size) {
    pData[0] = read(Size > 1);
    pData++;
    Size--;
  }
  stop();
  unlock();
  return true;
}

bool I2CBB2::Mem_Write(uint16_t DevAddress, uint16_t MemAddress, const uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  ack = send(MemAddress);
  if (!ack) {
    stop();
    unlock();
    return false;
  }
  while (Size) {
    resetWatchdog();
    ack = send(pData[0]);
    if (!ack) {
      stop();
      unlock();
      return false;
    }
    pData++;
    Size--;
  }
  stop();
  unlock();
  return true;
}

void I2CBB2::Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return;
  }
  start();
  bool ack = send(DevAddress);
  if (!ack) {
    stop();
    unlock();
    return;
  }
  while (Size) {
    ack = send(pData[0]);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    pData++;
    Size--;
  }
  stop();
  unlock();
}

void I2CBB2::Receive(uint16_t DevAddress, uint8_t *pData, uint16_t Size) {
  if (!lock()) {
    return;
  }
  start();
  bool ack = send(DevAddress | 1);
  if (!ack) {
    stop();
    unlock();
    return;
  }
  while (Size) {
    pData[0] = read(Size > 1);
    pData++;
    Size--;
  }
  stop();
  unlock();
}

void I2CBB2::TransmitReceive(uint16_t DevAddress, uint8_t *pData_tx, uint16_t Size_tx, uint8_t *pData_rx, uint16_t Size_rx) {
  if (Size_tx == 0 && Size_rx == 0) {
    return;
  }
  if (lock() == false) {
    return;
  }
  if (Size_tx) {
    start();
    bool ack = send(DevAddress);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    while (Size_tx) {
      ack = send(pData_tx[0]);
      if (!ack) {
        stop();
        unlock();
        return;
      }
      pData_tx++;
      Size_tx--;
    }
  }
  if (Size_rx) {
    start();
    bool ack = send(DevAddress | 1);
    if (!ack) {
      stop();
      unlock();
      return;
    }
    while (Size_rx) {
      pData_rx[0] = read(Size_rx > 1);
      pData_rx++;
      Size_rx--;
    }
  }
  stop();
  unlock();
}

void I2CBB2::start() {
  /* I2C Start condition, data line goes low when clock is high */
  SOFT_SCL2_HIGH();
  SOFT_SDA2_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SDA2_LOW();
  SOFT_I2C_DELAY();
  SOFT_SCL2_LOW();
  SOFT_I2C_DELAY();
  SOFT_SDA2_HIGH();
}

void I2CBB2::stop() {
  /* I2C Stop condition, clock goes high when data is low */
  SOFT_SDA2_LOW();
  SOFT_I2C_DELAY();
  SOFT_SCL2_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SDA2_HIGH();
  SOFT_I2C_DELAY();
}

bool I2CBB2::send(uint8_t value) {

  for (uint8_t i = 0; i < 8; i++) {
    write_bit(value & 0x80); // write the most-significant bit
    value <<= 1;
  }

  SOFT_SDA2_HIGH();
  bool ack = (read_bit() == 0);
  return ack;
}

uint8_t I2CBB2::read(bool ack) {
  uint8_t B = 0;

  uint8_t i;
  for (i = 0; i < 8; i++) {
    B <<= 1;
    B |= read_bit();
  }

  SOFT_SDA2_HIGH();
  if (ack) {
    write_bit(0);
  } else {
    write_bit(1);
  }
  return B;
}

uint8_t I2CBB2::read_bit() {
  uint8_t b;

  SOFT_SDA2_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SCL2_HIGH();
  SOFT_I2C_DELAY();

  if (SOFT_SDA2_READ()) {
    b = 1;
  } else {
    b = 0;
  }

  SOFT_SCL2_LOW();
  return b;
}

void I2CBB2::unlock() { xSemaphoreGive(I2CSemaphore); }

bool I2CBB2::lock() {
  if (I2CSemaphore == NULL) {
  }
  bool a = xSemaphoreTake(I2CSemaphore, (TickType_t)100) == pdTRUE;
  return a;
}

bool I2CBB2::I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data) { return Mem_Write(address, reg, &data, 1); }

uint8_t I2CBB2::I2C_RegisterRead(uint8_t address, uint8_t reg) {
  uint8_t temp = 0;
  Mem_Read(address, reg, &temp, 1);
  return temp;
}

void I2CBB2::write_bit(uint8_t val) {
  if (val) {
    SOFT_SDA2_HIGH();
  } else {
    SOFT_SDA2_LOW();
  }

  SOFT_I2C_DELAY();
  SOFT_SCL2_HIGH();
  SOFT_I2C_DELAY();
  SOFT_SCL2_LOW();
}

bool I2CBB2::writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength) {
  for (int index = 0; index < registersLength; index++) {
    if (!I2C_RegisterWrite(address, registers[index].reg, registers[index].val)) {
      return false;
    }
    if (registers[index].pause_ms) {
      delay_ms(registers[index].pause_ms);
    }
  }
  return true;
}

bool I2CBB2::wakePart(uint16_t DevAddress) {
  // wakepart is a special case  where only the device address is sent
  if (!lock()) {
    return false;
  }
  start();
  bool ack = send(DevAddress);
  stop();
  unlock();
  return ack;
}
#endif


================================================
FILE: source/Core/Drivers/I2CBB2.hpp
================================================
/*
 * I2CBB2.hpp
 *
 *  Created on: 12 Jun 2020
 *      Author: Ralim
 */

#ifndef BSP_MINIWARE_I2CBB2_HPP_
#define BSP_MINIWARE_I2CBB2_HPP_
#include "configuration.h"
#ifdef I2C_SOFT_BUS_2
#include "BSP.h"
#include "FreeRTOS.h"
#include "Pins.h"
#include "Setup.h"
#include "Software_I2C.h"
#include "semphr.h"

class I2CBB2 {
public:
  static void init();
  // Probe if device ACK's address or not
  static bool probe(uint8_t address);
  // Issues a complete 8bit register read
  static bool Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size);
  // Implements a register write
  static bool    Mem_Write(uint16_t DevAddress, uint16_t MemAddress, const uint8_t *pData, uint16_t Size);
  static void    Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    Receive(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    TransmitReceive(uint16_t DevAddress, uint8_t *pData_tx, uint16_t Size_tx, uint8_t *pData_rx, uint16_t Size_rx);
  static bool    I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data);
  static uint8_t I2C_RegisterRead(uint8_t address, uint8_t reg);
  typedef struct {
    const uint8_t reg;      // The register to write to
    uint8_t       val;      // The value to write to this register
    const uint8_t pause_ms; // How many ms to pause _after_ writing this reg
  } I2C_REG;
  static bool writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength);
  static bool wakePart(uint16_t DevAddress);

private:
  static SemaphoreHandle_t I2CSemaphore;
  static StaticSemaphore_t xSemaphoreBuffer;
  static void              unlock();
  static bool              lock();
  static void              start();
  static void              stop();
  static bool              send(uint8_t value);
  static uint8_t           read(bool ack);
  static uint8_t           read_bit();
  static void              write_bit(uint8_t val);
};
#endif
#endif /* BSP_MINIWARE_I2CBB_HPP_ */


================================================
FILE: source/Core/Drivers/I2C_Wrapper.hpp
================================================
/*
 * FRToSI2C.hpp
 *
 *  Created on: 14Apr.,2018
 *      Author: Ralim
 */

#ifndef FRTOSI2C_HPP_
#define FRTOSI2C_HPP_

#include "cmsis_os.h"

/*
 * Wrapper class to work with the device I2C bus
 *
 * This provides mutex protection of the peripheral
 * Also allows hardware to use DMA should it want to
 *
 *
 */
class FRToSI2C {
public:
  static void FRToSInit() {
    if (I2CSemaphore == nullptr) {
      I2CSemaphore = xSemaphoreCreateBinaryStatic(&xSemaphoreBuffer);
      xSemaphoreGive(I2CSemaphore);
    }
  }

  static void CpltCallback(); // Normal Tx Callback

  static bool Mem_Read(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size);
  static bool Mem_Write(uint16_t DevAddress, uint16_t MemAddress, uint8_t *pData, uint16_t Size);
  // Returns true if device ACK's being addressed
  static bool    probe(uint16_t DevAddress);
  static bool    wakePart(uint16_t DevAddress);
  static bool    Transmit(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    Receive(uint16_t DevAddress, uint8_t *pData, uint16_t Size);
  static void    TransmitReceive(uint16_t DevAddress, uint8_t *pData_tx, uint16_t Size_tx, uint8_t *pData_rx, uint16_t Size_rx);
  static bool    I2C_RegisterWrite(uint8_t address, uint8_t reg, uint8_t data);
  static uint8_t I2C_RegisterRead(uint8_t address, uint8_t reg);

  typedef struct {
    const uint8_t reg;      // The register to write to
    uint8_t       val;      // The value to write to this register
    const uint8_t pause_ms; // How many ms to pause _after_ writing this reg
  } I2C_REG;
  static bool writeRegistersBulk(const uint8_t address, const I2C_REG *registers, const uint8_t registersLength);

private:
  static void              unlock();
  static bool              lock();
  static void              I2C_Unstick();
  static SemaphoreHandle_t I2CSemaphore;
  static StaticSemaphore_t xSemaphoreBuffer;
};

#endif /* FRTOSI2C_HPP_ */


================================================
FILE: source/Core/Drivers/LIS2DH12.cpp
================================================
/*
 * LIS2DH12.cpp
 *
 *  Created on: 27Feb.,2018
 *      Author: Ralim
 */

#include "LIS2DH12.hpp"
#include "cmsis_os.h"
#include "configuration.h"
#include 

static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
    {    LIS_CTRL_REG1,       0x17, 0}, // 25Hz
    {    LIS_CTRL_REG2, 0b00001000, 0}, // Highpass filter off
    {    LIS_CTRL_REG3, 0b01100000, 0}, // Setup interrupt pins
    {    LIS_CTRL_REG4, 0b00001000, 0}, // Block update mode off, HR on
    {    LIS_CTRL_REG5, 0b00000010, 0}, //
    {    LIS_CTRL_REG6, 0b01100010, 0},
    // Basically setup the unit to run, and enable 4D orientation detection
    {     LIS_INT2_CFG, 0b01111110, 0}, // setup for movement detection
    {     LIS_INT2_THS,       0x28, 0}, //
    {LIS_INT2_DURATION,         64, 0}, //
    {     LIS_INT1_CFG, 0b01111110, 0}, //
    {     LIS_INT1_THS,       0x28, 0}, //
    {LIS_INT1_DURATION,         64, 0}
};

bool LIS2DH12::initalize() { return ACCEL_I2C_CLASS::writeRegistersBulk(LIS2DH_I2C_ADDRESS, i2c_registers, sizeof(i2c_registers) / sizeof(i2c_registers[0])); }

void LIS2DH12::getAxisReadings(int16_t &x, int16_t &y, int16_t &z) {
  std::array sensorData;

  ACCEL_I2C_CLASS::Mem_Read(LIS2DH_I2C_ADDRESS, 0xA8, reinterpret_cast(sensorData.begin()), sensorData.size() * sizeof(int16_t));

  x = sensorData[0];
  y = sensorData[1];
  z = sensorData[2];
}

bool LIS2DH12::detect() {
  if (!ACCEL_I2C_CLASS::probe(LIS2DH_I2C_ADDRESS)) {
    return false;
  }
  // Read chip id to ensure its not an address collision
  uint8_t id = 0;
  if (ACCEL_I2C_CLASS::Mem_Read(LIS2DH_I2C_ADDRESS, LIS2DH_WHOAMI_REG, &id, 1)) {
#ifdef ACCEL_LIS_CLONE
    return (id == LIS2DH_WHOAMI_ID) || (id == LIS2DH_CLONE_WHOAMI_ID);
#else
    return (id == LIS2DH_WHOAMI_ID);
#endif
  }
  return false; // cant read ID
}

bool LIS2DH12::isClone() {
#ifdef ACCEL_LIS_CLONE
  uint8_t id = 0;
  if (ACCEL_I2C_CLASS::Mem_Read(LIS2DH_I2C_ADDRESS, LIS2DH_WHOAMI_REG, &id, 1)) {
    return (id == LIS2DH_CLONE_WHOAMI_ID);
  }
#endif
  return false;
}

================================================
FILE: source/Core/Drivers/LIS2DH12.hpp
================================================
/*
 * LIS2DH12.hpp
 *
 *  Created on: 27Feb.,2018
 *      Author: Ralim
 */

#ifndef LIS2DH12_HPP_
#define LIS2DH12_HPP_
#include "BSP.h"

#include "LIS2DH12_defines.hpp"
#include "accelerometers_common.h"

class LIS2DH12 {
public:
  static bool detect();
  static bool isClone();
  static bool initalize();
  // 1 = rh, 2,=lh, 8=flat
  static Orientation getOrientation() {
#ifdef LIS_ORI_FLIP
    uint8_t val = (ACCEL_I2C_CLASS::I2C_RegisterRead(LIS2DH_I2C_ADDRESS, LIS_INT2_SRC) >> 2);
    if (val == 8)
      val = 3;
    else if (val == 1)
      val = 1;
    else if (val == 2)
      val = 0;
    else
      val = 3;
    return static_cast(val);
#else
    return static_cast((ACCEL_I2C_CLASS::I2C_RegisterRead(LIS2DH_I2C_ADDRESS, LIS_INT2_SRC) >> 2) - 1);
#endif
  }
  static void getAxisReadings(int16_t &x, int16_t &y, int16_t &z);

private:
};

#endif /* LIS2DH12_HPP_ */


================================================
FILE: source/Core/Drivers/LIS2DH12_defines.hpp
================================================
/*
 * LIS2DH12_defines.hpp
 *
 *  Created on: 27Feb.,2018
 *      Author: Ralim
 */

#ifndef LIS2DH12_DEFINES_HPP_
#define LIS2DH12_DEFINES_HPP_

#define LIS2DH_I2C_ADDRESS (25 << 1)
#define LIS2DH_WHOAMI_REG  0x0F
#define LIS2DH_WHOAMI_ID   (0b00110011)
#define LIS2DH_CLONE_WHOAMI_ID 0x11
#define LIS_CTRL_REG1      0x20 | 0x80
#define LIS_CTRL_REG2      0x21 | 0x80
#define LIS_CTRL_REG3      0x22 | 0x80
#define LIS_CTRL_REG4      0x23 | 0x80
#define LIS_CTRL_REG5      0x24 | 0x80
#define LIS_CTRL_REG6      0x25 | 0x80
#define LIS_INT1_CFG       0xB0 | 0x80
#define LIS_INT2_CFG       0xB4 | 0x80
#define LIS_INT1_DURATION  0x33 | 0x80
#define LIS_INT1_THS       0x32 | 0x80
#define LIS_INT1_SRC       0x31 | 0x80
#define LIS_INT2_DURATION  0x37 | 0x80
#define LIS_INT2_THS       0x36 | 0x80
#define LIS_INT2_SRC       0x35 | 0x80
#endif /* LIS2DH12_DEFINES_HPP_ */


================================================
FILE: source/Core/Drivers/MMA8652FC.cpp
================================================
/*
 * MMA8652FC.cpp
 *
 *  Created on: 31Aug.,2017
 *      Author: Ben V. Brown
 */

#include "MMA8652FC.hpp"
#include "accelerometers_common.h"
#include "cmsis_os.h"
#include 

#include "MMA8652FC.hpp"
#include "accelerometers_common.h"
#include "cmsis_os.h"

static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
    {           CTRL_REG2,               0, 0}, // Normal mode
    {           CTRL_REG2,            0x40, 2}, // Reset all registers to POR values
    {       FF_MT_CFG_REG,            0x78, 0}, // Enable motion detection for X, Y, Z axis, latch disabled
    {          PL_CFG_REG,            0x40, 0}, // Enable the orientation detection
    {        PL_COUNT_REG,             200, 0}, // 200 count debounce
    {     PL_BF_ZCOMP_REG,      0b01000111, 0}, // Set the threshold to 42 degrees
    {         P_L_THS_REG,      0b10011100, 0}, // Up the trip angles
    {           CTRL_REG4, 0x01 | (1 << 4), 0}, // Enable dataready interrupt & orientation interrupt
    {           CTRL_REG5,            0x01, 0}, // Route data ready interrupts to INT1 ->PB5 ->EXTI5, leaving orientation routed to INT2
    {           CTRL_REG2,            0x12, 0}, // Set maximum resolution oversampling
    {    XYZ_DATA_CFG_REG,        (1 << 4), 0}, // select high pass filtered data
    {HP_FILTER_CUTOFF_REG,            0x03, 0}, // select high pass filtered data
    {           CTRL_REG1,            0x19, 0}  // ODR=12 Hz, Active mode
};

bool MMA8652FC::initalize() { return ACCEL_I2C_CLASS::writeRegistersBulk(MMA8652FC_I2C_ADDRESS, i2c_registers, sizeof(i2c_registers) / sizeof(i2c_registers[0])); }

Orientation MMA8652FC::getOrientation() {
  // First read the PL_STATUS register
  uint8_t plStatus = ACCEL_I2C_CLASS::I2C_RegisterRead(MMA8652FC_I2C_ADDRESS, PL_STATUS_REG);
  if ((plStatus & 0b10000000) == 0b10000000) {
    plStatus >>= 1;   // We don't need the up/down bit
    plStatus &= 0x03; // mask to the two lower bits

    // 0 == left handed
    // 1 == right handed

    return static_cast(plStatus);
  }

  return ORIENTATION_FLAT;
}

void MMA8652FC::getAxisReadings(int16_t &x, int16_t &y, int16_t &z) {
  std::array sensorData;

  ACCEL_I2C_CLASS::Mem_Read(MMA8652FC_I2C_ADDRESS, OUT_X_MSB_REG, reinterpret_cast(sensorData.begin()), sensorData.size() * sizeof(int16_t));

  x = static_cast(__builtin_bswap16(*reinterpret_cast(&sensorData[0])));
  y = static_cast(__builtin_bswap16(*reinterpret_cast(&sensorData[1])));
  z = static_cast(__builtin_bswap16(*reinterpret_cast(&sensorData[2])));
}

bool MMA8652FC::detect() { return ACCEL_I2C_CLASS::probe(MMA8652FC_I2C_ADDRESS); }


================================================
FILE: source/Core/Drivers/MMA8652FC.hpp
================================================
/*
 * MMA8652FC.h
 *
 *  Created on: 31Aug.,2017
 *      Author: Ben V. Brown
 */

#ifndef MMA8652FC_HPP_
#define MMA8652FC_HPP_
#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "MMA8652FC_defines.h"

class MMA8652FC {

public:
  // Returns true if this accelerometer is detected
  static bool detect();
  // Init any internal state
  static bool        initalize();
  static Orientation getOrientation(); // Reads the I2C register and returns the orientation (true == left)
  static void        getAxisReadings(int16_t &x, int16_t &y, int16_t &z);

private:
};

#endif /* MMA8652FC_HPP_ */


================================================
FILE: source/Core/Drivers/MMA8652FC_defines.h
================================================
/*
 * MMA8652FC_defines.h
 *
 *  Created on: 31Aug.,2017
 *      Author: Ben V. Brown
 */

#ifndef MMA8652FC_DEFINES_H_
#define MMA8652FC_DEFINES_H_

//--------------MMA8652 Registers-------------------------------------------//

#define STATUS_REG 0x00 // STATUS Register

#define OUT_X_MSB_REG 0x01 // [7:0] are 8 MSBs of the 14-bit X-axis sample
#define OUT_X_LSB_REG 0x02 // [7:2] are the 6 LSB of 14-bit X-axis sample
#define OUT_Y_MSB_REG 0x03 // [7:0] are 8 MSBs of the 14-bit Y-axis sample
#define OUT_Y_LSB_REG 0x04 // [7:2] are the 6 LSB of 14-bit Y-axis sample
#define OUT_Z_MSB_REG 0x05 // [7:0] are 8 MSBs of the 14-bit Z-axis sample
#define OUT_Z_LSB_REG 0x06 // [7:2] are the 6 LSB of 14-bit Z-axis sample

#define F_SETUP_REG          0x09 // F_SETUP FIFO Setup Register
#define TRIG_CFG_REG         0x0A // TRIG_CFG Map of FIFO data capture events
#define SYSMOD_REG           0x0B // SYSMOD System Mode Register
#define INT_SOURCE_REG       0x0C // INT_SOURCE System Interrupt Status Register
#define WHO_AM_I_REG         0x0D // WHO_AM_I Device ID Register
#define XYZ_DATA_CFG_REG     0x0E // XYZ_DATA_CFG Sensor Data Configuration Register
#define HP_FILTER_CUTOFF_REG 0x0F // HP_FILTER_CUTOFF High Pass Filter Register

#define PL_STATUS_REG   0x10 // PL_STATUS Portrait/Landscape Status Register
#define PL_CFG_REG      0x11 // PL_CFG Portrait/Landscape Configuration Register
#define PL_COUNT_REG    0x12 // PL_COUNT Portrait/Landscape Debounce Register
#define PL_BF_ZCOMP_REG 0x13 // PL_BF_ZCOMP Back/Front and Z Compensation Register
#define P_L_THS_REG     0x14 // P_L_THS Portrait to Landscape Threshold Register

#define FF_MT_CFG_REG   0x15 // FF_MT_CFG Freefall and Motion Configuration Register
#define FF_MT_SRC_REG   0x16 // FF_MT_SRC Freefall and Motion Source Register
#define FF_MT_THS_REG   0x17 // FF_MT_THS Freefall and Motion Threshold Register
#define FF_MT_COUNT_REG 0x18 // FF_MT_COUNT Freefall Motion Count Register

#define TRANSIENT_CFG_REG   0x1D // TRANSIENT_CFG Transient Configuration Register
#define TRANSIENT_SRC_REG   0x1E // TRANSIENT_SRC Transient Source Register
#define TRANSIENT_THS_REG   0x1F // TRANSIENT_THS Transient Threshold Register
#define TRANSIENT_COUNT_REG 0x20 // TRANSIENT_COUNT Transient Debounce Counter Register

#define PULSE_CFG_REG  0x21 // PULSE_CFG Pulse Configuration Register
#define PULSE_SRC_REG  0x22 // PULSE_SRC Pulse Source Register
#define PULSE_THSX_REG 0x23 // PULSE_THS XYZ Pulse Threshold Registers
#define PULSE_THSY_REG 0x24
#define PULSE_THSZ_REG 0x25
#define PULSE_TMLT_REG 0x26 // PULSE_TMLT Pulse Time Window Register
#define PULSE_LTCY_REG 0x27 // PULSE_LTCY Pulse Latency Timer Register
#define PULSE_WIND_REG 0x28 // PULSE_WIND Second Pulse Time Window Register

#define ASLP_COUNT_REG 0x29 // ASLP_COUNT Auto Sleep Inactivity Timer Register

#define CTRL_REG1 0x2A // CTRL_REG1 System Control 1 Register
#define CTRL_REG2 0x2B // CTRL_REG2 System Control 2 Register
#define CTRL_REG3 0x2C // CTRL_REG3 Interrupt Control Register
#define CTRL_REG4 0x2D // CTRL_REG4 Interrupt Enable Register
#define CTRL_REG5 0x2E // CTRL_REG5 Interrupt Configuration Register

#define OFF_X_REG 0x2F // XYZ Offset Correction Registers
#define OFF_Y_REG 0x30
#define OFF_Z_REG 0x31

// MMA8652FC 7-bit I2C address

#define MMA8652FC_I2C_ADDRESS (0x1D << 1)

// MMA8652FC Sensitivity

#define SENSITIVITY_2G 1024
#define SENSITIVITY_4G 512
#define SENSITIVITY_8G 256

#define STATUS_REG 0x00
#define X_MSB_REG  0X01
#define X_LSB_REG  0X02
#define Y_MSB_REG  0X03
#define Y_LSB_REG  0X04
#define Z_MSB_REG  0X05
#define Z_LSB_REG  0X06

#define TRIG_CFG   0X0A
#define SYSMOD     0X0B
#define INT_SOURCE 0X0C
#define DEVICE_ID  0X0D

//-----STATUS_REG(0X00)-----Bit Define----------------------------------------//
#define ZYXDR_BIT 0X08
//----XYZ_DATA_CFG_REG(0xE)-Bit Define----------------------------------------//
#define FS_MASK       0x03
#define FULL_SCALE_2G 0x00 // 2g=0x0,4g=0x1,8g=0x2
#define FULL_SCALE_4G 0x01
#define FULL_SCALE_8G 0x02
//---------CTRL_REG1(0X2A)Bit Define------------------------------------------//
#define ACTIVE_MASK 1 << 0 // bit0
#define DR_MASK     0x38   // bit D5,D4,D3
#define FHZ800      0x0    // 800hz
#define FHZ400      0x1    // 400hz
#define FHZ200      0x2    // 200hz
#define FHZ100      0x3    // 100hz
#define FHZ50       0x4    // 50hz
#define FHZ2        0x5    // 12.5hz
#define FHZ1        0x6    // 6.25hz
#define FHZ0        0x7    // 1.563hz

//---------CTRL_REG2(0X2B)Bit Define------------------------------------------//
#define MODS_MASK   0x03 // Oversampling Mode 4
#define Normal_Mode 0x0  // Normal=0,Low Noise Low Power MODS=1,
// HI RESOLUTION=2,LOW POWER MODS = 11
//----CTRL_REG4---Interrupt Enable BIT ---------------------------------------//
// 0 interrupt is disabled (default)
// 1 interrupt is enabled
#define INT_EN_ASLP   1 << 7 // Auto-SLEEP/WAKE Interrupt Enable
#define INT_EN_FIFO   1 << 6 // FIFO Interrupt Enable
#define INT_EN_TRANS  1 << 5 // Transient Interrupt Enable
#define INT_EN_LNDPRT 1 << 4 // Orientation(Landscape/Portrait)Interrupt Enable
#define INT_EN_PULSE  1 << 3 // Pulse Detection Interrupt Enable
#define INT_EN_FF_MT  1 << 2 // Freefall/Motion Interrupt Enable
#define INT_EN_DRDY   1 << 0 // Data Ready Interrupt Enable

#endif /* MMA8652FC_DEFINES_H_ */


================================================
FILE: source/Core/Drivers/MSA301.cpp
================================================
/*
 * MSA301.cpp
 *
 *  Created on: 3 Jan 2021
 *      Author: Ralim
 */

#include "MSA301_defines.h"
#include "accelerometers_common.h"
#include 

#define MSA301_I2C_ADDRESS 0x26 << 1
bool MSA301::detect() { return ACCEL_I2C_CLASS::probe(MSA301_I2C_ADDRESS); }

static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
    //
    //
    {      MSA301_REG_ODR, 0b00001000, 1}, // X/Y/Z enabled @ 250Hz
    {MSA301_REG_POWERMODE,  0b0001001, 1}, // Normal mode
    { MSA301_REG_RESRANGE, 0b00000001, 0}, // 14bit resolution @ 4G range
    {MSA301_REG_ORIENT_HY, 0b01000000, 0}, // 4*62.5mg hyst, no blocking, symmetrical
    {  MSA301_REG_INTSET0,     1 << 6, 0}, // Turn on orientation detection (by enabling its interrupt)
};

bool MSA301::initalize() { return ACCEL_I2C_CLASS::writeRegistersBulk(MSA301_I2C_ADDRESS, i2c_registers, sizeof(i2c_registers) / sizeof(i2c_registers[0])); }

Orientation MSA301::getOrientation() {
  uint8_t temp = 0;
  ACCEL_I2C_CLASS::Mem_Read(MSA301_I2C_ADDRESS, MSA301_REG_ORIENT_STATUS, &temp, 1);
  switch (temp) {
  case 112:
    return Orientation::ORIENTATION_LEFT_HAND;
  case 96:
    return Orientation::ORIENTATION_RIGHT_HAND;
  default:
    return Orientation::ORIENTATION_FLAT;
  }
}

void MSA301::getAxisReadings(int16_t &x, int16_t &y, int16_t &z) {
  uint8_t temp[6];
  // Bulk read all 6 regs
  ACCEL_I2C_CLASS::Mem_Read(MSA301_I2C_ADDRESS, MSA301_REG_OUT_X_L, temp, 6);
  x = int16_t(((int16_t)temp[1]) << 8 | temp[0]) >> 2;
  y = int16_t(((int16_t)temp[3]) << 8 | temp[2]) >> 2;
  z = int16_t(((int16_t)temp[5]) << 8 | temp[4]) >> 2;
}


================================================
FILE: source/Core/Drivers/MSA301.h
================================================
/*
 * MSA301.h
 *
 *  Created on: 3 Jan 2021
 *      Author: Ralim
 */

#ifndef DRIVERS_MSA301_H_
#define DRIVERS_MSA301_H_
#include "BSP.h"
#include "I2C_Wrapper.hpp"

class MSA301 {
public:
  // Returns true if this accelerometer is detected
  static bool detect();
  // Init any internal state
  static bool initalize();
  // Reads the I2C register and returns the orientation
  static Orientation getOrientation();
  // Return the x/y/z axis readings as signed int16's
  static void getAxisReadings(int16_t &x, int16_t &y, int16_t &z);

private:
};

#endif /* DRIVERS_MSA301_H_ */


================================================
FILE: source/Core/Drivers/MSA301_defines.h
================================================
/*
 * MSA301_defines.h
 *
 *  Created on: 3 Jan 2021
 *      Author: Ralim
 */

#ifndef DRIVERS_MSA301_DEFINES_H_
#define DRIVERS_MSA301_DEFINES_H_
// Definitions from Adafruit <3

#define MSA301_REG_PARTID        0x01 ///< Register that contains the part ID
#define MSA301_REG_OUT_X_L       0x02 ///< Register address for X axis lower byte
#define MSA301_REG_OUT_X_H       0x03 ///< Register address for X axis higher byte
#define MSA301_REG_OUT_Y_L       0x04 ///< Register address for Y axis lower byte
#define MSA301_REG_OUT_Y_H       0x05 ///< Register address for Y axis higher byte
#define MSA301_REG_OUT_Z_L       0x06 ///< Register address for Z axis lower byte
#define MSA301_REG_OUT_Z_H       0x07 ///< Register address for Z axis higher byte
#define MSA301_REG_MOTIONINT     0x09 ///< Register address for motion interrupt
#define MSA301_REG_DATAINT       0x0A ///< Register address for data interrupt
#define MSA301_REG_CLICKSTATUS   0x0B ///< Register address for click/doubleclick status
#define MSA301_REG_RESRANGE      0x0F ///< Register address for resolution range
#define MSA301_REG_ODR           0x10 ///< Register address for data rate setting
#define MSA301_REG_POWERMODE     0x11 ///< Register address for power mode setting
#define MSA301_REG_INTSET0       0x16 ///< Register address for interrupt setting #0
#define MSA301_REG_INTSET1       0x17 ///< Register address for interrupt setting #1
#define MSA301_REG_INTMAP0       0x19 ///< Register address for interrupt map #0
#define MSA301_REG_INTMAP1       0x1A ///< Register address for interrupt map #1
#define MSA301_REG_TAPDUR        0x2A ///< Register address for tap duration
#define MSA301_REG_TAPTH         0x2B ///< Register address for tap threshold
#define MSA301_REG_ORIENT_HY     0x2C ///< Register address for orientation Hysteresis
#define MSA301_REG_ORIENT_STATUS 0x0C ///< Register address for orientation hysteresis

#endif /* DRIVERS_MSA301_DEFINES_H_ */


================================================
FILE: source/Core/Drivers/OLED.cpp
================================================
/*
 * OLED.cpp
 *
 *  Created on: 29Aug.,2017
 *      Author: Ben V. Brown
 */

#include "Buttons.hpp"
#include "Settings.h"
#include "Translation.h"
#include "cmsis_os.h"
#include "configuration.h"
#include 
#include 
#include 
#include 

// rendering to the buffer
uint8_t *OLED::stripPointers[4]; // Pointers to the strips to allow for buffer having extra content

bool OLED::inLeftHandedMode; // Whether the screen is in left or not (used for
// offsets in GRAM)
OLED::DisplayState OLED::displayState;
int16_t            OLED::cursor_x, OLED::cursor_y;
bool               OLED::initDone = false;
uint8_t            OLED::displayOffset;
alignas(uint32_t) uint8_t OLED::screenBuffer[16 + (OLED_WIDTH * (OLED_HEIGHT / 8)) + 10]; // The data buffer
alignas(uint32_t) uint8_t OLED::secondFrameBuffer[16 + (OLED_WIDTH * (OLED_HEIGHT / 8)) + 10];
uint32_t OLED::displayChecksum;
/*
 * Setup params for the OLED screen
 * http://www.displayfuture.com/Display/datasheet/controller/SSD1307.pdf
 * All commands are prefixed with 0x80
 * Data packets are prefixed with 0x40
 */
I2C_CLASS::I2C_REG OLED_Setup_Array[] = {
    /**/
    {0x80,         OLED_OFF, 0}, /* Display off */
    {0x80,     OLED_DIVIDER, 0}, /* Set display clock divide ratio / osc freq */
    {0x80,             0x52, 0}, /* Divide ratios */
    {0x80,             0xA8, 0}, /* Set Multiplex Ratio */
    {0x80,  OLED_HEIGHT - 1, 0}, /* Multiplex ratio adjusts how far down the matrix it scans */
    {0x80,             0xC0, 0}, /* Set COM Scan direction */
    {0x80,             0xD3, 0}, /* Set vertical Display offset */
    {0x80,             0x00, 0}, /* 0 Offset */
    {0x80,             0x40, 0}, /* Set Display start line to 0 */
#ifdef OLED_SEGMENT_MAP_REVERSED
    {0x80,             0xA1, 0}, /* Set Segment remap to normal */
#else
    {0x80, 0xA0, 0}, /* Set Segment remap to normal */
#endif
    {0x80,             0x8D, 0}, /* Charge Pump */
    {0x80,             0x14, 0}, /* Charge Pump settings */
    {0x80,             0xDA, 0}, /* Set VCOM Pins hardware config */
    {0x80, OLED_VCOM_LAYOUT, 0}, /* Combination 0x2 or 0x12 depending on OLED model */
    {0x80,             0x81, 0}, /* Brightness */
    {0x80,             0x00, 0}, /* ^0 */
    {0x80,             0xD9, 0}, /* Set pre-charge period */
    {0x80,             0xF1, 0}, /* Pre charge period */
    {0x80,             0xDB, 0}, /* Adjust VCOMH regulator ouput */
    {0x80,             0x30, 0}, /* VCOM level */
    {0x80,             0xA4, 0}, /* Enable the display GDDR */
    {0x80,             0xA6, 0}, /* Normal display */
    {0x80,             0x20, 0}, /* Memory Mode */
    {0x80,             0x00, 0}, /* Wrap memory */
    {0x80,          OLED_ON, 0}, /* Display on */
};
// Setup based on the SSD1307 and modified for the SSD1306

const uint8_t REFRESH_COMMANDS[17] = {
    // Set display ON:
    0x80,
    0xAF, // cmd

    // Set column address:
    //  A[6:0] - Column start address = 0x20
    //  B[6:0] - Column end address = 0x7F
    0x80,
    0x21, // cmd
    0x80,
    OLED_GRAM_START, // A
    0x80,
    OLED_GRAM_END, // B

    // Set COM output scan direction (normal mode, COM0 to COM[N-1])
    0x80,
    0xC0,

    // Set page address:
    //  A[2:0] - Page start address = 0
    //  B[2:0] - Page end address = 1
    0x80,
    0x22, // cmd
    0x80,
    0x00, // A
    0x80,
    (OLED_HEIGHT / 8) - 1, // B

    // Start of data
    0x40,
};

/*
 * Animation timing function that follows a bezier curve.
 * @param t A given percentage value [0..<100]
 * Returns a new percentage value with ease in and ease out.
 * Original floating point formula: t * t * (3.0f - 2.0f * t);
 */
static uint16_t easeInOutTiming(uint16_t t) { return t * t * (300 - 2 * t) / 10000; }

/*
 * Returns the value between a and b, using a percentage value t.
 * @param a The value associated with 0%
 * @param b The value associated with 100%
 * @param t The percentage [0..<100]
 */
static uint16_t lerp(uint16_t a, uint16_t b, uint16_t t) { return a + t * (b - a) / 100; }

void OLED::initialize() {
  cursor_x = cursor_y = 0;
  inLeftHandedMode    = false;

#ifdef OLED_128x32
  stripPointers[0] = &screenBuffer[FRAMEBUFFER_START];
  stripPointers[1] = &screenBuffer[FRAMEBUFFER_START + OLED_WIDTH];
  stripPointers[2] = &screenBuffer[FRAMEBUFFER_START + 2 * OLED_WIDTH];
  stripPointers[3] = &screenBuffer[FRAMEBUFFER_START + 3 * OLED_WIDTH];

#else
  stripPointers[0] = &screenBuffer[FRAMEBUFFER_START];
  stripPointers[1] = &screenBuffer[FRAMEBUFFER_START + OLED_WIDTH];

#endif /* OLED_128x32 */
  displayOffset = 0;
  memcpy(&screenBuffer[0], &REFRESH_COMMANDS[0], sizeof(REFRESH_COMMANDS));
  memcpy(&secondFrameBuffer[0], &REFRESH_COMMANDS[0], sizeof(REFRESH_COMMANDS));

  // Set the display to be ON once the settings block is sent and send the
  // initialisation data to the OLED.

  for (int tries = 0; tries < 10; tries++) {
    if (I2C_CLASS::writeRegistersBulk(DEVICEADDR_OLED, OLED_Setup_Array, sizeof(OLED_Setup_Array) / sizeof(OLED_Setup_Array[0]))) {
      tries = 11;
    }
  }
  setDisplayState(DisplayState::ON);
  initDone = true;
}

void OLED::setFramebuffer(uint8_t *buffer) {
  stripPointers[0] = &buffer[FRAMEBUFFER_START];
  stripPointers[1] = &buffer[FRAMEBUFFER_START + OLED_WIDTH];

#ifdef OLED_128x32
  stripPointers[2] = &buffer[FRAMEBUFFER_START + (2 * OLED_WIDTH)];
  stripPointers[3] = &buffer[FRAMEBUFFER_START + (3 * OLED_WIDTH)];
#endif /* OLED_128x32 */
}

/*
 * Prints a char to the screen.
 * UTF font handling is done using the two input chars.
 * Precursor is the command char that is used to select the table.
 */
void OLED::drawChar(const uint16_t charCode, const FontStyle fontStyle, const uint8_t soft_x_limit) {
  const uint8_t *currentFont;
  static uint8_t fontWidth, fontHeight;
  uint16_t       index;
  switch (fontStyle) {
  case FontStyle::EXTRAS:
    currentFont = ExtraFontChars;
    index       = charCode;
    fontHeight  = 16;
    fontWidth   = 12;
    break;
  case FontStyle::SMALL:
  case FontStyle::LARGE:
  default:
    currentFont = nullptr;
    index       = 0;
    switch (fontStyle) {
    case FontStyle::SMALL:
      fontHeight = 8;
      fontWidth  = 6;
      break;
    case FontStyle::LARGE:
    default:
      fontHeight = 16;
      fontWidth  = 12;
      break;
    }
    if (charCode == '\x01' && cursor_y == 0) { // 0x01 is used as new line char
      setCursor(soft_x_limit, fontHeight);
      return;
    } else if (charCode <= 0x01) {
      return;
    }

    currentFont = fontStyle == FontStyle::SMALL ? FontSectionInfo.font06_start_ptr : FontSectionInfo.font12_start_ptr;
    index       = charCode - 2;
    break;
  }
  const uint8_t *charPointer = currentFont + ((fontWidth * (fontHeight / 8)) * index);
  drawArea(cursor_x, cursor_y, fontWidth, fontHeight, charPointer);
  cursor_x += fontWidth;
}

/*
 * Draws a one pixel wide scrolling indicator. y is the upper vertical position
 * of the indicator in pixels (0..<16).
 */
void OLED::drawScrollIndicator(uint8_t y, uint8_t height) {

  const uint32_t whole = ((1 << height) - 1) << y; // preload a set of set bits of height
                                                   // Shift down by the y value
  const uint8_t strips[4] = {static_cast(whole & 0xff), static_cast((whole & 0xff00) >> 8 * 1), static_cast((whole & 0xff0000) >> 8 * 2),
                             static_cast((whole & 0xff000000) >> 8 * 3)};
  // Draw a one pixel wide bar to the left with a single pixel as
  // the scroll indicator.
  fillArea(OLED_WIDTH - 1, 0, 1, 8, strips[0]);
  fillArea(OLED_WIDTH - 1, 8, 1, 8, strips[1]);
#if OLED_HEIGHT == 32
  fillArea(OLED_WIDTH - 1, 16, 1, 8, strips[2]);
  fillArea(OLED_WIDTH - 1, 24, 1, 8, strips[3]);

#endif
}

/**
 * Masks (removes) the scrolling indicator, i.e. clears the rightmost column
 * on the screen. This operates directly on the OLED graphics RAM, as this
 * is intended to be used before calling `OLED::transitionScrollDown()`.
 */
void OLED::maskScrollIndicatorOnOLED() {
  // The right-most column depends on the screen rotation, so just take
  // it from the screen buffer which is updated by `OLED::setRotation`.
  uint8_t rightmostColumn = screenBuffer[7];
  uint8_t maskCommands[]  = {
      // Set column address:
      //  A[6:0] - Column start address = rightmost column
      //  B[6:0] - Column end address = rightmost column
      0x80,
      0x21, // cmd
      0x80,
      rightmostColumn, // A
      0x80,
      rightmostColumn, // B

      // Start of data
      0x40,
#ifdef OLED_128x32
      0x00,
      0x00,
#endif /* OLED_128x32 */
      // Clears two 8px strips
      0x00,
      0x00,
  };
  I2C_CLASS::Transmit(DEVICEADDR_OLED, maskCommands, sizeof(maskCommands));
}

/**
 * Plays a transition animation between two framebuffers.
 * @param forwardNavigation Direction of the navigation animation.
 *
 * If forward is true, this displays a forward navigation to the second framebuffer contents.
 * Otherwise a rewinding navigation animation is shown to the second framebuffer contents.
 */
void OLED::transitionSecondaryFramebuffer(const bool forwardNavigation, const TickType_t viewEnterTime) {
  bool     buttonsReleased = getButtonState() == BUTTON_NONE;
  uint8_t *stripBackPointers[4];
  stripBackPointers[0] = &secondFrameBuffer[FRAMEBUFFER_START + 0];
  stripBackPointers[1] = &secondFrameBuffer[FRAMEBUFFER_START + OLED_WIDTH];

#ifdef OLED_128x32
  stripBackPointers[2] = &secondFrameBuffer[FRAMEBUFFER_START + (OLED_WIDTH * 2)];
  stripBackPointers[3] = &secondFrameBuffer[FRAMEBUFFER_START + (OLED_WIDTH * 3)];
#endif /* OLED_128x32 */

  TickType_t totalDuration = TICKS_100MS * 5; // 500ms
  TickType_t duration      = 0;
  TickType_t start         = xTaskGetTickCount();
  uint8_t    offset        = 0;
  uint32_t   loopCounter   = 0;
  TickType_t startDraw     = xTaskGetTickCount();
  while (duration <= totalDuration) {
    loopCounter++;
    duration          = xTaskGetTickCount() - start;
    uint16_t progress = ((duration * 100) / totalDuration); // Percentage of the period we are through for animation
    progress          = easeInOutTiming(progress);
    progress          = lerp(0, OLED_WIDTH, progress);
    // Constrain
    if (progress > OLED_WIDTH) {
      progress = OLED_WIDTH;
    }

    // When forward, current contents move to the left out.
    // Otherwise the contents move to the right out.
    uint8_t oldStart    = forwardNavigation ? 0 : progress;
    uint8_t oldPrevious = forwardNavigation ? progress - offset : offset;

    // Content from the second framebuffer moves in from the right (forward)
    // or from the left (not forward).
    uint8_t newStart = forwardNavigation ? OLED_WIDTH - progress : 0;
    uint8_t newEnd   = forwardNavigation ? 0 : OLED_WIDTH - progress;

    offset = progress;

    memmove(&stripPointers[0][oldStart], &stripPointers[0][oldPrevious], OLED_WIDTH - progress);
    memmove(&stripPointers[1][oldStart], &stripPointers[1][oldPrevious], OLED_WIDTH - progress);

#ifdef OLED_128x32
    memmove(&stripPointers[2][oldStart], &stripPointers[2][oldPrevious], OLED_WIDTH - progress);
    memmove(&stripPointers[3][oldStart], &stripPointers[3][oldPrevious], OLED_WIDTH - progress);
#endif /* OLED_128x32 */

    memmove(&stripPointers[0][newStart], &stripBackPointers[0][newEnd], progress);
    memmove(&stripPointers[1][newStart], &stripBackPointers[1][newEnd], progress);

#ifdef OLED_128x32
    memmove(&stripPointers[2][newStart], &stripBackPointers[2][newEnd], progress);
    memmove(&stripPointers[3][newStart], &stripBackPointers[3][newEnd], progress);
#endif /* OLED_128x32 */

#ifdef OLED_128x32
    if (loopCounter % 2 == 0) {
      refresh();
    }
#else
    refresh(); // Now refresh to write out the contents to the new page
#endif /* OLED_128x32 */

    vTaskDelayUntil(&startDraw, TICKS_100MS / 7);
    buttonsReleased |= getButtonState() == BUTTON_NONE;
    if (getButtonState() != BUTTON_NONE && buttonsReleased) {
      memcpy(screenBuffer + FRAMEBUFFER_START, secondFrameBuffer + FRAMEBUFFER_START, sizeof(screenBuffer) - FRAMEBUFFER_START);
      refresh(); // Now refresh to write out the contents to the new page
      return;
    }
  }
  refresh(); // redraw at the end if required
}

void OLED::useSecondaryFramebuffer(bool useSecondary) {
  if (useSecondary) {
    setFramebuffer(secondFrameBuffer);
  } else {
    setFramebuffer(screenBuffer);
  }
}

/**
 * This assumes that the current display output buffer has the current on screen contents
 * Then the secondary buffer has the "new" contents to be slid up onto the screen
 * Sadly we cant use the hardware scroll as some devices with the 128x32 screens dont have the GRAM for holding both screens at once
 *
 * **This function blocks until the transition has completed or user presses button**
 */
void OLED::transitionScrollDown(const TickType_t viewEnterTime) {
  TickType_t startDraw       = xTaskGetTickCount();
  bool       buttonsReleased = getButtonState() == BUTTON_NONE;

  for (uint8_t heightPos = 0; heightPos < OLED_HEIGHT; heightPos++) {
    // For each line, we shuffle all bits up a row
    for (uint8_t xPos = 0; xPos < OLED_WIDTH; xPos++) {
      const uint16_t firstStripPos  = FRAMEBUFFER_START + xPos;
      const uint16_t secondStripPos = firstStripPos + OLED_WIDTH;
#ifdef OLED_128x32
      // For 32 pixel high OLED's we have four strips to tailchain
      const uint16_t thirdStripPos  = secondStripPos + OLED_WIDTH;
      const uint16_t fourthStripPos = thirdStripPos + OLED_WIDTH;
      // Move the MSB off the first strip, and pop MSB from second strip onto the first strip
      screenBuffer[firstStripPos] = (screenBuffer[firstStripPos] >> 1) | ((screenBuffer[secondStripPos] & 0x01) << 7);
      // Now shuffle off the second strip
      screenBuffer[secondStripPos] = (screenBuffer[secondStripPos] >> 1) | ((screenBuffer[thirdStripPos] & 0x01) << 7);
      // Now shuffle off the third strip
      screenBuffer[thirdStripPos] = (screenBuffer[thirdStripPos] >> 1) | ((screenBuffer[fourthStripPos] & 0x01) << 7);
      // Now forth strip gets the start of the new buffer
      screenBuffer[fourthStripPos] = (screenBuffer[fourthStripPos] >> 1) | ((secondFrameBuffer[firstStripPos] & 0x01) << 7);
      // Now cycle all the secondary buffers

      secondFrameBuffer[firstStripPos]  = (secondFrameBuffer[firstStripPos] >> 1) | ((secondFrameBuffer[secondStripPos] & 0x01) << 7);
      secondFrameBuffer[secondStripPos] = (secondFrameBuffer[secondStripPos] >> 1) | ((secondFrameBuffer[thirdStripPos] & 0x01) << 7);
      secondFrameBuffer[thirdStripPos]  = (secondFrameBuffer[thirdStripPos] >> 1) | ((secondFrameBuffer[fourthStripPos] & 0x01) << 7);
      // Finally on the bottom row; we shuffle it up ready
      secondFrameBuffer[fourthStripPos] >>= 1;
#else
      // Move the LSB off the first strip, and pop MSB from second strip onto the first strip
      screenBuffer[firstStripPos] = (screenBuffer[firstStripPos] >> 1) | ((screenBuffer[secondStripPos] & 0x01) << 7);
      // Now shuffle off the second strip MSB, and replace it with the LSB of the secondary buffer
      screenBuffer[secondStripPos] = (screenBuffer[secondStripPos] >> 1) | ((secondFrameBuffer[firstStripPos] & 0x01) << 7);
      // Finally, do the shuffle on the second frame buffer
      secondFrameBuffer[firstStripPos] = (secondFrameBuffer[firstStripPos] >> 1) | ((secondFrameBuffer[secondStripPos] & 0x01) << 7);
      // Finally on the bottom row; we shuffle it up ready
      secondFrameBuffer[secondStripPos] >>= 1;
#endif /* OLED_128x32 */
    }
    buttonsReleased |= getButtonState() == BUTTON_NONE;
    if (getButtonState() != BUTTON_NONE && buttonsReleased) {
      // Exit early, but have to transition whole buffer
      memcpy(screenBuffer + FRAMEBUFFER_START, secondFrameBuffer + FRAMEBUFFER_START, sizeof(screenBuffer) - FRAMEBUFFER_START);
      refresh(); // Now refresh to write out the contents to the new page
      return;
    }
#ifdef OLED_128x32
    // To keep things faster, only redraw every second line
    if (heightPos % 2 == 0) {
      refresh(); // Now refresh to write out the contents to the new page
    }
#else
    refresh(); // Now refresh to write out the contents to the new page
#endif
    vTaskDelayUntil(&startDraw, TICKS_100MS / 7);
  }
}
/**
 * This assumes that the current display output buffer has the current on screen contents
 * Then the secondary buffer has the "new" contents to be slid down onto the screen
 * Sadly we cant use the hardware scroll as some devices with the 128x32 screens dont have the GRAM for holding both screens at once
 *
 * **This function blocks until the transition has completed or user presses button**
 */
void OLED::transitionScrollUp(const TickType_t viewEnterTime) {
  TickType_t startDraw       = xTaskGetTickCount();
  bool       buttonsReleased = getButtonState() == BUTTON_NONE;

  for (uint8_t heightPos = 0; heightPos < OLED_HEIGHT; heightPos++) {
    // For each line, we shuffle all bits down a row
    for (uint8_t xPos = 0; xPos < OLED_WIDTH; xPos++) {
      const uint16_t firstStripPos  = FRAMEBUFFER_START + xPos;
      const uint16_t secondStripPos = firstStripPos + OLED_WIDTH;
#ifdef OLED_128x32
      // For 32 pixel high OLED's we have four strips to tailchain
      const uint16_t thirdStripPos  = secondStripPos + OLED_WIDTH;
      const uint16_t fourthStripPos = thirdStripPos + OLED_WIDTH;
      // We are shffling LSB's off the end and pushing bits down
      screenBuffer[fourthStripPos] = (screenBuffer[fourthStripPos] << 1) | ((screenBuffer[thirdStripPos] & 0x80) >> 7);
      screenBuffer[thirdStripPos]  = (screenBuffer[thirdStripPos] << 1) | ((screenBuffer[secondStripPos] & 0x80) >> 7);
      screenBuffer[secondStripPos] = (screenBuffer[secondStripPos] << 1) | ((screenBuffer[firstStripPos] & 0x80) >> 7);
      screenBuffer[firstStripPos]  = (screenBuffer[firstStripPos] << 1) | ((secondFrameBuffer[fourthStripPos] & 0x80) >> 7);

      secondFrameBuffer[fourthStripPos] = (secondFrameBuffer[fourthStripPos] << 1) | ((secondFrameBuffer[thirdStripPos] & 0x80) >> 7);
      secondFrameBuffer[thirdStripPos]  = (secondFrameBuffer[thirdStripPos] << 1) | ((secondFrameBuffer[secondStripPos] & 0x80) >> 7);
      secondFrameBuffer[secondStripPos] = (secondFrameBuffer[secondStripPos] << 1) | ((secondFrameBuffer[firstStripPos] & 0x80) >> 7);
      // Finally on the bottom row; we shuffle it up ready
      secondFrameBuffer[firstStripPos] <<= 1;
#else
      // We pop the LSB off the bottom row, and replace the MSB in that byte with the LSB of the row above
      screenBuffer[secondStripPos] = (screenBuffer[secondStripPos] << 1) | ((screenBuffer[firstStripPos] & 0x80) >> 7);
      // Move the LSB off the first strip, and pop MSB from second strip onto the first strip
      screenBuffer[firstStripPos] = (screenBuffer[firstStripPos] << 1) | ((secondFrameBuffer[secondStripPos] & 0x80) >> 7);

      // Finally, do the shuffle on the second frame buffer
      secondFrameBuffer[secondStripPos] = (secondFrameBuffer[secondStripPos] << 1) | ((secondFrameBuffer[firstStripPos] & 0x80) >> 7);
      // Finally on the bottom row; we shuffle it up ready
      secondFrameBuffer[firstStripPos] <<= 1;
#endif /* OLED_128x32 */
    }
    buttonsReleased |= getButtonState() == BUTTON_NONE;
    if (getButtonState() != BUTTON_NONE && buttonsReleased) {
      // Exit early, but have to transition whole buffer
      memcpy(screenBuffer + FRAMEBUFFER_START, secondFrameBuffer + FRAMEBUFFER_START, sizeof(screenBuffer) - FRAMEBUFFER_START);
      refresh(); // Now refresh to write out the contents to the new page
      return;
    }

#ifdef OLED_128x32
    // To keep things faster, only redraw every second line
    if (heightPos % 2 == 0) {
      refresh(); // Now refresh to write out the contents to the new page
    }
#else
    refresh(); // Now refresh to write out the contents to the new page
#endif
    vTaskDelayUntil(&startDraw, TICKS_100MS / 7);
  }
}

void OLED::setRotation(bool leftHanded) {
#ifdef OLED_FLIP
  leftHanded = !leftHanded;
#endif /* OLED_FLIP */
  if (inLeftHandedMode == leftHanded) {
    return;
  }
#ifdef OLED_SEGMENT_MAP_REVERSED
  if (!leftHanded) {
    OLED_Setup_Array[9].val = 0xA1;
  } else {
    OLED_Setup_Array[9].val = 0xA0;
  }
#else
  if (leftHanded) {
    OLED_Setup_Array[9].val = 0xA1;
  } else {
    OLED_Setup_Array[9].val = 0xA0;
  }
#endif /* OLED_SEGMENT_MAP_REVERSED */
  // send command struct again with changes
  if (leftHanded) {
    OLED_Setup_Array[5].val = 0xC8; // c1?
  } else {
    OLED_Setup_Array[5].val = 0xC0;
  }
  I2C_CLASS::writeRegistersBulk(DEVICEADDR_OLED, OLED_Setup_Array, sizeof(OLED_Setup_Array) / sizeof(OLED_Setup_Array[0]));
  osDelay(TICKS_10MS);
  inLeftHandedMode = leftHanded;

  screenBuffer[5] = inLeftHandedMode ? OLED_GRAM_START_FLIP : OLED_GRAM_START; // display is shifted by 32 in left handed
                                                                               // mode as driver ram is 128 wide
  screenBuffer[7] = inLeftHandedMode ? OLED_GRAM_END_FLIP : OLED_GRAM_END;     // End address of the ram segment we are writing to (96 wide)
  screenBuffer[9] = inLeftHandedMode ? 0xC8 : 0xC0;
  // Force a screen refresh
  const int len = FRAMEBUFFER_START + (OLED_WIDTH * (OLED_HEIGHT / 8));
  I2C_CLASS::Transmit(DEVICEADDR_OLED, screenBuffer, len);
  osDelay(TICKS_10MS);
  checkDisplayBufferChecksum();
}

void OLED::setBrightness(uint8_t contrast) {
  if (OLED_Setup_Array[15].val != contrast) {
    OLED_Setup_Array[15].val = contrast;
    I2C_CLASS::writeRegistersBulk(DEVICEADDR_OLED, &OLED_Setup_Array[14], 2);
  }
}

void OLED::setInverseDisplay(bool inverse) {
  uint8_t normalInverseCmd = inverse ? 0xA7 : 0xA6;
  if (OLED_Setup_Array[21].val != normalInverseCmd) {
    OLED_Setup_Array[21].val = normalInverseCmd;
    I2C_CLASS::I2C_RegisterWrite(DEVICEADDR_OLED, 0x80, normalInverseCmd);
  }
}

// print a string to the current cursor location, len chars MAX
void OLED::print(const char *const str, FontStyle fontStyle, uint8_t len, const uint8_t soft_x_limit) {
  const uint8_t *next = reinterpret_cast(str);
  if (next[0] == 0x01) {
    fontStyle = FontStyle::LARGE;
    next++;
  }
  while (next[0] && len--) {
    uint16_t index;
    if (next[0] <= 0xF0) {
      index = next[0];
      next++;
    } else {
      if (!next[1]) {
        return;
      }
      index = (next[0] - 0xF0) * 0xFF - 15 + next[1];
      next += 2;
    }
    drawChar(index, fontStyle, soft_x_limit);
  }
}

/**
 * Prints a static string message designed to use the whole screen, starting
 * from the top-left corner.
 *
 * If the message starts with a newline (`\\x01`), the string starting from
 * after the newline is printed in the large font. Otherwise, the message
 * is printed in the small font.
 *
 * @param string The string message to be printed
 */
void OLED::printWholeScreen(const char *string) {
  setCursor(0, 0);
  if (string[0] == '\x01') {
    // Empty first line means that this uses large font (for CJK).
    OLED::print(string + 1, FontStyle::LARGE);
  } else {
    OLED::print(string, FontStyle::SMALL);
  }
}

// Print *F or *C - in font style of Small, Large (by default) or Extra based on input arg
void OLED::printSymbolDeg(const FontStyle fontStyle) {
  switch (fontStyle) {
  case FontStyle::EXTRAS:
    // Picks *F or *C in ExtraFontChars[] from Font.h
    OLED::drawSymbol(getSettingValue(SettingsOptions::TemperatureInF) ? 0 : 1);
    break;
  case FontStyle::LARGE:
    OLED::print(getSettingValue(SettingsOptions::TemperatureInF) ? LargeSymbolDegF : LargeSymbolDegC, fontStyle);
    break;
  case FontStyle::SMALL:
  default:
    OLED::print(getSettingValue(SettingsOptions::TemperatureInF) ? SmallSymbolDegF : SmallSymbolDegC, fontStyle);
    break;
  }
}

inline void stripLeaderZeros(char *buffer, uint8_t places) {
  // Removing the leading zero's by swapping them to SymbolSpace
  // Stop 1 short so that we dont blank entire number if its zero
  for (int i = 0; i < (places - 1); i++) {
    if (buffer[i] == 2) {
      buffer[i] = LargeSymbolSpace[0];
    } else {
      return;
    }
  }
}

void OLED::drawHex(uint32_t x, FontStyle fontStyle, uint8_t digits) {
  // print number to hex
  for (uint_fast8_t i = 0; i < digits; i++) {
    uint16_t value = (x >> (4 * (7 - i))) & 0b1111;
    drawChar(value + 2, fontStyle, 0);
  }
}

// maximum places is 5
void OLED::printNumber(uint16_t number, uint8_t places, FontStyle fontStyle, bool noLeaderZeros) {
  char buffer[7] = {0};

  if (places >= 5) {
    buffer[5] = 2 + number % 10;
    number /= 10;
  }
  if (places > 4) {
    buffer[4] = 2 + number % 10;
    number /= 10;
  }

  if (places > 3) {
    buffer[3] = 2 + number % 10;
    number /= 10;
  }

  if (places > 2) {
    buffer[2] = 2 + number % 10;
    number /= 10;
  }

  if (places > 1) {
    buffer[1] = 2 + number % 10;
    number /= 10;
  }

  buffer[0] = 2 + number % 10;
  if (noLeaderZeros) {
    stripLeaderZeros(buffer, places);
  }
  print(buffer, fontStyle);
}

void OLED::debugNumber(int32_t val, FontStyle fontStyle) {
  if (abs(val) > 99999) {
    OLED::print(LargeSymbolSpace, fontStyle); // out of bounds
    return;
  }
  if (val >= 0) {
    OLED::print(LargeSymbolSpace, fontStyle);
    OLED::printNumber(val, 5, fontStyle);
  } else {
    OLED::print(LargeSymbolMinus, fontStyle);
    OLED::printNumber(-val, 5, fontStyle);
  }
}

void OLED::drawSymbol(uint8_t symbolID) {
  // draw a symbol to the current cursor location
  drawChar(symbolID, FontStyle::EXTRAS, 0);
}

// Draw an area, but y must be aligned on 0/8 offset
void OLED::drawArea(int16_t x, int8_t y, uint8_t width, uint8_t height, const uint8_t *ptr) {
  // Splat this from x->x+width in two strides
  if (x <= -width) {
    return; // cutoffleft
  }
  if (x > OLED_WIDTH) {
    return; // cutoff right
  }

  uint8_t visibleStart = 0;
  uint8_t visibleEnd   = width;

  // trimming to draw partials
  if (x < 0) {
    visibleStart -= x; // subtract negative value == add absolute value
  }
  if (x + width > OLED_WIDTH) {
    visibleEnd = OLED_WIDTH - x;
  }
  uint8_t rowsDrawn = 0;
  while (height > 0) {
    for (uint8_t xx = visibleStart; xx < visibleEnd; xx++) {
      stripPointers[(y / 8) + rowsDrawn][x + xx] = ptr[xx + (rowsDrawn * width)];
    }
    height -= 8;
    rowsDrawn++;
  }
}

// Draw an area, but y must be aligned on 0/8 offset
// For data which has octets swapped in a 16-bit word.
void OLED::drawAreaSwapped(int16_t x, int8_t y, uint8_t width, uint8_t height, const uint8_t *ptr) {
  // Splat this from x->x+width in two strides
  if (x <= -width) {
    return; // cutoffleft
  }
  if (x > OLED_WIDTH) {
    return; // cutoff right
  }

  uint8_t visibleStart = 0;
  uint8_t visibleEnd   = width;

  // trimming to draw partials
  if (x < 0) {
    visibleStart -= x; // subtract negative value == add absolute value
  }
  if (x + width > OLED_WIDTH) {
    visibleEnd = OLED_WIDTH - x;
  }

  uint8_t rowsDrawn = 0;
  while (height > 0) {
    for (uint8_t xx = visibleStart; xx < visibleEnd; xx += 2) {
      stripPointers[(y / 8) + rowsDrawn][x + xx]     = ptr[xx + 1 + (rowsDrawn * width)];
      stripPointers[(y / 8) + rowsDrawn][x + xx + 1] = ptr[xx + (rowsDrawn * width)];
    }
    height -= 8;
    rowsDrawn++;
  }
}

void OLED::fillArea(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t value) {
  // Splat this from x->x+wide in two strides
  if (x <= -wide) {
    return; // cutoffleft
  }
  if (x > OLED_WIDTH) {
    return; // cutoff right
  }

  uint8_t visibleStart = 0;
  uint8_t visibleEnd   = wide;

  // trimming to draw partials
  if (x < 0) {
    visibleStart -= x; // subtract negative value == add absolute value
  }
  if (x + wide > OLED_WIDTH) {
    visibleEnd = OLED_WIDTH - x;
  }

  uint8_t rowsDrawn = 0;
  while (height > 0) {
    for (uint8_t xx = visibleStart; xx < visibleEnd; xx++) {
      stripPointers[(y / 8) + rowsDrawn][x + xx] = value;
    }
    height -= 8;
    rowsDrawn++;
  }
}

void OLED::drawFilledRect(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, bool clear) {
  // Ensure coordinates are within bounds
  if (x0 >= OLED_WIDTH || y0 >= OLED_HEIGHT || x1 >= OLED_WIDTH || y1 >= OLED_HEIGHT) {
    return;
  }

  // Calculate the height in rows
  uint8_t startRow  = y0 / 8;
  uint8_t endRow    = y1 / 8;
  uint8_t startMask = 0xFF << (y0 % 8);
  uint8_t endMask   = 0xFF >> (7 - (y1 % 8));

  for (uint8_t row = startRow; row <= endRow; row++) {
    uint8_t mask = 0xFF;
    if (row == startRow) {
      mask &= startMask;
    }
    if (row == endRow) {
      mask &= endMask;
    }

    for (uint8_t x = x0; x <= x1; x++) {
      if (clear) {
        stripPointers[row][x] &= ~mask;
      } else {
        stripPointers[row][x] |= mask;
      }
    }
  }
}

void OLED::drawHeatSymbol(uint8_t state) {
  // Draw symbol 14
  // Then draw over it, the bottom 5 pixels always stay. 8 pixels above that are
  // the levels masks the symbol nicely
  state /= 31; // 0-> 8 range
  // Then we want to draw down (16-(5+state)
  uint16_t cursor_x_temp = cursor_x;
  drawSymbol(14);
  /*
       / / / / /
      / / / / /
      +---------+
      |         |
      +---------+


      <- 14 px ->
      What we are doing is aiming to clear a section of the screen, down to the base depending on how much PWM we are using.
      Larger numbers mean more heat, so we clear less of the screen.
  */
  drawFilledRect(cursor_x_temp, 0, cursor_x_temp + 12, 2 + (8 - state), true);
}

bool OLED::isInitDone() { return initDone; }


================================================
FILE: source/Core/Drivers/OLED.hpp
================================================
/*
 * OLED.hpp
 *
 *  Created on: 20Jan.,2017
 *      Author: Ben V. Brown 
 *      Designed for the SSD1307
 *      Cleared for release for TS100 2017/08/20
 */

#ifndef OLED_HPP_
#define OLED_HPP_
#include "Font.h"
#include "cmsis_os.h"
#include "configuration.h"
#include 
#include 
#include 

#ifdef __cplusplus
extern "C" {
#endif
#include "FreeRTOS.h"
#ifdef __cplusplus
}
#endif

#if defined(OLED_I2CBB2)
#include "I2CBB2.hpp"
#define I2C_CLASS I2CBB2
#elif defined(OLED_I2CBB1)
#include "I2CBB1.hpp"
#define I2C_CLASS I2CBB1
#else
#define I2C_CLASS FRToSI2C
#include "I2C_Wrapper.hpp"
#endif

#define DEVICEADDR_OLED (0x3c << 1)

#ifdef OLED_128x32

#define OLED_WIDTH           128
#define OLED_HEIGHT          32
#define OLED_GRAM_START      0x00 // Should be 0x00 when we have full width
#define OLED_GRAM_END        0x7F // Should be 0x7F when we have full width
#define OLED_GRAM_START_FLIP 0
#define OLED_GRAM_END_FLIP   0x7F

#define OLED_VCOM_LAYOUT 0x12
#define OLED_SEGMENT_MAP_REVERSED
#define OLED_DIVIDER 0xD3

#else

#define OLED_WIDTH           96
#define OLED_HEIGHT          16
#define OLED_GRAM_START      0x20
#define OLED_GRAM_END        0x7F
#define OLED_GRAM_START_FLIP 0
#define OLED_GRAM_END_FLIP   95

#define OLED_VCOM_LAYOUT 0x02
#define OLED_SEGMENT_MAP 0xA0
#define OLED_DIVIDER     0xD5

#endif /* OLED_128x32 */

#define OLED_ON  0xAF
#define OLED_OFF 0xAE

#define FRAMEBUFFER_START 17

enum class FontStyle {
  SMALL,
  LARGE,
  EXTRAS,
};

class OLED {
public:
  enum DisplayState : bool { OFF = false, ON = true };

  static void initialize(); // Startup the I2C coms (brings screen out of reset etc)
  static bool isInitDone();
  // Draw the buffer out to the LCD if any content has changed.
  static void refresh() {

    if (checkDisplayBufferChecksum()) {
      const int len = FRAMEBUFFER_START + (OLED_WIDTH * (OLED_HEIGHT / 8));
      I2C_CLASS::Transmit(DEVICEADDR_OLED, screenBuffer, len);
      // DMA tx time is ~ 20mS Ensure after calling this you delay for at least 25ms
      // or we need to goto double buffering
    }
  }

  static void setDisplayState(DisplayState state) {
    if (state != displayState) {
      displayState    = state;
      screenBuffer[1] = (state == ON) ? OLED_ON : OLED_OFF;
      // Dump the screen state change out _now_
      I2C_CLASS::Transmit(DEVICEADDR_OLED, screenBuffer, FRAMEBUFFER_START - 1);
      osDelay(TICKS_10MS);
    }
  }

  // Set the rotation for the screen
  static void setRotation(bool leftHanded);
  // Get the current rotation of the LCD
  static bool getRotation() {
#ifdef OLED_FLIP
    return !inLeftHandedMode;
#else
    return inLeftHandedMode;
#endif /* OLED_FLIP */
  }
  static void    setBrightness(uint8_t contrast);
  static void    setInverseDisplay(bool inverted);
  static int16_t getCursorX() { return cursor_x; }
  // Draw a string to the current location, with selected font; optionally - with MAX length only
  static void print(const char *string, FontStyle fontStyle, uint8_t length = 255, const uint8_t soft_x_limit = 0);
  static void printWholeScreen(const char *string);
  // Print *F or *C - in font style of Small, Large (by default) or Extra based on input arg
  static void printSymbolDeg(FontStyle fontStyle = FontStyle::LARGE);
  // Set the cursor location by pixels
  static void setCursor(int16_t x, int16_t y) {
    cursor_x = x;
    cursor_y = y;
  }
  // Draws an image to the buffer, at x offset from top to bottom (fixed height renders)
  static void drawImage(const uint8_t *buffer, uint8_t x, uint8_t width) { drawArea(x, 0, width, 16, buffer); }
  // Draws a number at the current cursor location
  static void printNumber(uint16_t number, uint8_t places, FontStyle fontStyle, bool noLeaderZeros = true);
  // Clears the buffer
  static void clearScreen() { memset(stripPointers[0], 0, OLED_WIDTH * (OLED_HEIGHT / 8)); }
  // Draws the battery level symbol
  static void drawBattery(uint8_t state) { drawSymbol(3 + (state > 10 ? 10 : state)); }
  // Draws a checkbox
  static void drawCheckbox(bool state) { drawSymbol((state) ? 16 : 17); }
  inline static void drawUnavailableIcon() { drawArea(OLED_WIDTH - OLED_HEIGHT - 2, 0, OLED_HEIGHT, OLED_HEIGHT, UnavailableIcon); }
  static void debugNumber(int32_t val, FontStyle fontStyle);
  static void drawHex(uint32_t x, FontStyle fontStyle, uint8_t digits);
  static void drawSymbol(uint8_t symbolID);                                                           // Used for drawing symbols of a predictable width
  static void drawArea(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t *ptr);        // Draw an area, but y must be aligned on 0/8 offset
  static void drawAreaSwapped(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t *ptr); // Draw an area, but y must be aligned on 0/8 offset
  static void fillArea(int16_t x, int8_t y, uint8_t wide, uint8_t height, const uint8_t value);       // Fill an area, but y must be aligned on 0/8 offset
  static void drawFilledRect(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, bool clear);
  static void drawHeatSymbol(uint8_t state);
  static void drawScrollIndicator(uint8_t p, uint8_t h); // Draws a scrolling position indicator
  static void maskScrollIndicatorOnOLED();
  static void transitionSecondaryFramebuffer(const bool forwardNavigation, const TickType_t viewEnterTime);
  static void useSecondaryFramebuffer(bool useSecondary);
  static void transitionScrollDown(const TickType_t viewEnterTime);
  static void transitionScrollUp(const TickType_t viewEnterTime);

private:
  static bool checkDisplayBufferChecksum() {
    uint32_t  hash = 0;
    const int len  = sizeof(screenBuffer);
    for (int i = 0; i < len; i++) {
      hash += (i * screenBuffer[i]);
    }

    bool result     = hash != displayChecksum;
    displayChecksum = hash;
    return result;
  }
  static void         drawChar(uint16_t charCode, FontStyle fontStyle, const uint8_t soft_x_limit); // Draw a character to the current cursor location
  static void         setFramebuffer(uint8_t *buffer);
  static uint8_t     *stripPointers[4]; // Pointers to the strips to allow for buffer having extra content
  static bool         inLeftHandedMode; // Whether the screen is in left or not (used for offsets in GRAM)
  static bool         initDone;
  static DisplayState displayState;
  static int16_t      cursor_x, cursor_y;
  static uint8_t      displayOffset;
  static uint32_t     displayChecksum;
  static uint8_t      screenBuffer[16 + (OLED_WIDTH * (OLED_HEIGHT / 8)) + 10]; // The data buffer
  static uint8_t      secondFrameBuffer[16 + OLED_WIDTH * (OLED_HEIGHT / 8) + 10];
};

#endif /* OLED_HPP_ */


================================================
FILE: source/Core/Drivers/README.md
================================================
# Drivers

Drivers are the classes used to represent physical hardware on the board in a more abstract way, that are more complex than just an IO

* OLED Display
* Accelerometers
* Button handling logic
* Tip thermo response modelling

All drivers should be written with minimal hardware assumptions, and defer hardware related logic to the BSP folder where possible

================================================
FILE: source/Core/Drivers/SC7A20.cpp
================================================
/*
 * SC7A20.cpp
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#include "LIS2DH12_defines.hpp"
#include "accelerometers_common.h"
#include 
#include 
#include 

bool SC7A20::isInImitationMode;
/*
- This little accelerometer seems to come in two forms, its "normal" setup, and then one where it imitates the LIS2DH12
- This can be detected by checking the whoami registers
*/

bool SC7A20::detect() {
  if (ACCEL_I2C_CLASS::probe(SC7A20_ADDRESS)) {
    // Read chip id to ensure its not an address collision
    uint8_t id = 0;
    if (ACCEL_I2C_CLASS::Mem_Read(SC7A20_ADDRESS, SC7A20_WHO_AMI_I, &id, 1)) {
      if (id == SC7A20_WHO_AM_I_VALUE) {
        isInImitationMode = false;
        return true;
      }
    }
  }
  if (ACCEL_I2C_CLASS::probe(SC7A20_ADDRESS2)) {
    // Read chip id to ensure its not an address collision
    uint8_t id = 0;
    if (ACCEL_I2C_CLASS::Mem_Read(SC7A20_ADDRESS2, SC7A20_WHO_AMI_I, &id, 1)) {
      if (id == SC7A20_WHO_AM_I_VALUE) {
        isInImitationMode = true;
        return true;
      }
    }
  }
  return false;
}

static const ACCEL_I2C_CLASS::I2C_REG i2c_registers[] = {
    //
    //
    {    SC7A20_CTRL_REG1, 0b01100111, 0}, // 200Hz, XYZ enabled
    {    SC7A20_CTRL_REG2, 0b00000000, 0}, // Setup filter to 0x00 ??
    {    SC7A20_CTRL_REG3, 0b00000000, 0}, // int1 off
    {    SC7A20_CTRL_REG4, 0b01001000, 0}, // Block mode off,little-endian,2G,High-pres,self test off
    {    SC7A20_CTRL_REG5, 0b00000100, 0}, // fifo off, D4D on int1
    {    SC7A20_CTRL_REG6,       0x00, 0}, // INT2 off
                                       // Basically setup the unit to run, and enable 4D orientation detection
    {     SC7A20_INT2_CFG, 0b01111110, 0}, // setup for movement detection
    {     SC7A20_INT2_THS,       0x28, 0}, //
    {SC7A20_INT2_DURATION,         64, 0}, //
    {     SC7A20_INT1_CFG, 0b01111110, 0}, //
    {     SC7A20_INT1_THS,       0x28, 0}, //
    {SC7A20_INT1_DURATION,         64, 0}

    //
};
static const ACCEL_I2C_CLASS::I2C_REG i2c_registers_alt[] = {
    {    LIS_CTRL_REG1, 0b00110111, 0}, // 200Hz XYZ
    {    LIS_CTRL_REG2, 0b00000000, 0}, //
    {    LIS_CTRL_REG3, 0b01100000, 0}, // Setup interrupt pins
    {    LIS_CTRL_REG4, 0b00001000, 0}, // Block update mode off, HR on
    {    LIS_CTRL_REG5, 0b00000010, 0}, //
    {    LIS_CTRL_REG6, 0b01100010, 0},
    // Basically setup the unit to run, and enable 4D orientation detection
    {     LIS_INT2_CFG, 0b01111110, 0}, // setup for movement detection
    {     LIS_INT2_THS,       0x28, 0}, //
    {LIS_INT2_DURATION,         64, 0}, //
    {     LIS_INT1_CFG, 0b01111110, 0}, //
    {     LIS_INT1_THS,       0x28, 0}, //
    {LIS_INT1_DURATION,         64, 0}
};

bool SC7A20::initalize() {
  // Setup acceleration readings
  // 2G range
  // bandwidth = 250Hz
  // High pass filter on (Slow compensation)
  // Turn off IRQ output pins
  // Orientation recognition in symmetrical mode
  // Hysteresis is set to ~ 16 counts
  // Theta blocking is set to 0b10
  if (isInImitationMode) {
    return ACCEL_I2C_CLASS::writeRegistersBulk(SC7A20_ADDRESS2, i2c_registers_alt, sizeof(i2c_registers_alt) / sizeof(i2c_registers_alt[0]));
  } else {
    return ACCEL_I2C_CLASS::writeRegistersBulk(SC7A20_ADDRESS, i2c_registers, sizeof(i2c_registers) / sizeof(i2c_registers[0]));
  }
}

void SC7A20::getAxisReadings(int16_t &x, int16_t &y, int16_t &z) {
  // We can tell the accelerometer to output in LE mode which makes this simple
  uint16_t sensorData[3] = {0, 0, 0};

  if (ACCEL_I2C_CLASS::Mem_Read(isInImitationMode ? SC7A20_ADDRESS2 : SC7A20_ADDRESS, isInImitationMode ? SC7A20_OUT_X_L_ALT : SC7A20_OUT_X_L, (uint8_t *)sensorData, 6) == false) {
    x = y = z = 0;
    return;
  }
  // Shift 6 to make its range ~= the other accelerometers
  x = sensorData[0];
  y = sensorData[1];
  z = sensorData[2];
}


================================================
FILE: source/Core/Drivers/SC7A20.hpp
================================================
/*
 * BMA223.hpp
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_SC7A20_HPP_
#define CORE_DRIVERS_SC7A20_HPP_
#include "BSP.h"
#include "I2C_Wrapper.hpp"
#include "SC7A20_defines.h"
#include "accelerometers_common.h"

class SC7A20 {
public:
  static bool detect();
  static bool initalize();
  // 1 = rh, 2,=lh, 8=flat
  static Orientation getOrientation() {
    uint8_t val = ((ACCEL_I2C_CLASS::I2C_RegisterRead(isInImitationMode ? SC7A20_ADDRESS2 : SC7A20_ADDRESS, SC7A20_INT2_SOURCE) >> 2) - 1);
    if (val == 1) {
#ifdef SC7_ORI_FLIP
      return Orientation::ORIENTATION_RIGHT_HAND;
#else
      return Orientation::ORIENTATION_LEFT_HAND;
#endif
    } else if (val == 4 || val == 0) {
#ifdef SC7_ORI_FLIP
      return Orientation::ORIENTATION_LEFT_HAND;
#else
      return Orientation::ORIENTATION_RIGHT_HAND;
#endif
    } else
      return Orientation::ORIENTATION_FLAT;
  }
  static void getAxisReadings(int16_t &x, int16_t &y, int16_t &z);

private:
  static bool isInImitationMode;
};

#endif /* CORE_DRIVERS_BMA223_HPP_ */


================================================
FILE: source/Core/Drivers/SC7A20_defines.h
================================================
/*
 * SC7A20_defines.h
 *
 *  Created on: 18 Sep. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_SC7A20_DEFINES_H_
#define CORE_DRIVERS_SC7A20_DEFINES_H_

#define SC7A20_ADDRESS 0x18 << 1
// Sometimes the SC7A20 turns up programmed to impersonate the LIS2DH12
#define SC7A20_ADDRESS2 (25 << 1)

#define SC7A20_WHO_AM_I_VALUE (0b00010001)
#define SC7A20_WHO_AMI_I      0x0F
#define SC7A20_CTRL_REG1      0x20
#define SC7A20_CTRL_REG2      0x21
#define SC7A20_CTRL_REG3      0x22
#define SC7A20_CTRL_REG4      0x23
#define SC7A20_CTRL_REG5      0x24
#define SC7A20_CTRL_REG6      0x25
#define SC7A20_REFERENCE      0x26
#define SC7A20_STATUS_REG     0x27
#define SC7A20_OUT_X_L        0x28
#define SC7A20_OUT_X_L_ALT    0xA8
#define SC7A20_OUT_X_H        0x29
#define SC7A20_OUT_Y_L        0x2A
#define SC7A20_OUT_Y_H        0x2B
#define SC7A20_OUT_Z_L        0x2C
#define SC7A20_OUT_Z_H        0x2D
#define SC7A20_FIFO_CTRL      0x2E
#define SC7A20_FIFO_SRC       0x2F
#define SC7A20_INT1_CFG       0x30
#define SC7A20_INT1_SOURCE    0x31
#define SC7A20_INT1_THS       0x32
#define SC7A20_INT1_DURATION  0x33
#define SC7A20_INT2_CFG       0x34
#define SC7A20_INT2_SOURCE    0x35
#define SC7A20_INT2_THS       0x36
#define SC7A20_INT2_DURATION  0x37
#define SC7A20_CLICK_CFG      0x38
#define SC7A20_CLICK_SRC      0x39
#define SC7A20_CLICK_THS      0x3A
#define SC7A20_TIME_LIMIT     0x3B
#define SC7A20_TIME_LATENCY   0x3C
#define SC7A20_TIME_WINDOW    0x3D
#define SC7A20_ACT_THS        0x3E
#define SC7A20_ACT_DURATION   0x3F

#endif /* CORE_DRIVERS_BMA223_DEFINES_H_ */


================================================
FILE: source/Core/Drivers/Si7210.cpp
================================================
/*
 * Si7210.cpp
 *
 *  Created on: 5 Oct. 2020
 *      Author: Ralim
 *
 *      This is based on the very nice sample code by Sean Farrelly (@FARLY7)
 *      Over here : https://github.com/FARLY7/si7210-driver
 *
 *      This class is licensed as MIT to match this code base
 */

#include "Si7210_defines.h"
#include "accelerometers_common.h"
#include 
#ifdef MAG_SLEEP_SUPPORT
bool Si7210::detect() { return FRToSI2C::wakePart(SI7210_ADDRESS); }

bool Si7210::init() {
  // Turn on auto increment and sanity check ID
  // Load OTP cal

  uint8_t temp;
  if (ACCEL_I2C_CLASS::Mem_Read(SI7210_ADDRESS, SI7210_REG_ID, &temp, 1)) {
    // We don't really care what model it is etc, just probing to check its probably this iC
    if (temp != 0x00 && temp != 0xFF) {
      temp = 0x00;

      /* Set device and internal driver settings */
      if (!write_reg(SI7210_CTRL1, (uint8_t)~SW_LOW4FIELD_MASK, 0)) {
        return false;
      }

      /* Disable periodic auto-wakeup by device, and tamper detect. */
      if ((!write_reg(SI7210_CTRL3, (uint8_t)~SL_TIMEENA_MASK, 0))) {
        return false;
      }

      /* Disable tamper detection by setting sw_tamper to 63 */
      if (!write_reg(SI7210_CTRL3, SL_FAST_MASK | SL_TIMEENA_MASK, 63 << 2)) {
        return false;
      }

      if (!set_high_range()) {
        return false;
      }

      /* Stop the control loop by setting stop bit */
      if (!write_reg(SI7210_POWER_CTRL, MEAS_MASK | USESTORE_MASK, STOP_MASK)) { /* WARNING: Removed USE_STORE MASK */
        return false;
      }

      /* Use a burst size of 128/4096 samples in FIR and IIR modes */
      if (!write_reg(SI7210_CTRL4, 0, DF_BURSTSIZE_128 | DF_BW_4096)) {
        return false;
      }

      /* Select field strength measurement */
      if (!write_reg(SI7210_DSPSIGSEL, 0, DSP_SIGSEL_FIELD_MASK)) {
        return false;
      }

      return true; // start_periodic_measurement();
    }
  }
  return false;
}

int16_t Si7210::read() {
  // Read the two regs
  int16_t temp = 0;
  if (!get_field_strength(&temp)) {
    temp = 0;
  }
  return temp;
}

bool Si7210::write_reg(const uint8_t reg, const uint8_t mask, const uint8_t val) {
  uint8_t temp = 0;
  if (mask) {
    if (!read_reg(reg, &temp)) {
      return false;
    }
    temp &= mask;
  }
  temp |= val;
  return ACCEL_I2C_CLASS::Mem_Write(SI7210_ADDRESS, reg, &temp, 1);
}

bool Si7210::read_reg(const uint8_t reg, uint8_t *val) { return ACCEL_I2C_CLASS::Mem_Read(SI7210_ADDRESS, reg, val, 1); }

bool Si7210::start_periodic_measurement() {
  /* Enable periodic wakeup */
  if (!write_reg(SI7210_CTRL3, (uint8_t)~SL_TIMEENA_MASK, SL_TIMEENA_MASK)) {
    return false;
  }

  /* Start measurement */
  /* Change to ~STOP_MASK with STOP_MASK */
  return write_reg(SI7210_POWER_CTRL, MEAS_MASK | USESTORE_MASK, 0);
}

bool Si7210::get_field_strength(int16_t *field) {
  *field      = 0;
  uint8_t val = 0;
  ACCEL_I2C_CLASS::wakePart(SI7210_ADDRESS);

  if (!write_reg(SI7210_POWER_CTRL, MEAS_MASK | USESTORE_MASK, STOP_MASK)) {
    return false;
  }

  /* Read most-significant byte */
  if (!read_reg(SI7210_DSPSIGM, &val)) {
    return false;
  }
  *field = (val & DSP_SIGM_DATA_MASK) << 8;

  /* Read least-significant byte of data */
  if (!read_reg(SI7210_DSPSIGL, &val)) {
    return false;
  }

  *field += val;
  *field -= 16384U;
  // field is now a +- measurement
  // In units of 0.0125 mT
  // Aka 12.5uT
  // Clear flags
  read_reg(SI7210_CTRL1, &val);
  read_reg(SI7210_CTRL2, &val);
  // Start next one

  /* Use a burst size of 128/4096 samples in FIR and IIR modes */
  write_reg(SI7210_CTRL4, 0, DF_BURSTSIZE_128 | DF_BW_4096);

  /* Selet field strength measurement */
  write_reg(SI7210_DSPSIGSEL, 0, DSP_SIGSEL_FIELD_MASK);

  /* Start measurement */
  write_reg(SI7210_POWER_CTRL, MEAS_MASK | USESTORE_MASK, ONEBURST_MASK);

  return true;
}

bool Si7210::set_high_range() {
  // To set the unit into 200mT range, no magnet temperature calibration
  // We want to copy OTP 0x27->0x2C into a0->a5
  uint8_t base_addr = 0x27; // You can change this to pick the temp calibration
  bool    worked    = true;
  uint8_t val       = 0;

  /* Load A0 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A0, 0, val);

  /* Load A1 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr + 1);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A1, 0, val);

  /* Load A2 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr + 2);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A2, 0, val);

  /* Load A3 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr + 3);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A3, 0, val);

  /* Load A4 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr + 4);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A4, 0, val);

  /* Load A5 register */
  worked &= write_reg(SI7210_OTP_ADDR, 0, base_addr + 5);
  worked &= write_reg(SI7210_OTP_CTRL, 0, OTP_READ_EN_MASK);
  worked &= read_reg(SI7210_OTP_DATA, &val);
  worked &= write_reg(SI7210_A5, 0, val);
  return worked;
}
#endif // MAG_SLEEP_SUPPORT

================================================
FILE: source/Core/Drivers/Si7210.h
================================================
/*
 * Si7210.h
 *
 *  Created on: 5 Oct. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_SI7210_H_
#define CORE_DRIVERS_SI7210_H_
#include "configuration.h"
#include 

#ifdef MAG_SLEEP_SUPPORT
class Si7210 {
public:
  // Return true if present
  static bool detect();

  static bool    init();
  static int16_t read();

private:
  static bool write_reg(const uint8_t reg, const uint8_t mask, const uint8_t val);
  static bool read_reg(const uint8_t reg, uint8_t *val);
  static bool start_periodic_measurement();
  static bool get_field_strength(int16_t *field);
  static bool set_high_range();
};
#endif // MAG_SLEEP_SUPPORT
#endif /* CORE_DRIVERS_SI7210_H_ */


================================================
FILE: source/Core/Drivers/Si7210_defines.h
================================================
/*
 * Si7210_defines.h
 *
 *  Created on: 5 Oct. 2020
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_SI7210_DEFINES_H_
#define CORE_DRIVERS_SI7210_DEFINES_H_

#define SI7210_ADDRESS (0x30 << 1)
#define SI7210_REG_ID  0xC0

/* Si7210 Register addresses */
#define SI7210_HREVID     0xC0U
#define SI7210_DSPSIGM    0xC1U
#define SI7210_DSPSIGL    0xC2U
#define SI7210_DSPSIGSEL  0xC3U
#define SI7210_POWER_CTRL 0xC4U
#define SI7210_ARAUTOINC  0xC5U
#define SI7210_CTRL1      0xC6U
#define SI7210_CTRL2      0xC7U
#define SI7210_SLTIME     0xC8U
#define SI7210_CTRL3      0xC9U
#define SI7210_A0         0xCAU
#define SI7210_A1         0xCBU
#define SI7210_A2         0xCCU
#define SI7210_CTRL4      0xCDU
#define SI7210_A3         0xCEU
#define SI7210_A4         0xCFU
#define SI7210_A5         0xD0U
#define SI7210_OTP_ADDR   0xE1U
#define SI7210_OTP_DATA   0xE2U
#define SI7210_OTP_CTRL   0xE3U
#define SI7210_TM_FG      0xE4U

/* Si7210 Register bit masks */
#define CHIP_ID_MASK        0xF0U
#define REV_ID_MASK         0x0FU
#define DSP_SIGSEL_MASK     0x07U
#define MEAS_MASK           0x80U
#define USESTORE_MASK       0x08U
#define ONEBURST_MASK       0x04U
#define STOP_MASK           0x02U
#define SLEEP_MASK          0x01U
#define ARAUTOINC_MASK      0x01U
#define SW_LOW4FIELD_MASK   0x80U
#define SW_OP_MASK          0x7FU
#define SW_FIELDPOLSEL_MASK 0xC0U
#define SW_HYST_MASK        0x3FU
#define SW_TAMPER_MASK      0xFCU
#define SL_FAST_MASK        0x02U
#define SL_TIMEENA_MASK     0x01U
#define DF_BURSTSIZE_MASK   0xE0U
#define DF_BW_MASK          0x1EU
#define DF_IIR_MASK         0x01U
#define OTP_READ_EN_MASK    0x02U
#define OTP_BUSY_MASK       0x01U
#define TM_FG_MASK          0x03U

#define DSP_SIGM_DATA_FLAG    0x80U
#define DSP_SIGM_DATA_MASK    0x7FU
#define DSP_SIGSEL_TEMP_MASK  0x01U
#define DSP_SIGSEL_FIELD_MASK 0x04U

/* Burst sizes */
#define DF_BW_1          0x0U << 1
#define DF_BW_2          0x1U << 1
#define DF_BW_4          0x2U << 1
#define DF_BW_8          0x3U << 1
#define DF_BW_16         0x4U << 1
#define DF_BW_32         0x5U << 1
#define DF_BW_64         0x6U << 1
#define DF_BW_128        0x7U << 1
#define DF_BW_256        0x8U << 1
#define DF_BW_512        0x9U << 1
#define DF_BW_1024       0xAU << 1
#define DF_BW_2048       0xBU << 1
#define DF_BW_4096       0xCU << 1
#define DF_BURSTSIZE_1   0x0U << 5
#define DF_BURSTSIZE_2   0x1U << 5
#define DF_BURSTSIZE_4   0x2U << 5
#define DF_BURSTSIZE_8   0x3U << 5
#define DF_BURSTSIZE_16  0x4U << 5
#define DF_BURSTSIZE_32  0x5U << 5
#define DF_BURSTSIZE_64  0x6U << 5
#define DF_BURSTSIZE_128 0x7U << 5

#endif /* CORE_DRIVERS_SI7210_DEFINES_H_ */


================================================
FILE: source/Core/Drivers/TipThermoModel.cpp
================================================
/*
 * TipThermoModel.cpp
 *
 *  Created on: 7 Oct 2019
 *      Author: ralim
 */

#include "TipThermoModel.h"
#include "BSP.h"
#include "Settings.h"
#include "Types.h"
#include "Utils.hpp"
#include "configuration.h"
#include "main.hpp"
#include "power.hpp"
/*
 * The hardware is laid out  as a non-inverting op-amp
 * There is a pullup of 39k(TS100) from the +ve input to 3.9V (1M pulup on TS100)
 *
 * The simplest case to model this, is to ignore the pullup resistors influence, and assume that its influence is mostly constant
 * -> Tip resistance *does* change with temp, but this should be much less than the rest of the system.
 *
 * When a thermocouple is equal temperature at both sides (hot and cold junction), then the output should be 0uV
 * Therefore, by measuring the uV when both are equal, the measured reading is the offset value.
 * This is a mix of the pull-up resistor, combined with tip manufacturing differences.
 *
 * All of the thermocouple readings are based on this expired patent
 * - > https://patents.google.com/patent/US6087631A/en
 *
 * This was bought to my attention by 
 */
volatile uint32_t lastuv = 0;
uint32_t          TipThermoModel::convertTipRawADCTouV(uint16_t rawADC, bool skipCalOffset) {
  // This takes the raw ADC samples, converts these to uV
  // Then divides this down by the gain to convert to the uV on the input to the op-amp (A+B terminals)
  // Then remove the calibration value that is stored as a tip offset
  uint32_t vddRailmVX10 = ADC_VDD_MV * 10; // The vreg is +-2%, but we have no higher accuracy available
  // 4096 * 8 readings for full scale
  // Convert the input ADC reading back into mV times 10 format.
  uint32_t rawInputmVX10 = (rawADC * vddRailmVX10) / (ADC_MAX_READING);

  uint32_t valueuV = rawInputmVX10 * 100; // shift into uV
  // Now to divide this down by the gain
  valueuV /= OP_AMP_GAIN_STAGE;

  if (getSettingValue(SettingsOptions::CalibrationOffset) && skipCalOffset == false) {
    // Remove uV tipOffset
    if (valueuV > getSettingValue(SettingsOptions::CalibrationOffset)) {
      valueuV -= getSettingValue(SettingsOptions::CalibrationOffset);
    } else {
      valueuV = 0;
    }
  }
  lastuv = valueuV;
  return valueuV;
}

TemperatureType_t TipThermoModel::convertTipRawADCToDegC(uint16_t rawADC) { return convertuVToDegC(convertTipRawADCTouV(rawADC)); }
TemperatureType_t TipThermoModel::convertTipRawADCToDegF(uint16_t rawADC) { return convertuVToDegF(convertTipRawADCTouV(rawADC)); }

TemperatureType_t TipThermoModel::convertuVToDegF(uint32_t tipuVDelta) { return convertCtoF(convertuVToDegC(tipuVDelta)); }

TemperatureType_t TipThermoModel::convertCtoF(TemperatureType_t degC) {
  //(Y °C × 9/5) + 32 =Y°F
  return (32 + ((degC * 9) / 5));
}

TemperatureType_t TipThermoModel::convertFtoC(TemperatureType_t degF) {
  //(Y°F − 32) × 5/9 = Y°C
  if (degF < 32) {
    return 0;
  }
  return ((degF - 32) * 5) / 9;
}
TemperatureType_t TipThermoModel::getTipInC(bool sampleNow) {
  TemperatureType_t currentTipTempInC = TipThermoModel::convertTipRawADCToDegC(getTipRawTemp(sampleNow));
  currentTipTempInC += getHandleTemperature(sampleNow) / 10; // Add handle offset

  if (currentTipTempInC < 0) {
    return 0;
  }
  return currentTipTempInC;
}

TemperatureType_t TipThermoModel::getTipInF(bool sampleNow) {
  TemperatureType_t currentTipTempInF = getTipInC(sampleNow);
  currentTipTempInF                   = convertCtoF(currentTipTempInF);
  return currentTipTempInF;
}

TemperatureType_t TipThermoModel::getTipMaxInC() {
#ifdef CUSTOM_MAX_TEMP_C
  return getCustomTipMaxInC();
#else
  TemperatureType_t maximumTipTemp = TipThermoModel::convertTipRawADCToDegC(ADC_MAX_READING - 1);
  maximumTipTemp += getHandleTemperature(0) / 10; // Add handle offset
  return maximumTipTemp - 1;
#endif
}


================================================
FILE: source/Core/Drivers/TipThermoModel.h
================================================
/*
 * TipThermoModel.h
 *
 *  Created on: 7 Oct 2019
 *      Author: ralim
 */

#include "BSP.h"
#include "Types.h"
#include "stdint.h"
#ifndef SRC_TIPTHERMOMODEL_H_
#define SRC_TIPTHERMOMODEL_H_
class TipThermoModel {
public:
  // These are the main two functions
  static TemperatureType_t getTipInC(bool sampleNow = false);
  static TemperatureType_t getTipInF(bool sampleNow = false);

  // Calculates the maximum temperature can can be read by the ADC range
  static TemperatureType_t getTipMaxInC();

  static TemperatureType_t convertTipRawADCToDegC(uint16_t rawADC);
  static TemperatureType_t convertTipRawADCToDegF(uint16_t rawADC);
  // Returns the uV of the tip reading before the op-amp compensating for pullups
  static uint32_t          convertTipRawADCTouV(uint16_t rawADC, bool skipCalOffset = false);
  static TemperatureType_t convertCtoF(TemperatureType_t degC);
  static TemperatureType_t convertFtoC(TemperatureType_t degF);

private:
  static TemperatureType_t convertuVToDegC(uint32_t tipuVDelta);
  static TemperatureType_t convertuVToDegF(uint32_t tipuVDelta);
};

#endif /* SRC_TIPTHERMOMODEL_H_ */


================================================
FILE: source/Core/Drivers/USBPD.cpp
================================================
#include "USBPD.h"
#include "configuration.h"
#ifdef POW_PD
#include "BSP_PD.h"
#include "FreeRTOS.h"
#include "Settings.h"
#include "fusb302b.h"
#include "main.hpp"
#include "pd.h"
#include "policy_engine.h"

#ifndef USB_PD_VMAX
#error Max PD Voltage must be defined
#endif

void ms_delay(uint32_t delayms) {
  // Convert ms -> ticks
  TickType_t ticks = delayms / portTICK_PERIOD_MS;

  vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
}
uint32_t get_ms_timestamp() {
  // Convert ticks -> ms
  return xTaskGetTickCount() * portTICK_PERIOD_MS;
}
bool         pdbs_dpm_evaluate_capability(const pd_msg *capabilities, pd_msg *request);
void         pdbs_dpm_get_sink_capability(pd_msg *cap, const bool isPD3);
bool         EPREvaluateCapabilityFunc(const epr_pd_msg *capabilities, pd_msg *request);
FUSB302      fusb((0x22 << 1), fusb_read_buf, fusb_write_buf, ms_delay); // Create FUSB driver
PolicyEngine pe(fusb, get_ms_timestamp, ms_delay, pdbs_dpm_get_sink_capability, pdbs_dpm_evaluate_capability, EPREvaluateCapabilityFunc, USB_PD_EPR_WATTAGE);
int          USBPowerDelivery::detectionState = 0;
bool         haveSeenCapabilityOffer          = false;
uint16_t     requested_voltage_mv             = 0;

/* The current draw when the output is disabled */
#define DPM_MIN_CURRENT PD_MA2PDI(100)

// Start processing
bool USBPowerDelivery::start() {
  if (fusbPresent() && fusb.fusb_setup()) {
    setupFUSBIRQ();
    return true;
  }
  return false;
}
void    USBPowerDelivery::IRQOccured() { pe.IRQOccured(); }
bool    USBPowerDelivery::negotiationHasWorked() { return pe.pdHasNegotiated(); }
uint8_t USBPowerDelivery::getStateNumber() { return pe.currentStateCode(true); }
void    USBPowerDelivery::step() {
  while (pe.thread()) {
  }
}

void USBPowerDelivery::PPSTimerCallback() { pe.TimersCallback(); }
bool USBPowerDelivery::negotiationInProgress() {
  if (USBPowerDelivery::negotiationComplete()) {
    return false;
  }
  if (haveSeenCapabilityOffer) {
    return false;
  }
  return true;
}
bool USBPowerDelivery::negotiationComplete() {
  if (!fusbPresent()) {
    return true;
  }
  return pe.setupCompleteOrTimedOut(getSettingValue(SettingsOptions::PDNegTimeout));
}
bool USBPowerDelivery::fusbPresent() {
  if (detectionState == 0) {
    if (fusb.fusb_read_id()) {
      detectionState = 1;
    }
  }
  return detectionState == 1;
}

bool USBPowerDelivery::isVBUSConnected() {
#if NEEDS_VBUS_PROBE == 1
  static uint8_t state = 0;
  if (state) {
    return state == 1;
  }
  // Dont run if we havent negotiated
  if (!negotiationComplete()) {
    return true;
  }
  if (fusb.isVBUSConnected()) {
    state = 1;
    return true;
  } else {
    state = 2;
    return false;
  }
#else
  return false;
#endif
}
uint32_t  lastCapabilities[11];
uint32_t *USBPowerDelivery::getLastSeenCapabilities() { return lastCapabilities; }

#ifdef POW_EPR
static unsigned int sqrtI(unsigned long sqrtArg) {
  unsigned int  answer, x;
  unsigned long temp;
  if (sqrtArg == 0) {
    return 0; // undefined result
  }
  if (sqrtArg == 1) {
    return 1; // identity
  }
  answer = 0;                           // integer square root
  for (x = 0x8000; x > 0; x = x >> 1) { // 16 bit shift
    answer |= x;                        // possible bit in root
    temp = answer * answer;             //
    if (temp == sqrtArg) {
      break; // exact, found it
    }
    if (temp > sqrtArg) {
      answer ^= x; // too large, reverse bit
    }
  }
  return answer; // approximate root
}
#endif

// parseCapabilitiesArray returns true if a valid capability was found
// caps is the array of capabilities objects
// best* are output references
bool parseCapabilitiesArray(const uint8_t numCaps, uint8_t *bestIndex, uint16_t *bestVoltage, uint16_t *bestCurrent, bool *bestIsPPS, bool *bestIsAVS) {
  // Walk the given capabilities array; and select the best option
  // Given assumption of fixed tip resistance; this can be simplified to highest voltage selection
  *bestIndex   = 0xFF; // Mark unselected
  *bestVoltage = 5000; // Default 5V

  // Fudge of 0.5 ohms to round up a little to account for us always having off periods in PWM
  uint8_t     tipResistance = getTipResistanceX10();
  usbpdMode_t pd_mode       = (usbpdMode_t)getSettingValue(SettingsOptions::USBPDMode);
  if (pd_mode == usbpdMode_t::DEFAULT) {
    tipResistance += 5;
  }
#ifdef MODEL_HAS_DCDC
  // If this device has step down DC/DC inductor to smooth out current spikes
  // We can instead ignore resistance and go for max voltage we can accept; and rely on the DC/DC regulation to keep under current limit
  tipResistance = 255; // (Push to 25.5 ohms to effectively disable this check)
#endif

  for (uint8_t i = 0; i < numCaps; i++) {
    if ((lastCapabilities[i] & PD_PDO_TYPE) == PD_PDO_TYPE_FIXED) {
      // This is a fixed PDO entry
      // Evaluate if it can produve sufficient current based on the TIP_RESISTANCE (ohms*10)
      // V=I*R -> V/I => minimum resistance, if our tip resistance is >= this then we can use this supply

      int voltage_mv             = PD_PDV2MV(PD_PDO_SRC_FIXED_VOLTAGE_GET(lastCapabilities[i])); // voltage in mV units
      int current_a_x100         = PD_PDO_SRC_FIXED_CURRENT_GET(lastCapabilities[i]);            // current in 10mA units
      int min_resistance_ohmsx10 = voltage_mv / current_a_x100;
      if (voltage_mv > 0) {
        if (voltage_mv <= (USB_PD_VMAX * 1000)) {
          if (voltage_mv <= 20000 || (pd_mode != usbpdMode_t::NO_DYNAMIC)) {
            if (min_resistance_ohmsx10 <= tipResistance) {
              // This is a valid power source we can select as
              if (voltage_mv > *bestVoltage) {

                // Higher voltage and valid, select this instead
                *bestIndex   = i;
                *bestVoltage = voltage_mv;
                *bestCurrent = current_a_x100;
                *bestIsPPS   = false;
                *bestIsAVS   = false;
              }
            }
          }
        }
      }
    } else if (((lastCapabilities[i] & PD_PDO_TYPE) == PD_PDO_TYPE_AUGMENTED) && (pd_mode != usbpdMode_t::NO_DYNAMIC)) {
      bool sourceIsEPRCapable = lastCapabilities[0] & PD_PDO_SRC_FIXED_EPR_CAPABLE;
      bool isPPS              = false;
      bool isAVS              = false;
      if (sourceIsEPRCapable) {
        isPPS = (lastCapabilities[i] & PD_APDO_TYPE) == PD_APDO_TYPE_PPS;
        isAVS = (lastCapabilities[i] & PD_APDO_TYPE) == PD_APDO_TYPE_AVS;
      } else {
        isPPS = true; // Assume PPS if no EPR support
      }
      if (isPPS) {
        // If this is a PPS slot, calculate the max voltage in the PPS range that can we be used and maintain
        uint16_t max_voltage = PD_PAV2MV(PD_APDO_PPS_MAX_VOLTAGE_GET(lastCapabilities[i]));
        // uint16_t min_voltage = PD_PAV2MV(PD_APDO_PPS_MIN_VOLTAGE_GET(lastCapabilities[i]));
        uint16_t max_current = PD_PAI2CA(PD_APDO_PPS_CURRENT_GET(lastCapabilities[i])); // max current in 10mA units
        // Using the current and tip resistance, calculate the ideal max voltage
        // if this is range, then we will work with this voltage
        // if this is not in range; then max_voltage can be safely selected
        int ideal_voltage_mv = (tipResistance * max_current);
        if (ideal_voltage_mv > max_voltage) {
          ideal_voltage_mv = max_voltage; // constrain to what this PDO offers
        }
        if (ideal_voltage_mv > 20000) {
          ideal_voltage_mv = 20000; // Limit to 20V as some advertise 21 but are not stable at 21
        }
        if (ideal_voltage_mv > (USB_PD_VMAX * 1000)) {
          ideal_voltage_mv = (USB_PD_VMAX * 1000); // constrain to model max voltage safe to select
        }
        if (ideal_voltage_mv > *bestVoltage) {
          *bestIndex   = i;
          *bestVoltage = ideal_voltage_mv;
          *bestCurrent = max_current;
          *bestIsPPS   = true;
          *bestIsAVS   = false;
        }
      }
#ifdef POW_EPR
      else if (isAVS) {
        uint16_t max_voltage = PD_PAV2MV(PD_APDO_AVS_MAX_VOLTAGE_GET(lastCapabilities[i]));
        uint8_t  max_wattage = PD_APDO_AVS_MAX_POWER_GET(lastCapabilities[i]);
        tipResistance        = getTipResistanceX10(); // Dont use fudge factor for EPR

        // W = v^2/tip_resistance => Wattage*tip_resistance == Max_voltage^2
        auto ideal_max_voltage = sqrtI((max_wattage * tipResistance) / 10) * 1000;
        if (ideal_max_voltage > (USB_PD_VMAX * 1000)) {
          ideal_max_voltage = (USB_PD_VMAX * 1000); // constrain to model max voltage safe to select
        }
        if (ideal_max_voltage > (max_voltage)) {
          ideal_max_voltage = (max_voltage); // constrain to model max voltage safe to select
        }
        auto operating_current = (ideal_max_voltage / tipResistance); // Current in centiamps

        if (ideal_max_voltage > *bestVoltage) {
          *bestIndex   = i;
          *bestVoltage = ideal_max_voltage;
          *bestCurrent = operating_current;
          *bestIsAVS   = true;
          *bestIsPPS   = false;
        }
      }
#endif
    }
  }
  // Now that the best index is known, set the current values
  return *bestIndex != 0xFF; // have we selected one
}

bool EPREvaluateCapabilityFunc(const epr_pd_msg *capabilities, pd_msg *request) {
#ifdef POW_EPR
  // Select any EPR slots up to USB_PD_VMAX
  memset(lastCapabilities, 0, sizeof(lastCapabilities));
  memcpy(lastCapabilities, capabilities->obj, sizeof(lastCapabilities));
  // PDO slots 1-7 shall be the standard PDO's
  // PDO slots 8-11 shall be the >20V slots
  uint8_t  numobj           = 11;
  uint8_t  bestIndex        = 0xFF;
  uint16_t bestIndexVoltage = 0;
  uint16_t bestIndexCurrent = 0;
  bool     bestIsPPS        = false;
  bool     bestIsAVS        = false;

  if (parseCapabilitiesArray(numobj, &bestIndex, &bestIndexVoltage, &bestIndexCurrent, &bestIsPPS, &bestIsAVS)) {
    /* We got what we wanted, so build a request for that */
    request->hdr    = PD_MSGTYPE_EPR_REQUEST | PD_NUMOBJ(2);
    request->obj[1] = lastCapabilities[bestIndex]; // Copy PDO into slot 2

    if (bestIsAVS) {
      request->obj[0] = PD_RDO_PROG_CURRENT_SET(PD_CA2PAI(bestIndexCurrent)) | PD_RDO_PROG_VOLTAGE_SET(PD_MV2APS(bestIndexVoltage));
    } else if (bestIsPPS) {
      request->obj[0] = PD_RDO_PROG_CURRENT_SET(PD_CA2PAI(bestIndexCurrent)) | PD_RDO_PROG_VOLTAGE_SET(PD_MV2PRV(bestIndexVoltage));
    } else {
      request->obj[0] = PD_RDO_FV_MAX_CURRENT_SET(bestIndexCurrent) | PD_RDO_FV_CURRENT_SET(bestIndexCurrent);
    }
    request->obj[0] |= PD_RDO_EPR_CAPABLE;
    request->obj[0] |= PD_RDO_NO_USB_SUSPEND;
    request->obj[0] |= PD_RDO_OBJPOS_SET(bestIndex + 1);

    // We dont do usb
    // request->obj[0] |= PD_RDO_USB_COMMS;

    /* Update requested voltage */
    requested_voltage_mv    = bestIndexVoltage;
    powerSupplyWattageLimit = bestIndexVoltage * bestIndexCurrent / 100 / 1000; // Set watts for limit from PSU limit

  } else {
    /* Nothing matched (or no configuration), so get 5 V at low current */
    request->hdr    = PD_MSGTYPE_EPR_REQUEST | PD_NUMOBJ(2);
    request->obj[1] = lastCapabilities[0];
    request->obj[0] = PD_RDO_FV_MAX_CURRENT_SET(100) | PD_RDO_FV_CURRENT_SET(100) | PD_RDO_NO_USB_SUSPEND | PD_RDO_OBJPOS_SET(1);
    // We dont do usb
    // request->obj[0] |= PD_RDO_USB_COMMS;

    /* Update requested voltage */
    requested_voltage_mv = 5000;
  }
  return true;
#endif
  return false;
}

bool pdbs_dpm_evaluate_capability(const pd_msg *capabilities, pd_msg *request) {
  memset(lastCapabilities, 0, sizeof(lastCapabilities));
  memcpy(lastCapabilities, capabilities->obj, sizeof(uint32_t) * 7);
  haveSeenCapabilityOffer = true;
  /* Get the number of PDOs */
  uint8_t numobj = PD_NUMOBJ_GET(capabilities);

  /* Make sure we have configuration */
  /* Look at the PDOs to see if one matches our desires */
  // Look against USB_PD_Desired_Levels to select in order of preference
  uint8_t  bestIndex        = 0xFF;
  uint16_t bestIndexVoltage = 0;
  uint16_t bestIndexCurrent = 0;
  bool     bestIsPPS        = false;
  bool     bestIsAVS        = false;

  if (parseCapabilitiesArray(numobj, &bestIndex, &bestIndexVoltage, &bestIndexCurrent, &bestIsPPS, &bestIsAVS)) {
    /* We got what we wanted, so build a request for that */
    request->hdr = PD_MSGTYPE_REQUEST | PD_NUMOBJ(1);
    if (bestIsPPS) {
      request->obj[0] = PD_RDO_PROG_CURRENT_SET(PD_CA2PAI(bestIndexCurrent)) | PD_RDO_PROG_VOLTAGE_SET(PD_MV2PRV(bestIndexVoltage)) | PD_RDO_NO_USB_SUSPEND | PD_RDO_OBJPOS_SET(bestIndex + 1);
    } else {
      request->obj[0] = PD_RDO_FV_MAX_CURRENT_SET(bestIndexCurrent) | PD_RDO_FV_CURRENT_SET(bestIndexCurrent) | PD_RDO_NO_USB_SUSPEND | PD_RDO_OBJPOS_SET(bestIndex + 1);
    }
    // We dont do usb
    // request->obj[0] |= PD_RDO_USB_COMMS;
#ifdef POW_EPR
    request->obj[0] |= PD_RDO_EPR_CAPABLE;
#endif

    /* Update requested voltage */
    requested_voltage_mv    = bestIndexVoltage;
    powerSupplyWattageLimit = bestIndexVoltage * bestIndexCurrent / 100 / 1000; // Set watts for limit from PSU limit

  } else {
    /* Nothing matched (or no configuration), so get 5 V at low current */
    request->hdr    = PD_MSGTYPE_REQUEST | PD_NUMOBJ(1);
    request->obj[0] = PD_RDO_FV_MAX_CURRENT_SET(100) | PD_RDO_FV_CURRENT_SET(100) | PD_RDO_NO_USB_SUSPEND | PD_RDO_OBJPOS_SET(1);
    // We dont do usb
    // request->obj[0] |= PD_RDO_USB_COMMS;

    /* Update requested voltage */
    requested_voltage_mv = 5000;
  }
  // Even if we didnt match, we return true as we would still like to handshake on 5V at the minimum
  return true;
}

void add_v_record(pd_msg *cap, uint16_t voltage_mv, int numobj) {

  uint16_t current = (voltage_mv) / getTipResistanceX10(); // In centi-amps

  /* Add a PDO for the desired power. */
  cap->obj[numobj] = PD_PDO_TYPE_FIXED | PD_PDO_SNK_FIXED_VOLTAGE_SET(PD_MV2PDV(voltage_mv)) | PD_PDO_SNK_FIXED_CURRENT_SET(current);
}
void pdbs_dpm_get_sink_capability(pd_msg *cap, const bool isPD3) {
  /* Keep track of how many PDOs we've added */
  int numobj = 0;

  /* If we have no configuration or want something other than 5 V, add a PDO
   * for vSafe5V */
  /* Minimum current, 5 V, and higher capability. */
  cap->obj[numobj++] = PD_PDO_TYPE_FIXED | PD_PDO_SNK_FIXED_VOLTAGE_SET(PD_MV2PDV(5000)) | PD_PDO_SNK_FIXED_CURRENT_SET(DPM_MIN_CURRENT);
  // Voltages must be in order of lowest -> highest
#if USB_PD_VMAX >= 20
  add_v_record(cap, 9000, numobj);
  numobj++;
  add_v_record(cap, 15000, numobj);
  numobj++;
  add_v_record(cap, 20000, numobj);
  numobj++;
#elif USB_PD_VMAX >= 15
  add_v_record(cap, 9000, numobj);
  numobj++;
  add_v_record(cap, 12000, numobj);
  numobj++;
  add_v_record(cap, 15000, numobj);
  numobj++;
#elif USB_PD_VMAX >= 12
  add_v_record(cap, 9000, numobj);
  numobj++;
  add_v_record(cap, 12000, numobj);
  numobj++;
#elif USB_PD_VMAX >= 9
  add_v_record(cap, 9000, numobj);
  numobj++;
#endif

  /* Set the USB communications capable flag. */
  cap->obj[0] |= PD_PDO_SNK_FIXED_USB_COMMS;

  /* Set the Sink_Capabilities message header */
  cap->hdr = PD_DATAROLE_UFP | PD_SPECREV_3_0 | PD_POWERROLE_SINK | PD_MSGTYPE_SINK_CAPABILITIES | PD_NUMOBJ(numobj);
}

#endif


================================================
FILE: source/Core/Drivers/USBPD.h
================================================

#ifndef DRIVERS_USBPD_H_
#define DRIVERS_USBPD_H_
#include "configuration.h"
#include 
#include 

#ifdef __cplusplus
#ifdef POW_PD
class USBPowerDelivery {
public:
  static bool      start();                   // Start the PD stack
  static bool      negotiationComplete();     // Has negotiation completed to a voltage > 5v
  static bool      negotiationInProgress();   // Is negotiation ongoing
  static bool      fusbPresent();             // Is the FUSB302 present on the bus
  static void      PPSTimerCallback();        // PPS Timer
  static void      IRQOccured();              // Thread callback that an irq occured
  static void      step();                    // Iterate the step machine
  static bool      negotiationHasWorked();    // Has PD negotiation worked (are we in a PD contract)
  static uint8_t   getStateNumber();          // Debugging - Get the internal state number
  static bool      isVBUSConnected();         // Is the VBus pin connected on the FUSB302
  static uint32_t *getLastSeenCapabilities(); // returns pointer to the last seen capabilities from the powersource
private:
  //
  static int detectionState;
};
#endif

#endif
#endif

================================================
FILE: source/Core/Drivers/Utils.cpp
================================================
/*
 * Utils.cpp
 *
 *  Created on: 28 Apr 2021
 *      Author: Ralim
 */

#include "BSP_Power.h"
#include "Settings.h"
#include "configuration.h"
#include 

int32_t Utils::InterpolateLookupTable(const int32_t *lookupTable, const int noItems, const int32_t value) {
  for (int i = 1; i < (noItems - 1); i++) {
    // If current tip temp is less than current lookup, then this current lookup is the higher point to interpolate
    if (value < lookupTable[i * 2]) {
      return LinearInterpolate(lookupTable[(i - 1) * 2], lookupTable[((i - 1) * 2) + 1], lookupTable[i * 2], lookupTable[(i * 2) + 1], value);
    }
  }
  return LinearInterpolate(lookupTable[(noItems - 2) * 2], lookupTable[((noItems - 2) * 2) + 1], lookupTable[(noItems - 1) * 2], lookupTable[((noItems - 1) * 2) + 1], value);
}

int32_t Utils::LinearInterpolate(int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t x) { return y1 + (((((x - x1) * 1000) / (x2 - x1)) * (y2 - y1))) / 1000; }

uint16_t Utils::RequiredCurrentForTipAtVoltage(uint16_t voltageX10) {
  uint8_t tipResistancex10 = getTipResistanceX10();
  if (getSettingValue(SettingsOptions::USBPDMode) == usbpdMode_t::DEFAULT) {
    tipResistancex10 += 5;
  }
#ifdef MODEL_HAS_DCDC
  // If this device has step down DC/DC inductor to smooth out current spikes
  // We can instead ignore resistance and go for max voltage we can accept; and rely on the DC/DC regulation to keep under current limit
  tipResistancex10 = 255; // (Push to 25.5 ohms to effectively disable this check)
#endif
  // V/R = I
  uint16_t currentX10 = (voltageX10 * 10) / tipResistancex10;
  return currentX10;
}


================================================
FILE: source/Core/Drivers/Utils.hpp
================================================
/*
 * Utils.hpp
 *
 *  Created on: 28 Apr 2021
 *      Author: Ralim
 */

#ifndef CORE_DRIVERS_UTILS_HPP_
#define CORE_DRIVERS_UTILS_HPP_
#include 
class Utils {
public:
  static int32_t InterpolateLookupTable(const int32_t *lookupTable, const int noItems, const int32_t value);
  static int32_t LinearInterpolate(int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t x);

  // Return the required current in X10 for the specified voltage
  static uint16_t RequiredCurrentForTipAtVoltage(uint16_t voltageX10);

};

#endif /* CORE_DRIVERS_UTILS_HPP_ */


================================================
FILE: source/Core/Drivers/WS2812.h
================================================
/*
 * WS2812.h
 *
 *  Created on: 2 May 2021
 *      Author: Ralim
 */
#include "Pins.h"
#include "Setup.h"
#include 
#include 
#include 

#ifndef CORE_DRIVERS_WS2812_H_
#define CORE_DRIVERS_WS2812_H_

#ifndef WS2812_LED_CHANNEL_COUNT
#define WS2812_LED_CHANNEL_COUNT 3
#endif

#define WS2812_RAW_BYTES_PER_LED (WS2812_LED_CHANNEL_COUNT * 8)

template  class WS2812 {
private:
  uint8_t leds_colors[WS2812_LED_CHANNEL_COUNT * LED_COUNT];

public:
  void led_update() {
    __disable_irq();
    // Bitbang it out as our cpu irq latency is too high
    for (unsigned int i = 0; i < sizeof(leds_colors); i++) {
      // Shove out MSB first
      for (int x = 0; x < 8; x++) {
        ((GPIO_TypeDef *)WS2812_GPIO_Port)->BSRR = WS2812_Pin;
        if ((leds_colors[i] & (1 << (7 - x))) == (1 << (7 - x))) {
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
        } else {

          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
          __asm__ __volatile__("nop");
        }
        ((GPIO_TypeDef *)WS2812_GPIO_Port)->BSRR = (uint32_t)WS2812_Pin << 16u;
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
        __asm__ __volatile__("nop");
      }
    }
    __enable_irq();
  }

  void init(void) { memset(leds_colors, 0, sizeof(leds_colors)); }

  void led_set_color(size_t index, uint8_t r, uint8_t g, uint8_t b) {
    leds_colors[index * WS2812_LED_CHANNEL_COUNT + 0] = g;
    leds_colors[index * WS2812_LED_CHANNEL_COUNT + 1] = r;
    leds_colors[index * WS2812_LED_CHANNEL_COUNT + 2] = b;
  }

  void led_set_color_all(uint8_t r, uint8_t g, uint8_t b) {
    for (int index = 0; index < LED_COUNT; index++) {
      leds_colors[index * WS2812_LED_CHANNEL_COUNT + 0] = g;
      leds_colors[index * WS2812_LED_CHANNEL_COUNT + 1] = r;
      leds_colors[index * WS2812_LED_CHANNEL_COUNT + 2] = b;
    }
  }
};

#endif /* CORE_DRIVERS_WS2812_H_ */


================================================
FILE: source/Core/Drivers/WS2812B.h
================================================
/*
 * WS2812B.h
 *
 *  Created on: 9 July 2023
 *      Author: Doegox
 *      Currently for RISC-V architecture only
 *      Based on WS2812.h by Ralim for STM32
 */
#include "Pins.h"
#include "Setup.h"
#include 
#include 
#include 

#ifndef CORE_DRIVERS_WS2812B_H_
#define CORE_DRIVERS_WS2812B_H_

#ifndef WS2812B_LED_CHANNEL_COUNT
#define WS2812B_LED_CHANNEL_COUNT 3
#endif

#define WS2812B_RAW_BYTES_PER_LED (WS2812B_LED_CHANNEL_COUNT * 8)

template  class WS2812B {
private:
  uint8_t leds_colors[WS2812B_LED_CHANNEL_COUNT * LED_COUNT];

public:
  void led_update() {
    __disable_irq();
    // Bitbang it out as our cpu irq latency is too high
    for (unsigned int i = 0; i < sizeof(leds_colors); i++) {
      // Shove out MSB first
      for (int x = 0; x < 8; x++) {
        if ((leds_colors[i] & (1 << (7 - x))) == (1 << (7 - x))) {
          gpio_write(LED_PIN, 1);
          for (int k = 0; k < 27; k++) {
            __ASM volatile("nop");
          }
          gpio_write(LED_PIN, 0);
          for (int k = 0; k < 10; k++) {
            __ASM volatile("nop");
          }
        } else {
          gpio_write(LED_PIN, 1);
          for (int k = 0; k < 10; k++) {
            __ASM volatile("nop");
          }
          gpio_write(LED_PIN, 0);
          for (int k = 0; k < 27; k++) {
            __ASM volatile("nop");
          }
        }
      }
    }
    __enable_irq();
  }

  void init(void) { memset(leds_colors, 0, sizeof(leds_colors));
    gpio_set_mode(LED_PIN, GPIO_OUTPUT_MODE);
    gpio_write(LED_PIN, 1);
    led_set_color(0, 0, 0xFF, 0); // green
    led_update();
}

  void led_set_color(size_t index, uint8_t r, uint8_t g, uint8_t b) {
    leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 0] = g;
    leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 1] = r;
    leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 2] = b;
  }

  void led_set_color_all(uint8_t r, uint8_t g, uint8_t b) {
    for (int index = 0; index < LED_COUNT; index++) {
      leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 0] = g;
      leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 1] = r;
      leds_colors[index * WS2812B_LED_CHANNEL_COUNT + 2] = b;
    }
  }
};

#endif /* CORE_DRIVERS_WS2812B_H_ */


================================================
FILE: source/Core/Drivers/accelerometers_common.h
================================================
#ifndef CORE_DRIVERS_ACCELEROMTERS_COMMON_H_
#define CORE_DRIVERS_ACCELEROMTERS_COMMON_H_
#include "configuration.h"
#if defined(ACCEL_I2CBB2)
#include "I2CBB2.hpp"
#define ACCEL_I2C_CLASS I2CBB2
#elif defined(ACCEL_I2CBB1)
#include "I2CBB1.hpp"
#define ACCEL_I2C_CLASS I2CBB1
#else
#include "I2C_Wrapper.hpp"
#define ACCEL_I2C_CLASS FRToSI2C
#endif

#endif

================================================
FILE: source/Core/Inc/FreeRTOSHooks.h
================================================
/*
 * FreeRTOSHooks.h
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#ifndef INC_FREERTOSHOOKS_H_
#define INC_FREERTOSHOOKS_H_

#include "FreeRTOS.h"
#include "cmsis_os.h"

#ifdef __cplusplus
extern "C" {
#endif

// RToS
void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize);
void vApplicationIdleHook(void);
#ifdef __cplusplus
}
#endif

#endif /* INC_FREERTOSHOOKS_H_ */


================================================
FILE: source/Core/Inc/QC3.h
================================================
/*
 * QC3.h
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#ifndef INC_QC3_H_
#define INC_QC3_H_
#include "stdint.h"
#ifdef __cplusplus
extern "C" {
#endif
void seekQC(int16_t Vx10, uint16_t divisor);
void startQC(uint16_t divisor); // Tries to negotiate QC for highest voltage, must be run after
bool hasQCNegotiated();         // Returns true if a QC negotiation worked (we are using QC)
#ifdef __cplusplus
}
#endif

#endif /* INC_QC3_H_ */


================================================
FILE: source/Core/Inc/ScrollMessage.hpp
================================================
#ifndef SCROLL_MESSAGE_HPP_
#define SCROLL_MESSAGE_HPP_

#include "portmacro.h"
#include 
/**
 * A helper for showing a full-screen scrolling message.
 */

/**
 * Draw and update the scroll message if needed.
 *
 * This function does not call `OLED::refresh()`. If this function
 * returns `true`, the caller shall call `OLED::refresh()` to draw the
 * modified framebuffer to the OLED screen.
 *
 * @param message The null-terminated message string. This must be the
 * same string as the previous call, unless this `ScrollMessage` instance
 * is in its initial state or `reset()` has been called.
 * @param currentTick The current tick as returned by `xTaskGetTickCount()` offset to 0 at start of scrolling.
 */
void drawScrollingText(const char *message, TickType_t currentTickOffset);

#endif /* SCROLL_MESSAGE_HPP_ */


================================================
FILE: source/Core/Inc/Settings.h
================================================
/*
 * Settings.h
 *
 *  Created on: 29 Sep 2016
 *      Author: Ralim
 *
 *      Houses the system settings and allows saving / restoring from flash
 */

#include "configuration.h"

#ifndef CORE_SETTINGS_H_
#define CORE_SETTINGS_H_
#include 
#include 
#ifdef MODEL_Pinecilv2
// Required settings reset for PR #1916
#define SETTINGSVERSION (0x55AB) // This number is frozen, do not edit
#else
#define SETTINGSVERSION (0x55AA) // This number is frozen, do not edit
#endif

enum SettingsOptions {
  SolderingTemp                  = 0,  // current set point for the iron
  SleepTemp                      = 1,  // temp to drop to in sleep
  SleepTime                      = 2,  // minutes timeout to sleep
  MinDCVoltageCells              = 3,  // The voltage we cut out at for under voltage when powered by DC jack
  MinVoltageCells                = 4,  // Minimum allowed voltage per cell <3S - 3.0V (30)> <4S - 2.4V (24)> <...> (Minimum recommended 2.7V)
  QCIdealVoltage                 = 5,  // Desired QC3.0 voltage (9,12,20V)
  OrientationMode                = 6,  // Selects between Auto,Right and left handed layouts
  Sensitivity                    = 7,  // Sensitivity of accelerometer (5 bits)
  AnimationLoop                  = 8,  // Animation loop switch
  AnimationSpeed                 = 9,  // Animation speed (in miliseconds)
  AutoStartMode                  = 10, // Should the unit automatically jump straight into soldering mode when power is applied
  ShutdownTime                   = 11, // Time until unit shuts down if left alone
  CoolingTempBlink               = 12, // Should the temperature blink on the cool down screen until its <50C
  DetailedIDLE                   = 13, // Detailed idle screen
  DetailedSoldering              = 14, // Detailed soldering screens
  TemperatureInF                 = 15, // Should the temp be in F or C (true is F)
  DescriptionScrollSpeed         = 16, // Description scroll speed
  LockingMode                    = 17, // Store the locking mode
  KeepAwakePulse                 = 18, // Keep Awake pulse power in 0.1 watts (10 = 1Watt)
  KeepAwakePulseWait             = 19, // Time between Keep Awake pulses in 2500 ms = 2.5 s increments
  KeepAwakePulseDuration         = 20, // Duration of the Keep Awake pusle in 250 ms increments
  VoltageDiv                     = 21, // Voltage divisor factor
  BoostTemp                      = 22, // Boost mode set point for the iron
  CalibrationOffset              = 23, // This stores the temperature offset for this tip in the iron.
  PowerLimit                     = 24, // Maximum power iron allowed to output
  ReverseButtonTempChangeEnabled = 25, // Change the plus and minus button assigment
  TempChangeLongStep             = 26, // Temperature-change-increment on long button press
  TempChangeShortStep            = 27, // Temperature-change-increment on short button press
  HallEffectSensitivity          = 28, // Operating mode of the hall effect sensor
  AccelMissingWarningCounter     = 29, // Counter of how many times we have warned we cannot detect the accelerometer
  PDMissingWarningCounter        = 30, // Counter of how many times we have warned we cannot detect the pd interface
  UILanguage                     = 31, // Selected UI Language code, null-terminated *only if* the length is less than 8 chars
  PDNegTimeout                   = 32, // PD timeout in 100ms steps
  OLEDInversion                  = 33, // Invert the colours on the display
  OLEDBrightness                 = 34, // Brightness for the OLED display
  LOGOTime                       = 35, // Duration the logo will be displayed for
  CalibrateCJC                   = 36, // Toggle calibrate CJC at next boot
  BluetoothLE                    = 37, // Toggle BLE if present
  USBPDMode                      = 38, // Toggle PPS & EPR
  ProfilePhases                  = 39, // Number of profile mode phases
  ProfilePreheatTemp             = 40, // Temperature to preheat to before the first phase
  ProfilePreheatSpeed            = 41, // Maximum allowed preheat speed in degrees per second
  ProfilePhase1Temp              = 42, // Temperature to target for the end of phase 1
  ProfilePhase1Duration          = 43, // Target duration for phase 1
  ProfilePhase2Temp              = 44, // Temperature to target for the end of phase 2
  ProfilePhase2Duration          = 45, // Target duration for phase 2
  ProfilePhase3Temp              = 46, // Temperature to target for the end of phase 3
  ProfilePhase3Duration          = 47, // Target duration for phase 3
  ProfilePhase4Temp              = 48, // Temperature to target for the end of phase 4
  ProfilePhase4Duration          = 49, // Target duration for phase 4
  ProfilePhase5Temp              = 50, // Temperature to target for the end of phase 5
  ProfilePhase5Duration          = 51, // Target duration for phase 5
  ProfileCooldownSpeed           = 52, // Maximum allowed cooldown speed in degrees per second
  HallEffectSleepTime            = 53, // Seconds (/5) timeout to sleep when hall effect over threshold
  SolderingTipType               = 54, // Selecting the type of soldering tip fitted
  ReverseButtonSettings          = 55, // Change the A and B button assigment in Settings menu
  //
  SettingsOptionsLength = 56, // End marker
};

typedef enum {
  OFF       = 0, // Off (disabled)
  SLOW      = 1, //
  MEDIUM    = 2, //
  FAST      = 3, //
  MAX_VALUE = 4  //
} settingOffSpeed_t;

typedef enum {
  NO     = 0, // Disabled
  SOLDER = 1, // Gain default soldering temp (Soldering Mode)
  SLEEP  = 2, // Gain default sleeping temp (Idle/Standby Mode)
  ZERO   = 3, // Power on only (No heat Mode)
} autoStartMode_t;

typedef enum {
  RIGHT = 0, // Right-hand screen orientation
  LEFT  = 1, // Left-hand screen orientation
  AUTO  = 2, // Automatic screen orientation based on accel.data if presented
} orientationMode_t;

typedef enum {
  SKIP     = 0, // Skip boot logo
  ONETIME  = 5, // Show boot logo once (if animated) and stall until a button toggled
  INFINITY = 6, // Show boot logo on repeat (if animated) until a button toggled
} logoMode_t;

typedef enum {
  DEFAULT    = 1, // PPS + EPR + more power request through increasing resistance by 0.5 Ohm to compensate power loss over cable/PCB/etc.
  SAFE       = 2, // PPS + EPR, without requesting more power
  NO_DYNAMIC = 0, // PPS + EPR disabled, fixed PDO only
} usbpdMode_t;

typedef enum {
  DISABLED = 0, // Locking buttons is disabled
  BOOST    = 1, // Locking buttons for Boost mode only
  FULL     = 2, // Locking buttons for Boost mode AND for Soldering mode
} lockingMode_t;

/* Selection of the soldering tip
 * Some devices allow multiple types of tips to be fitted, this allows selecting them or overriding the logic
 * The first type will be the default (gets value of 0)
 */
#ifdef TIP_TYPE_SUPPORT
typedef enum {
#ifdef AUTO_TIP_SELECTION
  TIP_TYPE_AUTO, // If the hardware supports automatic detection
#endif

#ifdef TIPTYPE_T12
  T12_8_OHM,   // TS100 style tips or Hakko T12 tips with adaptors
  T12_6_2_OHM, // Short Tips manufactured by Pine64
  T12_4_OHM,   // Longer tip but low resistance for PTS200
#endif
  // #ifdef TIPTYPE_TS80
  //   TS80_4_5_OHM, // TS80(P) default tips
  // // We do not know of other tuning tips (?yet?)
  // #endif
  // #ifdef TIPTYPE_JBC
  //   JBC_210_2_5_OHM, // Small JBC tips as used in the S60/S60P
  // #endif
  TIP_TYPE_MAX, // Max value marker
} tipType_t;
#else
typedef enum {
  TIP_TYPE_AUTO = 0, // value for the default case
  TIP_TYPE_MAX  = 0, // marker for settings when not supported
} tipType_t;
#endif /* TIP_TYPE_SUPPORT */

// returns the resistance matching the selected tip type or 0 for auto and when not supported
uint8_t getUserSelectedTipResistance();

// Settings wide operations
void saveSettings();
bool loadSettings();
void resetSettings();

// Settings access

uint16_t getSettingValue(const enum SettingsOptions option);
// Returns true if setting is now on the last value (next iteration will wrap)
void nextSettingValue(const enum SettingsOptions option);
void prevSettingValue(const enum SettingsOptions option);
bool isLastSettingValue(const enum SettingsOptions option);
// For setting values to settings
void setSettingValue(const enum SettingsOptions option, const uint16_t newValue);

// Special access helpers, to reduce logic duplication
uint8_t     lookupVoltageLevel();
uint16_t    lookupHallEffectThreshold();
#ifdef TIP_TYPE_SUPPORT
const char *lookupTipName(); // Get the name string for the current soldering tip
#endif /* TIP_TYPE_SUPPORT */
#endif                       /* SETTINGS_H_ */


================================================
FILE: source/Core/Inc/Translation.h
================================================
/*
 * Translation.h
 *
 *  Created on: 31Aug.,2017
 *      Author: Ben V. Brown
 */

#ifndef TRANSLATION_H_
#define TRANSLATION_H_

#include 
#include 

extern const bool HasFahrenheit;

extern const char *SmallSymbolPlus;
extern const char *LargeSymbolPlus;
extern const char *SmallSymbolMinus;
extern const char *LargeSymbolMinus;
extern const char *SmallSymbolSpace;
extern const char *LargeSymbolSpace;
extern const char *SmallSymbolAmps;
extern const char *LargeSymbolAmps;
extern const char *SmallSymbolDot;
extern const char *LargeSymbolDot;
extern const char *SmallSymbolSlash;
extern const char *SmallSymbolColon;
extern const char *SmallSymbolDegC;
extern const char *LargeSymbolDegC;
extern const char *SmallSymbolDegF;
extern const char *LargeSymbolDegF;
extern const char *LargeSymbolMinutes;
extern const char *SmallSymbolMinutes;
extern const char *LargeSymbolSeconds;
extern const char *SmallSymbolSeconds;
extern const char *LargeSymbolWatts;
extern const char *SmallSymbolWatts;
extern const char *LargeSymbolVolts;
extern const char *SmallSymbolVolts;
extern const char *LargeSymbolDC;
extern const char *SmallSymbolDC;
extern const char *LargeSymbolCellCount;
extern const char *SmallSymbolCellCount;
//
extern const char *SmallSymbolVersionNumber;
extern const char *SmallSymbolPDDebug;
extern const char *SmallSymbolState;
extern const char *SmallSymbolNoVBus;
extern const char *SmallSymbolVBus;

extern const char *LargeSymbolSleep;

extern const char *DebugMenu[];
extern const char *AccelTypeNames[];
extern const char *PowerSourceNames[];

enum class SettingsItemIndex : uint8_t {
  DCInCutoff,
  MinVolCell,
  QCMaxVoltage,
  PDNegTimeout,
  USBPDMode,
  BoostTemperature,
  AutoStart,
  TempChangeShortStep,
  TempChangeLongStep,
  LockingMode,
  ProfilePhases,
  ProfilePreheatTemp,
  ProfilePreheatSpeed,
  ProfilePhase1Temp,
  ProfilePhase1Duration,
  ProfilePhase2Temp,
  ProfilePhase2Duration,
  ProfilePhase3Temp,
  ProfilePhase3Duration,
  ProfilePhase4Temp,
  ProfilePhase4Duration,
  ProfilePhase5Temp,
  ProfilePhase5Duration,
  ProfileCooldownSpeed,
  MotionSensitivity,
  SleepTemperature,
  SleepTimeout,
  ShutdownTimeout,
  HallEffSensitivity,
  HallEffSleepTimeout,
  TemperatureUnit,
  DisplayRotation,
  CooldownBlink,
  ScrollingSpeed,
  ReverseButtonTempChange,
  ReverseButtonSettings,
  AnimSpeed,
  AnimLoop,
  Brightness,
  ColourInversion,
  LOGOTime,
  AdvancedIdle,
  AdvancedSoldering,
  BluetoothLE,
  PowerLimit,
  CalibrateCJC,
  VoltageCalibration,
  PowerPulsePower,
  PowerPulseWait,
  PowerPulseDuration,
  SettingsReset,
  LanguageSwitch,
  SolderingTipType,
  NUM_ITEMS,
};

struct TranslationIndexTable {
  uint16_t CalibrationDone;
  uint16_t ResetOKMessage;
  uint16_t SettingsResetMessage;
  uint16_t NoAccelerometerMessage;
  uint16_t NoPowerDeliveryMessage;
  uint16_t LockingKeysString;
  uint16_t UnlockingKeysString;
  uint16_t WarningKeysLockedString;
  uint16_t WarningThermalRunaway;
  uint16_t WarningTipShorted;

  uint16_t SettingsCalibrationWarning;
  uint16_t CJCCalibrating;
  uint16_t SettingsResetWarning;
  uint16_t UVLOWarningString;
  uint16_t UndervoltageString;
  uint16_t InputVoltageString;
  uint16_t ProfilePreheatString;
  uint16_t ProfileCooldownString;

  uint16_t SleepingAdvancedString;
  uint16_t SleepingTipAdvancedString;
  uint16_t DeviceFailedValidationWarning;
  uint16_t TooHotToStartProfileWarning;

  uint16_t SettingRightChar;
  uint16_t SettingLeftChar;
  uint16_t SettingAutoChar;
  uint16_t SettingSlowChar;
  uint16_t SettingMediumChar;
  uint16_t SettingFastChar;
  uint16_t SettingStartSolderingChar;
  uint16_t SettingStartSleepChar;
  uint16_t SettingStartSleepOffChar;
  uint16_t SettingLockBoostChar;
  uint16_t SettingLockFullChar;
  uint16_t USBPDModeDefault;
  uint16_t USBPDModeNoDynamic;
  uint16_t USBPDModeSafe;
  uint16_t TipTypeAuto;
  uint16_t TipTypeT12Long;
  uint16_t TipTypeT12Short;
  uint16_t TipTypeT12PTS;
  uint16_t TipTypeTS80;
  uint16_t TipTypeJBCC210;

  uint16_t SettingsDescriptions[static_cast(SettingsItemIndex::NUM_ITEMS)];
  uint16_t SettingsShortNames[static_cast(SettingsItemIndex::NUM_ITEMS)];
  uint16_t SettingsMenuEntriesDescriptions[5]; // unused
  uint16_t SettingsMenuEntries[5];
};

extern const TranslationIndexTable *Tr;

extern const char *TranslationStrings;

struct TranslationData {
  TranslationIndexTable indices;
  // Translation strings follows the translation index table.
  // C++ does not support flexible array member as in C, so we use a 1-element
  // array as a placeholder.
  char strings[1];
};

struct FontSection {
  const uint8_t *font12_start_ptr;
  const uint8_t *font06_start_ptr;
  uint16_t       font12_decompressed_size;
  uint16_t       font06_decompressed_size;
  const uint8_t *font12_compressed_source; // Pointer to compressed data or null
  const uint8_t *font06_compressed_source; // Pointer to compressed data or null
};

extern const FontSection FontSectionInfo;

constexpr uint8_t settings_item_index(const SettingsItemIndex i) { return static_cast(i); }
// Use a constexpr function for type-checking.
#define SETTINGS_DESC(i) (settings_item_index(i) + 1)

const char *translatedString(uint16_t index);

void prepareTranslations();
void settings_displayLanguageSwitch(void);
bool settings_showLanguageSwitch(void);
void settings_setLanguageSwitch(void);
bool isLastLanguageOption(void);

#endif /* TRANSLATION_H_ */


================================================
FILE: source/Core/Inc/Translation_multi.h
================================================
#ifndef TRANSLATION_MULTI_H_
#define TRANSLATION_MULTI_H_

#include "Translation.h"
#include 
// The compressed translation data will be decompressed to this buffer. These
// data may include:
//  - TranslationData (translation index table and translation strings)
//  - Font table(s)
// The translation index table consists of uint16_t (half words) which has a
// 2-byte alignment. Therefore, the declaration of this buffer must include
// the alignment specifier `alignas(TranslationData)` to satisfy its alignment.
// TranslationData must always be decompressed to the start of this buffer.
extern uint8_t        translation_data_out_buffer[];
extern const uint16_t translation_data_out_buffer_size;

struct LanguageMeta {
  uint16_t       uniqueID;
  const uint8_t *translation_data;
  uint16_t       translation_size : 15;
  bool           translation_is_compressed : 1;
};

extern const LanguageMeta LanguageMetas[];
extern const uint8_t      LanguageCount;

#endif /* TRANSLATION_MULTI_H_ */


================================================
FILE: source/Core/Inc/Types.h
================================================
#ifndef TYPES_H_
#define TYPES_H_
#include 

// Used for temperature represented in C or x10C.
//

typedef int32_t TemperatureType_t;

#endif


================================================
FILE: source/Core/Inc/expMovingAverage.h
================================================
/*
 * expMovingAverage.h
 *
 *  Created on: 8 Oct 2019
 *      Author: ralim
 */

#ifndef INC_EXPMOVINGAVERAGE_H_
#define INC_EXPMOVINGAVERAGE_H_

template  struct expMovingAverage {
  int32_t sum;
  void    update(T const val) { sum = ((val * weighting) + (sum * (256 - weighting))) / 256; }

  T average() const { return sum; }
};

#endif /* INC_EXPMOVINGAVERAGE_H_ */


================================================
FILE: source/Core/Inc/history.hpp
================================================
/*
 * history.hpp
 *
 *  Created on: 28 Oct, 2018
 *     Authors: Ben V. Brown, David Hilton
 */

#ifndef HISTORY_HPP_
#define HISTORY_HPP_

#include 

// max size = 127
template  struct history {
  static const uint8_t size = SIZE;
  T                    buf[size];
  uint32_t             sum;
  uint8_t              loc;

  void update(T const val) {
    // step backwards so i+1 is the previous value.

    sum -= buf[loc];
    sum += val;
    buf[loc] = val;
    loc      = (loc + 1) % size;
  }

  T operator[](uint8_t i) const {
    // 0 = newest, size-1 = oldest.
    i = (i + loc) % size;
    return buf[i];
  }

  T average() const { return sum / size; }
};

#endif /* HISTORY_HPP_ */


================================================
FILE: source/Core/Inc/main.hpp
================================================
#ifndef __MAIN_H
#define __MAIN_H
#include "OLED.hpp"
#include "Setup.h"
#include "Types.h"
#include 
extern volatile TemperatureType_t currentTempTargetDegC;
extern bool                       settingsWereReset;
extern bool                       usb_pd_available;
#ifdef __cplusplus
extern "C" {
#endif

void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName);

// Threads
void                startGUITask(void const *argument);
void                startPIDTask(void const *argument);
void                startMOVTask(void const *argument);
void                startPOWTask(void const *argument);
extern TaskHandle_t pidTaskNotification;
extern int32_t      powerSupplyWattageLimit;
extern uint8_t      accelInit;
extern TickType_t   lastMovementTime;
#ifdef __cplusplus
}
// Accelerometer type
enum class AccelType {
  Scanning  = 0,
  None      = 1,
  MMA       = 2,
  LIS       = 3,
  BMA       = 4,
  MSA       = 5,
  SC7       = 6,
  GPIO      = 7,
  LIS_CLONE = 8,
};
extern AccelType DetectedAccelerometerVersion;

#endif
#endif /* __MAIN_H */


================================================
FILE: source/Core/Inc/power.hpp
================================================
/*
 * Power.hpp
 *
 *  Created on: 28 Oct, 2018
 *     Authors: Ben V. Brown, David Hilton (David's Idea)
 */

#include "BSP.h"
#include "configuration.h"
#include "expMovingAverage.h"
#include "stdint.h"
#include 
#ifndef POWER_HPP_
#define POWER_HPP_

// thermal mass = 1690 milliJ/*C for my tip.
//  ->  Wattsx10*Seconds to raise Temp from room temp to +100*C, divided by 100*C.
// we divide mass by 20 to let the I term dominate near the set point.
//  This is necessary because of the temp noise and thermal lag in the system.
// Once we have feed-forward temp estimation we should be able to better tune this.

const uint8_t                                        wattHistoryFilter = 24; // I term look back weighting
extern expMovingAverage x10WattHistory;

uint32_t availableW10(uint8_t sample);
void     setTipX10Watts(int32_t mw);
uint8_t  X10WattsToPWM(int32_t milliWatts, uint8_t sample = 0);
#endif /* POWER_HPP_ */


================================================
FILE: source/Core/Inc/settingsGUI.hpp
================================================
/*
 * settingsGUI.h
 *
 *  Created on: 3Sep.,2017
 *      Author: Ben V. Brown
 */

#ifndef GUI_HPP_
#define GUI_HPP_
#include "BSP.h"
#include "Buttons.hpp"
#include "FreeRTOS.h"
#include "Settings.h"
#include "Translation.h"

#define PRESS_ACCEL_STEP         (TICKS_100MS / 3)
#define PRESS_ACCEL_INTERVAL_MIN TICKS_100MS
#define PRESS_ACCEL_INTERVAL_MAX (TICKS_100MS * 3)

// GUI holds the menu structure and all its methods for the menu itself

// Declarations for all the methods for the settings menu (at end of this file)

// Struct for holding the function pointers and descriptions
typedef struct {
  // The settings description index, please use the `SETTINGS_DESC` macro with
  // the `SettingsItemIndex` enum. Use 0 for no description.
  uint8_t description;
  void (*const incrementHandler)(void);
  void (*const draw)(void); // Must not be nullptr, as that marks end of menu
  bool (*const isVisible)(void);
  // If this is set, we will automatically use the settings increment handler instead, set >= num settings to disable
  SettingsOptions   autoSettingOption;
  SettingsItemIndex shortDescriptionIndex;
  uint8_t           shortDescriptionSize;
} menuitem;

void                   enterSettingsMenu();
extern const menuitem  rootSettingsMenu[];
extern const menuitem *subSettingsMenus[];

#endif /* GUI_HPP_ */


================================================
FILE: source/Core/Inc/stm32f1xx_hal_conf.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_hal_conf.h
 * @brief   HAL configuration file.
 ******************************************************************************
 * @attention
 *
 * 
© COPYRIGHT(c) 2017 STMicroelectronics

 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H
#define __STM32F1xx_HAL_CONF_H

#ifdef __cplusplus
extern "C" {
#endif

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/* ########################## Module Selection ############################## */
/**
 * @brief This is the list of modules to be used in the HAL driver
 */

#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED   */
/*#define HAL_CAN_MODULE_ENABLED   */
/*#define HAL_CEC_MODULE_ENABLED   */
/*#define HAL_CORTEX_MODULE_ENABLED   */
/*#define HAL_CRC_MODULE_ENABLED   */
/*#define HAL_DAC_MODULE_ENABLED   */
#define HAL_DMA_MODULE_ENABLED
/*#define HAL_ETH_MODULE_ENABLED   */
/*#define HAL_FLASH_MODULE_ENABLED   */
#define HAL_GPIO_MODULE_ENABLED
/* #define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED   */
/*#define HAL_IRDA_MODULE_ENABLED   */
#define HAL_IWDG_MODULE_ENABLED
/*#define HAL_NOR_MODULE_ENABLED   */
/*#define HAL_NAND_MODULE_ENABLED   */
/*#define HAL_PCCARD_MODULE_ENABLED   */
/*#define HAL_PCD_MODULE_ENABLED   */
/*#define HAL_HCD_MODULE_ENABLED   */
/*#define HAL_PWR_MODULE_ENABLED   */
/*#define HAL_RCC_MODULE_ENABLED   */
/*#define HAL_RTC_MODULE_ENABLED   */
/*#define HAL_SD_MODULE_ENABLED   */
/*#define HAL_MMC_MODULE_ENABLED   */
/*#define HAL_SDRAM_MODULE_ENABLED   */
/*#define HAL_SMARTCARD_MODULE_ENABLED   */
/*#define HAL_SPI_MODULE_ENABLED   */
/*#define HAL_SRAM_MODULE_ENABLED   */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_UART_MODULE_ENABLED   */
/*#define HAL_USART_MODULE_ENABLED   */
/*#define HAL_WWDG_MODULE_ENABLED   */

#define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED

/* ########################## Oscillator Values adaptation ####################*/
/**
 * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
 *        This value is used by the RCC HAL module to compute the system frequency
 *        (when HSE is used as system clock source, directly or through the PLL).
 */
#if !defined(HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif                                /* HSE_VALUE */

#if !defined(HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#endif                                      /* HSE_STARTUP_TIMEOUT */

/**
 * @brief Internal High Speed oscillator (HSI) value.
 *        This value is used by the RCC HAL module to compute the system frequency
 *        (when HSI is used as system clock source, directly or through the PLL).
 */
#if !defined(HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif                                /* HSI_VALUE */

/**
 * @brief Internal Low Speed oscillator (LSI) value.
 */
#if !defined(LSI_VALUE)
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */   /*!< Value of the Internal Low Speed oscillator in Hz    \
                              The real value may vary depending on the variations \
                              in voltage and temperature. */

/**
 * @brief External Low Speed oscillator (LSE) value.
 *        This value is used by the UART, RTC HAL module to compute the system frequency
 */
#if !defined(LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#endif                              /* LSE_VALUE */

#if !defined(LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif                                       /* LSE_STARTUP_TIMEOUT */

/* Tip: To avoid modifying this file each time you need to use different HSE,
   ===  you can define the HSE value in your toolchain compiler preprocessor. */

/* ########################### System Configuration ######################### */
/**
 * @brief This is the HAL system configuration section
 */
#define VDD_VALUE         ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0)    /*!< tick interrupt priority (lowest by default)  */
#define USE_RTOS          0
#define PREFETCH_ENABLE   1

/* ########################## Assert Selection ############################## */
/**
 * @brief Uncomment the line below to expanse the "assert_param" macro in the
 *        HAL drivers code
 */
/* #define USE_FULL_ASSERT    1 */

/* ################## Ethernet peripheral configuration ##################### */

/* Section 1 : Ethernet peripheral configuration */

/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0

/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive               */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
#define ETH_RXBUFNB     ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
#define ETH_TXBUFNB     ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */

/* Section 2: PHY configuration section */

/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)

#define PHY_READ_TO  ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)

/* Section 3: Common PHY Registers */

#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register   */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register    */

#define PHY_RESET                   ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK                ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M         ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M         ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M          ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s  */
#define PHY_HALFDUPLEX_10M          ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s  */
#define PHY_AUTONEGOTIATION         ((uint16_t)0x1000) /*!< Enable auto-negotiation function     */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function    */
#define PHY_POWERDOWN               ((uint16_t)0x0800) /*!< Select the power down mode           */
#define PHY_ISOLATE                 ((uint16_t)0x0400) /*!< Isolate PHY from MII                 */

#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed   */
#define PHY_LINKED_STATUS     ((uint16_t)0x0004) /*!< Valid link established               */
#define PHY_JABBER_DETECTION  ((uint16_t)0x0002) /*!< Jabber condition detected            */

/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset                      */

#define PHY_SPEED_STATUS  ((uint16_t)0x0002U) /*!< PHY Speed mask                                  */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask                                 */

/* Includes ------------------------------------------------------------------*/
/**
 * @brief Include module's header file
 */

#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f1xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */

#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */

#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */

#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f1xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */

#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */

#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */

#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f1xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */

#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f1xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */

#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f1xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */

#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f1xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */

#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f1xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */

#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f1xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */

#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f1xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */

#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f1xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */

#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f1xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */

#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */

#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f1xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */

#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f1xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */

#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */

#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */

#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f1xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */

#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f1xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */

#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */

#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */

#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f1xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */

#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f1xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */

#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f1xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */

#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f1xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */

#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f1xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */

#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */

#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */

/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
 * @brief  The assert_param macro is used for function's parameters check.
 * @param  expr: If expr is false, it calls assert_failed function
 *         which reports the name of the source file and the source
 *         line number of the call that failed.
 *         If expr is true, it returns no value.
 * @retval None
 */
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_HAL_CONF_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/Inc/stm32f1xx_it.h
================================================
/**
 ******************************************************************************
 * @file    stm32f1xx_it.h
 * @brief   This file contains the headers of the interrupt handlers.
 ******************************************************************************
 *
 * COPYRIGHT(c) 2017 STMicroelectronics
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *   1. Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *   2. Redistributions in binary form must reproduce the above copyright notice,
 *      this list of conditions and the following disclaimer in the documentation
 *      and/or other materials provided with the distribution.
 *   3. Neither the name of STMicroelectronics nor the names of its contributors
 *      may be used to endorse or promote products derived from this software
 *      without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_IT_H
#define __STM32F1xx_IT_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void SysTick_Handler(void);
void DMA1_Channel1_IRQHandler(void);
void DMA1_Channel6_IRQHandler(void);
void DMA1_Channel7_IRQHandler(void);
void ADC1_2_IRQHandler(void);
void TIM1_UP_IRQHandler(void);

#ifdef __cplusplus
}
#endif

#endif /* __STM32F1xx_IT_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/LangSupport/lang_multi.cpp
================================================
#include "OLED.hpp"
#include "Translation.h"
#include "Translation_multi.h"
#include "brieflz.h"
#include "configuration.h"
#include "settingsGUI.hpp"

const TranslationIndexTable *Tr                 = nullptr;
const char                  *TranslationStrings = nullptr;

static uint8_t selectedLangIndex = 255;

static void initSelectedLanguageIndex() {
  if (selectedLangIndex == 255) {

    const uint16_t wantedLanguageID = getSettingValue(SettingsOptions::UILanguage);

    for (size_t i = 0; i < LanguageCount; i++) {
      if (LanguageMetas[i].uniqueID == wantedLanguageID) {
        selectedLangIndex = i;
        return;
      }
    }
    // No match, use the first language.
    selectedLangIndex = 0;
  }
}

static void writeSelectedLanguageToSettings() { setSettingValue(SettingsOptions::UILanguage, LanguageMetas[selectedLangIndex].uniqueID); }

void prepareTranslations() {
  initSelectedLanguageIndex();
  if (selectedLangIndex >= LanguageCount) {
    // This shouldn't happen.
    return;
  }
  const LanguageMeta &langMeta = LanguageMetas[selectedLangIndex];

  const TranslationData *translationData;
  uint16_t               buffer_remaining_size = translation_data_out_buffer_size;
  uint8_t               *buffer_next_ptr       = translation_data_out_buffer;
  if (langMeta.translation_is_compressed) {
    unsigned int outsize;
    outsize = blz_depack_srcsize(langMeta.translation_data, buffer_next_ptr, langMeta.translation_size);

    translationData = reinterpret_cast(buffer_next_ptr);
    buffer_remaining_size -= outsize;
    buffer_next_ptr += outsize;
  } else {
    translationData = reinterpret_cast(langMeta.translation_data);
  }
  Tr                 = &translationData->indices;
  TranslationStrings = translationData->strings;

  // Font 12 can be compressed; if it is then we want to decompress it to ram
  if (FontSectionInfo.font12_compressed_source != NULL) {
    blz_depack(FontSectionInfo.font12_compressed_source, (uint8_t *)FontSectionInfo.font12_start_ptr, FontSectionInfo.font12_decompressed_size);
  }

  // Font 06 can be compressed; if it is then we want to decompress it to ram
  if (FontSectionInfo.font06_compressed_source != NULL) {
    blz_depack(FontSectionInfo.font06_compressed_source, (uint8_t *)FontSectionInfo.font06_start_ptr, FontSectionInfo.font06_decompressed_size);
  }
}

void settings_setLanguageSwitch(void) {
  selectedLangIndex = (selectedLangIndex + 1) % LanguageCount;
  writeSelectedLanguageToSettings();
  prepareTranslations();
}

bool settings_showLanguageSwitch(void) { return true; }
void settings_displayLanguageSwitch(void) { OLED::printWholeScreen(translatedString(Tr->SettingsShortNames[static_cast(SettingsItemIndex::LanguageSwitch)])); }

bool isLastLanguageOption(void) { return selectedLangIndex == (LanguageCount - 1); }

================================================
FILE: source/Core/LangSupport/lang_single.cpp
================================================
#include "Translation.h"

void settings_setLanguageSwitch(void) {}

void settings_displayLanguageSwitch(void) {}
bool settings_showLanguageSwitch(void) { return false; }
bool isLastLanguageOption(void) { return true; }

================================================
FILE: source/Core/Src/FreeRTOSHooks.c
================================================
/*
 * FreeRTOSHooks.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "FreeRTOSHooks.h"
#include "BSP.h"
void vApplicationIdleHook(void) { resetWatchdog(); }

/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t  xIdleStack[configMINIMAL_STACK_SIZE];

void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
  *ppxIdleTaskTCBBuffer   = &xIdleTaskTCBBuffer;
  *ppxIdleTaskStackBuffer = &xIdleStack[0];
  *pulIdleTaskStackSize   = configMINIMAL_STACK_SIZE;
  /* place for user code */
}

void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) {
  (void)xTask;
  (void)pcTaskName;

  // We dont have a good way to handle a stack overflow at this point in time
  reboot();
}


================================================
FILE: source/Core/Src/QC3.cpp
================================================
/*
 * QC3.c
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

// Quick charge 3.0 supporting functions
#include "QC3.h"
#include "BSP.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "stdint.h"

enum QCState {
  NOT_STARTED = 0, // Have not checked
  QC_3        = 1,
  QC_2        = 2,
  NO_QC       = 3,
};

void QC_Seek9V() {
  QC_DNegZero_Six();
  QC_DPlusThree_Three();
}

void QC_Seek12V() {
  QC_DNegZero_Six();
  QC_DPlusZero_Six();
}

void QC_Seek20V() {
  QC_DNegThree_Three();
  QC_DPlusThree_Three();
}

void QC_SeekContMode() {
  QC_DNegThree_Three();
  QC_DPlusZero_Six();
}

void QC_SeekContPlus() {
  QC_SeekContMode();
  osDelay(30);
  QC_Seek20V();
  osDelay(10);
  QC_SeekContMode();
}

void QC_SeekContNeg() {
  QC_SeekContMode();
  osDelay(30);
  QC_Seek12V();
  osDelay(10);
  QC_SeekContMode();
}

QCState QCMode  = QCState::NOT_STARTED;
uint8_t QCTries = 0;
void    seekQC(int16_t Vx10, uint16_t divisor) {
  if (QCMode == QCState::NOT_STARTED) {
    startQC(divisor);
  }

  if (Vx10 < 40) { // Bail out if less than 4V
    return;
  }

  if (xTaskGetTickCount() < TICKS_SECOND) {
    return;
  }

  // Seek the QC to the Voltage given if this adapter supports continuous mode
  // try and step towards the wanted value

  // 1. Measure current voltage
  int16_t vStart     = getInputVoltageX10(divisor, 0);
  int     difference = Vx10 - vStart;

  // 2. calculate ideal steps (0.2V changes)

  int steps = difference / 2;
  if (QCMode == QCState::QC_3) {
    while (steps < 0) {
      QC_SeekContNeg();
      vTaskDelay(3 * TICKS_10MS);
      steps++;
    }
    while (steps > 0) {
      QC_SeekContPlus();
      vTaskDelay(3 * TICKS_10MS);
      steps--;
    }
    osDelay(100);
  }
#ifdef ENABLE_QC2
  // Re-measure
  /* Disabled due to nothing to test and code space of around 1k*/
  steps = vStart - getInputVoltageX10(divisor, 0);
  if (steps < 0) {
    steps = -steps;
  }
  if (steps > 4) {
    // No continuous mode, so QC2
    QCMode = QCState::QC_2;
    // Goto nearest
    if (Vx10 > 190) {
      // request 20V
      QC_Seek20V();
    } else if (Vx10 > 110) {
      // request 12V
      QC_Seek12V();
    } else {
      // request 9V
      QC_Seek9V();
    }
  }
#endif /* ENABLE_QC2 */
}

// Must be called after FreeRToS Starts
void startQC(uint16_t divisor) {
  // Pre check that the input could be >5V already, and if so, dont both
  // negotiating as someone is feeding in hv
  if (getInputVoltageX10(divisor, 0) > 80) {
    QCTries = 11;
    QCMode  = QCState::NO_QC;
    return;
  }
  if (QCTries > 10) {
    QCMode = QCState::NO_QC;
    return;
  }
  QCMode = QCState::NOT_STARTED;
  QC_Init_GPIO();

  // Tries to negotiate QC for 9V
  // This is a multiple step process.
  // 1. Set around 0.6V on D+ for 1.25 Seconds or so
  // 2. After this It should un-short D+->D- and instead add a 20k pulldown on
  // D-
  QC_DPlusZero_Six();

  // Delay 1.25 seconds
  uint8_t enteredQC = 0;
  for (uint16_t i = 0; i < 200 && enteredQC == 0; i++) {
    vTaskDelay(TICKS_10MS); // 10mS pause
    if (i > 130) {
      if (QC_DM_PulledDown()) {
        enteredQC = 1;
      }
      if (i == 140) {
        // For some marginal QC chargers, we try adding a pulldown
        QC_DM_PullDown();
      }
    }
  }

  QC_DM_No_PullDown();

  if (enteredQC) {
    // We have a QC capable charger
    QC_Seek9V();
    QC_Post_Probe_En();
    QC_Seek9V();
    // Wait for frontend ADC to stabilise
    QCMode = QCState::QC_2;
    for (uint8_t i = 0; i < 10; i++) {
      if (getInputVoltageX10(divisor, 0) > 80) {
        // yay we have at least QC2.0 or QC3.0
        QCMode = QCState::QC_3; // We have at least QC2, pray for 3
        return;
      }
      vTaskDelay(TICKS_100MS); // 100mS
    }
    QCMode = QCState::NOT_STARTED;
    QCTries++;
  } else {
    // no QC
    QCTries++;
    QCMode = QCState::NO_QC;
  }
}

bool hasQCNegotiated() { return QCMode == QCState::QC_3 || QCMode == QCState::QC_2; }


================================================
FILE: source/Core/Src/ScrollMessage.cpp
================================================
#include "ScrollMessage.hpp"
#include "OLED.hpp"
#include "Settings.h"
#include "configuration.h"

/**
 * Counts the number of chars in the string excluding the null terminator.
 * This is a custom version of `strlen` which takes into account our custom
 * double-byte char encoding.
 * @param str The input string.
 * @return The length of the string.
 */
static uint16_t str_display_len(const char *const str) {
  const uint8_t *next  = reinterpret_cast(str);
  uint16_t       count = 0;
  while (next[0]) {
    if (next[0] <= 0xF0) {
      count++;
      next++;
    } else {
      if (!next[1]) {
        break;
      }
      count++;
      next += 2;
    }
  }
  return count;
}

/**
 * Calculate the width in pixels of the message string, in the large
 * font and taking into account multi-byte chars.
 *
 * @param message The null-terminated message string.
 */
uint16_t messageWidth(const char *message) { return FONT_12_WIDTH * str_display_len(message); }

void drawScrollingText(const char *message, TickType_t currentTickOffset) {
  OLED::clearScreen();
  int16_t  messageOffset;
  uint16_t msgWidth = messageWidth(message);
  if (msgWidth > OLED_WIDTH) {
    messageOffset = (currentTickOffset / (getSettingValue(SettingsOptions::DescriptionScrollSpeed) == 1 ? TICKS_100MS / 10 : (TICKS_100MS / 5)));
    messageOffset %= msgWidth + OLED_WIDTH; // Roll around at the end
    if (messageOffset < OLED_WIDTH) {
      // Snap the message to the left edge.
      messageOffset = OLED_WIDTH;
    } else if (messageOffset > msgWidth) {
      // Snap the message to the right edge.
      messageOffset = msgWidth;
    }
  } else {
    // Centre the message without scrolling.
    messageOffset = (OLED_WIDTH - msgWidth) / 2 + msgWidth;
  }

  //^ Rolling offset based on time
  OLED::setCursor((OLED_WIDTH - messageOffset), 0);
  OLED::print(message, FontStyle::LARGE);
}


================================================
FILE: source/Core/Src/Settings.cpp
================================================
/*
 * Settings.c
 *
 *  Created on: 29 Sep 2016
 *      Author: Ralim
 *
 *      This file holds the users settings and saves / restores them to the
 * devices flash
 */

#include "Settings.h"
#include "BSP.h"
#include "Setup.h"
#include "Translation.h"
#include "configuration.h"
#include  // for memset
bool sanitiseSettings();

/*
 * Used to constrain the QC 3.0 Voltage selection to suit hardware.
 * We allow a little overvoltage for users who want to push it
 */
#ifdef POW_QC_20V
#define QC_VOLTAGE_MAX 220
#else
#define QC_VOLTAGE_MAX 140
#endif /* POW_QC_20V */

/*
 * This struct must be a multiple of 2 bytes as it is saved / restored from
 * flash in uint16_t chunks
 */
typedef struct {
  uint16_t versionMarker;
  uint16_t length; // Length of valid bytes following
  uint16_t settingsValues[SettingsOptionsLength];
  // used to make this nicely "good enough" aligned to 32 bytes to make driver code trivial
  uint32_t padding;

} systemSettingsType;

//~1024 is common programming size, setting threshold to be lower so we have warning
static_assert(sizeof(systemSettingsType) < 512);

// char (*__kaboom)[sizeof(systemSettingsType)] = 1; // Uncomment to print size at compile time
volatile systemSettingsType systemSettings;

// For every setting we need to store the min/max/increment values
typedef struct {
  const uint16_t min;          // Inclusive minimum value
  const uint16_t max;          // Inclusive maximum value
  const uint16_t increment;    // Standard increment
  const uint16_t defaultValue; // Default vaue after reset
} SettingConstants;

static const SettingConstants settingsConstants[(int)SettingsOptions::SettingsOptionsLength] = {
    //{                   min,                               max,         increment,                      default}
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,               SOLDERING_TEMP}, // SolderingTemp
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                          150}, // SleepTemp
    {                     0,                                                                    15,                 1,                   SLEEP_TIME}, // SleepTime
    {                     0,                                                                     4,                 1,              CUT_OUT_SETTING}, // MinDCVoltageCells
    {                    24,                                                                    38,                 1,               RECOM_VOL_CELL}, // MinVoltageCells
    {                    90,                                                        QC_VOLTAGE_MAX,                 2,                           90}, // QCIdealVoltage
    {                     0,                                                  MAX_ORIENTATION_MODE,                 1,             ORIENTATION_MODE}, // OrientationMode
    {                     0,                                                                     9,                 1,                  SENSITIVITY}, // Sensitivity
    {                     0,                                                                     1,                 1,               ANIMATION_LOOP}, // AnimationLoop
    {                     0,                                      settingOffSpeed_t::MAX_VALUE - 1,                 1,              ANIMATION_SPEED}, // AnimationSpeed
    {                     0,                                                                     3,                 1,              AUTO_START_MODE}, // AutoStartMode
    {                     0,                                                                    60,                 1,                SHUTDOWN_TIME}, // ShutdownTime
    {                     0,                                                                     1,                 1,           COOLING_TEMP_BLINK}, // CoolingTempBlink
    {                     0,                                                                     1,                 1,                DETAILED_IDLE}, // DetailedIDLE
    {                     0,                                                                     1,                 1,           DETAILED_SOLDERING}, // DetailedSoldering
    {                     0,                                     (uint16_t)(HasFahrenheit ? 1 : 0),                 1,              TEMPERATURE_INF}, // TemperatureInF
    {                     0,                                                                     1,                 1,     DESCRIPTION_SCROLL_SPEED}, // DescriptionScrollSpeed
    {                     0,                                                                     2,                 1,                 LOCKING_MODE}, // LockingMode
    {                     0,                                                                    99,                 1,          POWER_PULSE_DEFAULT}, // KeepAwakePulse
    {                     1,                                                  POWER_PULSE_WAIT_MAX,                 1,     POWER_PULSE_WAIT_DEFAULT}, // KeepAwakePulseWait
    {                     1,                                              POWER_PULSE_DURATION_MAX,                 1, POWER_PULSE_DURATION_DEFAULT}, // KeepAwakePulseDuration
    {                   360,                                                                   900,                 1,                  VOLTAGE_DIV}, // VoltageDiv
    {                     0,                                                            MAX_TEMP_F,                10,                   BOOST_TEMP}, // BoostTemp
    {MIN_CALIBRATION_OFFSET,                                                                  2500,                 1,           CALIBRATION_OFFSET}, // CalibrationOffset
    {                     0,                                                       MAX_POWER_LIMIT, POWER_LIMIT_STEPS,                  POWER_LIMIT}, // PowerLimit
    {                     0,                                                                     1,                 1,   REVERSE_BUTTON_TEMP_CHANGE}, // ReverseButtonTempChangeEnabled
    {                     5,                                             TEMP_CHANGE_LONG_STEP_MAX,                 5,        TEMP_CHANGE_LONG_STEP}, // TempChangeLongStep
    {                     1,                                            TEMP_CHANGE_SHORT_STEP_MAX,                 1,       TEMP_CHANGE_SHORT_STEP}, // TempChangeShortStep
    {                     0,                                                                     9,                 1,                            7}, // HallEffectSensitivity
    {                     0,                                                                     9,                 1,                            0}, // AccelMissingWarningCounter
    {                     0,                                                                     9,                 1,                            0}, // PDMissingWarningCounter
    {                     0,                                                                0xFFFF,                 0,                 41431 /*EN*/}, // UILanguage
    {                     0,                                                                    50,                 1,                           20}, // PDNegTimeout
    {                     0,                                                                     1,                 1,                            0}, // OLEDInversion
    {        MIN_BRIGHTNESS,                                                        MAX_BRIGHTNESS,   BRIGHTNESS_STEP,           DEFAULT_BRIGHTNESS}, // OLEDBrightness
    {                     0,                                                                     6,                 1,                            1}, // LOGOTime
    {                     0,                                                                     1,                 1,                            0}, // CalibrateCJC
    {                     0,                                                                     1,                 1,                            0}, // BluetoothLE
    {                     0,                                                                     2,                 1,                            0}, // USBPDMode
    {                     1,                                                                     5,                 1,                            4}, // ProfilePhases
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                           90}, // ProfilePreheatTemp
    {                     1,                                                                    10,                 1,                            1}, // ProfilePreheatSpeed
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                          130}, // ProfilePhase1Temp
    {                    10,                                                                   180,                 5,                           90}, // ProfilePhase1Duration
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                          140}, // ProfilePhase2Temp
    {                    10,                                                                   180,                 5,                           30}, // ProfilePhase2Duration
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                          165}, // ProfilePhase3Temp
    {                    10,                                                                   180,                 5,                           30}, // ProfilePhase3Duration
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                          140}, // ProfilePhase4Temp
    {                    10,                                                                   180,                 5,                           30}, // ProfilePhase4Duration
    {            MIN_TEMP_C,                                                            MAX_TEMP_F,                 5,                           90}, // ProfilePhase5Temp
    {                    10,                                                                   180,                 5,                           30}, // ProfilePhase5Duration
    {                     1,                                                                    10,                 1,                            2}, // ProfileCooldownSpeed
    {                     0,                                                                    12,                 1,                            0}, // HallEffectSleepTime
    {                     0, (tipType_t::TIP_TYPE_MAX - 1) > 0 ? (tipType_t::TIP_TYPE_MAX - 1) : 0,                 1,                            0}, // SolderingTipType
    {                     0,                                                                     1,                 1,                            0}, // ReverseButtonSettings
};
static_assert((sizeof(settingsConstants) / sizeof(SettingConstants)) == ((int)SettingsOptions::SettingsOptionsLength));

void saveSettings() {
#ifdef CANT_DIRECT_READ_SETTINGS
  // For these devices flash is not 1:1 mapped, so need to read into staging buffer
  systemSettingsType settings;
  flash_read_buffer((uint8_t *)&settings, sizeof(systemSettingsType));
  if (memcmp((void *)&settings, (void *)&systemSettings, sizeof(systemSettingsType))) {
    flash_save_buffer((uint8_t *)&systemSettings, sizeof(systemSettingsType));
  }

#else
  if (memcmp((void *)SETTINGS_START_PAGE, (void *)&systemSettings, sizeof(systemSettingsType))) {
    flash_save_buffer((uint8_t *)&systemSettings, sizeof(systemSettingsType));
  }

#endif /* CANT_DIRECT_READ_SETTINGS */
}

bool loadSettings() {
  // We read the flash
  flash_read_buffer((uint8_t *)&systemSettings, sizeof(systemSettingsType));
  // Then ensure all values are valid
  return sanitiseSettings();
}

bool sanitiseSettings() {
  // For all settings, need to ensure settings are in a valid range
  // First for any not know about due to array growth, reset them and update the length value
  bool dirty = false;
  if (systemSettings.versionMarker != SETTINGSVERSION) {
    memset((void *)&systemSettings, 0xFF, sizeof(systemSettings));
    systemSettings.versionMarker = SETTINGSVERSION;
    dirty                        = true;
  }
  if (systemSettings.padding != 0xFFFFFFFF) {
    systemSettings.padding = 0xFFFFFFFF; // Force padding to 0xFFFFFFFF so that rolling forwards / back should be easier
    dirty                  = true;
  }
  if (systemSettings.length < (int)SettingsOptions::SettingsOptionsLength) {
    dirty = true;
    for (int i = systemSettings.length; i < (int)SettingsOptions::SettingsOptionsLength; i++) {
      systemSettings.settingsValues[i] = 0xFFFF; // Ensure its as if it was erased
    }
    systemSettings.length = (int)SettingsOptions::SettingsOptionsLength;
  }
  for (int i = 0; i < (int)SettingsOptions::SettingsOptionsLength; i++) {
    // Check min max for all settings, if outside the range, move to default
    if (systemSettings.settingsValues[i] < settingsConstants[i].min || systemSettings.settingsValues[i] > settingsConstants[i].max) {
      systemSettings.settingsValues[i] = settingsConstants[i].defaultValue;
      dirty                            = true;
    }
  }
  if (dirty) {
    saveSettings();
  }
  return dirty;
}

void resetSettings() {
  memset((void *)&systemSettings, 0xFF, sizeof(systemSettingsType));
  sanitiseSettings();
  saveSettings(); // Save defaults
}

void setSettingValue(const enum SettingsOptions option, const uint16_t newValue) {
  const auto constants        = settingsConstants[(int)option];
  uint16_t   constrainedValue = newValue;
  if (constrainedValue < constants.min) {
    // If less than min, constrain
    constrainedValue = constants.min;
  } else if (constrainedValue > constants.max) {
    // If hit max, constrain
    constrainedValue = constants.max;
  }
  systemSettings.settingsValues[(int)option] = constrainedValue;
}

// Lookup wrapper for ease of use (with typing)
uint16_t getSettingValue(const enum SettingsOptions option) { return systemSettings.settingsValues[(int)option]; }

// Increment by the step size to the next value. If past the end wrap to the minimum
// Returns true if we are on the _last_ value
void nextSettingValue(const enum SettingsOptions option) {
  const auto constants = settingsConstants[(int)option];
  if (systemSettings.settingsValues[(int)option] == (constants.max)) {
    // Already at max, wrap to the start
    systemSettings.settingsValues[(int)option] = constants.min;
  } else if (systemSettings.settingsValues[(int)option] >= (constants.max - constants.increment)) {
    // If within one increment of the end, constrain to the end
    systemSettings.settingsValues[(int)option] = constants.max;
  } else {
    // Otherwise increment
    systemSettings.settingsValues[(int)option] += constants.increment;
  }
}

bool isLastSettingValue(const enum SettingsOptions option) {
  const auto constants = settingsConstants[(int)option];
  uint16_t   max       = constants.max;
  // handle temp unit limitations
  if (option == SettingsOptions::SolderingTemp) {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      max = MAX_TEMP_F;
    } else {
      max = MAX_TEMP_C;
    }
  } else if (option == SettingsOptions::BoostTemp) {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      max = MAX_TEMP_F;
    } else {
      max = MAX_TEMP_C;
    }
  } else if (option == SettingsOptions::SleepTemp) {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      max = 580;
    } else {
      max = 300;
    }
  } else if (option == SettingsOptions::UILanguage) {
    return isLastLanguageOption();
  }
  return systemSettings.settingsValues[(int)option] > (max - constants.increment);
}
// Step backwards on the settings item
// Return true if we are at the end (min)
void prevSettingValue(const enum SettingsOptions option) {
  const auto constants = settingsConstants[(int)option];
  if (systemSettings.settingsValues[(int)option] == (constants.min)) {
    // Already at min, wrap to the max
    systemSettings.settingsValues[(int)option] = constants.max;
  } else if (systemSettings.settingsValues[(int)option] <= (constants.min + constants.increment)) {
    // If within one increment of the start, constrain to the start
    systemSettings.settingsValues[(int)option] = constants.min;
  } else {
    // Otherwise decrement
    systemSettings.settingsValues[(int)option] -= constants.increment;
  }
}

uint16_t lookupHallEffectThreshold() {
  // Return the threshold above which the hall effect sensor is "activated"
  // We want this to be roughly exponentially mapped from 0-1000
  switch (getSettingValue(SettingsOptions::HallEffectSensitivity)) {
  case 0:
    return 0;
  case 1:
    return 1000;
  case 2:
    return 750;
  case 3:
    return 500;
  case 4:
    return 250;
  case 5:
    return 150;
  case 6:
    return 100;
  case 7:
    return 75;
  case 8:
    return 50;
  case 9:
    return 25;
  default:
    return 0; // Off
  }
}

// Lookup function for cutoff setting -> X10 voltage
/*
 * 0=DC
 * 1=3S
 * 2=4S
 * 3=5S
 * 4=6S
 */
uint8_t lookupVoltageLevel() {
  auto minVoltageOnCell    = getSettingValue(SettingsOptions::MinDCVoltageCells);
  auto minVoltageCellCount = getSettingValue(SettingsOptions::MinVoltageCells);
  if (minVoltageOnCell == 0) {
    return 90; // 9V since iron does not function effectively below this
  } else {
    return (minVoltageOnCell * minVoltageCellCount) + (minVoltageCellCount * 2);
  }
}

#ifdef TIP_TYPE_SUPPORT
const char *lookupTipName() {
  // Get the name string for the current soldering tip
  tipType_t value = (tipType_t)getSettingValue(SettingsOptions::SolderingTipType);

  switch (value) {
#ifdef TIPTYPE_T12
  case tipType_t::T12_8_OHM:
    return translatedString(Tr->TipTypeT12Long);
    break;
  case tipType_t::T12_6_2_OHM:
    return translatedString(Tr->TipTypeT12Short);
    break;
  case tipType_t::T12_4_OHM:
    return translatedString(Tr->TipTypeT12PTS);
    break;
#endif
#ifdef TIPTYPE_TS80
  case tipType_t::TS80_4_5_OHM:
    return translatedString(Tr->TipTypeTS80);
    break;
#endif
#ifdef TIPTYPE_JBC
  case tipType_t::JBC_210_2_5_OHM:
    return translatedString(Tr->TipTypeJBCC210);
    break;
#endif
#ifdef AUTO_TIP_SELECTION
  case tipType_t::TIP_TYPE_AUTO:
#endif
  default:
    return translatedString(Tr->TipTypeAuto);
    break;
  }
}
#endif /* TIP_TYPE_SUPPORT */

// Returns the resistance for the current tip selected by the user or 0 for auto
#ifdef TIP_TYPE_SUPPORT
uint8_t getUserSelectedTipResistance() {
  tipType_t value = (tipType_t)getSettingValue(SettingsOptions::SolderingTipType);

  switch (value) {
#ifdef AUTO_TIP_SELECTION
  case tipType_t::TIP_TYPE_AUTO:
    return 0;
    break;
#endif
#ifdef TIPTYPE_T12
  case tipType_t::T12_8_OHM:
    return 80;
    break;
  case tipType_t::T12_6_2_OHM:
    return 62;
    break;
  case tipType_t::T12_4_OHM:
    return 40;
    break;
#endif
#ifdef TIPTYE_TS80
  case tipType_t::TS80_4_5_OHM:
    return 45;
    break;
#endif
#ifdef TIPTYPE_JBC
  case tipType_t::JBC_210_2_5_OHM:
    return 25;
    break;
#endif
  default:
    return 0;
    break;
  }
}
#else
uint8_t getUserSelectedTipResistance() { return tipType_t::TIP_TYPE_AUTO; }
#endif /* TIP_TYPE_SUPPORT */


================================================
FILE: source/Core/Src/Translation.cpp
================================================
#include "Translation.h"

const char *translatedString(uint16_t offset) { return TranslationStrings + offset; }


================================================
FILE: source/Core/Src/freertos.c
================================================
/**
 ******************************************************************************
 * File Name          : freertos.c
 * Description        : Code for freertos applications
 ******************************************************************************
 * This notice applies to any and all portions of this file
 * that are not between comment pairs USER CODE BEGIN and
 * USER CODE END. Other portions of this file, whether
 * inserted by the user or by software development tools
 * are owned by their respective copyright owners.
 *
 * Copyright (c) 2017 STMicroelectronics International N.V.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted, provided that the following conditions are met:
 *
 * 1. Redistribution of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. Neither the name of STMicroelectronics nor the names of other
 *    contributors to this software may be used to endorse or promote products
 *    derived from this software without specific written permission.
 * 4. This software, including modifications and/or derivative works of this
 *    software, must execute solely and exclusively on microcontroller or
 *    microprocessor devices manufactured by or for STMicroelectronics.
 * 5. Redistribution and use of this software other than as permitted under
 *    this license is void and will automatically terminate your rights under
 *    this license.
 *
 * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
 * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
 * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
 * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

/* Includes ------------------------------------------------------------------*/
#include "FreeRTOS.h"
#include "task.h"
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/


================================================
FILE: source/Core/Src/main.cpp
================================================
// By Ben V. Brown - V2.0 of the TS100 firmware

/*
 * Main.cpp bootstraps the device and then hands over to FreeRTOS and the threads
 */

#include "main.hpp"
#include "BSP.h"
#include "Settings.h"
#include "cmsis_os.h"
#include "power.hpp"
AccelType DetectedAccelerometerVersion = AccelType::Scanning;
bool      settingsWereReset            = false;
// FreeRTOS variables

osThreadId          GUITaskHandle;
static const size_t GUITaskStackSize = 1024 / 2;
uint32_t            GUITaskBuffer[GUITaskStackSize];
osStaticThreadDef_t GUITaskControlBlock;

osThreadId          PIDTaskHandle;
static const size_t PIDTaskStackSize = 1024 / 2;
uint32_t            PIDTaskBuffer[PIDTaskStackSize];
osStaticThreadDef_t PIDTaskControlBlock;

osThreadId          MOVTaskHandle;
static const size_t MOVTaskStackSize = 1024 / 2;
uint32_t            MOVTaskBuffer[MOVTaskStackSize];
osStaticThreadDef_t MOVTaskControlBlock;

osThreadId          POWTaskHandle;
static const size_t POWTaskStackSize = 512 / 2;
uint32_t            POWTaskBuffer[POWTaskStackSize];
osStaticThreadDef_t POWTaskControlBlock;

// End FreeRTOS
// Main sets up the hardware then hands over to the FreeRTOS kernel
int main(void) {
  preRToSInit();

  resetWatchdog();
  // Testing for which accelerometer is mounted
  settingsWereReset = loadSettings(); // load the settings from flash

  setTipX10Watts(0); // force tip off

  resetWatchdog();
  /* Create the thread(s) */

  /* definition and creation of PIDTask - Heating control*/
  osThreadStaticDef(PIDTask, startPIDTask, osPriorityRealtime, 0, PIDTaskStackSize, PIDTaskBuffer, &PIDTaskControlBlock);
  PIDTaskHandle = osThreadCreate(osThread(PIDTask), NULL);

  /* definition and creation of POWTask - Power management for QC / PD */
  osThreadStaticDef(POWTask, startPOWTask, osPriorityAboveNormal, 0, POWTaskStackSize, POWTaskBuffer, &POWTaskControlBlock);
  POWTaskHandle = osThreadCreate(osThread(POWTask), NULL);

  /* definition and creation of MOVTask - Accelerometer management */
  osThreadStaticDef(MOVTask, startMOVTask, osPriorityNormal, 0, MOVTaskStackSize, MOVTaskBuffer, &MOVTaskControlBlock);
  MOVTaskHandle = osThreadCreate(osThread(MOVTask), NULL);

  /* definition and creation of GUITask - The OLED control & update*/
  osThreadStaticDef(GUITask, startGUITask, osPriorityBelowNormal, 0, GUITaskStackSize, GUITaskBuffer, &GUITaskControlBlock);
  GUITaskHandle = osThreadCreate(osThread(GUITask), NULL);

  resetWatchdog();

  /* Start scheduler */
  osKernelStart();
  /* We should never get here as control is now taken by the scheduler */
  for (;;) {
  }
}


================================================
FILE: source/Core/Src/power.cpp
================================================
/*
 * power.cpp
 *
 *  Created on: 28 Oct, 2018
 *     Authors: Ben V. Brown, David Hilton <- Mostly David
 */

#include 
#include 
#include 

static int32_t PWMToX10Watts(uint8_t pwm, uint8_t sample);
const int      fastPWMChangeoverPoint     = 128;
const int      fastPWMChangeoverTolerance = 16;

expMovingAverage x10WattHistory = {0};

bool shouldBeUsingFastPWMMode(const uint8_t pwmTicks) {
  // Determine if we should use slow or fast PWM mode
  // Crossover between modes set around the midpoint of the PWM control point
  static bool lastPWMWasFast = true;
  if (pwmTicks > (fastPWMChangeoverPoint + fastPWMChangeoverTolerance) && lastPWMWasFast) {
    lastPWMWasFast = false;
  } else if (pwmTicks < (fastPWMChangeoverPoint - fastPWMChangeoverTolerance) && !lastPWMWasFast) {
    lastPWMWasFast = true;
  }
  return lastPWMWasFast;
}

void setTipX10Watts(int32_t mw) {
  int32_t    outputPWMLevel   = X10WattsToPWM(mw, 1);
  const bool shouldUseFastPWM = shouldBeUsingFastPWMMode(outputPWMLevel);
  setTipPWM(outputPWMLevel, shouldUseFastPWM);
  uint32_t actualMilliWatts = PWMToX10Watts(outputPWMLevel, 0);

  x10WattHistory.update(actualMilliWatts);
}

uint32_t availableW10(uint8_t sample) {
  // P = V^2 / R, v*v = v^2 * 100
  //				R = R*10
  // P therefore is in V^2*100/R*10 = W*10.
  uint32_t v             = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), sample); // 100 = 10v
  uint32_t tipResistance = getTipResistanceX10();
  if (tipResistance == 0) {
    return 100; // say 100 watt to force scale down
  }
  uint32_t availableWattsX10 = (v * v) / tipResistance;
  // However, 100% duty cycle is not possible as there is a dead time while the ADC takes a reading
  // Therefore need to scale available milliwats by this

  // avMw=(AvMw*powerPWM)/totalPWM.
  availableWattsX10 = availableWattsX10 * powerPWM;
  availableWattsX10 /= totalPWM;

  // availableMilliWattsX10 is now an accurate representation
  return availableWattsX10;
}
uint8_t X10WattsToPWM(int32_t x10Watts, uint8_t sample) {
  // Scale input x10Watts to the pwm range available
  if (x10Watts <= 0) {
    // keep the battery voltage updating the filter
    getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), sample);
    return 0;
  }

  // Calculate desired x10Watts as a percentage of availableW10
  uint32_t pwm;
  pwm = (powerPWM * x10Watts) / availableW10(sample);
  if (pwm > powerPWM) {
    // constrain to max PWM counter
    pwm = powerPWM;
  }
  return pwm;
}

static int32_t PWMToX10Watts(uint8_t pwm, uint8_t sample) {
  uint32_t maxMW = availableW10(sample); // Get the milliwatts for the max pwm period
  // Then convert pwm into percentage of powerPWM to get the percentage of the max mw
  return (((uint32_t)pwm) * maxMW) / powerPWM;
}


================================================
FILE: source/Core/Src/settingsGUI.cpp
================================================
/*
 * settingsGUI.cpp
 *
 *  Created on: 3Sep.,2017
 *      Author: Ben V. Brown
 */

#include "settingsGUI.hpp"
#include "Buttons.hpp"
#include "Font.h"
#include "ScrollMessage.hpp"
#include "TipThermoModel.h"
#include "Translation.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "main.hpp"
#include "ui_drawing.hpp"

#ifdef POW_DC
static void displayInputVRange(void);
static bool showInputVOptions(void);
static void displayInputMinVRange(void);
#endif /* POW_DC */

#ifdef POW_QC
static void displayQCInputV(void);
#endif /* POW_QC */

#ifdef POW_PD
static void displayPDNegTimeout(void);
static void displayUSBPDMode(void);
#endif /* POW_PD */

static void displaySensitivity(void);
static void displayShutdownTime(void);
static bool showSleepOptions(void);

#ifndef NO_SLEEP_MODE
static void setSleepTemp(void);
static void displaySleepTemp(void);
static void displaySleepTime(void);
#endif /* *not* NO_SLEEP_MODE */

static void setTempF(void);
static void displayTempF(void);
static void displayAdvancedSolderingScreens(void);
static void displayAdvancedIDLEScreens(void);
static void displayScrollSpeed(void);
static void displayReverseButtonTempChangeEnabled(void);
static void displayReverseButtonSettings(void);
static void displayPowerLimit(void);

#ifdef BLE_ENABLED
static void displayBluetoothLE(void);
#endif /* BLE_ENABLED */

#ifndef NO_DISPLAY_ROTATE
static void setDisplayRotation(void);
static void displayDisplayRotation(void);
#endif /* *not* NO_DISPLAY_ROTATE */

static void setBoostTemp(void);
static void displayBoostTemp(void);

#ifdef PROFILE_SUPPORT
static void setProfilePreheatTemp();
static void setProfilePhase1Temp();
static void setProfilePhase2Temp();
static void setProfilePhase3Temp();
static void setProfilePhase4Temp();
static void setProfilePhase5Temp();
static void displayProfilePhases(void);
static void displayProfilePreheatTemp(void);
static void displayProfilePreheatSpeed(void);
static void displayProfilePhase1Temp(void);
static void displayProfilePhase1Duration(void);
static void displayProfilePhase2Temp(void);
static void displayProfilePhase2Duration(void);
static void displayProfilePhase3Temp(void);
static void displayProfilePhase3Duration(void);
static void displayProfilePhase4Temp(void);
static void displayProfilePhase4Duration(void);
static void displayProfilePhase5Temp(void);
static void displayProfilePhase5Duration(void);
static void displayProfileCooldownSpeed(void);
static bool showProfileOptions(void);
static bool showProfilePhase2Options(void);
static bool showProfilePhase3Options(void);
static bool showProfilePhase4Options(void);
static bool showProfilePhase5Options(void);
#endif /* PROFILE_SUPPORT */

static void displayAutomaticStartMode(void);
static void displayLockingMode(void);
static void displayCoolingBlinkEnabled(void);
static void setResetSettings(void);
static void setCalibrate(void);
static void displayCalibrate(void);
static void setCalibrateVIN(void);
static void displayTempChangeShortStep(void);
static void displayTempChangeLongStep(void);
static void displayPowerPulse(void);
static bool displayAnimationOptions(void);
static void displayAnimationSpeed(void);
static void displayAnimationLoop(void);
static void displayPowerPulseWait(void);
static bool showPowerPulseOptions(void);
static void displayPowerPulseDuration(void);
static void displayBrightnessLevel(void);
static void displayInvertColor(void);
static void displayLogoTime(void);

#ifdef HALL_SENSOR
static void displayHallEffect(void);
static void displayHallEffectSleepTime(void);
static bool showHallEffect(void);
#endif /* HALL_SENSOR */

// Tip type selection
#ifdef TIP_TYPE_SUPPORT
static void displaySolderingTipType(void);
static bool showSolderingTipType(void);
#endif /* TIP_TYPE_SUPPORT */

// Menu functions

#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
static void displayPowerMenu(void);
#endif /* POW_DC or POW_QC */

static void displaySolderingMenu(void);
static void displayPowerSavingMenu(void);
static void displayUIMenu(void);
static void displayAdvancedMenu(void);

/*
 * Root Settings Menu
 *
 * Power Menu
 *  Power Source
 *  -Minimum Voltage
 *  QC Voltage
 *  PD Timeout
 *  USBPDMode
 *
 * Soldering
 *  Tip Type selection
 *  Boost Mode Temp
 *  Auto Start
 *  Temp Change Short Step
 *  Temp Change Long Step
 *  Locking Mode
 *  Profile Phases
 *  Profile Preheat Temperature
 *  Profile Preheat Max Temperature Change Per Second
 *  Profile Phase 1 Temperature
 *  Profile Phase 1 Duration (s)
 *  Profile Phase 2 Temperature
 *  Profile Phase 2 Duration (s)
 *  Profile Phase 3 Temperature
 *  Profile Phase 3 Duration (s)
 *  Profile Phase 4 Temperature
 *  Profile Phase 4 Duration (s)
 *  Profile Phase 5 Temperature
 *  Profile Phase 5 Duration (s)
 *  Profile Cooldown Max Temperature Change Per Second
 *
 * Power Saving
 *  Motion Sensitivity
 *  -Sleep Temp
 *  -Sleep Time
 *  -Shutdown Time
 *  Hall Sensor Sensitivity
 *  Hall Sensor Sleep Time
 *
 * UI
 *  Temperature Unit
 *  Display Orientation
 *  Cooldown Blink
 *  Scrolling Speed
 *  Swap Temp Change Buttons +/-
 *  Animation Speed
 *  -Animation Loop
 *  OLED Brightness
 *  Invert Screen
 *  Logo Timeout
 *  Detailed IDLE
 *  Detailed Soldering
 *
 * Advanced
 *  BluetoothLE
 *  Power Limit
 *  Calibrate CJC At Next Boot
 *  Calibrate Input V
 *  Power Pulse
 *  -Power Pulse Delay
 *  -Power Pulse Duration
 *  Factory Reset
 *
 */

void noOpDisplay() {}
/* vvv !!!DISABLE CLANG-FORMAT for menuitems initialization!!! vvv */

/* clang-format off */

/* A lot of suggestions by clang-format can be useful
 * but not when dealing with such menuitems declarations.
 */

const menuitem rootSettingsMenu[] {
  /*
   * Power Menu
   * Soldering Menu
   * Power Saving Menu
   * UI Menu
   * Advanced Menu
   * // Language
   * Exit
   */
#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
  /* Power */
  {0, nullptr, displayPowerMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
#endif
  /* Soldering */
  {0, nullptr, displaySolderingMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
  /* Sleep Options Menu */
  {0, nullptr, displayPowerSavingMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
  /* UI Menu */
  {0, nullptr, displayUIMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
  /* Advanced Menu */
  {0, nullptr, displayAdvancedMenu, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
  /* Language Switch */
  {0, settings_setLanguageSwitch, settings_displayLanguageSwitch, settings_showLanguageSwitch, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0},
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};

#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
const menuitem powerMenu[] = {
  /*
   * Power Source
   * -Minimum Voltage
   * QC Voltage
   * PD Timeout
   * USBPDMode
   */
#ifdef POW_DC
  /* Voltage input */
  {SETTINGS_DESC(SettingsItemIndex::DCInCutoff), nullptr, displayInputVRange, nullptr, SettingsOptions::MinDCVoltageCells, SettingsItemIndex::DCInCutoff, 6},
  /* Minimum voltage input */
  {SETTINGS_DESC(SettingsItemIndex::MinVolCell), nullptr, displayInputMinVRange, showInputVOptions, SettingsOptions::MinVoltageCells, SettingsItemIndex::MinVolCell, 5},
#endif
#ifdef POW_QC
  /* Voltage input */
  {SETTINGS_DESC(SettingsItemIndex::QCMaxVoltage), nullptr, displayQCInputV, nullptr, SettingsOptions::QCIdealVoltage, SettingsItemIndex::QCMaxVoltage, 4},
#endif
#ifdef POW_PD
  /* PD timeout setup */
  {SETTINGS_DESC(SettingsItemIndex::PDNegTimeout), nullptr, displayPDNegTimeout, nullptr, SettingsOptions::PDNegTimeout, SettingsItemIndex::PDNegTimeout, 6},
  /* Toggle PPS & EPR */
  {SETTINGS_DESC(SettingsItemIndex::USBPDMode), nullptr, displayUSBPDMode, nullptr, SettingsOptions::USBPDMode, SettingsItemIndex::USBPDMode, 4},
#endif
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};
#endif /* POW_DC or POW_QC or POW_PD */

const menuitem solderingMenu[] = {
  /*
   *  Boost Mode Temp
   *  Auto Start
   *  Temp Change Short Step
   *  Temp Change Long Step
   *  Locking Mode
   *  Tip Type
   *  Profile Phases
   *  Profile Preheat Temperature
   *  Profile Preheat Max Temperature Change Per Second
   *  Profile Phase 1 Temperature
   *  Profile Phase 1 Duration (s)
   *  Profile Phase 2 Temperature
   *  Profile Phase 2 Duration (s)
   *  Profile Phase 3 Temperature
   *  Profile Phase 3 Duration (s)
   *  Profile Phase 4 Temperature
   *  Profile Phase 4 Duration (s)
   *  Profile Phase 5 Temperature
   *  Profile Phase 5 Duration (s)
   *  Profile Cooldown Max Temperature Change Per Second
   */
  /* Boost Temp */
  {SETTINGS_DESC(SettingsItemIndex::BoostTemperature), setBoostTemp, displayBoostTemp, nullptr, SettingsOptions::BoostTemp, SettingsItemIndex::BoostTemperature, 5},
  /* Auto start */
  {SETTINGS_DESC(SettingsItemIndex::AutoStart), nullptr, displayAutomaticStartMode, nullptr, SettingsOptions::AutoStartMode, SettingsItemIndex::AutoStart, 7},
  /* Temp change short step */
  {SETTINGS_DESC(SettingsItemIndex::TempChangeShortStep), nullptr, displayTempChangeShortStep, nullptr, SettingsOptions::TempChangeShortStep, SettingsItemIndex::TempChangeShortStep, 6},
  /* Temp change long step */
  {SETTINGS_DESC(SettingsItemIndex::TempChangeLongStep), nullptr, displayTempChangeLongStep, nullptr, SettingsOptions::TempChangeLongStep, SettingsItemIndex::TempChangeLongStep, 6},
  /* Locking Mode */
  {SETTINGS_DESC(SettingsItemIndex::LockingMode), nullptr, displayLockingMode, nullptr, SettingsOptions::LockingMode, SettingsItemIndex::LockingMode, 7},
#ifdef TIP_TYPE_SUPPORT
  /* Tip Type */
  {SETTINGS_DESC(SettingsItemIndex::SolderingTipType), nullptr, displaySolderingTipType, showSolderingTipType, SettingsOptions::SolderingTipType, SettingsItemIndex::SolderingTipType, 5},
#endif /* TIP_TYPE_SUPPORT */
#ifdef PROFILE_SUPPORT
  /* Profile Phases */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhases), nullptr, displayProfilePhases, nullptr, SettingsOptions::ProfilePhases, SettingsItemIndex::ProfilePhases, 7},
  /* Profile Preheat Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePreheatTemp), setProfilePreheatTemp, displayProfilePreheatTemp, showProfileOptions, SettingsOptions::ProfilePreheatTemp, SettingsItemIndex::ProfilePreheatTemp, 5},
  /* Profile Preheat Speed */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePreheatSpeed), nullptr, displayProfilePreheatSpeed, showProfileOptions, SettingsOptions::ProfilePreheatSpeed, SettingsItemIndex::ProfilePreheatSpeed, 5},
  /* Phase 1 Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Temp), setProfilePhase1Temp, displayProfilePhase1Temp, showProfileOptions, SettingsOptions::ProfilePhase1Temp, SettingsItemIndex::ProfilePhase1Temp, 5},
  /* Phase 1 Duration */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Duration), nullptr, displayProfilePhase1Duration, showProfileOptions, SettingsOptions::ProfilePhase1Duration, SettingsItemIndex::ProfilePhase1Duration, 5},
  /* Phase 2 Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Temp), setProfilePhase2Temp, displayProfilePhase2Temp, showProfilePhase2Options, SettingsOptions::ProfilePhase1Temp, SettingsItemIndex::ProfilePhase2Temp, 5},
  /* Phase 2 Duration */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Duration), nullptr, displayProfilePhase2Duration, showProfilePhase2Options, SettingsOptions::ProfilePhase2Duration, SettingsItemIndex::ProfilePhase2Duration, 5},
  /* Phase 3 Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Temp), setProfilePhase3Temp, displayProfilePhase3Temp, showProfilePhase3Options, SettingsOptions::ProfilePhase1Temp, SettingsItemIndex::ProfilePhase3Temp, 5},
  /* Phase 3 Duration */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Duration), nullptr, displayProfilePhase3Duration, showProfilePhase3Options, SettingsOptions::ProfilePhase3Duration, SettingsItemIndex::ProfilePhase3Duration, 5},
  /* Phase 4 Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Temp), setProfilePhase4Temp, displayProfilePhase4Temp, showProfilePhase4Options, SettingsOptions::ProfilePhase1Temp, SettingsItemIndex::ProfilePhase4Temp, 5},
  /* Phase 4 Duration */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Duration), nullptr, displayProfilePhase4Duration, showProfilePhase4Options, SettingsOptions::ProfilePhase4Duration, SettingsItemIndex::ProfilePhase4Duration, 5},
  /* Phase 5 Temp */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Temp), setProfilePhase5Temp, displayProfilePhase5Temp, showProfilePhase5Options, SettingsOptions::ProfilePhase1Temp, SettingsItemIndex::ProfilePhase5Temp, 5},
  /* Phase 5 Duration */
  {SETTINGS_DESC(SettingsItemIndex::ProfilePhase1Duration), nullptr, displayProfilePhase5Duration, showProfilePhase5Options, SettingsOptions::ProfilePhase5Duration, SettingsItemIndex::ProfilePhase5Duration, 5},
  /* Profile Cooldown Speed */
  {SETTINGS_DESC(SettingsItemIndex::ProfileCooldownSpeed), nullptr, displayProfileCooldownSpeed, showProfileOptions, SettingsOptions::ProfileCooldownSpeed, SettingsItemIndex::ProfileCooldownSpeed, 5},
#endif /* PROFILE_SUPPORT */
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};

const menuitem PowerSavingMenu[] = {
  /*
   *  Motion Sensitivity
   *  -Sleep Temp
   *  -Sleep Time
   *  -Shutdown Time
   *  Hall Sensor Sensitivity
   */
  /* Motion Sensitivity */
  {SETTINGS_DESC(SettingsItemIndex::MotionSensitivity), nullptr, displaySensitivity, nullptr, SettingsOptions::Sensitivity, SettingsItemIndex::MotionSensitivity, 7},
#ifndef NO_SLEEP_MODE
  /* Sleep Temp */
  {SETTINGS_DESC(SettingsItemIndex::SleepTemperature), setSleepTemp, displaySleepTemp, showSleepOptions, SettingsOptions::SleepTemp, SettingsItemIndex::SleepTemperature, 5},
  /* Sleep Time */
  {SETTINGS_DESC(SettingsItemIndex::SleepTimeout), nullptr, displaySleepTime, showSleepOptions, SettingsOptions::SleepTime, SettingsItemIndex::SleepTimeout, 5},
#endif /* *not* NO_SLEEP_MODE */
  /* Shutdown Time */
  {SETTINGS_DESC(SettingsItemIndex::ShutdownTimeout), nullptr, displayShutdownTime, showSleepOptions, SettingsOptions::ShutdownTime, SettingsItemIndex::ShutdownTimeout, 5},
#ifdef HALL_SENSOR
  /* Hall Effect Sensitivity */
  {SETTINGS_DESC(SettingsItemIndex::HallEffSensitivity), nullptr, displayHallEffect, showHallEffect, SettingsOptions::HallEffectSensitivity, SettingsItemIndex::HallEffSensitivity, 7},
  /* Hall Effect Sleep Time */
  {SETTINGS_DESC(SettingsItemIndex::HallEffSleepTimeout), nullptr, displayHallEffectSleepTime, showHallEffect, SettingsOptions::HallEffectSleepTime, SettingsItemIndex::HallEffSleepTimeout, 5},
#endif /* HALL_SENSOR */
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};

const menuitem UIMenu[] = {
  /*
   *  Temperature Unit
   *  Display Orientation
   *  Cooldown Blink
   *  Scrolling Speed
   *  Swap Temp Change Buttons +/-
   *  Animation Speed
   *  -Animation Loop
   *  OLED Brightness
   *  Invert Screen
   *  Logo Timeout
   *  Detailed IDLE
   *  Detailed Soldering
   */
  /* Temperature units, this has to be the first element in the array to work with the logic in enterUIMenu() */
  {SETTINGS_DESC(SettingsItemIndex::TemperatureUnit), setTempF, displayTempF, nullptr, SettingsOptions::TemperatureInF, SettingsItemIndex::TemperatureUnit, 7},
#ifndef NO_DISPLAY_ROTATE
  /* Display Rotation */
  {SETTINGS_DESC(SettingsItemIndex::DisplayRotation), setDisplayRotation, displayDisplayRotation, nullptr, SettingsOptions::OrientationMode, SettingsItemIndex::DisplayRotation, 7},
#endif /* *not* NO_DISPLAY_ROTATE */
  /* Cooling blink warning */
  {SETTINGS_DESC(SettingsItemIndex::CooldownBlink), nullptr, displayCoolingBlinkEnabled, nullptr, SettingsOptions::CoolingTempBlink, SettingsItemIndex::CooldownBlink, 7},
  /* Scroll Speed for descriptions */
  {SETTINGS_DESC(SettingsItemIndex::ScrollingSpeed), nullptr, displayScrollSpeed, nullptr, SettingsOptions::DescriptionScrollSpeed, SettingsItemIndex::ScrollingSpeed, 7},
  /* Reverse Temp change buttons +/- */
  {SETTINGS_DESC(SettingsItemIndex::ReverseButtonTempChange), nullptr, displayReverseButtonTempChangeEnabled, nullptr, SettingsOptions::ReverseButtonTempChangeEnabled, SettingsItemIndex::ReverseButtonTempChange, 7},
  /* Reverse Settings menu buttons A/B */
  {SETTINGS_DESC(SettingsItemIndex::ReverseButtonSettings), nullptr, displayReverseButtonSettings, nullptr, SettingsOptions::ReverseButtonSettings, SettingsItemIndex::ReverseButtonSettings, 7},
  /* Animation Speed adjustment */
  {SETTINGS_DESC(SettingsItemIndex::AnimSpeed), nullptr, displayAnimationSpeed, nullptr, SettingsOptions::AnimationSpeed, SettingsItemIndex::AnimSpeed, 7},
  /* Animation Loop switch */
  {SETTINGS_DESC(SettingsItemIndex::AnimLoop), nullptr, displayAnimationLoop, displayAnimationOptions, SettingsOptions::AnimationLoop, SettingsItemIndex::AnimLoop, 7},
  /* Brightness Level */
  {SETTINGS_DESC(SettingsItemIndex::Brightness), nullptr, displayBrightnessLevel, nullptr, SettingsOptions::OLEDBrightness, SettingsItemIndex::Brightness, 7},
  /* Invert screen colour */
  {SETTINGS_DESC(SettingsItemIndex::ColourInversion), nullptr, displayInvertColor, nullptr, SettingsOptions::OLEDInversion, SettingsItemIndex::ColourInversion, 7},
  /* Set logo duration */
  {SETTINGS_DESC(SettingsItemIndex::LOGOTime), nullptr, displayLogoTime, nullptr, SettingsOptions::LOGOTime, SettingsItemIndex::LOGOTime, 6},
  /* Advanced idle screen */
  {SETTINGS_DESC(SettingsItemIndex::AdvancedIdle), nullptr, displayAdvancedIDLEScreens, nullptr, SettingsOptions::DetailedIDLE, SettingsItemIndex::AdvancedIdle, 7},
  /* Advanced soldering screen */
  {SETTINGS_DESC(SettingsItemIndex::AdvancedSoldering), nullptr, displayAdvancedSolderingScreens, nullptr, SettingsOptions::DetailedSoldering, SettingsItemIndex::AdvancedSoldering, 7},
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};

const menuitem advancedMenu[] = {
  /*
   *  BluetoothLE
   *  Power Limit
   *  Calibrate CJC At Next Boot
   *  Calibrate Input V
   *  Power Pulse
   *  -Power Pulse Delay
   *  -Power Pulse Duration
   *  Factory Reset
   */
#ifdef BLE_ENABLED
  /* Toggle BLE */
  {SETTINGS_DESC(SettingsItemIndex::BluetoothLE), nullptr, displayBluetoothLE, nullptr, SettingsOptions::BluetoothLE, SettingsItemIndex::BluetoothLE, 7},
#endif /* BLE_ENABLED */
  /* Power limit */
  {SETTINGS_DESC(SettingsItemIndex::PowerLimit), nullptr, displayPowerLimit, nullptr, SettingsOptions::PowerLimit, SettingsItemIndex::PowerLimit, 4},
  /* Calibrate Cold Junktion Compensation at next boot */
  {SETTINGS_DESC(SettingsItemIndex::CalibrateCJC), setCalibrate, displayCalibrate, nullptr, SettingsOptions::CalibrateCJC, SettingsItemIndex::CalibrateCJC, 7},
  /* Voltage input cal */
  {SETTINGS_DESC(SettingsItemIndex::VoltageCalibration), setCalibrateVIN, noOpDisplay, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::VoltageCalibration, 5},
  /* Power Pulse adjustment */
  {SETTINGS_DESC(SettingsItemIndex::PowerPulsePower), nullptr, displayPowerPulse, nullptr, SettingsOptions::KeepAwakePulse, SettingsItemIndex::PowerPulsePower, 5},
  /* Power Pulse Wait adjustment */
  {SETTINGS_DESC(SettingsItemIndex::PowerPulseWait), nullptr, displayPowerPulseWait, showPowerPulseOptions, SettingsOptions::KeepAwakePulseWait, SettingsItemIndex::PowerPulseWait, 7},
  /* Power Pulse Duration adjustment */
  {SETTINGS_DESC(SettingsItemIndex::PowerPulseDuration), nullptr, displayPowerPulseDuration, showPowerPulseOptions, SettingsOptions::KeepAwakePulseDuration, SettingsItemIndex::PowerPulseDuration, 7},
  /* Resets settings */
  {SETTINGS_DESC(SettingsItemIndex::SettingsReset), setResetSettings, noOpDisplay, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::SettingsReset, 7},
  /* vvvv end of menu marker. DO NOT REMOVE vvvv */
  {0, nullptr, nullptr, nullptr, SettingsOptions::SettingsOptionsLength, SettingsItemIndex::NUM_ITEMS, 0}
  /* ^^^^ end of menu marker. DO NOT REMOVE ^^^^ */
};

/* clang-format on */

const menuitem *subSettingsMenus[]{
#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
    powerMenu,
#endif
    solderingMenu, PowerSavingMenu, UIMenu, advancedMenu,
};
/* ^^^ !!!ENABLE CLANG-FORMAT back!!! ^^^ */

/**
 * Prints two small lines (or one line for CJK) of short description for
 * setting items and prepares cursor after it.
 * @param settingsItemIndex Index of the setting item.
 * @param cursorCharPosition Custom cursor char position to set after printing
 * description.
 */
static void printShortDescription(SettingsItemIndex settingsItemIndex, uint16_t cursorCharPosition) {
  // print short description (default single line, explicit double line)
  uint8_t shortDescIndex = static_cast(settingsItemIndex);
  OLED::printWholeScreen(translatedString(Tr->SettingsShortNames[shortDescIndex]));

  // prepare cursor for value
  // make room for scroll indicator
  OLED::setCursor(cursorCharPosition * FONT_12_WIDTH - 2, 0);
}

static int userConfirmation(const char *message) {
  TickType_t tickStart = xTaskGetTickCount();
  for (;;) {
    drawScrollingText(message, xTaskGetTickCount() - tickStart);

    ButtonState buttons = getButtonState();
    switch (buttons) {
    case BUTTON_F_SHORT:
      // User confirmed
      return 1;

    case BUTTON_NONE:
      break;
    default:
    case BUTTON_BOTH:
    case BUTTON_B_SHORT:
    case BUTTON_F_LONG:
    case BUTTON_B_LONG:
      return 0;
    }

    OLED::refresh();
    osDelay(40);
  }
  return 0;
}

#ifdef POW_DC

static void displayInputVRange(void) {
  if (getSettingValue(SettingsOptions::MinDCVoltageCells)) {
    OLED::printNumber(2 + getSettingValue(SettingsOptions::MinDCVoltageCells), 1, FontStyle::LARGE);
    OLED::print(LargeSymbolCellCount, FontStyle::LARGE);
  } else {
    OLED::print(LargeSymbolDC, FontStyle::LARGE);
  }
}

static bool showInputVOptions(void) { return getSettingValue(SettingsOptions::MinDCVoltageCells) > 0; }

static void displayInputMinVRange(void) {
  OLED::printNumber(getSettingValue(SettingsOptions::MinVoltageCells) / 10, 1, FontStyle::LARGE);
  OLED::print(LargeSymbolDot, FontStyle::LARGE);
  OLED::printNumber(getSettingValue(SettingsOptions::MinVoltageCells) % 10, 1, FontStyle::LARGE);
}

#endif /* POW_DC */

#ifdef POW_QC

static void displayQCInputV(void) {
  // These are only used in QC modes
  // Allows setting the voltage negotiated for QC
  auto voltage = getSettingValue(SettingsOptions::QCIdealVoltage);
  OLED::printNumber(voltage / 10, 2, FontStyle::LARGE);
  OLED::print(LargeSymbolDot, FontStyle::LARGE);
  OLED::printNumber(voltage % 10, 1, FontStyle::LARGE);
}

#endif /* POW_QC */

#ifdef POW_PD /* POW_PD */

static void displayPDNegTimeout(void) {
  auto value = getSettingValue(SettingsOptions::PDNegTimeout);
  value ? OLED::printNumber(value, 2, FontStyle::LARGE) : OLED::drawUnavailableIcon();
}

static void displayUSBPDMode(void) {
  /*
   * Supported PD modes:
   *  DEFAULT,    1 = PPS + EPR + more power request through increasing resistance by 0.5 Ohm to compensate power loss over cable/PCB/etc.
   *  SAFE,       2 = PPS + EPR, without requesting more power
   *  NO_DYNAMIC, 0 = PPS + EPR disabled, fixed PDO only
   */

  switch (getSettingValue(SettingsOptions::USBPDMode)) {
  case usbpdMode_t::DEFAULT:
    OLED::print(translatedString(Tr->USBPDModeDefault), FontStyle::SMALL, 255, OLED::getCursorX());
    break;
  case usbpdMode_t::SAFE:
    OLED::print(translatedString(Tr->USBPDModeSafe), FontStyle::SMALL, 255, OLED::getCursorX());
    break;
  case usbpdMode_t::NO_DYNAMIC:
  default:
    OLED::print(translatedString(Tr->USBPDModeNoDynamic), FontStyle::SMALL, 255, OLED::getCursorX());
    break;
  }
}

#endif /* POW_PD */

static void setBoostTemp(void) {
  uint16_t value = getSettingValue(SettingsOptions::BoostTemp);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    if (value == 0) {
      value = MIN_BOOST_TEMP_F; // loop back at 480
    } else {
      value += 20; // Go up 20F at a time
    }

    if (value >= MAX_TEMP_F) {
      value = 0; // jump to off
    }
  } else {
    if (value == 0) {
      value = MIN_BOOST_TEMP_C; // loop back at 250
    } else {
      value += 10; // Go up 10C at a time
    }
    if (value > MAX_TEMP_C) {
      value = 0; // Go to off state
    }
  }
  setSettingValue(SettingsOptions::BoostTemp, value);
}

static void displayBoostTemp(void) {
  if (getSettingValue(SettingsOptions::BoostTemp)) {
    OLED::printNumber(getSettingValue(SettingsOptions::BoostTemp), 3, FontStyle::LARGE);
  } else {
    OLED::drawUnavailableIcon();
  }
}

static void displayAutomaticStartMode(void) {
  switch (getSettingValue(SettingsOptions::AutoStartMode)) {
  case autoStartMode_t::NO:
    OLED::drawUnavailableIcon();
    break;
  case autoStartMode_t::SOLDER:
    OLED::print(translatedString(Tr->SettingStartSolderingChar), FontStyle::LARGE);
    break;
  case autoStartMode_t::SLEEP:
    OLED::print(translatedString(Tr->SettingStartSleepChar), FontStyle::LARGE);
    break;
  case autoStartMode_t::ZERO:
    OLED::print(translatedString(Tr->SettingStartSleepOffChar), FontStyle::LARGE);
    break;
  default:
    OLED::drawUnavailableIcon();
    break;
  }
}

static void displayTempChangeShortStep(void) { OLED::printNumber(getSettingValue(SettingsOptions::TempChangeShortStep), 2, FontStyle::LARGE); }

static void displayTempChangeLongStep(void) { OLED::printNumber(getSettingValue(SettingsOptions::TempChangeLongStep), 2, FontStyle::LARGE); }

static void displayLockingMode(void) {
  switch (getSettingValue(SettingsOptions::LockingMode)) {
  case lockingMode_t::DISABLED:
    OLED::drawUnavailableIcon();
    break;
  case lockingMode_t::BOOST:
    OLED::print(translatedString(Tr->SettingLockBoostChar), FontStyle::LARGE);
    break;
  case lockingMode_t::FULL:
    OLED::print(translatedString(Tr->SettingLockFullChar), FontStyle::LARGE);
    break;
  default:
    OLED::drawUnavailableIcon();
    break;
  }
}

#ifdef PROFILE_SUPPORT

static void displayProfilePhases(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhases), 1, FontStyle::LARGE); }

static void setProfileTemp(const enum SettingsOptions option) {
  // If in C, 5 deg, if in F 10 deg
  uint16_t temp = getSettingValue(option);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    temp += 10;
    if (temp > MAX_TEMP_F) {
      temp = MIN_TEMP_F;
    }
  } else {
    temp += 5;
    if (temp > MAX_TEMP_C) {
      temp = MIN_TEMP_C;
    }
  }
  setSettingValue(option, temp);
}

static void setProfilePreheatTemp(void) { return setProfileTemp(SettingsOptions::ProfilePreheatTemp); }
static void setProfilePhase1Temp(void) { return setProfileTemp(SettingsOptions::ProfilePhase1Temp); }
static void setProfilePhase2Temp(void) { return setProfileTemp(SettingsOptions::ProfilePhase2Temp); }
static void setProfilePhase3Temp(void) { return setProfileTemp(SettingsOptions::ProfilePhase3Temp); }
static void setProfilePhase4Temp(void) { return setProfileTemp(SettingsOptions::ProfilePhase4Temp); }
static void setProfilePhase5Temp(void) { return setProfileTemp(SettingsOptions::ProfilePhase5Temp); }

static void displayProfilePreheatTemp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePreheatTemp), 3, FontStyle::LARGE); }
static void displayProfilePhase1Temp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase1Temp), 3, FontStyle::LARGE); }
static void displayProfilePhase2Temp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase2Temp), 3, FontStyle::LARGE); }
static void displayProfilePhase3Temp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase3Temp), 3, FontStyle::LARGE); }
static void displayProfilePhase4Temp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase4Temp), 3, FontStyle::LARGE); }
static void displayProfilePhase5Temp(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase5Temp), 3, FontStyle::LARGE); }
static void displayProfilePreheatSpeed(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePreheatSpeed), 2, FontStyle::LARGE); }
static void displayProfileCooldownSpeed(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfileCooldownSpeed), 2, FontStyle::LARGE); }
static void displayProfilePhase1Duration(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase1Duration), 3, FontStyle::LARGE); }
static void displayProfilePhase2Duration(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase2Duration), 3, FontStyle::LARGE); }
static void displayProfilePhase3Duration(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase3Duration), 3, FontStyle::LARGE); }
static void displayProfilePhase4Duration(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase4Duration), 3, FontStyle::LARGE); }
static void displayProfilePhase5Duration(void) { OLED::printNumber(getSettingValue(SettingsOptions::ProfilePhase5Duration), 3, FontStyle::LARGE); }

static bool showProfileOptions(void) { return getSettingValue(SettingsOptions::ProfilePhases); }
static bool showProfilePhase2Options(void) { return getSettingValue(SettingsOptions::ProfilePhases) >= 2; }
static bool showProfilePhase3Options(void) { return getSettingValue(SettingsOptions::ProfilePhases) >= 3; }
static bool showProfilePhase4Options(void) { return getSettingValue(SettingsOptions::ProfilePhases) >= 4; }
static bool showProfilePhase5Options(void) { return getSettingValue(SettingsOptions::ProfilePhases) >= 5; }

#endif /* PROFILE_SUPPORT */

static void displaySensitivity(void) {
  if (getSettingValue(SettingsOptions::Sensitivity)) {
    OLED::printNumber(getSettingValue(SettingsOptions::Sensitivity), 1, FontStyle::LARGE, false);
  } else {
    OLED::drawUnavailableIcon();
  }
}
static bool showSleepOptions(void) { return getSettingValue(SettingsOptions::Sensitivity) > 0; }

#ifndef NO_SLEEP_MODE

static void setSleepTemp(void) {
  // If in C, 10 deg, if in F 20 deg
  uint16_t temp = getSettingValue(SettingsOptions::SleepTemp);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    temp += 20;
    if (temp > 580) {
      temp = 60;
    }
  } else {
    temp += 10;
    if (temp > 300) {
      temp = 10;
    }
  }
  setSettingValue(SettingsOptions::SleepTemp, temp);
}

static void displaySleepTemp(void) { OLED::printNumber(getSettingValue(SettingsOptions::SleepTemp), 3, FontStyle::LARGE); }

static void displaySleepTime(void) {
  if (getSettingValue(SettingsOptions::SleepTime) == 0) {
    OLED::drawUnavailableIcon();
  } else if (getSettingValue(SettingsOptions::SleepTime) < 6) {
    OLED::printNumber(getSettingValue(SettingsOptions::SleepTime) * 10, 2, FontStyle::LARGE);
    OLED::print(LargeSymbolSeconds, FontStyle::LARGE);
  } else {
    OLED::printNumber(getSettingValue(SettingsOptions::SleepTime) - 5, 2, FontStyle::LARGE);
    OLED::print(LargeSymbolMinutes, FontStyle::LARGE);
  }
}

#endif /* *not* NO_SLEEP_MODE */

static void displayShutdownTime(void) {
  if (getSettingValue(SettingsOptions::ShutdownTime) == 0) {
    OLED::drawUnavailableIcon();
  } else {
    OLED::printNumber(getSettingValue(SettingsOptions::ShutdownTime), 2, FontStyle::LARGE);
    OLED::print(LargeSymbolMinutes, FontStyle::LARGE);
  }
}

#ifdef HALL_SENSOR
static void displayHallEffect(void) {
  if (getSettingValue(SettingsOptions::HallEffectSensitivity)) {
    OLED::printNumber(getSettingValue(SettingsOptions::HallEffectSensitivity), 1, FontStyle::LARGE, false);
  } else {
    OLED::drawUnavailableIcon();
  }
}
static bool showHallEffect(void) { return getHallSensorFitted(); }
static void displayHallEffectSleepTime(void) {
  if (getSettingValue(SettingsOptions::HallEffectSleepTime)) {
    OLED::printNumber(getSettingValue(SettingsOptions::HallEffectSleepTime) * 5, 2, FontStyle::LARGE, false);
  } else {
    // When sleep time is set to zero, we sleep for 1 second anyways. This is the default.
    OLED::printNumber(1, 2, FontStyle::LARGE, false);
  }
  OLED::print(LargeSymbolSeconds, FontStyle::LARGE);
}
#endif /* HALL_SENSOR */

#ifdef TIP_TYPE_SUPPORT
static void displaySolderingTipType(void) {
  // TODO wrapping X value
  OLED::print(lookupTipName(), FontStyle::SMALL, 255, OLED::getCursorX());
}
// If there is no detection, and no options, max is 0
static bool showSolderingTipType(void) { return tipType_t::TIP_TYPE_MAX != 0; }
#endif /* TIP_TYPE_SUPPORT */

static void setTempF(const enum SettingsOptions option) {
  uint16_t Temp = getSettingValue(option);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    // Change temp to the F equiv
    // C to F == F= ( (C*9) +160)/5
    Temp = ((Temp * 9) + 160) / 5;
  } else {
    // Change temp to the C equiv
    // F->C == C = ((F-32)*5)/9
    Temp = ((Temp - 32) * 5) / 9;
  }
  // Rescale to be multiples of 10
  Temp = Temp / 10;
  Temp *= 10;
  setSettingValue(option, Temp);
}

static void setTempF(void) {
  nextSettingValue(SettingsOptions::TemperatureInF);
  setTempF(SettingsOptions::BoostTemp);
  setTempF(SettingsOptions::SolderingTemp);
#ifndef NO_SLEEP_MODE
  setTempF(SettingsOptions::SleepTemp);
#endif /* *not* NO_SLEEP_MODE */
#ifdef PROFILE_SUPPORT
  setTempF(SettingsOptions::ProfilePreheatTemp);
  setTempF(SettingsOptions::ProfilePhase1Temp);
  setTempF(SettingsOptions::ProfilePhase2Temp);
  setTempF(SettingsOptions::ProfilePhase3Temp);
  setTempF(SettingsOptions::ProfilePhase4Temp);
  setTempF(SettingsOptions::ProfilePhase5Temp);
#endif /* PROFILE_SUPPORT */
}

static void displayTempF(void) { OLED::printSymbolDeg(FontStyle::LARGE); }

#ifndef NO_DISPLAY_ROTATE

static void setDisplayRotation(void) {
  nextSettingValue(SettingsOptions::OrientationMode);
  switch (getSettingValue(SettingsOptions::OrientationMode)) {
  case orientationMode_t::RIGHT:
    OLED::setRotation(false);
    break;
  case orientationMode_t::LEFT:
    OLED::setRotation(true);
    break;
  case orientationMode_t::AUTO:
    // do nothing on auto
    break;
  default:
    break;
  }
}

static void displayDisplayRotation(void) {
  switch (getSettingValue(SettingsOptions::OrientationMode)) {
  case orientationMode_t::RIGHT:
    OLED::print(translatedString(Tr->SettingRightChar), FontStyle::LARGE);
    break;
  case orientationMode_t::LEFT:
    OLED::print(translatedString(Tr->SettingLeftChar), FontStyle::LARGE);
    break;
  case orientationMode_t::AUTO:
    OLED::print(translatedString(Tr->SettingAutoChar), FontStyle::LARGE);
    break;
  default:
    OLED::print(translatedString(Tr->SettingRightChar), FontStyle::LARGE);
    break;
  }
}

#endif /* NO_DISPLAY_ROTATE */

static void displayCoolingBlinkEnabled(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::CoolingTempBlink)); }

static void displayScrollSpeed(void) { OLED::print(translatedString((getSettingValue(SettingsOptions::DescriptionScrollSpeed)) ? Tr->SettingFastChar : Tr->SettingSlowChar), FontStyle::LARGE); }

static void displayReverseButtonTempChangeEnabled(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled)); }

static void displayReverseButtonSettings(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::ReverseButtonSettings)); }

static void displayAnimationSpeed(void) {
  switch (getSettingValue(SettingsOptions::AnimationSpeed)) {
  case settingOffSpeed_t::SLOW:
    OLED::print(translatedString(Tr->SettingSlowChar), FontStyle::LARGE);
    break;
  case settingOffSpeed_t::MEDIUM:
    OLED::print(translatedString(Tr->SettingMediumChar), FontStyle::LARGE);
    break;
  case settingOffSpeed_t::FAST:
    OLED::print(translatedString(Tr->SettingFastChar), FontStyle::LARGE);
    break;
  default:
    OLED::drawUnavailableIcon();
    break;
  }
}

static bool displayAnimationOptions(void) { return getSettingValue(SettingsOptions::AnimationSpeed) > 0; }
static void displayAnimationLoop(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::AnimationLoop)); }

static void displayBrightnessLevel(void) {
  OLED::printNumber((getSettingValue(SettingsOptions::OLEDBrightness) / BRIGHTNESS_STEP + 1), 1, FontStyle::LARGE);
  // While not optimal to apply this here, it is _very_ convenient
  OLED::setBrightness(getSettingValue(SettingsOptions::OLEDBrightness));
}

static void displayInvertColor(void) {
  OLED::drawCheckbox(getSettingValue(SettingsOptions::OLEDInversion));
  // While not optimal to apply this here, it is _very_ convenient
  OLED::setInverseDisplay(getSettingValue(SettingsOptions::OLEDInversion));
}

static void displayLogoTime(void) {
  switch (getSettingValue(SettingsOptions::LOGOTime)) {
  case logoMode_t::SKIP:
    OLED::drawUnavailableIcon();
    break;
  case logoMode_t::ONETIME:
    OLED::drawArea(OLED_WIDTH - OLED_HEIGHT - 2, 0, OLED_HEIGHT, OLED_HEIGHT, RepeatOnce);
    break;
  case logoMode_t::INFINITY:
    OLED::drawArea(OLED_WIDTH - OLED_HEIGHT - 2, 0, OLED_HEIGHT, OLED_HEIGHT, RepeatInf);
    break;
  default:
    OLED::printNumber(getSettingValue(SettingsOptions::LOGOTime), 1, FontStyle::LARGE);
    OLED::print(LargeSymbolSeconds, FontStyle::LARGE);
    break;
  }
}

static void displayAdvancedIDLEScreens(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedIDLE)); }

static void displayAdvancedSolderingScreens(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::DetailedSoldering)); }

#ifdef BLE_ENABLED
static void displayBluetoothLE(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::BluetoothLE)); }
#endif /* BLE_ENABLED */

static void displayPowerLimit(void) {
  if (getSettingValue(SettingsOptions::PowerLimit) == 0) {
    OLED::drawUnavailableIcon();
  } else {
    OLED::printNumber(getSettingValue(SettingsOptions::PowerLimit), 3, FontStyle::LARGE);
    OLED::print(LargeSymbolWatts, FontStyle::LARGE);
  }
}

static void setCalibrate(void) {
  if (getSettingValue(SettingsOptions::CalibrateCJC) < 1) {
    if (userConfirmation(translatedString(Tr->SettingsCalibrationWarning))) {
      // User confirmed
      // So we now set the tick
      setSettingValue(SettingsOptions::CalibrateCJC, 1);
    }
  } else {
    setSettingValue(SettingsOptions::CalibrateCJC, 0);
  }
}

static void displayCalibrate(void) { OLED::drawCheckbox(getSettingValue(SettingsOptions::CalibrateCJC)); }

static void setCalibrateVIN(void) {
  // Jump to the voltage calibration subscreen
  OLED::clearScreen();

  for (;;) {
    OLED::setCursor(25, 0);
    uint16_t voltage = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    OLED::printNumber(voltage / 10, 2, FontStyle::LARGE);
    OLED::print(LargeSymbolDot, FontStyle::LARGE);
    OLED::printNumber(voltage % 10, 1, FontStyle::LARGE, false);
    OLED::print(LargeSymbolVolts, FontStyle::LARGE);
    OLED::setCursor(0, 8);
    OLED::printNumber(getSettingValue(SettingsOptions::VoltageDiv), 3, FontStyle::SMALL);

    switch (getButtonState()) {
    case BUTTON_F_SHORT:
      prevSettingValue(SettingsOptions::VoltageDiv);
      break;
    case BUTTON_B_SHORT:
      nextSettingValue(SettingsOptions::VoltageDiv);
      break;
    case BUTTON_BOTH:
    case BUTTON_F_LONG:
    case BUTTON_B_LONG:
      saveSettings();
      OLED::clearScreen();
      OLED::setCursor(0, 0);
      warnUser(translatedString(Tr->CalibrationDone), getButtonState());
      OLED::refresh();
      waitForButtonPressOrTimeout(0.5 * TICKS_SECOND);
      return;
    case BUTTON_NONE:
    default:
      break;
    }

    OLED::refresh();
    osDelay(40);
  }
}

static void displayPowerPulse(void) {
  if (getSettingValue(SettingsOptions::KeepAwakePulse)) {
    OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulse) / 10, 1, FontStyle::LARGE);
    OLED::print(LargeSymbolDot, FontStyle::LARGE);
    OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulse) % 10, 1, FontStyle::LARGE);
  } else {
    OLED::drawUnavailableIcon();
  }
}

static bool showPowerPulseOptions(void) { return getSettingValue(SettingsOptions::KeepAwakePulse) > 0; }

static void displayPowerPulseWait(void) { OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseWait), 1, FontStyle::LARGE); }

static void displayPowerPulseDuration(void) { OLED::printNumber(getSettingValue(SettingsOptions::KeepAwakePulseDuration), 1, FontStyle::LARGE); }

static void setResetSettings(void) {
  if (userConfirmation(translatedString(Tr->SettingsResetWarning))) {
    resetSettings();
    OLED::clearScreen();
    while (!warnUser(translatedString(Tr->ResetOKMessage), getButtonState())) {
      OLED::refresh();
      vTaskDelay(TICKS_100MS);
      OLED::clearScreen();
    }
    reboot();
  }
}

// Indicates whether a menu transition is in progress, so that the menu icon
// animation is paused during the transition.
static bool animOpenState = false;

static void displayMenu(size_t index) {
  // Call into the menu
  // Draw title
  OLED::printWholeScreen(translatedString(Tr->SettingsMenuEntries[index]));
  static TickType_t menuSwitchLoopTick = 0;
  static size_t     menuCurrentIndex   = sizeof(rootSettingsMenu) + 1;
  TickType_t        step               = TICKS_100MS * 5;
  switch (getSettingValue(SettingsOptions::AnimationSpeed)) {
  case settingOffSpeed_t::FAST:
    step = TICKS_100MS * 3;
    break;
  case settingOffSpeed_t::MEDIUM:
    step = TICKS_100MS * 4;
    break;
  default: // SLOW or off - defaulted above
    break;
  }
  size_t currentFrame;
  if (!animOpenState && (getSettingValue(SettingsOptions::AnimationSpeed) != settingOffSpeed_t::OFF)) {
    if (menuCurrentIndex != index) {
      menuCurrentIndex   = index;
      menuSwitchLoopTick = xTaskGetTickCount();
    }
    currentFrame = ((xTaskGetTickCount() - menuSwitchLoopTick) / step);
    if (getSettingValue(SettingsOptions::AnimationLoop)) {
      currentFrame %= 3;
    } else if (currentFrame > 2) {
      currentFrame = 2;
    }
  } else {
    // We want the animation to restart after completing the transition.
    menuCurrentIndex = sizeof(rootSettingsMenu) + 1;
    // Always draw the last frame if icon animation is disabled.
    currentFrame = getSettingValue(SettingsOptions::AnimationSpeed) == settingOffSpeed_t::OFF ? 2 : 0;
  }
  // Draw symbol
  // 16 pixel wide image
  // less 2 pixel wide scrolling indicator

  OLED::drawArea(OLED_WIDTH - SETTINGS_ICON_WIDTH - 2, 0, SETTINGS_ICON_WIDTH, SETTINGS_ICON_HEIGHT, (&SettingsMenuIcons[index][(SETTINGS_ICON_WIDTH * (SETTINGS_ICON_HEIGHT / 8)) * currentFrame]));
}

#if defined(POW_DC) || defined(POW_QC) || defined(POW_PD)
static void displayPowerMenu(void) { displayMenu(0); }

#endif /* POW_DC or POW_QC */

static void displaySolderingMenu(void) { displayMenu(1); }

static void displayPowerSavingMenu(void) { displayMenu(2); }

static void displayUIMenu(void) { displayMenu(3); }

static void displayAdvancedMenu(void) { displayMenu(4); }


================================================
FILE: source/Core/Src/syscalls.c
================================================
/* Includes */
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 

/* Functions */
void initialise_monitor_handles() {}

/* Syscalls (stub implementations to avoid compile warnings and possibe future problems) */
int _getpid(void) { return 1; }

#if defined(MODEL_Pinecil) || defined(MODEL_Pinecilv2)
// do nothing here because some stubs and real implementations added for Pinecils already
#else
off_t   _lseek(int fd, off_t ptr, int dir) { return -1; }
ssize_t _read(int fd, void *ptr, size_t len) { return -1; }
ssize_t _write(int fd, const void *ptr, size_t len) { return -1; }
int     _close(int fd) { return -1; }
#endif


================================================
FILE: source/Core/Threads/GUIRendering.md
================================================
# GUI Rendering

The GUI aims to be somewhat similar to immediate mode rendering, where the screen is re-rendered each sweep.
This is due to a few aims:

1. Functions should try and contain their state to the context struct (helps keep state usage flatter)
2. Allows external events to change the state
3. Means state can be read/write over BLE or other external control interfaces

## Transitions

When changing the view to a new view it can be preferable to transition using an animation.
The tooling provides for left, right and down animations at this point.
The use of these gives a notion of "direction" when navigating the menu.

```
                          ┌───────────┐
                          │ Debug Menu│
                          └─────┬─────┘
                                │
                                │
                                │
┌──────────────┐           ┌────┴─────┐           ┌──────────────────┐           ┌─────────────────┐
│Soldering Mode│           │          │           │                  │           │                 │
│      OR      ├───────────┤Home Menu ├───────────┤Settings Main Menu├───────────┤Settings sub menu│
│Reflow    Mode│           │          │           │                  │           │                 │
└──────────────┘           └──────────┘           └──────────────────┘           └─────────┬───────┘
                                                                                           │
                                                                                 ┌─────────┴───────┐
                                                                                 │                 │
                                                                                 │Settings sub menu│
                                                                                 │                 │
                                                                                 └─────────────────┘
```

The downside of supporting transitions is that for these to work, the code should render the screen _first_ then return the new state.
This ensures there is a good working copy in the buffer before the transition changes the view.

The code that handles the dispatch will run a new render pass again to get the new buffer contents and then transition between the two for you.
At the moment scrolling "Up" isn't implemented but the enumeration is there so that its implementation can follow.


================================================
FILE: source/Core/Threads/GUIThread.cpp
================================================
/*
 * GUIThread.cpp
 *
 *  Created on: 19 Aug 2019
 *      Author: ralim
 */
extern "C" {
#include "FreeRTOSConfig.h"
}
#include "BootLogo.h"
#include "Buttons.hpp"
#include "I2CBB2.hpp"
#include "LIS2DH12.hpp"
#include "MMA8652FC.hpp"
#include "OLED.hpp"
#include "OperatingModeUtilities.h"
#include "OperatingModes.h"
#include "Settings.h"
#include "TipThermoModel.h"
#include "Translation.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "history.hpp"
#include "main.hpp"
#include "power.hpp"
#include "settingsGUI.hpp"
#include "stdlib.h"
#include "string.h"
#include "ui_drawing.hpp"
#ifdef POW_PD
#include "USBPD.h"
#include "pd.h"
#endif

// File local variables
#define MOVEMENT_INACTIVITY_TIME (60 * configTICK_RATE_HZ)
#define BUTTON_INACTIVITY_TIME   (60 * configTICK_RATE_HZ)

ButtonState   buttonsAtDeviceBoot;                                      // We record button state at startup, incase of jumping to debug modes
OperatingMode currentOperatingMode = OperatingMode::InitialisationDone; // Current mode we are rendering
guiContext    context;                                                  // Context passed to functions to aid in state during render passes

OperatingMode handle_post_init_state();
OperatingMode guiHandleDraw(void) {
  OLED::clearScreen(); // Clear ready for render pass
  // Read button state
  ButtonState buttons = getButtonState();
  // Enforce screen on if buttons pressed, movement, hot tip etc
  if (buttons != BUTTON_NONE) {
    OLED::setDisplayState(OLED::DisplayState::ON);
  } else {
    // Buttons are none; check if we can sleep display
    uint32_t tipTemp = TipThermoModel::getTipInC();
    if ((tipTemp < 50) && getSettingValue(SettingsOptions::Sensitivity) &&
        (((xTaskGetTickCount() - lastMovementTime) > MOVEMENT_INACTIVITY_TIME) && ((xTaskGetTickCount() - lastButtonTime) > BUTTON_INACTIVITY_TIME))) {
      OLED::setDisplayState(OLED::DisplayState::OFF);
      setStatusLED(LED_OFF);
    } else {
      OLED::setDisplayState(OLED::DisplayState::ON);
    }
    if (currentOperatingMode != OperatingMode::Soldering && currentOperatingMode != OperatingMode::SolderingProfile) {
      // Not in soldering mode, so set this based on temp
      if (tipTemp > 55) {
        setStatusLED(LED_COOLING_STILL_HOT);
      } else {
        setStatusLED(LED_STANDBY);
      }
    }
  }
  // Dispatch button state to gui mode
  OperatingMode newMode = currentOperatingMode;
  switch (currentOperatingMode) {
  case OperatingMode::StartupWarnings:
    newMode = showWarnings(buttons, &context);
    break;
  case OperatingMode::UsbPDDebug:
#ifdef HAS_POWER_DEBUG_MENU
    newMode = showPDDebug(buttons, &context);
    break;
#else
    newMode = OperatingMode::InitialisationDone;
#endif
  case OperatingMode::StartupLogo:
    showBootLogo();

    if (getSettingValue(SettingsOptions::AutoStartMode) == autoStartMode_t::SLEEP) {
      lastMovementTime = lastButtonTime = 0; // We mask the values so that sleep goes until user moves again or presses a button
      newMode                           = OperatingMode::Sleeping;
    } else if (getSettingValue(SettingsOptions::AutoStartMode) == autoStartMode_t::SOLDER) {
      lastMovementTime = lastButtonTime = xTaskGetTickCount(); // Move forward so we dont go to sleep
      newMode                           = OperatingMode::Soldering;
    } else if (getSettingValue(SettingsOptions::AutoStartMode) == autoStartMode_t::ZERO) {
      lastMovementTime = lastButtonTime = 0; // We mask the values so that sleep goes until user moves again or presses a button
      newMode                           = OperatingMode::Hibernating;
    } else {
      newMode = OperatingMode::HomeScreen;
    }

    break;
  default:
    /* Fallthrough */
  case OperatingMode::HomeScreen:
    newMode = drawHomeScreen(buttons, &context);
    break;
  case OperatingMode::Soldering:
    context.scratch_state.state4 = 0;
    newMode                      = gui_solderingMode(buttons, &context);
    break;
  case OperatingMode::SolderingProfile:
    newMode = gui_solderingProfileMode(buttons, &context);
    break;
  case OperatingMode::Sleeping:
    newMode = gui_SolderingSleepingMode(buttons, &context);
    break;
  case OperatingMode::TemperatureAdjust:
    newMode = gui_solderingTempAdjust(buttons, &context);
    break;
  case OperatingMode::DebugMenuReadout:
    newMode = showDebugMenu(buttons, &context);
    break;
  case OperatingMode::CJCCalibration:
    newMode = performCJCC(buttons, &context);
    break;
  case OperatingMode::SettingsMenu:
    newMode = gui_SettingsMenu(buttons, &context);
    break;
  case OperatingMode::InitialisationDone:
    newMode = handle_post_init_state();
    break;
  case OperatingMode::Hibernating:
    context.scratch_state.state4 = 1;
    gui_SolderingSleepingMode(buttons, &context);
    if (lastButtonTime > 0 || lastMovementTime > 0) {
      newMode = OperatingMode::Soldering;
    }
    break;
  case OperatingMode::ThermalRunaway:
    /*TODO*/
    newMode = OperatingMode::HomeScreen;
    break;
  };
  return newMode;
}
void guiRenderLoop(void) {
  OperatingMode newMode = guiHandleDraw(); // This does the screen drawing

  // Post draw we handle any state transitions

  if (newMode != currentOperatingMode) {
    context.viewEnterTime = xTaskGetTickCount();
    context.previousMode  = currentOperatingMode;
    // If the previous mode is the startup logo; we dont want to return to it, but instead dispatch out to either home or soldering
    if (currentOperatingMode == OperatingMode::StartupLogo) {
      if (getSettingValue(SettingsOptions::AutoStartMode)) {
        context.previousMode = OperatingMode::Soldering;
      } else {
        newMode = OperatingMode::HomeScreen;
      }
    }
    memset(&context.scratch_state, 0, sizeof(context.scratch_state));
    currentOperatingMode = newMode;
  }

  // If the transition marker is set, we need to make the next draw occur to the secondary buffer so we have something to transition to
  if (context.transitionMode != TransitionAnimation::None) {
    OLED::useSecondaryFramebuffer(true);
    // Now we need to fill the secondary buffer with the _next_ frame to transistion to
    guiHandleDraw();
    OLED::useSecondaryFramebuffer(false);
    // Now dispatch the transition
    switch (context.transitionMode) {
    case TransitionAnimation::Down:
      OLED::transitionScrollDown(context.viewEnterTime);
      break;
    case TransitionAnimation::Left:
      OLED::transitionSecondaryFramebuffer(false, context.viewEnterTime);
      break;
    case TransitionAnimation::Right:
      OLED::transitionSecondaryFramebuffer(true, context.viewEnterTime);
      break;
    case TransitionAnimation::Up:
      OLED::transitionScrollUp(context.viewEnterTime);

    case TransitionAnimation::None:
    default:
      break; // Do nothing on unknown
    }

    context.transitionMode = TransitionAnimation::None; // Clear transition flag
  }
  // Render done, draw it out
  OLED::refresh();
}

OperatingMode handle_post_init_state() {
#ifdef HAS_POWER_DEBUG_MENU
#ifdef DEBUG_POWER_MENU_BUTTON_B
  if (buttonsAtDeviceBoot == BUTTON_B_LONG || buttonsAtDeviceBoot == BUTTON_B_SHORT) {
#else
  if (buttonsAtDeviceBoot == BUTTON_F_LONG || buttonsAtDeviceBoot == BUTTON_F_SHORT) {
#endif
    buttonsAtDeviceBoot = BUTTON_NONE;
    return OperatingMode::UsbPDDebug;
  }
#endif

  if (getSettingValue(SettingsOptions::CalibrateCJC) > 0) {
    return OperatingMode::CJCCalibration;
  }

  return OperatingMode::StartupWarnings;
}

/* StartGUITask function */
void startGUITask(void const *argument) {
  (void)argument;
  prepareTranslations();

  OLED::initialize(); // start up the LCD
  OLED::setBrightness(getSettingValue(SettingsOptions::OLEDBrightness));
  OLED::setInverseDisplay(getSettingValue(SettingsOptions::OLEDInversion));

  bool buttonLockout = false;
  ui_pre_render_assets();
  getTipRawTemp(1); // reset filter
  memset(&context, 0, sizeof(context));

  OLED::setRotation(getSettingValue(SettingsOptions::OrientationMode) & 1);

  // Read boot button state
  if (getButtonA()) {
    buttonsAtDeviceBoot = BUTTON_F_LONG;
  }
  if (getButtonB()) {
    buttonsAtDeviceBoot = BUTTON_B_LONG;
  }

  TickType_t startRender = xTaskGetTickCount();
  for (;;) {
    guiRenderLoop();
    resetWatchdog();
    vTaskDelayUntil(&startRender, TICKS_100MS * 4 / 10); // Try and maintain 20-25fps ish update rate, way to fast but if we can its nice
  }
}


================================================
FILE: source/Core/Threads/MOVThread.cpp
================================================
/*
 * MOVThread.cpp
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BMA223.hpp"
#include "BSP.h"
#include "FreeRTOS.h"
#include "I2C_Wrapper.hpp"
#include "LIS2DH12.hpp"
#include "MMA8652FC.hpp"
#include "MSA301.h"
#include "Pins.h"
#include "QC3.h"
#include "SC7A20.hpp"
#include "Settings.h"
#include "TipThermoModel.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "history.hpp"
#include "main.hpp"
#include "power.hpp"
#include "stdlib.h"
#include "task.h"

#define MOVFilter 8
uint8_t    accelInit        = 0;
TickType_t lastMovementTime = 0;
// Order matters for probe order, some Acceleromters do NOT like bad reads; and we have a bunch of overlap of addresses
void detectAccelerometerVersion() {
#ifdef ACCEL_MMA
  if (MMA8652FC::detect()) {
    if (MMA8652FC::initalize()) {
      DetectedAccelerometerVersion = AccelType::MMA;
      return;
    }
  }
#endif
#ifdef ACCEL_LIS
  if (LIS2DH12::detect()) {
    // Setup the ST Accelerometer
    if (LIS2DH12::initalize()) {
      if (LIS2DH12::isClone()) {
        DetectedAccelerometerVersion = AccelType::LIS_CLONE;
      } else {
        DetectedAccelerometerVersion = AccelType::LIS;
      }
      return;
    }
  }
#endif
#ifdef ACCEL_BMA
  if (BMA223::detect()) {
    // Setup the BMA223 Accelerometer
    if (BMA223::initalize()) {
      DetectedAccelerometerVersion = AccelType::BMA;
      return;
    }
  }
#endif
#ifdef ACCEL_SC7
  if (SC7A20::detect()) {
    // Setup the SC7A20 Accelerometer
    if (SC7A20::initalize()) {
      DetectedAccelerometerVersion = AccelType::SC7;
      return;
    }
  }
#endif
#ifdef ACCEL_MSA
  if (MSA301::detect()) {
    // Setup the MSA301 Accelerometer
    if (MSA301::initalize()) {
      DetectedAccelerometerVersion = AccelType::MSA;
      return;
    }
  }
#endif
#ifdef GPIO_VIBRATION
  if (true) {
    DetectedAccelerometerVersion = AccelType::GPIO;
    return;
  }
#endif
  {
    // disable imu sensitivity
    setSettingValue(SettingsOptions::Sensitivity, 0);
    DetectedAccelerometerVersion = AccelType::None;
  }
}
inline void readAccelerometer(int16_t &tx, int16_t &ty, int16_t &tz, Orientation &rotation) {
#ifdef ACCEL_MMA
  if (DetectedAccelerometerVersion == AccelType::MMA) {
    MMA8652FC::getAxisReadings(tx, ty, tz);
    rotation = MMA8652FC::getOrientation();
  } else
#endif
#ifdef ACCEL_LIS
      if (DetectedAccelerometerVersion == AccelType::LIS || DetectedAccelerometerVersion == AccelType::LIS_CLONE) {
    LIS2DH12::getAxisReadings(tx, ty, tz);
    rotation = LIS2DH12::getOrientation();
  } else
#endif
#ifdef ACCEL_BMA
      if (DetectedAccelerometerVersion == AccelType::BMA) {
    BMA223::getAxisReadings(tx, ty, tz);
    rotation = BMA223::getOrientation();
  } else
#endif
#ifdef ACCEL_MSA
      if (DetectedAccelerometerVersion == AccelType::MSA) {
    MSA301::getAxisReadings(tx, ty, tz);
    rotation = MSA301::getOrientation();
  } else
#endif
#ifdef ACCEL_SC7
      if (DetectedAccelerometerVersion == AccelType::SC7) {
    SC7A20::getAxisReadings(tx, ty, tz);
    rotation = SC7A20::getOrientation();
  } else
#endif
#ifdef GPIO_VIBRATION
      if (DetectedAccelerometerVersion == AccelType::GPIO) {
    // TODO
    if (HAL_GPIO_ReadPin(MOVEMENT_GPIO_Port, MOVEMENT_Pin) == GPIO_PIN_SET) {
      // Movement
      tx = ty = tz = 5000;
    } else {
      // No Movement
      tx = ty = tz = 0;
    }
    rotation = Orientation::ORIENTATION_FLAT;
  } else
#endif
  {
    // do nothing :(
  }
}
void startMOVTask(void const *argument __unused) {
#ifdef NO_ACCEL
  DetectedAccelerometerVersion = AccelType::None;
  for (;;) {
    osDelay(2 * TICKS_SECOND);
  }
#endif

  osDelay(TICKS_100MS / 5); // This is here as the BMA doesnt start up instantly and can wedge the I2C bus if probed too fast after boot
  detectAccelerometerVersion();
  osDelay(TICKS_100MS / 2); // wait ~50ms for setup of accel to finalise
  lastMovementTime = 0;
  // Mask 2 seconds if we are in autostart so that if user is plugging in and
  // then putting in stand it doesnt wake instantly
  if (getSettingValue(SettingsOptions::AutoStartMode)) {
    osDelay(2 * TICKS_SECOND);
  }

  int16_t     datax[MOVFilter] = {0};
  int16_t     datay[MOVFilter] = {0};
  int16_t     dataz[MOVFilter] = {0};
  uint8_t     currentPointer   = 0;
  int16_t     tx = 0, ty = 0, tz = 0;
  int32_t     avgx, avgy, avgz;
  Orientation rotation = ORIENTATION_FLAT;
#ifdef ACCEL_EXITS_ON_MOVEMENT
  uint16_t tripCounter = 0;
#endif
  for (;;) {
    int32_t threshold = 1500 + (9 * 200);
    threshold -= getSettingValue(SettingsOptions::Sensitivity) * 200; // 200 is the step size
    readAccelerometer(tx, ty, tz, rotation);
    if (getSettingValue(SettingsOptions::OrientationMode) == 2) {
      if (rotation != ORIENTATION_FLAT) {
        OLED::setRotation(rotation == ORIENTATION_LEFT_HAND); // link the data through
      }
    }
    datax[currentPointer] = (int32_t)tx;
    datay[currentPointer] = (int32_t)ty;
    dataz[currentPointer] = (int32_t)tz;
    if (!accelInit) {
      for (uint8_t i = currentPointer + 1; i < MOVFilter; i++) {
        datax[i] = (int32_t)tx;
        datay[i] = (int32_t)ty;
        dataz[i] = (int32_t)tz;
      }
      accelInit = 1;
    }
    currentPointer = (currentPointer + 1) % MOVFilter;
    avgx = avgy = avgz = 0;
    // calculate averages
    for (uint8_t i = 0; i < MOVFilter; i++) {
      avgx += datax[i];
      avgy += datay[i];
      avgz += dataz[i];
    }
    avgx /= MOVFilter;
    avgy /= MOVFilter;
    avgz /= MOVFilter;

    // Sum the deltas
    int32_t error = (abs(avgx - tx) + abs(avgy - ty) + abs(avgz - tz));
    // So now we have averages, we want to look if these are different by more
    // than the threshold

    // If movement has occurred then we update the tick timer
    bool overThreshold = error > threshold;
#ifdef ACCEL_EXITS_ON_MOVEMENT
    if (overThreshold) {
      tripCounter++;
      if (tripCounter > 2) {
        lastMovementTime = xTaskGetTickCount();
      }
    } else if (tripCounter > 0) {
      tripCounter = 0;
    }
#else
    if (overThreshold) {
      lastMovementTime = xTaskGetTickCount();
    }

#endif

    vTaskDelay(TICKS_100MS); // Slow down update rate
  }
}


================================================
FILE: source/Core/Threads/PIDThread.cpp
================================================
/*
 * PIDThread.cpp
 *
 *  Created on: 29 May 2020
 *      Author: Ralim
 */

#include "BSP.h"
#include "FreeRTOS.h"
#include "Settings.h"
#include "TipThermoModel.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "history.hpp"
#include "main.hpp"
#include "power.hpp"
#include "task.h"

#ifdef POW_PD
#if POW_PD == 1
#include "USBPD.h"
#endif
#endif

static TickType_t          powerPulseWaitUnit          = 25 * TICKS_100MS;      // 2.5 s
static TickType_t          powerPulseDurationUnit      = (5 * TICKS_100MS) / 2; // 250 ms
TaskHandle_t               pidTaskNotification         = NULL;
volatile TemperatureType_t currentTempTargetDegC       = 0; // Current temperature target in C
int32_t                    powerSupplyWattageLimit     = 0;
uint8_t                    heaterThermalRunawayCounter = 0;

static int32_t getPIDResultX10Watts(TemperatureType_t set_point, TemperatureType_t current_value);
static void    detectThermalRunaway(const TemperatureType_t currentTipTempInC, const uint32_t x10WattsOut);
static void    setOutputx10WattsViaFilters(int32_t x10Watts);
static int32_t getX10WattageLimits();

/* StartPIDTask function */
void startPIDTask(void const *argument __unused) {
  /*
   * We take the current tip temperature & evaluate the next step for the tip
   * control PWM.
   */
  setTipX10Watts(0); // disable the output at startup

  currentTempTargetDegC = 0; // Force start with no output (off). If in sleep / soldering this will
                             // be over-ridden rapidly

  pidTaskNotification = xTaskGetCurrentTaskHandle();

  TemperatureType_t PIDTempTarget = 0;
  // Pre-seed the adc filters
  for (int i = 0; i < 32; i++) {
    ulTaskNotifyTake(pdTRUE, 5);
    TipThermoModel::getTipInC(true);
    getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 1);
  }

  while (preStartChecks() == 0) {
    resetWatchdog();
    ulTaskNotifyTake(pdTRUE, 2000);
  }
// Wait for PD if its in the middle of negotiation
#ifdef POW_PD
#if POW_PD == 1
  // This is an FUSB based PD capable device
  // Wait up to 3 seconds for USB-PD to settle
  while (USBPowerDelivery::negotiationInProgress() && xTaskGetTickCount() < (TICKS_SECOND * 3)) {
    resetWatchdog();
    ulTaskNotifyTake(pdTRUE, TICKS_100MS);
  }
#endif
#endif

  int32_t    x10WattsOut             = 0;
  TickType_t lastThermalRunawayDecay = xTaskGetTickCount();

  for (;;) {
    x10WattsOut = 0;
    // This is a call to block this thread until the ADC does its samples
    if (ulTaskNotifyTake(pdTRUE, TICKS_SECOND * 2)) {
      // Do the reading here to keep the temp calculations churning along
      TemperatureType_t currentTipTempInC = TipThermoModel::getTipInC(true);

      PIDTempTarget = currentTempTargetDegC;
      if (PIDTempTarget > 0) {
        // Cap the max set point to 450C
        if (PIDTempTarget > 450) {
          // Maximum allowed output
          PIDTempTarget = 450;
        }
        // Safety check that not aiming higher than current tip can measure
        if (PIDTempTarget > TipThermoModel::getTipMaxInC()) {
          PIDTempTarget = TipThermoModel::getTipMaxInC();
        }

        x10WattsOut = getPIDResultX10Watts(PIDTempTarget, currentTipTempInC);
        detectThermalRunaway(currentTipTempInC, x10WattsOut);
      } else {
        detectThermalRunaway(currentTipTempInC, 0);
      }
      setOutputx10WattsViaFilters(x10WattsOut);
    } else {
      // ADC interrupt timeout
      setTipPWM(0, false);
    }
#ifdef DEBUG_UART_OUTPUT
    log_system_state(x10WattsOut);
#endif
    if (xTaskGetTickCount() - lastThermalRunawayDecay > TICKS_SECOND) {
      lastThermalRunawayDecay = xTaskGetTickCount();
      if (heaterThermalRunawayCounter > 0) {
        heaterThermalRunawayCounter--;
      }
    }
  }
}

#ifdef TIP_CONTROL_PID
template  struct PID {
  T previous_error_term;
  T integration_running_sum;

  T update(const T set_point, const T new_reading, const TickType_t interval_ms, const T max_output) {
    const T target_delta = set_point - new_reading;

    // Proportional term
    const T kp_result = Kp * target_delta;

    // Integral term as we use mixed sampling rates, we cant assume a constant sample interval
    // Thus we multiply this out by the interval time to ~= dv/dt
    // Then the shift by 1000 is ms -> Seconds

    integration_running_sum += (target_delta * interval_ms * Ki) / 1000;

    // We constrain integration_running_sum to limit windup
    // This is not overly required for most use cases but can prevent large overshoot in constrained implementations
    if (integration_running_sum > integral_limit_scale * max_output) {
      integration_running_sum = integral_limit_scale * max_output;
    } else if (integration_running_sum < -integral_limit_scale * max_output) {
      integration_running_sum = -integral_limit_scale * max_output;
    }
    // Calculate the integral term, we use a shift 100 to get precision in integral as we often need small amounts
    T ki_result = integration_running_sum / 100;

    // Derivative term
    T derivative = (target_delta - previous_error_term);
    T kd_result  = ((Kd * derivative) / (T)(interval_ms));

    // Summation of the outputs
    T output = kp_result + ki_result + kd_result;

    // Restrict to max / 0
    if (output > max_output) {
      output = max_output;
    } else if (output < 0) {
      output = 0;
    }

    // Save target_delta to previous target_delta
    previous_error_term = target_delta;

    return output;
  }
};
#else
template  struct Integrator {
  T sum;

  T update(const T val, const int32_t inertia, const int32_t gain, const int32_t rate, const int32_t limit) {
    // Decay the old value. This is a simplified formula that still works with decent results
    // Ideally we would have used an exponential decay but the computational effort required
    // by exp function is just not justified here in respect to the outcome
    sum = (sum * (100 - (inertia / rate))) / 100;
    // Add the new value x integration interval ( 1 / rate)
    sum += (gain * val) / rate;

    // constrain the output between +- our max power output, this limits windup when doing the inital heatup or when solding something large
    if (sum > limit) {
      sum = limit;
    } else if (sum < -limit) {
      sum = -limit;
    }

    return sum;
  }

  void set(T const val) { sum = val; }

  T get(bool positiveOnly = true) const { return (positiveOnly) ? ((sum > 0) ? sum : 0) : sum; }
};
#endif
int32_t getPIDResultX10Watts(TemperatureType_t set_point, TemperatureType_t current_reading) {
  static TickType_t lastCall = 0;

#ifdef TIP_CONTROL_PID
  static PID pid = {0, 0};

  const TickType_t interval = (xTaskGetTickCount() - lastCall);

#else
  static Integrator powerStore = {0};
  const TickType_t                     rate       = TICKS_SECOND / (xTaskGetTickCount() - lastCall);
#endif
  lastCall = xTaskGetTickCount();
  // Sandman note:
  // PID Challenge - we have a small thermal mass that we to want heat up as fast as possible but we don't
  // want to overshot excessively (if at all) the set point temperature. In the same time we have 'imprecise'
  // instant temperature measurements. The nature of temperature reading imprecision is not necessarily
  // related to the sensor (thermocouple) or DAQ system, that otherwise are fairly decent. The real issue	is
  // the thermal inertia. We basically read the temperature in the window between two heating sessions when
  // the output is off. However, the heater temperature does not dissipate instantly into the tip mass so
  // at any moment right after heating, the thermocouple would sense a temperature significantly higher than
  // moments later. We could use longer delays but that would slow the PID loop and that would lead to other
  // negative side effects. As a result, we can only rely on the I term but with a twist. Instead of a simple
  // integrator we are going to use a self decaying integrator that acts more like a dual I term / P term
  // rather than a plain I term. Depending on the circumstances, like when the delta temperature is large,
  // it acts more like a P term whereas on closing to set point it acts increasingly closer to a plain I term.
  // So in a sense, we have a bit of both.
  //																		 So there we go...

  // P = (Thermal Mass) x (Delta Temperature ) / 1sec, where thermal mass is in X10 J / °C and
  // delta temperature is in °C. The result is the power in X10 W needed to raise (or decrease!) the
  // tip temperature with (Delta Temperature ) °C in 1 second.
  // Note on powerStore. On update, if the value is provided in X10 (W) units then inertia shall be provided
  // in X10 (J / °C) units as well.

#ifdef TIP_CONTROL_PID
  return pid.update(set_point, current_reading, interval, getX10WattageLimits());
#else
  return powerStore.update(((TemperatureType_t)getTipThermalMass()) * (set_point - current_reading), // the required power
                           getTipInertia(),                                                          // Inertia, smaller numbers increase dominance of the previous value
                           2,                                                                        // gain
                           rate,                                                                     // PID cycle frequency
                           getX10WattageLimits());
#endif
}

/*
 * Detection of thermal runaway
 * The goal of this is to handle cases where something has gone wrong
 * 1. The tip MOSFET is broken, so power is being constantly applied to the tip
 * a. This can show as temp being stuck at max
 * b. Or temp rising when the heater is off
 * 2. Broken temperature sense
 * a. Temp is stuck at a value
 * These boil down to either a constantly rising temperature or a temperature that is stuck at a value
 * These are both covered; but looking at the eye/delta between min and max temp seen
 */
void detectThermalRunaway(const TemperatureType_t currentTipTempInC, const uint32_t x10WattsOut) {

  static TemperatureType_t tiptempMin         = 0xFFFF; // Min tip temp seen
  static TemperatureType_t tipTempMax         = 0;      // Max tip temp seen while heater is on
  bool                     thisCycleIsHeating = x10WattsOut > 0;
  static TickType_t        heatCycleStart     = 0;

  static bool haveSeenDelta = false;

  // Check for readings being pegged at the top of the ADC while the heater is off
  if (!thisCycleIsHeating && (getTipRawTemp(0) > (ADC_MAX_READING - 8)) && heaterThermalRunawayCounter < 255) {
    heaterThermalRunawayCounter++;
  }

  if (haveSeenDelta) {
    return;
  }

  if (currentTipTempInC < tiptempMin) {
    tiptempMin = currentTipTempInC;
  }
  if (thisCycleIsHeating && currentTipTempInC > tipTempMax) {
    tipTempMax = currentTipTempInC;
  }
  if (thisCycleIsHeating) {
    if (heatCycleStart == 0) {
      heatCycleStart = xTaskGetTickCount();
    }
  } else {
    heatCycleStart = 0;
  }

  if ((xTaskGetTickCount() - heatCycleStart) > (THERMAL_RUNAWAY_TIME_SEC * TICKS_SECOND)) {
    if (tipTempMax > tiptempMin) {
      // Have been heating for min seconds, check if the delta is large enough
      TemperatureType_t delta = tipTempMax - tiptempMin;
      haveSeenDelta           = true;

      if (delta < THERMAL_RUNAWAY_TEMP_C && heaterThermalRunawayCounter < 255) {
        heaterThermalRunawayCounter++;
      }
    }
  }
}

int32_t getX10WattageLimits() {
  int32_t limit = availableW10(0);

  if (getSettingValue(SettingsOptions::PowerLimit) && limit > (getSettingValue(SettingsOptions::PowerLimit) * 10)) {
    limit = getSettingValue(SettingsOptions::PowerLimit) * 10;
  }
  if (powerSupplyWattageLimit && limit > powerSupplyWattageLimit * 10) {
    limit = powerSupplyWattageLimit * 10;
  }
  return limit;
}

void setOutputx10WattsViaFilters(int32_t x10WattsOut) {
  static TickType_t lastPowerPulseStart = 0;
  static TickType_t lastPowerPulseEnd   = 0;
#ifdef SLEW_LIMIT
  static int32_t x10WattsOutLast = 0;
#endif

  // If the user turns on the option of using an occasional pulse to keep the power bank on
  if (getSettingValue(SettingsOptions::KeepAwakePulse)) {
    const TickType_t powerPulseWait = powerPulseWaitUnit * getSettingValue(SettingsOptions::KeepAwakePulseWait);
    if (xTaskGetTickCount() - lastPowerPulseStart > powerPulseWait) {
      const TickType_t powerPulseDuration = powerPulseDurationUnit * getSettingValue(SettingsOptions::KeepAwakePulseDuration);
      lastPowerPulseStart                 = xTaskGetTickCount();
      lastPowerPulseEnd                   = lastPowerPulseStart + powerPulseDuration;
    }

    // If current PID is less than the pulse level, check if we want to constrain to the pulse as the floor
    if (x10WattsOut < getSettingValue(SettingsOptions::KeepAwakePulse) && xTaskGetTickCount() < lastPowerPulseEnd) {
      x10WattsOut = getSettingValue(SettingsOptions::KeepAwakePulse);
    }
  }

  // Secondary safety check to forcefully disable header when within ADC noise of top of ADC
  if (getTipRawTemp(0) > (0x7FFF - 32)) {
    x10WattsOut = 0;
  }
  if (heaterThermalRunawayCounter > 8) {
    x10WattsOut = 0;
  }
#ifdef SLEW_LIMIT
  if (x10WattsOut - x10WattsOutLast > SLEW_LIMIT) {
    x10WattsOut = x10WattsOutLast + SLEW_LIMIT;
  }
  if (x10WattsOut < 0) {
    x10WattsOut = 0;
  }
  x10WattsOutLast = x10WattsOut;
#endif
  setTipX10Watts(x10WattsOut);
  resetWatchdog();
}


================================================
FILE: source/Core/Threads/POWThread.cpp
================================================
/*
 * POWThread.cpp
 *
 *  Created on: 16 Jan 2021
 *      Author: Ralim
 */

#include "BSP.h"
#include "FS2711.hpp"
#include "FreeRTOS.h"
#include "HUB238.hpp"
#include "QC3.h"
#include "Settings.h"
#include "USBPD.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "main.hpp"
#include "stdbool.h"
#include "stdlib.h"
#include "task.h"

// Small worker thread to handle power (PD + QC) related steps

void startPOWTask(void const *argument __unused) {

  // Init any other misc sensors
  postRToSInit();
  while (preStartChecksDone() == 0) {
    osDelay(3);
  }
  // You have to run this once we are willing to answer PD messages
  // Setting up too early can mean that we miss the ~20ms window to respond on some chargers
#ifdef POW_PD
  USBPowerDelivery::start();
  // Crank the handle at boot until we are stable and waiting for IRQ
  USBPowerDelivery::step();
#endif
#if POW_PD_EXT == 2
  FS2711::start();
  FS2711::negotiate();
#endif

  BaseType_t res;
  for (;;) {
    res = pdFALSE;
    // While the interrupt is low, dont delay
    /*This is due to a possible race condition, where:
     * IRQ fires
     * We read interrupt register but dont see the Good CRC
     * Then Good CRC is set while reading it out (racing on I2C read)
     * Then we would sleep as nothing to do, but 100ms> 20ms power supply typical timeout
     */
    if (!getFUS302IRQLow()) {
      res = xTaskNotifyWait(0x0, 0xFFFFFF, NULL, TICKS_100MS / 2);
    }

#ifdef POW_PD
    if (res != pdFALSE || getFUS302IRQLow()) {
      USBPowerDelivery::IRQOccured();
    }
    USBPowerDelivery::PPSTimerCallback();
    USBPowerDelivery::step();

#else
    (void)res;
#endif
#if POW_PD_EXT == 1
    hub238_check_negotiation();
#endif
#if POW_PD_EXT == 2
    FS2711::negotiate();
#endif
    power_check();
  }
}


================================================
FILE: source/Core/Threads/UI/README.md
================================================
# UI

The User interface for IronOS is split into two halves in these folders.
The `logic` folder contains the `.cpp` files that implement the logic of each mode, this should handle button events and any logic.
The `drawing` folder contains the `.cpp` files that implement just the screen drawing for each mode. These are further subdivided by the screen _types_.


================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_cjc_sampling.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32
void ui_draw_cjc_sampling(const uint8_t num_dots) {
  OLED::setCursor(0, 0);
  OLED::print(translatedString(Tr->CJCCalibrating), FontStyle::SMALL);
  OLED::setCursor(0, 8);
  OLED::print(SmallSymbolDot, FontStyle::SMALL);
  for (uint8_t x = 0; x < num_dots; x++) {
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_debug_menu.cpp
================================================
#include "OperatingModes.h"
#include "TipThermoModel.h"
#include "main.hpp"
#include "ui_drawing.hpp"

#ifdef OLED_128x32
extern osThreadId GUITaskHandle;
extern osThreadId MOVTaskHandle;
extern osThreadId PIDTaskHandle;

void ui_draw_debug_menu(const uint8_t item_number) {
  OLED::setCursor(0, 0);                                   // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolVersionNumber, FontStyle::SMALL); // Print version number
  OLED::setCursor(0, 8);                                   // second line
  OLED::print(DebugMenu[item_number], FontStyle::SMALL);
  switch (item_number) {
  case 0: // Build Date
    break;
  case 1: // Device ID
  {
    uint64_t id = getDeviceID();
#ifdef DEVICE_HAS_VALIDATION_CODE
    // If device has validation code; then we want to take over both lines of the screen
    OLED::clearScreen();   // Ensure the buffer starts clean
    OLED::setCursor(0, 0); // Position the cursor at the 0,0 (top left)
    OLED::print(DebugMenu[item_number], FontStyle::SMALL);
    OLED::drawHex(getDeviceValidation(), FontStyle::SMALL, 8);
    OLED::setCursor(0, 8); // second line
#endif
    OLED::drawHex((uint32_t)(id >> 32), FontStyle::SMALL, 8);
    OLED::drawHex((uint32_t)(id & 0xFFFFFFFF), FontStyle::SMALL, 8);
  } break;
  case 2: // ACC Type
    OLED::print(AccelTypeNames[(int)DetectedAccelerometerVersion], FontStyle::SMALL);
    break;
  case 3: // Power Negotiation Status
    OLED::print(PowerSourceNames[getPowerSourceNumber()], FontStyle::SMALL);
    break;
  case 4: // Input Voltage
    printVoltage();
    break;
  case 5: // Temp in °C
    OLED::printNumber(TipThermoModel::getTipInC(), 6, FontStyle::SMALL);
    break;
  case 6: // Handle Temp in °C
    OLED::printNumber(getHandleTemperature(0) / 10, 6, FontStyle::SMALL);
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(getHandleTemperature(0) % 10, 1, FontStyle::SMALL);
    break;
  case 7: // Max Temp Limit in °C
    OLED::printNumber(TipThermoModel::getTipMaxInC(), 6, FontStyle::SMALL);
    break;
  case 8: // System Uptime
    OLED::printNumber(xTaskGetTickCount() / TICKS_100MS, 8, FontStyle::SMALL);
    break;
  case 9: // Movement Timestamp
    OLED::printNumber(lastMovementTime / TICKS_100MS, 8, FontStyle::SMALL);
    break;
  case 10:                                                              // Tip Resistance in Ω
    OLED::printNumber(getTipResistanceX10() / 10, 6, FontStyle::SMALL); // large to pad over so that we cover ID left overs
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(getTipResistanceX10() % 10, 1, FontStyle::SMALL);
    break;
  case 11: // Raw Tip in µV
    OLED::printNumber(TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true), 8, FontStyle::SMALL);
    break;
  case 12: // Tip Cold Junction Compensation Offset in µV
    OLED::printNumber(getSettingValue(SettingsOptions::CalibrationOffset), 8, FontStyle::SMALL);
    break;
  case 13: // High Water Mark for GUI
    OLED::printNumber(uxTaskGetStackHighWaterMark(GUITaskHandle), 8, FontStyle::SMALL);
    break;
  case 14: // High Water Mark for Movement Task
    OLED::printNumber(uxTaskGetStackHighWaterMark(MOVTaskHandle), 8, FontStyle::SMALL);
    break;
  case 15: // High Water Mark for PID Task
    OLED::printNumber(uxTaskGetStackHighWaterMark(PIDTaskHandle), 8, FontStyle::SMALL);
    break;
    break;
#ifdef HALL_SENSOR
  case 16: // Raw Hall Effect Value
  {
    int16_t hallEffectStrength = getRawHallEffect();
    if (hallEffectStrength < 0) {
      hallEffectStrength = -hallEffectStrength;
    }
    OLED::printNumber(hallEffectStrength, 6, FontStyle::SMALL);
  } break;
#endif

  default:
    break;
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_homescreen_detailed.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32

extern uint8_t buttonAF[sizeof(buttonA)];
extern uint8_t buttonBF[sizeof(buttonB)];
extern uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_draw_homescreen_detailed(TemperatureType_t tipTemp) {
  if (isTipDisconnected()) {
    if (OLED::getRotation()) {
      // in right handed mode we want to draw over the first part
      OLED::drawArea(54, 0, 56, 32, disconnectedTipF);
    } else {
      OLED::drawArea(0, 0, 56, 32, disconnectedTip);
    }
    if (OLED::getRotation()) {
      OLED::setCursor(-1, 0);
    } else {
      OLED::setCursor(56, 0);
    }
    uint32_t Vlt = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    OLED::printNumber(Vlt / 10, 2, FontStyle::LARGE);
    OLED::print(LargeSymbolDot, FontStyle::LARGE);
    OLED::printNumber(Vlt % 10, 1, FontStyle::LARGE);
    if (OLED::getRotation()) {
      OLED::setCursor(48, 8);
    } else {
      OLED::setCursor(91, 8);
    }
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  } else {
    if (!(getSettingValue(SettingsOptions::CoolingTempBlink) && (tipTemp > 55) && (xTaskGetTickCount() % 1000 < 300))) {
      // Blink temp if setting enable and temp < 55°
      // 1000 tick/sec
      // OFF 300ms ON 700ms
      ui_draw_tip_temperature(true, FontStyle::LARGE); // draw in the temp
    }
    if (OLED::getRotation()) {
      OLED::setCursor(6, 0);
    } else {
      OLED::setCursor(73, 0); // top right
    }
    // draw set temp
    OLED::printNumber(getSettingValue(SettingsOptions::SolderingTemp), 3, FontStyle::SMALL);

    OLED::printSymbolDeg(FontStyle::SMALL);

    if (OLED::getRotation()) {
      OLED::setCursor(0, 8);
    } else {
      OLED::setCursor(67, 8); // bottom right
    }
    printVoltage(); // draw voltage then symbol (v)
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_homescreen_simplified.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_128x32

extern uint8_t buttonAF[sizeof(buttonA)];
extern uint8_t buttonBF[sizeof(buttonB)];
extern uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_draw_homescreen_simplified(TemperatureType_t tipTemp) {
  bool tempOnDisplay          = false;
  bool tipDisconnectedDisplay = false;
  if (OLED::getRotation()) {
    OLED::drawArea(68, 0, 56, 32, buttonAF);
    OLED::drawArea(12, 0, 56, 32, buttonBF);
    OLED::setCursor(0, 0);
    ui_draw_power_source_icon();
  } else {
    OLED::drawArea(0, 0, 56, 32, buttonA);  // Needs to be flipped so button ends up
    OLED::drawArea(58, 0, 56, 32, buttonB); // on right side of screen
    OLED::setCursor(116, 0);
    ui_draw_power_source_icon();
  }
  tipDisconnectedDisplay = false;
  if (tipTemp > 55) {
    tempOnDisplay = true;
  } else if (tipTemp < 45) {
    tempOnDisplay = false;
  }
  if (isTipDisconnected()) {
    tempOnDisplay          = false;
    tipDisconnectedDisplay = true;
  }
  if (tempOnDisplay || tipDisconnectedDisplay) {
    // draw temp over the start soldering button
    // Location changes on screen rotation
    if (OLED::getRotation()) {
      // in right handed mode we want to draw over the first part
      OLED::fillArea(68, 0, 56, 32, 0); // clear the area for the temp
      OLED::setCursor(56, 0);
    } else {
      OLED::fillArea(0, 0, 56, 32, 0); // clear the area
      OLED::setCursor(0, 0);
    }
    // If we have a tip connected draw the temp, if not we leave it blank
    if (!tipDisconnectedDisplay) {
      // draw in the temp
      if (!(getSettingValue(SettingsOptions::CoolingTempBlink) && (xTaskGetTickCount() % 1000 < 300))) {
        ui_draw_tip_temperature(false, FontStyle::LARGE); // draw in the temp
      }
    } else {
      // Draw in missing tip symbol
      if (OLED::getRotation()) {
        // in right handed mode we want to draw over the first part
        OLED::drawArea(54, 0, 56, 32, disconnectedTipF);
      } else {
        OLED::drawArea(0, 0, 56, 32, disconnectedTip);
      }
    }
  }
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_power_source_icon.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32
void ui_draw_power_source_icon(void) {
#if defined(POW_PD) || defined(POW_QC) || defined(POW_PD_EXT)
  if (!getIsPoweredByDCIN()) {
    // On non-DC inputs we replace this symbol with the voltage we are operating on
    // If <9V then show single digit, if not show dual small ones vertically stacked
    uint16_t V = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    if (V % 10 >= 5) {
      V = (V / 10) + 1; // round up
    } else {
      V = V / 10;
    }
    int16_t xPos = OLED::getCursorX();
    OLED::printNumber(V / 10, 1, FontStyle::LARGE);
    OLED::setCursor(xPos, 16);
    OLED::printNumber(V % 10, 1, FontStyle::LARGE);
    return;
  }
#endif
#ifdef POW_DC
  if (getSettingValue(SettingsOptions::MinDCVoltageCells)) {
    // User is on a lithium battery
    // we need to calculate which of the 10 levels they are on
    uint8_t  cellCount = getSettingValue(SettingsOptions::MinDCVoltageCells) + 2;
    uint32_t cellV     = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0) / cellCount;
    // Should give us approx cell voltage X10
    // Range is 42 -> Minimum voltage setting (systemSettings.minVoltageCells) = 9 steps therefore we will use battery 0-9
    if (cellV < getSettingValue(SettingsOptions::MinVoltageCells)) {
      cellV = getSettingValue(SettingsOptions::MinVoltageCells);
    }
    cellV -= getSettingValue(SettingsOptions::MinVoltageCells); // Should leave us a number of 0-9
    if (cellV > 9) {
      cellV = 9;
    }
    OLED::drawBattery(cellV + 1);
  } else {
    OLED::drawSymbol(15); // Draw the DC Logo
  }
#endif
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_profile_advanced.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_128x32
void ui_draw_soldering_profile_advanced(TemperatureType_t tipTemp, TemperatureType_t profileCurrentTargetTemp, uint32_t phaseElapsedSeconds, uint32_t phase, const uint32_t phaseTimeGoal) {
  // print temperature
  if (OLED::getRotation()) {
    OLED::setCursor(48, 0);
  } else {
    OLED::setCursor(0, 0);
  }

  OLED::printNumber(tipTemp, 3, FontStyle::SMALL);
  OLED::print(SmallSymbolSlash, FontStyle::SMALL);
  OLED::printNumber(profileCurrentTargetTemp, 3, FontStyle::SMALL);

  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    OLED::print(SmallSymbolDegF, FontStyle::SMALL);
  } else {
    OLED::print(SmallSymbolDegC, FontStyle::SMALL);
  }

  // print phase
  if (phase > 0 && phase <= getSettingValue(SettingsOptions::ProfilePhases)) {
    if (OLED::getRotation()) {
      OLED::setCursor(36, 0);
    } else {
      OLED::setCursor(55, 0);
    }
    OLED::printNumber(phase, 1, FontStyle::SMALL);
  }

  // print time progress / preheat / cooldown
  if (OLED::getRotation()) {
    OLED::setCursor(42, 16);
  } else {
    OLED::setCursor(0, 16);
  }

  if (phase == 0) {
    OLED::print(translatedString(Tr->ProfilePreheatString), FontStyle::SMALL);
  } else if (phase > getSettingValue(SettingsOptions::ProfilePhases)) {
    OLED::print(translatedString(Tr->ProfileCooldownString), FontStyle::SMALL);
  } else {
    OLED::printNumber(phaseElapsedSeconds / 60, 1, FontStyle::SMALL);
    OLED::print(SmallSymbolColon, FontStyle::SMALL);
    OLED::printNumber(phaseElapsedSeconds % 60, 2, FontStyle::SMALL, false);

    OLED::print(SmallSymbolSlash, FontStyle::SMALL);

    // blink if we can't keep up with the time goal
    if (phaseElapsedSeconds < phaseTimeGoal + 2 || (xTaskGetTickCount() / TICKS_SECOND) % 2 == 0) {
      OLED::printNumber(phaseTimeGoal / 60, 1, FontStyle::SMALL);
      OLED::print(SmallSymbolColon, FontStyle::SMALL);
      OLED::printNumber(phaseTimeGoal % 60, 2, FontStyle::SMALL, false);
    }
  }
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_soldering_basic_status.cpp
================================================
#include "power.hpp"
#include "ui_drawing.hpp"
#ifdef OLED_128x32

void ui_draw_soldering_basic_status(bool boostModeOn) {
  OLED::setCursor(0, 0);
  // We switch the layout direction depending on the orientation of the oled
  if (OLED::getRotation()) {
    // battery
    ui_draw_power_source_icon();
    // Space out gap between battery <-> temp
    OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    // Draw current tip temp
    ui_draw_tip_temperature(true, FontStyle::LARGE);

    // We draw boost arrow if boosting,
    // or else gap temp <-> heat indicator
    if (boostModeOn) {
      OLED::drawSymbol(2);
    } else {
      OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    }

    // Draw heating/cooling symbols
    OLED::drawHeatSymbol(X10WattsToPWM(x10WattHistory.average()));
  } else {
    // Draw heating/cooling symbols
    OLED::drawHeatSymbol(X10WattsToPWM(x10WattHistory.average()));
    // We draw boost arrow if boosting,
    // or else gap temp <-> heat indicator
    if (boostModeOn) {
      OLED::drawSymbol(2);
    } else {
      OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    }
    // Draw current tip temp
    ui_draw_tip_temperature(true, FontStyle::LARGE);
    // Space out gap between battery <-> temp
    OLED::print(LargeSymbolSpace, FontStyle::LARGE);

    ui_draw_power_source_icon();
  }
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_soldering_power_status.cpp
================================================
#include "power.hpp"
#include "ui_drawing.hpp"
#include 
#ifdef OLED_128x32

void ui_draw_soldering_power_status(bool boost_mode_on) {
  if (OLED::getRotation()) {
    OLED::setCursor(50, 0);
  } else {
    OLED::setCursor(-1, 0);
  }

  ui_draw_tip_temperature(true, FontStyle::LARGE);

  if (boost_mode_on) { // Boost mode is on
    if (OLED::getRotation()) {
      OLED::setCursor(34, 0);
    } else {
      OLED::setCursor(50, 0);
    }
    OLED::print(LargeSymbolPlus, FontStyle::LARGE);
  } else {
#ifndef NO_SLEEP_MODE
    if (getSettingValue(SettingsOptions::Sensitivity) && getSettingValue(SettingsOptions::SleepTime)) {
      if (OLED::getRotation()) {
        OLED::setCursor(32, 0);
      } else {
        OLED::setCursor(47, 0);
      }
      printCountdownUntilSleep(getSleepTimeout());
    }
#endif
    if (OLED::getRotation()) {
      OLED::setCursor(32, 8);
    } else {
      OLED::setCursor(47, 8);
    }
    OLED::print(PowerSourceNames[getPowerSourceNumber()], FontStyle::SMALL, 2);
  }

  if (OLED::getRotation()) {
    OLED::setCursor(0, 0);
  } else {
    OLED::setCursor(67, 0);
  }
  // Print wattage
  {
    uint32_t x10Watt = x10WattHistory.average();
    if (x10Watt > 999) {
      // If we exceed 99.9W we drop the decimal place to keep it all fitting
      OLED::print(SmallSymbolSpace, FontStyle::SMALL);
      OLED::printNumber(x10WattHistory.average() / 10, 3, FontStyle::SMALL);
    } else {
      OLED::printNumber(x10WattHistory.average() / 10, 2, FontStyle::SMALL);
      OLED::print(SmallSymbolDot, FontStyle::SMALL);
      OLED::printNumber(x10WattHistory.average() % 10, 1, FontStyle::SMALL);
    }
    OLED::print(SmallSymbolWatts, FontStyle::SMALL);
  }

  if (OLED::getRotation()) {
    OLED::setCursor(0, 8);
  } else {
    OLED::setCursor(67, 8);
  }
  printVoltage();
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_soldering_sleep_mode.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_128x32
void ui_draw_soldering_detailed_sleep(TemperatureType_t tipTemp) {

  OLED::clearScreen();
  OLED::setCursor(0, 0);
  OLED::print(translatedString(Tr->SleepingAdvancedString), FontStyle::SMALL);
  OLED::setCursor(0, 8);
  OLED::print(translatedString(Tr->SleepingTipAdvancedString), FontStyle::SMALL);
  OLED::printNumber(tipTemp, 3, FontStyle::SMALL);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    OLED::print(SmallSymbolDegF, FontStyle::SMALL);
  } else {
    OLED::print(SmallSymbolDegC, FontStyle::SMALL);
  }

  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  printVoltage();
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);

  OLED::refresh();
}

void ui_draw_soldering_basic_sleep(TemperatureType_t tipTemp) {

  OLED::clearScreen();
  OLED::setCursor(0, 0);

  OLED::print(LargeSymbolSleep, FontStyle::LARGE);
  OLED::printNumber(tipTemp, 3, FontStyle::LARGE);
  OLED::printSymbolDeg(FontStyle::EXTRAS);

  OLED::refresh();
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_temperature_change.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_128x32
void ui_draw_temperature_change(void) {

  OLED::setCursor(8, 8);
  if (OLED::getRotation()) {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolPlus : LargeSymbolMinus, FontStyle::LARGE);
  } else {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolMinus : LargeSymbolPlus, FontStyle::LARGE);
  }

  OLED::print(LargeSymbolSpace, FontStyle::LARGE);
  OLED::printNumber(getSettingValue(SettingsOptions::SolderingTemp), 3, FontStyle::LARGE);
  OLED::printSymbolDeg(FontStyle::EXTRAS);
  OLED::print(LargeSymbolSpace, FontStyle::LARGE);
  if (OLED::getRotation()) {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolMinus : LargeSymbolPlus, FontStyle::LARGE);
  } else {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolPlus : LargeSymbolMinus, FontStyle::LARGE);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_tip_temperature.cpp
================================================
#include "OperatingModeUtilities.h"
#include "OperatingModes.h"
#include "SolderingCommon.h"
#include "TipThermoModel.h"
#ifdef OLED_128x32

void ui_draw_tip_temperature(bool symbol, const FontStyle font) {
  // Draw tip temp handling unit conversion & tolerance near setpoint
  TemperatureType_t Temp = getTipTemp();

  OLED::printNumber(Temp, 3, font); // Draw the tip temp out
  if (symbol) {
    // For big font, can draw nice symbols, otherwise fall back to chars
    OLED::printSymbolDeg(font == FontStyle::LARGE ? FontStyle::EXTRAS : font);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_usb_pd_debug.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32

void ui_draw_usb_pd_debug_state(const uint16_t vbus_sense_state, const uint8_t stateNumber) {
  OLED::setCursor(0, 0);                             // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolPDDebug, FontStyle::SMALL); // Print Title
  OLED::setCursor(0, 8);                             // second line
  // Print the PD state machine
  OLED::print(SmallSymbolState, FontStyle::SMALL);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  OLED::printNumber(stateNumber, 2, FontStyle::SMALL, true);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);

  if (vbus_sense_state == 2) {
    OLED::print(SmallSymbolNoVBus, FontStyle::SMALL);
  } else if (vbus_sense_state == 1) {
    OLED::print(SmallSymbolVBus, FontStyle::SMALL);
  }
}

void ui_draw_usb_pd_debug_pdo(const uint8_t entry_num, const uint16_t min_voltage, const uint16_t max_voltage, const uint16_t current_a_x100, const uint16_t wattage) {

  OLED::setCursor(0, 0);                                   // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolPDDebug, FontStyle::SMALL);       // Print Title
  OLED::setCursor(0, 8);                                   // second line
  OLED::printNumber(entry_num, 2, FontStyle::SMALL, true); // print the entry number
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  if (min_voltage > 0) {
    OLED::printNumber(min_voltage, 2, FontStyle::SMALL, true); // print the voltage
    OLED::print(SmallSymbolMinus, FontStyle::SMALL);
  }
  OLED::printNumber(max_voltage, 2, FontStyle::SMALL, true); // print the voltage
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  if (wattage) {
    OLED::printNumber(wattage, 3, FontStyle::SMALL, true); // print the current in 0.1A res
    OLED::print(SmallSymbolWatts, FontStyle::SMALL);
  } else {
    OLED::printNumber(current_a_x100 / 100, 2, FontStyle::SMALL, true); // print the current in 0.1A res
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(current_a_x100 % 100, 2, FontStyle::SMALL, false); // print the current in 0.1A res
    OLED::print(SmallSymbolAmps, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/draw_warning_undervoltage.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32

void ui_draw_warning_undervoltage(void) {
  OLED::clearScreen();
  OLED::setCursor(0, 0);
  if (getSettingValue(SettingsOptions::DetailedSoldering)) {
    OLED::print(translatedString(Tr->UndervoltageString), FontStyle::SMALL);
    OLED::setCursor(0, 8);
    OLED::print(translatedString(Tr->InputVoltageString), FontStyle::SMALL);
    printVoltage();
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  } else {
    OLED::print(translatedString(Tr->UVLOWarningString), FontStyle::LARGE);
  }

  OLED::refresh();
  GUIDelay();
  waitForButtonPress();
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/pre_render_assets.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32

uint8_t buttonAF[sizeof(buttonA)];
uint8_t buttonBF[sizeof(buttonB)];
uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_pre_render_assets(void) {
  // Generate the flipped screen into ram for later use
  // flipped is generated by flipping each row
  for (int row = 0; row < 4; row++) {
    for (int x = 0; x < 56; x++) {
      buttonAF[(row * 56) + x]         = buttonA[(row * 56) + (41 - x)];
      buttonBF[(row * 56) + x]         = buttonB[(row * 56) + (41 - x)];
      disconnectedTipF[(row * 56) + x] = disconnectedTip[(row * 56) + (41 - x)];
    }
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/printSleepCountdown.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"
#ifdef OLED_128x32
extern TickType_t lastMovementTime;
#ifndef NO_SLEEP_MODE
void printCountdownUntilSleep(int sleepThres) {
  /*
   * Print seconds or minutes (if > 99 seconds) until sleep
   * mode is triggered.
   */
  TickType_t lastEventTime = lastButtonTime < lastMovementTime ? lastMovementTime : lastButtonTime;
  TickType_t downCount     = sleepThres - xTaskGetTickCount() + lastEventTime;
  if (downCount > (99 * TICKS_SECOND)) {
    OLED::printNumber(downCount / 60000 + 1, 2, FontStyle::SMALL);
    OLED::print(SmallSymbolMinutes, FontStyle::SMALL);
  } else {
    OLED::printNumber(downCount / 1000 + 1, 2, FontStyle::SMALL);
    OLED::print(SmallSymbolSeconds, FontStyle::SMALL);
  }
}
#endif
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/print_voltage.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_128x32

void printVoltage(void) {
  uint32_t volt = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
  OLED::printNumber(volt / 10, 2, FontStyle::SMALL);
  OLED::print(SmallSymbolDot, FontStyle::SMALL);
  OLED::printNumber(volt % 10, 1, FontStyle::SMALL);
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_128x32/show_warning.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"
#include "OperatingModes.h"
#ifdef OLED_128x32
bool warnUser(const char *warning, const ButtonState buttons) {
  OLED::clearScreen();
  OLED::printWholeScreen(warning);
  // Also timeout after 5 seconds
  if ((xTaskGetTickCount() - lastButtonTime) > TICKS_SECOND * 5) {
    return true;
  }
  return buttons != BUTTON_NONE;
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_cjc_sampling.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_96x16
void ui_draw_cjc_sampling(const uint8_t num_dots) {
  OLED::setCursor(0, 0);
  OLED::print(translatedString(Tr->CJCCalibrating), FontStyle::SMALL);
  OLED::setCursor(0, 8);
  OLED::print(SmallSymbolDot, FontStyle::SMALL);
  for (uint8_t x = 0; x < num_dots; x++) {
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_debug_menu.cpp
================================================
#include "OperatingModes.h"
#include "TipThermoModel.h"
#include "main.hpp"
#include "ui_drawing.hpp"
#ifdef OLED_96x16
extern osThreadId GUITaskHandle;
extern osThreadId MOVTaskHandle;
extern osThreadId PIDTaskHandle;

void ui_draw_debug_menu(const uint8_t item_number) {
  OLED::setCursor(0, 0);                                   // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolVersionNumber, FontStyle::SMALL); // Print version number
  OLED::setCursor(0, 8);                                   // second line
  OLED::print(DebugMenu[item_number], FontStyle::SMALL);
  switch (item_number) {
  case 0: // Build Date
    break;
  case 1: // Device ID
  {
    uint64_t id = getDeviceID();
#ifdef DEVICE_HAS_VALIDATION_CODE
    // If device has validation code; then we want to take over both lines of the screen
    OLED::clearScreen();   // Ensure the buffer starts clean
    OLED::setCursor(0, 0); // Position the cursor at the 0,0 (top left)
    OLED::print(DebugMenu[item_number], FontStyle::SMALL);
    OLED::drawHex(getDeviceValidation(), FontStyle::SMALL, 8);
    OLED::setCursor(0, 8); // second line
#endif
    OLED::drawHex((uint32_t)(id >> 32), FontStyle::SMALL, 8);
    OLED::drawHex((uint32_t)(id & 0xFFFFFFFF), FontStyle::SMALL, 8);
  } break;
  case 2: // ACC Type
    OLED::print(AccelTypeNames[(int)DetectedAccelerometerVersion], FontStyle::SMALL);
    break;
  case 3: // Power Negotiation Status
    OLED::print(PowerSourceNames[getPowerSourceNumber()], FontStyle::SMALL);
    break;
  case 4: // Input Voltage
    printVoltage();
    break;
  case 5: // Temp in °C
    OLED::printNumber(TipThermoModel::getTipInC(), 6, FontStyle::SMALL);
    break;
  case 6: // Handle Temp in °C
    OLED::printNumber(getHandleTemperature(0) / 10, 6, FontStyle::SMALL);
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(getHandleTemperature(0) % 10, 1, FontStyle::SMALL);
    break;
  case 7: // Max Temp Limit in °C
    OLED::printNumber(TipThermoModel::getTipMaxInC(), 6, FontStyle::SMALL);
    break;
  case 8: // System Uptime
    OLED::printNumber(xTaskGetTickCount() / TICKS_100MS, 8, FontStyle::SMALL);
    break;
  case 9: // Movement Timestamp
    OLED::printNumber(lastMovementTime / TICKS_100MS, 8, FontStyle::SMALL);
    break;
  case 10:                                                              // Tip Resistance in Ω
    OLED::printNumber(getTipResistanceX10() / 10, 6, FontStyle::SMALL); // large to pad over so that we cover ID left overs
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(getTipResistanceX10() % 10, 1, FontStyle::SMALL);
    break;
  case 11: // Raw Tip in µV
    OLED::printNumber(TipThermoModel::convertTipRawADCTouV(getTipRawTemp(0), true), 8, FontStyle::SMALL);
    break;
  case 12: // Tip Cold Junction Compensation Offset in µV
    OLED::printNumber(getSettingValue(SettingsOptions::CalibrationOffset), 8, FontStyle::SMALL);
    break;
  case 13: // High Water Mark for GUI
    OLED::printNumber(uxTaskGetStackHighWaterMark(GUITaskHandle), 8, FontStyle::SMALL);
    break;
  case 14: // High Water Mark for Movement Task
    OLED::printNumber(uxTaskGetStackHighWaterMark(MOVTaskHandle), 8, FontStyle::SMALL);
    break;
  case 15: // High Water Mark for PID Task
    OLED::printNumber(uxTaskGetStackHighWaterMark(PIDTaskHandle), 8, FontStyle::SMALL);
    break;
    break;
#ifdef HALL_SENSOR
  case 16: // Raw Hall Effect Value
  {
    int16_t hallEffectStrength = getRawHallEffect();
    if (hallEffectStrength < 0) {
      hallEffectStrength = -hallEffectStrength;
    }
    OLED::printNumber(hallEffectStrength, 6, FontStyle::SMALL);
  } break;
#endif

  default:
    break;
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_homescreen_detailed.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

extern uint8_t buttonAF[sizeof(buttonA)];
extern uint8_t buttonBF[sizeof(buttonB)];
extern uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_draw_homescreen_detailed(TemperatureType_t tipTemp) {
  if (isTipDisconnected()) {
    if (OLED::getRotation()) {
      // in right handed mode we want to draw over the first part
      OLED::drawArea(54, 0, 42, 16, disconnectedTipF);
    } else {
      OLED::drawArea(0, 0, 42, 16, disconnectedTip);
    }
    if (OLED::getRotation()) {
      OLED::setCursor(-1, 0);
    } else {
      OLED::setCursor(42, 0);
    }
    uint32_t Vlt = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    OLED::printNumber(Vlt / 10, 2, FontStyle::LARGE);
    OLED::print(LargeSymbolDot, FontStyle::LARGE);
    OLED::printNumber(Vlt % 10, 1, FontStyle::LARGE);
    if (OLED::getRotation()) {
      OLED::setCursor(48, 8);
    } else {
      OLED::setCursor(91, 8);
    }
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  } else {
    if (!(getSettingValue(SettingsOptions::CoolingTempBlink) && (tipTemp > 55) && (xTaskGetTickCount() % 1000 < 300))) {
      // Blink temp if setting enable and temp < 55°
      // 1000 tick/sec
      // OFF 300ms ON 700ms
      ui_draw_tip_temperature(true, FontStyle::LARGE); // draw in the temp
    }
    if (OLED::getRotation()) {
      OLED::setCursor(6, 0);
    } else {
      OLED::setCursor(73, 0); // top right
    }
    // draw set temp
    OLED::printNumber(getSettingValue(SettingsOptions::SolderingTemp), 3, FontStyle::SMALL);

    OLED::printSymbolDeg(FontStyle::SMALL);

    if (OLED::getRotation()) {
      OLED::setCursor(0, 8);
    } else {
      OLED::setCursor(67, 8); // bottom right
    }
    printVoltage(); // draw voltage then symbol (v)
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_homescreen_simplified.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_96x16
extern uint8_t buttonAF[sizeof(buttonA)];
extern uint8_t buttonBF[sizeof(buttonB)];
extern uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_draw_homescreen_simplified(TemperatureType_t tipTemp) {
  bool tempOnDisplay          = false;
  bool tipDisconnectedDisplay = false;
  if (OLED::getRotation()) {
    OLED::drawArea(54, 0, 42, 16, buttonAF);
    OLED::drawArea(12, 0, 42, 16, buttonBF);
    OLED::setCursor(0, 0);
    ui_draw_power_source_icon();
  } else {
    OLED::drawArea(0, 0, 42, 16, buttonA);  // Needs to be flipped so button ends up
    OLED::drawArea(42, 0, 42, 16, buttonB); // on right side of screen
    OLED::setCursor(84, 0);
    ui_draw_power_source_icon();
  }
  tipDisconnectedDisplay = false;
  if (tipTemp > 55) {
    tempOnDisplay = true;
  } else if (tipTemp < 45) {
    tempOnDisplay = false;
  }
  if (isTipDisconnected()) {
    tempOnDisplay          = false;
    tipDisconnectedDisplay = true;
  }
  if (tempOnDisplay || tipDisconnectedDisplay) {
    // draw temp over the start soldering button
    // Location changes on screen rotation
    if (OLED::getRotation()) {
      // in right handed mode we want to draw over the first part
      OLED::fillArea(55, 0, 41, 16, 0); // clear the area for the temp
      OLED::setCursor(56, 0);
    } else {
      OLED::fillArea(0, 0, 41, 16, 0); // clear the area
      OLED::setCursor(0, 0);
    }
    // If we have a tip connected draw the temp, if not we leave it blank
    if (!tipDisconnectedDisplay) {
      // draw in the temp
      if (!(getSettingValue(SettingsOptions::CoolingTempBlink) && (xTaskGetTickCount() % 1000 < 300))) {
        ui_draw_tip_temperature(false, FontStyle::LARGE); // draw in the temp
      }
    } else {
      // Draw in missing tip symbol

      if (OLED::getRotation()) {
        // in right handed mode we want to draw over the first part
        OLED::drawArea(54, 0, 42, 16, disconnectedTipF);
      } else {
        OLED::drawArea(0, 0, 42, 16, disconnectedTip);
      }
    }
  }
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_power_source_icon.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_power_source_icon(void) {
#if defined(POW_PD) || defined(POW_QC) || defined(POW_PD_EXT)
  if (!getIsPoweredByDCIN()) {
    // On non-DC inputs we replace this symbol with the voltage we are operating on
    // If <9V then show single digit, if not show dual small ones vertically stacked
    uint16_t V = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
    if (V % 10 >= 5) {
      V = (V / 10) + 1; // round up
    } else {
      V = V / 10;
    }
    if (V > 9) {
      int16_t xPos = OLED::getCursorX();
      OLED::printNumber(V / 10, 1, FontStyle::SMALL);
      OLED::setCursor(xPos, 8);
      OLED::printNumber(V % 10, 1, FontStyle::SMALL);
      OLED::setCursor(xPos + 12, 0); // need to reset this as if we drew a wide char
    } else {
      OLED::printNumber(V, 1, FontStyle::LARGE);
    }
    return;
  }
#endif
#ifdef POW_DC
  if (getSettingValue(SettingsOptions::MinDCVoltageCells)) {
    // User is on a lithium battery
    // we need to calculate which of the 10 levels they are on
    uint8_t  cellCount = getSettingValue(SettingsOptions::MinDCVoltageCells) + 2;
    uint32_t cellV     = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0) / cellCount;
    // Should give us approx cell voltage X10
    // Range is 42 -> Minimum voltage setting (systemSettings.minVoltageCells) = 9 steps therefore we will use battery 0-9
    if (cellV < getSettingValue(SettingsOptions::MinVoltageCells)) {
      cellV = getSettingValue(SettingsOptions::MinVoltageCells);
    }
    cellV -= getSettingValue(SettingsOptions::MinVoltageCells); // Should leave us a number of 0-9
    if (cellV > 9) {
      cellV = 9;
    }
    OLED::drawBattery(cellV + 1);
  } else {
    OLED::drawSymbol(15); // Draw the DC Logo
  }
#endif
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_profile_advanced.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_soldering_profile_advanced(TemperatureType_t tipTemp, TemperatureType_t profileCurrentTargetTemp, uint32_t phaseElapsedSeconds, uint32_t phase, const uint32_t phaseTimeGoal) {
  // print temperature
  if (OLED::getRotation()) {
    OLED::setCursor(48, 0);
  } else {
    OLED::setCursor(0, 0);
  }

  OLED::printNumber(tipTemp, 3, FontStyle::SMALL);
  OLED::print(SmallSymbolSlash, FontStyle::SMALL);
  OLED::printNumber(profileCurrentTargetTemp, 3, FontStyle::SMALL);

  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    OLED::print(SmallSymbolDegF, FontStyle::SMALL);
  } else {
    OLED::print(SmallSymbolDegC, FontStyle::SMALL);
  }

  // print phase
  if (phase > 0 && phase <= getSettingValue(SettingsOptions::ProfilePhases)) {
    if (OLED::getRotation()) {
      OLED::setCursor(36, 0);
    } else {
      OLED::setCursor(55, 0);
    }
    OLED::printNumber(phase, 1, FontStyle::SMALL);
  }

  // print time progress / preheat / cooldown
  if (OLED::getRotation()) {
    OLED::setCursor(42, 8);
  } else {
    OLED::setCursor(0, 8);
  }

  if (phase == 0) {
    OLED::print(translatedString(Tr->ProfilePreheatString), FontStyle::SMALL);
  } else if (phase > getSettingValue(SettingsOptions::ProfilePhases)) {
    OLED::print(translatedString(Tr->ProfileCooldownString), FontStyle::SMALL);
  } else {
    OLED::printNumber(phaseElapsedSeconds / 60, 1, FontStyle::SMALL);
    OLED::print(SmallSymbolColon, FontStyle::SMALL);
    OLED::printNumber(phaseElapsedSeconds % 60, 2, FontStyle::SMALL, false);

    OLED::print(SmallSymbolSlash, FontStyle::SMALL);

    // blink if we can't keep up with the time goal
    if (phaseElapsedSeconds < phaseTimeGoal + 2 || (xTaskGetTickCount() / TICKS_SECOND) % 2 == 0) {
      OLED::printNumber(phaseTimeGoal / 60, 1, FontStyle::SMALL);
      OLED::print(SmallSymbolColon, FontStyle::SMALL);
      OLED::printNumber(phaseTimeGoal % 60, 2, FontStyle::SMALL, false);
    }
  }
}

#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_soldering_basic_status.cpp
================================================
#include "power.hpp"
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_soldering_basic_status(bool boostModeOn) {
  OLED::setCursor(0, 0);
  // We switch the layout direction depending on the orientation of the oled
  if (OLED::getRotation()) {
    // battery
    ui_draw_power_source_icon();
    // Space out gap between battery <-> temp
    OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    // Draw current tip temp
    ui_draw_tip_temperature(true, FontStyle::LARGE);

    // We draw boost arrow if boosting,
    // or else gap temp <-> heat indicator
    if (boostModeOn) {
      OLED::drawSymbol(2);
    } else {
      OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    }

    // Draw heating/cooling symbols
    OLED::drawHeatSymbol(X10WattsToPWM(x10WattHistory.average()));
  } else {
    // Draw heating/cooling symbols
    OLED::drawHeatSymbol(X10WattsToPWM(x10WattHistory.average()));
    // We draw boost arrow if boosting,
    // or else gap temp <-> heat indicator
    if (boostModeOn) {
      OLED::drawSymbol(2);
    } else {
      OLED::print(LargeSymbolSpace, FontStyle::LARGE);
    }
    // Draw current tip temp
    ui_draw_tip_temperature(true, FontStyle::LARGE);
    // Space out gap between battery <-> temp
    OLED::print(LargeSymbolSpace, FontStyle::LARGE);

    ui_draw_power_source_icon();
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_soldering_power_status.cpp
================================================
#include "power.hpp"
#include "ui_drawing.hpp"
#include 
#ifdef OLED_96x16

void ui_draw_soldering_power_status(bool boost_mode_on) {
  if (OLED::getRotation()) {
    OLED::setCursor(50, 0);
  } else {
    OLED::setCursor(-1, 0);
  }

  ui_draw_tip_temperature(true, FontStyle::LARGE);

  if (boost_mode_on) { // Boost mode is on
    if (OLED::getRotation()) {
      OLED::setCursor(34, 0);
    } else {
      OLED::setCursor(50, 0);
    }
    OLED::print(LargeSymbolPlus, FontStyle::LARGE);
  } else {
#ifndef NO_SLEEP_MODE
    if (getSettingValue(SettingsOptions::Sensitivity) && getSettingValue(SettingsOptions::SleepTime)) {
      if (OLED::getRotation()) {
        OLED::setCursor(32, 0);
      } else {
        OLED::setCursor(47, 0);
      }
      printCountdownUntilSleep(getSleepTimeout());
    }
#endif
    if (OLED::getRotation()) {
      OLED::setCursor(32, 8);
    } else {
      OLED::setCursor(47, 8);
    }
    OLED::print(PowerSourceNames[getPowerSourceNumber()], FontStyle::SMALL, 2);
  }

  if (OLED::getRotation()) {
    OLED::setCursor(0, 0);
  } else {
    OLED::setCursor(67, 0);
  }
  // Print wattage
  {
    uint32_t x10Watt = x10WattHistory.average();
    if (x10Watt > 999) {
      // If we exceed 99.9W we drop the decimal place to keep it all fitting
      OLED::print(SmallSymbolSpace, FontStyle::SMALL);
      OLED::printNumber(x10WattHistory.average() / 10, 3, FontStyle::SMALL);
    } else {
      OLED::printNumber(x10WattHistory.average() / 10, 2, FontStyle::SMALL);
      OLED::print(SmallSymbolDot, FontStyle::SMALL);
      OLED::printNumber(x10WattHistory.average() % 10, 1, FontStyle::SMALL);
    }
    OLED::print(SmallSymbolWatts, FontStyle::SMALL);
  }

  if (OLED::getRotation()) {
    OLED::setCursor(0, 8);
  } else {
    OLED::setCursor(67, 8);
  }
  printVoltage();
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_soldering_sleep_mode.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_soldering_detailed_sleep(TemperatureType_t tipTemp) {

  OLED::clearScreen();
  OLED::setCursor(0, 0);
  OLED::print(translatedString(Tr->SleepingAdvancedString), FontStyle::SMALL);
  OLED::setCursor(0, 8);
  OLED::print(translatedString(Tr->SleepingTipAdvancedString), FontStyle::SMALL);
  OLED::printNumber(tipTemp, 3, FontStyle::SMALL);
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    OLED::print(SmallSymbolDegF, FontStyle::SMALL);
  } else {
    OLED::print(SmallSymbolDegC, FontStyle::SMALL);
  }

  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  printVoltage();
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);

  OLED::refresh();
}

void ui_draw_soldering_basic_sleep(TemperatureType_t tipTemp) {

  OLED::clearScreen();
  OLED::setCursor(0, 0);

  OLED::print(LargeSymbolSleep, FontStyle::LARGE);
  OLED::printNumber(tipTemp, 3, FontStyle::LARGE);
  OLED::printSymbolDeg(FontStyle::EXTRAS);

  OLED::refresh();
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_temperature_change.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_temperature_change(void) {

  OLED::setCursor(0, 0);
  if (OLED::getRotation()) {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolPlus : LargeSymbolMinus, FontStyle::LARGE);
  } else {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolMinus : LargeSymbolPlus, FontStyle::LARGE);
  }

  OLED::print(LargeSymbolSpace, FontStyle::LARGE);
  OLED::printNumber(getSettingValue(SettingsOptions::SolderingTemp), 3, FontStyle::LARGE);
  OLED::printSymbolDeg(FontStyle::EXTRAS);
  OLED::print(LargeSymbolSpace, FontStyle::LARGE);
  if (OLED::getRotation()) {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolMinus : LargeSymbolPlus, FontStyle::LARGE);
  } else {
    OLED::print(getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled) ? LargeSymbolPlus : LargeSymbolMinus, FontStyle::LARGE);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_tip_temperature.cpp
================================================
#include "OperatingModeUtilities.h"
#include "OperatingModes.h"
#include "SolderingCommon.h"
#include "TipThermoModel.h"
#ifdef OLED_96x16

void ui_draw_tip_temperature(bool symbol, const FontStyle font) {
  // Draw tip temp handling unit conversion & tolerance near setpoint
  TemperatureType_t Temp = getTipTemp();

  OLED::printNumber(Temp, 3, font); // Draw the tip temp out
  if (symbol) {
    // For big font, can draw nice symbols, otherwise fall back to chars
    OLED::printSymbolDeg(font == FontStyle::LARGE ? FontStyle::EXTRAS : font);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_usb_pd_debug.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_usb_pd_debug_state(const uint16_t vbus_sense_state, const uint8_t stateNumber) {
  OLED::setCursor(0, 0);                             // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolPDDebug, FontStyle::SMALL); // Print Title
  OLED::setCursor(0, 8);                             // second line
  // Print the PD state machine
  OLED::print(SmallSymbolState, FontStyle::SMALL);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  OLED::printNumber(stateNumber, 2, FontStyle::SMALL, true);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);

  if (vbus_sense_state == 2) {
    OLED::print(SmallSymbolNoVBus, FontStyle::SMALL);
  } else if (vbus_sense_state == 1) {
    OLED::print(SmallSymbolVBus, FontStyle::SMALL);
  }
}

void ui_draw_usb_pd_debug_pdo(const uint8_t entry_num, const uint16_t min_voltage, const uint16_t max_voltage, const uint16_t current_a_x100, const uint16_t wattage) {

  OLED::setCursor(0, 0);                                   // Position the cursor at the 0,0 (top left)
  OLED::print(SmallSymbolPDDebug, FontStyle::SMALL);       // Print Title
  OLED::setCursor(0, 8);                                   // second line
  OLED::printNumber(entry_num, 2, FontStyle::SMALL, true); // print the entry number
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  if (min_voltage > 0) {
    OLED::printNumber(min_voltage, 2, FontStyle::SMALL, true); // print the voltage
    OLED::print(SmallSymbolMinus, FontStyle::SMALL);
  }
  OLED::printNumber(max_voltage, 2, FontStyle::SMALL, true); // print the voltage
  OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  OLED::print(SmallSymbolSpace, FontStyle::SMALL);
  if (wattage) {
    OLED::printNumber(wattage, 3, FontStyle::SMALL, true); // print the current in 0.1A res
    OLED::print(SmallSymbolWatts, FontStyle::SMALL);
  } else {
    OLED::printNumber(current_a_x100 / 100, 2, FontStyle::SMALL, true); // print the current in 0.1A res
    OLED::print(SmallSymbolDot, FontStyle::SMALL);
    OLED::printNumber(current_a_x100 % 100, 2, FontStyle::SMALL, false); // print the current in 0.1A res
    OLED::print(SmallSymbolAmps, FontStyle::SMALL);
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/draw_warning_undervoltage.cpp
================================================
#include "ui_drawing.hpp"
#ifdef OLED_96x16

void ui_draw_warning_undervoltage(void) {
  OLED::clearScreen();
  OLED::setCursor(0, 0);
  if (getSettingValue(SettingsOptions::DetailedSoldering)) {
    OLED::print(translatedString(Tr->UndervoltageString), FontStyle::SMALL);
    OLED::setCursor(0, 8);
    OLED::print(translatedString(Tr->InputVoltageString), FontStyle::SMALL);
    printVoltage();
    OLED::print(SmallSymbolVolts, FontStyle::SMALL);
  } else {
    OLED::print(translatedString(Tr->UVLOWarningString), FontStyle::LARGE);
  }

  OLED::refresh();
  GUIDelay();
  waitForButtonPress();
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/pre_render_assets.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_96x16
uint8_t buttonAF[sizeof(buttonA)];
uint8_t buttonBF[sizeof(buttonB)];
uint8_t disconnectedTipF[sizeof(disconnectedTip)];

void ui_pre_render_assets(void) {
  // Generate the flipped screen into ram for later use
  // flipped is generated by flipping each row
  for (int row = 0; row < 2; row++) {
    for (int x = 0; x < 42; x++) {
      buttonAF[(row * 42) + x]         = buttonA[(row * 42) + (41 - x)];
      buttonBF[(row * 42) + x]         = buttonB[(row * 42) + (41 - x)];
      disconnectedTipF[(row * 42) + x] = disconnectedTip[(row * 42) + (41 - x)];
    }
  }
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/printSleepCountdown.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"
#ifdef OLED_96x16
extern TickType_t lastMovementTime;
#ifndef NO_SLEEP_MODE
void printCountdownUntilSleep(int sleepThres) {
  /*
   * Print seconds or minutes (if > 99 seconds) until sleep
   * mode is triggered.
   */
  TickType_t lastEventTime = lastButtonTime < lastMovementTime ? lastMovementTime : lastButtonTime;
  TickType_t downCount     = sleepThres - xTaskGetTickCount() + lastEventTime;
  if (downCount > (99 * TICKS_SECOND)) {
    OLED::printNumber(downCount / 60000 + 1, 2, FontStyle::SMALL);
    OLED::print(SmallSymbolMinutes, FontStyle::SMALL);
  } else {
    OLED::printNumber(downCount / 1000 + 1, 2, FontStyle::SMALL);
    OLED::print(SmallSymbolSeconds, FontStyle::SMALL);
  }
}
#endif
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/print_voltage.cpp
================================================
#include "ui_drawing.hpp"

#ifdef OLED_96x16
void printVoltage(void) {
  uint32_t volt = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
  OLED::printNumber(volt / 10, 2, FontStyle::SMALL);
  OLED::print(SmallSymbolDot, FontStyle::SMALL);
  OLED::printNumber(volt % 10, 1, FontStyle::SMALL);
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/mono_96x16/show_warning.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"
#include "OperatingModes.h"
#ifdef OLED_96x16
bool warnUser(const char *warning, const ButtonState buttons) {
  OLED::clearScreen();
  OLED::printWholeScreen(warning);
  // Also timeout after 5 seconds
  if ((xTaskGetTickCount() - lastButtonTime) > TICKS_SECOND * 5) {
    return true;
  }
  return buttons != BUTTON_NONE;
}
#endif

================================================
FILE: source/Core/Threads/UI/drawing/ui_drawing.hpp
================================================
#ifndef UI_DRAWING_UI_DRAWING_HPP_
#define UI_DRAWING_UI_DRAWING_HPP_
#include "Buttons.hpp"
#include "OLED.hpp"
#include "OperatingModeUtilities.h"
#include "Settings.h"
#include "configuration.h"
#include 
#include 
#include 
void ui_draw_warning_undervoltage(void);
void ui_draw_power_source_icon(void);                            // Draw a single character wide power source icon
void ui_draw_tip_temperature(bool symbol, const FontStyle font); // Draw tip temp, aware of conversions
bool warnUser(const char *warning, const ButtonState buttons);   // Print a full screen warning to the user
void ui_draw_cjc_sampling(const uint8_t num_dots);               // Draws the CJC info text and progress dots
void ui_draw_debug_menu(const uint8_t item_number);              // Draws the debug menu state
void ui_draw_homescreen_detailed(TemperatureType_t tipTemp);     // Drawing the home screen -- Detailed mode
void ui_draw_homescreen_simplified(TemperatureType_t tipTemp);   // Drawing the home screen -- Simple mode
void ui_pre_render_assets(void);                                 // If any assets need to be pre-rendered into ram
// Soldering mode
void ui_draw_soldering_power_status(bool boost_mode_on);
void ui_draw_soldering_basic_status(bool boostModeOn);
void ui_draw_soldering_detailed_sleep(TemperatureType_t tipTemp);
void ui_draw_soldering_basic_sleep(TemperatureType_t tipTemp);
void ui_draw_soldering_profile_advanced(TemperatureType_t tipTemp, TemperatureType_t profileCurrentTargetTemp, uint32_t phaseElapsedSeconds, uint32_t phase, const uint32_t phaseTimeGoal);

// Temp change
void ui_draw_temperature_change(void);
// USB-PD debug
void ui_draw_usb_pd_debug_state(const uint16_t vbus_sense_state, const uint8_t stateNumber);
void ui_draw_usb_pd_debug_pdo(const uint8_t entry_num, const uint16_t min_voltage, const uint16_t max_voltage, const uint16_t current_a_x100, const uint16_t wattage);
// Utils
void printVoltage(void);
#endif // UI_DRAWING_UI_DRAWING_HPP_


================================================
FILE: source/Core/Threads/UI/logic/CJC.cpp
================================================
#include "OperatingModes.h"
#include "ui_drawing.hpp"

OperatingMode performCJCC(const ButtonState buttons, guiContext *cxt) {
  // Calibrate Cold Junction Compensation directly at boot, before internal components get warm.

  // While we wait for the pre-start checks to finish, we cant run CJC (as the pre-start checks control the tip)
  if (preStartChecks() == 0) {
    OLED::setCursor(0, 0);
    OLED::print(translatedString(Tr->CJCCalibrating), FontStyle::SMALL);
    return OperatingMode::CJCCalibration;
  }

  if (!isTipDisconnected() && abs(int(TipThermoModel::getTipInC() - getHandleTemperature(0) / 10)) < 10) {
    // Take 16 samples, only sample
    if (cxt->scratch_state.state1 < 16) {
      if ((xTaskGetTickCount() - cxt->scratch_state.state4) > TICKS_100MS) {
        cxt->scratch_state.state3 += getTipRawTemp(1);
        cxt->scratch_state.state1++;
        cxt->scratch_state.state4 = xTaskGetTickCount();
      }
      ui_draw_cjc_sampling(cxt->scratch_state.state1 / 4);
      return OperatingMode::CJCCalibration;
    }

    // If the thermo-couple at the end of the tip, and the handle are at
    // equilibrium, then the output should be zero, as there is no temperature
    // differential.

    uint16_t setOffset = TipThermoModel::convertTipRawADCTouV(cxt->scratch_state.state3 / 16, true);
    setSettingValue(SettingsOptions::CalibrationOffset, setOffset);
    if (warnUser(translatedString(Tr->CalibrationDone), buttons)) {
      // Preventing to repeat calibration at boot automatically (only one shot).
      setSettingValue(SettingsOptions::CalibrateCJC, 0);
      saveSettings();
      return OperatingMode::InitialisationDone;
    }
    return OperatingMode::CJCCalibration;
  }
  // Cant run calibration without the tip and for temps to be close
  return OperatingMode::StartupWarnings;
}


================================================
FILE: source/Core/Threads/UI/logic/DebugMenu.cpp
================================================
#include "OperatingModes.h"
#include "ui_drawing.hpp"

OperatingMode showDebugMenu(const ButtonState buttons, guiContext *cxt) {

  ui_draw_debug_menu(cxt->scratch_state.state1);

  if (buttons == BUTTON_B_SHORT) {
    cxt->transitionMode = TransitionAnimation::Up;
    return OperatingMode::HomeScreen;
  } else if (buttons == BUTTON_F_SHORT) {
    cxt->scratch_state.state1++;
#ifdef HALL_SENSOR
    cxt->scratch_state.state1 = cxt->scratch_state.state1 % 17;
#else
    cxt->scratch_state.state1 = cxt->scratch_state.state1 % 16;
#endif
  }
  return OperatingMode::DebugMenuReadout; // Stay in debug menu
}


================================================
FILE: source/Core/Threads/UI/logic/HomeScreen.cpp
================================================

#include "Buttons.hpp"
#include "OperatingModes.h"
#include "ui_drawing.hpp"

bool showExitMenuTransition = false;

OperatingMode handleHomeButtons(const ButtonState buttons, guiContext *cxt) {
  if (buttons != BUTTON_NONE && cxt->scratch_state.state1 == 0) {
    return OperatingMode::HomeScreen; // Ignore button press
  } else {
    cxt->scratch_state.state1 = 1;
  }
  switch (buttons) {
  case BUTTON_NONE:
    // Do nothing
    break;
  case BUTTON_BOTH:
    break;

  case BUTTON_B_LONG:
    cxt->transitionMode = TransitionAnimation::Down;
    return OperatingMode::DebugMenuReadout;
    break;
  case BUTTON_F_LONG:
#ifdef PROFILE_SUPPORT
    if (!isTipDisconnected()) {
      cxt->transitionMode = TransitionAnimation::Left;
      return OperatingMode::SolderingProfile;
    } else {
      return OperatingMode::HomeScreen;
    }
#else
    cxt->transitionMode = TransitionAnimation::Left;
    return OperatingMode::TemperatureAdjust;
#endif
    break;
  case BUTTON_F_SHORT:
    if (!isTipDisconnected()) {
      bool detailedView   = getSettingValue(SettingsOptions::DetailedIDLE) && getSettingValue(SettingsOptions::DetailedSoldering);
      cxt->transitionMode = detailedView ? TransitionAnimation::None : TransitionAnimation::Left;
      return OperatingMode::Soldering;
    }
    break;
  case BUTTON_B_SHORT:
    cxt->transitionMode = TransitionAnimation::Right;
    return OperatingMode::SettingsMenu;
    break;
  default:
    break;
  }
  return OperatingMode::HomeScreen;
}

OperatingMode drawHomeScreen(const ButtonState buttons, guiContext *cxt) {

  currentTempTargetDegC = 0; // ensure tip is off
  getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);
  uint32_t tipTemp = TipThermoModel::getTipInC();

  // Setup LCD Cursor location
  if (OLED::getRotation()) {
    OLED::setCursor(50, 0);
  } else {
    OLED::setCursor(-1, 0);
  }
  if (getSettingValue(SettingsOptions::DetailedIDLE)) {
    ui_draw_homescreen_detailed(tipTemp);
  } else {
    ui_draw_homescreen_simplified(tipTemp);
  }
  return handleHomeButtons(buttons, cxt);
}


================================================
FILE: source/Core/Threads/UI/logic/OperatingModes.cpp
================================================
//
// Created by Thomas White on 3/02/2023.
//

#include "OperatingModes.h"


================================================
FILE: source/Core/Threads/UI/logic/OperatingModes.h
================================================
#ifndef OPERATING_MODES_H_
#define OPERATING_MODES_H_

extern "C" {
#include "FreeRTOSConfig.h"
}
#include "Buttons.hpp"
#include "OLED.hpp"
#include "OperatingModeUtilities.h"
#include "Settings.h"
#include "TipThermoModel.h"
#include "Translation.h"
#include "Types.h"
#include "cmsis_os.h"
#include "configuration.h"
#include "history.hpp"
#include "main.hpp"
#include "power.hpp"
#include "settingsGUI.hpp"
#include "stdlib.h"
#include "string.h"
#ifdef POW_PD
#include "USBPD.h"
#include "pd.h"
#endif

enum class OperatingMode {
  StartupLogo=10,        // Showing the startup logo
  CJCCalibration=11,     // Cold Junction Calibration
  StartupWarnings=12,    // Startup checks and warnings
  InitialisationDone=13, // Special state we use just before we to home screen at first startup. Allows jumping to extra startup states
  HomeScreen=0,         // Home/Idle screen that is the main launchpad to other modes
  Soldering=1,          // Main soldering operating mode
  SolderingProfile=6,   // Soldering by following a profile, used for reflow for example
  Sleeping=3,           // Sleep state holds iron at lower sleep temp
  Hibernating=14,       // Like sleeping but keeps heater fully off until woken
  SettingsMenu=4,       // Settings Menu
  DebugMenuReadout=5,   // Debug metrics
  TemperatureAdjust=7,  // Set point temperature adjustment
  UsbPDDebug=8,         // USB PD debugging information
  ThermalRunaway=9,     // Thermal Runaway warning state.
};

enum class TransitionAnimation {
  None  = 0,
  Right = 1,
  Left  = 2,
  Down  = 3,
  Up    = 4,
};

// Generic context struct used for gui functions to be able to retain state
struct guiContext {
  TickType_t          viewEnterTime; // Set to ticks when this view state was first entered
  OperatingMode       previousMode;
  TransitionAnimation transitionMode;
  // Below is scratch state, this is retained over re-draws but blown away on state change
  struct scratch {
    uint16_t state1; // 16 bit state scratch
    uint16_t state2; // 16 bit state scratch
    uint32_t state3; // 32 bit state scratch
    uint32_t state4; // 32 bit state scratch
    uint16_t state5; // 16 bit state scratch
    uint16_t state6; // 16 bit state scratch
    uint32_t state7; // 32 bit state scratch

  } scratch_state;
};

// Main functions
OperatingMode gui_SolderingSleepingMode(const ButtonState buttons, guiContext *cxt); // Sleep mode
OperatingMode gui_solderingMode(const ButtonState buttons, guiContext *cxt);         // Main mode for hot pointy tool
OperatingMode gui_solderingTempAdjust(const ButtonState buttons, guiContext *cxt);   // For adjusting the setpoint temperature of the iron
OperatingMode drawHomeScreen(const ButtonState buttons, guiContext *cxt);            // IDLE / Home screen
OperatingMode gui_SettingsMenu(const ButtonState buttons, guiContext *cxt);          //

OperatingMode gui_solderingProfileMode(const ButtonState buttons, guiContext *cxt); // Profile mode for hot likely-not-so-pointy tool
OperatingMode performCJCC(const ButtonState buttons, guiContext *cxt);              // Used to calibrate the Cold Junction offset
OperatingMode showDebugMenu(const ButtonState buttons, guiContext *cxt);            // Debugging values
OperatingMode showPDDebug(const ButtonState buttons, guiContext *cxt);              // Debugging menu that shows PD adaptor info
OperatingMode showWarnings(const ButtonState buttons, guiContext *cxt);             // Shows user warnings if required

// Common helpers
int8_t getPowerSourceNumber(void); // Returns number ID of power source

extern uint8_t heaterThermalRunawayCounter;
#endif


================================================
FILE: source/Core/Threads/UI/logic/SettingsMenu.cpp
================================================
#include "OperatingModes.h"
#include "ScrollMessage.hpp"

#define HELP_TEXT_TIMEOUT_TICKS (TICKS_SECOND * 3)
/*
 * The settings menu is the most complex bit of GUI code we have
 * The menu consists of a two tier menu
 * Main menu -> Categories
 * Secondary menu -> Settings
 *
 * For each entry in the menu
 */

/**
 * Prints two small lines (or one line for CJK) of short description for
 * setting items and prepares cursor after it.
 * @param settingsItemIndex Index of the setting item.
 * @param cursorCharPosition Custom cursor char position to set after printing
 * description.
 */
static void printShortDescription(SettingsItemIndex settingsItemIndex, uint16_t cursorCharPosition) {
  // print short description (default single line, explicit double line)
  uint8_t shortDescIndex = static_cast(settingsItemIndex);
  OLED::printWholeScreen(translatedString(Tr->SettingsShortNames[shortDescIndex]));

  // prepare cursor for value
  // make room for scroll indicator
  OLED::setCursor(cursorCharPosition * FONT_12_WIDTH - 2, 0);
}

// Render a menu, based on the position given
// This will either draw the menu item, or the help text depending on how long its been since button press
void render_menu(const menuitem *item, guiContext *cxt) {
  // If recent interaction or not help text draw the entry
  if ((xTaskGetTickCount() - lastButtonTime < HELP_TEXT_TIMEOUT_TICKS) || item->description == 0) {

    if (item->shortDescriptionSize > 0) {
      printShortDescription(item->shortDescriptionIndex, item->shortDescriptionSize);
    }
    item->draw();
  } else {

    uint16_t *isRenderingHelp = &(cxt->scratch_state.state6);
    *isRenderingHelp          = 1;
    // Draw description
    const char *description = translatedString(Tr->SettingsDescriptions[item->description - 1]);
    drawScrollingText(description, (xTaskGetTickCount() - lastButtonTime) - HELP_TEXT_TIMEOUT_TICKS);
  }
}

uint16_t getMenuLength(const menuitem *menu, const uint16_t stop) {
  // walk this menu to find the length
  uint16_t counter = 0;
  for (uint16_t pos = 0; pos < stop; pos++) {
    // End of list
    if (menu[pos].draw == nullptr) {
      return counter;
    }
    // Otherwise increment for each visible item (null == always, or if not check function)
    if (menu[pos].isVisible == nullptr || menu[pos].isVisible()) {
      counter++;
    }
  }
  return counter;
}

OperatingMode moveToNextEntry(guiContext *cxt) {
  uint16_t *mainEntry         = &(cxt->scratch_state.state1);
  uint16_t *subEntry          = &(cxt->scratch_state.state2);
  uint16_t *currentMenuLength = &(cxt->scratch_state.state5);
  uint16_t *isRenderingHelp   = &(cxt->scratch_state.state6);

  if (*isRenderingHelp) {
    *isRenderingHelp = 0;
  } else {
    *currentMenuLength = 0; // Reset menu length
    // Scroll down
    // We can increment freely _once_
    cxt->transitionMode = TransitionAnimation::Down;
    if (*subEntry == 0) {
      (*mainEntry) += 1;

      if (rootSettingsMenu[*mainEntry].draw == nullptr) {
        // We are off the end of the menu now
        saveSettings();
        cxt->transitionMode = TransitionAnimation::Left;
        return OperatingMode::HomeScreen;
      }
      // Check if visible
      if (rootSettingsMenu[*mainEntry].isVisible != nullptr && !rootSettingsMenu[*mainEntry].isVisible()) {
        // We need to move on as this one isn't visible
        return moveToNextEntry(cxt);
      }
    } else {
      (*subEntry) += 1;

      // If the new entry is null, we need to exit
      if (subSettingsMenus[*mainEntry][(*subEntry) - 1].draw == nullptr) {
        (*subEntry)         = 0; // Reset back to the main menu
        cxt->transitionMode = TransitionAnimation::Left;
        // Have to break early to avoid the below check underflowing
        return OperatingMode::SettingsMenu;
      }
      // Check if visible
      if (subSettingsMenus[*mainEntry][(*subEntry) - 1].isVisible != nullptr && !subSettingsMenus[*mainEntry][(*subEntry) - 1].isVisible()) {
        // We need to move on as this one isn't visible
        return moveToNextEntry(cxt);
      }
    }
  }
  return OperatingMode::SettingsMenu;
}

OperatingMode gui_SettingsMenu(const ButtonState buttons, guiContext *cxt) {
  // Render out the current settings menu
  // State 1 -> Root menu
  // State 2 -> Sub entry
  // Draw main entry if sub-entry is 0, otherwise draw sub-entry

  uint16_t *mainEntry              = &(cxt->scratch_state.state1);
  uint16_t *subEntry               = &(cxt->scratch_state.state2);
  uint32_t *autoRepeatAcceleration = &(cxt->scratch_state.state3);
  uint32_t *autoRepeatTimer        = &(cxt->scratch_state.state4);
  uint16_t *currentMenuLength      = &(cxt->scratch_state.state5);
  uint16_t *isRenderingHelp        = &(cxt->scratch_state.state6);

  const menuitem *currentMenu;
  // Draw the currently on screen item
  uint16_t currentScreen;
  if (*subEntry == 0) {
    // Drawing main menu
    currentMenu   = rootSettingsMenu;
    currentScreen = *mainEntry;
  } else {
    // Drawing sub menu
    currentMenu   = subSettingsMenus[*mainEntry];
    currentScreen = (*subEntry) - 1;
  }
  render_menu(&(currentMenu[currentScreen]), cxt);

  // Update the cached menu length if unknown
  if (*currentMenuLength == 0) {
    // We walk the current menu to find the length
    *currentMenuLength = getMenuLength(currentMenu, 128 /* Max length of any menu*/);
  }

  if (*isRenderingHelp == 0) {
    //  Draw scroll

    // Get virtual pos by counting entries from start to _here_
    uint16_t currentVirtualPosition = getMenuLength(currentMenu, currentScreen + 1);
    if (currentVirtualPosition > 0) {
      currentVirtualPosition--;
    }

    // The height of the indicator is screen res height / total menu entries
    uint8_t indicatorHeight = OLED_HEIGHT / *currentMenuLength;
    if (indicatorHeight == 0) {
      indicatorHeight = 1; // always at least 1 pixel
    }

    uint16_t position = (OLED_HEIGHT * (uint16_t)currentVirtualPosition) / *currentMenuLength;

    bool showScrollbar = true;

    // Store if its the last option for this setting
    bool isLastOptionForSetting = false;
    if ((int)currentMenu[currentScreen].autoSettingOption < (int)SettingsOptions::SettingsOptionsLength) {
      isLastOptionForSetting = isLastSettingValue(currentMenu[currentScreen].autoSettingOption);
    }

    // Last settings menu entry, reset scroll show back so it flashes
    if (isLastOptionForSetting) {
      showScrollbar = false;
    }

    // Or Flash it
    showScrollbar |= (xTaskGetTickCount() % (TICKS_SECOND / 4) < (TICKS_SECOND / 8));

    if (showScrollbar) {
      OLED::drawScrollIndicator((uint8_t)position, indicatorHeight);
    }
  }

  // Now handle user button input
  auto callIncrementHandler = [&]() {
    if (currentMenu[currentScreen].incrementHandler != nullptr) {
      currentMenu[currentScreen].incrementHandler();
    } else if ((int)currentMenu[currentScreen].autoSettingOption < (int)SettingsOptions::SettingsOptionsLength) {
      nextSettingValue(currentMenu[currentScreen].autoSettingOption);
    }
    return false;
  };

  // Modify a button value before processing a key press if setting to swap buttons is enabled
  bool    swapButtonSettings = getSettingValue(SettingsOptions::ReverseButtonSettings);
  uint8_t buttonPress;
  switch (buttons) {
  case BUTTON_F_LONG:
    buttonPress = swapButtonSettings ? BUTTON_B_LONG : BUTTON_F_LONG;
    break;
  case BUTTON_F_SHORT:
    buttonPress = swapButtonSettings ? BUTTON_B_SHORT : BUTTON_F_SHORT;
    break;
  case BUTTON_B_LONG:
    buttonPress = swapButtonSettings ? BUTTON_F_LONG : BUTTON_B_LONG;
    break;
  case BUTTON_B_SHORT:
    buttonPress = swapButtonSettings ? BUTTON_F_SHORT : BUTTON_B_SHORT;
    break;
  default:
    buttonPress = buttons;
    break;
  }

  OperatingMode newMode = OperatingMode::SettingsMenu;
  switch (buttonPress) {
  case BUTTON_NONE:
    (*autoRepeatAcceleration) = 0; // reset acceleration
    (*autoRepeatTimer)        = 0; // reset acceleration
    break;
  case BUTTON_BOTH:
    if (*subEntry == 0) {
      saveSettings();
      cxt->transitionMode = TransitionAnimation::Left;
      return OperatingMode::HomeScreen;
    } else {
      cxt->transitionMode = TransitionAnimation::Left;
      *subEntry           = 0;
      return OperatingMode::SettingsMenu;
    }
    break;
  case BUTTON_F_LONG:
    if (xTaskGetTickCount() + (*autoRepeatAcceleration) > (*autoRepeatTimer) + PRESS_ACCEL_INTERVAL_MAX) {
      callIncrementHandler();
      // Update the check for if its the last version
      bool isLastOptionForSetting = false;
      if ((int)currentMenu[currentScreen].autoSettingOption < (int)SettingsOptions::SettingsOptionsLength) {
        isLastOptionForSetting = isLastSettingValue(currentMenu[currentScreen].autoSettingOption);
      }

      if (isLastOptionForSetting) {
        (*autoRepeatTimer) = TICKS_SECOND * 2;
      } else {
        (*autoRepeatTimer) = 0;
      }
      (*autoRepeatTimer) += xTaskGetTickCount();
      (*autoRepeatAcceleration) += PRESS_ACCEL_STEP;
      *currentMenuLength = 0; // Reset incase menu visible changes
    }
    break;
  case BUTTON_F_SHORT:
    // Increment setting
    if (*isRenderingHelp) {
      *isRenderingHelp = 0;
    } else {
      *currentMenuLength = 0; // Reset incase menu visible changes
      if (*subEntry == 0) {
        // In a root menu, if its null handler we enter the menu
        if (currentMenu[currentScreen].incrementHandler != nullptr) {
          currentMenu[currentScreen].incrementHandler();
        } else {
          (*subEntry) += 1;
          cxt->transitionMode = TransitionAnimation::Right;
        }
      } else {
        callIncrementHandler();
      }
    }
    break;
  case BUTTON_B_LONG:
    if (xTaskGetTickCount() + (*autoRepeatAcceleration) > (*autoRepeatTimer) + PRESS_ACCEL_INTERVAL_MAX) {
      (*autoRepeatTimer) = xTaskGetTickCount();
      (*autoRepeatAcceleration) += PRESS_ACCEL_STEP;
    } else {
      break;
    }
    /* Fall through*/
  case BUTTON_B_SHORT:
    // Increment menu item
    newMode = moveToNextEntry(cxt);
    break;
  default:
    break;
  }

  if ((PRESS_ACCEL_INTERVAL_MAX - (*autoRepeatAcceleration)) < PRESS_ACCEL_INTERVAL_MIN) {
    (*autoRepeatAcceleration) = PRESS_ACCEL_INTERVAL_MAX - PRESS_ACCEL_INTERVAL_MIN;
  }

  // Otherwise we stay put for next render iteration
  return newMode;
}


================================================
FILE: source/Core/Threads/UI/logic/ShowStartupWarnings.cpp
================================================
#include "FS2711.hpp"
#include "HUB238.hpp"
#include "OperatingModes.h"
#include "ui_drawing.hpp"
OperatingMode showWarnings(const ButtonState buttons, guiContext *cxt) {
  // Display alert if settings were reset

  switch (cxt->scratch_state.state1) {
  case 0: // Settings reset warning
    if (settingsWereReset) {
      if (warnUser(translatedString(Tr->SettingsResetMessage), buttons)) {
        settingsWereReset         = false;
        cxt->scratch_state.state1 = 1;
      }
    } else {
      cxt->scratch_state.state1 = 1;
    }
    break;
  case 1: // Device validations
#ifdef DEVICE_HAS_VALIDATION_SUPPORT
    if (getDeviceValidationStatus()) {
      // Warn user this device might be counterfeit
      if (warnUser(translatedString(Tr->DeviceFailedValidationWarning), buttons)) {
        cxt->scratch_state.state1 = 2;
      }
    } else {
      cxt->scratch_state.state1 = 2;
    }
#else
    cxt->scratch_state.state1 = 2;
#endif
    break;
  case 2: // Accelerometer detection
#ifdef NO_ACCEL
    cxt->scratch_state.state1 = 3;
#else
    if (DetectedAccelerometerVersion == AccelType::Scanning) {
      break;
    }
    // Display alert if accelerometer is not detected
    if (DetectedAccelerometerVersion == AccelType::None) {
      if (getSettingValue(SettingsOptions::AccelMissingWarningCounter) < 2) {

        if (warnUser(translatedString(Tr->NoAccelerometerMessage), buttons)) {
          cxt->scratch_state.state1 = 3;
          nextSettingValue(SettingsOptions::AccelMissingWarningCounter);
          saveSettings();
        }
      } else {
        cxt->scratch_state.state1 = 3;
      }
    } else {
      cxt->scratch_state.state1 = 3;
    }
#endif

    break;
  case 3:

#ifdef POW_PD
    // We expect pd to be present
    if (!USBPowerDelivery::fusbPresent()) {
      if (getSettingValue(SettingsOptions::PDMissingWarningCounter) < 2) {
        if (warnUser(translatedString(Tr->NoPowerDeliveryMessage), buttons)) {
          nextSettingValue(SettingsOptions::PDMissingWarningCounter);
          saveSettings();
          cxt->scratch_state.state1 = 4;
        }
      } else {
        cxt->scratch_state.state1 = 4;
      }
    } else {
      cxt->scratch_state.state1 = 4;
    }
#else
#if POW_PD_EXT == 1
    if (!hub238_probe()) {
      if (getSettingValue(SettingsOptions::PDMissingWarningCounter) < 2) {
        if (warnUser(translatedString(Tr->NoPowerDeliveryMessage), buttons)) {
          cxt->scratch_state.state1 = 4;
          nextSettingValue(SettingsOptions::PDMissingWarningCounter);
          saveSettings();
        }
      } else {
        cxt->scratch_state.state1 = 4;
      }
    } else {
      cxt->scratch_state.state1 = 4;
    }
#else
#if POW_PD_EXT == 2
    if (!FS2711::probe()) {
      if (getSettingValue(SettingsOptions::PDMissingWarningCounter) < 2) {
        if (warnUser(translatedString(Tr->NoPowerDeliveryMessage), buttons)) {
          cxt->scratch_state.state1 = 4;
          nextSettingValue(SettingsOptions::PDMissingWarningCounter);
          saveSettings();
        }
      } else {
        cxt->scratch_state.state1 = 4;
      }
    } else {
      cxt->scratch_state.state1 = 4;
    }
#else
    cxt->scratch_state.state1 = 4;
#endif /*POW_PD_EXT==1*/
#endif /*POW_PD_EXT==2*/
#endif /*POW_PD*/

    break;
  default:
    // We are off the end, warnings done
    return OperatingMode::StartupLogo;
  }

  return OperatingMode::StartupWarnings; // Stay in warnings
}


================================================
FILE: source/Core/Threads/UI/logic/Sleep.cpp
================================================
#include "OperatingModes.h"
#include "ui_drawing.hpp"
OperatingMode gui_SolderingSleepingMode(const ButtonState buttons, guiContext *cxt) {
#ifdef NO_SLEEP_MODE
  return OperatingMode::Soldering;
#endif
  // Drop to sleep temperature and display until movement or button press

  // user moved or pressed a button, go back to soldering
  // If in the first two seconds we disable this to let accelerometer warm up

#ifdef POW_DC
  if (checkForUnderVoltage()) {
    return OperatingMode::HomeScreen; // return non-zero on error
  }
#endif

  if (cxt->scratch_state.state4) {
    // Hibernating mode
    currentTempTargetDegC = 0;
  } else {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      currentTempTargetDegC = TipThermoModel::convertFtoC(min(getSettingValue(SettingsOptions::SleepTemp), getSettingValue(SettingsOptions::SolderingTemp)));
    } else {
      currentTempTargetDegC = min(getSettingValue(SettingsOptions::SleepTemp), getSettingValue(SettingsOptions::SolderingTemp));
    }
  }
  // draw the lcd
  uint16_t tipTemp = getSettingValue(SettingsOptions::TemperatureInF) ? TipThermoModel::getTipInF() : TipThermoModel::getTipInC();

  if (getSettingValue(SettingsOptions::DetailedSoldering)) {
    ui_draw_soldering_detailed_sleep(tipTemp);
  } else {
    ui_draw_soldering_basic_sleep(tipTemp);
  }

  if (!shouldBeSleeping()) {
    return cxt->previousMode;
  }

  if (shouldShutdown()) {
    // shutdown
    currentTempTargetDegC = 0;
    return OperatingMode::HomeScreen;
  }
  if (cxt->scratch_state.state4) {
    return OperatingMode::Hibernating;
  } else {
    return OperatingMode::Sleeping;
  }
}


================================================
FILE: source/Core/Threads/UI/logic/Soldering.cpp
================================================

#include "OperatingModes.h"
#include "SolderingCommon.h"
#include "ui_drawing.hpp"
// State 1 = button locking  (0:unlocked+released, 1:unlocked, 2:locked, 3:locked+released)
// State 2 = boost mode
// State 3 = buzzer timer

OperatingMode handleSolderingButtons(const ButtonState buttons, guiContext *cxt) {
  if (cxt->scratch_state.state1 >= 2) {
    // Buttons are currently locked
    if (buttons == BUTTON_BOTH_LONG) {
      if (cxt->scratch_state.state1 == 3) {
        // Unlocking
        if (warnUser(translatedString(Tr->UnlockingKeysString), buttons)) {
          cxt->scratch_state.state1 = 1;
          cxt->scratch_state.state7 = 0;
        }
      } else {
        warnUser(translatedString(Tr->LockingKeysString), buttons);
      }
      return OperatingMode::Soldering;
    }
    if (cxt->scratch_state.state7 != 0) {
      // show locked until timer is up
      if (xTaskGetTickCount() >= cxt->scratch_state.state7) {
        cxt->scratch_state.state7 = 0;
      } else {
        warnUser(translatedString(Tr->WarningKeysLockedString), buttons);
        return OperatingMode::Soldering;
      }
    }
    switch (buttons) {
    case BUTTON_NONE:
      cxt->scratch_state.state1 = 3;
      cxt->scratch_state.state2 = 0;
      break;
    case BUTTON_F_LONG:
      if (getSettingValue(SettingsOptions::BoostTemp) && (getSettingValue(SettingsOptions::LockingMode) == lockingMode_t::BOOST)) {
        cxt->scratch_state.state2 = 1;
        break;
      }
    /*Fall through*/
    default: // Set timer for and display a lock warning
      cxt->scratch_state.state7 = xTaskGetTickCount() + TICKS_SECOND;
      warnUser(translatedString(Tr->WarningKeysLockedString), buttons);
      break;
    }
    return OperatingMode::Soldering;
  }

  bool detailedView = getSettingValue(SettingsOptions::DetailedIDLE) && getSettingValue(SettingsOptions::DetailedSoldering);
  // otherwise we are unlocked
  switch (buttons) {
  case BUTTON_NONE:
    cxt->scratch_state.state2 = 0;
    cxt->scratch_state.state1 = 0;
    break;
  case BUTTON_BOTH:
  /*Fall through*/
  case BUTTON_B_LONG:
    cxt->transitionMode = detailedView ? TransitionAnimation::None : TransitionAnimation::Right;
    return OperatingMode::HomeScreen;
  case BUTTON_F_LONG:
    // if boost mode is enabled turn it on
    if (getSettingValue(SettingsOptions::BoostTemp)) {
      cxt->scratch_state.state2 = 1;
    }
    break;
  case BUTTON_F_SHORT:
  case BUTTON_B_SHORT:
    cxt->transitionMode = TransitionAnimation::Left;
    return OperatingMode::TemperatureAdjust;
  case BUTTON_BOTH_LONG:
    if (getSettingValue(SettingsOptions::LockingMode)) {
      // Lock buttons
      if (cxt->scratch_state.state1 == 0) {
        if (warnUser(translatedString(Tr->LockingKeysString), buttons)) {
          cxt->scratch_state.state1 = 2;
        }
      } else {
        // FIXME should be WarningKeysUnlockedString
        warnUser(translatedString(Tr->UnlockingKeysString), buttons);
      }
    }
    break;
  default:
    break;
  }
  return OperatingMode::Soldering;
}

OperatingMode gui_solderingMode(const ButtonState buttons, guiContext *cxt) {
  /*
   * * Soldering (gui_solderingMode)
   * -> Main loop where we draw temp, and animations
   * --> User presses buttons and they goto the temperature adjust screen
   * ---> Display the current setpoint temperature
   * ---> Use buttons to change forward and back on temperature
   * ---> Both buttons or timeout for exiting
   * --> Long hold front button to enter boost mode
   * ---> Just temporarily sets the system into the alternate temperature for
   * PID control
   * --> Long hold back button to exit
   * --> Double button to exit
   * --> Long hold double button to toggle key lock
   */

  // Update the setpoints for the temperature
  if (cxt->scratch_state.state2) {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      currentTempTargetDegC = TipThermoModel::convertFtoC(getSettingValue(SettingsOptions::BoostTemp));
    } else {
      currentTempTargetDegC = (getSettingValue(SettingsOptions::BoostTemp));
    }
  } else {
    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      currentTempTargetDegC = TipThermoModel::convertFtoC(getSettingValue(SettingsOptions::SolderingTemp));
    } else {
      currentTempTargetDegC = (getSettingValue(SettingsOptions::SolderingTemp));
    }
  }

  // Update status
  int error = currentTempTargetDegC - TipThermoModel::getTipInC();
  if (error >= -10 && error <= 10) {
    // converged
    if (!cxt->scratch_state.state5) {
      setBuzzer(true);
      cxt->scratch_state.state3 = xTaskGetTickCount() + TICKS_SECOND / 3;
      cxt->scratch_state.state5 = true;
    }
    setStatusLED(LED_HOT);
  } else {
    setStatusLED(LED_HEATING);
    cxt->scratch_state.state5 = false;
  }
  if (cxt->scratch_state.state3 != 0 && xTaskGetTickCount() >= cxt->scratch_state.state3) {
    setBuzzer(false);
  }

  // Draw in the screen details
  if (getSettingValue(SettingsOptions::DetailedSoldering)) {
    ui_draw_soldering_power_status(cxt->scratch_state.state2);
  } else {
    ui_draw_soldering_basic_status(cxt->scratch_state.state2);
  }

  bool detailedView = getSettingValue(SettingsOptions::DetailedIDLE) && getSettingValue(SettingsOptions::DetailedSoldering);
  // Check if we should bail due to undervoltage for example
  if (checkExitSoldering()) {
    setBuzzer(false);
    cxt->transitionMode = detailedView ? TransitionAnimation::None : TransitionAnimation::Right;
    return OperatingMode::HomeScreen;
  }
#ifdef NO_SLEEP_MODE

  if (shouldShutdown()) {
    // shutdown
    currentTempTargetDegC = 0;
    cxt->transitionMode   = detailedView ? TransitionAnimation::None : TransitionAnimation::Right;
    return OperatingMode::HomeScreen;
  }
#endif
  if (shouldBeSleeping()) {
    return OperatingMode::Sleeping;
  }

  if (heaterThermalRunawayCounter > 8) {
    currentTempTargetDegC       = 0; // heater control off
    heaterThermalRunawayCounter = 0;
    cxt->transitionMode         = TransitionAnimation::Right;
    return OperatingMode::ThermalRunaway;
  }
  return handleSolderingButtons(buttons, cxt);
}


================================================
FILE: source/Core/Threads/UI/logic/SolderingProfile.cpp
================================================

#include "OperatingModes.h"
#include "SolderingCommon.h"
#include "ui_drawing.hpp"

OperatingMode gui_solderingProfileMode(const ButtonState buttons, guiContext *cxt) {
  /*
   * * Soldering
   * -> Main loop where we draw temp, and animations
   * --> Long hold back button to exit
   * --> Double button to exit
   */

  uint16_t tipTemp = 0;

  // If this is during init, start at preheat
  if (cxt->scratch_state.state1 == 0) {
    cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePreheatTemp);
  }
  uint16_t phaseTicksPerDegree      = TICKS_SECOND / getSettingValue(SettingsOptions::ProfilePreheatSpeed);
  uint16_t profileCurrentTargetTemp = 0;

  switch (buttons) {
  case BUTTON_BOTH:
  case BUTTON_B_LONG:
    cxt->transitionMode = TransitionAnimation::Right;
    return OperatingMode::HomeScreen; // exit on back long hold
  case BUTTON_F_LONG:
  case BUTTON_F_SHORT:
  case BUTTON_B_SHORT:
  case BUTTON_NONE:
    // Not used yet
    break;
  default:
    break;
  }

  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    tipTemp = TipThermoModel::getTipInF();
  } else {
    tipTemp = TipThermoModel::getTipInC();
  }
  // If time of entering is unknown; then we start now
  if (cxt->scratch_state.state3 == 0) {
    cxt->scratch_state.state3 = xTaskGetTickCount();
  }

  // if start temp is unknown (preheat), we're setting it now
  if (cxt->scratch_state.state6 == 0) {
    cxt->scratch_state.state6 = tipTemp;
    // if this is hotter than the preheat temperature, we should fail
    if (cxt->scratch_state.state6 >= cxt->scratch_state.state5) {
      warnUser(translatedString(Tr->TooHotToStartProfileWarning), buttons);
      return OperatingMode::HomeScreen;
    }
  }
  uint16_t phaseElapsedSeconds = (xTaskGetTickCount() - cxt->scratch_state.state3) / TICKS_SECOND;

  // Have we finished this phase?
  // Check if we have hit our temperature target in either direction.
  bool phaseTargetReached = false;
  if (cxt->scratch_state.state6 < cxt->scratch_state.state5 && tipTemp >= cxt->scratch_state.state5) {
    phaseTargetReached = true;
  } else if (cxt->scratch_state.state6 > cxt->scratch_state.state5 && tipTemp <= cxt->scratch_state.state5) {
    phaseTargetReached = true;
  } else if (tipTemp == cxt->scratch_state.state5) {
    phaseTargetReached = true;
  }

  // If we both hit the temperature target and enough time has passed, phase complete.
  if (phaseElapsedSeconds >= cxt->scratch_state.state2 && phaseTargetReached) {
    cxt->scratch_state.state1++;
    cxt->scratch_state.state6 = cxt->scratch_state.state5;
    cxt->scratch_state.state3 = xTaskGetTickCount();
    phaseElapsedSeconds       = 0;
    if (cxt->scratch_state.state1 > getSettingValue(SettingsOptions::ProfilePhases)) {
      // done with all phases, lets go to cooldown
      cxt->scratch_state.state2 = 0;
      cxt->scratch_state.state5 = 0;
      phaseTicksPerDegree       = TICKS_SECOND / getSettingValue(SettingsOptions::ProfileCooldownSpeed);
    } else {
      // set up next phase
      switch (cxt->scratch_state.state1) {
      case 1:
        cxt->scratch_state.state2 = getSettingValue(SettingsOptions::ProfilePhase1Duration);
        cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePhase1Temp);
        break;
      case 2:
        cxt->scratch_state.state2 = getSettingValue(SettingsOptions::ProfilePhase2Duration);
        cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePhase2Temp);
        break;
      case 3:
        cxt->scratch_state.state2 = getSettingValue(SettingsOptions::ProfilePhase3Duration);
        cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePhase3Temp);
        break;
      case 4:
        cxt->scratch_state.state2 = getSettingValue(SettingsOptions::ProfilePhase4Duration);
        cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePhase4Temp);
        break;
      case 5:
        cxt->scratch_state.state2 = getSettingValue(SettingsOptions::ProfilePhase5Duration);
        cxt->scratch_state.state5 = getSettingValue(SettingsOptions::ProfilePhase5Temp);
        break;
      default:
        break;
      }
      if (cxt->scratch_state.state6 < cxt->scratch_state.state5) {
        phaseTicksPerDegree = (cxt->scratch_state.state2 * TICKS_SECOND) / (cxt->scratch_state.state5 - cxt->scratch_state.state6);
      } else {
        phaseTicksPerDegree = (cxt->scratch_state.state2 * TICKS_SECOND) / (cxt->scratch_state.state6 - cxt->scratch_state.state5);
      }
    }
  }

  // cooldown phase done?
  if (cxt->scratch_state.state1 > getSettingValue(SettingsOptions::ProfilePhases)) {
    if (TipThermoModel::getTipInC() < 55) {
      // we're done, let the buzzer beep too
      setStatusLED(LED_STANDBY);
      if (cxt->scratch_state.state4 == 0) {
        setBuzzer(true);
        cxt->scratch_state.state4 = xTaskGetTickCount() + TICKS_SECOND / 3;
      }
    }
  }

  // determine current target temp
  if (cxt->scratch_state.state6 < cxt->scratch_state.state5) {
    profileCurrentTargetTemp = cxt->scratch_state.state6 + ((xTaskGetTickCount() - cxt->viewEnterTime) / phaseTicksPerDegree);
    if (profileCurrentTargetTemp > cxt->scratch_state.state5) {
      profileCurrentTargetTemp = cxt->scratch_state.state5;
    }
  } else if (cxt->scratch_state.state6 > cxt->scratch_state.state5) {
    profileCurrentTargetTemp = cxt->scratch_state.state6 - ((xTaskGetTickCount() - cxt->viewEnterTime) / phaseTicksPerDegree);
    // Chance of an overflow when ramping up is basically zero, but chance of an underflow here is quite high. If the target underflowed, snap it back.
    if (profileCurrentTargetTemp < cxt->scratch_state.state5 || profileCurrentTargetTemp > cxt->scratch_state.state6) {
      profileCurrentTargetTemp = cxt->scratch_state.state5;
    }
  } else {
    profileCurrentTargetTemp = cxt->scratch_state.state5;
  }

  // Draw in the screen details
  if (getSettingValue(SettingsOptions::DetailedSoldering)) {
    ui_draw_soldering_profile_advanced(tipTemp, profileCurrentTargetTemp, phaseElapsedSeconds, cxt->scratch_state.state1, cxt->scratch_state.state2);
    ui_draw_soldering_power_status(false);
  } else {
    ui_draw_soldering_basic_status(false);
  }

  // Update the setpoints for the temperature
  if (getSettingValue(SettingsOptions::TemperatureInF)) {
    currentTempTargetDegC = TipThermoModel::convertFtoC(profileCurrentTargetTemp);
  } else {
    currentTempTargetDegC = profileCurrentTargetTemp;
  }

  if (checkExitSoldering() || (cxt->scratch_state.state4 != 0 && xTaskGetTickCount() >= cxt->scratch_state.state4)) {
    setBuzzer(false);
    return OperatingMode::HomeScreen;
  }
  if (heaterThermalRunawayCounter > 8) {
    currentTempTargetDegC       = 0; // heater control off
    heaterThermalRunawayCounter = 0;
    return OperatingMode::ThermalRunaway;
  }

  // Update LED status
  if (cxt->scratch_state.state1 == 0) {
    setStatusLED(LED_HEATING);
  } else if (cxt->scratch_state.state1 > getSettingValue(SettingsOptions::ProfilePhases)) {
    setStatusLED(LED_COOLING_STILL_HOT);
  } else {
    setStatusLED(LED_HOT);
  }
  return OperatingMode::SolderingProfile;
}


================================================
FILE: source/Core/Threads/UI/logic/TemperatureAdjust.cpp
================================================
#include "OperatingModes.h"
#include "ui_drawing.hpp"

OperatingMode gui_solderingTempAdjust(const ButtonState buttonIn, guiContext *cxt) {

  currentTempTargetDegC              = 0; // Turn off heater while adjusting temp
  uint16_t   *waitForRelease         = &(cxt->scratch_state.state1);
  uint32_t   *autoRepeatTimer        = &(cxt->scratch_state.state3);
  uint16_t   *autoRepeatAcceleration = &(cxt->scratch_state.state2);
  ButtonState buttons                = buttonIn;
  if (*waitForRelease == 0) {
    // When we first enter we wait for the user to release buttons before enabling changes
    if (buttons != BUTTON_NONE) {
      buttons = BUTTON_NONE;
    } else {
      (*waitForRelease)++;
    }
  }

  int16_t delta = 0;
  switch (buttons) {
  case BUTTON_NONE:
    // stay
    (*autoRepeatAcceleration) = 0;
    break;
  case BUTTON_BOTH:
    // exit
    saveSettings();
    cxt->transitionMode = TransitionAnimation::Right;
    return cxt->previousMode;
  case BUTTON_B_LONG:
    if (xTaskGetTickCount() - (*autoRepeatTimer) + (*autoRepeatAcceleration) > PRESS_ACCEL_INTERVAL_MAX) {
      delta              = -getSettingValue(SettingsOptions::TempChangeLongStep);
      (*autoRepeatTimer) = xTaskGetTickCount();
      (*autoRepeatAcceleration) += PRESS_ACCEL_STEP;
    }
    break;
  case BUTTON_B_SHORT:
    delta = -getSettingValue(SettingsOptions::TempChangeShortStep);
    break;
  case BUTTON_F_LONG:
    if (xTaskGetTickCount() - (*autoRepeatTimer) + (*autoRepeatAcceleration) > PRESS_ACCEL_INTERVAL_MAX) {
      delta              = getSettingValue(SettingsOptions::TempChangeLongStep);
      (*autoRepeatTimer) = xTaskGetTickCount();
      (*autoRepeatAcceleration) += PRESS_ACCEL_STEP;
    }
    break;
  case BUTTON_F_SHORT:
    delta = getSettingValue(SettingsOptions::TempChangeShortStep);
    break;
  default:
    break;
  }
  if ((PRESS_ACCEL_INTERVAL_MAX - (*autoRepeatAcceleration)) < PRESS_ACCEL_INTERVAL_MIN) {
    (*autoRepeatAcceleration) = PRESS_ACCEL_INTERVAL_MAX - PRESS_ACCEL_INTERVAL_MIN;
  }
  // If buttons are flipped; flip the delta
  if (getSettingValue(SettingsOptions::ReverseButtonTempChangeEnabled)) {
    delta = -delta;
  }
  if (delta != 0) {
    // constrain between the set temp limits, i.e. 10-450 C
    int16_t newTemp = getSettingValue(SettingsOptions::SolderingTemp);
    newTemp += delta;
    // Round to nearest increment of delta
    delta   = abs(delta);
    newTemp = (newTemp / delta) * delta;

    if (getSettingValue(SettingsOptions::TemperatureInF)) {
      if (newTemp > MAX_TEMP_F) {
        newTemp = MAX_TEMP_F;
      } else if (newTemp < MIN_TEMP_F) {
        newTemp = MIN_TEMP_F;
      }
    } else {
      if (newTemp > MAX_TEMP_C) {
        newTemp = MAX_TEMP_C;
      } else if (newTemp < MIN_TEMP_C) {
        newTemp = MIN_TEMP_C;
      }
    }
    setSettingValue(SettingsOptions::SolderingTemp, (uint16_t)newTemp);
  }
  ui_draw_temperature_change();

  if (xTaskGetTickCount() - lastButtonTime > (TICKS_SECOND * 3)) {
    saveSettings();
    cxt->transitionMode = TransitionAnimation::Right;
    return cxt->previousMode; // exit if user just doesn't press anything for a bit
  }
  return OperatingMode::TemperatureAdjust; // Stay in temp adjust
}


================================================
FILE: source/Core/Threads/UI/logic/USBPDDebug_FS2711.cpp
================================================
#include "FS2711.hpp"
#include "OperatingModes.h"
#include "stdbool.h"
#include "ui_drawing.hpp"
#if POW_PD_EXT == 2
#ifdef HAS_POWER_DEBUG_MENU

OperatingMode showPDDebug(const ButtonState buttons, guiContext *cxt) {
  // Print out the USB-PD state
  // Basically this is like the Debug menu, but instead we want to print out the PD status
  uint16_t *screen = &(cxt->scratch_state.state1);

  if (*screen > 7) {
    *screen = 0;
  }
  if (*screen == 0) {
    // Print the PD Debug state
    fs2711_state_t state = FS2711::debug_get_state();

    ui_draw_usb_pd_debug_state(0, state.pdo_num);
  } else {

    // Print out the Proposed power options one by one
    uint16_t max_voltage = FS2711::debug_pdo_max_voltage(*screen - 1);
    if (max_voltage == 0) {
      *screen += 1;
    } else {
      uint16_t min_voltage = FS2711::debug_pdo_min_voltage(*screen - 1);
      uint16_t current     = FS2711::debug_pdo_source_current(*screen - 1);
      uint16_t pdo_type    = FS2711::debug_pdo_type(*screen - 1);
      if (pdo_type != 1) {
        min_voltage = 0;
      }

      ui_draw_usb_pd_debug_pdo(*screen, min_voltage / 1000, max_voltage / 1000, current * 1, 0);
    }
  }

  OLED::refresh();

  if (buttons == BUTTON_B_SHORT) {
    return OperatingMode::InitialisationDone;
  } else if (buttons == BUTTON_F_SHORT) {
    *screen++;
  }

  return OperatingMode::UsbPDDebug;
}
#endif
#endif


================================================
FILE: source/Core/Threads/UI/logic/USBPDDebug_FUSB.cpp
================================================
#include "OperatingModes.h"
#include "ui_drawing.hpp"
#ifdef POW_PD
#include "pd.h"
#ifdef HAS_POWER_DEBUG_MENU
OperatingMode showPDDebug(const ButtonState buttons, guiContext *cxt) {
  // Print out the USB-PD state
  // Basically this is like the Debug menu, but instead we want to print out the PD status
  uint16_t *screen = &(cxt->scratch_state.state1);

  if ((*screen) == 0) {
    // Print the PD state machine
    uint8_t vbusState = 0;
    if (USBPowerDelivery::fusbPresent()) {
      if (USBPowerDelivery::negotiationComplete() || (xTaskGetTickCount() > (TICKS_SECOND * 10))) {
        if (!USBPowerDelivery::isVBUSConnected()) {
          vbusState = 2;
        } else {
          vbusState = 1;
        }
      }
    }
    ui_draw_usb_pd_debug_state(vbusState, USBPowerDelivery::getStateNumber());
  } else {
    // Print out the Proposed power options one by one
    auto lastCaps           = USBPowerDelivery::getLastSeenCapabilities();
    bool sourceIsEPRCapable = lastCaps[0] & PD_PDO_SRC_FIXED_EPR_CAPABLE;
    if (((*screen) - 1) < 11) {
      int voltage_mv     = 0;
      int min_voltage    = 0;
      int current_a_x100 = 0;
      int wattage        = 0;

      if ((lastCaps[(*screen) - 1] & PD_PDO_TYPE) == PD_PDO_TYPE_FIXED) {
        voltage_mv     = PD_PDV2MV(PD_PDO_SRC_FIXED_VOLTAGE_GET(lastCaps[(*screen) - 1])); // voltage in mV units
        current_a_x100 = PD_PDO_SRC_FIXED_CURRENT_GET(lastCaps[(*screen) - 1]);            // current in 10mA units
      } else if ((lastCaps[(*screen) - 1] & PD_PDO_TYPE) == PD_PDO_TYPE_AUGMENTED) {
        if (sourceIsEPRCapable) {
          if ((lastCaps[(*screen) - 1] & PD_APDO_TYPE) == PD_APDO_TYPE_AVS) {
            voltage_mv  = PD_PAV2MV(PD_APDO_AVS_MAX_VOLTAGE_GET(lastCaps[(*screen) - 1]));
            min_voltage = PD_PAV2MV(PD_APDO_PPS_MIN_VOLTAGE_GET(lastCaps[(*screen) - 1]));
            // Last value is wattage
            wattage = PD_APDO_AVS_MAX_POWER_GET(lastCaps[(*screen) - 1]);
          } else if (((lastCaps[(*screen) - 1] & PD_APDO_TYPE) == PD_APDO_TYPE_PPS)) {
            voltage_mv     = PD_PAV2MV(PD_APDO_PPS_MAX_VOLTAGE_GET(lastCaps[(*screen) - 1]));
            min_voltage    = PD_PAV2MV(PD_APDO_PPS_MIN_VOLTAGE_GET(lastCaps[(*screen) - 1]));
            current_a_x100 = PD_PAI2CA(PD_APDO_PPS_CURRENT_GET(lastCaps[(*screen) - 1])); // max current in 10mA units
          }
        } else {
          // Doesn't have EPR support. So treat as PPS
          // https://github.com/Ralim/IronOS/issues/1906
          voltage_mv     = PD_PAV2MV(PD_APDO_PPS_MAX_VOLTAGE_GET(lastCaps[(*screen) - 1]));
          min_voltage    = PD_PAV2MV(PD_APDO_PPS_MIN_VOLTAGE_GET(lastCaps[(*screen) - 1]));
          current_a_x100 = PD_PAI2CA(PD_APDO_PPS_CURRENT_GET(lastCaps[(*screen) - 1])); // max current in 10mA units
        }
      }
      // Skip not used entries
      if (voltage_mv == 0) {
        (*screen) += 1;
      } else {
        ui_draw_usb_pd_debug_pdo(*screen, min_voltage / 1000, voltage_mv / 1000, current_a_x100, wattage);
      }
    } else {
      (*screen) = 0;
    }
  }
  if (buttons == BUTTON_B_SHORT) {
    return OperatingMode::InitialisationDone;
  } else if (buttons == BUTTON_F_SHORT) {
    (*screen) += 1;
  }
  return OperatingMode::UsbPDDebug;
}
#endif
#endif


================================================
FILE: source/Core/Threads/UI/logic/USBPDDebug_HUSB238.cpp
================================================
#include "HUB238.hpp"
#include "OperatingModes.h"
#include "ui_drawing.hpp"
#if POW_PD_EXT == 1
#ifdef HAS_POWER_DEBUG_MENU
OperatingMode showPDDebug(const ButtonState buttons, guiContext *cxt) {
  // Print out the USB-PD state
  // Basically this is like the Debug menu, but instead we want to print out the PD status
  uint16_t *screen = &(cxt->scratch_state.state1);

  if (*screen > 6) {
    *screen = 0;
  }
  if (*screen == 0) {
    // Print the PD Debug state
    uint16_t temp = hub238_debug_state();
    ui_draw_usb_pd_debug_state(0, temp);
  } else {

    // Print out the Proposed power options one by one
    const uint8_t voltages[]  = {5, 9, 12, 15, 18, 20};
    uint16_t      voltage     = voltages[*screen - 1];
    uint16_t      currentx100 = hub238_getVoltagePDOCurrent(voltage);

    ui_draw_usb_pd_debug_pdo(*screen, 0, voltage, currentx100, 0);
  }

  if (buttons == BUTTON_B_SHORT) {
    return OperatingMode::InitialisationDone;
  } else if (buttons == BUTTON_F_SHORT) {
    *screen++;
  }

  return OperatingMode::UsbPDDebug;
}
#endif
#endif


================================================
FILE: source/Core/Threads/UI/logic/utils/GUIDelay.cpp
================================================

#include "OperatingModeUtilities.h"

void GUIDelay() {
  // Called in all UI looping tasks,
  // This limits the re-draw rate to the LCD and also lets the DMA run
  // As the gui task can very easily fill this bus with transactions, which will
  // prevent the movement detection from running
  vTaskDelay(5 * TICKS_10MS);
}

================================================
FILE: source/Core/Threads/UI/logic/utils/OperatingModeUtilities.h
================================================
#ifndef OPERATING_MODE_UTILITIES_H_
#define OPERATING_MODE_UTILITIES_H_
#include "Buttons.hpp"
#include "OLED.hpp"
#include "Settings.h"
#include 

void     GUIDelay();                               //
bool     checkForUnderVoltage(void);               //
uint32_t getSleepTimeout(void);                    //
uint32_t getHallEffectSleepTimeout(void);          //
bool     shouldBeSleeping();                       //
bool     shouldShutdown(void);                     //
void     printVoltage(void);                       //
bool     checkForUnderVoltage(void);               //
uint16_t min(uint16_t a, uint16_t b);              //
void     printCountdownUntilSleep(int sleepThres); //
#endif


================================================
FILE: source/Core/Threads/UI/logic/utils/SolderingCommon.cpp
================================================
//
// Created by laura on 24.04.23.
//

#include "SolderingCommon.h"
#include "OperatingModes.h"
#include "Types.h"
#include "configuration.h"
#include "history.hpp"
#include "ui_drawing.hpp"

extern uint8_t heaterThermalRunawayCounter;

bool checkExitSoldering(void) {
#ifdef POW_DC
  // Undervoltage test
  if (checkForUnderVoltage()) {
    lastButtonTime = xTaskGetTickCount();
    return true;
  }
#endif

#ifdef ACCEL_EXITS_ON_MOVEMENT
  // If the accel works in reverse where movement will cause exiting the soldering mode
  if (getSettingValue(Sensitivity)) {
    if (lastMovementTime) {
      if (lastMovementTime > TICKS_SECOND * 10) {
        // If we have moved recently; in the last second
        // Then exit soldering mode

        // Movement occurred in last update
        if (((TickType_t)(xTaskGetTickCount() - lastMovementTime)) < (TickType_t)(TICKS_SECOND / 5)) {
          currentTempTargetDegC = 0;
          lastMovementTime      = 0;
          return true;
        }
      }
    }
  }
#endif

  // If we have tripped thermal runaway, turn off heater and show warning

  return false;
}

int8_t getPowerSourceNumber(void) {
  int8_t sourceNumber = 0;
  if (getIsPoweredByDCIN()) {
    sourceNumber = 0;
  } else {
    // We are not powered via DC, so want to display the appropriate state for PD or QC
    bool poweredbyPD        = false;
    bool pdHasVBUSConnected = false;
#ifdef POW_PD
    if (USBPowerDelivery::fusbPresent()) {
      // We are PD capable
      if (USBPowerDelivery::negotiationComplete()) {
        // We are powered via PD
        poweredbyPD = true;
#ifdef VBUS_MOD_TEST
        pdHasVBUSConnected = USBPowerDelivery::isVBUSConnected();
#endif
      }
    }
#endif
    if (poweredbyPD) {
      if (pdHasVBUSConnected) {
        sourceNumber = 2;
      } else {
        sourceNumber = 3;
      }
    } else {
      sourceNumber = 1;
    }
  }
  return sourceNumber;
}

// Returns temperature of the tip in *C/*F (based on user settings)
TemperatureType_t getTipTemp(void) {
#ifdef FILTER_DISPLAYED_TIP_TEMP
  static history Filter_Temp;
  TemperatureType_t                                            reading = getSettingValue(SettingsOptions::TemperatureInF) ? TipThermoModel::getTipInF() : TipThermoModel::getTipInC();
  Filter_Temp.update(reading);
  return Filter_Temp.average();

#else
  return getSettingValue(SettingsOptions::TemperatureInF) ? TipThermoModel::getTipInF() : TipThermoModel::getTipInC();
#endif
}


================================================
FILE: source/Core/Threads/UI/logic/utils/SolderingCommon.h
================================================
#include "Types.h"
#include 
#ifndef SOLDERING_COMMON_H_
#define SOLDERING_COMMON_H_

bool              checkExitSoldering();
TemperatureType_t getTipTemp(void);

#endif // SOLDERING_COMMON_H_


================================================
FILE: source/Core/Threads/UI/logic/utils/checkUndervoltage.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"
#include "configuration.h"
#include "ui_drawing.hpp"
#ifdef POW_DC
extern volatile TemperatureType_t currentTempTargetDegC;
// returns true if undervoltage has occured
bool checkForUnderVoltage(void) {
  if (!getIsPoweredByDCIN()) {
    return false;
  }
  uint16_t v = getInputVoltageX10(getSettingValue(SettingsOptions::VoltageDiv), 0);

  // Dont check for first 2 seconds while the ADC stabilizes and the DMA fills
  // the buffer
  if (xTaskGetTickCount() > (TICKS_SECOND * 2)) {
    if ((v < lookupVoltageLevel())) {
      currentTempTargetDegC = 0;
      ui_draw_warning_undervoltage();
      return true;
    }
  }
  return false;
}
#endif

================================================
FILE: source/Core/Threads/UI/logic/utils/getHallEffectSleepTimeout.cpp
================================================
#include "OperatingModeUtilities.h"

#ifndef NO_SLEEP_MODE
#ifdef HALL_SENSOR
uint32_t getHallEffectSleepTimeout(void) {
  if (getSettingValue(SettingsOptions::HallEffectSensitivity) && getSettingValue(SettingsOptions::HallEffectSleepTime)) {
    uint32_t sleepThres = getSettingValue(SettingsOptions::HallEffectSleepTime) * 5 * TICKS_SECOND;
    return sleepThres;
  }
  return TICKS_SECOND;
}
#endif
#endif


================================================
FILE: source/Core/Threads/UI/logic/utils/getSleepTimeout.cpp
================================================
#include "OperatingModeUtilities.h"

#ifndef NO_SLEEP_MODE

uint32_t getSleepTimeout(void) {

  if (getSettingValue(SettingsOptions::Sensitivity) && getSettingValue(SettingsOptions::SleepTime)) {

    uint32_t sleepThres = 0;
    if (getSettingValue(SettingsOptions::SleepTime) < 6) {
      sleepThres = getSettingValue(SettingsOptions::SleepTime) * 10 * 1000;
    } else {
      sleepThres = (getSettingValue(SettingsOptions::SleepTime) - 5) * 60 * 1000;
    }
    return sleepThres;
  }
  return 0;
}
#endif


================================================
FILE: source/Core/Threads/UI/logic/utils/min.cpp
================================================


#include "OperatingModeUtilities.h"
#include 
uint16_t min(uint16_t a, uint16_t b) {
  if (a > b) {
    return b;
  } else {
    return a;
  }
}


================================================
FILE: source/Core/Threads/UI/logic/utils/shouldDeviceShutdown.cpp
================================================
#include "OperatingModeUtilities.h"

extern TickType_t lastMovementTime;
extern TickType_t lastHallEffectSleepStart;
#include "Buttons.hpp"

bool shouldShutdown(void) {
  if (getSettingValue(SettingsOptions::ShutdownTime)) { // only allow shutdown exit if time > 0
    if (lastMovementTime) {
      if (((TickType_t)(xTaskGetTickCount() - lastMovementTime)) > (TickType_t)(getSettingValue(SettingsOptions::ShutdownTime) * TICKS_MIN)) {
        return true;
      }
    }
    if (lastHallEffectSleepStart) {
      if (((TickType_t)(xTaskGetTickCount() - lastHallEffectSleepStart)) > (TickType_t)(getSettingValue(SettingsOptions::ShutdownTime) * TICKS_MIN)) {
        return true;
      }
    }
  }
  if (getButtonState() == BUTTON_B_LONG) { // allow also if back button is pressed long
    return true;
  }
  return false;
}


================================================
FILE: source/Core/Threads/UI/logic/utils/shouldDeviceSleep.cpp
================================================
#include "Buttons.hpp"
#include "OperatingModeUtilities.h"

TickType_t        lastHallEffectSleepStart = 0;
extern TickType_t lastMovementTime;

bool shouldBeSleeping() {
#ifndef NO_SLEEP_MODE
  // Return true if the iron should be in sleep mode
  if (getSettingValue(SettingsOptions::Sensitivity) && getSettingValue(SettingsOptions::SleepTime)) {
    // In auto start we are asleep until movement
    if (lastMovementTime == 0 && lastButtonTime == 0) {
      return true;
    }
    if (lastMovementTime > 0 || lastButtonTime > 0) {
      if (((xTaskGetTickCount() - lastMovementTime) > getSleepTimeout()) && ((xTaskGetTickCount() - lastButtonTime) > getSleepTimeout())) {
        return true;
      }
    }
  }

#ifdef HALL_SENSOR
  // If the hall effect sensor is enabled in the build, check if its over
  // threshold, and if so then we force sleep
  if (getHallSensorFitted() && lookupHallEffectThreshold()) {
    int16_t hallEffectStrength = getRawHallEffect();
    if (hallEffectStrength < 0) {
      hallEffectStrength = -hallEffectStrength;
    }
    // Have absolute value of measure of magnetic field strength
    if (hallEffectStrength > lookupHallEffectThreshold()) {
      if (lastHallEffectSleepStart == 0) {
        lastHallEffectSleepStart = xTaskGetTickCount();
      }
      if ((xTaskGetTickCount() - lastHallEffectSleepStart) > getHallEffectSleepTimeout()) {
        return true;
      }
    } else {
      lastHallEffectSleepStart = 0;
    }
  }
#endif
#endif
  return false;
}


================================================
FILE: source/Core/brieflz/README.md
================================================
This directory contains file originally by other people.


## BriefLZ

- `brieflz_btparse.h`
- `brieflz_hashbucket.h`
- `brieflz_lazy.h`
- `brieflz_leparse.h`
- `brieflz.c`
- `depack.c`

The above files are originally obtained from https://github.com/jibsen/brieflz
(commit 0ab07a5).

### License:

```
The zlib License (Zlib)

Copyright (c) 2002-2020 Joergen Ibsen

This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.

Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must
     not claim that you wrote the original software. If you use this
     software in a product, an acknowledgment in the product
     documentation would be appreciated but is not required.

  2. Altered source versions must be plainly marked as such, and must
     not be misrepresented as being the original software.

  3. This notice may not be removed or altered from any source
     distribution.
```


================================================
FILE: source/Core/brieflz/brieflz.c
================================================
//
// BriefLZ - small fast Lempel-Ziv
//
// C packer
//
// Copyright (c) 2002-2020 Joergen Ibsen
//
// This software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
//   1. The origin of this software must not be misrepresented; you must
//      not claim that you wrote the original software. If you use this
//      software in a product, an acknowledgment in the product
//      documentation would be appreciated but is not required.
//
//   2. Altered source versions must be plainly marked as such, and must
//      not be misrepresented as being the original software.
//
//   3. This notice may not be removed or altered from any source
//      distribution.
//

#include "brieflz.h"

#include 
#include 
#include 

#if _MSC_VER >= 1400
#include 
#define BLZ_BUILTIN_MSVC
#elif defined(__clang__) && defined(__has_builtin)
#if __has_builtin(__builtin_clz)
#define BLZ_BUILTIN_GCC
#endif
#elif __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
#define BLZ_BUILTIN_GCC
#endif

// Type used to store values in workmem.
//
// This is used to store positions and lengths, so src_size has to be within
// the range of this type.
//
typedef uint32_t blz_word;

#define BLZ_WORD_MAX UINT32_MAX

// Number of bits of hash to use for lookup.
//
// The size of the lookup table (and thus workmem) depends on this.
//
// Values between 10 and 18 work well. Lower values generally make compression
// speed faster but ratio worse. The default value 17 (128k entries) is a
// compromise.
//
#ifndef BLZ_HASH_BITS
#define BLZ_HASH_BITS 17
#endif

#define LOOKUP_SIZE (1UL << BLZ_HASH_BITS)

#define NO_MATCH_POS ((blz_word) - 1)

// Internal data structure
struct blz_state {
  unsigned char *next_out;
  unsigned char *tag_out;
  unsigned int   tag;
  int            bits_left;
};

// clang-format off
#if !defined(BLZ_NO_LUT)
static const unsigned short blz_gamma_lookup[512][2] = {
    {0, 0},       {0, 0},

    {0x00, 2},    {0x02, 2},

    {0x04, 4},    {0x06, 4},    {0x0C, 4},    {0x0E, 4},

    {0x14, 6},    {0x16, 6},    {0x1C, 6},    {0x1E, 6},    {0x34, 6},    {0x36, 6},    {0x3C, 6},    {0x3E, 6},

    {0x54, 8},    {0x56, 8},    {0x5C, 8},    {0x5E, 8},    {0x74, 8},    {0x76, 8},    {0x7C, 8},    {0x7E, 8},    {0xD4, 8},    {0xD6, 8},    {0xDC, 8},    {0xDE, 8},    {0xF4, 8},    {0xF6, 8},
    {0xFC, 8},    {0xFE, 8},

    {0x154, 10},  {0x156, 10},  {0x15C, 10},  {0x15E, 10},  {0x174, 10},  {0x176, 10},  {0x17C, 10},  {0x17E, 10},  {0x1D4, 10},  {0x1D6, 10},  {0x1DC, 10},  {0x1DE, 10},  {0x1F4, 10},  {0x1F6, 10},
    {0x1FC, 10},  {0x1FE, 10},  {0x354, 10},  {0x356, 10},  {0x35C, 10},  {0x35E, 10},  {0x374, 10},  {0x376, 10},  {0x37C, 10},  {0x37E, 10},  {0x3D4, 10},  {0x3D6, 10},  {0x3DC, 10},  {0x3DE, 10},
    {0x3F4, 10},  {0x3F6, 10},  {0x3FC, 10},  {0x3FE, 10},

    {0x554, 12},  {0x556, 12},  {0x55C, 12},  {0x55E, 12},  {0x574, 12},  {0x576, 12},  {0x57C, 12},  {0x57E, 12},  {0x5D4, 12},  {0x5D6, 12},  {0x5DC, 12},  {0x5DE, 12},  {0x5F4, 12},  {0x5F6, 12},
    {0x5FC, 12},  {0x5FE, 12},  {0x754, 12},  {0x756, 12},  {0x75C, 12},  {0x75E, 12},  {0x774, 12},  {0x776, 12},  {0x77C, 12},  {0x77E, 12},  {0x7D4, 12},  {0x7D6, 12},  {0x7DC, 12},  {0x7DE, 12},
    {0x7F4, 12},  {0x7F6, 12},  {0x7FC, 12},  {0x7FE, 12},  {0xD54, 12},  {0xD56, 12},  {0xD5C, 12},  {0xD5E, 12},  {0xD74, 12},  {0xD76, 12},  {0xD7C, 12},  {0xD7E, 12},  {0xDD4, 12},  {0xDD6, 12},
    {0xDDC, 12},  {0xDDE, 12},  {0xDF4, 12},  {0xDF6, 12},  {0xDFC, 12},  {0xDFE, 12},  {0xF54, 12},  {0xF56, 12},  {0xF5C, 12},  {0xF5E, 12},  {0xF74, 12},  {0xF76, 12},  {0xF7C, 12},  {0xF7E, 12},
    {0xFD4, 12},  {0xFD6, 12},  {0xFDC, 12},  {0xFDE, 12},  {0xFF4, 12},  {0xFF6, 12},  {0xFFC, 12},  {0xFFE, 12},

    {0x1554, 14}, {0x1556, 14}, {0x155C, 14}, {0x155E, 14}, {0x1574, 14}, {0x1576, 14}, {0x157C, 14}, {0x157E, 14}, {0x15D4, 14}, {0x15D6, 14}, {0x15DC, 14}, {0x15DE, 14}, {0x15F4, 14}, {0x15F6, 14},
    {0x15FC, 14}, {0x15FE, 14}, {0x1754, 14}, {0x1756, 14}, {0x175C, 14}, {0x175E, 14}, {0x1774, 14}, {0x1776, 14}, {0x177C, 14}, {0x177E, 14}, {0x17D4, 14}, {0x17D6, 14}, {0x17DC, 14}, {0x17DE, 14},
    {0x17F4, 14}, {0x17F6, 14}, {0x17FC, 14}, {0x17FE, 14}, {0x1D54, 14}, {0x1D56, 14}, {0x1D5C, 14}, {0x1D5E, 14}, {0x1D74, 14}, {0x1D76, 14}, {0x1D7C, 14}, {0x1D7E, 14}, {0x1DD4, 14}, {0x1DD6, 14},
    {0x1DDC, 14}, {0x1DDE, 14}, {0x1DF4, 14}, {0x1DF6, 14}, {0x1DFC, 14}, {0x1DFE, 14}, {0x1F54, 14}, {0x1F56, 14}, {0x1F5C, 14}, {0x1F5E, 14}, {0x1F74, 14}, {0x1F76, 14}, {0x1F7C, 14}, {0x1F7E, 14},
    {0x1FD4, 14}, {0x1FD6, 14}, {0x1FDC, 14}, {0x1FDE, 14}, {0x1FF4, 14}, {0x1FF6, 14}, {0x1FFC, 14}, {0x1FFE, 14}, {0x3554, 14}, {0x3556, 14}, {0x355C, 14}, {0x355E, 14}, {0x3574, 14}, {0x3576, 14},
    {0x357C, 14}, {0x357E, 14}, {0x35D4, 14}, {0x35D6, 14}, {0x35DC, 14}, {0x35DE, 14}, {0x35F4, 14}, {0x35F6, 14}, {0x35FC, 14}, {0x35FE, 14}, {0x3754, 14}, {0x3756, 14}, {0x375C, 14}, {0x375E, 14},
    {0x3774, 14}, {0x3776, 14}, {0x377C, 14}, {0x377E, 14}, {0x37D4, 14}, {0x37D6, 14}, {0x37DC, 14}, {0x37DE, 14}, {0x37F4, 14}, {0x37F6, 14}, {0x37FC, 14}, {0x37FE, 14}, {0x3D54, 14}, {0x3D56, 14},
    {0x3D5C, 14}, {0x3D5E, 14}, {0x3D74, 14}, {0x3D76, 14}, {0x3D7C, 14}, {0x3D7E, 14}, {0x3DD4, 14}, {0x3DD6, 14}, {0x3DDC, 14}, {0x3DDE, 14}, {0x3DF4, 14}, {0x3DF6, 14}, {0x3DFC, 14}, {0x3DFE, 14},
    {0x3F54, 14}, {0x3F56, 14}, {0x3F5C, 14}, {0x3F5E, 14}, {0x3F74, 14}, {0x3F76, 14}, {0x3F7C, 14}, {0x3F7E, 14}, {0x3FD4, 14}, {0x3FD6, 14}, {0x3FDC, 14}, {0x3FDE, 14}, {0x3FF4, 14}, {0x3FF6, 14},
    {0x3FFC, 14}, {0x3FFE, 14},

    {0x5554, 16}, {0x5556, 16}, {0x555C, 16}, {0x555E, 16}, {0x5574, 16}, {0x5576, 16}, {0x557C, 16}, {0x557E, 16}, {0x55D4, 16}, {0x55D6, 16}, {0x55DC, 16}, {0x55DE, 16}, {0x55F4, 16}, {0x55F6, 16},
    {0x55FC, 16}, {0x55FE, 16}, {0x5754, 16}, {0x5756, 16}, {0x575C, 16}, {0x575E, 16}, {0x5774, 16}, {0x5776, 16}, {0x577C, 16}, {0x577E, 16}, {0x57D4, 16}, {0x57D6, 16}, {0x57DC, 16}, {0x57DE, 16},
    {0x57F4, 16}, {0x57F6, 16}, {0x57FC, 16}, {0x57FE, 16}, {0x5D54, 16}, {0x5D56, 16}, {0x5D5C, 16}, {0x5D5E, 16}, {0x5D74, 16}, {0x5D76, 16}, {0x5D7C, 16}, {0x5D7E, 16}, {0x5DD4, 16}, {0x5DD6, 16},
    {0x5DDC, 16}, {0x5DDE, 16}, {0x5DF4, 16}, {0x5DF6, 16}, {0x5DFC, 16}, {0x5DFE, 16}, {0x5F54, 16}, {0x5F56, 16}, {0x5F5C, 16}, {0x5F5E, 16}, {0x5F74, 16}, {0x5F76, 16}, {0x5F7C, 16}, {0x5F7E, 16},
    {0x5FD4, 16}, {0x5FD6, 16}, {0x5FDC, 16}, {0x5FDE, 16}, {0x5FF4, 16}, {0x5FF6, 16}, {0x5FFC, 16}, {0x5FFE, 16}, {0x7554, 16}, {0x7556, 16}, {0x755C, 16}, {0x755E, 16}, {0x7574, 16}, {0x7576, 16},
    {0x757C, 16}, {0x757E, 16}, {0x75D4, 16}, {0x75D6, 16}, {0x75DC, 16}, {0x75DE, 16}, {0x75F4, 16}, {0x75F6, 16}, {0x75FC, 16}, {0x75FE, 16}, {0x7754, 16}, {0x7756, 16}, {0x775C, 16}, {0x775E, 16},
    {0x7774, 16}, {0x7776, 16}, {0x777C, 16}, {0x777E, 16}, {0x77D4, 16}, {0x77D6, 16}, {0x77DC, 16}, {0x77DE, 16}, {0x77F4, 16}, {0x77F6, 16}, {0x77FC, 16}, {0x77FE, 16}, {0x7D54, 16}, {0x7D56, 16},
    {0x7D5C, 16}, {0x7D5E, 16}, {0x7D74, 16}, {0x7D76, 16}, {0x7D7C, 16}, {0x7D7E, 16}, {0x7DD4, 16}, {0x7DD6, 16}, {0x7DDC, 16}, {0x7DDE, 16}, {0x7DF4, 16}, {0x7DF6, 16}, {0x7DFC, 16}, {0x7DFE, 16},
    {0x7F54, 16}, {0x7F56, 16}, {0x7F5C, 16}, {0x7F5E, 16}, {0x7F74, 16}, {0x7F76, 16}, {0x7F7C, 16}, {0x7F7E, 16}, {0x7FD4, 16}, {0x7FD6, 16}, {0x7FDC, 16}, {0x7FDE, 16}, {0x7FF4, 16}, {0x7FF6, 16},
    {0x7FFC, 16}, {0x7FFE, 16}, {0xD554, 16}, {0xD556, 16}, {0xD55C, 16}, {0xD55E, 16}, {0xD574, 16}, {0xD576, 16}, {0xD57C, 16}, {0xD57E, 16}, {0xD5D4, 16}, {0xD5D6, 16}, {0xD5DC, 16}, {0xD5DE, 16},
    {0xD5F4, 16}, {0xD5F6, 16}, {0xD5FC, 16}, {0xD5FE, 16}, {0xD754, 16}, {0xD756, 16}, {0xD75C, 16}, {0xD75E, 16}, {0xD774, 16}, {0xD776, 16}, {0xD77C, 16}, {0xD77E, 16}, {0xD7D4, 16}, {0xD7D6, 16},
    {0xD7DC, 16}, {0xD7DE, 16}, {0xD7F4, 16}, {0xD7F6, 16}, {0xD7FC, 16}, {0xD7FE, 16}, {0xDD54, 16}, {0xDD56, 16}, {0xDD5C, 16}, {0xDD5E, 16}, {0xDD74, 16}, {0xDD76, 16}, {0xDD7C, 16}, {0xDD7E, 16},
    {0xDDD4, 16}, {0xDDD6, 16}, {0xDDDC, 16}, {0xDDDE, 16}, {0xDDF4, 16}, {0xDDF6, 16}, {0xDDFC, 16}, {0xDDFE, 16}, {0xDF54, 16}, {0xDF56, 16}, {0xDF5C, 16}, {0xDF5E, 16}, {0xDF74, 16}, {0xDF76, 16},
    {0xDF7C, 16}, {0xDF7E, 16}, {0xDFD4, 16}, {0xDFD6, 16}, {0xDFDC, 16}, {0xDFDE, 16}, {0xDFF4, 16}, {0xDFF6, 16}, {0xDFFC, 16}, {0xDFFE, 16}, {0xF554, 16}, {0xF556, 16}, {0xF55C, 16}, {0xF55E, 16},
    {0xF574, 16}, {0xF576, 16}, {0xF57C, 16}, {0xF57E, 16}, {0xF5D4, 16}, {0xF5D6, 16}, {0xF5DC, 16}, {0xF5DE, 16}, {0xF5F4, 16}, {0xF5F6, 16}, {0xF5FC, 16}, {0xF5FE, 16}, {0xF754, 16}, {0xF756, 16},
    {0xF75C, 16}, {0xF75E, 16}, {0xF774, 16}, {0xF776, 16}, {0xF77C, 16}, {0xF77E, 16}, {0xF7D4, 16}, {0xF7D6, 16}, {0xF7DC, 16}, {0xF7DE, 16}, {0xF7F4, 16}, {0xF7F6, 16}, {0xF7FC, 16}, {0xF7FE, 16},
    {0xFD54, 16}, {0xFD56, 16}, {0xFD5C, 16}, {0xFD5E, 16}, {0xFD74, 16}, {0xFD76, 16}, {0xFD7C, 16}, {0xFD7E, 16}, {0xFDD4, 16}, {0xFDD6, 16}, {0xFDDC, 16}, {0xFDDE, 16}, {0xFDF4, 16}, {0xFDF6, 16},
    {0xFDFC, 16}, {0xFDFE, 16}, {0xFF54, 16}, {0xFF56, 16}, {0xFF5C, 16}, {0xFF5E, 16}, {0xFF74, 16}, {0xFF76, 16}, {0xFF7C, 16}, {0xFF7E, 16}, {0xFFD4, 16}, {0xFFD6, 16}, {0xFFDC, 16}, {0xFFDE, 16},
    {0xFFF4, 16}, {0xFFF6, 16}, {0xFFFC, 16}, {0xFFFE, 16}};
#endif
// clang-format on

static int blz_log2(unsigned long n) {
  assert(n > 0);

#if defined(BLZ_BUILTIN_MSVC)
  unsigned long msb_pos;
  _BitScanReverse(&msb_pos, n);
  return (int)msb_pos;
#elif defined(BLZ_BUILTIN_GCC)
  return (int)sizeof(n) * CHAR_BIT - 1 - __builtin_clzl(n);
#else
  int bits = 0;

  while (n >>= 1) {
    ++bits;
  }

  return bits;
#endif
}

static unsigned long blz_gamma_cost(unsigned long n) {
  assert(n >= 2);

  return 2 * (unsigned long)blz_log2(n);
}

static unsigned long blz_match_cost(unsigned long pos, unsigned long len) { return 1 + blz_gamma_cost(len - 2) + blz_gamma_cost((pos >> 8) + 2) + 8; }

// Heuristic to compare matches
static int blz_match_better(unsigned long cur, unsigned long new_pos, unsigned long new_len, unsigned long pos, unsigned long len) {
  const unsigned long offs     = cur - pos - 1;
  const unsigned long new_offs = cur - new_pos - 1;

  return (new_len > len + 1) || (new_len >= len + 1 && new_offs / 8 <= offs);
}

// Heuristic to compare match with match at next position
static int blz_next_match_better(unsigned long cur, unsigned long new_pos, unsigned long new_len, unsigned long pos, unsigned long len) {
  const unsigned long offs     = cur - pos - 1;
  const unsigned long new_offs = cur + 1 - new_pos - 1;

  return (new_len > len + 1 && new_offs / 8 < offs) || (new_len > len && new_offs < offs) || (new_len >= len && new_offs < offs / 4);
}

static void blz_putbit(struct blz_state *bs, unsigned int bit) {
  // Check if tag is full
  if (!bs->bits_left--) {
    // Store tag
    bs->tag_out[0] = bs->tag & 0x00FF;
    bs->tag_out[1] = (bs->tag >> 8) & 0x00FF;

    // Init next tag
    bs->tag_out = bs->next_out;
    bs->next_out += 2;
    bs->bits_left = 15;
  }

  // Shift bit into tag
  bs->tag = (bs->tag << 1) + bit;
}

static void blz_putbits(struct blz_state *bs, unsigned long bits, int num) {
  assert(num >= 0 && num <= 16);
  assert((bits & (~0UL << num)) == 0);

  // Shift num bits into tag
  unsigned long tag = ((unsigned long)bs->tag << num) | bits;
  bs->tag           = (unsigned int)tag;

  // Check if tag is full
  if (bs->bits_left < num) {
    const unsigned int top16 = (unsigned int)(tag >> (num - bs->bits_left));

    // Store tag
    bs->tag_out[0] = top16 & 0x00FF;
    bs->tag_out[1] = (top16 >> 8) & 0x00FF;

    // Init next tag
    bs->tag_out = bs->next_out;
    bs->next_out += 2;

    bs->bits_left += 16;
  }

  bs->bits_left -= num;
}

// Encode val using a universal code based on Elias gamma.
//
// This outputs each bit of val (after the leading one bit) as a pair where
// the first bit is the value, and the second is zero if this was the last
// pair, and one otherwise.
//
//     2 =  10 ->    00
//     3 =  11 ->    10
//     4 = 100 -> 01 00
//     5 = 101 -> 01 10
//     6 = 110 -> 11 00
//     ...
//
// On modern hardware this variant is slower to decode because we cannot count
// the leading zeroes to get the number of value bits and then read them
// directly. However on constrained hardware, it has the advantage of being
// decodable using only one variable (register) and a tiny loop:
//
//     result = 1;
//     do { result = (result << 1) + getbit(); } while (getbit());
//
// Strictly speaking, this is order-1 exp-Golomb, where we interleave the
// value bits with the bits of the unary coding of the length, but I've always
// known it as the gamma2 code. I am not sure where it originated from, but I
// can see I used it in aPLib around 1998.
//
static void blz_putgamma(struct blz_state *bs, unsigned long val) {
  assert(val >= 2);

#if !defined(BLZ_NO_LUT)
  // Output small values using lookup
  if (val < 512) {
    const unsigned int bits  = blz_gamma_lookup[val][0];
    const unsigned int shift = blz_gamma_lookup[val][1];

    blz_putbits(bs, bits, (int)shift);

    return;
  }
#endif

  // Create a mask for the second-highest bit of val
#if defined(BLZ_BUILTIN_MSVC)
  unsigned long msb_pos;
  _BitScanReverse(&msb_pos, val);
  unsigned long mask = 1UL << (msb_pos - 1);
#elif defined(BLZ_BUILTIN_GCC)
  unsigned long mask = 1UL << ((int)sizeof(val) * CHAR_BIT - 2 - __builtin_clzl(val));
#else
  unsigned long mask = val >> 1;

  // Clear bits except highest
  while (mask & (mask - 1)) {
    mask &= mask - 1;
  }
#endif

  // Output gamma2-encoded bits
  blz_putbit(bs, (val & mask) ? 1 : 0);

  while (mask >>= 1) {
    blz_putbit(bs, 1);
    blz_putbit(bs, (val & mask) ? 1 : 0);
  }

  blz_putbit(bs, 0);
}

static unsigned char *blz_finalize(struct blz_state *bs) {
  // Trailing one bit to delimit any literal tags
  blz_putbit(bs, 1);

  // Shift last tag into position and store
  bs->tag <<= bs->bits_left;
  bs->tag_out[0] = bs->tag & 0x00FF;
  bs->tag_out[1] = (bs->tag >> 8) & 0x00FF;

  // Return pointer one past end of output
  return bs->next_out;
}

// Hash four bytes starting a p.
//
// This is Fibonacci hashing, also known as Knuth's multiplicative hash. The
// constant is a prime close to 2^32/phi.
//
static unsigned long blz_hash4_bits(const unsigned char *p, int bits) {
  assert(bits > 0 && bits <= 32);

  uint32_t val = (uint32_t)p[0] | ((uint32_t)p[1] << 8) | ((uint32_t)p[2] << 16) | ((uint32_t)p[3] << 24);

  return (val * UINT32_C(2654435761)) >> (32 - bits);
}

static unsigned long blz_hash4(const unsigned char *p) { return blz_hash4_bits(p, BLZ_HASH_BITS); }

size_t blz_max_packed_size(size_t src_size) { return src_size + src_size / 8 + 64; }

size_t blz_workmem_size(size_t src_size) {
  (void)src_size;

  return LOOKUP_SIZE * sizeof(blz_word);
}

// Simple LZSS using hashing.
//
// The lookup table stores the previous position in the input that had a given
// hash value, or NO_MATCH_POS if none.
//
unsigned long blz_pack(const void *src, void *dst, unsigned long src_size, void *workmem) {
  struct blz_state           bs;
  blz_word *const            lookup         = (blz_word *)workmem;
  const unsigned char *const in             = (const unsigned char *)src;
  const unsigned long        last_match_pos = src_size > 4 ? src_size - 4 : 0;
  unsigned long              hash_pos       = 0;
  unsigned long              cur            = 0;

  assert(src_size < BLZ_WORD_MAX);

  // Check for empty input
  if (src_size == 0) {
    return 0;
  }

  bs.next_out = (unsigned char *)dst;

  // First byte verbatim
  *bs.next_out++ = in[0];

  // Check for 1 byte input
  if (src_size == 1) {
    return 1;
  }

  // Initialize first tag
  bs.tag_out = bs.next_out;
  bs.next_out += 2;
  bs.tag       = 0;
  bs.bits_left = 16;

  // Initialize lookup
  for (unsigned long i = 0; i < LOOKUP_SIZE; ++i) {
    lookup[i] = NO_MATCH_POS;
  }

  // Main compression loop
  for (cur = 1; cur <= last_match_pos;) {
    // Update lookup up to current position
    while (hash_pos < cur) {
      lookup[blz_hash4(&in[hash_pos])] = hash_pos;
      hash_pos++;
    }

    // Look up match for current position
    const unsigned long pos = lookup[blz_hash4(&in[cur])];
    unsigned long       len = 0;

    // Check match
    if (pos != NO_MATCH_POS) {
      const unsigned long len_limit = src_size - cur;

      while (len < len_limit && in[pos + len] == in[cur + len]) {
        ++len;
      }
    }

    // Output match or literal
    //
    // When offs >= 0x1FFE00, encoding a match of length 4
    // (37 bits) is longer than encoding 4 literals (36 bits).
    //
    // The value 0x7E00 is a heuristic that sacrifices some
    // length 4 matches in the hope that there will be a better
    // match at the next position.
    if (len > 4 || (len == 4 && cur - pos - 1 < 0x7E00UL)) {
      const unsigned long offs = cur - pos - 1;

      // Output match tag
      blz_putbit(&bs, 1);

      // Output match length
      blz_putgamma(&bs, len - 2);

      // Output match offset
      blz_putgamma(&bs, (offs >> 8) + 2);
      *bs.next_out++ = offs & 0x00FF;

      cur += len;
    } else {
      // Output literal tag
      blz_putbit(&bs, 0);

      // Copy literal
      *bs.next_out++ = in[cur++];
    }
  }

  // Output any remaining literals
  while (cur < src_size) {
    // Output literal tag
    blz_putbit(&bs, 0);

    // Copy literal
    *bs.next_out++ = in[cur++];
  }

  // Trailing one bit to delimit any literal tags
  blz_putbit(&bs, 1);

  // Shift last tag into position and store
  bs.tag <<= bs.bits_left;
  bs.tag_out[0] = bs.tag & 0x00FF;
  bs.tag_out[1] = (bs.tag >> 8) & 0x00FF;

  // Return compressed size
  return (unsigned long)(bs.next_out - (unsigned char *)dst);
}

// Include compression algorithms used by blz_pack_level
#include "brieflz_btparse.h"
#include "brieflz_hashbucket.h"
#include "brieflz_lazy.h"
#include "brieflz_leparse.h"

size_t blz_workmem_size_level(size_t src_size, int level) {
  switch (level) {
  case 1:
    return blz_workmem_size(src_size);
  case 2:
    return blz_lazy_workmem_size(src_size);
  case 3:
    return blz_hashbucket_workmem_size(src_size, 2);
  case 4:
    return blz_hashbucket_workmem_size(src_size, 4);
  case 5:
  case 6:
  case 7:
    return blz_leparse_workmem_size(src_size);
  case 8:
  case 9:
  case 10:
    return blz_btparse_workmem_size(src_size);
  default:
    return (size_t)-1;
  }
}

unsigned long blz_pack_level(const void *src, void *dst, unsigned long src_size, void *workmem, int level) {
  switch (level) {
  case 1:
    return blz_pack(src, dst, src_size, workmem);
  case 2:
    return blz_pack_lazy(src, dst, src_size, workmem);
  case 3:
    return blz_pack_hashbucket(src, dst, src_size, workmem, 2, 16);
  case 4:
    return blz_pack_hashbucket(src, dst, src_size, workmem, 4, 16);
  case 5:
    return blz_pack_leparse(src, dst, src_size, workmem, 1, 16);
  case 6:
    return blz_pack_leparse(src, dst, src_size, workmem, 8, 32);
  case 7:
    return blz_pack_leparse(src, dst, src_size, workmem, 64, 64);
  case 8:
    return blz_pack_btparse(src, dst, src_size, workmem, 16, 96);
  case 9:
    return blz_pack_btparse(src, dst, src_size, workmem, 32, 224);
  case 10:
    return blz_pack_btparse(src, dst, src_size, workmem, ULONG_MAX, ULONG_MAX);
  default:
    return BLZ_ERROR;
  }
}

// clang -g -O1 -fsanitize=fuzzer,address -DBLZ_FUZZING brieflz.c depack.c
#if defined(BLZ_FUZZING)
#include 
#include 
#include 
#include 
#include 

#ifndef BLZ_FUZZ_LEVEL
#define BLZ_FUZZ_LEVEL 1
#endif

extern int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) {
  if (size > ULONG_MAX / 2) {
    return 0;
  }
  void *workmem  = malloc(blz_workmem_size_level(size, BLZ_FUZZ_LEVEL));
  void *packed   = malloc(blz_max_packed_size(size));
  void *depacked = malloc(size);
  if (!workmem || !packed || !depacked) {
    abort();
  }
  unsigned long packed_size = blz_pack_level(data, packed, size, workmem, BLZ_FUZZ_LEVEL);
  blz_depack(packed, depacked, size);
  if (memcmp(data, depacked, size)) {
    abort();
  }
  free(depacked);
  free(packed);
  free(workmem);
  return 0;
}
#endif


================================================
FILE: source/Core/brieflz/brieflz.h
================================================
/*
 * BriefLZ - small fast Lempel-Ziv
 *
 * C/C++ header file
 *
 * Copyright (c) 2002-2020 Joergen Ibsen
 *
 * This software is provided 'as-is', without any express or implied
 * warranty. In no event will the authors be held liable for any damages
 * arising from the use of this software.
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
 * freely, subject to the following restrictions:
 *
 *   1. The origin of this software must not be misrepresented; you must
 *      not claim that you wrote the original software. If you use this
 *      software in a product, an acknowledgment in the product
 *      documentation would be appreciated but is not required.
 *
 *   2. Altered source versions must be plainly marked as such, and must
 *      not be misrepresented as being the original software.
 *
 *   3. This notice may not be removed or altered from any source
 *      distribution.
 */

#ifndef BRIEFLZ_H_INCLUDED
#define BRIEFLZ_H_INCLUDED

#include 

#ifdef __cplusplus
extern "C" {
#endif

#define BLZ_VER_MAJOR 1        /**< Major version number */
#define BLZ_VER_MINOR 3        /**< Minor version number */
#define BLZ_VER_PATCH 0        /**< Patch version number */
#define BLZ_VER_STRING "1.3.0" /**< Version number as a string */

#define BLZ_NO_LUT

#ifdef BLZ_DLL
#  if defined(_WIN32) || defined(__CYGWIN__)
#    ifdef BLZ_DLL_EXPORTS
#      define BLZ_API __declspec(dllexport)
#    else
#      define BLZ_API __declspec(dllimport)
#    endif
#    define BLZ_LOCAL
#  else
#    if __GNUC__ >= 4
#      define BLZ_API __attribute__ ((visibility ("default")))
#      define BLZ_LOCAL __attribute__ ((visibility ("hidden")))
#    else
#      define BLZ_API
#      define BLZ_LOCAL
#    endif
#  endif
#else
#  define BLZ_API
#  define BLZ_LOCAL
#endif

/**
 * Return value on error.
 *
 * @see blz_depack_safe
 */
#ifndef BLZ_ERROR
#  define BLZ_ERROR ((unsigned long) (-1))
#endif

/**
 * Get bound on compressed data size.
 *
 * @see blz_pack
 *
 * @param src_size number of bytes to compress
 * @return maximum size of compressed data
 */
BLZ_API size_t
blz_max_packed_size(size_t src_size);

/**
 * Get required size of `workmem` buffer.
 *
 * @see blz_pack
 *
 * @param src_size number of bytes to compress
 * @return required size in bytes of `workmem` buffer
 */
BLZ_API size_t
blz_workmem_size(size_t src_size);

/**
 * Compress `src_size` bytes of data from `src` to `dst`.
 *
 * @param src pointer to data
 * @param dst pointer to where to place compressed data
 * @param src_size number of bytes to compress
 * @param workmem pointer to memory for temporary use
 * @return size of compressed data
 */
BLZ_API unsigned long
blz_pack(const void *src, void *dst, unsigned long src_size, void *workmem);

/**
 * Get required size of `workmem` buffer.
 *
 * @see blz_pack_level
 *
 * @param src_size number of bytes to compress
 * @param level compression level
 * @return required size in bytes of `workmem` buffer
 */
BLZ_API size_t
blz_workmem_size_level(size_t src_size, int level);

/**
 * Compress `src_size` bytes of data from `src` to `dst`.
 *
 * Compression levels between 1 and 9 offer a trade-off between
 * time/space and ratio. Level 10 is optimal but very slow.
 *
 * @param src pointer to data
 * @param dst pointer to where to place compressed data
 * @param src_size number of bytes to compress
 * @param workmem pointer to memory for temporary use
 * @param level compression level
 * @return size of compressed data
 */
BLZ_API unsigned long
blz_pack_level(const void *src, void *dst, unsigned long src_size,
               void *workmem, int level);

/**
 * Decompress `depacked_size` bytes of data from `src` to `dst`.
 *
 * @param src pointer to compressed data
 * @param dst pointer to where to place decompressed data
 * @param depacked_size size of decompressed data
 * @return size of decompressed data
 */
BLZ_API unsigned long
blz_depack(const void *src, void *dst, unsigned long depacked_size);

/**
 * Decompress `src_size` bytes of data from `src` to `dst`.
 *
 * This function is unsafe. If the provided data is malformed, it may
 * read more than `src_size` from the `src` buffer.
 *
 * @param src pointer to compressed data
 * @param dst pointer to where to place decompressed data
 * @param src_size size of the compressed data
 * @return size of decompressed data
 */
BLZ_API unsigned long
blz_depack_srcsize(const void *src, void *dst, unsigned long src_size);

/**
 * Decompress `depacked_size` bytes of data from `src` to `dst`.
 *
 * Reads at most `src_size` bytes from `src`.
 * Writes at most `depacked_size` bytes to `dst`.
 *
 * @param src pointer to compressed data
 * @param src_size size of compressed data
 * @param dst pointer to where to place decompressed data
 * @param depacked_size size of decompressed data
 * @return size of decompressed data, `BLZ_ERROR` on error
 */
BLZ_API unsigned long
blz_depack_safe(const void *src, unsigned long src_size,
                void *dst, unsigned long depacked_size);

#ifdef __cplusplus
} /* extern "C" */
#endif

#endif /* BRIEFLZ_H_INCLUDED */


================================================
FILE: source/Core/brieflz/brieflz_btparse.h
================================================
//
// BriefLZ - small fast Lempel-Ziv
//
// Forwards dynamic programming parse using binary trees
//
// Copyright (c) 2016-2020 Joergen Ibsen
//
// This software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
//   1. The origin of this software must not be misrepresented; you must
//      not claim that you wrote the original software. If you use this
//      software in a product, an acknowledgment in the product
//      documentation would be appreciated but is not required.
//
//   2. Altered source versions must be plainly marked as such, and must
//      not be misrepresented as being the original software.
//
//   3. This notice may not be removed or altered from any source
//      distribution.
//

#ifndef BRIEFLZ_BTPARSE_H_INCLUDED
#define BRIEFLZ_BTPARSE_H_INCLUDED

static size_t
blz_btparse_workmem_size(size_t src_size)
{
	return (5 * src_size + 3 + LOOKUP_SIZE) * sizeof(blz_word);
}

// Forwards dynamic programming parse using binary trees, checking all
// possible matches.
//
// The match search uses a binary tree for each hash entry, which is updated
// dynamically as it is searched by re-rooting the tree at the search string.
//
// This does not result in balanced trees on all inputs, but often works well
// in practice, and has the advantage that we get the matches in order from
// closest and back.
//
// A drawback is the memory requirement of 5 * src_size words, since we cannot
// overlap the arrays in a forwards parse.
//
// This match search method is found in LZMA by Igor Pavlov, libdeflate
// by Eric Biggers, and other libraries.
//
static unsigned long
blz_pack_btparse(const void *src, void *dst, unsigned long src_size, void *workmem,
                 const unsigned long max_depth, const unsigned long accept_len)
{
	struct blz_state bs;
	const unsigned char *const in = (const unsigned char *) src;
	const unsigned long last_match_pos = src_size > 4 ? src_size - 4 : 0;

	assert(src_size < BLZ_WORD_MAX);

	// Check for empty input
	if (src_size == 0) {
		return 0;
	}

	bs.next_out = (unsigned char *) dst;

	// First byte verbatim
	*bs.next_out++ = in[0];

	// Check for 1 byte input
	if (src_size == 1) {
		return 1;
	}

	// Initialize first tag
	bs.tag_out = bs.next_out;
	bs.next_out += 2;
	bs.tag = 0;
	bs.bits_left = 16;

	if (src_size < 4) {
		for (unsigned long i = 1; i < src_size; ++i) {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[i];
		}

		// Return compressed size
		return (unsigned long) (blz_finalize(&bs) - (unsigned char *) dst);
	}

	blz_word *const cost = (blz_word *) workmem;
	blz_word *const mpos = cost + src_size + 1;
	blz_word *const mlen = mpos + src_size + 1;
	blz_word *const nodes = mlen + src_size + 1;
	blz_word *const lookup = nodes + 2 * src_size;

	// Initialize lookup
	for (unsigned long i = 0; i < LOOKUP_SIZE; ++i) {
		lookup[i] = NO_MATCH_POS;
	}

	// Since we are not processing the first literal, update tree for
	// position 0
	lookup[blz_hash4(&in[0])] = 0;
	nodes[0] = NO_MATCH_POS;
	nodes[1] = NO_MATCH_POS;

	// Initialize to all literals with infinite cost
	for (unsigned long i = 0; i <= src_size; ++i) {
		cost[i] = BLZ_WORD_MAX;
		mlen[i] = 1;
	}

	cost[0] = 0;
	cost[1] = 8;

	// Next position where we are going to check matches
	//
	// This is used to skip matching while still updating the trees when
	// we find a match that is accept_len or longer.
	//
	unsigned long next_match_cur = 1;

	// Phase 1: Find lowest cost path arriving at each position
	for (unsigned long cur = 1; cur <= last_match_pos; ++cur) {
		// Adjust remaining costs to avoid overflow
		if (cost[cur] > BLZ_WORD_MAX - 128) {
			blz_word min_cost = BLZ_WORD_MAX;

			for (unsigned long i = cur; i <= src_size; ++i) {
				min_cost = cost[i] < min_cost ? cost[i] : min_cost;
			}

			for (unsigned long i = cur; i <= src_size; ++i) {
				if (cost[i] != BLZ_WORD_MAX) {
					cost[i] -= min_cost;
				}
			}
		}

		// Check literal
		if (cost[cur + 1] > cost[cur] + 9) {
			cost[cur + 1] = cost[cur] + 9;
			mlen[cur + 1] = 1;
		}

		if (cur > next_match_cur) {
			next_match_cur = cur;
		}

		unsigned long max_len = 3;

		// Look up first match for current position
		//
		// pos is the current root of the tree of strings with this
		// hash. We are going to re-root the tree so cur becomes the
		// new root.
		//
		const unsigned long hash = blz_hash4(&in[cur]);
		unsigned long pos = lookup[hash];
		lookup[hash] = cur;

		blz_word *lt_node = &nodes[2 * cur];
		blz_word *gt_node = &nodes[2 * cur + 1];
		unsigned long lt_len = 0;
		unsigned long gt_len = 0;

		assert(pos == NO_MATCH_POS || pos < cur);

		// If we are checking matches, allow lengths up to end of
		// input, otherwise compare only up to accept_len
		const unsigned long len_limit = cur == next_match_cur ? src_size - cur
		                              : accept_len < src_size - cur ? accept_len
		                              : src_size - cur;
		unsigned long num_chain = max_depth;

		// Check matches
		for (;;) {
			// If at bottom of tree, mark leaf nodes
			//
			// In case we reached max_depth, this also prunes the
			// subtree we have not searched yet and do not know
			// where belongs.
			//
			if (pos == NO_MATCH_POS || num_chain-- == 0) {
				*lt_node = NO_MATCH_POS;
				*gt_node = NO_MATCH_POS;

				break;
			}

			// The string at pos is lexicographically greater than
			// a string that matched in the first lt_len positions,
			// and less than a string that matched in the first
			// gt_len positions, so it must match up to at least
			// the minimum of these.
			unsigned long len = lt_len < gt_len ? lt_len : gt_len;

			// Find match len
			while (len < len_limit && in[pos + len] == in[cur + len]) {
				++len;
			}

			// Extend current match if possible
			//
			// Note that we are checking matches in order from the
			// closest and back. This means for a match further
			// away, the encoding of all lengths up to the current
			// max length will always be longer or equal, so we need
			// only consider the extension.
			//
			if (cur == next_match_cur && len > max_len) {
				for (unsigned long i = max_len + 1; i <= len; ++i) {
					unsigned long match_cost = blz_match_cost(cur - pos - 1, i);

					assert(match_cost < BLZ_WORD_MAX - cost[cur]);

					unsigned long cost_there = cost[cur] + match_cost;

					if (cost_there < cost[cur + i]) {
						cost[cur + i] = cost_there;
						mpos[cur + i] = cur - pos - 1;
						mlen[cur + i] = i;
					}
				}

				max_len = len;

				if (len >= accept_len) {
					next_match_cur = cur + len;
				}
			}

			// If we reach maximum match length, the string at pos
			// is equal to cur, so we can assign the left and right
			// subtrees.
			//
			// This removes pos from the tree, but we added cur
			// which is equal and closer for future matches.
			//
			if (len >= accept_len || len == len_limit) {
				*lt_node = nodes[2 * pos];
				*gt_node = nodes[2 * pos + 1];

				break;
			}

			// Go to previous match and restructure tree
			//
			// lt_node points to a node that is going to contain
			// elements lexicographically less than cur (the search
			// string).
			//
			// If the string at pos is less than cur, we set that
			// lt_node to pos. We know that all elements in the
			// left subtree are less than pos, and thus less than
			// cur, so we point lt_node at the right subtree of
			// pos and continue our search there.
			//
			// The equivalent applies to gt_node when the string at
			// pos is greater than cur.
			//
			if (in[pos + len] < in[cur + len]) {
				*lt_node = pos;
				lt_node = &nodes[2 * pos + 1];
				assert(*lt_node == NO_MATCH_POS || *lt_node < pos);
				pos = *lt_node;
				lt_len = len;
			}
			else {
				*gt_node = pos;
				gt_node = &nodes[2 * pos];
				assert(*gt_node == NO_MATCH_POS || *gt_node < pos);
				pos = *gt_node;
				gt_len = len;
			}
		}
	}

	for (unsigned long cur = last_match_pos + 1; cur < src_size; ++cur) {
		// Check literal
		if (cost[cur + 1] > cost[cur] + 9) {
			cost[cur + 1] = cost[cur] + 9;
			mlen[cur + 1] = 1;
		}
	}

	// Phase 2: Follow lowest cost path backwards gathering tokens
	unsigned long next_token = src_size;

	for (unsigned long cur = src_size; cur > 1; cur -= mlen[cur], --next_token) {
		mlen[next_token] = mlen[cur];
		mpos[next_token] = mpos[cur];
	}

	// Phase 3: Output tokens
	unsigned long cur = 1;

	for (unsigned long i = next_token + 1; i <= src_size; cur += mlen[i++]) {
		if (mlen[i] == 1) {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[cur];
		}
		else {
			const unsigned long offs = mpos[i];

			// Output match tag
			blz_putbit(&bs, 1);

			// Output match length
			blz_putgamma(&bs, mlen[i] - 2);

			// Output match offset
			blz_putgamma(&bs, (offs >> 8) + 2);
			*bs.next_out++ = offs & 0x00FF;
		}
	}

	// Return compressed size
	return (unsigned long) (blz_finalize(&bs) - (unsigned char *) dst);
}

#endif /* BRIEFLZ_BTPARSE_H_INCLUDED */


================================================
FILE: source/Core/brieflz/brieflz_hashbucket.h
================================================
//
// BriefLZ - small fast Lempel-Ziv
//
// Lazy parsing with multiple previous positions per hash
//
// Copyright (c) 2016-2020 Joergen Ibsen
//
// This software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
//   1. The origin of this software must not be misrepresented; you must
//      not claim that you wrote the original software. If you use this
//      software in a product, an acknowledgment in the product
//      documentation would be appreciated but is not required.
//
//   2. Altered source versions must be plainly marked as such, and must
//      not be misrepresented as being the original software.
//
//   3. This notice may not be removed or altered from any source
//      distribution.
//

#ifndef BRIEFLZ_HASHBUCKET_H_INCLUDED
#define BRIEFLZ_HASHBUCKET_H_INCLUDED

static size_t
blz_hashbucket_workmem_size(size_t src_size, unsigned int bucket_size)
{
	(void) src_size;

	assert(bucket_size > 0);
	assert(sizeof(bucket_size) < sizeof(size_t)
	    || bucket_size < SIZE_MAX / (LOOKUP_SIZE * sizeof(blz_word)));

	return (LOOKUP_SIZE * bucket_size) * sizeof(blz_word);
}

// Lazy parsing with multiple previous positions per hash.
//
// Instead of storing only the previous position a given hash occured at,
// this stores the last bucket_size such positions in lookup. This means we
// can check each of these and choose the "best".
//
// There are multiple options for maintaining the entries of the buckets, we
// simply insert at the front to maintain the order of matches and avoid extra
// variables. This gives some overhead for moving elements, but as long as
// bucket_size is small and everything fits in a cache line it is pretty fast.
//
// If we find a match that is accept_len or longer, we stop searching.
//
static unsigned long
blz_pack_hashbucket(const void *src, void *dst, unsigned long src_size, void *workmem,
                    const unsigned int bucket_size, const unsigned long accept_len)
{
	struct blz_state bs;
	blz_word *const lookup = (blz_word *) workmem;
	const unsigned char *const in = (const unsigned char *) src;
	const unsigned long last_match_pos = src_size > 4 ? src_size - 4 : 0;
	unsigned long hash_pos = 0;
	unsigned long cur = 0;

	assert(src_size < BLZ_WORD_MAX);

	// Check for empty input
	if (src_size == 0) {
		return 0;
	}

	bs.next_out = (unsigned char *) dst;

	// First byte verbatim
	*bs.next_out++ = in[0];

	// Check for 1 byte input
	if (src_size == 1) {
		return 1;
	}

	// Initialize first tag
	bs.tag_out = bs.next_out;
	bs.next_out += 2;
	bs.tag = 0;
	bs.bits_left = 16;

	assert(bucket_size > 0);
	assert(sizeof(bucket_size) < sizeof(unsigned long)
	    || bucket_size < ULONG_MAX / LOOKUP_SIZE);

	// Initialize lookup
	for (unsigned long i = 0; i < LOOKUP_SIZE * bucket_size; ++i) {
		lookup[i] = NO_MATCH_POS;
	}

	// Main compression loop
	for (cur = 1; cur <= last_match_pos; ) {
		// Update lookup up to current position
		while (hash_pos < cur) {
			blz_word *const bucket = &lookup[blz_hash4(&in[hash_pos]) * bucket_size];
			unsigned long next = hash_pos;

			// Insert hash_pos at start of bucket
			for (unsigned int i = 0; i < bucket_size; ++i) {
				unsigned long tmp = bucket[i];
				bucket[i] = next;
				next = tmp;
			}

			hash_pos++;
		}

		unsigned long best_pos = NO_MATCH_POS;
		unsigned long best_len = 0;

		// Look up first match for current position
		const blz_word *const bucket = &lookup[blz_hash4(&in[cur]) * bucket_size];
		unsigned long pos = bucket[0];
		unsigned int bucket_idx = 0;

		const unsigned long len_limit = src_size - cur;

		// Check matches
		while (pos != NO_MATCH_POS) {
			unsigned long len = 0;

			// Check match
			if (best_len < len_limit
			 && in[pos + best_len] == in[cur + best_len]) {
				while (len < len_limit && in[pos + len] == in[cur + len]) {
					++len;
				}
			}

			// Update best match
			if (blz_match_better(cur, pos, len, best_pos, best_len)) {
				best_pos = pos;
				best_len = len;
				if (best_len >= accept_len) {
					break;
				}
			}

			// Go to previous match
			if (++bucket_idx == bucket_size) {
				break;
			}
			pos = bucket[bucket_idx];
		}

		// Check if match at next position is better
		if (best_len > 3 && best_len < accept_len && cur < last_match_pos) {
			// Update lookup up to next position
			{
				blz_word *const next_bucket = &lookup[blz_hash4(&in[hash_pos]) * bucket_size];
				unsigned long next = hash_pos;

				// Insert hash_pos at start of bucket
				for (unsigned int i = 0; i < bucket_size; ++i) {
					unsigned long tmp = next_bucket[i];
					next_bucket[i] = next;
					next = tmp;
				}

				hash_pos++;
			}

			// Look up first match for next position
			const blz_word *const next_bucket = &lookup[blz_hash4(&in[cur + 1]) * bucket_size];
			unsigned long next_pos = next_bucket[0];
			unsigned int next_bucket_idx = 0;

			const unsigned long next_len_limit = src_size - (cur + 1);

			// Check matches
			while (next_pos != NO_MATCH_POS) {
				unsigned long next_len = 0;

				// Check match
				if (best_len - 1 < next_len_limit
				 && in[next_pos + best_len - 1] == in[cur + 1 + best_len - 1]) {
					while (next_len < next_len_limit
					    && in[next_pos + next_len] == in[cur + 1 + next_len]) {
						++next_len;
					}
				}

				if (next_len >= best_len) {
					// Replace with next match if it extends backwards
					if (next_pos > 0 && in[next_pos - 1] == in[cur]) {
						if (blz_match_better(cur, next_pos - 1, next_len + 1, best_pos, best_len)) {
							best_pos = next_pos - 1;
							best_len = next_len + 1;
						}
					}
					else {
						// Drop current match if next match is better
						if (blz_next_match_better(cur, next_pos, next_len, best_pos, best_len)) {
							best_len = 0;
							break;
						}
					}
				}

				// Go to previous match
				if (++next_bucket_idx == bucket_size) {
					break;
				}
				next_pos = next_bucket[next_bucket_idx];
			}
		}

		// Output match or literal
		if (best_len > 4 || (best_len == 4 && cur - best_pos - 1 < 0x3FE00UL)) {
			const unsigned long offs = cur - best_pos - 1;

			// Output match tag
			blz_putbit(&bs, 1);

			// Output match length
			blz_putgamma(&bs, best_len - 2);

			// Output match offset
			blz_putgamma(&bs, (offs >> 8) + 2);
			*bs.next_out++ = offs & 0x00FF;

			cur += best_len;
		}
		else {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[cur++];
		}
	}

	// Output any remaining literals
	while (cur < src_size) {
		// Output literal tag
		blz_putbit(&bs, 0);

		// Copy literal
		*bs.next_out++ = in[cur++];
	}

	// Trailing one bit to delimit any literal tags
	blz_putbit(&bs, 1);

	// Shift last tag into position and store
	bs.tag <<= bs.bits_left;
	bs.tag_out[0] = bs.tag & 0x00FF;
	bs.tag_out[1] = (bs.tag >> 8) & 0x00FF;

	// Return compressed size
	return (unsigned long) (bs.next_out - (unsigned char *) dst);
}

#endif /* BRIEFLZ_HASHBUCKET_H_INCLUDED */


================================================
FILE: source/Core/brieflz/brieflz_lazy.h
================================================
//
// BriefLZ - small fast Lempel-Ziv
//
// Lazy (non-greedy) parsing with one-byte-lookahead
//
// Copyright (c) 2016-2020 Joergen Ibsen
//
// This software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
//   1. The origin of this software must not be misrepresented; you must
//      not claim that you wrote the original software. If you use this
//      software in a product, an acknowledgment in the product
//      documentation would be appreciated but is not required.
//
//   2. Altered source versions must be plainly marked as such, and must
//      not be misrepresented as being the original software.
//
//   3. This notice may not be removed or altered from any source
//      distribution.
//

#ifndef BRIEFLZ_LAZY_H_INCLUDED
#define BRIEFLZ_LAZY_H_INCLUDED

static size_t
blz_lazy_workmem_size(size_t src_size)
{
	(void) src_size;

	return LOOKUP_SIZE * sizeof(blz_word);
}

// Lazy (non-greedy) parsing with one-byte-lookahead.
//
// Each time we find a match, we check if there is a better match at the next
// position, and if so encode a literal instead.
//
static unsigned long
blz_pack_lazy(const void *src, void *dst, unsigned long src_size, void *workmem)
{
	struct blz_state bs;
	blz_word *const lookup = (blz_word *) workmem;
	const unsigned char *const in = (const unsigned char *) src;
	const unsigned long last_match_pos = src_size > 4 ? src_size - 4 : 0;
	unsigned long hash_pos = 0;
	unsigned long cur = 0;

	assert(src_size < BLZ_WORD_MAX);

	// Check for empty input
	if (src_size == 0) {
		return 0;
	}

	bs.next_out = (unsigned char *) dst;

	// First byte verbatim
	*bs.next_out++ = in[0];

	// Check for 1 byte input
	if (src_size == 1) {
		return 1;
	}

	// Initialize first tag
	bs.tag_out = bs.next_out;
	bs.next_out += 2;
	bs.tag = 0;
	bs.bits_left = 16;

	// Initialize lookup
	for (unsigned long i = 0; i < LOOKUP_SIZE; ++i) {
		lookup[i] = NO_MATCH_POS;
	}

	// Main compression loop
	for (cur = 1; cur <= last_match_pos; ) {
		// Update lookup up to current position
		while (hash_pos < cur) {
			lookup[blz_hash4(&in[hash_pos])] = hash_pos;
			hash_pos++;
		}

		// Look up match for current position
		unsigned long pos = lookup[blz_hash4(&in[cur])];
		unsigned long len = 0;

		// Check match
		if (pos != NO_MATCH_POS) {
			const unsigned long len_limit = src_size - cur;

			while (len < len_limit
			    && in[pos + len] == in[cur + len]) {
				++len;
			}
		}

		// Check if match at next position is better
		if (len > 3 && cur < last_match_pos) {
			// Update lookup up to next position
			lookup[blz_hash4(&in[hash_pos])] = hash_pos;
			hash_pos++;

			// Look up match for next position
			const unsigned long next_pos = lookup[blz_hash4(&in[cur + 1])];
			unsigned long next_len = 0;

			// Check match
			if (next_pos != NO_MATCH_POS && next_pos != pos + 1) {
				const unsigned long next_len_limit = src_size - (cur + 1);

				// If last byte matches, so this has a chance to be a better match
				if (len - 1 < next_len_limit
				 && in[next_pos + len - 1] == in[cur + 1 + len - 1]) {
					while (next_len < next_len_limit
					    && in[next_pos + next_len] == in[cur + 1 + next_len]) {
						++next_len;
					}
				}
			}

			if (next_len >= len) {
				// Replace with next match if it extends backwards
				if (next_pos > 0 && in[next_pos - 1] == in[cur]) {
					if (blz_match_better(cur, next_pos - 1, next_len + 1, pos, len)) {
						pos = next_pos - 1;
						len = next_len + 1;
					}
				}
				else {
					// Drop current match if next match is better
					if (blz_next_match_better(cur, next_pos, next_len, pos, len)) {
						len = 0;
					}
				}

			}
		}

		// Output match or literal
		if (len > 4 || (len == 4 && cur - pos - 1 < 0x3FE00UL)) {
			const unsigned long offs = cur - pos - 1;

			// Output match tag
			blz_putbit(&bs, 1);

			// Output match length
			blz_putgamma(&bs, len - 2);

			// Output match offset
			blz_putgamma(&bs, (offs >> 8) + 2);
			*bs.next_out++ = offs & 0x00FF;

			cur += len;
		}
		else {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[cur++];
		}
	}

	// Output any remaining literals
	while (cur < src_size) {
		// Output literal tag
		blz_putbit(&bs, 0);

		// Copy literal
		*bs.next_out++ = in[cur++];
	}

	// Trailing one bit to delimit any literal tags
	blz_putbit(&bs, 1);

	// Shift last tag into position and store
	bs.tag <<= bs.bits_left;
	bs.tag_out[0] = bs.tag & 0x00FF;
	bs.tag_out[1] = (bs.tag >> 8) & 0x00FF;

	// Return compressed size
	return (unsigned long) (bs.next_out - (unsigned char *) dst);
}

#endif /* BRIEFLZ_LAZY_H_INCLUDED */


================================================
FILE: source/Core/brieflz/brieflz_leparse.h
================================================
//
// BriefLZ - small fast Lempel-Ziv
//
// Backwards dynamic programming parse with left-extension of matches
//
// Copyright (c) 2016-2020 Joergen Ibsen
//
// This software is provided 'as-is', without any express or implied
// warranty. In no event will the authors be held liable for any damages
// arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it
// freely, subject to the following restrictions:
//
//   1. The origin of this software must not be misrepresented; you must
//      not claim that you wrote the original software. If you use this
//      software in a product, an acknowledgment in the product
//      documentation would be appreciated but is not required.
//
//   2. Altered source versions must be plainly marked as such, and must
//      not be misrepresented as being the original software.
//
//   3. This notice may not be removed or altered from any source
//      distribution.
//

#ifndef BRIEFLZ_LEPARSE_H_INCLUDED
#define BRIEFLZ_LEPARSE_H_INCLUDED

static size_t
blz_leparse_workmem_size(size_t src_size)
{
	return (LOOKUP_SIZE < 2 * src_size ? 3 * src_size : src_size + LOOKUP_SIZE)
	     * sizeof(blz_word);
}

// Backwards dynamic programming parse with left-extension of matches.
//
// Whenever we find a match that improves the cost at the current position,
// we try to extend this match to the left, and if possible we use that
// left-extension for each position to the left. Since we are processing
// the input from right to left, this matches repeated patterns without
// searching at each position.
//
// Essentially, this improves the worst case for the parsing at a small cost
// in ratio. The match finding is still O(n^2) in number of matches though,
// so may have to limit max_depth on larger block sizes.
//
// This is usually within a few percent of the "optimal" parse with the same
// parameters.
//
static unsigned long
blz_pack_leparse(const void *src, void *dst, unsigned long src_size, void *workmem,
                 const unsigned long max_depth, const unsigned long accept_len)
{
	struct blz_state bs;
	const unsigned char *const in = (const unsigned char *) src;
	const unsigned long last_match_pos = src_size > 4 ? src_size - 4 : 0;

	assert(src_size < BLZ_WORD_MAX);

	// Check for empty input
	if (src_size == 0) {
		return 0;
	}

	bs.next_out = (unsigned char *) dst;

	// First byte verbatim
	*bs.next_out++ = in[0];

	// Check for 1 byte input
	if (src_size == 1) {
		return 1;
	}

	// Initialize first tag
	bs.tag_out = bs.next_out;
	bs.next_out += 2;
	bs.tag = 0;
	bs.bits_left = 16;

	if (src_size < 4) {
		for (unsigned long i = 1; i < src_size; ++i) {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[i];
		}

		// Return compressed size
		return (unsigned long) (blz_finalize(&bs) - (unsigned char *) dst);
	}

	// With a bit of careful ordering we can fit in 3 * src_size words.
	//
	// The idea is that the lookup is only used in the first phase to
	// build the hash chains, so we overlap it with mpos and mlen.
	// Also, since we are using prev from right to left in phase two,
	// and that is the order we fill in cost, we can overlap these.
	//
	// One detail is that we actually use src_size + 1 elements of cost,
	// but we put mpos after it, where we do not need the first element.
	//
	blz_word *const prev = (blz_word *) workmem;
	blz_word *const mpos = prev + src_size;
	blz_word *const mlen = mpos + src_size;
	blz_word *const cost = prev;
	blz_word *const lookup = mpos;

	// Phase 1: Build hash chains
	const int bits = 2 * src_size < LOOKUP_SIZE ? BLZ_HASH_BITS : blz_log2(src_size);

	// Initialize lookup
	for (unsigned long i = 0; i < (1UL << bits); ++i) {
		lookup[i] = NO_MATCH_POS;
	}

	// Build hash chains in prev
	if (last_match_pos > 0) {
		for (unsigned long i = 0; i <= last_match_pos; ++i) {
			const unsigned long hash = blz_hash4_bits(&in[i], bits);
			prev[i] = lookup[hash];
			lookup[hash] = i;
		}
	}

	// Initialize last three positions as literals
	mlen[src_size - 3] = 1;
	mlen[src_size - 2] = 1;
	mlen[src_size - 1] = 1;

	cost[src_size - 3] = 27;
	cost[src_size - 2] = 18;
	cost[src_size - 1] = 9;
	cost[src_size] = 0;

	// Phase 2: Find lowest cost path from each position to end
	for (unsigned long cur = last_match_pos; cur > 0; --cur) {
		// Since we updated prev to the end in the first phase, we
		// do not need to hash, but can simply look up the previous
		// position directly.
		unsigned long pos = prev[cur];

		assert(pos == NO_MATCH_POS || pos < cur);

		// Start with a literal
		cost[cur] = cost[cur + 1] + 9;
		mlen[cur] = 1;

		unsigned long max_len = 3;

		const unsigned long len_limit = src_size - cur;
		unsigned long num_chain = max_depth;

		// Go through the chain of prev matches
		for (; pos != NO_MATCH_POS && num_chain--; pos = prev[pos]) {
			unsigned long len = 0;

			// If next byte matches, so this has a chance to be a longer match
			if (max_len < len_limit && in[pos + max_len] == in[cur + max_len]) {
				// Find match len
				while (len < len_limit && in[pos + len] == in[cur + len]) {
					++len;
				}
			}

			// Extend current match if possible
			//
			// Note that we are checking matches in order from the
			// closest and back. This means for a match further
			// away, the encoding of all lengths up to the current
			// max length will always be longer or equal, so we need
			// only consider the extension.
			if (len > max_len) {
				unsigned long min_cost = ULONG_MAX;
				unsigned long min_cost_len = 3;

				// Find lowest cost match length
				for (unsigned long i = max_len + 1; i <= len; ++i) {
					unsigned long match_cost = blz_match_cost(cur - pos - 1, i);
					assert(match_cost < BLZ_WORD_MAX - cost[cur + i]);
					unsigned long cost_here = match_cost + cost[cur + i];

					if (cost_here < min_cost) {
						min_cost = cost_here;
						min_cost_len = i;
					}
				}

				max_len = len;

				// Update cost if cheaper
				if (min_cost < cost[cur]) {
					cost[cur] = min_cost;
					mpos[cur] = pos;
					mlen[cur] = min_cost_len;

					// Left-extend current match if possible
					if (pos > 0 && in[pos - 1] == in[cur - 1]) {
						do {
							--cur;
							--pos;
							++min_cost_len;
							unsigned long match_cost = blz_match_cost(cur - pos - 1, min_cost_len);
							assert(match_cost < BLZ_WORD_MAX - cost[cur + min_cost_len]);
							unsigned long cost_here = match_cost + cost[cur + min_cost_len];
							cost[cur] = cost_here;
							mpos[cur] = pos;
							mlen[cur] = min_cost_len;
						} while (pos > 0 && in[pos - 1] == in[cur - 1]);
						break;
					}
				}
			}

			if (len >= accept_len || len == len_limit) {
				break;
			}
		}
	}

	mpos[0] = 0;
	mlen[0] = 1;

	// Phase 3: Output compressed data, following lowest cost path
	for (unsigned long i = 1; i < src_size; i += mlen[i]) {
		if (mlen[i] == 1) {
			// Output literal tag
			blz_putbit(&bs, 0);

			// Copy literal
			*bs.next_out++ = in[i];
		}
		else {
			const unsigned long offs = i - mpos[i] - 1;

			// Output match tag
			blz_putbit(&bs, 1);

			// Output match length
			blz_putgamma(&bs, mlen[i] - 2);

			// Output match offset
			blz_putgamma(&bs, (offs >> 8) + 2);
			*bs.next_out++ = offs & 0x00FF;
		}
	}

	// Return compressed size
	return (unsigned long) (blz_finalize(&bs) - (unsigned char *) dst);
}

#endif /* BRIEFLZ_LEPARSE_H_INCLUDED */


================================================
FILE: source/Core/brieflz/depack.c
================================================
/*
 * BriefLZ - small fast Lempel-Ziv
 *
 * C depacker
 *
 * Copyright (c) 2002-2018 Joergen Ibsen
 *
 * This software is provided 'as-is', without any express or implied
 * warranty. In no event will the authors be held liable for any damages
 * arising from the use of this software.
 *
 * Permission is granted to anyone to use this software for any purpose,
 * including commercial applications, and to alter it and redistribute it
 * freely, subject to the following restrictions:
 *
 *   1. The origin of this software must not be misrepresented; you must
 *      not claim that you wrote the original software. If you use this
 *      software in a product, an acknowledgment in the product
 *      documentation would be appreciated but is not required.
 *
 *   2. Altered source versions must be plainly marked as such, and must
 *      not be misrepresented as being the original software.
 *
 *   3. This notice may not be removed or altered from any source
 *      distribution.
 */

#include "brieflz.h"

/* Internal data structure */
struct blz_state {
  const unsigned char *src;
  unsigned char       *dst;
  unsigned int         tag;
  int                  bits_left;
};

#if !defined(BLZ_NO_LUT)
static const unsigned char blz_gamma_lookup[256][2] = {
    /* 00xxxxxx = 2 */
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},
    { 2, 2},

    /* 0100xxxx = 4 */
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},
    { 4, 4},

    /* 010100xx = 8 */
    { 8, 6},
    { 8, 6},
    { 8, 6},
    { 8, 6},

    /* 01010100 = 16  01010101 = 16+ 01010110 = 17  01010111 = 17+ */
    {16, 8},
    {16, 0},
    {17, 8},
    {17, 0},

    /* 010110xx = 9 */
    { 9, 6},
    { 9, 6},
    { 9, 6},
    { 9, 6},

    /* 01011100 = 18  01011101 = 18+ 01011110 = 19  01011111 = 19+ */
    {18, 8},
    {18, 0},
    {19, 8},
    {19, 0},

    /* 0110xxxx = 5 */
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},
    { 5, 4},

    /* 011100xx = 10 */
    {10, 6},
    {10, 6},
    {10, 6},
    {10, 6},

    /* 01110100 = 20  01110101 = 20+ 01110110 = 21  01110111 = 21+ */
    {20, 8},
    {20, 0},
    {21, 8},
    {21, 0},

    /* 011110xx = 11 */
    {11, 6},
    {11, 6},
    {11, 6},
    {11, 6},

    /* 01111100 = 22  01111101 = 22+ 01111110 = 23  01111111 = 23+ */
    {22, 8},
    {22, 0},
    {23, 8},
    {23, 0},

    /* 10xxxxxx = 3 */
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},
    { 3, 2},

    /* 1100xxxx = 6 */
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},
    { 6, 4},

    /* 110100xx = 12 */
    {12, 6},
    {12, 6},
    {12, 6},
    {12, 6},

    /* 11010100 = 24  11010101 = 24+ 11010110 = 25  11010111 = 25+ */
    {24, 8},
    {24, 0},
    {25, 8},
    {25, 0},

    /* 110110xx = 13 */
    {13, 6},
    {13, 6},
    {13, 6},
    {13, 6},

    /* 11011100 = 26  11011101 = 26+ 11011110 = 27  11011111 = 27+ */
    {26, 8},
    {26, 0},
    {27, 8},
    {27, 0},

    /* 1110xxxx = 7 */
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},
    { 7, 4},

    /* 111100xx = 14 */
    {14, 6},
    {14, 6},
    {14, 6},
    {14, 6},

    /* 11110100 = 28  11110101 = 28+ 11110110 = 29  11110111 = 29+ */
    {28, 8},
    {28, 0},
    {29, 8},
    {29, 0},

    /* 111110xx = 15 */
    {15, 6},
    {15, 6},
    {15, 6},
    {15, 6},

    /* 11111100 = 30  11111101 = 30+ 11111110 = 31  11111111 = 31+ */
    {30, 8},
    {30, 0},
    {31, 8},
    {31, 0}
};
#endif

static unsigned int blz_getbit(struct blz_state *bs) {
  unsigned int bit;

  /* Check if tag is empty */
  if (!bs->bits_left--) {
    /* Load next tag */
    bs->tag = (unsigned int)bs->src[0] | ((unsigned int)bs->src[1] << 8);
    bs->src += 2;
    bs->bits_left = 15;
  }

  /* Shift bit out of tag */
  bit = (bs->tag & 0x8000) ? 1 : 0;
  bs->tag <<= 1;

  return bit;
}

static unsigned long blz_getgamma(struct blz_state *bs) {
  unsigned long result = 1;

#if !defined(BLZ_NO_LUT)
  /* Decode up to 8 bits of gamma2 code using lookup if possible */
  if (bs->bits_left >= 8) {
    unsigned int top8 = (bs->tag >> 8) & 0x00FF;
    int          shift;

    result = blz_gamma_lookup[top8][0];
    shift  = (int)blz_gamma_lookup[top8][1];

    if (shift) {
      bs->tag <<= shift;
      bs->bits_left -= shift;
      return result;
    }

    bs->tag <<= 8;
    bs->bits_left -= 8;
  }
#endif

  /* Input gamma2-encoded bits */
  do {
    result = (result << 1) + blz_getbit(bs);
  } while (blz_getbit(bs));

  return result;
}

unsigned long blz_depack(const void *src, void *dst, unsigned long depacked_size) {
  struct blz_state bs;
  unsigned long    dst_size = 0;

  bs.src = (const unsigned char *)src;
  bs.dst = (unsigned char *)dst;

  /* Initialise to one bit left in tag; that bit is zero (a literal) */
  bs.bits_left = 1;
  bs.tag       = 0x4000;

  /* Main decompression loop */
  while (dst_size < depacked_size) {
    if (blz_getbit(&bs)) {
      /* Input match length and offset */
      unsigned long len = blz_getgamma(&bs) + 2;
      unsigned long off = blz_getgamma(&bs) - 2;

      off = (off << 8) + (unsigned long)*bs.src++ + 1;

      /* Copy match */
      {
        const unsigned char *p = bs.dst - off;
        unsigned long        i;

        for (i = len; i > 0; --i) {
          *bs.dst++ = *p++;
        }
      }

      dst_size += len;
    } else {
      /* Copy literal */
      *bs.dst++ = *bs.src++;

      dst_size++;
    }
  }

  /* Return decompressed size */
  return dst_size;
}

unsigned long blz_depack_srcsize(const void *src, void *dst, unsigned long src_size) {
  struct blz_state     bs;
  unsigned long        dst_size = 0;
  const unsigned char *src_end  = src + src_size;

  bs.src = (const unsigned char *)src;
  bs.dst = (unsigned char *)dst;

  /* Initialise to one bit left in tag; that bit is zero (a literal) */
  bs.bits_left = 1;
  bs.tag       = 0x4000;

  /* Main decompression loop */
  while (bs.src < src_end) {
    if (blz_getbit(&bs)) {
      /* Input match length and offset */
      unsigned long len = blz_getgamma(&bs) + 2;
      unsigned long off = blz_getgamma(&bs) - 2;

      off = (off << 8) + (unsigned long)*bs.src++ + 1;

      /* Copy match */
      {
        const unsigned char *p = bs.dst - off;
        unsigned long        i;

        for (i = len; i > 0; --i) {
          *bs.dst++ = *p++;
        }
      }

      dst_size += len;
    } else {
      /* Copy literal */
      *bs.dst++ = *bs.src++;

      dst_size++;
    }
  }

  /* Return decompressed size */
  return dst_size;
}


================================================
FILE: source/Makefile
================================================
ifndef model
model:=Pinecilv2
endif

ALL_MINIWARE_MODELS=TS100 TS80 TS80P TS101
ALL_PINECIL_MODELS=Pinecil
ALL_PINECIL_V2_MODELS=Pinecilv2
ALL_MHP30_MODELS=MHP30
ALL_SEQURE_MODELS=S60 S60P T55
ALL_MODELS=$(ALL_MINIWARE_MODELS) $(ALL_PINECIL_MODELS) $(ALL_MHP30_MODELS) $(ALL_PINECIL_V2_MODELS) $(ALL_SEQURE_MODELS)

ifneq ($(model),$(filter $(model),$(ALL_MODELS)))
$(error Invalid model '$(model)', valid options are: $(ALL_MODELS))
endif

# Output folder
HEXFILE_DIR=Hexfile

# Temporary objects folder
OUTPUT_DIR_BASE=Objects
OUTPUT_DIR=Objects/$(model)

ALL_LANGUAGES=BE BG CS DA DE EL EN ES ET FI FR HR HU IT JA_JP LT NB NL_BE NL PL PT RO RU SK SL SR_CYRL SR_LATN SV TR UK UZ VI YUE_HK ZH_CN ZH_TW

LANGUAGE_GROUP_CJK_LANGS=EN JA_JP YUE_HK ZH_TW ZH_CN
LANGUAGE_GROUP_CJK_NAME=Chinese+Japanese

ifdef custom_multi_langs
RUN_SHELL_CMD:=$(shell rm -Rf {Core/Gen,$(OUTPUT_DIR)/Core/Gen,$(HEXFILE_DIR)/*_Custom.*})
LANGUAGE_GROUP_CUSTOM_LANGS=$(custom_multi_langs)
LANGUAGE_GROUP_CUSTOM_NAME=Custom
endif

LANGUAGE_GROUP_CYRILLIC_LANGS=EN BE BG RU SR_CYRL SR_LATN UK
LANGUAGE_GROUP_CYRILLIC_NAME=Belarusian+Bulgarian+Russian+Serbian+Ukrainian

LANGUAGE_GROUP_EUR_LANGS=EN $(filter-out $(LANGUAGE_GROUP_CJK_LANGS) $(LANGUAGE_GROUP_CYRILLIC_LANGS),$(ALL_LANGUAGES))
LANGUAGE_GROUP_EUR_NAME=European

LANGUAGE_GROUPS=CUSTOM CJK CYRILLIC EUR

# Define for host Python
ifndef HOST_PYTHON
HOST_PYTHON:=python3
endif

# Defines for host tools
ifeq ($(HOST_CC),)
HOST_CC:=gcc
endif

HOST_OUTPUT_DIR=Objects/host

# DFU packing address to use
DEVICE_DFU_ADDRESS=0x08000000
DEVICE_DFU_VID_PID=0x28E9:0x0189


# Enumerate all of the include directories (HAL source dirs are used for clang-format only)
APP_INC_DIR=./Core/Inc
MIDDLEWARES_DIR=./Middlewares
BSP_INC_DIR=./Core/BSP
THREADS_DIR=./Core/Threads
SOURCE_CORE_DIR=./Core/Src
BRIEFLZ_DIR=./Core/brieflz
DRIVERS_DIR=./Core/Drivers
PD_DRIVER_DIR=./Core/Drivers/usb-pd
# Exclude USB-PD tests
PD_DRIVER_TESTS_DIR=./Core/Drivers/usb-pd/tests


# Excludes for clang-format

ALL_INCLUDES_EXCEPT:=-path $(PD_DRIVER_DIR) -o -not -name "configuration.h"
ALL_SOURCE_EXCEPT:=-path $(PD_DRIVER_DIR)
# Find-all's used for formatting; have to exclude external modules
ALL_INCLUDES=$(shell find  ./Core -type d \( $(ALL_INCLUDES_EXCEPT) \) -prune -false -o \( -type f \( -name '*.h' -o -name '*.hpp' \) \) )
ALL_SOURCE=$(shell find    ./Core -type d \( $(ALL_SOURCE_EXCEPT)   \) -prune -false -o \( -type f \( -name '*.c' -o -name '*.cpp' \) \) )

# Device dependent settings
ifeq ($(model),$(filter $(model),$(ALL_MINIWARE_MODELS)))
$(info Building for Miniware )
DEVICE_BSP_DIR=./Core/BSP/Miniware
LDSCRIPT=./Core/BSP/Miniware/stm32f103.ld

ifeq ($(model),$(filter $(model),TS101))
# 128K, but logo must be at 99K so their broken ass DFU can flash it
flash_size=98k
bootldr_size=0x8000
DEVICE_DFU_ADDRESS=0x08008000
else
flash_size=62k
bootldr_size=0x4000
DEVICE_DFU_ADDRESS=0x08004000
endif

DEV_GLOBAL_DEFS=-D STM32F103T8Ux       \
                -D STM32F1             \
                -D STM32               \
                -D USE_HAL_DRIVER      \
                -D STM32F103xB         \
                -D USE_RTOS_SYSTICK    \
                -D GCC_ARMCM3          \
                -D ARM_MATH_CM3        \
                -D STM32F10X_MD        \
                -finline-limit=9999999

DEV_LDFLAGS=-Wl,--wrap=printf  -Wl,--no-wchar-size-warning
DEV_AFLAGS=
DEV_CFLAGS=-D VECT_TAB_OFFSET=$(bootldr_size)U
DEV_CXXFLAGS=
CPUFLAGS=-mcpu=cortex-m3  \
         -mthumb          \
         -mfloat-abi=soft

DEVICE_DFU_VID_PID=0x1209:0xDB42
endif # ALL_MINIWARE_MODELS

ifeq ($(model),$(filter $(model),$(ALL_SEQURE_MODELS)))
$(info Building for Sequre )

DEVICE_BSP_DIR=./Core/BSP/Sequre
S_SRCS:=$(shell find $(DEVICE_BSP_DIR) -type f -name '*.S')
LDSCRIPT=./Core/BSP/Sequre/stm32f103.ld
DEV_GLOBAL_DEFS=-D STM32F103T8Ux       \
                -D STM32F1             \
                -D STM32               \
                -D USE_HAL_DRIVER      \
                -D STM32F103xB         \
                -D USE_RTOS_SYSTICK    \
                -D GCC_ARMCM3          \
                -D ARM_MATH_CM3        \
                -D STM32F10X_MD        \
                -finline-limit=9999999

DEV_LDFLAGS=-Wl,--wrap=printf  -Wl,--no-wchar-size-warning
DEV_AFLAGS=
DEV_CFLAGS=-D VECT_TAB_OFFSET=$(bootldr_size)U
DEV_CXXFLAGS=
CPUFLAGS=-mcpu=cortex-m3  \
         -mthumb          \
         -mfloat-abi=soft

flash_size=62k
ifeq ($(model), S60P)
bootldr_size=0x5000
DEVICE_DFU_ADDRESS=0x08005000
else 
# S60 or T55
bootldr_size=0x4400
DEVICE_DFU_ADDRESS=0x08004400
endif
DEVICE_DFU_VID_PID=0x1209:0xDB42
endif # ALL_SEQURE_MODELS

ifeq ($(model),$(filter $(model),$(ALL_MHP30_MODELS)))
$(info Building for MHP30 )

DEVICE_BSP_DIR=./Core/BSP/MHP30
LDSCRIPT=./Core/BSP/MHP30/stm32f103.ld
DEV_GLOBAL_DEFS=-D STM32F103T8Ux    \
                -D STM32F1          \
                -D STM32            \
                -D USE_HAL_DRIVER   \
                -D STM32F103xB      \
                -D USE_RTOS_SYSTICK \
                -D GCC_ARMCM3       \
                -D ARM_MATH_CM3     \
                -D STM32F10X_MD

DEV_LDFLAGS=
DEV_AFLAGS=
DEV_CFLAGS=-D VECT_TAB_OFFSET=$(bootldr_size)U
DEV_CXXFLAGS=
CPUFLAGS=-mcpu=cortex-m3 \
         -mthumb         \
         -mfloat-abi=soft

flash_size=126k
bootldr_size=32k
DEVICE_DFU_ADDRESS=0x08008000
DEVICE_DFU_VID_PID=0x1209:0xDB42
endif # ALL_MHP30_MODELS

ifeq ($(model),$(ALL_PINECIL_MODELS))
$(info Building for Pine64 Pinecilv1)


DEVICE_BSP_DIR=./Core/BSP/Pinecil
S_SRCS:=$(shell find $(DEVICE_BSP_DIR) -type f -name '*.S')
LDSCRIPT=./Core/BSP/Pinecil/Vendor/SoC/gd32vf103/Board/pinecil/Source/GCC/gcc_gd32vf103_flashxip.ld
flash_size=128k
bootldr_size=0x0

# Flags
CPUFLAGS=-march=rv32imaczicsr \
         -mabi=ilp32          \
         -mcmodel=medany      \
         -fsigned-char        \
         -fno-builtin         \
         -nostartfiles

DEV_LDFLAGS=-nostartfiles
DEV_AFLAGS=
DEV_GLOBAL_DEFS=-DRTOS_FREERTOS -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
DEV_CFLAGS=-D VECT_TAB_OFFSET=$(bootldr_size)U
DEV_CXXFLAGS=
endif # ALL_PINECIL_MODELS

ifeq ($(model),$(ALL_PINECIL_V2_MODELS))
$(info Building for Pine64 Pinecilv2 )


DEVICE_BSP_DIR=./Core/BSP/Pinecilv2
LDSCRIPT=./Core/BSP/Pinecilv2/bl_mcu_sdk/drivers/bl702_driver/bl702_flash.ld
DEVICE_DFU_ADDRESS=0x23000000
# DFU starts at the beginning of flash
# Flags
CPUFLAGS=-march=rv32imafczicsr                                \
         -mabi=ilp32f                                         \
         -mcmodel=medany                                      \
         -fsigned-char                                        \
         -fno-builtin                                         \
         -nostartfiles                                        \
         -DportasmHANDLE_INTERRUPT=FreeRTOS_Interrupt_Handler \
         -DARCH_RISCV                                         \
         -D__RISCV_FEATURE_MVE=0                              \
         -DBL702                                              \
         -DBFLB_USE_ROM_DRIVER=0                              \

# Binary blobs suck and they should be ashamed
PINECILV2_SDK_DIR=$(DEVICE_BSP_DIR)/bl_mcu_sdk
PINECILV2_COMPONENTS_DIR=$(PINECILV2_SDK_DIR)/components
PINECILV2_BLE_CRAPWARE_BLOB_DIR=$(PINECILV2_COMPONENTS_DIR)/ble/blecontroller/lib
PINECILV2_RF_CRAPWARE_BLOB_DIR=$(PINECILV2_COMPONENTS_DIR)/ble/bl702_rf/lib

DEV_LDFLAGS=-nostartfiles                         \
            -L $(PINECILV2_BLE_CRAPWARE_BLOB_DIR) \
            -L $(PINECILV2_RF_CRAPWARE_BLOB_DIR)  \
            -l blecontroller_702_m0s1s            \
            -l bl702_rf                           \
            -Wl,--wrap=printf                     \
            -Wl,--defsym=__wrap_printf=bflb_platform_printf

DEV_AFLAGS=
DEV_GLOBAL_DEFS=-DCFG_FREERTOS                                       \
                -DARCH_RISCV                                         \
                -DBL702                                              \
                -DCFG_BLE_ENABLE                                     \
                -DBFLB_BLE                                           \
                -DCFG_BLE                                            \
                -DOPTIMIZE_DATA_EVT_FLOW_FROM_CONTROLLER             \
                -DBL_MCU_SDK                                         \
                -DCFG_CON=1                                          \
                -DCFG_BLE_TX_BUFF_DATA=2                             \
                -DCONFIG_BT_PERIPHERAL                               \
                -DCONFIG_BT_L2CAP_DYNAMIC_CHANNEL                    \
                -DCONFIG_BT_GATT_CLIENT                              \
                -DCONFIG_BT_CONN                                     \
                -DCONFIG_BT_GATT_DIS_PNP                             \
                -DCONFIG_BT_GATT_DIS_SERIAL_NUMBER                   \
                -DCONFIG_BT_GATT_DIS_FW_REV                          \
                -DCONFIG_BT_GATT_DIS_HW_REV                          \
                -DCONFIG_BT_GATT_DIS_SW_REV                          \
                -DCONFIG_BT_ECC                                      \
                -DCONFIG_BT_GATT_DYNAMIC_DB                          \
                -DCONFIG_BT_GATT_SERVICE_CHANGED                     \
                -DCONFIG_BT_KEYS_OVERWRITE_OLDEST                    \
                -DCONFIG_BT_KEYS_SAVE_AGING_COUNTER_ON_PAIRING       \
                -DCONFIG_BT_GAP_PERIPHERAL_PREF_PARAMS               \
                -DCONFIG_BT_BONDABLE                                 \
                -DCONFIG_BT_HCI_VS_EVT_USER                          \
                -DCONFIG_BT_ASSERT                                   \
                -DCONFIG_BT_SIGNING                                  \
                -DCONFIG_BT_SETTINGS_CCC_LAZY_LOADING                \
                -DCONFIG_BT_SETTINGS_USE_PRINTK                      \
                -DCFG_SLEEP                                          \
                -DCONFIG_BT_OBSERVER                                 \
                -DCONFIG_BT_BROADCASTER                              \
                -DportasmHANDLE_INTERRUPT=FreeRTOS_Interrupt_Handler \
                -DCONFIG_BT_DEVICE_NAME=\"Pinecil\"                  \
                -DCONFIG_BT_DEVICE_APPEARANCE=0x06C1
                # -DCFG_BLE_STACK_DBG_PRINT                            \
                # -DCONFIG_BT_CENTRAL                                  \
                # -DCONFIG_BT_ALLROLES                                 \
# -DBFLB_USE_HAL_DRIVER \
# -DCONFIG_BT_SMP

# Required to be turned off due to their drivers tripping warnings
DEV_CFLAGS=-Wno-error=enum-conversion -Wno-type-limits -Wno-implicit-fallthrough -Wno-error=implicit-function-declaration -Wno-error=incompatible-pointer-types
DEV_CXXFLAGS=$(DEV_CFLAGS)
flash_size=128k
bootldr_size=0x0

endif # ALL_PINECIL_V2_MODELS

DEVICE_BSP_INCLUDE_DIRS:= ${shell find ${DEVICE_BSP_DIR} -type d -print}
THREADS_INCLUDE_DIRS:= ${shell find ${THREADS_DIR} -type d -print}
DRIVERS_INCLUDE_DIRS:= ${shell find ${DRIVERS_DIR} -type d -print}
BRIEFLZ_INCLUDE_DIRS:= ${shell find ${BRIEFLZ_DIR} -type d -print}
MIDDLEWARES_INCLUDE_DIRS:= ${shell find ${MIDDLEWARES_DIR} -type d -print}


INCLUDES=-I$(APP_INC_DIR)                              \
         -I$(BSP_INC_DIR)                              \
          ${patsubst %,-I%,${DEVICE_BSP_INCLUDE_DIRS}} \
          ${patsubst %,-I%,${THREADS_INCLUDE_DIRS}}    \
          ${patsubst %,-I%,${DRIVERS_INCLUDE_DIRS}}    \
          ${patsubst %,-I%,${BRIEFLZ_INCLUDE_DIRS}}    \
          ${patsubst %,-I%,${MIDDLEWARES_INCLUDE_DIRS}}

ASM_INC=$(INCLUDES)


SOURCE:=$(shell find ${THREADS_DIR}            -type f -name '*.c') \
        $(shell find ${SOURCE_CORE_DIR}        -type f -name '*.c') \
        $(shell find ${DRIVERS_DIR}            -type f -name '*.c') \
        $(shell find ${DEVICE_BSP_DIR}         -type f -name '*.c') \
        $(shell find ${MIDDLEWARES_DIR}        -type f -name '*.c') \
        $(BRIEFLZ_DIR)/depack.c

# We exclude the USB-PD stack tests $(PD_DRIVER_TESTS_DIR)
SOURCE_CPP:=$(shell find ${THREADS_DIR}      -type f -name '*.cpp') \
            $(shell find ${SOURCE_CORE_DIR}  -type f -name '*.cpp') \
            $(shell find ${DRIVERS_DIR}      -type f -name '*.cpp' -not -path "${PD_DRIVER_TESTS_DIR}/*" ) \
            $(shell find ${DEVICE_BSP_DIR}   -type f -name '*.cpp') \
            $(shell find ${MIDDLEWARES_DIR}  -type f -name '*.cpp')


S_SRCS:=$(shell find $(DEVICE_BSP_DIR) -type f -name '*.S')


# Code optimisation ------------------------------------------------------------
OPTIM=-Os                             \
      -fno-jump-tables                \
      -foptimize-strlen               \
      -faggressive-loop-optimizations \
      -fdevirtualize-at-ltrans        \
      -fmerge-all-constants           \
      -fshort-wchar                   \
      -flto=auto                      \
      -finline-small-functions        \
      -finline-functions              \
      -findirect-inlining             \
      -fdiagnostics-color             \
      -ffunction-sections             \
      -fdata-sections                 \
      -fshort-enums                   \
      -fsingle-precision-constant     \
      -fno-common                     \
      -fno-math-errno                 \
      -ffast-math                     \
      -ffinite-math-only              \
      -fno-signed-zeros               \
      -fsingle-precision-constant

# Global defines ---------------------------------------------------------------
GLOBAL_DEFINES+=$(DEV_GLOBAL_DEFS) -D USE_RTOS_SYSTICK -D MODEL_$(model) -D VECT_TAB_OFFSET=$(bootldr_size)U -fshort-wchar

ifdef swd_enable
GLOBAL_DEFINES+=-DSWD_ENABLE
endif

ifeq ($(model),$(filter $(model),$(ALL_PINECIL_V2_MODELS)))
ifdef ws2812b_enable
	GLOBAL_DEFINES += -DWS2812B_ENABLE
endif
endif

# Libs -------------------------------------------------------------------------
LIBS=

# Compilers --------------------------------------------------------------------
COMPILER=gcc

# arm-none-eabi is the general ARM compiler
# riscv-none-embed is the riscv compiler
# riscv-nuclei-elf is the nuclei tuned one for their cores
ifeq ($(model),$(filter $(model),$(ALL_MINIWARE_MODELS) $(ALL_MHP30_MODELS)))
COMPILER_PREFIX=arm-none-eabi
endif
ifeq ($(model),$(filter $(model),$(ALL_SEQURE_MODELS) ))
COMPILER_PREFIX=arm-none-eabi
endif
ifeq ($(model),$(filter $(model),$(ALL_PINECIL_MODELS) $(ALL_PINECIL_V2_MODELS)))
COMPILER_PREFIX=riscv-none-elf
endif

# Programs ---------------------------------------------------------------------
CC=$(COMPILER_PREFIX)-gcc
CPP=$(COMPILER_PREFIX)-g++
OBJCOPY=$(COMPILER_PREFIX)-objcopy
SIZE=$(COMPILER_PREFIX)-size
OBJDUMP=$(COMPILER_PREFIX)-objdump

# Use gcc in assembler mode so we can use defines etc in assembly
AS=$(COMPILER_PREFIX)-gcc -x assembler-with-cpp

# Linker flags -----------------------------------------------------------------
LINKER_FLAGS=-Wl,--gc-sections                             \
             -Wl,--wrap=malloc                             \
             -Wl,--wrap=free                               \
             -Wl,--undefined=vTaskSwitchContext            \
             -Wl,--undefined=pxCurrentTCB                  \
             -Wl,--defsym=__FLASH_SIZE__=$(flash_size)     \
             -Wl,--defsym=__BOOTLDR_SIZE__=$(bootldr_size) \
             -Wl,--print-memory-usage                      \
                 --specs=nosys.specs                       \
                 --specs=nano.specs                        \
             $(DEV_LDFLAGS)

# Compiler flags ---------------------------------------------------------------
CHECKOPTIONS=-Wtrigraphs                  \
             -Wuninitialized              \
             -Wmissing-braces             \
             -Wfloat-equal                \
             -Wunreachable-code           \
             -Wswitch-default             \
             -Wreturn-type                \
             -Wundef                      \
             -Wparentheses                \
             -Wnonnull                    \
             -Winit-self                  \
             -Wmissing-include-dirs       \
             -Wsequence-point             \
             -Wswitch                     \
             -Wformat                     \
             -Wsign-compare               \
             -Waddress                    \
             -Waggregate-return           \
             -Wmissing-field-initializers \
             -Wshadow                     \
             -Wno-unused-parameter        \
             -Wno-undef                   \
             -Wdouble-promotion

CHECKOPTIONS_C=$(CHECKOPTIONS) -Wbad-function-cast

CXXFLAGS=$(DEV_CXXFLAGS)        \
         $(CPUFLAGS)            \
         $(INCLUDES)            \
         $(GLOBAL_DEFINES)      \
       -D${COMPILER}            \
       -MMD                     \
         $(CHECKOPTIONS)        \
       -std=c++17               \
         $(OPTIM)               \
       -fno-rtti                \
       -fno-exceptions          \
       -fno-non-call-exceptions \
       -fno-use-cxa-atexit      \
       -fno-strict-aliasing     \
       -fno-threadsafe-statics  \
       -T$(LDSCRIPT)

CFLAGS=$(DEV_CFLAGS)     \
       $(CPUFLAGS)       \
       $(INCLUDES)       \
       $(CHECKOPTIONS_C) \
       $(GLOBAL_DEFINES) \
     -D${COMPILER}       \
     -MMD                \
     -std=gnu11          \
     -g3                 \
       $(OPTIM)          \
     -T$(LDSCRIPT)       \
     -c

AFLAGS=$(CPUFLAGS)       \
       $(DEV_AFLAGS)     \
       $(GLOBAL_DEFINES) \
       $(OPTIM)          \
       $(ASM_INC)        \
       $(INCLUDES)

OBJS=$(SOURCE:.c=.o)
OBJS_CPP=$(SOURCE_CPP:.cpp=.o)
OBJS_S=$(S_SRCS:.S=.o)

OUT_OBJS=$(addprefix $(OUTPUT_DIR)/,$(OBJS))
OUT_OBJS_CPP=$(addprefix $(OUTPUT_DIR)/,$(OBJS_CPP))
OUT_OBJS_S=$(addprefix $(OUTPUT_DIR)/,$(OBJS_S))

default: firmware-EN

firmware-%: $(HEXFILE_DIR)/$(model)_%.hex $(HEXFILE_DIR)/$(model)_%.bin $(HEXFILE_DIR)/$(model)_%.dfu
	@true

# Targets for binary files

%.hex: %.elf Makefile
	$(OBJCOPY) $< -O ihex $@

%.bin: %.elf Makefile
	$(OBJCOPY) $< -O binary $@
	$(SIZE) $<

%.dfu: %.bin Makefile
	$(HOST_PYTHON) dfuse-pack.py -b $(DEVICE_DFU_ADDRESS)@0:$< -D $(DEVICE_DFU_VID_PID) $@

$(HEXFILE_DIR)/$(model)_%.elf: \
		$(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)    \
		$(OUTPUT_DIR)/Core/Gen/Translation.%.o       \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o \
		Makefile $(LDSCRIPT)
	@test -d $(@D) || mkdir -p $(@D)
	@echo Linking $@
	@$(CPP) $(CXXFLAGS) $(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP) \
		$(OUTPUT_DIR)/Core/Gen/Translation.$*.o      \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o \
		$(LIBS) $(LINKER_FLAGS) -o$@ -Wl,-Map=$@.map

$(HEXFILE_DIR)/$(model)_string_compressed_%.elf: \
		$(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)      \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz.%.o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o   \
		Makefile $(LDSCRIPT)
	@test -d $(@D) || mkdir -p $(@D)
	@echo Linking $@
	@$(CPP) $(CXXFLAGS) $(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP) \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz.$*.o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o    \
		$(LIBS) $(LINKER_FLAGS) -o$@ -Wl,-Map=$@.map

$(HEXFILE_DIR)/$(model)_font_compressed_%.elf: \
		$(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)           \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz_font.%.o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o        \
		Makefile $(LDSCRIPT)
	@test -d $(@D) || mkdir -p $(@D)
	@echo Linking $@
	@$(CPP) $(CXXFLAGS) $(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP) \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz_font.$*.o  \
		$(OUTPUT_DIR)/Core/LangSupport/lang_single.o          \
		$(LIBS) $(LINKER_FLAGS) -o$@ -Wl,-Map=$@.map

$(OUT_OBJS): $(OUTPUT_DIR)/%.o: %.c Makefile
	@test -d $(@D) || mkdir -p $(@D)
	@$(CC) -c $(CFLAGS) $< -o $@

$(OUTPUT_DIR)/%.o: %.cpp Makefile
	@test -d $(@D) || mkdir -p $(@D)
	@$(CPP) -c $(CXXFLAGS) $< -o $@

$(OUT_OBJS_S): $(OUTPUT_DIR)/%.o: %.S Makefile
	@test -d $(@D) || mkdir -p $(@D)
	@echo 'Building file: $<'
	@$(AS) -c $(AFLAGS) $< -o $@

Core/Gen/Translation.%.cpp $(OUTPUT_DIR)/Core/Gen/translation.files/%.pickle: ../Translations/translation_%.json \
		../Translations/make_translation.py           \
		../Translations/translations_definitions.json \
		../Translations/font_tables.py                \
		Makefile ../Translations/wqy-bitmapsong/wenquanyi_9pt.bdf \
		Core/Gen/macros.txt
	@test -d Core/Gen || mkdir -p Core/Gen
	@test -d $(OUTPUT_DIR)/Core/Gen/translation.files || mkdir -p $(OUTPUT_DIR)/Core/Gen/translation.files
	@echo 'Generating translations for language $*'
	@$(HOST_PYTHON) ../Translations/make_translation.py \
		--macros "$(CURDIR)/Core/Gen/macros.txt"      \
		-o "$(CURDIR)/Core/Gen/Translation.$*.cpp"    \
		--output-pickled "$(OUTPUT_DIR)/Core/Gen/translation.files/$*.pickle" \
		$*

Core/Gen/macros.txt: Makefile
	@test -d "$(CURDIR)/Core/Gen" || mkdir -p "$(CURDIR)/Core/Gen"
	echo "#include " | $(CC) -dM -E $(CFLAGS) -MF "$(CURDIR)/Core/Gen/macros.tmp" - > "$(CURDIR)/Core/Gen/macros.txt"

# The recipes to produce compressed translation data

$(OUTPUT_DIR)/Core/Gen/translation.files/%.o: Core/Gen/Translation.%.cpp
	@test -d $(@D) || mkdir -p $(@D)
	@echo Generating $@
	@$(CPP) -c $(filter-out -flto=auto ,$(CXXFLAGS)) $< -o $@

$(OUTPUT_DIR)/Core/Gen/translation.files/multi.%.o: Core/Gen/Translation_multi.%.cpp
	@test -d $(@D) || mkdir -p $(@D)
	@echo Generating $@
	@$(CPP) -c $(filter-out -flto=auto ,$(CXXFLAGS)) $< -o $@

$(HOST_OUTPUT_DIR)/brieflz/libbrieflz.so: Core/brieflz/brieflz.c Core/brieflz/depack.c
	@test -d $(@D) || mkdir -p $(@D)
	@echo Building host brieflz shared library $@
	@$(HOST_CC) -fPIC -shared -DBLZ_DLL -DBLZ_DLL_EXPORTS -O $^ -o $@

Core/Gen/Translation_brieflz.%.cpp: $(OUTPUT_DIR)/Core/Gen/translation.files/%.o $(OUTPUT_DIR)/Core/Gen/translation.files/%.pickle $(HOST_OUTPUT_DIR)/brieflz/libbrieflz.so Core/Gen/macros.txt
	@test -d $(@D) || mkdir -p $(@D)
	@echo Generating BriefLZ compressed translation for $*
	@OBJCOPY=$(OBJCOPY) $(HOST_PYTHON) ../Translations/make_translation.py \
		--macros "$(CURDIR)/Core/Gen/macros.txt"           \
		-o "$(CURDIR)/Core/Gen/Translation_brieflz.$*.cpp" \
		--input-pickled "$(OUTPUT_DIR)/Core/Gen/translation.files/$*.pickle" \
		--strings-obj "$(OUTPUT_DIR)/Core/Gen/translation.files/$*.o"        \
		$*

Core/Gen/Translation_brieflz_font.%.cpp: $(OUTPUT_DIR)/Core/Gen/translation.files/%.pickle $(HOST_OUTPUT_DIR)/brieflz/libbrieflz.so Core/Gen/macros.txt
	@test -d $(@D) || mkdir -p $(@D)
	@echo Generating BriefLZ compressed translation font for $*
	@$(HOST_PYTHON) ../Translations/make_translation.py        \
		--macros $(PWD)/Core/Gen/macros.txt                \
		-o $(PWD)/Core/Gen/Translation_brieflz_font.$*.cpp \
		--input-pickled $(OUTPUT_DIR)/Core/Gen/translation.files/$*.pickle \
		--compress-font \
		$*

# The recipes to produce multi-language firmwares:

# Usage: $(eval $(call multi_lang_rule,$(1)=group_code,$(2)=group_name,$(3)=lang_codes))
define multi_lang_rule

$(HEXFILE_DIR)/$(model)_multi_$(2).elf: \
		$(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)       \
		$(OUTPUT_DIR)/Core/Gen/Translation_multi.$(1).o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_multi.o     \
		Makefile $(LDSCRIPT)
	@test -d $$(@D) || mkdir -p $$(@D)
	@echo Linking $$@
	@$(CPP) $(CXXFLAGS) $(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP) \
		$(OUTPUT_DIR)/Core/Gen/Translation_multi.$(1).o       \
		$(OUTPUT_DIR)/Core/LangSupport/lang_multi.o           \
		$(LIBS) $(LINKER_FLAGS) -o$$@ -Wl,-Map=$$@.map

$(HEXFILE_DIR)/$(model)_multi_compressed_$(2).elf: \
		$(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)               \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz_multi.$(1).o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_multi.o             \
		Makefile $(LDSCRIPT)
	@test -d $$(@D) || mkdir -p $$(@D)
	@echo Linking $$@
	@$(CPP) $(CXXFLAGS) $(OUT_OBJS_S) $(OUT_OBJS) $(OUT_OBJS_CPP)   \
		$(OUTPUT_DIR)/Core/Gen/Translation_brieflz_multi.$(1).o \
		$(OUTPUT_DIR)/Core/LangSupport/lang_multi.o             \
		$(LIBS) $(LINKER_FLAGS) -o$$@ -Wl,-Map=$$@.map

Core/Gen/Translation_multi.$(1).cpp: $(patsubst %,../Translations/translation_%.json,$(3)) \
		../Translations/make_translation.py           \
		../Translations/translations_definitions.json \
		../Translations/font_tables.py                \
		Makefile ../Translations/wqy-bitmapsong/wenquanyi_9pt.bdf \
		Core/Gen/macros.txt
	@test -d Core/Gen || mkdir -p Core/Gen
	@test -d $(OUTPUT_DIR)/Core/Gen/translation.files || mkdir -p $(OUTPUT_DIR)/Core/Gen/translation.files
	@echo 'Generating translations for multi-language $(2)'
	@$(HOST_PYTHON) ../Translations/make_translation.py   \
		--macros "$(CURDIR)/Core/Gen/macros.txt"           \
		-o "$(CURDIR)/Core/Gen/Translation_multi.$(1).cpp" \
		--output-pickled "$(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).pickle" \
		$(3)

$(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).pickle: Core/Gen/Translation_multi.$(1).cpp

Core/Gen/Translation_brieflz_multi.$(1).cpp: $(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).o $(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).pickle $(HOST_OUTPUT_DIR)/brieflz/libbrieflz.so Core/Gen/macros.txt
	@test -d $$(@D) || mkdir -p $$(@D)
	@echo Generating BriefLZ compressed translation for multi-language $(2)
	@OBJCOPY=$(OBJCOPY) $(HOST_PYTHON) ../Translations/make_translation.py \
		--macros "$(CURDIR)/Core/Gen/macros.txt"                   \
		-o "$(CURDIR)/Core/Gen/Translation_brieflz_multi.$(1).cpp" \
		--input-pickled "$(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).pickle" \
		--strings-obj "$(OUTPUT_DIR)/Core/Gen/translation.files/multi.$(1).o"        \
		--compress-font \
		$(3)

endef # multi_lang_rule

# Add multi-language firmware rules:
$(foreach group_code,$(LANGUAGE_GROUPS),$(eval $(call multi_lang_rule,$(group_code),$(LANGUAGE_GROUP_$(group_code)_NAME),$(LANGUAGE_GROUP_$(group_code)_LANGS))))

# Clean up targets

clean:
	rm -Rf Core/Gen
	rm -Rf $(OUTPUT_DIR_BASE)
	rm -Rf $(HEXFILE_DIR)/*
	rm -Rf ../Translations/__pycache__

clean-all: clean
	rm -Rf $(HEXFILE_DIR)

# Style formatting helper targets

# Overwrite source files in your local repo copy according to IronOS code style rules (source/.clang-format) WITHOUT A WARNING!
# Use `git diff` or your favorite diff tool via `git difftool` before commit to make sure there are no false-negative changes.
# If so, report an issue, please.
style:
	@for src in $(ALL_SOURCE) $(ALL_INCLUDES); do echo "Formatting $$src" ; clang-format -i "$$src" ; done;
	@echo "Done! Please, check the changes before commit."

# Code style checks using clang-format:
# - show output in gcc-like error compatible format for IDEs/editors;
# - external variables for debug purposes (can be used at the same time, i.e. STOP=1 LIST=1 ...):
#   * call `make check-style STOP=1` to exit after first failed file;
#   * call `make check-style LIST=1` to show failed file names only;
# - here we process only list of files;
# - per-file check happens in scripts/deploy.sh : check_style_file - since shell commands involved, the check logic moved to shell script for better maintainance outside of makefile syntax crossing.
# - $? / error / STOP conditional logic needed to:
#   * check errors in formatting from deploy.sh
#   * process STOP env variable
check-style:
	@error=0; export LIST=$$LIST; for src in $(ALL_SOURCE) $(ALL_INCLUDES) ; do \
		../scripts/deploy.sh  check_style_file  "$$src" ; \
		test "$${?}" -eq 1 && export error=1 ; \
		test "$${error}" -eq 1 && test -n "$${STOP}" && break; \
	done; \
	if [ $$error -eq 0 ] ; then  echo "" && echo "" && echo "Style check: PASS" && echo "" && echo "" && exit 0 ; \
	else  echo "" && echo "" && echo "Style check: FAIL! Please, check the log above for the details." && echo "If there is a false-negative trigger, please, report an issue attaching the log or link to the log!" && echo "" && echo "" && exit 1 ; \
	fi;

.PHONY: style  check-style  all  clean  default  clean-all
.SECONDARY:

# Pull in dependency info for *existing* .o files
-include $(OUT_OBJS:.o=.d)
-include $(OUT_OBJS_CPP:.o=.d)
-include $(OUTPUT_DIR)/Core/Gen/Translation.*.d
-include $(OUTPUT_DIR)/Core/Gen/Translation_*.d
-include $(OUTPUT_DIR)/Core/Gen/translation.files/*.d


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c
================================================
/* ----------------------------------------------------------------------
 * $Date:        5. February 2013
 * $Revision:    V1.02
 *
 * Project:      CMSIS-RTOS API
 * Title:        cmsis_os.c
 *
 * Version 0.02
 *    Initial Proposal Phase
 * Version 0.03
 *    osKernelStart added, optional feature: main started as thread
 *    osSemaphores have standard behavior
 *    osTimerCreate does not start the timer, added osTimerStart
 *    osThreadPass is renamed to osThreadYield
 * Version 1.01
 *    Support for C++ interface
 *     - const attribute removed from the osXxxxDef_t typedef's
 *     - const attribute added to the osXxxxDef macros
 *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
 *    Added: osKernelInitialize
 * Version 1.02
 *    Control functions for short timeouts in microsecond resolution:
 *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
 *    Removed: osSignalGet
 *
 *
 *----------------------------------------------------------------------------
 *
 * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved.
 * Portions Copyright (c) 2013 ARM LIMITED
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  - Neither the name of ARM  nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/

/**
 ******************************************************************************
 * @file    cmsis_os.c
 * @author  MCD Application Team
 * @date    03-March-2017
 * @brief   CMSIS-RTOS API implementation for FreeRTOS V9.0.0
 ******************************************************************************
 * @attention
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted, provided that the following conditions are met:
 *
 * 1. Redistribution of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 * 3. Neither the name of STMicroelectronics nor the names of other
 *    contributors to this software may be used to endorse or promote products
 *    derived from this software without specific written permission.
 * 4. This software, including modifications and/or derivative works of this
 *    software, must execute solely and exclusively on microcontroller or
 *    microprocessor devices manufactured by or for STMicroelectronics.
 * 5. Redistribution and use of this software other than as permitted under
 *    this license is void and will automatically terminate your rights under
 *    this license.
 *
 * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
 * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
 * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
 * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************
 */

#include "cmsis_os.h"
#include "portmacro.h"
#include 

/*
 * ARM Compiler 4/5
 */
#if defined(__CC_ARM)

#define __ASM           __asm
#define __INLINE        __inline
#define __STATIC_INLINE static __inline
#include "cmsis_armcc.h"

/*
 * GNU Compiler
 */
#elif defined(__GNUC__)

#define __ASM           __asm  /*!< asm keyword for GNU Compiler          */
#define __INLINE        inline /*!< inline keyword for GNU Compiler       */
#define __STATIC_INLINE static inline
uint32_t __get_IPSR(void);
// #include "cmsis_gcc.h"

/*
 * IAR Compiler
 */
#elif defined(__ICCARM__)

#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif

#include 
#endif

extern void xPortSysTickHandler(void);

/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority(osPriority priority) {
  unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;

  if (priority != osPriorityError) {
    fpriority += (priority - osPriorityIdle);
  }

  return fpriority;
}

#if (INCLUDE_uxTaskPriorityGet == 1)
/* Convert from FreeRTOS priority number to CMSIS type osPriority */
static osPriority makeCmsisPriority(unsigned portBASE_TYPE fpriority) {
  osPriority priority = osPriorityError;

  if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) {
    priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY));
  }

  return priority;
}
#endif

/* Determine whether we are in thread mode or handler mode. */
static int inHandlerMode(void) { return __get_IPSR() != 0; }

/*********************** Kernel Control Functions *****************************/
/**
 * @brief  Initialize the RTOS Kernel for creating objects.
 * @retval status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
 */
osStatus osKernelInitialize(void);

/**
 * @brief  Start the RTOS Kernel with executing the specified thread.
 * @param  thread_def    thread definition referenced with \ref osThread.
 * @param  argument      pointer that is passed to the thread function as start argument.
 * @retval status code that indicates the execution status of the function
 * @note   MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
 */
osStatus osKernelStart(void) {
  vTaskStartScheduler();

  return osOK;
}

/**
 * @brief  Check if the RTOS kernel is already started
 * @param  None
 * @retval (0) RTOS is not started
 *         (1) RTOS is started
 *         (-1) if this feature is disabled in FreeRTOSConfig.h
 * @note  MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
 */
int32_t osKernelRunning(void) {
#if ((INCLUDE_xTaskGetSchedulerState == 1) || (configUSE_TIMERS == 1))
  if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED)
    return 0;
  else
    return 1;
#else
  return (-1);
#endif
}

#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
/**
 * @brief  Get the value of the Kernel SysTick timer
 * @param  None
 * @retval None
 * @note   MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
 */
uint32_t osKernelSysTick(void) {
  if (inHandlerMode()) {
    return xTaskGetTickCountFromISR();
  } else {
    return xTaskGetTickCount();
  }
}
#endif // System Timer available
/*********************** Thread Management *****************************/
/**
 * @brief  Create a thread and add it to Active Threads and set it to state READY.
 * @param  thread_def    thread definition referenced with \ref osThread.
 * @param  argument      pointer that is passed to the thread function as start argument.
 * @retval thread ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
 */
osThreadId osThreadCreate(const osThreadDef_t *thread_def, void *argument) {
  TaskHandle_t handle;

#if (configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)
  if ((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread, (const portCHAR *)thread_def->name, thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
                               thread_def->buffer, thread_def->controlblock);
  } else {
    if (xTaskCreate((TaskFunction_t)thread_def->pthread, (const portCHAR *)thread_def->name, thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), &handle) != pdPASS) {
      return NULL;
    }
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1)

  handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread, (const portCHAR *)thread_def->name, thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), thread_def->buffer,
                             thread_def->controlblock);
#else
  if (xTaskCreate((TaskFunction_t)thread_def->pthread, (const portCHAR *)thread_def->name, thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), &handle) != pdPASS) {
    return NULL;
  }
#endif

  return handle;
}

/**
 * @brief  Return the thread ID of the current running thread.
 * @retval thread ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
 */
osThreadId osThreadGetId(void) {
#if ((INCLUDE_xTaskGetCurrentTaskHandle == 1) || (configUSE_MUTEXES == 1))
  return xTaskGetCurrentTaskHandle();
#else
  return NULL;
#endif
}

/**
 * @brief  Terminate execution of a thread and remove it from Active Threads.
 * @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
 */
osStatus osThreadTerminate(osThreadId thread_id) {
#if (INCLUDE_vTaskDelete == 1)
  vTaskDelete(thread_id);
  return osOK;
#else
  return osErrorOS;
#endif
}

/**
 * @brief  Pass control to next thread that is in state \b READY.
 * @retval status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
 */
osStatus osThreadYield(void) {
  taskYIELD();

  return osOK;
}

/**
 * @brief   Change priority of an active thread.
 * @param   thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @param   priority      new priority value for the thread function.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
 */
osStatus osThreadSetPriority(osThreadId thread_id, osPriority priority) {
#if (INCLUDE_vTaskPrioritySet == 1)
  vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority));
  return osOK;
#else
  return osErrorOS;
#endif
}

/**
 * @brief   Get current priority of an active thread.
 * @param   thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval  current priority value of the thread function.
 * @note   MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
 */
osPriority osThreadGetPriority(osThreadId thread_id) {
#if (INCLUDE_uxTaskPriorityGet == 1)
  if (inHandlerMode()) {
    return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id));
  } else {
    return makeCmsisPriority(uxTaskPriorityGet(thread_id));
  }
#else
  return osPriorityError;
#endif
}

/*********************** Generic Wait Functions *******************************/
/**
 * @brief   Wait for Timeout (Time Delay)
 * @param   millisec      time delay value
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osDelay(uint32_t millisec) {
#if INCLUDE_vTaskDelay
  TickType_t ticks = millisec / portTICK_PERIOD_MS;

  vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */

  return osOK;
#else
  (void)millisec;

  return osErrorResource;
#endif
}

#if (defined(osFeature_Wait) && (osFeature_Wait != 0)) /* Generic Wait available */
/**
 * @brief  Wait for Signal, Message, Mail, or Timeout
 * @param   millisec  timeout value or 0 in case of no time-out
 * @retval  event that contains signal, message, or mail information or error code.
 * @note   MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
 */
osEvent osWait(uint32_t millisec);

#endif /* Generic Wait available */

/***********************  Timer Management Functions ***************************/
/**
 * @brief  Create a timer.
 * @param  timer_def     timer object referenced with \ref osTimer.
 * @param  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
 * @param  argument      argument to the timer call back function.
 * @retval  timer ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
 */
osTimerId osTimerCreate(const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
#if (configUSE_TIMERS == 1)

#if ((configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1))
  if (timer_def->controlblock != NULL) {
    return xTimerCreateStatic((const char *)"",
                              1, // period should be filled when starting the Timer using osTimerStart
                              (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *)argument, (TaskFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock);
  } else {
    return xTimerCreate((const char *)"",
                        1, // period should be filled when starting the Timer using osTimerStart
                        (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *)argument, (TaskFunction_t)timer_def->ptimer);
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1)
  return xTimerCreateStatic((const char *)"",
                            1, // period should be filled when starting the Timer using osTimerStart
                            (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *)argument, (TaskFunction_t)timer_def->ptimer, (StaticTimer_t *)timer_def->controlblock);
#else
  return xTimerCreate((const char *)"",
                      1, // period should be filled when starting the Timer using osTimerStart
                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE, (void *)argument, (TaskFunction_t)timer_def->ptimer);
#endif

#else
  return NULL;
#endif
}

/**
 * @brief  Start or restart a timer.
 * @param  timer_id      timer ID obtained by \ref osTimerCreate.
 * @param  millisec      time delay value of the timer.
 * @retval  status code that indicates the execution status of the function
 * @note   MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
 */
osStatus osTimerStart(osTimerId timer_id, uint32_t millisec) {
  osStatus result = osOK;
#if (configUSE_TIMERS == 1)
  portBASE_TYPE taskWoken = pdFALSE;
  TickType_t    ticks     = millisec / portTICK_PERIOD_MS;

  if (ticks == 0)
    ticks = 1;

  if (inHandlerMode()) {
    if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS) {
      result = osErrorOS;
    } else {
      portEND_SWITCHING_ISR(taskWoken);
    }
  } else {
    if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS)
      result = osErrorOS;
  }

#else
  result = osErrorOS;
#endif
  return result;
}

/**
 * @brief  Stop a timer.
 * @param  timer_id      timer ID obtained by \ref osTimerCreate
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
 */
osStatus osTimerStop(osTimerId timer_id) {
  osStatus result = osOK;
#if (configUSE_TIMERS == 1)
  portBASE_TYPE taskWoken = pdFALSE;

  if (inHandlerMode()) {
    if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xTimerStop(timer_id, 0) != pdPASS) {
      result = osErrorOS;
    }
  }
#else
  result = osErrorOS;
#endif
  return result;
}

/**
 * @brief  Delete a timer.
 * @param  timer_id      timer ID obtained by \ref osTimerCreate
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
 */
osStatus osTimerDelete(osTimerId timer_id) {
  osStatus result = osOK;

#if (configUSE_TIMERS == 1)

  if (inHandlerMode()) {
    return osErrorISR;
  } else {
    if ((xTimerDelete(timer_id, osWaitForever)) != pdPASS) {
      result = osErrorOS;
    }
  }

#else
  result = osErrorOS;
#endif

  return result;
}

/****************************  Mutex Management ********************************/
/**
 * @brief  Create and Initialize a Mutex object
 * @param  mutex_def     mutex definition referenced with \ref osMutex.
 * @retval  mutex ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
 */
osMutexId osMutexCreate(const osMutexDef_t *mutex_def) {
#if (configUSE_MUTEXES == 1)

#if (configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)

  if (mutex_def->controlblock != NULL) {
    return xSemaphoreCreateMutexStatic(mutex_def->controlblock);
  } else {
    return xSemaphoreCreateMutex();
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1)
  return xSemaphoreCreateMutexStatic(mutex_def->controlblock);
#else
  return xSemaphoreCreateMutex();
#endif
#else
  return NULL;
#endif
}

/**
 * @brief Wait until a Mutex becomes available
 * @param mutex_id      mutex ID obtained by \ref osMutexCreate.
 * @param millisec      timeout value or 0 in case of no time-out.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
 */
osStatus osMutexWait(osMutexId mutex_id, uint32_t millisec) {
  TickType_t    ticks;
  portBASE_TYPE taskWoken = pdFALSE;

  if (mutex_id == NULL) {
    return osErrorParameter;
  }

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (inHandlerMode()) {
    if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
    return osErrorOS;
  }

  return osOK;
}

/**
 * @brief Release a Mutex that was obtained by \ref osMutexWait
 * @param mutex_id      mutex ID obtained by \ref osMutexCreate.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
 */
osStatus osMutexRelease(osMutexId mutex_id) {
  osStatus      result    = osOK;
  portBASE_TYPE taskWoken = pdFALSE;

  if (inHandlerMode()) {
    if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else if (xSemaphoreGive(mutex_id) != pdTRUE) {
    result = osErrorOS;
  }
  return result;
}

/**
 * @brief Delete a Mutex
 * @param mutex_id  mutex ID obtained by \ref osMutexCreate.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
 */
osStatus osMutexDelete(osMutexId mutex_id) {
  if (inHandlerMode()) {
    return osErrorISR;
  }

  vQueueDelete(mutex_id);

  return osOK;
}

/********************  Semaphore Management Functions **************************/

#if (defined(osFeature_Semaphore) && (osFeature_Semaphore != 0))

/**
 * @brief Create and Initialize a Semaphore object used for managing resources
 * @param semaphore_def semaphore definition referenced with \ref osSemaphore.
 * @param count         number of available resources.
 * @retval  semaphore ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
 */
osSemaphoreId osSemaphoreCreate(const osSemaphoreDef_t *semaphore_def, int32_t count) {
#if (configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)

  osSemaphoreId sema;

  if (semaphore_def->controlblock != NULL) {
    if (count == 1) {
      return xSemaphoreCreateBinaryStatic(semaphore_def->controlblock);
    } else {
#if (configUSE_COUNTING_SEMAPHORES == 1)
      return xSemaphoreCreateCountingStatic(count, count, semaphore_def->controlblock);
#else
      return NULL;
#endif
    }
  } else {
    if (count == 1) {
      vSemaphoreCreateBinary(sema);
      return sema;
    } else {
#if (configUSE_COUNTING_SEMAPHORES == 1)
      return xSemaphoreCreateCounting(count, count);
#else
      return NULL;
#endif
    }
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1) // configSUPPORT_DYNAMIC_ALLOCATION == 0
  if (count == 1) {
    return xSemaphoreCreateBinaryStatic(semaphore_def->controlblock);
  } else {
#if (configUSE_COUNTING_SEMAPHORES == 1)
    return xSemaphoreCreateCountingStatic(count, count, semaphore_def->controlblock);
#else
    return NULL;
#endif
  }
#else // configSUPPORT_STATIC_ALLOCATION == 0  && configSUPPORT_DYNAMIC_ALLOCATION == 1
  osSemaphoreId sema;

  if (count == 1) {
    vSemaphoreCreateBinary(sema);
    return sema;
  } else {
#if (configUSE_COUNTING_SEMAPHORES == 1)
    return xSemaphoreCreateCounting(count, count);
#else
    return NULL;
#endif
  }
#endif
}

/**
 * @brief Wait until a Semaphore token becomes available
 * @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
 * @param  millisec      timeout value or 0 in case of no time-out.
 * @retval  number of available tokens, or -1 in case of incorrect parameters.
 * @note   MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
 */
int32_t osSemaphoreWait(osSemaphoreId semaphore_id, uint32_t millisec) {
  TickType_t    ticks;
  portBASE_TYPE taskWoken = pdFALSE;

  if (semaphore_id == NULL) {
    return osErrorParameter;
  }

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (inHandlerMode()) {
    if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
    return osErrorOS;
  }

  return osOK;
}

/**
 * @brief Release a Semaphore token
 * @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
 */
osStatus osSemaphoreRelease(osSemaphoreId semaphore_id) {
  osStatus      result    = osOK;
  portBASE_TYPE taskWoken = pdFALSE;

  if (inHandlerMode()) {
    if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xSemaphoreGive(semaphore_id) != pdTRUE) {
      result = osErrorOS;
    }
  }

  return result;
}

/**
 * @brief Delete a Semaphore
 * @param  semaphore_id  semaphore object referenced with \ref osSemaphore.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
 */
osStatus osSemaphoreDelete(osSemaphoreId semaphore_id) {
  if (inHandlerMode()) {
    return osErrorISR;
  }

  vSemaphoreDelete(semaphore_id);

  return osOK;
}

#endif /* Use Semaphores */

/*******************   Memory Pool Management Functions  ***********************/

#if (defined(osFeature_Pool) && (osFeature_Pool != 0))

// TODO
// This is a primitive and inefficient wrapper around the existing FreeRTOS memory management.
// A better implementation will have to modify heap_x.c!

typedef struct os_pool_cb {
  void    *pool;
  uint8_t *markers;
  uint32_t pool_sz;
  uint32_t item_sz;
  uint32_t currentIndex;
} os_pool_cb_t;

/**
 * @brief Create and Initialize a memory pool
 * @param  pool_def      memory pool definition referenced with \ref osPool.
 * @retval  memory pool ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
 */
osPoolId osPoolCreate(const osPoolDef_t *pool_def) {
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
  osPoolId thePool;
  int      itemSize = 4 * ((pool_def->item_sz + 3) / 4);
  uint32_t i;

  /* First have to allocate memory for the pool control block. */
  thePool = pvPortMalloc(sizeof(os_pool_cb_t));

  if (thePool) {
    thePool->pool_sz      = pool_def->pool_sz;
    thePool->item_sz      = itemSize;
    thePool->currentIndex = 0;

    /* Memory for markers */
    thePool->markers = pvPortMalloc(pool_def->pool_sz);

    if (thePool->markers) {
      /* Now allocate the pool itself. */
      thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize);

      if (thePool->pool) {
        for (i = 0; i < pool_def->pool_sz; i++) {
          thePool->markers[i] = 0;
        }
      } else {
        vPortFree(thePool->markers);
        vPortFree(thePool);
        thePool = NULL;
      }
    } else {
      vPortFree(thePool);
      thePool = NULL;
    }
  }

  return thePool;

#else
  return NULL;
#endif
}

/**
 * @brief Allocate a memory block from a memory pool
 * @param pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 * @retval  address of the allocated memory block or NULL in case of no memory available.
 * @note   MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
 */
void *osPoolAlloc(osPoolId pool_id) {
  int      dummy = 0;
  void    *p     = NULL;
  uint32_t i;
  uint32_t index;

  if (inHandlerMode()) {
    dummy = portSET_INTERRUPT_MASK_FROM_ISR();
  } else {
    vPortEnterCritical();
  }

  for (i = 0; i < pool_id->pool_sz; i++) {
    index = pool_id->currentIndex + i;
    if (index >= pool_id->pool_sz) {
      index = 0;
    }

    if (pool_id->markers[index] == 0) {
      pool_id->markers[index] = 1;
      p                       = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz));
      pool_id->currentIndex   = index;
      break;
    }
  }

  if (inHandlerMode()) {
    portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy);
  } else {
    vPortExitCritical();
  }

  return p;
}

/**
 * @brief Allocate a memory block from a memory pool and set memory block to zero
 * @param  pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 * @retval  address of the allocated memory block or NULL in case of no memory available.
 * @note   MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
 */
void *osPoolCAlloc(osPoolId pool_id) {
  void *p = osPoolAlloc(pool_id);

  if (p != NULL) {
    memset(p, 0, sizeof(pool_id->pool_sz));
  }

  return p;
}

/**
 * @brief Return an allocated memory block back to a specific memory pool
 * @param  pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 * @param  block         address of the allocated memory block that is returned to the memory pool.
 * @retval  status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
 */
osStatus osPoolFree(osPoolId pool_id, void *block) {
  uint32_t index;

  if (pool_id == NULL) {
    return osErrorParameter;
  }

  if (block == NULL) {
    return osErrorParameter;
  }

  if (block < pool_id->pool) {
    return osErrorParameter;
  }

  index = (uint32_t)block - (uint32_t)(pool_id->pool);
  if (index % pool_id->item_sz) {
    return osErrorParameter;
  }
  index = index / pool_id->item_sz;
  if (index >= pool_id->pool_sz) {
    return osErrorParameter;
  }

  pool_id->markers[index] = 0;

  return osOK;
}

#endif /* Use Memory Pool Management */

/*******************   Message Queue Management Functions  *********************/

#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) /* Use Message Queues */

/**
 * @brief Create and Initialize a Message Queue
 * @param queue_def     queue definition referenced with \ref osMessageQ.
 * @param  thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 * @retval  message queue ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
 */
osMessageQId osMessageCreate(const osMessageQDef_t *queue_def, osThreadId thread_id) {
  (void)thread_id;

#if (configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)

  if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
    return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
  } else {
    return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1)
  return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
#else
  return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
#endif
}

/**
 * @brief Put a Message to a Queue.
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @param  info      message information.
 * @param  millisec  timeout value or 0 in case of no time-out.
 * @retval status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
 */
osStatus osMessagePut(osMessageQId queue_id, uint32_t info, uint32_t millisec) {
  portBASE_TYPE taskWoken = pdFALSE;
  TickType_t    ticks;

  ticks = millisec / portTICK_PERIOD_MS;
  if (ticks == 0) {
    ticks = 1;
  }

  if (inHandlerMode()) {
    if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
      return osErrorOS;
    }
  }

  return osOK;
}

/**
 * @brief Get a Message or Wait for a Message from a Queue.
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @param  millisec  timeout value or 0 in case of no time-out.
 * @retval event information that includes status code.
 * @note   MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
 */
osEvent osMessageGet(osMessageQId queue_id, uint32_t millisec) {
  portBASE_TYPE taskWoken;
  TickType_t    ticks;
  osEvent       event;

  event.def.message_id = queue_id;
  event.value.v        = 0;

  if (queue_id == NULL) {
    event.status = osErrorParameter;
    return event;
  }

  taskWoken = pdFALSE;

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (inHandlerMode()) {
    if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
      /* We have mail */
      event.status = osEventMessage;
    } else {
      event.status = osOK;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
      /* We have mail */
      event.status = osEventMessage;
    } else {
      event.status = (ticks == 0) ? osOK : osEventTimeout;
    }
  }

  return event;
}

#endif /* Use Message Queues */

/********************   Mail Queue Management Functions  ***********************/
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) /* Use Mail Queues */

typedef struct os_mailQ_cb {
  const osMailQDef_t *queue_def;
  QueueHandle_t       handle;
  osPoolId            pool;
} os_mailQ_cb_t;

/**
 * @brief Create and Initialize mail queue
 * @param  queue_def     reference to the mail queue definition obtain with \ref osMailQ
 * @param   thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 * @retval mail queue ID for reference by other functions or NULL in case of error.
 * @note   MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
 */
osMailQId osMailCreate(const osMailQDef_t *queue_def, osThreadId thread_id) {
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
  (void)thread_id;

  osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL};

  /* Create a mail queue control block */

  *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb));

  if (*(queue_def->cb) == NULL) {
    return NULL;
  }
  (*(queue_def->cb))->queue_def = queue_def;

  /* Create a queue in FreeRTOS */
  (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *));

  if ((*(queue_def->cb))->handle == NULL) {
    vPortFree(*(queue_def->cb));
    return NULL;
  }

  /* Create a mail pool */
  (*(queue_def->cb))->pool = osPoolCreate(&pool_def);
  if ((*(queue_def->cb))->pool == NULL) {
    // TODO: Delete queue. How to do it in FreeRTOS?
    vPortFree(*(queue_def->cb));
    return NULL;
  }

  return *(queue_def->cb);
#else
  return NULL;
#endif
}

/**
 * @brief Allocate a memory block from a mail
 * @param  queue_id      mail queue ID obtained with \ref osMailCreate.
 * @param  millisec      timeout value or 0 in case of no time-out.
 * @retval pointer to memory block that can be filled with mail or NULL in case error.
 * @note   MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
 */
void *osMailAlloc(osMailQId queue_id, uint32_t millisec) {
  (void)millisec;
  void *p;

  if (queue_id == NULL) {
    return NULL;
  }

  p = osPoolAlloc(queue_id->pool);

  return p;
}

/**
 * @brief Allocate a memory block from a mail and set memory block to zero
 * @param  queue_id      mail queue ID obtained with \ref osMailCreate.
 * @param  millisec      timeout value or 0 in case of no time-out.
 * @retval pointer to memory block that can be filled with mail or NULL in case error.
 * @note   MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
 */
void *osMailCAlloc(osMailQId queue_id, uint32_t millisec) {
  uint32_t i;
  void    *p = osMailAlloc(queue_id, millisec);

  if (p) {
    for (i = 0; i < queue_id->queue_def->item_sz; i++) {
      ((uint8_t *)p)[i] = 0;
    }
  }

  return p;
}

/**
 * @brief Put a mail to a queue
 * @param  queue_id      mail queue ID obtained with \ref osMailCreate.
 * @param  mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
 * @retval status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
 */
osStatus osMailPut(osMailQId queue_id, void *mail) {
  portBASE_TYPE taskWoken;

  if (queue_id == NULL) {
    return osErrorParameter;
  }

  taskWoken = pdFALSE;

  if (inHandlerMode()) {
    if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) {
      return osErrorOS;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) {
      return osErrorOS;
    }
  }

  return osOK;
}

/**
 * @brief Get a mail from a queue
 * @param  queue_id   mail queue ID obtained with \ref osMailCreate.
 * @param millisec    timeout value or 0 in case of no time-out
 * @retval event that contains mail information or error code.
 * @note   MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
 */
osEvent osMailGet(osMailQId queue_id, uint32_t millisec) {
  portBASE_TYPE taskWoken;
  TickType_t    ticks;
  osEvent       event;

  event.def.mail_id = queue_id;

  if (queue_id == NULL) {
    event.status = osErrorParameter;
    return event;
  }

  taskWoken = pdFALSE;

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (inHandlerMode()) {
    if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) {
      /* We have mail */
      event.status = osEventMail;
    } else {
      event.status = osOK;
    }
    portEND_SWITCHING_ISR(taskWoken);
  } else {
    if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) {
      /* We have mail */
      event.status = osEventMail;
    } else {
      event.status = (ticks == 0) ? osOK : osEventTimeout;
    }
  }

  return event;
}

/**
 * @brief Free a memory block from a mail
 * @param  queue_id mail queue ID obtained with \ref osMailCreate.
 * @param  mail     pointer to the memory block that was obtained with \ref osMailGet.
 * @retval status code that indicates the execution status of the function.
 * @note   MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
 */
osStatus osMailFree(osMailQId queue_id, void *mail) {
  if (queue_id == NULL) {
    return osErrorParameter;
  }

  return osPoolFree(queue_id->pool, mail);
}
#endif /* Use Mail Queues */

/*************************** Additional specific APIs to Free RTOS ************/
/**
 * @brief  Handles the tick increment
 * @param  none.
 * @retval none.
 */
void osSystickHandler(void) {

#if (INCLUDE_xTaskGetSchedulerState == 1)
  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
#endif /* INCLUDE_xTaskGetSchedulerState */
    xPortSysTickHandler();
#if (INCLUDE_xTaskGetSchedulerState == 1)
  }
#endif /* INCLUDE_xTaskGetSchedulerState */
}

#if (INCLUDE_eTaskGetState == 1)
/**
 * @brief  Obtain the state of any thread.
 * @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.
 */
osThreadState osThreadGetState(osThreadId thread_id) {
  eTaskState    ThreadState;
  osThreadState result;

  ThreadState = eTaskGetState(thread_id);

  switch (ThreadState) {
  case eRunning:
    result = osThreadRunning;
    break;
  case eReady:
    result = osThreadReady;
    break;
  case eBlocked:
    result = osThreadBlocked;
    break;
  case eSuspended:
    result = osThreadSuspended;
    break;
  case eDeleted:
    result = osThreadDeleted;
    break;
  default:
    result = osThreadError;
  }

  return result;
}
#endif /* INCLUDE_eTaskGetState */

#if (INCLUDE_eTaskGetState == 1)
/**
 * @brief Check if a thread is already suspended or not.
 * @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval status code that indicates the execution status of the function.
 */
osStatus osThreadIsSuspended(osThreadId thread_id) {
  if (eTaskGetState(thread_id) == eSuspended)
    return osOK;
  else
    return osErrorOS;
}
#endif /* INCLUDE_eTaskGetState */
/**
 * @brief  Suspend execution of a thread.
 * @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osThreadSuspend(osThreadId thread_id) {
#if (INCLUDE_vTaskSuspend == 1)
  vTaskSuspend(thread_id);

  return osOK;
#else
  return osErrorResource;
#endif
}

/**
 * @brief  Resume execution of a suspended thread.
 * @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osThreadResume(osThreadId thread_id) {
#if (INCLUDE_vTaskSuspend == 1)
  if (inHandlerMode()) {
    if (xTaskResumeFromISR(thread_id) == pdTRUE) {
      portYIELD_FROM_ISR(pdTRUE);
    }
  } else {
    vTaskResume(thread_id);
  }
  return osOK;
#else
  return osErrorResource;
#endif
}

/**
 * @brief  Suspend execution of a all active threads.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osThreadSuspendAll(void) {
  vTaskSuspendAll();

  return osOK;
}

/**
 * @brief  Resume execution of a all suspended threads.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osThreadResumeAll(void) {
  if (xTaskResumeAll() == pdTRUE)
    return osOK;
  else
    return osErrorOS;
}

/**
 * @brief  Delay a task until a specified time
 * @param   PreviousWakeTime   Pointer to a variable that holds the time at which the
 *          task was last unblocked. PreviousWakeTime must be initialised with the current time
 *          prior to its first use (PreviousWakeTime = osKernelSysTick() )
 * @param   millisec    time delay value
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osDelayUntil(uint32_t *PreviousWakeTime, uint32_t millisec) {
#if INCLUDE_vTaskDelayUntil
  TickType_t ticks = (millisec / portTICK_PERIOD_MS);
  vTaskDelayUntil((TickType_t *)PreviousWakeTime, ticks ? ticks : 1);

  return osOK;
#else
  (void)millisec;
  (void)PreviousWakeTime;

  return osErrorResource;
#endif
}

/**
 * @brief   Abort the delay for a specific thread
 * @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osAbortDelay(osThreadId thread_id) {
#if INCLUDE_xTaskAbortDelay

  xTaskAbortDelay(thread_id);

  return osOK;
#else
  (void)thread_id;

  return osErrorResource;
#endif
}

/**
 * @brief   Lists all the current threads, along with their current state
 *          and stack usage high water mark.
 * @param   buffer   A buffer into which the above mentioned details
 *          will be written
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osThreadList(uint8_t *buffer) {
#if ((configUSE_TRACE_FACILITY == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS == 1))
  vTaskList((char *)buffer);
#endif
  return osOK;
}

/**
 * @brief  Receive an item from a queue without removing the item from the queue.
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @param  millisec  timeout value or 0 in case of no time-out.
 * @retval event information that includes status code.
 */
osEvent osMessagePeek(osMessageQId queue_id, uint32_t millisec) {
  TickType_t ticks;
  osEvent    event;

  event.def.message_id = queue_id;

  if (queue_id == NULL) {
    event.status = osErrorParameter;
    return event;
  }

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) {
    /* We have mail */
    event.status = osEventMessage;
  } else {
    event.status = (ticks == 0) ? osOK : osEventTimeout;
  }

  return event;
}

/**
 * @brief  Get the number of messaged stored in a queue.
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @retval number of messages stored in a queue.
 */
uint32_t osMessageWaiting(osMessageQId queue_id) {
  if (inHandlerMode()) {
    return uxQueueMessagesWaitingFromISR(queue_id);
  } else {
    return uxQueueMessagesWaiting(queue_id);
  }
}

/**
 * @brief  Get the available space in a message queue.
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @retval available space in a message queue.
 */
uint32_t osMessageAvailableSpace(osMessageQId queue_id) { return uxQueueSpacesAvailable(queue_id); }

/**
 * @brief Delete a Message Queue
 * @param  queue_id  message queue ID obtained with \ref osMessageCreate.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osMessageDelete(osMessageQId queue_id) {
  if (inHandlerMode()) {
    return osErrorISR;
  }

  vQueueDelete(queue_id);

  return osOK;
}

/**
 * @brief  Create and Initialize a Recursive Mutex
 * @param  mutex_def     mutex definition referenced with \ref osMutex.
 * @retval  mutex ID for reference by other functions or NULL in case of error..
 */
osMutexId osRecursiveMutexCreate(const osMutexDef_t *mutex_def) {
#if (configUSE_RECURSIVE_MUTEXES == 1)
#if (configSUPPORT_STATIC_ALLOCATION == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)

  if (mutex_def->controlblock != NULL) {
    return xSemaphoreCreateRecursiveMutexStatic(mutex_def->controlblock);
  } else {
    return xSemaphoreCreateRecursiveMutex();
  }
#elif (configSUPPORT_STATIC_ALLOCATION == 1)
  return xSemaphoreCreateRecursiveMutexStatic(mutex_def->controlblock);
#else
  return xSemaphoreCreateRecursiveMutex();
#endif
#else
  return NULL;
#endif
}

/**
 * @brief  Release a Recursive Mutex
 * @param   mutex_id      mutex ID obtained by \ref osRecursiveMutexCreate.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osRecursiveMutexRelease(osMutexId mutex_id) {
#if (configUSE_RECURSIVE_MUTEXES == 1)
  osStatus result = osOK;

  if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) {
    result = osErrorOS;
  }
  return result;
#else
  return osErrorResource;
#endif
}

/**
 * @brief  Release a Recursive Mutex
 * @param   mutex_id    mutex ID obtained by \ref osRecursiveMutexCreate.
 * @param millisec      timeout value or 0 in case of no time-out.
 * @retval  status code that indicates the execution status of the function.
 */
osStatus osRecursiveMutexWait(osMutexId mutex_id, uint32_t millisec) {
#if (configUSE_RECURSIVE_MUTEXES == 1)
  TickType_t ticks;

  if (mutex_id == NULL) {
    return osErrorParameter;
  }

  ticks = 0;
  if (millisec == osWaitForever) {
    ticks = portMAX_DELAY;
  } else if (millisec != 0) {
    ticks = millisec / portTICK_PERIOD_MS;
    if (ticks == 0) {
      ticks = 1;
    }
  }

  if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) {
    return osErrorOS;
  }
  return osOK;
#else
  return osErrorResource;
#endif
}

/**
 * @brief  Returns the current count value of a counting semaphore
 * @param  semaphore_id  semaphore_id ID obtained by \ref osSemaphoreCreate.
 * @retval  count value
 */
uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id) { return uxSemaphoreGetCount(semaphore_id); }


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h
================================================
/* ----------------------------------------------------------------------
 * $Date:        5. February 2013
 * $Revision:    V1.02
 *
 * Project:      CMSIS-RTOS API
 * Title:        cmsis_os.h header file
 *
 * Version 0.02
 *    Initial Proposal Phase
 * Version 0.03
 *    osKernelStart added, optional feature: main started as thread
 *    osSemaphores have standard behavior
 *    osTimerCreate does not start the timer, added osTimerStart
 *    osThreadPass is renamed to osThreadYield
 * Version 1.01
 *    Support for C++ interface
 *     - const attribute removed from the osXxxxDef_t typedef's
 *     - const attribute added to the osXxxxDef macros
 *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
 *    Added: osKernelInitialize
 * Version 1.02
 *    Control functions for short timeouts in microsecond resolution:
 *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
 *    Removed: osSignalGet 
 *    
 *  
 *----------------------------------------------------------------------------
 *
 * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved.
 * Portions Copyright (c) 2013 ARM LIMITED
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  - Neither the name of ARM  nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/

 /**
  ******************************************************************************
  * @file    cmsis_os.h
  * @author  MCD Application Team
  * @date    03-March-2017
  * @brief   Header of cmsis_os.c
  *          A new set of APIs are added in addition to existing ones, these APIs 
  *          are specific to FreeRTOS.
  ******************************************************************************
  * @attention
  *
  * Redistribution and use in source and binary forms, with or without 
  * modification, are permitted, provided that the following conditions are met:
  *
  * 1. Redistribution of source code must retain the above copyright notice, 
  *    this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright notice,
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. Neither the name of STMicroelectronics nor the names of other 
  *    contributors to this software may be used to endorse or promote products 
  *    derived from this software without specific written permission.
  * 4. This software, including modifications and/or derivative works of this 
  *    software, must execute solely and exclusively on microcontroller or
  *    microprocessor devices manufactured by or for STMicroelectronics.
  * 5. Redistribution and use of this software other than as permitted under 
  *    this license is void and will automatically terminate your rights under 
  *    this license. 
  *
  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
	
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "queue.h"
#include "semphr.h"
#include "event_groups.h"

/**
\page cmsis_os_h Header File Template: cmsis_os.h

The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
its implementation.

The file cmsis_os.h contains:
 - CMSIS-RTOS API function definitions
 - struct definitions for parameters and return types
 - status and priority values used by CMSIS-RTOS API functions
 - macros for defining threads and other kernel objects


Name conventions and header file modifications

All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.

Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation.
These definitions can be specific to the underlying RTOS kernel.

Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.


Function calls from interrupt service routines

The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
  - \ref osSignalSet
  - \ref osSemaphoreRelease
  - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
  - \ref osMessagePut, \ref osMessageGet
  - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree

Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.

Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.


Define and reference object definitions

With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file
that is used throughout a project as shown below:

Header File
\code
#include                                          // CMSIS RTOS header file

// Thread definition
extern void thread_sample (void const *argument);             // function prototype
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);

// Pool definition
osPoolDef(MyPool, 10, long);
\endcode


This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is
present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
used throughout the whole project.

Example
\code
#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
\endcode

\code
#define osObjectExternal   // Objects will be defined as external symbols
#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
\endcode

*/

#ifndef _CMSIS_OS_H
#define _CMSIS_OS_H

/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])

/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])

/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string

/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore    1      ///< osFeature_Semaphore function: 1=available, 0=not available
#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available
#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available

#ifdef  __cplusplus
extern "C"
{
#endif


// ==== Enumeration, structures, defines ====

/// Priority used for thread control.
/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
typedef enum  {
  osPriorityIdle          = -3,          ///< priority: idle (lowest)
  osPriorityLow           = -2,          ///< priority: low
  osPriorityBelowNormal   = -1,          ///< priority: below normal
  osPriorityNormal        =  0,          ///< priority: normal (default)
  osPriorityAboveNormal   = +1,          ///< priority: above normal
  osPriorityHigh          = +2,          ///< priority: high
  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
} osPriority;

/// Timeout value.
/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value

/// Status code values returned by CMSIS-RTOS functions.
/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
typedef enum  {
  osOK                    =     0,       ///< function completed; no error or event occurred.
  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
  osEventMessage          =  0x10,       ///< function completed; message event occurred.
  osEventMail             =  0x20,       ///< function completed; mail event occurred.
  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
} osStatus;

#if ( INCLUDE_eTaskGetState == 1 )
/* Thread state returned by osThreadGetState */
typedef enum {
	osThreadRunning   = 0x0,	      /* A thread is querying the state of itself, so must be running. */
	osThreadReady     = 0x1 ,			        /* The thread being queried is in a read or pending ready list. */
	osThreadBlocked   = 0x2,		        /* The thread being queried is in the Blocked state. */
	osThreadSuspended = 0x3,	      /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
	osThreadDeleted   = 0x4,		          /* The thread being queried has been deleted, but its TCB has not yet been freed. */   
  osThreadError     = 0x7FFFFFFF
} osThreadState;
#endif /* INCLUDE_eTaskGetState */

/// Timer type value for the timer definition.
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
typedef enum  {
  osTimerOnce             =     0,       ///< one-shot timer
  osTimerPeriodic         =     1        ///< repeating timer
} os_timer_type;

/// Entry point of a thread.
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
typedef void (*os_pthread) (void const *argument);

/// Entry point of a timer call back function.
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
typedef void (*os_ptimer) (void const *argument);

// >>> the following data type definitions may shall adapted towards a specific RTOS

/// Thread ID identifies the thread (pointer to a thread control block).
/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
typedef TaskHandle_t osThreadId;

/// Timer ID identifies the timer (pointer to a timer control block).
/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
typedef TimerHandle_t osTimerId;

/// Mutex ID identifies the mutex (pointer to a mutex control block).
/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
typedef SemaphoreHandle_t osMutexId;

/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
typedef SemaphoreHandle_t osSemaphoreId;

/// Pool ID identifies the memory pool (pointer to a memory pool control block).
/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_cb *osPoolId;

/// Message ID identifies the message queue (pointer to a message queue control block).
/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
typedef QueueHandle_t osMessageQId;

/// Mail ID identifies the mail queue (pointer to a mail queue control block).
/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_cb *osMailQId;


#if( configSUPPORT_STATIC_ALLOCATION == 1 )

typedef StaticTask_t               osStaticThreadDef_t;
typedef StaticTimer_t              osStaticTimerDef_t;
typedef StaticSemaphore_t          osStaticMutexDef_t;         
typedef StaticSemaphore_t          osStaticSemaphoreDef_t;
typedef StaticQueue_t              osStaticMessageQDef_t;

#endif




/// Thread Definition structure contains startup information of a thread.
/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
typedef struct os_thread_def  {
  char                   *name;        ///< Thread name 
  os_pthread             pthread;      ///< start address of thread function
  osPriority             tpriority;    ///< initial thread priority
  uint32_t               instances;    ///< maximum number of instances of that thread function
  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
  uint32_t               *buffer;      ///< stack buffer for static allocation; NULL for dynamic allocation
  osStaticThreadDef_t    *controlblock;     ///< control block to hold thread's data for static allocation; NULL for dynamic allocation
#endif
} osThreadDef_t;

/// Timer Definition structure contains timer parameters.
/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
typedef struct os_timer_def  {
  os_ptimer                 ptimer;    ///< start address of a timer function
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
  osStaticTimerDef_t        *controlblock;      ///< control block to hold timer's data for static allocation; NULL for dynamic allocation
#endif
} osTimerDef_t;

/// Mutex Definition structure contains setup information for a mutex.
/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mutex_def  {
  uint32_t                   dummy;    ///< dummy value.
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
  osStaticMutexDef_t         *controlblock;      ///< control block for static allocation; NULL for dynamic allocation
#endif
} osMutexDef_t;

/// Semaphore Definition structure contains setup information for a semaphore.
/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
typedef struct os_semaphore_def  {
  uint32_t                   dummy;    ///< dummy value.
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
  osStaticSemaphoreDef_t     *controlblock;      ///< control block for static allocation; NULL for dynamic allocation
#endif
} osSemaphoreDef_t;

/// Definition structure for memory block allocation.
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_def  {
  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
  uint32_t                 item_sz;    ///< size of an item
  void                       *pool;    ///< pointer to memory for pool
} osPoolDef_t;

/// Definition structure for message queue.
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_messageQ_def  {
  uint32_t                queue_sz;    ///< number of elements in the queue
  uint32_t                item_sz;    ///< size of an item
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
  uint8_t                 *buffer;      ///< buffer for static allocation; NULL for dynamic allocation
  osStaticMessageQDef_t   *controlblock;     ///< control block to hold queue's data for static allocation; NULL for dynamic allocation
#endif
  //void                       *pool;    ///< memory array for messages
} osMessageQDef_t;

/// Definition structure for mail queue.
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_def  {
  uint32_t                queue_sz;    ///< number of elements in the queue
  uint32_t                 item_sz;    ///< size of an item
  struct os_mailQ_cb **cb;
} osMailQDef_t;

/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
///       However the struct may be extended at the end.
typedef struct  {
  osStatus                 status;     ///< status code: event or error information
  union  {
    uint32_t                    v;     ///< message as 32-bit value
    void                       *p;     ///< message or mail as void pointer
    int32_t               signals;     ///< signal flags
  } value;                             ///< event value
  union  {
    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
  } def;                               ///< event definition
} osEvent;


//  ==== Kernel Control Functions ====

/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
osStatus osKernelInitialize (void);

/// Start the RTOS Kernel.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
osStatus osKernelStart (void);

/// Check if the RTOS kernel is already started.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \return 0 RTOS is not started, 1 RTOS is started.
int32_t osKernelRunning(void);

#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available

/// Get the RTOS kernel system timer counter 
/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
/// \return RTOS kernel system timer as 32-bit value 
uint32_t osKernelSysTick (void);

/// The RTOS kernel system timer frequency in Hz
/// \note Reflects the system timer setting and is typically defined in a configuration file.
#define osKernelSysTickFrequency      (configTICK_RATE_HZ)

/// Convert a microseconds value to a RTOS kernel system timer value.
/// \param         microsec     time value in microseconds.
/// \return time value normalized to the \ref osKernelSysTickFrequency
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)

#endif    // System Timer available

//  ==== Thread Management ====

/// Create a Thread Definition with function, priority, and stack requirements.
/// \param         name         name of the thread function.
/// \param         priority     initial priority of the thread function.
/// \param         instances    number of possible thread instances.
/// \param         stacksz      stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osThreadDef(name, thread, priority, instances, stacksz)  \
extern const osThreadDef_t os_thread_def_##name
#else                            // define the object

#if( configSUPPORT_STATIC_ALLOCATION == 1 )
#define osThreadDef(name, thread, priority, instances, stacksz)  \
const osThreadDef_t os_thread_def_##name = \
{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL }

#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control)  \
const osThreadDef_t os_thread_def_##name = \
{(char*) #name, (thread), (priority), (instances), (stacksz), (buffer), (control) }
#else //configSUPPORT_STATIC_ALLOCATION == 0

#define osThreadDef(name, thread, priority, instances, stacksz)  \
const osThreadDef_t os_thread_def_##name = \
{ #name, (thread), (priority), (instances), (stacksz)}
#endif
#endif

/// Access a Thread definition.
/// \param         name          name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name)  \
&os_thread_def_##name

/// Create a thread and add it to Active Threads and set it to state READY.
/// \param[in]     thread_def    thread definition referenced with \ref osThread.
/// \param[in]     argument      pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);

/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
osThreadId osThreadGetId (void);

/// Terminate execution of a thread and remove it from Active Threads.
/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
osStatus osThreadTerminate (osThreadId thread_id);

/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
osStatus osThreadYield (void);

/// Change priority of an active thread.
/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in]     priority      new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);

/// Get current priority of an active thread.
/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the thread function.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
osPriority osThreadGetPriority (osThreadId thread_id);


//  ==== Generic Wait Functions ====

/// Wait for Timeout (Time Delay).
/// \param[in]     millisec      time delay value
/// \return status code that indicates the execution status of the function.
osStatus osDelay (uint32_t millisec);

#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available

/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec          timeout value or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
osEvent osWait (uint32_t millisec);

#endif  // Generic Wait available


//  ==== Timer Management Functions ====
/// Define a Timer object.
/// \param         name          name of the timer object.
/// \param         function      name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osTimerDef(name, function)  \
extern const osTimerDef_t os_timer_def_##name
#else                            // define the object

#if( configSUPPORT_STATIC_ALLOCATION == 1 ) 
#define osTimerDef(name, function)  \
const osTimerDef_t os_timer_def_##name = \
{ (function), NULL }

#define osTimerStaticDef(name, function, control)  \
const osTimerDef_t os_timer_def_##name = \
{ (function), (control) }
#else //configSUPPORT_STATIC_ALLOCATION == 0
#define osTimerDef(name, function)  \
const osTimerDef_t os_timer_def_##name = \
{ (function) }
#endif
#endif

/// Access a Timer definition.
/// \param         name          name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name

/// Create a timer.
/// \param[in]     timer_def     timer object referenced with \ref osTimer.
/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in]     argument      argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);

/// Start or restart a timer.
/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
/// \param[in]     millisec      time delay value of the timer.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);

/// Stop the timer.
/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
osStatus osTimerStop (osTimerId timer_id);

/// Delete a timer that was created by \ref osTimerCreate.
/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
osStatus osTimerDelete (osTimerId timer_id);


//  ==== Signal Management ====

/// Set the specified Signal Flags of an active thread.
/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in]     signals       specifies the signal flags of the thread that should be set.
/// \return osOK if successful, osErrorOS if failed.
/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);

/// Clear the specified Signal Flags of an active thread.
/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);

/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in]     millisec      timeout value or 0 in case of no time-out.
/// \return event flag information or error code.
/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
osEvent osSignalWait (int32_t signals, uint32_t millisec);


//  ==== Mutex Management ====

/// Define a Mutex.
/// \param         name          name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osMutexDef(name)  \
extern const osMutexDef_t os_mutex_def_##name
#else                            // define the object

#if( configSUPPORT_STATIC_ALLOCATION == 1 )
#define osMutexDef(name)  \
const osMutexDef_t os_mutex_def_##name = { 0, NULL }

#define osMutexStaticDef(name, control)  \
const osMutexDef_t os_mutex_def_##name = { 0, (control) }
#else //configSUPPORT_STATIC_ALLOCATION == 0
#define osMutexDef(name)  \
const osMutexDef_t os_mutex_def_##name = { 0 }

#endif

#endif

/// Access a Mutex definition.
/// \param         name          name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name)  \
&os_mutex_def_##name

/// Create and Initialize a Mutex object.
/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);

/// Wait until a Mutex becomes available.
/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);

/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
osStatus osMutexRelease (osMutexId mutex_id);

/// Delete a Mutex that was created by \ref osMutexCreate.
/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
osStatus osMutexDelete (osMutexId mutex_id);


//  ==== Semaphore Management Functions ====

#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available

/// Define a Semaphore object.
/// \param         name          name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osSemaphoreDef(name)  \
extern const osSemaphoreDef_t os_semaphore_def_##name
#else                            // define the object

#if( configSUPPORT_STATIC_ALLOCATION == 1 )
#define osSemaphoreDef(name)  \
const osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL }

#define osSemaphoreStaticDef(name, control)  \
const osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) }

#else //configSUPPORT_STATIC_ALLOCATION == 0
#define osSemaphoreDef(name)  \
const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
#endif
#endif

/// Access a Semaphore definition.
/// \param         name          name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name)  \
&os_semaphore_def_##name

/// Create and Initialize a Semaphore object used for managing resources.
/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in]     count         number of available resources.
/// \return semaphore ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);

/// Wait until a Semaphore token becomes available.
/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);

/// Release a Semaphore token.
/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);

/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);

#endif     // Semaphore available


//  ==== Memory Pool Management Functions ====

#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available

/// \brief Define a Memory Pool.
/// \param         name          name of the memory pool.
/// \param         no            maximum number of blocks (objects) in the memory pool.
/// \param         type          data type of a single block (object).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osPoolDef(name, no, type)   \
extern const osPoolDef_t os_pool_def_##name
#else                            // define the object
#define osPoolDef(name, no, type)   \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), NULL }
#endif

/// \brief Access a Memory Pool definition.
/// \param         name          name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name

/// Create and Initialize a memory pool.
/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);

/// Allocate a memory block from a memory pool.
/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolAlloc (osPoolId pool_id);

/// Allocate a memory block from a memory pool and set memory block to zero.
/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolCAlloc (osPoolId pool_id);

/// Return an allocated memory block back to a specific memory pool.
/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
osStatus osPoolFree (osPoolId pool_id, void *block);

#endif   // Memory Pool Management available


//  ==== Message Queue Management Functions ====

#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available

/// \brief Create a Message Queue Definition.
/// \param         name          name of the queue.
/// \param         queue_sz      maximum number of messages in the queue.
/// \param         type          data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osMessageQDef(name, queue_sz, type)   \
extern const osMessageQDef_t os_messageQ_def_##name
#else                            // define the object
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
#define osMessageQDef(name, queue_sz, type)   \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), sizeof (type), NULL, NULL  }

#define osMessageQStaticDef(name, queue_sz, type, buffer, control)   \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), sizeof (type) , (buffer), (control)}
#else //configSUPPORT_STATIC_ALLOCATION == 1
#define osMessageQDef(name, queue_sz, type)   \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), sizeof (type) }

#endif
#endif

/// \brief Access a Message Queue Definition.
/// \param         name          name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name

/// Create and Initialize a Message Queue.
/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);

/// Put a Message to a Queue.
/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
/// \param[in]     info          message information.
/// \param[in]     millisec      timeout value or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);

/// Get a Message or Wait for a Message from a Queue.
/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out.
/// \return event information that includes status code.
/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);

#endif     // Message Queues available


//  ==== Mail Queue Management Functions ====

#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available

/// \brief Create a Mail Queue Definition.
/// \param         name          name of the queue
/// \param         queue_sz      maximum number of messages in queue
/// \param         type          data type of a single message element
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal)  // object is external
#define osMailQDef(name, queue_sz, type) \
extern struct os_mailQ_cb *os_mailQ_cb_##name \
extern osMailQDef_t os_mailQ_def_##name
#else                            // define the object
#define osMailQDef(name, queue_sz, type) \
struct os_mailQ_cb *os_mailQ_cb_##name; \
const osMailQDef_t os_mailQ_def_##name =  \
{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) }
#endif

/// \brief Access a Mail Queue Definition.
/// \param         name          name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
///       macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name)  \
&os_mailQ_def_##name

/// Create and Initialize mail queue.
/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);

/// Allocate a memory block from a mail.
/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);

/// Allocate a memory block from a mail and set memory block to zero.
/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);

/// Put a mail to a queue.
/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
osStatus osMailPut (osMailQId queue_id, void *mail);

/// Get a mail from a queue.
/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
/// \param[in]     millisec      timeout value or 0 in case of no time-out
/// \return event that contains mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
osEvent osMailGet (osMailQId queue_id, uint32_t millisec);

/// Free a memory block from a mail.
/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
osStatus osMailFree (osMailQId queue_id, void *mail);

#endif  // Mail Queues available

/*************************** Additional specific APIs to Free RTOS ************/
/**
* @brief  Handles the tick increment
* @param  none.
* @retval none.
*/
void osSystickHandler(void);

#if ( INCLUDE_eTaskGetState == 1 )
/**
* @brief  Obtain the state of any thread.
* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.
*/
osThreadState osThreadGetState(osThreadId thread_id);
#endif /* INCLUDE_eTaskGetState */

#if ( INCLUDE_eTaskGetState == 1 )
/**
* @brief Check if a thread is already suspended or not.
* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
* @retval status code that indicates the execution status of the function.
*/

osStatus osThreadIsSuspended(osThreadId thread_id);

#endif /* INCLUDE_eTaskGetState */

/**
* @brief  Suspend execution of a thread.
* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osThreadSuspend (osThreadId thread_id);

/**
* @brief  Resume execution of a suspended thread.
* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osThreadResume (osThreadId thread_id);

/**
* @brief  Suspend execution of a all active threads.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osThreadSuspendAll (void);

/**
* @brief  Resume execution of a all suspended threads.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osThreadResumeAll (void);

/**
* @brief  Delay a task until a specified time
* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the 
*          task was last unblocked. PreviousWakeTime must be initialised with the current time
*          prior to its first use (PreviousWakeTime = osKernelSysTick() )
* @param   millisec    time delay value
* @retval  status code that indicates the execution status of the function.
*/
osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec);

/**
* @brief   Abort the delay for a specific thread
* @param   thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId   
* @retval  status code that indicates the execution status of the function.
*/
osStatus osAbortDelay(osThreadId thread_id);

/**
* @brief   Lists all the current threads, along with their current state 
*          and stack usage high water mark.
* @param   buffer   A buffer into which the above mentioned details
*          will be written
* @retval  status code that indicates the execution status of the function.
*/
osStatus osThreadList (uint8_t *buffer);

/**
* @brief  Receive an item from a queue without removing the item from the queue.
* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
* @param  millisec  timeout value or 0 in case of no time-out.
* @retval event information that includes status code.
*/
osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec);

/**
* @brief  Get the number of messaged stored in a queue.
* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
* @retval number of messages stored in a queue.
*/
uint32_t osMessageWaiting(osMessageQId queue_id);

/**
* @brief  Get the available space in a message queue.
* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
* @retval available space in a message queue.
*/
uint32_t osMessageAvailableSpace(osMessageQId queue_id);

/**
* @brief Delete a Message Queue
* @param  queue_id  message queue ID obtained with \ref osMessageCreate.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osMessageDelete (osMessageQId queue_id);

/**
* @brief  Create and Initialize a Recursive Mutex
* @param  mutex_def     mutex definition referenced with \ref osMutex.
* @retval  mutex ID for reference by other functions or NULL in case of error..
*/
osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def);

/**
* @brief  Release a Recursive Mutex
* @param   mutex_id      mutex ID obtained by \ref osRecursiveMutexCreate.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osRecursiveMutexRelease (osMutexId mutex_id);

/**
* @brief  Release a Recursive Mutex
* @param   mutex_id    mutex ID obtained by \ref osRecursiveMutexCreate.
* @param millisec      timeout value or 0 in case of no time-out.
* @retval  status code that indicates the execution status of the function.
*/
osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec);

/**
* @brief  Returns the current count value of a counting semaphore
* @param   semaphore_id  semaphore_id ID obtained by \ref osSemaphoreCreate.
* @retval  count value
*/
uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id);

#ifdef  __cplusplus
}
#endif

#endif  // _CMSIS_OS_H


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#include "FreeRTOS.h"
#include "task.h"
#include "croutine.h"

/* Remove the whole file if co-routines are not being used. */
#if ( configUSE_CO_ROUTINES != 0 )

/*
 * Some kernel aware debuggers require data to be viewed to be global, rather
 * than file scope.
 */
    #ifdef portREMOVE_STATIC_QUALIFIER
        #define static
    #endif


/* Lists for ready and blocked co-routines. --------------------*/
    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */
    static List_t xDelayedCoRoutineList1;                                   /**< Delayed co-routines. */
    static List_t xDelayedCoRoutineList2;                                   /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
    static List_t * pxDelayedCoRoutineList = NULL;                          /**< Points to the delayed co-routine list currently being used. */
    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
    static List_t xPendingReadyCoRoutineList;                               /**< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */

/* Other file private variables. --------------------------------*/
    CRCB_t * pxCurrentCoRoutine = NULL;
    static UBaseType_t uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
    static TickType_t xCoRoutineTickCount = ( TickType_t ) 0U;
    static TickType_t xLastTickCount = ( TickType_t ) 0U;
    static TickType_t xPassedTicks = ( TickType_t ) 0U;

/* The initial state of the co-routine when it is created. */
    #define corINITIAL_STATE    ( 0 )

/*
 * Place the co-routine represented by pxCRCB into the appropriate ready queue
 * for the priority.  It is inserted at the end of the list.
 *
 * This macro accesses the co-routine ready lists and therefore must not be
 * used from within an ISR.
 */
    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                               \
    do {                                                                                                                        \
        if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority )                                                              \
        {                                                                                                                       \
            uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority;                                                               \
        }                                                                                                                       \
        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \
    } while( 0 )

/*
 * Utility to ready all the lists used by the scheduler.  This is called
 * automatically upon the creation of the first co-routine.
 */
    static void prvInitialiseCoRoutineLists( void );

/*
 * Co-routines that are readied by an interrupt cannot be placed directly into
 * the ready lists (there is no mutual exclusion).  Instead they are placed in
 * in the pending ready list in order that they can later be moved to the ready
 * list by the co-routine scheduler.
 */
    static void prvCheckPendingReadyList( void );

/*
 * Macro that looks at the list of co-routines that are currently delayed to
 * see if any require waking.
 *
 * Co-routines are stored in the queue in the order of their wake time -
 * meaning once one co-routine has been found whose timer has not expired
 * we need not look any further down the list.
 */
    static void prvCheckDelayedList( void );

/*-----------------------------------------------------------*/

    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
                                 UBaseType_t uxPriority,
                                 UBaseType_t uxIndex )
    {
        BaseType_t xReturn;
        CRCB_t * pxCoRoutine;

        traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );

        /* Allocate the memory that will store the co-routine control block. */
        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );

        if( pxCoRoutine )
        {
            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
            * be created and the co-routine data structures need initialising. */
            if( pxCurrentCoRoutine == NULL )
            {
                pxCurrentCoRoutine = pxCoRoutine;
                prvInitialiseCoRoutineLists();
            }

            /* Check the priority is within limits. */
            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
            {
                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
            }

            /* Fill out the co-routine control block from the function parameters. */
            pxCoRoutine->uxState = corINITIAL_STATE;
            pxCoRoutine->uxPriority = uxPriority;
            pxCoRoutine->uxIndex = uxIndex;
            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;

            /* Initialise all the other co-routine control block parameters. */
            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );

            /* Set the co-routine control block as a link back from the ListItem_t.
             * This is so we can get back to the containing CRCB from a generic item
             * in a list. */
            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );

            /* Event lists are always in priority order. */
            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );

            /* Now the co-routine has been initialised it can be added to the ready
             * list at the correct priority. */
            prvAddCoRoutineToReadyQueue( pxCoRoutine );

            xReturn = pdPASS;
        }
        else
        {
            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
        }

        traceRETURN_xCoRoutineCreate( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
                                     List_t * pxEventList )
    {
        TickType_t xTimeToWake;

        traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList );

        /* Calculate the time to wake - this may overflow but this is
         * not a problem. */
        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;

        /* We must remove ourselves from the ready list before adding
         * ourselves to the blocked list as the same list item is used for
         * both lists. */
        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );

        /* The list item will be inserted in wake time order. */
        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );

        if( xTimeToWake < xCoRoutineTickCount )
        {
            /* Wake time has overflowed.  Place this item in the
             * overflow list. */
            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
        }
        else
        {
            /* The wake time has not overflowed, so we can use the
             * current block list. */
            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
        }

        if( pxEventList )
        {
            /* Also add the co-routine to an event list.  If this is done then the
             * function must be called with interrupts disabled. */
            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
        }

        traceRETURN_vCoRoutineAddToDelayedList();
    }
/*-----------------------------------------------------------*/

    static void prvCheckPendingReadyList( void )
    {
        /* Are there any co-routines waiting to get moved to the ready list?  These
         * are co-routines that have been readied by an ISR.  The ISR cannot access
         * the ready lists itself. */
        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
        {
            CRCB_t * pxUnblockedCRCB;

            /* The pending ready list can be accessed by an ISR. */
            portDISABLE_INTERRUPTS();
            {
                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
            }
            portENABLE_INTERRUPTS();

            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
        }
    }
/*-----------------------------------------------------------*/

    static void prvCheckDelayedList( void )
    {
        CRCB_t * pxCRCB;

        xPassedTicks = xTaskGetTickCount() - xLastTickCount;

        while( xPassedTicks )
        {
            xCoRoutineTickCount++;
            xPassedTicks--;

            /* If the tick count has overflowed we need to swap the ready lists. */
            if( xCoRoutineTickCount == 0 )
            {
                List_t * pxTemp;

                /* Tick count has overflowed so we need to swap the delay lists.  If there are
                 * any items in pxDelayedCoRoutineList here then there is an error! */
                pxTemp = pxDelayedCoRoutineList;
                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
                pxOverflowDelayedCoRoutineList = pxTemp;
            }

            /* See if this tick has made a timeout expire. */
            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
            {
                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );

                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
                {
                    /* Timeout not yet expired. */
                    break;
                }

                portDISABLE_INTERRUPTS();
                {
                    /* The event could have occurred just before this critical
                     *  section.  If this is the case then the generic list item will
                     *  have been moved to the pending ready list and the following
                     *  line is still valid.  Also the pvContainer parameter will have
                     *  been set to NULL so the following lines are also valid. */
                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );

                    /* Is the co-routine waiting on an event also? */
                    if( pxCRCB->xEventListItem.pxContainer )
                    {
                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
                    }
                }
                portENABLE_INTERRUPTS();

                prvAddCoRoutineToReadyQueue( pxCRCB );
            }
        }

        xLastTickCount = xCoRoutineTickCount;
    }
/*-----------------------------------------------------------*/

    void vCoRoutineSchedule( void )
    {
        traceENTER_vCoRoutineSchedule();

        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
         * called.  prvInitialiseCoRoutineLists() is called automatically when a
         * co-routine is created. */
        if( pxDelayedCoRoutineList != NULL )
        {
            /* See if any co-routines readied by events need moving to the ready lists. */
            prvCheckPendingReadyList();

            /* See if any delayed co-routines have timed out. */
            prvCheckDelayedList();

            /* Find the highest priority queue that contains ready co-routines. */
            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
            {
                if( uxTopCoRoutineReadyPriority == 0 )
                {
                    /* No more co-routines to check. */
                    return;
                }

                --uxTopCoRoutineReadyPriority;
            }

            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
             * of the same priority get an equal share of the processor time. */
            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );

            /* Call the co-routine. */
            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
        }

        traceRETURN_vCoRoutineSchedule();
    }
/*-----------------------------------------------------------*/

    static void prvInitialiseCoRoutineLists( void )
    {
        UBaseType_t uxPriority;

        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
        {
            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
        }

        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );

        /* Start with pxDelayedCoRoutineList using list1 and the
         * pxOverflowDelayedCoRoutineList using list2. */
        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
    }
/*-----------------------------------------------------------*/

    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
    {
        CRCB_t * pxUnblockedCRCB;
        BaseType_t xReturn;

        traceENTER_xCoRoutineRemoveFromEventList( pxEventList );

        /* This function is called from within an interrupt.  It can only access
         * event lists and the pending ready list.  This function assumes that a
         * check has already been made to ensure pxEventList is not empty. */
        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );

        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
        {
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }

        traceRETURN_xCoRoutineRemoveFromEventList( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

/*
 * Reset state in this file. This state is normally initialized at start up.
 * This function must be called by the application before restarting the
 * scheduler.
 */
    void vCoRoutineResetState( void )
    {
        /* Lists for ready and blocked co-routines. */
        pxDelayedCoRoutineList = NULL;
        pxOverflowDelayedCoRoutineList = NULL;

        /* Other file private variables. */
        pxCurrentCoRoutine = NULL;
        uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
        xCoRoutineTickCount = ( TickType_t ) 0U;
        xLastTickCount = ( TickType_t ) 0U;
        xPassedTicks = ( TickType_t ) 0U;
    }
/*-----------------------------------------------------------*/

#endif /* configUSE_CO_ROUTINES == 0 */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/* Standard includes. */
#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers. That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "event_groups.h"

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
 * for the header files above, but not in this file, in order to generate the
 * correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* This entire source file will be skipped if the application is not configured
 * to include event groups functionality. This #if is closed at the very bottom
 * of this file. If you want to include event groups then ensure
 * configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
#if ( configUSE_EVENT_GROUPS == 1 )

    typedef struct EventGroupDef_t
    {
        EventBits_t uxEventBits;
        List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */

        #if ( configUSE_TRACE_FACILITY == 1 )
            UBaseType_t uxEventGroupNumber;
        #endif

        #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
            uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
        #endif
    } EventGroup_t;

/*-----------------------------------------------------------*/

/*
 * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
 * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
 * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
 * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
 * wait condition is met if any of the bits set in uxBitsToWait for are also set
 * in uxCurrentEventBits.
 */
    static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
                                            const EventBits_t uxBitsToWaitFor,
                                            const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;

/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )

        EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
        {
            EventGroup_t * pxEventBits;

            traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer );

            /* A StaticEventGroup_t object must be provided. */
            configASSERT( pxEventGroupBuffer );

            #if ( configASSERT_DEFINED == 1 )
            {
                /* Sanity check that the size of the structure used to declare a
                 * variable of type StaticEventGroup_t equals the size of the real
                 * event group structure. */
                volatile size_t xSize = sizeof( StaticEventGroup_t );
                configASSERT( xSize == sizeof( EventGroup_t ) );
            }
            #endif /* configASSERT_DEFINED */

            /* The user has provided a statically allocated event group - use it. */
            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer;

            if( pxEventBits != NULL )
            {
                pxEventBits->uxEventBits = 0;
                vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );

                #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
                {
                    /* Both static and dynamic allocation can be used, so note that
                     * this event group was created statically in case the event group
                     * is later deleted. */
                    pxEventBits->ucStaticallyAllocated = pdTRUE;
                }
                #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

                traceEVENT_GROUP_CREATE( pxEventBits );
            }
            else
            {
                /* xEventGroupCreateStatic should only ever be called with
                 * pxEventGroupBuffer pointing to a pre-allocated (compile time
                 * allocated) StaticEventGroup_t variable. */
                traceEVENT_GROUP_CREATE_FAILED();
            }

            traceRETURN_xEventGroupCreateStatic( pxEventBits );

            return pxEventBits;
        }

    #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

        EventGroupHandle_t xEventGroupCreate( void )
        {
            EventGroup_t * pxEventBits;

            traceENTER_xEventGroupCreate();

            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );

            if( pxEventBits != NULL )
            {
                pxEventBits->uxEventBits = 0;
                vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );

                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                {
                    /* Both static and dynamic allocation can be used, so note this
                     * event group was allocated statically in case the event group is
                     * later deleted. */
                    pxEventBits->ucStaticallyAllocated = pdFALSE;
                }
                #endif /* configSUPPORT_STATIC_ALLOCATION */

                traceEVENT_GROUP_CREATE( pxEventBits );
            }
            else
            {
                traceEVENT_GROUP_CREATE_FAILED();
            }

            traceRETURN_xEventGroupCreate( pxEventBits );

            return pxEventBits;
        }

    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/

    EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
                                 const EventBits_t uxBitsToSet,
                                 const EventBits_t uxBitsToWaitFor,
                                 TickType_t xTicksToWait )
    {
        EventBits_t uxOriginalBitValue, uxReturn;
        EventGroup_t * pxEventBits = xEventGroup;
        BaseType_t xAlreadyYielded;
        BaseType_t xTimeoutOccurred = pdFALSE;

        traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );

        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
        configASSERT( uxBitsToWaitFor != 0 );
        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
        {
            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
        }
        #endif

        vTaskSuspendAll();
        {
            uxOriginalBitValue = pxEventBits->uxEventBits;

            ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );

            if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
            {
                /* All the rendezvous bits are now set - no need to block. */
                uxReturn = ( uxOriginalBitValue | uxBitsToSet );

                /* Rendezvous always clear the bits.  They will have been cleared
                 * already unless this is the only task in the rendezvous. */
                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;

                xTicksToWait = 0;
            }
            else
            {
                if( xTicksToWait != ( TickType_t ) 0 )
                {
                    traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );

                    /* Store the bits that the calling task is waiting for in the
                     * task's event list item so the kernel knows when a match is
                     * found.  Then enter the blocked state. */
                    vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );

                    /* This assignment is obsolete as uxReturn will get set after
                     * the task unblocks, but some compilers mistakenly generate a
                     * warning about uxReturn being returned without being set if the
                     * assignment is omitted. */
                    uxReturn = 0;
                }
                else
                {
                    /* The rendezvous bits were not set, but no block time was
                     * specified - just return the current event bit value. */
                    uxReturn = pxEventBits->uxEventBits;
                    xTimeoutOccurred = pdTRUE;
                }
            }
        }
        xAlreadyYielded = xTaskResumeAll();

        if( xTicksToWait != ( TickType_t ) 0 )
        {
            if( xAlreadyYielded == pdFALSE )
            {
                taskYIELD_WITHIN_API();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* The task blocked to wait for its required bits to be set - at this
             * point either the required bits were set or the block time expired.  If
             * the required bits were set they will have been stored in the task's
             * event list item, and they should now be retrieved then cleared. */
            uxReturn = uxTaskResetEventItemValue();

            if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
            {
                /* The task timed out, just return the current event bit value. */
                taskENTER_CRITICAL();
                {
                    uxReturn = pxEventBits->uxEventBits;

                    /* Although the task got here because it timed out before the
                     * bits it was waiting for were set, it is possible that since it
                     * unblocked another task has set the bits.  If this is the case
                     * then it needs to clear the bits before exiting. */
                    if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
                    {
                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                taskEXIT_CRITICAL();

                xTimeoutOccurred = pdTRUE;
            }
            else
            {
                /* The task unblocked because the bits were set. */
            }

            /* Control bits might be set as the task had blocked should not be
             * returned. */
            uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
        }

        traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );

        /* Prevent compiler warnings when trace macros are not used. */
        ( void ) xTimeoutOccurred;

        traceRETURN_xEventGroupSync( uxReturn );

        return uxReturn;
    }
/*-----------------------------------------------------------*/

    EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                                     const EventBits_t uxBitsToWaitFor,
                                     const BaseType_t xClearOnExit,
                                     const BaseType_t xWaitForAllBits,
                                     TickType_t xTicksToWait )
    {
        EventGroup_t * pxEventBits = xEventGroup;
        EventBits_t uxReturn, uxControlBits = 0;
        BaseType_t xWaitConditionMet, xAlreadyYielded;
        BaseType_t xTimeoutOccurred = pdFALSE;

        traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );

        /* Check the user is not attempting to wait on the bits used by the kernel
         * itself, and that at least one bit is being requested. */
        configASSERT( xEventGroup );
        configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
        configASSERT( uxBitsToWaitFor != 0 );
        #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
        {
            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
        }
        #endif

        vTaskSuspendAll();
        {
            const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;

            /* Check to see if the wait condition is already met or not. */
            xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );

            if( xWaitConditionMet != pdFALSE )
            {
                /* The wait condition has already been met so there is no need to
                 * block. */
                uxReturn = uxCurrentEventBits;
                xTicksToWait = ( TickType_t ) 0;

                /* Clear the wait bits if requested to do so. */
                if( xClearOnExit != pdFALSE )
                {
                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else if( xTicksToWait == ( TickType_t ) 0 )
            {
                /* The wait condition has not been met, but no block time was
                 * specified, so just return the current value. */
                uxReturn = uxCurrentEventBits;
                xTimeoutOccurred = pdTRUE;
            }
            else
            {
                /* The task is going to block to wait for its required bits to be
                 * set.  uxControlBits are used to remember the specified behaviour of
                 * this call to xEventGroupWaitBits() - for use when the event bits
                 * unblock the task. */
                if( xClearOnExit != pdFALSE )
                {
                    uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                if( xWaitForAllBits != pdFALSE )
                {
                    uxControlBits |= eventWAIT_FOR_ALL_BITS;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                /* Store the bits that the calling task is waiting for in the
                 * task's event list item so the kernel knows when a match is
                 * found.  Then enter the blocked state. */
                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );

                /* This is obsolete as it will get set after the task unblocks, but
                 * some compilers mistakenly generate a warning about the variable
                 * being returned without being set if it is not done. */
                uxReturn = 0;

                traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
            }
        }
        xAlreadyYielded = xTaskResumeAll();

        if( xTicksToWait != ( TickType_t ) 0 )
        {
            if( xAlreadyYielded == pdFALSE )
            {
                taskYIELD_WITHIN_API();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* The task blocked to wait for its required bits to be set - at this
             * point either the required bits were set or the block time expired.  If
             * the required bits were set they will have been stored in the task's
             * event list item, and they should now be retrieved then cleared. */
            uxReturn = uxTaskResetEventItemValue();

            if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
            {
                taskENTER_CRITICAL();
                {
                    /* The task timed out, just return the current event bit value. */
                    uxReturn = pxEventBits->uxEventBits;

                    /* It is possible that the event bits were updated between this
                     * task leaving the Blocked state and running again. */
                    if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
                    {
                        if( xClearOnExit != pdFALSE )
                        {
                            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    xTimeoutOccurred = pdTRUE;
                }
                taskEXIT_CRITICAL();
            }
            else
            {
                /* The task unblocked because the bits were set. */
            }

            /* The task blocked so control bits may have been set. */
            uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
        }

        traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );

        /* Prevent compiler warnings when trace macros are not used. */
        ( void ) xTimeoutOccurred;

        traceRETURN_xEventGroupWaitBits( uxReturn );

        return uxReturn;
    }
/*-----------------------------------------------------------*/

    EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                      const EventBits_t uxBitsToClear )
    {
        EventGroup_t * pxEventBits = xEventGroup;
        EventBits_t uxReturn;

        traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear );

        /* Check the user is not attempting to clear the bits used by the kernel
         * itself. */
        configASSERT( xEventGroup );
        configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

        taskENTER_CRITICAL();
        {
            traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );

            /* The value returned is the event group value prior to the bits being
             * cleared. */
            uxReturn = pxEventBits->uxEventBits;

            /* Clear the bits. */
            pxEventBits->uxEventBits &= ~uxBitsToClear;
        }
        taskEXIT_CRITICAL();

        traceRETURN_xEventGroupClearBits( uxReturn );

        return uxReturn;
    }
/*-----------------------------------------------------------*/

    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )

        BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                                const EventBits_t uxBitsToClear )
        {
            BaseType_t xReturn;

            traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear );

            traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
            xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );

            traceRETURN_xEventGroupClearBitsFromISR( xReturn );

            return xReturn;
        }

    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/

    EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
    {
        UBaseType_t uxSavedInterruptStatus;
        EventGroup_t const * const pxEventBits = xEventGroup;
        EventBits_t uxReturn;

        traceENTER_xEventGroupGetBitsFromISR( xEventGroup );

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
        {
            uxReturn = pxEventBits->uxEventBits;
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_xEventGroupGetBitsFromISR( uxReturn );

        return uxReturn;
    }
/*-----------------------------------------------------------*/

    EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
                                    const EventBits_t uxBitsToSet )
    {
        ListItem_t * pxListItem;
        ListItem_t * pxNext;
        ListItem_t const * pxListEnd;
        List_t const * pxList;
        EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
        EventGroup_t * pxEventBits = xEventGroup;
        BaseType_t xMatchFound = pdFALSE;

        traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet );

        /* Check the user is not attempting to set the bits used by the kernel
         * itself. */
        configASSERT( xEventGroup );
        configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );

        pxList = &( pxEventBits->xTasksWaitingForBits );
        pxListEnd = listGET_END_MARKER( pxList );
        vTaskSuspendAll();
        {
            traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );

            pxListItem = listGET_HEAD_ENTRY( pxList );

            /* Set the bits. */
            pxEventBits->uxEventBits |= uxBitsToSet;

            /* See if the new bit value should unblock any tasks. */
            while( pxListItem != pxListEnd )
            {
                pxNext = listGET_NEXT( pxListItem );
                uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
                xMatchFound = pdFALSE;

                /* Split the bits waited for from the control bits. */
                uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
                uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;

                if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
                {
                    /* Just looking for single bit being set. */
                    if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
                    {
                        xMatchFound = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
                {
                    /* All bits are set. */
                    xMatchFound = pdTRUE;
                }
                else
                {
                    /* Need all bits to be set, but not all the bits were set. */
                }

                if( xMatchFound != pdFALSE )
                {
                    /* The bits match.  Should the bits be cleared on exit? */
                    if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
                    {
                        uxBitsToClear |= uxBitsWaitedFor;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* Store the actual event flag value in the task's event list
                     * item before removing the task from the event list.  The
                     * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
                     * that is was unblocked due to its required bits matching, rather
                     * than because it timed out. */
                    vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
                }

                /* Move onto the next list item.  Note pxListItem->pxNext is not
                 * used here as the list item may have been removed from the event list
                 * and inserted into the ready/pending reading list. */
                pxListItem = pxNext;
            }

            /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
             * bit was set in the control word. */
            pxEventBits->uxEventBits &= ~uxBitsToClear;
        }
        ( void ) xTaskResumeAll();

        traceRETURN_xEventGroupSetBits( pxEventBits->uxEventBits );

        return pxEventBits->uxEventBits;
    }
/*-----------------------------------------------------------*/

    void vEventGroupDelete( EventGroupHandle_t xEventGroup )
    {
        EventGroup_t * pxEventBits = xEventGroup;
        const List_t * pxTasksWaitingForBits;

        traceENTER_vEventGroupDelete( xEventGroup );

        configASSERT( pxEventBits );

        pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );

        vTaskSuspendAll();
        {
            traceEVENT_GROUP_DELETE( xEventGroup );

            while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
            {
                /* Unblock the task, returning 0 as the event list is being deleted
                 * and cannot therefore have any bits set. */
                configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
                vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
            }
        }
        ( void ) xTaskResumeAll();

        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
        {
            /* The event group can only have been allocated dynamically - free
             * it again. */
            vPortFree( pxEventBits );
        }
        #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
        {
            /* The event group could have been allocated statically or
             * dynamically, so check before attempting to free the memory. */
            if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
            {
                vPortFree( pxEventBits );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

        traceRETURN_vEventGroupDelete();
    }
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
        BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                               StaticEventGroup_t ** ppxEventGroupBuffer )
        {
            BaseType_t xReturn;
            EventGroup_t * pxEventBits = xEventGroup;

            traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer );

            configASSERT( pxEventBits );
            configASSERT( ppxEventGroupBuffer );

            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
            {
                /* Check if the event group was statically allocated. */
                if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
                {
                    /* MISRA Ref 11.3.1 [Misaligned access] */
                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                    /* coverity[misra_c_2012_rule_11_3_violation] */
                    *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
                    xReturn = pdTRUE;
                }
                else
                {
                    xReturn = pdFALSE;
                }
            }
            #else /* configSUPPORT_DYNAMIC_ALLOCATION */
            {
                /* Event group must have been statically allocated. */
                /* MISRA Ref 11.3.1 [Misaligned access] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                /* coverity[misra_c_2012_rule_11_3_violation] */
                *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits;
                xReturn = pdTRUE;
            }
            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

            traceRETURN_xEventGroupGetStaticBuffer( xReturn );

            return xReturn;
        }
    #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

/* For internal use only - execute a 'set bits' command that was pended from
 * an interrupt. */
    void vEventGroupSetBitsCallback( void * pvEventGroup,
                                     uint32_t ulBitsToSet )
    {
        traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet );

        /* MISRA Ref 11.5.4 [Callback function parameter] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );

        traceRETURN_vEventGroupSetBitsCallback();
    }
/*-----------------------------------------------------------*/

/* For internal use only - execute a 'clear bits' command that was pended from
 * an interrupt. */
    void vEventGroupClearBitsCallback( void * pvEventGroup,
                                       uint32_t ulBitsToClear )
    {
        traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear );

        /* MISRA Ref 11.5.4 [Callback function parameter] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );

        traceRETURN_vEventGroupClearBitsCallback();
    }
/*-----------------------------------------------------------*/

    static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
                                            const EventBits_t uxBitsToWaitFor,
                                            const BaseType_t xWaitForAllBits )
    {
        BaseType_t xWaitConditionMet = pdFALSE;

        if( xWaitForAllBits == pdFALSE )
        {
            /* Task only has to wait for one bit within uxBitsToWaitFor to be
             * set.  Is one already set? */
            if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
            {
                xWaitConditionMet = pdTRUE;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
             * Are they set already? */
            if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
            {
                xWaitConditionMet = pdTRUE;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }

        return xWaitConditionMet;
    }
/*-----------------------------------------------------------*/

    #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )

        BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                              const EventBits_t uxBitsToSet,
                                              BaseType_t * pxHigherPriorityTaskWoken )
        {
            BaseType_t xReturn;

            traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken );

            traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
            xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );

            traceRETURN_xEventGroupSetBitsFromISR( xReturn );

            return xReturn;
        }

    #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

        UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
        {
            UBaseType_t xReturn;

            /* MISRA Ref 11.5.2 [Opaque pointer] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup;

            traceENTER_uxEventGroupGetNumber( xEventGroup );

            if( xEventGroup == NULL )
            {
                xReturn = 0;
            }
            else
            {
                xReturn = pxEventBits->uxEventGroupNumber;
            }

            traceRETURN_uxEventGroupGetNumber( xReturn );

            return xReturn;
        }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

        void vEventGroupSetNumber( void * xEventGroup,
                                   UBaseType_t uxEventGroupNumber )
        {
            traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber );

            /* MISRA Ref 11.5.2 [Opaque pointer] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;

            traceRETURN_vEventGroupSetNumber();
        }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

/* This entire source file will be skipped if the application is not configured
 * to include event groups functionality. If you want to include event groups
 * then ensure configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */
#endif /* configUSE_EVENT_GROUPS == 1 */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef INC_FREERTOS_H
#define INC_FREERTOS_H

/*
 * Include the generic headers required for the FreeRTOS port being used.
 */
#include 

/*
 * If stdint.h cannot be located then:
 *   + If using GCC ensure the -nostdint options is *not* being used.
 *   + Ensure the project's include path includes the directory in which your
 *     compiler stores stdint.h.
 *   + Set any compiler options necessary for it to support C99, as technically
 *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
 *     other way).
 *   + The FreeRTOS download includes a simple stdint.h definition that can be
 *     used in cases where none is provided by the compiler.  The files only
 *     contains the typedefs required to build FreeRTOS.  Read the instructions
 *     in FreeRTOS/source/stdint.readme for more information.
 */
#include  /* READ COMMENT ABOVE. */

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/* Acceptable values for configTICK_TYPE_WIDTH_IN_BITS. */
#define TICK_TYPE_WIDTH_16_BITS    0
#define TICK_TYPE_WIDTH_32_BITS    1
#define TICK_TYPE_WIDTH_64_BITS    2

/* Application specific configuration options. */
#include "FreeRTOSConfig.h"

#if !defined( configUSE_16_BIT_TICKS ) && !defined( configTICK_TYPE_WIDTH_IN_BITS )
    #error Missing definition:  One of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#if defined( configUSE_16_BIT_TICKS ) && defined( configTICK_TYPE_WIDTH_IN_BITS )
    #error Only one of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

/* Define configTICK_TYPE_WIDTH_IN_BITS according to the
 * value of configUSE_16_BIT_TICKS for backward compatibility. */
#ifndef configTICK_TYPE_WIDTH_IN_BITS
    #if ( configUSE_16_BIT_TICKS == 1 )
        #define configTICK_TYPE_WIDTH_IN_BITS    TICK_TYPE_WIDTH_16_BITS
    #else
        #define configTICK_TYPE_WIDTH_IN_BITS    TICK_TYPE_WIDTH_32_BITS
    #endif
#endif

/* Set configUSE_MPU_WRAPPERS_V1 to 1 to use MPU wrappers v1. */
#ifndef configUSE_MPU_WRAPPERS_V1
    #define configUSE_MPU_WRAPPERS_V1    0
#endif

/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to enable access control list support. */
#ifndef configENABLE_ACCESS_CONTROL_LIST
    #define configENABLE_ACCESS_CONTROL_LIST    0
#endif

/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */
#ifndef configNUMBER_OF_CORES
    #define configNUMBER_OF_CORES    1
#endif

#ifndef configUSE_MALLOC_FAILED_HOOK
    #define configUSE_MALLOC_FAILED_HOOK    0
#endif

/* Basic FreeRTOS definitions. */
#include "projdefs.h"

/* Definitions specific to the port being used. */
#include "portable.h"

/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
#ifndef configUSE_NEWLIB_REENTRANT
    #define configUSE_NEWLIB_REENTRANT    0
#endif

/* Required if struct _reent is used. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )

    #include "newlib-freertos.h"

#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */

/* Must be defaulted before configUSE_PICOLIBC_TLS is used below. */
#ifndef configUSE_PICOLIBC_TLS
    #define configUSE_PICOLIBC_TLS    0
#endif

#if ( configUSE_PICOLIBC_TLS == 1 )

    #include "picolibc-freertos.h"

#endif /* if ( configUSE_PICOLIBC_TLS == 1 ) */

#ifndef configUSE_C_RUNTIME_TLS_SUPPORT
    #define configUSE_C_RUNTIME_TLS_SUPPORT    0
#endif

#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )

    #ifndef configTLS_BLOCK_TYPE
        #error Missing definition:  configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
    #endif

    #ifndef configINIT_TLS_BLOCK
        #error Missing definition:  configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
    #endif

    #ifndef configSET_TLS_BLOCK
        #error Missing definition:  configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
    #endif

    #ifndef configDEINIT_TLS_BLOCK
        #error Missing definition:  configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1.
    #endif
#endif /* if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) */

/*
 * Check all the required application specific macros have been defined.
 * These macros are application specific and (as downloaded) are defined
 * within FreeRTOSConfig.h.
 */

#ifndef configMINIMAL_STACK_SIZE
    #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
#endif

#ifndef configMAX_PRIORITIES
    #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#if configMAX_PRIORITIES < 1
    #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
#endif

#ifndef configUSE_PREEMPTION
    #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#ifndef configUSE_IDLE_HOOK
    #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#if ( configNUMBER_OF_CORES > 1 )
    #ifndef configUSE_PASSIVE_IDLE_HOOK
        #error Missing definition:  configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
    #endif
#endif

#ifndef configUSE_TICK_HOOK
    #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#if ( ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_16_BITS ) && \
    ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_32_BITS ) &&   \
    ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_64_BITS ) )
    #error Macro configTICK_TYPE_WIDTH_IN_BITS is defined to incorrect value.  See the Configuration section of the FreeRTOS API documentation for details.
#endif

#ifndef configUSE_CO_ROUTINES
    #define configUSE_CO_ROUTINES    0
#endif

#ifndef INCLUDE_vTaskPrioritySet
    #define INCLUDE_vTaskPrioritySet    0
#endif

#ifndef INCLUDE_uxTaskPriorityGet
    #define INCLUDE_uxTaskPriorityGet    0
#endif

#ifndef INCLUDE_vTaskDelete
    #define INCLUDE_vTaskDelete    0
#endif

#ifndef INCLUDE_vTaskSuspend
    #define INCLUDE_vTaskSuspend    0
#endif

#ifdef INCLUDE_xTaskDelayUntil
    #ifdef INCLUDE_vTaskDelayUntil

/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil.  Backward
 * compatibility is maintained if only one or the other is defined, but
 * there is a conflict if both are defined. */
        #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined.  INCLUDE_vTaskDelayUntil is no longer required and should be removed
    #endif
#endif

#ifndef INCLUDE_xTaskDelayUntil
    #ifdef INCLUDE_vTaskDelayUntil

/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then
 * the project's FreeRTOSConfig.h probably pre-dates the introduction of
 * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever
 * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility.
 */
        #define INCLUDE_xTaskDelayUntil    INCLUDE_vTaskDelayUntil
    #endif
#endif

#ifndef INCLUDE_xTaskDelayUntil
    #define INCLUDE_xTaskDelayUntil    0
#endif

#ifndef INCLUDE_vTaskDelay
    #define INCLUDE_vTaskDelay    0
#endif

#ifndef INCLUDE_xTaskGetIdleTaskHandle
    #define INCLUDE_xTaskGetIdleTaskHandle    0
#endif

#ifndef INCLUDE_xTaskAbortDelay
    #define INCLUDE_xTaskAbortDelay    0
#endif

#ifndef INCLUDE_xQueueGetMutexHolder
    #define INCLUDE_xQueueGetMutexHolder    0
#endif

#ifndef INCLUDE_xSemaphoreGetMutexHolder
    #define INCLUDE_xSemaphoreGetMutexHolder    INCLUDE_xQueueGetMutexHolder
#endif

#ifndef INCLUDE_xTaskGetHandle
    #define INCLUDE_xTaskGetHandle    0
#endif

#ifndef INCLUDE_uxTaskGetStackHighWaterMark
    #define INCLUDE_uxTaskGetStackHighWaterMark    0
#endif

#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
    #define INCLUDE_uxTaskGetStackHighWaterMark2    0
#endif

#ifndef INCLUDE_eTaskGetState
    #define INCLUDE_eTaskGetState    0
#endif

#ifndef INCLUDE_xTaskResumeFromISR
    #define INCLUDE_xTaskResumeFromISR    1
#endif

#ifndef INCLUDE_xTimerPendFunctionCall
    #define INCLUDE_xTimerPendFunctionCall    0
#endif

#ifndef INCLUDE_xTaskGetSchedulerState
    #define INCLUDE_xTaskGetSchedulerState    0
#endif

#ifndef INCLUDE_xTaskGetCurrentTaskHandle
    #define INCLUDE_xTaskGetCurrentTaskHandle    1
#endif

#if configUSE_CO_ROUTINES != 0
    #ifndef configMAX_CO_ROUTINE_PRIORITIES
        #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
    #endif
#endif

#ifndef configUSE_APPLICATION_TASK_TAG
    #define configUSE_APPLICATION_TASK_TAG    0
#endif

#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
    #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
#endif

#ifndef configUSE_RECURSIVE_MUTEXES
    #define configUSE_RECURSIVE_MUTEXES    0
#endif

#ifndef configUSE_MUTEXES
    #define configUSE_MUTEXES    0
#endif

#ifndef configUSE_TIMERS
    #define configUSE_TIMERS    0
#endif

#ifndef configUSE_EVENT_GROUPS
    #define configUSE_EVENT_GROUPS    1
#endif

#ifndef configUSE_STREAM_BUFFERS
    #define configUSE_STREAM_BUFFERS    1
#endif

#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
#endif

#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 )
    #if ( configUSE_TIMERS == 0 )
        #error configUSE_DAEMON_TASK_STARTUP_HOOK is set, but the daemon task is not created because configUSE_TIMERS is 0.
    #endif
#endif

#ifndef configUSE_COUNTING_SEMAPHORES
    #define configUSE_COUNTING_SEMAPHORES    0
#endif

#ifndef configUSE_TASK_PREEMPTION_DISABLE
    #define configUSE_TASK_PREEMPTION_DISABLE    0
#endif

#ifndef configUSE_ALTERNATIVE_API
    #define configUSE_ALTERNATIVE_API    0
#endif

#ifndef portCRITICAL_NESTING_IN_TCB
    #define portCRITICAL_NESTING_IN_TCB    0
#endif

#ifndef configMAX_TASK_NAME_LEN
    #define configMAX_TASK_NAME_LEN    16
#endif

#ifndef configIDLE_SHOULD_YIELD
    #define configIDLE_SHOULD_YIELD    1
#endif

#if configMAX_TASK_NAME_LEN < 1
    #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
#endif

#ifndef configASSERT
    #define configASSERT( x )
    #define configASSERT_DEFINED    0
#else
    #define configASSERT_DEFINED    1
#endif

/* configPRECONDITION should be defined as configASSERT.
 * The CBMC proofs need a way to track assumptions and assertions.
 * A configPRECONDITION statement should express an implicit invariant or
 * assumption made.  A configASSERT statement should express an invariant that must
 * hold explicit before calling the code. */
#ifndef configPRECONDITION
    #define configPRECONDITION( X )    configASSERT( X )
    #define configPRECONDITION_DEFINED    0
#else
    #define configPRECONDITION_DEFINED    1
#endif

#ifndef configCHECK_HANDLER_INSTALLATION
    #define configCHECK_HANDLER_INSTALLATION    1
#else

/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION
 * to 1. The checks requires configASSERT() to be defined. */
    #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) )
        #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1.
    #endif
#endif

#ifndef portMEMORY_BARRIER
    #define portMEMORY_BARRIER()
#endif

#ifndef portSOFTWARE_BARRIER
    #define portSOFTWARE_BARRIER()
#endif

#ifndef configRUN_MULTIPLE_PRIORITIES
    #define configRUN_MULTIPLE_PRIORITIES    0
#endif

#ifndef portGET_CORE_ID

    #if ( configNUMBER_OF_CORES == 1 )
        #define portGET_CORE_ID()    0
    #else
        #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined.
    #endif /* configNUMBER_OF_CORES */

#endif /* portGET_CORE_ID */

#ifndef portYIELD_CORE

    #if ( configNUMBER_OF_CORES == 1 )
        #define portYIELD_CORE( x )    portYIELD()
    #else
        #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined.
    #endif /* configNUMBER_OF_CORES */

#endif /* portYIELD_CORE */

#ifndef portSET_INTERRUPT_MASK

    #if ( configNUMBER_OF_CORES > 1 )
        #error portSET_INTERRUPT_MASK is required in SMP
    #endif

#endif /* portSET_INTERRUPT_MASK */

#ifndef portCLEAR_INTERRUPT_MASK

    #if ( configNUMBER_OF_CORES > 1 )
        #error portCLEAR_INTERRUPT_MASK is required in SMP
    #endif

#endif /* portCLEAR_INTERRUPT_MASK */

#ifndef portRELEASE_TASK_LOCK

    #if ( configNUMBER_OF_CORES == 1 )
        #define portRELEASE_TASK_LOCK()
    #else
        #error portRELEASE_TASK_LOCK is required in SMP
    #endif

#endif /* portRELEASE_TASK_LOCK */

#ifndef portGET_TASK_LOCK

    #if ( configNUMBER_OF_CORES == 1 )
        #define portGET_TASK_LOCK()
    #else
        #error portGET_TASK_LOCK is required in SMP
    #endif

#endif /* portGET_TASK_LOCK */

#ifndef portRELEASE_ISR_LOCK

    #if ( configNUMBER_OF_CORES == 1 )
        #define portRELEASE_ISR_LOCK()
    #else
        #error portRELEASE_ISR_LOCK is required in SMP
    #endif

#endif /* portRELEASE_ISR_LOCK */

#ifndef portGET_ISR_LOCK

    #if ( configNUMBER_OF_CORES == 1 )
        #define portGET_ISR_LOCK()
    #else
        #error portGET_ISR_LOCK is required in SMP
    #endif

#endif /* portGET_ISR_LOCK */

#ifndef portENTER_CRITICAL_FROM_ISR

    #if ( configNUMBER_OF_CORES > 1 )
        #error portENTER_CRITICAL_FROM_ISR is required in SMP
    #endif

#endif

#ifndef portEXIT_CRITICAL_FROM_ISR

    #if ( configNUMBER_OF_CORES > 1 )
        #error portEXIT_CRITICAL_FROM_ISR is required in SMP
    #endif

#endif

#ifndef configUSE_CORE_AFFINITY
    #define configUSE_CORE_AFFINITY    0
#endif /* configUSE_CORE_AFFINITY */

#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    #ifndef configTASK_DEFAULT_CORE_AFFINITY
        #define configTASK_DEFAULT_CORE_AFFINITY    tskNO_AFFINITY
    #endif
#endif

#ifndef configUSE_PASSIVE_IDLE_HOOK
    #define configUSE_PASSIVE_IDLE_HOOK    0
#endif /* configUSE_PASSIVE_IDLE_HOOK */

/* The timers module relies on xTaskGetSchedulerState(). */
#if configUSE_TIMERS == 1

    #ifndef configTIMER_TASK_PRIORITY
        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
    #endif /* configTIMER_TASK_PRIORITY */

    #ifndef configTIMER_QUEUE_LENGTH
        #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
    #endif /* configTIMER_QUEUE_LENGTH */

    #ifndef configTIMER_TASK_STACK_DEPTH
        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
    #endif /* configTIMER_TASK_STACK_DEPTH */

    #ifndef portTIMER_CALLBACK_ATTRIBUTE
        #define portTIMER_CALLBACK_ATTRIBUTE
    #endif /* portTIMER_CALLBACK_ATTRIBUTE */

#endif /* configUSE_TIMERS */

#ifndef portHAS_NESTED_INTERRUPTS
    #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) && defined( portCLEAR_INTERRUPT_MASK_FROM_ISR )
        #define portHAS_NESTED_INTERRUPTS    1
    #else
        #define portHAS_NESTED_INTERRUPTS    0
    #endif
#endif

#ifndef portSET_INTERRUPT_MASK_FROM_ISR
    #if ( portHAS_NESTED_INTERRUPTS == 1 )
        #error portSET_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
    #else
        #define portSET_INTERRUPT_MASK_FROM_ISR()    0
    #endif
#else
    #if ( portHAS_NESTED_INTERRUPTS == 0 )
        #error portSET_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
    #endif
#endif

#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
    #if ( portHAS_NESTED_INTERRUPTS == 1 )
        #error portCLEAR_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts  (i.e. portHAS_NESTED_INTERRUPTS is set to 1)
    #else
        #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) ( uxSavedStatusValue )
    #endif
#else
    #if ( portHAS_NESTED_INTERRUPTS == 0 )
        #error portCLEAR_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
    #endif
#endif

#ifndef portCLEAN_UP_TCB
    #define portCLEAN_UP_TCB( pxTCB )    ( void ) ( pxTCB )
#endif

#ifndef portPRE_TASK_DELETE_HOOK
    #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
#endif

#ifndef portSETUP_TCB
    #define portSETUP_TCB( pxTCB )    ( void ) ( pxTCB )
#endif

#ifndef portTASK_SWITCH_HOOK
    #define portTASK_SWITCH_HOOK( pxTCB )    ( void ) ( pxTCB )
#endif

#ifndef configQUEUE_REGISTRY_SIZE
    #define configQUEUE_REGISTRY_SIZE    0U
#endif

#if ( configQUEUE_REGISTRY_SIZE < 1 )
    #define vQueueAddToRegistry( xQueue, pcName )
    #define vQueueUnregisterQueue( xQueue )
    #define pcQueueGetName( xQueue )
#endif

#ifndef configUSE_MINI_LIST_ITEM
    #define configUSE_MINI_LIST_ITEM    1
#endif

#ifndef portPOINTER_SIZE_TYPE
    #define portPOINTER_SIZE_TYPE    uint32_t
#endif

/* Remove any unused trace macros. */
#ifndef traceSTART

/* Used to perform any necessary initialisation - for example, open a file
 * into which trace is to be written. */
    #define traceSTART()
#endif

#ifndef traceEND

/* Use to close a trace, for example close a file into which trace has been
 * written. */
    #define traceEND()
#endif

#ifndef traceTASK_SWITCHED_IN

/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
 * to the task control block of the selected task. */
    #define traceTASK_SWITCHED_IN()
#endif

#ifndef traceINCREASE_TICK_COUNT

/* Called before stepping the tick count after waking from tickless idle
 * sleep. */
    #define traceINCREASE_TICK_COUNT( x )
#endif

#ifndef traceLOW_POWER_IDLE_BEGIN
    /* Called immediately before entering tickless idle. */
    #define traceLOW_POWER_IDLE_BEGIN()
#endif

#ifndef traceLOW_POWER_IDLE_END
    /* Called when returning to the Idle task after a tickless idle. */
    #define traceLOW_POWER_IDLE_END()
#endif

#ifndef traceTASK_SWITCHED_OUT

/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
 * to the task control block of the task being switched out. */
    #define traceTASK_SWITCHED_OUT()
#endif

#ifndef traceTASK_PRIORITY_INHERIT

/* Called when a task attempts to take a mutex that is already held by a
 * lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
 * that holds the mutex.  uxInheritedPriority is the priority the mutex holder
 * will inherit (the priority of the task that is attempting to obtain the
 * muted. */
    #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
#endif

#ifndef traceTASK_PRIORITY_DISINHERIT

/* Called when a task releases a mutex, the holding of which had resulted in
 * the task inheriting the priority of a higher priority task.
 * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
 * mutex.  uxOriginalPriority is the task's configured (base) priority. */
    #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
#endif

#ifndef traceBLOCKING_ON_QUEUE_RECEIVE

/* Task is about to block because it cannot read from a
 * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
 * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
 * task that attempted the read. */
    #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
#endif

#ifndef traceBLOCKING_ON_QUEUE_PEEK

/* Task is about to block because it cannot read from a
 * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
 * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
 * task that attempted the read. */
    #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
#endif

#ifndef traceBLOCKING_ON_QUEUE_SEND

/* Task is about to block because it cannot write to a
 * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
 * upon which the write was attempted.  pxCurrentTCB points to the TCB of the
 * task that attempted the write. */
    #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
#endif

#ifndef configCHECK_FOR_STACK_OVERFLOW
    #define configCHECK_FOR_STACK_OVERFLOW    0
#endif

#ifndef configRECORD_STACK_HIGH_ADDRESS
    #define configRECORD_STACK_HIGH_ADDRESS    0
#endif

#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
    #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H    0
#endif

/* The following event macros are embedded in the kernel API calls. */

#ifndef traceMOVED_TASK_TO_READY_STATE
    #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
#endif

#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
    #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
#endif

#ifndef traceMOVED_TASK_TO_DELAYED_LIST
    #define traceMOVED_TASK_TO_DELAYED_LIST()
#endif

#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
    #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
#endif

#ifndef traceQUEUE_CREATE
    #define traceQUEUE_CREATE( pxNewQueue )
#endif

#ifndef traceQUEUE_CREATE_FAILED
    #define traceQUEUE_CREATE_FAILED( ucQueueType )
#endif

#ifndef traceCREATE_MUTEX
    #define traceCREATE_MUTEX( pxNewQueue )
#endif

#ifndef traceCREATE_MUTEX_FAILED
    #define traceCREATE_MUTEX_FAILED()
#endif

#ifndef traceGIVE_MUTEX_RECURSIVE
    #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
#endif

#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
    #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
#endif

#ifndef traceTAKE_MUTEX_RECURSIVE
    #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
#endif

#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
    #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
#endif

#ifndef traceCREATE_COUNTING_SEMAPHORE
    #define traceCREATE_COUNTING_SEMAPHORE()
#endif

#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
    #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
#endif

#ifndef traceQUEUE_SET_SEND
    #define traceQUEUE_SET_SEND    traceQUEUE_SEND
#endif

#ifndef traceQUEUE_SEND
    #define traceQUEUE_SEND( pxQueue )
#endif

#ifndef traceQUEUE_SEND_FAILED
    #define traceQUEUE_SEND_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_RECEIVE
    #define traceQUEUE_RECEIVE( pxQueue )
#endif

#ifndef traceQUEUE_PEEK
    #define traceQUEUE_PEEK( pxQueue )
#endif

#ifndef traceQUEUE_PEEK_FAILED
    #define traceQUEUE_PEEK_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_PEEK_FROM_ISR
    #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
#endif

#ifndef traceQUEUE_RECEIVE_FAILED
    #define traceQUEUE_RECEIVE_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_SEND_FROM_ISR
    #define traceQUEUE_SEND_FROM_ISR( pxQueue )
#endif

#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
    #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_RECEIVE_FROM_ISR
    #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
#endif

#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
    #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
    #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
#endif

#ifndef traceQUEUE_DELETE
    #define traceQUEUE_DELETE( pxQueue )
#endif

#ifndef traceTASK_CREATE
    #define traceTASK_CREATE( pxNewTCB )
#endif

#ifndef traceTASK_CREATE_FAILED
    #define traceTASK_CREATE_FAILED()
#endif

#ifndef traceTASK_DELETE
    #define traceTASK_DELETE( pxTaskToDelete )
#endif

#ifndef traceTASK_DELAY_UNTIL
    #define traceTASK_DELAY_UNTIL( x )
#endif

#ifndef traceTASK_DELAY
    #define traceTASK_DELAY()
#endif

#ifndef traceTASK_PRIORITY_SET
    #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
#endif

#ifndef traceTASK_SUSPEND
    #define traceTASK_SUSPEND( pxTaskToSuspend )
#endif

#ifndef traceTASK_RESUME
    #define traceTASK_RESUME( pxTaskToResume )
#endif

#ifndef traceTASK_RESUME_FROM_ISR
    #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
#endif

#ifndef traceTASK_INCREMENT_TICK
    #define traceTASK_INCREMENT_TICK( xTickCount )
#endif

#ifndef traceTIMER_CREATE
    #define traceTIMER_CREATE( pxNewTimer )
#endif

#ifndef traceTIMER_CREATE_FAILED
    #define traceTIMER_CREATE_FAILED()
#endif

#ifndef traceTIMER_COMMAND_SEND
    #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
#endif

#ifndef traceTIMER_EXPIRED
    #define traceTIMER_EXPIRED( pxTimer )
#endif

#ifndef traceTIMER_COMMAND_RECEIVED
    #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
#endif

#ifndef traceMALLOC
    #define traceMALLOC( pvAddress, uiSize )
#endif

#ifndef traceFREE
    #define traceFREE( pvAddress, uiSize )
#endif

#ifndef traceEVENT_GROUP_CREATE
    #define traceEVENT_GROUP_CREATE( xEventGroup )
#endif

#ifndef traceEVENT_GROUP_CREATE_FAILED
    #define traceEVENT_GROUP_CREATE_FAILED()
#endif

#ifndef traceEVENT_GROUP_SYNC_BLOCK
    #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
#endif

#ifndef traceEVENT_GROUP_SYNC_END
    #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )
#endif

#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
    #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
#endif

#ifndef traceEVENT_GROUP_WAIT_BITS_END
    #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) ( xTimeoutOccurred )
#endif

#ifndef traceEVENT_GROUP_CLEAR_BITS
    #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
#endif

#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
    #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
#endif

#ifndef traceEVENT_GROUP_SET_BITS
    #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
#endif

#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
    #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
#endif

#ifndef traceEVENT_GROUP_DELETE
    #define traceEVENT_GROUP_DELETE( xEventGroup )
#endif

#ifndef tracePEND_FUNC_CALL
    #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret )
#endif

#ifndef tracePEND_FUNC_CALL_FROM_ISR
    #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret )
#endif

#ifndef traceQUEUE_REGISTRY_ADD
    #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName )
#endif

#ifndef traceTASK_NOTIFY_TAKE_BLOCK
    #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait )
#endif

#ifndef traceTASK_NOTIFY_TAKE
    #define traceTASK_NOTIFY_TAKE( uxIndexToWait )
#endif

#ifndef traceTASK_NOTIFY_WAIT_BLOCK
    #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait )
#endif

#ifndef traceTASK_NOTIFY_WAIT
    #define traceTASK_NOTIFY_WAIT( uxIndexToWait )
#endif

#ifndef traceTASK_NOTIFY
    #define traceTASK_NOTIFY( uxIndexToNotify )
#endif

#ifndef traceTASK_NOTIFY_FROM_ISR
    #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify )
#endif

#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
    #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
#endif

#ifndef traceISR_EXIT_TO_SCHEDULER
    #define traceISR_EXIT_TO_SCHEDULER()
#endif

#ifndef traceISR_EXIT
    #define traceISR_EXIT()
#endif

#ifndef traceISR_ENTER
    #define traceISR_ENTER()
#endif

#ifndef traceSTREAM_BUFFER_CREATE_FAILED
    #define traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType )
#endif

#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType )
#endif

#ifndef traceSTREAM_BUFFER_CREATE
    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType )
#endif

#ifndef traceSTREAM_BUFFER_DELETE
    #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_RESET
    #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_RESET_FROM_ISR
    #define traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer )
#endif

#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
    #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_SEND
    #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
#endif

#ifndef traceSTREAM_BUFFER_SEND_FAILED
    #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
    #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
#endif

#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
    #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_RECEIVE
    #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
#endif

#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
    #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
#endif

#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
    #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
#endif

#ifndef traceENTER_xEventGroupCreateStatic
    #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer )
#endif

#ifndef traceRETURN_xEventGroupCreateStatic
    #define traceRETURN_xEventGroupCreateStatic( pxEventBits )
#endif

#ifndef traceENTER_xEventGroupCreate
    #define traceENTER_xEventGroupCreate()
#endif

#ifndef traceRETURN_xEventGroupCreate
    #define traceRETURN_xEventGroupCreate( pxEventBits )
#endif

#ifndef traceENTER_xEventGroupSync
    #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait )
#endif

#ifndef traceRETURN_xEventGroupSync
    #define traceRETURN_xEventGroupSync( uxReturn )
#endif

#ifndef traceENTER_xEventGroupWaitBits
    #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait )
#endif

#ifndef traceRETURN_xEventGroupWaitBits
    #define traceRETURN_xEventGroupWaitBits( uxReturn )
#endif

#ifndef traceENTER_xEventGroupClearBits
    #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear )
#endif

#ifndef traceRETURN_xEventGroupClearBits
    #define traceRETURN_xEventGroupClearBits( uxReturn )
#endif

#ifndef traceENTER_xEventGroupClearBitsFromISR
    #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear )
#endif

#ifndef traceRETURN_xEventGroupClearBitsFromISR
    #define traceRETURN_xEventGroupClearBitsFromISR( xReturn )
#endif

#ifndef traceENTER_xEventGroupGetBitsFromISR
    #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup )
#endif

#ifndef traceRETURN_xEventGroupGetBitsFromISR
    #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn )
#endif

#ifndef traceENTER_xEventGroupSetBits
    #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet )
#endif

#ifndef traceRETURN_xEventGroupSetBits
    #define traceRETURN_xEventGroupSetBits( uxEventBits )
#endif

#ifndef traceENTER_vEventGroupDelete
    #define traceENTER_vEventGroupDelete( xEventGroup )
#endif

#ifndef traceRETURN_vEventGroupDelete
    #define traceRETURN_vEventGroupDelete()
#endif

#ifndef traceENTER_xEventGroupGetStaticBuffer
    #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer )
#endif

#ifndef traceRETURN_xEventGroupGetStaticBuffer
    #define traceRETURN_xEventGroupGetStaticBuffer( xReturn )
#endif

#ifndef traceENTER_vEventGroupSetBitsCallback
    #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet )
#endif

#ifndef traceRETURN_vEventGroupSetBitsCallback
    #define traceRETURN_vEventGroupSetBitsCallback()
#endif

#ifndef traceENTER_vEventGroupClearBitsCallback
    #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear )
#endif

#ifndef traceRETURN_vEventGroupClearBitsCallback
    #define traceRETURN_vEventGroupClearBitsCallback()
#endif

#ifndef traceENTER_xEventGroupSetBitsFromISR
    #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xEventGroupSetBitsFromISR
    #define traceRETURN_xEventGroupSetBitsFromISR( xReturn )
#endif

#ifndef traceENTER_uxEventGroupGetNumber
    #define traceENTER_uxEventGroupGetNumber( xEventGroup )
#endif

#ifndef traceRETURN_uxEventGroupGetNumber
    #define traceRETURN_uxEventGroupGetNumber( xReturn )
#endif

#ifndef traceENTER_vEventGroupSetNumber
    #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber )
#endif

#ifndef traceRETURN_vEventGroupSetNumber
    #define traceRETURN_vEventGroupSetNumber()
#endif

#ifndef traceENTER_xQueueGenericReset
    #define traceENTER_xQueueGenericReset( xQueue, xNewQueue )
#endif

#ifndef traceRETURN_xQueueGenericReset
    #define traceRETURN_xQueueGenericReset( xReturn )
#endif

#ifndef traceENTER_xQueueGenericCreateStatic
    #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType )
#endif

#ifndef traceRETURN_xQueueGenericCreateStatic
    #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue )
#endif

#ifndef traceENTER_xQueueGenericGetStaticBuffers
    #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )
#endif

#ifndef traceRETURN_xQueueGenericGetStaticBuffers
    #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn )
#endif

#ifndef traceENTER_xQueueGenericCreate
    #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType )
#endif

#ifndef traceRETURN_xQueueGenericCreate
    #define traceRETURN_xQueueGenericCreate( pxNewQueue )
#endif

#ifndef traceENTER_xQueueCreateMutex
    #define traceENTER_xQueueCreateMutex( ucQueueType )
#endif

#ifndef traceRETURN_xQueueCreateMutex
    #define traceRETURN_xQueueCreateMutex( xNewQueue )
#endif

#ifndef traceENTER_xQueueCreateMutexStatic
    #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue )
#endif

#ifndef traceRETURN_xQueueCreateMutexStatic
    #define traceRETURN_xQueueCreateMutexStatic( xNewQueue )
#endif

#ifndef traceENTER_xQueueGetMutexHolder
    #define traceENTER_xQueueGetMutexHolder( xSemaphore )
#endif

#ifndef traceRETURN_xQueueGetMutexHolder
    #define traceRETURN_xQueueGetMutexHolder( pxReturn )
#endif

#ifndef traceENTER_xQueueGetMutexHolderFromISR
    #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore )
#endif

#ifndef traceRETURN_xQueueGetMutexHolderFromISR
    #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn )
#endif

#ifndef traceENTER_xQueueGiveMutexRecursive
    #define traceENTER_xQueueGiveMutexRecursive( xMutex )
#endif

#ifndef traceRETURN_xQueueGiveMutexRecursive
    #define traceRETURN_xQueueGiveMutexRecursive( xReturn )
#endif

#ifndef traceENTER_xQueueTakeMutexRecursive
    #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueTakeMutexRecursive
    #define traceRETURN_xQueueTakeMutexRecursive( xReturn )
#endif

#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic
    #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue )
#endif

#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic
    #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle )
#endif

#ifndef traceENTER_xQueueCreateCountingSemaphore
    #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount )
#endif

#ifndef traceRETURN_xQueueCreateCountingSemaphore
    #define traceRETURN_xQueueCreateCountingSemaphore( xHandle )
#endif

#ifndef traceENTER_xQueueGenericSend
    #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition )
#endif

#ifndef traceRETURN_xQueueGenericSend
    #define traceRETURN_xQueueGenericSend( xReturn )
#endif

#ifndef traceENTER_xQueueGenericSendFromISR
    #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition )
#endif

#ifndef traceRETURN_xQueueGenericSendFromISR
    #define traceRETURN_xQueueGenericSendFromISR( xReturn )
#endif

#ifndef traceENTER_xQueueGiveFromISR
    #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xQueueGiveFromISR
    #define traceRETURN_xQueueGiveFromISR( xReturn )
#endif

#ifndef traceENTER_xQueueReceive
    #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueReceive
    #define traceRETURN_xQueueReceive( xReturn )
#endif

#ifndef traceENTER_xQueueSemaphoreTake
    #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueSemaphoreTake
    #define traceRETURN_xQueueSemaphoreTake( xReturn )
#endif

#ifndef traceENTER_xQueuePeek
    #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait )
#endif

#ifndef traceRETURN_xQueuePeek
    #define traceRETURN_xQueuePeek( xReturn )
#endif

#ifndef traceENTER_xQueueReceiveFromISR
    #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xQueueReceiveFromISR
    #define traceRETURN_xQueueReceiveFromISR( xReturn )
#endif

#ifndef traceENTER_xQueuePeekFromISR
    #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer )
#endif

#ifndef traceRETURN_xQueuePeekFromISR
    #define traceRETURN_xQueuePeekFromISR( xReturn )
#endif

#ifndef traceENTER_uxQueueMessagesWaiting
    #define traceENTER_uxQueueMessagesWaiting( xQueue )
#endif

#ifndef traceRETURN_uxQueueMessagesWaiting
    #define traceRETURN_uxQueueMessagesWaiting( uxReturn )
#endif

#ifndef traceENTER_uxQueueSpacesAvailable
    #define traceENTER_uxQueueSpacesAvailable( xQueue )
#endif

#ifndef traceRETURN_uxQueueSpacesAvailable
    #define traceRETURN_uxQueueSpacesAvailable( uxReturn )
#endif

#ifndef traceENTER_uxQueueMessagesWaitingFromISR
    #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue )
#endif

#ifndef traceRETURN_uxQueueMessagesWaitingFromISR
    #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn )
#endif

#ifndef traceENTER_vQueueDelete
    #define traceENTER_vQueueDelete( xQueue )
#endif

#ifndef traceRETURN_vQueueDelete
    #define traceRETURN_vQueueDelete()
#endif

#ifndef traceENTER_uxQueueGetQueueNumber
    #define traceENTER_uxQueueGetQueueNumber( xQueue )
#endif

#ifndef traceRETURN_uxQueueGetQueueNumber
    #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber )
#endif

#ifndef traceENTER_vQueueSetQueueNumber
    #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber )
#endif

#ifndef traceRETURN_vQueueSetQueueNumber
    #define traceRETURN_vQueueSetQueueNumber()
#endif

#ifndef traceENTER_ucQueueGetQueueType
    #define traceENTER_ucQueueGetQueueType( xQueue )
#endif

#ifndef traceRETURN_ucQueueGetQueueType
    #define traceRETURN_ucQueueGetQueueType( ucQueueType )
#endif

#ifndef traceENTER_uxQueueGetQueueItemSize
    #define traceENTER_uxQueueGetQueueItemSize( xQueue )
#endif

#ifndef traceRETURN_uxQueueGetQueueItemSize
    #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize )
#endif

#ifndef traceENTER_uxQueueGetQueueLength
    #define traceENTER_uxQueueGetQueueLength( xQueue )
#endif

#ifndef traceRETURN_uxQueueGetQueueLength
    #define traceRETURN_uxQueueGetQueueLength( uxLength )
#endif

#ifndef traceENTER_xQueueIsQueueEmptyFromISR
    #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue )
#endif

#ifndef traceRETURN_xQueueIsQueueEmptyFromISR
    #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn )
#endif

#ifndef traceENTER_xQueueIsQueueFullFromISR
    #define traceENTER_xQueueIsQueueFullFromISR( xQueue )
#endif

#ifndef traceRETURN_xQueueIsQueueFullFromISR
    #define traceRETURN_xQueueIsQueueFullFromISR( xReturn )
#endif

#ifndef traceENTER_xQueueCRSend
    #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueCRSend
    #define traceRETURN_xQueueCRSend( xReturn )
#endif

#ifndef traceENTER_xQueueCRReceive
    #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueCRReceive
    #define traceRETURN_xQueueCRReceive( xReturn )
#endif

#ifndef traceENTER_xQueueCRSendFromISR
    #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken )
#endif

#ifndef traceRETURN_xQueueCRSendFromISR
    #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken )
#endif

#ifndef traceENTER_xQueueCRReceiveFromISR
    #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken )
#endif

#ifndef traceRETURN_xQueueCRReceiveFromISR
    #define traceRETURN_xQueueCRReceiveFromISR( xReturn )
#endif

#ifndef traceENTER_vQueueAddToRegistry
    #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName )
#endif

#ifndef traceRETURN_vQueueAddToRegistry
    #define traceRETURN_vQueueAddToRegistry()
#endif

#ifndef traceENTER_pcQueueGetName
    #define traceENTER_pcQueueGetName( xQueue )
#endif

#ifndef traceRETURN_pcQueueGetName
    #define traceRETURN_pcQueueGetName( pcReturn )
#endif

#ifndef traceENTER_vQueueUnregisterQueue
    #define traceENTER_vQueueUnregisterQueue( xQueue )
#endif

#ifndef traceRETURN_vQueueUnregisterQueue
    #define traceRETURN_vQueueUnregisterQueue()
#endif

#ifndef traceENTER_vQueueWaitForMessageRestricted
    #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely )
#endif

#ifndef traceRETURN_vQueueWaitForMessageRestricted
    #define traceRETURN_vQueueWaitForMessageRestricted()
#endif

#ifndef traceENTER_xQueueCreateSet
    #define traceENTER_xQueueCreateSet( uxEventQueueLength )
#endif

#ifndef traceRETURN_xQueueCreateSet
    #define traceRETURN_xQueueCreateSet( pxQueue )
#endif

#ifndef traceENTER_xQueueAddToSet
    #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet )
#endif

#ifndef traceRETURN_xQueueAddToSet
    #define traceRETURN_xQueueAddToSet( xReturn )
#endif

#ifndef traceENTER_xQueueRemoveFromSet
    #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet )
#endif

#ifndef traceRETURN_xQueueRemoveFromSet
    #define traceRETURN_xQueueRemoveFromSet( xReturn )
#endif

#ifndef traceENTER_xQueueSelectFromSet
    #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait )
#endif

#ifndef traceRETURN_xQueueSelectFromSet
    #define traceRETURN_xQueueSelectFromSet( xReturn )
#endif

#ifndef traceENTER_xQueueSelectFromSetFromISR
    #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet )
#endif

#ifndef traceRETURN_xQueueSelectFromSetFromISR
    #define traceRETURN_xQueueSelectFromSetFromISR( xReturn )
#endif

#ifndef traceENTER_xTimerCreateTimerTask
    #define traceENTER_xTimerCreateTimerTask()
#endif

#ifndef traceRETURN_xTimerCreateTimerTask
    #define traceRETURN_xTimerCreateTimerTask( xReturn )
#endif

#ifndef traceENTER_xTimerCreate
    #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction )
#endif

#ifndef traceRETURN_xTimerCreate
    #define traceRETURN_xTimerCreate( pxNewTimer )
#endif

#ifndef traceENTER_xTimerCreateStatic
    #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer )
#endif

#ifndef traceRETURN_xTimerCreateStatic
    #define traceRETURN_xTimerCreateStatic( pxNewTimer )
#endif

#ifndef traceENTER_xTimerGenericCommandFromTask
    #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
#endif

#ifndef traceRETURN_xTimerGenericCommandFromTask
    #define traceRETURN_xTimerGenericCommandFromTask( xReturn )
#endif

#ifndef traceENTER_xTimerGenericCommandFromISR
    #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )
#endif

#ifndef traceRETURN_xTimerGenericCommandFromISR
    #define traceRETURN_xTimerGenericCommandFromISR( xReturn )
#endif

#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle
    #define traceENTER_xTimerGetTimerDaemonTaskHandle()
#endif

#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle
    #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle )
#endif

#ifndef traceENTER_xTimerGetPeriod
    #define traceENTER_xTimerGetPeriod( xTimer )
#endif

#ifndef traceRETURN_xTimerGetPeriod
    #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks )
#endif

#ifndef traceENTER_vTimerSetReloadMode
    #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload )
#endif

#ifndef traceRETURN_vTimerSetReloadMode
    #define traceRETURN_vTimerSetReloadMode()
#endif

#ifndef traceENTER_xTimerGetReloadMode
    #define traceENTER_xTimerGetReloadMode( xTimer )
#endif

#ifndef traceRETURN_xTimerGetReloadMode
    #define traceRETURN_xTimerGetReloadMode( xReturn )
#endif

#ifndef traceENTER_uxTimerGetReloadMode
    #define traceENTER_uxTimerGetReloadMode( xTimer )
#endif

#ifndef traceRETURN_uxTimerGetReloadMode
    #define traceRETURN_uxTimerGetReloadMode( uxReturn )
#endif

#ifndef traceENTER_xTimerGetExpiryTime
    #define traceENTER_xTimerGetExpiryTime( xTimer )
#endif

#ifndef traceRETURN_xTimerGetExpiryTime
    #define traceRETURN_xTimerGetExpiryTime( xReturn )
#endif

#ifndef traceENTER_xTimerGetStaticBuffer
    #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer )
#endif

#ifndef traceRETURN_xTimerGetStaticBuffer
    #define traceRETURN_xTimerGetStaticBuffer( xReturn )
#endif

#ifndef traceENTER_pcTimerGetName
    #define traceENTER_pcTimerGetName( xTimer )
#endif

#ifndef traceRETURN_pcTimerGetName
    #define traceRETURN_pcTimerGetName( pcTimerName )
#endif

#ifndef traceENTER_xTimerIsTimerActive
    #define traceENTER_xTimerIsTimerActive( xTimer )
#endif

#ifndef traceRETURN_xTimerIsTimerActive
    #define traceRETURN_xTimerIsTimerActive( xReturn )
#endif

#ifndef traceENTER_pvTimerGetTimerID
    #define traceENTER_pvTimerGetTimerID( xTimer )
#endif

#ifndef traceRETURN_pvTimerGetTimerID
    #define traceRETURN_pvTimerGetTimerID( pvReturn )
#endif

#ifndef traceENTER_vTimerSetTimerID
    #define traceENTER_vTimerSetTimerID( xTimer, pvNewID )
#endif

#ifndef traceRETURN_vTimerSetTimerID
    #define traceRETURN_vTimerSetTimerID()
#endif

#ifndef traceENTER_xTimerPendFunctionCallFromISR
    #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xTimerPendFunctionCallFromISR
    #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn )
#endif

#ifndef traceENTER_xTimerPendFunctionCall
    #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait )
#endif

#ifndef traceRETURN_xTimerPendFunctionCall
    #define traceRETURN_xTimerPendFunctionCall( xReturn )
#endif

#ifndef traceENTER_uxTimerGetTimerNumber
    #define traceENTER_uxTimerGetTimerNumber( xTimer )
#endif

#ifndef traceRETURN_uxTimerGetTimerNumber
    #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber )
#endif

#ifndef traceENTER_vTimerSetTimerNumber
    #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber )
#endif

#ifndef traceRETURN_vTimerSetTimerNumber
    #define traceRETURN_vTimerSetTimerNumber()
#endif

#ifndef traceENTER_xTaskCreateStatic
    #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer )
#endif

#ifndef traceRETURN_xTaskCreateStatic
    #define traceRETURN_xTaskCreateStatic( xReturn )
#endif

#ifndef traceENTER_xTaskCreateStaticAffinitySet
    #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask )
#endif

#ifndef traceRETURN_xTaskCreateStaticAffinitySet
    #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn )
#endif

#ifndef traceENTER_xTaskCreateRestrictedStatic
    #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreateRestrictedStatic
    #define traceRETURN_xTaskCreateRestrictedStatic( xReturn )
#endif

#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet
    #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet
    #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn )
#endif

#ifndef traceENTER_xTaskCreateRestricted
    #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreateRestricted
    #define traceRETURN_xTaskCreateRestricted( xReturn )
#endif

#ifndef traceENTER_xTaskCreateRestrictedAffinitySet
    #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet
    #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn )
#endif

#ifndef traceENTER_xTaskCreate
    #define traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreate
    #define traceRETURN_xTaskCreate( xReturn )
#endif

#ifndef traceENTER_xTaskCreateAffinitySet
    #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask )
#endif

#ifndef traceRETURN_xTaskCreateAffinitySet
    #define traceRETURN_xTaskCreateAffinitySet( xReturn )
#endif

#ifndef traceENTER_vTaskDelete
    #define traceENTER_vTaskDelete( xTaskToDelete )
#endif

#ifndef traceRETURN_vTaskDelete
    #define traceRETURN_vTaskDelete()
#endif

#ifndef traceENTER_xTaskDelayUntil
    #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )
#endif

#ifndef traceRETURN_xTaskDelayUntil
    #define traceRETURN_xTaskDelayUntil( xShouldDelay )
#endif

#ifndef traceENTER_vTaskDelay
    #define traceENTER_vTaskDelay( xTicksToDelay )
#endif

#ifndef traceRETURN_vTaskDelay
    #define traceRETURN_vTaskDelay()
#endif

#ifndef traceENTER_eTaskGetState
    #define traceENTER_eTaskGetState( xTask )
#endif

#ifndef traceRETURN_eTaskGetState
    #define traceRETURN_eTaskGetState( eReturn )
#endif

#ifndef traceENTER_uxTaskPriorityGet
    #define traceENTER_uxTaskPriorityGet( xTask )
#endif

#ifndef traceRETURN_uxTaskPriorityGet
    #define traceRETURN_uxTaskPriorityGet( uxReturn )
#endif

#ifndef traceENTER_uxTaskPriorityGetFromISR
    #define traceENTER_uxTaskPriorityGetFromISR( xTask )
#endif

#ifndef traceRETURN_uxTaskPriorityGetFromISR
    #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn )
#endif

#ifndef traceENTER_uxTaskBasePriorityGet
    #define traceENTER_uxTaskBasePriorityGet( xTask )
#endif

#ifndef traceRETURN_uxTaskBasePriorityGet
    #define traceRETURN_uxTaskBasePriorityGet( uxReturn )
#endif

#ifndef traceENTER_uxTaskBasePriorityGetFromISR
    #define traceENTER_uxTaskBasePriorityGetFromISR( xTask )
#endif

#ifndef traceRETURN_uxTaskBasePriorityGetFromISR
    #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn )
#endif

#ifndef traceENTER_vTaskPrioritySet
    #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority )
#endif

#ifndef traceRETURN_vTaskPrioritySet
    #define traceRETURN_vTaskPrioritySet()
#endif

#ifndef traceENTER_vTaskCoreAffinitySet
    #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask )
#endif

#ifndef traceRETURN_vTaskCoreAffinitySet
    #define traceRETURN_vTaskCoreAffinitySet()
#endif

#ifndef traceENTER_vTaskCoreAffinityGet
    #define traceENTER_vTaskCoreAffinityGet( xTask )
#endif

#ifndef traceRETURN_vTaskCoreAffinityGet
    #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask )
#endif

#ifndef traceENTER_vTaskPreemptionDisable
    #define traceENTER_vTaskPreemptionDisable( xTask )
#endif

#ifndef traceRETURN_vTaskPreemptionDisable
    #define traceRETURN_vTaskPreemptionDisable()
#endif

#ifndef traceENTER_vTaskPreemptionEnable
    #define traceENTER_vTaskPreemptionEnable( xTask )
#endif

#ifndef traceRETURN_vTaskPreemptionEnable
    #define traceRETURN_vTaskPreemptionEnable()
#endif

#ifndef traceENTER_vTaskSuspend
    #define traceENTER_vTaskSuspend( xTaskToSuspend )
#endif

#ifndef traceRETURN_vTaskSuspend
    #define traceRETURN_vTaskSuspend()
#endif

#ifndef traceENTER_vTaskResume
    #define traceENTER_vTaskResume( xTaskToResume )
#endif

#ifndef traceRETURN_vTaskResume
    #define traceRETURN_vTaskResume()
#endif

#ifndef traceENTER_xTaskResumeFromISR
    #define traceENTER_xTaskResumeFromISR( xTaskToResume )
#endif

#ifndef traceRETURN_xTaskResumeFromISR
    #define traceRETURN_xTaskResumeFromISR( xYieldRequired )
#endif

#ifndef traceENTER_vTaskStartScheduler
    #define traceENTER_vTaskStartScheduler()
#endif

#ifndef traceRETURN_vTaskStartScheduler
    #define traceRETURN_vTaskStartScheduler()
#endif

#ifndef traceENTER_vTaskEndScheduler
    #define traceENTER_vTaskEndScheduler()
#endif

#ifndef traceRETURN_vTaskEndScheduler
    #define traceRETURN_vTaskEndScheduler()
#endif

#ifndef traceENTER_vTaskSuspendAll
    #define traceENTER_vTaskSuspendAll()
#endif

#ifndef traceRETURN_vTaskSuspendAll
    #define traceRETURN_vTaskSuspendAll()
#endif

#ifndef traceENTER_xTaskResumeAll
    #define traceENTER_xTaskResumeAll()
#endif

#ifndef traceRETURN_xTaskResumeAll
    #define traceRETURN_xTaskResumeAll( xAlreadyYielded )
#endif

#ifndef traceENTER_xTaskGetTickCount
    #define traceENTER_xTaskGetTickCount()
#endif

#ifndef traceRETURN_xTaskGetTickCount
    #define traceRETURN_xTaskGetTickCount( xTicks )
#endif

#ifndef traceENTER_xTaskGetTickCountFromISR
    #define traceENTER_xTaskGetTickCountFromISR()
#endif

#ifndef traceRETURN_xTaskGetTickCountFromISR
    #define traceRETURN_xTaskGetTickCountFromISR( xReturn )
#endif

#ifndef traceENTER_uxTaskGetNumberOfTasks
    #define traceENTER_uxTaskGetNumberOfTasks()
#endif

#ifndef traceRETURN_uxTaskGetNumberOfTasks
    #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks )
#endif

#ifndef traceENTER_pcTaskGetName
    #define traceENTER_pcTaskGetName( xTaskToQuery )
#endif

#ifndef traceRETURN_pcTaskGetName
    #define traceRETURN_pcTaskGetName( pcTaskName )
#endif

#ifndef traceENTER_xTaskGetHandle
    #define traceENTER_xTaskGetHandle( pcNameToQuery )
#endif

#ifndef traceRETURN_xTaskGetHandle
    #define traceRETURN_xTaskGetHandle( pxTCB )
#endif

#ifndef traceENTER_xTaskGetStaticBuffers
    #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer )
#endif

#ifndef traceRETURN_xTaskGetStaticBuffers
    #define traceRETURN_xTaskGetStaticBuffers( xReturn )
#endif

#ifndef traceENTER_uxTaskGetSystemState
    #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime )
#endif

#ifndef traceRETURN_uxTaskGetSystemState
    #define traceRETURN_uxTaskGetSystemState( uxTask )
#endif

#if ( configNUMBER_OF_CORES == 1 )
    #ifndef traceENTER_xTaskGetIdleTaskHandle
        #define traceENTER_xTaskGetIdleTaskHandle()
    #endif
#endif

#if ( configNUMBER_OF_CORES == 1 )
    #ifndef traceRETURN_xTaskGetIdleTaskHandle
        #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle )
    #endif
#endif

#ifndef traceENTER_xTaskGetIdleTaskHandleForCore
    #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID )
#endif

#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore
    #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle )
#endif

#ifndef traceENTER_vTaskStepTick
    #define traceENTER_vTaskStepTick( xTicksToJump )
#endif

#ifndef traceRETURN_vTaskStepTick
    #define traceRETURN_vTaskStepTick()
#endif

#ifndef traceENTER_xTaskCatchUpTicks
    #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp )
#endif

#ifndef traceRETURN_xTaskCatchUpTicks
    #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred )
#endif

#ifndef traceENTER_xTaskAbortDelay
    #define traceENTER_xTaskAbortDelay( xTask )
#endif

#ifndef traceRETURN_xTaskAbortDelay
    #define traceRETURN_xTaskAbortDelay( xReturn )
#endif

#ifndef traceENTER_xTaskIncrementTick
    #define traceENTER_xTaskIncrementTick()
#endif

#ifndef traceRETURN_xTaskIncrementTick
    #define traceRETURN_xTaskIncrementTick( xSwitchRequired )
#endif

#ifndef traceENTER_vTaskSetApplicationTaskTag
    #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction )
#endif

#ifndef traceRETURN_vTaskSetApplicationTaskTag
    #define traceRETURN_vTaskSetApplicationTaskTag()
#endif

#ifndef traceENTER_xTaskGetApplicationTaskTag
    #define traceENTER_xTaskGetApplicationTaskTag( xTask )
#endif

#ifndef traceRETURN_xTaskGetApplicationTaskTag
    #define traceRETURN_xTaskGetApplicationTaskTag( xReturn )
#endif

#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR
    #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask )
#endif

#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR
    #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn )
#endif

#ifndef traceENTER_xTaskCallApplicationTaskHook
    #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter )
#endif

#ifndef traceRETURN_xTaskCallApplicationTaskHook
    #define traceRETURN_xTaskCallApplicationTaskHook( xReturn )
#endif

#ifndef traceENTER_vTaskSwitchContext
    #define traceENTER_vTaskSwitchContext()
#endif

#ifndef traceRETURN_vTaskSwitchContext
    #define traceRETURN_vTaskSwitchContext()
#endif

#ifndef traceENTER_vTaskPlaceOnEventList
    #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait )
#endif

#ifndef traceRETURN_vTaskPlaceOnEventList
    #define traceRETURN_vTaskPlaceOnEventList()
#endif

#ifndef traceENTER_vTaskPlaceOnUnorderedEventList
    #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait )
#endif

#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList
    #define traceRETURN_vTaskPlaceOnUnorderedEventList()
#endif

#ifndef traceENTER_vTaskPlaceOnEventListRestricted
    #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely )
#endif

#ifndef traceRETURN_vTaskPlaceOnEventListRestricted
    #define traceRETURN_vTaskPlaceOnEventListRestricted()
#endif

#ifndef traceENTER_xTaskRemoveFromEventList
    #define traceENTER_xTaskRemoveFromEventList( pxEventList )
#endif

#ifndef traceRETURN_xTaskRemoveFromEventList
    #define traceRETURN_xTaskRemoveFromEventList( xReturn )
#endif

#ifndef traceENTER_vTaskRemoveFromUnorderedEventList
    #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue )
#endif

#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList
    #define traceRETURN_vTaskRemoveFromUnorderedEventList()
#endif

#ifndef traceENTER_vTaskSetTimeOutState
    #define traceENTER_vTaskSetTimeOutState( pxTimeOut )
#endif

#ifndef traceRETURN_vTaskSetTimeOutState
    #define traceRETURN_vTaskSetTimeOutState()
#endif

#ifndef traceENTER_vTaskInternalSetTimeOutState
    #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut )
#endif

#ifndef traceRETURN_vTaskInternalSetTimeOutState
    #define traceRETURN_vTaskInternalSetTimeOutState()
#endif

#ifndef traceENTER_xTaskCheckForTimeOut
    #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait )
#endif

#ifndef traceRETURN_xTaskCheckForTimeOut
    #define traceRETURN_xTaskCheckForTimeOut( xReturn )
#endif

#ifndef traceENTER_vTaskMissedYield
    #define traceENTER_vTaskMissedYield()
#endif

#ifndef traceRETURN_vTaskMissedYield
    #define traceRETURN_vTaskMissedYield()
#endif

#ifndef traceENTER_uxTaskGetTaskNumber
    #define traceENTER_uxTaskGetTaskNumber( xTask )
#endif

#ifndef traceRETURN_uxTaskGetTaskNumber
    #define traceRETURN_uxTaskGetTaskNumber( uxReturn )
#endif

#ifndef traceENTER_vTaskSetTaskNumber
    #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle )
#endif

#ifndef traceRETURN_vTaskSetTaskNumber
    #define traceRETURN_vTaskSetTaskNumber()
#endif

#ifndef traceENTER_eTaskConfirmSleepModeStatus
    #define traceENTER_eTaskConfirmSleepModeStatus()
#endif

#ifndef traceRETURN_eTaskConfirmSleepModeStatus
    #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn )
#endif

#ifndef traceENTER_vTaskSetThreadLocalStoragePointer
    #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue )
#endif

#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer
    #define traceRETURN_vTaskSetThreadLocalStoragePointer()
#endif

#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer
    #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex )
#endif

#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer
    #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn )
#endif

#ifndef traceENTER_vTaskAllocateMPURegions
    #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions )
#endif

#ifndef traceRETURN_vTaskAllocateMPURegions
    #define traceRETURN_vTaskAllocateMPURegions()
#endif

#ifndef traceENTER_vTaskGetInfo
    #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState )
#endif

#ifndef traceRETURN_vTaskGetInfo
    #define traceRETURN_vTaskGetInfo()
#endif

#ifndef traceENTER_uxTaskGetStackHighWaterMark2
    #define traceENTER_uxTaskGetStackHighWaterMark2( xTask )
#endif

#ifndef traceRETURN_uxTaskGetStackHighWaterMark2
    #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn )
#endif

#ifndef traceENTER_uxTaskGetStackHighWaterMark
    #define traceENTER_uxTaskGetStackHighWaterMark( xTask )
#endif

#ifndef traceRETURN_uxTaskGetStackHighWaterMark
    #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn )
#endif

#ifndef traceENTER_xTaskGetCurrentTaskHandle
    #define traceENTER_xTaskGetCurrentTaskHandle()
#endif

#ifndef traceRETURN_xTaskGetCurrentTaskHandle
    #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn )
#endif

#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore
    #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID )
#endif

#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore
    #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn )
#endif

#ifndef traceENTER_xTaskGetSchedulerState
    #define traceENTER_xTaskGetSchedulerState()
#endif

#ifndef traceRETURN_xTaskGetSchedulerState
    #define traceRETURN_xTaskGetSchedulerState( xReturn )
#endif

#ifndef traceENTER_xTaskPriorityInherit
    #define traceENTER_xTaskPriorityInherit( pxMutexHolder )
#endif

#ifndef traceRETURN_xTaskPriorityInherit
    #define traceRETURN_xTaskPriorityInherit( xReturn )
#endif

#ifndef traceENTER_xTaskPriorityDisinherit
    #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder )
#endif

#ifndef traceRETURN_xTaskPriorityDisinherit
    #define traceRETURN_xTaskPriorityDisinherit( xReturn )
#endif

#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout
    #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask )
#endif

#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout
    #define traceRETURN_vTaskPriorityDisinheritAfterTimeout()
#endif

#ifndef traceENTER_vTaskYieldWithinAPI
    #define traceENTER_vTaskYieldWithinAPI()
#endif

#ifndef traceRETURN_vTaskYieldWithinAPI
    #define traceRETURN_vTaskYieldWithinAPI()
#endif

#ifndef traceENTER_vTaskEnterCritical
    #define traceENTER_vTaskEnterCritical()
#endif

#ifndef traceRETURN_vTaskEnterCritical
    #define traceRETURN_vTaskEnterCritical()
#endif

#ifndef traceENTER_vTaskEnterCriticalFromISR
    #define traceENTER_vTaskEnterCriticalFromISR()
#endif

#ifndef traceRETURN_vTaskEnterCriticalFromISR
    #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus )
#endif

#ifndef traceENTER_vTaskExitCritical
    #define traceENTER_vTaskExitCritical()
#endif

#ifndef traceRETURN_vTaskExitCritical
    #define traceRETURN_vTaskExitCritical()
#endif

#ifndef traceENTER_vTaskExitCriticalFromISR
    #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus )
#endif

#ifndef traceRETURN_vTaskExitCriticalFromISR
    #define traceRETURN_vTaskExitCriticalFromISR()
#endif

#ifndef traceENTER_vTaskListTasks
    #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength )
#endif

#ifndef traceRETURN_vTaskListTasks
    #define traceRETURN_vTaskListTasks()
#endif

#ifndef traceENTER_vTaskGetRunTimeStatistics
    #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength )
#endif

#ifndef traceRETURN_vTaskGetRunTimeStatistics
    #define traceRETURN_vTaskGetRunTimeStatistics()
#endif

#ifndef traceENTER_uxTaskResetEventItemValue
    #define traceENTER_uxTaskResetEventItemValue()
#endif

#ifndef traceRETURN_uxTaskResetEventItemValue
    #define traceRETURN_uxTaskResetEventItemValue( uxReturn )
#endif

#ifndef traceENTER_pvTaskIncrementMutexHeldCount
    #define traceENTER_pvTaskIncrementMutexHeldCount()
#endif

#ifndef traceRETURN_pvTaskIncrementMutexHeldCount
    #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB )
#endif

#ifndef traceENTER_ulTaskGenericNotifyTake
    #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait )
#endif

#ifndef traceRETURN_ulTaskGenericNotifyTake
    #define traceRETURN_ulTaskGenericNotifyTake( ulReturn )
#endif

#ifndef traceENTER_xTaskGenericNotifyWait
    #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait )
#endif

#ifndef traceRETURN_xTaskGenericNotifyWait
    #define traceRETURN_xTaskGenericNotifyWait( xReturn )
#endif

#ifndef traceENTER_xTaskGenericNotify
    #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue )
#endif

#ifndef traceRETURN_xTaskGenericNotify
    #define traceRETURN_xTaskGenericNotify( xReturn )
#endif

#ifndef traceENTER_xTaskGenericNotifyFromISR
    #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xTaskGenericNotifyFromISR
    #define traceRETURN_xTaskGenericNotifyFromISR( xReturn )
#endif

#ifndef traceENTER_vTaskGenericNotifyGiveFromISR
    #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR
    #define traceRETURN_vTaskGenericNotifyGiveFromISR()
#endif

#ifndef traceENTER_xTaskGenericNotifyStateClear
    #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear )
#endif

#ifndef traceRETURN_xTaskGenericNotifyStateClear
    #define traceRETURN_xTaskGenericNotifyStateClear( xReturn )
#endif

#ifndef traceENTER_ulTaskGenericNotifyValueClear
    #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear )
#endif

#ifndef traceRETURN_ulTaskGenericNotifyValueClear
    #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn )
#endif

#ifndef traceENTER_ulTaskGetRunTimeCounter
    #define traceENTER_ulTaskGetRunTimeCounter( xTask )
#endif

#ifndef traceRETURN_ulTaskGetRunTimeCounter
    #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter )
#endif

#ifndef traceENTER_ulTaskGetRunTimePercent
    #define traceENTER_ulTaskGetRunTimePercent( xTask )
#endif

#ifndef traceRETURN_ulTaskGetRunTimePercent
    #define traceRETURN_ulTaskGetRunTimePercent( ulReturn )
#endif

#ifndef traceENTER_ulTaskGetIdleRunTimeCounter
    #define traceENTER_ulTaskGetIdleRunTimeCounter()
#endif

#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter
    #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn )
#endif

#ifndef traceENTER_ulTaskGetIdleRunTimePercent
    #define traceENTER_ulTaskGetIdleRunTimePercent()
#endif

#ifndef traceRETURN_ulTaskGetIdleRunTimePercent
    #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn )
#endif

#ifndef traceENTER_xTaskGetMPUSettings
    #define traceENTER_xTaskGetMPUSettings( xTask )
#endif

#ifndef traceRETURN_xTaskGetMPUSettings
    #define traceRETURN_xTaskGetMPUSettings( xMPUSettings )
#endif

#ifndef traceENTER_xStreamBufferGenericCreate
    #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback )
#endif

#ifndef traceRETURN_xStreamBufferGenericCreate
    #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory )
#endif

#ifndef traceENTER_xStreamBufferGenericCreateStatic
    #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback )
#endif

#ifndef traceRETURN_xStreamBufferGenericCreateStatic
    #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn )
#endif

#ifndef traceENTER_xStreamBufferGetStaticBuffers
    #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferGetStaticBuffers
    #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn )
#endif

#ifndef traceENTER_vStreamBufferDelete
    #define traceENTER_vStreamBufferDelete( xStreamBuffer )
#endif

#ifndef traceRETURN_vStreamBufferDelete
    #define traceRETURN_vStreamBufferDelete()
#endif

#ifndef traceENTER_xStreamBufferReset
    #define traceENTER_xStreamBufferReset( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferReset
    #define traceRETURN_xStreamBufferReset( xReturn )
#endif

#ifndef traceENTER_xStreamBufferResetFromISR
    #define traceENTER_xStreamBufferResetFromISR( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferResetFromISR
    #define traceRETURN_xStreamBufferResetFromISR( xReturn )
#endif

#ifndef traceENTER_xStreamBufferSetTriggerLevel
    #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel )
#endif

#ifndef traceRETURN_xStreamBufferSetTriggerLevel
    #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn )
#endif

#ifndef traceENTER_xStreamBufferSpacesAvailable
    #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferSpacesAvailable
    #define traceRETURN_xStreamBufferSpacesAvailable( xSpace )
#endif

#ifndef traceENTER_xStreamBufferBytesAvailable
    #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferBytesAvailable
    #define traceRETURN_xStreamBufferBytesAvailable( xReturn )
#endif

#ifndef traceENTER_xStreamBufferSend
    #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
#endif

#ifndef traceRETURN_xStreamBufferSend
    #define traceRETURN_xStreamBufferSend( xReturn )
#endif

#ifndef traceENTER_xStreamBufferSendFromISR
    #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xStreamBufferSendFromISR
    #define traceRETURN_xStreamBufferSendFromISR( xReturn )
#endif

#ifndef traceENTER_xStreamBufferReceive
    #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
#endif

#ifndef traceRETURN_xStreamBufferReceive
    #define traceRETURN_xStreamBufferReceive( xReceivedLength )
#endif

#ifndef traceENTER_xStreamBufferNextMessageLengthBytes
    #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes
    #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn )
#endif

#ifndef traceENTER_xStreamBufferReceiveFromISR
    #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xStreamBufferReceiveFromISR
    #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength )
#endif

#ifndef traceENTER_xStreamBufferIsEmpty
    #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferIsEmpty
    #define traceRETURN_xStreamBufferIsEmpty( xReturn )
#endif

#ifndef traceENTER_xStreamBufferIsFull
    #define traceENTER_xStreamBufferIsFull( xStreamBuffer )
#endif

#ifndef traceRETURN_xStreamBufferIsFull
    #define traceRETURN_xStreamBufferIsFull( xReturn )
#endif

#ifndef traceENTER_xStreamBufferSendCompletedFromISR
    #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xStreamBufferSendCompletedFromISR
    #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn )
#endif

#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR
    #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken )
#endif

#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR
    #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn )
#endif

#ifndef traceENTER_uxStreamBufferGetStreamBufferNotificationIndex
    #define traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer )
#endif

#ifndef traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex
    #define traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( uxNotificationIndex )
#endif

#ifndef traceENTER_vStreamBufferSetStreamBufferNotificationIndex
    #define traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex )
#endif

#ifndef traceRETURN_vStreamBufferSetStreamBufferNotificationIndex
    #define traceRETURN_vStreamBufferSetStreamBufferNotificationIndex()
#endif

#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber
    #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer )
#endif

#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber
    #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber )
#endif

#ifndef traceENTER_vStreamBufferSetStreamBufferNumber
    #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber )
#endif

#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber
    #define traceRETURN_vStreamBufferSetStreamBufferNumber()
#endif

#ifndef traceENTER_ucStreamBufferGetStreamBufferType
    #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer )
#endif

#ifndef traceRETURN_ucStreamBufferGetStreamBufferType
    #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType )
#endif

#ifndef traceENTER_vListInitialise
    #define traceENTER_vListInitialise( pxList )
#endif

#ifndef traceRETURN_vListInitialise
    #define traceRETURN_vListInitialise()
#endif

#ifndef traceENTER_vListInitialiseItem
    #define traceENTER_vListInitialiseItem( pxItem )
#endif

#ifndef traceRETURN_vListInitialiseItem
    #define traceRETURN_vListInitialiseItem()
#endif

#ifndef traceENTER_vListInsertEnd
    #define traceENTER_vListInsertEnd( pxList, pxNewListItem )
#endif

#ifndef traceRETURN_vListInsertEnd
    #define traceRETURN_vListInsertEnd()
#endif

#ifndef traceENTER_vListInsert
    #define traceENTER_vListInsert( pxList, pxNewListItem )
#endif

#ifndef traceRETURN_vListInsert
    #define traceRETURN_vListInsert()
#endif

#ifndef traceENTER_uxListRemove
    #define traceENTER_uxListRemove( pxItemToRemove )
#endif

#ifndef traceRETURN_uxListRemove
    #define traceRETURN_uxListRemove( uxNumberOfItems )
#endif

#ifndef traceENTER_xCoRoutineCreate
    #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex )
#endif

#ifndef traceRETURN_xCoRoutineCreate
    #define traceRETURN_xCoRoutineCreate( xReturn )
#endif

#ifndef traceENTER_vCoRoutineAddToDelayedList
    #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList )
#endif

#ifndef traceRETURN_vCoRoutineAddToDelayedList
    #define traceRETURN_vCoRoutineAddToDelayedList()
#endif

#ifndef traceENTER_vCoRoutineSchedule
    #define traceENTER_vCoRoutineSchedule()
#endif

#ifndef traceRETURN_vCoRoutineSchedule
    #define traceRETURN_vCoRoutineSchedule()
#endif

#ifndef traceENTER_xCoRoutineRemoveFromEventList
    #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList )
#endif

#ifndef traceRETURN_xCoRoutineRemoveFromEventList
    #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn )
#endif

#ifndef configGENERATE_RUN_TIME_STATS
    #define configGENERATE_RUN_TIME_STATS    0
#endif

#if ( configGENERATE_RUN_TIME_STATS == 1 )

    #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
        #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
    #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */

    #ifndef portGET_RUN_TIME_COUNTER_VALUE
        #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
            #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
        #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
    #endif /* portGET_RUN_TIME_COUNTER_VALUE */

#endif /* configGENERATE_RUN_TIME_STATS */

#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
#endif

#ifndef portPRIVILEGE_BIT
    #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )
#endif

#ifndef portYIELD_WITHIN_API
    #define portYIELD_WITHIN_API    portYIELD
#endif

#ifndef portSUPPRESS_TICKS_AND_SLEEP
    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
#endif

#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
    #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP    2
#endif

#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
    #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
#endif

#ifndef configUSE_TICKLESS_IDLE
    #define configUSE_TICKLESS_IDLE    0
#endif

#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
    #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
#endif

#ifndef configPRE_SLEEP_PROCESSING
    #define configPRE_SLEEP_PROCESSING( x )
#endif

#ifndef configPOST_SLEEP_PROCESSING
    #define configPOST_SLEEP_PROCESSING( x )
#endif

#ifndef configUSE_QUEUE_SETS
    #define configUSE_QUEUE_SETS    0
#endif

#ifndef portTASK_USES_FLOATING_POINT
    #define portTASK_USES_FLOATING_POINT()
#endif

#ifndef portALLOCATE_SECURE_CONTEXT
    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
#endif

#ifndef portDONT_DISCARD
    #define portDONT_DISCARD
#endif

#ifndef configUSE_TIME_SLICING
    #define configUSE_TIME_SLICING    1
#endif

#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
    #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
#endif

#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
    #define configUSE_STATS_FORMATTING_FUNCTIONS    0
#endif

#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
#endif

#ifndef configUSE_TRACE_FACILITY
    #define configUSE_TRACE_FACILITY    0
#endif

#ifndef mtCOVERAGE_TEST_MARKER
    #define mtCOVERAGE_TEST_MARKER()
#endif

#ifndef mtCOVERAGE_TEST_DELAY
    #define mtCOVERAGE_TEST_DELAY()
#endif

#ifndef portASSERT_IF_IN_ISR
    #define portASSERT_IF_IN_ISR()
#endif

#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
#endif

#ifndef configAPPLICATION_ALLOCATED_HEAP
    #define configAPPLICATION_ALLOCATED_HEAP    0
#endif

#ifndef configENABLE_HEAP_PROTECTOR
    #define configENABLE_HEAP_PROTECTOR    0
#endif

#ifndef configUSE_TASK_NOTIFICATIONS
    #define configUSE_TASK_NOTIFICATIONS    1
#endif

#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES
    #define configTASK_NOTIFICATION_ARRAY_ENTRIES    1
#endif

#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1
    #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1
#endif

#ifndef configUSE_POSIX_ERRNO
    #define configUSE_POSIX_ERRNO    0
#endif

#ifndef configUSE_SB_COMPLETED_CALLBACK

/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */
    #define configUSE_SB_COMPLETED_CALLBACK    0
#endif

#ifndef portTICK_TYPE_IS_ATOMIC
    #define portTICK_TYPE_IS_ATOMIC    0
#endif

#ifndef configSUPPORT_STATIC_ALLOCATION
    /* Defaults to 0 for backward compatibility. */
    #define configSUPPORT_STATIC_ALLOCATION    0
#endif

#ifndef configKERNEL_PROVIDED_STATIC_MEMORY
    #define configKERNEL_PROVIDED_STATIC_MEMORY    0
#endif

#ifndef configSUPPORT_DYNAMIC_ALLOCATION
    /* Defaults to 1 for backward compatibility. */
    #define configSUPPORT_DYNAMIC_ALLOCATION    1
#endif

#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) )
    #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1.
#endif

#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )
    #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) )
        #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1.  Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h.
    #endif
#endif

#ifndef configSTATS_BUFFER_MAX_LENGTH
    #define configSTATS_BUFFER_MAX_LENGTH    0xFFFF
#endif

#ifndef configSTACK_DEPTH_TYPE

/* Defaults to StackType_t for backward compatibility, but can be overridden
 * in FreeRTOSConfig.h if StackType_t is too restrictive. */
    #define configSTACK_DEPTH_TYPE    StackType_t
#endif

#ifndef configRUN_TIME_COUNTER_TYPE

/* Defaults to uint32_t for backward compatibility, but can be overridden in
 * FreeRTOSConfig.h if uint32_t is too restrictive. */

    #define configRUN_TIME_COUNTER_TYPE    uint32_t
#endif

#ifndef configMESSAGE_BUFFER_LENGTH_TYPE

/* Defaults to size_t for backward compatibility, but can be overridden
 * in FreeRTOSConfig.h if lengths will always be less than the number of bytes
 * in a size_t. */
    #define configMESSAGE_BUFFER_LENGTH_TYPE    size_t
#endif

/* Sanity check the configuration. */
#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
    #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
#endif

#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
    #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
#endif

#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
    #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable
#endif

#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
    #error configUSE_PREEMPTION must be set to 1 to use task preemption disable
#endif

#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) )
    #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS
#endif

#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) )
    #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS
#endif

#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) )
    #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS
#endif

#ifndef configINITIAL_TICK_COUNT
    #define configINITIAL_TICK_COUNT    0
#endif

#if ( portTICK_TYPE_IS_ATOMIC == 0 )

/* Either variables of tick type cannot be read atomically, or
 * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
 * the tick count is returned to the standard critical section macros. */
    #define portTICK_TYPE_ENTER_CRITICAL()                      portENTER_CRITICAL()
    #define portTICK_TYPE_EXIT_CRITICAL()                       portEXIT_CRITICAL()
    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         portSET_INTERRUPT_MASK_FROM_ISR()
    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
#else

/* The tick type can be read atomically, so critical sections used when the
 * tick count is returned can be defined away. */
    #define portTICK_TYPE_ENTER_CRITICAL()
    #define portTICK_TYPE_EXIT_CRITICAL()
    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         0
    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( void ) ( x )
#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */

/* Definitions to allow backward compatibility with FreeRTOS versions prior to
 * V8 if desired. */
#ifndef configENABLE_BACKWARD_COMPATIBILITY
    #define configENABLE_BACKWARD_COMPATIBILITY    1
#endif

#ifndef configPRINTF

/* configPRINTF() was not defined, so define it away to nothing.  To use
 * configPRINTF() then define it as follows (where MyPrintFunction() is
 * provided by the application writer):
 *
 * void MyPrintFunction(const char *pcFormat, ... );
 #define configPRINTF( X )   MyPrintFunction X
 *
 * Then call like a standard printf() function, but placing brackets around
 * all parameters so they are passed as a single parameter.  For example:
 * configPRINTF( ("Value = %d", MyVariable) ); */
    #define configPRINTF( X )
#endif

#ifndef configMAX

/* The application writer has not provided their own MAX macro, so define
 * the following generic implementation. */
    #define configMAX( a, b )    ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
#endif

#ifndef configMIN

/* The application writer has not provided their own MIN macro, so define
 * the following generic implementation. */
    #define configMIN( a, b )    ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
#endif

#if configENABLE_BACKWARD_COMPATIBILITY == 1
    #define eTaskStateGet                 eTaskGetState
    #define portTickType                  TickType_t
    #define xTaskHandle                   TaskHandle_t
    #define xQueueHandle                  QueueHandle_t
    #define xSemaphoreHandle              SemaphoreHandle_t
    #define xQueueSetHandle               QueueSetHandle_t
    #define xQueueSetMemberHandle         QueueSetMemberHandle_t
    #define xTimeOutType                  TimeOut_t
    #define xMemoryRegion                 MemoryRegion_t
    #define xTaskParameters               TaskParameters_t
    #define xTaskStatusType               TaskStatus_t
    #define xTimerHandle                  TimerHandle_t
    #define xCoRoutineHandle              CoRoutineHandle_t
    #define pdTASK_HOOK_CODE              TaskHookFunction_t
    #define portTICK_RATE_MS              portTICK_PERIOD_MS
    #define pcTaskGetTaskName             pcTaskGetName
    #define pcTimerGetTimerName           pcTimerGetName
    #define pcQueueGetQueueName           pcQueueGetName
    #define vTaskGetTaskInfo              vTaskGetInfo
    #define xTaskGetIdleRunTimeCounter    ulTaskGetIdleRunTimeCounter

/* Backward compatibility within the scheduler code only - these definitions
 * are not really required but are included for completeness. */
    #define tmrTIMER_CALLBACK             TimerCallbackFunction_t
    #define pdTASK_CODE                   TaskFunction_t
    #define xListItem                     ListItem_t
    #define xList                         List_t

/* For libraries that break the list data hiding, and access list structure
 * members directly (which is not supposed to be done). */
    #define pxContainer                   pvContainer
#endif /* configENABLE_BACKWARD_COMPATIBILITY */

#if ( configUSE_ALTERNATIVE_API != 0 )
    #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
#endif

/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
 * if floating point hardware is otherwise supported by the FreeRTOS port in use.
 * This constant is not supported by all FreeRTOS ports that include floating
 * point support. */
#ifndef configUSE_TASK_FPU_SUPPORT
    #define configUSE_TASK_FPU_SUPPORT    1
#endif

/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
 * currently used in ARMv8M ports. */
#ifndef configENABLE_MPU
    #define configENABLE_MPU    0
#endif

/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
 * currently used in ARMv8M ports. */
#ifndef configENABLE_FPU
    #define configENABLE_FPU    1
#endif

/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is
 * currently used in ARMv8M ports. */
#ifndef configENABLE_MVE
    #define configENABLE_MVE    0
#endif

/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
 * This is currently used in ARMv8M ports. */
#ifndef configENABLE_TRUSTZONE
    #define configENABLE_TRUSTZONE    1
#endif

/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
 * the Secure Side only. */
#ifndef configRUN_FREERTOS_SECURE_ONLY
    #define configRUN_FREERTOS_SECURE_ONLY    0
#endif

#ifndef configRUN_ADDITIONAL_TESTS
    #define configRUN_ADDITIONAL_TESTS    0
#endif

/* The following config allows infinite loop control. For example, control the
 * infinite loop in idle task function when performing unit tests. */
#ifndef configCONTROL_INFINITE_LOOP
    #define configCONTROL_INFINITE_LOOP()
#endif

/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
 * dynamically allocated RAM, in which case when any task is deleted it is known
 * that both the task's stack and TCB need to be freed.  Sometimes the
 * FreeRTOSConfig.h settings only allow a task to be created using statically
 * allocated RAM, in which case when any task is deleted it is known that neither
 * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
 * settings allow a task to be created using either statically or dynamically
 * allocated RAM, in which case a member of the TCB is used to record whether the
 * stack and/or TCB were allocated statically or dynamically, so when a task is
 * deleted the RAM that was allocated dynamically is freed again and no attempt is
 * made to free the RAM that was allocated statically.
 * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
 * task to be created using either statically or dynamically allocated RAM.  Note
 * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
 * a statically allocated stack and a dynamically allocated TCB.
 *
 * The following table lists various combinations of portUSING_MPU_WRAPPERS,
 * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
 * when it is possible to have both static and dynamic allocation:
 *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
 * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
 * |     |         |        |                             |                                   | Static Possible  |           |
 * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
 * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
 * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
 * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
 * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
 * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
 * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
 * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
 * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
 * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
 * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
 * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
 * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
 * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
 * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
 * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
 * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
 * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
 * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
 */
#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE                                                                                     \
    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )

/*
 * In line with software engineering best practice, FreeRTOS implements a strict
 * data hiding policy, so the real structures used by FreeRTOS to maintain the
 * state of tasks, queues, semaphores, etc. are not accessible to the application
 * code.  However, if the application writer wants to statically allocate such
 * an object then the size of the object needs to be known.  Dummy structures
 * that are guaranteed to have the same size and alignment requirements of the
 * real objects are used for this purpose.  The dummy list and list item
 * structures below are used for inclusion in such a dummy structure.
 */
struct xSTATIC_LIST_ITEM
{
    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
        TickType_t xDummy1;
    #endif
    TickType_t xDummy2;
    void * pvDummy3[ 4 ];
    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
        TickType_t xDummy4;
    #endif
};
typedef struct xSTATIC_LIST_ITEM StaticListItem_t;

#if ( configUSE_MINI_LIST_ITEM == 1 )
    /* See the comments above the struct xSTATIC_LIST_ITEM definition. */
    struct xSTATIC_MINI_LIST_ITEM
    {
        #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
            TickType_t xDummy1;
        #endif
        TickType_t xDummy2;
        void * pvDummy3[ 2 ];
    };
    typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */
    typedef struct xSTATIC_LIST_ITEM      StaticMiniListItem_t;
#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */

/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
typedef struct xSTATIC_LIST
{
    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
        TickType_t xDummy1;
    #endif
    UBaseType_t uxDummy2;
    void * pvDummy3;
    StaticMiniListItem_t xDummy4;
    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
        TickType_t xDummy5;
    #endif
} StaticList_t;

/*
 * In line with software engineering best practice, especially when supplying a
 * library that is likely to change in future versions, FreeRTOS implements a
 * strict data hiding policy.  This means the Task structure used internally by
 * FreeRTOS is not accessible to application code.  However, if the application
 * writer wants to statically allocate the memory required to create a task then
 * the size of the task object needs to be known.  The StaticTask_t structure
 * below is provided for this purpose.  Its sizes and alignment requirements are
 * guaranteed to match those of the genuine structure, no matter which
 * architecture is being used, and no matter how the values in FreeRTOSConfig.h
 * are set.  Its contents are somewhat obfuscated in the hope users will
 * recognise that it would be unwise to make direct use of the structure members.
 */
typedef struct xSTATIC_TCB
{
    void * pxDummy1;
    #if ( portUSING_MPU_WRAPPERS == 1 )
        xMPU_SETTINGS xDummy2;
    #endif
    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
        UBaseType_t uxDummy26;
    #endif
    StaticListItem_t xDummy3[ 2 ];
    UBaseType_t uxDummy5;
    void * pxDummy6;
    #if ( configNUMBER_OF_CORES > 1 )
        BaseType_t xDummy23;
        UBaseType_t uxDummy24;
    #endif
    uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
        BaseType_t xDummy25;
    #endif
    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
        void * pxDummy8;
    #endif
    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
        UBaseType_t uxDummy9;
    #endif
    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxDummy10[ 2 ];
    #endif
    #if ( configUSE_MUTEXES == 1 )
        UBaseType_t uxDummy12[ 2 ];
    #endif
    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
        void * pxDummy14;
    #endif
    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
        void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
    #endif
    #if ( configGENERATE_RUN_TIME_STATS == 1 )
        configRUN_TIME_COUNTER_TYPE ulDummy16;
    #endif
    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
        configTLS_BLOCK_TYPE xDummy17;
    #endif
    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
        uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
        uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
    #endif
    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
        uint8_t uxDummy20;
    #endif

    #if ( INCLUDE_xTaskAbortDelay == 1 )
        uint8_t ucDummy21;
    #endif
    #if ( configUSE_POSIX_ERRNO == 1 )
        int iDummy22;
    #endif
} StaticTask_t;

/*
 * In line with software engineering best practice, especially when supplying a
 * library that is likely to change in future versions, FreeRTOS implements a
 * strict data hiding policy.  This means the Queue structure used internally by
 * FreeRTOS is not accessible to application code.  However, if the application
 * writer wants to statically allocate the memory required to create a queue
 * then the size of the queue object needs to be known.  The StaticQueue_t
 * structure below is provided for this purpose.  Its sizes and alignment
 * requirements are guaranteed to match those of the genuine structure, no
 * matter which architecture is being used, and no matter how the values in
 * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
 * users will recognise that it would be unwise to make direct use of the
 * structure members.
 */
typedef struct xSTATIC_QUEUE
{
    void * pvDummy1[ 3 ];

    union
    {
        void * pvDummy2;
        UBaseType_t uxDummy2;
    } u;

    StaticList_t xDummy3[ 2 ];
    UBaseType_t uxDummy4[ 3 ];
    uint8_t ucDummy5[ 2 ];

    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
        uint8_t ucDummy6;
    #endif

    #if ( configUSE_QUEUE_SETS == 1 )
        void * pvDummy7;
    #endif

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxDummy8;
        uint8_t ucDummy9;
    #endif
} StaticQueue_t;
typedef StaticQueue_t StaticSemaphore_t;

/*
 * In line with software engineering best practice, especially when supplying a
 * library that is likely to change in future versions, FreeRTOS implements a
 * strict data hiding policy.  This means the event group structure used
 * internally by FreeRTOS is not accessible to application code.  However, if
 * the application writer wants to statically allocate the memory required to
 * create an event group then the size of the event group object needs to be
 * know.  The StaticEventGroup_t structure below is provided for this purpose.
 * Its sizes and alignment requirements are guaranteed to match those of the
 * genuine structure, no matter which architecture is being used, and no matter
 * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
 * obfuscated in the hope users will recognise that it would be unwise to make
 * direct use of the structure members.
 */
typedef struct xSTATIC_EVENT_GROUP
{
    TickType_t xDummy1;
    StaticList_t xDummy2;

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxDummy3;
    #endif

    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
        uint8_t ucDummy4;
    #endif
} StaticEventGroup_t;

/*
 * In line with software engineering best practice, especially when supplying a
 * library that is likely to change in future versions, FreeRTOS implements a
 * strict data hiding policy.  This means the software timer structure used
 * internally by FreeRTOS is not accessible to application code.  However, if
 * the application writer wants to statically allocate the memory required to
 * create a software timer then the size of the queue object needs to be known.
 * The StaticTimer_t structure below is provided for this purpose.  Its sizes
 * and alignment requirements are guaranteed to match those of the genuine
 * structure, no matter which architecture is being used, and no matter how the
 * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
 * the hope users will recognise that it would be unwise to make direct use of
 * the structure members.
 */
typedef struct xSTATIC_TIMER
{
    void * pvDummy1;
    StaticListItem_t xDummy2;
    TickType_t xDummy3;
    void * pvDummy5;
    TaskFunction_t pvDummy6;
    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxDummy7;
    #endif
    uint8_t ucDummy8;
} StaticTimer_t;

/*
 * In line with software engineering best practice, especially when supplying a
 * library that is likely to change in future versions, FreeRTOS implements a
 * strict data hiding policy.  This means the stream buffer structure used
 * internally by FreeRTOS is not accessible to application code.  However, if
 * the application writer wants to statically allocate the memory required to
 * create a stream buffer then the size of the stream buffer object needs to be
 * known.  The StaticStreamBuffer_t structure below is provided for this
 * purpose.  Its size and alignment requirements are guaranteed to match those
 * of the genuine structure, no matter which architecture is being used, and
 * no matter how the values in FreeRTOSConfig.h are set.  Its contents are
 * somewhat obfuscated in the hope users will recognise that it would be unwise
 * to make direct use of the structure members.
 */
typedef struct xSTATIC_STREAM_BUFFER
{
    size_t uxDummy1[ 4 ];
    void * pvDummy2[ 3 ];
    uint8_t ucDummy3;
    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxDummy4;
    #endif
    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        void * pvDummy5[ 2 ];
    #endif
    UBaseType_t uxDummy6;
} StaticStreamBuffer_t;

/* Message buffers are built on stream buffers. */
typedef StaticStreamBuffer_t StaticMessageBuffer_t;

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* INC_FREERTOS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
    #warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in a future release.
#endif

#include "stack_macros.h"


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/**
 * @file atomic.h
 * @brief FreeRTOS atomic operation support.
 *
 * This file implements atomic functions by disabling interrupts globally.
 * Implementations with architecture specific atomic instructions can be
 * provided under each compiler directory.
 *
 * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
 * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
 * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
 * atomic interface must not be used in ISRs on FreeRTOS ports that do not
 * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
 * because ISRs on these ports cannot be interrupted and therefore, do not need
 * atomics in ISRs.
 */

#ifndef ATOMIC_H
#define ATOMIC_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include atomic.h"
#endif

/* Standard includes. */
#include 

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/*
 * Port specific definitions -- entering/exiting critical section.
 * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
 *
 * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
 * ATOMIC_ENTER_CRITICAL().
 *
 */
#if ( portHAS_NESTED_INTERRUPTS == 1 )

/* Nested interrupt scheme is supported in this port. */
    #define ATOMIC_ENTER_CRITICAL() \
    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()

    #define ATOMIC_EXIT_CRITICAL() \
    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )

#else

/* Nested interrupt scheme is NOT supported in this port. */
    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()
    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()

#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */

/*
 * Port specific definition -- "always inline".
 * Inline is compiler specific, and may not always get inlined depending on your
 * optimization level.  Also, inline is considered as performance optimization
 * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
 * instead of resulting error, simply define it away.
 */
#ifndef portFORCE_INLINE
    #define portFORCE_INLINE
#endif

#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */
#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */

/*----------------------------- Swap && CAS ------------------------------*/

/**
 * Atomic compare-and-swap
 *
 * @brief Performs an atomic compare-and-swap operation on the specified values.
 *
 * @param[in, out] pulDestination  Pointer to memory location from where value is
 *                               to be loaded and checked.
 * @param[in] ulExchange         If condition meets, write this value to memory.
 * @param[in] ulComparand        Swap condition.
 *
 * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
 *
 * @note This function only swaps *pulDestination with ulExchange, if previous
 *       *pulDestination value equals ulComparand.
 */
static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
                                                            uint32_t ulExchange,
                                                            uint32_t ulComparand )
{
    uint32_t ulReturnValue;

    ATOMIC_ENTER_CRITICAL();
    {
        if( *pulDestination == ulComparand )
        {
            *pulDestination = ulExchange;
            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
        }
        else
        {
            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
        }
    }
    ATOMIC_EXIT_CRITICAL();

    return ulReturnValue;
}
/*-----------------------------------------------------------*/

/**
 * Atomic swap (pointers)
 *
 * @brief Atomically sets the address pointed to by *ppvDestination to the value
 *        of *pvExchange.
 *
 * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
 *                                 value is to be loaded and written back to.
 * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
 *
 * @return The initial value of *ppvDestination.
 */
static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
                                                        void * pvExchange )
{
    void * pReturnValue;

    ATOMIC_ENTER_CRITICAL();
    {
        pReturnValue = *ppvDestination;
        *ppvDestination = pvExchange;
    }
    ATOMIC_EXIT_CRITICAL();

    return pReturnValue;
}
/*-----------------------------------------------------------*/

/**
 * Atomic compare-and-swap (pointers)
 *
 * @brief Performs an atomic compare-and-swap operation on the specified pointer
 *        values.
 *
 * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
 *                                 value is to be loaded and checked.
 * @param[in] pvExchange           If condition meets, write this value to memory.
 * @param[in] pvComparand          Swap condition.
 *
 * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
 *
 * @note This function only swaps *ppvDestination with pvExchange, if previous
 *       *ppvDestination value equals pvComparand.
 */
static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
                                                                    void * pvExchange,
                                                                    void * pvComparand )
{
    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;

    ATOMIC_ENTER_CRITICAL();
    {
        if( *ppvDestination == pvComparand )
        {
            *ppvDestination = pvExchange;
            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
        }
    }
    ATOMIC_EXIT_CRITICAL();

    return ulReturnValue;
}


/*----------------------------- Arithmetic ------------------------------*/

/**
 * Atomic add
 *
 * @brief Atomically adds count to the value of the specified pointer points to.
 *
 * @param[in,out] pulAddend  Pointer to memory location from where value is to be
 *                         loaded and written back to.
 * @param[in] ulCount      Value to be added to *pulAddend.
 *
 * @return previous *pulAddend value.
 */
static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
                                                 uint32_t ulCount )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulAddend;
        *pulAddend += ulCount;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic subtract
 *
 * @brief Atomically subtracts count from the value of the specified pointer
 *        pointers to.
 *
 * @param[in,out] pulAddend  Pointer to memory location from where value is to be
 *                         loaded and written back to.
 * @param[in] ulCount      Value to be subtract from *pulAddend.
 *
 * @return previous *pulAddend value.
 */
static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
                                                      uint32_t ulCount )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulAddend;
        *pulAddend -= ulCount;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic increment
 *
 * @brief Atomically increments the value of the specified pointer points to.
 *
 * @param[in,out] pulAddend  Pointer to memory location from where value is to be
 *                         loaded and written back to.
 *
 * @return *pulAddend value before increment.
 */
static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulAddend;
        *pulAddend += 1;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic decrement
 *
 * @brief Atomically decrements the value of the specified pointer points to
 *
 * @param[in,out] pulAddend  Pointer to memory location from where value is to be
 *                         loaded and written back to.
 *
 * @return *pulAddend value before decrement.
 */
static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulAddend;
        *pulAddend -= 1;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}

/*----------------------------- Bitwise Logical ------------------------------*/

/**
 * Atomic OR
 *
 * @brief Performs an atomic OR operation on the specified values.
 *
 * @param [in, out] pulDestination  Pointer to memory location from where value is
 *                                to be loaded and written back to.
 * @param [in] ulValue            Value to be ORed with *pulDestination.
 *
 * @return The original value of *pulDestination.
 */
static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
                                                uint32_t ulValue )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulDestination;
        *pulDestination |= ulValue;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic AND
 *
 * @brief Performs an atomic AND operation on the specified values.
 *
 * @param [in, out] pulDestination  Pointer to memory location from where value is
 *                                to be loaded and written back to.
 * @param [in] ulValue            Value to be ANDed with *pulDestination.
 *
 * @return The original value of *pulDestination.
 */
static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
                                                 uint32_t ulValue )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulDestination;
        *pulDestination &= ulValue;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic NAND
 *
 * @brief Performs an atomic NAND operation on the specified values.
 *
 * @param [in, out] pulDestination  Pointer to memory location from where value is
 *                                to be loaded and written back to.
 * @param [in] ulValue            Value to be NANDed with *pulDestination.
 *
 * @return The original value of *pulDestination.
 */
static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
                                                  uint32_t ulValue )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulDestination;
        *pulDestination = ~( ulCurrent & ulValue );
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}
/*-----------------------------------------------------------*/

/**
 * Atomic XOR
 *
 * @brief Performs an atomic XOR operation on the specified values.
 *
 * @param [in, out] pulDestination  Pointer to memory location from where value is
 *                                to be loaded and written back to.
 * @param [in] ulValue            Value to be XORed with *pulDestination.
 *
 * @return The original value of *pulDestination.
 */
static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
                                                 uint32_t ulValue )
{
    uint32_t ulCurrent;

    ATOMIC_ENTER_CRITICAL();
    {
        ulCurrent = *pulDestination;
        *pulDestination ^= ulValue;
    }
    ATOMIC_EXIT_CRITICAL();

    return ulCurrent;
}

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* ATOMIC_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef CO_ROUTINE_H
#define CO_ROUTINE_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include croutine.h"
#endif

#include "list.h"

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/* Used to hide the implementation of the co-routine control block.  The
 * control block structure however has to be included in the header due to
 * the macro implementation of the co-routine functionality. */
typedef void * CoRoutineHandle_t;

/* Defines the prototype to which co-routine functions must conform. */
typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle,
                                   UBaseType_t uxIndex );

typedef struct corCoRoutineControlBlock
{
    crCOROUTINE_CODE pxCoRoutineFunction;
    ListItem_t xGenericListItem; /**< List item used to place the CRCB in ready and blocked queues. */
    ListItem_t xEventListItem;   /**< List item used to place the CRCB in event lists. */
    UBaseType_t uxPriority;      /**< The priority of the co-routine in relation to other co-routines. */
    UBaseType_t uxIndex;         /**< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
    uint16_t uxState;            /**< Used internally by the co-routine implementation. */
} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */

/**
 * croutine. h
 * @code{c}
 * BaseType_t xCoRoutineCreate(
 *                               crCOROUTINE_CODE pxCoRoutineCode,
 *                               UBaseType_t uxPriority,
 *                               UBaseType_t uxIndex
 *                             );
 * @endcode
 *
 * Create a new co-routine and add it to the list of co-routines that are
 * ready to run.
 *
 * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
 * functions require special syntax - see the co-routine section of the WEB
 * documentation for more information.
 *
 * @param uxPriority The priority with respect to other co-routines at which
 *  the co-routine will run.
 *
 * @param uxIndex Used to distinguish between different co-routines that
 * execute the same function.  See the example below and the co-routine section
 * of the WEB documentation for further information.
 *
 * @return pdPASS if the co-routine was successfully created and added to a ready
 * list, otherwise an error code defined with ProjDefs.h.
 *
 * Example usage:
 * @code{c}
 * // Co-routine to be created.
 * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * // This may not be necessary for const variables.
 * static const char cLedToFlash[ 2 ] = { 5, 6 };
 * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
 *
 *   // Must start every co-routine with a call to crSTART();
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *       // This co-routine just delays for a fixed period, then toggles
 *       // an LED.  Two co-routines are created using this function, so
 *       // the uxIndex parameter is used to tell the co-routine which
 *       // LED to flash and how int32_t to delay.  This assumes xQueue has
 *       // already been created.
 *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
 *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
 *   }
 *
 *   // Must end every co-routine with a call to crEND();
 *   crEND();
 * }
 *
 * // Function that creates two co-routines.
 * void vOtherFunction( void )
 * {
 * uint8_t ucParameterToPass;
 * TaskHandle_t xHandle;
 *
 *   // Create two co-routines at priority 0.  The first is given index 0
 *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
 *   // is given index 1 so toggles LED 6 every 400 ticks.
 *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
 *   {
 *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
 *   }
 * }
 * @endcode
 * \defgroup xCoRoutineCreate xCoRoutineCreate
 * \ingroup Tasks
 */
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
                             UBaseType_t uxPriority,
                             UBaseType_t uxIndex );


/**
 * croutine. h
 * @code{c}
 * void vCoRoutineSchedule( void );
 * @endcode
 *
 * Run a co-routine.
 *
 * vCoRoutineSchedule() executes the highest priority co-routine that is able
 * to run.  The co-routine will execute until it either blocks, yields or is
 * preempted by a task.  Co-routines execute cooperatively so one
 * co-routine cannot be preempted by another, but can be preempted by a task.
 *
 * If an application comprises of both tasks and co-routines then
 * vCoRoutineSchedule should be called from the idle task (in an idle task
 * hook).
 *
 * Example usage:
 * @code{c}
 * // This idle task hook will schedule a co-routine each time it is called.
 * // The rest of the idle task will execute between co-routine calls.
 * void vApplicationIdleHook( void )
 * {
 *  vCoRoutineSchedule();
 * }
 *
 * // Alternatively, if you do not require any other part of the idle task to
 * // execute, the idle task hook can call vCoRoutineSchedule() within an
 * // infinite loop.
 * void vApplicationIdleHook( void )
 * {
 *  for( ;; )
 *  {
 *      vCoRoutineSchedule();
 *  }
 * }
 * @endcode
 * \defgroup vCoRoutineSchedule vCoRoutineSchedule
 * \ingroup Tasks
 */
void vCoRoutineSchedule( void );

/**
 * croutine. h
 * @code{c}
 * crSTART( CoRoutineHandle_t xHandle );
 * @endcode
 *
 * This macro MUST always be called at the start of a co-routine function.
 *
 * Example usage:
 * @code{c}
 * // Co-routine to be created.
 * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * static int32_t ulAVariable;
 *
 *   // Must start every co-routine with a call to crSTART();
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *        // Co-routine functionality goes here.
 *   }
 *
 *   // Must end every co-routine with a call to crEND();
 *   crEND();
 * }
 * @endcode
 * \defgroup crSTART crSTART
 * \ingroup Tasks
 */
#define crSTART( pxCRCB )                            \
    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
        case 0:

/**
 * croutine. h
 * @code{c}
 * crEND();
 * @endcode
 *
 * This macro MUST always be called at the end of a co-routine function.
 *
 * Example usage:
 * @code{c}
 * // Co-routine to be created.
 * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * static int32_t ulAVariable;
 *
 *   // Must start every co-routine with a call to crSTART();
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *        // Co-routine functionality goes here.
 *   }
 *
 *   // Must end every co-routine with a call to crEND();
 *   crEND();
 * }
 * @endcode
 * \defgroup crSTART crSTART
 * \ingroup Tasks
 */
#define crEND()    }

/*
 * These macros are intended for internal use by the co-routine implementation
 * only.  The macros should not be used directly by application writers.
 */
#define crSET_STATE0( xHandle )                                       \
    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
    case ( __LINE__ * 2 ):
#define crSET_STATE1( xHandle )                                               \
    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
    case ( ( __LINE__ * 2 ) + 1 ):

/**
 * croutine. h
 * @code{c}
 * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
 * @endcode
 *
 * Delay a co-routine for a fixed period of time.
 *
 * crDELAY can only be called from the co-routine function itself - not
 * from within a function called by the co-routine function.  This is because
 * co-routines do not maintain their own stack.
 *
 * @param xHandle The handle of the co-routine to delay.  This is the xHandle
 * parameter of the co-routine function.
 *
 * @param xTickToDelay The number of ticks that the co-routine should delay
 * for.  The actual amount of time this equates to is defined by
 * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
 * can be used to convert ticks to milliseconds.
 *
 * Example usage:
 * @code{c}
 * // Co-routine to be created.
 * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * // This may not be necessary for const variables.
 * // We are to delay for 200ms.
 * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
 *
 *   // Must start every co-routine with a call to crSTART();
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *      // Delay for 200ms.
 *      crDELAY( xHandle, xDelayTime );
 *
 *      // Do something here.
 *   }
 *
 *   // Must end every co-routine with a call to crEND();
 *   crEND();
 * }
 * @endcode
 * \defgroup crDELAY crDELAY
 * \ingroup Tasks
 */
#define crDELAY( xHandle, xTicksToDelay )                          \
    do {                                                           \
        if( ( xTicksToDelay ) > 0 )                                \
        {                                                          \
            vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
        }                                                          \
        crSET_STATE0( ( xHandle ) );                               \
    } while( 0 )

/**
 * @code{c}
 * crQUEUE_SEND(
 *                CoRoutineHandle_t xHandle,
 *                QueueHandle_t pxQueue,
 *                void *pvItemToQueue,
 *                TickType_t xTicksToWait,
 *                BaseType_t *pxResult
 *           )
 * @endcode
 *
 * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
 * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
 *
 * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
 * xQueueSend() and xQueueReceive() can only be used from tasks.
 *
 * crQUEUE_SEND can only be called from the co-routine function itself - not
 * from within a function called by the co-routine function.  This is because
 * co-routines do not maintain their own stack.
 *
 * See the co-routine section of the WEB documentation for information on
 * passing data between tasks and co-routines and between ISR's and
 * co-routines.
 *
 * @param xHandle The handle of the calling co-routine.  This is the xHandle
 * parameter of the co-routine function.
 *
 * @param pxQueue The handle of the queue on which the data will be posted.
 * The handle is obtained as the return value when the queue is created using
 * the xQueueCreate() API function.
 *
 * @param pvItemToQueue A pointer to the data being posted onto the queue.
 * The number of bytes of each queued item is specified when the queue is
 * created.  This number of bytes is copied from pvItemToQueue into the queue
 * itself.
 *
 * @param xTickToDelay The number of ticks that the co-routine should block
 * to wait for space to become available on the queue, should space not be
 * available immediately. The actual amount of time this equates to is defined
 * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
 * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
 * below).
 *
 * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
 * data was successfully posted onto the queue, otherwise it will be set to an
 * error defined within ProjDefs.h.
 *
 * Example usage:
 * @code{c}
 * // Co-routine function that blocks for a fixed period then posts a number onto
 * // a queue.
 * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * static BaseType_t xNumberToPost = 0;
 * static BaseType_t xResult;
 *
 *  // Co-routines must begin with a call to crSTART().
 *  crSTART( xHandle );
 *
 *  for( ;; )
 *  {
 *      // This assumes the queue has already been created.
 *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
 *
 *      if( xResult != pdPASS )
 *      {
 *          // The message was not posted!
 *      }
 *
 *      // Increment the number to be posted onto the queue.
 *      xNumberToPost++;
 *
 *      // Delay for 100 ticks.
 *      crDELAY( xHandle, 100 );
 *  }
 *
 *  // Co-routines must end with a call to crEND().
 *  crEND();
 * }
 * @endcode
 * \defgroup crQUEUE_SEND crQUEUE_SEND
 * \ingroup Tasks
 */
#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \
    do {                                                                                  \
        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \
        {                                                                                 \
            crSET_STATE0( ( xHandle ) );                                                  \
            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \
        }                                                                                 \
        if( *pxResult == errQUEUE_YIELD )                                                 \
        {                                                                                 \
            crSET_STATE1( ( xHandle ) );                                                  \
            *pxResult = pdPASS;                                                           \
        }                                                                                 \
    } while( 0 )

/**
 * croutine. h
 * @code{c}
 * crQUEUE_RECEIVE(
 *                   CoRoutineHandle_t xHandle,
 *                   QueueHandle_t pxQueue,
 *                   void *pvBuffer,
 *                   TickType_t xTicksToWait,
 *                   BaseType_t *pxResult
 *               )
 * @endcode
 *
 * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
 * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
 *
 * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
 * xQueueSend() and xQueueReceive() can only be used from tasks.
 *
 * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
 * from within a function called by the co-routine function.  This is because
 * co-routines do not maintain their own stack.
 *
 * See the co-routine section of the WEB documentation for information on
 * passing data between tasks and co-routines and between ISR's and
 * co-routines.
 *
 * @param xHandle The handle of the calling co-routine.  This is the xHandle
 * parameter of the co-routine function.
 *
 * @param pxQueue The handle of the queue from which the data will be received.
 * The handle is obtained as the return value when the queue is created using
 * the xQueueCreate() API function.
 *
 * @param pvBuffer The buffer into which the received item is to be copied.
 * The number of bytes of each queued item is specified when the queue is
 * created.  This number of bytes is copied into pvBuffer.
 *
 * @param xTickToDelay The number of ticks that the co-routine should block
 * to wait for data to become available from the queue, should data not be
 * available immediately. The actual amount of time this equates to is defined
 * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
 * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
 * crQUEUE_SEND example).
 *
 * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
 * data was successfully retrieved from the queue, otherwise it will be set to
 * an error code as defined within ProjDefs.h.
 *
 * Example usage:
 * @code{c}
 * // A co-routine receives the number of an LED to flash from a queue.  It
 * // blocks on the queue until the number is received.
 * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
 * static BaseType_t xResult;
 * static UBaseType_t uxLEDToFlash;
 *
 *  // All co-routines must start with a call to crSTART().
 *  crSTART( xHandle );
 *
 *  for( ;; )
 *  {
 *      // Wait for data to become available on the queue.
 *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
 *
 *      if( xResult == pdPASS )
 *      {
 *          // We received the LED to flash - flash it!
 *          vParTestToggleLED( uxLEDToFlash );
 *      }
 *  }
 *
 *  crEND();
 * }
 * @endcode
 * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
 * \ingroup Tasks
 */
#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \
    do {                                                                                \
        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \
        {                                                                               \
            crSET_STATE0( ( xHandle ) );                                                \
            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \
        }                                                                               \
        if( *( pxResult ) == errQUEUE_YIELD )                                           \
        {                                                                               \
            crSET_STATE1( ( xHandle ) );                                                \
            *( pxResult ) = pdPASS;                                                     \
        }                                                                               \
    } while( 0 )

/**
 * croutine. h
 * @code{c}
 * crQUEUE_SEND_FROM_ISR(
 *                          QueueHandle_t pxQueue,
 *                          void *pvItemToQueue,
 *                          BaseType_t xCoRoutinePreviouslyWoken
 *                     )
 * @endcode
 *
 * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
 * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
 * functions used by tasks.
 *
 * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
 * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
 * xQueueReceiveFromISR() can only be used to pass data between a task and and
 * ISR.
 *
 * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
 * that is being used from within a co-routine.
 *
 * See the co-routine section of the WEB documentation for information on
 * passing data between tasks and co-routines and between ISR's and
 * co-routines.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
 * the same queue multiple times from a single interrupt.  The first call
 * should always pass in pdFALSE.  Subsequent calls should pass in
 * the value returned from the previous call.
 *
 * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
 * used by the ISR to determine if a context switch may be required following
 * the ISR.
 *
 * Example usage:
 * @code{c}
 * // A co-routine that blocks on a queue waiting for characters to be received.
 * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * char cRxedChar;
 * BaseType_t xResult;
 *
 *   // All co-routines must start with a call to crSTART().
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *       // Wait for data to become available on the queue.  This assumes the
 *       // queue xCommsRxQueue has already been created!
 *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
 *
 *       // Was a character received?
 *       if( xResult == pdPASS )
 *       {
 *           // Process the character here.
 *       }
 *   }
 *
 *   // All co-routines must end with a call to crEND().
 *   crEND();
 * }
 *
 * // An ISR that uses a queue to send characters received on a serial port to
 * // a co-routine.
 * void vUART_ISR( void )
 * {
 * char cRxedChar;
 * BaseType_t xCRWokenByPost = pdFALSE;
 *
 *   // We loop around reading characters until there are none left in the UART.
 *   while( UART_RX_REG_NOT_EMPTY() )
 *   {
 *       // Obtain the character from the UART.
 *       cRxedChar = UART_RX_REG;
 *
 *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
 *       // the first time around the loop.  If the post causes a co-routine
 *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
 *       // In this manner we can ensure that if more than one co-routine is
 *       // blocked on the queue only one is woken by this ISR no matter how
 *       // many characters are posted to the queue.
 *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
 *   }
 * }
 * @endcode
 * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
 * \ingroup Tasks
 */
#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )


/**
 * croutine. h
 * @code{c}
 * crQUEUE_SEND_FROM_ISR(
 *                          QueueHandle_t pxQueue,
 *                          void *pvBuffer,
 *                          BaseType_t * pxCoRoutineWoken
 *                     )
 * @endcode
 *
 * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
 * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
 * functions used by tasks.
 *
 * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
 * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
 * xQueueReceiveFromISR() can only be used to pass data between a task and and
 * ISR.
 *
 * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
 * from a queue that is being used from within a co-routine (a co-routine
 * posted to the queue).
 *
 * See the co-routine section of the WEB documentation for information on
 * passing data between tasks and co-routines and between ISR's and
 * co-routines.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvBuffer A pointer to a buffer into which the received item will be
 * placed.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from the queue into
 * pvBuffer.
 *
 * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
 * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
 * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
 * *pxCoRoutineWoken will remain unchanged.
 *
 * @return pdTRUE an item was successfully received from the queue, otherwise
 * pdFALSE.
 *
 * Example usage:
 * @code{c}
 * // A co-routine that posts a character to a queue then blocks for a fixed
 * // period.  The character is incremented each time.
 * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
 * {
 * // cChar holds its value while this co-routine is blocked and must therefore
 * // be declared static.
 * static char cCharToTx = 'a';
 * BaseType_t xResult;
 *
 *   // All co-routines must start with a call to crSTART().
 *   crSTART( xHandle );
 *
 *   for( ;; )
 *   {
 *       // Send the next character to the queue.
 *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
 *
 *       if( xResult == pdPASS )
 *       {
 *           // The character was successfully posted to the queue.
 *       }
 *       else
 *       {
 *          // Could not post the character to the queue.
 *       }
 *
 *       // Enable the UART Tx interrupt to cause an interrupt in this
 *       // hypothetical UART.  The interrupt will obtain the character
 *       // from the queue and send it.
 *       ENABLE_RX_INTERRUPT();
 *
 *       // Increment to the next character then block for a fixed period.
 *       // cCharToTx will maintain its value across the delay as it is
 *       // declared static.
 *       cCharToTx++;
 *       if( cCharToTx > 'x' )
 *       {
 *          cCharToTx = 'a';
 *       }
 *       crDELAY( 100 );
 *   }
 *
 *   // All co-routines must end with a call to crEND().
 *   crEND();
 * }
 *
 * // An ISR that uses a queue to receive characters to send on a UART.
 * void vUART_ISR( void )
 * {
 * char cCharToTx;
 * BaseType_t xCRWokenByPost = pdFALSE;
 *
 *   while( UART_TX_REG_EMPTY() )
 *   {
 *       // Are there any characters in the queue waiting to be sent?
 *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
 *       // is woken by the post - ensuring that only a single co-routine is
 *       // woken no matter how many times we go around this loop.
 *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
 *       {
 *           SEND_CHARACTER( cCharToTx );
 *       }
 *   }
 * }
 * @endcode
 * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
 * \ingroup Tasks
 */
#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )

/*
 * This function is intended for internal use by the co-routine macros only.
 * The macro nature of the co-routine implementation requires that the
 * prototype appears here.  The function should not be used by application
 * writers.
 *
 * Removes the current co-routine from its ready list and places it in the
 * appropriate delayed list.
 */
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
                                 List_t * pxEventList );

/*
 * This function is intended for internal use by the queue implementation only.
 * The function should not be used by application writers.
 *
 * Removes the highest priority co-routine from the event list and places it in
 * the pending ready list.
 */
BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );


/*
 * This function resets the internal state of the coroutine module. It must be
 * called by the application before restarting the scheduler.
 */
void vCoRoutineResetState( void ) PRIVILEGED_FUNCTION;

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* CO_ROUTINE_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef EVENT_GROUPS_H
#define EVENT_GROUPS_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
#endif

/* FreeRTOS includes. */
#include "timers.h"

/* The following bit fields convey control information in a task's event list
 * item value.  It is important they don't clash with the
 * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000U )
    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000U )
    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000U )
    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000U )
    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000U )
    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000U )
    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000U )
#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/**
 * An event group is a collection of bits to which an application can assign a
 * meaning.  For example, an application may create an event group to convey
 * the status of various CAN bus related events in which bit 0 might mean "A CAN
 * message has been received and is ready for processing", bit 1 might mean "The
 * application has queued a message that is ready for sending onto the CAN
 * network", and bit 2 might mean "It is time to send a SYNC message onto the
 * CAN network" etc.  A task can then test the bit values to see which events
 * are active, and optionally enter the Blocked state to wait for a specified
 * bit or a group of specified bits to be active.  To continue the CAN bus
 * example, a CAN controlling task can enter the Blocked state (and therefore
 * not consume any processing time) until either bit 0, bit 1 or bit 2 are
 * active, at which time the bit that was actually active would inform the task
 * which action it had to take (process a received message, send a message, or
 * send a SYNC).
 *
 * The event groups implementation contains intelligence to avoid race
 * conditions that would otherwise occur were an application to use a simple
 * variable for the same purpose.  This is particularly important with respect
 * to when a bit within an event group is to be cleared, and when bits have to
 * be set and then tested atomically - as is the case where event groups are
 * used to create a synchronisation point between multiple tasks (a
 * 'rendezvous').
 */



/**
 * event_groups.h
 *
 * Type by which event groups are referenced.  For example, a call to
 * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
 * be used as a parameter to other event group functions.
 *
 * \defgroup EventGroupHandle_t EventGroupHandle_t
 * \ingroup EventGroup
 */
struct EventGroupDef_t;
typedef struct EventGroupDef_t   * EventGroupHandle_t;

/*
 * The type that holds event bits always matches TickType_t - therefore the
 * number of bits it holds is set by configTICK_TYPE_WIDTH_IN_BITS (16 bits if set to 0,
 * 32 bits if set to 1, 64 bits if set to 2.
 *
 * \defgroup EventBits_t EventBits_t
 * \ingroup EventGroup
 */
typedef TickType_t               EventBits_t;

/**
 * event_groups.h
 * @code{c}
 * EventGroupHandle_t xEventGroupCreate( void );
 * @endcode
 *
 * Create a new event group.
 *
 * Internally, within the FreeRTOS implementation, event groups use a [small]
 * block of memory, in which the event group's structure is stored.  If an event
 * groups is created using xEventGroupCreate() then the required memory is
 * automatically dynamically allocated inside the xEventGroupCreate() function.
 * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
 * using xEventGroupCreateStatic() then the application writer must instead
 * provide the memory that will get used by the event group.
 * xEventGroupCreateStatic() therefore allows an event group to be created
 * without using any dynamic memory allocation.
 *
 * Although event groups are not related to ticks, for internal implementation
 * reasons the number of bits available for use in an event group is dependent
 * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h.  If
 * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit
 * 0 to bit 7).  If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has
 * 24 usable bits (bit 0 to bit 23).  If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then
 * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
 * is used to store event bits within an event group.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreate()
 * to be available.
 *
 * @return If the event group was created then a handle to the event group is
 * returned.  If there was insufficient FreeRTOS heap available to create the
 * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
 *
 * Example usage:
 * @code{c}
 *  // Declare a variable to hold the created event group.
 *  EventGroupHandle_t xCreatedEventGroup;
 *
 *  // Attempt to create the event group.
 *  xCreatedEventGroup = xEventGroupCreate();
 *
 *  // Was the event group created successfully?
 *  if( xCreatedEventGroup == NULL )
 *  {
 *      // The event group was not created because there was insufficient
 *      // FreeRTOS heap available.
 *  }
 *  else
 *  {
 *      // The event group was created.
 *  }
 * @endcode
 * \defgroup xEventGroupCreate xEventGroupCreate
 * \ingroup EventGroup
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
#endif

/**
 * event_groups.h
 * @code{c}
 * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
 * @endcode
 *
 * Create a new event group.
 *
 * Internally, within the FreeRTOS implementation, event groups use a [small]
 * block of memory, in which the event group's structure is stored.  If an event
 * groups is created using xEventGroupCreate() then the required memory is
 * automatically dynamically allocated inside the xEventGroupCreate() function.
 * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
 * using xEventGroupCreateStatic() then the application writer must instead
 * provide the memory that will get used by the event group.
 * xEventGroupCreateStatic() therefore allows an event group to be created
 * without using any dynamic memory allocation.
 *
 * Although event groups are not related to ticks, for internal implementation
 * reasons the number of bits available for use in an event group is dependent
 * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h.  If
 * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit
 * 0 to bit 7).  If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has
 * 24 usable bits (bit 0 to bit 23).  If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then
 * each event group has 56 usable bits (bit 0 to bit 53).  The EventBits_t type
 * is used to store event bits within an event group.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreateStatic()
 * to be available.
 *
 * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
 * StaticEventGroup_t, which will be then be used to hold the event group's data
 * structures, removing the need for the memory to be allocated dynamically.
 *
 * @return If the event group was created then a handle to the event group is
 * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
 *
 * Example usage:
 * @code{c}
 *  // StaticEventGroup_t is a publicly accessible structure that has the same
 *  // size and alignment requirements as the real event group structure.  It is
 *  // provided as a mechanism for applications to know the size of the event
 *  // group (which is dependent on the architecture and configuration file
 *  // settings) without breaking the strict data hiding policy by exposing the
 *  // real event group internals.  This StaticEventGroup_t variable is passed
 *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
 *  // the event group's data structures
 *  StaticEventGroup_t xEventGroupBuffer;
 *
 *  // Create the event group without dynamically allocating any memory.
 *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
 * @endcode
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
#endif

/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
 *                                      const EventBits_t uxBitsToWaitFor,
 *                                      const BaseType_t xClearOnExit,
 *                                      const BaseType_t xWaitForAllBits,
 *                                      const TickType_t xTicksToWait );
 * @endcode
 *
 * [Potentially] block to wait for one or more bits to be set within a
 * previously created event group.
 *
 * This function cannot be called from an interrupt.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupWaitBits()
 * to be available.
 *
 * @param xEventGroup The event group in which the bits are being tested.  The
 * event group must have previously been created using a call to
 * xEventGroupCreate().
 *
 * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
 * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
 * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
 * uxBitsToWaitFor to 0x07.  Etc.
 *
 * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
 * uxBitsToWaitFor that are set within the event group will be cleared before
 * xEventGroupWaitBits() returns if the wait condition was met (if the function
 * returns for a reason other than a timeout).  If xClearOnExit is set to
 * pdFALSE then the bits set in the event group are not altered when the call to
 * xEventGroupWaitBits() returns.
 *
 * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
 * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
 * are set or the specified block time expires.  If xWaitForAllBits is set to
 * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
 * in uxBitsToWaitFor is set or the specified block time expires.  The block
 * time is specified by the xTicksToWait parameter.
 *
 * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
 * for one/all (depending on the xWaitForAllBits value) of the bits specified by
 * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block
 * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
 *
 * @return The value of the event group at the time either the bits being waited
 * for became set, or the block time expired.  Test the return value to know
 * which bits were set.  If xEventGroupWaitBits() returned because its timeout
 * expired then not all the bits being waited for will be set.  If
 * xEventGroupWaitBits() returned because the bits it was waiting for were set
 * then the returned value is the event group value before any bits were
 * automatically cleared in the case that xClearOnExit parameter was set to
 * pdTRUE.
 *
 * Example usage:
 * @code{c}
 * #define BIT_0 ( 1 << 0 )
 * #define BIT_4 ( 1 << 4 )
 *
 * void aFunction( EventGroupHandle_t xEventGroup )
 * {
 * EventBits_t uxBits;
 * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
 *
 *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
 *      // the event group.  Clear the bits before exiting.
 *      uxBits = xEventGroupWaitBits(
 *                  xEventGroup,    // The event group being tested.
 *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
 *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
 *                  pdFALSE,        // Don't wait for both bits, either bit will do.
 *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
 *
 *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
 *      {
 *          // xEventGroupWaitBits() returned because both bits were set.
 *      }
 *      else if( ( uxBits & BIT_0 ) != 0 )
 *      {
 *          // xEventGroupWaitBits() returned because just BIT_0 was set.
 *      }
 *      else if( ( uxBits & BIT_4 ) != 0 )
 *      {
 *          // xEventGroupWaitBits() returned because just BIT_4 was set.
 *      }
 *      else
 *      {
 *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
 *          // without either BIT_0 or BIT_4 becoming set.
 *      }
 * }
 * @endcode
 * \defgroup xEventGroupWaitBits xEventGroupWaitBits
 * \ingroup EventGroup
 */
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                                 const EventBits_t uxBitsToWaitFor,
                                 const BaseType_t xClearOnExit,
                                 const BaseType_t xWaitForAllBits,
                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
 * @endcode
 *
 * Clear bits within an event group.  This function cannot be called from an
 * interrupt.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupClearBits()
 * to be available.
 *
 * @param xEventGroup The event group in which the bits are to be cleared.
 *
 * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
 * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
 * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
 *
 * @return The value of the event group before the specified bits were cleared.
 *
 * Example usage:
 * @code{c}
 * #define BIT_0 ( 1 << 0 )
 * #define BIT_4 ( 1 << 4 )
 *
 * void aFunction( EventGroupHandle_t xEventGroup )
 * {
 * EventBits_t uxBits;
 *
 *      // Clear bit 0 and bit 4 in xEventGroup.
 *      uxBits = xEventGroupClearBits(
 *                              xEventGroup,    // The event group being updated.
 *                              BIT_0 | BIT_4 );// The bits being cleared.
 *
 *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
 *      {
 *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
 *          // called.  Both will now be clear (not set).
 *      }
 *      else if( ( uxBits & BIT_0 ) != 0 )
 *      {
 *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
 *          // now be clear.
 *      }
 *      else if( ( uxBits & BIT_4 ) != 0 )
 *      {
 *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
 *          // now be clear.
 *      }
 *      else
 *      {
 *          // Neither bit 0 nor bit 4 were set in the first place.
 *      }
 * }
 * @endcode
 * \defgroup xEventGroupClearBits xEventGroupClearBits
 * \ingroup EventGroup
 */
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;

/**
 * event_groups.h
 * @code{c}
 *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
 * @endcode
 *
 * A version of xEventGroupClearBits() that can be called from an interrupt.
 *
 * Setting bits in an event group is not a deterministic operation because there
 * are an unknown number of tasks that may be waiting for the bit or bits being
 * set.  FreeRTOS does not allow nondeterministic operations to be performed
 * while interrupts are disabled, so protects event groups that are accessed
 * from tasks by suspending the scheduler rather than disabling interrupts.  As
 * a result event groups cannot be accessed directly from an interrupt service
 * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
 * timer task to have the clear operation performed in the context of the timer
 * task.
 *
 * @note If this function returns pdPASS then the timer task is ready to run
 * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed
 * clear on the event group.  This behavior is different from
 * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is
 * not present.
 *
 * @param xEventGroup The event group in which the bits are to be cleared.
 *
 * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
 * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
 * and bit 0 set uxBitsToClear to 0x09.
 *
 * @return If the request to execute the function was posted successfully then
 * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
 * if the timer service queue was full.
 *
 * Example usage:
 * @code{c}
 * #define BIT_0 ( 1 << 0 )
 * #define BIT_4 ( 1 << 4 )
 *
 * // An event group which it is assumed has already been created by a call to
 * // xEventGroupCreate().
 * EventGroupHandle_t xEventGroup;
 *
 * void anInterruptHandler( void )
 * {
 *      // Clear bit 0 and bit 4 in xEventGroup.
 *      xResult = xEventGroupClearBitsFromISR(
 *                          xEventGroup,     // The event group being updated.
 *                          BIT_0 | BIT_4 ); // The bits being set.
 *
 *      if( xResult == pdPASS )
 *      {
 *          // The message was posted successfully.
 *          portYIELD_FROM_ISR(pdTRUE);
 *      }
 * }
 * @endcode
 * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
 * \ingroup EventGroup
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
#else
    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )
#endif

/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
 * @endcode
 *
 * Set bits within an event group.
 * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
 * is a version that can be called from an interrupt.
 *
 * Setting bits in an event group will automatically unblock tasks that are
 * blocked waiting for the bits.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSetBits()
 * to be available.
 *
 * @param xEventGroup The event group in which the bits are to be set.
 *
 * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
 * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
 * and bit 0 set uxBitsToSet to 0x09.
 *
 * @return The value of the event group at the time the call to
 * xEventGroupSetBits() returns.  There are two reasons why the returned value
 * might have the bits specified by the uxBitsToSet parameter cleared.  First,
 * if setting a bit results in a task that was waiting for the bit leaving the
 * blocked state then it is possible the bit will be cleared automatically
 * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
 * unblocked (or otherwise Ready state) task that has a priority above that of
 * the task that called xEventGroupSetBits() will execute and may change the
 * event group value before the call to xEventGroupSetBits() returns.
 *
 * Example usage:
 * @code{c}
 * #define BIT_0 ( 1 << 0 )
 * #define BIT_4 ( 1 << 4 )
 *
 * void aFunction( EventGroupHandle_t xEventGroup )
 * {
 * EventBits_t uxBits;
 *
 *      // Set bit 0 and bit 4 in xEventGroup.
 *      uxBits = xEventGroupSetBits(
 *                          xEventGroup,    // The event group being updated.
 *                          BIT_0 | BIT_4 );// The bits being set.
 *
 *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
 *      {
 *          // Both bit 0 and bit 4 remained set when the function returned.
 *      }
 *      else if( ( uxBits & BIT_0 ) != 0 )
 *      {
 *          // Bit 0 remained set when the function returned, but bit 4 was
 *          // cleared.  It might be that bit 4 was cleared automatically as a
 *          // task that was waiting for bit 4 was removed from the Blocked
 *          // state.
 *      }
 *      else if( ( uxBits & BIT_4 ) != 0 )
 *      {
 *          // Bit 4 remained set when the function returned, but bit 0 was
 *          // cleared.  It might be that bit 0 was cleared automatically as a
 *          // task that was waiting for bit 0 was removed from the Blocked
 *          // state.
 *      }
 *      else
 *      {
 *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
 *          // was waiting for both of the bits to be set, and the bits were
 *          // cleared as the task left the Blocked state.
 *      }
 * }
 * @endcode
 * \defgroup xEventGroupSetBits xEventGroupSetBits
 * \ingroup EventGroup
 */
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;

/**
 * event_groups.h
 * @code{c}
 *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * A version of xEventGroupSetBits() that can be called from an interrupt.
 *
 * Setting bits in an event group is not a deterministic operation because there
 * are an unknown number of tasks that may be waiting for the bit or bits being
 * set.  FreeRTOS does not allow nondeterministic operations to be performed in
 * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
 * sends a message to the timer task to have the set operation performed in the
 * context of the timer task - where a scheduler lock is used in place of a
 * critical section.
 *
 * @param xEventGroup The event group in which the bits are to be set.
 *
 * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
 * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
 * and bit 0 set uxBitsToSet to 0x09.
 *
 * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
 * will result in a message being sent to the timer daemon task.  If the
 * priority of the timer daemon task is higher than the priority of the
 * currently running task (the task the interrupt interrupted) then
 * *pxHigherPriorityTaskWoken will be set to pdTRUE by
 * xEventGroupSetBitsFromISR(), indicating that a context switch should be
 * requested before the interrupt exits.  For that reason
 * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
 * example code below.
 *
 * @return If the request to execute the function was posted successfully then
 * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
 * if the timer service queue was full.
 *
 * Example usage:
 * @code{c}
 * #define BIT_0 ( 1 << 0 )
 * #define BIT_4 ( 1 << 4 )
 *
 * // An event group which it is assumed has already been created by a call to
 * // xEventGroupCreate().
 * EventGroupHandle_t xEventGroup;
 *
 * void anInterruptHandler( void )
 * {
 * BaseType_t xHigherPriorityTaskWoken, xResult;
 *
 *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
 *      xHigherPriorityTaskWoken = pdFALSE;
 *
 *      // Set bit 0 and bit 4 in xEventGroup.
 *      xResult = xEventGroupSetBitsFromISR(
 *                          xEventGroup,    // The event group being updated.
 *                          BIT_0 | BIT_4   // The bits being set.
 *                          &xHigherPriorityTaskWoken );
 *
 *      // Was the message posted successfully?
 *      if( xResult == pdPASS )
 *      {
 *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
 *          // switch should be requested.  The macro used is port specific and
 *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
 *          // refer to the documentation page for the port being used.
 *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 *      }
 * }
 * @endcode
 * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
 * \ingroup EventGroup
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                          const EventBits_t uxBitsToSet,
                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#else
    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )
#endif

/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
 *                                  const EventBits_t uxBitsToSet,
 *                                  const EventBits_t uxBitsToWaitFor,
 *                                  TickType_t xTicksToWait );
 * @endcode
 *
 * Atomically set bits within an event group, then wait for a combination of
 * bits to be set within the same event group.  This functionality is typically
 * used to synchronise multiple tasks, where each task has to wait for the other
 * tasks to reach a synchronisation point before proceeding.
 *
 * This function cannot be used from an interrupt.
 *
 * The function will return before its block time expires if the bits specified
 * by the uxBitsToWait parameter are set, or become set within that time.  In
 * this case all the bits specified by uxBitsToWait will be automatically
 * cleared before the function returns.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSync()
 * to be available.
 *
 * @param xEventGroup The event group in which the bits are being tested.  The
 * event group must have previously been created using a call to
 * xEventGroupCreate().
 *
 * @param uxBitsToSet The bits to set in the event group before determining
 * if, and possibly waiting for, all the bits specified by the uxBitsToWait
 * parameter are set.
 *
 * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
 * inside the event group.  For example, to wait for bit 0 and bit 2 set
 * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
 * uxBitsToWaitFor to 0x07.  Etc.
 *
 * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
 * for all of the bits specified by uxBitsToWaitFor to become set.
 *
 * @return The value of the event group at the time either the bits being waited
 * for became set, or the block time expired.  Test the return value to know
 * which bits were set.  If xEventGroupSync() returned because its timeout
 * expired then not all the bits being waited for will be set.  If
 * xEventGroupSync() returned because all the bits it was waiting for were
 * set then the returned value is the event group value before any bits were
 * automatically cleared.
 *
 * Example usage:
 * @code{c}
 * // Bits used by the three tasks.
 * #define TASK_0_BIT     ( 1 << 0 )
 * #define TASK_1_BIT     ( 1 << 1 )
 * #define TASK_2_BIT     ( 1 << 2 )
 *
 * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
 *
 * // Use an event group to synchronise three tasks.  It is assumed this event
 * // group has already been created elsewhere.
 * EventGroupHandle_t xEventBits;
 *
 * void vTask0( void *pvParameters )
 * {
 * EventBits_t uxReturn;
 * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
 *
 *   for( ;; )
 *   {
 *      // Perform task functionality here.
 *
 *      // Set bit 0 in the event flag to note this task has reached the
 *      // sync point.  The other two tasks will set the other two bits defined
 *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
 *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
 *      // for this to happen.
 *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
 *
 *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
 *      {
 *          // All three tasks reached the synchronisation point before the call
 *          // to xEventGroupSync() timed out.
 *      }
 *  }
 * }
 *
 * void vTask1( void *pvParameters )
 * {
 *   for( ;; )
 *   {
 *      // Perform task functionality here.
 *
 *      // Set bit 1 in the event flag to note this task has reached the
 *      // synchronisation point.  The other two tasks will set the other two
 *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
 *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
 *      // indefinitely for this to happen.
 *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
 *
 *      // xEventGroupSync() was called with an indefinite block time, so
 *      // this task will only reach here if the synchronisation was made by all
 *      // three tasks, so there is no need to test the return value.
 *   }
 * }
 *
 * void vTask2( void *pvParameters )
 * {
 *   for( ;; )
 *   {
 *      // Perform task functionality here.
 *
 *      // Set bit 2 in the event flag to note this task has reached the
 *      // synchronisation point.  The other two tasks will set the other two
 *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
 *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
 *      // indefinitely for this to happen.
 *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
 *
 *      // xEventGroupSync() was called with an indefinite block time, so
 *      // this task will only reach here if the synchronisation was made by all
 *      // three tasks, so there is no need to test the return value.
 *  }
 * }
 *
 * @endcode
 * \defgroup xEventGroupSync xEventGroupSync
 * \ingroup EventGroup
 */
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
                             const EventBits_t uxBitsToSet,
                             const EventBits_t uxBitsToWaitFor,
                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;


/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
 * @endcode
 *
 * Returns the current value of the bits in an event group.  This function
 * cannot be used from an interrupt.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBits()
 * to be available.
 *
 * @param xEventGroup The event group being queried.
 *
 * @return The event group bits at the time xEventGroupGetBits() was called.
 *
 * \defgroup xEventGroupGetBits xEventGroupGetBits
 * \ingroup EventGroup
 */
#define xEventGroupGetBits( xEventGroup )    xEventGroupClearBits( ( xEventGroup ), 0 )

/**
 * event_groups.h
 * @code{c}
 *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
 * @endcode
 *
 * A version of xEventGroupGetBits() that can be called from an ISR.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBitsFromISR()
 * to be available.
 *
 * @param xEventGroup The event group being queried.
 *
 * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
 *
 * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
 * \ingroup EventGroup
 */
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;

/**
 * event_groups.h
 * @code{c}
 *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
 * @endcode
 *
 * Delete an event group that was previously created by a call to
 * xEventGroupCreate().  Tasks that are blocked on the event group will be
 * unblocked and obtain 0 as the event group's value.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for vEventGroupDelete()
 * to be available.
 *
 * @param xEventGroup The event group being deleted.
 */
void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;

/**
 * event_groups.h
 * @code{c}
 *  BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
 *                                         StaticEventGroup_t ** ppxEventGroupBuffer );
 * @endcode
 *
 * Retrieve a pointer to a statically created event groups's data structure
 * buffer. It is the same buffer that is supplied at the time of creation.
 *
 * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetStaticBuffer()
 * to be available.
 *
 * @param xEventGroup The event group for which to retrieve the buffer.
 *
 * @param ppxEventGroupBuffer Used to return a pointer to the event groups's
 * data structure buffer.
 *
 * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                           StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

/* For internal use only. */
void vEventGroupSetBitsCallback( void * pvEventGroup,
                                 uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
void vEventGroupClearBitsCallback( void * pvEventGroup,
                                   uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;


#if ( configUSE_TRACE_FACILITY == 1 )
    UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;
    void vEventGroupSetNumber( void * xEventGroup,
                               UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
#endif

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* EVENT_GROUPS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/*
 * This is the list implementation used by the scheduler.  While it is tailored
 * heavily for the schedulers needs, it is also available for use by
 * application code.
 *
 * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
 * numeric value (xItemValue).  Most of the time the lists are sorted in
 * ascending item value order.
 *
 * Lists are created already containing one list item.  The value of this
 * item is the maximum possible that can be stored, it is therefore always at
 * the end of the list and acts as a marker.  The list member pxHead always
 * points to this marker - even though it is at the tail of the list.  This
 * is because the tail contains a wrap back pointer to the true head of
 * the list.
 *
 * In addition to it's value, each list item contains a pointer to the next
 * item in the list (pxNext), a pointer to the list it is in (pxContainer)
 * and a pointer to back to the object that contains it.  These later two
 * pointers are included for efficiency of list manipulation.  There is
 * effectively a two way link between the object containing the list item and
 * the list item itself.
 *
 *
 * \page ListIntroduction List Implementation
 * \ingroup FreeRTOSIntro
 */


#ifndef LIST_H
#define LIST_H

#ifndef INC_FREERTOS_H
    #error "FreeRTOS.h must be included before list.h"
#endif

/*
 * The list structure members are modified from within interrupts, and therefore
 * by rights should be declared volatile.  However, they are only modified in a
 * functionally atomic way (within critical sections of with the scheduler
 * suspended) and are either passed by reference into a function or indexed via
 * a volatile variable.  Therefore, in all use cases tested so far, the volatile
 * qualifier can be omitted in order to provide a moderate performance
 * improvement without adversely affecting functional behaviour.  The assembly
 * instructions generated by the IAR, ARM and GCC compilers when the respective
 * compiler's options were set for maximum optimisation has been inspected and
 * deemed to be as intended.  That said, as compiler technology advances, and
 * especially if aggressive cross module optimisation is used (a use case that
 * has not been exercised to any great extend) then it is feasible that the
 * volatile qualifier will be needed for correct optimisation.  It is expected
 * that a compiler removing essential code because, without the volatile
 * qualifier on the list structure members and with aggressive cross module
 * optimisation, the compiler deemed the code unnecessary will result in
 * complete and obvious failure of the scheduler.  If this is ever experienced
 * then the volatile qualifier can be inserted in the relevant places within the
 * list structures by simply defining configLIST_VOLATILE to volatile in
 * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
 * If configLIST_VOLATILE is not defined then the preprocessor directives below
 * will simply #define configLIST_VOLATILE away completely.
 *
 * To use volatile list structure members then add the following line to
 * FreeRTOSConfig.h (without the quotes):
 * "#define configLIST_VOLATILE volatile"
 */
#ifndef configLIST_VOLATILE
    #define configLIST_VOLATILE
#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/* Macros that can be used to place known values within the list structures,
 * then check that the known values do not get corrupted during the execution of
 * the application.   These may catch the list data structures being overwritten in
 * memory.  They will not catch data errors caused by incorrect configuration or
 * use of FreeRTOS.*/
#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
    /* Define the macros to do nothing. */
    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
    #define listTEST_LIST_INTEGRITY( pxList )
#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
    /* Define macros that add new members into the list structures. */
    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;
    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;
    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;
    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;

/* Define macros that set the new structure members to known values. */
    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE

/* Define macros that will assert if one of the structure members does not
 * contain its expected value. */
    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */


/*
 * Definition of the only type of object that a list can contain.
 */
struct xLIST;
struct xLIST_ITEM
{
    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE           /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
    configLIST_VOLATILE TickType_t xItemValue;          /**< The value being listed.  In most cases this is used to sort the list in ascending order. */
    struct xLIST_ITEM * configLIST_VOLATILE pxNext;     /**< Pointer to the next ListItem_t in the list. */
    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /**< Pointer to the previous ListItem_t in the list. */
    void * pvOwner;                                     /**< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
    struct xLIST * configLIST_VOLATILE pxContainer;     /**< Pointer to the list in which this list item is placed (if any). */
    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
};
typedef struct xLIST_ITEM ListItem_t;

#if ( configUSE_MINI_LIST_ITEM == 1 )
    struct xMINI_LIST_ITEM
    {
        listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
        configLIST_VOLATILE TickType_t xItemValue;
        struct xLIST_ITEM * configLIST_VOLATILE pxNext;
        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
    };
    typedef struct xMINI_LIST_ITEM MiniListItem_t;
#else
    typedef struct xLIST_ITEM      MiniListItem_t;
#endif

/*
 * Definition of the type of queue used by the scheduler.
 */
typedef struct xLIST
{
    listFIRST_LIST_INTEGRITY_CHECK_VALUE      /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
    configLIST_VOLATILE UBaseType_t uxNumberOfItems;
    ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
    MiniListItem_t xListEnd;                  /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
    listSECOND_LIST_INTEGRITY_CHECK_VALUE     /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
} List_t;

/*
 * Access macro to set the owner of a list item.  The owner of a list item
 * is the object (usually a TCB) that contains the list item.
 *
 * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
 * \ingroup LinkedList
 */
#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )

/*
 * Access macro to get the owner of a list item.  The owner of a list item
 * is the object (usually a TCB) that contains the list item.
 *
 * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
 * \ingroup LinkedList
 */
#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )

/*
 * Access macro to set the value of the list item.  In most cases the value is
 * used to sort the list in ascending order.
 *
 * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
 * \ingroup LinkedList
 */
#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )

/*
 * Access macro to retrieve the value of the list item.  The value can
 * represent anything - for example the priority of a task, or the time at
 * which a task should be unblocked.
 *
 * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
 * \ingroup LinkedList
 */
#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )

/*
 * Access macro to retrieve the value of the list item at the head of a given
 * list.
 *
 * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
 * \ingroup LinkedList
 */
#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )

/*
 * Return the list item at the head of the list.
 *
 * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
 * \ingroup LinkedList
 */
#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )

/*
 * Return the next list item.
 *
 * \page listGET_NEXT listGET_NEXT
 * \ingroup LinkedList
 */
#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )

/*
 * Return the list item that marks the end of the list
 *
 * \page listGET_END_MARKER listGET_END_MARKER
 * \ingroup LinkedList
 */
#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )

/*
 * Access macro to determine if a list contains any items.  The macro will
 * only have the value true if the list is empty.
 *
 * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
 * \ingroup LinkedList
 */
#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )

/*
 * Access macro to return the number of items in the list.
 */
#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )

/*
 * Access function to obtain the owner of the next entry in a list.
 *
 * The list member pxIndex is used to walk through a list.  Calling
 * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
 * and returns that entry's pxOwner parameter.  Using multiple calls to this
 * function it is therefore possible to move through every item contained in
 * a list.
 *
 * The pxOwner parameter of a list item is a pointer to the object that owns
 * the list item.  In the scheduler this is normally a task control block.
 * The pxOwner parameter effectively creates a two way link between the list
 * item and its owner.
 *
 * @param pxTCB pxTCB is set to the address of the owner of the next list item.
 * @param pxList The list from which the next item owner is to be returned.
 *
 * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
 * \ingroup LinkedList
 */
#if ( configNUMBER_OF_CORES == 1 )
    #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                       \
    do {                                                                                       \
        List_t * const pxConstList = ( pxList );                                               \
        /* Increment the index to the next item and return the item, ensuring */               \
        /* we don't return the marker used at the end of the list.  */                         \
        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \
        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
        {                                                                                      \
            ( pxConstList )->pxIndex = ( pxConstList )->xListEnd.pxNext;                       \
        }                                                                                      \
        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
    } while( 0 )
#else /* #if ( configNUMBER_OF_CORES == 1 ) */

/* This function is not required in SMP. FreeRTOS SMP scheduler doesn't use
 * pxIndex and it should always point to the xListEnd. Not defining this macro
 * here to prevent updating pxIndex.
 */
#endif /* #if ( configNUMBER_OF_CORES == 1 ) */

/*
 * Version of uxListRemove() that does not return a value.  Provided as a slight
 * optimisation for xTaskIncrementTick() by being inline.
 *
 * Remove an item from a list.  The list item has a pointer to the list that
 * it is in, so only the list item need be passed into the function.
 *
 * @param uxListRemove The item to be removed.  The item will remove itself from
 * the list pointed to by it's pxContainer parameter.
 *
 * @return The number of items that remain in the list after the list item has
 * been removed.
 *
 * \page listREMOVE_ITEM listREMOVE_ITEM
 * \ingroup LinkedList
 */
#define listREMOVE_ITEM( pxItemToRemove ) \
    do {                                  \
        /* The list item knows which list it is in.  Obtain the list from the list \
         * item. */                                                                                 \
        List_t * const pxList = ( pxItemToRemove )->pxContainer;                                    \
                                                                                                    \
        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious;                    \
        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;                        \
        /* Make sure the index is left pointing to a valid item. */                                 \
        if( pxList->pxIndex == ( pxItemToRemove ) )                                                 \
        {                                                                                           \
            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                                       \
        }                                                                                           \
                                                                                                    \
        ( pxItemToRemove )->pxContainer = NULL;                                                     \
        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) - 1U ); \
    } while( 0 )

/*
 * Inline version of vListInsertEnd() to provide slight optimisation for
 * xTaskIncrementTick().
 *
 * Insert a list item into a list.  The item will be inserted in a position
 * such that it will be the last item within the list returned by multiple
 * calls to listGET_OWNER_OF_NEXT_ENTRY.
 *
 * The list member pxIndex is used to walk through a list.  Calling
 * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
 * Placing an item in a list using vListInsertEnd effectively places the item
 * in the list position pointed to by pxIndex.  This means that every other
 * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
 * the pxIndex parameter again points to the item being inserted.
 *
 * @param pxList The list into which the item is to be inserted.
 *
 * @param pxNewListItem The list item to be inserted into the list.
 *
 * \page listINSERT_END listINSERT_END
 * \ingroup LinkedList
 */
#define listINSERT_END( pxList, pxNewListItem )           \
    do {                                                  \
        ListItem_t * const pxIndex = ( pxList )->pxIndex; \
                                                          \
        /* Only effective when configASSERT() is also defined, these tests may catch \
         * the list data structures being overwritten in memory.  They will not catch \
         * data errors caused by incorrect configuration or use of FreeRTOS. */ \
        listTEST_LIST_INTEGRITY( ( pxList ) );                                  \
        listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) );                      \
                                                                                \
        /* Insert a new list item into ( pxList ), but rather than sort the list, \
         * makes the new list item the last item to be removed by a call to \
         * listGET_OWNER_OF_NEXT_ENTRY(). */                                                        \
        ( pxNewListItem )->pxNext = pxIndex;                                                        \
        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious;                                        \
                                                                                                    \
        pxIndex->pxPrevious->pxNext = ( pxNewListItem );                                            \
        pxIndex->pxPrevious = ( pxNewListItem );                                                    \
                                                                                                    \
        /* Remember which list the item is in. */                                                   \
        ( pxNewListItem )->pxContainer = ( pxList );                                                \
                                                                                                    \
        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) + 1U ); \
    } while( 0 )

/*
 * Access function to obtain the owner of the first entry in a list.  Lists
 * are normally sorted in ascending item value order.
 *
 * This function returns the pxOwner member of the first item in the list.
 * The pxOwner parameter of a list item is a pointer to the object that owns
 * the list item.  In the scheduler this is normally a task control block.
 * The pxOwner parameter effectively creates a two way link between the list
 * item and its owner.
 *
 * @param pxList The list from which the owner of the head item is to be
 * returned.
 *
 * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
 * \ingroup LinkedList
 */
#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )

/*
 * Check to see if a list item is within a list.  The list item maintains a
 * "container" pointer that points to the list it is in.  All this macro does
 * is check to see if the container and the list match.
 *
 * @param pxList The list we want to know if the list item is within.
 * @param pxListItem The list item we want to know if is in the list.
 * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
 */
#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )

/*
 * Return the list a list item is contained within (referenced from).
 *
 * @param pxListItem The list item being queried.
 * @return A pointer to the List_t object that references the pxListItem
 */
#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )

/*
 * This provides a crude means of knowing if a list has been initialised, as
 * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
 * function.
 */
#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )

/*
 * Must be called before a list is used!  This initialises all the members
 * of the list structure and inserts the xListEnd item into the list as a
 * marker to the back of the list.
 *
 * @param pxList Pointer to the list being initialised.
 *
 * \page vListInitialise vListInitialise
 * \ingroup LinkedList
 */
void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;

/*
 * Must be called before a list item is used.  This sets the list container to
 * null so the item does not think that it is already contained in a list.
 *
 * @param pxItem Pointer to the list item being initialised.
 *
 * \page vListInitialiseItem vListInitialiseItem
 * \ingroup LinkedList
 */
void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;

/*
 * Insert a list item into a list.  The item will be inserted into the list in
 * a position determined by its item value (ascending item value order).
 *
 * @param pxList The list into which the item is to be inserted.
 *
 * @param pxNewListItem The item that is to be placed in the list.
 *
 * \page vListInsert vListInsert
 * \ingroup LinkedList
 */
void vListInsert( List_t * const pxList,
                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;

/*
 * Insert a list item into a list.  The item will be inserted in a position
 * such that it will be the last item within the list returned by multiple
 * calls to listGET_OWNER_OF_NEXT_ENTRY.
 *
 * The list member pxIndex is used to walk through a list.  Calling
 * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
 * Placing an item in a list using vListInsertEnd effectively places the item
 * in the list position pointed to by pxIndex.  This means that every other
 * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
 * the pxIndex parameter again points to the item being inserted.
 *
 * @param pxList The list into which the item is to be inserted.
 *
 * @param pxNewListItem The list item to be inserted into the list.
 *
 * \page vListInsertEnd vListInsertEnd
 * \ingroup LinkedList
 */
void vListInsertEnd( List_t * const pxList,
                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;

/*
 * Remove an item from a list.  The list item has a pointer to the list that
 * it is in, so only the list item need be passed into the function.
 *
 * @param uxListRemove The item to be removed.  The item will remove itself from
 * the list pointed to by it's pxContainer parameter.
 *
 * @return The number of items that remain in the list after the list item has
 * been removed.
 *
 * \page uxListRemove uxListRemove
 * \ingroup LinkedList
 */
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* ifndef LIST_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


/*
 * Message buffers build functionality on top of FreeRTOS stream buffers.
 * Whereas stream buffers are used to send a continuous stream of data from one
 * task or interrupt to another, message buffers are used to send variable
 * length discrete messages from one task or interrupt to another.  Their
 * implementation is light weight, making them particularly suited for interrupt
 * to task and core to core communication scenarios.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xMessageBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xMessageBufferRead()) inside a critical section and set the receive
 * timeout to 0.
 *
 * Message buffers hold variable length messages.  To enable that, when a
 * message is written to the message buffer an additional sizeof( size_t ) bytes
 * are also written to store the message's length (that happens internally, with
 * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
 * architecture, so writing a 10 byte message to a message buffer on a 32-bit
 * architecture will actually reduce the available space in the message buffer
 * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
 * of the message).
 */

#ifndef FREERTOS_MESSAGE_BUFFER_H
#define FREERTOS_MESSAGE_BUFFER_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include message_buffer.h"
#endif

/* Message buffers are built onto of stream buffers. */
#include "stream_buffer.h"

/* *INDENT-OFF* */
#if defined( __cplusplus )
    extern "C" {
#endif
/* *INDENT-ON* */

/**
 * Type by which message buffers are referenced.  For example, a call to
 * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
 * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
 * etc. Message buffer is essentially built as a stream buffer hence its handle
 * is also set to same type as a stream buffer handle.
 */
typedef StreamBufferHandle_t MessageBufferHandle_t;

/*-----------------------------------------------------------*/

/**
 * message_buffer.h
 *
 * @code{c}
 * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
 * @endcode
 *
 * Creates a new message buffer using dynamically allocated memory.  See
 * xMessageBufferCreateStatic() for a version that uses statically allocated
 * memory (memory that is allocated at compile time).
 *
 * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
 * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferCreate() to be available.
 *
 * @param xBufferSizeBytes The total number of bytes (not messages) the message
 * buffer will be able to hold at any one time.  When a message is written to
 * the message buffer an additional sizeof( size_t ) bytes are also written to
 * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
 * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
 * take up 14 bytes of message buffer space.
 *
 * @param pxSendCompletedCallback Callback invoked when a send operation to the
 * message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
 * is called without the parameter, then it will use the default implementation
 * provided by sbSEND_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when a receive operation from
 * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
 * is called without the parameter, it will use the default implementation provided
 * by sbRECEIVE_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @return If NULL is returned, then the message buffer cannot be created
 * because there is insufficient heap memory available for FreeRTOS to allocate
 * the message buffer data structures and storage area.  A non-NULL value being
 * returned indicates that the message buffer has been created successfully -
 * the returned value should be stored as the handle to the created message
 * buffer.
 *
 * Example use:
 * @code{c}
 *
 * void vAFunction( void )
 * {
 * MessageBufferHandle_t xMessageBuffer;
 * const size_t xMessageBufferSizeBytes = 100;
 *
 *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
 *  // both the message buffer structure and the messages themselves is allocated
 *  // dynamically.  Each message added to the buffer consumes an additional 4
 *  // bytes which are used to hold the length of the message.
 *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
 *
 *  if( xMessageBuffer == NULL )
 *  {
 *      // There was not enough heap memory space available to create the
 *      // message buffer.
 *  }
 *  else
 *  {
 *      // The message buffer was created successfully and can now be used.
 *  }
 *
 * @endcode
 * \defgroup xMessageBufferCreate xMessageBufferCreate
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferCreate( xBufferSizeBytes ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * message_buffer.h
 *
 * @code{c}
 * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
 *                                                   uint8_t *pucMessageBufferStorageArea,
 *                                                   StaticMessageBuffer_t *pxStaticMessageBuffer );
 * @endcode
 * Creates a new message buffer using statically allocated memory.  See
 * xMessageBufferCreate() for a version that uses dynamically allocated memory.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferCreateStatic() to be available.
 *
 * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
 * pucMessageBufferStorageArea parameter.  When a message is written to the
 * message buffer an additional sizeof( size_t ) bytes are also written to store
 * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
 * architecture, so on most 32-bit architecture a 10 byte message will take up
 * 14 bytes of message buffer space.  The maximum number of bytes that can be
 * stored in the message buffer is actually (xBufferSizeBytes - 1).
 *
 * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
 * least xBufferSizeBytes big.  This is the array to which messages are
 * copied when they are written to the message buffer.
 *
 * @param pxStaticMessageBuffer Must point to a variable of type
 * StaticMessageBuffer_t, which will be used to hold the message buffer's data
 * structure.
 *
 * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer.
 * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default
 * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when a message is read from a
 * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will
 * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @return If the message buffer is created successfully then a handle to the
 * created message buffer is returned. If either pucMessageBufferStorageArea or
 * pxStaticmessageBuffer are NULL then NULL is returned.
 *
 * Example use:
 * @code{c}
 *
 * // Used to dimension the array used to hold the messages.  The available space
 * // will actually be one less than this, so 999.
 #define STORAGE_SIZE_BYTES 1000
 *
 * // Defines the memory that will actually hold the messages within the message
 * // buffer.
 * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
 *
 * // The variable used to hold the message buffer structure.
 * StaticMessageBuffer_t xMessageBufferStruct;
 *
 * void MyFunction( void )
 * {
 * MessageBufferHandle_t xMessageBuffer;
 *
 *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ),
 *                                               ucStorageBuffer,
 *                                               &xMessageBufferStruct );
 *
 *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
 *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
 *  // reference the created message buffer in other message buffer API calls.
 *
 *  // Other code that uses the message buffer can go here.
 * }
 *
 * @endcode
 * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * message_buffer.h
 *
 * @code{c}
 * BaseType_t xMessageBufferGetStaticBuffers( MessageBufferHandle_t xMessageBuffer,
 *                                            uint8_t ** ppucMessageBufferStorageArea,
 *                                            StaticMessageBuffer_t ** ppxStaticMessageBuffer );
 * @endcode
 *
 * Retrieve pointers to a statically created message buffer's data structure
 * buffer and storage area buffer. These are the same buffers that are supplied
 * at the time of creation.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferGetStaticBuffers() to be available.
 *
 * @param xMessageBuffer The message buffer for which to retrieve the buffers.
 *
 * @param ppucMessageBufferStorageArea Used to return a pointer to the
 * message buffer's storage area buffer.
 *
 * @param ppxStaticMessageBuffer Used to return a pointer to the message
 * buffer's data structure buffer.
 *
 * @return pdTRUE if buffers were retrieved, pdFALSE otherwise..
 *
 * \defgroup xMessageBufferGetStaticBuffers xMessageBufferGetStaticBuffers
 * \ingroup MessageBufferManagement
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xMessageBufferGetStaticBuffers( xMessageBuffer, ppucMessageBufferStorageArea, ppxStaticMessageBuffer ) \
    xStreamBufferGetStaticBuffers( ( xMessageBuffer ), ( ppucMessageBufferStorageArea ), ( ppxStaticMessageBuffer ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * message_buffer.h
 *
 * @code{c}
 * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
 *                            const void *pvTxData,
 *                            size_t xDataLengthBytes,
 *                            TickType_t xTicksToWait );
 * @endcode
 *
 * Sends a discrete message to the message buffer.  The message can be any
 * length that fits within the buffer's free space, and is copied into the
 * buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xMessageBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xMessageBufferRead()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xMessageBufferSend() to write to a message buffer from a task.  Use
 * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
 * service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferSend() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer to which a message is
 * being sent.
 *
 * @param pvTxData A pointer to the message that is to be copied into the
 * message buffer.
 *
 * @param xDataLengthBytes The length of the message.  That is, the number of
 * bytes to copy from pvTxData into the message buffer.  When a message is
 * written to the message buffer an additional sizeof( size_t ) bytes are also
 * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
 * on a 32-bit architecture, so on most 32-bit architecture setting
 * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
 * bytes (20 bytes of message data and 4 bytes to hold the message length).
 *
 * @param xTicksToWait The maximum amount of time the calling task should remain
 * in the Blocked state to wait for enough space to become available in the
 * message buffer, should the message buffer have insufficient space when
 * xMessageBufferSend() is called.  The calling task will never block if
 * xTicksToWait is zero.  The block time is specified in tick periods, so the
 * absolute time it represents is dependent on the tick frequency.  The macro
 * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
 * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
 * the task to wait indefinitely (without timing out), provided
 * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
 * CPU time when they are in the Blocked state.
 *
 * @return The number of bytes written to the message buffer.  If the call to
 * xMessageBufferSend() times out before there was enough space to write the
 * message into the message buffer then zero is returned.  If the call did not
 * time out then xDataLengthBytes is returned.
 *
 * Example use:
 * @code{c}
 * void vAFunction( MessageBufferHandle_t xMessageBuffer )
 * {
 * size_t xBytesSent;
 * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
 * char *pcStringToSend = "String to send";
 * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
 *
 *  // Send an array to the message buffer, blocking for a maximum of 100ms to
 *  // wait for enough space to be available in the message buffer.
 *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
 *
 *  if( xBytesSent != sizeof( ucArrayToSend ) )
 *  {
 *      // The call to xMessageBufferSend() times out before there was enough
 *      // space in the buffer for the data to be written.
 *  }
 *
 *  // Send the string to the message buffer.  Return immediately if there is
 *  // not enough space in the buffer.
 *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
 *
 *  if( xBytesSent != strlen( pcStringToSend ) )
 *  {
 *      // The string could not be added to the message buffer because there was
 *      // not enough free space in the buffer.
 *  }
 * }
 * @endcode
 * \defgroup xMessageBufferSend xMessageBufferSend
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
    xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) )

/**
 * message_buffer.h
 *
 * @code{c}
 * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
 *                                   const void *pvTxData,
 *                                   size_t xDataLengthBytes,
 *                                   BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * Interrupt safe version of the API function that sends a discrete message to
 * the message buffer.  The message can be any length that fits within the
 * buffer's free space, and is copied into the buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xMessageBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xMessageBufferRead()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xMessageBufferSend() to write to a message buffer from a task.  Use
 * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
 * service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferSendFromISR() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer to which a message is
 * being sent.
 *
 * @param pvTxData A pointer to the message that is to be copied into the
 * message buffer.
 *
 * @param xDataLengthBytes The length of the message.  That is, the number of
 * bytes to copy from pvTxData into the message buffer.  When a message is
 * written to the message buffer an additional sizeof( size_t ) bytes are also
 * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
 * on a 32-bit architecture, so on most 32-bit architecture setting
 * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
 * bytes (20 bytes of message data and 4 bytes to hold the message length).
 *
 * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
 * have a task blocked on it waiting for data.  Calling
 * xMessageBufferSendFromISR() can make data available, and so cause a task that
 * was waiting for data to leave the Blocked state.  If calling
 * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
 * unblocked task has a priority higher than the currently executing task (the
 * task that was interrupted), then, internally, xMessageBufferSendFromISR()
 * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
 * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
 * context switch should be performed before the interrupt is exited.  This will
 * ensure that the interrupt returns directly to the highest priority Ready
 * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
 * is passed into the function.  See the code example below for an example.
 *
 * @return The number of bytes actually written to the message buffer.  If the
 * message buffer didn't have enough free space for the message to be stored
 * then 0 is returned, otherwise xDataLengthBytes is returned.
 *
 * Example use:
 * @code{c}
 * // A message buffer that has already been created.
 * MessageBufferHandle_t xMessageBuffer;
 *
 * void vAnInterruptServiceRoutine( void )
 * {
 * size_t xBytesSent;
 * char *pcStringToSend = "String to send";
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
 *
 *  // Attempt to send the string to the message buffer.
 *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
 *                                          ( void * ) pcStringToSend,
 *                                          strlen( pcStringToSend ),
 *                                          &xHigherPriorityTaskWoken );
 *
 *  if( xBytesSent != strlen( pcStringToSend ) )
 *  {
 *      // The string could not be added to the message buffer because there was
 *      // not enough free space in the buffer.
 *  }
 *
 *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
 *  // xMessageBufferSendFromISR() then a task that has a priority above the
 *  // priority of the currently executing task was unblocked and a context
 *  // switch should be performed to ensure the ISR returns to the unblocked
 *  // task.  In most FreeRTOS ports this is done by simply passing
 *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
 *  // variables value, and perform the context switch if necessary.  Check the
 *  // documentation for the port in use for port specific instructions.
 *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 * }
 * @endcode
 * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
    xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) )

/**
 * message_buffer.h
 *
 * @code{c}
 * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
 *                               void *pvRxData,
 *                               size_t xBufferLengthBytes,
 *                               TickType_t xTicksToWait );
 * @endcode
 *
 * Receives a discrete message from a message buffer.  Messages can be of
 * variable length and are copied out of the buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xMessageBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xMessageBufferRead()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
 * xMessageBufferReceiveFromISR() to read from a message buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferReceive() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer from which a message
 * is being received.
 *
 * @param pvRxData A pointer to the buffer into which the received message is
 * to be copied.
 *
 * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
 * parameter.  This sets the maximum length of the message that can be received.
 * If xBufferLengthBytes is too small to hold the next message then the message
 * will be left in the message buffer and 0 will be returned.
 *
 * @param xTicksToWait The maximum amount of time the task should remain in the
 * Blocked state to wait for a message, should the message buffer be empty.
 * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
 * the message buffer is empty.  The block time is specified in tick periods, so
 * the absolute time it represents is dependent on the tick frequency.  The
 * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
 * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
 * cause the task to wait indefinitely (without timing out), provided
 * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
 * CPU time when they are in the Blocked state.
 *
 * @return The length, in bytes, of the message read from the message buffer, if
 * any.  If xMessageBufferReceive() times out before a message became available
 * then zero is returned.  If the length of the message is greater than
 * xBufferLengthBytes then the message will be left in the message buffer and
 * zero is returned.
 *
 * Example use:
 * @code{c}
 * void vAFunction( MessageBuffer_t xMessageBuffer )
 * {
 * uint8_t ucRxData[ 20 ];
 * size_t xReceivedBytes;
 * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
 *
 *  // Receive the next message from the message buffer.  Wait in the Blocked
 *  // state (so not using any CPU processing time) for a maximum of 100ms for
 *  // a message to become available.
 *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
 *                                          ( void * ) ucRxData,
 *                                          sizeof( ucRxData ),
 *                                          xBlockTime );
 *
 *  if( xReceivedBytes > 0 )
 *  {
 *      // A ucRxData contains a message that is xReceivedBytes long.  Process
 *      // the message here....
 *  }
 * }
 * @endcode
 * \defgroup xMessageBufferReceive xMessageBufferReceive
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
    xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) )


/**
 * message_buffer.h
 *
 * @code{c}
 * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
 *                                      void *pvRxData,
 *                                      size_t xBufferLengthBytes,
 *                                      BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * An interrupt safe version of the API function that receives a discrete
 * message from a message buffer.  Messages can be of variable length and are
 * copied out of the buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xMessageBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xMessageBufferRead()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
 * xMessageBufferReceiveFromISR() to read from a message buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferReceiveFromISR() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer from which a message
 * is being received.
 *
 * @param pvRxData A pointer to the buffer into which the received message is
 * to be copied.
 *
 * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
 * parameter.  This sets the maximum length of the message that can be received.
 * If xBufferLengthBytes is too small to hold the next message then the message
 * will be left in the message buffer and 0 will be returned.
 *
 * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
 * have a task blocked on it waiting for space to become available.  Calling
 * xMessageBufferReceiveFromISR() can make space available, and so cause a task
 * that is waiting for space to leave the Blocked state.  If calling
 * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
 * the unblocked task has a priority higher than the currently executing task
 * (the task that was interrupted), then, internally,
 * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
 * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
 * context switch should be performed before the interrupt is exited.  That will
 * ensure the interrupt returns directly to the highest priority Ready state
 * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
 * passed into the function.  See the code example below for an example.
 *
 * @return The length, in bytes, of the message read from the message buffer, if
 * any.
 *
 * Example use:
 * @code{c}
 * // A message buffer that has already been created.
 * MessageBuffer_t xMessageBuffer;
 *
 * void vAnInterruptServiceRoutine( void )
 * {
 * uint8_t ucRxData[ 20 ];
 * size_t xReceivedBytes;
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
 *
 *  // Receive the next message from the message buffer.
 *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
 *                                                ( void * ) ucRxData,
 *                                                sizeof( ucRxData ),
 *                                                &xHigherPriorityTaskWoken );
 *
 *  if( xReceivedBytes > 0 )
 *  {
 *      // A ucRxData contains a message that is xReceivedBytes long.  Process
 *      // the message here....
 *  }
 *
 *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
 *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
 *  // priority of the currently executing task was unblocked and a context
 *  // switch should be performed to ensure the ISR returns to the unblocked
 *  // task.  In most FreeRTOS ports this is done by simply passing
 *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
 *  // variables value, and perform the context switch if necessary.  Check the
 *  // documentation for the port in use for port specific instructions.
 *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 * }
 * @endcode
 * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
    xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) )

/**
 * message_buffer.h
 *
 * @code{c}
 * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 *
 * Deletes a message buffer that was previously created using a call to
 * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
 * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
 * then the allocated memory is freed.
 *
 * A message buffer handle must not be used after the message buffer has been
 * deleted.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * vMessageBufferDelete() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer to be deleted.
 *
 */
#define vMessageBufferDelete( xMessageBuffer ) \
    vStreamBufferDelete( xMessageBuffer )

/**
 * message_buffer.h
 * @code{c}
 * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 *
 * Tests to see if a message buffer is full.  A message buffer is full if it
 * cannot accept any more messages, of any size, until space is made available
 * by a message being removed from the message buffer.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferIsFull() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being queried.
 *
 * @return If the message buffer referenced by xMessageBuffer is full then
 * pdTRUE is returned.  Otherwise pdFALSE is returned.
 */
#define xMessageBufferIsFull( xMessageBuffer ) \
    xStreamBufferIsFull( xMessageBuffer )

/**
 * message_buffer.h
 * @code{c}
 * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 *
 * Tests to see if a message buffer is empty (does not contain any messages).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferIsEmpty() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being queried.
 *
 * @return If the message buffer referenced by xMessageBuffer is empty then
 * pdTRUE is returned.  Otherwise pdFALSE is returned.
 *
 */
#define xMessageBufferIsEmpty( xMessageBuffer ) \
    xStreamBufferIsEmpty( xMessageBuffer )

/**
 * message_buffer.h
 * @code{c}
 * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 *
 * Resets a message buffer to its initial empty state, discarding any message it
 * contained.
 *
 * A message buffer can only be reset if there are no tasks blocked on it.
 *
 * Use xMessageBufferReset() to reset a message buffer from a task.
 * Use xMessageBufferResetFromISR() to reset a message buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferReset() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being reset.
 *
 * @return If the message buffer was reset then pdPASS is returned.  If the
 * message buffer could not be reset because either there was a task blocked on
 * the message queue to wait for space to become available, or to wait for a
 * a message to be available, then pdFAIL is returned.
 *
 * \defgroup xMessageBufferReset xMessageBufferReset
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferReset( xMessageBuffer ) \
    xStreamBufferReset( xMessageBuffer )


/**
 * message_buffer.h
 * @code{c}
 * BaseType_t xMessageBufferResetFromISR( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 *
 * An interrupt safe version of the API function that resets the message buffer.
 * Resets a message buffer to its initial empty state, discarding any message it
 * contained.
 *
 * A message buffer can only be reset if there are no tasks blocked on it.
 *
 * Use xMessageBufferReset() to reset a message buffer from a task.
 * Use xMessageBufferResetFromISR() to reset a message buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferResetFromISR() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being reset.
 *
 * @return If the message buffer was reset then pdPASS is returned.  If the
 * message buffer could not be reset because either there was a task blocked on
 * the message queue to wait for space to become available, or to wait for a
 * a message to be available, then pdFAIL is returned.
 *
 * \defgroup xMessageBufferResetFromISR xMessageBufferResetFromISR
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferResetFromISR( xMessageBuffer ) \
    xStreamBufferResetFromISR( xMessageBuffer )

/**
 * message_buffer.h
 * @code{c}
 * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 * Returns the number of bytes of free space in the message buffer.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferSpaceAvailable() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being queried.
 *
 * @return The number of bytes that can be written to the message buffer before
 * the message buffer would be full.  When a message is written to the message
 * buffer an additional sizeof( size_t ) bytes are also written to store the
 * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
 * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
 * of the largest message that can be written to the message buffer is 6 bytes.
 *
 * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
    xStreamBufferSpacesAvailable( xMessageBuffer )
#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
    xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */

/**
 * message_buffer.h
 * @code{c}
 * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer );
 * @endcode
 * Returns the length (in bytes) of the next message in a message buffer.
 * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
 * passed into xMessageBufferReceive() was too small to hold the next message.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferNextLengthBytes() to be available.
 *
 * @param xMessageBuffer The handle of the message buffer being queried.
 *
 * @return The length (in bytes) of the next message in the message buffer, or 0
 * if the message buffer is empty.
 *
 * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
 * \ingroup MessageBufferManagement
 */
#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
    xStreamBufferNextMessageLengthBytes( xMessageBuffer )

/**
 * message_buffer.h
 *
 * @code{c}
 * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * For advanced users only.
 *
 * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
 * data is sent to a message buffer or stream buffer.  If there was a task that
 * was blocked on the message or stream buffer waiting for data to arrive then
 * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
 * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
 * thing.  It is provided to enable application writers to implement their own
 * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
 *
 * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
 * additional information.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferSendCompletedFromISR() to be available.
 *
 * @param xMessageBuffer The handle of the stream buffer to which data was
 * written.
 *
 * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
 * initialised to pdFALSE before it is passed into
 * xMessageBufferSendCompletedFromISR().  If calling
 * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
 * and the task has a priority above the priority of the currently running task,
 * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
 * context switch should be performed before exiting the ISR.
 *
 * @return If a task was removed from the Blocked state then pdTRUE is returned.
 * Otherwise pdFALSE is returned.
 *
 * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
 * \ingroup StreamBufferManagement
 */
#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
    xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )

/**
 * message_buffer.h
 *
 * @code{c}
 * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * For advanced users only.
 *
 * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
 * data is read out of a message buffer or stream buffer.  If there was a task
 * that was blocked on the message or stream buffer waiting for data to arrive
 * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
 * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
 * does the same thing.  It is provided to enable application writers to
 * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
 * ANY OTHER TIME.
 *
 * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
 * additional information.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xMessageBufferReceiveCompletedFromISR() to be available.
 *
 * @param xMessageBuffer The handle of the stream buffer from which data was
 * read.
 *
 * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
 * initialised to pdFALSE before it is passed into
 * xMessageBufferReceiveCompletedFromISR().  If calling
 * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
 * and the task has a priority above the priority of the currently running task,
 * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
 * context switch should be performed before exiting the ISR.
 *
 * @return If a task was removed from the Blocked state then pdTRUE is returned.
 * Otherwise pdFALSE is returned.
 *
 * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
 * \ingroup StreamBufferManagement
 */
#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
    xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )

/* *INDENT-OFF* */
#if defined( __cplusplus )
    } /* extern "C" */
#endif
/* *INDENT-ON* */

#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/*
 * When the MPU is used the standard (non MPU) API functions are mapped to
 * equivalents that start "MPU_", the prototypes for which are defined in this
 * header files.  This will cause the application code to call the MPU_ version
 * which wraps the non-MPU version with privilege promoting then demoting code,
 * so the kernel code always runs will full privileges.
 */


#ifndef MPU_PROTOTYPES_H
#define MPU_PROTOTYPES_H

typedef struct xTaskGenericNotifyParams
{
    TaskHandle_t xTaskToNotify;
    UBaseType_t uxIndexToNotify;
    uint32_t ulValue;
    eNotifyAction eAction;
    uint32_t * pulPreviousNotificationValue;
} xTaskGenericNotifyParams_t;

typedef struct xTaskGenericNotifyWaitParams
{
    UBaseType_t uxIndexToWaitOn;
    uint32_t ulBitsToClearOnEntry;
    uint32_t ulBitsToClearOnExit;
    uint32_t * pulNotificationValue;
    TickType_t xTicksToWait;
} xTaskGenericNotifyWaitParams_t;

typedef struct xTimerGenericCommandFromTaskParams
{
    TimerHandle_t xTimer;
    BaseType_t xCommandID;
    TickType_t xOptionalValue;
    BaseType_t * pxHigherPriorityTaskWoken;
    TickType_t xTicksToWait;
} xTimerGenericCommandFromTaskParams_t;

typedef struct xEventGroupWaitBitsParams
{
    EventGroupHandle_t xEventGroup;
    EventBits_t uxBitsToWaitFor;
    BaseType_t xClearOnExit;
    BaseType_t xWaitForAllBits;
    TickType_t xTicksToWait;
} xEventGroupWaitBitsParams_t;

/* MPU versions of task.h API functions. */
void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskGetInfo( TaskHandle_t xTask,
                       TaskStatus_t * pxTaskStatus,
                       BaseType_t xGetFreeStackSpace,
                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
                                            BaseType_t xIndex,
                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
                                      const UBaseType_t uxArraySize,
                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
                                   UBaseType_t uxIndexToNotify,
                                   uint32_t ulValue,
                                   eNotifyAction eAction,
                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                       uint32_t ulBitsToClearOnEntry,
                                       uint32_t ulBitsToClearOnExit,
                                       uint32_t * pulNotificationValue,
                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                      BaseType_t xClearCountOnExit,
                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
                                            UBaseType_t uxIndexToClear,
                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;

/* Privileged only wrappers for Task APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
                            const char * const pcName,
                            const configSTACK_DEPTH_TYPE uxStackDepth,
                            void * const pvParameters,
                            UBaseType_t uxPriority,
                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                    const char * const pcName,
                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                    void * const pvParameters,
                                    UBaseType_t uxPriority,
                                    StackType_t * const puxStackBuffer,
                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
void MPU_vTaskPrioritySet( TaskHandle_t xTask,
                           UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
                                             void * pvParameter ) PRIVILEGED_FUNCTION;
char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
                                      StackType_t ** ppuxStackBuffer,
                                      StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
                                          UBaseType_t uxIndexToNotify,
                                          uint32_t ulValue,
                                          eNotifyAction eAction,
                                          uint32_t * pulPreviousNotificationValue,
                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
void MPU_vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
                                        UBaseType_t uxIndexToNotify,
                                        BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/* MPU versions of queue.h API functions. */
BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
                                  const void * const pvItemToQueue,
                                  TickType_t xTicksToWait,
                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
                              void * const pvBuffer,
                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
                           void * const pvBuffer,
                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
                              const char * pcName ) FREERTOS_SYSTEM_CALL;
void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;

/* Privileged only wrappers for Queue APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
                                                       const UBaseType_t uxInitialCount,
                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
                                       const UBaseType_t uxItemSize,
                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
                                             const UBaseType_t uxItemSize,
                                             uint8_t * pucQueueStorage,
                                             StaticQueue_t * pxStaticQueue,
                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
                                   BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
                                              uint8_t ** ppucQueueStorage,
                                              StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueGenericSendFromISR( QueueHandle_t xQueue,
                                         const void * const pvItemToQueue,
                                         BaseType_t * const pxHigherPriorityTaskWoken,
                                         const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueGiveFromISR( QueueHandle_t xQueue,
                                  BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue,
                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueReceiveFromISR( QueueHandle_t xQueue,
                                     void * const pvBuffer,
                                     BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
UBaseType_t MPU_uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
TaskHandle_t MPU_xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
QueueSetMemberHandle_t MPU_xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;

/* MPU versions of timers.h API functions. */
void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
                                             const BaseType_t xCommandID,
                                             const TickType_t xOptionalValue,
                                             BaseType_t * const pxHigherPriorityTaskWoken,
                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
                              const BaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;

/* Privileged only wrappers for Timer APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
                                const TickType_t xTimerPeriodInTicks,
                                const UBaseType_t uxAutoReload,
                                void * const pvTimerID,
                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
                                      const TickType_t xTimerPeriodInTicks,
                                      const UBaseType_t uxAutoReload,
                                      void * const pvTimerID,
                                      TimerCallbackFunction_t pxCallbackFunction,
                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer,
                                      StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
                                            const BaseType_t xCommandID,
                                            const TickType_t xOptionalValue,
                                            BaseType_t * const pxHigherPriorityTaskWoken,
                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/* MPU versions of event_group.h API functions. */
EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                                     const EventBits_t uxBitsToWaitFor,
                                     const BaseType_t xClearOnExit,
                                     const BaseType_t xWaitForAllBits,
                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
                                 const EventBits_t uxBitsToSet,
                                 const EventBits_t uxBitsToWaitFor,
                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
#if ( configUSE_TRACE_FACILITY == 1 )
    UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
    void MPU_vEventGroupSetNumber( void * xEventGroup,
                                   UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
#endif /* ( configUSE_TRACE_FACILITY == 1 )*/

/* Privileged only wrappers for Event Group APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                           StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
                                          const EventBits_t uxBitsToSet,
                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;

/* MPU versions of message/stream_buffer.h API functions. */
size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                              const void * pvTxData,
                              size_t xDataLengthBytes,
                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
                                 void * pvRxData,
                                 size_t xBufferLengthBytes,
                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;

/* Privileged only wrappers for Stream Buffer APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                     size_t xTriggerLevelBytes,
                                                     BaseType_t xStreamBufferType,
                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                           size_t xTriggerLevelBytes,
                                                           BaseType_t xStreamBufferType,
                                                           uint8_t * const pucStreamBufferStorageArea,
                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
                                              uint8_t * ppucStreamBufferStorageArea,
                                              StaticStreamBuffer_t * ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
                                     const void * pvTxData,
                                     size_t xDataLengthBytes,
                                     BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
                                        void * pvRxData,
                                        size_t xBufferLengthBytes,
                                        BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                  BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                     BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

#endif /* MPU_PROTOTYPES_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_syscall_numbers.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef MPU_SYSCALL_NUMBERS_H
#define MPU_SYSCALL_NUMBERS_H

/* Numbers assigned to various system calls. */
#define SYSTEM_CALL_xTaskGenericNotify                     0
#define SYSTEM_CALL_xTaskGenericNotifyWait                 1
#define SYSTEM_CALL_xTimerGenericCommandFromTask           2
#define SYSTEM_CALL_xEventGroupWaitBits                    3
#define SYSTEM_CALL_xTaskDelayUntil                        4
#define SYSTEM_CALL_xTaskAbortDelay                        5
#define SYSTEM_CALL_vTaskDelay                             6
#define SYSTEM_CALL_uxTaskPriorityGet                      7
#define SYSTEM_CALL_eTaskGetState                          8
#define SYSTEM_CALL_vTaskGetInfo                           9
#define SYSTEM_CALL_xTaskGetIdleTaskHandle                 10
#define SYSTEM_CALL_vTaskSuspend                           11
#define SYSTEM_CALL_vTaskResume                            12
#define SYSTEM_CALL_xTaskGetTickCount                      13
#define SYSTEM_CALL_uxTaskGetNumberOfTasks                 14
#define SYSTEM_CALL_ulTaskGetRunTimeCounter                15
#define SYSTEM_CALL_ulTaskGetRunTimePercent                16
#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent            17
#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter            18
#define SYSTEM_CALL_vTaskSetApplicationTaskTag             19
#define SYSTEM_CALL_xTaskGetApplicationTaskTag             20
#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer      21
#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer     22
#define SYSTEM_CALL_uxTaskGetSystemState                   23
#define SYSTEM_CALL_uxTaskGetStackHighWaterMark            24
#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2           25
#define SYSTEM_CALL_xTaskGetCurrentTaskHandle              26
#define SYSTEM_CALL_xTaskGetSchedulerState                 27
#define SYSTEM_CALL_vTaskSetTimeOutState                   28
#define SYSTEM_CALL_xTaskCheckForTimeOut                   29
#define SYSTEM_CALL_ulTaskGenericNotifyTake                30
#define SYSTEM_CALL_xTaskGenericNotifyStateClear           31
#define SYSTEM_CALL_ulTaskGenericNotifyValueClear          32
#define SYSTEM_CALL_xQueueGenericSend                      33
#define SYSTEM_CALL_uxQueueMessagesWaiting                 34
#define SYSTEM_CALL_uxQueueSpacesAvailable                 35
#define SYSTEM_CALL_xQueueReceive                          36
#define SYSTEM_CALL_xQueuePeek                             37
#define SYSTEM_CALL_xQueueSemaphoreTake                    38
#define SYSTEM_CALL_xQueueGetMutexHolder                   39
#define SYSTEM_CALL_xQueueTakeMutexRecursive               40
#define SYSTEM_CALL_xQueueGiveMutexRecursive               41
#define SYSTEM_CALL_xQueueSelectFromSet                    42
#define SYSTEM_CALL_xQueueAddToSet                         43
#define SYSTEM_CALL_vQueueAddToRegistry                    44
#define SYSTEM_CALL_vQueueUnregisterQueue                  45
#define SYSTEM_CALL_pcQueueGetName                         46
#define SYSTEM_CALL_pvTimerGetTimerID                      47
#define SYSTEM_CALL_vTimerSetTimerID                       48
#define SYSTEM_CALL_xTimerIsTimerActive                    49
#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle         50
#define SYSTEM_CALL_pcTimerGetName                         51
#define SYSTEM_CALL_vTimerSetReloadMode                    52
#define SYSTEM_CALL_xTimerGetReloadMode                    53
#define SYSTEM_CALL_uxTimerGetReloadMode                   54
#define SYSTEM_CALL_xTimerGetPeriod                        55
#define SYSTEM_CALL_xTimerGetExpiryTime                    56
#define SYSTEM_CALL_xEventGroupClearBits                   57
#define SYSTEM_CALL_xEventGroupSetBits                     58
#define SYSTEM_CALL_xEventGroupSync                        59
#define SYSTEM_CALL_uxEventGroupGetNumber                  60
#define SYSTEM_CALL_vEventGroupSetNumber                   61
#define SYSTEM_CALL_xStreamBufferSend                      62
#define SYSTEM_CALL_xStreamBufferReceive                   63
#define SYSTEM_CALL_xStreamBufferIsFull                    64
#define SYSTEM_CALL_xStreamBufferIsEmpty                   65
#define SYSTEM_CALL_xStreamBufferSpacesAvailable           66
#define SYSTEM_CALL_xStreamBufferBytesAvailable            67
#define SYSTEM_CALL_xStreamBufferSetTriggerLevel           68
#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes    69
#define NUM_SYSTEM_CALLS                                   70  /* Total number of system calls. */

#endif /* MPU_SYSCALL_NUMBERS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef MPU_WRAPPERS_H
#define MPU_WRAPPERS_H

/* This file redefines API functions to be called through a wrapper macro, but
 * only for ports that are using the MPU. */
#if ( portUSING_MPU_WRAPPERS == 1 )

/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
 * included from queue.c or task.c to prevent it from having an effect within
 * those files. */
    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/*
 * Map standard (non MPU) API functions to equivalents that start
 * "MPU_".  This will cause the application code to call the MPU_
 * version, which wraps the non-MPU version with privilege promoting
 * then demoting code, so the kernel code always runs will full
 * privileges.
 */

/* Map standard task.h API functions to the MPU equivalents. */
        #define vTaskDelay                            MPU_vTaskDelay
        #define xTaskDelayUntil                       MPU_xTaskDelayUntil
        #define xTaskAbortDelay                       MPU_xTaskAbortDelay
        #define uxTaskPriorityGet                     MPU_uxTaskPriorityGet
        #define eTaskGetState                         MPU_eTaskGetState
        #define vTaskGetInfo                          MPU_vTaskGetInfo
        #define vTaskSuspend                          MPU_vTaskSuspend
        #define vTaskResume                           MPU_vTaskResume
        #define xTaskGetTickCount                     MPU_xTaskGetTickCount
        #define uxTaskGetNumberOfTasks                MPU_uxTaskGetNumberOfTasks
        #define uxTaskGetStackHighWaterMark           MPU_uxTaskGetStackHighWaterMark
        #define uxTaskGetStackHighWaterMark2          MPU_uxTaskGetStackHighWaterMark2
        #define vTaskSetApplicationTaskTag            MPU_vTaskSetApplicationTaskTag
        #define xTaskGetApplicationTaskTag            MPU_xTaskGetApplicationTaskTag
        #define vTaskSetThreadLocalStoragePointer     MPU_vTaskSetThreadLocalStoragePointer
        #define pvTaskGetThreadLocalStoragePointer    MPU_pvTaskGetThreadLocalStoragePointer
        #define xTaskGetIdleTaskHandle                MPU_xTaskGetIdleTaskHandle
        #define uxTaskGetSystemState                  MPU_uxTaskGetSystemState
        #define ulTaskGetIdleRunTimeCounter           MPU_ulTaskGetIdleRunTimeCounter
        #define ulTaskGetIdleRunTimePercent           MPU_ulTaskGetIdleRunTimePercent
        #define xTaskGenericNotify                    MPU_xTaskGenericNotify
        #define xTaskGenericNotifyWait                MPU_xTaskGenericNotifyWait
        #define ulTaskGenericNotifyTake               MPU_ulTaskGenericNotifyTake
        #define xTaskGenericNotifyStateClear          MPU_xTaskGenericNotifyStateClear
        #define ulTaskGenericNotifyValueClear         MPU_ulTaskGenericNotifyValueClear
        #define vTaskSetTimeOutState                  MPU_vTaskSetTimeOutState
        #define xTaskCheckForTimeOut                  MPU_xTaskCheckForTimeOut
        #define xTaskGetCurrentTaskHandle             MPU_xTaskGetCurrentTaskHandle
        #define xTaskGetSchedulerState                MPU_xTaskGetSchedulerState

        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define ulTaskGetRunTimeCounter           MPU_ulTaskGetRunTimeCounter
            #define ulTaskGetRunTimePercent           MPU_ulTaskGetRunTimePercent
        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

/* Privileged only wrappers for Task APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
        #define xTaskCreate                              MPU_xTaskCreate
        #define xTaskCreateStatic                        MPU_xTaskCreateStatic
        #define vTaskDelete                              MPU_vTaskDelete
        #define vTaskPrioritySet                         MPU_vTaskPrioritySet
        #define xTaskGetHandle                           MPU_xTaskGetHandle
        #define xTaskCallApplicationTaskHook             MPU_xTaskCallApplicationTaskHook

        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define pcTaskGetName                        MPU_pcTaskGetName
            #define xTaskCreateRestricted                MPU_xTaskCreateRestricted
            #define xTaskCreateRestrictedStatic          MPU_xTaskCreateRestrictedStatic
            #define vTaskAllocateMPURegions              MPU_vTaskAllocateMPURegions
            #define xTaskGetStaticBuffers                MPU_xTaskGetStaticBuffers
            #define uxTaskPriorityGetFromISR             MPU_uxTaskPriorityGetFromISR
            #define uxTaskBasePriorityGet                MPU_uxTaskBasePriorityGet
            #define uxTaskBasePriorityGetFromISR         MPU_uxTaskBasePriorityGetFromISR
            #define xTaskResumeFromISR                   MPU_xTaskResumeFromISR
            #define xTaskGetApplicationTaskTagFromISR    MPU_xTaskGetApplicationTaskTagFromISR
            #define xTaskGenericNotifyFromISR            MPU_xTaskGenericNotifyFromISR
            #define vTaskGenericNotifyGiveFromISR        MPU_vTaskGenericNotifyGiveFromISR
        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

/* Map standard queue.h API functions to the MPU equivalents. */
        #define xQueueGenericSend            MPU_xQueueGenericSend
        #define xQueueReceive                MPU_xQueueReceive
        #define xQueuePeek                   MPU_xQueuePeek
        #define xQueueSemaphoreTake          MPU_xQueueSemaphoreTake
        #define uxQueueMessagesWaiting       MPU_uxQueueMessagesWaiting
        #define uxQueueSpacesAvailable       MPU_uxQueueSpacesAvailable
        #define xQueueGetMutexHolder         MPU_xQueueGetMutexHolder
        #define xQueueTakeMutexRecursive     MPU_xQueueTakeMutexRecursive
        #define xQueueGiveMutexRecursive     MPU_xQueueGiveMutexRecursive
        #define xQueueAddToSet               MPU_xQueueAddToSet
        #define xQueueSelectFromSet          MPU_xQueueSelectFromSet

        #if ( configQUEUE_REGISTRY_SIZE > 0 )
            #define vQueueAddToRegistry      MPU_vQueueAddToRegistry
            #define vQueueUnregisterQueue    MPU_vQueueUnregisterQueue
            #define pcQueueGetName           MPU_pcQueueGetName
        #endif /* #if ( configQUEUE_REGISTRY_SIZE > 0 ) */

/* Privileged only wrappers for Queue APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
        #define vQueueDelete                           MPU_vQueueDelete
        #define xQueueCreateMutex                      MPU_xQueueCreateMutex
        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic
        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore
        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic
        #define xQueueGenericCreate                    MPU_xQueueGenericCreate
        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
        #define xQueueGenericReset                     MPU_xQueueGenericReset
        #define xQueueCreateSet                        MPU_xQueueCreateSet
        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet

        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define xQueueGenericGetStaticBuffers      MPU_xQueueGenericGetStaticBuffers
            #define xQueueGenericSendFromISR           MPU_xQueueGenericSendFromISR
            #define xQueueGiveFromISR                  MPU_xQueueGiveFromISR
            #define xQueuePeekFromISR                  MPU_xQueuePeekFromISR
            #define xQueueReceiveFromISR               MPU_xQueueReceiveFromISR
            #define xQueueIsQueueEmptyFromISR          MPU_xQueueIsQueueEmptyFromISR
            #define xQueueIsQueueFullFromISR           MPU_xQueueIsQueueFullFromISR
            #define uxQueueMessagesWaitingFromISR      MPU_uxQueueMessagesWaitingFromISR
            #define xQueueGetMutexHolderFromISR        MPU_xQueueGetMutexHolderFromISR
            #define xQueueSelectFromSetFromISR         MPU_xQueueSelectFromSetFromISR
        #endif /* if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

/* Map standard timer.h API functions to the MPU equivalents. */
        #define pvTimerGetTimerID                 MPU_pvTimerGetTimerID
        #define vTimerSetTimerID                  MPU_vTimerSetTimerID
        #define xTimerIsTimerActive               MPU_xTimerIsTimerActive
        #define xTimerGetTimerDaemonTaskHandle    MPU_xTimerGetTimerDaemonTaskHandle
        #define xTimerGenericCommandFromTask      MPU_xTimerGenericCommandFromTask
        #define pcTimerGetName                    MPU_pcTimerGetName
        #define vTimerSetReloadMode               MPU_vTimerSetReloadMode
        #define uxTimerGetReloadMode              MPU_uxTimerGetReloadMode
        #define xTimerGetPeriod                   MPU_xTimerGetPeriod
        #define xTimerGetExpiryTime               MPU_xTimerGetExpiryTime

/* Privileged only wrappers for Timer APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define xTimerGetReloadMode            MPU_xTimerGetReloadMode
            #define xTimerCreate                   MPU_xTimerCreate
            #define xTimerCreateStatic             MPU_xTimerCreateStatic
            #define xTimerGetStaticBuffer          MPU_xTimerGetStaticBuffer
            #define xTimerGenericCommandFromISR    MPU_xTimerGenericCommandFromISR
        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

/* Map standard event_group.h API functions to the MPU equivalents. */
        #define xEventGroupWaitBits          MPU_xEventGroupWaitBits
        #define xEventGroupClearBits         MPU_xEventGroupClearBits
        #define xEventGroupSetBits           MPU_xEventGroupSetBits
        #define xEventGroupSync              MPU_xEventGroupSync

        #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
            #define uxEventGroupGetNumber    MPU_uxEventGroupGetNumber
            #define vEventGroupSetNumber     MPU_vEventGroupSetNumber
        #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */

/* Privileged only wrappers for Event Group APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */
        #define xEventGroupCreate                  MPU_xEventGroupCreate
        #define xEventGroupCreateStatic            MPU_xEventGroupCreateStatic
        #define vEventGroupDelete                  MPU_vEventGroupDelete

        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define xEventGroupGetStaticBuffer     MPU_xEventGroupGetStaticBuffer
            #define xEventGroupClearBitsFromISR    MPU_xEventGroupClearBitsFromISR
            #define xEventGroupSetBitsFromISR      MPU_xEventGroupSetBitsFromISR
            #define xEventGroupGetBitsFromISR      MPU_xEventGroupGetBitsFromISR
        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

/* Map standard message/stream_buffer.h API functions to the MPU
 * equivalents. */
        #define xStreamBufferSend                      MPU_xStreamBufferSend
        #define xStreamBufferReceive                   MPU_xStreamBufferReceive
        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull
        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty
        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable
        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable
        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel
        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes

/* Privileged only wrappers for Stream Buffer APIs. These are needed so that
 * the application can use opaque handles maintained in mpu_wrappers.c
 * with all the APIs. */

        #define xStreamBufferGenericCreate                  MPU_xStreamBufferGenericCreate
        #define xStreamBufferGenericCreateStatic            MPU_xStreamBufferGenericCreateStatic
        #define vStreamBufferDelete                         MPU_vStreamBufferDelete
        #define xStreamBufferReset                          MPU_xStreamBufferReset

        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
            #define xStreamBufferGetStaticBuffers           MPU_xStreamBufferGetStaticBuffers
            #define xStreamBufferSendFromISR                MPU_xStreamBufferSendFromISR
            #define xStreamBufferReceiveFromISR             MPU_xStreamBufferReceiveFromISR
            #define xStreamBufferSendCompletedFromISR       MPU_xStreamBufferSendCompletedFromISR
            #define xStreamBufferReceiveCompletedFromISR    MPU_xStreamBufferReceiveCompletedFromISR
            #define xStreamBufferResetFromISR               MPU_xStreamBufferResetFromISR
        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */

        #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )

            #define vGrantAccessToTask( xTask, xTaskToGrantAccess )                        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
            #define vRevokeAccessToTask( xTask, xTaskToRevokeAccess )                      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToRevokeAccess ) )

            #define vGrantAccessToSemaphore( xTask, xSemaphoreToGrantAccess )              vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToGrantAccess ) )
            #define vRevokeAccessToSemaphore( xTask, xSemaphoreToRevokeAccess )            vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToRevokeAccess ) )

            #define vGrantAccessToQueue( xTask, xQueueToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToGrantAccess ) )
            #define vRevokeAccessToQueue( xTask, xQueueToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToRevokeAccess ) )

            #define vGrantAccessToQueueSet( xTask, xQueueSetToGrantAccess )                vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToGrantAccess ) )
            #define vRevokeAccessToQueueSet( xTask, xQueueSetToRevokeAccess )              vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToRevokeAccess ) )

            #define vGrantAccessToEventGroup( xTask, xEventGroupToGrantAccess )            vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToGrantAccess ) )
            #define vRevokeAccessToEventGroup( xTask, xEventGroupToRevokeAccess )          vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToRevokeAccess ) )

            #define vGrantAccessToStreamBuffer( xTask, xStreamBufferToGrantAccess )        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToGrantAccess ) )
            #define vRevokeAccessToStreamBuffer( xTask, xStreamBufferToRevokeAccess )      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToRevokeAccess ) )

            #define vGrantAccessToMessageBuffer( xTask, xMessageBufferToGrantAccess )      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToGrantAccess ) )
            #define vRevokeAccessToMessageBuffer( xTask, xMessageBufferToRevokeAccess )    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToRevokeAccess ) )

            #define vGrantAccessToTimer( xTask, xTimerToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToGrantAccess ) )
            #define vRevokeAccessToTimer( xTask, xTimerToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToRevokeAccess ) )

        #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */

    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */

    #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
    #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
    #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )

#else /* portUSING_MPU_WRAPPERS */

    #define PRIVILEGED_FUNCTION
    #define PRIVILEGED_DATA
    #define FREERTOS_SYSTEM_CALL

#endif /* portUSING_MPU_WRAPPERS */


#endif /* MPU_WRAPPERS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/newlib-freertos.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef INC_NEWLIB_FREERTOS_H
#define INC_NEWLIB_FREERTOS_H

/* Note Newlib support has been included by popular demand, but is not
 * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
 * responsible for resulting newlib operation.  User must be familiar with
 * newlib and must provide system-wide implementations of the necessary
 * stubs. Be warned that (at the time of writing) the current newlib design
 * implements a system-wide malloc() that must be provided with locks.
 *
 * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
 * for additional information. */

#include 

#define configUSE_C_RUNTIME_TLS_SUPPORT    1

#ifndef configTLS_BLOCK_TYPE
    #define configTLS_BLOCK_TYPE           struct _reent
#endif

#ifndef configINIT_TLS_BLOCK
    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )    _REENT_INIT_PTR( &( xTLSBlock ) )
#endif

#ifndef configSET_TLS_BLOCK
    #define configSET_TLS_BLOCK( xTLSBlock )    ( _impure_ptr = &( xTLSBlock ) )
#endif

#ifndef configDEINIT_TLS_BLOCK
    #define configDEINIT_TLS_BLOCK( xTLSBlock )    _reclaim_reent( &( xTLSBlock ) )
#endif

#endif /* INC_NEWLIB_FREERTOS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/picolibc-freertos.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef INC_PICOLIBC_FREERTOS_H
#define INC_PICOLIBC_FREERTOS_H

/* Use picolibc TLS support to allocate space for __thread variables,
 * initialize them at thread creation and set the TLS context at
 * thread switch time.
 *
 * See the picolibc TLS docs:
 * https://github.com/picolibc/picolibc/blob/main/doc/tls.md
 * for additional information. */

#include 

#define configUSE_C_RUNTIME_TLS_SUPPORT    1

#define configTLS_BLOCK_TYPE               void *

#define picolibcTLS_SIZE                   ( ( portPOINTER_SIZE_TYPE ) _tls_size() )
#define picolibcSTACK_ALIGNMENT_MASK       ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK )

#if __PICOLIBC_MAJOR__ > 1 || __PICOLIBC_MINOR__ >= 8

/* Picolibc 1.8 and newer have explicit alignment values provided
 * by the _tls_align() inline */
    #define picolibcTLS_ALIGNMENT_MASK    ( ( portPOINTER_SIZE_TYPE ) ( _tls_align() - 1 ) )
#else

/* For older Picolibc versions, use the general port alignment value */
    #define picolibcTLS_ALIGNMENT_MASK    ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK )
#endif

/* Allocate thread local storage block off the end of the
 * stack. The picolibcTLS_SIZE macro returns the size (in
 * bytes) of the total TLS area used by the application.
 * Calculate the top of stack address. */
#if ( portSTACK_GROWTH < 0 )

    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                  \
    do {                                                                                     \
        xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) -              \
                                   picolibcTLS_SIZE ) &                                      \
                                 ~picolibcTLS_ALIGNMENT_MASK );                              \
        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \
                                           ~picolibcSTACK_ALIGNMENT_MASK );                  \
        _init_tls( xTLSBlock );                                                              \
    } while( 0 )
#else /* portSTACK_GROWTH */
    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                          \
    do {                                                                                             \
        xTLSBlock = ( void * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack +                          \
                                   picolibcTLS_ALIGNMENT_MASK ) & ~picolibcTLS_ALIGNMENT_MASK );     \
        pxTopOfStack = ( StackType_t * ) ( ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) +             \
                                               picolibcTLS_SIZE ) + picolibcSTACK_ALIGNMENT_MASK ) & \
                                           ~picolibcSTACK_ALIGNMENT_MASK );                          \
        _init_tls( xTLSBlock );                                                                      \
    } while( 0 )
#endif /* portSTACK_GROWTH */

#define configSET_TLS_BLOCK( xTLSBlock )    _set_tls( xTLSBlock )

#define configDEINIT_TLS_BLOCK( xTLSBlock )

#endif /* INC_PICOLIBC_FREERTOS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/*-----------------------------------------------------------
 * Portable layer API.  Each function must be defined for each port.
 *----------------------------------------------------------*/

#ifndef PORTABLE_H
#define PORTABLE_H

/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
 * pre-processor definition was used to ensure the pre-processor found the correct
 * portmacro.h file for the port being used.  That scheme was deprecated in favour
 * of setting the compiler's include path such that it found the correct
 * portmacro.h file - removing the need for the constant and allowing the
 * portmacro.h file to be located anywhere in relation to the port being used.
 * Purely for reasons of backward compatibility the old method is still valid, but
 * to make it clear that new projects should not use it, support for the port
 * specific constants has been moved into the deprecated_definitions.h header
 * file. */

/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
 * did not result in a portmacro.h header file being included - and it should be
 * included here.  In this case the path to the correct portmacro.h header file
 * must be set in the compiler's include path. */
#ifndef portENTER_CRITICAL
#include "portmacro.h"
#endif

#if portBYTE_ALIGNMENT == 32
#define portBYTE_ALIGNMENT_MASK (0x001f)
#elif portBYTE_ALIGNMENT == 16
#define portBYTE_ALIGNMENT_MASK (0x000f)
#elif portBYTE_ALIGNMENT == 8
#define portBYTE_ALIGNMENT_MASK (0x0007)
#elif portBYTE_ALIGNMENT == 4
#define portBYTE_ALIGNMENT_MASK (0x0003)
#elif portBYTE_ALIGNMENT == 2
#define portBYTE_ALIGNMENT_MASK (0x0001)
#elif portBYTE_ALIGNMENT == 1
#define portBYTE_ALIGNMENT_MASK (0x0000)
#else /* if portBYTE_ALIGNMENT == 32 */
#error "Invalid portBYTE_ALIGNMENT definition"
#endif /* if portBYTE_ALIGNMENT == 32 */

#ifndef portUSING_MPU_WRAPPERS
#define portUSING_MPU_WRAPPERS 0
#endif

#ifndef portNUM_CONFIGURABLE_REGIONS
#define portNUM_CONFIGURABLE_REGIONS 1
#endif

#ifndef portHAS_STACK_OVERFLOW_CHECKING
#define portHAS_STACK_OVERFLOW_CHECKING 0
#endif

#ifndef portARCH_NAME
#define portARCH_NAME NULL
#endif

#ifndef configSTACK_DEPTH_TYPE
#define configSTACK_DEPTH_TYPE StackType_t
#endif

#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
/* Defaults to 0 for backward compatibility. */
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#endif

/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */

#include "mpu_wrappers.h"

/*
 * Setup the stack of a new task so it is ready to be placed under the
 * scheduler control.  The registers have to be placed on the stack in
 * the order that the port expects to find them.
 *
 */
#if (portUSING_MPU_WRAPPERS == 1)
#if (portHAS_STACK_OVERFLOW_CHECKING == 1)
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged,
                                   xMPU_SETTINGS *xMPUSettings) PRIVILEGED_FUNCTION;
#else
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged, xMPU_SETTINGS *xMPUSettings) PRIVILEGED_FUNCTION;
#endif /* if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) */
#else  /* if ( portUSING_MPU_WRAPPERS == 1 ) */
#if (portHAS_STACK_OVERFLOW_CHECKING == 1)
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters) PRIVILEGED_FUNCTION;
#else
StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters) PRIVILEGED_FUNCTION;
#endif
#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */

/* Used by heap_5.c to define the start address and size of each memory region
 * that together comprise the total FreeRTOS heap space. */
typedef struct HeapRegion {
  uint8_t *pucStartAddress;
  size_t   xSizeInBytes;
} HeapRegion_t;

/* Used to pass information about the heap out of vPortGetHeapStats(). */
typedef struct xHeapStats {
  size_t xAvailableHeapSpaceInBytes;      /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
  size_t xSizeOfLargestFreeBlockInBytes;  /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
  size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
  size_t xNumberOfFreeBlocks;             /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
  size_t xMinimumEverFreeBytesRemaining;  /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
  size_t xNumberOfSuccessfulAllocations;  /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
  size_t xNumberOfSuccessfulFrees;        /* The number of calls to vPortFree() that has successfully freed a block of memory. */
} HeapStats_t;

/*
 * Used to define multiple heap regions for use by heap_5.c.  This function
 * must be called before any calls to pvPortMalloc() - not creating a task,
 * queue, semaphore, mutex, software timer, event group, etc. will result in
 * pvPortMalloc being called.
 *
 * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
 * defines a region of memory that can be used as the heap.  The array is
 * terminated by a HeapRegions_t structure that has a size of 0.  The region
 * with the lowest start address must appear first in the array.
 */
void vPortDefineHeapRegions(const HeapRegion_t *const pxHeapRegions) PRIVILEGED_FUNCTION;

/*
 * Returns a HeapStats_t structure filled with information about the current
 * heap state.
 */
void vPortGetHeapStats(HeapStats_t *pxHeapStats);

/*
 * Map to the memory management routines required for the port.
 */
void  *pvPortMalloc(size_t xWantedSize) PRIVILEGED_FUNCTION;
void  *pvPortCalloc(size_t xNum, size_t xSize) PRIVILEGED_FUNCTION;
void   vPortFree(void *pv) PRIVILEGED_FUNCTION;
void   vPortInitialiseBlocks(void) PRIVILEGED_FUNCTION;
size_t xPortGetFreeHeapSize(void) PRIVILEGED_FUNCTION;
size_t xPortGetMinimumEverFreeHeapSize(void) PRIVILEGED_FUNCTION;

#if (configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1)
void *pvPortMallocStack(size_t xSize) PRIVILEGED_FUNCTION;
void  vPortFreeStack(void *pv) PRIVILEGED_FUNCTION;
#else
#define pvPortMallocStack pvPortMalloc
#define vPortFreeStack    vPortFree
#endif

/*
 * This function resets the internal state of the heap module. It must be called
 * by the application before restarting the scheduler.
 */
void vPortHeapResetState(void) PRIVILEGED_FUNCTION;

#if (configUSE_MALLOC_FAILED_HOOK == 1)

/**
 * task.h
 * @code{c}
 * void vApplicationMallocFailedHook( void )
 * @endcode
 *
 * This hook function is called when allocation failed.
 */
void vApplicationMallocFailedHook(void);
#endif

/*
 * Setup the hardware ready for the scheduler to take control.  This generally
 * sets up a tick interrupt and sets timers for the correct tick frequency.
 */
BaseType_t xPortStartScheduler(void) PRIVILEGED_FUNCTION;

/*
 * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
 * the hardware is left in its original condition after the scheduler stops
 * executing.
 */
void vPortEndScheduler(void) PRIVILEGED_FUNCTION;

/*
 * The structures and methods of manipulating the MPU are contained within the
 * port layer.
 *
 * Fills the xMPUSettings structure with the memory region information
 * contained in xRegions.
 */
#if (portUSING_MPU_WRAPPERS == 1)
struct xMEMORY_REGION;
void vPortStoreTaskMPUSettings(xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION *const xRegions, StackType_t *pxBottomOfStack, configSTACK_DEPTH_TYPE uxStackDepth) PRIVILEGED_FUNCTION;
#endif

/**
 * @brief Checks if the calling task is authorized to access the given buffer.
 *
 * @param pvBuffer The buffer which the calling task wants to access.
 * @param ulBufferLength The length of the pvBuffer.
 * @param ulAccessRequested The permissions that the calling task wants.
 *
 * @return pdTRUE if the calling task is authorized to access the buffer,
 *         pdFALSE otherwise.
 */
#if (portUSING_MPU_WRAPPERS == 1)
BaseType_t xPortIsAuthorizedToAccessBuffer(const void *pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested) PRIVILEGED_FUNCTION;
#endif

/**
 * @brief Checks if the calling task is authorized to access the given kernel object.
 *
 * @param lInternalIndexOfKernelObject The index of the kernel object in the kernel
 *                                     object handle pool.
 *
 * @return pdTRUE if the calling task is authorized to access the kernel object,
 *         pdFALSE otherwise.
 */
#if ((portUSING_MPU_WRAPPERS == 1) && (configUSE_MPU_WRAPPERS_V1 == 0))

BaseType_t xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject) PRIVILEGED_FUNCTION;

#endif

/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */

#endif /* PORTABLE_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef PROJDEFS_H
#define PROJDEFS_H

/*
 * Defines the prototype to which task functions must conform.  Defined in this
 * file to ensure the type is known before portable.h is included.
 */
typedef void (* TaskFunction_t)( void * arg );

/* Converts a time in milliseconds to a time in ticks.  This macro can be
 * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
 * definition here is not suitable for your application. */
#ifndef pdMS_TO_TICKS
    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) )
#endif

/* Converts a time in ticks to a time in milliseconds.  This macro can be
 * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
 * definition here is not suitable for your application. */
#ifndef pdTICKS_TO_MS
    #define pdTICKS_TO_MS( xTimeInTicks )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) )
#endif

#define pdFALSE                                  ( ( BaseType_t ) 0 )
#define pdTRUE                                   ( ( BaseType_t ) 1 )
#define pdFALSE_SIGNED                           ( ( BaseType_t ) 0 )
#define pdTRUE_SIGNED                            ( ( BaseType_t ) 1 )
#define pdFALSE_UNSIGNED                         ( ( UBaseType_t ) 0 )
#define pdTRUE_UNSIGNED                          ( ( UBaseType_t ) 1 )

#define pdPASS                                   ( pdTRUE )
#define pdFAIL                                   ( pdFALSE )
#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )
#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )

/* FreeRTOS error definitions. */
#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )
#define errQUEUE_BLOCKED                         ( -4 )
#define errQUEUE_YIELD                           ( -5 )

/* Macros used for basic data corruption checks. */
#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0
#endif

#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
    #define pdINTEGRITY_CHECK_VALUE    0x5a5a
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5a5a5a5a5aULL
#else
    #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif

/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
 * itself. */
#define pdFREERTOS_ERRNO_NONE             0   /* No errors */
#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */
#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */
#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */
#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */
#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */
#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */
#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */
#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */
#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */
#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */
#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */
#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */
#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */
#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */
#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */
#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */
#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */
#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */
#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */
#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */
#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */
#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */
#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */
#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */
#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */
#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */
#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */
#define pdFREERTOS_ERRNO_EAFNOSUPPORT     97  /* Address family not supported by protocol */
#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */
#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */
#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */
#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */
#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */
#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */
#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */
#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */
#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */
#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */
#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */
#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */

/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
 * itself. */
#define pdFREERTOS_LITTLE_ENDIAN          0
#define pdFREERTOS_BIG_ENDIAN             1

/* Re-defining endian values for generic naming. */
#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN
#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN


#endif /* PROJDEFS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


#ifndef QUEUE_H
#define QUEUE_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h" must appear in source files before "include queue.h"
#endif

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

#include "task.h"

/**
 * Type by which queues are referenced.  For example, a call to xQueueCreate()
 * returns an QueueHandle_t variable that can then be used as a parameter to
 * xQueueSend(), xQueueReceive(), etc.
 */
struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
typedef struct QueueDefinition   * QueueHandle_t;

/**
 * Type by which queue sets are referenced.  For example, a call to
 * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
 * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
 */
typedef struct QueueDefinition   * QueueSetHandle_t;

/**
 * Queue sets can contain both queues and semaphores, so the
 * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
 * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
 */
typedef struct QueueDefinition   * QueueSetMemberHandle_t;

/* For internal use only. */
#define queueSEND_TO_BACK                     ( ( BaseType_t ) 0 )
#define queueSEND_TO_FRONT                    ( ( BaseType_t ) 1 )
#define queueOVERWRITE                        ( ( BaseType_t ) 2 )

/* For internal use only.  These definitions *must* match those in queue.c. */
#define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
#define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
#define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
#define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
#define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )

/**
 * queue. h
 * @code{c}
 * QueueHandle_t xQueueCreate(
 *                            UBaseType_t uxQueueLength,
 *                            UBaseType_t uxItemSize
 *                        );
 * @endcode
 *
 * Creates a new queue instance, and returns a handle by which the new queue
 * can be referenced.
 *
 * Internally, within the FreeRTOS implementation, queues use two blocks of
 * memory.  The first block is used to hold the queue's data structures.  The
 * second block is used to hold items placed into the queue.  If a queue is
 * created using xQueueCreate() then both blocks of memory are automatically
 * dynamically allocated inside the xQueueCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
 * xQueueCreateStatic() then the application writer must provide the memory that
 * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
 * be created without using any dynamic memory allocation.
 *
 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
 *
 * @param uxQueueLength The maximum number of items that the queue can contain.
 *
 * @param uxItemSize The number of bytes each item in the queue will require.
 * Items are queued by copy, not by reference, so this is the number of bytes
 * that will be copied for each posted item.  Each item on the queue must be
 * the same size.
 *
 * @return If the queue is successfully create then a handle to the newly
 * created queue is returned.  If the queue cannot be created then 0 is
 * returned.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * };
 *
 * void vATask( void *pvParameters )
 * {
 * QueueHandle_t xQueue1, xQueue2;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
 *  if( xQueue1 == 0 )
 *  {
 *      // Queue was not created and must not be used.
 *  }
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *  if( xQueue2 == 0 )
 *  {
 *      // Queue was not created and must not be used.
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueCreate xQueueCreate
 * \ingroup QueueManagement
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    #define xQueueCreate( uxQueueLength, uxItemSize )    xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
#endif

/**
 * queue. h
 * @code{c}
 * QueueHandle_t xQueueCreateStatic(
 *                            UBaseType_t uxQueueLength,
 *                            UBaseType_t uxItemSize,
 *                            uint8_t *pucQueueStorage,
 *                            StaticQueue_t *pxQueueBuffer
 *                        );
 * @endcode
 *
 * Creates a new queue instance, and returns a handle by which the new queue
 * can be referenced.
 *
 * Internally, within the FreeRTOS implementation, queues use two blocks of
 * memory.  The first block is used to hold the queue's data structures.  The
 * second block is used to hold items placed into the queue.  If a queue is
 * created using xQueueCreate() then both blocks of memory are automatically
 * dynamically allocated inside the xQueueCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
 * xQueueCreateStatic() then the application writer must provide the memory that
 * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
 * be created without using any dynamic memory allocation.
 *
 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
 *
 * @param uxQueueLength The maximum number of items that the queue can contain.
 *
 * @param uxItemSize The number of bytes each item in the queue will require.
 * Items are queued by copy, not by reference, so this is the number of bytes
 * that will be copied for each posted item.  Each item on the queue must be
 * the same size.
 *
 * @param pucQueueStorage If uxItemSize is not zero then
 * pucQueueStorage must point to a uint8_t array that is at least large
 * enough to hold the maximum number of items that can be in the queue at any
 * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
 * zero then pucQueueStorage can be NULL.
 *
 * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
 * will be used to hold the queue's data structure.
 *
 * @return If the queue is created then a handle to the created queue is
 * returned.  If pxQueueBuffer is NULL then NULL is returned.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * };
 *
 #define QUEUE_LENGTH 10
 #define ITEM_SIZE sizeof( uint32_t )
 *
 * // xQueueBuffer will hold the queue structure.
 * StaticQueue_t xQueueBuffer;
 *
 * // ucQueueStorage will hold the items posted to the queue.  Must be at least
 * // [(queue length) * ( queue item size)] bytes long.
 * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
 *
 * void vATask( void *pvParameters )
 * {
 *  QueueHandle_t xQueue1;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
 *                          ITEM_SIZE     // The size of each item in the queue
 *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
 *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
 *
 *  // The queue is guaranteed to be created successfully as no dynamic memory
 *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueCreateStatic xQueueCreateStatic
 * \ingroup QueueManagement
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer )    xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueGetStaticBuffers( QueueHandle_t xQueue,
 *                                    uint8_t ** ppucQueueStorage,
 *                                    StaticQueue_t ** ppxStaticQueue );
 * @endcode
 *
 * Retrieve pointers to a statically created queue's data structure buffer
 * and storage area buffer. These are the same buffers that are supplied
 * at the time of creation.
 *
 * @param xQueue The queue for which to retrieve the buffers.
 *
 * @param ppucQueueStorage Used to return a pointer to the queue's storage
 * area buffer.
 *
 * @param ppxStaticQueue Used to return a pointer to the queue's data
 * structure buffer.
 *
 * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
 *
 * \defgroup xQueueGetStaticBuffers xQueueGetStaticBuffers
 * \ingroup QueueManagement
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xQueueGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue )    xQueueGenericGetStaticBuffers( ( xQueue ), ( ppucQueueStorage ), ( ppxStaticQueue ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSendToFront(
 *                                 QueueHandle_t    xQueue,
 *                                 const void       *pvItemToQueue,
 *                                 TickType_t       xTicksToWait
 *                             );
 * @endcode
 *
 * Post an item to the front of a queue.  The item is queued by copy, not by
 * reference.  This function must not be called from an interrupt service
 * routine.  See xQueueSendFromISR () for an alternative which may be used
 * in an ISR.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for space to become available on the queue, should it already
 * be full.  The call will return immediately if this is set to 0 and the
 * queue is full.  The time is defined in tick periods so the constant
 * portTICK_PERIOD_MS should be used to convert to real time if this is required.
 *
 * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * uint32_t ulVar = 10U;
 *
 * void vATask( void *pvParameters )
 * {
 * QueueHandle_t xQueue1, xQueue2;
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *
 *  // ...
 *
 *  if( xQueue1 != 0 )
 *  {
 *      // Send an uint32_t.  Wait for 10 ticks for space to become
 *      // available if necessary.
 *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
 *      {
 *          // Failed to post the message, even after 10 ticks.
 *      }
 *  }
 *
 *  if( xQueue2 != 0 )
 *  {
 *      // Send a pointer to a struct AMessage object.  Don't block if the
 *      // queue is already full.
 *      pxMessage = & xMessage;
 *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueSend xQueueSend
 * \ingroup QueueManagement
 */
#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \
    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSendToBack(
 *                                 QueueHandle_t    xQueue,
 *                                 const void       *pvItemToQueue,
 *                                 TickType_t       xTicksToWait
 *                             );
 * @endcode
 *
 * This is a macro that calls xQueueGenericSend().
 *
 * Post an item to the back of a queue.  The item is queued by copy, not by
 * reference.  This function must not be called from an interrupt service
 * routine.  See xQueueSendFromISR () for an alternative which may be used
 * in an ISR.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for space to become available on the queue, should it already
 * be full.  The call will return immediately if this is set to 0 and the queue
 * is full.  The  time is defined in tick periods so the constant
 * portTICK_PERIOD_MS should be used to convert to real time if this is required.
 *
 * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * uint32_t ulVar = 10U;
 *
 * void vATask( void *pvParameters )
 * {
 * QueueHandle_t xQueue1, xQueue2;
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *
 *  // ...
 *
 *  if( xQueue1 != 0 )
 *  {
 *      // Send an uint32_t.  Wait for 10 ticks for space to become
 *      // available if necessary.
 *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
 *      {
 *          // Failed to post the message, even after 10 ticks.
 *      }
 *  }
 *
 *  if( xQueue2 != 0 )
 *  {
 *      // Send a pointer to a struct AMessage object.  Don't block if the
 *      // queue is already full.
 *      pxMessage = & xMessage;
 *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueSend xQueueSend
 * \ingroup QueueManagement
 */
#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \
    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSend(
 *                            QueueHandle_t xQueue,
 *                            const void * pvItemToQueue,
 *                            TickType_t xTicksToWait
 *                       );
 * @endcode
 *
 * This is a macro that calls xQueueGenericSend().  It is included for
 * backward compatibility with versions of FreeRTOS.org that did not
 * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
 * equivalent to xQueueSendToBack().
 *
 * Post an item on a queue.  The item is queued by copy, not by reference.
 * This function must not be called from an interrupt service routine.
 * See xQueueSendFromISR () for an alternative which may be used in an ISR.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for space to become available on the queue, should it already
 * be full.  The call will return immediately if this is set to 0 and the
 * queue is full.  The time is defined in tick periods so the constant
 * portTICK_PERIOD_MS should be used to convert to real time if this is required.
 *
 * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * uint32_t ulVar = 10U;
 *
 * void vATask( void *pvParameters )
 * {
 * QueueHandle_t xQueue1, xQueue2;
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *
 *  // ...
 *
 *  if( xQueue1 != 0 )
 *  {
 *      // Send an uint32_t.  Wait for 10 ticks for space to become
 *      // available if necessary.
 *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
 *      {
 *          // Failed to post the message, even after 10 ticks.
 *      }
 *  }
 *
 *  if( xQueue2 != 0 )
 *  {
 *      // Send a pointer to a struct AMessage object.  Don't block if the
 *      // queue is already full.
 *      pxMessage = & xMessage;
 *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueSend xQueueSend
 * \ingroup QueueManagement
 */
#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \
    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueOverwrite(
 *                            QueueHandle_t xQueue,
 *                            const void * pvItemToQueue
 *                       );
 * @endcode
 *
 * Only for use with queues that have a length of one - so the queue is either
 * empty or full.
 *
 * Post an item on a queue.  If the queue is already full then overwrite the
 * value held in the queue.  The item is queued by copy, not by reference.
 *
 * This function must not be called from an interrupt service routine.
 * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
 *
 * @param xQueue The handle of the queue to which the data is being sent.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
 * therefore has the same return values as xQueueSendToFront().  However, pdPASS
 * is the only value that can be returned because xQueueOverwrite() will write
 * to the queue even when the queue is already full.
 *
 * Example usage:
 * @code{c}
 *
 * void vFunction( void *pvParameters )
 * {
 * QueueHandle_t xQueue;
 * uint32_t ulVarToSend, ulValReceived;
 *
 *  // Create a queue to hold one uint32_t value.  It is strongly
 *  // recommended *not* to use xQueueOverwrite() on queues that can
 *  // contain more than one value, and doing so will trigger an assertion
 *  // if configASSERT() is defined.
 *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
 *
 *  // Write the value 10 to the queue using xQueueOverwrite().
 *  ulVarToSend = 10;
 *  xQueueOverwrite( xQueue, &ulVarToSend );
 *
 *  // Peeking the queue should now return 10, but leave the value 10 in
 *  // the queue.  A block time of zero is used as it is known that the
 *  // queue holds a value.
 *  ulValReceived = 0;
 *  xQueuePeek( xQueue, &ulValReceived, 0 );
 *
 *  if( ulValReceived != 10 )
 *  {
 *      // Error unless the item was removed by a different task.
 *  }
 *
 *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
 *  // value held in the queue with 100.
 *  ulVarToSend = 100;
 *  xQueueOverwrite( xQueue, &ulVarToSend );
 *
 *  // This time read from the queue, leaving the queue empty once more.
 *  // A block time of 0 is used again.
 *  xQueueReceive( xQueue, &ulValReceived, 0 );
 *
 *  // The value read should be the last value written, even though the
 *  // queue was already full when the value was written.
 *  if( ulValReceived != 100 )
 *  {
 *      // Error!
 *  }
 *
 *  // ...
 * }
 * @endcode
 * \defgroup xQueueOverwrite xQueueOverwrite
 * \ingroup QueueManagement
 */
#define xQueueOverwrite( xQueue, pvItemToQueue ) \
    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )


/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueGenericSend(
 *                                  QueueHandle_t xQueue,
 *                                  const void * pvItemToQueue,
 *                                  TickType_t xTicksToWait
 *                                  BaseType_t xCopyPosition
 *                              );
 * @endcode
 *
 * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
 * xQueueSendToBack() are used in place of calling this function directly.
 *
 * Post an item on a queue.  The item is queued by copy, not by reference.
 * This function must not be called from an interrupt service routine.
 * See xQueueSendFromISR () for an alternative which may be used in an ISR.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for space to become available on the queue, should it already
 * be full.  The call will return immediately if this is set to 0 and the
 * queue is full.  The time is defined in tick periods so the constant
 * portTICK_PERIOD_MS should be used to convert to real time if this is required.
 *
 * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
 * item at the back of the queue, or queueSEND_TO_FRONT to place the item
 * at the front of the queue (for high priority messages).
 *
 * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * uint32_t ulVar = 10U;
 *
 * void vATask( void *pvParameters )
 * {
 * QueueHandle_t xQueue1, xQueue2;
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 uint32_t values.
 *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *
 *  // ...
 *
 *  if( xQueue1 != 0 )
 *  {
 *      // Send an uint32_t.  Wait for 10 ticks for space to become
 *      // available if necessary.
 *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
 *      {
 *          // Failed to post the message, even after 10 ticks.
 *      }
 *  }
 *
 *  if( xQueue2 != 0 )
 *  {
 *      // Send a pointer to a struct AMessage object.  Don't block if the
 *      // queue is already full.
 *      pxMessage = & xMessage;
 *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueSend xQueueSend
 * \ingroup QueueManagement
 */
BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                              const void * const pvItemToQueue,
                              TickType_t xTicksToWait,
                              const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueuePeek(
 *                           QueueHandle_t xQueue,
 *                           void * const pvBuffer,
 *                           TickType_t xTicksToWait
 *                       );
 * @endcode
 *
 * Receive an item from a queue without removing the item from the queue.
 * The item is received by copy so a buffer of adequate size must be
 * provided.  The number of bytes copied into the buffer was defined when
 * the queue was created.
 *
 * Successfully received items remain on the queue so will be returned again
 * by the next call, or a call to xQueueReceive().
 *
 * This macro must not be used in an interrupt service routine.  See
 * xQueuePeekFromISR() for an alternative that can be called from an interrupt
 * service routine.
 *
 * @param xQueue The handle to the queue from which the item is to be
 * received.
 *
 * @param pvBuffer Pointer to the buffer into which the received item will
 * be copied.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for an item to receive should the queue be empty at the time
 * of the call. The time is defined in tick periods so the constant
 * portTICK_PERIOD_MS should be used to convert to real time if this is required.
 * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
 * is empty.
 *
 * @return pdTRUE if an item was successfully received from the queue,
 * otherwise pdFALSE.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * QueueHandle_t xQueue;
 *
 * // Task to create a queue and post a value.
 * void vATask( void *pvParameters )
 * {
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *  if( xQueue == 0 )
 *  {
 *      // Failed to create the queue.
 *  }
 *
 *  // ...
 *
 *  // Send a pointer to a struct AMessage object.  Don't block if the
 *  // queue is already full.
 *  pxMessage = & xMessage;
 *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
 *
 *  // ... Rest of task code.
 * }
 *
 * // Task to peek the data from the queue.
 * void vADifferentTask( void *pvParameters )
 * {
 * struct AMessage *pxRxedMessage;
 *
 *  if( xQueue != 0 )
 *  {
 *      // Peek a message on the created queue.  Block for 10 ticks if a
 *      // message is not immediately available.
 *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
 *      {
 *          // pcRxedMessage now points to the struct AMessage variable posted
 *          // by vATask, but the item still remains on the queue.
 *      }
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueuePeek xQueuePeek
 * \ingroup QueueManagement
 */
BaseType_t xQueuePeek( QueueHandle_t xQueue,
                       void * const pvBuffer,
                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueuePeekFromISR(
 *                                  QueueHandle_t xQueue,
 *                                  void *pvBuffer,
 *                              );
 * @endcode
 *
 * A version of xQueuePeek() that can be called from an interrupt service
 * routine (ISR).
 *
 * Receive an item from a queue without removing the item from the queue.
 * The item is received by copy so a buffer of adequate size must be
 * provided.  The number of bytes copied into the buffer was defined when
 * the queue was created.
 *
 * Successfully received items remain on the queue so will be returned again
 * by the next call, or a call to xQueueReceive().
 *
 * @param xQueue The handle to the queue from which the item is to be
 * received.
 *
 * @param pvBuffer Pointer to the buffer into which the received item will
 * be copied.
 *
 * @return pdTRUE if an item was successfully received from the queue,
 * otherwise pdFALSE.
 *
 * \defgroup xQueuePeekFromISR xQueuePeekFromISR
 * \ingroup QueueManagement
 */
BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
                              void * const pvBuffer ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueReceive(
 *                               QueueHandle_t xQueue,
 *                               void *pvBuffer,
 *                               TickType_t xTicksToWait
 *                          );
 * @endcode
 *
 * Receive an item from a queue.  The item is received by copy so a buffer of
 * adequate size must be provided.  The number of bytes copied into the buffer
 * was defined when the queue was created.
 *
 * Successfully received items are removed from the queue.
 *
 * This function must not be used in an interrupt service routine.  See
 * xQueueReceiveFromISR for an alternative that can.
 *
 * @param xQueue The handle to the queue from which the item is to be
 * received.
 *
 * @param pvBuffer Pointer to the buffer into which the received item will
 * be copied.
 *
 * @param xTicksToWait The maximum amount of time the task should block
 * waiting for an item to receive should the queue be empty at the time
 * of the call. xQueueReceive() will return immediately if xTicksToWait
 * is zero and the queue is empty.  The time is defined in tick periods so the
 * constant portTICK_PERIOD_MS should be used to convert to real time if this is
 * required.
 *
 * @return pdTRUE if an item was successfully received from the queue,
 * otherwise pdFALSE.
 *
 * Example usage:
 * @code{c}
 * struct AMessage
 * {
 *  char ucMessageID;
 *  char ucData[ 20 ];
 * } xMessage;
 *
 * QueueHandle_t xQueue;
 *
 * // Task to create a queue and post a value.
 * void vATask( void *pvParameters )
 * {
 * struct AMessage *pxMessage;
 *
 *  // Create a queue capable of containing 10 pointers to AMessage structures.
 *  // These should be passed by pointer as they contain a lot of data.
 *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
 *  if( xQueue == 0 )
 *  {
 *      // Failed to create the queue.
 *  }
 *
 *  // ...
 *
 *  // Send a pointer to a struct AMessage object.  Don't block if the
 *  // queue is already full.
 *  pxMessage = & xMessage;
 *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
 *
 *  // ... Rest of task code.
 * }
 *
 * // Task to receive from the queue.
 * void vADifferentTask( void *pvParameters )
 * {
 * struct AMessage *pxRxedMessage;
 *
 *  if( xQueue != 0 )
 *  {
 *      // Receive a message on the created queue.  Block for 10 ticks if a
 *      // message is not immediately available.
 *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
 *      {
 *          // pcRxedMessage now points to the struct AMessage variable posted
 *          // by vATask.
 *      }
 *  }
 *
 *  // ... Rest of task code.
 * }
 * @endcode
 * \defgroup xQueueReceive xQueueReceive
 * \ingroup QueueManagement
 */
BaseType_t xQueueReceive( QueueHandle_t xQueue,
                          void * const pvBuffer,
                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
 * @endcode
 *
 * Return the number of messages stored in a queue.
 *
 * @param xQueue A handle to the queue being queried.
 *
 * @return The number of messages available in the queue.
 *
 * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
 * \ingroup QueueManagement
 */
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
 * @endcode
 *
 * Return the number of free spaces available in a queue.  This is equal to the
 * number of items that can be sent to the queue before the queue becomes full
 * if no items are removed.
 *
 * @param xQueue A handle to the queue being queried.
 *
 * @return The number of spaces available in the queue.
 *
 * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
 * \ingroup QueueManagement
 */
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * void vQueueDelete( QueueHandle_t xQueue );
 * @endcode
 *
 * Delete a queue - freeing all the memory allocated for storing of items
 * placed on the queue.
 *
 * @param xQueue A handle to the queue to be deleted.
 *
 * \defgroup vQueueDelete vQueueDelete
 * \ingroup QueueManagement
 */
void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSendToFrontFromISR(
 *                                       QueueHandle_t xQueue,
 *                                       const void *pvItemToQueue,
 *                                       BaseType_t *pxHigherPriorityTaskWoken
 *                                    );
 * @endcode
 *
 * This is a macro that calls xQueueGenericSendFromISR().
 *
 * Post an item to the front of a queue.  It is safe to use this macro from
 * within an interrupt service routine.
 *
 * Items are queued by copy not reference so it is preferable to only
 * queue small items, especially when called from an ISR.  In most cases
 * it would be preferable to store a pointer to the item being queued.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xQueueSendToFrontFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return pdTRUE if the data was successfully sent to the queue, otherwise
 * errQUEUE_FULL.
 *
 * Example usage for buffered IO (where the ISR can obtain more than one value
 * per call):
 * @code{c}
 * void vBufferISR( void )
 * {
 * char cIn;
 * BaseType_t xHigherPriorityTaskWoken;
 *
 *  // We have not woken a task at the start of the ISR.
 *  xHigherPriorityTaskWoken = pdFALSE;
 *
 *  // Loop until the buffer is empty.
 *  do
 *  {
 *      // Obtain a byte from the buffer.
 *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
 *
 *      // Post the byte.
 *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
 *
 *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
 *
 *  // Now the buffer is empty we can switch context if necessary.
 *  if( xHigherPriorityTaskWoken )
 *  {
 *      taskYIELD ();
 *  }
 * }
 * @endcode
 *
 * \defgroup xQueueSendFromISR xQueueSendFromISR
 * \ingroup QueueManagement
 */
#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )


/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSendToBackFromISR(
 *                                       QueueHandle_t xQueue,
 *                                       const void *pvItemToQueue,
 *                                       BaseType_t *pxHigherPriorityTaskWoken
 *                                    );
 * @endcode
 *
 * This is a macro that calls xQueueGenericSendFromISR().
 *
 * Post an item to the back of a queue.  It is safe to use this macro from
 * within an interrupt service routine.
 *
 * Items are queued by copy not reference so it is preferable to only
 * queue small items, especially when called from an ISR.  In most cases
 * it would be preferable to store a pointer to the item being queued.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return pdTRUE if the data was successfully sent to the queue, otherwise
 * errQUEUE_FULL.
 *
 * Example usage for buffered IO (where the ISR can obtain more than one value
 * per call):
 * @code{c}
 * void vBufferISR( void )
 * {
 * char cIn;
 * BaseType_t xHigherPriorityTaskWoken;
 *
 *  // We have not woken a task at the start of the ISR.
 *  xHigherPriorityTaskWoken = pdFALSE;
 *
 *  // Loop until the buffer is empty.
 *  do
 *  {
 *      // Obtain a byte from the buffer.
 *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
 *
 *      // Post the byte.
 *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
 *
 *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
 *
 *  // Now the buffer is empty we can switch context if necessary.
 *  if( xHigherPriorityTaskWoken )
 *  {
 *      taskYIELD ();
 *  }
 * }
 * @endcode
 *
 * \defgroup xQueueSendFromISR xQueueSendFromISR
 * \ingroup QueueManagement
 */
#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueOverwriteFromISR(
 *                            QueueHandle_t xQueue,
 *                            const void * pvItemToQueue,
 *                            BaseType_t *pxHigherPriorityTaskWoken
 *                       );
 * @endcode
 *
 * A version of xQueueOverwrite() that can be used in an interrupt service
 * routine (ISR).
 *
 * Only for use with queues that can hold a single item - so the queue is either
 * empty or full.
 *
 * Post an item on a queue.  If the queue is already full then overwrite the
 * value held in the queue.  The item is queued by copy, not by reference.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return xQueueOverwriteFromISR() is a macro that calls
 * xQueueGenericSendFromISR(), and therefore has the same return values as
 * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
 * returned because xQueueOverwriteFromISR() will write to the queue even when
 * the queue is already full.
 *
 * Example usage:
 * @code{c}
 *
 * QueueHandle_t xQueue;
 *
 * void vFunction( void *pvParameters )
 * {
 *  // Create a queue to hold one uint32_t value.  It is strongly
 *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
 *  // contain more than one value, and doing so will trigger an assertion
 *  // if configASSERT() is defined.
 *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
 * }
 *
 * void vAnInterruptHandler( void )
 * {
 * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 * uint32_t ulVarToSend, ulValReceived;
 *
 *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
 *  ulVarToSend = 10;
 *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
 *
 *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
 *  // pass because the value held in the queue will be overwritten with the
 *  // new value.
 *  ulVarToSend = 100;
 *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
 *
 *  // Reading from the queue will now return 100.
 *
 *  // ...
 *
 *  if( xHigherPrioritytaskWoken == pdTRUE )
 *  {
 *      // Writing to the queue caused a task to unblock and the unblocked task
 *      // has a priority higher than or equal to the priority of the currently
 *      // executing task (the task this interrupt interrupted). Perform a context
 *      // switch so this interrupt returns directly to the unblocked task.
 *      // The macro used is port specific and will be either
 *      // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation
 *      // page for the port being used.
 *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 *  }
 * }
 * @endcode
 * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
 * \ingroup QueueManagement
 */
#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueSendFromISR(
 *                                   QueueHandle_t xQueue,
 *                                   const void *pvItemToQueue,
 *                                   BaseType_t *pxHigherPriorityTaskWoken
 *                              );
 * @endcode
 *
 * This is a macro that calls xQueueGenericSendFromISR().  It is included
 * for backward compatibility with versions of FreeRTOS.org that did not
 * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
 * macros.
 *
 * Post an item to the back of a queue.  It is safe to use this function from
 * within an interrupt service routine.
 *
 * Items are queued by copy not reference so it is preferable to only
 * queue small items, especially when called from an ISR.  In most cases
 * it would be preferable to store a pointer to the item being queued.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return pdTRUE if the data was successfully sent to the queue, otherwise
 * errQUEUE_FULL.
 *
 * Example usage for buffered IO (where the ISR can obtain more than one value
 * per call):
 * @code{c}
 * void vBufferISR( void )
 * {
 * char cIn;
 * BaseType_t xHigherPriorityTaskWoken;
 *
 *  // We have not woken a task at the start of the ISR.
 *  xHigherPriorityTaskWoken = pdFALSE;
 *
 *  // Loop until the buffer is empty.
 *  do
 *  {
 *      // Obtain a byte from the buffer.
 *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
 *
 *      // Post the byte.
 *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
 *
 *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
 *
 *  // Now the buffer is empty we can switch context if necessary.
 *  if( xHigherPriorityTaskWoken )
 *  {
 *       // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
 *       // switch should be requested. The macro used is port specific and
 *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
 *       // refer to the documentation page for the port being used.
 *       portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 *  }
 * }
 * @endcode
 *
 * \defgroup xQueueSendFromISR xQueueSendFromISR
 * \ingroup QueueManagement
 */
#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueGenericSendFromISR(
 *                                         QueueHandle_t    xQueue,
 *                                         const    void    *pvItemToQueue,
 *                                         BaseType_t  *pxHigherPriorityTaskWoken,
 *                                         BaseType_t  xCopyPosition
 *                                     );
 * @endcode
 *
 * It is preferred that the macros xQueueSendFromISR(),
 * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
 * of calling this function directly.  xQueueGiveFromISR() is an
 * equivalent for use by semaphores that don't actually copy any data.
 *
 * Post an item on a queue.  It is safe to use this function from within an
 * interrupt service routine.
 *
 * Items are queued by copy not reference so it is preferable to only
 * queue small items, especially when called from an ISR.  In most cases
 * it would be preferable to store a pointer to the item being queued.
 *
 * @param xQueue The handle to the queue on which the item is to be posted.
 *
 * @param pvItemToQueue A pointer to the item that is to be placed on the
 * queue.  The size of the items the queue will hold was defined when the
 * queue was created, so this many bytes will be copied from pvItemToQueue
 * into the queue storage area.
 *
 * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
 * item at the back of the queue, or queueSEND_TO_FRONT to place the item
 * at the front of the queue (for high priority messages).
 *
 * @return pdTRUE if the data was successfully sent to the queue, otherwise
 * errQUEUE_FULL.
 *
 * Example usage for buffered IO (where the ISR can obtain more than one value
 * per call):
 * @code{c}
 * void vBufferISR( void )
 * {
 * char cIn;
 * BaseType_t xHigherPriorityTaskWokenByPost;
 *
 *  // We have not woken a task at the start of the ISR.
 *  xHigherPriorityTaskWokenByPost = pdFALSE;
 *
 *  // Loop until the buffer is empty.
 *  do
 *  {
 *      // Obtain a byte from the buffer.
 *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
 *
 *      // Post each byte.
 *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
 *
 *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
 *
 *  // Now the buffer is empty we can switch context if necessary.
 *  if( xHigherPriorityTaskWokenByPost )
 *  {
 *       // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context
 *       // switch should be requested. The macro used is port specific and
 *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
 *       // refer to the documentation page for the port being used.
 *       portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost );
 *  }
 * }
 * @endcode
 *
 * \defgroup xQueueSendFromISR xQueueSendFromISR
 * \ingroup QueueManagement
 */
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
                                     const void * const pvItemToQueue,
                                     BaseType_t * const pxHigherPriorityTaskWoken,
                                     const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
                              BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/**
 * queue. h
 * @code{c}
 * BaseType_t xQueueReceiveFromISR(
 *                                     QueueHandle_t    xQueue,
 *                                     void             *pvBuffer,
 *                                     BaseType_t       *pxTaskWoken
 *                                 );
 * @endcode
 *
 * Receive an item from a queue.  It is safe to use this function from within an
 * interrupt service routine.
 *
 * @param xQueue The handle to the queue from which the item is to be
 * received.
 *
 * @param pvBuffer Pointer to the buffer into which the received item will
 * be copied.
 *
 * @param pxHigherPriorityTaskWoken A task may be blocked waiting for space to
 * become available on the queue.  If xQueueReceiveFromISR causes such a task
 * to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
 * remain unchanged.
 *
 * @return pdTRUE if an item was successfully received from the queue,
 * otherwise pdFALSE.
 *
 * Example usage:
 * @code{c}
 *
 * QueueHandle_t xQueue;
 *
 * // Function to create a queue and post some values.
 * void vAFunction( void *pvParameters )
 * {
 * char cValueToPost;
 * const TickType_t xTicksToWait = ( TickType_t )0xff;
 *
 *  // Create a queue capable of containing 10 characters.
 *  xQueue = xQueueCreate( 10, sizeof( char ) );
 *  if( xQueue == 0 )
 *  {
 *      // Failed to create the queue.
 *  }
 *
 *  // ...
 *
 *  // Post some characters that will be used within an ISR.  If the queue
 *  // is full then this task will block for xTicksToWait ticks.
 *  cValueToPost = 'a';
 *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
 *  cValueToPost = 'b';
 *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
 *
 *  // ... keep posting characters ... this task may block when the queue
 *  // becomes full.
 *
 *  cValueToPost = 'c';
 *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
 * }
 *
 * // ISR that outputs all the characters received on the queue.
 * void vISR_Routine( void )
 * {
 * BaseType_t xTaskWokenByReceive = pdFALSE;
 * char cRxedChar;
 *
 *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
 *  {
 *      // A character was received.  Output the character now.
 *      vOutputCharacter( cRxedChar );
 *
 *      // If removing the character from the queue woke the task that was
 *      // posting onto the queue xTaskWokenByReceive will have been set to
 *      // pdTRUE.  No matter how many times this loop iterates only one
 *      // task will be woken.
 *  }
 *
 *  if( xTaskWokenByReceive != ( char ) pdFALSE;
 *  {
 *      taskYIELD ();
 *  }
 * }
 * @endcode
 * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
 * \ingroup QueueManagement
 */
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
                                 void * const pvBuffer,
                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/*
 * Utilities to query queues that are safe to use from an ISR.  These utilities
 * should be used only from within an ISR, or within a critical section.
 */
BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

#if ( configUSE_CO_ROUTINES == 1 )

/*
 * The functions defined above are for passing data to and from tasks.  The
 * functions below are the equivalents for passing data to and from
 * co-routines.
 *
 * These functions are called from the co-routine macro implementation and
 * should not be called directly from application code.  Instead use the macro
 * wrappers defined within croutine.h.
 */
    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
                                    const void * pvItemToQueue,
                                    BaseType_t xCoRoutinePreviouslyWoken );
    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
                                       void * pvBuffer,
                                       BaseType_t * pxTaskWoken );
    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
                             const void * pvItemToQueue,
                             TickType_t xTicksToWait );
    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
                                void * pvBuffer,
                                TickType_t xTicksToWait );

#endif /* if ( configUSE_CO_ROUTINES == 1 ) */

/*
 * For internal use only.  Use xSemaphoreCreateMutex(),
 * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
 * these functions directly.
 */
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
#endif

#if ( configUSE_COUNTING_SEMAPHORES == 1 )
    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
#endif

#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
                                                       const UBaseType_t uxInitialCount,
                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
#endif

BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                                TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
#endif

/*
 * For internal use only.  Use xSemaphoreTakeRecursive() or
 * xSemaphoreGiveRecursive() instead of calling these functions directly.
 */
BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                     TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;

/*
 * Reset a queue back to its original empty state.  The return value is now
 * obsolete and is always set to pdPASS.
 */
#define xQueueReset( xQueue )    xQueueGenericReset( ( xQueue ), pdFALSE )

/*
 * The registry is provided as a means for kernel aware debuggers to
 * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
 * a queue, semaphore or mutex handle to the registry if you want the handle
 * to be available to a kernel aware debugger.  If you are not using a kernel
 * aware debugger then this function can be ignored.
 *
 * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
 * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
 * within FreeRTOSConfig.h for the registry to be available.  Its value
 * does not affect the number of queues, semaphores and mutexes that can be
 * created - just the number that the registry can hold.
 *
 * If vQueueAddToRegistry is called more than once with the same xQueue
 * parameter, the registry will store the pcQueueName parameter from the
 * most recent call to vQueueAddToRegistry.
 *
 * @param xQueue The handle of the queue being added to the registry.  This
 * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
 * handles can also be passed in here.
 *
 * @param pcQueueName The name to be associated with the handle.  This is the
 * name that the kernel aware debugger will display.  The queue registry only
 * stores a pointer to the string - so the string must be persistent (global or
 * preferably in ROM/Flash), not on the stack.
 */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
    void vQueueAddToRegistry( QueueHandle_t xQueue,
                              const char * pcQueueName ) PRIVILEGED_FUNCTION;
#endif

/*
 * The registry is provided as a means for kernel aware debuggers to
 * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
 * a queue, semaphore or mutex handle to the registry if you want the handle
 * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
 * remove the queue, semaphore or mutex from the register.  If you are not using
 * a kernel aware debugger then this function can be ignored.
 *
 * @param xQueue The handle of the queue being removed from the registry.
 */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
    void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
#endif

/*
 * The queue registry is provided as a means for kernel aware debuggers to
 * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
 * up and return the name of a queue in the queue registry from the queue's
 * handle.
 *
 * @param xQueue The handle of the queue the name of which will be returned.
 * @return If the queue is in the registry then a pointer to the name of the
 * queue is returned.  If the queue is not in the registry then NULL is
 * returned.
 */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
#endif

/*
 * Generic version of the function used to create a queue using dynamic memory
 * allocation.  This is called by other functions and macros that create other
 * RTOS objects that use the queue structure as their base.
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
                                       const UBaseType_t uxItemSize,
                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
#endif

/*
 * Generic version of the function used to create a queue using dynamic memory
 * allocation.  This is called by other functions and macros that create other
 * RTOS objects that use the queue structure as their base.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
                                             const UBaseType_t uxItemSize,
                                             uint8_t * pucQueueStorage,
                                             StaticQueue_t * pxStaticQueue,
                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
#endif

/*
 * Generic version of the function used to retrieve the buffers of statically
 * created queues. This is called by other functions and macros that retrieve
 * the buffers of other statically created RTOS objects that use the queue
 * structure as their base.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
                                              uint8_t ** ppucQueueStorage,
                                              StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
#endif

/*
 * Queue sets provide a mechanism to allow a task to block (pend) on a read
 * operation from multiple queues or semaphores simultaneously.
 *
 * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
 * function.
 *
 * A queue set must be explicitly created using a call to xQueueCreateSet()
 * before it can be used.  Once created, standard FreeRTOS queues and semaphores
 * can be added to the set using calls to xQueueAddToSet().
 * xQueueSelectFromSet() is then used to determine which, if any, of the queues
 * or semaphores contained in the set is in a state where a queue read or
 * semaphore take operation would be successful.
 *
 * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
 * for reasons why queue sets are very rarely needed in practice as there are
 * simpler methods of blocking on multiple objects.
 *
 * Note 2:  Blocking on a queue set that contains a mutex will not cause the
 * mutex holder to inherit the priority of the blocked task.
 *
 * Note 3:  An additional 4 bytes of RAM is required for each space in a every
 * queue added to a queue set.  Therefore counting semaphores that have a high
 * maximum count value should not be added to a queue set.
 *
 * Note 4:  A receive (in the case of a queue) or take (in the case of a
 * semaphore) operation must not be performed on a member of a queue set unless
 * a call to xQueueSelectFromSet() has first returned a handle to that set member.
 *
 * @param uxEventQueueLength Queue sets store events that occur on
 * the queues and semaphores contained in the set.  uxEventQueueLength specifies
 * the maximum number of events that can be queued at once.  To be absolutely
 * certain that events are not lost uxEventQueueLength should be set to the
 * total sum of the length of the queues added to the set, where binary
 * semaphores and mutexes have a length of 1, and counting semaphores have a
 * length set by their maximum count value.  Examples:
 *  + If a queue set is to hold a queue of length 5, another queue of length 12,
 *    and a binary semaphore, then uxEventQueueLength should be set to
 *    (5 + 12 + 1), or 18.
 *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
 *    should be set to (1 + 1 + 1 ), or 3.
 *  + If a queue set is to hold a counting semaphore that has a maximum count of
 *    5, and a counting semaphore that has a maximum count of 3, then
 *    uxEventQueueLength should be set to (5 + 3), or 8.
 *
 * @return If the queue set is created successfully then a handle to the created
 * queue set is returned.  Otherwise NULL is returned.
 */
#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
#endif

/*
 * Adds a queue or semaphore to a queue set that was previously created by a
 * call to xQueueCreateSet().
 *
 * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
 * function.
 *
 * Note 1:  A receive (in the case of a queue) or take (in the case of a
 * semaphore) operation must not be performed on a member of a queue set unless
 * a call to xQueueSelectFromSet() has first returned a handle to that set member.
 *
 * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
 * the queue set (cast to an QueueSetMemberHandle_t type).
 *
 * @param xQueueSet The handle of the queue set to which the queue or semaphore
 * is being added.
 *
 * @return If the queue or semaphore was successfully added to the queue set
 * then pdPASS is returned.  If the queue could not be successfully added to the
 * queue set because it is already a member of a different queue set then pdFAIL
 * is returned.
 */
#if ( configUSE_QUEUE_SETS == 1 )
    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                               QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
#endif

/*
 * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
 * be removed from a set if the queue or semaphore is empty.
 *
 * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
 * function.
 *
 * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
 * from the queue set (cast to an QueueSetMemberHandle_t type).
 *
 * @param xQueueSet The handle of the queue set in which the queue or semaphore
 * is included.
 *
 * @return If the queue or semaphore was successfully removed from the queue set
 * then pdPASS is returned.  If the queue was not in the queue set, or the
 * queue (or semaphore) was not empty, then pdFAIL is returned.
 */
#if ( configUSE_QUEUE_SETS == 1 )
    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
#endif

/*
 * xQueueSelectFromSet() selects from the members of a queue set a queue or
 * semaphore that either contains data (in the case of a queue) or is available
 * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
 * allows a task to block (pend) on a read operation on all the queues and
 * semaphores in a queue set simultaneously.
 *
 * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
 * function.
 *
 * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
 * for reasons why queue sets are very rarely needed in practice as there are
 * simpler methods of blocking on multiple objects.
 *
 * Note 2:  Blocking on a queue set that contains a mutex will not cause the
 * mutex holder to inherit the priority of the blocked task.
 *
 * Note 3:  A receive (in the case of a queue) or take (in the case of a
 * semaphore) operation must not be performed on a member of a queue set unless
 * a call to xQueueSelectFromSet() has first returned a handle to that set member.
 *
 * @param xQueueSet The queue set on which the task will (potentially) block.
 *
 * @param xTicksToWait The maximum time, in ticks, that the calling task will
 * remain in the Blocked state (with other tasks executing) to wait for a member
 * of the queue set to be ready for a successful queue read or semaphore take
 * operation.
 *
 * @return xQueueSelectFromSet() will return the handle of a queue (cast to
 * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
 * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
 * in the queue set that is available, or NULL if no such queue or semaphore
 * exists before before the specified block time expires.
 */
#if ( configUSE_QUEUE_SETS == 1 )
    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
                                                const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
#endif

/*
 * A version of xQueueSelectFromSet() that can be used from an ISR.
 */
#if ( configUSE_QUEUE_SETS == 1 )
    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
#endif

/* Not public API functions. */
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
                                     TickType_t xTicksToWait,
                                     const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                               BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;

#if ( configUSE_TRACE_FACILITY == 1 )
    void vQueueSetQueueNumber( QueueHandle_t xQueue,
                               UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
#endif

#if ( configUSE_TRACE_FACILITY == 1 )
    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
#endif

#if ( configUSE_TRACE_FACILITY == 1 )
    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
#endif

UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */

#endif /* QUEUE_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef SEMAPHORE_H
#define SEMAPHORE_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
#endif

#include "queue.h"

typedef QueueHandle_t SemaphoreHandle_t;

#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )
#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )
#define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )


/**
 * semphr. h
 * @code{c}
 * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
 * @endcode
 *
 * In many usage scenarios it is faster and more memory efficient to use a
 * direct to task notification in place of a binary semaphore!
 * https://www.FreeRTOS.org/RTOS-task-notifications.html
 *
 * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
 * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
 * the vSemaphoreCreateBinary() macro are created in a state such that the
 * first call to 'take' the semaphore would pass, whereas binary semaphores
 * created using xSemaphoreCreateBinary() are created in a state such that the
 * the semaphore must first be 'given' before it can be 'taken'.
 *
 * Macro that implements a semaphore by using the existing queue mechanism.
 * The queue length is 1 as this is a binary semaphore.  The data size is 0
 * as we don't want to actually store any data - we just want to know if the
 * queue is empty or full.
 *
 * This type of semaphore can be used for pure synchronisation between tasks or
 * between an interrupt and a task.  The semaphore need not be given back once
 * obtained, so one task/interrupt can continuously 'give' the semaphore while
 * another continuously 'takes' the semaphore.  For this reason this type of
 * semaphore does not use a priority inheritance mechanism.  For an alternative
 * that does use priority inheritance see xSemaphoreCreateMutex().
 *
 * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
 *  // This is a macro so pass the variable in directly.
 *  vSemaphoreCreateBinary( xSemaphore );
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // The semaphore was created successfully.
 *      // The semaphore can now be used.
 *  }
 * }
 * @endcode
 * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
 * \ingroup Semaphores
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    #define vSemaphoreCreateBinary( xSemaphore )                                                                                     \
    do {                                                                                                                             \
        ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
        if( ( xSemaphore ) != NULL )                                                                                                 \
        {                                                                                                                            \
            ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                               \
        }                                                                                                                            \
    } while( 0 )
#endif

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateBinary( void );
 * @endcode
 *
 * Creates a new binary semaphore instance, and returns a handle by which the
 * new semaphore can be referenced.
 *
 * In many usage scenarios it is faster and more memory efficient to use a
 * direct to task notification in place of a binary semaphore!
 * https://www.FreeRTOS.org/RTOS-task-notifications.html
 *
 * Internally, within the FreeRTOS implementation, binary semaphores use a block
 * of memory, in which the semaphore structure is stored.  If a binary semaphore
 * is created using xSemaphoreCreateBinary() then the required memory is
 * automatically dynamically allocated inside the xSemaphoreCreateBinary()
 * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
 * is created using xSemaphoreCreateBinaryStatic() then the application writer
 * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
 * binary semaphore to be created without using any dynamic memory allocation.
 *
 * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
 * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
 * the vSemaphoreCreateBinary() macro are created in a state such that the
 * first call to 'take' the semaphore would pass, whereas binary semaphores
 * created using xSemaphoreCreateBinary() are created in a state such that the
 * the semaphore must first be 'given' before it can be 'taken'.
 *
 * This type of semaphore can be used for pure synchronisation between tasks or
 * between an interrupt and a task.  The semaphore need not be given back once
 * obtained, so one task/interrupt can continuously 'give' the semaphore while
 * another continuously 'takes' the semaphore.  For this reason this type of
 * semaphore does not use a priority inheritance mechanism.  For an alternative
 * that does use priority inheritance see xSemaphoreCreateMutex().
 *
 * @return Handle to the created semaphore, or NULL if the memory required to
 * hold the semaphore's data structures could not be allocated.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
 *  // This is a macro so pass the variable in directly.
 *  xSemaphore = xSemaphoreCreateBinary();
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // The semaphore was created successfully.
 *      // The semaphore can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
 * \ingroup Semaphores
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    #define xSemaphoreCreateBinary()    xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
#endif

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
 * @endcode
 *
 * Creates a new binary semaphore instance, and returns a handle by which the
 * new semaphore can be referenced.
 *
 * NOTE: In many usage scenarios it is faster and more memory efficient to use a
 * direct to task notification in place of a binary semaphore!
 * https://www.FreeRTOS.org/RTOS-task-notifications.html
 *
 * Internally, within the FreeRTOS implementation, binary semaphores use a block
 * of memory, in which the semaphore structure is stored.  If a binary semaphore
 * is created using xSemaphoreCreateBinary() then the required memory is
 * automatically dynamically allocated inside the xSemaphoreCreateBinary()
 * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
 * is created using xSemaphoreCreateBinaryStatic() then the application writer
 * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
 * binary semaphore to be created without using any dynamic memory allocation.
 *
 * This type of semaphore can be used for pure synchronisation between tasks or
 * between an interrupt and a task.  The semaphore need not be given back once
 * obtained, so one task/interrupt can continuously 'give' the semaphore while
 * another continuously 'takes' the semaphore.  For this reason this type of
 * semaphore does not use a priority inheritance mechanism.  For an alternative
 * that does use priority inheritance see xSemaphoreCreateMutex().
 *
 * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
 * which will then be used to hold the semaphore's data structure, removing the
 * need for the memory to be allocated dynamically.
 *
 * @return If the semaphore is created then a handle to the created semaphore is
 * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore = NULL;
 * StaticSemaphore_t xSemaphoreBuffer;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
 *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
 *  // variable, the address of which is passed into the function.  The
 *  // function's parameter is not NULL, so the function will not attempt any
 *  // dynamic memory allocation, and therefore the function will not return
 *  // return NULL.
 *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
 *
 *  // Rest of task code goes here.
 * }
 * @endcode
 * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
 * \ingroup Semaphores
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore )    xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * semphr. h
 * @code{c}
 * xSemaphoreTake(
 *                   SemaphoreHandle_t xSemaphore,
 *                   TickType_t xBlockTime
 *               );
 * @endcode
 *
 * Macro to obtain a semaphore.  The semaphore must have previously been
 * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
 * xSemaphoreCreateCounting().
 *
 * @param xSemaphore A handle to the semaphore being taken - obtained when
 * the semaphore was created.
 *
 * @param xBlockTime The time in ticks to wait for the semaphore to become
 * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
 * real time.  A block time of zero can be used to poll the semaphore.  A block
 * time of portMAX_DELAY can be used to block indefinitely (provided
 * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
 *
 * @return pdTRUE if the semaphore was obtained.  pdFALSE
 * if xBlockTime expired without the semaphore becoming available.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 * // A task that creates a semaphore.
 * void vATask( void * pvParameters )
 * {
 *  // Create the semaphore to guard a shared resource.
 *  xSemaphore = xSemaphoreCreateBinary();
 * }
 *
 * // A task that uses the semaphore.
 * void vAnotherTask( void * pvParameters )
 * {
 *  // ... Do other things.
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // See if we can obtain the semaphore.  If the semaphore is not available
 *      // wait 10 ticks to see if it becomes free.
 *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
 *      {
 *          // We were able to obtain the semaphore and can now access the
 *          // shared resource.
 *
 *          // ...
 *
 *          // We have finished accessing the shared resource.  Release the
 *          // semaphore.
 *          xSemaphoreGive( xSemaphore );
 *      }
 *      else
 *      {
 *          // We could not obtain the semaphore and can therefore not access
 *          // the shared resource safely.
 *      }
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreTake xSemaphoreTake
 * \ingroup Semaphores
 */
#define xSemaphoreTake( xSemaphore, xBlockTime )    xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )

/**
 * semphr. h
 * @code{c}
 * xSemaphoreTakeRecursive(
 *                          SemaphoreHandle_t xMutex,
 *                          TickType_t xBlockTime
 *                        );
 * @endcode
 *
 * Macro to recursively obtain, or 'take', a mutex type semaphore.
 * The mutex must have previously been created using a call to
 * xSemaphoreCreateRecursiveMutex();
 *
 * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
 * macro to be available.
 *
 * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
 *
 * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
 * doesn't become available again until the owner has called
 * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
 * if a task successfully 'takes' the same mutex 5 times then the mutex will
 * not be available to any other task until it has also  'given' the mutex back
 * exactly five times.
 *
 * @param xMutex A handle to the mutex being obtained.  This is the
 * handle returned by xSemaphoreCreateRecursiveMutex();
 *
 * @param xBlockTime The time in ticks to wait for the semaphore to become
 * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
 * real time.  A block time of zero can be used to poll the semaphore.  If
 * the task already owns the semaphore then xSemaphoreTakeRecursive() will
 * return immediately no matter what the value of xBlockTime.
 *
 * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
 * expired without the semaphore becoming available.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xMutex = NULL;
 *
 * // A task that creates a mutex.
 * void vATask( void * pvParameters )
 * {
 *  // Create the mutex to guard a shared resource.
 *  xMutex = xSemaphoreCreateRecursiveMutex();
 * }
 *
 * // A task that uses the mutex.
 * void vAnotherTask( void * pvParameters )
 * {
 *  // ... Do other things.
 *
 *  if( xMutex != NULL )
 *  {
 *      // See if we can obtain the mutex.  If the mutex is not available
 *      // wait 10 ticks to see if it becomes free.
 *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
 *      {
 *          // We were able to obtain the mutex and can now access the
 *          // shared resource.
 *
 *          // ...
 *          // For some reason due to the nature of the code further calls to
 *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
 *          // code these would not be just sequential calls as this would make
 *          // no sense.  Instead the calls are likely to be buried inside
 *          // a more complex call structure.
 *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
 *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
 *
 *          // The mutex has now been 'taken' three times, so will not be
 *          // available to another task until it has also been given back
 *          // three times.  Again it is unlikely that real code would have
 *          // these calls sequentially, but instead buried in a more complex
 *          // call structure.  This is just for illustrative purposes.
 *          xSemaphoreGiveRecursive( xMutex );
 *          xSemaphoreGiveRecursive( xMutex );
 *          xSemaphoreGiveRecursive( xMutex );
 *
 *          // Now the mutex can be taken by other tasks.
 *      }
 *      else
 *      {
 *          // We could not obtain the mutex and can therefore not access
 *          // the shared resource safely.
 *      }
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
 * \ingroup Semaphores
 */
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
    #define xSemaphoreTakeRecursive( xMutex, xBlockTime )    xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
#endif

/**
 * semphr. h
 * @code{c}
 * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
 * @endcode
 *
 * Macro to release a semaphore.  The semaphore must have previously been
 * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
 * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
 *
 * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
 * an alternative which can be used from an ISR.
 *
 * This macro must also not be used on semaphores created using
 * xSemaphoreCreateRecursiveMutex().
 *
 * @param xSemaphore A handle to the semaphore being released.  This is the
 * handle returned when the semaphore was created.
 *
 * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
 * Semaphores are implemented using queues.  An error can occur if there is
 * no space on the queue to post a message - indicating that the
 * semaphore was not first obtained correctly.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Create the semaphore to guard a shared resource.
 *  xSemaphore = vSemaphoreCreateBinary();
 *
 *  if( xSemaphore != NULL )
 *  {
 *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
 *      {
 *          // We would expect this call to fail because we cannot give
 *          // a semaphore without first "taking" it!
 *      }
 *
 *      // Obtain the semaphore - don't block if the semaphore is not
 *      // immediately available.
 *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
 *      {
 *          // We now have the semaphore and can access the shared resource.
 *
 *          // ...
 *
 *          // We have finished accessing the shared resource so can free the
 *          // semaphore.
 *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
 *          {
 *              // We would not expect this call to fail because we must have
 *              // obtained the semaphore to get here.
 *          }
 *      }
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreGive xSemaphoreGive
 * \ingroup Semaphores
 */
#define xSemaphoreGive( xSemaphore )    xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )

/**
 * semphr. h
 * @code{c}
 * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
 * @endcode
 *
 * Macro to recursively release, or 'give', a mutex type semaphore.
 * The mutex must have previously been created using a call to
 * xSemaphoreCreateRecursiveMutex();
 *
 * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
 * macro to be available.
 *
 * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
 *
 * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
 * doesn't become available again until the owner has called
 * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
 * if a task successfully 'takes' the same mutex 5 times then the mutex will
 * not be available to any other task until it has also  'given' the mutex back
 * exactly five times.
 *
 * @param xMutex A handle to the mutex being released, or 'given'.  This is the
 * handle returned by xSemaphoreCreateMutex();
 *
 * @return pdTRUE if the semaphore was given.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xMutex = NULL;
 *
 * // A task that creates a mutex.
 * void vATask( void * pvParameters )
 * {
 *  // Create the mutex to guard a shared resource.
 *  xMutex = xSemaphoreCreateRecursiveMutex();
 * }
 *
 * // A task that uses the mutex.
 * void vAnotherTask( void * pvParameters )
 * {
 *  // ... Do other things.
 *
 *  if( xMutex != NULL )
 *  {
 *      // See if we can obtain the mutex.  If the mutex is not available
 *      // wait 10 ticks to see if it becomes free.
 *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
 *      {
 *          // We were able to obtain the mutex and can now access the
 *          // shared resource.
 *
 *          // ...
 *          // For some reason due to the nature of the code further calls to
 *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
 *          // code these would not be just sequential calls as this would make
 *          // no sense.  Instead the calls are likely to be buried inside
 *          // a more complex call structure.
 *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
 *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
 *
 *          // The mutex has now been 'taken' three times, so will not be
 *          // available to another task until it has also been given back
 *          // three times.  Again it is unlikely that real code would have
 *          // these calls sequentially, it would be more likely that the calls
 *          // to xSemaphoreGiveRecursive() would be called as a call stack
 *          // unwound.  This is just for demonstrative purposes.
 *          xSemaphoreGiveRecursive( xMutex );
 *          xSemaphoreGiveRecursive( xMutex );
 *          xSemaphoreGiveRecursive( xMutex );
 *
 *          // Now the mutex can be taken by other tasks.
 *      }
 *      else
 *      {
 *          // We could not obtain the mutex and can therefore not access
 *          // the shared resource safely.
 *      }
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
 * \ingroup Semaphores
 */
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
    #define xSemaphoreGiveRecursive( xMutex )    xQueueGiveMutexRecursive( ( xMutex ) )
#endif

/**
 * semphr. h
 * @code{c}
 * xSemaphoreGiveFromISR(
 *                        SemaphoreHandle_t xSemaphore,
 *                        BaseType_t *pxHigherPriorityTaskWoken
 *                    );
 * @endcode
 *
 * Macro to  release a semaphore.  The semaphore must have previously been
 * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
 *
 * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
 * must not be used with this macro.
 *
 * This macro can be used from an ISR.
 *
 * @param xSemaphore A handle to the semaphore being released.  This is the
 * handle returned when the semaphore was created.
 *
 * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
 *
 * Example usage:
 * @code{c}
 \#define LONG_TIME 0xffff
 \#define TICKS_TO_WAIT 10
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 * // Repetitive task.
 * void vATask( void * pvParameters )
 * {
 *  for( ;; )
 *  {
 *      // We want this task to run every 10 ticks of a timer.  The semaphore
 *      // was created before this task was started.
 *
 *      // Block waiting for the semaphore to become available.
 *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
 *      {
 *          // It is time to execute.
 *
 *          // ...
 *
 *          // We have finished our task.  Return to the top of the loop where
 *          // we will block on the semaphore until it is time to execute
 *          // again.  Note when using the semaphore for synchronisation with an
 *          // ISR in this manner there is no need to 'give' the semaphore back.
 *      }
 *  }
 * }
 *
 * // Timer ISR
 * void vTimerISR( void * pvParameters )
 * {
 * static uint8_t ucLocalTickCount = 0;
 * static BaseType_t xHigherPriorityTaskWoken;
 *
 *  // A timer tick has occurred.
 *
 *  // ... Do other time functions.
 *
 *  // Is it time for vATask () to run?
 *  xHigherPriorityTaskWoken = pdFALSE;
 *  ucLocalTickCount++;
 *  if( ucLocalTickCount >= TICKS_TO_WAIT )
 *  {
 *      // Unblock the task by releasing the semaphore.
 *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
 *
 *      // Reset the count so we release the semaphore again in 10 ticks time.
 *      ucLocalTickCount = 0;
 *  }
 *
 *  if( xHigherPriorityTaskWoken != pdFALSE )
 *  {
 *      // We can force a context switch here.  Context switching from an
 *      // ISR uses port specific syntax.  Check the demo task for your port
 *      // to find the syntax required.
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
 * \ingroup Semaphores
 */
#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )

/**
 * semphr. h
 * @code{c}
 * xSemaphoreTakeFromISR(
 *                        SemaphoreHandle_t xSemaphore,
 *                        BaseType_t *pxHigherPriorityTaskWoken
 *                    );
 * @endcode
 *
 * Macro to  take a semaphore from an ISR.  The semaphore must have
 * previously been created with a call to xSemaphoreCreateBinary() or
 * xSemaphoreCreateCounting().
 *
 * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
 * must not be used with this macro.
 *
 * This macro can be used from an ISR, however taking a semaphore from an ISR
 * is not a common operation.  It is likely to only be useful when taking a
 * counting semaphore when an interrupt is obtaining an object from a resource
 * pool (when the semaphore count indicates the number of resources available).
 *
 * @param xSemaphore A handle to the semaphore being taken.  This is the
 * handle returned when the semaphore was created.
 *
 * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
 * to unblock, and the unblocked task has a priority higher than the currently
 * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
 * a context switch should be requested before the interrupt is exited.
 *
 * @return pdTRUE if the semaphore was successfully taken, otherwise
 * pdFALSE
 */
#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateMutex( void );
 * @endcode
 *
 * Creates a new mutex type semaphore instance, and returns a handle by which
 * the new mutex can be referenced.
 *
 * Internally, within the FreeRTOS implementation, mutex semaphores use a block
 * of memory, in which the mutex structure is stored.  If a mutex is created
 * using xSemaphoreCreateMutex() then the required memory is automatically
 * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
 * xSemaphoreCreateMutexStatic() then the application writer must provided the
 * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
 * without using any dynamic memory allocation.
 *
 * Mutexes created using this function can be accessed using the xSemaphoreTake()
 * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
 * xSemaphoreGiveRecursive() macros must not be used.
 *
 * This type of semaphore uses a priority inheritance mechanism so a task
 * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
 * semaphore it is no longer required.
 *
 * Mutex type semaphores cannot be used from within interrupt service routines.
 *
 * See xSemaphoreCreateBinary() for an alternative implementation that can be
 * used for pure synchronisation (where one task or interrupt always 'gives' the
 * semaphore and another always 'takes' the semaphore) and from within interrupt
 * service routines.
 *
 * @return If the mutex was successfully created then a handle to the created
 * semaphore is returned.  If there was not enough heap to allocate the mutex
 * data structures then NULL is returned.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
 *  // This is a macro so pass the variable in directly.
 *  xSemaphore = xSemaphoreCreateMutex();
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // The semaphore was created successfully.
 *      // The semaphore can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
 * \ingroup Semaphores
 */
#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
    #define xSemaphoreCreateMutex()    xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
#endif

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
 * @endcode
 *
 * Creates a new mutex type semaphore instance, and returns a handle by which
 * the new mutex can be referenced.
 *
 * Internally, within the FreeRTOS implementation, mutex semaphores use a block
 * of memory, in which the mutex structure is stored.  If a mutex is created
 * using xSemaphoreCreateMutex() then the required memory is automatically
 * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
 * xSemaphoreCreateMutexStatic() then the application writer must provided the
 * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
 * without using any dynamic memory allocation.
 *
 * Mutexes created using this function can be accessed using the xSemaphoreTake()
 * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
 * xSemaphoreGiveRecursive() macros must not be used.
 *
 * This type of semaphore uses a priority inheritance mechanism so a task
 * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
 * semaphore it is no longer required.
 *
 * Mutex type semaphores cannot be used from within interrupt service routines.
 *
 * See xSemaphoreCreateBinary() for an alternative implementation that can be
 * used for pure synchronisation (where one task or interrupt always 'gives' the
 * semaphore and another always 'takes' the semaphore) and from within interrupt
 * service routines.
 *
 * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
 * which will be used to hold the mutex's data structure, removing the need for
 * the memory to be allocated dynamically.
 *
 * @return If the mutex was successfully created then a handle to the created
 * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 * StaticSemaphore_t xMutexBuffer;
 *
 * void vATask( void * pvParameters )
 * {
 *  // A mutex cannot be used before it has been created.  xMutexBuffer is
 *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
 *  // attempted.
 *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
 *
 *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
 *  // so there is no need to check it.
 * }
 * @endcode
 * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
 * \ingroup Semaphores
 */
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) )
    #define xSemaphoreCreateMutexStatic( pxMutexBuffer )    xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
#endif


/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
 * @endcode
 *
 * Creates a new recursive mutex type semaphore instance, and returns a handle
 * by which the new recursive mutex can be referenced.
 *
 * Internally, within the FreeRTOS implementation, recursive mutexes use a block
 * of memory, in which the mutex structure is stored.  If a recursive mutex is
 * created using xSemaphoreCreateRecursiveMutex() then the required memory is
 * automatically dynamically allocated inside the
 * xSemaphoreCreateRecursiveMutex() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
 * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
 * provide the memory that will get used by the mutex.
 * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
 * be created without using any dynamic memory allocation.
 *
 * Mutexes created using this macro can be accessed using the
 * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
 * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
 *
 * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
 * doesn't become available again until the owner has called
 * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
 * if a task successfully 'takes' the same mutex 5 times then the mutex will
 * not be available to any other task until it has also  'given' the mutex back
 * exactly five times.
 *
 * This type of semaphore uses a priority inheritance mechanism so a task
 * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
 * semaphore it is no longer required.
 *
 * Mutex type semaphores cannot be used from within interrupt service routines.
 *
 * See xSemaphoreCreateBinary() for an alternative implementation that can be
 * used for pure synchronisation (where one task or interrupt always 'gives' the
 * semaphore and another always 'takes' the semaphore) and from within interrupt
 * service routines.
 *
 * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
 * SemaphoreHandle_t.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 *
 * void vATask( void * pvParameters )
 * {
 *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
 *  // This is a macro so pass the variable in directly.
 *  xSemaphore = xSemaphoreCreateRecursiveMutex();
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // The semaphore was created successfully.
 *      // The semaphore can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
 * \ingroup Semaphores
 */
#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
    #define xSemaphoreCreateRecursiveMutex()    xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
#endif

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
 * @endcode
 *
 * Creates a new recursive mutex type semaphore instance, and returns a handle
 * by which the new recursive mutex can be referenced.
 *
 * Internally, within the FreeRTOS implementation, recursive mutexes use a block
 * of memory, in which the mutex structure is stored.  If a recursive mutex is
 * created using xSemaphoreCreateRecursiveMutex() then the required memory is
 * automatically dynamically allocated inside the
 * xSemaphoreCreateRecursiveMutex() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
 * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
 * provide the memory that will get used by the mutex.
 * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
 * be created without using any dynamic memory allocation.
 *
 * Mutexes created using this macro can be accessed using the
 * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
 * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
 *
 * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
 * doesn't become available again until the owner has called
 * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
 * if a task successfully 'takes' the same mutex 5 times then the mutex will
 * not be available to any other task until it has also  'given' the mutex back
 * exactly five times.
 *
 * This type of semaphore uses a priority inheritance mechanism so a task
 * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
 * semaphore it is no longer required.
 *
 * Mutex type semaphores cannot be used from within interrupt service routines.
 *
 * See xSemaphoreCreateBinary() for an alternative implementation that can be
 * used for pure synchronisation (where one task or interrupt always 'gives' the
 * semaphore and another always 'takes' the semaphore) and from within interrupt
 * service routines.
 *
 * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
 * which will then be used to hold the recursive mutex's data structure,
 * removing the need for the memory to be allocated dynamically.
 *
 * @return If the recursive mutex was successfully created then a handle to the
 * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
 * returned.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 * StaticSemaphore_t xMutexBuffer;
 *
 * void vATask( void * pvParameters )
 * {
 *  // A recursive semaphore cannot be used before it is created.  Here a
 *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
 *  // The address of xMutexBuffer is passed into the function, and will hold
 *  // the mutexes data structures - so no dynamic memory allocation will be
 *  // attempted.
 *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
 *
 *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
 *  // so there is no need to check it.
 * }
 * @endcode
 * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
 * \ingroup Semaphores
 */
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
    #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore )    xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
 * @endcode
 *
 * Creates a new counting semaphore instance, and returns a handle by which the
 * new counting semaphore can be referenced.
 *
 * In many usage scenarios it is faster and more memory efficient to use a
 * direct to task notification in place of a counting semaphore!
 * https://www.FreeRTOS.org/RTOS-task-notifications.html
 *
 * Internally, within the FreeRTOS implementation, counting semaphores use a
 * block of memory, in which the counting semaphore structure is stored.  If a
 * counting semaphore is created using xSemaphoreCreateCounting() then the
 * required memory is automatically dynamically allocated inside the
 * xSemaphoreCreateCounting() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
 * using xSemaphoreCreateCountingStatic() then the application writer can
 * instead optionally provide the memory that will get used by the counting
 * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
 * semaphore to be created without using any dynamic memory allocation.
 *
 * Counting semaphores are typically used for two things:
 *
 * 1) Counting events.
 *
 *    In this usage scenario an event handler will 'give' a semaphore each time
 *    an event occurs (incrementing the semaphore count value), and a handler
 *    task will 'take' a semaphore each time it processes an event
 *    (decrementing the semaphore count value).  The count value is therefore
 *    the difference between the number of events that have occurred and the
 *    number that have been processed.  In this case it is desirable for the
 *    initial count value to be zero.
 *
 * 2) Resource management.
 *
 *    In this usage scenario the count value indicates the number of resources
 *    available.  To obtain control of a resource a task must first obtain a
 *    semaphore - decrementing the semaphore count value.  When the count value
 *    reaches zero there are no free resources.  When a task finishes with the
 *    resource it 'gives' the semaphore back - incrementing the semaphore count
 *    value.  In this case it is desirable for the initial count value to be
 *    equal to the maximum count value, indicating that all resources are free.
 *
 * @param uxMaxCount The maximum count value that can be reached.  When the
 *        semaphore reaches this value it can no longer be 'given'.
 *
 * @param uxInitialCount The count value assigned to the semaphore when it is
 *        created.
 *
 * @return Handle to the created semaphore.  Null if the semaphore could not be
 *         created.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 *
 * void vATask( void * pvParameters )
 * {
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
 *  // The max value to which the semaphore can count should be 10, and the
 *  // initial value assigned to the count should be 0.
 *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
 *
 *  if( xSemaphore != NULL )
 *  {
 *      // The semaphore was created successfully.
 *      // The semaphore can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
 * \ingroup Semaphores
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount )    xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
#endif

/**
 * semphr. h
 * @code{c}
 * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
 * @endcode
 *
 * Creates a new counting semaphore instance, and returns a handle by which the
 * new counting semaphore can be referenced.
 *
 * In many usage scenarios it is faster and more memory efficient to use a
 * direct to task notification in place of a counting semaphore!
 * https://www.FreeRTOS.org/RTOS-task-notifications.html
 *
 * Internally, within the FreeRTOS implementation, counting semaphores use a
 * block of memory, in which the counting semaphore structure is stored.  If a
 * counting semaphore is created using xSemaphoreCreateCounting() then the
 * required memory is automatically dynamically allocated inside the
 * xSemaphoreCreateCounting() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
 * using xSemaphoreCreateCountingStatic() then the application writer must
 * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
 * counting semaphore to be created without using any dynamic memory allocation.
 *
 * Counting semaphores are typically used for two things:
 *
 * 1) Counting events.
 *
 *    In this usage scenario an event handler will 'give' a semaphore each time
 *    an event occurs (incrementing the semaphore count value), and a handler
 *    task will 'take' a semaphore each time it processes an event
 *    (decrementing the semaphore count value).  The count value is therefore
 *    the difference between the number of events that have occurred and the
 *    number that have been processed.  In this case it is desirable for the
 *    initial count value to be zero.
 *
 * 2) Resource management.
 *
 *    In this usage scenario the count value indicates the number of resources
 *    available.  To obtain control of a resource a task must first obtain a
 *    semaphore - decrementing the semaphore count value.  When the count value
 *    reaches zero there are no free resources.  When a task finishes with the
 *    resource it 'gives' the semaphore back - incrementing the semaphore count
 *    value.  In this case it is desirable for the initial count value to be
 *    equal to the maximum count value, indicating that all resources are free.
 *
 * @param uxMaxCount The maximum count value that can be reached.  When the
 *        semaphore reaches this value it can no longer be 'given'.
 *
 * @param uxInitialCount The count value assigned to the semaphore when it is
 *        created.
 *
 * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
 * which will then be used to hold the semaphore's data structure, removing the
 * need for the memory to be allocated dynamically.
 *
 * @return If the counting semaphore was successfully created then a handle to
 * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
 * then NULL is returned.
 *
 * Example usage:
 * @code{c}
 * SemaphoreHandle_t xSemaphore;
 * StaticSemaphore_t xSemaphoreBuffer;
 *
 * void vATask( void * pvParameters )
 * {
 * SemaphoreHandle_t xSemaphore = NULL;
 *
 *  // Counting semaphore cannot be used before they have been created.  Create
 *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
 *  // value to which the semaphore can count is 10, and the initial value
 *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
 *  // passed in and will be used to hold the semaphore structure, so no dynamic
 *  // memory allocation will be used.
 *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
 *
 *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
 *  // is no need to check its value.
 * }
 * @endcode
 * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
 * \ingroup Semaphores
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer )    xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * semphr. h
 * @code{c}
 * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
 * @endcode
 *
 * Delete a semaphore.  This function must be used with care.  For example,
 * do not delete a mutex type semaphore if the mutex is held by a task.
 *
 * @param xSemaphore A handle to the semaphore to be deleted.
 *
 * \defgroup vSemaphoreDelete vSemaphoreDelete
 * \ingroup Semaphores
 */
#define vSemaphoreDelete( xSemaphore )    vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )

/**
 * semphr.h
 * @code{c}
 * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
 * @endcode
 *
 * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
 * If xMutex is not a mutex type semaphore, or the mutex is available (not held
 * by a task), return NULL.
 *
 * Note: This is a good way of determining if the calling task is the mutex
 * holder, but not a good way of determining the identity of the mutex holder as
 * the holder may change between the function exiting and the returned value
 * being tested.
 */
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
    #define xSemaphoreGetMutexHolder( xSemaphore )    xQueueGetMutexHolder( ( xSemaphore ) )
#endif

/**
 * semphr.h
 * @code{c}
 * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
 * @endcode
 *
 * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
 * If xMutex is not a mutex type semaphore, or the mutex is available (not held
 * by a task), return NULL.
 *
 */
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
    #define xSemaphoreGetMutexHolderFromISR( xSemaphore )    xQueueGetMutexHolderFromISR( ( xSemaphore ) )
#endif

/**
 * semphr.h
 * @code{c}
 * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
 * @endcode
 *
 * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
 * its current count value.  If the semaphore is a binary semaphore then
 * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
 * semaphore is not available.
 *
 */
#define uxSemaphoreGetCount( xSemaphore )           uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )

/**
 * semphr.h
 * @code{c}
 * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore );
 * @endcode
 *
 * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns
 * its current count value.  If the semaphore is a binary semaphore then
 * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the
 * semaphore is not available.
 *
 */
#define uxSemaphoreGetCountFromISR( xSemaphore )    uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )

/**
 * semphr.h
 * @code{c}
 * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore,
 *                                       StaticSemaphore_t ** ppxSemaphoreBuffer );
 * @endcode
 *
 * Retrieve pointer to a statically created binary semaphore, counting semaphore,
 * or mutex semaphore's data structure buffer. This is the same buffer that is
 * supplied at the time of creation.
 *
 * @param xSemaphore The semaphore for which to retrieve the buffer.
 *
 * @param ppxSemaphoreBuffer Used to return a pointer to the semaphore's
 * data structure buffer.
 *
 * @return pdTRUE if buffer was retrieved, pdFALSE otherwise.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    #define xSemaphoreGetStaticBuffer( xSemaphore, ppxSemaphoreBuffer )    xQueueGenericGetStaticBuffers( ( QueueHandle_t ) ( xSemaphore ), NULL, ( ppxSemaphoreBuffer ) )
#endif /* configSUPPORT_STATIC_ALLOCATION */

#endif /* SEMAPHORE_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef STACK_MACROS_H
#define STACK_MACROS_H

/*
 * Call the stack overflow hook function if the stack of the task being swapped
 * out is currently overflowed, or looks like it might have overflowed in the
 * past.
 *
 * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
 * the current stack state only - comparing the current top of stack value to
 * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
 * will also cause the last few stack bytes to be checked to ensure the value
 * to which the bytes were set when the task was created have not been
 * overwritten.  Note this second test does not guarantee that an overflowed
 * stack will always be recognised.
 */

/*-----------------------------------------------------------*/

/*
 * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in
 * use on the stack.
 */
#ifndef portSTACK_LIMIT_PADDING
    #define portSTACK_LIMIT_PADDING    0
#endif

#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )

/* Only the current stack state is to be checked. */
    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
    do {                                                                                        \
        /* Is the currently saved stack pointer within the stack limit? */                      \
        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
        {                                                                                       \
            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
        }                                                                                       \
    } while( 0 )

#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
/*-----------------------------------------------------------*/

#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )

/* Only the current stack state is to be checked. */
    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
    do {                                                                                         \
                                                                                                 \
        /* Is the currently saved stack pointer within the stack limit? */                       \
        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
        {                                                                                        \
            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
        }                                                                                        \
    } while( 0 )

#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
/*-----------------------------------------------------------*/

#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )

    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
    do {                                                                                        \
        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                 \
        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                 \
                                                                                                \
        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                \
            ( pulStack[ 1 ] != ulCheckValue ) ||                                                \
            ( pulStack[ 2 ] != ulCheckValue ) ||                                                \
            ( pulStack[ 3 ] != ulCheckValue ) )                                                 \
        {                                                                                       \
            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
        }                                                                                       \
    } while( 0 )

#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
/*-----------------------------------------------------------*/

#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )

    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
    do {                                                                                                                                  \
        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
                                                                                                                                          \
                                                                                                                                          \
        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
                                                                                                                                          \
        /* Has the extremity of the task stack ever been written over? */                                                                 \
        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
        {                                                                                                                                 \
            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );                                           \
        }                                                                                                                                 \
    } while( 0 )

#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
/*-----------------------------------------------------------*/

/* Remove stack overflow macro if not being used. */
#ifndef taskCHECK_FOR_STACK_OVERFLOW
    #define taskCHECK_FOR_STACK_OVERFLOW()
#endif



#endif /* STACK_MACROS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/*
 * Stream buffers are used to send a continuous stream of data from one task or
 * interrupt to another.  Their implementation is light weight, making them
 * particularly suited for interrupt to task and core to core communication
 * scenarios.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xStreamBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xStreamBufferReceive()) inside a critical section section and set the
 * receive block time to 0.
 *
 */

#ifndef STREAM_BUFFER_H
#define STREAM_BUFFER_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
#endif

/* *INDENT-OFF* */
#if defined( __cplusplus )
    extern "C" {
#endif
/* *INDENT-ON* */

/**
 * Type of stream buffer. For internal use only.
 */
#define sbTYPE_STREAM_BUFFER             ( ( BaseType_t ) 0 )
#define sbTYPE_MESSAGE_BUFFER            ( ( BaseType_t ) 1 )
#define sbTYPE_STREAM_BATCHING_BUFFER    ( ( BaseType_t ) 2 )

/**
 * Type by which stream buffers are referenced.  For example, a call to
 * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
 * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
 * etc.
 */
struct StreamBufferDef_t;
typedef struct StreamBufferDef_t * StreamBufferHandle_t;

/**
 *  Type used as a stream buffer's optional callback.
 */
typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer,
                                                 BaseType_t xIsInsideISR,
                                                 BaseType_t * const pxHigherPriorityTaskWoken );

/**
 * stream_buffer.h
 *
 * @code{c}
 * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
 * @endcode
 *
 * Creates a new stream buffer using dynamically allocated memory.  See
 * xStreamBufferCreateStatic() for a version that uses statically allocated
 * memory (memory that is allocated at compile time).
 *
 * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
 * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferCreate() to be available.
 *
 * @param xBufferSizeBytes The total number of bytes the stream buffer will be
 * able to hold at any one time.
 *
 * @param xTriggerLevelBytes The number of bytes that must be in the stream
 * buffer before a task that is blocked on the stream buffer to wait for data is
 * moved out of the blocked state.  For example, if a task is blocked on a read
 * of an empty stream buffer that has a trigger level of 1 then the task will be
 * unblocked when a single byte is written to the buffer or the task's block
 * time expires.  As another example, if a task is blocked on a read of an empty
 * stream buffer that has a trigger level of 10 then the task will not be
 * unblocked until the stream buffer contains at least 10 bytes or the task's
 * block time expires.  If a reading task's block time expires before the
 * trigger level is reached then the task will still receive however many bytes
 * are actually available.  Setting a trigger level of 0 will result in a
 * trigger level of 1 being used.  It is not valid to specify a trigger level
 * that is greater than the buffer size.
 *
 * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
 * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
 * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
 * stream buffer. If the parameter is NULL, it will use the default
 * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @return If NULL is returned, then the stream buffer cannot be created
 * because there is insufficient heap memory available for FreeRTOS to allocate
 * the stream buffer data structures and storage area.  A non-NULL value being
 * returned indicates that the stream buffer has been created successfully -
 * the returned value should be stored as the handle to the created stream
 * buffer.
 *
 * Example use:
 * @code{c}
 *
 * void vAFunction( void )
 * {
 * StreamBufferHandle_t xStreamBuffer;
 * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
 *
 *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
 *  // both the stream buffer structure and the data in the stream buffer is
 *  // allocated dynamically.
 *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
 *
 *  if( xStreamBuffer == NULL )
 *  {
 *      // There was not enough heap memory space available to create the
 *      // stream buffer.
 *  }
 *  else
 *  {
 *      // The stream buffer was created successfully and can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xStreamBufferCreate xStreamBufferCreate
 * \ingroup StreamBufferManagement
 */

#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * stream_buffer.h
 *
 * @code{c}
 * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
 *                                                 size_t xTriggerLevelBytes,
 *                                                 uint8_t *pucStreamBufferStorageArea,
 *                                                 StaticStreamBuffer_t *pxStaticStreamBuffer );
 * @endcode
 * Creates a new stream buffer using statically allocated memory.  See
 * xStreamBufferCreate() for a version that uses dynamically allocated memory.
 *
 * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
 * xStreamBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS must be
 * set to 1 in for FreeRTOSConfig.h for xStreamBufferCreateStatic() to be
 * available.
 *
 * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
 * pucStreamBufferStorageArea parameter.
 *
 * @param xTriggerLevelBytes The number of bytes that must be in the stream
 * buffer before a task that is blocked on the stream buffer to wait for data is
 * moved out of the blocked state.  For example, if a task is blocked on a read
 * of an empty stream buffer that has a trigger level of 1 then the task will be
 * unblocked when a single byte is written to the buffer or the task's block
 * time expires.  As another example, if a task is blocked on a read of an empty
 * stream buffer that has a trigger level of 10 then the task will not be
 * unblocked until the stream buffer contains at least 10 bytes or the task's
 * block time expires.  If a reading task's block time expires before the
 * trigger level is reached then the task will still receive however many bytes
 * are actually available.  Setting a trigger level of 0 will result in a
 * trigger level of 1 being used.  It is not valid to specify a trigger level
 * that is greater than the buffer size.
 *
 * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
 * least xBufferSizeBytes big.  This is the array to which streams are
 * copied when they are written to the stream buffer.
 *
 * @param pxStaticStreamBuffer Must point to a variable of type
 * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
 * structure.
 *
 * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
 * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
 * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
 * stream buffer. If the parameter is NULL, it will use the default
 * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
 * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
 *
 * @return If the stream buffer is created successfully then a handle to the
 * created stream buffer is returned. If either pucStreamBufferStorageArea or
 * pxStaticstreamBuffer are NULL then NULL is returned.
 *
 * Example use:
 * @code{c}
 *
 * // Used to dimension the array used to hold the streams.  The available space
 * // will actually be one less than this, so 999.
 #define STORAGE_SIZE_BYTES 1000
 *
 * // Defines the memory that will actually hold the streams within the stream
 * // buffer.
 * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
 *
 * // The variable used to hold the stream buffer structure.
 * StaticStreamBuffer_t xStreamBufferStruct;
 *
 * void MyFunction( void )
 * {
 * StreamBufferHandle_t xStreamBuffer;
 * const size_t xTriggerLevel = 1;
 *
 *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
 *                                             xTriggerLevel,
 *                                             ucStorageBuffer,
 *                                             &xStreamBufferStruct );
 *
 *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
 *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
 *  // reference the created stream buffer in other stream buffer API calls.
 *
 *  // Other code that uses the stream buffer can go here.
 * }
 *
 * @endcode
 * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
 * \ingroup StreamBufferManagement
 */

#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * stream_buffer.h
 *
 * @code{c}
 * StreamBufferHandle_t xStreamBatchingBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
 * @endcode
 *
 * Creates a new stream batching buffer using dynamically allocated memory.  See
 * xStreamBatchingBufferCreateStatic() for a version that uses statically
 * allocated memory (memory that is allocated at compile time).
 *
 * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
 * FreeRTOSConfig.h for xStreamBatchingBufferCreate() to be available.
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBatchingBufferCreate() to be available.
 *
 * The difference between a stream buffer and a stream batching buffer is when
 * a task performs read on a non-empty buffer:
 * - The task reading from a non-empty stream buffer returns immediately
 *   regardless of the amount of data in the buffer.
 * - The task reading from a non-empty steam batching buffer blocks until the
 *   amount of data in the buffer exceeds the trigger level or the block time
 *   expires.
 *
 * @param xBufferSizeBytes The total number of bytes the stream batching buffer
 * will be able to hold at any one time.
 *
 * @param xTriggerLevelBytes The number of bytes that must be in the stream
 * batching buffer to unblock a task calling xStreamBufferReceive before the
 * block time expires.
 *
 * @param pxSendCompletedCallback Callback invoked when number of bytes at least
 * equal to trigger level is sent to the stream batching buffer. If the
 * parameter is NULL, it will use the default implementation provided by
 * sbSEND_COMPLETED macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK
 * must be set to 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
 * are read from a stream batching buffer. If the parameter is NULL, it will use
 * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
 * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
 * FreeRTOSConfig.h.
 *
 * @return If NULL is returned, then the stream batching buffer cannot be created
 * because there is insufficient heap memory available for FreeRTOS to allocate
 * the stream batching buffer data structures and storage area.  A non-NULL value
 * being returned indicates that the stream batching buffer has been created
 * successfully - the returned value should be stored as the handle to the
 * created stream batching buffer.
 *
 * Example use:
 * @code{c}
 *
 * void vAFunction( void )
 * {
 * StreamBufferHandle_t xStreamBatchingBuffer;
 * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
 *
 *  // Create a stream batching buffer that can hold 100 bytes.  The memory used
 *  // to hold both the stream batching buffer structure and the data in the stream
 *  // batching buffer is allocated dynamically.
 *  xStreamBatchingBuffer = xStreamBatchingBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
 *
 *  if( xStreamBatchingBuffer == NULL )
 *  {
 *      // There was not enough heap memory space available to create the
 *      // stream batching buffer.
 *  }
 *  else
 *  {
 *      // The stream batching buffer was created successfully and can now be used.
 *  }
 * }
 * @endcode
 * \defgroup xStreamBatchingBufferCreate xStreamBatchingBufferCreate
 * \ingroup StreamBatchingBufferManagement
 */

#define xStreamBatchingBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xStreamBatchingBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * stream_buffer.h
 *
 * @code{c}
 * StreamBufferHandle_t xStreamBatchingBufferCreateStatic( size_t xBufferSizeBytes,
 *                                                         size_t xTriggerLevelBytes,
 *                                                         uint8_t *pucStreamBufferStorageArea,
 *                                                         StaticStreamBuffer_t *pxStaticStreamBuffer );
 * @endcode
 * Creates a new stream batching buffer using statically allocated memory.  See
 * xStreamBatchingBufferCreate() for a version that uses dynamically allocated
 * memory.
 *
 * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
 * xStreamBatchingBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS
 * must be set to 1 in for FreeRTOSConfig.h for xStreamBatchingBufferCreateStatic()
 * to be available.
 *
 * The difference between a stream buffer and a stream batching buffer is when
 * a task performs read on a non-empty buffer:
 * - The task reading from a non-empty stream buffer returns immediately
 *   regardless of the amount of data in the buffer.
 * - The task reading from a non-empty steam batching buffer blocks until the
 *   amount of data in the buffer exceeds the trigger level or the block time
 *   expires.
 *
 * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
 * pucStreamBufferStorageArea parameter.
 *
 * @param xTriggerLevelBytes The number of bytes that must be in the stream
 * batching buffer to unblock a task calling xStreamBufferReceive before the
 * block time expires.
 *
 * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
 * least xBufferSizeBytes big.  This is the array to which streams are
 * copied when they are written to the stream batching buffer.
 *
 * @param pxStaticStreamBuffer Must point to a variable of type
 * StaticStreamBuffer_t, which will be used to hold the stream batching buffer's
 * data structure.
 *
 * @param pxSendCompletedCallback Callback invoked when number of bytes at least
 * equal to trigger level is sent to the stream batching buffer. If the parameter
 * is NULL, it will use the default implementation provided by sbSEND_COMPLETED
 * macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK must be set to
 * 1 in FreeRTOSConfig.h.
 *
 * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
 * are read from a stream batching buffer. If the parameter is NULL, it will use
 * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
 * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
 * FreeRTOSConfig.h.
 *
 * @return If the stream batching buffer is created successfully then a handle
 * to the created stream batching buffer is returned. If either pucStreamBufferStorageArea
 * or pxStaticstreamBuffer are NULL then NULL is returned.
 *
 * Example use:
 * @code{c}
 *
 * // Used to dimension the array used to hold the streams.  The available space
 * // will actually be one less than this, so 999.
 * #define STORAGE_SIZE_BYTES 1000
 *
 * // Defines the memory that will actually hold the streams within the stream
 * // batching buffer.
 * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
 *
 * // The variable used to hold the stream batching buffer structure.
 * StaticStreamBuffer_t xStreamBufferStruct;
 *
 * void MyFunction( void )
 * {
 * StreamBufferHandle_t xStreamBatchingBuffer;
 * const size_t xTriggerLevel = 1;
 *
 *  xStreamBatchingBuffer = xStreamBatchingBufferCreateStatic( sizeof( ucStorageBuffer ),
 *                                                             xTriggerLevel,
 *                                                             ucStorageBuffer,
 *                                                             &xStreamBufferStruct );
 *
 *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
 *  // parameters were NULL, xStreamBatchingBuffer will not be NULL, and can be
 *  // used to reference the created stream batching buffer in other stream
 *  // buffer API calls.
 *
 *  // Other code that uses the stream batching buffer can go here.
 * }
 *
 * @endcode
 * \defgroup xStreamBatchingBufferCreateStatic xStreamBatchingBufferCreateStatic
 * \ingroup StreamBatchingBufferManagement
 */

#define xStreamBatchingBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )

#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    #define xStreamBatchingBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
#endif

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
 *                                           uint8_t ** ppucStreamBufferStorageArea,
 *                                           StaticStreamBuffer_t ** ppxStaticStreamBuffer );
 * @endcode
 *
 * Retrieve pointers to a statically created stream buffer's data structure
 * buffer and storage area buffer. These are the same buffers that are supplied
 * at the time of creation.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferGetStaticBuffers() to be available.
 *
 * @param xStreamBuffer The stream buffer for which to retrieve the buffers.
 *
 * @param ppucStreamBufferStorageArea Used to return a pointer to the stream
 * buffer's storage area buffer.
 *
 * @param ppxStaticStreamBuffer Used to return a pointer to the stream
 * buffer's data structure buffer.
 *
 * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
 *
 * \defgroup xStreamBufferGetStaticBuffers xStreamBufferGetStaticBuffers
 * \ingroup StreamBufferManagement
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
                                              uint8_t ** ppucStreamBufferStorageArea,
                                              StaticStreamBuffer_t ** ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
 *                           const void *pvTxData,
 *                           size_t xDataLengthBytes,
 *                           TickType_t xTicksToWait );
 * @endcode
 *
 * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xStreamBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xStreamBufferReceive()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
 * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
 * service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferSend() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer to which a stream is
 * being sent.
 *
 * @param pvTxData A pointer to the buffer that holds the bytes to be copied
 * into the stream buffer.
 *
 * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
 * into the stream buffer.
 *
 * @param xTicksToWait The maximum amount of time the task should remain in the
 * Blocked state to wait for enough space to become available in the stream
 * buffer, should the stream buffer contain too little space to hold the
 * another xDataLengthBytes bytes.  The block time is specified in tick periods,
 * so the absolute time it represents is dependent on the tick frequency.  The
 * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
 * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
 * cause the task to wait indefinitely (without timing out), provided
 * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
 * before it can write all xDataLengthBytes into the buffer it will still write
 * as many bytes as possible.  A task does not use any CPU time when it is in
 * the blocked state.
 *
 * @return The number of bytes written to the stream buffer.  If a task times
 * out before it can write all xDataLengthBytes into the buffer it will still
 * write as many bytes as possible.
 *
 * Example use:
 * @code{c}
 * void vAFunction( StreamBufferHandle_t xStreamBuffer )
 * {
 * size_t xBytesSent;
 * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
 * char *pcStringToSend = "String to send";
 * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
 *
 *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
 *  // wait for enough space to be available in the stream buffer.
 *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
 *
 *  if( xBytesSent != sizeof( ucArrayToSend ) )
 *  {
 *      // The call to xStreamBufferSend() times out before there was enough
 *      // space in the buffer for the data to be written, but it did
 *      // successfully write xBytesSent bytes.
 *  }
 *
 *  // Send the string to the stream buffer.  Return immediately if there is not
 *  // enough space in the buffer.
 *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
 *
 *  if( xBytesSent != strlen( pcStringToSend ) )
 *  {
 *      // The entire string could not be added to the stream buffer because
 *      // there was not enough free space in the buffer, but xBytesSent bytes
 *      // were sent.  Could try again to send the remaining bytes.
 *  }
 * }
 * @endcode
 * \defgroup xStreamBufferSend xStreamBufferSend
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                          const void * pvTxData,
                          size_t xDataLengthBytes,
                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
 *                                  const void *pvTxData,
 *                                  size_t xDataLengthBytes,
 *                                  BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * Interrupt safe version of the API function that sends a stream of bytes to
 * the stream buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xStreamBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xStreamBufferReceive()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
 * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
 * service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferSendFromISR() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer to which a stream is
 * being sent.
 *
 * @param pvTxData A pointer to the data that is to be copied into the stream
 * buffer.
 *
 * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
 * into the stream buffer.
 *
 * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
 * have a task blocked on it waiting for data.  Calling
 * xStreamBufferSendFromISR() can make data available, and so cause a task that
 * was waiting for data to leave the Blocked state.  If calling
 * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
 * unblocked task has a priority higher than the currently executing task (the
 * task that was interrupted), then, internally, xStreamBufferSendFromISR()
 * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
 * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
 * context switch should be performed before the interrupt is exited.  This will
 * ensure that the interrupt returns directly to the highest priority Ready
 * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
 * is passed into the function.  See the example code below for an example.
 *
 * @return The number of bytes actually written to the stream buffer, which will
 * be less than xDataLengthBytes if the stream buffer didn't have enough free
 * space for all the bytes to be written.
 *
 * Example use:
 * @code{c}
 * // A stream buffer that has already been created.
 * StreamBufferHandle_t xStreamBuffer;
 *
 * void vAnInterruptServiceRoutine( void )
 * {
 * size_t xBytesSent;
 * char *pcStringToSend = "String to send";
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
 *
 *  // Attempt to send the string to the stream buffer.
 *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
 *                                         ( void * ) pcStringToSend,
 *                                         strlen( pcStringToSend ),
 *                                         &xHigherPriorityTaskWoken );
 *
 *  if( xBytesSent != strlen( pcStringToSend ) )
 *  {
 *      // There was not enough free space in the stream buffer for the entire
 *      // string to be written, ut xBytesSent bytes were written.
 *  }
 *
 *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
 *  // xStreamBufferSendFromISR() then a task that has a priority above the
 *  // priority of the currently executing task was unblocked and a context
 *  // switch should be performed to ensure the ISR returns to the unblocked
 *  // task.  In most FreeRTOS ports this is done by simply passing
 *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
 *  // variables value, and perform the context switch if necessary.  Check the
 *  // documentation for the port in use for port specific instructions.
 *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 * }
 * @endcode
 * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
                                 const void * pvTxData,
                                 size_t xDataLengthBytes,
                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
 *                              void *pvRxData,
 *                              size_t xBufferLengthBytes,
 *                              TickType_t xTicksToWait );
 * @endcode
 *
 * Receives bytes from a stream buffer.
 *
 * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
 * implementation (so also the message buffer implementation, as message buffers
 * are built on top of stream buffers) assumes there is only one task or
 * interrupt that will write to the buffer (the writer), and only one task or
 * interrupt that will read from the buffer (the reader).  It is safe for the
 * writer and reader to be different tasks or interrupts, but, unlike other
 * FreeRTOS objects, it is not safe to have multiple different writers or
 * multiple different readers.  If there are to be multiple different writers
 * then the application writer must place each call to a writing API function
 * (such as xStreamBufferSend()) inside a critical section and set the send
 * block time to 0.  Likewise, if there are to be multiple different readers
 * then the application writer must place each call to a reading API function
 * (such as xStreamBufferReceive()) inside a critical section and set the receive
 * block time to 0.
 *
 * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
 * xStreamBufferReceiveFromISR() to read from a stream buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferReceive() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer from which bytes are to
 * be received.
 *
 * @param pvRxData A pointer to the buffer into which the received bytes will be
 * copied.
 *
 * @param xBufferLengthBytes The length of the buffer pointed to by the
 * pvRxData parameter.  This sets the maximum number of bytes to receive in one
 * call.  xStreamBufferReceive will return as many bytes as possible up to a
 * maximum set by xBufferLengthBytes.
 *
 * @param xTicksToWait The maximum amount of time the task should remain in the
 * Blocked state to wait for data to become available if the stream buffer is
 * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
 * zero.  The block time is specified in tick periods, so the absolute time it
 * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
 * be used to convert a time specified in milliseconds into a time specified in
 * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
 * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
 * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
 * Blocked state.
 *
 * @return The number of bytes actually read from the stream buffer, which will
 * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
 * out before xBufferLengthBytes were available.
 *
 * Example use:
 * @code{c}
 * void vAFunction( StreamBuffer_t xStreamBuffer )
 * {
 * uint8_t ucRxData[ 20 ];
 * size_t xReceivedBytes;
 * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
 *
 *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
 *  // Wait in the Blocked state (so not using any CPU processing time) for a
 *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
 *  // available.
 *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
 *                                         ( void * ) ucRxData,
 *                                         sizeof( ucRxData ),
 *                                         xBlockTime );
 *
 *  if( xReceivedBytes > 0 )
 *  {
 *      // A ucRxData contains another xReceivedBytes bytes of data, which can
 *      // be processed here....
 *  }
 * }
 * @endcode
 * \defgroup xStreamBufferReceive xStreamBufferReceive
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
                             void * pvRxData,
                             size_t xBufferLengthBytes,
                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
 *                                     void *pvRxData,
 *                                     size_t xBufferLengthBytes,
 *                                     BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * An interrupt safe version of the API function that receives bytes from a
 * stream buffer.
 *
 * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
 * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferReceiveFromISR() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer from which a stream
 * is being received.
 *
 * @param pvRxData A pointer to the buffer into which the received bytes are
 * copied.
 *
 * @param xBufferLengthBytes The length of the buffer pointed to by the
 * pvRxData parameter.  This sets the maximum number of bytes to receive in one
 * call.  xStreamBufferReceive will return as many bytes as possible up to a
 * maximum set by xBufferLengthBytes.
 *
 * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
 * have a task blocked on it waiting for space to become available.  Calling
 * xStreamBufferReceiveFromISR() can make space available, and so cause a task
 * that is waiting for space to leave the Blocked state.  If calling
 * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
 * the unblocked task has a priority higher than the currently executing task
 * (the task that was interrupted), then, internally,
 * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
 * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
 * context switch should be performed before the interrupt is exited.  That will
 * ensure the interrupt returns directly to the highest priority Ready state
 * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
 * passed into the function.  See the code example below for an example.
 *
 * @return The number of bytes read from the stream buffer, if any.
 *
 * Example use:
 * @code{c}
 * // A stream buffer that has already been created.
 * StreamBuffer_t xStreamBuffer;
 *
 * void vAnInterruptServiceRoutine( void )
 * {
 * uint8_t ucRxData[ 20 ];
 * size_t xReceivedBytes;
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
 *
 *  // Receive the next stream from the stream buffer.
 *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
 *                                                ( void * ) ucRxData,
 *                                                sizeof( ucRxData ),
 *                                                &xHigherPriorityTaskWoken );
 *
 *  if( xReceivedBytes > 0 )
 *  {
 *      // ucRxData contains xReceivedBytes read from the stream buffer.
 *      // Process the stream here....
 *  }
 *
 *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
 *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
 *  // priority of the currently executing task was unblocked and a context
 *  // switch should be performed to ensure the ISR returns to the unblocked
 *  // task.  In most FreeRTOS ports this is done by simply passing
 *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
 *  // variables value, and perform the context switch if necessary.  Check the
 *  // documentation for the port in use for port specific instructions.
 *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 * }
 * @endcode
 * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
                                    void * pvRxData,
                                    size_t xBufferLengthBytes,
                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Deletes a stream buffer that was previously created using a call to
 * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
 * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
 * then the allocated memory is freed.
 *
 * A stream buffer handle must not be used after the stream buffer has been
 * deleted.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * vStreamBufferDelete() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer to be deleted.
 *
 * \defgroup vStreamBufferDelete vStreamBufferDelete
 * \ingroup StreamBufferManagement
 */
void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Queries a stream buffer to see if it is full.  A stream buffer is full if it
 * does not have any free space, and therefore cannot accept any more data.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferIsFull() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being queried.
 *
 * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
 * pdFALSE is returned.
 *
 * \defgroup xStreamBufferIsFull xStreamBufferIsFull
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
 * it does not contain any data.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferIsEmpty() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being queried.
 *
 * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
 * pdFALSE is returned.
 *
 * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Resets a stream buffer to its initial, empty, state.  Any data that was in
 * the stream buffer is discarded.  A stream buffer can only be reset if there
 * are no tasks blocked waiting to either send to or receive from the stream
 * buffer.
 *
 * Use xStreamBufferReset() to reset a stream buffer from a task.
 * Use xStreamBufferResetFromISR() to reset a stream buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferReset() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being reset.
 *
 * @return If the stream buffer is reset then pdPASS is returned.  If there was
 * a task blocked waiting to send to or read from the stream buffer then the
 * stream buffer is not reset and pdFAIL is returned.
 *
 * \defgroup xStreamBufferReset xStreamBufferReset
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * An interrupt safe version of the API function that resets the stream buffer.
 *
 * Resets a stream buffer to its initial, empty, state.  Any data that was in
 * the stream buffer is discarded.  A stream buffer can only be reset if there
 * are no tasks blocked waiting to either send to or receive from the stream
 * buffer.
 *
 * Use xStreamBufferReset() to reset a stream buffer from a task.
 * Use xStreamBufferResetFromISR() to reset a stream buffer from an
 * interrupt service routine (ISR).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferResetFromISR() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being reset.
 *
 * @return If the stream buffer is reset then pdPASS is returned.  If there was
 * a task blocked waiting to send to or read from the stream buffer then the
 * stream buffer is not reset and pdFAIL is returned.
 *
 * \defgroup xStreamBufferResetFromISR xStreamBufferResetFromISR
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Queries a stream buffer to see how much free space it contains, which is
 * equal to the amount of data that can be sent to the stream buffer before it
 * is full.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferSpacesAvailable() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being queried.
 *
 * @return The number of bytes that can be written to the stream buffer before
 * the stream buffer would be full.
 *
 * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Queries a stream buffer to see how much data it contains, which is equal to
 * the number of bytes that can be read from the stream buffer before the stream
 * buffer would be empty.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferBytesAvailable() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being queried.
 *
 * @return The number of bytes that can be read from the stream buffer before
 * the stream buffer would be empty.
 *
 * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
 * \ingroup StreamBufferManagement
 */
size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
 * @endcode
 *
 * A stream buffer's trigger level is the number of bytes that must be in the
 * stream buffer before a task that is blocked on the stream buffer to
 * wait for data is moved out of the blocked state.  For example, if a task is
 * blocked on a read of an empty stream buffer that has a trigger level of 1
 * then the task will be unblocked when a single byte is written to the buffer
 * or the task's block time expires.  As another example, if a task is blocked
 * on a read of an empty stream buffer that has a trigger level of 10 then the
 * task will not be unblocked until the stream buffer contains at least 10 bytes
 * or the task's block time expires.  If a reading task's block time expires
 * before the trigger level is reached then the task will still receive however
 * many bytes are actually available.  Setting a trigger level of 0 will result
 * in a trigger level of 1 being used.  It is not valid to specify a trigger
 * level that is greater than the buffer size.
 *
 * A trigger level is set when the stream buffer is created, and can be modified
 * using xStreamBufferSetTriggerLevel().
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferSetTriggerLevel() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer being updated.
 *
 * @param xTriggerLevel The new trigger level for the stream buffer.
 *
 * @return If xTriggerLevel was less than or equal to the stream buffer's length
 * then the trigger level will be updated and pdTRUE is returned.  Otherwise
 * pdFALSE is returned.
 *
 * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * For advanced users only.
 *
 * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
 * data is sent to a message buffer or stream buffer.  If there was a task that
 * was blocked on the message or stream buffer waiting for data to arrive then
 * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
 * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
 * thing.  It is provided to enable application writers to implement their own
 * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
 *
 * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
 * additional information.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferSendCompletedFromISR() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer to which data was
 * written.
 *
 * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
 * initialised to pdFALSE before it is passed into
 * xStreamBufferSendCompletedFromISR().  If calling
 * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
 * and the task has a priority above the priority of the currently running task,
 * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
 * context switch should be performed before exiting the ISR.
 *
 * @return If a task was removed from the Blocked state then pdTRUE is returned.
 * Otherwise pdFALSE is returned.
 *
 * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * For advanced users only.
 *
 * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
 * data is read out of a message buffer or stream buffer.  If there was a task
 * that was blocked on the message or stream buffer waiting for data to arrive
 * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
 * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
 * does the same thing.  It is provided to enable application writers to
 * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
 * ANY OTHER TIME.
 *
 * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
 * additional information.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * xStreamBufferReceiveCompletedFromISR() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer from which data was
 * read.
 *
 * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
 * initialised to pdFALSE before it is passed into
 * xStreamBufferReceiveCompletedFromISR().  If calling
 * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
 * and the task has a priority above the priority of the currently running task,
 * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
 * context switch should be performed before exiting the ISR.
 *
 * @return If a task was removed from the Blocked state then pdTRUE is returned.
 * Otherwise pdFALSE is returned.
 *
 * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
 * \ingroup StreamBufferManagement
 */
BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer );
 * @endcode
 *
 * Get the task notification index used for the supplied stream buffer which can
 * be set using vStreamBufferSetStreamBufferNotificationIndex. If the task
 * notification index for the stream buffer is not changed using
 * vStreamBufferSetStreamBufferNotificationIndex, this function returns the
 * default value (tskDEFAULT_INDEX_TO_NOTIFY).
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * uxStreamBufferGetStreamBufferNotificationIndex() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer for which the task
 * notification index is retrieved.
 *
 * @return The task notification index for the stream buffer.
 *
 * \defgroup uxStreamBufferGetStreamBufferNotificationIndex uxStreamBufferGetStreamBufferNotificationIndex
 * \ingroup StreamBufferManagement
 */
UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

/**
 * stream_buffer.h
 *
 * @code{c}
 * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex );
 * @endcode
 *
 * Set the task notification index used for the supplied stream buffer.
 * Successive calls to stream buffer APIs (like xStreamBufferSend or
 * xStreamBufferReceive) for this stream buffer will use this new index for
 * their task notifications.
 *
 * If this function is not called, the default index (tskDEFAULT_INDEX_TO_NOTIFY)
 * is used for task notifications. It is recommended to call this function
 * before attempting to send or receive data from the stream buffer to avoid
 * inconsistencies.
 *
 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
 * vStreamBufferSetStreamBufferNotificationIndex() to be available.
 *
 * @param xStreamBuffer The handle of the stream buffer for which the task
 * notification index is set.
 *
 * @param uxNotificationIndex The task notification index to set.
 *
 * \defgroup vStreamBufferSetStreamBufferNotificationIndex vStreamBufferSetStreamBufferNotificationIndex
 * \ingroup StreamBufferManagement
 */
void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
                                                    UBaseType_t uxNotificationIndex ) PRIVILEGED_FUNCTION;

/* Functions below here are not part of the public API. */
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                 size_t xTriggerLevelBytes,
                                                 BaseType_t xStreamBufferType,
                                                 StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                 StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                           size_t xTriggerLevelBytes,
                                                           BaseType_t xStreamBufferType,
                                                           uint8_t * const pucStreamBufferStorageArea,
                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
#endif

size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;

#if ( configUSE_TRACE_FACILITY == 1 )
    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
#endif

/* *INDENT-OFF* */
#if defined( __cplusplus )
    }
#endif
/* *INDENT-ON* */

#endif /* !defined( STREAM_BUFFER_H ) */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


#ifndef INC_TASK_H
#define INC_TASK_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include task.h"
#endif

#include "list.h"

/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/*-----------------------------------------------------------
* MACROS AND DEFINITIONS
*----------------------------------------------------------*/

/*
 * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development
 * after the numbered release.
 *
 * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD
 * values will reflect the last released version number.
 */
#define tskKERNEL_VERSION_NUMBER       "V11.1.0"
#define tskKERNEL_VERSION_MAJOR        11
#define tskKERNEL_VERSION_MINOR        1
#define tskKERNEL_VERSION_BUILD        0

/* MPU region parameters passed in ulParameters
 * of MemoryRegion_t struct. */
#define tskMPU_REGION_READ_ONLY        ( 1U << 0U )
#define tskMPU_REGION_READ_WRITE       ( 1U << 1U )
#define tskMPU_REGION_EXECUTE_NEVER    ( 1U << 2U )
#define tskMPU_REGION_NORMAL_MEMORY    ( 1U << 3U )
#define tskMPU_REGION_DEVICE_MEMORY    ( 1U << 4U )

/* MPU region permissions stored in MPU settings to
 * authorize access requests. */
#define tskMPU_READ_PERMISSION         ( 1U << 0U )
#define tskMPU_WRITE_PERMISSION        ( 1U << 1U )

/* The direct to task notification feature used to have only a single notification
 * per task.  Now there is an array of notifications per task that is dimensioned by
 * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
 * original direct to task notification defaults to using the first index in the
 * array. */
#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )

/**
 * task. h
 *
 * Type by which tasks are referenced.  For example, a call to xTaskCreate
 * returns (via a pointer parameter) an TaskHandle_t variable that can then
 * be used as a parameter to vTaskDelete to delete the task.
 *
 * \defgroup TaskHandle_t TaskHandle_t
 * \ingroup Tasks
 */
struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
typedef struct tskTaskControlBlock         * TaskHandle_t;
typedef const struct tskTaskControlBlock   * ConstTaskHandle_t;

/*
 * Defines the prototype to which the application task hook function must
 * conform.
 */
typedef BaseType_t (* TaskHookFunction_t)( void * arg );

/* Task states returned by eTaskGetState. */
typedef enum
{
    eRunning = 0, /* A task is querying the state of itself, so must be running. */
    eReady,       /* The task being queried is in a ready or pending ready list. */
    eBlocked,     /* The task being queried is in the Blocked state. */
    eSuspended,   /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
    eDeleted,     /* The task being queried has been deleted, but its TCB has not yet been freed. */
    eInvalid      /* Used as an 'invalid state' value. */
} eTaskState;

/* Actions that can be performed when vTaskNotify() is called. */
typedef enum
{
    eNoAction = 0,            /* Notify the task without updating its notify value. */
    eSetBits,                 /* Set bits in the task's notification value. */
    eIncrement,               /* Increment the task's notification value. */
    eSetValueWithOverwrite,   /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
    eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */
} eNotifyAction;

/*
 * Used internally only.
 */
typedef struct xTIME_OUT
{
    BaseType_t xOverflowCount;
    TickType_t xTimeOnEntering;
} TimeOut_t;

/*
 * Defines the memory ranges allocated to the task when an MPU is used.
 */
typedef struct xMEMORY_REGION
{
    void * pvBaseAddress;
    uint32_t ulLengthInBytes;
    uint32_t ulParameters;
} MemoryRegion_t;

/*
 * Parameters required to create an MPU protected task.
 */
typedef struct xTASK_PARAMETERS
{
    TaskFunction_t pvTaskCode;
    const char * pcName;
    configSTACK_DEPTH_TYPE usStackDepth;
    void * pvParameters;
    UBaseType_t uxPriority;
    StackType_t * puxStackBuffer;
    MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
    #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
        StaticTask_t * const pxTaskBuffer;
    #endif
} TaskParameters_t;

/* Used with the uxTaskGetSystemState() function to return the state of each task
 * in the system. */
typedef struct xTASK_STATUS
{
    TaskHandle_t xHandle;                         /* The handle of the task to which the rest of the information in the structure relates. */
    const char * pcTaskName;                      /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */
    UBaseType_t xTaskNumber;                      /* A number unique to the task. */
    eTaskState eCurrentState;                     /* The state in which the task existed when the structure was populated. */
    UBaseType_t uxCurrentPriority;                /* The priority at which the task was running (may be inherited) when the structure was populated. */
    UBaseType_t uxBasePriority;                   /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
    configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
    StackType_t * pxStackBase;                    /* Points to the lowest address of the task's stack area. */
    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
        StackType_t * pxTopOfStack;               /* Points to the top address of the task's stack area. */
        StackType_t * pxEndOfStack;               /* Points to the end address of the task's stack area. */
    #endif
    configSTACK_DEPTH_TYPE usStackHighWaterMark;  /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
    #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
        UBaseType_t uxCoreAffinityMask;           /* The core affinity mask for the task */
    #endif
} TaskStatus_t;

/* Possible return values for eTaskConfirmSleepModeStatus(). */
typedef enum
{
    eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
    eStandardSleep   /* Enter a sleep mode that will not last any longer than the expected idle time. */
    #if ( INCLUDE_vTaskSuspend == 1 )
        ,
        eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
    #endif /* INCLUDE_vTaskSuspend */
} eSleepModeStatus;

/**
 * Defines the priority used by the idle task.  This must not be modified.
 *
 * \ingroup TaskUtils
 */
#define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )

/**
 * Defines affinity to all available cores.
 *
 * \ingroup TaskUtils
 */
#define tskNO_AFFINITY      ( ( UBaseType_t ) -1 )

/**
 * task. h
 *
 * Macro for forcing a context switch.
 *
 * \defgroup taskYIELD taskYIELD
 * \ingroup SchedulerControl
 */
#define taskYIELD()                          portYIELD()

/**
 * task. h
 *
 * Macro to mark the start of a critical code region.  Preemptive context
 * switches cannot occur when in a critical region.
 *
 * NOTE: This may alter the stack (depending on the portable implementation)
 * so must be used with care!
 *
 * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
 * \ingroup SchedulerControl
 */
#define taskENTER_CRITICAL()                 portENTER_CRITICAL()
#if ( configNUMBER_OF_CORES == 1 )
    #define taskENTER_CRITICAL_FROM_ISR()    portSET_INTERRUPT_MASK_FROM_ISR()
#else
    #define taskENTER_CRITICAL_FROM_ISR()    portENTER_CRITICAL_FROM_ISR()
#endif

/**
 * task. h
 *
 * Macro to mark the end of a critical code region.  Preemptive context
 * switches cannot occur when in a critical region.
 *
 * NOTE: This may alter the stack (depending on the portable implementation)
 * so must be used with care!
 *
 * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
 * \ingroup SchedulerControl
 */
#define taskEXIT_CRITICAL()                    portEXIT_CRITICAL()
#if ( configNUMBER_OF_CORES == 1 )
    #define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
#else
    #define taskEXIT_CRITICAL_FROM_ISR( x )    portEXIT_CRITICAL_FROM_ISR( x )
#endif

/**
 * task. h
 *
 * Macro to disable all maskable interrupts.
 *
 * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
 * \ingroup SchedulerControl
 */
#define taskDISABLE_INTERRUPTS()    portDISABLE_INTERRUPTS()

/**
 * task. h
 *
 * Macro to enable microcontroller interrupts.
 *
 * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
 * \ingroup SchedulerControl
 */
#define taskENABLE_INTERRUPTS()     portENABLE_INTERRUPTS()

/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
 * 0 to generate more optimal code when configASSERT() is defined as the constant
 * is used in assert() statements. */
#define taskSCHEDULER_SUSPENDED      ( ( BaseType_t ) 0 )
#define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )
#define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )

/* Checks if core ID is valid. */
#define taskVALID_CORE_ID( xCoreID )    ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) )

/*-----------------------------------------------------------
* TASK CREATION API
*----------------------------------------------------------*/

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskCreate(
 *                            TaskFunction_t pxTaskCode,
 *                            const char * const pcName,
 *                            const configSTACK_DEPTH_TYPE uxStackDepth,
 *                            void *pvParameters,
 *                            UBaseType_t uxPriority,
 *                            TaskHandle_t *pxCreatedTask
 *                        );
 * @endcode
 *
 * Create a new task and add it to the list of tasks that are ready to run.
 *
 * Internally, within the FreeRTOS implementation, tasks use two blocks of
 * memory.  The first block is used to hold the task's data structures.  The
 * second block is used by the task as its stack.  If a task is created using
 * xTaskCreate() then both blocks of memory are automatically dynamically
 * allocated inside the xTaskCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a task is created using
 * xTaskCreateStatic() then the application writer must provide the required
 * memory.  xTaskCreateStatic() therefore allows a task to be created without
 * using any dynamic memory allocation.
 *
 * See xTaskCreateStatic() for a version that does not use any dynamic memory
 * allocation.
 *
 * xTaskCreate() can only be used to create a task that has unrestricted
 * access to the entire microcontroller memory map.  Systems that include MPU
 * support can alternatively create an MPU constrained task using
 * xTaskCreateRestricted().
 *
 * @param pxTaskCode Pointer to the task entry function.  Tasks
 * must be implemented to never return (i.e. continuous loop).
 *
 * @param pcName A descriptive name for the task.  This is mainly used to
 * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
 * is 16.
 *
 * @param uxStackDepth The size of the task stack specified as the number of
 * variables the stack can hold - not the number of bytes.  For example, if
 * the stack is 16 bits wide and uxStackDepth is defined as 100, 200 bytes
 * will be allocated for stack storage.
 *
 * @param pvParameters Pointer that will be used as the parameter for the task
 * being created.
 *
 * @param uxPriority The priority at which the task should run.  Systems that
 * include MPU support can optionally create tasks in a privileged (system)
 * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
 * example, to create a privileged task at priority 2 the uxPriority parameter
 * should be set to ( 2 | portPRIVILEGE_BIT ).
 *
 * @param pxCreatedTask Used to pass back a handle by which the created task
 * can be referenced.
 *
 * @return pdPASS if the task was successfully created and added to a ready
 * list, otherwise an error code defined in the file projdefs.h
 *
 * Example usage:
 * @code{c}
 * // Task to be created.
 * void vTaskCode( void * pvParameters )
 * {
 *   for( ;; )
 *   {
 *       // Task code goes here.
 *   }
 * }
 *
 * // Function that creates a task.
 * void vOtherFunction( void )
 * {
 * static uint8_t ucParameterToPass;
 * TaskHandle_t xHandle = NULL;
 *
 *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
 *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
 *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
 *   // the new task attempts to access it.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
 *   configASSERT( xHandle );
 *
 *   // Use the handle to delete the task.
 *   if( xHandle != NULL )
 *   {
 *      vTaskDelete( xHandle );
 *   }
 * }
 * @endcode
 * \defgroup xTaskCreate xTaskCreate
 * \ingroup Tasks
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
                            const char * const pcName,
                            const configSTACK_DEPTH_TYPE uxStackDepth,
                            void * const pvParameters,
                            UBaseType_t uxPriority,
                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
                                       const char * const pcName,
                                       const configSTACK_DEPTH_TYPE uxStackDepth,
                                       void * const pvParameters,
                                       UBaseType_t uxPriority,
                                       UBaseType_t uxCoreAffinityMask,
                                       TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
 *                               const char * const pcName,
 *                               const configSTACK_DEPTH_TYPE uxStackDepth,
 *                               void *pvParameters,
 *                               UBaseType_t uxPriority,
 *                               StackType_t *puxStackBuffer,
 *                               StaticTask_t *pxTaskBuffer );
 * @endcode
 *
 * Create a new task and add it to the list of tasks that are ready to run.
 *
 * Internally, within the FreeRTOS implementation, tasks use two blocks of
 * memory.  The first block is used to hold the task's data structures.  The
 * second block is used by the task as its stack.  If a task is created using
 * xTaskCreate() then both blocks of memory are automatically dynamically
 * allocated inside the xTaskCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a task is created using
 * xTaskCreateStatic() then the application writer must provide the required
 * memory.  xTaskCreateStatic() therefore allows a task to be created without
 * using any dynamic memory allocation.
 *
 * @param pxTaskCode Pointer to the task entry function.  Tasks
 * must be implemented to never return (i.e. continuous loop).
 *
 * @param pcName A descriptive name for the task.  This is mainly used to
 * facilitate debugging.  The maximum length of the string is defined by
 * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
 *
 * @param uxStackDepth The size of the task stack specified as the number of
 * variables the stack can hold - not the number of bytes.  For example, if
 * the stack is 32-bits wide and uxStackDepth is defined as 100 then 400 bytes
 * will be allocated for stack storage.
 *
 * @param pvParameters Pointer that will be used as the parameter for the task
 * being created.
 *
 * @param uxPriority The priority at which the task will run.
 *
 * @param puxStackBuffer Must point to a StackType_t array that has at least
 * uxStackDepth indexes - the array will then be used as the task's stack,
 * removing the need for the stack to be allocated dynamically.
 *
 * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
 * then be used to hold the task's data structures, removing the need for the
 * memory to be allocated dynamically.
 *
 * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task
 * will be created and a handle to the created task is returned.  If either
 * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
 * NULL is returned.
 *
 * Example usage:
 * @code{c}
 *
 *  // Dimensions of the buffer that the task being created will use as its stack.
 *  // NOTE:  This is the number of words the stack will hold, not the number of
 *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
 *  // then 400 bytes (100 * 32-bits) will be allocated.
 #define STACK_SIZE 200
 *
 *  // Structure that will hold the TCB of the task being created.
 *  StaticTask_t xTaskBuffer;
 *
 *  // Buffer that the task being created will use as its stack.  Note this is
 *  // an array of StackType_t variables.  The size of StackType_t is dependent on
 *  // the RTOS port.
 *  StackType_t xStack[ STACK_SIZE ];
 *
 *  // Function that implements the task being created.
 *  void vTaskCode( void * pvParameters )
 *  {
 *      // The parameter value is expected to be 1 as 1 is passed in the
 *      // pvParameters value in the call to xTaskCreateStatic().
 *      configASSERT( ( uint32_t ) pvParameters == 1U );
 *
 *      for( ;; )
 *      {
 *          // Task code goes here.
 *      }
 *  }
 *
 *  // Function that creates a task.
 *  void vOtherFunction( void )
 *  {
 *      TaskHandle_t xHandle = NULL;
 *
 *      // Create the task without using any dynamic memory allocation.
 *      xHandle = xTaskCreateStatic(
 *                    vTaskCode,       // Function that implements the task.
 *                    "NAME",          // Text name for the task.
 *                    STACK_SIZE,      // Stack size in words, not bytes.
 *                    ( void * ) 1,    // Parameter passed into the task.
 *                    tskIDLE_PRIORITY,// Priority at which the task is created.
 *                    xStack,          // Array to use as the task's stack.
 *                    &xTaskBuffer );  // Variable to hold the task's data structure.
 *
 *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
 *      // been created, and xHandle will be the task's handle.  Use the handle
 *      // to suspend the task.
 *      vTaskSuspend( xHandle );
 *  }
 * @endcode
 * \defgroup xTaskCreateStatic xTaskCreateStatic
 * \ingroup Tasks
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                    const char * const pcName,
                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                    void * const pvParameters,
                                    UBaseType_t uxPriority,
                                    StackType_t * const puxStackBuffer,
                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
                                               const char * const pcName,
                                               const configSTACK_DEPTH_TYPE uxStackDepth,
                                               void * const pvParameters,
                                               UBaseType_t uxPriority,
                                               StackType_t * const puxStackBuffer,
                                               StaticTask_t * const pxTaskBuffer,
                                               UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
 * @endcode
 *
 * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
 *
 * xTaskCreateRestricted() should only be used in systems that include an MPU
 * implementation.
 *
 * Create a new task and add it to the list of tasks that are ready to run.
 * The function parameters define the memory regions and associated access
 * permissions allocated to the task.
 *
 * See xTaskCreateRestrictedStatic() for a version that does not use any
 * dynamic memory allocation.
 *
 * @param pxTaskDefinition Pointer to a structure that contains a member
 * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
 * documentation) plus an optional stack buffer and the memory region
 * definitions.
 *
 * @param pxCreatedTask Used to pass back a handle by which the created task
 * can be referenced.
 *
 * @return pdPASS if the task was successfully created and added to a ready
 * list, otherwise an error code defined in the file projdefs.h
 *
 * Example usage:
 * @code{c}
 * // Create an TaskParameters_t structure that defines the task to be created.
 * static const TaskParameters_t xCheckTaskParameters =
 * {
 *  vATask,     // pvTaskCode - the function that implements the task.
 *  "ATask",    // pcName - just a text name for the task to assist debugging.
 *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
 *  NULL,       // pvParameters - passed into the task function as the function parameters.
 *  ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
 *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
 *
 *  // xRegions - Allocate up to three separate memory regions for access by
 *  // the task, with appropriate access permissions.  Different processors have
 *  // different memory alignment requirements - refer to the FreeRTOS documentation
 *  // for full information.
 *  {
 *      // Base address                 Length  Parameters
 *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
 *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
 *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
 *  }
 * };
 *
 * int main( void )
 * {
 * TaskHandle_t xHandle;
 *
 *  // Create a task from the const structure defined above.  The task handle
 *  // is requested (the second parameter is not NULL) but in this case just for
 *  // demonstration purposes as its not actually used.
 *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
 *
 *  // Start the scheduler.
 *  vTaskStartScheduler();
 *
 *  // Will only get here if there was insufficient memory to create the idle
 *  // and/or timer task.
 *  for( ;; );
 * }
 * @endcode
 * \defgroup xTaskCreateRestricted xTaskCreateRestricted
 * \ingroup Tasks
 */
#if ( portUSING_MPU_WRAPPERS == 1 )
    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
                                                 UBaseType_t uxCoreAffinityMask,
                                                 TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
 * @endcode
 *
 * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
 *
 * xTaskCreateRestrictedStatic() should only be used in systems that include an
 * MPU implementation.
 *
 * Internally, within the FreeRTOS implementation, tasks use two blocks of
 * memory.  The first block is used to hold the task's data structures.  The
 * second block is used by the task as its stack.  If a task is created using
 * xTaskCreateRestricted() then the stack is provided by the application writer,
 * and the memory used to hold the task's data structure is automatically
 * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
 * is created using xTaskCreateRestrictedStatic() then the application writer
 * must provide the memory used to hold the task's data structures too.
 * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
 * created without using any dynamic memory allocation.
 *
 * @param pxTaskDefinition Pointer to a structure that contains a member
 * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
 * documentation) plus an optional stack buffer and the memory region
 * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
 * contains an additional member, which is used to point to a variable of type
 * StaticTask_t - which is then used to hold the task's data structure.
 *
 * @param pxCreatedTask Used to pass back a handle by which the created task
 * can be referenced.
 *
 * @return pdPASS if the task was successfully created and added to a ready
 * list, otherwise an error code defined in the file projdefs.h
 *
 * Example usage:
 * @code{c}
 * // Create an TaskParameters_t structure that defines the task to be created.
 * // The StaticTask_t variable is only included in the structure when
 * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
 * // be used to force the variable into the RTOS kernel's privileged data area.
 * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
 * static const TaskParameters_t xCheckTaskParameters =
 * {
 *  vATask,     // pvTaskCode - the function that implements the task.
 *  "ATask",    // pcName - just a text name for the task to assist debugging.
 *  100,        // uxStackDepth - the stack size DEFINED IN WORDS.
 *  NULL,       // pvParameters - passed into the task function as the function parameters.
 *  ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
 *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
 *
 *  // xRegions - Allocate up to three separate memory regions for access by
 *  // the task, with appropriate access permissions.  Different processors have
 *  // different memory alignment requirements - refer to the FreeRTOS documentation
 *  // for full information.
 *  {
 *      // Base address                 Length  Parameters
 *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
 *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
 *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
 *  }
 *
 *  &xTaskBuffer; // Holds the task's data structure.
 * };
 *
 * int main( void )
 * {
 * TaskHandle_t xHandle;
 *
 *  // Create a task from the const structure defined above.  The task handle
 *  // is requested (the second parameter is not NULL) but in this case just for
 *  // demonstration purposes as its not actually used.
 *  xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle );
 *
 *  // Start the scheduler.
 *  vTaskStartScheduler();
 *
 *  // Will only get here if there was insufficient memory to create the idle
 *  // and/or timer task.
 *  for( ;; );
 * }
 * @endcode
 * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
 * \ingroup Tasks
 */
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
                                                       UBaseType_t uxCoreAffinityMask,
                                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
 * @endcode
 *
 * Memory regions are assigned to a restricted task when the task is created by
 * a call to xTaskCreateRestricted().  These regions can be redefined using
 * vTaskAllocateMPURegions().
 *
 * @param xTaskToModify The handle of the task being updated.
 *
 * @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the
 * new memory region definitions.
 *
 * Example usage:
 * @code{c}
 * // Define an array of MemoryRegion_t structures that configures an MPU region
 * // allowing read/write access for 1024 bytes starting at the beginning of the
 * // ucOneKByte array.  The other two of the maximum 3 definable regions are
 * // unused so set to zero.
 * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
 * {
 *  // Base address     Length      Parameters
 *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
 *  { 0,                0,          0 },
 *  { 0,                0,          0 }
 * };
 *
 * void vATask( void *pvParameters )
 * {
 *  // This task was created such that it has access to certain regions of
 *  // memory as defined by the MPU configuration.  At some point it is
 *  // desired that these MPU regions are replaced with that defined in the
 *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
 *  // for this purpose.  NULL is used as the task handle to indicate that this
 *  // function should modify the MPU regions of the calling task.
 *  vTaskAllocateMPURegions( NULL, xAltRegions );
 *
 *  // Now the task can continue its function, but from this point on can only
 *  // access its stack and the ucOneKByte array (unless any other statically
 *  // defined or shared regions have been declared elsewhere).
 * }
 * @endcode
 * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions
 * \ingroup Tasks
 */
#if ( portUSING_MPU_WRAPPERS == 1 )
    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
                                  const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskDelete( TaskHandle_t xTaskToDelete );
 * @endcode
 *
 * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Remove a task from the RTOS real time kernel's management.  The task being
 * deleted will be removed from all ready, blocked, suspended and event lists.
 *
 * NOTE:  The idle task is responsible for freeing the kernel allocated
 * memory from tasks that have been deleted.  It is therefore important that
 * the idle task is not starved of microcontroller processing time if your
 * application makes any calls to vTaskDelete ().  Memory allocated by the
 * task code is not automatically freed, and should be freed before the task
 * is deleted.
 *
 * See the demo application file death.c for sample code that utilises
 * vTaskDelete ().
 *
 * @param xTaskToDelete The handle of the task to be deleted.  Passing NULL will
 * cause the calling task to be deleted.
 *
 * Example usage:
 * @code{c}
 * void vOtherFunction( void )
 * {
 * TaskHandle_t xHandle;
 *
 *   // Create the task, storing the handle.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
 *
 *   // Use the handle to delete the task.
 *   vTaskDelete( xHandle );
 * }
 * @endcode
 * \defgroup vTaskDelete vTaskDelete
 * \ingroup Tasks
 */
void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;

/*-----------------------------------------------------------
* TASK CONTROL API
*----------------------------------------------------------*/

/**
 * task. h
 * @code{c}
 * void vTaskDelay( const TickType_t xTicksToDelay );
 * @endcode
 *
 * Delay a task for a given number of ticks.  The actual time that the
 * task remains blocked depends on the tick rate.  The constant
 * portTICK_PERIOD_MS can be used to calculate real time from the tick
 * rate - with the resolution of one tick period.
 *
 * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 *
 * vTaskDelay() specifies a time at which the task wishes to unblock relative to
 * the time at which vTaskDelay() is called.  For example, specifying a block
 * period of 100 ticks will cause the task to unblock 100 ticks after
 * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
 * of controlling the frequency of a periodic task as the path taken through the
 * code, as well as other task and interrupt activity, will affect the frequency
 * at which vTaskDelay() gets called and therefore the time at which the task
 * next executes.  See xTaskDelayUntil() for an alternative API function designed
 * to facilitate fixed frequency execution.  It does this by specifying an
 * absolute time (rather than a relative time) at which the calling task should
 * unblock.
 *
 * @param xTicksToDelay The amount of time, in tick periods, that
 * the calling task should block.
 *
 * Example usage:
 *
 * void vTaskFunction( void * pvParameters )
 * {
 * // Block for 500ms.
 * const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
 *
 *   for( ;; )
 *   {
 *       // Simply toggle the LED every 500ms, blocking between each toggle.
 *       vToggleLED();
 *       vTaskDelay( xDelay );
 *   }
 * }
 *
 * \defgroup vTaskDelay vTaskDelay
 * \ingroup TaskCtrl
 */
void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
 * @endcode
 *
 * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Delay a task until a specified time.  This function can be used by periodic
 * tasks to ensure a constant execution frequency.
 *
 * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
 * cause a task to block for the specified number of ticks from the time vTaskDelay () is
 * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
 * execution frequency as the time between a task starting to execute and that task
 * calling vTaskDelay () may not be fixed [the task may take a different path though the
 * code between calls, or may get interrupted or preempted a different number of times
 * each time it executes].
 *
 * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
 * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
 * unblock.
 *
 * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a
 * time specified in milliseconds with a resolution of one tick period.
 *
 * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
 * task was last unblocked.  The variable must be initialised with the current time
 * prior to its first use (see the example below).  Following this the variable is
 * automatically updated within xTaskDelayUntil ().
 *
 * @param xTimeIncrement The cycle time period.  The task will be unblocked at
 * time *pxPreviousWakeTime + xTimeIncrement.  Calling xTaskDelayUntil with the
 * same xTimeIncrement parameter value will cause the task to execute with
 * a fixed interface period.
 *
 * @return Value which can be used to check whether the task was actually delayed.
 * Will be pdTRUE if the task way delayed and pdFALSE otherwise.  A task will not
 * be delayed if the next expected wake time is in the past.
 *
 * Example usage:
 * @code{c}
 * // Perform an action every 10 ticks.
 * void vTaskFunction( void * pvParameters )
 * {
 * TickType_t xLastWakeTime;
 * const TickType_t xFrequency = 10;
 * BaseType_t xWasDelayed;
 *
 *     // Initialise the xLastWakeTime variable with the current time.
 *     xLastWakeTime = xTaskGetTickCount ();
 *     for( ;; )
 *     {
 *         // Wait for the next cycle.
 *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
 *
 *         // Perform action here. xWasDelayed value can be used to determine
 *         // whether a deadline was missed if the code here took too long.
 *     }
 * }
 * @endcode
 * \defgroup xTaskDelayUntil xTaskDelayUntil
 * \ingroup TaskCtrl
 */
BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
                            const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;

/*
 * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not
 * return a value.
 */
#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )                   \
    do {                                                                        \
        ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \
    } while( 0 )


/**
 * task. h
 * @code{c}
 * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
 * function to be available.
 *
 * A task will enter the Blocked state when it is waiting for an event.  The
 * event it is waiting for can be a temporal event (waiting for a time), such
 * as when vTaskDelay() is called, or an event on an object, such as when
 * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
 * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
 * task will leave the Blocked state, and return from whichever function call
 * placed the task into the Blocked state.
 *
 * There is no 'FromISR' version of this function as an interrupt would need to
 * know which object a task was blocked on in order to know which actions to
 * take.  For example, if the task was blocked on a queue the interrupt handler
 * would then need to know if the queue was locked.
 *
 * @param xTask The handle of the task to remove from the Blocked state.
 *
 * @return If the task referenced by xTask was not in the Blocked state then
 * pdFAIL is returned.  Otherwise pdPASS is returned.
 *
 * \defgroup xTaskAbortDelay xTaskAbortDelay
 * \ingroup TaskCtrl
 */
#if ( INCLUDE_xTaskAbortDelay == 1 )
    BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Obtain the priority of any task.
 *
 * @param xTask Handle of the task to be queried.  Passing a NULL
 * handle results in the priority of the calling task being returned.
 *
 * @return The priority of xTask.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 *
 *   // Create a task, storing the handle.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
 *
 *   // ...
 *
 *   // Use the handle to obtain the priority of the created task.
 *   // It was created with tskIDLE_PRIORITY, but may have changed
 *   // it itself.
 *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
 *   {
 *       // The task has changed it's priority.
 *   }
 *
 *   // ...
 *
 *   // Is our priority higher than the created task?
 *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
 *   {
 *       // Our priority (obtained using NULL handle) is higher.
 *   }
 * }
 * @endcode
 * \defgroup uxTaskPriorityGet uxTaskPriorityGet
 * \ingroup TaskCtrl
 */
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
 * @endcode
 *
 * A version of uxTaskPriorityGet() that can be used from an ISR.
 */
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this
 * function to be available. See the configuration section for more information.
 *
 * Obtain the base priority of any task.
 *
 * @param xTask Handle of the task to be queried.  Passing a NULL
 * handle results in the base priority of the calling task being returned.
 *
 * @return The base priority of xTask.
 *
 * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet
 * \ingroup TaskCtrl
 */
UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask );
 * @endcode
 *
 * A version of uxTaskBasePriorityGet() that can be used from an ISR.
 */
UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * eTaskState eTaskGetState( TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Obtain the state of any task.  States are encoded by the eTaskState
 * enumerated type.
 *
 * @param xTask Handle of the task to be queried.
 *
 * @return The state of xTask at the time the function was called.  Note the
 * state of the task might change between the function being called, and the
 * functions return value being tested by the calling task.
 */
#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
    eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
 * @endcode
 *
 * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
 * available.  See the configuration section for more information.
 *
 * Populates a TaskStatus_t structure with information about a task.
 *
 * @param xTask Handle of the task being queried.  If xTask is NULL then
 * information will be returned about the calling task.
 *
 * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
 * filled with information about the task referenced by the handle passed using
 * the xTask parameter.
 *
 * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report
 * the stack high water mark of the task being queried.  Calculating the stack
 * high water mark takes a relatively long time, and can make the system
 * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
 * allow the high water mark checking to be skipped.  The high watermark value
 * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
 * not set to pdFALSE;
 *
 * @param eState The TaskStatus_t structure contains a member to report the
 * state of the task being queried.  Obtaining the task state is not as fast as
 * a simple assignment - so the eState parameter is provided to allow the state
 * information to be omitted from the TaskStatus_t structure.  To obtain state
 * information then set eState to eInvalid - otherwise the value passed in
 * eState will be reported as the task state in the TaskStatus_t structure.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 * TaskStatus_t xTaskDetails;
 *
 *  // Obtain the handle of a task from its name.
 *  xHandle = xTaskGetHandle( "Task_Name" );
 *
 *  // Check the handle is not NULL.
 *  configASSERT( xHandle );
 *
 *  // Use the handle to obtain further information about the task.
 *  vTaskGetInfo( xHandle,
 *                &xTaskDetails,
 *                pdTRUE, // Include the high water mark in xTaskDetails.
 *                eInvalid ); // Include the task state in xTaskDetails.
 * }
 * @endcode
 * \defgroup vTaskGetInfo vTaskGetInfo
 * \ingroup TaskCtrl
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    void vTaskGetInfo( TaskHandle_t xTask,
                       TaskStatus_t * pxTaskStatus,
                       BaseType_t xGetFreeStackSpace,
                       eTaskState eState ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
 * @endcode
 *
 * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Set the priority of any task.
 *
 * A context switch will occur before the function returns if the priority
 * being set is higher than the currently executing task.
 *
 * @param xTask Handle to the task for which the priority is being set.
 * Passing a NULL handle results in the priority of the calling task being set.
 *
 * @param uxNewPriority The priority to which the task will be set.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 *
 *   // Create a task, storing the handle.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
 *
 *   // ...
 *
 *   // Use the handle to raise the priority of the created task.
 *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
 *
 *   // ...
 *
 *   // Use a NULL handle to raise our priority to the same value.
 *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
 * }
 * @endcode
 * \defgroup vTaskPrioritySet vTaskPrioritySet
 * \ingroup TaskCtrl
 */
void vTaskPrioritySet( TaskHandle_t xTask,
                       UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
 * @endcode
 *
 * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Suspend any task.  When suspended a task will never get any microcontroller
 * processing time, no matter what its priority.
 *
 * Calls to vTaskSuspend are not accumulative -
 * i.e. calling vTaskSuspend () twice on the same task still only requires one
 * call to vTaskResume () to ready the suspended task.
 *
 * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
 * handle will cause the calling task to be suspended.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 *
 *   // Create a task, storing the handle.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
 *
 *   // ...
 *
 *   // Use the handle to suspend the created task.
 *   vTaskSuspend( xHandle );
 *
 *   // ...
 *
 *   // The created task will not run during this period, unless
 *   // another task calls vTaskResume( xHandle ).
 *
 *   //...
 *
 *
 *   // Suspend ourselves.
 *   vTaskSuspend( NULL );
 *
 *   // We cannot get here unless another task calls vTaskResume
 *   // with our handle as the parameter.
 * }
 * @endcode
 * \defgroup vTaskSuspend vTaskSuspend
 * \ingroup TaskCtrl
 */
void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * void vTaskResume( TaskHandle_t xTaskToResume );
 * @endcode
 *
 * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
 * See the configuration section for more information.
 *
 * Resumes a suspended task.
 *
 * A task that has been suspended by one or more calls to vTaskSuspend ()
 * will be made available for running again by a single call to
 * vTaskResume ().
 *
 * @param xTaskToResume Handle to the task being readied.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 *
 *   // Create a task, storing the handle.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
 *
 *   // ...
 *
 *   // Use the handle to suspend the created task.
 *   vTaskSuspend( xHandle );
 *
 *   // ...
 *
 *   // The created task will not run during this period, unless
 *   // another task calls vTaskResume( xHandle ).
 *
 *   //...
 *
 *
 *   // Resume the suspended task ourselves.
 *   vTaskResume( xHandle );
 *
 *   // The created task will once again get microcontroller processing
 *   // time in accordance with its priority within the system.
 * }
 * @endcode
 * \defgroup vTaskResume vTaskResume
 * \ingroup TaskCtrl
 */
void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
 * @endcode
 *
 * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
 * available.  See the configuration section for more information.
 *
 * An implementation of vTaskResume() that can be called from within an ISR.
 *
 * A task that has been suspended by one or more calls to vTaskSuspend ()
 * will be made available for running again by a single call to
 * xTaskResumeFromISR ().
 *
 * xTaskResumeFromISR() should not be used to synchronise a task with an
 * interrupt if there is a chance that the interrupt could arrive prior to the
 * task being suspended - as this can lead to interrupts being missed. Use of a
 * semaphore as a synchronisation mechanism would avoid this eventuality.
 *
 * @param xTaskToResume Handle to the task being readied.
 *
 * @return pdTRUE if resuming the task should result in a context switch,
 * otherwise pdFALSE. This is used by the ISR to determine if a context switch
 * may be required following the ISR.
 *
 * \defgroup vTaskResumeFromISR vTaskResumeFromISR
 * \ingroup TaskCtrl
 */
BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;

#if ( configUSE_CORE_AFFINITY == 1 )

/**
 * @brief Sets the core affinity mask for a task.
 *
 * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must
 * be defined as 1 for this function to be available.
 *
 * @param xTask The handle of the task to set the core affinity mask for.
 * Passing NULL will set the core affinity mask for the calling task.
 *
 * @param uxCoreAffinityMask A bitwise value that indicates the cores on
 * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1.
 * For example, to ensure that a task can run on core 0 and core 1, set
 * uxCoreAffinityMask to 0x03.
 *
 * Example usage:
 *
 * // The function that creates task.
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 * UBaseType_t uxCoreAffinityMask;
 *
 *      // Create a task, storing the handle.
 *      xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
 *
 *      // Define the core affinity mask such that this task can only run
 *      // on core 0 and core 2.
 *      uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) );
 *
 *      //Set the core affinity mask for the task.
 *      vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask );
 * }
 */
    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
                               UBaseType_t uxCoreAffinityMask );
#endif

#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )

/**
 * @brief Gets the core affinity mask for a task.
 *
 * configUSE_CORE_AFFINITY must be defined as 1 for this function to be
 * available.
 *
 * @param xTask The handle of the task to get the core affinity mask for.
 * Passing NULL will get the core affinity mask for the calling task.
 *
 * @return The core affinity mask which is a bitwise value that indicates
 * the cores on which a task can run. Cores are numbered from 0 to
 * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1,
 * the core affinity mask is 0x03.
 *
 * Example usage:
 *
 * // Task handle of the networking task - it is populated elsewhere.
 * TaskHandle_t xNetworkingTaskHandle;
 *
 * void vAFunction( void )
 * {
 * TaskHandle_t xHandle;
 * UBaseType_t uxNetworkingCoreAffinityMask;
 *
 *     // Create a task, storing the handle.
 *     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) );
 *
 *     //Get the core affinity mask for the networking task.
 *     uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle );
 *
 *     // Here is a hypothetical scenario, just for the example. Assume that we
 *     // have 2 cores - Core 0 and core 1. We want to pin the application task to
 *     // the core different than the networking task to ensure that the
 *     // application task does not interfere with networking.
 *     if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 )
 *     {
 *         // The networking task can run on core 0, pin our task to core 1.
 *         vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) );
 *     }
 *     else
 *     {
 *         // Otherwise, pin our task to core 0.
 *         vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) );
 *     }
 * }
 */
    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask );
#endif

#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )

/**
 * @brief Disables preemption for a task.
 *
 * @param xTask The handle of the task to disable preemption. Passing NULL
 * disables preemption for the calling task.
 *
 * Example usage:
 *
 * void vTaskCode( void *pvParameters )
 * {
 *     // Silence warnings about unused parameters.
 *     ( void ) pvParameters;
 *
 *     for( ;; )
 *     {
 *         // ... Perform some function here.
 *
 *         // Disable preemption for this task.
 *         vTaskPreemptionDisable( NULL );
 *
 *         // The task will not be preempted when it is executing in this portion ...
 *
 *         // ... until the preemption is enabled again.
 *         vTaskPreemptionEnable( NULL );
 *
 *         // The task can be preempted when it is executing in this portion.
 *     }
 * }
 */
    void vTaskPreemptionDisable( const TaskHandle_t xTask );
#endif

#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )

/**
 * @brief Enables preemption for a task.
 *
 * @param xTask The handle of the task to enable preemption. Passing NULL
 * enables preemption for the calling task.
 *
 * Example usage:
 *
 * void vTaskCode( void *pvParameters )
 * {
 *     // Silence warnings about unused parameters.
 *     ( void ) pvParameters;
 *
 *     for( ;; )
 *     {
 *         // ... Perform some function here.
 *
 *         // Disable preemption for this task.
 *         vTaskPreemptionDisable( NULL );
 *
 *         // The task will not be preempted when it is executing in this portion ...
 *
 *         // ... until the preemption is enabled again.
 *         vTaskPreemptionEnable( NULL );
 *
 *         // The task can be preempted when it is executing in this portion.
 *     }
 * }
 */
    void vTaskPreemptionEnable( const TaskHandle_t xTask );
#endif

/*-----------------------------------------------------------
* SCHEDULER CONTROL
*----------------------------------------------------------*/

/**
 * task. h
 * @code{c}
 * void vTaskStartScheduler( void );
 * @endcode
 *
 * Starts the real time kernel tick processing.  After calling the kernel
 * has control over which tasks are executed and when.
 *
 * See the demo application file main.c for an example of creating
 * tasks and starting the kernel.
 *
 * Example usage:
 * @code{c}
 * void vAFunction( void )
 * {
 *   // Create at least one task before starting the kernel.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
 *
 *   // Start the real time kernel with preemption.
 *   vTaskStartScheduler ();
 *
 *   // Will not get here unless a task calls vTaskEndScheduler ()
 * }
 * @endcode
 *
 * \defgroup vTaskStartScheduler vTaskStartScheduler
 * \ingroup SchedulerControl
 */
void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * void vTaskEndScheduler( void );
 * @endcode
 *
 * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
 * in place of DOS, implements this function.
 *
 * Stops the real time kernel tick.  All created tasks will be automatically
 * deleted and multitasking (either preemptive or cooperative) will
 * stop.  Execution then resumes from the point where vTaskStartScheduler ()
 * was called, as if vTaskStartScheduler () had just returned.
 *
 * See the demo application file main. c in the demo/PC directory for an
 * example that uses vTaskEndScheduler ().
 *
 * vTaskEndScheduler () requires an exit function to be defined within the
 * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
 * performs hardware specific operations such as stopping the kernel tick.
 *
 * vTaskEndScheduler () will cause all of the resources allocated by the
 * kernel to be freed - but will not free resources allocated by application
 * tasks.
 *
 * Example usage:
 * @code{c}
 * void vTaskCode( void * pvParameters )
 * {
 *   for( ;; )
 *   {
 *       // Task code goes here.
 *
 *       // At some point we want to end the real time kernel processing
 *       // so call ...
 *       vTaskEndScheduler ();
 *   }
 * }
 *
 * void vAFunction( void )
 * {
 *   // Create at least one task before starting the kernel.
 *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
 *
 *   // Start the real time kernel with preemption.
 *   vTaskStartScheduler ();
 *
 *   // Will only get here when the vTaskCode () task has called
 *   // vTaskEndScheduler ().  When we get here we are back to single task
 *   // execution.
 * }
 * @endcode
 *
 * \defgroup vTaskEndScheduler vTaskEndScheduler
 * \ingroup SchedulerControl
 */
void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * void vTaskSuspendAll( void );
 * @endcode
 *
 * Suspends the scheduler without disabling interrupts.  Context switches will
 * not occur while the scheduler is suspended.
 *
 * After calling vTaskSuspendAll () the calling task will continue to execute
 * without risk of being swapped out until a call to xTaskResumeAll () has been
 * made.
 *
 * API functions that have the potential to cause a context switch (for example,
 * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
 * is suspended.
 *
 * Example usage:
 * @code{c}
 * void vTask1( void * pvParameters )
 * {
 *   for( ;; )
 *   {
 *       // Task code goes here.
 *
 *       // ...
 *
 *       // At some point the task wants to perform a long operation during
 *       // which it does not want to get swapped out.  It cannot use
 *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
 *       // operation may cause interrupts to be missed - including the
 *       // ticks.
 *
 *       // Prevent the real time kernel swapping out the task.
 *       vTaskSuspendAll ();
 *
 *       // Perform the operation here.  There is no need to use critical
 *       // sections as we have all the microcontroller processing time.
 *       // During this time interrupts will still operate and the kernel
 *       // tick count will be maintained.
 *
 *       // ...
 *
 *       // The operation is complete.  Restart the kernel.
 *       xTaskResumeAll ();
 *   }
 * }
 * @endcode
 * \defgroup vTaskSuspendAll vTaskSuspendAll
 * \ingroup SchedulerControl
 */
void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskResumeAll( void );
 * @endcode
 *
 * Resumes scheduler activity after it was suspended by a call to
 * vTaskSuspendAll().
 *
 * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
 * that were previously suspended by a call to vTaskSuspend().
 *
 * @return If resuming the scheduler caused a context switch then pdTRUE is
 *         returned, otherwise pdFALSE is returned.
 *
 * Example usage:
 * @code{c}
 * void vTask1( void * pvParameters )
 * {
 *   for( ;; )
 *   {
 *       // Task code goes here.
 *
 *       // ...
 *
 *       // At some point the task wants to perform a long operation during
 *       // which it does not want to get swapped out.  It cannot use
 *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
 *       // operation may cause interrupts to be missed - including the
 *       // ticks.
 *
 *       // Prevent the real time kernel swapping out the task.
 *       vTaskSuspendAll ();
 *
 *       // Perform the operation here.  There is no need to use critical
 *       // sections as we have all the microcontroller processing time.
 *       // During this time interrupts will still operate and the real
 *       // time kernel tick count will be maintained.
 *
 *       // ...
 *
 *       // The operation is complete.  Restart the kernel.  We want to force
 *       // a context switch - but there is no point if resuming the scheduler
 *       // caused a context switch already.
 *       if( !xTaskResumeAll () )
 *       {
 *            taskYIELD ();
 *       }
 *   }
 * }
 * @endcode
 * \defgroup xTaskResumeAll xTaskResumeAll
 * \ingroup SchedulerControl
 */
BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;

/*-----------------------------------------------------------
* TASK UTILITIES
*----------------------------------------------------------*/

/**
 * task. h
 * @code{c}
 * TickType_t xTaskGetTickCount( void );
 * @endcode
 *
 * @return The count of ticks since vTaskStartScheduler was called.
 *
 * \defgroup xTaskGetTickCount xTaskGetTickCount
 * \ingroup TaskUtils
 */
TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * TickType_t xTaskGetTickCountFromISR( void );
 * @endcode
 *
 * @return The count of ticks since vTaskStartScheduler was called.
 *
 * This is a version of xTaskGetTickCount() that is safe to be called from an
 * ISR - provided that TickType_t is the natural word size of the
 * microcontroller being used or interrupt nesting is either not supported or
 * not being used.
 *
 * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
 * \ingroup TaskUtils
 */
TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * uint16_t uxTaskGetNumberOfTasks( void );
 * @endcode
 *
 * @return The number of tasks that the real time kernel is currently managing.
 * This includes all ready, blocked and suspended tasks.  A task that
 * has been deleted but not yet freed by the idle task will also be
 * included in the count.
 *
 * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
 * \ingroup TaskUtils
 */
UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * char *pcTaskGetName( TaskHandle_t xTaskToQuery );
 * @endcode
 *
 * @return The text (human readable) name of the task referenced by the handle
 * xTaskToQuery.  A task can query its own name by either passing in its own
 * handle, or by setting xTaskToQuery to NULL.
 *
 * \defgroup pcTaskGetName pcTaskGetName
 * \ingroup TaskUtils
 */
char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;

/**
 * task. h
 * @code{c}
 * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
 * @endcode
 *
 * NOTE:  This function takes a relatively long time to complete and should be
 * used sparingly.
 *
 * @return The handle of the task that has the human readable name pcNameToQuery.
 * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
 * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
 *
 * \defgroup pcTaskGetHandle pcTaskGetHandle
 * \ingroup TaskUtils
 */
#if ( INCLUDE_xTaskGetHandle == 1 )
    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
 *                                   StackType_t ** ppuxStackBuffer,
 *                                   StaticTask_t ** ppxTaskBuffer );
 * @endcode
 *
 * Retrieve pointers to a statically created task's data structure
 * buffer and stack buffer. These are the same buffers that are supplied
 * at the time of creation.
 *
 * @param xTask The task for which to retrieve the buffers.
 *
 * @param ppuxStackBuffer Used to return a pointer to the task's stack buffer.
 *
 * @param ppxTaskBuffer Used to return a pointer to the task's data structure
 * buffer.
 *
 * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.
 *
 * \defgroup xTaskGetStaticBuffers xTaskGetStaticBuffers
 * \ingroup TaskUtils
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
                                      StackType_t ** ppuxStackBuffer,
                                      StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * task.h
 * @code{c}
 * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
 * this function to be available.
 *
 * Returns the high water mark of the stack associated with xTask.  That is,
 * the minimum free stack space there has been (in words, so on a 32 bit machine
 * a value of 1 means 4 bytes) since the task started.  The smaller the returned
 * number the closer the task has come to overflowing its stack.
 *
 * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
 * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
 * user to determine the return type.  It gets around the problem of the value
 * overflowing on 8-bit types without breaking backward compatibility for
 * applications that expect an 8-bit return type.
 *
 * @param xTask Handle of the task associated with the stack to be checked.
 * Set xTask to NULL to check the stack of the calling task.
 *
 * @return The smallest amount of free stack space there has been (in words, so
 * actual spaces on the stack rather than bytes) since the task referenced by
 * xTask was created.
 */
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task.h
 * @code{c}
 * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
 * @endcode
 *
 * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
 * this function to be available.
 *
 * Returns the high water mark of the stack associated with xTask.  That is,
 * the minimum free stack space there has been (in words, so on a 32 bit machine
 * a value of 1 means 4 bytes) since the task started.  The smaller the returned
 * number the closer the task has come to overflowing its stack.
 *
 * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
 * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
 * user to determine the return type.  It gets around the problem of the value
 * overflowing on 8-bit types without breaking backward compatibility for
 * applications that expect an 8-bit return type.
 *
 * @param xTask Handle of the task associated with the stack to be checked.
 * Set xTask to NULL to check the stack of the calling task.
 *
 * @return The smallest amount of free stack space there has been (in words, so
 * actual spaces on the stack rather than bytes) since the task referenced by
 * xTask was created.
 */
#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/* When using trace macros it is sometimes necessary to include task.h before
 * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
 * so the following two prototypes will cause a compilation error.  This can be
 * fixed by simply guarding against the inclusion of these two prototypes unless
 * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
 * constant. */
#ifdef configUSE_APPLICATION_TASK_TAG
    #if configUSE_APPLICATION_TASK_TAG == 1

/**
 * task.h
 * @code{c}
 * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
 * @endcode
 *
 * Sets pxHookFunction to be the task hook function used by the task xTask.
 * Passing xTask as NULL has the effect of setting the calling tasks hook
 * function.
 */
        void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
                                         TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;

/**
 * task.h
 * @code{c}
 * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
 * @endcode
 *
 * Returns the pxHookFunction value assigned to the task xTask.  Do not
 * call from an interrupt service routine - call
 * xTaskGetApplicationTaskTagFromISR() instead.
 */
        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

/**
 * task.h
 * @code{c}
 * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
 * @endcode
 *
 * Returns the pxHookFunction value assigned to the task xTask.  Can
 * be called from an interrupt service routine.
 */
        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
    #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
#endif /* ifdef configUSE_APPLICATION_TASK_TAG */

#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )

/* Each task contains an array of pointers that is dimensioned by the
 * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
 * kernel does not use the pointers itself, so the application writer can use
 * the pointers for any purpose they wish.  The following two functions are
 * used to set and query a pointer respectively. */
    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
                                            BaseType_t xIndex,
                                            void * pvValue ) PRIVILEGED_FUNCTION;
    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
                                               BaseType_t xIndex ) PRIVILEGED_FUNCTION;

#endif

#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )

/**
 * task.h
 * @code{c}
 * void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName);
 * @endcode
 *
 * The application stack overflow hook is called when a stack overflow is detected for a task.
 *
 * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
 *
 * @param xTask the task that just exceeded its stack boundaries.
 * @param pcTaskName A character string containing the name of the offending task.
 */
    /* MISRA Ref 8.6.1 [External linkage] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
    /* coverity[misra_c_2012_rule_8_6_violation] */
    void vApplicationStackOverflowHook( TaskHandle_t xTask,
                                        char * pcTaskName );

#endif

#if ( configUSE_IDLE_HOOK == 1 )

/**
 * task.h
 * @code{c}
 * void vApplicationIdleHook( void );
 * @endcode
 *
 * The application idle hook is called by the idle task.
 * This allows the application designer to add background functionality without
 * the overhead of a separate task.
 * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
 */
    /* MISRA Ref 8.6.1 [External linkage] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
    /* coverity[misra_c_2012_rule_8_6_violation] */
    void vApplicationIdleHook( void );

#endif


#if  ( configUSE_TICK_HOOK != 0 )

/**
 *  task.h
 * @code{c}
 * void vApplicationTickHook( void );
 * @endcode
 *
 * This hook function is called in the system tick handler after any OS work is completed.
 */
    /* MISRA Ref 8.6.1 [External linkage] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
    /* coverity[misra_c_2012_rule_8_6_violation] */
    void vApplicationTickHook( void );

#endif

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

/**
 * task.h
 * @code{c}
 * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
 * @endcode
 *
 * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when
 * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
 *
 * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
 * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
 * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
 */
    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                        StackType_t ** ppxIdleTaskStackBuffer,
                                        configSTACK_DEPTH_TYPE * puxIdleTaskStackSize );

/**
 * task.h
 * @code{c}
 * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, BaseType_t xCoreID )
 * @endcode
 *
 * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB.  This function is required when
 * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
 *
 * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
 *  1. 1 Active idle task which does all the housekeeping.
 *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
 * These idle tasks are created to ensure that each core has an idle task to run when
 * no other task is available to run.
 *
 * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle
 * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle
 * tasks.
 *
 * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
 * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
 * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
 * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer
 */
    #if ( configNUMBER_OF_CORES > 1 )
        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                                   StackType_t ** ppxIdleTaskStackBuffer,
                                                   configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
                                                   BaseType_t xPassiveIdleTaskIndex );
    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */

/**
 * task.h
 * @code{c}
 * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
 * @endcode
 *
 * Calls the hook function associated with xTask.  Passing xTask as NULL has
 * the effect of calling the Running tasks (the calling task) hook function.
 *
 * pvParameter is passed to the hook function for the task to interpret as it
 * wants.  The return value is the value returned by the task hook function
 * registered by the user.
 */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
                                             void * pvParameter ) PRIVILEGED_FUNCTION;
#endif

/**
 * xTaskGetIdleTaskHandle() is only available if
 * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
 *
 * In single-core FreeRTOS, this function simply returns the handle of the idle
 * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler
 * has been started.
 *
 * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks:
 *  1. 1 Active idle task which does all the housekeeping.
 *  2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing.
 * These idle tasks are created to ensure that each core has an idle task to run when
 * no other task is available to run. Call xTaskGetIdleTaskHandle() or
 * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0  to get the Active
 * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to
 * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles.
 */
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
    #if ( configNUMBER_OF_CORES == 1 )
        TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */

/**
 * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
 * uxTaskGetSystemState() to be available.
 *
 * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
 * the system.  TaskStatus_t structures contain, among other things, members
 * for the task handle, task name, task priority, task state, and total amount
 * of run time consumed by the task.  See the TaskStatus_t structure
 * definition in this file for the full member list.
 *
 * NOTE:  This function is intended for debugging use only as its use results in
 * the scheduler remaining suspended for an extended period.
 *
 * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
 * The array must contain at least one TaskStatus_t structure for each task
 * that is under the control of the RTOS.  The number of tasks under the control
 * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
 *
 * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
 * parameter.  The size is specified as the number of indexes in the array, or
 * the number of TaskStatus_t structures contained in the array, not by the
 * number of bytes in the array.
 *
 * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
 * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
 * total run time (as defined by the run time stats clock, see
 * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted.
 * pulTotalRunTime can be set to NULL to omit the total run time information.
 *
 * @return The number of TaskStatus_t structures that were populated by
 * uxTaskGetSystemState().  This should equal the number returned by the
 * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
 * in the uxArraySize parameter was too small.
 *
 * Example usage:
 * @code{c}
 *  // This example demonstrates how a human readable table of run time stats
 *  // information is generated from raw data provided by uxTaskGetSystemState().
 *  // The human readable table is written to pcWriteBuffer
 *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
 *  {
 *  TaskStatus_t *pxTaskStatusArray;
 *  volatile UBaseType_t uxArraySize, x;
 *  configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage;
 *
 *      // Make sure the write buffer does not contain a string.
 * pcWriteBuffer = 0x00;
 *
 *      // Take a snapshot of the number of tasks in case it changes while this
 *      // function is executing.
 *      uxArraySize = uxTaskGetNumberOfTasks();
 *
 *      // Allocate a TaskStatus_t structure for each task.  An array could be
 *      // allocated statically at compile time.
 *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
 *
 *      if( pxTaskStatusArray != NULL )
 *      {
 *          // Generate raw status information about each task.
 *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
 *
 *          // For percentage calculations.
 *          ulTotalRunTime /= 100U;
 *
 *          // Avoid divide by zero errors.
 *          if( ulTotalRunTime > 0 )
 *          {
 *              // For each populated position in the pxTaskStatusArray array,
 *              // format the raw data as human readable ASCII data
 *              for( x = 0; x < uxArraySize; x++ )
 *              {
 *                  // What percentage of the total run time has the task used?
 *                  // This will always be rounded down to the nearest integer.
 *                  // ulTotalRunTimeDiv100 has already been divided by 100.
 *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
 *
 *                  if( ulStatsAsPercentage > 0U )
 *                  {
 *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
 *                  }
 *                  else
 *                  {
 *                      // If the percentage is zero here then the task has
 *                      // consumed less than 1% of the total run time.
 *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
 *                  }
 *
 *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
 *              }
 *          }
 *
 *          // The array is no longer needed, free the memory it consumes.
 *          vPortFree( pxTaskStatusArray );
 *      }
 *  }
 *  @endcode
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
                                      const UBaseType_t uxArraySize,
                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength );
 * @endcode
 *
 * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
 * both be defined as 1 for this function to be available.  See the
 * configuration section of the FreeRTOS.org website for more information.
 *
 * NOTE 1: This function will disable interrupts for its duration.  It is
 * not intended for normal application runtime use but as a debug aid.
 *
 * Lists all the current tasks, along with their current state and stack
 * usage high water mark.
 *
 * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
 * suspended ('S').
 *
 * PLEASE NOTE:
 *
 * This function is provided for convenience only, and is used by many of the
 * demo applications.  Do not consider it to be part of the scheduler.
 *
 * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
 * uxTaskGetSystemState() output into a human readable table that displays task:
 * names, states, priority, stack usage and task number.
 * Stack usage specified as the number of unused StackType_t words stack can hold
 * on top of stack - not the number of bytes.
 *
 * vTaskListTasks() has a dependency on the snprintf() C library function that might
 * bloat the code size, use a lot of stack, and provide different results on
 * different platforms.  An alternative, tiny, third party, and limited
 * functionality implementation of snprintf() is provided in many of the
 * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
 * printf-stdarg.c does not provide a full snprintf() implementation!).
 *
 * It is recommended that production systems call uxTaskGetSystemState()
 * directly to get access to raw stats data, rather than indirectly through a
 * call to vTaskListTasks().
 *
 * @param pcWriteBuffer A buffer into which the above mentioned details
 * will be written, in ASCII form.  This buffer is assumed to be large
 * enough to contain the generated report.  Approximately 40 bytes per
 * task should be sufficient.
 *
 * @param uxBufferLength Length of the pcWriteBuffer.
 *
 * \defgroup vTaskListTasks vTaskListTasks
 * \ingroup TaskUtils
 */
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
    void vTaskListTasks( char * pcWriteBuffer,
                         size_t uxBufferLength ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskList( char *pcWriteBuffer );
 * @endcode
 *
 * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
 * both be defined as 1 for this function to be available.  See the
 * configuration section of the FreeRTOS.org website for more information.
 *
 * WARN: This function assumes that the pcWriteBuffer is of length
 * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
 * backward compatibility. New applications are recommended to
 * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly.
 *
 * NOTE 1: This function will disable interrupts for its duration.  It is
 * not intended for normal application runtime use but as a debug aid.
 *
 * Lists all the current tasks, along with their current state and stack
 * usage high water mark.
 *
 * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
 * suspended ('S').
 *
 * PLEASE NOTE:
 *
 * This function is provided for convenience only, and is used by many of the
 * demo applications.  Do not consider it to be part of the scheduler.
 *
 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
 * uxTaskGetSystemState() output into a human readable table that displays task:
 * names, states, priority, stack usage and task number.
 * Stack usage specified as the number of unused StackType_t words stack can hold
 * on top of stack - not the number of bytes.
 *
 * vTaskList() has a dependency on the snprintf() C library function that might
 * bloat the code size, use a lot of stack, and provide different results on
 * different platforms.  An alternative, tiny, third party, and limited
 * functionality implementation of snprintf() is provided in many of the
 * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
 * printf-stdarg.c does not provide a full snprintf() implementation!).
 *
 * It is recommended that production systems call uxTaskGetSystemState()
 * directly to get access to raw stats data, rather than indirectly through a
 * call to vTaskList().
 *
 * @param pcWriteBuffer A buffer into which the above mentioned details
 * will be written, in ASCII form.  This buffer is assumed to be large
 * enough to contain the generated report.  Approximately 40 bytes per
 * task should be sufficient.
 *
 * \defgroup vTaskList vTaskList
 * \ingroup TaskUtils
 */
#define vTaskList( pcWriteBuffer )    vTaskListTasks( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )

/**
 * task. h
 * @code{c}
 * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength );
 * @endcode
 *
 * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
 * must both be defined as 1 for this function to be available.  The application
 * must also then provide definitions for
 * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
 * to configure a peripheral timer/counter and return the timers current count
 * value respectively.  The counter should be at least 10 times the frequency of
 * the tick count.
 *
 * NOTE 1: This function will disable interrupts for its duration.  It is
 * not intended for normal application runtime use but as a debug aid.
 *
 * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
 * accumulated execution time being stored for each task.  The resolution
 * of the accumulated time value depends on the frequency of the timer
 * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
 * Calling vTaskGetRunTimeStatistics() writes the total execution time of each
 * task into a buffer, both as an absolute count value and as a percentage
 * of the total system execution time.
 *
 * NOTE 2:
 *
 * This function is provided for convenience only, and is used by many of the
 * demo applications.  Do not consider it to be part of the scheduler.
 *
 * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of
 * the uxTaskGetSystemState() output into a human readable table that displays the
 * amount of time each task has spent in the Running state in both absolute and
 * percentage terms.
 *
 * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function
 * that might bloat the code size, use a lot of stack, and provide different
 * results on different platforms.  An alternative, tiny, third party, and
 * limited functionality implementation of snprintf() is provided in many of the
 * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
 * printf-stdarg.c does not provide a full snprintf() implementation!).
 *
 * It is recommended that production systems call uxTaskGetSystemState() directly
 * to get access to raw stats data, rather than indirectly through a call to
 * vTaskGetRunTimeStatistics().
 *
 * @param pcWriteBuffer A buffer into which the execution times will be
 * written, in ASCII form.  This buffer is assumed to be large enough to
 * contain the generated report.  Approximately 40 bytes per task should
 * be sufficient.
 *
 * @param uxBufferLength Length of the pcWriteBuffer.
 *
 * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics
 * \ingroup TaskUtils
 */
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )
    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
                                    size_t uxBufferLength ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * void vTaskGetRunTimeStats( char *pcWriteBuffer );
 * @endcode
 *
 * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
 * must both be defined as 1 for this function to be available.  The application
 * must also then provide definitions for
 * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
 * to configure a peripheral timer/counter and return the timers current count
 * value respectively.  The counter should be at least 10 times the frequency of
 * the tick count.
 *
 * WARN: This function assumes that the pcWriteBuffer is of length
 * configSTATS_BUFFER_MAX_LENGTH. This function is there only for
 * backward compatiblity. New applications are recommended to use
 * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer
 * explicitly.
 *
 * NOTE 1: This function will disable interrupts for its duration.  It is
 * not intended for normal application runtime use but as a debug aid.
 *
 * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
 * accumulated execution time being stored for each task.  The resolution
 * of the accumulated time value depends on the frequency of the timer
 * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
 * Calling vTaskGetRunTimeStats() writes the total execution time of each
 * task into a buffer, both as an absolute count value and as a percentage
 * of the total system execution time.
 *
 * NOTE 2:
 *
 * This function is provided for convenience only, and is used by many of the
 * demo applications.  Do not consider it to be part of the scheduler.
 *
 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
 * uxTaskGetSystemState() output into a human readable table that displays the
 * amount of time each task has spent in the Running state in both absolute and
 * percentage terms.
 *
 * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function
 * that might bloat the code size, use a lot of stack, and provide different
 * results on different platforms.  An alternative, tiny, third party, and
 * limited functionality implementation of snprintf() is provided in many of the
 * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
 * printf-stdarg.c does not provide a full snprintf() implementation!).
 *
 * It is recommended that production systems call uxTaskGetSystemState() directly
 * to get access to raw stats data, rather than indirectly through a call to
 * vTaskGetRunTimeStats().
 *
 * @param pcWriteBuffer A buffer into which the execution times will be
 * written, in ASCII form.  This buffer is assumed to be large enough to
 * contain the generated report.  Approximately 40 bytes per task should
 * be sufficient.
 *
 * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
 * \ingroup TaskUtils
 */
#define vTaskGetRunTimeStats( pcWriteBuffer )    vTaskGetRunTimeStatistics( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH )

/**
 * task. h
 * @code{c}
 * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask );
 * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask );
 * @endcode
 *
 * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be
 * available.  The application must also then provide definitions for
 * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
 * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and
 * return the timers current count value respectively.  The counter should be
 * at least 10 times the frequency of the tick count.
 *
 * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
 * accumulated execution time being stored for each task.  The resolution
 * of the accumulated time value depends on the frequency of the timer
 * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
 * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
 * execution time of each task into a buffer, ulTaskGetRunTimeCounter()
 * returns the total execution time of just one task and
 * ulTaskGetRunTimePercent() returns the percentage of the CPU time used by
 * just one task.
 *
 * @return The total run time of the given task or the percentage of the total
 * run time consumed by the given task.  This is the amount of time the task
 * has actually been executing.  The unit of time is dependent on the frequency
 * configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
 * portGET_RUN_TIME_COUNTER_VALUE() macros.
 *
 * \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter
 * \ingroup TaskUtils
 */
#if ( configGENERATE_RUN_TIME_STATS == 1 )
    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void );
 * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void );
 * @endcode
 *
 * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be
 * available.  The application must also then provide definitions for
 * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
 * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and
 * return the timers current count value respectively.  The counter should be
 * at least 10 times the frequency of the tick count.
 *
 * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
 * accumulated execution time being stored for each task.  The resolution
 * of the accumulated time value depends on the frequency of the timer
 * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
 * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
 * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
 * returns the total execution time of just the idle task and
 * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by
 * just the idle task.
 *
 * Note the amount of idle time is only a good measure of the slack time in a
 * system if there are no other tasks executing at the idle priority, tickless
 * idle is not used, and configIDLE_SHOULD_YIELD is set to 0.
 *
 * @return The total run time of the idle task or the percentage of the total
 * run time consumed by the idle task.  This is the amount of time the
 * idle task has actually been executing.  The unit of time is dependent on the
 * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
 * portGET_RUN_TIME_COUNTER_VALUE() macros.
 *
 * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
 * \ingroup TaskUtils
 */
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION;
#endif

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );
 * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
 * functions to be available.
 *
 * Sends a direct to task notification to a task, with an optional value and
 * action.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to
 * [optionally] block to wait for a notification to be pending.  The task does
 * not consume any CPU time while it is in the Blocked state.
 *
 * A notification sent to a task will remain pending until it is cleared by the
 * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
 * un-indexed equivalents).  If the task was already in the Blocked state to
 * wait for a notification when the notification arrives then the task will
 * automatically be removed from the Blocked state (unblocked) and the
 * notification cleared.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotify() is the original API function, and remains backward
 * compatible by always operating on the notification value at index 0 in the
 * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed()
 * with the uxIndexToNotify parameter set to 0.
 *
 * @param xTaskToNotify The handle of the task being notified.  The handle to a
 * task can be returned from the xTaskCreate() API function used to create the
 * task, and the handle of the currently running task can be obtained by calling
 * xTaskGetCurrentTaskHandle().
 *
 * @param uxIndexToNotify The index within the target task's array of
 * notification values to which the notification is to be sent.  uxIndexToNotify
 * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotify() does
 * not have this parameter and always sends notifications to index 0.
 *
 * @param ulValue Data that can be sent with the notification.  How the data is
 * used depends on the value of the eAction parameter.
 *
 * @param eAction Specifies how the notification updates the task's notification
 * value, if at all.  Valid values for eAction are as follows:
 *
 * eSetBits -
 * The target notification value is bitwise ORed with ulValue.
 * xTaskNotifyIndexed() always returns pdPASS in this case.
 *
 * eIncrement -
 * The target notification value is incremented.  ulValue is not used and
 * xTaskNotifyIndexed() always returns pdPASS in this case.
 *
 * eSetValueWithOverwrite -
 * The target notification value is set to the value of ulValue, even if the
 * task being notified had not yet processed the previous notification at the
 * same array index (the task already had a notification pending at that index).
 * xTaskNotifyIndexed() always returns pdPASS in this case.
 *
 * eSetValueWithoutOverwrite -
 * If the task being notified did not already have a notification pending at the
 * same array index then the target notification value is set to ulValue and
 * xTaskNotifyIndexed() will return pdPASS.  If the task being notified already
 * had a notification pending at the same array index then no action is
 * performed and pdFAIL is returned.
 *
 * eNoAction -
 * The task receives a notification at the specified array index without the
 * notification value at that index being updated.  ulValue is not used and
 * xTaskNotifyIndexed() always returns pdPASS in this case.
 *
 * pulPreviousNotificationValue -
 * Can be used to pass out the subject task's notification value before any
 * bits are modified by the notify function.
 *
 * @return Dependent on the value of eAction.  See the description of the
 * eAction parameter.
 *
 * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed
 * \ingroup TaskNotifications
 */
BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
                               UBaseType_t uxIndexToNotify,
                               uint32_t ulValue,
                               eNotifyAction eAction,
                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )
#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
 * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * xTaskNotifyAndQueryIndexed() performs the same operation as
 * xTaskNotifyIndexed() with the addition that it also returns the subject
 * task's prior notification value (the notification value at the time the
 * function is called rather than when the function returns) in the additional
 * pulPreviousNotifyValue parameter.
 *
 * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the
 * addition that it also returns the subject task's prior notification value
 * (the notification value as it was at the time the function is called, rather
 * than when the function returns) in the additional pulPreviousNotifyValue
 * parameter.
 *
 * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed
 * \ingroup TaskNotifications
 */
#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
 * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
 * functions to be available.
 *
 * A version of xTaskNotifyIndexed() that can be used from an interrupt service
 * routine (ISR).
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
 * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
 * to wait for a notification value to have a non-zero value.  The task does
 * not consume any CPU time while it is in the Blocked state.
 *
 * A notification sent to a task will remain pending until it is cleared by the
 * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
 * un-indexed equivalents).  If the task was already in the Blocked state to
 * wait for a notification when the notification arrives then the task will
 * automatically be removed from the Blocked state (unblocked) and the
 * notification cleared.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotifyFromISR() is the original API function, and remains
 * backward compatible by always operating on the notification value at index 0
 * within the array. Calling xTaskNotifyFromISR() is equivalent to calling
 * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0.
 *
 * @param uxIndexToNotify The index within the target task's array of
 * notification values to which the notification is to be sent.  uxIndexToNotify
 * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyFromISR()
 * does not have this parameter and always sends notifications to index 0.
 *
 * @param xTaskToNotify The handle of the task being notified.  The handle to a
 * task can be returned from the xTaskCreate() API function used to create the
 * task, and the handle of the currently running task can be obtained by calling
 * xTaskGetCurrentTaskHandle().
 *
 * @param ulValue Data that can be sent with the notification.  How the data is
 * used depends on the value of the eAction parameter.
 *
 * @param eAction Specifies how the notification updates the task's notification
 * value, if at all.  Valid values for eAction are as follows:
 *
 * eSetBits -
 * The task's notification value is bitwise ORed with ulValue.  xTaskNotify()
 * always returns pdPASS in this case.
 *
 * eIncrement -
 * The task's notification value is incremented.  ulValue is not used and
 * xTaskNotify() always returns pdPASS in this case.
 *
 * eSetValueWithOverwrite -
 * The task's notification value is set to the value of ulValue, even if the
 * task being notified had not yet processed the previous notification (the
 * task already had a notification pending).  xTaskNotify() always returns
 * pdPASS in this case.
 *
 * eSetValueWithoutOverwrite -
 * If the task being notified did not already have a notification pending then
 * the task's notification value is set to ulValue and xTaskNotify() will
 * return pdPASS.  If the task being notified already had a notification
 * pending then no action is performed and pdFAIL is returned.
 *
 * eNoAction -
 * The task receives a notification without its notification value being
 * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
 * this case.
 *
 * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
 * task to which the notification was sent to leave the Blocked state, and the
 * unblocked task has a priority higher than the currently running task.  If
 * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
 * be requested before the interrupt is exited.  How a context switch is
 * requested from an ISR is dependent on the port - see the documentation page
 * for the port in use.
 *
 * @return Dependent on the value of eAction.  See the description of the
 * eAction parameter.
 *
 * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR
 * \ingroup TaskNotifications
 */
BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
                                      UBaseType_t uxIndexToNotify,
                                      uint32_t ulValue,
                                      eNotifyAction eAction,
                                      uint32_t * pulPreviousNotificationValue,
                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
 * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as
 * xTaskNotifyIndexedFromISR() with the addition that it also returns the
 * subject task's prior notification value (the notification value at the time
 * the function is called rather than at the time the function returns) in the
 * additional pulPreviousNotifyValue parameter.
 *
 * xTaskNotifyAndQueryFromISR() performs the same operation as
 * xTaskNotifyFromISR() with the addition that it also returns the subject
 * task's prior notification value (the notification value at the time the
 * function is called rather than at the time the function returns) in the
 * additional pulPreviousNotifyValue parameter.
 *
 * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR
 * \ingroup TaskNotifications
 */
#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
 *
 * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
 * @endcode
 *
 * Waits for a direct to task notification to be pending at a given index within
 * an array of direct to task notifications.
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
 * function to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * A notification sent to a task will remain pending until it is cleared by the
 * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
 * un-indexed equivalents).  If the task was already in the Blocked state to
 * wait for a notification when the notification arrives then the task will
 * automatically be removed from the Blocked state (unblocked) and the
 * notification cleared.
 *
 * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
 * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
 * to wait for a notification value to have a non-zero value.  The task does
 * not consume any CPU time while it is in the Blocked state.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotifyWait() is the original API function, and remains backward
 * compatible by always operating on the notification value at index 0 in the
 * array. Calling xTaskNotifyWait() is equivalent to calling
 * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0.
 *
 * @param uxIndexToWaitOn The index within the calling task's array of
 * notification values on which the calling task will wait for a notification to
 * be received.  uxIndexToWaitOn must be less than
 * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyWait() does
 * not have this parameter and always waits for notifications on index 0.
 *
 * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
 * will be cleared in the calling task's notification value before the task
 * checks to see if any notifications are pending, and optionally blocks if no
 * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
 * limits.h is included) or 0xffffffffU (if limits.h is not included) will have
 * the effect of resetting the task's notification value to 0.  Setting
 * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
 *
 * @param ulBitsToClearOnExit If a notification is pending or received before
 * the calling task exits the xTaskNotifyWait() function then the task's
 * notification value (see the xTaskNotify() API function) is passed out using
 * the pulNotificationValue parameter.  Then any bits that are set in
 * ulBitsToClearOnExit will be cleared in the task's notification value (note
 * *pulNotificationValue is set before any bits are cleared).  Setting
 * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
 * (if limits.h is not included) will have the effect of resetting the task's
 * notification value to 0 before the function exits.  Setting
 * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
 * when the function exits (in which case the value passed out in
 * pulNotificationValue will match the task's notification value).
 *
 * @param pulNotificationValue Used to pass the task's notification value out
 * of the function.  Note the value passed out will not be effected by the
 * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
 *
 * @param xTicksToWait The maximum amount of time that the task should wait in
 * the Blocked state for a notification to be received, should a notification
 * not already be pending when xTaskNotifyWait() was called.  The task
 * will not consume any processing time while it is in the Blocked state.  This
 * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be
 * used to convert a time specified in milliseconds to a time specified in
 * ticks.
 *
 * @return If a notification was received (including notifications that were
 * already pending when xTaskNotifyWait was called) then pdPASS is
 * returned.  Otherwise pdFAIL is returned.
 *
 * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed
 * \ingroup TaskNotifications
 */
BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                   uint32_t ulBitsToClearOnEntry,
                                   uint32_t ulBitsToClearOnExit,
                                   uint32_t * pulNotificationValue,
                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
    xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
    xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );
 * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
 * @endcode
 *
 * Sends a direct to task notification to a particular index in the target
 * task's notification array in a manner similar to giving a counting semaphore.
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
 * macros to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * xTaskNotifyGiveIndexed() is a helper macro intended for use when task
 * notifications are used as light weight and faster binary or counting
 * semaphore equivalents.  Actual FreeRTOS semaphores are given using the
 * xSemaphoreGive() API function, the equivalent action that instead uses a task
 * notification is xTaskNotifyGiveIndexed().
 *
 * When task notifications are being used as a binary or counting semaphore
 * equivalent then the task being notified should wait for the notification
 * using the ulTaskNotifyTakeIndexed() API function rather than the
 * xTaskNotifyWaitIndexed() API function.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotifyGive() is the original API function, and remains backward
 * compatible by always operating on the notification value at index 0 in the
 * array. Calling xTaskNotifyGive() is equivalent to calling
 * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0.
 *
 * @param xTaskToNotify The handle of the task being notified.  The handle to a
 * task can be returned from the xTaskCreate() API function used to create the
 * task, and the handle of the currently running task can be obtained by calling
 * xTaskGetCurrentTaskHandle().
 *
 * @param uxIndexToNotify The index within the target task's array of
 * notification values to which the notification is to be sent.  uxIndexToNotify
 * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyGive()
 * does not have this parameter and always sends notifications to index 0.
 *
 * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
 * eAction parameter set to eIncrement - so pdPASS is always returned.
 *
 * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed
 * \ingroup TaskNotifications
 */
#define xTaskNotifyGive( xTaskToNotify ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )
#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \
    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )

/**
 * task. h
 * @code{c}
 * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );
 * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
 * @endcode
 *
 * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt
 * service routine (ISR).
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
 * to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications
 * are used as light weight and faster binary or counting semaphore equivalents.
 * Actual FreeRTOS semaphores are given from an ISR using the
 * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
 * a task notification is vTaskNotifyGiveIndexedFromISR().
 *
 * When task notifications are being used as a binary or counting semaphore
 * equivalent then the task being notified should wait for the notification
 * using the ulTaskNotifyTakeIndexed() API function rather than the
 * xTaskNotifyWaitIndexed() API function.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotifyFromISR() is the original API function, and remains
 * backward compatible by always operating on the notification value at index 0
 * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling
 * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0.
 *
 * @param xTaskToNotify The handle of the task being notified.  The handle to a
 * task can be returned from the xTaskCreate() API function used to create the
 * task, and the handle of the currently running task can be obtained by calling
 * xTaskGetCurrentTaskHandle().
 *
 * @param uxIndexToNotify The index within the target task's array of
 * notification values to which the notification is to be sent.  uxIndexToNotify
 * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
 * xTaskNotifyGiveFromISR() does not have this parameter and always sends
 * notifications to index 0.
 *
 * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
 * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
 * task to which the notification was sent to leave the Blocked state, and the
 * unblocked task has a priority higher than the currently running task.  If
 * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
 * should be requested before the interrupt is exited.  How a context switch is
 * requested from an ISR is dependent on the port - see the documentation page
 * for the port in use.
 *
 * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR
 * \ingroup TaskNotifications
 */
void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
                                    UBaseType_t uxIndexToNotify,
                                    BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \
    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )
#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \
    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )

/**
 * task. h
 * @code{c}
 * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
 *
 * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
 * @endcode
 *
 * Waits for a direct to task notification on a particular index in the calling
 * task's notification array in a manner similar to taking a counting semaphore.
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
 * function to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * Events can be sent to a task using an intermediary object.  Examples of such
 * objects are queues, semaphores, mutexes and event groups.  Task notifications
 * are a method of sending an event directly to a task without the need for such
 * an intermediary object.
 *
 * A notification sent to a task can optionally perform an action, such as
 * update, overwrite or increment one of the task's notification values.  In
 * that way task notifications can be used to send data to a task, or be used as
 * light weight and fast binary or counting semaphores.
 *
 * ulTaskNotifyTakeIndexed() is intended for use when a task notification is
 * used as a faster and lighter weight binary or counting semaphore alternative.
 * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function,
 * the equivalent action that instead uses a task notification is
 * ulTaskNotifyTakeIndexed().
 *
 * When a task is using its notification value as a binary or counting semaphore
 * other tasks should send notifications to it using the xTaskNotifyGiveIndexed()
 * macro, or xTaskNotifyIndex() function with the eAction parameter set to
 * eIncrement.
 *
 * ulTaskNotifyTakeIndexed() can either clear the task's notification value at
 * the array index specified by the uxIndexToWaitOn parameter to zero on exit,
 * in which case the notification value acts like a binary semaphore, or
 * decrement the notification value on exit, in which case the notification
 * value acts like a counting semaphore.
 *
 * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for
 * a notification.  The task does not consume any CPU time while it is in the
 * Blocked state.
 *
 * Where as xTaskNotifyWaitIndexed() will return when a notification is pending,
 * ulTaskNotifyTakeIndexed() will return when the task's notification value is
 * not zero.
 *
 * **NOTE** Each notification within the array operates independently - a task
 * can only block on one notification within the array at a time and will not be
 * unblocked by a notification sent to any other array index.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  ulTaskNotifyTake() is the original API function, and remains backward
 * compatible by always operating on the notification value at index 0 in the
 * array. Calling ulTaskNotifyTake() is equivalent to calling
 * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0.
 *
 * @param uxIndexToWaitOn The index within the calling task's array of
 * notification values on which the calling task will wait for a notification to
 * be non-zero.  uxIndexToWaitOn must be less than
 * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyTake() does
 * not have this parameter and always waits for notifications on index 0.
 *
 * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
 * notification value is decremented when the function exits.  In this way the
 * notification value acts like a counting semaphore.  If xClearCountOnExit is
 * not pdFALSE then the task's notification value is cleared to zero when the
 * function exits.  In this way the notification value acts like a binary
 * semaphore.
 *
 * @param xTicksToWait The maximum amount of time that the task should wait in
 * the Blocked state for the task's notification value to be greater than zero,
 * should the count not already be greater than zero when
 * ulTaskNotifyTake() was called.  The task will not consume any processing
 * time while it is in the Blocked state.  This is specified in kernel ticks,
 * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time
 * specified in milliseconds to a time specified in ticks.
 *
 * @return The task's notification count before it is either cleared to zero or
 * decremented (see the xClearCountOnExit parameter).
 *
 * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed
 * \ingroup TaskNotifications
 */
uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                  BaseType_t xClearCountOnExit,
                                  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \
    ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )
#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \
    ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )

/**
 * task. h
 * @code{c}
 * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
 *
 * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
 * functions to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * If a notification is sent to an index within the array of notifications then
 * the notification at that index is said to be 'pending' until it is read or
 * explicitly cleared by the receiving task.  xTaskNotifyStateClearIndexed()
 * is the function that clears a pending notification without reading the
 * notification value.  The notification value at the same array index is not
 * altered.  Set xTask to NULL to clear the notification state of the calling
 * task.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  xTaskNotifyStateClear() is the original API function, and remains
 * backward compatible by always operating on the notification value at index 0
 * within the array. Calling xTaskNotifyStateClear() is equivalent to calling
 * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0.
 *
 * @param xTask The handle of the RTOS task that will have a notification state
 * cleared.  Set xTask to NULL to clear a notification state in the calling
 * task.  To obtain a task's handle create the task using xTaskCreate() and
 * make use of the pxCreatedTask parameter, or create the task using
 * xTaskCreateStatic() and store the returned value, or use the task's name in
 * a call to xTaskGetHandle().
 *
 * @param uxIndexToClear The index within the target task's array of
 * notification values to act upon.  For example, setting uxIndexToClear to 1
 * will clear the state of the notification at index 1 within the array.
 * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
 * ulTaskNotifyStateClear() does not have this parameter and always acts on the
 * notification at index 0.
 *
 * @return pdTRUE if the task's notification state was set to
 * eNotWaitingNotification, otherwise pdFALSE.
 *
 * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed
 * \ingroup TaskNotifications
 */
BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
                                         UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION;
#define xTaskNotifyStateClear( xTask ) \
    xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )
#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \
    xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )

/**
 * task. h
 * @code{c}
 * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
 *
 * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
 * @endcode
 *
 * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
 *
 * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
 * functions to be available.
 *
 * Each task has a private array of "notification values" (or 'notifications'),
 * each of which is a 32-bit unsigned integer (uint32_t).  The constant
 * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
 * array, and (for backward compatibility) defaults to 1 if left undefined.
 * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
 *
 * ulTaskNotifyValueClearIndexed() clears the bits specified by the
 * ulBitsToClear bit mask in the notification value at array index uxIndexToClear
 * of the task referenced by xTask.
 *
 * Backward compatibility information:
 * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
 * all task notification API functions operated on that value. Replacing the
 * single notification value with an array of notification values necessitated a
 * new set of API functions that could address specific notifications within the
 * array.  ulTaskNotifyValueClear() is the original API function, and remains
 * backward compatible by always operating on the notification value at index 0
 * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling
 * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0.
 *
 * @param xTask The handle of the RTOS task that will have bits in one of its
 * notification values cleared. Set xTask to NULL to clear bits in a
 * notification value of the calling task.  To obtain a task's handle create the
 * task using xTaskCreate() and make use of the pxCreatedTask parameter, or
 * create the task using xTaskCreateStatic() and store the returned value, or
 * use the task's name in a call to xTaskGetHandle().
 *
 * @param uxIndexToClear The index within the target task's array of
 * notification values in which to clear the bits.  uxIndexToClear
 * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
 * ulTaskNotifyValueClear() does not have this parameter and always clears bits
 * in the notification value at index 0.
 *
 * @param ulBitsToClear Bit mask of the bits to clear in the notification value of
 * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification
 * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
 * the notification value to 0.  Set ulBitsToClear to 0 to query the task's
 * notification value without clearing any bits.
 *
 *
 * @return The value of the target task's notification value before the bits
 * specified by ulBitsToClear were cleared.
 * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
 * \ingroup TaskNotifications
 */
uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
                                        UBaseType_t uxIndexToClear,
                                        uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \
    ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )
#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \
    ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )

/**
 * task.h
 * @code{c}
 * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
 * @endcode
 *
 * Capture the current time for future use with xTaskCheckForTimeOut().
 *
 * @param pxTimeOut Pointer to a timeout object into which the current time
 * is to be captured.  The captured time includes the tick count and the number
 * of times the tick count has overflowed since the system first booted.
 * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
 * \ingroup TaskCtrl
 */
void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;

/**
 * task.h
 * @code{c}
 * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
 * @endcode
 *
 * Determines if pxTicksToWait ticks has passed since a time was captured
 * using a call to vTaskSetTimeOutState().  The captured time includes the tick
 * count and the number of times the tick count has overflowed.
 *
 * @param pxTimeOut The time status as captured previously using
 * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
 * to reflect the current time status.
 * @param pxTicksToWait The number of ticks to check for timeout i.e. if
 * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
 * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
 * If the timeout has not occurred, pxTicksToWait is updated to reflect the
 * number of remaining ticks.
 *
 * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
 * returned and pxTicksToWait is updated to reflect the number of remaining
 * ticks.
 *
 * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html
 *
 * Example Usage:
 * @code{c}
 *  // Driver library function used to receive uxWantedBytes from an Rx buffer
 *  // that is filled by a UART interrupt. If there are not enough bytes in the
 *  // Rx buffer then the task enters the Blocked state until it is notified that
 *  // more data has been placed into the buffer. If there is still not enough
 *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
 *  // is used to re-calculate the Block time to ensure the total amount of time
 *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
 *  // continues until either the buffer contains at least uxWantedBytes bytes,
 *  // or the total amount of time spent in the Blocked state reaches
 *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are
 *  // available up to a maximum of uxWantedBytes.
 *
 *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
 *  {
 *  size_t uxReceived = 0;
 *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
 *  TimeOut_t xTimeOut;
 *
 *      // Initialize xTimeOut.  This records the time at which this function
 *      // was entered.
 *      vTaskSetTimeOutState( &xTimeOut );
 *
 *      // Loop until the buffer contains the wanted number of bytes, or a
 *      // timeout occurs.
 *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
 *      {
 *          // The buffer didn't contain enough data so this task is going to
 *          // enter the Blocked state. Adjusting xTicksToWait to account for
 *          // any time that has been spent in the Blocked state within this
 *          // function so far to ensure the total amount of time spent in the
 *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
 *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
 *          {
 *              //Timed out before the wanted number of bytes were available,
 *              // exit the loop.
 *              break;
 *          }
 *
 *          // Wait for a maximum of xTicksToWait ticks to be notified that the
 *          // receive interrupt has placed more data into the buffer.
 *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
 *      }
 *
 *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
 *      // The actual number of bytes read (which might be less than
 *      // uxWantedBytes) is returned.
 *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
 *                                                  pucBuffer,
 *                                                  uxWantedBytes );
 *
 *      return uxReceived;
 *  }
 * @endcode
 * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
 * \ingroup TaskCtrl
 */
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
                                 TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;

/**
 * task.h
 * @code{c}
 * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
 * @endcode
 *
 * This function corrects the tick count value after the application code has held
 * interrupts disabled for an extended period resulting in tick interrupts having
 * been missed.
 *
 * This function is similar to vTaskStepTick(), however, unlike
 * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
 * time at which a task should be removed from the blocked state.  That means
 * tasks may have to be removed from the blocked state as the tick count is
 * moved.
 *
 * @param xTicksToCatchUp The number of tick interrupts that have been missed due to
 * interrupts being disabled.  Its value is not computed automatically, so must be
 * computed by the application writer.
 *
 * @return pdTRUE if moving the tick count forward resulted in a task leaving the
 * blocked state and a context switch being performed.  Otherwise pdFALSE.
 *
 * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks
 * \ingroup TaskCtrl
 */
BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;

/**
 * task.h
 * @code{c}
 * void vTaskResetState( void );
 * @endcode
 *
 * This function resets the internal state of the task. It must be called by the
 * application before restarting the scheduler.
 *
 * \defgroup vTaskResetState vTaskResetState
 * \ingroup SchedulerControl
 */
void vTaskResetState( void ) PRIVILEGED_FUNCTION;


/*-----------------------------------------------------------
* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
*----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES == 1 )
    #define taskYIELD_WITHIN_API()    portYIELD_WITHIN_API()
#else /* #if ( configNUMBER_OF_CORES == 1 ) */
    #define taskYIELD_WITHIN_API()    vTaskYieldWithinAPI()
#endif /* #if ( configNUMBER_OF_CORES == 1 ) */

/*
 * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
 * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
 * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
 *
 * Called from the real time kernel tick (either preemptive or cooperative),
 * this increments the tick count and checks if any tasks that are blocked
 * for a finite period required removing from a blocked list and placing on
 * a ready list.  If a non-zero value is returned then a context switch is
 * required because either:
 *   + A task was removed from a blocked list because its timeout had expired,
 *     or
 *   + Time slicing is in use and there is a task of equal priority to the
 *     currently running task.
 */
BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;

/*
 * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
 * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
 *
 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
 *
 * Removes the calling task from the ready list and places it both
 * on the list of tasks waiting for a particular event, and the
 * list of delayed tasks.  The task will be removed from both lists
 * and replaced on the ready list should either the event occur (and
 * there be no higher priority tasks waiting on the same event) or
 * the delay period expires.
 *
 * The 'unordered' version replaces the event list item value with the
 * xItemValue value, and inserts the list item at the end of the list.
 *
 * The 'ordered' version uses the existing event list item value (which is the
 * owning task's priority) to insert the list item into the event list in task
 * priority order.
 *
 * @param pxEventList The list containing tasks that are blocked waiting
 * for the event to occur.
 *
 * @param xItemValue The item value to use for the event list item when the
 * event list is not ordered by task priority.
 *
 * @param xTicksToWait The maximum amount of time that the task should wait
 * for the event to occur.  This is specified in kernel ticks, the constant
 * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
 * period.
 */
void vTaskPlaceOnEventList( List_t * const pxEventList,
                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
                                     const TickType_t xItemValue,
                                     const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

/*
 * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
 * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
 *
 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
 *
 * This function performs nearly the same function as vTaskPlaceOnEventList().
 * The difference being that this function does not permit tasks to block
 * indefinitely, whereas vTaskPlaceOnEventList() does.
 *
 */
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
                                      TickType_t xTicksToWait,
                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;

/*
 * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
 * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
 *
 * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
 *
 * Removes a task from both the specified event list and the list of blocked
 * tasks, and places it on a ready queue.
 *
 * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
 * if either an event occurs to unblock a task, or the block timeout period
 * expires.
 *
 * xTaskRemoveFromEventList() is used when the event list is in task priority
 * order.  It removes the list item from the head of the event list as that will
 * have the highest priority owning task of all the tasks on the event list.
 * vTaskRemoveFromUnorderedEventList() is used when the event list is not
 * ordered and the event list items hold something other than the owning tasks
 * priority.  In this case the event list item value is updated to the value
 * passed in the xItemValue parameter.
 *
 * @return pdTRUE if the task being removed has a higher priority than the task
 * making the call, otherwise pdFALSE.
 */
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
                                        const TickType_t xItemValue ) PRIVILEGED_FUNCTION;

/*
 * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
 * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
 * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
 *
 * Sets the pointer to the current TCB to the TCB of the highest priority task
 * that is ready to run.
 */
#if ( configNUMBER_OF_CORES == 1 )
    portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
#else
    portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;
#endif

/*
 * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
 * THE EVENT BITS MODULE.
 */
TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;

/*
 * Return the handle of the calling task.
 */
TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;

/*
 * Return the handle of the task running on specified core.
 */
TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION;

/*
 * Shortcut used by the queue implementation to prevent unnecessary call to
 * taskYIELD();
 */
void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;

/*
 * Returns the scheduler state as taskSCHEDULER_RUNNING,
 * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
 */
BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;

/*
 * Raises the priority of the mutex holder to that of the calling task should
 * the mutex holder have a priority less than the calling task.
 */
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;

/*
 * Set the priority of a task back to its proper priority in the case that it
 * inherited a higher priority while it was holding a semaphore.
 */
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;

/*
 * If a higher priority task attempting to obtain a mutex caused a lower
 * priority task to inherit the higher priority task's priority - but the higher
 * priority task then timed out without obtaining the mutex, then the lower
 * priority task will disinherit the priority again - but only down as far as
 * the highest priority task that is still waiting for the mutex (if there were
 * more than one task waiting for the mutex).
 */
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
                                          UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;

/*
 * Get the uxTaskNumber assigned to the task referenced by the xTask parameter.
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif

/*
 * Set the uxTaskNumber of the task referenced by the xTask parameter to
 * uxHandle.
 */
#if ( configUSE_TRACE_FACILITY == 1 )
    void vTaskSetTaskNumber( TaskHandle_t xTask,
                             const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
#endif

/*
 * Only available when configUSE_TICKLESS_IDLE is set to 1.
 * If tickless mode is being used, or a low power mode is implemented, then
 * the tick interrupt will not execute during idle periods.  When this is the
 * case, the tick count value maintained by the scheduler needs to be kept up
 * to date with the actual execution time by being skipped forward by a time
 * equal to the idle period.
 */
#if ( configUSE_TICKLESS_IDLE != 0 )
    void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
#endif

/*
 * Only available when configUSE_TICKLESS_IDLE is set to 1.
 * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
 * specific sleep function to determine if it is ok to proceed with the sleep,
 * and if it is ok to proceed, if it is ok to sleep indefinitely.
 *
 * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
 * called with the scheduler suspended, not from within a critical section.  It
 * is therefore possible for an interrupt to request a context switch between
 * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
 * entered.  eTaskConfirmSleepModeStatus() should be called from a short
 * critical section between the timer being stopped and the sleep mode being
 * entered to ensure it is ok to proceed into the sleep mode.
 */
#if ( configUSE_TICKLESS_IDLE != 0 )
    eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
#endif

/*
 * For internal use only.  Increment the mutex held count when a mutex is
 * taken and return the handle of the task that has taken the mutex.
 */
TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;

/*
 * For internal use only.  Same as vTaskSetTimeOutState(), but without a critical
 * section.
 */
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;

/*
 * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS.
 * For SMP this is not defined by the port.
 */
#if ( configNUMBER_OF_CORES > 1 )
    void vTaskYieldWithinAPI( void );
#endif

/*
 * This function is only intended for use when implementing a port of the scheduler
 * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
 * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL
 * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
 * It should be used in the implementation of portENTER_CRITICAL if port is running a
 * multiple core FreeRTOS.
 */
#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
    void vTaskEnterCritical( void );
#endif

/*
 * This function is only intended for use when implementing a port of the scheduler
 * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES
 * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL
 * if port wants to maintain critical nesting count in TCB in single core FreeRTOS.
 * It should be used in the implementation of portEXIT_CRITICAL if port is running a
 * multiple core FreeRTOS.
 */
#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) )
    void vTaskExitCritical( void );
#endif

/*
 * This function is only intended for use when implementing a port of the scheduler
 * and is only available when configNUMBER_OF_CORES is greater than 1. This function
 * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is
 * running a multiple core FreeRTOS.
 */
#if ( configNUMBER_OF_CORES > 1 )
    UBaseType_t vTaskEnterCriticalFromISR( void );
#endif

/*
 * This function is only intended for use when implementing a port of the scheduler
 * and is only available when configNUMBER_OF_CORES is greater than 1. This function
 * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is
 * running a multiple core FreeRTOS.
 */
#if ( configNUMBER_OF_CORES > 1 )
    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
#endif

#if ( portUSING_MPU_WRAPPERS == 1 )

/*
 * For internal use only.  Get MPU settings associated with a task.
 */
    xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

#endif /* portUSING_MPU_WRAPPERS */


#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )

/*
 * For internal use only.  Grant/Revoke a task's access to a kernel object.
 */
    void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
                                     int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;
    void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle,
                                      int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION;

/*
 * For internal use only.  Grant/Revoke a task's access to a kernel object.
 */
    void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                         int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
    void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
                                          int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;

#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */
#endif /* INC_TASK_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


#ifndef TIMERS_H
#define TIMERS_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include timers.h"
#endif

#include "task.h"


/* *INDENT-OFF* */
#ifdef __cplusplus
    extern "C" {
#endif
/* *INDENT-ON* */

/*-----------------------------------------------------------
* MACROS AND DEFINITIONS
*----------------------------------------------------------*/

/* IDs for commands that can be sent/received on the timer queue.  These are to
 * be used solely through the macros that make up the public software timer API,
 * as defined below.  The commands that are sent from interrupts must use the
 * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
 * or interrupt version of the queue send function should be used. */
#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )
#define tmrCOMMAND_EXECUTE_CALLBACK             ( ( BaseType_t ) -1 )
#define tmrCOMMAND_START_DONT_TRACE             ( ( BaseType_t ) 0 )
#define tmrCOMMAND_START                        ( ( BaseType_t ) 1 )
#define tmrCOMMAND_RESET                        ( ( BaseType_t ) 2 )
#define tmrCOMMAND_STOP                         ( ( BaseType_t ) 3 )
#define tmrCOMMAND_CHANGE_PERIOD                ( ( BaseType_t ) 4 )
#define tmrCOMMAND_DELETE                       ( ( BaseType_t ) 5 )

#define tmrFIRST_FROM_ISR_COMMAND               ( ( BaseType_t ) 6 )
#define tmrCOMMAND_START_FROM_ISR               ( ( BaseType_t ) 6 )
#define tmrCOMMAND_RESET_FROM_ISR               ( ( BaseType_t ) 7 )
#define tmrCOMMAND_STOP_FROM_ISR                ( ( BaseType_t ) 8 )
#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR       ( ( BaseType_t ) 9 )


/**
 * Type by which software timers are referenced.  For example, a call to
 * xTimerCreate() returns an TimerHandle_t variable that can then be used to
 * reference the subject timer in calls to other software timer API functions
 * (for example, xTimerStart(), xTimerReset(), etc.).
 */
struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
typedef struct tmrTimerControl * TimerHandle_t;

/*
 * Defines the prototype to which timer callback functions must conform.
 */
typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );

/*
 * Defines the prototype to which functions used with the
 * xTimerPendFunctionCallFromISR() function must conform.
 */
typedef void (* PendedFunction_t)( void * arg1,
                                   uint32_t arg2 );

/**
 * TimerHandle_t xTimerCreate(  const char * const pcTimerName,
 *                              TickType_t xTimerPeriodInTicks,
 *                              BaseType_t xAutoReload,
 *                              void * pvTimerID,
 *                              TimerCallbackFunction_t pxCallbackFunction );
 *
 * Creates a new software timer instance, and returns a handle by which the
 * created software timer can be referenced.
 *
 * Internally, within the FreeRTOS implementation, software timers use a block
 * of memory, in which the timer data structure is stored.  If a software timer
 * is created using xTimerCreate() then the required memory is automatically
 * dynamically allocated inside the xTimerCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
 * xTimerCreateStatic() then the application writer must provide the memory that
 * will get used by the software timer.  xTimerCreateStatic() therefore allows a
 * software timer to be created without using any dynamic memory allocation.
 *
 * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
 * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
 * xTimerChangePeriodFromISR() API functions can all be used to transition a
 * timer into the active state.
 *
 * @param pcTimerName A text name that is assigned to the timer.  This is done
 * purely to assist debugging.  The kernel itself only ever references a timer
 * by its handle, and never by its name.
 *
 * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
 * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
 * has been specified in milliseconds.  For example, if the timer must expire
 * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
 * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
 * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
 * equal to 1000.  Time timer period must be greater than 0.
 *
 * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
 * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
 * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
 * enter the dormant state after it expires.
 *
 * @param pvTimerID An identifier that is assigned to the timer being created.
 * Typically this would be used in the timer callback function to identify which
 * timer expired when the same callback function is assigned to more than one
 * timer.
 *
 * @param pxCallbackFunction The function to call when the timer expires.
 * Callback functions must have the prototype defined by TimerCallbackFunction_t,
 * which is "void vCallbackFunction( TimerHandle_t xTimer );".
 *
 * @return If the timer is successfully created then a handle to the newly
 * created timer is returned.  If the timer cannot be created because there is
 * insufficient FreeRTOS heap remaining to allocate the timer
 * structures then NULL is returned.
 *
 * Example usage:
 * @verbatim
 * #define NUM_TIMERS 5
 *
 * // An array to hold handles to the created timers.
 * TimerHandle_t xTimers[ NUM_TIMERS ];
 *
 * // An array to hold a count of the number of times each timer expires.
 * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
 *
 * // Define a callback function that will be used by multiple timer instances.
 * // The callback function does nothing but count the number of times the
 * // associated timer expires, and stop the timer once the timer has expired
 * // 10 times.
 * void vTimerCallback( TimerHandle_t pxTimer )
 * {
 * int32_t lArrayIndex;
 * const int32_t xMaxExpiryCountBeforeStopping = 10;
 *
 *     // Optionally do something if the pxTimer parameter is NULL.
 *     configASSERT( pxTimer );
 *
 *     // Which timer expired?
 *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
 *
 *     // Increment the number of times that pxTimer has expired.
 *     lExpireCounters[ lArrayIndex ] += 1;
 *
 *     // If the timer has expired 10 times then stop it from running.
 *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
 *     {
 *         // Do not use a block time if calling a timer API function from a
 *         // timer callback function, as doing so could cause a deadlock!
 *         xTimerStop( pxTimer, 0 );
 *     }
 * }
 *
 * void main( void )
 * {
 * int32_t x;
 *
 *     // Create then start some timers.  Starting the timers before the scheduler
 *     // has been started means the timers will start running immediately that
 *     // the scheduler starts.
 *     for( x = 0; x < NUM_TIMERS; x++ )
 *     {
 *         xTimers[ x ] = xTimerCreate(    "Timer",             // Just a text name, not used by the kernel.
 *                                         ( 100 * ( x + 1 ) ), // The timer period in ticks.
 *                                         pdTRUE,              // The timers will auto-reload themselves when they expire.
 *                                         ( void * ) x,        // Assign each timer a unique id equal to its array index.
 *                                         vTimerCallback       // Each timer calls the same callback when it expires.
 *                                     );
 *
 *         if( xTimers[ x ] == NULL )
 *         {
 *             // The timer was not created.
 *         }
 *         else
 *         {
 *             // Start the timer.  No block time is specified, and even if one was
 *             // it would be ignored because the scheduler has not yet been
 *             // started.
 *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
 *             {
 *                 // The timer could not be set into the Active state.
 *             }
 *         }
 *     }
 *
 *     // ...
 *     // Create tasks here.
 *     // ...
 *
 *     // Starting the scheduler will start the timers running as they have already
 *     // been set into the active state.
 *     vTaskStartScheduler();
 *
 *     // Should not reach here.
 *     for( ;; );
 * }
 * @endverbatim
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    TimerHandle_t xTimerCreate( const char * const pcTimerName,
                                const TickType_t xTimerPeriodInTicks,
                                const BaseType_t xAutoReload,
                                void * const pvTimerID,
                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
#endif

/**
 * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
 *                                  TickType_t xTimerPeriodInTicks,
 *                                  BaseType_t xAutoReload,
 *                                  void * pvTimerID,
 *                                  TimerCallbackFunction_t pxCallbackFunction,
 *                                  StaticTimer_t *pxTimerBuffer );
 *
 * Creates a new software timer instance, and returns a handle by which the
 * created software timer can be referenced.
 *
 * Internally, within the FreeRTOS implementation, software timers use a block
 * of memory, in which the timer data structure is stored.  If a software timer
 * is created using xTimerCreate() then the required memory is automatically
 * dynamically allocated inside the xTimerCreate() function.  (see
 * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
 * xTimerCreateStatic() then the application writer must provide the memory that
 * will get used by the software timer.  xTimerCreateStatic() therefore allows a
 * software timer to be created without using any dynamic memory allocation.
 *
 * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
 * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
 * xTimerChangePeriodFromISR() API functions can all be used to transition a
 * timer into the active state.
 *
 * @param pcTimerName A text name that is assigned to the timer.  This is done
 * purely to assist debugging.  The kernel itself only ever references a timer
 * by its handle, and never by its name.
 *
 * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
 * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
 * has been specified in milliseconds.  For example, if the timer must expire
 * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
 * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
 * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
 * equal to 1000.  The timer period must be greater than 0.
 *
 * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
 * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
 * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
 * enter the dormant state after it expires.
 *
 * @param pvTimerID An identifier that is assigned to the timer being created.
 * Typically this would be used in the timer callback function to identify which
 * timer expired when the same callback function is assigned to more than one
 * timer.
 *
 * @param pxCallbackFunction The function to call when the timer expires.
 * Callback functions must have the prototype defined by TimerCallbackFunction_t,
 * which is "void vCallbackFunction( TimerHandle_t xTimer );".
 *
 * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
 * will be then be used to hold the software timer's data structures, removing
 * the need for the memory to be allocated dynamically.
 *
 * @return If the timer is created then a handle to the created timer is
 * returned.  If pxTimerBuffer was NULL then NULL is returned.
 *
 * Example usage:
 * @verbatim
 *
 * // The buffer used to hold the software timer's data structure.
 * static StaticTimer_t xTimerBuffer;
 *
 * // A variable that will be incremented by the software timer's callback
 * // function.
 * UBaseType_t uxVariableToIncrement = 0;
 *
 * // A software timer callback function that increments a variable passed to
 * // it when the software timer was created.  After the 5th increment the
 * // callback function stops the software timer.
 * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
 * {
 * UBaseType_t *puxVariableToIncrement;
 * BaseType_t xReturned;
 *
 *     // Obtain the address of the variable to increment from the timer ID.
 *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
 *
 *     // Increment the variable to show the timer callback has executed.
 *     ( *puxVariableToIncrement )++;
 *
 *     // If this callback has executed the required number of times, stop the
 *     // timer.
 *     if( *puxVariableToIncrement == 5 )
 *     {
 *         // This is called from a timer callback so must not block.
 *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
 *     }
 * }
 *
 *
 * void main( void )
 * {
 *     // Create the software time.  xTimerCreateStatic() has an extra parameter
 *     // than the normal xTimerCreate() API function.  The parameter is a pointer
 *     // to the StaticTimer_t structure that will hold the software timer
 *     // structure.  If the parameter is passed as NULL then the structure will be
 *     // allocated dynamically, just as if xTimerCreate() had been called.
 *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
 *                                  xTimerPeriod,     // The period of the timer in ticks.
 *                                  pdTRUE,           // This is an auto-reload timer.
 *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
 *                                  prvTimerCallback, // The function to execute when the timer expires.
 *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
 *
 *     // The scheduler has not started yet so a block time is not used.
 *     xReturned = xTimerStart( xTimer, 0 );
 *
 *     // ...
 *     // Create tasks here.
 *     // ...
 *
 *     // Starting the scheduler will start the timers running as they have already
 *     // been set into the active state.
 *     vTaskStartScheduler();
 *
 *     // Should not reach here.
 *     for( ;; );
 * }
 * @endverbatim
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
                                      const TickType_t xTimerPeriodInTicks,
                                      const BaseType_t xAutoReload,
                                      void * const pvTimerID,
                                      TimerCallbackFunction_t pxCallbackFunction,
                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

/**
 * void *pvTimerGetTimerID( TimerHandle_t xTimer );
 *
 * Returns the ID assigned to the timer.
 *
 * IDs are assigned to timers using the pvTimerID parameter of the call to
 * xTimerCreated() that was used to create the timer, and by calling the
 * vTimerSetTimerID() API function.
 *
 * If the same callback function is assigned to multiple timers then the timer
 * ID can be used as time specific (timer local) storage.
 *
 * @param xTimer The timer being queried.
 *
 * @return The ID assigned to the timer being queried.
 *
 * Example usage:
 *
 * See the xTimerCreate() API function example usage scenario.
 */
void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
 *
 * Sets the ID assigned to the timer.
 *
 * IDs are assigned to timers using the pvTimerID parameter of the call to
 * xTimerCreated() that was used to create the timer.
 *
 * If the same callback function is assigned to multiple timers then the timer
 * ID can be used as time specific (timer local) storage.
 *
 * @param xTimer The timer being updated.
 *
 * @param pvNewID The ID to assign to the timer.
 *
 * Example usage:
 *
 * See the xTimerCreate() API function example usage scenario.
 */
void vTimerSetTimerID( TimerHandle_t xTimer,
                       void * pvNewID ) PRIVILEGED_FUNCTION;

/**
 * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
 *
 * Queries a timer to see if it is active or dormant.
 *
 * A timer will be dormant if:
 *     1) It has been created but not started, or
 *     2) It is an expired one-shot timer that has not been restarted.
 *
 * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
 * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
 * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
 * active state.
 *
 * @param xTimer The timer being queried.
 *
 * @return pdFALSE will be returned if the timer is dormant.  A value other than
 * pdFALSE will be returned if the timer is active.
 *
 * Example usage:
 * @verbatim
 * // This function assumes xTimer has already been created.
 * void vAFunction( TimerHandle_t xTimer )
 * {
 *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
 *     {
 *         // xTimer is active, do something.
 *     }
 *     else
 *     {
 *         // xTimer is not active, do something else.
 *     }
 * }
 * @endverbatim
 */
BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
 *
 * Simply returns the handle of the timer service/daemon task.  It it not valid
 * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
 */
TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;

/**
 * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
 *
 * Timer functionality is provided by a timer service/daemon task.  Many of the
 * public FreeRTOS timer API functions send commands to the timer service task
 * through a queue called the timer command queue.  The timer command queue is
 * private to the kernel itself and is not directly accessible to application
 * code.  The length of the timer command queue is set by the
 * configTIMER_QUEUE_LENGTH configuration constant.
 *
 * xTimerStart() starts a timer that was previously created using the
 * xTimerCreate() API function.  If the timer had already been started and was
 * already in the active state, then xTimerStart() has equivalent functionality
 * to the xTimerReset() API function.
 *
 * Starting a timer ensures the timer is in the active state.  If the timer
 * is not stopped, deleted, or reset in the mean time, the callback function
 * associated with the timer will get called 'n' ticks after xTimerStart() was
 * called, where 'n' is the timers defined period.
 *
 * It is valid to call xTimerStart() before the scheduler has been started, but
 * when this is done the timer will not actually start until the scheduler is
 * started, and the timers expiry time will be relative to when the scheduler is
 * started, not relative to when xTimerStart() was called.
 *
 * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
 * to be available.
 *
 * @param xTimer The handle of the timer being started/restarted.
 *
 * @param xTicksToWait Specifies the time, in ticks, that the calling task should
 * be held in the Blocked state to wait for the start command to be successfully
 * sent to the timer command queue, should the queue already be full when
 * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
 * before the scheduler is started.
 *
 * @return pdFAIL will be returned if the start command could not be sent to
 * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
 * be returned if the command was successfully sent to the timer command queue.
 * When the command is actually processed will depend on the priority of the
 * timer service/daemon task relative to other tasks in the system, although the
 * timers expiry time is relative to when xTimerStart() is actually called.  The
 * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
 * configuration constant.
 *
 * Example usage:
 *
 * See the xTimerCreate() API function example usage scenario.
 *
 */
#define xTimerStart( xTimer, xTicksToWait ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )

/**
 * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
 *
 * Timer functionality is provided by a timer service/daemon task.  Many of the
 * public FreeRTOS timer API functions send commands to the timer service task
 * through a queue called the timer command queue.  The timer command queue is
 * private to the kernel itself and is not directly accessible to application
 * code.  The length of the timer command queue is set by the
 * configTIMER_QUEUE_LENGTH configuration constant.
 *
 * xTimerStop() stops a timer that was previously started using either of the
 * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
 * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
 *
 * Stopping a timer ensures the timer is not in the active state.
 *
 * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
 * to be available.
 *
 * @param xTimer The handle of the timer being stopped.
 *
 * @param xTicksToWait Specifies the time, in ticks, that the calling task should
 * be held in the Blocked state to wait for the stop command to be successfully
 * sent to the timer command queue, should the queue already be full when
 * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
 * before the scheduler is started.
 *
 * @return pdFAIL will be returned if the stop command could not be sent to
 * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
 * be returned if the command was successfully sent to the timer command queue.
 * When the command is actually processed will depend on the priority of the
 * timer service/daemon task relative to other tasks in the system.  The timer
 * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
 * configuration constant.
 *
 * Example usage:
 *
 * See the xTimerCreate() API function example usage scenario.
 *
 */
#define xTimerStop( xTimer, xTicksToWait ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )

/**
 * BaseType_t xTimerChangePeriod(   TimerHandle_t xTimer,
 *                                  TickType_t xNewPeriod,
 *                                  TickType_t xTicksToWait );
 *
 * Timer functionality is provided by a timer service/daemon task.  Many of the
 * public FreeRTOS timer API functions send commands to the timer service task
 * through a queue called the timer command queue.  The timer command queue is
 * private to the kernel itself and is not directly accessible to application
 * code.  The length of the timer command queue is set by the
 * configTIMER_QUEUE_LENGTH configuration constant.
 *
 * xTimerChangePeriod() changes the period of a timer that was previously
 * created using the xTimerCreate() API function.
 *
 * xTimerChangePeriod() can be called to change the period of an active or
 * dormant state timer.
 *
 * The configUSE_TIMERS configuration constant must be set to 1 for
 * xTimerChangePeriod() to be available.
 *
 * @param xTimer The handle of the timer that is having its period changed.
 *
 * @param xNewPeriod The new period for xTimer. Timer periods are specified in
 * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
 * that has been specified in milliseconds.  For example, if the timer must
 * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
 * if the timer must expire after 500ms, then xNewPeriod can be set to
 * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
 * or equal to 1000.
 *
 * @param xTicksToWait Specifies the time, in ticks, that the calling task should
 * be held in the Blocked state to wait for the change period command to be
 * successfully sent to the timer command queue, should the queue already be
 * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
 * xTimerChangePeriod() is called before the scheduler is started.
 *
 * @return pdFAIL will be returned if the change period command could not be
 * sent to the timer command queue even after xTicksToWait ticks had passed.
 * pdPASS will be returned if the command was successfully sent to the timer
 * command queue.  When the command is actually processed will depend on the
 * priority of the timer service/daemon task relative to other tasks in the
 * system.  The timer service/daemon task priority is set by the
 * configTIMER_TASK_PRIORITY configuration constant.
 *
 * Example usage:
 * @verbatim
 * // This function assumes xTimer has already been created.  If the timer
 * // referenced by xTimer is already active when it is called, then the timer
 * // is deleted.  If the timer referenced by xTimer is not active when it is
 * // called, then the period of the timer is set to 500ms and the timer is
 * // started.
 * void vAFunction( TimerHandle_t xTimer )
 * {
 *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
 *     {
 *         // xTimer is already active - delete it.
 *         xTimerDelete( xTimer );
 *     }
 *     else
 *     {
 *         // xTimer is not active, change its period to 500ms.  This will also
 *         // cause the timer to start.  Block for a maximum of 100 ticks if the
 *         // change period command cannot immediately be sent to the timer
 *         // command queue.
 *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
 *         {
 *             // The command was successfully sent.
 *         }
 *         else
 *         {
 *             // The command could not be sent, even after waiting for 100 ticks
 *             // to pass.  Take appropriate action here.
 *         }
 *     }
 * }
 * @endverbatim
 */
#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )

/**
 * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
 *
 * Timer functionality is provided by a timer service/daemon task.  Many of the
 * public FreeRTOS timer API functions send commands to the timer service task
 * through a queue called the timer command queue.  The timer command queue is
 * private to the kernel itself and is not directly accessible to application
 * code.  The length of the timer command queue is set by the
 * configTIMER_QUEUE_LENGTH configuration constant.
 *
 * xTimerDelete() deletes a timer that was previously created using the
 * xTimerCreate() API function.
 *
 * The configUSE_TIMERS configuration constant must be set to 1 for
 * xTimerDelete() to be available.
 *
 * @param xTimer The handle of the timer being deleted.
 *
 * @param xTicksToWait Specifies the time, in ticks, that the calling task should
 * be held in the Blocked state to wait for the delete command to be
 * successfully sent to the timer command queue, should the queue already be
 * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
 * is called before the scheduler is started.
 *
 * @return pdFAIL will be returned if the delete command could not be sent to
 * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
 * be returned if the command was successfully sent to the timer command queue.
 * When the command is actually processed will depend on the priority of the
 * timer service/daemon task relative to other tasks in the system.  The timer
 * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
 * configuration constant.
 *
 * Example usage:
 *
 * See the xTimerChangePeriod() API function example usage scenario.
 */
#define xTimerDelete( xTimer, xTicksToWait ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )

/**
 * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
 *
 * Timer functionality is provided by a timer service/daemon task.  Many of the
 * public FreeRTOS timer API functions send commands to the timer service task
 * through a queue called the timer command queue.  The timer command queue is
 * private to the kernel itself and is not directly accessible to application
 * code.  The length of the timer command queue is set by the
 * configTIMER_QUEUE_LENGTH configuration constant.
 *
 * xTimerReset() re-starts a timer that was previously created using the
 * xTimerCreate() API function.  If the timer had already been started and was
 * already in the active state, then xTimerReset() will cause the timer to
 * re-evaluate its expiry time so that it is relative to when xTimerReset() was
 * called.  If the timer was in the dormant state then xTimerReset() has
 * equivalent functionality to the xTimerStart() API function.
 *
 * Resetting a timer ensures the timer is in the active state.  If the timer
 * is not stopped, deleted, or reset in the mean time, the callback function
 * associated with the timer will get called 'n' ticks after xTimerReset() was
 * called, where 'n' is the timers defined period.
 *
 * It is valid to call xTimerReset() before the scheduler has been started, but
 * when this is done the timer will not actually start until the scheduler is
 * started, and the timers expiry time will be relative to when the scheduler is
 * started, not relative to when xTimerReset() was called.
 *
 * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
 * to be available.
 *
 * @param xTimer The handle of the timer being reset/started/restarted.
 *
 * @param xTicksToWait Specifies the time, in ticks, that the calling task should
 * be held in the Blocked state to wait for the reset command to be successfully
 * sent to the timer command queue, should the queue already be full when
 * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
 * before the scheduler is started.
 *
 * @return pdFAIL will be returned if the reset command could not be sent to
 * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
 * be returned if the command was successfully sent to the timer command queue.
 * When the command is actually processed will depend on the priority of the
 * timer service/daemon task relative to other tasks in the system, although the
 * timers expiry time is relative to when xTimerStart() is actually called.  The
 * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
 * configuration constant.
 *
 * Example usage:
 * @verbatim
 * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
 * // without a key being pressed, then the LCD back-light is switched off.  In
 * // this case, the timer is a one-shot timer.
 *
 * TimerHandle_t xBacklightTimer = NULL;
 *
 * // The callback function assigned to the one-shot timer.  In this case the
 * // parameter is not used.
 * void vBacklightTimerCallback( TimerHandle_t pxTimer )
 * {
 *     // The timer expired, therefore 5 seconds must have passed since a key
 *     // was pressed.  Switch off the LCD back-light.
 *     vSetBacklightState( BACKLIGHT_OFF );
 * }
 *
 * // The key press event handler.
 * void vKeyPressEventHandler( char cKey )
 * {
 *     // Ensure the LCD back-light is on, then reset the timer that is
 *     // responsible for turning the back-light off after 5 seconds of
 *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
 *     // if it cannot be sent immediately.
 *     vSetBacklightState( BACKLIGHT_ON );
 *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
 *     {
 *         // The reset command was not executed successfully.  Take appropriate
 *         // action here.
 *     }
 *
 *     // Perform the rest of the key processing here.
 * }
 *
 * void main( void )
 * {
 * int32_t x;
 *
 *     // Create then start the one-shot timer that is responsible for turning
 *     // the back-light off if no keys are pressed within a 5 second period.
 *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
 *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
 *                                     pdFALSE,                    // The timer is a one-shot timer.
 *                                     0,                          // The id is not used by the callback so can take any value.
 *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
 *                                   );
 *
 *     if( xBacklightTimer == NULL )
 *     {
 *         // The timer was not created.
 *     }
 *     else
 *     {
 *         // Start the timer.  No block time is specified, and even if one was
 *         // it would be ignored because the scheduler has not yet been
 *         // started.
 *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
 *         {
 *             // The timer could not be set into the Active state.
 *         }
 *     }
 *
 *     // ...
 *     // Create tasks here.
 *     // ...
 *
 *     // Starting the scheduler will start the timer running as it has already
 *     // been set into the active state.
 *     vTaskStartScheduler();
 *
 *     // Should not reach here.
 *     for( ;; );
 * }
 * @endverbatim
 */
#define xTimerReset( xTimer, xTicksToWait ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )

/**
 * BaseType_t xTimerStartFromISR(   TimerHandle_t xTimer,
 *                                  BaseType_t *pxHigherPriorityTaskWoken );
 *
 * A version of xTimerStart() that can be called from an interrupt service
 * routine.
 *
 * @param xTimer The handle of the timer being started/restarted.
 *
 * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
 * of its time in the Blocked state, waiting for messages to arrive on the timer
 * command queue.  Calling xTimerStartFromISR() writes a message to the timer
 * command queue, so has the potential to transition the timer service/daemon
 * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
 * timer service/daemon task to leave the Blocked state, and the timer service/
 * daemon task has a priority equal to or greater than the currently executing
 * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
 * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
 * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
 * be performed before the interrupt exits.
 *
 * @return pdFAIL will be returned if the start command could not be sent to
 * the timer command queue.  pdPASS will be returned if the command was
 * successfully sent to the timer command queue.  When the command is actually
 * processed will depend on the priority of the timer service/daemon task
 * relative to other tasks in the system, although the timers expiry time is
 * relative to when xTimerStartFromISR() is actually called.  The timer
 * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
 * configuration constant.
 *
 * Example usage:
 * @verbatim
 * // This scenario assumes xBacklightTimer has already been created.  When a
 * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
 * // without a key being pressed, then the LCD back-light is switched off.  In
 * // this case, the timer is a one-shot timer, and unlike the example given for
 * // the xTimerReset() function, the key press event handler is an interrupt
 * // service routine.
 *
 * // The callback function assigned to the one-shot timer.  In this case the
 * // parameter is not used.
 * void vBacklightTimerCallback( TimerHandle_t pxTimer )
 * {
 *     // The timer expired, therefore 5 seconds must have passed since a key
 *     // was pressed.  Switch off the LCD back-light.
 *     vSetBacklightState( BACKLIGHT_OFF );
 * }
 *
 * // The key press interrupt service routine.
 * void vKeyPressEventInterruptHandler( void )
 * {
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 *
 *     // Ensure the LCD back-light is on, then restart the timer that is
 *     // responsible for turning the back-light off after 5 seconds of
 *     // key inactivity.  This is an interrupt service routine so can only
 *     // call FreeRTOS API functions that end in "FromISR".
 *     vSetBacklightState( BACKLIGHT_ON );
 *
 *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
 *     // as both cause the timer to re-calculate its expiry time.
 *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
 *     // declared (in this function).
 *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
 *     {
 *         // The start command was not executed successfully.  Take appropriate
 *         // action here.
 *     }
 *
 *     // Perform the rest of the key processing here.
 *
 *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
 *     // should be performed.  The syntax required to perform a context switch
 *     // from inside an ISR varies from port to port, and from compiler to
 *     // compiler.  Inspect the demos for the port you are using to find the
 *     // actual syntax required.
 *     if( xHigherPriorityTaskWoken != pdFALSE )
 *     {
 *         // Call the interrupt safe yield function here (actual function
 *         // depends on the FreeRTOS port being used).
 *     }
 * }
 * @endverbatim
 */
#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )

/**
 * BaseType_t xTimerStopFromISR(    TimerHandle_t xTimer,
 *                                  BaseType_t *pxHigherPriorityTaskWoken );
 *
 * A version of xTimerStop() that can be called from an interrupt service
 * routine.
 *
 * @param xTimer The handle of the timer being stopped.
 *
 * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
 * of its time in the Blocked state, waiting for messages to arrive on the timer
 * command queue.  Calling xTimerStopFromISR() writes a message to the timer
 * command queue, so has the potential to transition the timer service/daemon
 * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
 * timer service/daemon task to leave the Blocked state, and the timer service/
 * daemon task has a priority equal to or greater than the currently executing
 * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
 * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
 * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
 * be performed before the interrupt exits.
 *
 * @return pdFAIL will be returned if the stop command could not be sent to
 * the timer command queue.  pdPASS will be returned if the command was
 * successfully sent to the timer command queue.  When the command is actually
 * processed will depend on the priority of the timer service/daemon task
 * relative to other tasks in the system.  The timer service/daemon task
 * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
 *
 * Example usage:
 * @verbatim
 * // This scenario assumes xTimer has already been created and started.  When
 * // an interrupt occurs, the timer should be simply stopped.
 *
 * // The interrupt service routine that stops the timer.
 * void vAnExampleInterruptServiceRoutine( void )
 * {
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 *
 *     // The interrupt has occurred - simply stop the timer.
 *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
 *     // (within this function).  As this is an interrupt service routine, only
 *     // FreeRTOS API functions that end in "FromISR" can be used.
 *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
 *     {
 *         // The stop command was not executed successfully.  Take appropriate
 *         // action here.
 *     }
 *
 *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
 *     // should be performed.  The syntax required to perform a context switch
 *     // from inside an ISR varies from port to port, and from compiler to
 *     // compiler.  Inspect the demos for the port you are using to find the
 *     // actual syntax required.
 *     if( xHigherPriorityTaskWoken != pdFALSE )
 *     {
 *         // Call the interrupt safe yield function here (actual function
 *         // depends on the FreeRTOS port being used).
 *     }
 * }
 * @endverbatim
 */
#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )

/**
 * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
 *                                       TickType_t xNewPeriod,
 *                                       BaseType_t *pxHigherPriorityTaskWoken );
 *
 * A version of xTimerChangePeriod() that can be called from an interrupt
 * service routine.
 *
 * @param xTimer The handle of the timer that is having its period changed.
 *
 * @param xNewPeriod The new period for xTimer. Timer periods are specified in
 * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
 * that has been specified in milliseconds.  For example, if the timer must
 * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
 * if the timer must expire after 500ms, then xNewPeriod can be set to
 * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
 * or equal to 1000.
 *
 * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
 * of its time in the Blocked state, waiting for messages to arrive on the timer
 * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
 * timer command queue, so has the potential to transition the timer service/
 * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
 * causes the timer service/daemon task to leave the Blocked state, and the
 * timer service/daemon task has a priority equal to or greater than the
 * currently executing task (the task that was interrupted), then
 * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
 * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
 * this value to pdTRUE then a context switch should be performed before the
 * interrupt exits.
 *
 * @return pdFAIL will be returned if the command to change the timers period
 * could not be sent to the timer command queue.  pdPASS will be returned if the
 * command was successfully sent to the timer command queue.  When the command
 * is actually processed will depend on the priority of the timer service/daemon
 * task relative to other tasks in the system.  The timer service/daemon task
 * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
 *
 * Example usage:
 * @verbatim
 * // This scenario assumes xTimer has already been created and started.  When
 * // an interrupt occurs, the period of xTimer should be changed to 500ms.
 *
 * // The interrupt service routine that changes the period of xTimer.
 * void vAnExampleInterruptServiceRoutine( void )
 * {
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 *
 *     // The interrupt has occurred - change the period of xTimer to 500ms.
 *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
 *     // (within this function).  As this is an interrupt service routine, only
 *     // FreeRTOS API functions that end in "FromISR" can be used.
 *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
 *     {
 *         // The command to change the timers period was not executed
 *         // successfully.  Take appropriate action here.
 *     }
 *
 *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
 *     // should be performed.  The syntax required to perform a context switch
 *     // from inside an ISR varies from port to port, and from compiler to
 *     // compiler.  Inspect the demos for the port you are using to find the
 *     // actual syntax required.
 *     if( xHigherPriorityTaskWoken != pdFALSE )
 *     {
 *         // Call the interrupt safe yield function here (actual function
 *         // depends on the FreeRTOS port being used).
 *     }
 * }
 * @endverbatim
 */
#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )

/**
 * BaseType_t xTimerResetFromISR(   TimerHandle_t xTimer,
 *                                  BaseType_t *pxHigherPriorityTaskWoken );
 *
 * A version of xTimerReset() that can be called from an interrupt service
 * routine.
 *
 * @param xTimer The handle of the timer that is to be started, reset, or
 * restarted.
 *
 * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
 * of its time in the Blocked state, waiting for messages to arrive on the timer
 * command queue.  Calling xTimerResetFromISR() writes a message to the timer
 * command queue, so has the potential to transition the timer service/daemon
 * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
 * timer service/daemon task to leave the Blocked state, and the timer service/
 * daemon task has a priority equal to or greater than the currently executing
 * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
 * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
 * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
 * be performed before the interrupt exits.
 *
 * @return pdFAIL will be returned if the reset command could not be sent to
 * the timer command queue.  pdPASS will be returned if the command was
 * successfully sent to the timer command queue.  When the command is actually
 * processed will depend on the priority of the timer service/daemon task
 * relative to other tasks in the system, although the timers expiry time is
 * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
 * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
 *
 * Example usage:
 * @verbatim
 * // This scenario assumes xBacklightTimer has already been created.  When a
 * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
 * // without a key being pressed, then the LCD back-light is switched off.  In
 * // this case, the timer is a one-shot timer, and unlike the example given for
 * // the xTimerReset() function, the key press event handler is an interrupt
 * // service routine.
 *
 * // The callback function assigned to the one-shot timer.  In this case the
 * // parameter is not used.
 * void vBacklightTimerCallback( TimerHandle_t pxTimer )
 * {
 *     // The timer expired, therefore 5 seconds must have passed since a key
 *     // was pressed.  Switch off the LCD back-light.
 *     vSetBacklightState( BACKLIGHT_OFF );
 * }
 *
 * // The key press interrupt service routine.
 * void vKeyPressEventInterruptHandler( void )
 * {
 * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
 *
 *     // Ensure the LCD back-light is on, then reset the timer that is
 *     // responsible for turning the back-light off after 5 seconds of
 *     // key inactivity.  This is an interrupt service routine so can only
 *     // call FreeRTOS API functions that end in "FromISR".
 *     vSetBacklightState( BACKLIGHT_ON );
 *
 *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
 *     // as both cause the timer to re-calculate its expiry time.
 *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
 *     // declared (in this function).
 *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
 *     {
 *         // The reset command was not executed successfully.  Take appropriate
 *         // action here.
 *     }
 *
 *     // Perform the rest of the key processing here.
 *
 *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
 *     // should be performed.  The syntax required to perform a context switch
 *     // from inside an ISR varies from port to port, and from compiler to
 *     // compiler.  Inspect the demos for the port you are using to find the
 *     // actual syntax required.
 *     if( xHigherPriorityTaskWoken != pdFALSE )
 *     {
 *         // Call the interrupt safe yield function here (actual function
 *         // depends on the FreeRTOS port being used).
 *     }
 * }
 * @endverbatim
 */
#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \
    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )


/**
 * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
 *                                          void *pvParameter1,
 *                                          uint32_t ulParameter2,
 *                                          BaseType_t *pxHigherPriorityTaskWoken );
 *
 *
 * Used from application interrupt service routines to defer the execution of a
 * function to the RTOS daemon task (the timer service task, hence this function
 * is implemented in timers.c and is prefixed with 'Timer').
 *
 * Ideally an interrupt service routine (ISR) is kept as short as possible, but
 * sometimes an ISR either has a lot of processing to do, or needs to perform
 * processing that is not deterministic.  In these cases
 * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
 * to the RTOS daemon task.
 *
 * A mechanism is provided that allows the interrupt to return directly to the
 * task that will subsequently execute the pended callback function.  This
 * allows the callback function to execute contiguously in time with the
 * interrupt - just as if the callback had executed in the interrupt itself.
 *
 * @param xFunctionToPend The function to execute from the timer service/
 * daemon task.  The function must conform to the PendedFunction_t
 * prototype.
 *
 * @param pvParameter1 The value of the callback function's first parameter.
 * The parameter has a void * type to allow it to be used to pass any type.
 * For example, unsigned longs can be cast to a void *, or the void * can be
 * used to point to a structure.
 *
 * @param ulParameter2 The value of the callback function's second parameter.
 *
 * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
 * will result in a message being sent to the timer daemon task.  If the
 * priority of the timer daemon task (which is set using
 * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
 * the currently running task (the task the interrupt interrupted) then
 * *pxHigherPriorityTaskWoken will be set to pdTRUE within
 * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
 * requested before the interrupt exits.  For that reason
 * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
 * example code below.
 *
 * @return pdPASS is returned if the message was successfully sent to the
 * timer daemon task, otherwise pdFALSE is returned.
 *
 * Example usage:
 * @verbatim
 *
 *  // The callback function that will execute in the context of the daemon task.
 *  // Note callback functions must all use this same prototype.
 *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
 *  {
 *      BaseType_t xInterfaceToService;
 *
 *      // The interface that requires servicing is passed in the second
 *      // parameter.  The first parameter is not used in this case.
 *      xInterfaceToService = ( BaseType_t ) ulParameter2;
 *
 *      // ...Perform the processing here...
 *  }
 *
 *  // An ISR that receives data packets from multiple interfaces
 *  void vAnISR( void )
 *  {
 *      BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
 *
 *      // Query the hardware to determine which interface needs processing.
 *      xInterfaceToService = prvCheckInterfaces();
 *
 *      // The actual processing is to be deferred to a task.  Request the
 *      // vProcessInterface() callback function is executed, passing in the
 *      // number of the interface that needs processing.  The interface to
 *      // service is passed in the second parameter.  The first parameter is
 *      // not used in this case.
 *      xHigherPriorityTaskWoken = pdFALSE;
 *      xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
 *
 *      // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
 *      // switch should be requested.  The macro used is port specific and will
 *      // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
 *      // the documentation page for the port being used.
 *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
 *
 *  }
 * @endverbatim
 */
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
    BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
                                              void * pvParameter1,
                                              uint32_t ulParameter2,
                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
#endif

/**
 * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
 *                                    void *pvParameter1,
 *                                    uint32_t ulParameter2,
 *                                    TickType_t xTicksToWait );
 *
 *
 * Used to defer the execution of a function to the RTOS daemon task (the timer
 * service task, hence this function is implemented in timers.c and is prefixed
 * with 'Timer').
 *
 * @param xFunctionToPend The function to execute from the timer service/
 * daemon task.  The function must conform to the PendedFunction_t
 * prototype.
 *
 * @param pvParameter1 The value of the callback function's first parameter.
 * The parameter has a void * type to allow it to be used to pass any type.
 * For example, unsigned longs can be cast to a void *, or the void * can be
 * used to point to a structure.
 *
 * @param ulParameter2 The value of the callback function's second parameter.
 *
 * @param xTicksToWait Calling this function will result in a message being
 * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
 * time the calling task should remain in the Blocked state (so not using any
 * processing time) for space to become available on the timer queue if the
 * queue is found to be full.
 *
 * @return pdPASS is returned if the message was successfully sent to the
 * timer daemon task, otherwise pdFALSE is returned.
 *
 */
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
    BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
                                       void * pvParameter1,
                                       uint32_t ulParameter2,
                                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
#endif

/**
 * const char * const pcTimerGetName( TimerHandle_t xTimer );
 *
 * Returns the name that was assigned to a timer when the timer was created.
 *
 * @param xTimer The handle of the timer being queried.
 *
 * @return The name assigned to the timer specified by the xTimer parameter.
 */
const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
 *
 * Updates a timer to be either an auto-reload timer, in which case the timer
 * automatically resets itself each time it expires, or a one-shot timer, in
 * which case the timer will only expire once unless it is manually restarted.
 *
 * @param xTimer The handle of the timer being updated.
 *
 * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will
 * expire repeatedly with a frequency set by the timer's period (see the
 * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
 * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and
 * enter the dormant state after it expires.
 */
void vTimerSetReloadMode( TimerHandle_t xTimer,
                          const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION;

/**
 * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer );
 *
 * Queries a timer to determine if it is an auto-reload timer, in which case the timer
 * automatically resets itself each time it expires, or a one-shot timer, in
 * which case the timer will only expire once unless it is manually restarted.
 *
 * @param xTimer The handle of the timer being queried.
 *
 * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
 * pdFALSE is returned.
 */
BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
 *
 * Queries a timer to determine if it is an auto-reload timer, in which case the timer
 * automatically resets itself each time it expires, or a one-shot timer, in
 * which case the timer will only expire once unless it is manually restarted.
 *
 * @param xTimer The handle of the timer being queried.
 *
 * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
 * pdFALSE is returned.
 */
UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
 *
 * Returns the period of a timer.
 *
 * @param xTimer The handle of the timer being queried.
 *
 * @return The period of the timer in ticks.
 */
TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
 *
 * Returns the time in ticks at which the timer will expire.  If this is less
 * than the current tick count then the expiry time has overflowed from the
 * current time.
 *
 * @param xTimer The handle of the timer being queried.
 *
 * @return If the timer is running then the time in ticks at which the timer
 * will next expire is returned.  If the timer is not running then the return
 * value is undefined.
 */
TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;

/**
 * BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
 *                                   StaticTimer_t ** ppxTimerBuffer );
 *
 * Retrieve pointer to a statically created timer's data structure
 * buffer. This is the same buffer that is supplied at the time of
 * creation.
 *
 * @param xTimer The timer for which to retrieve the buffer.
 *
 * @param ppxTaskBuffer Used to return a pointer to the timers's data
 * structure buffer.
 *
 * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
                                      StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
#endif /* configSUPPORT_STATIC_ALLOCATION */

/*
 * Functions beyond this part are not part of the public API and are intended
 * for use by the kernel only.
 */
BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;

/*
 * Splitting the xTimerGenericCommand into two sub functions and making it a macro
 * removes a recursion path when called from ISRs. This is primarily for the XCore
 * XCC port which detects the recursion path and throws an error during compilation
 * when this is not split.
 */
BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
                                         const BaseType_t xCommandID,
                                         const TickType_t xOptionalValue,
                                         BaseType_t * const pxHigherPriorityTaskWoken,
                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
                                        const BaseType_t xCommandID,
                                        const TickType_t xOptionalValue,
                                        BaseType_t * const pxHigherPriorityTaskWoken,
                                        const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;

#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )         \
    ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ?                                                                  \
      xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \
      xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) )
#if ( configUSE_TRACE_FACILITY == 1 )
    void vTimerSetTimerNumber( TimerHandle_t xTimer,
                               UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
    UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
#endif

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

/**
 * task.h
 * @code{c}
 * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
 * @endcode
 *
 * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when
 * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
 *
 * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
 * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
 * @param puxTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
 */
    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
                                         StackType_t ** ppxTimerTaskStackBuffer,
                                         configSTACK_DEPTH_TYPE * puxTimerTaskStackSize );

#endif

#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 )

/**
 *  timers.h
 * @code{c}
 * void vApplicationDaemonTaskStartupHook( void );
 * @endcode
 *
 * This hook function is called form the timer task once when the task starts running.
 */
    /* MISRA Ref 8.6.1 [External linkage] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
    /* coverity[misra_c_2012_rule_8_6_violation] */
    void vApplicationDaemonTaskStartupHook( void );

#endif

/*
 * This function resets the internal state of the timer module. It must be called
 * by the application before restarting the scheduler.
 */
void vTimerResetState( void ) PRIVILEGED_FUNCTION;

/* *INDENT-OFF* */
#ifdef __cplusplus
    }
#endif
/* *INDENT-ON* */
#endif /* TIMERS_H */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/list.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */


#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers.  That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

#include "FreeRTOS.h"
#include "list.h"

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
 * defined for the header files above, but not in this file, in order to
 * generate the correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
    traceENTER_vListInitialise( pxList );

    /* The list structure contains a list item which is used to mark the
     * end of the list.  To initialise the list the list end is inserted
     * as the only list entry. */
    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );

    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );

    /* The list end value is the highest possible value in the list to
     * ensure it remains at the end of the list. */
    pxList->xListEnd.xItemValue = portMAX_DELAY;

    /* The list end next and previous pointers point to itself so we know
     * when the list is empty. */
    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );
    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );

    /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
    #if ( configUSE_MINI_LIST_ITEM == 0 )
    {
        pxList->xListEnd.pvOwner = NULL;
        pxList->xListEnd.pxContainer = NULL;
        listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
    }
    #endif

    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;

    /* Write known values into the list if
     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );

    traceRETURN_vListInitialise();
}
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
    traceENTER_vListInitialiseItem( pxItem );

    /* Make sure the list item is not recorded as being on a list. */
    pxItem->pxContainer = NULL;

    /* Write known values into the list item if
     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );

    traceRETURN_vListInitialiseItem();
}
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList,
                     ListItem_t * const pxNewListItem )
{
    ListItem_t * const pxIndex = pxList->pxIndex;

    traceENTER_vListInsertEnd( pxList, pxNewListItem );

    /* Only effective when configASSERT() is also defined, these tests may catch
     * the list data structures being overwritten in memory.  They will not catch
     * data errors caused by incorrect configuration or use of FreeRTOS. */
    listTEST_LIST_INTEGRITY( pxList );
    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

    /* Insert a new list item into pxList, but rather than sort the list,
     * makes the new list item the last item to be removed by a call to
     * listGET_OWNER_OF_NEXT_ENTRY(). */
    pxNewListItem->pxNext = pxIndex;
    pxNewListItem->pxPrevious = pxIndex->pxPrevious;

    /* Only used during decision coverage testing. */
    mtCOVERAGE_TEST_DELAY();

    pxIndex->pxPrevious->pxNext = pxNewListItem;
    pxIndex->pxPrevious = pxNewListItem;

    /* Remember which list the item is in. */
    pxNewListItem->pxContainer = pxList;

    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );

    traceRETURN_vListInsertEnd();
}
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList,
                  ListItem_t * const pxNewListItem )
{
    ListItem_t * pxIterator;
    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;

    traceENTER_vListInsert( pxList, pxNewListItem );

    /* Only effective when configASSERT() is also defined, these tests may catch
     * the list data structures being overwritten in memory.  They will not catch
     * data errors caused by incorrect configuration or use of FreeRTOS. */
    listTEST_LIST_INTEGRITY( pxList );
    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

    /* Insert the new list item into the list, sorted in xItemValue order.
     *
     * If the list already contains a list item with the same item value then the
     * new list item should be placed after it.  This ensures that TCBs which are
     * stored in ready lists (all of which have the same xItemValue value) get a
     * share of the CPU.  However, if the xItemValue is the same as the back marker
     * the iteration loop below will not end.  Therefore the value is checked
     * first, and the algorithm slightly modified if necessary. */
    if( xValueOfInsertion == portMAX_DELAY )
    {
        pxIterator = pxList->xListEnd.pxPrevious;
    }
    else
    {
        /* *** NOTE ***********************************************************
        *  If you find your application is crashing here then likely causes are
        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
        *  more tips, and ensure configASSERT() is defined!
        *  https://www.FreeRTOS.org/a00110.html#configASSERT
        *
        *   1) Stack overflow -
        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
        *   2) Incorrect interrupt priority assignment, especially on Cortex-M
        *      parts where numerically high priority values denote low actual
        *      interrupt priorities, which can seem counter intuitive.  See
        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on
        *      https://www.FreeRTOS.org/a00110.html
        *   3) Calling an API function from within a critical section or when
        *      the scheduler is suspended, or calling an API function that does
        *      not end in "FromISR" from an interrupt.
        *   4) Using a queue or semaphore before it has been initialised or
        *      before the scheduler has been started (are interrupts firing
        *      before vTaskStartScheduler() has been called?).
        *   5) If the FreeRTOS port supports interrupt nesting then ensure that
        *      the priority of the tick interrupt is at or below
        *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
        **********************************************************************/

        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
        {
            /* There is nothing to do here, just iterating to the wanted
             * insertion position. */
        }
    }

    pxNewListItem->pxNext = pxIterator->pxNext;
    pxNewListItem->pxNext->pxPrevious = pxNewListItem;
    pxNewListItem->pxPrevious = pxIterator;
    pxIterator->pxNext = pxNewListItem;

    /* Remember which list the item is in.  This allows fast removal of the
     * item later. */
    pxNewListItem->pxContainer = pxList;

    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );

    traceRETURN_vListInsert();
}
/*-----------------------------------------------------------*/


UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
    /* The list item knows which list it is in.  Obtain the list from the list
     * item. */
    List_t * const pxList = pxItemToRemove->pxContainer;

    traceENTER_uxListRemove( pxItemToRemove );

    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;

    /* Only used during decision coverage testing. */
    mtCOVERAGE_TEST_DELAY();

    /* Make sure the index is left pointing to a valid item. */
    if( pxList->pxIndex == pxItemToRemove )
    {
        pxList->pxIndex = pxItemToRemove->pxPrevious;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    pxItemToRemove->pxContainer = NULL;
    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems - 1U );

    traceRETURN_uxListRemove( pxList->uxNumberOfItems );

    return pxList->uxNumberOfItems;
}
/*-----------------------------------------------------------*/


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/queue.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#include 
#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers.  That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"

#if ( configUSE_CO_ROUTINES == 1 )
    #include "croutine.h"
#endif

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
 * for the header files above, but not in this file, in order to generate the
 * correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE


/* Constants used with the cRxLock and cTxLock structure members. */
#define queueUNLOCKED             ( ( int8_t ) -1 )
#define queueLOCKED_UNMODIFIED    ( ( int8_t ) 0 )
#define queueINT8_MAX             ( ( int8_t ) 127 )

/* When the Queue_t structure is used to represent a base queue its pcHead and
 * pcTail members are used as pointers into the queue storage area.  When the
 * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
 * not necessary, and the pcHead pointer is set to NULL to indicate that the
 * structure instead holds a pointer to the mutex holder (if any).  Map alternative
 * names to the pcHead and structure member to ensure the readability of the code
 * is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
 * a union as their usage is mutually exclusive dependent on what the queue is
 * being used for. */
#define uxQueueType               pcHead
#define queueQUEUE_IS_MUTEX       NULL

typedef struct QueuePointers
{
    int8_t * pcTail;     /**< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
    int8_t * pcReadFrom; /**< Points to the last place that a queued item was read from when the structure is used as a queue. */
} QueuePointers_t;

typedef struct SemaphoreData
{
    TaskHandle_t xMutexHolder;        /**< The handle of the task that holds the mutex. */
    UBaseType_t uxRecursiveCallCount; /**< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
} SemaphoreData_t;

/* Semaphores do not actually store or copy data, so have an item size of
 * zero. */
#define queueSEMAPHORE_QUEUE_ITEM_LENGTH    ( ( UBaseType_t ) 0 )
#define queueMUTEX_GIVE_BLOCK_TIME          ( ( TickType_t ) 0U )

#if ( configUSE_PREEMPTION == 0 )

/* If the cooperative scheduler is being used then a yield should not be
 * performed just because a higher priority task has been woken. */
    #define queueYIELD_IF_USING_PREEMPTION()
#else
    #if ( configNUMBER_OF_CORES == 1 )
        #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
        #define queueYIELD_IF_USING_PREEMPTION()    vTaskYieldWithinAPI()
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
#endif

/*
 * Definition of the queue used by the scheduler.
 * Items are queued by copy, not reference.  See the following link for the
 * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
 */
typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
    int8_t * pcHead;           /**< Points to the beginning of the queue storage area. */
    int8_t * pcWriteTo;        /**< Points to the free next place in the storage area. */

    union
    {
        QueuePointers_t xQueue;     /**< Data required exclusively when this structure is used as a queue. */
        SemaphoreData_t xSemaphore; /**< Data required exclusively when this structure is used as a semaphore. */
    } u;

    List_t xTasksWaitingToSend;             /**< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
    List_t xTasksWaitingToReceive;          /**< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */

    volatile UBaseType_t uxMessagesWaiting; /**< The number of items currently in the queue. */
    UBaseType_t uxLength;                   /**< The length of the queue defined as the number of items it will hold, not the number of bytes. */
    UBaseType_t uxItemSize;                 /**< The size of each items that the queue will hold. */

    volatile int8_t cRxLock;                /**< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
    volatile int8_t cTxLock;                /**< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */

    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
    #endif

    #if ( configUSE_QUEUE_SETS == 1 )
        struct QueueDefinition * pxQueueSetContainer;
    #endif

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxQueueNumber;
        uint8_t ucQueueType;
    #endif
} xQUEUE;

/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
 * name below to enable the use of older kernel aware debuggers. */
typedef xQUEUE Queue_t;

/*-----------------------------------------------------------*/

/*
 * The queue registry is just a means for kernel aware debuggers to locate
 * queue structures.  It has no other purpose so is an optional component.
 */
#if ( configQUEUE_REGISTRY_SIZE > 0 )

/* The type stored within the queue registry array.  This allows a name
 * to be assigned to each queue making kernel aware debugging a little
 * more user friendly. */
    typedef struct QUEUE_REGISTRY_ITEM
    {
        const char * pcQueueName;
        QueueHandle_t xHandle;
    } xQueueRegistryItem;

/* The old xQueueRegistryItem name is maintained above then typedefed to the
 * new xQueueRegistryItem name below to enable the use of older kernel aware
 * debuggers. */
    typedef xQueueRegistryItem QueueRegistryItem_t;

/* The queue registry is simply an array of QueueRegistryItem_t structures.
 * The pcQueueName member of a structure being NULL is indicative of the
 * array position being vacant. */

/* MISRA Ref 8.4.2 [Declaration shall be visible] */
/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
/* coverity[misra_c_2012_rule_8_4_violation] */
    PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];

#endif /* configQUEUE_REGISTRY_SIZE */

/*
 * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
 * prevent an ISR from adding or removing items to the queue, but does prevent
 * an ISR from removing tasks from the queue event lists.  If an ISR finds a
 * queue is locked it will instead increment the appropriate queue lock count
 * to indicate that a task may require unblocking.  When the queue in unlocked
 * these lock counts are inspected, and the appropriate action taken.
 */
static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;

/*
 * Uses a critical section to determine if there is any data in a queue.
 *
 * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
 */
static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;

/*
 * Uses a critical section to determine if there is any space in a queue.
 *
 * @return pdTRUE if there is no space, otherwise pdFALSE;
 */
static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;

/*
 * Copies an item into the queue, either at the front of the queue or the
 * back of the queue.
 */
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
                                      const void * pvItemToQueue,
                                      const BaseType_t xPosition ) PRIVILEGED_FUNCTION;

/*
 * Copies an item out of a queue.
 */
static void prvCopyDataFromQueue( Queue_t * const pxQueue,
                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;

#if ( configUSE_QUEUE_SETS == 1 )

/*
 * Checks to see if a queue is a member of a queue set, and if so, notifies
 * the queue set that the queue contains data.
 */
    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
#endif

/*
 * Called after a Queue_t structure has been allocated either statically or
 * dynamically to fill in the structure's members.
 */
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
                                   const UBaseType_t uxItemSize,
                                   uint8_t * pucQueueStorage,
                                   const uint8_t ucQueueType,
                                   Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;

/*
 * Mutexes are a special type of queue.  When a mutex is created, first the
 * queue is created, then prvInitialiseMutex() is called to configure the queue
 * as a mutex.
 */
#if ( configUSE_MUTEXES == 1 )
    static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
#endif

#if ( configUSE_MUTEXES == 1 )

/*
 * If a task waiting for a mutex causes the mutex holder to inherit a
 * priority, but the waiting task times out, then the holder should
 * disinherit the priority - but only down to the highest priority of any
 * other tasks that are waiting for the same mutex.  This function returns
 * that priority.
 */
    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
#endif
/*-----------------------------------------------------------*/

/*
 * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
 * accessing the queue event lists.
 */
#define prvLockQueue( pxQueue )                            \
    taskENTER_CRITICAL();                                  \
    {                                                      \
        if( ( pxQueue )->cRxLock == queueUNLOCKED )        \
        {                                                  \
            ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \
        }                                                  \
        if( ( pxQueue )->cTxLock == queueUNLOCKED )        \
        {                                                  \
            ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \
        }                                                  \
    }                                                      \
    taskEXIT_CRITICAL()

/*
 * Macro to increment cTxLock member of the queue data structure. It is
 * capped at the number of tasks in the system as we cannot unblock more
 * tasks than the number of tasks in the system.
 */
#define prvIncrementQueueTxLock( pxQueue, cTxLock )                           \
    do {                                                                      \
        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \
        if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks )                   \
        {                                                                     \
            configASSERT( ( cTxLock ) != queueINT8_MAX );                     \
            ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \
        }                                                                     \
    } while( 0 )

/*
 * Macro to increment cRxLock member of the queue data structure. It is
 * capped at the number of tasks in the system as we cannot unblock more
 * tasks than the number of tasks in the system.
 */
#define prvIncrementQueueRxLock( pxQueue, cRxLock )                           \
    do {                                                                      \
        const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks();         \
        if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks )                   \
        {                                                                     \
            configASSERT( ( cRxLock ) != queueINT8_MAX );                     \
            ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \
        }                                                                     \
    } while( 0 )
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                               BaseType_t xNewQueue )
{
    BaseType_t xReturn = pdPASS;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueGenericReset( xQueue, xNewQueue );

    configASSERT( pxQueue );

    if( ( pxQueue != NULL ) &&
        ( pxQueue->uxLength >= 1U ) &&
        /* Check for multiplication overflow. */
        ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) )
    {
        taskENTER_CRITICAL();
        {
            pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
            pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
            pxQueue->pcWriteTo = pxQueue->pcHead;
            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize );
            pxQueue->cRxLock = queueUNLOCKED;
            pxQueue->cTxLock = queueUNLOCKED;

            if( xNewQueue == pdFALSE )
            {
                /* If there are tasks blocked waiting to read from the queue, then
                 * the tasks will remain blocked as after this function exits the queue
                 * will still be empty.  If there are tasks blocked waiting to write to
                 * the queue, then one should be unblocked as after this function exits
                 * it will be possible to write to it. */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        queueYIELD_IF_USING_PREEMPTION();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* Ensure the event queues start in the correct state. */
                vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
                vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
            }
        }
        taskEXIT_CRITICAL();
    }
    else
    {
        xReturn = pdFAIL;
    }

    configASSERT( xReturn != pdFAIL );

    /* A value is returned for calling semantic consistency with previous
     * versions. */
    traceRETURN_xQueueGenericReset( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
                                             const UBaseType_t uxItemSize,
                                             uint8_t * pucQueueStorage,
                                             StaticQueue_t * pxStaticQueue,
                                             const uint8_t ucQueueType )
    {
        Queue_t * pxNewQueue = NULL;

        traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );

        /* The StaticQueue_t structure and the queue storage area must be
         * supplied. */
        configASSERT( pxStaticQueue );

        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
            ( pxStaticQueue != NULL ) &&

            /* A queue storage area should be provided if the item size is not 0, and
             * should not be provided if the item size is 0. */
            ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) &&
            ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) )
        {
            #if ( configASSERT_DEFINED == 1 )
            {
                /* Sanity check that the size of the structure used to declare a
                 * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
                 * the real queue and semaphore structures. */
                volatile size_t xSize = sizeof( StaticQueue_t );

                /* This assertion cannot be branch covered in unit tests */
                configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */
                ( void ) xSize;                             /* Prevent unused variable warning when configASSERT() is not defined. */
            }
            #endif /* configASSERT_DEFINED */

            /* The address of a statically allocated queue was passed in, use it.
             * The address of a statically allocated storage area was also passed in
             * but is already set. */
            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            pxNewQueue = ( Queue_t * ) pxStaticQueue;

            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
            {
                /* Queues can be allocated wither statically or dynamically, so
                 * note this queue was allocated statically in case the queue is
                 * later deleted. */
                pxNewQueue->ucStaticallyAllocated = pdTRUE;
            }
            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
        }
        else
        {
            configASSERT( pxNewQueue );
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xQueueGenericCreateStatic( pxNewQueue );

        return pxNewQueue;
    }

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

    BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
                                              uint8_t ** ppucQueueStorage,
                                              StaticQueue_t ** ppxStaticQueue )
    {
        BaseType_t xReturn;
        Queue_t * const pxQueue = xQueue;

        traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue );

        configASSERT( pxQueue );
        configASSERT( ppxStaticQueue );

        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
        {
            /* Check if the queue was statically allocated. */
            if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdTRUE )
            {
                if( ppucQueueStorage != NULL )
                {
                    *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
                }

                /* MISRA Ref 11.3.1 [Misaligned access] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                /* coverity[misra_c_2012_rule_11_3_violation] */
                *ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
                xReturn = pdTRUE;
            }
            else
            {
                xReturn = pdFALSE;
            }
        }
        #else /* configSUPPORT_DYNAMIC_ALLOCATION */
        {
            /* Queue must have been statically allocated. */
            if( ppucQueueStorage != NULL )
            {
                *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead;
            }

            *ppxStaticQueue = ( StaticQueue_t * ) pxQueue;
            xReturn = pdTRUE;
        }
        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

        traceRETURN_xQueueGenericGetStaticBuffers( xReturn );

        return xReturn;
    }

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
                                       const UBaseType_t uxItemSize,
                                       const uint8_t ucQueueType )
    {
        Queue_t * pxNewQueue = NULL;
        size_t xQueueSizeInBytes;
        uint8_t * pucQueueStorage;

        traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );

        if( ( uxQueueLength > ( UBaseType_t ) 0 ) &&
            /* Check for multiplication overflow. */
            ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) &&
            /* Check for addition overflow. */
            ( ( UBaseType_t ) ( SIZE_MAX - sizeof( Queue_t ) ) >= ( uxQueueLength * uxItemSize ) ) )
        {
            /* Allocate enough space to hold the maximum number of items that
             * can be in the queue at any time.  It is valid for uxItemSize to be
             * zero in the case the queue is used as a semaphore. */
            xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize );

            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );

            if( pxNewQueue != NULL )
            {
                /* Jump past the queue structure to find the location of the queue
                 * storage area. */
                pucQueueStorage = ( uint8_t * ) pxNewQueue;
                pucQueueStorage += sizeof( Queue_t );

                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                {
                    /* Queues can be created either statically or dynamically, so
                     * note this task was created dynamically in case it is later
                     * deleted. */
                    pxNewQueue->ucStaticallyAllocated = pdFALSE;
                }
                #endif /* configSUPPORT_STATIC_ALLOCATION */

                prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
            }
            else
            {
                traceQUEUE_CREATE_FAILED( ucQueueType );
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            configASSERT( pxNewQueue );
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xQueueGenericCreate( pxNewQueue );

        return pxNewQueue;
    }

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
                                   const UBaseType_t uxItemSize,
                                   uint8_t * pucQueueStorage,
                                   const uint8_t ucQueueType,
                                   Queue_t * pxNewQueue )
{
    /* Remove compiler warnings about unused parameters should
     * configUSE_TRACE_FACILITY not be set to 1. */
    ( void ) ucQueueType;

    if( uxItemSize == ( UBaseType_t ) 0 )
    {
        /* No RAM was allocated for the queue storage area, but PC head cannot
         * be set to NULL because NULL is used as a key to say the queue is used as
         * a mutex.  Therefore just set pcHead to point to the queue as a benign
         * value that is known to be within the memory map. */
        pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
    }
    else
    {
        /* Set the head to the start of the queue storage area. */
        pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
    }

    /* Initialise the queue members as described where the queue type is
     * defined. */
    pxNewQueue->uxLength = uxQueueLength;
    pxNewQueue->uxItemSize = uxItemSize;
    ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );

    #if ( configUSE_TRACE_FACILITY == 1 )
    {
        pxNewQueue->ucQueueType = ucQueueType;
    }
    #endif /* configUSE_TRACE_FACILITY */

    #if ( configUSE_QUEUE_SETS == 1 )
    {
        pxNewQueue->pxQueueSetContainer = NULL;
    }
    #endif /* configUSE_QUEUE_SETS */

    traceQUEUE_CREATE( pxNewQueue );
}
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    static void prvInitialiseMutex( Queue_t * pxNewQueue )
    {
        if( pxNewQueue != NULL )
        {
            /* The queue create function will set all the queue structure members
            * correctly for a generic queue, but this function is creating a
            * mutex.  Overwrite those members that need to be set differently -
            * in particular the information required for priority inheritance. */
            pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
            pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;

            /* In case this is a recursive mutex. */
            pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;

            traceCREATE_MUTEX( pxNewQueue );

            /* Start with the semaphore in the expected state. */
            ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
        }
        else
        {
            traceCREATE_MUTEX_FAILED();
        }
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )

    QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
    {
        QueueHandle_t xNewQueue;
        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;

        traceENTER_xQueueCreateMutex( ucQueueType );

        xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
        prvInitialiseMutex( ( Queue_t * ) xNewQueue );

        traceRETURN_xQueueCreateMutex( xNewQueue );

        return xNewQueue;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )

    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
                                           StaticQueue_t * pxStaticQueue )
    {
        QueueHandle_t xNewQueue;
        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;

        traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );

        /* Prevent compiler warnings about unused parameters if
         * configUSE_TRACE_FACILITY does not equal 1. */
        ( void ) ucQueueType;

        xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
        prvInitialiseMutex( ( Queue_t * ) xNewQueue );

        traceRETURN_xQueueCreateMutexStatic( xNewQueue );

        return xNewQueue;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )

    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
    {
        TaskHandle_t pxReturn;
        Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;

        traceENTER_xQueueGetMutexHolder( xSemaphore );

        configASSERT( xSemaphore );

        /* This function is called by xSemaphoreGetMutexHolder(), and should not
         * be called directly.  Note:  This is a good way of determining if the
         * calling task is the mutex holder, but not a good way of determining the
         * identity of the mutex holder, as the holder may change between the
         * following critical section exiting and the function returning. */
        taskENTER_CRITICAL();
        {
            if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
            {
                pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
            }
            else
            {
                pxReturn = NULL;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xQueueGetMutexHolder( pxReturn );

        return pxReturn;
    }

#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )

    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
    {
        TaskHandle_t pxReturn;

        traceENTER_xQueueGetMutexHolderFromISR( xSemaphore );

        configASSERT( xSemaphore );

        /* Mutexes cannot be used in interrupt service routines, so the mutex
         * holder should not change in an ISR, and therefore a critical section is
         * not required here. */
        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
        {
            pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
        }
        else
        {
            pxReturn = NULL;
        }

        traceRETURN_xQueueGetMutexHolderFromISR( pxReturn );

        return pxReturn;
    }

#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

    BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
    {
        BaseType_t xReturn;
        Queue_t * const pxMutex = ( Queue_t * ) xMutex;

        traceENTER_xQueueGiveMutexRecursive( xMutex );

        configASSERT( pxMutex );

        /* If this is the task that holds the mutex then xMutexHolder will not
         * change outside of this task.  If this task does not hold the mutex then
         * pxMutexHolder can never coincidentally equal the tasks handle, and as
         * this is the only condition we are interested in it does not matter if
         * pxMutexHolder is accessed simultaneously by another task.  Therefore no
         * mutual exclusion is required to test the pxMutexHolder variable. */
        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
        {
            traceGIVE_MUTEX_RECURSIVE( pxMutex );

            /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
             * the task handle, therefore no underflow check is required.  Also,
             * uxRecursiveCallCount is only modified by the mutex holder, and as
             * there can only be one, no mutual exclusion is required to modify the
             * uxRecursiveCallCount member. */
            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;

            /* Has the recursive call count unwound to 0? */
            if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
            {
                /* Return the mutex.  This will automatically unblock any other
                 * task that might be waiting to access the mutex. */
                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            xReturn = pdPASS;
        }
        else
        {
            /* The mutex cannot be given because the calling task is not the
             * holder. */
            xReturn = pdFAIL;

            traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
        }

        traceRETURN_xQueueGiveMutexRecursive( xReturn );

        return xReturn;
    }

#endif /* configUSE_RECURSIVE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( configUSE_RECURSIVE_MUTEXES == 1 )

    BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                         TickType_t xTicksToWait )
    {
        BaseType_t xReturn;
        Queue_t * const pxMutex = ( Queue_t * ) xMutex;

        traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait );

        configASSERT( pxMutex );

        /* Comments regarding mutual exclusion as per those within
         * xQueueGiveMutexRecursive(). */

        traceTAKE_MUTEX_RECURSIVE( pxMutex );

        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
        {
            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
            xReturn = pdPASS;
        }
        else
        {
            xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );

            /* pdPASS will only be returned if the mutex was successfully
             * obtained.  The calling task may have entered the Blocked state
             * before reaching here. */
            if( xReturn != pdFAIL )
            {
                ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
            }
            else
            {
                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
            }
        }

        traceRETURN_xQueueTakeMutexRecursive( xReturn );

        return xReturn;
    }

#endif /* configUSE_RECURSIVE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )

    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
                                                       const UBaseType_t uxInitialCount,
                                                       StaticQueue_t * pxStaticQueue )
    {
        QueueHandle_t xHandle = NULL;

        traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );

        if( ( uxMaxCount != 0U ) &&
            ( uxInitialCount <= uxMaxCount ) )
        {
            xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );

            if( xHandle != NULL )
            {
                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;

                traceCREATE_COUNTING_SEMAPHORE();
            }
            else
            {
                traceCREATE_COUNTING_SEMAPHORE_FAILED();
            }
        }
        else
        {
            configASSERT( xHandle );
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle );

        return xHandle;
    }

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )

    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
                                                 const UBaseType_t uxInitialCount )
    {
        QueueHandle_t xHandle = NULL;

        traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount );

        if( ( uxMaxCount != 0U ) &&
            ( uxInitialCount <= uxMaxCount ) )
        {
            xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );

            if( xHandle != NULL )
            {
                ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;

                traceCREATE_COUNTING_SEMAPHORE();
            }
            else
            {
                traceCREATE_COUNTING_SEMAPHORE_FAILED();
            }
        }
        else
        {
            configASSERT( xHandle );
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xQueueCreateCountingSemaphore( xHandle );

        return xHandle;
    }

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
                              const void * const pvItemToQueue,
                              TickType_t xTicksToWait,
                              const BaseType_t xCopyPosition )
{
    BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
    TimeOut_t xTimeOut;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );

    configASSERT( pxQueue );
    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
    {
        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
    }
    #endif

    for( ; ; )
    {
        taskENTER_CRITICAL();
        {
            /* Is there room on the queue now?  The running task must be the
             * highest priority task wanting to access the queue.  If the head item
             * in the queue is to be overwritten then it does not matter if the
             * queue is full. */
            if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
            {
                traceQUEUE_SEND( pxQueue );

                #if ( configUSE_QUEUE_SETS == 1 )
                {
                    const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;

                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

                    if( pxQueue->pxQueueSetContainer != NULL )
                    {
                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
                        {
                            /* Do not notify the queue set as an existing item
                             * was overwritten in the queue so the number of items
                             * in the queue has not changed. */
                            mtCOVERAGE_TEST_MARKER();
                        }
                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
                        {
                            /* The queue is a member of a queue set, and posting
                             * to the queue set caused a higher priority task to
                             * unblock. A context switch is required. */
                            queueYIELD_IF_USING_PREEMPTION();
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        /* If there was a task waiting for data to arrive on the
                         * queue then unblock it now. */
                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                        {
                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                            {
                                /* The unblocked task has a priority higher than
                                 * our own so yield immediately.  Yes it is ok to
                                 * do this from within the critical section - the
                                 * kernel takes care of that. */
                                queueYIELD_IF_USING_PREEMPTION();
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else if( xYieldRequired != pdFALSE )
                        {
                            /* This path is a special case that will only get
                             * executed if the task was holding multiple mutexes
                             * and the mutexes were given back in an order that is
                             * different to that in which they were taken. */
                            queueYIELD_IF_USING_PREEMPTION();
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                }
                #else /* configUSE_QUEUE_SETS */
                {
                    xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

                    /* If there was a task waiting for data to arrive on the
                     * queue then unblock it now. */
                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                    {
                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                        {
                            /* The unblocked task has a priority higher than
                             * our own so yield immediately.  Yes it is ok to do
                             * this from within the critical section - the kernel
                             * takes care of that. */
                            queueYIELD_IF_USING_PREEMPTION();
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else if( xYieldRequired != pdFALSE )
                    {
                        /* This path is a special case that will only get
                         * executed if the task was holding multiple mutexes and
                         * the mutexes were given back in an order that is
                         * different to that in which they were taken. */
                        queueYIELD_IF_USING_PREEMPTION();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #endif /* configUSE_QUEUE_SETS */

                taskEXIT_CRITICAL();

                traceRETURN_xQueueGenericSend( pdPASS );

                return pdPASS;
            }
            else
            {
                if( xTicksToWait == ( TickType_t ) 0 )
                {
                    /* The queue was full and no block time is specified (or
                     * the block time has expired) so leave now. */
                    taskEXIT_CRITICAL();

                    /* Return to the original privilege level before exiting
                     * the function. */
                    traceQUEUE_SEND_FAILED( pxQueue );
                    traceRETURN_xQueueGenericSend( errQUEUE_FULL );

                    return errQUEUE_FULL;
                }
                else if( xEntryTimeSet == pdFALSE )
                {
                    /* The queue was full and a block time was specified so
                     * configure the timeout structure. */
                    vTaskInternalSetTimeOutState( &xTimeOut );
                    xEntryTimeSet = pdTRUE;
                }
                else
                {
                    /* Entry time was already set. */
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        taskEXIT_CRITICAL();

        /* Interrupts and other tasks can send to and receive from the queue
         * now the critical section has been exited. */

        vTaskSuspendAll();
        prvLockQueue( pxQueue );

        /* Update the timeout state to see if it has expired yet. */
        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
        {
            if( prvIsQueueFull( pxQueue ) != pdFALSE )
            {
                traceBLOCKING_ON_QUEUE_SEND( pxQueue );
                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );

                /* Unlocking the queue means queue events can effect the
                 * event list. It is possible that interrupts occurring now
                 * remove this task from the event list again - but as the
                 * scheduler is suspended the task will go onto the pending
                 * ready list instead of the actual ready list. */
                prvUnlockQueue( pxQueue );

                /* Resuming the scheduler will move tasks from the pending
                 * ready list into the ready list - so it is feasible that this
                 * task is already in the ready list before it yields - in which
                 * case the yield will not cause a context switch unless there
                 * is also a higher priority task in the pending ready list. */
                if( xTaskResumeAll() == pdFALSE )
                {
                    taskYIELD_WITHIN_API();
                }
            }
            else
            {
                /* Try again. */
                prvUnlockQueue( pxQueue );
                ( void ) xTaskResumeAll();
            }
        }
        else
        {
            /* The timeout has expired. */
            prvUnlockQueue( pxQueue );
            ( void ) xTaskResumeAll();

            traceQUEUE_SEND_FAILED( pxQueue );
            traceRETURN_xQueueGenericSend( errQUEUE_FULL );

            return errQUEUE_FULL;
        }
    }
}
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
                                     const void * const pvItemToQueue,
                                     BaseType_t * const pxHigherPriorityTaskWoken,
                                     const BaseType_t xCopyPosition )
{
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition );

    configASSERT( pxQueue );
    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );

    /* RTOS ports that support interrupt nesting have the concept of a maximum
     * system call (or maximum API call) interrupt priority.  Interrupts that are
     * above the maximum system call priority are kept permanently enabled, even
     * when the RTOS kernel is in a critical section, but cannot make any calls to
     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
     * failure if a FreeRTOS API function is called from an interrupt that has been
     * assigned a priority above the configured maximum system call priority.
     * Only FreeRTOS functions that end in FromISR can be called from interrupts
     * that have been assigned a priority at or (logically) below the maximum
     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
     * safe API to ensure interrupt entry is as fast and as simple as possible.
     * More information (albeit Cortex-M specific) is provided on the following
     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

    /* Similar to xQueueGenericSend, except without blocking if there is no room
     * in the queue.  Also don't directly wake a task that was blocked on a queue
     * read, instead return a flag to say whether a context switch is required or
     * not (i.e. has a task with a higher priority than us been woken by this
     * post). */
    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
    {
        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
        {
            const int8_t cTxLock = pxQueue->cTxLock;
            const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;

            traceQUEUE_SEND_FROM_ISR( pxQueue );

            /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
             *  semaphore or mutex.  That means prvCopyDataToQueue() cannot result
             *  in a task disinheriting a priority and prvCopyDataToQueue() can be
             *  called here even though the disinherit function does not check if
             *  the scheduler is suspended before accessing the ready lists. */
            ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );

            /* The event list is not altered if the queue is locked.  This will
             * be done when the queue is unlocked later. */
            if( cTxLock == queueUNLOCKED )
            {
                #if ( configUSE_QUEUE_SETS == 1 )
                {
                    if( pxQueue->pxQueueSetContainer != NULL )
                    {
                        if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
                        {
                            /* Do not notify the queue set as an existing item
                             * was overwritten in the queue so the number of items
                             * in the queue has not changed. */
                            mtCOVERAGE_TEST_MARKER();
                        }
                        else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
                        {
                            /* The queue is a member of a queue set, and posting
                             * to the queue set caused a higher priority task to
                             * unblock.  A context switch is required. */
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                        {
                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                            {
                                /* The task waiting has a higher priority so
                                 *  record that a context switch is required. */
                                if( pxHigherPriorityTaskWoken != NULL )
                                {
                                    *pxHigherPriorityTaskWoken = pdTRUE;
                                }
                                else
                                {
                                    mtCOVERAGE_TEST_MARKER();
                                }
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                }
                #else /* configUSE_QUEUE_SETS */
                {
                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                    {
                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                        {
                            /* The task waiting has a higher priority so record that a
                             * context switch is required. */
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* Not used in this path. */
                    ( void ) uxPreviousMessagesWaiting;
                }
                #endif /* configUSE_QUEUE_SETS */
            }
            else
            {
                /* Increment the lock count so the task that unlocks the queue
                 * knows that data was posted while it was locked. */
                prvIncrementQueueTxLock( pxQueue, cTxLock );
            }

            xReturn = pdPASS;
        }
        else
        {
            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
            xReturn = errQUEUE_FULL;
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xQueueGenericSendFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
                              BaseType_t * const pxHigherPriorityTaskWoken )
{
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken );

    /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
     * item size is 0.  Don't directly wake a task that was blocked on a queue
     * read, instead return a flag to say whether a context switch is required or
     * not (i.e. has a task with a higher priority than us been woken by this
     * post). */

    configASSERT( pxQueue );

    /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
     * if the item size is not 0. */
    configASSERT( pxQueue->uxItemSize == 0 );

    /* Normally a mutex would not be given from an interrupt, especially if
     * there is a mutex holder, as priority inheritance makes no sense for an
     * interrupts, only tasks. */
    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );

    /* RTOS ports that support interrupt nesting have the concept of a maximum
     * system call (or maximum API call) interrupt priority.  Interrupts that are
     * above the maximum system call priority are kept permanently enabled, even
     * when the RTOS kernel is in a critical section, but cannot make any calls to
     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
     * failure if a FreeRTOS API function is called from an interrupt that has been
     * assigned a priority above the configured maximum system call priority.
     * Only FreeRTOS functions that end in FromISR can be called from interrupts
     * that have been assigned a priority at or (logically) below the maximum
     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
     * safe API to ensure interrupt entry is as fast and as simple as possible.
     * More information (albeit Cortex-M specific) is provided on the following
     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
    {
        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;

        /* When the queue is used to implement a semaphore no data is ever
         * moved through the queue but it is still valid to see if the queue 'has
         * space'. */
        if( uxMessagesWaiting < pxQueue->uxLength )
        {
            const int8_t cTxLock = pxQueue->cTxLock;

            traceQUEUE_SEND_FROM_ISR( pxQueue );

            /* A task can only have an inherited priority if it is a mutex
             * holder - and if there is a mutex holder then the mutex cannot be
             * given from an ISR.  As this is the ISR version of the function it
             * can be assumed there is no mutex holder and no need to determine if
             * priority disinheritance is needed.  Simply increase the count of
             * messages (semaphores) available. */
            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );

            /* The event list is not altered if the queue is locked.  This will
             * be done when the queue is unlocked later. */
            if( cTxLock == queueUNLOCKED )
            {
                #if ( configUSE_QUEUE_SETS == 1 )
                {
                    if( pxQueue->pxQueueSetContainer != NULL )
                    {
                        if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
                        {
                            /* The semaphore is a member of a queue set, and
                             * posting to the queue set caused a higher priority
                             * task to unblock.  A context switch is required. */
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                        {
                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                            {
                                /* The task waiting has a higher priority so
                                 *  record that a context switch is required. */
                                if( pxHigherPriorityTaskWoken != NULL )
                                {
                                    *pxHigherPriorityTaskWoken = pdTRUE;
                                }
                                else
                                {
                                    mtCOVERAGE_TEST_MARKER();
                                }
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                }
                #else /* configUSE_QUEUE_SETS */
                {
                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                    {
                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                        {
                            /* The task waiting has a higher priority so record that a
                             * context switch is required. */
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #endif /* configUSE_QUEUE_SETS */
            }
            else
            {
                /* Increment the lock count so the task that unlocks the queue
                 * knows that data was posted while it was locked. */
                prvIncrementQueueTxLock( pxQueue, cTxLock );
            }

            xReturn = pdPASS;
        }
        else
        {
            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
            xReturn = errQUEUE_FULL;
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xQueueGiveFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue,
                          void * const pvBuffer,
                          TickType_t xTicksToWait )
{
    BaseType_t xEntryTimeSet = pdFALSE;
    TimeOut_t xTimeOut;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait );

    /* Check the pointer is not NULL. */
    configASSERT( ( pxQueue ) );

    /* The buffer into which data is received can only be NULL if the data size
     * is zero (so no data is copied into the buffer). */
    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );

    /* Cannot block if the scheduler is suspended. */
    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
    {
        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
    }
    #endif

    for( ; ; )
    {
        taskENTER_CRITICAL();
        {
            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;

            /* Is there data in the queue now?  To be running the calling task
             * must be the highest priority task wanting to access the queue. */
            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
            {
                /* Data available, remove one item. */
                prvCopyDataFromQueue( pxQueue, pvBuffer );
                traceQUEUE_RECEIVE( pxQueue );
                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );

                /* There is now space in the queue, were any tasks waiting to
                 * post to the queue?  If so, unblock the highest priority waiting
                 * task. */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        queueYIELD_IF_USING_PREEMPTION();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                taskEXIT_CRITICAL();

                traceRETURN_xQueueReceive( pdPASS );

                return pdPASS;
            }
            else
            {
                if( xTicksToWait == ( TickType_t ) 0 )
                {
                    /* The queue was empty and no block time is specified (or
                     * the block time has expired) so leave now. */
                    taskEXIT_CRITICAL();

                    traceQUEUE_RECEIVE_FAILED( pxQueue );
                    traceRETURN_xQueueReceive( errQUEUE_EMPTY );

                    return errQUEUE_EMPTY;
                }
                else if( xEntryTimeSet == pdFALSE )
                {
                    /* The queue was empty and a block time was specified so
                     * configure the timeout structure. */
                    vTaskInternalSetTimeOutState( &xTimeOut );
                    xEntryTimeSet = pdTRUE;
                }
                else
                {
                    /* Entry time was already set. */
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        taskEXIT_CRITICAL();

        /* Interrupts and other tasks can send to and receive from the queue
         * now the critical section has been exited. */

        vTaskSuspendAll();
        prvLockQueue( pxQueue );

        /* Update the timeout state to see if it has expired yet. */
        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
        {
            /* The timeout has not expired.  If the queue is still empty place
             * the task on the list of tasks waiting to receive from the queue. */
            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
                prvUnlockQueue( pxQueue );

                if( xTaskResumeAll() == pdFALSE )
                {
                    taskYIELD_WITHIN_API();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* The queue contains data again.  Loop back to try and read the
                 * data. */
                prvUnlockQueue( pxQueue );
                ( void ) xTaskResumeAll();
            }
        }
        else
        {
            /* Timed out.  If there is no data in the queue exit, otherwise loop
             * back and attempt to read the data. */
            prvUnlockQueue( pxQueue );
            ( void ) xTaskResumeAll();

            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                traceQUEUE_RECEIVE_FAILED( pxQueue );
                traceRETURN_xQueueReceive( errQUEUE_EMPTY );

                return errQUEUE_EMPTY;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
    }
}
/*-----------------------------------------------------------*/

BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                                TickType_t xTicksToWait )
{
    BaseType_t xEntryTimeSet = pdFALSE;
    TimeOut_t xTimeOut;
    Queue_t * const pxQueue = xQueue;

    #if ( configUSE_MUTEXES == 1 )
        BaseType_t xInheritanceOccurred = pdFALSE;
    #endif

    traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait );

    /* Check the queue pointer is not NULL. */
    configASSERT( ( pxQueue ) );

    /* Check this really is a semaphore, in which case the item size will be
     * 0. */
    configASSERT( pxQueue->uxItemSize == 0 );

    /* Cannot block if the scheduler is suspended. */
    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
    {
        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
    }
    #endif

    for( ; ; )
    {
        taskENTER_CRITICAL();
        {
            /* Semaphores are queues with an item size of 0, and where the
             * number of messages in the queue is the semaphore's count value. */
            const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;

            /* Is there data in the queue now?  To be running the calling task
             * must be the highest priority task wanting to access the queue. */
            if( uxSemaphoreCount > ( UBaseType_t ) 0 )
            {
                traceQUEUE_RECEIVE( pxQueue );

                /* Semaphores are queues with a data size of zero and where the
                 * messages waiting is the semaphore's count.  Reduce the count. */
                pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 );

                #if ( configUSE_MUTEXES == 1 )
                {
                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
                    {
                        /* Record the information required to implement
                         * priority inheritance should it become necessary. */
                        pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #endif /* configUSE_MUTEXES */

                /* Check to see if other tasks are blocked waiting to give the
                 * semaphore, and if so, unblock the highest priority such task. */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        queueYIELD_IF_USING_PREEMPTION();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                taskEXIT_CRITICAL();

                traceRETURN_xQueueSemaphoreTake( pdPASS );

                return pdPASS;
            }
            else
            {
                if( xTicksToWait == ( TickType_t ) 0 )
                {
                    /* The semaphore count was 0 and no block time is specified
                     * (or the block time has expired) so exit now. */
                    taskEXIT_CRITICAL();

                    traceQUEUE_RECEIVE_FAILED( pxQueue );
                    traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );

                    return errQUEUE_EMPTY;
                }
                else if( xEntryTimeSet == pdFALSE )
                {
                    /* The semaphore count was 0 and a block time was specified
                     * so configure the timeout structure ready to block. */
                    vTaskInternalSetTimeOutState( &xTimeOut );
                    xEntryTimeSet = pdTRUE;
                }
                else
                {
                    /* Entry time was already set. */
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        taskEXIT_CRITICAL();

        /* Interrupts and other tasks can give to and take from the semaphore
         * now the critical section has been exited. */

        vTaskSuspendAll();
        prvLockQueue( pxQueue );

        /* Update the timeout state to see if it has expired yet. */
        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
        {
            /* A block time is specified and not expired.  If the semaphore
             * count is 0 then enter the Blocked state to wait for a semaphore to
             * become available.  As semaphores are implemented with queues the
             * queue being empty is equivalent to the semaphore count being 0. */
            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );

                #if ( configUSE_MUTEXES == 1 )
                {
                    if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
                    {
                        taskENTER_CRITICAL();
                        {
                            xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
                        }
                        taskEXIT_CRITICAL();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #endif /* if ( configUSE_MUTEXES == 1 ) */

                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
                prvUnlockQueue( pxQueue );

                if( xTaskResumeAll() == pdFALSE )
                {
                    taskYIELD_WITHIN_API();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* There was no timeout and the semaphore count was not 0, so
                 * attempt to take the semaphore again. */
                prvUnlockQueue( pxQueue );
                ( void ) xTaskResumeAll();
            }
        }
        else
        {
            /* Timed out. */
            prvUnlockQueue( pxQueue );
            ( void ) xTaskResumeAll();

            /* If the semaphore count is 0 exit now as the timeout has
             * expired.  Otherwise return to attempt to take the semaphore that is
             * known to be available.  As semaphores are implemented by queues the
             * queue being empty is equivalent to the semaphore count being 0. */
            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                #if ( configUSE_MUTEXES == 1 )
                {
                    /* xInheritanceOccurred could only have be set if
                     * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
                     * test the mutex type again to check it is actually a mutex. */
                    if( xInheritanceOccurred != pdFALSE )
                    {
                        taskENTER_CRITICAL();
                        {
                            UBaseType_t uxHighestWaitingPriority;

                            /* This task blocking on the mutex caused another
                             * task to inherit this task's priority.  Now this task
                             * has timed out the priority should be disinherited
                             * again, but only as low as the next highest priority
                             * task that is waiting for the same mutex. */
                            uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );

                            /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority
                             * parameter to index pxReadyTasksLists when adding the task holding
                             * mutex to the ready list for its new priority. Coverity thinks that
                             * it can result in out-of-bounds access which is not true because
                             * uxHighestWaitingPriority, as returned by prvGetDisinheritPriorityAfterTimeout,
                             * is capped at ( configMAX_PRIORITIES - 1 ). */
                            /* coverity[overrun] */
                            vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
                        }
                        taskEXIT_CRITICAL();
                    }
                }
                #endif /* configUSE_MUTEXES */

                traceQUEUE_RECEIVE_FAILED( pxQueue );
                traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY );

                return errQUEUE_EMPTY;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
    }
}
/*-----------------------------------------------------------*/

BaseType_t xQueuePeek( QueueHandle_t xQueue,
                       void * const pvBuffer,
                       TickType_t xTicksToWait )
{
    BaseType_t xEntryTimeSet = pdFALSE;
    TimeOut_t xTimeOut;
    int8_t * pcOriginalReadPosition;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait );

    /* Check the pointer is not NULL. */
    configASSERT( ( pxQueue ) );

    /* The buffer into which data is received can only be NULL if the data size
     * is zero (so no data is copied into the buffer. */
    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );

    /* Cannot block if the scheduler is suspended. */
    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
    {
        configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
    }
    #endif

    for( ; ; )
    {
        taskENTER_CRITICAL();
        {
            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;

            /* Is there data in the queue now?  To be running the calling task
             * must be the highest priority task wanting to access the queue. */
            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
            {
                /* Remember the read position so it can be reset after the data
                 * is read from the queue as this function is only peeking the
                 * data, not removing it. */
                pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;

                prvCopyDataFromQueue( pxQueue, pvBuffer );
                traceQUEUE_PEEK( pxQueue );

                /* The data is not being removed, so reset the read pointer. */
                pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;

                /* The data is being left in the queue, so see if there are
                 * any other tasks waiting for the data. */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                    {
                        /* The task waiting has a higher priority than this task. */
                        queueYIELD_IF_USING_PREEMPTION();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                taskEXIT_CRITICAL();

                traceRETURN_xQueuePeek( pdPASS );

                return pdPASS;
            }
            else
            {
                if( xTicksToWait == ( TickType_t ) 0 )
                {
                    /* The queue was empty and no block time is specified (or
                     * the block time has expired) so leave now. */
                    taskEXIT_CRITICAL();

                    traceQUEUE_PEEK_FAILED( pxQueue );
                    traceRETURN_xQueuePeek( errQUEUE_EMPTY );

                    return errQUEUE_EMPTY;
                }
                else if( xEntryTimeSet == pdFALSE )
                {
                    /* The queue was empty and a block time was specified so
                     * configure the timeout structure ready to enter the blocked
                     * state. */
                    vTaskInternalSetTimeOutState( &xTimeOut );
                    xEntryTimeSet = pdTRUE;
                }
                else
                {
                    /* Entry time was already set. */
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        taskEXIT_CRITICAL();

        /* Interrupts and other tasks can send to and receive from the queue
         * now that the critical section has been exited. */

        vTaskSuspendAll();
        prvLockQueue( pxQueue );

        /* Update the timeout state to see if it has expired yet. */
        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
        {
            /* Timeout has not expired yet, check to see if there is data in the
            * queue now, and if not enter the Blocked state to wait for data. */
            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
                prvUnlockQueue( pxQueue );

                if( xTaskResumeAll() == pdFALSE )
                {
                    taskYIELD_WITHIN_API();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* There is data in the queue now, so don't enter the blocked
                 * state, instead return to try and obtain the data. */
                prvUnlockQueue( pxQueue );
                ( void ) xTaskResumeAll();
            }
        }
        else
        {
            /* The timeout has expired.  If there is still no data in the queue
             * exit, otherwise go back and try to read the data again. */
            prvUnlockQueue( pxQueue );
            ( void ) xTaskResumeAll();

            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
            {
                traceQUEUE_PEEK_FAILED( pxQueue );
                traceRETURN_xQueuePeek( errQUEUE_EMPTY );

                return errQUEUE_EMPTY;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
    }
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
                                 void * const pvBuffer,
                                 BaseType_t * const pxHigherPriorityTaskWoken )
{
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken );

    configASSERT( pxQueue );
    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );

    /* RTOS ports that support interrupt nesting have the concept of a maximum
     * system call (or maximum API call) interrupt priority.  Interrupts that are
     * above the maximum system call priority are kept permanently enabled, even
     * when the RTOS kernel is in a critical section, but cannot make any calls to
     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
     * failure if a FreeRTOS API function is called from an interrupt that has been
     * assigned a priority above the configured maximum system call priority.
     * Only FreeRTOS functions that end in FromISR can be called from interrupts
     * that have been assigned a priority at or (logically) below the maximum
     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
     * safe API to ensure interrupt entry is as fast and as simple as possible.
     * More information (albeit Cortex-M specific) is provided on the following
     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
    {
        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;

        /* Cannot block in an ISR, so check there is data available. */
        if( uxMessagesWaiting > ( UBaseType_t ) 0 )
        {
            const int8_t cRxLock = pxQueue->cRxLock;

            traceQUEUE_RECEIVE_FROM_ISR( pxQueue );

            prvCopyDataFromQueue( pxQueue, pvBuffer );
            pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 );

            /* If the queue is locked the event list will not be modified.
             * Instead update the lock count so the task that unlocks the queue
             * will know that an ISR has removed data while the queue was
             * locked. */
            if( cRxLock == queueUNLOCKED )
            {
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        /* The task waiting has a higher priority than us so
                         * force a context switch. */
                        if( pxHigherPriorityTaskWoken != NULL )
                        {
                            *pxHigherPriorityTaskWoken = pdTRUE;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* Increment the lock count so the task that unlocks the queue
                 * knows that data was removed while it was locked. */
                prvIncrementQueueRxLock( pxQueue, cRxLock );
            }

            xReturn = pdPASS;
        }
        else
        {
            xReturn = pdFAIL;
            traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xQueueReceiveFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
                              void * const pvBuffer )
{
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;
    int8_t * pcOriginalReadPosition;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueuePeekFromISR( xQueue, pvBuffer );

    configASSERT( pxQueue );
    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */

    /* RTOS ports that support interrupt nesting have the concept of a maximum
     * system call (or maximum API call) interrupt priority.  Interrupts that are
     * above the maximum system call priority are kept permanently enabled, even
     * when the RTOS kernel is in a critical section, but cannot make any calls to
     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
     * failure if a FreeRTOS API function is called from an interrupt that has been
     * assigned a priority above the configured maximum system call priority.
     * Only FreeRTOS functions that end in FromISR can be called from interrupts
     * that have been assigned a priority at or (logically) below the maximum
     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
     * safe API to ensure interrupt entry is as fast and as simple as possible.
     * More information (albeit Cortex-M specific) is provided on the following
     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
    {
        /* Cannot block in an ISR, so check there is data available. */
        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
        {
            traceQUEUE_PEEK_FROM_ISR( pxQueue );

            /* Remember the read position so it can be reset as nothing is
             * actually being removed from the queue. */
            pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
            prvCopyDataFromQueue( pxQueue, pvBuffer );
            pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;

            xReturn = pdPASS;
        }
        else
        {
            xReturn = pdFAIL;
            traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xQueuePeekFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
{
    UBaseType_t uxReturn;

    traceENTER_uxQueueMessagesWaiting( xQueue );

    configASSERT( xQueue );

    taskENTER_CRITICAL();
    {
        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
    }
    taskEXIT_CRITICAL();

    traceRETURN_uxQueueMessagesWaiting( uxReturn );

    return uxReturn;
}
/*-----------------------------------------------------------*/

UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
{
    UBaseType_t uxReturn;
    Queue_t * const pxQueue = xQueue;

    traceENTER_uxQueueSpacesAvailable( xQueue );

    configASSERT( pxQueue );

    taskENTER_CRITICAL();
    {
        uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting );
    }
    taskEXIT_CRITICAL();

    traceRETURN_uxQueueSpacesAvailable( uxReturn );

    return uxReturn;
}
/*-----------------------------------------------------------*/

UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
{
    UBaseType_t uxReturn;
    Queue_t * const pxQueue = xQueue;

    traceENTER_uxQueueMessagesWaitingFromISR( xQueue );

    configASSERT( pxQueue );
    uxReturn = pxQueue->uxMessagesWaiting;

    traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn );

    return uxReturn;
}
/*-----------------------------------------------------------*/

void vQueueDelete( QueueHandle_t xQueue )
{
    Queue_t * const pxQueue = xQueue;

    traceENTER_vQueueDelete( xQueue );

    configASSERT( pxQueue );
    traceQUEUE_DELETE( pxQueue );

    #if ( configQUEUE_REGISTRY_SIZE > 0 )
    {
        vQueueUnregisterQueue( pxQueue );
    }
    #endif

    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
    {
        /* The queue can only have been allocated dynamically - free it
         * again. */
        vPortFree( pxQueue );
    }
    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
    {
        /* The queue could have been allocated statically or dynamically, so
         * check before attempting to free the memory. */
        if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
        {
            vPortFree( pxQueue );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */
    {
        /* The queue must have been statically allocated, so is not going to be
         * deleted.  Avoid compiler warnings about the unused parameter. */
        ( void ) pxQueue;
    }
    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */

    traceRETURN_vQueueDelete();
}
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
    {
        traceENTER_uxQueueGetQueueNumber( xQueue );

        traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber );

        return ( ( Queue_t * ) xQueue )->uxQueueNumber;
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    void vQueueSetQueueNumber( QueueHandle_t xQueue,
                               UBaseType_t uxQueueNumber )
    {
        traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber );

        ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;

        traceRETURN_vQueueSetQueueNumber();
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
    {
        traceENTER_ucQueueGetQueueType( xQueue );

        traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType );

        return ( ( Queue_t * ) xQueue )->ucQueueType;
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
{
    traceENTER_uxQueueGetQueueItemSize( xQueue );

    traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize );

    return ( ( Queue_t * ) xQueue )->uxItemSize;
}
/*-----------------------------------------------------------*/

UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */
{
    traceENTER_uxQueueGetQueueLength( xQueue );

    traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength );

    return ( ( Queue_t * ) xQueue )->uxLength;
}
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
    {
        UBaseType_t uxHighestPriorityOfWaitingTasks;

        /* If a task waiting for a mutex causes the mutex holder to inherit a
         * priority, but the waiting task times out, then the holder should
         * disinherit the priority - but only down to the highest priority of any
         * other tasks that are waiting for the same mutex.  For this purpose,
         * return the priority of the highest priority task that is waiting for the
         * mutex. */
        if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
        {
            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) );
        }
        else
        {
            uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
        }

        return uxHighestPriorityOfWaitingTasks;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
                                      const void * pvItemToQueue,
                                      const BaseType_t xPosition )
{
    BaseType_t xReturn = pdFALSE;
    UBaseType_t uxMessagesWaiting;

    /* This function is called from a critical section. */

    uxMessagesWaiting = pxQueue->uxMessagesWaiting;

    if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
    {
        #if ( configUSE_MUTEXES == 1 )
        {
            if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
            {
                /* The mutex is no longer being held. */
                xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
                pxQueue->u.xSemaphore.xMutexHolder = NULL;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* configUSE_MUTEXES */
    }
    else if( xPosition == queueSEND_TO_BACK )
    {
        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
        pxQueue->pcWriteTo += pxQueue->uxItemSize;

        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )
        {
            pxQueue->pcWriteTo = pxQueue->pcHead;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize );
        pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;

        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead )
        {
            pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        if( xPosition == queueOVERWRITE )
        {
            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
            {
                /* An item is not being added but overwritten, so subtract
                 * one from the recorded number of items in the queue so when
                 * one is added again below the number of recorded items remains
                 * correct. */
                --uxMessagesWaiting;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }

    pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 );

    return xReturn;
}
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue,
                                  void * const pvBuffer )
{
    if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
    {
        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;

        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
        {
            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize );
    }
}
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */

    /* The lock counts contains the number of extra data items placed or
     * removed from the queue while the queue was locked.  When a queue is
     * locked items can be added or removed, but the event lists cannot be
     * updated. */
    taskENTER_CRITICAL();
    {
        int8_t cTxLock = pxQueue->cTxLock;

        /* See if data was added to the queue while it was locked. */
        while( cTxLock > queueLOCKED_UNMODIFIED )
        {
            /* Data was posted while the queue was locked.  Are any tasks
             * blocked waiting for data to become available? */
            #if ( configUSE_QUEUE_SETS == 1 )
            {
                if( pxQueue->pxQueueSetContainer != NULL )
                {
                    if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
                    {
                        /* The queue is a member of a queue set, and posting to
                         * the queue set caused a higher priority task to unblock.
                         * A context switch is required. */
                        vTaskMissedYield();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    /* Tasks that are removed from the event list will get
                     * added to the pending ready list as the scheduler is still
                     * suspended. */
                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                    {
                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                        {
                            /* The task waiting has a higher priority so record that a
                             * context switch is required. */
                            vTaskMissedYield();
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    else
                    {
                        break;
                    }
                }
            }
            #else /* configUSE_QUEUE_SETS */
            {
                /* Tasks that are removed from the event list will get added to
                 * the pending ready list as the scheduler is still suspended. */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                    {
                        /* The task waiting has a higher priority so record that
                         * a context switch is required. */
                        vTaskMissedYield();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    break;
                }
            }
            #endif /* configUSE_QUEUE_SETS */

            --cTxLock;
        }

        pxQueue->cTxLock = queueUNLOCKED;
    }
    taskEXIT_CRITICAL();

    /* Do the same for the Rx lock. */
    taskENTER_CRITICAL();
    {
        int8_t cRxLock = pxQueue->cRxLock;

        while( cRxLock > queueLOCKED_UNMODIFIED )
        {
            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
            {
                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                {
                    vTaskMissedYield();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                --cRxLock;
            }
            else
            {
                break;
            }
        }

        pxQueue->cRxLock = queueUNLOCKED;
    }
    taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
{
    BaseType_t xReturn;

    taskENTER_CRITICAL();
    {
        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
        {
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }
    }
    taskEXIT_CRITICAL();

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
{
    BaseType_t xReturn;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueIsQueueEmptyFromISR( xQueue );

    configASSERT( pxQueue );

    if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
    {
        xReturn = pdTRUE;
    }
    else
    {
        xReturn = pdFALSE;
    }

    traceRETURN_xQueueIsQueueEmptyFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
{
    BaseType_t xReturn;

    taskENTER_CRITICAL();
    {
        if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
        {
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }
    }
    taskEXIT_CRITICAL();

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
{
    BaseType_t xReturn;
    Queue_t * const pxQueue = xQueue;

    traceENTER_xQueueIsQueueFullFromISR( xQueue );

    configASSERT( pxQueue );

    if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
    {
        xReturn = pdTRUE;
    }
    else
    {
        xReturn = pdFALSE;
    }

    traceRETURN_xQueueIsQueueFullFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

#if ( configUSE_CO_ROUTINES == 1 )

    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
                             const void * pvItemToQueue,
                             TickType_t xTicksToWait )
    {
        BaseType_t xReturn;
        Queue_t * const pxQueue = xQueue;

        traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait );

        /* If the queue is already full we may have to block.  A critical section
         * is required to prevent an interrupt removing something from the queue
         * between the check to see if the queue is full and blocking on the queue. */
        portDISABLE_INTERRUPTS();
        {
            if( prvIsQueueFull( pxQueue ) != pdFALSE )
            {
                /* The queue is full - do we want to block or just leave without
                 * posting? */
                if( xTicksToWait > ( TickType_t ) 0 )
                {
                    /* As this is called from a coroutine we cannot block directly, but
                     * return indicating that we need to block. */
                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
                    portENABLE_INTERRUPTS();
                    return errQUEUE_BLOCKED;
                }
                else
                {
                    portENABLE_INTERRUPTS();
                    return errQUEUE_FULL;
                }
            }
        }
        portENABLE_INTERRUPTS();

        portDISABLE_INTERRUPTS();
        {
            if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
            {
                /* There is room in the queue, copy the data into the queue. */
                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
                xReturn = pdPASS;

                /* Were any co-routines waiting for data to become available? */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                {
                    /* In this instance the co-routine could be placed directly
                     * into the ready list as we are within a critical section.
                     * Instead the same pending ready list mechanism is used as if
                     * the event were caused from within an interrupt. */
                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                    {
                        /* The co-routine waiting has a higher priority so record
                         * that a yield might be appropriate. */
                        xReturn = errQUEUE_YIELD;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                xReturn = errQUEUE_FULL;
            }
        }
        portENABLE_INTERRUPTS();

        traceRETURN_xQueueCRSend( xReturn );

        return xReturn;
    }

#endif /* configUSE_CO_ROUTINES */
/*-----------------------------------------------------------*/

#if ( configUSE_CO_ROUTINES == 1 )

    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
                                void * pvBuffer,
                                TickType_t xTicksToWait )
    {
        BaseType_t xReturn;
        Queue_t * const pxQueue = xQueue;

        traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait );

        /* If the queue is already empty we may have to block.  A critical section
         * is required to prevent an interrupt adding something to the queue
         * between the check to see if the queue is empty and blocking on the queue. */
        portDISABLE_INTERRUPTS();
        {
            if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
            {
                /* There are no messages in the queue, do we want to block or just
                 * leave with nothing? */
                if( xTicksToWait > ( TickType_t ) 0 )
                {
                    /* As this is a co-routine we cannot block directly, but return
                     * indicating that we need to block. */
                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
                    portENABLE_INTERRUPTS();
                    return errQUEUE_BLOCKED;
                }
                else
                {
                    portENABLE_INTERRUPTS();
                    return errQUEUE_FULL;
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        portENABLE_INTERRUPTS();

        portDISABLE_INTERRUPTS();
        {
            if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
            {
                /* Data is available from the queue. */
                pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;

                if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
                {
                    pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                --( pxQueue->uxMessagesWaiting );
                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );

                xReturn = pdPASS;

                /* Were any co-routines waiting for space to become available? */
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    /* In this instance the co-routine could be placed directly
                     * into the ready list as we are within a critical section.
                     * Instead the same pending ready list mechanism is used as if
                     * the event were caused from within an interrupt. */
                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        xReturn = errQUEUE_YIELD;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                xReturn = pdFAIL;
            }
        }
        portENABLE_INTERRUPTS();

        traceRETURN_xQueueCRReceive( xReturn );

        return xReturn;
    }

#endif /* configUSE_CO_ROUTINES */
/*-----------------------------------------------------------*/

#if ( configUSE_CO_ROUTINES == 1 )

    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
                                    const void * pvItemToQueue,
                                    BaseType_t xCoRoutinePreviouslyWoken )
    {
        Queue_t * const pxQueue = xQueue;

        traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken );

        /* Cannot block within an ISR so if there is no space on the queue then
         * exit without doing anything. */
        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
        {
            prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );

            /* We only want to wake one co-routine per ISR, so check that a
             * co-routine has not already been woken. */
            if( xCoRoutinePreviouslyWoken == pdFALSE )
            {
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
                {
                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
                    {
                        return pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken );

        return xCoRoutinePreviouslyWoken;
    }

#endif /* configUSE_CO_ROUTINES */
/*-----------------------------------------------------------*/

#if ( configUSE_CO_ROUTINES == 1 )

    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
                                       void * pvBuffer,
                                       BaseType_t * pxCoRoutineWoken )
    {
        BaseType_t xReturn;
        Queue_t * const pxQueue = xQueue;

        traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken );

        /* We cannot block from an ISR, so check there is data available. If
         * not then just leave without doing anything. */
        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
        {
            /* Copy the data from the queue. */
            pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;

            if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
            {
                pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            --( pxQueue->uxMessagesWaiting );
            ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );

            if( ( *pxCoRoutineWoken ) == pdFALSE )
            {
                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
                {
                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
                    {
                        *pxCoRoutineWoken = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            xReturn = pdPASS;
        }
        else
        {
            xReturn = pdFAIL;
        }

        traceRETURN_xQueueCRReceiveFromISR( xReturn );

        return xReturn;
    }

#endif /* configUSE_CO_ROUTINES */
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

    void vQueueAddToRegistry( QueueHandle_t xQueue,
                              const char * pcQueueName )
    {
        UBaseType_t ux;
        QueueRegistryItem_t * pxEntryToWrite = NULL;

        traceENTER_vQueueAddToRegistry( xQueue, pcQueueName );

        configASSERT( xQueue );

        if( pcQueueName != NULL )
        {
            /* See if there is an empty space in the registry.  A NULL name denotes
             * a free slot. */
            for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
            {
                /* Replace an existing entry if the queue is already in the registry. */
                if( xQueue == xQueueRegistry[ ux ].xHandle )
                {
                    pxEntryToWrite = &( xQueueRegistry[ ux ] );
                    break;
                }
                /* Otherwise, store in the next empty location */
                else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) )
                {
                    pxEntryToWrite = &( xQueueRegistry[ ux ] );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }

        if( pxEntryToWrite != NULL )
        {
            /* Store the information on this queue. */
            pxEntryToWrite->pcQueueName = pcQueueName;
            pxEntryToWrite->xHandle = xQueue;

            traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
        }

        traceRETURN_vQueueAddToRegistry();
    }

#endif /* configQUEUE_REGISTRY_SIZE */
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

    const char * pcQueueGetName( QueueHandle_t xQueue )
    {
        UBaseType_t ux;
        const char * pcReturn = NULL;

        traceENTER_pcQueueGetName( xQueue );

        configASSERT( xQueue );

        /* Note there is nothing here to protect against another task adding or
         * removing entries from the registry while it is being searched. */

        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
        {
            if( xQueueRegistry[ ux ].xHandle == xQueue )
            {
                pcReturn = xQueueRegistry[ ux ].pcQueueName;
                break;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }

        traceRETURN_pcQueueGetName( pcReturn );

        return pcReturn;
    }

#endif /* configQUEUE_REGISTRY_SIZE */
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

    void vQueueUnregisterQueue( QueueHandle_t xQueue )
    {
        UBaseType_t ux;

        traceENTER_vQueueUnregisterQueue( xQueue );

        configASSERT( xQueue );

        /* See if the handle of the queue being unregistered in actually in the
         * registry. */
        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
        {
            if( xQueueRegistry[ ux ].xHandle == xQueue )
            {
                /* Set the name to NULL to show that this slot if free again. */
                xQueueRegistry[ ux ].pcQueueName = NULL;

                /* Set the handle to NULL to ensure the same queue handle cannot
                 * appear in the registry twice if it is added, removed, then
                 * added again. */
                xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
                break;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }

        traceRETURN_vQueueUnregisterQueue();
    }

#endif /* configQUEUE_REGISTRY_SIZE */
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

    void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
                                         TickType_t xTicksToWait,
                                         const BaseType_t xWaitIndefinitely )
    {
        Queue_t * const pxQueue = xQueue;

        traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely );

        /* This function should not be called by application code hence the
         * 'Restricted' in its name.  It is not part of the public API.  It is
         * designed for use by kernel code, and has special calling requirements.
         * It can result in vListInsert() being called on a list that can only
         * possibly ever have one item in it, so the list will be fast, but even
         * so it should be called with the scheduler locked and not from a critical
         * section. */

        /* Only do anything if there are no messages in the queue.  This function
         *  will not actually cause the task to block, just place it on a blocked
         *  list.  It will not block until the scheduler is unlocked - at which
         *  time a yield will be performed.  If an item is added to the queue while
         *  the queue is locked, and the calling task blocks on the queue, then the
         *  calling task will be immediately unblocked when the queue is unlocked. */
        prvLockQueue( pxQueue );

        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
        {
            /* There is nothing in the queue, block for the specified period. */
            vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        prvUnlockQueue( pxQueue );

        traceRETURN_vQueueWaitForMessageRestricted();
    }

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )

    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
    {
        QueueSetHandle_t pxQueue;

        traceENTER_xQueueCreateSet( uxEventQueueLength );

        pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );

        traceRETURN_xQueueCreateSet( pxQueue );

        return pxQueue;
    }

#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/

#if ( configUSE_QUEUE_SETS == 1 )

    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                               QueueSetHandle_t xQueueSet )
    {
        BaseType_t xReturn;

        traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet );

        taskENTER_CRITICAL();
        {
            if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
            {
                /* Cannot add a queue/semaphore to more than one queue set. */
                xReturn = pdFAIL;
            }
            else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
            {
                /* Cannot add a queue/semaphore to a queue set if there are already
                 * items in the queue/semaphore. */
                xReturn = pdFAIL;
            }
            else
            {
                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
                xReturn = pdPASS;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xQueueAddToSet( xReturn );

        return xReturn;
    }

#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/

#if ( configUSE_QUEUE_SETS == 1 )

    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
                                    QueueSetHandle_t xQueueSet )
    {
        BaseType_t xReturn;
        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;

        traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );

        if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
        {
            /* The queue was not a member of the set. */
            xReturn = pdFAIL;
        }
        else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
        {
            /* It is dangerous to remove a queue from a set when the queue is
             * not empty because the queue set will still hold pending events for
             * the queue. */
            xReturn = pdFAIL;
        }
        else
        {
            taskENTER_CRITICAL();
            {
                /* The queue is no longer contained in the set. */
                pxQueueOrSemaphore->pxQueueSetContainer = NULL;
            }
            taskEXIT_CRITICAL();
            xReturn = pdPASS;
        }

        traceRETURN_xQueueRemoveFromSet( xReturn );

        return xReturn;
    }

#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/

#if ( configUSE_QUEUE_SETS == 1 )

    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
                                                TickType_t const xTicksToWait )
    {
        QueueSetMemberHandle_t xReturn = NULL;

        traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait );

        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait );

        traceRETURN_xQueueSelectFromSet( xReturn );

        return xReturn;
    }

#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/

#if ( configUSE_QUEUE_SETS == 1 )

    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
    {
        QueueSetMemberHandle_t xReturn = NULL;

        traceENTER_xQueueSelectFromSetFromISR( xQueueSet );

        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL );

        traceRETURN_xQueueSelectFromSetFromISR( xReturn );

        return xReturn;
    }

#endif /* configUSE_QUEUE_SETS */
/*-----------------------------------------------------------*/

#if ( configUSE_QUEUE_SETS == 1 )

    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
    {
        Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer;
        BaseType_t xReturn = pdFALSE;

        /* This function must be called form a critical section. */

        /* The following line is not reachable in unit tests because every call
         * to prvNotifyQueueSetContainer is preceded by a check that
         * pxQueueSetContainer != NULL */
        configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */
        configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );

        if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
        {
            const int8_t cTxLock = pxQueueSetContainer->cTxLock;

            traceQUEUE_SET_SEND( pxQueueSetContainer );

            /* The data copied is the handle of the queue that contains data. */
            xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );

            if( cTxLock == queueUNLOCKED )
            {
                if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
                {
                    if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
                    {
                        /* The task waiting has a higher priority. */
                        xReturn = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock );
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        return xReturn;
    }

#endif /* configUSE_QUEUE_SETS */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/* Standard includes. */
#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers.  That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "stream_buffer.h"

#if ( configUSE_TASK_NOTIFICATIONS != 1 )
    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
#endif

#if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 )
    #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c
#endif

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
 * for the header files above, but not in this file, in order to generate the
 * correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* This entire source file will be skipped if the application is not configured
 * to include stream buffer functionality. This #if is closed at the very bottom
 * of this file. If you want to include stream buffers then ensure
 * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
#if ( configUSE_STREAM_BUFFERS == 1 )

/* If the user has not provided application specific Rx notification macros,
 * or #defined the notification macros away, then provide default implementations
 * that uses task notifications. */
    #ifndef sbRECEIVE_COMPLETED
        #define sbRECEIVE_COMPLETED( pxStreamBuffer )                                 \
    do                                                                                \
    {                                                                                 \
        vTaskSuspendAll();                                                            \
        {                                                                             \
            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                      \
            {                                                                         \
                ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToSend,  \
                                             ( pxStreamBuffer )->uxNotificationIndex, \
                                             ( uint32_t ) 0,                          \
                                             eNoAction );                             \
                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                        \
            }                                                                         \
        }                                                                             \
        ( void ) xTaskResumeAll();                                                    \
    } while( 0 )
    #endif /* sbRECEIVE_COMPLETED */

/* If user has provided a per-instance receive complete callback, then
 * invoke the callback else use the receive complete macro which is provided by default for all instances.
 */
    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        #define prvRECEIVE_COMPLETED( pxStreamBuffer )                                           \
    do {                                                                                         \
        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                             \
        {                                                                                        \
            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
        }                                                                                        \
        else                                                                                     \
        {                                                                                        \
            sbRECEIVE_COMPLETED( ( pxStreamBuffer ) );                                           \
        }                                                                                        \
    } while( 0 )
    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
        #define prvRECEIVE_COMPLETED( pxStreamBuffer )    sbRECEIVE_COMPLETED( ( pxStreamBuffer ) )
    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */

    #ifndef sbRECEIVE_COMPLETED_FROM_ISR
        #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                \
                                              pxHigherPriorityTaskWoken )                    \
    do {                                                                                     \
        UBaseType_t uxSavedInterruptStatus;                                                  \
                                                                                             \
        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                              \
        {                                                                                    \
            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                             \
            {                                                                                \
                ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,  \
                                                    ( pxStreamBuffer )->uxNotificationIndex, \
                                                    ( uint32_t ) 0,                          \
                                                    eNoAction,                               \
                                                    ( pxHigherPriorityTaskWoken ) );         \
                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                               \
            }                                                                                \
        }                                                                                    \
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                \
    } while( 0 )
    #endif /* sbRECEIVE_COMPLETED_FROM_ISR */

    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                                                           \
                                               pxHigherPriorityTaskWoken )                                               \
    do {                                                                                                                 \
        if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL )                                                     \
        {                                                                                                                \
            ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
        }                                                                                                                \
        else                                                                                                             \
        {                                                                                                                \
            sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                           \
        }                                                                                                                \
    } while( 0 )
    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
        #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
    sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */

/* If the user has not provided an application specific Tx notification macro,
 * or #defined the notification macro away, then provide a default
 * implementation that uses task notifications.
 */
    #ifndef sbSEND_COMPLETED
        #define sbSEND_COMPLETED( pxStreamBuffer )                                  \
    vTaskSuspendAll();                                                              \
    {                                                                               \
        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
        {                                                                           \
            ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToReceive, \
                                         ( pxStreamBuffer )->uxNotificationIndex,   \
                                         ( uint32_t ) 0,                            \
                                         eNoAction );                               \
            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
        }                                                                           \
    }                                                                               \
    ( void ) xTaskResumeAll()
    #endif /* sbSEND_COMPLETED */

/* If user has provided a per-instance send completed callback, then
 * invoke the callback else use the send complete macro which is provided by default for all instances.
 */
    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        #define prvSEND_COMPLETED( pxStreamBuffer )                                           \
    do {                                                                                      \
        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                             \
        {                                                                                     \
            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \
        }                                                                                     \
        else                                                                                  \
        {                                                                                     \
            sbSEND_COMPLETED( ( pxStreamBuffer ) );                                           \
        }                                                                                     \
    } while( 0 )
    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
        #define prvSEND_COMPLETED( pxStreamBuffer )    sbSEND_COMPLETED( ( pxStreamBuffer ) )
    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */


    #ifndef sbSEND_COMPLETE_FROM_ISR
        #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )          \
    do {                                                                                       \
        UBaseType_t uxSavedInterruptStatus;                                                    \
                                                                                               \
        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();                                \
        {                                                                                      \
            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                            \
            {                                                                                  \
                ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
                                                    ( pxStreamBuffer )->uxNotificationIndex,   \
                                                    ( uint32_t ) 0,                            \
                                                    eNoAction,                                 \
                                                    ( pxHigherPriorityTaskWoken ) );           \
                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                              \
            }                                                                                  \
        }                                                                                      \
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );                                  \
    } while( 0 )
    #endif /* sbSEND_COMPLETE_FROM_ISR */


    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )                                \
    do {                                                                                                              \
        if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL )                                                     \
        {                                                                                                             \
            ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \
        }                                                                                                             \
        else                                                                                                          \
        {                                                                                                             \
            sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) );                            \
        }                                                                                                             \
    } while( 0 )
    #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
        #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
    sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) )
    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */

/* The number of bytes used to hold the length of a message in the buffer. */
    #define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )

/* Bits stored in the ucFlags field of the stream buffer. */
    #define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
    #define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
    #define sbFLAGS_IS_BATCHING_BUFFER         ( ( uint8_t ) 4 ) /* Set if the stream buffer was created as a batching buffer, meaning the receiver task will only unblock when the trigger level exceededs. */

/*-----------------------------------------------------------*/

/* Structure that hold state information on the buffer. */
typedef struct StreamBufferDef_t
{
    volatile size_t xTail;                       /* Index to the next item to read within the buffer. */
    volatile size_t xHead;                       /* Index to the next item to write within the buffer. */
    size_t xLength;                              /* The length of the buffer pointed to by pucBuffer. */
    size_t xTriggerLevelBytes;                   /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
    volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
    volatile TaskHandle_t xTaskWaitingToSend;    /* Holds the handle of a task waiting to send data to a message buffer that is full. */
    uint8_t * pucBuffer;                         /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
    uint8_t ucFlags;

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
    #endif

    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
        StreamBufferCallbackFunction_t pxSendCompletedCallback;    /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */
        StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete.  sbRECEIVE_COMPLETED is called if this is NULL. */
    #endif
    UBaseType_t uxNotificationIndex;                               /* The index we are using for notification, by default tskDEFAULT_INDEX_TO_NOTIFY. */
} StreamBuffer_t;

/*
 * The number of bytes available to be read from the buffer.
 */
static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;

/*
 * Add xCount bytes from pucData into the pxStreamBuffer's data storage area.
 * This function does not update the buffer's xHead pointer, so multiple writes
 * may be chained together "atomically". This is useful for Message Buffers where
 * the length and data bytes are written in two separate chunks, and we don't want
 * the reader to see the buffer as having grown until after all data is copied over.
 * This function takes a custom xHead value to indicate where to write to (necessary
 * for chaining) and returns the the resulting xHead position.
 * To mark the write as complete, manually set the buffer's xHead field with the
 * returned xHead from this function.
 */
static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
                                     const uint8_t * pucData,
                                     size_t xCount,
                                     size_t xHead ) PRIVILEGED_FUNCTION;

/*
 * If the stream buffer is being used as a message buffer, then reads an entire
 * message out of the buffer.  If the stream buffer is being used as a stream
 * buffer then read as many bytes as possible from the buffer.
 * prvReadBytesFromBuffer() is called to actually extract the bytes from the
 * buffer's data storage area.
 */
static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
                                        void * pvRxData,
                                        size_t xBufferLengthBytes,
                                        size_t xBytesAvailable ) PRIVILEGED_FUNCTION;

/*
 * If the stream buffer is being used as a message buffer, then writes an entire
 * message to the buffer.  If the stream buffer is being used as a stream
 * buffer then write as many bytes as possible to the buffer.
 * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
 * data storage area.
 */
static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
                                       const void * pvTxData,
                                       size_t xDataLengthBytes,
                                       size_t xSpace,
                                       size_t xRequiredSpace ) PRIVILEGED_FUNCTION;

/*
 * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData.
 * This function does not update the buffer's xTail pointer, so multiple reads
 * may be chained together "atomically". This is useful for Message Buffers where
 * the length and data bytes are read in two separate chunks, and we don't want
 * the writer to see the buffer as having more free space until after all data is
 * copied over, especially if we have to abort the read due to insufficient receiving space.
 * This function takes a custom xTail value to indicate where to read from (necessary
 * for chaining) and returns the the resulting xTail position.
 * To mark the read as complete, manually set the buffer's xTail field with the
 * returned xTail from this function.
 */
static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
                                      uint8_t * pucData,
                                      size_t xCount,
                                      size_t xTail ) PRIVILEGED_FUNCTION;

/*
 * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
 * initialise the members of the newly created stream buffer structure.
 */
static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
                                          uint8_t * const pucBuffer,
                                          size_t xBufferSizeBytes,
                                          size_t xTriggerLevelBytes,
                                          uint8_t ucFlags,
                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;

/*-----------------------------------------------------------*/
    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                     size_t xTriggerLevelBytes,
                                                     BaseType_t xStreamBufferType,
                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
    {
        void * pvAllocatedMemory;
        uint8_t ucFlags;

        traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback );

        /* In case the stream buffer is going to be used as a message buffer
         * (that is, it will hold discrete messages with a little meta data that
         * says how big the next message is) check the buffer will be large enough
         * to hold at least one message. */
        if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
        {
            /* Is a message buffer but not statically allocated. */
            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
        }
        else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
        {
            /* Is a batching buffer but not statically allocated. */
            ucFlags = sbFLAGS_IS_BATCHING_BUFFER;
            configASSERT( xBufferSizeBytes > 0 );
        }
        else
        {
            /* Not a message buffer and not statically allocated. */
            ucFlags = 0;
            configASSERT( xBufferSizeBytes > 0 );
        }

        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );

        /* A trigger level of 0 would cause a waiting task to unblock even when
         * the buffer was empty. */
        if( xTriggerLevelBytes == ( size_t ) 0 )
        {
            xTriggerLevelBytes = ( size_t ) 1;
        }

        /* A stream buffer requires a StreamBuffer_t structure and a buffer.
         * Both are allocated in a single call to pvPortMalloc().  The
         * StreamBuffer_t structure is placed at the start of the allocated memory
         * and the buffer follows immediately after.  The requested size is
         * incremented so the free space is returned as the user would expect -
         * this is a quirk of the implementation that means otherwise the free
         * space would be reported as one byte smaller than would be logically
         * expected. */
        if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) )
        {
            xBufferSizeBytes++;
            pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) );
        }
        else
        {
            pvAllocatedMemory = NULL;
        }

        if( pvAllocatedMemory != NULL )
        {
            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory,                         /* Structure at the start of the allocated memory. */
                                                                                                          /* MISRA Ref 11.5.1 [Malloc memory assignment] */
                                                                                                          /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                                                                                                          /* coverity[misra_c_2012_rule_11_5_violation] */
                                          ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */
                                          xBufferSizeBytes,
                                          xTriggerLevelBytes,
                                          ucFlags,
                                          pxSendCompletedCallback,
                                          pxReceiveCompletedCallback );

            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xStreamBufferType );
        }
        else
        {
            traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType );
        }

        traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory );

        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        return ( StreamBufferHandle_t ) pvAllocatedMemory;
    }
    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )

    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
                                                           size_t xTriggerLevelBytes,
                                                           BaseType_t xStreamBufferType,
                                                           uint8_t * const pucStreamBufferStorageArea,
                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
    {
        /* MISRA Ref 11.3.1 [Misaligned access] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
        /* coverity[misra_c_2012_rule_11_3_violation] */
        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer;
        StreamBufferHandle_t xReturn;
        uint8_t ucFlags;

        traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback );

        configASSERT( pucStreamBufferStorageArea );
        configASSERT( pxStaticStreamBuffer );
        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );

        /* A trigger level of 0 would cause a waiting task to unblock even when
         * the buffer was empty. */
        if( xTriggerLevelBytes == ( size_t ) 0 )
        {
            xTriggerLevelBytes = ( size_t ) 1;
        }

        /* In case the stream buffer is going to be used as a message buffer
         * (that is, it will hold discrete messages with a little meta data that
         * says how big the next message is) check the buffer will be large enough
         * to hold at least one message. */

        if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER )
        {
            /* Statically allocated message buffer. */
            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
        }
        else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER )
        {
            /* Statically allocated batching buffer. */
            ucFlags = sbFLAGS_IS_BATCHING_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
            configASSERT( xBufferSizeBytes > 0 );
        }
        else
        {
            /* Statically allocated stream buffer. */
            ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
        }

        #if ( configASSERT_DEFINED == 1 )
        {
            /* Sanity check that the size of the structure used to declare a
             * variable of type StaticStreamBuffer_t equals the size of the real
             * message buffer structure. */
            volatile size_t xSize = sizeof( StaticStreamBuffer_t );
            configASSERT( xSize == sizeof( StreamBuffer_t ) );
        }
        #endif /* configASSERT_DEFINED */

        if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
        {
            prvInitialiseNewStreamBuffer( pxStreamBuffer,
                                          pucStreamBufferStorageArea,
                                          xBufferSizeBytes,
                                          xTriggerLevelBytes,
                                          ucFlags,
                                          pxSendCompletedCallback,
                                          pxReceiveCompletedCallback );

            /* Remember this was statically allocated in case it is ever deleted
             * again. */
            pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;

            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType );

            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer;
        }
        else
        {
            xReturn = NULL;
            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType );
        }

        traceRETURN_xStreamBufferGenericCreateStatic( xReturn );

        return xReturn;
    }
    #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer,
                                              uint8_t ** ppucStreamBufferStorageArea,
                                              StaticStreamBuffer_t ** ppxStaticStreamBuffer )
    {
        BaseType_t xReturn;
        StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;

        traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer );

        configASSERT( pxStreamBuffer );
        configASSERT( ppucStreamBufferStorageArea );
        configASSERT( ppxStaticStreamBuffer );

        if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 )
        {
            *ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer;
            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            *ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer;
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }

        traceRETURN_xStreamBufferGetStaticBuffers( xReturn );

        return xReturn;
    }
    #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
{
    StreamBuffer_t * pxStreamBuffer = xStreamBuffer;

    traceENTER_vStreamBufferDelete( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    traceSTREAM_BUFFER_DELETE( xStreamBuffer );

    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
    {
        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
        {
            /* Both the structure and the buffer were allocated using a single call
            * to pvPortMalloc(), hence only one call to vPortFree() is required. */
            vPortFree( ( void * ) pxStreamBuffer );
        }
        #else
        {
            /* Should not be possible to get here, ucFlags must be corrupt.
             * Force an assert. */
            configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
        }
        #endif
    }
    else
    {
        /* The structure and buffer were not allocated dynamically and cannot be
         * freed - just scrub the structure so future use will assert. */
        ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
    }

    traceRETURN_vStreamBufferDelete();
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn = pdFAIL;
    StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxStreamBufferNumber;
    #endif

    traceENTER_xStreamBufferReset( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    #if ( configUSE_TRACE_FACILITY == 1 )
    {
        /* Store the stream buffer number so it can be restored after the
         * reset. */
        uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
    }
    #endif

    /* Can only reset a message buffer if there are no tasks blocked on it. */
    taskENTER_CRITICAL();
    {
        if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
        {
            #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
            {
                pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
                pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
            }
            #endif

            prvInitialiseNewStreamBuffer( pxStreamBuffer,
                                          pxStreamBuffer->pucBuffer,
                                          pxStreamBuffer->xLength,
                                          pxStreamBuffer->xTriggerLevelBytes,
                                          pxStreamBuffer->ucFlags,
                                          pxSendCallback,
                                          pxReceiveCallback );

            #if ( configUSE_TRACE_FACILITY == 1 )
            {
                pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
            }
            #endif

            traceSTREAM_BUFFER_RESET( xStreamBuffer );

            xReturn = pdPASS;
        }
    }
    taskEXIT_CRITICAL();

    traceRETURN_xStreamBufferReset( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn = pdFAIL;
    StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL;
    UBaseType_t uxSavedInterruptStatus;

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxStreamBufferNumber;
    #endif

    traceENTER_xStreamBufferResetFromISR( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    #if ( configUSE_TRACE_FACILITY == 1 )
    {
        /* Store the stream buffer number so it can be restored after the
         * reset. */
        uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
    }
    #endif

    /* Can only reset a message buffer if there are no tasks blocked on it. */
    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
    {
        if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) )
        {
            #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
            {
                pxSendCallback = pxStreamBuffer->pxSendCompletedCallback;
                pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback;
            }
            #endif

            prvInitialiseNewStreamBuffer( pxStreamBuffer,
                                          pxStreamBuffer->pucBuffer,
                                          pxStreamBuffer->xLength,
                                          pxStreamBuffer->xTriggerLevelBytes,
                                          pxStreamBuffer->ucFlags,
                                          pxSendCallback,
                                          pxReceiveCallback );

            #if ( configUSE_TRACE_FACILITY == 1 )
            {
                pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
            }
            #endif

            traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer );

            xReturn = pdPASS;
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xStreamBufferResetFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
                                         size_t xTriggerLevel )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn;

    traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );

    configASSERT( pxStreamBuffer );

    /* It is not valid for the trigger level to be 0. */
    if( xTriggerLevel == ( size_t ) 0 )
    {
        xTriggerLevel = ( size_t ) 1;
    }

    /* The trigger level is the number of bytes that must be in the stream
     * buffer before a task that is waiting for data is unblocked. */
    if( xTriggerLevel < pxStreamBuffer->xLength )
    {
        pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
        xReturn = pdPASS;
    }
    else
    {
        xReturn = pdFALSE;
    }

    traceRETURN_xStreamBufferSetTriggerLevel( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
{
    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xSpace;
    size_t xOriginalTail;

    traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    /* The code below reads xTail and then xHead.  This is safe if the stream
     * buffer is updated once between the two reads - but not if the stream buffer
     * is updated more than once between the two reads - hence the loop. */
    do
    {
        xOriginalTail = pxStreamBuffer->xTail;
        xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
        xSpace -= pxStreamBuffer->xHead;
    } while( xOriginalTail != pxStreamBuffer->xTail );

    xSpace -= ( size_t ) 1;

    if( xSpace >= pxStreamBuffer->xLength )
    {
        xSpace -= pxStreamBuffer->xLength;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    traceRETURN_xStreamBufferSpacesAvailable( xSpace );

    return xSpace;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
{
    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReturn;

    traceENTER_xStreamBufferBytesAvailable( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    xReturn = prvBytesInBuffer( pxStreamBuffer );

    traceRETURN_xStreamBufferBytesAvailable( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
                          const void * pvTxData,
                          size_t xDataLengthBytes,
                          TickType_t xTicksToWait )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReturn, xSpace = 0;
    size_t xRequiredSpace = xDataLengthBytes;
    TimeOut_t xTimeOut;
    size_t xMaxReportedSpace = 0;

    traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );

    configASSERT( pvTxData );
    configASSERT( pxStreamBuffer );

    /* The maximum amount of space a stream buffer will ever report is its length
     * minus 1. */
    xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1;

    /* This send function is used to write to both message buffers and stream
     * buffers.  If this is a message buffer then the space needed must be
     * increased by the amount of bytes needed to store the length of the
     * message. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;

        /* Overflow? */
        configASSERT( xRequiredSpace > xDataLengthBytes );

        /* If this is a message buffer then it must be possible to write the
         * whole message. */
        if( xRequiredSpace > xMaxReportedSpace )
        {
            /* The message would not fit even if the entire buffer was empty,
             * so don't wait for space. */
            xTicksToWait = ( TickType_t ) 0;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        /* If this is a stream buffer then it is acceptable to write only part
         * of the message to the buffer.  Cap the length to the total length of
         * the buffer. */
        if( xRequiredSpace > xMaxReportedSpace )
        {
            xRequiredSpace = xMaxReportedSpace;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }

    if( xTicksToWait != ( TickType_t ) 0 )
    {
        vTaskSetTimeOutState( &xTimeOut );

        do
        {
            /* Wait until the required number of bytes are free in the message
             * buffer. */
            taskENTER_CRITICAL();
            {
                xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );

                if( xSpace < xRequiredSpace )
                {
                    /* Clear notification state as going to wait for space. */
                    ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );

                    /* Should only be one writer. */
                    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
                    pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
                }
                else
                {
                    taskEXIT_CRITICAL();
                    break;
                }
            }
            taskEXIT_CRITICAL();

            traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
            ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
            pxStreamBuffer->xTaskWaitingToSend = NULL;
        } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    if( xSpace == ( size_t ) 0 )
    {
        xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );

    if( xReturn > ( size_t ) 0 )
    {
        traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );

        /* Was a task waiting for the data? */
        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
        {
            prvSEND_COMPLETED( pxStreamBuffer );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
        traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
    }

    traceRETURN_xStreamBufferSend( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
                                 const void * pvTxData,
                                 size_t xDataLengthBytes,
                                 BaseType_t * const pxHigherPriorityTaskWoken )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReturn, xSpace;
    size_t xRequiredSpace = xDataLengthBytes;

    traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );

    configASSERT( pvTxData );
    configASSERT( pxStreamBuffer );

    /* This send function is used to write to both message buffers and stream
     * buffers.  If this is a message buffer then the space needed must be
     * increased by the amount of bytes needed to store the length of the
     * message. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );

    if( xReturn > ( size_t ) 0 )
    {
        /* Was a task waiting for the data? */
        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
        {
            /* MISRA Ref 4.7.1 [Return value shall be checked] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
            /* coverity[misra_c_2012_directive_4_7_violation] */
            prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
    traceRETURN_xStreamBufferSendFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
                                       const void * pvTxData,
                                       size_t xDataLengthBytes,
                                       size_t xSpace,
                                       size_t xRequiredSpace )
{
    size_t xNextHead = pxStreamBuffer->xHead;
    configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength;

    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        /* This is a message buffer, as opposed to a stream buffer. */

        /* Convert xDataLengthBytes to the message length type. */
        xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes;

        /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */
        configASSERT( ( size_t ) xMessageLength == xDataLengthBytes );

        if( xSpace >= xRequiredSpace )
        {
            /* There is enough space to write both the message length and the message
             * itself into the buffer.  Start by writing the length of the data, the data
             * itself will be written later in this function. */
            xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead );
        }
        else
        {
            /* Not enough space, so do not write data to the buffer. */
            xDataLengthBytes = 0;
        }
    }
    else
    {
        /* This is a stream buffer, as opposed to a message buffer, so writing a
         * stream of bytes rather than discrete messages.  Plan to write as many
         * bytes as possible. */
        xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
    }

    if( xDataLengthBytes != ( size_t ) 0 )
    {
        /* Write the data to the buffer. */
        /* MISRA Ref 11.5.5 [Void pointer assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead );
    }

    return xDataLengthBytes;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
                             void * pvRxData,
                             size_t xBufferLengthBytes,
                             TickType_t xTicksToWait )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;

    traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );

    configASSERT( pvRxData );
    configASSERT( pxStreamBuffer );

    /* This receive function is used by both message buffers, which store
     * discrete messages, and stream buffers, which store a continuous stream of
     * bytes.  Discrete messages include an additional
     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
     * message. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
    }
    else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_BATCHING_BUFFER ) != ( uint8_t ) 0 )
    {
        /* Force task to block if the batching buffer contains less bytes than
         * the trigger level. */
        xBytesToStoreMessageLength = pxStreamBuffer->xTriggerLevelBytes;
    }
    else
    {
        xBytesToStoreMessageLength = 0;
    }

    if( xTicksToWait != ( TickType_t ) 0 )
    {
        /* Checking if there is data and clearing the notification state must be
         * performed atomically. */
        taskENTER_CRITICAL();
        {
            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );

            /* If this function was invoked by a message buffer read then
             * xBytesToStoreMessageLength holds the number of bytes used to hold
             * the length of the next discrete message.  If this function was
             * invoked by a stream buffer read then xBytesToStoreMessageLength will
             * be 0. If this function was invoked by a stream batch buffer read
             * then xBytesToStoreMessageLength will be xTriggerLevelBytes value
             * for the buffer.*/
            if( xBytesAvailable <= xBytesToStoreMessageLength )
            {
                /* Clear notification state as going to wait for data. */
                ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex );

                /* Should only be one reader. */
                configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
                pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL();

        if( xBytesAvailable <= xBytesToStoreMessageLength )
        {
            /* Wait for data to be available. */
            traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
            ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
            pxStreamBuffer->xTaskWaitingToReceive = NULL;

            /* Recheck the data available after blocking. */
            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
    }

    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
     * holds the number of bytes used to store the message length) or a stream of
     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
     * available must be greater than xBytesToStoreMessageLength to be able to
     * read bytes from the buffer. */
    if( xBytesAvailable > xBytesToStoreMessageLength )
    {
        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );

        /* Was a task waiting for space in the buffer? */
        if( xReceivedLength != ( size_t ) 0 )
        {
            traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
            prvRECEIVE_COMPLETED( xStreamBuffer );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
        mtCOVERAGE_TEST_MARKER();
    }

    traceRETURN_xStreamBufferReceive( xReceivedLength );

    return xReceivedLength;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReturn, xBytesAvailable;
    configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;

    traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    /* Ensure the stream buffer is being used as a message buffer. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );

        if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
        {
            /* The number of bytes available is greater than the number of bytes
             * required to hold the length of the next message, so another message
             * is available. */
            ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail );
            xReturn = ( size_t ) xTempReturn;
        }
        else
        {
            /* The minimum amount of bytes in a message buffer is
             * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
             * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
             * value is 0. */
            configASSERT( xBytesAvailable == 0 );
            xReturn = 0;
        }
    }
    else
    {
        xReturn = 0;
    }

    traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
                                    void * pvRxData,
                                    size_t xBufferLengthBytes,
                                    BaseType_t * const pxHigherPriorityTaskWoken )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;

    traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );

    configASSERT( pvRxData );
    configASSERT( pxStreamBuffer );

    /* This receive function is used by both message buffers, which store
     * discrete messages, and stream buffers, which store a continuous stream of
     * bytes.  Discrete messages include an additional
     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
     * message. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
    }
    else
    {
        xBytesToStoreMessageLength = 0;
    }

    xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );

    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
     * holds the number of bytes used to store the message length) or a stream of
     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
     * available must be greater than xBytesToStoreMessageLength to be able to
     * read bytes from the buffer. */
    if( xBytesAvailable > xBytesToStoreMessageLength )
    {
        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable );

        /* Was a task waiting for space in the buffer? */
        if( xReceivedLength != ( size_t ) 0 )
        {
            /* MISRA Ref 4.7.1 [Return value shall be checked] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
            /* coverity[misra_c_2012_directive_4_7_violation] */
            prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
    traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength );

    return xReceivedLength;
}
/*-----------------------------------------------------------*/

static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
                                        void * pvRxData,
                                        size_t xBufferLengthBytes,
                                        size_t xBytesAvailable )
{
    size_t xCount, xNextMessageLength;
    configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
    size_t xNextTail = pxStreamBuffer->xTail;

    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        /* A discrete message is being received.  First receive the length
         * of the message. */
        xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail );
        xNextMessageLength = ( size_t ) xTempNextMessageLength;

        /* Reduce the number of bytes available by the number of bytes just
         * read out. */
        xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH;

        /* Check there is enough space in the buffer provided by the
         * user. */
        if( xNextMessageLength > xBufferLengthBytes )
        {
            /* The user has provided insufficient space to read the message. */
            xNextMessageLength = 0;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    else
    {
        /* A stream of bytes is being received (as opposed to a discrete
         * message), so read as many bytes as possible. */
        xNextMessageLength = xBufferLengthBytes;
    }

    /* Use the minimum of the wanted bytes and the available bytes. */
    xCount = configMIN( xNextMessageLength, xBytesAvailable );

    if( xCount != ( size_t ) 0 )
    {
        /* Read the actual data and update the tail to mark the data as officially consumed. */
        /* MISRA Ref 11.5.5 [Void pointer assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail );
    }

    return xCount;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
{
    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn;
    size_t xTail;

    traceENTER_xStreamBufferIsEmpty( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    /* True if no bytes are available. */
    xTail = pxStreamBuffer->xTail;

    if( pxStreamBuffer->xHead == xTail )
    {
        xReturn = pdTRUE;
    }
    else
    {
        xReturn = pdFALSE;
    }

    traceRETURN_xStreamBufferIsEmpty( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
{
    BaseType_t xReturn;
    size_t xBytesToStoreMessageLength;
    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;

    traceENTER_xStreamBufferIsFull( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    /* This generic version of the receive function is used by both message
     * buffers, which store discrete messages, and stream buffers, which store a
     * continuous stream of bytes.  Discrete messages include an additional
     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
    {
        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
    }
    else
    {
        xBytesToStoreMessageLength = 0;
    }

    /* True if the available space equals zero. */
    if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
    {
        xReturn = pdTRUE;
    }
    else
    {
        xReturn = pdFALSE;
    }

    traceRETURN_xStreamBufferIsFull( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                              BaseType_t * pxHigherPriorityTaskWoken )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;

    traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );

    configASSERT( pxStreamBuffer );

    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
    {
        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
        {
            ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
                                                ( pxStreamBuffer )->uxNotificationIndex,
                                                ( uint32_t ) 0,
                                                eNoAction,
                                                pxHigherPriorityTaskWoken );
            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xStreamBufferSendCompletedFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                 BaseType_t * pxHigherPriorityTaskWoken )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
    BaseType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;

    traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken );

    configASSERT( pxStreamBuffer );

    /* MISRA Ref 4.7.1 [Return value shall be checked] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
    /* coverity[misra_c_2012_directive_4_7_violation] */
    uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
    {
        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
        {
            ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
                                                ( pxStreamBuffer )->uxNotificationIndex,
                                                ( uint32_t ) 0,
                                                eNoAction,
                                                pxHigherPriorityTaskWoken );
            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
            xReturn = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }
    }
    taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
                                     const uint8_t * pucData,
                                     size_t xCount,
                                     size_t xHead )
{
    size_t xFirstLength;

    configASSERT( xCount > ( size_t ) 0 );

    /* Calculate the number of bytes that can be added in the first write -
     * which may be less than the total number of bytes that need to be added if
     * the buffer will wrap back to the beginning. */
    xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount );

    /* Write as many bytes as can be written in the first write. */
    configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength );
    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength );

    /* If the number of bytes written was less than the number that could be
     * written in the first write... */
    if( xCount > xFirstLength )
    {
        /* ...then write the remaining bytes to the start of the buffer. */
        configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength );
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    xHead += xCount;

    if( xHead >= pxStreamBuffer->xLength )
    {
        xHead -= pxStreamBuffer->xLength;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    return xHead;
}
/*-----------------------------------------------------------*/

static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
                                      uint8_t * pucData,
                                      size_t xCount,
                                      size_t xTail )
{
    size_t xFirstLength;

    configASSERT( xCount != ( size_t ) 0 );

    /* Calculate the number of bytes that can be read - which may be
     * less than the number wanted if the data wraps around to the start of
     * the buffer. */
    xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount );

    /* Obtain the number of bytes it is possible to obtain in the first
     * read.  Asserts check bounds of read and write. */
    configASSERT( xFirstLength <= xCount );
    configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength );
    ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength );

    /* If the total number of wanted bytes is greater than the number
     * that could be read in the first read... */
    if( xCount > xFirstLength )
    {
        /* ...then read the remaining bytes from the start of the buffer. */
        ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength );
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    /* Move the tail pointer to effectively remove the data read from the buffer. */
    xTail += xCount;

    if( xTail >= pxStreamBuffer->xLength )
    {
        xTail -= pxStreamBuffer->xLength;
    }

    return xTail;
}
/*-----------------------------------------------------------*/

static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
{
    /* Returns the distance between xTail and xHead. */
    size_t xCount;

    xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
    xCount -= pxStreamBuffer->xTail;

    if( xCount >= pxStreamBuffer->xLength )
    {
        xCount -= pxStreamBuffer->xLength;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    return xCount;
}
/*-----------------------------------------------------------*/

static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
                                          uint8_t * const pucBuffer,
                                          size_t xBufferSizeBytes,
                                          size_t xTriggerLevelBytes,
                                          uint8_t ucFlags,
                                          StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                          StreamBufferCallbackFunction_t pxReceiveCompletedCallback )
{
    /* Assert here is deliberately writing to the entire buffer to ensure it can
     * be written to without generating exceptions, and is setting the buffer to a
     * known value to assist in development/debugging. */
    #if ( configASSERT_DEFINED == 1 )
    {
        /* The value written just has to be identifiable when looking at the
         * memory.  Don't use 0xA5 as that is the stack fill value and could
         * result in confusion as to what is actually being observed. */
        #define STREAM_BUFFER_BUFFER_WRITE_VALUE    ( 0x55 )
        configASSERT( memset( pucBuffer, ( int ) STREAM_BUFFER_BUFFER_WRITE_VALUE, xBufferSizeBytes ) == pucBuffer );
    }
    #endif

    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
    pxStreamBuffer->pucBuffer = pucBuffer;
    pxStreamBuffer->xLength = xBufferSizeBytes;
    pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
    pxStreamBuffer->ucFlags = ucFlags;
    pxStreamBuffer->uxNotificationIndex = tskDEFAULT_INDEX_TO_NOTIFY;
    #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
    {
        pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback;
        pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback;
    }
    #else
    {
        /* MISRA Ref 11.1.1 [Object type casting] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
        /* coverity[misra_c_2012_rule_11_1_violation] */
        ( void ) pxSendCompletedCallback;

        /* MISRA Ref 11.1.1 [Object type casting] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */
        /* coverity[misra_c_2012_rule_11_1_violation] */
        ( void ) pxReceiveCompletedCallback;
    }
    #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */
}
/*-----------------------------------------------------------*/

UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;

    traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer );

    configASSERT( pxStreamBuffer );

    traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( pxStreamBuffer->uxNotificationIndex );

    return pxStreamBuffer->uxNotificationIndex;
}
/*-----------------------------------------------------------*/

void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
                                                    UBaseType_t uxNotificationIndex )
{
    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;

    traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex );

    configASSERT( pxStreamBuffer );

    /* There should be no task waiting otherwise we'd never resume them. */
    configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );

    /* Check that the task notification index is valid. */
    configASSERT( uxNotificationIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES );

    pxStreamBuffer->uxNotificationIndex = uxNotificationIndex;

    traceRETURN_vStreamBufferSetStreamBufferNotificationIndex();
}
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
    {
        traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer );

        traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber );

        return xStreamBuffer->uxStreamBufferNumber;
    }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
                                             UBaseType_t uxStreamBufferNumber )
    {
        traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber );

        xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;

        traceRETURN_vStreamBufferSetStreamBufferNumber();
    }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
    {
        traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer );

        traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );

        return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) );
    }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

/* This entire source file will be skipped if the application is not configured
 * to include stream buffer functionality. This #if is closed at the very bottom
 * of this file. If you want to include stream buffers then ensure
 * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */
#endif /* configUSE_STREAM_BUFFERS == 1 */


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/* Standard includes. */
#include 
#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers.  That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "timers.h"
#include "stack_macros.h"

/* The default definitions are only available for non-MPU ports. The
 * reason is that the stack alignment requirements vary for different
 * architectures.*/
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS != 0 ) )
    #error configKERNEL_PROVIDED_STATIC_MEMORY cannot be set to 1 when using an MPU port. The vApplicationGet*TaskMemory() functions must be provided manually.
#endif

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
 * for the header files above, but not in this file, in order to generate the
 * correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
 * functions but without including stdio.h here. */
#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )

/* At the bottom of this file are two optional functions that can be used
 * to generate human readable text from the raw data generated by the
 * uxTaskGetSystemState() function.  Note the formatting functions are provided
 * for convenience only, and are NOT considered part of the kernel. */
    #include 
#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */

#if ( configUSE_PREEMPTION == 0 )

/* If the cooperative scheduler is being used then a yield should not be
 * performed just because a higher priority task has been woken. */
    #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )
    #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )
#else

    #if ( configNUMBER_OF_CORES == 1 )

/* This macro requests the running task pxTCB to yield. In single core
 * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API()
 * can be used to request the task running on core 0 to yield. Therefore, pxTCB
 * is not used in this macro. */
        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \
    do {                                                         \
        ( void ) ( pxTCB );                                      \
        portYIELD_WITHIN_API();                                  \
    } while( 0 )

        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \
    do {                                                        \
        if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority )  \
        {                                                       \
            portYIELD_WITHIN_API();                             \
        }                                                       \
        else                                                    \
        {                                                       \
            mtCOVERAGE_TEST_MARKER();                           \
        }                                                       \
    } while( 0 )

    #else /* if ( configNUMBER_OF_CORES == 1 ) */

/* Yield the core on which this task is running. */
        #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB )    prvYieldCore( ( pxTCB )->xTaskRunState )

/* Yield for the task if a running task has priority lower than this task. */
        #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB )     prvYieldForTask( pxTCB )

    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

#endif /* if ( configUSE_PREEMPTION == 0 ) */

/* Values that can be assigned to the ucNotifyState member of the TCB. */
#define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
#define taskWAITING_NOTIFICATION                  ( ( uint8_t ) 1 )
#define taskNOTIFICATION_RECEIVED                 ( ( uint8_t ) 2 )

/*
 * The value used to fill the stack of a task when the task is created.  This
 * is used purely for checking the high water mark for tasks.
 */
#define tskSTACK_FILL_BYTE                        ( 0xa5U )

/* Bits used to record how a task's stack and TCB were allocated. */
#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB    ( ( uint8_t ) 0 )
#define tskSTATICALLY_ALLOCATED_STACK_ONLY        ( ( uint8_t ) 1 )
#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB     ( ( uint8_t ) 2 )

/* If any of the following are set then task stacks are filled with a known
 * value so the high water mark can be determined.  If none of the following are
 * set then don't fill the stack so there is no unnecessary dependency on memset. */
#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    1
#else
    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    0
#endif

/*
 * Macros used by vListTask to indicate which state a task is in.
 */
#define tskRUNNING_CHAR      ( 'X' )
#define tskBLOCKED_CHAR      ( 'B' )
#define tskREADY_CHAR        ( 'R' )
#define tskDELETED_CHAR      ( 'D' )
#define tskSUSPENDED_CHAR    ( 'S' )

/*
 * Some kernel aware debuggers require the data the debugger needs access to be
 * global, rather than file scope.
 */
#ifdef portREMOVE_STATIC_QUALIFIER
    #define static
#endif

/* The name allocated to the Idle task.  This can be overridden by defining
 * configIDLE_TASK_NAME in FreeRTOSConfig.h. */
#ifndef configIDLE_TASK_NAME
    #define configIDLE_TASK_NAME    "IDLE"
#endif

#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )

/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
 * performed in a generic way that is not optimised to any particular
 * microcontroller architecture. */

/* uxTopReadyPriority holds the priority of the highest priority ready
 * state task. */
    #define taskRECORD_READY_PRIORITY( uxPriority ) \
    do {                                            \
        if( ( uxPriority ) > uxTopReadyPriority )   \
        {                                           \
            uxTopReadyPriority = ( uxPriority );    \
        }                                           \
    } while( 0 ) /* taskRECORD_READY_PRIORITY */

/*-----------------------------------------------------------*/

    #if ( configNUMBER_OF_CORES == 1 )
        #define taskSELECT_HIGHEST_PRIORITY_TASK()                                       \
    do {                                                                                 \
        UBaseType_t uxTopPriority = uxTopReadyPriority;                                  \
                                                                                         \
        /* Find the highest priority queue that contains ready tasks. */                 \
        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) != pdFALSE ) \
        {                                                                                \
            configASSERT( uxTopPriority );                                               \
            --uxTopPriority;                                                             \
        }                                                                                \
                                                                                         \
        /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
         * the  same priority get an equal share of the processor time. */                    \
        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
        uxTopReadyPriority = uxTopPriority;                                                   \
    } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */
    #else /* if ( configNUMBER_OF_CORES == 1 ) */

        #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID )    prvSelectHighestPriorityTask( xCoreID )

    #endif /* if ( configNUMBER_OF_CORES == 1 ) */

/*-----------------------------------------------------------*/

/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
 * they are only required when a port optimised method of task selection is
 * being used. */
    #define taskRESET_READY_PRIORITY( uxPriority )
    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )

#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
 * performed in a way that is tailored to the particular microcontroller
 * architecture being used. */

/* A port optimised version is provided.  Call the port defined macros. */
    #define taskRECORD_READY_PRIORITY( uxPriority )    portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority )

/*-----------------------------------------------------------*/

    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                  \
    do {                                                                                        \
        UBaseType_t uxTopPriority;                                                              \
                                                                                                \
        /* Find the highest priority list that contains ready tasks. */                         \
        portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                          \
        configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );   \
    } while( 0 )

/*-----------------------------------------------------------*/

/* A port optimised version is provided, call it only if the TCB being reset
 * is being referenced from a ready list.  If it is referenced from a delayed
 * or suspended list then it won't be in a ready list. */
    #define taskRESET_READY_PRIORITY( uxPriority )                                                     \
    do {                                                                                               \
        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
        {                                                                                              \
            portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                        \
        }                                                                                              \
    } while( 0 )

#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */

/*-----------------------------------------------------------*/

/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
 * count overflows. */
#define taskSWITCH_DELAYED_LISTS()                                                \
    do {                                                                          \
        List_t * pxTemp;                                                          \
                                                                                  \
        /* The delayed tasks list should be empty when the lists are switched. */ \
        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );               \
                                                                                  \
        pxTemp = pxDelayedTaskList;                                               \
        pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
        pxOverflowDelayedTaskList = pxTemp;                                       \
        xNumOfOverflows = ( BaseType_t ) ( xNumOfOverflows + 1 );                 \
        prvResetNextTaskUnblockTime();                                            \
    } while( 0 )

/*-----------------------------------------------------------*/

/*
 * Place the task represented by pxTCB into the appropriate ready list for
 * the task.  It is inserted at the end of the list.
 */
#define prvAddTaskToReadyList( pxTCB )                                                                     \
    do {                                                                                                   \
        traceMOVED_TASK_TO_READY_STATE( pxTCB );                                                           \
        taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                \
        listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
        tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB );                                                      \
    } while( 0 )
/*-----------------------------------------------------------*/

/*
 * Several functions take a TaskHandle_t parameter that can optionally be NULL,
 * where NULL is used to indicate that the handle of the currently executing
 * task should be used in place of the parameter.  This macro simply checks to
 * see if the parameter is NULL and returns a pointer to the appropriate TCB.
 */
#define prvGetTCBFromHandle( pxHandle )    ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )

/* The item value of the event list item is normally used to hold the priority
 * of the task to which it belongs (coded to allow it to be held in reverse
 * priority order).  However, it is occasionally borrowed for other purposes.  It
 * is important its value is not updated due to a task priority change while it is
 * being used for another purpose.  The following bit definition is used to inform
 * the scheduler that the value should not be changed - in which case it is the
 * responsibility of whichever module is using the value to ensure it gets set back
 * to its original value when it is released. */
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint16_t ) 0x8000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint32_t ) 0x80000000U )
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    ( ( uint64_t ) 0x8000000000000000U )
#endif

/* Indicates that the task is not actively running on any core. */
#define taskTASK_NOT_RUNNING           ( ( BaseType_t ) ( -1 ) )

/* Indicates that the task is actively running but scheduled to yield. */
#define taskTASK_SCHEDULED_TO_YIELD    ( ( BaseType_t ) ( -2 ) )

/* Returns pdTRUE if the task is actively running and not scheduled to yield. */
#if ( configNUMBER_OF_CORES == 1 )
    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) )
#else
    #define taskTASK_IS_RUNNING( pxTCB )                          ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) )
    #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB )    ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) )
#endif

/* Indicates that the task is an Idle task. */
#define taskATTRIBUTE_IS_IDLE    ( UBaseType_t ) ( 1U << 0U )

#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) )
    #define portGET_CRITICAL_NESTING_COUNT()          ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting )
    #define portSET_CRITICAL_NESTING_COUNT( x )       ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting = ( x ) )
    #define portINCREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting++ )
    #define portDECREMENT_CRITICAL_NESTING_COUNT()    ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxCriticalNesting-- )
#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */

#define taskBITS_PER_BYTE    ( ( size_t ) 8 )

#if ( configNUMBER_OF_CORES > 1 )

/* Yields the given core. This must be called from a critical section and xCoreID
 * must be valid. This macro is not required in single core since there is only
 * one core to yield. */
    #define prvYieldCore( xCoreID )                                                          \
    do {                                                                                     \
        if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() )                                \
        {                                                                                    \
            /* Pending a yield for this core since it is in the critical section. */         \
            xYieldPendings[ ( xCoreID ) ] = pdTRUE;                                          \
        }                                                                                    \
        else                                                                                 \
        {                                                                                    \
            /* Request other core to yield if it is not requested before. */                 \
            if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \
            {                                                                                \
                portYIELD_CORE( xCoreID );                                                   \
                pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD;   \
            }                                                                                \
        }                                                                                    \
    } while( 0 )
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

/*
 * Task control block.  A task control block (TCB) is allocated for each task,
 * and stores task state information, including a pointer to the task's context
 * (the task's run time environment, including register values)
 */
typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
    volatile StackType_t * pxTopOfStack; /**< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */

    #if ( portUSING_MPU_WRAPPERS == 1 )
        xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
    #endif

    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
        UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores.  UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */
    #endif

    ListItem_t xStateListItem;                  /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
    ListItem_t xEventListItem;                  /**< Used to reference a task from an event list. */
    UBaseType_t uxPriority;                     /**< The priority of the task.  0 is the lowest priority. */
    StackType_t * pxStack;                      /**< Points to the start of the stack. */
    #if ( configNUMBER_OF_CORES > 1 )
        volatile BaseType_t xTaskRunState;      /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */
        UBaseType_t uxTaskAttributes;           /**< Task's attributes - currently used to identify the idle tasks. */
    #endif
    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created.  Facilitates debugging only. */

    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
        BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */
    #endif

    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
        StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */
    #endif

    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
        UBaseType_t uxCriticalNesting; /**< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
    #endif

    #if ( configUSE_TRACE_FACILITY == 1 )
        UBaseType_t uxTCBNumber;  /**< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
        UBaseType_t uxTaskNumber; /**< Stores a number specifically for use by third party trace code. */
    #endif

    #if ( configUSE_MUTEXES == 1 )
        UBaseType_t uxBasePriority; /**< The priority last assigned to the task - used by the priority inheritance mechanism. */
        UBaseType_t uxMutexesHeld;
    #endif

    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
        TaskHookFunction_t pxTaskTag;
    #endif

    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
        void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
    #endif

    #if ( configGENERATE_RUN_TIME_STATS == 1 )
        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /**< Stores the amount of time the task has spent in the Running state. */
    #endif

    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
        configTLS_BLOCK_TYPE xTLSBlock; /**< Memory block used as Thread Local Storage (TLS) Block for the task. */
    #endif

    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
        volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
        volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
    #endif

    /* See the comments in FreeRTOS.h with the definition of
     * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
        uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
    #endif

    #if ( INCLUDE_xTaskAbortDelay == 1 )
        uint8_t ucDelayAborted;
    #endif

    #if ( configUSE_POSIX_ERRNO == 1 )
        int iTaskErrno;
    #endif
} tskTCB;

/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
 * below to enable the use of older kernel aware debuggers. */
typedef tskTCB TCB_t;

#if ( configNUMBER_OF_CORES == 1 )
    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
    /* coverity[misra_c_2012_rule_8_4_violation] */
    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
#else
    /* MISRA Ref 8.4.1 [Declaration shall be visible] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
    /* coverity[misra_c_2012_rule_8_4_violation] */
    portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ];
    #define pxCurrentTCB    xTaskGetCurrentTaskHandle()
#endif

/* Lists for ready and blocked tasks. --------------------
 * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but
 * doing so breaks some kernel aware debuggers and debuggers that rely on removing
 * the static qualifier. */
PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /**< Prioritised ready tasks. */
PRIVILEGED_DATA static List_t xDelayedTaskList1;                         /**< Delayed tasks. */
PRIVILEGED_DATA static List_t xDelayedTaskList2;                         /**< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;              /**< Points to the delayed task list currently being used. */
PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;      /**< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
PRIVILEGED_DATA static List_t xPendingReadyList;                         /**< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */

#if ( INCLUDE_vTaskDelete == 1 )

    PRIVILEGED_DATA static List_t xTasksWaitingTermination; /**< Tasks that have been deleted - but their memory not yet freed. */
    PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;

#endif

#if ( INCLUDE_vTaskSuspend == 1 )

    PRIVILEGED_DATA static List_t xSuspendedTaskList; /**< Tasks that are currently suspended. */

#endif

/* Global POSIX errno. Its value is changed upon context switching to match
 * the errno of the currently running task. */
#if ( configUSE_POSIX_ERRNO == 1 )
    int FreeRTOS_errno = 0;
#endif

/* Other file private variables. --------------------------------*/
PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE };
PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ];       /**< Holds the handles of the idle tasks.  The idle tasks are created automatically when the scheduler is started. */

/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
 * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
 * to determine the number of priority lists to read back from the remote target. */
static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;

/* Context switches are held pending while the scheduler is suspended.  Also,
 * interrupts must not manipulate the xStateListItem of a TCB, or any of the
 * lists the xStateListItem can be referenced from, if the scheduler is suspended.
 * If an interrupt needs to unblock a task while the scheduler is suspended then it
 * moves the task's event list item into the xPendingReadyList, ready for the
 * kernel to move the task from the pending ready list into the real ready list
 * when the scheduler is unsuspended.  The pending ready list itself can only be
 * accessed from a critical section.
 *
 * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock
 * and must not be done from an ISR. Reads must be protected by either lock and may be done
 * from either an ISR or a task. */
PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U;

#if ( configGENERATE_RUN_TIME_STATS == 1 )

/* Do not move these variables to function scope as doing so prevents the
 * code working with debuggers that need to remove the static qualifier. */
PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U };    /**< Holds the value of a timer/counter the last time a task was switched in. */
PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */

#endif

/*-----------------------------------------------------------*/

/* File private functions. --------------------------------*/

/*
 * Creates the idle tasks during scheduler start.
 */
static BaseType_t prvCreateIdleTasks( void );

#if ( configNUMBER_OF_CORES > 1 )

/*
 * Checks to see if another task moved the current task out of the ready
 * list while it was waiting to enter a critical section and yields, if so.
 */
    static void prvCheckForRunStateChange( void );
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

#if ( configNUMBER_OF_CORES > 1 )

/*
 * Yields a core, or cores if multiple priorities are not allowed to run
 * simultaneously, to allow the task pxTCB to run.
 */
    static void prvYieldForTask( const TCB_t * pxTCB );
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

#if ( configNUMBER_OF_CORES > 1 )

/*
 * Selects the highest priority available task for the given core.
 */
    static void prvSelectHighestPriorityTask( BaseType_t xCoreID );
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

/**
 * Utility task that simply returns pdTRUE if the task referenced by xTask is
 * currently in the Suspended state, or pdFALSE if the task referenced by xTask
 * is in any other state.
 */
#if ( INCLUDE_vTaskSuspend == 1 )

    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;

#endif /* INCLUDE_vTaskSuspend */

/*
 * Utility to ready all the lists used by the scheduler.  This is called
 * automatically upon the creation of the first task.
 */
static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;

/*
 * The idle task, which as all tasks is implemented as a never ending loop.
 * The idle task is automatically created and added to the ready lists upon
 * creation of the first user task.
 *
 * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also
 * created to ensure that each core has an idle task to run when no other
 * task is available to run.
 *
 * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
 * language extensions.  The equivalent prototype for these functions are:
 *
 * void prvIdleTask( void *pvParameters );
 * void prvPassiveIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
#if ( configNUMBER_OF_CORES > 1 )
    static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
#endif

/*
 * Utility to free all memory allocated by the scheduler to hold a TCB,
 * including the stack pointed to by the TCB.
 *
 * This does not free memory allocated by the task itself (i.e. memory
 * allocated by calls to pvPortMalloc from within the tasks application code).
 */
#if ( INCLUDE_vTaskDelete == 1 )

    static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION;

#endif

/*
 * Used only by the idle task.  This checks to see if anything has been placed
 * in the list of tasks waiting to be deleted.  If so the task is cleaned up
 * and its TCB deleted.
 */
static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;

/*
 * The currently executing task is entering the Blocked state.  Add the task to
 * either the current or the overflow delayed task list.
 */
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
                                            const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;

/*
 * Fills an TaskStatus_t structure with information on each task that is
 * referenced from the pxList list (which may be a ready list, a delayed list,
 * a suspended list, etc.).
 *
 * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
 * NORMAL APPLICATION CODE.
 */
#if ( configUSE_TRACE_FACILITY == 1 )

    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
                                                     List_t * pxList,
                                                     eTaskState eState ) PRIVILEGED_FUNCTION;

#endif

/*
 * Searches pxList for a task with name pcNameToQuery - returning a handle to
 * the task if it is found, or NULL if the task is not found.
 */
#if ( INCLUDE_xTaskGetHandle == 1 )

    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
                                                     const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;

#endif

/*
 * When a task is created, the stack of the task is filled with a known value.
 * This function determines the 'high water mark' of the task stack by
 * determining how much of the stack remains at the original preset value.
 */
#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )

    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;

#endif

/*
 * Return the amount of time, in ticks, that will pass before the kernel will
 * next move a task from the Blocked state to the Running state.
 *
 * This conditional compilation should use inequality to 0, not equality to 1.
 * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
 * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
 * set to a value other than 1.
 */
#if ( configUSE_TICKLESS_IDLE != 0 )

    static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;

#endif

/*
 * Set xNextTaskUnblockTime to the time at which the next Blocked state task
 * will exit the Blocked state.
 */
static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;

#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )

/*
 * Helper function used to pad task names with spaces when printing out
 * human readable tables of task information.
 */
    static char * prvWriteNameToBuffer( char * pcBuffer,
                                        const char * pcTaskName ) PRIVILEGED_FUNCTION;

#endif

/*
 * Called after a Task_t structure has been allocated either statically or
 * dynamically to fill in the structure's members.
 */
static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                                  const char * const pcName,
                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                  void * const pvParameters,
                                  UBaseType_t uxPriority,
                                  TaskHandle_t * const pxCreatedTask,
                                  TCB_t * pxNewTCB,
                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;

/*
 * Called after a new task has been created and initialised to place the task
 * under the control of the scheduler.
 */
static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;

/*
 * Create a task with static buffer for both TCB and stack. Returns a handle to
 * the task if it is created successfully. Otherwise, returns NULL.
 */
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
                                        const char * const pcName,
                                        const configSTACK_DEPTH_TYPE uxStackDepth,
                                        void * const pvParameters,
                                        UBaseType_t uxPriority,
                                        StackType_t * const puxStackBuffer,
                                        StaticTask_t * const pxTaskBuffer,
                                        TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */

/*
 * Create a restricted task with static buffer for both TCB and stack. Returns
 * a handle to the task if it is created successfully. Otherwise, returns NULL.
 */
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
                                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */

/*
 * Create a restricted task with static buffer for task stack and allocated buffer
 * for TCB. Returns a handle to the task if it is created successfully. Otherwise,
 * returns NULL.
 */
#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
                                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */

/*
 * Create a task with allocated buffer for both TCB and stack. Returns a handle to
 * the task if it is created successfully. Otherwise, returns NULL.
 */
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
                                  const char * const pcName,
                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                  void * const pvParameters,
                                  UBaseType_t uxPriority,
                                  TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */

/*
 * freertos_tasks_c_additions_init() should only be called if the user definable
 * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
 * called by the function.
 */
#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT

    static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;

#endif

#if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
    extern void vApplicationPassiveIdleHook( void );
#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */

#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )

/*
 * Convert the snprintf return value to the number of characters
 * written. The following are the possible cases:
 *
 * 1. The buffer supplied to snprintf is large enough to hold the
 *    generated string. The return value in this case is the number
 *    of characters actually written, not counting the terminating
 *    null character.
 * 2. The buffer supplied to snprintf is NOT large enough to hold
 *    the generated string. The return value in this case is the
 *    number of characters that would have been written if the
 *    buffer had been sufficiently large, not counting the
 *    terminating null character.
 * 3. Encoding error. The return value in this case is a negative
 *    number.
 *
 * From 1 and 2 above ==> Only when the return value is non-negative
 * and less than the supplied buffer length, the string has been
 * completely written.
 */
    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
                                                        size_t n );

#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )
    static void prvCheckForRunStateChange( void )
    {
        UBaseType_t uxPrevCriticalNesting;
        const TCB_t * pxThisTCB;

        /* This must only be called from within a task. */
        portASSERT_IF_IN_ISR();

        /* This function is always called with interrupts disabled
         * so this is safe. */
        pxThisTCB = pxCurrentTCBs[ portGET_CORE_ID() ];

        while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD )
        {
            /* We are only here if we just entered a critical section
            * or if we just suspended the scheduler, and another task
            * has requested that we yield.
            *
            * This is slightly complicated since we need to save and restore
            * the suspension and critical nesting counts, as well as release
            * and reacquire the correct locks. And then, do it all over again
            * if our state changed again during the reacquisition. */
            uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT();

            if( uxPrevCriticalNesting > 0U )
            {
                portSET_CRITICAL_NESTING_COUNT( 0U );
                portRELEASE_ISR_LOCK();
            }
            else
            {
                /* The scheduler is suspended. uxSchedulerSuspended is updated
                 * only when the task is not requested to yield. */
                mtCOVERAGE_TEST_MARKER();
            }

            portRELEASE_TASK_LOCK();
            portMEMORY_BARRIER();
            configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD );

            portENABLE_INTERRUPTS();

            /* Enabling interrupts should cause this core to immediately
             * service the pending interrupt and yield. If the run state is still
             * yielding here then that is a problem. */
            configASSERT( pxThisTCB->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD );

            portDISABLE_INTERRUPTS();
            portGET_TASK_LOCK();
            portGET_ISR_LOCK();

            portSET_CRITICAL_NESTING_COUNT( uxPrevCriticalNesting );

            if( uxPrevCriticalNesting == 0U )
            {
                portRELEASE_ISR_LOCK();
            }
        }
    }
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )
    static void prvYieldForTask( const TCB_t * pxTCB )
    {
        BaseType_t xLowestPriorityToPreempt;
        BaseType_t xCurrentCoreTaskPriority;
        BaseType_t xLowestPriorityCore = ( BaseType_t ) -1;
        BaseType_t xCoreID;

        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
            BaseType_t xYieldCount = 0;
        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */

        /* This must be called from a critical section. */
        configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );

        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )

            /* No task should yield for this one if it is a lower priority
             * than priority level of currently ready tasks. */
            if( pxTCB->uxPriority >= uxTopReadyPriority )
        #else
            /* Yield is not required for a task which is already running. */
            if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
        #endif
        {
            xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority;

            /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB
             * is 0. This is ok as we will give system idle tasks a priority of -1 below. */
            --xLowestPriorityToPreempt;

            for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
            {
                xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority;

                /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */
                if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                {
                    xCurrentCoreTaskPriority = ( BaseType_t ) ( xCurrentCoreTaskPriority - 1 );
                }

                if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) )
                {
                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                        if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE )
                    #endif
                    {
                        if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt )
                        {
                            #if ( configUSE_CORE_AFFINITY == 1 )
                                if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                            #endif
                            {
                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
                                    if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
                                #endif
                                {
                                    xLowestPriorityToPreempt = xCurrentCoreTaskPriority;
                                    xLowestPriorityCore = xCoreID;
                                }
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }

                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                    {
                        /* Yield all currently running non-idle tasks with a priority lower than
                         * the task that needs to run. */
                        if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) &&
                            ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) )
                        {
                            prvYieldCore( xCoreID );
                            xYieldCount++;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }

            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) )
            #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
                if( xLowestPriorityCore >= 0 )
            #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */
            {
                prvYieldCore( xLowestPriorityCore );
            }

            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                /* Verify that the calling core always yields to higher priority tasks. */
                if( ( ( pxCurrentTCBs[ portGET_CORE_ID() ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) &&
                    ( pxTCB->uxPriority > pxCurrentTCBs[ portGET_CORE_ID() ]->uxPriority ) )
                {
                    configASSERT( ( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) ||
                                  ( taskTASK_IS_RUNNING( pxCurrentTCBs[ portGET_CORE_ID() ] ) == pdFALSE ) );
                }
            #endif
        }
    }
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )
    static void prvSelectHighestPriorityTask( BaseType_t xCoreID )
    {
        UBaseType_t uxCurrentPriority = uxTopReadyPriority;
        BaseType_t xTaskScheduled = pdFALSE;
        BaseType_t xDecrementTopPriority = pdTRUE;
        TCB_t * pxTCB = NULL;

        #if ( configUSE_CORE_AFFINITY == 1 )
            const TCB_t * pxPreviousTCB = NULL;
        #endif
        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
            BaseType_t xPriorityDropped = pdFALSE;
        #endif

        /* This function should be called when scheduler is running. */
        configASSERT( xSchedulerRunning == pdTRUE );

        /* A new task is created and a running task with the same priority yields
         * itself to run the new task. When a running task yields itself, it is still
         * in the ready list. This running task will be selected before the new task
         * since the new task is always added to the end of the ready list.
         * The other problem is that the running task still in the same position of
         * the ready list when it yields itself. It is possible that it will be selected
         * earlier then other tasks which waits longer than this task.
         *
         * To fix these problems, the running task should be put to the end of the
         * ready list before searching for the ready task in the ready list. */
        if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
                                     &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE )
        {
            ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem );
            vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ),
                            &pxCurrentTCBs[ xCoreID ]->xStateListItem );
        }

        while( xTaskScheduled == pdFALSE )
        {
            #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
            {
                if( uxCurrentPriority < uxTopReadyPriority )
                {
                    /* We can't schedule any tasks, other than idle, that have a
                     * priority lower than the priority of a task currently running
                     * on another core. */
                    uxCurrentPriority = tskIDLE_PRIORITY;
                }
            }
            #endif

            if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE )
            {
                const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] );
                const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList );
                ListItem_t * pxIterator;

                /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority
                 * must not be decremented any further. */
                xDecrementTopPriority = pdFALSE;

                for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
                {
                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                    /* coverity[misra_c_2012_rule_11_5_violation] */
                    pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator );

                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                    {
                        /* When falling back to the idle priority because only one priority
                         * level is allowed to run at a time, we should ONLY schedule the true
                         * idle tasks, not user tasks at the idle priority. */
                        if( uxCurrentPriority < uxTopReadyPriority )
                        {
                            if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U )
                            {
                                continue;
                            }
                        }
                    }
                    #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */

                    if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
                    {
                        #if ( configUSE_CORE_AFFINITY == 1 )
                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                        #endif
                        {
                            /* If the task is not being executed by any core swap it in. */
                            pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING;
                            #if ( configUSE_CORE_AFFINITY == 1 )
                                pxPreviousTCB = pxCurrentTCBs[ xCoreID ];
                            #endif
                            pxTCB->xTaskRunState = xCoreID;
                            pxCurrentTCBs[ xCoreID ] = pxTCB;
                            xTaskScheduled = pdTRUE;
                        }
                    }
                    else if( pxTCB == pxCurrentTCBs[ xCoreID ] )
                    {
                        configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) );

                        #if ( configUSE_CORE_AFFINITY == 1 )
                            if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                        #endif
                        {
                            /* The task is already running on this core, mark it as scheduled. */
                            pxTCB->xTaskRunState = xCoreID;
                            xTaskScheduled = pdTRUE;
                        }
                    }
                    else
                    {
                        /* This task is running on the core other than xCoreID. */
                        mtCOVERAGE_TEST_MARKER();
                    }

                    if( xTaskScheduled != pdFALSE )
                    {
                        /* A task has been selected to run on this core. */
                        break;
                    }
                }
            }
            else
            {
                if( xDecrementTopPriority != pdFALSE )
                {
                    uxTopReadyPriority--;
                    #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
                    {
                        xPriorityDropped = pdTRUE;
                    }
                    #endif
                }
            }

            /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started.
             * The scheduler should be able to select a task to run when uxCurrentPriority
             * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow
             * tskIDLE_PRIORITY. */
            if( uxCurrentPriority > tskIDLE_PRIORITY )
            {
                uxCurrentPriority--;
            }
            else
            {
                /* This function is called when idle task is not created. Break the
                 * loop to prevent uxCurrentPriority overrun. */
                break;
            }
        }

        #if ( configRUN_MULTIPLE_PRIORITIES == 0 )
        {
            if( xTaskScheduled == pdTRUE )
            {
                if( xPriorityDropped != pdFALSE )
                {
                    /* There may be several ready tasks that were being prevented from running because there was
                     * a higher priority task running. Now that the last of the higher priority tasks is no longer
                     * running, make sure all the other idle tasks yield. */
                    BaseType_t x;

                    for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ )
                    {
                        if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                        {
                            prvYieldCore( x );
                        }
                    }
                }
            }
        }
        #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */

        #if ( configUSE_CORE_AFFINITY == 1 )
        {
            if( xTaskScheduled == pdTRUE )
            {
                if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) )
                {
                    /* A ready task was just evicted from this core. See if it can be
                     * scheduled on any other core. */
                    UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask;
                    BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority;
                    BaseType_t xLowestPriorityCore = -1;
                    BaseType_t x;

                    if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                    {
                        xLowestPriority = xLowestPriority - 1;
                    }

                    if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U )
                    {
                        /* pxPreviousTCB was removed from this core and this core is not excluded
                         * from it's core affinity mask.
                         *
                         * pxPreviousTCB is preempted by the new higher priority task
                         * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB,
                         * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ]
                         * is allowed to run. The reason is - when more than one cores are
                         * eligible for an incoming task, we preempt the core with the minimum
                         * priority task. Because this core (i.e. xCoreID) was preempted for
                         * pxCurrentTCBs[ xCoreID ], this means that all the others cores
                         * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority
                         * no lower than pxPreviousTCB's priority. Therefore, the only cores where
                         * which can be preempted for pxPreviousTCB are the ones where
                         * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously,
                         * pxPreviousTCB is allowed to run).
                         *
                         * This is an optimization which reduces the number of cores needed to be
                         * searched for pxPreviousTCB to run. */
                        uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask );
                    }
                    else
                    {
                        /* pxPreviousTCB's core affinity mask is changed and it is no longer
                         * allowed to run on this core. Searching all the cores in pxPreviousTCB's
                         * new core affinity mask to find a core on which it can run. */
                    }

                    uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U );

                    for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- )
                    {
                        UBaseType_t uxCore = ( UBaseType_t ) x;
                        BaseType_t xTaskPriority;

                        if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U )
                        {
                            xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority;

                            if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U )
                            {
                                xTaskPriority = xTaskPriority - ( BaseType_t ) 1;
                            }

                            uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore );

                            if( ( xTaskPriority < xLowestPriority ) &&
                                ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) &&
                                ( xYieldPendings[ uxCore ] == pdFALSE ) )
                            {
                                #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
                                    if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE )
                                #endif
                                {
                                    xLowestPriority = xTaskPriority;
                                    xLowestPriorityCore = ( BaseType_t ) uxCore;
                                }
                            }
                        }
                    }

                    if( xLowestPriorityCore >= 0 )
                    {
                        prvYieldCore( xLowestPriorityCore );
                    }
                }
            }
        }
        #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */
    }

#endif /* ( configNUMBER_OF_CORES > 1 ) */

/*-----------------------------------------------------------*/

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

    static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode,
                                        const char * const pcName,
                                        const configSTACK_DEPTH_TYPE uxStackDepth,
                                        void * const pvParameters,
                                        UBaseType_t uxPriority,
                                        StackType_t * const puxStackBuffer,
                                        StaticTask_t * const pxTaskBuffer,
                                        TaskHandle_t * const pxCreatedTask )
    {
        TCB_t * pxNewTCB;

        configASSERT( puxStackBuffer != NULL );
        configASSERT( pxTaskBuffer != NULL );

        #if ( configASSERT_DEFINED == 1 )
        {
            /* Sanity check that the size of the structure used to declare a
             * variable of type StaticTask_t equals the size of the real task
             * structure. */
            volatile size_t xSize = sizeof( StaticTask_t );
            configASSERT( xSize == sizeof( TCB_t ) );
            ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */
        }
        #endif /* configASSERT_DEFINED */

        if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
        {
            /* The memory used for the task's TCB and stack are passed into this
             * function - use them. */
            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            pxNewTCB = ( TCB_t * ) pxTaskBuffer;
            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );
            pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;

            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
            {
                /* Tasks can be created statically or dynamically, so note this
                 * task was created statically in case the task is later deleted. */
                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
            }
            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

            prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
        }
        else
        {
            pxNewTCB = NULL;
        }

        return pxNewTCB;
    }
/*-----------------------------------------------------------*/

    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
                                    const char * const pcName,
                                    const configSTACK_DEPTH_TYPE uxStackDepth,
                                    void * const pvParameters,
                                    UBaseType_t uxPriority,
                                    StackType_t * const puxStackBuffer,
                                    StaticTask_t * const pxTaskBuffer )
    {
        TaskHandle_t xReturn = NULL;
        TCB_t * pxNewTCB;

        traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );

        pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );

        if( pxNewTCB != NULL )
        {
            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
            }
            #endif

            prvAddNewTaskToReadyList( pxNewTCB );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTaskCreateStatic( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
        TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode,
                                                   const char * const pcName,
                                                   const configSTACK_DEPTH_TYPE uxStackDepth,
                                                   void * const pvParameters,
                                                   UBaseType_t uxPriority,
                                                   StackType_t * const puxStackBuffer,
                                                   StaticTask_t * const pxTaskBuffer,
                                                   UBaseType_t uxCoreAffinityMask )
        {
            TaskHandle_t xReturn = NULL;
            TCB_t * pxNewTCB;

            traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask );

            pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn );

            if( pxNewTCB != NULL )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;

                prvAddNewTaskToReadyList( pxNewTCB );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            traceRETURN_xTaskCreateStaticAffinitySet( xReturn );

            return xReturn;
        }
    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

#endif /* SUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
    static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition,
                                                  TaskHandle_t * const pxCreatedTask )
    {
        TCB_t * pxNewTCB;

        configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
        configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );

        if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
        {
            /* Allocate space for the TCB.  Where the memory comes from depends
             * on the implementation of the port malloc function and whether or
             * not static allocation is being used. */
            pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
            ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );

            /* Store the stack location in the TCB. */
            pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;

            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
            {
                /* Tasks can be created statically or dynamically, so note this
                 * task was created statically in case the task is later deleted. */
                pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
            }
            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

            prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
                                  pxTaskDefinition->pcName,
                                  pxTaskDefinition->usStackDepth,
                                  pxTaskDefinition->pvParameters,
                                  pxTaskDefinition->uxPriority,
                                  pxCreatedTask, pxNewTCB,
                                  pxTaskDefinition->xRegions );
        }
        else
        {
            pxNewTCB = NULL;
        }

        return pxNewTCB;
    }
/*-----------------------------------------------------------*/

    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                            TaskHandle_t * pxCreatedTask )
    {
        TCB_t * pxNewTCB;
        BaseType_t xReturn;

        traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );

        configASSERT( pxTaskDefinition != NULL );

        pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );

        if( pxNewTCB != NULL )
        {
            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
            }
            #endif

            prvAddNewTaskToReadyList( pxNewTCB );
            xReturn = pdPASS;
        }
        else
        {
            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
        }

        traceRETURN_xTaskCreateRestrictedStatic( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
        BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition,
                                                           UBaseType_t uxCoreAffinityMask,
                                                           TaskHandle_t * pxCreatedTask )
        {
            TCB_t * pxNewTCB;
            BaseType_t xReturn;

            traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );

            configASSERT( pxTaskDefinition != NULL );

            pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask );

            if( pxNewTCB != NULL )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;

                prvAddNewTaskToReadyList( pxNewTCB );
                xReturn = pdPASS;
            }
            else
            {
                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
            }

            traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn );

            return xReturn;
        }
    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
/*-----------------------------------------------------------*/

#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
    static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition,
                                            TaskHandle_t * const pxCreatedTask )
    {
        TCB_t * pxNewTCB;

        configASSERT( pxTaskDefinition->puxStackBuffer );

        if( pxTaskDefinition->puxStackBuffer != NULL )
        {
            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );

            if( pxNewTCB != NULL )
            {
                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );

                /* Store the stack location in the TCB. */
                pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;

                #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
                {
                    /* Tasks can be created statically or dynamically, so note
                     * this task had a statically allocated stack in case it is
                     * later deleted.  The TCB was allocated dynamically. */
                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
                }
                #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

                prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
                                      pxTaskDefinition->pcName,
                                      pxTaskDefinition->usStackDepth,
                                      pxTaskDefinition->pvParameters,
                                      pxTaskDefinition->uxPriority,
                                      pxCreatedTask, pxNewTCB,
                                      pxTaskDefinition->xRegions );
            }
        }
        else
        {
            pxNewTCB = NULL;
        }

        return pxNewTCB;
    }
/*-----------------------------------------------------------*/

    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                      TaskHandle_t * pxCreatedTask )
    {
        TCB_t * pxNewTCB;
        BaseType_t xReturn;

        traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );

        pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );

        if( pxNewTCB != NULL )
        {
            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
            }
            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

            prvAddNewTaskToReadyList( pxNewTCB );

            xReturn = pdPASS;
        }
        else
        {
            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
        }

        traceRETURN_xTaskCreateRestricted( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
        BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition,
                                                     UBaseType_t uxCoreAffinityMask,
                                                     TaskHandle_t * pxCreatedTask )
        {
            TCB_t * pxNewTCB;
            BaseType_t xReturn;

            traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask );

            pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask );

            if( pxNewTCB != NULL )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;

                prvAddNewTaskToReadyList( pxNewTCB );

                xReturn = pdPASS;
            }
            else
            {
                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
            }

            traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn );

            return xReturn;
        }
    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */


#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
    static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode,
                                  const char * const pcName,
                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                  void * const pvParameters,
                                  UBaseType_t uxPriority,
                                  TaskHandle_t * const pxCreatedTask )
    {
        TCB_t * pxNewTCB;

        /* If the stack grows down then allocate the stack then the TCB so the stack
         * does not grow into the TCB.  Likewise if the stack grows up then allocate
         * the TCB then the stack. */
        #if ( portSTACK_GROWTH > 0 )
        {
            /* Allocate space for the TCB.  Where the memory comes from depends on
             * the implementation of the port malloc function and whether or not static
             * allocation is being used. */
            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );

            if( pxNewTCB != NULL )
            {
                ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );

                /* Allocate space for the stack used by the task being created.
                 * The base of the stack memory stored in the TCB so the task can
                 * be deleted later if required. */
                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                /* coverity[misra_c_2012_rule_11_5_violation] */
                pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );

                if( pxNewTCB->pxStack == NULL )
                {
                    /* Could not allocate the stack.  Delete the allocated TCB. */
                    vPortFree( pxNewTCB );
                    pxNewTCB = NULL;
                }
            }
        }
        #else /* portSTACK_GROWTH */
        {
            StackType_t * pxStack;

            /* Allocate space for the stack used by the task being created. */
            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxStack = pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) );

            if( pxStack != NULL )
            {
                /* Allocate space for the TCB. */
                /* MISRA Ref 11.5.1 [Malloc memory assignment] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                /* coverity[misra_c_2012_rule_11_5_violation] */
                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );

                if( pxNewTCB != NULL )
                {
                    ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) );

                    /* Store the stack location in the TCB. */
                    pxNewTCB->pxStack = pxStack;
                }
                else
                {
                    /* The stack cannot be used as the TCB was not created.  Free
                     * it again. */
                    vPortFreeStack( pxStack );
                }
            }
            else
            {
                pxNewTCB = NULL;
            }
        }
        #endif /* portSTACK_GROWTH */

        if( pxNewTCB != NULL )
        {
            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
            {
                /* Tasks can be created statically or dynamically, so note this
                 * task was created dynamically in case it is later deleted. */
                pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
            }
            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

            prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
        }

        return pxNewTCB;
    }
/*-----------------------------------------------------------*/

    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
                            const char * const pcName,
                            const configSTACK_DEPTH_TYPE uxStackDepth,
                            void * const pvParameters,
                            UBaseType_t uxPriority,
                            TaskHandle_t * const pxCreatedTask )
    {
        TCB_t * pxNewTCB;
        BaseType_t xReturn;

        traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );

        pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );

        if( pxNewTCB != NULL )
        {
            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY;
            }
            #endif

            prvAddNewTaskToReadyList( pxNewTCB );
            xReturn = pdPASS;
        }
        else
        {
            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
        }

        traceRETURN_xTaskCreate( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
        BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode,
                                           const char * const pcName,
                                           const configSTACK_DEPTH_TYPE uxStackDepth,
                                           void * const pvParameters,
                                           UBaseType_t uxPriority,
                                           UBaseType_t uxCoreAffinityMask,
                                           TaskHandle_t * const pxCreatedTask )
        {
            TCB_t * pxNewTCB;
            BaseType_t xReturn;

            traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask );

            pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask );

            if( pxNewTCB != NULL )
            {
                /* Set the task's affinity before scheduling it. */
                pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask;

                prvAddNewTaskToReadyList( pxNewTCB );
                xReturn = pdPASS;
            }
            else
            {
                xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
            }

            traceRETURN_xTaskCreateAffinitySet( xReturn );

            return xReturn;
        }
    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
                                  const char * const pcName,
                                  const configSTACK_DEPTH_TYPE uxStackDepth,
                                  void * const pvParameters,
                                  UBaseType_t uxPriority,
                                  TaskHandle_t * const pxCreatedTask,
                                  TCB_t * pxNewTCB,
                                  const MemoryRegion_t * const xRegions )
{
    StackType_t * pxTopOfStack;
    UBaseType_t x;

    #if ( portUSING_MPU_WRAPPERS == 1 )
        /* Should the task be created in privileged mode? */
        BaseType_t xRunPrivileged;

        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
        {
            xRunPrivileged = pdTRUE;
        }
        else
        {
            xRunPrivileged = pdFALSE;
        }
        uxPriority &= ~portPRIVILEGE_BIT;
    #endif /* portUSING_MPU_WRAPPERS == 1 */

    /* Avoid dependency on memset() if it is not required. */
    #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
    {
        /* Fill the stack with a known value to assist debugging. */
        ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) uxStackDepth * sizeof( StackType_t ) );
    }
    #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */

    /* Calculate the top of stack address.  This depends on whether the stack
     * grows from high memory to low (as per the 80x86) or vice versa.
     * portSTACK_GROWTH is used to make the result positive or negative as required
     * by the port. */
    #if ( portSTACK_GROWTH < 0 )
    {
        pxTopOfStack = &( pxNewTCB->pxStack[ uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 ] );
        pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );

        /* Check the alignment of the calculated top of stack is correct. */
        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );

        #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
        {
            /* Also record the stack's high address, which may assist
             * debugging. */
            pxNewTCB->pxEndOfStack = pxTopOfStack;
        }
        #endif /* configRECORD_STACK_HIGH_ADDRESS */
    }
    #else /* portSTACK_GROWTH */
    {
        pxTopOfStack = pxNewTCB->pxStack;
        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );

        /* Check the alignment of the calculated top of stack is correct. */
        configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) );

        /* The other extreme of the stack space is required if stack checking is
         * performed. */
        pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 );
    }
    #endif /* portSTACK_GROWTH */

    /* Store the task name in the TCB. */
    if( pcName != NULL )
    {
        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
        {
            pxNewTCB->pcTaskName[ x ] = pcName[ x ];

            /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
             * configMAX_TASK_NAME_LEN characters just in case the memory after the
             * string is not accessible (extremely unlikely). */
            if( pcName[ x ] == ( char ) 0x00 )
            {
                break;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }

        /* Ensure the name string is terminated in the case that the string length
         * was greater or equal to configMAX_TASK_NAME_LEN. */
        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0';
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    /* This is used as an array index so must ensure it's not too large. */
    configASSERT( uxPriority < configMAX_PRIORITIES );

    if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
    {
        uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    pxNewTCB->uxPriority = uxPriority;
    #if ( configUSE_MUTEXES == 1 )
    {
        pxNewTCB->uxBasePriority = uxPriority;
    }
    #endif /* configUSE_MUTEXES */

    vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
    vListInitialiseItem( &( pxNewTCB->xEventListItem ) );

    /* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
     * back to  the containing TCB from a generic item in a list. */
    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );

    /* Event lists are always in priority order. */
    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority );
    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );

    #if ( portUSING_MPU_WRAPPERS == 1 )
    {
        vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, uxStackDepth );
    }
    #else
    {
        /* Avoid compiler warning about unreferenced parameter. */
        ( void ) xRegions;
    }
    #endif

    #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
    {
        /* Allocate and initialize memory for the task's TLS Block. */
        configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock, pxTopOfStack );
    }
    #endif

    /* Initialize the TCB stack to look as if the task was already running,
     * but had been interrupted by the scheduler.  The return address is set
     * to the start of the task function. Once the stack has been initialised
     * the top of stack variable is updated. */
    #if ( portUSING_MPU_WRAPPERS == 1 )
    {
        /* If the port has capability to detect stack overflow,
         * pass the stack end address to the stack initialization
         * function as well. */
        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
        {
            #if ( portSTACK_GROWTH < 0 )
            {
                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
            }
            #else /* portSTACK_GROWTH */
            {
                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
            }
            #endif /* portSTACK_GROWTH */
        }
        #else /* portHAS_STACK_OVERFLOW_CHECKING */
        {
            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) );
        }
        #endif /* portHAS_STACK_OVERFLOW_CHECKING */
    }
    #else /* portUSING_MPU_WRAPPERS */
    {
        /* If the port has capability to detect stack overflow,
         * pass the stack end address to the stack initialization
         * function as well. */
        #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
        {
            #if ( portSTACK_GROWTH < 0 )
            {
                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
            }
            #else /* portSTACK_GROWTH */
            {
                pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
            }
            #endif /* portSTACK_GROWTH */
        }
        #else /* portHAS_STACK_OVERFLOW_CHECKING */
        {
            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
        }
        #endif /* portHAS_STACK_OVERFLOW_CHECKING */
    }
    #endif /* portUSING_MPU_WRAPPERS */

    /* Initialize task state and task attributes. */
    #if ( configNUMBER_OF_CORES > 1 )
    {
        pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING;

        /* Is this an idle task? */
        if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvIdleTask ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) prvPassiveIdleTask ) )
        {
            pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE;
        }
    }
    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */

    if( pxCreatedTask != NULL )
    {
        /* Pass the handle out in an anonymous way.  The handle can be used to
         * change the created task's priority, delete the created task, etc.*/
        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }
}
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES == 1 )

    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
    {
        /* Ensure interrupts don't access the task lists while the lists are being
         * updated. */
        taskENTER_CRITICAL();
        {
            uxCurrentNumberOfTasks = ( UBaseType_t ) ( uxCurrentNumberOfTasks + 1U );

            if( pxCurrentTCB == NULL )
            {
                /* There are no other tasks, or all the other tasks are in
                 * the suspended state - make this the current task. */
                pxCurrentTCB = pxNewTCB;

                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
                {
                    /* This is the first task to be created so do the preliminary
                     * initialisation required.  We will not recover if this call
                     * fails, but we will report the failure. */
                    prvInitialiseTaskLists();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* If the scheduler is not already running, make this task the
                 * current task if it is the highest priority task to be created
                 * so far. */
                if( xSchedulerRunning == pdFALSE )
                {
                    if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
                    {
                        pxCurrentTCB = pxNewTCB;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }

            uxTaskNumber++;

            #if ( configUSE_TRACE_FACILITY == 1 )
            {
                /* Add a counter into the TCB for tracing only. */
                pxNewTCB->uxTCBNumber = uxTaskNumber;
            }
            #endif /* configUSE_TRACE_FACILITY */
            traceTASK_CREATE( pxNewTCB );

            prvAddTaskToReadyList( pxNewTCB );

            portSETUP_TCB( pxNewTCB );
        }
        taskEXIT_CRITICAL();

        if( xSchedulerRunning != pdFALSE )
        {
            /* If the created task is of a higher priority than the current task
             * then it should run now. */
            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }

#else /* #if ( configNUMBER_OF_CORES == 1 ) */

    static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
    {
        /* Ensure interrupts don't access the task lists while the lists are being
         * updated. */
        taskENTER_CRITICAL();
        {
            uxCurrentNumberOfTasks++;

            if( xSchedulerRunning == pdFALSE )
            {
                if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
                {
                    /* This is the first task to be created so do the preliminary
                     * initialisation required.  We will not recover if this call
                     * fails, but we will report the failure. */
                    prvInitialiseTaskLists();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                /* All the cores start with idle tasks before the SMP scheduler
                 * is running. Idle tasks are assigned to cores when they are
                 * created in prvCreateIdleTasks(). */
            }

            uxTaskNumber++;

            #if ( configUSE_TRACE_FACILITY == 1 )
            {
                /* Add a counter into the TCB for tracing only. */
                pxNewTCB->uxTCBNumber = uxTaskNumber;
            }
            #endif /* configUSE_TRACE_FACILITY */
            traceTASK_CREATE( pxNewTCB );

            prvAddTaskToReadyList( pxNewTCB );

            portSETUP_TCB( pxNewTCB );

            if( xSchedulerRunning != pdFALSE )
            {
                /* If the created task is of a higher priority than another
                 * currently running task and preemption is on then it should
                 * run now. */
                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL();
    }

#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
/*-----------------------------------------------------------*/

#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )

    static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue,
                                                        size_t n )
    {
        size_t uxCharsWritten;

        if( iSnprintfReturnValue < 0 )
        {
            /* Encoding error - Return 0 to indicate that nothing
             * was written to the buffer. */
            uxCharsWritten = 0;
        }
        else if( iSnprintfReturnValue >= ( int ) n )
        {
            /* This is the case when the supplied buffer is not
             * large to hold the generated string. Return the
             * number of characters actually written without
             * counting the terminating NULL character. */
            uxCharsWritten = n - 1U;
        }
        else
        {
            /* Complete string was written to the buffer. */
            uxCharsWritten = ( size_t ) iSnprintfReturnValue;
        }

        return uxCharsWritten;
    }

#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

    void vTaskDelete( TaskHandle_t xTaskToDelete )
    {
        TCB_t * pxTCB;
        BaseType_t xDeleteTCBInIdleTask = pdFALSE;
        BaseType_t xTaskIsRunningOrYielding;

        traceENTER_vTaskDelete( xTaskToDelete );

        taskENTER_CRITICAL();
        {
            /* If null is passed in here then it is the calling task that is
             * being deleted. */
            pxTCB = prvGetTCBFromHandle( xTaskToDelete );

            /* Remove task from the ready/delayed list. */
            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
            {
                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* Is the task waiting on an event also? */
            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
            {
                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* Increment the uxTaskNumber also so kernel aware debuggers can
             * detect that the task lists need re-generating.  This is done before
             * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
             * not return. */
            uxTaskNumber++;

            /* Use temp variable as distinct sequence points for reading volatile
             * variables prior to a logical operator to ensure compliance with
             * MISRA C 2012 Rule 13.5. */
            xTaskIsRunningOrYielding = taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB );

            /* If the task is running (or yielding), we must add it to the
             * termination list so that an idle task can delete it when it is
             * no longer running. */
            if( ( xSchedulerRunning != pdFALSE ) && ( xTaskIsRunningOrYielding != pdFALSE ) )
            {
                /* A running task or a task which is scheduled to yield is being
                 * deleted. This cannot complete when the task is still running
                 * on a core, as a context switch to another task is required.
                 * Place the task in the termination list. The idle task will check
                 * the termination list and free up any memory allocated by the
                 * scheduler for the TCB and stack of the deleted task. */
                vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );

                /* Increment the ucTasksDeleted variable so the idle task knows
                 * there is a task that has been deleted and that it should therefore
                 * check the xTasksWaitingTermination list. */
                ++uxDeletedTasksWaitingCleanUp;

                /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
                 * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
                traceTASK_DELETE( pxTCB );

                /* Delete the task TCB in idle task. */
                xDeleteTCBInIdleTask = pdTRUE;

                /* The pre-delete hook is primarily for the Windows simulator,
                 * in which Windows specific clean up operations are performed,
                 * after which it is not possible to yield away from this task -
                 * hence xYieldPending is used to latch that a context switch is
                 * required. */
                #if ( configNUMBER_OF_CORES == 1 )
                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) );
                #else
                    portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) );
                #endif

                /* In the case of SMP, it is possible that the task being deleted
                 * is running on another core. We must evict the task before
                 * exiting the critical section to ensure that the task cannot
                 * take an action which puts it back on ready/state/event list,
                 * thereby nullifying the delete operation. Once evicted, the
                 * task won't be scheduled ever as it will no longer be on the
                 * ready list. */
                #if ( configNUMBER_OF_CORES > 1 )
                {
                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                    {
                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
                        {
                            configASSERT( uxSchedulerSuspended == 0 );
                            taskYIELD_WITHIN_API();
                        }
                        else
                        {
                            prvYieldCore( pxTCB->xTaskRunState );
                        }
                    }
                }
                #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
            }
            else
            {
                --uxCurrentNumberOfTasks;
                traceTASK_DELETE( pxTCB );

                /* Reset the next expected unblock time in case it referred to
                 * the task that has just been deleted. */
                prvResetNextTaskUnblockTime();
            }
        }
        taskEXIT_CRITICAL();

        /* If the task is not deleting itself, call prvDeleteTCB from outside of
         * critical section. If a task deletes itself, prvDeleteTCB is called
         * from prvCheckTasksWaitingTermination which is called from Idle task. */
        if( xDeleteTCBInIdleTask != pdTRUE )
        {
            prvDeleteTCB( pxTCB );
        }

        /* Force a reschedule if it is the currently running task that has just
         * been deleted. */
        #if ( configNUMBER_OF_CORES == 1 )
        {
            if( xSchedulerRunning != pdFALSE )
            {
                if( pxTCB == pxCurrentTCB )
                {
                    configASSERT( uxSchedulerSuspended == 0 );
                    taskYIELD_WITHIN_API();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

        traceRETURN_vTaskDelete();
    }

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

#if ( INCLUDE_xTaskDelayUntil == 1 )

    BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
                                const TickType_t xTimeIncrement )
    {
        TickType_t xTimeToWake;
        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;

        traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );

        configASSERT( pxPreviousWakeTime );
        configASSERT( ( xTimeIncrement > 0U ) );

        vTaskSuspendAll();
        {
            /* Minor optimisation.  The tick count cannot change in this
             * block. */
            const TickType_t xConstTickCount = xTickCount;

            configASSERT( uxSchedulerSuspended == 1U );

            /* Generate the tick time at which the task wants to wake. */
            xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;

            if( xConstTickCount < *pxPreviousWakeTime )
            {
                /* The tick count has overflowed since this function was
                 * lasted called.  In this case the only time we should ever
                 * actually delay is if the wake time has also  overflowed,
                 * and the wake time is greater than the tick time.  When this
                 * is the case it is as if neither time had overflowed. */
                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
                {
                    xShouldDelay = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                /* The tick time has not overflowed.  In this case we will
                 * delay if either the wake time has overflowed, and/or the
                 * tick time is less than the wake time. */
                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
                {
                    xShouldDelay = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }

            /* Update the wake time ready for the next call. */
            *pxPreviousWakeTime = xTimeToWake;

            if( xShouldDelay != pdFALSE )
            {
                traceTASK_DELAY_UNTIL( xTimeToWake );

                /* prvAddCurrentTaskToDelayedList() needs the block time, not
                 * the time to wake, so subtract the current tick count. */
                prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        xAlreadyYielded = xTaskResumeAll();

        /* Force a reschedule if xTaskResumeAll has not already done so, we may
         * have put ourselves to sleep. */
        if( xAlreadyYielded == pdFALSE )
        {
            taskYIELD_WITHIN_API();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTaskDelayUntil( xShouldDelay );

        return xShouldDelay;
    }

#endif /* INCLUDE_xTaskDelayUntil */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

    void vTaskDelay( const TickType_t xTicksToDelay )
    {
        BaseType_t xAlreadyYielded = pdFALSE;

        traceENTER_vTaskDelay( xTicksToDelay );

        /* A delay time of zero just forces a reschedule. */
        if( xTicksToDelay > ( TickType_t ) 0U )
        {
            vTaskSuspendAll();
            {
                configASSERT( uxSchedulerSuspended == 1U );

                traceTASK_DELAY();

                /* A task that is removed from the event list while the
                 * scheduler is suspended will not get placed in the ready
                 * list or removed from the blocked list until the scheduler
                 * is resumed.
                 *
                 * This task cannot be in an event list as it is the currently
                 * executing task. */
                prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
            }
            xAlreadyYielded = xTaskResumeAll();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        /* Force a reschedule if xTaskResumeAll has not already done so, we may
         * have put ourselves to sleep. */
        if( xAlreadyYielded == pdFALSE )
        {
            taskYIELD_WITHIN_API();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskDelay();
    }

#endif /* INCLUDE_vTaskDelay */
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )

    eTaskState eTaskGetState( TaskHandle_t xTask )
    {
        eTaskState eReturn;
        List_t const * pxStateList;
        List_t const * pxEventList;
        List_t const * pxDelayedList;
        List_t const * pxOverflowedDelayedList;
        const TCB_t * const pxTCB = xTask;

        traceENTER_eTaskGetState( xTask );

        configASSERT( pxTCB );

        #if ( configNUMBER_OF_CORES == 1 )
            if( pxTCB == pxCurrentTCB )
            {
                /* The task calling this function is querying its own state. */
                eReturn = eRunning;
            }
            else
        #endif
        {
            taskENTER_CRITICAL();
            {
                pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
                pxEventList = listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) );
                pxDelayedList = pxDelayedTaskList;
                pxOverflowedDelayedList = pxOverflowDelayedTaskList;
            }
            taskEXIT_CRITICAL();

            if( pxEventList == &xPendingReadyList )
            {
                /* The task has been placed on the pending ready list, so its
                 * state is eReady regardless of what list the task's state list
                 * item is currently placed on. */
                eReturn = eReady;
            }
            else if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
            {
                /* The task being queried is referenced from one of the Blocked
                 * lists. */
                eReturn = eBlocked;
            }

            #if ( INCLUDE_vTaskSuspend == 1 )
                else if( pxStateList == &xSuspendedTaskList )
                {
                    /* The task being queried is referenced from the suspended
                     * list.  Is it genuinely suspended or is it blocked
                     * indefinitely? */
                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
                    {
                        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
                        {
                            BaseType_t x;

                            /* The task does not appear on the event list item of
                             * and of the RTOS objects, but could still be in the
                             * blocked state if it is waiting on its notification
                             * rather than waiting on an object.  If not, is
                             * suspended. */
                            eReturn = eSuspended;

                            for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                            {
                                if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                                {
                                    eReturn = eBlocked;
                                    break;
                                }
                            }
                        }
                        #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                        {
                            eReturn = eSuspended;
                        }
                        #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                    }
                    else
                    {
                        eReturn = eBlocked;
                    }
                }
            #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */

            #if ( INCLUDE_vTaskDelete == 1 )
                else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
                {
                    /* The task being queried is referenced from the deleted
                     * tasks list, or it is not referenced from any lists at
                     * all. */
                    eReturn = eDeleted;
                }
            #endif

            else
            {
                #if ( configNUMBER_OF_CORES == 1 )
                {
                    /* If the task is not in any other state, it must be in the
                     * Ready (including pending ready) state. */
                    eReturn = eReady;
                }
                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                {
                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                    {
                        /* Is it actively running on a core? */
                        eReturn = eRunning;
                    }
                    else
                    {
                        /* If the task is not in any other state, it must be in the
                         * Ready (including pending ready) state. */
                        eReturn = eReady;
                    }
                }
                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
            }
        }

        traceRETURN_eTaskGetState( eReturn );

        return eReturn;
    }

#endif /* INCLUDE_eTaskGetState */
/*-----------------------------------------------------------*/

#if ( INCLUDE_uxTaskPriorityGet == 1 )

    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
    {
        TCB_t const * pxTCB;
        UBaseType_t uxReturn;

        traceENTER_uxTaskPriorityGet( xTask );

        taskENTER_CRITICAL();
        {
            /* If null is passed in here then it is the priority of the task
             * that called uxTaskPriorityGet() that is being queried. */
            pxTCB = prvGetTCBFromHandle( xTask );
            uxReturn = pxTCB->uxPriority;
        }
        taskEXIT_CRITICAL();

        traceRETURN_uxTaskPriorityGet( uxReturn );

        return uxReturn;
    }

#endif /* INCLUDE_uxTaskPriorityGet */
/*-----------------------------------------------------------*/

#if ( INCLUDE_uxTaskPriorityGet == 1 )

    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
    {
        TCB_t const * pxTCB;
        UBaseType_t uxReturn;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_uxTaskPriorityGetFromISR( xTask );

        /* RTOS ports that support interrupt nesting have the concept of a
         * maximum  system call (or maximum API call) interrupt priority.
         * Interrupts that are  above the maximum system call priority are keep
         * permanently enabled, even when the RTOS kernel is in a critical section,
         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
         * is defined in FreeRTOSConfig.h then
         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
         * failure if a FreeRTOS API function is called from an interrupt that has
         * been assigned a priority above the configured maximum system call
         * priority.  Only FreeRTOS functions that end in FromISR can be called
         * from interrupts  that have been assigned a priority at or (logically)
         * below the maximum system call interrupt priority.  FreeRTOS maintains a
         * separate interrupt safe API to ensure interrupt entry is as fast and as
         * simple as possible.  More information (albeit Cortex-M specific) is
         * provided on the following link:
         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
        {
            /* If null is passed in here then it is the priority of the calling
             * task that is being queried. */
            pxTCB = prvGetTCBFromHandle( xTask );
            uxReturn = pxTCB->uxPriority;
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_uxTaskPriorityGetFromISR( uxReturn );

        return uxReturn;
    }

#endif /* INCLUDE_uxTaskPriorityGet */
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )

    UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask )
    {
        TCB_t const * pxTCB;
        UBaseType_t uxReturn;

        traceENTER_uxTaskBasePriorityGet( xTask );

        taskENTER_CRITICAL();
        {
            /* If null is passed in here then it is the base priority of the task
             * that called uxTaskBasePriorityGet() that is being queried. */
            pxTCB = prvGetTCBFromHandle( xTask );
            uxReturn = pxTCB->uxBasePriority;
        }
        taskEXIT_CRITICAL();

        traceRETURN_uxTaskBasePriorityGet( uxReturn );

        return uxReturn;
    }

#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) )

    UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask )
    {
        TCB_t const * pxTCB;
        UBaseType_t uxReturn;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_uxTaskBasePriorityGetFromISR( xTask );

        /* RTOS ports that support interrupt nesting have the concept of a
         * maximum  system call (or maximum API call) interrupt priority.
         * Interrupts that are  above the maximum system call priority are keep
         * permanently enabled, even when the RTOS kernel is in a critical section,
         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
         * is defined in FreeRTOSConfig.h then
         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
         * failure if a FreeRTOS API function is called from an interrupt that has
         * been assigned a priority above the configured maximum system call
         * priority.  Only FreeRTOS functions that end in FromISR can be called
         * from interrupts  that have been assigned a priority at or (logically)
         * below the maximum system call interrupt priority.  FreeRTOS maintains a
         * separate interrupt safe API to ensure interrupt entry is as fast and as
         * simple as possible.  More information (albeit Cortex-M specific) is
         * provided on the following link:
         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
        {
            /* If null is passed in here then it is the base priority of the calling
             * task that is being queried. */
            pxTCB = prvGetTCBFromHandle( xTask );
            uxReturn = pxTCB->uxBasePriority;
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn );

        return uxReturn;
    }

#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskPrioritySet == 1 )

    void vTaskPrioritySet( TaskHandle_t xTask,
                           UBaseType_t uxNewPriority )
    {
        TCB_t * pxTCB;
        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
        BaseType_t xYieldRequired = pdFALSE;

        #if ( configNUMBER_OF_CORES > 1 )
            BaseType_t xYieldForTask = pdFALSE;
        #endif

        traceENTER_vTaskPrioritySet( xTask, uxNewPriority );

        configASSERT( uxNewPriority < configMAX_PRIORITIES );

        /* Ensure the new priority is valid. */
        if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
        {
            uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        taskENTER_CRITICAL();
        {
            /* If null is passed in here then it is the priority of the calling
             * task that is being changed. */
            pxTCB = prvGetTCBFromHandle( xTask );

            traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );

            #if ( configUSE_MUTEXES == 1 )
            {
                uxCurrentBasePriority = pxTCB->uxBasePriority;
            }
            #else
            {
                uxCurrentBasePriority = pxTCB->uxPriority;
            }
            #endif

            if( uxCurrentBasePriority != uxNewPriority )
            {
                /* The priority change may have readied a task of higher
                 * priority than a running task. */
                if( uxNewPriority > uxCurrentBasePriority )
                {
                    #if ( configNUMBER_OF_CORES == 1 )
                    {
                        if( pxTCB != pxCurrentTCB )
                        {
                            /* The priority of a task other than the currently
                             * running task is being raised.  Is the priority being
                             * raised above that of the running task? */
                            if( uxNewPriority > pxCurrentTCB->uxPriority )
                            {
                                xYieldRequired = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        else
                        {
                            /* The priority of the running task is being raised,
                             * but the running task must already be the highest
                             * priority task able to run so no yield is required. */
                        }
                    }
                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                    {
                        /* The priority of a task is being raised so
                         * perform a yield for this task later. */
                        xYieldForTask = pdTRUE;
                    }
                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                }
                else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                {
                    /* Setting the priority of a running task down means
                     * there may now be another task of higher priority that
                     * is ready to execute. */
                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
                        if( pxTCB->xPreemptionDisable == pdFALSE )
                    #endif
                    {
                        xYieldRequired = pdTRUE;
                    }
                }
                else
                {
                    /* Setting the priority of any other task down does not
                     * require a yield as the running task must be above the
                     * new priority of the task being modified. */
                }

                /* Remember the ready list the task might be referenced from
                 * before its uxPriority member is changed so the
                 * taskRESET_READY_PRIORITY() macro can function correctly. */
                uxPriorityUsedOnEntry = pxTCB->uxPriority;

                #if ( configUSE_MUTEXES == 1 )
                {
                    /* Only change the priority being used if the task is not
                     * currently using an inherited priority or the new priority
                     * is bigger than the inherited priority. */
                    if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) )
                    {
                        pxTCB->uxPriority = uxNewPriority;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* The base priority gets set whatever. */
                    pxTCB->uxBasePriority = uxNewPriority;
                }
                #else /* if ( configUSE_MUTEXES == 1 ) */
                {
                    pxTCB->uxPriority = uxNewPriority;
                }
                #endif /* if ( configUSE_MUTEXES == 1 ) */

                /* Only reset the event list item value if the value is not
                 * being used for anything else. */
                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                {
                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                /* If the task is in the blocked or suspended list we need do
                 * nothing more than change its priority variable. However, if
                 * the task is in a ready list it needs to be removed and placed
                 * in the list appropriate to its new priority. */
                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
                {
                    /* The task is currently in its ready list - remove before
                     * adding it to its new ready list.  As we are in a critical
                     * section we can do this even if the scheduler is suspended. */
                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
                    {
                        /* It is known that the task is in its ready list so
                         * there is no need to check again and the port level
                         * reset macro can be called directly. */
                        portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    prvAddTaskToReadyList( pxTCB );
                }
                else
                {
                    #if ( configNUMBER_OF_CORES == 1 )
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                    #else
                    {
                        /* It's possible that xYieldForTask was already set to pdTRUE because
                         * its priority is being raised. However, since it is not in a ready list
                         * we don't actually need to yield for it. */
                        xYieldForTask = pdFALSE;
                    }
                    #endif
                }

                if( xYieldRequired != pdFALSE )
                {
                    /* The running task priority is set down. Request the task to yield. */
                    taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB );
                }
                else
                {
                    #if ( configNUMBER_OF_CORES > 1 )
                        if( xYieldForTask != pdFALSE )
                        {
                            /* The priority of the task is being raised. If a running
                             * task has priority lower than this task, it should yield
                             * for this task. */
                            taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
                        }
                        else
                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }

                /* Remove compiler warning about unused variables when the port
                 * optimised task selection is not being used. */
                ( void ) uxPriorityUsedOnEntry;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskPrioritySet();
    }

#endif /* INCLUDE_vTaskPrioritySet */
/*-----------------------------------------------------------*/

#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    void vTaskCoreAffinitySet( const TaskHandle_t xTask,
                               UBaseType_t uxCoreAffinityMask )
    {
        TCB_t * pxTCB;
        BaseType_t xCoreID;
        UBaseType_t uxPrevCoreAffinityMask;

        #if ( configUSE_PREEMPTION == 1 )
            UBaseType_t uxPrevNotAllowedCores;
        #endif

        traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask );

        taskENTER_CRITICAL();
        {
            pxTCB = prvGetTCBFromHandle( xTask );

            uxPrevCoreAffinityMask = pxTCB->uxCoreAffinityMask;
            pxTCB->uxCoreAffinityMask = uxCoreAffinityMask;

            if( xSchedulerRunning != pdFALSE )
            {
                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                {
                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;

                    /* If the task can no longer run on the core it was running,
                     * request the core to yield. */
                    if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U )
                    {
                        prvYieldCore( xCoreID );
                    }
                }
                else
                {
                    #if ( configUSE_PREEMPTION == 1 )
                    {
                        /* Calculate the cores on which this task was not allowed to
                         * run previously. */
                        uxPrevNotAllowedCores = ( ~uxPrevCoreAffinityMask ) & ( ( 1U << configNUMBER_OF_CORES ) - 1U );

                        /* Does the new core mask enables this task to run on any of the
                         * previously not allowed cores? If yes, check if this task can be
                         * scheduled on any of those cores. */
                        if( ( uxPrevNotAllowedCores & uxCoreAffinityMask ) != 0U )
                        {
                            prvYieldForTask( pxTCB );
                        }
                    }
                    #else /* #if( configUSE_PREEMPTION == 1 ) */
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                    #endif /* #if( configUSE_PREEMPTION == 1 ) */
                }
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskCoreAffinitySet();
    }
#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
    UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask )
    {
        const TCB_t * pxTCB;
        UBaseType_t uxCoreAffinityMask;

        traceENTER_vTaskCoreAffinityGet( xTask );

        taskENTER_CRITICAL();
        {
            pxTCB = prvGetTCBFromHandle( xTask );
            uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask );

        return uxCoreAffinityMask;
    }
#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

/*-----------------------------------------------------------*/

#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )

    void vTaskPreemptionDisable( const TaskHandle_t xTask )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskPreemptionDisable( xTask );

        taskENTER_CRITICAL();
        {
            pxTCB = prvGetTCBFromHandle( xTask );

            pxTCB->xPreemptionDisable = pdTRUE;
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskPreemptionDisable();
    }

#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )

    void vTaskPreemptionEnable( const TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        BaseType_t xCoreID;

        traceENTER_vTaskPreemptionEnable( xTask );

        taskENTER_CRITICAL();
        {
            pxTCB = prvGetTCBFromHandle( xTask );

            pxTCB->xPreemptionDisable = pdFALSE;

            if( xSchedulerRunning != pdFALSE )
            {
                if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                {
                    xCoreID = ( BaseType_t ) pxTCB->xTaskRunState;
                    prvYieldCore( xCoreID );
                }
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskPreemptionEnable();
    }

#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskSuspend == 1 )

    void vTaskSuspend( TaskHandle_t xTaskToSuspend )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskSuspend( xTaskToSuspend );

        taskENTER_CRITICAL();
        {
            /* If null is passed in here then it is the running task that is
             * being suspended. */
            pxTCB = prvGetTCBFromHandle( xTaskToSuspend );

            traceTASK_SUSPEND( pxTCB );

            /* Remove task from the ready/delayed list and place in the
             * suspended list. */
            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
            {
                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* Is the task waiting on an event also? */
            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
            {
                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );

            #if ( configUSE_TASK_NOTIFICATIONS == 1 )
            {
                BaseType_t x;

                for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                {
                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                    {
                        /* The task was blocked to wait for a notification, but is
                         * now suspended, so no notification was received. */
                        pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
                    }
                }
            }
            #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */

            /* In the case of SMP, it is possible that the task being suspended
             * is running on another core. We must evict the task before
             * exiting the critical section to ensure that the task cannot
             * take an action which puts it back on ready/state/event list,
             * thereby nullifying the suspend operation. Once evicted, the
             * task won't be scheduled before it is resumed as it will no longer
             * be on the ready list. */
            #if ( configNUMBER_OF_CORES > 1 )
            {
                if( xSchedulerRunning != pdFALSE )
                {
                    /* Reset the next expected unblock time in case it referred to the
                     * task that is now in the Suspended state. */
                    prvResetNextTaskUnblockTime();

                    if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                    {
                        if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() )
                        {
                            /* The current task has just been suspended. */
                            configASSERT( uxSchedulerSuspended == 0 );
                            vTaskYieldWithinAPI();
                        }
                        else
                        {
                            prvYieldCore( pxTCB->xTaskRunState );
                        }
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            #endif /* #if ( configNUMBER_OF_CORES > 1 ) */
        }
        taskEXIT_CRITICAL();

        #if ( configNUMBER_OF_CORES == 1 )
        {
            UBaseType_t uxCurrentListLength;

            if( xSchedulerRunning != pdFALSE )
            {
                /* Reset the next expected unblock time in case it referred to the
                 * task that is now in the Suspended state. */
                taskENTER_CRITICAL();
                {
                    prvResetNextTaskUnblockTime();
                }
                taskEXIT_CRITICAL();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            if( pxTCB == pxCurrentTCB )
            {
                if( xSchedulerRunning != pdFALSE )
                {
                    /* The current task has just been suspended. */
                    configASSERT( uxSchedulerSuspended == 0 );
                    portYIELD_WITHIN_API();
                }
                else
                {
                    /* The scheduler is not running, but the task that was pointed
                     * to by pxCurrentTCB has just been suspended and pxCurrentTCB
                     * must be adjusted to point to a different task. */

                    /* Use a temp variable as a distinct sequence point for reading
                     * volatile variables prior to a comparison to ensure compliance
                     * with MISRA C 2012 Rule 13.2. */
                    uxCurrentListLength = listCURRENT_LIST_LENGTH( &xSuspendedTaskList );

                    if( uxCurrentListLength == uxCurrentNumberOfTasks )
                    {
                        /* No other tasks are ready, so set pxCurrentTCB back to
                         * NULL so when the next task is created pxCurrentTCB will
                         * be set to point to it no matter what its relative priority
                         * is. */
                        pxCurrentTCB = NULL;
                    }
                    else
                    {
                        vTaskSwitchContext();
                    }
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

        traceRETURN_vTaskSuspend();
    }

#endif /* INCLUDE_vTaskSuspend */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskSuspend == 1 )

    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
    {
        BaseType_t xReturn = pdFALSE;
        const TCB_t * const pxTCB = xTask;

        /* Accesses xPendingReadyList so must be called from a critical
         * section. */

        /* It does not make sense to check if the calling task is suspended. */
        configASSERT( xTask );

        /* Is the task being resumed actually in the suspended list? */
        if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
        {
            /* Has the task already been resumed from within an ISR? */
            if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
            {
                /* Is it in the suspended list because it is in the Suspended
                 * state, or because it is blocked with no timeout? */
                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
                {
                    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
                    {
                        BaseType_t x;

                        /* The task does not appear on the event list item of
                         * and of the RTOS objects, but could still be in the
                         * blocked state if it is waiting on its notification
                         * rather than waiting on an object.  If not, is
                         * suspended. */
                        xReturn = pdTRUE;

                        for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                        {
                            if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                            {
                                xReturn = pdFALSE;
                                break;
                            }
                        }
                    }
                    #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                    {
                        xReturn = pdTRUE;
                    }
                    #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        return xReturn;
    }

#endif /* INCLUDE_vTaskSuspend */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskSuspend == 1 )

    void vTaskResume( TaskHandle_t xTaskToResume )
    {
        TCB_t * const pxTCB = xTaskToResume;

        traceENTER_vTaskResume( xTaskToResume );

        /* It does not make sense to resume the calling task. */
        configASSERT( xTaskToResume );

        #if ( configNUMBER_OF_CORES == 1 )

            /* The parameter cannot be NULL as it is impossible to resume the
             * currently executing task. */
            if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
        #else

            /* The parameter cannot be NULL as it is impossible to resume the
             * currently executing task. It is also impossible to resume a task
             * that is actively running on another core but it is not safe
             * to check their run state here. Therefore, we get into a critical
             * section and check if the task is actually suspended or not. */
            if( pxTCB != NULL )
        #endif
        {
            taskENTER_CRITICAL();
            {
                if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
                {
                    traceTASK_RESUME( pxTCB );

                    /* The ready list can be accessed even if the scheduler is
                     * suspended because this is inside a critical section. */
                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                    prvAddTaskToReadyList( pxTCB );

                    /* This yield may not cause the task just resumed to run,
                     * but will leave the lists in the correct state for the
                     * next yield. */
                    taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            taskEXIT_CRITICAL();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskResume();
    }

#endif /* INCLUDE_vTaskSuspend */

/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )

    BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
    {
        BaseType_t xYieldRequired = pdFALSE;
        TCB_t * const pxTCB = xTaskToResume;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_xTaskResumeFromISR( xTaskToResume );

        configASSERT( xTaskToResume );

        /* RTOS ports that support interrupt nesting have the concept of a
         * maximum  system call (or maximum API call) interrupt priority.
         * Interrupts that are  above the maximum system call priority are keep
         * permanently enabled, even when the RTOS kernel is in a critical section,
         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
         * is defined in FreeRTOSConfig.h then
         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
         * failure if a FreeRTOS API function is called from an interrupt that has
         * been assigned a priority above the configured maximum system call
         * priority.  Only FreeRTOS functions that end in FromISR can be called
         * from interrupts  that have been assigned a priority at or (logically)
         * below the maximum system call interrupt priority.  FreeRTOS maintains a
         * separate interrupt safe API to ensure interrupt entry is as fast and as
         * simple as possible.  More information (albeit Cortex-M specific) is
         * provided on the following link:
         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
        {
            if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
            {
                traceTASK_RESUME_FROM_ISR( pxTCB );

                /* Check the ready lists can be accessed. */
                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
                {
                    #if ( configNUMBER_OF_CORES == 1 )
                    {
                        /* Ready lists can be accessed so move the task from the
                         * suspended list to the ready list directly. */
                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                        {
                            xYieldRequired = pdTRUE;

                            /* Mark that a yield is pending in case the user is not
                             * using the return value to initiate a context switch
                             * from the ISR using the port specific portYIELD_FROM_ISR(). */
                            xYieldPendings[ 0 ] = pdTRUE;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                    prvAddTaskToReadyList( pxTCB );
                }
                else
                {
                    /* The delayed or ready lists cannot be accessed so the task
                     * is held in the pending ready list until the scheduler is
                     * unsuspended. */
                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                }

                #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) )
                {
                    prvYieldForTask( pxTCB );

                    if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
                    {
                        xYieldRequired = pdTRUE;
                    }
                }
                #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_xTaskResumeFromISR( xYieldRequired );

        return xYieldRequired;
    }

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

static BaseType_t prvCreateIdleTasks( void )
{
    BaseType_t xReturn = pdPASS;
    BaseType_t xCoreID;
    char cIdleName[ configMAX_TASK_NAME_LEN ];
    TaskFunction_t pxIdleTaskFunction = NULL;
    BaseType_t xIdleTaskNameIndex;

    for( xIdleTaskNameIndex = ( BaseType_t ) 0; xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN; xIdleTaskNameIndex++ )
    {
        cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ];

        /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
         * configMAX_TASK_NAME_LEN characters just in case the memory after the
         * string is not accessible (extremely unlikely). */
        if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 )
        {
            break;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }

    /* Add each idle task at the lowest priority. */
    for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
    {
        #if ( configNUMBER_OF_CORES == 1 )
        {
            pxIdleTaskFunction = prvIdleTask;
        }
        #else /* #if (  configNUMBER_OF_CORES == 1 ) */
        {
            /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks
             * are also created to ensure that each core has an idle task to
             * run when no other task is available to run. */
            if( xCoreID == 0 )
            {
                pxIdleTaskFunction = prvIdleTask;
            }
            else
            {
                pxIdleTaskFunction = prvPassiveIdleTask;
            }
        }
        #endif /* #if (  configNUMBER_OF_CORES == 1 ) */

        /* Update the idle task name with suffix to differentiate the idle tasks.
         * This function is not required in single core FreeRTOS since there is
         * only one idle task. */
        #if ( configNUMBER_OF_CORES > 1 )
        {
            /* Append the idle task number to the end of the name if there is space. */
            if( xIdleTaskNameIndex < ( BaseType_t ) configMAX_TASK_NAME_LEN )
            {
                cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' );

                /* And append a null character if there is space. */
                if( ( xIdleTaskNameIndex + 1 ) < ( BaseType_t ) configMAX_TASK_NAME_LEN )
                {
                    cIdleName[ xIdleTaskNameIndex + 1 ] = '\0';
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* if ( configNUMBER_OF_CORES > 1 ) */

        #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
        {
            StaticTask_t * pxIdleTaskTCBBuffer = NULL;
            StackType_t * pxIdleTaskStackBuffer = NULL;
            configSTACK_DEPTH_TYPE uxIdleTaskStackSize;

            /* The Idle task is created using user provided RAM - obtain the
             * address of the RAM then create the idle task. */
            #if ( configNUMBER_OF_CORES == 1 )
            {
                vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
            }
            #else
            {
                if( xCoreID == 0 )
                {
                    vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize );
                }
                else
                {
                    vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, ( BaseType_t ) ( xCoreID - 1 ) );
                }
            }
            #endif /* if ( configNUMBER_OF_CORES == 1 ) */
            xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction,
                                                             cIdleName,
                                                             uxIdleTaskStackSize,
                                                             ( void * ) NULL,
                                                             portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
                                                             pxIdleTaskStackBuffer,
                                                             pxIdleTaskTCBBuffer );

            if( xIdleTaskHandles[ xCoreID ] != NULL )
            {
                xReturn = pdPASS;
            }
            else
            {
                xReturn = pdFAIL;
            }
        }
        #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
        {
            /* The Idle task is being created using dynamically allocated RAM. */
            xReturn = xTaskCreate( pxIdleTaskFunction,
                                   cIdleName,
                                   configMINIMAL_STACK_SIZE,
                                   ( void * ) NULL,
                                   portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
                                   &xIdleTaskHandles[ xCoreID ] );
        }
        #endif /* configSUPPORT_STATIC_ALLOCATION */

        /* Break the loop if any of the idle task is failed to be created. */
        if( xReturn == pdFAIL )
        {
            break;
        }
        else
        {
            #if ( configNUMBER_OF_CORES == 1 )
            {
                mtCOVERAGE_TEST_MARKER();
            }
            #else
            {
                /* Assign idle task to each core before SMP scheduler is running. */
                xIdleTaskHandles[ xCoreID ]->xTaskRunState = xCoreID;
                pxCurrentTCBs[ xCoreID ] = xIdleTaskHandles[ xCoreID ];
            }
            #endif
        }
    }

    return xReturn;
}

/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
    BaseType_t xReturn;

    traceENTER_vTaskStartScheduler();

    #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 )
    {
        /* Sanity check that the UBaseType_t must have greater than or equal to
         * the number of bits as confNUMBER_OF_CORES. */
        configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES );
    }
    #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */

    xReturn = prvCreateIdleTasks();

    #if ( configUSE_TIMERS == 1 )
    {
        if( xReturn == pdPASS )
        {
            xReturn = xTimerCreateTimerTask();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    #endif /* configUSE_TIMERS */

    if( xReturn == pdPASS )
    {
        /* freertos_tasks_c_additions_init() should only be called if the user
         * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
         * the only macro called by the function. */
        #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
        {
            freertos_tasks_c_additions_init();
        }
        #endif

        /* Interrupts are turned off here, to ensure a tick does not occur
         * before or during the call to xPortStartScheduler().  The stacks of
         * the created tasks contain a status word with interrupts switched on
         * so interrupts will automatically get re-enabled when the first task
         * starts to run. */
        portDISABLE_INTERRUPTS();

        #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
        {
            /* Switch C-Runtime's TLS Block to point to the TLS
             * block specific to the task that will run first. */
            configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
        }
        #endif

        xNextTaskUnblockTime = portMAX_DELAY;
        xSchedulerRunning = pdTRUE;
        xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;

        /* If configGENERATE_RUN_TIME_STATS is defined then the following
         * macro must be defined to configure the timer/counter used to generate
         * the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
         * is set to 0 and the following line fails to build then ensure you do not
         * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
         * FreeRTOSConfig.h file. */
        portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();

        traceTASK_SWITCHED_IN();

        /* Setting up the timer tick is hardware specific and thus in the
         * portable interface. */

        /* The return value for xPortStartScheduler is not required
         * hence using a void datatype. */
        ( void ) xPortStartScheduler();

        /* In most cases, xPortStartScheduler() will not return. If it
         * returns pdTRUE then there was not enough heap memory available
         * to create either the Idle or the Timer task. If it returned
         * pdFALSE, then the application called xTaskEndScheduler().
         * Most ports don't implement xTaskEndScheduler() as there is
         * nothing to return to. */
    }
    else
    {
        /* This line will only be reached if the kernel could not be started,
         * because there was not enough FreeRTOS heap to create the idle task
         * or the timer task. */
        configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
    }

    /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
     * meaning xIdleTaskHandles are not used anywhere else. */
    ( void ) xIdleTaskHandles;

    /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
     * from getting optimized out as it is no longer used by the kernel. */
    ( void ) uxTopUsedPriority;

    traceRETURN_vTaskStartScheduler();
}
/*-----------------------------------------------------------*/

void vTaskEndScheduler( void )
{
    traceENTER_vTaskEndScheduler();

    #if ( INCLUDE_vTaskDelete == 1 )
    {
        BaseType_t xCoreID;

        #if ( configUSE_TIMERS == 1 )
        {
            /* Delete the timer task created by the kernel. */
            vTaskDelete( xTimerGetTimerDaemonTaskHandle() );
        }
        #endif /* #if ( configUSE_TIMERS == 1 ) */

        /* Delete Idle tasks created by the kernel.*/
        for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
        {
            vTaskDelete( xIdleTaskHandles[ xCoreID ] );
        }

        /* Idle task is responsible for reclaiming the resources of the tasks in
         * xTasksWaitingTermination list. Since the idle task is now deleted and
         * no longer going to run, we need to reclaim resources of all the tasks
         * in the xTasksWaitingTermination list. */
        prvCheckTasksWaitingTermination();
    }
    #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */

    /* Stop the scheduler interrupts and call the portable scheduler end
     * routine so the original ISRs can be restored if necessary.  The port
     * layer must ensure interrupts enable  bit is left in the correct state. */
    portDISABLE_INTERRUPTS();
    xSchedulerRunning = pdFALSE;

    /* This function must be called from a task and the application is
     * responsible for deleting that task after the scheduler is stopped. */
    vPortEndScheduler();

    traceRETURN_vTaskEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
    traceENTER_vTaskSuspendAll();

    #if ( configNUMBER_OF_CORES == 1 )
    {
        /* A critical section is not required as the variable is of type
         * BaseType_t.  Please read Richard Barry's reply in the following link to a
         * post in the FreeRTOS support forum before reporting this as a bug! -
         * https://goo.gl/wu4acr */

        /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that
         * do not otherwise exhibit real time behaviour. */
        portSOFTWARE_BARRIER();

        /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
         * is used to allow calls to vTaskSuspendAll() to nest. */
        uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended + 1U );

        /* Enforces ordering for ports and optimised compilers that may otherwise place
         * the above increment elsewhere. */
        portMEMORY_BARRIER();
    }
    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
    {
        UBaseType_t ulState;

        /* This must only be called from within a task. */
        portASSERT_IF_IN_ISR();

        if( xSchedulerRunning != pdFALSE )
        {
            /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks.
             * We must disable interrupts before we grab the locks in the event that this task is
             * interrupted and switches context before incrementing uxSchedulerSuspended.
             * It is safe to re-enable interrupts after releasing the ISR lock and incrementing
             * uxSchedulerSuspended since that will prevent context switches. */
            ulState = portSET_INTERRUPT_MASK();

            /* This must never be called from inside a critical section. */
            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );

            /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
             * do not otherwise exhibit real time behaviour. */
            portSOFTWARE_BARRIER();

            portGET_TASK_LOCK();

            /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The
             * purpose is to prevent altering the variable when fromISR APIs are readying
             * it. */
            if( uxSchedulerSuspended == 0U )
            {
                prvCheckForRunStateChange();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            portGET_ISR_LOCK();

            /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
             * is used to allow calls to vTaskSuspendAll() to nest. */
            ++uxSchedulerSuspended;
            portRELEASE_ISR_LOCK();

            portCLEAR_INTERRUPT_MASK( ulState );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }
    }
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    traceRETURN_vTaskSuspendAll();
}

/*----------------------------------------------------------*/

#if ( configUSE_TICKLESS_IDLE != 0 )

    static TickType_t prvGetExpectedIdleTime( void )
    {
        TickType_t xReturn;
        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;

        /* uxHigherPriorityReadyTasks takes care of the case where
         * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
         * task that are in the Ready state, even though the idle task is
         * running. */
        #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
        {
            if( uxTopReadyPriority > tskIDLE_PRIORITY )
            {
                uxHigherPriorityReadyTasks = pdTRUE;
            }
        }
        #else
        {
            const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;

            /* When port optimised task selection is used the uxTopReadyPriority
             * variable is used as a bit map.  If bits other than the least
             * significant bit are set then there are tasks that have a priority
             * above the idle priority that are in the Ready state.  This takes
             * care of the case where the co-operative scheduler is in use. */
            if( uxTopReadyPriority > uxLeastSignificantBit )
            {
                uxHigherPriorityReadyTasks = pdTRUE;
            }
        }
        #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */

        if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
        {
            xReturn = 0;
        }
        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U )
        {
            /* There are other idle priority tasks in the ready state.  If
             * time slicing is used then the very next tick interrupt must be
             * processed. */
            xReturn = 0;
        }
        else if( uxHigherPriorityReadyTasks != pdFALSE )
        {
            /* There are tasks in the Ready state that have a priority above the
             * idle priority.  This path can only be reached if
             * configUSE_PREEMPTION is 0. */
            xReturn = 0;
        }
        else
        {
            xReturn = xNextTaskUnblockTime;
            xReturn -= xTickCount;
        }

        return xReturn;
    }

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
    TCB_t * pxTCB = NULL;
    BaseType_t xAlreadyYielded = pdFALSE;

    traceENTER_xTaskResumeAll();

    #if ( configNUMBER_OF_CORES > 1 )
        if( xSchedulerRunning != pdFALSE )
    #endif
    {
        /* It is possible that an ISR caused a task to be removed from an event
         * list while the scheduler was suspended.  If this was the case then the
         * removed task will have been added to the xPendingReadyList.  Once the
         * scheduler has been resumed it is safe to move all the pending ready
         * tasks from this list into their appropriate ready list. */
        taskENTER_CRITICAL();
        {
            BaseType_t xCoreID;
            xCoreID = ( BaseType_t ) portGET_CORE_ID();

            /* If uxSchedulerSuspended is zero then this function does not match a
             * previous call to vTaskSuspendAll(). */
            configASSERT( uxSchedulerSuspended != 0U );

            uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended - 1U );
            portRELEASE_TASK_LOCK();

            if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
            {
                if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
                {
                    /* Move any readied tasks from the pending list into the
                     * appropriate ready list. */
                    while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
                    {
                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                        /* coverity[misra_c_2012_rule_11_5_violation] */
                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
                        portMEMORY_BARRIER();
                        listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                        prvAddTaskToReadyList( pxTCB );

                        #if ( configNUMBER_OF_CORES == 1 )
                        {
                            /* If the moved task has a priority higher than the current
                             * task then a yield must be performed. */
                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                            {
                                xYieldPendings[ xCoreID ] = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                        {
                            /* All appropriate tasks yield at the moment a task is added to xPendingReadyList.
                             * If the current core yielded then vTaskSwitchContext() has already been called
                             * which sets xYieldPendings for the current core to pdTRUE. */
                        }
                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                    }

                    if( pxTCB != NULL )
                    {
                        /* A task was unblocked while the scheduler was suspended,
                         * which may have prevented the next unblock time from being
                         * re-calculated, in which case re-calculate it now.  Mainly
                         * important for low power tickless implementations, where
                         * this can prevent an unnecessary exit from low power
                         * state. */
                        prvResetNextTaskUnblockTime();
                    }

                    /* If any ticks occurred while the scheduler was suspended then
                     * they should be processed now.  This ensures the tick count does
                     * not  slip, and that any delayed tasks are resumed at the correct
                     * time.
                     *
                     * It should be safe to call xTaskIncrementTick here from any core
                     * since we are in a critical section and xTaskIncrementTick itself
                     * protects itself within a critical section. Suspending the scheduler
                     * from any core causes xTaskIncrementTick to increment uxPendedCounts. */
                    {
                        TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */

                        if( xPendedCounts > ( TickType_t ) 0U )
                        {
                            do
                            {
                                if( xTaskIncrementTick() != pdFALSE )
                                {
                                    /* Other cores are interrupted from
                                     * within xTaskIncrementTick(). */
                                    xYieldPendings[ xCoreID ] = pdTRUE;
                                }
                                else
                                {
                                    mtCOVERAGE_TEST_MARKER();
                                }

                                --xPendedCounts;
                            } while( xPendedCounts > ( TickType_t ) 0U );

                            xPendedTicks = 0;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }

                    if( xYieldPendings[ xCoreID ] != pdFALSE )
                    {
                        #if ( configUSE_PREEMPTION != 0 )
                        {
                            xAlreadyYielded = pdTRUE;
                        }
                        #endif /* #if ( configUSE_PREEMPTION != 0 ) */

                        #if ( configNUMBER_OF_CORES == 1 )
                        {
                            taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB );
                        }
                        #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL();
    }

    traceRETURN_xTaskResumeAll( xAlreadyYielded );

    return xAlreadyYielded;
}
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
    TickType_t xTicks;

    traceENTER_xTaskGetTickCount();

    /* Critical section required if running on a 16 bit processor. */
    portTICK_TYPE_ENTER_CRITICAL();
    {
        xTicks = xTickCount;
    }
    portTICK_TYPE_EXIT_CRITICAL();

    traceRETURN_xTaskGetTickCount( xTicks );

    return xTicks;
}
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCountFromISR( void )
{
    TickType_t xReturn;
    UBaseType_t uxSavedInterruptStatus;

    traceENTER_xTaskGetTickCountFromISR();

    /* RTOS ports that support interrupt nesting have the concept of a maximum
     * system call (or maximum API call) interrupt priority.  Interrupts that are
     * above the maximum system call priority are kept permanently enabled, even
     * when the RTOS kernel is in a critical section, but cannot make any calls to
     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
     * failure if a FreeRTOS API function is called from an interrupt that has been
     * assigned a priority above the configured maximum system call priority.
     * Only FreeRTOS functions that end in FromISR can be called from interrupts
     * that have been assigned a priority at or (logically) below the maximum
     * system call  interrupt priority.  FreeRTOS maintains a separate interrupt
     * safe API to ensure interrupt entry is as fast and as simple as possible.
     * More information (albeit Cortex-M specific) is provided on the following
     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

    uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
    {
        xReturn = xTickCount;
    }
    portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

    traceRETURN_xTaskGetTickCountFromISR( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

UBaseType_t uxTaskGetNumberOfTasks( void )
{
    traceENTER_uxTaskGetNumberOfTasks();

    /* A critical section is not required because the variables are of type
     * BaseType_t. */
    traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks );

    return uxCurrentNumberOfTasks;
}
/*-----------------------------------------------------------*/

char * pcTaskGetName( TaskHandle_t xTaskToQuery )
{
    TCB_t * pxTCB;

    traceENTER_pcTaskGetName( xTaskToQuery );

    /* If null is passed in here then the name of the calling task is being
     * queried. */
    pxTCB = prvGetTCBFromHandle( xTaskToQuery );
    configASSERT( pxTCB );

    traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) );

    return &( pxTCB->pcTaskName[ 0 ] );
}
/*-----------------------------------------------------------*/

#if ( INCLUDE_xTaskGetHandle == 1 )
    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
                                                     const char pcNameToQuery[] )
    {
        TCB_t * pxReturn = NULL;
        TCB_t * pxTCB = NULL;
        UBaseType_t x;
        char cNextChar;
        BaseType_t xBreakLoop;
        const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
        ListItem_t * pxIterator;

        /* This function is called with the scheduler suspended. */

        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
        {
            for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
            {
                /* MISRA Ref 11.5.3 [Void pointer assignment] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                /* coverity[misra_c_2012_rule_11_5_violation] */
                pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );

                /* Check each character in the name looking for a match or
                 * mismatch. */
                xBreakLoop = pdFALSE;

                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
                {
                    cNextChar = pxTCB->pcTaskName[ x ];

                    if( cNextChar != pcNameToQuery[ x ] )
                    {
                        /* Characters didn't match. */
                        xBreakLoop = pdTRUE;
                    }
                    else if( cNextChar == ( char ) 0x00 )
                    {
                        /* Both strings terminated, a match must have been
                         * found. */
                        pxReturn = pxTCB;
                        xBreakLoop = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    if( xBreakLoop != pdFALSE )
                    {
                        break;
                    }
                }

                if( pxReturn != NULL )
                {
                    /* The handle has been found. */
                    break;
                }
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        return pxReturn;
    }

#endif /* INCLUDE_xTaskGetHandle */
/*-----------------------------------------------------------*/

#if ( INCLUDE_xTaskGetHandle == 1 )

    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery )
    {
        UBaseType_t uxQueue = configMAX_PRIORITIES;
        TCB_t * pxTCB;

        traceENTER_xTaskGetHandle( pcNameToQuery );

        /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
        configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );

        vTaskSuspendAll();
        {
            /* Search the ready lists. */
            do
            {
                uxQueue--;
                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );

                if( pxTCB != NULL )
                {
                    /* Found the handle. */
                    break;
                }
            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );

            /* Search the delayed lists. */
            if( pxTCB == NULL )
            {
                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
            }

            if( pxTCB == NULL )
            {
                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
            }

            #if ( INCLUDE_vTaskSuspend == 1 )
            {
                if( pxTCB == NULL )
                {
                    /* Search the suspended list. */
                    pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
                }
            }
            #endif

            #if ( INCLUDE_vTaskDelete == 1 )
            {
                if( pxTCB == NULL )
                {
                    /* Search the deleted list. */
                    pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
                }
            }
            #endif
        }
        ( void ) xTaskResumeAll();

        traceRETURN_xTaskGetHandle( pxTCB );

        return pxTCB;
    }

#endif /* INCLUDE_xTaskGetHandle */
/*-----------------------------------------------------------*/

#if ( configSUPPORT_STATIC_ALLOCATION == 1 )

    BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask,
                                      StackType_t ** ppuxStackBuffer,
                                      StaticTask_t ** ppxTaskBuffer )
    {
        BaseType_t xReturn;
        TCB_t * pxTCB;

        traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer );

        configASSERT( ppuxStackBuffer != NULL );
        configASSERT( ppxTaskBuffer != NULL );

        pxTCB = prvGetTCBFromHandle( xTask );

        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
        {
            if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB )
            {
                *ppuxStackBuffer = pxTCB->pxStack;
                /* MISRA Ref 11.3.1 [Misaligned access] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                /* coverity[misra_c_2012_rule_11_3_violation] */
                *ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
                xReturn = pdTRUE;
            }
            else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
            {
                *ppuxStackBuffer = pxTCB->pxStack;
                *ppxTaskBuffer = NULL;
                xReturn = pdTRUE;
            }
            else
            {
                xReturn = pdFALSE;
            }
        }
        #else /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */
        {
            *ppuxStackBuffer = pxTCB->pxStack;
            *ppxTaskBuffer = ( StaticTask_t * ) pxTCB;
            xReturn = pdTRUE;
        }
        #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */

        traceRETURN_xTaskGetStaticBuffers( xReturn );

        return xReturn;
    }

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
                                      const UBaseType_t uxArraySize,
                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime )
    {
        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;

        traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );

        vTaskSuspendAll();
        {
            /* Is there a space in the array for each task in the system? */
            if( uxArraySize >= uxCurrentNumberOfTasks )
            {
                /* Fill in an TaskStatus_t structure with information on each
                 * task in the Ready state. */
                do
                {
                    uxQueue--;
                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) );
                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY );

                /* Fill in an TaskStatus_t structure with information on each
                 * task in the Blocked state. */
                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) );
                uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) );

                #if ( INCLUDE_vTaskDelete == 1 )
                {
                    /* Fill in an TaskStatus_t structure with information on
                     * each task that has been deleted but not yet cleaned up. */
                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) );
                }
                #endif

                #if ( INCLUDE_vTaskSuspend == 1 )
                {
                    /* Fill in an TaskStatus_t structure with information on
                     * each task in the Suspended state. */
                    uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) );
                }
                #endif

                #if ( configGENERATE_RUN_TIME_STATS == 1 )
                {
                    if( pulTotalRunTime != NULL )
                    {
                        #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
                            portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
                        #else
                            *pulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();
                        #endif
                    }
                }
                #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
                {
                    if( pulTotalRunTime != NULL )
                    {
                        *pulTotalRunTime = 0;
                    }
                }
                #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        ( void ) xTaskResumeAll();

        traceRETURN_uxTaskGetSystemState( uxTask );

        return uxTask;
    }

#endif /* configUSE_TRACE_FACILITY */
/*----------------------------------------------------------*/

#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )

    #if ( configNUMBER_OF_CORES == 1 )
        TaskHandle_t xTaskGetIdleTaskHandle( void )
        {
            traceENTER_xTaskGetIdleTaskHandle();

            /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
             * started, then xIdleTaskHandles will be NULL. */
            configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) );

            traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] );

            return xIdleTaskHandles[ 0 ];
        }
    #endif /* if ( configNUMBER_OF_CORES == 1 ) */

    TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID )
    {
        traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID );

        /* Ensure the core ID is valid. */
        configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE );

        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
         * started, then xIdleTaskHandles will be NULL. */
        configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) );

        traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] );

        return xIdleTaskHandles[ xCoreID ];
    }

#endif /* INCLUDE_xTaskGetIdleTaskHandle */
/*----------------------------------------------------------*/

/* This conditional compilation should use inequality to 0, not equality to 1.
 * This is to ensure vTaskStepTick() is available when user defined low power mode
 * implementations require configUSE_TICKLESS_IDLE to be set to a value other than
 * 1. */
#if ( configUSE_TICKLESS_IDLE != 0 )

    void vTaskStepTick( TickType_t xTicksToJump )
    {
        TickType_t xUpdatedTickCount;

        traceENTER_vTaskStepTick( xTicksToJump );

        /* Correct the tick count value after a period during which the tick
         * was suppressed.  Note this does *not* call the tick hook function for
         * each stepped tick. */
        xUpdatedTickCount = xTickCount + xTicksToJump;
        configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime );

        if( xUpdatedTickCount == xNextTaskUnblockTime )
        {
            /* Arrange for xTickCount to reach xNextTaskUnblockTime in
             * xTaskIncrementTick() when the scheduler resumes.  This ensures
             * that any delayed tasks are resumed at the correct time. */
            configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );
            configASSERT( xTicksToJump != ( TickType_t ) 0 );

            /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
            taskENTER_CRITICAL();
            {
                xPendedTicks++;
            }
            taskEXIT_CRITICAL();
            xTicksToJump--;
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        xTickCount += xTicksToJump;

        traceINCREASE_TICK_COUNT( xTicksToJump );
        traceRETURN_vTaskStepTick();
    }

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
{
    BaseType_t xYieldOccurred;

    traceENTER_xTaskCatchUpTicks( xTicksToCatchUp );

    /* Must not be called with the scheduler suspended as the implementation
     * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
    configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U );

    /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
     * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
    vTaskSuspendAll();

    /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */
    taskENTER_CRITICAL();
    {
        xPendedTicks += xTicksToCatchUp;
    }
    taskEXIT_CRITICAL();
    xYieldOccurred = xTaskResumeAll();

    traceRETURN_xTaskCatchUpTicks( xYieldOccurred );

    return xYieldOccurred;
}
/*----------------------------------------------------------*/

#if ( INCLUDE_xTaskAbortDelay == 1 )

    BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
    {
        TCB_t * pxTCB = xTask;
        BaseType_t xReturn;

        traceENTER_xTaskAbortDelay( xTask );

        configASSERT( pxTCB );

        vTaskSuspendAll();
        {
            /* A task can only be prematurely removed from the Blocked state if
             * it is actually in the Blocked state. */
            if( eTaskGetState( xTask ) == eBlocked )
            {
                xReturn = pdPASS;

                /* Remove the reference to the task from the blocked list.  An
                 * interrupt won't touch the xStateListItem because the
                 * scheduler is suspended. */
                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );

                /* Is the task waiting on an event also?  If so remove it from
                 * the event list too.  Interrupts can touch the event list item,
                 * even though the scheduler is suspended, so a critical section
                 * is used. */
                taskENTER_CRITICAL();
                {
                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
                    {
                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );

                        /* This lets the task know it was forcibly removed from the
                         * blocked state so it should not re-evaluate its block time and
                         * then block again. */
                        pxTCB->ucDelayAborted = ( uint8_t ) pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                taskEXIT_CRITICAL();

                /* Place the unblocked task into the appropriate ready list. */
                prvAddTaskToReadyList( pxTCB );

                /* A task being unblocked cannot cause an immediate context
                 * switch if preemption is turned off. */
                #if ( configUSE_PREEMPTION == 1 )
                {
                    #if ( configNUMBER_OF_CORES == 1 )
                    {
                        /* Preemption is on, but a context switch should only be
                         * performed if the unblocked task has a priority that is
                         * higher than the currently executing task. */
                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                        {
                            /* Pend the yield to be performed when the scheduler
                             * is unsuspended. */
                            xYieldPendings[ 0 ] = pdTRUE;
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                    {
                        taskENTER_CRITICAL();
                        {
                            prvYieldForTask( pxTCB );
                        }
                        taskEXIT_CRITICAL();
                    }
                    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
                }
                #endif /* #if ( configUSE_PREEMPTION == 1 ) */
            }
            else
            {
                xReturn = pdFAIL;
            }
        }
        ( void ) xTaskResumeAll();

        traceRETURN_xTaskAbortDelay( xReturn );

        return xReturn;
    }

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
    TCB_t * pxTCB;
    TickType_t xItemValue;
    BaseType_t xSwitchRequired = pdFALSE;

    #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 )
    BaseType_t xYieldRequiredForCore[ configNUMBER_OF_CORES ] = { pdFALSE };
    #endif /* #if ( configUSE_PREEMPTION == 1 ) && ( configNUMBER_OF_CORES > 1 ) */

    traceENTER_xTaskIncrementTick();

    /* Called by the portable layer each time a tick interrupt occurs.
     * Increments the tick then checks to see if the new tick value will cause any
     * tasks to be unblocked. */
    traceTASK_INCREMENT_TICK( xTickCount );

    /* Tick increment should occur on every kernel timer event. Core 0 has the
     * responsibility to increment the tick, or increment the pended ticks if the
     * scheduler is suspended.  If pended ticks is greater than zero, the core that
     * calls xTaskResumeAll has the responsibility to increment the tick. */
    if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
    {
        /* Minor optimisation.  The tick count cannot change in this
         * block. */
        const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;

        /* Increment the RTOS tick, switching the delayed and overflowed
         * delayed lists if it wraps to 0. */
        xTickCount = xConstTickCount;

        if( xConstTickCount == ( TickType_t ) 0U )
        {
            taskSWITCH_DELAYED_LISTS();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        /* See if this tick has made a timeout expire.  Tasks are stored in
         * the  queue in the order of their wake time - meaning once one task
         * has been found whose block time has not expired there is no need to
         * look any further down the list. */
        if( xConstTickCount >= xNextTaskUnblockTime )
        {
            for( ; ; )
            {
                if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
                {
                    /* The delayed list is empty.  Set xNextTaskUnblockTime
                     * to the maximum possible value so it is extremely
                     * unlikely that the
                     * if( xTickCount >= xNextTaskUnblockTime ) test will pass
                     * next time through. */
                    xNextTaskUnblockTime = portMAX_DELAY;
                    break;
                }
                else
                {
                    /* The delayed list is not empty, get the value of the
                     * item at the head of the delayed list.  This is the time
                     * at which the task at the head of the delayed list must
                     * be removed from the Blocked state. */
                    /* MISRA Ref 11.5.3 [Void pointer assignment] */
                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                    /* coverity[misra_c_2012_rule_11_5_violation] */
                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
                    xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );

                    if( xConstTickCount < xItemValue )
                    {
                        /* It is not time to unblock this item yet, but the
                         * item value is the time at which the task at the head
                         * of the blocked list must be removed from the Blocked
                         * state -  so record the item value in
                         * xNextTaskUnblockTime. */
                        xNextTaskUnblockTime = xItemValue;
                        break;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* It is time to remove the item from the Blocked state. */
                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );

                    /* Is the task waiting on an event also?  If so remove
                     * it from the event list. */
                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
                    {
                        listREMOVE_ITEM( &( pxTCB->xEventListItem ) );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* Place the unblocked task into the appropriate ready
                     * list. */
                    prvAddTaskToReadyList( pxTCB );

                    /* A task being unblocked cannot cause an immediate
                     * context switch if preemption is turned off. */
                    #if ( configUSE_PREEMPTION == 1 )
                    {
                        #if ( configNUMBER_OF_CORES == 1 )
                        {
                            /* Preemption is on, but a context switch should
                             * only be performed if the unblocked task's
                             * priority is higher than the currently executing
                             * task.
                             * The case of equal priority tasks sharing
                             * processing time (which happens when both
                             * preemption and time slicing are on) is
                             * handled below.*/
                            if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                            {
                                xSwitchRequired = pdTRUE;
                            }
                            else
                            {
                                mtCOVERAGE_TEST_MARKER();
                            }
                        }
                        #else /* #if( configNUMBER_OF_CORES == 1 ) */
                        {
                            prvYieldForTask( pxTCB );
                        }
                        #endif /* #if( configNUMBER_OF_CORES == 1 ) */
                    }
                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                }
            }
        }

        /* Tasks of equal priority to the currently running task will share
         * processing time (time slice) if preemption is on, and the application
         * writer has not explicitly turned time slicing off. */
        #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
        {
            #if ( configNUMBER_OF_CORES == 1 )
            {
                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U )
                {
                    xSwitchRequired = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
            {
                BaseType_t xCoreID;

                for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ )
                {
                    if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U )
                    {
                        xYieldRequiredForCore[ xCoreID ] = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
            }
            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
        }
        #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */

        #if ( configUSE_TICK_HOOK == 1 )
        {
            /* Guard against the tick hook being called when the pended tick
             * count is being unwound (when the scheduler is being unlocked). */
            if( xPendedTicks == ( TickType_t ) 0 )
            {
                vApplicationTickHook();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* configUSE_TICK_HOOK */

        #if ( configUSE_PREEMPTION == 1 )
        {
            #if ( configNUMBER_OF_CORES == 1 )
            {
                /* For single core the core ID is always 0. */
                if( xYieldPendings[ 0 ] != pdFALSE )
                {
                    xSwitchRequired = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
            {
                BaseType_t xCoreID, xCurrentCoreID;
                xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID();

                for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ )
                {
                    #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 )
                        if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE )
                    #endif
                    {
                        if( ( xYieldRequiredForCore[ xCoreID ] != pdFALSE ) || ( xYieldPendings[ xCoreID ] != pdFALSE ) )
                        {
                            if( xCoreID == xCurrentCoreID )
                            {
                                xSwitchRequired = pdTRUE;
                            }
                            else
                            {
                                prvYieldCore( xCoreID );
                            }
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }
                    }
                }
            }
            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
        }
        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
    }
    else
    {
        xPendedTicks += 1U;

        /* The tick hook gets called at regular intervals, even if the
         * scheduler is locked. */
        #if ( configUSE_TICK_HOOK == 1 )
        {
            vApplicationTickHook();
        }
        #endif
    }

    traceRETURN_xTaskIncrementTick( xSwitchRequired );

    return xSwitchRequired;
}
/*-----------------------------------------------------------*/

#if ( configUSE_APPLICATION_TASK_TAG == 1 )

    void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
                                     TaskHookFunction_t pxHookFunction )
    {
        TCB_t * xTCB;

        traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction );

        /* If xTask is NULL then it is the task hook of the calling task that is
         * getting set. */
        if( xTask == NULL )
        {
            xTCB = ( TCB_t * ) pxCurrentTCB;
        }
        else
        {
            xTCB = xTask;
        }

        /* Save the hook function in the TCB.  A critical section is required as
         * the value can be accessed from an interrupt. */
        taskENTER_CRITICAL();
        {
            xTCB->pxTaskTag = pxHookFunction;
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTaskSetApplicationTaskTag();
    }

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

#if ( configUSE_APPLICATION_TASK_TAG == 1 )

    TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        TaskHookFunction_t xReturn;

        traceENTER_xTaskGetApplicationTaskTag( xTask );

        /* If xTask is NULL then set the calling task's hook. */
        pxTCB = prvGetTCBFromHandle( xTask );

        /* Save the hook function in the TCB.  A critical section is required as
         * the value can be accessed from an interrupt. */
        taskENTER_CRITICAL();
        {
            xReturn = pxTCB->pxTaskTag;
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTaskGetApplicationTaskTag( xReturn );

        return xReturn;
    }

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

#if ( configUSE_APPLICATION_TASK_TAG == 1 )

    TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        TaskHookFunction_t xReturn;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_xTaskGetApplicationTaskTagFromISR( xTask );

        /* If xTask is NULL then set the calling task's hook. */
        pxTCB = prvGetTCBFromHandle( xTask );

        /* Save the hook function in the TCB.  A critical section is required as
         * the value can be accessed from an interrupt. */
        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
        {
            xReturn = pxTCB->pxTaskTag;
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn );

        return xReturn;
    }

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

#if ( configUSE_APPLICATION_TASK_TAG == 1 )

    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
                                             void * pvParameter )
    {
        TCB_t * xTCB;
        BaseType_t xReturn;

        traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter );

        /* If xTask is NULL then we are calling our own task hook. */
        if( xTask == NULL )
        {
            xTCB = pxCurrentTCB;
        }
        else
        {
            xTCB = xTask;
        }

        if( xTCB->pxTaskTag != NULL )
        {
            xReturn = xTCB->pxTaskTag( pvParameter );
        }
        else
        {
            xReturn = pdFAIL;
        }

        traceRETURN_xTaskCallApplicationTaskHook( xReturn );

        return xReturn;
    }

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES == 1 )
    void vTaskSwitchContext( void )
    {
        traceENTER_vTaskSwitchContext();

        if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
        {
            /* The scheduler is currently suspended - do not allow a context
             * switch. */
            xYieldPendings[ 0 ] = pdTRUE;
        }
        else
        {
            xYieldPendings[ 0 ] = pdFALSE;
            traceTASK_SWITCHED_OUT();

            #if ( configGENERATE_RUN_TIME_STATS == 1 )
            {
                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] );
                #else
                    ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE();
                #endif

                /* Add the amount of time the task has been running to the
                 * accumulated time so far.  The time the task started running was
                 * stored in ulTaskSwitchedInTime.  Note that there is no overflow
                 * protection here so count values are only valid until the timer
                 * overflows.  The guard against negative values is to protect
                 * against suspect run time stat counter implementations - which
                 * are provided by the application, not the kernel. */
                if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] )
                {
                    pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ];
            }
            #endif /* configGENERATE_RUN_TIME_STATS */

            /* Check for stack overflow, if configured. */
            taskCHECK_FOR_STACK_OVERFLOW();

            /* Before the currently running task is switched out, save its errno. */
            #if ( configUSE_POSIX_ERRNO == 1 )
            {
                pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
            }
            #endif

            /* Select a new task to run using either the generic C or port
             * optimised asm code. */
            /* MISRA Ref 11.5.3 [Void pointer assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            taskSELECT_HIGHEST_PRIORITY_TASK();
            traceTASK_SWITCHED_IN();

            /* Macro to inject port specific behaviour immediately after
             * switching tasks, such as setting an end of stack watchpoint
             * or reconfiguring the MPU. */
            portTASK_SWITCH_HOOK( pxCurrentTCB );

            /* After the new task is switched in, update the global errno. */
            #if ( configUSE_POSIX_ERRNO == 1 )
            {
                FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
            }
            #endif

            #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
            {
                /* Switch C-Runtime's TLS Block to point to the TLS
                 * Block specific to this task. */
                configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock );
            }
            #endif
        }

        traceRETURN_vTaskSwitchContext();
    }
#else /* if ( configNUMBER_OF_CORES == 1 ) */
    void vTaskSwitchContext( BaseType_t xCoreID )
    {
        traceENTER_vTaskSwitchContext();

        /* Acquire both locks:
         * - The ISR lock protects the ready list from simultaneous access by
         *   both other ISRs and tasks.
         * - We also take the task lock to pause here in case another core has
         *   suspended the scheduler. We don't want to simply set xYieldPending
         *   and move on if another core suspended the scheduler. We should only
         *   do that if the current core has suspended the scheduler. */

        portGET_TASK_LOCK(); /* Must always acquire the task lock first. */
        portGET_ISR_LOCK();
        {
            /* vTaskSwitchContext() must never be called from within a critical section.
             * This is not necessarily true for single core FreeRTOS, but it is for this
             * SMP port. */
            configASSERT( portGET_CRITICAL_NESTING_COUNT() == 0 );

            if( uxSchedulerSuspended != ( UBaseType_t ) 0U )
            {
                /* The scheduler is currently suspended - do not allow a context
                 * switch. */
                xYieldPendings[ xCoreID ] = pdTRUE;
            }
            else
            {
                xYieldPendings[ xCoreID ] = pdFALSE;
                traceTASK_SWITCHED_OUT();

                #if ( configGENERATE_RUN_TIME_STATS == 1 )
                {
                    #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
                        portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] );
                    #else
                        ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE();
                    #endif

                    /* Add the amount of time the task has been running to the
                     * accumulated time so far.  The time the task started running was
                     * stored in ulTaskSwitchedInTime.  Note that there is no overflow
                     * protection here so count values are only valid until the timer
                     * overflows.  The guard against negative values is to protect
                     * against suspect run time stat counter implementations - which
                     * are provided by the application, not the kernel. */
                    if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] )
                    {
                        pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ];
                }
                #endif /* configGENERATE_RUN_TIME_STATS */

                /* Check for stack overflow, if configured. */
                taskCHECK_FOR_STACK_OVERFLOW();

                /* Before the currently running task is switched out, save its errno. */
                #if ( configUSE_POSIX_ERRNO == 1 )
                {
                    pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno;
                }
                #endif

                /* Select a new task to run. */
                taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID );
                traceTASK_SWITCHED_IN();

                /* Macro to inject port specific behaviour immediately after
                 * switching tasks, such as setting an end of stack watchpoint
                 * or reconfiguring the MPU. */
                portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] );

                /* After the new task is switched in, update the global errno. */
                #if ( configUSE_POSIX_ERRNO == 1 )
                {
                    FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno;
                }
                #endif

                #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
                {
                    /* Switch C-Runtime's TLS Block to point to the TLS
                     * Block specific to this task. */
                    configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock );
                }
                #endif
            }
        }
        portRELEASE_ISR_LOCK();
        portRELEASE_TASK_LOCK();

        traceRETURN_vTaskSwitchContext();
    }
#endif /* if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList,
                            const TickType_t xTicksToWait )
{
    traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait );

    configASSERT( pxEventList );

    /* THIS FUNCTION MUST BE CALLED WITH THE
     * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */

    /* Place the event list item of the TCB in the appropriate event list.
     * This is placed in the list in priority order so the highest priority task
     * is the first to be woken by the event.
     *
     * Note: Lists are sorted in ascending order by ListItem_t.xItemValue.
     * Normally, the xItemValue of a TCB's ListItem_t members is:
     *      xItemValue = ( configMAX_PRIORITIES - uxPriority )
     * Therefore, the event list is sorted in descending priority order.
     *
     * The queue that contains the event list is locked, preventing
     * simultaneous access from interrupts. */
    vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );

    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );

    traceRETURN_vTaskPlaceOnEventList();
}
/*-----------------------------------------------------------*/

void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
                                     const TickType_t xItemValue,
                                     const TickType_t xTicksToWait )
{
    traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait );

    configASSERT( pxEventList );

    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
     * the event groups implementation. */
    configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );

    /* Store the item value in the event list item.  It is safe to access the
     * event list item here as interrupts won't access the event list item of a
     * task that is not in the Blocked state. */
    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );

    /* Place the event list item of the TCB at the end of the appropriate event
     * list.  It is safe to access the event list here because it is part of an
     * event group implementation - and interrupts don't access event groups
     * directly (instead they access them indirectly by pending function calls to
     * the task level). */
    listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );

    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );

    traceRETURN_vTaskPlaceOnUnorderedEventList();
}
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

    void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
                                          TickType_t xTicksToWait,
                                          const BaseType_t xWaitIndefinitely )
    {
        traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely );

        configASSERT( pxEventList );

        /* This function should not be called by application code hence the
         * 'Restricted' in its name.  It is not part of the public API.  It is
         * designed for use by kernel code, and has special calling requirements -
         * it should be called with the scheduler suspended. */


        /* Place the event list item of the TCB in the appropriate event list.
         * In this case it is assume that this is the only task that is going to
         * be waiting on this event list, so the faster vListInsertEnd() function
         * can be used in place of vListInsert. */
        listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) );

        /* If the task should block indefinitely then set the block time to a
         * value that will be recognised as an indefinite delay inside the
         * prvAddCurrentTaskToDelayedList() function. */
        if( xWaitIndefinitely != pdFALSE )
        {
            xTicksToWait = portMAX_DELAY;
        }

        traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
        prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );

        traceRETURN_vTaskPlaceOnEventListRestricted();
    }

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
    TCB_t * pxUnblockedTCB;
    BaseType_t xReturn;

    traceENTER_xTaskRemoveFromEventList( pxEventList );

    /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
     * called from a critical section within an ISR. */

    /* The event list is sorted in priority order, so the first in the list can
     * be removed as it is known to be the highest priority.  Remove the TCB from
     * the delayed list, and add it to the ready list.
     *
     * If an event is for a queue that is locked then this function will never
     * get called - the lock count on the queue will get modified instead.  This
     * means exclusive access to the event list is guaranteed here.
     *
     * This function assumes that a check has already been made to ensure that
     * pxEventList is not empty. */
    /* MISRA Ref 11.5.3 [Void pointer assignment] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
    /* coverity[misra_c_2012_rule_11_5_violation] */
    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
    configASSERT( pxUnblockedTCB );
    listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) );

    if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
    {
        listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
        prvAddTaskToReadyList( pxUnblockedTCB );

        #if ( configUSE_TICKLESS_IDLE != 0 )
        {
            /* If a task is blocked on a kernel object then xNextTaskUnblockTime
             * might be set to the blocked task's time out time.  If the task is
             * unblocked for a reason other than a timeout xNextTaskUnblockTime is
             * normally left unchanged, because it is automatically reset to a new
             * value when the tick count equals xNextTaskUnblockTime.  However if
             * tickless idling is used it might be more important to enter sleep mode
             * at the earliest possible time - so reset xNextTaskUnblockTime here to
             * ensure it is updated at the earliest possible time. */
            prvResetNextTaskUnblockTime();
        }
        #endif
    }
    else
    {
        /* The delayed and ready lists cannot be accessed, so hold this task
         * pending until the scheduler is resumed. */
        listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
    }

    #if ( configNUMBER_OF_CORES == 1 )
    {
        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
        {
            /* Return true if the task removed from the event list has a higher
             * priority than the calling task.  This allows the calling task to know if
             * it should force a context switch now. */
            xReturn = pdTRUE;

            /* Mark that a yield is pending in case the user is not using the
             * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
            xYieldPendings[ 0 ] = pdTRUE;
        }
        else
        {
            xReturn = pdFALSE;
        }
    }
    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
    {
        xReturn = pdFALSE;

        #if ( configUSE_PREEMPTION == 1 )
        {
            prvYieldForTask( pxUnblockedTCB );

            if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
            {
                xReturn = pdTRUE;
            }
        }
        #endif /* #if ( configUSE_PREEMPTION == 1 ) */
    }
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    traceRETURN_xTaskRemoveFromEventList( xReturn );
    return xReturn;
}
/*-----------------------------------------------------------*/

void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
                                        const TickType_t xItemValue )
{
    TCB_t * pxUnblockedTCB;

    traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue );

    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
     * the event flags implementation. */
    configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U );

    /* Store the new item value in the event list. */
    listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );

    /* Remove the event list form the event flag.  Interrupts do not access
     * event flags. */
    /* MISRA Ref 11.5.3 [Void pointer assignment] */
    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
    /* coverity[misra_c_2012_rule_11_5_violation] */
    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem );
    configASSERT( pxUnblockedTCB );
    listREMOVE_ITEM( pxEventListItem );

    #if ( configUSE_TICKLESS_IDLE != 0 )
    {
        /* If a task is blocked on a kernel object then xNextTaskUnblockTime
         * might be set to the blocked task's time out time.  If the task is
         * unblocked for a reason other than a timeout xNextTaskUnblockTime is
         * normally left unchanged, because it is automatically reset to a new
         * value when the tick count equals xNextTaskUnblockTime.  However if
         * tickless idling is used it might be more important to enter sleep mode
         * at the earliest possible time - so reset xNextTaskUnblockTime here to
         * ensure it is updated at the earliest possible time. */
        prvResetNextTaskUnblockTime();
    }
    #endif

    /* Remove the task from the delayed list and add it to the ready list.  The
     * scheduler is suspended so interrupts will not be accessing the ready
     * lists. */
    listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) );
    prvAddTaskToReadyList( pxUnblockedTCB );

    #if ( configNUMBER_OF_CORES == 1 )
    {
        if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
        {
            /* The unblocked task has a priority above that of the calling task, so
             * a context switch is required.  This function is called with the
             * scheduler suspended so xYieldPending is set so the context switch
             * occurs immediately that the scheduler is resumed (unsuspended). */
            xYieldPendings[ 0 ] = pdTRUE;
        }
    }
    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
    {
        #if ( configUSE_PREEMPTION == 1 )
        {
            taskENTER_CRITICAL();
            {
                prvYieldForTask( pxUnblockedTCB );
            }
            taskEXIT_CRITICAL();
        }
        #endif
    }
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    traceRETURN_vTaskRemoveFromUnorderedEventList();
}
/*-----------------------------------------------------------*/

void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
{
    traceENTER_vTaskSetTimeOutState( pxTimeOut );

    configASSERT( pxTimeOut );
    taskENTER_CRITICAL();
    {
        pxTimeOut->xOverflowCount = xNumOfOverflows;
        pxTimeOut->xTimeOnEntering = xTickCount;
    }
    taskEXIT_CRITICAL();

    traceRETURN_vTaskSetTimeOutState();
}
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
    traceENTER_vTaskInternalSetTimeOutState( pxTimeOut );

    /* For internal use only as it does not use a critical section. */
    pxTimeOut->xOverflowCount = xNumOfOverflows;
    pxTimeOut->xTimeOnEntering = xTickCount;

    traceRETURN_vTaskInternalSetTimeOutState();
}
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
                                 TickType_t * const pxTicksToWait )
{
    BaseType_t xReturn;

    traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );

    configASSERT( pxTimeOut );
    configASSERT( pxTicksToWait );

    taskENTER_CRITICAL();
    {
        /* Minor optimisation.  The tick count cannot change in this block. */
        const TickType_t xConstTickCount = xTickCount;
        const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;

        #if ( INCLUDE_xTaskAbortDelay == 1 )
            if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
            {
                /* The delay was aborted, which is not the same as a time out,
                 * but has the same result. */
                pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
                xReturn = pdTRUE;
            }
            else
        #endif

        #if ( INCLUDE_vTaskSuspend == 1 )
            if( *pxTicksToWait == portMAX_DELAY )
            {
                /* If INCLUDE_vTaskSuspend is set to 1 and the block time
                 * specified is the maximum block time then the task should block
                 * indefinitely, and therefore never time out. */
                xReturn = pdFALSE;
            }
            else
        #endif

        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) )
        {
            /* The tick count is greater than the time at which
             * vTaskSetTimeout() was called, but has also overflowed since
             * vTaskSetTimeOut() was called.  It must have wrapped all the way
             * around and gone past again. This passed since vTaskSetTimeout()
             * was called. */
            xReturn = pdTRUE;
            *pxTicksToWait = ( TickType_t ) 0;
        }
        else if( xElapsedTime < *pxTicksToWait )
        {
            /* Not a genuine timeout. Adjust parameters for time remaining. */
            *pxTicksToWait -= xElapsedTime;
            vTaskInternalSetTimeOutState( pxTimeOut );
            xReturn = pdFALSE;
        }
        else
        {
            *pxTicksToWait = ( TickType_t ) 0;
            xReturn = pdTRUE;
        }
    }
    taskEXIT_CRITICAL();

    traceRETURN_xTaskCheckForTimeOut( xReturn );

    return xReturn;
}
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
    traceENTER_vTaskMissedYield();

    /* Must be called from within a critical section. */
    xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;

    traceRETURN_vTaskMissedYield();
}
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
    {
        UBaseType_t uxReturn;
        TCB_t const * pxTCB;

        traceENTER_uxTaskGetTaskNumber( xTask );

        if( xTask != NULL )
        {
            pxTCB = xTask;
            uxReturn = pxTCB->uxTaskNumber;
        }
        else
        {
            uxReturn = 0U;
        }

        traceRETURN_uxTaskGetTaskNumber( uxReturn );

        return uxReturn;
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    void vTaskSetTaskNumber( TaskHandle_t xTask,
                             const UBaseType_t uxHandle )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskSetTaskNumber( xTask, uxHandle );

        if( xTask != NULL )
        {
            pxTCB = xTask;
            pxTCB->uxTaskNumber = uxHandle;
        }

        traceRETURN_vTaskSetTaskNumber();
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

/*
 * -----------------------------------------------------------
 * The passive idle task.
 * ----------------------------------------------------------
 *
 * The passive idle task is used for all the additional cores in a SMP
 * system. There must be only 1 active idle task and the rest are passive
 * idle tasks.
 *
 * The portTASK_FUNCTION() macro is used to allow port/compiler specific
 * language extensions.  The equivalent prototype for this function is:
 *
 * void prvPassiveIdleTask( void *pvParameters );
 */

#if ( configNUMBER_OF_CORES > 1 )
    static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters )
    {
        ( void ) pvParameters;

        taskYIELD();

        for( ; configCONTROL_INFINITE_LOOP(); )
        {
            #if ( configUSE_PREEMPTION == 0 )
            {
                /* If we are not using preemption we keep forcing a task switch to
                 * see if any other task has become available.  If we are using
                 * preemption we don't need to do this as any task becoming available
                 * will automatically get the processor anyway. */
                taskYIELD();
            }
            #endif /* configUSE_PREEMPTION */

            #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
            {
                /* When using preemption tasks of equal priority will be
                 * timesliced.  If a task that is sharing the idle priority is ready
                 * to run then the idle task should yield before the end of the
                 * timeslice.
                 *
                 * A critical region is not required here as we are just reading from
                 * the list, and an occasional incorrect value will not matter.  If
                 * the ready list at the idle priority contains one more task than the
                 * number of idle tasks, which is equal to the configured numbers of cores
                 * then a task other than the idle task is ready to execute. */
                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
                {
                    taskYIELD();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */

            #if ( configUSE_PASSIVE_IDLE_HOOK == 1 )
            {
                /* Call the user defined function from within the idle task.  This
                 * allows the application designer to add background functionality
                 * without the overhead of a separate task.
                 *
                 * This hook is intended to manage core activity such as disabling cores that go idle.
                 *
                 * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
                 * CALL A FUNCTION THAT MIGHT BLOCK. */
                vApplicationPassiveIdleHook();
            }
            #endif /* configUSE_PASSIVE_IDLE_HOOK */
        }
    }
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

/*
 * -----------------------------------------------------------
 * The idle task.
 * ----------------------------------------------------------
 *
 * The portTASK_FUNCTION() macro is used to allow port/compiler specific
 * language extensions.  The equivalent prototype for this function is:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */

static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
    /* Stop warnings. */
    ( void ) pvParameters;

    /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
     * SCHEDULER IS STARTED. **/

    /* In case a task that has a secure context deletes itself, in which case
     * the idle task is responsible for deleting the task's secure context, if
     * any. */
    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );

    #if ( configNUMBER_OF_CORES > 1 )
    {
        /* SMP all cores start up in the idle task. This initial yield gets the application
         * tasks started. */
        taskYIELD();
    }
    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */

    for( ; configCONTROL_INFINITE_LOOP(); )
    {
        /* See if any tasks have deleted themselves - if so then the idle task
         * is responsible for freeing the deleted task's TCB and stack. */
        prvCheckTasksWaitingTermination();

        #if ( configUSE_PREEMPTION == 0 )
        {
            /* If we are not using preemption we keep forcing a task switch to
             * see if any other task has become available.  If we are using
             * preemption we don't need to do this as any task becoming available
             * will automatically get the processor anyway. */
            taskYIELD();
        }
        #endif /* configUSE_PREEMPTION */

        #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
        {
            /* When using preemption tasks of equal priority will be
             * timesliced.  If a task that is sharing the idle priority is ready
             * to run then the idle task should yield before the end of the
             * timeslice.
             *
             * A critical region is not required here as we are just reading from
             * the list, and an occasional incorrect value will not matter.  If
             * the ready list at the idle priority contains one more task than the
             * number of idle tasks, which is equal to the configured numbers of cores
             * then a task other than the idle task is ready to execute. */
            if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES )
            {
                taskYIELD();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */

        #if ( configUSE_IDLE_HOOK == 1 )
        {
            /* Call the user defined function from within the idle task. */
            vApplicationIdleHook();
        }
        #endif /* configUSE_IDLE_HOOK */

        /* This conditional compilation should use inequality to 0, not equality
         * to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
         * user defined low power mode  implementations require
         * configUSE_TICKLESS_IDLE to be set to a value other than 1. */
        #if ( configUSE_TICKLESS_IDLE != 0 )
        {
            TickType_t xExpectedIdleTime;

            /* It is not desirable to suspend then resume the scheduler on
             * each iteration of the idle task.  Therefore, a preliminary
             * test of the expected idle time is performed without the
             * scheduler suspended.  The result here is not necessarily
             * valid. */
            xExpectedIdleTime = prvGetExpectedIdleTime();

            if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
            {
                vTaskSuspendAll();
                {
                    /* Now the scheduler is suspended, the expected idle
                     * time can be sampled again, and this time its value can
                     * be used. */
                    configASSERT( xNextTaskUnblockTime >= xTickCount );
                    xExpectedIdleTime = prvGetExpectedIdleTime();

                    /* Define the following macro to set xExpectedIdleTime to 0
                     * if the application does not want
                     * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
                    configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );

                    if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
                    {
                        traceLOW_POWER_IDLE_BEGIN();
                        portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
                        traceLOW_POWER_IDLE_END();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                ( void ) xTaskResumeAll();
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* configUSE_TICKLESS_IDLE */

        #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) )
        {
            /* Call the user defined function from within the idle task.  This
             * allows the application designer to add background functionality
             * without the overhead of a separate task.
             *
             * This hook is intended to manage core activity such as disabling cores that go idle.
             *
             * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
             * CALL A FUNCTION THAT MIGHT BLOCK. */
            vApplicationPassiveIdleHook();
        }
        #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */
    }
}
/*-----------------------------------------------------------*/

#if ( configUSE_TICKLESS_IDLE != 0 )

    eSleepModeStatus eTaskConfirmSleepModeStatus( void )
    {
        #if ( INCLUDE_vTaskSuspend == 1 )
            /* The idle task exists in addition to the application tasks. */
            const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES;
        #endif /* INCLUDE_vTaskSuspend */

        eSleepModeStatus eReturn = eStandardSleep;

        traceENTER_eTaskConfirmSleepModeStatus();

        /* This function must be called from a critical section. */

        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U )
        {
            /* A task was made ready while the scheduler was suspended. */
            eReturn = eAbortSleep;
        }
        else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE )
        {
            /* A yield was pended while the scheduler was suspended. */
            eReturn = eAbortSleep;
        }
        else if( xPendedTicks != 0U )
        {
            /* A tick interrupt has already occurred but was held pending
             * because the scheduler is suspended. */
            eReturn = eAbortSleep;
        }

        #if ( INCLUDE_vTaskSuspend == 1 )
            else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
            {
                /* If all the tasks are in the suspended list (which might mean they
                 * have an infinite block time rather than actually being suspended)
                 * then it is safe to turn all clocks off and just wait for external
                 * interrupts. */
                eReturn = eNoTasksWaitingTimeout;
            }
        #endif /* INCLUDE_vTaskSuspend */
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_eTaskConfirmSleepModeStatus( eReturn );

        return eReturn;
    }

#endif /* configUSE_TICKLESS_IDLE */
/*-----------------------------------------------------------*/

#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )

    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
                                            BaseType_t xIndex,
                                            void * pvValue )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );

        if( ( xIndex >= 0 ) &&
            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
        {
            pxTCB = prvGetTCBFromHandle( xTaskToSet );
            configASSERT( pxTCB != NULL );
            pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
        }

        traceRETURN_vTaskSetThreadLocalStoragePointer();
    }

#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
/*-----------------------------------------------------------*/

#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )

    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
                                               BaseType_t xIndex )
    {
        void * pvReturn = NULL;
        TCB_t * pxTCB;

        traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );

        if( ( xIndex >= 0 ) &&
            ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) )
        {
            pxTCB = prvGetTCBFromHandle( xTaskToQuery );
            pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
        }
        else
        {
            pvReturn = NULL;
        }

        traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn );

        return pvReturn;
    }

#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
/*-----------------------------------------------------------*/

#if ( portUSING_MPU_WRAPPERS == 1 )

    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
                                  const MemoryRegion_t * const pxRegions )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions );

        /* If null is passed in here then we are modifying the MPU settings of
         * the calling task. */
        pxTCB = prvGetTCBFromHandle( xTaskToModify );

        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 );

        traceRETURN_vTaskAllocateMPURegions();
    }

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
    UBaseType_t uxPriority;

    for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
    {
        vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
    }

    vListInitialise( &xDelayedTaskList1 );
    vListInitialise( &xDelayedTaskList2 );
    vListInitialise( &xPendingReadyList );

    #if ( INCLUDE_vTaskDelete == 1 )
    {
        vListInitialise( &xTasksWaitingTermination );
    }
    #endif /* INCLUDE_vTaskDelete */

    #if ( INCLUDE_vTaskSuspend == 1 )
    {
        vListInitialise( &xSuspendedTaskList );
    }
    #endif /* INCLUDE_vTaskSuspend */

    /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
     * using list2. */
    pxDelayedTaskList = &xDelayedTaskList1;
    pxOverflowDelayedTaskList = &xDelayedTaskList2;
}
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
    /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/

    #if ( INCLUDE_vTaskDelete == 1 )
    {
        TCB_t * pxTCB;

        /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
         * being called too often in the idle task. */
        while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
        {
            #if ( configNUMBER_OF_CORES == 1 )
            {
                taskENTER_CRITICAL();
                {
                    {
                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                        /* coverity[misra_c_2012_rule_11_5_violation] */
                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
                        ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                        --uxCurrentNumberOfTasks;
                        --uxDeletedTasksWaitingCleanUp;
                    }
                }
                taskEXIT_CRITICAL();

                prvDeleteTCB( pxTCB );
            }
            #else /* #if( configNUMBER_OF_CORES == 1 ) */
            {
                pxTCB = NULL;

                taskENTER_CRITICAL();
                {
                    /* For SMP, multiple idles can be running simultaneously
                     * and we need to check that other idles did not cleanup while we were
                     * waiting to enter the critical section. */
                    if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
                    {
                        /* MISRA Ref 11.5.3 [Void pointer assignment] */
                        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                        /* coverity[misra_c_2012_rule_11_5_violation] */
                        pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );

                        if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING )
                        {
                            ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
                            --uxCurrentNumberOfTasks;
                            --uxDeletedTasksWaitingCleanUp;
                        }
                        else
                        {
                            /* The TCB to be deleted still has not yet been switched out
                             * by the scheduler, so we will just exit this loop early and
                             * try again next time. */
                            taskEXIT_CRITICAL();
                            break;
                        }
                    }
                }
                taskEXIT_CRITICAL();

                if( pxTCB != NULL )
                {
                    prvDeleteTCB( pxTCB );
                }
            }
            #endif /* #if( configNUMBER_OF_CORES == 1 ) */
        }
    }
    #endif /* INCLUDE_vTaskDelete */
}
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    void vTaskGetInfo( TaskHandle_t xTask,
                       TaskStatus_t * pxTaskStatus,
                       BaseType_t xGetFreeStackSpace,
                       eTaskState eState )
    {
        TCB_t * pxTCB;

        traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );

        /* xTask is NULL then get the state of the calling task. */
        pxTCB = prvGetTCBFromHandle( xTask );

        pxTaskStatus->xHandle = pxTCB;
        pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
        pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
        pxTaskStatus->pxStackBase = pxTCB->pxStack;
        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
            pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack;
            pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack;
        #endif
        pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;

        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
        {
            pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask;
        }
        #endif

        #if ( configUSE_MUTEXES == 1 )
        {
            pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
        }
        #else
        {
            pxTaskStatus->uxBasePriority = 0;
        }
        #endif

        #if ( configGENERATE_RUN_TIME_STATS == 1 )
        {
            pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
        }
        #else
        {
            pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0;
        }
        #endif

        /* Obtaining the task state is a little fiddly, so is only done if the
         * value of eState passed into this function is eInvalid - otherwise the
         * state is just set to whatever is passed in. */
        if( eState != eInvalid )
        {
            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
            {
                pxTaskStatus->eCurrentState = eRunning;
            }
            else
            {
                pxTaskStatus->eCurrentState = eState;

                #if ( INCLUDE_vTaskSuspend == 1 )
                {
                    /* If the task is in the suspended list then there is a
                     *  chance it is actually just blocked indefinitely - so really
                     *  it should be reported as being in the Blocked state. */
                    if( eState == eSuspended )
                    {
                        vTaskSuspendAll();
                        {
                            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
                            {
                                pxTaskStatus->eCurrentState = eBlocked;
                            }
                            else
                            {
                                #if ( configUSE_TASK_NOTIFICATIONS == 1 )
                                {
                                    BaseType_t x;

                                    /* The task does not appear on the event list item of
                                     * and of the RTOS objects, but could still be in the
                                     * blocked state if it is waiting on its notification
                                     * rather than waiting on an object.  If not, is
                                     * suspended. */
                                    for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
                                    {
                                        if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
                                        {
                                            pxTaskStatus->eCurrentState = eBlocked;
                                            break;
                                        }
                                    }
                                }
                                #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
                            }
                        }
                        ( void ) xTaskResumeAll();
                    }
                }
                #endif /* INCLUDE_vTaskSuspend */

                /* Tasks can be in pending ready list and other state list at the
                 * same time. These tasks are in ready state no matter what state
                 * list the task is in. */
                taskENTER_CRITICAL();
                {
                    if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdFALSE )
                    {
                        pxTaskStatus->eCurrentState = eReady;
                    }
                }
                taskEXIT_CRITICAL();
            }
        }
        else
        {
            pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
        }

        /* Obtaining the stack space takes some time, so the xGetFreeStackSpace
         * parameter is provided to allow it to be skipped. */
        if( xGetFreeStackSpace != pdFALSE )
        {
            #if ( portSTACK_GROWTH > 0 )
            {
                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
            }
            #else
            {
                pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
            }
            #endif
        }
        else
        {
            pxTaskStatus->usStackHighWaterMark = 0;
        }

        traceRETURN_vTaskGetInfo();
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

#if ( configUSE_TRACE_FACILITY == 1 )

    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
                                                     List_t * pxList,
                                                     eTaskState eState )
    {
        UBaseType_t uxTask = 0;
        const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList );
        ListItem_t * pxIterator;
        TCB_t * pxTCB = NULL;

        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
        {
            /* Populate an TaskStatus_t structure within the
             * pxTaskStatusArray array for each task that is referenced from
             * pxList.  See the definition of TaskStatus_t in task.h for the
             * meaning of each TaskStatus_t structure member. */
            for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) )
            {
                /* MISRA Ref 11.5.3 [Void pointer assignment] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
                /* coverity[misra_c_2012_rule_11_5_violation] */
                pxTCB = listGET_LIST_ITEM_OWNER( pxIterator );

                vTaskGetInfo( ( TaskHandle_t ) pxTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
                uxTask++;
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        return uxTask;
    }

#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )

    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
    {
        configSTACK_DEPTH_TYPE uxCount = 0U;

        while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
        {
            pucStackByte -= portSTACK_GROWTH;
            uxCount++;
        }

        uxCount /= ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t );

        return uxCount;
    }

#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )

/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
 * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
 * user to determine the return type.  It gets around the problem of the value
 * overflowing on 8-bit types without breaking backward compatibility for
 * applications that expect an 8-bit return type. */
    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        uint8_t * pucEndOfStack;
        configSTACK_DEPTH_TYPE uxReturn;

        traceENTER_uxTaskGetStackHighWaterMark2( xTask );

        /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
         * the same except for their return type.  Using configSTACK_DEPTH_TYPE
         * allows the user to determine the return type.  It gets around the
         * problem of the value overflowing on 8-bit types without breaking
         * backward compatibility for applications that expect an 8-bit return
         * type. */

        pxTCB = prvGetTCBFromHandle( xTask );

        #if portSTACK_GROWTH < 0
        {
            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
        }
        #else
        {
            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
        }
        #endif

        uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );

        traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn );

        return uxReturn;
    }

#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
/*-----------------------------------------------------------*/

#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )

    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        uint8_t * pucEndOfStack;
        UBaseType_t uxReturn;

        traceENTER_uxTaskGetStackHighWaterMark( xTask );

        pxTCB = prvGetTCBFromHandle( xTask );

        #if portSTACK_GROWTH < 0
        {
            pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
        }
        #else
        {
            pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
        }
        #endif

        uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );

        traceRETURN_uxTaskGetStackHighWaterMark( uxReturn );

        return uxReturn;
    }

#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

    static void prvDeleteTCB( TCB_t * pxTCB )
    {
        /* This call is required specifically for the TriCore port.  It must be
         * above the vPortFree() calls.  The call is also used by ports/demos that
         * want to allocate and clean RAM statically. */
        portCLEAN_UP_TCB( pxTCB );

        #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 )
        {
            /* Free up the memory allocated for the task's TLS Block. */
            configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock );
        }
        #endif

        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
        {
            /* The task can only have been allocated dynamically - free both
             * the stack and TCB. */
            vPortFreeStack( pxTCB->pxStack );
            vPortFree( pxTCB );
        }
        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
        {
            /* The task could have been allocated statically or dynamically, so
             * check what was statically allocated before trying to free the
             * memory. */
            if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
            {
                /* Both the stack and TCB were allocated dynamically, so both
                 * must be freed. */
                vPortFreeStack( pxTCB->pxStack );
                vPortFree( pxTCB );
            }
            else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
            {
                /* Only the stack was statically allocated, so the TCB is the
                 * only memory that must be freed. */
                vPortFree( pxTCB );
            }
            else
            {
                /* Neither the stack nor the TCB were allocated dynamically, so
                 * nothing needs to be freed. */
                configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
                mtCOVERAGE_TEST_MARKER();
            }
        }
        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
    }

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
    if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
    {
        /* The new current delayed list is empty.  Set xNextTaskUnblockTime to
         * the maximum possible value so it is  extremely unlikely that the
         * if( xTickCount >= xNextTaskUnblockTime ) test will pass until
         * there is an item in the delayed list. */
        xNextTaskUnblockTime = portMAX_DELAY;
    }
    else
    {
        /* The new current delayed list is not empty, get the value of
         * the item at the head of the delayed list.  This is the time at
         * which the task at the head of the delayed list should be removed
         * from the Blocked state. */
        xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
    }
}
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 )

    #if ( configNUMBER_OF_CORES == 1 )
        TaskHandle_t xTaskGetCurrentTaskHandle( void )
        {
            TaskHandle_t xReturn;

            traceENTER_xTaskGetCurrentTaskHandle();

            /* A critical section is not required as this is not called from
             * an interrupt and the current TCB will always be the same for any
             * individual execution thread. */
            xReturn = pxCurrentTCB;

            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );

            return xReturn;
        }
    #else /* #if ( configNUMBER_OF_CORES == 1 ) */
        TaskHandle_t xTaskGetCurrentTaskHandle( void )
        {
            TaskHandle_t xReturn;
            UBaseType_t uxSavedInterruptStatus;

            traceENTER_xTaskGetCurrentTaskHandle();

            uxSavedInterruptStatus = portSET_INTERRUPT_MASK();
            {
                xReturn = pxCurrentTCBs[ portGET_CORE_ID() ];
            }
            portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus );

            traceRETURN_xTaskGetCurrentTaskHandle( xReturn );

            return xReturn;
        }
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID )
    {
        TaskHandle_t xReturn = NULL;

        traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID );

        if( taskVALID_CORE_ID( xCoreID ) != pdFALSE )
        {
            #if ( configNUMBER_OF_CORES == 1 )
                xReturn = pxCurrentTCB;
            #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                xReturn = pxCurrentTCBs[ xCoreID ];
            #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
        }

        traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn );

        return xReturn;
    }

#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

    BaseType_t xTaskGetSchedulerState( void )
    {
        BaseType_t xReturn;

        traceENTER_xTaskGetSchedulerState();

        if( xSchedulerRunning == pdFALSE )
        {
            xReturn = taskSCHEDULER_NOT_STARTED;
        }
        else
        {
            #if ( configNUMBER_OF_CORES > 1 )
                taskENTER_CRITICAL();
            #endif
            {
                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
                {
                    xReturn = taskSCHEDULER_RUNNING;
                }
                else
                {
                    xReturn = taskSCHEDULER_SUSPENDED;
                }
            }
            #if ( configNUMBER_OF_CORES > 1 )
                taskEXIT_CRITICAL();
            #endif
        }

        traceRETURN_xTaskGetSchedulerState( xReturn );

        return xReturn;
    }

#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
    {
        TCB_t * const pxMutexHolderTCB = pxMutexHolder;
        BaseType_t xReturn = pdFALSE;

        traceENTER_xTaskPriorityInherit( pxMutexHolder );

        /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority
         * inheritance is not applied in this scenario. */
        if( pxMutexHolder != NULL )
        {
            /* If the holder of the mutex has a priority below the priority of
             * the task attempting to obtain the mutex then it will temporarily
             * inherit the priority of the task attempting to obtain the mutex. */
            if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
            {
                /* Adjust the mutex holder state to account for its new
                 * priority.  Only reset the event list item value if the value is
                 * not being used for anything else. */
                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                {
                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                /* If the task being modified is in the ready state it will need
                 * to be moved into a new list. */
                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
                {
                    if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
                    {
                        /* It is known that the task is in its ready list so
                         * there is no need to check again and the port level
                         * reset macro can be called directly. */
                        portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* Inherit the priority before being moved into the new list. */
                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
                    prvAddTaskToReadyList( pxMutexHolderTCB );
                    #if ( configNUMBER_OF_CORES > 1 )
                    {
                        /* The priority of the task is raised. Yield for this task
                         * if it is not running. */
                        if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE )
                        {
                            prvYieldForTask( pxMutexHolderTCB );
                        }
                    }
                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                }
                else
                {
                    /* Just inherit the priority. */
                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
                }

                traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );

                /* Inheritance occurred. */
                xReturn = pdTRUE;
            }
            else
            {
                if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
                {
                    /* The base priority of the mutex holder is lower than the
                     * priority of the task attempting to take the mutex, but the
                     * current priority of the mutex holder is not lower than the
                     * priority of the task attempting to take the mutex.
                     * Therefore the mutex holder must have already inherited a
                     * priority, but inheritance would have occurred if that had
                     * not been the case. */
                    xReturn = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTaskPriorityInherit( xReturn );

        return xReturn;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
    {
        TCB_t * const pxTCB = pxMutexHolder;
        BaseType_t xReturn = pdFALSE;

        traceENTER_xTaskPriorityDisinherit( pxMutexHolder );

        if( pxMutexHolder != NULL )
        {
            /* A task can only have an inherited priority if it holds the mutex.
             * If the mutex is held by a task then it cannot be given from an
             * interrupt, and if a mutex is given by the holding task then it must
             * be the running state task. */
            configASSERT( pxTCB == pxCurrentTCB );
            configASSERT( pxTCB->uxMutexesHeld );
            ( pxTCB->uxMutexesHeld )--;

            /* Has the holder of the mutex inherited the priority of another
             * task? */
            if( pxTCB->uxPriority != pxTCB->uxBasePriority )
            {
                /* Only disinherit if no other mutexes are held. */
                if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
                {
                    /* A task can only have an inherited priority if it holds
                     * the mutex.  If the mutex is held by a task then it cannot be
                     * given from an interrupt, and if a mutex is given by the
                     * holding task then it must be the running state task.  Remove
                     * the holding task from the ready list. */
                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
                    {
                        portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* Disinherit the priority before adding the task into the
                     * new  ready list. */
                    traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
                    pxTCB->uxPriority = pxTCB->uxBasePriority;

                    /* Reset the event list item value.  It cannot be in use for
                     * any other purpose if this task is running, and it must be
                     * running to give back the mutex. */
                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority );
                    prvAddTaskToReadyList( pxTCB );
                    #if ( configNUMBER_OF_CORES > 1 )
                    {
                        /* The priority of the task is dropped. Yield the core on
                         * which the task is running. */
                        if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                        {
                            prvYieldCore( pxTCB->xTaskRunState );
                        }
                    }
                    #endif /* if ( configNUMBER_OF_CORES > 1 ) */

                    /* Return true to indicate that a context switch is required.
                     * This is only actually required in the corner case whereby
                     * multiple mutexes were held and the mutexes were given back
                     * in an order different to that in which they were taken.
                     * If a context switch did not occur when the first mutex was
                     * returned, even if a task was waiting on it, then a context
                     * switch should occur when the last mutex is returned whether
                     * a task is waiting on it or not. */
                    xReturn = pdTRUE;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTaskPriorityDisinherit( xReturn );

        return xReturn;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
                                              UBaseType_t uxHighestPriorityWaitingTask )
    {
        TCB_t * const pxTCB = pxMutexHolder;
        UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
        const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;

        traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask );

        if( pxMutexHolder != NULL )
        {
            /* If pxMutexHolder is not NULL then the holder must hold at least
             * one mutex. */
            configASSERT( pxTCB->uxMutexesHeld );

            /* Determine the priority to which the priority of the task that
             * holds the mutex should be set.  This will be the greater of the
             * holding task's base priority and the priority of the highest
             * priority task that is waiting to obtain the mutex. */
            if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
            {
                uxPriorityToUse = uxHighestPriorityWaitingTask;
            }
            else
            {
                uxPriorityToUse = pxTCB->uxBasePriority;
            }

            /* Does the priority need to change? */
            if( pxTCB->uxPriority != uxPriorityToUse )
            {
                /* Only disinherit if no other mutexes are held.  This is a
                 * simplification in the priority inheritance implementation.  If
                 * the task that holds the mutex is also holding other mutexes then
                 * the other mutexes may have caused the priority inheritance. */
                if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
                {
                    /* If a task has timed out because it already holds the
                     * mutex it was trying to obtain then it cannot of inherited
                     * its own priority. */
                    configASSERT( pxTCB != pxCurrentTCB );

                    /* Disinherit the priority, remembering the previous
                     * priority to facilitate determining the subject task's
                     * state. */
                    traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
                    uxPriorityUsedOnEntry = pxTCB->uxPriority;
                    pxTCB->uxPriority = uxPriorityToUse;

                    /* Only reset the event list item value if the value is not
                     * being used for anything else. */
                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) )
                    {
                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }

                    /* If the running task is not the task that holds the mutex
                     * then the task that holds the mutex could be in either the
                     * Ready, Blocked or Suspended states.  Only remove the task
                     * from its current state list if it is in the Ready state as
                     * the task's priority is going to change and there is one
                     * Ready list per priority. */
                    if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
                    {
                        if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
                        {
                            /* It is known that the task is in its ready list so
                             * there is no need to check again and the port level
                             * reset macro can be called directly. */
                            portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }

                        prvAddTaskToReadyList( pxTCB );
                        #if ( configNUMBER_OF_CORES > 1 )
                        {
                            /* The priority of the task is dropped. Yield the core on
                             * which the task is running. */
                            if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE )
                            {
                                prvYieldCore( pxTCB->xTaskRunState );
                            }
                        }
                        #endif /* if ( configNUMBER_OF_CORES > 1 ) */
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskPriorityDisinheritAfterTimeout();
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )

/* If not in a critical section then yield immediately.
 * Otherwise set xYieldPendings to true to wait to
 * yield until exiting the critical section.
 */
    void vTaskYieldWithinAPI( void )
    {
        traceENTER_vTaskYieldWithinAPI();

        if( portGET_CRITICAL_NESTING_COUNT() == 0U )
        {
            portYIELD();
        }
        else
        {
            xYieldPendings[ portGET_CORE_ID() ] = pdTRUE;
        }

        traceRETURN_vTaskYieldWithinAPI();
    }
#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

/*-----------------------------------------------------------*/

#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )

    void vTaskEnterCritical( void )
    {
        traceENTER_vTaskEnterCritical();

        portDISABLE_INTERRUPTS();

        if( xSchedulerRunning != pdFALSE )
        {
            ( pxCurrentTCB->uxCriticalNesting )++;

            /* This is not the interrupt safe version of the enter critical
             * function so  assert() if it is being called from an interrupt
             * context.  Only API functions that end in "FromISR" can be used in an
             * interrupt.  Only assert if the critical nesting count is 1 to
             * protect against recursive calls if the assert function also uses a
             * critical section. */
            if( pxCurrentTCB->uxCriticalNesting == 1U )
            {
                portASSERT_IF_IN_ISR();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskEnterCritical();
    }

#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )

    void vTaskEnterCritical( void )
    {
        traceENTER_vTaskEnterCritical();

        portDISABLE_INTERRUPTS();

        if( xSchedulerRunning != pdFALSE )
        {
            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
            {
                portGET_TASK_LOCK();
                portGET_ISR_LOCK();
            }

            portINCREMENT_CRITICAL_NESTING_COUNT();

            /* This is not the interrupt safe version of the enter critical
             * function so  assert() if it is being called from an interrupt
             * context.  Only API functions that end in "FromISR" can be used in an
             * interrupt.  Only assert if the critical nesting count is 1 to
             * protect against recursive calls if the assert function also uses a
             * critical section. */
            if( portGET_CRITICAL_NESTING_COUNT() == 1U )
            {
                portASSERT_IF_IN_ISR();

                if( uxSchedulerSuspended == 0U )
                {
                    /* The only time there would be a problem is if this is called
                     * before a context switch and vTaskExitCritical() is called
                     * after pxCurrentTCB changes. Therefore this should not be
                     * used within vTaskSwitchContext(). */
                    prvCheckForRunStateChange();
                }
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskEnterCritical();
    }

#endif /* #if ( configNUMBER_OF_CORES > 1 ) */

/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )

    UBaseType_t vTaskEnterCriticalFromISR( void )
    {
        UBaseType_t uxSavedInterruptStatus = 0;

        traceENTER_vTaskEnterCriticalFromISR();

        if( xSchedulerRunning != pdFALSE )
        {
            uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();

            if( portGET_CRITICAL_NESTING_COUNT() == 0U )
            {
                portGET_ISR_LOCK();
            }

            portINCREMENT_CRITICAL_NESTING_COUNT();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus );

        return uxSavedInterruptStatus;
    }

#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) )

    void vTaskExitCritical( void )
    {
        traceENTER_vTaskExitCritical();

        if( xSchedulerRunning != pdFALSE )
        {
            /* If pxCurrentTCB->uxCriticalNesting is zero then this function
             * does not match a previous call to vTaskEnterCritical(). */
            configASSERT( pxCurrentTCB->uxCriticalNesting > 0U );

            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
             * to exit critical section from ISR. */
            portASSERT_IF_IN_ISR();

            if( pxCurrentTCB->uxCriticalNesting > 0U )
            {
                ( pxCurrentTCB->uxCriticalNesting )--;

                if( pxCurrentTCB->uxCriticalNesting == 0U )
                {
                    portENABLE_INTERRUPTS();
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskExitCritical();
    }

#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )

    void vTaskExitCritical( void )
    {
        traceENTER_vTaskExitCritical();

        if( xSchedulerRunning != pdFALSE )
        {
            /* If critical nesting count is zero then this function
             * does not match a previous call to vTaskEnterCritical(). */
            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );

            /* This function should not be called in ISR. Use vTaskExitCriticalFromISR
             * to exit critical section from ISR. */
            portASSERT_IF_IN_ISR();

            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
            {
                portDECREMENT_CRITICAL_NESTING_COUNT();

                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
                {
                    BaseType_t xYieldCurrentTask;

                    /* Get the xYieldPending stats inside the critical section. */
                    xYieldCurrentTask = xYieldPendings[ portGET_CORE_ID() ];

                    portRELEASE_ISR_LOCK();
                    portRELEASE_TASK_LOCK();
                    portENABLE_INTERRUPTS();

                    /* When a task yields in a critical section it just sets
                     * xYieldPending to true. So now that we have exited the
                     * critical section check if xYieldPending is true, and
                     * if so yield. */
                    if( xYieldCurrentTask != pdFALSE )
                    {
                        portYIELD();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskExitCritical();
    }

#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

#if ( configNUMBER_OF_CORES > 1 )

    void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus )
    {
        traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus );

        if( xSchedulerRunning != pdFALSE )
        {
            /* If critical nesting count is zero then this function
             * does not match a previous call to vTaskEnterCritical(). */
            configASSERT( portGET_CRITICAL_NESTING_COUNT() > 0U );

            if( portGET_CRITICAL_NESTING_COUNT() > 0U )
            {
                portDECREMENT_CRITICAL_NESTING_COUNT();

                if( portGET_CRITICAL_NESTING_COUNT() == 0U )
                {
                    portRELEASE_ISR_LOCK();
                    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskExitCriticalFromISR();
    }

#endif /* #if ( configNUMBER_OF_CORES > 1 ) */
/*-----------------------------------------------------------*/

#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 )

    static char * prvWriteNameToBuffer( char * pcBuffer,
                                        const char * pcTaskName )
    {
        size_t x;

        /* Start by copying the entire string. */
        ( void ) strcpy( pcBuffer, pcTaskName );

        /* Pad the end of the string with spaces to ensure columns line up when
         * printed out. */
        for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ )
        {
            pcBuffer[ x ] = ' ';
        }

        /* Terminate. */
        pcBuffer[ x ] = ( char ) 0x00;

        /* Return the new end of string. */
        return &( pcBuffer[ x ] );
    }

#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
/*-----------------------------------------------------------*/

#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )

    void vTaskListTasks( char * pcWriteBuffer,
                         size_t uxBufferLength )
    {
        TaskStatus_t * pxTaskStatusArray;
        size_t uxConsumedBufferLength = 0;
        size_t uxCharsWrittenBySnprintf;
        int iSnprintfReturnValue;
        BaseType_t xOutputBufferFull = pdFALSE;
        UBaseType_t uxArraySize, x;
        char cStatus;

        traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength );

        /*
         * PLEASE NOTE:
         *
         * This function is provided for convenience only, and is used by many
         * of the demo applications.  Do not consider it to be part of the
         * scheduler.
         *
         * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the
         * uxTaskGetSystemState() output into a human readable table that
         * displays task: names, states, priority, stack usage and task number.
         * Stack usage specified as the number of unused StackType_t words stack can hold
         * on top of stack - not the number of bytes.
         *
         * vTaskListTasks() has a dependency on the snprintf() C library function that
         * might bloat the code size, use a lot of stack, and provide different
         * results on different platforms.  An alternative, tiny, third party,
         * and limited functionality implementation of snprintf() is provided in
         * many of the FreeRTOS/Demo sub-directories in a file called
         * printf-stdarg.c (note printf-stdarg.c does not provide a full
         * snprintf() implementation!).
         *
         * It is recommended that production systems call uxTaskGetSystemState()
         * directly to get access to raw stats data, rather than indirectly
         * through a call to vTaskListTasks().
         */


        /* Make sure the write buffer does not contain a string. */
        *pcWriteBuffer = ( char ) 0x00;

        /* Take a snapshot of the number of tasks in case it changes while this
         * function is executing. */
        uxArraySize = uxCurrentNumberOfTasks;

        /* Allocate an array index for each task.  NOTE!  if
         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
         * equate to NULL. */
        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );

        if( pxTaskStatusArray != NULL )
        {
            /* Generate the (binary) data. */
            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );

            /* Create a human readable table from the binary data. */
            for( x = 0; x < uxArraySize; x++ )
            {
                switch( pxTaskStatusArray[ x ].eCurrentState )
                {
                    case eRunning:
                        cStatus = tskRUNNING_CHAR;
                        break;

                    case eReady:
                        cStatus = tskREADY_CHAR;
                        break;

                    case eBlocked:
                        cStatus = tskBLOCKED_CHAR;
                        break;

                    case eSuspended:
                        cStatus = tskSUSPENDED_CHAR;
                        break;

                    case eDeleted:
                        cStatus = tskDELETED_CHAR;
                        break;

                    case eInvalid: /* Fall through. */
                    default:       /* Should not get here, but it is included
                                    * to prevent static checking errors. */
                        cStatus = ( char ) 0x00;
                        break;
                }

                /* Is there enough space in the buffer to hold task name? */
                if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
                {
                    /* Write the task name to the string, padding with spaces so it
                     * can be printed in tabular form more easily. */
                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
                    /* Do not count the terminating null character. */
                    uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );

                    /* Is there space left in the buffer? -1 is done because snprintf
                     * writes a terminating null character. So we are essentially
                     * checking if the buffer has space to write at least one non-null
                     * character. */
                    if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
                    {
                        /* Write the rest of the string. */
                        #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) )
                            /* MISRA Ref 21.6.1 [snprintf for utility] */
                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                            /* coverity[misra_c_2012_rule_21_6_violation] */
                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                             uxBufferLength - uxConsumedBufferLength,
                                                             "\t%c\t%u\t%u\t%u\t0x%x\r\n",
                                                             cStatus,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask );
                        #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
                            /* MISRA Ref 21.6.1 [snprintf for utility] */
                            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                            /* coverity[misra_c_2012_rule_21_6_violation] */
                            iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                             uxBufferLength - uxConsumedBufferLength,
                                                             "\t%c\t%u\t%u\t%u\r\n",
                                                             cStatus,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark,
                                                             ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
                        #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */
                        uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );

                        uxConsumedBufferLength += uxCharsWrittenBySnprintf;
                        pcWriteBuffer += uxCharsWrittenBySnprintf;
                    }
                    else
                    {
                        xOutputBufferFull = pdTRUE;
                    }
                }
                else
                {
                    xOutputBufferFull = pdTRUE;
                }

                if( xOutputBufferFull == pdTRUE )
                {
                    break;
                }
            }

            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
             * is 0 then vPortFree() will be #defined to nothing. */
            vPortFree( pxTaskStatusArray );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskListTasks();
    }

#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*----------------------------------------------------------*/

#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) )

    void vTaskGetRunTimeStatistics( char * pcWriteBuffer,
                                    size_t uxBufferLength )
    {
        TaskStatus_t * pxTaskStatusArray;
        size_t uxConsumedBufferLength = 0;
        size_t uxCharsWrittenBySnprintf;
        int iSnprintfReturnValue;
        BaseType_t xOutputBufferFull = pdFALSE;
        UBaseType_t uxArraySize, x;
        configRUN_TIME_COUNTER_TYPE ulTotalTime = 0;
        configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage;

        traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength );

        /*
         * PLEASE NOTE:
         *
         * This function is provided for convenience only, and is used by many
         * of the demo applications.  Do not consider it to be part of the
         * scheduler.
         *
         * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part
         * of the uxTaskGetSystemState() output into a human readable table that
         * displays the amount of time each task has spent in the Running state
         * in both absolute and percentage terms.
         *
         * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library
         * function that might bloat the code size, use a lot of stack, and
         * provide different results on different platforms.  An alternative,
         * tiny, third party, and limited functionality implementation of
         * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in
         * a file called printf-stdarg.c (note printf-stdarg.c does not provide
         * a full snprintf() implementation!).
         *
         * It is recommended that production systems call uxTaskGetSystemState()
         * directly to get access to raw stats data, rather than indirectly
         * through a call to vTaskGetRunTimeStatistics().
         */

        /* Make sure the write buffer does not contain a string. */
        *pcWriteBuffer = ( char ) 0x00;

        /* Take a snapshot of the number of tasks in case it changes while this
         * function is executing. */
        uxArraySize = uxCurrentNumberOfTasks;

        /* Allocate an array index for each task.  NOTE!  If
         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
         * equate to NULL. */
        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );

        if( pxTaskStatusArray != NULL )
        {
            /* Generate the (binary) data. */
            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );

            /* For percentage calculations. */
            ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100U );

            /* Avoid divide by zero errors. */
            if( ulTotalTime > 0U )
            {
                /* Create a human readable table from the binary data. */
                for( x = 0; x < uxArraySize; x++ )
                {
                    /* What percentage of the total run time has the task used?
                     * This will always be rounded down to the nearest integer.
                     * ulTotalRunTime has already been divided by 100. */
                    ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;

                    /* Is there enough space in the buffer to hold task name? */
                    if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength )
                    {
                        /* Write the task name to the string, padding with
                         * spaces so it can be printed in tabular form more
                         * easily. */
                        pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
                        /* Do not count the terminating null character. */
                        uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U );

                        /* Is there space left in the buffer? -1 is done because snprintf
                         * writes a terminating null character. So we are essentially
                         * checking if the buffer has space to write at least one non-null
                         * character. */
                        if( uxConsumedBufferLength < ( uxBufferLength - 1U ) )
                        {
                            if( ulStatsAsPercentage > 0U )
                            {
                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
                                {
                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                     uxBufferLength - uxConsumedBufferLength,
                                                                     "\t%lu\t\t%lu%%\r\n",
                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter,
                                                                     ulStatsAsPercentage );
                                }
                                #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                                {
                                    /* sizeof( int ) == sizeof( long ) so a smaller
                                     * printf() library can be used. */
                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                     uxBufferLength - uxConsumedBufferLength,
                                                                     "\t%u\t\t%u%%\r\n",
                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter,
                                                                     ( unsigned int ) ulStatsAsPercentage );
                                }
                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                            }
                            else
                            {
                                /* If the percentage is zero here then the task has
                                 * consumed less than 1% of the total run time. */
                                #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
                                {
                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                     uxBufferLength - uxConsumedBufferLength,
                                                                     "\t%lu\t\t<1%%\r\n",
                                                                     pxTaskStatusArray[ x ].ulRunTimeCounter );
                                }
                                #else
                                {
                                    /* sizeof( int ) == sizeof( long ) so a smaller
                                     * printf() library can be used. */
                                    /* MISRA Ref 21.6.1 [snprintf for utility] */
                                    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */
                                    /* coverity[misra_c_2012_rule_21_6_violation] */
                                    iSnprintfReturnValue = snprintf( pcWriteBuffer,
                                                                     uxBufferLength - uxConsumedBufferLength,
                                                                     "\t%u\t\t<1%%\r\n",
                                                                     ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
                                }
                                #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */
                            }

                            uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength );
                            uxConsumedBufferLength += uxCharsWrittenBySnprintf;
                            pcWriteBuffer += uxCharsWrittenBySnprintf;
                        }
                        else
                        {
                            xOutputBufferFull = pdTRUE;
                        }
                    }
                    else
                    {
                        xOutputBufferFull = pdTRUE;
                    }

                    if( xOutputBufferFull == pdTRUE )
                    {
                        break;
                    }
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
             * is 0 then vPortFree() will be #defined to nothing. */
            vPortFree( pxTaskStatusArray );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_vTaskGetRunTimeStatistics();
    }

#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
/*-----------------------------------------------------------*/

TickType_t uxTaskResetEventItemValue( void )
{
    TickType_t uxReturn;

    traceENTER_uxTaskResetEventItemValue();

    uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );

    /* Reset the event list item to its normal value - so it can be used with
     * queues and semaphores. */
    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) );

    traceRETURN_uxTaskResetEventItemValue( uxReturn );

    return uxReturn;
}
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

    TaskHandle_t pvTaskIncrementMutexHeldCount( void )
    {
        TCB_t * pxTCB;

        traceENTER_pvTaskIncrementMutexHeldCount();

        pxTCB = pxCurrentTCB;

        /* If xSemaphoreCreateMutex() is called before any tasks have been created
         * then pxCurrentTCB will be NULL. */
        if( pxTCB != NULL )
        {
            ( pxTCB->uxMutexesHeld )++;
        }

        traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB );

        return pxTCB;
    }

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                      BaseType_t xClearCountOnExit,
                                      TickType_t xTicksToWait )
    {
        uint32_t ulReturn;
        BaseType_t xAlreadyYielded, xShouldBlock = pdFALSE;

        traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );

        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
         * non-deterministic operation. */
        vTaskSuspendAll();
        {
            /* We MUST enter a critical section to atomically check if a notification
             * has occurred and set the flag to indicate that we are waiting for
             * a notification. If we do not do so, a notification sent from an ISR
             * will get lost. */
            taskENTER_CRITICAL();
            {
                /* Only block if the notification count is not already non-zero. */
                if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U )
                {
                    /* Mark this task as waiting for a notification. */
                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;

                    if( xTicksToWait > ( TickType_t ) 0 )
                    {
                        xShouldBlock = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            taskEXIT_CRITICAL();

            /* We are now out of the critical section but the scheduler is still
             * suspended, so we are safe to do non-deterministic operations such
             * as prvAddCurrentTaskToDelayedList. */
            if( xShouldBlock == pdTRUE )
            {
                traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn );
                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        xAlreadyYielded = xTaskResumeAll();

        /* Force a reschedule if xTaskResumeAll has not already done so. */
        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
        {
            taskYIELD_WITHIN_API();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        taskENTER_CRITICAL();
        {
            traceTASK_NOTIFY_TAKE( uxIndexToWaitOn );
            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];

            if( ulReturn != 0U )
            {
                if( xClearCountOnExit != pdFALSE )
                {
                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0U;
                }
                else
                {
                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1;
                }
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }

            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
        }
        taskEXIT_CRITICAL();

        traceRETURN_ulTaskGenericNotifyTake( ulReturn );

        return ulReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                       uint32_t ulBitsToClearOnEntry,
                                       uint32_t ulBitsToClearOnExit,
                                       uint32_t * pulNotificationValue,
                                       TickType_t xTicksToWait )
    {
        BaseType_t xReturn, xAlreadyYielded, xShouldBlock = pdFALSE;

        traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );

        configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a
         * non-deterministic operation. */
        vTaskSuspendAll();
        {
            /* We MUST enter a critical section to atomically check and update the
             * task notification value. If we do not do so, a notification from
             * an ISR will get lost. */
            taskENTER_CRITICAL();
            {
                /* Only block if a notification is not already pending. */
                if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
                {
                    /* Clear bits in the task's notification value as bits may get
                     * set by the notifying task or interrupt. This can be used
                     * to clear the value to zero. */
                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry;

                    /* Mark this task as waiting for a notification. */
                    pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION;

                    if( xTicksToWait > ( TickType_t ) 0 )
                    {
                        xShouldBlock = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            taskEXIT_CRITICAL();

            /* We are now out of the critical section but the scheduler is still
             * suspended, so we are safe to do non-deterministic operations such
             * as prvAddCurrentTaskToDelayedList. */
            if( xShouldBlock == pdTRUE )
            {
                traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn );
                prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        xAlreadyYielded = xTaskResumeAll();

        /* Force a reschedule if xTaskResumeAll has not already done so. */
        if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) )
        {
            taskYIELD_WITHIN_API();
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        taskENTER_CRITICAL();
        {
            traceTASK_NOTIFY_WAIT( uxIndexToWaitOn );

            if( pulNotificationValue != NULL )
            {
                /* Output the current notification value, which may or may not
                 * have changed. */
                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ];
            }

            /* If ucNotifyValue is set then either the task never entered the
             * blocked state (because a notification was already pending) or the
             * task unblocked because of a notification.  Otherwise the task
             * unblocked because of a timeout. */
            if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED )
            {
                /* A notification was not received. */
                xReturn = pdFALSE;
            }
            else
            {
                /* A notification was already pending or a notification was
                 * received while the task was waiting. */
                pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit;
                xReturn = pdTRUE;
            }

            pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION;
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTaskGenericNotifyWait( xReturn );

        return xReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
                                   UBaseType_t uxIndexToNotify,
                                   uint32_t ulValue,
                                   eNotifyAction eAction,
                                   uint32_t * pulPreviousNotificationValue )
    {
        TCB_t * pxTCB;
        BaseType_t xReturn = pdPASS;
        uint8_t ucOriginalNotifyState;

        traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );

        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
        configASSERT( xTaskToNotify );
        pxTCB = xTaskToNotify;

        taskENTER_CRITICAL();
        {
            if( pulPreviousNotificationValue != NULL )
            {
                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
            }

            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];

            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;

            switch( eAction )
            {
                case eSetBits:
                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
                    break;

                case eIncrement:
                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
                    break;

                case eSetValueWithOverwrite:
                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
                    break;

                case eSetValueWithoutOverwrite:

                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
                    {
                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
                    }
                    else
                    {
                        /* The value could not be written to the task. */
                        xReturn = pdFAIL;
                    }

                    break;

                case eNoAction:

                    /* The task is being notified without its notify value being
                     * updated. */
                    break;

                default:

                    /* Should not get here if all enums are handled.
                     * Artificially force an assert by testing a value the
                     * compiler can't assume is const. */
                    configASSERT( xTickCount == ( TickType_t ) 0 );

                    break;
            }

            traceTASK_NOTIFY( uxIndexToNotify );

            /* If the task is in the blocked state specifically to wait for a
             * notification then unblock it now. */
            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
            {
                listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                prvAddTaskToReadyList( pxTCB );

                /* The task should not have been on an event list. */
                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );

                #if ( configUSE_TICKLESS_IDLE != 0 )
                {
                    /* If a task is blocked waiting for a notification then
                     * xNextTaskUnblockTime might be set to the blocked task's time
                     * out time.  If the task is unblocked for a reason other than
                     * a timeout xNextTaskUnblockTime is normally left unchanged,
                     * because it will automatically get reset to a new value when
                     * the tick count equals xNextTaskUnblockTime.  However if
                     * tickless idling is used it might be more important to enter
                     * sleep mode at the earliest possible time - so reset
                     * xNextTaskUnblockTime here to ensure it is updated at the
                     * earliest possible time. */
                    prvResetNextTaskUnblockTime();
                }
                #endif

                /* Check if the notified task has a priority above the currently
                 * executing task. */
                taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB );
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTaskGenericNotify( xReturn );

        return xReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
                                          UBaseType_t uxIndexToNotify,
                                          uint32_t ulValue,
                                          eNotifyAction eAction,
                                          uint32_t * pulPreviousNotificationValue,
                                          BaseType_t * pxHigherPriorityTaskWoken )
    {
        TCB_t * pxTCB;
        uint8_t ucOriginalNotifyState;
        BaseType_t xReturn = pdPASS;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken );

        configASSERT( xTaskToNotify );
        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* RTOS ports that support interrupt nesting have the concept of a
         * maximum  system call (or maximum API call) interrupt priority.
         * Interrupts that are  above the maximum system call priority are keep
         * permanently enabled, even when the RTOS kernel is in a critical section,
         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
         * is defined in FreeRTOSConfig.h then
         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
         * failure if a FreeRTOS API function is called from an interrupt that has
         * been assigned a priority above the configured maximum system call
         * priority.  Only FreeRTOS functions that end in FromISR can be called
         * from interrupts  that have been assigned a priority at or (logically)
         * below the maximum system call interrupt priority.  FreeRTOS maintains a
         * separate interrupt safe API to ensure interrupt entry is as fast and as
         * simple as possible.  More information (albeit Cortex-M specific) is
         * provided on the following link:
         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

        pxTCB = xTaskToNotify;

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
        {
            if( pulPreviousNotificationValue != NULL )
            {
                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
            }

            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;

            switch( eAction )
            {
                case eSetBits:
                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
                    break;

                case eIncrement:
                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
                    break;

                case eSetValueWithOverwrite:
                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
                    break;

                case eSetValueWithoutOverwrite:

                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
                    {
                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
                    }
                    else
                    {
                        /* The value could not be written to the task. */
                        xReturn = pdFAIL;
                    }

                    break;

                case eNoAction:

                    /* The task is being notified without its notify value being
                     * updated. */
                    break;

                default:

                    /* Should not get here if all enums are handled.
                     * Artificially force an assert by testing a value the
                     * compiler can't assume is const. */
                    configASSERT( xTickCount == ( TickType_t ) 0 );
                    break;
            }

            traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );

            /* If the task is in the blocked state specifically to wait for a
             * notification then unblock it now. */
            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
            {
                /* The task should not have been on an event list. */
                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );

                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
                {
                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                    prvAddTaskToReadyList( pxTCB );
                }
                else
                {
                    /* The delayed and ready lists cannot be accessed, so hold
                     * this task pending until the scheduler is resumed. */
                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                }

                #if ( configNUMBER_OF_CORES == 1 )
                {
                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                    {
                        /* The notified task has a priority above the currently
                         * executing task so a yield is required. */
                        if( pxHigherPriorityTaskWoken != NULL )
                        {
                            *pxHigherPriorityTaskWoken = pdTRUE;
                        }

                        /* Mark that a yield is pending in case the user is not
                         * using the "xHigherPriorityTaskWoken" parameter to an ISR
                         * safe FreeRTOS function. */
                        xYieldPendings[ 0 ] = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                {
                    #if ( configUSE_PREEMPTION == 1 )
                    {
                        prvYieldForTask( pxTCB );

                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
                        {
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                        }
                    }
                    #endif /* if ( configUSE_PREEMPTION == 1 ) */
                }
                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
            }
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_xTaskGenericNotifyFromISR( xReturn );

        return xReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
                                        UBaseType_t uxIndexToNotify,
                                        BaseType_t * pxHigherPriorityTaskWoken )
    {
        TCB_t * pxTCB;
        uint8_t ucOriginalNotifyState;
        UBaseType_t uxSavedInterruptStatus;

        traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken );

        configASSERT( xTaskToNotify );
        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* RTOS ports that support interrupt nesting have the concept of a
         * maximum  system call (or maximum API call) interrupt priority.
         * Interrupts that are  above the maximum system call priority are keep
         * permanently enabled, even when the RTOS kernel is in a critical section,
         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
         * is defined in FreeRTOSConfig.h then
         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
         * failure if a FreeRTOS API function is called from an interrupt that has
         * been assigned a priority above the configured maximum system call
         * priority.  Only FreeRTOS functions that end in FromISR can be called
         * from interrupts  that have been assigned a priority at or (logically)
         * below the maximum system call interrupt priority.  FreeRTOS maintains a
         * separate interrupt safe API to ensure interrupt entry is as fast and as
         * simple as possible.  More information (albeit Cortex-M specific) is
         * provided on the following link:
         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();

        pxTCB = xTaskToNotify;

        /* MISRA Ref 4.7.1 [Return value shall be checked] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */
        /* coverity[misra_c_2012_directive_4_7_violation] */
        uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR();
        {
            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;

            /* 'Giving' is equivalent to incrementing a count in a counting
             * semaphore. */
            ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;

            traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );

            /* If the task is in the blocked state specifically to wait for a
             * notification then unblock it now. */
            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
            {
                /* The task should not have been on an event list. */
                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );

                if( uxSchedulerSuspended == ( UBaseType_t ) 0U )
                {
                    listREMOVE_ITEM( &( pxTCB->xStateListItem ) );
                    prvAddTaskToReadyList( pxTCB );
                }
                else
                {
                    /* The delayed and ready lists cannot be accessed, so hold
                     * this task pending until the scheduler is resumed. */
                    listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
                }

                #if ( configNUMBER_OF_CORES == 1 )
                {
                    if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
                    {
                        /* The notified task has a priority above the currently
                         * executing task so a yield is required. */
                        if( pxHigherPriorityTaskWoken != NULL )
                        {
                            *pxHigherPriorityTaskWoken = pdTRUE;
                        }

                        /* Mark that a yield is pending in case the user is not
                         * using the "xHigherPriorityTaskWoken" parameter in an ISR
                         * safe FreeRTOS function. */
                        xYieldPendings[ 0 ] = pdTRUE;
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #else /* #if ( configNUMBER_OF_CORES == 1 ) */
                {
                    #if ( configUSE_PREEMPTION == 1 )
                    {
                        prvYieldForTask( pxTCB );

                        if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE )
                        {
                            if( pxHigherPriorityTaskWoken != NULL )
                            {
                                *pxHigherPriorityTaskWoken = pdTRUE;
                            }
                        }
                    }
                    #endif /* #if ( configUSE_PREEMPTION == 1 ) */
                }
                #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
            }
        }
        taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus );

        traceRETURN_vTaskGenericNotifyGiveFromISR();
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
                                             UBaseType_t uxIndexToClear )
    {
        TCB_t * pxTCB;
        BaseType_t xReturn;

        traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear );

        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* If null is passed in here then it is the calling task that is having
         * its notification state cleared. */
        pxTCB = prvGetTCBFromHandle( xTask );

        taskENTER_CRITICAL();
        {
            if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED )
            {
                pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION;
                xReturn = pdPASS;
            }
            else
            {
                xReturn = pdFAIL;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTaskGenericNotifyStateClear( xReturn );

        return xReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configUSE_TASK_NOTIFICATIONS == 1 )

    uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
                                            UBaseType_t uxIndexToClear,
                                            uint32_t ulBitsToClear )
    {
        TCB_t * pxTCB;
        uint32_t ulReturn;

        traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );

        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );

        /* If null is passed in here then it is the calling task that is having
         * its notification state cleared. */
        pxTCB = prvGetTCBFromHandle( xTask );

        taskENTER_CRITICAL();
        {
            /* Return the notification as it was before the bits were cleared,
             * then clear the bit mask. */
            ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ];
            pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear;
        }
        taskEXIT_CRITICAL();

        traceRETURN_ulTaskGenericNotifyValueClear( ulReturn );

        return ulReturn;
    }

#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/

#if ( configGENERATE_RUN_TIME_STATS == 1 )

    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask )
    {
        TCB_t * pxTCB;

        traceENTER_ulTaskGetRunTimeCounter( xTask );

        pxTCB = prvGetTCBFromHandle( xTask );

        traceRETURN_ulTaskGetRunTimeCounter( pxTCB->ulRunTimeCounter );

        return pxTCB->ulRunTimeCounter;
    }

#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
/*-----------------------------------------------------------*/

#if ( configGENERATE_RUN_TIME_STATS == 1 )

    configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask )
    {
        TCB_t * pxTCB;
        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;

        traceENTER_ulTaskGetRunTimePercent( xTask );

        ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE();

        /* For percentage calculations. */
        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;

        /* Avoid divide by zero errors. */
        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
        {
            pxTCB = prvGetTCBFromHandle( xTask );
            ulReturn = pxTCB->ulRunTimeCounter / ulTotalTime;
        }
        else
        {
            ulReturn = 0;
        }

        traceRETURN_ulTaskGetRunTimePercent( ulReturn );

        return ulReturn;
    }

#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
/*-----------------------------------------------------------*/

#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )

    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void )
    {
        configRUN_TIME_COUNTER_TYPE ulReturn = 0;
        BaseType_t i;

        traceENTER_ulTaskGetIdleRunTimeCounter();

        for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
        {
            ulReturn += xIdleTaskHandles[ i ]->ulRunTimeCounter;
        }

        traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn );

        return ulReturn;
    }

#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
/*-----------------------------------------------------------*/

#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )

    configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void )
    {
        configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn;
        configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0;
        BaseType_t i;

        traceENTER_ulTaskGetIdleRunTimePercent();

        ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE() * configNUMBER_OF_CORES;

        /* For percentage calculations. */
        ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100;

        /* Avoid divide by zero errors. */
        if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 )
        {
            for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ )
            {
                ulRunTimeCounter += xIdleTaskHandles[ i ]->ulRunTimeCounter;
            }

            ulReturn = ulRunTimeCounter / ulTotalTime;
        }
        else
        {
            ulReturn = 0;
        }

        traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn );

        return ulReturn;
    }

#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
                                            const BaseType_t xCanBlockIndefinitely )
{
    TickType_t xTimeToWake;
    const TickType_t xConstTickCount = xTickCount;
    List_t * const pxDelayedList = pxDelayedTaskList;
    List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList;

    #if ( INCLUDE_xTaskAbortDelay == 1 )
    {
        /* About to enter a delayed list, so ensure the ucDelayAborted flag is
         * reset to pdFALSE so it can be detected as having been set to pdTRUE
         * when the task leaves the Blocked state. */
        pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE;
    }
    #endif

    /* Remove the task from the ready list before adding it to the blocked list
     * as the same list item is used for both lists. */
    if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
    {
        /* The current task must be in a ready list, so there is no need to
         * check, and the port reset macro can be called directly. */
        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
    }
    else
    {
        mtCOVERAGE_TEST_MARKER();
    }

    #if ( INCLUDE_vTaskSuspend == 1 )
    {
        if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
        {
            /* Add the task to the suspended task list instead of a delayed task
             * list to ensure it is not woken by a timing event.  It will block
             * indefinitely. */
            listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
        }
        else
        {
            /* Calculate the time at which the task should be woken if the event
             * does not occur.  This may overflow but this doesn't matter, the
             * kernel will manage it correctly. */
            xTimeToWake = xConstTickCount + xTicksToWait;

            /* The list item will be inserted in wake time order. */
            listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );

            if( xTimeToWake < xConstTickCount )
            {
                /* Wake time has overflowed.  Place this item in the overflow
                 * list. */
                traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
                vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
            }
            else
            {
                /* The wake time has not overflowed, so the current block list
                 * is used. */
                traceMOVED_TASK_TO_DELAYED_LIST();
                vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );

                /* If the task entering the blocked state was placed at the
                 * head of the list of blocked tasks then xNextTaskUnblockTime
                 * needs to be updated too. */
                if( xTimeToWake < xNextTaskUnblockTime )
                {
                    xNextTaskUnblockTime = xTimeToWake;
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
        }
    }
    #else /* INCLUDE_vTaskSuspend */
    {
        /* Calculate the time at which the task should be woken if the event
         * does not occur.  This may overflow but this doesn't matter, the kernel
         * will manage it correctly. */
        xTimeToWake = xConstTickCount + xTicksToWait;

        /* The list item will be inserted in wake time order. */
        listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );

        if( xTimeToWake < xConstTickCount )
        {
            traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST();
            /* Wake time has overflowed.  Place this item in the overflow list. */
            vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) );
        }
        else
        {
            traceMOVED_TASK_TO_DELAYED_LIST();
            /* The wake time has not overflowed, so the current block list is used. */
            vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) );

            /* If the task entering the blocked state was placed at the head of the
             * list of blocked tasks then xNextTaskUnblockTime needs to be updated
             * too. */
            if( xTimeToWake < xNextTaskUnblockTime )
            {
                xNextTaskUnblockTime = xTimeToWake;
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }

        /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
        ( void ) xCanBlockIndefinitely;
    }
    #endif /* INCLUDE_vTaskSuspend */
}
/*-----------------------------------------------------------*/

#if ( portUSING_MPU_WRAPPERS == 1 )

    xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask )
    {
        TCB_t * pxTCB;

        traceENTER_xTaskGetMPUSettings( xTask );

        pxTCB = prvGetTCBFromHandle( xTask );

        traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) );

        return &( pxTCB->xMPUSettings );
    }

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

/* Code below here allows additional code to be inserted into this source file,
 * especially where access to file scope functions and data is needed (for example
 * when performing module tests). */

#ifdef FREERTOS_MODULE_TEST
    #include "tasks_test_access_functions.h"
#endif


#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )

    #include "freertos_tasks_c_additions.h"

    #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
        static void freertos_tasks_c_additions_init( void )
        {
            FREERTOS_TASKS_C_ADDITIONS_INIT();
        }
    #endif

#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
/*-----------------------------------------------------------*/

#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )

/*
 * This is the kernel provided implementation of vApplicationGetIdleTaskMemory()
 * to provide the memory that is used by the Idle task. It is used when
 * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
 * it's own implementation of vApplicationGetIdleTaskMemory by setting
 * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
 */
    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                        StackType_t ** ppxIdleTaskStackBuffer,
                                        configSTACK_DEPTH_TYPE * puxIdleTaskStackSize )
    {
        static StaticTask_t xIdleTaskTCB;
        static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];

        *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB );
        *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] );
        *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
    }

    #if ( configNUMBER_OF_CORES > 1 )

        void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
                                                   StackType_t ** ppxIdleTaskStackBuffer,
                                                   configSTACK_DEPTH_TYPE * puxIdleTaskStackSize,
                                                   BaseType_t xPassiveIdleTaskIndex )
        {
            static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ];
            static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ];

            *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] );
            *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] );
            *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE;
        }

    #endif /* #if ( configNUMBER_OF_CORES > 1 ) */

#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
/*-----------------------------------------------------------*/

#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) )

/*
 * This is the kernel provided implementation of vApplicationGetTimerTaskMemory()
 * to provide the memory that is used by the Timer service task. It is used when
 * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide
 * it's own implementation of vApplicationGetTimerTaskMemory by setting
 * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined.
 */
    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
                                         StackType_t ** ppxTimerTaskStackBuffer,
                                         configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
    {
        static StaticTask_t xTimerTaskTCB;
        static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];

        *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB );
        *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] );
        *puxTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
    }

#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */
/*-----------------------------------------------------------*/

/*
 * Reset the state in this file. This state is normally initialized at start up.
 * This function must be called by the application before restarting the
 * scheduler.
 */
void vTaskResetState( void )
{
    BaseType_t xCoreID;

    /* Task control block. */
    #if ( configNUMBER_OF_CORES == 1 )
    {
        pxCurrentTCB = NULL;
    }
    #endif /* #if ( configNUMBER_OF_CORES == 1 ) */

    #if ( INCLUDE_vTaskDelete == 1 )
    {
        uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
    }
    #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */

    #if ( configUSE_POSIX_ERRNO == 1 )
    {
        FreeRTOS_errno = 0;
    }
    #endif /* #if ( configUSE_POSIX_ERRNO == 1 ) */

    /* Other file private variables. */
    uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
    xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
    uxTopReadyPriority = tskIDLE_PRIORITY;
    xSchedulerRunning = pdFALSE;
    xPendedTicks = ( TickType_t ) 0U;

    for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
    {
        xYieldPendings[ xCoreID ] = pdFALSE;
    }

    xNumOfOverflows = ( BaseType_t ) 0;
    uxTaskNumber = ( UBaseType_t ) 0U;
    xNextTaskUnblockTime = ( TickType_t ) 0U;

    uxSchedulerSuspended = ( UBaseType_t ) 0U;

    #if ( configGENERATE_RUN_TIME_STATS == 1 )
    {
        for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ )
        {
            ulTaskSwitchedInTime[ xCoreID ] = 0U;
            ulTotalRunTime[ xCoreID ] = 0U;
        }
    }
    #endif /* #if ( configGENERATE_RUN_TIME_STATS == 1 ) */
}
/*-----------------------------------------------------------*/


================================================
FILE: source/Middlewares/Third_Party/FreeRTOS/Source/timers.c
================================================
/*
 * FreeRTOS Kernel V11.1.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

/* Standard includes. */
#include 

/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
 * all the API functions to use the MPU wrappers.  That should only be done when
 * task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE

#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"

#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
    #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
#endif

/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
 * for the header files above, but not in this file, in order to generate the
 * correct privileged Vs unprivileged linkage and placement. */
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE


/* This entire source file will be skipped if the application is not configured
 * to include software timer functionality.  This #if is closed at the very bottom
 * of this file.  If you want to include software timer functionality then ensure
 * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
#if ( configUSE_TIMERS == 1 )

/* Misc definitions. */
    #define tmrNO_DELAY                    ( ( TickType_t ) 0U )
    #define tmrMAX_TIME_BEFORE_OVERFLOW    ( ( TickType_t ) -1 )

/* The name assigned to the timer service task. This can be overridden by
 * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
    #ifndef configTIMER_SERVICE_TASK_NAME
        #define configTIMER_SERVICE_TASK_NAME    "Tmr Svc"
    #endif

    #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )

/* The core affinity assigned to the timer service task on SMP systems.
 * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */
        #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY
            #define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
        #endif
    #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */

/* Bit definitions used in the ucStatus member of a timer structure. */
    #define tmrSTATUS_IS_ACTIVE                  ( 0x01U )
    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( 0x02U )
    #define tmrSTATUS_IS_AUTORELOAD              ( 0x04U )

/* The definition of the timers themselves. */
    typedef struct tmrTimerControl                                               /* The old naming convention is used to prevent breaking kernel aware debuggers. */
    {
        const char * pcTimerName;                                                /**< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */
        ListItem_t xTimerListItem;                                               /**< Standard linked list item as used by all kernel features for event management. */
        TickType_t xTimerPeriodInTicks;                                          /**< How quickly and often the timer expires. */
        void * pvTimerID;                                                        /**< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
        portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */
        #if ( configUSE_TRACE_FACILITY == 1 )
            UBaseType_t uxTimerNumber;                                           /**< An ID assigned by trace tools such as FreeRTOS+Trace */
        #endif
        uint8_t ucStatus;                                                        /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
    } xTIMER;

/* The old xTIMER name is maintained above then typedefed to the new Timer_t
 * name below to enable the use of older kernel aware debuggers. */
    typedef xTIMER Timer_t;

/* The definition of messages that can be sent and received on the timer queue.
 * Two types of message can be queued - messages that manipulate a software timer,
 * and messages that request the execution of a non-timer related callback.  The
 * two message types are defined in two separate structures, xTimerParametersType
 * and xCallbackParametersType respectively. */
    typedef struct tmrTimerParameters
    {
        TickType_t xMessageValue; /**< An optional value used by a subset of commands, for example, when changing the period of a timer. */
        Timer_t * pxTimer;        /**< The timer to which the command will be applied. */
    } TimerParameter_t;


    typedef struct tmrCallbackParameters
    {
        portTIMER_CALLBACK_ATTRIBUTE
        PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
        void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */
        uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */
    } CallbackParameters_t;

/* The structure that contains the two message types, along with an identifier
 * that is used to determine which message type is valid. */
    typedef struct tmrTimerQueueMessage
    {
        BaseType_t xMessageID; /**< The command being sent to the timer service task. */
        union
        {
            TimerParameter_t xTimerParameters;

            /* Don't include xCallbackParameters if it is not going to be used as
             * it makes the structure (and therefore the timer queue) larger. */
            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
                CallbackParameters_t xCallbackParameters;
            #endif /* INCLUDE_xTimerPendFunctionCall */
        } u;
    } DaemonTaskMessage_t;

/* The list in which active timers are stored.  Timers are referenced in expire
 * time order, with the nearest expiry time at the front of the list.  Only the
 * timer service task is allowed to access these lists.
 * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
 * breaks some kernel aware debuggers, and debuggers that reply on removing the
 * static qualifier. */
    PRIVILEGED_DATA static List_t xActiveTimerList1;
    PRIVILEGED_DATA static List_t xActiveTimerList2;
    PRIVILEGED_DATA static List_t * pxCurrentTimerList;
    PRIVILEGED_DATA static List_t * pxOverflowTimerList;

/* A queue that is used to send commands to the timer service task. */
    PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
    PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;

/*-----------------------------------------------------------*/

/*
 * Initialise the infrastructure used by the timer service task if it has not
 * been initialised already.
 */
    static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;

/*
 * The timer service task (daemon).  Timer functionality is controlled by this
 * task.  Other tasks communicate with the timer service task using the
 * xTimerQueue queue.
 */
    static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;

/*
 * Called by the timer service task to interpret and process a command it
 * received on the timer queue.
 */
    static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;

/*
 * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
 * depending on if the expire time causes a timer counter overflow.
 */
    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
                                                  const TickType_t xNextExpiryTime,
                                                  const TickType_t xTimeNow,
                                                  const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;

/*
 * Reload the specified auto-reload timer.  If the reloading is backlogged,
 * clear the backlog, calling the callback for each additional reload.  When
 * this function returns, the next expiry time is after xTimeNow.
 */
    static void prvReloadTimer( Timer_t * const pxTimer,
                                TickType_t xExpiredTime,
                                const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;

/*
 * An active timer has reached its expire time.  Reload the timer if it is an
 * auto-reload timer, then call its callback.
 */
    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
                                        const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;

/*
 * The tick count has overflowed.  Switch the timer lists after ensuring the
 * current timer list does not still reference some timers.
 */
    static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;

/*
 * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
 * if a tick count overflow occurred since prvSampleTimeNow() was last called.
 */
    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;

/*
 * If the timer list contains any active timers then return the expire time of
 * the timer that will expire first and set *pxListWasEmpty to false.  If the
 * timer list does not contain any timers then return 0 and set *pxListWasEmpty
 * to pdTRUE.
 */
    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;

/*
 * If a timer has expired, process it.  Otherwise, block the timer service task
 * until either a timer does expire or a command is received.
 */
    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
                                            BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;

/*
 * Called after a Timer_t structure has been allocated either statically or
 * dynamically to fill in the structure's members.
 */
    static void prvInitialiseNewTimer( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
                                       const BaseType_t xAutoReload,
                                       void * const pvTimerID,
                                       TimerCallbackFunction_t pxCallbackFunction,
                                       Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

    BaseType_t xTimerCreateTimerTask( void )
    {
        BaseType_t xReturn = pdFAIL;

        traceENTER_xTimerCreateTimerTask();

        /* This function is called when the scheduler is started if
         * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
         * timer service task has been created/initialised.  If timers have already
         * been created then the initialisation will already have been performed. */
        prvCheckForValidListAndQueue();

        if( xTimerQueue != NULL )
        {
            #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) )
            {
                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                {
                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
                    StackType_t * pxTimerTaskStackBuffer = NULL;
                    configSTACK_DEPTH_TYPE uxTimerTaskStackSize;

                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
                    xTimerTaskHandle = xTaskCreateStaticAffinitySet( prvTimerTask,
                                                                     configTIMER_SERVICE_TASK_NAME,
                                                                     uxTimerTaskStackSize,
                                                                     NULL,
                                                                     ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                                                     pxTimerTaskStackBuffer,
                                                                     pxTimerTaskTCBBuffer,
                                                                     configTIMER_SERVICE_TASK_CORE_AFFINITY );

                    if( xTimerTaskHandle != NULL )
                    {
                        xReturn = pdPASS;
                    }
                }
                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
                {
                    xReturn = xTaskCreateAffinitySet( prvTimerTask,
                                                      configTIMER_SERVICE_TASK_NAME,
                                                      configTIMER_TASK_STACK_DEPTH,
                                                      NULL,
                                                      ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                                      configTIMER_SERVICE_TASK_CORE_AFFINITY,
                                                      &xTimerTaskHandle );
                }
                #endif /* configSUPPORT_STATIC_ALLOCATION */
            }
            #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
            {
                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                {
                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
                    StackType_t * pxTimerTaskStackBuffer = NULL;
                    configSTACK_DEPTH_TYPE uxTimerTaskStackSize;

                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize );
                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
                                                          configTIMER_SERVICE_TASK_NAME,
                                                          uxTimerTaskStackSize,
                                                          NULL,
                                                          ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                                          pxTimerTaskStackBuffer,
                                                          pxTimerTaskTCBBuffer );

                    if( xTimerTaskHandle != NULL )
                    {
                        xReturn = pdPASS;
                    }
                }
                #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
                {
                    xReturn = xTaskCreate( prvTimerTask,
                                           configTIMER_SERVICE_TASK_NAME,
                                           configTIMER_TASK_STACK_DEPTH,
                                           NULL,
                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
                                           &xTimerTaskHandle );
                }
                #endif /* configSUPPORT_STATIC_ALLOCATION */
            }
            #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        configASSERT( xReturn );

        traceRETURN_xTimerCreateTimerTask( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )

        TimerHandle_t xTimerCreate( const char * const pcTimerName,
                                    const TickType_t xTimerPeriodInTicks,
                                    const BaseType_t xAutoReload,
                                    void * const pvTimerID,
                                    TimerCallbackFunction_t pxCallbackFunction )
        {
            Timer_t * pxNewTimer;

            traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction );

            /* MISRA Ref 11.5.1 [Malloc memory assignment] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
            /* coverity[misra_c_2012_rule_11_5_violation] */
            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );

            if( pxNewTimer != NULL )
            {
                /* Status is thus far zero as the timer is not created statically
                 * and has not been started.  The auto-reload bit may get set in
                 * prvInitialiseNewTimer. */
                pxNewTimer->ucStatus = 0x00;
                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
            }

            traceRETURN_xTimerCreate( pxNewTimer );

            return pxNewTimer;
        }

    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )

        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
                                          const TickType_t xTimerPeriodInTicks,
                                          const BaseType_t xAutoReload,
                                          void * const pvTimerID,
                                          TimerCallbackFunction_t pxCallbackFunction,
                                          StaticTimer_t * pxTimerBuffer )
        {
            Timer_t * pxNewTimer;

            traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );

            #if ( configASSERT_DEFINED == 1 )
            {
                /* Sanity check that the size of the structure used to declare a
                 * variable of type StaticTimer_t equals the size of the real timer
                 * structure. */
                volatile size_t xSize = sizeof( StaticTimer_t );
                configASSERT( xSize == sizeof( Timer_t ) );
                ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */
            }
            #endif /* configASSERT_DEFINED */

            /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
            configASSERT( pxTimerBuffer );
            /* MISRA Ref 11.3.1 [Misaligned access] */
            /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
            /* coverity[misra_c_2012_rule_11_3_violation] */
            pxNewTimer = ( Timer_t * ) pxTimerBuffer;

            if( pxNewTimer != NULL )
            {
                /* Timers can be created statically or dynamically so note this
                 * timer was created statically in case it is later deleted.  The
                 * auto-reload bit may get set in prvInitialiseNewTimer(). */
                pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED;

                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
            }

            traceRETURN_xTimerCreateStatic( pxNewTimer );

            return pxNewTimer;
        }

    #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

    static void prvInitialiseNewTimer( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
                                       const BaseType_t xAutoReload,
                                       void * const pvTimerID,
                                       TimerCallbackFunction_t pxCallbackFunction,
                                       Timer_t * pxNewTimer )
    {
        /* 0 is not a valid value for xTimerPeriodInTicks. */
        configASSERT( ( xTimerPeriodInTicks > 0 ) );

        /* Ensure the infrastructure used by the timer service task has been
         * created/initialised. */
        prvCheckForValidListAndQueue();

        /* Initialise the timer structure members using the function
         * parameters. */
        pxNewTimer->pcTimerName = pcTimerName;
        pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
        pxNewTimer->pvTimerID = pvTimerID;
        pxNewTimer->pxCallbackFunction = pxCallbackFunction;
        vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );

        if( xAutoReload != pdFALSE )
        {
            pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
        }

        traceTIMER_CREATE( pxNewTimer );
    }
/*-----------------------------------------------------------*/

    BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
                                             const BaseType_t xCommandID,
                                             const TickType_t xOptionalValue,
                                             BaseType_t * const pxHigherPriorityTaskWoken,
                                             const TickType_t xTicksToWait )
    {
        BaseType_t xReturn = pdFAIL;
        DaemonTaskMessage_t xMessage;

        ( void ) pxHigherPriorityTaskWoken;

        traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );

        configASSERT( xTimer );

        /* Send a message to the timer service task to perform a particular action
         * on a particular timer definition. */
        if( xTimerQueue != NULL )
        {
            /* Send a command to the timer service task to start the xTimer timer. */
            xMessage.xMessageID = xCommandID;
            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
            xMessage.u.xTimerParameters.pxTimer = xTimer;

            configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND );

            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
            {
                if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
                {
                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
                }
                else
                {
                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
                }
            }

            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTimerGenericCommandFromTask( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
                                            const BaseType_t xCommandID,
                                            const TickType_t xOptionalValue,
                                            BaseType_t * const pxHigherPriorityTaskWoken,
                                            const TickType_t xTicksToWait )
    {
        BaseType_t xReturn = pdFAIL;
        DaemonTaskMessage_t xMessage;

        ( void ) xTicksToWait;

        traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );

        configASSERT( xTimer );

        /* Send a message to the timer service task to perform a particular action
         * on a particular timer definition. */
        if( xTimerQueue != NULL )
        {
            /* Send a command to the timer service task to start the xTimer timer. */
            xMessage.xMessageID = xCommandID;
            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
            xMessage.u.xTimerParameters.pxTimer = xTimer;

            configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND );

            if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND )
            {
                xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
            }

            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
        }
        else
        {
            mtCOVERAGE_TEST_MARKER();
        }

        traceRETURN_xTimerGenericCommandFromISR( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
    {
        traceENTER_xTimerGetTimerDaemonTaskHandle();

        /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
         * started, then xTimerTaskHandle will be NULL. */
        configASSERT( ( xTimerTaskHandle != NULL ) );

        traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle );

        return xTimerTaskHandle;
    }
/*-----------------------------------------------------------*/

    TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
    {
        Timer_t * pxTimer = xTimer;

        traceENTER_xTimerGetPeriod( xTimer );

        configASSERT( xTimer );

        traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks );

        return pxTimer->xTimerPeriodInTicks;
    }
/*-----------------------------------------------------------*/

    void vTimerSetReloadMode( TimerHandle_t xTimer,
                              const BaseType_t xAutoReload )
    {
        Timer_t * pxTimer = xTimer;

        traceENTER_vTimerSetReloadMode( xTimer, xAutoReload );

        configASSERT( xTimer );
        taskENTER_CRITICAL();
        {
            if( xAutoReload != pdFALSE )
            {
                pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD;
            }
            else
            {
                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD );
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTimerSetReloadMode();
    }
/*-----------------------------------------------------------*/

    BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer )
    {
        Timer_t * pxTimer = xTimer;
        BaseType_t xReturn;

        traceENTER_xTimerGetReloadMode( xTimer );

        configASSERT( xTimer );
        taskENTER_CRITICAL();
        {
            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U )
            {
                /* Not an auto-reload timer. */
                xReturn = pdFALSE;
            }
            else
            {
                /* Is an auto-reload timer. */
                xReturn = pdTRUE;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTimerGetReloadMode( xReturn );

        return xReturn;
    }

    UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
    {
        UBaseType_t uxReturn;

        traceENTER_uxTimerGetReloadMode( xTimer );

        uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer );

        traceRETURN_uxTimerGetReloadMode( uxReturn );

        return uxReturn;
    }
/*-----------------------------------------------------------*/

    TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
    {
        Timer_t * pxTimer = xTimer;
        TickType_t xReturn;

        traceENTER_xTimerGetExpiryTime( xTimer );

        configASSERT( xTimer );
        xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );

        traceRETURN_xTimerGetExpiryTime( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
        BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer,
                                          StaticTimer_t ** ppxTimerBuffer )
        {
            BaseType_t xReturn;
            Timer_t * pxTimer = xTimer;

            traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer );

            configASSERT( ppxTimerBuffer != NULL );

            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U )
            {
                /* MISRA Ref 11.3.1 [Misaligned access] */
                /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */
                /* coverity[misra_c_2012_rule_11_3_violation] */
                *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer;
                xReturn = pdTRUE;
            }
            else
            {
                xReturn = pdFALSE;
            }

            traceRETURN_xTimerGetStaticBuffer( xReturn );

            return xReturn;
        }
    #endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

    const char * pcTimerGetName( TimerHandle_t xTimer )
    {
        Timer_t * pxTimer = xTimer;

        traceENTER_pcTimerGetName( xTimer );

        configASSERT( xTimer );

        traceRETURN_pcTimerGetName( pxTimer->pcTimerName );

        return pxTimer->pcTimerName;
    }
/*-----------------------------------------------------------*/

    static void prvReloadTimer( Timer_t * const pxTimer,
                                TickType_t xExpiredTime,
                                const TickType_t xTimeNow )
    {
        /* Insert the timer into the appropriate list for the next expiry time.
         * If the next expiry time has already passed, advance the expiry time,
         * call the callback function, and try again. */
        while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE )
        {
            /* Advance the expiry time. */
            xExpiredTime += pxTimer->xTimerPeriodInTicks;

            /* Call the timer callback. */
            traceTIMER_EXPIRED( pxTimer );
            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
        }
    }
/*-----------------------------------------------------------*/

    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
                                        const TickType_t xTimeNow )
    {
        /* MISRA Ref 11.5.3 [Void pointer assignment] */
        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
        /* coverity[misra_c_2012_rule_11_5_violation] */
        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );

        /* Remove the timer from the list of active timers.  A check has already
         * been performed to ensure the list is not empty. */

        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );

        /* If the timer is an auto-reload timer then calculate the next
         * expiry time and re-insert the timer in the list of active timers. */
        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
        {
            prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow );
        }
        else
        {
            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
        }

        /* Call the timer callback. */
        traceTIMER_EXPIRED( pxTimer );
        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
    }
/*-----------------------------------------------------------*/

    static portTASK_FUNCTION( prvTimerTask, pvParameters )
    {
        TickType_t xNextExpireTime;
        BaseType_t xListWasEmpty;

        /* Just to avoid compiler warnings. */
        ( void ) pvParameters;

        #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
        {
            /* Allow the application writer to execute some code in the context of
             * this task at the point the task starts executing.  This is useful if the
             * application includes initialisation code that would benefit from
             * executing after the scheduler has been started. */
            vApplicationDaemonTaskStartupHook();
        }
        #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */

        for( ; configCONTROL_INFINITE_LOOP(); )
        {
            /* Query the timers list to see if it contains any timers, and if so,
             * obtain the time at which the next timer will expire. */
            xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );

            /* If a timer has expired, process it.  Otherwise, block this task
             * until either a timer does expire, or a command is received. */
            prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );

            /* Empty the command queue. */
            prvProcessReceivedCommands();
        }
    }
/*-----------------------------------------------------------*/

    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
                                            BaseType_t xListWasEmpty )
    {
        TickType_t xTimeNow;
        BaseType_t xTimerListsWereSwitched;

        vTaskSuspendAll();
        {
            /* Obtain the time now to make an assessment as to whether the timer
             * has expired or not.  If obtaining the time causes the lists to switch
             * then don't process this timer as any timers that remained in the list
             * when the lists were switched will have been processed within the
             * prvSampleTimeNow() function. */
            xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );

            if( xTimerListsWereSwitched == pdFALSE )
            {
                /* The tick count has not overflowed, has the timer expired? */
                if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
                {
                    ( void ) xTaskResumeAll();
                    prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
                }
                else
                {
                    /* The tick count has not overflowed, and the next expire
                     * time has not been reached yet.  This task should therefore
                     * block to wait for the next expire time or a command to be
                     * received - whichever comes first.  The following line cannot
                     * be reached unless xNextExpireTime > xTimeNow, except in the
                     * case when the current timer list is empty. */
                    if( xListWasEmpty != pdFALSE )
                    {
                        /* The current timer list is empty - is the overflow list
                         * also empty? */
                        xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
                    }

                    vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );

                    if( xTaskResumeAll() == pdFALSE )
                    {
                        /* Yield to wait for either a command to arrive, or the
                         * block time to expire.  If a command arrived between the
                         * critical section being exited and this yield then the yield
                         * will not cause the task to block. */
                        taskYIELD_WITHIN_API();
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
            }
            else
            {
                ( void ) xTaskResumeAll();
            }
        }
    }
/*-----------------------------------------------------------*/

    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
    {
        TickType_t xNextExpireTime;

        /* Timers are listed in expiry time order, with the head of the list
         * referencing the task that will expire first.  Obtain the time at which
         * the timer with the nearest expiry time will expire.  If there are no
         * active timers then just set the next expire time to 0.  That will cause
         * this task to unblock when the tick count overflows, at which point the
         * timer lists will be switched and the next expiry time can be
         * re-assessed.  */
        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );

        if( *pxListWasEmpty == pdFALSE )
        {
            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
        }
        else
        {
            /* Ensure the task unblocks when the tick count rolls over. */
            xNextExpireTime = ( TickType_t ) 0U;
        }

        return xNextExpireTime;
    }
/*-----------------------------------------------------------*/

    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
    {
        TickType_t xTimeNow;
        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U;

        xTimeNow = xTaskGetTickCount();

        if( xTimeNow < xLastTime )
        {
            prvSwitchTimerLists();
            *pxTimerListsWereSwitched = pdTRUE;
        }
        else
        {
            *pxTimerListsWereSwitched = pdFALSE;
        }

        xLastTime = xTimeNow;

        return xTimeNow;
    }
/*-----------------------------------------------------------*/

    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
                                                  const TickType_t xNextExpiryTime,
                                                  const TickType_t xTimeNow,
                                                  const TickType_t xCommandTime )
    {
        BaseType_t xProcessTimerNow = pdFALSE;

        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );

        if( xNextExpiryTime <= xTimeNow )
        {
            /* Has the expiry time elapsed between the command to start/reset a
             * timer was issued, and the time the command was processed? */
            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )
            {
                /* The time between a command being issued and the command being
                 * processed actually exceeds the timers period.  */
                xProcessTimerNow = pdTRUE;
            }
            else
            {
                vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
            }
        }
        else
        {
            if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
            {
                /* If, since the command was issued, the tick count has overflowed
                 * but the expiry time has not, then the timer must have already passed
                 * its expiry time and should be processed immediately. */
                xProcessTimerNow = pdTRUE;
            }
            else
            {
                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
            }
        }

        return xProcessTimerNow;
    }
/*-----------------------------------------------------------*/

    static void prvProcessReceivedCommands( void )
    {
        DaemonTaskMessage_t xMessage = { 0 };
        Timer_t * pxTimer;
        BaseType_t xTimerListsWereSwitched;
        TickType_t xTimeNow;

        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )
        {
            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
            {
                /* Negative commands are pended function calls rather than timer
                 * commands. */
                if( xMessage.xMessageID < ( BaseType_t ) 0 )
                {
                    const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );

                    /* The timer uses the xCallbackParameters member to request a
                     * callback be executed.  Check the callback is not NULL. */
                    configASSERT( pxCallback );

                    /* Call the function. */
                    pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }
            }
            #endif /* INCLUDE_xTimerPendFunctionCall */

            /* Commands that are positive are timer commands rather than pended
             * function calls. */
            if( xMessage.xMessageID >= ( BaseType_t ) 0 )
            {
                /* The messages uses the xTimerParameters member to work on a
                 * software timer. */
                pxTimer = xMessage.u.xTimerParameters.pxTimer;

                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
                {
                    /* The timer is in a list, remove it. */
                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
                }
                else
                {
                    mtCOVERAGE_TEST_MARKER();
                }

                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );

                /* In this case the xTimerListsWereSwitched parameter is not used, but
                 *  it must be present in the function call.  prvSampleTimeNow() must be
                 *  called after the message is received from xTimerQueue so there is no
                 *  possibility of a higher priority task adding a message to the message
                 *  queue with a time that is ahead of the timer daemon task (because it
                 *  pre-empted the timer daemon task after the xTimeNow value was set). */
                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );

                switch( xMessage.xMessageID )
                {
                    case tmrCOMMAND_START:
                    case tmrCOMMAND_START_FROM_ISR:
                    case tmrCOMMAND_RESET:
                    case tmrCOMMAND_RESET_FROM_ISR:
                        /* Start or restart a timer. */
                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;

                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
                        {
                            /* The timer expired before it was added to the active
                             * timer list.  Process it now. */
                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U )
                            {
                                prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow );
                            }
                            else
                            {
                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
                            }

                            /* Call the timer callback. */
                            traceTIMER_EXPIRED( pxTimer );
                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
                        }
                        else
                        {
                            mtCOVERAGE_TEST_MARKER();
                        }

                        break;

                    case tmrCOMMAND_STOP:
                    case tmrCOMMAND_STOP_FROM_ISR:
                        /* The timer has already been removed from the active list. */
                        pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
                        break;

                    case tmrCOMMAND_CHANGE_PERIOD:
                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
                        pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE;
                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );

                        /* The new period does not really have a reference, and can
                         * be longer or shorter than the old one.  The command time is
                         * therefore set to the current time, and as the period cannot
                         * be zero the next expiry time can only be in the future,
                         * meaning (unlike for the xTimerStart() case above) there is
                         * no fail case that needs to be handled here. */
                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
                        break;

                    case tmrCOMMAND_DELETE:
                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
                        {
                            /* The timer has already been removed from the active list,
                             * just free up the memory if the memory was dynamically
                             * allocated. */
                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
                            {
                                vPortFree( pxTimer );
                            }
                            else
                            {
                                pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
                            }
                        }
                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
                        {
                            /* If dynamic allocation is not enabled, the memory
                             * could not have been dynamically allocated. So there is
                             * no need to free the memory - just mark the timer as
                             * "not active". */
                            pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE );
                        }
                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
                        break;

                    default:
                        /* Don't expect to get here. */
                        break;
                }
            }
        }
    }
/*-----------------------------------------------------------*/

    static void prvSwitchTimerLists( void )
    {
        TickType_t xNextExpireTime;
        List_t * pxTemp;

        /* The tick count has overflowed.  The timer lists must be switched.
         * If there are any timers still referenced from the current timer list
         * then they must have expired and should be processed before the lists
         * are switched. */
        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
        {
            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );

            /* Process the expired timer.  For auto-reload timers, be careful to
             * process only expirations that occur on the current list.  Further
             * expirations must wait until after the lists are switched. */
            prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW );
        }

        pxTemp = pxCurrentTimerList;
        pxCurrentTimerList = pxOverflowTimerList;
        pxOverflowTimerList = pxTemp;
    }
/*-----------------------------------------------------------*/

    static void prvCheckForValidListAndQueue( void )
    {
        /* Check that the list from which active timers are referenced, and the
         * queue used to communicate with the timer service, have been
         * initialised. */
        taskENTER_CRITICAL();
        {
            if( xTimerQueue == NULL )
            {
                vListInitialise( &xActiveTimerList1 );
                vListInitialise( &xActiveTimerList2 );
                pxCurrentTimerList = &xActiveTimerList1;
                pxOverflowTimerList = &xActiveTimerList2;

                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
                {
                    /* The timer queue is allocated statically in case
                     * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
                    PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;
                    PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];

                    xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
                }
                #else
                {
                    xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) );
                }
                #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */

                #if ( configQUEUE_REGISTRY_SIZE > 0 )
                {
                    if( xTimerQueue != NULL )
                    {
                        vQueueAddToRegistry( xTimerQueue, "TmrQ" );
                    }
                    else
                    {
                        mtCOVERAGE_TEST_MARKER();
                    }
                }
                #endif /* configQUEUE_REGISTRY_SIZE */
            }
            else
            {
                mtCOVERAGE_TEST_MARKER();
            }
        }
        taskEXIT_CRITICAL();
    }
/*-----------------------------------------------------------*/

    BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
    {
        BaseType_t xReturn;
        Timer_t * pxTimer = xTimer;

        traceENTER_xTimerIsTimerActive( xTimer );

        configASSERT( xTimer );

        /* Is the timer in the list of active timers? */
        taskENTER_CRITICAL();
        {
            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U )
            {
                xReturn = pdFALSE;
            }
            else
            {
                xReturn = pdTRUE;
            }
        }
        taskEXIT_CRITICAL();

        traceRETURN_xTimerIsTimerActive( xReturn );

        return xReturn;
    }
/*-----------------------------------------------------------*/

    void * pvTimerGetTimerID( const TimerHandle_t xTimer )
    {
        Timer_t * const pxTimer = xTimer;
        void * pvReturn;

        traceENTER_pvTimerGetTimerID( xTimer );

        configASSERT( xTimer );

        taskENTER_CRITICAL();
        {
            pvReturn = pxTimer->pvTimerID;
        }
        taskEXIT_CRITICAL();

        traceRETURN_pvTimerGetTimerID( pvReturn );

        return pvReturn;
    }
/*-----------------------------------------------------------*/

    void vTimerSetTimerID( TimerHandle_t xTimer,
                           void * pvNewID )
    {
        Timer_t * const pxTimer = xTimer;

        traceENTER_vTimerSetTimerID( xTimer, pvNewID );

        configASSERT( xTimer );

        taskENTER_CRITICAL();
        {
            pxTimer->pvTimerID = pvNewID;
        }
        taskEXIT_CRITICAL();

        traceRETURN_vTimerSetTimerID();
    }
/*-----------------------------------------------------------*/

    #if ( INCLUDE_xTimerPendFunctionCall == 1 )

        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
                                                  void * pvParameter1,
                                                  uint32_t ulParameter2,
                                                  BaseType_t * pxHigherPriorityTaskWoken )
        {
            DaemonTaskMessage_t xMessage;
            BaseType_t xReturn;

            traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken );

            /* Complete the message with the function parameters and post it to the
             * daemon task. */
            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;

            xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );

            tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
            traceRETURN_xTimerPendFunctionCallFromISR( xReturn );

            return xReturn;
        }

    #endif /* INCLUDE_xTimerPendFunctionCall */
/*-----------------------------------------------------------*/

    #if ( INCLUDE_xTimerPendFunctionCall == 1 )

        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
                                           void * pvParameter1,
                                           uint32_t ulParameter2,
                                           TickType_t xTicksToWait )
        {
            DaemonTaskMessage_t xMessage;
            BaseType_t xReturn;

            traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );

            /* This function can only be called after a timer has been created or
             * after the scheduler has been started because, until then, the timer
             * queue does not exist. */
            configASSERT( xTimerQueue );

            /* Complete the message with the function parameters and post it to the
             * daemon task. */
            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;

            xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );

            tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
            traceRETURN_xTimerPendFunctionCall( xReturn );

            return xReturn;
        }

    #endif /* INCLUDE_xTimerPendFunctionCall */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

        UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
        {
            traceENTER_uxTimerGetTimerNumber( xTimer );

            traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber );

            return ( ( Timer_t * ) xTimer )->uxTimerNumber;
        }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

    #if ( configUSE_TRACE_FACILITY == 1 )

        void vTimerSetTimerNumber( TimerHandle_t xTimer,
                                   UBaseType_t uxTimerNumber )
        {
            traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber );

            ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;

            traceRETURN_vTimerSetTimerNumber();
        }

    #endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/

/*
 * Reset the state in this file. This state is normally initialized at start up.
 * This function must be called by the application before restarting the
 * scheduler.
 */
    void vTimerResetState( void )
    {
        xTimerQueue = NULL;
        xTimerTaskHandle = NULL;
    }
/*-----------------------------------------------------------*/

/* This entire source file will be skipped if the application is not configured
 * to include software timer functionality.  If you want to include software timer
 * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
#endif /* configUSE_TIMERS == 1 */


================================================
FILE: source/build.sh
================================================
#!/usr/bin/env bash
set -e
TRANSLATION_DIR="../Translations"
#TRANSLATION_SCRIPT="make_translation.py"

# AVAILABLE_LANGUAGES will be calculating according to json files in $TRANSLATION_DIR
AVAILABLE_LANGUAGES=()
BUILD_LANGUAGES=()
AVAILABLE_MODELS=("TS100" "TS80" "TS80P" "Pinecil" "MHP30" "Pinecilv2" "S60" "S60P" "T55" "TS101")
BUILD_MODELS=()
OPTIONS=()

builder_info() {
    echo -e "
********************************************
               IronOS Firmware
        builder for Miniware + Pine64

                                    by Ralim
********************************************"
}

# Calculate available languages
for f in "$TRANSLATION_DIR"/translation_*.json; do
    AVAILABLE_LANGUAGES+=("$(echo "$f" | tr "[:lower:]" "[:upper:]" | sed "s/[^_]*_//" | sed "s/\.JSON//g")")
done

usage() {
    builder_info
    echo -e "
Usage : 
    $(basename "$0") [-l ] [-m ] [-o ] [-h]

Parameters :
    -l LANG_CODE : Force a specific language (${AVAILABLE_LANGUAGES[*]})
    -m MODEL     : Force a specific model (${AVAILABLE_MODELS[*]})
    -o key=val   : Pass options to make
    -h           : Show this help message

Example : 
    $(basename "$0") -l EN -m TS100                     (Build one language and model)
    $(basename "$0") -l EN -m \"TS100 MHP30\"             (Build one language and multi models)
    $(basename "$0") -l \"DE EN\" -m \"TS100 MHP30\"        (Build multi languages and models)
    $(basename "$0") -l EN -m Pinecilv2 -o ws2812b_enable=1

INFO : 
    By default, without parameters, the build is for all platforms and all languages

" 1>&2
    exit 1
}

StartBuild() {
    read -n 1 -r -s -p $'Press Enter to start the building process...\n'
}

checkLastCommand() {
    if [ $? -eq 0 ]; then
        echo "    [Success]"
        echo "********************************************"
    else
        forceExit "checkLastCommand"
    fi
}

forceExit() {
    if [ -n "$*" ]; then
        echo -e "\n\n    [Error]: $*"
    else
        echo "    [Error]"
    fi
    echo "********************************************"
    echo " -- Stop on error --"
    exit 1
}

isInArray() {
    local value="$1"   # Save first argument in a variable
    shift              # Shift all arguments to the left (original $1 gets lost)
    local array=("$@") # Rebuild the array with rest of arguments

    for item in "${array[@]}"; do
        [[ $value == "$item" ]] && return 0
    done
    return 1
}

declare -a margs=()
declare -a largs=()
declare -a oargs=()

while getopts "h:l:m:o:" option; do
    case "${option}" in
    h)
        usage
        ;;
    l)
        IFS=' ' read -r -a largs <<<"${OPTARG}"
        ;;
    m)
        IFS=' ' read -r -a margs <<<"${OPTARG}"
        ;;
    o)
        IFS=' ' read -r -a oargs <<< "${OPTARG}"
        ;;
    *)
        usage
        ;;
    esac
done
shift $((OPTIND - 1))
builder_info

# Checking requested language
echo -n "Available languages :"
echo " ${AVAILABLE_LANGUAGES[*]}"
echo -n "Requested languages : "
if ((${#largs[@]})); then
    for i in "${largs[@]}"; do
        i=$(echo "${i}" | tr '[:lower:]' '[:upper:]')
        if isInArray "$i" "${AVAILABLE_LANGUAGES[@]}"; then
            echo -n "$i "
            BUILD_LANGUAGES+=("$i")
        else
            forceExit "Language '$i' is unknown. Check and use only from the available languages."
        fi
    done
    echo ""
fi
if [ -z "${BUILD_LANGUAGES[*]}" ]; then
    echo "    No custom languages selected."
    echo "    Building: [ALL LANGUAGES]"
    BUILD_LANGUAGES+=("${AVAILABLE_LANGUAGES[@]}")
fi
echo "********************************************"

# Checking requested model
echo -n "Available models :"
echo " ${AVAILABLE_MODELS[*]}"
echo -n "Requested models : "
if ((${#margs[@]})); then
    for i in "${margs[@]}"; do

        if [[ "$i" != "Pinecil" ]] && [[ "$i" != "Pinecilv2" ]]; then # Dirty. Need to adapt the Build process to use upper cases only
            i=$(echo "${i}" | tr '[:lower:]' '[:upper:]')
        fi

        if isInArray "$i" "${AVAILABLE_MODELS[@]}"; then
            echo -n "$i "
            BUILD_MODELS+=("$i")
        else
            forceExit "Model '$i' is unknown. Check and use only from the available models."
        fi
    done
    echo ""
fi

if [ -z "${BUILD_MODELS[*]}" ]; then
    echo "    No custom models selected."
    echo "    Building: [ALL MODELS]"
    BUILD_MODELS+=("${AVAILABLE_MODELS[@]}")
fi

echo "********************************************"

echo -n "Requested options : "
if ((${#oargs[@]})); then
    for i in "${oargs[@]}"; do
        echo -n "$i "
        OPTIONS+=("$i")
    done
    echo ""
fi

echo "********************************************"
##
#StartBuild

if [ ${#BUILD_LANGUAGES[@]} -gt 0 ] && [ ${#BUILD_MODELS[@]} -gt 0 ]; then
    echo "Cleaning previous builds"
    rm -rf Hexfile/ >/dev/null
    rm -rf Objects/ >/dev/null
    make clean >/dev/null
    checkLastCommand

    for model in "${BUILD_MODELS[@]}"; do
        echo "Building firmware for $model in ${BUILD_LANGUAGES[*]}"
        make -j"$(nproc)" model="$model" "${BUILD_LANGUAGES[@]/#/firmware-}" "${OPTIONS[@]}" >/dev/null
        checkLastCommand
    done
else
    forceExit "Nothing to build. (no model or language specified)"
fi
echo " -- Firmwares successfully generated --"
echo "End..."


================================================
FILE: source/dfuse-pack.py
================================================
#!/usr/bin/env python3

# Written by Antonio Galea - 2010/11/18
# Distributed under Gnu LGPL 3.0
# see http://www.gnu.org/licenses/lgpl-3.0.txt

import sys, struct, zlib, os
import binascii
from optparse import OptionParser

try:
    from intelhex import IntelHex
except ImportError:
    IntelHex = None

DEFAULT_DEVICE = "0x0483:0xdf11"
DEFAULT_NAME = b"ST..."

# Prefix and Suffix sizes are derived from ST's DfuSe File Format Specification (UM0391), DFU revision 1.1a
PREFIX_SIZE = 11
SUFFIX_SIZE = 16


def named(tuple, names):
    return dict(list(zip(names.split(), tuple)))


def consume(fmt, data, names):
    n = struct.calcsize(fmt)
    return named(struct.unpack(fmt, data[:n]), names), data[n:]


def cstring(bytestring):
    return bytestring.partition(b"\0")[0]


def compute_crc(data):
    return 0xFFFFFFFF & -zlib.crc32(data) - 1


def parse(file, dump_images=False):
    print('File: "%s"' % file)
    data = open(file, "rb").read()
    crc = compute_crc(data[:-4])
    prefix, data = consume("<5sBIB", data, "signature version size targets")
    print(
        "%(signature)s v%(version)d, image size: %(size)d, targets: %(targets)d"
        % prefix
    )
    for t in range(prefix["targets"]):
        tprefix, data = consume(
            "<6sBI255s2I", data, "signature altsetting named name size elements"
        )
        tprefix["num"] = t
        if tprefix["named"]:
            tprefix["name"] = cstring(tprefix["name"])
        else:
            tprefix["name"] = ""
        print(
            '%(signature)s %(num)d, alt setting: %(altsetting)s, name: "%(name)s", size: %(size)d, elements: %(elements)d'
            % tprefix
        )
        tsize = tprefix["size"]
        target, data = data[:tsize], data[tsize:]
        for e in range(tprefix["elements"]):
            eprefix, target = consume("<2I", target, "address size")
            eprefix["num"] = e
            print("  %(num)d, address: 0x%(address)08x, size: %(size)d" % eprefix)
            esize = eprefix["size"]
            image, target = target[:esize], target[esize:]
            if dump_images:
                out = "%s.target%d.image%d.bin" % (file, t, e)
                open(out, "wb").write(image)
                print('    DUMPED IMAGE TO "%s"' % out)
        if len(target):
            print("target %d: PARSE ERROR" % t)
    suffix = named(
        struct.unpack("<4H3sBI", data[:SUFFIX_SIZE]),
        "device product vendor dfu ufd len crc",
    )
    print(
        "usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x"
        % suffix
    )
    if crc != suffix["crc"]:
        print("CRC ERROR: computed crc32 is 0x%08x" % crc)
    data = data[SUFFIX_SIZE:]
    if data:
        print("PARSE ERROR")


def checkbin(binfile):
    data = open(binfile, "rb").read()
    if len(data) < SUFFIX_SIZE:
        return
    crc = compute_crc(data[:-4])
    suffix = named(
        struct.unpack("<4H3sBI", data[-SUFFIX_SIZE:]),
        "device product vendor dfu ufd len crc",
    )
    if crc == suffix["crc"] and suffix["ufd"] == b"UFD":
        print(
            "usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x"
            % suffix
        )
        print("It looks like the file %s has a DFU suffix!" % binfile)
        print("Please remove any DFU suffix and retry.")
        sys.exit(1)


def build(file, targets, name=DEFAULT_NAME, device=DEFAULT_DEVICE):
    data = b""
    for t, target in enumerate(targets):
        tdata = b""
        for image in target:
            tdata += (
                struct.pack("<2I", image["address"], len(image["data"])) + image["data"]
            )
            ealt = image["alt"]
        tdata = (
            struct.pack(
                "<6sBI255s2I", b"Target", ealt, 1, name, len(tdata), len(target)
            )
            + tdata
        )
        data += tdata
    data = (
        struct.pack(
            "<5sBIB", b"DfuSe", 1, PREFIX_SIZE + len(data) + SUFFIX_SIZE, len(targets)
        )
        + data
    )
    v, d = [int(x, 0) & 0xFFFF for x in device.split(":", 1)]
    data += struct.pack("<4H3sB", 0, d, v, 0x011A, b"UFD", SUFFIX_SIZE)
    crc = compute_crc(data)
    data += struct.pack(" 3:
    print("Usage: metadata.py OUTPUT_FILE [model]")
    print(
        "  OUTPUT_FILE      - the name of output file in json format with meta info about binary files"
    )
    print(
        "  model [optional] - name of the model (as for `make model=NAME`) to scan files for explicitly (all files in source/Hexfile by default otherwise)"
    )
    exit(1)

# If model is provided explicitly to scan related files only for json output, then process the argument
ModelName = None
if len(sys.argv) == 3:
    ModelName = sys.argv[2]
    if ModelName.endswith("_multi-lang"):
        # rename on-the-fly for direct compatibility with make targets like PINECILMODEL_multi-lang
        ModelName = ModelName.rstrip("-lang")

HERE = Path(__file__).resolve().parent

HexFileFolder = os.path.join(HERE, "Hexfile")
OutputJSONPath = os.path.join(HexFileFolder, sys.argv[1])
TranslationsFilesPath = os.path.join(HERE.parent, "Translations")


def load_json(filename: str):
    with open(filename) as f:
        return json.loads(f.read())


def read_git_tag():
    if os.environ.get("GITHUB_CI_PR_SHA", "") != "":
        return os.environ["GITHUB_CI_PR_SHA"][:7].upper()
    else:
        return f"{subprocess.check_output(['git', 'rev-parse', '--short=7', 'HEAD']).strip().decode('ascii').upper()}"


def read_version():
    with open(HERE / "version.h") as version_file:
        for line in version_file:
            if re.findall(r"^.*(?<=(#define)).*(?<=(BUILD_VERSION))", line):
                matches = re.findall(r"\"(.+?)\"", line)
                if matches:
                    return matches[0]
    raise Exception("Could not parse version")


# Fetch our file listings
translation_files = [
    os.path.join(TranslationsFilesPath, f)
    for f in os.listdir(TranslationsFilesPath)
    if os.path.isfile(os.path.join(TranslationsFilesPath, f)) and f.endswith(".json")
]
output_files = [
    os.path.join(HexFileFolder, f)
    for f in sorted(os.listdir(HexFileFolder))
    if os.path.isfile(os.path.join(HexFileFolder, f))
]

parsed_languages = {}
for path in translation_files:
    lang: dict = load_json(path)
    code = lang.get("languageCode", None)
    if code is not None:
        parsed_languages[code] = lang

# Now that we have the languages, we can generate our index of info on each file

output_json = {"git_tag": read_git_tag(), "release": read_version(), "contents": {}}

device_model_name = None
for file_path in output_files:
    if file_path.endswith(".hex") or file_path.endswith(".dfu"):
        # Find out what language this file is
        name: str = os.path.basename(file_path)
        if ModelName is not None:
            # If ModelName is provided as the second argument (compatible with make model=NAME fully) but current file name doesn't match the model name, then skip it
            if not name.startswith(ModelName + "_"):
                continue
            # If build of interest is not multi-lang one but scanning one is not MODEL_LANG-ID here, then skip it to avoid mess in json between MODEL_LANG-ID & MODEL_multi'
            if not ModelName.endswith("_multi") and not re.match(
                r"^" + ModelName + "_" + "([A-Z]+).*$", name
            ):
                continue
        matches = re.findall(r"^([a-zA-Z0-9]+)_(.+)\.(.+)$", name)
        if matches:
            matches = matches[0]
            if len(matches) == 3:
                if device_model_name is None:
                    device_model_name = matches[0]
                lang_code: str = matches[1]
                lang_file = parsed_languages.get(lang_code, None)
                if lang_file is None and lang_code.startswith("multi_"):
                    # Multi files wont match, but we fake this by just taking the filename to it
                    lang_file = {
                        "languageLocalName": lang_code.replace("multi_", "").replace(
                            "compressed_", ""
                        )
                    }
                if lang_file is None:
                    raise Exception(f"Could not match language code {lang_code}")
                file_record = {
                    "language_code": lang_code,
                    "language_name": lang_file.get("languageLocalName", None),
                }
                output_json["contents"][name] = file_record
            else:
                print(f"failed to parse {matches}")

if device_model_name is None:
    raise Exception("No files parsed")

output_json["model"] = device_model_name
with open(OutputJSONPath, "w", encoding="utf8") as json_file:
    json.dump(output_json, json_file, ensure_ascii=False)


================================================
FILE: source/version.h
================================================
/**
 * Firmware build version - format: xx.yy+[.zzzzzzzz]
 *
 * x: major version
 * y: minor version
 * +: build type:
 * * R - git-related release tag vXX.YY
 * * T - git-related release tag but version is not vXX.YY !
 * * D - git-related dev branch
 * * B - git-related custom branch
 * * G - neither above but git-related
 * * H - build outside of a git tree (i.e. release tarball)
 * * S - something special (should not happen?)
 * * V - something very special (should not happen!)
 * z: short commit ID hash generated automaticaly from git
 * * (for git-related build types only)
 *
 * i.e.:
 * * BUILD_VERSION = 'v2.22' -> from tarball:            'v2.22H'
 * * BUILD_VERSION = 'v2.22' -> from git dev branch:     'v2.22D.1A2B3C4D'
 * * BUILD_VERSION = 'v2.22' -> from stable git release: 'v2.22R.5E6F7G8H'
 */

#define BUILD_VERSION "v2.23"